1 ;; Machine description for GNU compiler,
2 ;; for ATMEL AVR micro controllers.
3 ;; Copyright (C) 1998, 1999, 2000, 2001, 2002, 2004, 2005, 2006, 2007, 2008,
4 ;; 2009, 2010 Free Software Foundation, Inc.
5 ;; Contributed by Denis Chertykov (chertykov@gmail.com)
7 ;; This file is part of GCC.
9 ;; GCC is free software; you can redistribute it and/or modify
10 ;; it under the terms of the GNU General Public License as published by
11 ;; the Free Software Foundation; either version 3, or (at your option)
14 ;; GCC is distributed in the hope that it will be useful,
15 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
16 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 ;; GNU General Public License for more details.
19 ;; You should have received a copy of the GNU General Public License
20 ;; along with GCC; see the file COPYING3. If not see
21 ;; <http://www.gnu.org/licenses/>.
23 ;; Special characters after '%':
24 ;; A No effect (add 0).
25 ;; B Add 1 to REG number, MEM address or CONST_INT.
28 ;; j Branch condition.
29 ;; k Reverse branch condition.
30 ;;..m..Constant Direct Data memory address.
31 ;; o Displacement for (mem (plus (reg) (const_int))) operands.
32 ;; p POST_INC or PRE_DEC address as a pointer (X, Y, Z)
33 ;; r POST_INC or PRE_DEC address as a register (r26, r28, r30)
34 ;;..x..Constant Direct Program memory address.
35 ;; ~ Output 'r' if not AVR_HAVE_JMP_CALL.
36 ;; ! Output 'e' if AVR_HAVE_EIJMP_EICALL.
39 ;; 0 Length of a string, see "strlenhi".
40 ;; 1 Jump by register pair Z or by table addressed by Z, see "casesi".
48 (TMP_REGNO 0) ; temporary register r0
49 (ZERO_REGNO 1) ; zero register r1
59 (UNSPECV_PROLOGUE_SAVES 0)
60 (UNSPECV_EPILOGUE_RESTORES 1)
61 (UNSPECV_WRITE_SP_IRQ_ON 2)
62 (UNSPECV_WRITE_SP_IRQ_OFF 3)
63 (UNSPECV_GOTO_RECEIVER 4)])
65 (include "predicates.md")
66 (include "constraints.md")
68 ;; Condition code settings.
69 (define_attr "cc" "none,set_czn,set_zn,set_n,compare,clobber"
70 (const_string "none"))
72 (define_attr "type" "branch,branch1,arith,xcall"
73 (const_string "arith"))
75 (define_attr "mcu_have_movw" "yes,no"
76 (const (if_then_else (symbol_ref "AVR_HAVE_MOVW")
78 (const_string "no"))))
80 (define_attr "mcu_mega" "yes,no"
81 (const (if_then_else (symbol_ref "AVR_HAVE_JMP_CALL")
83 (const_string "no"))))
86 ;; The size of instructions in bytes.
87 ;; XXX may depend from "cc"
89 (define_attr "length" ""
90 (cond [(eq_attr "type" "branch")
91 (if_then_else (and (ge (minus (pc) (match_dup 0))
93 (le (minus (pc) (match_dup 0))
96 (if_then_else (and (ge (minus (pc) (match_dup 0))
98 (le (minus (pc) (match_dup 0))
102 (eq_attr "type" "branch1")
103 (if_then_else (and (ge (minus (pc) (match_dup 0))
105 (le (minus (pc) (match_dup 0))
108 (if_then_else (and (ge (minus (pc) (match_dup 0))
110 (le (minus (pc) (match_dup 0))
114 (eq_attr "type" "xcall")
115 (if_then_else (eq_attr "mcu_mega" "no")
120 ;; Define mode iterator
121 (define_mode_iterator QISI [(QI "") (HI "") (SI "")])
122 (define_mode_iterator QIDI [(QI "") (HI "") (SI "") (DI "")])
123 (define_mode_iterator HIDI [(HI "") (SI "") (DI "")])
124 (define_mode_iterator HISI [(HI "") (SI "")])
126 ;;========================================================================
127 ;; The following is used by nonlocal_goto and setjmp.
128 ;; The receiver pattern will create no instructions since internally
129 ;; virtual_stack_vars = hard_frame_pointer + 1 so the RTL become R28=R28
130 ;; This avoids creating add/sub offsets in frame_pointer save/resore.
131 ;; The 'null' receiver also avoids problems with optimisation
132 ;; not recognising incoming jmp and removing code that resets frame_pointer.
133 ;; The code derived from builtins.c.
135 (define_expand "nonlocal_goto_receiver"
137 (unspec_volatile:HI [(const_int 0)] UNSPECV_GOTO_RECEIVER))]
140 emit_move_insn (virtual_stack_vars_rtx,
141 gen_rtx_PLUS (Pmode, hard_frame_pointer_rtx,
142 gen_int_mode (STARTING_FRAME_OFFSET,
144 /* This might change the hard frame pointer in ways that aren't
145 apparent to early optimization passes, so force a clobber. */
146 emit_clobber (hard_frame_pointer_rtx);
151 ;; Defining nonlocal_goto_receiver means we must also define this.
152 ;; even though its function is identical to that in builtins.c
154 (define_expand "nonlocal_goto"
156 (use (match_operand 0 "general_operand"))
157 (use (match_operand 1 "general_operand"))
158 (use (match_operand 2 "general_operand"))
159 (use (match_operand 3 "general_operand"))
163 rtx r_label = copy_to_reg (operands[1]);
164 rtx r_fp = operands[3];
165 rtx r_sp = operands[2];
167 emit_clobber (gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (VOIDmode)));
169 emit_clobber (gen_rtx_MEM (BLKmode, hard_frame_pointer_rtx));
171 emit_move_insn (hard_frame_pointer_rtx, r_fp);
172 emit_stack_restore (SAVE_NONLOCAL, r_sp, NULL_RTX);
174 emit_use (hard_frame_pointer_rtx);
175 emit_use (stack_pointer_rtx);
177 emit_indirect_jump (r_label);
183 (define_insn "*pushqi"
184 [(set (mem:QI (post_dec (reg:HI REG_SP)))
185 (match_operand:QI 0 "reg_or_0_operand" "r,L"))]
190 [(set_attr "length" "1,1")])
193 (define_insn "*pushhi"
194 [(set (mem:HI (post_dec (reg:HI REG_SP)))
195 (match_operand:HI 0 "reg_or_0_operand" "r,L"))]
199 push __zero_reg__\;push __zero_reg__"
200 [(set_attr "length" "2,2")])
202 (define_insn "*pushsi"
203 [(set (mem:SI (post_dec (reg:HI REG_SP)))
204 (match_operand:SI 0 "reg_or_0_operand" "r,L"))]
207 push %D0\;push %C0\;push %B0\;push %A0
208 push __zero_reg__\;push __zero_reg__\;push __zero_reg__\;push __zero_reg__"
209 [(set_attr "length" "4,4")])
211 (define_insn "*pushsf"
212 [(set (mem:SF (post_dec (reg:HI REG_SP)))
213 (match_operand:SF 0 "register_operand" "r"))]
219 [(set_attr "length" "4")])
221 ;;========================================================================
223 ;; The last alternative (any immediate constant to any register) is
224 ;; very expensive. It should be optimized by peephole2 if a scratch
225 ;; register is available, but then that register could just as well be
226 ;; allocated for the variable we are loading. But, most of NO_LD_REGS
227 ;; are call-saved registers, and most of LD_REGS are call-used registers,
228 ;; so this may still be a win for registers live across function calls.
230 (define_expand "movqi"
231 [(set (match_operand:QI 0 "nonimmediate_operand" "")
232 (match_operand:QI 1 "general_operand" ""))]
234 "/* One of the ops has to be in a register. */
235 if (!register_operand(operand0, QImode)
236 && ! (register_operand(operand1, QImode) || const0_rtx == operand1))
237 operands[1] = copy_to_mode_reg(QImode, operand1);
240 (define_insn "*movqi"
241 [(set (match_operand:QI 0 "nonimmediate_operand" "=r,d,Qm,r,q,r,*r")
242 (match_operand:QI 1 "general_operand" "rL,i,rL,Qm,r,q,i"))]
243 "(register_operand (operands[0],QImode)
244 || register_operand (operands[1], QImode) || const0_rtx == operands[1])"
245 "* return output_movqi (insn, operands, NULL);"
246 [(set_attr "length" "1,1,5,5,1,1,4")
247 (set_attr "cc" "none,none,clobber,clobber,none,none,clobber")])
249 ;; This is used in peephole2 to optimize loading immediate constants
250 ;; if a scratch register from LD_REGS happens to be available.
252 (define_insn "*reload_inqi"
253 [(set (match_operand:QI 0 "register_operand" "=l")
254 (match_operand:QI 1 "immediate_operand" "i"))
255 (clobber (match_operand:QI 2 "register_operand" "=&d"))]
259 [(set_attr "length" "2")
260 (set_attr "cc" "none")])
263 [(match_scratch:QI 2 "d")
264 (set (match_operand:QI 0 "l_register_operand" "")
265 (match_operand:QI 1 "immediate_operand" ""))]
266 "(operands[1] != const0_rtx
267 && operands[1] != const1_rtx
268 && operands[1] != constm1_rtx)"
269 [(parallel [(set (match_dup 0) (match_dup 1))
270 (clobber (match_dup 2))])]
273 ;;============================================================================
274 ;; move word (16 bit)
276 (define_expand "movhi"
277 [(set (match_operand:HI 0 "nonimmediate_operand" "")
278 (match_operand:HI 1 "general_operand" ""))]
282 /* One of the ops has to be in a register. */
283 if (!register_operand(operand0, HImode)
284 && !(register_operand(operand1, HImode) || const0_rtx == operands[1]))
286 operands[1] = copy_to_mode_reg(HImode, operand1);
290 (define_insn "*movhi_sp"
291 [(set (match_operand:HI 0 "register_operand" "=q,r")
292 (match_operand:HI 1 "register_operand" "r,q"))]
293 "((stack_register_operand(operands[0], HImode) && register_operand (operands[1], HImode))
294 || (register_operand (operands[0], HImode) && stack_register_operand(operands[1], HImode)))"
295 "* return output_movhi (insn, operands, NULL);"
296 [(set_attr "length" "5,2")
297 (set_attr "cc" "none,none")])
299 (define_insn "movhi_sp_r_irq_off"
300 [(set (match_operand:HI 0 "stack_register_operand" "=q")
301 (unspec_volatile:HI [(match_operand:HI 1 "register_operand" "r")]
302 UNSPECV_WRITE_SP_IRQ_OFF))]
306 [(set_attr "length" "2")
307 (set_attr "cc" "none")])
309 (define_insn "movhi_sp_r_irq_on"
310 [(set (match_operand:HI 0 "stack_register_operand" "=q")
311 (unspec_volatile:HI [(match_operand:HI 1 "register_operand" "r")]
312 UNSPECV_WRITE_SP_IRQ_ON))]
318 [(set_attr "length" "4")
319 (set_attr "cc" "none")])
322 [(match_scratch:QI 2 "d")
323 (set (match_operand:HI 0 "l_register_operand" "")
324 (match_operand:HI 1 "immediate_operand" ""))]
325 "(operands[1] != const0_rtx
326 && operands[1] != constm1_rtx)"
327 [(parallel [(set (match_dup 0) (match_dup 1))
328 (clobber (match_dup 2))])]
331 ;; '*' because it is not used in rtl generation, only in above peephole
332 (define_insn "*reload_inhi"
333 [(set (match_operand:HI 0 "register_operand" "=r")
334 (match_operand:HI 1 "immediate_operand" "i"))
335 (clobber (match_operand:QI 2 "register_operand" "=&d"))]
337 "* return output_reload_inhi (insn, operands, NULL);"
338 [(set_attr "length" "4")
339 (set_attr "cc" "none")])
341 (define_insn "*movhi"
342 [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,m,d,*r,q,r")
343 (match_operand:HI 1 "general_operand" "rL,m,rL,i,i,r,q"))]
344 "(register_operand (operands[0],HImode)
345 || register_operand (operands[1],HImode) || const0_rtx == operands[1])"
346 "* return output_movhi (insn, operands, NULL);"
347 [(set_attr "length" "2,6,7,2,6,5,2")
348 (set_attr "cc" "none,clobber,clobber,none,clobber,none,none")])
350 (define_peephole2 ; movw
351 [(set (match_operand:QI 0 "even_register_operand" "")
352 (match_operand:QI 1 "even_register_operand" ""))
353 (set (match_operand:QI 2 "odd_register_operand" "")
354 (match_operand:QI 3 "odd_register_operand" ""))]
356 && REGNO (operands[0]) == REGNO (operands[2]) - 1
357 && REGNO (operands[1]) == REGNO (operands[3]) - 1)"
358 [(set (match_dup 4) (match_dup 5))]
360 operands[4] = gen_rtx_REG (HImode, REGNO (operands[0]));
361 operands[5] = gen_rtx_REG (HImode, REGNO (operands[1]));
364 (define_peephole2 ; movw_r
365 [(set (match_operand:QI 0 "odd_register_operand" "")
366 (match_operand:QI 1 "odd_register_operand" ""))
367 (set (match_operand:QI 2 "even_register_operand" "")
368 (match_operand:QI 3 "even_register_operand" ""))]
370 && REGNO (operands[2]) == REGNO (operands[0]) - 1
371 && REGNO (operands[3]) == REGNO (operands[1]) - 1)"
372 [(set (match_dup 4) (match_dup 5))]
374 operands[4] = gen_rtx_REG (HImode, REGNO (operands[2]));
375 operands[5] = gen_rtx_REG (HImode, REGNO (operands[3]));
378 ;;==========================================================================
379 ;; move double word (32 bit)
381 (define_expand "movsi"
382 [(set (match_operand:SI 0 "nonimmediate_operand" "")
383 (match_operand:SI 1 "general_operand" ""))]
387 /* One of the ops has to be in a register. */
388 if (!register_operand (operand0, SImode)
389 && !(register_operand (operand1, SImode) || const0_rtx == operand1))
391 operands[1] = copy_to_mode_reg (SImode, operand1);
397 (define_peephole2 ; movsi_lreg_const
398 [(match_scratch:QI 2 "d")
399 (set (match_operand:SI 0 "l_register_operand" "")
400 (match_operand:SI 1 "immediate_operand" ""))
402 "(operands[1] != const0_rtx
403 && operands[1] != constm1_rtx)"
404 [(parallel [(set (match_dup 0) (match_dup 1))
405 (clobber (match_dup 2))])]
408 ;; '*' because it is not used in rtl generation.
409 (define_insn "*reload_insi"
410 [(set (match_operand:SI 0 "register_operand" "=r")
411 (match_operand:SI 1 "immediate_operand" "i"))
412 (clobber (match_operand:QI 2 "register_operand" "=&d"))]
414 "* return output_reload_insisf (insn, operands, NULL);"
415 [(set_attr "length" "8")
416 (set_attr "cc" "none")])
419 (define_insn "*movsi"
420 [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r,Qm,!d,r")
421 (match_operand:SI 1 "general_operand" "r,L,Qm,rL,i,i"))]
422 "(register_operand (operands[0],SImode)
423 || register_operand (operands[1],SImode) || const0_rtx == operands[1])"
424 "* return output_movsisf (insn, operands, NULL);"
425 [(set_attr "length" "4,4,8,9,4,10")
426 (set_attr "cc" "none,set_zn,clobber,clobber,none,clobber")])
428 ;; fffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff
429 ;; move floating point numbers (32 bit)
431 (define_expand "movsf"
432 [(set (match_operand:SF 0 "nonimmediate_operand" "")
433 (match_operand:SF 1 "general_operand" ""))]
437 /* One of the ops has to be in a register. */
438 if (!register_operand (operand1, SFmode)
439 && !register_operand (operand0, SFmode))
441 operands[1] = copy_to_mode_reg (SFmode, operand1);
445 (define_insn "*movsf"
446 [(set (match_operand:SF 0 "nonimmediate_operand" "=r,r,r,Qm,!d,r")
447 (match_operand:SF 1 "general_operand" "r,G,Qm,r,F,F"))]
448 "register_operand (operands[0], SFmode)
449 || register_operand (operands[1], SFmode)"
450 "* return output_movsisf (insn, operands, NULL);"
451 [(set_attr "length" "4,4,8,9,4,10")
452 (set_attr "cc" "none,set_zn,clobber,clobber,none,clobber")])
454 ;;=========================================================================
455 ;; move string (like memcpy)
456 ;; implement as RTL loop
458 (define_expand "movmemhi"
459 [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
460 (match_operand:BLK 1 "memory_operand" ""))
461 (use (match_operand:HI 2 "const_int_operand" ""))
462 (use (match_operand:HI 3 "const_int_operand" ""))])]
467 enum machine_mode mode;
468 rtx label = gen_label_rtx ();
472 /* Copy pointers into new psuedos - they will be changed. */
473 rtx addr0 = copy_to_mode_reg (Pmode, XEXP (operands[0], 0));
474 rtx addr1 = copy_to_mode_reg (Pmode, XEXP (operands[1], 0));
476 /* Create rtx for tmp register - we use this as scratch. */
477 rtx tmp_reg_rtx = gen_rtx_REG (QImode, TMP_REGNO);
479 if (GET_CODE (operands[2]) != CONST_INT)
482 count = INTVAL (operands[2]);
486 /* Work out branch probability for latter use. */
487 prob = REG_BR_PROB_BASE - REG_BR_PROB_BASE / count;
489 /* See if constant fit 8 bits. */
490 mode = (count < 0x100) ? QImode : HImode;
491 /* Create loop counter register. */
492 loop_reg = copy_to_mode_reg (mode, gen_int_mode (count, mode));
494 /* Now create RTL code for move loop. */
495 /* Label at top of loop. */
498 /* Move one byte into scratch and inc pointer. */
499 emit_move_insn (tmp_reg_rtx, gen_rtx_MEM (QImode, addr1));
500 emit_move_insn (addr1, gen_rtx_PLUS (Pmode, addr1, const1_rtx));
502 /* Move to mem and inc pointer. */
503 emit_move_insn (gen_rtx_MEM (QImode, addr0), tmp_reg_rtx);
504 emit_move_insn (addr0, gen_rtx_PLUS (Pmode, addr0, const1_rtx));
506 /* Decrement count. */
507 emit_move_insn (loop_reg, gen_rtx_PLUS (mode, loop_reg, constm1_rtx));
509 /* Compare with zero and jump if not equal. */
510 emit_cmp_and_jump_insns (loop_reg, const0_rtx, NE, NULL_RTX, mode, 1,
512 /* Set jump probability based on loop count. */
513 jump = get_last_insn ();
514 add_reg_note (jump, REG_BR_PROB, GEN_INT (prob));
518 ;; =%2 =%2 =%2 =%2 =%2 =%2 =%2 =%2 =%2 =%2 =%2 =%2 =%2 =%2 =%2 =%2 =%2 =%2 =%2 =%2 =%2
519 ;; memset (%0, %2, %1)
521 (define_expand "setmemhi"
522 [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
523 (match_operand 2 "const_int_operand" ""))
524 (use (match_operand:HI 1 "const_int_operand" ""))
525 (use (match_operand:HI 3 "const_int_operand" "n"))
526 (clobber (match_scratch:HI 4 ""))
527 (clobber (match_dup 5))])]
532 enum machine_mode mode;
534 /* If value to set is not zero, use the library routine. */
535 if (operands[2] != const0_rtx)
538 if (GET_CODE (operands[1]) != CONST_INT)
541 cnt8 = byte_immediate_operand (operands[1], GET_MODE (operands[1]));
542 mode = cnt8 ? QImode : HImode;
543 operands[5] = gen_rtx_SCRATCH (mode);
544 operands[1] = copy_to_mode_reg (mode,
545 gen_int_mode (INTVAL (operands[1]), mode));
546 addr0 = copy_to_mode_reg (Pmode, XEXP (operands[0], 0));
547 operands[0] = gen_rtx_MEM (BLKmode, addr0);
550 (define_insn "*clrmemqi"
551 [(set (mem:BLK (match_operand:HI 0 "register_operand" "e"))
553 (use (match_operand:QI 1 "register_operand" "r"))
554 (use (match_operand:QI 2 "const_int_operand" "n"))
555 (clobber (match_scratch:HI 3 "=0"))
556 (clobber (match_scratch:QI 4 "=&1"))]
558 "st %a0+,__zero_reg__
561 [(set_attr "length" "3")
562 (set_attr "cc" "clobber")])
564 (define_insn "*clrmemhi"
565 [(set (mem:BLK (match_operand:HI 0 "register_operand" "e,e"))
567 (use (match_operand:HI 1 "register_operand" "!w,d"))
568 (use (match_operand:HI 2 "const_int_operand" "n,n"))
569 (clobber (match_scratch:HI 3 "=0,0"))
570 (clobber (match_scratch:HI 4 "=&1,&1"))]
573 if (which_alternative==0)
574 return (AS2 (st,%a0+,__zero_reg__) CR_TAB
575 AS2 (sbiw,%A1,1) CR_TAB
578 return (AS2 (st,%a0+,__zero_reg__) CR_TAB
579 AS2 (subi,%A1,1) CR_TAB
580 AS2 (sbci,%B1,0) CR_TAB
583 [(set_attr "length" "3,4")
584 (set_attr "cc" "clobber,clobber")])
586 (define_expand "strlenhi"
588 (unspec:HI [(match_operand:BLK 1 "memory_operand" "")
589 (match_operand:QI 2 "const_int_operand" "")
590 (match_operand:HI 3 "immediate_operand" "")]
592 (set (match_dup 4) (plus:HI (match_dup 4)
594 (set (match_operand:HI 0 "register_operand" "")
595 (minus:HI (match_dup 4)
600 if (! (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == 0))
602 addr = copy_to_mode_reg (Pmode, XEXP (operands[1],0));
603 operands[1] = gen_rtx_MEM (BLKmode, addr);
605 operands[4] = gen_reg_rtx (HImode);
608 (define_insn "*strlenhi"
609 [(set (match_operand:HI 0 "register_operand" "=e")
610 (unspec:HI [(mem:BLK (match_operand:HI 1 "register_operand" "%0"))
612 (match_operand:HI 2 "immediate_operand" "i")]
618 [(set_attr "length" "3")
619 (set_attr "cc" "clobber")])
621 ;+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
624 (define_insn "addqi3"
625 [(set (match_operand:QI 0 "register_operand" "=r,d,r,r")
626 (plus:QI (match_operand:QI 1 "register_operand" "%0,0,0,0")
627 (match_operand:QI 2 "nonmemory_operand" "r,i,P,N")))]
634 [(set_attr "length" "1,1,1,1")
635 (set_attr "cc" "set_czn,set_czn,set_zn,set_zn")])
638 (define_expand "addhi3"
639 [(set (match_operand:HI 0 "register_operand" "")
640 (plus:HI (match_operand:HI 1 "register_operand" "")
641 (match_operand:HI 2 "nonmemory_operand" "")))]
645 if (GET_CODE (operands[2]) == CONST_INT)
647 short tmp = INTVAL (operands[2]);
648 operands[2] = GEN_INT(tmp);
653 (define_insn "*addhi3_zero_extend"
654 [(set (match_operand:HI 0 "register_operand" "=r")
655 (plus:HI (zero_extend:HI
656 (match_operand:QI 1 "register_operand" "r"))
657 (match_operand:HI 2 "register_operand" "0")))]
660 adc %B0,__zero_reg__"
661 [(set_attr "length" "2")
662 (set_attr "cc" "set_n")])
664 (define_insn "*addhi3_zero_extend1"
665 [(set (match_operand:HI 0 "register_operand" "=r")
666 (plus:HI (match_operand:HI 1 "register_operand" "%0")
668 (match_operand:QI 2 "register_operand" "r"))))]
671 adc %B0,__zero_reg__"
672 [(set_attr "length" "2")
673 (set_attr "cc" "set_n")])
675 (define_insn "*addhi3_sp_R_pc2"
676 [(set (match_operand:HI 1 "stack_register_operand" "=q")
677 (plus:HI (match_operand:HI 2 "stack_register_operand" "q")
678 (match_operand:HI 0 "avr_sp_immediate_operand" "R")))]
681 if (CONST_INT_P (operands[0]))
683 switch(INTVAL (operands[0]))
686 return \"rcall .\" CR_TAB
690 return \"rcall .\" CR_TAB
692 \"push __tmp_reg__\";
694 return \"rcall .\" CR_TAB
697 return \"rcall .\" CR_TAB
698 \"push __tmp_reg__\";
702 return \"push __tmp_reg__\";
706 return \"pop __tmp_reg__\";
708 return \"pop __tmp_reg__\" CR_TAB
711 return \"pop __tmp_reg__\" CR_TAB
712 \"pop __tmp_reg__\" CR_TAB
715 return \"pop __tmp_reg__\" CR_TAB
716 \"pop __tmp_reg__\" CR_TAB
717 \"pop __tmp_reg__\" CR_TAB
720 return \"pop __tmp_reg__\" CR_TAB
721 \"pop __tmp_reg__\" CR_TAB
722 \"pop __tmp_reg__\" CR_TAB
723 \"pop __tmp_reg__\" CR_TAB
729 [(set (attr "length")
730 (cond [(eq (const_int -6) (symbol_ref "INTVAL (operands[0])")) (const_int 3)
731 (eq (const_int -5) (symbol_ref "INTVAL (operands[0])")) (const_int 3)
732 (eq (const_int -4) (symbol_ref "INTVAL (operands[0])")) (const_int 2)
733 (eq (const_int -3) (symbol_ref "INTVAL (operands[0])")) (const_int 2)
734 (eq (const_int -2) (symbol_ref "INTVAL (operands[0])")) (const_int 1)
735 (eq (const_int -1) (symbol_ref "INTVAL (operands[0])")) (const_int 1)
736 (eq (const_int 0) (symbol_ref "INTVAL (operands[0])")) (const_int 0)
737 (eq (const_int 1) (symbol_ref "INTVAL (operands[0])")) (const_int 1)
738 (eq (const_int 2) (symbol_ref "INTVAL (operands[0])")) (const_int 2)
739 (eq (const_int 3) (symbol_ref "INTVAL (operands[0])")) (const_int 3)
740 (eq (const_int 4) (symbol_ref "INTVAL (operands[0])")) (const_int 4)
741 (eq (const_int 5) (symbol_ref "INTVAL (operands[0])")) (const_int 5)]
744 (define_insn "*addhi3_sp_R_pc3"
745 [(set (match_operand:HI 1 "stack_register_operand" "=q")
746 (plus:HI (match_operand:HI 2 "stack_register_operand" "q")
747 (match_operand:QI 0 "avr_sp_immediate_operand" "R")))]
750 if (CONST_INT_P (operands[0]))
752 switch(INTVAL (operands[0]))
755 return \"rcall .\" CR_TAB
758 return \"rcall .\" CR_TAB
759 \"push __tmp_reg__\" CR_TAB
760 \"push __tmp_reg__\";
762 return \"rcall .\" CR_TAB
763 \"push __tmp_reg__\";
767 return \"push __tmp_reg__\" CR_TAB
768 \"push __tmp_reg__\";
770 return \"push __tmp_reg__\";
774 return \"pop __tmp_reg__\";
776 return \"pop __tmp_reg__\" CR_TAB
779 return \"pop __tmp_reg__\" CR_TAB
780 \"pop __tmp_reg__\" CR_TAB
783 return \"pop __tmp_reg__\" CR_TAB
784 \"pop __tmp_reg__\" CR_TAB
785 \"pop __tmp_reg__\" CR_TAB
788 return \"pop __tmp_reg__\" CR_TAB
789 \"pop __tmp_reg__\" CR_TAB
790 \"pop __tmp_reg__\" CR_TAB
791 \"pop __tmp_reg__\" CR_TAB
797 [(set (attr "length")
798 (cond [(eq (const_int -6) (symbol_ref "INTVAL (operands[0])")) (const_int 2)
799 (eq (const_int -5) (symbol_ref "INTVAL (operands[0])")) (const_int 3)
800 (eq (const_int -4) (symbol_ref "INTVAL (operands[0])")) (const_int 2)
801 (eq (const_int -3) (symbol_ref "INTVAL (operands[0])")) (const_int 1)
802 (eq (const_int -2) (symbol_ref "INTVAL (operands[0])")) (const_int 2)
803 (eq (const_int -1) (symbol_ref "INTVAL (operands[0])")) (const_int 1)
804 (eq (const_int 0) (symbol_ref "INTVAL (operands[0])")) (const_int 0)
805 (eq (const_int 1) (symbol_ref "INTVAL (operands[0])")) (const_int 1)
806 (eq (const_int 2) (symbol_ref "INTVAL (operands[0])")) (const_int 2)
807 (eq (const_int 3) (symbol_ref "INTVAL (operands[0])")) (const_int 3)
808 (eq (const_int 4) (symbol_ref "INTVAL (operands[0])")) (const_int 4)
809 (eq (const_int 5) (symbol_ref "INTVAL (operands[0])")) (const_int 5)]
812 (define_insn "*addhi3"
813 [(set (match_operand:HI 0 "register_operand" "=r,!w,!w,d,r,r")
815 (match_operand:HI 1 "register_operand" "%0,0,0,0,0,0")
816 (match_operand:HI 2 "nonmemory_operand" "r,I,J,i,P,N")))]
819 add %A0,%A2\;adc %B0,%B2
822 subi %A0,lo8(-(%2))\;sbci %B0,hi8(-(%2))
823 sec\;adc %A0,__zero_reg__\;adc %B0,__zero_reg__
824 sec\;sbc %A0,__zero_reg__\;sbc %B0,__zero_reg__"
825 [(set_attr "length" "2,1,1,2,3,3")
826 (set_attr "cc" "set_n,set_czn,set_czn,set_czn,set_n,set_n")])
828 (define_insn "addsi3"
829 [(set (match_operand:SI 0 "register_operand" "=r,!w,!w,d,r,r")
831 (match_operand:SI 1 "register_operand" "%0,0,0,0,0,0")
832 (match_operand:SI 2 "nonmemory_operand" "r,I,J,i,P,N")))]
835 add %A0,%A2\;adc %B0,%B2\;adc %C0,%C2\;adc %D0,%D2
836 adiw %0,%2\;adc %C0,__zero_reg__\;adc %D0,__zero_reg__
837 sbiw %0,%n2\;sbc %C0,__zero_reg__\;sbc %D0,__zero_reg__
838 subi %0,lo8(-(%2))\;sbci %B0,hi8(-(%2))\;sbci %C0,hlo8(-(%2))\;sbci %D0,hhi8(-(%2))
839 sec\;adc %A0,__zero_reg__\;adc %B0,__zero_reg__\;adc %C0,__zero_reg__\;adc %D0,__zero_reg__
840 sec\;sbc %A0,__zero_reg__\;sbc %B0,__zero_reg__\;sbc %C0,__zero_reg__\;sbc %D0,__zero_reg__"
841 [(set_attr "length" "4,3,3,4,5,5")
842 (set_attr "cc" "set_n,set_n,set_czn,set_czn,set_n,set_n")])
844 (define_insn "*addsi3_zero_extend"
845 [(set (match_operand:SI 0 "register_operand" "=r")
846 (plus:SI (zero_extend:SI
847 (match_operand:QI 1 "register_operand" "r"))
848 (match_operand:SI 2 "register_operand" "0")))]
853 adc %D0,__zero_reg__"
854 [(set_attr "length" "4")
855 (set_attr "cc" "set_n")])
857 ;-----------------------------------------------------------------------------
859 (define_insn "subqi3"
860 [(set (match_operand:QI 0 "register_operand" "=r,d")
861 (minus:QI (match_operand:QI 1 "register_operand" "0,0")
862 (match_operand:QI 2 "nonmemory_operand" "r,i")))]
867 [(set_attr "length" "1,1")
868 (set_attr "cc" "set_czn,set_czn")])
870 (define_insn "subhi3"
871 [(set (match_operand:HI 0 "register_operand" "=r,d")
872 (minus:HI (match_operand:HI 1 "register_operand" "0,0")
873 (match_operand:HI 2 "nonmemory_operand" "r,i")))]
876 sub %A0,%A2\;sbc %B0,%B2
877 subi %A0,lo8(%2)\;sbci %B0,hi8(%2)"
878 [(set_attr "length" "2,2")
879 (set_attr "cc" "set_czn,set_czn")])
881 (define_insn "*subhi3_zero_extend1"
882 [(set (match_operand:HI 0 "register_operand" "=r")
883 (minus:HI (match_operand:HI 1 "register_operand" "0")
885 (match_operand:QI 2 "register_operand" "r"))))]
888 sbc %B0,__zero_reg__"
889 [(set_attr "length" "2")
890 (set_attr "cc" "set_n")])
892 (define_insn "subsi3"
893 [(set (match_operand:SI 0 "register_operand" "=r,d")
894 (minus:SI (match_operand:SI 1 "register_operand" "0,0")
895 (match_operand:SI 2 "nonmemory_operand" "r,i")))]
898 sub %0,%2\;sbc %B0,%B2\;sbc %C0,%C2\;sbc %D0,%D2
899 subi %A0,lo8(%2)\;sbci %B0,hi8(%2)\;sbci %C0,hlo8(%2)\;sbci %D0,hhi8(%2)"
900 [(set_attr "length" "4,4")
901 (set_attr "cc" "set_czn,set_czn")])
903 (define_insn "*subsi3_zero_extend"
904 [(set (match_operand:SI 0 "register_operand" "=r")
905 (minus:SI (match_operand:SI 1 "register_operand" "0")
907 (match_operand:QI 2 "register_operand" "r"))))]
912 sbc %D0,__zero_reg__"
913 [(set_attr "length" "4")
914 (set_attr "cc" "set_n")])
916 ;******************************************************************************
919 (define_expand "mulqi3"
920 [(set (match_operand:QI 0 "register_operand" "")
921 (mult:QI (match_operand:QI 1 "register_operand" "")
922 (match_operand:QI 2 "register_operand" "")))]
927 emit_insn (gen_mulqi3_call (operands[0], operands[1], operands[2]));
932 (define_insn "*mulqi3_enh"
933 [(set (match_operand:QI 0 "register_operand" "=r")
934 (mult:QI (match_operand:QI 1 "register_operand" "r")
935 (match_operand:QI 2 "register_operand" "r")))]
940 [(set_attr "length" "3")
941 (set_attr "cc" "clobber")])
943 (define_expand "mulqi3_call"
944 [(set (reg:QI 24) (match_operand:QI 1 "register_operand" ""))
945 (set (reg:QI 22) (match_operand:QI 2 "register_operand" ""))
946 (parallel [(set (reg:QI 24) (mult:QI (reg:QI 24) (reg:QI 22)))
947 (clobber (reg:QI 22))])
948 (set (match_operand:QI 0 "register_operand" "") (reg:QI 24))]
952 (define_insn "*mulqi3_call"
953 [(set (reg:QI 24) (mult:QI (reg:QI 24) (reg:QI 22)))
954 (clobber (reg:QI 22))]
957 [(set_attr "type" "xcall")
958 (set_attr "cc" "clobber")])
960 (define_insn "mulqihi3"
961 [(set (match_operand:HI 0 "register_operand" "=r")
962 (mult:HI (sign_extend:HI (match_operand:QI 1 "register_operand" "d"))
963 (sign_extend:HI (match_operand:QI 2 "register_operand" "d"))))]
968 [(set_attr "length" "3")
969 (set_attr "cc" "clobber")])
971 (define_insn "umulqihi3"
972 [(set (match_operand:HI 0 "register_operand" "=r")
973 (mult:HI (zero_extend:HI (match_operand:QI 1 "register_operand" "r"))
974 (zero_extend:HI (match_operand:QI 2 "register_operand" "r"))))]
979 [(set_attr "length" "3")
980 (set_attr "cc" "clobber")])
982 (define_expand "mulhi3"
983 [(set (match_operand:HI 0 "register_operand" "")
984 (mult:HI (match_operand:HI 1 "register_operand" "")
985 (match_operand:HI 2 "register_operand" "")))]
991 emit_insn (gen_mulhi3_call (operands[0], operands[1], operands[2]));
996 (define_insn "*mulhi3_enh"
997 [(set (match_operand:HI 0 "register_operand" "=&r")
998 (mult:HI (match_operand:HI 1 "register_operand" "r")
999 (match_operand:HI 2 "register_operand" "r")))]
1008 [(set_attr "length" "7")
1009 (set_attr "cc" "clobber")])
1011 (define_expand "mulhi3_call"
1012 [(set (reg:HI 24) (match_operand:HI 1 "register_operand" ""))
1013 (set (reg:HI 22) (match_operand:HI 2 "register_operand" ""))
1014 (parallel [(set (reg:HI 24) (mult:HI (reg:HI 24) (reg:HI 22)))
1015 (clobber (reg:HI 22))
1016 (clobber (reg:QI 21))])
1017 (set (match_operand:HI 0 "register_operand" "") (reg:HI 24))]
1021 (define_insn "*mulhi3_call"
1022 [(set (reg:HI 24) (mult:HI (reg:HI 24) (reg:HI 22)))
1023 (clobber (reg:HI 22))
1024 (clobber (reg:QI 21))]
1027 [(set_attr "type" "xcall")
1028 (set_attr "cc" "clobber")])
1030 ;; Operand 2 (reg:SI 18) not clobbered on the enhanced core.
1031 ;; All call-used registers clobbered otherwise - normal library call.
1032 (define_expand "mulsi3"
1033 [(set (reg:SI 22) (match_operand:SI 1 "register_operand" ""))
1034 (set (reg:SI 18) (match_operand:SI 2 "register_operand" ""))
1035 (parallel [(set (reg:SI 22) (mult:SI (reg:SI 22) (reg:SI 18)))
1036 (clobber (reg:HI 26))
1037 (clobber (reg:HI 30))])
1038 (set (match_operand:SI 0 "register_operand" "") (reg:SI 22))]
1042 (define_insn "*mulsi3_call"
1043 [(set (reg:SI 22) (mult:SI (reg:SI 22) (reg:SI 18)))
1044 (clobber (reg:HI 26))
1045 (clobber (reg:HI 30))]
1048 [(set_attr "type" "xcall")
1049 (set_attr "cc" "clobber")])
1051 ; / % / % / % / % / % / % / % / % / % / % / % / % / % / % / % / % / % / % / %
1054 ;; Generate libgcc.S calls ourselves, because:
1055 ;; - we know exactly which registers are clobbered (for QI and HI
1056 ;; modes, some of the call-used registers are preserved)
1057 ;; - we get both the quotient and the remainder at no extra cost
1058 ;; - we split the patterns only after the first CSE passes because
1059 ;; CSE has problems to operate on hard regs.
1061 (define_insn_and_split "divmodqi4"
1062 [(parallel [(set (match_operand:QI 0 "pseudo_register_operand" "")
1063 (div:QI (match_operand:QI 1 "pseudo_register_operand" "")
1064 (match_operand:QI 2 "pseudo_register_operand" "")))
1065 (set (match_operand:QI 3 "pseudo_register_operand" "")
1066 (mod:QI (match_dup 1) (match_dup 2)))
1067 (clobber (reg:QI 22))
1068 (clobber (reg:QI 23))
1069 (clobber (reg:QI 24))
1070 (clobber (reg:QI 25))])]
1072 "this divmodqi4 pattern should have been splitted;"
1074 [(set (reg:QI 24) (match_dup 1))
1075 (set (reg:QI 22) (match_dup 2))
1076 (parallel [(set (reg:QI 24) (div:QI (reg:QI 24) (reg:QI 22)))
1077 (set (reg:QI 25) (mod:QI (reg:QI 24) (reg:QI 22)))
1078 (clobber (reg:QI 22))
1079 (clobber (reg:QI 23))])
1080 (set (match_dup 0) (reg:QI 24))
1081 (set (match_dup 3) (reg:QI 25))]
1084 (define_insn "*divmodqi4_call"
1085 [(set (reg:QI 24) (div:QI (reg:QI 24) (reg:QI 22)))
1086 (set (reg:QI 25) (mod:QI (reg:QI 24) (reg:QI 22)))
1087 (clobber (reg:QI 22))
1088 (clobber (reg:QI 23))]
1090 "%~call __divmodqi4"
1091 [(set_attr "type" "xcall")
1092 (set_attr "cc" "clobber")])
1094 (define_insn_and_split "udivmodqi4"
1095 [(parallel [(set (match_operand:QI 0 "pseudo_register_operand" "")
1096 (udiv:QI (match_operand:QI 1 "pseudo_register_operand" "")
1097 (match_operand:QI 2 "pseudo_register_operand" "")))
1098 (set (match_operand:QI 3 "pseudo_register_operand" "")
1099 (umod:QI (match_dup 1) (match_dup 2)))
1100 (clobber (reg:QI 22))
1101 (clobber (reg:QI 23))
1102 (clobber (reg:QI 24))
1103 (clobber (reg:QI 25))])]
1105 "this udivmodqi4 pattern should have been splitted;"
1107 [(set (reg:QI 24) (match_dup 1))
1108 (set (reg:QI 22) (match_dup 2))
1109 (parallel [(set (reg:QI 24) (udiv:QI (reg:QI 24) (reg:QI 22)))
1110 (set (reg:QI 25) (umod:QI (reg:QI 24) (reg:QI 22)))
1111 (clobber (reg:QI 23))])
1112 (set (match_dup 0) (reg:QI 24))
1113 (set (match_dup 3) (reg:QI 25))]
1116 (define_insn "*udivmodqi4_call"
1117 [(set (reg:QI 24) (udiv:QI (reg:QI 24) (reg:QI 22)))
1118 (set (reg:QI 25) (umod:QI (reg:QI 24) (reg:QI 22)))
1119 (clobber (reg:QI 23))]
1121 "%~call __udivmodqi4"
1122 [(set_attr "type" "xcall")
1123 (set_attr "cc" "clobber")])
1125 (define_insn_and_split "divmodhi4"
1126 [(parallel [(set (match_operand:HI 0 "pseudo_register_operand" "")
1127 (div:HI (match_operand:HI 1 "pseudo_register_operand" "")
1128 (match_operand:HI 2 "pseudo_register_operand" "")))
1129 (set (match_operand:HI 3 "pseudo_register_operand" "")
1130 (mod:HI (match_dup 1) (match_dup 2)))
1131 (clobber (reg:QI 21))
1132 (clobber (reg:HI 22))
1133 (clobber (reg:HI 24))
1134 (clobber (reg:HI 26))])]
1136 "this should have been splitted;"
1138 [(set (reg:HI 24) (match_dup 1))
1139 (set (reg:HI 22) (match_dup 2))
1140 (parallel [(set (reg:HI 22) (div:HI (reg:HI 24) (reg:HI 22)))
1141 (set (reg:HI 24) (mod:HI (reg:HI 24) (reg:HI 22)))
1142 (clobber (reg:HI 26))
1143 (clobber (reg:QI 21))])
1144 (set (match_dup 0) (reg:HI 22))
1145 (set (match_dup 3) (reg:HI 24))]
1148 (define_insn "*divmodhi4_call"
1149 [(set (reg:HI 22) (div:HI (reg:HI 24) (reg:HI 22)))
1150 (set (reg:HI 24) (mod:HI (reg:HI 24) (reg:HI 22)))
1151 (clobber (reg:HI 26))
1152 (clobber (reg:QI 21))]
1154 "%~call __divmodhi4"
1155 [(set_attr "type" "xcall")
1156 (set_attr "cc" "clobber")])
1158 (define_insn_and_split "udivmodhi4"
1159 [(parallel [(set (match_operand:HI 0 "pseudo_register_operand" "")
1160 (udiv:HI (match_operand:HI 1 "pseudo_register_operand" "")
1161 (match_operand:HI 2 "pseudo_register_operand" "")))
1162 (set (match_operand:HI 3 "pseudo_register_operand" "")
1163 (umod:HI (match_dup 1) (match_dup 2)))
1164 (clobber (reg:QI 21))
1165 (clobber (reg:HI 22))
1166 (clobber (reg:HI 24))
1167 (clobber (reg:HI 26))])]
1169 "this udivmodhi4 pattern should have been splitted.;"
1171 [(set (reg:HI 24) (match_dup 1))
1172 (set (reg:HI 22) (match_dup 2))
1173 (parallel [(set (reg:HI 22) (udiv:HI (reg:HI 24) (reg:HI 22)))
1174 (set (reg:HI 24) (umod:HI (reg:HI 24) (reg:HI 22)))
1175 (clobber (reg:HI 26))
1176 (clobber (reg:QI 21))])
1177 (set (match_dup 0) (reg:HI 22))
1178 (set (match_dup 3) (reg:HI 24))]
1181 (define_insn "*udivmodhi4_call"
1182 [(set (reg:HI 22) (udiv:HI (reg:HI 24) (reg:HI 22)))
1183 (set (reg:HI 24) (umod:HI (reg:HI 24) (reg:HI 22)))
1184 (clobber (reg:HI 26))
1185 (clobber (reg:QI 21))]
1187 "%~call __udivmodhi4"
1188 [(set_attr "type" "xcall")
1189 (set_attr "cc" "clobber")])
1191 (define_insn_and_split "divmodsi4"
1192 [(parallel [(set (match_operand:SI 0 "pseudo_register_operand" "")
1193 (div:SI (match_operand:SI 1 "pseudo_register_operand" "")
1194 (match_operand:SI 2 "pseudo_register_operand" "")))
1195 (set (match_operand:SI 3 "pseudo_register_operand" "")
1196 (mod:SI (match_dup 1) (match_dup 2)))
1197 (clobber (reg:SI 18))
1198 (clobber (reg:SI 22))
1199 (clobber (reg:HI 26))
1200 (clobber (reg:HI 30))])]
1202 "this divmodsi4 pattern should have been splitted;"
1204 [(set (reg:SI 22) (match_dup 1))
1205 (set (reg:SI 18) (match_dup 2))
1206 (parallel [(set (reg:SI 18) (div:SI (reg:SI 22) (reg:SI 18)))
1207 (set (reg:SI 22) (mod:SI (reg:SI 22) (reg:SI 18)))
1208 (clobber (reg:HI 26))
1209 (clobber (reg:HI 30))])
1210 (set (match_dup 0) (reg:SI 18))
1211 (set (match_dup 3) (reg:SI 22))]
1214 (define_insn "*divmodsi4_call"
1215 [(set (reg:SI 18) (div:SI (reg:SI 22) (reg:SI 18)))
1216 (set (reg:SI 22) (mod:SI (reg:SI 22) (reg:SI 18)))
1217 (clobber (reg:HI 26))
1218 (clobber (reg:HI 30))]
1220 "%~call __divmodsi4"
1221 [(set_attr "type" "xcall")
1222 (set_attr "cc" "clobber")])
1224 (define_insn_and_split "udivmodsi4"
1225 [(parallel [(set (match_operand:SI 0 "pseudo_register_operand" "")
1226 (udiv:SI (match_operand:SI 1 "pseudo_register_operand" "")
1227 (match_operand:SI 2 "pseudo_register_operand" "")))
1228 (set (match_operand:SI 3 "pseudo_register_operand" "")
1229 (umod:SI (match_dup 1) (match_dup 2)))
1230 (clobber (reg:SI 18))
1231 (clobber (reg:SI 22))
1232 (clobber (reg:HI 26))
1233 (clobber (reg:HI 30))])]
1235 "this udivmodsi4 pattern should have been splitted;"
1237 [(set (reg:SI 22) (match_dup 1))
1238 (set (reg:SI 18) (match_dup 2))
1239 (parallel [(set (reg:SI 18) (udiv:SI (reg:SI 22) (reg:SI 18)))
1240 (set (reg:SI 22) (umod:SI (reg:SI 22) (reg:SI 18)))
1241 (clobber (reg:HI 26))
1242 (clobber (reg:HI 30))])
1243 (set (match_dup 0) (reg:SI 18))
1244 (set (match_dup 3) (reg:SI 22))]
1247 (define_insn "*udivmodsi4_call"
1248 [(set (reg:SI 18) (udiv:SI (reg:SI 22) (reg:SI 18)))
1249 (set (reg:SI 22) (umod:SI (reg:SI 22) (reg:SI 18)))
1250 (clobber (reg:HI 26))
1251 (clobber (reg:HI 30))]
1253 "%~call __udivmodsi4"
1254 [(set_attr "type" "xcall")
1255 (set_attr "cc" "clobber")])
1257 ;&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&
1260 (define_insn "andqi3"
1261 [(set (match_operand:QI 0 "register_operand" "=r,d")
1262 (and:QI (match_operand:QI 1 "register_operand" "%0,0")
1263 (match_operand:QI 2 "nonmemory_operand" "r,i")))]
1268 [(set_attr "length" "1,1")
1269 (set_attr "cc" "set_zn,set_zn")])
1271 (define_insn "andhi3"
1272 [(set (match_operand:HI 0 "register_operand" "=r,d,r")
1273 (and:HI (match_operand:HI 1 "register_operand" "%0,0,0")
1274 (match_operand:HI 2 "nonmemory_operand" "r,i,M")))
1275 (clobber (match_scratch:QI 3 "=X,X,&d"))]
1278 if (which_alternative==0)
1279 return ("and %A0,%A2" CR_TAB
1281 else if (which_alternative==1)
1283 if (GET_CODE (operands[2]) == CONST_INT)
1285 int mask = INTVAL (operands[2]);
1286 if ((mask & 0xff) != 0xff)
1287 output_asm_insn (AS2 (andi,%A0,lo8(%2)), operands);
1288 if ((mask & 0xff00) != 0xff00)
1289 output_asm_insn (AS2 (andi,%B0,hi8(%2)), operands);
1292 return (AS2 (andi,%A0,lo8(%2)) CR_TAB
1293 AS2 (andi,%B0,hi8(%2)));
1295 return (AS2 (ldi,%3,lo8(%2)) CR_TAB
1299 [(set_attr "length" "2,2,3")
1300 (set_attr "cc" "set_n,clobber,set_n")])
1302 (define_insn "andsi3"
1303 [(set (match_operand:SI 0 "register_operand" "=r,d")
1304 (and:SI (match_operand:SI 1 "register_operand" "%0,0")
1305 (match_operand:SI 2 "nonmemory_operand" "r,i")))]
1308 if (which_alternative==0)
1309 return ("and %0,%2" CR_TAB
1310 "and %B0,%B2" CR_TAB
1311 "and %C0,%C2" CR_TAB
1313 else if (which_alternative==1)
1315 if (GET_CODE (operands[2]) == CONST_INT)
1317 HOST_WIDE_INT mask = INTVAL (operands[2]);
1318 if ((mask & 0xff) != 0xff)
1319 output_asm_insn (AS2 (andi,%A0,lo8(%2)), operands);
1320 if ((mask & 0xff00) != 0xff00)
1321 output_asm_insn (AS2 (andi,%B0,hi8(%2)), operands);
1322 if ((mask & 0xff0000L) != 0xff0000L)
1323 output_asm_insn (AS2 (andi,%C0,hlo8(%2)), operands);
1324 if ((mask & 0xff000000L) != 0xff000000L)
1325 output_asm_insn (AS2 (andi,%D0,hhi8(%2)), operands);
1328 return (AS2 (andi, %A0,lo8(%2)) CR_TAB
1329 AS2 (andi, %B0,hi8(%2)) CR_TAB
1330 AS2 (andi, %C0,hlo8(%2)) CR_TAB
1331 AS2 (andi, %D0,hhi8(%2)));
1335 [(set_attr "length" "4,4")
1336 (set_attr "cc" "set_n,clobber")])
1338 (define_peephole2 ; andi
1339 [(set (match_operand:QI 0 "d_register_operand" "")
1340 (and:QI (match_dup 0)
1341 (match_operand:QI 1 "const_int_operand" "")))
1343 (and:QI (match_dup 0)
1344 (match_operand:QI 2 "const_int_operand" "")))]
1346 [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1)))]
1348 operands[1] = GEN_INT (INTVAL (operands[1]) & INTVAL (operands[2]));
1351 ;;|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
1354 (define_insn "iorqi3"
1355 [(set (match_operand:QI 0 "register_operand" "=r,d")
1356 (ior:QI (match_operand:QI 1 "register_operand" "%0,0")
1357 (match_operand:QI 2 "nonmemory_operand" "r,i")))]
1362 [(set_attr "length" "1,1")
1363 (set_attr "cc" "set_zn,set_zn")])
1365 (define_insn "iorhi3"
1366 [(set (match_operand:HI 0 "register_operand" "=r,d")
1367 (ior:HI (match_operand:HI 1 "register_operand" "%0,0")
1368 (match_operand:HI 2 "nonmemory_operand" "r,i")))]
1371 if (which_alternative==0)
1372 return ("or %A0,%A2" CR_TAB
1374 if (GET_CODE (operands[2]) == CONST_INT)
1376 int mask = INTVAL (operands[2]);
1378 output_asm_insn (AS2 (ori,%A0,lo8(%2)), operands);
1380 output_asm_insn (AS2 (ori,%B0,hi8(%2)), operands);
1383 return (AS2 (ori,%0,lo8(%2)) CR_TAB
1384 AS2 (ori,%B0,hi8(%2)));
1386 [(set_attr "length" "2,2")
1387 (set_attr "cc" "set_n,clobber")])
1389 (define_insn "*iorhi3_clobber"
1390 [(set (match_operand:HI 0 "register_operand" "=r,r")
1391 (ior:HI (match_operand:HI 1 "register_operand" "%0,0")
1392 (match_operand:HI 2 "immediate_operand" "M,i")))
1393 (clobber (match_scratch:QI 3 "=&d,&d"))]
1396 ldi %3,lo8(%2)\;or %A0,%3
1397 ldi %3,lo8(%2)\;or %A0,%3\;ldi %3,hi8(%2)\;or %B0,%3"
1398 [(set_attr "length" "2,4")
1399 (set_attr "cc" "clobber,set_n")])
1401 (define_insn "iorsi3"
1402 [(set (match_operand:SI 0 "register_operand" "=r,d")
1403 (ior:SI (match_operand:SI 1 "register_operand" "%0,0")
1404 (match_operand:SI 2 "nonmemory_operand" "r,i")))]
1407 if (which_alternative==0)
1408 return ("or %0,%2" CR_TAB
1412 if (GET_CODE (operands[2]) == CONST_INT)
1414 HOST_WIDE_INT mask = INTVAL (operands[2]);
1416 output_asm_insn (AS2 (ori,%A0,lo8(%2)), operands);
1418 output_asm_insn (AS2 (ori,%B0,hi8(%2)), operands);
1419 if (mask & 0xff0000L)
1420 output_asm_insn (AS2 (ori,%C0,hlo8(%2)), operands);
1421 if (mask & 0xff000000L)
1422 output_asm_insn (AS2 (ori,%D0,hhi8(%2)), operands);
1425 return (AS2 (ori, %A0,lo8(%2)) CR_TAB
1426 AS2 (ori, %B0,hi8(%2)) CR_TAB
1427 AS2 (ori, %C0,hlo8(%2)) CR_TAB
1428 AS2 (ori, %D0,hhi8(%2)));
1430 [(set_attr "length" "4,4")
1431 (set_attr "cc" "set_n,clobber")])
1433 (define_insn "*iorsi3_clobber"
1434 [(set (match_operand:SI 0 "register_operand" "=r,r")
1435 (ior:SI (match_operand:SI 1 "register_operand" "%0,0")
1436 (match_operand:SI 2 "immediate_operand" "M,i")))
1437 (clobber (match_scratch:QI 3 "=&d,&d"))]
1440 ldi %3,lo8(%2)\;or %A0,%3
1441 ldi %3,lo8(%2)\;or %A0,%3\;ldi %3,hi8(%2)\;or %B0,%3\;ldi %3,hlo8(%2)\;or %C0,%3\;ldi %3,hhi8(%2)\;or %D0,%3"
1442 [(set_attr "length" "2,8")
1443 (set_attr "cc" "clobber,set_n")])
1445 ;;^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
1448 (define_insn "xorqi3"
1449 [(set (match_operand:QI 0 "register_operand" "=r")
1450 (xor:QI (match_operand:QI 1 "register_operand" "%0")
1451 (match_operand:QI 2 "register_operand" "r")))]
1454 [(set_attr "length" "1")
1455 (set_attr "cc" "set_zn")])
1457 (define_insn "xorhi3"
1458 [(set (match_operand:HI 0 "register_operand" "=r")
1459 (xor:HI (match_operand:HI 1 "register_operand" "%0")
1460 (match_operand:HI 2 "register_operand" "r")))]
1464 [(set_attr "length" "2")
1465 (set_attr "cc" "set_n")])
1467 (define_insn "xorsi3"
1468 [(set (match_operand:SI 0 "register_operand" "=r")
1469 (xor:SI (match_operand:SI 1 "register_operand" "%0")
1470 (match_operand:SI 2 "register_operand" "r")))]
1476 [(set_attr "length" "4")
1477 (set_attr "cc" "set_n")])
1479 ;; swap swap swap swap swap swap swap swap swap swap swap swap swap swap swap
1482 (define_expand "rotlqi3"
1483 [(set (match_operand:QI 0 "register_operand" "")
1484 (rotate:QI (match_operand:QI 1 "register_operand" "")
1485 (match_operand:QI 2 "const_int_operand" "")))]
1489 if (!CONST_INT_P (operands[2]) || (INTVAL (operands[2]) != 4))
1493 (define_insn "*rotlqi3_4"
1494 [(set (match_operand:QI 0 "register_operand" "=r")
1495 (rotate:QI (match_operand:QI 1 "register_operand" "0")
1499 [(set_attr "length" "1")
1500 (set_attr "cc" "none")])
1502 ;; Split all rotates of HI,SI and DImode registers where rotation is by
1503 ;; a whole number of bytes. The split creates the appropriate moves and
1504 ;; considers all overlap situations. DImode is split before reload.
1506 ;; HImode does not need scratch. Use attribute for this constraint.
1507 ;; Use QI scratch for DI mode as this is often split into byte sized operands.
1509 (define_mode_attr rotx [(DI "&r,&r,X") (SI "&r,&r,X") (HI "X,X,X")])
1510 (define_mode_attr rotsmode [(DI "QI") (SI "HI") (HI "QI")])
1512 (define_expand "rotl<mode>3"
1513 [(parallel [(set (match_operand:HIDI 0 "register_operand" "")
1514 (rotate:HIDI (match_operand:HIDI 1 "register_operand" "")
1515 (match_operand:VOID 2 "const_int_operand" "")))
1516 (clobber (match_operand 3 ""))])]
1520 if (CONST_INT_P (operands[2]) && 0 == (INTVAL (operands[2]) % 8))
1522 if (AVR_HAVE_MOVW && 0 == INTVAL (operands[2]) % 16)
1523 operands[3] = gen_reg_rtx (<rotsmode>mode);
1525 operands[3] = gen_reg_rtx (QImode);
1532 ;; Overlapping non-HImode registers often (but not always) need a scratch.
1533 ;; The best we can do is use early clobber alternative "#&r" so that
1534 ;; completely non-overlapping operands dont get a scratch but # so register
1535 ;; allocation does not prefer non-overlapping.
1538 ; Split word aligned rotates using scratch that is mode dependent.
1539 (define_insn_and_split "*rotw<mode>"
1540 [(set (match_operand:HIDI 0 "register_operand" "=r,r,#&r")
1541 (rotate:HIDI (match_operand:HIDI 1 "register_operand" "0,r,r")
1542 (match_operand 2 "immediate_operand" "n,n,n")))
1543 (clobber (match_operand:<rotsmode> 3 "register_operand" "=<rotx>" ))]
1544 "(CONST_INT_P (operands[2]) &&
1545 (0 == (INTVAL (operands[2]) % 16) && AVR_HAVE_MOVW))"
1547 "&& (reload_completed || <MODE>mode == DImode)"
1549 "avr_rotate_bytes (operands);
1554 ; Split byte aligned rotates using scratch that is always QI mode.
1555 (define_insn_and_split "*rotb<mode>"
1556 [(set (match_operand:HIDI 0 "register_operand" "=r,r,#&r")
1557 (rotate:HIDI (match_operand:HIDI 1 "register_operand" "0,r,r")
1558 (match_operand 2 "immediate_operand" "n,n,n")))
1559 (clobber (match_operand:QI 3 "register_operand" "=<rotx>" ))]
1560 "(CONST_INT_P (operands[2]) &&
1561 (8 == (INTVAL (operands[2]) % 16)
1562 || (!AVR_HAVE_MOVW && 0 == (INTVAL (operands[2]) % 16))))"
1564 "&& (reload_completed || <MODE>mode == DImode)"
1566 "avr_rotate_bytes (operands);
1571 ;;<< << << << << << << << << << << << << << << << << << << << << << << << << <<
1572 ;; arithmetic shift left
1574 (define_expand "ashlqi3"
1575 [(set (match_operand:QI 0 "register_operand" "")
1576 (ashift:QI (match_operand:QI 1 "register_operand" "")
1577 (match_operand:QI 2 "general_operand" "")))]
1581 (define_split ; ashlqi3_const4
1582 [(set (match_operand:QI 0 "d_register_operand" "")
1583 (ashift:QI (match_dup 0)
1586 [(set (match_dup 0) (rotate:QI (match_dup 0) (const_int 4)))
1587 (set (match_dup 0) (and:QI (match_dup 0) (const_int -16)))]
1590 (define_split ; ashlqi3_const5
1591 [(set (match_operand:QI 0 "d_register_operand" "")
1592 (ashift:QI (match_dup 0)
1595 [(set (match_dup 0) (rotate:QI (match_dup 0) (const_int 4)))
1596 (set (match_dup 0) (ashift:QI (match_dup 0) (const_int 1)))
1597 (set (match_dup 0) (and:QI (match_dup 0) (const_int -32)))]
1600 (define_split ; ashlqi3_const6
1601 [(set (match_operand:QI 0 "d_register_operand" "")
1602 (ashift:QI (match_dup 0)
1605 [(set (match_dup 0) (rotate:QI (match_dup 0) (const_int 4)))
1606 (set (match_dup 0) (ashift:QI (match_dup 0) (const_int 2)))
1607 (set (match_dup 0) (and:QI (match_dup 0) (const_int -64)))]
1610 (define_insn "*ashlqi3"
1611 [(set (match_operand:QI 0 "register_operand" "=r,r,r,r,!d,r,r")
1612 (ashift:QI (match_operand:QI 1 "register_operand" "0,0,0,0,0,0,0")
1613 (match_operand:QI 2 "general_operand" "r,L,P,K,n,n,Qm")))]
1615 "* return ashlqi3_out (insn, operands, NULL);"
1616 [(set_attr "length" "5,0,1,2,4,6,9")
1617 (set_attr "cc" "clobber,none,set_czn,set_czn,set_czn,set_czn,clobber")])
1619 (define_insn "ashlhi3"
1620 [(set (match_operand:HI 0 "register_operand" "=r,r,r,r,r,r,r")
1621 (ashift:HI (match_operand:HI 1 "register_operand" "0,0,0,r,0,0,0")
1622 (match_operand:QI 2 "general_operand" "r,L,P,O,K,n,Qm")))]
1624 "* return ashlhi3_out (insn, operands, NULL);"
1625 [(set_attr "length" "6,0,2,2,4,10,10")
1626 (set_attr "cc" "clobber,none,set_n,clobber,set_n,clobber,clobber")])
1628 (define_insn "ashlsi3"
1629 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r,r,r,r")
1630 (ashift:SI (match_operand:SI 1 "register_operand" "0,0,0,r,0,0,0")
1631 (match_operand:QI 2 "general_operand" "r,L,P,O,K,n,Qm")))]
1633 "* return ashlsi3_out (insn, operands, NULL);"
1634 [(set_attr "length" "8,0,4,4,8,10,12")
1635 (set_attr "cc" "clobber,none,set_n,clobber,set_n,clobber,clobber")])
1637 ;; Optimize if a scratch register from LD_REGS happens to be available.
1639 (define_peephole2 ; ashlqi3_l_const4
1640 [(set (match_operand:QI 0 "l_register_operand" "")
1641 (ashift:QI (match_dup 0)
1643 (match_scratch:QI 1 "d")]
1645 [(set (match_dup 0) (rotate:QI (match_dup 0) (const_int 4)))
1646 (set (match_dup 1) (const_int -16))
1647 (set (match_dup 0) (and:QI (match_dup 0) (match_dup 1)))]
1650 (define_peephole2 ; ashlqi3_l_const5
1651 [(set (match_operand:QI 0 "l_register_operand" "")
1652 (ashift:QI (match_dup 0)
1654 (match_scratch:QI 1 "d")]
1656 [(set (match_dup 0) (rotate:QI (match_dup 0) (const_int 4)))
1657 (set (match_dup 0) (ashift:QI (match_dup 0) (const_int 1)))
1658 (set (match_dup 1) (const_int -32))
1659 (set (match_dup 0) (and:QI (match_dup 0) (match_dup 1)))]
1662 (define_peephole2 ; ashlqi3_l_const6
1663 [(set (match_operand:QI 0 "l_register_operand" "")
1664 (ashift:QI (match_dup 0)
1666 (match_scratch:QI 1 "d")]
1668 [(set (match_dup 0) (rotate:QI (match_dup 0) (const_int 4)))
1669 (set (match_dup 0) (ashift:QI (match_dup 0) (const_int 2)))
1670 (set (match_dup 1) (const_int -64))
1671 (set (match_dup 0) (and:QI (match_dup 0) (match_dup 1)))]
1675 [(match_scratch:QI 3 "d")
1676 (set (match_operand:HI 0 "register_operand" "")
1677 (ashift:HI (match_operand:HI 1 "register_operand" "")
1678 (match_operand:QI 2 "const_int_operand" "")))]
1680 [(parallel [(set (match_dup 0) (ashift:HI (match_dup 1) (match_dup 2)))
1681 (clobber (match_dup 3))])]
1684 (define_insn "*ashlhi3_const"
1685 [(set (match_operand:HI 0 "register_operand" "=r,r,r,r,r")
1686 (ashift:HI (match_operand:HI 1 "register_operand" "0,0,r,0,0")
1687 (match_operand:QI 2 "const_int_operand" "L,P,O,K,n")))
1688 (clobber (match_scratch:QI 3 "=X,X,X,X,&d"))]
1690 "* return ashlhi3_out (insn, operands, NULL);"
1691 [(set_attr "length" "0,2,2,4,10")
1692 (set_attr "cc" "none,set_n,clobber,set_n,clobber")])
1695 [(match_scratch:QI 3 "d")
1696 (set (match_operand:SI 0 "register_operand" "")
1697 (ashift:SI (match_operand:SI 1 "register_operand" "")
1698 (match_operand:QI 2 "const_int_operand" "")))]
1700 [(parallel [(set (match_dup 0) (ashift:SI (match_dup 1) (match_dup 2)))
1701 (clobber (match_dup 3))])]
1704 (define_insn "*ashlsi3_const"
1705 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r")
1706 (ashift:SI (match_operand:SI 1 "register_operand" "0,0,r,0")
1707 (match_operand:QI 2 "const_int_operand" "L,P,O,n")))
1708 (clobber (match_scratch:QI 3 "=X,X,X,&d"))]
1710 "* return ashlsi3_out (insn, operands, NULL);"
1711 [(set_attr "length" "0,4,4,10")
1712 (set_attr "cc" "none,set_n,clobber,clobber")])
1714 ;; >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >>
1715 ;; arithmetic shift right
1717 (define_insn "ashrqi3"
1718 [(set (match_operand:QI 0 "register_operand" "=r,r,r,r,r,r")
1719 (ashiftrt:QI (match_operand:QI 1 "register_operand" "0,0,0,0,0,0")
1720 (match_operand:QI 2 "general_operand" "r,L,P,K,n,Qm")))]
1722 "* return ashrqi3_out (insn, operands, NULL);"
1723 [(set_attr "length" "5,0,1,2,5,9")
1724 (set_attr "cc" "clobber,none,clobber,clobber,clobber,clobber")])
1726 (define_insn "ashrhi3"
1727 [(set (match_operand:HI 0 "register_operand" "=r,r,r,r,r,r,r")
1728 (ashiftrt:HI (match_operand:HI 1 "register_operand" "0,0,0,r,0,0,0")
1729 (match_operand:QI 2 "general_operand" "r,L,P,O,K,n,Qm")))]
1731 "* return ashrhi3_out (insn, operands, NULL);"
1732 [(set_attr "length" "6,0,2,4,4,10,10")
1733 (set_attr "cc" "clobber,none,clobber,set_n,clobber,clobber,clobber")])
1735 (define_insn "ashrsi3"
1736 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r,r,r,r")
1737 (ashiftrt:SI (match_operand:SI 1 "register_operand" "0,0,0,r,0,0,0")
1738 (match_operand:QI 2 "general_operand" "r,L,P,O,K,n,Qm")))]
1740 "* return ashrsi3_out (insn, operands, NULL);"
1741 [(set_attr "length" "8,0,4,6,8,10,12")
1742 (set_attr "cc" "clobber,none,clobber,set_n,clobber,clobber,clobber")])
1744 ;; Optimize if a scratch register from LD_REGS happens to be available.
1747 [(match_scratch:QI 3 "d")
1748 (set (match_operand:HI 0 "register_operand" "")
1749 (ashiftrt:HI (match_operand:HI 1 "register_operand" "")
1750 (match_operand:QI 2 "const_int_operand" "")))]
1752 [(parallel [(set (match_dup 0) (ashiftrt:HI (match_dup 1) (match_dup 2)))
1753 (clobber (match_dup 3))])]
1756 (define_insn "*ashrhi3_const"
1757 [(set (match_operand:HI 0 "register_operand" "=r,r,r,r,r")
1758 (ashiftrt:HI (match_operand:HI 1 "register_operand" "0,0,r,0,0")
1759 (match_operand:QI 2 "const_int_operand" "L,P,O,K,n")))
1760 (clobber (match_scratch:QI 3 "=X,X,X,X,&d"))]
1762 "* return ashrhi3_out (insn, operands, NULL);"
1763 [(set_attr "length" "0,2,4,4,10")
1764 (set_attr "cc" "none,clobber,set_n,clobber,clobber")])
1767 [(match_scratch:QI 3 "d")
1768 (set (match_operand:SI 0 "register_operand" "")
1769 (ashiftrt:SI (match_operand:SI 1 "register_operand" "")
1770 (match_operand:QI 2 "const_int_operand" "")))]
1772 [(parallel [(set (match_dup 0) (ashiftrt:SI (match_dup 1) (match_dup 2)))
1773 (clobber (match_dup 3))])]
1776 (define_insn "*ashrsi3_const"
1777 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r")
1778 (ashiftrt:SI (match_operand:SI 1 "register_operand" "0,0,r,0")
1779 (match_operand:QI 2 "const_int_operand" "L,P,O,n")))
1780 (clobber (match_scratch:QI 3 "=X,X,X,&d"))]
1782 "* return ashrsi3_out (insn, operands, NULL);"
1783 [(set_attr "length" "0,4,4,10")
1784 (set_attr "cc" "none,clobber,set_n,clobber")])
1786 ;; >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >>
1787 ;; logical shift right
1789 (define_expand "lshrqi3"
1790 [(set (match_operand:QI 0 "register_operand" "")
1791 (lshiftrt:QI (match_operand:QI 1 "register_operand" "")
1792 (match_operand:QI 2 "general_operand" "")))]
1796 (define_split ; lshrqi3_const4
1797 [(set (match_operand:QI 0 "d_register_operand" "")
1798 (lshiftrt:QI (match_dup 0)
1801 [(set (match_dup 0) (rotate:QI (match_dup 0) (const_int 4)))
1802 (set (match_dup 0) (and:QI (match_dup 0) (const_int 15)))]
1805 (define_split ; lshrqi3_const5
1806 [(set (match_operand:QI 0 "d_register_operand" "")
1807 (lshiftrt:QI (match_dup 0)
1810 [(set (match_dup 0) (rotate:QI (match_dup 0) (const_int 4)))
1811 (set (match_dup 0) (lshiftrt:QI (match_dup 0) (const_int 1)))
1812 (set (match_dup 0) (and:QI (match_dup 0) (const_int 7)))]
1815 (define_split ; lshrqi3_const6
1816 [(set (match_operand:QI 0 "d_register_operand" "")
1817 (lshiftrt:QI (match_dup 0)
1820 [(set (match_dup 0) (rotate:QI (match_dup 0) (const_int 4)))
1821 (set (match_dup 0) (lshiftrt:QI (match_dup 0) (const_int 2)))
1822 (set (match_dup 0) (and:QI (match_dup 0) (const_int 3)))]
1825 (define_insn "*lshrqi3"
1826 [(set (match_operand:QI 0 "register_operand" "=r,r,r,r,!d,r,r")
1827 (lshiftrt:QI (match_operand:QI 1 "register_operand" "0,0,0,0,0,0,0")
1828 (match_operand:QI 2 "general_operand" "r,L,P,K,n,n,Qm")))]
1830 "* return lshrqi3_out (insn, operands, NULL);"
1831 [(set_attr "length" "5,0,1,2,4,6,9")
1832 (set_attr "cc" "clobber,none,set_czn,set_czn,set_czn,set_czn,clobber")])
1834 (define_insn "lshrhi3"
1835 [(set (match_operand:HI 0 "register_operand" "=r,r,r,r,r,r,r")
1836 (lshiftrt:HI (match_operand:HI 1 "register_operand" "0,0,0,r,0,0,0")
1837 (match_operand:QI 2 "general_operand" "r,L,P,O,K,n,Qm")))]
1839 "* return lshrhi3_out (insn, operands, NULL);"
1840 [(set_attr "length" "6,0,2,2,4,10,10")
1841 (set_attr "cc" "clobber,none,clobber,clobber,clobber,clobber,clobber")])
1843 (define_insn "lshrsi3"
1844 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r,r,r,r")
1845 (lshiftrt:SI (match_operand:SI 1 "register_operand" "0,0,0,r,0,0,0")
1846 (match_operand:QI 2 "general_operand" "r,L,P,O,K,n,Qm")))]
1848 "* return lshrsi3_out (insn, operands, NULL);"
1849 [(set_attr "length" "8,0,4,4,8,10,12")
1850 (set_attr "cc" "clobber,none,clobber,clobber,clobber,clobber,clobber")])
1852 ;; Optimize if a scratch register from LD_REGS happens to be available.
1854 (define_peephole2 ; lshrqi3_l_const4
1855 [(set (match_operand:QI 0 "l_register_operand" "")
1856 (lshiftrt:QI (match_dup 0)
1858 (match_scratch:QI 1 "d")]
1860 [(set (match_dup 0) (rotate:QI (match_dup 0) (const_int 4)))
1861 (set (match_dup 1) (const_int 15))
1862 (set (match_dup 0) (and:QI (match_dup 0) (match_dup 1)))]
1865 (define_peephole2 ; lshrqi3_l_const5
1866 [(set (match_operand:QI 0 "l_register_operand" "")
1867 (lshiftrt:QI (match_dup 0)
1869 (match_scratch:QI 1 "d")]
1871 [(set (match_dup 0) (rotate:QI (match_dup 0) (const_int 4)))
1872 (set (match_dup 0) (lshiftrt:QI (match_dup 0) (const_int 1)))
1873 (set (match_dup 1) (const_int 7))
1874 (set (match_dup 0) (and:QI (match_dup 0) (match_dup 1)))]
1877 (define_peephole2 ; lshrqi3_l_const6
1878 [(set (match_operand:QI 0 "l_register_operand" "")
1879 (lshiftrt:QI (match_dup 0)
1881 (match_scratch:QI 1 "d")]
1883 [(set (match_dup 0) (rotate:QI (match_dup 0) (const_int 4)))
1884 (set (match_dup 0) (lshiftrt:QI (match_dup 0) (const_int 2)))
1885 (set (match_dup 1) (const_int 3))
1886 (set (match_dup 0) (and:QI (match_dup 0) (match_dup 1)))]
1890 [(match_scratch:QI 3 "d")
1891 (set (match_operand:HI 0 "register_operand" "")
1892 (lshiftrt:HI (match_operand:HI 1 "register_operand" "")
1893 (match_operand:QI 2 "const_int_operand" "")))]
1895 [(parallel [(set (match_dup 0) (lshiftrt:HI (match_dup 1) (match_dup 2)))
1896 (clobber (match_dup 3))])]
1899 (define_insn "*lshrhi3_const"
1900 [(set (match_operand:HI 0 "register_operand" "=r,r,r,r,r")
1901 (lshiftrt:HI (match_operand:HI 1 "register_operand" "0,0,r,0,0")
1902 (match_operand:QI 2 "const_int_operand" "L,P,O,K,n")))
1903 (clobber (match_scratch:QI 3 "=X,X,X,X,&d"))]
1905 "* return lshrhi3_out (insn, operands, NULL);"
1906 [(set_attr "length" "0,2,2,4,10")
1907 (set_attr "cc" "none,clobber,clobber,clobber,clobber")])
1910 [(match_scratch:QI 3 "d")
1911 (set (match_operand:SI 0 "register_operand" "")
1912 (lshiftrt:SI (match_operand:SI 1 "register_operand" "")
1913 (match_operand:QI 2 "const_int_operand" "")))]
1915 [(parallel [(set (match_dup 0) (lshiftrt:SI (match_dup 1) (match_dup 2)))
1916 (clobber (match_dup 3))])]
1919 (define_insn "*lshrsi3_const"
1920 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r")
1921 (lshiftrt:SI (match_operand:SI 1 "register_operand" "0,0,r,0")
1922 (match_operand:QI 2 "const_int_operand" "L,P,O,n")))
1923 (clobber (match_scratch:QI 3 "=X,X,X,&d"))]
1925 "* return lshrsi3_out (insn, operands, NULL);"
1926 [(set_attr "length" "0,4,4,10")
1927 (set_attr "cc" "none,clobber,clobber,clobber")])
1929 ;; abs(x) abs(x) abs(x) abs(x) abs(x) abs(x) abs(x) abs(x) abs(x) abs(x) abs(x)
1932 (define_insn "absqi2"
1933 [(set (match_operand:QI 0 "register_operand" "=r")
1934 (abs:QI (match_operand:QI 1 "register_operand" "0")))]
1938 [(set_attr "length" "2")
1939 (set_attr "cc" "clobber")])
1942 (define_insn "abssf2"
1943 [(set (match_operand:SF 0 "register_operand" "=d,r")
1944 (abs:SF (match_operand:SF 1 "register_operand" "0,0")))]
1949 [(set_attr "length" "1,2")
1950 (set_attr "cc" "set_n,clobber")])
1952 ;; 0 - x 0 - x 0 - x 0 - x 0 - x 0 - x 0 - x 0 - x 0 - x 0 - x 0 - x
1955 (define_insn "negqi2"
1956 [(set (match_operand:QI 0 "register_operand" "=r")
1957 (neg:QI (match_operand:QI 1 "register_operand" "0")))]
1960 [(set_attr "length" "1")
1961 (set_attr "cc" "set_zn")])
1963 (define_insn "neghi2"
1964 [(set (match_operand:HI 0 "register_operand" "=!d,r,&r")
1965 (neg:HI (match_operand:HI 1 "register_operand" "0,0,r")))]
1968 com %B0\;neg %A0\;sbci %B0,lo8(-1)
1969 com %B0\;neg %A0\;sbc %B0,__zero_reg__\;inc %B0
1970 clr %A0\;clr %B0\;sub %A0,%A1\;sbc %B0,%B1"
1971 [(set_attr "length" "3,4,4")
1972 (set_attr "cc" "set_czn,set_n,set_czn")])
1974 (define_insn "negsi2"
1975 [(set (match_operand:SI 0 "register_operand" "=!d,r,&r")
1976 (neg:SI (match_operand:SI 1 "register_operand" "0,0,r")))]
1979 com %D0\;com %C0\;com %B0\;neg %A0\;sbci %B0,lo8(-1)\;sbci %C0,lo8(-1)\;sbci %D0,lo8(-1)
1980 com %D0\;com %C0\;com %B0\;com %A0\;adc %A0,__zero_reg__\;adc %B0,__zero_reg__\;adc %C0,__zero_reg__\;adc %D0,__zero_reg__
1981 clr %A0\;clr %B0\;{clr %C0\;clr %D0|movw %C0,%A0}\;sub %A0,%A1\;sbc %B0,%B1\;sbc %C0,%C1\;sbc %D0,%D1"
1982 [(set_attr_alternative "length"
1985 (if_then_else (eq_attr "mcu_have_movw" "yes")
1988 (set_attr "cc" "set_czn,set_n,set_czn")])
1990 (define_insn "negsf2"
1991 [(set (match_operand:SF 0 "register_operand" "=d,r")
1992 (neg:SF (match_operand:SF 1 "register_operand" "0,0")))]
1996 bst %D0,7\;com %D0\;bld %D0,7\;com %D0"
1997 [(set_attr "length" "1,4")
1998 (set_attr "cc" "set_n,set_n")])
2000 ;; !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
2003 (define_insn "one_cmplqi2"
2004 [(set (match_operand:QI 0 "register_operand" "=r")
2005 (not:QI (match_operand:QI 1 "register_operand" "0")))]
2008 [(set_attr "length" "1")
2009 (set_attr "cc" "set_czn")])
2011 (define_insn "one_cmplhi2"
2012 [(set (match_operand:HI 0 "register_operand" "=r")
2013 (not:HI (match_operand:HI 1 "register_operand" "0")))]
2017 [(set_attr "length" "2")
2018 (set_attr "cc" "set_n")])
2020 (define_insn "one_cmplsi2"
2021 [(set (match_operand:SI 0 "register_operand" "=r")
2022 (not:SI (match_operand:SI 1 "register_operand" "0")))]
2028 [(set_attr "length" "4")
2029 (set_attr "cc" "set_n")])
2031 ;; xx<---x xx<---x xx<---x xx<---x xx<---x xx<---x xx<---x xx<---x xx<---x
2034 (define_insn "extendqihi2"
2035 [(set (match_operand:HI 0 "register_operand" "=r,r")
2036 (sign_extend:HI (match_operand:QI 1 "register_operand" "0,*r")))]
2039 clr %B0\;sbrc %0,7\;com %B0
2040 mov %A0,%A1\;clr %B0\;sbrc %A0,7\;com %B0"
2041 [(set_attr "length" "3,4")
2042 (set_attr "cc" "set_n,set_n")])
2044 (define_insn "extendqisi2"
2045 [(set (match_operand:SI 0 "register_operand" "=r,r")
2046 (sign_extend:SI (match_operand:QI 1 "register_operand" "0,*r")))]
2049 clr %B0\;sbrc %A0,7\;com %B0\;mov %C0,%B0\;mov %D0,%B0
2050 mov %A0,%A1\;clr %B0\;sbrc %A0,7\;com %B0\;mov %C0,%B0\;mov %D0,%B0"
2051 [(set_attr "length" "5,6")
2052 (set_attr "cc" "set_n,set_n")])
2054 (define_insn "extendhisi2"
2055 [(set (match_operand:SI 0 "register_operand" "=r,&r")
2056 (sign_extend:SI (match_operand:HI 1 "register_operand" "0,*r")))]
2059 clr %C0\;sbrc %B0,7\;com %C0\;mov %D0,%C0
2060 {mov %A0,%A1\;mov %B0,%B1|movw %A0,%A1}\;clr %C0\;sbrc %B0,7\;com %C0\;mov %D0,%C0"
2061 [(set_attr_alternative "length"
2063 (if_then_else (eq_attr "mcu_have_movw" "yes")
2066 (set_attr "cc" "set_n,set_n")])
2068 ;; xx<---x xx<---x xx<---x xx<---x xx<---x xx<---x xx<---x xx<---x xx<---x
2071 (define_insn_and_split "zero_extendqihi2"
2072 [(set (match_operand:HI 0 "register_operand" "=r")
2073 (zero_extend:HI (match_operand:QI 1 "register_operand" "r")))]
2077 [(set (match_dup 2) (match_dup 1))
2078 (set (match_dup 3) (const_int 0))]
2080 unsigned int low_off = subreg_lowpart_offset (QImode, HImode);
2081 unsigned int high_off = subreg_highpart_offset (QImode, HImode);
2083 operands[2] = simplify_gen_subreg (QImode, operands[0], HImode, low_off);
2084 operands[3] = simplify_gen_subreg (QImode, operands[0], HImode, high_off);
2087 (define_insn_and_split "zero_extendqisi2"
2088 [(set (match_operand:SI 0 "register_operand" "=r")
2089 (zero_extend:SI (match_operand:QI 1 "register_operand" "r")))]
2093 [(set (match_dup 2) (zero_extend:HI (match_dup 1)))
2094 (set (match_dup 3) (const_int 0))]
2096 unsigned int low_off = subreg_lowpart_offset (HImode, SImode);
2097 unsigned int high_off = subreg_highpart_offset (HImode, SImode);
2099 operands[2] = simplify_gen_subreg (HImode, operands[0], SImode, low_off);
2100 operands[3] = simplify_gen_subreg (HImode, operands[0], SImode, high_off);
2103 (define_insn_and_split "zero_extendhisi2"
2104 [(set (match_operand:SI 0 "register_operand" "=r")
2105 (zero_extend:SI (match_operand:HI 1 "register_operand" "r")))]
2109 [(set (match_dup 2) (match_dup 1))
2110 (set (match_dup 3) (const_int 0))]
2112 unsigned int low_off = subreg_lowpart_offset (HImode, SImode);
2113 unsigned int high_off = subreg_highpart_offset (HImode, SImode);
2115 operands[2] = simplify_gen_subreg (HImode, operands[0], SImode, low_off);
2116 operands[3] = simplify_gen_subreg (HImode, operands[0], SImode, high_off);
2119 (define_insn_and_split "zero_extendqidi2"
2120 [(set (match_operand:DI 0 "register_operand" "=r")
2121 (zero_extend:DI (match_operand:QI 1 "register_operand" "r")))]
2125 [(set (match_dup 2) (zero_extend:SI (match_dup 1)))
2126 (set (match_dup 3) (const_int 0))]
2128 unsigned int low_off = subreg_lowpart_offset (SImode, DImode);
2129 unsigned int high_off = subreg_highpart_offset (SImode, DImode);
2131 operands[2] = simplify_gen_subreg (SImode, operands[0], DImode, low_off);
2132 operands[3] = simplify_gen_subreg (SImode, operands[0], DImode, high_off);
2135 (define_insn_and_split "zero_extendhidi2"
2136 [(set (match_operand:DI 0 "register_operand" "=r")
2137 (zero_extend:DI (match_operand:HI 1 "register_operand" "r")))]
2141 [(set (match_dup 2) (zero_extend:SI (match_dup 1)))
2142 (set (match_dup 3) (const_int 0))]
2144 unsigned int low_off = subreg_lowpart_offset (SImode, DImode);
2145 unsigned int high_off = subreg_highpart_offset (SImode, DImode);
2147 operands[2] = simplify_gen_subreg (SImode, operands[0], DImode, low_off);
2148 operands[3] = simplify_gen_subreg (SImode, operands[0], DImode, high_off);
2151 (define_insn_and_split "zero_extendsidi2"
2152 [(set (match_operand:DI 0 "register_operand" "=r")
2153 (zero_extend:DI (match_operand:SI 1 "register_operand" "r")))]
2157 [(set (match_dup 2) (match_dup 1))
2158 (set (match_dup 3) (const_int 0))]
2160 unsigned int low_off = subreg_lowpart_offset (SImode, DImode);
2161 unsigned int high_off = subreg_highpart_offset (SImode, DImode);
2163 operands[2] = simplify_gen_subreg (SImode, operands[0], DImode, low_off);
2164 operands[3] = simplify_gen_subreg (SImode, operands[0], DImode, high_off);
2167 ;;<=><=><=><=><=><=><=><=><=><=><=><=><=><=><=><=><=><=><=><=><=><=><=><=><=>
2170 ; Optimize negated tests into reverse compare if overflow is undefined.
2171 (define_insn "*negated_tstqi"
2173 (compare (neg:QI (match_operand:QI 0 "register_operand" "r"))
2175 "(!flag_wrapv && !flag_trapv && flag_strict_overflow)"
2176 "cp __zero_reg__,%0"
2177 [(set_attr "cc" "compare")
2178 (set_attr "length" "1")])
2180 (define_insn "*reversed_tstqi"
2182 (compare (const_int 0)
2183 (match_operand:QI 0 "register_operand" "r")))]
2185 "cp __zero_reg__,%0"
2186 [(set_attr "cc" "compare")
2187 (set_attr "length" "2")])
2189 (define_insn "*negated_tsthi"
2191 (compare (neg:HI (match_operand:HI 0 "register_operand" "r"))
2193 "(!flag_wrapv && !flag_trapv && flag_strict_overflow)"
2194 "cp __zero_reg__,%A0
2195 cpc __zero_reg__,%B0"
2196 [(set_attr "cc" "compare")
2197 (set_attr "length" "2")])
2199 ;; Leave here the clobber used by the cmphi pattern for simplicity, even
2200 ;; though it is unused, because this pattern is synthesized by avr_reorg.
2201 (define_insn "*reversed_tsthi"
2203 (compare (const_int 0)
2204 (match_operand:HI 0 "register_operand" "r")))
2205 (clobber (match_scratch:QI 1 "=X"))]
2207 "cp __zero_reg__,%A0
2208 cpc __zero_reg__,%B0"
2209 [(set_attr "cc" "compare")
2210 (set_attr "length" "2")])
2212 (define_insn "*negated_tstsi"
2214 (compare (neg:SI (match_operand:SI 0 "register_operand" "r"))
2216 "(!flag_wrapv && !flag_trapv && flag_strict_overflow)"
2217 "cp __zero_reg__,%A0
2218 cpc __zero_reg__,%B0
2219 cpc __zero_reg__,%C0
2220 cpc __zero_reg__,%D0"
2221 [(set_attr "cc" "compare")
2222 (set_attr "length" "4")])
2224 (define_insn "*reversed_tstsi"
2226 (compare (const_int 0)
2227 (match_operand:SI 0 "register_operand" "r")))
2228 (clobber (match_scratch:QI 1 "=X"))]
2230 "cp __zero_reg__,%A0
2231 cpc __zero_reg__,%B0
2232 cpc __zero_reg__,%C0
2233 cpc __zero_reg__,%D0"
2234 [(set_attr "cc" "compare")
2235 (set_attr "length" "4")])
2238 (define_insn "*cmpqi"
2240 (compare (match_operand:QI 0 "register_operand" "r,r,d")
2241 (match_operand:QI 1 "nonmemory_operand" "L,r,i")))]
2247 [(set_attr "cc" "compare,compare,compare")
2248 (set_attr "length" "1,1,1")])
2250 (define_insn "*cmpqi_sign_extend"
2252 (compare (sign_extend:HI
2253 (match_operand:QI 0 "register_operand" "d"))
2254 (match_operand:HI 1 "const_int_operand" "n")))]
2255 "INTVAL (operands[1]) >= -128 && INTVAL (operands[1]) <= 127"
2257 [(set_attr "cc" "compare")
2258 (set_attr "length" "1")])
2260 (define_insn "*cmphi"
2262 (compare (match_operand:HI 0 "register_operand" "!w,r,r,d,d,r,r")
2263 (match_operand:HI 1 "nonmemory_operand" "L,L,r,M,i,M,i")))
2264 (clobber (match_scratch:QI 2 "=X,X,X,X,&d,&d,&d"))]
2267 switch (which_alternative)
2270 return out_tsthi (insn, operands[0], NULL);
2273 return (AS2 (cp,%A0,%A1) CR_TAB
2276 if (reg_unused_after (insn, operands[0])
2277 && INTVAL (operands[1]) >= 0 && INTVAL (operands[1]) <= 63
2278 && test_hard_reg_class (ADDW_REGS, operands[0]))
2279 return AS2 (sbiw,%0,%1);
2281 return (AS2 (cpi,%0,%1) CR_TAB
2282 AS2 (cpc,%B0,__zero_reg__));
2284 if (reg_unused_after (insn, operands[0]))
2285 return (AS2 (subi,%0,lo8(%1)) CR_TAB
2286 AS2 (sbci,%B0,hi8(%1)));
2288 return (AS2 (ldi, %2,hi8(%1)) CR_TAB
2289 AS2 (cpi, %A0,lo8(%1)) CR_TAB
2292 return (AS2 (ldi, %2,lo8(%1)) CR_TAB
2293 AS2 (cp, %A0,%2) CR_TAB
2294 AS2 (cpc, %B0,__zero_reg__));
2297 return (AS2 (ldi, %2,lo8(%1)) CR_TAB
2298 AS2 (cp, %A0,%2) CR_TAB
2299 AS2 (ldi, %2,hi8(%1)) CR_TAB
2304 [(set_attr "cc" "compare,compare,compare,compare,compare,compare,compare")
2305 (set_attr "length" "1,2,2,2,3,3,4")])
2308 (define_insn "*cmpsi"
2310 (compare (match_operand:SI 0 "register_operand" "r,r,d,d,r,r")
2311 (match_operand:SI 1 "nonmemory_operand" "L,r,M,i,M,i")))
2312 (clobber (match_scratch:QI 2 "=X,X,X,&d,&d,&d"))]
2315 switch (which_alternative)
2318 return out_tstsi (insn, operands[0], NULL);
2321 return (AS2 (cp,%A0,%A1) CR_TAB
2322 AS2 (cpc,%B0,%B1) CR_TAB
2323 AS2 (cpc,%C0,%C1) CR_TAB
2326 if (reg_unused_after (insn, operands[0])
2327 && INTVAL (operands[1]) >= 0 && INTVAL (operands[1]) <= 63
2328 && test_hard_reg_class (ADDW_REGS, operands[0]))
2329 return (AS2 (sbiw,%0,%1) CR_TAB
2330 AS2 (cpc,%C0,__zero_reg__) CR_TAB
2331 AS2 (cpc,%D0,__zero_reg__));
2333 return (AS2 (cpi,%A0,lo8(%1)) CR_TAB
2334 AS2 (cpc,%B0,__zero_reg__) CR_TAB
2335 AS2 (cpc,%C0,__zero_reg__) CR_TAB
2336 AS2 (cpc,%D0,__zero_reg__));
2338 if (reg_unused_after (insn, operands[0]))
2339 return (AS2 (subi,%A0,lo8(%1)) CR_TAB
2340 AS2 (sbci,%B0,hi8(%1)) CR_TAB
2341 AS2 (sbci,%C0,hlo8(%1)) CR_TAB
2342 AS2 (sbci,%D0,hhi8(%1)));
2344 return (AS2 (cpi, %A0,lo8(%1)) CR_TAB
2345 AS2 (ldi, %2,hi8(%1)) CR_TAB
2346 AS2 (cpc, %B0,%2) CR_TAB
2347 AS2 (ldi, %2,hlo8(%1)) CR_TAB
2348 AS2 (cpc, %C0,%2) CR_TAB
2349 AS2 (ldi, %2,hhi8(%1)) CR_TAB
2352 return (AS2 (ldi,%2,lo8(%1)) CR_TAB
2353 AS2 (cp,%A0,%2) CR_TAB
2354 AS2 (cpc,%B0,__zero_reg__) CR_TAB
2355 AS2 (cpc,%C0,__zero_reg__) CR_TAB
2356 AS2 (cpc,%D0,__zero_reg__));
2358 return (AS2 (ldi, %2,lo8(%1)) CR_TAB
2359 AS2 (cp, %A0,%2) CR_TAB
2360 AS2 (ldi, %2,hi8(%1)) CR_TAB
2361 AS2 (cpc, %B0,%2) CR_TAB
2362 AS2 (ldi, %2,hlo8(%1)) CR_TAB
2363 AS2 (cpc, %C0,%2) CR_TAB
2364 AS2 (ldi, %2,hhi8(%1)) CR_TAB
2369 [(set_attr "cc" "compare,compare,compare,compare,compare,compare")
2370 (set_attr "length" "4,4,4,7,5,8")])
2373 ;; ----------------------------------------------------------------------
2374 ;; JUMP INSTRUCTIONS
2375 ;; ----------------------------------------------------------------------
2376 ;; Conditional jump instructions
2378 (define_expand "cbranchsi4"
2379 [(parallel [(set (cc0)
2380 (compare (match_operand:SI 1 "register_operand" "")
2381 (match_operand:SI 2 "nonmemory_operand" "")))
2382 (clobber (match_scratch:QI 4 ""))])
2385 (match_operator 0 "ordered_comparison_operator" [(cc0)
2387 (label_ref (match_operand 3 "" ""))
2391 (define_expand "cbranchhi4"
2392 [(parallel [(set (cc0)
2393 (compare (match_operand:HI 1 "register_operand" "")
2394 (match_operand:HI 2 "nonmemory_operand" "")))
2395 (clobber (match_scratch:QI 4 ""))])
2398 (match_operator 0 "ordered_comparison_operator" [(cc0)
2400 (label_ref (match_operand 3 "" ""))
2404 (define_expand "cbranchqi4"
2406 (compare (match_operand:QI 1 "register_operand" "")
2407 (match_operand:QI 2 "nonmemory_operand" "")))
2410 (match_operator 0 "ordered_comparison_operator" [(cc0)
2412 (label_ref (match_operand 3 "" ""))
2417 ;; Test a single bit in a QI/HI/SImode register.
2418 ;; Combine will create zero extract patterns for single bit tests.
2419 ;; permit any mode in source pattern by using VOIDmode.
2421 (define_insn "*sbrx_branch<mode>"
2424 (match_operator 0 "eqne_operator"
2426 (match_operand:VOID 1 "register_operand" "r")
2428 (match_operand 2 "const_int_operand" "n"))
2430 (label_ref (match_operand 3 "" ""))
2433 "* return avr_out_sbxx_branch (insn, operands);"
2434 [(set (attr "length")
2435 (if_then_else (and (ge (minus (pc) (match_dup 3)) (const_int -2046))
2436 (le (minus (pc) (match_dup 3)) (const_int 2046)))
2438 (if_then_else (eq_attr "mcu_mega" "no")
2441 (set_attr "cc" "clobber")])
2443 ;; Same test based on Bitwise AND RTL. Keep this incase gcc changes patterns.
2444 ;; or for old peepholes.
2445 ;; Fixme - bitwise Mask will not work for DImode
2447 (define_insn "*sbrx_and_branch<mode>"
2450 (match_operator 0 "eqne_operator"
2452 (match_operand:QISI 1 "register_operand" "r")
2453 (match_operand:QISI 2 "single_one_operand" "n"))
2455 (label_ref (match_operand 3 "" ""))
2459 HOST_WIDE_INT bitnumber;
2460 bitnumber = exact_log2 (GET_MODE_MASK (<MODE>mode) & INTVAL (operands[2]));
2461 operands[2] = GEN_INT (bitnumber);
2462 return avr_out_sbxx_branch (insn, operands);
2464 [(set (attr "length")
2465 (if_then_else (and (ge (minus (pc) (match_dup 3)) (const_int -2046))
2466 (le (minus (pc) (match_dup 3)) (const_int 2046)))
2468 (if_then_else (eq_attr "mcu_mega" "no")
2471 (set_attr "cc" "clobber")])
2473 ;; Convert sign tests to bit 7/15/31 tests that match the above insns.
2475 [(set (cc0) (compare (match_operand:QI 0 "register_operand" "")
2477 (set (pc) (if_then_else (ge (cc0) (const_int 0))
2478 (label_ref (match_operand 1 "" ""))
2481 [(set (pc) (if_then_else (eq (zero_extract:HI (match_dup 0)
2485 (label_ref (match_dup 1))
2490 [(set (cc0) (compare (match_operand:QI 0 "register_operand" "")
2492 (set (pc) (if_then_else (lt (cc0) (const_int 0))
2493 (label_ref (match_operand 1 "" ""))
2496 [(set (pc) (if_then_else (ne (zero_extract:HI (match_dup 0)
2500 (label_ref (match_dup 1))
2505 [(parallel [(set (cc0) (compare (match_operand:HI 0 "register_operand" "")
2507 (clobber (match_operand:HI 2 ""))])
2508 (set (pc) (if_then_else (ge (cc0) (const_int 0))
2509 (label_ref (match_operand 1 "" ""))
2512 [(set (pc) (if_then_else (eq (and:HI (match_dup 0) (const_int -32768))
2514 (label_ref (match_dup 1))
2519 [(parallel [(set (cc0) (compare (match_operand:HI 0 "register_operand" "")
2521 (clobber (match_operand:HI 2 ""))])
2522 (set (pc) (if_then_else (lt (cc0) (const_int 0))
2523 (label_ref (match_operand 1 "" ""))
2526 [(set (pc) (if_then_else (ne (and:HI (match_dup 0) (const_int -32768))
2528 (label_ref (match_dup 1))
2533 [(parallel [(set (cc0) (compare (match_operand:SI 0 "register_operand" "")
2535 (clobber (match_operand:SI 2 ""))])
2536 (set (pc) (if_then_else (ge (cc0) (const_int 0))
2537 (label_ref (match_operand 1 "" ""))
2540 [(set (pc) (if_then_else (eq (and:SI (match_dup 0) (match_dup 2))
2542 (label_ref (match_dup 1))
2544 "operands[2] = GEN_INT (-2147483647 - 1);")
2547 [(parallel [(set (cc0) (compare (match_operand:SI 0 "register_operand" "")
2549 (clobber (match_operand:SI 2 ""))])
2550 (set (pc) (if_then_else (lt (cc0) (const_int 0))
2551 (label_ref (match_operand 1 "" ""))
2554 [(set (pc) (if_then_else (ne (and:SI (match_dup 0) (match_dup 2))
2556 (label_ref (match_dup 1))
2558 "operands[2] = GEN_INT (-2147483647 - 1);")
2560 ;; ************************************************************************
2561 ;; Implementation of conditional jumps here.
2562 ;; Compare with 0 (test) jumps
2563 ;; ************************************************************************
2565 (define_insn "branch"
2567 (if_then_else (match_operator 1 "simple_comparison_operator"
2570 (label_ref (match_operand 0 "" ""))
2574 return ret_cond_branch (operands[1], avr_jump_mode (operands[0],insn), 0);"
2575 [(set_attr "type" "branch")
2576 (set_attr "cc" "clobber")])
2578 ;; ****************************************************************
2579 ;; AVR does not have following conditional jumps: LE,LEU,GT,GTU.
2580 ;; Convert them all to proper jumps.
2581 ;; ****************************************************************/
2583 (define_insn "difficult_branch"
2585 (if_then_else (match_operator 1 "difficult_comparison_operator"
2588 (label_ref (match_operand 0 "" ""))
2592 return ret_cond_branch (operands[1], avr_jump_mode (operands[0],insn), 0);"
2593 [(set_attr "type" "branch1")
2594 (set_attr "cc" "clobber")])
2598 (define_insn "rvbranch"
2600 (if_then_else (match_operator 1 "simple_comparison_operator"
2604 (label_ref (match_operand 0 "" ""))))]
2607 return ret_cond_branch (operands[1], avr_jump_mode (operands[0], insn), 1);"
2608 [(set_attr "type" "branch1")
2609 (set_attr "cc" "clobber")])
2611 (define_insn "difficult_rvbranch"
2613 (if_then_else (match_operator 1 "difficult_comparison_operator"
2617 (label_ref (match_operand 0 "" ""))))]
2620 return ret_cond_branch (operands[1], avr_jump_mode (operands[0], insn), 1);"
2621 [(set_attr "type" "branch")
2622 (set_attr "cc" "clobber")])
2624 ;; **************************************************************************
2625 ;; Unconditional and other jump instructions.
2629 (label_ref (match_operand 0 "" "")))]
2632 if (AVR_HAVE_JMP_CALL && get_attr_length (insn) != 1)
2633 return AS1 (jmp,%x0);
2634 return AS1 (rjmp,%x0);
2636 [(set (attr "length")
2637 (if_then_else (match_operand 0 "symbol_ref_operand" "")
2638 (if_then_else (eq_attr "mcu_mega" "no")
2641 (if_then_else (and (ge (minus (pc) (match_dup 0)) (const_int -2047))
2642 (le (minus (pc) (match_dup 0)) (const_int 2047)))
2645 (set_attr "cc" "none")])
2649 (define_expand "call"
2650 [(call (match_operand:HI 0 "call_insn_operand" "")
2651 (match_operand:HI 1 "general_operand" ""))]
2652 ;; Operand 1 not used on the AVR.
2658 (define_expand "call_value"
2659 [(set (match_operand 0 "register_operand" "")
2660 (call (match_operand:HI 1 "call_insn_operand" "")
2661 (match_operand:HI 2 "general_operand" "")))]
2662 ;; Operand 2 not used on the AVR.
2666 (define_insn "call_insn"
2667 [(call (mem:HI (match_operand:HI 0 "nonmemory_operand" "!z,*r,s,n"))
2668 (match_operand:HI 1 "general_operand" "X,X,X,X"))]
2669 ;; We don't need in saving Z register because r30,r31 is a call used registers
2670 ;; Operand 1 not used on the AVR.
2671 "(register_operand (operands[0], HImode) || CONSTANT_P (operands[0]))"
2673 if (which_alternative==0)
2675 else if (which_alternative==1)
2678 return (AS2 (movw, r30, %0) CR_TAB
2681 return (AS2 (mov, r30, %A0) CR_TAB
2682 AS2 (mov, r31, %B0) CR_TAB
2685 else if (which_alternative==2)
2686 return AS1(%~call,%x0);
2687 return (AS2 (ldi,r30,lo8(%0)) CR_TAB
2688 AS2 (ldi,r31,hi8(%0)) CR_TAB
2691 [(set_attr "cc" "clobber,clobber,clobber,clobber")
2692 (set_attr_alternative "length"
2694 (if_then_else (eq_attr "mcu_have_movw" "yes")
2697 (if_then_else (eq_attr "mcu_mega" "yes")
2702 (define_insn "call_value_insn"
2703 [(set (match_operand 0 "register_operand" "=r,r,r,r")
2704 (call (mem:HI (match_operand:HI 1 "nonmemory_operand" "!z,*r,s,n"))
2705 ;; We don't need in saving Z register because r30,r31 is a call used registers
2706 (match_operand:HI 2 "general_operand" "X,X,X,X")))]
2707 ;; Operand 2 not used on the AVR.
2708 "(register_operand (operands[0], VOIDmode) || CONSTANT_P (operands[0]))"
2710 if (which_alternative==0)
2712 else if (which_alternative==1)
2715 return (AS2 (movw, r30, %1) CR_TAB
2718 return (AS2 (mov, r30, %A1) CR_TAB
2719 AS2 (mov, r31, %B1) CR_TAB
2722 else if (which_alternative==2)
2723 return AS1(%~call,%x1);
2724 return (AS2 (ldi, r30, lo8(%1)) CR_TAB
2725 AS2 (ldi, r31, hi8(%1)) CR_TAB
2728 [(set_attr "cc" "clobber,clobber,clobber,clobber")
2729 (set_attr_alternative "length"
2731 (if_then_else (eq_attr "mcu_have_movw" "yes")
2734 (if_then_else (eq_attr "mcu_mega" "yes")
2743 [(set_attr "cc" "none")
2744 (set_attr "length" "1")])
2748 (define_expand "indirect_jump"
2749 [(set (pc) (match_operand:HI 0 "nonmemory_operand" ""))]
2751 " if ((!AVR_HAVE_JMP_CALL) && !register_operand(operand0, HImode))
2753 operands[0] = copy_to_mode_reg(HImode, operand0);
2758 (define_insn "*jcindirect_jump"
2759 [(set (pc) (match_operand:HI 0 "immediate_operand" "i"))]
2763 [(set_attr "length" "2")
2764 (set_attr "cc" "none")])
2767 (define_insn "*njcindirect_jump"
2768 [(set (pc) (match_operand:HI 0 "register_operand" "!z,*r"))]
2769 "!AVR_HAVE_EIJMP_EICALL"
2772 push %A0\;push %B0\;ret"
2773 [(set_attr "length" "1,3")
2774 (set_attr "cc" "none,none")])
2776 (define_insn "*indirect_jump_avr6"
2777 [(set (pc) (match_operand:HI 0 "register_operand" "z"))]
2778 "AVR_HAVE_EIJMP_EICALL"
2780 [(set_attr "length" "1")
2781 (set_attr "cc" "none")])
2785 ;; Table made from "rjmp" instructions for <=8K devices.
2786 (define_insn "*tablejump_rjmp"
2787 [(set (pc) (unspec:HI [(match_operand:HI 0 "register_operand" "!z,*r")]
2789 (use (label_ref (match_operand 1 "" "")))
2790 (clobber (match_dup 0))]
2791 "(!AVR_HAVE_JMP_CALL) && (!AVR_HAVE_EIJMP_EICALL)"
2794 push %A0\;push %B0\;ret"
2795 [(set_attr "length" "1,3")
2796 (set_attr "cc" "none,none")])
2798 ;; Not a prologue, but similar idea - move the common piece of code to libgcc.
2799 (define_insn "*tablejump_lib"
2800 [(set (pc) (unspec:HI [(match_operand:HI 0 "register_operand" "z")]
2802 (use (label_ref (match_operand 1 "" "")))
2803 (clobber (match_dup 0))]
2804 "AVR_HAVE_JMP_CALL && TARGET_CALL_PROLOGUES"
2805 "%~jmp __tablejump2__"
2806 [(set_attr "length" "2")
2807 (set_attr "cc" "clobber")])
2809 (define_insn "*tablejump_enh"
2810 [(set (pc) (unspec:HI [(match_operand:HI 0 "register_operand" "z")]
2812 (use (label_ref (match_operand 1 "" "")))
2813 (clobber (match_dup 0))]
2814 "AVR_HAVE_JMP_CALL && AVR_HAVE_LPMX"
2821 [(set_attr "length" "6")
2822 (set_attr "cc" "clobber")])
2824 (define_insn "*tablejump"
2825 [(set (pc) (unspec:HI [(match_operand:HI 0 "register_operand" "z")]
2827 (use (label_ref (match_operand 1 "" "")))
2828 (clobber (match_dup 0))]
2829 "AVR_HAVE_JMP_CALL && !AVR_HAVE_EIJMP_EICALL"
2838 [(set_attr "length" "8")
2839 (set_attr "cc" "clobber")])
2841 (define_expand "casesi"
2843 (minus:HI (subreg:HI (match_operand:SI 0 "register_operand" "") 0)
2844 (match_operand:HI 1 "register_operand" "")))
2845 (parallel [(set (cc0)
2846 (compare (match_dup 6)
2847 (match_operand:HI 2 "register_operand" "")))
2848 (clobber (match_scratch:QI 9 ""))])
2851 (if_then_else (gtu (cc0)
2853 (label_ref (match_operand 4 "" ""))
2857 (plus:HI (match_dup 6) (label_ref (match_operand:HI 3 "" ""))))
2859 (parallel [(set (pc) (unspec:HI [(match_dup 6)] UNSPEC_INDEX_JMP))
2860 (use (label_ref (match_dup 3)))
2861 (clobber (match_dup 6))])]
2865 operands[6] = gen_reg_rtx (HImode);
2869 ;; ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
2870 ;; This instruction sets Z flag
2873 [(set (cc0) (const_int 0))]
2876 [(set_attr "length" "1")
2877 (set_attr "cc" "compare")])
2879 ;; Clear/set/test a single bit in I/O address space.
2882 [(set (mem:QI (match_operand 0 "low_io_address_operand" "n"))
2883 (and:QI (mem:QI (match_dup 0))
2884 (match_operand:QI 1 "single_zero_operand" "n")))]
2887 operands[2] = GEN_INT (exact_log2 (~INTVAL (operands[1]) & 0xff));
2888 return AS2 (cbi,%m0-0x20,%2);
2890 [(set_attr "length" "1")
2891 (set_attr "cc" "none")])
2894 [(set (mem:QI (match_operand 0 "low_io_address_operand" "n"))
2895 (ior:QI (mem:QI (match_dup 0))
2896 (match_operand:QI 1 "single_one_operand" "n")))]
2899 operands[2] = GEN_INT (exact_log2 (INTVAL (operands[1]) & 0xff));
2900 return AS2 (sbi,%m0-0x20,%2);
2902 [(set_attr "length" "1")
2903 (set_attr "cc" "none")])
2905 ;; Lower half of the I/O space - use sbic/sbis directly.
2906 (define_insn "*sbix_branch"
2909 (match_operator 0 "eqne_operator"
2911 (mem:QI (match_operand 1 "low_io_address_operand" "n"))
2913 (match_operand 2 "const_int_operand" "n"))
2915 (label_ref (match_operand 3 "" ""))
2918 "* return avr_out_sbxx_branch (insn, operands);"
2919 [(set (attr "length")
2920 (if_then_else (and (ge (minus (pc) (match_dup 3)) (const_int -2046))
2921 (le (minus (pc) (match_dup 3)) (const_int 2046)))
2923 (if_then_else (eq_attr "mcu_mega" "no")
2926 (set_attr "cc" "clobber")])
2928 ;; Tests of bit 7 are pessimized to sign tests, so we need this too...
2929 (define_insn "*sbix_branch_bit7"
2932 (match_operator 0 "gelt_operator"
2933 [(mem:QI (match_operand 1 "low_io_address_operand" "n"))
2935 (label_ref (match_operand 2 "" ""))
2939 operands[3] = operands[2];
2940 operands[2] = GEN_INT (7);
2941 return avr_out_sbxx_branch (insn, operands);
2943 [(set (attr "length")
2944 (if_then_else (and (ge (minus (pc) (match_dup 2)) (const_int -2046))
2945 (le (minus (pc) (match_dup 2)) (const_int 2046)))
2947 (if_then_else (eq_attr "mcu_mega" "no")
2950 (set_attr "cc" "clobber")])
2952 ;; Upper half of the I/O space - read port to __tmp_reg__ and use sbrc/sbrs.
2953 (define_insn "*sbix_branch_tmp"
2956 (match_operator 0 "eqne_operator"
2958 (mem:QI (match_operand 1 "high_io_address_operand" "n"))
2960 (match_operand 2 "const_int_operand" "n"))
2962 (label_ref (match_operand 3 "" ""))
2965 "* return avr_out_sbxx_branch (insn, operands);"
2966 [(set (attr "length")
2967 (if_then_else (and (ge (minus (pc) (match_dup 3)) (const_int -2046))
2968 (le (minus (pc) (match_dup 3)) (const_int 2045)))
2970 (if_then_else (eq_attr "mcu_mega" "no")
2973 (set_attr "cc" "clobber")])
2975 (define_insn "*sbix_branch_tmp_bit7"
2978 (match_operator 0 "gelt_operator"
2979 [(mem:QI (match_operand 1 "high_io_address_operand" "n"))
2981 (label_ref (match_operand 2 "" ""))
2985 operands[3] = operands[2];
2986 operands[2] = GEN_INT (7);
2987 return avr_out_sbxx_branch (insn, operands);
2989 [(set (attr "length")
2990 (if_then_else (and (ge (minus (pc) (match_dup 2)) (const_int -2046))
2991 (le (minus (pc) (match_dup 2)) (const_int 2045)))
2993 (if_then_else (eq_attr "mcu_mega" "no")
2996 (set_attr "cc" "clobber")])
2998 ;; ************************* Peepholes ********************************
3001 [(set (match_operand:SI 0 "d_register_operand" "")
3002 (plus:SI (match_dup 0)
3006 (compare (match_dup 0)
3008 (clobber (match_operand:QI 1 "d_register_operand" ""))])
3010 (if_then_else (ne (cc0) (const_int 0))
3011 (label_ref (match_operand 2 "" ""))
3017 if (test_hard_reg_class (ADDW_REGS, operands[0]))
3018 output_asm_insn (AS2 (sbiw,%0,1) CR_TAB
3019 AS2 (sbc,%C0,__zero_reg__) CR_TAB
3020 AS2 (sbc,%D0,__zero_reg__) \"\\n\", operands);
3022 output_asm_insn (AS2 (subi,%A0,1) CR_TAB
3023 AS2 (sbc,%B0,__zero_reg__) CR_TAB
3024 AS2 (sbc,%C0,__zero_reg__) CR_TAB
3025 AS2 (sbc,%D0,__zero_reg__) \"\\n\", operands);
3026 switch (avr_jump_mode (operands[2],insn))
3029 return AS1 (brcc,%2);
3031 return (AS1 (brcs,.+2) CR_TAB
3034 return (AS1 (brcs,.+4) CR_TAB
3039 [(set (match_operand:HI 0 "d_register_operand" "")
3040 (plus:HI (match_dup 0)
3044 (compare (match_dup 0)
3046 (clobber (match_operand:QI 1 "d_register_operand" ""))])
3048 (if_then_else (ne (cc0) (const_int 0))
3049 (label_ref (match_operand 2 "" ""))
3055 if (test_hard_reg_class (ADDW_REGS, operands[0]))
3056 output_asm_insn (AS2 (sbiw,%0,1), operands);
3058 output_asm_insn (AS2 (subi,%A0,1) CR_TAB
3059 AS2 (sbc,%B0,__zero_reg__) \"\\n\", operands);
3060 switch (avr_jump_mode (operands[2],insn))
3063 return AS1 (brcc,%2);
3065 return (AS1 (brcs,.+2) CR_TAB
3068 return (AS1 (brcs,.+4) CR_TAB
3073 [(set (match_operand:QI 0 "d_register_operand" "")
3074 (plus:QI (match_dup 0)
3077 (compare (match_dup 0)
3080 (if_then_else (ne (cc0) (const_int 0))
3081 (label_ref (match_operand 1 "" ""))
3087 cc_status.value1 = operands[0];
3088 cc_status.flags |= CC_OVERFLOW_UNUSABLE;
3089 output_asm_insn (AS2 (subi,%A0,1), operands);
3090 switch (avr_jump_mode (operands[1],insn))
3093 return AS1 (brcc,%1);
3095 return (AS1 (brcs,.+2) CR_TAB
3098 return (AS1 (brcs,.+4) CR_TAB
3104 (compare (match_operand:QI 0 "register_operand" "")
3107 (if_then_else (eq (cc0) (const_int 0))
3108 (label_ref (match_operand 1 "" ""))
3110 "jump_over_one_insn_p (insn, operands[1])"
3111 "cpse %0,__zero_reg__")
3115 (compare (match_operand:QI 0 "register_operand" "")
3116 (match_operand:QI 1 "register_operand" "")))
3118 (if_then_else (eq (cc0) (const_int 0))
3119 (label_ref (match_operand 2 "" ""))
3121 "jump_over_one_insn_p (insn, operands[2])"
3124 ;;pppppppppppppppppppppppppppppppppppppppppppppppppppp
3125 ;;prologue/epilogue support instructions
3127 (define_insn "popqi"
3128 [(set (match_operand:QI 0 "register_operand" "=r")
3129 (mem:QI (post_inc (reg:HI REG_SP))))]
3132 [(set_attr "cc" "none")
3133 (set_attr "length" "1")])
3135 (define_insn "pophi"
3136 [(set (match_operand:HI 0 "register_operand" "=r")
3137 (mem:HI (post_inc (reg:HI REG_SP))))]
3140 [(set_attr "cc" "none")
3141 (set_attr "length" "2")])
3143 ;; Enable Interrupts
3144 (define_insn "enable_interrupt"
3145 [(unspec [(const_int 0)] UNSPEC_SEI)]
3148 [(set_attr "length" "1")
3149 (set_attr "cc" "none")
3152 ;; Disable Interrupts
3153 (define_insn "disable_interrupt"
3154 [(unspec [(const_int 0)] UNSPEC_CLI)]
3157 [(set_attr "length" "1")
3158 (set_attr "cc" "none")
3161 ;; Library prologue saves
3162 (define_insn "call_prologue_saves"
3163 [(unspec_volatile:HI [(const_int 0)] UNSPECV_PROLOGUE_SAVES)
3164 (match_operand:HI 0 "immediate_operand" "")
3165 (set (reg:HI REG_SP) (minus:HI
3167 (match_operand:HI 1 "immediate_operand" "")))
3168 (use (reg:HI REG_X))
3169 (clobber (reg:HI REG_Z))]
3171 "ldi r30,lo8(gs(1f))
3173 %~jmp __prologue_saves__+((18 - %0) * 2)
3175 [(set_attr_alternative "length"
3176 [(if_then_else (eq_attr "mcu_mega" "yes")
3179 (set_attr "cc" "clobber")
3182 ; epilogue restores using library
3183 (define_insn "epilogue_restores"
3184 [(unspec_volatile:QI [(const_int 0)] UNSPECV_EPILOGUE_RESTORES)
3185 (set (reg:HI REG_Y ) (plus:HI
3187 (match_operand:HI 0 "immediate_operand" "")))
3188 (set (reg:HI REG_SP) (reg:HI REG_Y))
3189 (clobber (reg:QI REG_Z))]
3192 %~jmp __epilogue_restores__ + ((18 - %0) * 2)"
3193 [(set_attr_alternative "length"
3194 [(if_then_else (eq_attr "mcu_mega" "yes")
3197 (set_attr "cc" "clobber")
3201 (define_insn "return"
3203 "reload_completed && avr_simple_epilogue ()"
3205 [(set_attr "cc" "none")
3206 (set_attr "length" "1")])
3208 (define_insn "return_from_epilogue"
3212 && !(cfun->machine->is_interrupt || cfun->machine->is_signal)
3213 && !cfun->machine->is_naked)"
3215 [(set_attr "cc" "none")
3216 (set_attr "length" "1")])
3218 (define_insn "return_from_interrupt_epilogue"
3222 && (cfun->machine->is_interrupt || cfun->machine->is_signal)
3223 && !cfun->machine->is_naked)"
3225 [(set_attr "cc" "none")
3226 (set_attr "length" "1")])
3228 (define_insn "return_from_naked_epilogue"
3232 && cfun->machine->is_naked)"
3234 [(set_attr "cc" "none")
3235 (set_attr "length" "0")])
3237 (define_expand "prologue"
3246 (define_expand "epilogue"