1 ;; Predicate definitions for ARM and Thumb
2 ;; Copyright (C) 2004, 2007 Free Software Foundation, Inc.
3 ;; Contributed by ARM Ltd.
5 ;; This file is part of GCC.
7 ;; GCC is free software; you can redistribute it and/or modify it
8 ;; under the terms of the GNU General Public License as published
9 ;; by the Free Software Foundation; either version 3, or (at your
10 ;; option) any later version.
12 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
13 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 ;; License for more details.
17 ;; You should have received a copy of the GNU General Public License
18 ;; along with GCC; see the file COPYING3. If not see
19 ;; <http://www.gnu.org/licenses/>.
21 (define_predicate "s_register_operand"
22 (match_code "reg,subreg")
24 if (GET_CODE (op) == SUBREG)
26 /* We don't consider registers whose class is NO_REGS
27 to be a register operand. */
28 /* XXX might have to check for lo regs only for thumb ??? */
29 return (GET_CODE (op) == REG
30 && (REGNO (op) >= FIRST_PSEUDO_REGISTER
31 || REGNO_REG_CLASS (REGNO (op)) != NO_REGS));
35 (define_predicate "arm_hard_register_operand"
38 return REGNO (op) < FIRST_PSEUDO_REGISTER;
42 (define_predicate "low_register_operand"
43 (and (match_code "reg")
44 (match_test "REGNO (op) <= LAST_LO_REGNUM")))
46 ;; A low register or const_int.
47 (define_predicate "low_reg_or_int_operand"
48 (ior (match_code "const_int")
49 (match_operand 0 "low_register_operand")))
51 ;; Any core register, or any pseudo. */
52 (define_predicate "arm_general_register_operand"
53 (match_code "reg,subreg")
55 if (GET_CODE (op) == SUBREG)
58 return (GET_CODE (op) == REG
59 && (REGNO (op) <= LAST_ARM_REGNUM
60 || REGNO (op) >= FIRST_PSEUDO_REGISTER));
63 (define_predicate "f_register_operand"
64 (match_code "reg,subreg")
66 if (GET_CODE (op) == SUBREG)
69 /* We don't consider registers whose class is NO_REGS
70 to be a register operand. */
71 return (GET_CODE (op) == REG
72 && (REGNO (op) >= FIRST_PSEUDO_REGISTER
73 || REGNO_REG_CLASS (REGNO (op)) == FPA_REGS));
76 ;; Reg, subreg(reg) or const_int.
77 (define_predicate "reg_or_int_operand"
78 (ior (match_code "const_int")
79 (match_operand 0 "s_register_operand")))
81 (define_predicate "arm_immediate_operand"
82 (and (match_code "const_int")
83 (match_test "const_ok_for_arm (INTVAL (op))")))
85 (define_predicate "arm_neg_immediate_operand"
86 (and (match_code "const_int")
87 (match_test "const_ok_for_arm (-INTVAL (op))")))
89 (define_predicate "arm_not_immediate_operand"
90 (and (match_code "const_int")
91 (match_test "const_ok_for_arm (~INTVAL (op))")))
93 ;; Something valid on the RHS of an ARM data-processing instruction
94 (define_predicate "arm_rhs_operand"
95 (ior (match_operand 0 "s_register_operand")
96 (match_operand 0 "arm_immediate_operand")))
98 (define_predicate "arm_rhsm_operand"
99 (ior (match_operand 0 "arm_rhs_operand")
100 (match_operand 0 "memory_operand")))
102 (define_predicate "arm_add_operand"
103 (ior (match_operand 0 "arm_rhs_operand")
104 (match_operand 0 "arm_neg_immediate_operand")))
106 (define_predicate "arm_addimm_operand"
107 (ior (match_operand 0 "arm_immediate_operand")
108 (match_operand 0 "arm_neg_immediate_operand")))
110 (define_predicate "arm_not_operand"
111 (ior (match_operand 0 "arm_rhs_operand")
112 (match_operand 0 "arm_not_immediate_operand")))
114 ;; True if the operand is a memory reference which contains an
115 ;; offsettable address.
116 (define_predicate "offsettable_memory_operand"
117 (and (match_code "mem")
119 "offsettable_address_p (reload_completed | reload_in_progress,
120 mode, XEXP (op, 0))")))
122 ;; True if the operand is a memory operand that does not have an
123 ;; automodified base register (and thus will not generate output reloads).
124 (define_predicate "call_memory_operand"
125 (and (match_code "mem")
126 (and (match_test "GET_RTX_CLASS (GET_CODE (XEXP (op, 0)))
128 (match_operand 0 "memory_operand"))))
130 (define_predicate "arm_reload_memory_operand"
131 (and (match_code "mem,reg,subreg")
132 (match_test "(!CONSTANT_P (op)
133 && (true_regnum(op) == -1
134 || (GET_CODE (op) == REG
135 && REGNO (op) >= FIRST_PSEUDO_REGISTER)))")))
137 ;; True for valid operands for the rhs of an floating point insns.
138 ;; Allows regs or certain consts on FPA, just regs for everything else.
139 (define_predicate "arm_float_rhs_operand"
140 (ior (match_operand 0 "s_register_operand")
141 (and (match_code "const_double")
142 (match_test "TARGET_FPA && arm_const_double_rtx (op)"))))
144 (define_predicate "arm_float_add_operand"
145 (ior (match_operand 0 "arm_float_rhs_operand")
146 (and (match_code "const_double")
147 (match_test "TARGET_FPA && neg_const_double_rtx_ok_for_fpa (op)"))))
149 (define_predicate "vfp_compare_operand"
150 (ior (match_operand 0 "s_register_operand")
151 (and (match_code "const_double")
152 (match_test "arm_const_double_rtx (op)"))))
154 (define_predicate "arm_float_compare_operand"
155 (if_then_else (match_test "TARGET_VFP")
156 (match_operand 0 "vfp_compare_operand")
157 (match_operand 0 "arm_float_rhs_operand")))
159 ;; True for valid index operands.
160 (define_predicate "index_operand"
161 (ior (match_operand 0 "s_register_operand")
162 (and (match_operand 0 "immediate_operand")
163 (match_test "(GET_CODE (op) != CONST_INT
164 || (INTVAL (op) < 4096 && INTVAL (op) > -4096))"))))
166 ;; True for operators that can be combined with a shift in ARM state.
167 (define_special_predicate "shiftable_operator"
168 (and (match_code "plus,minus,ior,xor,and")
169 (match_test "mode == GET_MODE (op)")))
171 ;; True for logical binary operators.
172 (define_special_predicate "logical_binary_operator"
173 (and (match_code "ior,xor,and")
174 (match_test "mode == GET_MODE (op)")))
176 ;; True for shift operators.
177 (define_special_predicate "shift_operator"
178 (and (ior (ior (and (match_code "mult")
179 (match_test "power_of_two_operand (XEXP (op, 1), mode)"))
180 (and (match_code "rotate")
181 (match_test "GET_CODE (XEXP (op, 1)) == CONST_INT
182 && ((unsigned HOST_WIDE_INT) INTVAL (XEXP (op, 1))) < 32")))
183 (match_code "ashift,ashiftrt,lshiftrt,rotatert"))
184 (match_test "mode == GET_MODE (op)")))
186 ;; True for operators that have 16-bit thumb variants. */
187 (define_special_predicate "thumb_16bit_operator"
188 (match_code "plus,minus,and,ior,xor"))
191 (define_special_predicate "equality_operator"
192 (match_code "eq,ne"))
194 ;; True for comparisons other than LTGT or UNEQ.
195 (define_special_predicate "arm_comparison_operator"
196 (match_code "eq,ne,le,lt,ge,gt,geu,gtu,leu,ltu,unordered,ordered,unlt,unle,unge,ungt"))
198 (define_special_predicate "minmax_operator"
199 (and (match_code "smin,smax,umin,umax")
200 (match_test "mode == GET_MODE (op)")))
202 (define_special_predicate "cc_register"
203 (and (match_code "reg")
204 (and (match_test "REGNO (op) == CC_REGNUM")
205 (ior (match_test "mode == GET_MODE (op)")
206 (match_test "mode == VOIDmode && GET_MODE_CLASS (GET_MODE (op)) == MODE_CC")))))
208 (define_special_predicate "dominant_cc_register"
211 if (mode == VOIDmode)
213 mode = GET_MODE (op);
215 if (GET_MODE_CLASS (mode) != MODE_CC)
219 return (cc_register (op, mode)
220 && (mode == CC_DNEmode
221 || mode == CC_DEQmode
222 || mode == CC_DLEmode
223 || mode == CC_DLTmode
224 || mode == CC_DGEmode
225 || mode == CC_DGTmode
226 || mode == CC_DLEUmode
227 || mode == CC_DLTUmode
228 || mode == CC_DGEUmode
229 || mode == CC_DGTUmode));
232 (define_special_predicate "arm_extendqisi_mem_op"
233 (and (match_operand 0 "memory_operand")
234 (match_test "arm_legitimate_address_p (mode, XEXP (op, 0), SIGN_EXTEND,
237 (define_predicate "power_of_two_operand"
238 (match_code "const_int")
240 HOST_WIDE_INT value = INTVAL (op);
242 return value != 0 && (value & (value - 1)) == 0;
245 (define_predicate "nonimmediate_di_operand"
246 (match_code "reg,subreg,mem")
248 if (s_register_operand (op, mode))
251 if (GET_CODE (op) == SUBREG)
252 op = SUBREG_REG (op);
254 return GET_CODE (op) == MEM && memory_address_p (DImode, XEXP (op, 0));
257 (define_predicate "di_operand"
258 (ior (match_code "const_int,const_double")
259 (and (match_code "reg,subreg,mem")
260 (match_operand 0 "nonimmediate_di_operand"))))
262 (define_predicate "nonimmediate_soft_df_operand"
263 (match_code "reg,subreg,mem")
265 if (s_register_operand (op, mode))
268 if (GET_CODE (op) == SUBREG)
269 op = SUBREG_REG (op);
271 return GET_CODE (op) == MEM && memory_address_p (DFmode, XEXP (op, 0));
274 (define_predicate "soft_df_operand"
275 (ior (match_code "const_double")
276 (and (match_code "reg,subreg,mem")
277 (match_operand 0 "nonimmediate_soft_df_operand"))))
279 (define_predicate "const_shift_operand"
280 (and (match_code "const_int")
281 (ior (match_operand 0 "power_of_two_operand")
282 (match_test "((unsigned HOST_WIDE_INT) INTVAL (op)) < 32"))))
285 (define_special_predicate "load_multiple_operation"
286 (match_code "parallel")
288 HOST_WIDE_INT count = XVECLEN (op, 0);
291 HOST_WIDE_INT i = 1, base = 0;
295 || GET_CODE (XVECEXP (op, 0, 0)) != SET)
298 /* Check to see if this might be a write-back. */
299 if (GET_CODE (SET_SRC (elt = XVECEXP (op, 0, 0))) == PLUS)
304 /* Now check it more carefully. */
305 if (GET_CODE (SET_DEST (elt)) != REG
306 || GET_CODE (XEXP (SET_SRC (elt), 0)) != REG
307 || GET_CODE (XEXP (SET_SRC (elt), 1)) != CONST_INT
308 || INTVAL (XEXP (SET_SRC (elt), 1)) != (count - 1) * 4)
312 /* Perform a quick check so we don't blow up below. */
314 || GET_CODE (XVECEXP (op, 0, i - 1)) != SET
315 || GET_CODE (SET_DEST (XVECEXP (op, 0, i - 1))) != REG
316 || GET_CODE (SET_SRC (XVECEXP (op, 0, i - 1))) != MEM)
319 dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, i - 1)));
320 src_addr = XEXP (SET_SRC (XVECEXP (op, 0, i - 1)), 0);
322 for (; i < count; i++)
324 elt = XVECEXP (op, 0, i);
326 if (GET_CODE (elt) != SET
327 || GET_CODE (SET_DEST (elt)) != REG
328 || GET_MODE (SET_DEST (elt)) != SImode
329 || REGNO (SET_DEST (elt)) != (unsigned int)(dest_regno + i - base)
330 || GET_CODE (SET_SRC (elt)) != MEM
331 || GET_MODE (SET_SRC (elt)) != SImode
332 || GET_CODE (XEXP (SET_SRC (elt), 0)) != PLUS
333 || !rtx_equal_p (XEXP (XEXP (SET_SRC (elt), 0), 0), src_addr)
334 || GET_CODE (XEXP (XEXP (SET_SRC (elt), 0), 1)) != CONST_INT
335 || INTVAL (XEXP (XEXP (SET_SRC (elt), 0), 1)) != (i - base) * 4)
342 (define_special_predicate "store_multiple_operation"
343 (match_code "parallel")
345 HOST_WIDE_INT count = XVECLEN (op, 0);
348 HOST_WIDE_INT i = 1, base = 0;
352 || GET_CODE (XVECEXP (op, 0, 0)) != SET)
355 /* Check to see if this might be a write-back. */
356 if (GET_CODE (SET_SRC (elt = XVECEXP (op, 0, 0))) == PLUS)
361 /* Now check it more carefully. */
362 if (GET_CODE (SET_DEST (elt)) != REG
363 || GET_CODE (XEXP (SET_SRC (elt), 0)) != REG
364 || GET_CODE (XEXP (SET_SRC (elt), 1)) != CONST_INT
365 || INTVAL (XEXP (SET_SRC (elt), 1)) != (count - 1) * 4)
369 /* Perform a quick check so we don't blow up below. */
371 || GET_CODE (XVECEXP (op, 0, i - 1)) != SET
372 || GET_CODE (SET_DEST (XVECEXP (op, 0, i - 1))) != MEM
373 || GET_CODE (SET_SRC (XVECEXP (op, 0, i - 1))) != REG)
376 src_regno = REGNO (SET_SRC (XVECEXP (op, 0, i - 1)));
377 dest_addr = XEXP (SET_DEST (XVECEXP (op, 0, i - 1)), 0);
379 for (; i < count; i++)
381 elt = XVECEXP (op, 0, i);
383 if (GET_CODE (elt) != SET
384 || GET_CODE (SET_SRC (elt)) != REG
385 || GET_MODE (SET_SRC (elt)) != SImode
386 || REGNO (SET_SRC (elt)) != (unsigned int)(src_regno + i - base)
387 || GET_CODE (SET_DEST (elt)) != MEM
388 || GET_MODE (SET_DEST (elt)) != SImode
389 || GET_CODE (XEXP (SET_DEST (elt), 0)) != PLUS
390 || !rtx_equal_p (XEXP (XEXP (SET_DEST (elt), 0), 0), dest_addr)
391 || GET_CODE (XEXP (XEXP (SET_DEST (elt), 0), 1)) != CONST_INT
392 || INTVAL (XEXP (XEXP (SET_DEST (elt), 0), 1)) != (i - base) * 4)
399 (define_special_predicate "multi_register_push"
400 (match_code "parallel")
402 if ((GET_CODE (XVECEXP (op, 0, 0)) != SET)
403 || (GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != UNSPEC)
404 || (XINT (SET_SRC (XVECEXP (op, 0, 0)), 1) != UNSPEC_PUSH_MULT))
410 ;;-------------------------------------------------------------------------
415 (define_predicate "thumb1_cmp_operand"
416 (ior (and (match_code "reg,subreg")
417 (match_operand 0 "s_register_operand"))
418 (and (match_code "const_int")
419 (match_test "((unsigned HOST_WIDE_INT) INTVAL (op)) < 256"))))
421 (define_predicate "thumb1_cmpneg_operand"
422 (and (match_code "const_int")
423 (match_test "INTVAL (op) < 0 && INTVAL (op) > -256")))
425 ;; Return TRUE if a result can be stored in OP without clobbering the
426 ;; condition code register. Prior to reload we only accept a
427 ;; register. After reload we have to be able to handle memory as
428 ;; well, since a pseudo may not get a hard reg and reload cannot
429 ;; handle output-reloads on jump insns.
431 ;; We could possibly handle mem before reload as well, but that might
432 ;; complicate things with the need to handle increment
434 (define_predicate "thumb_cbrch_target_operand"
435 (and (match_code "reg,subreg,mem")
436 (ior (match_operand 0 "s_register_operand")
437 (and (match_test "reload_in_progress || reload_completed")
438 (match_operand 0 "memory_operand")))))
440 ;;-------------------------------------------------------------------------
442 ;; MAVERICK predicates
445 (define_predicate "cirrus_register_operand"
446 (match_code "reg,subreg")
448 if (GET_CODE (op) == SUBREG)
449 op = SUBREG_REG (op);
451 return (GET_CODE (op) == REG
452 && (REGNO_REG_CLASS (REGNO (op)) == CIRRUS_REGS
453 || REGNO_REG_CLASS (REGNO (op)) == GENERAL_REGS));
456 (define_predicate "cirrus_fp_register"
457 (match_code "reg,subreg")
459 if (GET_CODE (op) == SUBREG)
460 op = SUBREG_REG (op);
462 return (GET_CODE (op) == REG
463 && (REGNO (op) >= FIRST_PSEUDO_REGISTER
464 || REGNO_REG_CLASS (REGNO (op)) == CIRRUS_REGS));
467 (define_predicate "cirrus_shift_const"
468 (and (match_code "const_int")
469 (match_test "((unsigned HOST_WIDE_INT) INTVAL (op)) < 64")))
474 (define_predicate "const_multiple_of_8_operand"
475 (match_code "const_int")
477 unsigned HOST_WIDE_INT val = INTVAL (op);
478 return (val & 7) == 0;
481 (define_predicate "imm_for_neon_mov_operand"
482 (match_code "const_vector")
484 return neon_immediate_valid_for_move (op, mode, NULL, NULL);
487 (define_predicate "imm_for_neon_logic_operand"
488 (match_code "const_vector")
490 return neon_immediate_valid_for_logic (op, mode, 0, NULL, NULL);
493 (define_predicate "imm_for_neon_inv_logic_operand"
494 (match_code "const_vector")
496 return neon_immediate_valid_for_logic (op, mode, 1, NULL, NULL);
499 (define_predicate "neon_logic_op2"
500 (ior (match_operand 0 "imm_for_neon_logic_operand")
501 (match_operand 0 "s_register_operand")))
503 (define_predicate "neon_inv_logic_op2"
504 (ior (match_operand 0 "imm_for_neon_inv_logic_operand")
505 (match_operand 0 "s_register_operand")))
507 ;; TODO: We could check lane numbers more precisely based on the mode.
508 (define_predicate "neon_lane_number"
509 (and (match_code "const_int")
510 (match_test "INTVAL (op) >= 0 && INTVAL (op) <= 7")))