1 /* Definitions of target machine for GNU compiler, for ARM.
2 Copyright (C) 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
3 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009
4 Free Software Foundation, Inc.
5 Contributed by Pieter `Tiggr' Schoenmakers (rcpieter@win.tue.nl)
6 and Martin Simmons (@harleqn.co.uk).
7 More major hacks by Richard Earnshaw (rearnsha@arm.com)
8 Minor hacks by Nick Clifton (nickc@cygnus.com)
10 This file is part of GCC.
12 GCC is free software; you can redistribute it and/or modify it
13 under the terms of the GNU General Public License as published
14 by the Free Software Foundation; either version 3, or (at your
15 option) any later version.
17 GCC is distributed in the hope that it will be useful, but WITHOUT
18 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
19 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
20 License for more details.
22 You should have received a copy of the GNU General Public License
23 along with GCC; see the file COPYING3. If not see
24 <http://www.gnu.org/licenses/>. */
29 #include "config/vxworks-dummy.h"
31 /* The architecture define. */
32 extern char arm_arch_name[];
34 /* Target CPU builtins. */
35 #define TARGET_CPU_CPP_BUILTINS() \
38 /* Define __arm__ even when in thumb mode, for \
39 consistency with armcc. */ \
40 builtin_define ("__arm__"); \
41 builtin_define ("__APCS_32__"); \
43 builtin_define ("__thumb__"); \
45 builtin_define ("__thumb2__"); \
49 builtin_define ("__ARMEB__"); \
51 builtin_define ("__THUMBEB__"); \
52 if (TARGET_LITTLE_WORDS) \
53 builtin_define ("__ARMWEL__"); \
57 builtin_define ("__ARMEL__"); \
59 builtin_define ("__THUMBEL__"); \
62 if (TARGET_SOFT_FLOAT) \
63 builtin_define ("__SOFTFP__"); \
66 builtin_define ("__VFP_FP__"); \
69 builtin_define ("__ARM_NEON__"); \
71 /* Add a define for interworking. \
72 Needed when building libgcc.a. */ \
73 if (arm_cpp_interwork) \
74 builtin_define ("__THUMB_INTERWORK__"); \
76 builtin_assert ("cpu=arm"); \
77 builtin_assert ("machine=arm"); \
79 builtin_define (arm_arch_name); \
80 if (arm_arch_cirrus) \
81 builtin_define ("__MAVERICK__"); \
82 if (arm_arch_xscale) \
83 builtin_define ("__XSCALE__"); \
84 if (arm_arch_iwmmxt) \
85 builtin_define ("__IWMMXT__"); \
86 if (TARGET_AAPCS_BASED) \
87 builtin_define ("__ARM_EABI__"); \
90 /* The various ARM cores. */
93 #define ARM_CORE(NAME, IDENT, ARCH, FLAGS, COSTS) \
95 #include "arm-cores.def"
97 /* Used to indicate that no processor has been specified. */
103 #define ARM_CORE(NAME, IDENT, ARCH, FLAGS, COSTS) \
105 #include "arm-cores.def"
110 /* The processor for which instructions should be scheduled. */
111 extern enum processor_type arm_tune;
113 typedef enum arm_cond_code
115 ARM_EQ = 0, ARM_NE, ARM_CS, ARM_CC, ARM_MI, ARM_PL, ARM_VS, ARM_VC,
116 ARM_HI, ARM_LS, ARM_GE, ARM_LT, ARM_GT, ARM_LE, ARM_AL, ARM_NV
120 extern arm_cc arm_current_cc;
122 #define ARM_INVERSE_CONDITION_CODE(X) ((arm_cc) (((int)X) ^ 1))
124 extern int arm_target_label;
125 extern int arm_ccfsm_state;
126 extern GTY(()) rtx arm_target_insn;
127 /* The label of the current constant pool. */
128 extern rtx pool_vector_label;
129 /* Set to 1 when a return insn is output, this means that the epilogue
131 extern int return_used_this_function;
132 /* Callback to output language specific object attributes. */
133 extern void (*arm_lang_output_object_attributes_hook)(void);
135 /* Just in case configure has failed to define anything. */
136 #ifndef TARGET_CPU_DEFAULT
137 #define TARGET_CPU_DEFAULT TARGET_CPU_generic
142 #define CPP_SPEC "%(subtarget_cpp_spec) \
143 %{msoft-float:%{mhard-float: \
144 %e-msoft-float and -mhard_float may not be used together}} \
145 %{mbig-endian:%{mlittle-endian: \
146 %e-mbig-endian and -mlittle-endian may not be used together}}"
152 /* This macro defines names of additional specifications to put in the specs
153 that can be used in various specifications like CC1_SPEC. Its definition
154 is an initializer with a subgrouping for each command option.
156 Each subgrouping contains a string constant, that defines the
157 specification name, and a string constant that used by the GCC driver
160 Do not define this macro if it does not need to do anything. */
161 #define EXTRA_SPECS \
162 { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \
163 SUBTARGET_EXTRA_SPECS
165 #ifndef SUBTARGET_EXTRA_SPECS
166 #define SUBTARGET_EXTRA_SPECS
169 #ifndef SUBTARGET_CPP_SPEC
170 #define SUBTARGET_CPP_SPEC ""
173 /* Run-time Target Specification. */
174 #ifndef TARGET_VERSION
175 #define TARGET_VERSION fputs (" (ARM/generic)", stderr);
178 #define TARGET_SOFT_FLOAT (arm_float_abi == ARM_FLOAT_ABI_SOFT)
179 /* Use hardware floating point instructions. */
180 #define TARGET_HARD_FLOAT (arm_float_abi != ARM_FLOAT_ABI_SOFT)
181 /* Use hardware floating point calling convention. */
182 #define TARGET_HARD_FLOAT_ABI (arm_float_abi == ARM_FLOAT_ABI_HARD)
183 #define TARGET_FPA (arm_fp_model == ARM_FP_MODEL_FPA)
184 #define TARGET_MAVERICK (arm_fp_model == ARM_FP_MODEL_MAVERICK)
185 #define TARGET_VFP (arm_fp_model == ARM_FP_MODEL_VFP)
186 #define TARGET_IWMMXT (arm_arch_iwmmxt)
187 #define TARGET_REALLY_IWMMXT (TARGET_IWMMXT && TARGET_32BIT)
188 #define TARGET_IWMMXT_ABI (TARGET_32BIT && arm_abi == ARM_ABI_IWMMXT)
189 #define TARGET_ARM (! TARGET_THUMB)
190 #define TARGET_EITHER 1 /* (TARGET_ARM | TARGET_THUMB) */
191 #define TARGET_BACKTRACE (leaf_function_p () \
192 ? TARGET_TPCS_LEAF_FRAME \
194 #define TARGET_LDRD (arm_arch5e && ARM_DOUBLEWORD_ALIGN)
195 #define TARGET_AAPCS_BASED \
196 (arm_abi != ARM_ABI_APCS && arm_abi != ARM_ABI_ATPCS)
198 #define TARGET_HARD_TP (target_thread_pointer == TP_CP15)
199 #define TARGET_SOFT_TP (target_thread_pointer == TP_SOFT)
201 /* Only 16-bit thumb code. */
202 #define TARGET_THUMB1 (TARGET_THUMB && !arm_arch_thumb2)
203 /* Arm or Thumb-2 32-bit code. */
204 #define TARGET_32BIT (TARGET_ARM || arm_arch_thumb2)
205 /* 32-bit Thumb-2 code. */
206 #define TARGET_THUMB2 (TARGET_THUMB && arm_arch_thumb2)
208 #define TARGET_THUMB1_ONLY (TARGET_THUMB1 && !arm_arch_notm)
210 /* The following two macros concern the ability to execute coprocessor
211 instructions for VFPv3 or NEON. TARGET_VFP3/TARGET_VFPD32 are currently
212 only ever tested when we know we are generating for VFP hardware; we need
213 to be more careful with TARGET_NEON as noted below. */
215 /* FPU is has the full VFPv3/NEON register file of 32 D registers. */
216 #define TARGET_VFPD32 (arm_fp_model == ARM_FP_MODEL_VFP \
217 && (arm_fpu_arch == FPUTYPE_VFP3 \
218 || arm_fpu_arch == FPUTYPE_NEON))
220 /* FPU supports VFPv3 instructions. */
221 #define TARGET_VFP3 (arm_fp_model == ARM_FP_MODEL_VFP \
222 && (arm_fpu_arch == FPUTYPE_VFP3D16 \
225 /* FPU supports Neon instructions. The setting of this macro gets
226 revealed via __ARM_NEON__ so we add extra guards upon TARGET_32BIT
227 and TARGET_HARD_FLOAT to ensure that NEON instructions are
229 #define TARGET_NEON (TARGET_32BIT && TARGET_HARD_FLOAT \
230 && arm_fp_model == ARM_FP_MODEL_VFP \
231 && arm_fpu_arch == FPUTYPE_NEON)
233 /* "DSP" multiply instructions, eg. SMULxy. */
234 #define TARGET_DSP_MULTIPLY \
235 (TARGET_32BIT && arm_arch5e && arm_arch_notm)
236 /* Integer SIMD instructions, and extend-accumulate instructions. */
237 #define TARGET_INT_SIMD \
238 (TARGET_32BIT && arm_arch6 && arm_arch_notm)
240 /* Should MOVW/MOVT be used in preference to a constant pool. */
241 #define TARGET_USE_MOVT (arm_arch_thumb2 && !optimize_size)
243 /* We could use unified syntax for arm mode, but for now we just use it
245 #define TARGET_UNIFIED_ASM TARGET_THUMB2
248 /* True iff the full BPABI is being used. If TARGET_BPABI is true,
249 then TARGET_AAPCS_BASED must be true -- but the converse does not
250 hold. TARGET_BPABI implies the use of the BPABI runtime library,
251 etc., in addition to just the AAPCS calling conventions. */
253 #define TARGET_BPABI false
256 /* Support for a compile-time default CPU, et cetera. The rules are:
257 --with-arch is ignored if -march or -mcpu are specified.
258 --with-cpu is ignored if -march or -mcpu are specified, and is overridden
260 --with-tune is ignored if -mtune or -mcpu are specified (but not affected
262 --with-float is ignored if -mhard-float, -msoft-float or -mfloat-abi are
264 --with-fpu is ignored if -mfpu is specified.
265 --with-abi is ignored is -mabi is specified. */
266 #define OPTION_DEFAULT_SPECS \
267 {"arch", "%{!march=*:%{!mcpu=*:-march=%(VALUE)}}" }, \
268 {"cpu", "%{!march=*:%{!mcpu=*:-mcpu=%(VALUE)}}" }, \
269 {"tune", "%{!mcpu=*:%{!mtune=*:-mtune=%(VALUE)}}" }, \
271 "%{!msoft-float:%{!mhard-float:%{!mfloat-abi=*:-mfloat-abi=%(VALUE)}}}" }, \
272 {"fpu", "%{!mfpu=*:-mfpu=%(VALUE)}"}, \
273 {"abi", "%{!mabi=*:-mabi=%(VALUE)}"}, \
274 {"mode", "%{!marm:%{!mthumb:-m%(VALUE)}}"},
276 /* Which floating point model to use. */
279 ARM_FP_MODEL_UNKNOWN,
280 /* FPA model (Hardware or software). */
282 /* Cirrus Maverick floating point model. */
283 ARM_FP_MODEL_MAVERICK,
284 /* VFP floating point model. */
288 extern enum arm_fp_model arm_fp_model;
290 /* Which floating point hardware is available. Also update
291 fp_model_for_fpu in arm.c when adding entries to this list. */
294 /* No FP hardware. */
296 /* Full FPA support. */
298 /* Emulated FPA hardware, Issue 2 emulator (no LFM/SFM). */
300 /* Emulated FPA hardware, Issue 3 emulator. */
302 /* Cirrus Maverick floating point co-processor. */
314 /* Recast the floating point class to be the floating point attribute. */
315 #define arm_fpu_attr ((enum attr_fpu) arm_fpu_tune)
317 /* What type of floating point to tune for */
318 extern enum fputype arm_fpu_tune;
320 /* What type of floating point instructions are available */
321 extern enum fputype arm_fpu_arch;
326 ARM_FLOAT_ABI_SOFTFP,
330 extern enum float_abi_type arm_float_abi;
332 #ifndef TARGET_DEFAULT_FLOAT_ABI
333 #define TARGET_DEFAULT_FLOAT_ABI ARM_FLOAT_ABI_SOFT
336 /* Which ABI to use. */
346 extern enum arm_abi_type arm_abi;
348 #ifndef ARM_DEFAULT_ABI
349 #define ARM_DEFAULT_ABI ARM_ABI_APCS
352 /* Which thread pointer access sequence to use. */
359 extern enum arm_tp_type target_thread_pointer;
361 /* Nonzero if this chip supports the ARM Architecture 3M extensions. */
362 extern int arm_arch3m;
364 /* Nonzero if this chip supports the ARM Architecture 4 extensions. */
365 extern int arm_arch4;
367 /* Nonzero if this chip supports the ARM Architecture 4T extensions. */
368 extern int arm_arch4t;
370 /* Nonzero if this chip supports the ARM Architecture 5 extensions. */
371 extern int arm_arch5;
373 /* Nonzero if this chip supports the ARM Architecture 5E extensions. */
374 extern int arm_arch5e;
376 /* Nonzero if this chip supports the ARM Architecture 6 extensions. */
377 extern int arm_arch6;
379 /* Nonzero if instructions not present in the 'M' profile can be used. */
380 extern int arm_arch_notm;
382 /* Nonzero if this chip can benefit from load scheduling. */
383 extern int arm_ld_sched;
385 /* Nonzero if generating thumb code. */
386 extern int thumb_code;
388 /* Nonzero if this chip is a StrongARM. */
389 extern int arm_tune_strongarm;
391 /* Nonzero if this chip is a Cirrus variant. */
392 extern int arm_arch_cirrus;
394 /* Nonzero if this chip supports Intel XScale with Wireless MMX technology. */
395 extern int arm_arch_iwmmxt;
397 /* Nonzero if this chip is an XScale. */
398 extern int arm_arch_xscale;
400 /* Nonzero if tuning for XScale. */
401 extern int arm_tune_xscale;
403 /* Nonzero if tuning for stores via the write buffer. */
404 extern int arm_tune_wbuf;
406 /* Nonzero if tuning for Cortex-A9. */
407 extern int arm_tune_cortex_a9;
409 /* Nonzero if we should define __THUMB_INTERWORK__ in the
411 XXX This is a bit of a hack, it's intended to help work around
412 problems in GLD which doesn't understand that armv5t code is
413 interworking clean. */
414 extern int arm_cpp_interwork;
416 /* Nonzero if chip supports Thumb 2. */
417 extern int arm_arch_thumb2;
419 /* Nonzero if chip supports integer division instruction. */
420 extern int arm_arch_hwdiv;
422 #ifndef TARGET_DEFAULT
423 #define TARGET_DEFAULT (MASK_APCS_FRAME)
426 /* The frame pointer register used in gcc has nothing to do with debugging;
427 that is controlled by the APCS-FRAME option. */
428 #define CAN_DEBUG_WITHOUT_FP
430 #define OVERRIDE_OPTIONS arm_override_options ()
432 #define OPTIMIZATION_OPTIONS(LEVEL,SIZE) \
433 arm_optimization_options ((LEVEL), (SIZE))
435 /* Nonzero if PIC code requires explicit qualifiers to generate
436 PLT and GOT relocs rather than the assembler doing so implicitly.
437 Subtargets can override these if required. */
438 #ifndef NEED_GOT_RELOC
439 #define NEED_GOT_RELOC 0
441 #ifndef NEED_PLT_RELOC
442 #define NEED_PLT_RELOC 0
445 /* Nonzero if we need to refer to the GOT with a PC-relative
446 offset. In other words, generate
448 .word _GLOBAL_OFFSET_TABLE_ - [. - (.Lxx + 8)]
452 .word _GLOBAL_OFFSET_TABLE_ - (.Lxx + 8)
454 The default is true, which matches NetBSD. Subtargets can
455 override this if required. */
460 /* Target machine storage Layout. */
463 /* Define this macro if it is advisable to hold scalars in registers
464 in a wider mode than that declared by the program. In such cases,
465 the value is constrained to be within the bounds of the declared
466 type, but kept valid in the wider mode. The signedness of the
467 extension may differ from that of the type. */
469 /* It is far faster to zero extend chars than to sign extend them */
471 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
472 if (GET_MODE_CLASS (MODE) == MODE_INT \
473 && GET_MODE_SIZE (MODE) < 4) \
475 if (MODE == QImode) \
477 else if (MODE == HImode) \
482 #define PROMOTE_FUNCTION_MODE(MODE, UNSIGNEDP, TYPE) \
483 if ((GET_MODE_CLASS (MODE) == MODE_INT \
484 || GET_MODE_CLASS (MODE) == MODE_COMPLEX_INT) \
485 && GET_MODE_SIZE (MODE) < 4) \
488 /* Define this if most significant bit is lowest numbered
489 in instructions that operate on numbered bit-fields. */
490 #define BITS_BIG_ENDIAN 0
492 /* Define this if most significant byte of a word is the lowest numbered.
493 Most ARM processors are run in little endian mode, so that is the default.
494 If you want to have it run-time selectable, change the definition in a
495 cover file to be TARGET_BIG_ENDIAN. */
496 #define BYTES_BIG_ENDIAN (TARGET_BIG_END != 0)
498 /* Define this if most significant word of a multiword number is the lowest
500 This is always false, even when in big-endian mode. */
501 #define WORDS_BIG_ENDIAN (BYTES_BIG_ENDIAN && ! TARGET_LITTLE_WORDS)
503 /* LIBGCC2_WORDS_BIG_ENDIAN has to be a constant, so we define this based
504 on processor pre-defineds when compiling libgcc2.c. */
505 #if defined(__ARMEB__) && !defined(__ARMWEL__)
506 #define LIBGCC2_WORDS_BIG_ENDIAN 1
508 #define LIBGCC2_WORDS_BIG_ENDIAN 0
511 /* Define this if most significant word of doubles is the lowest numbered.
512 The rules are different based on whether or not we use FPA-format,
513 VFP-format or some other floating point co-processor's format doubles. */
514 #define FLOAT_WORDS_BIG_ENDIAN (arm_float_words_big_endian ())
516 #define UNITS_PER_WORD 4
518 /* Use the option -mvectorize-with-neon-quad to override the use of doubleword
519 registers when autovectorizing for Neon, at least until multiple vector
520 widths are supported properly by the middle-end. */
521 #define UNITS_PER_SIMD_WORD(MODE) \
522 (TARGET_NEON ? (TARGET_NEON_VECTORIZE_QUAD ? 16 : 8) : UNITS_PER_WORD)
524 /* True if natural alignment is used for doubleword types. */
525 #define ARM_DOUBLEWORD_ALIGN TARGET_AAPCS_BASED
527 #define DOUBLEWORD_ALIGNMENT 64
529 #define PARM_BOUNDARY 32
531 #define STACK_BOUNDARY (ARM_DOUBLEWORD_ALIGN ? DOUBLEWORD_ALIGNMENT : 32)
533 #define PREFERRED_STACK_BOUNDARY \
534 (arm_abi == ARM_ABI_ATPCS ? 64 : STACK_BOUNDARY)
536 #define FUNCTION_BOUNDARY ((TARGET_THUMB && optimize_size) ? 16 : 32)
538 /* The lowest bit is used to indicate Thumb-mode functions, so the
539 vbit must go into the delta field of pointers to member
541 #define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_delta
543 #define EMPTY_FIELD_BOUNDARY 32
545 #define BIGGEST_ALIGNMENT (ARM_DOUBLEWORD_ALIGN ? DOUBLEWORD_ALIGNMENT : 32)
547 /* XXX Blah -- this macro is used directly by libobjc. Since it
548 supports no vector modes, cut out the complexity and fall back
549 on BIGGEST_FIELD_ALIGNMENT. */
550 #ifdef IN_TARGET_LIBS
551 #define BIGGEST_FIELD_ALIGNMENT 64
554 /* Make strings word-aligned so strcpy from constants will be faster. */
555 #define CONSTANT_ALIGNMENT_FACTOR (TARGET_THUMB || ! arm_tune_xscale ? 1 : 2)
557 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
558 ((TREE_CODE (EXP) == STRING_CST \
560 && (ALIGN) < BITS_PER_WORD * CONSTANT_ALIGNMENT_FACTOR) \
561 ? BITS_PER_WORD * CONSTANT_ALIGNMENT_FACTOR : (ALIGN))
563 /* Align definitions of arrays, unions and structures so that
564 initializations and copies can be made more efficient. This is not
565 ABI-changing, so it only affects places where we can see the
567 #define DATA_ALIGNMENT(EXP, ALIGN) \
568 ((((ALIGN) < BITS_PER_WORD) \
569 && (TREE_CODE (EXP) == ARRAY_TYPE \
570 || TREE_CODE (EXP) == UNION_TYPE \
571 || TREE_CODE (EXP) == RECORD_TYPE)) ? BITS_PER_WORD : (ALIGN))
573 /* Similarly, make sure that objects on the stack are sensibly aligned. */
574 #define LOCAL_ALIGNMENT(EXP, ALIGN) DATA_ALIGNMENT(EXP, ALIGN)
576 /* Setting STRUCTURE_SIZE_BOUNDARY to 32 produces more efficient code, but the
577 value set in previous versions of this toolchain was 8, which produces more
578 compact structures. The command line option -mstructure_size_boundary=<n>
579 can be used to change this value. For compatibility with the ARM SDK
580 however the value should be left at 32. ARM SDT Reference Manual (ARM DUI
581 0020D) page 2-20 says "Structures are aligned on word boundaries".
582 The AAPCS specifies a value of 8. */
583 #define STRUCTURE_SIZE_BOUNDARY arm_structure_size_boundary
584 extern int arm_structure_size_boundary;
586 /* This is the value used to initialize arm_structure_size_boundary. If a
587 particular arm target wants to change the default value it should change
588 the definition of this macro, not STRUCTURE_SIZE_BOUNDARY. See netbsd.h
589 for an example of this. */
590 #ifndef DEFAULT_STRUCTURE_SIZE_BOUNDARY
591 #define DEFAULT_STRUCTURE_SIZE_BOUNDARY 32
594 /* Nonzero if move instructions will actually fail to work
595 when given unaligned data. */
596 #define STRICT_ALIGNMENT 1
598 /* wchar_t is unsigned under the AAPCS. */
600 #define WCHAR_TYPE (TARGET_AAPCS_BASED ? "unsigned int" : "int")
602 #define WCHAR_TYPE_SIZE BITS_PER_WORD
606 #define SIZE_TYPE (TARGET_AAPCS_BASED ? "unsigned int" : "long unsigned int")
610 #define PTRDIFF_TYPE (TARGET_AAPCS_BASED ? "int" : "long int")
613 /* AAPCS requires that structure alignment is affected by bitfields. */
614 #ifndef PCC_BITFIELD_TYPE_MATTERS
615 #define PCC_BITFIELD_TYPE_MATTERS TARGET_AAPCS_BASED
619 /* Standard register usage. */
621 /* Register allocation in ARM Procedure Call Standard (as used on RISCiX):
622 (S - saved over call).
624 r0 * argument word/integer result
627 r4-r8 S register variable
628 r9 S (rfp) register variable (real frame pointer)
630 r10 F S (sl) stack limit (used by -mapcs-stack-check)
631 r11 F S (fp) argument pointer
632 r12 (ip) temp workspace
633 r13 F S (sp) lower end of current stack frame
634 r14 (lr) link address/workspace
635 r15 F (pc) program counter
637 f0 floating point result
638 f1-f3 floating point scratch
640 f4-f7 S floating point variable
642 cc This is NOT a real register, but is used internally
643 to represent things that use or set the condition
645 sfp This isn't either. It is used during rtl generation
646 since the offset between the frame pointer and the
647 auto's isn't known until after register allocation.
648 afp Nor this, we only need this because of non-local
649 goto. Without it fp appears to be used and the
650 elimination code won't get rid of sfp. It tracks
651 fp exactly at all times.
653 *: See CONDITIONAL_REGISTER_USAGE */
656 mvf0 Cirrus floating point result
657 mvf1-mvf3 Cirrus floating point scratch
658 mvf4-mvf15 S Cirrus floating point variable. */
660 /* s0-s15 VFP scratch (aka d0-d7).
661 s16-s31 S VFP variable (aka d8-d15).
662 vfpcc Not a real register. Represents the VFP condition
665 /* The stack backtrace structure is as follows:
666 fp points to here: | save code pointer | [fp]
667 | return link value | [fp, #-4]
668 | return sp value | [fp, #-8]
669 | return fp value | [fp, #-12]
670 [| saved r10 value |]
681 [| saved f7 value |] three words
682 [| saved f6 value |] three words
683 [| saved f5 value |] three words
684 [| saved f4 value |] three words
685 r0-r3 are not normally saved in a C function. */
687 /* 1 for registers that have pervasive standard uses
688 and are not available for the register allocator. */
689 #define FIXED_REGISTERS \
711 /* 1 for registers not available across function calls.
712 These must include the FIXED_REGISTERS and also any
713 registers that can be used without being saved.
714 The latter must include the registers where values are returned
715 and the register where structure-value addresses are passed.
716 Aside from that, you can include as many other registers as you like.
717 The CC is not preserved over function calls on the ARM 6, so it is
718 easier to assume this for all. SFP is preserved, since FP is. */
719 #define CALL_USED_REGISTERS \
741 #ifndef SUBTARGET_CONDITIONAL_REGISTER_USAGE
742 #define SUBTARGET_CONDITIONAL_REGISTER_USAGE
745 #define CONDITIONAL_REGISTER_USAGE \
749 if (TARGET_SOFT_FLOAT || TARGET_THUMB1 || !TARGET_FPA) \
751 for (regno = FIRST_FPA_REGNUM; \
752 regno <= LAST_FPA_REGNUM; ++regno) \
753 fixed_regs[regno] = call_used_regs[regno] = 1; \
756 if (TARGET_THUMB && optimize_size) \
758 /* When optimizing for size, it's better not to use \
759 the HI regs, because of the overhead of stacking \
761 /* ??? Is this still true for thumb2? */ \
762 for (regno = FIRST_HI_REGNUM; \
763 regno <= LAST_HI_REGNUM; ++regno) \
764 fixed_regs[regno] = call_used_regs[regno] = 1; \
767 /* The link register can be clobbered by any branch insn, \
768 but we have no way to track that at present, so mark \
769 it as unavailable. */ \
771 fixed_regs[LR_REGNUM] = call_used_regs[LR_REGNUM] = 1; \
773 if (TARGET_32BIT && TARGET_HARD_FLOAT) \
775 if (TARGET_MAVERICK) \
777 for (regno = FIRST_FPA_REGNUM; \
778 regno <= LAST_FPA_REGNUM; ++ regno) \
779 fixed_regs[regno] = call_used_regs[regno] = 1; \
780 for (regno = FIRST_CIRRUS_FP_REGNUM; \
781 regno <= LAST_CIRRUS_FP_REGNUM; ++ regno) \
783 fixed_regs[regno] = 0; \
784 call_used_regs[regno] = regno < FIRST_CIRRUS_FP_REGNUM + 4; \
789 /* VFPv3 registers are disabled when earlier VFP \
790 versions are selected due to the definition of \
791 LAST_VFP_REGNUM. */ \
792 for (regno = FIRST_VFP_REGNUM; \
793 regno <= LAST_VFP_REGNUM; ++ regno) \
795 fixed_regs[regno] = 0; \
796 call_used_regs[regno] = regno < FIRST_VFP_REGNUM + 16 \
797 || regno >= FIRST_VFP_REGNUM + 32; \
802 if (TARGET_REALLY_IWMMXT) \
804 regno = FIRST_IWMMXT_GR_REGNUM; \
805 /* The 2002/10/09 revision of the XScale ABI has wCG0 \
806 and wCG1 as call-preserved registers. The 2002/11/21 \
807 revision changed this so that all wCG registers are \
808 scratch registers. */ \
809 for (regno = FIRST_IWMMXT_GR_REGNUM; \
810 regno <= LAST_IWMMXT_GR_REGNUM; ++ regno) \
811 fixed_regs[regno] = 0; \
812 /* The XScale ABI has wR0 - wR9 as scratch registers, \
813 the rest as call-preserved registers. */ \
814 for (regno = FIRST_IWMMXT_REGNUM; \
815 regno <= LAST_IWMMXT_REGNUM; ++ regno) \
817 fixed_regs[regno] = 0; \
818 call_used_regs[regno] = regno < FIRST_IWMMXT_REGNUM + 10; \
822 if ((unsigned) PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM) \
824 fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
825 call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
827 else if (TARGET_APCS_STACK) \
829 fixed_regs[10] = 1; \
830 call_used_regs[10] = 1; \
832 /* -mcaller-super-interworking reserves r11 for calls to \
833 _interwork_r11_call_via_rN(). Making the register global \
834 is an easy way of ensuring that it remains valid for all \
836 if (TARGET_APCS_FRAME || TARGET_CALLER_INTERWORKING \
837 || TARGET_TPCS_FRAME || TARGET_TPCS_LEAF_FRAME) \
839 fixed_regs[ARM_HARD_FRAME_POINTER_REGNUM] = 1; \
840 call_used_regs[ARM_HARD_FRAME_POINTER_REGNUM] = 1; \
841 if (TARGET_CALLER_INTERWORKING) \
842 global_regs[ARM_HARD_FRAME_POINTER_REGNUM] = 1; \
844 SUBTARGET_CONDITIONAL_REGISTER_USAGE \
847 /* These are a couple of extensions to the formats accepted
849 %@ prints out ASM_COMMENT_START
850 %r prints out REGISTER_PREFIX reg_names[arg] */
851 #define ASM_FPRINTF_EXTENSIONS(FILE, ARGS, P) \
853 fputs (ASM_COMMENT_START, FILE); \
857 fputs (REGISTER_PREFIX, FILE); \
858 fputs (reg_names [va_arg (ARGS, int)], FILE); \
861 /* Round X up to the nearest word. */
862 #define ROUND_UP_WORD(X) (((X) + 3) & ~3)
864 /* Convert fron bytes to ints. */
865 #define ARM_NUM_INTS(X) (((X) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
867 /* The number of (integer) registers required to hold a quantity of type MODE.
868 Also used for VFP registers. */
869 #define ARM_NUM_REGS(MODE) \
870 ARM_NUM_INTS (GET_MODE_SIZE (MODE))
872 /* The number of (integer) registers required to hold a quantity of TYPE MODE. */
873 #define ARM_NUM_REGS2(MODE, TYPE) \
874 ARM_NUM_INTS ((MODE) == BLKmode ? \
875 int_size_in_bytes (TYPE) : GET_MODE_SIZE (MODE))
877 /* The number of (integer) argument register available. */
878 #define NUM_ARG_REGS 4
880 /* Return the register number of the N'th (integer) argument. */
881 #define ARG_REGISTER(N) (N - 1)
883 /* Specify the registers used for certain standard purposes.
884 The values of these macros are register numbers. */
886 /* The number of the last argument register. */
887 #define LAST_ARG_REGNUM ARG_REGISTER (NUM_ARG_REGS)
889 /* The numbers of the Thumb register ranges. */
890 #define FIRST_LO_REGNUM 0
891 #define LAST_LO_REGNUM 7
892 #define FIRST_HI_REGNUM 8
893 #define LAST_HI_REGNUM 11
895 #ifndef TARGET_UNWIND_INFO
896 /* We use sjlj exceptions for backwards compatibility. */
897 #define MUST_USE_SJLJ_EXCEPTIONS 1
900 /* We can generate DWARF2 Unwind info, even though we don't use it. */
901 #define DWARF2_UNWIND_INFO 1
903 /* Use r0 and r1 to pass exception handling information. */
904 #define EH_RETURN_DATA_REGNO(N) (((N) < 2) ? N : INVALID_REGNUM)
906 /* The register that holds the return address in exception handlers. */
907 #define ARM_EH_STACKADJ_REGNUM 2
908 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (SImode, ARM_EH_STACKADJ_REGNUM)
910 /* The native (Norcroft) Pascal compiler for the ARM passes the static chain
911 as an invisible last argument (possible since varargs don't exist in
912 Pascal), so the following is not true. */
913 #define STATIC_CHAIN_REGNUM 12
915 /* Define this to be where the real frame pointer is if it is not possible to
916 work out the offset between the frame pointer and the automatic variables
917 until after register allocation has taken place. FRAME_POINTER_REGNUM
918 should point to a special register that we will make sure is eliminated.
920 For the Thumb we have another problem. The TPCS defines the frame pointer
921 as r11, and GCC believes that it is always possible to use the frame pointer
922 as base register for addressing purposes. (See comments in
923 find_reloads_address()). But - the Thumb does not allow high registers,
924 including r11, to be used as base address registers. Hence our problem.
926 The solution used here, and in the old thumb port is to use r7 instead of
927 r11 as the hard frame pointer and to have special code to generate
928 backtrace structures on the stack (if required to do so via a command line
929 option) using r11. This is the only 'user visible' use of r11 as a frame
931 #define ARM_HARD_FRAME_POINTER_REGNUM 11
932 #define THUMB_HARD_FRAME_POINTER_REGNUM 7
934 #define HARD_FRAME_POINTER_REGNUM \
936 ? ARM_HARD_FRAME_POINTER_REGNUM \
937 : THUMB_HARD_FRAME_POINTER_REGNUM)
939 #define FP_REGNUM HARD_FRAME_POINTER_REGNUM
941 /* Register to use for pushing function arguments. */
942 #define STACK_POINTER_REGNUM SP_REGNUM
944 /* ARM floating pointer registers. */
945 #define FIRST_FPA_REGNUM 16
946 #define LAST_FPA_REGNUM 23
947 #define IS_FPA_REGNUM(REGNUM) \
948 (((REGNUM) >= FIRST_FPA_REGNUM) && ((REGNUM) <= LAST_FPA_REGNUM))
950 #define FIRST_IWMMXT_GR_REGNUM 43
951 #define LAST_IWMMXT_GR_REGNUM 46
952 #define FIRST_IWMMXT_REGNUM 47
953 #define LAST_IWMMXT_REGNUM 62
954 #define IS_IWMMXT_REGNUM(REGNUM) \
955 (((REGNUM) >= FIRST_IWMMXT_REGNUM) && ((REGNUM) <= LAST_IWMMXT_REGNUM))
956 #define IS_IWMMXT_GR_REGNUM(REGNUM) \
957 (((REGNUM) >= FIRST_IWMMXT_GR_REGNUM) && ((REGNUM) <= LAST_IWMMXT_GR_REGNUM))
959 /* Base register for access to local variables of the function. */
960 #define FRAME_POINTER_REGNUM 25
962 /* Base register for access to arguments of the function. */
963 #define ARG_POINTER_REGNUM 26
965 #define FIRST_CIRRUS_FP_REGNUM 27
966 #define LAST_CIRRUS_FP_REGNUM 42
967 #define IS_CIRRUS_REGNUM(REGNUM) \
968 (((REGNUM) >= FIRST_CIRRUS_FP_REGNUM) && ((REGNUM) <= LAST_CIRRUS_FP_REGNUM))
970 #define FIRST_VFP_REGNUM 63
971 #define D7_VFP_REGNUM 78 /* Registers 77 and 78 == VFP reg D7. */
972 #define LAST_VFP_REGNUM \
973 (TARGET_VFPD32 ? LAST_HI_VFP_REGNUM : LAST_LO_VFP_REGNUM)
975 #define IS_VFP_REGNUM(REGNUM) \
976 (((REGNUM) >= FIRST_VFP_REGNUM) && ((REGNUM) <= LAST_VFP_REGNUM))
978 /* VFP registers are split into two types: those defined by VFP versions < 3
979 have D registers overlaid on consecutive pairs of S registers. VFP version 3
980 defines 16 new D registers (d16-d31) which, for simplicity and correctness
981 in various parts of the backend, we implement as "fake" single-precision
982 registers (which would be S32-S63, but cannot be used in that way). The
983 following macros define these ranges of registers. */
984 #define LAST_LO_VFP_REGNUM 94
985 #define FIRST_HI_VFP_REGNUM 95
986 #define LAST_HI_VFP_REGNUM 126
988 #define VFP_REGNO_OK_FOR_SINGLE(REGNUM) \
989 ((REGNUM) <= LAST_LO_VFP_REGNUM)
991 /* DFmode values are only valid in even register pairs. */
992 #define VFP_REGNO_OK_FOR_DOUBLE(REGNUM) \
993 ((((REGNUM) - FIRST_VFP_REGNUM) & 1) == 0)
995 /* Neon Quad values must start at a multiple of four registers. */
996 #define NEON_REGNO_OK_FOR_QUAD(REGNUM) \
997 ((((REGNUM) - FIRST_VFP_REGNUM) & 3) == 0)
999 /* Neon structures of vectors must be in even register pairs and there
1000 must be enough registers available. Because of various patterns
1001 requiring quad registers, we require them to start at a multiple of
1003 #define NEON_REGNO_OK_FOR_NREGS(REGNUM, N) \
1004 ((((REGNUM) - FIRST_VFP_REGNUM) & 3) == 0 \
1005 && (LAST_VFP_REGNUM - (REGNUM) >= 2 * (N) - 1))
1007 /* The number of hard registers is 16 ARM + 8 FPA + 1 CC + 1 SFP + 1 AFP. */
1008 /* + 16 Cirrus registers take us up to 43. */
1009 /* Intel Wireless MMX Technology registers add 16 + 4 more. */
1010 /* VFP (VFP3) adds 32 (64) + 1 more. */
1011 #define FIRST_PSEUDO_REGISTER 128
1013 #define DBX_REGISTER_NUMBER(REGNO) arm_dbx_register_number (REGNO)
1015 /* Value should be nonzero if functions must have frame pointers.
1016 Zero means the frame pointer need not be set up (and parms may be accessed
1017 via the stack pointer) in functions that seem suitable.
1018 If we have to have a frame pointer we might as well make use of it.
1019 APCS says that the frame pointer does not need to be pushed in leaf
1020 functions, or simple tail call functions. */
1022 #ifndef SUBTARGET_FRAME_POINTER_REQUIRED
1023 #define SUBTARGET_FRAME_POINTER_REQUIRED 0
1026 #define FRAME_POINTER_REQUIRED \
1027 (cfun->has_nonlocal_label \
1028 || SUBTARGET_FRAME_POINTER_REQUIRED \
1029 || (TARGET_ARM && TARGET_APCS_FRAME && ! leaf_function_p ()))
1031 /* Return number of consecutive hard regs needed starting at reg REGNO
1032 to hold something of mode MODE.
1033 This is ordinarily the length in words of a value of mode MODE
1034 but can be less for certain modes in special long registers.
1036 On the ARM regs are UNITS_PER_WORD bits wide; FPA regs can hold any FP
1038 #define HARD_REGNO_NREGS(REGNO, MODE) \
1040 && REGNO >= FIRST_FPA_REGNUM \
1041 && REGNO != FRAME_POINTER_REGNUM \
1042 && REGNO != ARG_POINTER_REGNUM) \
1043 && !IS_VFP_REGNUM (REGNO) \
1044 ? 1 : ARM_NUM_REGS (MODE))
1046 /* Return true if REGNO is suitable for holding a quantity of type MODE. */
1047 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
1048 arm_hard_regno_mode_ok ((REGNO), (MODE))
1050 /* Value is 1 if it is a good idea to tie two pseudo registers
1051 when one has mode MODE1 and one has mode MODE2.
1052 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
1053 for any hard reg, then this must be 0 for correct output. */
1054 #define MODES_TIEABLE_P(MODE1, MODE2) \
1055 (GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2))
1057 #define VALID_IWMMXT_REG_MODE(MODE) \
1058 (arm_vector_mode_supported_p (MODE) || (MODE) == DImode)
1060 /* Modes valid for Neon D registers. */
1061 #define VALID_NEON_DREG_MODE(MODE) \
1062 ((MODE) == V2SImode || (MODE) == V4HImode || (MODE) == V8QImode \
1063 || (MODE) == V2SFmode || (MODE) == DImode)
1065 /* Modes valid for Neon Q registers. */
1066 #define VALID_NEON_QREG_MODE(MODE) \
1067 ((MODE) == V4SImode || (MODE) == V8HImode || (MODE) == V16QImode \
1068 || (MODE) == V4SFmode || (MODE) == V2DImode)
1070 /* Structure modes valid for Neon registers. */
1071 #define VALID_NEON_STRUCT_MODE(MODE) \
1072 ((MODE) == TImode || (MODE) == EImode || (MODE) == OImode \
1073 || (MODE) == CImode || (MODE) == XImode)
1075 /* The order in which register should be allocated. It is good to use ip
1076 since no saving is required (though calls clobber it) and it never contains
1077 function parameters. It is quite good to use lr since other calls may
1078 clobber it anyway. Allocate r0 through r3 in reverse order since r3 is
1079 least likely to contain a function parameter; in addition results are
1081 For VFP/VFPv3, allocate D16-D31 first, then caller-saved registers (D0-D7),
1082 then D8-D15. The reason for doing this is to attempt to reduce register
1083 pressure when both single- and double-precision registers are used in a
1086 #define REG_ALLOC_ORDER \
1088 3, 2, 1, 0, 12, 14, 4, 5, \
1089 6, 7, 8, 10, 9, 11, 13, 15, \
1090 16, 17, 18, 19, 20, 21, 22, 23, \
1091 27, 28, 29, 30, 31, 32, 33, 34, \
1092 35, 36, 37, 38, 39, 40, 41, 42, \
1093 43, 44, 45, 46, 47, 48, 49, 50, \
1094 51, 52, 53, 54, 55, 56, 57, 58, \
1097 95, 96, 97, 98, 99, 100, 101, 102, \
1098 103, 104, 105, 106, 107, 108, 109, 110, \
1099 111, 112, 113, 114, 115, 116, 117, 118, \
1100 119, 120, 121, 122, 123, 124, 125, 126, \
1101 78, 77, 76, 75, 74, 73, 72, 71, \
1102 70, 69, 68, 67, 66, 65, 64, 63, \
1103 79, 80, 81, 82, 83, 84, 85, 86, \
1104 87, 88, 89, 90, 91, 92, 93, 94, \
1108 /* Use different register alloc ordering for Thumb. */
1109 #define ORDER_REGS_FOR_LOCAL_ALLOC arm_order_regs_for_local_alloc ()
1111 /* Interrupt functions can only use registers that have already been
1112 saved by the prologue, even if they would normally be
1114 #define HARD_REGNO_RENAME_OK(SRC, DST) \
1115 (! IS_INTERRUPT (cfun->machine->func_type) || \
1116 df_regs_ever_live_p (DST))
1118 /* Register and constant classes. */
1120 /* Register classes: used to be simple, just all ARM regs or all FPA regs
1121 Now that the Thumb is involved it has become more complicated. */
1145 #define N_REG_CLASSES (int) LIM_REG_CLASSES
1147 /* Give names of register classes as strings for dump file. */
1148 #define REG_CLASS_NAMES \
1170 /* Define which registers fit in which classes.
1171 This is an initializer for a vector of HARD_REG_SET
1172 of length N_REG_CLASSES. */
1173 #define REG_CLASS_CONTENTS \
1175 { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* NO_REGS */ \
1176 { 0x00FF0000, 0x00000000, 0x00000000, 0x00000000 }, /* FPA_REGS */ \
1177 { 0xF8000000, 0x000007FF, 0x00000000, 0x00000000 }, /* CIRRUS_REGS */ \
1178 { 0x00000000, 0x80000000, 0x00007FFF, 0x00000000 }, /* VFP_D0_D7_REGS */ \
1179 { 0x00000000, 0x80000000, 0x7FFFFFFF, 0x00000000 }, /* VFP_LO_REGS */ \
1180 { 0x00000000, 0x00000000, 0x80000000, 0x7FFFFFFF }, /* VFP_HI_REGS */ \
1181 { 0x00000000, 0x80000000, 0xFFFFFFFF, 0x7FFFFFFF }, /* VFP_REGS */ \
1182 { 0x00000000, 0x00007800, 0x00000000, 0x00000000 }, /* IWMMXT_GR_REGS */ \
1183 { 0x00000000, 0x7FFF8000, 0x00000000, 0x00000000 }, /* IWMMXT_REGS */ \
1184 { 0x000000FF, 0x00000000, 0x00000000, 0x00000000 }, /* LO_REGS */ \
1185 { 0x00002000, 0x00000000, 0x00000000, 0x00000000 }, /* STACK_REG */ \
1186 { 0x000020FF, 0x00000000, 0x00000000, 0x00000000 }, /* BASE_REGS */ \
1187 { 0x0000DF00, 0x00000000, 0x00000000, 0x00000000 }, /* HI_REGS */ \
1188 { 0x01000000, 0x00000000, 0x00000000, 0x00000000 }, /* CC_REG */ \
1189 { 0x00000000, 0x00000000, 0x00000000, 0x80000000 }, /* VFPCC_REG */ \
1190 { 0x0200DFFF, 0x00000000, 0x00000000, 0x00000000 }, /* GENERAL_REGS */ \
1191 { 0x0200FFFF, 0x00000000, 0x00000000, 0x00000000 }, /* CORE_REGS */ \
1192 { 0xFAFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0x7FFFFFFF } /* ALL_REGS */ \
1195 /* Any of the VFP register classes. */
1196 #define IS_VFP_CLASS(X) \
1197 ((X) == VFP_D0_D7_REGS || (X) == VFP_LO_REGS \
1198 || (X) == VFP_HI_REGS || (X) == VFP_REGS)
1200 /* The same information, inverted:
1201 Return the class number of the smallest class containing
1202 reg number REGNO. This could be a conditional expression
1203 or could index an array. */
1204 #define REGNO_REG_CLASS(REGNO) arm_regno_class (REGNO)
1206 /* The following macro defines cover classes for Integrated Register
1207 Allocator. Cover classes is a set of non-intersected register
1208 classes covering all hard registers used for register allocation
1209 purpose. Any move between two registers of a cover class should be
1210 cheaper than load or store of the registers. The macro value is
1211 array of register classes with LIM_REG_CLASSES used as the end
1214 #define IRA_COVER_CLASSES \
1216 GENERAL_REGS, FPA_REGS, CIRRUS_REGS, VFP_REGS, IWMMXT_GR_REGS, IWMMXT_REGS,\
1220 /* FPA registers can't do subreg as all values are reformatted to internal
1221 precision. VFP registers may only be accessed in the mode they
1223 #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
1224 (GET_MODE_SIZE (FROM) != GET_MODE_SIZE (TO) \
1225 ? reg_classes_intersect_p (FPA_REGS, (CLASS)) \
1226 || reg_classes_intersect_p (VFP_REGS, (CLASS)) \
1229 /* We need to define this for LO_REGS on thumb. Otherwise we can end up
1230 using r0-r4 for function arguments, r7 for the stack frame and don't
1231 have enough left over to do doubleword arithmetic. */
1232 #define CLASS_LIKELY_SPILLED_P(CLASS) \
1233 ((TARGET_THUMB && (CLASS) == LO_REGS) \
1234 || (CLASS) == CC_REG)
1236 /* The class value for index registers, and the one for base regs. */
1237 #define INDEX_REG_CLASS (TARGET_THUMB1 ? LO_REGS : GENERAL_REGS)
1238 #define BASE_REG_CLASS (TARGET_THUMB1 ? LO_REGS : CORE_REGS)
1240 /* For the Thumb the high registers cannot be used as base registers
1241 when addressing quantities in QI or HI mode; if we don't know the
1242 mode, then we must be conservative. */
1243 #define MODE_BASE_REG_CLASS(MODE) \
1244 (TARGET_32BIT ? CORE_REGS : \
1245 (((MODE) == SImode) ? BASE_REGS : LO_REGS))
1247 /* For Thumb we can not support SP+reg addressing, so we return LO_REGS
1248 instead of BASE_REGS. */
1249 #define MODE_BASE_REG_REG_CLASS(MODE) BASE_REG_CLASS
1251 /* When SMALL_REGISTER_CLASSES is nonzero, the compiler allows
1252 registers explicitly used in the rtl to be used as spill registers
1253 but prevents the compiler from extending the lifetime of these
1255 #define SMALL_REGISTER_CLASSES TARGET_THUMB1
1257 /* Given an rtx X being reloaded into a reg required to be
1258 in class CLASS, return the class of reg to actually use.
1259 In general this is just CLASS, but for the Thumb core registers and
1260 immediate constants we prefer a LO_REGS class or a subset. */
1261 #define PREFERRED_RELOAD_CLASS(X, CLASS) \
1262 (TARGET_ARM ? (CLASS) : \
1263 ((CLASS) == GENERAL_REGS || (CLASS) == HI_REGS \
1264 || (CLASS) == NO_REGS || (CLASS) == STACK_REG \
1265 ? LO_REGS : (CLASS)))
1267 /* Must leave BASE_REGS reloads alone */
1268 #define THUMB_SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
1269 ((CLASS) != LO_REGS && (CLASS) != BASE_REGS \
1270 ? ((true_regnum (X) == -1 ? LO_REGS \
1271 : (true_regnum (X) + HARD_REGNO_NREGS (0, MODE) > 8) ? LO_REGS \
1275 #define THUMB_SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \
1276 ((CLASS) != LO_REGS && (CLASS) != BASE_REGS \
1277 ? ((true_regnum (X) == -1 ? LO_REGS \
1278 : (true_regnum (X) + HARD_REGNO_NREGS (0, MODE) > 8) ? LO_REGS \
1282 /* Return the register class of a scratch register needed to copy IN into
1283 or out of a register in CLASS in MODE. If it can be done directly,
1284 NO_REGS is returned. */
1285 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \
1286 /* Restrict which direct reloads are allowed for VFP/iWMMXt regs. */ \
1287 ((TARGET_VFP && TARGET_HARD_FLOAT \
1288 && IS_VFP_CLASS (CLASS)) \
1289 ? coproc_secondary_reload_class (MODE, X, FALSE) \
1290 : (TARGET_IWMMXT && (CLASS) == IWMMXT_REGS) \
1291 ? coproc_secondary_reload_class (MODE, X, TRUE) \
1293 ? (((MODE) == HImode && ! arm_arch4 && true_regnum (X) == -1) \
1294 ? GENERAL_REGS : NO_REGS) \
1295 : THUMB_SECONDARY_OUTPUT_RELOAD_CLASS (CLASS, MODE, X))
1297 /* If we need to load shorts byte-at-a-time, then we need a scratch. */
1298 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
1299 /* Restrict which direct reloads are allowed for VFP/iWMMXt regs. */ \
1300 ((TARGET_VFP && TARGET_HARD_FLOAT \
1301 && IS_VFP_CLASS (CLASS)) \
1302 ? coproc_secondary_reload_class (MODE, X, FALSE) : \
1303 (TARGET_IWMMXT && (CLASS) == IWMMXT_REGS) ? \
1304 coproc_secondary_reload_class (MODE, X, TRUE) : \
1305 /* Cannot load constants into Cirrus registers. */ \
1306 (TARGET_MAVERICK && TARGET_HARD_FLOAT \
1307 && (CLASS) == CIRRUS_REGS \
1308 && (CONSTANT_P (X) || GET_CODE (X) == SYMBOL_REF)) \
1311 (((CLASS) == IWMMXT_REGS || (CLASS) == IWMMXT_GR_REGS) \
1312 && CONSTANT_P (X)) \
1314 (((MODE) == HImode && ! arm_arch4 \
1315 && (GET_CODE (X) == MEM \
1316 || ((GET_CODE (X) == REG || GET_CODE (X) == SUBREG) \
1317 && true_regnum (X) == -1))) \
1318 ? GENERAL_REGS : NO_REGS) \
1319 : THUMB_SECONDARY_INPUT_RELOAD_CLASS (CLASS, MODE, X)))
1321 /* Try a machine-dependent way of reloading an illegitimate address
1322 operand. If we find one, push the reload and jump to WIN. This
1323 macro is used in only one place: `find_reloads_address' in reload.c.
1325 For the ARM, we wish to handle large displacements off a base
1326 register by splitting the addend across a MOV and the mem insn.
1327 This can cut the number of reloads needed. */
1328 #define ARM_LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND, WIN) \
1331 if (GET_CODE (X) == PLUS \
1332 && GET_CODE (XEXP (X, 0)) == REG \
1333 && REGNO (XEXP (X, 0)) < FIRST_PSEUDO_REGISTER \
1334 && REG_MODE_OK_FOR_BASE_P (XEXP (X, 0), MODE) \
1335 && GET_CODE (XEXP (X, 1)) == CONST_INT) \
1337 HOST_WIDE_INT val = INTVAL (XEXP (X, 1)); \
1338 HOST_WIDE_INT low, high; \
1340 if (MODE == DImode || (MODE == DFmode && TARGET_SOFT_FLOAT)) \
1341 low = ((val & 0xf) ^ 0x8) - 0x8; \
1342 else if (TARGET_MAVERICK && TARGET_HARD_FLOAT) \
1343 /* Need to be careful, -256 is not a valid offset. */ \
1344 low = val >= 0 ? (val & 0xff) : -((-val) & 0xff); \
1345 else if (MODE == SImode \
1346 || (MODE == SFmode && TARGET_SOFT_FLOAT) \
1347 || ((MODE == HImode || MODE == QImode) && ! arm_arch4)) \
1348 /* Need to be careful, -4096 is not a valid offset. */ \
1349 low = val >= 0 ? (val & 0xfff) : -((-val) & 0xfff); \
1350 else if ((MODE == HImode || MODE == QImode) && arm_arch4) \
1351 /* Need to be careful, -256 is not a valid offset. */ \
1352 low = val >= 0 ? (val & 0xff) : -((-val) & 0xff); \
1353 else if (GET_MODE_CLASS (MODE) == MODE_FLOAT \
1354 && TARGET_HARD_FLOAT && TARGET_FPA) \
1355 /* Need to be careful, -1024 is not a valid offset. */ \
1356 low = val >= 0 ? (val & 0x3ff) : -((-val) & 0x3ff); \
1360 high = ((((val - low) & (unsigned HOST_WIDE_INT) 0xffffffff) \
1361 ^ (unsigned HOST_WIDE_INT) 0x80000000) \
1362 - (unsigned HOST_WIDE_INT) 0x80000000); \
1363 /* Check for overflow or zero */ \
1364 if (low == 0 || high == 0 || (high + low != val)) \
1367 /* Reload the high part into a base reg; leave the low part \
1369 X = gen_rtx_PLUS (GET_MODE (X), \
1370 gen_rtx_PLUS (GET_MODE (X), XEXP (X, 0), \
1373 push_reload (XEXP (X, 0), NULL_RTX, &XEXP (X, 0), NULL, \
1374 MODE_BASE_REG_CLASS (MODE), GET_MODE (X), \
1375 VOIDmode, 0, 0, OPNUM, TYPE); \
1381 /* XXX If an HImode FP+large_offset address is converted to an HImode
1382 SP+large_offset address, then reload won't know how to fix it. It sees
1383 only that SP isn't valid for HImode, and so reloads the SP into an index
1384 register, but the resulting address is still invalid because the offset
1385 is too big. We fix it here instead by reloading the entire address. */
1386 /* We could probably achieve better results by defining PROMOTE_MODE to help
1387 cope with the variances between the Thumb's signed and unsigned byte and
1388 halfword load instructions. */
1389 /* ??? This should be safe for thumb2, but we may be able to do better. */
1390 #define THUMB_LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND_L, WIN) \
1392 rtx new_x = thumb_legitimize_reload_address (&X, MODE, OPNUM, TYPE, IND_L); \
1400 #define LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND_LEVELS, WIN) \
1402 ARM_LEGITIMIZE_RELOAD_ADDRESS (X, MODE, OPNUM, TYPE, IND_LEVELS, WIN); \
1404 THUMB_LEGITIMIZE_RELOAD_ADDRESS (X, MODE, OPNUM, TYPE, IND_LEVELS, WIN)
1406 /* Return the maximum number of consecutive registers
1407 needed to represent mode MODE in a register of class CLASS.
1408 ARM regs are UNITS_PER_WORD bits while FPA regs can hold any FP mode */
1409 #define CLASS_MAX_NREGS(CLASS, MODE) \
1410 (((CLASS) == FPA_REGS || (CLASS) == CIRRUS_REGS) ? 1 : ARM_NUM_REGS (MODE))
1412 /* If defined, gives a class of registers that cannot be used as the
1413 operand of a SUBREG that changes the mode of the object illegally. */
1415 /* Moves between FPA_REGS and GENERAL_REGS are two memory insns. */
1416 #define REGISTER_MOVE_COST(MODE, FROM, TO) \
1418 ((FROM) == FPA_REGS && (TO) != FPA_REGS ? 20 : \
1419 (FROM) != FPA_REGS && (TO) == FPA_REGS ? 20 : \
1420 IS_VFP_CLASS (FROM) && !IS_VFP_CLASS (TO) ? 10 : \
1421 !IS_VFP_CLASS (FROM) && IS_VFP_CLASS (TO) ? 10 : \
1422 (FROM) == IWMMXT_REGS && (TO) != IWMMXT_REGS ? 4 : \
1423 (FROM) != IWMMXT_REGS && (TO) == IWMMXT_REGS ? 4 : \
1424 (FROM) == IWMMXT_GR_REGS || (TO) == IWMMXT_GR_REGS ? 20 : \
1425 (FROM) == CIRRUS_REGS && (TO) != CIRRUS_REGS ? 20 : \
1426 (FROM) != CIRRUS_REGS && (TO) == CIRRUS_REGS ? 20 : \
1429 ((FROM) == HI_REGS || (TO) == HI_REGS) ? 4 : 2)
1431 /* Stack layout; function entry, exit and calling. */
1433 /* Define this if pushing a word on the stack
1434 makes the stack pointer a smaller address. */
1435 #define STACK_GROWS_DOWNWARD 1
1437 /* Define this to nonzero if the nominal address of the stack frame
1438 is at the high-address end of the local variables;
1439 that is, each additional local variable allocated
1440 goes at a more negative offset in the frame. */
1441 #define FRAME_GROWS_DOWNWARD 1
1443 /* The amount of scratch space needed by _interwork_{r7,r11}_call_via_rN().
1444 When present, it is one word in size, and sits at the top of the frame,
1445 between the soft frame pointer and either r7 or r11.
1447 We only need _interwork_rM_call_via_rN() for -mcaller-super-interworking,
1448 and only then if some outgoing arguments are passed on the stack. It would
1449 be tempting to also check whether the stack arguments are passed by indirect
1450 calls, but there seems to be no reason in principle why a post-reload pass
1451 couldn't convert a direct call into an indirect one. */
1452 #define CALLER_INTERWORKING_SLOT_SIZE \
1453 (TARGET_CALLER_INTERWORKING \
1454 && crtl->outgoing_args_size != 0 \
1455 ? UNITS_PER_WORD : 0)
1457 /* Offset within stack frame to start allocating local variables at.
1458 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
1459 first local allocated. Otherwise, it is the offset to the BEGINNING
1460 of the first local allocated. */
1461 #define STARTING_FRAME_OFFSET 0
1463 /* If we generate an insn to push BYTES bytes,
1464 this says how many the stack pointer really advances by. */
1465 /* The push insns do not do this rounding implicitly.
1466 So don't define this. */
1467 /* #define PUSH_ROUNDING(NPUSHED) ROUND_UP_WORD (NPUSHED) */
1469 /* Define this if the maximum size of all the outgoing args is to be
1470 accumulated and pushed during the prologue. The amount can be
1471 found in the variable crtl->outgoing_args_size. */
1472 #define ACCUMULATE_OUTGOING_ARGS 1
1474 /* Offset of first parameter from the argument pointer register value. */
1475 #define FIRST_PARM_OFFSET(FNDECL) (TARGET_ARM ? 4 : 0)
1477 /* Value is the number of byte of arguments automatically
1478 popped when returning from a subroutine call.
1479 FUNDECL is the declaration node of the function (as a tree),
1480 FUNTYPE is the data type of the function (as a tree),
1481 or for a library call it is an identifier node for the subroutine name.
1482 SIZE is the number of bytes of arguments passed on the stack.
1484 On the ARM, the caller does not pop any of its arguments that were passed
1486 #define RETURN_POPS_ARGS(FUNDECL, FUNTYPE, SIZE) 0
1488 /* Define how to find the value returned by a library function
1489 assuming the value has mode MODE. */
1490 #define LIBCALL_VALUE(MODE) \
1491 (TARGET_32BIT && TARGET_HARD_FLOAT_ABI && TARGET_FPA \
1492 && GET_MODE_CLASS (MODE) == MODE_FLOAT \
1493 ? gen_rtx_REG (MODE, FIRST_FPA_REGNUM) \
1494 : TARGET_32BIT && TARGET_HARD_FLOAT_ABI && TARGET_MAVERICK \
1495 && GET_MODE_CLASS (MODE) == MODE_FLOAT \
1496 ? gen_rtx_REG (MODE, FIRST_CIRRUS_FP_REGNUM) \
1497 : TARGET_IWMMXT_ABI && arm_vector_mode_supported_p (MODE) \
1498 ? gen_rtx_REG (MODE, FIRST_IWMMXT_REGNUM) \
1499 : gen_rtx_REG (MODE, ARG_REGISTER (1)))
1501 /* Define how to find the value returned by a function.
1502 VALTYPE is the data type of the value (as a tree).
1503 If the precise function being called is known, FUNC is its FUNCTION_DECL;
1504 otherwise, FUNC is 0. */
1505 #define FUNCTION_VALUE(VALTYPE, FUNC) \
1506 arm_function_value (VALTYPE, FUNC);
1508 /* 1 if N is a possible register number for a function value.
1509 On the ARM, only r0 and f0 can return results. */
1510 /* On a Cirrus chip, mvf0 can return results. */
1511 #define FUNCTION_VALUE_REGNO_P(REGNO) \
1512 ((REGNO) == ARG_REGISTER (1) \
1513 || (TARGET_32BIT && ((REGNO) == FIRST_CIRRUS_FP_REGNUM) \
1514 && TARGET_HARD_FLOAT_ABI && TARGET_MAVERICK) \
1515 || ((REGNO) == FIRST_IWMMXT_REGNUM && TARGET_IWMMXT_ABI) \
1516 || (TARGET_32BIT && ((REGNO) == FIRST_FPA_REGNUM) \
1517 && TARGET_HARD_FLOAT_ABI && TARGET_FPA))
1519 /* Amount of memory needed for an untyped call to save all possible return
1521 #define APPLY_RESULT_SIZE arm_apply_result_size()
1523 /* Define DEFAULT_PCC_STRUCT_RETURN to 1 if all structure and union return
1524 values must be in memory. On the ARM, they need only do so if larger
1525 than a word, or if they contain elements offset from zero in the struct. */
1526 #define DEFAULT_PCC_STRUCT_RETURN 0
1528 /* These bits describe the different types of function supported
1529 by the ARM backend. They are exclusive. i.e. a function cannot be both a
1530 normal function and an interworked function, for example. Knowing the
1531 type of a function is important for determining its prologue and
1533 Note value 7 is currently unassigned. Also note that the interrupt
1534 function types all have bit 2 set, so that they can be tested for easily.
1535 Note that 0 is deliberately chosen for ARM_FT_UNKNOWN so that when the
1536 machine_function structure is initialized (to zero) func_type will
1537 default to unknown. This will force the first use of arm_current_func_type
1538 to call arm_compute_func_type. */
1539 #define ARM_FT_UNKNOWN 0 /* Type has not yet been determined. */
1540 #define ARM_FT_NORMAL 1 /* Your normal, straightforward function. */
1541 #define ARM_FT_INTERWORKED 2 /* A function that supports interworking. */
1542 #define ARM_FT_ISR 4 /* An interrupt service routine. */
1543 #define ARM_FT_FIQ 5 /* A fast interrupt service routine. */
1544 #define ARM_FT_EXCEPTION 6 /* An ARM exception handler (subcase of ISR). */
1546 #define ARM_FT_TYPE_MASK ((1 << 3) - 1)
1548 /* In addition functions can have several type modifiers,
1549 outlined by these bit masks: */
1550 #define ARM_FT_INTERRUPT (1 << 2) /* Note overlap with FT_ISR and above. */
1551 #define ARM_FT_NAKED (1 << 3) /* No prologue or epilogue. */
1552 #define ARM_FT_VOLATILE (1 << 4) /* Does not return. */
1553 #define ARM_FT_NESTED (1 << 5) /* Embedded inside another func. */
1554 #define ARM_FT_STACKALIGN (1 << 6) /* Called with misaligned stack. */
1556 /* Some macros to test these flags. */
1557 #define ARM_FUNC_TYPE(t) (t & ARM_FT_TYPE_MASK)
1558 #define IS_INTERRUPT(t) (t & ARM_FT_INTERRUPT)
1559 #define IS_VOLATILE(t) (t & ARM_FT_VOLATILE)
1560 #define IS_NAKED(t) (t & ARM_FT_NAKED)
1561 #define IS_NESTED(t) (t & ARM_FT_NESTED)
1562 #define IS_STACKALIGN(t) (t & ARM_FT_STACKALIGN)
1565 /* Structure used to hold the function stack frame layout. Offsets are
1566 relative to the stack pointer on function entry. Positive offsets are
1567 in the direction of stack growth.
1568 Only soft_frame is used in thumb mode. */
1570 typedef struct GTY(()) arm_stack_offsets
1572 int saved_args; /* ARG_POINTER_REGNUM. */
1573 int frame; /* ARM_HARD_FRAME_POINTER_REGNUM. */
1575 int soft_frame; /* FRAME_POINTER_REGNUM. */
1576 int locals_base; /* THUMB_HARD_FRAME_POINTER_REGNUM. */
1577 int outgoing_args; /* STACK_POINTER_REGNUM. */
1578 unsigned int saved_regs_mask;
1582 /* A C structure for machine-specific, per-function data.
1583 This is added to the cfun structure. */
1584 typedef struct GTY(()) machine_function
1586 /* Additional stack adjustment in __builtin_eh_throw. */
1587 rtx eh_epilogue_sp_ofs;
1588 /* Records if LR has to be saved for far jumps. */
1590 /* Records if ARG_POINTER was ever live. */
1591 int arg_pointer_live;
1592 /* Records if the save of LR has been eliminated. */
1593 int lr_save_eliminated;
1594 /* The size of the stack frame. Only valid after reload. */
1595 arm_stack_offsets stack_offsets;
1596 /* Records the type of the current function. */
1597 unsigned long func_type;
1598 /* Record if the function has a variable argument list. */
1599 int uses_anonymous_args;
1600 /* Records if sibcalls are blocked because an argument
1601 register is needed to preserve stack alignment. */
1602 int sibcall_blocked;
1603 /* The PIC register for this function. This might be a pseudo. */
1605 /* Labels for per-function Thumb call-via stubs. One per potential calling
1606 register. We can never call via LR or PC. We can call via SP if a
1607 trampoline happens to be on the top of the stack. */
1609 /* Set to 1 when a return insn is output, this means that the epilogue
1611 int return_used_this_function;
1615 /* As in the machine_function, a global set of call-via labels, for code
1616 that is in text_section. */
1617 extern GTY(()) rtx thumb_call_via_label[14];
1619 /* A C type for declaring a variable that is used as the first argument of
1620 `FUNCTION_ARG' and other related values. For some target machines, the
1621 type `int' suffices and can hold the number of bytes of argument so far. */
1624 /* This is the number of registers of arguments scanned so far. */
1626 /* This is the number of iWMMXt register arguments scanned so far. */
1633 /* Define where to put the arguments to a function.
1634 Value is zero to push the argument on the stack,
1635 or a hard register in which to store the argument.
1637 MODE is the argument's machine mode.
1638 TYPE is the data type of the argument (as a tree).
1639 This is null for libcalls where that information may
1641 CUM is a variable of type CUMULATIVE_ARGS which gives info about
1642 the preceding args and about the function being called.
1643 NAMED is nonzero if this argument is a named parameter
1644 (otherwise it is an extra parameter matching an ellipsis).
1646 On the ARM, normally the first 16 bytes are passed in registers r0-r3; all
1647 other arguments are passed on the stack. If (NAMED == 0) (which happens
1648 only in assign_parms, since TARGET_SETUP_INCOMING_VARARGS is
1649 defined), say it is passed in the stack (function_prologue will
1650 indeed make it pass in the stack if necessary). */
1651 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
1652 arm_function_arg (&(CUM), (MODE), (TYPE), (NAMED))
1654 #define FUNCTION_ARG_PADDING(MODE, TYPE) \
1655 (arm_pad_arg_upward (MODE, TYPE) ? upward : downward)
1657 #define BLOCK_REG_PADDING(MODE, TYPE, FIRST) \
1658 (arm_pad_reg_upward (MODE, TYPE, FIRST) ? upward : downward)
1660 /* For AAPCS, padding should never be below the argument. For other ABIs,
1661 * mimic the default. */
1662 #define PAD_VARARGS_DOWN \
1663 ((TARGET_AAPCS_BASED) ? 0 : BYTES_BIG_ENDIAN)
1665 /* Initialize a variable CUM of type CUMULATIVE_ARGS
1666 for a call to a function whose data type is FNTYPE.
1667 For a library call, FNTYPE is 0.
1668 On the ARM, the offset starts at 0. */
1669 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \
1670 arm_init_cumulative_args (&(CUM), (FNTYPE), (LIBNAME), (FNDECL))
1672 /* Update the data in CUM to advance over an argument
1673 of mode MODE and data type TYPE.
1674 (TYPE is null for libcalls where that information may not be available.) */
1675 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
1677 if (arm_vector_mode_supported_p (MODE) \
1678 && (CUM).named_count > (CUM).nargs \
1679 && TARGET_IWMMXT_ABI) \
1680 (CUM).iwmmxt_nregs += 1; \
1682 (CUM).nregs += ARM_NUM_REGS2 (MODE, TYPE)
1684 /* If defined, a C expression that gives the alignment boundary, in bits, of an
1685 argument with the specified mode and type. If it is not defined,
1686 `PARM_BOUNDARY' is used for all arguments. */
1687 #define FUNCTION_ARG_BOUNDARY(MODE,TYPE) \
1688 ((ARM_DOUBLEWORD_ALIGN && arm_needs_doubleword_align (MODE, TYPE)) \
1689 ? DOUBLEWORD_ALIGNMENT \
1692 /* 1 if N is a possible register number for function argument passing.
1693 On the ARM, r0-r3 are used to pass args. */
1694 #define FUNCTION_ARG_REGNO_P(REGNO) \
1695 (IN_RANGE ((REGNO), 0, 3) \
1696 || (TARGET_IWMMXT_ABI \
1697 && IN_RANGE ((REGNO), FIRST_IWMMXT_REGNUM, FIRST_IWMMXT_REGNUM + 9)))
1700 /* If your target environment doesn't prefix user functions with an
1701 underscore, you may wish to re-define this to prevent any conflicts. */
1702 #ifndef ARM_MCOUNT_NAME
1703 #define ARM_MCOUNT_NAME "*mcount"
1706 /* Call the function profiler with a given profile label. The Acorn
1707 compiler puts this BEFORE the prolog but gcc puts it afterwards.
1708 On the ARM the full profile code will look like:
1717 profile_function() in final.c outputs the .data section, FUNCTION_PROFILER
1718 will output the .text section.
1720 The ``mov ip,lr'' seems like a good idea to stick with cc convention.
1721 ``prof'' doesn't seem to mind about this!
1723 Note - this version of the code is designed to work in both ARM and
1725 #ifndef ARM_FUNCTION_PROFILER
1726 #define ARM_FUNCTION_PROFILER(STREAM, LABELNO) \
1731 asm_fprintf (STREAM, "\tmov\t%r, %r\n\tbl\t", \
1732 IP_REGNUM, LR_REGNUM); \
1733 assemble_name (STREAM, ARM_MCOUNT_NAME); \
1734 fputc ('\n', STREAM); \
1735 ASM_GENERATE_INTERNAL_LABEL (temp, "LP", LABELNO); \
1736 sym = gen_rtx_SYMBOL_REF (Pmode, temp); \
1737 assemble_aligned_integer (UNITS_PER_WORD, sym); \
1741 #ifdef THUMB_FUNCTION_PROFILER
1742 #define FUNCTION_PROFILER(STREAM, LABELNO) \
1744 ARM_FUNCTION_PROFILER (STREAM, LABELNO) \
1746 THUMB_FUNCTION_PROFILER (STREAM, LABELNO)
1748 #define FUNCTION_PROFILER(STREAM, LABELNO) \
1749 ARM_FUNCTION_PROFILER (STREAM, LABELNO)
1752 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
1753 the stack pointer does not matter. The value is tested only in
1754 functions that have frame pointers.
1755 No definition is equivalent to always zero.
1757 On the ARM, the function epilogue recovers the stack pointer from the
1759 #define EXIT_IGNORE_STACK 1
1761 #define EPILOGUE_USES(REGNO) ((REGNO) == LR_REGNUM)
1763 /* Determine if the epilogue should be output as RTL.
1764 You should override this if you define FUNCTION_EXTRA_EPILOGUE. */
1765 /* This is disabled for Thumb-2 because it will confuse the
1766 conditional insn counter. */
1767 #define USE_RETURN_INSN(ISCOND) \
1768 (TARGET_ARM ? use_return_insn (ISCOND, NULL) : 0)
1770 /* Definitions for register eliminations.
1772 This is an array of structures. Each structure initializes one pair
1773 of eliminable registers. The "from" register number is given first,
1774 followed by "to". Eliminations of the same "from" register are listed
1775 in order of preference.
1777 We have two registers that can be eliminated on the ARM. First, the
1778 arg pointer register can often be eliminated in favor of the stack
1779 pointer register. Secondly, the pseudo frame pointer register can always
1780 be eliminated; it is replaced with either the stack or the real frame
1781 pointer. Note we have to use {ARM|THUMB}_HARD_FRAME_POINTER_REGNUM
1782 because the definition of HARD_FRAME_POINTER_REGNUM is not a constant. */
1784 #define ELIMINABLE_REGS \
1785 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM },\
1786 { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM },\
1787 { ARG_POINTER_REGNUM, ARM_HARD_FRAME_POINTER_REGNUM },\
1788 { ARG_POINTER_REGNUM, THUMB_HARD_FRAME_POINTER_REGNUM },\
1789 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM },\
1790 { FRAME_POINTER_REGNUM, ARM_HARD_FRAME_POINTER_REGNUM },\
1791 { FRAME_POINTER_REGNUM, THUMB_HARD_FRAME_POINTER_REGNUM }}
1793 /* Given FROM and TO register numbers, say whether this elimination is
1794 allowed. Frame pointer elimination is automatically handled.
1796 All eliminations are permissible. Note that ARG_POINTER_REGNUM and
1797 HARD_FRAME_POINTER_REGNUM are in fact the same thing. If we need a frame
1798 pointer, we must eliminate FRAME_POINTER_REGNUM into
1799 HARD_FRAME_POINTER_REGNUM and not into STACK_POINTER_REGNUM or
1800 ARG_POINTER_REGNUM. */
1801 #define CAN_ELIMINATE(FROM, TO) \
1802 (((TO) == FRAME_POINTER_REGNUM && (FROM) == ARG_POINTER_REGNUM) ? 0 : \
1803 ((TO) == STACK_POINTER_REGNUM && frame_pointer_needed) ? 0 : \
1804 ((TO) == ARM_HARD_FRAME_POINTER_REGNUM && TARGET_THUMB) ? 0 : \
1805 ((TO) == THUMB_HARD_FRAME_POINTER_REGNUM && TARGET_ARM) ? 0 : \
1808 /* Define the offset between two registers, one to be eliminated, and the
1809 other its replacement, at the start of a routine. */
1810 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1812 (OFFSET) = arm_compute_initial_elimination_offset (FROM, TO); \
1814 (OFFSET) = thumb_compute_initial_elimination_offset (FROM, TO)
1816 /* Special case handling of the location of arguments passed on the stack. */
1817 #define DEBUGGER_ARG_OFFSET(value, addr) value ? value : arm_debugger_arg_offset (value, addr)
1819 /* Initialize data used by insn expanders. This is called from insn_emit,
1820 once for every function before code is generated. */
1821 #define INIT_EXPANDERS arm_init_expanders ()
1823 /* Output assembler code for a block containing the constant parts
1824 of a trampoline, leaving space for the variable parts.
1826 On the ARM, (if r8 is the static chain regnum, and remembering that
1827 referencing pc adds an offset of 8) the trampoline looks like:
1830 .word static chain value
1831 .word function's address
1832 XXX FIXME: When the trampoline returns, r8 will be clobbered. */
1833 #define ARM_TRAMPOLINE_TEMPLATE(FILE) \
1835 asm_fprintf (FILE, "\tldr\t%r, [%r, #0]\n", \
1836 STATIC_CHAIN_REGNUM, PC_REGNUM); \
1837 asm_fprintf (FILE, "\tldr\t%r, [%r, #0]\n", \
1838 PC_REGNUM, PC_REGNUM); \
1839 assemble_aligned_integer (UNITS_PER_WORD, const0_rtx); \
1840 assemble_aligned_integer (UNITS_PER_WORD, const0_rtx); \
1843 /* The Thumb-2 trampoline is similar to the arm implementation.
1844 Unlike 16-bit Thumb, we enter the stub in thumb mode. */
1845 #define THUMB2_TRAMPOLINE_TEMPLATE(FILE) \
1847 asm_fprintf (FILE, "\tldr.w\t%r, [%r, #4]\n", \
1848 STATIC_CHAIN_REGNUM, PC_REGNUM); \
1849 asm_fprintf (FILE, "\tldr.w\t%r, [%r, #4]\n", \
1850 PC_REGNUM, PC_REGNUM); \
1851 assemble_aligned_integer (UNITS_PER_WORD, const0_rtx); \
1852 assemble_aligned_integer (UNITS_PER_WORD, const0_rtx); \
1855 #define THUMB1_TRAMPOLINE_TEMPLATE(FILE) \
1857 ASM_OUTPUT_ALIGN(FILE, 2); \
1858 fprintf (FILE, "\t.code\t16\n"); \
1859 fprintf (FILE, ".Ltrampoline_start:\n"); \
1860 asm_fprintf (FILE, "\tpush\t{r0, r1}\n"); \
1861 asm_fprintf (FILE, "\tldr\tr0, [%r, #8]\n", \
1863 asm_fprintf (FILE, "\tmov\t%r, r0\n", \
1864 STATIC_CHAIN_REGNUM); \
1865 asm_fprintf (FILE, "\tldr\tr0, [%r, #8]\n", \
1867 asm_fprintf (FILE, "\tstr\tr0, [%r, #4]\n", \
1869 asm_fprintf (FILE, "\tpop\t{r0, %r}\n", \
1871 assemble_aligned_integer (UNITS_PER_WORD, const0_rtx); \
1872 assemble_aligned_integer (UNITS_PER_WORD, const0_rtx); \
1875 #define TRAMPOLINE_TEMPLATE(FILE) \
1877 ARM_TRAMPOLINE_TEMPLATE (FILE) \
1878 else if (TARGET_THUMB2) \
1879 THUMB2_TRAMPOLINE_TEMPLATE (FILE) \
1881 THUMB1_TRAMPOLINE_TEMPLATE (FILE)
1883 /* Thumb trampolines should be entered in thumb mode, so set the bottom bit
1885 #define TRAMPOLINE_ADJUST_ADDRESS(ADDR) do \
1888 (ADDR) = expand_simple_binop (Pmode, IOR, (ADDR), GEN_INT(1), \
1889 gen_reg_rtx (Pmode), 0, OPTAB_LIB_WIDEN); \
1892 /* Length in units of the trampoline for entering a nested function. */
1893 #define TRAMPOLINE_SIZE (TARGET_32BIT ? 16 : 20)
1895 /* Alignment required for a trampoline in bits. */
1896 #define TRAMPOLINE_ALIGNMENT 32
1899 /* Emit RTL insns to initialize the variable parts of a trampoline.
1900 FNADDR is an RTX for the address of the function's pure code.
1901 CXT is an RTX for the static chain value for the function. */
1902 #ifndef INITIALIZE_TRAMPOLINE
1903 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
1905 emit_move_insn (gen_rtx_MEM (SImode, \
1906 plus_constant (TRAMP, \
1907 TARGET_32BIT ? 8 : 12)), \
1909 emit_move_insn (gen_rtx_MEM (SImode, \
1910 plus_constant (TRAMP, \
1911 TARGET_32BIT ? 12 : 16)), \
1913 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, "__clear_cache"), \
1914 LCT_NORMAL, VOIDmode, 2, TRAMP, Pmode, \
1915 plus_constant (TRAMP, TRAMPOLINE_SIZE), Pmode); \
1920 /* Addressing modes, and classification of registers for them. */
1921 #define HAVE_POST_INCREMENT 1
1922 #define HAVE_PRE_INCREMENT TARGET_32BIT
1923 #define HAVE_POST_DECREMENT TARGET_32BIT
1924 #define HAVE_PRE_DECREMENT TARGET_32BIT
1925 #define HAVE_PRE_MODIFY_DISP TARGET_32BIT
1926 #define HAVE_POST_MODIFY_DISP TARGET_32BIT
1927 #define HAVE_PRE_MODIFY_REG TARGET_32BIT
1928 #define HAVE_POST_MODIFY_REG TARGET_32BIT
1930 /* Macros to check register numbers against specific register classes. */
1932 /* These assume that REGNO is a hard or pseudo reg number.
1933 They give nonzero only if REGNO is a hard reg of the suitable class
1934 or a pseudo reg currently allocated to a suitable hard reg.
1935 Since they use reg_renumber, they are safe only once reg_renumber
1936 has been allocated, which happens in local-alloc.c. */
1937 #define TEST_REGNO(R, TEST, VALUE) \
1938 ((R TEST VALUE) || ((unsigned) reg_renumber[R] TEST VALUE))
1940 /* Don't allow the pc to be used. */
1941 #define ARM_REGNO_OK_FOR_BASE_P(REGNO) \
1942 (TEST_REGNO (REGNO, <, PC_REGNUM) \
1943 || TEST_REGNO (REGNO, ==, FRAME_POINTER_REGNUM) \
1944 || TEST_REGNO (REGNO, ==, ARG_POINTER_REGNUM))
1946 #define THUMB1_REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \
1947 (TEST_REGNO (REGNO, <=, LAST_LO_REGNUM) \
1948 || (GET_MODE_SIZE (MODE) >= 4 \
1949 && TEST_REGNO (REGNO, ==, STACK_POINTER_REGNUM)))
1951 #define REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \
1953 ? THUMB1_REGNO_MODE_OK_FOR_BASE_P (REGNO, MODE) \
1954 : ARM_REGNO_OK_FOR_BASE_P (REGNO))
1956 /* Nonzero if X can be the base register in a reg+reg addressing mode.
1957 For Thumb, we can not use SP + reg, so reject SP. */
1958 #define REGNO_MODE_OK_FOR_REG_BASE_P(X, MODE) \
1959 REGNO_MODE_OK_FOR_BASE_P (X, QImode)
1961 /* For ARM code, we don't care about the mode, but for Thumb, the index
1962 must be suitable for use in a QImode load. */
1963 #define REGNO_OK_FOR_INDEX_P(REGNO) \
1964 (REGNO_MODE_OK_FOR_BASE_P (REGNO, QImode) \
1965 && !TEST_REGNO (REGNO, ==, STACK_POINTER_REGNUM))
1967 /* Maximum number of registers that can appear in a valid memory address.
1968 Shifts in addresses can't be by a register. */
1969 #define MAX_REGS_PER_ADDRESS 2
1971 /* Recognize any constant value that is a valid address. */
1972 /* XXX We can address any constant, eventually... */
1973 /* ??? Should the TARGET_ARM here also apply to thumb2? */
1974 #define CONSTANT_ADDRESS_P(X) \
1975 (GET_CODE (X) == SYMBOL_REF \
1976 && (CONSTANT_POOL_ADDRESS_P (X) \
1977 || (TARGET_ARM && optimize > 0 && SYMBOL_REF_FLAG (X))))
1979 /* True if SYMBOL + OFFSET constants must refer to something within
1980 SYMBOL's section. */
1981 #define ARM_OFFSETS_MUST_BE_WITHIN_SECTIONS_P 0
1983 /* Nonzero if all target requires all absolute relocations be R_ARM_ABS32. */
1984 #ifndef TARGET_DEFAULT_WORD_RELOCATIONS
1985 #define TARGET_DEFAULT_WORD_RELOCATIONS 0
1988 /* Nonzero if the constant value X is a legitimate general operand.
1989 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE.
1991 On the ARM, allow any integer (invalid ones are removed later by insn
1992 patterns), nice doubles and symbol_refs which refer to the function's
1995 When generating pic allow anything. */
1996 #define ARM_LEGITIMATE_CONSTANT_P(X) (flag_pic || ! label_mentioned_p (X))
1998 #define THUMB_LEGITIMATE_CONSTANT_P(X) \
1999 ( GET_CODE (X) == CONST_INT \
2000 || GET_CODE (X) == CONST_DOUBLE \
2001 || CONSTANT_ADDRESS_P (X) \
2004 #define LEGITIMATE_CONSTANT_P(X) \
2005 (!arm_cannot_force_const_mem (X) \
2006 && (TARGET_32BIT ? ARM_LEGITIMATE_CONSTANT_P (X) \
2007 : THUMB_LEGITIMATE_CONSTANT_P (X)))
2009 #ifndef SUBTARGET_NAME_ENCODING_LENGTHS
2010 #define SUBTARGET_NAME_ENCODING_LENGTHS
2013 /* This is a C fragment for the inside of a switch statement.
2014 Each case label should return the number of characters to
2015 be stripped from the start of a function's name, if that
2016 name starts with the indicated character. */
2017 #define ARM_NAME_ENCODING_LENGTHS \
2018 case '*': return 1; \
2019 SUBTARGET_NAME_ENCODING_LENGTHS
2021 /* This is how to output a reference to a user-level label named NAME.
2022 `assemble_name' uses this. */
2023 #undef ASM_OUTPUT_LABELREF
2024 #define ASM_OUTPUT_LABELREF(FILE, NAME) \
2025 arm_asm_output_labelref (FILE, NAME)
2027 /* Output IT instructions for conditionally executed Thumb-2 instructions. */
2028 #define ASM_OUTPUT_OPCODE(STREAM, PTR) \
2029 if (TARGET_THUMB2) \
2030 thumb2_asm_output_opcode (STREAM);
2032 /* The EABI specifies that constructors should go in .init_array.
2033 Other targets use .ctors for compatibility. */
2034 #ifndef ARM_EABI_CTORS_SECTION_OP
2035 #define ARM_EABI_CTORS_SECTION_OP \
2036 "\t.section\t.init_array,\"aw\",%init_array"
2038 #ifndef ARM_EABI_DTORS_SECTION_OP
2039 #define ARM_EABI_DTORS_SECTION_OP \
2040 "\t.section\t.fini_array,\"aw\",%fini_array"
2042 #define ARM_CTORS_SECTION_OP \
2043 "\t.section\t.ctors,\"aw\",%progbits"
2044 #define ARM_DTORS_SECTION_OP \
2045 "\t.section\t.dtors,\"aw\",%progbits"
2047 /* Define CTORS_SECTION_ASM_OP. */
2048 #undef CTORS_SECTION_ASM_OP
2049 #undef DTORS_SECTION_ASM_OP
2051 # define CTORS_SECTION_ASM_OP \
2052 (TARGET_AAPCS_BASED ? ARM_EABI_CTORS_SECTION_OP : ARM_CTORS_SECTION_OP)
2053 # define DTORS_SECTION_ASM_OP \
2054 (TARGET_AAPCS_BASED ? ARM_EABI_DTORS_SECTION_OP : ARM_DTORS_SECTION_OP)
2055 #else /* !defined (IN_LIBGCC2) */
2056 /* In libgcc, CTORS_SECTION_ASM_OP must be a compile-time constant,
2057 so we cannot use the definition above. */
2058 # ifdef __ARM_EABI__
2059 /* The .ctors section is not part of the EABI, so we do not define
2060 CTORS_SECTION_ASM_OP when in libgcc; that prevents crtstuff
2061 from trying to use it. We do define it when doing normal
2062 compilation, as .init_array can be used instead of .ctors. */
2063 /* There is no need to emit begin or end markers when using
2064 init_array; the dynamic linker will compute the size of the
2065 array itself based on special symbols created by the static
2066 linker. However, we do need to arrange to set up
2067 exception-handling here. */
2068 # define CTOR_LIST_BEGIN asm (ARM_EABI_CTORS_SECTION_OP)
2069 # define CTOR_LIST_END /* empty */
2070 # define DTOR_LIST_BEGIN asm (ARM_EABI_DTORS_SECTION_OP)
2071 # define DTOR_LIST_END /* empty */
2072 # else /* !defined (__ARM_EABI__) */
2073 # define CTORS_SECTION_ASM_OP ARM_CTORS_SECTION_OP
2074 # define DTORS_SECTION_ASM_OP ARM_DTORS_SECTION_OP
2075 # endif /* !defined (__ARM_EABI__) */
2076 #endif /* !defined (IN_LIBCC2) */
2078 /* True if the operating system can merge entities with vague linkage
2079 (e.g., symbols in COMDAT group) during dynamic linking. */
2080 #ifndef TARGET_ARM_DYNAMIC_VAGUE_LINKAGE_P
2081 #define TARGET_ARM_DYNAMIC_VAGUE_LINKAGE_P true
2084 #define ARM_OUTPUT_FN_UNWIND(F, PROLOGUE) arm_output_fn_unwind (F, PROLOGUE)
2086 #ifdef TARGET_UNWIND_INFO
2087 #define ARM_EABI_UNWIND_TABLES \
2088 ((!USING_SJLJ_EXCEPTIONS && flag_exceptions) || flag_unwind_tables)
2090 #define ARM_EABI_UNWIND_TABLES 0
2093 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
2094 and check its validity for a certain class.
2095 We have two alternate definitions for each of them.
2096 The usual definition accepts all pseudo regs; the other rejects
2097 them unless they have been allocated suitable hard regs.
2098 The symbol REG_OK_STRICT causes the latter definition to be used.
2099 Thumb-2 has the same restrictions as arm. */
2100 #ifndef REG_OK_STRICT
2102 #define ARM_REG_OK_FOR_BASE_P(X) \
2103 (REGNO (X) <= LAST_ARM_REGNUM \
2104 || REGNO (X) >= FIRST_PSEUDO_REGISTER \
2105 || REGNO (X) == FRAME_POINTER_REGNUM \
2106 || REGNO (X) == ARG_POINTER_REGNUM)
2108 #define ARM_REG_OK_FOR_INDEX_P(X) \
2109 ((REGNO (X) <= LAST_ARM_REGNUM \
2110 && REGNO (X) != STACK_POINTER_REGNUM) \
2111 || REGNO (X) >= FIRST_PSEUDO_REGISTER \
2112 || REGNO (X) == FRAME_POINTER_REGNUM \
2113 || REGNO (X) == ARG_POINTER_REGNUM)
2115 #define THUMB1_REG_MODE_OK_FOR_BASE_P(X, MODE) \
2116 (REGNO (X) <= LAST_LO_REGNUM \
2117 || REGNO (X) >= FIRST_PSEUDO_REGISTER \
2118 || (GET_MODE_SIZE (MODE) >= 4 \
2119 && (REGNO (X) == STACK_POINTER_REGNUM \
2120 || (X) == hard_frame_pointer_rtx \
2121 || (X) == arg_pointer_rtx)))
2123 #define REG_STRICT_P 0
2125 #else /* REG_OK_STRICT */
2127 #define ARM_REG_OK_FOR_BASE_P(X) \
2128 ARM_REGNO_OK_FOR_BASE_P (REGNO (X))
2130 #define ARM_REG_OK_FOR_INDEX_P(X) \
2131 ARM_REGNO_OK_FOR_INDEX_P (REGNO (X))
2133 #define THUMB1_REG_MODE_OK_FOR_BASE_P(X, MODE) \
2134 THUMB1_REGNO_MODE_OK_FOR_BASE_P (REGNO (X), MODE)
2136 #define REG_STRICT_P 1
2138 #endif /* REG_OK_STRICT */
2140 /* Now define some helpers in terms of the above. */
2142 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \
2144 ? THUMB1_REG_MODE_OK_FOR_BASE_P (X, MODE) \
2145 : ARM_REG_OK_FOR_BASE_P (X))
2147 /* For 16-bit Thumb, a valid index register is anything that can be used in
2148 a byte load instruction. */
2149 #define THUMB1_REG_OK_FOR_INDEX_P(X) \
2150 THUMB1_REG_MODE_OK_FOR_BASE_P (X, QImode)
2152 /* Nonzero if X is a hard reg that can be used as an index
2153 or if it is a pseudo reg. On the Thumb, the stack pointer
2155 #define REG_OK_FOR_INDEX_P(X) \
2157 ? THUMB1_REG_OK_FOR_INDEX_P (X) \
2158 : ARM_REG_OK_FOR_INDEX_P (X))
2160 /* Nonzero if X can be the base register in a reg+reg addressing mode.
2161 For Thumb, we can not use SP + reg, so reject SP. */
2162 #define REG_MODE_OK_FOR_REG_BASE_P(X, MODE) \
2163 REG_OK_FOR_INDEX_P (X)
2165 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
2166 that is a valid memory address for an instruction.
2167 The MODE argument is the machine mode for the MEM expression
2168 that wants to use this address. */
2170 #define ARM_BASE_REGISTER_RTX_P(X) \
2171 (GET_CODE (X) == REG && ARM_REG_OK_FOR_BASE_P (X))
2173 #define ARM_INDEX_REGISTER_RTX_P(X) \
2174 (GET_CODE (X) == REG && ARM_REG_OK_FOR_INDEX_P (X))
2176 #define ARM_GO_IF_LEGITIMATE_ADDRESS(MODE,X,WIN) \
2178 if (arm_legitimate_address_p (MODE, X, SET, REG_STRICT_P)) \
2182 #define THUMB2_GO_IF_LEGITIMATE_ADDRESS(MODE,X,WIN) \
2184 if (thumb2_legitimate_address_p (MODE, X, REG_STRICT_P)) \
2188 #define THUMB1_GO_IF_LEGITIMATE_ADDRESS(MODE,X,WIN) \
2190 if (thumb1_legitimate_address_p (MODE, X, REG_STRICT_P)) \
2194 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, WIN) \
2196 ARM_GO_IF_LEGITIMATE_ADDRESS (MODE, X, WIN) \
2197 else if (TARGET_THUMB2) \
2198 THUMB2_GO_IF_LEGITIMATE_ADDRESS (MODE, X, WIN) \
2199 else /* if (TARGET_THUMB1) */ \
2200 THUMB1_GO_IF_LEGITIMATE_ADDRESS (MODE, X, WIN)
2203 /* Define this for compatibility reasons. */
2204 #define HANDLE_PRAGMA_PACK_PUSH_POP
2206 /* Specify the machine mode that this machine uses
2207 for the index in the tablejump instruction. */
2208 #define CASE_VECTOR_MODE Pmode
2210 #define CASE_VECTOR_PC_RELATIVE TARGET_THUMB2
2212 #define CASE_VECTOR_SHORTEN_MODE(min, max, body) \
2213 ((min < 0 || max >= 0x2000 || !TARGET_THUMB2) ? SImode \
2214 : (max >= 0x200) ? HImode \
2217 /* signed 'char' is most compatible, but RISC OS wants it unsigned.
2218 unsigned is probably best, but may break some code. */
2219 #ifndef DEFAULT_SIGNED_CHAR
2220 #define DEFAULT_SIGNED_CHAR 0
2223 /* Max number of bytes we can move from memory to memory
2224 in one reasonably fast instruction. */
2228 #define MOVE_RATIO(speed) (arm_tune_xscale ? 4 : 2)
2230 /* Define if operations between registers always perform the operation
2231 on the full register even if a narrower mode is specified. */
2232 #define WORD_REGISTER_OPERATIONS
2234 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
2235 will either zero-extend or sign-extend. The value of this macro should
2236 be the code that says which one of the two operations is implicitly
2237 done, UNKNOWN if none. */
2238 #define LOAD_EXTEND_OP(MODE) \
2239 (TARGET_THUMB ? ZERO_EXTEND : \
2240 ((arm_arch4 || (MODE) == QImode) ? ZERO_EXTEND \
2241 : ((BYTES_BIG_ENDIAN && (MODE) == HImode) ? SIGN_EXTEND : UNKNOWN)))
2243 /* Nonzero if access to memory by bytes is slow and undesirable. */
2244 #define SLOW_BYTE_ACCESS 0
2246 #define SLOW_UNALIGNED_ACCESS(MODE, ALIGN) 1
2248 /* Immediate shift counts are truncated by the output routines (or was it
2249 the assembler?). Shift counts in a register are truncated by ARM. Note
2250 that the native compiler puts too large (> 32) immediate shift counts
2251 into a register and shifts by the register, letting the ARM decide what
2252 to do instead of doing that itself. */
2253 /* This is all wrong. Defining SHIFT_COUNT_TRUNCATED tells combine that
2254 code like (X << (Y % 32)) for register X, Y is equivalent to (X << Y).
2255 On the arm, Y in a register is used modulo 256 for the shift. Only for
2256 rotates is modulo 32 used. */
2257 /* #define SHIFT_COUNT_TRUNCATED 1 */
2259 /* All integers have the same format so truncation is easy. */
2260 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
2262 /* Calling from registers is a massive pain. */
2263 #define NO_FUNCTION_CSE 1
2265 /* The machine modes of pointers and functions */
2266 #define Pmode SImode
2267 #define FUNCTION_MODE Pmode
2269 #define ARM_FRAME_RTX(X) \
2270 ( (X) == frame_pointer_rtx || (X) == stack_pointer_rtx \
2271 || (X) == arg_pointer_rtx)
2273 /* Moves to and from memory are quite expensive */
2274 #define MEMORY_MOVE_COST(M, CLASS, IN) \
2275 (TARGET_32BIT ? 10 : \
2276 ((GET_MODE_SIZE (M) < 4 ? 8 : 2 * GET_MODE_SIZE (M)) \
2277 * (CLASS == LO_REGS ? 1 : 2)))
2279 /* Try to generate sequences that don't involve branches, we can then use
2280 conditional instructions */
2281 #define BRANCH_COST(speed_p, predictable_p) \
2282 (TARGET_32BIT ? 4 : (optimize > 0 ? 2 : 0))
2284 /* Position Independent Code. */
2285 /* We decide which register to use based on the compilation options and
2286 the assembler in use; this is more general than the APCS restriction of
2287 using sb (r9) all the time. */
2288 extern unsigned arm_pic_register;
2290 /* The register number of the register used to address a table of static
2291 data addresses in memory. */
2292 #define PIC_OFFSET_TABLE_REGNUM arm_pic_register
2294 /* We can't directly access anything that contains a symbol,
2295 nor can we indirect via the constant pool. One exception is
2296 UNSPEC_TLS, which is always PIC. */
2297 #define LEGITIMATE_PIC_OPERAND_P(X) \
2298 (!(symbol_mentioned_p (X) \
2299 || label_mentioned_p (X) \
2300 || (GET_CODE (X) == SYMBOL_REF \
2301 && CONSTANT_POOL_ADDRESS_P (X) \
2302 && (symbol_mentioned_p (get_pool_constant (X)) \
2303 || label_mentioned_p (get_pool_constant (X))))) \
2304 || tls_mentioned_p (X))
2306 /* We need to know when we are making a constant pool; this determines
2307 whether data needs to be in the GOT or can be referenced via a GOT
2309 extern int making_const_table;
2311 /* Handle pragmas for compatibility with Intel's compilers. */
2312 /* Also abuse this to register additional C specific EABI attributes. */
2313 #define REGISTER_TARGET_PRAGMAS() do { \
2314 c_register_pragma (0, "long_calls", arm_pr_long_calls); \
2315 c_register_pragma (0, "no_long_calls", arm_pr_no_long_calls); \
2316 c_register_pragma (0, "long_calls_off", arm_pr_long_calls_off); \
2317 arm_lang_object_attributes_init(); \
2320 /* Condition code information. */
2321 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
2322 return the mode to be used for the comparison. */
2324 #define SELECT_CC_MODE(OP, X, Y) arm_select_cc_mode (OP, X, Y)
2326 #define REVERSIBLE_CC_MODE(MODE) 1
2328 #define REVERSE_CONDITION(CODE,MODE) \
2329 (((MODE) == CCFPmode || (MODE) == CCFPEmode) \
2330 ? reverse_condition_maybe_unordered (code) \
2331 : reverse_condition (code))
2333 #define CANONICALIZE_COMPARISON(CODE, OP0, OP1) \
2336 if (GET_CODE (OP1) == CONST_INT \
2337 && ! (const_ok_for_arm (INTVAL (OP1)) \
2338 || (const_ok_for_arm (- INTVAL (OP1))))) \
2340 rtx const_op = OP1; \
2341 CODE = arm_canonicalize_comparison ((CODE), GET_MODE (OP0), \
2348 /* The arm5 clz instruction returns 32. */
2349 #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) ((VALUE) = 32, 1)
2352 #define ASM_APP_OFF (TARGET_THUMB1 ? "\t.code\t16\n" : \
2353 TARGET_THUMB2 ? "\t.thumb\n" : "")
2355 /* Output a push or a pop instruction (only used when profiling). */
2356 #define ASM_OUTPUT_REG_PUSH(STREAM, REGNO) \
2360 asm_fprintf (STREAM,"\tstmfd\t%r!,{%r}\n", \
2361 STACK_POINTER_REGNUM, REGNO); \
2363 asm_fprintf (STREAM, "\tpush {%r}\n", REGNO); \
2367 #define ASM_OUTPUT_REG_POP(STREAM, REGNO) \
2371 asm_fprintf (STREAM, "\tldmfd\t%r!,{%r}\n", \
2372 STACK_POINTER_REGNUM, REGNO); \
2374 asm_fprintf (STREAM, "\tpop {%r}\n", REGNO); \
2377 /* Jump table alignment is explicit in ASM_OUTPUT_CASE_LABEL. */
2378 #define ADDR_VEC_ALIGN(JUMPTABLE) 0
2380 /* This is how to output a label which precedes a jumptable. Since
2381 Thumb instructions are 2 bytes, we may need explicit alignment here. */
2382 #undef ASM_OUTPUT_CASE_LABEL
2383 #define ASM_OUTPUT_CASE_LABEL(FILE, PREFIX, NUM, JUMPTABLE) \
2386 if (TARGET_THUMB && GET_MODE (PATTERN (JUMPTABLE)) == SImode) \
2387 ASM_OUTPUT_ALIGN (FILE, 2); \
2388 (*targetm.asm_out.internal_label) (FILE, PREFIX, NUM); \
2392 /* Make sure subsequent insns are aligned after a TBB. */
2393 #define ASM_OUTPUT_CASE_END(FILE, NUM, JUMPTABLE) \
2396 if (GET_MODE (PATTERN (JUMPTABLE)) == QImode) \
2397 ASM_OUTPUT_ALIGN (FILE, 1); \
2401 #define ARM_DECLARE_FUNCTION_NAME(STREAM, NAME, DECL) \
2406 if (is_called_in_ARM_mode (DECL) \
2407 || (TARGET_THUMB1 && !TARGET_THUMB1_ONLY \
2408 && cfun->is_thunk)) \
2409 fprintf (STREAM, "\t.code 32\n") ; \
2410 else if (TARGET_THUMB1) \
2411 fprintf (STREAM, "\t.code\t16\n\t.thumb_func\n") ; \
2413 fprintf (STREAM, "\t.thumb\n\t.thumb_func\n") ; \
2415 if (TARGET_POKE_FUNCTION_NAME) \
2416 arm_poke_function_name (STREAM, (const char *) NAME); \
2420 /* For aliases of functions we use .thumb_set instead. */
2421 #define ASM_OUTPUT_DEF_FROM_DECLS(FILE, DECL1, DECL2) \
2424 const char *const LABEL1 = XSTR (XEXP (DECL_RTL (decl), 0), 0); \
2425 const char *const LABEL2 = IDENTIFIER_POINTER (DECL2); \
2427 if (TARGET_THUMB && TREE_CODE (DECL1) == FUNCTION_DECL) \
2429 fprintf (FILE, "\t.thumb_set "); \
2430 assemble_name (FILE, LABEL1); \
2431 fprintf (FILE, ","); \
2432 assemble_name (FILE, LABEL2); \
2433 fprintf (FILE, "\n"); \
2436 ASM_OUTPUT_DEF (FILE, LABEL1, LABEL2); \
2440 #ifdef HAVE_GAS_MAX_SKIP_P2ALIGN
2441 /* To support -falign-* switches we need to use .p2align so
2442 that alignment directives in code sections will be padded
2443 with no-op instructions, rather than zeroes. */
2444 #define ASM_OUTPUT_MAX_SKIP_ALIGN(FILE, LOG, MAX_SKIP) \
2447 if ((MAX_SKIP) == 0) \
2448 fprintf ((FILE), "\t.p2align %d\n", (int) (LOG)); \
2450 fprintf ((FILE), "\t.p2align %d,,%d\n", \
2451 (int) (LOG), (int) (MAX_SKIP)); \
2455 /* Add two bytes to the length of conditionally executed Thumb-2
2456 instructions for the IT instruction. */
2457 #define ADJUST_INSN_LENGTH(insn, length) \
2458 if (TARGET_THUMB2 && GET_CODE (PATTERN (insn)) == COND_EXEC) \
2461 /* Only perform branch elimination (by making instructions conditional) if
2462 we're optimizing. For Thumb-2 check if any IT instructions need
2464 #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \
2465 if (TARGET_ARM && optimize) \
2466 arm_final_prescan_insn (INSN); \
2467 else if (TARGET_THUMB2) \
2468 thumb2_final_prescan_insn (INSN); \
2469 else if (TARGET_THUMB1) \
2470 thumb1_final_prescan_insn (INSN)
2472 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) \
2473 (CODE == '@' || CODE == '|' || CODE == '.' \
2474 || CODE == '(' || CODE == ')' || CODE == '#' \
2475 || (TARGET_32BIT && (CODE == '?')) \
2476 || (TARGET_THUMB2 && (CODE == '!')) \
2477 || (TARGET_THUMB && (CODE == '_')))
2479 /* Output an operand of an instruction. */
2480 #define PRINT_OPERAND(STREAM, X, CODE) \
2481 arm_print_operand (STREAM, X, CODE)
2483 #define ARM_SIGN_EXTEND(x) ((HOST_WIDE_INT) \
2484 (HOST_BITS_PER_WIDE_INT <= 32 ? (unsigned HOST_WIDE_INT) (x) \
2485 : ((((unsigned HOST_WIDE_INT)(x)) & (unsigned HOST_WIDE_INT) 0xffffffff) |\
2486 ((((unsigned HOST_WIDE_INT)(x)) & (unsigned HOST_WIDE_INT) 0x80000000) \
2487 ? ((~ (unsigned HOST_WIDE_INT) 0) \
2488 & ~ (unsigned HOST_WIDE_INT) 0xffffffff) \
2491 /* Output the address of an operand. */
2492 #define ARM_PRINT_OPERAND_ADDRESS(STREAM, X) \
2494 int is_minus = GET_CODE (X) == MINUS; \
2496 if (GET_CODE (X) == REG) \
2497 asm_fprintf (STREAM, "[%r, #0]", REGNO (X)); \
2498 else if (GET_CODE (X) == PLUS || is_minus) \
2500 rtx base = XEXP (X, 0); \
2501 rtx index = XEXP (X, 1); \
2502 HOST_WIDE_INT offset = 0; \
2503 if (GET_CODE (base) != REG \
2504 || (GET_CODE (index) == REG && REGNO (index) == SP_REGNUM)) \
2506 /* Ensure that BASE is a register. */ \
2507 /* (one of them must be). */ \
2508 /* Also ensure the SP is not used as in index register. */ \
2513 switch (GET_CODE (index)) \
2516 offset = INTVAL (index); \
2519 asm_fprintf (STREAM, "[%r, #%wd]", \
2520 REGNO (base), offset); \
2524 asm_fprintf (STREAM, "[%r, %s%r]", \
2525 REGNO (base), is_minus ? "-" : "", \
2535 asm_fprintf (STREAM, "[%r, %s%r", \
2536 REGNO (base), is_minus ? "-" : "", \
2537 REGNO (XEXP (index, 0))); \
2538 arm_print_operand (STREAM, index, 'S'); \
2539 fputs ("]", STREAM); \
2544 gcc_unreachable (); \
2547 else if (GET_CODE (X) == PRE_INC || GET_CODE (X) == POST_INC \
2548 || GET_CODE (X) == PRE_DEC || GET_CODE (X) == POST_DEC) \
2550 extern enum machine_mode output_memory_reference_mode; \
2552 gcc_assert (GET_CODE (XEXP (X, 0)) == REG); \
2554 if (GET_CODE (X) == PRE_DEC || GET_CODE (X) == PRE_INC) \
2555 asm_fprintf (STREAM, "[%r, #%s%d]!", \
2556 REGNO (XEXP (X, 0)), \
2557 GET_CODE (X) == PRE_DEC ? "-" : "", \
2558 GET_MODE_SIZE (output_memory_reference_mode)); \
2560 asm_fprintf (STREAM, "[%r], #%s%d", \
2561 REGNO (XEXP (X, 0)), \
2562 GET_CODE (X) == POST_DEC ? "-" : "", \
2563 GET_MODE_SIZE (output_memory_reference_mode)); \
2565 else if (GET_CODE (X) == PRE_MODIFY) \
2567 asm_fprintf (STREAM, "[%r, ", REGNO (XEXP (X, 0))); \
2568 if (GET_CODE (XEXP (XEXP (X, 1), 1)) == CONST_INT) \
2569 asm_fprintf (STREAM, "#%wd]!", \
2570 INTVAL (XEXP (XEXP (X, 1), 1))); \
2572 asm_fprintf (STREAM, "%r]!", \
2573 REGNO (XEXP (XEXP (X, 1), 1))); \
2575 else if (GET_CODE (X) == POST_MODIFY) \
2577 asm_fprintf (STREAM, "[%r], ", REGNO (XEXP (X, 0))); \
2578 if (GET_CODE (XEXP (XEXP (X, 1), 1)) == CONST_INT) \
2579 asm_fprintf (STREAM, "#%wd", \
2580 INTVAL (XEXP (XEXP (X, 1), 1))); \
2582 asm_fprintf (STREAM, "%r", \
2583 REGNO (XEXP (XEXP (X, 1), 1))); \
2585 else output_addr_const (STREAM, X); \
2588 #define THUMB_PRINT_OPERAND_ADDRESS(STREAM, X) \
2590 if (GET_CODE (X) == REG) \
2591 asm_fprintf (STREAM, "[%r]", REGNO (X)); \
2592 else if (GET_CODE (X) == POST_INC) \
2593 asm_fprintf (STREAM, "%r!", REGNO (XEXP (X, 0))); \
2594 else if (GET_CODE (X) == PLUS) \
2596 gcc_assert (GET_CODE (XEXP (X, 0)) == REG); \
2597 if (GET_CODE (XEXP (X, 1)) == CONST_INT) \
2598 asm_fprintf (STREAM, "[%r, #%wd]", \
2599 REGNO (XEXP (X, 0)), \
2600 INTVAL (XEXP (X, 1))); \
2602 asm_fprintf (STREAM, "[%r, %r]", \
2603 REGNO (XEXP (X, 0)), \
2604 REGNO (XEXP (X, 1))); \
2607 output_addr_const (STREAM, X); \
2610 #define PRINT_OPERAND_ADDRESS(STREAM, X) \
2612 ARM_PRINT_OPERAND_ADDRESS (STREAM, X) \
2614 THUMB_PRINT_OPERAND_ADDRESS (STREAM, X)
2616 #define OUTPUT_ADDR_CONST_EXTRA(file, x, fail) \
2617 if (arm_output_addr_const_extra (file, x) == FALSE) \
2620 /* A C expression whose value is RTL representing the value of the return
2621 address for the frame COUNT steps up from the current frame. */
2623 #define RETURN_ADDR_RTX(COUNT, FRAME) \
2624 arm_return_addr (COUNT, FRAME)
2626 /* Mask of the bits in the PC that contain the real return address
2627 when running in 26-bit mode. */
2628 #define RETURN_ADDR_MASK26 (0x03fffffc)
2630 /* Pick up the return address upon entry to a procedure. Used for
2631 dwarf2 unwind information. This also enables the table driven
2633 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, LR_REGNUM)
2634 #define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (LR_REGNUM)
2636 /* Used to mask out junk bits from the return address, such as
2637 processor state, interrupt status, condition codes and the like. */
2638 #define MASK_RETURN_ADDR \
2639 /* If we are generating code for an ARM2/ARM3 machine or for an ARM6 \
2640 in 26 bit mode, the condition codes must be masked out of the \
2641 return address. This does not apply to ARM6 and later processors \
2642 when running in 32 bit mode. */ \
2643 ((arm_arch4 || TARGET_THUMB) \
2644 ? (gen_int_mode ((unsigned long)0xffffffff, Pmode)) \
2645 : arm_gen_return_addr_mask ())
2648 /* Neon defines builtins from ARM_BUILTIN_MAX upwards, though they don't have
2649 symbolic names defined here (which would require too much duplication).
2658 ARM_BUILTIN_WAVG2BR,
2659 ARM_BUILTIN_WAVG2HR,
2686 ARM_BUILTIN_TMOVMSKB,
2687 ARM_BUILTIN_TMOVMSKH,
2688 ARM_BUILTIN_TMOVMSKW,
2697 ARM_BUILTIN_WPACKHSS,
2698 ARM_BUILTIN_WPACKWSS,
2699 ARM_BUILTIN_WPACKDSS,
2700 ARM_BUILTIN_WPACKHUS,
2701 ARM_BUILTIN_WPACKWUS,
2702 ARM_BUILTIN_WPACKDUS,
2707 ARM_BUILTIN_WADDSSB,
2708 ARM_BUILTIN_WADDSSH,
2709 ARM_BUILTIN_WADDSSW,
2710 ARM_BUILTIN_WADDUSB,
2711 ARM_BUILTIN_WADDUSH,
2712 ARM_BUILTIN_WADDUSW,
2716 ARM_BUILTIN_WSUBSSB,
2717 ARM_BUILTIN_WSUBSSH,
2718 ARM_BUILTIN_WSUBSSW,
2719 ARM_BUILTIN_WSUBUSB,
2720 ARM_BUILTIN_WSUBUSH,
2721 ARM_BUILTIN_WSUBUSW,
2728 ARM_BUILTIN_WCMPEQB,
2729 ARM_BUILTIN_WCMPEQH,
2730 ARM_BUILTIN_WCMPEQW,
2731 ARM_BUILTIN_WCMPGTUB,
2732 ARM_BUILTIN_WCMPGTUH,
2733 ARM_BUILTIN_WCMPGTUW,
2734 ARM_BUILTIN_WCMPGTSB,
2735 ARM_BUILTIN_WCMPGTSH,
2736 ARM_BUILTIN_WCMPGTSW,
2738 ARM_BUILTIN_TEXTRMSB,
2739 ARM_BUILTIN_TEXTRMSH,
2740 ARM_BUILTIN_TEXTRMSW,
2741 ARM_BUILTIN_TEXTRMUB,
2742 ARM_BUILTIN_TEXTRMUH,
2743 ARM_BUILTIN_TEXTRMUW,
2793 ARM_BUILTIN_WUNPCKIHB,
2794 ARM_BUILTIN_WUNPCKIHH,
2795 ARM_BUILTIN_WUNPCKIHW,
2796 ARM_BUILTIN_WUNPCKILB,
2797 ARM_BUILTIN_WUNPCKILH,
2798 ARM_BUILTIN_WUNPCKILW,
2800 ARM_BUILTIN_WUNPCKEHSB,
2801 ARM_BUILTIN_WUNPCKEHSH,
2802 ARM_BUILTIN_WUNPCKEHSW,
2803 ARM_BUILTIN_WUNPCKEHUB,
2804 ARM_BUILTIN_WUNPCKEHUH,
2805 ARM_BUILTIN_WUNPCKEHUW,
2806 ARM_BUILTIN_WUNPCKELSB,
2807 ARM_BUILTIN_WUNPCKELSH,
2808 ARM_BUILTIN_WUNPCKELSW,
2809 ARM_BUILTIN_WUNPCKELUB,
2810 ARM_BUILTIN_WUNPCKELUH,
2811 ARM_BUILTIN_WUNPCKELUW,
2813 ARM_BUILTIN_THREAD_POINTER,
2815 ARM_BUILTIN_NEON_BASE,
2817 ARM_BUILTIN_MAX = ARM_BUILTIN_NEON_BASE /* FIXME: Wrong! */
2820 /* Do not emit .note.GNU-stack by default. */
2821 #ifndef NEED_INDICATE_EXEC_STACK
2822 #define NEED_INDICATE_EXEC_STACK 0
2825 #endif /* ! GCC_ARM_H */
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