1 /* Definitions of target machine for GNU compiler, for Acorn RISC Machine.
2 Copyright (C) 1991, 1993, 1994, 1995 Free Software Foundation, Inc.
3 Contributed by Pieter `Tiggr' Schoenmakers (rcpieter@win.tue.nl)
4 and Martin Simmons (@harleqn.co.uk).
5 More major hacks by Richard Earnshaw (rwe11@cl.cam.ac.uk)
7 This file is part of GNU CC.
9 GNU CC is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2, or (at your option)
14 GNU CC is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with GNU CC; see the file COPYING. If not, write to
21 the Free Software Foundation, 59 Temple Place - Suite 330,
22 Boston, MA 02111-1307, USA. */
24 extern void output_func_prologue ();
25 extern void output_func_epilogue ();
26 extern char *output_add_immediate ();
27 extern char *output_call ();
28 extern char *output_call_mem ();
29 extern char *output_move_double ();
30 extern char *output_mov_double_fpu_from_arm ();
31 extern char *output_mov_double_arm_from_fpu ();
32 extern char *output_mov_long_double_fpu_from_arm ();
33 extern char *output_mov_long_double_arm_from_fpu ();
34 extern char *output_mov_long_double_arm_from_arm ();
35 extern char *output_mov_immediate ();
36 extern char *output_multi_immediate ();
37 extern char *output_return_instruction ();
38 extern char *output_load_symbol ();
39 extern char *fp_immediate_constant ();
40 extern struct rtx_def *gen_compare_reg ();
41 extern struct rtx_def *arm_gen_store_multiple ();
42 extern struct rtx_def *arm_gen_load_multiple ();
44 extern char *arm_condition_codes[];
46 /* This is needed by the tail-calling peepholes */
47 extern int frame_pointer_needed;
50 #ifndef CPP_PREDEFINES
51 #define CPP_PREDEFINES "-Darm -Acpu(arm) -Amachine(arm)"
55 #define CPP_SPEC "%{m6:-D__arm6__} \
58 %{mapcs-32:-D__APCS_32__ -U__APCS_26__} \
59 %{mapcs-26:-D__APCS_26__ -U__APCS_32__} \
60 %{!mapcs-32: %{!mapcs-26:-D__APCS_26__}} \
61 %{msoft-float:-D__SOFTFP__} \
62 %{mhard-float:-U__SOFTFP__} \
63 %{!mhard-float: %{!msoft-float:-U__SOFTFP__}} \
64 %{mbig-endian:-D__ARMEB__ %{mwords-little-endian:-D__ARMWEL__}} \
65 %{mbe:-D__ARMEB__ %{mwords-little-endian:-D__ARMWEL__}} \
66 %{!mbe: %{!mbig-endian:-D__ARMEL__}} \
70 /* Run-time Target Specification. */
71 #ifndef TARGET_VERSION
72 #define TARGET_VERSION \
73 fputs (" (ARM/generic)", stderr);
76 /* Run-time compilation parameters selecting different hardware subsets. */
77 extern int target_flags;
79 /* These two are used by TARGET_OPTIONS, they are parsed in OVERRIDE_OPTIONS */
80 extern char *target_cpu_name;
81 extern char *target_fpe_name;
83 /* Nonzero if the function prologue (and epilogue) should obey
84 the ARM Procedure Call Standard. */
85 #define ARM_FLAG_APCS_FRAME (0x0001)
87 /* Nonzero if the function prologue should output the function name to enable
88 the post mortem debugger to print a backtrace (very useful on RISCOS,
89 unused on RISCiX). Specifying this flag also enables
90 -fno-omit-frame-pointer.
91 XXX Must still be implemented in the prologue. */
92 #define ARM_FLAG_POKE (0x0002)
94 /* Nonzero if floating point instructions are emulated by the FPE, in which
95 case instruction scheduling becomes very uninteresting. */
96 #define ARM_FLAG_FPE (0x0004)
98 /* Nonzero if destined for an ARM6xx. Takes out bits that assume restoration
99 of condition flags when returning from a branch & link (ie. a function) */
100 /* ********* DEPRECATED ******** */
101 #define ARM_FLAG_ARM6 (0x0008)
103 /* ********* DEPRECATED ******** */
104 #define ARM_FLAG_ARM3 (0x0010)
106 /* Nonzero if destined for a processor in 32-bit program mode. Takes out bit
107 that assume restoration of the condition flags when returning from a
108 branch and link (ie a function). */
109 #define ARM_FLAG_APCS_32 (0x0020)
111 /* Nonzero if stack checking should be performed on entry to each function
112 which allocates temporary variables on the stack. */
113 #define ARM_FLAG_APCS_STACK (0x0040)
115 /* Nonzero if floating point parameters should be passed to functions in
116 floating point registers. */
117 #define ARM_FLAG_APCS_FLOAT (0x0080)
119 /* Nonzero if re-entrant, position independent code should be generated.
120 This is equivalent to -fpic. */
121 #define ARM_FLAG_APCS_REENT (0x0100)
123 /* Nonzero if the MMU will trap unaligned word accesses, so shorts must be
124 loaded byte-at-a-time. */
125 #define ARM_FLAG_SHORT_BYTE (0x0200)
127 /* Nonzero if all floating point instructions are missing (and there is no
128 emulator either). Generate function calls for all ops in this case. */
129 #define ARM_FLAG_SOFT_FLOAT (0x0400)
131 /* Nonzero if we should compile with BYTES_BIG_ENDIAN set to 1. */
132 #define ARM_FLAG_BIG_END (0x0800)
134 /* Nonzero if we should compile for Thumb interworking. */
135 #define ARM_FLAG_THUMB (0x1000)
137 /* Nonzero if we should have little-endian words even when compiling for
138 big-endian (for backwards compatibility with older versions of GCC). */
139 #define ARM_FLAG_LITTLE_WORDS (0x2000)
141 #define TARGET_APCS (target_flags & ARM_FLAG_APCS_FRAME)
142 #define TARGET_POKE_FUNCTION_NAME (target_flags & ARM_FLAG_POKE)
143 #define TARGET_FPE (target_flags & ARM_FLAG_FPE)
144 #define TARGET_6 (target_flags & ARM_FLAG_ARM6)
145 #define TARGET_3 (target_flags & ARM_FLAG_ARM3)
146 #define TARGET_APCS_32 (target_flags & ARM_FLAG_APCS_32)
147 #define TARGET_APCS_STACK (target_flags & ARM_FLAG_APCS_STACK)
148 #define TARGET_APCS_FLOAT (target_flags & ARM_FLAG_APCS_FLOAT)
149 #define TARGET_APCS_REENT (target_flags & ARM_FLAG_APCS_REENT)
150 #define TARGET_SHORT_BY_BYTES (target_flags & ARM_FLAG_SHORT_BYTE)
151 #define TARGET_SOFT_FLOAT (target_flags & ARM_FLAG_SOFT_FLOAT)
152 #define TARGET_HARD_FLOAT (! TARGET_SOFT_FLOAT)
153 #define TARGET_BIG_END (target_flags & ARM_FLAG_BIG_END)
154 #define TARGET_THUMB_INTERWORK (target_flags & ARM_FLAG_THUMB)
155 #define TARGET_LITTLE_WORDS (target_flags & ARM_FLAG_LITTLE_WORDS)
157 /* SUBTARGET_SWITCHES is used to add flags on a per-config basis.
158 Bit 31 is reserved. See riscix.h. */
159 #ifndef SUBTARGET_SWITCHES
160 #define SUBTARGET_SWITCHES
163 #define TARGET_SWITCHES \
165 {"apcs", ARM_FLAG_APCS_FRAME}, \
166 {"apcs-frame", ARM_FLAG_APCS_FRAME}, \
167 {"no-apcs-frame", -ARM_FLAG_APCS_FRAME}, \
168 {"poke-function-name", ARM_FLAG_POKE}, \
169 {"fpe", ARM_FLAG_FPE}, \
170 {"6", ARM_FLAG_ARM6}, \
171 {"2", ARM_FLAG_ARM3}, \
172 {"3", ARM_FLAG_ARM3}, \
173 {"apcs-32", ARM_FLAG_APCS_32}, \
174 {"apcs-26", -ARM_FLAG_APCS_32}, \
175 {"apcs-stack-check", ARM_FLAG_APCS_STACK}, \
176 {"no-apcs-stack-check", -ARM_FLAG_APCS_STACK}, \
177 {"apcs-float", ARM_FLAG_APCS_FLOAT}, \
178 {"no-apcs-float", -ARM_FLAG_APCS_FLOAT}, \
179 {"apcs-reentrant", ARM_FLAG_APCS_REENT}, \
180 {"no-apcs-rentrant", -ARM_FLAG_APCS_REENT}, \
181 {"short-load-bytes", ARM_FLAG_SHORT_BYTE}, \
182 {"no-short-load-bytes", -ARM_FLAG_SHORT_BYTE}, \
183 {"short-load-words", -ARM_FLAG_SHORT_BYTE}, \
184 {"no-short-load-words", ARM_FLAG_SHORT_BYTE}, \
185 {"soft-float", ARM_FLAG_SOFT_FLOAT}, \
186 {"hard-float", -ARM_FLAG_SOFT_FLOAT}, \
187 {"big-endian", ARM_FLAG_BIG_END}, \
188 {"be", ARM_FLAG_BIG_END}, \
189 {"little-endian", -ARM_FLAG_BIG_END}, \
190 {"le", -ARM_FLAG_BIG_END}, \
191 {"thumb-interwork", ARM_FLAG_THUMB}, \
192 {"no-thumb-interwork", -ARM_FLAG_THUMB}, \
193 {"words-little-endian", ARM_FLAG_LITTLE_WORDS}, \
195 {"", TARGET_DEFAULT } \
198 #define TARGET_OPTIONS \
200 {"cpu-", &target_cpu_name}, \
201 {"cpu=", &target_cpu_name}, \
202 {"fpe-", &target_fpe_name}, \
203 {"fpe=", &target_fpe_name} \
206 /* Which processor we are running on. */
215 /* Recast the cpu class to be the cpu attribute. */
217 /* Recast the cpu class to be the cpu attribute. */
218 #define arm_cpu_attr ((enum attr_cpu)arm_cpu)
220 extern enum processor_type arm_cpu;
228 /* Recast the program mode class to be the prog_mode attribute */
229 #define arm_prog_mode ((enum attr_prog_mode) arm_prgmode)
231 extern enum prog_mode_type arm_prgmode;
233 /* What sort of floating point unit do we have? Hardware or software.
234 If software, is it issue 2 or issue 3? */
235 enum floating_point_type
242 /* Recast the floating point class to be the floating point attribute. */
243 #define arm_fpu_attr ((enum attr_fpu) arm_fpu)
245 extern enum floating_point_type arm_fpu;
247 /* Nonzero if the processor has a fast multiply insn, and one that does
248 a 64-bit multiply of two 32-bit values. */
249 extern int arm_fast_multiply;
251 /* Nonzero if this chip support the ARM Architecture 4 extensions */
252 extern int arm_arch4;
254 #ifndef TARGET_DEFAULT
255 #define TARGET_DEFAULT 0
258 /* A particular target can define this to a particular cpu name, eg "arm710dmi"
259 and the code generated should then be appropriate for that processor. */
261 #define ARM_CPU_NAME NULL
264 /* The frame pointer register used in gcc has nothing to do with debugging;
265 that is controlled by the APCS-FRAME option. */
266 /* Not fully implemented yet */
267 /* #define CAN_DEBUG_WITHOUT_FP 1 */
269 #define TARGET_MEM_FUNCTIONS 1
271 #define OVERRIDE_OPTIONS arm_override_options ()
273 /* Target machine storage Layout. */
276 /* Define this macro if it is advisable to hold scalars in registers
277 in a wider mode than that declared by the program. In such cases,
278 the value is constrained to be within the bounds of the declared
279 type, but kept valid in the wider mode. The signedness of the
280 extension may differ from that of the type. */
282 /* It is far faster to zero extend chars than to sign extend them */
284 #define PROMOTE_MODE(MODE,UNSIGNEDP,TYPE) \
285 if (GET_MODE_CLASS (MODE) == MODE_INT \
286 && GET_MODE_SIZE (MODE) < 4) \
288 if (MODE == QImode) \
290 else if (MODE == HImode) \
291 UNSIGNEDP = TARGET_SHORT_BY_BYTES != 0; \
295 /* Define for XFmode extended real floating point support.
296 This will automatically cause REAL_ARITHMETIC to be defined. */
298 I think I have added all the code to make this work. Unfortunately,
299 early releases of the floating point emulation code on RISCiX used a
300 different format for extended precision numbers. On my RISCiX box there
301 is a bug somewhere which causes the machine to lock up when running enquire
302 with long doubles. There is the additional aspect that Norcroft C
303 treats long doubles as doubles and we ought to remain compatible.
304 Perhaps someone with an FPA coprocessor and not running RISCiX would like
305 to try this someday. */
306 /* #define LONG_DOUBLE_TYPE_SIZE 96 */
308 /* Disable XFmode patterns in md file */
309 #define ENABLE_XF_PATTERNS 0
311 /* Define if you don't want extended real, but do want to use the
312 software floating point emulator for REAL_ARITHMETIC and
313 decimal <-> binary conversion. */
314 /* See comment above */
315 #define REAL_ARITHMETIC
317 /* Define this if most significant bit is lowest numbered
318 in instructions that operate on numbered bit-fields. */
319 #define BITS_BIG_ENDIAN 0
321 /* Define this if most significant byte of a word is the lowest numbered.
322 Most ARM processors are run in little endian mode, so that is the default.
323 If you want to have it run-time selectable, change the definition in a
324 cover file to be TARGET_BIG_ENDIAN. */
325 #define BYTES_BIG_ENDIAN (TARGET_BIG_END != 0)
327 /* Define this if most significant word of a multiword number is the lowest
329 This is always false, even when in big-endian mode. */
330 #define WORDS_BIG_ENDIAN (BYTES_BIG_ENDIAN && ! TARGET_LITTLE_WORDS)
332 /* LIBGCC2_WORDS_BIG_ENDIAN has to be a constant, so we define this based
333 on processor pre-defineds when compiling libgcc2.c. */
334 #if defined(__ARMEB__) && !defined(__ARMWEL__)
335 #define LIBGCC2_WORDS_BIG_ENDIAN 1
337 #define LIBGCC2_WORDS_BIG_ENDIAN 0
340 /* Define this if most significant word of doubles is the lowest numbered.
341 This is always true, even when in little-endian mode. */
342 #define FLOAT_WORDS_BIG_ENDIAN 1
344 /* Number of bits in an addressable storage unit */
345 #define BITS_PER_UNIT 8
347 #define BITS_PER_WORD 32
349 #define UNITS_PER_WORD 4
351 #define POINTER_SIZE 32
353 #define PARM_BOUNDARY 32
355 #define STACK_BOUNDARY 32
357 #define FUNCTION_BOUNDARY 32
359 #define EMPTY_FIELD_BOUNDARY 32
361 #define BIGGEST_ALIGNMENT 32
363 /* Make strings word-aligned so strcpy from constants will be faster. */
364 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
365 (TREE_CODE (EXP) == STRING_CST \
366 && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
368 /* Every structures size must be a multiple of 32 bits. */
369 #define STRUCTURE_SIZE_BOUNDARY 32
371 /* Non-zero if move instructions will actually fail to work
372 when given unaligned data. */
373 #define STRICT_ALIGNMENT 1
375 #define TARGET_FLOAT_FORMAT IEEE_FLOAT_FORMAT
378 /* Standard register usage. */
380 /* Register allocation in ARM Procedure Call Standard (as used on RISCiX):
381 (S - saved over call).
383 r0 * argument word/integer result
386 r4-r8 S register variable
387 r9 S (rfp) register variable (real frame pointer)
389 r10 F S (sl) stack limit (not currently used)
390 r11 F S (fp) argument pointer
391 r12 (ip) temp workspace
392 r13 F S (sp) lower end of current stack frame
393 r14 (lr) link address/workspace
394 r15 F (pc) program counter
396 f0 floating point result
397 f1-f3 floating point scratch
399 f4-f7 S floating point variable
401 cc This is NOT a real register, but is used internally
402 to represent things that use or set the condition
404 sfp This isn't either. It is used during rtl generation
405 since the offset between the frame pointer and the
406 auto's isn't known until after register allocation.
407 afp Nor this, we only need this because of non-local
408 goto. Without it fp appears to be used and the
409 elimination code won't get rid of sfp. It tracks
410 fp exactly at all times.
412 *: See CONDITIONAL_REGISTER_USAGE */
414 /* The stack backtrace structure is as follows:
415 fp points to here: | save code pointer | [fp]
416 | return link value | [fp, #-4]
417 | return sp value | [fp, #-8]
418 | return fp value | [fp, #-12]
419 [| saved r10 value |]
430 [| saved f7 value |] three words
431 [| saved f6 value |] three words
432 [| saved f5 value |] three words
433 [| saved f4 value |] three words
434 r0-r3 are not normally saved in a C function. */
436 /* The number of hard registers is 16 ARM + 8 FPU + 1 CC + 1 SFP. */
437 #define FIRST_PSEUDO_REGISTER 27
439 /* 1 for registers that have pervasive standard uses
440 and are not available for the register allocator. */
441 #define FIXED_REGISTERS \
449 /* 1 for registers not available across function calls.
450 These must include the FIXED_REGISTERS and also any
451 registers that can be used without being saved.
452 The latter must include the registers where values are returned
453 and the register where structure-value addresses are passed.
454 Aside from that, you can include as many other registers as you like.
455 The CC is not preserved over function calls on the ARM 6, so it is
456 easier to assume this for all. SFP is preserved, since FP is. */
457 #define CALL_USED_REGISTERS \
465 /* If doing stupid life analysis, avoid a bug causing a return value r0 to be
466 trampled. This effectively reduces the number of available registers by 1.
467 XXX It is a hack, I know.
468 XXX Is this still needed? */
469 #define CONDITIONAL_REGISTER_USAGE \
473 if (TARGET_SOFT_FLOAT) \
476 for (regno = 16; regno < 24; ++regno) \
477 fixed_regs[regno] = call_used_regs[regno] = 1; \
481 /* Return number of consecutive hard regs needed starting at reg REGNO
482 to hold something of mode MODE.
483 This is ordinarily the length in words of a value of mode MODE
484 but can be less for certain modes in special long registers.
486 On the ARM regs are UNITS_PER_WORD bits wide; FPU regs can hold any FP
488 #define HARD_REGNO_NREGS(REGNO, MODE) \
489 (((REGNO) >= 16 && REGNO != FRAME_POINTER_REGNUM \
490 && (REGNO) != ARG_POINTER_REGNUM) ? 1 \
491 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
493 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
494 This is TRUE for ARM regs since they can hold anything, and TRUE for FPU
496 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
497 ((GET_MODE_CLASS (MODE) == MODE_CC) ? (REGNO == CC_REGNUM) : \
498 ((REGNO) < 16 || REGNO == FRAME_POINTER_REGNUM \
499 || REGNO == ARG_POINTER_REGNUM \
500 || GET_MODE_CLASS (MODE) == MODE_FLOAT))
502 /* Value is 1 if it is a good idea to tie two pseudo registers
503 when one has mode MODE1 and one has mode MODE2.
504 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
505 for any hard reg, then this must be 0 for correct output. */
506 #define MODES_TIEABLE_P(MODE1, MODE2) \
507 (GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2))
509 /* Specify the registers used for certain standard purposes.
510 The values of these macros are register numbers. */
512 /* Define this if the program counter is overloaded on a register. */
515 /* Register to use for pushing function arguments. */
516 #define STACK_POINTER_REGNUM 13
518 /* Base register for access to local variables of the function. */
519 #define FRAME_POINTER_REGNUM 25
521 /* Define this to be where the real frame pointer is if it is not possible to
522 work out the offset between the frame pointer and the automatic variables
523 until after register allocation has taken place. FRAME_POINTER_REGNUM
524 should point to a special register that we will make sure is eliminated. */
525 #define HARD_FRAME_POINTER_REGNUM 11
527 /* Value should be nonzero if functions must have frame pointers.
528 Zero means the frame pointer need not be set up (and parms may be accessed
529 via the stack pointer) in functions that seem suitable.
530 If we have to have a frame pointer we might as well make use of it.
531 APCS says that the frame pointer does not need to be pushed in leaf
533 #define FRAME_POINTER_REQUIRED \
534 (current_function_has_nonlocal_label || (TARGET_APCS && !leaf_function_p ()))
536 /* Base register for access to arguments of the function. */
537 #define ARG_POINTER_REGNUM 26
539 /* The native (Norcroft) Pascal compiler for the ARM passes the static chain
540 as an invisible last argument (possible since varargs don't exist in
541 Pascal), so the following is not true. */
542 #define STATIC_CHAIN_REGNUM 8
544 /* Register in which address to store a structure value
545 is passed to a function. */
546 #define STRUCT_VALUE_REGNUM 0
548 /* Internal, so that we don't need to refer to a raw number */
551 /* The order in which register should be allocated. It is good to use ip
552 since no saving is required (though calls clobber it) and it never contains
553 function parameters. It is quite good to use lr since other calls may
554 clobber it anyway. Allocate r0 through r3 in reverse order since r3 is
555 least likely to contain a function parameter; in addition results are
558 #define REG_ALLOC_ORDER \
560 3, 2, 1, 0, 12, 14, 4, 5, \
561 6, 7, 8, 10, 9, 11, 13, 15, \
562 16, 17, 18, 19, 20, 21, 22, 23, \
566 /* Register and constant classes. */
568 /* Register classes: all ARM regs or all FPU regs---simple! */
578 #define N_REG_CLASSES (int) LIM_REG_CLASSES
580 /* Give names of register classes as strings for dump file. */
581 #define REG_CLASS_NAMES \
589 /* Define which registers fit in which classes.
590 This is an initializer for a vector of HARD_REG_SET
591 of length N_REG_CLASSES. */
592 #define REG_CLASS_CONTENTS \
594 0x0000000, /* NO_REGS */ \
595 0x0FF0000, /* FPU_REGS */ \
596 0x200FFFF, /* GENERAL_REGS */ \
597 0x2FFFFFF /* ALL_REGS */ \
600 /* The same information, inverted:
601 Return the class number of the smallest class containing
602 reg number REGNO. This could be a conditional expression
603 or could index an array. */
604 #define REGNO_REG_CLASS(REGNO) \
605 (((REGNO) < 16 || REGNO == FRAME_POINTER_REGNUM \
606 || REGNO == ARG_POINTER_REGNUM) \
607 ? GENERAL_REGS : (REGNO) == CC_REGNUM \
608 ? NO_REGS : FPU_REGS)
610 /* The class value for index registers, and the one for base regs. */
611 #define INDEX_REG_CLASS GENERAL_REGS
612 #define BASE_REG_CLASS GENERAL_REGS
614 /* Get reg_class from a letter such as appears in the machine description.
615 We only need constraint `f' for FPU_REGS (`r' == GENERAL_REGS). */
616 #define REG_CLASS_FROM_LETTER(C) \
617 ((C)=='f' ? FPU_REGS : NO_REGS)
619 /* The letters I, J, K, L and M in a register constraint string
620 can be used to stand for particular ranges of immediate operands.
621 This macro defines what the ranges are.
622 C is the letter, and VALUE is a constant value.
623 Return 1 if VALUE is in the range specified by C.
624 I: immediate arithmetic operand (i.e. 8 bits shifted as required).
625 J: valid indexing constants.
626 K: ~value ok in rhs argument of data operand.
627 L: -value ok in rhs argument of data operand.
628 M: 0..32, or a power of 2 (for shifts, or mult done by shift). */
629 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
630 ((C) == 'I' ? const_ok_for_arm (VALUE) : \
631 (C) == 'J' ? ((VALUE) < 4096 && (VALUE) > -4096) : \
632 (C) == 'K' ? (const_ok_for_arm (~(VALUE))) : \
633 (C) == 'L' ? (const_ok_for_arm (-(VALUE))) : \
634 (C) == 'M' ? (((VALUE >= 0 && VALUE <= 32)) \
635 || (((VALUE) & ((VALUE) - 1)) == 0)) \
638 /* For the ARM, `Q' means that this is a memory operand that is just
639 an offset from a register.
640 `S' means any symbol that has the SYMBOL_REF_FLAG set or a CONSTANT_POOL
641 address. This means that the symbol is in the text segment and can be
642 accessed without using a load. */
644 #define EXTRA_CONSTRAINT(OP, C) \
645 ((C) == 'Q' ? GET_CODE (OP) == MEM && GET_CODE (XEXP (OP, 0)) == REG \
646 : (C) == 'R' ? (GET_CODE (OP) == MEM \
647 && GET_CODE (XEXP (OP, 0)) == SYMBOL_REF \
648 && CONSTANT_POOL_ADDRESS_P (XEXP (OP, 0))) \
649 : (C) == 'S' ? (optimize > 0 && CONSTANT_ADDRESS_P (OP)) : 0)
651 /* Constant letter 'G' for the FPU immediate constants.
652 'H' means the same constant negated. */
653 #define CONST_DOUBLE_OK_FOR_LETTER_P(X,C) \
654 ((C) == 'G' ? const_double_rtx_ok_for_fpu (X) \
655 : (C) == 'H' ? neg_const_double_rtx_ok_for_fpu (X) : 0)
657 /* Given an rtx X being reloaded into a reg required to be
658 in class CLASS, return the class of reg to actually use.
659 In general this is just CLASS; but on some machines
660 in some cases it is preferable to use a more restrictive class. */
661 #define PREFERRED_RELOAD_CLASS(X, CLASS) (CLASS)
663 /* Return the register class of a scratch register needed to copy IN into
664 or out of a register in CLASS in MODE. If it can be done directly,
665 NO_REGS is returned. */
666 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS,MODE,X) \
667 (((MODE) == HImode && ! arm_arch4 && true_regnum (X) == -1) \
668 ? GENERAL_REGS : NO_REGS)
670 /* If we need to load shorts byte-at-a-time, then we need a scratch. */
671 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS,MODE,X) \
672 (((MODE) == HImode && TARGET_SHORT_BY_BYTES && true_regnum (X) == -1) \
673 ? GENERAL_REGS : NO_REGS)
675 /* Return the maximum number of consecutive registers
676 needed to represent mode MODE in a register of class CLASS.
677 ARM regs are UNITS_PER_WORD bits while FPU regs can hold any FP mode */
678 #define CLASS_MAX_NREGS(CLASS, MODE) \
679 ((CLASS) == FPU_REGS ? 1 \
680 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
682 /* Moves between FPU_REGS and GENERAL_REGS are two memory insns. */
683 #define REGISTER_MOVE_COST(CLASS1, CLASS2) \
684 ((((CLASS1) == FPU_REGS && (CLASS2) != FPU_REGS) \
685 || ((CLASS2) == FPU_REGS && (CLASS1) != FPU_REGS)) \
688 /* Stack layout; function entry, exit and calling. */
690 /* Define this if pushing a word on the stack
691 makes the stack pointer a smaller address. */
692 #define STACK_GROWS_DOWNWARD 1
694 /* Define this if the nominal address of the stack frame
695 is at the high-address end of the local variables;
696 that is, each additional local variable allocated
697 goes at a more negative offset in the frame. */
698 #define FRAME_GROWS_DOWNWARD 1
700 /* Offset within stack frame to start allocating local variables at.
701 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
702 first local allocated. Otherwise, it is the offset to the BEGINNING
703 of the first local allocated. */
704 #define STARTING_FRAME_OFFSET 0
706 /* If we generate an insn to push BYTES bytes,
707 this says how many the stack pointer really advances by. */
708 #define PUSH_ROUNDING(NPUSHED) (((NPUSHED) + 3) & ~3)
710 /* Offset of first parameter from the argument pointer register value. */
711 #define FIRST_PARM_OFFSET(FNDECL) 4
713 /* Value is the number of byte of arguments automatically
714 popped when returning from a subroutine call.
715 FUNDECL is the declaration node of the function (as a tree),
716 FUNTYPE is the data type of the function (as a tree),
717 or for a library call it is an identifier node for the subroutine name.
718 SIZE is the number of bytes of arguments passed on the stack.
720 On the ARM, the caller does not pop any of its arguments that were passed
722 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0
724 /* Define how to find the value returned by a function.
725 VALTYPE is the data type of the value (as a tree).
726 If the precise function being called is known, FUNC is its FUNCTION_DECL;
727 otherwise, FUNC is 0. */
728 #define FUNCTION_VALUE(VALTYPE, FUNC) \
729 (GET_MODE_CLASS (TYPE_MODE (VALTYPE)) == MODE_FLOAT && TARGET_HARD_FLOAT \
730 ? gen_rtx (REG, TYPE_MODE (VALTYPE), 16) \
731 : gen_rtx (REG, TYPE_MODE (VALTYPE), 0))
733 /* Define how to find the value returned by a library function
734 assuming the value has mode MODE. */
735 #define LIBCALL_VALUE(MODE) \
736 (GET_MODE_CLASS (MODE) == MODE_FLOAT && TARGET_HARD_FLOAT \
737 ? gen_rtx (REG, MODE, 16) \
738 : gen_rtx (REG, MODE, 0))
740 /* 1 if N is a possible register number for a function value.
741 On the ARM, only r0 and f0 can return results. */
742 #define FUNCTION_VALUE_REGNO_P(REGNO) \
743 ((REGNO) == 0 || ((REGNO) == 16) && TARGET_HARD_FLOAT)
745 /* How large values are returned */
746 /* A C expression which can inhibit the returning of certain function values
747 in registers, based on the type of value. */
748 #define RETURN_IN_MEMORY(TYPE) \
749 (TYPE_MODE ((TYPE)) == BLKmode || \
750 (AGGREGATE_TYPE_P ((TYPE)) && arm_return_in_memory ((TYPE))))
752 /* Define DEFAULT_PCC_STRUCT_RETURN to 1 if all structure and union return
753 values must be in memory. On the ARM, they need only do so if larger
754 than a word, or if they contain elements offset from zero in the struct. */
755 #define DEFAULT_PCC_STRUCT_RETURN 0
757 /* Define where to put the arguments to a function.
758 Value is zero to push the argument on the stack,
759 or a hard register in which to store the argument.
761 MODE is the argument's machine mode.
762 TYPE is the data type of the argument (as a tree).
763 This is null for libcalls where that information may
765 CUM is a variable of type CUMULATIVE_ARGS which gives info about
766 the preceding args and about the function being called.
767 NAMED is nonzero if this argument is a named parameter
768 (otherwise it is an extra parameter matching an ellipsis).
770 On the ARM, normally the first 16 bytes are passed in registers r0-r3; all
771 other arguments are passed on the stack. If (NAMED == 0) (which happens
772 only in assign_parms, since SETUP_INCOMING_VARARGS is defined), say it is
773 passed in the stack (function_prologue will indeed make it pass in the
774 stack if necessary). */
775 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
777 ? ((CUM) >= 16 ? 0 : gen_rtx (REG, MODE, (CUM) / 4)) \
780 /* For an arg passed partly in registers and partly in memory,
781 this is the number of registers used.
782 For args passed entirely in registers or entirely in memory, zero. */
783 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
784 ((CUM) < 16 && 16 < (CUM) + ((MODE) != BLKmode \
785 ? GET_MODE_SIZE (MODE) \
786 : int_size_in_bytes (TYPE)) \
789 /* A C type for declaring a variable that is used as the first argument of
790 `FUNCTION_ARG' and other related values. For some target machines, the
791 type `int' suffices and can hold the number of bytes of argument so far.
793 On the ARM, this is the number of bytes of arguments scanned so far. */
794 #define CUMULATIVE_ARGS int
796 /* Initialize a variable CUM of type CUMULATIVE_ARGS
797 for a call to a function whose data type is FNTYPE.
798 For a library call, FNTYPE is 0.
799 On the ARM, the offset starts at 0. */
800 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME) \
801 ((CUM) = (((FNTYPE) && aggregate_value_p (TREE_TYPE ((FNTYPE)))) ? 4 : 0))
803 /* Update the data in CUM to advance over an argument
804 of mode MODE and data type TYPE.
805 (TYPE is null for libcalls where that information may not be available.) */
806 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
807 (CUM) += ((MODE) != BLKmode \
808 ? (GET_MODE_SIZE (MODE) + 3) & ~3 \
809 : (int_size_in_bytes (TYPE) + 3) & ~3) \
811 /* 1 if N is a possible register number for function argument passing.
812 On the ARM, r0-r3 are used to pass args. */
813 #define FUNCTION_ARG_REGNO_P(REGNO) \
814 ((REGNO) >= 0 && (REGNO) <= 3)
816 /* Perform any actions needed for a function that is receiving a variable
817 number of arguments. CUM is as above. MODE and TYPE are the mode and type
818 of the current parameter. PRETEND_SIZE is a variable that should be set to
819 the amount of stack that must be pushed by the prolog to pretend that our
822 Normally, this macro will push all remaining incoming registers on the
823 stack and set PRETEND_SIZE to the length of the registers pushed.
825 On the ARM, PRETEND_SIZE is set in order to have the prologue push the last
826 named arg and all anonymous args onto the stack.
827 XXX I know the prologue shouldn't be pushing registers, but it is faster
829 #define SETUP_INCOMING_VARARGS(CUM, MODE, TYPE, PRETEND_SIZE, NO_RTL) \
831 extern int current_function_anonymous_args; \
832 current_function_anonymous_args = 1; \
834 (PRETEND_SIZE) = 16 - (CUM); \
837 /* Generate assembly output for the start of a function. */
838 #define FUNCTION_PROLOGUE(STREAM, SIZE) \
839 output_func_prologue ((STREAM), (SIZE))
841 /* Call the function profiler with a given profile label. The Acorn compiler
842 puts this BEFORE the prolog but gcc pust it afterwards. The ``mov ip,lr''
843 seems like a good idea to stick with cc convention. ``prof'' doesn't seem
844 to mind about this! */
845 #define FUNCTION_PROFILER(STREAM,LABELNO) \
847 fprintf(STREAM, "\tmov\t%sip, %slr\n", REGISTER_PREFIX, REGISTER_PREFIX); \
848 fprintf(STREAM, "\tbl\tmcount\n"); \
849 fprintf(STREAM, "\t.word\tLP%d\n", (LABELNO)); \
852 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
853 the stack pointer does not matter. The value is tested only in
854 functions that have frame pointers.
855 No definition is equivalent to always zero.
857 On the ARM, the function epilogue recovers the stack pointer from the
859 #define EXIT_IGNORE_STACK 1
861 /* Generate the assembly code for function exit. */
862 #define FUNCTION_EPILOGUE(STREAM, SIZE) \
863 output_func_epilogue ((STREAM), (SIZE))
865 /* Determine if the epilogue should be output as RTL.
866 You should override this if you define FUNCTION_EXTRA_EPILOGUE. */
867 #define USE_RETURN_INSN use_return_insn ()
869 /* Definitions for register eliminations.
871 This is an array of structures. Each structure initializes one pair
872 of eliminable registers. The "from" register number is given first,
873 followed by "to". Eliminations of the same "from" register are listed
874 in order of preference.
876 We have two registers that can be eliminated on the ARM. First, the
877 arg pointer register can often be eliminated in favor of the stack
878 pointer register. Secondly, the pseudo frame pointer register can always
879 be eliminated; it is replaced with either the stack or the real frame
882 #define ELIMINABLE_REGS \
883 {{ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
884 {ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \
885 {FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
886 {FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}}
888 /* Given FROM and TO register numbers, say whether this elimination is allowed.
889 Frame pointer elimination is automatically handled.
891 All eliminations are permissible. Note that ARG_POINTER_REGNUM and
892 HARD_FRAME_POINTER_REGNUM are in fact the same thing. If we need a frame
893 pointer, we must eliminate FRAME_POINTER_REGNUM into
894 HARD_FRAME_POINTER_REGNUM and not into STACK_POINTER_REGNUM. */
895 #define CAN_ELIMINATE(FROM, TO) \
896 (((TO) == STACK_POINTER_REGNUM && frame_pointer_needed) ? 0 : 1)
898 /* Define the offset between two registers, one to be eliminated, and the other
899 its replacement, at the start of a routine. */
900 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
902 int volatile_func = arm_volatile_func (); \
903 if ((FROM) == ARG_POINTER_REGNUM && (TO) == HARD_FRAME_POINTER_REGNUM)\
905 else if ((FROM) == FRAME_POINTER_REGNUM && (TO) == STACK_POINTER_REGNUM)\
906 (OFFSET) = (get_frame_size () + 3 & ~3); \
911 int saved_hard_reg = 0; \
913 if (! volatile_func) \
915 for (regno = 0; regno <= 10; regno++) \
916 if (regs_ever_live[regno] && ! call_used_regs[regno]) \
917 saved_hard_reg = 1, offset += 4; \
918 for (regno = 16; regno <=23; regno++) \
919 if (regs_ever_live[regno] && ! call_used_regs[regno]) \
922 if ((FROM) == FRAME_POINTER_REGNUM) \
923 (OFFSET) = -offset; \
926 if (! frame_pointer_needed) \
928 if (! volatile_func && (regs_ever_live[14] || saved_hard_reg)) \
930 (OFFSET) = (get_frame_size () + 3 & ~3) + offset; \
935 /* Output assembler code for a block containing the constant parts
936 of a trampoline, leaving space for the variable parts.
938 On the ARM, (if r8 is the static chain regnum, and remembering that
939 referencing pc adds an offset of 8) the trampoline looks like:
942 .word static chain value
943 .word function's address
944 ??? FIXME: When the trampoline returns, r8 will be clobbered. */
945 #define TRAMPOLINE_TEMPLATE(FILE) \
947 fprintf ((FILE), "\tldr\t%sr8, [%spc, #0]\n", \
948 REGISTER_PREFIX, REGISTER_PREFIX); \
949 fprintf ((FILE), "\tldr\t%spc, [%spc, #0]\n", \
950 REGISTER_PREFIX, REGISTER_PREFIX); \
951 fprintf ((FILE), "\t.word\t0\n"); \
952 fprintf ((FILE), "\t.word\t0\n"); \
955 /* Length in units of the trampoline for entering a nested function. */
956 #define TRAMPOLINE_SIZE 16
958 /* Alignment required for a trampoline in units. */
959 #define TRAMPOLINE_ALIGN 4
961 /* Emit RTL insns to initialize the variable parts of a trampoline.
962 FNADDR is an RTX for the address of the function's pure code.
963 CXT is an RTX for the static chain value for the function. */
964 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
966 emit_move_insn (gen_rtx (MEM, SImode, plus_constant ((TRAMP), 8)), \
968 emit_move_insn (gen_rtx (MEM, SImode, plus_constant ((TRAMP), 12)), \
973 /* Addressing modes, and classification of registers for them. */
975 #define HAVE_POST_INCREMENT 1
976 #define HAVE_PRE_INCREMENT 1
977 #define HAVE_POST_DECREMENT 1
978 #define HAVE_PRE_DECREMENT 1
980 /* Macros to check register numbers against specific register classes. */
982 /* These assume that REGNO is a hard or pseudo reg number.
983 They give nonzero only if REGNO is a hard reg of the suitable class
984 or a pseudo reg currently allocated to a suitable hard reg.
985 Since they use reg_renumber, they are safe only once reg_renumber
986 has been allocated, which happens in local-alloc.c.
988 On the ARM, don't allow the pc to be used. */
989 #define REGNO_OK_FOR_BASE_P(REGNO) \
990 ((REGNO) < 15 || (REGNO) == FRAME_POINTER_REGNUM \
991 || (REGNO) == ARG_POINTER_REGNUM \
992 || (unsigned) reg_renumber[(REGNO)] < 15 \
993 || (unsigned) reg_renumber[(REGNO)] == FRAME_POINTER_REGNUM \
994 || (unsigned) reg_renumber[(REGNO)] == ARG_POINTER_REGNUM)
995 #define REGNO_OK_FOR_INDEX_P(REGNO) \
996 REGNO_OK_FOR_BASE_P(REGNO)
998 /* Maximum number of registers that can appear in a valid memory address.
999 Shifts in addresses can't be by a register. */
1001 #define MAX_REGS_PER_ADDRESS 2
1003 /* Recognize any constant value that is a valid address. */
1004 /* XXX We can address any constant, eventually... */
1006 #ifdef AOF_ASSEMBLER
1008 #define CONSTANT_ADDRESS_P(X) \
1009 (GET_CODE (X) == SYMBOL_REF \
1010 && CONSTANT_POOL_ADDRESS_P (X))
1014 #define CONSTANT_ADDRESS_P(X) \
1015 (GET_CODE (X) == SYMBOL_REF \
1016 && (CONSTANT_POOL_ADDRESS_P (X) \
1017 || (optimize > 0 && SYMBOL_REF_FLAG (X))))
1019 #endif /* AOF_ASSEMBLER */
1021 /* Nonzero if the constant value X is a legitimate general operand.
1022 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE.
1024 On the ARM, allow any integer (invalid ones are removed later by insn
1025 patterns), nice doubles and symbol_refs which refer to the function's
1026 constant pool XXX. */
1027 #define LEGITIMATE_CONSTANT_P(X) (! label_mentioned_p (X))
1029 /* Symbols in the text segment can be accessed without indirecting via the
1030 constant pool; it may take an extra binary operation, but this is still
1031 faster than indirecting via memory. Don't do this when not optimizing,
1032 since we won't be calculating al of the offsets necessary to do this
1034 /* This doesn't work with AOF syntax, since the string table may be in
1035 a different AREA. */
1036 #ifndef AOF_ASSEMBLER
1037 #define ENCODE_SECTION_INFO(decl) \
1039 if (optimize > 0 && TREE_CONSTANT (decl) \
1040 && (!flag_writable_strings || TREE_CODE (decl) != STRING_CST)) \
1042 rtx rtl = (TREE_CODE_CLASS (TREE_CODE (decl)) != 'd' \
1043 ? TREE_CST_RTL (decl) : DECL_RTL (decl)); \
1044 SYMBOL_REF_FLAG (XEXP (rtl, 0)) = 1; \
1048 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
1049 and check its validity for a certain class.
1050 We have two alternate definitions for each of them.
1051 The usual definition accepts all pseudo regs; the other rejects
1052 them unless they have been allocated suitable hard regs.
1053 The symbol REG_OK_STRICT causes the latter definition to be used. */
1054 #ifndef REG_OK_STRICT
1056 /* Nonzero if X is a hard reg that can be used as a base reg
1057 or if it is a pseudo reg. */
1058 #define REG_OK_FOR_BASE_P(X) \
1059 (REGNO (X) < 16 || REGNO (X) >= FIRST_PSEUDO_REGISTER \
1060 || REGNO (X) == FRAME_POINTER_REGNUM || REGNO (X) == ARG_POINTER_REGNUM)
1062 /* Nonzero if X is a hard reg that can be used as an index
1063 or if it is a pseudo reg. */
1064 #define REG_OK_FOR_INDEX_P(X) \
1065 REG_OK_FOR_BASE_P(X)
1067 #define REG_OK_FOR_PRE_POST_P(X) \
1068 (REGNO (X) < 16 || REGNO (X) >= FIRST_PSEUDO_REGISTER \
1069 || REGNO (X) == FRAME_POINTER_REGNUM || REGNO (X) == ARG_POINTER_REGNUM)
1073 /* Nonzero if X is a hard reg that can be used as a base reg. */
1074 #define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X))
1076 /* Nonzero if X is a hard reg that can be used as an index. */
1077 #define REG_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X))
1079 #define REG_OK_FOR_PRE_POST_P(X) \
1080 (REGNO (X) < 16 || (unsigned) reg_renumber[REGNO (X)] < 16 \
1081 || REGNO (X) == FRAME_POINTER_REGNUM || REGNO (X) == ARG_POINTER_REGNUM \
1082 || (unsigned) reg_renumber[REGNO (X)] == FRAME_POINTER_REGNUM \
1083 || (unsigned) reg_renumber[REGNO (X)] == ARG_POINTER_REGNUM)
1087 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
1088 that is a valid memory address for an instruction.
1089 The MODE argument is the machine mode for the MEM expression
1090 that wants to use this address.
1092 The other macros defined here are used only in GO_IF_LEGITIMATE_ADDRESS. */
1093 #define BASE_REGISTER_RTX_P(X) \
1094 (GET_CODE (X) == REG && REG_OK_FOR_BASE_P (X))
1096 #define INDEX_REGISTER_RTX_P(X) \
1097 (GET_CODE (X) == REG && REG_OK_FOR_INDEX_P (X))
1099 /* A C statement (sans semicolon) to jump to LABEL for legitimate index RTXs
1100 used by the macro GO_IF_LEGITIMATE_ADDRESS. Floating point indices can
1101 only be small constants. */
1102 #define GO_IF_LEGITIMATE_INDEX(MODE, BASE_REGNO, INDEX, LABEL) \
1105 HOST_WIDE_INT range; \
1106 enum rtx_code code = GET_CODE (INDEX); \
1108 if (TARGET_HARD_FLOAT && GET_MODE_CLASS (MODE) == MODE_FLOAT) \
1110 if (code == CONST_INT && INTVAL (INDEX) < 1024 \
1111 && INTVAL (INDEX) > -1024 \
1112 && (INTVAL (INDEX) & 3) == 0) \
1117 if (INDEX_REGISTER_RTX_P (INDEX) && GET_MODE_SIZE (MODE) <= 4) \
1119 if (GET_MODE_SIZE (MODE) <= 4 && code == MULT \
1120 && (! arm_arch4 || (MODE) != HImode)) \
1122 rtx xiop0 = XEXP (INDEX, 0); \
1123 rtx xiop1 = XEXP (INDEX, 1); \
1124 if (INDEX_REGISTER_RTX_P (xiop0) \
1125 && power_of_two_operand (xiop1, SImode)) \
1127 if (INDEX_REGISTER_RTX_P (xiop1) \
1128 && power_of_two_operand (xiop0, SImode)) \
1131 if (GET_MODE_SIZE (MODE) <= 4 \
1132 && (code == LSHIFTRT || code == ASHIFTRT \
1133 || code == ASHIFT || code == ROTATERT) \
1134 && (! arm_arch4 || (MODE) != HImode)) \
1136 rtx op = XEXP (INDEX, 1); \
1137 if (INDEX_REGISTER_RTX_P (XEXP (INDEX, 0)) \
1138 && GET_CODE (op) == CONST_INT && INTVAL (op) > 0 \
1139 && INTVAL (op) <= 31) \
1142 range = (MODE) == HImode ? (arm_arch4 ? 256 : 4095) : 4096; \
1143 if (code == CONST_INT && INTVAL (INDEX) < range \
1144 && INTVAL (INDEX) > -range) \
1149 /* Jump to LABEL if X is a valid address RTX. This must also take
1150 REG_OK_STRICT into account when deciding about valid registers, but it uses
1151 the above macros so we are in luck. Allow REG, REG+REG, REG+INDEX,
1152 INDEX+REG, REG-INDEX, and non floating SYMBOL_REF to the constant pool.
1153 Allow REG-only and AUTINC-REG if handling TImode or HImode. Other symbol
1154 refs must be forced though a static cell to ensure addressability. */
1155 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, LABEL) \
1157 if (BASE_REGISTER_RTX_P (X)) \
1159 else if ((GET_CODE (X) == POST_INC || GET_CODE (X) == PRE_DEC) \
1160 && GET_CODE (XEXP (X, 0)) == REG \
1161 && REG_OK_FOR_PRE_POST_P (XEXP (X, 0))) \
1163 else if (GET_MODE_SIZE (MODE) >= 4 && reload_completed \
1164 && (GET_CODE (X) == LABEL_REF \
1165 || (GET_CODE (X) == CONST \
1166 && GET_CODE (XEXP ((X), 0)) == PLUS \
1167 && GET_CODE (XEXP (XEXP ((X), 0), 0)) == LABEL_REF \
1168 && GET_CODE (XEXP (XEXP ((X), 0), 1)) == CONST_INT)))\
1170 else if ((MODE) == TImode) \
1172 else if ((MODE) == DImode || (TARGET_SOFT_FLOAT && (MODE) == DFmode)) \
1174 if (GET_CODE (X) == PLUS && BASE_REGISTER_RTX_P (XEXP (X, 0)) \
1175 && GET_CODE (XEXP (X, 1)) == CONST_INT) \
1177 HOST_WIDE_INT val = INTVAL (XEXP (X, 1)); \
1178 if (val == 4 || val == -4 || val == -8) \
1182 else if (GET_CODE (X) == PLUS) \
1184 rtx xop0 = XEXP(X,0); \
1185 rtx xop1 = XEXP(X,1); \
1187 if (BASE_REGISTER_RTX_P (xop0)) \
1188 GO_IF_LEGITIMATE_INDEX (MODE, REGNO (xop0), xop1, LABEL); \
1189 else if (BASE_REGISTER_RTX_P (xop1)) \
1190 GO_IF_LEGITIMATE_INDEX (MODE, REGNO (xop1), xop0, LABEL); \
1192 else if (GET_CODE (X) == MINUS) \
1194 rtx xop0 = XEXP (X,0); \
1195 rtx xop1 = XEXP (X,1); \
1197 if (BASE_REGISTER_RTX_P (xop0)) \
1198 GO_IF_LEGITIMATE_INDEX (MODE, -1, xop1, LABEL); \
1200 else if (GET_MODE_CLASS (MODE) != MODE_FLOAT \
1201 && GET_CODE (X) == SYMBOL_REF \
1202 && CONSTANT_POOL_ADDRESS_P (X)) \
1204 else if ((GET_CODE (X) == PRE_INC || GET_CODE (X) == POST_DEC) \
1205 && (GET_MODE_SIZE (MODE) <= 4) \
1206 && GET_CODE (XEXP (X, 0)) == REG \
1207 && REG_OK_FOR_PRE_POST_P (XEXP (X, 0))) \
1211 /* Try machine-dependent ways of modifying an illegitimate address
1212 to be legitimate. If we find one, return the new, valid address.
1213 This macro is used in only one place: `memory_address' in explow.c.
1215 OLDX is the address as it was before break_out_memory_refs was called.
1216 In some cases it is useful to look at this to decide what needs to be done.
1218 MODE and WIN are passed so that this macro can use
1219 GO_IF_LEGITIMATE_ADDRESS.
1221 It is always safe for this macro to do nothing. It exists to recognize
1222 opportunities to optimize the output.
1224 On the ARM, try to convert [REG, #BIGCONST]
1225 into ADD BASE, REG, #UPPERCONST and [BASE, #VALIDCONST],
1226 where VALIDCONST == 0 in case of TImode. */
1227 #define LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
1229 if (GET_CODE (X) == PLUS) \
1231 rtx xop0 = XEXP (X, 0); \
1232 rtx xop1 = XEXP (X, 1); \
1234 if (CONSTANT_P (xop0) && ! symbol_mentioned_p (xop0)) \
1235 xop0 = force_reg (SImode, xop0); \
1236 if (CONSTANT_P (xop1) && ! symbol_mentioned_p (xop1)) \
1237 xop1 = force_reg (SImode, xop1); \
1238 if (BASE_REGISTER_RTX_P (xop0) && GET_CODE (xop1) == CONST_INT) \
1240 HOST_WIDE_INT n, low_n; \
1241 rtx base_reg, val; \
1242 n = INTVAL (xop1); \
1244 if (MODE == DImode || (TARGET_SOFT_FLOAT && MODE == DFmode)) \
1256 low_n = ((MODE) == TImode ? 0 \
1257 : n >= 0 ? (n & 0xfff) : -((-n) & 0xfff)); \
1260 base_reg = gen_reg_rtx (SImode); \
1261 val = force_operand (gen_rtx (PLUS, SImode, xop0, \
1262 GEN_INT (n)), NULL_RTX); \
1263 emit_move_insn (base_reg, val); \
1264 (X) = (low_n == 0 ? base_reg \
1265 : gen_rtx (PLUS, SImode, base_reg, GEN_INT (low_n))); \
1267 else if (xop0 != XEXP (X, 0) || xop1 != XEXP (x, 1)) \
1268 (X) = gen_rtx (PLUS, SImode, xop0, xop1); \
1270 else if (GET_CODE (X) == MINUS) \
1272 rtx xop0 = XEXP (X, 0); \
1273 rtx xop1 = XEXP (X, 1); \
1275 if (CONSTANT_P (xop0)) \
1276 xop0 = force_reg (SImode, xop0); \
1277 if (CONSTANT_P (xop1) && ! symbol_mentioned_p (xop1)) \
1278 xop1 = force_reg (SImode, xop1); \
1279 if (xop0 != XEXP (X, 0) || xop1 != XEXP (X, 1)) \
1280 (X) = gen_rtx (MINUS, SImode, xop0, xop1); \
1282 if (memory_address_p (MODE, X)) \
1286 /* Go to LABEL if ADDR (a legitimate address expression)
1287 has an effect that depends on the machine mode it is used for. */
1288 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) \
1290 if (GET_CODE(ADDR) == PRE_DEC || GET_CODE(ADDR) == POST_DEC \
1291 || GET_CODE(ADDR) == PRE_INC || GET_CODE(ADDR) == POST_INC) \
1295 /* Specify the machine mode that this machine uses
1296 for the index in the tablejump instruction. */
1297 #define CASE_VECTOR_MODE SImode
1299 /* Define this if the tablejump instruction expects the table
1300 to contain offsets from the address of the table.
1301 Do not define this if the table should contain absolute addresses. */
1302 /* #define CASE_VECTOR_PC_RELATIVE */
1304 /* Specify the tree operation to be used to convert reals to integers. */
1305 #define IMPLICIT_FIX_EXPR FIX_ROUND_EXPR
1307 /* This is the kind of divide that is easiest to do in the general case. */
1308 #define EASY_DIV_EXPR TRUNC_DIV_EXPR
1310 /* signed 'char' is most compatible, but RISC OS wants it unsigned.
1311 unsigned is probably best, but may break some code. */
1312 #ifndef DEFAULT_SIGNED_CHAR
1313 #define DEFAULT_SIGNED_CHAR 0
1316 /* Don't cse the address of the function being compiled. */
1317 #define NO_RECURSIVE_FUNCTION_CSE 1
1319 /* Max number of bytes we can move from memory to memory
1320 in one reasonably fast instruction. */
1323 /* Define if operations between registers always perform the operation
1324 on the full register even if a narrower mode is specified. */
1325 #define WORD_REGISTER_OPERATIONS
1327 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
1328 will either zero-extend or sign-extend. The value of this macro should
1329 be the code that says which one of the two operations is implicitly
1330 done, NIL if none. */
1331 #define LOAD_EXTEND_OP(MODE) \
1332 ((arm_arch4 || (MODE) == QImode) ? ZERO_EXTEND \
1333 : ((BYTES_BIG_ENDIAN && (MODE) == HImode) ? SIGN_EXTEND : NIL))
1335 /* Define this if zero-extension is slow (more than one real instruction).
1336 On the ARM, it is more than one instruction only if not fetching from
1338 /* #define SLOW_ZERO_EXTEND */
1340 /* Nonzero if access to memory by bytes is slow and undesirable. */
1341 #define SLOW_BYTE_ACCESS 0
1343 /* Immediate shift counts are truncated by the output routines (or was it
1344 the assembler?). Shift counts in a register are truncated by ARM. Note
1345 that the native compiler puts too large (> 32) immediate shift counts
1346 into a register and shifts by the register, letting the ARM decide what
1347 to do instead of doing that itself. */
1348 /* This is all wrong. Defining SHIFT_COUNT_TRUNCATED tells combine that
1349 code like (X << (Y % 32)) for register X, Y is equivalent to (X << Y).
1350 On the arm, Y in a register is used modulo 256 for the shift. Only for
1351 rotates is modulo 32 used. */
1352 /* #define SHIFT_COUNT_TRUNCATED 1 */
1354 /* All integers have the same format so truncation is easy. */
1355 #define TRULY_NOOP_TRUNCATION(OUTPREC,INPREC) 1
1357 /* Calling from registers is a massive pain. */
1358 #define NO_FUNCTION_CSE 1
1360 /* Chars and shorts should be passed as ints. */
1361 #define PROMOTE_PROTOTYPES 1
1363 /* The machine modes of pointers and functions */
1364 #define Pmode SImode
1365 #define FUNCTION_MODE Pmode
1367 /* The structure type of the machine dependent info field of insns
1368 No uses for this yet. */
1369 /* #define INSN_MACHINE_INFO struct machine_info */
1371 /* The relative costs of various types of constants. Note that cse.c defines
1372 REG = 1, SUBREG = 2, any node = (2 + sum of subnodes). */
1373 #define CONST_COSTS(RTX, CODE, OUTER_CODE) \
1375 if (const_ok_for_arm (INTVAL (RTX))) \
1376 return (OUTER_CODE) == SET ? 2 : -1; \
1377 else if (OUTER_CODE == AND \
1378 && const_ok_for_arm (~INTVAL (RTX))) \
1380 else if ((OUTER_CODE == COMPARE \
1381 || OUTER_CODE == PLUS || OUTER_CODE == MINUS) \
1382 && const_ok_for_arm (-INTVAL (RTX))) \
1390 case CONST_DOUBLE: \
1391 if (const_double_rtx_ok_for_fpu (RTX)) \
1392 return (OUTER_CODE) == SET ? 2 : -1; \
1393 else if (((OUTER_CODE) == COMPARE || (OUTER_CODE) == PLUS) \
1394 && neg_const_double_rtx_ok_for_fpu (RTX)) \
1398 #define ARM_FRAME_RTX(X) \
1399 ((X) == frame_pointer_rtx || (X) == stack_pointer_rtx \
1400 || (X) == arg_pointer_rtx)
1402 #define RTX_COSTS(X,CODE,OUTER_CODE) \
1404 return arm_rtx_costs (X, CODE, OUTER_CODE);
1406 /* Moves to and from memory are quite expensive */
1407 #define MEMORY_MOVE_COST(MODE) 10
1409 /* All address computations that can be done are free, but rtx cost returns
1410 the same for practically all of them. So we weight the different types
1411 of address here in the order (most pref first):
1412 PRE/POST_INC/DEC, SHIFT or NON-INT sum, INT sum, REG, MEM or LABEL. */
1413 #define ADDRESS_COST(X) \
1414 (10 - ((GET_CODE (X) == MEM || GET_CODE (X) == LABEL_REF \
1415 || GET_CODE (X) == SYMBOL_REF) \
1417 : ((GET_CODE (X) == PRE_INC || GET_CODE (X) == PRE_DEC \
1418 || GET_CODE (X) == POST_INC || GET_CODE (X) == POST_DEC) \
1420 : (((GET_CODE (X) == PLUS || GET_CODE (X) == MINUS) \
1421 ? 6 + (GET_CODE (XEXP (X, 1)) == CONST_INT ? 2 \
1422 : ((GET_RTX_CLASS (GET_CODE (XEXP (X, 0))) == '2' \
1423 || GET_RTX_CLASS (GET_CODE (XEXP (X, 0))) == 'c' \
1424 || GET_RTX_CLASS (GET_CODE (XEXP (X, 1))) == '2' \
1425 || GET_RTX_CLASS (GET_CODE (XEXP (X, 1))) == 'c') \
1431 /* Try to generate sequences that don't involve branches, we can then use
1432 conditional instructions */
1433 #define BRANCH_COST 4
1435 /* Condition code information. */
1436 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
1437 return the mode to be used for the comparison.
1438 CCFPEmode should be used with floating inequalities,
1439 CCFPmode should be used with floating equalities.
1440 CC_NOOVmode should be used with SImode integer equalities.
1441 CCmode should be used otherwise. */
1443 #define EXTRA_CC_MODES CC_NOOVmode, CCFPmode, CCFPEmode
1445 #define EXTRA_CC_NAMES "CC_NOOV", "CCFP", "CCFPE"
1447 #define SELECT_CC_MODE(OP,X,Y) \
1448 (GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT \
1449 ? ((OP == EQ || OP == NE) ? CCFPmode : CCFPEmode) \
1450 : ((GET_MODE (X) == SImode) \
1451 && ((OP) == EQ || (OP) == NE) \
1452 && (GET_CODE (X) == PLUS || GET_CODE (X) == MINUS \
1453 || GET_CODE (X) == AND || GET_CODE (X) == IOR \
1454 || GET_CODE (X) == XOR || GET_CODE (X) == MULT \
1455 || GET_CODE (X) == NOT || GET_CODE (X) == NEG \
1456 || GET_CODE (X) == LSHIFTRT \
1457 || GET_CODE (X) == ASHIFT || GET_CODE (X) == ASHIFTRT \
1458 || GET_CODE (X) == ROTATERT || GET_CODE (X) == ZERO_EXTRACT) \
1460 : GET_MODE (X) == QImode ? CC_NOOVmode : CCmode))
1462 #define REVERSIBLE_CC_MODE(MODE) ((MODE) != CCFPEmode)
1464 #define STORE_FLAG_VALUE 1
1466 /* Define the information needed to generate branch insns. This is
1467 stored from the compare operation. Note that we can't use "rtx" here
1468 since it hasn't been defined! */
1470 extern struct rtx_def *arm_compare_op0, *arm_compare_op1;
1471 extern int arm_compare_fp;
1473 /* Define the codes that are matched by predicates in arm.c */
1474 #define PREDICATE_CODES \
1475 {"s_register_operand", {SUBREG, REG}}, \
1476 {"arm_add_operand", {SUBREG, REG, CONST_INT}}, \
1477 {"fpu_add_operand", {SUBREG, REG, CONST_DOUBLE}}, \
1478 {"arm_rhs_operand", {SUBREG, REG, CONST_INT}}, \
1479 {"fpu_rhs_operand", {SUBREG, REG, CONST_DOUBLE}}, \
1480 {"arm_not_operand", {SUBREG, REG, CONST_INT}}, \
1481 {"shiftable_operator", {PLUS, MINUS, AND, IOR, XOR}}, \
1482 {"minmax_operator", {SMIN, SMAX, UMIN, UMAX}}, \
1483 {"shift_operator", {ASHIFT, ASHIFTRT, LSHIFTRT, ROTATERT, MULT}}, \
1484 {"di_operand", {SUBREG, REG, CONST_INT, CONST_DOUBLE, MEM}}, \
1485 {"soft_df_operand", {SUBREG, REG, CONST_DOUBLE, MEM}}, \
1486 {"load_multiple_operation", {PARALLEL}}, \
1487 {"store_multiple_operation", {PARALLEL}}, \
1488 {"equality_operator", {EQ, NE}}, \
1489 {"arm_rhsm_operand", {SUBREG, REG, CONST_INT, MEM}}, \
1490 {"const_shift_operand", {CONST_INT}}, \
1491 {"index_operand", {SUBREG, REG, CONST_INT}}, \
1492 {"reg_or_int_operand", {SUBREG, REG, CONST_INT}}, \
1493 {"multi_register_push", {PARALLEL}}, \
1494 {"cc_register", {REG}}, \
1495 {"reversible_cc_register", {REG}},
1499 /* Gcc puts the pool in the wrong place for ARM, since we can only
1500 load addresses a limited distance around the pc. We do some
1501 special munging to move the constant pool values to the correct
1502 point in the code. */
1503 #define MACHINE_DEPENDENT_REORG(INSN) arm_reorg ((INSN))
1505 /* The pool is empty, since we have moved everything into the code. */
1506 #define ASM_OUTPUT_SPECIAL_POOL_ENTRY(FILE,X,MODE,ALIGN,LABELNO,JUMPTO) \
1509 /* Output an internal label definition. */
1510 #define ASM_OUTPUT_INTERNAL_LABEL(STREAM, PREFIX, NUM) \
1513 char *s = (char *) alloca (40 + strlen (PREFIX)); \
1514 extern int arm_target_label, arm_ccfsm_state; \
1515 extern rtx arm_target_insn; \
1517 if (arm_ccfsm_state == 3 && arm_target_label == (NUM) \
1518 && !strcmp (PREFIX, "L")) \
1520 arm_ccfsm_state = 0; \
1521 arm_target_insn = NULL; \
1523 ASM_GENERATE_INTERNAL_LABEL (s, (PREFIX), (NUM)); \
1524 arm_asm_output_label (STREAM, s); \
1527 /* Output a label definition. */
1528 #define ASM_OUTPUT_LABEL(STREAM,NAME) \
1529 arm_asm_output_label ((STREAM), (NAME))
1531 /* Output a push or a pop instruction (only used when profiling). */
1532 #define ASM_OUTPUT_REG_PUSH(STREAM,REGNO) \
1533 fprintf(STREAM,"\tstmfd\t%ssp!,{%s%s}\n", \
1534 REGISTER_PREFIX, REGISTER_PREFIX, reg_names[REGNO])
1536 #define ASM_OUTPUT_REG_POP(STREAM,REGNO) \
1537 fprintf(STREAM,"\tldmfd\t%ssp!,{%s%s}\n", \
1538 REGISTER_PREFIX, REGISTER_PREFIX, reg_names[REGNO])
1540 /* Target characters. */
1541 #define TARGET_BELL 007
1542 #define TARGET_BS 010
1543 #define TARGET_TAB 011
1544 #define TARGET_NEWLINE 012
1545 #define TARGET_VT 013
1546 #define TARGET_FF 014
1547 #define TARGET_CR 015
1549 /* Only perform branch elimination (by making instructions conditional) if
1550 we're optimising. Otherwise it's of no use anyway. */
1551 #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \
1553 final_prescan_insn (INSN, OPVEC, NOPERANDS)
1555 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) \
1556 ((CODE) == '?' || (CODE) == '|' || (CODE) == '@')
1557 /* Output an operand of an instruction. */
1558 #define PRINT_OPERAND(STREAM, X, CODE) \
1559 arm_print_operand (STREAM, X, CODE)
1561 #define ARM_SIGN_EXTEND(x) ((HOST_WIDE_INT) \
1562 (HOST_BITS_PER_WIDE_INT <= 32 ? (x) \
1563 : (((x) & (unsigned HOST_WIDE_INT) 0xffffffff) | \
1564 (((x) & (unsigned HOST_WIDE_INT) 0x80000000) \
1565 ? ((~ (HOST_WIDE_INT) 0) \
1566 & ~ (unsigned HOST_WIDE_INT) 0xffffffff) \
1569 /* Output the address of an operand. */
1570 #define PRINT_OPERAND_ADDRESS(STREAM,X) \
1572 int is_minus = GET_CODE (X) == MINUS; \
1574 if (GET_CODE (X) == REG) \
1575 fprintf (STREAM, "[%s%s, #0]", REGISTER_PREFIX, \
1576 reg_names[REGNO (X)]); \
1577 else if (GET_CODE (X) == PLUS || is_minus) \
1579 rtx base = XEXP (X, 0); \
1580 rtx index = XEXP (X, 1); \
1581 char *base_reg_name; \
1582 HOST_WIDE_INT offset = 0; \
1583 if (GET_CODE (base) != REG) \
1585 /* Ensure that BASE is a register (one of them must be). */ \
1590 base_reg_name = reg_names[REGNO (base)]; \
1591 switch (GET_CODE (index)) \
1594 offset = INTVAL (index); \
1597 fprintf (STREAM, "[%s%s, #%d]", REGISTER_PREFIX, \
1598 base_reg_name, offset); \
1602 fprintf (STREAM, "[%s%s, %s%s%s]", REGISTER_PREFIX, \
1603 base_reg_name, is_minus ? "-" : "", \
1604 REGISTER_PREFIX, reg_names[REGNO (index)] ); \
1613 fprintf (STREAM, "[%s%s, %s%s%s", REGISTER_PREFIX, \
1614 base_reg_name, is_minus ? "-" : "", REGISTER_PREFIX,\
1615 reg_names[REGNO (XEXP (index, 0))]); \
1616 arm_print_operand (STREAM, index, 'S'); \
1617 fputs ("]", STREAM); \
1625 else if (GET_CODE (X) == PRE_INC || GET_CODE (X) == POST_INC \
1626 || GET_CODE (X) == PRE_DEC || GET_CODE (X) == POST_DEC) \
1628 extern int output_memory_reference_mode; \
1630 if (GET_CODE (XEXP (X, 0)) != REG) \
1633 if (GET_CODE (X) == PRE_DEC || GET_CODE (X) == PRE_INC) \
1634 fprintf (STREAM, "[%s%s, #%s%d]!", REGISTER_PREFIX, \
1635 reg_names[REGNO (XEXP (X, 0))], \
1636 GET_CODE (X) == PRE_DEC ? "-" : "", \
1637 GET_MODE_SIZE (output_memory_reference_mode)); \
1639 fprintf (STREAM, "[%s%s], #%s%d", REGISTER_PREFIX, \
1640 reg_names[REGNO (XEXP (X, 0))], \
1641 GET_CODE (X) == POST_DEC ? "-" : "", \
1642 GET_MODE_SIZE (output_memory_reference_mode)); \
1644 else output_addr_const(STREAM, X); \
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