1 /* Output routines for GCC for ARM.
2 Copyright (C) 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001,
3 2002, 2003, 2004 Free Software Foundation, Inc.
4 Contributed by Pieter `Tiggr' Schoenmakers (rcpieter@win.tue.nl)
5 and Martin Simmons (@harleqn.co.uk).
6 More major hacks by Richard Earnshaw (rearnsha@arm.com).
8 This file is part of GCC.
10 GCC is free software; you can redistribute it and/or modify it
11 under the terms of the GNU General Public License as published
12 by the Free Software Foundation; either version 2, or (at your
13 option) any later version.
15 GCC is distributed in the hope that it will be useful, but WITHOUT
16 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
17 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
18 License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GCC; see the file COPYING. If not, write to
22 the Free Software Foundation, 59 Temple Place - Suite 330,
23 Boston, MA 02111-1307, USA. */
27 #include "coretypes.h"
33 #include "hard-reg-set.h"
35 #include "insn-config.h"
36 #include "conditions.h"
38 #include "insn-attr.h"
49 #include "integrate.h"
52 #include "target-def.h"
55 /* Forward definitions of types. */
56 typedef struct minipool_node Mnode;
57 typedef struct minipool_fixup Mfix;
59 const struct attribute_spec arm_attribute_table[];
61 /* Forward function declarations. */
62 static arm_stack_offsets *arm_get_frame_offsets (void);
63 static void arm_add_gc_roots (void);
64 static int arm_gen_constant (enum rtx_code, enum machine_mode, rtx,
65 HOST_WIDE_INT, rtx, rtx, int, int);
66 static unsigned bit_count (unsigned long);
67 static int arm_address_register_rtx_p (rtx, int);
68 static int arm_legitimate_index_p (enum machine_mode, rtx, RTX_CODE, int);
69 static int thumb_base_register_rtx_p (rtx, enum machine_mode, int);
70 inline static int thumb_index_register_rtx_p (rtx, int);
71 static int thumb_far_jump_used_p (void);
72 static int const_ok_for_op (HOST_WIDE_INT, enum rtx_code);
73 static rtx emit_multi_reg_push (int);
74 static rtx emit_sfm (int, int);
76 static bool arm_assemble_integer (rtx, unsigned int, int);
78 static const char *fp_const_from_val (REAL_VALUE_TYPE *);
79 static arm_cc get_arm_condition_code (rtx);
80 static HOST_WIDE_INT int_log2 (HOST_WIDE_INT);
81 static rtx is_jump_table (rtx);
82 static const char *output_multi_immediate (rtx *, const char *, const char *,
84 static void print_multi_reg (FILE *, const char *, int, int);
85 static const char *shift_op (rtx, HOST_WIDE_INT *);
86 static struct machine_function *arm_init_machine_status (void);
87 static int number_of_first_bit_set (int);
88 static void replace_symbols_in_block (tree, rtx, rtx);
89 static void thumb_exit (FILE *, int, rtx);
90 static void thumb_pushpop (FILE *, int, int, int *, int);
91 static rtx is_jump_table (rtx);
92 static HOST_WIDE_INT get_jump_table_size (rtx);
93 static Mnode *move_minipool_fix_forward_ref (Mnode *, Mnode *, HOST_WIDE_INT);
94 static Mnode *add_minipool_forward_ref (Mfix *);
95 static Mnode *move_minipool_fix_backward_ref (Mnode *, Mnode *, HOST_WIDE_INT);
96 static Mnode *add_minipool_backward_ref (Mfix *);
97 static void assign_minipool_offsets (Mfix *);
98 static void arm_print_value (FILE *, rtx);
99 static void dump_minipool (rtx);
100 static int arm_barrier_cost (rtx);
101 static Mfix *create_fix_barrier (Mfix *, HOST_WIDE_INT);
102 static void push_minipool_barrier (rtx, HOST_WIDE_INT);
103 static void push_minipool_fix (rtx, HOST_WIDE_INT, rtx *, enum machine_mode,
105 static void arm_reorg (void);
106 static bool note_invalid_constants (rtx, HOST_WIDE_INT, int);
107 static int current_file_function_operand (rtx);
108 static unsigned long arm_compute_save_reg0_reg12_mask (void);
109 static unsigned long arm_compute_save_reg_mask (void);
110 static unsigned long arm_isr_value (tree);
111 static unsigned long arm_compute_func_type (void);
112 static tree arm_handle_fndecl_attribute (tree *, tree, tree, int, bool *);
113 static tree arm_handle_isr_attribute (tree *, tree, tree, int, bool *);
114 static void arm_output_function_epilogue (FILE *, HOST_WIDE_INT);
115 static void arm_output_function_prologue (FILE *, HOST_WIDE_INT);
116 static void thumb_output_function_prologue (FILE *, HOST_WIDE_INT);
117 static int arm_comp_type_attributes (tree, tree);
118 static void arm_set_default_type_attributes (tree);
119 static int arm_adjust_cost (rtx, rtx, rtx, int);
120 static int arm_use_dfa_pipeline_interface (void);
121 static int count_insns_for_constant (HOST_WIDE_INT, int);
122 static int arm_get_strip_length (int);
123 static bool arm_function_ok_for_sibcall (tree, tree);
124 static void arm_internal_label (FILE *, const char *, unsigned long);
125 static void arm_output_mi_thunk (FILE *, tree, HOST_WIDE_INT, HOST_WIDE_INT,
127 static int arm_rtx_costs_1 (rtx, enum rtx_code, enum rtx_code);
128 static bool arm_slowmul_rtx_costs (rtx, int, int, int *);
129 static bool arm_fastmul_rtx_costs (rtx, int, int, int *);
130 static bool arm_xscale_rtx_costs (rtx, int, int, int *);
131 static bool arm_9e_rtx_costs (rtx, int, int, int *);
132 static int arm_address_cost (rtx);
133 static bool arm_memory_load_p (rtx);
134 static bool arm_cirrus_insn_p (rtx);
135 static void cirrus_reorg (rtx);
136 static void arm_init_builtins (void);
137 static rtx arm_expand_builtin (tree, rtx, rtx, enum machine_mode, int);
138 static void arm_init_iwmmxt_builtins (void);
139 static rtx safe_vector_operand (rtx, enum machine_mode);
140 static rtx arm_expand_binop_builtin (enum insn_code, tree, rtx);
141 static rtx arm_expand_unop_builtin (enum insn_code, tree, rtx, int);
142 static rtx arm_expand_builtin (tree, rtx, rtx, enum machine_mode, int);
143 static void emit_constant_insn (rtx cond, rtx pattern);
145 #ifdef OBJECT_FORMAT_ELF
146 static void arm_elf_asm_named_section (const char *, unsigned int);
149 static void arm_encode_section_info (tree, rtx, int);
152 static void aof_globalize_label (FILE *, const char *);
153 static void aof_dump_imports (FILE *);
154 static void aof_dump_pic_table (FILE *);
155 static void aof_file_start (void);
156 static void aof_file_end (void);
158 static rtx arm_struct_value_rtx (tree, int);
159 static void arm_setup_incoming_varargs (CUMULATIVE_ARGS *, enum machine_mode,
161 static bool arm_promote_prototypes (tree);
164 /* Initialize the GCC target structure. */
165 #ifdef TARGET_DLLIMPORT_DECL_ATTRIBUTES
166 #undef TARGET_MERGE_DECL_ATTRIBUTES
167 #define TARGET_MERGE_DECL_ATTRIBUTES merge_dllimport_decl_attributes
170 #undef TARGET_ATTRIBUTE_TABLE
171 #define TARGET_ATTRIBUTE_TABLE arm_attribute_table
174 #undef TARGET_ASM_BYTE_OP
175 #define TARGET_ASM_BYTE_OP "\tDCB\t"
176 #undef TARGET_ASM_ALIGNED_HI_OP
177 #define TARGET_ASM_ALIGNED_HI_OP "\tDCW\t"
178 #undef TARGET_ASM_ALIGNED_SI_OP
179 #define TARGET_ASM_ALIGNED_SI_OP "\tDCD\t"
180 #undef TARGET_ASM_GLOBALIZE_LABEL
181 #define TARGET_ASM_GLOBALIZE_LABEL aof_globalize_label
182 #undef TARGET_ASM_FILE_START
183 #define TARGET_ASM_FILE_START aof_file_start
184 #undef TARGET_ASM_FILE_END
185 #define TARGET_ASM_FILE_END aof_file_end
187 #undef TARGET_ASM_ALIGNED_SI_OP
188 #define TARGET_ASM_ALIGNED_SI_OP NULL
189 #undef TARGET_ASM_INTEGER
190 #define TARGET_ASM_INTEGER arm_assemble_integer
193 #undef TARGET_ASM_FUNCTION_PROLOGUE
194 #define TARGET_ASM_FUNCTION_PROLOGUE arm_output_function_prologue
196 #undef TARGET_ASM_FUNCTION_EPILOGUE
197 #define TARGET_ASM_FUNCTION_EPILOGUE arm_output_function_epilogue
199 #undef TARGET_COMP_TYPE_ATTRIBUTES
200 #define TARGET_COMP_TYPE_ATTRIBUTES arm_comp_type_attributes
202 #undef TARGET_SET_DEFAULT_TYPE_ATTRIBUTES
203 #define TARGET_SET_DEFAULT_TYPE_ATTRIBUTES arm_set_default_type_attributes
205 #undef TARGET_SCHED_ADJUST_COST
206 #define TARGET_SCHED_ADJUST_COST arm_adjust_cost
208 #undef TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE
209 #define TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE arm_use_dfa_pipeline_interface
211 #undef TARGET_ENCODE_SECTION_INFO
213 #define TARGET_ENCODE_SECTION_INFO arm_pe_encode_section_info
215 #define TARGET_ENCODE_SECTION_INFO arm_encode_section_info
218 #undef TARGET_STRIP_NAME_ENCODING
219 #define TARGET_STRIP_NAME_ENCODING arm_strip_name_encoding
221 #undef TARGET_ASM_INTERNAL_LABEL
222 #define TARGET_ASM_INTERNAL_LABEL arm_internal_label
224 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
225 #define TARGET_FUNCTION_OK_FOR_SIBCALL arm_function_ok_for_sibcall
227 #undef TARGET_ASM_OUTPUT_MI_THUNK
228 #define TARGET_ASM_OUTPUT_MI_THUNK arm_output_mi_thunk
229 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
230 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK default_can_output_mi_thunk_no_vcall
232 /* This will be overridden in arm_override_options. */
233 #undef TARGET_RTX_COSTS
234 #define TARGET_RTX_COSTS arm_slowmul_rtx_costs
235 #undef TARGET_ADDRESS_COST
236 #define TARGET_ADDRESS_COST arm_address_cost
238 #undef TARGET_MACHINE_DEPENDENT_REORG
239 #define TARGET_MACHINE_DEPENDENT_REORG arm_reorg
241 #undef TARGET_INIT_BUILTINS
242 #define TARGET_INIT_BUILTINS arm_init_builtins
243 #undef TARGET_EXPAND_BUILTIN
244 #define TARGET_EXPAND_BUILTIN arm_expand_builtin
246 #undef TARGET_PROMOTE_FUNCTION_ARGS
247 #define TARGET_PROMOTE_FUNCTION_ARGS hook_bool_tree_true
248 #undef TARGET_PROMOTE_FUNCTION_RETURN
249 #define TARGET_PROMOTE_FUNCTION_RETURN hook_bool_tree_true
250 #undef TARGET_PROMOTE_PROTOTYPES
251 #define TARGET_PROMOTE_PROTOTYPES arm_promote_prototypes
253 #undef TARGET_STRUCT_VALUE_RTX
254 #define TARGET_STRUCT_VALUE_RTX arm_struct_value_rtx
256 #undef TARGET_SETUP_INCOMING_VARARGS
257 #define TARGET_SETUP_INCOMING_VARARGS arm_setup_incoming_varargs
259 struct gcc_target targetm = TARGET_INITIALIZER;
261 /* Obstack for minipool constant handling. */
262 static struct obstack minipool_obstack;
263 static char * minipool_startobj;
265 /* The maximum number of insns skipped which
266 will be conditionalised if possible. */
267 static int max_insns_skipped = 5;
269 extern FILE * asm_out_file;
271 /* True if we are currently building a constant table. */
272 int making_const_table;
274 /* Define the information needed to generate branch insns. This is
275 stored from the compare operation. */
276 rtx arm_compare_op0, arm_compare_op1;
278 /* The processor for which instructions should be scheduled. */
279 enum processor_type arm_tune = arm_none;
281 /* Which floating point model to use. */
282 enum arm_fp_model arm_fp_model;
284 /* Which floating point hardware is available. */
285 enum fputype arm_fpu_arch;
287 /* Which floating point hardware to schedule for. */
288 enum fputype arm_fpu_tune;
290 /* Whether to use floating point hardware. */
291 enum float_abi_type arm_float_abi;
293 /* Which ABI to use. */
294 enum arm_abi_type arm_abi;
296 /* What program mode is the cpu running in? 26-bit mode or 32-bit mode. */
297 enum prog_mode_type arm_prgmode;
299 /* Set by the -mfpu=... option. */
300 const char * target_fpu_name = NULL;
302 /* Set by the -mfpe=... option. */
303 const char * target_fpe_name = NULL;
305 /* Set by the -mfloat-abi=... option. */
306 const char * target_float_abi_name = NULL;
308 /* Set by the -mabi=... option. */
309 const char * target_abi_name = NULL;
311 /* Used to parse -mstructure_size_boundary command line option. */
312 const char * structure_size_string = NULL;
313 int arm_structure_size_boundary = DEFAULT_STRUCTURE_SIZE_BOUNDARY;
315 /* Bit values used to identify processor capabilities. */
316 #define FL_CO_PROC (1 << 0) /* Has external co-processor bus */
317 #define FL_ARCH3M (1 << 1) /* Extended multiply */
318 #define FL_MODE26 (1 << 2) /* 26-bit mode support */
319 #define FL_MODE32 (1 << 3) /* 32-bit mode support */
320 #define FL_ARCH4 (1 << 4) /* Architecture rel 4 */
321 #define FL_ARCH5 (1 << 5) /* Architecture rel 5 */
322 #define FL_THUMB (1 << 6) /* Thumb aware */
323 #define FL_LDSCHED (1 << 7) /* Load scheduling necessary */
324 #define FL_STRONG (1 << 8) /* StrongARM */
325 #define FL_ARCH5E (1 << 9) /* DSP extensions to v5 */
326 #define FL_XSCALE (1 << 10) /* XScale */
327 #define FL_CIRRUS (1 << 11) /* Cirrus/DSP. */
328 #define FL_ARCH6 (1 << 12) /* Architecture rel 6. Adds
329 media instructions. */
330 #define FL_VFPV2 (1 << 13) /* Vector Floating Point V2. */
332 #define FL_IWMMXT (1 << 29) /* XScale v2 or "Intel Wireless MMX technology". */
334 #define FL_FOR_ARCH2 0
335 #define FL_FOR_ARCH3 FL_MODE32
336 #define FL_FOR_ARCH3M (FL_FOR_ARCH3 | FL_ARCH3M)
337 #define FL_FOR_ARCH4 (FL_FOR_ARCH3M | FL_ARCH4)
338 #define FL_FOR_ARCH4T (FL_FOR_ARCH4 | FL_THUMB)
339 #define FL_FOR_ARCH5 (FL_FOR_ARCH4 | FL_ARCH5)
340 #define FL_FOR_ARCH5T (FL_FOR_ARCH5 | FL_THUMB)
341 #define FL_FOR_ARCH5E (FL_FOR_ARCH5 | FL_ARCH5E)
342 #define FL_FOR_ARCH5TE (FL_FOR_ARCH5E | FL_THUMB)
343 #define FL_FOR_ARCH5TEJ FL_FOR_ARCH5TE
344 #define FL_FOR_ARCH6 (FL_FOR_ARCH5TE | FL_ARCH6)
345 #define FL_FOR_ARCH6J FL_FOR_ARCH6
347 /* The bits in this mask specify which
348 instructions we are allowed to generate. */
349 static unsigned long insn_flags = 0;
351 /* The bits in this mask specify which instruction scheduling options should
353 static unsigned long tune_flags = 0;
355 /* The following are used in the arm.md file as equivalents to bits
356 in the above two flag variables. */
358 /* Nonzero if this chip supports the ARM Architecture 3M extensions. */
361 /* Nonzero if this chip supports the ARM Architecture 4 extensions. */
364 /* Nonzero if this chip supports the ARM Architecture 5 extensions. */
367 /* Nonzero if this chip supports the ARM Architecture 5E extensions. */
370 /* Nonzero if this chip supports the ARM Architecture 6 extensions. */
373 /* Nonzero if this chip can benefit from load scheduling. */
374 int arm_ld_sched = 0;
376 /* Nonzero if this chip is a StrongARM. */
377 int arm_is_strong = 0;
379 /* Nonzero if this chip is a Cirrus variant. */
380 int arm_arch_cirrus = 0;
382 /* Nonzero if this chip supports Intel Wireless MMX technology. */
383 int arm_arch_iwmmxt = 0;
385 /* Nonzero if this chip is an XScale. */
386 int arm_arch_xscale = 0;
388 /* Nonzero if tuning for XScale */
389 int arm_tune_xscale = 0;
391 /* Nonzero if this chip is an ARM6 or an ARM7. */
392 int arm_is_6_or_7 = 0;
394 /* Nonzero if generating Thumb instructions. */
397 /* In case of a PRE_INC, POST_INC, PRE_DEC, POST_DEC memory reference, we
398 must report the mode of the memory reference from PRINT_OPERAND to
399 PRINT_OPERAND_ADDRESS. */
400 enum machine_mode output_memory_reference_mode;
402 /* The register number to be used for the PIC offset register. */
403 const char * arm_pic_register_string = NULL;
404 int arm_pic_register = INVALID_REGNUM;
406 /* Set to 1 when a return insn is output, this means that the epilogue
408 int return_used_this_function;
410 /* Set to 1 after arm_reorg has started. Reset to start at the start of
411 the next function. */
412 static int after_arm_reorg = 0;
414 /* The maximum number of insns to be used when loading a constant. */
415 static int arm_constant_limit = 3;
417 /* For an explanation of these variables, see final_prescan_insn below. */
419 enum arm_cond_code arm_current_cc;
421 int arm_target_label;
423 /* The condition codes of the ARM, and the inverse function. */
424 static const char * const arm_condition_codes[] =
426 "eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc",
427 "hi", "ls", "ge", "lt", "gt", "le", "al", "nv"
430 #define streq(string1, string2) (strcmp (string1, string2) == 0)
432 /* Initialization code. */
436 const char *const name;
437 enum processor_type core;
439 const unsigned long flags;
440 bool (* rtx_costs) (rtx, int, int, int *);
443 /* Not all of these give usefully different compilation alternatives,
444 but there is no simple way of generalizing them. */
445 static const struct processors all_cores[] =
448 #define ARM_CORE(NAME, ARCH, FLAGS, COSTS) \
449 {#NAME, arm_none, #ARCH, FLAGS | FL_FOR_ARCH##ARCH, arm_##COSTS##_rtx_costs},
450 #include "arm-cores.def"
452 {NULL, arm_none, NULL, 0, NULL}
455 static const struct processors all_architectures[] =
457 /* ARM Architectures */
458 /* We don't specify rtx_costs here as it will be figured out
461 {"armv2", arm2, "2", FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH2, NULL},
462 {"armv2a", arm2, "2", FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH2, NULL},
463 {"armv3", arm6, "3", FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH3, NULL},
464 {"armv3m", arm7m, "3M", FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH3M, NULL},
465 {"armv4", arm7tdmi, "4", FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH4, NULL},
466 /* Strictly, FL_MODE26 is a permitted option for v4t, but there are no
467 implementations that support it, so we will leave it out for now. */
468 {"armv4t", arm7tdmi, "4T", FL_CO_PROC | FL_FOR_ARCH4T, NULL},
469 {"armv5", arm10tdmi, "5", FL_CO_PROC | FL_FOR_ARCH5, NULL},
470 {"armv5t", arm10tdmi, "5T", FL_CO_PROC | FL_FOR_ARCH5T, NULL},
471 {"armv5e", arm1026ejs, "5E", FL_CO_PROC | FL_FOR_ARCH5E, NULL},
472 {"armv5te", arm1026ejs, "5TE", FL_CO_PROC | FL_FOR_ARCH5TE, NULL},
473 {"armv6", arm1136js, "6", FL_CO_PROC | FL_FOR_ARCH6, NULL},
474 {"armv6j", arm1136js, "6J", FL_CO_PROC | FL_FOR_ARCH6J, NULL},
475 {"ep9312", ep9312, "4T", FL_LDSCHED | FL_CIRRUS | FL_FOR_ARCH4, NULL},
476 {"iwmmxt", iwmmxt, "5TE", FL_LDSCHED | FL_STRONG | FL_FOR_ARCH5TE | FL_XSCALE | FL_IWMMXT , NULL},
477 {NULL, arm_none, NULL, 0 , NULL}
480 /* This is a magic structure. The 'string' field is magically filled in
481 with a pointer to the value specified by the user on the command line
482 assuming that the user has specified such a value. */
484 struct arm_cpu_select arm_select[] =
486 /* string name processors */
487 { NULL, "-mcpu=", all_cores },
488 { NULL, "-march=", all_architectures },
489 { NULL, "-mtune=", all_cores }
493 /* The name of the proprocessor macro to define for this architecture. */
495 char arm_arch_name[] = "__ARM_ARCH_0UNK__";
504 /* Available values for for -mfpu=. */
506 static const struct fpu_desc all_fpus[] =
508 {"fpa", FPUTYPE_FPA},
509 {"fpe2", FPUTYPE_FPA_EMU2},
510 {"fpe3", FPUTYPE_FPA_EMU2},
511 {"maverick", FPUTYPE_MAVERICK},
516 /* Floating point models used by the different hardware.
517 See fputype in arm.h. */
519 static const enum fputype fp_model_for_fpu[] =
521 /* No FP hardware. */
522 ARM_FP_MODEL_UNKNOWN, /* FPUTYPE_NONE */
523 ARM_FP_MODEL_FPA, /* FPUTYPE_FPA */
524 ARM_FP_MODEL_FPA, /* FPUTYPE_FPA_EMU2 */
525 ARM_FP_MODEL_FPA, /* FPUTYPE_FPA_EMU3 */
526 ARM_FP_MODEL_MAVERICK, /* FPUTYPE_MAVERICK */
527 ARM_FP_MODEL_VFP /* FPUTYPE_VFP */
534 enum float_abi_type abi_type;
538 /* Available values for -mfloat-abi=. */
540 static const struct float_abi all_float_abis[] =
542 {"soft", ARM_FLOAT_ABI_SOFT},
543 {"softfp", ARM_FLOAT_ABI_SOFTFP},
544 {"hard", ARM_FLOAT_ABI_HARD}
551 enum arm_abi_type abi_type;
555 /* Available values for -mabi=. */
557 static const struct abi_name arm_all_abis[] =
559 {"apcs-gnu", ARM_ABI_APCS},
560 {"atpcs", ARM_ABI_ATPCS},
561 {"aapcs", ARM_ABI_AAPCS},
562 {"iwmmxt", ARM_ABI_IWMMXT}
565 /* Return the number of bits set in VALUE. */
567 bit_count (unsigned long value)
569 unsigned long count = 0;
574 value &= value - 1; /* Clear the least-significant set bit. */
580 /* Fix up any incompatible options that the user has specified.
581 This has now turned into a maze. */
583 arm_override_options (void)
587 /* Set up the flags based on the cpu/architecture selected by the user. */
588 for (i = ARRAY_SIZE (arm_select); i--;)
590 struct arm_cpu_select * ptr = arm_select + i;
592 if (ptr->string != NULL && ptr->string[0] != '\0')
594 const struct processors * sel;
596 for (sel = ptr->processors; sel->name != NULL; sel++)
597 if (streq (ptr->string, sel->name))
599 /* Set the architecture define. */
601 sprintf (arm_arch_name, "__ARM_ARCH_%s__", sel->arch);
603 /* Determine the processor core for which we should
604 tune code-generation. */
605 if (/* -mcpu= is a sensible default. */
607 /* If -march= is used, and -mcpu= has not been used,
608 assume that we should tune for a representative
609 CPU from that architecture. */
611 /* -mtune= overrides -mcpu= and -march=. */
613 arm_tune = (enum processor_type) (sel - ptr->processors);
617 /* If we have been given an architecture and a processor
618 make sure that they are compatible. We only generate
619 a warning though, and we prefer the CPU over the
621 if (insn_flags != 0 && (insn_flags ^ sel->flags))
622 warning ("switch -mcpu=%s conflicts with -march= switch",
625 insn_flags = sel->flags;
631 if (sel->name == NULL)
632 error ("bad value (%s) for %s switch", ptr->string, ptr->name);
636 /* If the user did not specify a processor, choose one for them. */
639 const struct processors * sel;
641 enum processor_type cpu;
643 cpu = TARGET_CPU_DEFAULT;
646 #ifdef SUBTARGET_CPU_DEFAULT
647 /* Use the subtarget default CPU if none was specified by
649 cpu = SUBTARGET_CPU_DEFAULT;
651 /* Default to ARM6. */
655 sel = &all_cores[cpu];
657 insn_flags = sel->flags;
659 /* Now check to see if the user has specified some command line
660 switch that require certain abilities from the cpu. */
663 if (TARGET_INTERWORK || TARGET_THUMB)
665 sought |= (FL_THUMB | FL_MODE32);
667 /* Force apcs-32 to be used for interworking. */
668 target_flags |= ARM_FLAG_APCS_32;
670 /* There are no ARM processors that support both APCS-26 and
671 interworking. Therefore we force FL_MODE26 to be removed
672 from insn_flags here (if it was set), so that the search
673 below will always be able to find a compatible processor. */
674 insn_flags &= ~FL_MODE26;
676 else if (!TARGET_APCS_32)
679 if (sought != 0 && ((sought & insn_flags) != sought))
681 /* Try to locate a CPU type that supports all of the abilities
682 of the default CPU, plus the extra abilities requested by
684 for (sel = all_cores; sel->name != NULL; sel++)
685 if ((sel->flags & sought) == (sought | insn_flags))
688 if (sel->name == NULL)
690 unsigned current_bit_count = 0;
691 const struct processors * best_fit = NULL;
693 /* Ideally we would like to issue an error message here
694 saying that it was not possible to find a CPU compatible
695 with the default CPU, but which also supports the command
696 line options specified by the programmer, and so they
697 ought to use the -mcpu=<name> command line option to
698 override the default CPU type.
700 Unfortunately this does not work with multilibing. We
701 need to be able to support multilibs for -mapcs-26 and for
702 -mthumb-interwork and there is no CPU that can support both
703 options. Instead if we cannot find a cpu that has both the
704 characteristics of the default cpu and the given command line
705 options we scan the array again looking for a best match. */
706 for (sel = all_cores; sel->name != NULL; sel++)
707 if ((sel->flags & sought) == sought)
711 count = bit_count (sel->flags & insn_flags);
713 if (count >= current_bit_count)
716 current_bit_count = count;
720 if (best_fit == NULL)
726 insn_flags = sel->flags;
728 sprintf (arm_arch_name, "__ARM_ARCH_%s__", sel->arch);
729 if (arm_tune == arm_none)
730 arm_tune = (enum processor_type) (sel - all_cores);
733 /* The processor for which we should tune should now have been
735 if (arm_tune == arm_none)
738 tune_flags = all_cores[(int)arm_tune].flags;
739 targetm.rtx_costs = all_cores[(int)arm_tune].rtx_costs;
741 /* Make sure that the processor choice does not conflict with any of the
742 other command line choices. */
743 if (TARGET_APCS_32 && !(insn_flags & FL_MODE32))
745 /* If APCS-32 was not the default then it must have been set by the
746 user, so issue a warning message. If the user has specified
747 "-mapcs-32 -mcpu=arm2" then we loose here. */
748 if ((TARGET_DEFAULT & ARM_FLAG_APCS_32) == 0)
749 warning ("target CPU does not support APCS-32" );
750 target_flags &= ~ARM_FLAG_APCS_32;
752 else if (!TARGET_APCS_32 && !(insn_flags & FL_MODE26))
754 warning ("target CPU does not support APCS-26" );
755 target_flags |= ARM_FLAG_APCS_32;
758 if (TARGET_INTERWORK && !(insn_flags & FL_THUMB))
760 warning ("target CPU does not support interworking" );
761 target_flags &= ~ARM_FLAG_INTERWORK;
764 if (TARGET_THUMB && !(insn_flags & FL_THUMB))
766 warning ("target CPU does not support THUMB instructions");
767 target_flags &= ~ARM_FLAG_THUMB;
770 if (TARGET_APCS_FRAME && TARGET_THUMB)
772 /* warning ("ignoring -mapcs-frame because -mthumb was used"); */
773 target_flags &= ~ARM_FLAG_APCS_FRAME;
776 /* TARGET_BACKTRACE calls leaf_function_p, which causes a crash if done
777 from here where no function is being compiled currently. */
778 if ((target_flags & (THUMB_FLAG_LEAF_BACKTRACE | THUMB_FLAG_BACKTRACE))
780 warning ("enabling backtrace support is only meaningful when compiling for the Thumb");
782 if (TARGET_ARM && TARGET_CALLEE_INTERWORKING)
783 warning ("enabling callee interworking support is only meaningful when compiling for the Thumb");
785 if (TARGET_ARM && TARGET_CALLER_INTERWORKING)
786 warning ("enabling caller interworking support is only meaningful when compiling for the Thumb");
788 /* If interworking is enabled then APCS-32 must be selected as well. */
789 if (TARGET_INTERWORK)
792 warning ("interworking forces APCS-32 to be used" );
793 target_flags |= ARM_FLAG_APCS_32;
796 if (TARGET_APCS_STACK && !TARGET_APCS_FRAME)
798 warning ("-mapcs-stack-check incompatible with -mno-apcs-frame");
799 target_flags |= ARM_FLAG_APCS_FRAME;
802 if (TARGET_POKE_FUNCTION_NAME)
803 target_flags |= ARM_FLAG_APCS_FRAME;
805 if (TARGET_APCS_REENT && flag_pic)
806 error ("-fpic and -mapcs-reent are incompatible");
808 if (TARGET_APCS_REENT)
809 warning ("APCS reentrant code not supported. Ignored");
811 /* If this target is normally configured to use APCS frames, warn if they
812 are turned off and debugging is turned on. */
814 && write_symbols != NO_DEBUG
815 && !TARGET_APCS_FRAME
816 && (TARGET_DEFAULT & ARM_FLAG_APCS_FRAME))
817 warning ("-g with -mno-apcs-frame may not give sensible debugging");
819 /* If stack checking is disabled, we can use r10 as the PIC register,
820 which keeps r9 available. */
822 arm_pic_register = TARGET_APCS_STACK ? 9 : 10;
824 if (TARGET_APCS_FLOAT)
825 warning ("passing floating point arguments in fp regs not yet supported");
827 /* Initialize boolean versions of the flags, for use in the arm.md file. */
828 arm_arch3m = (insn_flags & FL_ARCH3M) != 0;
829 arm_arch4 = (insn_flags & FL_ARCH4) != 0;
830 arm_arch5 = (insn_flags & FL_ARCH5) != 0;
831 arm_arch5e = (insn_flags & FL_ARCH5E) != 0;
832 arm_arch6 = (insn_flags & FL_ARCH6) != 0;
833 arm_arch_xscale = (insn_flags & FL_XSCALE) != 0;
834 arm_arch_cirrus = (insn_flags & FL_CIRRUS) != 0;
836 arm_ld_sched = (tune_flags & FL_LDSCHED) != 0;
837 arm_is_strong = (tune_flags & FL_STRONG) != 0;
838 thumb_code = (TARGET_ARM == 0);
839 arm_is_6_or_7 = (((tune_flags & (FL_MODE26 | FL_MODE32))
840 && !(tune_flags & FL_ARCH4))) != 0;
841 arm_tune_xscale = (tune_flags & FL_XSCALE) != 0;
842 arm_arch_iwmmxt = (insn_flags & FL_IWMMXT) != 0;
846 for (i = 0; i < ARRAY_SIZE (arm_all_abis); i++)
848 if (streq (arm_all_abis[i].name, target_abi_name))
850 arm_abi = arm_all_abis[i].abi_type;
854 if (i == ARRAY_SIZE (arm_all_abis))
855 error ("invalid ABI option: -mabi=%s", target_abi_name);
858 arm_abi = ARM_DEFAULT_ABI;
860 if (TARGET_IWMMXT && !ARM_DOUBLEWORD_ALIGN)
861 error ("iwmmxt requires an AAPCS compatible ABI for proper operation");
863 if (TARGET_IWMMXT_ABI && !TARGET_IWMMXT)
864 error ("iwmmxt abi requires an iwmmxt capable cpu");
866 arm_fp_model = ARM_FP_MODEL_UNKNOWN;
867 if (target_fpu_name == NULL && target_fpe_name != NULL)
869 if (streq (target_fpe_name, "2"))
870 target_fpu_name = "fpe2";
871 else if (streq (target_fpe_name, "3"))
872 target_fpu_name = "fpe3";
874 error ("invalid floating point emulation option: -mfpe=%s",
877 if (target_fpu_name != NULL)
879 /* The user specified a FPU. */
880 for (i = 0; i < ARRAY_SIZE (all_fpus); i++)
882 if (streq (all_fpus[i].name, target_fpu_name))
884 arm_fpu_arch = all_fpus[i].fpu;
885 arm_fpu_tune = arm_fpu_arch;
886 arm_fp_model = fp_model_for_fpu[arm_fpu_arch];
890 if (arm_fp_model == ARM_FP_MODEL_UNKNOWN)
891 error ("invalid floating point option: -mfpu=%s", target_fpu_name);
895 #ifdef FPUTYPE_DEFAULT
896 /* Use the default if it is specified for this platform. */
897 arm_fpu_arch = FPUTYPE_DEFAULT;
898 arm_fpu_tune = FPUTYPE_DEFAULT;
900 /* Pick one based on CPU type. */
901 /* ??? Some targets assume FPA is the default.
902 if ((insn_flags & FL_VFP) != 0)
903 arm_fpu_arch = FPUTYPE_VFP;
907 arm_fpu_arch = FPUTYPE_MAVERICK;
909 arm_fpu_arch = FPUTYPE_FPA_EMU2;
911 if (tune_flags & FL_CO_PROC && arm_fpu_arch == FPUTYPE_FPA_EMU2)
912 arm_fpu_tune = FPUTYPE_FPA;
914 arm_fpu_tune = arm_fpu_arch;
915 arm_fp_model = fp_model_for_fpu[arm_fpu_arch];
916 if (arm_fp_model == ARM_FP_MODEL_UNKNOWN)
920 if (target_float_abi_name != NULL)
922 /* The user specified a FP ABI. */
923 for (i = 0; i < ARRAY_SIZE (all_float_abis); i++)
925 if (streq (all_float_abis[i].name, target_float_abi_name))
927 arm_float_abi = all_float_abis[i].abi_type;
931 if (i == ARRAY_SIZE (all_float_abis))
932 error ("invalid floating point abi: -mfloat-abi=%s",
933 target_float_abi_name);
937 /* Use soft-float target flag. */
938 if (target_flags & ARM_FLAG_SOFT_FLOAT)
939 arm_float_abi = ARM_FLOAT_ABI_SOFT;
941 arm_float_abi = ARM_FLOAT_ABI_HARD;
944 if (arm_float_abi == ARM_FLOAT_ABI_SOFTFP)
945 sorry ("-mfloat-abi=softfp");
946 /* If soft-float is specified then don't use FPU. */
947 if (TARGET_SOFT_FLOAT)
948 arm_fpu_arch = FPUTYPE_NONE;
950 /* For arm2/3 there is no need to do any scheduling if there is only
951 a floating point emulator, or we are doing software floating-point. */
952 if ((TARGET_SOFT_FLOAT
953 || arm_fpu_tune == FPUTYPE_FPA_EMU2
954 || arm_fpu_tune == FPUTYPE_FPA_EMU3)
955 && (tune_flags & FL_MODE32) == 0)
956 flag_schedule_insns = flag_schedule_insns_after_reload = 0;
958 arm_prgmode = TARGET_APCS_32 ? PROG_MODE_PROG32 : PROG_MODE_PROG26;
960 /* Override the default structure alignment for AAPCS ABI. */
961 if (arm_abi == ARM_ABI_AAPCS)
962 arm_structure_size_boundary = 8;
964 if (structure_size_string != NULL)
966 int size = strtol (structure_size_string, NULL, 0);
968 if (size == 8 || size == 32
969 || (ARM_DOUBLEWORD_ALIGN && size == 64))
970 arm_structure_size_boundary = size;
972 warning ("structure size boundary can only be set to %s",
973 ARM_DOUBLEWORD_ALIGN ? "8, 32 or 64": "8 or 32");
976 if (arm_pic_register_string != NULL)
978 int pic_register = decode_reg_name (arm_pic_register_string);
981 warning ("-mpic-register= is useless without -fpic");
983 /* Prevent the user from choosing an obviously stupid PIC register. */
984 else if (pic_register < 0 || call_used_regs[pic_register]
985 || pic_register == HARD_FRAME_POINTER_REGNUM
986 || pic_register == STACK_POINTER_REGNUM
987 || pic_register >= PC_REGNUM)
988 error ("unable to use '%s' for PIC register", arm_pic_register_string);
990 arm_pic_register = pic_register;
993 if (TARGET_THUMB && flag_schedule_insns)
995 /* Don't warn since it's on by default in -O2. */
996 flag_schedule_insns = 0;
1001 /* There's some dispute as to whether this should be 1 or 2. However,
1002 experiments seem to show that in pathological cases a setting of
1003 1 degrades less severely than a setting of 2. This could change if
1004 other parts of the compiler change their behavior. */
1005 arm_constant_limit = 1;
1007 /* If optimizing for size, bump the number of instructions that we
1008 are prepared to conditionally execute (even on a StrongARM). */
1009 max_insns_skipped = 6;
1013 /* For processors with load scheduling, it never costs more than
1014 2 cycles to load a constant, and the load scheduler may well
1015 reduce that to 1. */
1016 if (tune_flags & FL_LDSCHED)
1017 arm_constant_limit = 1;
1019 /* On XScale the longer latency of a load makes it more difficult
1020 to achieve a good schedule, so it's faster to synthesize
1021 constants that can be done in two insns. */
1022 if (arm_tune_xscale)
1023 arm_constant_limit = 2;
1025 /* StrongARM has early execution of branches, so a sequence
1026 that is worth skipping is shorter. */
1028 max_insns_skipped = 3;
1031 /* Register global variables with the garbage collector. */
1032 arm_add_gc_roots ();
1036 arm_add_gc_roots (void)
1038 gcc_obstack_init(&minipool_obstack);
1039 minipool_startobj = (char *) obstack_alloc (&minipool_obstack, 0);
1042 /* A table of known ARM exception types.
1043 For use with the interrupt function attribute. */
1047 const char *const arg;
1048 const unsigned long return_value;
1052 static const isr_attribute_arg isr_attribute_args [] =
1054 { "IRQ", ARM_FT_ISR },
1055 { "irq", ARM_FT_ISR },
1056 { "FIQ", ARM_FT_FIQ },
1057 { "fiq", ARM_FT_FIQ },
1058 { "ABORT", ARM_FT_ISR },
1059 { "abort", ARM_FT_ISR },
1060 { "ABORT", ARM_FT_ISR },
1061 { "abort", ARM_FT_ISR },
1062 { "UNDEF", ARM_FT_EXCEPTION },
1063 { "undef", ARM_FT_EXCEPTION },
1064 { "SWI", ARM_FT_EXCEPTION },
1065 { "swi", ARM_FT_EXCEPTION },
1066 { NULL, ARM_FT_NORMAL }
1069 /* Returns the (interrupt) function type of the current
1070 function, or ARM_FT_UNKNOWN if the type cannot be determined. */
1072 static unsigned long
1073 arm_isr_value (tree argument)
1075 const isr_attribute_arg * ptr;
1078 /* No argument - default to IRQ. */
1079 if (argument == NULL_TREE)
1082 /* Get the value of the argument. */
1083 if (TREE_VALUE (argument) == NULL_TREE
1084 || TREE_CODE (TREE_VALUE (argument)) != STRING_CST)
1085 return ARM_FT_UNKNOWN;
1087 arg = TREE_STRING_POINTER (TREE_VALUE (argument));
1089 /* Check it against the list of known arguments. */
1090 for (ptr = isr_attribute_args; ptr->arg != NULL; ptr++)
1091 if (streq (arg, ptr->arg))
1092 return ptr->return_value;
1094 /* An unrecognized interrupt type. */
1095 return ARM_FT_UNKNOWN;
1098 /* Computes the type of the current function. */
1100 static unsigned long
1101 arm_compute_func_type (void)
1103 unsigned long type = ARM_FT_UNKNOWN;
1107 if (TREE_CODE (current_function_decl) != FUNCTION_DECL)
1110 /* Decide if the current function is volatile. Such functions
1111 never return, and many memory cycles can be saved by not storing
1112 register values that will never be needed again. This optimization
1113 was added to speed up context switching in a kernel application. */
1115 && current_function_nothrow
1116 && TREE_THIS_VOLATILE (current_function_decl))
1117 type |= ARM_FT_VOLATILE;
1119 if (current_function_needs_context)
1120 type |= ARM_FT_NESTED;
1122 attr = DECL_ATTRIBUTES (current_function_decl);
1124 a = lookup_attribute ("naked", attr);
1126 type |= ARM_FT_NAKED;
1128 if (cfun->machine->eh_epilogue_sp_ofs != NULL_RTX)
1129 type |= ARM_FT_EXCEPTION_HANDLER;
1132 a = lookup_attribute ("isr", attr);
1134 a = lookup_attribute ("interrupt", attr);
1137 type |= TARGET_INTERWORK ? ARM_FT_INTERWORKED : ARM_FT_NORMAL;
1139 type |= arm_isr_value (TREE_VALUE (a));
1145 /* Returns the type of the current function. */
1148 arm_current_func_type (void)
1150 if (ARM_FUNC_TYPE (cfun->machine->func_type) == ARM_FT_UNKNOWN)
1151 cfun->machine->func_type = arm_compute_func_type ();
1153 return cfun->machine->func_type;
1156 /* Return 1 if it is possible to return using a single instruction.
1157 If SIBLING is non-null, this is a test for a return before a sibling
1158 call. SIBLING is the call insn, so we can examine its register usage. */
1161 use_return_insn (int iscond, rtx sibling)
1164 unsigned int func_type;
1165 unsigned long saved_int_regs;
1166 unsigned HOST_WIDE_INT stack_adjust;
1167 arm_stack_offsets *offsets;
1169 /* Never use a return instruction before reload has run. */
1170 if (!reload_completed)
1173 func_type = arm_current_func_type ();
1175 /* Naked functions and volatile functions need special
1177 if (func_type & (ARM_FT_VOLATILE | ARM_FT_NAKED))
1180 /* So do interrupt functions that use the frame pointer. */
1181 if (IS_INTERRUPT (func_type) && frame_pointer_needed)
1184 offsets = arm_get_frame_offsets ();
1185 stack_adjust = offsets->outgoing_args - offsets->saved_regs;
1187 /* As do variadic functions. */
1188 if (current_function_pretend_args_size
1189 || cfun->machine->uses_anonymous_args
1190 /* Or if the function calls __builtin_eh_return () */
1191 || ARM_FUNC_TYPE (func_type) == ARM_FT_EXCEPTION_HANDLER
1192 /* Or if the function calls alloca */
1193 || current_function_calls_alloca
1194 /* Or if there is a stack adjustment. However, if the stack pointer
1195 is saved on the stack, we can use a pre-incrementing stack load. */
1196 || !(stack_adjust == 0 || (frame_pointer_needed && stack_adjust == 4)))
1199 saved_int_regs = arm_compute_save_reg_mask ();
1201 /* Unfortunately, the insn
1203 ldmib sp, {..., sp, ...}
1205 triggers a bug on most SA-110 based devices, such that the stack
1206 pointer won't be correctly restored if the instruction takes a
1207 page fault. We work around this problem by popping r3 along with
1208 the other registers, since that is never slower than executing
1209 another instruction.
1211 We test for !arm_arch5 here, because code for any architecture
1212 less than this could potentially be run on one of the buggy
1214 if (stack_adjust == 4 && !arm_arch5)
1216 /* Validate that r3 is a call-clobbered register (always true in
1217 the default abi) ... */
1218 if (!call_used_regs[3])
1221 /* ... that it isn't being used for a return value (always true
1222 until we implement return-in-regs), or for a tail-call
1226 if (GET_CODE (sibling) != CALL_INSN)
1229 if (find_regno_fusage (sibling, USE, 3))
1233 /* ... and that there are no call-saved registers in r0-r2
1234 (always true in the default ABI). */
1235 if (saved_int_regs & 0x7)
1239 /* Can't be done if interworking with Thumb, and any registers have been
1241 if (TARGET_INTERWORK && saved_int_regs != 0)
1244 /* On StrongARM, conditional returns are expensive if they aren't
1245 taken and multiple registers have been stacked. */
1246 if (iscond && arm_is_strong)
1248 /* Conditional return when just the LR is stored is a simple
1249 conditional-load instruction, that's not expensive. */
1250 if (saved_int_regs != 0 && saved_int_regs != (1 << LR_REGNUM))
1253 if (flag_pic && regs_ever_live[PIC_OFFSET_TABLE_REGNUM])
1257 /* If there are saved registers but the LR isn't saved, then we need
1258 two instructions for the return. */
1259 if (saved_int_regs && !(saved_int_regs & (1 << LR_REGNUM)))
1262 /* Can't be done if any of the FPA regs are pushed,
1263 since this also requires an insn. */
1264 if (TARGET_HARD_FLOAT && TARGET_FPA)
1265 for (regno = FIRST_FPA_REGNUM; regno <= LAST_FPA_REGNUM; regno++)
1266 if (regs_ever_live[regno] && !call_used_regs[regno])
1269 /* Likewise VFP regs. */
1270 if (TARGET_HARD_FLOAT && TARGET_VFP)
1271 for (regno = FIRST_VFP_REGNUM; regno <= LAST_VFP_REGNUM; regno++)
1272 if (regs_ever_live[regno] && !call_used_regs[regno])
1275 if (TARGET_REALLY_IWMMXT)
1276 for (regno = FIRST_IWMMXT_REGNUM; regno <= LAST_IWMMXT_REGNUM; regno++)
1277 if (regs_ever_live[regno] && ! call_used_regs [regno])
1283 /* Return TRUE if int I is a valid immediate ARM constant. */
1286 const_ok_for_arm (HOST_WIDE_INT i)
1288 unsigned HOST_WIDE_INT mask = ~(unsigned HOST_WIDE_INT)0xFF;
1290 /* For machines with >32 bit HOST_WIDE_INT, the bits above bit 31 must
1291 be all zero, or all one. */
1292 if ((i & ~(unsigned HOST_WIDE_INT) 0xffffffff) != 0
1293 && ((i & ~(unsigned HOST_WIDE_INT) 0xffffffff)
1294 != ((~(unsigned HOST_WIDE_INT) 0)
1295 & ~(unsigned HOST_WIDE_INT) 0xffffffff)))
1298 /* Fast return for 0 and powers of 2 */
1299 if ((i & (i - 1)) == 0)
1304 if ((i & mask & (unsigned HOST_WIDE_INT) 0xffffffff) == 0)
1307 (mask << 2) | ((mask & (unsigned HOST_WIDE_INT) 0xffffffff)
1308 >> (32 - 2)) | ~(unsigned HOST_WIDE_INT) 0xffffffff;
1310 while (mask != ~(unsigned HOST_WIDE_INT) 0xFF);
1315 /* Return true if I is a valid constant for the operation CODE. */
1317 const_ok_for_op (HOST_WIDE_INT i, enum rtx_code code)
1319 if (const_ok_for_arm (i))
1325 return const_ok_for_arm (ARM_SIGN_EXTEND (-i));
1327 case MINUS: /* Should only occur with (MINUS I reg) => rsb */
1333 return const_ok_for_arm (ARM_SIGN_EXTEND (~i));
1340 /* Emit a sequence of insns to handle a large constant.
1341 CODE is the code of the operation required, it can be any of SET, PLUS,
1342 IOR, AND, XOR, MINUS;
1343 MODE is the mode in which the operation is being performed;
1344 VAL is the integer to operate on;
1345 SOURCE is the other operand (a register, or a null-pointer for SET);
1346 SUBTARGETS means it is safe to create scratch registers if that will
1347 either produce a simpler sequence, or we will want to cse the values.
1348 Return value is the number of insns emitted. */
1351 arm_split_constant (enum rtx_code code, enum machine_mode mode, rtx insn,
1352 HOST_WIDE_INT val, rtx target, rtx source, int subtargets)
1356 if (insn && GET_CODE (PATTERN (insn)) == COND_EXEC)
1357 cond = COND_EXEC_TEST (PATTERN (insn));
1361 if (subtargets || code == SET
1362 || (GET_CODE (target) == REG && GET_CODE (source) == REG
1363 && REGNO (target) != REGNO (source)))
1365 /* After arm_reorg has been called, we can't fix up expensive
1366 constants by pushing them into memory so we must synthesize
1367 them in-line, regardless of the cost. This is only likely to
1368 be more costly on chips that have load delay slots and we are
1369 compiling without running the scheduler (so no splitting
1370 occurred before the final instruction emission).
1372 Ref: gcc -O1 -mcpu=strongarm gcc.c-torture/compile/980506-2.c
1374 if (!after_arm_reorg
1376 && (arm_gen_constant (code, mode, NULL_RTX, val, target, source,
1378 > arm_constant_limit + (code != SET)))
1382 /* Currently SET is the only monadic value for CODE, all
1383 the rest are diadic. */
1384 emit_insn (gen_rtx_SET (VOIDmode, target, GEN_INT (val)));
1389 rtx temp = subtargets ? gen_reg_rtx (mode) : target;
1391 emit_insn (gen_rtx_SET (VOIDmode, temp, GEN_INT (val)));
1392 /* For MINUS, the value is subtracted from, since we never
1393 have subtraction of a constant. */
1395 emit_insn (gen_rtx_SET (VOIDmode, target,
1396 gen_rtx_MINUS (mode, temp, source)));
1398 emit_insn (gen_rtx_SET (VOIDmode, target,
1399 gen_rtx_fmt_ee (code, mode, source, temp)));
1405 return arm_gen_constant (code, mode, cond, val, target, source, subtargets,
1410 count_insns_for_constant (HOST_WIDE_INT remainder, int i)
1412 HOST_WIDE_INT temp1;
1420 if (remainder & (3 << (i - 2)))
1425 temp1 = remainder & ((0x0ff << end)
1426 | ((i < end) ? (0xff >> (32 - end)) : 0));
1427 remainder &= ~temp1;
1432 } while (remainder);
1436 /* Emit an instruction with the indicated PATTERN. If COND is
1437 non-NULL, conditionalize the execution of the instruction on COND
1441 emit_constant_insn (rtx cond, rtx pattern)
1444 pattern = gen_rtx_COND_EXEC (VOIDmode, copy_rtx (cond), pattern);
1445 emit_insn (pattern);
1448 /* As above, but extra parameter GENERATE which, if clear, suppresses
1452 arm_gen_constant (enum rtx_code code, enum machine_mode mode, rtx cond,
1453 HOST_WIDE_INT val, rtx target, rtx source, int subtargets,
1458 int can_negate_initial = 0;
1461 int num_bits_set = 0;
1462 int set_sign_bit_copies = 0;
1463 int clear_sign_bit_copies = 0;
1464 int clear_zero_bit_copies = 0;
1465 int set_zero_bit_copies = 0;
1467 unsigned HOST_WIDE_INT temp1, temp2;
1468 unsigned HOST_WIDE_INT remainder = val & 0xffffffff;
1470 /* Find out which operations are safe for a given CODE. Also do a quick
1471 check for degenerate cases; these can occur when DImode operations
1483 can_negate_initial = 1;
1487 if (remainder == 0xffffffff)
1490 emit_constant_insn (cond,
1491 gen_rtx_SET (VOIDmode, target,
1492 GEN_INT (ARM_SIGN_EXTEND (val))));
1497 if (reload_completed && rtx_equal_p (target, source))
1500 emit_constant_insn (cond,
1501 gen_rtx_SET (VOIDmode, target, source));
1510 emit_constant_insn (cond,
1511 gen_rtx_SET (VOIDmode, target, const0_rtx));
1514 if (remainder == 0xffffffff)
1516 if (reload_completed && rtx_equal_p (target, source))
1519 emit_constant_insn (cond,
1520 gen_rtx_SET (VOIDmode, target, source));
1529 if (reload_completed && rtx_equal_p (target, source))
1532 emit_constant_insn (cond,
1533 gen_rtx_SET (VOIDmode, target, source));
1536 if (remainder == 0xffffffff)
1539 emit_constant_insn (cond,
1540 gen_rtx_SET (VOIDmode, target,
1541 gen_rtx_NOT (mode, source)));
1545 /* We don't know how to handle this yet below. */
1549 /* We treat MINUS as (val - source), since (source - val) is always
1550 passed as (source + (-val)). */
1554 emit_constant_insn (cond,
1555 gen_rtx_SET (VOIDmode, target,
1556 gen_rtx_NEG (mode, source)));
1559 if (const_ok_for_arm (val))
1562 emit_constant_insn (cond,
1563 gen_rtx_SET (VOIDmode, target,
1564 gen_rtx_MINUS (mode, GEN_INT (val),
1576 /* If we can do it in one insn get out quickly. */
1577 if (const_ok_for_arm (val)
1578 || (can_negate_initial && const_ok_for_arm (-val))
1579 || (can_invert && const_ok_for_arm (~val)))
1582 emit_constant_insn (cond,
1583 gen_rtx_SET (VOIDmode, target,
1585 ? gen_rtx_fmt_ee (code, mode, source,
1591 /* Calculate a few attributes that may be useful for specific
1593 for (i = 31; i >= 0; i--)
1595 if ((remainder & (1 << i)) == 0)
1596 clear_sign_bit_copies++;
1601 for (i = 31; i >= 0; i--)
1603 if ((remainder & (1 << i)) != 0)
1604 set_sign_bit_copies++;
1609 for (i = 0; i <= 31; i++)
1611 if ((remainder & (1 << i)) == 0)
1612 clear_zero_bit_copies++;
1617 for (i = 0; i <= 31; i++)
1619 if ((remainder & (1 << i)) != 0)
1620 set_zero_bit_copies++;
1628 /* See if we can do this by sign_extending a constant that is known
1629 to be negative. This is a good, way of doing it, since the shift
1630 may well merge into a subsequent insn. */
1631 if (set_sign_bit_copies > 1)
1633 if (const_ok_for_arm
1634 (temp1 = ARM_SIGN_EXTEND (remainder
1635 << (set_sign_bit_copies - 1))))
1639 rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
1640 emit_constant_insn (cond,
1641 gen_rtx_SET (VOIDmode, new_src,
1643 emit_constant_insn (cond,
1644 gen_ashrsi3 (target, new_src,
1645 GEN_INT (set_sign_bit_copies - 1)));
1649 /* For an inverted constant, we will need to set the low bits,
1650 these will be shifted out of harm's way. */
1651 temp1 |= (1 << (set_sign_bit_copies - 1)) - 1;
1652 if (const_ok_for_arm (~temp1))
1656 rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
1657 emit_constant_insn (cond,
1658 gen_rtx_SET (VOIDmode, new_src,
1660 emit_constant_insn (cond,
1661 gen_ashrsi3 (target, new_src,
1662 GEN_INT (set_sign_bit_copies - 1)));
1668 /* See if we can generate this by setting the bottom (or the top)
1669 16 bits, and then shifting these into the other half of the
1670 word. We only look for the simplest cases, to do more would cost
1671 too much. Be careful, however, not to generate this when the
1672 alternative would take fewer insns. */
1673 if (val & 0xffff0000)
1675 temp1 = remainder & 0xffff0000;
1676 temp2 = remainder & 0x0000ffff;
1678 /* Overlaps outside this range are best done using other methods. */
1679 for (i = 9; i < 24; i++)
1681 if ((((temp2 | (temp2 << i)) & 0xffffffff) == remainder)
1682 && !const_ok_for_arm (temp2))
1684 rtx new_src = (subtargets
1685 ? (generate ? gen_reg_rtx (mode) : NULL_RTX)
1687 insns = arm_gen_constant (code, mode, cond, temp2, new_src,
1688 source, subtargets, generate);
1696 gen_rtx_ASHIFT (mode, source,
1703 /* Don't duplicate cases already considered. */
1704 for (i = 17; i < 24; i++)
1706 if (((temp1 | (temp1 >> i)) == remainder)
1707 && !const_ok_for_arm (temp1))
1709 rtx new_src = (subtargets
1710 ? (generate ? gen_reg_rtx (mode) : NULL_RTX)
1712 insns = arm_gen_constant (code, mode, cond, temp1, new_src,
1713 source, subtargets, generate);
1718 gen_rtx_SET (VOIDmode, target,
1721 gen_rtx_LSHIFTRT (mode, source,
1732 /* If we have IOR or XOR, and the constant can be loaded in a
1733 single instruction, and we can find a temporary to put it in,
1734 then this can be done in two instructions instead of 3-4. */
1736 /* TARGET can't be NULL if SUBTARGETS is 0 */
1737 || (reload_completed && !reg_mentioned_p (target, source)))
1739 if (const_ok_for_arm (ARM_SIGN_EXTEND (~val)))
1743 rtx sub = subtargets ? gen_reg_rtx (mode) : target;
1745 emit_constant_insn (cond,
1746 gen_rtx_SET (VOIDmode, sub,
1748 emit_constant_insn (cond,
1749 gen_rtx_SET (VOIDmode, target,
1750 gen_rtx_fmt_ee (code, mode,
1760 if (set_sign_bit_copies > 8
1761 && (val & (-1 << (32 - set_sign_bit_copies))) == val)
1765 rtx sub = subtargets ? gen_reg_rtx (mode) : target;
1766 rtx shift = GEN_INT (set_sign_bit_copies);
1770 gen_rtx_SET (VOIDmode, sub,
1772 gen_rtx_ASHIFT (mode,
1777 gen_rtx_SET (VOIDmode, target,
1779 gen_rtx_LSHIFTRT (mode, sub,
1785 if (set_zero_bit_copies > 8
1786 && (remainder & ((1 << set_zero_bit_copies) - 1)) == remainder)
1790 rtx sub = subtargets ? gen_reg_rtx (mode) : target;
1791 rtx shift = GEN_INT (set_zero_bit_copies);
1795 gen_rtx_SET (VOIDmode, sub,
1797 gen_rtx_LSHIFTRT (mode,
1802 gen_rtx_SET (VOIDmode, target,
1804 gen_rtx_ASHIFT (mode, sub,
1810 if (const_ok_for_arm (temp1 = ARM_SIGN_EXTEND (~val)))
1814 rtx sub = subtargets ? gen_reg_rtx (mode) : target;
1815 emit_constant_insn (cond,
1816 gen_rtx_SET (VOIDmode, sub,
1817 gen_rtx_NOT (mode, source)));
1820 sub = gen_reg_rtx (mode);
1821 emit_constant_insn (cond,
1822 gen_rtx_SET (VOIDmode, sub,
1823 gen_rtx_AND (mode, source,
1825 emit_constant_insn (cond,
1826 gen_rtx_SET (VOIDmode, target,
1827 gen_rtx_NOT (mode, sub)));
1834 /* See if two shifts will do 2 or more insn's worth of work. */
1835 if (clear_sign_bit_copies >= 16 && clear_sign_bit_copies < 24)
1837 HOST_WIDE_INT shift_mask = ((0xffffffff
1838 << (32 - clear_sign_bit_copies))
1841 if ((remainder | shift_mask) != 0xffffffff)
1845 rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
1846 insns = arm_gen_constant (AND, mode, cond,
1847 remainder | shift_mask,
1848 new_src, source, subtargets, 1);
1853 rtx targ = subtargets ? NULL_RTX : target;
1854 insns = arm_gen_constant (AND, mode, cond,
1855 remainder | shift_mask,
1856 targ, source, subtargets, 0);
1862 rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
1863 rtx shift = GEN_INT (clear_sign_bit_copies);
1865 emit_insn (gen_ashlsi3 (new_src, source, shift));
1866 emit_insn (gen_lshrsi3 (target, new_src, shift));
1872 if (clear_zero_bit_copies >= 16 && clear_zero_bit_copies < 24)
1874 HOST_WIDE_INT shift_mask = (1 << clear_zero_bit_copies) - 1;
1876 if ((remainder | shift_mask) != 0xffffffff)
1880 rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
1882 insns = arm_gen_constant (AND, mode, cond,
1883 remainder | shift_mask,
1884 new_src, source, subtargets, 1);
1889 rtx targ = subtargets ? NULL_RTX : target;
1891 insns = arm_gen_constant (AND, mode, cond,
1892 remainder | shift_mask,
1893 targ, source, subtargets, 0);
1899 rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
1900 rtx shift = GEN_INT (clear_zero_bit_copies);
1902 emit_insn (gen_lshrsi3 (new_src, source, shift));
1903 emit_insn (gen_ashlsi3 (target, new_src, shift));
1915 for (i = 0; i < 32; i++)
1916 if (remainder & (1 << i))
1919 if (code == AND || (can_invert && num_bits_set > 16))
1920 remainder = (~remainder) & 0xffffffff;
1921 else if (code == PLUS && num_bits_set > 16)
1922 remainder = (-remainder) & 0xffffffff;
1929 /* Now try and find a way of doing the job in either two or three
1931 We start by looking for the largest block of zeros that are aligned on
1932 a 2-bit boundary, we then fill up the temps, wrapping around to the
1933 top of the word when we drop off the bottom.
1934 In the worst case this code should produce no more than four insns. */
1937 int best_consecutive_zeros = 0;
1939 for (i = 0; i < 32; i += 2)
1941 int consecutive_zeros = 0;
1943 if (!(remainder & (3 << i)))
1945 while ((i < 32) && !(remainder & (3 << i)))
1947 consecutive_zeros += 2;
1950 if (consecutive_zeros > best_consecutive_zeros)
1952 best_consecutive_zeros = consecutive_zeros;
1953 best_start = i - consecutive_zeros;
1959 /* So long as it won't require any more insns to do so, it's
1960 desirable to emit a small constant (in bits 0...9) in the last
1961 insn. This way there is more chance that it can be combined with
1962 a later addressing insn to form a pre-indexed load or store
1963 operation. Consider:
1965 *((volatile int *)0xe0000100) = 1;
1966 *((volatile int *)0xe0000110) = 2;
1968 We want this to wind up as:
1972 str rB, [rA, #0x100]
1974 str rB, [rA, #0x110]
1976 rather than having to synthesize both large constants from scratch.
1978 Therefore, we calculate how many insns would be required to emit
1979 the constant starting from `best_start', and also starting from
1980 zero (ie with bit 31 first to be output). If `best_start' doesn't
1981 yield a shorter sequence, we may as well use zero. */
1983 && ((((unsigned HOST_WIDE_INT) 1) << best_start) < remainder)
1984 && (count_insns_for_constant (remainder, 0) <=
1985 count_insns_for_constant (remainder, best_start)))
1988 /* Now start emitting the insns. */
1996 if (remainder & (3 << (i - 2)))
2001 temp1 = remainder & ((0x0ff << end)
2002 | ((i < end) ? (0xff >> (32 - end)) : 0));
2003 remainder &= ~temp1;
2007 rtx new_src, temp1_rtx;
2009 if (code == SET || code == MINUS)
2011 new_src = (subtargets ? gen_reg_rtx (mode) : target);
2012 if (can_invert && code != MINUS)
2017 if (remainder && subtargets)
2018 new_src = gen_reg_rtx (mode);
2023 else if (can_negate)
2027 temp1 = trunc_int_for_mode (temp1, mode);
2028 temp1_rtx = GEN_INT (temp1);
2032 else if (code == MINUS)
2033 temp1_rtx = gen_rtx_MINUS (mode, temp1_rtx, source);
2035 temp1_rtx = gen_rtx_fmt_ee (code, mode, source, temp1_rtx);
2037 emit_constant_insn (cond,
2038 gen_rtx_SET (VOIDmode, new_src,
2048 else if (code == MINUS)
2062 /* Canonicalize a comparison so that we are more likely to recognize it.
2063 This can be done for a few constant compares, where we can make the
2064 immediate value easier to load. */
2067 arm_canonicalize_comparison (enum rtx_code code, rtx * op1)
2069 unsigned HOST_WIDE_INT i = INTVAL (*op1);
2079 if (i != ((((unsigned HOST_WIDE_INT) 1) << (HOST_BITS_PER_WIDE_INT - 1)) - 1)
2080 && (const_ok_for_arm (i + 1) || const_ok_for_arm (-(i + 1))))
2082 *op1 = GEN_INT (i + 1);
2083 return code == GT ? GE : LT;
2089 if (i != (((unsigned HOST_WIDE_INT) 1) << (HOST_BITS_PER_WIDE_INT - 1))
2090 && (const_ok_for_arm (i - 1) || const_ok_for_arm (-(i - 1))))
2092 *op1 = GEN_INT (i - 1);
2093 return code == GE ? GT : LE;
2099 if (i != ~((unsigned HOST_WIDE_INT) 0)
2100 && (const_ok_for_arm (i + 1) || const_ok_for_arm (-(i + 1))))
2102 *op1 = GEN_INT (i + 1);
2103 return code == GTU ? GEU : LTU;
2110 && (const_ok_for_arm (i - 1) || const_ok_for_arm (-(i - 1))))
2112 *op1 = GEN_INT (i - 1);
2113 return code == GEU ? GTU : LEU;
2125 /* Define how to find the value returned by a function. */
2127 rtx arm_function_value(tree type, tree func ATTRIBUTE_UNUSED)
2129 enum machine_mode mode;
2130 int unsignedp ATTRIBUTE_UNUSED;
2131 rtx r ATTRIBUTE_UNUSED;
2134 mode = TYPE_MODE (type);
2135 /* Promote integer types. */
2136 if (INTEGRAL_TYPE_P (type))
2137 PROMOTE_FUNCTION_MODE (mode, unsignedp, type);
2138 return LIBCALL_VALUE(mode);
2142 /* Decide whether a type should be returned in memory (true)
2143 or in a register (false). This is called by the macro
2144 RETURN_IN_MEMORY. */
2146 arm_return_in_memory (tree type)
2150 if (!AGGREGATE_TYPE_P (type))
2151 /* All simple types are returned in registers. */
2154 size = int_size_in_bytes (type);
2156 if (arm_abi != ARM_ABI_APCS)
2158 /* ATPCS and later return aggregate types in memory only if they are
2159 larger than a word (or are variable size). */
2160 return (size < 0 || size > UNITS_PER_WORD);
2163 /* For the arm-wince targets we choose to be compatible with Microsoft's
2164 ARM and Thumb compilers, which always return aggregates in memory. */
2166 /* All structures/unions bigger than one word are returned in memory.
2167 Also catch the case where int_size_in_bytes returns -1. In this case
2168 the aggregate is either huge or of variable size, and in either case
2169 we will want to return it via memory and not in a register. */
2170 if (size < 0 || size > UNITS_PER_WORD)
2173 if (TREE_CODE (type) == RECORD_TYPE)
2177 /* For a struct the APCS says that we only return in a register
2178 if the type is 'integer like' and every addressable element
2179 has an offset of zero. For practical purposes this means
2180 that the structure can have at most one non bit-field element
2181 and that this element must be the first one in the structure. */
2183 /* Find the first field, ignoring non FIELD_DECL things which will
2184 have been created by C++. */
2185 for (field = TYPE_FIELDS (type);
2186 field && TREE_CODE (field) != FIELD_DECL;
2187 field = TREE_CHAIN (field))
2191 return 0; /* An empty structure. Allowed by an extension to ANSI C. */
2193 /* Check that the first field is valid for returning in a register. */
2195 /* ... Floats are not allowed */
2196 if (FLOAT_TYPE_P (TREE_TYPE (field)))
2199 /* ... Aggregates that are not themselves valid for returning in
2200 a register are not allowed. */
2201 if (RETURN_IN_MEMORY (TREE_TYPE (field)))
2204 /* Now check the remaining fields, if any. Only bitfields are allowed,
2205 since they are not addressable. */
2206 for (field = TREE_CHAIN (field);
2208 field = TREE_CHAIN (field))
2210 if (TREE_CODE (field) != FIELD_DECL)
2213 if (!DECL_BIT_FIELD_TYPE (field))
2220 if (TREE_CODE (type) == UNION_TYPE)
2224 /* Unions can be returned in registers if every element is
2225 integral, or can be returned in an integer register. */
2226 for (field = TYPE_FIELDS (type);
2228 field = TREE_CHAIN (field))
2230 if (TREE_CODE (field) != FIELD_DECL)
2233 if (FLOAT_TYPE_P (TREE_TYPE (field)))
2236 if (RETURN_IN_MEMORY (TREE_TYPE (field)))
2242 #endif /* not ARM_WINCE */
2244 /* Return all other types in memory. */
2248 /* Indicate whether or not words of a double are in big-endian order. */
2251 arm_float_words_big_endian (void)
2253 if (TARGET_MAVERICK)
2256 /* For FPA, float words are always big-endian. For VFP, floats words
2257 follow the memory system mode. */
2265 return (TARGET_BIG_END ? 1 : 0);
2270 /* Initialize a variable CUM of type CUMULATIVE_ARGS
2271 for a call to a function whose data type is FNTYPE.
2272 For a library call, FNTYPE is NULL. */
2274 arm_init_cumulative_args (CUMULATIVE_ARGS *pcum, tree fntype,
2275 rtx libname ATTRIBUTE_UNUSED,
2276 tree fndecl ATTRIBUTE_UNUSED)
2278 /* On the ARM, the offset starts at 0. */
2279 pcum->nregs = ((fntype && aggregate_value_p (TREE_TYPE (fntype), fntype)) ? 1 : 0);
2280 pcum->iwmmxt_nregs = 0;
2281 pcum->can_split = true;
2283 pcum->call_cookie = CALL_NORMAL;
2285 if (TARGET_LONG_CALLS)
2286 pcum->call_cookie = CALL_LONG;
2288 /* Check for long call/short call attributes. The attributes
2289 override any command line option. */
2292 if (lookup_attribute ("short_call", TYPE_ATTRIBUTES (fntype)))
2293 pcum->call_cookie = CALL_SHORT;
2294 else if (lookup_attribute ("long_call", TYPE_ATTRIBUTES (fntype)))
2295 pcum->call_cookie = CALL_LONG;
2298 /* Varargs vectors are treated the same as long long.
2299 named_count avoids having to change the way arm handles 'named' */
2300 pcum->named_count = 0;
2303 if (TARGET_REALLY_IWMMXT && fntype)
2307 for (fn_arg = TYPE_ARG_TYPES (fntype);
2309 fn_arg = TREE_CHAIN (fn_arg))
2310 pcum->named_count += 1;
2312 if (! pcum->named_count)
2313 pcum->named_count = INT_MAX;
2318 /* Return true if mode/type need doubleword alignment. */
2320 arm_needs_doubleword_align (enum machine_mode mode, tree type)
2322 return (GET_MODE_ALIGNMENT (mode) > PARM_BOUNDARY
2323 || (type && TYPE_ALIGN (type) > PARM_BOUNDARY));
2327 /* Determine where to put an argument to a function.
2328 Value is zero to push the argument on the stack,
2329 or a hard register in which to store the argument.
2331 MODE is the argument's machine mode.
2332 TYPE is the data type of the argument (as a tree).
2333 This is null for libcalls where that information may
2335 CUM is a variable of type CUMULATIVE_ARGS which gives info about
2336 the preceding args and about the function being called.
2337 NAMED is nonzero if this argument is a named parameter
2338 (otherwise it is an extra parameter matching an ellipsis). */
2341 arm_function_arg (CUMULATIVE_ARGS *pcum, enum machine_mode mode,
2342 tree type, int named)
2346 /* Varargs vectors are treated the same as long long.
2347 named_count avoids having to change the way arm handles 'named' */
2348 if (TARGET_IWMMXT_ABI
2349 && VECTOR_MODE_SUPPORTED_P (mode)
2350 && pcum->named_count > pcum->nargs + 1)
2352 if (pcum->iwmmxt_nregs <= 9)
2353 return gen_rtx_REG (mode, pcum->iwmmxt_nregs + FIRST_IWMMXT_REGNUM);
2356 pcum->can_split = false;
2361 /* Put doubleword aligned quantities in even register pairs. */
2363 && ARM_DOUBLEWORD_ALIGN
2364 && arm_needs_doubleword_align (mode, type))
2367 if (mode == VOIDmode)
2368 /* Compute operand 2 of the call insn. */
2369 return GEN_INT (pcum->call_cookie);
2371 /* Only allow splitting an arg between regs and memory if all preceding
2372 args were allocated to regs. For args passed by reference we only count
2373 the reference pointer. */
2374 if (pcum->can_split)
2377 nregs = ARM_NUM_REGS2 (mode, type);
2379 if (!named || pcum->nregs + nregs > NUM_ARG_REGS)
2382 return gen_rtx_REG (mode, pcum->nregs);
2385 /* Variable sized types are passed by reference. This is a GCC
2386 extension to the ARM ABI. */
2389 arm_function_arg_pass_by_reference (CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED,
2390 enum machine_mode mode ATTRIBUTE_UNUSED,
2391 tree type, int named ATTRIBUTE_UNUSED)
2393 return type && TREE_CODE (TYPE_SIZE (type)) != INTEGER_CST;
2396 /* Implement va_arg. */
2399 arm_va_arg (tree valist, tree type)
2403 /* Variable sized types are passed by reference. */
2404 if (TREE_CODE (TYPE_SIZE (type)) != INTEGER_CST)
2406 rtx addr = std_expand_builtin_va_arg (valist, build_pointer_type (type));
2407 return gen_rtx_MEM (ptr_mode, force_reg (Pmode, addr));
2410 align = FUNCTION_ARG_BOUNDARY (TYPE_MODE (type), type);
2411 if (align > PARM_BOUNDARY)
2416 /* Maintain 64-bit alignment of the valist pointer by
2417 constructing: valist = ((valist + (8 - 1)) & -8). */
2418 mask = build_int_2 (- (align / BITS_PER_UNIT), -1);
2419 t = build_int_2 ((align / BITS_PER_UNIT) - 1, 0);
2420 t = build (PLUS_EXPR, TREE_TYPE (valist), valist, t);
2421 t = build (BIT_AND_EXPR, TREE_TYPE (t), t, mask);
2422 t = build (MODIFY_EXPR, TREE_TYPE (valist), valist, t);
2423 TREE_SIDE_EFFECTS (t) = 1;
2424 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
2426 /* This is to stop the combine pass optimizing
2427 away the alignment adjustment. */
2428 mark_reg_pointer (arg_pointer_rtx, PARM_BOUNDARY);
2431 return std_expand_builtin_va_arg (valist, type);
2434 /* Encode the current state of the #pragma [no_]long_calls. */
2437 OFF, /* No #pramgma [no_]long_calls is in effect. */
2438 LONG, /* #pragma long_calls is in effect. */
2439 SHORT /* #pragma no_long_calls is in effect. */
2442 static arm_pragma_enum arm_pragma_long_calls = OFF;
2445 arm_pr_long_calls (struct cpp_reader * pfile ATTRIBUTE_UNUSED)
2447 arm_pragma_long_calls = LONG;
2451 arm_pr_no_long_calls (struct cpp_reader * pfile ATTRIBUTE_UNUSED)
2453 arm_pragma_long_calls = SHORT;
2457 arm_pr_long_calls_off (struct cpp_reader * pfile ATTRIBUTE_UNUSED)
2459 arm_pragma_long_calls = OFF;
2462 /* Table of machine attributes. */
2463 const struct attribute_spec arm_attribute_table[] =
2465 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
2466 /* Function calls made to this symbol must be done indirectly, because
2467 it may lie outside of the 26 bit addressing range of a normal function
2469 { "long_call", 0, 0, false, true, true, NULL },
2470 /* Whereas these functions are always known to reside within the 26 bit
2471 addressing range. */
2472 { "short_call", 0, 0, false, true, true, NULL },
2473 /* Interrupt Service Routines have special prologue and epilogue requirements. */
2474 { "isr", 0, 1, false, false, false, arm_handle_isr_attribute },
2475 { "interrupt", 0, 1, false, false, false, arm_handle_isr_attribute },
2476 { "naked", 0, 0, true, false, false, arm_handle_fndecl_attribute },
2478 /* ARM/PE has three new attributes:
2480 dllexport - for exporting a function/variable that will live in a dll
2481 dllimport - for importing a function/variable from a dll
2483 Microsoft allows multiple declspecs in one __declspec, separating
2484 them with spaces. We do NOT support this. Instead, use __declspec
2487 { "dllimport", 0, 0, true, false, false, NULL },
2488 { "dllexport", 0, 0, true, false, false, NULL },
2489 { "interfacearm", 0, 0, true, false, false, arm_handle_fndecl_attribute },
2491 { NULL, 0, 0, false, false, false, NULL }
2494 /* Handle an attribute requiring a FUNCTION_DECL;
2495 arguments as in struct attribute_spec.handler. */
2497 arm_handle_fndecl_attribute (tree *node, tree name, tree args ATTRIBUTE_UNUSED,
2498 int flags ATTRIBUTE_UNUSED, bool *no_add_attrs)
2500 if (TREE_CODE (*node) != FUNCTION_DECL)
2502 warning ("`%s' attribute only applies to functions",
2503 IDENTIFIER_POINTER (name));
2504 *no_add_attrs = true;
2510 /* Handle an "interrupt" or "isr" attribute;
2511 arguments as in struct attribute_spec.handler. */
2513 arm_handle_isr_attribute (tree *node, tree name, tree args, int flags,
2518 if (TREE_CODE (*node) != FUNCTION_DECL)
2520 warning ("`%s' attribute only applies to functions",
2521 IDENTIFIER_POINTER (name));
2522 *no_add_attrs = true;
2524 /* FIXME: the argument if any is checked for type attributes;
2525 should it be checked for decl ones? */
2529 if (TREE_CODE (*node) == FUNCTION_TYPE
2530 || TREE_CODE (*node) == METHOD_TYPE)
2532 if (arm_isr_value (args) == ARM_FT_UNKNOWN)
2534 warning ("`%s' attribute ignored", IDENTIFIER_POINTER (name));
2535 *no_add_attrs = true;
2538 else if (TREE_CODE (*node) == POINTER_TYPE
2539 && (TREE_CODE (TREE_TYPE (*node)) == FUNCTION_TYPE
2540 || TREE_CODE (TREE_TYPE (*node)) == METHOD_TYPE)
2541 && arm_isr_value (args) != ARM_FT_UNKNOWN)
2543 *node = build_type_copy (*node);
2544 TREE_TYPE (*node) = build_type_attribute_variant
2546 tree_cons (name, args, TYPE_ATTRIBUTES (TREE_TYPE (*node))));
2547 *no_add_attrs = true;
2551 /* Possibly pass this attribute on from the type to a decl. */
2552 if (flags & ((int) ATTR_FLAG_DECL_NEXT
2553 | (int) ATTR_FLAG_FUNCTION_NEXT
2554 | (int) ATTR_FLAG_ARRAY_NEXT))
2556 *no_add_attrs = true;
2557 return tree_cons (name, args, NULL_TREE);
2561 warning ("`%s' attribute ignored", IDENTIFIER_POINTER (name));
2569 /* Return 0 if the attributes for two types are incompatible, 1 if they
2570 are compatible, and 2 if they are nearly compatible (which causes a
2571 warning to be generated). */
2573 arm_comp_type_attributes (tree type1, tree type2)
2577 /* Check for mismatch of non-default calling convention. */
2578 if (TREE_CODE (type1) != FUNCTION_TYPE)
2581 /* Check for mismatched call attributes. */
2582 l1 = lookup_attribute ("long_call", TYPE_ATTRIBUTES (type1)) != NULL;
2583 l2 = lookup_attribute ("long_call", TYPE_ATTRIBUTES (type2)) != NULL;
2584 s1 = lookup_attribute ("short_call", TYPE_ATTRIBUTES (type1)) != NULL;
2585 s2 = lookup_attribute ("short_call", TYPE_ATTRIBUTES (type2)) != NULL;
2587 /* Only bother to check if an attribute is defined. */
2588 if (l1 | l2 | s1 | s2)
2590 /* If one type has an attribute, the other must have the same attribute. */
2591 if ((l1 != l2) || (s1 != s2))
2594 /* Disallow mixed attributes. */
2595 if ((l1 & s2) || (l2 & s1))
2599 /* Check for mismatched ISR attribute. */
2600 l1 = lookup_attribute ("isr", TYPE_ATTRIBUTES (type1)) != NULL;
2602 l1 = lookup_attribute ("interrupt", TYPE_ATTRIBUTES (type1)) != NULL;
2603 l2 = lookup_attribute ("isr", TYPE_ATTRIBUTES (type2)) != NULL;
2605 l1 = lookup_attribute ("interrupt", TYPE_ATTRIBUTES (type2)) != NULL;
2612 /* Encode long_call or short_call attribute by prefixing
2613 symbol name in DECL with a special character FLAG. */
2615 arm_encode_call_attribute (tree decl, int flag)
2617 const char * str = XSTR (XEXP (DECL_RTL (decl), 0), 0);
2618 int len = strlen (str);
2621 /* Do not allow weak functions to be treated as short call. */
2622 if (DECL_WEAK (decl) && flag == SHORT_CALL_FLAG_CHAR)
2625 newstr = alloca (len + 2);
2627 strcpy (newstr + 1, str);
2629 newstr = (char *) ggc_alloc_string (newstr, len + 1);
2630 XSTR (XEXP (DECL_RTL (decl), 0), 0) = newstr;
2633 /* Assigns default attributes to newly defined type. This is used to
2634 set short_call/long_call attributes for function types of
2635 functions defined inside corresponding #pragma scopes. */
2637 arm_set_default_type_attributes (tree type)
2639 /* Add __attribute__ ((long_call)) to all functions, when
2640 inside #pragma long_calls or __attribute__ ((short_call)),
2641 when inside #pragma no_long_calls. */
2642 if (TREE_CODE (type) == FUNCTION_TYPE || TREE_CODE (type) == METHOD_TYPE)
2644 tree type_attr_list, attr_name;
2645 type_attr_list = TYPE_ATTRIBUTES (type);
2647 if (arm_pragma_long_calls == LONG)
2648 attr_name = get_identifier ("long_call");
2649 else if (arm_pragma_long_calls == SHORT)
2650 attr_name = get_identifier ("short_call");
2654 type_attr_list = tree_cons (attr_name, NULL_TREE, type_attr_list);
2655 TYPE_ATTRIBUTES (type) = type_attr_list;
2659 /* Return 1 if the operand is a SYMBOL_REF for a function known to be
2660 defined within the current compilation unit. If this cannot be
2661 determined, then 0 is returned. */
2663 current_file_function_operand (rtx sym_ref)
2665 /* This is a bit of a fib. A function will have a short call flag
2666 applied to its name if it has the short call attribute, or it has
2667 already been defined within the current compilation unit. */
2668 if (ENCODED_SHORT_CALL_ATTR_P (XSTR (sym_ref, 0)))
2671 /* The current function is always defined within the current compilation
2672 unit. if it s a weak definition however, then this may not be the real
2673 definition of the function, and so we have to say no. */
2674 if (sym_ref == XEXP (DECL_RTL (current_function_decl), 0)
2675 && !DECL_WEAK (current_function_decl))
2678 /* We cannot make the determination - default to returning 0. */
2682 /* Return nonzero if a 32 bit "long_call" should be generated for
2683 this call. We generate a long_call if the function:
2685 a. has an __attribute__((long call))
2686 or b. is within the scope of a #pragma long_calls
2687 or c. the -mlong-calls command line switch has been specified
2689 However we do not generate a long call if the function:
2691 d. has an __attribute__ ((short_call))
2692 or e. is inside the scope of a #pragma no_long_calls
2693 or f. has an __attribute__ ((section))
2694 or g. is defined within the current compilation unit.
2696 This function will be called by C fragments contained in the machine
2697 description file. CALL_REF and CALL_COOKIE correspond to the matched
2698 rtl operands. CALL_SYMBOL is used to distinguish between
2699 two different callers of the function. It is set to 1 in the
2700 "call_symbol" and "call_symbol_value" patterns and to 0 in the "call"
2701 and "call_value" patterns. This is because of the difference in the
2702 SYM_REFs passed by these patterns. */
2704 arm_is_longcall_p (rtx sym_ref, int call_cookie, int call_symbol)
2708 if (GET_CODE (sym_ref) != MEM)
2711 sym_ref = XEXP (sym_ref, 0);
2714 if (GET_CODE (sym_ref) != SYMBOL_REF)
2717 if (call_cookie & CALL_SHORT)
2720 if (TARGET_LONG_CALLS && flag_function_sections)
2723 if (current_file_function_operand (sym_ref))
2726 return (call_cookie & CALL_LONG)
2727 || ENCODED_LONG_CALL_ATTR_P (XSTR (sym_ref, 0))
2728 || TARGET_LONG_CALLS;
2731 /* Return nonzero if it is ok to make a tail-call to DECL. */
2733 arm_function_ok_for_sibcall (tree decl, tree exp ATTRIBUTE_UNUSED)
2735 int call_type = TARGET_LONG_CALLS ? CALL_LONG : CALL_NORMAL;
2737 if (cfun->machine->sibcall_blocked)
2740 /* Never tailcall something for which we have no decl, or if we
2741 are in Thumb mode. */
2742 if (decl == NULL || TARGET_THUMB)
2745 /* Get the calling method. */
2746 if (lookup_attribute ("short_call", TYPE_ATTRIBUTES (TREE_TYPE (decl))))
2747 call_type = CALL_SHORT;
2748 else if (lookup_attribute ("long_call", TYPE_ATTRIBUTES (TREE_TYPE (decl))))
2749 call_type = CALL_LONG;
2751 /* Cannot tail-call to long calls, since these are out of range of
2752 a branch instruction. However, if not compiling PIC, we know
2753 we can reach the symbol if it is in this compilation unit. */
2754 if (call_type == CALL_LONG && (flag_pic || !TREE_ASM_WRITTEN (decl)))
2757 /* If we are interworking and the function is not declared static
2758 then we can't tail-call it unless we know that it exists in this
2759 compilation unit (since it might be a Thumb routine). */
2760 if (TARGET_INTERWORK && TREE_PUBLIC (decl) && !TREE_ASM_WRITTEN (decl))
2763 /* Never tailcall from an ISR routine - it needs a special exit sequence. */
2764 if (IS_INTERRUPT (arm_current_func_type ()))
2767 /* Everything else is ok. */
2772 /* Addressing mode support functions. */
2774 /* Return nonzero if X is a legitimate immediate operand when compiling
2777 legitimate_pic_operand_p (rtx x)
2781 && (GET_CODE (x) == SYMBOL_REF
2782 || (GET_CODE (x) == CONST
2783 && GET_CODE (XEXP (x, 0)) == PLUS
2784 && GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF)))
2791 legitimize_pic_address (rtx orig, enum machine_mode mode, rtx reg)
2793 if (GET_CODE (orig) == SYMBOL_REF
2794 || GET_CODE (orig) == LABEL_REF)
2796 #ifndef AOF_ASSEMBLER
2797 rtx pic_ref, address;
2807 reg = gen_reg_rtx (Pmode);
2812 #ifdef AOF_ASSEMBLER
2813 /* The AOF assembler can generate relocations for these directly, and
2814 understands that the PIC register has to be added into the offset. */
2815 insn = emit_insn (gen_pic_load_addr_based (reg, orig));
2818 address = gen_reg_rtx (Pmode);
2823 emit_insn (gen_pic_load_addr_arm (address, orig));
2825 emit_insn (gen_pic_load_addr_thumb (address, orig));
2827 if ((GET_CODE (orig) == LABEL_REF
2828 || (GET_CODE (orig) == SYMBOL_REF &&
2829 SYMBOL_REF_LOCAL_P (orig)))
2831 pic_ref = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, address);
2834 pic_ref = gen_rtx_MEM (Pmode,
2835 gen_rtx_PLUS (Pmode, pic_offset_table_rtx,
2837 RTX_UNCHANGING_P (pic_ref) = 1;
2840 insn = emit_move_insn (reg, pic_ref);
2842 current_function_uses_pic_offset_table = 1;
2843 /* Put a REG_EQUAL note on this insn, so that it can be optimized
2845 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_EQUAL, orig,
2849 else if (GET_CODE (orig) == CONST)
2853 if (GET_CODE (XEXP (orig, 0)) == PLUS
2854 && XEXP (XEXP (orig, 0), 0) == pic_offset_table_rtx)
2862 reg = gen_reg_rtx (Pmode);
2865 if (GET_CODE (XEXP (orig, 0)) == PLUS)
2867 base = legitimize_pic_address (XEXP (XEXP (orig, 0), 0), Pmode, reg);
2868 offset = legitimize_pic_address (XEXP (XEXP (orig, 0), 1), Pmode,
2869 base == reg ? 0 : reg);
2874 if (GET_CODE (offset) == CONST_INT)
2876 /* The base register doesn't really matter, we only want to
2877 test the index for the appropriate mode. */
2878 if (!arm_legitimate_index_p (mode, offset, SET, 0))
2880 if (!no_new_pseudos)
2881 offset = force_reg (Pmode, offset);
2886 if (GET_CODE (offset) == CONST_INT)
2887 return plus_constant (base, INTVAL (offset));
2890 if (GET_MODE_SIZE (mode) > 4
2891 && (GET_MODE_CLASS (mode) == MODE_INT
2892 || TARGET_SOFT_FLOAT))
2894 emit_insn (gen_addsi3 (reg, base, offset));
2898 return gen_rtx_PLUS (Pmode, base, offset);
2904 /* Generate code to load the PIC register. PROLOGUE is true if
2905 called from arm_expand_prologue (in which case we want the
2906 generated insns at the start of the function); false if called
2907 by an exception receiver that needs the PIC register reloaded
2908 (in which case the insns are just dumped at the current location). */
2910 arm_finalize_pic (int prologue ATTRIBUTE_UNUSED)
2912 #ifndef AOF_ASSEMBLER
2913 rtx l1, pic_tmp, pic_tmp2, seq, pic_rtx;
2914 rtx global_offset_table;
2916 if (current_function_uses_pic_offset_table == 0 || TARGET_SINGLE_PIC_BASE)
2923 l1 = gen_label_rtx ();
2925 global_offset_table = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
2926 /* On the ARM the PC register contains 'dot + 8' at the time of the
2927 addition, on the Thumb it is 'dot + 4'. */
2928 pic_tmp = plus_constant (gen_rtx_LABEL_REF (Pmode, l1), TARGET_ARM ? 8 : 4);
2930 pic_tmp2 = gen_rtx_CONST (VOIDmode,
2931 gen_rtx_PLUS (Pmode, global_offset_table, pc_rtx));
2933 pic_tmp2 = gen_rtx_CONST (VOIDmode, global_offset_table);
2935 pic_rtx = gen_rtx_CONST (Pmode, gen_rtx_MINUS (Pmode, pic_tmp2, pic_tmp));
2939 emit_insn (gen_pic_load_addr_arm (pic_offset_table_rtx, pic_rtx));
2940 emit_insn (gen_pic_add_dot_plus_eight (pic_offset_table_rtx, l1));
2944 emit_insn (gen_pic_load_addr_thumb (pic_offset_table_rtx, pic_rtx));
2945 emit_insn (gen_pic_add_dot_plus_four (pic_offset_table_rtx, l1));
2951 emit_insn_after (seq, get_insns ());
2955 /* Need to emit this whether or not we obey regdecls,
2956 since setjmp/longjmp can cause life info to screw up. */
2957 emit_insn (gen_rtx_USE (VOIDmode, pic_offset_table_rtx));
2958 #endif /* AOF_ASSEMBLER */
2961 /* Return nonzero if X is valid as an ARM state addressing register. */
2963 arm_address_register_rtx_p (rtx x, int strict_p)
2967 if (GET_CODE (x) != REG)
2973 return ARM_REGNO_OK_FOR_BASE_P (regno);
2975 return (regno <= LAST_ARM_REGNUM
2976 || regno >= FIRST_PSEUDO_REGISTER
2977 || regno == FRAME_POINTER_REGNUM
2978 || regno == ARG_POINTER_REGNUM);
2981 /* Return nonzero if X is a valid ARM state address operand. */
2983 arm_legitimate_address_p (enum machine_mode mode, rtx x, RTX_CODE outer,
2986 if (arm_address_register_rtx_p (x, strict_p))
2989 else if (GET_CODE (x) == POST_INC || GET_CODE (x) == PRE_DEC)
2990 return arm_address_register_rtx_p (XEXP (x, 0), strict_p);
2992 else if ((GET_CODE (x) == POST_MODIFY || GET_CODE (x) == PRE_MODIFY)
2993 && GET_MODE_SIZE (mode) <= 4
2994 && arm_address_register_rtx_p (XEXP (x, 0), strict_p)
2995 && GET_CODE (XEXP (x, 1)) == PLUS
2996 && rtx_equal_p (XEXP (XEXP (x, 1), 0), XEXP (x, 0)))
2997 return arm_legitimate_index_p (mode, XEXP (XEXP (x, 1), 1), outer,
3000 /* After reload constants split into minipools will have addresses
3001 from a LABEL_REF. */
3002 else if (reload_completed
3003 && (GET_CODE (x) == LABEL_REF
3004 || (GET_CODE (x) == CONST
3005 && GET_CODE (XEXP (x, 0)) == PLUS
3006 && GET_CODE (XEXP (XEXP (x, 0), 0)) == LABEL_REF
3007 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT)))
3010 else if (mode == TImode)
3013 else if (mode == DImode || (TARGET_SOFT_FLOAT && mode == DFmode))
3015 if (GET_CODE (x) == PLUS
3016 && arm_address_register_rtx_p (XEXP (x, 0), strict_p)
3017 && GET_CODE (XEXP (x, 1)) == CONST_INT)
3019 HOST_WIDE_INT val = INTVAL (XEXP (x, 1));
3021 if (val == 4 || val == -4 || val == -8)
3026 else if (TARGET_HARD_FLOAT && TARGET_VFP && mode == DFmode)
3028 if (GET_CODE (x) == PLUS
3029 && arm_address_register_rtx_p (XEXP (x, 0), strict_p)
3030 && GET_CODE (XEXP (x, 1)) == CONST_INT)
3032 HOST_WIDE_INT val = INTVAL (XEXP (x, 1));
3034 /* ??? valid arm offsets are a subset of VFP offsets.
3035 For now only allow this subset. Proper fix is to add an
3036 additional memory constraint for arm address modes.
3037 Alternatively allow full vfp addressing and let
3038 output_move_double fix it up with a sub-optimal sequence. */
3039 if (val == 4 || val == -4 || val == -8)
3044 else if (GET_CODE (x) == PLUS)
3046 rtx xop0 = XEXP (x, 0);
3047 rtx xop1 = XEXP (x, 1);
3049 return ((arm_address_register_rtx_p (xop0, strict_p)
3050 && arm_legitimate_index_p (mode, xop1, outer, strict_p))
3051 || (arm_address_register_rtx_p (xop1, strict_p)
3052 && arm_legitimate_index_p (mode, xop0, outer, strict_p)));
3056 /* Reload currently can't handle MINUS, so disable this for now */
3057 else if (GET_CODE (x) == MINUS)
3059 rtx xop0 = XEXP (x, 0);
3060 rtx xop1 = XEXP (x, 1);
3062 return (arm_address_register_rtx_p (xop0, strict_p)
3063 && arm_legitimate_index_p (mode, xop1, outer, strict_p));
3067 else if (GET_MODE_CLASS (mode) != MODE_FLOAT
3068 && GET_CODE (x) == SYMBOL_REF
3069 && CONSTANT_POOL_ADDRESS_P (x)
3071 && symbol_mentioned_p (get_pool_constant (x))))
3074 else if ((GET_CODE (x) == PRE_INC || GET_CODE (x) == POST_DEC)
3075 && (GET_MODE_SIZE (mode) <= 4)
3076 && arm_address_register_rtx_p (XEXP (x, 0), strict_p))
3082 /* Return nonzero if INDEX is valid for an address index operand in
3085 arm_legitimate_index_p (enum machine_mode mode, rtx index, RTX_CODE outer,
3088 HOST_WIDE_INT range;
3089 enum rtx_code code = GET_CODE (index);
3091 /* Standard coprocessor addressing modes. */
3092 if (TARGET_HARD_FLOAT
3093 && (TARGET_FPA || TARGET_MAVERICK)
3094 && (GET_MODE_CLASS (mode) == MODE_FLOAT
3095 || (TARGET_MAVERICK && mode == DImode)))
3096 return (code == CONST_INT && INTVAL (index) < 1024
3097 && INTVAL (index) > -1024
3098 && (INTVAL (index) & 3) == 0);
3100 if (arm_address_register_rtx_p (index, strict_p)
3101 && GET_MODE_SIZE (mode) <= 4)
3104 if (TARGET_REALLY_IWMMXT && VALID_IWMMXT_REG_MODE (mode))
3105 return (code == CONST_INT
3106 && INTVAL (index) < 1024
3107 && INTVAL (index) > -1024
3108 && (INTVAL (index) & 3) == 0);
3110 if (GET_MODE_SIZE (mode) <= 4
3113 || (mode == QImode && outer == SIGN_EXTEND))))
3117 rtx xiop0 = XEXP (index, 0);
3118 rtx xiop1 = XEXP (index, 1);
3120 return ((arm_address_register_rtx_p (xiop0, strict_p)
3121 && power_of_two_operand (xiop1, SImode))
3122 || (arm_address_register_rtx_p (xiop1, strict_p)
3123 && power_of_two_operand (xiop0, SImode)));
3125 else if (code == LSHIFTRT || code == ASHIFTRT
3126 || code == ASHIFT || code == ROTATERT)
3128 rtx op = XEXP (index, 1);
3130 return (arm_address_register_rtx_p (XEXP (index, 0), strict_p)
3131 && GET_CODE (op) == CONST_INT
3133 && INTVAL (op) <= 31);
3137 /* For ARM v4 we may be doing a sign-extend operation during the
3141 if (mode == HImode || (outer == SIGN_EXTEND && mode == QImode))
3147 range = (mode == HImode) ? 4095 : 4096;
3149 return (code == CONST_INT
3150 && INTVAL (index) < range
3151 && INTVAL (index) > -range);
3154 /* Return nonzero if X is valid as a Thumb state base register. */
3156 thumb_base_register_rtx_p (rtx x, enum machine_mode mode, int strict_p)
3160 if (GET_CODE (x) != REG)
3166 return THUMB_REGNO_MODE_OK_FOR_BASE_P (regno, mode);
3168 return (regno <= LAST_LO_REGNUM
3169 || regno > LAST_VIRTUAL_REGISTER
3170 || regno == FRAME_POINTER_REGNUM
3171 || (GET_MODE_SIZE (mode) >= 4
3172 && (regno == STACK_POINTER_REGNUM
3173 || regno >= FIRST_PSEUDO_REGISTER
3174 || x == hard_frame_pointer_rtx
3175 || x == arg_pointer_rtx)));
3178 /* Return nonzero if x is a legitimate index register. This is the case
3179 for any base register that can access a QImode object. */
3181 thumb_index_register_rtx_p (rtx x, int strict_p)
3183 return thumb_base_register_rtx_p (x, QImode, strict_p);
3186 /* Return nonzero if x is a legitimate Thumb-state address.
3188 The AP may be eliminated to either the SP or the FP, so we use the
3189 least common denominator, e.g. SImode, and offsets from 0 to 64.
3191 ??? Verify whether the above is the right approach.
3193 ??? Also, the FP may be eliminated to the SP, so perhaps that
3194 needs special handling also.
3196 ??? Look at how the mips16 port solves this problem. It probably uses
3197 better ways to solve some of these problems.
3199 Although it is not incorrect, we don't accept QImode and HImode
3200 addresses based on the frame pointer or arg pointer until the
3201 reload pass starts. This is so that eliminating such addresses
3202 into stack based ones won't produce impossible code. */
3204 thumb_legitimate_address_p (enum machine_mode mode, rtx x, int strict_p)
3206 /* ??? Not clear if this is right. Experiment. */
3207 if (GET_MODE_SIZE (mode) < 4
3208 && !(reload_in_progress || reload_completed)
3209 && (reg_mentioned_p (frame_pointer_rtx, x)
3210 || reg_mentioned_p (arg_pointer_rtx, x)
3211 || reg_mentioned_p (virtual_incoming_args_rtx, x)
3212 || reg_mentioned_p (virtual_outgoing_args_rtx, x)
3213 || reg_mentioned_p (virtual_stack_dynamic_rtx, x)
3214 || reg_mentioned_p (virtual_stack_vars_rtx, x)))
3217 /* Accept any base register. SP only in SImode or larger. */
3218 else if (thumb_base_register_rtx_p (x, mode, strict_p))
3221 /* This is PC relative data before arm_reorg runs. */
3222 else if (GET_MODE_SIZE (mode) >= 4 && CONSTANT_P (x)
3223 && GET_CODE (x) == SYMBOL_REF
3224 && CONSTANT_POOL_ADDRESS_P (x) && ! flag_pic)
3227 /* This is PC relative data after arm_reorg runs. */
3228 else if (GET_MODE_SIZE (mode) >= 4 && reload_completed
3229 && (GET_CODE (x) == LABEL_REF
3230 || (GET_CODE (x) == CONST
3231 && GET_CODE (XEXP (x, 0)) == PLUS
3232 && GET_CODE (XEXP (XEXP (x, 0), 0)) == LABEL_REF
3233 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT)))
3236 /* Post-inc indexing only supported for SImode and larger. */
3237 else if (GET_CODE (x) == POST_INC && GET_MODE_SIZE (mode) >= 4
3238 && thumb_index_register_rtx_p (XEXP (x, 0), strict_p))
3241 else if (GET_CODE (x) == PLUS)
3243 /* REG+REG address can be any two index registers. */
3244 /* We disallow FRAME+REG addressing since we know that FRAME
3245 will be replaced with STACK, and SP relative addressing only
3246 permits SP+OFFSET. */
3247 if (GET_MODE_SIZE (mode) <= 4
3248 && XEXP (x, 0) != frame_pointer_rtx
3249 && XEXP (x, 1) != frame_pointer_rtx
3250 && thumb_index_register_rtx_p (XEXP (x, 0), strict_p)
3251 && thumb_index_register_rtx_p (XEXP (x, 1), strict_p))
3254 /* REG+const has 5-7 bit offset for non-SP registers. */
3255 else if ((thumb_index_register_rtx_p (XEXP (x, 0), strict_p)
3256 || XEXP (x, 0) == arg_pointer_rtx)
3257 && GET_CODE (XEXP (x, 1)) == CONST_INT
3258 && thumb_legitimate_offset_p (mode, INTVAL (XEXP (x, 1))))
3261 /* REG+const has 10 bit offset for SP, but only SImode and
3262 larger is supported. */
3263 /* ??? Should probably check for DI/DFmode overflow here
3264 just like GO_IF_LEGITIMATE_OFFSET does. */
3265 else if (GET_CODE (XEXP (x, 0)) == REG
3266 && REGNO (XEXP (x, 0)) == STACK_POINTER_REGNUM
3267 && GET_MODE_SIZE (mode) >= 4
3268 && GET_CODE (XEXP (x, 1)) == CONST_INT
3269 && INTVAL (XEXP (x, 1)) >= 0
3270 && INTVAL (XEXP (x, 1)) + GET_MODE_SIZE (mode) <= 1024
3271 && (INTVAL (XEXP (x, 1)) & 3) == 0)
3274 else if (GET_CODE (XEXP (x, 0)) == REG
3275 && REGNO (XEXP (x, 0)) == FRAME_POINTER_REGNUM
3276 && GET_MODE_SIZE (mode) >= 4
3277 && GET_CODE (XEXP (x, 1)) == CONST_INT
3278 && (INTVAL (XEXP (x, 1)) & 3) == 0)
3282 else if (GET_MODE_CLASS (mode) != MODE_FLOAT
3283 && GET_MODE_SIZE (mode) == 4
3284 && GET_CODE (x) == SYMBOL_REF
3285 && CONSTANT_POOL_ADDRESS_P (x)
3287 && symbol_mentioned_p (get_pool_constant (x))))
3293 /* Return nonzero if VAL can be used as an offset in a Thumb-state address
3294 instruction of mode MODE. */
3296 thumb_legitimate_offset_p (enum machine_mode mode, HOST_WIDE_INT val)
3298 switch (GET_MODE_SIZE (mode))
3301 return val >= 0 && val < 32;
3304 return val >= 0 && val < 64 && (val & 1) == 0;
3308 && (val + GET_MODE_SIZE (mode)) <= 128
3313 /* Try machine-dependent ways of modifying an illegitimate address
3314 to be legitimate. If we find one, return the new, valid address. */
3316 arm_legitimize_address (rtx x, rtx orig_x, enum machine_mode mode)
3318 if (GET_CODE (x) == PLUS)
3320 rtx xop0 = XEXP (x, 0);
3321 rtx xop1 = XEXP (x, 1);
3323 if (CONSTANT_P (xop0) && !symbol_mentioned_p (xop0))
3324 xop0 = force_reg (SImode, xop0);
3326 if (CONSTANT_P (xop1) && !symbol_mentioned_p (xop1))
3327 xop1 = force_reg (SImode, xop1);
3329 if (ARM_BASE_REGISTER_RTX_P (xop0)
3330 && GET_CODE (xop1) == CONST_INT)
3332 HOST_WIDE_INT n, low_n;
3336 /* VFP addressing modes actually allow greater offsets, but for
3337 now we just stick with the lowest common denominator. */
3339 || ((TARGET_SOFT_FLOAT || TARGET_VFP) && mode == DFmode))
3351 low_n = ((mode) == TImode ? 0
3352 : n >= 0 ? (n & 0xfff) : -((-n) & 0xfff));
3356 base_reg = gen_reg_rtx (SImode);
3357 val = force_operand (gen_rtx_PLUS (SImode, xop0,
3358 GEN_INT (n)), NULL_RTX);
3359 emit_move_insn (base_reg, val);
3360 x = (low_n == 0 ? base_reg
3361 : gen_rtx_PLUS (SImode, base_reg, GEN_INT (low_n)));
3363 else if (xop0 != XEXP (x, 0) || xop1 != XEXP (x, 1))
3364 x = gen_rtx_PLUS (SImode, xop0, xop1);
3367 /* XXX We don't allow MINUS any more -- see comment in
3368 arm_legitimate_address_p (). */
3369 else if (GET_CODE (x) == MINUS)
3371 rtx xop0 = XEXP (x, 0);
3372 rtx xop1 = XEXP (x, 1);
3374 if (CONSTANT_P (xop0))
3375 xop0 = force_reg (SImode, xop0);
3377 if (CONSTANT_P (xop1) && ! symbol_mentioned_p (xop1))
3378 xop1 = force_reg (SImode, xop1);
3380 if (xop0 != XEXP (x, 0) || xop1 != XEXP (x, 1))
3381 x = gen_rtx_MINUS (SImode, xop0, xop1);
3386 /* We need to find and carefully transform any SYMBOL and LABEL
3387 references; so go back to the original address expression. */
3388 rtx new_x = legitimize_pic_address (orig_x, mode, NULL_RTX);
3390 if (new_x != orig_x)
3398 /* Try machine-dependent ways of modifying an illegitimate Thumb address
3399 to be legitimate. If we find one, return the new, valid address. */
3401 thumb_legitimize_address (rtx x, rtx orig_x, enum machine_mode mode)
3403 if (GET_CODE (x) == PLUS
3404 && GET_CODE (XEXP (x, 1)) == CONST_INT
3405 && (INTVAL (XEXP (x, 1)) >= 32 * GET_MODE_SIZE (mode)
3406 || INTVAL (XEXP (x, 1)) < 0))
3408 rtx xop0 = XEXP (x, 0);
3409 rtx xop1 = XEXP (x, 1);
3410 HOST_WIDE_INT offset = INTVAL (xop1);
3412 /* Try and fold the offset into a biasing of the base register and
3413 then offsetting that. Don't do this when optimizing for space
3414 since it can cause too many CSEs. */
3415 if (optimize_size && offset >= 0
3416 && offset < 256 + 31 * GET_MODE_SIZE (mode))
3418 HOST_WIDE_INT delta;
3421 delta = offset - (256 - GET_MODE_SIZE (mode));
3422 else if (offset < 32 * GET_MODE_SIZE (mode) + 8)
3423 delta = 31 * GET_MODE_SIZE (mode);
3425 delta = offset & (~31 * GET_MODE_SIZE (mode));
3427 xop0 = force_operand (plus_constant (xop0, offset - delta),
3429 x = plus_constant (xop0, delta);
3431 else if (offset < 0 && offset > -256)
3432 /* Small negative offsets are best done with a subtract before the
3433 dereference, forcing these into a register normally takes two
3435 x = force_operand (x, NULL_RTX);
3438 /* For the remaining cases, force the constant into a register. */
3439 xop1 = force_reg (SImode, xop1);
3440 x = gen_rtx_PLUS (SImode, xop0, xop1);
3443 else if (GET_CODE (x) == PLUS
3444 && s_register_operand (XEXP (x, 1), SImode)
3445 && !s_register_operand (XEXP (x, 0), SImode))
3447 rtx xop0 = force_operand (XEXP (x, 0), NULL_RTX);
3449 x = gen_rtx_PLUS (SImode, xop0, XEXP (x, 1));
3454 /* We need to find and carefully transform any SYMBOL and LABEL
3455 references; so go back to the original address expression. */
3456 rtx new_x = legitimize_pic_address (orig_x, mode, NULL_RTX);
3458 if (new_x != orig_x)
3467 #define REG_OR_SUBREG_REG(X) \
3468 (GET_CODE (X) == REG \
3469 || (GET_CODE (X) == SUBREG && GET_CODE (SUBREG_REG (X)) == REG))
3471 #define REG_OR_SUBREG_RTX(X) \
3472 (GET_CODE (X) == REG ? (X) : SUBREG_REG (X))
3474 #ifndef COSTS_N_INSNS
3475 #define COSTS_N_INSNS(N) ((N) * 4 - 2)
3478 thumb_rtx_costs (rtx x, enum rtx_code code, enum rtx_code outer)
3480 enum machine_mode mode = GET_MODE (x);
3493 return COSTS_N_INSNS (1);
3496 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
3499 unsigned HOST_WIDE_INT i = INTVAL (XEXP (x, 1));
3506 return COSTS_N_INSNS (2) + cycles;
3508 return COSTS_N_INSNS (1) + 16;
3511 return (COSTS_N_INSNS (1)
3512 + 4 * ((GET_CODE (SET_SRC (x)) == MEM)
3513 + GET_CODE (SET_DEST (x)) == MEM));
3518 if ((unsigned HOST_WIDE_INT) INTVAL (x) < 256)
3520 if (thumb_shiftable_const (INTVAL (x)))
3521 return COSTS_N_INSNS (2);
3522 return COSTS_N_INSNS (3);
3524 else if ((outer == PLUS || outer == COMPARE)
3525 && INTVAL (x) < 256 && INTVAL (x) > -256)
3527 else if (outer == AND
3528 && INTVAL (x) < 256 && INTVAL (x) >= -256)
3529 return COSTS_N_INSNS (1);
3530 else if (outer == ASHIFT || outer == ASHIFTRT
3531 || outer == LSHIFTRT)
3533 return COSTS_N_INSNS (2);
3539 return COSTS_N_INSNS (3);
3558 /* XXX another guess. */
3559 /* Memory costs quite a lot for the first word, but subsequent words
3560 load at the equivalent of a single insn each. */
3561 return (10 + 4 * ((GET_MODE_SIZE (mode) - 1) / UNITS_PER_WORD)
3562 + ((GET_CODE (x) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (x))
3567 if (GET_CODE (XEXP (x, 1)) == PC || GET_CODE (XEXP (x, 2)) == PC)
3572 /* XXX still guessing. */
3573 switch (GET_MODE (XEXP (x, 0)))
3576 return (1 + (mode == DImode ? 4 : 0)
3577 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0));
3580 return (4 + (mode == DImode ? 4 : 0)
3581 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0));
3584 return (1 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0));
3596 /* Worker routine for arm_rtx_costs. */
3598 arm_rtx_costs_1 (rtx x, enum rtx_code code, enum rtx_code outer)
3600 enum machine_mode mode = GET_MODE (x);
3601 enum rtx_code subcode;
3607 /* Memory costs quite a lot for the first word, but subsequent words
3608 load at the equivalent of a single insn each. */
3609 return (10 + 4 * ((GET_MODE_SIZE (mode) - 1) / UNITS_PER_WORD)
3610 + (GET_CODE (x) == SYMBOL_REF
3611 && CONSTANT_POOL_ADDRESS_P (x) ? 4 : 0));
3617 return optimize_size ? COSTS_N_INSNS (2) : 100;
3620 if (mode == SImode && GET_CODE (XEXP (x, 1)) == REG)
3627 case ASHIFT: case LSHIFTRT: case ASHIFTRT:
3629 return (8 + (GET_CODE (XEXP (x, 1)) == CONST_INT ? 0 : 8)
3630 + ((GET_CODE (XEXP (x, 0)) == REG
3631 || (GET_CODE (XEXP (x, 0)) == SUBREG
3632 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == REG))
3634 return (1 + ((GET_CODE (XEXP (x, 0)) == REG
3635 || (GET_CODE (XEXP (x, 0)) == SUBREG
3636 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == REG))
3638 + ((GET_CODE (XEXP (x, 1)) == REG
3639 || (GET_CODE (XEXP (x, 1)) == SUBREG
3640 && GET_CODE (SUBREG_REG (XEXP (x, 1))) == REG)
3641 || (GET_CODE (XEXP (x, 1)) == CONST_INT))
3646 return (4 + (REG_OR_SUBREG_REG (XEXP (x, 1)) ? 0 : 8)
3647 + ((REG_OR_SUBREG_REG (XEXP (x, 0))
3648 || (GET_CODE (XEXP (x, 0)) == CONST_INT
3649 && const_ok_for_arm (INTVAL (XEXP (x, 0)))))
3652 if (GET_MODE_CLASS (mode) == MODE_FLOAT)
3653 return (2 + ((REG_OR_SUBREG_REG (XEXP (x, 1))
3654 || (GET_CODE (XEXP (x, 1)) == CONST_DOUBLE
3655 && arm_const_double_rtx (XEXP (x, 1))))
3657 + ((REG_OR_SUBREG_REG (XEXP (x, 0))
3658 || (GET_CODE (XEXP (x, 0)) == CONST_DOUBLE
3659 && arm_const_double_rtx (XEXP (x, 0))))
3662 if (((GET_CODE (XEXP (x, 0)) == CONST_INT
3663 && const_ok_for_arm (INTVAL (XEXP (x, 0)))
3664 && REG_OR_SUBREG_REG (XEXP (x, 1))))
3665 || (((subcode = GET_CODE (XEXP (x, 1))) == ASHIFT
3666 || subcode == ASHIFTRT || subcode == LSHIFTRT
3667 || subcode == ROTATE || subcode == ROTATERT
3669 && GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT
3670 && ((INTVAL (XEXP (XEXP (x, 1), 1)) &
3671 (INTVAL (XEXP (XEXP (x, 1), 1)) - 1)) == 0)))
3672 && REG_OR_SUBREG_REG (XEXP (XEXP (x, 1), 0))
3673 && (REG_OR_SUBREG_REG (XEXP (XEXP (x, 1), 1))
3674 || GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT)
3675 && REG_OR_SUBREG_REG (XEXP (x, 0))))
3680 if (GET_MODE_CLASS (mode) == MODE_FLOAT)
3681 return (2 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 8)
3682 + ((REG_OR_SUBREG_REG (XEXP (x, 1))
3683 || (GET_CODE (XEXP (x, 1)) == CONST_DOUBLE
3684 && arm_const_double_rtx (XEXP (x, 1))))
3688 case AND: case XOR: case IOR:
3691 /* Normally the frame registers will be spilt into reg+const during
3692 reload, so it is a bad idea to combine them with other instructions,
3693 since then they might not be moved outside of loops. As a compromise
3694 we allow integration with ops that have a constant as their second
3696 if ((REG_OR_SUBREG_REG (XEXP (x, 0))
3697 && ARM_FRAME_RTX (REG_OR_SUBREG_RTX (XEXP (x, 0)))
3698 && GET_CODE (XEXP (x, 1)) != CONST_INT)
3699 || (REG_OR_SUBREG_REG (XEXP (x, 0))
3700 && ARM_FRAME_RTX (REG_OR_SUBREG_RTX (XEXP (x, 0)))))
3704 return (4 + extra_cost + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 8)
3705 + ((REG_OR_SUBREG_REG (XEXP (x, 1))
3706 || (GET_CODE (XEXP (x, 1)) == CONST_INT
3707 && const_ok_for_op (INTVAL (XEXP (x, 1)), code)))
3710 if (REG_OR_SUBREG_REG (XEXP (x, 0)))
3711 return (1 + (GET_CODE (XEXP (x, 1)) == CONST_INT ? 0 : extra_cost)
3712 + ((REG_OR_SUBREG_REG (XEXP (x, 1))
3713 || (GET_CODE (XEXP (x, 1)) == CONST_INT
3714 && const_ok_for_op (INTVAL (XEXP (x, 1)), code)))
3717 else if (REG_OR_SUBREG_REG (XEXP (x, 1)))
3718 return (1 + extra_cost
3719 + ((((subcode = GET_CODE (XEXP (x, 0))) == ASHIFT
3720 || subcode == LSHIFTRT || subcode == ASHIFTRT
3721 || subcode == ROTATE || subcode == ROTATERT
3723 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3724 && ((INTVAL (XEXP (XEXP (x, 0), 1)) &
3725 (INTVAL (XEXP (XEXP (x, 0), 1)) - 1)) == 0)))
3726 && (REG_OR_SUBREG_REG (XEXP (XEXP (x, 0), 0)))
3727 && ((REG_OR_SUBREG_REG (XEXP (XEXP (x, 0), 1)))
3728 || GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT))
3734 /* This should have been handled by the CPU specific routines. */
3738 if (arm_arch3m && mode == SImode
3739 && GET_CODE (XEXP (x, 0)) == LSHIFTRT
3740 && GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT
3741 && (GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 0))
3742 == GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)))
3743 && (GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == ZERO_EXTEND
3744 || GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == SIGN_EXTEND))
3749 if (GET_MODE_CLASS (mode) == MODE_FLOAT)
3750 return 4 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 6);
3754 return 4 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 4);
3756 return 1 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 4);
3759 if (GET_CODE (XEXP (x, 1)) == PC || GET_CODE (XEXP (x, 2)) == PC)
3767 return 4 + (mode == DImode ? 4 : 0);
3770 if (GET_MODE (XEXP (x, 0)) == QImode)
3771 return (4 + (mode == DImode ? 4 : 0)
3772 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0));
3775 switch (GET_MODE (XEXP (x, 0)))
3778 return (1 + (mode == DImode ? 4 : 0)
3779 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0));
3782 return (4 + (mode == DImode ? 4 : 0)
3783 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0));
3786 return (1 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0));
3801 if (const_ok_for_arm (INTVAL (x)))
3802 return outer == SET ? 2 : -1;
3803 else if (outer == AND
3804 && const_ok_for_arm (~INTVAL (x)))
3806 else if ((outer == COMPARE
3807 || outer == PLUS || outer == MINUS)
3808 && const_ok_for_arm (-INTVAL (x)))
3819 if (arm_const_double_rtx (x))
3820 return outer == SET ? 2 : -1;
3821 else if ((outer == COMPARE || outer == PLUS)
3822 && neg_const_double_rtx_ok_for_fpa (x))
3831 /* RTX costs for cores with a slow MUL implementation. */
3834 arm_slowmul_rtx_costs (rtx x, int code, int outer_code, int *total)
3836 enum machine_mode mode = GET_MODE (x);
3840 *total = thumb_rtx_costs (x, code, outer_code);
3847 if (GET_MODE_CLASS (mode) == MODE_FLOAT
3854 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
3856 unsigned HOST_WIDE_INT i = (INTVAL (XEXP (x, 1))
3857 & (unsigned HOST_WIDE_INT) 0xffffffff);
3858 int cost, const_ok = const_ok_for_arm (i);
3859 int j, booth_unit_size;
3861 /* Tune as appropriate. */
3862 cost = const_ok ? 4 : 8;
3863 booth_unit_size = 2;
3864 for (j = 0; i && j < 32; j += booth_unit_size)
3866 i >>= booth_unit_size;
3874 *total = 30 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 4)
3875 + (REG_OR_SUBREG_REG (XEXP (x, 1)) ? 0 : 4);
3879 *total = arm_rtx_costs_1 (x, code, outer_code);
3885 /* RTX cost for cores with a fast multiply unit (M variants). */
3888 arm_fastmul_rtx_costs (rtx x, int code, int outer_code, int *total)
3890 enum machine_mode mode = GET_MODE (x);
3894 *total = thumb_rtx_costs (x, code, outer_code);
3901 /* There is no point basing this on the tuning, since it is always the
3902 fast variant if it exists at all. */
3904 && (GET_CODE (XEXP (x, 0)) == GET_CODE (XEXP (x, 1)))
3905 && (GET_CODE (XEXP (x, 0)) == ZERO_EXTEND
3906 || GET_CODE (XEXP (x, 0)) == SIGN_EXTEND))
3913 if (GET_MODE_CLASS (mode) == MODE_FLOAT
3920 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
3922 unsigned HOST_WIDE_INT i = (INTVAL (XEXP (x, 1))
3923 & (unsigned HOST_WIDE_INT) 0xffffffff);
3924 int cost, const_ok = const_ok_for_arm (i);
3925 int j, booth_unit_size;
3927 /* Tune as appropriate. */
3928 cost = const_ok ? 4 : 8;
3929 booth_unit_size = 8;
3930 for (j = 0; i && j < 32; j += booth_unit_size)
3932 i >>= booth_unit_size;
3940 *total = 8 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 4)
3941 + (REG_OR_SUBREG_REG (XEXP (x, 1)) ? 0 : 4);
3945 *total = arm_rtx_costs_1 (x, code, outer_code);
3951 /* RTX cost for XScale CPUs. */
3954 arm_xscale_rtx_costs (rtx x, int code, int outer_code, int *total)
3956 enum machine_mode mode = GET_MODE (x);
3960 *total = thumb_rtx_costs (x, code, outer_code);
3967 /* There is no point basing this on the tuning, since it is always the
3968 fast variant if it exists at all. */
3970 && (GET_CODE (XEXP (x, 0)) == GET_CODE (XEXP (x, 1)))
3971 && (GET_CODE (XEXP (x, 0)) == ZERO_EXTEND
3972 || GET_CODE (XEXP (x, 0)) == SIGN_EXTEND))
3979 if (GET_MODE_CLASS (mode) == MODE_FLOAT
3986 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
3988 unsigned HOST_WIDE_INT i = (INTVAL (XEXP (x, 1))
3989 & (unsigned HOST_WIDE_INT) 0xffffffff);
3990 int cost, const_ok = const_ok_for_arm (i);
3991 unsigned HOST_WIDE_INT masked_const;
3993 /* The cost will be related to two insns.
3994 First a load of the constant (MOV or LDR), then a multiply. */
3997 cost += 1; /* LDR is probably more expensive because
3998 of longer result latency. */
3999 masked_const = i & 0xffff8000;
4000 if (masked_const != 0 && masked_const != 0xffff8000)
4002 masked_const = i & 0xf8000000;
4003 if (masked_const == 0 || masked_const == 0xf8000000)
4012 *total = 8 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 4)
4013 + (REG_OR_SUBREG_REG (XEXP (x, 1)) ? 0 : 4);
4017 *total = arm_rtx_costs_1 (x, code, outer_code);
4023 /* RTX costs for 9e (and later) cores. */
4026 arm_9e_rtx_costs (rtx x, int code, int outer_code, int *total)
4028 enum machine_mode mode = GET_MODE (x);
4037 *total = COSTS_N_INSNS (3);
4041 *total = thumb_rtx_costs (x, code, outer_code);
4049 /* There is no point basing this on the tuning, since it is always the
4050 fast variant if it exists at all. */
4052 && (GET_CODE (XEXP (x, 0)) == GET_CODE (XEXP (x, 1)))
4053 && (GET_CODE (XEXP (x, 0)) == ZERO_EXTEND
4054 || GET_CODE (XEXP (x, 0)) == SIGN_EXTEND))
4061 if (GET_MODE_CLASS (mode) == MODE_FLOAT)
4078 *total = cost + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : nonreg_cost)
4079 + (REG_OR_SUBREG_REG (XEXP (x, 1)) ? 0 : nonreg_cost);
4083 *total = arm_rtx_costs_1 (x, code, outer_code);
4087 /* All address computations that can be done are free, but rtx cost returns
4088 the same for practically all of them. So we weight the different types
4089 of address here in the order (most pref first):
4090 PRE/POST_INC/DEC, SHIFT or NON-INT sum, INT sum, REG, MEM or LABEL. */
4092 arm_arm_address_cost (rtx x)
4094 enum rtx_code c = GET_CODE (x);
4096 if (c == PRE_INC || c == PRE_DEC || c == POST_INC || c == POST_DEC)
4098 if (c == MEM || c == LABEL_REF || c == SYMBOL_REF)
4101 if (c == PLUS || c == MINUS)
4103 if (GET_CODE (XEXP (x, 0)) == CONST_INT)
4106 if (ARITHMETIC_P (XEXP (x, 0)) || ARITHMETIC_P (XEXP (x, 1)))
4116 arm_thumb_address_cost (rtx x)
4118 enum rtx_code c = GET_CODE (x);
4123 && GET_CODE (XEXP (x, 0)) == REG
4124 && GET_CODE (XEXP (x, 1)) == CONST_INT)
4131 arm_address_cost (rtx x)
4133 return TARGET_ARM ? arm_arm_address_cost (x) : arm_thumb_address_cost (x);
4137 arm_use_dfa_pipeline_interface (void)
4143 arm_adjust_cost (rtx insn, rtx link, rtx dep, int cost)
4147 /* Some true dependencies can have a higher cost depending
4148 on precisely how certain input operands are used. */
4150 && REG_NOTE_KIND (link) == 0
4151 && recog_memoized (insn) >= 0
4152 && recog_memoized (dep) >= 0)
4154 int shift_opnum = get_attr_shift (insn);
4155 enum attr_type attr_type = get_attr_type (dep);
4157 /* If nonzero, SHIFT_OPNUM contains the operand number of a shifted
4158 operand for INSN. If we have a shifted input operand and the
4159 instruction we depend on is another ALU instruction, then we may
4160 have to account for an additional stall. */
4161 if (shift_opnum != 0
4162 && (attr_type == TYPE_ALU_SHIFT || attr_type == TYPE_ALU_SHIFT_REG))
4164 rtx shifted_operand;
4167 /* Get the shifted operand. */
4168 extract_insn (insn);
4169 shifted_operand = recog_data.operand[shift_opnum];
4171 /* Iterate over all the operands in DEP. If we write an operand
4172 that overlaps with SHIFTED_OPERAND, then we have increase the
4173 cost of this dependency. */
4175 preprocess_constraints ();
4176 for (opno = 0; opno < recog_data.n_operands; opno++)
4178 /* We can ignore strict inputs. */
4179 if (recog_data.operand_type[opno] == OP_IN)
4182 if (reg_overlap_mentioned_p (recog_data.operand[opno],
4189 /* XXX This is not strictly true for the FPA. */
4190 if (REG_NOTE_KIND (link) == REG_DEP_ANTI
4191 || REG_NOTE_KIND (link) == REG_DEP_OUTPUT)
4194 /* Call insns don't incur a stall, even if they follow a load. */
4195 if (REG_NOTE_KIND (link) == 0
4196 && GET_CODE (insn) == CALL_INSN)
4199 if ((i_pat = single_set (insn)) != NULL
4200 && GET_CODE (SET_SRC (i_pat)) == MEM
4201 && (d_pat = single_set (dep)) != NULL
4202 && GET_CODE (SET_DEST (d_pat)) == MEM)
4204 rtx src_mem = XEXP (SET_SRC (i_pat), 0);
4205 /* This is a load after a store, there is no conflict if the load reads
4206 from a cached area. Assume that loads from the stack, and from the
4207 constant pool are cached, and that others will miss. This is a
4210 if ((GET_CODE (src_mem) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (src_mem))
4211 || reg_mentioned_p (stack_pointer_rtx, src_mem)
4212 || reg_mentioned_p (frame_pointer_rtx, src_mem)
4213 || reg_mentioned_p (hard_frame_pointer_rtx, src_mem))
4220 static int fp_consts_inited = 0;
4222 /* Only zero is valid for VFP. Other values are also valid for FPA. */
4223 static const char * const strings_fp[8] =
4226 "4", "5", "0.5", "10"
4229 static REAL_VALUE_TYPE values_fp[8];
4232 init_fp_table (void)
4238 fp_consts_inited = 1;
4240 fp_consts_inited = 8;
4242 for (i = 0; i < fp_consts_inited; i++)
4244 r = REAL_VALUE_ATOF (strings_fp[i], DFmode);
4249 /* Return TRUE if rtx X is a valid immediate FP constant. */
4251 arm_const_double_rtx (rtx x)
4256 if (!fp_consts_inited)
4259 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
4260 if (REAL_VALUE_MINUS_ZERO (r))
4263 for (i = 0; i < fp_consts_inited; i++)
4264 if (REAL_VALUES_EQUAL (r, values_fp[i]))
4270 /* Return TRUE if rtx X is a valid immediate FPA constant. */
4272 neg_const_double_rtx_ok_for_fpa (rtx x)
4277 if (!fp_consts_inited)
4280 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
4281 r = REAL_VALUE_NEGATE (r);
4282 if (REAL_VALUE_MINUS_ZERO (r))
4285 for (i = 0; i < 8; i++)
4286 if (REAL_VALUES_EQUAL (r, values_fp[i]))
4292 /* Predicates for `match_operand' and `match_operator'. */
4294 /* s_register_operand is the same as register_operand, but it doesn't accept
4297 This function exists because at the time it was put in it led to better
4298 code. SUBREG(MEM) always needs a reload in the places where
4299 s_register_operand is used, and this seemed to lead to excessive
4302 s_register_operand (rtx op, enum machine_mode mode)
4304 if (GET_MODE (op) != mode && mode != VOIDmode)
4307 if (GET_CODE (op) == SUBREG)
4308 op = SUBREG_REG (op);
4310 /* We don't consider registers whose class is NO_REGS
4311 to be a register operand. */
4312 /* XXX might have to check for lo regs only for thumb ??? */
4313 return (GET_CODE (op) == REG
4314 && (REGNO (op) >= FIRST_PSEUDO_REGISTER
4315 || REGNO_REG_CLASS (REGNO (op)) != NO_REGS));
4318 /* A hard register operand (even before reload. */
4320 arm_hard_register_operand (rtx op, enum machine_mode mode)
4322 if (GET_MODE (op) != mode && mode != VOIDmode)
4325 return (GET_CODE (op) == REG
4326 && REGNO (op) < FIRST_PSEUDO_REGISTER);
4329 /* An arm register operand. */
4331 arm_general_register_operand (rtx op, enum machine_mode mode)
4333 if (GET_MODE (op) != mode && mode != VOIDmode)
4336 if (GET_CODE (op) == SUBREG)
4337 op = SUBREG_REG (op);
4339 return (GET_CODE (op) == REG
4340 && (REGNO (op) <= LAST_ARM_REGNUM
4341 || REGNO (op) >= FIRST_PSEUDO_REGISTER));
4344 /* Only accept reg, subreg(reg), const_int. */
4346 reg_or_int_operand (rtx op, enum machine_mode mode)
4348 if (GET_CODE (op) == CONST_INT)
4351 if (GET_MODE (op) != mode && mode != VOIDmode)
4354 if (GET_CODE (op) == SUBREG)
4355 op = SUBREG_REG (op);
4357 /* We don't consider registers whose class is NO_REGS
4358 to be a register operand. */
4359 return (GET_CODE (op) == REG
4360 && (REGNO (op) >= FIRST_PSEUDO_REGISTER
4361 || REGNO_REG_CLASS (REGNO (op)) != NO_REGS));
4364 /* Return 1 if OP is an item in memory, given that we are in reload. */
4366 arm_reload_memory_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
4368 int regno = true_regnum (op);
4370 return (!CONSTANT_P (op)
4372 || (GET_CODE (op) == REG
4373 && REGNO (op) >= FIRST_PSEUDO_REGISTER)));
4376 /* Return TRUE for valid operands for the rhs of an ARM instruction. */
4378 arm_rhs_operand (rtx op, enum machine_mode mode)
4380 return (s_register_operand (op, mode)
4381 || (GET_CODE (op) == CONST_INT && const_ok_for_arm (INTVAL (op))));
4384 /* Return TRUE for valid operands for the
4385 rhs of an ARM instruction, or a load. */
4387 arm_rhsm_operand (rtx op, enum machine_mode mode)
4389 return (s_register_operand (op, mode)
4390 || (GET_CODE (op) == CONST_INT && const_ok_for_arm (INTVAL (op)))
4391 || memory_operand (op, mode));
4394 /* Return TRUE for valid operands for the rhs of an ARM instruction, or if a
4395 constant that is valid when negated. */
4397 arm_add_operand (rtx op, enum machine_mode mode)
4400 return thumb_cmp_operand (op, mode);
4402 return (s_register_operand (op, mode)
4403 || (GET_CODE (op) == CONST_INT
4404 && (const_ok_for_arm (INTVAL (op))
4405 || const_ok_for_arm (-INTVAL (op)))));
4408 /* Return TRUE for valid ARM constants (or when valid if negated). */
4410 arm_addimm_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
4412 return (GET_CODE (op) == CONST_INT
4413 && (const_ok_for_arm (INTVAL (op))
4414 || const_ok_for_arm (-INTVAL (op))));
4418 arm_not_operand (rtx op, enum machine_mode mode)
4420 return (s_register_operand (op, mode)
4421 || (GET_CODE (op) == CONST_INT
4422 && (const_ok_for_arm (INTVAL (op))
4423 || const_ok_for_arm (~INTVAL (op)))));
4426 /* Return TRUE if the operand is a memory reference which contains an
4427 offsettable address. */
4429 offsettable_memory_operand (rtx op, enum machine_mode mode)
4431 if (mode == VOIDmode)
4432 mode = GET_MODE (op);
4434 return (mode == GET_MODE (op)
4435 && GET_CODE (op) == MEM
4436 && offsettable_address_p (reload_completed | reload_in_progress,
4437 mode, XEXP (op, 0)));
4440 /* Return TRUE if the operand is a memory reference which is, or can be
4441 made word aligned by adjusting the offset. */
4443 alignable_memory_operand (rtx op, enum machine_mode mode)
4447 if (mode == VOIDmode)
4448 mode = GET_MODE (op);
4450 if (mode != GET_MODE (op) || GET_CODE (op) != MEM)
4455 return ((GET_CODE (reg = op) == REG
4456 || (GET_CODE (op) == SUBREG
4457 && GET_CODE (reg = SUBREG_REG (op)) == REG)
4458 || (GET_CODE (op) == PLUS
4459 && GET_CODE (XEXP (op, 1)) == CONST_INT
4460 && (GET_CODE (reg = XEXP (op, 0)) == REG
4461 || (GET_CODE (XEXP (op, 0)) == SUBREG
4462 && GET_CODE (reg = SUBREG_REG (XEXP (op, 0))) == REG))))
4463 && REGNO_POINTER_ALIGN (REGNO (reg)) >= 32);
4466 /* Similar to s_register_operand, but does not allow hard integer
4469 f_register_operand (rtx op, enum machine_mode mode)
4471 if (GET_MODE (op) != mode && mode != VOIDmode)
4474 if (GET_CODE (op) == SUBREG)
4475 op = SUBREG_REG (op);
4477 /* We don't consider registers whose class is NO_REGS
4478 to be a register operand. */
4479 return (GET_CODE (op) == REG
4480 && (REGNO (op) >= FIRST_PSEUDO_REGISTER
4481 || REGNO_REG_CLASS (REGNO (op)) == FPA_REGS));
4484 /* Return TRUE for valid operands for the rhs of an floating point insns.
4485 Allows regs or certain consts on FPA, just regs for everything else. */
4487 arm_float_rhs_operand (rtx op, enum machine_mode mode)
4489 if (s_register_operand (op, mode))
4492 if (GET_MODE (op) != mode && mode != VOIDmode)
4495 if (TARGET_FPA && GET_CODE (op) == CONST_DOUBLE)
4496 return arm_const_double_rtx (op);
4502 arm_float_add_operand (rtx op, enum machine_mode mode)
4504 if (s_register_operand (op, mode))
4507 if (GET_MODE (op) != mode && mode != VOIDmode)
4510 if (TARGET_FPA && GET_CODE (op) == CONST_DOUBLE)
4511 return (arm_const_double_rtx (op)
4512 || neg_const_double_rtx_ok_for_fpa (op));
4518 /* Return TRUE if OP is suitable for the rhs of a floating point comparison.
4519 Depends which fpu we are targeting. */
4522 arm_float_compare_operand (rtx op, enum machine_mode mode)
4525 return vfp_compare_operand (op, mode);
4527 return arm_float_rhs_operand (op, mode);
4531 /* Return nonzero if OP is a valid Cirrus memory address pattern. */
4533 cirrus_memory_offset (rtx op)
4535 /* Reject eliminable registers. */
4536 if (! (reload_in_progress || reload_completed)
4537 && ( reg_mentioned_p (frame_pointer_rtx, op)
4538 || reg_mentioned_p (arg_pointer_rtx, op)
4539 || reg_mentioned_p (virtual_incoming_args_rtx, op)
4540 || reg_mentioned_p (virtual_outgoing_args_rtx, op)
4541 || reg_mentioned_p (virtual_stack_dynamic_rtx, op)
4542 || reg_mentioned_p (virtual_stack_vars_rtx, op)))
4545 if (GET_CODE (op) == MEM)
4551 /* Match: (mem (reg)). */
4552 if (GET_CODE (ind) == REG)
4558 if (GET_CODE (ind) == PLUS
4559 && GET_CODE (XEXP (ind, 0)) == REG
4560 && REG_MODE_OK_FOR_BASE_P (XEXP (ind, 0), VOIDmode)
4561 && GET_CODE (XEXP (ind, 1)) == CONST_INT)
4569 arm_extendqisi_mem_op (rtx op, enum machine_mode mode)
4571 if (!memory_operand (op, mode))
4574 return arm_legitimate_address_p (mode, XEXP (op, 0), SIGN_EXTEND, 0);
4577 /* Return nonzero if OP is a Cirrus or general register. */
4579 cirrus_register_operand (rtx op, enum machine_mode mode)
4581 if (GET_MODE (op) != mode && mode != VOIDmode)
4584 if (GET_CODE (op) == SUBREG)
4585 op = SUBREG_REG (op);
4587 return (GET_CODE (op) == REG
4588 && (REGNO_REG_CLASS (REGNO (op)) == CIRRUS_REGS
4589 || REGNO_REG_CLASS (REGNO (op)) == GENERAL_REGS));
4592 /* Return nonzero if OP is a cirrus FP register. */
4594 cirrus_fp_register (rtx op, enum machine_mode mode)
4596 if (GET_MODE (op) != mode && mode != VOIDmode)
4599 if (GET_CODE (op) == SUBREG)
4600 op = SUBREG_REG (op);
4602 return (GET_CODE (op) == REG
4603 && (REGNO (op) >= FIRST_PSEUDO_REGISTER
4604 || REGNO_REG_CLASS (REGNO (op)) == CIRRUS_REGS));
4607 /* Return nonzero if OP is a 6bit constant (0..63). */
4609 cirrus_shift_const (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
4611 return (GET_CODE (op) == CONST_INT
4613 && INTVAL (op) < 64);
4617 /* Return TRUE if OP is a valid VFP memory address pattern. */
4618 /* Copied from cirrus_memory_offset but with restricted offset range. */
4621 vfp_mem_operand (rtx op)
4623 /* Reject eliminable registers. */
4625 if (! (reload_in_progress || reload_completed)
4626 && ( reg_mentioned_p (frame_pointer_rtx, op)
4627 || reg_mentioned_p (arg_pointer_rtx, op)
4628 || reg_mentioned_p (virtual_incoming_args_rtx, op)
4629 || reg_mentioned_p (virtual_outgoing_args_rtx, op)
4630 || reg_mentioned_p (virtual_stack_dynamic_rtx, op)
4631 || reg_mentioned_p (virtual_stack_vars_rtx, op)))
4634 /* Constants are converted into offsets from labels. */
4635 if (GET_CODE (op) == MEM)
4641 if (reload_completed
4642 && (GET_CODE (ind) == LABEL_REF
4643 || (GET_CODE (ind) == CONST
4644 && GET_CODE (XEXP (ind, 0)) == PLUS
4645 && GET_CODE (XEXP (XEXP (ind, 0), 0)) == LABEL_REF
4646 && GET_CODE (XEXP (XEXP (ind, 0), 1)) == CONST_INT)))
4649 /* Match: (mem (reg)). */
4650 if (GET_CODE (ind) == REG)
4651 return arm_address_register_rtx_p (ind, 0);
4656 if (GET_CODE (ind) == PLUS
4657 && GET_CODE (XEXP (ind, 0)) == REG
4658 && REG_MODE_OK_FOR_BASE_P (XEXP (ind, 0), VOIDmode)
4659 && GET_CODE (XEXP (ind, 1)) == CONST_INT
4660 && INTVAL (XEXP (ind, 1)) > -1024
4661 && INTVAL (XEXP (ind, 1)) < 1024)
4669 /* Return TRUE if OP is a REG or constant zero. */
4671 vfp_compare_operand (rtx op, enum machine_mode mode)
4673 if (s_register_operand (op, mode))
4676 return (GET_CODE (op) == CONST_DOUBLE
4677 && arm_const_double_rtx (op));
4681 /* Return GENERAL_REGS if a scratch register required to reload x to/from
4682 VFP registers. Otherwise return NO_REGS. */
4685 vfp_secondary_reload_class (enum machine_mode mode, rtx x)
4687 if (vfp_mem_operand (x) || s_register_operand (x, mode))
4690 return GENERAL_REGS;
4694 /* Returns TRUE if INSN is an "LDR REG, ADDR" instruction.
4695 Use by the Cirrus Maverick code which has to workaround
4696 a hardware bug triggered by such instructions. */
4698 arm_memory_load_p (rtx insn)
4700 rtx body, lhs, rhs;;
4702 if (insn == NULL_RTX || GET_CODE (insn) != INSN)
4705 body = PATTERN (insn);
4707 if (GET_CODE (body) != SET)
4710 lhs = XEXP (body, 0);
4711 rhs = XEXP (body, 1);
4713 lhs = REG_OR_SUBREG_RTX (lhs);
4715 /* If the destination is not a general purpose
4716 register we do not have to worry. */
4717 if (GET_CODE (lhs) != REG
4718 || REGNO_REG_CLASS (REGNO (lhs)) != GENERAL_REGS)
4721 /* As well as loads from memory we also have to react
4722 to loads of invalid constants which will be turned
4723 into loads from the minipool. */
4724 return (GET_CODE (rhs) == MEM
4725 || GET_CODE (rhs) == SYMBOL_REF
4726 || note_invalid_constants (insn, -1, false));
4729 /* Return TRUE if INSN is a Cirrus instruction. */
4731 arm_cirrus_insn_p (rtx insn)
4733 enum attr_cirrus attr;
4735 /* get_attr aborts on USE and CLOBBER. */
4737 || GET_CODE (insn) != INSN
4738 || GET_CODE (PATTERN (insn)) == USE
4739 || GET_CODE (PATTERN (insn)) == CLOBBER)
4742 attr = get_attr_cirrus (insn);
4744 return attr != CIRRUS_NOT;
4747 /* Cirrus reorg for invalid instruction combinations. */
4749 cirrus_reorg (rtx first)
4751 enum attr_cirrus attr;
4752 rtx body = PATTERN (first);
4756 /* Any branch must be followed by 2 non Cirrus instructions. */
4757 if (GET_CODE (first) == JUMP_INSN && GET_CODE (body) != RETURN)
4760 t = next_nonnote_insn (first);
4762 if (arm_cirrus_insn_p (t))
4765 if (arm_cirrus_insn_p (next_nonnote_insn (t)))
4769 emit_insn_after (gen_nop (), first);
4774 /* (float (blah)) is in parallel with a clobber. */
4775 if (GET_CODE (body) == PARALLEL && XVECLEN (body, 0) > 0)
4776 body = XVECEXP (body, 0, 0);
4778 if (GET_CODE (body) == SET)
4780 rtx lhs = XEXP (body, 0), rhs = XEXP (body, 1);
4782 /* cfldrd, cfldr64, cfstrd, cfstr64 must
4783 be followed by a non Cirrus insn. */
4784 if (get_attr_cirrus (first) == CIRRUS_DOUBLE)
4786 if (arm_cirrus_insn_p (next_nonnote_insn (first)))
4787 emit_insn_after (gen_nop (), first);
4791 else if (arm_memory_load_p (first))
4793 unsigned int arm_regno;
4795 /* Any ldr/cfmvdlr, ldr/cfmvdhr, ldr/cfmvsr, ldr/cfmv64lr,
4796 ldr/cfmv64hr combination where the Rd field is the same
4797 in both instructions must be split with a non Cirrus
4804 /* Get Arm register number for ldr insn. */
4805 if (GET_CODE (lhs) == REG)
4806 arm_regno = REGNO (lhs);
4807 else if (GET_CODE (rhs) == REG)
4808 arm_regno = REGNO (rhs);
4813 first = next_nonnote_insn (first);
4815 if (! arm_cirrus_insn_p (first))
4818 body = PATTERN (first);
4820 /* (float (blah)) is in parallel with a clobber. */
4821 if (GET_CODE (body) == PARALLEL && XVECLEN (body, 0))
4822 body = XVECEXP (body, 0, 0);
4824 if (GET_CODE (body) == FLOAT)
4825 body = XEXP (body, 0);
4827 if (get_attr_cirrus (first) == CIRRUS_MOVE
4828 && GET_CODE (XEXP (body, 1)) == REG
4829 && arm_regno == REGNO (XEXP (body, 1)))
4830 emit_insn_after (gen_nop (), first);
4836 /* get_attr aborts on USE and CLOBBER. */
4838 || GET_CODE (first) != INSN
4839 || GET_CODE (PATTERN (first)) == USE
4840 || GET_CODE (PATTERN (first)) == CLOBBER)
4843 attr = get_attr_cirrus (first);
4845 /* Any coprocessor compare instruction (cfcmps, cfcmpd, ...)
4846 must be followed by a non-coprocessor instruction. */
4847 if (attr == CIRRUS_COMPARE)
4851 t = next_nonnote_insn (first);
4853 if (arm_cirrus_insn_p (t))
4856 if (arm_cirrus_insn_p (next_nonnote_insn (t)))
4860 emit_insn_after (gen_nop (), first);
4866 /* Return nonzero if OP is a constant power of two. */
4868 power_of_two_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
4870 if (GET_CODE (op) == CONST_INT)
4872 HOST_WIDE_INT value = INTVAL (op);
4874 return value != 0 && (value & (value - 1)) == 0;
4880 /* Return TRUE for a valid operand of a DImode operation.
4881 Either: REG, SUBREG, CONST_DOUBLE or MEM(DImode_address).
4882 Note that this disallows MEM(REG+REG), but allows
4883 MEM(PRE/POST_INC/DEC(REG)). */
4885 di_operand (rtx op, enum machine_mode mode)
4887 if (s_register_operand (op, mode))
4890 if (mode != VOIDmode && GET_MODE (op) != VOIDmode && GET_MODE (op) != DImode)
4893 if (GET_CODE (op) == SUBREG)
4894 op = SUBREG_REG (op);
4896 switch (GET_CODE (op))
4903 return memory_address_p (DImode, XEXP (op, 0));
4910 /* Like di_operand, but don't accept constants. */
4912 nonimmediate_di_operand (rtx op, enum machine_mode mode)
4914 if (s_register_operand (op, mode))
4917 if (mode != VOIDmode && GET_MODE (op) != VOIDmode && GET_MODE (op) != DImode)
4920 if (GET_CODE (op) == SUBREG)
4921 op = SUBREG_REG (op);
4923 if (GET_CODE (op) == MEM)
4924 return memory_address_p (DImode, XEXP (op, 0));
4929 /* Return TRUE for a valid operand of a DFmode operation when soft-float.
4930 Either: REG, SUBREG, CONST_DOUBLE or MEM(DImode_address).
4931 Note that this disallows MEM(REG+REG), but allows
4932 MEM(PRE/POST_INC/DEC(REG)). */
4934 soft_df_operand (rtx op, enum machine_mode mode)
4936 if (s_register_operand (op, mode))
4939 if (mode != VOIDmode && GET_MODE (op) != mode)
4942 if (GET_CODE (op) == SUBREG && CONSTANT_P (SUBREG_REG (op)))
4945 if (GET_CODE (op) == SUBREG)
4946 op = SUBREG_REG (op);
4948 switch (GET_CODE (op))
4954 return memory_address_p (DFmode, XEXP (op, 0));
4961 /* Like soft_df_operand, but don't accept constants. */
4963 nonimmediate_soft_df_operand (rtx op, enum machine_mode mode)
4965 if (s_register_operand (op, mode))
4968 if (mode != VOIDmode && GET_MODE (op) != mode)
4971 if (GET_CODE (op) == SUBREG)
4972 op = SUBREG_REG (op);
4974 if (GET_CODE (op) == MEM)
4975 return memory_address_p (DFmode, XEXP (op, 0));
4979 /* Return TRUE for valid index operands. */
4981 index_operand (rtx op, enum machine_mode mode)
4983 return (s_register_operand (op, mode)
4984 || (immediate_operand (op, mode)
4985 && (GET_CODE (op) != CONST_INT
4986 || (INTVAL (op) < 4096 && INTVAL (op) > -4096))));
4989 /* Return TRUE for valid shifts by a constant. This also accepts any
4990 power of two on the (somewhat overly relaxed) assumption that the
4991 shift operator in this case was a mult. */
4993 const_shift_operand (rtx op, enum machine_mode mode)
4995 return (power_of_two_operand (op, mode)
4996 || (immediate_operand (op, mode)
4997 && (GET_CODE (op) != CONST_INT
4998 || (INTVAL (op) < 32 && INTVAL (op) > 0))));
5001 /* Return TRUE for arithmetic operators which can be combined with a multiply
5004 shiftable_operator (rtx x, enum machine_mode mode)
5008 if (GET_MODE (x) != mode)
5011 code = GET_CODE (x);
5013 return (code == PLUS || code == MINUS
5014 || code == IOR || code == XOR || code == AND);
5017 /* Return TRUE for binary logical operators. */
5019 logical_binary_operator (rtx x, enum machine_mode mode)
5023 if (GET_MODE (x) != mode)
5026 code = GET_CODE (x);
5028 return (code == IOR || code == XOR || code == AND);
5031 /* Return TRUE for shift operators. */
5033 shift_operator (rtx x,enum machine_mode mode)
5037 if (GET_MODE (x) != mode)
5040 code = GET_CODE (x);
5043 return power_of_two_operand (XEXP (x, 1), mode);
5045 return (code == ASHIFT || code == ASHIFTRT || code == LSHIFTRT
5046 || code == ROTATERT);
5049 /* Return TRUE if x is EQ or NE. */
5051 equality_operator (rtx x, enum machine_mode mode ATTRIBUTE_UNUSED)
5053 return GET_CODE (x) == EQ || GET_CODE (x) == NE;
5056 /* Return TRUE if x is a comparison operator other than LTGT or UNEQ. */
5058 arm_comparison_operator (rtx x, enum machine_mode mode)
5060 return (comparison_operator (x, mode)
5061 && GET_CODE (x) != LTGT
5062 && GET_CODE (x) != UNEQ);
5065 /* Return TRUE for SMIN SMAX UMIN UMAX operators. */
5067 minmax_operator (rtx x, enum machine_mode mode)
5069 enum rtx_code code = GET_CODE (x);
5071 if (GET_MODE (x) != mode)
5074 return code == SMIN || code == SMAX || code == UMIN || code == UMAX;
5077 /* Return TRUE if this is the condition code register, if we aren't given
5078 a mode, accept any class CCmode register. */
5080 cc_register (rtx x, enum machine_mode mode)
5082 if (mode == VOIDmode)
5084 mode = GET_MODE (x);
5086 if (GET_MODE_CLASS (mode) != MODE_CC)
5090 if ( GET_MODE (x) == mode
5091 && GET_CODE (x) == REG
5092 && REGNO (x) == CC_REGNUM)
5098 /* Return TRUE if this is the condition code register, if we aren't given
5099 a mode, accept any class CCmode register which indicates a dominance
5102 dominant_cc_register (rtx x, enum machine_mode mode)
5104 if (mode == VOIDmode)
5106 mode = GET_MODE (x);
5108 if (GET_MODE_CLASS (mode) != MODE_CC)
5112 if (mode != CC_DNEmode && mode != CC_DEQmode
5113 && mode != CC_DLEmode && mode != CC_DLTmode
5114 && mode != CC_DGEmode && mode != CC_DGTmode
5115 && mode != CC_DLEUmode && mode != CC_DLTUmode
5116 && mode != CC_DGEUmode && mode != CC_DGTUmode)
5119 return cc_register (x, mode);
5122 /* Return TRUE if X references a SYMBOL_REF. */
5124 symbol_mentioned_p (rtx x)
5129 if (GET_CODE (x) == SYMBOL_REF)
5132 fmt = GET_RTX_FORMAT (GET_CODE (x));
5134 for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
5140 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
5141 if (symbol_mentioned_p (XVECEXP (x, i, j)))
5144 else if (fmt[i] == 'e' && symbol_mentioned_p (XEXP (x, i)))
5151 /* Return TRUE if X references a LABEL_REF. */
5153 label_mentioned_p (rtx x)
5158 if (GET_CODE (x) == LABEL_REF)
5161 fmt = GET_RTX_FORMAT (GET_CODE (x));
5162 for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
5168 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
5169 if (label_mentioned_p (XVECEXP (x, i, j)))
5172 else if (fmt[i] == 'e' && label_mentioned_p (XEXP (x, i)))
5182 enum rtx_code code = GET_CODE (x);
5186 else if (code == SMIN)
5188 else if (code == UMIN)
5190 else if (code == UMAX)
5196 /* Return 1 if memory locations are adjacent. */
5198 adjacent_mem_locations (rtx a, rtx b)
5200 if ((GET_CODE (XEXP (a, 0)) == REG
5201 || (GET_CODE (XEXP (a, 0)) == PLUS
5202 && GET_CODE (XEXP (XEXP (a, 0), 1)) == CONST_INT))
5203 && (GET_CODE (XEXP (b, 0)) == REG
5204 || (GET_CODE (XEXP (b, 0)) == PLUS
5205 && GET_CODE (XEXP (XEXP (b, 0), 1)) == CONST_INT)))
5207 int val0 = 0, val1 = 0;
5210 if (GET_CODE (XEXP (a, 0)) == PLUS)
5212 reg0 = REGNO (XEXP (XEXP (a, 0), 0));
5213 val0 = INTVAL (XEXP (XEXP (a, 0), 1));
5216 reg0 = REGNO (XEXP (a, 0));
5218 if (GET_CODE (XEXP (b, 0)) == PLUS)
5220 reg1 = REGNO (XEXP (XEXP (b, 0), 0));
5221 val1 = INTVAL (XEXP (XEXP (b, 0), 1));
5224 reg1 = REGNO (XEXP (b, 0));
5226 /* Don't accept any offset that will require multiple
5227 instructions to handle, since this would cause the
5228 arith_adjacentmem pattern to output an overlong sequence. */
5229 if (!const_ok_for_op (PLUS, val0) || !const_ok_for_op (PLUS, val1))
5232 return (reg0 == reg1) && ((val1 - val0) == 4 || (val0 - val1) == 4);
5237 /* Return 1 if OP is a load multiple operation. It is known to be
5238 parallel and the first section will be tested. */
5240 load_multiple_operation (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
5242 HOST_WIDE_INT count = XVECLEN (op, 0);
5245 HOST_WIDE_INT i = 1, base = 0;
5249 || GET_CODE (XVECEXP (op, 0, 0)) != SET)
5252 /* Check to see if this might be a write-back. */
5253 if (GET_CODE (SET_SRC (elt = XVECEXP (op, 0, 0))) == PLUS)
5258 /* Now check it more carefully. */
5259 if (GET_CODE (SET_DEST (elt)) != REG
5260 || GET_CODE (XEXP (SET_SRC (elt), 0)) != REG
5261 || GET_CODE (XEXP (SET_SRC (elt), 1)) != CONST_INT
5262 || INTVAL (XEXP (SET_SRC (elt), 1)) != (count - 1) * 4)
5266 /* Perform a quick check so we don't blow up below. */
5268 || GET_CODE (XVECEXP (op, 0, i - 1)) != SET
5269 || GET_CODE (SET_DEST (XVECEXP (op, 0, i - 1))) != REG
5270 || GET_CODE (SET_SRC (XVECEXP (op, 0, i - 1))) != MEM)
5273 dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, i - 1)));
5274 src_addr = XEXP (SET_SRC (XVECEXP (op, 0, i - 1)), 0);
5276 for (; i < count; i++)
5278 elt = XVECEXP (op, 0, i);
5280 if (GET_CODE (elt) != SET
5281 || GET_CODE (SET_DEST (elt)) != REG
5282 || GET_MODE (SET_DEST (elt)) != SImode
5283 || REGNO (SET_DEST (elt)) != (unsigned int)(dest_regno + i - base)
5284 || GET_CODE (SET_SRC (elt)) != MEM
5285 || GET_MODE (SET_SRC (elt)) != SImode
5286 || GET_CODE (XEXP (SET_SRC (elt), 0)) != PLUS
5287 || !rtx_equal_p (XEXP (XEXP (SET_SRC (elt), 0), 0), src_addr)
5288 || GET_CODE (XEXP (XEXP (SET_SRC (elt), 0), 1)) != CONST_INT
5289 || INTVAL (XEXP (XEXP (SET_SRC (elt), 0), 1)) != (i - base) * 4)
5296 /* Return 1 if OP is a store multiple operation. It is known to be
5297 parallel and the first section will be tested. */
5299 store_multiple_operation (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
5301 HOST_WIDE_INT count = XVECLEN (op, 0);
5304 HOST_WIDE_INT i = 1, base = 0;
5308 || GET_CODE (XVECEXP (op, 0, 0)) != SET)
5311 /* Check to see if this might be a write-back. */
5312 if (GET_CODE (SET_SRC (elt = XVECEXP (op, 0, 0))) == PLUS)
5317 /* Now check it more carefully. */
5318 if (GET_CODE (SET_DEST (elt)) != REG
5319 || GET_CODE (XEXP (SET_SRC (elt), 0)) != REG
5320 || GET_CODE (XEXP (SET_SRC (elt), 1)) != CONST_INT
5321 || INTVAL (XEXP (SET_SRC (elt), 1)) != (count - 1) * 4)
5325 /* Perform a quick check so we don't blow up below. */
5327 || GET_CODE (XVECEXP (op, 0, i - 1)) != SET
5328 || GET_CODE (SET_DEST (XVECEXP (op, 0, i - 1))) != MEM
5329 || GET_CODE (SET_SRC (XVECEXP (op, 0, i - 1))) != REG)
5332 src_regno = REGNO (SET_SRC (XVECEXP (op, 0, i - 1)));
5333 dest_addr = XEXP (SET_DEST (XVECEXP (op, 0, i - 1)), 0);
5335 for (; i < count; i++)
5337 elt = XVECEXP (op, 0, i);
5339 if (GET_CODE (elt) != SET
5340 || GET_CODE (SET_SRC (elt)) != REG
5341 || GET_MODE (SET_SRC (elt)) != SImode
5342 || REGNO (SET_SRC (elt)) != (unsigned int)(src_regno + i - base)
5343 || GET_CODE (SET_DEST (elt)) != MEM
5344 || GET_MODE (SET_DEST (elt)) != SImode
5345 || GET_CODE (XEXP (SET_DEST (elt), 0)) != PLUS
5346 || !rtx_equal_p (XEXP (XEXP (SET_DEST (elt), 0), 0), dest_addr)
5347 || GET_CODE (XEXP (XEXP (SET_DEST (elt), 0), 1)) != CONST_INT
5348 || INTVAL (XEXP (XEXP (SET_DEST (elt), 0), 1)) != (i - base) * 4)
5356 load_multiple_sequence (rtx *operands, int nops, int *regs, int *base,
5357 HOST_WIDE_INT *load_offset)
5359 int unsorted_regs[4];
5360 HOST_WIDE_INT unsorted_offsets[4];
5365 /* Can only handle 2, 3, or 4 insns at present,
5366 though could be easily extended if required. */
5367 if (nops < 2 || nops > 4)
5370 /* Loop over the operands and check that the memory references are
5371 suitable (ie immediate offsets from the same base register). At
5372 the same time, extract the target register, and the memory
5374 for (i = 0; i < nops; i++)
5379 /* Convert a subreg of a mem into the mem itself. */
5380 if (GET_CODE (operands[nops + i]) == SUBREG)
5381 operands[nops + i] = alter_subreg (operands + (nops + i));
5383 if (GET_CODE (operands[nops + i]) != MEM)
5386 /* Don't reorder volatile memory references; it doesn't seem worth
5387 looking for the case where the order is ok anyway. */
5388 if (MEM_VOLATILE_P (operands[nops + i]))
5391 offset = const0_rtx;
5393 if ((GET_CODE (reg = XEXP (operands[nops + i], 0)) == REG
5394 || (GET_CODE (reg) == SUBREG
5395 && GET_CODE (reg = SUBREG_REG (reg)) == REG))
5396 || (GET_CODE (XEXP (operands[nops + i], 0)) == PLUS
5397 && ((GET_CODE (reg = XEXP (XEXP (operands[nops + i], 0), 0))
5399 || (GET_CODE (reg) == SUBREG
5400 && GET_CODE (reg = SUBREG_REG (reg)) == REG))
5401 && (GET_CODE (offset = XEXP (XEXP (operands[nops + i], 0), 1))
5406 base_reg = REGNO (reg);
5407 unsorted_regs[0] = (GET_CODE (operands[i]) == REG
5408 ? REGNO (operands[i])
5409 : REGNO (SUBREG_REG (operands[i])));
5414 if (base_reg != (int) REGNO (reg))
5415 /* Not addressed from the same base register. */
5418 unsorted_regs[i] = (GET_CODE (operands[i]) == REG
5419 ? REGNO (operands[i])
5420 : REGNO (SUBREG_REG (operands[i])));
5421 if (unsorted_regs[i] < unsorted_regs[order[0]])
5425 /* If it isn't an integer register, or if it overwrites the
5426 base register but isn't the last insn in the list, then
5427 we can't do this. */
5428 if (unsorted_regs[i] < 0 || unsorted_regs[i] > 14
5429 || (i != nops - 1 && unsorted_regs[i] == base_reg))
5432 unsorted_offsets[i] = INTVAL (offset);
5435 /* Not a suitable memory address. */
5439 /* All the useful information has now been extracted from the
5440 operands into unsorted_regs and unsorted_offsets; additionally,
5441 order[0] has been set to the lowest numbered register in the
5442 list. Sort the registers into order, and check that the memory
5443 offsets are ascending and adjacent. */
5445 for (i = 1; i < nops; i++)
5449 order[i] = order[i - 1];
5450 for (j = 0; j < nops; j++)
5451 if (unsorted_regs[j] > unsorted_regs[order[i - 1]]
5452 && (order[i] == order[i - 1]
5453 || unsorted_regs[j] < unsorted_regs[order[i]]))
5456 /* Have we found a suitable register? if not, one must be used more
5458 if (order[i] == order[i - 1])
5461 /* Is the memory address adjacent and ascending? */
5462 if (unsorted_offsets[order[i]] != unsorted_offsets[order[i - 1]] + 4)
5470 for (i = 0; i < nops; i++)
5471 regs[i] = unsorted_regs[order[i]];
5473 *load_offset = unsorted_offsets[order[0]];
5476 if (unsorted_offsets[order[0]] == 0)
5477 return 1; /* ldmia */
5479 if (unsorted_offsets[order[0]] == 4)
5480 return 2; /* ldmib */
5482 if (unsorted_offsets[order[nops - 1]] == 0)
5483 return 3; /* ldmda */
5485 if (unsorted_offsets[order[nops - 1]] == -4)
5486 return 4; /* ldmdb */
5488 /* For ARM8,9 & StrongARM, 2 ldr instructions are faster than an ldm
5489 if the offset isn't small enough. The reason 2 ldrs are faster
5490 is because these ARMs are able to do more than one cache access
5491 in a single cycle. The ARM9 and StrongARM have Harvard caches,
5492 whilst the ARM8 has a double bandwidth cache. This means that
5493 these cores can do both an instruction fetch and a data fetch in
5494 a single cycle, so the trick of calculating the address into a
5495 scratch register (one of the result regs) and then doing a load
5496 multiple actually becomes slower (and no smaller in code size).
5497 That is the transformation
5499 ldr rd1, [rbase + offset]
5500 ldr rd2, [rbase + offset + 4]
5504 add rd1, rbase, offset
5505 ldmia rd1, {rd1, rd2}
5507 produces worse code -- '3 cycles + any stalls on rd2' instead of
5508 '2 cycles + any stalls on rd2'. On ARMs with only one cache
5509 access per cycle, the first sequence could never complete in less
5510 than 6 cycles, whereas the ldm sequence would only take 5 and
5511 would make better use of sequential accesses if not hitting the
5514 We cheat here and test 'arm_ld_sched' which we currently know to
5515 only be true for the ARM8, ARM9 and StrongARM. If this ever
5516 changes, then the test below needs to be reworked. */
5517 if (nops == 2 && arm_ld_sched)
5520 /* Can't do it without setting up the offset, only do this if it takes
5521 no more than one insn. */
5522 return (const_ok_for_arm (unsorted_offsets[order[0]])
5523 || const_ok_for_arm (-unsorted_offsets[order[0]])) ? 5 : 0;
5527 emit_ldm_seq (rtx *operands, int nops)
5531 HOST_WIDE_INT offset;
5535 switch (load_multiple_sequence (operands, nops, regs, &base_reg, &offset))
5538 strcpy (buf, "ldm%?ia\t");
5542 strcpy (buf, "ldm%?ib\t");
5546 strcpy (buf, "ldm%?da\t");
5550 strcpy (buf, "ldm%?db\t");
5555 sprintf (buf, "add%%?\t%s%s, %s%s, #%ld", REGISTER_PREFIX,
5556 reg_names[regs[0]], REGISTER_PREFIX, reg_names[base_reg],
5559 sprintf (buf, "sub%%?\t%s%s, %s%s, #%ld", REGISTER_PREFIX,
5560 reg_names[regs[0]], REGISTER_PREFIX, reg_names[base_reg],
5562 output_asm_insn (buf, operands);
5564 strcpy (buf, "ldm%?ia\t");
5571 sprintf (buf + strlen (buf), "%s%s, {%s%s", REGISTER_PREFIX,
5572 reg_names[base_reg], REGISTER_PREFIX, reg_names[regs[0]]);
5574 for (i = 1; i < nops; i++)
5575 sprintf (buf + strlen (buf), ", %s%s", REGISTER_PREFIX,
5576 reg_names[regs[i]]);
5578 strcat (buf, "}\t%@ phole ldm");
5580 output_asm_insn (buf, operands);
5585 store_multiple_sequence (rtx *operands, int nops, int *regs, int *base,
5586 HOST_WIDE_INT * load_offset)
5588 int unsorted_regs[4];
5589 HOST_WIDE_INT unsorted_offsets[4];
5594 /* Can only handle 2, 3, or 4 insns at present, though could be easily
5595 extended if required. */
5596 if (nops < 2 || nops > 4)
5599 /* Loop over the operands and check that the memory references are
5600 suitable (ie immediate offsets from the same base register). At
5601 the same time, extract the target register, and the memory
5603 for (i = 0; i < nops; i++)
5608 /* Convert a subreg of a mem into the mem itself. */
5609 if (GET_CODE (operands[nops + i]) == SUBREG)
5610 operands[nops + i] = alter_subreg (operands + (nops + i));
5612 if (GET_CODE (operands[nops + i]) != MEM)
5615 /* Don't reorder volatile memory references; it doesn't seem worth
5616 looking for the case where the order is ok anyway. */
5617 if (MEM_VOLATILE_P (operands[nops + i]))
5620 offset = const0_rtx;
5622 if ((GET_CODE (reg = XEXP (operands[nops + i], 0)) == REG
5623 || (GET_CODE (reg) == SUBREG
5624 && GET_CODE (reg = SUBREG_REG (reg)) == REG))
5625 || (GET_CODE (XEXP (operands[nops + i], 0)) == PLUS
5626 && ((GET_CODE (reg = XEXP (XEXP (operands[nops + i], 0), 0))
5628 || (GET_CODE (reg) == SUBREG
5629 && GET_CODE (reg = SUBREG_REG (reg)) == REG))
5630 && (GET_CODE (offset = XEXP (XEXP (operands[nops + i], 0), 1))
5635 base_reg = REGNO (reg);
5636 unsorted_regs[0] = (GET_CODE (operands[i]) == REG
5637 ? REGNO (operands[i])
5638 : REGNO (SUBREG_REG (operands[i])));
5643 if (base_reg != (int) REGNO (reg))
5644 /* Not addressed from the same base register. */
5647 unsorted_regs[i] = (GET_CODE (operands[i]) == REG
5648 ? REGNO (operands[i])
5649 : REGNO (SUBREG_REG (operands[i])));
5650 if (unsorted_regs[i] < unsorted_regs[order[0]])
5654 /* If it isn't an integer register, then we can't do this. */
5655 if (unsorted_regs[i] < 0 || unsorted_regs[i] > 14)
5658 unsorted_offsets[i] = INTVAL (offset);
5661 /* Not a suitable memory address. */
5665 /* All the useful information has now been extracted from the
5666 operands into unsorted_regs and unsorted_offsets; additionally,
5667 order[0] has been set to the lowest numbered register in the
5668 list. Sort the registers into order, and check that the memory
5669 offsets are ascending and adjacent. */
5671 for (i = 1; i < nops; i++)
5675 order[i] = order[i - 1];
5676 for (j = 0; j < nops; j++)
5677 if (unsorted_regs[j] > unsorted_regs[order[i - 1]]
5678 && (order[i] == order[i - 1]
5679 || unsorted_regs[j] < unsorted_regs[order[i]]))
5682 /* Have we found a suitable register? if not, one must be used more
5684 if (order[i] == order[i - 1])
5687 /* Is the memory address adjacent and ascending? */
5688 if (unsorted_offsets[order[i]] != unsorted_offsets[order[i - 1]] + 4)
5696 for (i = 0; i < nops; i++)
5697 regs[i] = unsorted_regs[order[i]];
5699 *load_offset = unsorted_offsets[order[0]];
5702 if (unsorted_offsets[order[0]] == 0)
5703 return 1; /* stmia */
5705 if (unsorted_offsets[order[0]] == 4)
5706 return 2; /* stmib */
5708 if (unsorted_offsets[order[nops - 1]] == 0)
5709 return 3; /* stmda */
5711 if (unsorted_offsets[order[nops - 1]] == -4)
5712 return 4; /* stmdb */
5718 emit_stm_seq (rtx *operands, int nops)
5722 HOST_WIDE_INT offset;
5726 switch (store_multiple_sequence (operands, nops, regs, &base_reg, &offset))
5729 strcpy (buf, "stm%?ia\t");
5733 strcpy (buf, "stm%?ib\t");
5737 strcpy (buf, "stm%?da\t");
5741 strcpy (buf, "stm%?db\t");
5748 sprintf (buf + strlen (buf), "%s%s, {%s%s", REGISTER_PREFIX,
5749 reg_names[base_reg], REGISTER_PREFIX, reg_names[regs[0]]);
5751 for (i = 1; i < nops; i++)
5752 sprintf (buf + strlen (buf), ", %s%s", REGISTER_PREFIX,
5753 reg_names[regs[i]]);
5755 strcat (buf, "}\t%@ phole stm");
5757 output_asm_insn (buf, operands);
5762 multi_register_push (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
5764 if (GET_CODE (op) != PARALLEL
5765 || (GET_CODE (XVECEXP (op, 0, 0)) != SET)
5766 || (GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != UNSPEC)
5767 || (XINT (SET_SRC (XVECEXP (op, 0, 0)), 1) != UNSPEC_PUSH_MULT))
5773 /* Routines for use in generating RTL. */
5776 arm_gen_load_multiple (int base_regno, int count, rtx from, int up,
5777 int write_back, int unchanging_p, int in_struct_p,
5782 int sign = up ? 1 : -1;
5785 /* XScale has load-store double instructions, but they have stricter
5786 alignment requirements than load-store multiple, so we can not
5789 For XScale ldm requires 2 + NREGS cycles to complete and blocks
5790 the pipeline until completion.
5798 An ldr instruction takes 1-3 cycles, but does not block the
5807 Best case ldr will always win. However, the more ldr instructions
5808 we issue, the less likely we are to be able to schedule them well.
5809 Using ldr instructions also increases code size.
5811 As a compromise, we use ldr for counts of 1 or 2 regs, and ldm
5812 for counts of 3 or 4 regs. */
5813 if (arm_tune_xscale && count <= 2 && ! optimize_size)
5819 for (i = 0; i < count; i++)
5821 mem = gen_rtx_MEM (SImode, plus_constant (from, i * 4 * sign));
5822 RTX_UNCHANGING_P (mem) = unchanging_p;
5823 MEM_IN_STRUCT_P (mem) = in_struct_p;
5824 MEM_SCALAR_P (mem) = scalar_p;
5825 emit_move_insn (gen_rtx_REG (SImode, base_regno + i), mem);
5829 emit_move_insn (from, plus_constant (from, count * 4 * sign));
5837 result = gen_rtx_PARALLEL (VOIDmode,
5838 rtvec_alloc (count + (write_back ? 1 : 0)));
5841 XVECEXP (result, 0, 0)
5842 = gen_rtx_SET (GET_MODE (from), from,
5843 plus_constant (from, count * 4 * sign));
5848 for (j = 0; i < count; i++, j++)
5850 mem = gen_rtx_MEM (SImode, plus_constant (from, j * 4 * sign));
5851 RTX_UNCHANGING_P (mem) = unchanging_p;
5852 MEM_IN_STRUCT_P (mem) = in_struct_p;
5853 MEM_SCALAR_P (mem) = scalar_p;
5854 XVECEXP (result, 0, i)
5855 = gen_rtx_SET (VOIDmode, gen_rtx_REG (SImode, base_regno + j), mem);
5862 arm_gen_store_multiple (int base_regno, int count, rtx to, int up,
5863 int write_back, int unchanging_p, int in_struct_p,
5868 int sign = up ? 1 : -1;
5871 /* See arm_gen_load_multiple for discussion of
5872 the pros/cons of ldm/stm usage for XScale. */
5873 if (arm_tune_xscale && count <= 2 && ! optimize_size)
5879 for (i = 0; i < count; i++)
5881 mem = gen_rtx_MEM (SImode, plus_constant (to, i * 4 * sign));
5882 RTX_UNCHANGING_P (mem) = unchanging_p;
5883 MEM_IN_STRUCT_P (mem) = in_struct_p;
5884 MEM_SCALAR_P (mem) = scalar_p;
5885 emit_move_insn (mem, gen_rtx_REG (SImode, base_regno + i));
5889 emit_move_insn (to, plus_constant (to, count * 4 * sign));
5897 result = gen_rtx_PARALLEL (VOIDmode,
5898 rtvec_alloc (count + (write_back ? 1 : 0)));
5901 XVECEXP (result, 0, 0)
5902 = gen_rtx_SET (GET_MODE (to), to,
5903 plus_constant (to, count * 4 * sign));
5908 for (j = 0; i < count; i++, j++)
5910 mem = gen_rtx_MEM (SImode, plus_constant (to, j * 4 * sign));
5911 RTX_UNCHANGING_P (mem) = unchanging_p;
5912 MEM_IN_STRUCT_P (mem) = in_struct_p;
5913 MEM_SCALAR_P (mem) = scalar_p;
5915 XVECEXP (result, 0, i)
5916 = gen_rtx_SET (VOIDmode, mem, gen_rtx_REG (SImode, base_regno + j));
5923 arm_gen_movstrqi (rtx *operands)
5925 HOST_WIDE_INT in_words_to_go, out_words_to_go, last_bytes;
5928 rtx st_src, st_dst, fin_src, fin_dst;
5929 rtx part_bytes_reg = NULL;
5931 int dst_unchanging_p, dst_in_struct_p, src_unchanging_p, src_in_struct_p;
5932 int dst_scalar_p, src_scalar_p;
5934 if (GET_CODE (operands[2]) != CONST_INT
5935 || GET_CODE (operands[3]) != CONST_INT
5936 || INTVAL (operands[2]) > 64
5937 || INTVAL (operands[3]) & 3)
5940 st_dst = XEXP (operands[0], 0);
5941 st_src = XEXP (operands[1], 0);
5943 dst_unchanging_p = RTX_UNCHANGING_P (operands[0]);
5944 dst_in_struct_p = MEM_IN_STRUCT_P (operands[0]);
5945 dst_scalar_p = MEM_SCALAR_P (operands[0]);
5946 src_unchanging_p = RTX_UNCHANGING_P (operands[1]);
5947 src_in_struct_p = MEM_IN_STRUCT_P (operands[1]);
5948 src_scalar_p = MEM_SCALAR_P (operands[1]);
5950 fin_dst = dst = copy_to_mode_reg (SImode, st_dst);
5951 fin_src = src = copy_to_mode_reg (SImode, st_src);
5953 in_words_to_go = ARM_NUM_INTS (INTVAL (operands[2]));
5954 out_words_to_go = INTVAL (operands[2]) / 4;
5955 last_bytes = INTVAL (operands[2]) & 3;
5957 if (out_words_to_go != in_words_to_go && ((in_words_to_go - 1) & 3) != 0)
5958 part_bytes_reg = gen_rtx_REG (SImode, (in_words_to_go - 1) & 3);
5960 for (i = 0; in_words_to_go >= 2; i+=4)
5962 if (in_words_to_go > 4)
5963 emit_insn (arm_gen_load_multiple (0, 4, src, TRUE, TRUE,
5968 emit_insn (arm_gen_load_multiple (0, in_words_to_go, src, TRUE,
5969 FALSE, src_unchanging_p,
5970 src_in_struct_p, src_scalar_p));
5972 if (out_words_to_go)
5974 if (out_words_to_go > 4)
5975 emit_insn (arm_gen_store_multiple (0, 4, dst, TRUE, TRUE,
5979 else if (out_words_to_go != 1)
5980 emit_insn (arm_gen_store_multiple (0, out_words_to_go,
5989 mem = gen_rtx_MEM (SImode, dst);
5990 RTX_UNCHANGING_P (mem) = dst_unchanging_p;
5991 MEM_IN_STRUCT_P (mem) = dst_in_struct_p;
5992 MEM_SCALAR_P (mem) = dst_scalar_p;
5993 emit_move_insn (mem, gen_rtx_REG (SImode, 0));
5994 if (last_bytes != 0)
5995 emit_insn (gen_addsi3 (dst, dst, GEN_INT (4)));
5999 in_words_to_go -= in_words_to_go < 4 ? in_words_to_go : 4;
6000 out_words_to_go -= out_words_to_go < 4 ? out_words_to_go : 4;
6003 /* OUT_WORDS_TO_GO will be zero here if there are byte stores to do. */
6004 if (out_words_to_go)
6008 mem = gen_rtx_MEM (SImode, src);
6009 RTX_UNCHANGING_P (mem) = src_unchanging_p;
6010 MEM_IN_STRUCT_P (mem) = src_in_struct_p;
6011 MEM_SCALAR_P (mem) = src_scalar_p;
6012 emit_move_insn (sreg = gen_reg_rtx (SImode), mem);
6013 emit_move_insn (fin_src = gen_reg_rtx (SImode), plus_constant (src, 4));
6015 mem = gen_rtx_MEM (SImode, dst);
6016 RTX_UNCHANGING_P (mem) = dst_unchanging_p;
6017 MEM_IN_STRUCT_P (mem) = dst_in_struct_p;
6018 MEM_SCALAR_P (mem) = dst_scalar_p;
6019 emit_move_insn (mem, sreg);
6020 emit_move_insn (fin_dst = gen_reg_rtx (SImode), plus_constant (dst, 4));
6023 if (in_words_to_go) /* Sanity check */
6029 if (in_words_to_go < 0)
6032 mem = gen_rtx_MEM (SImode, src);
6033 RTX_UNCHANGING_P (mem) = src_unchanging_p;
6034 MEM_IN_STRUCT_P (mem) = src_in_struct_p;
6035 MEM_SCALAR_P (mem) = src_scalar_p;
6036 part_bytes_reg = copy_to_mode_reg (SImode, mem);
6039 if (last_bytes && part_bytes_reg == NULL)
6042 if (BYTES_BIG_ENDIAN && last_bytes)
6044 rtx tmp = gen_reg_rtx (SImode);
6046 /* The bytes we want are in the top end of the word. */
6047 emit_insn (gen_lshrsi3 (tmp, part_bytes_reg,
6048 GEN_INT (8 * (4 - last_bytes))));
6049 part_bytes_reg = tmp;
6053 mem = gen_rtx_MEM (QImode, plus_constant (dst, last_bytes - 1));
6054 RTX_UNCHANGING_P (mem) = dst_unchanging_p;
6055 MEM_IN_STRUCT_P (mem) = dst_in_struct_p;
6056 MEM_SCALAR_P (mem) = dst_scalar_p;
6057 emit_move_insn (mem, gen_lowpart (QImode, part_bytes_reg));
6061 tmp = gen_reg_rtx (SImode);
6062 emit_insn (gen_lshrsi3 (tmp, part_bytes_reg, GEN_INT (8)));
6063 part_bytes_reg = tmp;
6072 mem = gen_rtx_MEM (HImode, dst);
6073 RTX_UNCHANGING_P (mem) = dst_unchanging_p;
6074 MEM_IN_STRUCT_P (mem) = dst_in_struct_p;
6075 MEM_SCALAR_P (mem) = dst_scalar_p;
6076 emit_move_insn (mem, gen_lowpart (HImode, part_bytes_reg));
6080 rtx tmp = gen_reg_rtx (SImode);
6082 emit_insn (gen_addsi3 (dst, dst, const2_rtx));
6083 emit_insn (gen_lshrsi3 (tmp, part_bytes_reg, GEN_INT (16)));
6084 part_bytes_reg = tmp;
6090 mem = gen_rtx_MEM (QImode, dst);
6091 RTX_UNCHANGING_P (mem) = dst_unchanging_p;
6092 MEM_IN_STRUCT_P (mem) = dst_in_struct_p;
6093 MEM_SCALAR_P (mem) = dst_scalar_p;
6094 emit_move_insn (mem, gen_lowpart (QImode, part_bytes_reg));
6101 /* Generate a memory reference for a half word, such that it will be loaded
6102 into the top 16 bits of the word. We can assume that the address is
6103 known to be alignable and of the form reg, or plus (reg, const). */
6106 arm_gen_rotated_half_load (rtx memref)
6108 HOST_WIDE_INT offset = 0;
6109 rtx base = XEXP (memref, 0);
6111 if (GET_CODE (base) == PLUS)
6113 offset = INTVAL (XEXP (base, 1));
6114 base = XEXP (base, 0);
6117 /* If we aren't allowed to generate unaligned addresses, then fail. */
6118 if (TARGET_MMU_TRAPS
6119 && ((BYTES_BIG_ENDIAN ? 1 : 0) ^ ((offset & 2) == 0)))
6122 base = gen_rtx_MEM (SImode, plus_constant (base, offset & ~2));
6124 if ((BYTES_BIG_ENDIAN ? 1 : 0) ^ ((offset & 2) == 2))
6127 return gen_rtx_ROTATE (SImode, base, GEN_INT (16));
6130 /* Select a dominance comparison mode if possible for a test of the general
6131 form (OP (COND_OR (X) (Y)) (const_int 0)). We support three forms.
6132 COND_OR == DOM_CC_X_AND_Y => (X && Y)
6133 COND_OR == DOM_CC_NX_OR_Y => ((! X) || Y)
6134 COND_OR == DOM_CC_X_OR_Y => (X || Y)
6135 In all cases OP will be either EQ or NE, but we don't need to know which
6136 here. If we are unable to support a dominance comparison we return
6137 CC mode. This will then fail to match for the RTL expressions that
6138 generate this call. */
6140 arm_select_dominance_cc_mode (rtx x, rtx y, HOST_WIDE_INT cond_or)
6142 enum rtx_code cond1, cond2;
6145 /* Currently we will probably get the wrong result if the individual
6146 comparisons are not simple. This also ensures that it is safe to
6147 reverse a comparison if necessary. */
6148 if ((arm_select_cc_mode (cond1 = GET_CODE (x), XEXP (x, 0), XEXP (x, 1))
6150 || (arm_select_cc_mode (cond2 = GET_CODE (y), XEXP (y, 0), XEXP (y, 1))
6154 /* The if_then_else variant of this tests the second condition if the
6155 first passes, but is true if the first fails. Reverse the first
6156 condition to get a true "inclusive-or" expression. */
6157 if (cond_or == DOM_CC_NX_OR_Y)
6158 cond1 = reverse_condition (cond1);
6160 /* If the comparisons are not equal, and one doesn't dominate the other,
6161 then we can't do this. */
6163 && !comparison_dominates_p (cond1, cond2)
6164 && (swapped = 1, !comparison_dominates_p (cond2, cond1)))
6169 enum rtx_code temp = cond1;
6177 if (cond2 == EQ || cond_or == DOM_CC_X_AND_Y)
6182 case LE: return CC_DLEmode;
6183 case LEU: return CC_DLEUmode;
6184 case GE: return CC_DGEmode;
6185 case GEU: return CC_DGEUmode;
6192 if (cond2 == LT || cond_or == DOM_CC_X_AND_Y)
6201 if (cond2 == GT || cond_or == DOM_CC_X_AND_Y)
6210 if (cond2 == LTU || cond_or == DOM_CC_X_AND_Y)
6219 if (cond2 == GTU || cond_or == DOM_CC_X_AND_Y)
6227 /* The remaining cases only occur when both comparisons are the
6252 arm_select_cc_mode (enum rtx_code op, rtx x, rtx y)
6254 /* All floating point compares return CCFP if it is an equality
6255 comparison, and CCFPE otherwise. */
6256 if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
6276 if (TARGET_HARD_FLOAT && TARGET_MAVERICK)
6285 /* A compare with a shifted operand. Because of canonicalization, the
6286 comparison will have to be swapped when we emit the assembler. */
6287 if (GET_MODE (y) == SImode && GET_CODE (y) == REG
6288 && (GET_CODE (x) == ASHIFT || GET_CODE (x) == ASHIFTRT
6289 || GET_CODE (x) == LSHIFTRT || GET_CODE (x) == ROTATE
6290 || GET_CODE (x) == ROTATERT))
6293 /* This is a special case that is used by combine to allow a
6294 comparison of a shifted byte load to be split into a zero-extend
6295 followed by a comparison of the shifted integer (only valid for
6296 equalities and unsigned inequalities). */
6297 if (GET_MODE (x) == SImode
6298 && GET_CODE (x) == ASHIFT
6299 && GET_CODE (XEXP (x, 1)) == CONST_INT && INTVAL (XEXP (x, 1)) == 24
6300 && GET_CODE (XEXP (x, 0)) == SUBREG
6301 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == MEM
6302 && GET_MODE (SUBREG_REG (XEXP (x, 0))) == QImode
6303 && (op == EQ || op == NE
6304 || op == GEU || op == GTU || op == LTU || op == LEU)
6305 && GET_CODE (y) == CONST_INT)
6308 /* A construct for a conditional compare, if the false arm contains
6309 0, then both conditions must be true, otherwise either condition
6310 must be true. Not all conditions are possible, so CCmode is
6311 returned if it can't be done. */
6312 if (GET_CODE (x) == IF_THEN_ELSE
6313 && (XEXP (x, 2) == const0_rtx
6314 || XEXP (x, 2) == const1_rtx)
6315 && COMPARISON_P (XEXP (x, 0))
6316 && COMPARISON_P (XEXP (x, 1)))
6317 return arm_select_dominance_cc_mode (XEXP (x, 0), XEXP (x, 1),
6318 INTVAL (XEXP (x, 2)));
6320 /* Alternate canonicalizations of the above. These are somewhat cleaner. */
6321 if (GET_CODE (x) == AND
6322 && COMPARISON_P (XEXP (x, 0))
6323 && COMPARISON_P (XEXP (x, 1)))
6324 return arm_select_dominance_cc_mode (XEXP (x, 0), XEXP (x, 1),
6327 if (GET_CODE (x) == IOR
6328 && COMPARISON_P (XEXP (x, 0))
6329 && COMPARISON_P (XEXP (x, 1)))
6330 return arm_select_dominance_cc_mode (XEXP (x, 0), XEXP (x, 1),
6333 /* An operation (on Thumb) where we want to test for a single bit.
6334 This is done by shifting that bit up into the top bit of a
6335 scratch register; we can then branch on the sign bit. */
6337 && GET_MODE (x) == SImode
6338 && (op == EQ || op == NE)
6339 && (GET_CODE (x) == ZERO_EXTRACT))
6342 /* An operation that sets the condition codes as a side-effect, the
6343 V flag is not set correctly, so we can only use comparisons where
6344 this doesn't matter. (For LT and GE we can use "mi" and "pl"
6346 if (GET_MODE (x) == SImode
6348 && (op == EQ || op == NE || op == LT || op == GE)
6349 && (GET_CODE (x) == PLUS || GET_CODE (x) == MINUS
6350 || GET_CODE (x) == AND || GET_CODE (x) == IOR
6351 || GET_CODE (x) == XOR || GET_CODE (x) == MULT
6352 || GET_CODE (x) == NOT || GET_CODE (x) == NEG
6353 || GET_CODE (x) == LSHIFTRT
6354 || GET_CODE (x) == ASHIFT || GET_CODE (x) == ASHIFTRT
6355 || GET_CODE (x) == ROTATERT
6356 || (TARGET_ARM && GET_CODE (x) == ZERO_EXTRACT)))
6359 if (GET_MODE (x) == QImode && (op == EQ || op == NE))
6362 if (GET_MODE (x) == SImode && (op == LTU || op == GEU)
6363 && GET_CODE (x) == PLUS
6364 && (rtx_equal_p (XEXP (x, 0), y) || rtx_equal_p (XEXP (x, 1), y)))
6370 /* X and Y are two things to compare using CODE. Emit the compare insn and
6371 return the rtx for register 0 in the proper mode. FP means this is a
6372 floating point compare: I don't think that it is needed on the arm. */
6374 arm_gen_compare_reg (enum rtx_code code, rtx x, rtx y)
6376 enum machine_mode mode = SELECT_CC_MODE (code, x, y);
6377 rtx cc_reg = gen_rtx_REG (mode, CC_REGNUM);
6379 emit_insn (gen_rtx_SET (VOIDmode, cc_reg,
6380 gen_rtx_COMPARE (mode, x, y)));
6385 /* Generate a sequence of insns that will generate the correct return
6386 address mask depending on the physical architecture that the program
6389 arm_gen_return_addr_mask (void)
6391 rtx reg = gen_reg_rtx (Pmode);
6393 emit_insn (gen_return_addr_mask (reg));
6398 arm_reload_in_hi (rtx *operands)
6400 rtx ref = operands[1];
6402 HOST_WIDE_INT offset = 0;
6404 if (GET_CODE (ref) == SUBREG)
6406 offset = SUBREG_BYTE (ref);
6407 ref = SUBREG_REG (ref);
6410 if (GET_CODE (ref) == REG)
6412 /* We have a pseudo which has been spilt onto the stack; there
6413 are two cases here: the first where there is a simple
6414 stack-slot replacement and a second where the stack-slot is
6415 out of range, or is used as a subreg. */
6416 if (reg_equiv_mem[REGNO (ref)])
6418 ref = reg_equiv_mem[REGNO (ref)];
6419 base = find_replacement (&XEXP (ref, 0));
6422 /* The slot is out of range, or was dressed up in a SUBREG. */
6423 base = reg_equiv_address[REGNO (ref)];
6426 base = find_replacement (&XEXP (ref, 0));
6428 /* Handle the case where the address is too complex to be offset by 1. */
6429 if (GET_CODE (base) == MINUS
6430 || (GET_CODE (base) == PLUS && GET_CODE (XEXP (base, 1)) != CONST_INT))
6432 rtx base_plus = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
6434 emit_insn (gen_rtx_SET (VOIDmode, base_plus, base));
6437 else if (GET_CODE (base) == PLUS)
6439 /* The addend must be CONST_INT, or we would have dealt with it above. */
6440 HOST_WIDE_INT hi, lo;
6442 offset += INTVAL (XEXP (base, 1));
6443 base = XEXP (base, 0);
6445 /* Rework the address into a legal sequence of insns. */
6446 /* Valid range for lo is -4095 -> 4095 */
6449 : -((-offset) & 0xfff));
6451 /* Corner case, if lo is the max offset then we would be out of range
6452 once we have added the additional 1 below, so bump the msb into the
6453 pre-loading insn(s). */
6457 hi = ((((offset - lo) & (HOST_WIDE_INT) 0xffffffff)
6458 ^ (HOST_WIDE_INT) 0x80000000)
6459 - (HOST_WIDE_INT) 0x80000000);
6461 if (hi + lo != offset)
6466 rtx base_plus = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
6468 /* Get the base address; addsi3 knows how to handle constants
6469 that require more than one insn. */
6470 emit_insn (gen_addsi3 (base_plus, base, GEN_INT (hi)));
6476 /* Operands[2] may overlap operands[0] (though it won't overlap
6477 operands[1]), that's why we asked for a DImode reg -- so we can
6478 use the bit that does not overlap. */
6479 if (REGNO (operands[2]) == REGNO (operands[0]))
6480 scratch = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
6482 scratch = gen_rtx_REG (SImode, REGNO (operands[2]));
6484 emit_insn (gen_zero_extendqisi2 (scratch,
6485 gen_rtx_MEM (QImode,
6486 plus_constant (base,
6488 emit_insn (gen_zero_extendqisi2 (gen_rtx_SUBREG (SImode, operands[0], 0),
6489 gen_rtx_MEM (QImode,
6490 plus_constant (base,
6492 if (!BYTES_BIG_ENDIAN)
6493 emit_insn (gen_rtx_SET (VOIDmode, gen_rtx_SUBREG (SImode, operands[0], 0),
6494 gen_rtx_IOR (SImode,
6497 gen_rtx_SUBREG (SImode, operands[0], 0),
6501 emit_insn (gen_rtx_SET (VOIDmode, gen_rtx_SUBREG (SImode, operands[0], 0),
6502 gen_rtx_IOR (SImode,
6503 gen_rtx_ASHIFT (SImode, scratch,
6505 gen_rtx_SUBREG (SImode, operands[0],
6509 /* Handle storing a half-word to memory during reload by synthesizing as two
6510 byte stores. Take care not to clobber the input values until after we
6511 have moved them somewhere safe. This code assumes that if the DImode
6512 scratch in operands[2] overlaps either the input value or output address
6513 in some way, then that value must die in this insn (we absolutely need
6514 two scratch registers for some corner cases). */
6516 arm_reload_out_hi (rtx *operands)
6518 rtx ref = operands[0];
6519 rtx outval = operands[1];
6521 HOST_WIDE_INT offset = 0;
6523 if (GET_CODE (ref) == SUBREG)
6525 offset = SUBREG_BYTE (ref);
6526 ref = SUBREG_REG (ref);
6529 if (GET_CODE (ref) == REG)
6531 /* We have a pseudo which has been spilt onto the stack; there
6532 are two cases here: the first where there is a simple
6533 stack-slot replacement and a second where the stack-slot is
6534 out of range, or is used as a subreg. */
6535 if (reg_equiv_mem[REGNO (ref)])
6537 ref = reg_equiv_mem[REGNO (ref)];
6538 base = find_replacement (&XEXP (ref, 0));
6541 /* The slot is out of range, or was dressed up in a SUBREG. */
6542 base = reg_equiv_address[REGNO (ref)];
6545 base = find_replacement (&XEXP (ref, 0));
6547 scratch = gen_rtx_REG (SImode, REGNO (operands[2]));
6549 /* Handle the case where the address is too complex to be offset by 1. */
6550 if (GET_CODE (base) == MINUS
6551 || (GET_CODE (base) == PLUS && GET_CODE (XEXP (base, 1)) != CONST_INT))
6553 rtx base_plus = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
6555 /* Be careful not to destroy OUTVAL. */
6556 if (reg_overlap_mentioned_p (base_plus, outval))
6558 /* Updating base_plus might destroy outval, see if we can
6559 swap the scratch and base_plus. */
6560 if (!reg_overlap_mentioned_p (scratch, outval))
6563 scratch = base_plus;
6568 rtx scratch_hi = gen_rtx_REG (HImode, REGNO (operands[2]));
6570 /* Be conservative and copy OUTVAL into the scratch now,
6571 this should only be necessary if outval is a subreg
6572 of something larger than a word. */
6573 /* XXX Might this clobber base? I can't see how it can,
6574 since scratch is known to overlap with OUTVAL, and
6575 must be wider than a word. */
6576 emit_insn (gen_movhi (scratch_hi, outval));
6577 outval = scratch_hi;
6581 emit_insn (gen_rtx_SET (VOIDmode, base_plus, base));
6584 else if (GET_CODE (base) == PLUS)
6586 /* The addend must be CONST_INT, or we would have dealt with it above. */
6587 HOST_WIDE_INT hi, lo;
6589 offset += INTVAL (XEXP (base, 1));
6590 base = XEXP (base, 0);
6592 /* Rework the address into a legal sequence of insns. */
6593 /* Valid range for lo is -4095 -> 4095 */
6596 : -((-offset) & 0xfff));
6598 /* Corner case, if lo is the max offset then we would be out of range
6599 once we have added the additional 1 below, so bump the msb into the
6600 pre-loading insn(s). */
6604 hi = ((((offset - lo) & (HOST_WIDE_INT) 0xffffffff)
6605 ^ (HOST_WIDE_INT) 0x80000000)
6606 - (HOST_WIDE_INT) 0x80000000);
6608 if (hi + lo != offset)
6613 rtx base_plus = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
6615 /* Be careful not to destroy OUTVAL. */
6616 if (reg_overlap_mentioned_p (base_plus, outval))
6618 /* Updating base_plus might destroy outval, see if we
6619 can swap the scratch and base_plus. */
6620 if (!reg_overlap_mentioned_p (scratch, outval))
6623 scratch = base_plus;
6628 rtx scratch_hi = gen_rtx_REG (HImode, REGNO (operands[2]));
6630 /* Be conservative and copy outval into scratch now,
6631 this should only be necessary if outval is a
6632 subreg of something larger than a word. */
6633 /* XXX Might this clobber base? I can't see how it
6634 can, since scratch is known to overlap with
6636 emit_insn (gen_movhi (scratch_hi, outval));
6637 outval = scratch_hi;
6641 /* Get the base address; addsi3 knows how to handle constants
6642 that require more than one insn. */
6643 emit_insn (gen_addsi3 (base_plus, base, GEN_INT (hi)));
6649 if (BYTES_BIG_ENDIAN)
6651 emit_insn (gen_movqi (gen_rtx_MEM (QImode,
6652 plus_constant (base, offset + 1)),
6653 gen_lowpart (QImode, outval)));
6654 emit_insn (gen_lshrsi3 (scratch,
6655 gen_rtx_SUBREG (SImode, outval, 0),
6657 emit_insn (gen_movqi (gen_rtx_MEM (QImode, plus_constant (base, offset)),
6658 gen_lowpart (QImode, scratch)));
6662 emit_insn (gen_movqi (gen_rtx_MEM (QImode, plus_constant (base, offset)),
6663 gen_lowpart (QImode, outval)));
6664 emit_insn (gen_lshrsi3 (scratch,
6665 gen_rtx_SUBREG (SImode, outval, 0),
6667 emit_insn (gen_movqi (gen_rtx_MEM (QImode,
6668 plus_constant (base, offset + 1)),
6669 gen_lowpart (QImode, scratch)));
6673 /* Print a symbolic form of X to the debug file, F. */
6675 arm_print_value (FILE *f, rtx x)
6677 switch (GET_CODE (x))
6680 fprintf (f, HOST_WIDE_INT_PRINT_HEX, INTVAL (x));
6684 fprintf (f, "<0x%lx,0x%lx>", (long)XWINT (x, 2), (long)XWINT (x, 3));
6692 for (i = 0; i < CONST_VECTOR_NUNITS (x); i++)
6694 fprintf (f, HOST_WIDE_INT_PRINT_HEX, INTVAL (CONST_VECTOR_ELT (x, i)));
6695 if (i < (CONST_VECTOR_NUNITS (x) - 1))
6703 fprintf (f, "\"%s\"", XSTR (x, 0));
6707 fprintf (f, "`%s'", XSTR (x, 0));
6711 fprintf (f, "L%d", INSN_UID (XEXP (x, 0)));
6715 arm_print_value (f, XEXP (x, 0));
6719 arm_print_value (f, XEXP (x, 0));
6721 arm_print_value (f, XEXP (x, 1));
6729 fprintf (f, "????");
6734 /* Routines for manipulation of the constant pool. */
6736 /* Arm instructions cannot load a large constant directly into a
6737 register; they have to come from a pc relative load. The constant
6738 must therefore be placed in the addressable range of the pc
6739 relative load. Depending on the precise pc relative load
6740 instruction the range is somewhere between 256 bytes and 4k. This
6741 means that we often have to dump a constant inside a function, and
6742 generate code to branch around it.
6744 It is important to minimize this, since the branches will slow
6745 things down and make the code larger.
6747 Normally we can hide the table after an existing unconditional
6748 branch so that there is no interruption of the flow, but in the
6749 worst case the code looks like this:
6767 We fix this by performing a scan after scheduling, which notices
6768 which instructions need to have their operands fetched from the
6769 constant table and builds the table.
6771 The algorithm starts by building a table of all the constants that
6772 need fixing up and all the natural barriers in the function (places
6773 where a constant table can be dropped without breaking the flow).
6774 For each fixup we note how far the pc-relative replacement will be
6775 able to reach and the offset of the instruction into the function.
6777 Having built the table we then group the fixes together to form
6778 tables that are as large as possible (subject to addressing
6779 constraints) and emit each table of constants after the last
6780 barrier that is within range of all the instructions in the group.
6781 If a group does not contain a barrier, then we forcibly create one
6782 by inserting a jump instruction into the flow. Once the table has
6783 been inserted, the insns are then modified to reference the
6784 relevant entry in the pool.
6786 Possible enhancements to the algorithm (not implemented) are:
6788 1) For some processors and object formats, there may be benefit in
6789 aligning the pools to the start of cache lines; this alignment
6790 would need to be taken into account when calculating addressability
6793 /* These typedefs are located at the start of this file, so that
6794 they can be used in the prototypes there. This comment is to
6795 remind readers of that fact so that the following structures
6796 can be understood more easily.
6798 typedef struct minipool_node Mnode;
6799 typedef struct minipool_fixup Mfix; */
6801 struct minipool_node
6803 /* Doubly linked chain of entries. */
6806 /* The maximum offset into the code that this entry can be placed. While
6807 pushing fixes for forward references, all entries are sorted in order
6808 of increasing max_address. */
6809 HOST_WIDE_INT max_address;
6810 /* Similarly for an entry inserted for a backwards ref. */
6811 HOST_WIDE_INT min_address;
6812 /* The number of fixes referencing this entry. This can become zero
6813 if we "unpush" an entry. In this case we ignore the entry when we
6814 come to emit the code. */
6816 /* The offset from the start of the minipool. */
6817 HOST_WIDE_INT offset;
6818 /* The value in table. */
6820 /* The mode of value. */
6821 enum machine_mode mode;
6822 /* The size of the value. With iWMMXt enabled
6823 sizes > 4 also imply an alignment of 8-bytes. */
6827 struct minipool_fixup
6831 HOST_WIDE_INT address;
6833 enum machine_mode mode;
6837 HOST_WIDE_INT forwards;
6838 HOST_WIDE_INT backwards;
6841 /* Fixes less than a word need padding out to a word boundary. */
6842 #define MINIPOOL_FIX_SIZE(mode) \
6843 (GET_MODE_SIZE ((mode)) >= 4 ? GET_MODE_SIZE ((mode)) : 4)
6845 static Mnode * minipool_vector_head;
6846 static Mnode * minipool_vector_tail;
6847 static rtx minipool_vector_label;
6849 /* The linked list of all minipool fixes required for this function. */
6850 Mfix * minipool_fix_head;
6851 Mfix * minipool_fix_tail;
6852 /* The fix entry for the current minipool, once it has been placed. */
6853 Mfix * minipool_barrier;
6855 /* Determines if INSN is the start of a jump table. Returns the end
6856 of the TABLE or NULL_RTX. */
6858 is_jump_table (rtx insn)
6862 if (GET_CODE (insn) == JUMP_INSN
6863 && JUMP_LABEL (insn) != NULL
6864 && ((table = next_real_insn (JUMP_LABEL (insn)))
6865 == next_real_insn (insn))
6867 && GET_CODE (table) == JUMP_INSN
6868 && (GET_CODE (PATTERN (table)) == ADDR_VEC
6869 || GET_CODE (PATTERN (table)) == ADDR_DIFF_VEC))
6875 #ifndef JUMP_TABLES_IN_TEXT_SECTION
6876 #define JUMP_TABLES_IN_TEXT_SECTION 0
6879 static HOST_WIDE_INT
6880 get_jump_table_size (rtx insn)
6882 /* ADDR_VECs only take room if read-only data does into the text
6884 if (JUMP_TABLES_IN_TEXT_SECTION
6885 #if !defined(READONLY_DATA_SECTION) && !defined(READONLY_DATA_SECTION_ASM_OP)
6890 rtx body = PATTERN (insn);
6891 int elt = GET_CODE (body) == ADDR_DIFF_VEC ? 1 : 0;
6893 return GET_MODE_SIZE (GET_MODE (body)) * XVECLEN (body, elt);
6899 /* Move a minipool fix MP from its current location to before MAX_MP.
6900 If MAX_MP is NULL, then MP doesn't need moving, but the addressing
6901 constraints may need updating. */
6903 move_minipool_fix_forward_ref (Mnode *mp, Mnode *max_mp,
6904 HOST_WIDE_INT max_address)
6906 /* This should never be true and the code below assumes these are
6913 if (max_address < mp->max_address)
6914 mp->max_address = max_address;
6918 if (max_address > max_mp->max_address - mp->fix_size)
6919 mp->max_address = max_mp->max_address - mp->fix_size;
6921 mp->max_address = max_address;
6923 /* Unlink MP from its current position. Since max_mp is non-null,
6924 mp->prev must be non-null. */
6925 mp->prev->next = mp->next;
6926 if (mp->next != NULL)
6927 mp->next->prev = mp->prev;
6929 minipool_vector_tail = mp->prev;
6931 /* Re-insert it before MAX_MP. */
6933 mp->prev = max_mp->prev;
6936 if (mp->prev != NULL)
6937 mp->prev->next = mp;
6939 minipool_vector_head = mp;
6942 /* Save the new entry. */
6945 /* Scan over the preceding entries and adjust their addresses as
6947 while (mp->prev != NULL
6948 && mp->prev->max_address > mp->max_address - mp->prev->fix_size)
6950 mp->prev->max_address = mp->max_address - mp->prev->fix_size;
6957 /* Add a constant to the minipool for a forward reference. Returns the
6958 node added or NULL if the constant will not fit in this pool. */
6960 add_minipool_forward_ref (Mfix *fix)
6962 /* If set, max_mp is the first pool_entry that has a lower
6963 constraint than the one we are trying to add. */
6964 Mnode * max_mp = NULL;
6965 HOST_WIDE_INT max_address = fix->address + fix->forwards;
6968 /* If this fix's address is greater than the address of the first
6969 entry, then we can't put the fix in this pool. We subtract the
6970 size of the current fix to ensure that if the table is fully
6971 packed we still have enough room to insert this value by suffling
6972 the other fixes forwards. */
6973 if (minipool_vector_head &&
6974 fix->address >= minipool_vector_head->max_address - fix->fix_size)
6977 /* Scan the pool to see if a constant with the same value has
6978 already been added. While we are doing this, also note the
6979 location where we must insert the constant if it doesn't already
6981 for (mp = minipool_vector_head; mp != NULL; mp = mp->next)
6983 if (GET_CODE (fix->value) == GET_CODE (mp->value)
6984 && fix->mode == mp->mode
6985 && (GET_CODE (fix->value) != CODE_LABEL
6986 || (CODE_LABEL_NUMBER (fix->value)
6987 == CODE_LABEL_NUMBER (mp->value)))
6988 && rtx_equal_p (fix->value, mp->value))
6990 /* More than one fix references this entry. */
6992 return move_minipool_fix_forward_ref (mp, max_mp, max_address);
6995 /* Note the insertion point if necessary. */
6997 && mp->max_address > max_address)
7000 /* If we are inserting an 8-bytes aligned quantity and
7001 we have not already found an insertion point, then
7002 make sure that all such 8-byte aligned quantities are
7003 placed at the start of the pool. */
7004 if (ARM_DOUBLEWORD_ALIGN
7006 && fix->fix_size == 8
7007 && mp->fix_size != 8)
7010 max_address = mp->max_address;
7014 /* The value is not currently in the minipool, so we need to create
7015 a new entry for it. If MAX_MP is NULL, the entry will be put on
7016 the end of the list since the placement is less constrained than
7017 any existing entry. Otherwise, we insert the new fix before
7018 MAX_MP and, if necessary, adjust the constraints on the other
7020 mp = xmalloc (sizeof (* mp));
7021 mp->fix_size = fix->fix_size;
7022 mp->mode = fix->mode;
7023 mp->value = fix->value;
7025 /* Not yet required for a backwards ref. */
7026 mp->min_address = -65536;
7030 mp->max_address = max_address;
7032 mp->prev = minipool_vector_tail;
7034 if (mp->prev == NULL)
7036 minipool_vector_head = mp;
7037 minipool_vector_label = gen_label_rtx ();
7040 mp->prev->next = mp;
7042 minipool_vector_tail = mp;
7046 if (max_address > max_mp->max_address - mp->fix_size)
7047 mp->max_address = max_mp->max_address - mp->fix_size;
7049 mp->max_address = max_address;
7052 mp->prev = max_mp->prev;
7054 if (mp->prev != NULL)
7055 mp->prev->next = mp;
7057 minipool_vector_head = mp;
7060 /* Save the new entry. */
7063 /* Scan over the preceding entries and adjust their addresses as
7065 while (mp->prev != NULL
7066 && mp->prev->max_address > mp->max_address - mp->prev->fix_size)
7068 mp->prev->max_address = mp->max_address - mp->prev->fix_size;
7076 move_minipool_fix_backward_ref (Mnode *mp, Mnode *min_mp,
7077 HOST_WIDE_INT min_address)
7079 HOST_WIDE_INT offset;
7081 /* This should never be true, and the code below assumes these are
7088 if (min_address > mp->min_address)
7089 mp->min_address = min_address;
7093 /* We will adjust this below if it is too loose. */
7094 mp->min_address = min_address;
7096 /* Unlink MP from its current position. Since min_mp is non-null,
7097 mp->next must be non-null. */
7098 mp->next->prev = mp->prev;
7099 if (mp->prev != NULL)
7100 mp->prev->next = mp->next;
7102 minipool_vector_head = mp->next;
7104 /* Reinsert it after MIN_MP. */
7106 mp->next = min_mp->next;
7108 if (mp->next != NULL)
7109 mp->next->prev = mp;
7111 minipool_vector_tail = mp;
7117 for (mp = minipool_vector_head; mp != NULL; mp = mp->next)
7119 mp->offset = offset;
7120 if (mp->refcount > 0)
7121 offset += mp->fix_size;
7123 if (mp->next && mp->next->min_address < mp->min_address + mp->fix_size)
7124 mp->next->min_address = mp->min_address + mp->fix_size;
7130 /* Add a constant to the minipool for a backward reference. Returns the
7131 node added or NULL if the constant will not fit in this pool.
7133 Note that the code for insertion for a backwards reference can be
7134 somewhat confusing because the calculated offsets for each fix do
7135 not take into account the size of the pool (which is still under
7138 add_minipool_backward_ref (Mfix *fix)
7140 /* If set, min_mp is the last pool_entry that has a lower constraint
7141 than the one we are trying to add. */
7142 Mnode *min_mp = NULL;
7143 /* This can be negative, since it is only a constraint. */
7144 HOST_WIDE_INT min_address = fix->address - fix->backwards;
7147 /* If we can't reach the current pool from this insn, or if we can't
7148 insert this entry at the end of the pool without pushing other
7149 fixes out of range, then we don't try. This ensures that we
7150 can't fail later on. */
7151 if (min_address >= minipool_barrier->address
7152 || (minipool_vector_tail->min_address + fix->fix_size
7153 >= minipool_barrier->address))
7156 /* Scan the pool to see if a constant with the same value has
7157 already been added. While we are doing this, also note the
7158 location where we must insert the constant if it doesn't already
7160 for (mp = minipool_vector_tail; mp != NULL; mp = mp->prev)
7162 if (GET_CODE (fix->value) == GET_CODE (mp->value)
7163 && fix->mode == mp->mode
7164 && (GET_CODE (fix->value) != CODE_LABEL
7165 || (CODE_LABEL_NUMBER (fix->value)
7166 == CODE_LABEL_NUMBER (mp->value)))
7167 && rtx_equal_p (fix->value, mp->value)
7168 /* Check that there is enough slack to move this entry to the
7169 end of the table (this is conservative). */
7171 > (minipool_barrier->address
7172 + minipool_vector_tail->offset
7173 + minipool_vector_tail->fix_size)))
7176 return move_minipool_fix_backward_ref (mp, min_mp, min_address);
7180 mp->min_address += fix->fix_size;
7183 /* Note the insertion point if necessary. */
7184 if (mp->min_address < min_address)
7186 /* For now, we do not allow the insertion of 8-byte alignment
7187 requiring nodes anywhere but at the start of the pool. */
7188 if (ARM_DOUBLEWORD_ALIGN
7189 && fix->fix_size == 8 && mp->fix_size != 8)
7194 else if (mp->max_address
7195 < minipool_barrier->address + mp->offset + fix->fix_size)
7197 /* Inserting before this entry would push the fix beyond
7198 its maximum address (which can happen if we have
7199 re-located a forwards fix); force the new fix to come
7202 min_address = mp->min_address + fix->fix_size;
7204 /* If we are inserting an 8-bytes aligned quantity and
7205 we have not already found an insertion point, then
7206 make sure that all such 8-byte aligned quantities are
7207 placed at the start of the pool. */
7208 else if (ARM_DOUBLEWORD_ALIGN
7210 && fix->fix_size == 8
7211 && mp->fix_size < 8)
7214 min_address = mp->min_address + fix->fix_size;
7219 /* We need to create a new entry. */
7220 mp = xmalloc (sizeof (* mp));
7221 mp->fix_size = fix->fix_size;
7222 mp->mode = fix->mode;
7223 mp->value = fix->value;
7225 mp->max_address = minipool_barrier->address + 65536;
7227 mp->min_address = min_address;
7232 mp->next = minipool_vector_head;
7234 if (mp->next == NULL)
7236 minipool_vector_tail = mp;
7237 minipool_vector_label = gen_label_rtx ();
7240 mp->next->prev = mp;
7242 minipool_vector_head = mp;
7246 mp->next = min_mp->next;
7250 if (mp->next != NULL)
7251 mp->next->prev = mp;
7253 minipool_vector_tail = mp;
7256 /* Save the new entry. */
7264 /* Scan over the following entries and adjust their offsets. */
7265 while (mp->next != NULL)
7267 if (mp->next->min_address < mp->min_address + mp->fix_size)
7268 mp->next->min_address = mp->min_address + mp->fix_size;
7271 mp->next->offset = mp->offset + mp->fix_size;
7273 mp->next->offset = mp->offset;
7282 assign_minipool_offsets (Mfix *barrier)
7284 HOST_WIDE_INT offset = 0;
7287 minipool_barrier = barrier;
7289 for (mp = minipool_vector_head; mp != NULL; mp = mp->next)
7291 mp->offset = offset;
7293 if (mp->refcount > 0)
7294 offset += mp->fix_size;
7298 /* Output the literal table */
7300 dump_minipool (rtx scan)
7306 if (ARM_DOUBLEWORD_ALIGN)
7307 for (mp = minipool_vector_head; mp != NULL; mp = mp->next)
7308 if (mp->refcount > 0 && mp->fix_size == 8)
7316 ";; Emitting minipool after insn %u; address %ld; align %d (bytes)\n",
7317 INSN_UID (scan), (unsigned long) minipool_barrier->address, align64 ? 8 : 4);
7319 scan = emit_label_after (gen_label_rtx (), scan);
7320 scan = emit_insn_after (align64 ? gen_align_8 () : gen_align_4 (), scan);
7321 scan = emit_label_after (minipool_vector_label, scan);
7323 for (mp = minipool_vector_head; mp != NULL; mp = nmp)
7325 if (mp->refcount > 0)
7330 ";; Offset %u, min %ld, max %ld ",
7331 (unsigned) mp->offset, (unsigned long) mp->min_address,
7332 (unsigned long) mp->max_address);
7333 arm_print_value (dump_file, mp->value);
7334 fputc ('\n', dump_file);
7337 switch (mp->fix_size)
7339 #ifdef HAVE_consttable_1
7341 scan = emit_insn_after (gen_consttable_1 (mp->value), scan);
7345 #ifdef HAVE_consttable_2
7347 scan = emit_insn_after (gen_consttable_2 (mp->value), scan);
7351 #ifdef HAVE_consttable_4
7353 scan = emit_insn_after (gen_consttable_4 (mp->value), scan);
7357 #ifdef HAVE_consttable_8
7359 scan = emit_insn_after (gen_consttable_8 (mp->value), scan);
7373 minipool_vector_head = minipool_vector_tail = NULL;
7374 scan = emit_insn_after (gen_consttable_end (), scan);
7375 scan = emit_barrier_after (scan);
7378 /* Return the cost of forcibly inserting a barrier after INSN. */
7380 arm_barrier_cost (rtx insn)
7382 /* Basing the location of the pool on the loop depth is preferable,
7383 but at the moment, the basic block information seems to be
7384 corrupt by this stage of the compilation. */
7386 rtx next = next_nonnote_insn (insn);
7388 if (next != NULL && GET_CODE (next) == CODE_LABEL)
7391 switch (GET_CODE (insn))
7394 /* It will always be better to place the table before the label, rather
7403 return base_cost - 10;
7406 return base_cost + 10;
7410 /* Find the best place in the insn stream in the range
7411 (FIX->address,MAX_ADDRESS) to forcibly insert a minipool barrier.
7412 Create the barrier by inserting a jump and add a new fix entry for
7415 create_fix_barrier (Mfix *fix, HOST_WIDE_INT max_address)
7417 HOST_WIDE_INT count = 0;
7419 rtx from = fix->insn;
7420 rtx selected = from;
7422 HOST_WIDE_INT selected_address;
7424 HOST_WIDE_INT max_count = max_address - fix->address;
7425 rtx label = gen_label_rtx ();
7427 selected_cost = arm_barrier_cost (from);
7428 selected_address = fix->address;
7430 while (from && count < max_count)
7435 /* This code shouldn't have been called if there was a natural barrier
7437 if (GET_CODE (from) == BARRIER)
7440 /* Count the length of this insn. */
7441 count += get_attr_length (from);
7443 /* If there is a jump table, add its length. */
7444 tmp = is_jump_table (from);
7447 count += get_jump_table_size (tmp);
7449 /* Jump tables aren't in a basic block, so base the cost on
7450 the dispatch insn. If we select this location, we will
7451 still put the pool after the table. */
7452 new_cost = arm_barrier_cost (from);
7454 if (count < max_count && new_cost <= selected_cost)
7457 selected_cost = new_cost;
7458 selected_address = fix->address + count;
7461 /* Continue after the dispatch table. */
7462 from = NEXT_INSN (tmp);
7466 new_cost = arm_barrier_cost (from);
7468 if (count < max_count && new_cost <= selected_cost)
7471 selected_cost = new_cost;
7472 selected_address = fix->address + count;
7475 from = NEXT_INSN (from);
7478 /* Create a new JUMP_INSN that branches around a barrier. */
7479 from = emit_jump_insn_after (gen_jump (label), selected);
7480 JUMP_LABEL (from) = label;
7481 barrier = emit_barrier_after (from);
7482 emit_label_after (label, barrier);
7484 /* Create a minipool barrier entry for the new barrier. */
7485 new_fix = (Mfix *) obstack_alloc (&minipool_obstack, sizeof (* new_fix));
7486 new_fix->insn = barrier;
7487 new_fix->address = selected_address;
7488 new_fix->next = fix->next;
7489 fix->next = new_fix;
7494 /* Record that there is a natural barrier in the insn stream at
7497 push_minipool_barrier (rtx insn, HOST_WIDE_INT address)
7499 Mfix * fix = (Mfix *) obstack_alloc (&minipool_obstack, sizeof (* fix));
7502 fix->address = address;
7505 if (minipool_fix_head != NULL)
7506 minipool_fix_tail->next = fix;
7508 minipool_fix_head = fix;
7510 minipool_fix_tail = fix;
7513 /* Record INSN, which will need fixing up to load a value from the
7514 minipool. ADDRESS is the offset of the insn since the start of the
7515 function; LOC is a pointer to the part of the insn which requires
7516 fixing; VALUE is the constant that must be loaded, which is of type
7519 push_minipool_fix (rtx insn, HOST_WIDE_INT address, rtx *loc,
7520 enum machine_mode mode, rtx value)
7522 Mfix * fix = (Mfix *) obstack_alloc (&minipool_obstack, sizeof (* fix));
7524 #ifdef AOF_ASSEMBLER
7525 /* PIC symbol references need to be converted into offsets into the
7527 /* XXX This shouldn't be done here. */
7528 if (flag_pic && GET_CODE (value) == SYMBOL_REF)
7529 value = aof_pic_entry (value);
7530 #endif /* AOF_ASSEMBLER */
7533 fix->address = address;
7536 fix->fix_size = MINIPOOL_FIX_SIZE (mode);
7538 fix->forwards = get_attr_pool_range (insn);
7539 fix->backwards = get_attr_neg_pool_range (insn);
7540 fix->minipool = NULL;
7542 /* If an insn doesn't have a range defined for it, then it isn't
7543 expecting to be reworked by this code. Better to abort now than
7544 to generate duff assembly code. */
7545 if (fix->forwards == 0 && fix->backwards == 0)
7548 /* With AAPCS/iWMMXt enabled, the pool is aligned to an 8-byte boundary.
7549 So there might be an empty word before the start of the pool.
7550 Hence we reduce the forward range by 4 to allow for this
7552 if (ARM_DOUBLEWORD_ALIGN && fix->fix_size == 8)
7558 ";; %smode fixup for i%d; addr %lu, range (%ld,%ld): ",
7559 GET_MODE_NAME (mode),
7560 INSN_UID (insn), (unsigned long) address,
7561 -1 * (long)fix->backwards, (long)fix->forwards);
7562 arm_print_value (dump_file, fix->value);
7563 fprintf (dump_file, "\n");
7566 /* Add it to the chain of fixes. */
7569 if (minipool_fix_head != NULL)
7570 minipool_fix_tail->next = fix;
7572 minipool_fix_head = fix;
7574 minipool_fix_tail = fix;
7577 /* Scan INSN and note any of its operands that need fixing.
7578 If DO_PUSHES is false we do not actually push any of the fixups
7579 needed. The function returns TRUE is any fixups were needed/pushed.
7580 This is used by arm_memory_load_p() which needs to know about loads
7581 of constants that will be converted into minipool loads. */
7583 note_invalid_constants (rtx insn, HOST_WIDE_INT address, int do_pushes)
7585 bool result = false;
7588 extract_insn (insn);
7590 if (!constrain_operands (1))
7591 fatal_insn_not_found (insn);
7593 if (recog_data.n_alternatives == 0)
7596 /* Fill in recog_op_alt with information about the constraints of this insn. */
7597 preprocess_constraints ();
7599 for (opno = 0; opno < recog_data.n_operands; opno++)
7601 /* Things we need to fix can only occur in inputs. */
7602 if (recog_data.operand_type[opno] != OP_IN)
7605 /* If this alternative is a memory reference, then any mention
7606 of constants in this alternative is really to fool reload
7607 into allowing us to accept one there. We need to fix them up
7608 now so that we output the right code. */
7609 if (recog_op_alt[opno][which_alternative].memory_ok)
7611 rtx op = recog_data.operand[opno];
7613 if (CONSTANT_P (op))
7616 push_minipool_fix (insn, address, recog_data.operand_loc[opno],
7617 recog_data.operand_mode[opno], op);
7620 else if (GET_CODE (op) == MEM
7621 && GET_CODE (XEXP (op, 0)) == SYMBOL_REF
7622 && CONSTANT_POOL_ADDRESS_P (XEXP (op, 0)))
7626 rtx cop = avoid_constant_pool_reference (op);
7628 /* Casting the address of something to a mode narrower
7629 than a word can cause avoid_constant_pool_reference()
7630 to return the pool reference itself. That's no good to
7631 us here. Lets just hope that we can use the
7632 constant pool value directly. */
7634 cop = get_pool_constant (XEXP (op, 0));
7636 push_minipool_fix (insn, address,
7637 recog_data.operand_loc[opno],
7638 recog_data.operand_mode[opno], cop);
7649 /* Gcc puts the pool in the wrong place for ARM, since we can only
7650 load addresses a limited distance around the pc. We do some
7651 special munging to move the constant pool values to the correct
7652 point in the code. */
7657 HOST_WIDE_INT address = 0;
7660 minipool_fix_head = minipool_fix_tail = NULL;
7662 /* The first insn must always be a note, or the code below won't
7663 scan it properly. */
7664 insn = get_insns ();
7665 if (GET_CODE (insn) != NOTE)
7668 /* Scan all the insns and record the operands that will need fixing. */
7669 for (insn = next_nonnote_insn (insn); insn; insn = next_nonnote_insn (insn))
7671 if (TARGET_CIRRUS_FIX_INVALID_INSNS
7672 && (arm_cirrus_insn_p (insn)
7673 || GET_CODE (insn) == JUMP_INSN
7674 || arm_memory_load_p (insn)))
7675 cirrus_reorg (insn);
7677 if (GET_CODE (insn) == BARRIER)
7678 push_minipool_barrier (insn, address);
7679 else if (INSN_P (insn))
7683 note_invalid_constants (insn, address, true);
7684 address += get_attr_length (insn);
7686 /* If the insn is a vector jump, add the size of the table
7687 and skip the table. */
7688 if ((table = is_jump_table (insn)) != NULL)
7690 address += get_jump_table_size (table);
7696 fix = minipool_fix_head;
7698 /* Now scan the fixups and perform the required changes. */
7703 Mfix * last_added_fix;
7704 Mfix * last_barrier = NULL;
7707 /* Skip any further barriers before the next fix. */
7708 while (fix && GET_CODE (fix->insn) == BARRIER)
7711 /* No more fixes. */
7715 last_added_fix = NULL;
7717 for (ftmp = fix; ftmp; ftmp = ftmp->next)
7719 if (GET_CODE (ftmp->insn) == BARRIER)
7721 if (ftmp->address >= minipool_vector_head->max_address)
7724 last_barrier = ftmp;
7726 else if ((ftmp->minipool = add_minipool_forward_ref (ftmp)) == NULL)
7729 last_added_fix = ftmp; /* Keep track of the last fix added. */
7732 /* If we found a barrier, drop back to that; any fixes that we
7733 could have reached but come after the barrier will now go in
7734 the next mini-pool. */
7735 if (last_barrier != NULL)
7737 /* Reduce the refcount for those fixes that won't go into this
7739 for (fdel = last_barrier->next;
7740 fdel && fdel != ftmp;
7743 fdel->minipool->refcount--;
7744 fdel->minipool = NULL;
7747 ftmp = last_barrier;
7751 /* ftmp is first fix that we can't fit into this pool and
7752 there no natural barriers that we could use. Insert a
7753 new barrier in the code somewhere between the previous
7754 fix and this one, and arrange to jump around it. */
7755 HOST_WIDE_INT max_address;
7757 /* The last item on the list of fixes must be a barrier, so
7758 we can never run off the end of the list of fixes without
7759 last_barrier being set. */
7763 max_address = minipool_vector_head->max_address;
7764 /* Check that there isn't another fix that is in range that
7765 we couldn't fit into this pool because the pool was
7766 already too large: we need to put the pool before such an
7768 if (ftmp->address < max_address)
7769 max_address = ftmp->address;
7771 last_barrier = create_fix_barrier (last_added_fix, max_address);
7774 assign_minipool_offsets (last_barrier);
7778 if (GET_CODE (ftmp->insn) != BARRIER
7779 && ((ftmp->minipool = add_minipool_backward_ref (ftmp))
7786 /* Scan over the fixes we have identified for this pool, fixing them
7787 up and adding the constants to the pool itself. */
7788 for (this_fix = fix; this_fix && ftmp != this_fix;
7789 this_fix = this_fix->next)
7790 if (GET_CODE (this_fix->insn) != BARRIER)
7793 = plus_constant (gen_rtx_LABEL_REF (VOIDmode,
7794 minipool_vector_label),
7795 this_fix->minipool->offset);
7796 *this_fix->loc = gen_rtx_MEM (this_fix->mode, addr);
7799 dump_minipool (last_barrier->insn);
7803 /* From now on we must synthesize any constants that we can't handle
7804 directly. This can happen if the RTL gets split during final
7805 instruction generation. */
7806 after_arm_reorg = 1;
7808 /* Free the minipool memory. */
7809 obstack_free (&minipool_obstack, minipool_startobj);
7812 /* Routines to output assembly language. */
7814 /* If the rtx is the correct value then return the string of the number.
7815 In this way we can ensure that valid double constants are generated even
7816 when cross compiling. */
7818 fp_immediate_constant (rtx x)
7823 if (!fp_consts_inited)
7826 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
7827 for (i = 0; i < 8; i++)
7828 if (REAL_VALUES_EQUAL (r, values_fp[i]))
7829 return strings_fp[i];
7834 /* As for fp_immediate_constant, but value is passed directly, not in rtx. */
7836 fp_const_from_val (REAL_VALUE_TYPE *r)
7840 if (!fp_consts_inited)
7843 for (i = 0; i < 8; i++)
7844 if (REAL_VALUES_EQUAL (*r, values_fp[i]))
7845 return strings_fp[i];
7850 /* Output the operands of a LDM/STM instruction to STREAM.
7851 MASK is the ARM register set mask of which only bits 0-15 are important.
7852 REG is the base register, either the frame pointer or the stack pointer,
7853 INSTR is the possibly suffixed load or store instruction. */
7855 print_multi_reg (FILE *stream, const char *instr, int reg, int mask)
7858 int not_first = FALSE;
7860 fputc ('\t', stream);
7861 asm_fprintf (stream, instr, reg);
7862 fputs (", {", stream);
7864 for (i = 0; i <= LAST_ARM_REGNUM; i++)
7865 if (mask & (1 << i))
7868 fprintf (stream, ", ");
7870 asm_fprintf (stream, "%r", i);
7874 fprintf (stream, "}");
7876 /* Add a ^ character for the 26-bit ABI, but only if we were loading
7877 the PC. Otherwise we would generate an UNPREDICTABLE instruction.
7878 Strictly speaking the instruction would be unpredicatble only if
7879 we were writing back the base register as well, but since we never
7880 want to generate an LDM type 2 instruction (register bank switching)
7881 which is what you get if the PC is not being loaded, we do not need
7882 to check for writeback. */
7883 if (! TARGET_APCS_32
7884 && ((mask & (1 << PC_REGNUM)) != 0))
7885 fprintf (stream, "^");
7887 fprintf (stream, "\n");
7891 /* Output a FLDMX instruction to STREAM.
7892 BASE if the register containing the address.
7893 REG and COUNT specify the register range.
7894 Extra registers may be added to avoid hardware bugs. */
7897 arm_output_fldmx (FILE * stream, unsigned int base, int reg, int count)
7901 /* Workaround ARM10 VFPr1 bug. */
7902 if (count == 2 && !arm_arch6)
7909 fputc ('\t', stream);
7910 asm_fprintf (stream, "fldmfdx\t%r!, {", base);
7912 for (i = reg; i < reg + count; i++)
7915 fputs (", ", stream);
7916 asm_fprintf (stream, "d%d", i);
7918 fputs ("}\n", stream);
7923 /* Output the assembly for a store multiple. */
7926 vfp_output_fstmx (rtx * operands)
7933 strcpy (pattern, "fstmfdx\t%m0!, {%P1");
7934 p = strlen (pattern);
7936 if (GET_CODE (operands[1]) != REG)
7939 base = (REGNO (operands[1]) - FIRST_VFP_REGNUM) / 2;
7940 for (i = 1; i < XVECLEN (operands[2], 0); i++)
7942 p += sprintf (&pattern[p], ", d%d", base + i);
7944 strcpy (&pattern[p], "}");
7946 output_asm_insn (pattern, operands);
7951 /* Emit RTL to save block of VFP register pairs to the stack. Returns the
7952 number of bytes pushed. */
7955 vfp_emit_fstmx (int base_reg, int count)
7962 /* Workaround ARM10 VFPr1 bug. Data corruption can occur when exactly two
7963 register pairs are stored by a store multiple insn. We avoid this
7964 by pushing an extra pair. */
7965 if (count == 2 && !arm_arch6)
7967 if (base_reg == LAST_VFP_REGNUM - 3)
7972 /* ??? The frame layout is implementation defined. We describe
7973 standard format 1 (equivalent to a FSTMD insn and unused pad word).
7974 We really need some way of representing the whole block so that the
7975 unwinder can figure it out at runtime. */
7976 par = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
7977 dwarf = gen_rtx_SEQUENCE (VOIDmode, rtvec_alloc (count + 1));
7979 reg = gen_rtx_REG (DFmode, base_reg);
7983 = gen_rtx_SET (VOIDmode,
7984 gen_rtx_MEM (BLKmode,
7985 gen_rtx_PRE_DEC (BLKmode, stack_pointer_rtx)),
7986 gen_rtx_UNSPEC (BLKmode,
7990 tmp = gen_rtx_SET (VOIDmode, stack_pointer_rtx,
7991 gen_rtx_PLUS (SImode, stack_pointer_rtx,
7992 GEN_INT (-(count * 8 + 4))));
7993 RTX_FRAME_RELATED_P (tmp) = 1;
7994 XVECEXP (dwarf, 0, 0) = tmp;
7996 tmp = gen_rtx_SET (VOIDmode,
7997 gen_rtx_MEM (DFmode, stack_pointer_rtx),
7999 RTX_FRAME_RELATED_P (tmp) = 1;
8000 XVECEXP (dwarf, 0, 1) = tmp;
8002 for (i = 1; i < count; i++)
8004 reg = gen_rtx_REG (DFmode, base_reg);
8006 XVECEXP (par, 0, i) = gen_rtx_USE (VOIDmode, reg);
8008 tmp = gen_rtx_SET (VOIDmode,
8009 gen_rtx_MEM (DFmode,
8010 gen_rtx_PLUS (SImode,
8014 RTX_FRAME_RELATED_P (tmp) = 1;
8015 XVECEXP (dwarf, 0, i + 1) = tmp;
8018 par = emit_insn (par);
8019 REG_NOTES (par) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, dwarf,
8021 RTX_FRAME_RELATED_P (par) = 1;
8023 return count * 8 + 4;
8027 /* Output a 'call' insn. */
8029 output_call (rtx *operands)
8031 /* Handle calls to lr using ip (which may be clobbered in subr anyway). */
8033 if (REGNO (operands[0]) == LR_REGNUM)
8035 operands[0] = gen_rtx_REG (SImode, IP_REGNUM);
8036 output_asm_insn ("mov%?\t%0, %|lr", operands);
8039 output_asm_insn ("mov%?\t%|lr, %|pc", operands);
8041 if (TARGET_INTERWORK)
8042 output_asm_insn ("bx%?\t%0", operands);
8044 output_asm_insn ("mov%?\t%|pc, %0", operands);
8049 /* Output a 'call' insn that is a reference in memory. */
8051 output_call_mem (rtx *operands)
8053 if (TARGET_INTERWORK)
8055 output_asm_insn ("ldr%?\t%|ip, %0", operands);
8056 output_asm_insn ("mov%?\t%|lr, %|pc", operands);
8057 output_asm_insn ("bx%?\t%|ip", operands);
8059 else if (regno_use_in (LR_REGNUM, operands[0]))
8061 /* LR is used in the memory address. We load the address in the
8062 first instruction. It's safe to use IP as the target of the
8063 load since the call will kill it anyway. */
8064 output_asm_insn ("ldr%?\t%|ip, %0", operands);
8065 output_asm_insn ("mov%?\t%|lr, %|pc", operands);
8066 output_asm_insn ("mov%?\t%|pc, %|ip", operands);
8070 output_asm_insn ("mov%?\t%|lr, %|pc", operands);
8071 output_asm_insn ("ldr%?\t%|pc, %0", operands);
8078 /* Output a move from arm registers to an fpa registers.
8079 OPERANDS[0] is an fpa register.
8080 OPERANDS[1] is the first registers of an arm register pair. */
8082 output_mov_long_double_fpa_from_arm (rtx *operands)
8084 int arm_reg0 = REGNO (operands[1]);
8087 if (arm_reg0 == IP_REGNUM)
8090 ops[0] = gen_rtx_REG (SImode, arm_reg0);
8091 ops[1] = gen_rtx_REG (SImode, 1 + arm_reg0);
8092 ops[2] = gen_rtx_REG (SImode, 2 + arm_reg0);
8094 output_asm_insn ("stm%?fd\t%|sp!, {%0, %1, %2}", ops);
8095 output_asm_insn ("ldf%?e\t%0, [%|sp], #12", operands);
8100 /* Output a move from an fpa register to arm registers.
8101 OPERANDS[0] is the first registers of an arm register pair.
8102 OPERANDS[1] is an fpa register. */
8104 output_mov_long_double_arm_from_fpa (rtx *operands)
8106 int arm_reg0 = REGNO (operands[0]);
8109 if (arm_reg0 == IP_REGNUM)
8112 ops[0] = gen_rtx_REG (SImode, arm_reg0);
8113 ops[1] = gen_rtx_REG (SImode, 1 + arm_reg0);
8114 ops[2] = gen_rtx_REG (SImode, 2 + arm_reg0);
8116 output_asm_insn ("stf%?e\t%1, [%|sp, #-12]!", operands);
8117 output_asm_insn ("ldm%?fd\t%|sp!, {%0, %1, %2}", ops);
8121 /* Output a move from arm registers to arm registers of a long double
8122 OPERANDS[0] is the destination.
8123 OPERANDS[1] is the source. */
8125 output_mov_long_double_arm_from_arm (rtx *operands)
8127 /* We have to be careful here because the two might overlap. */
8128 int dest_start = REGNO (operands[0]);
8129 int src_start = REGNO (operands[1]);
8133 if (dest_start < src_start)
8135 for (i = 0; i < 3; i++)
8137 ops[0] = gen_rtx_REG (SImode, dest_start + i);
8138 ops[1] = gen_rtx_REG (SImode, src_start + i);
8139 output_asm_insn ("mov%?\t%0, %1", ops);
8144 for (i = 2; i >= 0; i--)
8146 ops[0] = gen_rtx_REG (SImode, dest_start + i);
8147 ops[1] = gen_rtx_REG (SImode, src_start + i);
8148 output_asm_insn ("mov%?\t%0, %1", ops);
8156 /* Output a move from arm registers to an fpa registers.
8157 OPERANDS[0] is an fpa register.
8158 OPERANDS[1] is the first registers of an arm register pair. */
8160 output_mov_double_fpa_from_arm (rtx *operands)
8162 int arm_reg0 = REGNO (operands[1]);
8165 if (arm_reg0 == IP_REGNUM)
8168 ops[0] = gen_rtx_REG (SImode, arm_reg0);
8169 ops[1] = gen_rtx_REG (SImode, 1 + arm_reg0);
8170 output_asm_insn ("stm%?fd\t%|sp!, {%0, %1}", ops);
8171 output_asm_insn ("ldf%?d\t%0, [%|sp], #8", operands);
8175 /* Output a move from an fpa register to arm registers.
8176 OPERANDS[0] is the first registers of an arm register pair.
8177 OPERANDS[1] is an fpa register. */
8179 output_mov_double_arm_from_fpa (rtx *operands)
8181 int arm_reg0 = REGNO (operands[0]);
8184 if (arm_reg0 == IP_REGNUM)
8187 ops[0] = gen_rtx_REG (SImode, arm_reg0);
8188 ops[1] = gen_rtx_REG (SImode, 1 + arm_reg0);
8189 output_asm_insn ("stf%?d\t%1, [%|sp, #-8]!", operands);
8190 output_asm_insn ("ldm%?fd\t%|sp!, {%0, %1}", ops);
8194 /* Output a move between double words.
8195 It must be REG<-REG, REG<-CONST_DOUBLE, REG<-CONST_INT, REG<-MEM
8196 or MEM<-REG and all MEMs must be offsettable addresses. */
8198 output_move_double (rtx *operands)
8200 enum rtx_code code0 = GET_CODE (operands[0]);
8201 enum rtx_code code1 = GET_CODE (operands[1]);
8206 int reg0 = REGNO (operands[0]);
8208 otherops[0] = gen_rtx_REG (SImode, 1 + reg0);
8212 int reg1 = REGNO (operands[1]);
8213 if (reg1 == IP_REGNUM)
8216 /* Ensure the second source is not overwritten. */
8217 if (reg1 == reg0 + (WORDS_BIG_ENDIAN ? -1 : 1))
8218 output_asm_insn ("mov%?\t%Q0, %Q1\n\tmov%?\t%R0, %R1", operands);
8220 output_asm_insn ("mov%?\t%R0, %R1\n\tmov%?\t%Q0, %Q1", operands);
8222 else if (code1 == CONST_VECTOR)
8224 HOST_WIDE_INT hint = 0;
8226 switch (GET_MODE (operands[1]))
8229 otherops[1] = GEN_INT (INTVAL (CONST_VECTOR_ELT (operands[1], 1)));
8230 operands[1] = GEN_INT (INTVAL (CONST_VECTOR_ELT (operands[1], 0)));
8234 if (BYTES_BIG_ENDIAN)
8236 hint = INTVAL (CONST_VECTOR_ELT (operands[1], 2));
8238 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 3));
8242 hint = INTVAL (CONST_VECTOR_ELT (operands[1], 3));
8244 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 2));
8247 otherops[1] = GEN_INT (hint);
8250 if (BYTES_BIG_ENDIAN)
8252 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 0));
8254 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 1));
8258 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 1));
8260 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 0));
8263 operands[1] = GEN_INT (hint);
8267 if (BYTES_BIG_ENDIAN)
8269 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 4));
8271 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 5));
8273 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 6));
8275 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 7));
8279 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 7));
8281 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 6));
8283 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 5));
8285 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 4));
8288 otherops[1] = GEN_INT (hint);
8291 if (BYTES_BIG_ENDIAN)
8293 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 0));
8295 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 1));
8297 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 2));
8299 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 3));
8303 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 3));
8305 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 2));
8307 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 1));
8309 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 0));
8312 operands[1] = GEN_INT (hint);
8318 output_mov_immediate (operands);
8319 output_mov_immediate (otherops);
8321 else if (code1 == CONST_DOUBLE)
8323 if (GET_MODE (operands[1]) == DFmode)
8328 REAL_VALUE_FROM_CONST_DOUBLE (r, operands[1]);
8329 REAL_VALUE_TO_TARGET_DOUBLE (r, l);
8330 otherops[1] = GEN_INT (l[1]);
8331 operands[1] = GEN_INT (l[0]);
8333 else if (GET_MODE (operands[1]) != VOIDmode)
8335 else if (WORDS_BIG_ENDIAN)
8337 otherops[1] = GEN_INT (CONST_DOUBLE_LOW (operands[1]));
8338 operands[1] = GEN_INT (CONST_DOUBLE_HIGH (operands[1]));
8342 otherops[1] = GEN_INT (CONST_DOUBLE_HIGH (operands[1]));
8343 operands[1] = GEN_INT (CONST_DOUBLE_LOW (operands[1]));
8346 output_mov_immediate (operands);
8347 output_mov_immediate (otherops);
8349 else if (code1 == CONST_INT)
8351 #if HOST_BITS_PER_WIDE_INT > 32
8352 /* If HOST_WIDE_INT is more than 32 bits, the intval tells us
8353 what the upper word is. */
8354 if (WORDS_BIG_ENDIAN)
8356 otherops[1] = GEN_INT (ARM_SIGN_EXTEND (INTVAL (operands[1])));
8357 operands[1] = GEN_INT (INTVAL (operands[1]) >> 32);
8361 otherops[1] = GEN_INT (INTVAL (operands[1]) >> 32);
8362 operands[1] = GEN_INT (ARM_SIGN_EXTEND (INTVAL (operands[1])));
8365 /* Sign extend the intval into the high-order word. */
8366 if (WORDS_BIG_ENDIAN)
8368 otherops[1] = operands[1];
8369 operands[1] = (INTVAL (operands[1]) < 0
8370 ? constm1_rtx : const0_rtx);
8373 otherops[1] = INTVAL (operands[1]) < 0 ? constm1_rtx : const0_rtx;
8375 output_mov_immediate (otherops);
8376 output_mov_immediate (operands);
8378 else if (code1 == MEM)
8380 switch (GET_CODE (XEXP (operands[1], 0)))
8383 output_asm_insn ("ldm%?ia\t%m1, %M0", operands);
8387 abort (); /* Should never happen now. */
8391 output_asm_insn ("ldm%?db\t%m1!, %M0", operands);
8395 output_asm_insn ("ldm%?ia\t%m1!, %M0", operands);
8399 abort (); /* Should never happen now. */
8404 output_asm_insn ("adr%?\t%0, %1", operands);
8405 output_asm_insn ("ldm%?ia\t%0, %M0", operands);
8409 if (arm_add_operand (XEXP (XEXP (operands[1], 0), 1),
8410 GET_MODE (XEXP (XEXP (operands[1], 0), 1))))
8412 otherops[0] = operands[0];
8413 otherops[1] = XEXP (XEXP (operands[1], 0), 0);
8414 otherops[2] = XEXP (XEXP (operands[1], 0), 1);
8416 if (GET_CODE (XEXP (operands[1], 0)) == PLUS)
8418 if (GET_CODE (otherops[2]) == CONST_INT)
8420 switch ((int) INTVAL (otherops[2]))
8423 output_asm_insn ("ldm%?db\t%1, %M0", otherops);
8426 output_asm_insn ("ldm%?da\t%1, %M0", otherops);
8429 output_asm_insn ("ldm%?ib\t%1, %M0", otherops);
8433 if (!(const_ok_for_arm (INTVAL (otherops[2]))))
8434 output_asm_insn ("sub%?\t%0, %1, #%n2", otherops);
8436 output_asm_insn ("add%?\t%0, %1, %2", otherops);
8439 output_asm_insn ("add%?\t%0, %1, %2", otherops);
8442 output_asm_insn ("sub%?\t%0, %1, %2", otherops);
8444 return "ldm%?ia\t%0, %M0";
8448 otherops[1] = adjust_address (operands[1], SImode, 4);
8449 /* Take care of overlapping base/data reg. */
8450 if (reg_mentioned_p (operands[0], operands[1]))
8452 output_asm_insn ("ldr%?\t%0, %1", otherops);
8453 output_asm_insn ("ldr%?\t%0, %1", operands);
8457 output_asm_insn ("ldr%?\t%0, %1", operands);
8458 output_asm_insn ("ldr%?\t%0, %1", otherops);
8464 abort (); /* Constraints should prevent this. */
8466 else if (code0 == MEM && code1 == REG)
8468 if (REGNO (operands[1]) == IP_REGNUM)
8471 switch (GET_CODE (XEXP (operands[0], 0)))
8474 output_asm_insn ("stm%?ia\t%m0, %M1", operands);
8478 abort (); /* Should never happen now. */
8482 output_asm_insn ("stm%?db\t%m0!, %M1", operands);
8486 output_asm_insn ("stm%?ia\t%m0!, %M1", operands);
8490 abort (); /* Should never happen now. */
8494 if (GET_CODE (XEXP (XEXP (operands[0], 0), 1)) == CONST_INT)
8496 switch ((int) INTVAL (XEXP (XEXP (operands[0], 0), 1)))
8499 output_asm_insn ("stm%?db\t%m0, %M1", operands);
8503 output_asm_insn ("stm%?da\t%m0, %M1", operands);
8507 output_asm_insn ("stm%?ib\t%m0, %M1", operands);
8514 otherops[0] = adjust_address (operands[0], SImode, 4);
8515 otherops[1] = gen_rtx_REG (SImode, 1 + REGNO (operands[1]));
8516 output_asm_insn ("str%?\t%1, %0", operands);
8517 output_asm_insn ("str%?\t%1, %0", otherops);
8521 /* Constraints should prevent this. */
8528 /* Output an arbitrary MOV reg, #n.
8529 OPERANDS[0] is a register. OPERANDS[1] is a const_int. */
8531 output_mov_immediate (rtx *operands)
8533 HOST_WIDE_INT n = INTVAL (operands[1]);
8535 /* Try to use one MOV. */
8536 if (const_ok_for_arm (n))
8537 output_asm_insn ("mov%?\t%0, %1", operands);
8539 /* Try to use one MVN. */
8540 else if (const_ok_for_arm (~n))
8542 operands[1] = GEN_INT (~n);
8543 output_asm_insn ("mvn%?\t%0, %1", operands);
8550 /* If all else fails, make it out of ORRs or BICs as appropriate. */
8551 for (i = 0; i < 32; i++)
8555 if (n_ones > 16) /* Shorter to use MVN with BIC in this case. */
8556 output_multi_immediate (operands, "mvn%?\t%0, %1", "bic%?\t%0, %0, %1", 1, ~ n);
8558 output_multi_immediate (operands, "mov%?\t%0, %1", "orr%?\t%0, %0, %1", 1, n);
8564 /* Output an ADD r, s, #n where n may be too big for one instruction.
8565 If adding zero to one register, output nothing. */
8567 output_add_immediate (rtx *operands)
8569 HOST_WIDE_INT n = INTVAL (operands[2]);
8571 if (n != 0 || REGNO (operands[0]) != REGNO (operands[1]))
8574 output_multi_immediate (operands,
8575 "sub%?\t%0, %1, %2", "sub%?\t%0, %0, %2", 2,
8578 output_multi_immediate (operands,
8579 "add%?\t%0, %1, %2", "add%?\t%0, %0, %2", 2,
8586 /* Output a multiple immediate operation.
8587 OPERANDS is the vector of operands referred to in the output patterns.
8588 INSTR1 is the output pattern to use for the first constant.
8589 INSTR2 is the output pattern to use for subsequent constants.
8590 IMMED_OP is the index of the constant slot in OPERANDS.
8591 N is the constant value. */
8593 output_multi_immediate (rtx *operands, const char *instr1, const char *instr2,
8594 int immed_op, HOST_WIDE_INT n)
8596 #if HOST_BITS_PER_WIDE_INT > 32
8602 /* Quick and easy output. */
8603 operands[immed_op] = const0_rtx;
8604 output_asm_insn (instr1, operands);
8609 const char * instr = instr1;
8611 /* Note that n is never zero here (which would give no output). */
8612 for (i = 0; i < 32; i += 2)
8616 operands[immed_op] = GEN_INT (n & (255 << i));
8617 output_asm_insn (instr, operands);
8627 /* Return the appropriate ARM instruction for the operation code.
8628 The returned result should not be overwritten. OP is the rtx of the
8629 operation. SHIFT_FIRST_ARG is TRUE if the first argument of the operator
8632 arithmetic_instr (rtx op, int shift_first_arg)
8634 switch (GET_CODE (op))
8640 return shift_first_arg ? "rsb" : "sub";
8656 /* Ensure valid constant shifts and return the appropriate shift mnemonic
8657 for the operation code. The returned result should not be overwritten.
8658 OP is the rtx code of the shift.
8659 On exit, *AMOUNTP will be -1 if the shift is by a register, or a constant
8662 shift_op (rtx op, HOST_WIDE_INT *amountp)
8665 enum rtx_code code = GET_CODE (op);
8667 if (GET_CODE (XEXP (op, 1)) == REG || GET_CODE (XEXP (op, 1)) == SUBREG)
8669 else if (GET_CODE (XEXP (op, 1)) == CONST_INT)
8670 *amountp = INTVAL (XEXP (op, 1));
8693 /* We never have to worry about the amount being other than a
8694 power of 2, since this case can never be reloaded from a reg. */
8696 *amountp = int_log2 (*amountp);
8707 /* This is not 100% correct, but follows from the desire to merge
8708 multiplication by a power of 2 with the recognizer for a
8709 shift. >=32 is not a valid shift for "asl", so we must try and
8710 output a shift that produces the correct arithmetical result.
8711 Using lsr #32 is identical except for the fact that the carry bit
8712 is not set correctly if we set the flags; but we never use the
8713 carry bit from such an operation, so we can ignore that. */
8714 if (code == ROTATERT)
8715 /* Rotate is just modulo 32. */
8717 else if (*amountp != (*amountp & 31))
8724 /* Shifts of 0 are no-ops. */
8732 /* Obtain the shift from the POWER of two. */
8734 static HOST_WIDE_INT
8735 int_log2 (HOST_WIDE_INT power)
8737 HOST_WIDE_INT shift = 0;
8739 while ((((HOST_WIDE_INT) 1 << shift) & power) == 0)
8749 /* Output a .ascii pseudo-op, keeping track of lengths. This is because
8750 /bin/as is horribly restrictive. */
8751 #define MAX_ASCII_LEN 51
8754 output_ascii_pseudo_op (FILE *stream, const unsigned char *p, int len)
8759 fputs ("\t.ascii\t\"", stream);
8761 for (i = 0; i < len; i++)
8765 if (len_so_far >= MAX_ASCII_LEN)
8767 fputs ("\"\n\t.ascii\t\"", stream);
8774 fputs ("\\t", stream);
8779 fputs ("\\f", stream);
8784 fputs ("\\b", stream);
8789 fputs ("\\r", stream);
8793 case TARGET_NEWLINE:
8794 fputs ("\\n", stream);
8796 if ((c >= ' ' && c <= '~')
8798 /* This is a good place for a line break. */
8799 len_so_far = MAX_ASCII_LEN;
8806 putc ('\\', stream);
8811 if (c >= ' ' && c <= '~')
8818 fprintf (stream, "\\%03o", c);
8825 fputs ("\"\n", stream);
8828 /* Compute the register sabe mask for registers 0 through 12
8829 inclusive. This code is used by arm_compute_save_reg_mask. */
8830 static unsigned long
8831 arm_compute_save_reg0_reg12_mask (void)
8833 unsigned long func_type = arm_current_func_type ();
8834 unsigned int save_reg_mask = 0;
8837 if (IS_INTERRUPT (func_type))
8839 unsigned int max_reg;
8840 /* Interrupt functions must not corrupt any registers,
8841 even call clobbered ones. If this is a leaf function
8842 we can just examine the registers used by the RTL, but
8843 otherwise we have to assume that whatever function is
8844 called might clobber anything, and so we have to save
8845 all the call-clobbered registers as well. */
8846 if (ARM_FUNC_TYPE (func_type) == ARM_FT_FIQ)
8847 /* FIQ handlers have registers r8 - r12 banked, so
8848 we only need to check r0 - r7, Normal ISRs only
8849 bank r14 and r15, so we must check up to r12.
8850 r13 is the stack pointer which is always preserved,
8851 so we do not need to consider it here. */
8856 for (reg = 0; reg <= max_reg; reg++)
8857 if (regs_ever_live[reg]
8858 || (! current_function_is_leaf && call_used_regs [reg]))
8859 save_reg_mask |= (1 << reg);
8863 /* In the normal case we only need to save those registers
8864 which are call saved and which are used by this function. */
8865 for (reg = 0; reg <= 10; reg++)
8866 if (regs_ever_live[reg] && ! call_used_regs [reg])
8867 save_reg_mask |= (1 << reg);
8869 /* Handle the frame pointer as a special case. */
8870 if (! TARGET_APCS_FRAME
8871 && ! frame_pointer_needed
8872 && regs_ever_live[HARD_FRAME_POINTER_REGNUM]
8873 && ! call_used_regs[HARD_FRAME_POINTER_REGNUM])
8874 save_reg_mask |= 1 << HARD_FRAME_POINTER_REGNUM;
8876 /* If we aren't loading the PIC register,
8877 don't stack it even though it may be live. */
8879 && ! TARGET_SINGLE_PIC_BASE
8880 && regs_ever_live[PIC_OFFSET_TABLE_REGNUM])
8881 save_reg_mask |= 1 << PIC_OFFSET_TABLE_REGNUM;
8884 return save_reg_mask;
8887 /* Compute a bit mask of which registers need to be
8888 saved on the stack for the current function. */
8890 static unsigned long
8891 arm_compute_save_reg_mask (void)
8893 unsigned int save_reg_mask = 0;
8894 unsigned long func_type = arm_current_func_type ();
8896 if (IS_NAKED (func_type))
8897 /* This should never really happen. */
8900 /* If we are creating a stack frame, then we must save the frame pointer,
8901 IP (which will hold the old stack pointer), LR and the PC. */
8902 if (frame_pointer_needed)
8904 (1 << ARM_HARD_FRAME_POINTER_REGNUM)
8909 /* Volatile functions do not return, so there
8910 is no need to save any other registers. */
8911 if (IS_VOLATILE (func_type))
8912 return save_reg_mask;
8914 save_reg_mask |= arm_compute_save_reg0_reg12_mask ();
8916 /* Decide if we need to save the link register.
8917 Interrupt routines have their own banked link register,
8918 so they never need to save it.
8919 Otherwise if we do not use the link register we do not need to save
8920 it. If we are pushing other registers onto the stack however, we
8921 can save an instruction in the epilogue by pushing the link register
8922 now and then popping it back into the PC. This incurs extra memory
8923 accesses though, so we only do it when optimizing for size, and only
8924 if we know that we will not need a fancy return sequence. */
8925 if (regs_ever_live [LR_REGNUM]
8928 && ARM_FUNC_TYPE (func_type) == ARM_FT_NORMAL))
8929 save_reg_mask |= 1 << LR_REGNUM;
8931 if (cfun->machine->lr_save_eliminated)
8932 save_reg_mask &= ~ (1 << LR_REGNUM);
8934 if (TARGET_REALLY_IWMMXT
8935 && ((bit_count (save_reg_mask)
8936 + ARM_NUM_INTS (current_function_pretend_args_size)) % 2) != 0)
8940 /* The total number of registers that are going to be pushed
8941 onto the stack is odd. We need to ensure that the stack
8942 is 64-bit aligned before we start to save iWMMXt registers,
8943 and also before we start to create locals. (A local variable
8944 might be a double or long long which we will load/store using
8945 an iWMMXt instruction). Therefore we need to push another
8946 ARM register, so that the stack will be 64-bit aligned. We
8947 try to avoid using the arg registers (r0 -r3) as they might be
8948 used to pass values in a tail call. */
8949 for (reg = 4; reg <= 12; reg++)
8950 if ((save_reg_mask & (1 << reg)) == 0)
8954 save_reg_mask |= (1 << reg);
8957 cfun->machine->sibcall_blocked = 1;
8958 save_reg_mask |= (1 << 3);
8962 return save_reg_mask;
8966 /* Return the number of bytes required to save VFP registers. */
8968 arm_get_vfp_saved_size (void)
8975 /* Space for saved VFP registers. */
8976 if (TARGET_HARD_FLOAT && TARGET_VFP)
8979 for (regno = FIRST_VFP_REGNUM;
8980 regno < LAST_VFP_REGNUM;
8983 if ((!regs_ever_live[regno] || call_used_regs[regno])
8984 && (!regs_ever_live[regno + 1] || call_used_regs[regno + 1]))
8988 /* Workaround ARM10 VFPr1 bug. */
8989 if (count == 2 && !arm_arch6)
8991 saved += count * 8 + 4;
9000 if (count == 2 && !arm_arch6)
9002 saved += count * 8 + 4;
9009 /* Generate a function exit sequence. If REALLY_RETURN is false, then do
9010 everything bar the final return instruction. */
9012 output_return_instruction (rtx operand, int really_return, int reverse)
9014 char conditional[10];
9017 unsigned long live_regs_mask;
9018 unsigned long func_type;
9019 arm_stack_offsets *offsets;
9021 func_type = arm_current_func_type ();
9023 if (IS_NAKED (func_type))
9026 if (IS_VOLATILE (func_type) && TARGET_ABORT_NORETURN)
9028 /* If this function was declared non-returning, and we have
9029 found a tail call, then we have to trust that the called
9030 function won't return. */
9035 /* Otherwise, trap an attempted return by aborting. */
9037 ops[1] = gen_rtx_SYMBOL_REF (Pmode, NEED_PLT_RELOC ? "abort(PLT)"
9039 assemble_external_libcall (ops[1]);
9040 output_asm_insn (reverse ? "bl%D0\t%a1" : "bl%d0\t%a1", ops);
9046 if (current_function_calls_alloca && !really_return)
9049 sprintf (conditional, "%%?%%%c0", reverse ? 'D' : 'd');
9051 return_used_this_function = 1;
9053 live_regs_mask = arm_compute_save_reg_mask ();
9057 const char * return_reg;
9059 /* If we do not have any special requirements for function exit
9060 (eg interworking, or ISR) then we can load the return address
9061 directly into the PC. Otherwise we must load it into LR. */
9063 && ! TARGET_INTERWORK)
9064 return_reg = reg_names[PC_REGNUM];
9066 return_reg = reg_names[LR_REGNUM];
9068 if ((live_regs_mask & (1 << IP_REGNUM)) == (1 << IP_REGNUM))
9070 /* There are three possible reasons for the IP register
9071 being saved. 1) a stack frame was created, in which case
9072 IP contains the old stack pointer, or 2) an ISR routine
9073 corrupted it, or 3) it was saved to align the stack on
9074 iWMMXt. In case 1, restore IP into SP, otherwise just
9076 if (frame_pointer_needed)
9078 live_regs_mask &= ~ (1 << IP_REGNUM);
9079 live_regs_mask |= (1 << SP_REGNUM);
9083 if (! IS_INTERRUPT (func_type)
9084 && ! TARGET_REALLY_IWMMXT)
9089 /* On some ARM architectures it is faster to use LDR rather than
9090 LDM to load a single register. On other architectures, the
9091 cost is the same. In 26 bit mode, or for exception handlers,
9092 we have to use LDM to load the PC so that the CPSR is also
9094 for (reg = 0; reg <= LAST_ARM_REGNUM; reg++)
9096 if (live_regs_mask == (unsigned int)(1 << reg))
9099 if (reg <= LAST_ARM_REGNUM
9100 && (reg != LR_REGNUM
9102 || (TARGET_APCS_32 && ! IS_INTERRUPT (func_type))))
9104 sprintf (instr, "ldr%s\t%%|%s, [%%|sp], #4", conditional,
9105 (reg == LR_REGNUM) ? return_reg : reg_names[reg]);
9112 /* Generate the load multiple instruction to restore the
9113 registers. Note we can get here, even if
9114 frame_pointer_needed is true, but only if sp already
9115 points to the base of the saved core registers. */
9116 if (live_regs_mask & (1 << SP_REGNUM))
9118 unsigned HOST_WIDE_INT stack_adjust;
9120 offsets = arm_get_frame_offsets ();
9121 stack_adjust = offsets->outgoing_args - offsets->saved_regs;
9122 if (stack_adjust != 0 && stack_adjust != 4)
9125 if (stack_adjust && arm_arch5)
9126 sprintf (instr, "ldm%sib\t%%|sp, {", conditional);
9129 /* If we can't use ldmib (SA110 bug), then try to pop r3
9132 live_regs_mask |= 1 << 3;
9133 sprintf (instr, "ldm%sfd\t%%|sp, {", conditional);
9137 sprintf (instr, "ldm%sfd\t%%|sp!, {", conditional);
9139 p = instr + strlen (instr);
9141 for (reg = 0; reg <= SP_REGNUM; reg++)
9142 if (live_regs_mask & (1 << reg))
9144 int l = strlen (reg_names[reg]);
9150 memcpy (p, ", ", 2);
9154 memcpy (p, "%|", 2);
9155 memcpy (p + 2, reg_names[reg], l);
9159 if (live_regs_mask & (1 << LR_REGNUM))
9161 sprintf (p, "%s%%|%s}", first ? "" : ", ", return_reg);
9162 /* Decide if we need to add the ^ symbol to the end of the
9163 register list. This causes the saved condition codes
9164 register to be copied into the current condition codes
9165 register. We do the copy if we are conforming to the 32-bit
9166 ABI and this is an interrupt function, or if we are
9167 conforming to the 26-bit ABI. There is a special case for
9168 the 26-bit ABI however, which is if we are writing back the
9169 stack pointer but not loading the PC. In this case adding
9170 the ^ symbol would create a type 2 LDM instruction, where
9171 writeback is UNPREDICTABLE. We are safe in leaving the ^
9172 character off in this case however, since the actual return
9173 instruction will be a MOVS which will restore the CPSR. */
9174 if ((TARGET_APCS_32 && IS_INTERRUPT (func_type))
9175 || (! TARGET_APCS_32 && really_return))
9182 output_asm_insn (instr, & operand);
9184 /* See if we need to generate an extra instruction to
9185 perform the actual function return. */
9187 && func_type != ARM_FT_INTERWORKED
9188 && (live_regs_mask & (1 << LR_REGNUM)) != 0)
9190 /* The return has already been handled
9191 by loading the LR into the PC. */
9198 switch ((int) ARM_FUNC_TYPE (func_type))
9202 sprintf (instr, "sub%ss\t%%|pc, %%|lr, #4", conditional);
9205 case ARM_FT_INTERWORKED:
9206 sprintf (instr, "bx%s\t%%|lr", conditional);
9209 case ARM_FT_EXCEPTION:
9210 sprintf (instr, "mov%ss\t%%|pc, %%|lr", conditional);
9214 /* ARMv5 implementations always provide BX, so interworking
9215 is the default unless APCS-26 is in use. */
9216 if ((insn_flags & FL_ARCH5) != 0 && TARGET_APCS_32)
9217 sprintf (instr, "bx%s\t%%|lr", conditional);
9219 sprintf (instr, "mov%s%s\t%%|pc, %%|lr",
9220 conditional, TARGET_APCS_32 ? "" : "s");
9224 output_asm_insn (instr, & operand);
9230 /* Write the function name into the code section, directly preceding
9231 the function prologue.
9233 Code will be output similar to this:
9235 .ascii "arm_poke_function_name", 0
9238 .word 0xff000000 + (t1 - t0)
9239 arm_poke_function_name
9241 stmfd sp!, {fp, ip, lr, pc}
9244 When performing a stack backtrace, code can inspect the value
9245 of 'pc' stored at 'fp' + 0. If the trace function then looks
9246 at location pc - 12 and the top 8 bits are set, then we know
9247 that there is a function name embedded immediately preceding this
9248 location and has length ((pc[-3]) & 0xff000000).
9250 We assume that pc is declared as a pointer to an unsigned long.
9252 It is of no benefit to output the function name if we are assembling
9253 a leaf function. These function types will not contain a stack
9254 backtrace structure, therefore it is not possible to determine the
9257 arm_poke_function_name (FILE *stream, const char *name)
9259 unsigned long alignlength;
9260 unsigned long length;
9263 length = strlen (name) + 1;
9264 alignlength = ROUND_UP_WORD (length);
9266 ASM_OUTPUT_ASCII (stream, name, length);
9267 ASM_OUTPUT_ALIGN (stream, 2);
9268 x = GEN_INT ((unsigned HOST_WIDE_INT) 0xff000000 + alignlength);
9269 assemble_aligned_integer (UNITS_PER_WORD, x);
9272 /* Place some comments into the assembler stream
9273 describing the current function. */
9275 arm_output_function_prologue (FILE *f, HOST_WIDE_INT frame_size)
9277 unsigned long func_type;
9281 thumb_output_function_prologue (f, frame_size);
9286 if (arm_ccfsm_state || arm_target_insn)
9289 func_type = arm_current_func_type ();
9291 switch ((int) ARM_FUNC_TYPE (func_type))
9296 case ARM_FT_INTERWORKED:
9297 asm_fprintf (f, "\t%@ Function supports interworking.\n");
9299 case ARM_FT_EXCEPTION_HANDLER:
9300 asm_fprintf (f, "\t%@ C++ Exception Handler.\n");
9303 asm_fprintf (f, "\t%@ Interrupt Service Routine.\n");
9306 asm_fprintf (f, "\t%@ Fast Interrupt Service Routine.\n");
9308 case ARM_FT_EXCEPTION:
9309 asm_fprintf (f, "\t%@ ARM Exception Handler.\n");
9313 if (IS_NAKED (func_type))
9314 asm_fprintf (f, "\t%@ Naked Function: prologue and epilogue provided by programmer.\n");
9316 if (IS_VOLATILE (func_type))
9317 asm_fprintf (f, "\t%@ Volatile: function does not return.\n");
9319 if (IS_NESTED (func_type))
9320 asm_fprintf (f, "\t%@ Nested: function declared inside another function.\n");
9322 asm_fprintf (f, "\t%@ args = %d, pretend = %d, frame = %wd\n",
9323 current_function_args_size,
9324 current_function_pretend_args_size, frame_size);
9326 asm_fprintf (f, "\t%@ frame_needed = %d, uses_anonymous_args = %d\n",
9327 frame_pointer_needed,
9328 cfun->machine->uses_anonymous_args);
9330 if (cfun->machine->lr_save_eliminated)
9331 asm_fprintf (f, "\t%@ link register save eliminated.\n");
9333 #ifdef AOF_ASSEMBLER
9335 asm_fprintf (f, "\tmov\t%r, %r\n", IP_REGNUM, PIC_OFFSET_TABLE_REGNUM);
9338 return_used_this_function = 0;
9342 arm_output_epilogue (rtx sibling)
9345 unsigned long saved_regs_mask;
9346 unsigned long func_type;
9347 /* Floats_offset is the offset from the "virtual" frame. In an APCS
9348 frame that is $fp + 4 for a non-variadic function. */
9349 int floats_offset = 0;
9351 FILE * f = asm_out_file;
9352 rtx eh_ofs = cfun->machine->eh_epilogue_sp_ofs;
9353 unsigned int lrm_count = 0;
9354 int really_return = (sibling == NULL);
9356 arm_stack_offsets *offsets;
9358 /* If we have already generated the return instruction
9359 then it is futile to generate anything else. */
9360 if (use_return_insn (FALSE, sibling) && return_used_this_function)
9363 func_type = arm_current_func_type ();
9365 if (IS_NAKED (func_type))
9366 /* Naked functions don't have epilogues. */
9369 if (IS_VOLATILE (func_type) && TARGET_ABORT_NORETURN)
9373 /* A volatile function should never return. Call abort. */
9374 op = gen_rtx_SYMBOL_REF (Pmode, NEED_PLT_RELOC ? "abort(PLT)" : "abort");
9375 assemble_external_libcall (op);
9376 output_asm_insn ("bl\t%a0", &op);
9381 if (ARM_FUNC_TYPE (func_type) == ARM_FT_EXCEPTION_HANDLER
9383 /* If we are throwing an exception, then we really must
9384 be doing a return, so we can't tail-call. */
9387 offsets = arm_get_frame_offsets ();
9388 saved_regs_mask = arm_compute_save_reg_mask ();
9391 lrm_count = bit_count (saved_regs_mask);
9393 floats_offset = offsets->saved_args;
9394 /* Compute how far away the floats will be. */
9395 for (reg = 0; reg <= LAST_ARM_REGNUM; reg++)
9396 if (saved_regs_mask & (1 << reg))
9399 if (frame_pointer_needed)
9401 /* This variable is for the Virtual Frame Pointer, not VFP regs. */
9402 int vfp_offset = offsets->frame;
9404 if (arm_fpu_arch == FPUTYPE_FPA_EMU2)
9406 for (reg = LAST_FPA_REGNUM; reg >= FIRST_FPA_REGNUM; reg--)
9407 if (regs_ever_live[reg] && !call_used_regs[reg])
9409 floats_offset += 12;
9410 asm_fprintf (f, "\tldfe\t%r, [%r, #-%d]\n",
9411 reg, FP_REGNUM, floats_offset - vfp_offset);
9416 start_reg = LAST_FPA_REGNUM;
9418 for (reg = LAST_FPA_REGNUM; reg >= FIRST_FPA_REGNUM; reg--)
9420 if (regs_ever_live[reg] && !call_used_regs[reg])
9422 floats_offset += 12;
9424 /* We can't unstack more than four registers at once. */
9425 if (start_reg - reg == 3)
9427 asm_fprintf (f, "\tlfm\t%r, 4, [%r, #-%d]\n",
9428 reg, FP_REGNUM, floats_offset - vfp_offset);
9429 start_reg = reg - 1;
9434 if (reg != start_reg)
9435 asm_fprintf (f, "\tlfm\t%r, %d, [%r, #-%d]\n",
9436 reg + 1, start_reg - reg,
9437 FP_REGNUM, floats_offset - vfp_offset);
9438 start_reg = reg - 1;
9442 /* Just in case the last register checked also needs unstacking. */
9443 if (reg != start_reg)
9444 asm_fprintf (f, "\tlfm\t%r, %d, [%r, #-%d]\n",
9445 reg + 1, start_reg - reg,
9446 FP_REGNUM, floats_offset - vfp_offset);
9449 if (TARGET_HARD_FLOAT && TARGET_VFP)
9453 /* The fldmx insn does not have base+offset addressing modes,
9454 so we use IP to hold the address. */
9455 saved_size = arm_get_vfp_saved_size ();
9459 floats_offset += saved_size;
9460 asm_fprintf (f, "\tsub\t%r, %r, #%d\n", IP_REGNUM,
9461 FP_REGNUM, floats_offset - vfp_offset);
9463 start_reg = FIRST_VFP_REGNUM;
9464 for (reg = FIRST_VFP_REGNUM; reg < LAST_VFP_REGNUM; reg += 2)
9466 if ((!regs_ever_live[reg] || call_used_regs[reg])
9467 && (!regs_ever_live[reg + 1] || call_used_regs[reg + 1]))
9469 if (start_reg != reg)
9470 arm_output_fldmx (f, IP_REGNUM,
9471 (start_reg - FIRST_VFP_REGNUM) / 2,
9472 (reg - start_reg) / 2);
9473 start_reg = reg + 2;
9476 if (start_reg != reg)
9477 arm_output_fldmx (f, IP_REGNUM,
9478 (start_reg - FIRST_VFP_REGNUM) / 2,
9479 (reg - start_reg) / 2);
9484 /* The frame pointer is guaranteed to be non-double-word aligned.
9485 This is because it is set to (old_stack_pointer - 4) and the
9486 old_stack_pointer was double word aligned. Thus the offset to
9487 the iWMMXt registers to be loaded must also be non-double-word
9488 sized, so that the resultant address *is* double-word aligned.
9489 We can ignore floats_offset since that was already included in
9490 the live_regs_mask. */
9491 lrm_count += (lrm_count % 2 ? 2 : 1);
9493 for (reg = LAST_IWMMXT_REGNUM; reg >= FIRST_IWMMXT_REGNUM; reg--)
9494 if (regs_ever_live[reg] && !call_used_regs[reg])
9496 asm_fprintf (f, "\twldrd\t%r, [%r, #-%d]\n",
9497 reg, FP_REGNUM, lrm_count * 4);
9502 /* saved_regs_mask should contain the IP, which at the time of stack
9503 frame generation actually contains the old stack pointer. So a
9504 quick way to unwind the stack is just pop the IP register directly
9505 into the stack pointer. */
9506 if ((saved_regs_mask & (1 << IP_REGNUM)) == 0)
9508 saved_regs_mask &= ~ (1 << IP_REGNUM);
9509 saved_regs_mask |= (1 << SP_REGNUM);
9511 /* There are two registers left in saved_regs_mask - LR and PC. We
9512 only need to restore the LR register (the return address), but to
9513 save time we can load it directly into the PC, unless we need a
9514 special function exit sequence, or we are not really returning. */
9515 if (really_return && ARM_FUNC_TYPE (func_type) == ARM_FT_NORMAL)
9516 /* Delete the LR from the register mask, so that the LR on
9517 the stack is loaded into the PC in the register mask. */
9518 saved_regs_mask &= ~ (1 << LR_REGNUM);
9520 saved_regs_mask &= ~ (1 << PC_REGNUM);
9522 /* We must use SP as the base register, because SP is one of the
9523 registers being restored. If an interrupt or page fault
9524 happens in the ldm instruction, the SP might or might not
9525 have been restored. That would be bad, as then SP will no
9526 longer indicate the safe area of stack, and we can get stack
9527 corruption. Using SP as the base register means that it will
9528 be reset correctly to the original value, should an interrupt
9529 occur. If the stack pointer already points at the right
9530 place, then omit the subtraction. */
9531 if (offsets->outgoing_args != (1 + (int) bit_count (saved_regs_mask))
9532 || current_function_calls_alloca)
9533 asm_fprintf (f, "\tsub\t%r, %r, #%d\n", SP_REGNUM, FP_REGNUM,
9534 4 * bit_count (saved_regs_mask));
9535 print_multi_reg (f, "ldmfd\t%r", SP_REGNUM, saved_regs_mask);
9537 if (IS_INTERRUPT (func_type))
9538 /* Interrupt handlers will have pushed the
9539 IP onto the stack, so restore it now. */
9540 print_multi_reg (f, "ldmfd\t%r!", SP_REGNUM, 1 << IP_REGNUM);
9544 /* Restore stack pointer if necessary. */
9545 if (offsets->outgoing_args != offsets->saved_regs)
9547 operands[0] = operands[1] = stack_pointer_rtx;
9548 operands[2] = GEN_INT (offsets->outgoing_args - offsets->saved_regs);
9549 output_add_immediate (operands);
9552 if (arm_fpu_arch == FPUTYPE_FPA_EMU2)
9554 for (reg = FIRST_FPA_REGNUM; reg <= LAST_FPA_REGNUM; reg++)
9555 if (regs_ever_live[reg] && !call_used_regs[reg])
9556 asm_fprintf (f, "\tldfe\t%r, [%r], #12\n",
9561 start_reg = FIRST_FPA_REGNUM;
9563 for (reg = FIRST_FPA_REGNUM; reg <= LAST_FPA_REGNUM; reg++)
9565 if (regs_ever_live[reg] && !call_used_regs[reg])
9567 if (reg - start_reg == 3)
9569 asm_fprintf (f, "\tlfmfd\t%r, 4, [%r]!\n",
9570 start_reg, SP_REGNUM);
9571 start_reg = reg + 1;
9576 if (reg != start_reg)
9577 asm_fprintf (f, "\tlfmfd\t%r, %d, [%r]!\n",
9578 start_reg, reg - start_reg,
9581 start_reg = reg + 1;
9585 /* Just in case the last register checked also needs unstacking. */
9586 if (reg != start_reg)
9587 asm_fprintf (f, "\tlfmfd\t%r, %d, [%r]!\n",
9588 start_reg, reg - start_reg, SP_REGNUM);
9591 if (TARGET_HARD_FLOAT && TARGET_VFP)
9593 start_reg = FIRST_VFP_REGNUM;
9594 for (reg = FIRST_VFP_REGNUM; reg < LAST_VFP_REGNUM; reg += 2)
9596 if ((!regs_ever_live[reg] || call_used_regs[reg])
9597 && (!regs_ever_live[reg + 1] || call_used_regs[reg + 1]))
9599 if (start_reg != reg)
9600 arm_output_fldmx (f, SP_REGNUM,
9601 (start_reg - FIRST_VFP_REGNUM) / 2,
9602 (reg - start_reg) / 2);
9603 start_reg = reg + 2;
9606 if (start_reg != reg)
9607 arm_output_fldmx (f, SP_REGNUM,
9608 (start_reg - FIRST_VFP_REGNUM) / 2,
9609 (reg - start_reg) / 2);
9612 for (reg = FIRST_IWMMXT_REGNUM; reg <= LAST_IWMMXT_REGNUM; reg++)
9613 if (regs_ever_live[reg] && !call_used_regs[reg])
9614 asm_fprintf (f, "\twldrd\t%r, [%r], #8\n", reg, SP_REGNUM);
9616 /* If we can, restore the LR into the PC. */
9617 if (ARM_FUNC_TYPE (func_type) == ARM_FT_NORMAL
9619 && current_function_pretend_args_size == 0
9620 && saved_regs_mask & (1 << LR_REGNUM))
9622 saved_regs_mask &= ~ (1 << LR_REGNUM);
9623 saved_regs_mask |= (1 << PC_REGNUM);
9626 /* Load the registers off the stack. If we only have one register
9627 to load use the LDR instruction - it is faster. */
9628 if (saved_regs_mask == (1 << LR_REGNUM))
9630 /* The exception handler ignores the LR, so we do
9631 not really need to load it off the stack. */
9633 asm_fprintf (f, "\tadd\t%r, %r, #4\n", SP_REGNUM, SP_REGNUM);
9635 asm_fprintf (f, "\tldr\t%r, [%r], #4\n", LR_REGNUM, SP_REGNUM);
9637 else if (saved_regs_mask)
9639 if (saved_regs_mask & (1 << SP_REGNUM))
9640 /* Note - write back to the stack register is not enabled
9641 (ie "ldmfd sp!..."). We know that the stack pointer is
9642 in the list of registers and if we add writeback the
9643 instruction becomes UNPREDICTABLE. */
9644 print_multi_reg (f, "ldmfd\t%r", SP_REGNUM, saved_regs_mask);
9646 print_multi_reg (f, "ldmfd\t%r!", SP_REGNUM, saved_regs_mask);
9649 if (current_function_pretend_args_size)
9651 /* Unwind the pre-pushed regs. */
9652 operands[0] = operands[1] = stack_pointer_rtx;
9653 operands[2] = GEN_INT (current_function_pretend_args_size);
9654 output_add_immediate (operands);
9659 || (ARM_FUNC_TYPE (func_type) == ARM_FT_NORMAL
9660 && current_function_pretend_args_size == 0
9661 && saved_regs_mask & (1 << PC_REGNUM)))
9664 /* Generate the return instruction. */
9665 switch ((int) ARM_FUNC_TYPE (func_type))
9667 case ARM_FT_EXCEPTION_HANDLER:
9668 /* Even in 26-bit mode we do a mov (rather than a movs)
9669 because we don't have the PSR bits set in the address. */
9670 asm_fprintf (f, "\tmov\t%r, %r\n", PC_REGNUM, EXCEPTION_LR_REGNUM);
9675 asm_fprintf (f, "\tsubs\t%r, %r, #4\n", PC_REGNUM, LR_REGNUM);
9678 case ARM_FT_EXCEPTION:
9679 asm_fprintf (f, "\tmovs\t%r, %r\n", PC_REGNUM, LR_REGNUM);
9682 case ARM_FT_INTERWORKED:
9683 asm_fprintf (f, "\tbx\t%r\n", LR_REGNUM);
9687 if (frame_pointer_needed)
9688 /* If we used the frame pointer then the return address
9689 will have been loaded off the stack directly into the
9690 PC, so there is no need to issue a MOV instruction
9693 else if (current_function_pretend_args_size == 0
9694 && (saved_regs_mask & (1 << LR_REGNUM)))
9695 /* Similarly we may have been able to load LR into the PC
9696 even if we did not create a stack frame. */
9698 else if (TARGET_APCS_32)
9699 asm_fprintf (f, "\tmov\t%r, %r\n", PC_REGNUM, LR_REGNUM);
9701 asm_fprintf (f, "\tmovs\t%r, %r\n", PC_REGNUM, LR_REGNUM);
9709 arm_output_function_epilogue (FILE *file ATTRIBUTE_UNUSED,
9710 HOST_WIDE_INT frame_size ATTRIBUTE_UNUSED)
9712 arm_stack_offsets *offsets;
9716 /* ??? Probably not safe to set this here, since it assumes that a
9717 function will be emitted as assembly immediately after we generate
9718 RTL for it. This does not happen for inline functions. */
9719 return_used_this_function = 0;
9723 /* We need to take into account any stack-frame rounding. */
9724 offsets = arm_get_frame_offsets ();
9726 if (use_return_insn (FALSE, NULL)
9727 && return_used_this_function
9728 && offsets->saved_regs != offsets->outgoing_args
9729 && !frame_pointer_needed)
9732 /* Reset the ARM-specific per-function variables. */
9733 after_arm_reorg = 0;
9737 /* Generate and emit an insn that we will recognize as a push_multi.
9738 Unfortunately, since this insn does not reflect very well the actual
9739 semantics of the operation, we need to annotate the insn for the benefit
9740 of DWARF2 frame unwind information. */
9742 emit_multi_reg_push (int mask)
9749 int dwarf_par_index;
9752 for (i = 0; i <= LAST_ARM_REGNUM; i++)
9753 if (mask & (1 << i))
9756 if (num_regs == 0 || num_regs > 16)
9759 /* We don't record the PC in the dwarf frame information. */
9760 num_dwarf_regs = num_regs;
9761 if (mask & (1 << PC_REGNUM))
9764 /* For the body of the insn we are going to generate an UNSPEC in
9765 parallel with several USEs. This allows the insn to be recognized
9766 by the push_multi pattern in the arm.md file. The insn looks
9767 something like this:
9770 (set (mem:BLK (pre_dec:BLK (reg:SI sp)))
9771 (unspec:BLK [(reg:SI r4)] UNSPEC_PUSH_MULT))
9772 (use (reg:SI 11 fp))
9773 (use (reg:SI 12 ip))
9774 (use (reg:SI 14 lr))
9775 (use (reg:SI 15 pc))
9778 For the frame note however, we try to be more explicit and actually
9779 show each register being stored into the stack frame, plus a (single)
9780 decrement of the stack pointer. We do it this way in order to be
9781 friendly to the stack unwinding code, which only wants to see a single
9782 stack decrement per instruction. The RTL we generate for the note looks
9783 something like this:
9786 (set (reg:SI sp) (plus:SI (reg:SI sp) (const_int -20)))
9787 (set (mem:SI (reg:SI sp)) (reg:SI r4))
9788 (set (mem:SI (plus:SI (reg:SI sp) (const_int 4))) (reg:SI fp))
9789 (set (mem:SI (plus:SI (reg:SI sp) (const_int 8))) (reg:SI ip))
9790 (set (mem:SI (plus:SI (reg:SI sp) (const_int 12))) (reg:SI lr))
9793 This sequence is used both by the code to support stack unwinding for
9794 exceptions handlers and the code to generate dwarf2 frame debugging. */
9796 par = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (num_regs));
9797 dwarf = gen_rtx_SEQUENCE (VOIDmode, rtvec_alloc (num_dwarf_regs + 1));
9798 dwarf_par_index = 1;
9800 for (i = 0; i <= LAST_ARM_REGNUM; i++)
9802 if (mask & (1 << i))
9804 reg = gen_rtx_REG (SImode, i);
9807 = gen_rtx_SET (VOIDmode,
9808 gen_rtx_MEM (BLKmode,
9809 gen_rtx_PRE_DEC (BLKmode,
9810 stack_pointer_rtx)),
9811 gen_rtx_UNSPEC (BLKmode,
9817 tmp = gen_rtx_SET (VOIDmode,
9818 gen_rtx_MEM (SImode, stack_pointer_rtx),
9820 RTX_FRAME_RELATED_P (tmp) = 1;
9821 XVECEXP (dwarf, 0, dwarf_par_index) = tmp;
9829 for (j = 1, i++; j < num_regs; i++)
9831 if (mask & (1 << i))
9833 reg = gen_rtx_REG (SImode, i);
9835 XVECEXP (par, 0, j) = gen_rtx_USE (VOIDmode, reg);
9839 tmp = gen_rtx_SET (VOIDmode,
9840 gen_rtx_MEM (SImode,
9841 plus_constant (stack_pointer_rtx,
9844 RTX_FRAME_RELATED_P (tmp) = 1;
9845 XVECEXP (dwarf, 0, dwarf_par_index++) = tmp;
9852 par = emit_insn (par);
9854 tmp = gen_rtx_SET (SImode,
9856 gen_rtx_PLUS (SImode,
9858 GEN_INT (-4 * num_regs)));
9859 RTX_FRAME_RELATED_P (tmp) = 1;
9860 XVECEXP (dwarf, 0, 0) = tmp;
9862 REG_NOTES (par) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, dwarf,
9868 emit_sfm (int base_reg, int count)
9875 par = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
9876 dwarf = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
9878 reg = gen_rtx_REG (XFmode, base_reg++);
9881 = gen_rtx_SET (VOIDmode,
9882 gen_rtx_MEM (BLKmode,
9883 gen_rtx_PRE_DEC (BLKmode, stack_pointer_rtx)),
9884 gen_rtx_UNSPEC (BLKmode,
9888 = gen_rtx_SET (VOIDmode,
9889 gen_rtx_MEM (XFmode,
9890 gen_rtx_PRE_DEC (BLKmode, stack_pointer_rtx)),
9892 RTX_FRAME_RELATED_P (tmp) = 1;
9893 XVECEXP (dwarf, 0, count - 1) = tmp;
9895 for (i = 1; i < count; i++)
9897 reg = gen_rtx_REG (XFmode, base_reg++);
9898 XVECEXP (par, 0, i) = gen_rtx_USE (VOIDmode, reg);
9900 tmp = gen_rtx_SET (VOIDmode,
9901 gen_rtx_MEM (XFmode,
9902 gen_rtx_PRE_DEC (BLKmode,
9903 stack_pointer_rtx)),
9905 RTX_FRAME_RELATED_P (tmp) = 1;
9906 XVECEXP (dwarf, 0, count - i - 1) = tmp;
9909 par = emit_insn (par);
9910 REG_NOTES (par) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, dwarf,
9916 /* Compute the distance from register FROM to register TO.
9917 These can be the arg pointer (26), the soft frame pointer (25),
9918 the stack pointer (13) or the hard frame pointer (11).
9919 Typical stack layout looks like this:
9921 old stack pointer -> | |
9924 | | saved arguments for
9925 | | vararg functions
9928 hard FP & arg pointer -> | | \
9936 soft frame pointer -> | | /
9946 current stack pointer -> | | /
9949 For a given function some or all of these stack components
9950 may not be needed, giving rise to the possibility of
9951 eliminating some of the registers.
9953 The values returned by this function must reflect the behavior
9954 of arm_expand_prologue() and arm_compute_save_reg_mask().
9956 The sign of the number returned reflects the direction of stack
9957 growth, so the values are positive for all eliminations except
9958 from the soft frame pointer to the hard frame pointer.
9960 SFP may point just inside the local variables block to ensure correct
9964 /* Calculate stack offsets. These are used to calculate register elimination
9965 offsets and in prologue/epilogue code. */
9967 static arm_stack_offsets *
9968 arm_get_frame_offsets (void)
9970 struct arm_stack_offsets *offsets;
9971 unsigned long func_type;
9974 HOST_WIDE_INT frame_size;
9976 offsets = &cfun->machine->stack_offsets;
9978 /* We need to know if we are a leaf function. Unfortunately, it
9979 is possible to be called after start_sequence has been called,
9980 which causes get_insns to return the insns for the sequence,
9981 not the function, which will cause leaf_function_p to return
9982 the incorrect result.
9984 to know about leaf functions once reload has completed, and the
9985 frame size cannot be changed after that time, so we can safely
9986 use the cached value. */
9988 if (reload_completed)
9991 /* Initially this is the size of the local variables. It will translated
9992 into an offset once we have determined the size of preceding data. */
9993 frame_size = ROUND_UP_WORD (get_frame_size ());
9995 leaf = leaf_function_p ();
9997 /* Space for variadic functions. */
9998 offsets->saved_args = current_function_pretend_args_size;
10000 offsets->frame = offsets->saved_args + (frame_pointer_needed ? 4 : 0);
10004 unsigned int regno;
10006 saved = bit_count (arm_compute_save_reg_mask ()) * 4;
10008 /* We know that SP will be doubleword aligned on entry, and we must
10009 preserve that condition at any subroutine call. We also require the
10010 soft frame pointer to be doubleword aligned. */
10012 if (TARGET_REALLY_IWMMXT)
10014 /* Check for the call-saved iWMMXt registers. */
10015 for (regno = FIRST_IWMMXT_REGNUM;
10016 regno <= LAST_IWMMXT_REGNUM;
10018 if (regs_ever_live [regno] && ! call_used_regs [regno])
10022 func_type = arm_current_func_type ();
10023 if (! IS_VOLATILE (func_type))
10025 /* Space for saved FPA registers. */
10026 for (regno = FIRST_FPA_REGNUM; regno <= LAST_FPA_REGNUM; regno++)
10027 if (regs_ever_live[regno] && ! call_used_regs[regno])
10030 /* Space for saved VFP registers. */
10031 if (TARGET_HARD_FLOAT && TARGET_VFP)
10032 saved += arm_get_vfp_saved_size ();
10035 else /* TARGET_THUMB */
10042 for (reg = 8; reg < 13; reg ++)
10043 if (THUMB_REG_PUSHED_P (reg))
10046 saved += 4 * count_regs;
10048 for (reg = 0; reg <= LAST_LO_REGNUM; reg ++)
10049 if (THUMB_REG_PUSHED_P (reg))
10051 if (count_regs || ! leaf_function_p ()
10052 || thumb_far_jump_used_p ())
10053 saved += 4 * (count_regs + 1);
10054 if (TARGET_BACKTRACE)
10056 if ((count_regs & 0xFF) == 0 && (regs_ever_live[3] != 0))
10063 /* Saved registers include the stack frame. */
10064 offsets->saved_regs = offsets->saved_args + saved;
10065 offsets->soft_frame = offsets->saved_regs;
10066 /* A leaf function does not need any stack alignment if it has nothing
10068 if (leaf && frame_size == 0)
10070 offsets->outgoing_args = offsets->soft_frame;
10074 /* Ensure SFP has the correct alignment. */
10075 if (ARM_DOUBLEWORD_ALIGN
10076 && (offsets->soft_frame & 7))
10077 offsets->soft_frame += 4;
10079 offsets->outgoing_args = offsets->soft_frame + frame_size
10080 + current_function_outgoing_args_size;
10082 if (ARM_DOUBLEWORD_ALIGN)
10084 /* Ensure SP remains doubleword aligned. */
10085 if (offsets->outgoing_args & 7)
10086 offsets->outgoing_args += 4;
10087 if (offsets->outgoing_args & 7)
10095 /* Calculate the relative offsets for the different stack pointers. Positive
10096 offsets are in the direction of stack growth. */
10099 arm_compute_initial_elimination_offset (unsigned int from, unsigned int to)
10101 arm_stack_offsets *offsets;
10103 offsets = arm_get_frame_offsets ();
10105 /* OK, now we have enough information to compute the distances.
10106 There must be an entry in these switch tables for each pair
10107 of registers in ELIMINABLE_REGS, even if some of the entries
10108 seem to be redundant or useless. */
10111 case ARG_POINTER_REGNUM:
10114 case THUMB_HARD_FRAME_POINTER_REGNUM:
10117 case FRAME_POINTER_REGNUM:
10118 /* This is the reverse of the soft frame pointer
10119 to hard frame pointer elimination below. */
10120 return offsets->soft_frame - offsets->saved_args;
10122 case ARM_HARD_FRAME_POINTER_REGNUM:
10123 /* If there is no stack frame then the hard
10124 frame pointer and the arg pointer coincide. */
10125 if (offsets->frame == offsets->saved_regs)
10127 /* FIXME: Not sure about this. Maybe we should always return 0 ? */
10128 return (frame_pointer_needed
10129 && current_function_needs_context
10130 && ! cfun->machine->uses_anonymous_args) ? 4 : 0;
10132 case STACK_POINTER_REGNUM:
10133 /* If nothing has been pushed on the stack at all
10134 then this will return -4. This *is* correct! */
10135 return offsets->outgoing_args - (offsets->saved_args + 4);
10142 case FRAME_POINTER_REGNUM:
10145 case THUMB_HARD_FRAME_POINTER_REGNUM:
10148 case ARM_HARD_FRAME_POINTER_REGNUM:
10149 /* The hard frame pointer points to the top entry in the
10150 stack frame. The soft frame pointer to the bottom entry
10151 in the stack frame. If there is no stack frame at all,
10152 then they are identical. */
10154 return offsets->frame - offsets->soft_frame;
10156 case STACK_POINTER_REGNUM:
10157 return offsets->outgoing_args - offsets->soft_frame;
10165 /* You cannot eliminate from the stack pointer.
10166 In theory you could eliminate from the hard frame
10167 pointer to the stack pointer, but this will never
10168 happen, since if a stack frame is not needed the
10169 hard frame pointer will never be used. */
10175 /* Generate the prologue instructions for entry into an ARM function. */
10177 arm_expand_prologue (void)
10183 unsigned long live_regs_mask;
10184 unsigned long func_type;
10186 int saved_pretend_args = 0;
10187 int saved_regs = 0;
10188 unsigned int args_to_push;
10189 arm_stack_offsets *offsets;
10191 func_type = arm_current_func_type ();
10193 /* Naked functions don't have prologues. */
10194 if (IS_NAKED (func_type))
10197 /* Make a copy of c_f_p_a_s as we may need to modify it locally. */
10198 args_to_push = current_function_pretend_args_size;
10200 /* Compute which register we will have to save onto the stack. */
10201 live_regs_mask = arm_compute_save_reg_mask ();
10203 ip_rtx = gen_rtx_REG (SImode, IP_REGNUM);
10205 if (frame_pointer_needed)
10207 if (IS_INTERRUPT (func_type))
10209 /* Interrupt functions must not corrupt any registers.
10210 Creating a frame pointer however, corrupts the IP
10211 register, so we must push it first. */
10212 insn = emit_multi_reg_push (1 << IP_REGNUM);
10214 /* Do not set RTX_FRAME_RELATED_P on this insn.
10215 The dwarf stack unwinding code only wants to see one
10216 stack decrement per function, and this is not it. If
10217 this instruction is labeled as being part of the frame
10218 creation sequence then dwarf2out_frame_debug_expr will
10219 abort when it encounters the assignment of IP to FP
10220 later on, since the use of SP here establishes SP as
10221 the CFA register and not IP.
10223 Anyway this instruction is not really part of the stack
10224 frame creation although it is part of the prologue. */
10226 else if (IS_NESTED (func_type))
10228 /* The Static chain register is the same as the IP register
10229 used as a scratch register during stack frame creation.
10230 To get around this need to find somewhere to store IP
10231 whilst the frame is being created. We try the following
10234 1. The last argument register.
10235 2. A slot on the stack above the frame. (This only
10236 works if the function is not a varargs function).
10237 3. Register r3, after pushing the argument registers
10240 Note - we only need to tell the dwarf2 backend about the SP
10241 adjustment in the second variant; the static chain register
10242 doesn't need to be unwound, as it doesn't contain a value
10243 inherited from the caller. */
10245 if (regs_ever_live[3] == 0)
10247 insn = gen_rtx_REG (SImode, 3);
10248 insn = gen_rtx_SET (SImode, insn, ip_rtx);
10249 insn = emit_insn (insn);
10251 else if (args_to_push == 0)
10254 insn = gen_rtx_PRE_DEC (SImode, stack_pointer_rtx);
10255 insn = gen_rtx_MEM (SImode, insn);
10256 insn = gen_rtx_SET (VOIDmode, insn, ip_rtx);
10257 insn = emit_insn (insn);
10261 /* Just tell the dwarf backend that we adjusted SP. */
10262 dwarf = gen_rtx_SET (VOIDmode, stack_pointer_rtx,
10263 gen_rtx_PLUS (SImode, stack_pointer_rtx,
10264 GEN_INT (-fp_offset)));
10265 RTX_FRAME_RELATED_P (insn) = 1;
10266 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
10267 dwarf, REG_NOTES (insn));
10271 /* Store the args on the stack. */
10272 if (cfun->machine->uses_anonymous_args)
10273 insn = emit_multi_reg_push
10274 ((0xf0 >> (args_to_push / 4)) & 0xf);
10277 (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,
10278 GEN_INT (- args_to_push)));
10280 RTX_FRAME_RELATED_P (insn) = 1;
10282 saved_pretend_args = 1;
10283 fp_offset = args_to_push;
10286 /* Now reuse r3 to preserve IP. */
10287 insn = gen_rtx_REG (SImode, 3);
10288 insn = gen_rtx_SET (SImode, insn, ip_rtx);
10289 (void) emit_insn (insn);
10295 insn = gen_rtx_PLUS (SImode, stack_pointer_rtx, GEN_INT (fp_offset));
10296 insn = gen_rtx_SET (SImode, ip_rtx, insn);
10299 insn = gen_movsi (ip_rtx, stack_pointer_rtx);
10301 insn = emit_insn (insn);
10302 RTX_FRAME_RELATED_P (insn) = 1;
10307 /* Push the argument registers, or reserve space for them. */
10308 if (cfun->machine->uses_anonymous_args)
10309 insn = emit_multi_reg_push
10310 ((0xf0 >> (args_to_push / 4)) & 0xf);
10313 (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,
10314 GEN_INT (- args_to_push)));
10315 RTX_FRAME_RELATED_P (insn) = 1;
10318 /* If this is an interrupt service routine, and the link register
10319 is going to be pushed, and we are not creating a stack frame,
10320 (which would involve an extra push of IP and a pop in the epilogue)
10321 subtracting four from LR now will mean that the function return
10322 can be done with a single instruction. */
10323 if ((func_type == ARM_FT_ISR || func_type == ARM_FT_FIQ)
10324 && (live_regs_mask & (1 << LR_REGNUM)) != 0
10325 && ! frame_pointer_needed)
10326 emit_insn (gen_rtx_SET (SImode,
10327 gen_rtx_REG (SImode, LR_REGNUM),
10328 gen_rtx_PLUS (SImode,
10329 gen_rtx_REG (SImode, LR_REGNUM),
10332 if (live_regs_mask)
10334 insn = emit_multi_reg_push (live_regs_mask);
10335 saved_regs += bit_count (live_regs_mask) * 4;
10336 RTX_FRAME_RELATED_P (insn) = 1;
10340 for (reg = LAST_IWMMXT_REGNUM; reg >= FIRST_IWMMXT_REGNUM; reg--)
10341 if (regs_ever_live[reg] && ! call_used_regs [reg])
10343 insn = gen_rtx_PRE_DEC (V2SImode, stack_pointer_rtx);
10344 insn = gen_rtx_MEM (V2SImode, insn);
10345 insn = emit_insn (gen_rtx_SET (VOIDmode, insn,
10346 gen_rtx_REG (V2SImode, reg)));
10347 RTX_FRAME_RELATED_P (insn) = 1;
10351 if (! IS_VOLATILE (func_type))
10355 /* Save any floating point call-saved registers used by this
10357 if (arm_fpu_arch == FPUTYPE_FPA_EMU2)
10359 for (reg = LAST_FPA_REGNUM; reg >= FIRST_FPA_REGNUM; reg--)
10360 if (regs_ever_live[reg] && !call_used_regs[reg])
10362 insn = gen_rtx_PRE_DEC (XFmode, stack_pointer_rtx);
10363 insn = gen_rtx_MEM (XFmode, insn);
10364 insn = emit_insn (gen_rtx_SET (VOIDmode, insn,
10365 gen_rtx_REG (XFmode, reg)));
10366 RTX_FRAME_RELATED_P (insn) = 1;
10372 start_reg = LAST_FPA_REGNUM;
10374 for (reg = LAST_FPA_REGNUM; reg >= FIRST_FPA_REGNUM; reg--)
10376 if (regs_ever_live[reg] && !call_used_regs[reg])
10378 if (start_reg - reg == 3)
10380 insn = emit_sfm (reg, 4);
10381 RTX_FRAME_RELATED_P (insn) = 1;
10383 start_reg = reg - 1;
10388 if (start_reg != reg)
10390 insn = emit_sfm (reg + 1, start_reg - reg);
10391 RTX_FRAME_RELATED_P (insn) = 1;
10392 saved_regs += (start_reg - reg) * 12;
10394 start_reg = reg - 1;
10398 if (start_reg != reg)
10400 insn = emit_sfm (reg + 1, start_reg - reg);
10401 saved_regs += (start_reg - reg) * 12;
10402 RTX_FRAME_RELATED_P (insn) = 1;
10405 if (TARGET_HARD_FLOAT && TARGET_VFP)
10407 start_reg = FIRST_VFP_REGNUM;
10409 for (reg = FIRST_VFP_REGNUM; reg < LAST_VFP_REGNUM; reg += 2)
10411 if ((!regs_ever_live[reg] || call_used_regs[reg])
10412 && (!regs_ever_live[reg + 1] || call_used_regs[reg + 1]))
10414 if (start_reg != reg)
10415 saved_regs += vfp_emit_fstmx (start_reg,
10416 (reg - start_reg) / 2);
10417 start_reg = reg + 2;
10420 if (start_reg != reg)
10421 saved_regs += vfp_emit_fstmx (start_reg,
10422 (reg - start_reg) / 2);
10426 if (frame_pointer_needed)
10428 /* Create the new frame pointer. */
10429 insn = GEN_INT (-(4 + args_to_push + fp_offset));
10430 insn = emit_insn (gen_addsi3 (hard_frame_pointer_rtx, ip_rtx, insn));
10431 RTX_FRAME_RELATED_P (insn) = 1;
10433 if (IS_NESTED (func_type))
10435 /* Recover the static chain register. */
10436 if (regs_ever_live [3] == 0
10437 || saved_pretend_args)
10438 insn = gen_rtx_REG (SImode, 3);
10439 else /* if (current_function_pretend_args_size == 0) */
10441 insn = gen_rtx_PLUS (SImode, hard_frame_pointer_rtx,
10443 insn = gen_rtx_MEM (SImode, insn);
10446 emit_insn (gen_rtx_SET (SImode, ip_rtx, insn));
10447 /* Add a USE to stop propagate_one_insn() from barfing. */
10448 emit_insn (gen_prologue_use (ip_rtx));
10452 offsets = arm_get_frame_offsets ();
10453 if (offsets->outgoing_args != offsets->saved_args + saved_regs)
10455 /* This add can produce multiple insns for a large constant, so we
10456 need to get tricky. */
10457 rtx last = get_last_insn ();
10459 amount = GEN_INT (offsets->saved_args + saved_regs
10460 - offsets->outgoing_args);
10462 insn = emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,
10466 last = last ? NEXT_INSN (last) : get_insns ();
10467 RTX_FRAME_RELATED_P (last) = 1;
10469 while (last != insn);
10471 /* If the frame pointer is needed, emit a special barrier that
10472 will prevent the scheduler from moving stores to the frame
10473 before the stack adjustment. */
10474 if (frame_pointer_needed)
10475 insn = emit_insn (gen_stack_tie (stack_pointer_rtx,
10476 hard_frame_pointer_rtx));
10479 /* If we are profiling, make sure no instructions are scheduled before
10480 the call to mcount. Similarly if the user has requested no
10481 scheduling in the prolog. */
10482 if (current_function_profile || TARGET_NO_SCHED_PRO)
10483 emit_insn (gen_blockage ());
10485 /* If the link register is being kept alive, with the return address in it,
10486 then make sure that it does not get reused by the ce2 pass. */
10487 if ((live_regs_mask & (1 << LR_REGNUM)) == 0)
10489 emit_insn (gen_prologue_use (gen_rtx_REG (SImode, LR_REGNUM)));
10490 cfun->machine->lr_save_eliminated = 1;
10494 /* If CODE is 'd', then the X is a condition operand and the instruction
10495 should only be executed if the condition is true.
10496 if CODE is 'D', then the X is a condition operand and the instruction
10497 should only be executed if the condition is false: however, if the mode
10498 of the comparison is CCFPEmode, then always execute the instruction -- we
10499 do this because in these circumstances !GE does not necessarily imply LT;
10500 in these cases the instruction pattern will take care to make sure that
10501 an instruction containing %d will follow, thereby undoing the effects of
10502 doing this instruction unconditionally.
10503 If CODE is 'N' then X is a floating point operand that must be negated
10505 If CODE is 'B' then output a bitwise inverted value of X (a const int).
10506 If X is a REG and CODE is `M', output a ldm/stm style multi-reg. */
10508 arm_print_operand (FILE *stream, rtx x, int code)
10513 fputs (ASM_COMMENT_START, stream);
10517 fputs (user_label_prefix, stream);
10521 fputs (REGISTER_PREFIX, stream);
10525 if (arm_ccfsm_state == 3 || arm_ccfsm_state == 4)
10527 if (TARGET_THUMB || current_insn_predicate != NULL)
10530 fputs (arm_condition_codes[arm_current_cc], stream);
10532 else if (current_insn_predicate)
10534 enum arm_cond_code code;
10539 code = get_arm_condition_code (current_insn_predicate);
10540 fputs (arm_condition_codes[code], stream);
10547 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
10548 r = REAL_VALUE_NEGATE (r);
10549 fprintf (stream, "%s", fp_const_from_val (&r));
10554 if (GET_CODE (x) == CONST_INT)
10557 val = ARM_SIGN_EXTEND (~INTVAL (x));
10558 fprintf (stream, HOST_WIDE_INT_PRINT_DEC, val);
10562 putc ('~', stream);
10563 output_addr_const (stream, x);
10568 fprintf (stream, "%s", arithmetic_instr (x, 1));
10571 /* Truncate Cirrus shift counts. */
10573 if (GET_CODE (x) == CONST_INT)
10575 fprintf (stream, HOST_WIDE_INT_PRINT_DEC, INTVAL (x) & 0x3f);
10578 arm_print_operand (stream, x, 0);
10582 fprintf (stream, "%s", arithmetic_instr (x, 0));
10588 const char * shift = shift_op (x, &val);
10592 fprintf (stream, ", %s ", shift_op (x, &val));
10594 arm_print_operand (stream, XEXP (x, 1), 0);
10596 fprintf (stream, "#" HOST_WIDE_INT_PRINT_DEC, val);
10601 /* An explanation of the 'Q', 'R' and 'H' register operands:
10603 In a pair of registers containing a DI or DF value the 'Q'
10604 operand returns the register number of the register containing
10605 the least significant part of the value. The 'R' operand returns
10606 the register number of the register containing the most
10607 significant part of the value.
10609 The 'H' operand returns the higher of the two register numbers.
10610 On a run where WORDS_BIG_ENDIAN is true the 'H' operand is the
10611 same as the 'Q' operand, since the most significant part of the
10612 value is held in the lower number register. The reverse is true
10613 on systems where WORDS_BIG_ENDIAN is false.
10615 The purpose of these operands is to distinguish between cases
10616 where the endian-ness of the values is important (for example
10617 when they are added together), and cases where the endian-ness
10618 is irrelevant, but the order of register operations is important.
10619 For example when loading a value from memory into a register
10620 pair, the endian-ness does not matter. Provided that the value
10621 from the lower memory address is put into the lower numbered
10622 register, and the value from the higher address is put into the
10623 higher numbered register, the load will work regardless of whether
10624 the value being loaded is big-wordian or little-wordian. The
10625 order of the two register loads can matter however, if the address
10626 of the memory location is actually held in one of the registers
10627 being overwritten by the load. */
10629 if (REGNO (x) > LAST_ARM_REGNUM)
10631 asm_fprintf (stream, "%r", REGNO (x) + (WORDS_BIG_ENDIAN ? 1 : 0));
10635 if (REGNO (x) > LAST_ARM_REGNUM)
10637 asm_fprintf (stream, "%r", REGNO (x) + (WORDS_BIG_ENDIAN ? 0 : 1));
10641 if (REGNO (x) > LAST_ARM_REGNUM)
10643 asm_fprintf (stream, "%r", REGNO (x) + 1);
10647 asm_fprintf (stream, "%r",
10648 GET_CODE (XEXP (x, 0)) == REG
10649 ? REGNO (XEXP (x, 0)) : REGNO (XEXP (XEXP (x, 0), 0)));
10653 asm_fprintf (stream, "{%r-%r}",
10655 REGNO (x) + ARM_NUM_REGS (GET_MODE (x)) - 1);
10659 /* CONST_TRUE_RTX means always -- that's the default. */
10660 if (x == const_true_rtx)
10663 fputs (arm_condition_codes[get_arm_condition_code (x)],
10668 /* CONST_TRUE_RTX means not always -- ie never. We shouldn't ever
10669 want to do that. */
10670 if (x == const_true_rtx)
10673 fputs (arm_condition_codes[ARM_INVERSE_CONDITION_CODE
10674 (get_arm_condition_code (x))],
10678 /* Cirrus registers can be accessed in a variety of ways:
10679 single floating point (f)
10680 double floating point (d)
10682 64bit integer (dx). */
10683 case 'W': /* Cirrus register in F mode. */
10684 case 'X': /* Cirrus register in D mode. */
10685 case 'Y': /* Cirrus register in FX mode. */
10686 case 'Z': /* Cirrus register in DX mode. */
10687 if (GET_CODE (x) != REG || REGNO_REG_CLASS (REGNO (x)) != CIRRUS_REGS)
10690 fprintf (stream, "mv%s%s",
10692 : code == 'X' ? "d"
10693 : code == 'Y' ? "fx" : "dx", reg_names[REGNO (x)] + 2);
10697 /* Print cirrus register in the mode specified by the register's mode. */
10700 int mode = GET_MODE (x);
10702 if (GET_CODE (x) != REG || REGNO_REG_CLASS (REGNO (x)) != CIRRUS_REGS)
10705 fprintf (stream, "mv%s%s",
10706 mode == DFmode ? "d"
10707 : mode == SImode ? "fx"
10708 : mode == DImode ? "dx"
10709 : "f", reg_names[REGNO (x)] + 2);
10715 if (GET_CODE (x) != REG
10716 || REGNO (x) < FIRST_IWMMXT_GR_REGNUM
10717 || REGNO (x) > LAST_IWMMXT_GR_REGNUM)
10718 /* Bad value for wCG register number. */
10721 fprintf (stream, "%d", REGNO (x) - FIRST_IWMMXT_GR_REGNUM);
10724 /* Print an iWMMXt control register name. */
10726 if (GET_CODE (x) != CONST_INT
10728 || INTVAL (x) >= 16)
10729 /* Bad value for wC register number. */
10733 static const char * wc_reg_names [16] =
10735 "wCID", "wCon", "wCSSF", "wCASF",
10736 "wC4", "wC5", "wC6", "wC7",
10737 "wCGR0", "wCGR1", "wCGR2", "wCGR3",
10738 "wC12", "wC13", "wC14", "wC15"
10741 fprintf (stream, wc_reg_names [INTVAL (x)]);
10745 /* Print a VFP double precision register name. */
10748 int mode = GET_MODE (x);
10751 if (mode != DImode && mode != DFmode)
10754 if (GET_CODE (x) != REG
10755 || !IS_VFP_REGNUM (REGNO (x)))
10758 num = REGNO(x) - FIRST_VFP_REGNUM;
10762 fprintf (stream, "d%d", num >> 1);
10770 if (GET_CODE (x) == REG)
10771 asm_fprintf (stream, "%r", REGNO (x));
10772 else if (GET_CODE (x) == MEM)
10774 output_memory_reference_mode = GET_MODE (x);
10775 output_address (XEXP (x, 0));
10777 else if (GET_CODE (x) == CONST_DOUBLE)
10778 fprintf (stream, "#%s", fp_immediate_constant (x));
10779 else if (GET_CODE (x) == NEG)
10780 abort (); /* This should never happen now. */
10783 fputc ('#', stream);
10784 output_addr_const (stream, x);
10789 #ifndef AOF_ASSEMBLER
10790 /* Target hook for assembling integer objects. The ARM version needs to
10791 handle word-sized values specially. */
10793 arm_assemble_integer (rtx x, unsigned int size, int aligned_p)
10795 if (size == UNITS_PER_WORD && aligned_p)
10797 fputs ("\t.word\t", asm_out_file);
10798 output_addr_const (asm_out_file, x);
10800 /* Mark symbols as position independent. We only do this in the
10801 .text segment, not in the .data segment. */
10802 if (NEED_GOT_RELOC && flag_pic && making_const_table &&
10803 (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == LABEL_REF))
10805 if (GET_CODE (x) == SYMBOL_REF
10806 && (CONSTANT_POOL_ADDRESS_P (x)
10807 || SYMBOL_REF_LOCAL_P (x)))
10808 fputs ("(GOTOFF)", asm_out_file);
10809 else if (GET_CODE (x) == LABEL_REF)
10810 fputs ("(GOTOFF)", asm_out_file);
10812 fputs ("(GOT)", asm_out_file);
10814 fputc ('\n', asm_out_file);
10818 if (VECTOR_MODE_SUPPORTED_P (GET_MODE (x)))
10822 if (GET_CODE (x) != CONST_VECTOR)
10825 units = CONST_VECTOR_NUNITS (x);
10827 switch (GET_MODE (x))
10829 case V2SImode: size = 4; break;
10830 case V4HImode: size = 2; break;
10831 case V8QImode: size = 1; break;
10836 for (i = 0; i < units; i++)
10840 elt = CONST_VECTOR_ELT (x, i);
10842 (elt, size, i == 0 ? BIGGEST_ALIGNMENT : size * BITS_PER_UNIT, 1);
10848 return default_assemble_integer (x, size, aligned_p);
10852 /* A finite state machine takes care of noticing whether or not instructions
10853 can be conditionally executed, and thus decrease execution time and code
10854 size by deleting branch instructions. The fsm is controlled by
10855 final_prescan_insn, and controls the actions of ASM_OUTPUT_OPCODE. */
10857 /* The state of the fsm controlling condition codes are:
10858 0: normal, do nothing special
10859 1: make ASM_OUTPUT_OPCODE not output this instruction
10860 2: make ASM_OUTPUT_OPCODE not output this instruction
10861 3: make instructions conditional
10862 4: make instructions conditional
10864 State transitions (state->state by whom under condition):
10865 0 -> 1 final_prescan_insn if the `target' is a label
10866 0 -> 2 final_prescan_insn if the `target' is an unconditional branch
10867 1 -> 3 ASM_OUTPUT_OPCODE after not having output the conditional branch
10868 2 -> 4 ASM_OUTPUT_OPCODE after not having output the conditional branch
10869 3 -> 0 (*targetm.asm_out.internal_label) if the `target' label is reached
10870 (the target label has CODE_LABEL_NUMBER equal to arm_target_label).
10871 4 -> 0 final_prescan_insn if the `target' unconditional branch is reached
10872 (the target insn is arm_target_insn).
10874 If the jump clobbers the conditions then we use states 2 and 4.
10876 A similar thing can be done with conditional return insns.
10878 XXX In case the `target' is an unconditional branch, this conditionalising
10879 of the instructions always reduces code size, but not always execution
10880 time. But then, I want to reduce the code size to somewhere near what
10881 /bin/cc produces. */
10883 /* Returns the index of the ARM condition code string in
10884 `arm_condition_codes'. COMPARISON should be an rtx like
10885 `(eq (...) (...))'. */
10886 static enum arm_cond_code
10887 get_arm_condition_code (rtx comparison)
10889 enum machine_mode mode = GET_MODE (XEXP (comparison, 0));
10891 enum rtx_code comp_code = GET_CODE (comparison);
10893 if (GET_MODE_CLASS (mode) != MODE_CC)
10894 mode = SELECT_CC_MODE (comp_code, XEXP (comparison, 0),
10895 XEXP (comparison, 1));
10899 case CC_DNEmode: code = ARM_NE; goto dominance;
10900 case CC_DEQmode: code = ARM_EQ; goto dominance;
10901 case CC_DGEmode: code = ARM_GE; goto dominance;
10902 case CC_DGTmode: code = ARM_GT; goto dominance;
10903 case CC_DLEmode: code = ARM_LE; goto dominance;
10904 case CC_DLTmode: code = ARM_LT; goto dominance;
10905 case CC_DGEUmode: code = ARM_CS; goto dominance;
10906 case CC_DGTUmode: code = ARM_HI; goto dominance;
10907 case CC_DLEUmode: code = ARM_LS; goto dominance;
10908 case CC_DLTUmode: code = ARM_CC;
10911 if (comp_code != EQ && comp_code != NE)
10914 if (comp_code == EQ)
10915 return ARM_INVERSE_CONDITION_CODE (code);
10921 case NE: return ARM_NE;
10922 case EQ: return ARM_EQ;
10923 case GE: return ARM_PL;
10924 case LT: return ARM_MI;
10931 case NE: return ARM_NE;
10932 case EQ: return ARM_EQ;
10939 case NE: return ARM_MI;
10940 case EQ: return ARM_PL;
10946 /* These encodings assume that AC=1 in the FPA system control
10947 byte. This allows us to handle all cases except UNEQ and
10951 case GE: return ARM_GE;
10952 case GT: return ARM_GT;
10953 case LE: return ARM_LS;
10954 case LT: return ARM_MI;
10955 case NE: return ARM_NE;
10956 case EQ: return ARM_EQ;
10957 case ORDERED: return ARM_VC;
10958 case UNORDERED: return ARM_VS;
10959 case UNLT: return ARM_LT;
10960 case UNLE: return ARM_LE;
10961 case UNGT: return ARM_HI;
10962 case UNGE: return ARM_PL;
10963 /* UNEQ and LTGT do not have a representation. */
10964 case UNEQ: /* Fall through. */
10965 case LTGT: /* Fall through. */
10972 case NE: return ARM_NE;
10973 case EQ: return ARM_EQ;
10974 case GE: return ARM_LE;
10975 case GT: return ARM_LT;
10976 case LE: return ARM_GE;
10977 case LT: return ARM_GT;
10978 case GEU: return ARM_LS;
10979 case GTU: return ARM_CC;
10980 case LEU: return ARM_CS;
10981 case LTU: return ARM_HI;
10988 case LTU: return ARM_CS;
10989 case GEU: return ARM_CC;
10996 case NE: return ARM_NE;
10997 case EQ: return ARM_EQ;
10998 case GE: return ARM_GE;
10999 case GT: return ARM_GT;
11000 case LE: return ARM_LE;
11001 case LT: return ARM_LT;
11002 case GEU: return ARM_CS;
11003 case GTU: return ARM_HI;
11004 case LEU: return ARM_LS;
11005 case LTU: return ARM_CC;
11016 arm_final_prescan_insn (rtx insn)
11018 /* BODY will hold the body of INSN. */
11019 rtx body = PATTERN (insn);
11021 /* This will be 1 if trying to repeat the trick, and things need to be
11022 reversed if it appears to fail. */
11025 /* JUMP_CLOBBERS will be one implies that the conditions if a branch is
11026 taken are clobbered, even if the rtl suggests otherwise. It also
11027 means that we have to grub around within the jump expression to find
11028 out what the conditions are when the jump isn't taken. */
11029 int jump_clobbers = 0;
11031 /* If we start with a return insn, we only succeed if we find another one. */
11032 int seeking_return = 0;
11034 /* START_INSN will hold the insn from where we start looking. This is the
11035 first insn after the following code_label if REVERSE is true. */
11036 rtx start_insn = insn;
11038 /* If in state 4, check if the target branch is reached, in order to
11039 change back to state 0. */
11040 if (arm_ccfsm_state == 4)
11042 if (insn == arm_target_insn)
11044 arm_target_insn = NULL;
11045 arm_ccfsm_state = 0;
11050 /* If in state 3, it is possible to repeat the trick, if this insn is an
11051 unconditional branch to a label, and immediately following this branch
11052 is the previous target label which is only used once, and the label this
11053 branch jumps to is not too far off. */
11054 if (arm_ccfsm_state == 3)
11056 if (simplejump_p (insn))
11058 start_insn = next_nonnote_insn (start_insn);
11059 if (GET_CODE (start_insn) == BARRIER)
11061 /* XXX Isn't this always a barrier? */
11062 start_insn = next_nonnote_insn (start_insn);
11064 if (GET_CODE (start_insn) == CODE_LABEL
11065 && CODE_LABEL_NUMBER (start_insn) == arm_target_label
11066 && LABEL_NUSES (start_insn) == 1)
11071 else if (GET_CODE (body) == RETURN)
11073 start_insn = next_nonnote_insn (start_insn);
11074 if (GET_CODE (start_insn) == BARRIER)
11075 start_insn = next_nonnote_insn (start_insn);
11076 if (GET_CODE (start_insn) == CODE_LABEL
11077 && CODE_LABEL_NUMBER (start_insn) == arm_target_label
11078 && LABEL_NUSES (start_insn) == 1)
11081 seeking_return = 1;
11090 if (arm_ccfsm_state != 0 && !reverse)
11092 if (GET_CODE (insn) != JUMP_INSN)
11095 /* This jump might be paralleled with a clobber of the condition codes
11096 the jump should always come first */
11097 if (GET_CODE (body) == PARALLEL && XVECLEN (body, 0) > 0)
11098 body = XVECEXP (body, 0, 0);
11101 || (GET_CODE (body) == SET && GET_CODE (SET_DEST (body)) == PC
11102 && GET_CODE (SET_SRC (body)) == IF_THEN_ELSE))
11105 int fail = FALSE, succeed = FALSE;
11106 /* Flag which part of the IF_THEN_ELSE is the LABEL_REF. */
11107 int then_not_else = TRUE;
11108 rtx this_insn = start_insn, label = 0;
11110 /* If the jump cannot be done with one instruction, we cannot
11111 conditionally execute the instruction in the inverse case. */
11112 if (get_attr_conds (insn) == CONDS_JUMP_CLOB)
11118 /* Register the insn jumped to. */
11121 if (!seeking_return)
11122 label = XEXP (SET_SRC (body), 0);
11124 else if (GET_CODE (XEXP (SET_SRC (body), 1)) == LABEL_REF)
11125 label = XEXP (XEXP (SET_SRC (body), 1), 0);
11126 else if (GET_CODE (XEXP (SET_SRC (body), 2)) == LABEL_REF)
11128 label = XEXP (XEXP (SET_SRC (body), 2), 0);
11129 then_not_else = FALSE;
11131 else if (GET_CODE (XEXP (SET_SRC (body), 1)) == RETURN)
11132 seeking_return = 1;
11133 else if (GET_CODE (XEXP (SET_SRC (body), 2)) == RETURN)
11135 seeking_return = 1;
11136 then_not_else = FALSE;
11141 /* See how many insns this branch skips, and what kind of insns. If all
11142 insns are okay, and the label or unconditional branch to the same
11143 label is not too far away, succeed. */
11144 for (insns_skipped = 0;
11145 !fail && !succeed && insns_skipped++ < max_insns_skipped;)
11149 this_insn = next_nonnote_insn (this_insn);
11153 switch (GET_CODE (this_insn))
11156 /* Succeed if it is the target label, otherwise fail since
11157 control falls in from somewhere else. */
11158 if (this_insn == label)
11162 arm_ccfsm_state = 2;
11163 this_insn = next_nonnote_insn (this_insn);
11166 arm_ccfsm_state = 1;
11174 /* Succeed if the following insn is the target label.
11176 If return insns are used then the last insn in a function
11177 will be a barrier. */
11178 this_insn = next_nonnote_insn (this_insn);
11179 if (this_insn && this_insn == label)
11183 arm_ccfsm_state = 2;
11184 this_insn = next_nonnote_insn (this_insn);
11187 arm_ccfsm_state = 1;
11195 /* If using 32-bit addresses the cc is not preserved over
11197 if (TARGET_APCS_32)
11199 /* Succeed if the following insn is the target label,
11200 or if the following two insns are a barrier and
11201 the target label. */
11202 this_insn = next_nonnote_insn (this_insn);
11203 if (this_insn && GET_CODE (this_insn) == BARRIER)
11204 this_insn = next_nonnote_insn (this_insn);
11206 if (this_insn && this_insn == label
11207 && insns_skipped < max_insns_skipped)
11211 arm_ccfsm_state = 2;
11212 this_insn = next_nonnote_insn (this_insn);
11215 arm_ccfsm_state = 1;
11224 /* If this is an unconditional branch to the same label, succeed.
11225 If it is to another label, do nothing. If it is conditional,
11227 /* XXX Probably, the tests for SET and the PC are
11230 scanbody = PATTERN (this_insn);
11231 if (GET_CODE (scanbody) == SET
11232 && GET_CODE (SET_DEST (scanbody)) == PC)
11234 if (GET_CODE (SET_SRC (scanbody)) == LABEL_REF
11235 && XEXP (SET_SRC (scanbody), 0) == label && !reverse)
11237 arm_ccfsm_state = 2;
11240 else if (GET_CODE (SET_SRC (scanbody)) == IF_THEN_ELSE)
11243 /* Fail if a conditional return is undesirable (eg on a
11244 StrongARM), but still allow this if optimizing for size. */
11245 else if (GET_CODE (scanbody) == RETURN
11246 && !use_return_insn (TRUE, NULL)
11249 else if (GET_CODE (scanbody) == RETURN
11252 arm_ccfsm_state = 2;
11255 else if (GET_CODE (scanbody) == PARALLEL)
11257 switch (get_attr_conds (this_insn))
11267 fail = TRUE; /* Unrecognized jump (eg epilogue). */
11272 /* Instructions using or affecting the condition codes make it
11274 scanbody = PATTERN (this_insn);
11275 if (!(GET_CODE (scanbody) == SET
11276 || GET_CODE (scanbody) == PARALLEL)
11277 || get_attr_conds (this_insn) != CONDS_NOCOND)
11280 /* A conditional cirrus instruction must be followed by
11281 a non Cirrus instruction. However, since we
11282 conditionalize instructions in this function and by
11283 the time we get here we can't add instructions
11284 (nops), because shorten_branches() has already been
11285 called, we will disable conditionalizing Cirrus
11286 instructions to be safe. */
11287 if (GET_CODE (scanbody) != USE
11288 && GET_CODE (scanbody) != CLOBBER
11289 && get_attr_cirrus (this_insn) != CIRRUS_NOT)
11299 if ((!seeking_return) && (arm_ccfsm_state == 1 || reverse))
11300 arm_target_label = CODE_LABEL_NUMBER (label);
11301 else if (seeking_return || arm_ccfsm_state == 2)
11303 while (this_insn && GET_CODE (PATTERN (this_insn)) == USE)
11305 this_insn = next_nonnote_insn (this_insn);
11306 if (this_insn && (GET_CODE (this_insn) == BARRIER
11307 || GET_CODE (this_insn) == CODE_LABEL))
11312 /* Oh, dear! we ran off the end.. give up. */
11313 recog (PATTERN (insn), insn, NULL);
11314 arm_ccfsm_state = 0;
11315 arm_target_insn = NULL;
11318 arm_target_insn = this_insn;
11327 get_arm_condition_code (XEXP (XEXP (XEXP (SET_SRC (body),
11329 if (GET_CODE (XEXP (XEXP (SET_SRC (body), 0), 0)) == AND)
11330 arm_current_cc = ARM_INVERSE_CONDITION_CODE (arm_current_cc);
11331 if (GET_CODE (XEXP (SET_SRC (body), 0)) == NE)
11332 arm_current_cc = ARM_INVERSE_CONDITION_CODE (arm_current_cc);
11336 /* If REVERSE is true, ARM_CURRENT_CC needs to be inverted from
11339 arm_current_cc = get_arm_condition_code (XEXP (SET_SRC (body),
11343 if (reverse || then_not_else)
11344 arm_current_cc = ARM_INVERSE_CONDITION_CODE (arm_current_cc);
11347 /* Restore recog_data (getting the attributes of other insns can
11348 destroy this array, but final.c assumes that it remains intact
11349 across this call; since the insn has been recognized already we
11350 call recog direct). */
11351 recog (PATTERN (insn), insn, NULL);
11355 /* Returns true if REGNO is a valid register
11356 for holding a quantity of tyoe MODE. */
11358 arm_hard_regno_mode_ok (unsigned int regno, enum machine_mode mode)
11360 if (GET_MODE_CLASS (mode) == MODE_CC)
11361 return regno == CC_REGNUM || regno == VFPCC_REGNUM;
11364 /* For the Thumb we only allow values bigger than SImode in
11365 registers 0 - 6, so that there is always a second low
11366 register available to hold the upper part of the value.
11367 We probably we ought to ensure that the register is the
11368 start of an even numbered register pair. */
11369 return (ARM_NUM_REGS (mode) < 2) || (regno < LAST_LO_REGNUM);
11371 if (IS_CIRRUS_REGNUM (regno))
11372 /* We have outlawed SI values in Cirrus registers because they
11373 reside in the lower 32 bits, but SF values reside in the
11374 upper 32 bits. This causes gcc all sorts of grief. We can't
11375 even split the registers into pairs because Cirrus SI values
11376 get sign extended to 64bits-- aldyh. */
11377 return (GET_MODE_CLASS (mode) == MODE_FLOAT) || (mode == DImode);
11379 if (IS_VFP_REGNUM (regno))
11381 if (mode == SFmode || mode == SImode)
11384 /* DFmode values are only valid in even register pairs. */
11385 if (mode == DFmode)
11386 return ((regno - FIRST_VFP_REGNUM) & 1) == 0;
11390 if (IS_IWMMXT_GR_REGNUM (regno))
11391 return mode == SImode;
11393 if (IS_IWMMXT_REGNUM (regno))
11394 return VALID_IWMMXT_REG_MODE (mode);
11396 if (regno <= LAST_ARM_REGNUM)
11397 /* We allow any value to be stored in the general registers. */
11400 if ( regno == FRAME_POINTER_REGNUM
11401 || regno == ARG_POINTER_REGNUM)
11402 /* We only allow integers in the fake hard registers. */
11403 return GET_MODE_CLASS (mode) == MODE_INT;
11405 /* The only registers left are the FPA registers
11406 which we only allow to hold FP values. */
11407 return GET_MODE_CLASS (mode) == MODE_FLOAT
11408 && regno >= FIRST_FPA_REGNUM
11409 && regno <= LAST_FPA_REGNUM;
11413 arm_regno_class (int regno)
11417 if (regno == STACK_POINTER_REGNUM)
11419 if (regno == CC_REGNUM)
11426 if ( regno <= LAST_ARM_REGNUM
11427 || regno == FRAME_POINTER_REGNUM
11428 || regno == ARG_POINTER_REGNUM)
11429 return GENERAL_REGS;
11431 if (regno == CC_REGNUM || regno == VFPCC_REGNUM)
11434 if (IS_CIRRUS_REGNUM (regno))
11435 return CIRRUS_REGS;
11437 if (IS_VFP_REGNUM (regno))
11440 if (IS_IWMMXT_REGNUM (regno))
11441 return IWMMXT_REGS;
11443 if (IS_IWMMXT_GR_REGNUM (regno))
11444 return IWMMXT_GR_REGS;
11449 /* Handle a special case when computing the offset
11450 of an argument from the frame pointer. */
11452 arm_debugger_arg_offset (int value, rtx addr)
11456 /* We are only interested if dbxout_parms() failed to compute the offset. */
11460 /* We can only cope with the case where the address is held in a register. */
11461 if (GET_CODE (addr) != REG)
11464 /* If we are using the frame pointer to point at the argument, then
11465 an offset of 0 is correct. */
11466 if (REGNO (addr) == (unsigned) HARD_FRAME_POINTER_REGNUM)
11469 /* If we are using the stack pointer to point at the
11470 argument, then an offset of 0 is correct. */
11471 if ((TARGET_THUMB || !frame_pointer_needed)
11472 && REGNO (addr) == SP_REGNUM)
11475 /* Oh dear. The argument is pointed to by a register rather
11476 than being held in a register, or being stored at a known
11477 offset from the frame pointer. Since GDB only understands
11478 those two kinds of argument we must translate the address
11479 held in the register into an offset from the frame pointer.
11480 We do this by searching through the insns for the function
11481 looking to see where this register gets its value. If the
11482 register is initialized from the frame pointer plus an offset
11483 then we are in luck and we can continue, otherwise we give up.
11485 This code is exercised by producing debugging information
11486 for a function with arguments like this:
11488 double func (double a, double b, int c, double d) {return d;}
11490 Without this code the stab for parameter 'd' will be set to
11491 an offset of 0 from the frame pointer, rather than 8. */
11493 /* The if() statement says:
11495 If the insn is a normal instruction
11496 and if the insn is setting the value in a register
11497 and if the register being set is the register holding the address of the argument
11498 and if the address is computing by an addition
11499 that involves adding to a register
11500 which is the frame pointer
11505 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
11507 if ( GET_CODE (insn) == INSN
11508 && GET_CODE (PATTERN (insn)) == SET
11509 && REGNO (XEXP (PATTERN (insn), 0)) == REGNO (addr)
11510 && GET_CODE (XEXP (PATTERN (insn), 1)) == PLUS
11511 && GET_CODE (XEXP (XEXP (PATTERN (insn), 1), 0)) == REG
11512 && REGNO (XEXP (XEXP (PATTERN (insn), 1), 0)) == (unsigned) HARD_FRAME_POINTER_REGNUM
11513 && GET_CODE (XEXP (XEXP (PATTERN (insn), 1), 1)) == CONST_INT
11516 value = INTVAL (XEXP (XEXP (PATTERN (insn), 1), 1));
11525 warning ("unable to compute real location of stacked parameter");
11526 value = 8; /* XXX magic hack */
11532 #define def_mbuiltin(MASK, NAME, TYPE, CODE) \
11535 if ((MASK) & insn_flags) \
11536 builtin_function ((NAME), (TYPE), (CODE), BUILT_IN_MD, NULL, NULL_TREE); \
11540 struct builtin_description
11542 const unsigned int mask;
11543 const enum insn_code icode;
11544 const char * const name;
11545 const enum arm_builtins code;
11546 const enum rtx_code comparison;
11547 const unsigned int flag;
11550 static const struct builtin_description bdesc_2arg[] =
11552 #define IWMMXT_BUILTIN(code, string, builtin) \
11553 { FL_IWMMXT, CODE_FOR_##code, "__builtin_arm_" string, \
11554 ARM_BUILTIN_##builtin, 0, 0 },
11556 IWMMXT_BUILTIN (addv8qi3, "waddb", WADDB)
11557 IWMMXT_BUILTIN (addv4hi3, "waddh", WADDH)
11558 IWMMXT_BUILTIN (addv2si3, "waddw", WADDW)
11559 IWMMXT_BUILTIN (subv8qi3, "wsubb", WSUBB)
11560 IWMMXT_BUILTIN (subv4hi3, "wsubh", WSUBH)
11561 IWMMXT_BUILTIN (subv2si3, "wsubw", WSUBW)
11562 IWMMXT_BUILTIN (ssaddv8qi3, "waddbss", WADDSSB)
11563 IWMMXT_BUILTIN (ssaddv4hi3, "waddhss", WADDSSH)
11564 IWMMXT_BUILTIN (ssaddv2si3, "waddwss", WADDSSW)
11565 IWMMXT_BUILTIN (sssubv8qi3, "wsubbss", WSUBSSB)
11566 IWMMXT_BUILTIN (sssubv4hi3, "wsubhss", WSUBSSH)
11567 IWMMXT_BUILTIN (sssubv2si3, "wsubwss", WSUBSSW)
11568 IWMMXT_BUILTIN (usaddv8qi3, "waddbus", WADDUSB)
11569 IWMMXT_BUILTIN (usaddv4hi3, "waddhus", WADDUSH)
11570 IWMMXT_BUILTIN (usaddv2si3, "waddwus", WADDUSW)
11571 IWMMXT_BUILTIN (ussubv8qi3, "wsubbus", WSUBUSB)
11572 IWMMXT_BUILTIN (ussubv4hi3, "wsubhus", WSUBUSH)
11573 IWMMXT_BUILTIN (ussubv2si3, "wsubwus", WSUBUSW)
11574 IWMMXT_BUILTIN (mulv4hi3, "wmulul", WMULUL)
11575 IWMMXT_BUILTIN (smulv4hi3_highpart, "wmulsm", WMULSM)
11576 IWMMXT_BUILTIN (umulv4hi3_highpart, "wmulum", WMULUM)
11577 IWMMXT_BUILTIN (eqv8qi3, "wcmpeqb", WCMPEQB)
11578 IWMMXT_BUILTIN (eqv4hi3, "wcmpeqh", WCMPEQH)
11579 IWMMXT_BUILTIN (eqv2si3, "wcmpeqw", WCMPEQW)
11580 IWMMXT_BUILTIN (gtuv8qi3, "wcmpgtub", WCMPGTUB)
11581 IWMMXT_BUILTIN (gtuv4hi3, "wcmpgtuh", WCMPGTUH)
11582 IWMMXT_BUILTIN (gtuv2si3, "wcmpgtuw", WCMPGTUW)
11583 IWMMXT_BUILTIN (gtv8qi3, "wcmpgtsb", WCMPGTSB)
11584 IWMMXT_BUILTIN (gtv4hi3, "wcmpgtsh", WCMPGTSH)
11585 IWMMXT_BUILTIN (gtv2si3, "wcmpgtsw", WCMPGTSW)
11586 IWMMXT_BUILTIN (umaxv8qi3, "wmaxub", WMAXUB)
11587 IWMMXT_BUILTIN (smaxv8qi3, "wmaxsb", WMAXSB)
11588 IWMMXT_BUILTIN (umaxv4hi3, "wmaxuh", WMAXUH)
11589 IWMMXT_BUILTIN (smaxv4hi3, "wmaxsh", WMAXSH)
11590 IWMMXT_BUILTIN (umaxv2si3, "wmaxuw", WMAXUW)
11591 IWMMXT_BUILTIN (smaxv2si3, "wmaxsw", WMAXSW)
11592 IWMMXT_BUILTIN (uminv8qi3, "wminub", WMINUB)
11593 IWMMXT_BUILTIN (sminv8qi3, "wminsb", WMINSB)
11594 IWMMXT_BUILTIN (uminv4hi3, "wminuh", WMINUH)
11595 IWMMXT_BUILTIN (sminv4hi3, "wminsh", WMINSH)
11596 IWMMXT_BUILTIN (uminv2si3, "wminuw", WMINUW)
11597 IWMMXT_BUILTIN (sminv2si3, "wminsw", WMINSW)
11598 IWMMXT_BUILTIN (iwmmxt_anddi3, "wand", WAND)
11599 IWMMXT_BUILTIN (iwmmxt_nanddi3, "wandn", WANDN)
11600 IWMMXT_BUILTIN (iwmmxt_iordi3, "wor", WOR)
11601 IWMMXT_BUILTIN (iwmmxt_xordi3, "wxor", WXOR)
11602 IWMMXT_BUILTIN (iwmmxt_uavgv8qi3, "wavg2b", WAVG2B)
11603 IWMMXT_BUILTIN (iwmmxt_uavgv4hi3, "wavg2h", WAVG2H)
11604 IWMMXT_BUILTIN (iwmmxt_uavgrndv8qi3, "wavg2br", WAVG2BR)
11605 IWMMXT_BUILTIN (iwmmxt_uavgrndv4hi3, "wavg2hr", WAVG2HR)
11606 IWMMXT_BUILTIN (iwmmxt_wunpckilb, "wunpckilb", WUNPCKILB)
11607 IWMMXT_BUILTIN (iwmmxt_wunpckilh, "wunpckilh", WUNPCKILH)
11608 IWMMXT_BUILTIN (iwmmxt_wunpckilw, "wunpckilw", WUNPCKILW)
11609 IWMMXT_BUILTIN (iwmmxt_wunpckihb, "wunpckihb", WUNPCKIHB)
11610 IWMMXT_BUILTIN (iwmmxt_wunpckihh, "wunpckihh", WUNPCKIHH)
11611 IWMMXT_BUILTIN (iwmmxt_wunpckihw, "wunpckihw", WUNPCKIHW)
11612 IWMMXT_BUILTIN (iwmmxt_wmadds, "wmadds", WMADDS)
11613 IWMMXT_BUILTIN (iwmmxt_wmaddu, "wmaddu", WMADDU)
11615 #define IWMMXT_BUILTIN2(code, builtin) \
11616 { FL_IWMMXT, CODE_FOR_##code, NULL, ARM_BUILTIN_##builtin, 0, 0 },
11618 IWMMXT_BUILTIN2 (iwmmxt_wpackhss, WPACKHSS)
11619 IWMMXT_BUILTIN2 (iwmmxt_wpackwss, WPACKWSS)
11620 IWMMXT_BUILTIN2 (iwmmxt_wpackdss, WPACKDSS)
11621 IWMMXT_BUILTIN2 (iwmmxt_wpackhus, WPACKHUS)
11622 IWMMXT_BUILTIN2 (iwmmxt_wpackwus, WPACKWUS)
11623 IWMMXT_BUILTIN2 (iwmmxt_wpackdus, WPACKDUS)
11624 IWMMXT_BUILTIN2 (ashlv4hi3_di, WSLLH)
11625 IWMMXT_BUILTIN2 (ashlv4hi3, WSLLHI)
11626 IWMMXT_BUILTIN2 (ashlv2si3_di, WSLLW)
11627 IWMMXT_BUILTIN2 (ashlv2si3, WSLLWI)
11628 IWMMXT_BUILTIN2 (ashldi3_di, WSLLD)
11629 IWMMXT_BUILTIN2 (ashldi3_iwmmxt, WSLLDI)
11630 IWMMXT_BUILTIN2 (lshrv4hi3_di, WSRLH)
11631 IWMMXT_BUILTIN2 (lshrv4hi3, WSRLHI)
11632 IWMMXT_BUILTIN2 (lshrv2si3_di, WSRLW)
11633 IWMMXT_BUILTIN2 (lshrv2si3, WSRLWI)
11634 IWMMXT_BUILTIN2 (lshrdi3_di, WSRLD)
11635 IWMMXT_BUILTIN2 (lshrdi3_iwmmxt, WSRLDI)
11636 IWMMXT_BUILTIN2 (ashrv4hi3_di, WSRAH)
11637 IWMMXT_BUILTIN2 (ashrv4hi3, WSRAHI)
11638 IWMMXT_BUILTIN2 (ashrv2si3_di, WSRAW)
11639 IWMMXT_BUILTIN2 (ashrv2si3, WSRAWI)
11640 IWMMXT_BUILTIN2 (ashrdi3_di, WSRAD)
11641 IWMMXT_BUILTIN2 (ashrdi3_iwmmxt, WSRADI)
11642 IWMMXT_BUILTIN2 (rorv4hi3_di, WRORH)
11643 IWMMXT_BUILTIN2 (rorv4hi3, WRORHI)
11644 IWMMXT_BUILTIN2 (rorv2si3_di, WRORW)
11645 IWMMXT_BUILTIN2 (rorv2si3, WRORWI)
11646 IWMMXT_BUILTIN2 (rordi3_di, WRORD)
11647 IWMMXT_BUILTIN2 (rordi3, WRORDI)
11648 IWMMXT_BUILTIN2 (iwmmxt_wmacuz, WMACUZ)
11649 IWMMXT_BUILTIN2 (iwmmxt_wmacsz, WMACSZ)
11652 static const struct builtin_description bdesc_1arg[] =
11654 IWMMXT_BUILTIN (iwmmxt_tmovmskb, "tmovmskb", TMOVMSKB)
11655 IWMMXT_BUILTIN (iwmmxt_tmovmskh, "tmovmskh", TMOVMSKH)
11656 IWMMXT_BUILTIN (iwmmxt_tmovmskw, "tmovmskw", TMOVMSKW)
11657 IWMMXT_BUILTIN (iwmmxt_waccb, "waccb", WACCB)
11658 IWMMXT_BUILTIN (iwmmxt_wacch, "wacch", WACCH)
11659 IWMMXT_BUILTIN (iwmmxt_waccw, "waccw", WACCW)
11660 IWMMXT_BUILTIN (iwmmxt_wunpckehub, "wunpckehub", WUNPCKEHUB)
11661 IWMMXT_BUILTIN (iwmmxt_wunpckehuh, "wunpckehuh", WUNPCKEHUH)
11662 IWMMXT_BUILTIN (iwmmxt_wunpckehuw, "wunpckehuw", WUNPCKEHUW)
11663 IWMMXT_BUILTIN (iwmmxt_wunpckehsb, "wunpckehsb", WUNPCKEHSB)
11664 IWMMXT_BUILTIN (iwmmxt_wunpckehsh, "wunpckehsh", WUNPCKEHSH)
11665 IWMMXT_BUILTIN (iwmmxt_wunpckehsw, "wunpckehsw", WUNPCKEHSW)
11666 IWMMXT_BUILTIN (iwmmxt_wunpckelub, "wunpckelub", WUNPCKELUB)
11667 IWMMXT_BUILTIN (iwmmxt_wunpckeluh, "wunpckeluh", WUNPCKELUH)
11668 IWMMXT_BUILTIN (iwmmxt_wunpckeluw, "wunpckeluw", WUNPCKELUW)
11669 IWMMXT_BUILTIN (iwmmxt_wunpckelsb, "wunpckelsb", WUNPCKELSB)
11670 IWMMXT_BUILTIN (iwmmxt_wunpckelsh, "wunpckelsh", WUNPCKELSH)
11671 IWMMXT_BUILTIN (iwmmxt_wunpckelsw, "wunpckelsw", WUNPCKELSW)
11674 /* Set up all the iWMMXt builtins. This is
11675 not called if TARGET_IWMMXT is zero. */
11678 arm_init_iwmmxt_builtins (void)
11680 const struct builtin_description * d;
11682 tree endlink = void_list_node;
11684 tree V2SI_type_node = build_vector_type_for_mode (intSI_type_node, V2SImode);
11685 tree V4HI_type_node = build_vector_type_for_mode (intHI_type_node, V4HImode);
11686 tree V8QI_type_node = build_vector_type_for_mode (intQI_type_node, V8QImode);
11689 = build_function_type (integer_type_node,
11690 tree_cons (NULL_TREE, integer_type_node, endlink));
11691 tree v8qi_ftype_v8qi_v8qi_int
11692 = build_function_type (V8QI_type_node,
11693 tree_cons (NULL_TREE, V8QI_type_node,
11694 tree_cons (NULL_TREE, V8QI_type_node,
11695 tree_cons (NULL_TREE,
11698 tree v4hi_ftype_v4hi_int
11699 = build_function_type (V4HI_type_node,
11700 tree_cons (NULL_TREE, V4HI_type_node,
11701 tree_cons (NULL_TREE, integer_type_node,
11703 tree v2si_ftype_v2si_int
11704 = build_function_type (V2SI_type_node,
11705 tree_cons (NULL_TREE, V2SI_type_node,
11706 tree_cons (NULL_TREE, integer_type_node,
11708 tree v2si_ftype_di_di
11709 = build_function_type (V2SI_type_node,
11710 tree_cons (NULL_TREE, long_long_integer_type_node,
11711 tree_cons (NULL_TREE, long_long_integer_type_node,
11713 tree di_ftype_di_int
11714 = build_function_type (long_long_integer_type_node,
11715 tree_cons (NULL_TREE, long_long_integer_type_node,
11716 tree_cons (NULL_TREE, integer_type_node,
11718 tree di_ftype_di_int_int
11719 = build_function_type (long_long_integer_type_node,
11720 tree_cons (NULL_TREE, long_long_integer_type_node,
11721 tree_cons (NULL_TREE, integer_type_node,
11722 tree_cons (NULL_TREE,
11725 tree int_ftype_v8qi
11726 = build_function_type (integer_type_node,
11727 tree_cons (NULL_TREE, V8QI_type_node,
11729 tree int_ftype_v4hi
11730 = build_function_type (integer_type_node,
11731 tree_cons (NULL_TREE, V4HI_type_node,
11733 tree int_ftype_v2si
11734 = build_function_type (integer_type_node,
11735 tree_cons (NULL_TREE, V2SI_type_node,
11737 tree int_ftype_v8qi_int
11738 = build_function_type (integer_type_node,
11739 tree_cons (NULL_TREE, V8QI_type_node,
11740 tree_cons (NULL_TREE, integer_type_node,
11742 tree int_ftype_v4hi_int
11743 = build_function_type (integer_type_node,
11744 tree_cons (NULL_TREE, V4HI_type_node,
11745 tree_cons (NULL_TREE, integer_type_node,
11747 tree int_ftype_v2si_int
11748 = build_function_type (integer_type_node,
11749 tree_cons (NULL_TREE, V2SI_type_node,
11750 tree_cons (NULL_TREE, integer_type_node,
11752 tree v8qi_ftype_v8qi_int_int
11753 = build_function_type (V8QI_type_node,
11754 tree_cons (NULL_TREE, V8QI_type_node,
11755 tree_cons (NULL_TREE, integer_type_node,
11756 tree_cons (NULL_TREE,
11759 tree v4hi_ftype_v4hi_int_int
11760 = build_function_type (V4HI_type_node,
11761 tree_cons (NULL_TREE, V4HI_type_node,
11762 tree_cons (NULL_TREE, integer_type_node,
11763 tree_cons (NULL_TREE,
11766 tree v2si_ftype_v2si_int_int
11767 = build_function_type (V2SI_type_node,
11768 tree_cons (NULL_TREE, V2SI_type_node,
11769 tree_cons (NULL_TREE, integer_type_node,
11770 tree_cons (NULL_TREE,
11773 /* Miscellaneous. */
11774 tree v8qi_ftype_v4hi_v4hi
11775 = build_function_type (V8QI_type_node,
11776 tree_cons (NULL_TREE, V4HI_type_node,
11777 tree_cons (NULL_TREE, V4HI_type_node,
11779 tree v4hi_ftype_v2si_v2si
11780 = build_function_type (V4HI_type_node,
11781 tree_cons (NULL_TREE, V2SI_type_node,
11782 tree_cons (NULL_TREE, V2SI_type_node,
11784 tree v2si_ftype_v4hi_v4hi
11785 = build_function_type (V2SI_type_node,
11786 tree_cons (NULL_TREE, V4HI_type_node,
11787 tree_cons (NULL_TREE, V4HI_type_node,
11789 tree v2si_ftype_v8qi_v8qi
11790 = build_function_type (V2SI_type_node,
11791 tree_cons (NULL_TREE, V8QI_type_node,
11792 tree_cons (NULL_TREE, V8QI_type_node,
11794 tree v4hi_ftype_v4hi_di
11795 = build_function_type (V4HI_type_node,
11796 tree_cons (NULL_TREE, V4HI_type_node,
11797 tree_cons (NULL_TREE,
11798 long_long_integer_type_node,
11800 tree v2si_ftype_v2si_di
11801 = build_function_type (V2SI_type_node,
11802 tree_cons (NULL_TREE, V2SI_type_node,
11803 tree_cons (NULL_TREE,
11804 long_long_integer_type_node,
11806 tree void_ftype_int_int
11807 = build_function_type (void_type_node,
11808 tree_cons (NULL_TREE, integer_type_node,
11809 tree_cons (NULL_TREE, integer_type_node,
11812 = build_function_type (long_long_unsigned_type_node, endlink);
11814 = build_function_type (long_long_integer_type_node,
11815 tree_cons (NULL_TREE, V8QI_type_node,
11818 = build_function_type (long_long_integer_type_node,
11819 tree_cons (NULL_TREE, V4HI_type_node,
11822 = build_function_type (long_long_integer_type_node,
11823 tree_cons (NULL_TREE, V2SI_type_node,
11825 tree v2si_ftype_v4hi
11826 = build_function_type (V2SI_type_node,
11827 tree_cons (NULL_TREE, V4HI_type_node,
11829 tree v4hi_ftype_v8qi
11830 = build_function_type (V4HI_type_node,
11831 tree_cons (NULL_TREE, V8QI_type_node,
11834 tree di_ftype_di_v4hi_v4hi
11835 = build_function_type (long_long_unsigned_type_node,
11836 tree_cons (NULL_TREE,
11837 long_long_unsigned_type_node,
11838 tree_cons (NULL_TREE, V4HI_type_node,
11839 tree_cons (NULL_TREE,
11843 tree di_ftype_v4hi_v4hi
11844 = build_function_type (long_long_unsigned_type_node,
11845 tree_cons (NULL_TREE, V4HI_type_node,
11846 tree_cons (NULL_TREE, V4HI_type_node,
11849 /* Normal vector binops. */
11850 tree v8qi_ftype_v8qi_v8qi
11851 = build_function_type (V8QI_type_node,
11852 tree_cons (NULL_TREE, V8QI_type_node,
11853 tree_cons (NULL_TREE, V8QI_type_node,
11855 tree v4hi_ftype_v4hi_v4hi
11856 = build_function_type (V4HI_type_node,
11857 tree_cons (NULL_TREE, V4HI_type_node,
11858 tree_cons (NULL_TREE, V4HI_type_node,
11860 tree v2si_ftype_v2si_v2si
11861 = build_function_type (V2SI_type_node,
11862 tree_cons (NULL_TREE, V2SI_type_node,
11863 tree_cons (NULL_TREE, V2SI_type_node,
11865 tree di_ftype_di_di
11866 = build_function_type (long_long_unsigned_type_node,
11867 tree_cons (NULL_TREE, long_long_unsigned_type_node,
11868 tree_cons (NULL_TREE,
11869 long_long_unsigned_type_node,
11872 /* Add all builtins that are more or less simple operations on two
11874 for (i = 0, d = bdesc_2arg; i < ARRAY_SIZE (bdesc_2arg); i++, d++)
11876 /* Use one of the operands; the target can have a different mode for
11877 mask-generating compares. */
11878 enum machine_mode mode;
11884 mode = insn_data[d->icode].operand[1].mode;
11889 type = v8qi_ftype_v8qi_v8qi;
11892 type = v4hi_ftype_v4hi_v4hi;
11895 type = v2si_ftype_v2si_v2si;
11898 type = di_ftype_di_di;
11905 def_mbuiltin (d->mask, d->name, type, d->code);
11908 /* Add the remaining MMX insns with somewhat more complicated types. */
11909 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wzero", di_ftype_void, ARM_BUILTIN_WZERO);
11910 def_mbuiltin (FL_IWMMXT, "__builtin_arm_setwcx", void_ftype_int_int, ARM_BUILTIN_SETWCX);
11911 def_mbuiltin (FL_IWMMXT, "__builtin_arm_getwcx", int_ftype_int, ARM_BUILTIN_GETWCX);
11913 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsllh", v4hi_ftype_v4hi_di, ARM_BUILTIN_WSLLH);
11914 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsllw", v2si_ftype_v2si_di, ARM_BUILTIN_WSLLW);
11915 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wslld", di_ftype_di_di, ARM_BUILTIN_WSLLD);
11916 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsllhi", v4hi_ftype_v4hi_int, ARM_BUILTIN_WSLLHI);
11917 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsllwi", v2si_ftype_v2si_int, ARM_BUILTIN_WSLLWI);
11918 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wslldi", di_ftype_di_int, ARM_BUILTIN_WSLLDI);
11920 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrlh", v4hi_ftype_v4hi_di, ARM_BUILTIN_WSRLH);
11921 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrlw", v2si_ftype_v2si_di, ARM_BUILTIN_WSRLW);
11922 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrld", di_ftype_di_di, ARM_BUILTIN_WSRLD);
11923 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrlhi", v4hi_ftype_v4hi_int, ARM_BUILTIN_WSRLHI);
11924 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrlwi", v2si_ftype_v2si_int, ARM_BUILTIN_WSRLWI);
11925 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrldi", di_ftype_di_int, ARM_BUILTIN_WSRLDI);
11927 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrah", v4hi_ftype_v4hi_di, ARM_BUILTIN_WSRAH);
11928 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsraw", v2si_ftype_v2si_di, ARM_BUILTIN_WSRAW);
11929 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrad", di_ftype_di_di, ARM_BUILTIN_WSRAD);
11930 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrahi", v4hi_ftype_v4hi_int, ARM_BUILTIN_WSRAHI);
11931 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrawi", v2si_ftype_v2si_int, ARM_BUILTIN_WSRAWI);
11932 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsradi", di_ftype_di_int, ARM_BUILTIN_WSRADI);
11934 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wrorh", v4hi_ftype_v4hi_di, ARM_BUILTIN_WRORH);
11935 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wrorw", v2si_ftype_v2si_di, ARM_BUILTIN_WRORW);
11936 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wrord", di_ftype_di_di, ARM_BUILTIN_WRORD);
11937 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wrorhi", v4hi_ftype_v4hi_int, ARM_BUILTIN_WRORHI);
11938 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wrorwi", v2si_ftype_v2si_int, ARM_BUILTIN_WRORWI);
11939 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wrordi", di_ftype_di_int, ARM_BUILTIN_WRORDI);
11941 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wshufh", v4hi_ftype_v4hi_int, ARM_BUILTIN_WSHUFH);
11943 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsadb", v2si_ftype_v8qi_v8qi, ARM_BUILTIN_WSADB);
11944 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsadh", v2si_ftype_v4hi_v4hi, ARM_BUILTIN_WSADH);
11945 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsadbz", v2si_ftype_v8qi_v8qi, ARM_BUILTIN_WSADBZ);
11946 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsadhz", v2si_ftype_v4hi_v4hi, ARM_BUILTIN_WSADHZ);
11948 def_mbuiltin (FL_IWMMXT, "__builtin_arm_textrmsb", int_ftype_v8qi_int, ARM_BUILTIN_TEXTRMSB);
11949 def_mbuiltin (FL_IWMMXT, "__builtin_arm_textrmsh", int_ftype_v4hi_int, ARM_BUILTIN_TEXTRMSH);
11950 def_mbuiltin (FL_IWMMXT, "__builtin_arm_textrmsw", int_ftype_v2si_int, ARM_BUILTIN_TEXTRMSW);
11951 def_mbuiltin (FL_IWMMXT, "__builtin_arm_textrmub", int_ftype_v8qi_int, ARM_BUILTIN_TEXTRMUB);
11952 def_mbuiltin (FL_IWMMXT, "__builtin_arm_textrmuh", int_ftype_v4hi_int, ARM_BUILTIN_TEXTRMUH);
11953 def_mbuiltin (FL_IWMMXT, "__builtin_arm_textrmuw", int_ftype_v2si_int, ARM_BUILTIN_TEXTRMUW);
11954 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tinsrb", v8qi_ftype_v8qi_int_int, ARM_BUILTIN_TINSRB);
11955 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tinsrh", v4hi_ftype_v4hi_int_int, ARM_BUILTIN_TINSRH);
11956 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tinsrw", v2si_ftype_v2si_int_int, ARM_BUILTIN_TINSRW);
11958 def_mbuiltin (FL_IWMMXT, "__builtin_arm_waccb", di_ftype_v8qi, ARM_BUILTIN_WACCB);
11959 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wacch", di_ftype_v4hi, ARM_BUILTIN_WACCH);
11960 def_mbuiltin (FL_IWMMXT, "__builtin_arm_waccw", di_ftype_v2si, ARM_BUILTIN_WACCW);
11962 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmovmskb", int_ftype_v8qi, ARM_BUILTIN_TMOVMSKB);
11963 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmovmskh", int_ftype_v4hi, ARM_BUILTIN_TMOVMSKH);
11964 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmovmskw", int_ftype_v2si, ARM_BUILTIN_TMOVMSKW);
11966 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wpackhss", v8qi_ftype_v4hi_v4hi, ARM_BUILTIN_WPACKHSS);
11967 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wpackhus", v8qi_ftype_v4hi_v4hi, ARM_BUILTIN_WPACKHUS);
11968 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wpackwus", v4hi_ftype_v2si_v2si, ARM_BUILTIN_WPACKWUS);
11969 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wpackwss", v4hi_ftype_v2si_v2si, ARM_BUILTIN_WPACKWSS);
11970 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wpackdus", v2si_ftype_di_di, ARM_BUILTIN_WPACKDUS);
11971 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wpackdss", v2si_ftype_di_di, ARM_BUILTIN_WPACKDSS);
11973 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckehub", v4hi_ftype_v8qi, ARM_BUILTIN_WUNPCKEHUB);
11974 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckehuh", v2si_ftype_v4hi, ARM_BUILTIN_WUNPCKEHUH);
11975 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckehuw", di_ftype_v2si, ARM_BUILTIN_WUNPCKEHUW);
11976 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckehsb", v4hi_ftype_v8qi, ARM_BUILTIN_WUNPCKEHSB);
11977 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckehsh", v2si_ftype_v4hi, ARM_BUILTIN_WUNPCKEHSH);
11978 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckehsw", di_ftype_v2si, ARM_BUILTIN_WUNPCKEHSW);
11979 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckelub", v4hi_ftype_v8qi, ARM_BUILTIN_WUNPCKELUB);
11980 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckeluh", v2si_ftype_v4hi, ARM_BUILTIN_WUNPCKELUH);
11981 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckeluw", di_ftype_v2si, ARM_BUILTIN_WUNPCKELUW);
11982 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckelsb", v4hi_ftype_v8qi, ARM_BUILTIN_WUNPCKELSB);
11983 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckelsh", v2si_ftype_v4hi, ARM_BUILTIN_WUNPCKELSH);
11984 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckelsw", di_ftype_v2si, ARM_BUILTIN_WUNPCKELSW);
11986 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wmacs", di_ftype_di_v4hi_v4hi, ARM_BUILTIN_WMACS);
11987 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wmacsz", di_ftype_v4hi_v4hi, ARM_BUILTIN_WMACSZ);
11988 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wmacu", di_ftype_di_v4hi_v4hi, ARM_BUILTIN_WMACU);
11989 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wmacuz", di_ftype_v4hi_v4hi, ARM_BUILTIN_WMACUZ);
11991 def_mbuiltin (FL_IWMMXT, "__builtin_arm_walign", v8qi_ftype_v8qi_v8qi_int, ARM_BUILTIN_WALIGN);
11992 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmia", di_ftype_di_int_int, ARM_BUILTIN_TMIA);
11993 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmiaph", di_ftype_di_int_int, ARM_BUILTIN_TMIAPH);
11994 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmiabb", di_ftype_di_int_int, ARM_BUILTIN_TMIABB);
11995 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmiabt", di_ftype_di_int_int, ARM_BUILTIN_TMIABT);
11996 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmiatb", di_ftype_di_int_int, ARM_BUILTIN_TMIATB);
11997 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmiatt", di_ftype_di_int_int, ARM_BUILTIN_TMIATT);
12001 arm_init_builtins (void)
12003 if (TARGET_REALLY_IWMMXT)
12004 arm_init_iwmmxt_builtins ();
12007 /* Errors in the source file can cause expand_expr to return const0_rtx
12008 where we expect a vector. To avoid crashing, use one of the vector
12009 clear instructions. */
12012 safe_vector_operand (rtx x, enum machine_mode mode)
12014 if (x != const0_rtx)
12016 x = gen_reg_rtx (mode);
12018 emit_insn (gen_iwmmxt_clrdi (mode == DImode ? x
12019 : gen_rtx_SUBREG (DImode, x, 0)));
12023 /* Subroutine of arm_expand_builtin to take care of binop insns. */
12026 arm_expand_binop_builtin (enum insn_code icode,
12027 tree arglist, rtx target)
12030 tree arg0 = TREE_VALUE (arglist);
12031 tree arg1 = TREE_VALUE (TREE_CHAIN (arglist));
12032 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
12033 rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
12034 enum machine_mode tmode = insn_data[icode].operand[0].mode;
12035 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
12036 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
12038 if (VECTOR_MODE_P (mode0))
12039 op0 = safe_vector_operand (op0, mode0);
12040 if (VECTOR_MODE_P (mode1))
12041 op1 = safe_vector_operand (op1, mode1);
12044 || GET_MODE (target) != tmode
12045 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
12046 target = gen_reg_rtx (tmode);
12048 /* In case the insn wants input operands in modes different from
12049 the result, abort. */
12050 if (GET_MODE (op0) != mode0 || GET_MODE (op1) != mode1)
12053 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
12054 op0 = copy_to_mode_reg (mode0, op0);
12055 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
12056 op1 = copy_to_mode_reg (mode1, op1);
12058 pat = GEN_FCN (icode) (target, op0, op1);
12065 /* Subroutine of arm_expand_builtin to take care of unop insns. */
12068 arm_expand_unop_builtin (enum insn_code icode,
12069 tree arglist, rtx target, int do_load)
12072 tree arg0 = TREE_VALUE (arglist);
12073 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
12074 enum machine_mode tmode = insn_data[icode].operand[0].mode;
12075 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
12078 || GET_MODE (target) != tmode
12079 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
12080 target = gen_reg_rtx (tmode);
12082 op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0));
12085 if (VECTOR_MODE_P (mode0))
12086 op0 = safe_vector_operand (op0, mode0);
12088 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
12089 op0 = copy_to_mode_reg (mode0, op0);
12092 pat = GEN_FCN (icode) (target, op0);
12099 /* Expand an expression EXP that calls a built-in function,
12100 with result going to TARGET if that's convenient
12101 (and in mode MODE if that's convenient).
12102 SUBTARGET may be used as the target for computing one of EXP's operands.
12103 IGNORE is nonzero if the value is to be ignored. */
12106 arm_expand_builtin (tree exp,
12108 rtx subtarget ATTRIBUTE_UNUSED,
12109 enum machine_mode mode ATTRIBUTE_UNUSED,
12110 int ignore ATTRIBUTE_UNUSED)
12112 const struct builtin_description * d;
12113 enum insn_code icode;
12114 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
12115 tree arglist = TREE_OPERAND (exp, 1);
12123 int fcode = DECL_FUNCTION_CODE (fndecl);
12125 enum machine_mode tmode;
12126 enum machine_mode mode0;
12127 enum machine_mode mode1;
12128 enum machine_mode mode2;
12132 case ARM_BUILTIN_TEXTRMSB:
12133 case ARM_BUILTIN_TEXTRMUB:
12134 case ARM_BUILTIN_TEXTRMSH:
12135 case ARM_BUILTIN_TEXTRMUH:
12136 case ARM_BUILTIN_TEXTRMSW:
12137 case ARM_BUILTIN_TEXTRMUW:
12138 icode = (fcode == ARM_BUILTIN_TEXTRMSB ? CODE_FOR_iwmmxt_textrmsb
12139 : fcode == ARM_BUILTIN_TEXTRMUB ? CODE_FOR_iwmmxt_textrmub
12140 : fcode == ARM_BUILTIN_TEXTRMSH ? CODE_FOR_iwmmxt_textrmsh
12141 : fcode == ARM_BUILTIN_TEXTRMUH ? CODE_FOR_iwmmxt_textrmuh
12142 : CODE_FOR_iwmmxt_textrmw);
12144 arg0 = TREE_VALUE (arglist);
12145 arg1 = TREE_VALUE (TREE_CHAIN (arglist));
12146 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
12147 op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
12148 tmode = insn_data[icode].operand[0].mode;
12149 mode0 = insn_data[icode].operand[1].mode;
12150 mode1 = insn_data[icode].operand[2].mode;
12152 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
12153 op0 = copy_to_mode_reg (mode0, op0);
12154 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
12156 /* @@@ better error message */
12157 error ("selector must be an immediate");
12158 return gen_reg_rtx (tmode);
12161 || GET_MODE (target) != tmode
12162 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
12163 target = gen_reg_rtx (tmode);
12164 pat = GEN_FCN (icode) (target, op0, op1);
12170 case ARM_BUILTIN_TINSRB:
12171 case ARM_BUILTIN_TINSRH:
12172 case ARM_BUILTIN_TINSRW:
12173 icode = (fcode == ARM_BUILTIN_TINSRB ? CODE_FOR_iwmmxt_tinsrb
12174 : fcode == ARM_BUILTIN_TINSRH ? CODE_FOR_iwmmxt_tinsrh
12175 : CODE_FOR_iwmmxt_tinsrw);
12176 arg0 = TREE_VALUE (arglist);
12177 arg1 = TREE_VALUE (TREE_CHAIN (arglist));
12178 arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
12179 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
12180 op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
12181 op2 = expand_expr (arg2, NULL_RTX, VOIDmode, 0);
12182 tmode = insn_data[icode].operand[0].mode;
12183 mode0 = insn_data[icode].operand[1].mode;
12184 mode1 = insn_data[icode].operand[2].mode;
12185 mode2 = insn_data[icode].operand[3].mode;
12187 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
12188 op0 = copy_to_mode_reg (mode0, op0);
12189 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
12190 op1 = copy_to_mode_reg (mode1, op1);
12191 if (! (*insn_data[icode].operand[3].predicate) (op2, mode2))
12193 /* @@@ better error message */
12194 error ("selector must be an immediate");
12198 || GET_MODE (target) != tmode
12199 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
12200 target = gen_reg_rtx (tmode);
12201 pat = GEN_FCN (icode) (target, op0, op1, op2);
12207 case ARM_BUILTIN_SETWCX:
12208 arg0 = TREE_VALUE (arglist);
12209 arg1 = TREE_VALUE (TREE_CHAIN (arglist));
12210 op0 = force_reg (SImode, expand_expr (arg0, NULL_RTX, VOIDmode, 0));
12211 op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
12212 emit_insn (gen_iwmmxt_tmcr (op1, op0));
12215 case ARM_BUILTIN_GETWCX:
12216 arg0 = TREE_VALUE (arglist);
12217 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
12218 target = gen_reg_rtx (SImode);
12219 emit_insn (gen_iwmmxt_tmrc (target, op0));
12222 case ARM_BUILTIN_WSHUFH:
12223 icode = CODE_FOR_iwmmxt_wshufh;
12224 arg0 = TREE_VALUE (arglist);
12225 arg1 = TREE_VALUE (TREE_CHAIN (arglist));
12226 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
12227 op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
12228 tmode = insn_data[icode].operand[0].mode;
12229 mode1 = insn_data[icode].operand[1].mode;
12230 mode2 = insn_data[icode].operand[2].mode;
12232 if (! (*insn_data[icode].operand[1].predicate) (op0, mode1))
12233 op0 = copy_to_mode_reg (mode1, op0);
12234 if (! (*insn_data[icode].operand[2].predicate) (op1, mode2))
12236 /* @@@ better error message */
12237 error ("mask must be an immediate");
12241 || GET_MODE (target) != tmode
12242 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
12243 target = gen_reg_rtx (tmode);
12244 pat = GEN_FCN (icode) (target, op0, op1);
12250 case ARM_BUILTIN_WSADB:
12251 return arm_expand_binop_builtin (CODE_FOR_iwmmxt_wsadb, arglist, target);
12252 case ARM_BUILTIN_WSADH:
12253 return arm_expand_binop_builtin (CODE_FOR_iwmmxt_wsadh, arglist, target);
12254 case ARM_BUILTIN_WSADBZ:
12255 return arm_expand_binop_builtin (CODE_FOR_iwmmxt_wsadbz, arglist, target);
12256 case ARM_BUILTIN_WSADHZ:
12257 return arm_expand_binop_builtin (CODE_FOR_iwmmxt_wsadhz, arglist, target);
12259 /* Several three-argument builtins. */
12260 case ARM_BUILTIN_WMACS:
12261 case ARM_BUILTIN_WMACU:
12262 case ARM_BUILTIN_WALIGN:
12263 case ARM_BUILTIN_TMIA:
12264 case ARM_BUILTIN_TMIAPH:
12265 case ARM_BUILTIN_TMIATT:
12266 case ARM_BUILTIN_TMIATB:
12267 case ARM_BUILTIN_TMIABT:
12268 case ARM_BUILTIN_TMIABB:
12269 icode = (fcode == ARM_BUILTIN_WMACS ? CODE_FOR_iwmmxt_wmacs
12270 : fcode == ARM_BUILTIN_WMACU ? CODE_FOR_iwmmxt_wmacu
12271 : fcode == ARM_BUILTIN_TMIA ? CODE_FOR_iwmmxt_tmia
12272 : fcode == ARM_BUILTIN_TMIAPH ? CODE_FOR_iwmmxt_tmiaph
12273 : fcode == ARM_BUILTIN_TMIABB ? CODE_FOR_iwmmxt_tmiabb
12274 : fcode == ARM_BUILTIN_TMIABT ? CODE_FOR_iwmmxt_tmiabt
12275 : fcode == ARM_BUILTIN_TMIATB ? CODE_FOR_iwmmxt_tmiatb
12276 : fcode == ARM_BUILTIN_TMIATT ? CODE_FOR_iwmmxt_tmiatt
12277 : CODE_FOR_iwmmxt_walign);
12278 arg0 = TREE_VALUE (arglist);
12279 arg1 = TREE_VALUE (TREE_CHAIN (arglist));
12280 arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
12281 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
12282 op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
12283 op2 = expand_expr (arg2, NULL_RTX, VOIDmode, 0);
12284 tmode = insn_data[icode].operand[0].mode;
12285 mode0 = insn_data[icode].operand[1].mode;
12286 mode1 = insn_data[icode].operand[2].mode;
12287 mode2 = insn_data[icode].operand[3].mode;
12289 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
12290 op0 = copy_to_mode_reg (mode0, op0);
12291 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
12292 op1 = copy_to_mode_reg (mode1, op1);
12293 if (! (*insn_data[icode].operand[3].predicate) (op2, mode2))
12294 op2 = copy_to_mode_reg (mode2, op2);
12296 || GET_MODE (target) != tmode
12297 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
12298 target = gen_reg_rtx (tmode);
12299 pat = GEN_FCN (icode) (target, op0, op1, op2);
12305 case ARM_BUILTIN_WZERO:
12306 target = gen_reg_rtx (DImode);
12307 emit_insn (gen_iwmmxt_clrdi (target));
12314 for (i = 0, d = bdesc_2arg; i < ARRAY_SIZE (bdesc_2arg); i++, d++)
12315 if (d->code == (const enum arm_builtins) fcode)
12316 return arm_expand_binop_builtin (d->icode, arglist, target);
12318 for (i = 0, d = bdesc_1arg; i < ARRAY_SIZE (bdesc_1arg); i++, d++)
12319 if (d->code == (const enum arm_builtins) fcode)
12320 return arm_expand_unop_builtin (d->icode, arglist, target, 0);
12322 /* @@@ Should really do something sensible here. */
12326 /* Recursively search through all of the blocks in a function
12327 checking to see if any of the variables created in that
12328 function match the RTX called 'orig'. If they do then
12329 replace them with the RTX called 'new'. */
12331 replace_symbols_in_block (tree block, rtx orig, rtx new)
12333 for (; block; block = BLOCK_CHAIN (block))
12337 if (!TREE_USED (block))
12340 for (sym = BLOCK_VARS (block); sym; sym = TREE_CHAIN (sym))
12342 if ( (DECL_NAME (sym) == 0 && TREE_CODE (sym) != TYPE_DECL)
12343 || DECL_IGNORED_P (sym)
12344 || TREE_CODE (sym) != VAR_DECL
12345 || DECL_EXTERNAL (sym)
12346 || !rtx_equal_p (DECL_RTL (sym), orig)
12350 SET_DECL_RTL (sym, new);
12353 replace_symbols_in_block (BLOCK_SUBBLOCKS (block), orig, new);
12357 /* Return the number (counting from 0) of
12358 the least significant set bit in MASK. */
12361 number_of_first_bit_set (int mask)
12366 (mask & (1 << bit)) == 0;
12373 /* Generate code to return from a thumb function.
12374 If 'reg_containing_return_addr' is -1, then the return address is
12375 actually on the stack, at the stack pointer. */
12377 thumb_exit (FILE *f, int reg_containing_return_addr, rtx eh_ofs)
12379 unsigned regs_available_for_popping;
12380 unsigned regs_to_pop;
12382 unsigned available;
12386 int restore_a4 = FALSE;
12388 /* Compute the registers we need to pop. */
12392 /* There is an assumption here, that if eh_ofs is not NULL, the
12393 normal return address will have been pushed. */
12394 if (reg_containing_return_addr == -1 || eh_ofs)
12396 /* When we are generating a return for __builtin_eh_return,
12397 reg_containing_return_addr must specify the return regno. */
12398 if (eh_ofs && reg_containing_return_addr == -1)
12401 regs_to_pop |= 1 << LR_REGNUM;
12405 if (TARGET_BACKTRACE)
12407 /* Restore the (ARM) frame pointer and stack pointer. */
12408 regs_to_pop |= (1 << ARM_HARD_FRAME_POINTER_REGNUM) | (1 << SP_REGNUM);
12412 /* If there is nothing to pop then just emit the BX instruction and
12414 if (pops_needed == 0)
12417 asm_fprintf (f, "\tadd\t%r, %r\n", SP_REGNUM, REGNO (eh_ofs));
12419 asm_fprintf (f, "\tbx\t%r\n", reg_containing_return_addr);
12422 /* Otherwise if we are not supporting interworking and we have not created
12423 a backtrace structure and the function was not entered in ARM mode then
12424 just pop the return address straight into the PC. */
12425 else if (!TARGET_INTERWORK
12426 && !TARGET_BACKTRACE
12427 && !is_called_in_ARM_mode (current_function_decl))
12431 asm_fprintf (f, "\tadd\t%r, #4\n", SP_REGNUM);
12432 asm_fprintf (f, "\tadd\t%r, %r\n", SP_REGNUM, REGNO (eh_ofs));
12433 asm_fprintf (f, "\tbx\t%r\n", reg_containing_return_addr);
12436 asm_fprintf (f, "\tpop\t{%r}\n", PC_REGNUM);
12441 /* Find out how many of the (return) argument registers we can corrupt. */
12442 regs_available_for_popping = 0;
12444 /* If returning via __builtin_eh_return, the bottom three registers
12445 all contain information needed for the return. */
12451 /* If we can deduce the registers used from the function's
12452 return value. This is more reliable that examining
12453 regs_ever_live[] because that will be set if the register is
12454 ever used in the function, not just if the register is used
12455 to hold a return value. */
12457 if (current_function_return_rtx != 0)
12458 mode = GET_MODE (current_function_return_rtx);
12461 mode = DECL_MODE (DECL_RESULT (current_function_decl));
12463 size = GET_MODE_SIZE (mode);
12467 /* In a void function we can use any argument register.
12468 In a function that returns a structure on the stack
12469 we can use the second and third argument registers. */
12470 if (mode == VOIDmode)
12471 regs_available_for_popping =
12472 (1 << ARG_REGISTER (1))
12473 | (1 << ARG_REGISTER (2))
12474 | (1 << ARG_REGISTER (3));
12476 regs_available_for_popping =
12477 (1 << ARG_REGISTER (2))
12478 | (1 << ARG_REGISTER (3));
12480 else if (size <= 4)
12481 regs_available_for_popping =
12482 (1 << ARG_REGISTER (2))
12483 | (1 << ARG_REGISTER (3));
12484 else if (size <= 8)
12485 regs_available_for_popping =
12486 (1 << ARG_REGISTER (3));
12489 /* Match registers to be popped with registers into which we pop them. */
12490 for (available = regs_available_for_popping,
12491 required = regs_to_pop;
12492 required != 0 && available != 0;
12493 available &= ~(available & - available),
12494 required &= ~(required & - required))
12497 /* If we have any popping registers left over, remove them. */
12499 regs_available_for_popping &= ~available;
12501 /* Otherwise if we need another popping register we can use
12502 the fourth argument register. */
12503 else if (pops_needed)
12505 /* If we have not found any free argument registers and
12506 reg a4 contains the return address, we must move it. */
12507 if (regs_available_for_popping == 0
12508 && reg_containing_return_addr == LAST_ARG_REGNUM)
12510 asm_fprintf (f, "\tmov\t%r, %r\n", LR_REGNUM, LAST_ARG_REGNUM);
12511 reg_containing_return_addr = LR_REGNUM;
12513 else if (size > 12)
12515 /* Register a4 is being used to hold part of the return value,
12516 but we have dire need of a free, low register. */
12519 asm_fprintf (f, "\tmov\t%r, %r\n",IP_REGNUM, LAST_ARG_REGNUM);
12522 if (reg_containing_return_addr != LAST_ARG_REGNUM)
12524 /* The fourth argument register is available. */
12525 regs_available_for_popping |= 1 << LAST_ARG_REGNUM;
12531 /* Pop as many registers as we can. */
12532 thumb_pushpop (f, regs_available_for_popping, FALSE, NULL,
12533 regs_available_for_popping);
12535 /* Process the registers we popped. */
12536 if (reg_containing_return_addr == -1)
12538 /* The return address was popped into the lowest numbered register. */
12539 regs_to_pop &= ~(1 << LR_REGNUM);
12541 reg_containing_return_addr =
12542 number_of_first_bit_set (regs_available_for_popping);
12544 /* Remove this register for the mask of available registers, so that
12545 the return address will not be corrupted by further pops. */
12546 regs_available_for_popping &= ~(1 << reg_containing_return_addr);
12549 /* If we popped other registers then handle them here. */
12550 if (regs_available_for_popping)
12554 /* Work out which register currently contains the frame pointer. */
12555 frame_pointer = number_of_first_bit_set (regs_available_for_popping);
12557 /* Move it into the correct place. */
12558 asm_fprintf (f, "\tmov\t%r, %r\n",
12559 ARM_HARD_FRAME_POINTER_REGNUM, frame_pointer);
12561 /* (Temporarily) remove it from the mask of popped registers. */
12562 regs_available_for_popping &= ~(1 << frame_pointer);
12563 regs_to_pop &= ~(1 << ARM_HARD_FRAME_POINTER_REGNUM);
12565 if (regs_available_for_popping)
12569 /* We popped the stack pointer as well,
12570 find the register that contains it. */
12571 stack_pointer = number_of_first_bit_set (regs_available_for_popping);
12573 /* Move it into the stack register. */
12574 asm_fprintf (f, "\tmov\t%r, %r\n", SP_REGNUM, stack_pointer);
12576 /* At this point we have popped all necessary registers, so
12577 do not worry about restoring regs_available_for_popping
12578 to its correct value:
12580 assert (pops_needed == 0)
12581 assert (regs_available_for_popping == (1 << frame_pointer))
12582 assert (regs_to_pop == (1 << STACK_POINTER)) */
12586 /* Since we have just move the popped value into the frame
12587 pointer, the popping register is available for reuse, and
12588 we know that we still have the stack pointer left to pop. */
12589 regs_available_for_popping |= (1 << frame_pointer);
12593 /* If we still have registers left on the stack, but we no longer have
12594 any registers into which we can pop them, then we must move the return
12595 address into the link register and make available the register that
12597 if (regs_available_for_popping == 0 && pops_needed > 0)
12599 regs_available_for_popping |= 1 << reg_containing_return_addr;
12601 asm_fprintf (f, "\tmov\t%r, %r\n", LR_REGNUM,
12602 reg_containing_return_addr);
12604 reg_containing_return_addr = LR_REGNUM;
12607 /* If we have registers left on the stack then pop some more.
12608 We know that at most we will want to pop FP and SP. */
12609 if (pops_needed > 0)
12614 thumb_pushpop (f, regs_available_for_popping, FALSE, NULL,
12615 regs_available_for_popping);
12617 /* We have popped either FP or SP.
12618 Move whichever one it is into the correct register. */
12619 popped_into = number_of_first_bit_set (regs_available_for_popping);
12620 move_to = number_of_first_bit_set (regs_to_pop);
12622 asm_fprintf (f, "\tmov\t%r, %r\n", move_to, popped_into);
12624 regs_to_pop &= ~(1 << move_to);
12629 /* If we still have not popped everything then we must have only
12630 had one register available to us and we are now popping the SP. */
12631 if (pops_needed > 0)
12635 thumb_pushpop (f, regs_available_for_popping, FALSE, NULL,
12636 regs_available_for_popping);
12638 popped_into = number_of_first_bit_set (regs_available_for_popping);
12640 asm_fprintf (f, "\tmov\t%r, %r\n", SP_REGNUM, popped_into);
12642 assert (regs_to_pop == (1 << STACK_POINTER))
12643 assert (pops_needed == 1)
12647 /* If necessary restore the a4 register. */
12650 if (reg_containing_return_addr != LR_REGNUM)
12652 asm_fprintf (f, "\tmov\t%r, %r\n", LR_REGNUM, LAST_ARG_REGNUM);
12653 reg_containing_return_addr = LR_REGNUM;
12656 asm_fprintf (f, "\tmov\t%r, %r\n", LAST_ARG_REGNUM, IP_REGNUM);
12660 asm_fprintf (f, "\tadd\t%r, %r\n", SP_REGNUM, REGNO (eh_ofs));
12662 /* Return to caller. */
12663 asm_fprintf (f, "\tbx\t%r\n", reg_containing_return_addr);
12666 /* Emit code to push or pop registers to or from the stack. F is the
12667 assembly file. MASK is the registers to push or pop. PUSH is
12668 nonzero if we should push, and zero if we should pop. For debugging
12669 output, if pushing, adjust CFA_OFFSET by the amount of space added
12670 to the stack. REAL_REGS should have the same number of bits set as
12671 MASK, and will be used instead (in the same order) to describe which
12672 registers were saved - this is used to mark the save slots when we
12673 push high registers after moving them to low registers. */
12675 thumb_pushpop (FILE *f, int mask, int push, int *cfa_offset, int real_regs)
12678 int lo_mask = mask & 0xFF;
12679 int pushed_words = 0;
12681 if (lo_mask == 0 && !push && (mask & (1 << 15)))
12683 /* Special case. Do not generate a POP PC statement here, do it in
12685 thumb_exit (f, -1, NULL_RTX);
12689 fprintf (f, "\t%s\t{", push ? "push" : "pop");
12691 /* Look at the low registers first. */
12692 for (regno = 0; regno <= LAST_LO_REGNUM; regno++, lo_mask >>= 1)
12696 asm_fprintf (f, "%r", regno);
12698 if ((lo_mask & ~1) != 0)
12705 if (push && (mask & (1 << LR_REGNUM)))
12707 /* Catch pushing the LR. */
12711 asm_fprintf (f, "%r", LR_REGNUM);
12715 else if (!push && (mask & (1 << PC_REGNUM)))
12717 /* Catch popping the PC. */
12718 if (TARGET_INTERWORK || TARGET_BACKTRACE)
12720 /* The PC is never poped directly, instead
12721 it is popped into r3 and then BX is used. */
12722 fprintf (f, "}\n");
12724 thumb_exit (f, -1, NULL_RTX);
12733 asm_fprintf (f, "%r", PC_REGNUM);
12737 fprintf (f, "}\n");
12739 if (push && pushed_words && dwarf2out_do_frame ())
12741 char *l = dwarf2out_cfi_label ();
12742 int pushed_mask = real_regs;
12744 *cfa_offset += pushed_words * 4;
12745 dwarf2out_def_cfa (l, SP_REGNUM, *cfa_offset);
12748 pushed_mask = real_regs;
12749 for (regno = 0; regno <= 14; regno++, pushed_mask >>= 1)
12751 if (pushed_mask & 1)
12752 dwarf2out_reg_save (l, regno, 4 * pushed_words++ - *cfa_offset);
12758 thumb_final_prescan_insn (rtx insn)
12760 if (flag_print_asm_name)
12761 asm_fprintf (asm_out_file, "%@ 0x%04x\n",
12762 INSN_ADDRESSES (INSN_UID (insn)));
12766 thumb_shiftable_const (unsigned HOST_WIDE_INT val)
12768 unsigned HOST_WIDE_INT mask = 0xff;
12771 if (val == 0) /* XXX */
12774 for (i = 0; i < 25; i++)
12775 if ((val & (mask << i)) == val)
12781 /* Returns nonzero if the current function contains,
12782 or might contain a far jump. */
12784 thumb_far_jump_used_p (void)
12788 /* This test is only important for leaf functions. */
12789 /* assert (!leaf_function_p ()); */
12791 /* If we have already decided that far jumps may be used,
12792 do not bother checking again, and always return true even if
12793 it turns out that they are not being used. Once we have made
12794 the decision that far jumps are present (and that hence the link
12795 register will be pushed onto the stack) we cannot go back on it. */
12796 if (cfun->machine->far_jump_used)
12799 /* If this function is not being called from the prologue/epilogue
12800 generation code then it must be being called from the
12801 INITIAL_ELIMINATION_OFFSET macro. */
12802 if (!(ARM_DOUBLEWORD_ALIGN || reload_completed))
12804 /* In this case we know that we are being asked about the elimination
12805 of the arg pointer register. If that register is not being used,
12806 then there are no arguments on the stack, and we do not have to
12807 worry that a far jump might force the prologue to push the link
12808 register, changing the stack offsets. In this case we can just
12809 return false, since the presence of far jumps in the function will
12810 not affect stack offsets.
12812 If the arg pointer is live (or if it was live, but has now been
12813 eliminated and so set to dead) then we do have to test to see if
12814 the function might contain a far jump. This test can lead to some
12815 false negatives, since before reload is completed, then length of
12816 branch instructions is not known, so gcc defaults to returning their
12817 longest length, which in turn sets the far jump attribute to true.
12819 A false negative will not result in bad code being generated, but it
12820 will result in a needless push and pop of the link register. We
12821 hope that this does not occur too often.
12823 If we need doubleword stack alignment this could affect the other
12824 elimination offsets so we can't risk getting it wrong. */
12825 if (regs_ever_live [ARG_POINTER_REGNUM])
12826 cfun->machine->arg_pointer_live = 1;
12827 else if (!cfun->machine->arg_pointer_live)
12831 /* Check to see if the function contains a branch
12832 insn with the far jump attribute set. */
12833 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
12835 if (GET_CODE (insn) == JUMP_INSN
12836 /* Ignore tablejump patterns. */
12837 && GET_CODE (PATTERN (insn)) != ADDR_VEC
12838 && GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC
12839 && get_attr_far_jump (insn) == FAR_JUMP_YES
12842 /* Record the fact that we have decided that
12843 the function does use far jumps. */
12844 cfun->machine->far_jump_used = 1;
12852 /* Return nonzero if FUNC must be entered in ARM mode. */
12854 is_called_in_ARM_mode (tree func)
12856 if (TREE_CODE (func) != FUNCTION_DECL)
12859 /* Ignore the problem about functions whoes address is taken. */
12860 if (TARGET_CALLEE_INTERWORKING && TREE_PUBLIC (func))
12864 return lookup_attribute ("interfacearm", DECL_ATTRIBUTES (func)) != NULL_TREE;
12870 /* The bits which aren't usefully expanded as rtl. */
12872 thumb_unexpanded_epilogue (void)
12875 int live_regs_mask = 0;
12876 int high_regs_pushed = 0;
12877 int leaf_function = leaf_function_p ();
12878 int had_to_push_lr;
12879 rtx eh_ofs = cfun->machine->eh_epilogue_sp_ofs;
12881 if (return_used_this_function)
12884 if (IS_NAKED (arm_current_func_type ()))
12887 for (regno = 0; regno <= LAST_LO_REGNUM; regno++)
12888 if (THUMB_REG_PUSHED_P (regno))
12889 live_regs_mask |= 1 << regno;
12891 for (regno = 8; regno < 13; regno++)
12892 if (THUMB_REG_PUSHED_P (regno))
12893 high_regs_pushed++;
12895 /* The prolog may have pushed some high registers to use as
12896 work registers. eg the testsuite file:
12897 gcc/testsuite/gcc/gcc.c-torture/execute/complex-2.c
12898 compiles to produce:
12899 push {r4, r5, r6, r7, lr}
12903 as part of the prolog. We have to undo that pushing here. */
12905 if (high_regs_pushed)
12907 int mask = live_regs_mask;
12913 /* If we can deduce the registers used from the function's return value.
12914 This is more reliable that examining regs_ever_live[] because that
12915 will be set if the register is ever used in the function, not just if
12916 the register is used to hold a return value. */
12918 if (current_function_return_rtx != 0)
12919 mode = GET_MODE (current_function_return_rtx);
12922 mode = DECL_MODE (DECL_RESULT (current_function_decl));
12924 size = GET_MODE_SIZE (mode);
12926 /* Unless we are returning a type of size > 12 register r3 is
12932 /* Oh dear! We have no low registers into which we can pop
12935 ("no low registers available for popping high registers");
12937 for (next_hi_reg = 8; next_hi_reg < 13; next_hi_reg++)
12938 if (THUMB_REG_PUSHED_P (next_hi_reg))
12941 while (high_regs_pushed)
12943 /* Find lo register(s) into which the high register(s) can
12945 for (regno = 0; regno <= LAST_LO_REGNUM; regno++)
12947 if (mask & (1 << regno))
12948 high_regs_pushed--;
12949 if (high_regs_pushed == 0)
12953 mask &= (2 << regno) - 1; /* A noop if regno == 8 */
12955 /* Pop the values into the low register(s). */
12956 thumb_pushpop (asm_out_file, mask, 0, NULL, mask);
12958 /* Move the value(s) into the high registers. */
12959 for (regno = 0; regno <= LAST_LO_REGNUM; regno++)
12961 if (mask & (1 << regno))
12963 asm_fprintf (asm_out_file, "\tmov\t%r, %r\n", next_hi_reg,
12966 for (next_hi_reg++; next_hi_reg < 13; next_hi_reg++)
12967 if (THUMB_REG_PUSHED_P (next_hi_reg))
12974 had_to_push_lr = (live_regs_mask || !leaf_function
12975 || thumb_far_jump_used_p ());
12977 if (TARGET_BACKTRACE
12978 && ((live_regs_mask & 0xFF) == 0)
12979 && regs_ever_live [LAST_ARG_REGNUM] != 0)
12981 /* The stack backtrace structure creation code had to
12982 push R7 in order to get a work register, so we pop
12984 live_regs_mask |= (1 << LAST_LO_REGNUM);
12987 if (current_function_pretend_args_size == 0 || TARGET_BACKTRACE)
12990 && !is_called_in_ARM_mode (current_function_decl)
12992 live_regs_mask |= 1 << PC_REGNUM;
12994 /* Either no argument registers were pushed or a backtrace
12995 structure was created which includes an adjusted stack
12996 pointer, so just pop everything. */
12997 if (live_regs_mask)
12998 thumb_pushpop (asm_out_file, live_regs_mask, FALSE, NULL,
13002 thumb_exit (asm_out_file, 2, eh_ofs);
13003 /* We have either just popped the return address into the
13004 PC or it is was kept in LR for the entire function or
13005 it is still on the stack because we do not want to
13006 return by doing a pop {pc}. */
13007 else if ((live_regs_mask & (1 << PC_REGNUM)) == 0)
13008 thumb_exit (asm_out_file,
13010 && is_called_in_ARM_mode (current_function_decl)) ?
13011 -1 : LR_REGNUM, NULL_RTX);
13015 /* Pop everything but the return address. */
13016 live_regs_mask &= ~(1 << PC_REGNUM);
13018 if (live_regs_mask)
13019 thumb_pushpop (asm_out_file, live_regs_mask, FALSE, NULL,
13022 if (had_to_push_lr)
13023 /* Get the return address into a temporary register. */
13024 thumb_pushpop (asm_out_file, 1 << LAST_ARG_REGNUM, 0, NULL,
13025 1 << LAST_ARG_REGNUM);
13027 /* Remove the argument registers that were pushed onto the stack. */
13028 asm_fprintf (asm_out_file, "\tadd\t%r, %r, #%d\n",
13029 SP_REGNUM, SP_REGNUM,
13030 current_function_pretend_args_size);
13033 thumb_exit (asm_out_file, 2, eh_ofs);
13035 thumb_exit (asm_out_file,
13036 had_to_push_lr ? LAST_ARG_REGNUM : LR_REGNUM, NULL_RTX);
13042 /* Functions to save and restore machine-specific function data. */
13043 static struct machine_function *
13044 arm_init_machine_status (void)
13046 struct machine_function *machine;
13047 machine = (machine_function *) ggc_alloc_cleared (sizeof (machine_function));
13049 #if ARM_FT_UNKNOWN != 0
13050 machine->func_type = ARM_FT_UNKNOWN;
13055 /* Return an RTX indicating where the return address to the
13056 calling function can be found. */
13058 arm_return_addr (int count, rtx frame ATTRIBUTE_UNUSED)
13063 if (TARGET_APCS_32)
13064 return get_hard_reg_initial_val (Pmode, LR_REGNUM);
13067 rtx lr = gen_rtx_AND (Pmode, gen_rtx_REG (Pmode, LR_REGNUM),
13068 GEN_INT (RETURN_ADDR_MASK26));
13069 return get_func_hard_reg_initial_val (cfun, lr);
13073 /* Do anything needed before RTL is emitted for each function. */
13075 arm_init_expanders (void)
13077 /* Arrange to initialize and mark the machine per-function status. */
13078 init_machine_status = arm_init_machine_status;
13082 /* Like arm_compute_initial_elimination offset. Simpler because
13083 THUMB_HARD_FRAME_POINTER isn't actually the ABI specified frame pointer. */
13086 thumb_compute_initial_elimination_offset (unsigned int from, unsigned int to)
13088 arm_stack_offsets *offsets;
13090 offsets = arm_get_frame_offsets ();
13094 case ARG_POINTER_REGNUM:
13097 case STACK_POINTER_REGNUM:
13098 return offsets->outgoing_args - offsets->saved_args;
13100 case FRAME_POINTER_REGNUM:
13101 return offsets->soft_frame - offsets->saved_args;
13103 case THUMB_HARD_FRAME_POINTER_REGNUM:
13104 case ARM_HARD_FRAME_POINTER_REGNUM:
13105 return offsets->saved_regs - offsets->saved_args;
13112 case FRAME_POINTER_REGNUM:
13115 case STACK_POINTER_REGNUM:
13116 return offsets->outgoing_args - offsets->soft_frame;
13118 case THUMB_HARD_FRAME_POINTER_REGNUM:
13119 case ARM_HARD_FRAME_POINTER_REGNUM:
13120 return offsets->saved_regs - offsets->soft_frame;
13133 /* Generate the rest of a function's prologue. */
13135 thumb_expand_prologue (void)
13139 HOST_WIDE_INT amount;
13140 arm_stack_offsets *offsets;
13141 unsigned long func_type;
13143 func_type = arm_current_func_type ();
13145 /* Naked functions don't have prologues. */
13146 if (IS_NAKED (func_type))
13149 if (IS_INTERRUPT (func_type))
13151 error ("interrupt Service Routines cannot be coded in Thumb mode");
13155 offsets = arm_get_frame_offsets ();
13157 if (frame_pointer_needed)
13159 insn = emit_insn (gen_movsi (hard_frame_pointer_rtx,
13160 stack_pointer_rtx));
13161 RTX_FRAME_RELATED_P (insn) = 1;
13164 amount = offsets->outgoing_args - offsets->saved_regs;
13169 insn = emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,
13170 GEN_INT (- amount)));
13171 RTX_FRAME_RELATED_P (insn) = 1;
13178 /* The stack decrement is too big for an immediate value in a single
13179 insn. In theory we could issue multiple subtracts, but after
13180 three of them it becomes more space efficient to place the full
13181 value in the constant pool and load into a register. (Also the
13182 ARM debugger really likes to see only one stack decrement per
13183 function). So instead we look for a scratch register into which
13184 we can load the decrement, and then we subtract this from the
13185 stack pointer. Unfortunately on the thumb the only available
13186 scratch registers are the argument registers, and we cannot use
13187 these as they may hold arguments to the function. Instead we
13188 attempt to locate a call preserved register which is used by this
13189 function. If we can find one, then we know that it will have
13190 been pushed at the start of the prologue and so we can corrupt
13192 for (regno = LAST_ARG_REGNUM + 1; regno <= LAST_LO_REGNUM; regno++)
13193 if (THUMB_REG_PUSHED_P (regno)
13194 && !(frame_pointer_needed
13195 && (regno == THUMB_HARD_FRAME_POINTER_REGNUM)))
13198 if (regno > LAST_LO_REGNUM) /* Very unlikely. */
13200 rtx spare = gen_rtx_REG (SImode, IP_REGNUM);
13202 /* Choose an arbitrary, non-argument low register. */
13203 reg = gen_rtx_REG (SImode, LAST_LO_REGNUM);
13205 /* Save it by copying it into a high, scratch register. */
13206 emit_insn (gen_movsi (spare, reg));
13207 /* Add a USE to stop propagate_one_insn() from barfing. */
13208 emit_insn (gen_prologue_use (spare));
13210 /* Decrement the stack. */
13211 emit_insn (gen_movsi (reg, GEN_INT (- amount)));
13212 insn = emit_insn (gen_addsi3 (stack_pointer_rtx,
13213 stack_pointer_rtx, reg));
13214 RTX_FRAME_RELATED_P (insn) = 1;
13215 dwarf = gen_rtx_SET (SImode, stack_pointer_rtx,
13216 plus_constant (stack_pointer_rtx,
13217 GEN_INT (- amount)));
13218 RTX_FRAME_RELATED_P (dwarf) = 1;
13220 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, dwarf,
13223 /* Restore the low register's original value. */
13224 emit_insn (gen_movsi (reg, spare));
13226 /* Emit a USE of the restored scratch register, so that flow
13227 analysis will not consider the restore redundant. The
13228 register won't be used again in this function and isn't
13229 restored by the epilogue. */
13230 emit_insn (gen_prologue_use (reg));
13234 reg = gen_rtx_REG (SImode, regno);
13236 emit_insn (gen_movsi (reg, GEN_INT (- amount)));
13238 insn = emit_insn (gen_addsi3 (stack_pointer_rtx,
13239 stack_pointer_rtx, reg));
13240 RTX_FRAME_RELATED_P (insn) = 1;
13241 dwarf = gen_rtx_SET (SImode, stack_pointer_rtx,
13242 plus_constant (stack_pointer_rtx,
13243 GEN_INT (- amount)));
13244 RTX_FRAME_RELATED_P (dwarf) = 1;
13246 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, dwarf,
13250 /* If the frame pointer is needed, emit a special barrier that
13251 will prevent the scheduler from moving stores to the frame
13252 before the stack adjustment. */
13253 if (frame_pointer_needed)
13254 emit_insn (gen_stack_tie (stack_pointer_rtx,
13255 hard_frame_pointer_rtx));
13258 if (current_function_profile || TARGET_NO_SCHED_PRO)
13259 emit_insn (gen_blockage ());
13263 thumb_expand_epilogue (void)
13265 HOST_WIDE_INT amount;
13266 arm_stack_offsets *offsets;
13269 /* Naked functions don't have prologues. */
13270 if (IS_NAKED (arm_current_func_type ()))
13273 offsets = arm_get_frame_offsets ();
13274 amount = offsets->outgoing_args - offsets->saved_regs;
13276 if (frame_pointer_needed)
13277 emit_insn (gen_movsi (stack_pointer_rtx, hard_frame_pointer_rtx));
13281 emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,
13282 GEN_INT (amount)));
13285 /* r3 is always free in the epilogue. */
13286 rtx reg = gen_rtx_REG (SImode, LAST_ARG_REGNUM);
13288 emit_insn (gen_movsi (reg, GEN_INT (amount)));
13289 emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, reg));
13293 /* Emit a USE (stack_pointer_rtx), so that
13294 the stack adjustment will not be deleted. */
13295 emit_insn (gen_prologue_use (stack_pointer_rtx));
13297 if (current_function_profile || TARGET_NO_SCHED_PRO)
13298 emit_insn (gen_blockage ());
13300 /* Emit a clobber for each insn that will be restored in the epilogue,
13301 so that flow2 will get register lifetimes correct. */
13302 for (regno = 0; regno < 13; regno++)
13303 if (regs_ever_live[regno] && !call_used_regs[regno])
13304 emit_insn (gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, regno)));
13306 if (! regs_ever_live[LR_REGNUM])
13307 emit_insn (gen_rtx_USE (VOIDmode, gen_rtx_REG (SImode, LR_REGNUM)));
13311 thumb_output_function_prologue (FILE *f, HOST_WIDE_INT size ATTRIBUTE_UNUSED)
13313 int live_regs_mask = 0;
13314 int high_regs_pushed = 0;
13315 int cfa_offset = 0;
13318 if (IS_NAKED (arm_current_func_type ()))
13321 if (is_called_in_ARM_mode (current_function_decl))
13325 if (GET_CODE (DECL_RTL (current_function_decl)) != MEM)
13327 if (GET_CODE (XEXP (DECL_RTL (current_function_decl), 0)) != SYMBOL_REF)
13329 name = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
13331 /* Generate code sequence to switch us into Thumb mode. */
13332 /* The .code 32 directive has already been emitted by
13333 ASM_DECLARE_FUNCTION_NAME. */
13334 asm_fprintf (f, "\torr\t%r, %r, #1\n", IP_REGNUM, PC_REGNUM);
13335 asm_fprintf (f, "\tbx\t%r\n", IP_REGNUM);
13337 /* Generate a label, so that the debugger will notice the
13338 change in instruction sets. This label is also used by
13339 the assembler to bypass the ARM code when this function
13340 is called from a Thumb encoded function elsewhere in the
13341 same file. Hence the definition of STUB_NAME here must
13342 agree with the definition in gas/config/tc-arm.c. */
13344 #define STUB_NAME ".real_start_of"
13346 fprintf (f, "\t.code\t16\n");
13348 if (arm_dllexport_name_p (name))
13349 name = arm_strip_name_encoding (name);
13351 asm_fprintf (f, "\t.globl %s%U%s\n", STUB_NAME, name);
13352 fprintf (f, "\t.thumb_func\n");
13353 asm_fprintf (f, "%s%U%s:\n", STUB_NAME, name);
13356 if (current_function_pretend_args_size)
13358 if (cfun->machine->uses_anonymous_args)
13362 fprintf (f, "\tpush\t{");
13364 num_pushes = ARM_NUM_INTS (current_function_pretend_args_size);
13366 for (regno = LAST_ARG_REGNUM + 1 - num_pushes;
13367 regno <= LAST_ARG_REGNUM;
13369 asm_fprintf (f, "%r%s", regno,
13370 regno == LAST_ARG_REGNUM ? "" : ", ");
13372 fprintf (f, "}\n");
13375 asm_fprintf (f, "\tsub\t%r, %r, #%d\n",
13376 SP_REGNUM, SP_REGNUM,
13377 current_function_pretend_args_size);
13379 /* We don't need to record the stores for unwinding (would it
13380 help the debugger any if we did?), but record the change in
13381 the stack pointer. */
13382 if (dwarf2out_do_frame ())
13384 char *l = dwarf2out_cfi_label ();
13385 cfa_offset = cfa_offset + current_function_pretend_args_size;
13386 dwarf2out_def_cfa (l, SP_REGNUM, cfa_offset);
13390 for (regno = 0; regno <= LAST_LO_REGNUM; regno++)
13391 if (THUMB_REG_PUSHED_P (regno))
13392 live_regs_mask |= 1 << regno;
13394 if (live_regs_mask || !leaf_function_p () || thumb_far_jump_used_p ())
13395 live_regs_mask |= 1 << LR_REGNUM;
13397 if (TARGET_BACKTRACE)
13400 int work_register = 0;
13403 /* We have been asked to create a stack backtrace structure.
13404 The code looks like this:
13408 0 sub SP, #16 Reserve space for 4 registers.
13409 2 push {R7} Get a work register.
13410 4 add R7, SP, #20 Get the stack pointer before the push.
13411 6 str R7, [SP, #8] Store the stack pointer (before reserving the space).
13412 8 mov R7, PC Get hold of the start of this code plus 12.
13413 10 str R7, [SP, #16] Store it.
13414 12 mov R7, FP Get hold of the current frame pointer.
13415 14 str R7, [SP, #4] Store it.
13416 16 mov R7, LR Get hold of the current return address.
13417 18 str R7, [SP, #12] Store it.
13418 20 add R7, SP, #16 Point at the start of the backtrace structure.
13419 22 mov FP, R7 Put this value into the frame pointer. */
13421 if ((live_regs_mask & 0xFF) == 0)
13423 /* See if the a4 register is free. */
13425 if (regs_ever_live [LAST_ARG_REGNUM] == 0)
13426 work_register = LAST_ARG_REGNUM;
13427 else /* We must push a register of our own. */
13428 live_regs_mask |= (1 << LAST_LO_REGNUM);
13431 if (work_register == 0)
13433 /* Select a register from the list that will be pushed to
13434 use as our work register. */
13435 for (work_register = (LAST_LO_REGNUM + 1); work_register--;)
13436 if ((1 << work_register) & live_regs_mask)
13441 (f, "\tsub\t%r, %r, #16\t%@ Create stack backtrace structure\n",
13442 SP_REGNUM, SP_REGNUM);
13444 if (dwarf2out_do_frame ())
13446 char *l = dwarf2out_cfi_label ();
13447 cfa_offset = cfa_offset + 16;
13448 dwarf2out_def_cfa (l, SP_REGNUM, cfa_offset);
13451 if (live_regs_mask)
13452 thumb_pushpop (f, live_regs_mask, 1, &cfa_offset, live_regs_mask);
13454 for (offset = 0, wr = 1 << 15; wr != 0; wr >>= 1)
13455 if (wr & live_regs_mask)
13458 asm_fprintf (f, "\tadd\t%r, %r, #%d\n", work_register, SP_REGNUM,
13459 offset + 16 + current_function_pretend_args_size);
13461 asm_fprintf (f, "\tstr\t%r, [%r, #%d]\n", work_register, SP_REGNUM,
13464 /* Make sure that the instruction fetching the PC is in the right place
13465 to calculate "start of backtrace creation code + 12". */
13466 if (live_regs_mask)
13468 asm_fprintf (f, "\tmov\t%r, %r\n", work_register, PC_REGNUM);
13469 asm_fprintf (f, "\tstr\t%r, [%r, #%d]\n", work_register, SP_REGNUM,
13471 asm_fprintf (f, "\tmov\t%r, %r\n", work_register,
13472 ARM_HARD_FRAME_POINTER_REGNUM);
13473 asm_fprintf (f, "\tstr\t%r, [%r, #%d]\n", work_register, SP_REGNUM,
13478 asm_fprintf (f, "\tmov\t%r, %r\n", work_register,
13479 ARM_HARD_FRAME_POINTER_REGNUM);
13480 asm_fprintf (f, "\tstr\t%r, [%r, #%d]\n", work_register, SP_REGNUM,
13482 asm_fprintf (f, "\tmov\t%r, %r\n", work_register, PC_REGNUM);
13483 asm_fprintf (f, "\tstr\t%r, [%r, #%d]\n", work_register, SP_REGNUM,
13487 asm_fprintf (f, "\tmov\t%r, %r\n", work_register, LR_REGNUM);
13488 asm_fprintf (f, "\tstr\t%r, [%r, #%d]\n", work_register, SP_REGNUM,
13490 asm_fprintf (f, "\tadd\t%r, %r, #%d\n", work_register, SP_REGNUM,
13492 asm_fprintf (f, "\tmov\t%r, %r\t\t%@ Backtrace structure created\n",
13493 ARM_HARD_FRAME_POINTER_REGNUM, work_register);
13495 else if (live_regs_mask)
13496 thumb_pushpop (f, live_regs_mask, 1, &cfa_offset, live_regs_mask);
13498 for (regno = 8; regno < 13; regno++)
13499 if (THUMB_REG_PUSHED_P (regno))
13500 high_regs_pushed++;
13502 if (high_regs_pushed)
13504 int pushable_regs = 0;
13505 int mask = live_regs_mask & 0xff;
13508 for (next_hi_reg = 12; next_hi_reg > LAST_LO_REGNUM; next_hi_reg--)
13509 if (THUMB_REG_PUSHED_P (next_hi_reg))
13512 pushable_regs = mask;
13514 if (pushable_regs == 0)
13516 /* Desperation time -- this probably will never happen. */
13517 if (THUMB_REG_PUSHED_P (LAST_ARG_REGNUM))
13518 asm_fprintf (f, "\tmov\t%r, %r\n", IP_REGNUM, LAST_ARG_REGNUM);
13519 mask = 1 << LAST_ARG_REGNUM;
13522 while (high_regs_pushed > 0)
13524 int real_regs_mask = 0;
13526 for (regno = LAST_LO_REGNUM; regno >= 0; regno--)
13528 if (mask & (1 << regno))
13530 asm_fprintf (f, "\tmov\t%r, %r\n", regno, next_hi_reg);
13532 high_regs_pushed--;
13533 real_regs_mask |= (1 << next_hi_reg);
13535 if (high_regs_pushed)
13537 for (next_hi_reg--; next_hi_reg > LAST_LO_REGNUM;
13539 if (THUMB_REG_PUSHED_P (next_hi_reg))
13544 mask &= ~((1 << regno) - 1);
13550 thumb_pushpop (f, mask, 1, &cfa_offset, real_regs_mask);
13553 if (pushable_regs == 0
13554 && (THUMB_REG_PUSHED_P (LAST_ARG_REGNUM)))
13555 asm_fprintf (f, "\tmov\t%r, %r\n", LAST_ARG_REGNUM, IP_REGNUM);
13559 /* Handle the case of a double word load into a low register from
13560 a computed memory address. The computed address may involve a
13561 register which is overwritten by the load. */
13563 thumb_load_double_from_address (rtx *operands)
13571 if (GET_CODE (operands[0]) != REG)
13574 if (GET_CODE (operands[1]) != MEM)
13577 /* Get the memory address. */
13578 addr = XEXP (operands[1], 0);
13580 /* Work out how the memory address is computed. */
13581 switch (GET_CODE (addr))
13584 operands[2] = gen_rtx_MEM (SImode,
13585 plus_constant (XEXP (operands[1], 0), 4));
13587 if (REGNO (operands[0]) == REGNO (addr))
13589 output_asm_insn ("ldr\t%H0, %2", operands);
13590 output_asm_insn ("ldr\t%0, %1", operands);
13594 output_asm_insn ("ldr\t%0, %1", operands);
13595 output_asm_insn ("ldr\t%H0, %2", operands);
13600 /* Compute <address> + 4 for the high order load. */
13601 operands[2] = gen_rtx_MEM (SImode,
13602 plus_constant (XEXP (operands[1], 0), 4));
13604 output_asm_insn ("ldr\t%0, %1", operands);
13605 output_asm_insn ("ldr\t%H0, %2", operands);
13609 arg1 = XEXP (addr, 0);
13610 arg2 = XEXP (addr, 1);
13612 if (CONSTANT_P (arg1))
13613 base = arg2, offset = arg1;
13615 base = arg1, offset = arg2;
13617 if (GET_CODE (base) != REG)
13620 /* Catch the case of <address> = <reg> + <reg> */
13621 if (GET_CODE (offset) == REG)
13623 int reg_offset = REGNO (offset);
13624 int reg_base = REGNO (base);
13625 int reg_dest = REGNO (operands[0]);
13627 /* Add the base and offset registers together into the
13628 higher destination register. */
13629 asm_fprintf (asm_out_file, "\tadd\t%r, %r, %r",
13630 reg_dest + 1, reg_base, reg_offset);
13632 /* Load the lower destination register from the address in
13633 the higher destination register. */
13634 asm_fprintf (asm_out_file, "\tldr\t%r, [%r, #0]",
13635 reg_dest, reg_dest + 1);
13637 /* Load the higher destination register from its own address
13639 asm_fprintf (asm_out_file, "\tldr\t%r, [%r, #4]",
13640 reg_dest + 1, reg_dest + 1);
13644 /* Compute <address> + 4 for the high order load. */
13645 operands[2] = gen_rtx_MEM (SImode,
13646 plus_constant (XEXP (operands[1], 0), 4));
13648 /* If the computed address is held in the low order register
13649 then load the high order register first, otherwise always
13650 load the low order register first. */
13651 if (REGNO (operands[0]) == REGNO (base))
13653 output_asm_insn ("ldr\t%H0, %2", operands);
13654 output_asm_insn ("ldr\t%0, %1", operands);
13658 output_asm_insn ("ldr\t%0, %1", operands);
13659 output_asm_insn ("ldr\t%H0, %2", operands);
13665 /* With no registers to worry about we can just load the value
13667 operands[2] = gen_rtx_MEM (SImode,
13668 plus_constant (XEXP (operands[1], 0), 4));
13670 output_asm_insn ("ldr\t%H0, %2", operands);
13671 output_asm_insn ("ldr\t%0, %1", operands);
13683 thumb_output_move_mem_multiple (int n, rtx *operands)
13690 if (REGNO (operands[4]) > REGNO (operands[5]))
13693 operands[4] = operands[5];
13696 output_asm_insn ("ldmia\t%1!, {%4, %5}", operands);
13697 output_asm_insn ("stmia\t%0!, {%4, %5}", operands);
13701 if (REGNO (operands[4]) > REGNO (operands[5]))
13704 operands[4] = operands[5];
13707 if (REGNO (operands[5]) > REGNO (operands[6]))
13710 operands[5] = operands[6];
13713 if (REGNO (operands[4]) > REGNO (operands[5]))
13716 operands[4] = operands[5];
13720 output_asm_insn ("ldmia\t%1!, {%4, %5, %6}", operands);
13721 output_asm_insn ("stmia\t%0!, {%4, %5, %6}", operands);
13731 /* Routines for generating rtl. */
13733 thumb_expand_movstrqi (rtx *operands)
13735 rtx out = copy_to_mode_reg (SImode, XEXP (operands[0], 0));
13736 rtx in = copy_to_mode_reg (SImode, XEXP (operands[1], 0));
13737 HOST_WIDE_INT len = INTVAL (operands[2]);
13738 HOST_WIDE_INT offset = 0;
13742 emit_insn (gen_movmem12b (out, in, out, in));
13748 emit_insn (gen_movmem8b (out, in, out, in));
13754 rtx reg = gen_reg_rtx (SImode);
13755 emit_insn (gen_movsi (reg, gen_rtx_MEM (SImode, in)));
13756 emit_insn (gen_movsi (gen_rtx_MEM (SImode, out), reg));
13763 rtx reg = gen_reg_rtx (HImode);
13764 emit_insn (gen_movhi (reg, gen_rtx_MEM (HImode,
13765 plus_constant (in, offset))));
13766 emit_insn (gen_movhi (gen_rtx_MEM (HImode, plus_constant (out, offset)),
13774 rtx reg = gen_reg_rtx (QImode);
13775 emit_insn (gen_movqi (reg, gen_rtx_MEM (QImode,
13776 plus_constant (in, offset))));
13777 emit_insn (gen_movqi (gen_rtx_MEM (QImode, plus_constant (out, offset)),
13783 thumb_cmp_operand (rtx op, enum machine_mode mode)
13785 return ((GET_CODE (op) == CONST_INT
13786 && INTVAL (op) < 256
13787 && INTVAL (op) >= 0)
13788 || s_register_operand (op, mode));
13792 thumb_cmpneg_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
13794 return (GET_CODE (op) == CONST_INT
13796 && INTVAL (op) > -256);
13799 /* Return TRUE if a result can be stored in OP without clobbering the
13800 condition code register. Prior to reload we only accept a
13801 register. After reload we have to be able to handle memory as
13802 well, since a pseudo may not get a hard reg and reload cannot
13803 handle output-reloads on jump insns.
13805 We could possibly handle mem before reload as well, but that might
13806 complicate things with the need to handle increment
13810 thumb_cbrch_target_operand (rtx op, enum machine_mode mode)
13812 return (s_register_operand (op, mode)
13813 || ((reload_in_progress || reload_completed)
13814 && memory_operand (op, mode)));
13817 /* Handle storing a half-word to memory during reload. */
13819 thumb_reload_out_hi (rtx *operands)
13821 emit_insn (gen_thumb_movhi_clobber (operands[0], operands[1], operands[2]));
13824 /* Handle reading a half-word from memory during reload. */
13826 thumb_reload_in_hi (rtx *operands ATTRIBUTE_UNUSED)
13831 /* Return the length of a function name prefix
13832 that starts with the character 'c'. */
13834 arm_get_strip_length (int c)
13838 ARM_NAME_ENCODING_LENGTHS
13843 /* Return a pointer to a function's name with any
13844 and all prefix encodings stripped from it. */
13846 arm_strip_name_encoding (const char *name)
13850 while ((skip = arm_get_strip_length (* name)))
13856 /* If there is a '*' anywhere in the name's prefix, then
13857 emit the stripped name verbatim, otherwise prepend an
13858 underscore if leading underscores are being used. */
13860 arm_asm_output_labelref (FILE *stream, const char *name)
13865 while ((skip = arm_get_strip_length (* name)))
13867 verbatim |= (*name == '*');
13872 fputs (name, stream);
13874 asm_fprintf (stream, "%U%s", name);
13879 #ifdef AOF_ASSEMBLER
13880 /* Special functions only needed when producing AOF syntax assembler. */
13884 struct pic_chain * next;
13885 const char * symname;
13888 static struct pic_chain * aof_pic_chain = NULL;
13891 aof_pic_entry (rtx x)
13893 struct pic_chain ** chainp;
13896 if (aof_pic_label == NULL_RTX)
13898 aof_pic_label = gen_rtx_SYMBOL_REF (Pmode, "x$adcons");
13901 for (offset = 0, chainp = &aof_pic_chain; *chainp;
13902 offset += 4, chainp = &(*chainp)->next)
13903 if ((*chainp)->symname == XSTR (x, 0))
13904 return plus_constant (aof_pic_label, offset);
13906 *chainp = (struct pic_chain *) xmalloc (sizeof (struct pic_chain));
13907 (*chainp)->next = NULL;
13908 (*chainp)->symname = XSTR (x, 0);
13909 return plus_constant (aof_pic_label, offset);
13913 aof_dump_pic_table (FILE *f)
13915 struct pic_chain * chain;
13917 if (aof_pic_chain == NULL)
13920 asm_fprintf (f, "\tAREA |%r$$adcons|, BASED %r\n",
13921 PIC_OFFSET_TABLE_REGNUM,
13922 PIC_OFFSET_TABLE_REGNUM);
13923 fputs ("|x$adcons|\n", f);
13925 for (chain = aof_pic_chain; chain; chain = chain->next)
13927 fputs ("\tDCD\t", f);
13928 assemble_name (f, chain->symname);
13933 int arm_text_section_count = 1;
13936 aof_text_section (void )
13938 static char buf[100];
13939 sprintf (buf, "\tAREA |C$$code%d|, CODE, READONLY",
13940 arm_text_section_count++);
13942 strcat (buf, ", PIC, REENTRANT");
13946 static int arm_data_section_count = 1;
13949 aof_data_section (void)
13951 static char buf[100];
13952 sprintf (buf, "\tAREA |C$$data%d|, DATA", arm_data_section_count++);
13956 /* The AOF assembler is religiously strict about declarations of
13957 imported and exported symbols, so that it is impossible to declare
13958 a function as imported near the beginning of the file, and then to
13959 export it later on. It is, however, possible to delay the decision
13960 until all the functions in the file have been compiled. To get
13961 around this, we maintain a list of the imports and exports, and
13962 delete from it any that are subsequently defined. At the end of
13963 compilation we spit the remainder of the list out before the END
13968 struct import * next;
13972 static struct import * imports_list = NULL;
13975 aof_add_import (const char *name)
13977 struct import * new;
13979 for (new = imports_list; new; new = new->next)
13980 if (new->name == name)
13983 new = (struct import *) xmalloc (sizeof (struct import));
13984 new->next = imports_list;
13985 imports_list = new;
13990 aof_delete_import (const char *name)
13992 struct import ** old;
13994 for (old = &imports_list; *old; old = & (*old)->next)
13996 if ((*old)->name == name)
13998 *old = (*old)->next;
14004 int arm_main_function = 0;
14007 aof_dump_imports (FILE *f)
14009 /* The AOF assembler needs this to cause the startup code to be extracted
14010 from the library. Brining in __main causes the whole thing to work
14012 if (arm_main_function)
14015 fputs ("\tIMPORT __main\n", f);
14016 fputs ("\tDCD __main\n", f);
14019 /* Now dump the remaining imports. */
14020 while (imports_list)
14022 fprintf (f, "\tIMPORT\t");
14023 assemble_name (f, imports_list->name);
14025 imports_list = imports_list->next;
14030 aof_globalize_label (FILE *stream, const char *name)
14032 default_globalize_label (stream, name);
14033 if (! strcmp (name, "main"))
14034 arm_main_function = 1;
14038 aof_file_start (void)
14040 fputs ("__r0\tRN\t0\n", asm_out_file);
14041 fputs ("__a1\tRN\t0\n", asm_out_file);
14042 fputs ("__a2\tRN\t1\n", asm_out_file);
14043 fputs ("__a3\tRN\t2\n", asm_out_file);
14044 fputs ("__a4\tRN\t3\n", asm_out_file);
14045 fputs ("__v1\tRN\t4\n", asm_out_file);
14046 fputs ("__v2\tRN\t5\n", asm_out_file);
14047 fputs ("__v3\tRN\t6\n", asm_out_file);
14048 fputs ("__v4\tRN\t7\n", asm_out_file);
14049 fputs ("__v5\tRN\t8\n", asm_out_file);
14050 fputs ("__v6\tRN\t9\n", asm_out_file);
14051 fputs ("__sl\tRN\t10\n", asm_out_file);
14052 fputs ("__fp\tRN\t11\n", asm_out_file);
14053 fputs ("__ip\tRN\t12\n", asm_out_file);
14054 fputs ("__sp\tRN\t13\n", asm_out_file);
14055 fputs ("__lr\tRN\t14\n", asm_out_file);
14056 fputs ("__pc\tRN\t15\n", asm_out_file);
14057 fputs ("__f0\tFN\t0\n", asm_out_file);
14058 fputs ("__f1\tFN\t1\n", asm_out_file);
14059 fputs ("__f2\tFN\t2\n", asm_out_file);
14060 fputs ("__f3\tFN\t3\n", asm_out_file);
14061 fputs ("__f4\tFN\t4\n", asm_out_file);
14062 fputs ("__f5\tFN\t5\n", asm_out_file);
14063 fputs ("__f6\tFN\t6\n", asm_out_file);
14064 fputs ("__f7\tFN\t7\n", asm_out_file);
14069 aof_file_end (void)
14072 aof_dump_pic_table (asm_out_file);
14073 aof_dump_imports (asm_out_file);
14074 fputs ("\tEND\n", asm_out_file);
14076 #endif /* AOF_ASSEMBLER */
14078 #ifdef OBJECT_FORMAT_ELF
14079 /* Switch to an arbitrary section NAME with attributes as specified
14080 by FLAGS. ALIGN specifies any known alignment requirements for
14081 the section; 0 if the default should be used.
14083 Differs from the default elf version only in the prefix character
14084 used before the section type. */
14087 arm_elf_asm_named_section (const char *name, unsigned int flags)
14089 char flagchars[10], *f = flagchars;
14091 if (! named_section_first_declaration (name))
14093 fprintf (asm_out_file, "\t.section\t%s\n", name);
14097 if (!(flags & SECTION_DEBUG))
14099 if (flags & SECTION_WRITE)
14101 if (flags & SECTION_CODE)
14103 if (flags & SECTION_SMALL)
14105 if (flags & SECTION_MERGE)
14107 if (flags & SECTION_STRINGS)
14109 if (flags & SECTION_TLS)
14113 fprintf (asm_out_file, "\t.section\t%s,\"%s\"", name, flagchars);
14115 if (!(flags & SECTION_NOTYPE))
14119 if (flags & SECTION_BSS)
14124 fprintf (asm_out_file, ",%%%s", type);
14126 if (flags & SECTION_ENTSIZE)
14127 fprintf (asm_out_file, ",%d", flags & SECTION_ENTSIZE);
14130 putc ('\n', asm_out_file);
14135 /* Symbols in the text segment can be accessed without indirecting via the
14136 constant pool; it may take an extra binary operation, but this is still
14137 faster than indirecting via memory. Don't do this when not optimizing,
14138 since we won't be calculating al of the offsets necessary to do this
14142 arm_encode_section_info (tree decl, rtx rtl, int first)
14144 /* This doesn't work with AOF syntax, since the string table may be in
14145 a different AREA. */
14146 #ifndef AOF_ASSEMBLER
14147 if (optimize > 0 && TREE_CONSTANT (decl))
14148 SYMBOL_REF_FLAG (XEXP (rtl, 0)) = 1;
14151 /* If we are referencing a function that is weak then encode a long call
14152 flag in the function name, otherwise if the function is static or
14153 or known to be defined in this file then encode a short call flag. */
14154 if (first && TREE_CODE_CLASS (TREE_CODE (decl)) == 'd')
14156 if (TREE_CODE (decl) == FUNCTION_DECL && DECL_WEAK (decl))
14157 arm_encode_call_attribute (decl, LONG_CALL_FLAG_CHAR);
14158 else if (! TREE_PUBLIC (decl))
14159 arm_encode_call_attribute (decl, SHORT_CALL_FLAG_CHAR);
14162 #endif /* !ARM_PE */
14165 arm_internal_label (FILE *stream, const char *prefix, unsigned long labelno)
14167 if (arm_ccfsm_state == 3 && (unsigned) arm_target_label == labelno
14168 && !strcmp (prefix, "L"))
14170 arm_ccfsm_state = 0;
14171 arm_target_insn = NULL;
14173 default_internal_label (stream, prefix, labelno);
14176 /* Output code to add DELTA to the first argument, and then jump
14177 to FUNCTION. Used for C++ multiple inheritance. */
14179 arm_output_mi_thunk (FILE *file, tree thunk ATTRIBUTE_UNUSED,
14180 HOST_WIDE_INT delta,
14181 HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED,
14184 static int thunk_label = 0;
14186 int mi_delta = delta;
14187 const char *const mi_op = mi_delta < 0 ? "sub" : "add";
14189 int this_regno = (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function)
14192 mi_delta = - mi_delta;
14195 int labelno = thunk_label++;
14196 ASM_GENERATE_INTERNAL_LABEL (label, "LTHUMBFUNC", labelno);
14197 fputs ("\tldr\tr12, ", file);
14198 assemble_name (file, label);
14199 fputc ('\n', file);
14201 while (mi_delta != 0)
14203 if ((mi_delta & (3 << shift)) == 0)
14207 asm_fprintf (file, "\t%s\t%r, %r, #%d\n",
14208 mi_op, this_regno, this_regno,
14209 mi_delta & (0xff << shift));
14210 mi_delta &= ~(0xff << shift);
14216 fprintf (file, "\tbx\tr12\n");
14217 ASM_OUTPUT_ALIGN (file, 2);
14218 assemble_name (file, label);
14219 fputs (":\n", file);
14220 assemble_integer (XEXP (DECL_RTL (function), 0), 4, BITS_PER_WORD, 1);
14224 fputs ("\tb\t", file);
14225 assemble_name (file, XSTR (XEXP (DECL_RTL (function), 0), 0));
14226 if (NEED_PLT_RELOC)
14227 fputs ("(PLT)", file);
14228 fputc ('\n', file);
14233 arm_emit_vector_const (FILE *file, rtx x)
14236 const char * pattern;
14238 if (GET_CODE (x) != CONST_VECTOR)
14241 switch (GET_MODE (x))
14243 case V2SImode: pattern = "%08x"; break;
14244 case V4HImode: pattern = "%04x"; break;
14245 case V8QImode: pattern = "%02x"; break;
14249 fprintf (file, "0x");
14250 for (i = CONST_VECTOR_NUNITS (x); i--;)
14254 element = CONST_VECTOR_ELT (x, i);
14255 fprintf (file, pattern, INTVAL (element));
14262 arm_output_load_gr (rtx *operands)
14269 if (GET_CODE (operands [1]) != MEM
14270 || GET_CODE (sum = XEXP (operands [1], 0)) != PLUS
14271 || GET_CODE (reg = XEXP (sum, 0)) != REG
14272 || GET_CODE (offset = XEXP (sum, 1)) != CONST_INT
14273 || ((INTVAL (offset) < 1024) && (INTVAL (offset) > -1024)))
14274 return "wldrw%?\t%0, %1";
14276 /* Fix up an out-of-range load of a GR register. */
14277 output_asm_insn ("str%?\t%0, [sp, #-4]!\t@ Start of GR load expansion", & reg);
14278 wcgr = operands[0];
14280 output_asm_insn ("ldr%?\t%0, %1", operands);
14282 operands[0] = wcgr;
14284 output_asm_insn ("tmcr%?\t%0, %1", operands);
14285 output_asm_insn ("ldr%?\t%0, [sp], #4\t@ End of GR load expansion", & reg);
14291 arm_struct_value_rtx (tree fntype ATTRIBUTE_UNUSED,
14292 int incoming ATTRIBUTE_UNUSED)
14295 /* FIXME: The ARM backend has special code to handle structure
14296 returns, and will reserve its own hidden first argument. So
14297 if this macro is enabled a *second* hidden argument will be
14298 reserved, which will break binary compatibility with old
14299 toolchains and also thunk handling. One day this should be
14303 /* Register in which address to store a structure value
14304 is passed to a function. */
14305 return gen_rtx_REG (Pmode, ARG_REGISTER (1));
14309 /* Worker function for TARGET_SETUP_INCOMING_VARARGS.
14311 On the ARM, PRETEND_SIZE is set in order to have the prologue push the last
14312 named arg and all anonymous args onto the stack.
14313 XXX I know the prologue shouldn't be pushing registers, but it is faster
14317 arm_setup_incoming_varargs (CUMULATIVE_ARGS *cum,
14318 enum machine_mode mode ATTRIBUTE_UNUSED,
14319 tree type ATTRIBUTE_UNUSED,
14321 int second_time ATTRIBUTE_UNUSED)
14323 cfun->machine->uses_anonymous_args = 1;
14324 if (cum->nregs < NUM_ARG_REGS)
14325 *pretend_size = (NUM_ARG_REGS - cum->nregs) * UNITS_PER_WORD;
14328 /* Return nonzero if the CONSUMER instruction (a store) does not need
14329 PRODUCER's value to calculate the address. */
14332 arm_no_early_store_addr_dep (rtx producer, rtx consumer)
14334 rtx value = PATTERN (producer);
14335 rtx addr = PATTERN (consumer);
14337 if (GET_CODE (value) == COND_EXEC)
14338 value = COND_EXEC_CODE (value);
14339 if (GET_CODE (value) == PARALLEL)
14340 value = XVECEXP (value, 0, 0);
14341 value = XEXP (value, 0);
14342 if (GET_CODE (addr) == COND_EXEC)
14343 addr = COND_EXEC_CODE (addr);
14344 if (GET_CODE (addr) == PARALLEL)
14345 addr = XVECEXP (addr, 0, 0);
14346 addr = XEXP (addr, 0);
14348 return !reg_overlap_mentioned_p (value, addr);
14351 /* Return nonzero if the CONSUMER instruction (an ALU op) does not
14352 have an early register shift value or amount dependency on the
14353 result of PRODUCER. */
14356 arm_no_early_alu_shift_dep (rtx producer, rtx consumer)
14358 rtx value = PATTERN (producer);
14359 rtx op = PATTERN (consumer);
14362 if (GET_CODE (value) == COND_EXEC)
14363 value = COND_EXEC_CODE (value);
14364 if (GET_CODE (value) == PARALLEL)
14365 value = XVECEXP (value, 0, 0);
14366 value = XEXP (value, 0);
14367 if (GET_CODE (op) == COND_EXEC)
14368 op = COND_EXEC_CODE (op);
14369 if (GET_CODE (op) == PARALLEL)
14370 op = XVECEXP (op, 0, 0);
14373 early_op = XEXP (op, 0);
14374 /* This is either an actual independent shift, or a shift applied to
14375 the first operand of another operation. We want the whole shift
14377 if (GET_CODE (early_op) == REG)
14380 return !reg_overlap_mentioned_p (value, early_op);
14383 /* Return nonzero if the CONSUMER instruction (an ALU op) does not
14384 have an early register shift value dependency on the result of
14388 arm_no_early_alu_shift_value_dep (rtx producer, rtx consumer)
14390 rtx value = PATTERN (producer);
14391 rtx op = PATTERN (consumer);
14394 if (GET_CODE (value) == COND_EXEC)
14395 value = COND_EXEC_CODE (value);
14396 if (GET_CODE (value) == PARALLEL)
14397 value = XVECEXP (value, 0, 0);
14398 value = XEXP (value, 0);
14399 if (GET_CODE (op) == COND_EXEC)
14400 op = COND_EXEC_CODE (op);
14401 if (GET_CODE (op) == PARALLEL)
14402 op = XVECEXP (op, 0, 0);
14405 early_op = XEXP (op, 0);
14407 /* This is either an actual independent shift, or a shift applied to
14408 the first operand of another operation. We want the value being
14409 shifted, in either case. */
14410 if (GET_CODE (early_op) != REG)
14411 early_op = XEXP (early_op, 0);
14413 return !reg_overlap_mentioned_p (value, early_op);
14416 /* Return nonzero if the CONSUMER (a mul or mac op) does not
14417 have an early register mult dependency on the result of
14421 arm_no_early_mul_dep (rtx producer, rtx consumer)
14423 rtx value = PATTERN (producer);
14424 rtx op = PATTERN (consumer);
14426 if (GET_CODE (value) == COND_EXEC)
14427 value = COND_EXEC_CODE (value);
14428 if (GET_CODE (value) == PARALLEL)
14429 value = XVECEXP (value, 0, 0);
14430 value = XEXP (value, 0);
14431 if (GET_CODE (op) == COND_EXEC)
14432 op = COND_EXEC_CODE (op);
14433 if (GET_CODE (op) == PARALLEL)
14434 op = XVECEXP (op, 0, 0);
14437 return (GET_CODE (op) == PLUS
14438 && !reg_overlap_mentioned_p (value, XEXP (op, 0)));
14442 /* We can't rely on the caller doing the proper promotion when
14443 using APCS or ATPCS. */
14446 arm_promote_prototypes (tree t ATTRIBUTE_UNUSED)
14448 return arm_abi == ARM_ABI_APCS || arm_abi == ARM_ABI_ATPCS;