1 /* Output routines for GCC for ARM.
2 Copyright (C) 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001
3 Free Software Foundation, Inc.
4 Contributed by Pieter `Tiggr' Schoenmakers (rcpieter@win.tue.nl)
5 and Martin Simmons (@harleqn.co.uk).
6 More major hacks by Richard Earnshaw (rearnsha@arm.com).
8 This file is part of GNU CC.
10 GNU CC is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2, or (at your option)
15 GNU CC is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GNU CC; see the file COPYING. If not, write to
22 the Free Software Foundation, 59 Temple Place - Suite 330,
23 Boston, MA 02111-1307, USA. */
31 #include "hard-reg-set.h"
33 #include "insn-config.h"
34 #include "conditions.h"
36 #include "insn-attr.h"
48 /* Forward definitions of types. */
49 typedef struct minipool_node Mnode;
50 typedef struct minipool_fixup Mfix;
52 /* In order to improve the layout of the prototypes below
53 some short type abbreviations are defined here. */
54 #define Hint HOST_WIDE_INT
55 #define Mmode enum machine_mode
56 #define Ulong unsigned long
57 #define Ccstar const char *
59 /* Forward function declarations. */
60 static void arm_add_gc_roots PARAMS ((void));
61 static int arm_gen_constant PARAMS ((enum rtx_code, Mmode, Hint, rtx, rtx, int, int));
62 static Ulong bit_count PARAMS ((signed int));
63 static int const_ok_for_op PARAMS ((Hint, enum rtx_code));
64 static int eliminate_lr2ip PARAMS ((rtx *));
65 static rtx emit_multi_reg_push PARAMS ((int));
66 static rtx emit_sfm PARAMS ((int, int));
67 static Ccstar fp_const_from_val PARAMS ((REAL_VALUE_TYPE *));
68 static arm_cc get_arm_condition_code PARAMS ((rtx));
69 static void init_fpa_table PARAMS ((void));
70 static Hint int_log2 PARAMS ((Hint));
71 static rtx is_jump_table PARAMS ((rtx));
72 static Ccstar output_multi_immediate PARAMS ((rtx *, Ccstar, Ccstar, int, Hint));
73 static void print_multi_reg PARAMS ((FILE *, Ccstar, int, int));
74 static Mmode select_dominance_cc_mode PARAMS ((rtx, rtx, Hint));
75 static Ccstar shift_op PARAMS ((rtx, Hint *));
76 static void arm_init_machine_status PARAMS ((struct function *));
77 static void arm_mark_machine_status PARAMS ((struct function *));
78 static void arm_free_machine_status PARAMS ((struct function *));
79 static int number_of_first_bit_set PARAMS ((int));
80 static void replace_symbols_in_block PARAMS ((tree, rtx, rtx));
81 static void thumb_exit PARAMS ((FILE *, int, rtx));
82 static void thumb_pushpop PARAMS ((FILE *, int, int));
83 static Ccstar thumb_condition_code PARAMS ((rtx, int));
84 static rtx is_jump_table PARAMS ((rtx));
85 static Hint get_jump_table_size PARAMS ((rtx));
86 static Mnode * move_minipool_fix_forward_ref PARAMS ((Mnode *, Mnode *, Hint));
87 static Mnode * add_minipool_forward_ref PARAMS ((Mfix *));
88 static Mnode * move_minipool_fix_backward_ref PARAMS ((Mnode *, Mnode *, Hint));
89 static Mnode * add_minipool_backward_ref PARAMS ((Mfix *));
90 static void assign_minipool_offsets PARAMS ((Mfix *));
91 static void arm_print_value PARAMS ((FILE *, rtx));
92 static void dump_minipool PARAMS ((rtx));
93 static int arm_barrier_cost PARAMS ((rtx));
94 static Mfix * create_fix_barrier PARAMS ((Mfix *, Hint));
95 static void push_minipool_barrier PARAMS ((rtx, Hint));
96 static void push_minipool_fix PARAMS ((rtx, Hint, rtx *, Mmode, rtx));
97 static void note_invalid_constants PARAMS ((rtx, Hint));
98 static int current_file_function_operand PARAMS ((rtx));
99 static Ulong arm_compute_save_reg_mask PARAMS ((void));
100 static Ulong arm_isr_value PARAMS ((tree));
101 static Ulong arm_compute_func_type PARAMS ((void));
108 /* Obstack for minipool constant handling. */
109 static struct obstack minipool_obstack;
110 static char *minipool_startobj;
112 #define obstack_chunk_alloc xmalloc
113 #define obstack_chunk_free free
115 /* The maximum number of insns skipped which will be conditionalised if
117 static int max_insns_skipped = 5;
119 extern FILE * asm_out_file;
121 /* True if we are currently building a constant table. */
122 int making_const_table;
124 /* Define the information needed to generate branch insns. This is
125 stored from the compare operation. */
126 rtx arm_compare_op0, arm_compare_op1;
128 /* What type of floating point are we tuning for? */
129 enum floating_point_type arm_fpu;
131 /* What type of floating point instructions are available? */
132 enum floating_point_type arm_fpu_arch;
134 /* What program mode is the cpu running in? 26-bit mode or 32-bit mode. */
135 enum prog_mode_type arm_prgmode;
137 /* Set by the -mfp=... option. */
138 const char * target_fp_name = NULL;
140 /* Used to parse -mstructure_size_boundary command line option. */
141 const char * structure_size_string = NULL;
142 int arm_structure_size_boundary = DEFAULT_STRUCTURE_SIZE_BOUNDARY;
144 /* Bit values used to identify processor capabilities. */
145 #define FL_CO_PROC (1 << 0) /* Has external co-processor bus */
146 #define FL_FAST_MULT (1 << 1) /* Fast multiply */
147 #define FL_MODE26 (1 << 2) /* 26-bit mode support */
148 #define FL_MODE32 (1 << 3) /* 32-bit mode support */
149 #define FL_ARCH4 (1 << 4) /* Architecture rel 4 */
150 #define FL_ARCH5 (1 << 5) /* Architecture rel 5 */
151 #define FL_THUMB (1 << 6) /* Thumb aware */
152 #define FL_LDSCHED (1 << 7) /* Load scheduling necessary */
153 #define FL_STRONG (1 << 8) /* StrongARM */
154 #define FL_ARCH5E (1 << 9) /* DSP extenstions to v5 */
155 #define FL_XSCALE (1 << 10) /* XScale */
157 /* The bits in this mask specify which instructions we are
158 allowed to generate. */
159 static int insn_flags = 0;
161 /* The bits in this mask specify which instruction scheduling options should
162 be used. Note - there is an overlap with the FL_FAST_MULT. For some
163 hardware we want to be able to generate the multiply instructions, but to
164 tune as if they were not present in the architecture. */
165 static int tune_flags = 0;
167 /* The following are used in the arm.md file as equivalents to bits
168 in the above two flag variables. */
170 /* Nonzero if this is an "M" variant of the processor. */
171 int arm_fast_multiply = 0;
173 /* Nonzero if this chip supports the ARM Architecture 4 extensions. */
176 /* Nonzero if this chip supports the ARM Architecture 5 extensions. */
179 /* Nonzero if this chip supports the ARM Architecture 5E extensions. */
182 /* Nonzero if this chip can benefit from load scheduling. */
183 int arm_ld_sched = 0;
185 /* Nonzero if this chip is a StrongARM. */
186 int arm_is_strong = 0;
188 /* Nonzero if this chip is an XScale. */
189 int arm_is_xscale = 0;
191 /* Nonzero if this chip is a an ARM6 or an ARM7. */
192 int arm_is_6_or_7 = 0;
194 /* Nonzero if generating Thumb instructions. */
197 /* In case of a PRE_INC, POST_INC, PRE_DEC, POST_DEC memory reference, we
198 must report the mode of the memory reference from PRINT_OPERAND to
199 PRINT_OPERAND_ADDRESS. */
200 enum machine_mode output_memory_reference_mode;
202 /* Nonzero if the prologue must setup `fp'. */
203 int current_function_anonymous_args;
205 /* The register number to be used for the PIC offset register. */
206 const char * arm_pic_register_string = NULL;
207 int arm_pic_register = 9;
209 /* Set to 1 when a return insn is output, this means that the epilogue
211 int return_used_this_function;
213 /* Set to 1 after arm_reorg has started. Reset to start at the start of
214 the next function. */
215 static int after_arm_reorg = 0;
217 /* The maximum number of insns to be used when loading a constant. */
218 static int arm_constant_limit = 3;
220 /* For an explanation of these variables, see final_prescan_insn below. */
222 enum arm_cond_code arm_current_cc;
224 int arm_target_label;
226 /* The condition codes of the ARM, and the inverse function. */
227 const char * arm_condition_codes[] =
229 "eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc",
230 "hi", "ls", "ge", "lt", "gt", "le", "al", "nv"
233 #define streq(string1, string2) (strcmp (string1, string2) == 0)
235 /* Initialization code. */
243 /* Not all of these give usefully different compilation alternatives,
244 but there is no simple way of generalizing them. */
245 static struct processors all_cores[] =
249 {"arm2", FL_CO_PROC | FL_MODE26 },
250 {"arm250", FL_CO_PROC | FL_MODE26 },
251 {"arm3", FL_CO_PROC | FL_MODE26 },
252 {"arm6", FL_CO_PROC | FL_MODE26 | FL_MODE32 },
253 {"arm60", FL_CO_PROC | FL_MODE26 | FL_MODE32 },
254 {"arm600", FL_CO_PROC | FL_MODE26 | FL_MODE32 },
255 {"arm610", FL_MODE26 | FL_MODE32 },
256 {"arm620", FL_CO_PROC | FL_MODE26 | FL_MODE32 },
257 {"arm7", FL_CO_PROC | FL_MODE26 | FL_MODE32 },
258 /* arm7m doesn't exist on its own, but only with D, (and I), but
259 those don't alter the code, so arm7m is sometimes used. */
260 {"arm7m", FL_CO_PROC | FL_MODE26 | FL_MODE32 | FL_FAST_MULT },
261 {"arm7d", FL_CO_PROC | FL_MODE26 | FL_MODE32 },
262 {"arm7dm", FL_CO_PROC | FL_MODE26 | FL_MODE32 | FL_FAST_MULT },
263 {"arm7di", FL_CO_PROC | FL_MODE26 | FL_MODE32 },
264 {"arm7dmi", FL_CO_PROC | FL_MODE26 | FL_MODE32 | FL_FAST_MULT },
265 {"arm70", FL_CO_PROC | FL_MODE26 | FL_MODE32 },
266 {"arm700", FL_CO_PROC | FL_MODE26 | FL_MODE32 },
267 {"arm700i", FL_CO_PROC | FL_MODE26 | FL_MODE32 },
268 {"arm710", FL_MODE26 | FL_MODE32 },
269 {"arm710t", FL_MODE26 | FL_MODE32 | FL_THUMB },
270 {"arm720", FL_MODE26 | FL_MODE32 },
271 {"arm720t", FL_MODE26 | FL_MODE32 | FL_THUMB },
272 {"arm740t", FL_MODE26 | FL_MODE32 | FL_THUMB },
273 {"arm710c", FL_MODE26 | FL_MODE32 },
274 {"arm7100", FL_MODE26 | FL_MODE32 },
275 {"arm7500", FL_MODE26 | FL_MODE32 },
276 /* Doesn't have an external co-proc, but does have embedded fpu. */
277 {"arm7500fe", FL_CO_PROC | FL_MODE26 | FL_MODE32 },
278 {"arm7tdmi", FL_CO_PROC | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB },
279 {"arm8", FL_MODE26 | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_LDSCHED },
280 {"arm810", FL_MODE26 | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_LDSCHED },
281 {"arm9", FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB | FL_LDSCHED },
282 {"arm920", FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_LDSCHED },
283 {"arm920t", FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB | FL_LDSCHED },
284 {"arm940t", FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB | FL_LDSCHED },
285 {"arm9tdmi", FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB | FL_LDSCHED },
286 {"arm9e", FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_LDSCHED },
287 {"strongarm", FL_MODE26 | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_LDSCHED | FL_STRONG },
288 {"strongarm110", FL_MODE26 | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_LDSCHED | FL_STRONG },
289 {"strongarm1100", FL_MODE26 | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_LDSCHED | FL_STRONG },
290 {"strongarm1110", FL_MODE26 | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_LDSCHED | FL_STRONG },
291 {"arm10tdmi", FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB | FL_LDSCHED | FL_ARCH5 },
292 {"arm1020t", FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB | FL_LDSCHED | FL_ARCH5 },
293 {"xscale", FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB | FL_LDSCHED | FL_STRONG | FL_ARCH5 | FL_ARCH5E | FL_XSCALE },
298 static struct processors all_architectures[] =
300 /* ARM Architectures */
302 { "armv2", FL_CO_PROC | FL_MODE26 },
303 { "armv2a", FL_CO_PROC | FL_MODE26 },
304 { "armv3", FL_CO_PROC | FL_MODE26 | FL_MODE32 },
305 { "armv3m", FL_CO_PROC | FL_MODE26 | FL_MODE32 | FL_FAST_MULT },
306 { "armv4", FL_CO_PROC | FL_MODE26 | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 },
307 /* Strictly, FL_MODE26 is a permitted option for v4t, but there are no
308 implementations that support it, so we will leave it out for now. */
309 { "armv4t", FL_CO_PROC | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB },
310 { "armv5", FL_CO_PROC | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB | FL_ARCH5 },
311 { "armv5t", FL_CO_PROC | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB | FL_ARCH5 },
312 { "armv5te", FL_CO_PROC | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB | FL_ARCH5 | FL_ARCH5E },
316 /* This is a magic stucture. The 'string' field is magically filled in
317 with a pointer to the value specified by the user on the command line
318 assuming that the user has specified such a value. */
320 struct arm_cpu_select arm_select[] =
322 /* string name processors */
323 { NULL, "-mcpu=", all_cores },
324 { NULL, "-march=", all_architectures },
325 { NULL, "-mtune=", all_cores }
328 /* Return the number of bits set in value' */
333 unsigned long count = 0;
337 value &= ~(value & -value);
344 /* Fix up any incompatible options that the user has specified.
345 This has now turned into a maze. */
347 arm_override_options ()
351 /* Set up the flags based on the cpu/architecture selected by the user. */
352 for (i = ARRAY_SIZE (arm_select); i--;)
354 struct arm_cpu_select * ptr = arm_select + i;
356 if (ptr->string != NULL && ptr->string[0] != '\0')
358 const struct processors * sel;
360 for (sel = ptr->processors; sel->name != NULL; sel++)
361 if (streq (ptr->string, sel->name))
364 tune_flags = sel->flags;
367 /* If we have been given an architecture and a processor
368 make sure that they are compatible. We only generate
369 a warning though, and we prefer the CPU over the
371 if (insn_flags != 0 && (insn_flags ^ sel->flags))
372 warning ("switch -mcpu=%s conflicts with -march= switch",
375 insn_flags = sel->flags;
381 if (sel->name == NULL)
382 error ("bad value (%s) for %s switch", ptr->string, ptr->name);
386 /* If the user did not specify a processor, choose one for them. */
389 struct processors * sel;
391 static struct cpu_default
398 { TARGET_CPU_arm2, "arm2" },
399 { TARGET_CPU_arm6, "arm6" },
400 { TARGET_CPU_arm610, "arm610" },
401 { TARGET_CPU_arm710, "arm710" },
402 { TARGET_CPU_arm7m, "arm7m" },
403 { TARGET_CPU_arm7500fe, "arm7500fe" },
404 { TARGET_CPU_arm7tdmi, "arm7tdmi" },
405 { TARGET_CPU_arm8, "arm8" },
406 { TARGET_CPU_arm810, "arm810" },
407 { TARGET_CPU_arm9, "arm9" },
408 { TARGET_CPU_strongarm, "strongarm" },
409 { TARGET_CPU_xscale, "xscale" },
410 { TARGET_CPU_generic, "arm" },
413 struct cpu_default * def;
415 /* Find the default. */
416 for (def = cpu_defaults; def->name; def++)
417 if (def->cpu == TARGET_CPU_DEFAULT)
420 /* Make sure we found the default CPU. */
421 if (def->name == NULL)
424 /* Find the default CPU's flags. */
425 for (sel = all_cores; sel->name != NULL; sel++)
426 if (streq (def->name, sel->name))
429 if (sel->name == NULL)
432 insn_flags = sel->flags;
434 /* Now check to see if the user has specified some command line
435 switch that require certain abilities from the cpu. */
438 if (TARGET_INTERWORK || TARGET_THUMB)
440 sought |= (FL_THUMB | FL_MODE32);
442 /* Force apcs-32 to be used for interworking. */
443 target_flags |= ARM_FLAG_APCS_32;
445 /* There are no ARM processors that support both APCS-26 and
446 interworking. Therefore we force FL_MODE26 to be removed
447 from insn_flags here (if it was set), so that the search
448 below will always be able to find a compatible processor. */
449 insn_flags &= ~FL_MODE26;
451 else if (!TARGET_APCS_32)
454 if (sought != 0 && ((sought & insn_flags) != sought))
456 /* Try to locate a CPU type that supports all of the abilities
457 of the default CPU, plus the extra abilities requested by
459 for (sel = all_cores; sel->name != NULL; sel++)
460 if ((sel->flags & sought) == (sought | insn_flags))
463 if (sel->name == NULL)
465 unsigned int current_bit_count = 0;
466 struct processors * best_fit = NULL;
468 /* Ideally we would like to issue an error message here
469 saying that it was not possible to find a CPU compatible
470 with the default CPU, but which also supports the command
471 line options specified by the programmer, and so they
472 ought to use the -mcpu=<name> command line option to
473 override the default CPU type.
475 Unfortunately this does not work with multilibing. We
476 need to be able to support multilibs for -mapcs-26 and for
477 -mthumb-interwork and there is no CPU that can support both
478 options. Instead if we cannot find a cpu that has both the
479 characteristics of the default cpu and the given command line
480 options we scan the array again looking for a best match. */
481 for (sel = all_cores; sel->name != NULL; sel++)
482 if ((sel->flags & sought) == sought)
486 count = bit_count (sel->flags & insn_flags);
488 if (count >= current_bit_count)
491 current_bit_count = count;
495 if (best_fit == NULL)
501 insn_flags = sel->flags;
505 /* If tuning has not been specified, tune for whichever processor or
506 architecture has been selected. */
508 tune_flags = insn_flags;
510 /* Make sure that the processor choice does not conflict with any of the
511 other command line choices. */
512 if (TARGET_APCS_32 && !(insn_flags & FL_MODE32))
514 /* If APCS-32 was not the default then it must have been set by the
515 user, so issue a warning message. If the user has specified
516 "-mapcs-32 -mcpu=arm2" then we loose here. */
517 if ((TARGET_DEFAULT & ARM_FLAG_APCS_32) == 0)
518 warning ("target CPU does not support APCS-32" );
519 target_flags &= ~ARM_FLAG_APCS_32;
521 else if (!TARGET_APCS_32 && !(insn_flags & FL_MODE26))
523 warning ("target CPU does not support APCS-26" );
524 target_flags |= ARM_FLAG_APCS_32;
527 if (TARGET_INTERWORK && !(insn_flags & FL_THUMB))
529 warning ("target CPU does not support interworking" );
530 target_flags &= ~ARM_FLAG_INTERWORK;
533 if (TARGET_THUMB && !(insn_flags & FL_THUMB))
535 warning ("target CPU does not support THUMB instructions.");
536 target_flags &= ~ARM_FLAG_THUMB;
539 if (TARGET_APCS_FRAME && TARGET_THUMB)
541 /* warning ("ignoring -mapcs-frame because -mthumb was used."); */
542 target_flags &= ~ARM_FLAG_APCS_FRAME;
545 /* TARGET_BACKTRACE calls leaf_function_p, which causes a crash if done
546 from here where no function is being compiled currently. */
547 if ((target_flags & (THUMB_FLAG_LEAF_BACKTRACE | THUMB_FLAG_BACKTRACE))
549 warning ("enabling backtrace support is only meaningful when compiling for the Thumb.");
551 if (TARGET_ARM && TARGET_CALLEE_INTERWORKING)
552 warning ("enabling callee interworking support is only meaningful when compiling for the Thumb.");
554 if (TARGET_ARM && TARGET_CALLER_INTERWORKING)
555 warning ("enabling caller interworking support is only meaningful when compiling for the Thumb.");
557 /* If interworking is enabled then APCS-32 must be selected as well. */
558 if (TARGET_INTERWORK)
561 warning ("interworking forces APCS-32 to be used" );
562 target_flags |= ARM_FLAG_APCS_32;
565 if (TARGET_APCS_STACK && !TARGET_APCS_FRAME)
567 warning ("-mapcs-stack-check incompatible with -mno-apcs-frame");
568 target_flags |= ARM_FLAG_APCS_FRAME;
571 if (TARGET_POKE_FUNCTION_NAME)
572 target_flags |= ARM_FLAG_APCS_FRAME;
574 if (TARGET_APCS_REENT && flag_pic)
575 error ("-fpic and -mapcs-reent are incompatible");
577 if (TARGET_APCS_REENT)
578 warning ("APCS reentrant code not supported. Ignored");
580 /* If this target is normally configured to use APCS frames, warn if they
581 are turned off and debugging is turned on. */
583 && write_symbols != NO_DEBUG
584 && !TARGET_APCS_FRAME
585 && (TARGET_DEFAULT & ARM_FLAG_APCS_FRAME))
586 warning ("-g with -mno-apcs-frame may not give sensible debugging");
588 /* If stack checking is disabled, we can use r10 as the PIC register,
589 which keeps r9 available. */
590 if (flag_pic && !TARGET_APCS_STACK)
591 arm_pic_register = 10;
593 if (TARGET_APCS_FLOAT)
594 warning ("Passing floating point arguments in fp regs not yet supported");
596 /* Initialise boolean versions of the flags, for use in the arm.md file. */
597 arm_fast_multiply = (insn_flags & FL_FAST_MULT) != 0;
598 arm_arch4 = (insn_flags & FL_ARCH4) != 0;
599 arm_arch5 = (insn_flags & FL_ARCH5) != 0;
600 arm_arch5e = (insn_flags & FL_ARCH5E) != 0;
601 arm_is_xscale = (insn_flags & FL_XSCALE) != 0;
603 arm_ld_sched = (tune_flags & FL_LDSCHED) != 0;
604 arm_is_strong = (tune_flags & FL_STRONG) != 0;
605 thumb_code = (TARGET_ARM == 0);
606 arm_is_6_or_7 = (((tune_flags & (FL_MODE26 | FL_MODE32))
607 && !(tune_flags & FL_ARCH4))) != 0;
609 /* Default value for floating point code... if no co-processor
610 bus, then schedule for emulated floating point. Otherwise,
611 assume the user has an FPA.
612 Note: this does not prevent use of floating point instructions,
613 -msoft-float does that. */
614 arm_fpu = (tune_flags & FL_CO_PROC) ? FP_HARD : FP_SOFT3;
618 if (streq (target_fp_name, "2"))
619 arm_fpu_arch = FP_SOFT2;
620 else if (streq (target_fp_name, "3"))
621 arm_fpu_arch = FP_SOFT3;
623 error ("Invalid floating point emulation option: -mfpe-%s",
627 arm_fpu_arch = FP_DEFAULT;
629 if (TARGET_FPE && arm_fpu != FP_HARD)
632 /* For arm2/3 there is no need to do any scheduling if there is only
633 a floating point emulator, or we are doing software floating-point. */
634 if ((TARGET_SOFT_FLOAT || arm_fpu != FP_HARD)
635 && (tune_flags & FL_MODE32) == 0)
636 flag_schedule_insns = flag_schedule_insns_after_reload = 0;
638 arm_prgmode = TARGET_APCS_32 ? PROG_MODE_PROG32 : PROG_MODE_PROG26;
640 if (structure_size_string != NULL)
642 int size = strtol (structure_size_string, NULL, 0);
644 if (size == 8 || size == 32)
645 arm_structure_size_boundary = size;
647 warning ("Structure size boundary can only be set to 8 or 32");
650 if (arm_pic_register_string != NULL)
655 warning ("-mpic-register= is useless without -fpic");
657 pic_register = decode_reg_name (arm_pic_register_string);
659 /* Prevent the user from choosing an obviously stupid PIC register. */
660 if (pic_register < 0 || call_used_regs[pic_register]
661 || pic_register == HARD_FRAME_POINTER_REGNUM
662 || pic_register == STACK_POINTER_REGNUM
663 || pic_register >= PC_REGNUM)
664 error ("Unable to use '%s' for PIC register", arm_pic_register_string);
666 arm_pic_register = pic_register;
669 if (TARGET_THUMB && flag_schedule_insns)
671 /* Don't warn since it's on by default in -O2. */
672 flag_schedule_insns = 0;
675 /* If optimizing for space, don't synthesize constants.
676 For processors with load scheduling, it never costs more than 2 cycles
677 to load a constant, and the load scheduler may well reduce that to 1. */
678 if (optimize_size || (tune_flags & FL_LDSCHED))
679 arm_constant_limit = 1;
682 arm_constant_limit = 2;
684 /* If optimizing for size, bump the number of instructions that we
685 are prepared to conditionally execute (even on a StrongARM).
686 Otherwise for the StrongARM, which has early execution of branches,
687 a sequence that is worth skipping is shorter. */
689 max_insns_skipped = 6;
690 else if (arm_is_strong)
691 max_insns_skipped = 3;
693 /* Register global variables with the garbage collector. */
700 ggc_add_rtx_root (&arm_compare_op0, 1);
701 ggc_add_rtx_root (&arm_compare_op1, 1);
702 ggc_add_rtx_root (&arm_target_insn, 1); /* Not sure this is really a root. */
704 gcc_obstack_init(&minipool_obstack);
705 minipool_startobj = (char *) obstack_alloc (&minipool_obstack, 0);
708 /* A table of known ARM exception types.
709 For use with the interrupt function attribute. */
714 unsigned long return_value;
718 static isr_attribute_arg isr_attribute_args [] =
720 { "IRQ", ARM_FT_ISR },
721 { "irq", ARM_FT_ISR },
722 { "FIQ", ARM_FT_FIQ },
723 { "fiq", ARM_FT_FIQ },
724 { "ABORT", ARM_FT_ISR },
725 { "abort", ARM_FT_ISR },
726 { "ABORT", ARM_FT_ISR },
727 { "abort", ARM_FT_ISR },
728 { "UNDEF", ARM_FT_EXCEPTION },
729 { "undef", ARM_FT_EXCEPTION },
730 { "SWI", ARM_FT_EXCEPTION },
731 { "swi", ARM_FT_EXCEPTION },
732 { NULL, ARM_FT_NORMAL }
735 /* Returns the (interrupt) function type of the current
736 function, or ARM_FT_UNKNOWN if the type cannot be determined. */
739 arm_isr_value (argument)
742 isr_attribute_arg * ptr;
745 /* No argument - default to IRQ. */
746 if (argument == NULL_TREE)
749 /* Get the value of the argument. */
750 if (TREE_VALUE (argument) == NULL_TREE
751 || TREE_CODE (TREE_VALUE (argument)) != STRING_CST)
752 return ARM_FT_UNKNOWN;
754 arg = TREE_STRING_POINTER (TREE_VALUE (argument));
756 /* Check it against the list of known arguments. */
757 for (ptr = isr_attribute_args; ptr->arg != NULL; ptr ++)
758 if (strcmp (arg, ptr->arg) == 0)
759 return ptr->return_value;
761 /* An unrecognised interrupt type. */
762 return ARM_FT_UNKNOWN;
765 /* Computes the type of the current function. */
768 arm_compute_func_type ()
770 unsigned long type = ARM_FT_UNKNOWN;
774 if (TREE_CODE (current_function_decl) != FUNCTION_DECL)
777 /* Decide if the current function is volatile. Such functions
778 never return, and many memory cycles can be saved by not storing
779 register values that will never be needed again. This optimization
780 was added to speed up context switching in a kernel application. */
782 && current_function_nothrow
783 && TREE_THIS_VOLATILE (current_function_decl))
784 type |= ARM_FT_VOLATILE;
786 if (current_function_needs_context)
787 type |= ARM_FT_NESTED;
789 attr = DECL_MACHINE_ATTRIBUTES (current_function_decl);
791 a = lookup_attribute ("naked", attr);
793 type |= ARM_FT_NAKED;
795 if (cfun->machine->eh_epilogue_sp_ofs != NULL_RTX)
796 type |= ARM_FT_EXCEPTION_HANDLER;
799 a = lookup_attribute ("isr", attr);
801 a = lookup_attribute ("interrupt", attr);
804 type |= TARGET_INTERWORK ? ARM_FT_INTERWORKED : ARM_FT_NORMAL;
806 type |= arm_isr_value (TREE_VALUE (a));
812 /* Returns the type of the current function. */
815 arm_current_func_type ()
817 if (ARM_FUNC_TYPE (cfun->machine->func_type) == ARM_FT_UNKNOWN)
818 cfun->machine->func_type = arm_compute_func_type ();
820 return cfun->machine->func_type;
823 /* Return 1 if it is possible to return using a single instruction. */
826 use_return_insn (iscond)
830 unsigned int func_type;
832 /* Never use a return instruction before reload has run. */
833 if (!reload_completed)
836 func_type = arm_current_func_type ();
838 /* Naked functions, volatile functiond and interrupt
839 functions all need special consideration. */
840 if (func_type & (ARM_FT_INTERRUPT | ARM_FT_VOLATILE | ARM_FT_NAKED))
843 /* As do variadic functions. */
844 if (current_function_pretend_args_size
845 || current_function_anonymous_args
846 /* Of if the function calls __builtin_eh_return () */
847 || ARM_FUNC_TYPE (func_type) == ARM_FT_EXCEPTION_HANDLER
848 /* Or if there is no frame pointer and there is a stack adjustment. */
849 || ((get_frame_size () + current_function_outgoing_args_size != 0)
850 && !frame_pointer_needed))
853 /* Can't be done if interworking with Thumb, and any registers have been
854 stacked. Similarly, on StrongARM, conditional returns are expensive
855 if they aren't taken and registers have been stacked. */
856 if (iscond && arm_is_strong && frame_pointer_needed)
859 if ((iscond && arm_is_strong)
862 for (regno = 0; regno <= LAST_ARM_REGNUM; regno++)
863 if (regs_ever_live[regno] && !call_used_regs[regno])
866 if (flag_pic && regs_ever_live[PIC_OFFSET_TABLE_REGNUM])
870 /* Can't be done if any of the FPU regs are pushed,
871 since this also requires an insn. */
872 if (TARGET_HARD_FLOAT)
873 for (regno = FIRST_ARM_FP_REGNUM; regno <= LAST_ARM_FP_REGNUM; regno++)
874 if (regs_ever_live[regno] && !call_used_regs[regno])
880 /* Return TRUE if int I is a valid immediate ARM constant. */
886 unsigned HOST_WIDE_INT mask = ~HOST_UINT (0xFF);
888 /* For machines with >32 bit HOST_WIDE_INT, the bits above bit 31 must
889 be all zero, or all one. */
890 if ((i & ~HOST_UINT (0xffffffff)) != 0
891 && ((i & ~HOST_UINT (0xffffffff))
893 & ~HOST_UINT (0xffffffff))))
896 /* Fast return for 0 and powers of 2 */
897 if ((i & (i - 1)) == 0)
902 if ((i & mask & HOST_UINT (0xffffffff)) == 0)
905 (mask << 2) | ((mask & HOST_UINT (0xffffffff))
906 >> (32 - 2)) | ~(HOST_UINT (0xffffffff));
907 } while (mask != ~HOST_UINT (0xFF));
912 /* Return true if I is a valid constant for the operation CODE. */
914 const_ok_for_op (i, code)
918 if (const_ok_for_arm (i))
924 return const_ok_for_arm (ARM_SIGN_EXTEND (-i));
926 case MINUS: /* Should only occur with (MINUS I reg) => rsb */
932 return const_ok_for_arm (ARM_SIGN_EXTEND (~i));
939 /* Emit a sequence of insns to handle a large constant.
940 CODE is the code of the operation required, it can be any of SET, PLUS,
941 IOR, AND, XOR, MINUS;
942 MODE is the mode in which the operation is being performed;
943 VAL is the integer to operate on;
944 SOURCE is the other operand (a register, or a null-pointer for SET);
945 SUBTARGETS means it is safe to create scratch registers if that will
946 either produce a simpler sequence, or we will want to cse the values.
947 Return value is the number of insns emitted. */
950 arm_split_constant (code, mode, val, target, source, subtargets)
952 enum machine_mode mode;
958 if (subtargets || code == SET
959 || (GET_CODE (target) == REG && GET_CODE (source) == REG
960 && REGNO (target) != REGNO (source)))
962 /* After arm_reorg has been called, we can't fix up expensive
963 constants by pushing them into memory so we must synthesise
964 them in-line, regardless of the cost. This is only likely to
965 be more costly on chips that have load delay slots and we are
966 compiling without running the scheduler (so no splitting
967 occurred before the final instruction emission).
969 Ref: gcc -O1 -mcpu=strongarm gcc.c-torture/compile/980506-2.c
972 && (arm_gen_constant (code, mode, val, target, source, 1, 0)
973 > arm_constant_limit + (code != SET)))
977 /* Currently SET is the only monadic value for CODE, all
978 the rest are diadic. */
979 emit_insn (gen_rtx_SET (VOIDmode, target, GEN_INT (val)));
984 rtx temp = subtargets ? gen_reg_rtx (mode) : target;
986 emit_insn (gen_rtx_SET (VOIDmode, temp, GEN_INT (val)));
987 /* For MINUS, the value is subtracted from, since we never
988 have subtraction of a constant. */
990 emit_insn (gen_rtx_SET (VOIDmode, target,
991 gen_rtx_MINUS (mode, temp, source)));
993 emit_insn (gen_rtx_SET (VOIDmode, target,
994 gen_rtx (code, mode, source, temp)));
1000 return arm_gen_constant (code, mode, val, target, source, subtargets, 1);
1004 count_insns_for_constant (HOST_WIDE_INT remainder, int i)
1006 HOST_WIDE_INT temp1;
1014 if (remainder & (3 << (i - 2)))
1019 temp1 = remainder & ((0x0ff << end)
1020 | ((i < end) ? (0xff >> (32 - end)) : 0));
1021 remainder &= ~temp1;
1026 } while (remainder);
1030 /* As above, but extra parameter GENERATE which, if clear, suppresses
1033 arm_gen_constant (code, mode, val, target, source, subtargets, generate)
1035 enum machine_mode mode;
1044 int can_negate_initial = 0;
1047 int num_bits_set = 0;
1048 int set_sign_bit_copies = 0;
1049 int clear_sign_bit_copies = 0;
1050 int clear_zero_bit_copies = 0;
1051 int set_zero_bit_copies = 0;
1053 unsigned HOST_WIDE_INT temp1, temp2;
1054 unsigned HOST_WIDE_INT remainder = val & HOST_UINT (0xffffffff);
1056 /* Find out which operations are safe for a given CODE. Also do a quick
1057 check for degenerate cases; these can occur when DImode operations
1069 can_negate_initial = 1;
1073 if (remainder == HOST_UINT (0xffffffff))
1076 emit_insn (gen_rtx_SET (VOIDmode, target,
1077 GEN_INT (ARM_SIGN_EXTEND (val))));
1082 if (reload_completed && rtx_equal_p (target, source))
1085 emit_insn (gen_rtx_SET (VOIDmode, target, source));
1094 emit_insn (gen_rtx_SET (VOIDmode, target, const0_rtx));
1097 if (remainder == HOST_UINT (0xffffffff))
1099 if (reload_completed && rtx_equal_p (target, source))
1102 emit_insn (gen_rtx_SET (VOIDmode, target, source));
1111 if (reload_completed && rtx_equal_p (target, source))
1114 emit_insn (gen_rtx_SET (VOIDmode, target, source));
1117 if (remainder == HOST_UINT (0xffffffff))
1120 emit_insn (gen_rtx_SET (VOIDmode, target,
1121 gen_rtx_NOT (mode, source)));
1125 /* We don't know how to handle this yet below. */
1129 /* We treat MINUS as (val - source), since (source - val) is always
1130 passed as (source + (-val)). */
1134 emit_insn (gen_rtx_SET (VOIDmode, target,
1135 gen_rtx_NEG (mode, source)));
1138 if (const_ok_for_arm (val))
1141 emit_insn (gen_rtx_SET (VOIDmode, target,
1142 gen_rtx_MINUS (mode, GEN_INT (val),
1154 /* If we can do it in one insn get out quickly. */
1155 if (const_ok_for_arm (val)
1156 || (can_negate_initial && const_ok_for_arm (-val))
1157 || (can_invert && const_ok_for_arm (~val)))
1160 emit_insn (gen_rtx_SET (VOIDmode, target,
1161 (source ? gen_rtx (code, mode, source,
1167 /* Calculate a few attributes that may be useful for specific
1169 for (i = 31; i >= 0; i--)
1171 if ((remainder & (1 << i)) == 0)
1172 clear_sign_bit_copies++;
1177 for (i = 31; i >= 0; i--)
1179 if ((remainder & (1 << i)) != 0)
1180 set_sign_bit_copies++;
1185 for (i = 0; i <= 31; i++)
1187 if ((remainder & (1 << i)) == 0)
1188 clear_zero_bit_copies++;
1193 for (i = 0; i <= 31; i++)
1195 if ((remainder & (1 << i)) != 0)
1196 set_zero_bit_copies++;
1204 /* See if we can do this by sign_extending a constant that is known
1205 to be negative. This is a good, way of doing it, since the shift
1206 may well merge into a subsequent insn. */
1207 if (set_sign_bit_copies > 1)
1209 if (const_ok_for_arm
1210 (temp1 = ARM_SIGN_EXTEND (remainder
1211 << (set_sign_bit_copies - 1))))
1215 rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
1216 emit_insn (gen_rtx_SET (VOIDmode, new_src,
1218 emit_insn (gen_ashrsi3 (target, new_src,
1219 GEN_INT (set_sign_bit_copies - 1)));
1223 /* For an inverted constant, we will need to set the low bits,
1224 these will be shifted out of harm's way. */
1225 temp1 |= (1 << (set_sign_bit_copies - 1)) - 1;
1226 if (const_ok_for_arm (~temp1))
1230 rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
1231 emit_insn (gen_rtx_SET (VOIDmode, new_src,
1233 emit_insn (gen_ashrsi3 (target, new_src,
1234 GEN_INT (set_sign_bit_copies - 1)));
1240 /* See if we can generate this by setting the bottom (or the top)
1241 16 bits, and then shifting these into the other half of the
1242 word. We only look for the simplest cases, to do more would cost
1243 too much. Be careful, however, not to generate this when the
1244 alternative would take fewer insns. */
1245 if (val & HOST_UINT (0xffff0000))
1247 temp1 = remainder & HOST_UINT (0xffff0000);
1248 temp2 = remainder & 0x0000ffff;
1250 /* Overlaps outside this range are best done using other methods. */
1251 for (i = 9; i < 24; i++)
1253 if ((((temp2 | (temp2 << i))
1254 & HOST_UINT (0xffffffff)) == remainder)
1255 && !const_ok_for_arm (temp2))
1257 rtx new_src = (subtargets
1258 ? (generate ? gen_reg_rtx (mode) : NULL_RTX)
1260 insns = arm_gen_constant (code, mode, temp2, new_src,
1261 source, subtargets, generate);
1264 emit_insn (gen_rtx_SET
1267 gen_rtx_ASHIFT (mode, source,
1274 /* Don't duplicate cases already considered. */
1275 for (i = 17; i < 24; i++)
1277 if (((temp1 | (temp1 >> i)) == remainder)
1278 && !const_ok_for_arm (temp1))
1280 rtx new_src = (subtargets
1281 ? (generate ? gen_reg_rtx (mode) : NULL_RTX)
1283 insns = arm_gen_constant (code, mode, temp1, new_src,
1284 source, subtargets, generate);
1288 (gen_rtx_SET (VOIDmode, target,
1291 gen_rtx_LSHIFTRT (mode, source,
1302 /* If we have IOR or XOR, and the constant can be loaded in a
1303 single instruction, and we can find a temporary to put it in,
1304 then this can be done in two instructions instead of 3-4. */
1306 /* TARGET can't be NULL if SUBTARGETS is 0 */
1307 || (reload_completed && !reg_mentioned_p (target, source)))
1309 if (const_ok_for_arm (ARM_SIGN_EXTEND (~val)))
1313 rtx sub = subtargets ? gen_reg_rtx (mode) : target;
1315 emit_insn (gen_rtx_SET (VOIDmode, sub, GEN_INT (val)));
1316 emit_insn (gen_rtx_SET (VOIDmode, target,
1317 gen_rtx (code, mode, source, sub)));
1326 if (set_sign_bit_copies > 8
1327 && (val & (-1 << (32 - set_sign_bit_copies))) == val)
1331 rtx sub = subtargets ? gen_reg_rtx (mode) : target;
1332 rtx shift = GEN_INT (set_sign_bit_copies);
1334 emit_insn (gen_rtx_SET (VOIDmode, sub,
1336 gen_rtx_ASHIFT (mode,
1339 emit_insn (gen_rtx_SET (VOIDmode, target,
1341 gen_rtx_LSHIFTRT (mode, sub,
1347 if (set_zero_bit_copies > 8
1348 && (remainder & ((1 << set_zero_bit_copies) - 1)) == remainder)
1352 rtx sub = subtargets ? gen_reg_rtx (mode) : target;
1353 rtx shift = GEN_INT (set_zero_bit_copies);
1355 emit_insn (gen_rtx_SET (VOIDmode, sub,
1357 gen_rtx_LSHIFTRT (mode,
1360 emit_insn (gen_rtx_SET (VOIDmode, target,
1362 gen_rtx_ASHIFT (mode, sub,
1368 if (const_ok_for_arm (temp1 = ARM_SIGN_EXTEND (~val)))
1372 rtx sub = subtargets ? gen_reg_rtx (mode) : target;
1373 emit_insn (gen_rtx_SET (VOIDmode, sub,
1374 gen_rtx_NOT (mode, source)));
1377 sub = gen_reg_rtx (mode);
1378 emit_insn (gen_rtx_SET (VOIDmode, sub,
1379 gen_rtx_AND (mode, source,
1381 emit_insn (gen_rtx_SET (VOIDmode, target,
1382 gen_rtx_NOT (mode, sub)));
1389 /* See if two shifts will do 2 or more insn's worth of work. */
1390 if (clear_sign_bit_copies >= 16 && clear_sign_bit_copies < 24)
1392 HOST_WIDE_INT shift_mask = (((HOST_UINT (0xffffffff))
1393 << (32 - clear_sign_bit_copies))
1394 & HOST_UINT (0xffffffff));
1396 if ((remainder | shift_mask) != HOST_UINT (0xffffffff))
1400 rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
1401 insns = arm_gen_constant (AND, mode, remainder | shift_mask,
1402 new_src, source, subtargets, 1);
1407 rtx targ = subtargets ? NULL_RTX : target;
1408 insns = arm_gen_constant (AND, mode, remainder | shift_mask,
1409 targ, source, subtargets, 0);
1415 rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
1416 rtx shift = GEN_INT (clear_sign_bit_copies);
1418 emit_insn (gen_ashlsi3 (new_src, source, shift));
1419 emit_insn (gen_lshrsi3 (target, new_src, shift));
1425 if (clear_zero_bit_copies >= 16 && clear_zero_bit_copies < 24)
1427 HOST_WIDE_INT shift_mask = (1 << clear_zero_bit_copies) - 1;
1429 if ((remainder | shift_mask) != HOST_UINT (0xffffffff))
1433 rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
1435 insns = arm_gen_constant (AND, mode, remainder | shift_mask,
1436 new_src, source, subtargets, 1);
1441 rtx targ = subtargets ? NULL_RTX : target;
1443 insns = arm_gen_constant (AND, mode, remainder | shift_mask,
1444 targ, source, subtargets, 0);
1450 rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
1451 rtx shift = GEN_INT (clear_zero_bit_copies);
1453 emit_insn (gen_lshrsi3 (new_src, source, shift));
1454 emit_insn (gen_ashlsi3 (target, new_src, shift));
1466 for (i = 0; i < 32; i++)
1467 if (remainder & (1 << i))
1470 if (code == AND || (can_invert && num_bits_set > 16))
1471 remainder = (~remainder) & HOST_UINT (0xffffffff);
1472 else if (code == PLUS && num_bits_set > 16)
1473 remainder = (-remainder) & HOST_UINT (0xffffffff);
1480 /* Now try and find a way of doing the job in either two or three
1482 We start by looking for the largest block of zeros that are aligned on
1483 a 2-bit boundary, we then fill up the temps, wrapping around to the
1484 top of the word when we drop off the bottom.
1485 In the worst case this code should produce no more than four insns. */
1488 int best_consecutive_zeros = 0;
1490 for (i = 0; i < 32; i += 2)
1492 int consecutive_zeros = 0;
1494 if (!(remainder & (3 << i)))
1496 while ((i < 32) && !(remainder & (3 << i)))
1498 consecutive_zeros += 2;
1501 if (consecutive_zeros > best_consecutive_zeros)
1503 best_consecutive_zeros = consecutive_zeros;
1504 best_start = i - consecutive_zeros;
1510 /* So long as it won't require any more insns to do so, it's
1511 desirable to emit a small constant (in bits 0...9) in the last
1512 insn. This way there is more chance that it can be combined with
1513 a later addressing insn to form a pre-indexed load or store
1514 operation. Consider:
1516 *((volatile int *)0xe0000100) = 1;
1517 *((volatile int *)0xe0000110) = 2;
1519 We want this to wind up as:
1523 str rB, [rA, #0x100]
1525 str rB, [rA, #0x110]
1527 rather than having to synthesize both large constants from scratch.
1529 Therefore, we calculate how many insns would be required to emit
1530 the constant starting from `best_start', and also starting from
1531 zero (ie with bit 31 first to be output). If `best_start' doesn't
1532 yield a shorter sequence, we may as well use zero. */
1534 && ((((unsigned HOST_WIDE_INT) 1) << best_start) < remainder)
1535 && (count_insns_for_constant (remainder, 0) <=
1536 count_insns_for_constant (remainder, best_start)))
1539 /* Now start emitting the insns. */
1547 if (remainder & (3 << (i - 2)))
1552 temp1 = remainder & ((0x0ff << end)
1553 | ((i < end) ? (0xff >> (32 - end)) : 0));
1554 remainder &= ~temp1;
1561 emit_insn (gen_rtx_SET (VOIDmode,
1562 new_src = (subtargets
1563 ? gen_reg_rtx (mode)
1566 ? ~temp1 : temp1)));
1567 else if (code == MINUS)
1568 emit_insn (gen_rtx_SET (VOIDmode,
1569 new_src = (subtargets
1570 ? gen_reg_rtx (mode)
1572 gen_rtx (code, mode, GEN_INT (temp1),
1575 emit_insn (gen_rtx_SET (VOIDmode,
1576 new_src = (remainder
1578 ? gen_reg_rtx (mode)
1581 gen_rtx (code, mode, source,
1582 GEN_INT (can_invert ? ~temp1
1594 else if (code == MINUS)
1601 } while (remainder);
1606 /* Canonicalize a comparison so that we are more likely to recognize it.
1607 This can be done for a few constant compares, where we can make the
1608 immediate value easier to load. */
1610 arm_canonicalize_comparison (code, op1)
1614 unsigned HOST_WIDE_INT i = INTVAL (*op1);
1624 if (i != (((HOST_UINT (1)) << (HOST_BITS_PER_WIDE_INT - 1)) - 1)
1625 && (const_ok_for_arm (i + 1) || const_ok_for_arm (-(i + 1))))
1627 *op1 = GEN_INT (i + 1);
1628 return code == GT ? GE : LT;
1634 if (i != ((HOST_UINT (1)) << (HOST_BITS_PER_WIDE_INT - 1))
1635 && (const_ok_for_arm (i - 1) || const_ok_for_arm (-(i - 1))))
1637 *op1 = GEN_INT (i - 1);
1638 return code == GE ? GT : LE;
1644 if (i != ~(HOST_UINT (0))
1645 && (const_ok_for_arm (i + 1) || const_ok_for_arm (-(i + 1))))
1647 *op1 = GEN_INT (i + 1);
1648 return code == GTU ? GEU : LTU;
1655 && (const_ok_for_arm (i - 1) || const_ok_for_arm (-(i - 1))))
1657 *op1 = GEN_INT (i - 1);
1658 return code == GEU ? GTU : LEU;
1669 /* Decide whether a type should be returned in memory (true)
1670 or in a register (false). This is called by the macro
1671 RETURN_IN_MEMORY. */
1673 arm_return_in_memory (type)
1676 if (!AGGREGATE_TYPE_P (type))
1677 /* All simple types are returned in registers. */
1680 /* For the arm-wince targets we choose to be compitable with Microsoft's
1681 ARM and Thumb compilers, which always return aggregates in memory. */
1684 if (int_size_in_bytes (type) > 4)
1685 /* All structures/unions bigger than one word are returned in memory. */
1688 if (TREE_CODE (type) == RECORD_TYPE)
1692 /* For a struct the APCS says that we only return in a register
1693 if the type is 'integer like' and every addressable element
1694 has an offset of zero. For practical purposes this means
1695 that the structure can have at most one non bit-field element
1696 and that this element must be the first one in the structure. */
1698 /* Find the first field, ignoring non FIELD_DECL things which will
1699 have been created by C++. */
1700 for (field = TYPE_FIELDS (type);
1701 field && TREE_CODE (field) != FIELD_DECL;
1702 field = TREE_CHAIN (field))
1706 return 0; /* An empty structure. Allowed by an extension to ANSI C. */
1708 /* Check that the first field is valid for returning in a register. */
1710 /* ... Floats are not allowed */
1711 if (FLOAT_TYPE_P (TREE_TYPE (field)))
1714 /* ... Aggregates that are not themselves valid for returning in
1715 a register are not allowed. */
1716 if (RETURN_IN_MEMORY (TREE_TYPE (field)))
1719 /* Now check the remaining fields, if any. Only bitfields are allowed,
1720 since they are not addressable. */
1721 for (field = TREE_CHAIN (field);
1723 field = TREE_CHAIN (field))
1725 if (TREE_CODE (field) != FIELD_DECL)
1728 if (!DECL_BIT_FIELD_TYPE (field))
1735 if (TREE_CODE (type) == UNION_TYPE)
1739 /* Unions can be returned in registers if every element is
1740 integral, or can be returned in an integer register. */
1741 for (field = TYPE_FIELDS (type);
1743 field = TREE_CHAIN (field))
1745 if (TREE_CODE (field) != FIELD_DECL)
1748 if (FLOAT_TYPE_P (TREE_TYPE (field)))
1751 if (RETURN_IN_MEMORY (TREE_TYPE (field)))
1757 #endif /* not ARM_WINCE */
1759 /* Return all other types in memory. */
1763 /* Initialize a variable CUM of type CUMULATIVE_ARGS
1764 for a call to a function whose data type is FNTYPE.
1765 For a library call, FNTYPE is NULL. */
1767 arm_init_cumulative_args (pcum, fntype, libname, indirect)
1768 CUMULATIVE_ARGS * pcum;
1770 rtx libname ATTRIBUTE_UNUSED;
1771 int indirect ATTRIBUTE_UNUSED;
1773 /* On the ARM, the offset starts at 0. */
1774 pcum->nregs = ((fntype && aggregate_value_p (TREE_TYPE (fntype))) ? 1 : 0);
1776 pcum->call_cookie = CALL_NORMAL;
1778 if (TARGET_LONG_CALLS)
1779 pcum->call_cookie = CALL_LONG;
1781 /* Check for long call/short call attributes. The attributes
1782 override any command line option. */
1785 if (lookup_attribute ("short_call", TYPE_ATTRIBUTES (fntype)))
1786 pcum->call_cookie = CALL_SHORT;
1787 else if (lookup_attribute ("long_call", TYPE_ATTRIBUTES (fntype)))
1788 pcum->call_cookie = CALL_LONG;
1792 /* Determine where to put an argument to a function.
1793 Value is zero to push the argument on the stack,
1794 or a hard register in which to store the argument.
1796 MODE is the argument's machine mode.
1797 TYPE is the data type of the argument (as a tree).
1798 This is null for libcalls where that information may
1800 CUM is a variable of type CUMULATIVE_ARGS which gives info about
1801 the preceding args and about the function being called.
1802 NAMED is nonzero if this argument is a named parameter
1803 (otherwise it is an extra parameter matching an ellipsis). */
1805 arm_function_arg (pcum, mode, type, named)
1806 CUMULATIVE_ARGS * pcum;
1807 enum machine_mode mode;
1808 tree type ATTRIBUTE_UNUSED;
1811 if (mode == VOIDmode)
1812 /* Compute operand 2 of the call insn. */
1813 return GEN_INT (pcum->call_cookie);
1815 if (!named || pcum->nregs >= NUM_ARG_REGS)
1818 return gen_rtx_REG (mode, pcum->nregs);
1821 /* Encode the current state of the #pragma [no_]long_calls. */
1824 OFF, /* No #pramgma [no_]long_calls is in effect. */
1825 LONG, /* #pragma long_calls is in effect. */
1826 SHORT /* #pragma no_long_calls is in effect. */
1829 static arm_pragma_enum arm_pragma_long_calls = OFF;
1832 arm_pr_long_calls (pfile)
1833 cpp_reader *pfile ATTRIBUTE_UNUSED;
1835 arm_pragma_long_calls = LONG;
1839 arm_pr_no_long_calls (pfile)
1840 cpp_reader *pfile ATTRIBUTE_UNUSED;
1842 arm_pragma_long_calls = SHORT;
1846 arm_pr_long_calls_off (pfile)
1847 cpp_reader *pfile ATTRIBUTE_UNUSED;
1849 arm_pragma_long_calls = OFF;
1853 /* Return nonzero if IDENTIFIER with arguments ARGS is a valid machine specific
1854 attribute for TYPE. The attributes in ATTRIBUTES have previously been
1855 assigned to TYPE. */
1857 arm_valid_type_attribute_p (type, attributes, identifier, args)
1859 tree attributes ATTRIBUTE_UNUSED;
1863 if ( TREE_CODE (type) != FUNCTION_TYPE
1864 && TREE_CODE (type) != METHOD_TYPE
1865 && TREE_CODE (type) != FIELD_DECL
1866 && TREE_CODE (type) != TYPE_DECL)
1869 /* Function calls made to this symbol must be done indirectly, because
1870 it may lie outside of the 26 bit addressing range of a normal function
1872 if (is_attribute_p ("long_call", identifier))
1873 return (args == NULL_TREE);
1875 /* Whereas these functions are always known to reside within the 26 bit
1876 addressing range. */
1877 if (is_attribute_p ("short_call", identifier))
1878 return (args == NULL_TREE);
1880 /* Interrupt Service Routines have special prologue and epilogue requirements. */
1881 if (is_attribute_p ("isr", identifier)
1882 || is_attribute_p ("interrupt", identifier))
1883 return arm_isr_value (args);
1888 /* Return 0 if the attributes for two types are incompatible, 1 if they
1889 are compatible, and 2 if they are nearly compatible (which causes a
1890 warning to be generated). */
1892 arm_comp_type_attributes (type1, type2)
1898 /* Check for mismatch of non-default calling convention. */
1899 if (TREE_CODE (type1) != FUNCTION_TYPE)
1902 /* Check for mismatched call attributes. */
1903 l1 = lookup_attribute ("long_call", TYPE_ATTRIBUTES (type1)) != NULL;
1904 l2 = lookup_attribute ("long_call", TYPE_ATTRIBUTES (type2)) != NULL;
1905 s1 = lookup_attribute ("short_call", TYPE_ATTRIBUTES (type1)) != NULL;
1906 s2 = lookup_attribute ("short_call", TYPE_ATTRIBUTES (type2)) != NULL;
1908 /* Only bother to check if an attribute is defined. */
1909 if (l1 | l2 | s1 | s2)
1911 /* If one type has an attribute, the other must have the same attribute. */
1912 if ((l1 != l2) || (s1 != s2))
1915 /* Disallow mixed attributes. */
1916 if ((l1 & s2) || (l2 & s1))
1920 /* Check for mismatched ISR attribute. */
1921 l1 = lookup_attribute ("isr", TYPE_ATTRIBUTES (type1)) != NULL;
1923 l1 = lookup_attribute ("interrupt", TYPE_ATTRIBUTES (type1)) != NULL;
1924 l2 = lookup_attribute ("isr", TYPE_ATTRIBUTES (type2)) != NULL;
1926 l1 = lookup_attribute ("interrupt", TYPE_ATTRIBUTES (type2)) != NULL;
1933 /* Encode long_call or short_call attribute by prefixing
1934 symbol name in DECL with a special character FLAG. */
1936 arm_encode_call_attribute (decl, flag)
1940 const char * str = XSTR (XEXP (DECL_RTL (decl), 0), 0);
1941 int len = strlen (str);
1944 if (TREE_CODE (decl) != FUNCTION_DECL)
1947 /* Do not allow weak functions to be treated as short call. */
1948 if (DECL_WEAK (decl) && flag == SHORT_CALL_FLAG_CHAR)
1951 newstr = alloca (len + 2);
1953 strcpy (newstr + 1, str);
1955 newstr = (char *) ggc_alloc_string (newstr, len + 1);
1956 XSTR (XEXP (DECL_RTL (decl), 0), 0) = newstr;
1959 /* Assigns default attributes to newly defined type. This is used to
1960 set short_call/long_call attributes for function types of
1961 functions defined inside corresponding #pragma scopes. */
1963 arm_set_default_type_attributes (type)
1966 /* Add __attribute__ ((long_call)) to all functions, when
1967 inside #pragma long_calls or __attribute__ ((short_call)),
1968 when inside #pragma no_long_calls. */
1969 if (TREE_CODE (type) == FUNCTION_TYPE || TREE_CODE (type) == METHOD_TYPE)
1971 tree type_attr_list, attr_name;
1972 type_attr_list = TYPE_ATTRIBUTES (type);
1974 if (arm_pragma_long_calls == LONG)
1975 attr_name = get_identifier ("long_call");
1976 else if (arm_pragma_long_calls == SHORT)
1977 attr_name = get_identifier ("short_call");
1981 type_attr_list = tree_cons (attr_name, NULL_TREE, type_attr_list);
1982 TYPE_ATTRIBUTES (type) = type_attr_list;
1986 /* Return 1 if the operand is a SYMBOL_REF for a function known to be
1987 defined within the current compilation unit. If this caanot be
1988 determined, then 0 is returned. */
1990 current_file_function_operand (sym_ref)
1993 /* This is a bit of a fib. A function will have a short call flag
1994 applied to its name if it has the short call attribute, or it has
1995 already been defined within the current compilation unit. */
1996 if (ENCODED_SHORT_CALL_ATTR_P (XSTR (sym_ref, 0)))
1999 /* The current function is always defined within the current compilation
2000 unit. if it s a weak defintion however, then this may not be the real
2001 defintion of the function, and so we have to say no. */
2002 if (sym_ref == XEXP (DECL_RTL (current_function_decl), 0)
2003 && !DECL_WEAK (current_function_decl))
2006 /* We cannot make the determination - default to returning 0. */
2010 /* Return non-zero if a 32 bit "long_call" should be generated for
2011 this call. We generate a long_call if the function:
2013 a. has an __attribute__((long call))
2014 or b. is within the scope of a #pragma long_calls
2015 or c. the -mlong-calls command line switch has been specified
2017 However we do not generate a long call if the function:
2019 d. has an __attribute__ ((short_call))
2020 or e. is inside the scope of a #pragma no_long_calls
2021 or f. has an __attribute__ ((section))
2022 or g. is defined within the current compilation unit.
2024 This function will be called by C fragments contained in the machine
2025 description file. CALL_REF and CALL_COOKIE correspond to the matched
2026 rtl operands. CALL_SYMBOL is used to distinguish between
2027 two different callers of the function. It is set to 1 in the
2028 "call_symbol" and "call_symbol_value" patterns and to 0 in the "call"
2029 and "call_value" patterns. This is because of the difference in the
2030 SYM_REFs passed by these patterns. */
2032 arm_is_longcall_p (sym_ref, call_cookie, call_symbol)
2039 if (GET_CODE (sym_ref) != MEM)
2042 sym_ref = XEXP (sym_ref, 0);
2045 if (GET_CODE (sym_ref) != SYMBOL_REF)
2048 if (call_cookie & CALL_SHORT)
2051 if (TARGET_LONG_CALLS && flag_function_sections)
2054 if (current_file_function_operand (sym_ref))
2057 return (call_cookie & CALL_LONG)
2058 || ENCODED_LONG_CALL_ATTR_P (XSTR (sym_ref, 0))
2059 || TARGET_LONG_CALLS;
2062 /* Return non-zero if it is ok to make a tail-call to DECL. */
2064 arm_function_ok_for_sibcall (decl)
2067 int call_type = TARGET_LONG_CALLS ? CALL_LONG : CALL_NORMAL;
2069 /* Never tailcall something for which we have no decl, or if we
2070 are in Thumb mode. */
2071 if (decl == NULL || TARGET_THUMB)
2074 /* Get the calling method. */
2075 if (lookup_attribute ("short_call", TYPE_ATTRIBUTES (TREE_TYPE (decl))))
2076 call_type = CALL_SHORT;
2077 else if (lookup_attribute ("long_call", TYPE_ATTRIBUTES (TREE_TYPE (decl))))
2078 call_type = CALL_LONG;
2080 /* Cannot tail-call to long calls, since these are out of range of
2081 a branch instruction. However, if not compiling PIC, we know
2082 we can reach the symbol if it is in this compilation unit. */
2083 if (call_type == CALL_LONG && (flag_pic || !TREE_ASM_WRITTEN (decl)))
2086 /* If we are interworking and the function is not declared static
2087 then we can't tail-call it unless we know that it exists in this
2088 compilation unit (since it might be a Thumb routine). */
2089 if (TARGET_INTERWORK && TREE_PUBLIC (decl) && !TREE_ASM_WRITTEN (decl))
2092 /* Never tailcall from an ISR routine - it needs a special exit sequence. */
2093 if (IS_INTERRUPT (arm_current_func_type ()))
2096 /* Everything else is ok. */
2102 legitimate_pic_operand_p (x)
2107 && (GET_CODE (x) == SYMBOL_REF
2108 || (GET_CODE (x) == CONST
2109 && GET_CODE (XEXP (x, 0)) == PLUS
2110 && GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF)))
2117 legitimize_pic_address (orig, mode, reg)
2119 enum machine_mode mode;
2122 if (GET_CODE (orig) == SYMBOL_REF)
2124 rtx pic_ref, address;
2133 reg = gen_reg_rtx (Pmode);
2138 #ifdef AOF_ASSEMBLER
2139 /* The AOF assembler can generate relocations for these directly, and
2140 understands that the PIC register has to be added into the offset. */
2141 insn = emit_insn (gen_pic_load_addr_based (reg, orig));
2144 address = gen_reg_rtx (Pmode);
2149 emit_insn (gen_pic_load_addr_arm (address, orig));
2151 emit_insn (gen_pic_load_addr_thumb (address, orig));
2153 pic_ref = gen_rtx_MEM (Pmode,
2154 gen_rtx_PLUS (Pmode, pic_offset_table_rtx,
2156 RTX_UNCHANGING_P (pic_ref) = 1;
2157 insn = emit_move_insn (reg, pic_ref);
2159 current_function_uses_pic_offset_table = 1;
2160 /* Put a REG_EQUAL note on this insn, so that it can be optimized
2162 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_EQUAL, orig,
2166 else if (GET_CODE (orig) == CONST)
2170 if (GET_CODE (XEXP (orig, 0)) == PLUS
2171 && XEXP (XEXP (orig, 0), 0) == pic_offset_table_rtx)
2179 reg = gen_reg_rtx (Pmode);
2182 if (GET_CODE (XEXP (orig, 0)) == PLUS)
2184 base = legitimize_pic_address (XEXP (XEXP (orig, 0), 0), Pmode, reg);
2185 offset = legitimize_pic_address (XEXP (XEXP (orig, 0), 1), Pmode,
2186 base == reg ? 0 : reg);
2191 if (GET_CODE (offset) == CONST_INT)
2193 /* The base register doesn't really matter, we only want to
2194 test the index for the appropriate mode. */
2195 ARM_GO_IF_LEGITIMATE_INDEX (mode, 0, offset, win);
2197 if (!no_new_pseudos)
2198 offset = force_reg (Pmode, offset);
2203 if (GET_CODE (offset) == CONST_INT)
2204 return plus_constant_for_output (base, INTVAL (offset));
2207 if (GET_MODE_SIZE (mode) > 4
2208 && (GET_MODE_CLASS (mode) == MODE_INT
2209 || TARGET_SOFT_FLOAT))
2211 emit_insn (gen_addsi3 (reg, base, offset));
2215 return gen_rtx_PLUS (Pmode, base, offset);
2217 else if (GET_CODE (orig) == LABEL_REF)
2219 current_function_uses_pic_offset_table = 1;
2223 rtx pic_ref, address = gen_reg_rtx (Pmode);
2226 emit_insn (gen_pic_load_addr_arm (address, orig));
2228 emit_insn (gen_pic_load_addr_thumb (address, orig));
2230 pic_ref = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, address);
2232 emit_move_insn (address, pic_ref);
2240 /* Generate code to load the PIC register. PROLOGUE is true if
2241 called from arm_expand_prologue (in which case we want the
2242 generated insns at the start of the function); false if called
2243 by an exception receiver that needs the PIC register reloaded
2244 (in which case the insns are just dumped at the current location). */
2247 arm_finalize_pic (prologue)
2250 #ifndef AOF_ASSEMBLER
2251 rtx l1, pic_tmp, pic_tmp2, seq, pic_rtx;
2252 rtx global_offset_table;
2254 if (current_function_uses_pic_offset_table == 0 || TARGET_SINGLE_PIC_BASE)
2261 l1 = gen_label_rtx ();
2263 global_offset_table = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
2264 /* On the ARM the PC register contains 'dot + 8' at the time of the
2265 addition, on the Thumb it is 'dot + 4'. */
2266 pic_tmp = plus_constant (gen_rtx_LABEL_REF (Pmode, l1), TARGET_ARM ? 8 : 4);
2268 pic_tmp2 = gen_rtx_CONST (VOIDmode,
2269 gen_rtx_PLUS (Pmode, global_offset_table, pc_rtx));
2271 pic_tmp2 = gen_rtx_CONST (VOIDmode, global_offset_table);
2273 pic_rtx = gen_rtx_CONST (Pmode, gen_rtx_MINUS (Pmode, pic_tmp2, pic_tmp));
2277 emit_insn (gen_pic_load_addr_arm (pic_offset_table_rtx, pic_rtx));
2278 emit_insn (gen_pic_add_dot_plus_eight (pic_offset_table_rtx, l1));
2282 emit_insn (gen_pic_load_addr_thumb (pic_offset_table_rtx, pic_rtx));
2283 emit_insn (gen_pic_add_dot_plus_four (pic_offset_table_rtx, l1));
2286 seq = gen_sequence ();
2289 emit_insn_after (seq, get_insns ());
2293 /* Need to emit this whether or not we obey regdecls,
2294 since setjmp/longjmp can cause life info to screw up. */
2295 emit_insn (gen_rtx_USE (VOIDmode, pic_offset_table_rtx));
2296 #endif /* AOF_ASSEMBLER */
2299 #define REG_OR_SUBREG_REG(X) \
2300 (GET_CODE (X) == REG \
2301 || (GET_CODE (X) == SUBREG && GET_CODE (SUBREG_REG (X)) == REG))
2303 #define REG_OR_SUBREG_RTX(X) \
2304 (GET_CODE (X) == REG ? (X) : SUBREG_REG (X))
2306 #ifndef COSTS_N_INSNS
2307 #define COSTS_N_INSNS(N) ((N) * 4 - 2)
2311 arm_rtx_costs (x, code, outer)
2314 enum rtx_code outer;
2316 enum machine_mode mode = GET_MODE (x);
2317 enum rtx_code subcode;
2333 return COSTS_N_INSNS (1);
2336 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
2339 unsigned HOST_WIDE_INT i = INTVAL (XEXP (x, 1));
2346 return COSTS_N_INSNS (2) + cycles;
2348 return COSTS_N_INSNS (1) + 16;
2351 return (COSTS_N_INSNS (1)
2352 + 4 * ((GET_CODE (SET_SRC (x)) == MEM)
2353 + GET_CODE (SET_DEST (x)) == MEM));
2358 if ((unsigned HOST_WIDE_INT) INTVAL (x) < 256)
2360 if (thumb_shiftable_const (INTVAL (x)))
2361 return COSTS_N_INSNS (2);
2362 return COSTS_N_INSNS (3);
2364 else if (outer == PLUS
2365 && INTVAL (x) < 256 && INTVAL (x) > -256)
2367 else if (outer == COMPARE
2368 && (unsigned HOST_WIDE_INT) INTVAL (x) < 256)
2370 else if (outer == ASHIFT || outer == ASHIFTRT
2371 || outer == LSHIFTRT)
2373 return COSTS_N_INSNS (2);
2379 return COSTS_N_INSNS (3);
2398 /* XXX another guess. */
2399 /* Memory costs quite a lot for the first word, but subsequent words
2400 load at the equivalent of a single insn each. */
2401 return (10 + 4 * ((GET_MODE_SIZE (mode) - 1) / UNITS_PER_WORD)
2402 + (CONSTANT_POOL_ADDRESS_P (x) ? 4 : 0));
2406 if (GET_CODE (XEXP (x, 1)) == PC || GET_CODE (XEXP (x, 2)) == PC)
2411 /* XXX still guessing. */
2412 switch (GET_MODE (XEXP (x, 0)))
2415 return (1 + (mode == DImode ? 4 : 0)
2416 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0));
2419 return (4 + (mode == DImode ? 4 : 0)
2420 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0));
2423 return (1 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0));
2437 fprintf (stderr, "unexpected code for thumb in rtx_costs: %s\n",
2447 /* Memory costs quite a lot for the first word, but subsequent words
2448 load at the equivalent of a single insn each. */
2449 return (10 + 4 * ((GET_MODE_SIZE (mode) - 1) / UNITS_PER_WORD)
2450 + (CONSTANT_POOL_ADDRESS_P (x) ? 4 : 0));
2457 if (mode == SImode && GET_CODE (XEXP (x, 1)) == REG)
2464 case ASHIFT: case LSHIFTRT: case ASHIFTRT:
2466 return (8 + (GET_CODE (XEXP (x, 1)) == CONST_INT ? 0 : 8)
2467 + ((GET_CODE (XEXP (x, 0)) == REG
2468 || (GET_CODE (XEXP (x, 0)) == SUBREG
2469 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == REG))
2471 return (1 + ((GET_CODE (XEXP (x, 0)) == REG
2472 || (GET_CODE (XEXP (x, 0)) == SUBREG
2473 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == REG))
2475 + ((GET_CODE (XEXP (x, 1)) == REG
2476 || (GET_CODE (XEXP (x, 1)) == SUBREG
2477 && GET_CODE (SUBREG_REG (XEXP (x, 1))) == REG)
2478 || (GET_CODE (XEXP (x, 1)) == CONST_INT))
2483 return (4 + (REG_OR_SUBREG_REG (XEXP (x, 1)) ? 0 : 8)
2484 + ((REG_OR_SUBREG_REG (XEXP (x, 0))
2485 || (GET_CODE (XEXP (x, 0)) == CONST_INT
2486 && const_ok_for_arm (INTVAL (XEXP (x, 0)))))
2489 if (GET_MODE_CLASS (mode) == MODE_FLOAT)
2490 return (2 + ((REG_OR_SUBREG_REG (XEXP (x, 1))
2491 || (GET_CODE (XEXP (x, 1)) == CONST_DOUBLE
2492 && const_double_rtx_ok_for_fpu (XEXP (x, 1))))
2494 + ((REG_OR_SUBREG_REG (XEXP (x, 0))
2495 || (GET_CODE (XEXP (x, 0)) == CONST_DOUBLE
2496 && const_double_rtx_ok_for_fpu (XEXP (x, 0))))
2499 if (((GET_CODE (XEXP (x, 0)) == CONST_INT
2500 && const_ok_for_arm (INTVAL (XEXP (x, 0)))
2501 && REG_OR_SUBREG_REG (XEXP (x, 1))))
2502 || (((subcode = GET_CODE (XEXP (x, 1))) == ASHIFT
2503 || subcode == ASHIFTRT || subcode == LSHIFTRT
2504 || subcode == ROTATE || subcode == ROTATERT
2506 && GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT
2507 && ((INTVAL (XEXP (XEXP (x, 1), 1)) &
2508 (INTVAL (XEXP (XEXP (x, 1), 1)) - 1)) == 0)))
2509 && REG_OR_SUBREG_REG (XEXP (XEXP (x, 1), 0))
2510 && (REG_OR_SUBREG_REG (XEXP (XEXP (x, 1), 1))
2511 || GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT)
2512 && REG_OR_SUBREG_REG (XEXP (x, 0))))
2517 if (GET_MODE_CLASS (mode) == MODE_FLOAT)
2518 return (2 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 8)
2519 + ((REG_OR_SUBREG_REG (XEXP (x, 1))
2520 || (GET_CODE (XEXP (x, 1)) == CONST_DOUBLE
2521 && const_double_rtx_ok_for_fpu (XEXP (x, 1))))
2525 case AND: case XOR: case IOR:
2528 /* Normally the frame registers will be spilt into reg+const during
2529 reload, so it is a bad idea to combine them with other instructions,
2530 since then they might not be moved outside of loops. As a compromise
2531 we allow integration with ops that have a constant as their second
2533 if ((REG_OR_SUBREG_REG (XEXP (x, 0))
2534 && ARM_FRAME_RTX (REG_OR_SUBREG_RTX (XEXP (x, 0)))
2535 && GET_CODE (XEXP (x, 1)) != CONST_INT)
2536 || (REG_OR_SUBREG_REG (XEXP (x, 0))
2537 && ARM_FRAME_RTX (REG_OR_SUBREG_RTX (XEXP (x, 0)))))
2541 return (4 + extra_cost + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 8)
2542 + ((REG_OR_SUBREG_REG (XEXP (x, 1))
2543 || (GET_CODE (XEXP (x, 1)) == CONST_INT
2544 && const_ok_for_op (INTVAL (XEXP (x, 1)), code)))
2547 if (REG_OR_SUBREG_REG (XEXP (x, 0)))
2548 return (1 + (GET_CODE (XEXP (x, 1)) == CONST_INT ? 0 : extra_cost)
2549 + ((REG_OR_SUBREG_REG (XEXP (x, 1))
2550 || (GET_CODE (XEXP (x, 1)) == CONST_INT
2551 && const_ok_for_op (INTVAL (XEXP (x, 1)), code)))
2554 else if (REG_OR_SUBREG_REG (XEXP (x, 1)))
2555 return (1 + extra_cost
2556 + ((((subcode = GET_CODE (XEXP (x, 0))) == ASHIFT
2557 || subcode == LSHIFTRT || subcode == ASHIFTRT
2558 || subcode == ROTATE || subcode == ROTATERT
2560 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
2561 && ((INTVAL (XEXP (XEXP (x, 0), 1)) &
2562 (INTVAL (XEXP (XEXP (x, 0), 1)) - 1)) == 0)))
2563 && (REG_OR_SUBREG_REG (XEXP (XEXP (x, 0), 0)))
2564 && ((REG_OR_SUBREG_REG (XEXP (XEXP (x, 0), 1)))
2565 || GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT))
2571 /* There is no point basing this on the tuning, since it is always the
2572 fast variant if it exists at all. */
2573 if (arm_fast_multiply && mode == DImode
2574 && (GET_CODE (XEXP (x, 0)) == GET_CODE (XEXP (x, 1)))
2575 && (GET_CODE (XEXP (x, 0)) == ZERO_EXTEND
2576 || GET_CODE (XEXP (x, 0)) == SIGN_EXTEND))
2579 if (GET_MODE_CLASS (mode) == MODE_FLOAT
2583 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
2585 unsigned HOST_WIDE_INT i = (INTVAL (XEXP (x, 1))
2586 & HOST_UINT (0xffffffff));
2587 int add_cost = const_ok_for_arm (i) ? 4 : 8;
2590 /* Tune as appropriate. */
2591 int booth_unit_size = ((tune_flags & FL_FAST_MULT) ? 8 : 2);
2593 for (j = 0; i && j < 32; j += booth_unit_size)
2595 i >>= booth_unit_size;
2602 return (((tune_flags & FL_FAST_MULT) ? 8 : 30)
2603 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 4)
2604 + (REG_OR_SUBREG_REG (XEXP (x, 1)) ? 0 : 4));
2607 if (arm_fast_multiply && mode == SImode
2608 && GET_CODE (XEXP (x, 0)) == LSHIFTRT
2609 && GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT
2610 && (GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 0))
2611 == GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)))
2612 && (GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == ZERO_EXTEND
2613 || GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == SIGN_EXTEND))
2618 if (GET_MODE_CLASS (mode) == MODE_FLOAT)
2619 return 4 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 6);
2623 return 4 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 4);
2625 return 1 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 4);
2628 if (GET_CODE (XEXP (x, 1)) == PC || GET_CODE (XEXP (x, 2)) == PC)
2636 return 4 + (mode == DImode ? 4 : 0);
2639 if (GET_MODE (XEXP (x, 0)) == QImode)
2640 return (4 + (mode == DImode ? 4 : 0)
2641 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0));
2644 switch (GET_MODE (XEXP (x, 0)))
2647 return (1 + (mode == DImode ? 4 : 0)
2648 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0));
2651 return (4 + (mode == DImode ? 4 : 0)
2652 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0));
2655 return (1 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0));
2663 if (const_ok_for_arm (INTVAL (x)))
2664 return outer == SET ? 2 : -1;
2665 else if (outer == AND
2666 && const_ok_for_arm (~INTVAL (x)))
2668 else if ((outer == COMPARE
2669 || outer == PLUS || outer == MINUS)
2670 && const_ok_for_arm (-INTVAL (x)))
2681 if (const_double_rtx_ok_for_fpu (x))
2682 return outer == SET ? 2 : -1;
2683 else if ((outer == COMPARE || outer == PLUS)
2684 && neg_const_double_rtx_ok_for_fpu (x))
2694 arm_adjust_cost (insn, link, dep, cost)
2702 /* Some true dependencies can have a higher cost depending
2703 on precisely how certain input operands are used. */
2705 && REG_NOTE_KIND (link) == 0
2706 && recog_memoized (insn) < 0
2707 && recog_memoized (dep) < 0)
2709 int shift_opnum = get_attr_shift (insn);
2710 enum attr_type attr_type = get_attr_type (dep);
2712 /* If nonzero, SHIFT_OPNUM contains the operand number of a shifted
2713 operand for INSN. If we have a shifted input operand and the
2714 instruction we depend on is another ALU instruction, then we may
2715 have to account for an additional stall. */
2716 if (shift_opnum != 0 && attr_type == TYPE_NORMAL)
2718 rtx shifted_operand;
2721 /* Get the shifted operand. */
2722 extract_insn (insn);
2723 shifted_operand = recog_data.operand[shift_opnum];
2725 /* Iterate over all the operands in DEP. If we write an operand
2726 that overlaps with SHIFTED_OPERAND, then we have increase the
2727 cost of this dependency. */
2729 preprocess_constraints ();
2730 for (opno = 0; opno < recog_data.n_operands; opno++)
2732 /* We can ignore strict inputs. */
2733 if (recog_data.operand_type[opno] == OP_IN)
2736 if (reg_overlap_mentioned_p (recog_data.operand[opno],
2743 /* XXX This is not strictly true for the FPA. */
2744 if (REG_NOTE_KIND (link) == REG_DEP_ANTI
2745 || REG_NOTE_KIND (link) == REG_DEP_OUTPUT)
2748 /* Call insns don't incur a stall, even if they follow a load. */
2749 if (REG_NOTE_KIND (link) == 0
2750 && GET_CODE (insn) == CALL_INSN)
2753 if ((i_pat = single_set (insn)) != NULL
2754 && GET_CODE (SET_SRC (i_pat)) == MEM
2755 && (d_pat = single_set (dep)) != NULL
2756 && GET_CODE (SET_DEST (d_pat)) == MEM)
2758 /* This is a load after a store, there is no conflict if the load reads
2759 from a cached area. Assume that loads from the stack, and from the
2760 constant pool are cached, and that others will miss. This is a
2763 if (CONSTANT_POOL_ADDRESS_P (XEXP (SET_SRC (i_pat), 0))
2764 || reg_mentioned_p (stack_pointer_rtx, XEXP (SET_SRC (i_pat), 0))
2765 || reg_mentioned_p (frame_pointer_rtx, XEXP (SET_SRC (i_pat), 0))
2766 || reg_mentioned_p (hard_frame_pointer_rtx,
2767 XEXP (SET_SRC (i_pat), 0)))
2774 /* This code has been fixed for cross compilation. */
2776 static int fpa_consts_inited = 0;
2778 static const char * strings_fpa[8] =
2781 "4", "5", "0.5", "10"
2784 static REAL_VALUE_TYPE values_fpa[8];
2792 for (i = 0; i < 8; i++)
2794 r = REAL_VALUE_ATOF (strings_fpa[i], DFmode);
2798 fpa_consts_inited = 1;
2801 /* Return TRUE if rtx X is a valid immediate FPU constant. */
2804 const_double_rtx_ok_for_fpu (x)
2810 if (!fpa_consts_inited)
2813 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
2814 if (REAL_VALUE_MINUS_ZERO (r))
2817 for (i = 0; i < 8; i++)
2818 if (REAL_VALUES_EQUAL (r, values_fpa[i]))
2824 /* Return TRUE if rtx X is a valid immediate FPU constant. */
2827 neg_const_double_rtx_ok_for_fpu (x)
2833 if (!fpa_consts_inited)
2836 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
2837 r = REAL_VALUE_NEGATE (r);
2838 if (REAL_VALUE_MINUS_ZERO (r))
2841 for (i = 0; i < 8; i++)
2842 if (REAL_VALUES_EQUAL (r, values_fpa[i]))
2848 /* Predicates for `match_operand' and `match_operator'. */
2850 /* s_register_operand is the same as register_operand, but it doesn't accept
2853 This function exists because at the time it was put in it led to better
2854 code. SUBREG(MEM) always needs a reload in the places where
2855 s_register_operand is used, and this seemed to lead to excessive
2859 s_register_operand (op, mode)
2861 enum machine_mode mode;
2863 if (GET_MODE (op) != mode && mode != VOIDmode)
2866 if (GET_CODE (op) == SUBREG)
2867 op = SUBREG_REG (op);
2869 /* We don't consider registers whose class is NO_REGS
2870 to be a register operand. */
2871 /* XXX might have to check for lo regs only for thumb ??? */
2872 return (GET_CODE (op) == REG
2873 && (REGNO (op) >= FIRST_PSEUDO_REGISTER
2874 || REGNO_REG_CLASS (REGNO (op)) != NO_REGS));
2877 /* A hard register operand (even before reload. */
2879 arm_hard_register_operand (op, mode)
2881 enum machine_mode mode;
2883 if (GET_MODE (op) != mode && mode != VOIDmode)
2886 return (GET_CODE (op) == REG
2887 && REGNO (op) < FIRST_PSEUDO_REGISTER);
2890 /* Only accept reg, subreg(reg), const_int. */
2893 reg_or_int_operand (op, mode)
2895 enum machine_mode mode;
2897 if (GET_CODE (op) == CONST_INT)
2900 if (GET_MODE (op) != mode && mode != VOIDmode)
2903 if (GET_CODE (op) == SUBREG)
2904 op = SUBREG_REG (op);
2906 /* We don't consider registers whose class is NO_REGS
2907 to be a register operand. */
2908 return (GET_CODE (op) == REG
2909 && (REGNO (op) >= FIRST_PSEUDO_REGISTER
2910 || REGNO_REG_CLASS (REGNO (op)) != NO_REGS));
2913 /* Return 1 if OP is an item in memory, given that we are in reload. */
2916 arm_reload_memory_operand (op, mode)
2918 enum machine_mode mode ATTRIBUTE_UNUSED;
2920 int regno = true_regnum (op);
2922 return (!CONSTANT_P (op)
2924 || (GET_CODE (op) == REG
2925 && REGNO (op) >= FIRST_PSEUDO_REGISTER)));
2928 /* Return 1 if OP is a valid memory address, but not valid for a signed byte
2929 memory access (architecture V4).
2930 MODE is QImode if called when computing contraints, or VOIDmode when
2931 emitting patterns. In this latter case we cannot use memory_operand()
2932 because it will fail on badly formed MEMs, which is precisly what we are
2935 bad_signed_byte_operand (op, mode)
2937 enum machine_mode mode ATTRIBUTE_UNUSED;
2940 if ((mode == QImode && !memory_operand (op, mode)) || GET_CODE (op) != MEM)
2943 if (GET_CODE (op) != MEM)
2948 /* A sum of anything more complex than reg + reg or reg + const is bad. */
2949 if ((GET_CODE (op) == PLUS || GET_CODE (op) == MINUS)
2950 && (!s_register_operand (XEXP (op, 0), VOIDmode)
2951 || (!s_register_operand (XEXP (op, 1), VOIDmode)
2952 && GET_CODE (XEXP (op, 1)) != CONST_INT)))
2955 /* Big constants are also bad. */
2956 if (GET_CODE (op) == PLUS && GET_CODE (XEXP (op, 1)) == CONST_INT
2957 && (INTVAL (XEXP (op, 1)) > 0xff
2958 || -INTVAL (XEXP (op, 1)) > 0xff))
2961 /* Everything else is good, or can will automatically be made so. */
2965 /* Return TRUE for valid operands for the rhs of an ARM instruction. */
2968 arm_rhs_operand (op, mode)
2970 enum machine_mode mode;
2972 return (s_register_operand (op, mode)
2973 || (GET_CODE (op) == CONST_INT && const_ok_for_arm (INTVAL (op))));
2976 /* Return TRUE for valid operands for the rhs of an ARM instruction, or a load.
2980 arm_rhsm_operand (op, mode)
2982 enum machine_mode mode;
2984 return (s_register_operand (op, mode)
2985 || (GET_CODE (op) == CONST_INT && const_ok_for_arm (INTVAL (op)))
2986 || memory_operand (op, mode));
2989 /* Return TRUE for valid operands for the rhs of an ARM instruction, or if a
2990 constant that is valid when negated. */
2993 arm_add_operand (op, mode)
2995 enum machine_mode mode;
2998 return thumb_cmp_operand (op, mode);
3000 return (s_register_operand (op, mode)
3001 || (GET_CODE (op) == CONST_INT
3002 && (const_ok_for_arm (INTVAL (op))
3003 || const_ok_for_arm (-INTVAL (op)))));
3007 arm_not_operand (op, mode)
3009 enum machine_mode mode;
3011 return (s_register_operand (op, mode)
3012 || (GET_CODE (op) == CONST_INT
3013 && (const_ok_for_arm (INTVAL (op))
3014 || const_ok_for_arm (~INTVAL (op)))));
3017 /* Return TRUE if the operand is a memory reference which contains an
3018 offsettable address. */
3020 offsettable_memory_operand (op, mode)
3022 enum machine_mode mode;
3024 if (mode == VOIDmode)
3025 mode = GET_MODE (op);
3027 return (mode == GET_MODE (op)
3028 && GET_CODE (op) == MEM
3029 && offsettable_address_p (reload_completed | reload_in_progress,
3030 mode, XEXP (op, 0)));
3033 /* Return TRUE if the operand is a memory reference which is, or can be
3034 made word aligned by adjusting the offset. */
3036 alignable_memory_operand (op, mode)
3038 enum machine_mode mode;
3042 if (mode == VOIDmode)
3043 mode = GET_MODE (op);
3045 if (mode != GET_MODE (op) || GET_CODE (op) != MEM)
3050 return ((GET_CODE (reg = op) == REG
3051 || (GET_CODE (op) == SUBREG
3052 && GET_CODE (reg = SUBREG_REG (op)) == REG)
3053 || (GET_CODE (op) == PLUS
3054 && GET_CODE (XEXP (op, 1)) == CONST_INT
3055 && (GET_CODE (reg = XEXP (op, 0)) == REG
3056 || (GET_CODE (XEXP (op, 0)) == SUBREG
3057 && GET_CODE (reg = SUBREG_REG (XEXP (op, 0))) == REG))))
3058 && REGNO_POINTER_ALIGN (REGNO (reg)) >= 32);
3061 /* Similar to s_register_operand, but does not allow hard integer
3064 f_register_operand (op, mode)
3066 enum machine_mode mode;
3068 if (GET_MODE (op) != mode && mode != VOIDmode)
3071 if (GET_CODE (op) == SUBREG)
3072 op = SUBREG_REG (op);
3074 /* We don't consider registers whose class is NO_REGS
3075 to be a register operand. */
3076 return (GET_CODE (op) == REG
3077 && (REGNO (op) >= FIRST_PSEUDO_REGISTER
3078 || REGNO_REG_CLASS (REGNO (op)) == FPU_REGS));
3081 /* Return TRUE for valid operands for the rhs of an FPU instruction. */
3084 fpu_rhs_operand (op, mode)
3086 enum machine_mode mode;
3088 if (s_register_operand (op, mode))
3091 if (GET_MODE (op) != mode && mode != VOIDmode)
3094 if (GET_CODE (op) == CONST_DOUBLE)
3095 return const_double_rtx_ok_for_fpu (op);
3101 fpu_add_operand (op, mode)
3103 enum machine_mode mode;
3105 if (s_register_operand (op, mode))
3108 if (GET_MODE (op) != mode && mode != VOIDmode)
3111 if (GET_CODE (op) == CONST_DOUBLE)
3112 return (const_double_rtx_ok_for_fpu (op)
3113 || neg_const_double_rtx_ok_for_fpu (op));
3118 /* Return nonzero if OP is a constant power of two. */
3121 power_of_two_operand (op, mode)
3123 enum machine_mode mode ATTRIBUTE_UNUSED;
3125 if (GET_CODE (op) == CONST_INT)
3127 HOST_WIDE_INT value = INTVAL (op);
3128 return value != 0 && (value & (value - 1)) == 0;
3133 /* Return TRUE for a valid operand of a DImode operation.
3134 Either: REG, SUBREG, CONST_DOUBLE or MEM(DImode_address).
3135 Note that this disallows MEM(REG+REG), but allows
3136 MEM(PRE/POST_INC/DEC(REG)). */
3139 di_operand (op, mode)
3141 enum machine_mode mode;
3143 if (s_register_operand (op, mode))
3146 if (mode != VOIDmode && GET_MODE (op) != VOIDmode && GET_MODE (op) != DImode)
3149 if (GET_CODE (op) == SUBREG)
3150 op = SUBREG_REG (op);
3152 switch (GET_CODE (op))
3159 return memory_address_p (DImode, XEXP (op, 0));
3166 /* Like di_operand, but don't accept constants. */
3168 nonimmediate_di_operand (op, mode)
3170 enum machine_mode mode;
3172 if (s_register_operand (op, mode))
3175 if (mode != VOIDmode && GET_MODE (op) != VOIDmode && GET_MODE (op) != DImode)
3178 if (GET_CODE (op) == SUBREG)
3179 op = SUBREG_REG (op);
3181 if (GET_CODE (op) == MEM)
3182 return memory_address_p (DImode, XEXP (op, 0));
3187 /* Return TRUE for a valid operand of a DFmode operation when -msoft-float.
3188 Either: REG, SUBREG, CONST_DOUBLE or MEM(DImode_address).
3189 Note that this disallows MEM(REG+REG), but allows
3190 MEM(PRE/POST_INC/DEC(REG)). */
3193 soft_df_operand (op, mode)
3195 enum machine_mode mode;
3197 if (s_register_operand (op, mode))
3200 if (mode != VOIDmode && GET_MODE (op) != mode)
3203 if (GET_CODE (op) == SUBREG && CONSTANT_P (SUBREG_REG (op)))
3206 if (GET_CODE (op) == SUBREG)
3207 op = SUBREG_REG (op);
3209 switch (GET_CODE (op))
3215 return memory_address_p (DFmode, XEXP (op, 0));
3222 /* Like soft_df_operand, but don't accept constants. */
3224 nonimmediate_soft_df_operand (op, mode)
3226 enum machine_mode mode;
3228 if (s_register_operand (op, mode))
3231 if (mode != VOIDmode && GET_MODE (op) != mode)
3234 if (GET_CODE (op) == SUBREG)
3235 op = SUBREG_REG (op);
3237 if (GET_CODE (op) == MEM)
3238 return memory_address_p (DFmode, XEXP (op, 0));
3242 /* Return TRUE for valid index operands. */
3244 index_operand (op, mode)
3246 enum machine_mode mode;
3248 return (s_register_operand (op, mode)
3249 || (immediate_operand (op, mode)
3250 && (GET_CODE (op) != CONST_INT
3251 || (INTVAL (op) < 4096 && INTVAL (op) > -4096))));
3254 /* Return TRUE for valid shifts by a constant. This also accepts any
3255 power of two on the (somewhat overly relaxed) assumption that the
3256 shift operator in this case was a mult. */
3259 const_shift_operand (op, mode)
3261 enum machine_mode mode;
3263 return (power_of_two_operand (op, mode)
3264 || (immediate_operand (op, mode)
3265 && (GET_CODE (op) != CONST_INT
3266 || (INTVAL (op) < 32 && INTVAL (op) > 0))));
3269 /* Return TRUE for arithmetic operators which can be combined with a multiply
3273 shiftable_operator (x, mode)
3275 enum machine_mode mode;
3277 if (GET_MODE (x) != mode)
3281 enum rtx_code code = GET_CODE (x);
3283 return (code == PLUS || code == MINUS
3284 || code == IOR || code == XOR || code == AND);
3288 /* Return TRUE for binary logical operators. */
3291 logical_binary_operator (x, mode)
3293 enum machine_mode mode;
3295 if (GET_MODE (x) != mode)
3299 enum rtx_code code = GET_CODE (x);
3301 return (code == IOR || code == XOR || code == AND);
3305 /* Return TRUE for shift operators. */
3308 shift_operator (x, mode)
3310 enum machine_mode mode;
3312 if (GET_MODE (x) != mode)
3316 enum rtx_code code = GET_CODE (x);
3319 return power_of_two_operand (XEXP (x, 1), mode);
3321 return (code == ASHIFT || code == ASHIFTRT || code == LSHIFTRT
3322 || code == ROTATERT);
3326 /* Return TRUE if x is EQ or NE. */
3328 equality_operator (x, mode)
3330 enum machine_mode mode ATTRIBUTE_UNUSED;
3332 return GET_CODE (x) == EQ || GET_CODE (x) == NE;
3335 /* Return TRUE if x is a comparison operator other than LTGT or UNEQ. */
3337 arm_comparison_operator (x, mode)
3339 enum machine_mode mode;
3341 return (comparison_operator (x, mode)
3342 && GET_CODE (x) != LTGT
3343 && GET_CODE (x) != UNEQ);
3346 /* Return TRUE for SMIN SMAX UMIN UMAX operators. */
3348 minmax_operator (x, mode)
3350 enum machine_mode mode;
3352 enum rtx_code code = GET_CODE (x);
3354 if (GET_MODE (x) != mode)
3357 return code == SMIN || code == SMAX || code == UMIN || code == UMAX;
3360 /* Return TRUE if this is the condition code register, if we aren't given
3361 a mode, accept any class CCmode register. */
3363 cc_register (x, mode)
3365 enum machine_mode mode;
3367 if (mode == VOIDmode)
3369 mode = GET_MODE (x);
3371 if (GET_MODE_CLASS (mode) != MODE_CC)
3375 if ( GET_MODE (x) == mode
3376 && GET_CODE (x) == REG
3377 && REGNO (x) == CC_REGNUM)
3383 /* Return TRUE if this is the condition code register, if we aren't given
3384 a mode, accept any class CCmode register which indicates a dominance
3387 dominant_cc_register (x, mode)
3389 enum machine_mode mode;
3391 if (mode == VOIDmode)
3393 mode = GET_MODE (x);
3395 if (GET_MODE_CLASS (mode) != MODE_CC)
3399 if ( mode != CC_DNEmode && mode != CC_DEQmode
3400 && mode != CC_DLEmode && mode != CC_DLTmode
3401 && mode != CC_DGEmode && mode != CC_DGTmode
3402 && mode != CC_DLEUmode && mode != CC_DLTUmode
3403 && mode != CC_DGEUmode && mode != CC_DGTUmode)
3406 return cc_register (x, mode);
3409 /* Return TRUE if X references a SYMBOL_REF. */
3411 symbol_mentioned_p (x)
3414 register const char * fmt;
3417 if (GET_CODE (x) == SYMBOL_REF)
3420 fmt = GET_RTX_FORMAT (GET_CODE (x));
3422 for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
3428 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
3429 if (symbol_mentioned_p (XVECEXP (x, i, j)))
3432 else if (fmt[i] == 'e' && symbol_mentioned_p (XEXP (x, i)))
3439 /* Return TRUE if X references a LABEL_REF. */
3441 label_mentioned_p (x)
3444 register const char * fmt;
3447 if (GET_CODE (x) == LABEL_REF)
3450 fmt = GET_RTX_FORMAT (GET_CODE (x));
3451 for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
3457 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
3458 if (label_mentioned_p (XVECEXP (x, i, j)))
3461 else if (fmt[i] == 'e' && label_mentioned_p (XEXP (x, i)))
3472 enum rtx_code code = GET_CODE (x);
3476 else if (code == SMIN)
3478 else if (code == UMIN)
3480 else if (code == UMAX)
3486 /* Return 1 if memory locations are adjacent. */
3488 adjacent_mem_locations (a, b)
3491 int val0 = 0, val1 = 0;
3494 if ((GET_CODE (XEXP (a, 0)) == REG
3495 || (GET_CODE (XEXP (a, 0)) == PLUS
3496 && GET_CODE (XEXP (XEXP (a, 0), 1)) == CONST_INT))
3497 && (GET_CODE (XEXP (b, 0)) == REG
3498 || (GET_CODE (XEXP (b, 0)) == PLUS
3499 && GET_CODE (XEXP (XEXP (b, 0), 1)) == CONST_INT)))
3501 if (GET_CODE (XEXP (a, 0)) == PLUS)
3503 reg0 = REGNO (XEXP (XEXP (a, 0), 0));
3504 val0 = INTVAL (XEXP (XEXP (a, 0), 1));
3507 reg0 = REGNO (XEXP (a, 0));
3508 if (GET_CODE (XEXP (b, 0)) == PLUS)
3510 reg1 = REGNO (XEXP (XEXP (b, 0), 0));
3511 val1 = INTVAL (XEXP (XEXP (b, 0), 1));
3514 reg1 = REGNO (XEXP (b, 0));
3515 return (reg0 == reg1) && ((val1 - val0) == 4 || (val0 - val1) == 4);
3520 /* Return 1 if OP is a load multiple operation. It is known to be
3521 parallel and the first section will be tested. */
3523 load_multiple_operation (op, mode)
3525 enum machine_mode mode ATTRIBUTE_UNUSED;
3527 HOST_WIDE_INT count = XVECLEN (op, 0);
3530 HOST_WIDE_INT i = 1, base = 0;
3534 || GET_CODE (XVECEXP (op, 0, 0)) != SET)
3537 /* Check to see if this might be a write-back. */
3538 if (GET_CODE (SET_SRC (elt = XVECEXP (op, 0, 0))) == PLUS)
3543 /* Now check it more carefully. */
3544 if (GET_CODE (SET_DEST (elt)) != REG
3545 || GET_CODE (XEXP (SET_SRC (elt), 0)) != REG
3546 || REGNO (XEXP (SET_SRC (elt), 0)) != REGNO (SET_DEST (elt))
3547 || GET_CODE (XEXP (SET_SRC (elt), 1)) != CONST_INT
3548 || INTVAL (XEXP (SET_SRC (elt), 1)) != (count - 1) * 4)
3552 /* Perform a quick check so we don't blow up below. */
3554 || GET_CODE (XVECEXP (op, 0, i - 1)) != SET
3555 || GET_CODE (SET_DEST (XVECEXP (op, 0, i - 1))) != REG
3556 || GET_CODE (SET_SRC (XVECEXP (op, 0, i - 1))) != MEM)
3559 dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, i - 1)));
3560 src_addr = XEXP (SET_SRC (XVECEXP (op, 0, i - 1)), 0);
3562 for (; i < count; i++)
3564 elt = XVECEXP (op, 0, i);
3566 if (GET_CODE (elt) != SET
3567 || GET_CODE (SET_DEST (elt)) != REG
3568 || GET_MODE (SET_DEST (elt)) != SImode
3569 || REGNO (SET_DEST (elt)) != (unsigned int)(dest_regno + i - base)
3570 || GET_CODE (SET_SRC (elt)) != MEM
3571 || GET_MODE (SET_SRC (elt)) != SImode
3572 || GET_CODE (XEXP (SET_SRC (elt), 0)) != PLUS
3573 || !rtx_equal_p (XEXP (XEXP (SET_SRC (elt), 0), 0), src_addr)
3574 || GET_CODE (XEXP (XEXP (SET_SRC (elt), 0), 1)) != CONST_INT
3575 || INTVAL (XEXP (XEXP (SET_SRC (elt), 0), 1)) != (i - base) * 4)
3582 /* Return 1 if OP is a store multiple operation. It is known to be
3583 parallel and the first section will be tested. */
3585 store_multiple_operation (op, mode)
3587 enum machine_mode mode ATTRIBUTE_UNUSED;
3589 HOST_WIDE_INT count = XVECLEN (op, 0);
3592 HOST_WIDE_INT i = 1, base = 0;
3596 || GET_CODE (XVECEXP (op, 0, 0)) != SET)
3599 /* Check to see if this might be a write-back. */
3600 if (GET_CODE (SET_SRC (elt = XVECEXP (op, 0, 0))) == PLUS)
3605 /* Now check it more carefully. */
3606 if (GET_CODE (SET_DEST (elt)) != REG
3607 || GET_CODE (XEXP (SET_SRC (elt), 0)) != REG
3608 || REGNO (XEXP (SET_SRC (elt), 0)) != REGNO (SET_DEST (elt))
3609 || GET_CODE (XEXP (SET_SRC (elt), 1)) != CONST_INT
3610 || INTVAL (XEXP (SET_SRC (elt), 1)) != (count - 1) * 4)
3614 /* Perform a quick check so we don't blow up below. */
3616 || GET_CODE (XVECEXP (op, 0, i - 1)) != SET
3617 || GET_CODE (SET_DEST (XVECEXP (op, 0, i - 1))) != MEM
3618 || GET_CODE (SET_SRC (XVECEXP (op, 0, i - 1))) != REG)
3621 src_regno = REGNO (SET_SRC (XVECEXP (op, 0, i - 1)));
3622 dest_addr = XEXP (SET_DEST (XVECEXP (op, 0, i - 1)), 0);
3624 for (; i < count; i++)
3626 elt = XVECEXP (op, 0, i);
3628 if (GET_CODE (elt) != SET
3629 || GET_CODE (SET_SRC (elt)) != REG
3630 || GET_MODE (SET_SRC (elt)) != SImode
3631 || REGNO (SET_SRC (elt)) != (unsigned int)(src_regno + i - base)
3632 || GET_CODE (SET_DEST (elt)) != MEM
3633 || GET_MODE (SET_DEST (elt)) != SImode
3634 || GET_CODE (XEXP (SET_DEST (elt), 0)) != PLUS
3635 || !rtx_equal_p (XEXP (XEXP (SET_DEST (elt), 0), 0), dest_addr)
3636 || GET_CODE (XEXP (XEXP (SET_DEST (elt), 0), 1)) != CONST_INT
3637 || INTVAL (XEXP (XEXP (SET_DEST (elt), 0), 1)) != (i - base) * 4)
3645 load_multiple_sequence (operands, nops, regs, base, load_offset)
3650 HOST_WIDE_INT * load_offset;
3652 int unsorted_regs[4];
3653 HOST_WIDE_INT unsorted_offsets[4];
3658 /* Can only handle 2, 3, or 4 insns at present, though could be easily
3659 extended if required. */
3660 if (nops < 2 || nops > 4)
3663 /* Loop over the operands and check that the memory references are
3664 suitable (ie immediate offsets from the same base register). At
3665 the same time, extract the target register, and the memory
3667 for (i = 0; i < nops; i++)
3672 /* Convert a subreg of a mem into the mem itself. */
3673 if (GET_CODE (operands[nops + i]) == SUBREG)
3674 operands[nops + i] = alter_subreg (operands[nops + i]);
3676 if (GET_CODE (operands[nops + i]) != MEM)
3679 /* Don't reorder volatile memory references; it doesn't seem worth
3680 looking for the case where the order is ok anyway. */
3681 if (MEM_VOLATILE_P (operands[nops + i]))
3684 offset = const0_rtx;
3686 if ((GET_CODE (reg = XEXP (operands[nops + i], 0)) == REG
3687 || (GET_CODE (reg) == SUBREG
3688 && GET_CODE (reg = SUBREG_REG (reg)) == REG))
3689 || (GET_CODE (XEXP (operands[nops + i], 0)) == PLUS
3690 && ((GET_CODE (reg = XEXP (XEXP (operands[nops + i], 0), 0))
3692 || (GET_CODE (reg) == SUBREG
3693 && GET_CODE (reg = SUBREG_REG (reg)) == REG))
3694 && (GET_CODE (offset = XEXP (XEXP (operands[nops + i], 0), 1))
3699 base_reg = REGNO (reg);
3700 unsorted_regs[0] = (GET_CODE (operands[i]) == REG
3701 ? REGNO (operands[i])
3702 : REGNO (SUBREG_REG (operands[i])));
3707 if (base_reg != (int) REGNO (reg))
3708 /* Not addressed from the same base register. */
3711 unsorted_regs[i] = (GET_CODE (operands[i]) == REG
3712 ? REGNO (operands[i])
3713 : REGNO (SUBREG_REG (operands[i])));
3714 if (unsorted_regs[i] < unsorted_regs[order[0]])
3718 /* If it isn't an integer register, or if it overwrites the
3719 base register but isn't the last insn in the list, then
3720 we can't do this. */
3721 if (unsorted_regs[i] < 0 || unsorted_regs[i] > 14
3722 || (i != nops - 1 && unsorted_regs[i] == base_reg))
3725 unsorted_offsets[i] = INTVAL (offset);
3728 /* Not a suitable memory address. */
3732 /* All the useful information has now been extracted from the
3733 operands into unsorted_regs and unsorted_offsets; additionally,
3734 order[0] has been set to the lowest numbered register in the
3735 list. Sort the registers into order, and check that the memory
3736 offsets are ascending and adjacent. */
3738 for (i = 1; i < nops; i++)
3742 order[i] = order[i - 1];
3743 for (j = 0; j < nops; j++)
3744 if (unsorted_regs[j] > unsorted_regs[order[i - 1]]
3745 && (order[i] == order[i - 1]
3746 || unsorted_regs[j] < unsorted_regs[order[i]]))
3749 /* Have we found a suitable register? if not, one must be used more
3751 if (order[i] == order[i - 1])
3754 /* Is the memory address adjacent and ascending? */
3755 if (unsorted_offsets[order[i]] != unsorted_offsets[order[i - 1]] + 4)
3763 for (i = 0; i < nops; i++)
3764 regs[i] = unsorted_regs[order[i]];
3766 *load_offset = unsorted_offsets[order[0]];
3769 if (unsorted_offsets[order[0]] == 0)
3770 return 1; /* ldmia */
3772 if (unsorted_offsets[order[0]] == 4)
3773 return 2; /* ldmib */
3775 if (unsorted_offsets[order[nops - 1]] == 0)
3776 return 3; /* ldmda */
3778 if (unsorted_offsets[order[nops - 1]] == -4)
3779 return 4; /* ldmdb */
3781 /* For ARM8,9 & StrongARM, 2 ldr instructions are faster than an ldm
3782 if the offset isn't small enough. The reason 2 ldrs are faster
3783 is because these ARMs are able to do more than one cache access
3784 in a single cycle. The ARM9 and StrongARM have Harvard caches,
3785 whilst the ARM8 has a double bandwidth cache. This means that
3786 these cores can do both an instruction fetch and a data fetch in
3787 a single cycle, so the trick of calculating the address into a
3788 scratch register (one of the result regs) and then doing a load
3789 multiple actually becomes slower (and no smaller in code size).
3790 That is the transformation
3792 ldr rd1, [rbase + offset]
3793 ldr rd2, [rbase + offset + 4]
3797 add rd1, rbase, offset
3798 ldmia rd1, {rd1, rd2}
3800 produces worse code -- '3 cycles + any stalls on rd2' instead of
3801 '2 cycles + any stalls on rd2'. On ARMs with only one cache
3802 access per cycle, the first sequence could never complete in less
3803 than 6 cycles, whereas the ldm sequence would only take 5 and
3804 would make better use of sequential accesses if not hitting the
3807 We cheat here and test 'arm_ld_sched' which we currently know to
3808 only be true for the ARM8, ARM9 and StrongARM. If this ever
3809 changes, then the test below needs to be reworked. */
3810 if (nops == 2 && arm_ld_sched)
3813 /* Can't do it without setting up the offset, only do this if it takes
3814 no more than one insn. */
3815 return (const_ok_for_arm (unsorted_offsets[order[0]])
3816 || const_ok_for_arm (-unsorted_offsets[order[0]])) ? 5 : 0;
3820 emit_ldm_seq (operands, nops)
3826 HOST_WIDE_INT offset;
3830 switch (load_multiple_sequence (operands, nops, regs, &base_reg, &offset))
3833 strcpy (buf, "ldm%?ia\t");
3837 strcpy (buf, "ldm%?ib\t");
3841 strcpy (buf, "ldm%?da\t");
3845 strcpy (buf, "ldm%?db\t");
3850 sprintf (buf, "add%%?\t%s%s, %s%s, #%ld", REGISTER_PREFIX,
3851 reg_names[regs[0]], REGISTER_PREFIX, reg_names[base_reg],
3854 sprintf (buf, "sub%%?\t%s%s, %s%s, #%ld", REGISTER_PREFIX,
3855 reg_names[regs[0]], REGISTER_PREFIX, reg_names[base_reg],
3857 output_asm_insn (buf, operands);
3859 strcpy (buf, "ldm%?ia\t");
3866 sprintf (buf + strlen (buf), "%s%s, {%s%s", REGISTER_PREFIX,
3867 reg_names[base_reg], REGISTER_PREFIX, reg_names[regs[0]]);
3869 for (i = 1; i < nops; i++)
3870 sprintf (buf + strlen (buf), ", %s%s", REGISTER_PREFIX,
3871 reg_names[regs[i]]);
3873 strcat (buf, "}\t%@ phole ldm");
3875 output_asm_insn (buf, operands);
3880 store_multiple_sequence (operands, nops, regs, base, load_offset)
3885 HOST_WIDE_INT * load_offset;
3887 int unsorted_regs[4];
3888 HOST_WIDE_INT unsorted_offsets[4];
3893 /* Can only handle 2, 3, or 4 insns at present, though could be easily
3894 extended if required. */
3895 if (nops < 2 || nops > 4)
3898 /* Loop over the operands and check that the memory references are
3899 suitable (ie immediate offsets from the same base register). At
3900 the same time, extract the target register, and the memory
3902 for (i = 0; i < nops; i++)
3907 /* Convert a subreg of a mem into the mem itself. */
3908 if (GET_CODE (operands[nops + i]) == SUBREG)
3909 operands[nops + i] = alter_subreg (operands[nops + i]);
3911 if (GET_CODE (operands[nops + i]) != MEM)
3914 /* Don't reorder volatile memory references; it doesn't seem worth
3915 looking for the case where the order is ok anyway. */
3916 if (MEM_VOLATILE_P (operands[nops + i]))
3919 offset = const0_rtx;
3921 if ((GET_CODE (reg = XEXP (operands[nops + i], 0)) == REG
3922 || (GET_CODE (reg) == SUBREG
3923 && GET_CODE (reg = SUBREG_REG (reg)) == REG))
3924 || (GET_CODE (XEXP (operands[nops + i], 0)) == PLUS
3925 && ((GET_CODE (reg = XEXP (XEXP (operands[nops + i], 0), 0))
3927 || (GET_CODE (reg) == SUBREG
3928 && GET_CODE (reg = SUBREG_REG (reg)) == REG))
3929 && (GET_CODE (offset = XEXP (XEXP (operands[nops + i], 0), 1))
3934 base_reg = REGNO (reg);
3935 unsorted_regs[0] = (GET_CODE (operands[i]) == REG
3936 ? REGNO (operands[i])
3937 : REGNO (SUBREG_REG (operands[i])));
3942 if (base_reg != (int) REGNO (reg))
3943 /* Not addressed from the same base register. */
3946 unsorted_regs[i] = (GET_CODE (operands[i]) == REG
3947 ? REGNO (operands[i])
3948 : REGNO (SUBREG_REG (operands[i])));
3949 if (unsorted_regs[i] < unsorted_regs[order[0]])
3953 /* If it isn't an integer register, then we can't do this. */
3954 if (unsorted_regs[i] < 0 || unsorted_regs[i] > 14)
3957 unsorted_offsets[i] = INTVAL (offset);
3960 /* Not a suitable memory address. */
3964 /* All the useful information has now been extracted from the
3965 operands into unsorted_regs and unsorted_offsets; additionally,
3966 order[0] has been set to the lowest numbered register in the
3967 list. Sort the registers into order, and check that the memory
3968 offsets are ascending and adjacent. */
3970 for (i = 1; i < nops; i++)
3974 order[i] = order[i - 1];
3975 for (j = 0; j < nops; j++)
3976 if (unsorted_regs[j] > unsorted_regs[order[i - 1]]
3977 && (order[i] == order[i - 1]
3978 || unsorted_regs[j] < unsorted_regs[order[i]]))
3981 /* Have we found a suitable register? if not, one must be used more
3983 if (order[i] == order[i - 1])
3986 /* Is the memory address adjacent and ascending? */
3987 if (unsorted_offsets[order[i]] != unsorted_offsets[order[i - 1]] + 4)
3995 for (i = 0; i < nops; i++)
3996 regs[i] = unsorted_regs[order[i]];
3998 *load_offset = unsorted_offsets[order[0]];
4001 if (unsorted_offsets[order[0]] == 0)
4002 return 1; /* stmia */
4004 if (unsorted_offsets[order[0]] == 4)
4005 return 2; /* stmib */
4007 if (unsorted_offsets[order[nops - 1]] == 0)
4008 return 3; /* stmda */
4010 if (unsorted_offsets[order[nops - 1]] == -4)
4011 return 4; /* stmdb */
4017 emit_stm_seq (operands, nops)
4023 HOST_WIDE_INT offset;
4027 switch (store_multiple_sequence (operands, nops, regs, &base_reg, &offset))
4030 strcpy (buf, "stm%?ia\t");
4034 strcpy (buf, "stm%?ib\t");
4038 strcpy (buf, "stm%?da\t");
4042 strcpy (buf, "stm%?db\t");
4049 sprintf (buf + strlen (buf), "%s%s, {%s%s", REGISTER_PREFIX,
4050 reg_names[base_reg], REGISTER_PREFIX, reg_names[regs[0]]);
4052 for (i = 1; i < nops; i++)
4053 sprintf (buf + strlen (buf), ", %s%s", REGISTER_PREFIX,
4054 reg_names[regs[i]]);
4056 strcat (buf, "}\t%@ phole stm");
4058 output_asm_insn (buf, operands);
4063 multi_register_push (op, mode)
4065 enum machine_mode mode ATTRIBUTE_UNUSED;
4067 if (GET_CODE (op) != PARALLEL
4068 || (GET_CODE (XVECEXP (op, 0, 0)) != SET)
4069 || (GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != UNSPEC)
4070 || (XINT (SET_SRC (XVECEXP (op, 0, 0)), 1) != UNSPEC_PUSH_MULT))
4076 /* Routines for use with attributes. */
4078 /* Return nonzero if ATTR is a valid attribute for DECL.
4079 ATTRIBUTES are any existing attributes and ARGS are
4080 the arguments supplied with ATTR.
4082 Supported attributes:
4085 don't output any prologue or epilogue code, the user is assumed
4086 to do the right thing.
4089 Interrupt Service Routine.
4092 Always assume that this function will be entered in ARM mode,
4093 not Thumb mode, and that the caller wishes to be returned to in
4096 arm_valid_machine_decl_attribute (decl, attr, args)
4101 /* The interrupt attribute can take args, so check for it before
4102 rejecting other attributes on the grounds that they did have args. */
4103 if (is_attribute_p ("isr", attr)
4104 || is_attribute_p ("interrupt", attr))
4105 return TREE_CODE (decl) == FUNCTION_DECL;
4107 if (args != NULL_TREE)
4110 if (is_attribute_p ("naked", attr))
4111 return TREE_CODE (decl) == FUNCTION_DECL;
4114 if (is_attribute_p ("interfacearm", attr))
4115 return TREE_CODE (decl) == FUNCTION_DECL;
4121 /* Routines for use in generating RTL. */
4123 arm_gen_load_multiple (base_regno, count, from, up, write_back, unchanging_p,
4124 in_struct_p, scalar_p)
4136 int sign = up ? 1 : -1;
4139 /* XScale has load-store double instructions, but they have stricter
4140 alignment requirements than load-store multiple, so we can not
4143 For XScale ldm requires 2 + NREGS cycles to complete and blocks
4144 the pipeline until completion.
4152 An ldr instruction takes 1-3 cycles, but does not block the
4161 Best case ldr will always win. However, the more ldr instructions
4162 we issue, the less likely we are to be able to schedule them well.
4163 Using ldr instructions also increases code size.
4165 As a compromise, we use ldr for counts of 1 or 2 regs, and ldm
4166 for counts of 3 or 4 regs. */
4167 if (arm_is_xscale && count <= 2 && ! optimize_size)
4173 for (i = 0; i < count; i++)
4175 mem = gen_rtx_MEM (SImode, plus_constant (from, i * 4 * sign));
4176 RTX_UNCHANGING_P (mem) = unchanging_p;
4177 MEM_IN_STRUCT_P (mem) = in_struct_p;
4178 MEM_SCALAR_P (mem) = scalar_p;
4179 emit_move_insn (gen_rtx_REG (SImode, base_regno + i), mem);
4183 emit_move_insn (from, plus_constant (from, count * 4 * sign));
4185 seq = gen_sequence ();
4191 result = gen_rtx_PARALLEL (VOIDmode,
4192 rtvec_alloc (count + (write_back ? 1 : 0)));
4195 XVECEXP (result, 0, 0)
4196 = gen_rtx_SET (GET_MODE (from), from,
4197 plus_constant (from, count * 4 * sign));
4202 for (j = 0; i < count; i++, j++)
4204 mem = gen_rtx_MEM (SImode, plus_constant (from, j * 4 * sign));
4205 RTX_UNCHANGING_P (mem) = unchanging_p;
4206 MEM_IN_STRUCT_P (mem) = in_struct_p;
4207 MEM_SCALAR_P (mem) = scalar_p;
4208 XVECEXP (result, 0, i)
4209 = gen_rtx_SET (VOIDmode, gen_rtx_REG (SImode, base_regno + j), mem);
4216 arm_gen_store_multiple (base_regno, count, to, up, write_back, unchanging_p,
4217 in_struct_p, scalar_p)
4229 int sign = up ? 1 : -1;
4232 /* See arm_gen_load_multiple for discussion of
4233 the pros/cons of ldm/stm usage for XScale. */
4234 if (arm_is_xscale && count <= 2 && ! optimize_size)
4240 for (i = 0; i < count; i++)
4242 mem = gen_rtx_MEM (SImode, plus_constant (to, i * 4 * sign));
4243 RTX_UNCHANGING_P (mem) = unchanging_p;
4244 MEM_IN_STRUCT_P (mem) = in_struct_p;
4245 MEM_SCALAR_P (mem) = scalar_p;
4246 emit_move_insn (mem, gen_rtx_REG (SImode, base_regno + i));
4250 emit_move_insn (to, plus_constant (to, count * 4 * sign));
4252 seq = gen_sequence ();
4258 result = gen_rtx_PARALLEL (VOIDmode,
4259 rtvec_alloc (count + (write_back ? 1 : 0)));
4262 XVECEXP (result, 0, 0)
4263 = gen_rtx_SET (GET_MODE (to), to,
4264 plus_constant (to, count * 4 * sign));
4269 for (j = 0; i < count; i++, j++)
4271 mem = gen_rtx_MEM (SImode, plus_constant (to, j * 4 * sign));
4272 RTX_UNCHANGING_P (mem) = unchanging_p;
4273 MEM_IN_STRUCT_P (mem) = in_struct_p;
4274 MEM_SCALAR_P (mem) = scalar_p;
4276 XVECEXP (result, 0, i)
4277 = gen_rtx_SET (VOIDmode, mem, gen_rtx_REG (SImode, base_regno + j));
4284 arm_gen_movstrqi (operands)
4287 HOST_WIDE_INT in_words_to_go, out_words_to_go, last_bytes;
4290 rtx st_src, st_dst, fin_src, fin_dst;
4291 rtx part_bytes_reg = NULL;
4293 int dst_unchanging_p, dst_in_struct_p, src_unchanging_p, src_in_struct_p;
4294 int dst_scalar_p, src_scalar_p;
4296 if (GET_CODE (operands[2]) != CONST_INT
4297 || GET_CODE (operands[3]) != CONST_INT
4298 || INTVAL (operands[2]) > 64
4299 || INTVAL (operands[3]) & 3)
4302 st_dst = XEXP (operands[0], 0);
4303 st_src = XEXP (operands[1], 0);
4305 dst_unchanging_p = RTX_UNCHANGING_P (operands[0]);
4306 dst_in_struct_p = MEM_IN_STRUCT_P (operands[0]);
4307 dst_scalar_p = MEM_SCALAR_P (operands[0]);
4308 src_unchanging_p = RTX_UNCHANGING_P (operands[1]);
4309 src_in_struct_p = MEM_IN_STRUCT_P (operands[1]);
4310 src_scalar_p = MEM_SCALAR_P (operands[1]);
4312 fin_dst = dst = copy_to_mode_reg (SImode, st_dst);
4313 fin_src = src = copy_to_mode_reg (SImode, st_src);
4315 in_words_to_go = NUM_INTS (INTVAL (operands[2]));
4316 out_words_to_go = INTVAL (operands[2]) / 4;
4317 last_bytes = INTVAL (operands[2]) & 3;
4319 if (out_words_to_go != in_words_to_go && ((in_words_to_go - 1) & 3) != 0)
4320 part_bytes_reg = gen_rtx_REG (SImode, (in_words_to_go - 1) & 3);
4322 for (i = 0; in_words_to_go >= 2; i+=4)
4324 if (in_words_to_go > 4)
4325 emit_insn (arm_gen_load_multiple (0, 4, src, TRUE, TRUE,
4330 emit_insn (arm_gen_load_multiple (0, in_words_to_go, src, TRUE,
4331 FALSE, src_unchanging_p,
4332 src_in_struct_p, src_scalar_p));
4334 if (out_words_to_go)
4336 if (out_words_to_go > 4)
4337 emit_insn (arm_gen_store_multiple (0, 4, dst, TRUE, TRUE,
4341 else if (out_words_to_go != 1)
4342 emit_insn (arm_gen_store_multiple (0, out_words_to_go,
4351 mem = gen_rtx_MEM (SImode, dst);
4352 RTX_UNCHANGING_P (mem) = dst_unchanging_p;
4353 MEM_IN_STRUCT_P (mem) = dst_in_struct_p;
4354 MEM_SCALAR_P (mem) = dst_scalar_p;
4355 emit_move_insn (mem, gen_rtx_REG (SImode, 0));
4356 if (last_bytes != 0)
4357 emit_insn (gen_addsi3 (dst, dst, GEN_INT (4)));
4361 in_words_to_go -= in_words_to_go < 4 ? in_words_to_go : 4;
4362 out_words_to_go -= out_words_to_go < 4 ? out_words_to_go : 4;
4365 /* OUT_WORDS_TO_GO will be zero here if there are byte stores to do. */
4366 if (out_words_to_go)
4370 mem = gen_rtx_MEM (SImode, src);
4371 RTX_UNCHANGING_P (mem) = src_unchanging_p;
4372 MEM_IN_STRUCT_P (mem) = src_in_struct_p;
4373 MEM_SCALAR_P (mem) = src_scalar_p;
4374 emit_move_insn (sreg = gen_reg_rtx (SImode), mem);
4375 emit_move_insn (fin_src = gen_reg_rtx (SImode), plus_constant (src, 4));
4377 mem = gen_rtx_MEM (SImode, dst);
4378 RTX_UNCHANGING_P (mem) = dst_unchanging_p;
4379 MEM_IN_STRUCT_P (mem) = dst_in_struct_p;
4380 MEM_SCALAR_P (mem) = dst_scalar_p;
4381 emit_move_insn (mem, sreg);
4382 emit_move_insn (fin_dst = gen_reg_rtx (SImode), plus_constant (dst, 4));
4385 if (in_words_to_go) /* Sanity check */
4391 if (in_words_to_go < 0)
4394 mem = gen_rtx_MEM (SImode, src);
4395 RTX_UNCHANGING_P (mem) = src_unchanging_p;
4396 MEM_IN_STRUCT_P (mem) = src_in_struct_p;
4397 MEM_SCALAR_P (mem) = src_scalar_p;
4398 part_bytes_reg = copy_to_mode_reg (SImode, mem);
4401 if (last_bytes && part_bytes_reg == NULL)
4404 if (BYTES_BIG_ENDIAN && last_bytes)
4406 rtx tmp = gen_reg_rtx (SImode);
4408 /* The bytes we want are in the top end of the word. */
4409 emit_insn (gen_lshrsi3 (tmp, part_bytes_reg,
4410 GEN_INT (8 * (4 - last_bytes))));
4411 part_bytes_reg = tmp;
4415 mem = gen_rtx_MEM (QImode, plus_constant (dst, last_bytes - 1));
4416 RTX_UNCHANGING_P (mem) = dst_unchanging_p;
4417 MEM_IN_STRUCT_P (mem) = dst_in_struct_p;
4418 MEM_SCALAR_P (mem) = dst_scalar_p;
4419 emit_move_insn (mem, gen_rtx_SUBREG (QImode, part_bytes_reg, 0));
4423 tmp = gen_reg_rtx (SImode);
4424 emit_insn (gen_lshrsi3 (tmp, part_bytes_reg, GEN_INT (8)));
4425 part_bytes_reg = tmp;
4434 mem = gen_rtx_MEM (HImode, dst);
4435 RTX_UNCHANGING_P (mem) = dst_unchanging_p;
4436 MEM_IN_STRUCT_P (mem) = dst_in_struct_p;
4437 MEM_SCALAR_P (mem) = dst_scalar_p;
4438 emit_move_insn (mem, gen_rtx_SUBREG (HImode, part_bytes_reg, 0));
4442 rtx tmp = gen_reg_rtx (SImode);
4444 emit_insn (gen_addsi3 (dst, dst, GEN_INT (2)));
4445 emit_insn (gen_lshrsi3 (tmp, part_bytes_reg, GEN_INT (16)));
4446 part_bytes_reg = tmp;
4452 mem = gen_rtx_MEM (QImode, dst);
4453 RTX_UNCHANGING_P (mem) = dst_unchanging_p;
4454 MEM_IN_STRUCT_P (mem) = dst_in_struct_p;
4455 MEM_SCALAR_P (mem) = dst_scalar_p;
4456 emit_move_insn (mem, gen_rtx_SUBREG (QImode, part_bytes_reg, 0));
4463 /* Generate a memory reference for a half word, such that it will be loaded
4464 into the top 16 bits of the word. We can assume that the address is
4465 known to be alignable and of the form reg, or plus (reg, const). */
4467 arm_gen_rotated_half_load (memref)
4470 HOST_WIDE_INT offset = 0;
4471 rtx base = XEXP (memref, 0);
4473 if (GET_CODE (base) == PLUS)
4475 offset = INTVAL (XEXP (base, 1));
4476 base = XEXP (base, 0);
4479 /* If we aren't allowed to generate unaligned addresses, then fail. */
4480 if (TARGET_MMU_TRAPS
4481 && ((BYTES_BIG_ENDIAN ? 1 : 0) ^ ((offset & 2) == 0)))
4484 base = gen_rtx_MEM (SImode, plus_constant (base, offset & ~2));
4486 if ((BYTES_BIG_ENDIAN ? 1 : 0) ^ ((offset & 2) == 2))
4489 return gen_rtx_ROTATE (SImode, base, GEN_INT (16));
4492 /* Select a dominance comparison mode if possible. We support three forms.
4493 COND_OR == 0 => (X && Y)
4494 COND_OR == 1 => ((! X( || Y)
4495 COND_OR == 2 => (X || Y)
4496 If we are unable to support a dominance comparsison we return CC mode.
4497 This will then fail to match for the RTL expressions that generate this
4500 static enum machine_mode
4501 select_dominance_cc_mode (x, y, cond_or)
4504 HOST_WIDE_INT cond_or;
4506 enum rtx_code cond1, cond2;
4509 /* Currently we will probably get the wrong result if the individual
4510 comparisons are not simple. This also ensures that it is safe to
4511 reverse a comparison if necessary. */
4512 if ((arm_select_cc_mode (cond1 = GET_CODE (x), XEXP (x, 0), XEXP (x, 1))
4514 || (arm_select_cc_mode (cond2 = GET_CODE (y), XEXP (y, 0), XEXP (y, 1))
4518 /* The if_then_else variant of this tests the second condition if the
4519 first passes, but is true if the first fails. Reverse the first
4520 condition to get a true "inclusive-or" expression. */
4522 cond1 = reverse_condition (cond1);
4524 /* If the comparisons are not equal, and one doesn't dominate the other,
4525 then we can't do this. */
4527 && !comparison_dominates_p (cond1, cond2)
4528 && (swapped = 1, !comparison_dominates_p (cond2, cond1)))
4533 enum rtx_code temp = cond1;
4541 if (cond2 == EQ || !cond_or)
4546 case LE: return CC_DLEmode;
4547 case LEU: return CC_DLEUmode;
4548 case GE: return CC_DGEmode;
4549 case GEU: return CC_DGEUmode;
4556 if (cond2 == LT || !cond_or)
4565 if (cond2 == GT || !cond_or)
4574 if (cond2 == LTU || !cond_or)
4583 if (cond2 == GTU || !cond_or)
4591 /* The remaining cases only occur when both comparisons are the
4616 arm_select_cc_mode (op, x, y)
4621 /* All floating point compares return CCFP if it is an equality
4622 comparison, and CCFPE otherwise. */
4623 if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
4650 /* A compare with a shifted operand. Because of canonicalization, the
4651 comparison will have to be swapped when we emit the assembler. */
4652 if (GET_MODE (y) == SImode && GET_CODE (y) == REG
4653 && (GET_CODE (x) == ASHIFT || GET_CODE (x) == ASHIFTRT
4654 || GET_CODE (x) == LSHIFTRT || GET_CODE (x) == ROTATE
4655 || GET_CODE (x) == ROTATERT))
4658 /* This is a special case that is used by combine to allow a
4659 comparison of a shifted byte load to be split into a zero-extend
4660 followed by a comparison of the shifted integer (only valid for
4661 equalities and unsigned inequalities). */
4662 if (GET_MODE (x) == SImode
4663 && GET_CODE (x) == ASHIFT
4664 && GET_CODE (XEXP (x, 1)) == CONST_INT && INTVAL (XEXP (x, 1)) == 24
4665 && GET_CODE (XEXP (x, 0)) == SUBREG
4666 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == MEM
4667 && GET_MODE (SUBREG_REG (XEXP (x, 0))) == QImode
4668 && (op == EQ || op == NE
4669 || op == GEU || op == GTU || op == LTU || op == LEU)
4670 && GET_CODE (y) == CONST_INT)
4673 /* A construct for a conditional compare, if the false arm contains
4674 0, then both conditions must be true, otherwise either condition
4675 must be true. Not all conditions are possible, so CCmode is
4676 returned if it can't be done. */
4677 if (GET_CODE (x) == IF_THEN_ELSE
4678 && (XEXP (x, 2) == const0_rtx
4679 || XEXP (x, 2) == const1_rtx)
4680 && GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
4681 && GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) == '<')
4682 return select_dominance_cc_mode (XEXP (x, 0), XEXP (x, 1),
4683 INTVAL (XEXP (x, 2)));
4685 /* Alternate canonicalizations of the above. These are somewhat cleaner. */
4686 if (GET_CODE (x) == AND
4687 && GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
4688 && GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) == '<')
4689 return select_dominance_cc_mode (XEXP (x, 0), XEXP (x, 1), 0);
4691 if (GET_CODE (x) == IOR
4692 && GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
4693 && GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) == '<')
4694 return select_dominance_cc_mode (XEXP (x, 0), XEXP (x, 1), 2);
4696 /* An operation that sets the condition codes as a side-effect, the
4697 V flag is not set correctly, so we can only use comparisons where
4698 this doesn't matter. (For LT and GE we can use "mi" and "pl"
4700 if (GET_MODE (x) == SImode
4702 && (op == EQ || op == NE || op == LT || op == GE)
4703 && (GET_CODE (x) == PLUS || GET_CODE (x) == MINUS
4704 || GET_CODE (x) == AND || GET_CODE (x) == IOR
4705 || GET_CODE (x) == XOR || GET_CODE (x) == MULT
4706 || GET_CODE (x) == NOT || GET_CODE (x) == NEG
4707 || GET_CODE (x) == LSHIFTRT
4708 || GET_CODE (x) == ASHIFT || GET_CODE (x) == ASHIFTRT
4709 || GET_CODE (x) == ROTATERT || GET_CODE (x) == ZERO_EXTRACT))
4712 if (GET_MODE (x) == QImode && (op == EQ || op == NE))
4715 if (GET_MODE (x) == SImode && (op == LTU || op == GEU)
4716 && GET_CODE (x) == PLUS
4717 && (rtx_equal_p (XEXP (x, 0), y) || rtx_equal_p (XEXP (x, 1), y)))
4723 /* X and Y are two things to compare using CODE. Emit the compare insn and
4724 return the rtx for register 0 in the proper mode. FP means this is a
4725 floating point compare: I don't think that it is needed on the arm. */
4728 arm_gen_compare_reg (code, x, y)
4732 enum machine_mode mode = SELECT_CC_MODE (code, x, y);
4733 rtx cc_reg = gen_rtx_REG (mode, CC_REGNUM);
4735 emit_insn (gen_rtx_SET (VOIDmode, cc_reg,
4736 gen_rtx_COMPARE (mode, x, y)));
4742 arm_reload_in_hi (operands)
4745 rtx ref = operands[1];
4747 HOST_WIDE_INT offset = 0;
4749 if (GET_CODE (ref) == SUBREG)
4751 offset = SUBREG_BYTE (ref);
4752 ref = SUBREG_REG (ref);
4755 if (GET_CODE (ref) == REG)
4757 /* We have a pseudo which has been spilt onto the stack; there
4758 are two cases here: the first where there is a simple
4759 stack-slot replacement and a second where the stack-slot is
4760 out of range, or is used as a subreg. */
4761 if (reg_equiv_mem[REGNO (ref)])
4763 ref = reg_equiv_mem[REGNO (ref)];
4764 base = find_replacement (&XEXP (ref, 0));
4767 /* The slot is out of range, or was dressed up in a SUBREG. */
4768 base = reg_equiv_address[REGNO (ref)];
4771 base = find_replacement (&XEXP (ref, 0));
4773 /* Handle the case where the address is too complex to be offset by 1. */
4774 if (GET_CODE (base) == MINUS
4775 || (GET_CODE (base) == PLUS && GET_CODE (XEXP (base, 1)) != CONST_INT))
4777 rtx base_plus = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
4779 emit_insn (gen_rtx_SET (VOIDmode, base_plus, base));
4782 else if (GET_CODE (base) == PLUS)
4784 /* The addend must be CONST_INT, or we would have dealt with it above. */
4785 HOST_WIDE_INT hi, lo;
4787 offset += INTVAL (XEXP (base, 1));
4788 base = XEXP (base, 0);
4790 /* Rework the address into a legal sequence of insns. */
4791 /* Valid range for lo is -4095 -> 4095 */
4794 : -((-offset) & 0xfff));
4796 /* Corner case, if lo is the max offset then we would be out of range
4797 once we have added the additional 1 below, so bump the msb into the
4798 pre-loading insn(s). */
4802 hi = ((((offset - lo) & HOST_INT (0xffffffff))
4803 ^ HOST_INT (0x80000000))
4804 - HOST_INT (0x80000000));
4806 if (hi + lo != offset)
4811 rtx base_plus = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
4813 /* Get the base address; addsi3 knows how to handle constants
4814 that require more than one insn. */
4815 emit_insn (gen_addsi3 (base_plus, base, GEN_INT (hi)));
4821 scratch = gen_rtx_REG (SImode, REGNO (operands[2]));
4822 emit_insn (gen_zero_extendqisi2 (scratch,
4823 gen_rtx_MEM (QImode,
4824 plus_constant (base,
4826 emit_insn (gen_zero_extendqisi2 (gen_rtx_SUBREG (SImode, operands[0], 0),
4827 gen_rtx_MEM (QImode,
4828 plus_constant (base,
4830 if (!BYTES_BIG_ENDIAN)
4831 emit_insn (gen_rtx_SET (VOIDmode, gen_rtx_SUBREG (SImode, operands[0], 0),
4832 gen_rtx_IOR (SImode,
4835 gen_rtx_SUBREG (SImode, operands[0], 0),
4839 emit_insn (gen_rtx_SET (VOIDmode, gen_rtx_SUBREG (SImode, operands[0], 0),
4840 gen_rtx_IOR (SImode,
4841 gen_rtx_ASHIFT (SImode, scratch,
4843 gen_rtx_SUBREG (SImode, operands[0],
4847 /* Handle storing a half-word to memory during reload by synthesising as two
4848 byte stores. Take care not to clobber the input values until after we
4849 have moved them somewhere safe. This code assumes that if the DImode
4850 scratch in operands[2] overlaps either the input value or output address
4851 in some way, then that value must die in this insn (we absolutely need
4852 two scratch registers for some corner cases). */
4854 arm_reload_out_hi (operands)
4857 rtx ref = operands[0];
4858 rtx outval = operands[1];
4860 HOST_WIDE_INT offset = 0;
4862 if (GET_CODE (ref) == SUBREG)
4864 offset = SUBREG_BYTE (ref);
4865 ref = SUBREG_REG (ref);
4869 if (GET_CODE (ref) == REG)
4871 /* We have a pseudo which has been spilt onto the stack; there
4872 are two cases here: the first where there is a simple
4873 stack-slot replacement and a second where the stack-slot is
4874 out of range, or is used as a subreg. */
4875 if (reg_equiv_mem[REGNO (ref)])
4877 ref = reg_equiv_mem[REGNO (ref)];
4878 base = find_replacement (&XEXP (ref, 0));
4881 /* The slot is out of range, or was dressed up in a SUBREG. */
4882 base = reg_equiv_address[REGNO (ref)];
4885 base = find_replacement (&XEXP (ref, 0));
4887 scratch = gen_rtx_REG (SImode, REGNO (operands[2]));
4889 /* Handle the case where the address is too complex to be offset by 1. */
4890 if (GET_CODE (base) == MINUS
4891 || (GET_CODE (base) == PLUS && GET_CODE (XEXP (base, 1)) != CONST_INT))
4893 rtx base_plus = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
4895 /* Be careful not to destroy OUTVAL. */
4896 if (reg_overlap_mentioned_p (base_plus, outval))
4898 /* Updating base_plus might destroy outval, see if we can
4899 swap the scratch and base_plus. */
4900 if (!reg_overlap_mentioned_p (scratch, outval))
4903 scratch = base_plus;
4908 rtx scratch_hi = gen_rtx_REG (HImode, REGNO (operands[2]));
4910 /* Be conservative and copy OUTVAL into the scratch now,
4911 this should only be necessary if outval is a subreg
4912 of something larger than a word. */
4913 /* XXX Might this clobber base? I can't see how it can,
4914 since scratch is known to overlap with OUTVAL, and
4915 must be wider than a word. */
4916 emit_insn (gen_movhi (scratch_hi, outval));
4917 outval = scratch_hi;
4921 emit_insn (gen_rtx_SET (VOIDmode, base_plus, base));
4924 else if (GET_CODE (base) == PLUS)
4926 /* The addend must be CONST_INT, or we would have dealt with it above. */
4927 HOST_WIDE_INT hi, lo;
4929 offset += INTVAL (XEXP (base, 1));
4930 base = XEXP (base, 0);
4932 /* Rework the address into a legal sequence of insns. */
4933 /* Valid range for lo is -4095 -> 4095 */
4936 : -((-offset) & 0xfff));
4938 /* Corner case, if lo is the max offset then we would be out of range
4939 once we have added the additional 1 below, so bump the msb into the
4940 pre-loading insn(s). */
4944 hi = ((((offset - lo) & HOST_INT (0xffffffff))
4945 ^ HOST_INT (0x80000000))
4946 - HOST_INT (0x80000000));
4948 if (hi + lo != offset)
4953 rtx base_plus = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
4955 /* Be careful not to destroy OUTVAL. */
4956 if (reg_overlap_mentioned_p (base_plus, outval))
4958 /* Updating base_plus might destroy outval, see if we
4959 can swap the scratch and base_plus. */
4960 if (!reg_overlap_mentioned_p (scratch, outval))
4963 scratch = base_plus;
4968 rtx scratch_hi = gen_rtx_REG (HImode, REGNO (operands[2]));
4970 /* Be conservative and copy outval into scratch now,
4971 this should only be necessary if outval is a
4972 subreg of something larger than a word. */
4973 /* XXX Might this clobber base? I can't see how it
4974 can, since scratch is known to overlap with
4976 emit_insn (gen_movhi (scratch_hi, outval));
4977 outval = scratch_hi;
4981 /* Get the base address; addsi3 knows how to handle constants
4982 that require more than one insn. */
4983 emit_insn (gen_addsi3 (base_plus, base, GEN_INT (hi)));
4989 if (BYTES_BIG_ENDIAN)
4991 emit_insn (gen_movqi (gen_rtx_MEM (QImode,
4992 plus_constant (base, offset + 1)),
4993 gen_rtx_SUBREG (QImode, outval, 0)));
4994 emit_insn (gen_lshrsi3 (scratch,
4995 gen_rtx_SUBREG (SImode, outval, 0),
4997 emit_insn (gen_movqi (gen_rtx_MEM (QImode, plus_constant (base, offset)),
4998 gen_rtx_SUBREG (QImode, scratch, 0)));
5002 emit_insn (gen_movqi (gen_rtx_MEM (QImode, plus_constant (base, offset)),
5003 gen_rtx_SUBREG (QImode, outval, 0)));
5004 emit_insn (gen_lshrsi3 (scratch,
5005 gen_rtx_SUBREG (SImode, outval, 0),
5007 emit_insn (gen_movqi (gen_rtx_MEM (QImode,
5008 plus_constant (base, offset + 1)),
5009 gen_rtx_SUBREG (QImode, scratch, 0)));
5013 /* Print a symbolic form of X to the debug file, F. */
5015 arm_print_value (f, x)
5019 switch (GET_CODE (x))
5022 fprintf (f, HOST_WIDE_INT_PRINT_HEX, INTVAL (x));
5026 fprintf (f, "<0x%lx,0x%lx>", (long)XWINT (x, 2), (long)XWINT (x, 3));
5030 fprintf (f, "\"%s\"", XSTR (x, 0));
5034 fprintf (f, "`%s'", XSTR (x, 0));
5038 fprintf (f, "L%d", INSN_UID (XEXP (x, 0)));
5042 arm_print_value (f, XEXP (x, 0));
5046 arm_print_value (f, XEXP (x, 0));
5048 arm_print_value (f, XEXP (x, 1));
5056 fprintf (f, "????");
5061 /* Routines for manipulation of the constant pool. */
5063 /* Arm instructions cannot load a large constant directly into a
5064 register; they have to come from a pc relative load. The constant
5065 must therefore be placed in the addressable range of the pc
5066 relative load. Depending on the precise pc relative load
5067 instruction the range is somewhere between 256 bytes and 4k. This
5068 means that we often have to dump a constant inside a function, and
5069 generate code to branch around it.
5071 It is important to minimize this, since the branches will slow
5072 things down and make the code larger.
5074 Normally we can hide the table after an existing unconditional
5075 branch so that there is no interruption of the flow, but in the
5076 worst case the code looks like this:
5094 We fix this by performing a scan after scheduling, which notices
5095 which instructions need to have their operands fetched from the
5096 constant table and builds the table.
5098 The algorithm starts by building a table of all the constants that
5099 need fixing up and all the natural barriers in the function (places
5100 where a constant table can be dropped without breaking the flow).
5101 For each fixup we note how far the pc-relative replacement will be
5102 able to reach and the offset of the instruction into the function.
5104 Having built the table we then group the fixes together to form
5105 tables that are as large as possible (subject to addressing
5106 constraints) and emit each table of constants after the last
5107 barrier that is within range of all the instructions in the group.
5108 If a group does not contain a barrier, then we forcibly create one
5109 by inserting a jump instruction into the flow. Once the table has
5110 been inserted, the insns are then modified to reference the
5111 relevant entry in the pool.
5113 Possible enhancements to the algorithm (not implemented) are:
5115 1) For some processors and object formats, there may be benefit in
5116 aligning the pools to the start of cache lines; this alignment
5117 would need to be taken into account when calculating addressability
5120 /* These typedefs are located at the start of this file, so that
5121 they can be used in the prototypes there. This comment is to
5122 remind readers of that fact so that the following structures
5123 can be understood more easily.
5125 typedef struct minipool_node Mnode;
5126 typedef struct minipool_fixup Mfix; */
5128 struct minipool_node
5130 /* Doubly linked chain of entries. */
5133 /* The maximum offset into the code that this entry can be placed. While
5134 pushing fixes for forward references, all entries are sorted in order
5135 of increasing max_address. */
5136 HOST_WIDE_INT max_address;
5137 /* Similarly for a entry inserted for a backwards ref. */
5138 HOST_WIDE_INT min_address;
5139 /* The number of fixes referencing this entry. This can become zero
5140 if we "unpush" an entry. In this case we ignore the entry when we
5141 come to emit the code. */
5143 /* The offset from the start of the minipool. */
5144 HOST_WIDE_INT offset;
5145 /* The value in table. */
5147 /* The mode of value. */
5148 enum machine_mode mode;
5152 struct minipool_fixup
5156 HOST_WIDE_INT address;
5158 enum machine_mode mode;
5162 HOST_WIDE_INT forwards;
5163 HOST_WIDE_INT backwards;
5166 /* Fixes less than a word need padding out to a word boundary. */
5167 #define MINIPOOL_FIX_SIZE(mode) \
5168 (GET_MODE_SIZE ((mode)) >= 4 ? GET_MODE_SIZE ((mode)) : 4)
5170 static Mnode * minipool_vector_head;
5171 static Mnode * minipool_vector_tail;
5172 static rtx minipool_vector_label;
5174 /* The linked list of all minipool fixes required for this function. */
5175 Mfix * minipool_fix_head;
5176 Mfix * minipool_fix_tail;
5177 /* The fix entry for the current minipool, once it has been placed. */
5178 Mfix * minipool_barrier;
5180 /* Determines if INSN is the start of a jump table. Returns the end
5181 of the TABLE or NULL_RTX. */
5183 is_jump_table (insn)
5188 if (GET_CODE (insn) == JUMP_INSN
5189 && JUMP_LABEL (insn) != NULL
5190 && ((table = next_real_insn (JUMP_LABEL (insn)))
5191 == next_real_insn (insn))
5193 && GET_CODE (table) == JUMP_INSN
5194 && (GET_CODE (PATTERN (table)) == ADDR_VEC
5195 || GET_CODE (PATTERN (table)) == ADDR_DIFF_VEC))
5201 static HOST_WIDE_INT
5202 get_jump_table_size (insn)
5205 rtx body = PATTERN (insn);
5206 int elt = GET_CODE (body) == ADDR_DIFF_VEC ? 1 : 0;
5208 return GET_MODE_SIZE (GET_MODE (body)) * XVECLEN (body, elt);
5211 /* Move a minipool fix MP from its current location to before MAX_MP.
5212 If MAX_MP is NULL, then MP doesn't need moving, but the addressing
5213 contrains may need updating. */
5215 move_minipool_fix_forward_ref (mp, max_mp, max_address)
5218 HOST_WIDE_INT max_address;
5220 /* This should never be true and the code below assumes these are
5227 if (max_address < mp->max_address)
5228 mp->max_address = max_address;
5232 if (max_address > max_mp->max_address - mp->fix_size)
5233 mp->max_address = max_mp->max_address - mp->fix_size;
5235 mp->max_address = max_address;
5237 /* Unlink MP from its current position. Since max_mp is non-null,
5238 mp->prev must be non-null. */
5239 mp->prev->next = mp->next;
5240 if (mp->next != NULL)
5241 mp->next->prev = mp->prev;
5243 minipool_vector_tail = mp->prev;
5245 /* Re-insert it before MAX_MP. */
5247 mp->prev = max_mp->prev;
5250 if (mp->prev != NULL)
5251 mp->prev->next = mp;
5253 minipool_vector_head = mp;
5256 /* Save the new entry. */
5259 /* Scan over the preceeding entries and adjust their addresses as
5261 while (mp->prev != NULL
5262 && mp->prev->max_address > mp->max_address - mp->prev->fix_size)
5264 mp->prev->max_address = mp->max_address - mp->prev->fix_size;
5271 /* Add a constant to the minipool for a forward reference. Returns the
5272 node added or NULL if the constant will not fit in this pool. */
5274 add_minipool_forward_ref (fix)
5277 /* If set, max_mp is the first pool_entry that has a lower
5278 constraint than the one we are trying to add. */
5279 Mnode * max_mp = NULL;
5280 HOST_WIDE_INT max_address = fix->address + fix->forwards;
5283 /* If this fix's address is greater than the address of the first
5284 entry, then we can't put the fix in this pool. We subtract the
5285 size of the current fix to ensure that if the table is fully
5286 packed we still have enough room to insert this value by suffling
5287 the other fixes forwards. */
5288 if (minipool_vector_head &&
5289 fix->address >= minipool_vector_head->max_address - fix->fix_size)
5292 /* Scan the pool to see if a constant with the same value has
5293 already been added. While we are doing this, also note the
5294 location where we must insert the constant if it doesn't already
5296 for (mp = minipool_vector_head; mp != NULL; mp = mp->next)
5298 if (GET_CODE (fix->value) == GET_CODE (mp->value)
5299 && fix->mode == mp->mode
5300 && (GET_CODE (fix->value) != CODE_LABEL
5301 || (CODE_LABEL_NUMBER (fix->value)
5302 == CODE_LABEL_NUMBER (mp->value)))
5303 && rtx_equal_p (fix->value, mp->value))
5305 /* More than one fix references this entry. */
5307 return move_minipool_fix_forward_ref (mp, max_mp, max_address);
5310 /* Note the insertion point if necessary. */
5312 && mp->max_address > max_address)
5316 /* The value is not currently in the minipool, so we need to create
5317 a new entry for it. If MAX_MP is NULL, the entry will be put on
5318 the end of the list since the placement is less constrained than
5319 any existing entry. Otherwise, we insert the new fix before
5320 MAX_MP and, if neceesary, adjust the constraints on the other
5322 mp = xmalloc (sizeof (* mp));
5323 mp->fix_size = fix->fix_size;
5324 mp->mode = fix->mode;
5325 mp->value = fix->value;
5327 /* Not yet required for a backwards ref. */
5328 mp->min_address = -65536;
5332 mp->max_address = max_address;
5334 mp->prev = minipool_vector_tail;
5336 if (mp->prev == NULL)
5338 minipool_vector_head = mp;
5339 minipool_vector_label = gen_label_rtx ();
5342 mp->prev->next = mp;
5344 minipool_vector_tail = mp;
5348 if (max_address > max_mp->max_address - mp->fix_size)
5349 mp->max_address = max_mp->max_address - mp->fix_size;
5351 mp->max_address = max_address;
5354 mp->prev = max_mp->prev;
5356 if (mp->prev != NULL)
5357 mp->prev->next = mp;
5359 minipool_vector_head = mp;
5362 /* Save the new entry. */
5365 /* Scan over the preceeding entries and adjust their addresses as
5367 while (mp->prev != NULL
5368 && mp->prev->max_address > mp->max_address - mp->prev->fix_size)
5370 mp->prev->max_address = mp->max_address - mp->prev->fix_size;
5378 move_minipool_fix_backward_ref (mp, min_mp, min_address)
5381 HOST_WIDE_INT min_address;
5383 HOST_WIDE_INT offset;
5385 /* This should never be true, and the code below assumes these are
5392 if (min_address > mp->min_address)
5393 mp->min_address = min_address;
5397 /* We will adjust this below if it is too loose. */
5398 mp->min_address = min_address;
5400 /* Unlink MP from its current position. Since min_mp is non-null,
5401 mp->next must be non-null. */
5402 mp->next->prev = mp->prev;
5403 if (mp->prev != NULL)
5404 mp->prev->next = mp->next;
5406 minipool_vector_head = mp->next;
5408 /* Reinsert it after MIN_MP. */
5410 mp->next = min_mp->next;
5412 if (mp->next != NULL)
5413 mp->next->prev = mp;
5415 minipool_vector_tail = mp;
5421 for (mp = minipool_vector_head; mp != NULL; mp = mp->next)
5423 mp->offset = offset;
5424 if (mp->refcount > 0)
5425 offset += mp->fix_size;
5427 if (mp->next && mp->next->min_address < mp->min_address + mp->fix_size)
5428 mp->next->min_address = mp->min_address + mp->fix_size;
5434 /* Add a constant to the minipool for a backward reference. Returns the
5435 node added or NULL if the constant will not fit in this pool.
5437 Note that the code for insertion for a backwards reference can be
5438 somewhat confusing because the calculated offsets for each fix do
5439 not take into account the size of the pool (which is still under
5442 add_minipool_backward_ref (fix)
5445 /* If set, min_mp is the last pool_entry that has a lower constraint
5446 than the one we are trying to add. */
5447 Mnode * min_mp = NULL;
5448 /* This can be negative, since it is only a constraint. */
5449 HOST_WIDE_INT min_address = fix->address - fix->backwards;
5452 /* If we can't reach the current pool from this insn, or if we can't
5453 insert this entry at the end of the pool without pushing other
5454 fixes out of range, then we don't try. This ensures that we
5455 can't fail later on. */
5456 if (min_address >= minipool_barrier->address
5457 || (minipool_vector_tail->min_address + fix->fix_size
5458 >= minipool_barrier->address))
5461 /* Scan the pool to see if a constant with the same value has
5462 already been added. While we are doing this, also note the
5463 location where we must insert the constant if it doesn't already
5465 for (mp = minipool_vector_tail; mp != NULL; mp = mp->prev)
5467 if (GET_CODE (fix->value) == GET_CODE (mp->value)
5468 && fix->mode == mp->mode
5469 && (GET_CODE (fix->value) != CODE_LABEL
5470 || (CODE_LABEL_NUMBER (fix->value)
5471 == CODE_LABEL_NUMBER (mp->value)))
5472 && rtx_equal_p (fix->value, mp->value)
5473 /* Check that there is enough slack to move this entry to the
5474 end of the table (this is conservative). */
5476 > (minipool_barrier->address
5477 + minipool_vector_tail->offset
5478 + minipool_vector_tail->fix_size)))
5481 return move_minipool_fix_backward_ref (mp, min_mp, min_address);
5485 mp->min_address += fix->fix_size;
5488 /* Note the insertion point if necessary. */
5489 if (mp->min_address < min_address)
5491 else if (mp->max_address
5492 < minipool_barrier->address + mp->offset + fix->fix_size)
5494 /* Inserting before this entry would push the fix beyond
5495 its maximum address (which can happen if we have
5496 re-located a forwards fix); force the new fix to come
5499 min_address = mp->min_address + fix->fix_size;
5504 /* We need to create a new entry. */
5505 mp = xmalloc (sizeof (* mp));
5506 mp->fix_size = fix->fix_size;
5507 mp->mode = fix->mode;
5508 mp->value = fix->value;
5510 mp->max_address = minipool_barrier->address + 65536;
5512 mp->min_address = min_address;
5517 mp->next = minipool_vector_head;
5519 if (mp->next == NULL)
5521 minipool_vector_tail = mp;
5522 minipool_vector_label = gen_label_rtx ();
5525 mp->next->prev = mp;
5527 minipool_vector_head = mp;
5531 mp->next = min_mp->next;
5535 if (mp->next != NULL)
5536 mp->next->prev = mp;
5538 minipool_vector_tail = mp;
5541 /* Save the new entry. */
5549 /* Scan over the following entries and adjust their offsets. */
5550 while (mp->next != NULL)
5552 if (mp->next->min_address < mp->min_address + mp->fix_size)
5553 mp->next->min_address = mp->min_address + mp->fix_size;
5556 mp->next->offset = mp->offset + mp->fix_size;
5558 mp->next->offset = mp->offset;
5567 assign_minipool_offsets (barrier)
5570 HOST_WIDE_INT offset = 0;
5573 minipool_barrier = barrier;
5575 for (mp = minipool_vector_head; mp != NULL; mp = mp->next)
5577 mp->offset = offset;
5579 if (mp->refcount > 0)
5580 offset += mp->fix_size;
5584 /* Output the literal table */
5586 dump_minipool (scan)
5593 fprintf (rtl_dump_file,
5594 ";; Emitting minipool after insn %u; address %ld\n",
5595 INSN_UID (scan), (unsigned long) minipool_barrier->address);
5597 scan = emit_label_after (gen_label_rtx (), scan);
5598 scan = emit_insn_after (gen_align_4 (), scan);
5599 scan = emit_label_after (minipool_vector_label, scan);
5601 for (mp = minipool_vector_head; mp != NULL; mp = nmp)
5603 if (mp->refcount > 0)
5607 fprintf (rtl_dump_file,
5608 ";; Offset %u, min %ld, max %ld ",
5609 (unsigned) mp->offset, (unsigned long) mp->min_address,
5610 (unsigned long) mp->max_address);
5611 arm_print_value (rtl_dump_file, mp->value);
5612 fputc ('\n', rtl_dump_file);
5615 switch (mp->fix_size)
5617 #ifdef HAVE_consttable_1
5619 scan = emit_insn_after (gen_consttable_1 (mp->value), scan);
5623 #ifdef HAVE_consttable_2
5625 scan = emit_insn_after (gen_consttable_2 (mp->value), scan);
5629 #ifdef HAVE_consttable_4
5631 scan = emit_insn_after (gen_consttable_4 (mp->value), scan);
5635 #ifdef HAVE_consttable_8
5637 scan = emit_insn_after (gen_consttable_8 (mp->value), scan);
5651 minipool_vector_head = minipool_vector_tail = NULL;
5652 scan = emit_insn_after (gen_consttable_end (), scan);
5653 scan = emit_barrier_after (scan);
5656 /* Return the cost of forcibly inserting a barrier after INSN. */
5658 arm_barrier_cost (insn)
5661 /* Basing the location of the pool on the loop depth is preferable,
5662 but at the moment, the basic block information seems to be
5663 corrupt by this stage of the compilation. */
5665 rtx next = next_nonnote_insn (insn);
5667 if (next != NULL && GET_CODE (next) == CODE_LABEL)
5670 switch (GET_CODE (insn))
5673 /* It will always be better to place the table before the label, rather
5682 return base_cost - 10;
5685 return base_cost + 10;
5689 /* Find the best place in the insn stream in the range
5690 (FIX->address,MAX_ADDRESS) to forcibly insert a minipool barrier.
5691 Create the barrier by inserting a jump and add a new fix entry for
5694 create_fix_barrier (fix, max_address)
5696 HOST_WIDE_INT max_address;
5698 HOST_WIDE_INT count = 0;
5700 rtx from = fix->insn;
5701 rtx selected = from;
5703 HOST_WIDE_INT selected_address;
5705 HOST_WIDE_INT max_count = max_address - fix->address;
5706 rtx label = gen_label_rtx ();
5708 selected_cost = arm_barrier_cost (from);
5709 selected_address = fix->address;
5711 while (from && count < max_count)
5716 /* This code shouldn't have been called if there was a natural barrier
5718 if (GET_CODE (from) == BARRIER)
5721 /* Count the length of this insn. */
5722 count += get_attr_length (from);
5724 /* If there is a jump table, add its length. */
5725 tmp = is_jump_table (from);
5728 count += get_jump_table_size (tmp);
5730 /* Jump tables aren't in a basic block, so base the cost on
5731 the dispatch insn. If we select this location, we will
5732 still put the pool after the table. */
5733 new_cost = arm_barrier_cost (from);
5735 if (count < max_count && new_cost <= selected_cost)
5738 selected_cost = new_cost;
5739 selected_address = fix->address + count;
5742 /* Continue after the dispatch table. */
5743 from = NEXT_INSN (tmp);
5747 new_cost = arm_barrier_cost (from);
5749 if (count < max_count && new_cost <= selected_cost)
5752 selected_cost = new_cost;
5753 selected_address = fix->address + count;
5756 from = NEXT_INSN (from);
5759 /* Create a new JUMP_INSN that branches around a barrier. */
5760 from = emit_jump_insn_after (gen_jump (label), selected);
5761 JUMP_LABEL (from) = label;
5762 barrier = emit_barrier_after (from);
5763 emit_label_after (label, barrier);
5765 /* Create a minipool barrier entry for the new barrier. */
5766 new_fix = (Mfix *) obstack_alloc (&minipool_obstack, sizeof (* new_fix));
5767 new_fix->insn = barrier;
5768 new_fix->address = selected_address;
5769 new_fix->next = fix->next;
5770 fix->next = new_fix;
5775 /* Record that there is a natural barrier in the insn stream at
5778 push_minipool_barrier (insn, address)
5780 HOST_WIDE_INT address;
5782 Mfix * fix = (Mfix *) obstack_alloc (&minipool_obstack, sizeof (* fix));
5785 fix->address = address;
5788 if (minipool_fix_head != NULL)
5789 minipool_fix_tail->next = fix;
5791 minipool_fix_head = fix;
5793 minipool_fix_tail = fix;
5796 /* Record INSN, which will need fixing up to load a value from the
5797 minipool. ADDRESS is the offset of the insn since the start of the
5798 function; LOC is a pointer to the part of the insn which requires
5799 fixing; VALUE is the constant that must be loaded, which is of type
5802 push_minipool_fix (insn, address, loc, mode, value)
5804 HOST_WIDE_INT address;
5806 enum machine_mode mode;
5809 Mfix * fix = (Mfix *) obstack_alloc (&minipool_obstack, sizeof (* fix));
5811 #ifdef AOF_ASSEMBLER
5812 /* PIC symbol refereneces need to be converted into offsets into the
5814 /* XXX This shouldn't be done here. */
5815 if (flag_pic && GET_CODE (value) == SYMBOL_REF)
5816 value = aof_pic_entry (value);
5817 #endif /* AOF_ASSEMBLER */
5820 fix->address = address;
5823 fix->fix_size = MINIPOOL_FIX_SIZE (mode);
5825 fix->forwards = get_attr_pool_range (insn);
5826 fix->backwards = get_attr_neg_pool_range (insn);
5827 fix->minipool = NULL;
5829 /* If an insn doesn't have a range defined for it, then it isn't
5830 expecting to be reworked by this code. Better to abort now than
5831 to generate duff assembly code. */
5832 if (fix->forwards == 0 && fix->backwards == 0)
5837 fprintf (rtl_dump_file,
5838 ";; %smode fixup for i%d; addr %lu, range (%ld,%ld): ",
5839 GET_MODE_NAME (mode),
5840 INSN_UID (insn), (unsigned long) address,
5841 -1 * (long)fix->backwards, (long)fix->forwards);
5842 arm_print_value (rtl_dump_file, fix->value);
5843 fprintf (rtl_dump_file, "\n");
5846 /* Add it to the chain of fixes. */
5849 if (minipool_fix_head != NULL)
5850 minipool_fix_tail->next = fix;
5852 minipool_fix_head = fix;
5854 minipool_fix_tail = fix;
5857 /* Scan INSN and note any of its operands that need fixing. */
5859 note_invalid_constants (insn, address)
5861 HOST_WIDE_INT address;
5865 extract_insn (insn);
5867 if (!constrain_operands (1))
5868 fatal_insn_not_found (insn);
5870 /* Fill in recog_op_alt with information about the constraints of this
5872 preprocess_constraints ();
5874 for (opno = 0; opno < recog_data.n_operands; opno++)
5876 /* Things we need to fix can only occur in inputs. */
5877 if (recog_data.operand_type[opno] != OP_IN)
5880 /* If this alternative is a memory reference, then any mention
5881 of constants in this alternative is really to fool reload
5882 into allowing us to accept one there. We need to fix them up
5883 now so that we output the right code. */
5884 if (recog_op_alt[opno][which_alternative].memory_ok)
5886 rtx op = recog_data.operand[opno];
5888 if (CONSTANT_P (op))
5889 push_minipool_fix (insn, address, recog_data.operand_loc[opno],
5890 recog_data.operand_mode[opno], op);
5892 /* RWE: Now we look correctly at the operands for the insn,
5893 this shouldn't be needed any more. */
5894 #ifndef AOF_ASSEMBLER
5895 /* XXX Is this still needed? */
5896 else if (GET_CODE (op) == UNSPEC && XINT (op, 1) == UNSPEC_PIC_SYM)
5897 push_minipool_fix (insn, address, recog_data.operand_loc[opno],
5898 recog_data.operand_mode[opno],
5899 XVECEXP (op, 0, 0));
5902 else if (GET_CODE (op) == MEM
5903 && GET_CODE (XEXP (op, 0)) == SYMBOL_REF
5904 && CONSTANT_POOL_ADDRESS_P (XEXP (op, 0)))
5905 push_minipool_fix (insn, address, recog_data.operand_loc[opno],
5906 recog_data.operand_mode[opno],
5907 get_pool_constant (XEXP (op, 0)));
5917 HOST_WIDE_INT address = 0;
5920 minipool_fix_head = minipool_fix_tail = NULL;
5922 /* The first insn must always be a note, or the code below won't
5923 scan it properly. */
5924 if (GET_CODE (first) != NOTE)
5927 /* Scan all the insns and record the operands that will need fixing. */
5928 for (insn = next_nonnote_insn (first); insn; insn = next_nonnote_insn (insn))
5930 if (GET_CODE (insn) == BARRIER)
5931 push_minipool_barrier (insn, address);
5932 else if (GET_CODE (insn) == INSN || GET_CODE (insn) == CALL_INSN
5933 || GET_CODE (insn) == JUMP_INSN)
5937 note_invalid_constants (insn, address);
5938 address += get_attr_length (insn);
5940 /* If the insn is a vector jump, add the size of the table
5941 and skip the table. */
5942 if ((table = is_jump_table (insn)) != NULL)
5944 address += get_jump_table_size (table);
5950 fix = minipool_fix_head;
5952 /* Now scan the fixups and perform the required changes. */
5957 Mfix * last_added_fix;
5958 Mfix * last_barrier = NULL;
5961 /* Skip any further barriers before the next fix. */
5962 while (fix && GET_CODE (fix->insn) == BARRIER)
5965 /* No more fixes. */
5969 last_added_fix = NULL;
5971 for (ftmp = fix; ftmp; ftmp = ftmp->next)
5973 if (GET_CODE (ftmp->insn) == BARRIER)
5975 if (ftmp->address >= minipool_vector_head->max_address)
5978 last_barrier = ftmp;
5980 else if ((ftmp->minipool = add_minipool_forward_ref (ftmp)) == NULL)
5983 last_added_fix = ftmp; /* Keep track of the last fix added. */
5986 /* If we found a barrier, drop back to that; any fixes that we
5987 could have reached but come after the barrier will now go in
5988 the next mini-pool. */
5989 if (last_barrier != NULL)
5991 /* Reduce the refcount for those fixes that won't go into this
5993 for (fdel = last_barrier->next;
5994 fdel && fdel != ftmp;
5997 fdel->minipool->refcount--;
5998 fdel->minipool = NULL;
6001 ftmp = last_barrier;
6005 /* ftmp is first fix that we can't fit into this pool and
6006 there no natural barriers that we could use. Insert a
6007 new barrier in the code somewhere between the previous
6008 fix and this one, and arrange to jump around it. */
6009 HOST_WIDE_INT max_address;
6011 /* The last item on the list of fixes must be a barrier, so
6012 we can never run off the end of the list of fixes without
6013 last_barrier being set. */
6017 max_address = minipool_vector_head->max_address;
6018 /* Check that there isn't another fix that is in range that
6019 we couldn't fit into this pool because the pool was
6020 already too large: we need to put the pool before such an
6022 if (ftmp->address < max_address)
6023 max_address = ftmp->address;
6025 last_barrier = create_fix_barrier (last_added_fix, max_address);
6028 assign_minipool_offsets (last_barrier);
6032 if (GET_CODE (ftmp->insn) != BARRIER
6033 && ((ftmp->minipool = add_minipool_backward_ref (ftmp))
6040 /* Scan over the fixes we have identified for this pool, fixing them
6041 up and adding the constants to the pool itself. */
6042 for (this_fix = fix; this_fix && ftmp != this_fix;
6043 this_fix = this_fix->next)
6044 if (GET_CODE (this_fix->insn) != BARRIER)
6047 = plus_constant (gen_rtx_LABEL_REF (VOIDmode,
6048 minipool_vector_label),
6049 this_fix->minipool->offset);
6050 *this_fix->loc = gen_rtx_MEM (this_fix->mode, addr);
6053 dump_minipool (last_barrier->insn);
6057 /* From now on we must synthesize any constants that we can't handle
6058 directly. This can happen if the RTL gets split during final
6059 instruction generation. */
6060 after_arm_reorg = 1;
6062 /* Free the minipool memory. */
6063 obstack_free (&minipool_obstack, minipool_startobj);
6066 /* Routines to output assembly language. */
6068 /* If the rtx is the correct value then return the string of the number.
6069 In this way we can ensure that valid double constants are generated even
6070 when cross compiling. */
6072 fp_immediate_constant (x)
6078 if (!fpa_consts_inited)
6081 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
6082 for (i = 0; i < 8; i++)
6083 if (REAL_VALUES_EQUAL (r, values_fpa[i]))
6084 return strings_fpa[i];
6089 /* As for fp_immediate_constant, but value is passed directly, not in rtx. */
6091 fp_const_from_val (r)
6092 REAL_VALUE_TYPE * r;
6096 if (!fpa_consts_inited)
6099 for (i = 0; i < 8; i++)
6100 if (REAL_VALUES_EQUAL (*r, values_fpa[i]))
6101 return strings_fpa[i];
6106 /* Output the operands of a LDM/STM instruction to STREAM.
6107 MASK is the ARM register set mask of which only bits 0-15 are important.
6108 REG is the base register, either the frame pointer or the stack pointer,
6109 INSTR is the possibly suffixed load or store instruction. */
6112 print_multi_reg (stream, instr, reg, mask)
6119 int not_first = FALSE;
6121 fputc ('\t', stream);
6122 asm_fprintf (stream, instr, reg);
6123 fputs (", {", stream);
6125 for (i = 0; i <= LAST_ARM_REGNUM; i++)
6126 if (mask & (1 << i))
6129 fprintf (stream, ", ");
6131 asm_fprintf (stream, "%r", i);
6135 fprintf (stream, "}%s\n", TARGET_APCS_32 ? "" : "^");
6138 /* Output a 'call' insn. */
6141 output_call (operands)
6144 /* Handle calls to lr using ip (which may be clobbered in subr anyway). */
6146 if (REGNO (operands[0]) == LR_REGNUM)
6148 operands[0] = gen_rtx_REG (SImode, IP_REGNUM);
6149 output_asm_insn ("mov%?\t%0, %|lr", operands);
6152 output_asm_insn ("mov%?\t%|lr, %|pc", operands);
6154 if (TARGET_INTERWORK)
6155 output_asm_insn ("bx%?\t%0", operands);
6157 output_asm_insn ("mov%?\t%|pc, %0", operands);
6166 int something_changed = 0;
6168 int code = GET_CODE (x0);
6170 register const char * fmt;
6175 if (REGNO (x0) == LR_REGNUM)
6177 *x = gen_rtx_REG (SImode, IP_REGNUM);
6182 /* Scan through the sub-elements and change any references there. */
6183 fmt = GET_RTX_FORMAT (code);
6185 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
6187 something_changed |= eliminate_lr2ip (&XEXP (x0, i));
6188 else if (fmt[i] == 'E')
6189 for (j = 0; j < XVECLEN (x0, i); j++)
6190 something_changed |= eliminate_lr2ip (&XVECEXP (x0, i, j));
6192 return something_changed;
6196 /* Output a 'call' insn that is a reference in memory. */
6199 output_call_mem (operands)
6202 operands[0] = copy_rtx (operands[0]); /* Be ultra careful. */
6203 /* Handle calls using lr by using ip (which may be clobbered in subr anyway). */
6204 if (eliminate_lr2ip (&operands[0]))
6205 output_asm_insn ("mov%?\t%|ip, %|lr", operands);
6207 if (TARGET_INTERWORK)
6209 output_asm_insn ("ldr%?\t%|ip, %0", operands);
6210 output_asm_insn ("mov%?\t%|lr, %|pc", operands);
6211 output_asm_insn ("bx%?\t%|ip", operands);
6215 output_asm_insn ("mov%?\t%|lr, %|pc", operands);
6216 output_asm_insn ("ldr%?\t%|pc, %0", operands);
6223 /* Output a move from arm registers to an fpu registers.
6224 OPERANDS[0] is an fpu register.
6225 OPERANDS[1] is the first registers of an arm register pair. */
6228 output_mov_long_double_fpu_from_arm (operands)
6231 int arm_reg0 = REGNO (operands[1]);
6234 if (arm_reg0 == IP_REGNUM)
6237 ops[0] = gen_rtx_REG (SImode, arm_reg0);
6238 ops[1] = gen_rtx_REG (SImode, 1 + arm_reg0);
6239 ops[2] = gen_rtx_REG (SImode, 2 + arm_reg0);
6241 output_asm_insn ("stm%?fd\t%|sp!, {%0, %1, %2}", ops);
6242 output_asm_insn ("ldf%?e\t%0, [%|sp], #12", operands);
6247 /* Output a move from an fpu register to arm registers.
6248 OPERANDS[0] is the first registers of an arm register pair.
6249 OPERANDS[1] is an fpu register. */
6252 output_mov_long_double_arm_from_fpu (operands)
6255 int arm_reg0 = REGNO (operands[0]);
6258 if (arm_reg0 == IP_REGNUM)
6261 ops[0] = gen_rtx_REG (SImode, arm_reg0);
6262 ops[1] = gen_rtx_REG (SImode, 1 + arm_reg0);
6263 ops[2] = gen_rtx_REG (SImode, 2 + arm_reg0);
6265 output_asm_insn ("stf%?e\t%1, [%|sp, #-12]!", operands);
6266 output_asm_insn ("ldm%?fd\t%|sp!, {%0, %1, %2}", ops);
6270 /* Output a move from arm registers to arm registers of a long double
6271 OPERANDS[0] is the destination.
6272 OPERANDS[1] is the source. */
6274 output_mov_long_double_arm_from_arm (operands)
6277 /* We have to be careful here because the two might overlap. */
6278 int dest_start = REGNO (operands[0]);
6279 int src_start = REGNO (operands[1]);
6283 if (dest_start < src_start)
6285 for (i = 0; i < 3; i++)
6287 ops[0] = gen_rtx_REG (SImode, dest_start + i);
6288 ops[1] = gen_rtx_REG (SImode, src_start + i);
6289 output_asm_insn ("mov%?\t%0, %1", ops);
6294 for (i = 2; i >= 0; i--)
6296 ops[0] = gen_rtx_REG (SImode, dest_start + i);
6297 ops[1] = gen_rtx_REG (SImode, src_start + i);
6298 output_asm_insn ("mov%?\t%0, %1", ops);
6306 /* Output a move from arm registers to an fpu registers.
6307 OPERANDS[0] is an fpu register.
6308 OPERANDS[1] is the first registers of an arm register pair. */
6311 output_mov_double_fpu_from_arm (operands)
6314 int arm_reg0 = REGNO (operands[1]);
6317 if (arm_reg0 == IP_REGNUM)
6320 ops[0] = gen_rtx_REG (SImode, arm_reg0);
6321 ops[1] = gen_rtx_REG (SImode, 1 + arm_reg0);
6322 output_asm_insn ("stm%?fd\t%|sp!, {%0, %1}", ops);
6323 output_asm_insn ("ldf%?d\t%0, [%|sp], #8", operands);
6327 /* Output a move from an fpu register to arm registers.
6328 OPERANDS[0] is the first registers of an arm register pair.
6329 OPERANDS[1] is an fpu register. */
6332 output_mov_double_arm_from_fpu (operands)
6335 int arm_reg0 = REGNO (operands[0]);
6338 if (arm_reg0 == IP_REGNUM)
6341 ops[0] = gen_rtx_REG (SImode, arm_reg0);
6342 ops[1] = gen_rtx_REG (SImode, 1 + arm_reg0);
6343 output_asm_insn ("stf%?d\t%1, [%|sp, #-8]!", operands);
6344 output_asm_insn ("ldm%?fd\t%|sp!, {%0, %1}", ops);
6348 /* Output a move between double words.
6349 It must be REG<-REG, REG<-CONST_DOUBLE, REG<-CONST_INT, REG<-MEM
6350 or MEM<-REG and all MEMs must be offsettable addresses. */
6353 output_move_double (operands)
6356 enum rtx_code code0 = GET_CODE (operands[0]);
6357 enum rtx_code code1 = GET_CODE (operands[1]);
6362 int reg0 = REGNO (operands[0]);
6364 otherops[0] = gen_rtx_REG (SImode, 1 + reg0);
6368 int reg1 = REGNO (operands[1]);
6369 if (reg1 == IP_REGNUM)
6372 /* Ensure the second source is not overwritten. */
6373 if (reg1 == reg0 + (WORDS_BIG_ENDIAN ? -1 : 1))
6374 output_asm_insn ("mov%?\t%Q0, %Q1\n\tmov%?\t%R0, %R1", operands);
6376 output_asm_insn ("mov%?\t%R0, %R1\n\tmov%?\t%Q0, %Q1", operands);
6378 else if (code1 == CONST_DOUBLE)
6380 if (GET_MODE (operands[1]) == DFmode)
6383 union real_extract u;
6385 memcpy (&u, &CONST_DOUBLE_LOW (operands[1]), sizeof (u));
6386 REAL_VALUE_TO_TARGET_DOUBLE (u.d, l);
6387 otherops[1] = GEN_INT (l[1]);
6388 operands[1] = GEN_INT (l[0]);
6390 else if (GET_MODE (operands[1]) != VOIDmode)
6392 else if (WORDS_BIG_ENDIAN)
6395 otherops[1] = GEN_INT (CONST_DOUBLE_LOW (operands[1]));
6396 operands[1] = GEN_INT (CONST_DOUBLE_HIGH (operands[1]));
6401 otherops[1] = GEN_INT (CONST_DOUBLE_HIGH (operands[1]));
6402 operands[1] = GEN_INT (CONST_DOUBLE_LOW (operands[1]));
6405 output_mov_immediate (operands);
6406 output_mov_immediate (otherops);
6408 else if (code1 == CONST_INT)
6410 #if HOST_BITS_PER_WIDE_INT > 32
6411 /* If HOST_WIDE_INT is more than 32 bits, the intval tells us
6412 what the upper word is. */
6413 if (WORDS_BIG_ENDIAN)
6415 otherops[1] = GEN_INT (ARM_SIGN_EXTEND (INTVAL (operands[1])));
6416 operands[1] = GEN_INT (INTVAL (operands[1]) >> 32);
6420 otherops[1] = GEN_INT (INTVAL (operands[1]) >> 32);
6421 operands[1] = GEN_INT (ARM_SIGN_EXTEND (INTVAL (operands[1])));
6424 /* Sign extend the intval into the high-order word. */
6425 if (WORDS_BIG_ENDIAN)
6427 otherops[1] = operands[1];
6428 operands[1] = (INTVAL (operands[1]) < 0
6429 ? constm1_rtx : const0_rtx);
6432 otherops[1] = INTVAL (operands[1]) < 0 ? constm1_rtx : const0_rtx;
6434 output_mov_immediate (otherops);
6435 output_mov_immediate (operands);
6437 else if (code1 == MEM)
6439 switch (GET_CODE (XEXP (operands[1], 0)))
6442 output_asm_insn ("ldm%?ia\t%m1, %M0", operands);
6446 abort (); /* Should never happen now. */
6450 output_asm_insn ("ldm%?db\t%m1!, %M0", operands);
6454 output_asm_insn ("ldm%?ia\t%m1!, %M0", operands);
6458 abort (); /* Should never happen now. */
6463 output_asm_insn ("adr%?\t%0, %1", operands);
6464 output_asm_insn ("ldm%?ia\t%0, %M0", operands);
6468 if (arm_add_operand (XEXP (XEXP (operands[1], 0), 1),
6469 GET_MODE (XEXP (XEXP (operands[1], 0), 1))))
6471 otherops[0] = operands[0];
6472 otherops[1] = XEXP (XEXP (operands[1], 0), 0);
6473 otherops[2] = XEXP (XEXP (operands[1], 0), 1);
6474 if (GET_CODE (XEXP (operands[1], 0)) == PLUS)
6476 if (GET_CODE (otherops[2]) == CONST_INT)
6478 switch (INTVAL (otherops[2]))
6481 output_asm_insn ("ldm%?db\t%1, %M0", otherops);
6484 output_asm_insn ("ldm%?da\t%1, %M0", otherops);
6487 output_asm_insn ("ldm%?ib\t%1, %M0", otherops);
6490 if (!(const_ok_for_arm (INTVAL (otherops[2]))))
6491 output_asm_insn ("sub%?\t%0, %1, #%n2", otherops);
6493 output_asm_insn ("add%?\t%0, %1, %2", otherops);
6496 output_asm_insn ("add%?\t%0, %1, %2", otherops);
6499 output_asm_insn ("sub%?\t%0, %1, %2", otherops);
6501 return "ldm%?ia\t%0, %M0";
6505 otherops[1] = adj_offsettable_operand (operands[1], 4);
6506 /* Take care of overlapping base/data reg. */
6507 if (reg_mentioned_p (operands[0], operands[1]))
6509 output_asm_insn ("ldr%?\t%0, %1", otherops);
6510 output_asm_insn ("ldr%?\t%0, %1", operands);
6514 output_asm_insn ("ldr%?\t%0, %1", operands);
6515 output_asm_insn ("ldr%?\t%0, %1", otherops);
6521 abort (); /* Constraints should prevent this. */
6523 else if (code0 == MEM && code1 == REG)
6525 if (REGNO (operands[1]) == IP_REGNUM)
6528 switch (GET_CODE (XEXP (operands[0], 0)))
6531 output_asm_insn ("stm%?ia\t%m0, %M1", operands);
6535 abort (); /* Should never happen now. */
6539 output_asm_insn ("stm%?db\t%m0!, %M1", operands);
6543 output_asm_insn ("stm%?ia\t%m0!, %M1", operands);
6547 abort (); /* Should never happen now. */
6551 if (GET_CODE (XEXP (XEXP (operands[0], 0), 1)) == CONST_INT)
6553 switch (INTVAL (XEXP (XEXP (operands[0], 0), 1)))
6556 output_asm_insn ("stm%?db\t%m0, %M1", operands);
6560 output_asm_insn ("stm%?da\t%m0, %M1", operands);
6564 output_asm_insn ("stm%?ib\t%m0, %M1", operands);
6571 otherops[0] = adj_offsettable_operand (operands[0], 4);
6572 otherops[1] = gen_rtx_REG (SImode, 1 + REGNO (operands[1]));
6573 output_asm_insn ("str%?\t%1, %0", operands);
6574 output_asm_insn ("str%?\t%1, %0", otherops);
6578 abort (); /* Constraints should prevent this */
6584 /* Output an arbitrary MOV reg, #n.
6585 OPERANDS[0] is a register. OPERANDS[1] is a const_int. */
6588 output_mov_immediate (operands)
6591 HOST_WIDE_INT n = INTVAL (operands[1]);
6595 /* Try to use one MOV */
6596 if (const_ok_for_arm (n))
6598 output_asm_insn ("mov%?\t%0, %1", operands);
6602 /* Try to use one MVN */
6603 if (const_ok_for_arm (~n))
6605 operands[1] = GEN_INT (~n);
6606 output_asm_insn ("mvn%?\t%0, %1", operands);
6610 /* If all else fails, make it out of ORRs or BICs as appropriate. */
6612 for (i=0; i < 32; i++)
6616 if (n_ones > 16) /* Shorter to use MVN with BIC in this case. */
6617 output_multi_immediate (operands, "mvn%?\t%0, %1", "bic%?\t%0, %0, %1", 1, ~n);
6619 output_multi_immediate (operands, "mov%?\t%0, %1", "orr%?\t%0, %0, %1", 1, n);
6625 /* Output an ADD r, s, #n where n may be too big for one instruction. If
6626 adding zero to one register, output nothing. */
6629 output_add_immediate (operands)
6632 HOST_WIDE_INT n = INTVAL (operands[2]);
6634 if (n != 0 || REGNO (operands[0]) != REGNO (operands[1]))
6637 output_multi_immediate (operands,
6638 "sub%?\t%0, %1, %2", "sub%?\t%0, %0, %2", 2,
6641 output_multi_immediate (operands,
6642 "add%?\t%0, %1, %2", "add%?\t%0, %0, %2", 2,
6649 /* Output a multiple immediate operation.
6650 OPERANDS is the vector of operands referred to in the output patterns.
6651 INSTR1 is the output pattern to use for the first constant.
6652 INSTR2 is the output pattern to use for subsequent constants.
6653 IMMED_OP is the index of the constant slot in OPERANDS.
6654 N is the constant value. */
6657 output_multi_immediate (operands, instr1, instr2, immed_op, n)
6659 const char * instr1;
6660 const char * instr2;
6664 #if HOST_BITS_PER_WIDE_INT > 32
6665 n &= HOST_UINT (0xffffffff);
6670 operands[immed_op] = const0_rtx;
6671 output_asm_insn (instr1, operands); /* Quick and easy output. */
6676 const char * instr = instr1;
6678 /* Note that n is never zero here (which would give no output). */
6679 for (i = 0; i < 32; i += 2)
6683 operands[immed_op] = GEN_INT (n & (255 << i));
6684 output_asm_insn (instr, operands);
6695 /* Return the appropriate ARM instruction for the operation code.
6696 The returned result should not be overwritten. OP is the rtx of the
6697 operation. SHIFT_FIRST_ARG is TRUE if the first argument of the operator
6701 arithmetic_instr (op, shift_first_arg)
6703 int shift_first_arg;
6705 switch (GET_CODE (op))
6711 return shift_first_arg ? "rsb" : "sub";
6728 /* Ensure valid constant shifts and return the appropriate shift mnemonic
6729 for the operation code. The returned result should not be overwritten.
6730 OP is the rtx code of the shift.
6731 On exit, *AMOUNTP will be -1 if the shift is by a register, or a constant
6735 shift_op (op, amountp)
6737 HOST_WIDE_INT *amountp;
6740 enum rtx_code code = GET_CODE (op);
6742 if (GET_CODE (XEXP (op, 1)) == REG || GET_CODE (XEXP (op, 1)) == SUBREG)
6744 else if (GET_CODE (XEXP (op, 1)) == CONST_INT)
6745 *amountp = INTVAL (XEXP (op, 1));
6768 /* We never have to worry about the amount being other than a
6769 power of 2, since this case can never be reloaded from a reg. */
6771 *amountp = int_log2 (*amountp);
6782 /* This is not 100% correct, but follows from the desire to merge
6783 multiplication by a power of 2 with the recognizer for a
6784 shift. >=32 is not a valid shift for "asl", so we must try and
6785 output a shift that produces the correct arithmetical result.
6786 Using lsr #32 is identical except for the fact that the carry bit
6787 is not set correctly if we set the flags; but we never use the
6788 carry bit from such an operation, so we can ignore that. */
6789 if (code == ROTATERT)
6790 *amountp &= 31; /* Rotate is just modulo 32 */
6791 else if (*amountp != (*amountp & 31))
6798 /* Shifts of 0 are no-ops. */
6807 /* Obtain the shift from the POWER of two. */
6808 static HOST_WIDE_INT
6810 HOST_WIDE_INT power;
6812 HOST_WIDE_INT shift = 0;
6814 while ((((HOST_INT (1)) << shift) & power) == 0)
6824 /* Output a .ascii pseudo-op, keeping track of lengths. This is because
6825 /bin/as is horribly restrictive. */
6826 #define MAX_ASCII_LEN 51
6829 output_ascii_pseudo_op (stream, p, len)
6831 const unsigned char * p;
6837 fputs ("\t.ascii\t\"", stream);
6839 for (i = 0; i < len; i++)
6841 register int c = p[i];
6843 if (len_so_far >= MAX_ASCII_LEN)
6845 fputs ("\"\n\t.ascii\t\"", stream);
6852 fputs ("\\t", stream);
6857 fputs ("\\f", stream);
6862 fputs ("\\b", stream);
6867 fputs ("\\r", stream);
6871 case TARGET_NEWLINE:
6872 fputs ("\\n", stream);
6874 if ((c >= ' ' && c <= '~')
6876 /* This is a good place for a line break. */
6877 len_so_far = MAX_ASCII_LEN;
6884 putc ('\\', stream);
6889 if (c >= ' ' && c <= '~')
6896 fprintf (stream, "\\%03o", c);
6903 fputs ("\"\n", stream);
6906 /* Compute a bit mask of which registers need to be
6907 saved on the stack for the current function. */
6909 static unsigned long
6910 arm_compute_save_reg_mask ()
6912 unsigned int save_reg_mask = 0;
6914 unsigned long func_type = arm_current_func_type ();
6916 if (IS_NAKED (func_type))
6917 /* This should never really happen. */
6920 /* If we are creating a stack frame, then we must save the frame pointer,
6921 IP (which will hold the old stack pointer), LR and the PC. */
6922 if (frame_pointer_needed)
6924 (1 << ARM_HARD_FRAME_POINTER_REGNUM)
6929 /* Volatile functions do not return, so there
6930 is no need to save any other registers. */
6931 if (IS_VOLATILE (func_type))
6932 return save_reg_mask;
6934 if (ARM_FUNC_TYPE (func_type) == ARM_FT_ISR)
6936 /* FIQ handlers have registers r8 - r12 banked, so
6937 we only need to check r0 - r7, they must save them. */
6938 for (reg = 0; reg < 8; reg++)
6939 if (regs_ever_live[reg])
6940 save_reg_mask |= (1 << reg);
6944 /* In the normal case we only need to save those registers
6945 which are call saved and which are used by this function. */
6946 for (reg = 0; reg <= 10; reg++)
6947 if (regs_ever_live[reg] && ! call_used_regs [reg])
6948 save_reg_mask |= (1 << reg);
6950 /* Handle the frame pointer as a special case. */
6951 if (! TARGET_APCS_FRAME
6952 && ! frame_pointer_needed
6953 && regs_ever_live[HARD_FRAME_POINTER_REGNUM]
6954 && ! call_used_regs[HARD_FRAME_POINTER_REGNUM])
6955 save_reg_mask |= 1 << HARD_FRAME_POINTER_REGNUM;
6957 /* If we aren't loading the PIC register,
6958 don't stack it even though it may be live. */
6960 && ! TARGET_SINGLE_PIC_BASE
6961 && regs_ever_live[PIC_OFFSET_TABLE_REGNUM])
6962 save_reg_mask |= 1 << PIC_OFFSET_TABLE_REGNUM;
6965 /* Decide if we need to save the link register.
6966 Interrupt routines have their own banked link register,
6967 so they never need to save it.
6968 Otheriwse if we do not use the link register we do not need to save
6969 it. If we are pushing other registers onto the stack however, we
6970 can save an instruction in the epilogue by pushing the link register
6971 now and then popping it back into the PC. This incurs extra memory
6972 accesses though, so we only do it when optimising for size, and only
6973 if we know that we will not need a fancy return sequence. */
6974 if (! IS_INTERRUPT (func_type)
6975 && (regs_ever_live [LR_REGNUM]
6978 && ARM_FUNC_TYPE (func_type) == ARM_FT_NORMAL)))
6979 save_reg_mask |= 1 << LR_REGNUM;
6981 if (cfun->machine->lr_save_eliminated)
6982 save_reg_mask &= ~ (1 << LR_REGNUM);
6984 return save_reg_mask;
6987 /* Generate a function exit sequence. If REALLY_RETURN is true, then do
6988 everything bar the final return instruction. */
6991 output_return_instruction (operand, really_return, reverse)
6996 char conditional[10];
6999 unsigned long live_regs_mask;
7000 unsigned long func_type;
7002 func_type = arm_current_func_type ();
7004 if (IS_NAKED (func_type))
7007 if (IS_VOLATILE (func_type) && TARGET_ABORT_NORETURN)
7009 /* If this function was declared non-returning, and we have found a tail
7010 call, then we have to trust that the called function won't return. */
7015 /* Otherwise, trap an attempted return by aborting. */
7017 ops[1] = gen_rtx_SYMBOL_REF (Pmode, NEED_PLT_RELOC ? "abort(PLT)"
7019 assemble_external_libcall (ops[1]);
7020 output_asm_insn (reverse ? "bl%D0\t%a1" : "bl%d0\t%a1", ops);
7026 if (current_function_calls_alloca && !really_return)
7029 /* Construct the conditional part of the instruction(s) to be emitted. */
7030 sprintf (conditional, "%%?%%%c0", reverse ? 'D' : 'd');
7032 return_used_this_function = 1;
7034 live_regs_mask = arm_compute_save_reg_mask ();
7036 /* On some ARM architectures it is faster to use LDR rather than LDM to
7037 load a single register. On other architectures, the cost is the same.
7038 In 26 bit mode we have to use LDM in order to be able to restore the CPSR. */
7039 if ((live_regs_mask == (1 << LR_REGNUM))
7040 && ! TARGET_INTERWORK
7041 && ! IS_INTERRUPT (func_type)
7042 && (! really_return || TARGET_APCS_32))
7044 if (! really_return)
7045 sprintf (instr, "ldr%s\t%%|lr, [%%|sp], #4", conditional);
7047 sprintf (instr, "ldr%s\t%%|pc, [%%|sp], #4", conditional);
7049 else if (live_regs_mask)
7051 if ((live_regs_mask & (1 << IP_REGNUM)) == (1 << IP_REGNUM))
7052 /* There are two possible reasons for the IP register being saved.
7053 Either a stack frame was created, in which case IP contains the
7054 old stack pointer, or an ISR routine corrupted it. If this in an
7055 ISR routine then just restore IP, otherwise restore IP into SP. */
7056 if (! IS_INTERRUPT (func_type))
7058 live_regs_mask &= ~ (1 << IP_REGNUM);
7059 live_regs_mask |= (1 << SP_REGNUM);
7062 /* Generate the load multiple instruction to restore the registers. */
7063 if (frame_pointer_needed)
7064 sprintf (instr, "ldm%sea\t%%|fp, {", conditional);
7066 sprintf (instr, "ldm%sfd\t%%|sp!, {", conditional);
7068 for (reg = 0; reg <= SP_REGNUM; reg++)
7069 if (live_regs_mask & (1 << reg))
7071 strcat (instr, "%|");
7072 strcat (instr, reg_names[reg]);
7073 strcat (instr, ", ");
7076 if ((live_regs_mask & (1 << LR_REGNUM)) == 0)
7078 /* If we are not restoring the LR register then we will
7079 have added one too many commas to the list above.
7080 Replace it with a closing brace. */
7081 instr [strlen (instr) - 2] = '}';
7085 strcat (instr, "%|");
7087 /* At this point there should only be one or two registers left in
7088 live_regs_mask: always LR, and possibly PC if we created a stack
7089 frame. LR contains the return address. If we do not have any
7090 special requirements for function exit (eg interworking, or ISR)
7091 then we can load this value directly into the PC and save an
7093 if (! TARGET_INTERWORK
7094 && ! IS_INTERRUPT (func_type)
7096 strcat (instr, reg_names [PC_REGNUM]);
7098 strcat (instr, reg_names [LR_REGNUM]);
7100 strcat (instr, (TARGET_APCS_32 || !really_return) ? "}" : "}^");
7105 /* See if we need to generate an extra instruction to
7106 perform the actual function return. */
7107 switch ((int) ARM_FUNC_TYPE (func_type))
7111 output_asm_insn (instr, & operand);
7113 strcpy (instr, "sub");
7114 strcat (instr, conditional);
7115 strcat (instr, "s\t%|pc, %|lr, #4");
7118 case ARM_FT_EXCEPTION:
7119 output_asm_insn (instr, & operand);
7121 strcpy (instr, "mov");
7122 strcat (instr, conditional);
7123 strcat (instr, "s\t%|pc, %|lr");
7126 case ARM_FT_INTERWORKED:
7127 output_asm_insn (instr, & operand);
7129 strcpy (instr, "bx");
7130 strcat (instr, conditional);
7131 strcat (instr, "\t%|lr");
7135 /* The return has already been handled
7136 by loading the LR into the PC. */
7137 if ((live_regs_mask & (1 << LR_REGNUM)) == 0)
7139 output_asm_insn (instr, & operand);
7141 strcpy (instr, "mov");
7142 strcat (instr, conditional);
7143 if (! TARGET_APCS_32)
7144 strcat (instr, "s");
7145 strcat (instr, "\t%|pc, %|lr");
7151 else if (really_return)
7153 switch ((int) ARM_FUNC_TYPE (func_type))
7157 sprintf (instr, "sub%ss\t%%|pc, %%|lr, #4", conditional);
7160 case ARM_FT_INTERWORKED:
7161 sprintf (instr, "bx%s\t%%|lr", conditional);
7164 case ARM_FT_EXCEPTION:
7165 sprintf (instr, "mov%ss\t%%|pc, %%|lr", conditional);
7169 sprintf (instr, "mov%s%s\t%%|pc, %%|lr",
7170 conditional, TARGET_APCS_32 ? "" : "s");
7175 /* Nothing to load off the stack, and
7176 no return instruction to generate. */
7179 output_asm_insn (instr, & operand);
7184 /* Write the function name into the code section, directly preceding
7185 the function prologue.
7187 Code will be output similar to this:
7189 .ascii "arm_poke_function_name", 0
7192 .word 0xff000000 + (t1 - t0)
7193 arm_poke_function_name
7195 stmfd sp!, {fp, ip, lr, pc}
7198 When performing a stack backtrace, code can inspect the value
7199 of 'pc' stored at 'fp' + 0. If the trace function then looks
7200 at location pc - 12 and the top 8 bits are set, then we know
7201 that there is a function name embedded immediately preceding this
7202 location and has length ((pc[-3]) & 0xff000000).
7204 We assume that pc is declared as a pointer to an unsigned long.
7206 It is of no benefit to output the function name if we are assembling
7207 a leaf function. These function types will not contain a stack
7208 backtrace structure, therefore it is not possible to determine the
7212 arm_poke_function_name (stream, name)
7216 unsigned long alignlength;
7217 unsigned long length;
7220 length = strlen (name) + 1;
7221 alignlength = ROUND_UP (length);
7223 ASM_OUTPUT_ASCII (stream, name, length);
7224 ASM_OUTPUT_ALIGN (stream, 2);
7225 x = GEN_INT (HOST_UINT(0xff000000) + alignlength);
7226 ASM_OUTPUT_INT (stream, x);
7229 /* Place some comments into the assembler stream
7230 describing the current function. */
7233 output_arm_prologue (f, frame_size)
7237 unsigned long func_type;
7240 if (arm_ccfsm_state || arm_target_insn)
7243 func_type = arm_current_func_type ();
7245 switch ((int) ARM_FUNC_TYPE (func_type))
7250 case ARM_FT_INTERWORKED:
7251 asm_fprintf (f, "\t%@ Function supports interworking.\n");
7253 case ARM_FT_EXCEPTION_HANDLER:
7254 asm_fprintf (f, "\t%@ C++ Exception Handler.\n");
7257 asm_fprintf (f, "\t%@ Interrupt Service Routine.\n");
7260 asm_fprintf (f, "\t%@ Fast Interrupt Service Routine.\n");
7262 case ARM_FT_EXCEPTION:
7263 asm_fprintf (f, "\t%@ ARM Exception Handler.\n");
7267 if (IS_NAKED (func_type))
7268 asm_fprintf (f, "\t%@ Naked Function: prologue and epilogue provided by programmer.\n");
7270 if (IS_VOLATILE (func_type))
7271 asm_fprintf (f, "\t%@ Volatile: function does not return.\n");
7273 if (IS_NESTED (func_type))
7274 asm_fprintf (f, "\t%@ Nested: function declared inside another function.\n");
7276 asm_fprintf (f, "\t%@ args = %d, pretend = %d, frame = %d\n",
7277 current_function_args_size,
7278 current_function_pretend_args_size, frame_size);
7280 asm_fprintf (f, "\t%@ frame_needed = %d, current_function_anonymous_args = %d\n",
7281 frame_pointer_needed,
7282 current_function_anonymous_args);
7284 if (cfun->machine->lr_save_eliminated)
7285 asm_fprintf (f, "\t%@ link register save eliminated.\n");
7287 #ifdef AOF_ASSEMBLER
7289 asm_fprintf (f, "\tmov\t%r, %r\n", IP_REGNUM, PIC_OFFSET_TABLE_REGNUM);
7292 return_used_this_function = 0;
7296 arm_output_epilogue (really_return)
7300 unsigned long saved_regs_mask;
7301 unsigned long func_type;
7302 /* If we need this, then it will always be at least this much. */
7303 int floats_offset = 12;
7305 int frame_size = get_frame_size ();
7306 FILE * f = asm_out_file;
7307 rtx eh_ofs = cfun->machine->eh_epilogue_sp_ofs;
7309 /* If we have already generated the return instruction
7310 then it is futile to generate anything else. */
7311 if (use_return_insn (FALSE) && return_used_this_function)
7314 func_type = arm_current_func_type ();
7316 if (IS_NAKED (func_type))
7317 /* Naked functions don't have epilogues. */
7320 if (IS_VOLATILE (func_type) && TARGET_ABORT_NORETURN)
7324 /* A volatile function should never return. Call abort. */
7325 op = gen_rtx_SYMBOL_REF (Pmode, NEED_PLT_RELOC ? "abort(PLT)" : "abort");
7326 assemble_external_libcall (op);
7327 output_asm_insn ("bl\t%a0", &op);
7332 if (ARM_FUNC_TYPE (func_type) == ARM_FT_EXCEPTION_HANDLER
7334 /* If we are throwing an exception, then we really must
7335 be doing a return, so we can't tail-call. */
7338 saved_regs_mask = arm_compute_save_reg_mask ();
7340 /* Compute how far away the floats will be. */
7341 for (reg = 0; reg <= LAST_ARM_REGNUM; reg ++)
7342 if (saved_regs_mask & (1 << reg))
7345 if (frame_pointer_needed)
7347 if (arm_fpu_arch == FP_SOFT2)
7349 for (reg = LAST_ARM_FP_REGNUM; reg >= FIRST_ARM_FP_REGNUM; reg--)
7350 if (regs_ever_live[reg] && !call_used_regs[reg])
7352 floats_offset += 12;
7353 asm_fprintf (f, "\tldfe\t%r, [%r, #-%d]\n",
7354 reg, FP_REGNUM, floats_offset);
7359 int start_reg = LAST_ARM_FP_REGNUM;
7361 for (reg = LAST_ARM_FP_REGNUM; reg >= FIRST_ARM_FP_REGNUM; reg--)
7363 if (regs_ever_live[reg] && !call_used_regs[reg])
7365 floats_offset += 12;
7367 /* We can't unstack more than four registers at once. */
7368 if (start_reg - reg == 3)
7370 asm_fprintf (f, "\tlfm\t%r, 4, [%r, #-%d]\n",
7371 reg, FP_REGNUM, floats_offset);
7372 start_reg = reg - 1;
7377 if (reg != start_reg)
7378 asm_fprintf (f, "\tlfm\t%r, %d, [%r, #-%d]\n",
7379 reg + 1, start_reg - reg,
7380 FP_REGNUM, floats_offset);
7381 start_reg = reg - 1;
7385 /* Just in case the last register checked also needs unstacking. */
7386 if (reg != start_reg)
7387 asm_fprintf (f, "\tlfm\t%r, %d, [%r, #-%d]\n",
7388 reg + 1, start_reg - reg,
7389 FP_REGNUM, floats_offset);
7392 /* saved_regs_mask should contain the IP, which at the time of stack
7393 frame generation actually contains the old stack pointer. So a
7394 quick way to unwind the stack is just pop the IP register directly
7395 into the stack pointer. */
7396 if ((saved_regs_mask & (1 << IP_REGNUM)) == 0)
7398 saved_regs_mask &= ~ (1 << IP_REGNUM);
7399 saved_regs_mask |= (1 << SP_REGNUM);
7401 /* There are two registers left in saved_regs_mask - LR and PC. We
7402 only need to restore the LR register (the return address), but to
7403 save time we can load it directly into the PC, unless we need a
7404 special function exit sequence, or we are not really returning. */
7405 if (really_return && ARM_FUNC_TYPE (func_type) == ARM_FT_NORMAL)
7406 /* Delete the LR from the register mask, so that the LR on
7407 the stack is loaded into the PC in the register mask. */
7408 saved_regs_mask &= ~ (1 << LR_REGNUM);
7410 saved_regs_mask &= ~ (1 << PC_REGNUM);
7412 print_multi_reg (f, "ldmea\t%r", FP_REGNUM, saved_regs_mask);
7416 /* Restore stack pointer if necessary. */
7417 if (frame_size + current_function_outgoing_args_size != 0)
7419 operands[0] = operands[1] = stack_pointer_rtx;
7420 operands[2] = GEN_INT (frame_size
7421 + current_function_outgoing_args_size);
7422 output_add_immediate (operands);
7425 if (arm_fpu_arch == FP_SOFT2)
7427 for (reg = FIRST_ARM_FP_REGNUM; reg <= LAST_ARM_FP_REGNUM; reg++)
7428 if (regs_ever_live[reg] && !call_used_regs[reg])
7429 asm_fprintf (f, "\tldfe\t%r, [%r], #12\n",
7434 int start_reg = FIRST_ARM_FP_REGNUM;
7436 for (reg = FIRST_ARM_FP_REGNUM; reg <= LAST_ARM_FP_REGNUM; reg++)
7438 if (regs_ever_live[reg] && !call_used_regs[reg])
7440 if (reg - start_reg == 3)
7442 asm_fprintf (f, "\tlfmfd\t%r, 4, [%r]!\n",
7443 start_reg, SP_REGNUM);
7444 start_reg = reg + 1;
7449 if (reg != start_reg)
7450 asm_fprintf (f, "\tlfmfd\t%r, %d, [%r]!\n",
7451 start_reg, reg - start_reg,
7454 start_reg = reg + 1;
7458 /* Just in case the last register checked also needs unstacking. */
7459 if (reg != start_reg)
7460 asm_fprintf (f, "\tlfmfd\t%r, %d, [%r]!\n",
7461 start_reg, reg - start_reg, SP_REGNUM);
7464 /* If we can, restore the LR into the PC. */
7465 if (ARM_FUNC_TYPE (func_type) == ARM_FT_NORMAL
7467 && current_function_pretend_args_size == 0
7468 && saved_regs_mask & (1 << LR_REGNUM))
7470 saved_regs_mask &= ~ (1 << LR_REGNUM);
7471 saved_regs_mask |= (1 << PC_REGNUM);
7474 /* Load the registers off the stack. If we only have one register
7475 to load use the LDR instruction - it is faster. */
7476 if (saved_regs_mask == (1 << LR_REGNUM))
7478 /* The excpetion handler ignores the LR, so we do
7479 not really need to load it off the stack. */
7481 asm_fprintf (f, "\tadd\t%r, %r, #4\n", SP_REGNUM, SP_REGNUM);
7483 asm_fprintf (f, "\tldr\t%r, [%r], #4\n", LR_REGNUM, SP_REGNUM);
7485 else if (saved_regs_mask)
7486 print_multi_reg (f, "ldmfd\t%r!", SP_REGNUM, saved_regs_mask);
7488 if (current_function_pretend_args_size)
7490 /* Unwind the pre-pushed regs. */
7491 operands[0] = operands[1] = stack_pointer_rtx;
7492 operands[2] = GEN_INT (current_function_pretend_args_size);
7493 output_add_immediate (operands);
7498 if (ARM_FUNC_TYPE (func_type) == ARM_FT_EXCEPTION_HANDLER)
7499 /* Adjust the stack to remove the exception handler stuff. */
7500 asm_fprintf (f, "\tadd\t%r, %r, %r\n", SP_REGNUM, SP_REGNUM,
7504 if (! really_return)
7507 /* Generate the return instruction. */
7508 switch ((int) ARM_FUNC_TYPE (func_type))
7510 case ARM_FT_EXCEPTION_HANDLER:
7511 /* Even in 26-bit mode we do a mov (rather than a movs)
7512 because we don't have the PSR bits set in the address. */
7513 asm_fprintf (f, "\tmov\t%r, %r\n", PC_REGNUM, EXCEPTION_LR_REGNUM);
7518 asm_fprintf (f, "\tsubs\t%r, %r, #4\n", PC_REGNUM, LR_REGNUM);
7521 case ARM_FT_EXCEPTION:
7522 asm_fprintf (f, "\tmovs\t%r, %r\n", PC_REGNUM, LR_REGNUM);
7525 case ARM_FT_INTERWORKED:
7526 asm_fprintf (f, "\tbx\t%r\n", LR_REGNUM);
7530 if (frame_pointer_needed)
7531 /* If we used the frame pointer then the return adddress
7532 will have been loaded off the stack directly into the
7533 PC, so there is no need to issue a MOV instruction
7536 else if (current_function_pretend_args_size == 0
7537 && (saved_regs_mask & (1 << LR_REGNUM)))
7538 /* Similarly we may have been able to load LR into the PC
7539 even if we did not create a stack frame. */
7541 else if (TARGET_APCS_32)
7542 asm_fprintf (f, "\tmov\t%r, %r\n", PC_REGNUM, LR_REGNUM);
7544 asm_fprintf (f, "\tmovs\t%r, %r\n", PC_REGNUM, LR_REGNUM);
7552 output_func_epilogue (frame_size)
7557 /* ??? Probably not safe to set this here, since it assumes that a
7558 function will be emitted as assembly immediately after we generate
7559 RTL for it. This does not happen for inline functions. */
7560 return_used_this_function = 0;
7564 if (use_return_insn (FALSE)
7565 && return_used_this_function
7566 && (frame_size + current_function_outgoing_args_size) != 0
7567 && !frame_pointer_needed)
7570 /* Reset the ARM-specific per-function variables. */
7571 current_function_anonymous_args = 0;
7572 after_arm_reorg = 0;
7576 /* Generate and emit an insn that we will recognize as a push_multi.
7577 Unfortunately, since this insn does not reflect very well the actual
7578 semantics of the operation, we need to annotate the insn for the benefit
7579 of DWARF2 frame unwind information. */
7582 emit_multi_reg_push (mask)
7590 int dwarf_par_index;
7593 for (i = 0; i <= LAST_ARM_REGNUM; i++)
7594 if (mask & (1 << i))
7597 if (num_regs == 0 || num_regs > 16)
7600 /* We don't record the PC in the dwarf frame information. */
7601 num_dwarf_regs = num_regs;
7602 if (mask & (1 << PC_REGNUM))
7605 /* For the body of the insn we are going to generate an UNSPEC in
7606 parallel with several USEs. This allows the insn to be recognised
7607 by the push_multi pattern in the arm.md file. The insn looks
7608 something like this:
7611 (set (mem:BLK (pre_dec:BLK (reg:SI sp)))
7612 (unspec:BLK [(reg:SI r4)] UNSPEC_PUSH_MULT))
7613 (use (reg:SI 11 fp))
7614 (use (reg:SI 12 ip))
7615 (use (reg:SI 14 lr))
7616 (use (reg:SI 15 pc))
7619 For the frame note however, we try to be more explicit and actually
7620 show each register being stored into the stack frame, plus a (single)
7621 decrement of the stack pointer. We do it this way in order to be
7622 friendly to the stack unwinding code, which only wants to see a single
7623 stack decrement per instruction. The RTL we generate for the note looks
7624 something like this:
7627 (set (reg:SI sp) (plus:SI (reg:SI sp) (const_int -20)))
7628 (set (mem:SI (reg:SI sp)) (reg:SI r4))
7629 (set (mem:SI (plus:SI (reg:SI sp) (const_int 4))) (reg:SI fp))
7630 (set (mem:SI (plus:SI (reg:SI sp) (const_int 8))) (reg:SI ip))
7631 (set (mem:SI (plus:SI (reg:SI sp) (const_int 12))) (reg:SI lr))
7634 This sequence is used both by the code to support stack unwinding for
7635 exceptions handlers and the code to generate dwarf2 frame debugging. */
7637 par = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (num_regs));
7638 dwarf = gen_rtx_SEQUENCE (VOIDmode, rtvec_alloc (num_dwarf_regs + 1));
7639 RTX_FRAME_RELATED_P (dwarf) = 1;
7640 dwarf_par_index = 1;
7642 for (i = 0; i <= LAST_ARM_REGNUM; i++)
7644 if (mask & (1 << i))
7646 reg = gen_rtx_REG (SImode, i);
7649 = gen_rtx_SET (VOIDmode,
7650 gen_rtx_MEM (BLKmode,
7651 gen_rtx_PRE_DEC (BLKmode,
7652 stack_pointer_rtx)),
7653 gen_rtx_UNSPEC (BLKmode,
7659 tmp = gen_rtx_SET (VOIDmode,
7660 gen_rtx_MEM (SImode, stack_pointer_rtx),
7662 RTX_FRAME_RELATED_P (tmp) = 1;
7663 XVECEXP (dwarf, 0, dwarf_par_index) = tmp;
7671 for (j = 1, i++; j < num_regs; i++)
7673 if (mask & (1 << i))
7675 reg = gen_rtx_REG (SImode, i);
7677 XVECEXP (par, 0, j) = gen_rtx_USE (VOIDmode, reg);
7681 tmp = gen_rtx_SET (VOIDmode,
7682 gen_rtx_MEM (SImode,
7683 plus_constant (stack_pointer_rtx,
7686 RTX_FRAME_RELATED_P (tmp) = 1;
7687 XVECEXP (dwarf, 0, dwarf_par_index++) = tmp;
7694 par = emit_insn (par);
7696 tmp = gen_rtx_SET (SImode,
7698 gen_rtx_PLUS (SImode,
7700 GEN_INT (-4 * num_regs)));
7701 RTX_FRAME_RELATED_P (tmp) = 1;
7702 XVECEXP (dwarf, 0, 0) = tmp;
7704 REG_NOTES (par) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, dwarf,
7710 emit_sfm (base_reg, count)
7719 par = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
7720 dwarf = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
7721 RTX_FRAME_RELATED_P (dwarf) = 1;
7723 reg = gen_rtx_REG (XFmode, base_reg++);
7726 = gen_rtx_SET (VOIDmode,
7727 gen_rtx_MEM (BLKmode,
7728 gen_rtx_PRE_DEC (BLKmode, stack_pointer_rtx)),
7729 gen_rtx_UNSPEC (BLKmode,
7733 = gen_rtx_SET (VOIDmode,
7734 gen_rtx_MEM (XFmode,
7735 gen_rtx_PRE_DEC (BLKmode, stack_pointer_rtx)),
7737 RTX_FRAME_RELATED_P (tmp) = 1;
7738 XVECEXP (dwarf, 0, count - 1) = tmp;
7740 for (i = 1; i < count; i++)
7742 reg = gen_rtx_REG (XFmode, base_reg++);
7743 XVECEXP (par, 0, i) = gen_rtx_USE (VOIDmode, reg);
7745 tmp = gen_rtx_SET (VOIDmode,
7746 gen_rtx_MEM (XFmode,
7747 gen_rtx_PRE_DEC (BLKmode,
7748 stack_pointer_rtx)),
7750 RTX_FRAME_RELATED_P (tmp) = 1;
7751 XVECEXP (dwarf, 0, count - i - 1) = tmp;
7754 par = emit_insn (par);
7755 REG_NOTES (par) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, dwarf,
7760 /* Generate the prologue instructions for entry into an ARM function. */
7763 arm_expand_prologue ()
7769 unsigned long live_regs_mask;
7770 unsigned long func_type;
7773 func_type = arm_current_func_type ();
7775 /* Naked functions don't have prologues. */
7776 if (IS_NAKED (func_type))
7779 /* Compute which register we will have to save onto the stack. */
7780 live_regs_mask = arm_compute_save_reg_mask ();
7782 ip_rtx = gen_rtx_REG (SImode, IP_REGNUM);
7784 if (frame_pointer_needed)
7786 if (IS_NESTED (func_type))
7788 /* The Static chain register is the same as the IP register
7789 used as a scratch register during stack frame creation.
7790 To get around this need to find somewhere to store IP
7791 whilst the frame is being created. We try the following
7794 1. The last argument register.
7795 2. A slot on the stack above the frame. (This only
7796 works if the function is not a varargs function).
7798 If neither of these places is available, we abort (for now).
7800 Note - we only need to tell the dwarf2 backend about the SP
7801 adjustment in the second variant; the static chain register
7802 doesn't need to be unwound, as it doesn't contain a value
7803 inherited from the caller. */
7805 if (regs_ever_live[3] == 0)
7807 insn = gen_rtx_REG (SImode, 3);
7808 insn = gen_rtx_SET (SImode, insn, ip_rtx);
7809 insn = emit_insn (insn);
7811 else if (current_function_pretend_args_size == 0)
7814 insn = gen_rtx_PRE_DEC (SImode, stack_pointer_rtx);
7815 insn = gen_rtx_MEM (SImode, insn);
7816 insn = gen_rtx_SET (VOIDmode, insn, ip_rtx);
7817 insn = emit_insn (insn);
7821 /* Just tell the dwarf backend that we adjusted SP. */
7822 dwarf = gen_rtx_SET (VOIDmode, stack_pointer_rtx,
7823 gen_rtx_PLUS (SImode, stack_pointer_rtx,
7824 GEN_INT (-fp_offset)));
7825 RTX_FRAME_RELATED_P (insn) = 1;
7826 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
7827 dwarf, REG_NOTES (insn));
7830 /* FIXME - the way to handle this situation is to allow
7831 the pretend args to be dumped onto the stack, then
7832 reuse r3 to save IP. This would involve moving the
7833 copying of SP into IP until after the pretend args
7834 have been dumped, but this is not too hard. */
7835 /* [See e.g. gcc.c-torture/execute/nest-stdar-1.c.] */
7836 error ("Unable to find a temporary location for static chain register");
7841 insn = gen_rtx_PLUS (SImode, stack_pointer_rtx, GEN_INT (fp_offset));
7842 insn = gen_rtx_SET (SImode, ip_rtx, insn);
7845 insn = gen_movsi (ip_rtx, stack_pointer_rtx);
7847 insn = emit_insn (insn);
7848 RTX_FRAME_RELATED_P (insn) = 1;
7851 if (current_function_pretend_args_size)
7853 /* Push the argument registers, or reserve space for them. */
7854 if (current_function_anonymous_args)
7855 insn = emit_multi_reg_push
7856 ((0xf0 >> (current_function_pretend_args_size / 4)) & 0xf);
7859 (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,
7860 GEN_INT (-current_function_pretend_args_size)));
7861 RTX_FRAME_RELATED_P (insn) = 1;
7866 insn = emit_multi_reg_push (live_regs_mask);
7867 RTX_FRAME_RELATED_P (insn) = 1;
7870 if (! IS_VOLATILE (func_type))
7872 /* Save any floating point call-saved registers used by this function. */
7873 if (arm_fpu_arch == FP_SOFT2)
7875 for (reg = LAST_ARM_FP_REGNUM; reg >= FIRST_ARM_FP_REGNUM; reg --)
7876 if (regs_ever_live[reg] && !call_used_regs[reg])
7878 insn = gen_rtx_PRE_DEC (XFmode, stack_pointer_rtx);
7879 insn = gen_rtx_MEM (XFmode, insn);
7880 insn = emit_insn (gen_rtx_SET (VOIDmode, insn,
7881 gen_rtx_REG (XFmode, reg)));
7882 RTX_FRAME_RELATED_P (insn) = 1;
7887 int start_reg = LAST_ARM_FP_REGNUM;
7889 for (reg = LAST_ARM_FP_REGNUM; reg >= FIRST_ARM_FP_REGNUM; reg --)
7891 if (regs_ever_live[reg] && !call_used_regs[reg])
7893 if (start_reg - reg == 3)
7895 insn = emit_sfm (reg, 4);
7896 RTX_FRAME_RELATED_P (insn) = 1;
7897 start_reg = reg - 1;
7902 if (start_reg != reg)
7904 insn = emit_sfm (reg + 1, start_reg - reg);
7905 RTX_FRAME_RELATED_P (insn) = 1;
7907 start_reg = reg - 1;
7911 if (start_reg != reg)
7913 insn = emit_sfm (reg + 1, start_reg - reg);
7914 RTX_FRAME_RELATED_P (insn) = 1;
7919 if (frame_pointer_needed)
7921 /* Create the new frame pointer. */
7922 insn = GEN_INT (-(4 + current_function_pretend_args_size + fp_offset));
7923 insn = emit_insn (gen_addsi3 (hard_frame_pointer_rtx, ip_rtx, insn));
7924 RTX_FRAME_RELATED_P (insn) = 1;
7926 if (IS_NESTED (func_type))
7928 /* Recover the static chain register. */
7929 if (regs_ever_live [3] == 0)
7931 insn = gen_rtx_REG (SImode, 3);
7932 insn = gen_rtx_SET (SImode, ip_rtx, insn);
7933 insn = emit_insn (insn);
7935 else /* if (current_function_pretend_args_size == 0) */
7937 insn = gen_rtx_PLUS (SImode, hard_frame_pointer_rtx, GEN_INT (4));
7938 insn = gen_rtx_MEM (SImode, insn);
7939 insn = gen_rtx_SET (SImode, ip_rtx, insn);
7940 insn = emit_insn (insn);
7945 amount = GEN_INT (-(get_frame_size ()
7946 + current_function_outgoing_args_size));
7948 if (amount != const0_rtx)
7950 /* This add can produce multiple insns for a large constant, so we
7951 need to get tricky. */
7952 rtx last = get_last_insn ();
7953 insn = emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,
7957 last = last ? NEXT_INSN (last) : get_insns ();
7958 RTX_FRAME_RELATED_P (last) = 1;
7960 while (last != insn);
7962 /* If the frame pointer is needed, emit a special barrier that
7963 will prevent the scheduler from moving stores to the frame
7964 before the stack adjustment. */
7965 if (frame_pointer_needed)
7967 rtx unspec = gen_rtx_UNSPEC (SImode,
7968 gen_rtvec (2, stack_pointer_rtx,
7969 hard_frame_pointer_rtx),
7972 insn = emit_insn (gen_rtx_CLOBBER (VOIDmode,
7973 gen_rtx_MEM (BLKmode, unspec)));
7977 /* If we are profiling, make sure no instructions are scheduled before
7978 the call to mcount. Similarly if the user has requested no
7979 scheduling in the prolog. */
7980 if (profile_flag || profile_block_flag || TARGET_NO_SCHED_PRO)
7981 emit_insn (gen_blockage ());
7983 /* If the link register is being kept alive, with the return address in it,
7984 then make sure that it does not get reused by the ce2 pass. */
7985 if ((live_regs_mask & (1 << LR_REGNUM)) == 0)
7987 emit_insn (gen_rtx_USE (VOIDmode, gen_rtx_REG (SImode, LR_REGNUM)));
7988 cfun->machine->lr_save_eliminated = 1;
7992 /* If CODE is 'd', then the X is a condition operand and the instruction
7993 should only be executed if the condition is true.
7994 if CODE is 'D', then the X is a condition operand and the instruction
7995 should only be executed if the condition is false: however, if the mode
7996 of the comparison is CCFPEmode, then always execute the instruction -- we
7997 do this because in these circumstances !GE does not necessarily imply LT;
7998 in these cases the instruction pattern will take care to make sure that
7999 an instruction containing %d will follow, thereby undoing the effects of
8000 doing this instruction unconditionally.
8001 If CODE is 'N' then X is a floating point operand that must be negated
8003 If CODE is 'B' then output a bitwise inverted value of X (a const int).
8004 If X is a REG and CODE is `M', output a ldm/stm style multi-reg. */
8007 arm_print_operand (stream, x, code)
8015 fputs (ASM_COMMENT_START, stream);
8019 fputs (user_label_prefix, stream);
8023 fputs (REGISTER_PREFIX, stream);
8027 if (arm_ccfsm_state == 3 || arm_ccfsm_state == 4)
8029 if (TARGET_THUMB || current_insn_predicate != NULL)
8032 fputs (arm_condition_codes[arm_current_cc], stream);
8034 else if (current_insn_predicate)
8036 enum arm_cond_code code;
8041 code = get_arm_condition_code (current_insn_predicate);
8042 fputs (arm_condition_codes[code], stream);
8049 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
8050 r = REAL_VALUE_NEGATE (r);
8051 fprintf (stream, "%s", fp_const_from_val (&r));
8056 if (GET_CODE (x) == CONST_INT)
8059 val = ARM_SIGN_EXTEND (~INTVAL (x));
8060 fprintf (stream, HOST_WIDE_INT_PRINT_DEC, val);
8065 output_addr_const (stream, x);
8070 fprintf (stream, "%s", arithmetic_instr (x, 1));
8074 fprintf (stream, "%s", arithmetic_instr (x, 0));
8080 const char * shift = shift_op (x, &val);
8084 fprintf (stream, ", %s ", shift_op (x, &val));
8086 arm_print_operand (stream, XEXP (x, 1), 0);
8089 fputc ('#', stream);
8090 fprintf (stream, HOST_WIDE_INT_PRINT_DEC, val);
8096 /* An explanation of the 'Q', 'R' and 'H' register operands:
8098 In a pair of registers containing a DI or DF value the 'Q'
8099 operand returns the register number of the register containing
8100 the least signficant part of the value. The 'R' operand returns
8101 the register number of the register containing the most
8102 significant part of the value.
8104 The 'H' operand returns the higher of the two register numbers.
8105 On a run where WORDS_BIG_ENDIAN is true the 'H' operand is the
8106 same as the 'Q' operand, since the most signficant part of the
8107 value is held in the lower number register. The reverse is true
8108 on systems where WORDS_BIG_ENDIAN is false.
8110 The purpose of these operands is to distinguish between cases
8111 where the endian-ness of the values is important (for example
8112 when they are added together), and cases where the endian-ness
8113 is irrelevant, but the order of register operations is important.
8114 For example when loading a value from memory into a register
8115 pair, the endian-ness does not matter. Provided that the value
8116 from the lower memory address is put into the lower numbered
8117 register, and the value from the higher address is put into the
8118 higher numbered register, the load will work regardless of whether
8119 the value being loaded is big-wordian or little-wordian. The
8120 order of the two register loads can matter however, if the address
8121 of the memory location is actually held in one of the registers
8122 being overwritten by the load. */
8124 if (REGNO (x) > LAST_ARM_REGNUM)
8126 asm_fprintf (stream, "%r", REGNO (x) + (WORDS_BIG_ENDIAN ? 1 : 0));
8130 if (REGNO (x) > LAST_ARM_REGNUM)
8132 asm_fprintf (stream, "%r", REGNO (x) + (WORDS_BIG_ENDIAN ? 0 : 1));
8136 if (REGNO (x) > LAST_ARM_REGNUM)
8138 asm_fprintf (stream, "%r", REGNO (x) + 1);
8142 asm_fprintf (stream, "%r",
8143 GET_CODE (XEXP (x, 0)) == REG
8144 ? REGNO (XEXP (x, 0)) : REGNO (XEXP (XEXP (x, 0), 0)));
8148 asm_fprintf (stream, "{%r-%r}",
8150 REGNO (x) + NUM_REGS (GET_MODE (x)) - 1);
8158 fputs (arm_condition_codes[get_arm_condition_code (x)],
8161 fputs (thumb_condition_code (x, 0), stream);
8169 fputs (arm_condition_codes[ARM_INVERSE_CONDITION_CODE
8170 (get_arm_condition_code (x))],
8173 fputs (thumb_condition_code (x, 1), stream);
8180 if (GET_CODE (x) == REG)
8181 asm_fprintf (stream, "%r", REGNO (x));
8182 else if (GET_CODE (x) == MEM)
8184 output_memory_reference_mode = GET_MODE (x);
8185 output_address (XEXP (x, 0));
8187 else if (GET_CODE (x) == CONST_DOUBLE)
8188 fprintf (stream, "#%s", fp_immediate_constant (x));
8189 else if (GET_CODE (x) == NEG)
8190 abort (); /* This should never happen now. */
8193 fputc ('#', stream);
8194 output_addr_const (stream, x);
8199 /* A finite state machine takes care of noticing whether or not instructions
8200 can be conditionally executed, and thus decrease execution time and code
8201 size by deleting branch instructions. The fsm is controlled by
8202 final_prescan_insn, and controls the actions of ASM_OUTPUT_OPCODE. */
8204 /* The state of the fsm controlling condition codes are:
8205 0: normal, do nothing special
8206 1: make ASM_OUTPUT_OPCODE not output this instruction
8207 2: make ASM_OUTPUT_OPCODE not output this instruction
8208 3: make instructions conditional
8209 4: make instructions conditional
8211 State transitions (state->state by whom under condition):
8212 0 -> 1 final_prescan_insn if the `target' is a label
8213 0 -> 2 final_prescan_insn if the `target' is an unconditional branch
8214 1 -> 3 ASM_OUTPUT_OPCODE after not having output the conditional branch
8215 2 -> 4 ASM_OUTPUT_OPCODE after not having output the conditional branch
8216 3 -> 0 ASM_OUTPUT_INTERNAL_LABEL if the `target' label is reached
8217 (the target label has CODE_LABEL_NUMBER equal to arm_target_label).
8218 4 -> 0 final_prescan_insn if the `target' unconditional branch is reached
8219 (the target insn is arm_target_insn).
8221 If the jump clobbers the conditions then we use states 2 and 4.
8223 A similar thing can be done with conditional return insns.
8225 XXX In case the `target' is an unconditional branch, this conditionalising
8226 of the instructions always reduces code size, but not always execution
8227 time. But then, I want to reduce the code size to somewhere near what
8228 /bin/cc produces. */
8230 /* Returns the index of the ARM condition code string in
8231 `arm_condition_codes'. COMPARISON should be an rtx like
8232 `(eq (...) (...))'. */
8234 static enum arm_cond_code
8235 get_arm_condition_code (comparison)
8238 enum machine_mode mode = GET_MODE (XEXP (comparison, 0));
8240 register enum rtx_code comp_code = GET_CODE (comparison);
8242 if (GET_MODE_CLASS (mode) != MODE_CC)
8243 mode = SELECT_CC_MODE (comp_code, XEXP (comparison, 0),
8244 XEXP (comparison, 1));
8248 case CC_DNEmode: code = ARM_NE; goto dominance;
8249 case CC_DEQmode: code = ARM_EQ; goto dominance;
8250 case CC_DGEmode: code = ARM_GE; goto dominance;
8251 case CC_DGTmode: code = ARM_GT; goto dominance;
8252 case CC_DLEmode: code = ARM_LE; goto dominance;
8253 case CC_DLTmode: code = ARM_LT; goto dominance;
8254 case CC_DGEUmode: code = ARM_CS; goto dominance;
8255 case CC_DGTUmode: code = ARM_HI; goto dominance;
8256 case CC_DLEUmode: code = ARM_LS; goto dominance;
8257 case CC_DLTUmode: code = ARM_CC;
8260 if (comp_code != EQ && comp_code != NE)
8263 if (comp_code == EQ)
8264 return ARM_INVERSE_CONDITION_CODE (code);
8270 case NE: return ARM_NE;
8271 case EQ: return ARM_EQ;
8272 case GE: return ARM_PL;
8273 case LT: return ARM_MI;
8280 case NE: return ARM_NE;
8281 case EQ: return ARM_EQ;
8287 /* These encodings assume that AC=1 in the FPA system control
8288 byte. This allows us to handle all cases except UNEQ and
8292 case GE: return ARM_GE;
8293 case GT: return ARM_GT;
8294 case LE: return ARM_LS;
8295 case LT: return ARM_MI;
8296 case NE: return ARM_NE;
8297 case EQ: return ARM_EQ;
8298 case ORDERED: return ARM_VC;
8299 case UNORDERED: return ARM_VS;
8300 case UNLT: return ARM_LT;
8301 case UNLE: return ARM_LE;
8302 case UNGT: return ARM_HI;
8303 case UNGE: return ARM_PL;
8304 /* UNEQ and LTGT do not have a representation. */
8305 case UNEQ: /* Fall through. */
8306 case LTGT: /* Fall through. */
8313 case NE: return ARM_NE;
8314 case EQ: return ARM_EQ;
8315 case GE: return ARM_LE;
8316 case GT: return ARM_LT;
8317 case LE: return ARM_GE;
8318 case LT: return ARM_GT;
8319 case GEU: return ARM_LS;
8320 case GTU: return ARM_CC;
8321 case LEU: return ARM_CS;
8322 case LTU: return ARM_HI;
8329 case LTU: return ARM_CS;
8330 case GEU: return ARM_CC;
8337 case NE: return ARM_NE;
8338 case EQ: return ARM_EQ;
8339 case GE: return ARM_GE;
8340 case GT: return ARM_GT;
8341 case LE: return ARM_LE;
8342 case LT: return ARM_LT;
8343 case GEU: return ARM_CS;
8344 case GTU: return ARM_HI;
8345 case LEU: return ARM_LS;
8346 case LTU: return ARM_CC;
8358 arm_final_prescan_insn (insn)
8361 /* BODY will hold the body of INSN. */
8362 register rtx body = PATTERN (insn);
8364 /* This will be 1 if trying to repeat the trick, and things need to be
8365 reversed if it appears to fail. */
8368 /* JUMP_CLOBBERS will be one implies that the conditions if a branch is
8369 taken are clobbered, even if the rtl suggests otherwise. It also
8370 means that we have to grub around within the jump expression to find
8371 out what the conditions are when the jump isn't taken. */
8372 int jump_clobbers = 0;
8374 /* If we start with a return insn, we only succeed if we find another one. */
8375 int seeking_return = 0;
8377 /* START_INSN will hold the insn from where we start looking. This is the
8378 first insn after the following code_label if REVERSE is true. */
8379 rtx start_insn = insn;
8381 /* If in state 4, check if the target branch is reached, in order to
8382 change back to state 0. */
8383 if (arm_ccfsm_state == 4)
8385 if (insn == arm_target_insn)
8387 arm_target_insn = NULL;
8388 arm_ccfsm_state = 0;
8393 /* If in state 3, it is possible to repeat the trick, if this insn is an
8394 unconditional branch to a label, and immediately following this branch
8395 is the previous target label which is only used once, and the label this
8396 branch jumps to is not too far off. */
8397 if (arm_ccfsm_state == 3)
8399 if (simplejump_p (insn))
8401 start_insn = next_nonnote_insn (start_insn);
8402 if (GET_CODE (start_insn) == BARRIER)
8404 /* XXX Isn't this always a barrier? */
8405 start_insn = next_nonnote_insn (start_insn);
8407 if (GET_CODE (start_insn) == CODE_LABEL
8408 && CODE_LABEL_NUMBER (start_insn) == arm_target_label
8409 && LABEL_NUSES (start_insn) == 1)
8414 else if (GET_CODE (body) == RETURN)
8416 start_insn = next_nonnote_insn (start_insn);
8417 if (GET_CODE (start_insn) == BARRIER)
8418 start_insn = next_nonnote_insn (start_insn);
8419 if (GET_CODE (start_insn) == CODE_LABEL
8420 && CODE_LABEL_NUMBER (start_insn) == arm_target_label
8421 && LABEL_NUSES (start_insn) == 1)
8433 if (arm_ccfsm_state != 0 && !reverse)
8435 if (GET_CODE (insn) != JUMP_INSN)
8438 /* This jump might be paralleled with a clobber of the condition codes
8439 the jump should always come first */
8440 if (GET_CODE (body) == PARALLEL && XVECLEN (body, 0) > 0)
8441 body = XVECEXP (body, 0, 0);
8444 /* If this is a conditional return then we don't want to know */
8445 if (GET_CODE (body) == SET && GET_CODE (SET_DEST (body)) == PC
8446 && GET_CODE (SET_SRC (body)) == IF_THEN_ELSE
8447 && (GET_CODE (XEXP (SET_SRC (body), 1)) == RETURN
8448 || GET_CODE (XEXP (SET_SRC (body), 2)) == RETURN))
8453 || (GET_CODE (body) == SET && GET_CODE (SET_DEST (body)) == PC
8454 && GET_CODE (SET_SRC (body)) == IF_THEN_ELSE))
8457 int fail = FALSE, succeed = FALSE;
8458 /* Flag which part of the IF_THEN_ELSE is the LABEL_REF. */
8459 int then_not_else = TRUE;
8460 rtx this_insn = start_insn, label = 0;
8462 /* If the jump cannot be done with one instruction, we cannot
8463 conditionally execute the instruction in the inverse case. */
8464 if (get_attr_conds (insn) == CONDS_JUMP_CLOB)
8470 /* Register the insn jumped to. */
8473 if (!seeking_return)
8474 label = XEXP (SET_SRC (body), 0);
8476 else if (GET_CODE (XEXP (SET_SRC (body), 1)) == LABEL_REF)
8477 label = XEXP (XEXP (SET_SRC (body), 1), 0);
8478 else if (GET_CODE (XEXP (SET_SRC (body), 2)) == LABEL_REF)
8480 label = XEXP (XEXP (SET_SRC (body), 2), 0);
8481 then_not_else = FALSE;
8483 else if (GET_CODE (XEXP (SET_SRC (body), 1)) == RETURN)
8485 else if (GET_CODE (XEXP (SET_SRC (body), 2)) == RETURN)
8488 then_not_else = FALSE;
8493 /* See how many insns this branch skips, and what kind of insns. If all
8494 insns are okay, and the label or unconditional branch to the same
8495 label is not too far away, succeed. */
8496 for (insns_skipped = 0;
8497 !fail && !succeed && insns_skipped++ < max_insns_skipped;)
8501 this_insn = next_nonnote_insn (this_insn);
8505 switch (GET_CODE (this_insn))
8508 /* Succeed if it is the target label, otherwise fail since
8509 control falls in from somewhere else. */
8510 if (this_insn == label)
8514 arm_ccfsm_state = 2;
8515 this_insn = next_nonnote_insn (this_insn);
8518 arm_ccfsm_state = 1;
8526 /* Succeed if the following insn is the target label.
8528 If return insns are used then the last insn in a function
8529 will be a barrier. */
8530 this_insn = next_nonnote_insn (this_insn);
8531 if (this_insn && this_insn == label)
8535 arm_ccfsm_state = 2;
8536 this_insn = next_nonnote_insn (this_insn);
8539 arm_ccfsm_state = 1;
8547 /* If using 32-bit addresses the cc is not preserved over
8551 /* Succeed if the following insn is the target label,
8552 or if the following two insns are a barrier and
8553 the target label. */
8554 this_insn = next_nonnote_insn (this_insn);
8555 if (this_insn && GET_CODE (this_insn) == BARRIER)
8556 this_insn = next_nonnote_insn (this_insn);
8558 if (this_insn && this_insn == label
8559 && insns_skipped < max_insns_skipped)
8563 arm_ccfsm_state = 2;
8564 this_insn = next_nonnote_insn (this_insn);
8567 arm_ccfsm_state = 1;
8576 /* If this is an unconditional branch to the same label, succeed.
8577 If it is to another label, do nothing. If it is conditional,
8579 /* XXX Probably, the tests for SET and the PC are unnecessary. */
8581 scanbody = PATTERN (this_insn);
8582 if (GET_CODE (scanbody) == SET
8583 && GET_CODE (SET_DEST (scanbody)) == PC)
8585 if (GET_CODE (SET_SRC (scanbody)) == LABEL_REF
8586 && XEXP (SET_SRC (scanbody), 0) == label && !reverse)
8588 arm_ccfsm_state = 2;
8591 else if (GET_CODE (SET_SRC (scanbody)) == IF_THEN_ELSE)
8594 /* Fail if a conditional return is undesirable (eg on a
8595 StrongARM), but still allow this if optimizing for size. */
8596 else if (GET_CODE (scanbody) == RETURN
8597 && !use_return_insn (TRUE)
8600 else if (GET_CODE (scanbody) == RETURN
8603 arm_ccfsm_state = 2;
8606 else if (GET_CODE (scanbody) == PARALLEL)
8608 switch (get_attr_conds (this_insn))
8618 fail = TRUE; /* Unrecognized jump (eg epilogue). */
8623 /* Instructions using or affecting the condition codes make it
8625 scanbody = PATTERN (this_insn);
8626 if (!(GET_CODE (scanbody) == SET
8627 || GET_CODE (scanbody) == PARALLEL)
8628 || get_attr_conds (this_insn) != CONDS_NOCOND)
8638 if ((!seeking_return) && (arm_ccfsm_state == 1 || reverse))
8639 arm_target_label = CODE_LABEL_NUMBER (label);
8640 else if (seeking_return || arm_ccfsm_state == 2)
8642 while (this_insn && GET_CODE (PATTERN (this_insn)) == USE)
8644 this_insn = next_nonnote_insn (this_insn);
8645 if (this_insn && (GET_CODE (this_insn) == BARRIER
8646 || GET_CODE (this_insn) == CODE_LABEL))
8651 /* Oh, dear! we ran off the end.. give up */
8652 recog (PATTERN (insn), insn, NULL);
8653 arm_ccfsm_state = 0;
8654 arm_target_insn = NULL;
8657 arm_target_insn = this_insn;
8666 get_arm_condition_code (XEXP (XEXP (XEXP (SET_SRC (body),
8668 if (GET_CODE (XEXP (XEXP (SET_SRC (body), 0), 0)) == AND)
8669 arm_current_cc = ARM_INVERSE_CONDITION_CODE (arm_current_cc);
8670 if (GET_CODE (XEXP (SET_SRC (body), 0)) == NE)
8671 arm_current_cc = ARM_INVERSE_CONDITION_CODE (arm_current_cc);
8675 /* If REVERSE is true, ARM_CURRENT_CC needs to be inverted from
8678 arm_current_cc = get_arm_condition_code (XEXP (SET_SRC (body),
8682 if (reverse || then_not_else)
8683 arm_current_cc = ARM_INVERSE_CONDITION_CODE (arm_current_cc);
8686 /* Restore recog_data (getting the attributes of other insns can
8687 destroy this array, but final.c assumes that it remains intact
8688 across this call; since the insn has been recognized already we
8689 call recog direct). */
8690 recog (PATTERN (insn), insn, NULL);
8695 arm_regno_class (regno)
8700 if (regno == STACK_POINTER_REGNUM)
8702 if (regno == CC_REGNUM)
8709 if ( regno <= LAST_ARM_REGNUM
8710 || regno == FRAME_POINTER_REGNUM
8711 || regno == ARG_POINTER_REGNUM)
8712 return GENERAL_REGS;
8714 if (regno == CC_REGNUM)
8720 /* Handle a special case when computing the offset
8721 of an argument from the frame pointer. */
8723 arm_debugger_arg_offset (value, addr)
8729 /* We are only interested if dbxout_parms() failed to compute the offset. */
8733 /* We can only cope with the case where the address is held in a register. */
8734 if (GET_CODE (addr) != REG)
8737 /* If we are using the frame pointer to point at the argument, then
8738 an offset of 0 is correct. */
8739 if (REGNO (addr) == (unsigned) HARD_FRAME_POINTER_REGNUM)
8742 /* If we are using the stack pointer to point at the
8743 argument, then an offset of 0 is correct. */
8744 if ((TARGET_THUMB || !frame_pointer_needed)
8745 && REGNO (addr) == SP_REGNUM)
8748 /* Oh dear. The argument is pointed to by a register rather
8749 than being held in a register, or being stored at a known
8750 offset from the frame pointer. Since GDB only understands
8751 those two kinds of argument we must translate the address
8752 held in the register into an offset from the frame pointer.
8753 We do this by searching through the insns for the function
8754 looking to see where this register gets its value. If the
8755 register is initialised from the frame pointer plus an offset
8756 then we are in luck and we can continue, otherwise we give up.
8758 This code is exercised by producing debugging information
8759 for a function with arguments like this:
8761 double func (double a, double b, int c, double d) {return d;}
8763 Without this code the stab for parameter 'd' will be set to
8764 an offset of 0 from the frame pointer, rather than 8. */
8766 /* The if() statement says:
8768 If the insn is a normal instruction
8769 and if the insn is setting the value in a register
8770 and if the register being set is the register holding the address of the argument
8771 and if the address is computing by an addition
8772 that involves adding to a register
8773 which is the frame pointer
8778 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
8780 if ( GET_CODE (insn) == INSN
8781 && GET_CODE (PATTERN (insn)) == SET
8782 && REGNO (XEXP (PATTERN (insn), 0)) == REGNO (addr)
8783 && GET_CODE (XEXP (PATTERN (insn), 1)) == PLUS
8784 && GET_CODE (XEXP (XEXP (PATTERN (insn), 1), 0)) == REG
8785 && REGNO (XEXP (XEXP (PATTERN (insn), 1), 0)) == (unsigned) HARD_FRAME_POINTER_REGNUM
8786 && GET_CODE (XEXP (XEXP (PATTERN (insn), 1), 1)) == CONST_INT
8789 value = INTVAL (XEXP (XEXP (PATTERN (insn), 1), 1));
8798 warning ("Unable to compute real location of stacked parameter");
8799 value = 8; /* XXX magic hack */
8805 #define def_builtin(NAME, TYPE, CODE) \
8806 builtin_function ((NAME), (TYPE), (CODE), BUILT_IN_MD, NULL)
8809 arm_init_builtins ()
8811 tree endlink = void_list_node;
8812 tree int_endlink = tree_cons (NULL_TREE, integer_type_node, endlink);
8813 tree pchar_type_node = build_pointer_type (char_type_node);
8815 tree int_ftype_int, void_ftype_pchar;
8817 /* void func (void *) */
8819 = build_function_type (void_type_node,
8820 tree_cons (NULL_TREE, pchar_type_node, endlink));
8822 /* int func (int) */
8824 = build_function_type (integer_type_node, int_endlink);
8826 /* Initialize arm V5 builtins. */
8828 def_builtin ("__builtin_clz", int_ftype_int, ARM_BUILTIN_CLZ);
8830 /* Initialize arm V5E builtins. */
8832 def_builtin ("__builtin_prefetch", void_ftype_pchar,
8833 ARM_BUILTIN_PREFETCH);
8836 /* Expand an expression EXP that calls a built-in function,
8837 with result going to TARGET if that's convenient
8838 (and in mode MODE if that's convenient).
8839 SUBTARGET may be used as the target for computing one of EXP's operands.
8840 IGNORE is nonzero if the value is to be ignored. */
8843 arm_expand_builtin (exp, target, subtarget, mode, ignore)
8846 rtx subtarget ATTRIBUTE_UNUSED;
8847 enum machine_mode mode ATTRIBUTE_UNUSED;
8848 int ignore ATTRIBUTE_UNUSED;
8850 enum insn_code icode;
8851 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
8852 tree arglist = TREE_OPERAND (exp, 1);
8855 enum machine_mode tmode, mode0;
8856 int fcode = DECL_FUNCTION_CODE (fndecl);
8863 case ARM_BUILTIN_CLZ:
8864 icode = CODE_FOR_clz;
8865 arg0 = TREE_VALUE (arglist);
8866 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
8867 tmode = insn_data[icode].operand[0].mode;
8868 mode0 = insn_data[icode].operand[1].mode;
8870 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
8871 op0 = copy_to_mode_reg (mode0, op0);
8873 || GET_MODE (target) != tmode
8874 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
8875 target = gen_reg_rtx (tmode);
8876 pat = GEN_FCN (icode) (target, op0);
8882 case ARM_BUILTIN_PREFETCH:
8883 icode = CODE_FOR_prefetch;
8884 arg0 = TREE_VALUE (arglist);
8885 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
8887 op0 = gen_rtx_MEM (SImode, copy_to_mode_reg (Pmode, op0));
8889 pat = GEN_FCN (icode) (op0);
8896 /* @@@ Should really do something sensible here. */
8900 /* Recursively search through all of the blocks in a function
8901 checking to see if any of the variables created in that
8902 function match the RTX called 'orig'. If they do then
8903 replace them with the RTX called 'new'. */
8906 replace_symbols_in_block (block, orig, new)
8911 for (; block; block = BLOCK_CHAIN (block))
8915 if (!TREE_USED (block))
8918 for (sym = BLOCK_VARS (block); sym; sym = TREE_CHAIN (sym))
8920 if ( (DECL_NAME (sym) == 0 && TREE_CODE (sym) != TYPE_DECL)
8921 || DECL_IGNORED_P (sym)
8922 || TREE_CODE (sym) != VAR_DECL
8923 || DECL_EXTERNAL (sym)
8924 || !rtx_equal_p (DECL_RTL (sym), orig)
8928 DECL_RTL (sym) = new;
8931 replace_symbols_in_block (BLOCK_SUBBLOCKS (block), orig, new);
8935 /* Return the number (counting from 0) of the least significant set
8941 number_of_first_bit_set (mask)
8947 (mask & (1 << bit)) == 0;
8954 /* Generate code to return from a thumb function.
8955 If 'reg_containing_return_addr' is -1, then the return address is
8956 actually on the stack, at the stack pointer. */
8958 thumb_exit (f, reg_containing_return_addr, eh_ofs)
8960 int reg_containing_return_addr;
8963 unsigned regs_available_for_popping;
8964 unsigned regs_to_pop;
8970 int restore_a4 = FALSE;
8972 /* Compute the registers we need to pop. */
8976 /* There is an assumption here, that if eh_ofs is not NULL, the
8977 normal return address will have been pushed. */
8978 if (reg_containing_return_addr == -1 || eh_ofs)
8980 /* When we are generating a return for __builtin_eh_return,
8981 reg_containing_return_addr must specify the return regno. */
8982 if (eh_ofs && reg_containing_return_addr == -1)
8985 regs_to_pop |= 1 << LR_REGNUM;
8989 if (TARGET_BACKTRACE)
8991 /* Restore the (ARM) frame pointer and stack pointer. */
8992 regs_to_pop |= (1 << ARM_HARD_FRAME_POINTER_REGNUM) | (1 << SP_REGNUM);
8996 /* If there is nothing to pop then just emit the BX instruction and
8998 if (pops_needed == 0)
9001 asm_fprintf (f, "\tadd\t%r, %r\n", SP_REGNUM, REGNO (eh_ofs));
9003 asm_fprintf (f, "\tbx\t%r\n", reg_containing_return_addr);
9006 /* Otherwise if we are not supporting interworking and we have not created
9007 a backtrace structure and the function was not entered in ARM mode then
9008 just pop the return address straight into the PC. */
9009 else if (!TARGET_INTERWORK
9010 && !TARGET_BACKTRACE
9011 && !is_called_in_ARM_mode (current_function_decl))
9015 asm_fprintf (f, "\tadd\t%r, #4\n", SP_REGNUM);
9016 asm_fprintf (f, "\tadd\t%r, %r\n", SP_REGNUM, REGNO (eh_ofs));
9017 asm_fprintf (f, "\tbx\t%r\n", reg_containing_return_addr);
9020 asm_fprintf (f, "\tpop\t{%r}\n", PC_REGNUM);
9025 /* Find out how many of the (return) argument registers we can corrupt. */
9026 regs_available_for_popping = 0;
9028 /* If returning via __builtin_eh_return, the bottom three registers
9029 all contain information needed for the return. */
9035 /* If we can deduce the registers used from the function's
9036 return value. This is more reliable that examining
9037 regs_ever_live[] because that will be set if the register is
9038 ever used in the function, not just if the register is used
9039 to hold a return value. */
9041 if (current_function_return_rtx != 0)
9042 mode = GET_MODE (current_function_return_rtx);
9045 mode = DECL_MODE (DECL_RESULT (current_function_decl));
9047 size = GET_MODE_SIZE (mode);
9051 /* In a void function we can use any argument register.
9052 In a function that returns a structure on the stack
9053 we can use the second and third argument registers. */
9054 if (mode == VOIDmode)
9055 regs_available_for_popping =
9056 (1 << ARG_REGISTER (1))
9057 | (1 << ARG_REGISTER (2))
9058 | (1 << ARG_REGISTER (3));
9060 regs_available_for_popping =
9061 (1 << ARG_REGISTER (2))
9062 | (1 << ARG_REGISTER (3));
9065 regs_available_for_popping =
9066 (1 << ARG_REGISTER (2))
9067 | (1 << ARG_REGISTER (3));
9069 regs_available_for_popping =
9070 (1 << ARG_REGISTER (3));
9073 /* Match registers to be popped with registers into which we pop them. */
9074 for (available = regs_available_for_popping,
9075 required = regs_to_pop;
9076 required != 0 && available != 0;
9077 available &= ~(available & - available),
9078 required &= ~(required & - required))
9081 /* If we have any popping registers left over, remove them. */
9083 regs_available_for_popping &= ~available;
9085 /* Otherwise if we need another popping register we can use
9086 the fourth argument register. */
9087 else if (pops_needed)
9089 /* If we have not found any free argument registers and
9090 reg a4 contains the return address, we must move it. */
9091 if (regs_available_for_popping == 0
9092 && reg_containing_return_addr == LAST_ARG_REGNUM)
9094 asm_fprintf (f, "\tmov\t%r, %r\n", LR_REGNUM, LAST_ARG_REGNUM);
9095 reg_containing_return_addr = LR_REGNUM;
9099 /* Register a4 is being used to hold part of the return value,
9100 but we have dire need of a free, low register. */
9103 asm_fprintf (f, "\tmov\t%r, %r\n",IP_REGNUM, LAST_ARG_REGNUM);
9106 if (reg_containing_return_addr != LAST_ARG_REGNUM)
9108 /* The fourth argument register is available. */
9109 regs_available_for_popping |= 1 << LAST_ARG_REGNUM;
9115 /* Pop as many registers as we can. */
9116 thumb_pushpop (f, regs_available_for_popping, FALSE);
9118 /* Process the registers we popped. */
9119 if (reg_containing_return_addr == -1)
9121 /* The return address was popped into the lowest numbered register. */
9122 regs_to_pop &= ~(1 << LR_REGNUM);
9124 reg_containing_return_addr =
9125 number_of_first_bit_set (regs_available_for_popping);
9127 /* Remove this register for the mask of available registers, so that
9128 the return address will not be corrupted by futher pops. */
9129 regs_available_for_popping &= ~(1 << reg_containing_return_addr);
9132 /* If we popped other registers then handle them here. */
9133 if (regs_available_for_popping)
9137 /* Work out which register currently contains the frame pointer. */
9138 frame_pointer = number_of_first_bit_set (regs_available_for_popping);
9140 /* Move it into the correct place. */
9141 asm_fprintf (f, "\tmov\t%r, %r\n",
9142 ARM_HARD_FRAME_POINTER_REGNUM, frame_pointer);
9144 /* (Temporarily) remove it from the mask of popped registers. */
9145 regs_available_for_popping &= ~(1 << frame_pointer);
9146 regs_to_pop &= ~(1 << ARM_HARD_FRAME_POINTER_REGNUM);
9148 if (regs_available_for_popping)
9152 /* We popped the stack pointer as well,
9153 find the register that contains it. */
9154 stack_pointer = number_of_first_bit_set (regs_available_for_popping);
9156 /* Move it into the stack register. */
9157 asm_fprintf (f, "\tmov\t%r, %r\n", SP_REGNUM, stack_pointer);
9159 /* At this point we have popped all necessary registers, so
9160 do not worry about restoring regs_available_for_popping
9161 to its correct value:
9163 assert (pops_needed == 0)
9164 assert (regs_available_for_popping == (1 << frame_pointer))
9165 assert (regs_to_pop == (1 << STACK_POINTER)) */
9169 /* Since we have just move the popped value into the frame
9170 pointer, the popping register is available for reuse, and
9171 we know that we still have the stack pointer left to pop. */
9172 regs_available_for_popping |= (1 << frame_pointer);
9176 /* If we still have registers left on the stack, but we no longer have
9177 any registers into which we can pop them, then we must move the return
9178 address into the link register and make available the register that
9180 if (regs_available_for_popping == 0 && pops_needed > 0)
9182 regs_available_for_popping |= 1 << reg_containing_return_addr;
9184 asm_fprintf (f, "\tmov\t%r, %r\n", LR_REGNUM,
9185 reg_containing_return_addr);
9187 reg_containing_return_addr = LR_REGNUM;
9190 /* If we have registers left on the stack then pop some more.
9191 We know that at most we will want to pop FP and SP. */
9192 if (pops_needed > 0)
9197 thumb_pushpop (f, regs_available_for_popping, FALSE);
9199 /* We have popped either FP or SP.
9200 Move whichever one it is into the correct register. */
9201 popped_into = number_of_first_bit_set (regs_available_for_popping);
9202 move_to = number_of_first_bit_set (regs_to_pop);
9204 asm_fprintf (f, "\tmov\t%r, %r\n", move_to, popped_into);
9206 regs_to_pop &= ~(1 << move_to);
9211 /* If we still have not popped everything then we must have only
9212 had one register available to us and we are now popping the SP. */
9213 if (pops_needed > 0)
9217 thumb_pushpop (f, regs_available_for_popping, FALSE);
9219 popped_into = number_of_first_bit_set (regs_available_for_popping);
9221 asm_fprintf (f, "\tmov\t%r, %r\n", SP_REGNUM, popped_into);
9223 assert (regs_to_pop == (1 << STACK_POINTER))
9224 assert (pops_needed == 1)
9228 /* If necessary restore the a4 register. */
9231 if (reg_containing_return_addr != LR_REGNUM)
9233 asm_fprintf (f, "\tmov\t%r, %r\n", LR_REGNUM, LAST_ARG_REGNUM);
9234 reg_containing_return_addr = LR_REGNUM;
9237 asm_fprintf (f, "\tmov\t%r, %r\n", LAST_ARG_REGNUM, IP_REGNUM);
9241 asm_fprintf (f, "\tadd\t%r, %r\n", SP_REGNUM, REGNO (eh_ofs));
9243 /* Return to caller. */
9244 asm_fprintf (f, "\tbx\t%r\n", reg_containing_return_addr);
9247 /* Emit code to push or pop registers to or from the stack. */
9249 thumb_pushpop (f, mask, push)
9255 int lo_mask = mask & 0xFF;
9257 if (lo_mask == 0 && !push && (mask & (1 << 15)))
9259 /* Special case. Do not generate a POP PC statement here, do it in
9261 thumb_exit (f, -1, NULL_RTX);
9265 fprintf (f, "\t%s\t{", push ? "push" : "pop");
9267 /* Look at the low registers first. */
9268 for (regno = 0; regno <= LAST_LO_REGNUM; regno++, lo_mask >>= 1)
9272 asm_fprintf (f, "%r", regno);
9274 if ((lo_mask & ~1) != 0)
9279 if (push && (mask & (1 << LR_REGNUM)))
9281 /* Catch pushing the LR. */
9285 asm_fprintf (f, "%r", LR_REGNUM);
9287 else if (!push && (mask & (1 << PC_REGNUM)))
9289 /* Catch popping the PC. */
9290 if (TARGET_INTERWORK || TARGET_BACKTRACE)
9292 /* The PC is never poped directly, instead
9293 it is popped into r3 and then BX is used. */
9296 thumb_exit (f, -1, NULL_RTX);
9305 asm_fprintf (f, "%r", PC_REGNUM);
9313 thumb_final_prescan_insn (insn)
9316 if (flag_print_asm_name)
9317 asm_fprintf (asm_out_file, "%@ 0x%04x\n",
9318 INSN_ADDRESSES (INSN_UID (insn)));
9322 thumb_shiftable_const (val)
9323 unsigned HOST_WIDE_INT val;
9325 unsigned HOST_WIDE_INT mask = 0xff;
9328 if (val == 0) /* XXX */
9331 for (i = 0; i < 25; i++)
9332 if ((val & (mask << i)) == val)
9338 /* Returns non-zero if the current function contains,
9339 or might contain a far jump. */
9341 thumb_far_jump_used_p (int in_prologue)
9345 /* This test is only important for leaf functions. */
9346 /* assert (!leaf_function_p ()); */
9348 /* If we have already decided that far jumps may be used,
9349 do not bother checking again, and always return true even if
9350 it turns out that they are not being used. Once we have made
9351 the decision that far jumps are present (and that hence the link
9352 register will be pushed onto the stack) we cannot go back on it. */
9353 if (cfun->machine->far_jump_used)
9356 /* If this function is not being called from the prologue/epilogue
9357 generation code then it must be being called from the
9358 INITIAL_ELIMINATION_OFFSET macro. */
9361 /* In this case we know that we are being asked about the elimination
9362 of the arg pointer register. If that register is not being used,
9363 then there are no arguments on the stack, and we do not have to
9364 worry that a far jump might force the prologue to push the link
9365 register, changing the stack offsets. In this case we can just
9366 return false, since the presence of far jumps in the function will
9367 not affect stack offsets.
9369 If the arg pointer is live (or if it was live, but has now been
9370 eliminated and so set to dead) then we do have to test to see if
9371 the function might contain a far jump. This test can lead to some
9372 false negatives, since before reload is completed, then length of
9373 branch instructions is not known, so gcc defaults to returning their
9374 longest length, which in turn sets the far jump attribute to true.
9376 A false negative will not result in bad code being generated, but it
9377 will result in a needless push and pop of the link register. We
9378 hope that this does not occur too often. */
9379 if (regs_ever_live [ARG_POINTER_REGNUM])
9380 cfun->machine->arg_pointer_live = 1;
9381 else if (!cfun->machine->arg_pointer_live)
9385 /* Check to see if the function contains a branch
9386 insn with the far jump attribute set. */
9387 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
9389 if (GET_CODE (insn) == JUMP_INSN
9390 /* Ignore tablejump patterns. */
9391 && GET_CODE (PATTERN (insn)) != ADDR_VEC
9392 && GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC
9393 && get_attr_far_jump (insn) == FAR_JUMP_YES
9396 /* Record the fact that we have decied that
9397 the function does use far jumps. */
9398 cfun->machine->far_jump_used = 1;
9406 /* Return non-zero if FUNC must be entered in ARM mode. */
9408 is_called_in_ARM_mode (func)
9411 if (TREE_CODE (func) != FUNCTION_DECL)
9414 /* Ignore the problem about functions whoes address is taken. */
9415 if (TARGET_CALLEE_INTERWORKING && TREE_PUBLIC (func))
9419 return lookup_attribute ("interfacearm", DECL_MACHINE_ATTRIBUTES (func)) != NULL_TREE;
9425 /* The bits which aren't usefully expanded as rtl. */
9428 thumb_unexpanded_epilogue ()
9431 int live_regs_mask = 0;
9432 int high_regs_pushed = 0;
9433 int leaf_function = leaf_function_p ();
9435 rtx eh_ofs = cfun->machine->eh_epilogue_sp_ofs;
9437 if (return_used_this_function)
9440 for (regno = 0; regno <= LAST_LO_REGNUM; regno++)
9441 if (regs_ever_live[regno] && !call_used_regs[regno]
9442 && !(TARGET_SINGLE_PIC_BASE && (regno == arm_pic_register)))
9443 live_regs_mask |= 1 << regno;
9445 for (regno = 8; regno < 13; regno++)
9447 if (regs_ever_live[regno] && !call_used_regs[regno]
9448 && !(TARGET_SINGLE_PIC_BASE && (regno == arm_pic_register)))
9452 /* The prolog may have pushed some high registers to use as
9453 work registers. eg the testuite file:
9454 gcc/testsuite/gcc/gcc.c-torture/execute/complex-2.c
9455 compiles to produce:
9456 push {r4, r5, r6, r7, lr}
9460 as part of the prolog. We have to undo that pushing here. */
9462 if (high_regs_pushed)
9464 int mask = live_regs_mask;
9470 /* If we can deduce the registers used from the function's return value.
9471 This is more reliable that examining regs_ever_live[] because that
9472 will be set if the register is ever used in the function, not just if
9473 the register is used to hold a return value. */
9475 if (current_function_return_rtx != 0)
9476 mode = GET_MODE (current_function_return_rtx);
9479 mode = DECL_MODE (DECL_RESULT (current_function_decl));
9481 size = GET_MODE_SIZE (mode);
9483 /* Unless we are returning a type of size > 12 register r3 is
9489 /* Oh dear! We have no low registers into which we can pop
9492 ("no low registers available for popping high registers");
9494 for (next_hi_reg = 8; next_hi_reg < 13; next_hi_reg++)
9495 if (regs_ever_live[next_hi_reg] && !call_used_regs[next_hi_reg]
9496 && !(TARGET_SINGLE_PIC_BASE && (next_hi_reg == arm_pic_register)))
9499 while (high_regs_pushed)
9501 /* Find lo register(s) into which the high register(s) can
9503 for (regno = 0; regno <= LAST_LO_REGNUM; regno++)
9505 if (mask & (1 << regno))
9507 if (high_regs_pushed == 0)
9511 mask &= (2 << regno) - 1; /* A noop if regno == 8 */
9513 /* Pop the values into the low register(s). */
9514 thumb_pushpop (asm_out_file, mask, 0);
9516 /* Move the value(s) into the high registers. */
9517 for (regno = 0; regno <= LAST_LO_REGNUM; regno++)
9519 if (mask & (1 << regno))
9521 asm_fprintf (asm_out_file, "\tmov\t%r, %r\n", next_hi_reg,
9524 for (next_hi_reg++; next_hi_reg < 13; next_hi_reg++)
9525 if (regs_ever_live[next_hi_reg]
9526 && !call_used_regs[next_hi_reg]
9527 && !(TARGET_SINGLE_PIC_BASE
9528 && (next_hi_reg == arm_pic_register)))
9535 had_to_push_lr = (live_regs_mask || !leaf_function
9536 || thumb_far_jump_used_p (1));
9538 if (TARGET_BACKTRACE
9539 && ((live_regs_mask & 0xFF) == 0)
9540 && regs_ever_live [LAST_ARG_REGNUM] != 0)
9542 /* The stack backtrace structure creation code had to
9543 push R7 in order to get a work register, so we pop
9545 live_regs_mask |= (1 << LAST_LO_REGNUM);
9548 if (current_function_pretend_args_size == 0 || TARGET_BACKTRACE)
9551 && !is_called_in_ARM_mode (current_function_decl)
9553 live_regs_mask |= 1 << PC_REGNUM;
9555 /* Either no argument registers were pushed or a backtrace
9556 structure was created which includes an adjusted stack
9557 pointer, so just pop everything. */
9559 thumb_pushpop (asm_out_file, live_regs_mask, FALSE);
9562 thumb_exit (asm_out_file, 2, eh_ofs);
9563 /* We have either just popped the return address into the
9564 PC or it is was kept in LR for the entire function or
9565 it is still on the stack because we do not want to
9566 return by doing a pop {pc}. */
9567 else if ((live_regs_mask & (1 << PC_REGNUM)) == 0)
9568 thumb_exit (asm_out_file,
9570 && is_called_in_ARM_mode (current_function_decl)) ?
9571 -1 : LR_REGNUM, NULL_RTX);
9575 /* Pop everything but the return address. */
9576 live_regs_mask &= ~(1 << PC_REGNUM);
9579 thumb_pushpop (asm_out_file, live_regs_mask, FALSE);
9582 /* Get the return address into a temporary register. */
9583 thumb_pushpop (asm_out_file, 1 << LAST_ARG_REGNUM, 0);
9585 /* Remove the argument registers that were pushed onto the stack. */
9586 asm_fprintf (asm_out_file, "\tadd\t%r, %r, #%d\n",
9587 SP_REGNUM, SP_REGNUM,
9588 current_function_pretend_args_size);
9591 thumb_exit (asm_out_file, 2, eh_ofs);
9593 thumb_exit (asm_out_file,
9594 had_to_push_lr ? LAST_ARG_REGNUM : LR_REGNUM, NULL_RTX);
9600 /* Functions to save and restore machine-specific function data. */
9603 arm_mark_machine_status (p)
9604 struct function * p;
9606 machine_function *machine = p->machine;
9609 ggc_mark_rtx (machine->eh_epilogue_sp_ofs);
9613 arm_init_machine_status (p)
9614 struct function * p;
9617 (machine_function *) xcalloc (1, sizeof (machine_function));
9619 #if ARM_FT_UNKNOWWN != 0
9620 ((machine_function *) p->machine)->func_type = ARM_FT_UNKNOWN;
9625 arm_free_machine_status (p)
9626 struct function * p;
9635 /* Return an RTX indicating where the return address to the
9636 calling function can be found. */
9638 arm_return_addr (count, frame)
9640 rtx frame ATTRIBUTE_UNUSED;
9646 return get_hard_reg_initial_val (Pmode, LR_REGNUM);
9649 rtx lr = gen_rtx_AND (Pmode, gen_rtx_REG (Pmode, LR_REGNUM),
9650 GEN_INT (RETURN_ADDR_MASK26));
9651 return get_func_hard_reg_initial_val (cfun, lr);
9655 /* Do anything needed before RTL is emitted for each function. */
9657 arm_init_expanders ()
9659 /* Arrange to initialize and mark the machine per-function status. */
9660 init_machine_status = arm_init_machine_status;
9661 mark_machine_status = arm_mark_machine_status;
9662 free_machine_status = arm_free_machine_status;
9665 /* Generate the rest of a function's prologue. */
9667 thumb_expand_prologue ()
9669 HOST_WIDE_INT amount = (get_frame_size ()
9670 + current_function_outgoing_args_size);
9671 unsigned long func_type;
9673 func_type = arm_current_func_type ();
9675 /* Naked functions don't have prologues. */
9676 if (IS_NAKED (func_type))
9679 if (IS_INTERRUPT (func_type))
9681 error ("Interrupt Service Routines cannot be coded in Thumb mode.");
9685 if (frame_pointer_needed)
9686 emit_insn (gen_movsi (hard_frame_pointer_rtx, stack_pointer_rtx));
9690 amount = ROUND_UP (amount);
9693 emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,
9694 GEN_INT (-amount)));
9700 /* The stack decrement is too big for an immediate value in a single
9701 insn. In theory we could issue multiple subtracts, but after
9702 three of them it becomes more space efficient to place the full
9703 value in the constant pool and load into a register. (Also the
9704 ARM debugger really likes to see only one stack decrement per
9705 function). So instead we look for a scratch register into which
9706 we can load the decrement, and then we subtract this from the
9707 stack pointer. Unfortunately on the thumb the only available
9708 scratch registers are the argument registers, and we cannot use
9709 these as they may hold arguments to the function. Instead we
9710 attempt to locate a call preserved register which is used by this
9711 function. If we can find one, then we know that it will have
9712 been pushed at the start of the prologue and so we can corrupt
9714 for (regno = LAST_ARG_REGNUM + 1; regno <= LAST_LO_REGNUM; regno++)
9715 if (regs_ever_live[regno]
9716 && !call_used_regs[regno] /* Paranoia */
9717 && !(TARGET_SINGLE_PIC_BASE && (regno == arm_pic_register))
9718 && !(frame_pointer_needed
9719 && (regno == THUMB_HARD_FRAME_POINTER_REGNUM)))
9722 if (regno > LAST_LO_REGNUM) /* Very unlikely */
9724 rtx spare = gen_rtx (REG, SImode, IP_REGNUM);
9726 /* Choose an arbitary, non-argument low register. */
9727 reg = gen_rtx (REG, SImode, LAST_LO_REGNUM);
9729 /* Save it by copying it into a high, scratch register. */
9730 emit_insn (gen_movsi (spare, reg));
9732 /* Decrement the stack. */
9733 emit_insn (gen_movsi (reg, GEN_INT (-amount)));
9734 emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,
9737 /* Restore the low register's original value. */
9738 emit_insn (gen_movsi (reg, spare));
9740 /* Emit a USE of the restored scratch register, so that flow
9741 analysis will not consider the restore redundant. The
9742 register won't be used again in this function and isn't
9743 restored by the epilogue. */
9744 emit_insn (gen_rtx_USE (VOIDmode, reg));
9748 reg = gen_rtx (REG, SImode, regno);
9750 emit_insn (gen_movsi (reg, GEN_INT (-amount)));
9751 emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,
9757 if (profile_flag || profile_block_flag || TARGET_NO_SCHED_PRO)
9758 emit_insn (gen_blockage ());
9762 thumb_expand_epilogue ()
9764 HOST_WIDE_INT amount = (get_frame_size ()
9765 + current_function_outgoing_args_size);
9767 /* Naked functions don't have prologues. */
9768 if (IS_NAKED (arm_current_func_type ()))
9771 if (frame_pointer_needed)
9772 emit_insn (gen_movsi (stack_pointer_rtx, hard_frame_pointer_rtx));
9775 amount = ROUND_UP (amount);
9778 emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,
9782 /* r3 is always free in the epilogue. */
9783 rtx reg = gen_rtx (REG, SImode, LAST_ARG_REGNUM);
9785 emit_insn (gen_movsi (reg, GEN_INT (amount)));
9786 emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, reg));
9790 /* Emit a USE (stack_pointer_rtx), so that
9791 the stack adjustment will not be deleted. */
9792 emit_insn (gen_rtx_USE (VOIDmode, stack_pointer_rtx));
9794 if (profile_flag || profile_block_flag || TARGET_NO_SCHED_PRO)
9795 emit_insn (gen_blockage ());
9799 output_thumb_prologue (f)
9802 int live_regs_mask = 0;
9803 int high_regs_pushed = 0;
9806 if (IS_NAKED (arm_current_func_type ()))
9809 if (is_called_in_ARM_mode (current_function_decl))
9813 if (GET_CODE (DECL_RTL (current_function_decl)) != MEM)
9815 if (GET_CODE (XEXP (DECL_RTL (current_function_decl), 0)) != SYMBOL_REF)
9817 name = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
9819 /* Generate code sequence to switch us into Thumb mode. */
9820 /* The .code 32 directive has already been emitted by
9821 ASM_DECLARE_FUNCTION_NAME. */
9822 asm_fprintf (f, "\torr\t%r, %r, #1\n", IP_REGNUM, PC_REGNUM);
9823 asm_fprintf (f, "\tbx\t%r\n", IP_REGNUM);
9825 /* Generate a label, so that the debugger will notice the
9826 change in instruction sets. This label is also used by
9827 the assembler to bypass the ARM code when this function
9828 is called from a Thumb encoded function elsewhere in the
9829 same file. Hence the definition of STUB_NAME here must
9830 agree with the definition in gas/config/tc-arm.c */
9832 #define STUB_NAME ".real_start_of"
9834 asm_fprintf (f, "\t.code\t16\n");
9836 if (arm_dllexport_name_p (name))
9837 name = arm_strip_name_encoding (name);
9839 asm_fprintf (f, "\t.globl %s%U%s\n", STUB_NAME, name);
9840 asm_fprintf (f, "\t.thumb_func\n");
9841 asm_fprintf (f, "%s%U%s:\n", STUB_NAME, name);
9844 if (current_function_pretend_args_size)
9846 if (current_function_anonymous_args)
9850 asm_fprintf (f, "\tpush\t{");
9852 num_pushes = NUM_INTS (current_function_pretend_args_size);
9854 for (regno = LAST_ARG_REGNUM + 1 - num_pushes;
9855 regno <= LAST_ARG_REGNUM;
9857 asm_fprintf (f, "%r%s", regno,
9858 regno == LAST_ARG_REGNUM ? "" : ", ");
9860 asm_fprintf (f, "}\n");
9863 asm_fprintf (f, "\tsub\t%r, %r, #%d\n",
9864 SP_REGNUM, SP_REGNUM,
9865 current_function_pretend_args_size);
9868 for (regno = 0; regno <= LAST_LO_REGNUM; regno++)
9869 if (regs_ever_live[regno] && !call_used_regs[regno]
9870 && !(TARGET_SINGLE_PIC_BASE && (regno == arm_pic_register)))
9871 live_regs_mask |= 1 << regno;
9873 if (live_regs_mask || !leaf_function_p () || thumb_far_jump_used_p (1))
9874 live_regs_mask |= 1 << LR_REGNUM;
9876 if (TARGET_BACKTRACE)
9879 int work_register = 0;
9882 /* We have been asked to create a stack backtrace structure.
9883 The code looks like this:
9887 0 sub SP, #16 Reserve space for 4 registers.
9888 2 push {R7} Get a work register.
9889 4 add R7, SP, #20 Get the stack pointer before the push.
9890 6 str R7, [SP, #8] Store the stack pointer (before reserving the space).
9891 8 mov R7, PC Get hold of the start of this code plus 12.
9892 10 str R7, [SP, #16] Store it.
9893 12 mov R7, FP Get hold of the current frame pointer.
9894 14 str R7, [SP, #4] Store it.
9895 16 mov R7, LR Get hold of the current return address.
9896 18 str R7, [SP, #12] Store it.
9897 20 add R7, SP, #16 Point at the start of the backtrace structure.
9898 22 mov FP, R7 Put this value into the frame pointer. */
9900 if ((live_regs_mask & 0xFF) == 0)
9902 /* See if the a4 register is free. */
9904 if (regs_ever_live [LAST_ARG_REGNUM] == 0)
9905 work_register = LAST_ARG_REGNUM;
9906 else /* We must push a register of our own */
9907 live_regs_mask |= (1 << LAST_LO_REGNUM);
9910 if (work_register == 0)
9912 /* Select a register from the list that will be pushed to
9913 use as our work register. */
9914 for (work_register = (LAST_LO_REGNUM + 1); work_register--;)
9915 if ((1 << work_register) & live_regs_mask)
9920 (f, "\tsub\t%r, %r, #16\t%@ Create stack backtrace structure\n",
9921 SP_REGNUM, SP_REGNUM);
9924 thumb_pushpop (f, live_regs_mask, 1);
9926 for (offset = 0, wr = 1 << 15; wr != 0; wr >>= 1)
9927 if (wr & live_regs_mask)
9930 asm_fprintf (f, "\tadd\t%r, %r, #%d\n", work_register, SP_REGNUM,
9931 offset + 16 + current_function_pretend_args_size);
9933 asm_fprintf (f, "\tstr\t%r, [%r, #%d]\n", work_register, SP_REGNUM,
9936 /* Make sure that the instruction fetching the PC is in the right place
9937 to calculate "start of backtrace creation code + 12". */
9940 asm_fprintf (f, "\tmov\t%r, %r\n", work_register, PC_REGNUM);
9941 asm_fprintf (f, "\tstr\t%r, [%r, #%d]\n", work_register, SP_REGNUM,
9943 asm_fprintf (f, "\tmov\t%r, %r\n", work_register,
9944 ARM_HARD_FRAME_POINTER_REGNUM);
9945 asm_fprintf (f, "\tstr\t%r, [%r, #%d]\n", work_register, SP_REGNUM,
9950 asm_fprintf (f, "\tmov\t%r, %r\n", work_register,
9951 ARM_HARD_FRAME_POINTER_REGNUM);
9952 asm_fprintf (f, "\tstr\t%r, [%r, #%d]\n", work_register, SP_REGNUM,
9954 asm_fprintf (f, "\tmov\t%r, %r\n", work_register, PC_REGNUM);
9955 asm_fprintf (f, "\tstr\t%r, [%r, #%d]\n", work_register, SP_REGNUM,
9959 asm_fprintf (f, "\tmov\t%r, %r\n", work_register, LR_REGNUM);
9960 asm_fprintf (f, "\tstr\t%r, [%r, #%d]\n", work_register, SP_REGNUM,
9962 asm_fprintf (f, "\tadd\t%r, %r, #%d\n", work_register, SP_REGNUM,
9964 asm_fprintf (f, "\tmov\t%r, %r\t\t%@ Backtrace structure created\n",
9965 ARM_HARD_FRAME_POINTER_REGNUM, work_register);
9967 else if (live_regs_mask)
9968 thumb_pushpop (f, live_regs_mask, 1);
9970 for (regno = 8; regno < 13; regno++)
9972 if (regs_ever_live[regno] && !call_used_regs[regno]
9973 && !(TARGET_SINGLE_PIC_BASE && (regno == arm_pic_register)))
9977 if (high_regs_pushed)
9979 int pushable_regs = 0;
9980 int mask = live_regs_mask & 0xff;
9983 for (next_hi_reg = 12; next_hi_reg > LAST_LO_REGNUM; next_hi_reg--)
9985 if (regs_ever_live[next_hi_reg] && !call_used_regs[next_hi_reg]
9986 && !(TARGET_SINGLE_PIC_BASE
9987 && (next_hi_reg == arm_pic_register)))
9991 pushable_regs = mask;
9993 if (pushable_regs == 0)
9995 /* Desperation time -- this probably will never happen. */
9996 if (regs_ever_live[LAST_ARG_REGNUM]
9997 || !call_used_regs[LAST_ARG_REGNUM])
9998 asm_fprintf (f, "\tmov\t%r, %r\n", IP_REGNUM, LAST_ARG_REGNUM);
9999 mask = 1 << LAST_ARG_REGNUM;
10002 while (high_regs_pushed > 0)
10004 for (regno = LAST_LO_REGNUM; regno >= 0; regno--)
10006 if (mask & (1 << regno))
10008 asm_fprintf (f, "\tmov\t%r, %r\n", regno, next_hi_reg);
10010 high_regs_pushed--;
10012 if (high_regs_pushed)
10013 for (next_hi_reg--; next_hi_reg > LAST_LO_REGNUM;
10016 if (regs_ever_live[next_hi_reg]
10017 && !call_used_regs[next_hi_reg]
10018 && !(TARGET_SINGLE_PIC_BASE
10019 && (next_hi_reg == arm_pic_register)))
10024 mask &= ~((1 << regno) - 1);
10030 thumb_pushpop (f, mask, 1);
10033 if (pushable_regs == 0
10034 && (regs_ever_live[LAST_ARG_REGNUM]
10035 || !call_used_regs[LAST_ARG_REGNUM]))
10036 asm_fprintf (f, "\tmov\t%r, %r\n", LAST_ARG_REGNUM, IP_REGNUM);
10040 /* Handle the case of a double word load into a low register from
10041 a computed memory address. The computed address may involve a
10042 register which is overwritten by the load. */
10045 thumb_load_double_from_address (operands)
10054 if (GET_CODE (operands[0]) != REG)
10057 if (GET_CODE (operands[1]) != MEM)
10060 /* Get the memory address. */
10061 addr = XEXP (operands[1], 0);
10063 /* Work out how the memory address is computed. */
10064 switch (GET_CODE (addr))
10067 operands[2] = gen_rtx (MEM, SImode,
10068 plus_constant (XEXP (operands[1], 0), 4));
10070 if (REGNO (operands[0]) == REGNO (addr))
10072 output_asm_insn ("ldr\t%H0, %2", operands);
10073 output_asm_insn ("ldr\t%0, %1", operands);
10077 output_asm_insn ("ldr\t%0, %1", operands);
10078 output_asm_insn ("ldr\t%H0, %2", operands);
10083 /* Compute <address> + 4 for the high order load. */
10084 operands[2] = gen_rtx (MEM, SImode,
10085 plus_constant (XEXP (operands[1], 0), 4));
10087 output_asm_insn ("ldr\t%0, %1", operands);
10088 output_asm_insn ("ldr\t%H0, %2", operands);
10092 arg1 = XEXP (addr, 0);
10093 arg2 = XEXP (addr, 1);
10095 if (CONSTANT_P (arg1))
10096 base = arg2, offset = arg1;
10098 base = arg1, offset = arg2;
10100 if (GET_CODE (base) != REG)
10103 /* Catch the case of <address> = <reg> + <reg> */
10104 if (GET_CODE (offset) == REG)
10106 int reg_offset = REGNO (offset);
10107 int reg_base = REGNO (base);
10108 int reg_dest = REGNO (operands[0]);
10110 /* Add the base and offset registers together into the
10111 higher destination register. */
10112 asm_fprintf (asm_out_file, "\tadd\t%r, %r, %r",
10113 reg_dest + 1, reg_base, reg_offset);
10115 /* Load the lower destination register from the address in
10116 the higher destination register. */
10117 asm_fprintf (asm_out_file, "\tldr\t%r, [%r, #0]",
10118 reg_dest, reg_dest + 1);
10120 /* Load the higher destination register from its own address
10122 asm_fprintf (asm_out_file, "\tldr\t%r, [%r, #4]",
10123 reg_dest + 1, reg_dest + 1);
10127 /* Compute <address> + 4 for the high order load. */
10128 operands[2] = gen_rtx (MEM, SImode,
10129 plus_constant (XEXP (operands[1], 0), 4));
10131 /* If the computed address is held in the low order register
10132 then load the high order register first, otherwise always
10133 load the low order register first. */
10134 if (REGNO (operands[0]) == REGNO (base))
10136 output_asm_insn ("ldr\t%H0, %2", operands);
10137 output_asm_insn ("ldr\t%0, %1", operands);
10141 output_asm_insn ("ldr\t%0, %1", operands);
10142 output_asm_insn ("ldr\t%H0, %2", operands);
10148 /* With no registers to worry about we can just load the value
10150 operands[2] = gen_rtx (MEM, SImode,
10151 plus_constant (XEXP (operands[1], 0), 4));
10153 output_asm_insn ("ldr\t%H0, %2", operands);
10154 output_asm_insn ("ldr\t%0, %1", operands);
10167 thumb_output_move_mem_multiple (n, operands)
10176 if (REGNO (operands[4]) > REGNO (operands[5]))
10179 operands[4] = operands[5];
10182 output_asm_insn ("ldmia\t%1!, {%4, %5}", operands);
10183 output_asm_insn ("stmia\t%0!, {%4, %5}", operands);
10187 if (REGNO (operands[4]) > REGNO (operands[5]))
10190 operands[4] = operands[5];
10193 if (REGNO (operands[5]) > REGNO (operands[6]))
10196 operands[5] = operands[6];
10199 if (REGNO (operands[4]) > REGNO (operands[5]))
10202 operands[4] = operands[5];
10206 output_asm_insn ("ldmia\t%1!, {%4, %5, %6}", operands);
10207 output_asm_insn ("stmia\t%0!, {%4, %5, %6}", operands);
10217 /* Routines for generating rtl */
10220 thumb_expand_movstrqi (operands)
10223 rtx out = copy_to_mode_reg (SImode, XEXP (operands[0], 0));
10224 rtx in = copy_to_mode_reg (SImode, XEXP (operands[1], 0));
10225 HOST_WIDE_INT len = INTVAL (operands[2]);
10226 HOST_WIDE_INT offset = 0;
10230 emit_insn (gen_movmem12b (out, in, out, in));
10236 emit_insn (gen_movmem8b (out, in, out, in));
10242 rtx reg = gen_reg_rtx (SImode);
10243 emit_insn (gen_movsi (reg, gen_rtx (MEM, SImode, in)));
10244 emit_insn (gen_movsi (gen_rtx (MEM, SImode, out), reg));
10251 rtx reg = gen_reg_rtx (HImode);
10252 emit_insn (gen_movhi (reg, gen_rtx (MEM, HImode,
10253 plus_constant (in, offset))));
10254 emit_insn (gen_movhi (gen_rtx (MEM, HImode, plus_constant (out, offset)),
10262 rtx reg = gen_reg_rtx (QImode);
10263 emit_insn (gen_movqi (reg, gen_rtx (MEM, QImode,
10264 plus_constant (in, offset))));
10265 emit_insn (gen_movqi (gen_rtx (MEM, QImode, plus_constant (out, offset)),
10271 thumb_cmp_operand (op, mode)
10273 enum machine_mode mode;
10275 return ((GET_CODE (op) == CONST_INT
10276 && (unsigned HOST_WIDE_INT) (INTVAL (op)) < 256)
10277 || register_operand (op, mode));
10280 static const char *
10281 thumb_condition_code (x, invert)
10285 static const char * conds[] =
10287 "eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc",
10288 "hi", "ls", "ge", "lt", "gt", "le"
10292 switch (GET_CODE (x))
10294 case EQ: val = 0; break;
10295 case NE: val = 1; break;
10296 case GEU: val = 2; break;
10297 case LTU: val = 3; break;
10298 case GTU: val = 8; break;
10299 case LEU: val = 9; break;
10300 case GE: val = 10; break;
10301 case LT: val = 11; break;
10302 case GT: val = 12; break;
10303 case LE: val = 13; break;
10308 return conds[val ^ invert];
10311 /* Handle storing a half-word to memory during reload. */
10313 thumb_reload_out_hi (operands)
10316 emit_insn (gen_thumb_movhi_clobber (operands[0], operands[1], operands[2]));
10319 /* Handle storing a half-word to memory during reload. */
10321 thumb_reload_in_hi (operands)
10322 rtx * operands ATTRIBUTE_UNUSED;
10327 /* Return the length of a function name prefix
10328 that starts with the character 'c'. */
10330 arm_get_strip_length (char c)
10334 ARM_NAME_ENCODING_LENGTHS
10339 /* Return a pointer to a function's name with any
10340 and all prefix encodings stripped from it. */
10342 arm_strip_name_encoding (const char * name)
10346 while ((skip = arm_get_strip_length (* name)))
10352 #ifdef AOF_ASSEMBLER
10353 /* Special functions only needed when producing AOF syntax assembler. */
10355 rtx aof_pic_label = NULL_RTX;
10358 struct pic_chain * next;
10362 static struct pic_chain * aof_pic_chain = NULL;
10368 struct pic_chain ** chainp;
10371 if (aof_pic_label == NULL_RTX)
10373 /* We mark this here and not in arm_add_gc_roots() to avoid
10374 polluting even more code with ifdefs, and because it never
10375 contains anything useful until we assign to it here. */
10376 ggc_add_rtx_root (&aof_pic_label, 1);
10377 aof_pic_label = gen_rtx_SYMBOL_REF (Pmode, "x$adcons");
10380 for (offset = 0, chainp = &aof_pic_chain; *chainp;
10381 offset += 4, chainp = &(*chainp)->next)
10382 if ((*chainp)->symname == XSTR (x, 0))
10383 return plus_constant (aof_pic_label, offset);
10385 *chainp = (struct pic_chain *) xmalloc (sizeof (struct pic_chain));
10386 (*chainp)->next = NULL;
10387 (*chainp)->symname = XSTR (x, 0);
10388 return plus_constant (aof_pic_label, offset);
10392 aof_dump_pic_table (f)
10395 struct pic_chain * chain;
10397 if (aof_pic_chain == NULL)
10400 asm_fprintf (f, "\tAREA |%r$$adcons|, BASED %r\n",
10401 PIC_OFFSET_TABLE_REGNUM,
10402 PIC_OFFSET_TABLE_REGNUM);
10403 fputs ("|x$adcons|\n", f);
10405 for (chain = aof_pic_chain; chain; chain = chain->next)
10407 fputs ("\tDCD\t", f);
10408 assemble_name (f, chain->symname);
10413 int arm_text_section_count = 1;
10416 aof_text_section ()
10418 static char buf[100];
10419 sprintf (buf, "\tAREA |C$$code%d|, CODE, READONLY",
10420 arm_text_section_count++);
10422 strcat (buf, ", PIC, REENTRANT");
10426 static int arm_data_section_count = 1;
10429 aof_data_section ()
10431 static char buf[100];
10432 sprintf (buf, "\tAREA |C$$data%d|, DATA", arm_data_section_count++);
10436 /* The AOF assembler is religiously strict about declarations of
10437 imported and exported symbols, so that it is impossible to declare
10438 a function as imported near the beginning of the file, and then to
10439 export it later on. It is, however, possible to delay the decision
10440 until all the functions in the file have been compiled. To get
10441 around this, we maintain a list of the imports and exports, and
10442 delete from it any that are subsequently defined. At the end of
10443 compilation we spit the remainder of the list out before the END
10448 struct import * next;
10452 static struct import * imports_list = NULL;
10455 aof_add_import (name)
10458 struct import * new;
10460 for (new = imports_list; new; new = new->next)
10461 if (new->name == name)
10464 new = (struct import *) xmalloc (sizeof (struct import));
10465 new->next = imports_list;
10466 imports_list = new;
10471 aof_delete_import (name)
10474 struct import ** old;
10476 for (old = &imports_list; *old; old = & (*old)->next)
10478 if ((*old)->name == name)
10480 *old = (*old)->next;
10486 int arm_main_function = 0;
10489 aof_dump_imports (f)
10492 /* The AOF assembler needs this to cause the startup code to be extracted
10493 from the library. Brining in __main causes the whole thing to work
10495 if (arm_main_function)
10498 fputs ("\tIMPORT __main\n", f);
10499 fputs ("\tDCD __main\n", f);
10502 /* Now dump the remaining imports. */
10503 while (imports_list)
10505 fprintf (f, "\tIMPORT\t");
10506 assemble_name (f, imports_list->name);
10508 imports_list = imports_list->next;
10511 #endif /* AOF_ASSEMBLER */