1 /* Output routines for GCC for ARM.
2 Copyright (C) 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001,
3 2002, 2003, 2004 Free Software Foundation, Inc.
4 Contributed by Pieter `Tiggr' Schoenmakers (rcpieter@win.tue.nl)
5 and Martin Simmons (@harleqn.co.uk).
6 More major hacks by Richard Earnshaw (rearnsha@arm.com).
8 This file is part of GCC.
10 GCC is free software; you can redistribute it and/or modify it
11 under the terms of the GNU General Public License as published
12 by the Free Software Foundation; either version 2, or (at your
13 option) any later version.
15 GCC is distributed in the hope that it will be useful, but WITHOUT
16 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
17 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
18 License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GCC; see the file COPYING. If not, write to
22 the Free Software Foundation, 59 Temple Place - Suite 330,
23 Boston, MA 02111-1307, USA. */
27 #include "coretypes.h"
33 #include "hard-reg-set.h"
35 #include "insn-config.h"
36 #include "conditions.h"
38 #include "insn-attr.h"
49 #include "integrate.h"
52 #include "target-def.h"
55 /* Forward definitions of types. */
56 typedef struct minipool_node Mnode;
57 typedef struct minipool_fixup Mfix;
59 const struct attribute_spec arm_attribute_table[];
61 /* Forward function declarations. */
62 static arm_stack_offsets *arm_get_frame_offsets (void);
63 static void arm_add_gc_roots (void);
64 static int arm_gen_constant (enum rtx_code, enum machine_mode, rtx,
65 HOST_WIDE_INT, rtx, rtx, int, int);
66 static unsigned bit_count (unsigned long);
67 static int arm_address_register_rtx_p (rtx, int);
68 static int arm_legitimate_index_p (enum machine_mode, rtx, RTX_CODE, int);
69 static int thumb_base_register_rtx_p (rtx, enum machine_mode, int);
70 inline static int thumb_index_register_rtx_p (rtx, int);
71 static int thumb_far_jump_used_p (void);
72 static int const_ok_for_op (HOST_WIDE_INT, enum rtx_code);
73 static rtx emit_multi_reg_push (int);
74 static rtx emit_sfm (int, int);
76 static bool arm_assemble_integer (rtx, unsigned int, int);
78 static const char *fp_const_from_val (REAL_VALUE_TYPE *);
79 static arm_cc get_arm_condition_code (rtx);
80 static HOST_WIDE_INT int_log2 (HOST_WIDE_INT);
81 static rtx is_jump_table (rtx);
82 static const char *output_multi_immediate (rtx *, const char *, const char *,
84 static void print_multi_reg (FILE *, const char *, int, int);
85 static const char *shift_op (rtx, HOST_WIDE_INT *);
86 static struct machine_function *arm_init_machine_status (void);
87 static int number_of_first_bit_set (int);
88 static void replace_symbols_in_block (tree, rtx, rtx);
89 static void thumb_exit (FILE *, int, rtx);
90 static void thumb_pushpop (FILE *, int, int, int *, int);
91 static rtx is_jump_table (rtx);
92 static HOST_WIDE_INT get_jump_table_size (rtx);
93 static Mnode *move_minipool_fix_forward_ref (Mnode *, Mnode *, HOST_WIDE_INT);
94 static Mnode *add_minipool_forward_ref (Mfix *);
95 static Mnode *move_minipool_fix_backward_ref (Mnode *, Mnode *, HOST_WIDE_INT);
96 static Mnode *add_minipool_backward_ref (Mfix *);
97 static void assign_minipool_offsets (Mfix *);
98 static void arm_print_value (FILE *, rtx);
99 static void dump_minipool (rtx);
100 static int arm_barrier_cost (rtx);
101 static Mfix *create_fix_barrier (Mfix *, HOST_WIDE_INT);
102 static void push_minipool_barrier (rtx, HOST_WIDE_INT);
103 static void push_minipool_fix (rtx, HOST_WIDE_INT, rtx *, enum machine_mode,
105 static void arm_reorg (void);
106 static bool note_invalid_constants (rtx, HOST_WIDE_INT, int);
107 static int current_file_function_operand (rtx);
108 static unsigned long arm_compute_save_reg0_reg12_mask (void);
109 static unsigned long arm_compute_save_reg_mask (void);
110 static unsigned long arm_isr_value (tree);
111 static unsigned long arm_compute_func_type (void);
112 static tree arm_handle_fndecl_attribute (tree *, tree, tree, int, bool *);
113 static tree arm_handle_isr_attribute (tree *, tree, tree, int, bool *);
114 static void arm_output_function_epilogue (FILE *, HOST_WIDE_INT);
115 static void arm_output_function_prologue (FILE *, HOST_WIDE_INT);
116 static void thumb_output_function_prologue (FILE *, HOST_WIDE_INT);
117 static int arm_comp_type_attributes (tree, tree);
118 static void arm_set_default_type_attributes (tree);
119 static int arm_adjust_cost (rtx, rtx, rtx, int);
120 static int count_insns_for_constant (HOST_WIDE_INT, int);
121 static int arm_get_strip_length (int);
122 static bool arm_function_ok_for_sibcall (tree, tree);
123 static void arm_internal_label (FILE *, const char *, unsigned long);
124 static void arm_output_mi_thunk (FILE *, tree, HOST_WIDE_INT, HOST_WIDE_INT,
126 static int arm_rtx_costs_1 (rtx, enum rtx_code, enum rtx_code);
127 static bool arm_slowmul_rtx_costs (rtx, int, int, int *);
128 static bool arm_fastmul_rtx_costs (rtx, int, int, int *);
129 static bool arm_xscale_rtx_costs (rtx, int, int, int *);
130 static bool arm_9e_rtx_costs (rtx, int, int, int *);
131 static int arm_address_cost (rtx);
132 static bool arm_memory_load_p (rtx);
133 static bool arm_cirrus_insn_p (rtx);
134 static void cirrus_reorg (rtx);
135 static void arm_init_builtins (void);
136 static rtx arm_expand_builtin (tree, rtx, rtx, enum machine_mode, int);
137 static void arm_init_iwmmxt_builtins (void);
138 static rtx safe_vector_operand (rtx, enum machine_mode);
139 static rtx arm_expand_binop_builtin (enum insn_code, tree, rtx);
140 static rtx arm_expand_unop_builtin (enum insn_code, tree, rtx, int);
141 static rtx arm_expand_builtin (tree, rtx, rtx, enum machine_mode, int);
142 static void emit_constant_insn (rtx cond, rtx pattern);
144 #ifdef OBJECT_FORMAT_ELF
145 static void arm_elf_asm_named_section (const char *, unsigned int);
148 static void arm_encode_section_info (tree, rtx, int);
151 static void aof_globalize_label (FILE *, const char *);
152 static void aof_dump_imports (FILE *);
153 static void aof_dump_pic_table (FILE *);
154 static void aof_file_start (void);
155 static void aof_file_end (void);
157 static rtx arm_struct_value_rtx (tree, int);
158 static void arm_setup_incoming_varargs (CUMULATIVE_ARGS *, enum machine_mode,
160 static bool arm_pass_by_reference (CUMULATIVE_ARGS *,
161 enum machine_mode, tree, bool);
162 static bool arm_promote_prototypes (tree);
163 static bool arm_default_short_enums (void);
164 static bool arm_align_anon_bitfield (void);
166 static tree arm_cxx_guard_type (void);
167 static bool arm_cxx_guard_mask_bit (void);
168 static tree arm_get_cookie_size (tree);
169 static bool arm_cookie_has_size (void);
172 /* Initialize the GCC target structure. */
173 #ifdef TARGET_DLLIMPORT_DECL_ATTRIBUTES
174 #undef TARGET_MERGE_DECL_ATTRIBUTES
175 #define TARGET_MERGE_DECL_ATTRIBUTES merge_dllimport_decl_attributes
178 #undef TARGET_ATTRIBUTE_TABLE
179 #define TARGET_ATTRIBUTE_TABLE arm_attribute_table
182 #undef TARGET_ASM_BYTE_OP
183 #define TARGET_ASM_BYTE_OP "\tDCB\t"
184 #undef TARGET_ASM_ALIGNED_HI_OP
185 #define TARGET_ASM_ALIGNED_HI_OP "\tDCW\t"
186 #undef TARGET_ASM_ALIGNED_SI_OP
187 #define TARGET_ASM_ALIGNED_SI_OP "\tDCD\t"
188 #undef TARGET_ASM_GLOBALIZE_LABEL
189 #define TARGET_ASM_GLOBALIZE_LABEL aof_globalize_label
190 #undef TARGET_ASM_FILE_START
191 #define TARGET_ASM_FILE_START aof_file_start
192 #undef TARGET_ASM_FILE_END
193 #define TARGET_ASM_FILE_END aof_file_end
195 #undef TARGET_ASM_ALIGNED_SI_OP
196 #define TARGET_ASM_ALIGNED_SI_OP NULL
197 #undef TARGET_ASM_INTEGER
198 #define TARGET_ASM_INTEGER arm_assemble_integer
201 #undef TARGET_ASM_FUNCTION_PROLOGUE
202 #define TARGET_ASM_FUNCTION_PROLOGUE arm_output_function_prologue
204 #undef TARGET_ASM_FUNCTION_EPILOGUE
205 #define TARGET_ASM_FUNCTION_EPILOGUE arm_output_function_epilogue
207 #undef TARGET_COMP_TYPE_ATTRIBUTES
208 #define TARGET_COMP_TYPE_ATTRIBUTES arm_comp_type_attributes
210 #undef TARGET_SET_DEFAULT_TYPE_ATTRIBUTES
211 #define TARGET_SET_DEFAULT_TYPE_ATTRIBUTES arm_set_default_type_attributes
213 #undef TARGET_SCHED_ADJUST_COST
214 #define TARGET_SCHED_ADJUST_COST arm_adjust_cost
216 #undef TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE
217 #define TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE hook_int_void_1
219 #undef TARGET_ENCODE_SECTION_INFO
221 #define TARGET_ENCODE_SECTION_INFO arm_pe_encode_section_info
223 #define TARGET_ENCODE_SECTION_INFO arm_encode_section_info
226 #undef TARGET_STRIP_NAME_ENCODING
227 #define TARGET_STRIP_NAME_ENCODING arm_strip_name_encoding
229 #undef TARGET_ASM_INTERNAL_LABEL
230 #define TARGET_ASM_INTERNAL_LABEL arm_internal_label
232 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
233 #define TARGET_FUNCTION_OK_FOR_SIBCALL arm_function_ok_for_sibcall
235 #undef TARGET_ASM_OUTPUT_MI_THUNK
236 #define TARGET_ASM_OUTPUT_MI_THUNK arm_output_mi_thunk
237 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
238 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK default_can_output_mi_thunk_no_vcall
240 /* This will be overridden in arm_override_options. */
241 #undef TARGET_RTX_COSTS
242 #define TARGET_RTX_COSTS arm_slowmul_rtx_costs
243 #undef TARGET_ADDRESS_COST
244 #define TARGET_ADDRESS_COST arm_address_cost
246 #undef TARGET_MACHINE_DEPENDENT_REORG
247 #define TARGET_MACHINE_DEPENDENT_REORG arm_reorg
249 #undef TARGET_INIT_BUILTINS
250 #define TARGET_INIT_BUILTINS arm_init_builtins
251 #undef TARGET_EXPAND_BUILTIN
252 #define TARGET_EXPAND_BUILTIN arm_expand_builtin
254 #undef TARGET_PROMOTE_FUNCTION_ARGS
255 #define TARGET_PROMOTE_FUNCTION_ARGS hook_bool_tree_true
256 #undef TARGET_PROMOTE_FUNCTION_RETURN
257 #define TARGET_PROMOTE_FUNCTION_RETURN hook_bool_tree_true
258 #undef TARGET_PROMOTE_PROTOTYPES
259 #define TARGET_PROMOTE_PROTOTYPES arm_promote_prototypes
260 #undef TARGET_PASS_BY_REFERENCE
261 #define TARGET_PASS_BY_REFERENCE arm_pass_by_reference
263 #undef TARGET_STRUCT_VALUE_RTX
264 #define TARGET_STRUCT_VALUE_RTX arm_struct_value_rtx
266 #undef TARGET_SETUP_INCOMING_VARARGS
267 #define TARGET_SETUP_INCOMING_VARARGS arm_setup_incoming_varargs
269 #undef TARGET_DEFAULT_SHORT_ENUMS
270 #define TARGET_DEFAULT_SHORT_ENUMS arm_default_short_enums
272 #undef TARGET_ALIGN_ANON_BITFIELD
273 #define TARGET_ALIGN_ANON_BITFIELD arm_align_anon_bitfield
275 #undef TARGET_CXX_GUARD_TYPE
276 #define TARGET_CXX_GUARD_TYPE arm_cxx_guard_type
278 #undef TARGET_CXX_GUARD_MASK_BIT
279 #define TARGET_CXX_GUARD_MASK_BIT arm_cxx_guard_mask_bit
281 #undef TARGET_CXX_GET_COOKIE_SIZE
282 #define TARGET_CXX_GET_COOKIE_SIZE arm_get_cookie_size
284 #undef TARGET_CXX_COOKIE_HAS_SIZE
285 #define TARGET_CXX_COOKIE_HAS_SIZE arm_cookie_has_size
287 struct gcc_target targetm = TARGET_INITIALIZER;
289 /* Obstack for minipool constant handling. */
290 static struct obstack minipool_obstack;
291 static char * minipool_startobj;
293 /* The maximum number of insns skipped which
294 will be conditionalised if possible. */
295 static int max_insns_skipped = 5;
297 extern FILE * asm_out_file;
299 /* True if we are currently building a constant table. */
300 int making_const_table;
302 /* Define the information needed to generate branch insns. This is
303 stored from the compare operation. */
304 rtx arm_compare_op0, arm_compare_op1;
306 /* The processor for which instructions should be scheduled. */
307 enum processor_type arm_tune = arm_none;
309 /* Which floating point model to use. */
310 enum arm_fp_model arm_fp_model;
312 /* Which floating point hardware is available. */
313 enum fputype arm_fpu_arch;
315 /* Which floating point hardware to schedule for. */
316 enum fputype arm_fpu_tune;
318 /* Whether to use floating point hardware. */
319 enum float_abi_type arm_float_abi;
321 /* Which ABI to use. */
322 enum arm_abi_type arm_abi;
324 /* Set by the -mfpu=... option. */
325 const char * target_fpu_name = NULL;
327 /* Set by the -mfpe=... option. */
328 const char * target_fpe_name = NULL;
330 /* Set by the -mfloat-abi=... option. */
331 const char * target_float_abi_name = NULL;
333 /* Set by the -mabi=... option. */
334 const char * target_abi_name = NULL;
336 /* Used to parse -mstructure_size_boundary command line option. */
337 const char * structure_size_string = NULL;
338 int arm_structure_size_boundary = DEFAULT_STRUCTURE_SIZE_BOUNDARY;
340 /* Bit values used to identify processor capabilities. */
341 #define FL_CO_PROC (1 << 0) /* Has external co-processor bus */
342 #define FL_ARCH3M (1 << 1) /* Extended multiply */
343 #define FL_MODE26 (1 << 2) /* 26-bit mode support */
344 #define FL_MODE32 (1 << 3) /* 32-bit mode support */
345 #define FL_ARCH4 (1 << 4) /* Architecture rel 4 */
346 #define FL_ARCH5 (1 << 5) /* Architecture rel 5 */
347 #define FL_THUMB (1 << 6) /* Thumb aware */
348 #define FL_LDSCHED (1 << 7) /* Load scheduling necessary */
349 #define FL_STRONG (1 << 8) /* StrongARM */
350 #define FL_ARCH5E (1 << 9) /* DSP extensions to v5 */
351 #define FL_XSCALE (1 << 10) /* XScale */
352 #define FL_CIRRUS (1 << 11) /* Cirrus/DSP. */
353 #define FL_ARCH6 (1 << 12) /* Architecture rel 6. Adds
354 media instructions. */
355 #define FL_VFPV2 (1 << 13) /* Vector Floating Point V2. */
357 #define FL_IWMMXT (1 << 29) /* XScale v2 or "Intel Wireless MMX technology". */
359 #define FL_FOR_ARCH2 0
360 #define FL_FOR_ARCH3 FL_MODE32
361 #define FL_FOR_ARCH3M (FL_FOR_ARCH3 | FL_ARCH3M)
362 #define FL_FOR_ARCH4 (FL_FOR_ARCH3M | FL_ARCH4)
363 #define FL_FOR_ARCH4T (FL_FOR_ARCH4 | FL_THUMB)
364 #define FL_FOR_ARCH5 (FL_FOR_ARCH4 | FL_ARCH5)
365 #define FL_FOR_ARCH5T (FL_FOR_ARCH5 | FL_THUMB)
366 #define FL_FOR_ARCH5E (FL_FOR_ARCH5 | FL_ARCH5E)
367 #define FL_FOR_ARCH5TE (FL_FOR_ARCH5E | FL_THUMB)
368 #define FL_FOR_ARCH5TEJ FL_FOR_ARCH5TE
369 #define FL_FOR_ARCH6 (FL_FOR_ARCH5TE | FL_ARCH6)
370 #define FL_FOR_ARCH6J FL_FOR_ARCH6
372 /* The bits in this mask specify which
373 instructions we are allowed to generate. */
374 static unsigned long insn_flags = 0;
376 /* The bits in this mask specify which instruction scheduling options should
378 static unsigned long tune_flags = 0;
380 /* The following are used in the arm.md file as equivalents to bits
381 in the above two flag variables. */
383 /* Nonzero if this chip supports the ARM Architecture 3M extensions. */
386 /* Nonzero if this chip supports the ARM Architecture 4 extensions. */
389 /* Nonzero if this chip supports the ARM Architecture 4t extensions. */
392 /* Nonzero if this chip supports the ARM Architecture 5 extensions. */
395 /* Nonzero if this chip supports the ARM Architecture 5E extensions. */
398 /* Nonzero if this chip supports the ARM Architecture 6 extensions. */
401 /* Nonzero if this chip can benefit from load scheduling. */
402 int arm_ld_sched = 0;
404 /* Nonzero if this chip is a StrongARM. */
405 int arm_is_strong = 0;
407 /* Nonzero if this chip is a Cirrus variant. */
408 int arm_arch_cirrus = 0;
410 /* Nonzero if this chip supports Intel Wireless MMX technology. */
411 int arm_arch_iwmmxt = 0;
413 /* Nonzero if this chip is an XScale. */
414 int arm_arch_xscale = 0;
416 /* Nonzero if tuning for XScale */
417 int arm_tune_xscale = 0;
419 /* Nonzero if this chip is an ARM6 or an ARM7. */
420 int arm_is_6_or_7 = 0;
422 /* Nonzero if generating Thumb instructions. */
425 /* Nonzero if we should define __THUMB_INTERWORK__ in the
427 XXX This is a bit of a hack, it's intended to help work around
428 problems in GLD which doesn't understand that armv5t code is
429 interworking clean. */
430 int arm_cpp_interwork = 0;
432 /* In case of a PRE_INC, POST_INC, PRE_DEC, POST_DEC memory reference, we
433 must report the mode of the memory reference from PRINT_OPERAND to
434 PRINT_OPERAND_ADDRESS. */
435 enum machine_mode output_memory_reference_mode;
437 /* The register number to be used for the PIC offset register. */
438 const char * arm_pic_register_string = NULL;
439 int arm_pic_register = INVALID_REGNUM;
441 /* Set to 1 when a return insn is output, this means that the epilogue
443 int return_used_this_function;
445 /* Set to 1 after arm_reorg has started. Reset to start at the start of
446 the next function. */
447 static int after_arm_reorg = 0;
449 /* The maximum number of insns to be used when loading a constant. */
450 static int arm_constant_limit = 3;
452 /* For an explanation of these variables, see final_prescan_insn below. */
454 enum arm_cond_code arm_current_cc;
456 int arm_target_label;
458 /* The condition codes of the ARM, and the inverse function. */
459 static const char * const arm_condition_codes[] =
461 "eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc",
462 "hi", "ls", "ge", "lt", "gt", "le", "al", "nv"
465 #define streq(string1, string2) (strcmp (string1, string2) == 0)
467 /* Initialization code. */
471 const char *const name;
472 enum processor_type core;
474 const unsigned long flags;
475 bool (* rtx_costs) (rtx, int, int, int *);
478 /* Not all of these give usefully different compilation alternatives,
479 but there is no simple way of generalizing them. */
480 static const struct processors all_cores[] =
483 #define ARM_CORE(NAME, ARCH, FLAGS, COSTS) \
484 {#NAME, arm_none, #ARCH, FLAGS | FL_FOR_ARCH##ARCH, arm_##COSTS##_rtx_costs},
485 #include "arm-cores.def"
487 {NULL, arm_none, NULL, 0, NULL}
490 static const struct processors all_architectures[] =
492 /* ARM Architectures */
493 /* We don't specify rtx_costs here as it will be figured out
496 {"armv2", arm2, "2", FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH2, NULL},
497 {"armv2a", arm2, "2", FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH2, NULL},
498 {"armv3", arm6, "3", FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH3, NULL},
499 {"armv3m", arm7m, "3M", FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH3M, NULL},
500 {"armv4", arm7tdmi, "4", FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH4, NULL},
501 /* Strictly, FL_MODE26 is a permitted option for v4t, but there are no
502 implementations that support it, so we will leave it out for now. */
503 {"armv4t", arm7tdmi, "4T", FL_CO_PROC | FL_FOR_ARCH4T, NULL},
504 {"armv5", arm10tdmi, "5", FL_CO_PROC | FL_FOR_ARCH5, NULL},
505 {"armv5t", arm10tdmi, "5T", FL_CO_PROC | FL_FOR_ARCH5T, NULL},
506 {"armv5e", arm1026ejs, "5E", FL_CO_PROC | FL_FOR_ARCH5E, NULL},
507 {"armv5te", arm1026ejs, "5TE", FL_CO_PROC | FL_FOR_ARCH5TE, NULL},
508 {"armv6", arm1136js, "6", FL_CO_PROC | FL_FOR_ARCH6, NULL},
509 {"armv6j", arm1136js, "6J", FL_CO_PROC | FL_FOR_ARCH6J, NULL},
510 {"ep9312", ep9312, "4T", FL_LDSCHED | FL_CIRRUS | FL_FOR_ARCH4, NULL},
511 {"iwmmxt", iwmmxt, "5TE", FL_LDSCHED | FL_STRONG | FL_FOR_ARCH5TE | FL_XSCALE | FL_IWMMXT , NULL},
512 {NULL, arm_none, NULL, 0 , NULL}
515 /* This is a magic structure. The 'string' field is magically filled in
516 with a pointer to the value specified by the user on the command line
517 assuming that the user has specified such a value. */
519 struct arm_cpu_select arm_select[] =
521 /* string name processors */
522 { NULL, "-mcpu=", all_cores },
523 { NULL, "-march=", all_architectures },
524 { NULL, "-mtune=", all_cores }
528 /* The name of the proprocessor macro to define for this architecture. */
530 char arm_arch_name[] = "__ARM_ARCH_0UNK__";
539 /* Available values for for -mfpu=. */
541 static const struct fpu_desc all_fpus[] =
543 {"fpa", FPUTYPE_FPA},
544 {"fpe2", FPUTYPE_FPA_EMU2},
545 {"fpe3", FPUTYPE_FPA_EMU2},
546 {"maverick", FPUTYPE_MAVERICK},
551 /* Floating point models used by the different hardware.
552 See fputype in arm.h. */
554 static const enum fputype fp_model_for_fpu[] =
556 /* No FP hardware. */
557 ARM_FP_MODEL_UNKNOWN, /* FPUTYPE_NONE */
558 ARM_FP_MODEL_FPA, /* FPUTYPE_FPA */
559 ARM_FP_MODEL_FPA, /* FPUTYPE_FPA_EMU2 */
560 ARM_FP_MODEL_FPA, /* FPUTYPE_FPA_EMU3 */
561 ARM_FP_MODEL_MAVERICK, /* FPUTYPE_MAVERICK */
562 ARM_FP_MODEL_VFP /* FPUTYPE_VFP */
569 enum float_abi_type abi_type;
573 /* Available values for -mfloat-abi=. */
575 static const struct float_abi all_float_abis[] =
577 {"soft", ARM_FLOAT_ABI_SOFT},
578 {"softfp", ARM_FLOAT_ABI_SOFTFP},
579 {"hard", ARM_FLOAT_ABI_HARD}
586 enum arm_abi_type abi_type;
590 /* Available values for -mabi=. */
592 static const struct abi_name arm_all_abis[] =
594 {"apcs-gnu", ARM_ABI_APCS},
595 {"atpcs", ARM_ABI_ATPCS},
596 {"aapcs", ARM_ABI_AAPCS},
597 {"iwmmxt", ARM_ABI_IWMMXT}
600 /* Return the number of bits set in VALUE. */
602 bit_count (unsigned long value)
604 unsigned long count = 0;
609 value &= value - 1; /* Clear the least-significant set bit. */
615 /* Fix up any incompatible options that the user has specified.
616 This has now turned into a maze. */
618 arm_override_options (void)
622 /* Set up the flags based on the cpu/architecture selected by the user. */
623 for (i = ARRAY_SIZE (arm_select); i--;)
625 struct arm_cpu_select * ptr = arm_select + i;
627 if (ptr->string != NULL && ptr->string[0] != '\0')
629 const struct processors * sel;
631 for (sel = ptr->processors; sel->name != NULL; sel++)
632 if (streq (ptr->string, sel->name))
634 /* Set the architecture define. */
636 sprintf (arm_arch_name, "__ARM_ARCH_%s__", sel->arch);
638 /* Determine the processor core for which we should
639 tune code-generation. */
640 if (/* -mcpu= is a sensible default. */
642 /* If -march= is used, and -mcpu= has not been used,
643 assume that we should tune for a representative
644 CPU from that architecture. */
646 /* -mtune= overrides -mcpu= and -march=. */
648 arm_tune = (enum processor_type) (sel - ptr->processors);
652 /* If we have been given an architecture and a processor
653 make sure that they are compatible. We only generate
654 a warning though, and we prefer the CPU over the
656 if (insn_flags != 0 && (insn_flags ^ sel->flags))
657 warning ("switch -mcpu=%s conflicts with -march= switch",
660 insn_flags = sel->flags;
666 if (sel->name == NULL)
667 error ("bad value (%s) for %s switch", ptr->string, ptr->name);
671 /* If the user did not specify a processor, choose one for them. */
674 const struct processors * sel;
676 enum processor_type cpu;
678 cpu = TARGET_CPU_DEFAULT;
681 #ifdef SUBTARGET_CPU_DEFAULT
682 /* Use the subtarget default CPU if none was specified by
684 cpu = SUBTARGET_CPU_DEFAULT;
686 /* Default to ARM6. */
690 sel = &all_cores[cpu];
692 insn_flags = sel->flags;
694 /* Now check to see if the user has specified some command line
695 switch that require certain abilities from the cpu. */
698 if (TARGET_INTERWORK || TARGET_THUMB)
700 sought |= (FL_THUMB | FL_MODE32);
702 /* There are no ARM processors that support both APCS-26 and
703 interworking. Therefore we force FL_MODE26 to be removed
704 from insn_flags here (if it was set), so that the search
705 below will always be able to find a compatible processor. */
706 insn_flags &= ~FL_MODE26;
709 if (sought != 0 && ((sought & insn_flags) != sought))
711 /* Try to locate a CPU type that supports all of the abilities
712 of the default CPU, plus the extra abilities requested by
714 for (sel = all_cores; sel->name != NULL; sel++)
715 if ((sel->flags & sought) == (sought | insn_flags))
718 if (sel->name == NULL)
720 unsigned current_bit_count = 0;
721 const struct processors * best_fit = NULL;
723 /* Ideally we would like to issue an error message here
724 saying that it was not possible to find a CPU compatible
725 with the default CPU, but which also supports the command
726 line options specified by the programmer, and so they
727 ought to use the -mcpu=<name> command line option to
728 override the default CPU type.
730 If we cannot find a cpu that has both the
731 characteristics of the default cpu and the given
732 command line options we scan the array again looking
734 for (sel = all_cores; sel->name != NULL; sel++)
735 if ((sel->flags & sought) == sought)
739 count = bit_count (sel->flags & insn_flags);
741 if (count >= current_bit_count)
744 current_bit_count = count;
748 if (best_fit == NULL)
754 insn_flags = sel->flags;
756 sprintf (arm_arch_name, "__ARM_ARCH_%s__", sel->arch);
757 if (arm_tune == arm_none)
758 arm_tune = (enum processor_type) (sel - all_cores);
761 /* The processor for which we should tune should now have been
763 if (arm_tune == arm_none)
766 tune_flags = all_cores[(int)arm_tune].flags;
767 targetm.rtx_costs = all_cores[(int)arm_tune].rtx_costs;
769 /* Make sure that the processor choice does not conflict with any of the
770 other command line choices. */
771 if (TARGET_INTERWORK && !(insn_flags & FL_THUMB))
773 warning ("target CPU does not support interworking" );
774 target_flags &= ~ARM_FLAG_INTERWORK;
777 if (TARGET_THUMB && !(insn_flags & FL_THUMB))
779 warning ("target CPU does not support THUMB instructions");
780 target_flags &= ~ARM_FLAG_THUMB;
783 if (TARGET_APCS_FRAME && TARGET_THUMB)
785 /* warning ("ignoring -mapcs-frame because -mthumb was used"); */
786 target_flags &= ~ARM_FLAG_APCS_FRAME;
789 /* TARGET_BACKTRACE calls leaf_function_p, which causes a crash if done
790 from here where no function is being compiled currently. */
791 if ((target_flags & (THUMB_FLAG_LEAF_BACKTRACE | THUMB_FLAG_BACKTRACE))
793 warning ("enabling backtrace support is only meaningful when compiling for the Thumb");
795 if (TARGET_ARM && TARGET_CALLEE_INTERWORKING)
796 warning ("enabling callee interworking support is only meaningful when compiling for the Thumb");
798 if (TARGET_ARM && TARGET_CALLER_INTERWORKING)
799 warning ("enabling caller interworking support is only meaningful when compiling for the Thumb");
801 if (TARGET_APCS_STACK && !TARGET_APCS_FRAME)
803 warning ("-mapcs-stack-check incompatible with -mno-apcs-frame");
804 target_flags |= ARM_FLAG_APCS_FRAME;
807 if (TARGET_POKE_FUNCTION_NAME)
808 target_flags |= ARM_FLAG_APCS_FRAME;
810 if (TARGET_APCS_REENT && flag_pic)
811 error ("-fpic and -mapcs-reent are incompatible");
813 if (TARGET_APCS_REENT)
814 warning ("APCS reentrant code not supported. Ignored");
816 /* If this target is normally configured to use APCS frames, warn if they
817 are turned off and debugging is turned on. */
819 && write_symbols != NO_DEBUG
820 && !TARGET_APCS_FRAME
821 && (TARGET_DEFAULT & ARM_FLAG_APCS_FRAME))
822 warning ("-g with -mno-apcs-frame may not give sensible debugging");
824 /* If stack checking is disabled, we can use r10 as the PIC register,
825 which keeps r9 available. */
827 arm_pic_register = TARGET_APCS_STACK ? 9 : 10;
829 if (TARGET_APCS_FLOAT)
830 warning ("passing floating point arguments in fp regs not yet supported");
832 /* Initialize boolean versions of the flags, for use in the arm.md file. */
833 arm_arch3m = (insn_flags & FL_ARCH3M) != 0;
834 arm_arch4 = (insn_flags & FL_ARCH4) != 0;
835 arm_arch4t = arm_arch4 & ((insn_flags & FL_THUMB) != 0);
836 arm_arch5 = (insn_flags & FL_ARCH5) != 0;
837 arm_arch5e = (insn_flags & FL_ARCH5E) != 0;
838 arm_arch6 = (insn_flags & FL_ARCH6) != 0;
839 arm_arch_xscale = (insn_flags & FL_XSCALE) != 0;
840 arm_arch_cirrus = (insn_flags & FL_CIRRUS) != 0;
842 arm_ld_sched = (tune_flags & FL_LDSCHED) != 0;
843 arm_is_strong = (tune_flags & FL_STRONG) != 0;
844 thumb_code = (TARGET_ARM == 0);
845 arm_is_6_or_7 = (((tune_flags & (FL_MODE26 | FL_MODE32))
846 && !(tune_flags & FL_ARCH4))) != 0;
847 arm_tune_xscale = (tune_flags & FL_XSCALE) != 0;
848 arm_arch_iwmmxt = (insn_flags & FL_IWMMXT) != 0;
850 /* V5 code we generate is completely interworking capable, so we turn off
851 TARGET_INTERWORK here to avoid many tests later on. */
853 /* XXX However, we must pass the right pre-processor defines to CPP
854 or GLD can get confused. This is a hack. */
855 if (TARGET_INTERWORK)
856 arm_cpp_interwork = 1;
859 target_flags &= ~ARM_FLAG_INTERWORK;
863 for (i = 0; i < ARRAY_SIZE (arm_all_abis); i++)
865 if (streq (arm_all_abis[i].name, target_abi_name))
867 arm_abi = arm_all_abis[i].abi_type;
871 if (i == ARRAY_SIZE (arm_all_abis))
872 error ("invalid ABI option: -mabi=%s", target_abi_name);
875 arm_abi = ARM_DEFAULT_ABI;
877 if (TARGET_IWMMXT && !ARM_DOUBLEWORD_ALIGN)
878 error ("iwmmxt requires an AAPCS compatible ABI for proper operation");
880 if (TARGET_IWMMXT_ABI && !TARGET_IWMMXT)
881 error ("iwmmxt abi requires an iwmmxt capable cpu");
883 arm_fp_model = ARM_FP_MODEL_UNKNOWN;
884 if (target_fpu_name == NULL && target_fpe_name != NULL)
886 if (streq (target_fpe_name, "2"))
887 target_fpu_name = "fpe2";
888 else if (streq (target_fpe_name, "3"))
889 target_fpu_name = "fpe3";
891 error ("invalid floating point emulation option: -mfpe=%s",
894 if (target_fpu_name != NULL)
896 /* The user specified a FPU. */
897 for (i = 0; i < ARRAY_SIZE (all_fpus); i++)
899 if (streq (all_fpus[i].name, target_fpu_name))
901 arm_fpu_arch = all_fpus[i].fpu;
902 arm_fpu_tune = arm_fpu_arch;
903 arm_fp_model = fp_model_for_fpu[arm_fpu_arch];
907 if (arm_fp_model == ARM_FP_MODEL_UNKNOWN)
908 error ("invalid floating point option: -mfpu=%s", target_fpu_name);
912 #ifdef FPUTYPE_DEFAULT
913 /* Use the default if it is specified for this platform. */
914 arm_fpu_arch = FPUTYPE_DEFAULT;
915 arm_fpu_tune = FPUTYPE_DEFAULT;
917 /* Pick one based on CPU type. */
918 /* ??? Some targets assume FPA is the default.
919 if ((insn_flags & FL_VFP) != 0)
920 arm_fpu_arch = FPUTYPE_VFP;
924 arm_fpu_arch = FPUTYPE_MAVERICK;
926 arm_fpu_arch = FPUTYPE_FPA_EMU2;
928 if (tune_flags & FL_CO_PROC && arm_fpu_arch == FPUTYPE_FPA_EMU2)
929 arm_fpu_tune = FPUTYPE_FPA;
931 arm_fpu_tune = arm_fpu_arch;
932 arm_fp_model = fp_model_for_fpu[arm_fpu_arch];
933 if (arm_fp_model == ARM_FP_MODEL_UNKNOWN)
937 if (target_float_abi_name != NULL)
939 /* The user specified a FP ABI. */
940 for (i = 0; i < ARRAY_SIZE (all_float_abis); i++)
942 if (streq (all_float_abis[i].name, target_float_abi_name))
944 arm_float_abi = all_float_abis[i].abi_type;
948 if (i == ARRAY_SIZE (all_float_abis))
949 error ("invalid floating point abi: -mfloat-abi=%s",
950 target_float_abi_name);
954 /* Use soft-float target flag. */
955 if (target_flags & ARM_FLAG_SOFT_FLOAT)
956 arm_float_abi = ARM_FLOAT_ABI_SOFT;
958 arm_float_abi = ARM_FLOAT_ABI_HARD;
961 if (arm_float_abi == ARM_FLOAT_ABI_SOFTFP)
962 sorry ("-mfloat-abi=softfp");
963 /* If soft-float is specified then don't use FPU. */
964 if (TARGET_SOFT_FLOAT)
965 arm_fpu_arch = FPUTYPE_NONE;
967 /* For arm2/3 there is no need to do any scheduling if there is only
968 a floating point emulator, or we are doing software floating-point. */
969 if ((TARGET_SOFT_FLOAT
970 || arm_fpu_tune == FPUTYPE_FPA_EMU2
971 || arm_fpu_tune == FPUTYPE_FPA_EMU3)
972 && (tune_flags & FL_MODE32) == 0)
973 flag_schedule_insns = flag_schedule_insns_after_reload = 0;
975 /* Override the default structure alignment for AAPCS ABI. */
976 if (arm_abi == ARM_ABI_AAPCS)
977 arm_structure_size_boundary = 8;
979 if (structure_size_string != NULL)
981 int size = strtol (structure_size_string, NULL, 0);
983 if (size == 8 || size == 32
984 || (ARM_DOUBLEWORD_ALIGN && size == 64))
985 arm_structure_size_boundary = size;
987 warning ("structure size boundary can only be set to %s",
988 ARM_DOUBLEWORD_ALIGN ? "8, 32 or 64": "8 or 32");
991 if (arm_pic_register_string != NULL)
993 int pic_register = decode_reg_name (arm_pic_register_string);
996 warning ("-mpic-register= is useless without -fpic");
998 /* Prevent the user from choosing an obviously stupid PIC register. */
999 else if (pic_register < 0 || call_used_regs[pic_register]
1000 || pic_register == HARD_FRAME_POINTER_REGNUM
1001 || pic_register == STACK_POINTER_REGNUM
1002 || pic_register >= PC_REGNUM)
1003 error ("unable to use '%s' for PIC register", arm_pic_register_string);
1005 arm_pic_register = pic_register;
1008 if (TARGET_THUMB && flag_schedule_insns)
1010 /* Don't warn since it's on by default in -O2. */
1011 flag_schedule_insns = 0;
1016 /* There's some dispute as to whether this should be 1 or 2. However,
1017 experiments seem to show that in pathological cases a setting of
1018 1 degrades less severely than a setting of 2. This could change if
1019 other parts of the compiler change their behavior. */
1020 arm_constant_limit = 1;
1022 /* If optimizing for size, bump the number of instructions that we
1023 are prepared to conditionally execute (even on a StrongARM). */
1024 max_insns_skipped = 6;
1028 /* For processors with load scheduling, it never costs more than
1029 2 cycles to load a constant, and the load scheduler may well
1030 reduce that to 1. */
1031 if (tune_flags & FL_LDSCHED)
1032 arm_constant_limit = 1;
1034 /* On XScale the longer latency of a load makes it more difficult
1035 to achieve a good schedule, so it's faster to synthesize
1036 constants that can be done in two insns. */
1037 if (arm_tune_xscale)
1038 arm_constant_limit = 2;
1040 /* StrongARM has early execution of branches, so a sequence
1041 that is worth skipping is shorter. */
1043 max_insns_skipped = 3;
1046 /* Register global variables with the garbage collector. */
1047 arm_add_gc_roots ();
1051 arm_add_gc_roots (void)
1053 gcc_obstack_init(&minipool_obstack);
1054 minipool_startobj = (char *) obstack_alloc (&minipool_obstack, 0);
1057 /* A table of known ARM exception types.
1058 For use with the interrupt function attribute. */
1062 const char *const arg;
1063 const unsigned long return_value;
1067 static const isr_attribute_arg isr_attribute_args [] =
1069 { "IRQ", ARM_FT_ISR },
1070 { "irq", ARM_FT_ISR },
1071 { "FIQ", ARM_FT_FIQ },
1072 { "fiq", ARM_FT_FIQ },
1073 { "ABORT", ARM_FT_ISR },
1074 { "abort", ARM_FT_ISR },
1075 { "ABORT", ARM_FT_ISR },
1076 { "abort", ARM_FT_ISR },
1077 { "UNDEF", ARM_FT_EXCEPTION },
1078 { "undef", ARM_FT_EXCEPTION },
1079 { "SWI", ARM_FT_EXCEPTION },
1080 { "swi", ARM_FT_EXCEPTION },
1081 { NULL, ARM_FT_NORMAL }
1084 /* Returns the (interrupt) function type of the current
1085 function, or ARM_FT_UNKNOWN if the type cannot be determined. */
1087 static unsigned long
1088 arm_isr_value (tree argument)
1090 const isr_attribute_arg * ptr;
1093 /* No argument - default to IRQ. */
1094 if (argument == NULL_TREE)
1097 /* Get the value of the argument. */
1098 if (TREE_VALUE (argument) == NULL_TREE
1099 || TREE_CODE (TREE_VALUE (argument)) != STRING_CST)
1100 return ARM_FT_UNKNOWN;
1102 arg = TREE_STRING_POINTER (TREE_VALUE (argument));
1104 /* Check it against the list of known arguments. */
1105 for (ptr = isr_attribute_args; ptr->arg != NULL; ptr++)
1106 if (streq (arg, ptr->arg))
1107 return ptr->return_value;
1109 /* An unrecognized interrupt type. */
1110 return ARM_FT_UNKNOWN;
1113 /* Computes the type of the current function. */
1115 static unsigned long
1116 arm_compute_func_type (void)
1118 unsigned long type = ARM_FT_UNKNOWN;
1122 if (TREE_CODE (current_function_decl) != FUNCTION_DECL)
1125 /* Decide if the current function is volatile. Such functions
1126 never return, and many memory cycles can be saved by not storing
1127 register values that will never be needed again. This optimization
1128 was added to speed up context switching in a kernel application. */
1130 && TREE_NOTHROW (current_function_decl)
1131 && TREE_THIS_VOLATILE (current_function_decl))
1132 type |= ARM_FT_VOLATILE;
1134 if (cfun->static_chain_decl != NULL)
1135 type |= ARM_FT_NESTED;
1137 attr = DECL_ATTRIBUTES (current_function_decl);
1139 a = lookup_attribute ("naked", attr);
1141 type |= ARM_FT_NAKED;
1143 if (cfun->machine->eh_epilogue_sp_ofs != NULL_RTX)
1144 type |= ARM_FT_EXCEPTION_HANDLER;
1147 a = lookup_attribute ("isr", attr);
1149 a = lookup_attribute ("interrupt", attr);
1152 type |= TARGET_INTERWORK ? ARM_FT_INTERWORKED : ARM_FT_NORMAL;
1154 type |= arm_isr_value (TREE_VALUE (a));
1160 /* Returns the type of the current function. */
1163 arm_current_func_type (void)
1165 if (ARM_FUNC_TYPE (cfun->machine->func_type) == ARM_FT_UNKNOWN)
1166 cfun->machine->func_type = arm_compute_func_type ();
1168 return cfun->machine->func_type;
1171 /* Return 1 if it is possible to return using a single instruction.
1172 If SIBLING is non-null, this is a test for a return before a sibling
1173 call. SIBLING is the call insn, so we can examine its register usage. */
1176 use_return_insn (int iscond, rtx sibling)
1179 unsigned int func_type;
1180 unsigned long saved_int_regs;
1181 unsigned HOST_WIDE_INT stack_adjust;
1182 arm_stack_offsets *offsets;
1184 /* Never use a return instruction before reload has run. */
1185 if (!reload_completed)
1188 func_type = arm_current_func_type ();
1190 /* Naked functions and volatile functions need special
1192 if (func_type & (ARM_FT_VOLATILE | ARM_FT_NAKED))
1195 /* So do interrupt functions that use the frame pointer. */
1196 if (IS_INTERRUPT (func_type) && frame_pointer_needed)
1199 offsets = arm_get_frame_offsets ();
1200 stack_adjust = offsets->outgoing_args - offsets->saved_regs;
1202 /* As do variadic functions. */
1203 if (current_function_pretend_args_size
1204 || cfun->machine->uses_anonymous_args
1205 /* Or if the function calls __builtin_eh_return () */
1206 || ARM_FUNC_TYPE (func_type) == ARM_FT_EXCEPTION_HANDLER
1207 /* Or if the function calls alloca */
1208 || current_function_calls_alloca
1209 /* Or if there is a stack adjustment. However, if the stack pointer
1210 is saved on the stack, we can use a pre-incrementing stack load. */
1211 || !(stack_adjust == 0 || (frame_pointer_needed && stack_adjust == 4)))
1214 saved_int_regs = arm_compute_save_reg_mask ();
1216 /* Unfortunately, the insn
1218 ldmib sp, {..., sp, ...}
1220 triggers a bug on most SA-110 based devices, such that the stack
1221 pointer won't be correctly restored if the instruction takes a
1222 page fault. We work around this problem by popping r3 along with
1223 the other registers, since that is never slower than executing
1224 another instruction.
1226 We test for !arm_arch5 here, because code for any architecture
1227 less than this could potentially be run on one of the buggy
1229 if (stack_adjust == 4 && !arm_arch5)
1231 /* Validate that r3 is a call-clobbered register (always true in
1232 the default abi) ... */
1233 if (!call_used_regs[3])
1236 /* ... that it isn't being used for a return value (always true
1237 until we implement return-in-regs), or for a tail-call
1241 if (GET_CODE (sibling) != CALL_INSN)
1244 if (find_regno_fusage (sibling, USE, 3))
1248 /* ... and that there are no call-saved registers in r0-r2
1249 (always true in the default ABI). */
1250 if (saved_int_regs & 0x7)
1254 /* Can't be done if interworking with Thumb, and any registers have been
1256 if (TARGET_INTERWORK && saved_int_regs != 0)
1259 /* On StrongARM, conditional returns are expensive if they aren't
1260 taken and multiple registers have been stacked. */
1261 if (iscond && arm_is_strong)
1263 /* Conditional return when just the LR is stored is a simple
1264 conditional-load instruction, that's not expensive. */
1265 if (saved_int_regs != 0 && saved_int_regs != (1 << LR_REGNUM))
1268 if (flag_pic && regs_ever_live[PIC_OFFSET_TABLE_REGNUM])
1272 /* If there are saved registers but the LR isn't saved, then we need
1273 two instructions for the return. */
1274 if (saved_int_regs && !(saved_int_regs & (1 << LR_REGNUM)))
1277 /* Can't be done if any of the FPA regs are pushed,
1278 since this also requires an insn. */
1279 if (TARGET_HARD_FLOAT && TARGET_FPA)
1280 for (regno = FIRST_FPA_REGNUM; regno <= LAST_FPA_REGNUM; regno++)
1281 if (regs_ever_live[regno] && !call_used_regs[regno])
1284 /* Likewise VFP regs. */
1285 if (TARGET_HARD_FLOAT && TARGET_VFP)
1286 for (regno = FIRST_VFP_REGNUM; regno <= LAST_VFP_REGNUM; regno++)
1287 if (regs_ever_live[regno] && !call_used_regs[regno])
1290 if (TARGET_REALLY_IWMMXT)
1291 for (regno = FIRST_IWMMXT_REGNUM; regno <= LAST_IWMMXT_REGNUM; regno++)
1292 if (regs_ever_live[regno] && ! call_used_regs [regno])
1298 /* Return TRUE if int I is a valid immediate ARM constant. */
1301 const_ok_for_arm (HOST_WIDE_INT i)
1303 unsigned HOST_WIDE_INT mask = ~(unsigned HOST_WIDE_INT)0xFF;
1305 /* For machines with >32 bit HOST_WIDE_INT, the bits above bit 31 must
1306 be all zero, or all one. */
1307 if ((i & ~(unsigned HOST_WIDE_INT) 0xffffffff) != 0
1308 && ((i & ~(unsigned HOST_WIDE_INT) 0xffffffff)
1309 != ((~(unsigned HOST_WIDE_INT) 0)
1310 & ~(unsigned HOST_WIDE_INT) 0xffffffff)))
1313 /* Fast return for 0 and powers of 2 */
1314 if ((i & (i - 1)) == 0)
1319 if ((i & mask & (unsigned HOST_WIDE_INT) 0xffffffff) == 0)
1322 (mask << 2) | ((mask & (unsigned HOST_WIDE_INT) 0xffffffff)
1323 >> (32 - 2)) | ~(unsigned HOST_WIDE_INT) 0xffffffff;
1325 while (mask != ~(unsigned HOST_WIDE_INT) 0xFF);
1330 /* Return true if I is a valid constant for the operation CODE. */
1332 const_ok_for_op (HOST_WIDE_INT i, enum rtx_code code)
1334 if (const_ok_for_arm (i))
1340 return const_ok_for_arm (ARM_SIGN_EXTEND (-i));
1342 case MINUS: /* Should only occur with (MINUS I reg) => rsb */
1348 return const_ok_for_arm (ARM_SIGN_EXTEND (~i));
1355 /* Emit a sequence of insns to handle a large constant.
1356 CODE is the code of the operation required, it can be any of SET, PLUS,
1357 IOR, AND, XOR, MINUS;
1358 MODE is the mode in which the operation is being performed;
1359 VAL is the integer to operate on;
1360 SOURCE is the other operand (a register, or a null-pointer for SET);
1361 SUBTARGETS means it is safe to create scratch registers if that will
1362 either produce a simpler sequence, or we will want to cse the values.
1363 Return value is the number of insns emitted. */
1366 arm_split_constant (enum rtx_code code, enum machine_mode mode, rtx insn,
1367 HOST_WIDE_INT val, rtx target, rtx source, int subtargets)
1371 if (insn && GET_CODE (PATTERN (insn)) == COND_EXEC)
1372 cond = COND_EXEC_TEST (PATTERN (insn));
1376 if (subtargets || code == SET
1377 || (GET_CODE (target) == REG && GET_CODE (source) == REG
1378 && REGNO (target) != REGNO (source)))
1380 /* After arm_reorg has been called, we can't fix up expensive
1381 constants by pushing them into memory so we must synthesize
1382 them in-line, regardless of the cost. This is only likely to
1383 be more costly on chips that have load delay slots and we are
1384 compiling without running the scheduler (so no splitting
1385 occurred before the final instruction emission).
1387 Ref: gcc -O1 -mcpu=strongarm gcc.c-torture/compile/980506-2.c
1389 if (!after_arm_reorg
1391 && (arm_gen_constant (code, mode, NULL_RTX, val, target, source,
1393 > arm_constant_limit + (code != SET)))
1397 /* Currently SET is the only monadic value for CODE, all
1398 the rest are diadic. */
1399 emit_insn (gen_rtx_SET (VOIDmode, target, GEN_INT (val)));
1404 rtx temp = subtargets ? gen_reg_rtx (mode) : target;
1406 emit_insn (gen_rtx_SET (VOIDmode, temp, GEN_INT (val)));
1407 /* For MINUS, the value is subtracted from, since we never
1408 have subtraction of a constant. */
1410 emit_insn (gen_rtx_SET (VOIDmode, target,
1411 gen_rtx_MINUS (mode, temp, source)));
1413 emit_insn (gen_rtx_SET (VOIDmode, target,
1414 gen_rtx_fmt_ee (code, mode, source, temp)));
1420 return arm_gen_constant (code, mode, cond, val, target, source, subtargets,
1425 count_insns_for_constant (HOST_WIDE_INT remainder, int i)
1427 HOST_WIDE_INT temp1;
1435 if (remainder & (3 << (i - 2)))
1440 temp1 = remainder & ((0x0ff << end)
1441 | ((i < end) ? (0xff >> (32 - end)) : 0));
1442 remainder &= ~temp1;
1447 } while (remainder);
1451 /* Emit an instruction with the indicated PATTERN. If COND is
1452 non-NULL, conditionalize the execution of the instruction on COND
1456 emit_constant_insn (rtx cond, rtx pattern)
1459 pattern = gen_rtx_COND_EXEC (VOIDmode, copy_rtx (cond), pattern);
1460 emit_insn (pattern);
1463 /* As above, but extra parameter GENERATE which, if clear, suppresses
1467 arm_gen_constant (enum rtx_code code, enum machine_mode mode, rtx cond,
1468 HOST_WIDE_INT val, rtx target, rtx source, int subtargets,
1473 int can_negate_initial = 0;
1476 int num_bits_set = 0;
1477 int set_sign_bit_copies = 0;
1478 int clear_sign_bit_copies = 0;
1479 int clear_zero_bit_copies = 0;
1480 int set_zero_bit_copies = 0;
1482 unsigned HOST_WIDE_INT temp1, temp2;
1483 unsigned HOST_WIDE_INT remainder = val & 0xffffffff;
1485 /* Find out which operations are safe for a given CODE. Also do a quick
1486 check for degenerate cases; these can occur when DImode operations
1498 can_negate_initial = 1;
1502 if (remainder == 0xffffffff)
1505 emit_constant_insn (cond,
1506 gen_rtx_SET (VOIDmode, target,
1507 GEN_INT (ARM_SIGN_EXTEND (val))));
1512 if (reload_completed && rtx_equal_p (target, source))
1515 emit_constant_insn (cond,
1516 gen_rtx_SET (VOIDmode, target, source));
1525 emit_constant_insn (cond,
1526 gen_rtx_SET (VOIDmode, target, const0_rtx));
1529 if (remainder == 0xffffffff)
1531 if (reload_completed && rtx_equal_p (target, source))
1534 emit_constant_insn (cond,
1535 gen_rtx_SET (VOIDmode, target, source));
1544 if (reload_completed && rtx_equal_p (target, source))
1547 emit_constant_insn (cond,
1548 gen_rtx_SET (VOIDmode, target, source));
1551 if (remainder == 0xffffffff)
1554 emit_constant_insn (cond,
1555 gen_rtx_SET (VOIDmode, target,
1556 gen_rtx_NOT (mode, source)));
1560 /* We don't know how to handle this yet below. */
1564 /* We treat MINUS as (val - source), since (source - val) is always
1565 passed as (source + (-val)). */
1569 emit_constant_insn (cond,
1570 gen_rtx_SET (VOIDmode, target,
1571 gen_rtx_NEG (mode, source)));
1574 if (const_ok_for_arm (val))
1577 emit_constant_insn (cond,
1578 gen_rtx_SET (VOIDmode, target,
1579 gen_rtx_MINUS (mode, GEN_INT (val),
1591 /* If we can do it in one insn get out quickly. */
1592 if (const_ok_for_arm (val)
1593 || (can_negate_initial && const_ok_for_arm (-val))
1594 || (can_invert && const_ok_for_arm (~val)))
1597 emit_constant_insn (cond,
1598 gen_rtx_SET (VOIDmode, target,
1600 ? gen_rtx_fmt_ee (code, mode, source,
1606 /* Calculate a few attributes that may be useful for specific
1608 for (i = 31; i >= 0; i--)
1610 if ((remainder & (1 << i)) == 0)
1611 clear_sign_bit_copies++;
1616 for (i = 31; i >= 0; i--)
1618 if ((remainder & (1 << i)) != 0)
1619 set_sign_bit_copies++;
1624 for (i = 0; i <= 31; i++)
1626 if ((remainder & (1 << i)) == 0)
1627 clear_zero_bit_copies++;
1632 for (i = 0; i <= 31; i++)
1634 if ((remainder & (1 << i)) != 0)
1635 set_zero_bit_copies++;
1643 /* See if we can do this by sign_extending a constant that is known
1644 to be negative. This is a good, way of doing it, since the shift
1645 may well merge into a subsequent insn. */
1646 if (set_sign_bit_copies > 1)
1648 if (const_ok_for_arm
1649 (temp1 = ARM_SIGN_EXTEND (remainder
1650 << (set_sign_bit_copies - 1))))
1654 rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
1655 emit_constant_insn (cond,
1656 gen_rtx_SET (VOIDmode, new_src,
1658 emit_constant_insn (cond,
1659 gen_ashrsi3 (target, new_src,
1660 GEN_INT (set_sign_bit_copies - 1)));
1664 /* For an inverted constant, we will need to set the low bits,
1665 these will be shifted out of harm's way. */
1666 temp1 |= (1 << (set_sign_bit_copies - 1)) - 1;
1667 if (const_ok_for_arm (~temp1))
1671 rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
1672 emit_constant_insn (cond,
1673 gen_rtx_SET (VOIDmode, new_src,
1675 emit_constant_insn (cond,
1676 gen_ashrsi3 (target, new_src,
1677 GEN_INT (set_sign_bit_copies - 1)));
1683 /* See if we can generate this by setting the bottom (or the top)
1684 16 bits, and then shifting these into the other half of the
1685 word. We only look for the simplest cases, to do more would cost
1686 too much. Be careful, however, not to generate this when the
1687 alternative would take fewer insns. */
1688 if (val & 0xffff0000)
1690 temp1 = remainder & 0xffff0000;
1691 temp2 = remainder & 0x0000ffff;
1693 /* Overlaps outside this range are best done using other methods. */
1694 for (i = 9; i < 24; i++)
1696 if ((((temp2 | (temp2 << i)) & 0xffffffff) == remainder)
1697 && !const_ok_for_arm (temp2))
1699 rtx new_src = (subtargets
1700 ? (generate ? gen_reg_rtx (mode) : NULL_RTX)
1702 insns = arm_gen_constant (code, mode, cond, temp2, new_src,
1703 source, subtargets, generate);
1711 gen_rtx_ASHIFT (mode, source,
1718 /* Don't duplicate cases already considered. */
1719 for (i = 17; i < 24; i++)
1721 if (((temp1 | (temp1 >> i)) == remainder)
1722 && !const_ok_for_arm (temp1))
1724 rtx new_src = (subtargets
1725 ? (generate ? gen_reg_rtx (mode) : NULL_RTX)
1727 insns = arm_gen_constant (code, mode, cond, temp1, new_src,
1728 source, subtargets, generate);
1733 gen_rtx_SET (VOIDmode, target,
1736 gen_rtx_LSHIFTRT (mode, source,
1747 /* If we have IOR or XOR, and the constant can be loaded in a
1748 single instruction, and we can find a temporary to put it in,
1749 then this can be done in two instructions instead of 3-4. */
1751 /* TARGET can't be NULL if SUBTARGETS is 0 */
1752 || (reload_completed && !reg_mentioned_p (target, source)))
1754 if (const_ok_for_arm (ARM_SIGN_EXTEND (~val)))
1758 rtx sub = subtargets ? gen_reg_rtx (mode) : target;
1760 emit_constant_insn (cond,
1761 gen_rtx_SET (VOIDmode, sub,
1763 emit_constant_insn (cond,
1764 gen_rtx_SET (VOIDmode, target,
1765 gen_rtx_fmt_ee (code, mode,
1775 if (set_sign_bit_copies > 8
1776 && (val & (-1 << (32 - set_sign_bit_copies))) == val)
1780 rtx sub = subtargets ? gen_reg_rtx (mode) : target;
1781 rtx shift = GEN_INT (set_sign_bit_copies);
1785 gen_rtx_SET (VOIDmode, sub,
1787 gen_rtx_ASHIFT (mode,
1792 gen_rtx_SET (VOIDmode, target,
1794 gen_rtx_LSHIFTRT (mode, sub,
1800 if (set_zero_bit_copies > 8
1801 && (remainder & ((1 << set_zero_bit_copies) - 1)) == remainder)
1805 rtx sub = subtargets ? gen_reg_rtx (mode) : target;
1806 rtx shift = GEN_INT (set_zero_bit_copies);
1810 gen_rtx_SET (VOIDmode, sub,
1812 gen_rtx_LSHIFTRT (mode,
1817 gen_rtx_SET (VOIDmode, target,
1819 gen_rtx_ASHIFT (mode, sub,
1825 if (const_ok_for_arm (temp1 = ARM_SIGN_EXTEND (~val)))
1829 rtx sub = subtargets ? gen_reg_rtx (mode) : target;
1830 emit_constant_insn (cond,
1831 gen_rtx_SET (VOIDmode, sub,
1832 gen_rtx_NOT (mode, source)));
1835 sub = gen_reg_rtx (mode);
1836 emit_constant_insn (cond,
1837 gen_rtx_SET (VOIDmode, sub,
1838 gen_rtx_AND (mode, source,
1840 emit_constant_insn (cond,
1841 gen_rtx_SET (VOIDmode, target,
1842 gen_rtx_NOT (mode, sub)));
1849 /* See if two shifts will do 2 or more insn's worth of work. */
1850 if (clear_sign_bit_copies >= 16 && clear_sign_bit_copies < 24)
1852 HOST_WIDE_INT shift_mask = ((0xffffffff
1853 << (32 - clear_sign_bit_copies))
1856 if ((remainder | shift_mask) != 0xffffffff)
1860 rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
1861 insns = arm_gen_constant (AND, mode, cond,
1862 remainder | shift_mask,
1863 new_src, source, subtargets, 1);
1868 rtx targ = subtargets ? NULL_RTX : target;
1869 insns = arm_gen_constant (AND, mode, cond,
1870 remainder | shift_mask,
1871 targ, source, subtargets, 0);
1877 rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
1878 rtx shift = GEN_INT (clear_sign_bit_copies);
1880 emit_insn (gen_ashlsi3 (new_src, source, shift));
1881 emit_insn (gen_lshrsi3 (target, new_src, shift));
1887 if (clear_zero_bit_copies >= 16 && clear_zero_bit_copies < 24)
1889 HOST_WIDE_INT shift_mask = (1 << clear_zero_bit_copies) - 1;
1891 if ((remainder | shift_mask) != 0xffffffff)
1895 rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
1897 insns = arm_gen_constant (AND, mode, cond,
1898 remainder | shift_mask,
1899 new_src, source, subtargets, 1);
1904 rtx targ = subtargets ? NULL_RTX : target;
1906 insns = arm_gen_constant (AND, mode, cond,
1907 remainder | shift_mask,
1908 targ, source, subtargets, 0);
1914 rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
1915 rtx shift = GEN_INT (clear_zero_bit_copies);
1917 emit_insn (gen_lshrsi3 (new_src, source, shift));
1918 emit_insn (gen_ashlsi3 (target, new_src, shift));
1930 for (i = 0; i < 32; i++)
1931 if (remainder & (1 << i))
1934 if (code == AND || (can_invert && num_bits_set > 16))
1935 remainder = (~remainder) & 0xffffffff;
1936 else if (code == PLUS && num_bits_set > 16)
1937 remainder = (-remainder) & 0xffffffff;
1944 /* Now try and find a way of doing the job in either two or three
1946 We start by looking for the largest block of zeros that are aligned on
1947 a 2-bit boundary, we then fill up the temps, wrapping around to the
1948 top of the word when we drop off the bottom.
1949 In the worst case this code should produce no more than four insns. */
1952 int best_consecutive_zeros = 0;
1954 for (i = 0; i < 32; i += 2)
1956 int consecutive_zeros = 0;
1958 if (!(remainder & (3 << i)))
1960 while ((i < 32) && !(remainder & (3 << i)))
1962 consecutive_zeros += 2;
1965 if (consecutive_zeros > best_consecutive_zeros)
1967 best_consecutive_zeros = consecutive_zeros;
1968 best_start = i - consecutive_zeros;
1974 /* So long as it won't require any more insns to do so, it's
1975 desirable to emit a small constant (in bits 0...9) in the last
1976 insn. This way there is more chance that it can be combined with
1977 a later addressing insn to form a pre-indexed load or store
1978 operation. Consider:
1980 *((volatile int *)0xe0000100) = 1;
1981 *((volatile int *)0xe0000110) = 2;
1983 We want this to wind up as:
1987 str rB, [rA, #0x100]
1989 str rB, [rA, #0x110]
1991 rather than having to synthesize both large constants from scratch.
1993 Therefore, we calculate how many insns would be required to emit
1994 the constant starting from `best_start', and also starting from
1995 zero (ie with bit 31 first to be output). If `best_start' doesn't
1996 yield a shorter sequence, we may as well use zero. */
1998 && ((((unsigned HOST_WIDE_INT) 1) << best_start) < remainder)
1999 && (count_insns_for_constant (remainder, 0) <=
2000 count_insns_for_constant (remainder, best_start)))
2003 /* Now start emitting the insns. */
2011 if (remainder & (3 << (i - 2)))
2016 temp1 = remainder & ((0x0ff << end)
2017 | ((i < end) ? (0xff >> (32 - end)) : 0));
2018 remainder &= ~temp1;
2022 rtx new_src, temp1_rtx;
2024 if (code == SET || code == MINUS)
2026 new_src = (subtargets ? gen_reg_rtx (mode) : target);
2027 if (can_invert && code != MINUS)
2032 if (remainder && subtargets)
2033 new_src = gen_reg_rtx (mode);
2038 else if (can_negate)
2042 temp1 = trunc_int_for_mode (temp1, mode);
2043 temp1_rtx = GEN_INT (temp1);
2047 else if (code == MINUS)
2048 temp1_rtx = gen_rtx_MINUS (mode, temp1_rtx, source);
2050 temp1_rtx = gen_rtx_fmt_ee (code, mode, source, temp1_rtx);
2052 emit_constant_insn (cond,
2053 gen_rtx_SET (VOIDmode, new_src,
2063 else if (code == MINUS)
2077 /* Canonicalize a comparison so that we are more likely to recognize it.
2078 This can be done for a few constant compares, where we can make the
2079 immediate value easier to load. */
2082 arm_canonicalize_comparison (enum rtx_code code, rtx * op1)
2084 unsigned HOST_WIDE_INT i = INTVAL (*op1);
2094 if (i != ((((unsigned HOST_WIDE_INT) 1) << (HOST_BITS_PER_WIDE_INT - 1)) - 1)
2095 && (const_ok_for_arm (i + 1) || const_ok_for_arm (-(i + 1))))
2097 *op1 = GEN_INT (i + 1);
2098 return code == GT ? GE : LT;
2104 if (i != (((unsigned HOST_WIDE_INT) 1) << (HOST_BITS_PER_WIDE_INT - 1))
2105 && (const_ok_for_arm (i - 1) || const_ok_for_arm (-(i - 1))))
2107 *op1 = GEN_INT (i - 1);
2108 return code == GE ? GT : LE;
2114 if (i != ~((unsigned HOST_WIDE_INT) 0)
2115 && (const_ok_for_arm (i + 1) || const_ok_for_arm (-(i + 1))))
2117 *op1 = GEN_INT (i + 1);
2118 return code == GTU ? GEU : LTU;
2125 && (const_ok_for_arm (i - 1) || const_ok_for_arm (-(i - 1))))
2127 *op1 = GEN_INT (i - 1);
2128 return code == GEU ? GTU : LEU;
2140 /* Define how to find the value returned by a function. */
2142 rtx arm_function_value(tree type, tree func ATTRIBUTE_UNUSED)
2144 enum machine_mode mode;
2145 int unsignedp ATTRIBUTE_UNUSED;
2146 rtx r ATTRIBUTE_UNUSED;
2149 mode = TYPE_MODE (type);
2150 /* Promote integer types. */
2151 if (INTEGRAL_TYPE_P (type))
2152 PROMOTE_FUNCTION_MODE (mode, unsignedp, type);
2153 return LIBCALL_VALUE(mode);
2157 /* Decide whether a type should be returned in memory (true)
2158 or in a register (false). This is called by the macro
2159 RETURN_IN_MEMORY. */
2161 arm_return_in_memory (tree type)
2165 if (!AGGREGATE_TYPE_P (type))
2166 /* All simple types are returned in registers. */
2169 size = int_size_in_bytes (type);
2171 if (arm_abi != ARM_ABI_APCS)
2173 /* ATPCS and later return aggregate types in memory only if they are
2174 larger than a word (or are variable size). */
2175 return (size < 0 || size > UNITS_PER_WORD);
2178 /* For the arm-wince targets we choose to be compatible with Microsoft's
2179 ARM and Thumb compilers, which always return aggregates in memory. */
2181 /* All structures/unions bigger than one word are returned in memory.
2182 Also catch the case where int_size_in_bytes returns -1. In this case
2183 the aggregate is either huge or of variable size, and in either case
2184 we will want to return it via memory and not in a register. */
2185 if (size < 0 || size > UNITS_PER_WORD)
2188 if (TREE_CODE (type) == RECORD_TYPE)
2192 /* For a struct the APCS says that we only return in a register
2193 if the type is 'integer like' and every addressable element
2194 has an offset of zero. For practical purposes this means
2195 that the structure can have at most one non bit-field element
2196 and that this element must be the first one in the structure. */
2198 /* Find the first field, ignoring non FIELD_DECL things which will
2199 have been created by C++. */
2200 for (field = TYPE_FIELDS (type);
2201 field && TREE_CODE (field) != FIELD_DECL;
2202 field = TREE_CHAIN (field))
2206 return 0; /* An empty structure. Allowed by an extension to ANSI C. */
2208 /* Check that the first field is valid for returning in a register. */
2210 /* ... Floats are not allowed */
2211 if (FLOAT_TYPE_P (TREE_TYPE (field)))
2214 /* ... Aggregates that are not themselves valid for returning in
2215 a register are not allowed. */
2216 if (RETURN_IN_MEMORY (TREE_TYPE (field)))
2219 /* Now check the remaining fields, if any. Only bitfields are allowed,
2220 since they are not addressable. */
2221 for (field = TREE_CHAIN (field);
2223 field = TREE_CHAIN (field))
2225 if (TREE_CODE (field) != FIELD_DECL)
2228 if (!DECL_BIT_FIELD_TYPE (field))
2235 if (TREE_CODE (type) == UNION_TYPE)
2239 /* Unions can be returned in registers if every element is
2240 integral, or can be returned in an integer register. */
2241 for (field = TYPE_FIELDS (type);
2243 field = TREE_CHAIN (field))
2245 if (TREE_CODE (field) != FIELD_DECL)
2248 if (FLOAT_TYPE_P (TREE_TYPE (field)))
2251 if (RETURN_IN_MEMORY (TREE_TYPE (field)))
2257 #endif /* not ARM_WINCE */
2259 /* Return all other types in memory. */
2263 /* Indicate whether or not words of a double are in big-endian order. */
2266 arm_float_words_big_endian (void)
2268 if (TARGET_MAVERICK)
2271 /* For FPA, float words are always big-endian. For VFP, floats words
2272 follow the memory system mode. */
2280 return (TARGET_BIG_END ? 1 : 0);
2285 /* Initialize a variable CUM of type CUMULATIVE_ARGS
2286 for a call to a function whose data type is FNTYPE.
2287 For a library call, FNTYPE is NULL. */
2289 arm_init_cumulative_args (CUMULATIVE_ARGS *pcum, tree fntype,
2290 rtx libname ATTRIBUTE_UNUSED,
2291 tree fndecl ATTRIBUTE_UNUSED)
2293 /* On the ARM, the offset starts at 0. */
2294 pcum->nregs = ((fntype && aggregate_value_p (TREE_TYPE (fntype), fntype)) ? 1 : 0);
2295 pcum->iwmmxt_nregs = 0;
2296 pcum->can_split = true;
2298 pcum->call_cookie = CALL_NORMAL;
2300 if (TARGET_LONG_CALLS)
2301 pcum->call_cookie = CALL_LONG;
2303 /* Check for long call/short call attributes. The attributes
2304 override any command line option. */
2307 if (lookup_attribute ("short_call", TYPE_ATTRIBUTES (fntype)))
2308 pcum->call_cookie = CALL_SHORT;
2309 else if (lookup_attribute ("long_call", TYPE_ATTRIBUTES (fntype)))
2310 pcum->call_cookie = CALL_LONG;
2313 /* Varargs vectors are treated the same as long long.
2314 named_count avoids having to change the way arm handles 'named' */
2315 pcum->named_count = 0;
2318 if (TARGET_REALLY_IWMMXT && fntype)
2322 for (fn_arg = TYPE_ARG_TYPES (fntype);
2324 fn_arg = TREE_CHAIN (fn_arg))
2325 pcum->named_count += 1;
2327 if (! pcum->named_count)
2328 pcum->named_count = INT_MAX;
2333 /* Return true if mode/type need doubleword alignment. */
2335 arm_needs_doubleword_align (enum machine_mode mode, tree type)
2337 return (GET_MODE_ALIGNMENT (mode) > PARM_BOUNDARY
2338 || (type && TYPE_ALIGN (type) > PARM_BOUNDARY));
2342 /* Determine where to put an argument to a function.
2343 Value is zero to push the argument on the stack,
2344 or a hard register in which to store the argument.
2346 MODE is the argument's machine mode.
2347 TYPE is the data type of the argument (as a tree).
2348 This is null for libcalls where that information may
2350 CUM is a variable of type CUMULATIVE_ARGS which gives info about
2351 the preceding args and about the function being called.
2352 NAMED is nonzero if this argument is a named parameter
2353 (otherwise it is an extra parameter matching an ellipsis). */
2356 arm_function_arg (CUMULATIVE_ARGS *pcum, enum machine_mode mode,
2357 tree type, int named)
2361 /* Varargs vectors are treated the same as long long.
2362 named_count avoids having to change the way arm handles 'named' */
2363 if (TARGET_IWMMXT_ABI
2364 && VECTOR_MODE_SUPPORTED_P (mode)
2365 && pcum->named_count > pcum->nargs + 1)
2367 if (pcum->iwmmxt_nregs <= 9)
2368 return gen_rtx_REG (mode, pcum->iwmmxt_nregs + FIRST_IWMMXT_REGNUM);
2371 pcum->can_split = false;
2376 /* Put doubleword aligned quantities in even register pairs. */
2378 && ARM_DOUBLEWORD_ALIGN
2379 && arm_needs_doubleword_align (mode, type))
2382 if (mode == VOIDmode)
2383 /* Compute operand 2 of the call insn. */
2384 return GEN_INT (pcum->call_cookie);
2386 /* Only allow splitting an arg between regs and memory if all preceding
2387 args were allocated to regs. For args passed by reference we only count
2388 the reference pointer. */
2389 if (pcum->can_split)
2392 nregs = ARM_NUM_REGS2 (mode, type);
2394 if (!named || pcum->nregs + nregs > NUM_ARG_REGS)
2397 return gen_rtx_REG (mode, pcum->nregs);
2400 /* Variable sized types are passed by reference. This is a GCC
2401 extension to the ARM ABI. */
2404 arm_pass_by_reference (CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED,
2405 enum machine_mode mode ATTRIBUTE_UNUSED,
2406 tree type, bool named ATTRIBUTE_UNUSED)
2408 return type && TREE_CODE (TYPE_SIZE (type)) != INTEGER_CST;
2411 /* Encode the current state of the #pragma [no_]long_calls. */
2414 OFF, /* No #pramgma [no_]long_calls is in effect. */
2415 LONG, /* #pragma long_calls is in effect. */
2416 SHORT /* #pragma no_long_calls is in effect. */
2419 static arm_pragma_enum arm_pragma_long_calls = OFF;
2422 arm_pr_long_calls (struct cpp_reader * pfile ATTRIBUTE_UNUSED)
2424 arm_pragma_long_calls = LONG;
2428 arm_pr_no_long_calls (struct cpp_reader * pfile ATTRIBUTE_UNUSED)
2430 arm_pragma_long_calls = SHORT;
2434 arm_pr_long_calls_off (struct cpp_reader * pfile ATTRIBUTE_UNUSED)
2436 arm_pragma_long_calls = OFF;
2439 /* Table of machine attributes. */
2440 const struct attribute_spec arm_attribute_table[] =
2442 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
2443 /* Function calls made to this symbol must be done indirectly, because
2444 it may lie outside of the 26 bit addressing range of a normal function
2446 { "long_call", 0, 0, false, true, true, NULL },
2447 /* Whereas these functions are always known to reside within the 26 bit
2448 addressing range. */
2449 { "short_call", 0, 0, false, true, true, NULL },
2450 /* Interrupt Service Routines have special prologue and epilogue requirements. */
2451 { "isr", 0, 1, false, false, false, arm_handle_isr_attribute },
2452 { "interrupt", 0, 1, false, false, false, arm_handle_isr_attribute },
2453 { "naked", 0, 0, true, false, false, arm_handle_fndecl_attribute },
2455 /* ARM/PE has three new attributes:
2457 dllexport - for exporting a function/variable that will live in a dll
2458 dllimport - for importing a function/variable from a dll
2460 Microsoft allows multiple declspecs in one __declspec, separating
2461 them with spaces. We do NOT support this. Instead, use __declspec
2464 { "dllimport", 0, 0, true, false, false, NULL },
2465 { "dllexport", 0, 0, true, false, false, NULL },
2466 { "interfacearm", 0, 0, true, false, false, arm_handle_fndecl_attribute },
2468 { NULL, 0, 0, false, false, false, NULL }
2471 /* Handle an attribute requiring a FUNCTION_DECL;
2472 arguments as in struct attribute_spec.handler. */
2474 arm_handle_fndecl_attribute (tree *node, tree name, tree args ATTRIBUTE_UNUSED,
2475 int flags ATTRIBUTE_UNUSED, bool *no_add_attrs)
2477 if (TREE_CODE (*node) != FUNCTION_DECL)
2479 warning ("`%s' attribute only applies to functions",
2480 IDENTIFIER_POINTER (name));
2481 *no_add_attrs = true;
2487 /* Handle an "interrupt" or "isr" attribute;
2488 arguments as in struct attribute_spec.handler. */
2490 arm_handle_isr_attribute (tree *node, tree name, tree args, int flags,
2495 if (TREE_CODE (*node) != FUNCTION_DECL)
2497 warning ("`%s' attribute only applies to functions",
2498 IDENTIFIER_POINTER (name));
2499 *no_add_attrs = true;
2501 /* FIXME: the argument if any is checked for type attributes;
2502 should it be checked for decl ones? */
2506 if (TREE_CODE (*node) == FUNCTION_TYPE
2507 || TREE_CODE (*node) == METHOD_TYPE)
2509 if (arm_isr_value (args) == ARM_FT_UNKNOWN)
2511 warning ("`%s' attribute ignored", IDENTIFIER_POINTER (name));
2512 *no_add_attrs = true;
2515 else if (TREE_CODE (*node) == POINTER_TYPE
2516 && (TREE_CODE (TREE_TYPE (*node)) == FUNCTION_TYPE
2517 || TREE_CODE (TREE_TYPE (*node)) == METHOD_TYPE)
2518 && arm_isr_value (args) != ARM_FT_UNKNOWN)
2520 *node = build_type_copy (*node);
2521 TREE_TYPE (*node) = build_type_attribute_variant
2523 tree_cons (name, args, TYPE_ATTRIBUTES (TREE_TYPE (*node))));
2524 *no_add_attrs = true;
2528 /* Possibly pass this attribute on from the type to a decl. */
2529 if (flags & ((int) ATTR_FLAG_DECL_NEXT
2530 | (int) ATTR_FLAG_FUNCTION_NEXT
2531 | (int) ATTR_FLAG_ARRAY_NEXT))
2533 *no_add_attrs = true;
2534 return tree_cons (name, args, NULL_TREE);
2538 warning ("`%s' attribute ignored", IDENTIFIER_POINTER (name));
2546 /* Return 0 if the attributes for two types are incompatible, 1 if they
2547 are compatible, and 2 if they are nearly compatible (which causes a
2548 warning to be generated). */
2550 arm_comp_type_attributes (tree type1, tree type2)
2554 /* Check for mismatch of non-default calling convention. */
2555 if (TREE_CODE (type1) != FUNCTION_TYPE)
2558 /* Check for mismatched call attributes. */
2559 l1 = lookup_attribute ("long_call", TYPE_ATTRIBUTES (type1)) != NULL;
2560 l2 = lookup_attribute ("long_call", TYPE_ATTRIBUTES (type2)) != NULL;
2561 s1 = lookup_attribute ("short_call", TYPE_ATTRIBUTES (type1)) != NULL;
2562 s2 = lookup_attribute ("short_call", TYPE_ATTRIBUTES (type2)) != NULL;
2564 /* Only bother to check if an attribute is defined. */
2565 if (l1 | l2 | s1 | s2)
2567 /* If one type has an attribute, the other must have the same attribute. */
2568 if ((l1 != l2) || (s1 != s2))
2571 /* Disallow mixed attributes. */
2572 if ((l1 & s2) || (l2 & s1))
2576 /* Check for mismatched ISR attribute. */
2577 l1 = lookup_attribute ("isr", TYPE_ATTRIBUTES (type1)) != NULL;
2579 l1 = lookup_attribute ("interrupt", TYPE_ATTRIBUTES (type1)) != NULL;
2580 l2 = lookup_attribute ("isr", TYPE_ATTRIBUTES (type2)) != NULL;
2582 l1 = lookup_attribute ("interrupt", TYPE_ATTRIBUTES (type2)) != NULL;
2589 /* Encode long_call or short_call attribute by prefixing
2590 symbol name in DECL with a special character FLAG. */
2592 arm_encode_call_attribute (tree decl, int flag)
2594 const char * str = XSTR (XEXP (DECL_RTL (decl), 0), 0);
2595 int len = strlen (str);
2598 /* Do not allow weak functions to be treated as short call. */
2599 if (DECL_WEAK (decl) && flag == SHORT_CALL_FLAG_CHAR)
2602 newstr = alloca (len + 2);
2604 strcpy (newstr + 1, str);
2606 newstr = (char *) ggc_alloc_string (newstr, len + 1);
2607 XSTR (XEXP (DECL_RTL (decl), 0), 0) = newstr;
2610 /* Assigns default attributes to newly defined type. This is used to
2611 set short_call/long_call attributes for function types of
2612 functions defined inside corresponding #pragma scopes. */
2614 arm_set_default_type_attributes (tree type)
2616 /* Add __attribute__ ((long_call)) to all functions, when
2617 inside #pragma long_calls or __attribute__ ((short_call)),
2618 when inside #pragma no_long_calls. */
2619 if (TREE_CODE (type) == FUNCTION_TYPE || TREE_CODE (type) == METHOD_TYPE)
2621 tree type_attr_list, attr_name;
2622 type_attr_list = TYPE_ATTRIBUTES (type);
2624 if (arm_pragma_long_calls == LONG)
2625 attr_name = get_identifier ("long_call");
2626 else if (arm_pragma_long_calls == SHORT)
2627 attr_name = get_identifier ("short_call");
2631 type_attr_list = tree_cons (attr_name, NULL_TREE, type_attr_list);
2632 TYPE_ATTRIBUTES (type) = type_attr_list;
2636 /* Return 1 if the operand is a SYMBOL_REF for a function known to be
2637 defined within the current compilation unit. If this cannot be
2638 determined, then 0 is returned. */
2640 current_file_function_operand (rtx sym_ref)
2642 /* This is a bit of a fib. A function will have a short call flag
2643 applied to its name if it has the short call attribute, or it has
2644 already been defined within the current compilation unit. */
2645 if (ENCODED_SHORT_CALL_ATTR_P (XSTR (sym_ref, 0)))
2648 /* The current function is always defined within the current compilation
2649 unit. if it s a weak definition however, then this may not be the real
2650 definition of the function, and so we have to say no. */
2651 if (sym_ref == XEXP (DECL_RTL (current_function_decl), 0)
2652 && !DECL_WEAK (current_function_decl))
2655 /* We cannot make the determination - default to returning 0. */
2659 /* Return nonzero if a 32 bit "long_call" should be generated for
2660 this call. We generate a long_call if the function:
2662 a. has an __attribute__((long call))
2663 or b. is within the scope of a #pragma long_calls
2664 or c. the -mlong-calls command line switch has been specified
2666 However we do not generate a long call if the function:
2668 d. has an __attribute__ ((short_call))
2669 or e. is inside the scope of a #pragma no_long_calls
2670 or f. has an __attribute__ ((section))
2671 or g. is defined within the current compilation unit.
2673 This function will be called by C fragments contained in the machine
2674 description file. CALL_REF and CALL_COOKIE correspond to the matched
2675 rtl operands. CALL_SYMBOL is used to distinguish between
2676 two different callers of the function. It is set to 1 in the
2677 "call_symbol" and "call_symbol_value" patterns and to 0 in the "call"
2678 and "call_value" patterns. This is because of the difference in the
2679 SYM_REFs passed by these patterns. */
2681 arm_is_longcall_p (rtx sym_ref, int call_cookie, int call_symbol)
2685 if (GET_CODE (sym_ref) != MEM)
2688 sym_ref = XEXP (sym_ref, 0);
2691 if (GET_CODE (sym_ref) != SYMBOL_REF)
2694 if (call_cookie & CALL_SHORT)
2697 if (TARGET_LONG_CALLS && flag_function_sections)
2700 if (current_file_function_operand (sym_ref))
2703 return (call_cookie & CALL_LONG)
2704 || ENCODED_LONG_CALL_ATTR_P (XSTR (sym_ref, 0))
2705 || TARGET_LONG_CALLS;
2708 /* Return nonzero if it is ok to make a tail-call to DECL. */
2710 arm_function_ok_for_sibcall (tree decl, tree exp ATTRIBUTE_UNUSED)
2712 int call_type = TARGET_LONG_CALLS ? CALL_LONG : CALL_NORMAL;
2714 if (cfun->machine->sibcall_blocked)
2717 /* Never tailcall something for which we have no decl, or if we
2718 are in Thumb mode. */
2719 if (decl == NULL || TARGET_THUMB)
2722 /* Get the calling method. */
2723 if (lookup_attribute ("short_call", TYPE_ATTRIBUTES (TREE_TYPE (decl))))
2724 call_type = CALL_SHORT;
2725 else if (lookup_attribute ("long_call", TYPE_ATTRIBUTES (TREE_TYPE (decl))))
2726 call_type = CALL_LONG;
2728 /* Cannot tail-call to long calls, since these are out of range of
2729 a branch instruction. However, if not compiling PIC, we know
2730 we can reach the symbol if it is in this compilation unit. */
2731 if (call_type == CALL_LONG && (flag_pic || !TREE_ASM_WRITTEN (decl)))
2734 /* If we are interworking and the function is not declared static
2735 then we can't tail-call it unless we know that it exists in this
2736 compilation unit (since it might be a Thumb routine). */
2737 if (TARGET_INTERWORK && TREE_PUBLIC (decl) && !TREE_ASM_WRITTEN (decl))
2740 /* Never tailcall from an ISR routine - it needs a special exit sequence. */
2741 if (IS_INTERRUPT (arm_current_func_type ()))
2744 /* Everything else is ok. */
2749 /* Addressing mode support functions. */
2751 /* Return nonzero if X is a legitimate immediate operand when compiling
2754 legitimate_pic_operand_p (rtx x)
2758 && (GET_CODE (x) == SYMBOL_REF
2759 || (GET_CODE (x) == CONST
2760 && GET_CODE (XEXP (x, 0)) == PLUS
2761 && GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF)))
2768 legitimize_pic_address (rtx orig, enum machine_mode mode, rtx reg)
2770 if (GET_CODE (orig) == SYMBOL_REF
2771 || GET_CODE (orig) == LABEL_REF)
2773 #ifndef AOF_ASSEMBLER
2774 rtx pic_ref, address;
2784 reg = gen_reg_rtx (Pmode);
2789 #ifdef AOF_ASSEMBLER
2790 /* The AOF assembler can generate relocations for these directly, and
2791 understands that the PIC register has to be added into the offset. */
2792 insn = emit_insn (gen_pic_load_addr_based (reg, orig));
2795 address = gen_reg_rtx (Pmode);
2800 emit_insn (gen_pic_load_addr_arm (address, orig));
2802 emit_insn (gen_pic_load_addr_thumb (address, orig));
2804 if ((GET_CODE (orig) == LABEL_REF
2805 || (GET_CODE (orig) == SYMBOL_REF &&
2806 SYMBOL_REF_LOCAL_P (orig)))
2808 pic_ref = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, address);
2811 pic_ref = gen_rtx_MEM (Pmode,
2812 gen_rtx_PLUS (Pmode, pic_offset_table_rtx,
2814 RTX_UNCHANGING_P (pic_ref) = 1;
2817 insn = emit_move_insn (reg, pic_ref);
2819 current_function_uses_pic_offset_table = 1;
2820 /* Put a REG_EQUAL note on this insn, so that it can be optimized
2822 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_EQUAL, orig,
2826 else if (GET_CODE (orig) == CONST)
2830 if (GET_CODE (XEXP (orig, 0)) == PLUS
2831 && XEXP (XEXP (orig, 0), 0) == pic_offset_table_rtx)
2839 reg = gen_reg_rtx (Pmode);
2842 if (GET_CODE (XEXP (orig, 0)) == PLUS)
2844 base = legitimize_pic_address (XEXP (XEXP (orig, 0), 0), Pmode, reg);
2845 offset = legitimize_pic_address (XEXP (XEXP (orig, 0), 1), Pmode,
2846 base == reg ? 0 : reg);
2851 if (GET_CODE (offset) == CONST_INT)
2853 /* The base register doesn't really matter, we only want to
2854 test the index for the appropriate mode. */
2855 if (!arm_legitimate_index_p (mode, offset, SET, 0))
2857 if (!no_new_pseudos)
2858 offset = force_reg (Pmode, offset);
2863 if (GET_CODE (offset) == CONST_INT)
2864 return plus_constant (base, INTVAL (offset));
2867 if (GET_MODE_SIZE (mode) > 4
2868 && (GET_MODE_CLASS (mode) == MODE_INT
2869 || TARGET_SOFT_FLOAT))
2871 emit_insn (gen_addsi3 (reg, base, offset));
2875 return gen_rtx_PLUS (Pmode, base, offset);
2881 /* Generate code to load the PIC register. PROLOGUE is true if
2882 called from arm_expand_prologue (in which case we want the
2883 generated insns at the start of the function); false if called
2884 by an exception receiver that needs the PIC register reloaded
2885 (in which case the insns are just dumped at the current location). */
2887 arm_finalize_pic (int prologue ATTRIBUTE_UNUSED)
2889 #ifndef AOF_ASSEMBLER
2890 rtx l1, pic_tmp, pic_tmp2, seq, pic_rtx;
2891 rtx global_offset_table;
2893 if (current_function_uses_pic_offset_table == 0 || TARGET_SINGLE_PIC_BASE)
2900 l1 = gen_label_rtx ();
2902 global_offset_table = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
2903 /* On the ARM the PC register contains 'dot + 8' at the time of the
2904 addition, on the Thumb it is 'dot + 4'. */
2905 pic_tmp = plus_constant (gen_rtx_LABEL_REF (Pmode, l1), TARGET_ARM ? 8 : 4);
2907 pic_tmp2 = gen_rtx_CONST (VOIDmode,
2908 gen_rtx_PLUS (Pmode, global_offset_table, pc_rtx));
2910 pic_tmp2 = gen_rtx_CONST (VOIDmode, global_offset_table);
2912 pic_rtx = gen_rtx_CONST (Pmode, gen_rtx_MINUS (Pmode, pic_tmp2, pic_tmp));
2916 emit_insn (gen_pic_load_addr_arm (pic_offset_table_rtx, pic_rtx));
2917 emit_insn (gen_pic_add_dot_plus_eight (pic_offset_table_rtx, l1));
2921 emit_insn (gen_pic_load_addr_thumb (pic_offset_table_rtx, pic_rtx));
2922 emit_insn (gen_pic_add_dot_plus_four (pic_offset_table_rtx, l1));
2928 emit_insn_after (seq, get_insns ());
2932 /* Need to emit this whether or not we obey regdecls,
2933 since setjmp/longjmp can cause life info to screw up. */
2934 emit_insn (gen_rtx_USE (VOIDmode, pic_offset_table_rtx));
2935 #endif /* AOF_ASSEMBLER */
2938 /* Return nonzero if X is valid as an ARM state addressing register. */
2940 arm_address_register_rtx_p (rtx x, int strict_p)
2944 if (GET_CODE (x) != REG)
2950 return ARM_REGNO_OK_FOR_BASE_P (regno);
2952 return (regno <= LAST_ARM_REGNUM
2953 || regno >= FIRST_PSEUDO_REGISTER
2954 || regno == FRAME_POINTER_REGNUM
2955 || regno == ARG_POINTER_REGNUM);
2958 /* Return nonzero if X is a valid ARM state address operand. */
2960 arm_legitimate_address_p (enum machine_mode mode, rtx x, RTX_CODE outer,
2964 enum rtx_code code = GET_CODE (x);
2966 if (arm_address_register_rtx_p (x, strict_p))
2969 use_ldrd = (TARGET_LDRD
2971 || (mode == DFmode && (TARGET_SOFT_FLOAT || TARGET_VFP))));
2973 if (code == POST_INC || code == PRE_DEC
2974 || ((code == PRE_INC || code == POST_DEC)
2975 && (use_ldrd || GET_MODE_SIZE (mode) <= 4)))
2976 return arm_address_register_rtx_p (XEXP (x, 0), strict_p);
2978 else if ((code == POST_MODIFY || code == PRE_MODIFY)
2979 && arm_address_register_rtx_p (XEXP (x, 0), strict_p)
2980 && GET_CODE (XEXP (x, 1)) == PLUS
2981 && rtx_equal_p (XEXP (XEXP (x, 1), 0), XEXP (x, 0)))
2983 rtx addend = XEXP (XEXP (x, 1), 1);
2985 /* Don't allow ldrd post increment by register becuase it's hard
2986 to fixup invalid register choices. */
2988 && GET_CODE (x) == POST_MODIFY
2989 && GET_CODE (addend) == REG)
2992 return ((use_ldrd || GET_MODE_SIZE (mode) <= 4)
2993 && arm_legitimate_index_p (mode, addend, outer, strict_p));
2996 /* After reload constants split into minipools will have addresses
2997 from a LABEL_REF. */
2998 else if (reload_completed
2999 && (code == LABEL_REF
3001 && GET_CODE (XEXP (x, 0)) == PLUS
3002 && GET_CODE (XEXP (XEXP (x, 0), 0)) == LABEL_REF
3003 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT)))
3006 else if (mode == TImode)
3009 else if (code == PLUS)
3011 rtx xop0 = XEXP (x, 0);
3012 rtx xop1 = XEXP (x, 1);
3014 return ((arm_address_register_rtx_p (xop0, strict_p)
3015 && arm_legitimate_index_p (mode, xop1, outer, strict_p))
3016 || (arm_address_register_rtx_p (xop1, strict_p)
3017 && arm_legitimate_index_p (mode, xop0, outer, strict_p)));
3021 /* Reload currently can't handle MINUS, so disable this for now */
3022 else if (GET_CODE (x) == MINUS)
3024 rtx xop0 = XEXP (x, 0);
3025 rtx xop1 = XEXP (x, 1);
3027 return (arm_address_register_rtx_p (xop0, strict_p)
3028 && arm_legitimate_index_p (mode, xop1, outer, strict_p));
3032 else if (GET_MODE_CLASS (mode) != MODE_FLOAT
3033 && code == SYMBOL_REF
3034 && CONSTANT_POOL_ADDRESS_P (x)
3036 && symbol_mentioned_p (get_pool_constant (x))))
3042 /* Return nonzero if INDEX is valid for an address index operand in
3045 arm_legitimate_index_p (enum machine_mode mode, rtx index, RTX_CODE outer,
3048 HOST_WIDE_INT range;
3049 enum rtx_code code = GET_CODE (index);
3051 /* Standard coprocessor addressing modes. */
3052 if (TARGET_HARD_FLOAT
3053 && (TARGET_FPA || TARGET_MAVERICK)
3054 && (GET_MODE_CLASS (mode) == MODE_FLOAT
3055 || (TARGET_MAVERICK && mode == DImode)))
3056 return (code == CONST_INT && INTVAL (index) < 1024
3057 && INTVAL (index) > -1024
3058 && (INTVAL (index) & 3) == 0);
3060 if (TARGET_REALLY_IWMMXT && VALID_IWMMXT_REG_MODE (mode))
3061 return (code == CONST_INT
3062 && INTVAL (index) < 1024
3063 && INTVAL (index) > -1024
3064 && (INTVAL (index) & 3) == 0);
3066 if (arm_address_register_rtx_p (index, strict_p)
3067 && (GET_MODE_SIZE (mode) <= 4))
3070 if (mode == DImode || mode == DFmode)
3072 if (code == CONST_INT)
3074 HOST_WIDE_INT val = INTVAL (index);
3077 return val > -256 && val < 256;
3079 return val > -4096 && val < 4092;
3082 return TARGET_LDRD && arm_address_register_rtx_p (index, strict_p);
3085 if (GET_MODE_SIZE (mode) <= 4
3088 || (mode == QImode && outer == SIGN_EXTEND))))
3092 rtx xiop0 = XEXP (index, 0);
3093 rtx xiop1 = XEXP (index, 1);
3095 return ((arm_address_register_rtx_p (xiop0, strict_p)
3096 && power_of_two_operand (xiop1, SImode))
3097 || (arm_address_register_rtx_p (xiop1, strict_p)
3098 && power_of_two_operand (xiop0, SImode)));
3100 else if (code == LSHIFTRT || code == ASHIFTRT
3101 || code == ASHIFT || code == ROTATERT)
3103 rtx op = XEXP (index, 1);
3105 return (arm_address_register_rtx_p (XEXP (index, 0), strict_p)
3106 && GET_CODE (op) == CONST_INT
3108 && INTVAL (op) <= 31);
3112 /* For ARM v4 we may be doing a sign-extend operation during the
3116 if (mode == HImode || (outer == SIGN_EXTEND && mode == QImode))
3122 range = (mode == HImode) ? 4095 : 4096;
3124 return (code == CONST_INT
3125 && INTVAL (index) < range
3126 && INTVAL (index) > -range);
3129 /* Return nonzero if X is valid as a Thumb state base register. */
3131 thumb_base_register_rtx_p (rtx x, enum machine_mode mode, int strict_p)
3135 if (GET_CODE (x) != REG)
3141 return THUMB_REGNO_MODE_OK_FOR_BASE_P (regno, mode);
3143 return (regno <= LAST_LO_REGNUM
3144 || regno > LAST_VIRTUAL_REGISTER
3145 || regno == FRAME_POINTER_REGNUM
3146 || (GET_MODE_SIZE (mode) >= 4
3147 && (regno == STACK_POINTER_REGNUM
3148 || regno >= FIRST_PSEUDO_REGISTER
3149 || x == hard_frame_pointer_rtx
3150 || x == arg_pointer_rtx)));
3153 /* Return nonzero if x is a legitimate index register. This is the case
3154 for any base register that can access a QImode object. */
3156 thumb_index_register_rtx_p (rtx x, int strict_p)
3158 return thumb_base_register_rtx_p (x, QImode, strict_p);
3161 /* Return nonzero if x is a legitimate Thumb-state address.
3163 The AP may be eliminated to either the SP or the FP, so we use the
3164 least common denominator, e.g. SImode, and offsets from 0 to 64.
3166 ??? Verify whether the above is the right approach.
3168 ??? Also, the FP may be eliminated to the SP, so perhaps that
3169 needs special handling also.
3171 ??? Look at how the mips16 port solves this problem. It probably uses
3172 better ways to solve some of these problems.
3174 Although it is not incorrect, we don't accept QImode and HImode
3175 addresses based on the frame pointer or arg pointer until the
3176 reload pass starts. This is so that eliminating such addresses
3177 into stack based ones won't produce impossible code. */
3179 thumb_legitimate_address_p (enum machine_mode mode, rtx x, int strict_p)
3181 /* ??? Not clear if this is right. Experiment. */
3182 if (GET_MODE_SIZE (mode) < 4
3183 && !(reload_in_progress || reload_completed)
3184 && (reg_mentioned_p (frame_pointer_rtx, x)
3185 || reg_mentioned_p (arg_pointer_rtx, x)
3186 || reg_mentioned_p (virtual_incoming_args_rtx, x)
3187 || reg_mentioned_p (virtual_outgoing_args_rtx, x)
3188 || reg_mentioned_p (virtual_stack_dynamic_rtx, x)
3189 || reg_mentioned_p (virtual_stack_vars_rtx, x)))
3192 /* Accept any base register. SP only in SImode or larger. */
3193 else if (thumb_base_register_rtx_p (x, mode, strict_p))
3196 /* This is PC relative data before arm_reorg runs. */
3197 else if (GET_MODE_SIZE (mode) >= 4 && CONSTANT_P (x)
3198 && GET_CODE (x) == SYMBOL_REF
3199 && CONSTANT_POOL_ADDRESS_P (x) && ! flag_pic)
3202 /* This is PC relative data after arm_reorg runs. */
3203 else if (GET_MODE_SIZE (mode) >= 4 && reload_completed
3204 && (GET_CODE (x) == LABEL_REF
3205 || (GET_CODE (x) == CONST
3206 && GET_CODE (XEXP (x, 0)) == PLUS
3207 && GET_CODE (XEXP (XEXP (x, 0), 0)) == LABEL_REF
3208 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT)))
3211 /* Post-inc indexing only supported for SImode and larger. */
3212 else if (GET_CODE (x) == POST_INC && GET_MODE_SIZE (mode) >= 4
3213 && thumb_index_register_rtx_p (XEXP (x, 0), strict_p))
3216 else if (GET_CODE (x) == PLUS)
3218 /* REG+REG address can be any two index registers. */
3219 /* We disallow FRAME+REG addressing since we know that FRAME
3220 will be replaced with STACK, and SP relative addressing only
3221 permits SP+OFFSET. */
3222 if (GET_MODE_SIZE (mode) <= 4
3223 && XEXP (x, 0) != frame_pointer_rtx
3224 && XEXP (x, 1) != frame_pointer_rtx
3225 && thumb_index_register_rtx_p (XEXP (x, 0), strict_p)
3226 && thumb_index_register_rtx_p (XEXP (x, 1), strict_p))
3229 /* REG+const has 5-7 bit offset for non-SP registers. */
3230 else if ((thumb_index_register_rtx_p (XEXP (x, 0), strict_p)
3231 || XEXP (x, 0) == arg_pointer_rtx)
3232 && GET_CODE (XEXP (x, 1)) == CONST_INT
3233 && thumb_legitimate_offset_p (mode, INTVAL (XEXP (x, 1))))
3236 /* REG+const has 10 bit offset for SP, but only SImode and
3237 larger is supported. */
3238 /* ??? Should probably check for DI/DFmode overflow here
3239 just like GO_IF_LEGITIMATE_OFFSET does. */
3240 else if (GET_CODE (XEXP (x, 0)) == REG
3241 && REGNO (XEXP (x, 0)) == STACK_POINTER_REGNUM
3242 && GET_MODE_SIZE (mode) >= 4
3243 && GET_CODE (XEXP (x, 1)) == CONST_INT
3244 && INTVAL (XEXP (x, 1)) >= 0
3245 && INTVAL (XEXP (x, 1)) + GET_MODE_SIZE (mode) <= 1024
3246 && (INTVAL (XEXP (x, 1)) & 3) == 0)
3249 else if (GET_CODE (XEXP (x, 0)) == REG
3250 && REGNO (XEXP (x, 0)) == FRAME_POINTER_REGNUM
3251 && GET_MODE_SIZE (mode) >= 4
3252 && GET_CODE (XEXP (x, 1)) == CONST_INT
3253 && (INTVAL (XEXP (x, 1)) & 3) == 0)
3257 else if (GET_MODE_CLASS (mode) != MODE_FLOAT
3258 && GET_MODE_SIZE (mode) == 4
3259 && GET_CODE (x) == SYMBOL_REF
3260 && CONSTANT_POOL_ADDRESS_P (x)
3262 && symbol_mentioned_p (get_pool_constant (x))))
3268 /* Return nonzero if VAL can be used as an offset in a Thumb-state address
3269 instruction of mode MODE. */
3271 thumb_legitimate_offset_p (enum machine_mode mode, HOST_WIDE_INT val)
3273 switch (GET_MODE_SIZE (mode))
3276 return val >= 0 && val < 32;
3279 return val >= 0 && val < 64 && (val & 1) == 0;
3283 && (val + GET_MODE_SIZE (mode)) <= 128
3288 /* Try machine-dependent ways of modifying an illegitimate address
3289 to be legitimate. If we find one, return the new, valid address. */
3291 arm_legitimize_address (rtx x, rtx orig_x, enum machine_mode mode)
3293 if (GET_CODE (x) == PLUS)
3295 rtx xop0 = XEXP (x, 0);
3296 rtx xop1 = XEXP (x, 1);
3298 if (CONSTANT_P (xop0) && !symbol_mentioned_p (xop0))
3299 xop0 = force_reg (SImode, xop0);
3301 if (CONSTANT_P (xop1) && !symbol_mentioned_p (xop1))
3302 xop1 = force_reg (SImode, xop1);
3304 if (ARM_BASE_REGISTER_RTX_P (xop0)
3305 && GET_CODE (xop1) == CONST_INT)
3307 HOST_WIDE_INT n, low_n;
3311 /* VFP addressing modes actually allow greater offsets, but for
3312 now we just stick with the lowest common denominator. */
3314 || ((TARGET_SOFT_FLOAT || TARGET_VFP) && mode == DFmode))
3326 low_n = ((mode) == TImode ? 0
3327 : n >= 0 ? (n & 0xfff) : -((-n) & 0xfff));
3331 base_reg = gen_reg_rtx (SImode);
3332 val = force_operand (gen_rtx_PLUS (SImode, xop0,
3333 GEN_INT (n)), NULL_RTX);
3334 emit_move_insn (base_reg, val);
3335 x = (low_n == 0 ? base_reg
3336 : gen_rtx_PLUS (SImode, base_reg, GEN_INT (low_n)));
3338 else if (xop0 != XEXP (x, 0) || xop1 != XEXP (x, 1))
3339 x = gen_rtx_PLUS (SImode, xop0, xop1);
3342 /* XXX We don't allow MINUS any more -- see comment in
3343 arm_legitimate_address_p (). */
3344 else if (GET_CODE (x) == MINUS)
3346 rtx xop0 = XEXP (x, 0);
3347 rtx xop1 = XEXP (x, 1);
3349 if (CONSTANT_P (xop0))
3350 xop0 = force_reg (SImode, xop0);
3352 if (CONSTANT_P (xop1) && ! symbol_mentioned_p (xop1))
3353 xop1 = force_reg (SImode, xop1);
3355 if (xop0 != XEXP (x, 0) || xop1 != XEXP (x, 1))
3356 x = gen_rtx_MINUS (SImode, xop0, xop1);
3361 /* We need to find and carefully transform any SYMBOL and LABEL
3362 references; so go back to the original address expression. */
3363 rtx new_x = legitimize_pic_address (orig_x, mode, NULL_RTX);
3365 if (new_x != orig_x)
3373 /* Try machine-dependent ways of modifying an illegitimate Thumb address
3374 to be legitimate. If we find one, return the new, valid address. */
3376 thumb_legitimize_address (rtx x, rtx orig_x, enum machine_mode mode)
3378 if (GET_CODE (x) == PLUS
3379 && GET_CODE (XEXP (x, 1)) == CONST_INT
3380 && (INTVAL (XEXP (x, 1)) >= 32 * GET_MODE_SIZE (mode)
3381 || INTVAL (XEXP (x, 1)) < 0))
3383 rtx xop0 = XEXP (x, 0);
3384 rtx xop1 = XEXP (x, 1);
3385 HOST_WIDE_INT offset = INTVAL (xop1);
3387 /* Try and fold the offset into a biasing of the base register and
3388 then offsetting that. Don't do this when optimizing for space
3389 since it can cause too many CSEs. */
3390 if (optimize_size && offset >= 0
3391 && offset < 256 + 31 * GET_MODE_SIZE (mode))
3393 HOST_WIDE_INT delta;
3396 delta = offset - (256 - GET_MODE_SIZE (mode));
3397 else if (offset < 32 * GET_MODE_SIZE (mode) + 8)
3398 delta = 31 * GET_MODE_SIZE (mode);
3400 delta = offset & (~31 * GET_MODE_SIZE (mode));
3402 xop0 = force_operand (plus_constant (xop0, offset - delta),
3404 x = plus_constant (xop0, delta);
3406 else if (offset < 0 && offset > -256)
3407 /* Small negative offsets are best done with a subtract before the
3408 dereference, forcing these into a register normally takes two
3410 x = force_operand (x, NULL_RTX);
3413 /* For the remaining cases, force the constant into a register. */
3414 xop1 = force_reg (SImode, xop1);
3415 x = gen_rtx_PLUS (SImode, xop0, xop1);
3418 else if (GET_CODE (x) == PLUS
3419 && s_register_operand (XEXP (x, 1), SImode)
3420 && !s_register_operand (XEXP (x, 0), SImode))
3422 rtx xop0 = force_operand (XEXP (x, 0), NULL_RTX);
3424 x = gen_rtx_PLUS (SImode, xop0, XEXP (x, 1));
3429 /* We need to find and carefully transform any SYMBOL and LABEL
3430 references; so go back to the original address expression. */
3431 rtx new_x = legitimize_pic_address (orig_x, mode, NULL_RTX);
3433 if (new_x != orig_x)
3442 #define REG_OR_SUBREG_REG(X) \
3443 (GET_CODE (X) == REG \
3444 || (GET_CODE (X) == SUBREG && GET_CODE (SUBREG_REG (X)) == REG))
3446 #define REG_OR_SUBREG_RTX(X) \
3447 (GET_CODE (X) == REG ? (X) : SUBREG_REG (X))
3449 #ifndef COSTS_N_INSNS
3450 #define COSTS_N_INSNS(N) ((N) * 4 - 2)
3453 thumb_rtx_costs (rtx x, enum rtx_code code, enum rtx_code outer)
3455 enum machine_mode mode = GET_MODE (x);
3468 return COSTS_N_INSNS (1);
3471 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
3474 unsigned HOST_WIDE_INT i = INTVAL (XEXP (x, 1));
3481 return COSTS_N_INSNS (2) + cycles;
3483 return COSTS_N_INSNS (1) + 16;
3486 return (COSTS_N_INSNS (1)
3487 + 4 * ((GET_CODE (SET_SRC (x)) == MEM)
3488 + GET_CODE (SET_DEST (x)) == MEM));
3493 if ((unsigned HOST_WIDE_INT) INTVAL (x) < 256)
3495 if (thumb_shiftable_const (INTVAL (x)))
3496 return COSTS_N_INSNS (2);
3497 return COSTS_N_INSNS (3);
3499 else if ((outer == PLUS || outer == COMPARE)
3500 && INTVAL (x) < 256 && INTVAL (x) > -256)
3502 else if (outer == AND
3503 && INTVAL (x) < 256 && INTVAL (x) >= -256)
3504 return COSTS_N_INSNS (1);
3505 else if (outer == ASHIFT || outer == ASHIFTRT
3506 || outer == LSHIFTRT)
3508 return COSTS_N_INSNS (2);
3514 return COSTS_N_INSNS (3);
3532 /* XXX another guess. */
3533 /* Memory costs quite a lot for the first word, but subsequent words
3534 load at the equivalent of a single insn each. */
3535 return (10 + 4 * ((GET_MODE_SIZE (mode) - 1) / UNITS_PER_WORD)
3536 + ((GET_CODE (x) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (x))
3541 if (GET_CODE (XEXP (x, 1)) == PC || GET_CODE (XEXP (x, 2)) == PC)
3546 /* XXX still guessing. */
3547 switch (GET_MODE (XEXP (x, 0)))
3550 return (1 + (mode == DImode ? 4 : 0)
3551 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0));
3554 return (4 + (mode == DImode ? 4 : 0)
3555 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0));
3558 return (1 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0));
3570 /* Worker routine for arm_rtx_costs. */
3572 arm_rtx_costs_1 (rtx x, enum rtx_code code, enum rtx_code outer)
3574 enum machine_mode mode = GET_MODE (x);
3575 enum rtx_code subcode;
3581 /* Memory costs quite a lot for the first word, but subsequent words
3582 load at the equivalent of a single insn each. */
3583 return (10 + 4 * ((GET_MODE_SIZE (mode) - 1) / UNITS_PER_WORD)
3584 + (GET_CODE (x) == SYMBOL_REF
3585 && CONSTANT_POOL_ADDRESS_P (x) ? 4 : 0));
3591 return optimize_size ? COSTS_N_INSNS (2) : 100;
3594 if (mode == SImode && GET_CODE (XEXP (x, 1)) == REG)
3601 case ASHIFT: case LSHIFTRT: case ASHIFTRT:
3603 return (8 + (GET_CODE (XEXP (x, 1)) == CONST_INT ? 0 : 8)
3604 + ((GET_CODE (XEXP (x, 0)) == REG
3605 || (GET_CODE (XEXP (x, 0)) == SUBREG
3606 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == REG))
3608 return (1 + ((GET_CODE (XEXP (x, 0)) == REG
3609 || (GET_CODE (XEXP (x, 0)) == SUBREG
3610 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == REG))
3612 + ((GET_CODE (XEXP (x, 1)) == REG
3613 || (GET_CODE (XEXP (x, 1)) == SUBREG
3614 && GET_CODE (SUBREG_REG (XEXP (x, 1))) == REG)
3615 || (GET_CODE (XEXP (x, 1)) == CONST_INT))
3620 return (4 + (REG_OR_SUBREG_REG (XEXP (x, 1)) ? 0 : 8)
3621 + ((REG_OR_SUBREG_REG (XEXP (x, 0))
3622 || (GET_CODE (XEXP (x, 0)) == CONST_INT
3623 && const_ok_for_arm (INTVAL (XEXP (x, 0)))))
3626 if (GET_MODE_CLASS (mode) == MODE_FLOAT)
3627 return (2 + ((REG_OR_SUBREG_REG (XEXP (x, 1))
3628 || (GET_CODE (XEXP (x, 1)) == CONST_DOUBLE
3629 && arm_const_double_rtx (XEXP (x, 1))))
3631 + ((REG_OR_SUBREG_REG (XEXP (x, 0))
3632 || (GET_CODE (XEXP (x, 0)) == CONST_DOUBLE
3633 && arm_const_double_rtx (XEXP (x, 0))))
3636 if (((GET_CODE (XEXP (x, 0)) == CONST_INT
3637 && const_ok_for_arm (INTVAL (XEXP (x, 0)))
3638 && REG_OR_SUBREG_REG (XEXP (x, 1))))
3639 || (((subcode = GET_CODE (XEXP (x, 1))) == ASHIFT
3640 || subcode == ASHIFTRT || subcode == LSHIFTRT
3641 || subcode == ROTATE || subcode == ROTATERT
3643 && GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT
3644 && ((INTVAL (XEXP (XEXP (x, 1), 1)) &
3645 (INTVAL (XEXP (XEXP (x, 1), 1)) - 1)) == 0)))
3646 && REG_OR_SUBREG_REG (XEXP (XEXP (x, 1), 0))
3647 && (REG_OR_SUBREG_REG (XEXP (XEXP (x, 1), 1))
3648 || GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT)
3649 && REG_OR_SUBREG_REG (XEXP (x, 0))))
3654 if (GET_MODE_CLASS (mode) == MODE_FLOAT)
3655 return (2 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 8)
3656 + ((REG_OR_SUBREG_REG (XEXP (x, 1))
3657 || (GET_CODE (XEXP (x, 1)) == CONST_DOUBLE
3658 && arm_const_double_rtx (XEXP (x, 1))))
3662 case AND: case XOR: case IOR:
3665 /* Normally the frame registers will be spilt into reg+const during
3666 reload, so it is a bad idea to combine them with other instructions,
3667 since then they might not be moved outside of loops. As a compromise
3668 we allow integration with ops that have a constant as their second
3670 if ((REG_OR_SUBREG_REG (XEXP (x, 0))
3671 && ARM_FRAME_RTX (REG_OR_SUBREG_RTX (XEXP (x, 0)))
3672 && GET_CODE (XEXP (x, 1)) != CONST_INT)
3673 || (REG_OR_SUBREG_REG (XEXP (x, 0))
3674 && ARM_FRAME_RTX (REG_OR_SUBREG_RTX (XEXP (x, 0)))))
3678 return (4 + extra_cost + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 8)
3679 + ((REG_OR_SUBREG_REG (XEXP (x, 1))
3680 || (GET_CODE (XEXP (x, 1)) == CONST_INT
3681 && const_ok_for_op (INTVAL (XEXP (x, 1)), code)))
3684 if (REG_OR_SUBREG_REG (XEXP (x, 0)))
3685 return (1 + (GET_CODE (XEXP (x, 1)) == CONST_INT ? 0 : extra_cost)
3686 + ((REG_OR_SUBREG_REG (XEXP (x, 1))
3687 || (GET_CODE (XEXP (x, 1)) == CONST_INT
3688 && const_ok_for_op (INTVAL (XEXP (x, 1)), code)))
3691 else if (REG_OR_SUBREG_REG (XEXP (x, 1)))
3692 return (1 + extra_cost
3693 + ((((subcode = GET_CODE (XEXP (x, 0))) == ASHIFT
3694 || subcode == LSHIFTRT || subcode == ASHIFTRT
3695 || subcode == ROTATE || subcode == ROTATERT
3697 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3698 && ((INTVAL (XEXP (XEXP (x, 0), 1)) &
3699 (INTVAL (XEXP (XEXP (x, 0), 1)) - 1)) == 0)))
3700 && (REG_OR_SUBREG_REG (XEXP (XEXP (x, 0), 0)))
3701 && ((REG_OR_SUBREG_REG (XEXP (XEXP (x, 0), 1)))
3702 || GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT))
3708 /* This should have been handled by the CPU specific routines. */
3712 if (arm_arch3m && mode == SImode
3713 && GET_CODE (XEXP (x, 0)) == LSHIFTRT
3714 && GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT
3715 && (GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 0))
3716 == GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)))
3717 && (GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == ZERO_EXTEND
3718 || GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == SIGN_EXTEND))
3723 if (GET_MODE_CLASS (mode) == MODE_FLOAT)
3724 return 4 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 6);
3728 return 4 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 4);
3730 return 1 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 4);
3733 if (GET_CODE (XEXP (x, 1)) == PC || GET_CODE (XEXP (x, 2)) == PC)
3741 return 4 + (mode == DImode ? 4 : 0);
3744 if (GET_MODE (XEXP (x, 0)) == QImode)
3745 return (4 + (mode == DImode ? 4 : 0)
3746 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0));
3749 switch (GET_MODE (XEXP (x, 0)))
3752 return (1 + (mode == DImode ? 4 : 0)
3753 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0));
3756 return (4 + (mode == DImode ? 4 : 0)
3757 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0));
3760 return (1 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0));
3775 if (const_ok_for_arm (INTVAL (x)))
3776 return outer == SET ? 2 : -1;
3777 else if (outer == AND
3778 && const_ok_for_arm (~INTVAL (x)))
3780 else if ((outer == COMPARE
3781 || outer == PLUS || outer == MINUS)
3782 && const_ok_for_arm (-INTVAL (x)))
3793 if (arm_const_double_rtx (x))
3794 return outer == SET ? 2 : -1;
3795 else if ((outer == COMPARE || outer == PLUS)
3796 && neg_const_double_rtx_ok_for_fpa (x))
3805 /* RTX costs for cores with a slow MUL implementation. */
3808 arm_slowmul_rtx_costs (rtx x, int code, int outer_code, int *total)
3810 enum machine_mode mode = GET_MODE (x);
3814 *total = thumb_rtx_costs (x, code, outer_code);
3821 if (GET_MODE_CLASS (mode) == MODE_FLOAT
3828 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
3830 unsigned HOST_WIDE_INT i = (INTVAL (XEXP (x, 1))
3831 & (unsigned HOST_WIDE_INT) 0xffffffff);
3832 int cost, const_ok = const_ok_for_arm (i);
3833 int j, booth_unit_size;
3835 /* Tune as appropriate. */
3836 cost = const_ok ? 4 : 8;
3837 booth_unit_size = 2;
3838 for (j = 0; i && j < 32; j += booth_unit_size)
3840 i >>= booth_unit_size;
3848 *total = 30 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 4)
3849 + (REG_OR_SUBREG_REG (XEXP (x, 1)) ? 0 : 4);
3853 *total = arm_rtx_costs_1 (x, code, outer_code);
3859 /* RTX cost for cores with a fast multiply unit (M variants). */
3862 arm_fastmul_rtx_costs (rtx x, int code, int outer_code, int *total)
3864 enum machine_mode mode = GET_MODE (x);
3868 *total = thumb_rtx_costs (x, code, outer_code);
3875 /* There is no point basing this on the tuning, since it is always the
3876 fast variant if it exists at all. */
3878 && (GET_CODE (XEXP (x, 0)) == GET_CODE (XEXP (x, 1)))
3879 && (GET_CODE (XEXP (x, 0)) == ZERO_EXTEND
3880 || GET_CODE (XEXP (x, 0)) == SIGN_EXTEND))
3887 if (GET_MODE_CLASS (mode) == MODE_FLOAT
3894 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
3896 unsigned HOST_WIDE_INT i = (INTVAL (XEXP (x, 1))
3897 & (unsigned HOST_WIDE_INT) 0xffffffff);
3898 int cost, const_ok = const_ok_for_arm (i);
3899 int j, booth_unit_size;
3901 /* Tune as appropriate. */
3902 cost = const_ok ? 4 : 8;
3903 booth_unit_size = 8;
3904 for (j = 0; i && j < 32; j += booth_unit_size)
3906 i >>= booth_unit_size;
3914 *total = 8 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 4)
3915 + (REG_OR_SUBREG_REG (XEXP (x, 1)) ? 0 : 4);
3919 *total = arm_rtx_costs_1 (x, code, outer_code);
3925 /* RTX cost for XScale CPUs. */
3928 arm_xscale_rtx_costs (rtx x, int code, int outer_code, int *total)
3930 enum machine_mode mode = GET_MODE (x);
3934 *total = thumb_rtx_costs (x, code, outer_code);
3941 /* There is no point basing this on the tuning, since it is always the
3942 fast variant if it exists at all. */
3944 && (GET_CODE (XEXP (x, 0)) == GET_CODE (XEXP (x, 1)))
3945 && (GET_CODE (XEXP (x, 0)) == ZERO_EXTEND
3946 || GET_CODE (XEXP (x, 0)) == SIGN_EXTEND))
3953 if (GET_MODE_CLASS (mode) == MODE_FLOAT
3960 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
3962 unsigned HOST_WIDE_INT i = (INTVAL (XEXP (x, 1))
3963 & (unsigned HOST_WIDE_INT) 0xffffffff);
3964 int cost, const_ok = const_ok_for_arm (i);
3965 unsigned HOST_WIDE_INT masked_const;
3967 /* The cost will be related to two insns.
3968 First a load of the constant (MOV or LDR), then a multiply. */
3971 cost += 1; /* LDR is probably more expensive because
3972 of longer result latency. */
3973 masked_const = i & 0xffff8000;
3974 if (masked_const != 0 && masked_const != 0xffff8000)
3976 masked_const = i & 0xf8000000;
3977 if (masked_const == 0 || masked_const == 0xf8000000)
3986 *total = 8 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 4)
3987 + (REG_OR_SUBREG_REG (XEXP (x, 1)) ? 0 : 4);
3991 *total = arm_rtx_costs_1 (x, code, outer_code);
3997 /* RTX costs for 9e (and later) cores. */
4000 arm_9e_rtx_costs (rtx x, int code, int outer_code, int *total)
4002 enum machine_mode mode = GET_MODE (x);
4011 *total = COSTS_N_INSNS (3);
4015 *total = thumb_rtx_costs (x, code, outer_code);
4023 /* There is no point basing this on the tuning, since it is always the
4024 fast variant if it exists at all. */
4026 && (GET_CODE (XEXP (x, 0)) == GET_CODE (XEXP (x, 1)))
4027 && (GET_CODE (XEXP (x, 0)) == ZERO_EXTEND
4028 || GET_CODE (XEXP (x, 0)) == SIGN_EXTEND))
4035 if (GET_MODE_CLASS (mode) == MODE_FLOAT)
4052 *total = cost + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : nonreg_cost)
4053 + (REG_OR_SUBREG_REG (XEXP (x, 1)) ? 0 : nonreg_cost);
4057 *total = arm_rtx_costs_1 (x, code, outer_code);
4061 /* All address computations that can be done are free, but rtx cost returns
4062 the same for practically all of them. So we weight the different types
4063 of address here in the order (most pref first):
4064 PRE/POST_INC/DEC, SHIFT or NON-INT sum, INT sum, REG, MEM or LABEL. */
4066 arm_arm_address_cost (rtx x)
4068 enum rtx_code c = GET_CODE (x);
4070 if (c == PRE_INC || c == PRE_DEC || c == POST_INC || c == POST_DEC)
4072 if (c == MEM || c == LABEL_REF || c == SYMBOL_REF)
4075 if (c == PLUS || c == MINUS)
4077 if (GET_CODE (XEXP (x, 0)) == CONST_INT)
4080 if (ARITHMETIC_P (XEXP (x, 0)) || ARITHMETIC_P (XEXP (x, 1)))
4090 arm_thumb_address_cost (rtx x)
4092 enum rtx_code c = GET_CODE (x);
4097 && GET_CODE (XEXP (x, 0)) == REG
4098 && GET_CODE (XEXP (x, 1)) == CONST_INT)
4105 arm_address_cost (rtx x)
4107 return TARGET_ARM ? arm_arm_address_cost (x) : arm_thumb_address_cost (x);
4111 arm_adjust_cost (rtx insn, rtx link, rtx dep, int cost)
4115 /* Some true dependencies can have a higher cost depending
4116 on precisely how certain input operands are used. */
4118 && REG_NOTE_KIND (link) == 0
4119 && recog_memoized (insn) >= 0
4120 && recog_memoized (dep) >= 0)
4122 int shift_opnum = get_attr_shift (insn);
4123 enum attr_type attr_type = get_attr_type (dep);
4125 /* If nonzero, SHIFT_OPNUM contains the operand number of a shifted
4126 operand for INSN. If we have a shifted input operand and the
4127 instruction we depend on is another ALU instruction, then we may
4128 have to account for an additional stall. */
4129 if (shift_opnum != 0
4130 && (attr_type == TYPE_ALU_SHIFT || attr_type == TYPE_ALU_SHIFT_REG))
4132 rtx shifted_operand;
4135 /* Get the shifted operand. */
4136 extract_insn (insn);
4137 shifted_operand = recog_data.operand[shift_opnum];
4139 /* Iterate over all the operands in DEP. If we write an operand
4140 that overlaps with SHIFTED_OPERAND, then we have increase the
4141 cost of this dependency. */
4143 preprocess_constraints ();
4144 for (opno = 0; opno < recog_data.n_operands; opno++)
4146 /* We can ignore strict inputs. */
4147 if (recog_data.operand_type[opno] == OP_IN)
4150 if (reg_overlap_mentioned_p (recog_data.operand[opno],
4157 /* XXX This is not strictly true for the FPA. */
4158 if (REG_NOTE_KIND (link) == REG_DEP_ANTI
4159 || REG_NOTE_KIND (link) == REG_DEP_OUTPUT)
4162 /* Call insns don't incur a stall, even if they follow a load. */
4163 if (REG_NOTE_KIND (link) == 0
4164 && GET_CODE (insn) == CALL_INSN)
4167 if ((i_pat = single_set (insn)) != NULL
4168 && GET_CODE (SET_SRC (i_pat)) == MEM
4169 && (d_pat = single_set (dep)) != NULL
4170 && GET_CODE (SET_DEST (d_pat)) == MEM)
4172 rtx src_mem = XEXP (SET_SRC (i_pat), 0);
4173 /* This is a load after a store, there is no conflict if the load reads
4174 from a cached area. Assume that loads from the stack, and from the
4175 constant pool are cached, and that others will miss. This is a
4178 if ((GET_CODE (src_mem) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (src_mem))
4179 || reg_mentioned_p (stack_pointer_rtx, src_mem)
4180 || reg_mentioned_p (frame_pointer_rtx, src_mem)
4181 || reg_mentioned_p (hard_frame_pointer_rtx, src_mem))
4188 static int fp_consts_inited = 0;
4190 /* Only zero is valid for VFP. Other values are also valid for FPA. */
4191 static const char * const strings_fp[8] =
4194 "4", "5", "0.5", "10"
4197 static REAL_VALUE_TYPE values_fp[8];
4200 init_fp_table (void)
4206 fp_consts_inited = 1;
4208 fp_consts_inited = 8;
4210 for (i = 0; i < fp_consts_inited; i++)
4212 r = REAL_VALUE_ATOF (strings_fp[i], DFmode);
4217 /* Return TRUE if rtx X is a valid immediate FP constant. */
4219 arm_const_double_rtx (rtx x)
4224 if (!fp_consts_inited)
4227 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
4228 if (REAL_VALUE_MINUS_ZERO (r))
4231 for (i = 0; i < fp_consts_inited; i++)
4232 if (REAL_VALUES_EQUAL (r, values_fp[i]))
4238 /* Return TRUE if rtx X is a valid immediate FPA constant. */
4240 neg_const_double_rtx_ok_for_fpa (rtx x)
4245 if (!fp_consts_inited)
4248 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
4249 r = REAL_VALUE_NEGATE (r);
4250 if (REAL_VALUE_MINUS_ZERO (r))
4253 for (i = 0; i < 8; i++)
4254 if (REAL_VALUES_EQUAL (r, values_fp[i]))
4260 /* Predicates for `match_operand' and `match_operator'. */
4262 /* s_register_operand is the same as register_operand, but it doesn't accept
4265 This function exists because at the time it was put in it led to better
4266 code. SUBREG(MEM) always needs a reload in the places where
4267 s_register_operand is used, and this seemed to lead to excessive
4270 s_register_operand (rtx op, enum machine_mode mode)
4272 if (GET_MODE (op) != mode && mode != VOIDmode)
4275 if (GET_CODE (op) == SUBREG)
4276 op = SUBREG_REG (op);
4278 /* We don't consider registers whose class is NO_REGS
4279 to be a register operand. */
4280 /* XXX might have to check for lo regs only for thumb ??? */
4281 return (GET_CODE (op) == REG
4282 && (REGNO (op) >= FIRST_PSEUDO_REGISTER
4283 || REGNO_REG_CLASS (REGNO (op)) != NO_REGS));
4286 /* A hard register operand (even before reload. */
4288 arm_hard_register_operand (rtx op, enum machine_mode mode)
4290 if (GET_MODE (op) != mode && mode != VOIDmode)
4293 return (GET_CODE (op) == REG
4294 && REGNO (op) < FIRST_PSEUDO_REGISTER);
4297 /* An arm register operand. */
4299 arm_general_register_operand (rtx op, enum machine_mode mode)
4301 if (GET_MODE (op) != mode && mode != VOIDmode)
4304 if (GET_CODE (op) == SUBREG)
4305 op = SUBREG_REG (op);
4307 return (GET_CODE (op) == REG
4308 && (REGNO (op) <= LAST_ARM_REGNUM
4309 || REGNO (op) >= FIRST_PSEUDO_REGISTER));
4312 /* Only accept reg, subreg(reg), const_int. */
4314 reg_or_int_operand (rtx op, enum machine_mode mode)
4316 if (GET_CODE (op) == CONST_INT)
4319 if (GET_MODE (op) != mode && mode != VOIDmode)
4322 if (GET_CODE (op) == SUBREG)
4323 op = SUBREG_REG (op);
4325 /* We don't consider registers whose class is NO_REGS
4326 to be a register operand. */
4327 return (GET_CODE (op) == REG
4328 && (REGNO (op) >= FIRST_PSEUDO_REGISTER
4329 || REGNO_REG_CLASS (REGNO (op)) != NO_REGS));
4332 /* Return 1 if OP is an item in memory, given that we are in reload. */
4334 arm_reload_memory_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
4336 int regno = true_regnum (op);
4338 return (!CONSTANT_P (op)
4340 || (GET_CODE (op) == REG
4341 && REGNO (op) >= FIRST_PSEUDO_REGISTER)));
4344 /* Return TRUE for valid operands for the rhs of an ARM instruction. */
4346 arm_rhs_operand (rtx op, enum machine_mode mode)
4348 return (s_register_operand (op, mode)
4349 || (GET_CODE (op) == CONST_INT && const_ok_for_arm (INTVAL (op))));
4352 /* Return TRUE for valid operands for the
4353 rhs of an ARM instruction, or a load. */
4355 arm_rhsm_operand (rtx op, enum machine_mode mode)
4357 return (s_register_operand (op, mode)
4358 || (GET_CODE (op) == CONST_INT && const_ok_for_arm (INTVAL (op)))
4359 || memory_operand (op, mode));
4362 /* Return TRUE for valid operands for the rhs of an ARM instruction, or if a
4363 constant that is valid when negated. */
4365 arm_add_operand (rtx op, enum machine_mode mode)
4368 return thumb_cmp_operand (op, mode);
4370 return (s_register_operand (op, mode)
4371 || (GET_CODE (op) == CONST_INT
4372 && (const_ok_for_arm (INTVAL (op))
4373 || const_ok_for_arm (-INTVAL (op)))));
4376 /* Return TRUE for valid ARM constants (or when valid if negated). */
4378 arm_addimm_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
4380 return (GET_CODE (op) == CONST_INT
4381 && (const_ok_for_arm (INTVAL (op))
4382 || const_ok_for_arm (-INTVAL (op))));
4386 arm_not_operand (rtx op, enum machine_mode mode)
4388 return (s_register_operand (op, mode)
4389 || (GET_CODE (op) == CONST_INT
4390 && (const_ok_for_arm (INTVAL (op))
4391 || const_ok_for_arm (~INTVAL (op)))));
4394 /* Return TRUE if the operand is a memory reference which contains an
4395 offsettable address. */
4397 offsettable_memory_operand (rtx op, enum machine_mode mode)
4399 if (mode == VOIDmode)
4400 mode = GET_MODE (op);
4402 return (mode == GET_MODE (op)
4403 && GET_CODE (op) == MEM
4404 && offsettable_address_p (reload_completed | reload_in_progress,
4405 mode, XEXP (op, 0)));
4408 /* Return TRUE if the operand is a memory reference which is, or can be
4409 made word aligned by adjusting the offset. */
4411 alignable_memory_operand (rtx op, enum machine_mode mode)
4415 if (mode == VOIDmode)
4416 mode = GET_MODE (op);
4418 if (mode != GET_MODE (op) || GET_CODE (op) != MEM)
4423 return ((GET_CODE (reg = op) == REG
4424 || (GET_CODE (op) == SUBREG
4425 && GET_CODE (reg = SUBREG_REG (op)) == REG)
4426 || (GET_CODE (op) == PLUS
4427 && GET_CODE (XEXP (op, 1)) == CONST_INT
4428 && (GET_CODE (reg = XEXP (op, 0)) == REG
4429 || (GET_CODE (XEXP (op, 0)) == SUBREG
4430 && GET_CODE (reg = SUBREG_REG (XEXP (op, 0))) == REG))))
4431 && REGNO_POINTER_ALIGN (REGNO (reg)) >= 32);
4434 /* Similar to s_register_operand, but does not allow hard integer
4437 f_register_operand (rtx op, enum machine_mode mode)
4439 if (GET_MODE (op) != mode && mode != VOIDmode)
4442 if (GET_CODE (op) == SUBREG)
4443 op = SUBREG_REG (op);
4445 /* We don't consider registers whose class is NO_REGS
4446 to be a register operand. */
4447 return (GET_CODE (op) == REG
4448 && (REGNO (op) >= FIRST_PSEUDO_REGISTER
4449 || REGNO_REG_CLASS (REGNO (op)) == FPA_REGS));
4452 /* Return TRUE for valid operands for the rhs of an floating point insns.
4453 Allows regs or certain consts on FPA, just regs for everything else. */
4455 arm_float_rhs_operand (rtx op, enum machine_mode mode)
4457 if (s_register_operand (op, mode))
4460 if (GET_MODE (op) != mode && mode != VOIDmode)
4463 if (TARGET_FPA && GET_CODE (op) == CONST_DOUBLE)
4464 return arm_const_double_rtx (op);
4470 arm_float_add_operand (rtx op, enum machine_mode mode)
4472 if (s_register_operand (op, mode))
4475 if (GET_MODE (op) != mode && mode != VOIDmode)
4478 if (TARGET_FPA && GET_CODE (op) == CONST_DOUBLE)
4479 return (arm_const_double_rtx (op)
4480 || neg_const_double_rtx_ok_for_fpa (op));
4486 /* Return TRUE if OP is suitable for the rhs of a floating point comparison.
4487 Depends which fpu we are targeting. */
4490 arm_float_compare_operand (rtx op, enum machine_mode mode)
4493 return vfp_compare_operand (op, mode);
4495 return arm_float_rhs_operand (op, mode);
4499 /* Return nonzero if OP is a valid Cirrus memory address pattern. */
4501 cirrus_memory_offset (rtx op)
4503 /* Reject eliminable registers. */
4504 if (! (reload_in_progress || reload_completed)
4505 && ( reg_mentioned_p (frame_pointer_rtx, op)
4506 || reg_mentioned_p (arg_pointer_rtx, op)
4507 || reg_mentioned_p (virtual_incoming_args_rtx, op)
4508 || reg_mentioned_p (virtual_outgoing_args_rtx, op)
4509 || reg_mentioned_p (virtual_stack_dynamic_rtx, op)
4510 || reg_mentioned_p (virtual_stack_vars_rtx, op)))
4513 if (GET_CODE (op) == MEM)
4519 /* Match: (mem (reg)). */
4520 if (GET_CODE (ind) == REG)
4526 if (GET_CODE (ind) == PLUS
4527 && GET_CODE (XEXP (ind, 0)) == REG
4528 && REG_MODE_OK_FOR_BASE_P (XEXP (ind, 0), VOIDmode)
4529 && GET_CODE (XEXP (ind, 1)) == CONST_INT)
4537 arm_extendqisi_mem_op (rtx op, enum machine_mode mode)
4539 if (!memory_operand (op, mode))
4542 return arm_legitimate_address_p (mode, XEXP (op, 0), SIGN_EXTEND, 0);
4545 /* Return nonzero if OP is a Cirrus or general register. */
4547 cirrus_register_operand (rtx op, enum machine_mode mode)
4549 if (GET_MODE (op) != mode && mode != VOIDmode)
4552 if (GET_CODE (op) == SUBREG)
4553 op = SUBREG_REG (op);
4555 return (GET_CODE (op) == REG
4556 && (REGNO_REG_CLASS (REGNO (op)) == CIRRUS_REGS
4557 || REGNO_REG_CLASS (REGNO (op)) == GENERAL_REGS));
4560 /* Return nonzero if OP is a cirrus FP register. */
4562 cirrus_fp_register (rtx op, enum machine_mode mode)
4564 if (GET_MODE (op) != mode && mode != VOIDmode)
4567 if (GET_CODE (op) == SUBREG)
4568 op = SUBREG_REG (op);
4570 return (GET_CODE (op) == REG
4571 && (REGNO (op) >= FIRST_PSEUDO_REGISTER
4572 || REGNO_REG_CLASS (REGNO (op)) == CIRRUS_REGS));
4575 /* Return nonzero if OP is a 6bit constant (0..63). */
4577 cirrus_shift_const (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
4579 return (GET_CODE (op) == CONST_INT
4581 && INTVAL (op) < 64);
4585 /* Return TRUE if OP is a valid VFP memory address pattern.
4586 WB if true if writeback address modes are allowed. */
4589 arm_coproc_mem_operand (rtx op, bool wb)
4593 /* Reject eliminable registers. */
4594 if (! (reload_in_progress || reload_completed)
4595 && ( reg_mentioned_p (frame_pointer_rtx, op)
4596 || reg_mentioned_p (arg_pointer_rtx, op)
4597 || reg_mentioned_p (virtual_incoming_args_rtx, op)
4598 || reg_mentioned_p (virtual_outgoing_args_rtx, op)
4599 || reg_mentioned_p (virtual_stack_dynamic_rtx, op)
4600 || reg_mentioned_p (virtual_stack_vars_rtx, op)))
4603 /* Constants are converted into offsets from labels. */
4604 if (GET_CODE (op) != MEM)
4609 if (reload_completed
4610 && (GET_CODE (ind) == LABEL_REF
4611 || (GET_CODE (ind) == CONST
4612 && GET_CODE (XEXP (ind, 0)) == PLUS
4613 && GET_CODE (XEXP (XEXP (ind, 0), 0)) == LABEL_REF
4614 && GET_CODE (XEXP (XEXP (ind, 0), 1)) == CONST_INT)))
4617 /* Match: (mem (reg)). */
4618 if (GET_CODE (ind) == REG)
4619 return arm_address_register_rtx_p (ind, 0);
4621 /* Autoincremment addressing modes. */
4623 && (GET_CODE (ind) == PRE_INC
4624 || GET_CODE (ind) == POST_INC
4625 || GET_CODE (ind) == PRE_DEC
4626 || GET_CODE (ind) == POST_DEC))
4627 return arm_address_register_rtx_p (XEXP (ind, 0), 0);
4630 && (GET_CODE (ind) == POST_MODIFY || GET_CODE (ind) == PRE_MODIFY)
4631 && arm_address_register_rtx_p (XEXP (ind, 0), 0)
4632 && GET_CODE (XEXP (ind, 1)) == PLUS
4633 && rtx_equal_p (XEXP (XEXP (ind, 1), 0), XEXP (ind, 0)))
4634 ind = XEXP (ind, 1);
4639 if (GET_CODE (ind) == PLUS
4640 && GET_CODE (XEXP (ind, 0)) == REG
4641 && REG_MODE_OK_FOR_BASE_P (XEXP (ind, 0), VOIDmode)
4642 && GET_CODE (XEXP (ind, 1)) == CONST_INT
4643 && INTVAL (XEXP (ind, 1)) > -1024
4644 && INTVAL (XEXP (ind, 1)) < 1024
4645 && (INTVAL (XEXP (ind, 1)) & 3) == 0)
4652 /* Return TRUE if OP is a REG or constant zero. */
4654 vfp_compare_operand (rtx op, enum machine_mode mode)
4656 if (s_register_operand (op, mode))
4659 return (GET_CODE (op) == CONST_DOUBLE
4660 && arm_const_double_rtx (op));
4664 /* Return GENERAL_REGS if a scratch register required to reload x to/from
4665 VFP registers. Otherwise return NO_REGS. */
4668 vfp_secondary_reload_class (enum machine_mode mode, rtx x)
4670 if (arm_coproc_mem_operand (x, FALSE) || s_register_operand (x, mode))
4673 return GENERAL_REGS;
4677 /* Returns TRUE if INSN is an "LDR REG, ADDR" instruction.
4678 Use by the Cirrus Maverick code which has to workaround
4679 a hardware bug triggered by such instructions. */
4681 arm_memory_load_p (rtx insn)
4683 rtx body, lhs, rhs;;
4685 if (insn == NULL_RTX || GET_CODE (insn) != INSN)
4688 body = PATTERN (insn);
4690 if (GET_CODE (body) != SET)
4693 lhs = XEXP (body, 0);
4694 rhs = XEXP (body, 1);
4696 lhs = REG_OR_SUBREG_RTX (lhs);
4698 /* If the destination is not a general purpose
4699 register we do not have to worry. */
4700 if (GET_CODE (lhs) != REG
4701 || REGNO_REG_CLASS (REGNO (lhs)) != GENERAL_REGS)
4704 /* As well as loads from memory we also have to react
4705 to loads of invalid constants which will be turned
4706 into loads from the minipool. */
4707 return (GET_CODE (rhs) == MEM
4708 || GET_CODE (rhs) == SYMBOL_REF
4709 || note_invalid_constants (insn, -1, false));
4712 /* Return TRUE if INSN is a Cirrus instruction. */
4714 arm_cirrus_insn_p (rtx insn)
4716 enum attr_cirrus attr;
4718 /* get_attr aborts on USE and CLOBBER. */
4720 || GET_CODE (insn) != INSN
4721 || GET_CODE (PATTERN (insn)) == USE
4722 || GET_CODE (PATTERN (insn)) == CLOBBER)
4725 attr = get_attr_cirrus (insn);
4727 return attr != CIRRUS_NOT;
4730 /* Cirrus reorg for invalid instruction combinations. */
4732 cirrus_reorg (rtx first)
4734 enum attr_cirrus attr;
4735 rtx body = PATTERN (first);
4739 /* Any branch must be followed by 2 non Cirrus instructions. */
4740 if (GET_CODE (first) == JUMP_INSN && GET_CODE (body) != RETURN)
4743 t = next_nonnote_insn (first);
4745 if (arm_cirrus_insn_p (t))
4748 if (arm_cirrus_insn_p (next_nonnote_insn (t)))
4752 emit_insn_after (gen_nop (), first);
4757 /* (float (blah)) is in parallel with a clobber. */
4758 if (GET_CODE (body) == PARALLEL && XVECLEN (body, 0) > 0)
4759 body = XVECEXP (body, 0, 0);
4761 if (GET_CODE (body) == SET)
4763 rtx lhs = XEXP (body, 0), rhs = XEXP (body, 1);
4765 /* cfldrd, cfldr64, cfstrd, cfstr64 must
4766 be followed by a non Cirrus insn. */
4767 if (get_attr_cirrus (first) == CIRRUS_DOUBLE)
4769 if (arm_cirrus_insn_p (next_nonnote_insn (first)))
4770 emit_insn_after (gen_nop (), first);
4774 else if (arm_memory_load_p (first))
4776 unsigned int arm_regno;
4778 /* Any ldr/cfmvdlr, ldr/cfmvdhr, ldr/cfmvsr, ldr/cfmv64lr,
4779 ldr/cfmv64hr combination where the Rd field is the same
4780 in both instructions must be split with a non Cirrus
4787 /* Get Arm register number for ldr insn. */
4788 if (GET_CODE (lhs) == REG)
4789 arm_regno = REGNO (lhs);
4790 else if (GET_CODE (rhs) == REG)
4791 arm_regno = REGNO (rhs);
4796 first = next_nonnote_insn (first);
4798 if (! arm_cirrus_insn_p (first))
4801 body = PATTERN (first);
4803 /* (float (blah)) is in parallel with a clobber. */
4804 if (GET_CODE (body) == PARALLEL && XVECLEN (body, 0))
4805 body = XVECEXP (body, 0, 0);
4807 if (GET_CODE (body) == FLOAT)
4808 body = XEXP (body, 0);
4810 if (get_attr_cirrus (first) == CIRRUS_MOVE
4811 && GET_CODE (XEXP (body, 1)) == REG
4812 && arm_regno == REGNO (XEXP (body, 1)))
4813 emit_insn_after (gen_nop (), first);
4819 /* get_attr aborts on USE and CLOBBER. */
4821 || GET_CODE (first) != INSN
4822 || GET_CODE (PATTERN (first)) == USE
4823 || GET_CODE (PATTERN (first)) == CLOBBER)
4826 attr = get_attr_cirrus (first);
4828 /* Any coprocessor compare instruction (cfcmps, cfcmpd, ...)
4829 must be followed by a non-coprocessor instruction. */
4830 if (attr == CIRRUS_COMPARE)
4834 t = next_nonnote_insn (first);
4836 if (arm_cirrus_insn_p (t))
4839 if (arm_cirrus_insn_p (next_nonnote_insn (t)))
4843 emit_insn_after (gen_nop (), first);
4849 /* Return nonzero if OP is a constant power of two. */
4851 power_of_two_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
4853 if (GET_CODE (op) == CONST_INT)
4855 HOST_WIDE_INT value = INTVAL (op);
4857 return value != 0 && (value & (value - 1)) == 0;
4863 /* Return TRUE for a valid operand of a DImode operation.
4864 Either: REG, SUBREG, CONST_DOUBLE or MEM(DImode_address).
4865 Note that this disallows MEM(REG+REG), but allows
4866 MEM(PRE/POST_INC/DEC(REG)). */
4868 di_operand (rtx op, enum machine_mode mode)
4870 if (s_register_operand (op, mode))
4873 if (mode != VOIDmode && GET_MODE (op) != VOIDmode && GET_MODE (op) != DImode)
4876 if (GET_CODE (op) == SUBREG)
4877 op = SUBREG_REG (op);
4879 switch (GET_CODE (op))
4886 return memory_address_p (DImode, XEXP (op, 0));
4893 /* Like di_operand, but don't accept constants. */
4895 nonimmediate_di_operand (rtx op, enum machine_mode mode)
4897 if (s_register_operand (op, mode))
4900 if (mode != VOIDmode && GET_MODE (op) != VOIDmode && GET_MODE (op) != DImode)
4903 if (GET_CODE (op) == SUBREG)
4904 op = SUBREG_REG (op);
4906 if (GET_CODE (op) == MEM)
4907 return memory_address_p (DImode, XEXP (op, 0));
4912 /* Return TRUE for a valid operand of a DFmode operation when soft-float.
4913 Either: REG, SUBREG, CONST_DOUBLE or MEM(DImode_address).
4914 Note that this disallows MEM(REG+REG), but allows
4915 MEM(PRE/POST_INC/DEC(REG)). */
4917 soft_df_operand (rtx op, enum machine_mode mode)
4919 if (s_register_operand (op, mode))
4922 if (mode != VOIDmode && GET_MODE (op) != mode)
4925 if (GET_CODE (op) == SUBREG && CONSTANT_P (SUBREG_REG (op)))
4928 if (GET_CODE (op) == SUBREG)
4929 op = SUBREG_REG (op);
4931 switch (GET_CODE (op))
4937 return memory_address_p (DFmode, XEXP (op, 0));
4944 /* Like soft_df_operand, but don't accept constants. */
4946 nonimmediate_soft_df_operand (rtx op, enum machine_mode mode)
4948 if (s_register_operand (op, mode))
4951 if (mode != VOIDmode && GET_MODE (op) != mode)
4954 if (GET_CODE (op) == SUBREG)
4955 op = SUBREG_REG (op);
4957 if (GET_CODE (op) == MEM)
4958 return memory_address_p (DFmode, XEXP (op, 0));
4962 /* Return TRUE for valid index operands. */
4964 index_operand (rtx op, enum machine_mode mode)
4966 return (s_register_operand (op, mode)
4967 || (immediate_operand (op, mode)
4968 && (GET_CODE (op) != CONST_INT
4969 || (INTVAL (op) < 4096 && INTVAL (op) > -4096))));
4972 /* Return TRUE for valid shifts by a constant. This also accepts any
4973 power of two on the (somewhat overly relaxed) assumption that the
4974 shift operator in this case was a mult. */
4976 const_shift_operand (rtx op, enum machine_mode mode)
4978 return (power_of_two_operand (op, mode)
4979 || (immediate_operand (op, mode)
4980 && (GET_CODE (op) != CONST_INT
4981 || (INTVAL (op) < 32 && INTVAL (op) > 0))));
4984 /* Return TRUE for arithmetic operators which can be combined with a multiply
4987 shiftable_operator (rtx x, enum machine_mode mode)
4991 if (GET_MODE (x) != mode)
4994 code = GET_CODE (x);
4996 return (code == PLUS || code == MINUS
4997 || code == IOR || code == XOR || code == AND);
5000 /* Return TRUE for binary logical operators. */
5002 logical_binary_operator (rtx x, enum machine_mode mode)
5006 if (GET_MODE (x) != mode)
5009 code = GET_CODE (x);
5011 return (code == IOR || code == XOR || code == AND);
5014 /* Return TRUE for shift operators. */
5016 shift_operator (rtx x,enum machine_mode mode)
5020 if (GET_MODE (x) != mode)
5023 code = GET_CODE (x);
5026 return power_of_two_operand (XEXP (x, 1), mode);
5028 return (code == ASHIFT || code == ASHIFTRT || code == LSHIFTRT
5029 || code == ROTATERT);
5032 /* Return TRUE if x is EQ or NE. */
5034 equality_operator (rtx x, enum machine_mode mode ATTRIBUTE_UNUSED)
5036 return GET_CODE (x) == EQ || GET_CODE (x) == NE;
5039 /* Return TRUE if x is a comparison operator other than LTGT or UNEQ. */
5041 arm_comparison_operator (rtx x, enum machine_mode mode)
5043 return (comparison_operator (x, mode)
5044 && GET_CODE (x) != LTGT
5045 && GET_CODE (x) != UNEQ);
5048 /* Return TRUE for SMIN SMAX UMIN UMAX operators. */
5050 minmax_operator (rtx x, enum machine_mode mode)
5052 enum rtx_code code = GET_CODE (x);
5054 if (GET_MODE (x) != mode)
5057 return code == SMIN || code == SMAX || code == UMIN || code == UMAX;
5060 /* Return TRUE if this is the condition code register, if we aren't given
5061 a mode, accept any class CCmode register. */
5063 cc_register (rtx x, enum machine_mode mode)
5065 if (mode == VOIDmode)
5067 mode = GET_MODE (x);
5069 if (GET_MODE_CLASS (mode) != MODE_CC)
5073 if ( GET_MODE (x) == mode
5074 && GET_CODE (x) == REG
5075 && REGNO (x) == CC_REGNUM)
5081 /* Return TRUE if this is the condition code register, if we aren't given
5082 a mode, accept any class CCmode register which indicates a dominance
5085 dominant_cc_register (rtx x, enum machine_mode mode)
5087 if (mode == VOIDmode)
5089 mode = GET_MODE (x);
5091 if (GET_MODE_CLASS (mode) != MODE_CC)
5095 if (mode != CC_DNEmode && mode != CC_DEQmode
5096 && mode != CC_DLEmode && mode != CC_DLTmode
5097 && mode != CC_DGEmode && mode != CC_DGTmode
5098 && mode != CC_DLEUmode && mode != CC_DLTUmode
5099 && mode != CC_DGEUmode && mode != CC_DGTUmode)
5102 return cc_register (x, mode);
5105 /* Return TRUE if X references a SYMBOL_REF. */
5107 symbol_mentioned_p (rtx x)
5112 if (GET_CODE (x) == SYMBOL_REF)
5115 fmt = GET_RTX_FORMAT (GET_CODE (x));
5117 for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
5123 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
5124 if (symbol_mentioned_p (XVECEXP (x, i, j)))
5127 else if (fmt[i] == 'e' && symbol_mentioned_p (XEXP (x, i)))
5134 /* Return TRUE if X references a LABEL_REF. */
5136 label_mentioned_p (rtx x)
5141 if (GET_CODE (x) == LABEL_REF)
5144 fmt = GET_RTX_FORMAT (GET_CODE (x));
5145 for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
5151 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
5152 if (label_mentioned_p (XVECEXP (x, i, j)))
5155 else if (fmt[i] == 'e' && label_mentioned_p (XEXP (x, i)))
5165 enum rtx_code code = GET_CODE (x);
5169 else if (code == SMIN)
5171 else if (code == UMIN)
5173 else if (code == UMAX)
5179 /* Return 1 if memory locations are adjacent. */
5181 adjacent_mem_locations (rtx a, rtx b)
5183 if ((GET_CODE (XEXP (a, 0)) == REG
5184 || (GET_CODE (XEXP (a, 0)) == PLUS
5185 && GET_CODE (XEXP (XEXP (a, 0), 1)) == CONST_INT))
5186 && (GET_CODE (XEXP (b, 0)) == REG
5187 || (GET_CODE (XEXP (b, 0)) == PLUS
5188 && GET_CODE (XEXP (XEXP (b, 0), 1)) == CONST_INT)))
5190 int val0 = 0, val1 = 0;
5193 if (GET_CODE (XEXP (a, 0)) == PLUS)
5195 reg0 = REGNO (XEXP (XEXP (a, 0), 0));
5196 val0 = INTVAL (XEXP (XEXP (a, 0), 1));
5199 reg0 = REGNO (XEXP (a, 0));
5201 if (GET_CODE (XEXP (b, 0)) == PLUS)
5203 reg1 = REGNO (XEXP (XEXP (b, 0), 0));
5204 val1 = INTVAL (XEXP (XEXP (b, 0), 1));
5207 reg1 = REGNO (XEXP (b, 0));
5209 /* Don't accept any offset that will require multiple
5210 instructions to handle, since this would cause the
5211 arith_adjacentmem pattern to output an overlong sequence. */
5212 if (!const_ok_for_op (PLUS, val0) || !const_ok_for_op (PLUS, val1))
5215 return (reg0 == reg1) && ((val1 - val0) == 4 || (val0 - val1) == 4);
5220 /* Return 1 if OP is a load multiple operation. It is known to be
5221 parallel and the first section will be tested. */
5223 load_multiple_operation (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
5225 HOST_WIDE_INT count = XVECLEN (op, 0);
5228 HOST_WIDE_INT i = 1, base = 0;
5232 || GET_CODE (XVECEXP (op, 0, 0)) != SET)
5235 /* Check to see if this might be a write-back. */
5236 if (GET_CODE (SET_SRC (elt = XVECEXP (op, 0, 0))) == PLUS)
5241 /* Now check it more carefully. */
5242 if (GET_CODE (SET_DEST (elt)) != REG
5243 || GET_CODE (XEXP (SET_SRC (elt), 0)) != REG
5244 || GET_CODE (XEXP (SET_SRC (elt), 1)) != CONST_INT
5245 || INTVAL (XEXP (SET_SRC (elt), 1)) != (count - 1) * 4)
5249 /* Perform a quick check so we don't blow up below. */
5251 || GET_CODE (XVECEXP (op, 0, i - 1)) != SET
5252 || GET_CODE (SET_DEST (XVECEXP (op, 0, i - 1))) != REG
5253 || GET_CODE (SET_SRC (XVECEXP (op, 0, i - 1))) != MEM)
5256 dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, i - 1)));
5257 src_addr = XEXP (SET_SRC (XVECEXP (op, 0, i - 1)), 0);
5259 for (; i < count; i++)
5261 elt = XVECEXP (op, 0, i);
5263 if (GET_CODE (elt) != SET
5264 || GET_CODE (SET_DEST (elt)) != REG
5265 || GET_MODE (SET_DEST (elt)) != SImode
5266 || REGNO (SET_DEST (elt)) != (unsigned int)(dest_regno + i - base)
5267 || GET_CODE (SET_SRC (elt)) != MEM
5268 || GET_MODE (SET_SRC (elt)) != SImode
5269 || GET_CODE (XEXP (SET_SRC (elt), 0)) != PLUS
5270 || !rtx_equal_p (XEXP (XEXP (SET_SRC (elt), 0), 0), src_addr)
5271 || GET_CODE (XEXP (XEXP (SET_SRC (elt), 0), 1)) != CONST_INT
5272 || INTVAL (XEXP (XEXP (SET_SRC (elt), 0), 1)) != (i - base) * 4)
5279 /* Return 1 if OP is a store multiple operation. It is known to be
5280 parallel and the first section will be tested. */
5282 store_multiple_operation (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
5284 HOST_WIDE_INT count = XVECLEN (op, 0);
5287 HOST_WIDE_INT i = 1, base = 0;
5291 || GET_CODE (XVECEXP (op, 0, 0)) != SET)
5294 /* Check to see if this might be a write-back. */
5295 if (GET_CODE (SET_SRC (elt = XVECEXP (op, 0, 0))) == PLUS)
5300 /* Now check it more carefully. */
5301 if (GET_CODE (SET_DEST (elt)) != REG
5302 || GET_CODE (XEXP (SET_SRC (elt), 0)) != REG
5303 || GET_CODE (XEXP (SET_SRC (elt), 1)) != CONST_INT
5304 || INTVAL (XEXP (SET_SRC (elt), 1)) != (count - 1) * 4)
5308 /* Perform a quick check so we don't blow up below. */
5310 || GET_CODE (XVECEXP (op, 0, i - 1)) != SET
5311 || GET_CODE (SET_DEST (XVECEXP (op, 0, i - 1))) != MEM
5312 || GET_CODE (SET_SRC (XVECEXP (op, 0, i - 1))) != REG)
5315 src_regno = REGNO (SET_SRC (XVECEXP (op, 0, i - 1)));
5316 dest_addr = XEXP (SET_DEST (XVECEXP (op, 0, i - 1)), 0);
5318 for (; i < count; i++)
5320 elt = XVECEXP (op, 0, i);
5322 if (GET_CODE (elt) != SET
5323 || GET_CODE (SET_SRC (elt)) != REG
5324 || GET_MODE (SET_SRC (elt)) != SImode
5325 || REGNO (SET_SRC (elt)) != (unsigned int)(src_regno + i - base)
5326 || GET_CODE (SET_DEST (elt)) != MEM
5327 || GET_MODE (SET_DEST (elt)) != SImode
5328 || GET_CODE (XEXP (SET_DEST (elt), 0)) != PLUS
5329 || !rtx_equal_p (XEXP (XEXP (SET_DEST (elt), 0), 0), dest_addr)
5330 || GET_CODE (XEXP (XEXP (SET_DEST (elt), 0), 1)) != CONST_INT
5331 || INTVAL (XEXP (XEXP (SET_DEST (elt), 0), 1)) != (i - base) * 4)
5339 load_multiple_sequence (rtx *operands, int nops, int *regs, int *base,
5340 HOST_WIDE_INT *load_offset)
5342 int unsorted_regs[4];
5343 HOST_WIDE_INT unsorted_offsets[4];
5348 /* Can only handle 2, 3, or 4 insns at present,
5349 though could be easily extended if required. */
5350 if (nops < 2 || nops > 4)
5353 /* Loop over the operands and check that the memory references are
5354 suitable (ie immediate offsets from the same base register). At
5355 the same time, extract the target register, and the memory
5357 for (i = 0; i < nops; i++)
5362 /* Convert a subreg of a mem into the mem itself. */
5363 if (GET_CODE (operands[nops + i]) == SUBREG)
5364 operands[nops + i] = alter_subreg (operands + (nops + i));
5366 if (GET_CODE (operands[nops + i]) != MEM)
5369 /* Don't reorder volatile memory references; it doesn't seem worth
5370 looking for the case where the order is ok anyway. */
5371 if (MEM_VOLATILE_P (operands[nops + i]))
5374 offset = const0_rtx;
5376 if ((GET_CODE (reg = XEXP (operands[nops + i], 0)) == REG
5377 || (GET_CODE (reg) == SUBREG
5378 && GET_CODE (reg = SUBREG_REG (reg)) == REG))
5379 || (GET_CODE (XEXP (operands[nops + i], 0)) == PLUS
5380 && ((GET_CODE (reg = XEXP (XEXP (operands[nops + i], 0), 0))
5382 || (GET_CODE (reg) == SUBREG
5383 && GET_CODE (reg = SUBREG_REG (reg)) == REG))
5384 && (GET_CODE (offset = XEXP (XEXP (operands[nops + i], 0), 1))
5389 base_reg = REGNO (reg);
5390 unsorted_regs[0] = (GET_CODE (operands[i]) == REG
5391 ? REGNO (operands[i])
5392 : REGNO (SUBREG_REG (operands[i])));
5397 if (base_reg != (int) REGNO (reg))
5398 /* Not addressed from the same base register. */
5401 unsorted_regs[i] = (GET_CODE (operands[i]) == REG
5402 ? REGNO (operands[i])
5403 : REGNO (SUBREG_REG (operands[i])));
5404 if (unsorted_regs[i] < unsorted_regs[order[0]])
5408 /* If it isn't an integer register, or if it overwrites the
5409 base register but isn't the last insn in the list, then
5410 we can't do this. */
5411 if (unsorted_regs[i] < 0 || unsorted_regs[i] > 14
5412 || (i != nops - 1 && unsorted_regs[i] == base_reg))
5415 unsorted_offsets[i] = INTVAL (offset);
5418 /* Not a suitable memory address. */
5422 /* All the useful information has now been extracted from the
5423 operands into unsorted_regs and unsorted_offsets; additionally,
5424 order[0] has been set to the lowest numbered register in the
5425 list. Sort the registers into order, and check that the memory
5426 offsets are ascending and adjacent. */
5428 for (i = 1; i < nops; i++)
5432 order[i] = order[i - 1];
5433 for (j = 0; j < nops; j++)
5434 if (unsorted_regs[j] > unsorted_regs[order[i - 1]]
5435 && (order[i] == order[i - 1]
5436 || unsorted_regs[j] < unsorted_regs[order[i]]))
5439 /* Have we found a suitable register? if not, one must be used more
5441 if (order[i] == order[i - 1])
5444 /* Is the memory address adjacent and ascending? */
5445 if (unsorted_offsets[order[i]] != unsorted_offsets[order[i - 1]] + 4)
5453 for (i = 0; i < nops; i++)
5454 regs[i] = unsorted_regs[order[i]];
5456 *load_offset = unsorted_offsets[order[0]];
5459 if (unsorted_offsets[order[0]] == 0)
5460 return 1; /* ldmia */
5462 if (unsorted_offsets[order[0]] == 4)
5463 return 2; /* ldmib */
5465 if (unsorted_offsets[order[nops - 1]] == 0)
5466 return 3; /* ldmda */
5468 if (unsorted_offsets[order[nops - 1]] == -4)
5469 return 4; /* ldmdb */
5471 /* For ARM8,9 & StrongARM, 2 ldr instructions are faster than an ldm
5472 if the offset isn't small enough. The reason 2 ldrs are faster
5473 is because these ARMs are able to do more than one cache access
5474 in a single cycle. The ARM9 and StrongARM have Harvard caches,
5475 whilst the ARM8 has a double bandwidth cache. This means that
5476 these cores can do both an instruction fetch and a data fetch in
5477 a single cycle, so the trick of calculating the address into a
5478 scratch register (one of the result regs) and then doing a load
5479 multiple actually becomes slower (and no smaller in code size).
5480 That is the transformation
5482 ldr rd1, [rbase + offset]
5483 ldr rd2, [rbase + offset + 4]
5487 add rd1, rbase, offset
5488 ldmia rd1, {rd1, rd2}
5490 produces worse code -- '3 cycles + any stalls on rd2' instead of
5491 '2 cycles + any stalls on rd2'. On ARMs with only one cache
5492 access per cycle, the first sequence could never complete in less
5493 than 6 cycles, whereas the ldm sequence would only take 5 and
5494 would make better use of sequential accesses if not hitting the
5497 We cheat here and test 'arm_ld_sched' which we currently know to
5498 only be true for the ARM8, ARM9 and StrongARM. If this ever
5499 changes, then the test below needs to be reworked. */
5500 if (nops == 2 && arm_ld_sched)
5503 /* Can't do it without setting up the offset, only do this if it takes
5504 no more than one insn. */
5505 return (const_ok_for_arm (unsorted_offsets[order[0]])
5506 || const_ok_for_arm (-unsorted_offsets[order[0]])) ? 5 : 0;
5510 emit_ldm_seq (rtx *operands, int nops)
5514 HOST_WIDE_INT offset;
5518 switch (load_multiple_sequence (operands, nops, regs, &base_reg, &offset))
5521 strcpy (buf, "ldm%?ia\t");
5525 strcpy (buf, "ldm%?ib\t");
5529 strcpy (buf, "ldm%?da\t");
5533 strcpy (buf, "ldm%?db\t");
5538 sprintf (buf, "add%%?\t%s%s, %s%s, #%ld", REGISTER_PREFIX,
5539 reg_names[regs[0]], REGISTER_PREFIX, reg_names[base_reg],
5542 sprintf (buf, "sub%%?\t%s%s, %s%s, #%ld", REGISTER_PREFIX,
5543 reg_names[regs[0]], REGISTER_PREFIX, reg_names[base_reg],
5545 output_asm_insn (buf, operands);
5547 strcpy (buf, "ldm%?ia\t");
5554 sprintf (buf + strlen (buf), "%s%s, {%s%s", REGISTER_PREFIX,
5555 reg_names[base_reg], REGISTER_PREFIX, reg_names[regs[0]]);
5557 for (i = 1; i < nops; i++)
5558 sprintf (buf + strlen (buf), ", %s%s", REGISTER_PREFIX,
5559 reg_names[regs[i]]);
5561 strcat (buf, "}\t%@ phole ldm");
5563 output_asm_insn (buf, operands);
5568 store_multiple_sequence (rtx *operands, int nops, int *regs, int *base,
5569 HOST_WIDE_INT * load_offset)
5571 int unsorted_regs[4];
5572 HOST_WIDE_INT unsorted_offsets[4];
5577 /* Can only handle 2, 3, or 4 insns at present, though could be easily
5578 extended if required. */
5579 if (nops < 2 || nops > 4)
5582 /* Loop over the operands and check that the memory references are
5583 suitable (ie immediate offsets from the same base register). At
5584 the same time, extract the target register, and the memory
5586 for (i = 0; i < nops; i++)
5591 /* Convert a subreg of a mem into the mem itself. */
5592 if (GET_CODE (operands[nops + i]) == SUBREG)
5593 operands[nops + i] = alter_subreg (operands + (nops + i));
5595 if (GET_CODE (operands[nops + i]) != MEM)
5598 /* Don't reorder volatile memory references; it doesn't seem worth
5599 looking for the case where the order is ok anyway. */
5600 if (MEM_VOLATILE_P (operands[nops + i]))
5603 offset = const0_rtx;
5605 if ((GET_CODE (reg = XEXP (operands[nops + i], 0)) == REG
5606 || (GET_CODE (reg) == SUBREG
5607 && GET_CODE (reg = SUBREG_REG (reg)) == REG))
5608 || (GET_CODE (XEXP (operands[nops + i], 0)) == PLUS
5609 && ((GET_CODE (reg = XEXP (XEXP (operands[nops + i], 0), 0))
5611 || (GET_CODE (reg) == SUBREG
5612 && GET_CODE (reg = SUBREG_REG (reg)) == REG))
5613 && (GET_CODE (offset = XEXP (XEXP (operands[nops + i], 0), 1))
5618 base_reg = REGNO (reg);
5619 unsorted_regs[0] = (GET_CODE (operands[i]) == REG
5620 ? REGNO (operands[i])
5621 : REGNO (SUBREG_REG (operands[i])));
5626 if (base_reg != (int) REGNO (reg))
5627 /* Not addressed from the same base register. */
5630 unsorted_regs[i] = (GET_CODE (operands[i]) == REG
5631 ? REGNO (operands[i])
5632 : REGNO (SUBREG_REG (operands[i])));
5633 if (unsorted_regs[i] < unsorted_regs[order[0]])
5637 /* If it isn't an integer register, then we can't do this. */
5638 if (unsorted_regs[i] < 0 || unsorted_regs[i] > 14)
5641 unsorted_offsets[i] = INTVAL (offset);
5644 /* Not a suitable memory address. */
5648 /* All the useful information has now been extracted from the
5649 operands into unsorted_regs and unsorted_offsets; additionally,
5650 order[0] has been set to the lowest numbered register in the
5651 list. Sort the registers into order, and check that the memory
5652 offsets are ascending and adjacent. */
5654 for (i = 1; i < nops; i++)
5658 order[i] = order[i - 1];
5659 for (j = 0; j < nops; j++)
5660 if (unsorted_regs[j] > unsorted_regs[order[i - 1]]
5661 && (order[i] == order[i - 1]
5662 || unsorted_regs[j] < unsorted_regs[order[i]]))
5665 /* Have we found a suitable register? if not, one must be used more
5667 if (order[i] == order[i - 1])
5670 /* Is the memory address adjacent and ascending? */
5671 if (unsorted_offsets[order[i]] != unsorted_offsets[order[i - 1]] + 4)
5679 for (i = 0; i < nops; i++)
5680 regs[i] = unsorted_regs[order[i]];
5682 *load_offset = unsorted_offsets[order[0]];
5685 if (unsorted_offsets[order[0]] == 0)
5686 return 1; /* stmia */
5688 if (unsorted_offsets[order[0]] == 4)
5689 return 2; /* stmib */
5691 if (unsorted_offsets[order[nops - 1]] == 0)
5692 return 3; /* stmda */
5694 if (unsorted_offsets[order[nops - 1]] == -4)
5695 return 4; /* stmdb */
5701 emit_stm_seq (rtx *operands, int nops)
5705 HOST_WIDE_INT offset;
5709 switch (store_multiple_sequence (operands, nops, regs, &base_reg, &offset))
5712 strcpy (buf, "stm%?ia\t");
5716 strcpy (buf, "stm%?ib\t");
5720 strcpy (buf, "stm%?da\t");
5724 strcpy (buf, "stm%?db\t");
5731 sprintf (buf + strlen (buf), "%s%s, {%s%s", REGISTER_PREFIX,
5732 reg_names[base_reg], REGISTER_PREFIX, reg_names[regs[0]]);
5734 for (i = 1; i < nops; i++)
5735 sprintf (buf + strlen (buf), ", %s%s", REGISTER_PREFIX,
5736 reg_names[regs[i]]);
5738 strcat (buf, "}\t%@ phole stm");
5740 output_asm_insn (buf, operands);
5745 multi_register_push (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
5747 if (GET_CODE (op) != PARALLEL
5748 || (GET_CODE (XVECEXP (op, 0, 0)) != SET)
5749 || (GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != UNSPEC)
5750 || (XINT (SET_SRC (XVECEXP (op, 0, 0)), 1) != UNSPEC_PUSH_MULT))
5756 /* Routines for use in generating RTL. */
5759 arm_gen_load_multiple (int base_regno, int count, rtx from, int up,
5760 int write_back, int unchanging_p, int in_struct_p,
5765 int sign = up ? 1 : -1;
5768 /* XScale has load-store double instructions, but they have stricter
5769 alignment requirements than load-store multiple, so we can not
5772 For XScale ldm requires 2 + NREGS cycles to complete and blocks
5773 the pipeline until completion.
5781 An ldr instruction takes 1-3 cycles, but does not block the
5790 Best case ldr will always win. However, the more ldr instructions
5791 we issue, the less likely we are to be able to schedule them well.
5792 Using ldr instructions also increases code size.
5794 As a compromise, we use ldr for counts of 1 or 2 regs, and ldm
5795 for counts of 3 or 4 regs. */
5796 if (arm_tune_xscale && count <= 2 && ! optimize_size)
5802 for (i = 0; i < count; i++)
5804 mem = gen_rtx_MEM (SImode, plus_constant (from, i * 4 * sign));
5805 RTX_UNCHANGING_P (mem) = unchanging_p;
5806 MEM_IN_STRUCT_P (mem) = in_struct_p;
5807 MEM_SCALAR_P (mem) = scalar_p;
5808 emit_move_insn (gen_rtx_REG (SImode, base_regno + i), mem);
5812 emit_move_insn (from, plus_constant (from, count * 4 * sign));
5820 result = gen_rtx_PARALLEL (VOIDmode,
5821 rtvec_alloc (count + (write_back ? 1 : 0)));
5824 XVECEXP (result, 0, 0)
5825 = gen_rtx_SET (GET_MODE (from), from,
5826 plus_constant (from, count * 4 * sign));
5831 for (j = 0; i < count; i++, j++)
5833 mem = gen_rtx_MEM (SImode, plus_constant (from, j * 4 * sign));
5834 RTX_UNCHANGING_P (mem) = unchanging_p;
5835 MEM_IN_STRUCT_P (mem) = in_struct_p;
5836 MEM_SCALAR_P (mem) = scalar_p;
5837 XVECEXP (result, 0, i)
5838 = gen_rtx_SET (VOIDmode, gen_rtx_REG (SImode, base_regno + j), mem);
5845 arm_gen_store_multiple (int base_regno, int count, rtx to, int up,
5846 int write_back, int unchanging_p, int in_struct_p,
5851 int sign = up ? 1 : -1;
5854 /* See arm_gen_load_multiple for discussion of
5855 the pros/cons of ldm/stm usage for XScale. */
5856 if (arm_tune_xscale && count <= 2 && ! optimize_size)
5862 for (i = 0; i < count; i++)
5864 mem = gen_rtx_MEM (SImode, plus_constant (to, i * 4 * sign));
5865 RTX_UNCHANGING_P (mem) = unchanging_p;
5866 MEM_IN_STRUCT_P (mem) = in_struct_p;
5867 MEM_SCALAR_P (mem) = scalar_p;
5868 emit_move_insn (mem, gen_rtx_REG (SImode, base_regno + i));
5872 emit_move_insn (to, plus_constant (to, count * 4 * sign));
5880 result = gen_rtx_PARALLEL (VOIDmode,
5881 rtvec_alloc (count + (write_back ? 1 : 0)));
5884 XVECEXP (result, 0, 0)
5885 = gen_rtx_SET (GET_MODE (to), to,
5886 plus_constant (to, count * 4 * sign));
5891 for (j = 0; i < count; i++, j++)
5893 mem = gen_rtx_MEM (SImode, plus_constant (to, j * 4 * sign));
5894 RTX_UNCHANGING_P (mem) = unchanging_p;
5895 MEM_IN_STRUCT_P (mem) = in_struct_p;
5896 MEM_SCALAR_P (mem) = scalar_p;
5898 XVECEXP (result, 0, i)
5899 = gen_rtx_SET (VOIDmode, mem, gen_rtx_REG (SImode, base_regno + j));
5906 arm_gen_movmemqi (rtx *operands)
5908 HOST_WIDE_INT in_words_to_go, out_words_to_go, last_bytes;
5911 rtx st_src, st_dst, fin_src, fin_dst;
5912 rtx part_bytes_reg = NULL;
5914 int dst_unchanging_p, dst_in_struct_p, src_unchanging_p, src_in_struct_p;
5915 int dst_scalar_p, src_scalar_p;
5917 if (GET_CODE (operands[2]) != CONST_INT
5918 || GET_CODE (operands[3]) != CONST_INT
5919 || INTVAL (operands[2]) > 64
5920 || INTVAL (operands[3]) & 3)
5923 st_dst = XEXP (operands[0], 0);
5924 st_src = XEXP (operands[1], 0);
5926 dst_unchanging_p = RTX_UNCHANGING_P (operands[0]);
5927 dst_in_struct_p = MEM_IN_STRUCT_P (operands[0]);
5928 dst_scalar_p = MEM_SCALAR_P (operands[0]);
5929 src_unchanging_p = RTX_UNCHANGING_P (operands[1]);
5930 src_in_struct_p = MEM_IN_STRUCT_P (operands[1]);
5931 src_scalar_p = MEM_SCALAR_P (operands[1]);
5933 fin_dst = dst = copy_to_mode_reg (SImode, st_dst);
5934 fin_src = src = copy_to_mode_reg (SImode, st_src);
5936 in_words_to_go = ARM_NUM_INTS (INTVAL (operands[2]));
5937 out_words_to_go = INTVAL (operands[2]) / 4;
5938 last_bytes = INTVAL (operands[2]) & 3;
5940 if (out_words_to_go != in_words_to_go && ((in_words_to_go - 1) & 3) != 0)
5941 part_bytes_reg = gen_rtx_REG (SImode, (in_words_to_go - 1) & 3);
5943 for (i = 0; in_words_to_go >= 2; i+=4)
5945 if (in_words_to_go > 4)
5946 emit_insn (arm_gen_load_multiple (0, 4, src, TRUE, TRUE,
5951 emit_insn (arm_gen_load_multiple (0, in_words_to_go, src, TRUE,
5952 FALSE, src_unchanging_p,
5953 src_in_struct_p, src_scalar_p));
5955 if (out_words_to_go)
5957 if (out_words_to_go > 4)
5958 emit_insn (arm_gen_store_multiple (0, 4, dst, TRUE, TRUE,
5962 else if (out_words_to_go != 1)
5963 emit_insn (arm_gen_store_multiple (0, out_words_to_go,
5972 mem = gen_rtx_MEM (SImode, dst);
5973 RTX_UNCHANGING_P (mem) = dst_unchanging_p;
5974 MEM_IN_STRUCT_P (mem) = dst_in_struct_p;
5975 MEM_SCALAR_P (mem) = dst_scalar_p;
5976 emit_move_insn (mem, gen_rtx_REG (SImode, 0));
5977 if (last_bytes != 0)
5978 emit_insn (gen_addsi3 (dst, dst, GEN_INT (4)));
5982 in_words_to_go -= in_words_to_go < 4 ? in_words_to_go : 4;
5983 out_words_to_go -= out_words_to_go < 4 ? out_words_to_go : 4;
5986 /* OUT_WORDS_TO_GO will be zero here if there are byte stores to do. */
5987 if (out_words_to_go)
5991 mem = gen_rtx_MEM (SImode, src);
5992 RTX_UNCHANGING_P (mem) = src_unchanging_p;
5993 MEM_IN_STRUCT_P (mem) = src_in_struct_p;
5994 MEM_SCALAR_P (mem) = src_scalar_p;
5995 emit_move_insn (sreg = gen_reg_rtx (SImode), mem);
5996 emit_move_insn (fin_src = gen_reg_rtx (SImode), plus_constant (src, 4));
5998 mem = gen_rtx_MEM (SImode, dst);
5999 RTX_UNCHANGING_P (mem) = dst_unchanging_p;
6000 MEM_IN_STRUCT_P (mem) = dst_in_struct_p;
6001 MEM_SCALAR_P (mem) = dst_scalar_p;
6002 emit_move_insn (mem, sreg);
6003 emit_move_insn (fin_dst = gen_reg_rtx (SImode), plus_constant (dst, 4));
6006 if (in_words_to_go) /* Sanity check */
6012 if (in_words_to_go < 0)
6015 mem = gen_rtx_MEM (SImode, src);
6016 RTX_UNCHANGING_P (mem) = src_unchanging_p;
6017 MEM_IN_STRUCT_P (mem) = src_in_struct_p;
6018 MEM_SCALAR_P (mem) = src_scalar_p;
6019 part_bytes_reg = copy_to_mode_reg (SImode, mem);
6022 if (last_bytes && part_bytes_reg == NULL)
6025 if (BYTES_BIG_ENDIAN && last_bytes)
6027 rtx tmp = gen_reg_rtx (SImode);
6029 /* The bytes we want are in the top end of the word. */
6030 emit_insn (gen_lshrsi3 (tmp, part_bytes_reg,
6031 GEN_INT (8 * (4 - last_bytes))));
6032 part_bytes_reg = tmp;
6036 mem = gen_rtx_MEM (QImode, plus_constant (dst, last_bytes - 1));
6037 RTX_UNCHANGING_P (mem) = dst_unchanging_p;
6038 MEM_IN_STRUCT_P (mem) = dst_in_struct_p;
6039 MEM_SCALAR_P (mem) = dst_scalar_p;
6040 emit_move_insn (mem, gen_lowpart (QImode, part_bytes_reg));
6044 tmp = gen_reg_rtx (SImode);
6045 emit_insn (gen_lshrsi3 (tmp, part_bytes_reg, GEN_INT (8)));
6046 part_bytes_reg = tmp;
6055 mem = gen_rtx_MEM (HImode, dst);
6056 RTX_UNCHANGING_P (mem) = dst_unchanging_p;
6057 MEM_IN_STRUCT_P (mem) = dst_in_struct_p;
6058 MEM_SCALAR_P (mem) = dst_scalar_p;
6059 emit_move_insn (mem, gen_lowpart (HImode, part_bytes_reg));
6063 rtx tmp = gen_reg_rtx (SImode);
6065 emit_insn (gen_addsi3 (dst, dst, const2_rtx));
6066 emit_insn (gen_lshrsi3 (tmp, part_bytes_reg, GEN_INT (16)));
6067 part_bytes_reg = tmp;
6073 mem = gen_rtx_MEM (QImode, dst);
6074 RTX_UNCHANGING_P (mem) = dst_unchanging_p;
6075 MEM_IN_STRUCT_P (mem) = dst_in_struct_p;
6076 MEM_SCALAR_P (mem) = dst_scalar_p;
6077 emit_move_insn (mem, gen_lowpart (QImode, part_bytes_reg));
6084 /* Generate a memory reference for a half word, such that it will be loaded
6085 into the top 16 bits of the word. We can assume that the address is
6086 known to be alignable and of the form reg, or plus (reg, const). */
6089 arm_gen_rotated_half_load (rtx memref)
6091 HOST_WIDE_INT offset = 0;
6092 rtx base = XEXP (memref, 0);
6094 if (GET_CODE (base) == PLUS)
6096 offset = INTVAL (XEXP (base, 1));
6097 base = XEXP (base, 0);
6100 /* If we aren't allowed to generate unaligned addresses, then fail. */
6101 if ((BYTES_BIG_ENDIAN ? 1 : 0) ^ ((offset & 2) == 0))
6104 base = gen_rtx_MEM (SImode, plus_constant (base, offset & ~2));
6106 if ((BYTES_BIG_ENDIAN ? 1 : 0) ^ ((offset & 2) == 2))
6109 return gen_rtx_ROTATE (SImode, base, GEN_INT (16));
6112 /* Select a dominance comparison mode if possible for a test of the general
6113 form (OP (COND_OR (X) (Y)) (const_int 0)). We support three forms.
6114 COND_OR == DOM_CC_X_AND_Y => (X && Y)
6115 COND_OR == DOM_CC_NX_OR_Y => ((! X) || Y)
6116 COND_OR == DOM_CC_X_OR_Y => (X || Y)
6117 In all cases OP will be either EQ or NE, but we don't need to know which
6118 here. If we are unable to support a dominance comparison we return
6119 CC mode. This will then fail to match for the RTL expressions that
6120 generate this call. */
6122 arm_select_dominance_cc_mode (rtx x, rtx y, HOST_WIDE_INT cond_or)
6124 enum rtx_code cond1, cond2;
6127 /* Currently we will probably get the wrong result if the individual
6128 comparisons are not simple. This also ensures that it is safe to
6129 reverse a comparison if necessary. */
6130 if ((arm_select_cc_mode (cond1 = GET_CODE (x), XEXP (x, 0), XEXP (x, 1))
6132 || (arm_select_cc_mode (cond2 = GET_CODE (y), XEXP (y, 0), XEXP (y, 1))
6136 /* The if_then_else variant of this tests the second condition if the
6137 first passes, but is true if the first fails. Reverse the first
6138 condition to get a true "inclusive-or" expression. */
6139 if (cond_or == DOM_CC_NX_OR_Y)
6140 cond1 = reverse_condition (cond1);
6142 /* If the comparisons are not equal, and one doesn't dominate the other,
6143 then we can't do this. */
6145 && !comparison_dominates_p (cond1, cond2)
6146 && (swapped = 1, !comparison_dominates_p (cond2, cond1)))
6151 enum rtx_code temp = cond1;
6159 if (cond2 == EQ || cond_or == DOM_CC_X_AND_Y)
6164 case LE: return CC_DLEmode;
6165 case LEU: return CC_DLEUmode;
6166 case GE: return CC_DGEmode;
6167 case GEU: return CC_DGEUmode;
6174 if (cond2 == LT || cond_or == DOM_CC_X_AND_Y)
6183 if (cond2 == GT || cond_or == DOM_CC_X_AND_Y)
6192 if (cond2 == LTU || cond_or == DOM_CC_X_AND_Y)
6201 if (cond2 == GTU || cond_or == DOM_CC_X_AND_Y)
6209 /* The remaining cases only occur when both comparisons are the
6234 arm_select_cc_mode (enum rtx_code op, rtx x, rtx y)
6236 /* All floating point compares return CCFP if it is an equality
6237 comparison, and CCFPE otherwise. */
6238 if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
6258 if (TARGET_HARD_FLOAT && TARGET_MAVERICK)
6267 /* A compare with a shifted operand. Because of canonicalization, the
6268 comparison will have to be swapped when we emit the assembler. */
6269 if (GET_MODE (y) == SImode && GET_CODE (y) == REG
6270 && (GET_CODE (x) == ASHIFT || GET_CODE (x) == ASHIFTRT
6271 || GET_CODE (x) == LSHIFTRT || GET_CODE (x) == ROTATE
6272 || GET_CODE (x) == ROTATERT))
6275 /* This is a special case that is used by combine to allow a
6276 comparison of a shifted byte load to be split into a zero-extend
6277 followed by a comparison of the shifted integer (only valid for
6278 equalities and unsigned inequalities). */
6279 if (GET_MODE (x) == SImode
6280 && GET_CODE (x) == ASHIFT
6281 && GET_CODE (XEXP (x, 1)) == CONST_INT && INTVAL (XEXP (x, 1)) == 24
6282 && GET_CODE (XEXP (x, 0)) == SUBREG
6283 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == MEM
6284 && GET_MODE (SUBREG_REG (XEXP (x, 0))) == QImode
6285 && (op == EQ || op == NE
6286 || op == GEU || op == GTU || op == LTU || op == LEU)
6287 && GET_CODE (y) == CONST_INT)
6290 /* A construct for a conditional compare, if the false arm contains
6291 0, then both conditions must be true, otherwise either condition
6292 must be true. Not all conditions are possible, so CCmode is
6293 returned if it can't be done. */
6294 if (GET_CODE (x) == IF_THEN_ELSE
6295 && (XEXP (x, 2) == const0_rtx
6296 || XEXP (x, 2) == const1_rtx)
6297 && COMPARISON_P (XEXP (x, 0))
6298 && COMPARISON_P (XEXP (x, 1)))
6299 return arm_select_dominance_cc_mode (XEXP (x, 0), XEXP (x, 1),
6300 INTVAL (XEXP (x, 2)));
6302 /* Alternate canonicalizations of the above. These are somewhat cleaner. */
6303 if (GET_CODE (x) == AND
6304 && COMPARISON_P (XEXP (x, 0))
6305 && COMPARISON_P (XEXP (x, 1)))
6306 return arm_select_dominance_cc_mode (XEXP (x, 0), XEXP (x, 1),
6309 if (GET_CODE (x) == IOR
6310 && COMPARISON_P (XEXP (x, 0))
6311 && COMPARISON_P (XEXP (x, 1)))
6312 return arm_select_dominance_cc_mode (XEXP (x, 0), XEXP (x, 1),
6315 /* An operation (on Thumb) where we want to test for a single bit.
6316 This is done by shifting that bit up into the top bit of a
6317 scratch register; we can then branch on the sign bit. */
6319 && GET_MODE (x) == SImode
6320 && (op == EQ || op == NE)
6321 && (GET_CODE (x) == ZERO_EXTRACT))
6324 /* An operation that sets the condition codes as a side-effect, the
6325 V flag is not set correctly, so we can only use comparisons where
6326 this doesn't matter. (For LT and GE we can use "mi" and "pl"
6328 if (GET_MODE (x) == SImode
6330 && (op == EQ || op == NE || op == LT || op == GE)
6331 && (GET_CODE (x) == PLUS || GET_CODE (x) == MINUS
6332 || GET_CODE (x) == AND || GET_CODE (x) == IOR
6333 || GET_CODE (x) == XOR || GET_CODE (x) == MULT
6334 || GET_CODE (x) == NOT || GET_CODE (x) == NEG
6335 || GET_CODE (x) == LSHIFTRT
6336 || GET_CODE (x) == ASHIFT || GET_CODE (x) == ASHIFTRT
6337 || GET_CODE (x) == ROTATERT
6338 || (TARGET_ARM && GET_CODE (x) == ZERO_EXTRACT)))
6341 if (GET_MODE (x) == QImode && (op == EQ || op == NE))
6344 if (GET_MODE (x) == SImode && (op == LTU || op == GEU)
6345 && GET_CODE (x) == PLUS
6346 && (rtx_equal_p (XEXP (x, 0), y) || rtx_equal_p (XEXP (x, 1), y)))
6352 /* X and Y are two things to compare using CODE. Emit the compare insn and
6353 return the rtx for register 0 in the proper mode. FP means this is a
6354 floating point compare: I don't think that it is needed on the arm. */
6356 arm_gen_compare_reg (enum rtx_code code, rtx x, rtx y)
6358 enum machine_mode mode = SELECT_CC_MODE (code, x, y);
6359 rtx cc_reg = gen_rtx_REG (mode, CC_REGNUM);
6361 emit_insn (gen_rtx_SET (VOIDmode, cc_reg,
6362 gen_rtx_COMPARE (mode, x, y)));
6367 /* Generate a sequence of insns that will generate the correct return
6368 address mask depending on the physical architecture that the program
6371 arm_gen_return_addr_mask (void)
6373 rtx reg = gen_reg_rtx (Pmode);
6375 emit_insn (gen_return_addr_mask (reg));
6380 arm_reload_in_hi (rtx *operands)
6382 rtx ref = operands[1];
6384 HOST_WIDE_INT offset = 0;
6386 if (GET_CODE (ref) == SUBREG)
6388 offset = SUBREG_BYTE (ref);
6389 ref = SUBREG_REG (ref);
6392 if (GET_CODE (ref) == REG)
6394 /* We have a pseudo which has been spilt onto the stack; there
6395 are two cases here: the first where there is a simple
6396 stack-slot replacement and a second where the stack-slot is
6397 out of range, or is used as a subreg. */
6398 if (reg_equiv_mem[REGNO (ref)])
6400 ref = reg_equiv_mem[REGNO (ref)];
6401 base = find_replacement (&XEXP (ref, 0));
6404 /* The slot is out of range, or was dressed up in a SUBREG. */
6405 base = reg_equiv_address[REGNO (ref)];
6408 base = find_replacement (&XEXP (ref, 0));
6410 /* Handle the case where the address is too complex to be offset by 1. */
6411 if (GET_CODE (base) == MINUS
6412 || (GET_CODE (base) == PLUS && GET_CODE (XEXP (base, 1)) != CONST_INT))
6414 rtx base_plus = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
6416 emit_insn (gen_rtx_SET (VOIDmode, base_plus, base));
6419 else if (GET_CODE (base) == PLUS)
6421 /* The addend must be CONST_INT, or we would have dealt with it above. */
6422 HOST_WIDE_INT hi, lo;
6424 offset += INTVAL (XEXP (base, 1));
6425 base = XEXP (base, 0);
6427 /* Rework the address into a legal sequence of insns. */
6428 /* Valid range for lo is -4095 -> 4095 */
6431 : -((-offset) & 0xfff));
6433 /* Corner case, if lo is the max offset then we would be out of range
6434 once we have added the additional 1 below, so bump the msb into the
6435 pre-loading insn(s). */
6439 hi = ((((offset - lo) & (HOST_WIDE_INT) 0xffffffff)
6440 ^ (HOST_WIDE_INT) 0x80000000)
6441 - (HOST_WIDE_INT) 0x80000000);
6443 if (hi + lo != offset)
6448 rtx base_plus = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
6450 /* Get the base address; addsi3 knows how to handle constants
6451 that require more than one insn. */
6452 emit_insn (gen_addsi3 (base_plus, base, GEN_INT (hi)));
6458 /* Operands[2] may overlap operands[0] (though it won't overlap
6459 operands[1]), that's why we asked for a DImode reg -- so we can
6460 use the bit that does not overlap. */
6461 if (REGNO (operands[2]) == REGNO (operands[0]))
6462 scratch = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
6464 scratch = gen_rtx_REG (SImode, REGNO (operands[2]));
6466 emit_insn (gen_zero_extendqisi2 (scratch,
6467 gen_rtx_MEM (QImode,
6468 plus_constant (base,
6470 emit_insn (gen_zero_extendqisi2 (gen_rtx_SUBREG (SImode, operands[0], 0),
6471 gen_rtx_MEM (QImode,
6472 plus_constant (base,
6474 if (!BYTES_BIG_ENDIAN)
6475 emit_insn (gen_rtx_SET (VOIDmode, gen_rtx_SUBREG (SImode, operands[0], 0),
6476 gen_rtx_IOR (SImode,
6479 gen_rtx_SUBREG (SImode, operands[0], 0),
6483 emit_insn (gen_rtx_SET (VOIDmode, gen_rtx_SUBREG (SImode, operands[0], 0),
6484 gen_rtx_IOR (SImode,
6485 gen_rtx_ASHIFT (SImode, scratch,
6487 gen_rtx_SUBREG (SImode, operands[0],
6491 /* Handle storing a half-word to memory during reload by synthesizing as two
6492 byte stores. Take care not to clobber the input values until after we
6493 have moved them somewhere safe. This code assumes that if the DImode
6494 scratch in operands[2] overlaps either the input value or output address
6495 in some way, then that value must die in this insn (we absolutely need
6496 two scratch registers for some corner cases). */
6498 arm_reload_out_hi (rtx *operands)
6500 rtx ref = operands[0];
6501 rtx outval = operands[1];
6503 HOST_WIDE_INT offset = 0;
6505 if (GET_CODE (ref) == SUBREG)
6507 offset = SUBREG_BYTE (ref);
6508 ref = SUBREG_REG (ref);
6511 if (GET_CODE (ref) == REG)
6513 /* We have a pseudo which has been spilt onto the stack; there
6514 are two cases here: the first where there is a simple
6515 stack-slot replacement and a second where the stack-slot is
6516 out of range, or is used as a subreg. */
6517 if (reg_equiv_mem[REGNO (ref)])
6519 ref = reg_equiv_mem[REGNO (ref)];
6520 base = find_replacement (&XEXP (ref, 0));
6523 /* The slot is out of range, or was dressed up in a SUBREG. */
6524 base = reg_equiv_address[REGNO (ref)];
6527 base = find_replacement (&XEXP (ref, 0));
6529 scratch = gen_rtx_REG (SImode, REGNO (operands[2]));
6531 /* Handle the case where the address is too complex to be offset by 1. */
6532 if (GET_CODE (base) == MINUS
6533 || (GET_CODE (base) == PLUS && GET_CODE (XEXP (base, 1)) != CONST_INT))
6535 rtx base_plus = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
6537 /* Be careful not to destroy OUTVAL. */
6538 if (reg_overlap_mentioned_p (base_plus, outval))
6540 /* Updating base_plus might destroy outval, see if we can
6541 swap the scratch and base_plus. */
6542 if (!reg_overlap_mentioned_p (scratch, outval))
6545 scratch = base_plus;
6550 rtx scratch_hi = gen_rtx_REG (HImode, REGNO (operands[2]));
6552 /* Be conservative and copy OUTVAL into the scratch now,
6553 this should only be necessary if outval is a subreg
6554 of something larger than a word. */
6555 /* XXX Might this clobber base? I can't see how it can,
6556 since scratch is known to overlap with OUTVAL, and
6557 must be wider than a word. */
6558 emit_insn (gen_movhi (scratch_hi, outval));
6559 outval = scratch_hi;
6563 emit_insn (gen_rtx_SET (VOIDmode, base_plus, base));
6566 else if (GET_CODE (base) == PLUS)
6568 /* The addend must be CONST_INT, or we would have dealt with it above. */
6569 HOST_WIDE_INT hi, lo;
6571 offset += INTVAL (XEXP (base, 1));
6572 base = XEXP (base, 0);
6574 /* Rework the address into a legal sequence of insns. */
6575 /* Valid range for lo is -4095 -> 4095 */
6578 : -((-offset) & 0xfff));
6580 /* Corner case, if lo is the max offset then we would be out of range
6581 once we have added the additional 1 below, so bump the msb into the
6582 pre-loading insn(s). */
6586 hi = ((((offset - lo) & (HOST_WIDE_INT) 0xffffffff)
6587 ^ (HOST_WIDE_INT) 0x80000000)
6588 - (HOST_WIDE_INT) 0x80000000);
6590 if (hi + lo != offset)
6595 rtx base_plus = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
6597 /* Be careful not to destroy OUTVAL. */
6598 if (reg_overlap_mentioned_p (base_plus, outval))
6600 /* Updating base_plus might destroy outval, see if we
6601 can swap the scratch and base_plus. */
6602 if (!reg_overlap_mentioned_p (scratch, outval))
6605 scratch = base_plus;
6610 rtx scratch_hi = gen_rtx_REG (HImode, REGNO (operands[2]));
6612 /* Be conservative and copy outval into scratch now,
6613 this should only be necessary if outval is a
6614 subreg of something larger than a word. */
6615 /* XXX Might this clobber base? I can't see how it
6616 can, since scratch is known to overlap with
6618 emit_insn (gen_movhi (scratch_hi, outval));
6619 outval = scratch_hi;
6623 /* Get the base address; addsi3 knows how to handle constants
6624 that require more than one insn. */
6625 emit_insn (gen_addsi3 (base_plus, base, GEN_INT (hi)));
6631 if (BYTES_BIG_ENDIAN)
6633 emit_insn (gen_movqi (gen_rtx_MEM (QImode,
6634 plus_constant (base, offset + 1)),
6635 gen_lowpart (QImode, outval)));
6636 emit_insn (gen_lshrsi3 (scratch,
6637 gen_rtx_SUBREG (SImode, outval, 0),
6639 emit_insn (gen_movqi (gen_rtx_MEM (QImode, plus_constant (base, offset)),
6640 gen_lowpart (QImode, scratch)));
6644 emit_insn (gen_movqi (gen_rtx_MEM (QImode, plus_constant (base, offset)),
6645 gen_lowpart (QImode, outval)));
6646 emit_insn (gen_lshrsi3 (scratch,
6647 gen_rtx_SUBREG (SImode, outval, 0),
6649 emit_insn (gen_movqi (gen_rtx_MEM (QImode,
6650 plus_constant (base, offset + 1)),
6651 gen_lowpart (QImode, scratch)));
6655 /* Print a symbolic form of X to the debug file, F. */
6657 arm_print_value (FILE *f, rtx x)
6659 switch (GET_CODE (x))
6662 fprintf (f, HOST_WIDE_INT_PRINT_HEX, INTVAL (x));
6666 fprintf (f, "<0x%lx,0x%lx>", (long)XWINT (x, 2), (long)XWINT (x, 3));
6674 for (i = 0; i < CONST_VECTOR_NUNITS (x); i++)
6676 fprintf (f, HOST_WIDE_INT_PRINT_HEX, INTVAL (CONST_VECTOR_ELT (x, i)));
6677 if (i < (CONST_VECTOR_NUNITS (x) - 1))
6685 fprintf (f, "\"%s\"", XSTR (x, 0));
6689 fprintf (f, "`%s'", XSTR (x, 0));
6693 fprintf (f, "L%d", INSN_UID (XEXP (x, 0)));
6697 arm_print_value (f, XEXP (x, 0));
6701 arm_print_value (f, XEXP (x, 0));
6703 arm_print_value (f, XEXP (x, 1));
6711 fprintf (f, "????");
6716 /* Routines for manipulation of the constant pool. */
6718 /* Arm instructions cannot load a large constant directly into a
6719 register; they have to come from a pc relative load. The constant
6720 must therefore be placed in the addressable range of the pc
6721 relative load. Depending on the precise pc relative load
6722 instruction the range is somewhere between 256 bytes and 4k. This
6723 means that we often have to dump a constant inside a function, and
6724 generate code to branch around it.
6726 It is important to minimize this, since the branches will slow
6727 things down and make the code larger.
6729 Normally we can hide the table after an existing unconditional
6730 branch so that there is no interruption of the flow, but in the
6731 worst case the code looks like this:
6749 We fix this by performing a scan after scheduling, which notices
6750 which instructions need to have their operands fetched from the
6751 constant table and builds the table.
6753 The algorithm starts by building a table of all the constants that
6754 need fixing up and all the natural barriers in the function (places
6755 where a constant table can be dropped without breaking the flow).
6756 For each fixup we note how far the pc-relative replacement will be
6757 able to reach and the offset of the instruction into the function.
6759 Having built the table we then group the fixes together to form
6760 tables that are as large as possible (subject to addressing
6761 constraints) and emit each table of constants after the last
6762 barrier that is within range of all the instructions in the group.
6763 If a group does not contain a barrier, then we forcibly create one
6764 by inserting a jump instruction into the flow. Once the table has
6765 been inserted, the insns are then modified to reference the
6766 relevant entry in the pool.
6768 Possible enhancements to the algorithm (not implemented) are:
6770 1) For some processors and object formats, there may be benefit in
6771 aligning the pools to the start of cache lines; this alignment
6772 would need to be taken into account when calculating addressability
6775 /* These typedefs are located at the start of this file, so that
6776 they can be used in the prototypes there. This comment is to
6777 remind readers of that fact so that the following structures
6778 can be understood more easily.
6780 typedef struct minipool_node Mnode;
6781 typedef struct minipool_fixup Mfix; */
6783 struct minipool_node
6785 /* Doubly linked chain of entries. */
6788 /* The maximum offset into the code that this entry can be placed. While
6789 pushing fixes for forward references, all entries are sorted in order
6790 of increasing max_address. */
6791 HOST_WIDE_INT max_address;
6792 /* Similarly for an entry inserted for a backwards ref. */
6793 HOST_WIDE_INT min_address;
6794 /* The number of fixes referencing this entry. This can become zero
6795 if we "unpush" an entry. In this case we ignore the entry when we
6796 come to emit the code. */
6798 /* The offset from the start of the minipool. */
6799 HOST_WIDE_INT offset;
6800 /* The value in table. */
6802 /* The mode of value. */
6803 enum machine_mode mode;
6804 /* The size of the value. With iWMMXt enabled
6805 sizes > 4 also imply an alignment of 8-bytes. */
6809 struct minipool_fixup
6813 HOST_WIDE_INT address;
6815 enum machine_mode mode;
6819 HOST_WIDE_INT forwards;
6820 HOST_WIDE_INT backwards;
6823 /* Fixes less than a word need padding out to a word boundary. */
6824 #define MINIPOOL_FIX_SIZE(mode) \
6825 (GET_MODE_SIZE ((mode)) >= 4 ? GET_MODE_SIZE ((mode)) : 4)
6827 static Mnode * minipool_vector_head;
6828 static Mnode * minipool_vector_tail;
6829 static rtx minipool_vector_label;
6831 /* The linked list of all minipool fixes required for this function. */
6832 Mfix * minipool_fix_head;
6833 Mfix * minipool_fix_tail;
6834 /* The fix entry for the current minipool, once it has been placed. */
6835 Mfix * minipool_barrier;
6837 /* Determines if INSN is the start of a jump table. Returns the end
6838 of the TABLE or NULL_RTX. */
6840 is_jump_table (rtx insn)
6844 if (GET_CODE (insn) == JUMP_INSN
6845 && JUMP_LABEL (insn) != NULL
6846 && ((table = next_real_insn (JUMP_LABEL (insn)))
6847 == next_real_insn (insn))
6849 && GET_CODE (table) == JUMP_INSN
6850 && (GET_CODE (PATTERN (table)) == ADDR_VEC
6851 || GET_CODE (PATTERN (table)) == ADDR_DIFF_VEC))
6857 #ifndef JUMP_TABLES_IN_TEXT_SECTION
6858 #define JUMP_TABLES_IN_TEXT_SECTION 0
6861 static HOST_WIDE_INT
6862 get_jump_table_size (rtx insn)
6864 /* ADDR_VECs only take room if read-only data does into the text
6866 if (JUMP_TABLES_IN_TEXT_SECTION
6867 #if !defined(READONLY_DATA_SECTION) && !defined(READONLY_DATA_SECTION_ASM_OP)
6872 rtx body = PATTERN (insn);
6873 int elt = GET_CODE (body) == ADDR_DIFF_VEC ? 1 : 0;
6875 return GET_MODE_SIZE (GET_MODE (body)) * XVECLEN (body, elt);
6881 /* Move a minipool fix MP from its current location to before MAX_MP.
6882 If MAX_MP is NULL, then MP doesn't need moving, but the addressing
6883 constraints may need updating. */
6885 move_minipool_fix_forward_ref (Mnode *mp, Mnode *max_mp,
6886 HOST_WIDE_INT max_address)
6888 /* This should never be true and the code below assumes these are
6895 if (max_address < mp->max_address)
6896 mp->max_address = max_address;
6900 if (max_address > max_mp->max_address - mp->fix_size)
6901 mp->max_address = max_mp->max_address - mp->fix_size;
6903 mp->max_address = max_address;
6905 /* Unlink MP from its current position. Since max_mp is non-null,
6906 mp->prev must be non-null. */
6907 mp->prev->next = mp->next;
6908 if (mp->next != NULL)
6909 mp->next->prev = mp->prev;
6911 minipool_vector_tail = mp->prev;
6913 /* Re-insert it before MAX_MP. */
6915 mp->prev = max_mp->prev;
6918 if (mp->prev != NULL)
6919 mp->prev->next = mp;
6921 minipool_vector_head = mp;
6924 /* Save the new entry. */
6927 /* Scan over the preceding entries and adjust their addresses as
6929 while (mp->prev != NULL
6930 && mp->prev->max_address > mp->max_address - mp->prev->fix_size)
6932 mp->prev->max_address = mp->max_address - mp->prev->fix_size;
6939 /* Add a constant to the minipool for a forward reference. Returns the
6940 node added or NULL if the constant will not fit in this pool. */
6942 add_minipool_forward_ref (Mfix *fix)
6944 /* If set, max_mp is the first pool_entry that has a lower
6945 constraint than the one we are trying to add. */
6946 Mnode * max_mp = NULL;
6947 HOST_WIDE_INT max_address = fix->address + fix->forwards;
6950 /* If this fix's address is greater than the address of the first
6951 entry, then we can't put the fix in this pool. We subtract the
6952 size of the current fix to ensure that if the table is fully
6953 packed we still have enough room to insert this value by suffling
6954 the other fixes forwards. */
6955 if (minipool_vector_head &&
6956 fix->address >= minipool_vector_head->max_address - fix->fix_size)
6959 /* Scan the pool to see if a constant with the same value has
6960 already been added. While we are doing this, also note the
6961 location where we must insert the constant if it doesn't already
6963 for (mp = minipool_vector_head; mp != NULL; mp = mp->next)
6965 if (GET_CODE (fix->value) == GET_CODE (mp->value)
6966 && fix->mode == mp->mode
6967 && (GET_CODE (fix->value) != CODE_LABEL
6968 || (CODE_LABEL_NUMBER (fix->value)
6969 == CODE_LABEL_NUMBER (mp->value)))
6970 && rtx_equal_p (fix->value, mp->value))
6972 /* More than one fix references this entry. */
6974 return move_minipool_fix_forward_ref (mp, max_mp, max_address);
6977 /* Note the insertion point if necessary. */
6979 && mp->max_address > max_address)
6982 /* If we are inserting an 8-bytes aligned quantity and
6983 we have not already found an insertion point, then
6984 make sure that all such 8-byte aligned quantities are
6985 placed at the start of the pool. */
6986 if (ARM_DOUBLEWORD_ALIGN
6988 && fix->fix_size == 8
6989 && mp->fix_size != 8)
6992 max_address = mp->max_address;
6996 /* The value is not currently in the minipool, so we need to create
6997 a new entry for it. If MAX_MP is NULL, the entry will be put on
6998 the end of the list since the placement is less constrained than
6999 any existing entry. Otherwise, we insert the new fix before
7000 MAX_MP and, if necessary, adjust the constraints on the other
7002 mp = xmalloc (sizeof (* mp));
7003 mp->fix_size = fix->fix_size;
7004 mp->mode = fix->mode;
7005 mp->value = fix->value;
7007 /* Not yet required for a backwards ref. */
7008 mp->min_address = -65536;
7012 mp->max_address = max_address;
7014 mp->prev = minipool_vector_tail;
7016 if (mp->prev == NULL)
7018 minipool_vector_head = mp;
7019 minipool_vector_label = gen_label_rtx ();
7022 mp->prev->next = mp;
7024 minipool_vector_tail = mp;
7028 if (max_address > max_mp->max_address - mp->fix_size)
7029 mp->max_address = max_mp->max_address - mp->fix_size;
7031 mp->max_address = max_address;
7034 mp->prev = max_mp->prev;
7036 if (mp->prev != NULL)
7037 mp->prev->next = mp;
7039 minipool_vector_head = mp;
7042 /* Save the new entry. */
7045 /* Scan over the preceding entries and adjust their addresses as
7047 while (mp->prev != NULL
7048 && mp->prev->max_address > mp->max_address - mp->prev->fix_size)
7050 mp->prev->max_address = mp->max_address - mp->prev->fix_size;
7058 move_minipool_fix_backward_ref (Mnode *mp, Mnode *min_mp,
7059 HOST_WIDE_INT min_address)
7061 HOST_WIDE_INT offset;
7063 /* This should never be true, and the code below assumes these are
7070 if (min_address > mp->min_address)
7071 mp->min_address = min_address;
7075 /* We will adjust this below if it is too loose. */
7076 mp->min_address = min_address;
7078 /* Unlink MP from its current position. Since min_mp is non-null,
7079 mp->next must be non-null. */
7080 mp->next->prev = mp->prev;
7081 if (mp->prev != NULL)
7082 mp->prev->next = mp->next;
7084 minipool_vector_head = mp->next;
7086 /* Reinsert it after MIN_MP. */
7088 mp->next = min_mp->next;
7090 if (mp->next != NULL)
7091 mp->next->prev = mp;
7093 minipool_vector_tail = mp;
7099 for (mp = minipool_vector_head; mp != NULL; mp = mp->next)
7101 mp->offset = offset;
7102 if (mp->refcount > 0)
7103 offset += mp->fix_size;
7105 if (mp->next && mp->next->min_address < mp->min_address + mp->fix_size)
7106 mp->next->min_address = mp->min_address + mp->fix_size;
7112 /* Add a constant to the minipool for a backward reference. Returns the
7113 node added or NULL if the constant will not fit in this pool.
7115 Note that the code for insertion for a backwards reference can be
7116 somewhat confusing because the calculated offsets for each fix do
7117 not take into account the size of the pool (which is still under
7120 add_minipool_backward_ref (Mfix *fix)
7122 /* If set, min_mp is the last pool_entry that has a lower constraint
7123 than the one we are trying to add. */
7124 Mnode *min_mp = NULL;
7125 /* This can be negative, since it is only a constraint. */
7126 HOST_WIDE_INT min_address = fix->address - fix->backwards;
7129 /* If we can't reach the current pool from this insn, or if we can't
7130 insert this entry at the end of the pool without pushing other
7131 fixes out of range, then we don't try. This ensures that we
7132 can't fail later on. */
7133 if (min_address >= minipool_barrier->address
7134 || (minipool_vector_tail->min_address + fix->fix_size
7135 >= minipool_barrier->address))
7138 /* Scan the pool to see if a constant with the same value has
7139 already been added. While we are doing this, also note the
7140 location where we must insert the constant if it doesn't already
7142 for (mp = minipool_vector_tail; mp != NULL; mp = mp->prev)
7144 if (GET_CODE (fix->value) == GET_CODE (mp->value)
7145 && fix->mode == mp->mode
7146 && (GET_CODE (fix->value) != CODE_LABEL
7147 || (CODE_LABEL_NUMBER (fix->value)
7148 == CODE_LABEL_NUMBER (mp->value)))
7149 && rtx_equal_p (fix->value, mp->value)
7150 /* Check that there is enough slack to move this entry to the
7151 end of the table (this is conservative). */
7153 > (minipool_barrier->address
7154 + minipool_vector_tail->offset
7155 + minipool_vector_tail->fix_size)))
7158 return move_minipool_fix_backward_ref (mp, min_mp, min_address);
7162 mp->min_address += fix->fix_size;
7165 /* Note the insertion point if necessary. */
7166 if (mp->min_address < min_address)
7168 /* For now, we do not allow the insertion of 8-byte alignment
7169 requiring nodes anywhere but at the start of the pool. */
7170 if (ARM_DOUBLEWORD_ALIGN
7171 && fix->fix_size == 8 && mp->fix_size != 8)
7176 else if (mp->max_address
7177 < minipool_barrier->address + mp->offset + fix->fix_size)
7179 /* Inserting before this entry would push the fix beyond
7180 its maximum address (which can happen if we have
7181 re-located a forwards fix); force the new fix to come
7184 min_address = mp->min_address + fix->fix_size;
7186 /* If we are inserting an 8-bytes aligned quantity and
7187 we have not already found an insertion point, then
7188 make sure that all such 8-byte aligned quantities are
7189 placed at the start of the pool. */
7190 else if (ARM_DOUBLEWORD_ALIGN
7192 && fix->fix_size == 8
7193 && mp->fix_size < 8)
7196 min_address = mp->min_address + fix->fix_size;
7201 /* We need to create a new entry. */
7202 mp = xmalloc (sizeof (* mp));
7203 mp->fix_size = fix->fix_size;
7204 mp->mode = fix->mode;
7205 mp->value = fix->value;
7207 mp->max_address = minipool_barrier->address + 65536;
7209 mp->min_address = min_address;
7214 mp->next = minipool_vector_head;
7216 if (mp->next == NULL)
7218 minipool_vector_tail = mp;
7219 minipool_vector_label = gen_label_rtx ();
7222 mp->next->prev = mp;
7224 minipool_vector_head = mp;
7228 mp->next = min_mp->next;
7232 if (mp->next != NULL)
7233 mp->next->prev = mp;
7235 minipool_vector_tail = mp;
7238 /* Save the new entry. */
7246 /* Scan over the following entries and adjust their offsets. */
7247 while (mp->next != NULL)
7249 if (mp->next->min_address < mp->min_address + mp->fix_size)
7250 mp->next->min_address = mp->min_address + mp->fix_size;
7253 mp->next->offset = mp->offset + mp->fix_size;
7255 mp->next->offset = mp->offset;
7264 assign_minipool_offsets (Mfix *barrier)
7266 HOST_WIDE_INT offset = 0;
7269 minipool_barrier = barrier;
7271 for (mp = minipool_vector_head; mp != NULL; mp = mp->next)
7273 mp->offset = offset;
7275 if (mp->refcount > 0)
7276 offset += mp->fix_size;
7280 /* Output the literal table */
7282 dump_minipool (rtx scan)
7288 if (ARM_DOUBLEWORD_ALIGN)
7289 for (mp = minipool_vector_head; mp != NULL; mp = mp->next)
7290 if (mp->refcount > 0 && mp->fix_size == 8)
7298 ";; Emitting minipool after insn %u; address %ld; align %d (bytes)\n",
7299 INSN_UID (scan), (unsigned long) minipool_barrier->address, align64 ? 8 : 4);
7301 scan = emit_label_after (gen_label_rtx (), scan);
7302 scan = emit_insn_after (align64 ? gen_align_8 () : gen_align_4 (), scan);
7303 scan = emit_label_after (minipool_vector_label, scan);
7305 for (mp = minipool_vector_head; mp != NULL; mp = nmp)
7307 if (mp->refcount > 0)
7312 ";; Offset %u, min %ld, max %ld ",
7313 (unsigned) mp->offset, (unsigned long) mp->min_address,
7314 (unsigned long) mp->max_address);
7315 arm_print_value (dump_file, mp->value);
7316 fputc ('\n', dump_file);
7319 switch (mp->fix_size)
7321 #ifdef HAVE_consttable_1
7323 scan = emit_insn_after (gen_consttable_1 (mp->value), scan);
7327 #ifdef HAVE_consttable_2
7329 scan = emit_insn_after (gen_consttable_2 (mp->value), scan);
7333 #ifdef HAVE_consttable_4
7335 scan = emit_insn_after (gen_consttable_4 (mp->value), scan);
7339 #ifdef HAVE_consttable_8
7341 scan = emit_insn_after (gen_consttable_8 (mp->value), scan);
7355 minipool_vector_head = minipool_vector_tail = NULL;
7356 scan = emit_insn_after (gen_consttable_end (), scan);
7357 scan = emit_barrier_after (scan);
7360 /* Return the cost of forcibly inserting a barrier after INSN. */
7362 arm_barrier_cost (rtx insn)
7364 /* Basing the location of the pool on the loop depth is preferable,
7365 but at the moment, the basic block information seems to be
7366 corrupt by this stage of the compilation. */
7368 rtx next = next_nonnote_insn (insn);
7370 if (next != NULL && GET_CODE (next) == CODE_LABEL)
7373 switch (GET_CODE (insn))
7376 /* It will always be better to place the table before the label, rather
7385 return base_cost - 10;
7388 return base_cost + 10;
7392 /* Find the best place in the insn stream in the range
7393 (FIX->address,MAX_ADDRESS) to forcibly insert a minipool barrier.
7394 Create the barrier by inserting a jump and add a new fix entry for
7397 create_fix_barrier (Mfix *fix, HOST_WIDE_INT max_address)
7399 HOST_WIDE_INT count = 0;
7401 rtx from = fix->insn;
7402 rtx selected = from;
7404 HOST_WIDE_INT selected_address;
7406 HOST_WIDE_INT max_count = max_address - fix->address;
7407 rtx label = gen_label_rtx ();
7409 selected_cost = arm_barrier_cost (from);
7410 selected_address = fix->address;
7412 while (from && count < max_count)
7417 /* This code shouldn't have been called if there was a natural barrier
7419 if (GET_CODE (from) == BARRIER)
7422 /* Count the length of this insn. */
7423 count += get_attr_length (from);
7425 /* If there is a jump table, add its length. */
7426 tmp = is_jump_table (from);
7429 count += get_jump_table_size (tmp);
7431 /* Jump tables aren't in a basic block, so base the cost on
7432 the dispatch insn. If we select this location, we will
7433 still put the pool after the table. */
7434 new_cost = arm_barrier_cost (from);
7436 if (count < max_count && new_cost <= selected_cost)
7439 selected_cost = new_cost;
7440 selected_address = fix->address + count;
7443 /* Continue after the dispatch table. */
7444 from = NEXT_INSN (tmp);
7448 new_cost = arm_barrier_cost (from);
7450 if (count < max_count && new_cost <= selected_cost)
7453 selected_cost = new_cost;
7454 selected_address = fix->address + count;
7457 from = NEXT_INSN (from);
7460 /* Create a new JUMP_INSN that branches around a barrier. */
7461 from = emit_jump_insn_after (gen_jump (label), selected);
7462 JUMP_LABEL (from) = label;
7463 barrier = emit_barrier_after (from);
7464 emit_label_after (label, barrier);
7466 /* Create a minipool barrier entry for the new barrier. */
7467 new_fix = (Mfix *) obstack_alloc (&minipool_obstack, sizeof (* new_fix));
7468 new_fix->insn = barrier;
7469 new_fix->address = selected_address;
7470 new_fix->next = fix->next;
7471 fix->next = new_fix;
7476 /* Record that there is a natural barrier in the insn stream at
7479 push_minipool_barrier (rtx insn, HOST_WIDE_INT address)
7481 Mfix * fix = (Mfix *) obstack_alloc (&minipool_obstack, sizeof (* fix));
7484 fix->address = address;
7487 if (minipool_fix_head != NULL)
7488 minipool_fix_tail->next = fix;
7490 minipool_fix_head = fix;
7492 minipool_fix_tail = fix;
7495 /* Record INSN, which will need fixing up to load a value from the
7496 minipool. ADDRESS is the offset of the insn since the start of the
7497 function; LOC is a pointer to the part of the insn which requires
7498 fixing; VALUE is the constant that must be loaded, which is of type
7501 push_minipool_fix (rtx insn, HOST_WIDE_INT address, rtx *loc,
7502 enum machine_mode mode, rtx value)
7504 Mfix * fix = (Mfix *) obstack_alloc (&minipool_obstack, sizeof (* fix));
7506 #ifdef AOF_ASSEMBLER
7507 /* PIC symbol references need to be converted into offsets into the
7509 /* XXX This shouldn't be done here. */
7510 if (flag_pic && GET_CODE (value) == SYMBOL_REF)
7511 value = aof_pic_entry (value);
7512 #endif /* AOF_ASSEMBLER */
7515 fix->address = address;
7518 fix->fix_size = MINIPOOL_FIX_SIZE (mode);
7520 fix->forwards = get_attr_pool_range (insn);
7521 fix->backwards = get_attr_neg_pool_range (insn);
7522 fix->minipool = NULL;
7524 /* If an insn doesn't have a range defined for it, then it isn't
7525 expecting to be reworked by this code. Better to abort now than
7526 to generate duff assembly code. */
7527 if (fix->forwards == 0 && fix->backwards == 0)
7530 /* With AAPCS/iWMMXt enabled, the pool is aligned to an 8-byte boundary.
7531 So there might be an empty word before the start of the pool.
7532 Hence we reduce the forward range by 4 to allow for this
7534 if (ARM_DOUBLEWORD_ALIGN && fix->fix_size == 8)
7540 ";; %smode fixup for i%d; addr %lu, range (%ld,%ld): ",
7541 GET_MODE_NAME (mode),
7542 INSN_UID (insn), (unsigned long) address,
7543 -1 * (long)fix->backwards, (long)fix->forwards);
7544 arm_print_value (dump_file, fix->value);
7545 fprintf (dump_file, "\n");
7548 /* Add it to the chain of fixes. */
7551 if (minipool_fix_head != NULL)
7552 minipool_fix_tail->next = fix;
7554 minipool_fix_head = fix;
7556 minipool_fix_tail = fix;
7559 /* Scan INSN and note any of its operands that need fixing.
7560 If DO_PUSHES is false we do not actually push any of the fixups
7561 needed. The function returns TRUE is any fixups were needed/pushed.
7562 This is used by arm_memory_load_p() which needs to know about loads
7563 of constants that will be converted into minipool loads. */
7565 note_invalid_constants (rtx insn, HOST_WIDE_INT address, int do_pushes)
7567 bool result = false;
7570 extract_insn (insn);
7572 if (!constrain_operands (1))
7573 fatal_insn_not_found (insn);
7575 if (recog_data.n_alternatives == 0)
7578 /* Fill in recog_op_alt with information about the constraints of this insn. */
7579 preprocess_constraints ();
7581 for (opno = 0; opno < recog_data.n_operands; opno++)
7583 /* Things we need to fix can only occur in inputs. */
7584 if (recog_data.operand_type[opno] != OP_IN)
7587 /* If this alternative is a memory reference, then any mention
7588 of constants in this alternative is really to fool reload
7589 into allowing us to accept one there. We need to fix them up
7590 now so that we output the right code. */
7591 if (recog_op_alt[opno][which_alternative].memory_ok)
7593 rtx op = recog_data.operand[opno];
7595 if (CONSTANT_P (op))
7598 push_minipool_fix (insn, address, recog_data.operand_loc[opno],
7599 recog_data.operand_mode[opno], op);
7602 else if (GET_CODE (op) == MEM
7603 && GET_CODE (XEXP (op, 0)) == SYMBOL_REF
7604 && CONSTANT_POOL_ADDRESS_P (XEXP (op, 0)))
7608 rtx cop = avoid_constant_pool_reference (op);
7610 /* Casting the address of something to a mode narrower
7611 than a word can cause avoid_constant_pool_reference()
7612 to return the pool reference itself. That's no good to
7613 us here. Lets just hope that we can use the
7614 constant pool value directly. */
7616 cop = get_pool_constant (XEXP (op, 0));
7618 push_minipool_fix (insn, address,
7619 recog_data.operand_loc[opno],
7620 recog_data.operand_mode[opno], cop);
7631 /* Gcc puts the pool in the wrong place for ARM, since we can only
7632 load addresses a limited distance around the pc. We do some
7633 special munging to move the constant pool values to the correct
7634 point in the code. */
7639 HOST_WIDE_INT address = 0;
7642 minipool_fix_head = minipool_fix_tail = NULL;
7644 /* The first insn must always be a note, or the code below won't
7645 scan it properly. */
7646 insn = get_insns ();
7647 if (GET_CODE (insn) != NOTE)
7650 /* Scan all the insns and record the operands that will need fixing. */
7651 for (insn = next_nonnote_insn (insn); insn; insn = next_nonnote_insn (insn))
7653 if (TARGET_CIRRUS_FIX_INVALID_INSNS
7654 && (arm_cirrus_insn_p (insn)
7655 || GET_CODE (insn) == JUMP_INSN
7656 || arm_memory_load_p (insn)))
7657 cirrus_reorg (insn);
7659 if (GET_CODE (insn) == BARRIER)
7660 push_minipool_barrier (insn, address);
7661 else if (INSN_P (insn))
7665 note_invalid_constants (insn, address, true);
7666 address += get_attr_length (insn);
7668 /* If the insn is a vector jump, add the size of the table
7669 and skip the table. */
7670 if ((table = is_jump_table (insn)) != NULL)
7672 address += get_jump_table_size (table);
7678 fix = minipool_fix_head;
7680 /* Now scan the fixups and perform the required changes. */
7685 Mfix * last_added_fix;
7686 Mfix * last_barrier = NULL;
7689 /* Skip any further barriers before the next fix. */
7690 while (fix && GET_CODE (fix->insn) == BARRIER)
7693 /* No more fixes. */
7697 last_added_fix = NULL;
7699 for (ftmp = fix; ftmp; ftmp = ftmp->next)
7701 if (GET_CODE (ftmp->insn) == BARRIER)
7703 if (ftmp->address >= minipool_vector_head->max_address)
7706 last_barrier = ftmp;
7708 else if ((ftmp->minipool = add_minipool_forward_ref (ftmp)) == NULL)
7711 last_added_fix = ftmp; /* Keep track of the last fix added. */
7714 /* If we found a barrier, drop back to that; any fixes that we
7715 could have reached but come after the barrier will now go in
7716 the next mini-pool. */
7717 if (last_barrier != NULL)
7719 /* Reduce the refcount for those fixes that won't go into this
7721 for (fdel = last_barrier->next;
7722 fdel && fdel != ftmp;
7725 fdel->minipool->refcount--;
7726 fdel->minipool = NULL;
7729 ftmp = last_barrier;
7733 /* ftmp is first fix that we can't fit into this pool and
7734 there no natural barriers that we could use. Insert a
7735 new barrier in the code somewhere between the previous
7736 fix and this one, and arrange to jump around it. */
7737 HOST_WIDE_INT max_address;
7739 /* The last item on the list of fixes must be a barrier, so
7740 we can never run off the end of the list of fixes without
7741 last_barrier being set. */
7745 max_address = minipool_vector_head->max_address;
7746 /* Check that there isn't another fix that is in range that
7747 we couldn't fit into this pool because the pool was
7748 already too large: we need to put the pool before such an
7750 if (ftmp->address < max_address)
7751 max_address = ftmp->address;
7753 last_barrier = create_fix_barrier (last_added_fix, max_address);
7756 assign_minipool_offsets (last_barrier);
7760 if (GET_CODE (ftmp->insn) != BARRIER
7761 && ((ftmp->minipool = add_minipool_backward_ref (ftmp))
7768 /* Scan over the fixes we have identified for this pool, fixing them
7769 up and adding the constants to the pool itself. */
7770 for (this_fix = fix; this_fix && ftmp != this_fix;
7771 this_fix = this_fix->next)
7772 if (GET_CODE (this_fix->insn) != BARRIER)
7775 = plus_constant (gen_rtx_LABEL_REF (VOIDmode,
7776 minipool_vector_label),
7777 this_fix->minipool->offset);
7778 *this_fix->loc = gen_rtx_MEM (this_fix->mode, addr);
7781 dump_minipool (last_barrier->insn);
7785 /* From now on we must synthesize any constants that we can't handle
7786 directly. This can happen if the RTL gets split during final
7787 instruction generation. */
7788 after_arm_reorg = 1;
7790 /* Free the minipool memory. */
7791 obstack_free (&minipool_obstack, minipool_startobj);
7794 /* Routines to output assembly language. */
7796 /* If the rtx is the correct value then return the string of the number.
7797 In this way we can ensure that valid double constants are generated even
7798 when cross compiling. */
7800 fp_immediate_constant (rtx x)
7805 if (!fp_consts_inited)
7808 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
7809 for (i = 0; i < 8; i++)
7810 if (REAL_VALUES_EQUAL (r, values_fp[i]))
7811 return strings_fp[i];
7816 /* As for fp_immediate_constant, but value is passed directly, not in rtx. */
7818 fp_const_from_val (REAL_VALUE_TYPE *r)
7822 if (!fp_consts_inited)
7825 for (i = 0; i < 8; i++)
7826 if (REAL_VALUES_EQUAL (*r, values_fp[i]))
7827 return strings_fp[i];
7832 /* Output the operands of a LDM/STM instruction to STREAM.
7833 MASK is the ARM register set mask of which only bits 0-15 are important.
7834 REG is the base register, either the frame pointer or the stack pointer,
7835 INSTR is the possibly suffixed load or store instruction. */
7837 print_multi_reg (FILE *stream, const char *instr, int reg, int mask)
7840 int not_first = FALSE;
7842 fputc ('\t', stream);
7843 asm_fprintf (stream, instr, reg);
7844 fputs (", {", stream);
7846 for (i = 0; i <= LAST_ARM_REGNUM; i++)
7847 if (mask & (1 << i))
7850 fprintf (stream, ", ");
7852 asm_fprintf (stream, "%r", i);
7856 fprintf (stream, "}\n");
7860 /* Output a FLDMX instruction to STREAM.
7861 BASE if the register containing the address.
7862 REG and COUNT specify the register range.
7863 Extra registers may be added to avoid hardware bugs. */
7866 arm_output_fldmx (FILE * stream, unsigned int base, int reg, int count)
7870 /* Workaround ARM10 VFPr1 bug. */
7871 if (count == 2 && !arm_arch6)
7878 fputc ('\t', stream);
7879 asm_fprintf (stream, "fldmfdx\t%r!, {", base);
7881 for (i = reg; i < reg + count; i++)
7884 fputs (", ", stream);
7885 asm_fprintf (stream, "d%d", i);
7887 fputs ("}\n", stream);
7892 /* Output the assembly for a store multiple. */
7895 vfp_output_fstmx (rtx * operands)
7902 strcpy (pattern, "fstmfdx\t%m0!, {%P1");
7903 p = strlen (pattern);
7905 if (GET_CODE (operands[1]) != REG)
7908 base = (REGNO (operands[1]) - FIRST_VFP_REGNUM) / 2;
7909 for (i = 1; i < XVECLEN (operands[2], 0); i++)
7911 p += sprintf (&pattern[p], ", d%d", base + i);
7913 strcpy (&pattern[p], "}");
7915 output_asm_insn (pattern, operands);
7920 /* Emit RTL to save block of VFP register pairs to the stack. Returns the
7921 number of bytes pushed. */
7924 vfp_emit_fstmx (int base_reg, int count)
7931 /* Workaround ARM10 VFPr1 bug. Data corruption can occur when exactly two
7932 register pairs are stored by a store multiple insn. We avoid this
7933 by pushing an extra pair. */
7934 if (count == 2 && !arm_arch6)
7936 if (base_reg == LAST_VFP_REGNUM - 3)
7941 /* ??? The frame layout is implementation defined. We describe
7942 standard format 1 (equivalent to a FSTMD insn and unused pad word).
7943 We really need some way of representing the whole block so that the
7944 unwinder can figure it out at runtime. */
7945 par = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
7946 dwarf = gen_rtx_SEQUENCE (VOIDmode, rtvec_alloc (count + 1));
7948 reg = gen_rtx_REG (DFmode, base_reg);
7952 = gen_rtx_SET (VOIDmode,
7953 gen_rtx_MEM (BLKmode,
7954 gen_rtx_PRE_DEC (BLKmode, stack_pointer_rtx)),
7955 gen_rtx_UNSPEC (BLKmode,
7959 tmp = gen_rtx_SET (VOIDmode, stack_pointer_rtx,
7960 gen_rtx_PLUS (SImode, stack_pointer_rtx,
7961 GEN_INT (-(count * 8 + 4))));
7962 RTX_FRAME_RELATED_P (tmp) = 1;
7963 XVECEXP (dwarf, 0, 0) = tmp;
7965 tmp = gen_rtx_SET (VOIDmode,
7966 gen_rtx_MEM (DFmode, stack_pointer_rtx),
7968 RTX_FRAME_RELATED_P (tmp) = 1;
7969 XVECEXP (dwarf, 0, 1) = tmp;
7971 for (i = 1; i < count; i++)
7973 reg = gen_rtx_REG (DFmode, base_reg);
7975 XVECEXP (par, 0, i) = gen_rtx_USE (VOIDmode, reg);
7977 tmp = gen_rtx_SET (VOIDmode,
7978 gen_rtx_MEM (DFmode,
7979 gen_rtx_PLUS (SImode,
7983 RTX_FRAME_RELATED_P (tmp) = 1;
7984 XVECEXP (dwarf, 0, i + 1) = tmp;
7987 par = emit_insn (par);
7988 REG_NOTES (par) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, dwarf,
7990 RTX_FRAME_RELATED_P (par) = 1;
7992 return count * 8 + 4;
7996 /* Output a 'call' insn. */
7998 output_call (rtx *operands)
8001 abort (); /* Patterns should call blx <reg> directly. */
8003 /* Handle calls to lr using ip (which may be clobbered in subr anyway). */
8004 if (REGNO (operands[0]) == LR_REGNUM)
8006 operands[0] = gen_rtx_REG (SImode, IP_REGNUM);
8007 output_asm_insn ("mov%?\t%0, %|lr", operands);
8010 output_asm_insn ("mov%?\t%|lr, %|pc", operands);
8012 if (TARGET_INTERWORK || arm_arch4t)
8013 output_asm_insn ("bx%?\t%0", operands);
8015 output_asm_insn ("mov%?\t%|pc, %0", operands);
8020 /* Output a 'call' insn that is a reference in memory. */
8022 output_call_mem (rtx *operands)
8024 if (TARGET_INTERWORK && !arm_arch5)
8026 output_asm_insn ("ldr%?\t%|ip, %0", operands);
8027 output_asm_insn ("mov%?\t%|lr, %|pc", operands);
8028 output_asm_insn ("bx%?\t%|ip", operands);
8030 else if (regno_use_in (LR_REGNUM, operands[0]))
8032 /* LR is used in the memory address. We load the address in the
8033 first instruction. It's safe to use IP as the target of the
8034 load since the call will kill it anyway. */
8035 output_asm_insn ("ldr%?\t%|ip, %0", operands);
8037 output_asm_insn ("blx%?%|ip", operands);
8040 output_asm_insn ("mov%?\t%|lr, %|pc", operands);
8042 output_asm_insn ("bx%?\t%|ip", operands);
8044 output_asm_insn ("mov%?\t%|pc, %|ip", operands);
8049 output_asm_insn ("mov%?\t%|lr, %|pc", operands);
8050 output_asm_insn ("ldr%?\t%|pc, %0", operands);
8057 /* Output a move from arm registers to an fpa registers.
8058 OPERANDS[0] is an fpa register.
8059 OPERANDS[1] is the first registers of an arm register pair. */
8061 output_mov_long_double_fpa_from_arm (rtx *operands)
8063 int arm_reg0 = REGNO (operands[1]);
8066 if (arm_reg0 == IP_REGNUM)
8069 ops[0] = gen_rtx_REG (SImode, arm_reg0);
8070 ops[1] = gen_rtx_REG (SImode, 1 + arm_reg0);
8071 ops[2] = gen_rtx_REG (SImode, 2 + arm_reg0);
8073 output_asm_insn ("stm%?fd\t%|sp!, {%0, %1, %2}", ops);
8074 output_asm_insn ("ldf%?e\t%0, [%|sp], #12", operands);
8079 /* Output a move from an fpa register to arm registers.
8080 OPERANDS[0] is the first registers of an arm register pair.
8081 OPERANDS[1] is an fpa register. */
8083 output_mov_long_double_arm_from_fpa (rtx *operands)
8085 int arm_reg0 = REGNO (operands[0]);
8088 if (arm_reg0 == IP_REGNUM)
8091 ops[0] = gen_rtx_REG (SImode, arm_reg0);
8092 ops[1] = gen_rtx_REG (SImode, 1 + arm_reg0);
8093 ops[2] = gen_rtx_REG (SImode, 2 + arm_reg0);
8095 output_asm_insn ("stf%?e\t%1, [%|sp, #-12]!", operands);
8096 output_asm_insn ("ldm%?fd\t%|sp!, {%0, %1, %2}", ops);
8100 /* Output a move from arm registers to arm registers of a long double
8101 OPERANDS[0] is the destination.
8102 OPERANDS[1] is the source. */
8104 output_mov_long_double_arm_from_arm (rtx *operands)
8106 /* We have to be careful here because the two might overlap. */
8107 int dest_start = REGNO (operands[0]);
8108 int src_start = REGNO (operands[1]);
8112 if (dest_start < src_start)
8114 for (i = 0; i < 3; i++)
8116 ops[0] = gen_rtx_REG (SImode, dest_start + i);
8117 ops[1] = gen_rtx_REG (SImode, src_start + i);
8118 output_asm_insn ("mov%?\t%0, %1", ops);
8123 for (i = 2; i >= 0; i--)
8125 ops[0] = gen_rtx_REG (SImode, dest_start + i);
8126 ops[1] = gen_rtx_REG (SImode, src_start + i);
8127 output_asm_insn ("mov%?\t%0, %1", ops);
8135 /* Output a move from arm registers to an fpa registers.
8136 OPERANDS[0] is an fpa register.
8137 OPERANDS[1] is the first registers of an arm register pair. */
8139 output_mov_double_fpa_from_arm (rtx *operands)
8141 int arm_reg0 = REGNO (operands[1]);
8144 if (arm_reg0 == IP_REGNUM)
8147 ops[0] = gen_rtx_REG (SImode, arm_reg0);
8148 ops[1] = gen_rtx_REG (SImode, 1 + arm_reg0);
8149 output_asm_insn ("stm%?fd\t%|sp!, {%0, %1}", ops);
8150 output_asm_insn ("ldf%?d\t%0, [%|sp], #8", operands);
8154 /* Output a move from an fpa register to arm registers.
8155 OPERANDS[0] is the first registers of an arm register pair.
8156 OPERANDS[1] is an fpa register. */
8158 output_mov_double_arm_from_fpa (rtx *operands)
8160 int arm_reg0 = REGNO (operands[0]);
8163 if (arm_reg0 == IP_REGNUM)
8166 ops[0] = gen_rtx_REG (SImode, arm_reg0);
8167 ops[1] = gen_rtx_REG (SImode, 1 + arm_reg0);
8168 output_asm_insn ("stf%?d\t%1, [%|sp, #-8]!", operands);
8169 output_asm_insn ("ldm%?fd\t%|sp!, {%0, %1}", ops);
8173 /* Output a move between double words.
8174 It must be REG<-REG, REG<-CONST_DOUBLE, REG<-CONST_INT, REG<-MEM
8175 or MEM<-REG and all MEMs must be offsettable addresses. */
8177 output_move_double (rtx *operands)
8179 enum rtx_code code0 = GET_CODE (operands[0]);
8180 enum rtx_code code1 = GET_CODE (operands[1]);
8185 int reg0 = REGNO (operands[0]);
8187 otherops[0] = gen_rtx_REG (SImode, 1 + reg0);
8191 int reg1 = REGNO (operands[1]);
8192 if (reg1 == IP_REGNUM)
8195 /* Ensure the second source is not overwritten. */
8196 if (reg1 == reg0 + (WORDS_BIG_ENDIAN ? -1 : 1))
8197 output_asm_insn ("mov%?\t%Q0, %Q1\n\tmov%?\t%R0, %R1", operands);
8199 output_asm_insn ("mov%?\t%R0, %R1\n\tmov%?\t%Q0, %Q1", operands);
8201 else if (code1 == CONST_VECTOR)
8203 HOST_WIDE_INT hint = 0;
8205 switch (GET_MODE (operands[1]))
8208 otherops[1] = GEN_INT (INTVAL (CONST_VECTOR_ELT (operands[1], 1)));
8209 operands[1] = GEN_INT (INTVAL (CONST_VECTOR_ELT (operands[1], 0)));
8213 if (BYTES_BIG_ENDIAN)
8215 hint = INTVAL (CONST_VECTOR_ELT (operands[1], 2));
8217 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 3));
8221 hint = INTVAL (CONST_VECTOR_ELT (operands[1], 3));
8223 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 2));
8226 otherops[1] = GEN_INT (hint);
8229 if (BYTES_BIG_ENDIAN)
8231 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 0));
8233 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 1));
8237 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 1));
8239 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 0));
8242 operands[1] = GEN_INT (hint);
8246 if (BYTES_BIG_ENDIAN)
8248 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 4));
8250 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 5));
8252 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 6));
8254 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 7));
8258 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 7));
8260 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 6));
8262 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 5));
8264 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 4));
8267 otherops[1] = GEN_INT (hint);
8270 if (BYTES_BIG_ENDIAN)
8272 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 0));
8274 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 1));
8276 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 2));
8278 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 3));
8282 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 3));
8284 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 2));
8286 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 1));
8288 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 0));
8291 operands[1] = GEN_INT (hint);
8297 output_mov_immediate (operands);
8298 output_mov_immediate (otherops);
8300 else if (code1 == CONST_DOUBLE)
8302 if (GET_MODE (operands[1]) == DFmode)
8307 REAL_VALUE_FROM_CONST_DOUBLE (r, operands[1]);
8308 REAL_VALUE_TO_TARGET_DOUBLE (r, l);
8309 otherops[1] = GEN_INT (l[1]);
8310 operands[1] = GEN_INT (l[0]);
8312 else if (GET_MODE (operands[1]) != VOIDmode)
8314 else if (WORDS_BIG_ENDIAN)
8316 otherops[1] = GEN_INT (CONST_DOUBLE_LOW (operands[1]));
8317 operands[1] = GEN_INT (CONST_DOUBLE_HIGH (operands[1]));
8321 otherops[1] = GEN_INT (CONST_DOUBLE_HIGH (operands[1]));
8322 operands[1] = GEN_INT (CONST_DOUBLE_LOW (operands[1]));
8325 output_mov_immediate (operands);
8326 output_mov_immediate (otherops);
8328 else if (code1 == CONST_INT)
8330 #if HOST_BITS_PER_WIDE_INT > 32
8331 /* If HOST_WIDE_INT is more than 32 bits, the intval tells us
8332 what the upper word is. */
8333 if (WORDS_BIG_ENDIAN)
8335 otherops[1] = GEN_INT (ARM_SIGN_EXTEND (INTVAL (operands[1])));
8336 operands[1] = GEN_INT (INTVAL (operands[1]) >> 32);
8340 otherops[1] = GEN_INT (INTVAL (operands[1]) >> 32);
8341 operands[1] = GEN_INT (ARM_SIGN_EXTEND (INTVAL (operands[1])));
8344 /* Sign extend the intval into the high-order word. */
8345 if (WORDS_BIG_ENDIAN)
8347 otherops[1] = operands[1];
8348 operands[1] = (INTVAL (operands[1]) < 0
8349 ? constm1_rtx : const0_rtx);
8352 otherops[1] = INTVAL (operands[1]) < 0 ? constm1_rtx : const0_rtx;
8354 output_mov_immediate (otherops);
8355 output_mov_immediate (operands);
8357 else if (code1 == MEM)
8359 switch (GET_CODE (XEXP (operands[1], 0)))
8362 output_asm_insn ("ldm%?ia\t%m1, %M0", operands);
8367 abort (); /* Should never happen now. */
8368 output_asm_insn ("ldr%?d\t%0, [%m1, #8]!", operands);
8372 output_asm_insn ("ldm%?db\t%m1!, %M0", operands);
8376 output_asm_insn ("ldm%?ia\t%m1!, %M0", operands);
8381 abort (); /* Should never happen now. */
8382 output_asm_insn ("ldr%?d\t%0, [%m1], #-8", operands);
8387 otherops[0] = operands[0];
8388 otherops[1] = XEXP (XEXP (XEXP (operands[1], 0), 1), 0);
8389 otherops[2] = XEXP (XEXP (XEXP (operands[1], 0), 1), 1);
8391 if (GET_CODE (XEXP (operands[1], 0)) == PRE_MODIFY)
8393 if (reg_overlap_mentioned_p (otherops[0], otherops[2]))
8395 /* Registers overlap so split out the increment. */
8396 output_asm_insn ("add%?\t%1, %1, %2", otherops);
8397 output_asm_insn ("ldr%?d\t%0, [%1] @split", otherops);
8400 output_asm_insn ("ldr%?d\t%0, [%1, %2]!", otherops);
8404 /* We only allow constant increments, so this is safe. */
8405 output_asm_insn ("ldr%?d\t%0, [%1], %2", otherops);
8411 output_asm_insn ("adr%?\t%0, %1", operands);
8412 output_asm_insn ("ldm%?ia\t%0, %M0", operands);
8416 if (arm_add_operand (XEXP (XEXP (operands[1], 0), 1),
8417 GET_MODE (XEXP (XEXP (operands[1], 0), 1))))
8419 otherops[0] = operands[0];
8420 otherops[1] = XEXP (XEXP (operands[1], 0), 0);
8421 otherops[2] = XEXP (XEXP (operands[1], 0), 1);
8423 if (GET_CODE (XEXP (operands[1], 0)) == PLUS)
8425 if (GET_CODE (otherops[2]) == CONST_INT)
8427 switch ((int) INTVAL (otherops[2]))
8430 output_asm_insn ("ldm%?db\t%1, %M0", otherops);
8433 output_asm_insn ("ldm%?da\t%1, %M0", otherops);
8436 output_asm_insn ("ldm%?ib\t%1, %M0", otherops);
8441 && (GET_CODE (otherops[2]) == REG
8442 || (GET_CODE (otherops[2]) == CONST_INT
8443 && INTVAL (otherops[2]) > -256
8444 && INTVAL (otherops[2]) < 256)))
8446 if (reg_overlap_mentioned_p (otherops[0],
8449 /* Swap base and index registers over to
8450 avoid a conflict. */
8451 otherops[1] = XEXP (XEXP (operands[1], 0), 1);
8452 otherops[2] = XEXP (XEXP (operands[1], 0), 0);
8455 /* If both registers conflict, it will usually
8456 have been fixed by a splitter. */
8457 if (reg_overlap_mentioned_p (otherops[0],
8460 output_asm_insn ("add%?\t%1, %1, %2", otherops);
8461 output_asm_insn ("ldr%?d\t%0, [%1]",
8467 output_asm_insn ("ldr%?d\t%0, [%1, %2]",
8472 if (GET_CODE (otherops[2]) == CONST_INT)
8474 if (!(const_ok_for_arm (INTVAL (otherops[2]))))
8475 output_asm_insn ("sub%?\t%0, %1, #%n2", otherops);
8477 output_asm_insn ("add%?\t%0, %1, %2", otherops);
8480 output_asm_insn ("add%?\t%0, %1, %2", otherops);
8483 output_asm_insn ("sub%?\t%0, %1, %2", otherops);
8485 return "ldm%?ia\t%0, %M0";
8489 otherops[1] = adjust_address (operands[1], SImode, 4);
8490 /* Take care of overlapping base/data reg. */
8491 if (reg_mentioned_p (operands[0], operands[1]))
8493 output_asm_insn ("ldr%?\t%0, %1", otherops);
8494 output_asm_insn ("ldr%?\t%0, %1", operands);
8498 output_asm_insn ("ldr%?\t%0, %1", operands);
8499 output_asm_insn ("ldr%?\t%0, %1", otherops);
8505 abort (); /* Constraints should prevent this. */
8507 else if (code0 == MEM && code1 == REG)
8509 if (REGNO (operands[1]) == IP_REGNUM)
8512 switch (GET_CODE (XEXP (operands[0], 0)))
8515 output_asm_insn ("stm%?ia\t%m0, %M1", operands);
8520 abort (); /* Should never happen now. */
8521 output_asm_insn ("str%?d\t%1, [%m0, #8]!", operands);
8525 output_asm_insn ("stm%?db\t%m0!, %M1", operands);
8529 output_asm_insn ("stm%?ia\t%m0!, %M1", operands);
8534 abort (); /* Should never happen now. */
8535 output_asm_insn ("str%?d\t%1, [%m0], #-8", operands);
8540 otherops[0] = operands[1];
8541 otherops[1] = XEXP (XEXP (XEXP (operands[0], 0), 1), 0);
8542 otherops[2] = XEXP (XEXP (XEXP (operands[0], 0), 1), 1);
8544 if (GET_CODE (XEXP (operands[0], 0)) == PRE_MODIFY)
8545 output_asm_insn ("str%?d\t%0, [%1, %2]!", otherops);
8547 output_asm_insn ("str%?d\t%0, [%1], %2", otherops);
8551 otherops[2] = XEXP (XEXP (operands[0], 0), 1);
8552 if (GET_CODE (otherops[2]) == CONST_INT)
8554 switch ((int) INTVAL (XEXP (XEXP (operands[0], 0), 1)))
8557 output_asm_insn ("stm%?db\t%m0, %M1", operands);
8561 output_asm_insn ("stm%?da\t%m0, %M1", operands);
8565 output_asm_insn ("stm%?ib\t%m0, %M1", operands);
8570 && (GET_CODE (otherops[2]) == REG
8571 || (GET_CODE (otherops[2]) == CONST_INT
8572 && INTVAL (otherops[2]) > -256
8573 && INTVAL (otherops[2]) < 256)))
8575 otherops[0] = operands[1];
8576 otherops[1] = XEXP (XEXP (operands[0], 0), 0);
8577 output_asm_insn ("str%?d\t%0, [%1, %2]", otherops);
8583 otherops[0] = adjust_address (operands[0], SImode, 4);
8584 otherops[1] = gen_rtx_REG (SImode, 1 + REGNO (operands[1]));
8585 output_asm_insn ("str%?\t%1, %0", operands);
8586 output_asm_insn ("str%?\t%1, %0", otherops);
8590 /* Constraints should prevent this. */
8597 /* Output an arbitrary MOV reg, #n.
8598 OPERANDS[0] is a register. OPERANDS[1] is a const_int. */
8600 output_mov_immediate (rtx *operands)
8602 HOST_WIDE_INT n = INTVAL (operands[1]);
8604 /* Try to use one MOV. */
8605 if (const_ok_for_arm (n))
8606 output_asm_insn ("mov%?\t%0, %1", operands);
8608 /* Try to use one MVN. */
8609 else if (const_ok_for_arm (~n))
8611 operands[1] = GEN_INT (~n);
8612 output_asm_insn ("mvn%?\t%0, %1", operands);
8619 /* If all else fails, make it out of ORRs or BICs as appropriate. */
8620 for (i = 0; i < 32; i++)
8624 if (n_ones > 16) /* Shorter to use MVN with BIC in this case. */
8625 output_multi_immediate (operands, "mvn%?\t%0, %1", "bic%?\t%0, %0, %1", 1, ~ n);
8627 output_multi_immediate (operands, "mov%?\t%0, %1", "orr%?\t%0, %0, %1", 1, n);
8633 /* Output an ADD r, s, #n where n may be too big for one instruction.
8634 If adding zero to one register, output nothing. */
8636 output_add_immediate (rtx *operands)
8638 HOST_WIDE_INT n = INTVAL (operands[2]);
8640 if (n != 0 || REGNO (operands[0]) != REGNO (operands[1]))
8643 output_multi_immediate (operands,
8644 "sub%?\t%0, %1, %2", "sub%?\t%0, %0, %2", 2,
8647 output_multi_immediate (operands,
8648 "add%?\t%0, %1, %2", "add%?\t%0, %0, %2", 2,
8655 /* Output a multiple immediate operation.
8656 OPERANDS is the vector of operands referred to in the output patterns.
8657 INSTR1 is the output pattern to use for the first constant.
8658 INSTR2 is the output pattern to use for subsequent constants.
8659 IMMED_OP is the index of the constant slot in OPERANDS.
8660 N is the constant value. */
8662 output_multi_immediate (rtx *operands, const char *instr1, const char *instr2,
8663 int immed_op, HOST_WIDE_INT n)
8665 #if HOST_BITS_PER_WIDE_INT > 32
8671 /* Quick and easy output. */
8672 operands[immed_op] = const0_rtx;
8673 output_asm_insn (instr1, operands);
8678 const char * instr = instr1;
8680 /* Note that n is never zero here (which would give no output). */
8681 for (i = 0; i < 32; i += 2)
8685 operands[immed_op] = GEN_INT (n & (255 << i));
8686 output_asm_insn (instr, operands);
8696 /* Return the appropriate ARM instruction for the operation code.
8697 The returned result should not be overwritten. OP is the rtx of the
8698 operation. SHIFT_FIRST_ARG is TRUE if the first argument of the operator
8701 arithmetic_instr (rtx op, int shift_first_arg)
8703 switch (GET_CODE (op))
8709 return shift_first_arg ? "rsb" : "sub";
8725 /* Ensure valid constant shifts and return the appropriate shift mnemonic
8726 for the operation code. The returned result should not be overwritten.
8727 OP is the rtx code of the shift.
8728 On exit, *AMOUNTP will be -1 if the shift is by a register, or a constant
8731 shift_op (rtx op, HOST_WIDE_INT *amountp)
8734 enum rtx_code code = GET_CODE (op);
8736 if (GET_CODE (XEXP (op, 1)) == REG || GET_CODE (XEXP (op, 1)) == SUBREG)
8738 else if (GET_CODE (XEXP (op, 1)) == CONST_INT)
8739 *amountp = INTVAL (XEXP (op, 1));
8762 /* We never have to worry about the amount being other than a
8763 power of 2, since this case can never be reloaded from a reg. */
8765 *amountp = int_log2 (*amountp);
8776 /* This is not 100% correct, but follows from the desire to merge
8777 multiplication by a power of 2 with the recognizer for a
8778 shift. >=32 is not a valid shift for "asl", so we must try and
8779 output a shift that produces the correct arithmetical result.
8780 Using lsr #32 is identical except for the fact that the carry bit
8781 is not set correctly if we set the flags; but we never use the
8782 carry bit from such an operation, so we can ignore that. */
8783 if (code == ROTATERT)
8784 /* Rotate is just modulo 32. */
8786 else if (*amountp != (*amountp & 31))
8793 /* Shifts of 0 are no-ops. */
8801 /* Obtain the shift from the POWER of two. */
8803 static HOST_WIDE_INT
8804 int_log2 (HOST_WIDE_INT power)
8806 HOST_WIDE_INT shift = 0;
8808 while ((((HOST_WIDE_INT) 1 << shift) & power) == 0)
8818 /* Output a .ascii pseudo-op, keeping track of lengths. This is because
8819 /bin/as is horribly restrictive. */
8820 #define MAX_ASCII_LEN 51
8823 output_ascii_pseudo_op (FILE *stream, const unsigned char *p, int len)
8828 fputs ("\t.ascii\t\"", stream);
8830 for (i = 0; i < len; i++)
8834 if (len_so_far >= MAX_ASCII_LEN)
8836 fputs ("\"\n\t.ascii\t\"", stream);
8843 fputs ("\\t", stream);
8848 fputs ("\\f", stream);
8853 fputs ("\\b", stream);
8858 fputs ("\\r", stream);
8862 case TARGET_NEWLINE:
8863 fputs ("\\n", stream);
8865 if ((c >= ' ' && c <= '~')
8867 /* This is a good place for a line break. */
8868 len_so_far = MAX_ASCII_LEN;
8875 putc ('\\', stream);
8880 if (c >= ' ' && c <= '~')
8887 fprintf (stream, "\\%03o", c);
8894 fputs ("\"\n", stream);
8897 /* Compute the register sabe mask for registers 0 through 12
8898 inclusive. This code is used by arm_compute_save_reg_mask. */
8899 static unsigned long
8900 arm_compute_save_reg0_reg12_mask (void)
8902 unsigned long func_type = arm_current_func_type ();
8903 unsigned int save_reg_mask = 0;
8906 if (IS_INTERRUPT (func_type))
8908 unsigned int max_reg;
8909 /* Interrupt functions must not corrupt any registers,
8910 even call clobbered ones. If this is a leaf function
8911 we can just examine the registers used by the RTL, but
8912 otherwise we have to assume that whatever function is
8913 called might clobber anything, and so we have to save
8914 all the call-clobbered registers as well. */
8915 if (ARM_FUNC_TYPE (func_type) == ARM_FT_FIQ)
8916 /* FIQ handlers have registers r8 - r12 banked, so
8917 we only need to check r0 - r7, Normal ISRs only
8918 bank r14 and r15, so we must check up to r12.
8919 r13 is the stack pointer which is always preserved,
8920 so we do not need to consider it here. */
8925 for (reg = 0; reg <= max_reg; reg++)
8926 if (regs_ever_live[reg]
8927 || (! current_function_is_leaf && call_used_regs [reg]))
8928 save_reg_mask |= (1 << reg);
8932 /* In the normal case we only need to save those registers
8933 which are call saved and which are used by this function. */
8934 for (reg = 0; reg <= 10; reg++)
8935 if (regs_ever_live[reg] && ! call_used_regs [reg])
8936 save_reg_mask |= (1 << reg);
8938 /* Handle the frame pointer as a special case. */
8939 if (! TARGET_APCS_FRAME
8940 && ! frame_pointer_needed
8941 && regs_ever_live[HARD_FRAME_POINTER_REGNUM]
8942 && ! call_used_regs[HARD_FRAME_POINTER_REGNUM])
8943 save_reg_mask |= 1 << HARD_FRAME_POINTER_REGNUM;
8945 /* If we aren't loading the PIC register,
8946 don't stack it even though it may be live. */
8948 && ! TARGET_SINGLE_PIC_BASE
8949 && regs_ever_live[PIC_OFFSET_TABLE_REGNUM])
8950 save_reg_mask |= 1 << PIC_OFFSET_TABLE_REGNUM;
8953 return save_reg_mask;
8956 /* Compute a bit mask of which registers need to be
8957 saved on the stack for the current function. */
8959 static unsigned long
8960 arm_compute_save_reg_mask (void)
8962 unsigned int save_reg_mask = 0;
8963 unsigned long func_type = arm_current_func_type ();
8965 if (IS_NAKED (func_type))
8966 /* This should never really happen. */
8969 /* If we are creating a stack frame, then we must save the frame pointer,
8970 IP (which will hold the old stack pointer), LR and the PC. */
8971 if (frame_pointer_needed)
8973 (1 << ARM_HARD_FRAME_POINTER_REGNUM)
8978 /* Volatile functions do not return, so there
8979 is no need to save any other registers. */
8980 if (IS_VOLATILE (func_type))
8981 return save_reg_mask;
8983 save_reg_mask |= arm_compute_save_reg0_reg12_mask ();
8985 /* Decide if we need to save the link register.
8986 Interrupt routines have their own banked link register,
8987 so they never need to save it.
8988 Otherwise if we do not use the link register we do not need to save
8989 it. If we are pushing other registers onto the stack however, we
8990 can save an instruction in the epilogue by pushing the link register
8991 now and then popping it back into the PC. This incurs extra memory
8992 accesses though, so we only do it when optimizing for size, and only
8993 if we know that we will not need a fancy return sequence. */
8994 if (regs_ever_live [LR_REGNUM]
8997 && ARM_FUNC_TYPE (func_type) == ARM_FT_NORMAL))
8998 save_reg_mask |= 1 << LR_REGNUM;
9000 if (cfun->machine->lr_save_eliminated)
9001 save_reg_mask &= ~ (1 << LR_REGNUM);
9003 if (TARGET_REALLY_IWMMXT
9004 && ((bit_count (save_reg_mask)
9005 + ARM_NUM_INTS (current_function_pretend_args_size)) % 2) != 0)
9009 /* The total number of registers that are going to be pushed
9010 onto the stack is odd. We need to ensure that the stack
9011 is 64-bit aligned before we start to save iWMMXt registers,
9012 and also before we start to create locals. (A local variable
9013 might be a double or long long which we will load/store using
9014 an iWMMXt instruction). Therefore we need to push another
9015 ARM register, so that the stack will be 64-bit aligned. We
9016 try to avoid using the arg registers (r0 -r3) as they might be
9017 used to pass values in a tail call. */
9018 for (reg = 4; reg <= 12; reg++)
9019 if ((save_reg_mask & (1 << reg)) == 0)
9023 save_reg_mask |= (1 << reg);
9026 cfun->machine->sibcall_blocked = 1;
9027 save_reg_mask |= (1 << 3);
9031 return save_reg_mask;
9035 /* Return the number of bytes required to save VFP registers. */
9037 arm_get_vfp_saved_size (void)
9044 /* Space for saved VFP registers. */
9045 if (TARGET_HARD_FLOAT && TARGET_VFP)
9048 for (regno = FIRST_VFP_REGNUM;
9049 regno < LAST_VFP_REGNUM;
9052 if ((!regs_ever_live[regno] || call_used_regs[regno])
9053 && (!regs_ever_live[regno + 1] || call_used_regs[regno + 1]))
9057 /* Workaround ARM10 VFPr1 bug. */
9058 if (count == 2 && !arm_arch6)
9060 saved += count * 8 + 4;
9069 if (count == 2 && !arm_arch6)
9071 saved += count * 8 + 4;
9078 /* Generate a function exit sequence. If REALLY_RETURN is false, then do
9079 everything bar the final return instruction. */
9081 output_return_instruction (rtx operand, int really_return, int reverse)
9083 char conditional[10];
9086 unsigned long live_regs_mask;
9087 unsigned long func_type;
9088 arm_stack_offsets *offsets;
9090 func_type = arm_current_func_type ();
9092 if (IS_NAKED (func_type))
9095 if (IS_VOLATILE (func_type) && TARGET_ABORT_NORETURN)
9097 /* If this function was declared non-returning, and we have
9098 found a tail call, then we have to trust that the called
9099 function won't return. */
9104 /* Otherwise, trap an attempted return by aborting. */
9106 ops[1] = gen_rtx_SYMBOL_REF (Pmode, NEED_PLT_RELOC ? "abort(PLT)"
9108 assemble_external_libcall (ops[1]);
9109 output_asm_insn (reverse ? "bl%D0\t%a1" : "bl%d0\t%a1", ops);
9115 if (current_function_calls_alloca && !really_return)
9118 sprintf (conditional, "%%?%%%c0", reverse ? 'D' : 'd');
9120 return_used_this_function = 1;
9122 live_regs_mask = arm_compute_save_reg_mask ();
9126 const char * return_reg;
9128 /* If we do not have any special requirements for function exit
9129 (eg interworking, or ISR) then we can load the return address
9130 directly into the PC. Otherwise we must load it into LR. */
9132 && ! TARGET_INTERWORK)
9133 return_reg = reg_names[PC_REGNUM];
9135 return_reg = reg_names[LR_REGNUM];
9137 if ((live_regs_mask & (1 << IP_REGNUM)) == (1 << IP_REGNUM))
9139 /* There are three possible reasons for the IP register
9140 being saved. 1) a stack frame was created, in which case
9141 IP contains the old stack pointer, or 2) an ISR routine
9142 corrupted it, or 3) it was saved to align the stack on
9143 iWMMXt. In case 1, restore IP into SP, otherwise just
9145 if (frame_pointer_needed)
9147 live_regs_mask &= ~ (1 << IP_REGNUM);
9148 live_regs_mask |= (1 << SP_REGNUM);
9152 if (! IS_INTERRUPT (func_type)
9153 && ! TARGET_REALLY_IWMMXT)
9158 /* On some ARM architectures it is faster to use LDR rather than
9159 LDM to load a single register. On other architectures, the
9160 cost is the same. In 26 bit mode, or for exception handlers,
9161 we have to use LDM to load the PC so that the CPSR is also
9163 for (reg = 0; reg <= LAST_ARM_REGNUM; reg++)
9165 if (live_regs_mask == (unsigned int)(1 << reg))
9168 if (reg <= LAST_ARM_REGNUM
9169 && (reg != LR_REGNUM
9171 || ! IS_INTERRUPT (func_type)))
9173 sprintf (instr, "ldr%s\t%%|%s, [%%|sp], #4", conditional,
9174 (reg == LR_REGNUM) ? return_reg : reg_names[reg]);
9181 /* Generate the load multiple instruction to restore the
9182 registers. Note we can get here, even if
9183 frame_pointer_needed is true, but only if sp already
9184 points to the base of the saved core registers. */
9185 if (live_regs_mask & (1 << SP_REGNUM))
9187 unsigned HOST_WIDE_INT stack_adjust;
9189 offsets = arm_get_frame_offsets ();
9190 stack_adjust = offsets->outgoing_args - offsets->saved_regs;
9191 if (stack_adjust != 0 && stack_adjust != 4)
9194 if (stack_adjust && arm_arch5)
9195 sprintf (instr, "ldm%sib\t%%|sp, {", conditional);
9198 /* If we can't use ldmib (SA110 bug), then try to pop r3
9201 live_regs_mask |= 1 << 3;
9202 sprintf (instr, "ldm%sfd\t%%|sp, {", conditional);
9206 sprintf (instr, "ldm%sfd\t%%|sp!, {", conditional);
9208 p = instr + strlen (instr);
9210 for (reg = 0; reg <= SP_REGNUM; reg++)
9211 if (live_regs_mask & (1 << reg))
9213 int l = strlen (reg_names[reg]);
9219 memcpy (p, ", ", 2);
9223 memcpy (p, "%|", 2);
9224 memcpy (p + 2, reg_names[reg], l);
9228 if (live_regs_mask & (1 << LR_REGNUM))
9230 sprintf (p, "%s%%|%s}", first ? "" : ", ", return_reg);
9231 /* If returning from an interrupt, restore the CPSR. */
9232 if (IS_INTERRUPT (func_type))
9239 output_asm_insn (instr, & operand);
9241 /* See if we need to generate an extra instruction to
9242 perform the actual function return. */
9244 && func_type != ARM_FT_INTERWORKED
9245 && (live_regs_mask & (1 << LR_REGNUM)) != 0)
9247 /* The return has already been handled
9248 by loading the LR into the PC. */
9255 switch ((int) ARM_FUNC_TYPE (func_type))
9259 sprintf (instr, "sub%ss\t%%|pc, %%|lr, #4", conditional);
9262 case ARM_FT_INTERWORKED:
9263 sprintf (instr, "bx%s\t%%|lr", conditional);
9266 case ARM_FT_EXCEPTION:
9267 sprintf (instr, "mov%ss\t%%|pc, %%|lr", conditional);
9271 /* Use bx if it's available. */
9272 if (arm_arch5 || arm_arch4t)
9273 sprintf (instr, "bx%s\t%%|lr", conditional);
9275 sprintf (instr, "mov%s\t%%|pc, %%|lr", conditional);
9279 output_asm_insn (instr, & operand);
9285 /* Write the function name into the code section, directly preceding
9286 the function prologue.
9288 Code will be output similar to this:
9290 .ascii "arm_poke_function_name", 0
9293 .word 0xff000000 + (t1 - t0)
9294 arm_poke_function_name
9296 stmfd sp!, {fp, ip, lr, pc}
9299 When performing a stack backtrace, code can inspect the value
9300 of 'pc' stored at 'fp' + 0. If the trace function then looks
9301 at location pc - 12 and the top 8 bits are set, then we know
9302 that there is a function name embedded immediately preceding this
9303 location and has length ((pc[-3]) & 0xff000000).
9305 We assume that pc is declared as a pointer to an unsigned long.
9307 It is of no benefit to output the function name if we are assembling
9308 a leaf function. These function types will not contain a stack
9309 backtrace structure, therefore it is not possible to determine the
9312 arm_poke_function_name (FILE *stream, const char *name)
9314 unsigned long alignlength;
9315 unsigned long length;
9318 length = strlen (name) + 1;
9319 alignlength = ROUND_UP_WORD (length);
9321 ASM_OUTPUT_ASCII (stream, name, length);
9322 ASM_OUTPUT_ALIGN (stream, 2);
9323 x = GEN_INT ((unsigned HOST_WIDE_INT) 0xff000000 + alignlength);
9324 assemble_aligned_integer (UNITS_PER_WORD, x);
9327 /* Place some comments into the assembler stream
9328 describing the current function. */
9330 arm_output_function_prologue (FILE *f, HOST_WIDE_INT frame_size)
9332 unsigned long func_type;
9336 thumb_output_function_prologue (f, frame_size);
9341 if (arm_ccfsm_state || arm_target_insn)
9344 func_type = arm_current_func_type ();
9346 switch ((int) ARM_FUNC_TYPE (func_type))
9351 case ARM_FT_INTERWORKED:
9352 asm_fprintf (f, "\t%@ Function supports interworking.\n");
9354 case ARM_FT_EXCEPTION_HANDLER:
9355 asm_fprintf (f, "\t%@ C++ Exception Handler.\n");
9358 asm_fprintf (f, "\t%@ Interrupt Service Routine.\n");
9361 asm_fprintf (f, "\t%@ Fast Interrupt Service Routine.\n");
9363 case ARM_FT_EXCEPTION:
9364 asm_fprintf (f, "\t%@ ARM Exception Handler.\n");
9368 if (IS_NAKED (func_type))
9369 asm_fprintf (f, "\t%@ Naked Function: prologue and epilogue provided by programmer.\n");
9371 if (IS_VOLATILE (func_type))
9372 asm_fprintf (f, "\t%@ Volatile: function does not return.\n");
9374 if (IS_NESTED (func_type))
9375 asm_fprintf (f, "\t%@ Nested: function declared inside another function.\n");
9377 asm_fprintf (f, "\t%@ args = %d, pretend = %d, frame = %wd\n",
9378 current_function_args_size,
9379 current_function_pretend_args_size, frame_size);
9381 asm_fprintf (f, "\t%@ frame_needed = %d, uses_anonymous_args = %d\n",
9382 frame_pointer_needed,
9383 cfun->machine->uses_anonymous_args);
9385 if (cfun->machine->lr_save_eliminated)
9386 asm_fprintf (f, "\t%@ link register save eliminated.\n");
9388 #ifdef AOF_ASSEMBLER
9390 asm_fprintf (f, "\tmov\t%r, %r\n", IP_REGNUM, PIC_OFFSET_TABLE_REGNUM);
9393 return_used_this_function = 0;
9397 arm_output_epilogue (rtx sibling)
9400 unsigned long saved_regs_mask;
9401 unsigned long func_type;
9402 /* Floats_offset is the offset from the "virtual" frame. In an APCS
9403 frame that is $fp + 4 for a non-variadic function. */
9404 int floats_offset = 0;
9406 FILE * f = asm_out_file;
9407 rtx eh_ofs = cfun->machine->eh_epilogue_sp_ofs;
9408 unsigned int lrm_count = 0;
9409 int really_return = (sibling == NULL);
9411 arm_stack_offsets *offsets;
9413 /* If we have already generated the return instruction
9414 then it is futile to generate anything else. */
9415 if (use_return_insn (FALSE, sibling) && return_used_this_function)
9418 func_type = arm_current_func_type ();
9420 if (IS_NAKED (func_type))
9421 /* Naked functions don't have epilogues. */
9424 if (IS_VOLATILE (func_type) && TARGET_ABORT_NORETURN)
9428 /* A volatile function should never return. Call abort. */
9429 op = gen_rtx_SYMBOL_REF (Pmode, NEED_PLT_RELOC ? "abort(PLT)" : "abort");
9430 assemble_external_libcall (op);
9431 output_asm_insn ("bl\t%a0", &op);
9436 if (ARM_FUNC_TYPE (func_type) == ARM_FT_EXCEPTION_HANDLER
9438 /* If we are throwing an exception, then we really must
9439 be doing a return, so we can't tail-call. */
9442 offsets = arm_get_frame_offsets ();
9443 saved_regs_mask = arm_compute_save_reg_mask ();
9446 lrm_count = bit_count (saved_regs_mask);
9448 floats_offset = offsets->saved_args;
9449 /* Compute how far away the floats will be. */
9450 for (reg = 0; reg <= LAST_ARM_REGNUM; reg++)
9451 if (saved_regs_mask & (1 << reg))
9454 if (frame_pointer_needed)
9456 /* This variable is for the Virtual Frame Pointer, not VFP regs. */
9457 int vfp_offset = offsets->frame;
9459 if (arm_fpu_arch == FPUTYPE_FPA_EMU2)
9461 for (reg = LAST_FPA_REGNUM; reg >= FIRST_FPA_REGNUM; reg--)
9462 if (regs_ever_live[reg] && !call_used_regs[reg])
9464 floats_offset += 12;
9465 asm_fprintf (f, "\tldfe\t%r, [%r, #-%d]\n",
9466 reg, FP_REGNUM, floats_offset - vfp_offset);
9471 start_reg = LAST_FPA_REGNUM;
9473 for (reg = LAST_FPA_REGNUM; reg >= FIRST_FPA_REGNUM; reg--)
9475 if (regs_ever_live[reg] && !call_used_regs[reg])
9477 floats_offset += 12;
9479 /* We can't unstack more than four registers at once. */
9480 if (start_reg - reg == 3)
9482 asm_fprintf (f, "\tlfm\t%r, 4, [%r, #-%d]\n",
9483 reg, FP_REGNUM, floats_offset - vfp_offset);
9484 start_reg = reg - 1;
9489 if (reg != start_reg)
9490 asm_fprintf (f, "\tlfm\t%r, %d, [%r, #-%d]\n",
9491 reg + 1, start_reg - reg,
9492 FP_REGNUM, floats_offset - vfp_offset);
9493 start_reg = reg - 1;
9497 /* Just in case the last register checked also needs unstacking. */
9498 if (reg != start_reg)
9499 asm_fprintf (f, "\tlfm\t%r, %d, [%r, #-%d]\n",
9500 reg + 1, start_reg - reg,
9501 FP_REGNUM, floats_offset - vfp_offset);
9504 if (TARGET_HARD_FLOAT && TARGET_VFP)
9508 /* The fldmx insn does not have base+offset addressing modes,
9509 so we use IP to hold the address. */
9510 saved_size = arm_get_vfp_saved_size ();
9514 floats_offset += saved_size;
9515 asm_fprintf (f, "\tsub\t%r, %r, #%d\n", IP_REGNUM,
9516 FP_REGNUM, floats_offset - vfp_offset);
9518 start_reg = FIRST_VFP_REGNUM;
9519 for (reg = FIRST_VFP_REGNUM; reg < LAST_VFP_REGNUM; reg += 2)
9521 if ((!regs_ever_live[reg] || call_used_regs[reg])
9522 && (!regs_ever_live[reg + 1] || call_used_regs[reg + 1]))
9524 if (start_reg != reg)
9525 arm_output_fldmx (f, IP_REGNUM,
9526 (start_reg - FIRST_VFP_REGNUM) / 2,
9527 (reg - start_reg) / 2);
9528 start_reg = reg + 2;
9531 if (start_reg != reg)
9532 arm_output_fldmx (f, IP_REGNUM,
9533 (start_reg - FIRST_VFP_REGNUM) / 2,
9534 (reg - start_reg) / 2);
9539 /* The frame pointer is guaranteed to be non-double-word aligned.
9540 This is because it is set to (old_stack_pointer - 4) and the
9541 old_stack_pointer was double word aligned. Thus the offset to
9542 the iWMMXt registers to be loaded must also be non-double-word
9543 sized, so that the resultant address *is* double-word aligned.
9544 We can ignore floats_offset since that was already included in
9545 the live_regs_mask. */
9546 lrm_count += (lrm_count % 2 ? 2 : 1);
9548 for (reg = LAST_IWMMXT_REGNUM; reg >= FIRST_IWMMXT_REGNUM; reg--)
9549 if (regs_ever_live[reg] && !call_used_regs[reg])
9551 asm_fprintf (f, "\twldrd\t%r, [%r, #-%d]\n",
9552 reg, FP_REGNUM, lrm_count * 4);
9557 /* saved_regs_mask should contain the IP, which at the time of stack
9558 frame generation actually contains the old stack pointer. So a
9559 quick way to unwind the stack is just pop the IP register directly
9560 into the stack pointer. */
9561 if ((saved_regs_mask & (1 << IP_REGNUM)) == 0)
9563 saved_regs_mask &= ~ (1 << IP_REGNUM);
9564 saved_regs_mask |= (1 << SP_REGNUM);
9566 /* There are two registers left in saved_regs_mask - LR and PC. We
9567 only need to restore the LR register (the return address), but to
9568 save time we can load it directly into the PC, unless we need a
9569 special function exit sequence, or we are not really returning. */
9570 if (really_return && ARM_FUNC_TYPE (func_type) == ARM_FT_NORMAL)
9571 /* Delete the LR from the register mask, so that the LR on
9572 the stack is loaded into the PC in the register mask. */
9573 saved_regs_mask &= ~ (1 << LR_REGNUM);
9575 saved_regs_mask &= ~ (1 << PC_REGNUM);
9577 /* We must use SP as the base register, because SP is one of the
9578 registers being restored. If an interrupt or page fault
9579 happens in the ldm instruction, the SP might or might not
9580 have been restored. That would be bad, as then SP will no
9581 longer indicate the safe area of stack, and we can get stack
9582 corruption. Using SP as the base register means that it will
9583 be reset correctly to the original value, should an interrupt
9584 occur. If the stack pointer already points at the right
9585 place, then omit the subtraction. */
9586 if (offsets->outgoing_args != (1 + (int) bit_count (saved_regs_mask))
9587 || current_function_calls_alloca)
9588 asm_fprintf (f, "\tsub\t%r, %r, #%d\n", SP_REGNUM, FP_REGNUM,
9589 4 * bit_count (saved_regs_mask));
9590 print_multi_reg (f, "ldmfd\t%r", SP_REGNUM, saved_regs_mask);
9592 if (IS_INTERRUPT (func_type))
9593 /* Interrupt handlers will have pushed the
9594 IP onto the stack, so restore it now. */
9595 print_multi_reg (f, "ldmfd\t%r!", SP_REGNUM, 1 << IP_REGNUM);
9599 /* Restore stack pointer if necessary. */
9600 if (offsets->outgoing_args != offsets->saved_regs)
9602 operands[0] = operands[1] = stack_pointer_rtx;
9603 operands[2] = GEN_INT (offsets->outgoing_args - offsets->saved_regs);
9604 output_add_immediate (operands);
9607 if (arm_fpu_arch == FPUTYPE_FPA_EMU2)
9609 for (reg = FIRST_FPA_REGNUM; reg <= LAST_FPA_REGNUM; reg++)
9610 if (regs_ever_live[reg] && !call_used_regs[reg])
9611 asm_fprintf (f, "\tldfe\t%r, [%r], #12\n",
9616 start_reg = FIRST_FPA_REGNUM;
9618 for (reg = FIRST_FPA_REGNUM; reg <= LAST_FPA_REGNUM; reg++)
9620 if (regs_ever_live[reg] && !call_used_regs[reg])
9622 if (reg - start_reg == 3)
9624 asm_fprintf (f, "\tlfmfd\t%r, 4, [%r]!\n",
9625 start_reg, SP_REGNUM);
9626 start_reg = reg + 1;
9631 if (reg != start_reg)
9632 asm_fprintf (f, "\tlfmfd\t%r, %d, [%r]!\n",
9633 start_reg, reg - start_reg,
9636 start_reg = reg + 1;
9640 /* Just in case the last register checked also needs unstacking. */
9641 if (reg != start_reg)
9642 asm_fprintf (f, "\tlfmfd\t%r, %d, [%r]!\n",
9643 start_reg, reg - start_reg, SP_REGNUM);
9646 if (TARGET_HARD_FLOAT && TARGET_VFP)
9648 start_reg = FIRST_VFP_REGNUM;
9649 for (reg = FIRST_VFP_REGNUM; reg < LAST_VFP_REGNUM; reg += 2)
9651 if ((!regs_ever_live[reg] || call_used_regs[reg])
9652 && (!regs_ever_live[reg + 1] || call_used_regs[reg + 1]))
9654 if (start_reg != reg)
9655 arm_output_fldmx (f, SP_REGNUM,
9656 (start_reg - FIRST_VFP_REGNUM) / 2,
9657 (reg - start_reg) / 2);
9658 start_reg = reg + 2;
9661 if (start_reg != reg)
9662 arm_output_fldmx (f, SP_REGNUM,
9663 (start_reg - FIRST_VFP_REGNUM) / 2,
9664 (reg - start_reg) / 2);
9667 for (reg = FIRST_IWMMXT_REGNUM; reg <= LAST_IWMMXT_REGNUM; reg++)
9668 if (regs_ever_live[reg] && !call_used_regs[reg])
9669 asm_fprintf (f, "\twldrd\t%r, [%r], #8\n", reg, SP_REGNUM);
9671 /* If we can, restore the LR into the PC. */
9672 if (ARM_FUNC_TYPE (func_type) == ARM_FT_NORMAL
9674 && current_function_pretend_args_size == 0
9675 && saved_regs_mask & (1 << LR_REGNUM))
9677 saved_regs_mask &= ~ (1 << LR_REGNUM);
9678 saved_regs_mask |= (1 << PC_REGNUM);
9681 /* Load the registers off the stack. If we only have one register
9682 to load use the LDR instruction - it is faster. */
9683 if (saved_regs_mask == (1 << LR_REGNUM))
9685 /* The exception handler ignores the LR, so we do
9686 not really need to load it off the stack. */
9688 asm_fprintf (f, "\tadd\t%r, %r, #4\n", SP_REGNUM, SP_REGNUM);
9690 asm_fprintf (f, "\tldr\t%r, [%r], #4\n", LR_REGNUM, SP_REGNUM);
9692 else if (saved_regs_mask)
9694 if (saved_regs_mask & (1 << SP_REGNUM))
9695 /* Note - write back to the stack register is not enabled
9696 (ie "ldmfd sp!..."). We know that the stack pointer is
9697 in the list of registers and if we add writeback the
9698 instruction becomes UNPREDICTABLE. */
9699 print_multi_reg (f, "ldmfd\t%r", SP_REGNUM, saved_regs_mask);
9701 print_multi_reg (f, "ldmfd\t%r!", SP_REGNUM, saved_regs_mask);
9704 if (current_function_pretend_args_size)
9706 /* Unwind the pre-pushed regs. */
9707 operands[0] = operands[1] = stack_pointer_rtx;
9708 operands[2] = GEN_INT (current_function_pretend_args_size);
9709 output_add_immediate (operands);
9713 /* We may have already restored PC directly from the stack. */
9714 if (!really_return || saved_regs_mask & (1 << PC_REGNUM))
9717 /* Generate the return instruction. */
9718 switch ((int) ARM_FUNC_TYPE (func_type))
9720 case ARM_FT_EXCEPTION_HANDLER:
9721 asm_fprintf (f, "\tmov\t%r, %r\n", PC_REGNUM, EXCEPTION_LR_REGNUM);
9726 asm_fprintf (f, "\tsubs\t%r, %r, #4\n", PC_REGNUM, LR_REGNUM);
9729 case ARM_FT_EXCEPTION:
9730 asm_fprintf (f, "\tmovs\t%r, %r\n", PC_REGNUM, LR_REGNUM);
9733 case ARM_FT_INTERWORKED:
9734 asm_fprintf (f, "\tbx\t%r\n", LR_REGNUM);
9738 if (arm_arch5 || arm_arch4t)
9739 asm_fprintf (f, "\tbx\t%r\n", LR_REGNUM);
9741 asm_fprintf (f, "\tmov\t%r, %r\n", PC_REGNUM, LR_REGNUM);
9749 arm_output_function_epilogue (FILE *file ATTRIBUTE_UNUSED,
9750 HOST_WIDE_INT frame_size ATTRIBUTE_UNUSED)
9752 arm_stack_offsets *offsets;
9756 /* ??? Probably not safe to set this here, since it assumes that a
9757 function will be emitted as assembly immediately after we generate
9758 RTL for it. This does not happen for inline functions. */
9759 return_used_this_function = 0;
9763 /* We need to take into account any stack-frame rounding. */
9764 offsets = arm_get_frame_offsets ();
9766 if (use_return_insn (FALSE, NULL)
9767 && return_used_this_function
9768 && offsets->saved_regs != offsets->outgoing_args
9769 && !frame_pointer_needed)
9772 /* Reset the ARM-specific per-function variables. */
9773 after_arm_reorg = 0;
9777 /* Generate and emit an insn that we will recognize as a push_multi.
9778 Unfortunately, since this insn does not reflect very well the actual
9779 semantics of the operation, we need to annotate the insn for the benefit
9780 of DWARF2 frame unwind information. */
9782 emit_multi_reg_push (int mask)
9789 int dwarf_par_index;
9792 for (i = 0; i <= LAST_ARM_REGNUM; i++)
9793 if (mask & (1 << i))
9796 if (num_regs == 0 || num_regs > 16)
9799 /* We don't record the PC in the dwarf frame information. */
9800 num_dwarf_regs = num_regs;
9801 if (mask & (1 << PC_REGNUM))
9804 /* For the body of the insn we are going to generate an UNSPEC in
9805 parallel with several USEs. This allows the insn to be recognized
9806 by the push_multi pattern in the arm.md file. The insn looks
9807 something like this:
9810 (set (mem:BLK (pre_dec:BLK (reg:SI sp)))
9811 (unspec:BLK [(reg:SI r4)] UNSPEC_PUSH_MULT))
9812 (use (reg:SI 11 fp))
9813 (use (reg:SI 12 ip))
9814 (use (reg:SI 14 lr))
9815 (use (reg:SI 15 pc))
9818 For the frame note however, we try to be more explicit and actually
9819 show each register being stored into the stack frame, plus a (single)
9820 decrement of the stack pointer. We do it this way in order to be
9821 friendly to the stack unwinding code, which only wants to see a single
9822 stack decrement per instruction. The RTL we generate for the note looks
9823 something like this:
9826 (set (reg:SI sp) (plus:SI (reg:SI sp) (const_int -20)))
9827 (set (mem:SI (reg:SI sp)) (reg:SI r4))
9828 (set (mem:SI (plus:SI (reg:SI sp) (const_int 4))) (reg:SI fp))
9829 (set (mem:SI (plus:SI (reg:SI sp) (const_int 8))) (reg:SI ip))
9830 (set (mem:SI (plus:SI (reg:SI sp) (const_int 12))) (reg:SI lr))
9833 This sequence is used both by the code to support stack unwinding for
9834 exceptions handlers and the code to generate dwarf2 frame debugging. */
9836 par = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (num_regs));
9837 dwarf = gen_rtx_SEQUENCE (VOIDmode, rtvec_alloc (num_dwarf_regs + 1));
9838 dwarf_par_index = 1;
9840 for (i = 0; i <= LAST_ARM_REGNUM; i++)
9842 if (mask & (1 << i))
9844 reg = gen_rtx_REG (SImode, i);
9847 = gen_rtx_SET (VOIDmode,
9848 gen_rtx_MEM (BLKmode,
9849 gen_rtx_PRE_DEC (BLKmode,
9850 stack_pointer_rtx)),
9851 gen_rtx_UNSPEC (BLKmode,
9857 tmp = gen_rtx_SET (VOIDmode,
9858 gen_rtx_MEM (SImode, stack_pointer_rtx),
9860 RTX_FRAME_RELATED_P (tmp) = 1;
9861 XVECEXP (dwarf, 0, dwarf_par_index) = tmp;
9869 for (j = 1, i++; j < num_regs; i++)
9871 if (mask & (1 << i))
9873 reg = gen_rtx_REG (SImode, i);
9875 XVECEXP (par, 0, j) = gen_rtx_USE (VOIDmode, reg);
9879 tmp = gen_rtx_SET (VOIDmode,
9880 gen_rtx_MEM (SImode,
9881 plus_constant (stack_pointer_rtx,
9884 RTX_FRAME_RELATED_P (tmp) = 1;
9885 XVECEXP (dwarf, 0, dwarf_par_index++) = tmp;
9892 par = emit_insn (par);
9894 tmp = gen_rtx_SET (SImode,
9896 gen_rtx_PLUS (SImode,
9898 GEN_INT (-4 * num_regs)));
9899 RTX_FRAME_RELATED_P (tmp) = 1;
9900 XVECEXP (dwarf, 0, 0) = tmp;
9902 REG_NOTES (par) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, dwarf,
9908 emit_sfm (int base_reg, int count)
9915 par = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
9916 dwarf = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
9918 reg = gen_rtx_REG (XFmode, base_reg++);
9921 = gen_rtx_SET (VOIDmode,
9922 gen_rtx_MEM (BLKmode,
9923 gen_rtx_PRE_DEC (BLKmode, stack_pointer_rtx)),
9924 gen_rtx_UNSPEC (BLKmode,
9928 = gen_rtx_SET (VOIDmode,
9929 gen_rtx_MEM (XFmode,
9930 gen_rtx_PRE_DEC (BLKmode, stack_pointer_rtx)),
9932 RTX_FRAME_RELATED_P (tmp) = 1;
9933 XVECEXP (dwarf, 0, count - 1) = tmp;
9935 for (i = 1; i < count; i++)
9937 reg = gen_rtx_REG (XFmode, base_reg++);
9938 XVECEXP (par, 0, i) = gen_rtx_USE (VOIDmode, reg);
9940 tmp = gen_rtx_SET (VOIDmode,
9941 gen_rtx_MEM (XFmode,
9942 gen_rtx_PRE_DEC (BLKmode,
9943 stack_pointer_rtx)),
9945 RTX_FRAME_RELATED_P (tmp) = 1;
9946 XVECEXP (dwarf, 0, count - i - 1) = tmp;
9949 par = emit_insn (par);
9950 REG_NOTES (par) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, dwarf,
9956 /* Return true if the current function needs to save/restore LR. */
9959 thumb_force_lr_save (void)
9961 return !cfun->machine->lr_save_eliminated
9962 && (!leaf_function_p ()
9963 || thumb_far_jump_used_p ()
9964 || regs_ever_live [LR_REGNUM]);
9968 /* Compute the distance from register FROM to register TO.
9969 These can be the arg pointer (26), the soft frame pointer (25),
9970 the stack pointer (13) or the hard frame pointer (11).
9971 Typical stack layout looks like this:
9973 old stack pointer -> | |
9976 | | saved arguments for
9977 | | vararg functions
9980 hard FP & arg pointer -> | | \
9988 soft frame pointer -> | | /
9998 current stack pointer -> | | /
10001 For a given function some or all of these stack components
10002 may not be needed, giving rise to the possibility of
10003 eliminating some of the registers.
10005 The values returned by this function must reflect the behavior
10006 of arm_expand_prologue() and arm_compute_save_reg_mask().
10008 The sign of the number returned reflects the direction of stack
10009 growth, so the values are positive for all eliminations except
10010 from the soft frame pointer to the hard frame pointer.
10012 SFP may point just inside the local variables block to ensure correct
10016 /* Calculate stack offsets. These are used to calculate register elimination
10017 offsets and in prologue/epilogue code. */
10019 static arm_stack_offsets *
10020 arm_get_frame_offsets (void)
10022 struct arm_stack_offsets *offsets;
10023 unsigned long func_type;
10026 HOST_WIDE_INT frame_size;
10028 offsets = &cfun->machine->stack_offsets;
10030 /* We need to know if we are a leaf function. Unfortunately, it
10031 is possible to be called after start_sequence has been called,
10032 which causes get_insns to return the insns for the sequence,
10033 not the function, which will cause leaf_function_p to return
10034 the incorrect result.
10036 to know about leaf functions once reload has completed, and the
10037 frame size cannot be changed after that time, so we can safely
10038 use the cached value. */
10040 if (reload_completed)
10043 /* Initially this is the size of the local variables. It will translated
10044 into an offset once we have determined the size of preceding data. */
10045 frame_size = ROUND_UP_WORD (get_frame_size ());
10047 leaf = leaf_function_p ();
10049 /* Space for variadic functions. */
10050 offsets->saved_args = current_function_pretend_args_size;
10052 offsets->frame = offsets->saved_args + (frame_pointer_needed ? 4 : 0);
10056 unsigned int regno;
10058 saved = bit_count (arm_compute_save_reg_mask ()) * 4;
10060 /* We know that SP will be doubleword aligned on entry, and we must
10061 preserve that condition at any subroutine call. We also require the
10062 soft frame pointer to be doubleword aligned. */
10064 if (TARGET_REALLY_IWMMXT)
10066 /* Check for the call-saved iWMMXt registers. */
10067 for (regno = FIRST_IWMMXT_REGNUM;
10068 regno <= LAST_IWMMXT_REGNUM;
10070 if (regs_ever_live [regno] && ! call_used_regs [regno])
10074 func_type = arm_current_func_type ();
10075 if (! IS_VOLATILE (func_type))
10077 /* Space for saved FPA registers. */
10078 for (regno = FIRST_FPA_REGNUM; regno <= LAST_FPA_REGNUM; regno++)
10079 if (regs_ever_live[regno] && ! call_used_regs[regno])
10082 /* Space for saved VFP registers. */
10083 if (TARGET_HARD_FLOAT && TARGET_VFP)
10084 saved += arm_get_vfp_saved_size ();
10087 else /* TARGET_THUMB */
10094 for (reg = 8; reg < 13; reg ++)
10095 if (THUMB_REG_PUSHED_P (reg))
10098 saved += 4 * count_regs;
10100 for (reg = 0; reg <= LAST_LO_REGNUM; reg ++)
10101 if (THUMB_REG_PUSHED_P (reg))
10103 if (count_regs || thumb_force_lr_save ())
10104 saved += 4 * (count_regs + 1);
10105 if (TARGET_BACKTRACE)
10107 if ((count_regs & 0xFF) == 0 && (regs_ever_live[3] != 0))
10114 /* Saved registers include the stack frame. */
10115 offsets->saved_regs = offsets->saved_args + saved;
10116 offsets->soft_frame = offsets->saved_regs;
10117 /* A leaf function does not need any stack alignment if it has nothing
10119 if (leaf && frame_size == 0)
10121 offsets->outgoing_args = offsets->soft_frame;
10125 /* Ensure SFP has the correct alignment. */
10126 if (ARM_DOUBLEWORD_ALIGN
10127 && (offsets->soft_frame & 7))
10128 offsets->soft_frame += 4;
10130 offsets->outgoing_args = offsets->soft_frame + frame_size
10131 + current_function_outgoing_args_size;
10133 if (ARM_DOUBLEWORD_ALIGN)
10135 /* Ensure SP remains doubleword aligned. */
10136 if (offsets->outgoing_args & 7)
10137 offsets->outgoing_args += 4;
10138 if (offsets->outgoing_args & 7)
10146 /* Calculate the relative offsets for the different stack pointers. Positive
10147 offsets are in the direction of stack growth. */
10150 arm_compute_initial_elimination_offset (unsigned int from, unsigned int to)
10152 arm_stack_offsets *offsets;
10154 offsets = arm_get_frame_offsets ();
10156 /* OK, now we have enough information to compute the distances.
10157 There must be an entry in these switch tables for each pair
10158 of registers in ELIMINABLE_REGS, even if some of the entries
10159 seem to be redundant or useless. */
10162 case ARG_POINTER_REGNUM:
10165 case THUMB_HARD_FRAME_POINTER_REGNUM:
10168 case FRAME_POINTER_REGNUM:
10169 /* This is the reverse of the soft frame pointer
10170 to hard frame pointer elimination below. */
10171 return offsets->soft_frame - offsets->saved_args;
10173 case ARM_HARD_FRAME_POINTER_REGNUM:
10174 /* If there is no stack frame then the hard
10175 frame pointer and the arg pointer coincide. */
10176 if (offsets->frame == offsets->saved_regs)
10178 /* FIXME: Not sure about this. Maybe we should always return 0 ? */
10179 return (frame_pointer_needed
10180 && cfun->static_chain_decl != NULL
10181 && ! cfun->machine->uses_anonymous_args) ? 4 : 0;
10183 case STACK_POINTER_REGNUM:
10184 /* If nothing has been pushed on the stack at all
10185 then this will return -4. This *is* correct! */
10186 return offsets->outgoing_args - (offsets->saved_args + 4);
10193 case FRAME_POINTER_REGNUM:
10196 case THUMB_HARD_FRAME_POINTER_REGNUM:
10199 case ARM_HARD_FRAME_POINTER_REGNUM:
10200 /* The hard frame pointer points to the top entry in the
10201 stack frame. The soft frame pointer to the bottom entry
10202 in the stack frame. If there is no stack frame at all,
10203 then they are identical. */
10205 return offsets->frame - offsets->soft_frame;
10207 case STACK_POINTER_REGNUM:
10208 return offsets->outgoing_args - offsets->soft_frame;
10216 /* You cannot eliminate from the stack pointer.
10217 In theory you could eliminate from the hard frame
10218 pointer to the stack pointer, but this will never
10219 happen, since if a stack frame is not needed the
10220 hard frame pointer will never be used. */
10226 /* Generate the prologue instructions for entry into an ARM function. */
10228 arm_expand_prologue (void)
10234 unsigned long live_regs_mask;
10235 unsigned long func_type;
10237 int saved_pretend_args = 0;
10238 int saved_regs = 0;
10239 unsigned int args_to_push;
10240 arm_stack_offsets *offsets;
10242 func_type = arm_current_func_type ();
10244 /* Naked functions don't have prologues. */
10245 if (IS_NAKED (func_type))
10248 /* Make a copy of c_f_p_a_s as we may need to modify it locally. */
10249 args_to_push = current_function_pretend_args_size;
10251 /* Compute which register we will have to save onto the stack. */
10252 live_regs_mask = arm_compute_save_reg_mask ();
10254 ip_rtx = gen_rtx_REG (SImode, IP_REGNUM);
10256 if (frame_pointer_needed)
10258 if (IS_INTERRUPT (func_type))
10260 /* Interrupt functions must not corrupt any registers.
10261 Creating a frame pointer however, corrupts the IP
10262 register, so we must push it first. */
10263 insn = emit_multi_reg_push (1 << IP_REGNUM);
10265 /* Do not set RTX_FRAME_RELATED_P on this insn.
10266 The dwarf stack unwinding code only wants to see one
10267 stack decrement per function, and this is not it. If
10268 this instruction is labeled as being part of the frame
10269 creation sequence then dwarf2out_frame_debug_expr will
10270 abort when it encounters the assignment of IP to FP
10271 later on, since the use of SP here establishes SP as
10272 the CFA register and not IP.
10274 Anyway this instruction is not really part of the stack
10275 frame creation although it is part of the prologue. */
10277 else if (IS_NESTED (func_type))
10279 /* The Static chain register is the same as the IP register
10280 used as a scratch register during stack frame creation.
10281 To get around this need to find somewhere to store IP
10282 whilst the frame is being created. We try the following
10285 1. The last argument register.
10286 2. A slot on the stack above the frame. (This only
10287 works if the function is not a varargs function).
10288 3. Register r3, after pushing the argument registers
10291 Note - we only need to tell the dwarf2 backend about the SP
10292 adjustment in the second variant; the static chain register
10293 doesn't need to be unwound, as it doesn't contain a value
10294 inherited from the caller. */
10296 if (regs_ever_live[3] == 0)
10298 insn = gen_rtx_REG (SImode, 3);
10299 insn = gen_rtx_SET (SImode, insn, ip_rtx);
10300 insn = emit_insn (insn);
10302 else if (args_to_push == 0)
10305 insn = gen_rtx_PRE_DEC (SImode, stack_pointer_rtx);
10306 insn = gen_rtx_MEM (SImode, insn);
10307 insn = gen_rtx_SET (VOIDmode, insn, ip_rtx);
10308 insn = emit_insn (insn);
10312 /* Just tell the dwarf backend that we adjusted SP. */
10313 dwarf = gen_rtx_SET (VOIDmode, stack_pointer_rtx,
10314 gen_rtx_PLUS (SImode, stack_pointer_rtx,
10315 GEN_INT (-fp_offset)));
10316 RTX_FRAME_RELATED_P (insn) = 1;
10317 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
10318 dwarf, REG_NOTES (insn));
10322 /* Store the args on the stack. */
10323 if (cfun->machine->uses_anonymous_args)
10324 insn = emit_multi_reg_push
10325 ((0xf0 >> (args_to_push / 4)) & 0xf);
10328 (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,
10329 GEN_INT (- args_to_push)));
10331 RTX_FRAME_RELATED_P (insn) = 1;
10333 saved_pretend_args = 1;
10334 fp_offset = args_to_push;
10337 /* Now reuse r3 to preserve IP. */
10338 insn = gen_rtx_REG (SImode, 3);
10339 insn = gen_rtx_SET (SImode, insn, ip_rtx);
10340 (void) emit_insn (insn);
10346 insn = gen_rtx_PLUS (SImode, stack_pointer_rtx, GEN_INT (fp_offset));
10347 insn = gen_rtx_SET (SImode, ip_rtx, insn);
10350 insn = gen_movsi (ip_rtx, stack_pointer_rtx);
10352 insn = emit_insn (insn);
10353 RTX_FRAME_RELATED_P (insn) = 1;
10358 /* Push the argument registers, or reserve space for them. */
10359 if (cfun->machine->uses_anonymous_args)
10360 insn = emit_multi_reg_push
10361 ((0xf0 >> (args_to_push / 4)) & 0xf);
10364 (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,
10365 GEN_INT (- args_to_push)));
10366 RTX_FRAME_RELATED_P (insn) = 1;
10369 /* If this is an interrupt service routine, and the link register
10370 is going to be pushed, and we are not creating a stack frame,
10371 (which would involve an extra push of IP and a pop in the epilogue)
10372 subtracting four from LR now will mean that the function return
10373 can be done with a single instruction. */
10374 if ((func_type == ARM_FT_ISR || func_type == ARM_FT_FIQ)
10375 && (live_regs_mask & (1 << LR_REGNUM)) != 0
10376 && ! frame_pointer_needed)
10377 emit_insn (gen_rtx_SET (SImode,
10378 gen_rtx_REG (SImode, LR_REGNUM),
10379 gen_rtx_PLUS (SImode,
10380 gen_rtx_REG (SImode, LR_REGNUM),
10383 if (live_regs_mask)
10385 insn = emit_multi_reg_push (live_regs_mask);
10386 saved_regs += bit_count (live_regs_mask) * 4;
10387 RTX_FRAME_RELATED_P (insn) = 1;
10391 for (reg = LAST_IWMMXT_REGNUM; reg >= FIRST_IWMMXT_REGNUM; reg--)
10392 if (regs_ever_live[reg] && ! call_used_regs [reg])
10394 insn = gen_rtx_PRE_DEC (V2SImode, stack_pointer_rtx);
10395 insn = gen_rtx_MEM (V2SImode, insn);
10396 insn = emit_insn (gen_rtx_SET (VOIDmode, insn,
10397 gen_rtx_REG (V2SImode, reg)));
10398 RTX_FRAME_RELATED_P (insn) = 1;
10402 if (! IS_VOLATILE (func_type))
10406 /* Save any floating point call-saved registers used by this
10408 if (arm_fpu_arch == FPUTYPE_FPA_EMU2)
10410 for (reg = LAST_FPA_REGNUM; reg >= FIRST_FPA_REGNUM; reg--)
10411 if (regs_ever_live[reg] && !call_used_regs[reg])
10413 insn = gen_rtx_PRE_DEC (XFmode, stack_pointer_rtx);
10414 insn = gen_rtx_MEM (XFmode, insn);
10415 insn = emit_insn (gen_rtx_SET (VOIDmode, insn,
10416 gen_rtx_REG (XFmode, reg)));
10417 RTX_FRAME_RELATED_P (insn) = 1;
10423 start_reg = LAST_FPA_REGNUM;
10425 for (reg = LAST_FPA_REGNUM; reg >= FIRST_FPA_REGNUM; reg--)
10427 if (regs_ever_live[reg] && !call_used_regs[reg])
10429 if (start_reg - reg == 3)
10431 insn = emit_sfm (reg, 4);
10432 RTX_FRAME_RELATED_P (insn) = 1;
10434 start_reg = reg - 1;
10439 if (start_reg != reg)
10441 insn = emit_sfm (reg + 1, start_reg - reg);
10442 RTX_FRAME_RELATED_P (insn) = 1;
10443 saved_regs += (start_reg - reg) * 12;
10445 start_reg = reg - 1;
10449 if (start_reg != reg)
10451 insn = emit_sfm (reg + 1, start_reg - reg);
10452 saved_regs += (start_reg - reg) * 12;
10453 RTX_FRAME_RELATED_P (insn) = 1;
10456 if (TARGET_HARD_FLOAT && TARGET_VFP)
10458 start_reg = FIRST_VFP_REGNUM;
10460 for (reg = FIRST_VFP_REGNUM; reg < LAST_VFP_REGNUM; reg += 2)
10462 if ((!regs_ever_live[reg] || call_used_regs[reg])
10463 && (!regs_ever_live[reg + 1] || call_used_regs[reg + 1]))
10465 if (start_reg != reg)
10466 saved_regs += vfp_emit_fstmx (start_reg,
10467 (reg - start_reg) / 2);
10468 start_reg = reg + 2;
10471 if (start_reg != reg)
10472 saved_regs += vfp_emit_fstmx (start_reg,
10473 (reg - start_reg) / 2);
10477 if (frame_pointer_needed)
10479 /* Create the new frame pointer. */
10480 insn = GEN_INT (-(4 + args_to_push + fp_offset));
10481 insn = emit_insn (gen_addsi3 (hard_frame_pointer_rtx, ip_rtx, insn));
10482 RTX_FRAME_RELATED_P (insn) = 1;
10484 if (IS_NESTED (func_type))
10486 /* Recover the static chain register. */
10487 if (regs_ever_live [3] == 0
10488 || saved_pretend_args)
10489 insn = gen_rtx_REG (SImode, 3);
10490 else /* if (current_function_pretend_args_size == 0) */
10492 insn = gen_rtx_PLUS (SImode, hard_frame_pointer_rtx,
10494 insn = gen_rtx_MEM (SImode, insn);
10497 emit_insn (gen_rtx_SET (SImode, ip_rtx, insn));
10498 /* Add a USE to stop propagate_one_insn() from barfing. */
10499 emit_insn (gen_prologue_use (ip_rtx));
10503 offsets = arm_get_frame_offsets ();
10504 if (offsets->outgoing_args != offsets->saved_args + saved_regs)
10506 /* This add can produce multiple insns for a large constant, so we
10507 need to get tricky. */
10508 rtx last = get_last_insn ();
10510 amount = GEN_INT (offsets->saved_args + saved_regs
10511 - offsets->outgoing_args);
10513 insn = emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,
10517 last = last ? NEXT_INSN (last) : get_insns ();
10518 RTX_FRAME_RELATED_P (last) = 1;
10520 while (last != insn);
10522 /* If the frame pointer is needed, emit a special barrier that
10523 will prevent the scheduler from moving stores to the frame
10524 before the stack adjustment. */
10525 if (frame_pointer_needed)
10526 insn = emit_insn (gen_stack_tie (stack_pointer_rtx,
10527 hard_frame_pointer_rtx));
10530 /* If we are profiling, make sure no instructions are scheduled before
10531 the call to mcount. Similarly if the user has requested no
10532 scheduling in the prolog. */
10533 if (current_function_profile || TARGET_NO_SCHED_PRO)
10534 emit_insn (gen_blockage ());
10536 /* If the link register is being kept alive, with the return address in it,
10537 then make sure that it does not get reused by the ce2 pass. */
10538 if ((live_regs_mask & (1 << LR_REGNUM)) == 0)
10540 emit_insn (gen_prologue_use (gen_rtx_REG (SImode, LR_REGNUM)));
10541 cfun->machine->lr_save_eliminated = 1;
10545 /* If CODE is 'd', then the X is a condition operand and the instruction
10546 should only be executed if the condition is true.
10547 if CODE is 'D', then the X is a condition operand and the instruction
10548 should only be executed if the condition is false: however, if the mode
10549 of the comparison is CCFPEmode, then always execute the instruction -- we
10550 do this because in these circumstances !GE does not necessarily imply LT;
10551 in these cases the instruction pattern will take care to make sure that
10552 an instruction containing %d will follow, thereby undoing the effects of
10553 doing this instruction unconditionally.
10554 If CODE is 'N' then X is a floating point operand that must be negated
10556 If CODE is 'B' then output a bitwise inverted value of X (a const int).
10557 If X is a REG and CODE is `M', output a ldm/stm style multi-reg. */
10559 arm_print_operand (FILE *stream, rtx x, int code)
10564 fputs (ASM_COMMENT_START, stream);
10568 fputs (user_label_prefix, stream);
10572 fputs (REGISTER_PREFIX, stream);
10576 if (arm_ccfsm_state == 3 || arm_ccfsm_state == 4)
10578 if (TARGET_THUMB || current_insn_predicate != NULL)
10581 fputs (arm_condition_codes[arm_current_cc], stream);
10583 else if (current_insn_predicate)
10585 enum arm_cond_code code;
10590 code = get_arm_condition_code (current_insn_predicate);
10591 fputs (arm_condition_codes[code], stream);
10598 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
10599 r = REAL_VALUE_NEGATE (r);
10600 fprintf (stream, "%s", fp_const_from_val (&r));
10605 if (GET_CODE (x) == CONST_INT)
10608 val = ARM_SIGN_EXTEND (~INTVAL (x));
10609 fprintf (stream, HOST_WIDE_INT_PRINT_DEC, val);
10613 putc ('~', stream);
10614 output_addr_const (stream, x);
10619 fprintf (stream, "%s", arithmetic_instr (x, 1));
10622 /* Truncate Cirrus shift counts. */
10624 if (GET_CODE (x) == CONST_INT)
10626 fprintf (stream, HOST_WIDE_INT_PRINT_DEC, INTVAL (x) & 0x3f);
10629 arm_print_operand (stream, x, 0);
10633 fprintf (stream, "%s", arithmetic_instr (x, 0));
10639 const char * shift = shift_op (x, &val);
10643 fprintf (stream, ", %s ", shift_op (x, &val));
10645 arm_print_operand (stream, XEXP (x, 1), 0);
10647 fprintf (stream, "#" HOST_WIDE_INT_PRINT_DEC, val);
10652 /* An explanation of the 'Q', 'R' and 'H' register operands:
10654 In a pair of registers containing a DI or DF value the 'Q'
10655 operand returns the register number of the register containing
10656 the least significant part of the value. The 'R' operand returns
10657 the register number of the register containing the most
10658 significant part of the value.
10660 The 'H' operand returns the higher of the two register numbers.
10661 On a run where WORDS_BIG_ENDIAN is true the 'H' operand is the
10662 same as the 'Q' operand, since the most significant part of the
10663 value is held in the lower number register. The reverse is true
10664 on systems where WORDS_BIG_ENDIAN is false.
10666 The purpose of these operands is to distinguish between cases
10667 where the endian-ness of the values is important (for example
10668 when they are added together), and cases where the endian-ness
10669 is irrelevant, but the order of register operations is important.
10670 For example when loading a value from memory into a register
10671 pair, the endian-ness does not matter. Provided that the value
10672 from the lower memory address is put into the lower numbered
10673 register, and the value from the higher address is put into the
10674 higher numbered register, the load will work regardless of whether
10675 the value being loaded is big-wordian or little-wordian. The
10676 order of the two register loads can matter however, if the address
10677 of the memory location is actually held in one of the registers
10678 being overwritten by the load. */
10680 if (REGNO (x) > LAST_ARM_REGNUM)
10682 asm_fprintf (stream, "%r", REGNO (x) + (WORDS_BIG_ENDIAN ? 1 : 0));
10686 if (REGNO (x) > LAST_ARM_REGNUM)
10688 asm_fprintf (stream, "%r", REGNO (x) + (WORDS_BIG_ENDIAN ? 0 : 1));
10692 if (REGNO (x) > LAST_ARM_REGNUM)
10694 asm_fprintf (stream, "%r", REGNO (x) + 1);
10698 asm_fprintf (stream, "%r",
10699 GET_CODE (XEXP (x, 0)) == REG
10700 ? REGNO (XEXP (x, 0)) : REGNO (XEXP (XEXP (x, 0), 0)));
10704 asm_fprintf (stream, "{%r-%r}",
10706 REGNO (x) + ARM_NUM_REGS (GET_MODE (x)) - 1);
10710 /* CONST_TRUE_RTX means always -- that's the default. */
10711 if (x == const_true_rtx)
10714 fputs (arm_condition_codes[get_arm_condition_code (x)],
10719 /* CONST_TRUE_RTX means not always -- ie never. We shouldn't ever
10720 want to do that. */
10721 if (x == const_true_rtx)
10724 fputs (arm_condition_codes[ARM_INVERSE_CONDITION_CODE
10725 (get_arm_condition_code (x))],
10729 /* Cirrus registers can be accessed in a variety of ways:
10730 single floating point (f)
10731 double floating point (d)
10733 64bit integer (dx). */
10734 case 'W': /* Cirrus register in F mode. */
10735 case 'X': /* Cirrus register in D mode. */
10736 case 'Y': /* Cirrus register in FX mode. */
10737 case 'Z': /* Cirrus register in DX mode. */
10738 if (GET_CODE (x) != REG || REGNO_REG_CLASS (REGNO (x)) != CIRRUS_REGS)
10741 fprintf (stream, "mv%s%s",
10743 : code == 'X' ? "d"
10744 : code == 'Y' ? "fx" : "dx", reg_names[REGNO (x)] + 2);
10748 /* Print cirrus register in the mode specified by the register's mode. */
10751 int mode = GET_MODE (x);
10753 if (GET_CODE (x) != REG || REGNO_REG_CLASS (REGNO (x)) != CIRRUS_REGS)
10756 fprintf (stream, "mv%s%s",
10757 mode == DFmode ? "d"
10758 : mode == SImode ? "fx"
10759 : mode == DImode ? "dx"
10760 : "f", reg_names[REGNO (x)] + 2);
10766 if (GET_CODE (x) != REG
10767 || REGNO (x) < FIRST_IWMMXT_GR_REGNUM
10768 || REGNO (x) > LAST_IWMMXT_GR_REGNUM)
10769 /* Bad value for wCG register number. */
10772 fprintf (stream, "%d", REGNO (x) - FIRST_IWMMXT_GR_REGNUM);
10775 /* Print an iWMMXt control register name. */
10777 if (GET_CODE (x) != CONST_INT
10779 || INTVAL (x) >= 16)
10780 /* Bad value for wC register number. */
10784 static const char * wc_reg_names [16] =
10786 "wCID", "wCon", "wCSSF", "wCASF",
10787 "wC4", "wC5", "wC6", "wC7",
10788 "wCGR0", "wCGR1", "wCGR2", "wCGR3",
10789 "wC12", "wC13", "wC14", "wC15"
10792 fprintf (stream, wc_reg_names [INTVAL (x)]);
10796 /* Print a VFP double precision register name. */
10799 int mode = GET_MODE (x);
10802 if (mode != DImode && mode != DFmode)
10805 if (GET_CODE (x) != REG
10806 || !IS_VFP_REGNUM (REGNO (x)))
10809 num = REGNO(x) - FIRST_VFP_REGNUM;
10813 fprintf (stream, "d%d", num >> 1);
10821 if (GET_CODE (x) == REG)
10822 asm_fprintf (stream, "%r", REGNO (x));
10823 else if (GET_CODE (x) == MEM)
10825 output_memory_reference_mode = GET_MODE (x);
10826 output_address (XEXP (x, 0));
10828 else if (GET_CODE (x) == CONST_DOUBLE)
10829 fprintf (stream, "#%s", fp_immediate_constant (x));
10830 else if (GET_CODE (x) == NEG)
10831 abort (); /* This should never happen now. */
10834 fputc ('#', stream);
10835 output_addr_const (stream, x);
10840 #ifndef AOF_ASSEMBLER
10841 /* Target hook for assembling integer objects. The ARM version needs to
10842 handle word-sized values specially. */
10844 arm_assemble_integer (rtx x, unsigned int size, int aligned_p)
10846 if (size == UNITS_PER_WORD && aligned_p)
10848 fputs ("\t.word\t", asm_out_file);
10849 output_addr_const (asm_out_file, x);
10851 /* Mark symbols as position independent. We only do this in the
10852 .text segment, not in the .data segment. */
10853 if (NEED_GOT_RELOC && flag_pic && making_const_table &&
10854 (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == LABEL_REF))
10856 if (GET_CODE (x) == SYMBOL_REF
10857 && (CONSTANT_POOL_ADDRESS_P (x)
10858 || SYMBOL_REF_LOCAL_P (x)))
10859 fputs ("(GOTOFF)", asm_out_file);
10860 else if (GET_CODE (x) == LABEL_REF)
10861 fputs ("(GOTOFF)", asm_out_file);
10863 fputs ("(GOT)", asm_out_file);
10865 fputc ('\n', asm_out_file);
10869 if (VECTOR_MODE_SUPPORTED_P (GET_MODE (x)))
10873 if (GET_CODE (x) != CONST_VECTOR)
10876 units = CONST_VECTOR_NUNITS (x);
10878 switch (GET_MODE (x))
10880 case V2SImode: size = 4; break;
10881 case V4HImode: size = 2; break;
10882 case V8QImode: size = 1; break;
10887 for (i = 0; i < units; i++)
10891 elt = CONST_VECTOR_ELT (x, i);
10893 (elt, size, i == 0 ? BIGGEST_ALIGNMENT : size * BITS_PER_UNIT, 1);
10899 return default_assemble_integer (x, size, aligned_p);
10903 /* A finite state machine takes care of noticing whether or not instructions
10904 can be conditionally executed, and thus decrease execution time and code
10905 size by deleting branch instructions. The fsm is controlled by
10906 final_prescan_insn, and controls the actions of ASM_OUTPUT_OPCODE. */
10908 /* The state of the fsm controlling condition codes are:
10909 0: normal, do nothing special
10910 1: make ASM_OUTPUT_OPCODE not output this instruction
10911 2: make ASM_OUTPUT_OPCODE not output this instruction
10912 3: make instructions conditional
10913 4: make instructions conditional
10915 State transitions (state->state by whom under condition):
10916 0 -> 1 final_prescan_insn if the `target' is a label
10917 0 -> 2 final_prescan_insn if the `target' is an unconditional branch
10918 1 -> 3 ASM_OUTPUT_OPCODE after not having output the conditional branch
10919 2 -> 4 ASM_OUTPUT_OPCODE after not having output the conditional branch
10920 3 -> 0 (*targetm.asm_out.internal_label) if the `target' label is reached
10921 (the target label has CODE_LABEL_NUMBER equal to arm_target_label).
10922 4 -> 0 final_prescan_insn if the `target' unconditional branch is reached
10923 (the target insn is arm_target_insn).
10925 If the jump clobbers the conditions then we use states 2 and 4.
10927 A similar thing can be done with conditional return insns.
10929 XXX In case the `target' is an unconditional branch, this conditionalising
10930 of the instructions always reduces code size, but not always execution
10931 time. But then, I want to reduce the code size to somewhere near what
10932 /bin/cc produces. */
10934 /* Returns the index of the ARM condition code string in
10935 `arm_condition_codes'. COMPARISON should be an rtx like
10936 `(eq (...) (...))'. */
10937 static enum arm_cond_code
10938 get_arm_condition_code (rtx comparison)
10940 enum machine_mode mode = GET_MODE (XEXP (comparison, 0));
10942 enum rtx_code comp_code = GET_CODE (comparison);
10944 if (GET_MODE_CLASS (mode) != MODE_CC)
10945 mode = SELECT_CC_MODE (comp_code, XEXP (comparison, 0),
10946 XEXP (comparison, 1));
10950 case CC_DNEmode: code = ARM_NE; goto dominance;
10951 case CC_DEQmode: code = ARM_EQ; goto dominance;
10952 case CC_DGEmode: code = ARM_GE; goto dominance;
10953 case CC_DGTmode: code = ARM_GT; goto dominance;
10954 case CC_DLEmode: code = ARM_LE; goto dominance;
10955 case CC_DLTmode: code = ARM_LT; goto dominance;
10956 case CC_DGEUmode: code = ARM_CS; goto dominance;
10957 case CC_DGTUmode: code = ARM_HI; goto dominance;
10958 case CC_DLEUmode: code = ARM_LS; goto dominance;
10959 case CC_DLTUmode: code = ARM_CC;
10962 if (comp_code != EQ && comp_code != NE)
10965 if (comp_code == EQ)
10966 return ARM_INVERSE_CONDITION_CODE (code);
10972 case NE: return ARM_NE;
10973 case EQ: return ARM_EQ;
10974 case GE: return ARM_PL;
10975 case LT: return ARM_MI;
10982 case NE: return ARM_NE;
10983 case EQ: return ARM_EQ;
10990 case NE: return ARM_MI;
10991 case EQ: return ARM_PL;
10997 /* These encodings assume that AC=1 in the FPA system control
10998 byte. This allows us to handle all cases except UNEQ and
11002 case GE: return ARM_GE;
11003 case GT: return ARM_GT;
11004 case LE: return ARM_LS;
11005 case LT: return ARM_MI;
11006 case NE: return ARM_NE;
11007 case EQ: return ARM_EQ;
11008 case ORDERED: return ARM_VC;
11009 case UNORDERED: return ARM_VS;
11010 case UNLT: return ARM_LT;
11011 case UNLE: return ARM_LE;
11012 case UNGT: return ARM_HI;
11013 case UNGE: return ARM_PL;
11014 /* UNEQ and LTGT do not have a representation. */
11015 case UNEQ: /* Fall through. */
11016 case LTGT: /* Fall through. */
11023 case NE: return ARM_NE;
11024 case EQ: return ARM_EQ;
11025 case GE: return ARM_LE;
11026 case GT: return ARM_LT;
11027 case LE: return ARM_GE;
11028 case LT: return ARM_GT;
11029 case GEU: return ARM_LS;
11030 case GTU: return ARM_CC;
11031 case LEU: return ARM_CS;
11032 case LTU: return ARM_HI;
11039 case LTU: return ARM_CS;
11040 case GEU: return ARM_CC;
11047 case NE: return ARM_NE;
11048 case EQ: return ARM_EQ;
11049 case GE: return ARM_GE;
11050 case GT: return ARM_GT;
11051 case LE: return ARM_LE;
11052 case LT: return ARM_LT;
11053 case GEU: return ARM_CS;
11054 case GTU: return ARM_HI;
11055 case LEU: return ARM_LS;
11056 case LTU: return ARM_CC;
11067 arm_final_prescan_insn (rtx insn)
11069 /* BODY will hold the body of INSN. */
11070 rtx body = PATTERN (insn);
11072 /* This will be 1 if trying to repeat the trick, and things need to be
11073 reversed if it appears to fail. */
11076 /* JUMP_CLOBBERS will be one implies that the conditions if a branch is
11077 taken are clobbered, even if the rtl suggests otherwise. It also
11078 means that we have to grub around within the jump expression to find
11079 out what the conditions are when the jump isn't taken. */
11080 int jump_clobbers = 0;
11082 /* If we start with a return insn, we only succeed if we find another one. */
11083 int seeking_return = 0;
11085 /* START_INSN will hold the insn from where we start looking. This is the
11086 first insn after the following code_label if REVERSE is true. */
11087 rtx start_insn = insn;
11089 /* If in state 4, check if the target branch is reached, in order to
11090 change back to state 0. */
11091 if (arm_ccfsm_state == 4)
11093 if (insn == arm_target_insn)
11095 arm_target_insn = NULL;
11096 arm_ccfsm_state = 0;
11101 /* If in state 3, it is possible to repeat the trick, if this insn is an
11102 unconditional branch to a label, and immediately following this branch
11103 is the previous target label which is only used once, and the label this
11104 branch jumps to is not too far off. */
11105 if (arm_ccfsm_state == 3)
11107 if (simplejump_p (insn))
11109 start_insn = next_nonnote_insn (start_insn);
11110 if (GET_CODE (start_insn) == BARRIER)
11112 /* XXX Isn't this always a barrier? */
11113 start_insn = next_nonnote_insn (start_insn);
11115 if (GET_CODE (start_insn) == CODE_LABEL
11116 && CODE_LABEL_NUMBER (start_insn) == arm_target_label
11117 && LABEL_NUSES (start_insn) == 1)
11122 else if (GET_CODE (body) == RETURN)
11124 start_insn = next_nonnote_insn (start_insn);
11125 if (GET_CODE (start_insn) == BARRIER)
11126 start_insn = next_nonnote_insn (start_insn);
11127 if (GET_CODE (start_insn) == CODE_LABEL
11128 && CODE_LABEL_NUMBER (start_insn) == arm_target_label
11129 && LABEL_NUSES (start_insn) == 1)
11132 seeking_return = 1;
11141 if (arm_ccfsm_state != 0 && !reverse)
11143 if (GET_CODE (insn) != JUMP_INSN)
11146 /* This jump might be paralleled with a clobber of the condition codes
11147 the jump should always come first */
11148 if (GET_CODE (body) == PARALLEL && XVECLEN (body, 0) > 0)
11149 body = XVECEXP (body, 0, 0);
11152 || (GET_CODE (body) == SET && GET_CODE (SET_DEST (body)) == PC
11153 && GET_CODE (SET_SRC (body)) == IF_THEN_ELSE))
11156 int fail = FALSE, succeed = FALSE;
11157 /* Flag which part of the IF_THEN_ELSE is the LABEL_REF. */
11158 int then_not_else = TRUE;
11159 rtx this_insn = start_insn, label = 0;
11161 /* If the jump cannot be done with one instruction, we cannot
11162 conditionally execute the instruction in the inverse case. */
11163 if (get_attr_conds (insn) == CONDS_JUMP_CLOB)
11169 /* Register the insn jumped to. */
11172 if (!seeking_return)
11173 label = XEXP (SET_SRC (body), 0);
11175 else if (GET_CODE (XEXP (SET_SRC (body), 1)) == LABEL_REF)
11176 label = XEXP (XEXP (SET_SRC (body), 1), 0);
11177 else if (GET_CODE (XEXP (SET_SRC (body), 2)) == LABEL_REF)
11179 label = XEXP (XEXP (SET_SRC (body), 2), 0);
11180 then_not_else = FALSE;
11182 else if (GET_CODE (XEXP (SET_SRC (body), 1)) == RETURN)
11183 seeking_return = 1;
11184 else if (GET_CODE (XEXP (SET_SRC (body), 2)) == RETURN)
11186 seeking_return = 1;
11187 then_not_else = FALSE;
11192 /* See how many insns this branch skips, and what kind of insns. If all
11193 insns are okay, and the label or unconditional branch to the same
11194 label is not too far away, succeed. */
11195 for (insns_skipped = 0;
11196 !fail && !succeed && insns_skipped++ < max_insns_skipped;)
11200 this_insn = next_nonnote_insn (this_insn);
11204 switch (GET_CODE (this_insn))
11207 /* Succeed if it is the target label, otherwise fail since
11208 control falls in from somewhere else. */
11209 if (this_insn == label)
11213 arm_ccfsm_state = 2;
11214 this_insn = next_nonnote_insn (this_insn);
11217 arm_ccfsm_state = 1;
11225 /* Succeed if the following insn is the target label.
11227 If return insns are used then the last insn in a function
11228 will be a barrier. */
11229 this_insn = next_nonnote_insn (this_insn);
11230 if (this_insn && this_insn == label)
11234 arm_ccfsm_state = 2;
11235 this_insn = next_nonnote_insn (this_insn);
11238 arm_ccfsm_state = 1;
11246 /* The AAPCS says that conditional calls should not be
11247 used since they make interworking inefficient (the
11248 linker can't transform BL<cond> into BLX). That's
11249 only a problem if the machine has BLX. */
11256 /* Succeed if the following insn is the target label, or
11257 if the following two insns are a barrier and the
11259 this_insn = next_nonnote_insn (this_insn);
11260 if (this_insn && GET_CODE (this_insn) == BARRIER)
11261 this_insn = next_nonnote_insn (this_insn);
11263 if (this_insn && this_insn == label
11264 && insns_skipped < max_insns_skipped)
11268 arm_ccfsm_state = 2;
11269 this_insn = next_nonnote_insn (this_insn);
11272 arm_ccfsm_state = 1;
11280 /* If this is an unconditional branch to the same label, succeed.
11281 If it is to another label, do nothing. If it is conditional,
11283 /* XXX Probably, the tests for SET and the PC are
11286 scanbody = PATTERN (this_insn);
11287 if (GET_CODE (scanbody) == SET
11288 && GET_CODE (SET_DEST (scanbody)) == PC)
11290 if (GET_CODE (SET_SRC (scanbody)) == LABEL_REF
11291 && XEXP (SET_SRC (scanbody), 0) == label && !reverse)
11293 arm_ccfsm_state = 2;
11296 else if (GET_CODE (SET_SRC (scanbody)) == IF_THEN_ELSE)
11299 /* Fail if a conditional return is undesirable (eg on a
11300 StrongARM), but still allow this if optimizing for size. */
11301 else if (GET_CODE (scanbody) == RETURN
11302 && !use_return_insn (TRUE, NULL)
11305 else if (GET_CODE (scanbody) == RETURN
11308 arm_ccfsm_state = 2;
11311 else if (GET_CODE (scanbody) == PARALLEL)
11313 switch (get_attr_conds (this_insn))
11323 fail = TRUE; /* Unrecognized jump (eg epilogue). */
11328 /* Instructions using or affecting the condition codes make it
11330 scanbody = PATTERN (this_insn);
11331 if (!(GET_CODE (scanbody) == SET
11332 || GET_CODE (scanbody) == PARALLEL)
11333 || get_attr_conds (this_insn) != CONDS_NOCOND)
11336 /* A conditional cirrus instruction must be followed by
11337 a non Cirrus instruction. However, since we
11338 conditionalize instructions in this function and by
11339 the time we get here we can't add instructions
11340 (nops), because shorten_branches() has already been
11341 called, we will disable conditionalizing Cirrus
11342 instructions to be safe. */
11343 if (GET_CODE (scanbody) != USE
11344 && GET_CODE (scanbody) != CLOBBER
11345 && get_attr_cirrus (this_insn) != CIRRUS_NOT)
11355 if ((!seeking_return) && (arm_ccfsm_state == 1 || reverse))
11356 arm_target_label = CODE_LABEL_NUMBER (label);
11357 else if (seeking_return || arm_ccfsm_state == 2)
11359 while (this_insn && GET_CODE (PATTERN (this_insn)) == USE)
11361 this_insn = next_nonnote_insn (this_insn);
11362 if (this_insn && (GET_CODE (this_insn) == BARRIER
11363 || GET_CODE (this_insn) == CODE_LABEL))
11368 /* Oh, dear! we ran off the end.. give up. */
11369 recog (PATTERN (insn), insn, NULL);
11370 arm_ccfsm_state = 0;
11371 arm_target_insn = NULL;
11374 arm_target_insn = this_insn;
11383 get_arm_condition_code (XEXP (XEXP (XEXP (SET_SRC (body),
11385 if (GET_CODE (XEXP (XEXP (SET_SRC (body), 0), 0)) == AND)
11386 arm_current_cc = ARM_INVERSE_CONDITION_CODE (arm_current_cc);
11387 if (GET_CODE (XEXP (SET_SRC (body), 0)) == NE)
11388 arm_current_cc = ARM_INVERSE_CONDITION_CODE (arm_current_cc);
11392 /* If REVERSE is true, ARM_CURRENT_CC needs to be inverted from
11395 arm_current_cc = get_arm_condition_code (XEXP (SET_SRC (body),
11399 if (reverse || then_not_else)
11400 arm_current_cc = ARM_INVERSE_CONDITION_CODE (arm_current_cc);
11403 /* Restore recog_data (getting the attributes of other insns can
11404 destroy this array, but final.c assumes that it remains intact
11405 across this call; since the insn has been recognized already we
11406 call recog direct). */
11407 recog (PATTERN (insn), insn, NULL);
11411 /* Returns true if REGNO is a valid register
11412 for holding a quantity of tyoe MODE. */
11414 arm_hard_regno_mode_ok (unsigned int regno, enum machine_mode mode)
11416 if (GET_MODE_CLASS (mode) == MODE_CC)
11417 return regno == CC_REGNUM || regno == VFPCC_REGNUM;
11420 /* For the Thumb we only allow values bigger than SImode in
11421 registers 0 - 6, so that there is always a second low
11422 register available to hold the upper part of the value.
11423 We probably we ought to ensure that the register is the
11424 start of an even numbered register pair. */
11425 return (ARM_NUM_REGS (mode) < 2) || (regno < LAST_LO_REGNUM);
11427 if (IS_CIRRUS_REGNUM (regno))
11428 /* We have outlawed SI values in Cirrus registers because they
11429 reside in the lower 32 bits, but SF values reside in the
11430 upper 32 bits. This causes gcc all sorts of grief. We can't
11431 even split the registers into pairs because Cirrus SI values
11432 get sign extended to 64bits-- aldyh. */
11433 return (GET_MODE_CLASS (mode) == MODE_FLOAT) || (mode == DImode);
11435 if (IS_VFP_REGNUM (regno))
11437 if (mode == SFmode || mode == SImode)
11440 /* DFmode values are only valid in even register pairs. */
11441 if (mode == DFmode)
11442 return ((regno - FIRST_VFP_REGNUM) & 1) == 0;
11446 if (IS_IWMMXT_GR_REGNUM (regno))
11447 return mode == SImode;
11449 if (IS_IWMMXT_REGNUM (regno))
11450 return VALID_IWMMXT_REG_MODE (mode);
11452 /* We allow any value to be stored in the general registers.
11453 Restrict doubleword quantities to even register pairs so that we can
11455 if (regno <= LAST_ARM_REGNUM)
11456 return !(TARGET_LDRD && GET_MODE_SIZE (mode) > 4 && (regno & 1) != 0);
11458 if ( regno == FRAME_POINTER_REGNUM
11459 || regno == ARG_POINTER_REGNUM)
11460 /* We only allow integers in the fake hard registers. */
11461 return GET_MODE_CLASS (mode) == MODE_INT;
11463 /* The only registers left are the FPA registers
11464 which we only allow to hold FP values. */
11465 return GET_MODE_CLASS (mode) == MODE_FLOAT
11466 && regno >= FIRST_FPA_REGNUM
11467 && regno <= LAST_FPA_REGNUM;
11471 arm_regno_class (int regno)
11475 if (regno == STACK_POINTER_REGNUM)
11477 if (regno == CC_REGNUM)
11484 if ( regno <= LAST_ARM_REGNUM
11485 || regno == FRAME_POINTER_REGNUM
11486 || regno == ARG_POINTER_REGNUM)
11487 return GENERAL_REGS;
11489 if (regno == CC_REGNUM || regno == VFPCC_REGNUM)
11492 if (IS_CIRRUS_REGNUM (regno))
11493 return CIRRUS_REGS;
11495 if (IS_VFP_REGNUM (regno))
11498 if (IS_IWMMXT_REGNUM (regno))
11499 return IWMMXT_REGS;
11501 if (IS_IWMMXT_GR_REGNUM (regno))
11502 return IWMMXT_GR_REGS;
11507 /* Handle a special case when computing the offset
11508 of an argument from the frame pointer. */
11510 arm_debugger_arg_offset (int value, rtx addr)
11514 /* We are only interested if dbxout_parms() failed to compute the offset. */
11518 /* We can only cope with the case where the address is held in a register. */
11519 if (GET_CODE (addr) != REG)
11522 /* If we are using the frame pointer to point at the argument, then
11523 an offset of 0 is correct. */
11524 if (REGNO (addr) == (unsigned) HARD_FRAME_POINTER_REGNUM)
11527 /* If we are using the stack pointer to point at the
11528 argument, then an offset of 0 is correct. */
11529 if ((TARGET_THUMB || !frame_pointer_needed)
11530 && REGNO (addr) == SP_REGNUM)
11533 /* Oh dear. The argument is pointed to by a register rather
11534 than being held in a register, or being stored at a known
11535 offset from the frame pointer. Since GDB only understands
11536 those two kinds of argument we must translate the address
11537 held in the register into an offset from the frame pointer.
11538 We do this by searching through the insns for the function
11539 looking to see where this register gets its value. If the
11540 register is initialized from the frame pointer plus an offset
11541 then we are in luck and we can continue, otherwise we give up.
11543 This code is exercised by producing debugging information
11544 for a function with arguments like this:
11546 double func (double a, double b, int c, double d) {return d;}
11548 Without this code the stab for parameter 'd' will be set to
11549 an offset of 0 from the frame pointer, rather than 8. */
11551 /* The if() statement says:
11553 If the insn is a normal instruction
11554 and if the insn is setting the value in a register
11555 and if the register being set is the register holding the address of the argument
11556 and if the address is computing by an addition
11557 that involves adding to a register
11558 which is the frame pointer
11563 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
11565 if ( GET_CODE (insn) == INSN
11566 && GET_CODE (PATTERN (insn)) == SET
11567 && REGNO (XEXP (PATTERN (insn), 0)) == REGNO (addr)
11568 && GET_CODE (XEXP (PATTERN (insn), 1)) == PLUS
11569 && GET_CODE (XEXP (XEXP (PATTERN (insn), 1), 0)) == REG
11570 && REGNO (XEXP (XEXP (PATTERN (insn), 1), 0)) == (unsigned) HARD_FRAME_POINTER_REGNUM
11571 && GET_CODE (XEXP (XEXP (PATTERN (insn), 1), 1)) == CONST_INT
11574 value = INTVAL (XEXP (XEXP (PATTERN (insn), 1), 1));
11583 warning ("unable to compute real location of stacked parameter");
11584 value = 8; /* XXX magic hack */
11590 #define def_mbuiltin(MASK, NAME, TYPE, CODE) \
11593 if ((MASK) & insn_flags) \
11594 builtin_function ((NAME), (TYPE), (CODE), BUILT_IN_MD, NULL, NULL_TREE); \
11598 struct builtin_description
11600 const unsigned int mask;
11601 const enum insn_code icode;
11602 const char * const name;
11603 const enum arm_builtins code;
11604 const enum rtx_code comparison;
11605 const unsigned int flag;
11608 static const struct builtin_description bdesc_2arg[] =
11610 #define IWMMXT_BUILTIN(code, string, builtin) \
11611 { FL_IWMMXT, CODE_FOR_##code, "__builtin_arm_" string, \
11612 ARM_BUILTIN_##builtin, 0, 0 },
11614 IWMMXT_BUILTIN (addv8qi3, "waddb", WADDB)
11615 IWMMXT_BUILTIN (addv4hi3, "waddh", WADDH)
11616 IWMMXT_BUILTIN (addv2si3, "waddw", WADDW)
11617 IWMMXT_BUILTIN (subv8qi3, "wsubb", WSUBB)
11618 IWMMXT_BUILTIN (subv4hi3, "wsubh", WSUBH)
11619 IWMMXT_BUILTIN (subv2si3, "wsubw", WSUBW)
11620 IWMMXT_BUILTIN (ssaddv8qi3, "waddbss", WADDSSB)
11621 IWMMXT_BUILTIN (ssaddv4hi3, "waddhss", WADDSSH)
11622 IWMMXT_BUILTIN (ssaddv2si3, "waddwss", WADDSSW)
11623 IWMMXT_BUILTIN (sssubv8qi3, "wsubbss", WSUBSSB)
11624 IWMMXT_BUILTIN (sssubv4hi3, "wsubhss", WSUBSSH)
11625 IWMMXT_BUILTIN (sssubv2si3, "wsubwss", WSUBSSW)
11626 IWMMXT_BUILTIN (usaddv8qi3, "waddbus", WADDUSB)
11627 IWMMXT_BUILTIN (usaddv4hi3, "waddhus", WADDUSH)
11628 IWMMXT_BUILTIN (usaddv2si3, "waddwus", WADDUSW)
11629 IWMMXT_BUILTIN (ussubv8qi3, "wsubbus", WSUBUSB)
11630 IWMMXT_BUILTIN (ussubv4hi3, "wsubhus", WSUBUSH)
11631 IWMMXT_BUILTIN (ussubv2si3, "wsubwus", WSUBUSW)
11632 IWMMXT_BUILTIN (mulv4hi3, "wmulul", WMULUL)
11633 IWMMXT_BUILTIN (smulv4hi3_highpart, "wmulsm", WMULSM)
11634 IWMMXT_BUILTIN (umulv4hi3_highpart, "wmulum", WMULUM)
11635 IWMMXT_BUILTIN (eqv8qi3, "wcmpeqb", WCMPEQB)
11636 IWMMXT_BUILTIN (eqv4hi3, "wcmpeqh", WCMPEQH)
11637 IWMMXT_BUILTIN (eqv2si3, "wcmpeqw", WCMPEQW)
11638 IWMMXT_BUILTIN (gtuv8qi3, "wcmpgtub", WCMPGTUB)
11639 IWMMXT_BUILTIN (gtuv4hi3, "wcmpgtuh", WCMPGTUH)
11640 IWMMXT_BUILTIN (gtuv2si3, "wcmpgtuw", WCMPGTUW)
11641 IWMMXT_BUILTIN (gtv8qi3, "wcmpgtsb", WCMPGTSB)
11642 IWMMXT_BUILTIN (gtv4hi3, "wcmpgtsh", WCMPGTSH)
11643 IWMMXT_BUILTIN (gtv2si3, "wcmpgtsw", WCMPGTSW)
11644 IWMMXT_BUILTIN (umaxv8qi3, "wmaxub", WMAXUB)
11645 IWMMXT_BUILTIN (smaxv8qi3, "wmaxsb", WMAXSB)
11646 IWMMXT_BUILTIN (umaxv4hi3, "wmaxuh", WMAXUH)
11647 IWMMXT_BUILTIN (smaxv4hi3, "wmaxsh", WMAXSH)
11648 IWMMXT_BUILTIN (umaxv2si3, "wmaxuw", WMAXUW)
11649 IWMMXT_BUILTIN (smaxv2si3, "wmaxsw", WMAXSW)
11650 IWMMXT_BUILTIN (uminv8qi3, "wminub", WMINUB)
11651 IWMMXT_BUILTIN (sminv8qi3, "wminsb", WMINSB)
11652 IWMMXT_BUILTIN (uminv4hi3, "wminuh", WMINUH)
11653 IWMMXT_BUILTIN (sminv4hi3, "wminsh", WMINSH)
11654 IWMMXT_BUILTIN (uminv2si3, "wminuw", WMINUW)
11655 IWMMXT_BUILTIN (sminv2si3, "wminsw", WMINSW)
11656 IWMMXT_BUILTIN (iwmmxt_anddi3, "wand", WAND)
11657 IWMMXT_BUILTIN (iwmmxt_nanddi3, "wandn", WANDN)
11658 IWMMXT_BUILTIN (iwmmxt_iordi3, "wor", WOR)
11659 IWMMXT_BUILTIN (iwmmxt_xordi3, "wxor", WXOR)
11660 IWMMXT_BUILTIN (iwmmxt_uavgv8qi3, "wavg2b", WAVG2B)
11661 IWMMXT_BUILTIN (iwmmxt_uavgv4hi3, "wavg2h", WAVG2H)
11662 IWMMXT_BUILTIN (iwmmxt_uavgrndv8qi3, "wavg2br", WAVG2BR)
11663 IWMMXT_BUILTIN (iwmmxt_uavgrndv4hi3, "wavg2hr", WAVG2HR)
11664 IWMMXT_BUILTIN (iwmmxt_wunpckilb, "wunpckilb", WUNPCKILB)
11665 IWMMXT_BUILTIN (iwmmxt_wunpckilh, "wunpckilh", WUNPCKILH)
11666 IWMMXT_BUILTIN (iwmmxt_wunpckilw, "wunpckilw", WUNPCKILW)
11667 IWMMXT_BUILTIN (iwmmxt_wunpckihb, "wunpckihb", WUNPCKIHB)
11668 IWMMXT_BUILTIN (iwmmxt_wunpckihh, "wunpckihh", WUNPCKIHH)
11669 IWMMXT_BUILTIN (iwmmxt_wunpckihw, "wunpckihw", WUNPCKIHW)
11670 IWMMXT_BUILTIN (iwmmxt_wmadds, "wmadds", WMADDS)
11671 IWMMXT_BUILTIN (iwmmxt_wmaddu, "wmaddu", WMADDU)
11673 #define IWMMXT_BUILTIN2(code, builtin) \
11674 { FL_IWMMXT, CODE_FOR_##code, NULL, ARM_BUILTIN_##builtin, 0, 0 },
11676 IWMMXT_BUILTIN2 (iwmmxt_wpackhss, WPACKHSS)
11677 IWMMXT_BUILTIN2 (iwmmxt_wpackwss, WPACKWSS)
11678 IWMMXT_BUILTIN2 (iwmmxt_wpackdss, WPACKDSS)
11679 IWMMXT_BUILTIN2 (iwmmxt_wpackhus, WPACKHUS)
11680 IWMMXT_BUILTIN2 (iwmmxt_wpackwus, WPACKWUS)
11681 IWMMXT_BUILTIN2 (iwmmxt_wpackdus, WPACKDUS)
11682 IWMMXT_BUILTIN2 (ashlv4hi3_di, WSLLH)
11683 IWMMXT_BUILTIN2 (ashlv4hi3, WSLLHI)
11684 IWMMXT_BUILTIN2 (ashlv2si3_di, WSLLW)
11685 IWMMXT_BUILTIN2 (ashlv2si3, WSLLWI)
11686 IWMMXT_BUILTIN2 (ashldi3_di, WSLLD)
11687 IWMMXT_BUILTIN2 (ashldi3_iwmmxt, WSLLDI)
11688 IWMMXT_BUILTIN2 (lshrv4hi3_di, WSRLH)
11689 IWMMXT_BUILTIN2 (lshrv4hi3, WSRLHI)
11690 IWMMXT_BUILTIN2 (lshrv2si3_di, WSRLW)
11691 IWMMXT_BUILTIN2 (lshrv2si3, WSRLWI)
11692 IWMMXT_BUILTIN2 (lshrdi3_di, WSRLD)
11693 IWMMXT_BUILTIN2 (lshrdi3_iwmmxt, WSRLDI)
11694 IWMMXT_BUILTIN2 (ashrv4hi3_di, WSRAH)
11695 IWMMXT_BUILTIN2 (ashrv4hi3, WSRAHI)
11696 IWMMXT_BUILTIN2 (ashrv2si3_di, WSRAW)
11697 IWMMXT_BUILTIN2 (ashrv2si3, WSRAWI)
11698 IWMMXT_BUILTIN2 (ashrdi3_di, WSRAD)
11699 IWMMXT_BUILTIN2 (ashrdi3_iwmmxt, WSRADI)
11700 IWMMXT_BUILTIN2 (rorv4hi3_di, WRORH)
11701 IWMMXT_BUILTIN2 (rorv4hi3, WRORHI)
11702 IWMMXT_BUILTIN2 (rorv2si3_di, WRORW)
11703 IWMMXT_BUILTIN2 (rorv2si3, WRORWI)
11704 IWMMXT_BUILTIN2 (rordi3_di, WRORD)
11705 IWMMXT_BUILTIN2 (rordi3, WRORDI)
11706 IWMMXT_BUILTIN2 (iwmmxt_wmacuz, WMACUZ)
11707 IWMMXT_BUILTIN2 (iwmmxt_wmacsz, WMACSZ)
11710 static const struct builtin_description bdesc_1arg[] =
11712 IWMMXT_BUILTIN (iwmmxt_tmovmskb, "tmovmskb", TMOVMSKB)
11713 IWMMXT_BUILTIN (iwmmxt_tmovmskh, "tmovmskh", TMOVMSKH)
11714 IWMMXT_BUILTIN (iwmmxt_tmovmskw, "tmovmskw", TMOVMSKW)
11715 IWMMXT_BUILTIN (iwmmxt_waccb, "waccb", WACCB)
11716 IWMMXT_BUILTIN (iwmmxt_wacch, "wacch", WACCH)
11717 IWMMXT_BUILTIN (iwmmxt_waccw, "waccw", WACCW)
11718 IWMMXT_BUILTIN (iwmmxt_wunpckehub, "wunpckehub", WUNPCKEHUB)
11719 IWMMXT_BUILTIN (iwmmxt_wunpckehuh, "wunpckehuh", WUNPCKEHUH)
11720 IWMMXT_BUILTIN (iwmmxt_wunpckehuw, "wunpckehuw", WUNPCKEHUW)
11721 IWMMXT_BUILTIN (iwmmxt_wunpckehsb, "wunpckehsb", WUNPCKEHSB)
11722 IWMMXT_BUILTIN (iwmmxt_wunpckehsh, "wunpckehsh", WUNPCKEHSH)
11723 IWMMXT_BUILTIN (iwmmxt_wunpckehsw, "wunpckehsw", WUNPCKEHSW)
11724 IWMMXT_BUILTIN (iwmmxt_wunpckelub, "wunpckelub", WUNPCKELUB)
11725 IWMMXT_BUILTIN (iwmmxt_wunpckeluh, "wunpckeluh", WUNPCKELUH)
11726 IWMMXT_BUILTIN (iwmmxt_wunpckeluw, "wunpckeluw", WUNPCKELUW)
11727 IWMMXT_BUILTIN (iwmmxt_wunpckelsb, "wunpckelsb", WUNPCKELSB)
11728 IWMMXT_BUILTIN (iwmmxt_wunpckelsh, "wunpckelsh", WUNPCKELSH)
11729 IWMMXT_BUILTIN (iwmmxt_wunpckelsw, "wunpckelsw", WUNPCKELSW)
11732 /* Set up all the iWMMXt builtins. This is
11733 not called if TARGET_IWMMXT is zero. */
11736 arm_init_iwmmxt_builtins (void)
11738 const struct builtin_description * d;
11740 tree endlink = void_list_node;
11742 tree V2SI_type_node = build_vector_type_for_mode (intSI_type_node, V2SImode);
11743 tree V4HI_type_node = build_vector_type_for_mode (intHI_type_node, V4HImode);
11744 tree V8QI_type_node = build_vector_type_for_mode (intQI_type_node, V8QImode);
11747 = build_function_type (integer_type_node,
11748 tree_cons (NULL_TREE, integer_type_node, endlink));
11749 tree v8qi_ftype_v8qi_v8qi_int
11750 = build_function_type (V8QI_type_node,
11751 tree_cons (NULL_TREE, V8QI_type_node,
11752 tree_cons (NULL_TREE, V8QI_type_node,
11753 tree_cons (NULL_TREE,
11756 tree v4hi_ftype_v4hi_int
11757 = build_function_type (V4HI_type_node,
11758 tree_cons (NULL_TREE, V4HI_type_node,
11759 tree_cons (NULL_TREE, integer_type_node,
11761 tree v2si_ftype_v2si_int
11762 = build_function_type (V2SI_type_node,
11763 tree_cons (NULL_TREE, V2SI_type_node,
11764 tree_cons (NULL_TREE, integer_type_node,
11766 tree v2si_ftype_di_di
11767 = build_function_type (V2SI_type_node,
11768 tree_cons (NULL_TREE, long_long_integer_type_node,
11769 tree_cons (NULL_TREE, long_long_integer_type_node,
11771 tree di_ftype_di_int
11772 = build_function_type (long_long_integer_type_node,
11773 tree_cons (NULL_TREE, long_long_integer_type_node,
11774 tree_cons (NULL_TREE, integer_type_node,
11776 tree di_ftype_di_int_int
11777 = build_function_type (long_long_integer_type_node,
11778 tree_cons (NULL_TREE, long_long_integer_type_node,
11779 tree_cons (NULL_TREE, integer_type_node,
11780 tree_cons (NULL_TREE,
11783 tree int_ftype_v8qi
11784 = build_function_type (integer_type_node,
11785 tree_cons (NULL_TREE, V8QI_type_node,
11787 tree int_ftype_v4hi
11788 = build_function_type (integer_type_node,
11789 tree_cons (NULL_TREE, V4HI_type_node,
11791 tree int_ftype_v2si
11792 = build_function_type (integer_type_node,
11793 tree_cons (NULL_TREE, V2SI_type_node,
11795 tree int_ftype_v8qi_int
11796 = build_function_type (integer_type_node,
11797 tree_cons (NULL_TREE, V8QI_type_node,
11798 tree_cons (NULL_TREE, integer_type_node,
11800 tree int_ftype_v4hi_int
11801 = build_function_type (integer_type_node,
11802 tree_cons (NULL_TREE, V4HI_type_node,
11803 tree_cons (NULL_TREE, integer_type_node,
11805 tree int_ftype_v2si_int
11806 = build_function_type (integer_type_node,
11807 tree_cons (NULL_TREE, V2SI_type_node,
11808 tree_cons (NULL_TREE, integer_type_node,
11810 tree v8qi_ftype_v8qi_int_int
11811 = build_function_type (V8QI_type_node,
11812 tree_cons (NULL_TREE, V8QI_type_node,
11813 tree_cons (NULL_TREE, integer_type_node,
11814 tree_cons (NULL_TREE,
11817 tree v4hi_ftype_v4hi_int_int
11818 = build_function_type (V4HI_type_node,
11819 tree_cons (NULL_TREE, V4HI_type_node,
11820 tree_cons (NULL_TREE, integer_type_node,
11821 tree_cons (NULL_TREE,
11824 tree v2si_ftype_v2si_int_int
11825 = build_function_type (V2SI_type_node,
11826 tree_cons (NULL_TREE, V2SI_type_node,
11827 tree_cons (NULL_TREE, integer_type_node,
11828 tree_cons (NULL_TREE,
11831 /* Miscellaneous. */
11832 tree v8qi_ftype_v4hi_v4hi
11833 = build_function_type (V8QI_type_node,
11834 tree_cons (NULL_TREE, V4HI_type_node,
11835 tree_cons (NULL_TREE, V4HI_type_node,
11837 tree v4hi_ftype_v2si_v2si
11838 = build_function_type (V4HI_type_node,
11839 tree_cons (NULL_TREE, V2SI_type_node,
11840 tree_cons (NULL_TREE, V2SI_type_node,
11842 tree v2si_ftype_v4hi_v4hi
11843 = build_function_type (V2SI_type_node,
11844 tree_cons (NULL_TREE, V4HI_type_node,
11845 tree_cons (NULL_TREE, V4HI_type_node,
11847 tree v2si_ftype_v8qi_v8qi
11848 = build_function_type (V2SI_type_node,
11849 tree_cons (NULL_TREE, V8QI_type_node,
11850 tree_cons (NULL_TREE, V8QI_type_node,
11852 tree v4hi_ftype_v4hi_di
11853 = build_function_type (V4HI_type_node,
11854 tree_cons (NULL_TREE, V4HI_type_node,
11855 tree_cons (NULL_TREE,
11856 long_long_integer_type_node,
11858 tree v2si_ftype_v2si_di
11859 = build_function_type (V2SI_type_node,
11860 tree_cons (NULL_TREE, V2SI_type_node,
11861 tree_cons (NULL_TREE,
11862 long_long_integer_type_node,
11864 tree void_ftype_int_int
11865 = build_function_type (void_type_node,
11866 tree_cons (NULL_TREE, integer_type_node,
11867 tree_cons (NULL_TREE, integer_type_node,
11870 = build_function_type (long_long_unsigned_type_node, endlink);
11872 = build_function_type (long_long_integer_type_node,
11873 tree_cons (NULL_TREE, V8QI_type_node,
11876 = build_function_type (long_long_integer_type_node,
11877 tree_cons (NULL_TREE, V4HI_type_node,
11880 = build_function_type (long_long_integer_type_node,
11881 tree_cons (NULL_TREE, V2SI_type_node,
11883 tree v2si_ftype_v4hi
11884 = build_function_type (V2SI_type_node,
11885 tree_cons (NULL_TREE, V4HI_type_node,
11887 tree v4hi_ftype_v8qi
11888 = build_function_type (V4HI_type_node,
11889 tree_cons (NULL_TREE, V8QI_type_node,
11892 tree di_ftype_di_v4hi_v4hi
11893 = build_function_type (long_long_unsigned_type_node,
11894 tree_cons (NULL_TREE,
11895 long_long_unsigned_type_node,
11896 tree_cons (NULL_TREE, V4HI_type_node,
11897 tree_cons (NULL_TREE,
11901 tree di_ftype_v4hi_v4hi
11902 = build_function_type (long_long_unsigned_type_node,
11903 tree_cons (NULL_TREE, V4HI_type_node,
11904 tree_cons (NULL_TREE, V4HI_type_node,
11907 /* Normal vector binops. */
11908 tree v8qi_ftype_v8qi_v8qi
11909 = build_function_type (V8QI_type_node,
11910 tree_cons (NULL_TREE, V8QI_type_node,
11911 tree_cons (NULL_TREE, V8QI_type_node,
11913 tree v4hi_ftype_v4hi_v4hi
11914 = build_function_type (V4HI_type_node,
11915 tree_cons (NULL_TREE, V4HI_type_node,
11916 tree_cons (NULL_TREE, V4HI_type_node,
11918 tree v2si_ftype_v2si_v2si
11919 = build_function_type (V2SI_type_node,
11920 tree_cons (NULL_TREE, V2SI_type_node,
11921 tree_cons (NULL_TREE, V2SI_type_node,
11923 tree di_ftype_di_di
11924 = build_function_type (long_long_unsigned_type_node,
11925 tree_cons (NULL_TREE, long_long_unsigned_type_node,
11926 tree_cons (NULL_TREE,
11927 long_long_unsigned_type_node,
11930 /* Add all builtins that are more or less simple operations on two
11932 for (i = 0, d = bdesc_2arg; i < ARRAY_SIZE (bdesc_2arg); i++, d++)
11934 /* Use one of the operands; the target can have a different mode for
11935 mask-generating compares. */
11936 enum machine_mode mode;
11942 mode = insn_data[d->icode].operand[1].mode;
11947 type = v8qi_ftype_v8qi_v8qi;
11950 type = v4hi_ftype_v4hi_v4hi;
11953 type = v2si_ftype_v2si_v2si;
11956 type = di_ftype_di_di;
11963 def_mbuiltin (d->mask, d->name, type, d->code);
11966 /* Add the remaining MMX insns with somewhat more complicated types. */
11967 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wzero", di_ftype_void, ARM_BUILTIN_WZERO);
11968 def_mbuiltin (FL_IWMMXT, "__builtin_arm_setwcx", void_ftype_int_int, ARM_BUILTIN_SETWCX);
11969 def_mbuiltin (FL_IWMMXT, "__builtin_arm_getwcx", int_ftype_int, ARM_BUILTIN_GETWCX);
11971 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsllh", v4hi_ftype_v4hi_di, ARM_BUILTIN_WSLLH);
11972 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsllw", v2si_ftype_v2si_di, ARM_BUILTIN_WSLLW);
11973 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wslld", di_ftype_di_di, ARM_BUILTIN_WSLLD);
11974 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsllhi", v4hi_ftype_v4hi_int, ARM_BUILTIN_WSLLHI);
11975 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsllwi", v2si_ftype_v2si_int, ARM_BUILTIN_WSLLWI);
11976 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wslldi", di_ftype_di_int, ARM_BUILTIN_WSLLDI);
11978 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrlh", v4hi_ftype_v4hi_di, ARM_BUILTIN_WSRLH);
11979 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrlw", v2si_ftype_v2si_di, ARM_BUILTIN_WSRLW);
11980 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrld", di_ftype_di_di, ARM_BUILTIN_WSRLD);
11981 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrlhi", v4hi_ftype_v4hi_int, ARM_BUILTIN_WSRLHI);
11982 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrlwi", v2si_ftype_v2si_int, ARM_BUILTIN_WSRLWI);
11983 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrldi", di_ftype_di_int, ARM_BUILTIN_WSRLDI);
11985 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrah", v4hi_ftype_v4hi_di, ARM_BUILTIN_WSRAH);
11986 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsraw", v2si_ftype_v2si_di, ARM_BUILTIN_WSRAW);
11987 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrad", di_ftype_di_di, ARM_BUILTIN_WSRAD);
11988 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrahi", v4hi_ftype_v4hi_int, ARM_BUILTIN_WSRAHI);
11989 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrawi", v2si_ftype_v2si_int, ARM_BUILTIN_WSRAWI);
11990 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsradi", di_ftype_di_int, ARM_BUILTIN_WSRADI);
11992 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wrorh", v4hi_ftype_v4hi_di, ARM_BUILTIN_WRORH);
11993 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wrorw", v2si_ftype_v2si_di, ARM_BUILTIN_WRORW);
11994 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wrord", di_ftype_di_di, ARM_BUILTIN_WRORD);
11995 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wrorhi", v4hi_ftype_v4hi_int, ARM_BUILTIN_WRORHI);
11996 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wrorwi", v2si_ftype_v2si_int, ARM_BUILTIN_WRORWI);
11997 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wrordi", di_ftype_di_int, ARM_BUILTIN_WRORDI);
11999 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wshufh", v4hi_ftype_v4hi_int, ARM_BUILTIN_WSHUFH);
12001 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsadb", v2si_ftype_v8qi_v8qi, ARM_BUILTIN_WSADB);
12002 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsadh", v2si_ftype_v4hi_v4hi, ARM_BUILTIN_WSADH);
12003 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsadbz", v2si_ftype_v8qi_v8qi, ARM_BUILTIN_WSADBZ);
12004 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsadhz", v2si_ftype_v4hi_v4hi, ARM_BUILTIN_WSADHZ);
12006 def_mbuiltin (FL_IWMMXT, "__builtin_arm_textrmsb", int_ftype_v8qi_int, ARM_BUILTIN_TEXTRMSB);
12007 def_mbuiltin (FL_IWMMXT, "__builtin_arm_textrmsh", int_ftype_v4hi_int, ARM_BUILTIN_TEXTRMSH);
12008 def_mbuiltin (FL_IWMMXT, "__builtin_arm_textrmsw", int_ftype_v2si_int, ARM_BUILTIN_TEXTRMSW);
12009 def_mbuiltin (FL_IWMMXT, "__builtin_arm_textrmub", int_ftype_v8qi_int, ARM_BUILTIN_TEXTRMUB);
12010 def_mbuiltin (FL_IWMMXT, "__builtin_arm_textrmuh", int_ftype_v4hi_int, ARM_BUILTIN_TEXTRMUH);
12011 def_mbuiltin (FL_IWMMXT, "__builtin_arm_textrmuw", int_ftype_v2si_int, ARM_BUILTIN_TEXTRMUW);
12012 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tinsrb", v8qi_ftype_v8qi_int_int, ARM_BUILTIN_TINSRB);
12013 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tinsrh", v4hi_ftype_v4hi_int_int, ARM_BUILTIN_TINSRH);
12014 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tinsrw", v2si_ftype_v2si_int_int, ARM_BUILTIN_TINSRW);
12016 def_mbuiltin (FL_IWMMXT, "__builtin_arm_waccb", di_ftype_v8qi, ARM_BUILTIN_WACCB);
12017 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wacch", di_ftype_v4hi, ARM_BUILTIN_WACCH);
12018 def_mbuiltin (FL_IWMMXT, "__builtin_arm_waccw", di_ftype_v2si, ARM_BUILTIN_WACCW);
12020 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmovmskb", int_ftype_v8qi, ARM_BUILTIN_TMOVMSKB);
12021 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmovmskh", int_ftype_v4hi, ARM_BUILTIN_TMOVMSKH);
12022 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmovmskw", int_ftype_v2si, ARM_BUILTIN_TMOVMSKW);
12024 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wpackhss", v8qi_ftype_v4hi_v4hi, ARM_BUILTIN_WPACKHSS);
12025 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wpackhus", v8qi_ftype_v4hi_v4hi, ARM_BUILTIN_WPACKHUS);
12026 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wpackwus", v4hi_ftype_v2si_v2si, ARM_BUILTIN_WPACKWUS);
12027 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wpackwss", v4hi_ftype_v2si_v2si, ARM_BUILTIN_WPACKWSS);
12028 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wpackdus", v2si_ftype_di_di, ARM_BUILTIN_WPACKDUS);
12029 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wpackdss", v2si_ftype_di_di, ARM_BUILTIN_WPACKDSS);
12031 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckehub", v4hi_ftype_v8qi, ARM_BUILTIN_WUNPCKEHUB);
12032 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckehuh", v2si_ftype_v4hi, ARM_BUILTIN_WUNPCKEHUH);
12033 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckehuw", di_ftype_v2si, ARM_BUILTIN_WUNPCKEHUW);
12034 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckehsb", v4hi_ftype_v8qi, ARM_BUILTIN_WUNPCKEHSB);
12035 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckehsh", v2si_ftype_v4hi, ARM_BUILTIN_WUNPCKEHSH);
12036 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckehsw", di_ftype_v2si, ARM_BUILTIN_WUNPCKEHSW);
12037 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckelub", v4hi_ftype_v8qi, ARM_BUILTIN_WUNPCKELUB);
12038 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckeluh", v2si_ftype_v4hi, ARM_BUILTIN_WUNPCKELUH);
12039 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckeluw", di_ftype_v2si, ARM_BUILTIN_WUNPCKELUW);
12040 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckelsb", v4hi_ftype_v8qi, ARM_BUILTIN_WUNPCKELSB);
12041 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckelsh", v2si_ftype_v4hi, ARM_BUILTIN_WUNPCKELSH);
12042 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckelsw", di_ftype_v2si, ARM_BUILTIN_WUNPCKELSW);
12044 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wmacs", di_ftype_di_v4hi_v4hi, ARM_BUILTIN_WMACS);
12045 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wmacsz", di_ftype_v4hi_v4hi, ARM_BUILTIN_WMACSZ);
12046 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wmacu", di_ftype_di_v4hi_v4hi, ARM_BUILTIN_WMACU);
12047 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wmacuz", di_ftype_v4hi_v4hi, ARM_BUILTIN_WMACUZ);
12049 def_mbuiltin (FL_IWMMXT, "__builtin_arm_walign", v8qi_ftype_v8qi_v8qi_int, ARM_BUILTIN_WALIGN);
12050 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmia", di_ftype_di_int_int, ARM_BUILTIN_TMIA);
12051 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmiaph", di_ftype_di_int_int, ARM_BUILTIN_TMIAPH);
12052 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmiabb", di_ftype_di_int_int, ARM_BUILTIN_TMIABB);
12053 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmiabt", di_ftype_di_int_int, ARM_BUILTIN_TMIABT);
12054 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmiatb", di_ftype_di_int_int, ARM_BUILTIN_TMIATB);
12055 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmiatt", di_ftype_di_int_int, ARM_BUILTIN_TMIATT);
12059 arm_init_builtins (void)
12061 if (TARGET_REALLY_IWMMXT)
12062 arm_init_iwmmxt_builtins ();
12065 /* Errors in the source file can cause expand_expr to return const0_rtx
12066 where we expect a vector. To avoid crashing, use one of the vector
12067 clear instructions. */
12070 safe_vector_operand (rtx x, enum machine_mode mode)
12072 if (x != const0_rtx)
12074 x = gen_reg_rtx (mode);
12076 emit_insn (gen_iwmmxt_clrdi (mode == DImode ? x
12077 : gen_rtx_SUBREG (DImode, x, 0)));
12081 /* Subroutine of arm_expand_builtin to take care of binop insns. */
12084 arm_expand_binop_builtin (enum insn_code icode,
12085 tree arglist, rtx target)
12088 tree arg0 = TREE_VALUE (arglist);
12089 tree arg1 = TREE_VALUE (TREE_CHAIN (arglist));
12090 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
12091 rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
12092 enum machine_mode tmode = insn_data[icode].operand[0].mode;
12093 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
12094 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
12096 if (VECTOR_MODE_P (mode0))
12097 op0 = safe_vector_operand (op0, mode0);
12098 if (VECTOR_MODE_P (mode1))
12099 op1 = safe_vector_operand (op1, mode1);
12102 || GET_MODE (target) != tmode
12103 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
12104 target = gen_reg_rtx (tmode);
12106 /* In case the insn wants input operands in modes different from
12107 the result, abort. */
12108 if (GET_MODE (op0) != mode0 || GET_MODE (op1) != mode1)
12111 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
12112 op0 = copy_to_mode_reg (mode0, op0);
12113 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
12114 op1 = copy_to_mode_reg (mode1, op1);
12116 pat = GEN_FCN (icode) (target, op0, op1);
12123 /* Subroutine of arm_expand_builtin to take care of unop insns. */
12126 arm_expand_unop_builtin (enum insn_code icode,
12127 tree arglist, rtx target, int do_load)
12130 tree arg0 = TREE_VALUE (arglist);
12131 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
12132 enum machine_mode tmode = insn_data[icode].operand[0].mode;
12133 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
12136 || GET_MODE (target) != tmode
12137 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
12138 target = gen_reg_rtx (tmode);
12140 op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0));
12143 if (VECTOR_MODE_P (mode0))
12144 op0 = safe_vector_operand (op0, mode0);
12146 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
12147 op0 = copy_to_mode_reg (mode0, op0);
12150 pat = GEN_FCN (icode) (target, op0);
12157 /* Expand an expression EXP that calls a built-in function,
12158 with result going to TARGET if that's convenient
12159 (and in mode MODE if that's convenient).
12160 SUBTARGET may be used as the target for computing one of EXP's operands.
12161 IGNORE is nonzero if the value is to be ignored. */
12164 arm_expand_builtin (tree exp,
12166 rtx subtarget ATTRIBUTE_UNUSED,
12167 enum machine_mode mode ATTRIBUTE_UNUSED,
12168 int ignore ATTRIBUTE_UNUSED)
12170 const struct builtin_description * d;
12171 enum insn_code icode;
12172 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
12173 tree arglist = TREE_OPERAND (exp, 1);
12181 int fcode = DECL_FUNCTION_CODE (fndecl);
12183 enum machine_mode tmode;
12184 enum machine_mode mode0;
12185 enum machine_mode mode1;
12186 enum machine_mode mode2;
12190 case ARM_BUILTIN_TEXTRMSB:
12191 case ARM_BUILTIN_TEXTRMUB:
12192 case ARM_BUILTIN_TEXTRMSH:
12193 case ARM_BUILTIN_TEXTRMUH:
12194 case ARM_BUILTIN_TEXTRMSW:
12195 case ARM_BUILTIN_TEXTRMUW:
12196 icode = (fcode == ARM_BUILTIN_TEXTRMSB ? CODE_FOR_iwmmxt_textrmsb
12197 : fcode == ARM_BUILTIN_TEXTRMUB ? CODE_FOR_iwmmxt_textrmub
12198 : fcode == ARM_BUILTIN_TEXTRMSH ? CODE_FOR_iwmmxt_textrmsh
12199 : fcode == ARM_BUILTIN_TEXTRMUH ? CODE_FOR_iwmmxt_textrmuh
12200 : CODE_FOR_iwmmxt_textrmw);
12202 arg0 = TREE_VALUE (arglist);
12203 arg1 = TREE_VALUE (TREE_CHAIN (arglist));
12204 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
12205 op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
12206 tmode = insn_data[icode].operand[0].mode;
12207 mode0 = insn_data[icode].operand[1].mode;
12208 mode1 = insn_data[icode].operand[2].mode;
12210 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
12211 op0 = copy_to_mode_reg (mode0, op0);
12212 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
12214 /* @@@ better error message */
12215 error ("selector must be an immediate");
12216 return gen_reg_rtx (tmode);
12219 || GET_MODE (target) != tmode
12220 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
12221 target = gen_reg_rtx (tmode);
12222 pat = GEN_FCN (icode) (target, op0, op1);
12228 case ARM_BUILTIN_TINSRB:
12229 case ARM_BUILTIN_TINSRH:
12230 case ARM_BUILTIN_TINSRW:
12231 icode = (fcode == ARM_BUILTIN_TINSRB ? CODE_FOR_iwmmxt_tinsrb
12232 : fcode == ARM_BUILTIN_TINSRH ? CODE_FOR_iwmmxt_tinsrh
12233 : CODE_FOR_iwmmxt_tinsrw);
12234 arg0 = TREE_VALUE (arglist);
12235 arg1 = TREE_VALUE (TREE_CHAIN (arglist));
12236 arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
12237 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
12238 op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
12239 op2 = expand_expr (arg2, NULL_RTX, VOIDmode, 0);
12240 tmode = insn_data[icode].operand[0].mode;
12241 mode0 = insn_data[icode].operand[1].mode;
12242 mode1 = insn_data[icode].operand[2].mode;
12243 mode2 = insn_data[icode].operand[3].mode;
12245 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
12246 op0 = copy_to_mode_reg (mode0, op0);
12247 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
12248 op1 = copy_to_mode_reg (mode1, op1);
12249 if (! (*insn_data[icode].operand[3].predicate) (op2, mode2))
12251 /* @@@ better error message */
12252 error ("selector must be an immediate");
12256 || GET_MODE (target) != tmode
12257 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
12258 target = gen_reg_rtx (tmode);
12259 pat = GEN_FCN (icode) (target, op0, op1, op2);
12265 case ARM_BUILTIN_SETWCX:
12266 arg0 = TREE_VALUE (arglist);
12267 arg1 = TREE_VALUE (TREE_CHAIN (arglist));
12268 op0 = force_reg (SImode, expand_expr (arg0, NULL_RTX, VOIDmode, 0));
12269 op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
12270 emit_insn (gen_iwmmxt_tmcr (op1, op0));
12273 case ARM_BUILTIN_GETWCX:
12274 arg0 = TREE_VALUE (arglist);
12275 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
12276 target = gen_reg_rtx (SImode);
12277 emit_insn (gen_iwmmxt_tmrc (target, op0));
12280 case ARM_BUILTIN_WSHUFH:
12281 icode = CODE_FOR_iwmmxt_wshufh;
12282 arg0 = TREE_VALUE (arglist);
12283 arg1 = TREE_VALUE (TREE_CHAIN (arglist));
12284 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
12285 op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
12286 tmode = insn_data[icode].operand[0].mode;
12287 mode1 = insn_data[icode].operand[1].mode;
12288 mode2 = insn_data[icode].operand[2].mode;
12290 if (! (*insn_data[icode].operand[1].predicate) (op0, mode1))
12291 op0 = copy_to_mode_reg (mode1, op0);
12292 if (! (*insn_data[icode].operand[2].predicate) (op1, mode2))
12294 /* @@@ better error message */
12295 error ("mask must be an immediate");
12299 || GET_MODE (target) != tmode
12300 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
12301 target = gen_reg_rtx (tmode);
12302 pat = GEN_FCN (icode) (target, op0, op1);
12308 case ARM_BUILTIN_WSADB:
12309 return arm_expand_binop_builtin (CODE_FOR_iwmmxt_wsadb, arglist, target);
12310 case ARM_BUILTIN_WSADH:
12311 return arm_expand_binop_builtin (CODE_FOR_iwmmxt_wsadh, arglist, target);
12312 case ARM_BUILTIN_WSADBZ:
12313 return arm_expand_binop_builtin (CODE_FOR_iwmmxt_wsadbz, arglist, target);
12314 case ARM_BUILTIN_WSADHZ:
12315 return arm_expand_binop_builtin (CODE_FOR_iwmmxt_wsadhz, arglist, target);
12317 /* Several three-argument builtins. */
12318 case ARM_BUILTIN_WMACS:
12319 case ARM_BUILTIN_WMACU:
12320 case ARM_BUILTIN_WALIGN:
12321 case ARM_BUILTIN_TMIA:
12322 case ARM_BUILTIN_TMIAPH:
12323 case ARM_BUILTIN_TMIATT:
12324 case ARM_BUILTIN_TMIATB:
12325 case ARM_BUILTIN_TMIABT:
12326 case ARM_BUILTIN_TMIABB:
12327 icode = (fcode == ARM_BUILTIN_WMACS ? CODE_FOR_iwmmxt_wmacs
12328 : fcode == ARM_BUILTIN_WMACU ? CODE_FOR_iwmmxt_wmacu
12329 : fcode == ARM_BUILTIN_TMIA ? CODE_FOR_iwmmxt_tmia
12330 : fcode == ARM_BUILTIN_TMIAPH ? CODE_FOR_iwmmxt_tmiaph
12331 : fcode == ARM_BUILTIN_TMIABB ? CODE_FOR_iwmmxt_tmiabb
12332 : fcode == ARM_BUILTIN_TMIABT ? CODE_FOR_iwmmxt_tmiabt
12333 : fcode == ARM_BUILTIN_TMIATB ? CODE_FOR_iwmmxt_tmiatb
12334 : fcode == ARM_BUILTIN_TMIATT ? CODE_FOR_iwmmxt_tmiatt
12335 : CODE_FOR_iwmmxt_walign);
12336 arg0 = TREE_VALUE (arglist);
12337 arg1 = TREE_VALUE (TREE_CHAIN (arglist));
12338 arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
12339 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
12340 op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
12341 op2 = expand_expr (arg2, NULL_RTX, VOIDmode, 0);
12342 tmode = insn_data[icode].operand[0].mode;
12343 mode0 = insn_data[icode].operand[1].mode;
12344 mode1 = insn_data[icode].operand[2].mode;
12345 mode2 = insn_data[icode].operand[3].mode;
12347 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
12348 op0 = copy_to_mode_reg (mode0, op0);
12349 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
12350 op1 = copy_to_mode_reg (mode1, op1);
12351 if (! (*insn_data[icode].operand[3].predicate) (op2, mode2))
12352 op2 = copy_to_mode_reg (mode2, op2);
12354 || GET_MODE (target) != tmode
12355 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
12356 target = gen_reg_rtx (tmode);
12357 pat = GEN_FCN (icode) (target, op0, op1, op2);
12363 case ARM_BUILTIN_WZERO:
12364 target = gen_reg_rtx (DImode);
12365 emit_insn (gen_iwmmxt_clrdi (target));
12372 for (i = 0, d = bdesc_2arg; i < ARRAY_SIZE (bdesc_2arg); i++, d++)
12373 if (d->code == (const enum arm_builtins) fcode)
12374 return arm_expand_binop_builtin (d->icode, arglist, target);
12376 for (i = 0, d = bdesc_1arg; i < ARRAY_SIZE (bdesc_1arg); i++, d++)
12377 if (d->code == (const enum arm_builtins) fcode)
12378 return arm_expand_unop_builtin (d->icode, arglist, target, 0);
12380 /* @@@ Should really do something sensible here. */
12384 /* Recursively search through all of the blocks in a function
12385 checking to see if any of the variables created in that
12386 function match the RTX called 'orig'. If they do then
12387 replace them with the RTX called 'new'. */
12389 replace_symbols_in_block (tree block, rtx orig, rtx new)
12391 for (; block; block = BLOCK_CHAIN (block))
12395 if (!TREE_USED (block))
12398 for (sym = BLOCK_VARS (block); sym; sym = TREE_CHAIN (sym))
12400 if ( (DECL_NAME (sym) == 0 && TREE_CODE (sym) != TYPE_DECL)
12401 || DECL_IGNORED_P (sym)
12402 || TREE_CODE (sym) != VAR_DECL
12403 || DECL_EXTERNAL (sym)
12404 || !rtx_equal_p (DECL_RTL (sym), orig)
12408 SET_DECL_RTL (sym, new);
12411 replace_symbols_in_block (BLOCK_SUBBLOCKS (block), orig, new);
12415 /* Return the number (counting from 0) of
12416 the least significant set bit in MASK. */
12419 number_of_first_bit_set (int mask)
12424 (mask & (1 << bit)) == 0;
12431 /* Generate code to return from a thumb function.
12432 If 'reg_containing_return_addr' is -1, then the return address is
12433 actually on the stack, at the stack pointer. */
12435 thumb_exit (FILE *f, int reg_containing_return_addr, rtx eh_ofs)
12437 unsigned regs_available_for_popping;
12438 unsigned regs_to_pop;
12440 unsigned available;
12444 int restore_a4 = FALSE;
12446 /* Compute the registers we need to pop. */
12450 /* There is an assumption here, that if eh_ofs is not NULL, the
12451 normal return address will have been pushed. */
12452 if (reg_containing_return_addr == -1 || eh_ofs)
12454 /* When we are generating a return for __builtin_eh_return,
12455 reg_containing_return_addr must specify the return regno. */
12456 if (eh_ofs && reg_containing_return_addr == -1)
12459 regs_to_pop |= 1 << LR_REGNUM;
12463 if (TARGET_BACKTRACE)
12465 /* Restore the (ARM) frame pointer and stack pointer. */
12466 regs_to_pop |= (1 << ARM_HARD_FRAME_POINTER_REGNUM) | (1 << SP_REGNUM);
12470 /* If there is nothing to pop then just emit the BX instruction and
12472 if (pops_needed == 0)
12475 asm_fprintf (f, "\tadd\t%r, %r\n", SP_REGNUM, REGNO (eh_ofs));
12477 asm_fprintf (f, "\tbx\t%r\n", reg_containing_return_addr);
12480 /* Otherwise if we are not supporting interworking and we have not created
12481 a backtrace structure and the function was not entered in ARM mode then
12482 just pop the return address straight into the PC. */
12483 else if (!TARGET_INTERWORK
12484 && !TARGET_BACKTRACE
12485 && !is_called_in_ARM_mode (current_function_decl))
12489 asm_fprintf (f, "\tadd\t%r, #4\n", SP_REGNUM);
12490 asm_fprintf (f, "\tadd\t%r, %r\n", SP_REGNUM, REGNO (eh_ofs));
12491 asm_fprintf (f, "\tbx\t%r\n", reg_containing_return_addr);
12494 asm_fprintf (f, "\tpop\t{%r}\n", PC_REGNUM);
12499 /* Find out how many of the (return) argument registers we can corrupt. */
12500 regs_available_for_popping = 0;
12502 /* If returning via __builtin_eh_return, the bottom three registers
12503 all contain information needed for the return. */
12508 /* If we can deduce the registers used from the function's
12509 return value. This is more reliable that examining
12510 regs_ever_live[] because that will be set if the register is
12511 ever used in the function, not just if the register is used
12512 to hold a return value. */
12514 if (current_function_return_rtx != 0)
12515 mode = GET_MODE (current_function_return_rtx);
12517 mode = DECL_MODE (DECL_RESULT (current_function_decl));
12519 size = GET_MODE_SIZE (mode);
12523 /* In a void function we can use any argument register.
12524 In a function that returns a structure on the stack
12525 we can use the second and third argument registers. */
12526 if (mode == VOIDmode)
12527 regs_available_for_popping =
12528 (1 << ARG_REGISTER (1))
12529 | (1 << ARG_REGISTER (2))
12530 | (1 << ARG_REGISTER (3));
12532 regs_available_for_popping =
12533 (1 << ARG_REGISTER (2))
12534 | (1 << ARG_REGISTER (3));
12536 else if (size <= 4)
12537 regs_available_for_popping =
12538 (1 << ARG_REGISTER (2))
12539 | (1 << ARG_REGISTER (3));
12540 else if (size <= 8)
12541 regs_available_for_popping =
12542 (1 << ARG_REGISTER (3));
12545 /* Match registers to be popped with registers into which we pop them. */
12546 for (available = regs_available_for_popping,
12547 required = regs_to_pop;
12548 required != 0 && available != 0;
12549 available &= ~(available & - available),
12550 required &= ~(required & - required))
12553 /* If we have any popping registers left over, remove them. */
12555 regs_available_for_popping &= ~available;
12557 /* Otherwise if we need another popping register we can use
12558 the fourth argument register. */
12559 else if (pops_needed)
12561 /* If we have not found any free argument registers and
12562 reg a4 contains the return address, we must move it. */
12563 if (regs_available_for_popping == 0
12564 && reg_containing_return_addr == LAST_ARG_REGNUM)
12566 asm_fprintf (f, "\tmov\t%r, %r\n", LR_REGNUM, LAST_ARG_REGNUM);
12567 reg_containing_return_addr = LR_REGNUM;
12569 else if (size > 12)
12571 /* Register a4 is being used to hold part of the return value,
12572 but we have dire need of a free, low register. */
12575 asm_fprintf (f, "\tmov\t%r, %r\n",IP_REGNUM, LAST_ARG_REGNUM);
12578 if (reg_containing_return_addr != LAST_ARG_REGNUM)
12580 /* The fourth argument register is available. */
12581 regs_available_for_popping |= 1 << LAST_ARG_REGNUM;
12587 /* Pop as many registers as we can. */
12588 thumb_pushpop (f, regs_available_for_popping, FALSE, NULL,
12589 regs_available_for_popping);
12591 /* Process the registers we popped. */
12592 if (reg_containing_return_addr == -1)
12594 /* The return address was popped into the lowest numbered register. */
12595 regs_to_pop &= ~(1 << LR_REGNUM);
12597 reg_containing_return_addr =
12598 number_of_first_bit_set (regs_available_for_popping);
12600 /* Remove this register for the mask of available registers, so that
12601 the return address will not be corrupted by further pops. */
12602 regs_available_for_popping &= ~(1 << reg_containing_return_addr);
12605 /* If we popped other registers then handle them here. */
12606 if (regs_available_for_popping)
12610 /* Work out which register currently contains the frame pointer. */
12611 frame_pointer = number_of_first_bit_set (regs_available_for_popping);
12613 /* Move it into the correct place. */
12614 asm_fprintf (f, "\tmov\t%r, %r\n",
12615 ARM_HARD_FRAME_POINTER_REGNUM, frame_pointer);
12617 /* (Temporarily) remove it from the mask of popped registers. */
12618 regs_available_for_popping &= ~(1 << frame_pointer);
12619 regs_to_pop &= ~(1 << ARM_HARD_FRAME_POINTER_REGNUM);
12621 if (regs_available_for_popping)
12625 /* We popped the stack pointer as well,
12626 find the register that contains it. */
12627 stack_pointer = number_of_first_bit_set (regs_available_for_popping);
12629 /* Move it into the stack register. */
12630 asm_fprintf (f, "\tmov\t%r, %r\n", SP_REGNUM, stack_pointer);
12632 /* At this point we have popped all necessary registers, so
12633 do not worry about restoring regs_available_for_popping
12634 to its correct value:
12636 assert (pops_needed == 0)
12637 assert (regs_available_for_popping == (1 << frame_pointer))
12638 assert (regs_to_pop == (1 << STACK_POINTER)) */
12642 /* Since we have just move the popped value into the frame
12643 pointer, the popping register is available for reuse, and
12644 we know that we still have the stack pointer left to pop. */
12645 regs_available_for_popping |= (1 << frame_pointer);
12649 /* If we still have registers left on the stack, but we no longer have
12650 any registers into which we can pop them, then we must move the return
12651 address into the link register and make available the register that
12653 if (regs_available_for_popping == 0 && pops_needed > 0)
12655 regs_available_for_popping |= 1 << reg_containing_return_addr;
12657 asm_fprintf (f, "\tmov\t%r, %r\n", LR_REGNUM,
12658 reg_containing_return_addr);
12660 reg_containing_return_addr = LR_REGNUM;
12663 /* If we have registers left on the stack then pop some more.
12664 We know that at most we will want to pop FP and SP. */
12665 if (pops_needed > 0)
12670 thumb_pushpop (f, regs_available_for_popping, FALSE, NULL,
12671 regs_available_for_popping);
12673 /* We have popped either FP or SP.
12674 Move whichever one it is into the correct register. */
12675 popped_into = number_of_first_bit_set (regs_available_for_popping);
12676 move_to = number_of_first_bit_set (regs_to_pop);
12678 asm_fprintf (f, "\tmov\t%r, %r\n", move_to, popped_into);
12680 regs_to_pop &= ~(1 << move_to);
12685 /* If we still have not popped everything then we must have only
12686 had one register available to us and we are now popping the SP. */
12687 if (pops_needed > 0)
12691 thumb_pushpop (f, regs_available_for_popping, FALSE, NULL,
12692 regs_available_for_popping);
12694 popped_into = number_of_first_bit_set (regs_available_for_popping);
12696 asm_fprintf (f, "\tmov\t%r, %r\n", SP_REGNUM, popped_into);
12698 assert (regs_to_pop == (1 << STACK_POINTER))
12699 assert (pops_needed == 1)
12703 /* If necessary restore the a4 register. */
12706 if (reg_containing_return_addr != LR_REGNUM)
12708 asm_fprintf (f, "\tmov\t%r, %r\n", LR_REGNUM, LAST_ARG_REGNUM);
12709 reg_containing_return_addr = LR_REGNUM;
12712 asm_fprintf (f, "\tmov\t%r, %r\n", LAST_ARG_REGNUM, IP_REGNUM);
12716 asm_fprintf (f, "\tadd\t%r, %r\n", SP_REGNUM, REGNO (eh_ofs));
12718 /* Return to caller. */
12719 asm_fprintf (f, "\tbx\t%r\n", reg_containing_return_addr);
12722 /* Emit code to push or pop registers to or from the stack. F is the
12723 assembly file. MASK is the registers to push or pop. PUSH is
12724 nonzero if we should push, and zero if we should pop. For debugging
12725 output, if pushing, adjust CFA_OFFSET by the amount of space added
12726 to the stack. REAL_REGS should have the same number of bits set as
12727 MASK, and will be used instead (in the same order) to describe which
12728 registers were saved - this is used to mark the save slots when we
12729 push high registers after moving them to low registers. */
12731 thumb_pushpop (FILE *f, int mask, int push, int *cfa_offset, int real_regs)
12734 int lo_mask = mask & 0xFF;
12735 int pushed_words = 0;
12737 if (lo_mask == 0 && !push && (mask & (1 << 15)))
12739 /* Special case. Do not generate a POP PC statement here, do it in
12741 thumb_exit (f, -1, NULL_RTX);
12745 fprintf (f, "\t%s\t{", push ? "push" : "pop");
12747 /* Look at the low registers first. */
12748 for (regno = 0; regno <= LAST_LO_REGNUM; regno++, lo_mask >>= 1)
12752 asm_fprintf (f, "%r", regno);
12754 if ((lo_mask & ~1) != 0)
12761 if (push && (mask & (1 << LR_REGNUM)))
12763 /* Catch pushing the LR. */
12767 asm_fprintf (f, "%r", LR_REGNUM);
12771 else if (!push && (mask & (1 << PC_REGNUM)))
12773 /* Catch popping the PC. */
12774 if (TARGET_INTERWORK || TARGET_BACKTRACE)
12776 /* The PC is never poped directly, instead
12777 it is popped into r3 and then BX is used. */
12778 fprintf (f, "}\n");
12780 thumb_exit (f, -1, NULL_RTX);
12789 asm_fprintf (f, "%r", PC_REGNUM);
12793 fprintf (f, "}\n");
12795 if (push && pushed_words && dwarf2out_do_frame ())
12797 char *l = dwarf2out_cfi_label ();
12798 int pushed_mask = real_regs;
12800 *cfa_offset += pushed_words * 4;
12801 dwarf2out_def_cfa (l, SP_REGNUM, *cfa_offset);
12804 pushed_mask = real_regs;
12805 for (regno = 0; regno <= 14; regno++, pushed_mask >>= 1)
12807 if (pushed_mask & 1)
12808 dwarf2out_reg_save (l, regno, 4 * pushed_words++ - *cfa_offset);
12814 thumb_final_prescan_insn (rtx insn)
12816 if (flag_print_asm_name)
12817 asm_fprintf (asm_out_file, "%@ 0x%04x\n",
12818 INSN_ADDRESSES (INSN_UID (insn)));
12822 thumb_shiftable_const (unsigned HOST_WIDE_INT val)
12824 unsigned HOST_WIDE_INT mask = 0xff;
12827 if (val == 0) /* XXX */
12830 for (i = 0; i < 25; i++)
12831 if ((val & (mask << i)) == val)
12837 /* Returns nonzero if the current function contains,
12838 or might contain a far jump. */
12840 thumb_far_jump_used_p (void)
12844 /* This test is only important for leaf functions. */
12845 /* assert (!leaf_function_p ()); */
12847 /* If we have already decided that far jumps may be used,
12848 do not bother checking again, and always return true even if
12849 it turns out that they are not being used. Once we have made
12850 the decision that far jumps are present (and that hence the link
12851 register will be pushed onto the stack) we cannot go back on it. */
12852 if (cfun->machine->far_jump_used)
12855 /* If this function is not being called from the prologue/epilogue
12856 generation code then it must be being called from the
12857 INITIAL_ELIMINATION_OFFSET macro. */
12858 if (!(ARM_DOUBLEWORD_ALIGN || reload_completed))
12860 /* In this case we know that we are being asked about the elimination
12861 of the arg pointer register. If that register is not being used,
12862 then there are no arguments on the stack, and we do not have to
12863 worry that a far jump might force the prologue to push the link
12864 register, changing the stack offsets. In this case we can just
12865 return false, since the presence of far jumps in the function will
12866 not affect stack offsets.
12868 If the arg pointer is live (or if it was live, but has now been
12869 eliminated and so set to dead) then we do have to test to see if
12870 the function might contain a far jump. This test can lead to some
12871 false negatives, since before reload is completed, then length of
12872 branch instructions is not known, so gcc defaults to returning their
12873 longest length, which in turn sets the far jump attribute to true.
12875 A false negative will not result in bad code being generated, but it
12876 will result in a needless push and pop of the link register. We
12877 hope that this does not occur too often.
12879 If we need doubleword stack alignment this could affect the other
12880 elimination offsets so we can't risk getting it wrong. */
12881 if (regs_ever_live [ARG_POINTER_REGNUM])
12882 cfun->machine->arg_pointer_live = 1;
12883 else if (!cfun->machine->arg_pointer_live)
12887 /* Check to see if the function contains a branch
12888 insn with the far jump attribute set. */
12889 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
12891 if (GET_CODE (insn) == JUMP_INSN
12892 /* Ignore tablejump patterns. */
12893 && GET_CODE (PATTERN (insn)) != ADDR_VEC
12894 && GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC
12895 && get_attr_far_jump (insn) == FAR_JUMP_YES
12898 /* Record the fact that we have decided that
12899 the function does use far jumps. */
12900 cfun->machine->far_jump_used = 1;
12908 /* Return nonzero if FUNC must be entered in ARM mode. */
12910 is_called_in_ARM_mode (tree func)
12912 if (TREE_CODE (func) != FUNCTION_DECL)
12915 /* Ignore the problem about functions whoes address is taken. */
12916 if (TARGET_CALLEE_INTERWORKING && TREE_PUBLIC (func))
12920 return lookup_attribute ("interfacearm", DECL_ATTRIBUTES (func)) != NULL_TREE;
12926 /* The bits which aren't usefully expanded as rtl. */
12928 thumb_unexpanded_epilogue (void)
12931 int live_regs_mask = 0;
12932 int high_regs_pushed = 0;
12933 int had_to_push_lr;
12934 rtx eh_ofs = cfun->machine->eh_epilogue_sp_ofs;
12936 if (return_used_this_function)
12939 if (IS_NAKED (arm_current_func_type ()))
12942 for (regno = 0; regno <= LAST_LO_REGNUM; regno++)
12943 if (THUMB_REG_PUSHED_P (regno))
12944 live_regs_mask |= 1 << regno;
12946 for (regno = 8; regno < 13; regno++)
12947 if (THUMB_REG_PUSHED_P (regno))
12948 high_regs_pushed++;
12950 /* The prolog may have pushed some high registers to use as
12951 work registers. eg the testsuite file:
12952 gcc/testsuite/gcc/gcc.c-torture/execute/complex-2.c
12953 compiles to produce:
12954 push {r4, r5, r6, r7, lr}
12958 as part of the prolog. We have to undo that pushing here. */
12960 if (high_regs_pushed)
12962 int mask = live_regs_mask;
12967 /* If we can deduce the registers used from the function's return value.
12968 This is more reliable that examining regs_ever_live[] because that
12969 will be set if the register is ever used in the function, not just if
12970 the register is used to hold a return value. */
12972 if (current_function_return_rtx != 0)
12973 mode = GET_MODE (current_function_return_rtx);
12975 mode = DECL_MODE (DECL_RESULT (current_function_decl));
12977 size = GET_MODE_SIZE (mode);
12979 /* Unless we are returning a type of size > 12 register r3 is
12985 /* Oh dear! We have no low registers into which we can pop
12988 ("no low registers available for popping high registers");
12990 for (next_hi_reg = 8; next_hi_reg < 13; next_hi_reg++)
12991 if (THUMB_REG_PUSHED_P (next_hi_reg))
12994 while (high_regs_pushed)
12996 /* Find lo register(s) into which the high register(s) can
12998 for (regno = 0; regno <= LAST_LO_REGNUM; regno++)
13000 if (mask & (1 << regno))
13001 high_regs_pushed--;
13002 if (high_regs_pushed == 0)
13006 mask &= (2 << regno) - 1; /* A noop if regno == 8 */
13008 /* Pop the values into the low register(s). */
13009 thumb_pushpop (asm_out_file, mask, 0, NULL, mask);
13011 /* Move the value(s) into the high registers. */
13012 for (regno = 0; regno <= LAST_LO_REGNUM; regno++)
13014 if (mask & (1 << regno))
13016 asm_fprintf (asm_out_file, "\tmov\t%r, %r\n", next_hi_reg,
13019 for (next_hi_reg++; next_hi_reg < 13; next_hi_reg++)
13020 if (THUMB_REG_PUSHED_P (next_hi_reg))
13027 had_to_push_lr = (live_regs_mask || thumb_force_lr_save ());
13029 if (TARGET_BACKTRACE
13030 && ((live_regs_mask & 0xFF) == 0)
13031 && regs_ever_live [LAST_ARG_REGNUM] != 0)
13033 /* The stack backtrace structure creation code had to
13034 push R7 in order to get a work register, so we pop
13036 live_regs_mask |= (1 << LAST_LO_REGNUM);
13039 if (current_function_pretend_args_size == 0 || TARGET_BACKTRACE)
13042 && !is_called_in_ARM_mode (current_function_decl)
13044 live_regs_mask |= 1 << PC_REGNUM;
13046 /* Either no argument registers were pushed or a backtrace
13047 structure was created which includes an adjusted stack
13048 pointer, so just pop everything. */
13049 if (live_regs_mask)
13050 thumb_pushpop (asm_out_file, live_regs_mask, FALSE, NULL,
13054 thumb_exit (asm_out_file, 2, eh_ofs);
13055 /* We have either just popped the return address into the
13056 PC or it is was kept in LR for the entire function or
13057 it is still on the stack because we do not want to
13058 return by doing a pop {pc}. */
13059 else if ((live_regs_mask & (1 << PC_REGNUM)) == 0)
13060 thumb_exit (asm_out_file,
13062 && is_called_in_ARM_mode (current_function_decl)) ?
13063 -1 : LR_REGNUM, NULL_RTX);
13067 /* Pop everything but the return address. */
13068 live_regs_mask &= ~(1 << PC_REGNUM);
13070 if (live_regs_mask)
13071 thumb_pushpop (asm_out_file, live_regs_mask, FALSE, NULL,
13074 if (had_to_push_lr)
13075 /* Get the return address into a temporary register. */
13076 thumb_pushpop (asm_out_file, 1 << LAST_ARG_REGNUM, 0, NULL,
13077 1 << LAST_ARG_REGNUM);
13079 /* Remove the argument registers that were pushed onto the stack. */
13080 asm_fprintf (asm_out_file, "\tadd\t%r, %r, #%d\n",
13081 SP_REGNUM, SP_REGNUM,
13082 current_function_pretend_args_size);
13085 thumb_exit (asm_out_file, 2, eh_ofs);
13087 thumb_exit (asm_out_file,
13088 had_to_push_lr ? LAST_ARG_REGNUM : LR_REGNUM, NULL_RTX);
13094 /* Functions to save and restore machine-specific function data. */
13095 static struct machine_function *
13096 arm_init_machine_status (void)
13098 struct machine_function *machine;
13099 machine = (machine_function *) ggc_alloc_cleared (sizeof (machine_function));
13101 #if ARM_FT_UNKNOWN != 0
13102 machine->func_type = ARM_FT_UNKNOWN;
13107 /* Return an RTX indicating where the return address to the
13108 calling function can be found. */
13110 arm_return_addr (int count, rtx frame ATTRIBUTE_UNUSED)
13115 return get_hard_reg_initial_val (Pmode, LR_REGNUM);
13118 /* Do anything needed before RTL is emitted for each function. */
13120 arm_init_expanders (void)
13122 /* Arrange to initialize and mark the machine per-function status. */
13123 init_machine_status = arm_init_machine_status;
13125 /* This is to stop the combine pass optimizing away the alignment
13126 adjustment of va_arg. */
13127 /* ??? It is claimed that this should not be necessary. */
13129 mark_reg_pointer (arg_pointer_rtx, PARM_BOUNDARY);
13133 /* Like arm_compute_initial_elimination offset. Simpler because
13134 THUMB_HARD_FRAME_POINTER isn't actually the ABI specified frame pointer. */
13137 thumb_compute_initial_elimination_offset (unsigned int from, unsigned int to)
13139 arm_stack_offsets *offsets;
13141 offsets = arm_get_frame_offsets ();
13145 case ARG_POINTER_REGNUM:
13148 case STACK_POINTER_REGNUM:
13149 return offsets->outgoing_args - offsets->saved_args;
13151 case FRAME_POINTER_REGNUM:
13152 return offsets->soft_frame - offsets->saved_args;
13154 case THUMB_HARD_FRAME_POINTER_REGNUM:
13155 case ARM_HARD_FRAME_POINTER_REGNUM:
13156 return offsets->saved_regs - offsets->saved_args;
13163 case FRAME_POINTER_REGNUM:
13166 case STACK_POINTER_REGNUM:
13167 return offsets->outgoing_args - offsets->soft_frame;
13169 case THUMB_HARD_FRAME_POINTER_REGNUM:
13170 case ARM_HARD_FRAME_POINTER_REGNUM:
13171 return offsets->saved_regs - offsets->soft_frame;
13184 /* Generate the rest of a function's prologue. */
13186 thumb_expand_prologue (void)
13190 HOST_WIDE_INT amount;
13191 arm_stack_offsets *offsets;
13192 unsigned long func_type;
13195 func_type = arm_current_func_type ();
13197 /* Naked functions don't have prologues. */
13198 if (IS_NAKED (func_type))
13201 if (IS_INTERRUPT (func_type))
13203 error ("interrupt Service Routines cannot be coded in Thumb mode");
13207 offsets = arm_get_frame_offsets ();
13209 if (frame_pointer_needed)
13211 insn = emit_insn (gen_movsi (hard_frame_pointer_rtx,
13212 stack_pointer_rtx));
13213 RTX_FRAME_RELATED_P (insn) = 1;
13216 amount = offsets->outgoing_args - offsets->saved_regs;
13221 insn = emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,
13222 GEN_INT (- amount)));
13223 RTX_FRAME_RELATED_P (insn) = 1;
13229 /* The stack decrement is too big for an immediate value in a single
13230 insn. In theory we could issue multiple subtracts, but after
13231 three of them it becomes more space efficient to place the full
13232 value in the constant pool and load into a register. (Also the
13233 ARM debugger really likes to see only one stack decrement per
13234 function). So instead we look for a scratch register into which
13235 we can load the decrement, and then we subtract this from the
13236 stack pointer. Unfortunately on the thumb the only available
13237 scratch registers are the argument registers, and we cannot use
13238 these as they may hold arguments to the function. Instead we
13239 attempt to locate a call preserved register which is used by this
13240 function. If we can find one, then we know that it will have
13241 been pushed at the start of the prologue and so we can corrupt
13243 for (regno = LAST_ARG_REGNUM + 1; regno <= LAST_LO_REGNUM; regno++)
13244 if (THUMB_REG_PUSHED_P (regno)
13245 && !(frame_pointer_needed
13246 && (regno == THUMB_HARD_FRAME_POINTER_REGNUM)))
13249 if (regno > LAST_LO_REGNUM) /* Very unlikely. */
13251 rtx spare = gen_rtx_REG (SImode, IP_REGNUM);
13253 /* Choose an arbitrary, non-argument low register. */
13254 reg = gen_rtx_REG (SImode, LAST_LO_REGNUM);
13256 /* Save it by copying it into a high, scratch register. */
13257 emit_insn (gen_movsi (spare, reg));
13258 /* Add a USE to stop propagate_one_insn() from barfing. */
13259 emit_insn (gen_prologue_use (spare));
13261 /* Decrement the stack. */
13262 emit_insn (gen_movsi (reg, GEN_INT (- amount)));
13263 insn = emit_insn (gen_addsi3 (stack_pointer_rtx,
13264 stack_pointer_rtx, reg));
13265 RTX_FRAME_RELATED_P (insn) = 1;
13266 dwarf = gen_rtx_SET (SImode, stack_pointer_rtx,
13267 plus_constant (stack_pointer_rtx,
13268 GEN_INT (- amount)));
13269 RTX_FRAME_RELATED_P (dwarf) = 1;
13271 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, dwarf,
13274 /* Restore the low register's original value. */
13275 emit_insn (gen_movsi (reg, spare));
13277 /* Emit a USE of the restored scratch register, so that flow
13278 analysis will not consider the restore redundant. The
13279 register won't be used again in this function and isn't
13280 restored by the epilogue. */
13281 emit_insn (gen_prologue_use (reg));
13285 reg = gen_rtx_REG (SImode, regno);
13287 emit_insn (gen_movsi (reg, GEN_INT (- amount)));
13289 insn = emit_insn (gen_addsi3 (stack_pointer_rtx,
13290 stack_pointer_rtx, reg));
13291 RTX_FRAME_RELATED_P (insn) = 1;
13292 dwarf = gen_rtx_SET (SImode, stack_pointer_rtx,
13293 plus_constant (stack_pointer_rtx,
13294 GEN_INT (- amount)));
13295 RTX_FRAME_RELATED_P (dwarf) = 1;
13297 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, dwarf,
13301 /* If the frame pointer is needed, emit a special barrier that
13302 will prevent the scheduler from moving stores to the frame
13303 before the stack adjustment. */
13304 if (frame_pointer_needed)
13305 emit_insn (gen_stack_tie (stack_pointer_rtx,
13306 hard_frame_pointer_rtx));
13309 if (current_function_profile || TARGET_NO_SCHED_PRO)
13310 emit_insn (gen_blockage ());
13312 cfun->machine->lr_save_eliminated = !thumb_force_lr_save ();
13313 for (regno = 0; regno <= LAST_LO_REGNUM; regno++)
13315 if (THUMB_REG_PUSHED_P (regno))
13317 cfun->machine->lr_save_eliminated = 0;
13322 /* If the link register is being kept alive, with the return address in it,
13323 then make sure that it does not get reused by the ce2 pass. */
13324 if (cfun->machine->lr_save_eliminated)
13325 emit_insn (gen_prologue_use (gen_rtx_REG (SImode, LR_REGNUM)));
13329 thumb_expand_epilogue (void)
13331 HOST_WIDE_INT amount;
13332 arm_stack_offsets *offsets;
13335 /* Naked functions don't have prologues. */
13336 if (IS_NAKED (arm_current_func_type ()))
13339 offsets = arm_get_frame_offsets ();
13340 amount = offsets->outgoing_args - offsets->saved_regs;
13342 if (frame_pointer_needed)
13343 emit_insn (gen_movsi (stack_pointer_rtx, hard_frame_pointer_rtx));
13347 emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,
13348 GEN_INT (amount)));
13351 /* r3 is always free in the epilogue. */
13352 rtx reg = gen_rtx_REG (SImode, LAST_ARG_REGNUM);
13354 emit_insn (gen_movsi (reg, GEN_INT (amount)));
13355 emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, reg));
13359 /* Emit a USE (stack_pointer_rtx), so that
13360 the stack adjustment will not be deleted. */
13361 emit_insn (gen_prologue_use (stack_pointer_rtx));
13363 if (current_function_profile || TARGET_NO_SCHED_PRO)
13364 emit_insn (gen_blockage ());
13366 /* Emit a clobber for each insn that will be restored in the epilogue,
13367 so that flow2 will get register lifetimes correct. */
13368 for (regno = 0; regno < 13; regno++)
13369 if (regs_ever_live[regno] && !call_used_regs[regno])
13370 emit_insn (gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, regno)));
13372 if (! regs_ever_live[LR_REGNUM])
13373 emit_insn (gen_rtx_USE (VOIDmode, gen_rtx_REG (SImode, LR_REGNUM)));
13377 thumb_output_function_prologue (FILE *f, HOST_WIDE_INT size ATTRIBUTE_UNUSED)
13379 int live_regs_mask = 0;
13380 int high_regs_pushed = 0;
13381 int cfa_offset = 0;
13384 if (IS_NAKED (arm_current_func_type ()))
13387 if (is_called_in_ARM_mode (current_function_decl))
13391 if (GET_CODE (DECL_RTL (current_function_decl)) != MEM)
13393 if (GET_CODE (XEXP (DECL_RTL (current_function_decl), 0)) != SYMBOL_REF)
13395 name = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
13397 /* Generate code sequence to switch us into Thumb mode. */
13398 /* The .code 32 directive has already been emitted by
13399 ASM_DECLARE_FUNCTION_NAME. */
13400 asm_fprintf (f, "\torr\t%r, %r, #1\n", IP_REGNUM, PC_REGNUM);
13401 asm_fprintf (f, "\tbx\t%r\n", IP_REGNUM);
13403 /* Generate a label, so that the debugger will notice the
13404 change in instruction sets. This label is also used by
13405 the assembler to bypass the ARM code when this function
13406 is called from a Thumb encoded function elsewhere in the
13407 same file. Hence the definition of STUB_NAME here must
13408 agree with the definition in gas/config/tc-arm.c. */
13410 #define STUB_NAME ".real_start_of"
13412 fprintf (f, "\t.code\t16\n");
13414 if (arm_dllexport_name_p (name))
13415 name = arm_strip_name_encoding (name);
13417 asm_fprintf (f, "\t.globl %s%U%s\n", STUB_NAME, name);
13418 fprintf (f, "\t.thumb_func\n");
13419 asm_fprintf (f, "%s%U%s:\n", STUB_NAME, name);
13422 if (current_function_pretend_args_size)
13424 if (cfun->machine->uses_anonymous_args)
13428 fprintf (f, "\tpush\t{");
13430 num_pushes = ARM_NUM_INTS (current_function_pretend_args_size);
13432 for (regno = LAST_ARG_REGNUM + 1 - num_pushes;
13433 regno <= LAST_ARG_REGNUM;
13435 asm_fprintf (f, "%r%s", regno,
13436 regno == LAST_ARG_REGNUM ? "" : ", ");
13438 fprintf (f, "}\n");
13441 asm_fprintf (f, "\tsub\t%r, %r, #%d\n",
13442 SP_REGNUM, SP_REGNUM,
13443 current_function_pretend_args_size);
13445 /* We don't need to record the stores for unwinding (would it
13446 help the debugger any if we did?), but record the change in
13447 the stack pointer. */
13448 if (dwarf2out_do_frame ())
13450 char *l = dwarf2out_cfi_label ();
13451 cfa_offset = cfa_offset + current_function_pretend_args_size;
13452 dwarf2out_def_cfa (l, SP_REGNUM, cfa_offset);
13456 for (regno = 0; regno <= LAST_LO_REGNUM; regno++)
13457 if (THUMB_REG_PUSHED_P (regno))
13458 live_regs_mask |= 1 << regno;
13460 if (live_regs_mask || thumb_force_lr_save ())
13461 live_regs_mask |= 1 << LR_REGNUM;
13463 if (TARGET_BACKTRACE)
13466 int work_register = 0;
13469 /* We have been asked to create a stack backtrace structure.
13470 The code looks like this:
13474 0 sub SP, #16 Reserve space for 4 registers.
13475 2 push {R7} Get a work register.
13476 4 add R7, SP, #20 Get the stack pointer before the push.
13477 6 str R7, [SP, #8] Store the stack pointer (before reserving the space).
13478 8 mov R7, PC Get hold of the start of this code plus 12.
13479 10 str R7, [SP, #16] Store it.
13480 12 mov R7, FP Get hold of the current frame pointer.
13481 14 str R7, [SP, #4] Store it.
13482 16 mov R7, LR Get hold of the current return address.
13483 18 str R7, [SP, #12] Store it.
13484 20 add R7, SP, #16 Point at the start of the backtrace structure.
13485 22 mov FP, R7 Put this value into the frame pointer. */
13487 if ((live_regs_mask & 0xFF) == 0)
13489 /* See if the a4 register is free. */
13491 if (regs_ever_live [LAST_ARG_REGNUM] == 0)
13492 work_register = LAST_ARG_REGNUM;
13493 else /* We must push a register of our own. */
13494 live_regs_mask |= (1 << LAST_LO_REGNUM);
13497 if (work_register == 0)
13499 /* Select a register from the list that will be pushed to
13500 use as our work register. */
13501 for (work_register = (LAST_LO_REGNUM + 1); work_register--;)
13502 if ((1 << work_register) & live_regs_mask)
13507 (f, "\tsub\t%r, %r, #16\t%@ Create stack backtrace structure\n",
13508 SP_REGNUM, SP_REGNUM);
13510 if (dwarf2out_do_frame ())
13512 char *l = dwarf2out_cfi_label ();
13513 cfa_offset = cfa_offset + 16;
13514 dwarf2out_def_cfa (l, SP_REGNUM, cfa_offset);
13517 if (live_regs_mask)
13518 thumb_pushpop (f, live_regs_mask, 1, &cfa_offset, live_regs_mask);
13520 for (offset = 0, wr = 1 << 15; wr != 0; wr >>= 1)
13521 if (wr & live_regs_mask)
13524 asm_fprintf (f, "\tadd\t%r, %r, #%d\n", work_register, SP_REGNUM,
13525 offset + 16 + current_function_pretend_args_size);
13527 asm_fprintf (f, "\tstr\t%r, [%r, #%d]\n", work_register, SP_REGNUM,
13530 /* Make sure that the instruction fetching the PC is in the right place
13531 to calculate "start of backtrace creation code + 12". */
13532 if (live_regs_mask)
13534 asm_fprintf (f, "\tmov\t%r, %r\n", work_register, PC_REGNUM);
13535 asm_fprintf (f, "\tstr\t%r, [%r, #%d]\n", work_register, SP_REGNUM,
13537 asm_fprintf (f, "\tmov\t%r, %r\n", work_register,
13538 ARM_HARD_FRAME_POINTER_REGNUM);
13539 asm_fprintf (f, "\tstr\t%r, [%r, #%d]\n", work_register, SP_REGNUM,
13544 asm_fprintf (f, "\tmov\t%r, %r\n", work_register,
13545 ARM_HARD_FRAME_POINTER_REGNUM);
13546 asm_fprintf (f, "\tstr\t%r, [%r, #%d]\n", work_register, SP_REGNUM,
13548 asm_fprintf (f, "\tmov\t%r, %r\n", work_register, PC_REGNUM);
13549 asm_fprintf (f, "\tstr\t%r, [%r, #%d]\n", work_register, SP_REGNUM,
13553 asm_fprintf (f, "\tmov\t%r, %r\n", work_register, LR_REGNUM);
13554 asm_fprintf (f, "\tstr\t%r, [%r, #%d]\n", work_register, SP_REGNUM,
13556 asm_fprintf (f, "\tadd\t%r, %r, #%d\n", work_register, SP_REGNUM,
13558 asm_fprintf (f, "\tmov\t%r, %r\t\t%@ Backtrace structure created\n",
13559 ARM_HARD_FRAME_POINTER_REGNUM, work_register);
13561 else if (live_regs_mask)
13562 thumb_pushpop (f, live_regs_mask, 1, &cfa_offset, live_regs_mask);
13564 for (regno = 8; regno < 13; regno++)
13565 if (THUMB_REG_PUSHED_P (regno))
13566 high_regs_pushed++;
13568 if (high_regs_pushed)
13570 int pushable_regs = 0;
13571 int mask = live_regs_mask & 0xff;
13574 for (next_hi_reg = 12; next_hi_reg > LAST_LO_REGNUM; next_hi_reg--)
13575 if (THUMB_REG_PUSHED_P (next_hi_reg))
13578 pushable_regs = mask;
13580 if (pushable_regs == 0)
13582 /* Desperation time -- this probably will never happen. */
13583 if (THUMB_REG_PUSHED_P (LAST_ARG_REGNUM))
13584 asm_fprintf (f, "\tmov\t%r, %r\n", IP_REGNUM, LAST_ARG_REGNUM);
13585 mask = 1 << LAST_ARG_REGNUM;
13588 while (high_regs_pushed > 0)
13590 int real_regs_mask = 0;
13592 for (regno = LAST_LO_REGNUM; regno >= 0; regno--)
13594 if (mask & (1 << regno))
13596 asm_fprintf (f, "\tmov\t%r, %r\n", regno, next_hi_reg);
13598 high_regs_pushed--;
13599 real_regs_mask |= (1 << next_hi_reg);
13601 if (high_regs_pushed)
13603 for (next_hi_reg--; next_hi_reg > LAST_LO_REGNUM;
13605 if (THUMB_REG_PUSHED_P (next_hi_reg))
13610 mask &= ~((1 << regno) - 1);
13616 thumb_pushpop (f, mask, 1, &cfa_offset, real_regs_mask);
13619 if (pushable_regs == 0
13620 && (THUMB_REG_PUSHED_P (LAST_ARG_REGNUM)))
13621 asm_fprintf (f, "\tmov\t%r, %r\n", LAST_ARG_REGNUM, IP_REGNUM);
13625 /* Handle the case of a double word load into a low register from
13626 a computed memory address. The computed address may involve a
13627 register which is overwritten by the load. */
13629 thumb_load_double_from_address (rtx *operands)
13637 if (GET_CODE (operands[0]) != REG)
13640 if (GET_CODE (operands[1]) != MEM)
13643 /* Get the memory address. */
13644 addr = XEXP (operands[1], 0);
13646 /* Work out how the memory address is computed. */
13647 switch (GET_CODE (addr))
13650 operands[2] = gen_rtx_MEM (SImode,
13651 plus_constant (XEXP (operands[1], 0), 4));
13653 if (REGNO (operands[0]) == REGNO (addr))
13655 output_asm_insn ("ldr\t%H0, %2", operands);
13656 output_asm_insn ("ldr\t%0, %1", operands);
13660 output_asm_insn ("ldr\t%0, %1", operands);
13661 output_asm_insn ("ldr\t%H0, %2", operands);
13666 /* Compute <address> + 4 for the high order load. */
13667 operands[2] = gen_rtx_MEM (SImode,
13668 plus_constant (XEXP (operands[1], 0), 4));
13670 output_asm_insn ("ldr\t%0, %1", operands);
13671 output_asm_insn ("ldr\t%H0, %2", operands);
13675 arg1 = XEXP (addr, 0);
13676 arg2 = XEXP (addr, 1);
13678 if (CONSTANT_P (arg1))
13679 base = arg2, offset = arg1;
13681 base = arg1, offset = arg2;
13683 if (GET_CODE (base) != REG)
13686 /* Catch the case of <address> = <reg> + <reg> */
13687 if (GET_CODE (offset) == REG)
13689 int reg_offset = REGNO (offset);
13690 int reg_base = REGNO (base);
13691 int reg_dest = REGNO (operands[0]);
13693 /* Add the base and offset registers together into the
13694 higher destination register. */
13695 asm_fprintf (asm_out_file, "\tadd\t%r, %r, %r",
13696 reg_dest + 1, reg_base, reg_offset);
13698 /* Load the lower destination register from the address in
13699 the higher destination register. */
13700 asm_fprintf (asm_out_file, "\tldr\t%r, [%r, #0]",
13701 reg_dest, reg_dest + 1);
13703 /* Load the higher destination register from its own address
13705 asm_fprintf (asm_out_file, "\tldr\t%r, [%r, #4]",
13706 reg_dest + 1, reg_dest + 1);
13710 /* Compute <address> + 4 for the high order load. */
13711 operands[2] = gen_rtx_MEM (SImode,
13712 plus_constant (XEXP (operands[1], 0), 4));
13714 /* If the computed address is held in the low order register
13715 then load the high order register first, otherwise always
13716 load the low order register first. */
13717 if (REGNO (operands[0]) == REGNO (base))
13719 output_asm_insn ("ldr\t%H0, %2", operands);
13720 output_asm_insn ("ldr\t%0, %1", operands);
13724 output_asm_insn ("ldr\t%0, %1", operands);
13725 output_asm_insn ("ldr\t%H0, %2", operands);
13731 /* With no registers to worry about we can just load the value
13733 operands[2] = gen_rtx_MEM (SImode,
13734 plus_constant (XEXP (operands[1], 0), 4));
13736 output_asm_insn ("ldr\t%H0, %2", operands);
13737 output_asm_insn ("ldr\t%0, %1", operands);
13749 thumb_output_move_mem_multiple (int n, rtx *operands)
13756 if (REGNO (operands[4]) > REGNO (operands[5]))
13759 operands[4] = operands[5];
13762 output_asm_insn ("ldmia\t%1!, {%4, %5}", operands);
13763 output_asm_insn ("stmia\t%0!, {%4, %5}", operands);
13767 if (REGNO (operands[4]) > REGNO (operands[5]))
13770 operands[4] = operands[5];
13773 if (REGNO (operands[5]) > REGNO (operands[6]))
13776 operands[5] = operands[6];
13779 if (REGNO (operands[4]) > REGNO (operands[5]))
13782 operands[4] = operands[5];
13786 output_asm_insn ("ldmia\t%1!, {%4, %5, %6}", operands);
13787 output_asm_insn ("stmia\t%0!, {%4, %5, %6}", operands);
13797 /* Routines for generating rtl. */
13799 thumb_expand_movmemqi (rtx *operands)
13801 rtx out = copy_to_mode_reg (SImode, XEXP (operands[0], 0));
13802 rtx in = copy_to_mode_reg (SImode, XEXP (operands[1], 0));
13803 HOST_WIDE_INT len = INTVAL (operands[2]);
13804 HOST_WIDE_INT offset = 0;
13808 emit_insn (gen_movmem12b (out, in, out, in));
13814 emit_insn (gen_movmem8b (out, in, out, in));
13820 rtx reg = gen_reg_rtx (SImode);
13821 emit_insn (gen_movsi (reg, gen_rtx_MEM (SImode, in)));
13822 emit_insn (gen_movsi (gen_rtx_MEM (SImode, out), reg));
13829 rtx reg = gen_reg_rtx (HImode);
13830 emit_insn (gen_movhi (reg, gen_rtx_MEM (HImode,
13831 plus_constant (in, offset))));
13832 emit_insn (gen_movhi (gen_rtx_MEM (HImode, plus_constant (out, offset)),
13840 rtx reg = gen_reg_rtx (QImode);
13841 emit_insn (gen_movqi (reg, gen_rtx_MEM (QImode,
13842 plus_constant (in, offset))));
13843 emit_insn (gen_movqi (gen_rtx_MEM (QImode, plus_constant (out, offset)),
13849 thumb_cmp_operand (rtx op, enum machine_mode mode)
13851 return ((GET_CODE (op) == CONST_INT
13852 && INTVAL (op) < 256
13853 && INTVAL (op) >= 0)
13854 || s_register_operand (op, mode));
13858 thumb_cmpneg_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
13860 return (GET_CODE (op) == CONST_INT
13862 && INTVAL (op) > -256);
13865 /* Return TRUE if a result can be stored in OP without clobbering the
13866 condition code register. Prior to reload we only accept a
13867 register. After reload we have to be able to handle memory as
13868 well, since a pseudo may not get a hard reg and reload cannot
13869 handle output-reloads on jump insns.
13871 We could possibly handle mem before reload as well, but that might
13872 complicate things with the need to handle increment
13876 thumb_cbrch_target_operand (rtx op, enum machine_mode mode)
13878 return (s_register_operand (op, mode)
13879 || ((reload_in_progress || reload_completed)
13880 && memory_operand (op, mode)));
13883 /* Handle storing a half-word to memory during reload. */
13885 thumb_reload_out_hi (rtx *operands)
13887 emit_insn (gen_thumb_movhi_clobber (operands[0], operands[1], operands[2]));
13890 /* Handle reading a half-word from memory during reload. */
13892 thumb_reload_in_hi (rtx *operands ATTRIBUTE_UNUSED)
13897 /* Return the length of a function name prefix
13898 that starts with the character 'c'. */
13900 arm_get_strip_length (int c)
13904 ARM_NAME_ENCODING_LENGTHS
13909 /* Return a pointer to a function's name with any
13910 and all prefix encodings stripped from it. */
13912 arm_strip_name_encoding (const char *name)
13916 while ((skip = arm_get_strip_length (* name)))
13922 /* If there is a '*' anywhere in the name's prefix, then
13923 emit the stripped name verbatim, otherwise prepend an
13924 underscore if leading underscores are being used. */
13926 arm_asm_output_labelref (FILE *stream, const char *name)
13931 while ((skip = arm_get_strip_length (* name)))
13933 verbatim |= (*name == '*');
13938 fputs (name, stream);
13940 asm_fprintf (stream, "%U%s", name);
13945 #ifdef AOF_ASSEMBLER
13946 /* Special functions only needed when producing AOF syntax assembler. */
13950 struct pic_chain * next;
13951 const char * symname;
13954 static struct pic_chain * aof_pic_chain = NULL;
13957 aof_pic_entry (rtx x)
13959 struct pic_chain ** chainp;
13962 if (aof_pic_label == NULL_RTX)
13964 aof_pic_label = gen_rtx_SYMBOL_REF (Pmode, "x$adcons");
13967 for (offset = 0, chainp = &aof_pic_chain; *chainp;
13968 offset += 4, chainp = &(*chainp)->next)
13969 if ((*chainp)->symname == XSTR (x, 0))
13970 return plus_constant (aof_pic_label, offset);
13972 *chainp = (struct pic_chain *) xmalloc (sizeof (struct pic_chain));
13973 (*chainp)->next = NULL;
13974 (*chainp)->symname = XSTR (x, 0);
13975 return plus_constant (aof_pic_label, offset);
13979 aof_dump_pic_table (FILE *f)
13981 struct pic_chain * chain;
13983 if (aof_pic_chain == NULL)
13986 asm_fprintf (f, "\tAREA |%r$$adcons|, BASED %r\n",
13987 PIC_OFFSET_TABLE_REGNUM,
13988 PIC_OFFSET_TABLE_REGNUM);
13989 fputs ("|x$adcons|\n", f);
13991 for (chain = aof_pic_chain; chain; chain = chain->next)
13993 fputs ("\tDCD\t", f);
13994 assemble_name (f, chain->symname);
13999 int arm_text_section_count = 1;
14002 aof_text_section (void )
14004 static char buf[100];
14005 sprintf (buf, "\tAREA |C$$code%d|, CODE, READONLY",
14006 arm_text_section_count++);
14008 strcat (buf, ", PIC, REENTRANT");
14012 static int arm_data_section_count = 1;
14015 aof_data_section (void)
14017 static char buf[100];
14018 sprintf (buf, "\tAREA |C$$data%d|, DATA", arm_data_section_count++);
14022 /* The AOF assembler is religiously strict about declarations of
14023 imported and exported symbols, so that it is impossible to declare
14024 a function as imported near the beginning of the file, and then to
14025 export it later on. It is, however, possible to delay the decision
14026 until all the functions in the file have been compiled. To get
14027 around this, we maintain a list of the imports and exports, and
14028 delete from it any that are subsequently defined. At the end of
14029 compilation we spit the remainder of the list out before the END
14034 struct import * next;
14038 static struct import * imports_list = NULL;
14041 aof_add_import (const char *name)
14043 struct import * new;
14045 for (new = imports_list; new; new = new->next)
14046 if (new->name == name)
14049 new = (struct import *) xmalloc (sizeof (struct import));
14050 new->next = imports_list;
14051 imports_list = new;
14056 aof_delete_import (const char *name)
14058 struct import ** old;
14060 for (old = &imports_list; *old; old = & (*old)->next)
14062 if ((*old)->name == name)
14064 *old = (*old)->next;
14070 int arm_main_function = 0;
14073 aof_dump_imports (FILE *f)
14075 /* The AOF assembler needs this to cause the startup code to be extracted
14076 from the library. Brining in __main causes the whole thing to work
14078 if (arm_main_function)
14081 fputs ("\tIMPORT __main\n", f);
14082 fputs ("\tDCD __main\n", f);
14085 /* Now dump the remaining imports. */
14086 while (imports_list)
14088 fprintf (f, "\tIMPORT\t");
14089 assemble_name (f, imports_list->name);
14091 imports_list = imports_list->next;
14096 aof_globalize_label (FILE *stream, const char *name)
14098 default_globalize_label (stream, name);
14099 if (! strcmp (name, "main"))
14100 arm_main_function = 1;
14104 aof_file_start (void)
14106 fputs ("__r0\tRN\t0\n", asm_out_file);
14107 fputs ("__a1\tRN\t0\n", asm_out_file);
14108 fputs ("__a2\tRN\t1\n", asm_out_file);
14109 fputs ("__a3\tRN\t2\n", asm_out_file);
14110 fputs ("__a4\tRN\t3\n", asm_out_file);
14111 fputs ("__v1\tRN\t4\n", asm_out_file);
14112 fputs ("__v2\tRN\t5\n", asm_out_file);
14113 fputs ("__v3\tRN\t6\n", asm_out_file);
14114 fputs ("__v4\tRN\t7\n", asm_out_file);
14115 fputs ("__v5\tRN\t8\n", asm_out_file);
14116 fputs ("__v6\tRN\t9\n", asm_out_file);
14117 fputs ("__sl\tRN\t10\n", asm_out_file);
14118 fputs ("__fp\tRN\t11\n", asm_out_file);
14119 fputs ("__ip\tRN\t12\n", asm_out_file);
14120 fputs ("__sp\tRN\t13\n", asm_out_file);
14121 fputs ("__lr\tRN\t14\n", asm_out_file);
14122 fputs ("__pc\tRN\t15\n", asm_out_file);
14123 fputs ("__f0\tFN\t0\n", asm_out_file);
14124 fputs ("__f1\tFN\t1\n", asm_out_file);
14125 fputs ("__f2\tFN\t2\n", asm_out_file);
14126 fputs ("__f3\tFN\t3\n", asm_out_file);
14127 fputs ("__f4\tFN\t4\n", asm_out_file);
14128 fputs ("__f5\tFN\t5\n", asm_out_file);
14129 fputs ("__f6\tFN\t6\n", asm_out_file);
14130 fputs ("__f7\tFN\t7\n", asm_out_file);
14135 aof_file_end (void)
14138 aof_dump_pic_table (asm_out_file);
14139 aof_dump_imports (asm_out_file);
14140 fputs ("\tEND\n", asm_out_file);
14142 #endif /* AOF_ASSEMBLER */
14144 #ifdef OBJECT_FORMAT_ELF
14145 /* Switch to an arbitrary section NAME with attributes as specified
14146 by FLAGS. ALIGN specifies any known alignment requirements for
14147 the section; 0 if the default should be used.
14149 Differs from the default elf version only in the prefix character
14150 used before the section type. */
14153 arm_elf_asm_named_section (const char *name, unsigned int flags)
14155 char flagchars[10], *f = flagchars;
14157 if (! named_section_first_declaration (name))
14159 fprintf (asm_out_file, "\t.section\t%s\n", name);
14163 if (!(flags & SECTION_DEBUG))
14165 if (flags & SECTION_WRITE)
14167 if (flags & SECTION_CODE)
14169 if (flags & SECTION_SMALL)
14171 if (flags & SECTION_MERGE)
14173 if (flags & SECTION_STRINGS)
14175 if (flags & SECTION_TLS)
14179 fprintf (asm_out_file, "\t.section\t%s,\"%s\"", name, flagchars);
14181 if (!(flags & SECTION_NOTYPE))
14185 if (flags & SECTION_BSS)
14190 fprintf (asm_out_file, ",%%%s", type);
14192 if (flags & SECTION_ENTSIZE)
14193 fprintf (asm_out_file, ",%d", flags & SECTION_ENTSIZE);
14196 putc ('\n', asm_out_file);
14201 /* Symbols in the text segment can be accessed without indirecting via the
14202 constant pool; it may take an extra binary operation, but this is still
14203 faster than indirecting via memory. Don't do this when not optimizing,
14204 since we won't be calculating al of the offsets necessary to do this
14208 arm_encode_section_info (tree decl, rtx rtl, int first)
14210 /* This doesn't work with AOF syntax, since the string table may be in
14211 a different AREA. */
14212 #ifndef AOF_ASSEMBLER
14213 if (optimize > 0 && TREE_CONSTANT (decl))
14214 SYMBOL_REF_FLAG (XEXP (rtl, 0)) = 1;
14217 /* If we are referencing a function that is weak then encode a long call
14218 flag in the function name, otherwise if the function is static or
14219 or known to be defined in this file then encode a short call flag. */
14220 if (first && TREE_CODE_CLASS (TREE_CODE (decl)) == 'd')
14222 if (TREE_CODE (decl) == FUNCTION_DECL && DECL_WEAK (decl))
14223 arm_encode_call_attribute (decl, LONG_CALL_FLAG_CHAR);
14224 else if (! TREE_PUBLIC (decl))
14225 arm_encode_call_attribute (decl, SHORT_CALL_FLAG_CHAR);
14228 #endif /* !ARM_PE */
14231 arm_internal_label (FILE *stream, const char *prefix, unsigned long labelno)
14233 if (arm_ccfsm_state == 3 && (unsigned) arm_target_label == labelno
14234 && !strcmp (prefix, "L"))
14236 arm_ccfsm_state = 0;
14237 arm_target_insn = NULL;
14239 default_internal_label (stream, prefix, labelno);
14242 /* Output code to add DELTA to the first argument, and then jump
14243 to FUNCTION. Used for C++ multiple inheritance. */
14245 arm_output_mi_thunk (FILE *file, tree thunk ATTRIBUTE_UNUSED,
14246 HOST_WIDE_INT delta,
14247 HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED,
14250 static int thunk_label = 0;
14252 int mi_delta = delta;
14253 const char *const mi_op = mi_delta < 0 ? "sub" : "add";
14255 int this_regno = (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function)
14258 mi_delta = - mi_delta;
14261 int labelno = thunk_label++;
14262 ASM_GENERATE_INTERNAL_LABEL (label, "LTHUMBFUNC", labelno);
14263 fputs ("\tldr\tr12, ", file);
14264 assemble_name (file, label);
14265 fputc ('\n', file);
14267 while (mi_delta != 0)
14269 if ((mi_delta & (3 << shift)) == 0)
14273 asm_fprintf (file, "\t%s\t%r, %r, #%d\n",
14274 mi_op, this_regno, this_regno,
14275 mi_delta & (0xff << shift));
14276 mi_delta &= ~(0xff << shift);
14282 fprintf (file, "\tbx\tr12\n");
14283 ASM_OUTPUT_ALIGN (file, 2);
14284 assemble_name (file, label);
14285 fputs (":\n", file);
14286 assemble_integer (XEXP (DECL_RTL (function), 0), 4, BITS_PER_WORD, 1);
14290 fputs ("\tb\t", file);
14291 assemble_name (file, XSTR (XEXP (DECL_RTL (function), 0), 0));
14292 if (NEED_PLT_RELOC)
14293 fputs ("(PLT)", file);
14294 fputc ('\n', file);
14299 arm_emit_vector_const (FILE *file, rtx x)
14302 const char * pattern;
14304 if (GET_CODE (x) != CONST_VECTOR)
14307 switch (GET_MODE (x))
14309 case V2SImode: pattern = "%08x"; break;
14310 case V4HImode: pattern = "%04x"; break;
14311 case V8QImode: pattern = "%02x"; break;
14315 fprintf (file, "0x");
14316 for (i = CONST_VECTOR_NUNITS (x); i--;)
14320 element = CONST_VECTOR_ELT (x, i);
14321 fprintf (file, pattern, INTVAL (element));
14328 arm_output_load_gr (rtx *operands)
14335 if (GET_CODE (operands [1]) != MEM
14336 || GET_CODE (sum = XEXP (operands [1], 0)) != PLUS
14337 || GET_CODE (reg = XEXP (sum, 0)) != REG
14338 || GET_CODE (offset = XEXP (sum, 1)) != CONST_INT
14339 || ((INTVAL (offset) < 1024) && (INTVAL (offset) > -1024)))
14340 return "wldrw%?\t%0, %1";
14342 /* Fix up an out-of-range load of a GR register. */
14343 output_asm_insn ("str%?\t%0, [sp, #-4]!\t@ Start of GR load expansion", & reg);
14344 wcgr = operands[0];
14346 output_asm_insn ("ldr%?\t%0, %1", operands);
14348 operands[0] = wcgr;
14350 output_asm_insn ("tmcr%?\t%0, %1", operands);
14351 output_asm_insn ("ldr%?\t%0, [sp], #4\t@ End of GR load expansion", & reg);
14357 arm_struct_value_rtx (tree fntype ATTRIBUTE_UNUSED,
14358 int incoming ATTRIBUTE_UNUSED)
14361 /* FIXME: The ARM backend has special code to handle structure
14362 returns, and will reserve its own hidden first argument. So
14363 if this macro is enabled a *second* hidden argument will be
14364 reserved, which will break binary compatibility with old
14365 toolchains and also thunk handling. One day this should be
14369 /* Register in which address to store a structure value
14370 is passed to a function. */
14371 return gen_rtx_REG (Pmode, ARG_REGISTER (1));
14375 /* Worker function for TARGET_SETUP_INCOMING_VARARGS.
14377 On the ARM, PRETEND_SIZE is set in order to have the prologue push the last
14378 named arg and all anonymous args onto the stack.
14379 XXX I know the prologue shouldn't be pushing registers, but it is faster
14383 arm_setup_incoming_varargs (CUMULATIVE_ARGS *cum,
14384 enum machine_mode mode ATTRIBUTE_UNUSED,
14385 tree type ATTRIBUTE_UNUSED,
14387 int second_time ATTRIBUTE_UNUSED)
14389 cfun->machine->uses_anonymous_args = 1;
14390 if (cum->nregs < NUM_ARG_REGS)
14391 *pretend_size = (NUM_ARG_REGS - cum->nregs) * UNITS_PER_WORD;
14394 /* Return nonzero if the CONSUMER instruction (a store) does not need
14395 PRODUCER's value to calculate the address. */
14398 arm_no_early_store_addr_dep (rtx producer, rtx consumer)
14400 rtx value = PATTERN (producer);
14401 rtx addr = PATTERN (consumer);
14403 if (GET_CODE (value) == COND_EXEC)
14404 value = COND_EXEC_CODE (value);
14405 if (GET_CODE (value) == PARALLEL)
14406 value = XVECEXP (value, 0, 0);
14407 value = XEXP (value, 0);
14408 if (GET_CODE (addr) == COND_EXEC)
14409 addr = COND_EXEC_CODE (addr);
14410 if (GET_CODE (addr) == PARALLEL)
14411 addr = XVECEXP (addr, 0, 0);
14412 addr = XEXP (addr, 0);
14414 return !reg_overlap_mentioned_p (value, addr);
14417 /* Return nonzero if the CONSUMER instruction (an ALU op) does not
14418 have an early register shift value or amount dependency on the
14419 result of PRODUCER. */
14422 arm_no_early_alu_shift_dep (rtx producer, rtx consumer)
14424 rtx value = PATTERN (producer);
14425 rtx op = PATTERN (consumer);
14428 if (GET_CODE (value) == COND_EXEC)
14429 value = COND_EXEC_CODE (value);
14430 if (GET_CODE (value) == PARALLEL)
14431 value = XVECEXP (value, 0, 0);
14432 value = XEXP (value, 0);
14433 if (GET_CODE (op) == COND_EXEC)
14434 op = COND_EXEC_CODE (op);
14435 if (GET_CODE (op) == PARALLEL)
14436 op = XVECEXP (op, 0, 0);
14439 early_op = XEXP (op, 0);
14440 /* This is either an actual independent shift, or a shift applied to
14441 the first operand of another operation. We want the whole shift
14443 if (GET_CODE (early_op) == REG)
14446 return !reg_overlap_mentioned_p (value, early_op);
14449 /* Return nonzero if the CONSUMER instruction (an ALU op) does not
14450 have an early register shift value dependency on the result of
14454 arm_no_early_alu_shift_value_dep (rtx producer, rtx consumer)
14456 rtx value = PATTERN (producer);
14457 rtx op = PATTERN (consumer);
14460 if (GET_CODE (value) == COND_EXEC)
14461 value = COND_EXEC_CODE (value);
14462 if (GET_CODE (value) == PARALLEL)
14463 value = XVECEXP (value, 0, 0);
14464 value = XEXP (value, 0);
14465 if (GET_CODE (op) == COND_EXEC)
14466 op = COND_EXEC_CODE (op);
14467 if (GET_CODE (op) == PARALLEL)
14468 op = XVECEXP (op, 0, 0);
14471 early_op = XEXP (op, 0);
14473 /* This is either an actual independent shift, or a shift applied to
14474 the first operand of another operation. We want the value being
14475 shifted, in either case. */
14476 if (GET_CODE (early_op) != REG)
14477 early_op = XEXP (early_op, 0);
14479 return !reg_overlap_mentioned_p (value, early_op);
14482 /* Return nonzero if the CONSUMER (a mul or mac op) does not
14483 have an early register mult dependency on the result of
14487 arm_no_early_mul_dep (rtx producer, rtx consumer)
14489 rtx value = PATTERN (producer);
14490 rtx op = PATTERN (consumer);
14492 if (GET_CODE (value) == COND_EXEC)
14493 value = COND_EXEC_CODE (value);
14494 if (GET_CODE (value) == PARALLEL)
14495 value = XVECEXP (value, 0, 0);
14496 value = XEXP (value, 0);
14497 if (GET_CODE (op) == COND_EXEC)
14498 op = COND_EXEC_CODE (op);
14499 if (GET_CODE (op) == PARALLEL)
14500 op = XVECEXP (op, 0, 0);
14503 return (GET_CODE (op) == PLUS
14504 && !reg_overlap_mentioned_p (value, XEXP (op, 0)));
14508 /* We can't rely on the caller doing the proper promotion when
14509 using APCS or ATPCS. */
14512 arm_promote_prototypes (tree t ATTRIBUTE_UNUSED)
14514 return !TARGET_AAPCS_BASED;
14518 /* AAPCS based ABIs use short enums by default. */
14521 arm_default_short_enums (void)
14523 return TARGET_AAPCS_BASED;
14527 /* AAPCS requires that anonymous bitfields affect structure alignment. */
14530 arm_align_anon_bitfield (void)
14532 return TARGET_AAPCS_BASED;
14536 /* The generic C++ ABI says 64-bit (long long). The EABI says 32-bit. */
14539 arm_cxx_guard_type (void)
14541 return TARGET_AAPCS_BASED ? integer_type_node : long_long_integer_type_node;
14545 /* The EABI says test the least significan bit of a guard variable. */
14548 arm_cxx_guard_mask_bit (void)
14550 return TARGET_AAPCS_BASED;
14554 /* The EABI specifies that all array cookies are 8 bytes long. */
14557 arm_get_cookie_size (tree type)
14561 if (!TARGET_AAPCS_BASED)
14562 return default_cxx_get_cookie_size (type);
14564 size = build_int_2 (8, 0);
14565 TREE_TYPE (size) = sizetype;
14570 /* The EABI says that array cookies should also contain the element size. */
14573 arm_cookie_has_size (void)
14575 return TARGET_AAPCS_BASED;