1 /* Output routines for GCC for ARM.
2 Copyright (C) 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001,
3 2002, 2003, 2004 Free Software Foundation, Inc.
4 Contributed by Pieter `Tiggr' Schoenmakers (rcpieter@win.tue.nl)
5 and Martin Simmons (@harleqn.co.uk).
6 More major hacks by Richard Earnshaw (rearnsha@arm.com).
8 This file is part of GCC.
10 GCC is free software; you can redistribute it and/or modify it
11 under the terms of the GNU General Public License as published
12 by the Free Software Foundation; either version 2, or (at your
13 option) any later version.
15 GCC is distributed in the hope that it will be useful, but WITHOUT
16 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
17 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
18 License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GCC; see the file COPYING. If not, write to
22 the Free Software Foundation, 59 Temple Place - Suite 330,
23 Boston, MA 02111-1307, USA. */
27 #include "coretypes.h"
33 #include "hard-reg-set.h"
35 #include "insn-config.h"
36 #include "conditions.h"
38 #include "insn-attr.h"
49 #include "integrate.h"
52 #include "target-def.h"
54 #include "langhooks.h"
56 /* Forward definitions of types. */
57 typedef struct minipool_node Mnode;
58 typedef struct minipool_fixup Mfix;
60 const struct attribute_spec arm_attribute_table[];
62 /* Forward function declarations. */
63 static arm_stack_offsets *arm_get_frame_offsets (void);
64 static void arm_add_gc_roots (void);
65 static int arm_gen_constant (enum rtx_code, enum machine_mode, rtx,
66 HOST_WIDE_INT, rtx, rtx, int, int);
67 static unsigned bit_count (unsigned long);
68 static int arm_address_register_rtx_p (rtx, int);
69 static int arm_legitimate_index_p (enum machine_mode, rtx, RTX_CODE, int);
70 static int thumb_base_register_rtx_p (rtx, enum machine_mode, int);
71 inline static int thumb_index_register_rtx_p (rtx, int);
72 static int thumb_far_jump_used_p (void);
73 static bool thumb_force_lr_save (void);
74 static unsigned long thumb_compute_save_reg_mask (void);
75 static int const_ok_for_op (HOST_WIDE_INT, enum rtx_code);
76 static rtx emit_multi_reg_push (int);
77 static rtx emit_sfm (int, int);
79 static bool arm_assemble_integer (rtx, unsigned int, int);
81 static const char *fp_const_from_val (REAL_VALUE_TYPE *);
82 static arm_cc get_arm_condition_code (rtx);
83 static HOST_WIDE_INT int_log2 (HOST_WIDE_INT);
84 static rtx is_jump_table (rtx);
85 static const char *output_multi_immediate (rtx *, const char *, const char *,
87 static void print_multi_reg (FILE *, const char *, int, int);
88 static const char *shift_op (rtx, HOST_WIDE_INT *);
89 static struct machine_function *arm_init_machine_status (void);
90 static int number_of_first_bit_set (int);
91 static void replace_symbols_in_block (tree, rtx, rtx);
92 static void thumb_exit (FILE *, int);
93 static void thumb_pushpop (FILE *, int, int, int *, int);
94 static rtx is_jump_table (rtx);
95 static HOST_WIDE_INT get_jump_table_size (rtx);
96 static Mnode *move_minipool_fix_forward_ref (Mnode *, Mnode *, HOST_WIDE_INT);
97 static Mnode *add_minipool_forward_ref (Mfix *);
98 static Mnode *move_minipool_fix_backward_ref (Mnode *, Mnode *, HOST_WIDE_INT);
99 static Mnode *add_minipool_backward_ref (Mfix *);
100 static void assign_minipool_offsets (Mfix *);
101 static void arm_print_value (FILE *, rtx);
102 static void dump_minipool (rtx);
103 static int arm_barrier_cost (rtx);
104 static Mfix *create_fix_barrier (Mfix *, HOST_WIDE_INT);
105 static void push_minipool_barrier (rtx, HOST_WIDE_INT);
106 static void push_minipool_fix (rtx, HOST_WIDE_INT, rtx *, enum machine_mode,
108 static void arm_reorg (void);
109 static bool note_invalid_constants (rtx, HOST_WIDE_INT, int);
110 static int current_file_function_operand (rtx);
111 static unsigned long arm_compute_save_reg0_reg12_mask (void);
112 static unsigned long arm_compute_save_reg_mask (void);
113 static unsigned long arm_isr_value (tree);
114 static unsigned long arm_compute_func_type (void);
115 static tree arm_handle_fndecl_attribute (tree *, tree, tree, int, bool *);
116 static tree arm_handle_isr_attribute (tree *, tree, tree, int, bool *);
117 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
118 static tree arm_handle_notshared_attribute (tree *, tree, tree, int, bool *);
120 static void arm_output_function_epilogue (FILE *, HOST_WIDE_INT);
121 static void arm_output_function_prologue (FILE *, HOST_WIDE_INT);
122 static void thumb_output_function_prologue (FILE *, HOST_WIDE_INT);
123 static int arm_comp_type_attributes (tree, tree);
124 static void arm_set_default_type_attributes (tree);
125 static int arm_adjust_cost (rtx, rtx, rtx, int);
126 static int count_insns_for_constant (HOST_WIDE_INT, int);
127 static int arm_get_strip_length (int);
128 static bool arm_function_ok_for_sibcall (tree, tree);
129 static void arm_internal_label (FILE *, const char *, unsigned long);
130 static void arm_output_mi_thunk (FILE *, tree, HOST_WIDE_INT, HOST_WIDE_INT,
132 static int arm_rtx_costs_1 (rtx, enum rtx_code, enum rtx_code);
133 static bool arm_size_rtx_costs (rtx, int, int, int *);
134 static bool arm_slowmul_rtx_costs (rtx, int, int, int *);
135 static bool arm_fastmul_rtx_costs (rtx, int, int, int *);
136 static bool arm_xscale_rtx_costs (rtx, int, int, int *);
137 static bool arm_9e_rtx_costs (rtx, int, int, int *);
138 static int arm_address_cost (rtx);
139 static bool arm_memory_load_p (rtx);
140 static bool arm_cirrus_insn_p (rtx);
141 static void cirrus_reorg (rtx);
142 static void arm_init_builtins (void);
143 static rtx arm_expand_builtin (tree, rtx, rtx, enum machine_mode, int);
144 static void arm_init_iwmmxt_builtins (void);
145 static rtx safe_vector_operand (rtx, enum machine_mode);
146 static rtx arm_expand_binop_builtin (enum insn_code, tree, rtx);
147 static rtx arm_expand_unop_builtin (enum insn_code, tree, rtx, int);
148 static rtx arm_expand_builtin (tree, rtx, rtx, enum machine_mode, int);
149 static void emit_constant_insn (rtx cond, rtx pattern);
152 static void arm_encode_section_info (tree, rtx, int);
155 static void aof_globalize_label (FILE *, const char *);
156 static void aof_dump_imports (FILE *);
157 static void aof_dump_pic_table (FILE *);
158 static void aof_file_start (void);
159 static void aof_file_end (void);
161 static rtx arm_struct_value_rtx (tree, int);
162 static void arm_setup_incoming_varargs (CUMULATIVE_ARGS *, enum machine_mode,
164 static bool arm_pass_by_reference (CUMULATIVE_ARGS *,
165 enum machine_mode, tree, bool);
166 static bool arm_promote_prototypes (tree);
167 static bool arm_default_short_enums (void);
168 static bool arm_align_anon_bitfield (void);
170 static tree arm_cxx_guard_type (void);
171 static bool arm_cxx_guard_mask_bit (void);
172 static tree arm_get_cookie_size (tree);
173 static bool arm_cookie_has_size (void);
174 static bool arm_cxx_cdtor_returns_this (void);
175 static bool arm_cxx_key_method_may_be_inline (void);
176 static bool arm_cxx_export_class_data (void);
177 static void arm_init_libfuncs (void);
178 static unsigned HOST_WIDE_INT arm_shift_truncation_mask (enum machine_mode);
180 /* Initialize the GCC target structure. */
181 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
182 #undef TARGET_MERGE_DECL_ATTRIBUTES
183 #define TARGET_MERGE_DECL_ATTRIBUTES merge_dllimport_decl_attributes
186 #undef TARGET_ATTRIBUTE_TABLE
187 #define TARGET_ATTRIBUTE_TABLE arm_attribute_table
190 #undef TARGET_ASM_BYTE_OP
191 #define TARGET_ASM_BYTE_OP "\tDCB\t"
192 #undef TARGET_ASM_ALIGNED_HI_OP
193 #define TARGET_ASM_ALIGNED_HI_OP "\tDCW\t"
194 #undef TARGET_ASM_ALIGNED_SI_OP
195 #define TARGET_ASM_ALIGNED_SI_OP "\tDCD\t"
196 #undef TARGET_ASM_GLOBALIZE_LABEL
197 #define TARGET_ASM_GLOBALIZE_LABEL aof_globalize_label
198 #undef TARGET_ASM_FILE_START
199 #define TARGET_ASM_FILE_START aof_file_start
200 #undef TARGET_ASM_FILE_END
201 #define TARGET_ASM_FILE_END aof_file_end
203 #undef TARGET_ASM_ALIGNED_SI_OP
204 #define TARGET_ASM_ALIGNED_SI_OP NULL
205 #undef TARGET_ASM_INTEGER
206 #define TARGET_ASM_INTEGER arm_assemble_integer
209 #undef TARGET_ASM_FUNCTION_PROLOGUE
210 #define TARGET_ASM_FUNCTION_PROLOGUE arm_output_function_prologue
212 #undef TARGET_ASM_FUNCTION_EPILOGUE
213 #define TARGET_ASM_FUNCTION_EPILOGUE arm_output_function_epilogue
215 #undef TARGET_COMP_TYPE_ATTRIBUTES
216 #define TARGET_COMP_TYPE_ATTRIBUTES arm_comp_type_attributes
218 #undef TARGET_SET_DEFAULT_TYPE_ATTRIBUTES
219 #define TARGET_SET_DEFAULT_TYPE_ATTRIBUTES arm_set_default_type_attributes
221 #undef TARGET_SCHED_ADJUST_COST
222 #define TARGET_SCHED_ADJUST_COST arm_adjust_cost
224 #undef TARGET_ENCODE_SECTION_INFO
226 #define TARGET_ENCODE_SECTION_INFO arm_pe_encode_section_info
228 #define TARGET_ENCODE_SECTION_INFO arm_encode_section_info
231 #undef TARGET_STRIP_NAME_ENCODING
232 #define TARGET_STRIP_NAME_ENCODING arm_strip_name_encoding
234 #undef TARGET_ASM_INTERNAL_LABEL
235 #define TARGET_ASM_INTERNAL_LABEL arm_internal_label
237 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
238 #define TARGET_FUNCTION_OK_FOR_SIBCALL arm_function_ok_for_sibcall
240 #undef TARGET_ASM_OUTPUT_MI_THUNK
241 #define TARGET_ASM_OUTPUT_MI_THUNK arm_output_mi_thunk
242 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
243 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK default_can_output_mi_thunk_no_vcall
245 /* This will be overridden in arm_override_options. */
246 #undef TARGET_RTX_COSTS
247 #define TARGET_RTX_COSTS arm_slowmul_rtx_costs
248 #undef TARGET_ADDRESS_COST
249 #define TARGET_ADDRESS_COST arm_address_cost
251 #undef TARGET_SHIFT_TRUNCATION_MASK
252 #define TARGET_SHIFT_TRUNCATION_MASK arm_shift_truncation_mask
253 #undef TARGET_VECTOR_MODE_SUPPORTED_P
254 #define TARGET_VECTOR_MODE_SUPPORTED_P arm_vector_mode_supported_p
256 #undef TARGET_MACHINE_DEPENDENT_REORG
257 #define TARGET_MACHINE_DEPENDENT_REORG arm_reorg
259 #undef TARGET_INIT_BUILTINS
260 #define TARGET_INIT_BUILTINS arm_init_builtins
261 #undef TARGET_EXPAND_BUILTIN
262 #define TARGET_EXPAND_BUILTIN arm_expand_builtin
264 #undef TARGET_INIT_LIBFUNCS
265 #define TARGET_INIT_LIBFUNCS arm_init_libfuncs
267 #undef TARGET_PROMOTE_FUNCTION_ARGS
268 #define TARGET_PROMOTE_FUNCTION_ARGS hook_bool_tree_true
269 #undef TARGET_PROMOTE_FUNCTION_RETURN
270 #define TARGET_PROMOTE_FUNCTION_RETURN hook_bool_tree_true
271 #undef TARGET_PROMOTE_PROTOTYPES
272 #define TARGET_PROMOTE_PROTOTYPES arm_promote_prototypes
273 #undef TARGET_PASS_BY_REFERENCE
274 #define TARGET_PASS_BY_REFERENCE arm_pass_by_reference
276 #undef TARGET_STRUCT_VALUE_RTX
277 #define TARGET_STRUCT_VALUE_RTX arm_struct_value_rtx
279 #undef TARGET_SETUP_INCOMING_VARARGS
280 #define TARGET_SETUP_INCOMING_VARARGS arm_setup_incoming_varargs
282 #undef TARGET_DEFAULT_SHORT_ENUMS
283 #define TARGET_DEFAULT_SHORT_ENUMS arm_default_short_enums
285 #undef TARGET_ALIGN_ANON_BITFIELD
286 #define TARGET_ALIGN_ANON_BITFIELD arm_align_anon_bitfield
288 #undef TARGET_CXX_GUARD_TYPE
289 #define TARGET_CXX_GUARD_TYPE arm_cxx_guard_type
291 #undef TARGET_CXX_GUARD_MASK_BIT
292 #define TARGET_CXX_GUARD_MASK_BIT arm_cxx_guard_mask_bit
294 #undef TARGET_CXX_GET_COOKIE_SIZE
295 #define TARGET_CXX_GET_COOKIE_SIZE arm_get_cookie_size
297 #undef TARGET_CXX_COOKIE_HAS_SIZE
298 #define TARGET_CXX_COOKIE_HAS_SIZE arm_cookie_has_size
300 #undef TARGET_CXX_CDTOR_RETURNS_THIS
301 #define TARGET_CXX_CDTOR_RETURNS_THIS arm_cxx_cdtor_returns_this
303 #undef TARGET_CXX_KEY_METHOD_MAY_BE_INLINE
304 #define TARGET_CXX_KEY_METHOD_MAY_BE_INLINE arm_cxx_key_method_may_be_inline
306 #undef TARGET_CXX_EXPORT_CLASS_DATA
307 #define TARGET_CXX_EXPORT_CLASS_DATA arm_cxx_export_class_data
309 struct gcc_target targetm = TARGET_INITIALIZER;
311 /* Obstack for minipool constant handling. */
312 static struct obstack minipool_obstack;
313 static char * minipool_startobj;
315 /* The maximum number of insns skipped which
316 will be conditionalised if possible. */
317 static int max_insns_skipped = 5;
319 extern FILE * asm_out_file;
321 /* True if we are currently building a constant table. */
322 int making_const_table;
324 /* Define the information needed to generate branch insns. This is
325 stored from the compare operation. */
326 rtx arm_compare_op0, arm_compare_op1;
328 /* The processor for which instructions should be scheduled. */
329 enum processor_type arm_tune = arm_none;
331 /* Which floating point model to use. */
332 enum arm_fp_model arm_fp_model;
334 /* Which floating point hardware is available. */
335 enum fputype arm_fpu_arch;
337 /* Which floating point hardware to schedule for. */
338 enum fputype arm_fpu_tune;
340 /* Whether to use floating point hardware. */
341 enum float_abi_type arm_float_abi;
343 /* Which ABI to use. */
344 enum arm_abi_type arm_abi;
346 /* Set by the -mfpu=... option. */
347 const char * target_fpu_name = NULL;
349 /* Set by the -mfpe=... option. */
350 const char * target_fpe_name = NULL;
352 /* Set by the -mfloat-abi=... option. */
353 const char * target_float_abi_name = NULL;
355 /* Set by the legacy -mhard-float and -msoft-float options. */
356 const char * target_float_switch = NULL;
358 /* Set by the -mabi=... option. */
359 const char * target_abi_name = NULL;
361 /* Used to parse -mstructure_size_boundary command line option. */
362 const char * structure_size_string = NULL;
363 int arm_structure_size_boundary = DEFAULT_STRUCTURE_SIZE_BOUNDARY;
365 /* Bit values used to identify processor capabilities. */
366 #define FL_CO_PROC (1 << 0) /* Has external co-processor bus */
367 #define FL_ARCH3M (1 << 1) /* Extended multiply */
368 #define FL_MODE26 (1 << 2) /* 26-bit mode support */
369 #define FL_MODE32 (1 << 3) /* 32-bit mode support */
370 #define FL_ARCH4 (1 << 4) /* Architecture rel 4 */
371 #define FL_ARCH5 (1 << 5) /* Architecture rel 5 */
372 #define FL_THUMB (1 << 6) /* Thumb aware */
373 #define FL_LDSCHED (1 << 7) /* Load scheduling necessary */
374 #define FL_STRONG (1 << 8) /* StrongARM */
375 #define FL_ARCH5E (1 << 9) /* DSP extensions to v5 */
376 #define FL_XSCALE (1 << 10) /* XScale */
377 #define FL_CIRRUS (1 << 11) /* Cirrus/DSP. */
378 #define FL_ARCH6 (1 << 12) /* Architecture rel 6. Adds
379 media instructions. */
380 #define FL_VFPV2 (1 << 13) /* Vector Floating Point V2. */
382 #define FL_IWMMXT (1 << 29) /* XScale v2 or "Intel Wireless MMX technology". */
384 #define FL_FOR_ARCH2 0
385 #define FL_FOR_ARCH3 FL_MODE32
386 #define FL_FOR_ARCH3M (FL_FOR_ARCH3 | FL_ARCH3M)
387 #define FL_FOR_ARCH4 (FL_FOR_ARCH3M | FL_ARCH4)
388 #define FL_FOR_ARCH4T (FL_FOR_ARCH4 | FL_THUMB)
389 #define FL_FOR_ARCH5 (FL_FOR_ARCH4 | FL_ARCH5)
390 #define FL_FOR_ARCH5T (FL_FOR_ARCH5 | FL_THUMB)
391 #define FL_FOR_ARCH5E (FL_FOR_ARCH5 | FL_ARCH5E)
392 #define FL_FOR_ARCH5TE (FL_FOR_ARCH5E | FL_THUMB)
393 #define FL_FOR_ARCH5TEJ FL_FOR_ARCH5TE
394 #define FL_FOR_ARCH6 (FL_FOR_ARCH5TE | FL_ARCH6)
395 #define FL_FOR_ARCH6J FL_FOR_ARCH6
396 #define FL_FOR_ARCH6K FL_FOR_ARCH6
397 #define FL_FOR_ARCH6Z FL_FOR_ARCH6
398 #define FL_FOR_ARCH6ZK FL_FOR_ARCH6
400 /* The bits in this mask specify which
401 instructions we are allowed to generate. */
402 static unsigned long insn_flags = 0;
404 /* The bits in this mask specify which instruction scheduling options should
406 static unsigned long tune_flags = 0;
408 /* The following are used in the arm.md file as equivalents to bits
409 in the above two flag variables. */
411 /* Nonzero if this chip supports the ARM Architecture 3M extensions. */
414 /* Nonzero if this chip supports the ARM Architecture 4 extensions. */
417 /* Nonzero if this chip supports the ARM Architecture 4t extensions. */
420 /* Nonzero if this chip supports the ARM Architecture 5 extensions. */
423 /* Nonzero if this chip supports the ARM Architecture 5E extensions. */
426 /* Nonzero if this chip supports the ARM Architecture 6 extensions. */
429 /* Nonzero if this chip can benefit from load scheduling. */
430 int arm_ld_sched = 0;
432 /* Nonzero if this chip is a StrongARM. */
433 int arm_is_strong = 0;
435 /* Nonzero if this chip is a Cirrus variant. */
436 int arm_arch_cirrus = 0;
438 /* Nonzero if this chip supports Intel Wireless MMX technology. */
439 int arm_arch_iwmmxt = 0;
441 /* Nonzero if this chip is an XScale. */
442 int arm_arch_xscale = 0;
444 /* Nonzero if tuning for XScale */
445 int arm_tune_xscale = 0;
447 /* Nonzero if this chip is an ARM6 or an ARM7. */
448 int arm_is_6_or_7 = 0;
450 /* Nonzero if generating Thumb instructions. */
453 /* Nonzero if we should define __THUMB_INTERWORK__ in the
455 XXX This is a bit of a hack, it's intended to help work around
456 problems in GLD which doesn't understand that armv5t code is
457 interworking clean. */
458 int arm_cpp_interwork = 0;
460 /* In case of a PRE_INC, POST_INC, PRE_DEC, POST_DEC memory reference, we
461 must report the mode of the memory reference from PRINT_OPERAND to
462 PRINT_OPERAND_ADDRESS. */
463 enum machine_mode output_memory_reference_mode;
465 /* The register number to be used for the PIC offset register. */
466 const char * arm_pic_register_string = NULL;
467 int arm_pic_register = INVALID_REGNUM;
469 /* Set to 1 when a return insn is output, this means that the epilogue
471 int return_used_this_function;
473 /* Set to 1 after arm_reorg has started. Reset to start at the start of
474 the next function. */
475 static int after_arm_reorg = 0;
477 /* The maximum number of insns to be used when loading a constant. */
478 static int arm_constant_limit = 3;
480 /* For an explanation of these variables, see final_prescan_insn below. */
482 enum arm_cond_code arm_current_cc;
484 int arm_target_label;
486 /* The condition codes of the ARM, and the inverse function. */
487 static const char * const arm_condition_codes[] =
489 "eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc",
490 "hi", "ls", "ge", "lt", "gt", "le", "al", "nv"
493 #define streq(string1, string2) (strcmp (string1, string2) == 0)
495 /* Initialization code. */
499 const char *const name;
500 enum processor_type core;
502 const unsigned long flags;
503 bool (* rtx_costs) (rtx, int, int, int *);
506 /* Not all of these give usefully different compilation alternatives,
507 but there is no simple way of generalizing them. */
508 static const struct processors all_cores[] =
511 #define ARM_CORE(NAME, IDENT, ARCH, FLAGS, COSTS) \
512 {NAME, arm_none, #ARCH, FLAGS | FL_FOR_ARCH##ARCH, arm_##COSTS##_rtx_costs},
513 #include "arm-cores.def"
515 {NULL, arm_none, NULL, 0, NULL}
518 static const struct processors all_architectures[] =
520 /* ARM Architectures */
521 /* We don't specify rtx_costs here as it will be figured out
524 {"armv2", arm2, "2", FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH2, NULL},
525 {"armv2a", arm2, "2", FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH2, NULL},
526 {"armv3", arm6, "3", FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH3, NULL},
527 {"armv3m", arm7m, "3M", FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH3M, NULL},
528 {"armv4", arm7tdmi, "4", FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH4, NULL},
529 /* Strictly, FL_MODE26 is a permitted option for v4t, but there are no
530 implementations that support it, so we will leave it out for now. */
531 {"armv4t", arm7tdmi, "4T", FL_CO_PROC | FL_FOR_ARCH4T, NULL},
532 {"armv5", arm10tdmi, "5", FL_CO_PROC | FL_FOR_ARCH5, NULL},
533 {"armv5t", arm10tdmi, "5T", FL_CO_PROC | FL_FOR_ARCH5T, NULL},
534 {"armv5e", arm1026ejs, "5E", FL_CO_PROC | FL_FOR_ARCH5E, NULL},
535 {"armv5te", arm1026ejs, "5TE", FL_CO_PROC | FL_FOR_ARCH5TE, NULL},
536 {"armv6", arm1136js, "6", FL_CO_PROC | FL_FOR_ARCH6, NULL},
537 {"armv6j", arm1136js, "6J", FL_CO_PROC | FL_FOR_ARCH6J, NULL},
538 {"armv6k", mpcore, "6K", FL_CO_PROC | FL_FOR_ARCH6K, NULL},
539 {"armv6z", arm1176jzs, "6Z", FL_CO_PROC | FL_FOR_ARCH6Z, NULL},
540 {"armv6zk", arm1176jzs, "6ZK", FL_CO_PROC | FL_FOR_ARCH6ZK, NULL},
541 {"ep9312", ep9312, "4T", FL_LDSCHED | FL_CIRRUS | FL_FOR_ARCH4, NULL},
542 {"iwmmxt", iwmmxt, "5TE", FL_LDSCHED | FL_STRONG | FL_FOR_ARCH5TE | FL_XSCALE | FL_IWMMXT , NULL},
543 {NULL, arm_none, NULL, 0 , NULL}
546 /* This is a magic structure. The 'string' field is magically filled in
547 with a pointer to the value specified by the user on the command line
548 assuming that the user has specified such a value. */
550 struct arm_cpu_select arm_select[] =
552 /* string name processors */
553 { NULL, "-mcpu=", all_cores },
554 { NULL, "-march=", all_architectures },
555 { NULL, "-mtune=", all_cores }
559 /* The name of the proprocessor macro to define for this architecture. */
561 char arm_arch_name[] = "__ARM_ARCH_0UNK__";
570 /* Available values for for -mfpu=. */
572 static const struct fpu_desc all_fpus[] =
574 {"fpa", FPUTYPE_FPA},
575 {"fpe2", FPUTYPE_FPA_EMU2},
576 {"fpe3", FPUTYPE_FPA_EMU2},
577 {"maverick", FPUTYPE_MAVERICK},
582 /* Floating point models used by the different hardware.
583 See fputype in arm.h. */
585 static const enum fputype fp_model_for_fpu[] =
587 /* No FP hardware. */
588 ARM_FP_MODEL_UNKNOWN, /* FPUTYPE_NONE */
589 ARM_FP_MODEL_FPA, /* FPUTYPE_FPA */
590 ARM_FP_MODEL_FPA, /* FPUTYPE_FPA_EMU2 */
591 ARM_FP_MODEL_FPA, /* FPUTYPE_FPA_EMU3 */
592 ARM_FP_MODEL_MAVERICK, /* FPUTYPE_MAVERICK */
593 ARM_FP_MODEL_VFP /* FPUTYPE_VFP */
600 enum float_abi_type abi_type;
604 /* Available values for -mfloat-abi=. */
606 static const struct float_abi all_float_abis[] =
608 {"soft", ARM_FLOAT_ABI_SOFT},
609 {"softfp", ARM_FLOAT_ABI_SOFTFP},
610 {"hard", ARM_FLOAT_ABI_HARD}
617 enum arm_abi_type abi_type;
621 /* Available values for -mabi=. */
623 static const struct abi_name arm_all_abis[] =
625 {"apcs-gnu", ARM_ABI_APCS},
626 {"atpcs", ARM_ABI_ATPCS},
627 {"aapcs", ARM_ABI_AAPCS},
628 {"iwmmxt", ARM_ABI_IWMMXT}
631 /* Return the number of bits set in VALUE. */
633 bit_count (unsigned long value)
635 unsigned long count = 0;
640 value &= value - 1; /* Clear the least-significant set bit. */
646 /* Set up library functions unique to ARM. */
649 arm_init_libfuncs (void)
651 /* There are no special library functions unless we are using the
656 /* The functions below are described in Section 4 of the "Run-Time
657 ABI for the ARM architecture", Version 1.0. */
659 /* Double-precision floating-point arithmetic. Table 2. */
660 set_optab_libfunc (add_optab, DFmode, "__aeabi_dadd");
661 set_optab_libfunc (sdiv_optab, DFmode, "__aeabi_ddiv");
662 set_optab_libfunc (smul_optab, DFmode, "__aeabi_dmul");
663 set_optab_libfunc (neg_optab, DFmode, "__aeabi_dneg");
664 set_optab_libfunc (sub_optab, DFmode, "__aeabi_dsub");
666 /* Double-precision comparisons. Table 3. */
667 set_optab_libfunc (eq_optab, DFmode, "__aeabi_dcmpeq");
668 set_optab_libfunc (ne_optab, DFmode, NULL);
669 set_optab_libfunc (lt_optab, DFmode, "__aeabi_dcmplt");
670 set_optab_libfunc (le_optab, DFmode, "__aeabi_dcmple");
671 set_optab_libfunc (ge_optab, DFmode, "__aeabi_dcmpge");
672 set_optab_libfunc (gt_optab, DFmode, "__aeabi_dcmpgt");
673 set_optab_libfunc (unord_optab, DFmode, "__aeabi_dcmpun");
675 /* Single-precision floating-point arithmetic. Table 4. */
676 set_optab_libfunc (add_optab, SFmode, "__aeabi_fadd");
677 set_optab_libfunc (sdiv_optab, SFmode, "__aeabi_fdiv");
678 set_optab_libfunc (smul_optab, SFmode, "__aeabi_fmul");
679 set_optab_libfunc (neg_optab, SFmode, "__aeabi_fneg");
680 set_optab_libfunc (sub_optab, SFmode, "__aeabi_fsub");
682 /* Single-precision comparisons. Table 5. */
683 set_optab_libfunc (eq_optab, SFmode, "__aeabi_fcmpeq");
684 set_optab_libfunc (ne_optab, SFmode, NULL);
685 set_optab_libfunc (lt_optab, SFmode, "__aeabi_fcmplt");
686 set_optab_libfunc (le_optab, SFmode, "__aeabi_fcmple");
687 set_optab_libfunc (ge_optab, SFmode, "__aeabi_fcmpge");
688 set_optab_libfunc (gt_optab, SFmode, "__aeabi_fcmpgt");
689 set_optab_libfunc (unord_optab, SFmode, "__aeabi_fcmpun");
691 /* Floating-point to integer conversions. Table 6. */
692 set_conv_libfunc (sfix_optab, SImode, DFmode, "__aeabi_d2iz");
693 set_conv_libfunc (ufix_optab, SImode, DFmode, "__aeabi_d2uiz");
694 set_conv_libfunc (sfix_optab, DImode, DFmode, "__aeabi_d2lz");
695 set_conv_libfunc (ufix_optab, DImode, DFmode, "__aeabi_d2ulz");
696 set_conv_libfunc (sfix_optab, SImode, SFmode, "__aeabi_f2iz");
697 set_conv_libfunc (ufix_optab, SImode, SFmode, "__aeabi_f2uiz");
698 set_conv_libfunc (sfix_optab, DImode, SFmode, "__aeabi_f2lz");
699 set_conv_libfunc (ufix_optab, DImode, SFmode, "__aeabi_f2ulz");
701 /* Conversions between floating types. Table 7. */
702 set_conv_libfunc (trunc_optab, SFmode, DFmode, "__aeabi_d2f");
703 set_conv_libfunc (sext_optab, DFmode, SFmode, "__aeabi_f2d");
705 /* Integer to floating-point conversions. Table 8. */
706 set_conv_libfunc (sfloat_optab, DFmode, SImode, "__aeabi_i2d");
707 set_conv_libfunc (ufloat_optab, DFmode, SImode, "__aeabi_ui2d");
708 set_conv_libfunc (sfloat_optab, DFmode, DImode, "__aeabi_l2d");
709 set_conv_libfunc (ufloat_optab, DFmode, DImode, "__aeabi_ul2d");
710 set_conv_libfunc (sfloat_optab, SFmode, SImode, "__aeabi_i2f");
711 set_conv_libfunc (ufloat_optab, SFmode, SImode, "__aeabi_ui2f");
712 set_conv_libfunc (sfloat_optab, SFmode, DImode, "__aeabi_l2f");
713 set_conv_libfunc (ufloat_optab, SFmode, DImode, "__aeabi_ul2f");
715 /* Long long. Table 9. */
716 set_optab_libfunc (smul_optab, DImode, "__aeabi_lmul");
717 set_optab_libfunc (sdivmod_optab, DImode, "__aeabi_ldivmod");
718 set_optab_libfunc (udivmod_optab, DImode, "__aeabi_uldivmod");
719 set_optab_libfunc (ashl_optab, DImode, "__aeabi_llsl");
720 set_optab_libfunc (lshr_optab, DImode, "__aeabi_llsr");
721 set_optab_libfunc (ashr_optab, DImode, "__aeabi_lasr");
722 set_optab_libfunc (cmp_optab, DImode, "__aeabi_lcmp");
723 set_optab_libfunc (ucmp_optab, DImode, "__aeabi_ulcmp");
725 /* Integer (32/32->32) division. \S 4.3.1. */
726 set_optab_libfunc (sdivmod_optab, SImode, "__aeabi_idivmod");
727 set_optab_libfunc (udivmod_optab, SImode, "__aeabi_uidivmod");
729 /* The divmod functions are designed so that they can be used for
730 plain division, even though they return both the quotient and the
731 remainder. The quotient is returned in the usual location (i.e.,
732 r0 for SImode, {r0, r1} for DImode), just as would be expected
733 for an ordinary division routine. Because the AAPCS calling
734 conventions specify that all of { r0, r1, r2, r3 } are
735 callee-saved registers, there is no need to tell the compiler
736 explicitly that those registers are clobbered by these
738 set_optab_libfunc (sdiv_optab, DImode, "__aeabi_ldivmod");
739 set_optab_libfunc (udiv_optab, DImode, "__aeabi_uldivmod");
740 set_optab_libfunc (sdiv_optab, SImode, "__aeabi_idivmod");
741 set_optab_libfunc (udiv_optab, SImode, "__aeabi_uidivmod");
744 /* Fix up any incompatible options that the user has specified.
745 This has now turned into a maze. */
747 arm_override_options (void)
751 /* Set up the flags based on the cpu/architecture selected by the user. */
752 for (i = ARRAY_SIZE (arm_select); i--;)
754 struct arm_cpu_select * ptr = arm_select + i;
756 if (ptr->string != NULL && ptr->string[0] != '\0')
758 const struct processors * sel;
760 for (sel = ptr->processors; sel->name != NULL; sel++)
761 if (streq (ptr->string, sel->name))
763 /* Set the architecture define. */
765 sprintf (arm_arch_name, "__ARM_ARCH_%s__", sel->arch);
767 /* Determine the processor core for which we should
768 tune code-generation. */
769 if (/* -mcpu= is a sensible default. */
771 /* If -march= is used, and -mcpu= has not been used,
772 assume that we should tune for a representative
773 CPU from that architecture. */
775 /* -mtune= overrides -mcpu= and -march=. */
777 arm_tune = (enum processor_type) (sel - ptr->processors);
781 /* If we have been given an architecture and a processor
782 make sure that they are compatible. We only generate
783 a warning though, and we prefer the CPU over the
785 if (insn_flags != 0 && (insn_flags ^ sel->flags))
786 warning ("switch -mcpu=%s conflicts with -march= switch",
789 insn_flags = sel->flags;
795 if (sel->name == NULL)
796 error ("bad value (%s) for %s switch", ptr->string, ptr->name);
800 /* If the user did not specify a processor, choose one for them. */
803 const struct processors * sel;
805 enum processor_type cpu;
807 cpu = TARGET_CPU_DEFAULT;
810 #ifdef SUBTARGET_CPU_DEFAULT
811 /* Use the subtarget default CPU if none was specified by
813 cpu = SUBTARGET_CPU_DEFAULT;
815 /* Default to ARM6. */
819 sel = &all_cores[cpu];
821 insn_flags = sel->flags;
823 /* Now check to see if the user has specified some command line
824 switch that require certain abilities from the cpu. */
827 if (TARGET_INTERWORK || TARGET_THUMB)
829 sought |= (FL_THUMB | FL_MODE32);
831 /* There are no ARM processors that support both APCS-26 and
832 interworking. Therefore we force FL_MODE26 to be removed
833 from insn_flags here (if it was set), so that the search
834 below will always be able to find a compatible processor. */
835 insn_flags &= ~FL_MODE26;
838 if (sought != 0 && ((sought & insn_flags) != sought))
840 /* Try to locate a CPU type that supports all of the abilities
841 of the default CPU, plus the extra abilities requested by
843 for (sel = all_cores; sel->name != NULL; sel++)
844 if ((sel->flags & sought) == (sought | insn_flags))
847 if (sel->name == NULL)
849 unsigned current_bit_count = 0;
850 const struct processors * best_fit = NULL;
852 /* Ideally we would like to issue an error message here
853 saying that it was not possible to find a CPU compatible
854 with the default CPU, but which also supports the command
855 line options specified by the programmer, and so they
856 ought to use the -mcpu=<name> command line option to
857 override the default CPU type.
859 If we cannot find a cpu that has both the
860 characteristics of the default cpu and the given
861 command line options we scan the array again looking
863 for (sel = all_cores; sel->name != NULL; sel++)
864 if ((sel->flags & sought) == sought)
868 count = bit_count (sel->flags & insn_flags);
870 if (count >= current_bit_count)
873 current_bit_count = count;
877 if (best_fit == NULL)
883 insn_flags = sel->flags;
885 sprintf (arm_arch_name, "__ARM_ARCH_%s__", sel->arch);
886 if (arm_tune == arm_none)
887 arm_tune = (enum processor_type) (sel - all_cores);
890 /* The processor for which we should tune should now have been
892 if (arm_tune == arm_none)
895 tune_flags = all_cores[(int)arm_tune].flags;
897 targetm.rtx_costs = arm_size_rtx_costs;
899 targetm.rtx_costs = all_cores[(int)arm_tune].rtx_costs;
901 /* Make sure that the processor choice does not conflict with any of the
902 other command line choices. */
903 if (TARGET_INTERWORK && !(insn_flags & FL_THUMB))
905 warning ("target CPU does not support interworking" );
906 target_flags &= ~ARM_FLAG_INTERWORK;
909 if (TARGET_THUMB && !(insn_flags & FL_THUMB))
911 warning ("target CPU does not support THUMB instructions");
912 target_flags &= ~ARM_FLAG_THUMB;
915 if (TARGET_APCS_FRAME && TARGET_THUMB)
917 /* warning ("ignoring -mapcs-frame because -mthumb was used"); */
918 target_flags &= ~ARM_FLAG_APCS_FRAME;
921 /* TARGET_BACKTRACE calls leaf_function_p, which causes a crash if done
922 from here where no function is being compiled currently. */
923 if ((target_flags & (THUMB_FLAG_LEAF_BACKTRACE | THUMB_FLAG_BACKTRACE))
925 warning ("enabling backtrace support is only meaningful when compiling for the Thumb");
927 if (TARGET_ARM && TARGET_CALLEE_INTERWORKING)
928 warning ("enabling callee interworking support is only meaningful when compiling for the Thumb");
930 if (TARGET_ARM && TARGET_CALLER_INTERWORKING)
931 warning ("enabling caller interworking support is only meaningful when compiling for the Thumb");
933 if (TARGET_APCS_STACK && !TARGET_APCS_FRAME)
935 warning ("-mapcs-stack-check incompatible with -mno-apcs-frame");
936 target_flags |= ARM_FLAG_APCS_FRAME;
939 if (TARGET_POKE_FUNCTION_NAME)
940 target_flags |= ARM_FLAG_APCS_FRAME;
942 if (TARGET_APCS_REENT && flag_pic)
943 error ("-fpic and -mapcs-reent are incompatible");
945 if (TARGET_APCS_REENT)
946 warning ("APCS reentrant code not supported. Ignored");
948 /* If this target is normally configured to use APCS frames, warn if they
949 are turned off and debugging is turned on. */
951 && write_symbols != NO_DEBUG
952 && !TARGET_APCS_FRAME
953 && (TARGET_DEFAULT & ARM_FLAG_APCS_FRAME))
954 warning ("-g with -mno-apcs-frame may not give sensible debugging");
956 /* If stack checking is disabled, we can use r10 as the PIC register,
957 which keeps r9 available. */
959 arm_pic_register = TARGET_APCS_STACK ? 9 : 10;
961 if (TARGET_APCS_FLOAT)
962 warning ("passing floating point arguments in fp regs not yet supported");
964 /* Initialize boolean versions of the flags, for use in the arm.md file. */
965 arm_arch3m = (insn_flags & FL_ARCH3M) != 0;
966 arm_arch4 = (insn_flags & FL_ARCH4) != 0;
967 arm_arch4t = arm_arch4 & ((insn_flags & FL_THUMB) != 0);
968 arm_arch5 = (insn_flags & FL_ARCH5) != 0;
969 arm_arch5e = (insn_flags & FL_ARCH5E) != 0;
970 arm_arch6 = (insn_flags & FL_ARCH6) != 0;
971 arm_arch_xscale = (insn_flags & FL_XSCALE) != 0;
972 arm_arch_cirrus = (insn_flags & FL_CIRRUS) != 0;
974 arm_ld_sched = (tune_flags & FL_LDSCHED) != 0;
975 arm_is_strong = (tune_flags & FL_STRONG) != 0;
976 thumb_code = (TARGET_ARM == 0);
977 arm_is_6_or_7 = (((tune_flags & (FL_MODE26 | FL_MODE32))
978 && !(tune_flags & FL_ARCH4))) != 0;
979 arm_tune_xscale = (tune_flags & FL_XSCALE) != 0;
980 arm_arch_iwmmxt = (insn_flags & FL_IWMMXT) != 0;
982 /* V5 code we generate is completely interworking capable, so we turn off
983 TARGET_INTERWORK here to avoid many tests later on. */
985 /* XXX However, we must pass the right pre-processor defines to CPP
986 or GLD can get confused. This is a hack. */
987 if (TARGET_INTERWORK)
988 arm_cpp_interwork = 1;
991 target_flags &= ~ARM_FLAG_INTERWORK;
995 for (i = 0; i < ARRAY_SIZE (arm_all_abis); i++)
997 if (streq (arm_all_abis[i].name, target_abi_name))
999 arm_abi = arm_all_abis[i].abi_type;
1003 if (i == ARRAY_SIZE (arm_all_abis))
1004 error ("invalid ABI option: -mabi=%s", target_abi_name);
1007 arm_abi = ARM_DEFAULT_ABI;
1009 if (TARGET_IWMMXT && !ARM_DOUBLEWORD_ALIGN)
1010 error ("iwmmxt requires an AAPCS compatible ABI for proper operation");
1012 if (TARGET_IWMMXT_ABI && !TARGET_IWMMXT)
1013 error ("iwmmxt abi requires an iwmmxt capable cpu");
1015 arm_fp_model = ARM_FP_MODEL_UNKNOWN;
1016 if (target_fpu_name == NULL && target_fpe_name != NULL)
1018 if (streq (target_fpe_name, "2"))
1019 target_fpu_name = "fpe2";
1020 else if (streq (target_fpe_name, "3"))
1021 target_fpu_name = "fpe3";
1023 error ("invalid floating point emulation option: -mfpe=%s",
1026 if (target_fpu_name != NULL)
1028 /* The user specified a FPU. */
1029 for (i = 0; i < ARRAY_SIZE (all_fpus); i++)
1031 if (streq (all_fpus[i].name, target_fpu_name))
1033 arm_fpu_arch = all_fpus[i].fpu;
1034 arm_fpu_tune = arm_fpu_arch;
1035 arm_fp_model = fp_model_for_fpu[arm_fpu_arch];
1039 if (arm_fp_model == ARM_FP_MODEL_UNKNOWN)
1040 error ("invalid floating point option: -mfpu=%s", target_fpu_name);
1044 #ifdef FPUTYPE_DEFAULT
1045 /* Use the default if it is specified for this platform. */
1046 arm_fpu_arch = FPUTYPE_DEFAULT;
1047 arm_fpu_tune = FPUTYPE_DEFAULT;
1049 /* Pick one based on CPU type. */
1050 /* ??? Some targets assume FPA is the default.
1051 if ((insn_flags & FL_VFP) != 0)
1052 arm_fpu_arch = FPUTYPE_VFP;
1055 if (arm_arch_cirrus)
1056 arm_fpu_arch = FPUTYPE_MAVERICK;
1058 arm_fpu_arch = FPUTYPE_FPA_EMU2;
1060 if (tune_flags & FL_CO_PROC && arm_fpu_arch == FPUTYPE_FPA_EMU2)
1061 arm_fpu_tune = FPUTYPE_FPA;
1063 arm_fpu_tune = arm_fpu_arch;
1064 arm_fp_model = fp_model_for_fpu[arm_fpu_arch];
1065 if (arm_fp_model == ARM_FP_MODEL_UNKNOWN)
1069 if (target_float_abi_name != NULL)
1071 /* The user specified a FP ABI. */
1072 for (i = 0; i < ARRAY_SIZE (all_float_abis); i++)
1074 if (streq (all_float_abis[i].name, target_float_abi_name))
1076 arm_float_abi = all_float_abis[i].abi_type;
1080 if (i == ARRAY_SIZE (all_float_abis))
1081 error ("invalid floating point abi: -mfloat-abi=%s",
1082 target_float_abi_name);
1084 else if (target_float_switch)
1086 /* This is a bit of a hack to avoid needing target flags for these. */
1087 if (target_float_switch[1] == 'h')
1088 arm_float_abi = ARM_FLOAT_ABI_HARD;
1090 arm_float_abi = ARM_FLOAT_ABI_SOFT;
1093 arm_float_abi = TARGET_DEFAULT_FLOAT_ABI;
1095 if (arm_float_abi == ARM_FLOAT_ABI_HARD && TARGET_VFP)
1096 sorry ("-mfloat-abi=hard and VFP");
1098 /* If soft-float is specified then don't use FPU. */
1099 if (TARGET_SOFT_FLOAT)
1100 arm_fpu_arch = FPUTYPE_NONE;
1102 /* For arm2/3 there is no need to do any scheduling if there is only
1103 a floating point emulator, or we are doing software floating-point. */
1104 if ((TARGET_SOFT_FLOAT
1105 || arm_fpu_tune == FPUTYPE_FPA_EMU2
1106 || arm_fpu_tune == FPUTYPE_FPA_EMU3)
1107 && (tune_flags & FL_MODE32) == 0)
1108 flag_schedule_insns = flag_schedule_insns_after_reload = 0;
1110 /* Override the default structure alignment for AAPCS ABI. */
1111 if (arm_abi == ARM_ABI_AAPCS)
1112 arm_structure_size_boundary = 8;
1114 if (structure_size_string != NULL)
1116 int size = strtol (structure_size_string, NULL, 0);
1118 if (size == 8 || size == 32
1119 || (ARM_DOUBLEWORD_ALIGN && size == 64))
1120 arm_structure_size_boundary = size;
1122 warning ("structure size boundary can only be set to %s",
1123 ARM_DOUBLEWORD_ALIGN ? "8, 32 or 64": "8 or 32");
1126 if (arm_pic_register_string != NULL)
1128 int pic_register = decode_reg_name (arm_pic_register_string);
1131 warning ("-mpic-register= is useless without -fpic");
1133 /* Prevent the user from choosing an obviously stupid PIC register. */
1134 else if (pic_register < 0 || call_used_regs[pic_register]
1135 || pic_register == HARD_FRAME_POINTER_REGNUM
1136 || pic_register == STACK_POINTER_REGNUM
1137 || pic_register >= PC_REGNUM)
1138 error ("unable to use '%s' for PIC register", arm_pic_register_string);
1140 arm_pic_register = pic_register;
1143 if (TARGET_THUMB && flag_schedule_insns)
1145 /* Don't warn since it's on by default in -O2. */
1146 flag_schedule_insns = 0;
1151 /* There's some dispute as to whether this should be 1 or 2. However,
1152 experiments seem to show that in pathological cases a setting of
1153 1 degrades less severely than a setting of 2. This could change if
1154 other parts of the compiler change their behavior. */
1155 arm_constant_limit = 1;
1157 /* If optimizing for size, bump the number of instructions that we
1158 are prepared to conditionally execute (even on a StrongARM). */
1159 max_insns_skipped = 6;
1163 /* For processors with load scheduling, it never costs more than
1164 2 cycles to load a constant, and the load scheduler may well
1165 reduce that to 1. */
1167 arm_constant_limit = 1;
1169 /* On XScale the longer latency of a load makes it more difficult
1170 to achieve a good schedule, so it's faster to synthesize
1171 constants that can be done in two insns. */
1172 if (arm_tune_xscale)
1173 arm_constant_limit = 2;
1175 /* StrongARM has early execution of branches, so a sequence
1176 that is worth skipping is shorter. */
1178 max_insns_skipped = 3;
1181 /* Register global variables with the garbage collector. */
1182 arm_add_gc_roots ();
1186 arm_add_gc_roots (void)
1188 gcc_obstack_init(&minipool_obstack);
1189 minipool_startobj = (char *) obstack_alloc (&minipool_obstack, 0);
1192 /* A table of known ARM exception types.
1193 For use with the interrupt function attribute. */
1197 const char *const arg;
1198 const unsigned long return_value;
1202 static const isr_attribute_arg isr_attribute_args [] =
1204 { "IRQ", ARM_FT_ISR },
1205 { "irq", ARM_FT_ISR },
1206 { "FIQ", ARM_FT_FIQ },
1207 { "fiq", ARM_FT_FIQ },
1208 { "ABORT", ARM_FT_ISR },
1209 { "abort", ARM_FT_ISR },
1210 { "ABORT", ARM_FT_ISR },
1211 { "abort", ARM_FT_ISR },
1212 { "UNDEF", ARM_FT_EXCEPTION },
1213 { "undef", ARM_FT_EXCEPTION },
1214 { "SWI", ARM_FT_EXCEPTION },
1215 { "swi", ARM_FT_EXCEPTION },
1216 { NULL, ARM_FT_NORMAL }
1219 /* Returns the (interrupt) function type of the current
1220 function, or ARM_FT_UNKNOWN if the type cannot be determined. */
1222 static unsigned long
1223 arm_isr_value (tree argument)
1225 const isr_attribute_arg * ptr;
1228 /* No argument - default to IRQ. */
1229 if (argument == NULL_TREE)
1232 /* Get the value of the argument. */
1233 if (TREE_VALUE (argument) == NULL_TREE
1234 || TREE_CODE (TREE_VALUE (argument)) != STRING_CST)
1235 return ARM_FT_UNKNOWN;
1237 arg = TREE_STRING_POINTER (TREE_VALUE (argument));
1239 /* Check it against the list of known arguments. */
1240 for (ptr = isr_attribute_args; ptr->arg != NULL; ptr++)
1241 if (streq (arg, ptr->arg))
1242 return ptr->return_value;
1244 /* An unrecognized interrupt type. */
1245 return ARM_FT_UNKNOWN;
1248 /* Computes the type of the current function. */
1250 static unsigned long
1251 arm_compute_func_type (void)
1253 unsigned long type = ARM_FT_UNKNOWN;
1257 if (TREE_CODE (current_function_decl) != FUNCTION_DECL)
1260 /* Decide if the current function is volatile. Such functions
1261 never return, and many memory cycles can be saved by not storing
1262 register values that will never be needed again. This optimization
1263 was added to speed up context switching in a kernel application. */
1265 && TREE_NOTHROW (current_function_decl)
1266 && TREE_THIS_VOLATILE (current_function_decl))
1267 type |= ARM_FT_VOLATILE;
1269 if (cfun->static_chain_decl != NULL)
1270 type |= ARM_FT_NESTED;
1272 attr = DECL_ATTRIBUTES (current_function_decl);
1274 a = lookup_attribute ("naked", attr);
1276 type |= ARM_FT_NAKED;
1278 a = lookup_attribute ("isr", attr);
1280 a = lookup_attribute ("interrupt", attr);
1283 type |= TARGET_INTERWORK ? ARM_FT_INTERWORKED : ARM_FT_NORMAL;
1285 type |= arm_isr_value (TREE_VALUE (a));
1290 /* Returns the type of the current function. */
1293 arm_current_func_type (void)
1295 if (ARM_FUNC_TYPE (cfun->machine->func_type) == ARM_FT_UNKNOWN)
1296 cfun->machine->func_type = arm_compute_func_type ();
1298 return cfun->machine->func_type;
1301 /* Return 1 if it is possible to return using a single instruction.
1302 If SIBLING is non-null, this is a test for a return before a sibling
1303 call. SIBLING is the call insn, so we can examine its register usage. */
1306 use_return_insn (int iscond, rtx sibling)
1309 unsigned int func_type;
1310 unsigned long saved_int_regs;
1311 unsigned HOST_WIDE_INT stack_adjust;
1312 arm_stack_offsets *offsets;
1314 /* Never use a return instruction before reload has run. */
1315 if (!reload_completed)
1318 func_type = arm_current_func_type ();
1320 /* Naked functions and volatile functions need special
1322 if (func_type & (ARM_FT_VOLATILE | ARM_FT_NAKED))
1325 /* So do interrupt functions that use the frame pointer. */
1326 if (IS_INTERRUPT (func_type) && frame_pointer_needed)
1329 offsets = arm_get_frame_offsets ();
1330 stack_adjust = offsets->outgoing_args - offsets->saved_regs;
1332 /* As do variadic functions. */
1333 if (current_function_pretend_args_size
1334 || cfun->machine->uses_anonymous_args
1335 /* Or if the function calls __builtin_eh_return () */
1336 || current_function_calls_eh_return
1337 /* Or if the function calls alloca */
1338 || current_function_calls_alloca
1339 /* Or if there is a stack adjustment. However, if the stack pointer
1340 is saved on the stack, we can use a pre-incrementing stack load. */
1341 || !(stack_adjust == 0 || (frame_pointer_needed && stack_adjust == 4)))
1344 saved_int_regs = arm_compute_save_reg_mask ();
1346 /* Unfortunately, the insn
1348 ldmib sp, {..., sp, ...}
1350 triggers a bug on most SA-110 based devices, such that the stack
1351 pointer won't be correctly restored if the instruction takes a
1352 page fault. We work around this problem by popping r3 along with
1353 the other registers, since that is never slower than executing
1354 another instruction.
1356 We test for !arm_arch5 here, because code for any architecture
1357 less than this could potentially be run on one of the buggy
1359 if (stack_adjust == 4 && !arm_arch5)
1361 /* Validate that r3 is a call-clobbered register (always true in
1362 the default abi) ... */
1363 if (!call_used_regs[3])
1366 /* ... that it isn't being used for a return value (always true
1367 until we implement return-in-regs), or for a tail-call
1371 if (GET_CODE (sibling) != CALL_INSN)
1374 if (find_regno_fusage (sibling, USE, 3))
1378 /* ... and that there are no call-saved registers in r0-r2
1379 (always true in the default ABI). */
1380 if (saved_int_regs & 0x7)
1384 /* Can't be done if interworking with Thumb, and any registers have been
1386 if (TARGET_INTERWORK && saved_int_regs != 0)
1389 /* On StrongARM, conditional returns are expensive if they aren't
1390 taken and multiple registers have been stacked. */
1391 if (iscond && arm_is_strong)
1393 /* Conditional return when just the LR is stored is a simple
1394 conditional-load instruction, that's not expensive. */
1395 if (saved_int_regs != 0 && saved_int_regs != (1 << LR_REGNUM))
1398 if (flag_pic && regs_ever_live[PIC_OFFSET_TABLE_REGNUM])
1402 /* If there are saved registers but the LR isn't saved, then we need
1403 two instructions for the return. */
1404 if (saved_int_regs && !(saved_int_regs & (1 << LR_REGNUM)))
1407 /* Can't be done if any of the FPA regs are pushed,
1408 since this also requires an insn. */
1409 if (TARGET_HARD_FLOAT && TARGET_FPA)
1410 for (regno = FIRST_FPA_REGNUM; regno <= LAST_FPA_REGNUM; regno++)
1411 if (regs_ever_live[regno] && !call_used_regs[regno])
1414 /* Likewise VFP regs. */
1415 if (TARGET_HARD_FLOAT && TARGET_VFP)
1416 for (regno = FIRST_VFP_REGNUM; regno <= LAST_VFP_REGNUM; regno++)
1417 if (regs_ever_live[regno] && !call_used_regs[regno])
1420 if (TARGET_REALLY_IWMMXT)
1421 for (regno = FIRST_IWMMXT_REGNUM; regno <= LAST_IWMMXT_REGNUM; regno++)
1422 if (regs_ever_live[regno] && ! call_used_regs [regno])
1428 /* Return TRUE if int I is a valid immediate ARM constant. */
1431 const_ok_for_arm (HOST_WIDE_INT i)
1433 unsigned HOST_WIDE_INT mask = ~(unsigned HOST_WIDE_INT)0xFF;
1435 /* For machines with >32 bit HOST_WIDE_INT, the bits above bit 31 must
1436 be all zero, or all one. */
1437 if ((i & ~(unsigned HOST_WIDE_INT) 0xffffffff) != 0
1438 && ((i & ~(unsigned HOST_WIDE_INT) 0xffffffff)
1439 != ((~(unsigned HOST_WIDE_INT) 0)
1440 & ~(unsigned HOST_WIDE_INT) 0xffffffff)))
1443 /* Fast return for 0 and powers of 2 */
1444 if ((i & (i - 1)) == 0)
1449 if ((i & mask & (unsigned HOST_WIDE_INT) 0xffffffff) == 0)
1452 (mask << 2) | ((mask & (unsigned HOST_WIDE_INT) 0xffffffff)
1453 >> (32 - 2)) | ~(unsigned HOST_WIDE_INT) 0xffffffff;
1455 while (mask != ~(unsigned HOST_WIDE_INT) 0xFF);
1460 /* Return true if I is a valid constant for the operation CODE. */
1462 const_ok_for_op (HOST_WIDE_INT i, enum rtx_code code)
1464 if (const_ok_for_arm (i))
1470 return const_ok_for_arm (ARM_SIGN_EXTEND (-i));
1472 case MINUS: /* Should only occur with (MINUS I reg) => rsb */
1478 return const_ok_for_arm (ARM_SIGN_EXTEND (~i));
1485 /* Emit a sequence of insns to handle a large constant.
1486 CODE is the code of the operation required, it can be any of SET, PLUS,
1487 IOR, AND, XOR, MINUS;
1488 MODE is the mode in which the operation is being performed;
1489 VAL is the integer to operate on;
1490 SOURCE is the other operand (a register, or a null-pointer for SET);
1491 SUBTARGETS means it is safe to create scratch registers if that will
1492 either produce a simpler sequence, or we will want to cse the values.
1493 Return value is the number of insns emitted. */
1496 arm_split_constant (enum rtx_code code, enum machine_mode mode, rtx insn,
1497 HOST_WIDE_INT val, rtx target, rtx source, int subtargets)
1501 if (insn && GET_CODE (PATTERN (insn)) == COND_EXEC)
1502 cond = COND_EXEC_TEST (PATTERN (insn));
1506 if (subtargets || code == SET
1507 || (GET_CODE (target) == REG && GET_CODE (source) == REG
1508 && REGNO (target) != REGNO (source)))
1510 /* After arm_reorg has been called, we can't fix up expensive
1511 constants by pushing them into memory so we must synthesize
1512 them in-line, regardless of the cost. This is only likely to
1513 be more costly on chips that have load delay slots and we are
1514 compiling without running the scheduler (so no splitting
1515 occurred before the final instruction emission).
1517 Ref: gcc -O1 -mcpu=strongarm gcc.c-torture/compile/980506-2.c
1519 if (!after_arm_reorg
1521 && (arm_gen_constant (code, mode, NULL_RTX, val, target, source,
1523 > arm_constant_limit + (code != SET)))
1527 /* Currently SET is the only monadic value for CODE, all
1528 the rest are diadic. */
1529 emit_insn (gen_rtx_SET (VOIDmode, target, GEN_INT (val)));
1534 rtx temp = subtargets ? gen_reg_rtx (mode) : target;
1536 emit_insn (gen_rtx_SET (VOIDmode, temp, GEN_INT (val)));
1537 /* For MINUS, the value is subtracted from, since we never
1538 have subtraction of a constant. */
1540 emit_insn (gen_rtx_SET (VOIDmode, target,
1541 gen_rtx_MINUS (mode, temp, source)));
1543 emit_insn (gen_rtx_SET (VOIDmode, target,
1544 gen_rtx_fmt_ee (code, mode, source, temp)));
1550 return arm_gen_constant (code, mode, cond, val, target, source, subtargets,
1555 count_insns_for_constant (HOST_WIDE_INT remainder, int i)
1557 HOST_WIDE_INT temp1;
1565 if (remainder & (3 << (i - 2)))
1570 temp1 = remainder & ((0x0ff << end)
1571 | ((i < end) ? (0xff >> (32 - end)) : 0));
1572 remainder &= ~temp1;
1577 } while (remainder);
1581 /* Emit an instruction with the indicated PATTERN. If COND is
1582 non-NULL, conditionalize the execution of the instruction on COND
1586 emit_constant_insn (rtx cond, rtx pattern)
1589 pattern = gen_rtx_COND_EXEC (VOIDmode, copy_rtx (cond), pattern);
1590 emit_insn (pattern);
1593 /* As above, but extra parameter GENERATE which, if clear, suppresses
1597 arm_gen_constant (enum rtx_code code, enum machine_mode mode, rtx cond,
1598 HOST_WIDE_INT val, rtx target, rtx source, int subtargets,
1603 int can_negate_initial = 0;
1606 int num_bits_set = 0;
1607 int set_sign_bit_copies = 0;
1608 int clear_sign_bit_copies = 0;
1609 int clear_zero_bit_copies = 0;
1610 int set_zero_bit_copies = 0;
1612 unsigned HOST_WIDE_INT temp1, temp2;
1613 unsigned HOST_WIDE_INT remainder = val & 0xffffffff;
1615 /* Find out which operations are safe for a given CODE. Also do a quick
1616 check for degenerate cases; these can occur when DImode operations
1628 can_negate_initial = 1;
1632 if (remainder == 0xffffffff)
1635 emit_constant_insn (cond,
1636 gen_rtx_SET (VOIDmode, target,
1637 GEN_INT (ARM_SIGN_EXTEND (val))));
1642 if (reload_completed && rtx_equal_p (target, source))
1645 emit_constant_insn (cond,
1646 gen_rtx_SET (VOIDmode, target, source));
1655 emit_constant_insn (cond,
1656 gen_rtx_SET (VOIDmode, target, const0_rtx));
1659 if (remainder == 0xffffffff)
1661 if (reload_completed && rtx_equal_p (target, source))
1664 emit_constant_insn (cond,
1665 gen_rtx_SET (VOIDmode, target, source));
1674 if (reload_completed && rtx_equal_p (target, source))
1677 emit_constant_insn (cond,
1678 gen_rtx_SET (VOIDmode, target, source));
1681 if (remainder == 0xffffffff)
1684 emit_constant_insn (cond,
1685 gen_rtx_SET (VOIDmode, target,
1686 gen_rtx_NOT (mode, source)));
1690 /* We don't know how to handle this yet below. */
1694 /* We treat MINUS as (val - source), since (source - val) is always
1695 passed as (source + (-val)). */
1699 emit_constant_insn (cond,
1700 gen_rtx_SET (VOIDmode, target,
1701 gen_rtx_NEG (mode, source)));
1704 if (const_ok_for_arm (val))
1707 emit_constant_insn (cond,
1708 gen_rtx_SET (VOIDmode, target,
1709 gen_rtx_MINUS (mode, GEN_INT (val),
1721 /* If we can do it in one insn get out quickly. */
1722 if (const_ok_for_arm (val)
1723 || (can_negate_initial && const_ok_for_arm (-val))
1724 || (can_invert && const_ok_for_arm (~val)))
1727 emit_constant_insn (cond,
1728 gen_rtx_SET (VOIDmode, target,
1730 ? gen_rtx_fmt_ee (code, mode, source,
1736 /* Calculate a few attributes that may be useful for specific
1738 for (i = 31; i >= 0; i--)
1740 if ((remainder & (1 << i)) == 0)
1741 clear_sign_bit_copies++;
1746 for (i = 31; i >= 0; i--)
1748 if ((remainder & (1 << i)) != 0)
1749 set_sign_bit_copies++;
1754 for (i = 0; i <= 31; i++)
1756 if ((remainder & (1 << i)) == 0)
1757 clear_zero_bit_copies++;
1762 for (i = 0; i <= 31; i++)
1764 if ((remainder & (1 << i)) != 0)
1765 set_zero_bit_copies++;
1773 /* See if we can do this by sign_extending a constant that is known
1774 to be negative. This is a good, way of doing it, since the shift
1775 may well merge into a subsequent insn. */
1776 if (set_sign_bit_copies > 1)
1778 if (const_ok_for_arm
1779 (temp1 = ARM_SIGN_EXTEND (remainder
1780 << (set_sign_bit_copies - 1))))
1784 rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
1785 emit_constant_insn (cond,
1786 gen_rtx_SET (VOIDmode, new_src,
1788 emit_constant_insn (cond,
1789 gen_ashrsi3 (target, new_src,
1790 GEN_INT (set_sign_bit_copies - 1)));
1794 /* For an inverted constant, we will need to set the low bits,
1795 these will be shifted out of harm's way. */
1796 temp1 |= (1 << (set_sign_bit_copies - 1)) - 1;
1797 if (const_ok_for_arm (~temp1))
1801 rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
1802 emit_constant_insn (cond,
1803 gen_rtx_SET (VOIDmode, new_src,
1805 emit_constant_insn (cond,
1806 gen_ashrsi3 (target, new_src,
1807 GEN_INT (set_sign_bit_copies - 1)));
1813 /* See if we can generate this by setting the bottom (or the top)
1814 16 bits, and then shifting these into the other half of the
1815 word. We only look for the simplest cases, to do more would cost
1816 too much. Be careful, however, not to generate this when the
1817 alternative would take fewer insns. */
1818 if (val & 0xffff0000)
1820 temp1 = remainder & 0xffff0000;
1821 temp2 = remainder & 0x0000ffff;
1823 /* Overlaps outside this range are best done using other methods. */
1824 for (i = 9; i < 24; i++)
1826 if ((((temp2 | (temp2 << i)) & 0xffffffff) == remainder)
1827 && !const_ok_for_arm (temp2))
1829 rtx new_src = (subtargets
1830 ? (generate ? gen_reg_rtx (mode) : NULL_RTX)
1832 insns = arm_gen_constant (code, mode, cond, temp2, new_src,
1833 source, subtargets, generate);
1841 gen_rtx_ASHIFT (mode, source,
1848 /* Don't duplicate cases already considered. */
1849 for (i = 17; i < 24; i++)
1851 if (((temp1 | (temp1 >> i)) == remainder)
1852 && !const_ok_for_arm (temp1))
1854 rtx new_src = (subtargets
1855 ? (generate ? gen_reg_rtx (mode) : NULL_RTX)
1857 insns = arm_gen_constant (code, mode, cond, temp1, new_src,
1858 source, subtargets, generate);
1863 gen_rtx_SET (VOIDmode, target,
1866 gen_rtx_LSHIFTRT (mode, source,
1877 /* If we have IOR or XOR, and the constant can be loaded in a
1878 single instruction, and we can find a temporary to put it in,
1879 then this can be done in two instructions instead of 3-4. */
1881 /* TARGET can't be NULL if SUBTARGETS is 0 */
1882 || (reload_completed && !reg_mentioned_p (target, source)))
1884 if (const_ok_for_arm (ARM_SIGN_EXTEND (~val)))
1888 rtx sub = subtargets ? gen_reg_rtx (mode) : target;
1890 emit_constant_insn (cond,
1891 gen_rtx_SET (VOIDmode, sub,
1893 emit_constant_insn (cond,
1894 gen_rtx_SET (VOIDmode, target,
1895 gen_rtx_fmt_ee (code, mode,
1905 if (set_sign_bit_copies > 8
1906 && (val & (-1 << (32 - set_sign_bit_copies))) == val)
1910 rtx sub = subtargets ? gen_reg_rtx (mode) : target;
1911 rtx shift = GEN_INT (set_sign_bit_copies);
1915 gen_rtx_SET (VOIDmode, sub,
1917 gen_rtx_ASHIFT (mode,
1922 gen_rtx_SET (VOIDmode, target,
1924 gen_rtx_LSHIFTRT (mode, sub,
1930 if (set_zero_bit_copies > 8
1931 && (remainder & ((1 << set_zero_bit_copies) - 1)) == remainder)
1935 rtx sub = subtargets ? gen_reg_rtx (mode) : target;
1936 rtx shift = GEN_INT (set_zero_bit_copies);
1940 gen_rtx_SET (VOIDmode, sub,
1942 gen_rtx_LSHIFTRT (mode,
1947 gen_rtx_SET (VOIDmode, target,
1949 gen_rtx_ASHIFT (mode, sub,
1955 if (const_ok_for_arm (temp1 = ARM_SIGN_EXTEND (~val)))
1959 rtx sub = subtargets ? gen_reg_rtx (mode) : target;
1960 emit_constant_insn (cond,
1961 gen_rtx_SET (VOIDmode, sub,
1962 gen_rtx_NOT (mode, source)));
1965 sub = gen_reg_rtx (mode);
1966 emit_constant_insn (cond,
1967 gen_rtx_SET (VOIDmode, sub,
1968 gen_rtx_AND (mode, source,
1970 emit_constant_insn (cond,
1971 gen_rtx_SET (VOIDmode, target,
1972 gen_rtx_NOT (mode, sub)));
1979 /* See if two shifts will do 2 or more insn's worth of work. */
1980 if (clear_sign_bit_copies >= 16 && clear_sign_bit_copies < 24)
1982 HOST_WIDE_INT shift_mask = ((0xffffffff
1983 << (32 - clear_sign_bit_copies))
1986 if ((remainder | shift_mask) != 0xffffffff)
1990 rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
1991 insns = arm_gen_constant (AND, mode, cond,
1992 remainder | shift_mask,
1993 new_src, source, subtargets, 1);
1998 rtx targ = subtargets ? NULL_RTX : target;
1999 insns = arm_gen_constant (AND, mode, cond,
2000 remainder | shift_mask,
2001 targ, source, subtargets, 0);
2007 rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
2008 rtx shift = GEN_INT (clear_sign_bit_copies);
2010 emit_insn (gen_ashlsi3 (new_src, source, shift));
2011 emit_insn (gen_lshrsi3 (target, new_src, shift));
2017 if (clear_zero_bit_copies >= 16 && clear_zero_bit_copies < 24)
2019 HOST_WIDE_INT shift_mask = (1 << clear_zero_bit_copies) - 1;
2021 if ((remainder | shift_mask) != 0xffffffff)
2025 rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
2027 insns = arm_gen_constant (AND, mode, cond,
2028 remainder | shift_mask,
2029 new_src, source, subtargets, 1);
2034 rtx targ = subtargets ? NULL_RTX : target;
2036 insns = arm_gen_constant (AND, mode, cond,
2037 remainder | shift_mask,
2038 targ, source, subtargets, 0);
2044 rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
2045 rtx shift = GEN_INT (clear_zero_bit_copies);
2047 emit_insn (gen_lshrsi3 (new_src, source, shift));
2048 emit_insn (gen_ashlsi3 (target, new_src, shift));
2060 for (i = 0; i < 32; i++)
2061 if (remainder & (1 << i))
2064 if (code == AND || (can_invert && num_bits_set > 16))
2065 remainder = (~remainder) & 0xffffffff;
2066 else if (code == PLUS && num_bits_set > 16)
2067 remainder = (-remainder) & 0xffffffff;
2074 /* Now try and find a way of doing the job in either two or three
2076 We start by looking for the largest block of zeros that are aligned on
2077 a 2-bit boundary, we then fill up the temps, wrapping around to the
2078 top of the word when we drop off the bottom.
2079 In the worst case this code should produce no more than four insns. */
2082 int best_consecutive_zeros = 0;
2084 for (i = 0; i < 32; i += 2)
2086 int consecutive_zeros = 0;
2088 if (!(remainder & (3 << i)))
2090 while ((i < 32) && !(remainder & (3 << i)))
2092 consecutive_zeros += 2;
2095 if (consecutive_zeros > best_consecutive_zeros)
2097 best_consecutive_zeros = consecutive_zeros;
2098 best_start = i - consecutive_zeros;
2104 /* So long as it won't require any more insns to do so, it's
2105 desirable to emit a small constant (in bits 0...9) in the last
2106 insn. This way there is more chance that it can be combined with
2107 a later addressing insn to form a pre-indexed load or store
2108 operation. Consider:
2110 *((volatile int *)0xe0000100) = 1;
2111 *((volatile int *)0xe0000110) = 2;
2113 We want this to wind up as:
2117 str rB, [rA, #0x100]
2119 str rB, [rA, #0x110]
2121 rather than having to synthesize both large constants from scratch.
2123 Therefore, we calculate how many insns would be required to emit
2124 the constant starting from `best_start', and also starting from
2125 zero (i.e. with bit 31 first to be output). If `best_start' doesn't
2126 yield a shorter sequence, we may as well use zero. */
2128 && ((((unsigned HOST_WIDE_INT) 1) << best_start) < remainder)
2129 && (count_insns_for_constant (remainder, 0) <=
2130 count_insns_for_constant (remainder, best_start)))
2133 /* Now start emitting the insns. */
2141 if (remainder & (3 << (i - 2)))
2146 temp1 = remainder & ((0x0ff << end)
2147 | ((i < end) ? (0xff >> (32 - end)) : 0));
2148 remainder &= ~temp1;
2152 rtx new_src, temp1_rtx;
2154 if (code == SET || code == MINUS)
2156 new_src = (subtargets ? gen_reg_rtx (mode) : target);
2157 if (can_invert && code != MINUS)
2162 if (remainder && subtargets)
2163 new_src = gen_reg_rtx (mode);
2168 else if (can_negate)
2172 temp1 = trunc_int_for_mode (temp1, mode);
2173 temp1_rtx = GEN_INT (temp1);
2177 else if (code == MINUS)
2178 temp1_rtx = gen_rtx_MINUS (mode, temp1_rtx, source);
2180 temp1_rtx = gen_rtx_fmt_ee (code, mode, source, temp1_rtx);
2182 emit_constant_insn (cond,
2183 gen_rtx_SET (VOIDmode, new_src,
2193 else if (code == MINUS)
2207 /* Canonicalize a comparison so that we are more likely to recognize it.
2208 This can be done for a few constant compares, where we can make the
2209 immediate value easier to load. */
2212 arm_canonicalize_comparison (enum rtx_code code, rtx * op1)
2214 unsigned HOST_WIDE_INT i = INTVAL (*op1);
2224 if (i != ((((unsigned HOST_WIDE_INT) 1) << (HOST_BITS_PER_WIDE_INT - 1)) - 1)
2225 && (const_ok_for_arm (i + 1) || const_ok_for_arm (-(i + 1))))
2227 *op1 = GEN_INT (i + 1);
2228 return code == GT ? GE : LT;
2234 if (i != (((unsigned HOST_WIDE_INT) 1) << (HOST_BITS_PER_WIDE_INT - 1))
2235 && (const_ok_for_arm (i - 1) || const_ok_for_arm (-(i - 1))))
2237 *op1 = GEN_INT (i - 1);
2238 return code == GE ? GT : LE;
2244 if (i != ~((unsigned HOST_WIDE_INT) 0)
2245 && (const_ok_for_arm (i + 1) || const_ok_for_arm (-(i + 1))))
2247 *op1 = GEN_INT (i + 1);
2248 return code == GTU ? GEU : LTU;
2255 && (const_ok_for_arm (i - 1) || const_ok_for_arm (-(i - 1))))
2257 *op1 = GEN_INT (i - 1);
2258 return code == GEU ? GTU : LEU;
2270 /* Define how to find the value returned by a function. */
2272 rtx arm_function_value(tree type, tree func ATTRIBUTE_UNUSED)
2274 enum machine_mode mode;
2275 int unsignedp ATTRIBUTE_UNUSED;
2276 rtx r ATTRIBUTE_UNUSED;
2279 mode = TYPE_MODE (type);
2280 /* Promote integer types. */
2281 if (INTEGRAL_TYPE_P (type))
2282 PROMOTE_FUNCTION_MODE (mode, unsignedp, type);
2283 return LIBCALL_VALUE(mode);
2287 /* Decide whether a type should be returned in memory (true)
2288 or in a register (false). This is called by the macro
2289 RETURN_IN_MEMORY. */
2291 arm_return_in_memory (tree type)
2295 if (!AGGREGATE_TYPE_P (type))
2296 /* All simple types are returned in registers. */
2299 size = int_size_in_bytes (type);
2301 if (arm_abi != ARM_ABI_APCS)
2303 /* ATPCS and later return aggregate types in memory only if they are
2304 larger than a word (or are variable size). */
2305 return (size < 0 || size > UNITS_PER_WORD);
2308 /* For the arm-wince targets we choose to be compatible with Microsoft's
2309 ARM and Thumb compilers, which always return aggregates in memory. */
2311 /* All structures/unions bigger than one word are returned in memory.
2312 Also catch the case where int_size_in_bytes returns -1. In this case
2313 the aggregate is either huge or of variable size, and in either case
2314 we will want to return it via memory and not in a register. */
2315 if (size < 0 || size > UNITS_PER_WORD)
2318 if (TREE_CODE (type) == RECORD_TYPE)
2322 /* For a struct the APCS says that we only return in a register
2323 if the type is 'integer like' and every addressable element
2324 has an offset of zero. For practical purposes this means
2325 that the structure can have at most one non bit-field element
2326 and that this element must be the first one in the structure. */
2328 /* Find the first field, ignoring non FIELD_DECL things which will
2329 have been created by C++. */
2330 for (field = TYPE_FIELDS (type);
2331 field && TREE_CODE (field) != FIELD_DECL;
2332 field = TREE_CHAIN (field))
2336 return 0; /* An empty structure. Allowed by an extension to ANSI C. */
2338 /* Check that the first field is valid for returning in a register. */
2340 /* ... Floats are not allowed */
2341 if (FLOAT_TYPE_P (TREE_TYPE (field)))
2344 /* ... Aggregates that are not themselves valid for returning in
2345 a register are not allowed. */
2346 if (RETURN_IN_MEMORY (TREE_TYPE (field)))
2349 /* Now check the remaining fields, if any. Only bitfields are allowed,
2350 since they are not addressable. */
2351 for (field = TREE_CHAIN (field);
2353 field = TREE_CHAIN (field))
2355 if (TREE_CODE (field) != FIELD_DECL)
2358 if (!DECL_BIT_FIELD_TYPE (field))
2365 if (TREE_CODE (type) == UNION_TYPE)
2369 /* Unions can be returned in registers if every element is
2370 integral, or can be returned in an integer register. */
2371 for (field = TYPE_FIELDS (type);
2373 field = TREE_CHAIN (field))
2375 if (TREE_CODE (field) != FIELD_DECL)
2378 if (FLOAT_TYPE_P (TREE_TYPE (field)))
2381 if (RETURN_IN_MEMORY (TREE_TYPE (field)))
2387 #endif /* not ARM_WINCE */
2389 /* Return all other types in memory. */
2393 /* Indicate whether or not words of a double are in big-endian order. */
2396 arm_float_words_big_endian (void)
2398 if (TARGET_MAVERICK)
2401 /* For FPA, float words are always big-endian. For VFP, floats words
2402 follow the memory system mode. */
2410 return (TARGET_BIG_END ? 1 : 0);
2415 /* Initialize a variable CUM of type CUMULATIVE_ARGS
2416 for a call to a function whose data type is FNTYPE.
2417 For a library call, FNTYPE is NULL. */
2419 arm_init_cumulative_args (CUMULATIVE_ARGS *pcum, tree fntype,
2420 rtx libname ATTRIBUTE_UNUSED,
2421 tree fndecl ATTRIBUTE_UNUSED)
2423 /* On the ARM, the offset starts at 0. */
2424 pcum->nregs = ((fntype && aggregate_value_p (TREE_TYPE (fntype), fntype)) ? 1 : 0);
2425 pcum->iwmmxt_nregs = 0;
2426 pcum->can_split = true;
2428 pcum->call_cookie = CALL_NORMAL;
2430 if (TARGET_LONG_CALLS)
2431 pcum->call_cookie = CALL_LONG;
2433 /* Check for long call/short call attributes. The attributes
2434 override any command line option. */
2437 if (lookup_attribute ("short_call", TYPE_ATTRIBUTES (fntype)))
2438 pcum->call_cookie = CALL_SHORT;
2439 else if (lookup_attribute ("long_call", TYPE_ATTRIBUTES (fntype)))
2440 pcum->call_cookie = CALL_LONG;
2443 /* Varargs vectors are treated the same as long long.
2444 named_count avoids having to change the way arm handles 'named' */
2445 pcum->named_count = 0;
2448 if (TARGET_REALLY_IWMMXT && fntype)
2452 for (fn_arg = TYPE_ARG_TYPES (fntype);
2454 fn_arg = TREE_CHAIN (fn_arg))
2455 pcum->named_count += 1;
2457 if (! pcum->named_count)
2458 pcum->named_count = INT_MAX;
2463 /* Return true if mode/type need doubleword alignment. */
2465 arm_needs_doubleword_align (enum machine_mode mode, tree type)
2467 return (GET_MODE_ALIGNMENT (mode) > PARM_BOUNDARY
2468 || (type && TYPE_ALIGN (type) > PARM_BOUNDARY));
2472 /* Determine where to put an argument to a function.
2473 Value is zero to push the argument on the stack,
2474 or a hard register in which to store the argument.
2476 MODE is the argument's machine mode.
2477 TYPE is the data type of the argument (as a tree).
2478 This is null for libcalls where that information may
2480 CUM is a variable of type CUMULATIVE_ARGS which gives info about
2481 the preceding args and about the function being called.
2482 NAMED is nonzero if this argument is a named parameter
2483 (otherwise it is an extra parameter matching an ellipsis). */
2486 arm_function_arg (CUMULATIVE_ARGS *pcum, enum machine_mode mode,
2487 tree type, int named)
2491 /* Varargs vectors are treated the same as long long.
2492 named_count avoids having to change the way arm handles 'named' */
2493 if (TARGET_IWMMXT_ABI
2494 && arm_vector_mode_supported_p (mode)
2495 && pcum->named_count > pcum->nargs + 1)
2497 if (pcum->iwmmxt_nregs <= 9)
2498 return gen_rtx_REG (mode, pcum->iwmmxt_nregs + FIRST_IWMMXT_REGNUM);
2501 pcum->can_split = false;
2506 /* Put doubleword aligned quantities in even register pairs. */
2508 && ARM_DOUBLEWORD_ALIGN
2509 && arm_needs_doubleword_align (mode, type))
2512 if (mode == VOIDmode)
2513 /* Compute operand 2 of the call insn. */
2514 return GEN_INT (pcum->call_cookie);
2516 /* Only allow splitting an arg between regs and memory if all preceding
2517 args were allocated to regs. For args passed by reference we only count
2518 the reference pointer. */
2519 if (pcum->can_split)
2522 nregs = ARM_NUM_REGS2 (mode, type);
2524 if (!named || pcum->nregs + nregs > NUM_ARG_REGS)
2527 return gen_rtx_REG (mode, pcum->nregs);
2530 /* Variable sized types are passed by reference. This is a GCC
2531 extension to the ARM ABI. */
2534 arm_pass_by_reference (CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED,
2535 enum machine_mode mode ATTRIBUTE_UNUSED,
2536 tree type, bool named ATTRIBUTE_UNUSED)
2538 return type && TREE_CODE (TYPE_SIZE (type)) != INTEGER_CST;
2541 /* Encode the current state of the #pragma [no_]long_calls. */
2544 OFF, /* No #pramgma [no_]long_calls is in effect. */
2545 LONG, /* #pragma long_calls is in effect. */
2546 SHORT /* #pragma no_long_calls is in effect. */
2549 static arm_pragma_enum arm_pragma_long_calls = OFF;
2552 arm_pr_long_calls (struct cpp_reader * pfile ATTRIBUTE_UNUSED)
2554 arm_pragma_long_calls = LONG;
2558 arm_pr_no_long_calls (struct cpp_reader * pfile ATTRIBUTE_UNUSED)
2560 arm_pragma_long_calls = SHORT;
2564 arm_pr_long_calls_off (struct cpp_reader * pfile ATTRIBUTE_UNUSED)
2566 arm_pragma_long_calls = OFF;
2569 /* Table of machine attributes. */
2570 const struct attribute_spec arm_attribute_table[] =
2572 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
2573 /* Function calls made to this symbol must be done indirectly, because
2574 it may lie outside of the 26 bit addressing range of a normal function
2576 { "long_call", 0, 0, false, true, true, NULL },
2577 /* Whereas these functions are always known to reside within the 26 bit
2578 addressing range. */
2579 { "short_call", 0, 0, false, true, true, NULL },
2580 /* Interrupt Service Routines have special prologue and epilogue requirements. */
2581 { "isr", 0, 1, false, false, false, arm_handle_isr_attribute },
2582 { "interrupt", 0, 1, false, false, false, arm_handle_isr_attribute },
2583 { "naked", 0, 0, true, false, false, arm_handle_fndecl_attribute },
2585 /* ARM/PE has three new attributes:
2587 dllexport - for exporting a function/variable that will live in a dll
2588 dllimport - for importing a function/variable from a dll
2590 Microsoft allows multiple declspecs in one __declspec, separating
2591 them with spaces. We do NOT support this. Instead, use __declspec
2594 { "dllimport", 0, 0, true, false, false, NULL },
2595 { "dllexport", 0, 0, true, false, false, NULL },
2596 { "interfacearm", 0, 0, true, false, false, arm_handle_fndecl_attribute },
2597 #elif TARGET_DLLIMPORT_DECL_ATTRIBUTES
2598 { "dllimport", 0, 0, false, false, false, handle_dll_attribute },
2599 { "dllexport", 0, 0, false, false, false, handle_dll_attribute },
2600 { "notshared", 0, 0, false, true, false, arm_handle_notshared_attribute },
2602 { NULL, 0, 0, false, false, false, NULL }
2605 /* Handle an attribute requiring a FUNCTION_DECL;
2606 arguments as in struct attribute_spec.handler. */
2608 arm_handle_fndecl_attribute (tree *node, tree name, tree args ATTRIBUTE_UNUSED,
2609 int flags ATTRIBUTE_UNUSED, bool *no_add_attrs)
2611 if (TREE_CODE (*node) != FUNCTION_DECL)
2613 warning ("%qs attribute only applies to functions",
2614 IDENTIFIER_POINTER (name));
2615 *no_add_attrs = true;
2621 /* Handle an "interrupt" or "isr" attribute;
2622 arguments as in struct attribute_spec.handler. */
2624 arm_handle_isr_attribute (tree *node, tree name, tree args, int flags,
2629 if (TREE_CODE (*node) != FUNCTION_DECL)
2631 warning ("%qs attribute only applies to functions",
2632 IDENTIFIER_POINTER (name));
2633 *no_add_attrs = true;
2635 /* FIXME: the argument if any is checked for type attributes;
2636 should it be checked for decl ones? */
2640 if (TREE_CODE (*node) == FUNCTION_TYPE
2641 || TREE_CODE (*node) == METHOD_TYPE)
2643 if (arm_isr_value (args) == ARM_FT_UNKNOWN)
2645 warning ("%qs attribute ignored", IDENTIFIER_POINTER (name));
2646 *no_add_attrs = true;
2649 else if (TREE_CODE (*node) == POINTER_TYPE
2650 && (TREE_CODE (TREE_TYPE (*node)) == FUNCTION_TYPE
2651 || TREE_CODE (TREE_TYPE (*node)) == METHOD_TYPE)
2652 && arm_isr_value (args) != ARM_FT_UNKNOWN)
2654 *node = build_variant_type_copy (*node);
2655 TREE_TYPE (*node) = build_type_attribute_variant
2657 tree_cons (name, args, TYPE_ATTRIBUTES (TREE_TYPE (*node))));
2658 *no_add_attrs = true;
2662 /* Possibly pass this attribute on from the type to a decl. */
2663 if (flags & ((int) ATTR_FLAG_DECL_NEXT
2664 | (int) ATTR_FLAG_FUNCTION_NEXT
2665 | (int) ATTR_FLAG_ARRAY_NEXT))
2667 *no_add_attrs = true;
2668 return tree_cons (name, args, NULL_TREE);
2672 warning ("%qs attribute ignored", IDENTIFIER_POINTER (name));
2680 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
2681 /* Handle the "notshared" attribute. This attribute is another way of
2682 requesting hidden visibility. ARM's compiler supports
2683 "__declspec(notshared)"; we support the same thing via an
2687 arm_handle_notshared_attribute (tree *node,
2688 tree name ATTRIBUTE_UNUSED,
2689 tree args ATTRIBUTE_UNUSED,
2690 int flags ATTRIBUTE_UNUSED,
2693 tree decl = TYPE_NAME (*node);
2697 DECL_VISIBILITY (decl) = VISIBILITY_HIDDEN;
2698 DECL_VISIBILITY_SPECIFIED (decl) = 1;
2699 *no_add_attrs = false;
2705 /* Return 0 if the attributes for two types are incompatible, 1 if they
2706 are compatible, and 2 if they are nearly compatible (which causes a
2707 warning to be generated). */
2709 arm_comp_type_attributes (tree type1, tree type2)
2713 /* Check for mismatch of non-default calling convention. */
2714 if (TREE_CODE (type1) != FUNCTION_TYPE)
2717 /* Check for mismatched call attributes. */
2718 l1 = lookup_attribute ("long_call", TYPE_ATTRIBUTES (type1)) != NULL;
2719 l2 = lookup_attribute ("long_call", TYPE_ATTRIBUTES (type2)) != NULL;
2720 s1 = lookup_attribute ("short_call", TYPE_ATTRIBUTES (type1)) != NULL;
2721 s2 = lookup_attribute ("short_call", TYPE_ATTRIBUTES (type2)) != NULL;
2723 /* Only bother to check if an attribute is defined. */
2724 if (l1 | l2 | s1 | s2)
2726 /* If one type has an attribute, the other must have the same attribute. */
2727 if ((l1 != l2) || (s1 != s2))
2730 /* Disallow mixed attributes. */
2731 if ((l1 & s2) || (l2 & s1))
2735 /* Check for mismatched ISR attribute. */
2736 l1 = lookup_attribute ("isr", TYPE_ATTRIBUTES (type1)) != NULL;
2738 l1 = lookup_attribute ("interrupt", TYPE_ATTRIBUTES (type1)) != NULL;
2739 l2 = lookup_attribute ("isr", TYPE_ATTRIBUTES (type2)) != NULL;
2741 l1 = lookup_attribute ("interrupt", TYPE_ATTRIBUTES (type2)) != NULL;
2748 /* Encode long_call or short_call attribute by prefixing
2749 symbol name in DECL with a special character FLAG. */
2751 arm_encode_call_attribute (tree decl, int flag)
2753 const char * str = XSTR (XEXP (DECL_RTL (decl), 0), 0);
2754 int len = strlen (str);
2757 /* Do not allow weak functions to be treated as short call. */
2758 if (DECL_WEAK (decl) && flag == SHORT_CALL_FLAG_CHAR)
2761 newstr = alloca (len + 2);
2763 strcpy (newstr + 1, str);
2765 newstr = (char *) ggc_alloc_string (newstr, len + 1);
2766 XSTR (XEXP (DECL_RTL (decl), 0), 0) = newstr;
2769 /* Assigns default attributes to newly defined type. This is used to
2770 set short_call/long_call attributes for function types of
2771 functions defined inside corresponding #pragma scopes. */
2773 arm_set_default_type_attributes (tree type)
2775 /* Add __attribute__ ((long_call)) to all functions, when
2776 inside #pragma long_calls or __attribute__ ((short_call)),
2777 when inside #pragma no_long_calls. */
2778 if (TREE_CODE (type) == FUNCTION_TYPE || TREE_CODE (type) == METHOD_TYPE)
2780 tree type_attr_list, attr_name;
2781 type_attr_list = TYPE_ATTRIBUTES (type);
2783 if (arm_pragma_long_calls == LONG)
2784 attr_name = get_identifier ("long_call");
2785 else if (arm_pragma_long_calls == SHORT)
2786 attr_name = get_identifier ("short_call");
2790 type_attr_list = tree_cons (attr_name, NULL_TREE, type_attr_list);
2791 TYPE_ATTRIBUTES (type) = type_attr_list;
2795 /* Return 1 if the operand is a SYMBOL_REF for a function known to be
2796 defined within the current compilation unit. If this cannot be
2797 determined, then 0 is returned. */
2799 current_file_function_operand (rtx sym_ref)
2801 /* This is a bit of a fib. A function will have a short call flag
2802 applied to its name if it has the short call attribute, or it has
2803 already been defined within the current compilation unit. */
2804 if (ENCODED_SHORT_CALL_ATTR_P (XSTR (sym_ref, 0)))
2807 /* The current function is always defined within the current compilation
2808 unit. If it s a weak definition however, then this may not be the real
2809 definition of the function, and so we have to say no. */
2810 if (sym_ref == XEXP (DECL_RTL (current_function_decl), 0)
2811 && !DECL_WEAK (current_function_decl))
2814 /* We cannot make the determination - default to returning 0. */
2818 /* Return nonzero if a 32 bit "long_call" should be generated for
2819 this call. We generate a long_call if the function:
2821 a. has an __attribute__((long call))
2822 or b. is within the scope of a #pragma long_calls
2823 or c. the -mlong-calls command line switch has been specified
2825 1. -ffunction-sections is in effect
2826 or 2. the current function has __attribute__ ((section))
2827 or 3. the target function has __attribute__ ((section))
2829 However we do not generate a long call if the function:
2831 d. has an __attribute__ ((short_call))
2832 or e. is inside the scope of a #pragma no_long_calls
2833 or f. is defined within the current compilation unit.
2835 This function will be called by C fragments contained in the machine
2836 description file. SYM_REF and CALL_COOKIE correspond to the matched
2837 rtl operands. CALL_SYMBOL is used to distinguish between
2838 two different callers of the function. It is set to 1 in the
2839 "call_symbol" and "call_symbol_value" patterns and to 0 in the "call"
2840 and "call_value" patterns. This is because of the difference in the
2841 SYM_REFs passed by these patterns. */
2843 arm_is_longcall_p (rtx sym_ref, int call_cookie, int call_symbol)
2847 if (GET_CODE (sym_ref) != MEM)
2850 sym_ref = XEXP (sym_ref, 0);
2853 if (GET_CODE (sym_ref) != SYMBOL_REF)
2856 if (call_cookie & CALL_SHORT)
2859 if (TARGET_LONG_CALLS)
2861 if (flag_function_sections
2862 || DECL_SECTION_NAME (current_function_decl))
2863 /* c.3 is handled by the definition of the
2864 ARM_DECLARE_FUNCTION_SIZE macro. */
2868 if (current_file_function_operand (sym_ref))
2871 return (call_cookie & CALL_LONG)
2872 || ENCODED_LONG_CALL_ATTR_P (XSTR (sym_ref, 0))
2873 || TARGET_LONG_CALLS;
2876 /* Return nonzero if it is ok to make a tail-call to DECL. */
2878 arm_function_ok_for_sibcall (tree decl, tree exp ATTRIBUTE_UNUSED)
2880 int call_type = TARGET_LONG_CALLS ? CALL_LONG : CALL_NORMAL;
2882 if (cfun->machine->sibcall_blocked)
2885 /* Never tailcall something for which we have no decl, or if we
2886 are in Thumb mode. */
2887 if (decl == NULL || TARGET_THUMB)
2890 /* Get the calling method. */
2891 if (lookup_attribute ("short_call", TYPE_ATTRIBUTES (TREE_TYPE (decl))))
2892 call_type = CALL_SHORT;
2893 else if (lookup_attribute ("long_call", TYPE_ATTRIBUTES (TREE_TYPE (decl))))
2894 call_type = CALL_LONG;
2896 /* Cannot tail-call to long calls, since these are out of range of
2897 a branch instruction. However, if not compiling PIC, we know
2898 we can reach the symbol if it is in this compilation unit. */
2899 if (call_type == CALL_LONG && (flag_pic || !TREE_ASM_WRITTEN (decl)))
2902 /* If we are interworking and the function is not declared static
2903 then we can't tail-call it unless we know that it exists in this
2904 compilation unit (since it might be a Thumb routine). */
2905 if (TARGET_INTERWORK && TREE_PUBLIC (decl) && !TREE_ASM_WRITTEN (decl))
2908 /* Never tailcall from an ISR routine - it needs a special exit sequence. */
2909 if (IS_INTERRUPT (arm_current_func_type ()))
2912 /* Everything else is ok. */
2917 /* Addressing mode support functions. */
2919 /* Return nonzero if X is a legitimate immediate operand when compiling
2922 legitimate_pic_operand_p (rtx x)
2926 && (GET_CODE (x) == SYMBOL_REF
2927 || (GET_CODE (x) == CONST
2928 && GET_CODE (XEXP (x, 0)) == PLUS
2929 && GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF)))
2936 legitimize_pic_address (rtx orig, enum machine_mode mode, rtx reg)
2938 if (GET_CODE (orig) == SYMBOL_REF
2939 || GET_CODE (orig) == LABEL_REF)
2941 #ifndef AOF_ASSEMBLER
2942 rtx pic_ref, address;
2952 reg = gen_reg_rtx (Pmode);
2957 #ifdef AOF_ASSEMBLER
2958 /* The AOF assembler can generate relocations for these directly, and
2959 understands that the PIC register has to be added into the offset. */
2960 insn = emit_insn (gen_pic_load_addr_based (reg, orig));
2963 address = gen_reg_rtx (Pmode);
2968 emit_insn (gen_pic_load_addr_arm (address, orig));
2970 emit_insn (gen_pic_load_addr_thumb (address, orig));
2972 if ((GET_CODE (orig) == LABEL_REF
2973 || (GET_CODE (orig) == SYMBOL_REF &&
2974 SYMBOL_REF_LOCAL_P (orig)))
2976 pic_ref = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, address);
2979 pic_ref = gen_const_mem (Pmode,
2980 gen_rtx_PLUS (Pmode, pic_offset_table_rtx,
2984 insn = emit_move_insn (reg, pic_ref);
2986 current_function_uses_pic_offset_table = 1;
2987 /* Put a REG_EQUAL note on this insn, so that it can be optimized
2989 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_EQUAL, orig,
2993 else if (GET_CODE (orig) == CONST)
2997 if (GET_CODE (XEXP (orig, 0)) == PLUS
2998 && XEXP (XEXP (orig, 0), 0) == pic_offset_table_rtx)
3006 reg = gen_reg_rtx (Pmode);
3009 if (GET_CODE (XEXP (orig, 0)) == PLUS)
3011 base = legitimize_pic_address (XEXP (XEXP (orig, 0), 0), Pmode, reg);
3012 offset = legitimize_pic_address (XEXP (XEXP (orig, 0), 1), Pmode,
3013 base == reg ? 0 : reg);
3018 if (GET_CODE (offset) == CONST_INT)
3020 /* The base register doesn't really matter, we only want to
3021 test the index for the appropriate mode. */
3022 if (!arm_legitimate_index_p (mode, offset, SET, 0))
3024 if (!no_new_pseudos)
3025 offset = force_reg (Pmode, offset);
3030 if (GET_CODE (offset) == CONST_INT)
3031 return plus_constant (base, INTVAL (offset));
3034 if (GET_MODE_SIZE (mode) > 4
3035 && (GET_MODE_CLASS (mode) == MODE_INT
3036 || TARGET_SOFT_FLOAT))
3038 emit_insn (gen_addsi3 (reg, base, offset));
3042 return gen_rtx_PLUS (Pmode, base, offset);
3049 /* Find a spare low register. */
3052 thumb_find_work_register (int live_regs_mask)
3056 /* Use a spare arg register. */
3057 if (!regs_ever_live[LAST_ARG_REGNUM])
3058 return LAST_ARG_REGNUM;
3060 /* Look for a pushed register. This is used before the frame pointer is
3061 setup, so r7 is a candidate. */
3062 for (reg = LAST_LO_REGNUM; reg >=0; reg--)
3063 if (live_regs_mask & (1 << reg))
3066 /* Something went wrong. */
3071 /* Generate code to load the PIC register. In thumb mode SCRATCH is a
3075 arm_load_pic_register (unsigned int scratch)
3077 #ifndef AOF_ASSEMBLER
3078 rtx l1, pic_tmp, pic_tmp2, pic_rtx;
3079 rtx global_offset_table;
3081 if (current_function_uses_pic_offset_table == 0 || TARGET_SINGLE_PIC_BASE)
3087 l1 = gen_label_rtx ();
3089 global_offset_table = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
3090 /* On the ARM the PC register contains 'dot + 8' at the time of the
3091 addition, on the Thumb it is 'dot + 4'. */
3092 pic_tmp = plus_constant (gen_rtx_LABEL_REF (Pmode, l1), TARGET_ARM ? 8 : 4);
3094 pic_tmp2 = gen_rtx_CONST (VOIDmode,
3095 gen_rtx_PLUS (Pmode, global_offset_table, pc_rtx));
3097 pic_tmp2 = gen_rtx_CONST (VOIDmode, global_offset_table);
3099 pic_rtx = gen_rtx_CONST (Pmode, gen_rtx_MINUS (Pmode, pic_tmp2, pic_tmp));
3103 emit_insn (gen_pic_load_addr_arm (pic_offset_table_rtx, pic_rtx));
3104 emit_insn (gen_pic_add_dot_plus_eight (pic_offset_table_rtx, l1));
3108 if (REGNO (pic_offset_table_rtx) > LAST_LO_REGNUM)
3110 /* We will have pushed the pic register, so should always be
3111 able to find a work register. */
3112 pic_tmp = gen_rtx_REG (SImode, scratch);
3113 emit_insn (gen_pic_load_addr_thumb (pic_tmp, pic_rtx));
3114 emit_insn (gen_movsi (pic_offset_table_rtx, pic_tmp));
3117 emit_insn (gen_pic_load_addr_thumb (pic_offset_table_rtx, pic_rtx));
3118 emit_insn (gen_pic_add_dot_plus_four (pic_offset_table_rtx, l1));
3121 /* Need to emit this whether or not we obey regdecls,
3122 since setjmp/longjmp can cause life info to screw up. */
3123 emit_insn (gen_rtx_USE (VOIDmode, pic_offset_table_rtx));
3124 #endif /* AOF_ASSEMBLER */
3128 /* Return nonzero if X is valid as an ARM state addressing register. */
3130 arm_address_register_rtx_p (rtx x, int strict_p)
3134 if (GET_CODE (x) != REG)
3140 return ARM_REGNO_OK_FOR_BASE_P (regno);
3142 return (regno <= LAST_ARM_REGNUM
3143 || regno >= FIRST_PSEUDO_REGISTER
3144 || regno == FRAME_POINTER_REGNUM
3145 || regno == ARG_POINTER_REGNUM);
3148 /* Return nonzero if X is a valid ARM state address operand. */
3150 arm_legitimate_address_p (enum machine_mode mode, rtx x, RTX_CODE outer,
3154 enum rtx_code code = GET_CODE (x);
3156 if (arm_address_register_rtx_p (x, strict_p))
3159 use_ldrd = (TARGET_LDRD
3161 || (mode == DFmode && (TARGET_SOFT_FLOAT || TARGET_VFP))));
3163 if (code == POST_INC || code == PRE_DEC
3164 || ((code == PRE_INC || code == POST_DEC)
3165 && (use_ldrd || GET_MODE_SIZE (mode) <= 4)))
3166 return arm_address_register_rtx_p (XEXP (x, 0), strict_p);
3168 else if ((code == POST_MODIFY || code == PRE_MODIFY)
3169 && arm_address_register_rtx_p (XEXP (x, 0), strict_p)
3170 && GET_CODE (XEXP (x, 1)) == PLUS
3171 && rtx_equal_p (XEXP (XEXP (x, 1), 0), XEXP (x, 0)))
3173 rtx addend = XEXP (XEXP (x, 1), 1);
3175 /* Don't allow ldrd post increment by register because it's hard
3176 to fixup invalid register choices. */
3178 && GET_CODE (x) == POST_MODIFY
3179 && GET_CODE (addend) == REG)
3182 return ((use_ldrd || GET_MODE_SIZE (mode) <= 4)
3183 && arm_legitimate_index_p (mode, addend, outer, strict_p));
3186 /* After reload constants split into minipools will have addresses
3187 from a LABEL_REF. */
3188 else if (reload_completed
3189 && (code == LABEL_REF
3191 && GET_CODE (XEXP (x, 0)) == PLUS
3192 && GET_CODE (XEXP (XEXP (x, 0), 0)) == LABEL_REF
3193 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT)))
3196 else if (mode == TImode)
3199 else if (code == PLUS)
3201 rtx xop0 = XEXP (x, 0);
3202 rtx xop1 = XEXP (x, 1);
3204 return ((arm_address_register_rtx_p (xop0, strict_p)
3205 && arm_legitimate_index_p (mode, xop1, outer, strict_p))
3206 || (arm_address_register_rtx_p (xop1, strict_p)
3207 && arm_legitimate_index_p (mode, xop0, outer, strict_p)));
3211 /* Reload currently can't handle MINUS, so disable this for now */
3212 else if (GET_CODE (x) == MINUS)
3214 rtx xop0 = XEXP (x, 0);
3215 rtx xop1 = XEXP (x, 1);
3217 return (arm_address_register_rtx_p (xop0, strict_p)
3218 && arm_legitimate_index_p (mode, xop1, outer, strict_p));
3222 else if (GET_MODE_CLASS (mode) != MODE_FLOAT
3223 && code == SYMBOL_REF
3224 && CONSTANT_POOL_ADDRESS_P (x)
3226 && symbol_mentioned_p (get_pool_constant (x))))
3232 /* Return nonzero if INDEX is valid for an address index operand in
3235 arm_legitimate_index_p (enum machine_mode mode, rtx index, RTX_CODE outer,
3238 HOST_WIDE_INT range;
3239 enum rtx_code code = GET_CODE (index);
3241 /* Standard coprocessor addressing modes. */
3242 if (TARGET_HARD_FLOAT
3243 && (TARGET_FPA || TARGET_MAVERICK)
3244 && (GET_MODE_CLASS (mode) == MODE_FLOAT
3245 || (TARGET_MAVERICK && mode == DImode)))
3246 return (code == CONST_INT && INTVAL (index) < 1024
3247 && INTVAL (index) > -1024
3248 && (INTVAL (index) & 3) == 0);
3250 if (TARGET_REALLY_IWMMXT && VALID_IWMMXT_REG_MODE (mode))
3251 return (code == CONST_INT
3252 && INTVAL (index) < 1024
3253 && INTVAL (index) > -1024
3254 && (INTVAL (index) & 3) == 0);
3256 if (arm_address_register_rtx_p (index, strict_p)
3257 && (GET_MODE_SIZE (mode) <= 4))
3260 if (mode == DImode || mode == DFmode)
3262 if (code == CONST_INT)
3264 HOST_WIDE_INT val = INTVAL (index);
3267 return val > -256 && val < 256;
3269 return val > -4096 && val < 4092;
3272 return TARGET_LDRD && arm_address_register_rtx_p (index, strict_p);
3275 if (GET_MODE_SIZE (mode) <= 4
3278 || (mode == QImode && outer == SIGN_EXTEND))))
3282 rtx xiop0 = XEXP (index, 0);
3283 rtx xiop1 = XEXP (index, 1);
3285 return ((arm_address_register_rtx_p (xiop0, strict_p)
3286 && power_of_two_operand (xiop1, SImode))
3287 || (arm_address_register_rtx_p (xiop1, strict_p)
3288 && power_of_two_operand (xiop0, SImode)));
3290 else if (code == LSHIFTRT || code == ASHIFTRT
3291 || code == ASHIFT || code == ROTATERT)
3293 rtx op = XEXP (index, 1);
3295 return (arm_address_register_rtx_p (XEXP (index, 0), strict_p)
3296 && GET_CODE (op) == CONST_INT
3298 && INTVAL (op) <= 31);
3302 /* For ARM v4 we may be doing a sign-extend operation during the
3306 if (mode == HImode || (outer == SIGN_EXTEND && mode == QImode))
3312 range = (mode == HImode) ? 4095 : 4096;
3314 return (code == CONST_INT
3315 && INTVAL (index) < range
3316 && INTVAL (index) > -range);
3319 /* Return nonzero if X is valid as a Thumb state base register. */
3321 thumb_base_register_rtx_p (rtx x, enum machine_mode mode, int strict_p)
3325 if (GET_CODE (x) != REG)
3331 return THUMB_REGNO_MODE_OK_FOR_BASE_P (regno, mode);
3333 return (regno <= LAST_LO_REGNUM
3334 || regno > LAST_VIRTUAL_REGISTER
3335 || regno == FRAME_POINTER_REGNUM
3336 || (GET_MODE_SIZE (mode) >= 4
3337 && (regno == STACK_POINTER_REGNUM
3338 || regno >= FIRST_PSEUDO_REGISTER
3339 || x == hard_frame_pointer_rtx
3340 || x == arg_pointer_rtx)));
3343 /* Return nonzero if x is a legitimate index register. This is the case
3344 for any base register that can access a QImode object. */
3346 thumb_index_register_rtx_p (rtx x, int strict_p)
3348 return thumb_base_register_rtx_p (x, QImode, strict_p);
3351 /* Return nonzero if x is a legitimate Thumb-state address.
3353 The AP may be eliminated to either the SP or the FP, so we use the
3354 least common denominator, e.g. SImode, and offsets from 0 to 64.
3356 ??? Verify whether the above is the right approach.
3358 ??? Also, the FP may be eliminated to the SP, so perhaps that
3359 needs special handling also.
3361 ??? Look at how the mips16 port solves this problem. It probably uses
3362 better ways to solve some of these problems.
3364 Although it is not incorrect, we don't accept QImode and HImode
3365 addresses based on the frame pointer or arg pointer until the
3366 reload pass starts. This is so that eliminating such addresses
3367 into stack based ones won't produce impossible code. */
3369 thumb_legitimate_address_p (enum machine_mode mode, rtx x, int strict_p)
3371 /* ??? Not clear if this is right. Experiment. */
3372 if (GET_MODE_SIZE (mode) < 4
3373 && !(reload_in_progress || reload_completed)
3374 && (reg_mentioned_p (frame_pointer_rtx, x)
3375 || reg_mentioned_p (arg_pointer_rtx, x)
3376 || reg_mentioned_p (virtual_incoming_args_rtx, x)
3377 || reg_mentioned_p (virtual_outgoing_args_rtx, x)
3378 || reg_mentioned_p (virtual_stack_dynamic_rtx, x)
3379 || reg_mentioned_p (virtual_stack_vars_rtx, x)))
3382 /* Accept any base register. SP only in SImode or larger. */
3383 else if (thumb_base_register_rtx_p (x, mode, strict_p))
3386 /* This is PC relative data before arm_reorg runs. */
3387 else if (GET_MODE_SIZE (mode) >= 4 && CONSTANT_P (x)
3388 && GET_CODE (x) == SYMBOL_REF
3389 && CONSTANT_POOL_ADDRESS_P (x) && ! flag_pic)
3392 /* This is PC relative data after arm_reorg runs. */
3393 else if (GET_MODE_SIZE (mode) >= 4 && reload_completed
3394 && (GET_CODE (x) == LABEL_REF
3395 || (GET_CODE (x) == CONST
3396 && GET_CODE (XEXP (x, 0)) == PLUS
3397 && GET_CODE (XEXP (XEXP (x, 0), 0)) == LABEL_REF
3398 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT)))
3401 /* Post-inc indexing only supported for SImode and larger. */
3402 else if (GET_CODE (x) == POST_INC && GET_MODE_SIZE (mode) >= 4
3403 && thumb_index_register_rtx_p (XEXP (x, 0), strict_p))
3406 else if (GET_CODE (x) == PLUS)
3408 /* REG+REG address can be any two index registers. */
3409 /* We disallow FRAME+REG addressing since we know that FRAME
3410 will be replaced with STACK, and SP relative addressing only
3411 permits SP+OFFSET. */
3412 if (GET_MODE_SIZE (mode) <= 4
3413 && XEXP (x, 0) != frame_pointer_rtx
3414 && XEXP (x, 1) != frame_pointer_rtx
3415 && thumb_index_register_rtx_p (XEXP (x, 0), strict_p)
3416 && thumb_index_register_rtx_p (XEXP (x, 1), strict_p))
3419 /* REG+const has 5-7 bit offset for non-SP registers. */
3420 else if ((thumb_index_register_rtx_p (XEXP (x, 0), strict_p)
3421 || XEXP (x, 0) == arg_pointer_rtx)
3422 && GET_CODE (XEXP (x, 1)) == CONST_INT
3423 && thumb_legitimate_offset_p (mode, INTVAL (XEXP (x, 1))))
3426 /* REG+const has 10 bit offset for SP, but only SImode and
3427 larger is supported. */
3428 /* ??? Should probably check for DI/DFmode overflow here
3429 just like GO_IF_LEGITIMATE_OFFSET does. */
3430 else if (GET_CODE (XEXP (x, 0)) == REG
3431 && REGNO (XEXP (x, 0)) == STACK_POINTER_REGNUM
3432 && GET_MODE_SIZE (mode) >= 4
3433 && GET_CODE (XEXP (x, 1)) == CONST_INT
3434 && INTVAL (XEXP (x, 1)) >= 0
3435 && INTVAL (XEXP (x, 1)) + GET_MODE_SIZE (mode) <= 1024
3436 && (INTVAL (XEXP (x, 1)) & 3) == 0)
3439 else if (GET_CODE (XEXP (x, 0)) == REG
3440 && REGNO (XEXP (x, 0)) == FRAME_POINTER_REGNUM
3441 && GET_MODE_SIZE (mode) >= 4
3442 && GET_CODE (XEXP (x, 1)) == CONST_INT
3443 && (INTVAL (XEXP (x, 1)) & 3) == 0)
3447 else if (GET_MODE_CLASS (mode) != MODE_FLOAT
3448 && GET_MODE_SIZE (mode) == 4
3449 && GET_CODE (x) == SYMBOL_REF
3450 && CONSTANT_POOL_ADDRESS_P (x)
3452 && symbol_mentioned_p (get_pool_constant (x))))
3458 /* Return nonzero if VAL can be used as an offset in a Thumb-state address
3459 instruction of mode MODE. */
3461 thumb_legitimate_offset_p (enum machine_mode mode, HOST_WIDE_INT val)
3463 switch (GET_MODE_SIZE (mode))
3466 return val >= 0 && val < 32;
3469 return val >= 0 && val < 64 && (val & 1) == 0;
3473 && (val + GET_MODE_SIZE (mode)) <= 128
3478 /* Try machine-dependent ways of modifying an illegitimate address
3479 to be legitimate. If we find one, return the new, valid address. */
3481 arm_legitimize_address (rtx x, rtx orig_x, enum machine_mode mode)
3483 if (GET_CODE (x) == PLUS)
3485 rtx xop0 = XEXP (x, 0);
3486 rtx xop1 = XEXP (x, 1);
3488 if (CONSTANT_P (xop0) && !symbol_mentioned_p (xop0))
3489 xop0 = force_reg (SImode, xop0);
3491 if (CONSTANT_P (xop1) && !symbol_mentioned_p (xop1))
3492 xop1 = force_reg (SImode, xop1);
3494 if (ARM_BASE_REGISTER_RTX_P (xop0)
3495 && GET_CODE (xop1) == CONST_INT)
3497 HOST_WIDE_INT n, low_n;
3501 /* VFP addressing modes actually allow greater offsets, but for
3502 now we just stick with the lowest common denominator. */
3504 || ((TARGET_SOFT_FLOAT || TARGET_VFP) && mode == DFmode))
3516 low_n = ((mode) == TImode ? 0
3517 : n >= 0 ? (n & 0xfff) : -((-n) & 0xfff));
3521 base_reg = gen_reg_rtx (SImode);
3522 val = force_operand (gen_rtx_PLUS (SImode, xop0,
3523 GEN_INT (n)), NULL_RTX);
3524 emit_move_insn (base_reg, val);
3525 x = (low_n == 0 ? base_reg
3526 : gen_rtx_PLUS (SImode, base_reg, GEN_INT (low_n)));
3528 else if (xop0 != XEXP (x, 0) || xop1 != XEXP (x, 1))
3529 x = gen_rtx_PLUS (SImode, xop0, xop1);
3532 /* XXX We don't allow MINUS any more -- see comment in
3533 arm_legitimate_address_p (). */
3534 else if (GET_CODE (x) == MINUS)
3536 rtx xop0 = XEXP (x, 0);
3537 rtx xop1 = XEXP (x, 1);
3539 if (CONSTANT_P (xop0))
3540 xop0 = force_reg (SImode, xop0);
3542 if (CONSTANT_P (xop1) && ! symbol_mentioned_p (xop1))
3543 xop1 = force_reg (SImode, xop1);
3545 if (xop0 != XEXP (x, 0) || xop1 != XEXP (x, 1))
3546 x = gen_rtx_MINUS (SImode, xop0, xop1);
3551 /* We need to find and carefully transform any SYMBOL and LABEL
3552 references; so go back to the original address expression. */
3553 rtx new_x = legitimize_pic_address (orig_x, mode, NULL_RTX);
3555 if (new_x != orig_x)
3563 /* Try machine-dependent ways of modifying an illegitimate Thumb address
3564 to be legitimate. If we find one, return the new, valid address. */
3566 thumb_legitimize_address (rtx x, rtx orig_x, enum machine_mode mode)
3568 if (GET_CODE (x) == PLUS
3569 && GET_CODE (XEXP (x, 1)) == CONST_INT
3570 && (INTVAL (XEXP (x, 1)) >= 32 * GET_MODE_SIZE (mode)
3571 || INTVAL (XEXP (x, 1)) < 0))
3573 rtx xop0 = XEXP (x, 0);
3574 rtx xop1 = XEXP (x, 1);
3575 HOST_WIDE_INT offset = INTVAL (xop1);
3577 /* Try and fold the offset into a biasing of the base register and
3578 then offsetting that. Don't do this when optimizing for space
3579 since it can cause too many CSEs. */
3580 if (optimize_size && offset >= 0
3581 && offset < 256 + 31 * GET_MODE_SIZE (mode))
3583 HOST_WIDE_INT delta;
3586 delta = offset - (256 - GET_MODE_SIZE (mode));
3587 else if (offset < 32 * GET_MODE_SIZE (mode) + 8)
3588 delta = 31 * GET_MODE_SIZE (mode);
3590 delta = offset & (~31 * GET_MODE_SIZE (mode));
3592 xop0 = force_operand (plus_constant (xop0, offset - delta),
3594 x = plus_constant (xop0, delta);
3596 else if (offset < 0 && offset > -256)
3597 /* Small negative offsets are best done with a subtract before the
3598 dereference, forcing these into a register normally takes two
3600 x = force_operand (x, NULL_RTX);
3603 /* For the remaining cases, force the constant into a register. */
3604 xop1 = force_reg (SImode, xop1);
3605 x = gen_rtx_PLUS (SImode, xop0, xop1);
3608 else if (GET_CODE (x) == PLUS
3609 && s_register_operand (XEXP (x, 1), SImode)
3610 && !s_register_operand (XEXP (x, 0), SImode))
3612 rtx xop0 = force_operand (XEXP (x, 0), NULL_RTX);
3614 x = gen_rtx_PLUS (SImode, xop0, XEXP (x, 1));
3619 /* We need to find and carefully transform any SYMBOL and LABEL
3620 references; so go back to the original address expression. */
3621 rtx new_x = legitimize_pic_address (orig_x, mode, NULL_RTX);
3623 if (new_x != orig_x)
3632 #define REG_OR_SUBREG_REG(X) \
3633 (GET_CODE (X) == REG \
3634 || (GET_CODE (X) == SUBREG && GET_CODE (SUBREG_REG (X)) == REG))
3636 #define REG_OR_SUBREG_RTX(X) \
3637 (GET_CODE (X) == REG ? (X) : SUBREG_REG (X))
3639 #ifndef COSTS_N_INSNS
3640 #define COSTS_N_INSNS(N) ((N) * 4 - 2)
3643 thumb_rtx_costs (rtx x, enum rtx_code code, enum rtx_code outer)
3645 enum machine_mode mode = GET_MODE (x);
3658 return COSTS_N_INSNS (1);
3661 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
3664 unsigned HOST_WIDE_INT i = INTVAL (XEXP (x, 1));
3671 return COSTS_N_INSNS (2) + cycles;
3673 return COSTS_N_INSNS (1) + 16;
3676 return (COSTS_N_INSNS (1)
3677 + 4 * ((GET_CODE (SET_SRC (x)) == MEM)
3678 + GET_CODE (SET_DEST (x)) == MEM));
3683 if ((unsigned HOST_WIDE_INT) INTVAL (x) < 256)
3685 if (thumb_shiftable_const (INTVAL (x)))
3686 return COSTS_N_INSNS (2);
3687 return COSTS_N_INSNS (3);
3689 else if ((outer == PLUS || outer == COMPARE)
3690 && INTVAL (x) < 256 && INTVAL (x) > -256)
3692 else if (outer == AND
3693 && INTVAL (x) < 256 && INTVAL (x) >= -256)
3694 return COSTS_N_INSNS (1);
3695 else if (outer == ASHIFT || outer == ASHIFTRT
3696 || outer == LSHIFTRT)
3698 return COSTS_N_INSNS (2);
3704 return COSTS_N_INSNS (3);
3722 /* XXX another guess. */
3723 /* Memory costs quite a lot for the first word, but subsequent words
3724 load at the equivalent of a single insn each. */
3725 return (10 + 4 * ((GET_MODE_SIZE (mode) - 1) / UNITS_PER_WORD)
3726 + ((GET_CODE (x) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (x))
3731 if (GET_CODE (XEXP (x, 1)) == PC || GET_CODE (XEXP (x, 2)) == PC)
3736 /* XXX still guessing. */
3737 switch (GET_MODE (XEXP (x, 0)))
3740 return (1 + (mode == DImode ? 4 : 0)
3741 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0));
3744 return (4 + (mode == DImode ? 4 : 0)
3745 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0));
3748 return (1 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0));
3760 /* Worker routine for arm_rtx_costs. */
3762 arm_rtx_costs_1 (rtx x, enum rtx_code code, enum rtx_code outer)
3764 enum machine_mode mode = GET_MODE (x);
3765 enum rtx_code subcode;
3771 /* Memory costs quite a lot for the first word, but subsequent words
3772 load at the equivalent of a single insn each. */
3773 return (10 + 4 * ((GET_MODE_SIZE (mode) - 1) / UNITS_PER_WORD)
3774 + (GET_CODE (x) == SYMBOL_REF
3775 && CONSTANT_POOL_ADDRESS_P (x) ? 4 : 0));
3781 return optimize_size ? COSTS_N_INSNS (2) : 100;
3784 if (mode == SImode && GET_CODE (XEXP (x, 1)) == REG)
3791 case ASHIFT: case LSHIFTRT: case ASHIFTRT:
3793 return (8 + (GET_CODE (XEXP (x, 1)) == CONST_INT ? 0 : 8)
3794 + ((GET_CODE (XEXP (x, 0)) == REG
3795 || (GET_CODE (XEXP (x, 0)) == SUBREG
3796 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == REG))
3798 return (1 + ((GET_CODE (XEXP (x, 0)) == REG
3799 || (GET_CODE (XEXP (x, 0)) == SUBREG
3800 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == REG))
3802 + ((GET_CODE (XEXP (x, 1)) == REG
3803 || (GET_CODE (XEXP (x, 1)) == SUBREG
3804 && GET_CODE (SUBREG_REG (XEXP (x, 1))) == REG)
3805 || (GET_CODE (XEXP (x, 1)) == CONST_INT))
3810 return (4 + (REG_OR_SUBREG_REG (XEXP (x, 1)) ? 0 : 8)
3811 + ((REG_OR_SUBREG_REG (XEXP (x, 0))
3812 || (GET_CODE (XEXP (x, 0)) == CONST_INT
3813 && const_ok_for_arm (INTVAL (XEXP (x, 0)))))
3816 if (GET_MODE_CLASS (mode) == MODE_FLOAT)
3817 return (2 + ((REG_OR_SUBREG_REG (XEXP (x, 1))
3818 || (GET_CODE (XEXP (x, 1)) == CONST_DOUBLE
3819 && arm_const_double_rtx (XEXP (x, 1))))
3821 + ((REG_OR_SUBREG_REG (XEXP (x, 0))
3822 || (GET_CODE (XEXP (x, 0)) == CONST_DOUBLE
3823 && arm_const_double_rtx (XEXP (x, 0))))
3826 if (((GET_CODE (XEXP (x, 0)) == CONST_INT
3827 && const_ok_for_arm (INTVAL (XEXP (x, 0)))
3828 && REG_OR_SUBREG_REG (XEXP (x, 1))))
3829 || (((subcode = GET_CODE (XEXP (x, 1))) == ASHIFT
3830 || subcode == ASHIFTRT || subcode == LSHIFTRT
3831 || subcode == ROTATE || subcode == ROTATERT
3833 && GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT
3834 && ((INTVAL (XEXP (XEXP (x, 1), 1)) &
3835 (INTVAL (XEXP (XEXP (x, 1), 1)) - 1)) == 0)))
3836 && REG_OR_SUBREG_REG (XEXP (XEXP (x, 1), 0))
3837 && (REG_OR_SUBREG_REG (XEXP (XEXP (x, 1), 1))
3838 || GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT)
3839 && REG_OR_SUBREG_REG (XEXP (x, 0))))
3844 if (GET_MODE_CLASS (mode) == MODE_FLOAT)
3845 return (2 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 8)
3846 + ((REG_OR_SUBREG_REG (XEXP (x, 1))
3847 || (GET_CODE (XEXP (x, 1)) == CONST_DOUBLE
3848 && arm_const_double_rtx (XEXP (x, 1))))
3852 case AND: case XOR: case IOR:
3855 /* Normally the frame registers will be spilt into reg+const during
3856 reload, so it is a bad idea to combine them with other instructions,
3857 since then they might not be moved outside of loops. As a compromise
3858 we allow integration with ops that have a constant as their second
3860 if ((REG_OR_SUBREG_REG (XEXP (x, 0))
3861 && ARM_FRAME_RTX (REG_OR_SUBREG_RTX (XEXP (x, 0)))
3862 && GET_CODE (XEXP (x, 1)) != CONST_INT)
3863 || (REG_OR_SUBREG_REG (XEXP (x, 0))
3864 && ARM_FRAME_RTX (REG_OR_SUBREG_RTX (XEXP (x, 0)))))
3868 return (4 + extra_cost + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 8)
3869 + ((REG_OR_SUBREG_REG (XEXP (x, 1))
3870 || (GET_CODE (XEXP (x, 1)) == CONST_INT
3871 && const_ok_for_op (INTVAL (XEXP (x, 1)), code)))
3874 if (REG_OR_SUBREG_REG (XEXP (x, 0)))
3875 return (1 + (GET_CODE (XEXP (x, 1)) == CONST_INT ? 0 : extra_cost)
3876 + ((REG_OR_SUBREG_REG (XEXP (x, 1))
3877 || (GET_CODE (XEXP (x, 1)) == CONST_INT
3878 && const_ok_for_op (INTVAL (XEXP (x, 1)), code)))
3881 else if (REG_OR_SUBREG_REG (XEXP (x, 1)))
3882 return (1 + extra_cost
3883 + ((((subcode = GET_CODE (XEXP (x, 0))) == ASHIFT
3884 || subcode == LSHIFTRT || subcode == ASHIFTRT
3885 || subcode == ROTATE || subcode == ROTATERT
3887 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3888 && ((INTVAL (XEXP (XEXP (x, 0), 1)) &
3889 (INTVAL (XEXP (XEXP (x, 0), 1)) - 1)) == 0)))
3890 && (REG_OR_SUBREG_REG (XEXP (XEXP (x, 0), 0)))
3891 && ((REG_OR_SUBREG_REG (XEXP (XEXP (x, 0), 1)))
3892 || GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT))
3898 /* This should have been handled by the CPU specific routines. */
3902 if (arm_arch3m && mode == SImode
3903 && GET_CODE (XEXP (x, 0)) == LSHIFTRT
3904 && GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT
3905 && (GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 0))
3906 == GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)))
3907 && (GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == ZERO_EXTEND
3908 || GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == SIGN_EXTEND))
3913 if (GET_MODE_CLASS (mode) == MODE_FLOAT)
3914 return 4 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 6);
3918 return 4 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 4);
3920 return 1 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 4);
3923 if (GET_CODE (XEXP (x, 1)) == PC || GET_CODE (XEXP (x, 2)) == PC)
3931 return 4 + (mode == DImode ? 4 : 0);
3934 if (GET_MODE (XEXP (x, 0)) == QImode)
3935 return (4 + (mode == DImode ? 4 : 0)
3936 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0));
3939 switch (GET_MODE (XEXP (x, 0)))
3942 return (1 + (mode == DImode ? 4 : 0)
3943 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0));
3946 return (4 + (mode == DImode ? 4 : 0)
3947 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0));
3950 return (1 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0));
3965 if (const_ok_for_arm (INTVAL (x)))
3966 return outer == SET ? 2 : -1;
3967 else if (outer == AND
3968 && const_ok_for_arm (~INTVAL (x)))
3970 else if ((outer == COMPARE
3971 || outer == PLUS || outer == MINUS)
3972 && const_ok_for_arm (-INTVAL (x)))
3983 if (arm_const_double_rtx (x))
3984 return outer == SET ? 2 : -1;
3985 else if ((outer == COMPARE || outer == PLUS)
3986 && neg_const_double_rtx_ok_for_fpa (x))
3995 /* RTX costs when optimizing for size. */
3997 arm_size_rtx_costs (rtx x, int code, int outer_code, int *total)
3999 enum machine_mode mode = GET_MODE (x);
4003 /* XXX TBD. For now, use the standard costs. */
4004 *total = thumb_rtx_costs (x, code, outer_code);
4011 /* A memory access costs 1 insn if the mode is small, or the address is
4012 a single register, otherwise it costs one insn per word. */
4013 if (REG_P (XEXP (x, 0)))
4014 *total = COSTS_N_INSNS (1);
4016 *total = COSTS_N_INSNS (ARM_NUM_REGS (mode));
4023 /* Needs a libcall, so it costs about this. */
4024 *total = COSTS_N_INSNS (2);
4028 if (mode == SImode && GET_CODE (XEXP (x, 1)) == REG)
4030 *total = COSTS_N_INSNS (2) + rtx_cost (XEXP (x, 0), code);
4038 if (mode == DImode && GET_CODE (XEXP (x, 1)) == CONST_INT)
4040 *total = COSTS_N_INSNS (3) + rtx_cost (XEXP (x, 0), code);
4043 else if (mode == SImode)
4045 *total = COSTS_N_INSNS (1) + rtx_cost (XEXP (x, 0), code);
4046 /* Slightly disparage register shifts, but not by much. */
4047 if (GET_CODE (XEXP (x, 1)) != CONST_INT)
4048 *total += 1 + rtx_cost (XEXP (x, 1), code);
4052 /* Needs a libcall. */
4053 *total = COSTS_N_INSNS (2);
4057 if (TARGET_HARD_FLOAT && GET_MODE_CLASS (mode) == MODE_FLOAT)
4059 *total = COSTS_N_INSNS (1);
4065 enum rtx_code subcode0 = GET_CODE (XEXP (x, 0));
4066 enum rtx_code subcode1 = GET_CODE (XEXP (x, 1));
4068 if (subcode0 == ROTATE || subcode0 == ROTATERT || subcode0 == ASHIFT
4069 || subcode0 == LSHIFTRT || subcode0 == ASHIFTRT
4070 || subcode1 == ROTATE || subcode1 == ROTATERT
4071 || subcode1 == ASHIFT || subcode1 == LSHIFTRT
4072 || subcode1 == ASHIFTRT)
4074 /* It's just the cost of the two operands. */
4079 *total = COSTS_N_INSNS (1);
4083 *total = COSTS_N_INSNS (ARM_NUM_REGS (mode));
4087 if (TARGET_HARD_FLOAT && GET_MODE_CLASS (mode) == MODE_FLOAT)
4089 *total = COSTS_N_INSNS (1);
4094 case AND: case XOR: case IOR:
4097 enum rtx_code subcode = GET_CODE (XEXP (x, 0));
4099 if (subcode == ROTATE || subcode == ROTATERT || subcode == ASHIFT
4100 || subcode == LSHIFTRT || subcode == ASHIFTRT
4101 || (code == AND && subcode == NOT))
4103 /* It's just the cost of the two operands. */
4109 *total = COSTS_N_INSNS (ARM_NUM_REGS (mode));
4113 *total = COSTS_N_INSNS (ARM_NUM_REGS (mode));
4117 if (TARGET_HARD_FLOAT && GET_MODE_CLASS (mode) == MODE_FLOAT)
4118 *total = COSTS_N_INSNS (1);
4121 *total = COSTS_N_INSNS (ARM_NUM_REGS (mode));
4130 if (cc_register (XEXP (x, 0), VOIDmode))
4133 *total = COSTS_N_INSNS (1);
4137 if (TARGET_HARD_FLOAT && GET_MODE_CLASS (mode) == MODE_FLOAT)
4138 *total = COSTS_N_INSNS (1);
4140 *total = COSTS_N_INSNS (1 + ARM_NUM_REGS (mode));
4145 if (GET_MODE_SIZE (GET_MODE (XEXP (x, 0))) < 4)
4147 if (!(arm_arch4 && MEM_P (XEXP (x, 0))))
4148 *total += COSTS_N_INSNS (arm_arch6 ? 1 : 2);
4151 *total += COSTS_N_INSNS (1);
4156 if (!(arm_arch4 && MEM_P (XEXP (x, 0))))
4158 switch (GET_MODE (XEXP (x, 0)))
4161 *total += COSTS_N_INSNS (1);
4165 *total += COSTS_N_INSNS (arm_arch6 ? 1 : 2);
4171 *total += COSTS_N_INSNS (2);
4176 *total += COSTS_N_INSNS (1);
4181 if (const_ok_for_arm (INTVAL (x)))
4182 *total = COSTS_N_INSNS (outer_code == SET ? 1 : 0);
4183 else if (const_ok_for_arm (~INTVAL (x)))
4184 *total = COSTS_N_INSNS (outer_code == AND ? 0 : 1);
4185 else if (const_ok_for_arm (-INTVAL (x)))
4187 if (outer_code == COMPARE || outer_code == PLUS
4188 || outer_code == MINUS)
4191 *total = COSTS_N_INSNS (1);
4194 *total = COSTS_N_INSNS (2);
4200 *total = COSTS_N_INSNS (2);
4204 *total = COSTS_N_INSNS (4);
4208 if (mode != VOIDmode)
4209 *total = COSTS_N_INSNS (ARM_NUM_REGS (mode));
4211 *total = COSTS_N_INSNS (4); /* How knows? */
4216 /* RTX costs for cores with a slow MUL implementation. */
4219 arm_slowmul_rtx_costs (rtx x, int code, int outer_code, int *total)
4221 enum machine_mode mode = GET_MODE (x);
4225 *total = thumb_rtx_costs (x, code, outer_code);
4232 if (GET_MODE_CLASS (mode) == MODE_FLOAT
4239 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
4241 unsigned HOST_WIDE_INT i = (INTVAL (XEXP (x, 1))
4242 & (unsigned HOST_WIDE_INT) 0xffffffff);
4243 int cost, const_ok = const_ok_for_arm (i);
4244 int j, booth_unit_size;
4246 /* Tune as appropriate. */
4247 cost = const_ok ? 4 : 8;
4248 booth_unit_size = 2;
4249 for (j = 0; i && j < 32; j += booth_unit_size)
4251 i >>= booth_unit_size;
4259 *total = 30 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 4)
4260 + (REG_OR_SUBREG_REG (XEXP (x, 1)) ? 0 : 4);
4264 *total = arm_rtx_costs_1 (x, code, outer_code);
4270 /* RTX cost for cores with a fast multiply unit (M variants). */
4273 arm_fastmul_rtx_costs (rtx x, int code, int outer_code, int *total)
4275 enum machine_mode mode = GET_MODE (x);
4279 *total = thumb_rtx_costs (x, code, outer_code);
4286 /* There is no point basing this on the tuning, since it is always the
4287 fast variant if it exists at all. */
4289 && (GET_CODE (XEXP (x, 0)) == GET_CODE (XEXP (x, 1)))
4290 && (GET_CODE (XEXP (x, 0)) == ZERO_EXTEND
4291 || GET_CODE (XEXP (x, 0)) == SIGN_EXTEND))
4298 if (GET_MODE_CLASS (mode) == MODE_FLOAT
4305 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
4307 unsigned HOST_WIDE_INT i = (INTVAL (XEXP (x, 1))
4308 & (unsigned HOST_WIDE_INT) 0xffffffff);
4309 int cost, const_ok = const_ok_for_arm (i);
4310 int j, booth_unit_size;
4312 /* Tune as appropriate. */
4313 cost = const_ok ? 4 : 8;
4314 booth_unit_size = 8;
4315 for (j = 0; i && j < 32; j += booth_unit_size)
4317 i >>= booth_unit_size;
4325 *total = 8 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 4)
4326 + (REG_OR_SUBREG_REG (XEXP (x, 1)) ? 0 : 4);
4330 *total = arm_rtx_costs_1 (x, code, outer_code);
4336 /* RTX cost for XScale CPUs. */
4339 arm_xscale_rtx_costs (rtx x, int code, int outer_code, int *total)
4341 enum machine_mode mode = GET_MODE (x);
4345 *total = thumb_rtx_costs (x, code, outer_code);
4352 /* There is no point basing this on the tuning, since it is always the
4353 fast variant if it exists at all. */
4355 && (GET_CODE (XEXP (x, 0)) == GET_CODE (XEXP (x, 1)))
4356 && (GET_CODE (XEXP (x, 0)) == ZERO_EXTEND
4357 || GET_CODE (XEXP (x, 0)) == SIGN_EXTEND))
4364 if (GET_MODE_CLASS (mode) == MODE_FLOAT
4371 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
4373 unsigned HOST_WIDE_INT i = (INTVAL (XEXP (x, 1))
4374 & (unsigned HOST_WIDE_INT) 0xffffffff);
4375 int cost, const_ok = const_ok_for_arm (i);
4376 unsigned HOST_WIDE_INT masked_const;
4378 /* The cost will be related to two insns.
4379 First a load of the constant (MOV or LDR), then a multiply. */
4382 cost += 1; /* LDR is probably more expensive because
4383 of longer result latency. */
4384 masked_const = i & 0xffff8000;
4385 if (masked_const != 0 && masked_const != 0xffff8000)
4387 masked_const = i & 0xf8000000;
4388 if (masked_const == 0 || masked_const == 0xf8000000)
4397 *total = 8 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 4)
4398 + (REG_OR_SUBREG_REG (XEXP (x, 1)) ? 0 : 4);
4402 *total = arm_rtx_costs_1 (x, code, outer_code);
4408 /* RTX costs for 9e (and later) cores. */
4411 arm_9e_rtx_costs (rtx x, int code, int outer_code, int *total)
4413 enum machine_mode mode = GET_MODE (x);
4422 *total = COSTS_N_INSNS (3);
4426 *total = thumb_rtx_costs (x, code, outer_code);
4434 /* There is no point basing this on the tuning, since it is always the
4435 fast variant if it exists at all. */
4437 && (GET_CODE (XEXP (x, 0)) == GET_CODE (XEXP (x, 1)))
4438 && (GET_CODE (XEXP (x, 0)) == ZERO_EXTEND
4439 || GET_CODE (XEXP (x, 0)) == SIGN_EXTEND))
4446 if (GET_MODE_CLASS (mode) == MODE_FLOAT)
4463 *total = cost + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : nonreg_cost)
4464 + (REG_OR_SUBREG_REG (XEXP (x, 1)) ? 0 : nonreg_cost);
4468 *total = arm_rtx_costs_1 (x, code, outer_code);
4472 /* All address computations that can be done are free, but rtx cost returns
4473 the same for practically all of them. So we weight the different types
4474 of address here in the order (most pref first):
4475 PRE/POST_INC/DEC, SHIFT or NON-INT sum, INT sum, REG, MEM or LABEL. */
4477 arm_arm_address_cost (rtx x)
4479 enum rtx_code c = GET_CODE (x);
4481 if (c == PRE_INC || c == PRE_DEC || c == POST_INC || c == POST_DEC)
4483 if (c == MEM || c == LABEL_REF || c == SYMBOL_REF)
4486 if (c == PLUS || c == MINUS)
4488 if (GET_CODE (XEXP (x, 0)) == CONST_INT)
4491 if (ARITHMETIC_P (XEXP (x, 0)) || ARITHMETIC_P (XEXP (x, 1)))
4501 arm_thumb_address_cost (rtx x)
4503 enum rtx_code c = GET_CODE (x);
4508 && GET_CODE (XEXP (x, 0)) == REG
4509 && GET_CODE (XEXP (x, 1)) == CONST_INT)
4516 arm_address_cost (rtx x)
4518 return TARGET_ARM ? arm_arm_address_cost (x) : arm_thumb_address_cost (x);
4522 arm_adjust_cost (rtx insn, rtx link, rtx dep, int cost)
4526 /* Some true dependencies can have a higher cost depending
4527 on precisely how certain input operands are used. */
4529 && REG_NOTE_KIND (link) == 0
4530 && recog_memoized (insn) >= 0
4531 && recog_memoized (dep) >= 0)
4533 int shift_opnum = get_attr_shift (insn);
4534 enum attr_type attr_type = get_attr_type (dep);
4536 /* If nonzero, SHIFT_OPNUM contains the operand number of a shifted
4537 operand for INSN. If we have a shifted input operand and the
4538 instruction we depend on is another ALU instruction, then we may
4539 have to account for an additional stall. */
4540 if (shift_opnum != 0
4541 && (attr_type == TYPE_ALU_SHIFT || attr_type == TYPE_ALU_SHIFT_REG))
4543 rtx shifted_operand;
4546 /* Get the shifted operand. */
4547 extract_insn (insn);
4548 shifted_operand = recog_data.operand[shift_opnum];
4550 /* Iterate over all the operands in DEP. If we write an operand
4551 that overlaps with SHIFTED_OPERAND, then we have increase the
4552 cost of this dependency. */
4554 preprocess_constraints ();
4555 for (opno = 0; opno < recog_data.n_operands; opno++)
4557 /* We can ignore strict inputs. */
4558 if (recog_data.operand_type[opno] == OP_IN)
4561 if (reg_overlap_mentioned_p (recog_data.operand[opno],
4568 /* XXX This is not strictly true for the FPA. */
4569 if (REG_NOTE_KIND (link) == REG_DEP_ANTI
4570 || REG_NOTE_KIND (link) == REG_DEP_OUTPUT)
4573 /* Call insns don't incur a stall, even if they follow a load. */
4574 if (REG_NOTE_KIND (link) == 0
4575 && GET_CODE (insn) == CALL_INSN)
4578 if ((i_pat = single_set (insn)) != NULL
4579 && GET_CODE (SET_SRC (i_pat)) == MEM
4580 && (d_pat = single_set (dep)) != NULL
4581 && GET_CODE (SET_DEST (d_pat)) == MEM)
4583 rtx src_mem = XEXP (SET_SRC (i_pat), 0);
4584 /* This is a load after a store, there is no conflict if the load reads
4585 from a cached area. Assume that loads from the stack, and from the
4586 constant pool are cached, and that others will miss. This is a
4589 if ((GET_CODE (src_mem) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (src_mem))
4590 || reg_mentioned_p (stack_pointer_rtx, src_mem)
4591 || reg_mentioned_p (frame_pointer_rtx, src_mem)
4592 || reg_mentioned_p (hard_frame_pointer_rtx, src_mem))
4599 static int fp_consts_inited = 0;
4601 /* Only zero is valid for VFP. Other values are also valid for FPA. */
4602 static const char * const strings_fp[8] =
4605 "4", "5", "0.5", "10"
4608 static REAL_VALUE_TYPE values_fp[8];
4611 init_fp_table (void)
4617 fp_consts_inited = 1;
4619 fp_consts_inited = 8;
4621 for (i = 0; i < fp_consts_inited; i++)
4623 r = REAL_VALUE_ATOF (strings_fp[i], DFmode);
4628 /* Return TRUE if rtx X is a valid immediate FP constant. */
4630 arm_const_double_rtx (rtx x)
4635 if (!fp_consts_inited)
4638 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
4639 if (REAL_VALUE_MINUS_ZERO (r))
4642 for (i = 0; i < fp_consts_inited; i++)
4643 if (REAL_VALUES_EQUAL (r, values_fp[i]))
4649 /* Return TRUE if rtx X is a valid immediate FPA constant. */
4651 neg_const_double_rtx_ok_for_fpa (rtx x)
4656 if (!fp_consts_inited)
4659 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
4660 r = REAL_VALUE_NEGATE (r);
4661 if (REAL_VALUE_MINUS_ZERO (r))
4664 for (i = 0; i < 8; i++)
4665 if (REAL_VALUES_EQUAL (r, values_fp[i]))
4671 /* Predicates for `match_operand' and `match_operator'. */
4673 /* Return nonzero if OP is a valid Cirrus memory address pattern. */
4675 cirrus_memory_offset (rtx op)
4677 /* Reject eliminable registers. */
4678 if (! (reload_in_progress || reload_completed)
4679 && ( reg_mentioned_p (frame_pointer_rtx, op)
4680 || reg_mentioned_p (arg_pointer_rtx, op)
4681 || reg_mentioned_p (virtual_incoming_args_rtx, op)
4682 || reg_mentioned_p (virtual_outgoing_args_rtx, op)
4683 || reg_mentioned_p (virtual_stack_dynamic_rtx, op)
4684 || reg_mentioned_p (virtual_stack_vars_rtx, op)))
4687 if (GET_CODE (op) == MEM)
4693 /* Match: (mem (reg)). */
4694 if (GET_CODE (ind) == REG)
4700 if (GET_CODE (ind) == PLUS
4701 && GET_CODE (XEXP (ind, 0)) == REG
4702 && REG_MODE_OK_FOR_BASE_P (XEXP (ind, 0), VOIDmode)
4703 && GET_CODE (XEXP (ind, 1)) == CONST_INT)
4710 /* Return TRUE if OP is a valid VFP memory address pattern.
4711 WB if true if writeback address modes are allowed. */
4714 arm_coproc_mem_operand (rtx op, bool wb)
4718 /* Reject eliminable registers. */
4719 if (! (reload_in_progress || reload_completed)
4720 && ( reg_mentioned_p (frame_pointer_rtx, op)
4721 || reg_mentioned_p (arg_pointer_rtx, op)
4722 || reg_mentioned_p (virtual_incoming_args_rtx, op)
4723 || reg_mentioned_p (virtual_outgoing_args_rtx, op)
4724 || reg_mentioned_p (virtual_stack_dynamic_rtx, op)
4725 || reg_mentioned_p (virtual_stack_vars_rtx, op)))
4728 /* Constants are converted into offsets from labels. */
4729 if (GET_CODE (op) != MEM)
4734 if (reload_completed
4735 && (GET_CODE (ind) == LABEL_REF
4736 || (GET_CODE (ind) == CONST
4737 && GET_CODE (XEXP (ind, 0)) == PLUS
4738 && GET_CODE (XEXP (XEXP (ind, 0), 0)) == LABEL_REF
4739 && GET_CODE (XEXP (XEXP (ind, 0), 1)) == CONST_INT)))
4742 /* Match: (mem (reg)). */
4743 if (GET_CODE (ind) == REG)
4744 return arm_address_register_rtx_p (ind, 0);
4746 /* Autoincremment addressing modes. */
4748 && (GET_CODE (ind) == PRE_INC
4749 || GET_CODE (ind) == POST_INC
4750 || GET_CODE (ind) == PRE_DEC
4751 || GET_CODE (ind) == POST_DEC))
4752 return arm_address_register_rtx_p (XEXP (ind, 0), 0);
4755 && (GET_CODE (ind) == POST_MODIFY || GET_CODE (ind) == PRE_MODIFY)
4756 && arm_address_register_rtx_p (XEXP (ind, 0), 0)
4757 && GET_CODE (XEXP (ind, 1)) == PLUS
4758 && rtx_equal_p (XEXP (XEXP (ind, 1), 0), XEXP (ind, 0)))
4759 ind = XEXP (ind, 1);
4764 if (GET_CODE (ind) == PLUS
4765 && GET_CODE (XEXP (ind, 0)) == REG
4766 && REG_MODE_OK_FOR_BASE_P (XEXP (ind, 0), VOIDmode)
4767 && GET_CODE (XEXP (ind, 1)) == CONST_INT
4768 && INTVAL (XEXP (ind, 1)) > -1024
4769 && INTVAL (XEXP (ind, 1)) < 1024
4770 && (INTVAL (XEXP (ind, 1)) & 3) == 0)
4777 /* Return GENERAL_REGS if a scratch register required to reload x to/from
4778 VFP registers. Otherwise return NO_REGS. */
4781 vfp_secondary_reload_class (enum machine_mode mode, rtx x)
4783 if (arm_coproc_mem_operand (x, FALSE) || s_register_operand (x, mode))
4786 return GENERAL_REGS;
4790 /* Returns TRUE if INSN is an "LDR REG, ADDR" instruction.
4791 Use by the Cirrus Maverick code which has to workaround
4792 a hardware bug triggered by such instructions. */
4794 arm_memory_load_p (rtx insn)
4796 rtx body, lhs, rhs;;
4798 if (insn == NULL_RTX || GET_CODE (insn) != INSN)
4801 body = PATTERN (insn);
4803 if (GET_CODE (body) != SET)
4806 lhs = XEXP (body, 0);
4807 rhs = XEXP (body, 1);
4809 lhs = REG_OR_SUBREG_RTX (lhs);
4811 /* If the destination is not a general purpose
4812 register we do not have to worry. */
4813 if (GET_CODE (lhs) != REG
4814 || REGNO_REG_CLASS (REGNO (lhs)) != GENERAL_REGS)
4817 /* As well as loads from memory we also have to react
4818 to loads of invalid constants which will be turned
4819 into loads from the minipool. */
4820 return (GET_CODE (rhs) == MEM
4821 || GET_CODE (rhs) == SYMBOL_REF
4822 || note_invalid_constants (insn, -1, false));
4825 /* Return TRUE if INSN is a Cirrus instruction. */
4827 arm_cirrus_insn_p (rtx insn)
4829 enum attr_cirrus attr;
4831 /* get_attr aborts on USE and CLOBBER. */
4833 || GET_CODE (insn) != INSN
4834 || GET_CODE (PATTERN (insn)) == USE
4835 || GET_CODE (PATTERN (insn)) == CLOBBER)
4838 attr = get_attr_cirrus (insn);
4840 return attr != CIRRUS_NOT;
4843 /* Cirrus reorg for invalid instruction combinations. */
4845 cirrus_reorg (rtx first)
4847 enum attr_cirrus attr;
4848 rtx body = PATTERN (first);
4852 /* Any branch must be followed by 2 non Cirrus instructions. */
4853 if (GET_CODE (first) == JUMP_INSN && GET_CODE (body) != RETURN)
4856 t = next_nonnote_insn (first);
4858 if (arm_cirrus_insn_p (t))
4861 if (arm_cirrus_insn_p (next_nonnote_insn (t)))
4865 emit_insn_after (gen_nop (), first);
4870 /* (float (blah)) is in parallel with a clobber. */
4871 if (GET_CODE (body) == PARALLEL && XVECLEN (body, 0) > 0)
4872 body = XVECEXP (body, 0, 0);
4874 if (GET_CODE (body) == SET)
4876 rtx lhs = XEXP (body, 0), rhs = XEXP (body, 1);
4878 /* cfldrd, cfldr64, cfstrd, cfstr64 must
4879 be followed by a non Cirrus insn. */
4880 if (get_attr_cirrus (first) == CIRRUS_DOUBLE)
4882 if (arm_cirrus_insn_p (next_nonnote_insn (first)))
4883 emit_insn_after (gen_nop (), first);
4887 else if (arm_memory_load_p (first))
4889 unsigned int arm_regno;
4891 /* Any ldr/cfmvdlr, ldr/cfmvdhr, ldr/cfmvsr, ldr/cfmv64lr,
4892 ldr/cfmv64hr combination where the Rd field is the same
4893 in both instructions must be split with a non Cirrus
4900 /* Get Arm register number for ldr insn. */
4901 if (GET_CODE (lhs) == REG)
4902 arm_regno = REGNO (lhs);
4903 else if (GET_CODE (rhs) == REG)
4904 arm_regno = REGNO (rhs);
4909 first = next_nonnote_insn (first);
4911 if (! arm_cirrus_insn_p (first))
4914 body = PATTERN (first);
4916 /* (float (blah)) is in parallel with a clobber. */
4917 if (GET_CODE (body) == PARALLEL && XVECLEN (body, 0))
4918 body = XVECEXP (body, 0, 0);
4920 if (GET_CODE (body) == FLOAT)
4921 body = XEXP (body, 0);
4923 if (get_attr_cirrus (first) == CIRRUS_MOVE
4924 && GET_CODE (XEXP (body, 1)) == REG
4925 && arm_regno == REGNO (XEXP (body, 1)))
4926 emit_insn_after (gen_nop (), first);
4932 /* get_attr aborts on USE and CLOBBER. */
4934 || GET_CODE (first) != INSN
4935 || GET_CODE (PATTERN (first)) == USE
4936 || GET_CODE (PATTERN (first)) == CLOBBER)
4939 attr = get_attr_cirrus (first);
4941 /* Any coprocessor compare instruction (cfcmps, cfcmpd, ...)
4942 must be followed by a non-coprocessor instruction. */
4943 if (attr == CIRRUS_COMPARE)
4947 t = next_nonnote_insn (first);
4949 if (arm_cirrus_insn_p (t))
4952 if (arm_cirrus_insn_p (next_nonnote_insn (t)))
4956 emit_insn_after (gen_nop (), first);
4962 /* Return TRUE if X references a SYMBOL_REF. */
4964 symbol_mentioned_p (rtx x)
4969 if (GET_CODE (x) == SYMBOL_REF)
4972 fmt = GET_RTX_FORMAT (GET_CODE (x));
4974 for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
4980 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
4981 if (symbol_mentioned_p (XVECEXP (x, i, j)))
4984 else if (fmt[i] == 'e' && symbol_mentioned_p (XEXP (x, i)))
4991 /* Return TRUE if X references a LABEL_REF. */
4993 label_mentioned_p (rtx x)
4998 if (GET_CODE (x) == LABEL_REF)
5001 fmt = GET_RTX_FORMAT (GET_CODE (x));
5002 for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
5008 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
5009 if (label_mentioned_p (XVECEXP (x, i, j)))
5012 else if (fmt[i] == 'e' && label_mentioned_p (XEXP (x, i)))
5022 enum rtx_code code = GET_CODE (x);
5026 else if (code == SMIN)
5028 else if (code == UMIN)
5030 else if (code == UMAX)
5036 /* Return 1 if memory locations are adjacent. */
5038 adjacent_mem_locations (rtx a, rtx b)
5040 if ((GET_CODE (XEXP (a, 0)) == REG
5041 || (GET_CODE (XEXP (a, 0)) == PLUS
5042 && GET_CODE (XEXP (XEXP (a, 0), 1)) == CONST_INT))
5043 && (GET_CODE (XEXP (b, 0)) == REG
5044 || (GET_CODE (XEXP (b, 0)) == PLUS
5045 && GET_CODE (XEXP (XEXP (b, 0), 1)) == CONST_INT)))
5047 int val0 = 0, val1 = 0;
5050 if (GET_CODE (XEXP (a, 0)) == PLUS)
5052 reg0 = REGNO (XEXP (XEXP (a, 0), 0));
5053 val0 = INTVAL (XEXP (XEXP (a, 0), 1));
5056 reg0 = REGNO (XEXP (a, 0));
5058 if (GET_CODE (XEXP (b, 0)) == PLUS)
5060 reg1 = REGNO (XEXP (XEXP (b, 0), 0));
5061 val1 = INTVAL (XEXP (XEXP (b, 0), 1));
5064 reg1 = REGNO (XEXP (b, 0));
5066 /* Don't accept any offset that will require multiple
5067 instructions to handle, since this would cause the
5068 arith_adjacentmem pattern to output an overlong sequence. */
5069 if (!const_ok_for_op (PLUS, val0) || !const_ok_for_op (PLUS, val1))
5072 return (reg0 == reg1) && ((val1 - val0) == 4 || (val0 - val1) == 4);
5078 load_multiple_sequence (rtx *operands, int nops, int *regs, int *base,
5079 HOST_WIDE_INT *load_offset)
5081 int unsorted_regs[4];
5082 HOST_WIDE_INT unsorted_offsets[4];
5087 /* Can only handle 2, 3, or 4 insns at present,
5088 though could be easily extended if required. */
5089 if (nops < 2 || nops > 4)
5092 /* Loop over the operands and check that the memory references are
5093 suitable (i.e. immediate offsets from the same base register). At
5094 the same time, extract the target register, and the memory
5096 for (i = 0; i < nops; i++)
5101 /* Convert a subreg of a mem into the mem itself. */
5102 if (GET_CODE (operands[nops + i]) == SUBREG)
5103 operands[nops + i] = alter_subreg (operands + (nops + i));
5105 if (GET_CODE (operands[nops + i]) != MEM)
5108 /* Don't reorder volatile memory references; it doesn't seem worth
5109 looking for the case where the order is ok anyway. */
5110 if (MEM_VOLATILE_P (operands[nops + i]))
5113 offset = const0_rtx;
5115 if ((GET_CODE (reg = XEXP (operands[nops + i], 0)) == REG
5116 || (GET_CODE (reg) == SUBREG
5117 && GET_CODE (reg = SUBREG_REG (reg)) == REG))
5118 || (GET_CODE (XEXP (operands[nops + i], 0)) == PLUS
5119 && ((GET_CODE (reg = XEXP (XEXP (operands[nops + i], 0), 0))
5121 || (GET_CODE (reg) == SUBREG
5122 && GET_CODE (reg = SUBREG_REG (reg)) == REG))
5123 && (GET_CODE (offset = XEXP (XEXP (operands[nops + i], 0), 1))
5128 base_reg = REGNO (reg);
5129 unsorted_regs[0] = (GET_CODE (operands[i]) == REG
5130 ? REGNO (operands[i])
5131 : REGNO (SUBREG_REG (operands[i])));
5136 if (base_reg != (int) REGNO (reg))
5137 /* Not addressed from the same base register. */
5140 unsorted_regs[i] = (GET_CODE (operands[i]) == REG
5141 ? REGNO (operands[i])
5142 : REGNO (SUBREG_REG (operands[i])));
5143 if (unsorted_regs[i] < unsorted_regs[order[0]])
5147 /* If it isn't an integer register, or if it overwrites the
5148 base register but isn't the last insn in the list, then
5149 we can't do this. */
5150 if (unsorted_regs[i] < 0 || unsorted_regs[i] > 14
5151 || (i != nops - 1 && unsorted_regs[i] == base_reg))
5154 unsorted_offsets[i] = INTVAL (offset);
5157 /* Not a suitable memory address. */
5161 /* All the useful information has now been extracted from the
5162 operands into unsorted_regs and unsorted_offsets; additionally,
5163 order[0] has been set to the lowest numbered register in the
5164 list. Sort the registers into order, and check that the memory
5165 offsets are ascending and adjacent. */
5167 for (i = 1; i < nops; i++)
5171 order[i] = order[i - 1];
5172 for (j = 0; j < nops; j++)
5173 if (unsorted_regs[j] > unsorted_regs[order[i - 1]]
5174 && (order[i] == order[i - 1]
5175 || unsorted_regs[j] < unsorted_regs[order[i]]))
5178 /* Have we found a suitable register? if not, one must be used more
5180 if (order[i] == order[i - 1])
5183 /* Is the memory address adjacent and ascending? */
5184 if (unsorted_offsets[order[i]] != unsorted_offsets[order[i - 1]] + 4)
5192 for (i = 0; i < nops; i++)
5193 regs[i] = unsorted_regs[order[i]];
5195 *load_offset = unsorted_offsets[order[0]];
5198 if (unsorted_offsets[order[0]] == 0)
5199 return 1; /* ldmia */
5201 if (unsorted_offsets[order[0]] == 4)
5202 return 2; /* ldmib */
5204 if (unsorted_offsets[order[nops - 1]] == 0)
5205 return 3; /* ldmda */
5207 if (unsorted_offsets[order[nops - 1]] == -4)
5208 return 4; /* ldmdb */
5210 /* For ARM8,9 & StrongARM, 2 ldr instructions are faster than an ldm
5211 if the offset isn't small enough. The reason 2 ldrs are faster
5212 is because these ARMs are able to do more than one cache access
5213 in a single cycle. The ARM9 and StrongARM have Harvard caches,
5214 whilst the ARM8 has a double bandwidth cache. This means that
5215 these cores can do both an instruction fetch and a data fetch in
5216 a single cycle, so the trick of calculating the address into a
5217 scratch register (one of the result regs) and then doing a load
5218 multiple actually becomes slower (and no smaller in code size).
5219 That is the transformation
5221 ldr rd1, [rbase + offset]
5222 ldr rd2, [rbase + offset + 4]
5226 add rd1, rbase, offset
5227 ldmia rd1, {rd1, rd2}
5229 produces worse code -- '3 cycles + any stalls on rd2' instead of
5230 '2 cycles + any stalls on rd2'. On ARMs with only one cache
5231 access per cycle, the first sequence could never complete in less
5232 than 6 cycles, whereas the ldm sequence would only take 5 and
5233 would make better use of sequential accesses if not hitting the
5236 We cheat here and test 'arm_ld_sched' which we currently know to
5237 only be true for the ARM8, ARM9 and StrongARM. If this ever
5238 changes, then the test below needs to be reworked. */
5239 if (nops == 2 && arm_ld_sched)
5242 /* Can't do it without setting up the offset, only do this if it takes
5243 no more than one insn. */
5244 return (const_ok_for_arm (unsorted_offsets[order[0]])
5245 || const_ok_for_arm (-unsorted_offsets[order[0]])) ? 5 : 0;
5249 emit_ldm_seq (rtx *operands, int nops)
5253 HOST_WIDE_INT offset;
5257 switch (load_multiple_sequence (operands, nops, regs, &base_reg, &offset))
5260 strcpy (buf, "ldm%?ia\t");
5264 strcpy (buf, "ldm%?ib\t");
5268 strcpy (buf, "ldm%?da\t");
5272 strcpy (buf, "ldm%?db\t");
5277 sprintf (buf, "add%%?\t%s%s, %s%s, #%ld", REGISTER_PREFIX,
5278 reg_names[regs[0]], REGISTER_PREFIX, reg_names[base_reg],
5281 sprintf (buf, "sub%%?\t%s%s, %s%s, #%ld", REGISTER_PREFIX,
5282 reg_names[regs[0]], REGISTER_PREFIX, reg_names[base_reg],
5284 output_asm_insn (buf, operands);
5286 strcpy (buf, "ldm%?ia\t");
5293 sprintf (buf + strlen (buf), "%s%s, {%s%s", REGISTER_PREFIX,
5294 reg_names[base_reg], REGISTER_PREFIX, reg_names[regs[0]]);
5296 for (i = 1; i < nops; i++)
5297 sprintf (buf + strlen (buf), ", %s%s", REGISTER_PREFIX,
5298 reg_names[regs[i]]);
5300 strcat (buf, "}\t%@ phole ldm");
5302 output_asm_insn (buf, operands);
5307 store_multiple_sequence (rtx *operands, int nops, int *regs, int *base,
5308 HOST_WIDE_INT * load_offset)
5310 int unsorted_regs[4];
5311 HOST_WIDE_INT unsorted_offsets[4];
5316 /* Can only handle 2, 3, or 4 insns at present, though could be easily
5317 extended if required. */
5318 if (nops < 2 || nops > 4)
5321 /* Loop over the operands and check that the memory references are
5322 suitable (i.e. immediate offsets from the same base register). At
5323 the same time, extract the target register, and the memory
5325 for (i = 0; i < nops; i++)
5330 /* Convert a subreg of a mem into the mem itself. */
5331 if (GET_CODE (operands[nops + i]) == SUBREG)
5332 operands[nops + i] = alter_subreg (operands + (nops + i));
5334 if (GET_CODE (operands[nops + i]) != MEM)
5337 /* Don't reorder volatile memory references; it doesn't seem worth
5338 looking for the case where the order is ok anyway. */
5339 if (MEM_VOLATILE_P (operands[nops + i]))
5342 offset = const0_rtx;
5344 if ((GET_CODE (reg = XEXP (operands[nops + i], 0)) == REG
5345 || (GET_CODE (reg) == SUBREG
5346 && GET_CODE (reg = SUBREG_REG (reg)) == REG))
5347 || (GET_CODE (XEXP (operands[nops + i], 0)) == PLUS
5348 && ((GET_CODE (reg = XEXP (XEXP (operands[nops + i], 0), 0))
5350 || (GET_CODE (reg) == SUBREG
5351 && GET_CODE (reg = SUBREG_REG (reg)) == REG))
5352 && (GET_CODE (offset = XEXP (XEXP (operands[nops + i], 0), 1))
5357 base_reg = REGNO (reg);
5358 unsorted_regs[0] = (GET_CODE (operands[i]) == REG
5359 ? REGNO (operands[i])
5360 : REGNO (SUBREG_REG (operands[i])));
5365 if (base_reg != (int) REGNO (reg))
5366 /* Not addressed from the same base register. */
5369 unsorted_regs[i] = (GET_CODE (operands[i]) == REG
5370 ? REGNO (operands[i])
5371 : REGNO (SUBREG_REG (operands[i])));
5372 if (unsorted_regs[i] < unsorted_regs[order[0]])
5376 /* If it isn't an integer register, then we can't do this. */
5377 if (unsorted_regs[i] < 0 || unsorted_regs[i] > 14)
5380 unsorted_offsets[i] = INTVAL (offset);
5383 /* Not a suitable memory address. */
5387 /* All the useful information has now been extracted from the
5388 operands into unsorted_regs and unsorted_offsets; additionally,
5389 order[0] has been set to the lowest numbered register in the
5390 list. Sort the registers into order, and check that the memory
5391 offsets are ascending and adjacent. */
5393 for (i = 1; i < nops; i++)
5397 order[i] = order[i - 1];
5398 for (j = 0; j < nops; j++)
5399 if (unsorted_regs[j] > unsorted_regs[order[i - 1]]
5400 && (order[i] == order[i - 1]
5401 || unsorted_regs[j] < unsorted_regs[order[i]]))
5404 /* Have we found a suitable register? if not, one must be used more
5406 if (order[i] == order[i - 1])
5409 /* Is the memory address adjacent and ascending? */
5410 if (unsorted_offsets[order[i]] != unsorted_offsets[order[i - 1]] + 4)
5418 for (i = 0; i < nops; i++)
5419 regs[i] = unsorted_regs[order[i]];
5421 *load_offset = unsorted_offsets[order[0]];
5424 if (unsorted_offsets[order[0]] == 0)
5425 return 1; /* stmia */
5427 if (unsorted_offsets[order[0]] == 4)
5428 return 2; /* stmib */
5430 if (unsorted_offsets[order[nops - 1]] == 0)
5431 return 3; /* stmda */
5433 if (unsorted_offsets[order[nops - 1]] == -4)
5434 return 4; /* stmdb */
5440 emit_stm_seq (rtx *operands, int nops)
5444 HOST_WIDE_INT offset;
5448 switch (store_multiple_sequence (operands, nops, regs, &base_reg, &offset))
5451 strcpy (buf, "stm%?ia\t");
5455 strcpy (buf, "stm%?ib\t");
5459 strcpy (buf, "stm%?da\t");
5463 strcpy (buf, "stm%?db\t");
5470 sprintf (buf + strlen (buf), "%s%s, {%s%s", REGISTER_PREFIX,
5471 reg_names[base_reg], REGISTER_PREFIX, reg_names[regs[0]]);
5473 for (i = 1; i < nops; i++)
5474 sprintf (buf + strlen (buf), ", %s%s", REGISTER_PREFIX,
5475 reg_names[regs[i]]);
5477 strcat (buf, "}\t%@ phole stm");
5479 output_asm_insn (buf, operands);
5484 /* Routines for use in generating RTL. */
5487 arm_gen_load_multiple (int base_regno, int count, rtx from, int up,
5488 int write_back, rtx basemem, HOST_WIDE_INT *offsetp)
5490 HOST_WIDE_INT offset = *offsetp;
5493 int sign = up ? 1 : -1;
5496 /* XScale has load-store double instructions, but they have stricter
5497 alignment requirements than load-store multiple, so we cannot
5500 For XScale ldm requires 2 + NREGS cycles to complete and blocks
5501 the pipeline until completion.
5509 An ldr instruction takes 1-3 cycles, but does not block the
5518 Best case ldr will always win. However, the more ldr instructions
5519 we issue, the less likely we are to be able to schedule them well.
5520 Using ldr instructions also increases code size.
5522 As a compromise, we use ldr for counts of 1 or 2 regs, and ldm
5523 for counts of 3 or 4 regs. */
5524 if (arm_tune_xscale && count <= 2 && ! optimize_size)
5530 for (i = 0; i < count; i++)
5532 addr = plus_constant (from, i * 4 * sign);
5533 mem = adjust_automodify_address (basemem, SImode, addr, offset);
5534 emit_move_insn (gen_rtx_REG (SImode, base_regno + i), mem);
5540 emit_move_insn (from, plus_constant (from, count * 4 * sign));
5550 result = gen_rtx_PARALLEL (VOIDmode,
5551 rtvec_alloc (count + (write_back ? 1 : 0)));
5554 XVECEXP (result, 0, 0)
5555 = gen_rtx_SET (GET_MODE (from), from,
5556 plus_constant (from, count * 4 * sign));
5561 for (j = 0; i < count; i++, j++)
5563 addr = plus_constant (from, j * 4 * sign);
5564 mem = adjust_automodify_address_nv (basemem, SImode, addr, offset);
5565 XVECEXP (result, 0, i)
5566 = gen_rtx_SET (VOIDmode, gen_rtx_REG (SImode, base_regno + j), mem);
5577 arm_gen_store_multiple (int base_regno, int count, rtx to, int up,
5578 int write_back, rtx basemem, HOST_WIDE_INT *offsetp)
5580 HOST_WIDE_INT offset = *offsetp;
5583 int sign = up ? 1 : -1;
5586 /* See arm_gen_load_multiple for discussion of
5587 the pros/cons of ldm/stm usage for XScale. */
5588 if (arm_tune_xscale && count <= 2 && ! optimize_size)
5594 for (i = 0; i < count; i++)
5596 addr = plus_constant (to, i * 4 * sign);
5597 mem = adjust_automodify_address (basemem, SImode, addr, offset);
5598 emit_move_insn (mem, gen_rtx_REG (SImode, base_regno + i));
5604 emit_move_insn (to, plus_constant (to, count * 4 * sign));
5614 result = gen_rtx_PARALLEL (VOIDmode,
5615 rtvec_alloc (count + (write_back ? 1 : 0)));
5618 XVECEXP (result, 0, 0)
5619 = gen_rtx_SET (GET_MODE (to), to,
5620 plus_constant (to, count * 4 * sign));
5625 for (j = 0; i < count; i++, j++)
5627 addr = plus_constant (to, j * 4 * sign);
5628 mem = adjust_automodify_address_nv (basemem, SImode, addr, offset);
5629 XVECEXP (result, 0, i)
5630 = gen_rtx_SET (VOIDmode, mem, gen_rtx_REG (SImode, base_regno + j));
5641 arm_gen_movmemqi (rtx *operands)
5643 HOST_WIDE_INT in_words_to_go, out_words_to_go, last_bytes;
5644 HOST_WIDE_INT srcoffset, dstoffset;
5646 rtx src, dst, srcbase, dstbase;
5647 rtx part_bytes_reg = NULL;
5650 if (GET_CODE (operands[2]) != CONST_INT
5651 || GET_CODE (operands[3]) != CONST_INT
5652 || INTVAL (operands[2]) > 64
5653 || INTVAL (operands[3]) & 3)
5656 dstbase = operands[0];
5657 srcbase = operands[1];
5659 dst = copy_to_mode_reg (SImode, XEXP (dstbase, 0));
5660 src = copy_to_mode_reg (SImode, XEXP (srcbase, 0));
5662 in_words_to_go = ARM_NUM_INTS (INTVAL (operands[2]));
5663 out_words_to_go = INTVAL (operands[2]) / 4;
5664 last_bytes = INTVAL (operands[2]) & 3;
5665 dstoffset = srcoffset = 0;
5667 if (out_words_to_go != in_words_to_go && ((in_words_to_go - 1) & 3) != 0)
5668 part_bytes_reg = gen_rtx_REG (SImode, (in_words_to_go - 1) & 3);
5670 for (i = 0; in_words_to_go >= 2; i+=4)
5672 if (in_words_to_go > 4)
5673 emit_insn (arm_gen_load_multiple (0, 4, src, TRUE, TRUE,
5674 srcbase, &srcoffset));
5676 emit_insn (arm_gen_load_multiple (0, in_words_to_go, src, TRUE,
5677 FALSE, srcbase, &srcoffset));
5679 if (out_words_to_go)
5681 if (out_words_to_go > 4)
5682 emit_insn (arm_gen_store_multiple (0, 4, dst, TRUE, TRUE,
5683 dstbase, &dstoffset));
5684 else if (out_words_to_go != 1)
5685 emit_insn (arm_gen_store_multiple (0, out_words_to_go,
5689 dstbase, &dstoffset));
5692 mem = adjust_automodify_address (dstbase, SImode, dst, dstoffset);
5693 emit_move_insn (mem, gen_rtx_REG (SImode, 0));
5694 if (last_bytes != 0)
5696 emit_insn (gen_addsi3 (dst, dst, GEN_INT (4)));
5702 in_words_to_go -= in_words_to_go < 4 ? in_words_to_go : 4;
5703 out_words_to_go -= out_words_to_go < 4 ? out_words_to_go : 4;
5706 /* OUT_WORDS_TO_GO will be zero here if there are byte stores to do. */
5707 if (out_words_to_go)
5711 mem = adjust_automodify_address (srcbase, SImode, src, srcoffset);
5712 sreg = copy_to_reg (mem);
5714 mem = adjust_automodify_address (dstbase, SImode, dst, dstoffset);
5715 emit_move_insn (mem, sreg);
5718 if (in_words_to_go) /* Sanity check */
5724 if (in_words_to_go < 0)
5727 mem = adjust_automodify_address (srcbase, SImode, src, srcoffset);
5728 part_bytes_reg = copy_to_mode_reg (SImode, mem);
5731 if (last_bytes && part_bytes_reg == NULL)
5734 if (BYTES_BIG_ENDIAN && last_bytes)
5736 rtx tmp = gen_reg_rtx (SImode);
5738 /* The bytes we want are in the top end of the word. */
5739 emit_insn (gen_lshrsi3 (tmp, part_bytes_reg,
5740 GEN_INT (8 * (4 - last_bytes))));
5741 part_bytes_reg = tmp;
5745 mem = adjust_automodify_address (dstbase, QImode,
5746 plus_constant (dst, last_bytes - 1),
5747 dstoffset + last_bytes - 1);
5748 emit_move_insn (mem, gen_lowpart (QImode, part_bytes_reg));
5752 tmp = gen_reg_rtx (SImode);
5753 emit_insn (gen_lshrsi3 (tmp, part_bytes_reg, GEN_INT (8)));
5754 part_bytes_reg = tmp;
5763 mem = adjust_automodify_address (dstbase, HImode, dst, dstoffset);
5764 emit_move_insn (mem, gen_lowpart (HImode, part_bytes_reg));
5768 rtx tmp = gen_reg_rtx (SImode);
5769 emit_insn (gen_addsi3 (dst, dst, const2_rtx));
5770 emit_insn (gen_lshrsi3 (tmp, part_bytes_reg, GEN_INT (16)));
5771 part_bytes_reg = tmp;
5778 mem = adjust_automodify_address (dstbase, QImode, dst, dstoffset);
5779 emit_move_insn (mem, gen_lowpart (QImode, part_bytes_reg));
5786 /* Generate a memory reference for a half word, such that it will be loaded
5787 into the top 16 bits of the word. We can assume that the address is
5788 known to be alignable and of the form reg, or plus (reg, const). */
5791 arm_gen_rotated_half_load (rtx memref)
5793 HOST_WIDE_INT offset = 0;
5794 rtx base = XEXP (memref, 0);
5796 if (GET_CODE (base) == PLUS)
5798 offset = INTVAL (XEXP (base, 1));
5799 base = XEXP (base, 0);
5802 /* If we aren't allowed to generate unaligned addresses, then fail. */
5803 if ((BYTES_BIG_ENDIAN ? 1 : 0) ^ ((offset & 2) == 0))
5806 base = gen_rtx_MEM (SImode, plus_constant (base, offset & ~2));
5808 if ((BYTES_BIG_ENDIAN ? 1 : 0) ^ ((offset & 2) == 2))
5811 return gen_rtx_ROTATE (SImode, base, GEN_INT (16));
5814 /* Select a dominance comparison mode if possible for a test of the general
5815 form (OP (COND_OR (X) (Y)) (const_int 0)). We support three forms.
5816 COND_OR == DOM_CC_X_AND_Y => (X && Y)
5817 COND_OR == DOM_CC_NX_OR_Y => ((! X) || Y)
5818 COND_OR == DOM_CC_X_OR_Y => (X || Y)
5819 In all cases OP will be either EQ or NE, but we don't need to know which
5820 here. If we are unable to support a dominance comparison we return
5821 CC mode. This will then fail to match for the RTL expressions that
5822 generate this call. */
5824 arm_select_dominance_cc_mode (rtx x, rtx y, HOST_WIDE_INT cond_or)
5826 enum rtx_code cond1, cond2;
5829 /* Currently we will probably get the wrong result if the individual
5830 comparisons are not simple. This also ensures that it is safe to
5831 reverse a comparison if necessary. */
5832 if ((arm_select_cc_mode (cond1 = GET_CODE (x), XEXP (x, 0), XEXP (x, 1))
5834 || (arm_select_cc_mode (cond2 = GET_CODE (y), XEXP (y, 0), XEXP (y, 1))
5838 /* The if_then_else variant of this tests the second condition if the
5839 first passes, but is true if the first fails. Reverse the first
5840 condition to get a true "inclusive-or" expression. */
5841 if (cond_or == DOM_CC_NX_OR_Y)
5842 cond1 = reverse_condition (cond1);
5844 /* If the comparisons are not equal, and one doesn't dominate the other,
5845 then we can't do this. */
5847 && !comparison_dominates_p (cond1, cond2)
5848 && (swapped = 1, !comparison_dominates_p (cond2, cond1)))
5853 enum rtx_code temp = cond1;
5861 if (cond2 == EQ || cond_or == DOM_CC_X_AND_Y)
5866 case LE: return CC_DLEmode;
5867 case LEU: return CC_DLEUmode;
5868 case GE: return CC_DGEmode;
5869 case GEU: return CC_DGEUmode;
5876 if (cond2 == LT || cond_or == DOM_CC_X_AND_Y)
5885 if (cond2 == GT || cond_or == DOM_CC_X_AND_Y)
5894 if (cond2 == LTU || cond_or == DOM_CC_X_AND_Y)
5903 if (cond2 == GTU || cond_or == DOM_CC_X_AND_Y)
5911 /* The remaining cases only occur when both comparisons are the
5936 arm_select_cc_mode (enum rtx_code op, rtx x, rtx y)
5938 /* All floating point compares return CCFP if it is an equality
5939 comparison, and CCFPE otherwise. */
5940 if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
5960 if (TARGET_HARD_FLOAT && TARGET_MAVERICK)
5969 /* A compare with a shifted operand. Because of canonicalization, the
5970 comparison will have to be swapped when we emit the assembler. */
5971 if (GET_MODE (y) == SImode && GET_CODE (y) == REG
5972 && (GET_CODE (x) == ASHIFT || GET_CODE (x) == ASHIFTRT
5973 || GET_CODE (x) == LSHIFTRT || GET_CODE (x) == ROTATE
5974 || GET_CODE (x) == ROTATERT))
5977 /* This is a special case that is used by combine to allow a
5978 comparison of a shifted byte load to be split into a zero-extend
5979 followed by a comparison of the shifted integer (only valid for
5980 equalities and unsigned inequalities). */
5981 if (GET_MODE (x) == SImode
5982 && GET_CODE (x) == ASHIFT
5983 && GET_CODE (XEXP (x, 1)) == CONST_INT && INTVAL (XEXP (x, 1)) == 24
5984 && GET_CODE (XEXP (x, 0)) == SUBREG
5985 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == MEM
5986 && GET_MODE (SUBREG_REG (XEXP (x, 0))) == QImode
5987 && (op == EQ || op == NE
5988 || op == GEU || op == GTU || op == LTU || op == LEU)
5989 && GET_CODE (y) == CONST_INT)
5992 /* A construct for a conditional compare, if the false arm contains
5993 0, then both conditions must be true, otherwise either condition
5994 must be true. Not all conditions are possible, so CCmode is
5995 returned if it can't be done. */
5996 if (GET_CODE (x) == IF_THEN_ELSE
5997 && (XEXP (x, 2) == const0_rtx
5998 || XEXP (x, 2) == const1_rtx)
5999 && COMPARISON_P (XEXP (x, 0))
6000 && COMPARISON_P (XEXP (x, 1)))
6001 return arm_select_dominance_cc_mode (XEXP (x, 0), XEXP (x, 1),
6002 INTVAL (XEXP (x, 2)));
6004 /* Alternate canonicalizations of the above. These are somewhat cleaner. */
6005 if (GET_CODE (x) == AND
6006 && COMPARISON_P (XEXP (x, 0))
6007 && COMPARISON_P (XEXP (x, 1)))
6008 return arm_select_dominance_cc_mode (XEXP (x, 0), XEXP (x, 1),
6011 if (GET_CODE (x) == IOR
6012 && COMPARISON_P (XEXP (x, 0))
6013 && COMPARISON_P (XEXP (x, 1)))
6014 return arm_select_dominance_cc_mode (XEXP (x, 0), XEXP (x, 1),
6017 /* An operation (on Thumb) where we want to test for a single bit.
6018 This is done by shifting that bit up into the top bit of a
6019 scratch register; we can then branch on the sign bit. */
6021 && GET_MODE (x) == SImode
6022 && (op == EQ || op == NE)
6023 && (GET_CODE (x) == ZERO_EXTRACT))
6026 /* An operation that sets the condition codes as a side-effect, the
6027 V flag is not set correctly, so we can only use comparisons where
6028 this doesn't matter. (For LT and GE we can use "mi" and "pl"
6030 if (GET_MODE (x) == SImode
6032 && (op == EQ || op == NE || op == LT || op == GE)
6033 && (GET_CODE (x) == PLUS || GET_CODE (x) == MINUS
6034 || GET_CODE (x) == AND || GET_CODE (x) == IOR
6035 || GET_CODE (x) == XOR || GET_CODE (x) == MULT
6036 || GET_CODE (x) == NOT || GET_CODE (x) == NEG
6037 || GET_CODE (x) == LSHIFTRT
6038 || GET_CODE (x) == ASHIFT || GET_CODE (x) == ASHIFTRT
6039 || GET_CODE (x) == ROTATERT
6040 || (TARGET_ARM && GET_CODE (x) == ZERO_EXTRACT)))
6043 if (GET_MODE (x) == QImode && (op == EQ || op == NE))
6046 if (GET_MODE (x) == SImode && (op == LTU || op == GEU)
6047 && GET_CODE (x) == PLUS
6048 && (rtx_equal_p (XEXP (x, 0), y) || rtx_equal_p (XEXP (x, 1), y)))
6054 /* X and Y are two things to compare using CODE. Emit the compare insn and
6055 return the rtx for register 0 in the proper mode. FP means this is a
6056 floating point compare: I don't think that it is needed on the arm. */
6058 arm_gen_compare_reg (enum rtx_code code, rtx x, rtx y)
6060 enum machine_mode mode = SELECT_CC_MODE (code, x, y);
6061 rtx cc_reg = gen_rtx_REG (mode, CC_REGNUM);
6063 emit_insn (gen_rtx_SET (VOIDmode, cc_reg,
6064 gen_rtx_COMPARE (mode, x, y)));
6069 /* Generate a sequence of insns that will generate the correct return
6070 address mask depending on the physical architecture that the program
6073 arm_gen_return_addr_mask (void)
6075 rtx reg = gen_reg_rtx (Pmode);
6077 emit_insn (gen_return_addr_mask (reg));
6082 arm_reload_in_hi (rtx *operands)
6084 rtx ref = operands[1];
6086 HOST_WIDE_INT offset = 0;
6088 if (GET_CODE (ref) == SUBREG)
6090 offset = SUBREG_BYTE (ref);
6091 ref = SUBREG_REG (ref);
6094 if (GET_CODE (ref) == REG)
6096 /* We have a pseudo which has been spilt onto the stack; there
6097 are two cases here: the first where there is a simple
6098 stack-slot replacement and a second where the stack-slot is
6099 out of range, or is used as a subreg. */
6100 if (reg_equiv_mem[REGNO (ref)])
6102 ref = reg_equiv_mem[REGNO (ref)];
6103 base = find_replacement (&XEXP (ref, 0));
6106 /* The slot is out of range, or was dressed up in a SUBREG. */
6107 base = reg_equiv_address[REGNO (ref)];
6110 base = find_replacement (&XEXP (ref, 0));
6112 /* Handle the case where the address is too complex to be offset by 1. */
6113 if (GET_CODE (base) == MINUS
6114 || (GET_CODE (base) == PLUS && GET_CODE (XEXP (base, 1)) != CONST_INT))
6116 rtx base_plus = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
6118 emit_insn (gen_rtx_SET (VOIDmode, base_plus, base));
6121 else if (GET_CODE (base) == PLUS)
6123 /* The addend must be CONST_INT, or we would have dealt with it above. */
6124 HOST_WIDE_INT hi, lo;
6126 offset += INTVAL (XEXP (base, 1));
6127 base = XEXP (base, 0);
6129 /* Rework the address into a legal sequence of insns. */
6130 /* Valid range for lo is -4095 -> 4095 */
6133 : -((-offset) & 0xfff));
6135 /* Corner case, if lo is the max offset then we would be out of range
6136 once we have added the additional 1 below, so bump the msb into the
6137 pre-loading insn(s). */
6141 hi = ((((offset - lo) & (HOST_WIDE_INT) 0xffffffff)
6142 ^ (HOST_WIDE_INT) 0x80000000)
6143 - (HOST_WIDE_INT) 0x80000000);
6145 if (hi + lo != offset)
6150 rtx base_plus = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
6152 /* Get the base address; addsi3 knows how to handle constants
6153 that require more than one insn. */
6154 emit_insn (gen_addsi3 (base_plus, base, GEN_INT (hi)));
6160 /* Operands[2] may overlap operands[0] (though it won't overlap
6161 operands[1]), that's why we asked for a DImode reg -- so we can
6162 use the bit that does not overlap. */
6163 if (REGNO (operands[2]) == REGNO (operands[0]))
6164 scratch = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
6166 scratch = gen_rtx_REG (SImode, REGNO (operands[2]));
6168 emit_insn (gen_zero_extendqisi2 (scratch,
6169 gen_rtx_MEM (QImode,
6170 plus_constant (base,
6172 emit_insn (gen_zero_extendqisi2 (gen_rtx_SUBREG (SImode, operands[0], 0),
6173 gen_rtx_MEM (QImode,
6174 plus_constant (base,
6176 if (!BYTES_BIG_ENDIAN)
6177 emit_insn (gen_rtx_SET (VOIDmode, gen_rtx_SUBREG (SImode, operands[0], 0),
6178 gen_rtx_IOR (SImode,
6181 gen_rtx_SUBREG (SImode, operands[0], 0),
6185 emit_insn (gen_rtx_SET (VOIDmode, gen_rtx_SUBREG (SImode, operands[0], 0),
6186 gen_rtx_IOR (SImode,
6187 gen_rtx_ASHIFT (SImode, scratch,
6189 gen_rtx_SUBREG (SImode, operands[0],
6193 /* Handle storing a half-word to memory during reload by synthesizing as two
6194 byte stores. Take care not to clobber the input values until after we
6195 have moved them somewhere safe. This code assumes that if the DImode
6196 scratch in operands[2] overlaps either the input value or output address
6197 in some way, then that value must die in this insn (we absolutely need
6198 two scratch registers for some corner cases). */
6200 arm_reload_out_hi (rtx *operands)
6202 rtx ref = operands[0];
6203 rtx outval = operands[1];
6205 HOST_WIDE_INT offset = 0;
6207 if (GET_CODE (ref) == SUBREG)
6209 offset = SUBREG_BYTE (ref);
6210 ref = SUBREG_REG (ref);
6213 if (GET_CODE (ref) == REG)
6215 /* We have a pseudo which has been spilt onto the stack; there
6216 are two cases here: the first where there is a simple
6217 stack-slot replacement and a second where the stack-slot is
6218 out of range, or is used as a subreg. */
6219 if (reg_equiv_mem[REGNO (ref)])
6221 ref = reg_equiv_mem[REGNO (ref)];
6222 base = find_replacement (&XEXP (ref, 0));
6225 /* The slot is out of range, or was dressed up in a SUBREG. */
6226 base = reg_equiv_address[REGNO (ref)];
6229 base = find_replacement (&XEXP (ref, 0));
6231 scratch = gen_rtx_REG (SImode, REGNO (operands[2]));
6233 /* Handle the case where the address is too complex to be offset by 1. */
6234 if (GET_CODE (base) == MINUS
6235 || (GET_CODE (base) == PLUS && GET_CODE (XEXP (base, 1)) != CONST_INT))
6237 rtx base_plus = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
6239 /* Be careful not to destroy OUTVAL. */
6240 if (reg_overlap_mentioned_p (base_plus, outval))
6242 /* Updating base_plus might destroy outval, see if we can
6243 swap the scratch and base_plus. */
6244 if (!reg_overlap_mentioned_p (scratch, outval))
6247 scratch = base_plus;
6252 rtx scratch_hi = gen_rtx_REG (HImode, REGNO (operands[2]));
6254 /* Be conservative and copy OUTVAL into the scratch now,
6255 this should only be necessary if outval is a subreg
6256 of something larger than a word. */
6257 /* XXX Might this clobber base? I can't see how it can,
6258 since scratch is known to overlap with OUTVAL, and
6259 must be wider than a word. */
6260 emit_insn (gen_movhi (scratch_hi, outval));
6261 outval = scratch_hi;
6265 emit_insn (gen_rtx_SET (VOIDmode, base_plus, base));
6268 else if (GET_CODE (base) == PLUS)
6270 /* The addend must be CONST_INT, or we would have dealt with it above. */
6271 HOST_WIDE_INT hi, lo;
6273 offset += INTVAL (XEXP (base, 1));
6274 base = XEXP (base, 0);
6276 /* Rework the address into a legal sequence of insns. */
6277 /* Valid range for lo is -4095 -> 4095 */
6280 : -((-offset) & 0xfff));
6282 /* Corner case, if lo is the max offset then we would be out of range
6283 once we have added the additional 1 below, so bump the msb into the
6284 pre-loading insn(s). */
6288 hi = ((((offset - lo) & (HOST_WIDE_INT) 0xffffffff)
6289 ^ (HOST_WIDE_INT) 0x80000000)
6290 - (HOST_WIDE_INT) 0x80000000);
6292 if (hi + lo != offset)
6297 rtx base_plus = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
6299 /* Be careful not to destroy OUTVAL. */
6300 if (reg_overlap_mentioned_p (base_plus, outval))
6302 /* Updating base_plus might destroy outval, see if we
6303 can swap the scratch and base_plus. */
6304 if (!reg_overlap_mentioned_p (scratch, outval))
6307 scratch = base_plus;
6312 rtx scratch_hi = gen_rtx_REG (HImode, REGNO (operands[2]));
6314 /* Be conservative and copy outval into scratch now,
6315 this should only be necessary if outval is a
6316 subreg of something larger than a word. */
6317 /* XXX Might this clobber base? I can't see how it
6318 can, since scratch is known to overlap with
6320 emit_insn (gen_movhi (scratch_hi, outval));
6321 outval = scratch_hi;
6325 /* Get the base address; addsi3 knows how to handle constants
6326 that require more than one insn. */
6327 emit_insn (gen_addsi3 (base_plus, base, GEN_INT (hi)));
6333 if (BYTES_BIG_ENDIAN)
6335 emit_insn (gen_movqi (gen_rtx_MEM (QImode,
6336 plus_constant (base, offset + 1)),
6337 gen_lowpart (QImode, outval)));
6338 emit_insn (gen_lshrsi3 (scratch,
6339 gen_rtx_SUBREG (SImode, outval, 0),
6341 emit_insn (gen_movqi (gen_rtx_MEM (QImode, plus_constant (base, offset)),
6342 gen_lowpart (QImode, scratch)));
6346 emit_insn (gen_movqi (gen_rtx_MEM (QImode, plus_constant (base, offset)),
6347 gen_lowpart (QImode, outval)));
6348 emit_insn (gen_lshrsi3 (scratch,
6349 gen_rtx_SUBREG (SImode, outval, 0),
6351 emit_insn (gen_movqi (gen_rtx_MEM (QImode,
6352 plus_constant (base, offset + 1)),
6353 gen_lowpart (QImode, scratch)));
6357 /* Print a symbolic form of X to the debug file, F. */
6359 arm_print_value (FILE *f, rtx x)
6361 switch (GET_CODE (x))
6364 fprintf (f, HOST_WIDE_INT_PRINT_HEX, INTVAL (x));
6368 fprintf (f, "<0x%lx,0x%lx>", (long)XWINT (x, 2), (long)XWINT (x, 3));
6376 for (i = 0; i < CONST_VECTOR_NUNITS (x); i++)
6378 fprintf (f, HOST_WIDE_INT_PRINT_HEX, INTVAL (CONST_VECTOR_ELT (x, i)));
6379 if (i < (CONST_VECTOR_NUNITS (x) - 1))
6387 fprintf (f, "\"%s\"", XSTR (x, 0));
6391 fprintf (f, "`%s'", XSTR (x, 0));
6395 fprintf (f, "L%d", INSN_UID (XEXP (x, 0)));
6399 arm_print_value (f, XEXP (x, 0));
6403 arm_print_value (f, XEXP (x, 0));
6405 arm_print_value (f, XEXP (x, 1));
6413 fprintf (f, "????");
6418 /* Routines for manipulation of the constant pool. */
6420 /* Arm instructions cannot load a large constant directly into a
6421 register; they have to come from a pc relative load. The constant
6422 must therefore be placed in the addressable range of the pc
6423 relative load. Depending on the precise pc relative load
6424 instruction the range is somewhere between 256 bytes and 4k. This
6425 means that we often have to dump a constant inside a function, and
6426 generate code to branch around it.
6428 It is important to minimize this, since the branches will slow
6429 things down and make the code larger.
6431 Normally we can hide the table after an existing unconditional
6432 branch so that there is no interruption of the flow, but in the
6433 worst case the code looks like this:
6451 We fix this by performing a scan after scheduling, which notices
6452 which instructions need to have their operands fetched from the
6453 constant table and builds the table.
6455 The algorithm starts by building a table of all the constants that
6456 need fixing up and all the natural barriers in the function (places
6457 where a constant table can be dropped without breaking the flow).
6458 For each fixup we note how far the pc-relative replacement will be
6459 able to reach and the offset of the instruction into the function.
6461 Having built the table we then group the fixes together to form
6462 tables that are as large as possible (subject to addressing
6463 constraints) and emit each table of constants after the last
6464 barrier that is within range of all the instructions in the group.
6465 If a group does not contain a barrier, then we forcibly create one
6466 by inserting a jump instruction into the flow. Once the table has
6467 been inserted, the insns are then modified to reference the
6468 relevant entry in the pool.
6470 Possible enhancements to the algorithm (not implemented) are:
6472 1) For some processors and object formats, there may be benefit in
6473 aligning the pools to the start of cache lines; this alignment
6474 would need to be taken into account when calculating addressability
6477 /* These typedefs are located at the start of this file, so that
6478 they can be used in the prototypes there. This comment is to
6479 remind readers of that fact so that the following structures
6480 can be understood more easily.
6482 typedef struct minipool_node Mnode;
6483 typedef struct minipool_fixup Mfix; */
6485 struct minipool_node
6487 /* Doubly linked chain of entries. */
6490 /* The maximum offset into the code that this entry can be placed. While
6491 pushing fixes for forward references, all entries are sorted in order
6492 of increasing max_address. */
6493 HOST_WIDE_INT max_address;
6494 /* Similarly for an entry inserted for a backwards ref. */
6495 HOST_WIDE_INT min_address;
6496 /* The number of fixes referencing this entry. This can become zero
6497 if we "unpush" an entry. In this case we ignore the entry when we
6498 come to emit the code. */
6500 /* The offset from the start of the minipool. */
6501 HOST_WIDE_INT offset;
6502 /* The value in table. */
6504 /* The mode of value. */
6505 enum machine_mode mode;
6506 /* The size of the value. With iWMMXt enabled
6507 sizes > 4 also imply an alignment of 8-bytes. */
6511 struct minipool_fixup
6515 HOST_WIDE_INT address;
6517 enum machine_mode mode;
6521 HOST_WIDE_INT forwards;
6522 HOST_WIDE_INT backwards;
6525 /* Fixes less than a word need padding out to a word boundary. */
6526 #define MINIPOOL_FIX_SIZE(mode) \
6527 (GET_MODE_SIZE ((mode)) >= 4 ? GET_MODE_SIZE ((mode)) : 4)
6529 static Mnode * minipool_vector_head;
6530 static Mnode * minipool_vector_tail;
6531 static rtx minipool_vector_label;
6533 /* The linked list of all minipool fixes required for this function. */
6534 Mfix * minipool_fix_head;
6535 Mfix * minipool_fix_tail;
6536 /* The fix entry for the current minipool, once it has been placed. */
6537 Mfix * minipool_barrier;
6539 /* Determines if INSN is the start of a jump table. Returns the end
6540 of the TABLE or NULL_RTX. */
6542 is_jump_table (rtx insn)
6546 if (GET_CODE (insn) == JUMP_INSN
6547 && JUMP_LABEL (insn) != NULL
6548 && ((table = next_real_insn (JUMP_LABEL (insn)))
6549 == next_real_insn (insn))
6551 && GET_CODE (table) == JUMP_INSN
6552 && (GET_CODE (PATTERN (table)) == ADDR_VEC
6553 || GET_CODE (PATTERN (table)) == ADDR_DIFF_VEC))
6559 #ifndef JUMP_TABLES_IN_TEXT_SECTION
6560 #define JUMP_TABLES_IN_TEXT_SECTION 0
6563 static HOST_WIDE_INT
6564 get_jump_table_size (rtx insn)
6566 /* ADDR_VECs only take room if read-only data does into the text
6568 if (JUMP_TABLES_IN_TEXT_SECTION
6569 #if !defined(READONLY_DATA_SECTION) && !defined(READONLY_DATA_SECTION_ASM_OP)
6574 rtx body = PATTERN (insn);
6575 int elt = GET_CODE (body) == ADDR_DIFF_VEC ? 1 : 0;
6577 return GET_MODE_SIZE (GET_MODE (body)) * XVECLEN (body, elt);
6583 /* Move a minipool fix MP from its current location to before MAX_MP.
6584 If MAX_MP is NULL, then MP doesn't need moving, but the addressing
6585 constraints may need updating. */
6587 move_minipool_fix_forward_ref (Mnode *mp, Mnode *max_mp,
6588 HOST_WIDE_INT max_address)
6590 /* This should never be true and the code below assumes these are
6597 if (max_address < mp->max_address)
6598 mp->max_address = max_address;
6602 if (max_address > max_mp->max_address - mp->fix_size)
6603 mp->max_address = max_mp->max_address - mp->fix_size;
6605 mp->max_address = max_address;
6607 /* Unlink MP from its current position. Since max_mp is non-null,
6608 mp->prev must be non-null. */
6609 mp->prev->next = mp->next;
6610 if (mp->next != NULL)
6611 mp->next->prev = mp->prev;
6613 minipool_vector_tail = mp->prev;
6615 /* Re-insert it before MAX_MP. */
6617 mp->prev = max_mp->prev;
6620 if (mp->prev != NULL)
6621 mp->prev->next = mp;
6623 minipool_vector_head = mp;
6626 /* Save the new entry. */
6629 /* Scan over the preceding entries and adjust their addresses as
6631 while (mp->prev != NULL
6632 && mp->prev->max_address > mp->max_address - mp->prev->fix_size)
6634 mp->prev->max_address = mp->max_address - mp->prev->fix_size;
6641 /* Add a constant to the minipool for a forward reference. Returns the
6642 node added or NULL if the constant will not fit in this pool. */
6644 add_minipool_forward_ref (Mfix *fix)
6646 /* If set, max_mp is the first pool_entry that has a lower
6647 constraint than the one we are trying to add. */
6648 Mnode * max_mp = NULL;
6649 HOST_WIDE_INT max_address = fix->address + fix->forwards;
6652 /* If this fix's address is greater than the address of the first
6653 entry, then we can't put the fix in this pool. We subtract the
6654 size of the current fix to ensure that if the table is fully
6655 packed we still have enough room to insert this value by suffling
6656 the other fixes forwards. */
6657 if (minipool_vector_head &&
6658 fix->address >= minipool_vector_head->max_address - fix->fix_size)
6661 /* Scan the pool to see if a constant with the same value has
6662 already been added. While we are doing this, also note the
6663 location where we must insert the constant if it doesn't already
6665 for (mp = minipool_vector_head; mp != NULL; mp = mp->next)
6667 if (GET_CODE (fix->value) == GET_CODE (mp->value)
6668 && fix->mode == mp->mode
6669 && (GET_CODE (fix->value) != CODE_LABEL
6670 || (CODE_LABEL_NUMBER (fix->value)
6671 == CODE_LABEL_NUMBER (mp->value)))
6672 && rtx_equal_p (fix->value, mp->value))
6674 /* More than one fix references this entry. */
6676 return move_minipool_fix_forward_ref (mp, max_mp, max_address);
6679 /* Note the insertion point if necessary. */
6681 && mp->max_address > max_address)
6684 /* If we are inserting an 8-bytes aligned quantity and
6685 we have not already found an insertion point, then
6686 make sure that all such 8-byte aligned quantities are
6687 placed at the start of the pool. */
6688 if (ARM_DOUBLEWORD_ALIGN
6690 && fix->fix_size == 8
6691 && mp->fix_size != 8)
6694 max_address = mp->max_address;
6698 /* The value is not currently in the minipool, so we need to create
6699 a new entry for it. If MAX_MP is NULL, the entry will be put on
6700 the end of the list since the placement is less constrained than
6701 any existing entry. Otherwise, we insert the new fix before
6702 MAX_MP and, if necessary, adjust the constraints on the other
6704 mp = xmalloc (sizeof (* mp));
6705 mp->fix_size = fix->fix_size;
6706 mp->mode = fix->mode;
6707 mp->value = fix->value;
6709 /* Not yet required for a backwards ref. */
6710 mp->min_address = -65536;
6714 mp->max_address = max_address;
6716 mp->prev = minipool_vector_tail;
6718 if (mp->prev == NULL)
6720 minipool_vector_head = mp;
6721 minipool_vector_label = gen_label_rtx ();
6724 mp->prev->next = mp;
6726 minipool_vector_tail = mp;
6730 if (max_address > max_mp->max_address - mp->fix_size)
6731 mp->max_address = max_mp->max_address - mp->fix_size;
6733 mp->max_address = max_address;
6736 mp->prev = max_mp->prev;
6738 if (mp->prev != NULL)
6739 mp->prev->next = mp;
6741 minipool_vector_head = mp;
6744 /* Save the new entry. */
6747 /* Scan over the preceding entries and adjust their addresses as
6749 while (mp->prev != NULL
6750 && mp->prev->max_address > mp->max_address - mp->prev->fix_size)
6752 mp->prev->max_address = mp->max_address - mp->prev->fix_size;
6760 move_minipool_fix_backward_ref (Mnode *mp, Mnode *min_mp,
6761 HOST_WIDE_INT min_address)
6763 HOST_WIDE_INT offset;
6765 /* This should never be true, and the code below assumes these are
6772 if (min_address > mp->min_address)
6773 mp->min_address = min_address;
6777 /* We will adjust this below if it is too loose. */
6778 mp->min_address = min_address;
6780 /* Unlink MP from its current position. Since min_mp is non-null,
6781 mp->next must be non-null. */
6782 mp->next->prev = mp->prev;
6783 if (mp->prev != NULL)
6784 mp->prev->next = mp->next;
6786 minipool_vector_head = mp->next;
6788 /* Reinsert it after MIN_MP. */
6790 mp->next = min_mp->next;
6792 if (mp->next != NULL)
6793 mp->next->prev = mp;
6795 minipool_vector_tail = mp;
6801 for (mp = minipool_vector_head; mp != NULL; mp = mp->next)
6803 mp->offset = offset;
6804 if (mp->refcount > 0)
6805 offset += mp->fix_size;
6807 if (mp->next && mp->next->min_address < mp->min_address + mp->fix_size)
6808 mp->next->min_address = mp->min_address + mp->fix_size;
6814 /* Add a constant to the minipool for a backward reference. Returns the
6815 node added or NULL if the constant will not fit in this pool.
6817 Note that the code for insertion for a backwards reference can be
6818 somewhat confusing because the calculated offsets for each fix do
6819 not take into account the size of the pool (which is still under
6822 add_minipool_backward_ref (Mfix *fix)
6824 /* If set, min_mp is the last pool_entry that has a lower constraint
6825 than the one we are trying to add. */
6826 Mnode *min_mp = NULL;
6827 /* This can be negative, since it is only a constraint. */
6828 HOST_WIDE_INT min_address = fix->address - fix->backwards;
6831 /* If we can't reach the current pool from this insn, or if we can't
6832 insert this entry at the end of the pool without pushing other
6833 fixes out of range, then we don't try. This ensures that we
6834 can't fail later on. */
6835 if (min_address >= minipool_barrier->address
6836 || (minipool_vector_tail->min_address + fix->fix_size
6837 >= minipool_barrier->address))
6840 /* Scan the pool to see if a constant with the same value has
6841 already been added. While we are doing this, also note the
6842 location where we must insert the constant if it doesn't already
6844 for (mp = minipool_vector_tail; mp != NULL; mp = mp->prev)
6846 if (GET_CODE (fix->value) == GET_CODE (mp->value)
6847 && fix->mode == mp->mode
6848 && (GET_CODE (fix->value) != CODE_LABEL
6849 || (CODE_LABEL_NUMBER (fix->value)
6850 == CODE_LABEL_NUMBER (mp->value)))
6851 && rtx_equal_p (fix->value, mp->value)
6852 /* Check that there is enough slack to move this entry to the
6853 end of the table (this is conservative). */
6855 > (minipool_barrier->address
6856 + minipool_vector_tail->offset
6857 + minipool_vector_tail->fix_size)))
6860 return move_minipool_fix_backward_ref (mp, min_mp, min_address);
6864 mp->min_address += fix->fix_size;
6867 /* Note the insertion point if necessary. */
6868 if (mp->min_address < min_address)
6870 /* For now, we do not allow the insertion of 8-byte alignment
6871 requiring nodes anywhere but at the start of the pool. */
6872 if (ARM_DOUBLEWORD_ALIGN
6873 && fix->fix_size == 8 && mp->fix_size != 8)
6878 else if (mp->max_address
6879 < minipool_barrier->address + mp->offset + fix->fix_size)
6881 /* Inserting before this entry would push the fix beyond
6882 its maximum address (which can happen if we have
6883 re-located a forwards fix); force the new fix to come
6886 min_address = mp->min_address + fix->fix_size;
6888 /* If we are inserting an 8-bytes aligned quantity and
6889 we have not already found an insertion point, then
6890 make sure that all such 8-byte aligned quantities are
6891 placed at the start of the pool. */
6892 else if (ARM_DOUBLEWORD_ALIGN
6894 && fix->fix_size == 8
6895 && mp->fix_size < 8)
6898 min_address = mp->min_address + fix->fix_size;
6903 /* We need to create a new entry. */
6904 mp = xmalloc (sizeof (* mp));
6905 mp->fix_size = fix->fix_size;
6906 mp->mode = fix->mode;
6907 mp->value = fix->value;
6909 mp->max_address = minipool_barrier->address + 65536;
6911 mp->min_address = min_address;
6916 mp->next = minipool_vector_head;
6918 if (mp->next == NULL)
6920 minipool_vector_tail = mp;
6921 minipool_vector_label = gen_label_rtx ();
6924 mp->next->prev = mp;
6926 minipool_vector_head = mp;
6930 mp->next = min_mp->next;
6934 if (mp->next != NULL)
6935 mp->next->prev = mp;
6937 minipool_vector_tail = mp;
6940 /* Save the new entry. */
6948 /* Scan over the following entries and adjust their offsets. */
6949 while (mp->next != NULL)
6951 if (mp->next->min_address < mp->min_address + mp->fix_size)
6952 mp->next->min_address = mp->min_address + mp->fix_size;
6955 mp->next->offset = mp->offset + mp->fix_size;
6957 mp->next->offset = mp->offset;
6966 assign_minipool_offsets (Mfix *barrier)
6968 HOST_WIDE_INT offset = 0;
6971 minipool_barrier = barrier;
6973 for (mp = minipool_vector_head; mp != NULL; mp = mp->next)
6975 mp->offset = offset;
6977 if (mp->refcount > 0)
6978 offset += mp->fix_size;
6982 /* Output the literal table */
6984 dump_minipool (rtx scan)
6990 if (ARM_DOUBLEWORD_ALIGN)
6991 for (mp = minipool_vector_head; mp != NULL; mp = mp->next)
6992 if (mp->refcount > 0 && mp->fix_size == 8)
7000 ";; Emitting minipool after insn %u; address %ld; align %d (bytes)\n",
7001 INSN_UID (scan), (unsigned long) minipool_barrier->address, align64 ? 8 : 4);
7003 scan = emit_label_after (gen_label_rtx (), scan);
7004 scan = emit_insn_after (align64 ? gen_align_8 () : gen_align_4 (), scan);
7005 scan = emit_label_after (minipool_vector_label, scan);
7007 for (mp = minipool_vector_head; mp != NULL; mp = nmp)
7009 if (mp->refcount > 0)
7014 ";; Offset %u, min %ld, max %ld ",
7015 (unsigned) mp->offset, (unsigned long) mp->min_address,
7016 (unsigned long) mp->max_address);
7017 arm_print_value (dump_file, mp->value);
7018 fputc ('\n', dump_file);
7021 switch (mp->fix_size)
7023 #ifdef HAVE_consttable_1
7025 scan = emit_insn_after (gen_consttable_1 (mp->value), scan);
7029 #ifdef HAVE_consttable_2
7031 scan = emit_insn_after (gen_consttable_2 (mp->value), scan);
7035 #ifdef HAVE_consttable_4
7037 scan = emit_insn_after (gen_consttable_4 (mp->value), scan);
7041 #ifdef HAVE_consttable_8
7043 scan = emit_insn_after (gen_consttable_8 (mp->value), scan);
7057 minipool_vector_head = minipool_vector_tail = NULL;
7058 scan = emit_insn_after (gen_consttable_end (), scan);
7059 scan = emit_barrier_after (scan);
7062 /* Return the cost of forcibly inserting a barrier after INSN. */
7064 arm_barrier_cost (rtx insn)
7066 /* Basing the location of the pool on the loop depth is preferable,
7067 but at the moment, the basic block information seems to be
7068 corrupt by this stage of the compilation. */
7070 rtx next = next_nonnote_insn (insn);
7072 if (next != NULL && GET_CODE (next) == CODE_LABEL)
7075 switch (GET_CODE (insn))
7078 /* It will always be better to place the table before the label, rather
7087 return base_cost - 10;
7090 return base_cost + 10;
7094 /* Find the best place in the insn stream in the range
7095 (FIX->address,MAX_ADDRESS) to forcibly insert a minipool barrier.
7096 Create the barrier by inserting a jump and add a new fix entry for
7099 create_fix_barrier (Mfix *fix, HOST_WIDE_INT max_address)
7101 HOST_WIDE_INT count = 0;
7103 rtx from = fix->insn;
7104 rtx selected = from;
7106 HOST_WIDE_INT selected_address;
7108 HOST_WIDE_INT max_count = max_address - fix->address;
7109 rtx label = gen_label_rtx ();
7111 selected_cost = arm_barrier_cost (from);
7112 selected_address = fix->address;
7114 while (from && count < max_count)
7119 /* This code shouldn't have been called if there was a natural barrier
7121 if (GET_CODE (from) == BARRIER)
7124 /* Count the length of this insn. */
7125 count += get_attr_length (from);
7127 /* If there is a jump table, add its length. */
7128 tmp = is_jump_table (from);
7131 count += get_jump_table_size (tmp);
7133 /* Jump tables aren't in a basic block, so base the cost on
7134 the dispatch insn. If we select this location, we will
7135 still put the pool after the table. */
7136 new_cost = arm_barrier_cost (from);
7138 if (count < max_count && new_cost <= selected_cost)
7141 selected_cost = new_cost;
7142 selected_address = fix->address + count;
7145 /* Continue after the dispatch table. */
7146 from = NEXT_INSN (tmp);
7150 new_cost = arm_barrier_cost (from);
7152 if (count < max_count && new_cost <= selected_cost)
7155 selected_cost = new_cost;
7156 selected_address = fix->address + count;
7159 from = NEXT_INSN (from);
7162 /* Create a new JUMP_INSN that branches around a barrier. */
7163 from = emit_jump_insn_after (gen_jump (label), selected);
7164 JUMP_LABEL (from) = label;
7165 barrier = emit_barrier_after (from);
7166 emit_label_after (label, barrier);
7168 /* Create a minipool barrier entry for the new barrier. */
7169 new_fix = (Mfix *) obstack_alloc (&minipool_obstack, sizeof (* new_fix));
7170 new_fix->insn = barrier;
7171 new_fix->address = selected_address;
7172 new_fix->next = fix->next;
7173 fix->next = new_fix;
7178 /* Record that there is a natural barrier in the insn stream at
7181 push_minipool_barrier (rtx insn, HOST_WIDE_INT address)
7183 Mfix * fix = (Mfix *) obstack_alloc (&minipool_obstack, sizeof (* fix));
7186 fix->address = address;
7189 if (minipool_fix_head != NULL)
7190 minipool_fix_tail->next = fix;
7192 minipool_fix_head = fix;
7194 minipool_fix_tail = fix;
7197 /* Record INSN, which will need fixing up to load a value from the
7198 minipool. ADDRESS is the offset of the insn since the start of the
7199 function; LOC is a pointer to the part of the insn which requires
7200 fixing; VALUE is the constant that must be loaded, which is of type
7203 push_minipool_fix (rtx insn, HOST_WIDE_INT address, rtx *loc,
7204 enum machine_mode mode, rtx value)
7206 Mfix * fix = (Mfix *) obstack_alloc (&minipool_obstack, sizeof (* fix));
7208 #ifdef AOF_ASSEMBLER
7209 /* PIC symbol references need to be converted into offsets into the
7211 /* XXX This shouldn't be done here. */
7212 if (flag_pic && GET_CODE (value) == SYMBOL_REF)
7213 value = aof_pic_entry (value);
7214 #endif /* AOF_ASSEMBLER */
7217 fix->address = address;
7220 fix->fix_size = MINIPOOL_FIX_SIZE (mode);
7222 fix->forwards = get_attr_pool_range (insn);
7223 fix->backwards = get_attr_neg_pool_range (insn);
7224 fix->minipool = NULL;
7226 /* If an insn doesn't have a range defined for it, then it isn't
7227 expecting to be reworked by this code. Better to abort now than
7228 to generate duff assembly code. */
7229 if (fix->forwards == 0 && fix->backwards == 0)
7232 /* With AAPCS/iWMMXt enabled, the pool is aligned to an 8-byte boundary.
7233 So there might be an empty word before the start of the pool.
7234 Hence we reduce the forward range by 4 to allow for this
7236 if (ARM_DOUBLEWORD_ALIGN && fix->fix_size == 8)
7242 ";; %smode fixup for i%d; addr %lu, range (%ld,%ld): ",
7243 GET_MODE_NAME (mode),
7244 INSN_UID (insn), (unsigned long) address,
7245 -1 * (long)fix->backwards, (long)fix->forwards);
7246 arm_print_value (dump_file, fix->value);
7247 fprintf (dump_file, "\n");
7250 /* Add it to the chain of fixes. */
7253 if (minipool_fix_head != NULL)
7254 minipool_fix_tail->next = fix;
7256 minipool_fix_head = fix;
7258 minipool_fix_tail = fix;
7261 /* Return the cost of synthesising the const_double VAL inline.
7262 Returns the number of insns needed, or 99 if we don't know how to
7265 arm_const_double_inline_cost (rtx val)
7269 if (GET_MODE (val) == DFmode)
7272 if (!TARGET_SOFT_FLOAT)
7274 REAL_VALUE_FROM_CONST_DOUBLE (r, val);
7275 REAL_VALUE_TO_TARGET_DOUBLE (r, parts);
7277 else if (GET_MODE (val) != VOIDmode)
7281 parts[0] = CONST_DOUBLE_LOW (val);
7282 parts[1] = CONST_DOUBLE_HIGH (val);
7285 return (arm_gen_constant (SET, SImode, NULL_RTX, parts[0],
7286 NULL_RTX, NULL_RTX, 0, 0)
7287 + arm_gen_constant (SET, SImode, NULL_RTX, parts[1],
7288 NULL_RTX, NULL_RTX, 0, 0));
7291 /* Determine if a CONST_DOUBLE should be pushed to the minipool */
7293 const_double_needs_minipool (rtx val)
7295 /* thumb only knows to load a CONST_DOUBLE from memory at the moment */
7299 /* Don't push anything to the minipool if a CONST_DOUBLE can be built with
7300 a few ALU insns directly. On balance, the optimum is likely to be around
7301 3 insns, except when there are no load delay slots where it should be 4.
7302 When optimizing for size, a limit of 3 allows saving at least one word
7303 except for cases where a single minipool entry could be shared more than
7304 2 times which is rather unlikely to outweight the overall savings. */
7305 return (arm_const_double_inline_cost (val)
7306 > ((optimize_size || arm_ld_sched) ? 3 : 4));
7309 /* Scan INSN and note any of its operands that need fixing.
7310 If DO_PUSHES is false we do not actually push any of the fixups
7311 needed. The function returns TRUE is any fixups were needed/pushed.
7312 This is used by arm_memory_load_p() which needs to know about loads
7313 of constants that will be converted into minipool loads. */
7315 note_invalid_constants (rtx insn, HOST_WIDE_INT address, int do_pushes)
7317 bool result = false;
7320 extract_insn (insn);
7322 if (!constrain_operands (1))
7323 fatal_insn_not_found (insn);
7325 if (recog_data.n_alternatives == 0)
7328 /* Fill in recog_op_alt with information about the constraints of this insn. */
7329 preprocess_constraints ();
7331 for (opno = 0; opno < recog_data.n_operands; opno++)
7333 /* Things we need to fix can only occur in inputs. */
7334 if (recog_data.operand_type[opno] != OP_IN)
7337 /* If this alternative is a memory reference, then any mention
7338 of constants in this alternative is really to fool reload
7339 into allowing us to accept one there. We need to fix them up
7340 now so that we output the right code. */
7341 if (recog_op_alt[opno][which_alternative].memory_ok)
7343 rtx op = recog_data.operand[opno];
7346 && (GET_CODE (op) != CONST_DOUBLE
7347 || const_double_needs_minipool (op)))
7350 push_minipool_fix (insn, address, recog_data.operand_loc[opno],
7351 recog_data.operand_mode[opno], op);
7354 else if (GET_CODE (op) == MEM
7355 && GET_CODE (XEXP (op, 0)) == SYMBOL_REF
7356 && CONSTANT_POOL_ADDRESS_P (XEXP (op, 0)))
7360 rtx cop = avoid_constant_pool_reference (op);
7362 /* Casting the address of something to a mode narrower
7363 than a word can cause avoid_constant_pool_reference()
7364 to return the pool reference itself. That's no good to
7365 us here. Lets just hope that we can use the
7366 constant pool value directly. */
7368 cop = get_pool_constant (XEXP (op, 0));
7370 push_minipool_fix (insn, address,
7371 recog_data.operand_loc[opno],
7372 recog_data.operand_mode[opno], cop);
7383 /* Gcc puts the pool in the wrong place for ARM, since we can only
7384 load addresses a limited distance around the pc. We do some
7385 special munging to move the constant pool values to the correct
7386 point in the code. */
7391 HOST_WIDE_INT address = 0;
7394 minipool_fix_head = minipool_fix_tail = NULL;
7396 /* The first insn must always be a note, or the code below won't
7397 scan it properly. */
7398 insn = get_insns ();
7399 if (GET_CODE (insn) != NOTE)
7402 /* Scan all the insns and record the operands that will need fixing. */
7403 for (insn = next_nonnote_insn (insn); insn; insn = next_nonnote_insn (insn))
7405 if (TARGET_CIRRUS_FIX_INVALID_INSNS
7406 && (arm_cirrus_insn_p (insn)
7407 || GET_CODE (insn) == JUMP_INSN
7408 || arm_memory_load_p (insn)))
7409 cirrus_reorg (insn);
7411 if (GET_CODE (insn) == BARRIER)
7412 push_minipool_barrier (insn, address);
7413 else if (INSN_P (insn))
7417 note_invalid_constants (insn, address, true);
7418 address += get_attr_length (insn);
7420 /* If the insn is a vector jump, add the size of the table
7421 and skip the table. */
7422 if ((table = is_jump_table (insn)) != NULL)
7424 address += get_jump_table_size (table);
7430 fix = minipool_fix_head;
7432 /* Now scan the fixups and perform the required changes. */
7437 Mfix * last_added_fix;
7438 Mfix * last_barrier = NULL;
7441 /* Skip any further barriers before the next fix. */
7442 while (fix && GET_CODE (fix->insn) == BARRIER)
7445 /* No more fixes. */
7449 last_added_fix = NULL;
7451 for (ftmp = fix; ftmp; ftmp = ftmp->next)
7453 if (GET_CODE (ftmp->insn) == BARRIER)
7455 if (ftmp->address >= minipool_vector_head->max_address)
7458 last_barrier = ftmp;
7460 else if ((ftmp->minipool = add_minipool_forward_ref (ftmp)) == NULL)
7463 last_added_fix = ftmp; /* Keep track of the last fix added. */
7466 /* If we found a barrier, drop back to that; any fixes that we
7467 could have reached but come after the barrier will now go in
7468 the next mini-pool. */
7469 if (last_barrier != NULL)
7471 /* Reduce the refcount for those fixes that won't go into this
7473 for (fdel = last_barrier->next;
7474 fdel && fdel != ftmp;
7477 fdel->minipool->refcount--;
7478 fdel->minipool = NULL;
7481 ftmp = last_barrier;
7485 /* ftmp is first fix that we can't fit into this pool and
7486 there no natural barriers that we could use. Insert a
7487 new barrier in the code somewhere between the previous
7488 fix and this one, and arrange to jump around it. */
7489 HOST_WIDE_INT max_address;
7491 /* The last item on the list of fixes must be a barrier, so
7492 we can never run off the end of the list of fixes without
7493 last_barrier being set. */
7497 max_address = minipool_vector_head->max_address;
7498 /* Check that there isn't another fix that is in range that
7499 we couldn't fit into this pool because the pool was
7500 already too large: we need to put the pool before such an
7502 if (ftmp->address < max_address)
7503 max_address = ftmp->address;
7505 last_barrier = create_fix_barrier (last_added_fix, max_address);
7508 assign_minipool_offsets (last_barrier);
7512 if (GET_CODE (ftmp->insn) != BARRIER
7513 && ((ftmp->minipool = add_minipool_backward_ref (ftmp))
7520 /* Scan over the fixes we have identified for this pool, fixing them
7521 up and adding the constants to the pool itself. */
7522 for (this_fix = fix; this_fix && ftmp != this_fix;
7523 this_fix = this_fix->next)
7524 if (GET_CODE (this_fix->insn) != BARRIER)
7527 = plus_constant (gen_rtx_LABEL_REF (VOIDmode,
7528 minipool_vector_label),
7529 this_fix->minipool->offset);
7530 *this_fix->loc = gen_rtx_MEM (this_fix->mode, addr);
7533 dump_minipool (last_barrier->insn);
7537 /* From now on we must synthesize any constants that we can't handle
7538 directly. This can happen if the RTL gets split during final
7539 instruction generation. */
7540 after_arm_reorg = 1;
7542 /* Free the minipool memory. */
7543 obstack_free (&minipool_obstack, minipool_startobj);
7546 /* Routines to output assembly language. */
7548 /* If the rtx is the correct value then return the string of the number.
7549 In this way we can ensure that valid double constants are generated even
7550 when cross compiling. */
7552 fp_immediate_constant (rtx x)
7557 if (!fp_consts_inited)
7560 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
7561 for (i = 0; i < 8; i++)
7562 if (REAL_VALUES_EQUAL (r, values_fp[i]))
7563 return strings_fp[i];
7568 /* As for fp_immediate_constant, but value is passed directly, not in rtx. */
7570 fp_const_from_val (REAL_VALUE_TYPE *r)
7574 if (!fp_consts_inited)
7577 for (i = 0; i < 8; i++)
7578 if (REAL_VALUES_EQUAL (*r, values_fp[i]))
7579 return strings_fp[i];
7584 /* Output the operands of a LDM/STM instruction to STREAM.
7585 MASK is the ARM register set mask of which only bits 0-15 are important.
7586 REG is the base register, either the frame pointer or the stack pointer,
7587 INSTR is the possibly suffixed load or store instruction. */
7589 print_multi_reg (FILE *stream, const char *instr, int reg, int mask)
7592 int not_first = FALSE;
7594 fputc ('\t', stream);
7595 asm_fprintf (stream, instr, reg);
7596 fputs (", {", stream);
7598 for (i = 0; i <= LAST_ARM_REGNUM; i++)
7599 if (mask & (1 << i))
7602 fprintf (stream, ", ");
7604 asm_fprintf (stream, "%r", i);
7608 fprintf (stream, "}\n");
7612 /* Output a FLDMX instruction to STREAM.
7613 BASE if the register containing the address.
7614 REG and COUNT specify the register range.
7615 Extra registers may be added to avoid hardware bugs. */
7618 arm_output_fldmx (FILE * stream, unsigned int base, int reg, int count)
7622 /* Workaround ARM10 VFPr1 bug. */
7623 if (count == 2 && !arm_arch6)
7630 fputc ('\t', stream);
7631 asm_fprintf (stream, "fldmfdx\t%r!, {", base);
7633 for (i = reg; i < reg + count; i++)
7636 fputs (", ", stream);
7637 asm_fprintf (stream, "d%d", i);
7639 fputs ("}\n", stream);
7644 /* Output the assembly for a store multiple. */
7647 vfp_output_fstmx (rtx * operands)
7654 strcpy (pattern, "fstmfdx\t%m0!, {%P1");
7655 p = strlen (pattern);
7657 if (GET_CODE (operands[1]) != REG)
7660 base = (REGNO (operands[1]) - FIRST_VFP_REGNUM) / 2;
7661 for (i = 1; i < XVECLEN (operands[2], 0); i++)
7663 p += sprintf (&pattern[p], ", d%d", base + i);
7665 strcpy (&pattern[p], "}");
7667 output_asm_insn (pattern, operands);
7672 /* Emit RTL to save block of VFP register pairs to the stack. Returns the
7673 number of bytes pushed. */
7676 vfp_emit_fstmx (int base_reg, int count)
7683 /* Workaround ARM10 VFPr1 bug. Data corruption can occur when exactly two
7684 register pairs are stored by a store multiple insn. We avoid this
7685 by pushing an extra pair. */
7686 if (count == 2 && !arm_arch6)
7688 if (base_reg == LAST_VFP_REGNUM - 3)
7693 /* ??? The frame layout is implementation defined. We describe
7694 standard format 1 (equivalent to a FSTMD insn and unused pad word).
7695 We really need some way of representing the whole block so that the
7696 unwinder can figure it out at runtime. */
7697 par = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
7698 dwarf = gen_rtx_SEQUENCE (VOIDmode, rtvec_alloc (count + 1));
7700 reg = gen_rtx_REG (DFmode, base_reg);
7704 = gen_rtx_SET (VOIDmode,
7705 gen_rtx_MEM (BLKmode,
7706 gen_rtx_PRE_DEC (BLKmode, stack_pointer_rtx)),
7707 gen_rtx_UNSPEC (BLKmode,
7711 tmp = gen_rtx_SET (VOIDmode, stack_pointer_rtx,
7712 gen_rtx_PLUS (SImode, stack_pointer_rtx,
7713 GEN_INT (-(count * 8 + 4))));
7714 RTX_FRAME_RELATED_P (tmp) = 1;
7715 XVECEXP (dwarf, 0, 0) = tmp;
7717 tmp = gen_rtx_SET (VOIDmode,
7718 gen_rtx_MEM (DFmode, stack_pointer_rtx),
7720 RTX_FRAME_RELATED_P (tmp) = 1;
7721 XVECEXP (dwarf, 0, 1) = tmp;
7723 for (i = 1; i < count; i++)
7725 reg = gen_rtx_REG (DFmode, base_reg);
7727 XVECEXP (par, 0, i) = gen_rtx_USE (VOIDmode, reg);
7729 tmp = gen_rtx_SET (VOIDmode,
7730 gen_rtx_MEM (DFmode,
7731 gen_rtx_PLUS (SImode,
7735 RTX_FRAME_RELATED_P (tmp) = 1;
7736 XVECEXP (dwarf, 0, i + 1) = tmp;
7739 par = emit_insn (par);
7740 REG_NOTES (par) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, dwarf,
7742 RTX_FRAME_RELATED_P (par) = 1;
7744 return count * 8 + 4;
7748 /* Output a 'call' insn. */
7750 output_call (rtx *operands)
7753 abort (); /* Patterns should call blx <reg> directly. */
7755 /* Handle calls to lr using ip (which may be clobbered in subr anyway). */
7756 if (REGNO (operands[0]) == LR_REGNUM)
7758 operands[0] = gen_rtx_REG (SImode, IP_REGNUM);
7759 output_asm_insn ("mov%?\t%0, %|lr", operands);
7762 output_asm_insn ("mov%?\t%|lr, %|pc", operands);
7764 if (TARGET_INTERWORK || arm_arch4t)
7765 output_asm_insn ("bx%?\t%0", operands);
7767 output_asm_insn ("mov%?\t%|pc, %0", operands);
7772 /* Output a 'call' insn that is a reference in memory. */
7774 output_call_mem (rtx *operands)
7776 if (TARGET_INTERWORK && !arm_arch5)
7778 output_asm_insn ("ldr%?\t%|ip, %0", operands);
7779 output_asm_insn ("mov%?\t%|lr, %|pc", operands);
7780 output_asm_insn ("bx%?\t%|ip", operands);
7782 else if (regno_use_in (LR_REGNUM, operands[0]))
7784 /* LR is used in the memory address. We load the address in the
7785 first instruction. It's safe to use IP as the target of the
7786 load since the call will kill it anyway. */
7787 output_asm_insn ("ldr%?\t%|ip, %0", operands);
7789 output_asm_insn ("blx%?\t%|ip", operands);
7792 output_asm_insn ("mov%?\t%|lr, %|pc", operands);
7794 output_asm_insn ("bx%?\t%|ip", operands);
7796 output_asm_insn ("mov%?\t%|pc, %|ip", operands);
7801 output_asm_insn ("mov%?\t%|lr, %|pc", operands);
7802 output_asm_insn ("ldr%?\t%|pc, %0", operands);
7809 /* Output a move from arm registers to an fpa registers.
7810 OPERANDS[0] is an fpa register.
7811 OPERANDS[1] is the first registers of an arm register pair. */
7813 output_mov_long_double_fpa_from_arm (rtx *operands)
7815 int arm_reg0 = REGNO (operands[1]);
7818 if (arm_reg0 == IP_REGNUM)
7821 ops[0] = gen_rtx_REG (SImode, arm_reg0);
7822 ops[1] = gen_rtx_REG (SImode, 1 + arm_reg0);
7823 ops[2] = gen_rtx_REG (SImode, 2 + arm_reg0);
7825 output_asm_insn ("stm%?fd\t%|sp!, {%0, %1, %2}", ops);
7826 output_asm_insn ("ldf%?e\t%0, [%|sp], #12", operands);
7831 /* Output a move from an fpa register to arm registers.
7832 OPERANDS[0] is the first registers of an arm register pair.
7833 OPERANDS[1] is an fpa register. */
7835 output_mov_long_double_arm_from_fpa (rtx *operands)
7837 int arm_reg0 = REGNO (operands[0]);
7840 if (arm_reg0 == IP_REGNUM)
7843 ops[0] = gen_rtx_REG (SImode, arm_reg0);
7844 ops[1] = gen_rtx_REG (SImode, 1 + arm_reg0);
7845 ops[2] = gen_rtx_REG (SImode, 2 + arm_reg0);
7847 output_asm_insn ("stf%?e\t%1, [%|sp, #-12]!", operands);
7848 output_asm_insn ("ldm%?fd\t%|sp!, {%0, %1, %2}", ops);
7852 /* Output a move from arm registers to arm registers of a long double
7853 OPERANDS[0] is the destination.
7854 OPERANDS[1] is the source. */
7856 output_mov_long_double_arm_from_arm (rtx *operands)
7858 /* We have to be careful here because the two might overlap. */
7859 int dest_start = REGNO (operands[0]);
7860 int src_start = REGNO (operands[1]);
7864 if (dest_start < src_start)
7866 for (i = 0; i < 3; i++)
7868 ops[0] = gen_rtx_REG (SImode, dest_start + i);
7869 ops[1] = gen_rtx_REG (SImode, src_start + i);
7870 output_asm_insn ("mov%?\t%0, %1", ops);
7875 for (i = 2; i >= 0; i--)
7877 ops[0] = gen_rtx_REG (SImode, dest_start + i);
7878 ops[1] = gen_rtx_REG (SImode, src_start + i);
7879 output_asm_insn ("mov%?\t%0, %1", ops);
7887 /* Output a move from arm registers to an fpa registers.
7888 OPERANDS[0] is an fpa register.
7889 OPERANDS[1] is the first registers of an arm register pair. */
7891 output_mov_double_fpa_from_arm (rtx *operands)
7893 int arm_reg0 = REGNO (operands[1]);
7896 if (arm_reg0 == IP_REGNUM)
7899 ops[0] = gen_rtx_REG (SImode, arm_reg0);
7900 ops[1] = gen_rtx_REG (SImode, 1 + arm_reg0);
7901 output_asm_insn ("stm%?fd\t%|sp!, {%0, %1}", ops);
7902 output_asm_insn ("ldf%?d\t%0, [%|sp], #8", operands);
7906 /* Output a move from an fpa register to arm registers.
7907 OPERANDS[0] is the first registers of an arm register pair.
7908 OPERANDS[1] is an fpa register. */
7910 output_mov_double_arm_from_fpa (rtx *operands)
7912 int arm_reg0 = REGNO (operands[0]);
7915 if (arm_reg0 == IP_REGNUM)
7918 ops[0] = gen_rtx_REG (SImode, arm_reg0);
7919 ops[1] = gen_rtx_REG (SImode, 1 + arm_reg0);
7920 output_asm_insn ("stf%?d\t%1, [%|sp, #-8]!", operands);
7921 output_asm_insn ("ldm%?fd\t%|sp!, {%0, %1}", ops);
7925 /* Output a move between double words.
7926 It must be REG<-REG, REG<-CONST_DOUBLE, REG<-CONST_INT, REG<-MEM
7927 or MEM<-REG and all MEMs must be offsettable addresses. */
7929 output_move_double (rtx *operands)
7931 enum rtx_code code0 = GET_CODE (operands[0]);
7932 enum rtx_code code1 = GET_CODE (operands[1]);
7937 int reg0 = REGNO (operands[0]);
7939 otherops[0] = gen_rtx_REG (SImode, 1 + reg0);
7943 int reg1 = REGNO (operands[1]);
7944 if (reg1 == IP_REGNUM)
7947 /* Ensure the second source is not overwritten. */
7948 if (reg1 == reg0 + (WORDS_BIG_ENDIAN ? -1 : 1))
7949 output_asm_insn ("mov%?\t%Q0, %Q1\n\tmov%?\t%R0, %R1", operands);
7951 output_asm_insn ("mov%?\t%R0, %R1\n\tmov%?\t%Q0, %Q1", operands);
7953 else if (code1 == CONST_VECTOR)
7955 HOST_WIDE_INT hint = 0;
7957 switch (GET_MODE (operands[1]))
7960 otherops[1] = GEN_INT (INTVAL (CONST_VECTOR_ELT (operands[1], 1)));
7961 operands[1] = GEN_INT (INTVAL (CONST_VECTOR_ELT (operands[1], 0)));
7965 if (BYTES_BIG_ENDIAN)
7967 hint = INTVAL (CONST_VECTOR_ELT (operands[1], 2));
7969 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 3));
7973 hint = INTVAL (CONST_VECTOR_ELT (operands[1], 3));
7975 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 2));
7978 otherops[1] = GEN_INT (hint);
7981 if (BYTES_BIG_ENDIAN)
7983 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 0));
7985 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 1));
7989 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 1));
7991 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 0));
7994 operands[1] = GEN_INT (hint);
7998 if (BYTES_BIG_ENDIAN)
8000 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 4));
8002 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 5));
8004 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 6));
8006 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 7));
8010 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 7));
8012 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 6));
8014 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 5));
8016 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 4));
8019 otherops[1] = GEN_INT (hint);
8022 if (BYTES_BIG_ENDIAN)
8024 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 0));
8026 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 1));
8028 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 2));
8030 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 3));
8034 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 3));
8036 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 2));
8038 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 1));
8040 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 0));
8043 operands[1] = GEN_INT (hint);
8049 output_mov_immediate (operands);
8050 output_mov_immediate (otherops);
8052 else if (code1 == CONST_DOUBLE)
8054 if (GET_MODE (operands[1]) == DFmode)
8059 REAL_VALUE_FROM_CONST_DOUBLE (r, operands[1]);
8060 REAL_VALUE_TO_TARGET_DOUBLE (r, l);
8061 otherops[1] = GEN_INT (l[1]);
8062 operands[1] = GEN_INT (l[0]);
8064 else if (GET_MODE (operands[1]) != VOIDmode)
8066 else if (WORDS_BIG_ENDIAN)
8068 otherops[1] = GEN_INT (CONST_DOUBLE_LOW (operands[1]));
8069 operands[1] = GEN_INT (CONST_DOUBLE_HIGH (operands[1]));
8073 otherops[1] = GEN_INT (CONST_DOUBLE_HIGH (operands[1]));
8074 operands[1] = GEN_INT (CONST_DOUBLE_LOW (operands[1]));
8077 output_mov_immediate (operands);
8078 output_mov_immediate (otherops);
8080 else if (code1 == CONST_INT)
8082 #if HOST_BITS_PER_WIDE_INT > 32
8083 /* If HOST_WIDE_INT is more than 32 bits, the intval tells us
8084 what the upper word is. */
8085 if (WORDS_BIG_ENDIAN)
8087 otherops[1] = GEN_INT (ARM_SIGN_EXTEND (INTVAL (operands[1])));
8088 operands[1] = GEN_INT (INTVAL (operands[1]) >> 32);
8092 otherops[1] = GEN_INT (INTVAL (operands[1]) >> 32);
8093 operands[1] = GEN_INT (ARM_SIGN_EXTEND (INTVAL (operands[1])));
8096 /* Sign extend the intval into the high-order word. */
8097 if (WORDS_BIG_ENDIAN)
8099 otherops[1] = operands[1];
8100 operands[1] = (INTVAL (operands[1]) < 0
8101 ? constm1_rtx : const0_rtx);
8104 otherops[1] = INTVAL (operands[1]) < 0 ? constm1_rtx : const0_rtx;
8106 output_mov_immediate (otherops);
8107 output_mov_immediate (operands);
8109 else if (code1 == MEM)
8111 switch (GET_CODE (XEXP (operands[1], 0)))
8114 output_asm_insn ("ldm%?ia\t%m1, %M0", operands);
8119 abort (); /* Should never happen now. */
8120 output_asm_insn ("ldr%?d\t%0, [%m1, #8]!", operands);
8124 output_asm_insn ("ldm%?db\t%m1!, %M0", operands);
8128 output_asm_insn ("ldm%?ia\t%m1!, %M0", operands);
8133 abort (); /* Should never happen now. */
8134 output_asm_insn ("ldr%?d\t%0, [%m1], #-8", operands);
8139 otherops[0] = operands[0];
8140 otherops[1] = XEXP (XEXP (XEXP (operands[1], 0), 1), 0);
8141 otherops[2] = XEXP (XEXP (XEXP (operands[1], 0), 1), 1);
8143 if (GET_CODE (XEXP (operands[1], 0)) == PRE_MODIFY)
8145 if (reg_overlap_mentioned_p (otherops[0], otherops[2]))
8147 /* Registers overlap so split out the increment. */
8148 output_asm_insn ("add%?\t%1, %1, %2", otherops);
8149 output_asm_insn ("ldr%?d\t%0, [%1] @split", otherops);
8152 output_asm_insn ("ldr%?d\t%0, [%1, %2]!", otherops);
8156 /* We only allow constant increments, so this is safe. */
8157 output_asm_insn ("ldr%?d\t%0, [%1], %2", otherops);
8163 output_asm_insn ("adr%?\t%0, %1", operands);
8164 output_asm_insn ("ldm%?ia\t%0, %M0", operands);
8168 if (arm_add_operand (XEXP (XEXP (operands[1], 0), 1),
8169 GET_MODE (XEXP (XEXP (operands[1], 0), 1))))
8171 otherops[0] = operands[0];
8172 otherops[1] = XEXP (XEXP (operands[1], 0), 0);
8173 otherops[2] = XEXP (XEXP (operands[1], 0), 1);
8175 if (GET_CODE (XEXP (operands[1], 0)) == PLUS)
8177 if (GET_CODE (otherops[2]) == CONST_INT)
8179 switch ((int) INTVAL (otherops[2]))
8182 output_asm_insn ("ldm%?db\t%1, %M0", otherops);
8185 output_asm_insn ("ldm%?da\t%1, %M0", otherops);
8188 output_asm_insn ("ldm%?ib\t%1, %M0", otherops);
8193 && (GET_CODE (otherops[2]) == REG
8194 || (GET_CODE (otherops[2]) == CONST_INT
8195 && INTVAL (otherops[2]) > -256
8196 && INTVAL (otherops[2]) < 256)))
8198 if (reg_overlap_mentioned_p (otherops[0],
8201 /* Swap base and index registers over to
8202 avoid a conflict. */
8203 otherops[1] = XEXP (XEXP (operands[1], 0), 1);
8204 otherops[2] = XEXP (XEXP (operands[1], 0), 0);
8207 /* If both registers conflict, it will usually
8208 have been fixed by a splitter. */
8209 if (reg_overlap_mentioned_p (otherops[0],
8212 output_asm_insn ("add%?\t%1, %1, %2", otherops);
8213 output_asm_insn ("ldr%?d\t%0, [%1]",
8219 output_asm_insn ("ldr%?d\t%0, [%1, %2]",
8224 if (GET_CODE (otherops[2]) == CONST_INT)
8226 if (!(const_ok_for_arm (INTVAL (otherops[2]))))
8227 output_asm_insn ("sub%?\t%0, %1, #%n2", otherops);
8229 output_asm_insn ("add%?\t%0, %1, %2", otherops);
8232 output_asm_insn ("add%?\t%0, %1, %2", otherops);
8235 output_asm_insn ("sub%?\t%0, %1, %2", otherops);
8237 return "ldm%?ia\t%0, %M0";
8241 otherops[1] = adjust_address (operands[1], SImode, 4);
8242 /* Take care of overlapping base/data reg. */
8243 if (reg_mentioned_p (operands[0], operands[1]))
8245 output_asm_insn ("ldr%?\t%0, %1", otherops);
8246 output_asm_insn ("ldr%?\t%0, %1", operands);
8250 output_asm_insn ("ldr%?\t%0, %1", operands);
8251 output_asm_insn ("ldr%?\t%0, %1", otherops);
8257 abort (); /* Constraints should prevent this. */
8259 else if (code0 == MEM && code1 == REG)
8261 if (REGNO (operands[1]) == IP_REGNUM)
8264 switch (GET_CODE (XEXP (operands[0], 0)))
8267 output_asm_insn ("stm%?ia\t%m0, %M1", operands);
8272 abort (); /* Should never happen now. */
8273 output_asm_insn ("str%?d\t%1, [%m0, #8]!", operands);
8277 output_asm_insn ("stm%?db\t%m0!, %M1", operands);
8281 output_asm_insn ("stm%?ia\t%m0!, %M1", operands);
8286 abort (); /* Should never happen now. */
8287 output_asm_insn ("str%?d\t%1, [%m0], #-8", operands);
8292 otherops[0] = operands[1];
8293 otherops[1] = XEXP (XEXP (XEXP (operands[0], 0), 1), 0);
8294 otherops[2] = XEXP (XEXP (XEXP (operands[0], 0), 1), 1);
8296 if (GET_CODE (XEXP (operands[0], 0)) == PRE_MODIFY)
8297 output_asm_insn ("str%?d\t%0, [%1, %2]!", otherops);
8299 output_asm_insn ("str%?d\t%0, [%1], %2", otherops);
8303 otherops[2] = XEXP (XEXP (operands[0], 0), 1);
8304 if (GET_CODE (otherops[2]) == CONST_INT)
8306 switch ((int) INTVAL (XEXP (XEXP (operands[0], 0), 1)))
8309 output_asm_insn ("stm%?db\t%m0, %M1", operands);
8313 output_asm_insn ("stm%?da\t%m0, %M1", operands);
8317 output_asm_insn ("stm%?ib\t%m0, %M1", operands);
8322 && (GET_CODE (otherops[2]) == REG
8323 || (GET_CODE (otherops[2]) == CONST_INT
8324 && INTVAL (otherops[2]) > -256
8325 && INTVAL (otherops[2]) < 256)))
8327 otherops[0] = operands[1];
8328 otherops[1] = XEXP (XEXP (operands[0], 0), 0);
8329 output_asm_insn ("str%?d\t%0, [%1, %2]", otherops);
8335 otherops[0] = adjust_address (operands[0], SImode, 4);
8336 otherops[1] = gen_rtx_REG (SImode, 1 + REGNO (operands[1]));
8337 output_asm_insn ("str%?\t%1, %0", operands);
8338 output_asm_insn ("str%?\t%1, %0", otherops);
8342 /* Constraints should prevent this. */
8349 /* Output an arbitrary MOV reg, #n.
8350 OPERANDS[0] is a register. OPERANDS[1] is a const_int. */
8352 output_mov_immediate (rtx *operands)
8354 HOST_WIDE_INT n = INTVAL (operands[1]);
8356 /* Try to use one MOV. */
8357 if (const_ok_for_arm (n))
8358 output_asm_insn ("mov%?\t%0, %1", operands);
8360 /* Try to use one MVN. */
8361 else if (const_ok_for_arm (~n))
8363 operands[1] = GEN_INT (~n);
8364 output_asm_insn ("mvn%?\t%0, %1", operands);
8371 /* If all else fails, make it out of ORRs or BICs as appropriate. */
8372 for (i = 0; i < 32; i++)
8376 if (n_ones > 16) /* Shorter to use MVN with BIC in this case. */
8377 output_multi_immediate (operands, "mvn%?\t%0, %1", "bic%?\t%0, %0, %1", 1, ~ n);
8379 output_multi_immediate (operands, "mov%?\t%0, %1", "orr%?\t%0, %0, %1", 1, n);
8385 /* Output an ADD r, s, #n where n may be too big for one instruction.
8386 If adding zero to one register, output nothing. */
8388 output_add_immediate (rtx *operands)
8390 HOST_WIDE_INT n = INTVAL (operands[2]);
8392 if (n != 0 || REGNO (operands[0]) != REGNO (operands[1]))
8395 output_multi_immediate (operands,
8396 "sub%?\t%0, %1, %2", "sub%?\t%0, %0, %2", 2,
8399 output_multi_immediate (operands,
8400 "add%?\t%0, %1, %2", "add%?\t%0, %0, %2", 2,
8407 /* Output a multiple immediate operation.
8408 OPERANDS is the vector of operands referred to in the output patterns.
8409 INSTR1 is the output pattern to use for the first constant.
8410 INSTR2 is the output pattern to use for subsequent constants.
8411 IMMED_OP is the index of the constant slot in OPERANDS.
8412 N is the constant value. */
8414 output_multi_immediate (rtx *operands, const char *instr1, const char *instr2,
8415 int immed_op, HOST_WIDE_INT n)
8417 #if HOST_BITS_PER_WIDE_INT > 32
8423 /* Quick and easy output. */
8424 operands[immed_op] = const0_rtx;
8425 output_asm_insn (instr1, operands);
8430 const char * instr = instr1;
8432 /* Note that n is never zero here (which would give no output). */
8433 for (i = 0; i < 32; i += 2)
8437 operands[immed_op] = GEN_INT (n & (255 << i));
8438 output_asm_insn (instr, operands);
8448 /* Return the appropriate ARM instruction for the operation code.
8449 The returned result should not be overwritten. OP is the rtx of the
8450 operation. SHIFT_FIRST_ARG is TRUE if the first argument of the operator
8453 arithmetic_instr (rtx op, int shift_first_arg)
8455 switch (GET_CODE (op))
8461 return shift_first_arg ? "rsb" : "sub";
8477 /* Ensure valid constant shifts and return the appropriate shift mnemonic
8478 for the operation code. The returned result should not be overwritten.
8479 OP is the rtx code of the shift.
8480 On exit, *AMOUNTP will be -1 if the shift is by a register, or a constant
8483 shift_op (rtx op, HOST_WIDE_INT *amountp)
8486 enum rtx_code code = GET_CODE (op);
8488 if (GET_CODE (XEXP (op, 1)) == REG || GET_CODE (XEXP (op, 1)) == SUBREG)
8490 else if (GET_CODE (XEXP (op, 1)) == CONST_INT)
8491 *amountp = INTVAL (XEXP (op, 1));
8512 *amountp = 32 - *amountp;
8521 /* We never have to worry about the amount being other than a
8522 power of 2, since this case can never be reloaded from a reg. */
8524 *amountp = int_log2 (*amountp);
8535 /* This is not 100% correct, but follows from the desire to merge
8536 multiplication by a power of 2 with the recognizer for a
8537 shift. >=32 is not a valid shift for "asl", so we must try and
8538 output a shift that produces the correct arithmetical result.
8539 Using lsr #32 is identical except for the fact that the carry bit
8540 is not set correctly if we set the flags; but we never use the
8541 carry bit from such an operation, so we can ignore that. */
8542 if (code == ROTATERT)
8543 /* Rotate is just modulo 32. */
8545 else if (*amountp != (*amountp & 31))
8552 /* Shifts of 0 are no-ops. */
8560 /* Obtain the shift from the POWER of two. */
8562 static HOST_WIDE_INT
8563 int_log2 (HOST_WIDE_INT power)
8565 HOST_WIDE_INT shift = 0;
8567 while ((((HOST_WIDE_INT) 1 << shift) & power) == 0)
8577 /* Output a .ascii pseudo-op, keeping track of lengths. This is because
8578 /bin/as is horribly restrictive. */
8579 #define MAX_ASCII_LEN 51
8582 output_ascii_pseudo_op (FILE *stream, const unsigned char *p, int len)
8587 fputs ("\t.ascii\t\"", stream);
8589 for (i = 0; i < len; i++)
8593 if (len_so_far >= MAX_ASCII_LEN)
8595 fputs ("\"\n\t.ascii\t\"", stream);
8602 fputs ("\\t", stream);
8607 fputs ("\\f", stream);
8612 fputs ("\\b", stream);
8617 fputs ("\\r", stream);
8621 case TARGET_NEWLINE:
8622 fputs ("\\n", stream);
8624 if ((c >= ' ' && c <= '~')
8626 /* This is a good place for a line break. */
8627 len_so_far = MAX_ASCII_LEN;
8634 putc ('\\', stream);
8639 if (c >= ' ' && c <= '~')
8646 fprintf (stream, "\\%03o", c);
8653 fputs ("\"\n", stream);
8656 /* Compute the register save mask for registers 0 through 12
8657 inclusive. This code is used by arm_compute_save_reg_mask. */
8658 static unsigned long
8659 arm_compute_save_reg0_reg12_mask (void)
8661 unsigned long func_type = arm_current_func_type ();
8662 unsigned int save_reg_mask = 0;
8665 if (IS_INTERRUPT (func_type))
8667 unsigned int max_reg;
8668 /* Interrupt functions must not corrupt any registers,
8669 even call clobbered ones. If this is a leaf function
8670 we can just examine the registers used by the RTL, but
8671 otherwise we have to assume that whatever function is
8672 called might clobber anything, and so we have to save
8673 all the call-clobbered registers as well. */
8674 if (ARM_FUNC_TYPE (func_type) == ARM_FT_FIQ)
8675 /* FIQ handlers have registers r8 - r12 banked, so
8676 we only need to check r0 - r7, Normal ISRs only
8677 bank r14 and r15, so we must check up to r12.
8678 r13 is the stack pointer which is always preserved,
8679 so we do not need to consider it here. */
8684 for (reg = 0; reg <= max_reg; reg++)
8685 if (regs_ever_live[reg]
8686 || (! current_function_is_leaf && call_used_regs [reg]))
8687 save_reg_mask |= (1 << reg);
8689 /* Also save the pic base register if necessary. */
8691 && !TARGET_SINGLE_PIC_BASE
8692 && current_function_uses_pic_offset_table)
8693 save_reg_mask |= 1 << PIC_OFFSET_TABLE_REGNUM;
8697 /* In the normal case we only need to save those registers
8698 which are call saved and which are used by this function. */
8699 for (reg = 0; reg <= 10; reg++)
8700 if (regs_ever_live[reg] && ! call_used_regs [reg])
8701 save_reg_mask |= (1 << reg);
8703 /* Handle the frame pointer as a special case. */
8704 if (! TARGET_APCS_FRAME
8705 && ! frame_pointer_needed
8706 && regs_ever_live[HARD_FRAME_POINTER_REGNUM]
8707 && ! call_used_regs[HARD_FRAME_POINTER_REGNUM])
8708 save_reg_mask |= 1 << HARD_FRAME_POINTER_REGNUM;
8710 /* If we aren't loading the PIC register,
8711 don't stack it even though it may be live. */
8713 && !TARGET_SINGLE_PIC_BASE
8714 && (regs_ever_live[PIC_OFFSET_TABLE_REGNUM]
8715 || current_function_uses_pic_offset_table))
8716 save_reg_mask |= 1 << PIC_OFFSET_TABLE_REGNUM;
8719 /* Save registers so the exception handler can modify them. */
8720 if (current_function_calls_eh_return)
8726 reg = EH_RETURN_DATA_REGNO (i);
8727 if (reg == INVALID_REGNUM)
8729 save_reg_mask |= 1 << reg;
8733 return save_reg_mask;
8736 /* Compute a bit mask of which registers need to be
8737 saved on the stack for the current function. */
8739 static unsigned long
8740 arm_compute_save_reg_mask (void)
8742 unsigned int save_reg_mask = 0;
8743 unsigned long func_type = arm_current_func_type ();
8745 if (IS_NAKED (func_type))
8746 /* This should never really happen. */
8749 /* If we are creating a stack frame, then we must save the frame pointer,
8750 IP (which will hold the old stack pointer), LR and the PC. */
8751 if (frame_pointer_needed)
8753 (1 << ARM_HARD_FRAME_POINTER_REGNUM)
8758 /* Volatile functions do not return, so there
8759 is no need to save any other registers. */
8760 if (IS_VOLATILE (func_type))
8761 return save_reg_mask;
8763 save_reg_mask |= arm_compute_save_reg0_reg12_mask ();
8765 /* Decide if we need to save the link register.
8766 Interrupt routines have their own banked link register,
8767 so they never need to save it.
8768 Otherwise if we do not use the link register we do not need to save
8769 it. If we are pushing other registers onto the stack however, we
8770 can save an instruction in the epilogue by pushing the link register
8771 now and then popping it back into the PC. This incurs extra memory
8772 accesses though, so we only do it when optimizing for size, and only
8773 if we know that we will not need a fancy return sequence. */
8774 if (regs_ever_live [LR_REGNUM]
8777 && ARM_FUNC_TYPE (func_type) == ARM_FT_NORMAL
8778 && !current_function_calls_eh_return))
8779 save_reg_mask |= 1 << LR_REGNUM;
8781 if (cfun->machine->lr_save_eliminated)
8782 save_reg_mask &= ~ (1 << LR_REGNUM);
8784 if (TARGET_REALLY_IWMMXT
8785 && ((bit_count (save_reg_mask)
8786 + ARM_NUM_INTS (current_function_pretend_args_size)) % 2) != 0)
8790 /* The total number of registers that are going to be pushed
8791 onto the stack is odd. We need to ensure that the stack
8792 is 64-bit aligned before we start to save iWMMXt registers,
8793 and also before we start to create locals. (A local variable
8794 might be a double or long long which we will load/store using
8795 an iWMMXt instruction). Therefore we need to push another
8796 ARM register, so that the stack will be 64-bit aligned. We
8797 try to avoid using the arg registers (r0 -r3) as they might be
8798 used to pass values in a tail call. */
8799 for (reg = 4; reg <= 12; reg++)
8800 if ((save_reg_mask & (1 << reg)) == 0)
8804 save_reg_mask |= (1 << reg);
8807 cfun->machine->sibcall_blocked = 1;
8808 save_reg_mask |= (1 << 3);
8812 return save_reg_mask;
8816 /* Compute a bit mask of which registers need to be
8817 saved on the stack for the current function. */
8818 static unsigned long
8819 thumb_compute_save_reg_mask (void)
8825 for (reg = 0; reg < 12; reg ++)
8827 if (regs_ever_live[reg] && !call_used_regs[reg])
8831 if (flag_pic && !TARGET_SINGLE_PIC_BASE)
8832 mask |= (1 << PIC_OFFSET_TABLE_REGNUM);
8833 if (TARGET_SINGLE_PIC_BASE)
8834 mask &= ~(1 << arm_pic_register);
8835 /* See if we might need r11 for calls to _interwork_r11_call_via_rN(). */
8836 if (!frame_pointer_needed && CALLER_INTERWORKING_SLOT_SIZE > 0)
8837 mask |= 1 << ARM_HARD_FRAME_POINTER_REGNUM;
8839 /* lr will also be pushed if any lo regs are pushed. */
8840 if (mask & 0xff || thumb_force_lr_save ())
8841 mask |= (1 << LR_REGNUM);
8843 /* Make sure we have a low work register if we need one. */
8844 if (((mask & 0xff) == 0 && regs_ever_live[LAST_ARG_REGNUM])
8845 && ((mask & 0x0f00) || TARGET_BACKTRACE))
8846 mask |= 1 << LAST_LO_REGNUM;
8852 /* Return the number of bytes required to save VFP registers. */
8854 arm_get_vfp_saved_size (void)
8861 /* Space for saved VFP registers. */
8862 if (TARGET_HARD_FLOAT && TARGET_VFP)
8865 for (regno = FIRST_VFP_REGNUM;
8866 regno < LAST_VFP_REGNUM;
8869 if ((!regs_ever_live[regno] || call_used_regs[regno])
8870 && (!regs_ever_live[regno + 1] || call_used_regs[regno + 1]))
8874 /* Workaround ARM10 VFPr1 bug. */
8875 if (count == 2 && !arm_arch6)
8877 saved += count * 8 + 4;
8886 if (count == 2 && !arm_arch6)
8888 saved += count * 8 + 4;
8895 /* Generate a function exit sequence. If REALLY_RETURN is false, then do
8896 everything bar the final return instruction. */
8898 output_return_instruction (rtx operand, int really_return, int reverse)
8900 char conditional[10];
8903 unsigned long live_regs_mask;
8904 unsigned long func_type;
8905 arm_stack_offsets *offsets;
8907 func_type = arm_current_func_type ();
8909 if (IS_NAKED (func_type))
8912 if (IS_VOLATILE (func_type) && TARGET_ABORT_NORETURN)
8914 /* If this function was declared non-returning, and we have
8915 found a tail call, then we have to trust that the called
8916 function won't return. */
8921 /* Otherwise, trap an attempted return by aborting. */
8923 ops[1] = gen_rtx_SYMBOL_REF (Pmode, NEED_PLT_RELOC ? "abort(PLT)"
8925 assemble_external_libcall (ops[1]);
8926 output_asm_insn (reverse ? "bl%D0\t%a1" : "bl%d0\t%a1", ops);
8932 if (current_function_calls_alloca && !really_return)
8935 sprintf (conditional, "%%?%%%c0", reverse ? 'D' : 'd');
8937 return_used_this_function = 1;
8939 live_regs_mask = arm_compute_save_reg_mask ();
8943 const char * return_reg;
8945 /* If we do not have any special requirements for function exit
8946 (e.g. interworking, or ISR) then we can load the return address
8947 directly into the PC. Otherwise we must load it into LR. */
8949 && ! TARGET_INTERWORK)
8950 return_reg = reg_names[PC_REGNUM];
8952 return_reg = reg_names[LR_REGNUM];
8954 if ((live_regs_mask & (1 << IP_REGNUM)) == (1 << IP_REGNUM))
8956 /* There are three possible reasons for the IP register
8957 being saved. 1) a stack frame was created, in which case
8958 IP contains the old stack pointer, or 2) an ISR routine
8959 corrupted it, or 3) it was saved to align the stack on
8960 iWMMXt. In case 1, restore IP into SP, otherwise just
8962 if (frame_pointer_needed)
8964 live_regs_mask &= ~ (1 << IP_REGNUM);
8965 live_regs_mask |= (1 << SP_REGNUM);
8969 if (! IS_INTERRUPT (func_type)
8970 && ! TARGET_REALLY_IWMMXT)
8975 /* On some ARM architectures it is faster to use LDR rather than
8976 LDM to load a single register. On other architectures, the
8977 cost is the same. In 26 bit mode, or for exception handlers,
8978 we have to use LDM to load the PC so that the CPSR is also
8980 for (reg = 0; reg <= LAST_ARM_REGNUM; reg++)
8982 if (live_regs_mask == (unsigned int)(1 << reg))
8985 if (reg <= LAST_ARM_REGNUM
8986 && (reg != LR_REGNUM
8988 || ! IS_INTERRUPT (func_type)))
8990 sprintf (instr, "ldr%s\t%%|%s, [%%|sp], #4", conditional,
8991 (reg == LR_REGNUM) ? return_reg : reg_names[reg]);
8998 /* Generate the load multiple instruction to restore the
8999 registers. Note we can get here, even if
9000 frame_pointer_needed is true, but only if sp already
9001 points to the base of the saved core registers. */
9002 if (live_regs_mask & (1 << SP_REGNUM))
9004 unsigned HOST_WIDE_INT stack_adjust;
9006 offsets = arm_get_frame_offsets ();
9007 stack_adjust = offsets->outgoing_args - offsets->saved_regs;
9008 if (stack_adjust != 0 && stack_adjust != 4)
9011 if (stack_adjust && arm_arch5)
9012 sprintf (instr, "ldm%sib\t%%|sp, {", conditional);
9015 /* If we can't use ldmib (SA110 bug), then try to pop r3
9018 live_regs_mask |= 1 << 3;
9019 sprintf (instr, "ldm%sfd\t%%|sp, {", conditional);
9023 sprintf (instr, "ldm%sfd\t%%|sp!, {", conditional);
9025 p = instr + strlen (instr);
9027 for (reg = 0; reg <= SP_REGNUM; reg++)
9028 if (live_regs_mask & (1 << reg))
9030 int l = strlen (reg_names[reg]);
9036 memcpy (p, ", ", 2);
9040 memcpy (p, "%|", 2);
9041 memcpy (p + 2, reg_names[reg], l);
9045 if (live_regs_mask & (1 << LR_REGNUM))
9047 sprintf (p, "%s%%|%s}", first ? "" : ", ", return_reg);
9048 /* If returning from an interrupt, restore the CPSR. */
9049 if (IS_INTERRUPT (func_type))
9056 output_asm_insn (instr, & operand);
9058 /* See if we need to generate an extra instruction to
9059 perform the actual function return. */
9061 && func_type != ARM_FT_INTERWORKED
9062 && (live_regs_mask & (1 << LR_REGNUM)) != 0)
9064 /* The return has already been handled
9065 by loading the LR into the PC. */
9072 switch ((int) ARM_FUNC_TYPE (func_type))
9076 sprintf (instr, "sub%ss\t%%|pc, %%|lr, #4", conditional);
9079 case ARM_FT_INTERWORKED:
9080 sprintf (instr, "bx%s\t%%|lr", conditional);
9083 case ARM_FT_EXCEPTION:
9084 sprintf (instr, "mov%ss\t%%|pc, %%|lr", conditional);
9088 /* Use bx if it's available. */
9089 if (arm_arch5 || arm_arch4t)
9090 sprintf (instr, "bx%s\t%%|lr", conditional);
9092 sprintf (instr, "mov%s\t%%|pc, %%|lr", conditional);
9096 output_asm_insn (instr, & operand);
9102 /* Write the function name into the code section, directly preceding
9103 the function prologue.
9105 Code will be output similar to this:
9107 .ascii "arm_poke_function_name", 0
9110 .word 0xff000000 + (t1 - t0)
9111 arm_poke_function_name
9113 stmfd sp!, {fp, ip, lr, pc}
9116 When performing a stack backtrace, code can inspect the value
9117 of 'pc' stored at 'fp' + 0. If the trace function then looks
9118 at location pc - 12 and the top 8 bits are set, then we know
9119 that there is a function name embedded immediately preceding this
9120 location and has length ((pc[-3]) & 0xff000000).
9122 We assume that pc is declared as a pointer to an unsigned long.
9124 It is of no benefit to output the function name if we are assembling
9125 a leaf function. These function types will not contain a stack
9126 backtrace structure, therefore it is not possible to determine the
9129 arm_poke_function_name (FILE *stream, const char *name)
9131 unsigned long alignlength;
9132 unsigned long length;
9135 length = strlen (name) + 1;
9136 alignlength = ROUND_UP_WORD (length);
9138 ASM_OUTPUT_ASCII (stream, name, length);
9139 ASM_OUTPUT_ALIGN (stream, 2);
9140 x = GEN_INT ((unsigned HOST_WIDE_INT) 0xff000000 + alignlength);
9141 assemble_aligned_integer (UNITS_PER_WORD, x);
9144 /* Place some comments into the assembler stream
9145 describing the current function. */
9147 arm_output_function_prologue (FILE *f, HOST_WIDE_INT frame_size)
9149 unsigned long func_type;
9153 thumb_output_function_prologue (f, frame_size);
9158 if (arm_ccfsm_state || arm_target_insn)
9161 func_type = arm_current_func_type ();
9163 switch ((int) ARM_FUNC_TYPE (func_type))
9168 case ARM_FT_INTERWORKED:
9169 asm_fprintf (f, "\t%@ Function supports interworking.\n");
9172 asm_fprintf (f, "\t%@ Interrupt Service Routine.\n");
9175 asm_fprintf (f, "\t%@ Fast Interrupt Service Routine.\n");
9177 case ARM_FT_EXCEPTION:
9178 asm_fprintf (f, "\t%@ ARM Exception Handler.\n");
9182 if (IS_NAKED (func_type))
9183 asm_fprintf (f, "\t%@ Naked Function: prologue and epilogue provided by programmer.\n");
9185 if (IS_VOLATILE (func_type))
9186 asm_fprintf (f, "\t%@ Volatile: function does not return.\n");
9188 if (IS_NESTED (func_type))
9189 asm_fprintf (f, "\t%@ Nested: function declared inside another function.\n");
9191 asm_fprintf (f, "\t%@ args = %d, pretend = %d, frame = %wd\n",
9192 current_function_args_size,
9193 current_function_pretend_args_size, frame_size);
9195 asm_fprintf (f, "\t%@ frame_needed = %d, uses_anonymous_args = %d\n",
9196 frame_pointer_needed,
9197 cfun->machine->uses_anonymous_args);
9199 if (cfun->machine->lr_save_eliminated)
9200 asm_fprintf (f, "\t%@ link register save eliminated.\n");
9202 if (current_function_calls_eh_return)
9203 asm_fprintf (f, "\t@ Calls __builtin_eh_return.\n");
9205 #ifdef AOF_ASSEMBLER
9207 asm_fprintf (f, "\tmov\t%r, %r\n", IP_REGNUM, PIC_OFFSET_TABLE_REGNUM);
9210 return_used_this_function = 0;
9214 arm_output_epilogue (rtx sibling)
9217 unsigned long saved_regs_mask;
9218 unsigned long func_type;
9219 /* Floats_offset is the offset from the "virtual" frame. In an APCS
9220 frame that is $fp + 4 for a non-variadic function. */
9221 int floats_offset = 0;
9223 FILE * f = asm_out_file;
9224 unsigned int lrm_count = 0;
9225 int really_return = (sibling == NULL);
9227 arm_stack_offsets *offsets;
9229 /* If we have already generated the return instruction
9230 then it is futile to generate anything else. */
9231 if (use_return_insn (FALSE, sibling) && return_used_this_function)
9234 func_type = arm_current_func_type ();
9236 if (IS_NAKED (func_type))
9237 /* Naked functions don't have epilogues. */
9240 if (IS_VOLATILE (func_type) && TARGET_ABORT_NORETURN)
9244 /* A volatile function should never return. Call abort. */
9245 op = gen_rtx_SYMBOL_REF (Pmode, NEED_PLT_RELOC ? "abort(PLT)" : "abort");
9246 assemble_external_libcall (op);
9247 output_asm_insn ("bl\t%a0", &op);
9252 if (current_function_calls_eh_return
9254 /* If we are throwing an exception, then we really must
9255 be doing a return, so we can't tail-call. */
9258 offsets = arm_get_frame_offsets ();
9259 saved_regs_mask = arm_compute_save_reg_mask ();
9262 lrm_count = bit_count (saved_regs_mask);
9264 floats_offset = offsets->saved_args;
9265 /* Compute how far away the floats will be. */
9266 for (reg = 0; reg <= LAST_ARM_REGNUM; reg++)
9267 if (saved_regs_mask & (1 << reg))
9270 if (frame_pointer_needed)
9272 /* This variable is for the Virtual Frame Pointer, not VFP regs. */
9273 int vfp_offset = offsets->frame;
9275 if (arm_fpu_arch == FPUTYPE_FPA_EMU2)
9277 for (reg = LAST_FPA_REGNUM; reg >= FIRST_FPA_REGNUM; reg--)
9278 if (regs_ever_live[reg] && !call_used_regs[reg])
9280 floats_offset += 12;
9281 asm_fprintf (f, "\tldfe\t%r, [%r, #-%d]\n",
9282 reg, FP_REGNUM, floats_offset - vfp_offset);
9287 start_reg = LAST_FPA_REGNUM;
9289 for (reg = LAST_FPA_REGNUM; reg >= FIRST_FPA_REGNUM; reg--)
9291 if (regs_ever_live[reg] && !call_used_regs[reg])
9293 floats_offset += 12;
9295 /* We can't unstack more than four registers at once. */
9296 if (start_reg - reg == 3)
9298 asm_fprintf (f, "\tlfm\t%r, 4, [%r, #-%d]\n",
9299 reg, FP_REGNUM, floats_offset - vfp_offset);
9300 start_reg = reg - 1;
9305 if (reg != start_reg)
9306 asm_fprintf (f, "\tlfm\t%r, %d, [%r, #-%d]\n",
9307 reg + 1, start_reg - reg,
9308 FP_REGNUM, floats_offset - vfp_offset);
9309 start_reg = reg - 1;
9313 /* Just in case the last register checked also needs unstacking. */
9314 if (reg != start_reg)
9315 asm_fprintf (f, "\tlfm\t%r, %d, [%r, #-%d]\n",
9316 reg + 1, start_reg - reg,
9317 FP_REGNUM, floats_offset - vfp_offset);
9320 if (TARGET_HARD_FLOAT && TARGET_VFP)
9324 /* The fldmx insn does not have base+offset addressing modes,
9325 so we use IP to hold the address. */
9326 saved_size = arm_get_vfp_saved_size ();
9330 floats_offset += saved_size;
9331 asm_fprintf (f, "\tsub\t%r, %r, #%d\n", IP_REGNUM,
9332 FP_REGNUM, floats_offset - vfp_offset);
9334 start_reg = FIRST_VFP_REGNUM;
9335 for (reg = FIRST_VFP_REGNUM; reg < LAST_VFP_REGNUM; reg += 2)
9337 if ((!regs_ever_live[reg] || call_used_regs[reg])
9338 && (!regs_ever_live[reg + 1] || call_used_regs[reg + 1]))
9340 if (start_reg != reg)
9341 arm_output_fldmx (f, IP_REGNUM,
9342 (start_reg - FIRST_VFP_REGNUM) / 2,
9343 (reg - start_reg) / 2);
9344 start_reg = reg + 2;
9347 if (start_reg != reg)
9348 arm_output_fldmx (f, IP_REGNUM,
9349 (start_reg - FIRST_VFP_REGNUM) / 2,
9350 (reg - start_reg) / 2);
9355 /* The frame pointer is guaranteed to be non-double-word aligned.
9356 This is because it is set to (old_stack_pointer - 4) and the
9357 old_stack_pointer was double word aligned. Thus the offset to
9358 the iWMMXt registers to be loaded must also be non-double-word
9359 sized, so that the resultant address *is* double-word aligned.
9360 We can ignore floats_offset since that was already included in
9361 the live_regs_mask. */
9362 lrm_count += (lrm_count % 2 ? 2 : 1);
9364 for (reg = LAST_IWMMXT_REGNUM; reg >= FIRST_IWMMXT_REGNUM; reg--)
9365 if (regs_ever_live[reg] && !call_used_regs[reg])
9367 asm_fprintf (f, "\twldrd\t%r, [%r, #-%d]\n",
9368 reg, FP_REGNUM, lrm_count * 4);
9373 /* saved_regs_mask should contain the IP, which at the time of stack
9374 frame generation actually contains the old stack pointer. So a
9375 quick way to unwind the stack is just pop the IP register directly
9376 into the stack pointer. */
9377 if ((saved_regs_mask & (1 << IP_REGNUM)) == 0)
9379 saved_regs_mask &= ~ (1 << IP_REGNUM);
9380 saved_regs_mask |= (1 << SP_REGNUM);
9382 /* There are two registers left in saved_regs_mask - LR and PC. We
9383 only need to restore the LR register (the return address), but to
9384 save time we can load it directly into the PC, unless we need a
9385 special function exit sequence, or we are not really returning. */
9387 && ARM_FUNC_TYPE (func_type) == ARM_FT_NORMAL
9388 && !current_function_calls_eh_return)
9389 /* Delete the LR from the register mask, so that the LR on
9390 the stack is loaded into the PC in the register mask. */
9391 saved_regs_mask &= ~ (1 << LR_REGNUM);
9393 saved_regs_mask &= ~ (1 << PC_REGNUM);
9395 /* We must use SP as the base register, because SP is one of the
9396 registers being restored. If an interrupt or page fault
9397 happens in the ldm instruction, the SP might or might not
9398 have been restored. That would be bad, as then SP will no
9399 longer indicate the safe area of stack, and we can get stack
9400 corruption. Using SP as the base register means that it will
9401 be reset correctly to the original value, should an interrupt
9402 occur. If the stack pointer already points at the right
9403 place, then omit the subtraction. */
9404 if (offsets->outgoing_args != (1 + (int) bit_count (saved_regs_mask))
9405 || current_function_calls_alloca)
9406 asm_fprintf (f, "\tsub\t%r, %r, #%d\n", SP_REGNUM, FP_REGNUM,
9407 4 * bit_count (saved_regs_mask));
9408 print_multi_reg (f, "ldmfd\t%r", SP_REGNUM, saved_regs_mask);
9410 if (IS_INTERRUPT (func_type))
9411 /* Interrupt handlers will have pushed the
9412 IP onto the stack, so restore it now. */
9413 print_multi_reg (f, "ldmfd\t%r!", SP_REGNUM, 1 << IP_REGNUM);
9417 /* Restore stack pointer if necessary. */
9418 if (offsets->outgoing_args != offsets->saved_regs)
9420 operands[0] = operands[1] = stack_pointer_rtx;
9421 operands[2] = GEN_INT (offsets->outgoing_args - offsets->saved_regs);
9422 output_add_immediate (operands);
9425 if (arm_fpu_arch == FPUTYPE_FPA_EMU2)
9427 for (reg = FIRST_FPA_REGNUM; reg <= LAST_FPA_REGNUM; reg++)
9428 if (regs_ever_live[reg] && !call_used_regs[reg])
9429 asm_fprintf (f, "\tldfe\t%r, [%r], #12\n",
9434 start_reg = FIRST_FPA_REGNUM;
9436 for (reg = FIRST_FPA_REGNUM; reg <= LAST_FPA_REGNUM; reg++)
9438 if (regs_ever_live[reg] && !call_used_regs[reg])
9440 if (reg - start_reg == 3)
9442 asm_fprintf (f, "\tlfmfd\t%r, 4, [%r]!\n",
9443 start_reg, SP_REGNUM);
9444 start_reg = reg + 1;
9449 if (reg != start_reg)
9450 asm_fprintf (f, "\tlfmfd\t%r, %d, [%r]!\n",
9451 start_reg, reg - start_reg,
9454 start_reg = reg + 1;
9458 /* Just in case the last register checked also needs unstacking. */
9459 if (reg != start_reg)
9460 asm_fprintf (f, "\tlfmfd\t%r, %d, [%r]!\n",
9461 start_reg, reg - start_reg, SP_REGNUM);
9464 if (TARGET_HARD_FLOAT && TARGET_VFP)
9466 start_reg = FIRST_VFP_REGNUM;
9467 for (reg = FIRST_VFP_REGNUM; reg < LAST_VFP_REGNUM; reg += 2)
9469 if ((!regs_ever_live[reg] || call_used_regs[reg])
9470 && (!regs_ever_live[reg + 1] || call_used_regs[reg + 1]))
9472 if (start_reg != reg)
9473 arm_output_fldmx (f, SP_REGNUM,
9474 (start_reg - FIRST_VFP_REGNUM) / 2,
9475 (reg - start_reg) / 2);
9476 start_reg = reg + 2;
9479 if (start_reg != reg)
9480 arm_output_fldmx (f, SP_REGNUM,
9481 (start_reg - FIRST_VFP_REGNUM) / 2,
9482 (reg - start_reg) / 2);
9485 for (reg = FIRST_IWMMXT_REGNUM; reg <= LAST_IWMMXT_REGNUM; reg++)
9486 if (regs_ever_live[reg] && !call_used_regs[reg])
9487 asm_fprintf (f, "\twldrd\t%r, [%r], #8\n", reg, SP_REGNUM);
9489 /* If we can, restore the LR into the PC. */
9490 if (ARM_FUNC_TYPE (func_type) == ARM_FT_NORMAL
9492 && current_function_pretend_args_size == 0
9493 && saved_regs_mask & (1 << LR_REGNUM)
9494 && !current_function_calls_eh_return)
9496 saved_regs_mask &= ~ (1 << LR_REGNUM);
9497 saved_regs_mask |= (1 << PC_REGNUM);
9500 /* Load the registers off the stack. If we only have one register
9501 to load use the LDR instruction - it is faster. */
9502 if (saved_regs_mask == (1 << LR_REGNUM))
9504 asm_fprintf (f, "\tldr\t%r, [%r], #4\n", LR_REGNUM, SP_REGNUM);
9506 else if (saved_regs_mask)
9508 if (saved_regs_mask & (1 << SP_REGNUM))
9509 /* Note - write back to the stack register is not enabled
9510 (i.e. "ldmfd sp!..."). We know that the stack pointer is
9511 in the list of registers and if we add writeback the
9512 instruction becomes UNPREDICTABLE. */
9513 print_multi_reg (f, "ldmfd\t%r", SP_REGNUM, saved_regs_mask);
9515 print_multi_reg (f, "ldmfd\t%r!", SP_REGNUM, saved_regs_mask);
9518 if (current_function_pretend_args_size)
9520 /* Unwind the pre-pushed regs. */
9521 operands[0] = operands[1] = stack_pointer_rtx;
9522 operands[2] = GEN_INT (current_function_pretend_args_size);
9523 output_add_immediate (operands);
9527 /* We may have already restored PC directly from the stack. */
9528 if (!really_return || saved_regs_mask & (1 << PC_REGNUM))
9531 /* Stack adjustment for exception handler. */
9532 if (current_function_calls_eh_return)
9533 asm_fprintf (f, "\tadd\t%r, %r, %r\n", SP_REGNUM, SP_REGNUM,
9534 ARM_EH_STACKADJ_REGNUM);
9536 /* Generate the return instruction. */
9537 switch ((int) ARM_FUNC_TYPE (func_type))
9541 asm_fprintf (f, "\tsubs\t%r, %r, #4\n", PC_REGNUM, LR_REGNUM);
9544 case ARM_FT_EXCEPTION:
9545 asm_fprintf (f, "\tmovs\t%r, %r\n", PC_REGNUM, LR_REGNUM);
9548 case ARM_FT_INTERWORKED:
9549 asm_fprintf (f, "\tbx\t%r\n", LR_REGNUM);
9553 if (arm_arch5 || arm_arch4t)
9554 asm_fprintf (f, "\tbx\t%r\n", LR_REGNUM);
9556 asm_fprintf (f, "\tmov\t%r, %r\n", PC_REGNUM, LR_REGNUM);
9564 arm_output_function_epilogue (FILE *file ATTRIBUTE_UNUSED,
9565 HOST_WIDE_INT frame_size ATTRIBUTE_UNUSED)
9567 arm_stack_offsets *offsets;
9571 /* ??? Probably not safe to set this here, since it assumes that a
9572 function will be emitted as assembly immediately after we generate
9573 RTL for it. This does not happen for inline functions. */
9574 return_used_this_function = 0;
9578 /* We need to take into account any stack-frame rounding. */
9579 offsets = arm_get_frame_offsets ();
9581 if (use_return_insn (FALSE, NULL)
9582 && return_used_this_function
9583 && offsets->saved_regs != offsets->outgoing_args
9584 && !frame_pointer_needed)
9587 /* Reset the ARM-specific per-function variables. */
9588 after_arm_reorg = 0;
9592 /* Generate and emit an insn that we will recognize as a push_multi.
9593 Unfortunately, since this insn does not reflect very well the actual
9594 semantics of the operation, we need to annotate the insn for the benefit
9595 of DWARF2 frame unwind information. */
9597 emit_multi_reg_push (int mask)
9604 int dwarf_par_index;
9607 for (i = 0; i <= LAST_ARM_REGNUM; i++)
9608 if (mask & (1 << i))
9611 if (num_regs == 0 || num_regs > 16)
9614 /* We don't record the PC in the dwarf frame information. */
9615 num_dwarf_regs = num_regs;
9616 if (mask & (1 << PC_REGNUM))
9619 /* For the body of the insn we are going to generate an UNSPEC in
9620 parallel with several USEs. This allows the insn to be recognized
9621 by the push_multi pattern in the arm.md file. The insn looks
9622 something like this:
9625 (set (mem:BLK (pre_dec:BLK (reg:SI sp)))
9626 (unspec:BLK [(reg:SI r4)] UNSPEC_PUSH_MULT))
9627 (use (reg:SI 11 fp))
9628 (use (reg:SI 12 ip))
9629 (use (reg:SI 14 lr))
9630 (use (reg:SI 15 pc))
9633 For the frame note however, we try to be more explicit and actually
9634 show each register being stored into the stack frame, plus a (single)
9635 decrement of the stack pointer. We do it this way in order to be
9636 friendly to the stack unwinding code, which only wants to see a single
9637 stack decrement per instruction. The RTL we generate for the note looks
9638 something like this:
9641 (set (reg:SI sp) (plus:SI (reg:SI sp) (const_int -20)))
9642 (set (mem:SI (reg:SI sp)) (reg:SI r4))
9643 (set (mem:SI (plus:SI (reg:SI sp) (const_int 4))) (reg:SI fp))
9644 (set (mem:SI (plus:SI (reg:SI sp) (const_int 8))) (reg:SI ip))
9645 (set (mem:SI (plus:SI (reg:SI sp) (const_int 12))) (reg:SI lr))
9648 This sequence is used both by the code to support stack unwinding for
9649 exceptions handlers and the code to generate dwarf2 frame debugging. */
9651 par = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (num_regs));
9652 dwarf = gen_rtx_SEQUENCE (VOIDmode, rtvec_alloc (num_dwarf_regs + 1));
9653 dwarf_par_index = 1;
9655 for (i = 0; i <= LAST_ARM_REGNUM; i++)
9657 if (mask & (1 << i))
9659 reg = gen_rtx_REG (SImode, i);
9662 = gen_rtx_SET (VOIDmode,
9663 gen_rtx_MEM (BLKmode,
9664 gen_rtx_PRE_DEC (BLKmode,
9665 stack_pointer_rtx)),
9666 gen_rtx_UNSPEC (BLKmode,
9672 tmp = gen_rtx_SET (VOIDmode,
9673 gen_rtx_MEM (SImode, stack_pointer_rtx),
9675 RTX_FRAME_RELATED_P (tmp) = 1;
9676 XVECEXP (dwarf, 0, dwarf_par_index) = tmp;
9684 for (j = 1, i++; j < num_regs; i++)
9686 if (mask & (1 << i))
9688 reg = gen_rtx_REG (SImode, i);
9690 XVECEXP (par, 0, j) = gen_rtx_USE (VOIDmode, reg);
9694 tmp = gen_rtx_SET (VOIDmode,
9695 gen_rtx_MEM (SImode,
9696 plus_constant (stack_pointer_rtx,
9699 RTX_FRAME_RELATED_P (tmp) = 1;
9700 XVECEXP (dwarf, 0, dwarf_par_index++) = tmp;
9707 par = emit_insn (par);
9709 tmp = gen_rtx_SET (SImode,
9711 gen_rtx_PLUS (SImode,
9713 GEN_INT (-4 * num_regs)));
9714 RTX_FRAME_RELATED_P (tmp) = 1;
9715 XVECEXP (dwarf, 0, 0) = tmp;
9717 REG_NOTES (par) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, dwarf,
9723 emit_sfm (int base_reg, int count)
9730 par = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
9731 dwarf = gen_rtx_SEQUENCE (VOIDmode, rtvec_alloc (count + 1));
9733 reg = gen_rtx_REG (XFmode, base_reg++);
9736 = gen_rtx_SET (VOIDmode,
9737 gen_rtx_MEM (BLKmode,
9738 gen_rtx_PRE_DEC (BLKmode, stack_pointer_rtx)),
9739 gen_rtx_UNSPEC (BLKmode,
9742 tmp = gen_rtx_SET (VOIDmode,
9743 gen_rtx_MEM (XFmode, stack_pointer_rtx), reg);
9744 RTX_FRAME_RELATED_P (tmp) = 1;
9745 XVECEXP (dwarf, 0, 1) = tmp;
9747 for (i = 1; i < count; i++)
9749 reg = gen_rtx_REG (XFmode, base_reg++);
9750 XVECEXP (par, 0, i) = gen_rtx_USE (VOIDmode, reg);
9752 tmp = gen_rtx_SET (VOIDmode,
9753 gen_rtx_MEM (XFmode,
9754 plus_constant (stack_pointer_rtx,
9757 RTX_FRAME_RELATED_P (tmp) = 1;
9758 XVECEXP (dwarf, 0, i + 1) = tmp;
9761 tmp = gen_rtx_SET (VOIDmode,
9763 gen_rtx_PLUS (SImode,
9765 GEN_INT (-12 * count)));
9766 RTX_FRAME_RELATED_P (tmp) = 1;
9767 XVECEXP (dwarf, 0, 0) = tmp;
9769 par = emit_insn (par);
9770 REG_NOTES (par) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, dwarf,
9776 /* Return true if the current function needs to save/restore LR. */
9779 thumb_force_lr_save (void)
9781 return !cfun->machine->lr_save_eliminated
9782 && (!leaf_function_p ()
9783 || thumb_far_jump_used_p ()
9784 || regs_ever_live [LR_REGNUM]);
9788 /* Compute the distance from register FROM to register TO.
9789 These can be the arg pointer (26), the soft frame pointer (25),
9790 the stack pointer (13) or the hard frame pointer (11).
9791 In thumb mode r7 is used as the soft frame pointer, if needed.
9792 Typical stack layout looks like this:
9794 old stack pointer -> | |
9797 | | saved arguments for
9798 | | vararg functions
9801 hard FP & arg pointer -> | | \
9809 soft frame pointer -> | | /
9819 current stack pointer -> | | /
9822 For a given function some or all of these stack components
9823 may not be needed, giving rise to the possibility of
9824 eliminating some of the registers.
9826 The values returned by this function must reflect the behavior
9827 of arm_expand_prologue() and arm_compute_save_reg_mask().
9829 The sign of the number returned reflects the direction of stack
9830 growth, so the values are positive for all eliminations except
9831 from the soft frame pointer to the hard frame pointer.
9833 SFP may point just inside the local variables block to ensure correct
9837 /* Calculate stack offsets. These are used to calculate register elimination
9838 offsets and in prologue/epilogue code. */
9840 static arm_stack_offsets *
9841 arm_get_frame_offsets (void)
9843 struct arm_stack_offsets *offsets;
9844 unsigned long func_type;
9847 HOST_WIDE_INT frame_size;
9849 offsets = &cfun->machine->stack_offsets;
9851 /* We need to know if we are a leaf function. Unfortunately, it
9852 is possible to be called after start_sequence has been called,
9853 which causes get_insns to return the insns for the sequence,
9854 not the function, which will cause leaf_function_p to return
9855 the incorrect result.
9857 to know about leaf functions once reload has completed, and the
9858 frame size cannot be changed after that time, so we can safely
9859 use the cached value. */
9861 if (reload_completed)
9864 /* Initially this is the size of the local variables. It will translated
9865 into an offset once we have determined the size of preceding data. */
9866 frame_size = ROUND_UP_WORD (get_frame_size ());
9868 leaf = leaf_function_p ();
9870 /* Space for variadic functions. */
9871 offsets->saved_args = current_function_pretend_args_size;
9873 offsets->frame = offsets->saved_args + (frame_pointer_needed ? 4 : 0);
9879 saved = bit_count (arm_compute_save_reg_mask ()) * 4;
9881 /* We know that SP will be doubleword aligned on entry, and we must
9882 preserve that condition at any subroutine call. We also require the
9883 soft frame pointer to be doubleword aligned. */
9885 if (TARGET_REALLY_IWMMXT)
9887 /* Check for the call-saved iWMMXt registers. */
9888 for (regno = FIRST_IWMMXT_REGNUM;
9889 regno <= LAST_IWMMXT_REGNUM;
9891 if (regs_ever_live [regno] && ! call_used_regs [regno])
9895 func_type = arm_current_func_type ();
9896 if (! IS_VOLATILE (func_type))
9898 /* Space for saved FPA registers. */
9899 for (regno = FIRST_FPA_REGNUM; regno <= LAST_FPA_REGNUM; regno++)
9900 if (regs_ever_live[regno] && ! call_used_regs[regno])
9903 /* Space for saved VFP registers. */
9904 if (TARGET_HARD_FLOAT && TARGET_VFP)
9905 saved += arm_get_vfp_saved_size ();
9908 else /* TARGET_THUMB */
9910 saved = bit_count (thumb_compute_save_reg_mask ()) * 4;
9911 if (TARGET_BACKTRACE)
9915 /* Saved registers include the stack frame. */
9916 offsets->saved_regs = offsets->saved_args + saved;
9917 offsets->soft_frame = offsets->saved_regs + CALLER_INTERWORKING_SLOT_SIZE;
9918 /* A leaf function does not need any stack alignment if it has nothing
9920 if (leaf && frame_size == 0)
9922 offsets->outgoing_args = offsets->soft_frame;
9926 /* Ensure SFP has the correct alignment. */
9927 if (ARM_DOUBLEWORD_ALIGN
9928 && (offsets->soft_frame & 7))
9929 offsets->soft_frame += 4;
9931 offsets->outgoing_args = offsets->soft_frame + frame_size
9932 + current_function_outgoing_args_size;
9934 if (ARM_DOUBLEWORD_ALIGN)
9936 /* Ensure SP remains doubleword aligned. */
9937 if (offsets->outgoing_args & 7)
9938 offsets->outgoing_args += 4;
9939 if (offsets->outgoing_args & 7)
9947 /* Calculate the relative offsets for the different stack pointers. Positive
9948 offsets are in the direction of stack growth. */
9951 arm_compute_initial_elimination_offset (unsigned int from, unsigned int to)
9953 arm_stack_offsets *offsets;
9955 offsets = arm_get_frame_offsets ();
9957 /* OK, now we have enough information to compute the distances.
9958 There must be an entry in these switch tables for each pair
9959 of registers in ELIMINABLE_REGS, even if some of the entries
9960 seem to be redundant or useless. */
9963 case ARG_POINTER_REGNUM:
9966 case THUMB_HARD_FRAME_POINTER_REGNUM:
9969 case FRAME_POINTER_REGNUM:
9970 /* This is the reverse of the soft frame pointer
9971 to hard frame pointer elimination below. */
9972 return offsets->soft_frame - offsets->saved_args;
9974 case ARM_HARD_FRAME_POINTER_REGNUM:
9975 /* If there is no stack frame then the hard
9976 frame pointer and the arg pointer coincide. */
9977 if (offsets->frame == offsets->saved_regs)
9979 /* FIXME: Not sure about this. Maybe we should always return 0 ? */
9980 return (frame_pointer_needed
9981 && cfun->static_chain_decl != NULL
9982 && ! cfun->machine->uses_anonymous_args) ? 4 : 0;
9984 case STACK_POINTER_REGNUM:
9985 /* If nothing has been pushed on the stack at all
9986 then this will return -4. This *is* correct! */
9987 return offsets->outgoing_args - (offsets->saved_args + 4);
9994 case FRAME_POINTER_REGNUM:
9997 case THUMB_HARD_FRAME_POINTER_REGNUM:
10000 case ARM_HARD_FRAME_POINTER_REGNUM:
10001 /* The hard frame pointer points to the top entry in the
10002 stack frame. The soft frame pointer to the bottom entry
10003 in the stack frame. If there is no stack frame at all,
10004 then they are identical. */
10006 return offsets->frame - offsets->soft_frame;
10008 case STACK_POINTER_REGNUM:
10009 return offsets->outgoing_args - offsets->soft_frame;
10017 /* You cannot eliminate from the stack pointer.
10018 In theory you could eliminate from the hard frame
10019 pointer to the stack pointer, but this will never
10020 happen, since if a stack frame is not needed the
10021 hard frame pointer will never be used. */
10027 /* Generate the prologue instructions for entry into an ARM function. */
10029 arm_expand_prologue (void)
10035 unsigned long live_regs_mask;
10036 unsigned long func_type;
10038 int saved_pretend_args = 0;
10039 int saved_regs = 0;
10040 unsigned HOST_WIDE_INT args_to_push;
10041 arm_stack_offsets *offsets;
10043 func_type = arm_current_func_type ();
10045 /* Naked functions don't have prologues. */
10046 if (IS_NAKED (func_type))
10049 /* Make a copy of c_f_p_a_s as we may need to modify it locally. */
10050 args_to_push = current_function_pretend_args_size;
10052 /* Compute which register we will have to save onto the stack. */
10053 live_regs_mask = arm_compute_save_reg_mask ();
10055 ip_rtx = gen_rtx_REG (SImode, IP_REGNUM);
10057 if (frame_pointer_needed)
10059 if (IS_INTERRUPT (func_type))
10061 /* Interrupt functions must not corrupt any registers.
10062 Creating a frame pointer however, corrupts the IP
10063 register, so we must push it first. */
10064 insn = emit_multi_reg_push (1 << IP_REGNUM);
10066 /* Do not set RTX_FRAME_RELATED_P on this insn.
10067 The dwarf stack unwinding code only wants to see one
10068 stack decrement per function, and this is not it. If
10069 this instruction is labeled as being part of the frame
10070 creation sequence then dwarf2out_frame_debug_expr will
10071 abort when it encounters the assignment of IP to FP
10072 later on, since the use of SP here establishes SP as
10073 the CFA register and not IP.
10075 Anyway this instruction is not really part of the stack
10076 frame creation although it is part of the prologue. */
10078 else if (IS_NESTED (func_type))
10080 /* The Static chain register is the same as the IP register
10081 used as a scratch register during stack frame creation.
10082 To get around this need to find somewhere to store IP
10083 whilst the frame is being created. We try the following
10086 1. The last argument register.
10087 2. A slot on the stack above the frame. (This only
10088 works if the function is not a varargs function).
10089 3. Register r3, after pushing the argument registers
10092 Note - we only need to tell the dwarf2 backend about the SP
10093 adjustment in the second variant; the static chain register
10094 doesn't need to be unwound, as it doesn't contain a value
10095 inherited from the caller. */
10097 if (regs_ever_live[3] == 0)
10099 insn = gen_rtx_REG (SImode, 3);
10100 insn = gen_rtx_SET (SImode, insn, ip_rtx);
10101 insn = emit_insn (insn);
10103 else if (args_to_push == 0)
10106 insn = gen_rtx_PRE_DEC (SImode, stack_pointer_rtx);
10107 insn = gen_rtx_MEM (SImode, insn);
10108 insn = gen_rtx_SET (VOIDmode, insn, ip_rtx);
10109 insn = emit_insn (insn);
10113 /* Just tell the dwarf backend that we adjusted SP. */
10114 dwarf = gen_rtx_SET (VOIDmode, stack_pointer_rtx,
10115 gen_rtx_PLUS (SImode, stack_pointer_rtx,
10116 GEN_INT (-fp_offset)));
10117 RTX_FRAME_RELATED_P (insn) = 1;
10118 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
10119 dwarf, REG_NOTES (insn));
10123 /* Store the args on the stack. */
10124 if (cfun->machine->uses_anonymous_args)
10125 insn = emit_multi_reg_push
10126 ((0xf0 >> (args_to_push / 4)) & 0xf);
10129 (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,
10130 GEN_INT (- args_to_push)));
10132 RTX_FRAME_RELATED_P (insn) = 1;
10134 saved_pretend_args = 1;
10135 fp_offset = args_to_push;
10138 /* Now reuse r3 to preserve IP. */
10139 insn = gen_rtx_REG (SImode, 3);
10140 insn = gen_rtx_SET (SImode, insn, ip_rtx);
10141 (void) emit_insn (insn);
10147 insn = gen_rtx_PLUS (SImode, stack_pointer_rtx, GEN_INT (fp_offset));
10148 insn = gen_rtx_SET (SImode, ip_rtx, insn);
10151 insn = gen_movsi (ip_rtx, stack_pointer_rtx);
10153 insn = emit_insn (insn);
10154 RTX_FRAME_RELATED_P (insn) = 1;
10159 /* Push the argument registers, or reserve space for them. */
10160 if (cfun->machine->uses_anonymous_args)
10161 insn = emit_multi_reg_push
10162 ((0xf0 >> (args_to_push / 4)) & 0xf);
10165 (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,
10166 GEN_INT (- args_to_push)));
10167 RTX_FRAME_RELATED_P (insn) = 1;
10170 /* If this is an interrupt service routine, and the link register
10171 is going to be pushed, and we are not creating a stack frame,
10172 (which would involve an extra push of IP and a pop in the epilogue)
10173 subtracting four from LR now will mean that the function return
10174 can be done with a single instruction. */
10175 if ((func_type == ARM_FT_ISR || func_type == ARM_FT_FIQ)
10176 && (live_regs_mask & (1 << LR_REGNUM)) != 0
10177 && ! frame_pointer_needed)
10178 emit_insn (gen_rtx_SET (SImode,
10179 gen_rtx_REG (SImode, LR_REGNUM),
10180 gen_rtx_PLUS (SImode,
10181 gen_rtx_REG (SImode, LR_REGNUM),
10184 if (live_regs_mask)
10186 insn = emit_multi_reg_push (live_regs_mask);
10187 saved_regs += bit_count (live_regs_mask) * 4;
10188 RTX_FRAME_RELATED_P (insn) = 1;
10192 for (reg = LAST_IWMMXT_REGNUM; reg >= FIRST_IWMMXT_REGNUM; reg--)
10193 if (regs_ever_live[reg] && ! call_used_regs [reg])
10195 insn = gen_rtx_PRE_DEC (V2SImode, stack_pointer_rtx);
10196 insn = gen_rtx_MEM (V2SImode, insn);
10197 insn = emit_insn (gen_rtx_SET (VOIDmode, insn,
10198 gen_rtx_REG (V2SImode, reg)));
10199 RTX_FRAME_RELATED_P (insn) = 1;
10203 if (! IS_VOLATILE (func_type))
10207 /* Save any floating point call-saved registers used by this
10209 if (arm_fpu_arch == FPUTYPE_FPA_EMU2)
10211 for (reg = LAST_FPA_REGNUM; reg >= FIRST_FPA_REGNUM; reg--)
10212 if (regs_ever_live[reg] && !call_used_regs[reg])
10214 insn = gen_rtx_PRE_DEC (XFmode, stack_pointer_rtx);
10215 insn = gen_rtx_MEM (XFmode, insn);
10216 insn = emit_insn (gen_rtx_SET (VOIDmode, insn,
10217 gen_rtx_REG (XFmode, reg)));
10218 RTX_FRAME_RELATED_P (insn) = 1;
10224 start_reg = LAST_FPA_REGNUM;
10226 for (reg = LAST_FPA_REGNUM; reg >= FIRST_FPA_REGNUM; reg--)
10228 if (regs_ever_live[reg] && !call_used_regs[reg])
10230 if (start_reg - reg == 3)
10232 insn = emit_sfm (reg, 4);
10233 RTX_FRAME_RELATED_P (insn) = 1;
10235 start_reg = reg - 1;
10240 if (start_reg != reg)
10242 insn = emit_sfm (reg + 1, start_reg - reg);
10243 RTX_FRAME_RELATED_P (insn) = 1;
10244 saved_regs += (start_reg - reg) * 12;
10246 start_reg = reg - 1;
10250 if (start_reg != reg)
10252 insn = emit_sfm (reg + 1, start_reg - reg);
10253 saved_regs += (start_reg - reg) * 12;
10254 RTX_FRAME_RELATED_P (insn) = 1;
10257 if (TARGET_HARD_FLOAT && TARGET_VFP)
10259 start_reg = FIRST_VFP_REGNUM;
10261 for (reg = FIRST_VFP_REGNUM; reg < LAST_VFP_REGNUM; reg += 2)
10263 if ((!regs_ever_live[reg] || call_used_regs[reg])
10264 && (!regs_ever_live[reg + 1] || call_used_regs[reg + 1]))
10266 if (start_reg != reg)
10267 saved_regs += vfp_emit_fstmx (start_reg,
10268 (reg - start_reg) / 2);
10269 start_reg = reg + 2;
10272 if (start_reg != reg)
10273 saved_regs += vfp_emit_fstmx (start_reg,
10274 (reg - start_reg) / 2);
10278 if (frame_pointer_needed)
10280 /* Create the new frame pointer. */
10281 insn = GEN_INT (-(4 + args_to_push + fp_offset));
10282 insn = emit_insn (gen_addsi3 (hard_frame_pointer_rtx, ip_rtx, insn));
10283 RTX_FRAME_RELATED_P (insn) = 1;
10285 if (IS_NESTED (func_type))
10287 /* Recover the static chain register. */
10288 if (regs_ever_live [3] == 0
10289 || saved_pretend_args)
10290 insn = gen_rtx_REG (SImode, 3);
10291 else /* if (current_function_pretend_args_size == 0) */
10293 insn = gen_rtx_PLUS (SImode, hard_frame_pointer_rtx,
10295 insn = gen_rtx_MEM (SImode, insn);
10298 emit_insn (gen_rtx_SET (SImode, ip_rtx, insn));
10299 /* Add a USE to stop propagate_one_insn() from barfing. */
10300 emit_insn (gen_prologue_use (ip_rtx));
10304 offsets = arm_get_frame_offsets ();
10305 if (offsets->outgoing_args != offsets->saved_args + saved_regs)
10307 /* This add can produce multiple insns for a large constant, so we
10308 need to get tricky. */
10309 rtx last = get_last_insn ();
10311 amount = GEN_INT (offsets->saved_args + saved_regs
10312 - offsets->outgoing_args);
10314 insn = emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,
10318 last = last ? NEXT_INSN (last) : get_insns ();
10319 RTX_FRAME_RELATED_P (last) = 1;
10321 while (last != insn);
10323 /* If the frame pointer is needed, emit a special barrier that
10324 will prevent the scheduler from moving stores to the frame
10325 before the stack adjustment. */
10326 if (frame_pointer_needed)
10327 insn = emit_insn (gen_stack_tie (stack_pointer_rtx,
10328 hard_frame_pointer_rtx));
10333 arm_load_pic_register (INVALID_REGNUM);
10335 /* If we are profiling, make sure no instructions are scheduled before
10336 the call to mcount. Similarly if the user has requested no
10337 scheduling in the prolog. */
10338 if (current_function_profile || TARGET_NO_SCHED_PRO)
10339 emit_insn (gen_blockage ());
10341 /* If the link register is being kept alive, with the return address in it,
10342 then make sure that it does not get reused by the ce2 pass. */
10343 if ((live_regs_mask & (1 << LR_REGNUM)) == 0)
10345 emit_insn (gen_prologue_use (gen_rtx_REG (SImode, LR_REGNUM)));
10346 cfun->machine->lr_save_eliminated = 1;
10350 /* If CODE is 'd', then the X is a condition operand and the instruction
10351 should only be executed if the condition is true.
10352 if CODE is 'D', then the X is a condition operand and the instruction
10353 should only be executed if the condition is false: however, if the mode
10354 of the comparison is CCFPEmode, then always execute the instruction -- we
10355 do this because in these circumstances !GE does not necessarily imply LT;
10356 in these cases the instruction pattern will take care to make sure that
10357 an instruction containing %d will follow, thereby undoing the effects of
10358 doing this instruction unconditionally.
10359 If CODE is 'N' then X is a floating point operand that must be negated
10361 If CODE is 'B' then output a bitwise inverted value of X (a const int).
10362 If X is a REG and CODE is `M', output a ldm/stm style multi-reg. */
10364 arm_print_operand (FILE *stream, rtx x, int code)
10369 fputs (ASM_COMMENT_START, stream);
10373 fputs (user_label_prefix, stream);
10377 fputs (REGISTER_PREFIX, stream);
10381 if (arm_ccfsm_state == 3 || arm_ccfsm_state == 4)
10385 output_operand_lossage ("predicated Thumb instruction");
10388 if (current_insn_predicate != NULL)
10390 output_operand_lossage
10391 ("predicated instruction in conditional sequence");
10395 fputs (arm_condition_codes[arm_current_cc], stream);
10397 else if (current_insn_predicate)
10399 enum arm_cond_code code;
10403 output_operand_lossage ("predicated Thumb instruction");
10407 code = get_arm_condition_code (current_insn_predicate);
10408 fputs (arm_condition_codes[code], stream);
10415 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
10416 r = REAL_VALUE_NEGATE (r);
10417 fprintf (stream, "%s", fp_const_from_val (&r));
10422 if (GET_CODE (x) == CONST_INT)
10425 val = ARM_SIGN_EXTEND (~INTVAL (x));
10426 fprintf (stream, HOST_WIDE_INT_PRINT_DEC, val);
10430 putc ('~', stream);
10431 output_addr_const (stream, x);
10436 fprintf (stream, "%s", arithmetic_instr (x, 1));
10439 /* Truncate Cirrus shift counts. */
10441 if (GET_CODE (x) == CONST_INT)
10443 fprintf (stream, HOST_WIDE_INT_PRINT_DEC, INTVAL (x) & 0x3f);
10446 arm_print_operand (stream, x, 0);
10450 fprintf (stream, "%s", arithmetic_instr (x, 0));
10456 const char * shift = shift_op (x, &val);
10460 fprintf (stream, ", %s ", shift_op (x, &val));
10462 arm_print_operand (stream, XEXP (x, 1), 0);
10464 fprintf (stream, "#" HOST_WIDE_INT_PRINT_DEC, val);
10469 /* An explanation of the 'Q', 'R' and 'H' register operands:
10471 In a pair of registers containing a DI or DF value the 'Q'
10472 operand returns the register number of the register containing
10473 the least significant part of the value. The 'R' operand returns
10474 the register number of the register containing the most
10475 significant part of the value.
10477 The 'H' operand returns the higher of the two register numbers.
10478 On a run where WORDS_BIG_ENDIAN is true the 'H' operand is the
10479 same as the 'Q' operand, since the most significant part of the
10480 value is held in the lower number register. The reverse is true
10481 on systems where WORDS_BIG_ENDIAN is false.
10483 The purpose of these operands is to distinguish between cases
10484 where the endian-ness of the values is important (for example
10485 when they are added together), and cases where the endian-ness
10486 is irrelevant, but the order of register operations is important.
10487 For example when loading a value from memory into a register
10488 pair, the endian-ness does not matter. Provided that the value
10489 from the lower memory address is put into the lower numbered
10490 register, and the value from the higher address is put into the
10491 higher numbered register, the load will work regardless of whether
10492 the value being loaded is big-wordian or little-wordian. The
10493 order of the two register loads can matter however, if the address
10494 of the memory location is actually held in one of the registers
10495 being overwritten by the load. */
10497 if (GET_CODE (x) != REG || REGNO (x) > LAST_ARM_REGNUM)
10499 output_operand_lossage ("invalid operand for code '%c'", code);
10503 asm_fprintf (stream, "%r", REGNO (x) + (WORDS_BIG_ENDIAN ? 1 : 0));
10507 if (GET_CODE (x) != REG || REGNO (x) > LAST_ARM_REGNUM)
10509 output_operand_lossage ("invalid operand for code '%c'", code);
10513 asm_fprintf (stream, "%r", REGNO (x) + (WORDS_BIG_ENDIAN ? 0 : 1));
10517 if (GET_CODE (x) != REG || REGNO (x) > LAST_ARM_REGNUM)
10519 output_operand_lossage ("invalid operand for code '%c'", code);
10523 asm_fprintf (stream, "%r", REGNO (x) + 1);
10527 asm_fprintf (stream, "%r",
10528 GET_CODE (XEXP (x, 0)) == REG
10529 ? REGNO (XEXP (x, 0)) : REGNO (XEXP (XEXP (x, 0), 0)));
10533 asm_fprintf (stream, "{%r-%r}",
10535 REGNO (x) + ARM_NUM_REGS (GET_MODE (x)) - 1);
10539 /* CONST_TRUE_RTX means always -- that's the default. */
10540 if (x == const_true_rtx)
10543 if (!COMPARISON_P (x))
10545 output_operand_lossage ("invalid operand for code '%c'", code);
10549 fputs (arm_condition_codes[get_arm_condition_code (x)],
10554 /* CONST_TRUE_RTX means not always -- i.e. never. We shouldn't ever
10555 want to do that. */
10556 if (x == const_true_rtx)
10558 output_operand_lossage ("instruction never exectued");
10561 if (!COMPARISON_P (x))
10563 output_operand_lossage ("invalid operand for code '%c'", code);
10567 fputs (arm_condition_codes[ARM_INVERSE_CONDITION_CODE
10568 (get_arm_condition_code (x))],
10572 /* Cirrus registers can be accessed in a variety of ways:
10573 single floating point (f)
10574 double floating point (d)
10576 64bit integer (dx). */
10577 case 'W': /* Cirrus register in F mode. */
10578 case 'X': /* Cirrus register in D mode. */
10579 case 'Y': /* Cirrus register in FX mode. */
10580 case 'Z': /* Cirrus register in DX mode. */
10581 if (GET_CODE (x) != REG || REGNO_REG_CLASS (REGNO (x)) != CIRRUS_REGS)
10584 fprintf (stream, "mv%s%s",
10586 : code == 'X' ? "d"
10587 : code == 'Y' ? "fx" : "dx", reg_names[REGNO (x)] + 2);
10591 /* Print cirrus register in the mode specified by the register's mode. */
10594 int mode = GET_MODE (x);
10596 if (GET_CODE (x) != REG || REGNO_REG_CLASS (REGNO (x)) != CIRRUS_REGS)
10598 output_operand_lossage ("invalid operand for code '%c'", code);
10602 fprintf (stream, "mv%s%s",
10603 mode == DFmode ? "d"
10604 : mode == SImode ? "fx"
10605 : mode == DImode ? "dx"
10606 : "f", reg_names[REGNO (x)] + 2);
10612 if (GET_CODE (x) != REG
10613 || REGNO (x) < FIRST_IWMMXT_GR_REGNUM
10614 || REGNO (x) > LAST_IWMMXT_GR_REGNUM)
10615 /* Bad value for wCG register number. */
10617 output_operand_lossage ("invalid operand for code '%c'", code);
10622 fprintf (stream, "%d", REGNO (x) - FIRST_IWMMXT_GR_REGNUM);
10625 /* Print an iWMMXt control register name. */
10627 if (GET_CODE (x) != CONST_INT
10629 || INTVAL (x) >= 16)
10630 /* Bad value for wC register number. */
10632 output_operand_lossage ("invalid operand for code '%c'", code);
10638 static const char * wc_reg_names [16] =
10640 "wCID", "wCon", "wCSSF", "wCASF",
10641 "wC4", "wC5", "wC6", "wC7",
10642 "wCGR0", "wCGR1", "wCGR2", "wCGR3",
10643 "wC12", "wC13", "wC14", "wC15"
10646 fprintf (stream, wc_reg_names [INTVAL (x)]);
10650 /* Print a VFP double precision register name. */
10653 int mode = GET_MODE (x);
10656 if (mode != DImode && mode != DFmode)
10658 output_operand_lossage ("invalid operand for code '%c'", code);
10662 if (GET_CODE (x) != REG
10663 || !IS_VFP_REGNUM (REGNO (x)))
10665 output_operand_lossage ("invalid operand for code '%c'", code);
10669 num = REGNO(x) - FIRST_VFP_REGNUM;
10672 output_operand_lossage ("invalid operand for code '%c'", code);
10676 fprintf (stream, "d%d", num >> 1);
10683 output_operand_lossage ("missing operand");
10687 if (GET_CODE (x) == REG)
10688 asm_fprintf (stream, "%r", REGNO (x));
10689 else if (GET_CODE (x) == MEM)
10691 output_memory_reference_mode = GET_MODE (x);
10692 output_address (XEXP (x, 0));
10694 else if (GET_CODE (x) == CONST_DOUBLE)
10695 fprintf (stream, "#%s", fp_immediate_constant (x));
10696 else if (GET_CODE (x) == NEG)
10697 abort (); /* This should never happen now. */
10700 fputc ('#', stream);
10701 output_addr_const (stream, x);
10706 #ifndef AOF_ASSEMBLER
10707 /* Target hook for assembling integer objects. The ARM version needs to
10708 handle word-sized values specially. */
10710 arm_assemble_integer (rtx x, unsigned int size, int aligned_p)
10712 if (size == UNITS_PER_WORD && aligned_p)
10714 fputs ("\t.word\t", asm_out_file);
10715 output_addr_const (asm_out_file, x);
10717 /* Mark symbols as position independent. We only do this in the
10718 .text segment, not in the .data segment. */
10719 if (NEED_GOT_RELOC && flag_pic && making_const_table &&
10720 (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == LABEL_REF))
10722 if (GET_CODE (x) == SYMBOL_REF
10723 && (CONSTANT_POOL_ADDRESS_P (x)
10724 || SYMBOL_REF_LOCAL_P (x)))
10725 fputs ("(GOTOFF)", asm_out_file);
10726 else if (GET_CODE (x) == LABEL_REF)
10727 fputs ("(GOTOFF)", asm_out_file);
10729 fputs ("(GOT)", asm_out_file);
10731 fputc ('\n', asm_out_file);
10735 if (arm_vector_mode_supported_p (GET_MODE (x)))
10739 if (GET_CODE (x) != CONST_VECTOR)
10742 units = CONST_VECTOR_NUNITS (x);
10744 switch (GET_MODE (x))
10746 case V2SImode: size = 4; break;
10747 case V4HImode: size = 2; break;
10748 case V8QImode: size = 1; break;
10753 for (i = 0; i < units; i++)
10757 elt = CONST_VECTOR_ELT (x, i);
10759 (elt, size, i == 0 ? BIGGEST_ALIGNMENT : size * BITS_PER_UNIT, 1);
10765 return default_assemble_integer (x, size, aligned_p);
10769 /* A finite state machine takes care of noticing whether or not instructions
10770 can be conditionally executed, and thus decrease execution time and code
10771 size by deleting branch instructions. The fsm is controlled by
10772 final_prescan_insn, and controls the actions of ASM_OUTPUT_OPCODE. */
10774 /* The state of the fsm controlling condition codes are:
10775 0: normal, do nothing special
10776 1: make ASM_OUTPUT_OPCODE not output this instruction
10777 2: make ASM_OUTPUT_OPCODE not output this instruction
10778 3: make instructions conditional
10779 4: make instructions conditional
10781 State transitions (state->state by whom under condition):
10782 0 -> 1 final_prescan_insn if the `target' is a label
10783 0 -> 2 final_prescan_insn if the `target' is an unconditional branch
10784 1 -> 3 ASM_OUTPUT_OPCODE after not having output the conditional branch
10785 2 -> 4 ASM_OUTPUT_OPCODE after not having output the conditional branch
10786 3 -> 0 (*targetm.asm_out.internal_label) if the `target' label is reached
10787 (the target label has CODE_LABEL_NUMBER equal to arm_target_label).
10788 4 -> 0 final_prescan_insn if the `target' unconditional branch is reached
10789 (the target insn is arm_target_insn).
10791 If the jump clobbers the conditions then we use states 2 and 4.
10793 A similar thing can be done with conditional return insns.
10795 XXX In case the `target' is an unconditional branch, this conditionalising
10796 of the instructions always reduces code size, but not always execution
10797 time. But then, I want to reduce the code size to somewhere near what
10798 /bin/cc produces. */
10800 /* Returns the index of the ARM condition code string in
10801 `arm_condition_codes'. COMPARISON should be an rtx like
10802 `(eq (...) (...))'. */
10803 static enum arm_cond_code
10804 get_arm_condition_code (rtx comparison)
10806 enum machine_mode mode = GET_MODE (XEXP (comparison, 0));
10808 enum rtx_code comp_code = GET_CODE (comparison);
10810 if (GET_MODE_CLASS (mode) != MODE_CC)
10811 mode = SELECT_CC_MODE (comp_code, XEXP (comparison, 0),
10812 XEXP (comparison, 1));
10816 case CC_DNEmode: code = ARM_NE; goto dominance;
10817 case CC_DEQmode: code = ARM_EQ; goto dominance;
10818 case CC_DGEmode: code = ARM_GE; goto dominance;
10819 case CC_DGTmode: code = ARM_GT; goto dominance;
10820 case CC_DLEmode: code = ARM_LE; goto dominance;
10821 case CC_DLTmode: code = ARM_LT; goto dominance;
10822 case CC_DGEUmode: code = ARM_CS; goto dominance;
10823 case CC_DGTUmode: code = ARM_HI; goto dominance;
10824 case CC_DLEUmode: code = ARM_LS; goto dominance;
10825 case CC_DLTUmode: code = ARM_CC;
10828 if (comp_code != EQ && comp_code != NE)
10831 if (comp_code == EQ)
10832 return ARM_INVERSE_CONDITION_CODE (code);
10838 case NE: return ARM_NE;
10839 case EQ: return ARM_EQ;
10840 case GE: return ARM_PL;
10841 case LT: return ARM_MI;
10848 case NE: return ARM_NE;
10849 case EQ: return ARM_EQ;
10856 case NE: return ARM_MI;
10857 case EQ: return ARM_PL;
10863 /* These encodings assume that AC=1 in the FPA system control
10864 byte. This allows us to handle all cases except UNEQ and
10868 case GE: return ARM_GE;
10869 case GT: return ARM_GT;
10870 case LE: return ARM_LS;
10871 case LT: return ARM_MI;
10872 case NE: return ARM_NE;
10873 case EQ: return ARM_EQ;
10874 case ORDERED: return ARM_VC;
10875 case UNORDERED: return ARM_VS;
10876 case UNLT: return ARM_LT;
10877 case UNLE: return ARM_LE;
10878 case UNGT: return ARM_HI;
10879 case UNGE: return ARM_PL;
10880 /* UNEQ and LTGT do not have a representation. */
10881 case UNEQ: /* Fall through. */
10882 case LTGT: /* Fall through. */
10889 case NE: return ARM_NE;
10890 case EQ: return ARM_EQ;
10891 case GE: return ARM_LE;
10892 case GT: return ARM_LT;
10893 case LE: return ARM_GE;
10894 case LT: return ARM_GT;
10895 case GEU: return ARM_LS;
10896 case GTU: return ARM_CC;
10897 case LEU: return ARM_CS;
10898 case LTU: return ARM_HI;
10905 case LTU: return ARM_CS;
10906 case GEU: return ARM_CC;
10913 case NE: return ARM_NE;
10914 case EQ: return ARM_EQ;
10915 case GE: return ARM_GE;
10916 case GT: return ARM_GT;
10917 case LE: return ARM_LE;
10918 case LT: return ARM_LT;
10919 case GEU: return ARM_CS;
10920 case GTU: return ARM_HI;
10921 case LEU: return ARM_LS;
10922 case LTU: return ARM_CC;
10933 arm_final_prescan_insn (rtx insn)
10935 /* BODY will hold the body of INSN. */
10936 rtx body = PATTERN (insn);
10938 /* This will be 1 if trying to repeat the trick, and things need to be
10939 reversed if it appears to fail. */
10942 /* JUMP_CLOBBERS will be one implies that the conditions if a branch is
10943 taken are clobbered, even if the rtl suggests otherwise. It also
10944 means that we have to grub around within the jump expression to find
10945 out what the conditions are when the jump isn't taken. */
10946 int jump_clobbers = 0;
10948 /* If we start with a return insn, we only succeed if we find another one. */
10949 int seeking_return = 0;
10951 /* START_INSN will hold the insn from where we start looking. This is the
10952 first insn after the following code_label if REVERSE is true. */
10953 rtx start_insn = insn;
10955 /* If in state 4, check if the target branch is reached, in order to
10956 change back to state 0. */
10957 if (arm_ccfsm_state == 4)
10959 if (insn == arm_target_insn)
10961 arm_target_insn = NULL;
10962 arm_ccfsm_state = 0;
10967 /* If in state 3, it is possible to repeat the trick, if this insn is an
10968 unconditional branch to a label, and immediately following this branch
10969 is the previous target label which is only used once, and the label this
10970 branch jumps to is not too far off. */
10971 if (arm_ccfsm_state == 3)
10973 if (simplejump_p (insn))
10975 start_insn = next_nonnote_insn (start_insn);
10976 if (GET_CODE (start_insn) == BARRIER)
10978 /* XXX Isn't this always a barrier? */
10979 start_insn = next_nonnote_insn (start_insn);
10981 if (GET_CODE (start_insn) == CODE_LABEL
10982 && CODE_LABEL_NUMBER (start_insn) == arm_target_label
10983 && LABEL_NUSES (start_insn) == 1)
10988 else if (GET_CODE (body) == RETURN)
10990 start_insn = next_nonnote_insn (start_insn);
10991 if (GET_CODE (start_insn) == BARRIER)
10992 start_insn = next_nonnote_insn (start_insn);
10993 if (GET_CODE (start_insn) == CODE_LABEL
10994 && CODE_LABEL_NUMBER (start_insn) == arm_target_label
10995 && LABEL_NUSES (start_insn) == 1)
10998 seeking_return = 1;
11007 if (arm_ccfsm_state != 0 && !reverse)
11009 if (GET_CODE (insn) != JUMP_INSN)
11012 /* This jump might be paralleled with a clobber of the condition codes
11013 the jump should always come first */
11014 if (GET_CODE (body) == PARALLEL && XVECLEN (body, 0) > 0)
11015 body = XVECEXP (body, 0, 0);
11018 || (GET_CODE (body) == SET && GET_CODE (SET_DEST (body)) == PC
11019 && GET_CODE (SET_SRC (body)) == IF_THEN_ELSE))
11022 int fail = FALSE, succeed = FALSE;
11023 /* Flag which part of the IF_THEN_ELSE is the LABEL_REF. */
11024 int then_not_else = TRUE;
11025 rtx this_insn = start_insn, label = 0;
11027 /* If the jump cannot be done with one instruction, we cannot
11028 conditionally execute the instruction in the inverse case. */
11029 if (get_attr_conds (insn) == CONDS_JUMP_CLOB)
11035 /* Register the insn jumped to. */
11038 if (!seeking_return)
11039 label = XEXP (SET_SRC (body), 0);
11041 else if (GET_CODE (XEXP (SET_SRC (body), 1)) == LABEL_REF)
11042 label = XEXP (XEXP (SET_SRC (body), 1), 0);
11043 else if (GET_CODE (XEXP (SET_SRC (body), 2)) == LABEL_REF)
11045 label = XEXP (XEXP (SET_SRC (body), 2), 0);
11046 then_not_else = FALSE;
11048 else if (GET_CODE (XEXP (SET_SRC (body), 1)) == RETURN)
11049 seeking_return = 1;
11050 else if (GET_CODE (XEXP (SET_SRC (body), 2)) == RETURN)
11052 seeking_return = 1;
11053 then_not_else = FALSE;
11058 /* See how many insns this branch skips, and what kind of insns. If all
11059 insns are okay, and the label or unconditional branch to the same
11060 label is not too far away, succeed. */
11061 for (insns_skipped = 0;
11062 !fail && !succeed && insns_skipped++ < max_insns_skipped;)
11066 this_insn = next_nonnote_insn (this_insn);
11070 switch (GET_CODE (this_insn))
11073 /* Succeed if it is the target label, otherwise fail since
11074 control falls in from somewhere else. */
11075 if (this_insn == label)
11079 arm_ccfsm_state = 2;
11080 this_insn = next_nonnote_insn (this_insn);
11083 arm_ccfsm_state = 1;
11091 /* Succeed if the following insn is the target label.
11093 If return insns are used then the last insn in a function
11094 will be a barrier. */
11095 this_insn = next_nonnote_insn (this_insn);
11096 if (this_insn && this_insn == label)
11100 arm_ccfsm_state = 2;
11101 this_insn = next_nonnote_insn (this_insn);
11104 arm_ccfsm_state = 1;
11112 /* The AAPCS says that conditional calls should not be
11113 used since they make interworking inefficient (the
11114 linker can't transform BL<cond> into BLX). That's
11115 only a problem if the machine has BLX. */
11122 /* Succeed if the following insn is the target label, or
11123 if the following two insns are a barrier and the
11125 this_insn = next_nonnote_insn (this_insn);
11126 if (this_insn && GET_CODE (this_insn) == BARRIER)
11127 this_insn = next_nonnote_insn (this_insn);
11129 if (this_insn && this_insn == label
11130 && insns_skipped < max_insns_skipped)
11134 arm_ccfsm_state = 2;
11135 this_insn = next_nonnote_insn (this_insn);
11138 arm_ccfsm_state = 1;
11146 /* If this is an unconditional branch to the same label, succeed.
11147 If it is to another label, do nothing. If it is conditional,
11149 /* XXX Probably, the tests for SET and the PC are
11152 scanbody = PATTERN (this_insn);
11153 if (GET_CODE (scanbody) == SET
11154 && GET_CODE (SET_DEST (scanbody)) == PC)
11156 if (GET_CODE (SET_SRC (scanbody)) == LABEL_REF
11157 && XEXP (SET_SRC (scanbody), 0) == label && !reverse)
11159 arm_ccfsm_state = 2;
11162 else if (GET_CODE (SET_SRC (scanbody)) == IF_THEN_ELSE)
11165 /* Fail if a conditional return is undesirable (e.g. on a
11166 StrongARM), but still allow this if optimizing for size. */
11167 else if (GET_CODE (scanbody) == RETURN
11168 && !use_return_insn (TRUE, NULL)
11171 else if (GET_CODE (scanbody) == RETURN
11174 arm_ccfsm_state = 2;
11177 else if (GET_CODE (scanbody) == PARALLEL)
11179 switch (get_attr_conds (this_insn))
11189 fail = TRUE; /* Unrecognized jump (e.g. epilogue). */
11194 /* Instructions using or affecting the condition codes make it
11196 scanbody = PATTERN (this_insn);
11197 if (!(GET_CODE (scanbody) == SET
11198 || GET_CODE (scanbody) == PARALLEL)
11199 || get_attr_conds (this_insn) != CONDS_NOCOND)
11202 /* A conditional cirrus instruction must be followed by
11203 a non Cirrus instruction. However, since we
11204 conditionalize instructions in this function and by
11205 the time we get here we can't add instructions
11206 (nops), because shorten_branches() has already been
11207 called, we will disable conditionalizing Cirrus
11208 instructions to be safe. */
11209 if (GET_CODE (scanbody) != USE
11210 && GET_CODE (scanbody) != CLOBBER
11211 && get_attr_cirrus (this_insn) != CIRRUS_NOT)
11221 if ((!seeking_return) && (arm_ccfsm_state == 1 || reverse))
11222 arm_target_label = CODE_LABEL_NUMBER (label);
11223 else if (seeking_return || arm_ccfsm_state == 2)
11225 while (this_insn && GET_CODE (PATTERN (this_insn)) == USE)
11227 this_insn = next_nonnote_insn (this_insn);
11228 if (this_insn && (GET_CODE (this_insn) == BARRIER
11229 || GET_CODE (this_insn) == CODE_LABEL))
11234 /* Oh, dear! we ran off the end.. give up. */
11235 recog (PATTERN (insn), insn, NULL);
11236 arm_ccfsm_state = 0;
11237 arm_target_insn = NULL;
11240 arm_target_insn = this_insn;
11249 get_arm_condition_code (XEXP (XEXP (XEXP (SET_SRC (body),
11251 if (GET_CODE (XEXP (XEXP (SET_SRC (body), 0), 0)) == AND)
11252 arm_current_cc = ARM_INVERSE_CONDITION_CODE (arm_current_cc);
11253 if (GET_CODE (XEXP (SET_SRC (body), 0)) == NE)
11254 arm_current_cc = ARM_INVERSE_CONDITION_CODE (arm_current_cc);
11258 /* If REVERSE is true, ARM_CURRENT_CC needs to be inverted from
11261 arm_current_cc = get_arm_condition_code (XEXP (SET_SRC (body),
11265 if (reverse || then_not_else)
11266 arm_current_cc = ARM_INVERSE_CONDITION_CODE (arm_current_cc);
11269 /* Restore recog_data (getting the attributes of other insns can
11270 destroy this array, but final.c assumes that it remains intact
11271 across this call; since the insn has been recognized already we
11272 call recog direct). */
11273 recog (PATTERN (insn), insn, NULL);
11277 /* Returns true if REGNO is a valid register
11278 for holding a quantity of type MODE. */
11280 arm_hard_regno_mode_ok (unsigned int regno, enum machine_mode mode)
11282 if (GET_MODE_CLASS (mode) == MODE_CC)
11283 return regno == CC_REGNUM || regno == VFPCC_REGNUM;
11286 /* For the Thumb we only allow values bigger than SImode in
11287 registers 0 - 6, so that there is always a second low
11288 register available to hold the upper part of the value.
11289 We probably we ought to ensure that the register is the
11290 start of an even numbered register pair. */
11291 return (ARM_NUM_REGS (mode) < 2) || (regno < LAST_LO_REGNUM);
11293 if (IS_CIRRUS_REGNUM (regno))
11294 /* We have outlawed SI values in Cirrus registers because they
11295 reside in the lower 32 bits, but SF values reside in the
11296 upper 32 bits. This causes gcc all sorts of grief. We can't
11297 even split the registers into pairs because Cirrus SI values
11298 get sign extended to 64bits-- aldyh. */
11299 return (GET_MODE_CLASS (mode) == MODE_FLOAT) || (mode == DImode);
11301 if (IS_VFP_REGNUM (regno))
11303 if (mode == SFmode || mode == SImode)
11306 /* DFmode values are only valid in even register pairs. */
11307 if (mode == DFmode)
11308 return ((regno - FIRST_VFP_REGNUM) & 1) == 0;
11312 if (IS_IWMMXT_GR_REGNUM (regno))
11313 return mode == SImode;
11315 if (IS_IWMMXT_REGNUM (regno))
11316 return VALID_IWMMXT_REG_MODE (mode);
11318 /* We allow any value to be stored in the general registers.
11319 Restrict doubleword quantities to even register pairs so that we can
11321 if (regno <= LAST_ARM_REGNUM)
11322 return !(TARGET_LDRD && GET_MODE_SIZE (mode) > 4 && (regno & 1) != 0);
11324 if ( regno == FRAME_POINTER_REGNUM
11325 || regno == ARG_POINTER_REGNUM)
11326 /* We only allow integers in the fake hard registers. */
11327 return GET_MODE_CLASS (mode) == MODE_INT;
11329 /* The only registers left are the FPA registers
11330 which we only allow to hold FP values. */
11331 return GET_MODE_CLASS (mode) == MODE_FLOAT
11332 && regno >= FIRST_FPA_REGNUM
11333 && regno <= LAST_FPA_REGNUM;
11337 arm_regno_class (int regno)
11341 if (regno == STACK_POINTER_REGNUM)
11343 if (regno == CC_REGNUM)
11350 if ( regno <= LAST_ARM_REGNUM
11351 || regno == FRAME_POINTER_REGNUM
11352 || regno == ARG_POINTER_REGNUM)
11353 return GENERAL_REGS;
11355 if (regno == CC_REGNUM || regno == VFPCC_REGNUM)
11358 if (IS_CIRRUS_REGNUM (regno))
11359 return CIRRUS_REGS;
11361 if (IS_VFP_REGNUM (regno))
11364 if (IS_IWMMXT_REGNUM (regno))
11365 return IWMMXT_REGS;
11367 if (IS_IWMMXT_GR_REGNUM (regno))
11368 return IWMMXT_GR_REGS;
11373 /* Handle a special case when computing the offset
11374 of an argument from the frame pointer. */
11376 arm_debugger_arg_offset (int value, rtx addr)
11380 /* We are only interested if dbxout_parms() failed to compute the offset. */
11384 /* We can only cope with the case where the address is held in a register. */
11385 if (GET_CODE (addr) != REG)
11388 /* If we are using the frame pointer to point at the argument, then
11389 an offset of 0 is correct. */
11390 if (REGNO (addr) == (unsigned) HARD_FRAME_POINTER_REGNUM)
11393 /* If we are using the stack pointer to point at the
11394 argument, then an offset of 0 is correct. */
11395 if ((TARGET_THUMB || !frame_pointer_needed)
11396 && REGNO (addr) == SP_REGNUM)
11399 /* Oh dear. The argument is pointed to by a register rather
11400 than being held in a register, or being stored at a known
11401 offset from the frame pointer. Since GDB only understands
11402 those two kinds of argument we must translate the address
11403 held in the register into an offset from the frame pointer.
11404 We do this by searching through the insns for the function
11405 looking to see where this register gets its value. If the
11406 register is initialized from the frame pointer plus an offset
11407 then we are in luck and we can continue, otherwise we give up.
11409 This code is exercised by producing debugging information
11410 for a function with arguments like this:
11412 double func (double a, double b, int c, double d) {return d;}
11414 Without this code the stab for parameter 'd' will be set to
11415 an offset of 0 from the frame pointer, rather than 8. */
11417 /* The if() statement says:
11419 If the insn is a normal instruction
11420 and if the insn is setting the value in a register
11421 and if the register being set is the register holding the address of the argument
11422 and if the address is computing by an addition
11423 that involves adding to a register
11424 which is the frame pointer
11429 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
11431 if ( GET_CODE (insn) == INSN
11432 && GET_CODE (PATTERN (insn)) == SET
11433 && REGNO (XEXP (PATTERN (insn), 0)) == REGNO (addr)
11434 && GET_CODE (XEXP (PATTERN (insn), 1)) == PLUS
11435 && GET_CODE (XEXP (XEXP (PATTERN (insn), 1), 0)) == REG
11436 && REGNO (XEXP (XEXP (PATTERN (insn), 1), 0)) == (unsigned) HARD_FRAME_POINTER_REGNUM
11437 && GET_CODE (XEXP (XEXP (PATTERN (insn), 1), 1)) == CONST_INT
11440 value = INTVAL (XEXP (XEXP (PATTERN (insn), 1), 1));
11449 warning ("unable to compute real location of stacked parameter");
11450 value = 8; /* XXX magic hack */
11456 #define def_mbuiltin(MASK, NAME, TYPE, CODE) \
11459 if ((MASK) & insn_flags) \
11460 lang_hooks.builtin_function ((NAME), (TYPE), (CODE), \
11461 BUILT_IN_MD, NULL, NULL_TREE); \
11465 struct builtin_description
11467 const unsigned int mask;
11468 const enum insn_code icode;
11469 const char * const name;
11470 const enum arm_builtins code;
11471 const enum rtx_code comparison;
11472 const unsigned int flag;
11475 static const struct builtin_description bdesc_2arg[] =
11477 #define IWMMXT_BUILTIN(code, string, builtin) \
11478 { FL_IWMMXT, CODE_FOR_##code, "__builtin_arm_" string, \
11479 ARM_BUILTIN_##builtin, 0, 0 },
11481 IWMMXT_BUILTIN (addv8qi3, "waddb", WADDB)
11482 IWMMXT_BUILTIN (addv4hi3, "waddh", WADDH)
11483 IWMMXT_BUILTIN (addv2si3, "waddw", WADDW)
11484 IWMMXT_BUILTIN (subv8qi3, "wsubb", WSUBB)
11485 IWMMXT_BUILTIN (subv4hi3, "wsubh", WSUBH)
11486 IWMMXT_BUILTIN (subv2si3, "wsubw", WSUBW)
11487 IWMMXT_BUILTIN (ssaddv8qi3, "waddbss", WADDSSB)
11488 IWMMXT_BUILTIN (ssaddv4hi3, "waddhss", WADDSSH)
11489 IWMMXT_BUILTIN (ssaddv2si3, "waddwss", WADDSSW)
11490 IWMMXT_BUILTIN (sssubv8qi3, "wsubbss", WSUBSSB)
11491 IWMMXT_BUILTIN (sssubv4hi3, "wsubhss", WSUBSSH)
11492 IWMMXT_BUILTIN (sssubv2si3, "wsubwss", WSUBSSW)
11493 IWMMXT_BUILTIN (usaddv8qi3, "waddbus", WADDUSB)
11494 IWMMXT_BUILTIN (usaddv4hi3, "waddhus", WADDUSH)
11495 IWMMXT_BUILTIN (usaddv2si3, "waddwus", WADDUSW)
11496 IWMMXT_BUILTIN (ussubv8qi3, "wsubbus", WSUBUSB)
11497 IWMMXT_BUILTIN (ussubv4hi3, "wsubhus", WSUBUSH)
11498 IWMMXT_BUILTIN (ussubv2si3, "wsubwus", WSUBUSW)
11499 IWMMXT_BUILTIN (mulv4hi3, "wmulul", WMULUL)
11500 IWMMXT_BUILTIN (smulv4hi3_highpart, "wmulsm", WMULSM)
11501 IWMMXT_BUILTIN (umulv4hi3_highpart, "wmulum", WMULUM)
11502 IWMMXT_BUILTIN (eqv8qi3, "wcmpeqb", WCMPEQB)
11503 IWMMXT_BUILTIN (eqv4hi3, "wcmpeqh", WCMPEQH)
11504 IWMMXT_BUILTIN (eqv2si3, "wcmpeqw", WCMPEQW)
11505 IWMMXT_BUILTIN (gtuv8qi3, "wcmpgtub", WCMPGTUB)
11506 IWMMXT_BUILTIN (gtuv4hi3, "wcmpgtuh", WCMPGTUH)
11507 IWMMXT_BUILTIN (gtuv2si3, "wcmpgtuw", WCMPGTUW)
11508 IWMMXT_BUILTIN (gtv8qi3, "wcmpgtsb", WCMPGTSB)
11509 IWMMXT_BUILTIN (gtv4hi3, "wcmpgtsh", WCMPGTSH)
11510 IWMMXT_BUILTIN (gtv2si3, "wcmpgtsw", WCMPGTSW)
11511 IWMMXT_BUILTIN (umaxv8qi3, "wmaxub", WMAXUB)
11512 IWMMXT_BUILTIN (smaxv8qi3, "wmaxsb", WMAXSB)
11513 IWMMXT_BUILTIN (umaxv4hi3, "wmaxuh", WMAXUH)
11514 IWMMXT_BUILTIN (smaxv4hi3, "wmaxsh", WMAXSH)
11515 IWMMXT_BUILTIN (umaxv2si3, "wmaxuw", WMAXUW)
11516 IWMMXT_BUILTIN (smaxv2si3, "wmaxsw", WMAXSW)
11517 IWMMXT_BUILTIN (uminv8qi3, "wminub", WMINUB)
11518 IWMMXT_BUILTIN (sminv8qi3, "wminsb", WMINSB)
11519 IWMMXT_BUILTIN (uminv4hi3, "wminuh", WMINUH)
11520 IWMMXT_BUILTIN (sminv4hi3, "wminsh", WMINSH)
11521 IWMMXT_BUILTIN (uminv2si3, "wminuw", WMINUW)
11522 IWMMXT_BUILTIN (sminv2si3, "wminsw", WMINSW)
11523 IWMMXT_BUILTIN (iwmmxt_anddi3, "wand", WAND)
11524 IWMMXT_BUILTIN (iwmmxt_nanddi3, "wandn", WANDN)
11525 IWMMXT_BUILTIN (iwmmxt_iordi3, "wor", WOR)
11526 IWMMXT_BUILTIN (iwmmxt_xordi3, "wxor", WXOR)
11527 IWMMXT_BUILTIN (iwmmxt_uavgv8qi3, "wavg2b", WAVG2B)
11528 IWMMXT_BUILTIN (iwmmxt_uavgv4hi3, "wavg2h", WAVG2H)
11529 IWMMXT_BUILTIN (iwmmxt_uavgrndv8qi3, "wavg2br", WAVG2BR)
11530 IWMMXT_BUILTIN (iwmmxt_uavgrndv4hi3, "wavg2hr", WAVG2HR)
11531 IWMMXT_BUILTIN (iwmmxt_wunpckilb, "wunpckilb", WUNPCKILB)
11532 IWMMXT_BUILTIN (iwmmxt_wunpckilh, "wunpckilh", WUNPCKILH)
11533 IWMMXT_BUILTIN (iwmmxt_wunpckilw, "wunpckilw", WUNPCKILW)
11534 IWMMXT_BUILTIN (iwmmxt_wunpckihb, "wunpckihb", WUNPCKIHB)
11535 IWMMXT_BUILTIN (iwmmxt_wunpckihh, "wunpckihh", WUNPCKIHH)
11536 IWMMXT_BUILTIN (iwmmxt_wunpckihw, "wunpckihw", WUNPCKIHW)
11537 IWMMXT_BUILTIN (iwmmxt_wmadds, "wmadds", WMADDS)
11538 IWMMXT_BUILTIN (iwmmxt_wmaddu, "wmaddu", WMADDU)
11540 #define IWMMXT_BUILTIN2(code, builtin) \
11541 { FL_IWMMXT, CODE_FOR_##code, NULL, ARM_BUILTIN_##builtin, 0, 0 },
11543 IWMMXT_BUILTIN2 (iwmmxt_wpackhss, WPACKHSS)
11544 IWMMXT_BUILTIN2 (iwmmxt_wpackwss, WPACKWSS)
11545 IWMMXT_BUILTIN2 (iwmmxt_wpackdss, WPACKDSS)
11546 IWMMXT_BUILTIN2 (iwmmxt_wpackhus, WPACKHUS)
11547 IWMMXT_BUILTIN2 (iwmmxt_wpackwus, WPACKWUS)
11548 IWMMXT_BUILTIN2 (iwmmxt_wpackdus, WPACKDUS)
11549 IWMMXT_BUILTIN2 (ashlv4hi3_di, WSLLH)
11550 IWMMXT_BUILTIN2 (ashlv4hi3, WSLLHI)
11551 IWMMXT_BUILTIN2 (ashlv2si3_di, WSLLW)
11552 IWMMXT_BUILTIN2 (ashlv2si3, WSLLWI)
11553 IWMMXT_BUILTIN2 (ashldi3_di, WSLLD)
11554 IWMMXT_BUILTIN2 (ashldi3_iwmmxt, WSLLDI)
11555 IWMMXT_BUILTIN2 (lshrv4hi3_di, WSRLH)
11556 IWMMXT_BUILTIN2 (lshrv4hi3, WSRLHI)
11557 IWMMXT_BUILTIN2 (lshrv2si3_di, WSRLW)
11558 IWMMXT_BUILTIN2 (lshrv2si3, WSRLWI)
11559 IWMMXT_BUILTIN2 (lshrdi3_di, WSRLD)
11560 IWMMXT_BUILTIN2 (lshrdi3_iwmmxt, WSRLDI)
11561 IWMMXT_BUILTIN2 (ashrv4hi3_di, WSRAH)
11562 IWMMXT_BUILTIN2 (ashrv4hi3, WSRAHI)
11563 IWMMXT_BUILTIN2 (ashrv2si3_di, WSRAW)
11564 IWMMXT_BUILTIN2 (ashrv2si3, WSRAWI)
11565 IWMMXT_BUILTIN2 (ashrdi3_di, WSRAD)
11566 IWMMXT_BUILTIN2 (ashrdi3_iwmmxt, WSRADI)
11567 IWMMXT_BUILTIN2 (rorv4hi3_di, WRORH)
11568 IWMMXT_BUILTIN2 (rorv4hi3, WRORHI)
11569 IWMMXT_BUILTIN2 (rorv2si3_di, WRORW)
11570 IWMMXT_BUILTIN2 (rorv2si3, WRORWI)
11571 IWMMXT_BUILTIN2 (rordi3_di, WRORD)
11572 IWMMXT_BUILTIN2 (rordi3, WRORDI)
11573 IWMMXT_BUILTIN2 (iwmmxt_wmacuz, WMACUZ)
11574 IWMMXT_BUILTIN2 (iwmmxt_wmacsz, WMACSZ)
11577 static const struct builtin_description bdesc_1arg[] =
11579 IWMMXT_BUILTIN (iwmmxt_tmovmskb, "tmovmskb", TMOVMSKB)
11580 IWMMXT_BUILTIN (iwmmxt_tmovmskh, "tmovmskh", TMOVMSKH)
11581 IWMMXT_BUILTIN (iwmmxt_tmovmskw, "tmovmskw", TMOVMSKW)
11582 IWMMXT_BUILTIN (iwmmxt_waccb, "waccb", WACCB)
11583 IWMMXT_BUILTIN (iwmmxt_wacch, "wacch", WACCH)
11584 IWMMXT_BUILTIN (iwmmxt_waccw, "waccw", WACCW)
11585 IWMMXT_BUILTIN (iwmmxt_wunpckehub, "wunpckehub", WUNPCKEHUB)
11586 IWMMXT_BUILTIN (iwmmxt_wunpckehuh, "wunpckehuh", WUNPCKEHUH)
11587 IWMMXT_BUILTIN (iwmmxt_wunpckehuw, "wunpckehuw", WUNPCKEHUW)
11588 IWMMXT_BUILTIN (iwmmxt_wunpckehsb, "wunpckehsb", WUNPCKEHSB)
11589 IWMMXT_BUILTIN (iwmmxt_wunpckehsh, "wunpckehsh", WUNPCKEHSH)
11590 IWMMXT_BUILTIN (iwmmxt_wunpckehsw, "wunpckehsw", WUNPCKEHSW)
11591 IWMMXT_BUILTIN (iwmmxt_wunpckelub, "wunpckelub", WUNPCKELUB)
11592 IWMMXT_BUILTIN (iwmmxt_wunpckeluh, "wunpckeluh", WUNPCKELUH)
11593 IWMMXT_BUILTIN (iwmmxt_wunpckeluw, "wunpckeluw", WUNPCKELUW)
11594 IWMMXT_BUILTIN (iwmmxt_wunpckelsb, "wunpckelsb", WUNPCKELSB)
11595 IWMMXT_BUILTIN (iwmmxt_wunpckelsh, "wunpckelsh", WUNPCKELSH)
11596 IWMMXT_BUILTIN (iwmmxt_wunpckelsw, "wunpckelsw", WUNPCKELSW)
11599 /* Set up all the iWMMXt builtins. This is
11600 not called if TARGET_IWMMXT is zero. */
11603 arm_init_iwmmxt_builtins (void)
11605 const struct builtin_description * d;
11607 tree endlink = void_list_node;
11609 tree V2SI_type_node = build_vector_type_for_mode (intSI_type_node, V2SImode);
11610 tree V4HI_type_node = build_vector_type_for_mode (intHI_type_node, V4HImode);
11611 tree V8QI_type_node = build_vector_type_for_mode (intQI_type_node, V8QImode);
11614 = build_function_type (integer_type_node,
11615 tree_cons (NULL_TREE, integer_type_node, endlink));
11616 tree v8qi_ftype_v8qi_v8qi_int
11617 = build_function_type (V8QI_type_node,
11618 tree_cons (NULL_TREE, V8QI_type_node,
11619 tree_cons (NULL_TREE, V8QI_type_node,
11620 tree_cons (NULL_TREE,
11623 tree v4hi_ftype_v4hi_int
11624 = build_function_type (V4HI_type_node,
11625 tree_cons (NULL_TREE, V4HI_type_node,
11626 tree_cons (NULL_TREE, integer_type_node,
11628 tree v2si_ftype_v2si_int
11629 = build_function_type (V2SI_type_node,
11630 tree_cons (NULL_TREE, V2SI_type_node,
11631 tree_cons (NULL_TREE, integer_type_node,
11633 tree v2si_ftype_di_di
11634 = build_function_type (V2SI_type_node,
11635 tree_cons (NULL_TREE, long_long_integer_type_node,
11636 tree_cons (NULL_TREE, long_long_integer_type_node,
11638 tree di_ftype_di_int
11639 = build_function_type (long_long_integer_type_node,
11640 tree_cons (NULL_TREE, long_long_integer_type_node,
11641 tree_cons (NULL_TREE, integer_type_node,
11643 tree di_ftype_di_int_int
11644 = build_function_type (long_long_integer_type_node,
11645 tree_cons (NULL_TREE, long_long_integer_type_node,
11646 tree_cons (NULL_TREE, integer_type_node,
11647 tree_cons (NULL_TREE,
11650 tree int_ftype_v8qi
11651 = build_function_type (integer_type_node,
11652 tree_cons (NULL_TREE, V8QI_type_node,
11654 tree int_ftype_v4hi
11655 = build_function_type (integer_type_node,
11656 tree_cons (NULL_TREE, V4HI_type_node,
11658 tree int_ftype_v2si
11659 = build_function_type (integer_type_node,
11660 tree_cons (NULL_TREE, V2SI_type_node,
11662 tree int_ftype_v8qi_int
11663 = build_function_type (integer_type_node,
11664 tree_cons (NULL_TREE, V8QI_type_node,
11665 tree_cons (NULL_TREE, integer_type_node,
11667 tree int_ftype_v4hi_int
11668 = build_function_type (integer_type_node,
11669 tree_cons (NULL_TREE, V4HI_type_node,
11670 tree_cons (NULL_TREE, integer_type_node,
11672 tree int_ftype_v2si_int
11673 = build_function_type (integer_type_node,
11674 tree_cons (NULL_TREE, V2SI_type_node,
11675 tree_cons (NULL_TREE, integer_type_node,
11677 tree v8qi_ftype_v8qi_int_int
11678 = build_function_type (V8QI_type_node,
11679 tree_cons (NULL_TREE, V8QI_type_node,
11680 tree_cons (NULL_TREE, integer_type_node,
11681 tree_cons (NULL_TREE,
11684 tree v4hi_ftype_v4hi_int_int
11685 = build_function_type (V4HI_type_node,
11686 tree_cons (NULL_TREE, V4HI_type_node,
11687 tree_cons (NULL_TREE, integer_type_node,
11688 tree_cons (NULL_TREE,
11691 tree v2si_ftype_v2si_int_int
11692 = build_function_type (V2SI_type_node,
11693 tree_cons (NULL_TREE, V2SI_type_node,
11694 tree_cons (NULL_TREE, integer_type_node,
11695 tree_cons (NULL_TREE,
11698 /* Miscellaneous. */
11699 tree v8qi_ftype_v4hi_v4hi
11700 = build_function_type (V8QI_type_node,
11701 tree_cons (NULL_TREE, V4HI_type_node,
11702 tree_cons (NULL_TREE, V4HI_type_node,
11704 tree v4hi_ftype_v2si_v2si
11705 = build_function_type (V4HI_type_node,
11706 tree_cons (NULL_TREE, V2SI_type_node,
11707 tree_cons (NULL_TREE, V2SI_type_node,
11709 tree v2si_ftype_v4hi_v4hi
11710 = build_function_type (V2SI_type_node,
11711 tree_cons (NULL_TREE, V4HI_type_node,
11712 tree_cons (NULL_TREE, V4HI_type_node,
11714 tree v2si_ftype_v8qi_v8qi
11715 = build_function_type (V2SI_type_node,
11716 tree_cons (NULL_TREE, V8QI_type_node,
11717 tree_cons (NULL_TREE, V8QI_type_node,
11719 tree v4hi_ftype_v4hi_di
11720 = build_function_type (V4HI_type_node,
11721 tree_cons (NULL_TREE, V4HI_type_node,
11722 tree_cons (NULL_TREE,
11723 long_long_integer_type_node,
11725 tree v2si_ftype_v2si_di
11726 = build_function_type (V2SI_type_node,
11727 tree_cons (NULL_TREE, V2SI_type_node,
11728 tree_cons (NULL_TREE,
11729 long_long_integer_type_node,
11731 tree void_ftype_int_int
11732 = build_function_type (void_type_node,
11733 tree_cons (NULL_TREE, integer_type_node,
11734 tree_cons (NULL_TREE, integer_type_node,
11737 = build_function_type (long_long_unsigned_type_node, endlink);
11739 = build_function_type (long_long_integer_type_node,
11740 tree_cons (NULL_TREE, V8QI_type_node,
11743 = build_function_type (long_long_integer_type_node,
11744 tree_cons (NULL_TREE, V4HI_type_node,
11747 = build_function_type (long_long_integer_type_node,
11748 tree_cons (NULL_TREE, V2SI_type_node,
11750 tree v2si_ftype_v4hi
11751 = build_function_type (V2SI_type_node,
11752 tree_cons (NULL_TREE, V4HI_type_node,
11754 tree v4hi_ftype_v8qi
11755 = build_function_type (V4HI_type_node,
11756 tree_cons (NULL_TREE, V8QI_type_node,
11759 tree di_ftype_di_v4hi_v4hi
11760 = build_function_type (long_long_unsigned_type_node,
11761 tree_cons (NULL_TREE,
11762 long_long_unsigned_type_node,
11763 tree_cons (NULL_TREE, V4HI_type_node,
11764 tree_cons (NULL_TREE,
11768 tree di_ftype_v4hi_v4hi
11769 = build_function_type (long_long_unsigned_type_node,
11770 tree_cons (NULL_TREE, V4HI_type_node,
11771 tree_cons (NULL_TREE, V4HI_type_node,
11774 /* Normal vector binops. */
11775 tree v8qi_ftype_v8qi_v8qi
11776 = build_function_type (V8QI_type_node,
11777 tree_cons (NULL_TREE, V8QI_type_node,
11778 tree_cons (NULL_TREE, V8QI_type_node,
11780 tree v4hi_ftype_v4hi_v4hi
11781 = build_function_type (V4HI_type_node,
11782 tree_cons (NULL_TREE, V4HI_type_node,
11783 tree_cons (NULL_TREE, V4HI_type_node,
11785 tree v2si_ftype_v2si_v2si
11786 = build_function_type (V2SI_type_node,
11787 tree_cons (NULL_TREE, V2SI_type_node,
11788 tree_cons (NULL_TREE, V2SI_type_node,
11790 tree di_ftype_di_di
11791 = build_function_type (long_long_unsigned_type_node,
11792 tree_cons (NULL_TREE, long_long_unsigned_type_node,
11793 tree_cons (NULL_TREE,
11794 long_long_unsigned_type_node,
11797 /* Add all builtins that are more or less simple operations on two
11799 for (i = 0, d = bdesc_2arg; i < ARRAY_SIZE (bdesc_2arg); i++, d++)
11801 /* Use one of the operands; the target can have a different mode for
11802 mask-generating compares. */
11803 enum machine_mode mode;
11809 mode = insn_data[d->icode].operand[1].mode;
11814 type = v8qi_ftype_v8qi_v8qi;
11817 type = v4hi_ftype_v4hi_v4hi;
11820 type = v2si_ftype_v2si_v2si;
11823 type = di_ftype_di_di;
11830 def_mbuiltin (d->mask, d->name, type, d->code);
11833 /* Add the remaining MMX insns with somewhat more complicated types. */
11834 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wzero", di_ftype_void, ARM_BUILTIN_WZERO);
11835 def_mbuiltin (FL_IWMMXT, "__builtin_arm_setwcx", void_ftype_int_int, ARM_BUILTIN_SETWCX);
11836 def_mbuiltin (FL_IWMMXT, "__builtin_arm_getwcx", int_ftype_int, ARM_BUILTIN_GETWCX);
11838 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsllh", v4hi_ftype_v4hi_di, ARM_BUILTIN_WSLLH);
11839 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsllw", v2si_ftype_v2si_di, ARM_BUILTIN_WSLLW);
11840 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wslld", di_ftype_di_di, ARM_BUILTIN_WSLLD);
11841 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsllhi", v4hi_ftype_v4hi_int, ARM_BUILTIN_WSLLHI);
11842 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsllwi", v2si_ftype_v2si_int, ARM_BUILTIN_WSLLWI);
11843 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wslldi", di_ftype_di_int, ARM_BUILTIN_WSLLDI);
11845 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrlh", v4hi_ftype_v4hi_di, ARM_BUILTIN_WSRLH);
11846 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrlw", v2si_ftype_v2si_di, ARM_BUILTIN_WSRLW);
11847 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrld", di_ftype_di_di, ARM_BUILTIN_WSRLD);
11848 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrlhi", v4hi_ftype_v4hi_int, ARM_BUILTIN_WSRLHI);
11849 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrlwi", v2si_ftype_v2si_int, ARM_BUILTIN_WSRLWI);
11850 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrldi", di_ftype_di_int, ARM_BUILTIN_WSRLDI);
11852 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrah", v4hi_ftype_v4hi_di, ARM_BUILTIN_WSRAH);
11853 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsraw", v2si_ftype_v2si_di, ARM_BUILTIN_WSRAW);
11854 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrad", di_ftype_di_di, ARM_BUILTIN_WSRAD);
11855 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrahi", v4hi_ftype_v4hi_int, ARM_BUILTIN_WSRAHI);
11856 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrawi", v2si_ftype_v2si_int, ARM_BUILTIN_WSRAWI);
11857 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsradi", di_ftype_di_int, ARM_BUILTIN_WSRADI);
11859 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wrorh", v4hi_ftype_v4hi_di, ARM_BUILTIN_WRORH);
11860 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wrorw", v2si_ftype_v2si_di, ARM_BUILTIN_WRORW);
11861 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wrord", di_ftype_di_di, ARM_BUILTIN_WRORD);
11862 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wrorhi", v4hi_ftype_v4hi_int, ARM_BUILTIN_WRORHI);
11863 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wrorwi", v2si_ftype_v2si_int, ARM_BUILTIN_WRORWI);
11864 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wrordi", di_ftype_di_int, ARM_BUILTIN_WRORDI);
11866 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wshufh", v4hi_ftype_v4hi_int, ARM_BUILTIN_WSHUFH);
11868 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsadb", v2si_ftype_v8qi_v8qi, ARM_BUILTIN_WSADB);
11869 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsadh", v2si_ftype_v4hi_v4hi, ARM_BUILTIN_WSADH);
11870 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsadbz", v2si_ftype_v8qi_v8qi, ARM_BUILTIN_WSADBZ);
11871 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsadhz", v2si_ftype_v4hi_v4hi, ARM_BUILTIN_WSADHZ);
11873 def_mbuiltin (FL_IWMMXT, "__builtin_arm_textrmsb", int_ftype_v8qi_int, ARM_BUILTIN_TEXTRMSB);
11874 def_mbuiltin (FL_IWMMXT, "__builtin_arm_textrmsh", int_ftype_v4hi_int, ARM_BUILTIN_TEXTRMSH);
11875 def_mbuiltin (FL_IWMMXT, "__builtin_arm_textrmsw", int_ftype_v2si_int, ARM_BUILTIN_TEXTRMSW);
11876 def_mbuiltin (FL_IWMMXT, "__builtin_arm_textrmub", int_ftype_v8qi_int, ARM_BUILTIN_TEXTRMUB);
11877 def_mbuiltin (FL_IWMMXT, "__builtin_arm_textrmuh", int_ftype_v4hi_int, ARM_BUILTIN_TEXTRMUH);
11878 def_mbuiltin (FL_IWMMXT, "__builtin_arm_textrmuw", int_ftype_v2si_int, ARM_BUILTIN_TEXTRMUW);
11879 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tinsrb", v8qi_ftype_v8qi_int_int, ARM_BUILTIN_TINSRB);
11880 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tinsrh", v4hi_ftype_v4hi_int_int, ARM_BUILTIN_TINSRH);
11881 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tinsrw", v2si_ftype_v2si_int_int, ARM_BUILTIN_TINSRW);
11883 def_mbuiltin (FL_IWMMXT, "__builtin_arm_waccb", di_ftype_v8qi, ARM_BUILTIN_WACCB);
11884 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wacch", di_ftype_v4hi, ARM_BUILTIN_WACCH);
11885 def_mbuiltin (FL_IWMMXT, "__builtin_arm_waccw", di_ftype_v2si, ARM_BUILTIN_WACCW);
11887 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmovmskb", int_ftype_v8qi, ARM_BUILTIN_TMOVMSKB);
11888 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmovmskh", int_ftype_v4hi, ARM_BUILTIN_TMOVMSKH);
11889 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmovmskw", int_ftype_v2si, ARM_BUILTIN_TMOVMSKW);
11891 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wpackhss", v8qi_ftype_v4hi_v4hi, ARM_BUILTIN_WPACKHSS);
11892 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wpackhus", v8qi_ftype_v4hi_v4hi, ARM_BUILTIN_WPACKHUS);
11893 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wpackwus", v4hi_ftype_v2si_v2si, ARM_BUILTIN_WPACKWUS);
11894 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wpackwss", v4hi_ftype_v2si_v2si, ARM_BUILTIN_WPACKWSS);
11895 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wpackdus", v2si_ftype_di_di, ARM_BUILTIN_WPACKDUS);
11896 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wpackdss", v2si_ftype_di_di, ARM_BUILTIN_WPACKDSS);
11898 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckehub", v4hi_ftype_v8qi, ARM_BUILTIN_WUNPCKEHUB);
11899 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckehuh", v2si_ftype_v4hi, ARM_BUILTIN_WUNPCKEHUH);
11900 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckehuw", di_ftype_v2si, ARM_BUILTIN_WUNPCKEHUW);
11901 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckehsb", v4hi_ftype_v8qi, ARM_BUILTIN_WUNPCKEHSB);
11902 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckehsh", v2si_ftype_v4hi, ARM_BUILTIN_WUNPCKEHSH);
11903 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckehsw", di_ftype_v2si, ARM_BUILTIN_WUNPCKEHSW);
11904 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckelub", v4hi_ftype_v8qi, ARM_BUILTIN_WUNPCKELUB);
11905 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckeluh", v2si_ftype_v4hi, ARM_BUILTIN_WUNPCKELUH);
11906 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckeluw", di_ftype_v2si, ARM_BUILTIN_WUNPCKELUW);
11907 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckelsb", v4hi_ftype_v8qi, ARM_BUILTIN_WUNPCKELSB);
11908 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckelsh", v2si_ftype_v4hi, ARM_BUILTIN_WUNPCKELSH);
11909 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckelsw", di_ftype_v2si, ARM_BUILTIN_WUNPCKELSW);
11911 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wmacs", di_ftype_di_v4hi_v4hi, ARM_BUILTIN_WMACS);
11912 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wmacsz", di_ftype_v4hi_v4hi, ARM_BUILTIN_WMACSZ);
11913 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wmacu", di_ftype_di_v4hi_v4hi, ARM_BUILTIN_WMACU);
11914 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wmacuz", di_ftype_v4hi_v4hi, ARM_BUILTIN_WMACUZ);
11916 def_mbuiltin (FL_IWMMXT, "__builtin_arm_walign", v8qi_ftype_v8qi_v8qi_int, ARM_BUILTIN_WALIGN);
11917 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmia", di_ftype_di_int_int, ARM_BUILTIN_TMIA);
11918 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmiaph", di_ftype_di_int_int, ARM_BUILTIN_TMIAPH);
11919 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmiabb", di_ftype_di_int_int, ARM_BUILTIN_TMIABB);
11920 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmiabt", di_ftype_di_int_int, ARM_BUILTIN_TMIABT);
11921 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmiatb", di_ftype_di_int_int, ARM_BUILTIN_TMIATB);
11922 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmiatt", di_ftype_di_int_int, ARM_BUILTIN_TMIATT);
11926 arm_init_builtins (void)
11928 if (TARGET_REALLY_IWMMXT)
11929 arm_init_iwmmxt_builtins ();
11932 /* Errors in the source file can cause expand_expr to return const0_rtx
11933 where we expect a vector. To avoid crashing, use one of the vector
11934 clear instructions. */
11937 safe_vector_operand (rtx x, enum machine_mode mode)
11939 if (x != const0_rtx)
11941 x = gen_reg_rtx (mode);
11943 emit_insn (gen_iwmmxt_clrdi (mode == DImode ? x
11944 : gen_rtx_SUBREG (DImode, x, 0)));
11948 /* Subroutine of arm_expand_builtin to take care of binop insns. */
11951 arm_expand_binop_builtin (enum insn_code icode,
11952 tree arglist, rtx target)
11955 tree arg0 = TREE_VALUE (arglist);
11956 tree arg1 = TREE_VALUE (TREE_CHAIN (arglist));
11957 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
11958 rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
11959 enum machine_mode tmode = insn_data[icode].operand[0].mode;
11960 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
11961 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
11963 if (VECTOR_MODE_P (mode0))
11964 op0 = safe_vector_operand (op0, mode0);
11965 if (VECTOR_MODE_P (mode1))
11966 op1 = safe_vector_operand (op1, mode1);
11969 || GET_MODE (target) != tmode
11970 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
11971 target = gen_reg_rtx (tmode);
11973 /* In case the insn wants input operands in modes different from
11974 the result, abort. */
11975 if (GET_MODE (op0) != mode0 || GET_MODE (op1) != mode1)
11978 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
11979 op0 = copy_to_mode_reg (mode0, op0);
11980 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
11981 op1 = copy_to_mode_reg (mode1, op1);
11983 pat = GEN_FCN (icode) (target, op0, op1);
11990 /* Subroutine of arm_expand_builtin to take care of unop insns. */
11993 arm_expand_unop_builtin (enum insn_code icode,
11994 tree arglist, rtx target, int do_load)
11997 tree arg0 = TREE_VALUE (arglist);
11998 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
11999 enum machine_mode tmode = insn_data[icode].operand[0].mode;
12000 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
12003 || GET_MODE (target) != tmode
12004 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
12005 target = gen_reg_rtx (tmode);
12007 op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0));
12010 if (VECTOR_MODE_P (mode0))
12011 op0 = safe_vector_operand (op0, mode0);
12013 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
12014 op0 = copy_to_mode_reg (mode0, op0);
12017 pat = GEN_FCN (icode) (target, op0);
12024 /* Expand an expression EXP that calls a built-in function,
12025 with result going to TARGET if that's convenient
12026 (and in mode MODE if that's convenient).
12027 SUBTARGET may be used as the target for computing one of EXP's operands.
12028 IGNORE is nonzero if the value is to be ignored. */
12031 arm_expand_builtin (tree exp,
12033 rtx subtarget ATTRIBUTE_UNUSED,
12034 enum machine_mode mode ATTRIBUTE_UNUSED,
12035 int ignore ATTRIBUTE_UNUSED)
12037 const struct builtin_description * d;
12038 enum insn_code icode;
12039 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
12040 tree arglist = TREE_OPERAND (exp, 1);
12048 int fcode = DECL_FUNCTION_CODE (fndecl);
12050 enum machine_mode tmode;
12051 enum machine_mode mode0;
12052 enum machine_mode mode1;
12053 enum machine_mode mode2;
12057 case ARM_BUILTIN_TEXTRMSB:
12058 case ARM_BUILTIN_TEXTRMUB:
12059 case ARM_BUILTIN_TEXTRMSH:
12060 case ARM_BUILTIN_TEXTRMUH:
12061 case ARM_BUILTIN_TEXTRMSW:
12062 case ARM_BUILTIN_TEXTRMUW:
12063 icode = (fcode == ARM_BUILTIN_TEXTRMSB ? CODE_FOR_iwmmxt_textrmsb
12064 : fcode == ARM_BUILTIN_TEXTRMUB ? CODE_FOR_iwmmxt_textrmub
12065 : fcode == ARM_BUILTIN_TEXTRMSH ? CODE_FOR_iwmmxt_textrmsh
12066 : fcode == ARM_BUILTIN_TEXTRMUH ? CODE_FOR_iwmmxt_textrmuh
12067 : CODE_FOR_iwmmxt_textrmw);
12069 arg0 = TREE_VALUE (arglist);
12070 arg1 = TREE_VALUE (TREE_CHAIN (arglist));
12071 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
12072 op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
12073 tmode = insn_data[icode].operand[0].mode;
12074 mode0 = insn_data[icode].operand[1].mode;
12075 mode1 = insn_data[icode].operand[2].mode;
12077 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
12078 op0 = copy_to_mode_reg (mode0, op0);
12079 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
12081 /* @@@ better error message */
12082 error ("selector must be an immediate");
12083 return gen_reg_rtx (tmode);
12086 || GET_MODE (target) != tmode
12087 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
12088 target = gen_reg_rtx (tmode);
12089 pat = GEN_FCN (icode) (target, op0, op1);
12095 case ARM_BUILTIN_TINSRB:
12096 case ARM_BUILTIN_TINSRH:
12097 case ARM_BUILTIN_TINSRW:
12098 icode = (fcode == ARM_BUILTIN_TINSRB ? CODE_FOR_iwmmxt_tinsrb
12099 : fcode == ARM_BUILTIN_TINSRH ? CODE_FOR_iwmmxt_tinsrh
12100 : CODE_FOR_iwmmxt_tinsrw);
12101 arg0 = TREE_VALUE (arglist);
12102 arg1 = TREE_VALUE (TREE_CHAIN (arglist));
12103 arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
12104 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
12105 op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
12106 op2 = expand_expr (arg2, NULL_RTX, VOIDmode, 0);
12107 tmode = insn_data[icode].operand[0].mode;
12108 mode0 = insn_data[icode].operand[1].mode;
12109 mode1 = insn_data[icode].operand[2].mode;
12110 mode2 = insn_data[icode].operand[3].mode;
12112 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
12113 op0 = copy_to_mode_reg (mode0, op0);
12114 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
12115 op1 = copy_to_mode_reg (mode1, op1);
12116 if (! (*insn_data[icode].operand[3].predicate) (op2, mode2))
12118 /* @@@ better error message */
12119 error ("selector must be an immediate");
12123 || GET_MODE (target) != tmode
12124 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
12125 target = gen_reg_rtx (tmode);
12126 pat = GEN_FCN (icode) (target, op0, op1, op2);
12132 case ARM_BUILTIN_SETWCX:
12133 arg0 = TREE_VALUE (arglist);
12134 arg1 = TREE_VALUE (TREE_CHAIN (arglist));
12135 op0 = force_reg (SImode, expand_expr (arg0, NULL_RTX, VOIDmode, 0));
12136 op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
12137 emit_insn (gen_iwmmxt_tmcr (op1, op0));
12140 case ARM_BUILTIN_GETWCX:
12141 arg0 = TREE_VALUE (arglist);
12142 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
12143 target = gen_reg_rtx (SImode);
12144 emit_insn (gen_iwmmxt_tmrc (target, op0));
12147 case ARM_BUILTIN_WSHUFH:
12148 icode = CODE_FOR_iwmmxt_wshufh;
12149 arg0 = TREE_VALUE (arglist);
12150 arg1 = TREE_VALUE (TREE_CHAIN (arglist));
12151 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
12152 op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
12153 tmode = insn_data[icode].operand[0].mode;
12154 mode1 = insn_data[icode].operand[1].mode;
12155 mode2 = insn_data[icode].operand[2].mode;
12157 if (! (*insn_data[icode].operand[1].predicate) (op0, mode1))
12158 op0 = copy_to_mode_reg (mode1, op0);
12159 if (! (*insn_data[icode].operand[2].predicate) (op1, mode2))
12161 /* @@@ better error message */
12162 error ("mask must be an immediate");
12166 || GET_MODE (target) != tmode
12167 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
12168 target = gen_reg_rtx (tmode);
12169 pat = GEN_FCN (icode) (target, op0, op1);
12175 case ARM_BUILTIN_WSADB:
12176 return arm_expand_binop_builtin (CODE_FOR_iwmmxt_wsadb, arglist, target);
12177 case ARM_BUILTIN_WSADH:
12178 return arm_expand_binop_builtin (CODE_FOR_iwmmxt_wsadh, arglist, target);
12179 case ARM_BUILTIN_WSADBZ:
12180 return arm_expand_binop_builtin (CODE_FOR_iwmmxt_wsadbz, arglist, target);
12181 case ARM_BUILTIN_WSADHZ:
12182 return arm_expand_binop_builtin (CODE_FOR_iwmmxt_wsadhz, arglist, target);
12184 /* Several three-argument builtins. */
12185 case ARM_BUILTIN_WMACS:
12186 case ARM_BUILTIN_WMACU:
12187 case ARM_BUILTIN_WALIGN:
12188 case ARM_BUILTIN_TMIA:
12189 case ARM_BUILTIN_TMIAPH:
12190 case ARM_BUILTIN_TMIATT:
12191 case ARM_BUILTIN_TMIATB:
12192 case ARM_BUILTIN_TMIABT:
12193 case ARM_BUILTIN_TMIABB:
12194 icode = (fcode == ARM_BUILTIN_WMACS ? CODE_FOR_iwmmxt_wmacs
12195 : fcode == ARM_BUILTIN_WMACU ? CODE_FOR_iwmmxt_wmacu
12196 : fcode == ARM_BUILTIN_TMIA ? CODE_FOR_iwmmxt_tmia
12197 : fcode == ARM_BUILTIN_TMIAPH ? CODE_FOR_iwmmxt_tmiaph
12198 : fcode == ARM_BUILTIN_TMIABB ? CODE_FOR_iwmmxt_tmiabb
12199 : fcode == ARM_BUILTIN_TMIABT ? CODE_FOR_iwmmxt_tmiabt
12200 : fcode == ARM_BUILTIN_TMIATB ? CODE_FOR_iwmmxt_tmiatb
12201 : fcode == ARM_BUILTIN_TMIATT ? CODE_FOR_iwmmxt_tmiatt
12202 : CODE_FOR_iwmmxt_walign);
12203 arg0 = TREE_VALUE (arglist);
12204 arg1 = TREE_VALUE (TREE_CHAIN (arglist));
12205 arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
12206 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
12207 op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
12208 op2 = expand_expr (arg2, NULL_RTX, VOIDmode, 0);
12209 tmode = insn_data[icode].operand[0].mode;
12210 mode0 = insn_data[icode].operand[1].mode;
12211 mode1 = insn_data[icode].operand[2].mode;
12212 mode2 = insn_data[icode].operand[3].mode;
12214 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
12215 op0 = copy_to_mode_reg (mode0, op0);
12216 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
12217 op1 = copy_to_mode_reg (mode1, op1);
12218 if (! (*insn_data[icode].operand[3].predicate) (op2, mode2))
12219 op2 = copy_to_mode_reg (mode2, op2);
12221 || GET_MODE (target) != tmode
12222 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
12223 target = gen_reg_rtx (tmode);
12224 pat = GEN_FCN (icode) (target, op0, op1, op2);
12230 case ARM_BUILTIN_WZERO:
12231 target = gen_reg_rtx (DImode);
12232 emit_insn (gen_iwmmxt_clrdi (target));
12239 for (i = 0, d = bdesc_2arg; i < ARRAY_SIZE (bdesc_2arg); i++, d++)
12240 if (d->code == (const enum arm_builtins) fcode)
12241 return arm_expand_binop_builtin (d->icode, arglist, target);
12243 for (i = 0, d = bdesc_1arg; i < ARRAY_SIZE (bdesc_1arg); i++, d++)
12244 if (d->code == (const enum arm_builtins) fcode)
12245 return arm_expand_unop_builtin (d->icode, arglist, target, 0);
12247 /* @@@ Should really do something sensible here. */
12251 /* Recursively search through all of the blocks in a function
12252 checking to see if any of the variables created in that
12253 function match the RTX called 'orig'. If they do then
12254 replace them with the RTX called 'new'. */
12256 replace_symbols_in_block (tree block, rtx orig, rtx new)
12258 for (; block; block = BLOCK_CHAIN (block))
12262 if (!TREE_USED (block))
12265 for (sym = BLOCK_VARS (block); sym; sym = TREE_CHAIN (sym))
12267 if ( (DECL_NAME (sym) == 0 && TREE_CODE (sym) != TYPE_DECL)
12268 || DECL_IGNORED_P (sym)
12269 || TREE_CODE (sym) != VAR_DECL
12270 || DECL_EXTERNAL (sym)
12271 || !rtx_equal_p (DECL_RTL (sym), orig)
12275 SET_DECL_RTL (sym, new);
12278 replace_symbols_in_block (BLOCK_SUBBLOCKS (block), orig, new);
12282 /* Return the number (counting from 0) of
12283 the least significant set bit in MASK. */
12286 number_of_first_bit_set (int mask)
12291 (mask & (1 << bit)) == 0;
12298 /* Generate code to return from a thumb function.
12299 If 'reg_containing_return_addr' is -1, then the return address is
12300 actually on the stack, at the stack pointer. */
12302 thumb_exit (FILE *f, int reg_containing_return_addr)
12304 unsigned regs_available_for_popping;
12305 unsigned regs_to_pop;
12307 unsigned available;
12311 int restore_a4 = FALSE;
12313 /* Compute the registers we need to pop. */
12317 if (reg_containing_return_addr == -1)
12319 regs_to_pop |= 1 << LR_REGNUM;
12323 if (TARGET_BACKTRACE)
12325 /* Restore the (ARM) frame pointer and stack pointer. */
12326 regs_to_pop |= (1 << ARM_HARD_FRAME_POINTER_REGNUM) | (1 << SP_REGNUM);
12330 /* If there is nothing to pop then just emit the BX instruction and
12332 if (pops_needed == 0)
12334 if (current_function_calls_eh_return)
12335 asm_fprintf (f, "\tadd\t%r, %r\n", SP_REGNUM, ARM_EH_STACKADJ_REGNUM);
12337 asm_fprintf (f, "\tbx\t%r\n", reg_containing_return_addr);
12340 /* Otherwise if we are not supporting interworking and we have not created
12341 a backtrace structure and the function was not entered in ARM mode then
12342 just pop the return address straight into the PC. */
12343 else if (!TARGET_INTERWORK
12344 && !TARGET_BACKTRACE
12345 && !is_called_in_ARM_mode (current_function_decl)
12346 && !current_function_calls_eh_return)
12348 asm_fprintf (f, "\tpop\t{%r}\n", PC_REGNUM);
12352 /* Find out how many of the (return) argument registers we can corrupt. */
12353 regs_available_for_popping = 0;
12355 /* If returning via __builtin_eh_return, the bottom three registers
12356 all contain information needed for the return. */
12357 if (current_function_calls_eh_return)
12361 /* If we can deduce the registers used from the function's
12362 return value. This is more reliable that examining
12363 regs_ever_live[] because that will be set if the register is
12364 ever used in the function, not just if the register is used
12365 to hold a return value. */
12367 if (current_function_return_rtx != 0)
12368 mode = GET_MODE (current_function_return_rtx);
12370 mode = DECL_MODE (DECL_RESULT (current_function_decl));
12372 size = GET_MODE_SIZE (mode);
12376 /* In a void function we can use any argument register.
12377 In a function that returns a structure on the stack
12378 we can use the second and third argument registers. */
12379 if (mode == VOIDmode)
12380 regs_available_for_popping =
12381 (1 << ARG_REGISTER (1))
12382 | (1 << ARG_REGISTER (2))
12383 | (1 << ARG_REGISTER (3));
12385 regs_available_for_popping =
12386 (1 << ARG_REGISTER (2))
12387 | (1 << ARG_REGISTER (3));
12389 else if (size <= 4)
12390 regs_available_for_popping =
12391 (1 << ARG_REGISTER (2))
12392 | (1 << ARG_REGISTER (3));
12393 else if (size <= 8)
12394 regs_available_for_popping =
12395 (1 << ARG_REGISTER (3));
12398 /* Match registers to be popped with registers into which we pop them. */
12399 for (available = regs_available_for_popping,
12400 required = regs_to_pop;
12401 required != 0 && available != 0;
12402 available &= ~(available & - available),
12403 required &= ~(required & - required))
12406 /* If we have any popping registers left over, remove them. */
12408 regs_available_for_popping &= ~available;
12410 /* Otherwise if we need another popping register we can use
12411 the fourth argument register. */
12412 else if (pops_needed)
12414 /* If we have not found any free argument registers and
12415 reg a4 contains the return address, we must move it. */
12416 if (regs_available_for_popping == 0
12417 && reg_containing_return_addr == LAST_ARG_REGNUM)
12419 asm_fprintf (f, "\tmov\t%r, %r\n", LR_REGNUM, LAST_ARG_REGNUM);
12420 reg_containing_return_addr = LR_REGNUM;
12422 else if (size > 12)
12424 /* Register a4 is being used to hold part of the return value,
12425 but we have dire need of a free, low register. */
12428 asm_fprintf (f, "\tmov\t%r, %r\n",IP_REGNUM, LAST_ARG_REGNUM);
12431 if (reg_containing_return_addr != LAST_ARG_REGNUM)
12433 /* The fourth argument register is available. */
12434 regs_available_for_popping |= 1 << LAST_ARG_REGNUM;
12440 /* Pop as many registers as we can. */
12441 thumb_pushpop (f, regs_available_for_popping, FALSE, NULL,
12442 regs_available_for_popping);
12444 /* Process the registers we popped. */
12445 if (reg_containing_return_addr == -1)
12447 /* The return address was popped into the lowest numbered register. */
12448 regs_to_pop &= ~(1 << LR_REGNUM);
12450 reg_containing_return_addr =
12451 number_of_first_bit_set (regs_available_for_popping);
12453 /* Remove this register for the mask of available registers, so that
12454 the return address will not be corrupted by further pops. */
12455 regs_available_for_popping &= ~(1 << reg_containing_return_addr);
12458 /* If we popped other registers then handle them here. */
12459 if (regs_available_for_popping)
12463 /* Work out which register currently contains the frame pointer. */
12464 frame_pointer = number_of_first_bit_set (regs_available_for_popping);
12466 /* Move it into the correct place. */
12467 asm_fprintf (f, "\tmov\t%r, %r\n",
12468 ARM_HARD_FRAME_POINTER_REGNUM, frame_pointer);
12470 /* (Temporarily) remove it from the mask of popped registers. */
12471 regs_available_for_popping &= ~(1 << frame_pointer);
12472 regs_to_pop &= ~(1 << ARM_HARD_FRAME_POINTER_REGNUM);
12474 if (regs_available_for_popping)
12478 /* We popped the stack pointer as well,
12479 find the register that contains it. */
12480 stack_pointer = number_of_first_bit_set (regs_available_for_popping);
12482 /* Move it into the stack register. */
12483 asm_fprintf (f, "\tmov\t%r, %r\n", SP_REGNUM, stack_pointer);
12485 /* At this point we have popped all necessary registers, so
12486 do not worry about restoring regs_available_for_popping
12487 to its correct value:
12489 assert (pops_needed == 0)
12490 assert (regs_available_for_popping == (1 << frame_pointer))
12491 assert (regs_to_pop == (1 << STACK_POINTER)) */
12495 /* Since we have just move the popped value into the frame
12496 pointer, the popping register is available for reuse, and
12497 we know that we still have the stack pointer left to pop. */
12498 regs_available_for_popping |= (1 << frame_pointer);
12502 /* If we still have registers left on the stack, but we no longer have
12503 any registers into which we can pop them, then we must move the return
12504 address into the link register and make available the register that
12506 if (regs_available_for_popping == 0 && pops_needed > 0)
12508 regs_available_for_popping |= 1 << reg_containing_return_addr;
12510 asm_fprintf (f, "\tmov\t%r, %r\n", LR_REGNUM,
12511 reg_containing_return_addr);
12513 reg_containing_return_addr = LR_REGNUM;
12516 /* If we have registers left on the stack then pop some more.
12517 We know that at most we will want to pop FP and SP. */
12518 if (pops_needed > 0)
12523 thumb_pushpop (f, regs_available_for_popping, FALSE, NULL,
12524 regs_available_for_popping);
12526 /* We have popped either FP or SP.
12527 Move whichever one it is into the correct register. */
12528 popped_into = number_of_first_bit_set (regs_available_for_popping);
12529 move_to = number_of_first_bit_set (regs_to_pop);
12531 asm_fprintf (f, "\tmov\t%r, %r\n", move_to, popped_into);
12533 regs_to_pop &= ~(1 << move_to);
12538 /* If we still have not popped everything then we must have only
12539 had one register available to us and we are now popping the SP. */
12540 if (pops_needed > 0)
12544 thumb_pushpop (f, regs_available_for_popping, FALSE, NULL,
12545 regs_available_for_popping);
12547 popped_into = number_of_first_bit_set (regs_available_for_popping);
12549 asm_fprintf (f, "\tmov\t%r, %r\n", SP_REGNUM, popped_into);
12551 assert (regs_to_pop == (1 << STACK_POINTER))
12552 assert (pops_needed == 1)
12556 /* If necessary restore the a4 register. */
12559 if (reg_containing_return_addr != LR_REGNUM)
12561 asm_fprintf (f, "\tmov\t%r, %r\n", LR_REGNUM, LAST_ARG_REGNUM);
12562 reg_containing_return_addr = LR_REGNUM;
12565 asm_fprintf (f, "\tmov\t%r, %r\n", LAST_ARG_REGNUM, IP_REGNUM);
12568 if (current_function_calls_eh_return)
12569 asm_fprintf (f, "\tadd\t%r, %r\n", SP_REGNUM, ARM_EH_STACKADJ_REGNUM);
12571 /* Return to caller. */
12572 asm_fprintf (f, "\tbx\t%r\n", reg_containing_return_addr);
12575 /* Emit code to push or pop registers to or from the stack. F is the
12576 assembly file. MASK is the registers to push or pop. PUSH is
12577 nonzero if we should push, and zero if we should pop. For debugging
12578 output, if pushing, adjust CFA_OFFSET by the amount of space added
12579 to the stack. REAL_REGS should have the same number of bits set as
12580 MASK, and will be used instead (in the same order) to describe which
12581 registers were saved - this is used to mark the save slots when we
12582 push high registers after moving them to low registers. */
12584 thumb_pushpop (FILE *f, int mask, int push, int *cfa_offset, int real_regs)
12587 int lo_mask = mask & 0xFF;
12588 int pushed_words = 0;
12590 if (lo_mask == 0 && !push && (mask & (1 << PC_REGNUM)))
12592 /* Special case. Do not generate a POP PC statement here, do it in
12594 thumb_exit (f, -1);
12598 fprintf (f, "\t%s\t{", push ? "push" : "pop");
12600 /* Look at the low registers first. */
12601 for (regno = 0; regno <= LAST_LO_REGNUM; regno++, lo_mask >>= 1)
12605 asm_fprintf (f, "%r", regno);
12607 if ((lo_mask & ~1) != 0)
12614 if (push && (mask & (1 << LR_REGNUM)))
12616 /* Catch pushing the LR. */
12620 asm_fprintf (f, "%r", LR_REGNUM);
12624 else if (!push && (mask & (1 << PC_REGNUM)))
12626 /* Catch popping the PC. */
12627 if (TARGET_INTERWORK || TARGET_BACKTRACE
12628 || current_function_calls_eh_return)
12630 /* The PC is never poped directly, instead
12631 it is popped into r3 and then BX is used. */
12632 fprintf (f, "}\n");
12634 thumb_exit (f, -1);
12643 asm_fprintf (f, "%r", PC_REGNUM);
12647 fprintf (f, "}\n");
12649 if (push && pushed_words && dwarf2out_do_frame ())
12651 char *l = dwarf2out_cfi_label ();
12652 int pushed_mask = real_regs;
12654 *cfa_offset += pushed_words * 4;
12655 dwarf2out_def_cfa (l, SP_REGNUM, *cfa_offset);
12658 pushed_mask = real_regs;
12659 for (regno = 0; regno <= 14; regno++, pushed_mask >>= 1)
12661 if (pushed_mask & 1)
12662 dwarf2out_reg_save (l, regno, 4 * pushed_words++ - *cfa_offset);
12668 thumb_final_prescan_insn (rtx insn)
12670 if (flag_print_asm_name)
12671 asm_fprintf (asm_out_file, "%@ 0x%04x\n",
12672 INSN_ADDRESSES (INSN_UID (insn)));
12676 thumb_shiftable_const (unsigned HOST_WIDE_INT val)
12678 unsigned HOST_WIDE_INT mask = 0xff;
12681 if (val == 0) /* XXX */
12684 for (i = 0; i < 25; i++)
12685 if ((val & (mask << i)) == val)
12691 /* Returns nonzero if the current function contains,
12692 or might contain a far jump. */
12694 thumb_far_jump_used_p (void)
12698 /* This test is only important for leaf functions. */
12699 /* assert (!leaf_function_p ()); */
12701 /* If we have already decided that far jumps may be used,
12702 do not bother checking again, and always return true even if
12703 it turns out that they are not being used. Once we have made
12704 the decision that far jumps are present (and that hence the link
12705 register will be pushed onto the stack) we cannot go back on it. */
12706 if (cfun->machine->far_jump_used)
12709 /* If this function is not being called from the prologue/epilogue
12710 generation code then it must be being called from the
12711 INITIAL_ELIMINATION_OFFSET macro. */
12712 if (!(ARM_DOUBLEWORD_ALIGN || reload_completed))
12714 /* In this case we know that we are being asked about the elimination
12715 of the arg pointer register. If that register is not being used,
12716 then there are no arguments on the stack, and we do not have to
12717 worry that a far jump might force the prologue to push the link
12718 register, changing the stack offsets. In this case we can just
12719 return false, since the presence of far jumps in the function will
12720 not affect stack offsets.
12722 If the arg pointer is live (or if it was live, but has now been
12723 eliminated and so set to dead) then we do have to test to see if
12724 the function might contain a far jump. This test can lead to some
12725 false negatives, since before reload is completed, then length of
12726 branch instructions is not known, so gcc defaults to returning their
12727 longest length, which in turn sets the far jump attribute to true.
12729 A false negative will not result in bad code being generated, but it
12730 will result in a needless push and pop of the link register. We
12731 hope that this does not occur too often.
12733 If we need doubleword stack alignment this could affect the other
12734 elimination offsets so we can't risk getting it wrong. */
12735 if (regs_ever_live [ARG_POINTER_REGNUM])
12736 cfun->machine->arg_pointer_live = 1;
12737 else if (!cfun->machine->arg_pointer_live)
12741 /* Check to see if the function contains a branch
12742 insn with the far jump attribute set. */
12743 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
12745 if (GET_CODE (insn) == JUMP_INSN
12746 /* Ignore tablejump patterns. */
12747 && GET_CODE (PATTERN (insn)) != ADDR_VEC
12748 && GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC
12749 && get_attr_far_jump (insn) == FAR_JUMP_YES
12752 /* Record the fact that we have decided that
12753 the function does use far jumps. */
12754 cfun->machine->far_jump_used = 1;
12762 /* Return nonzero if FUNC must be entered in ARM mode. */
12764 is_called_in_ARM_mode (tree func)
12766 if (TREE_CODE (func) != FUNCTION_DECL)
12769 /* Ignore the problem about functions whoes address is taken. */
12770 if (TARGET_CALLEE_INTERWORKING && TREE_PUBLIC (func))
12774 return lookup_attribute ("interfacearm", DECL_ATTRIBUTES (func)) != NULL_TREE;
12780 /* The bits which aren't usefully expanded as rtl. */
12782 thumb_unexpanded_epilogue (void)
12785 int live_regs_mask = 0;
12786 int high_regs_pushed = 0;
12787 int had_to_push_lr;
12791 if (return_used_this_function)
12794 if (IS_NAKED (arm_current_func_type ()))
12797 live_regs_mask = thumb_compute_save_reg_mask ();
12798 high_regs_pushed = bit_count (live_regs_mask & 0x0f00);
12800 /* If we can deduce the registers used from the function's return value.
12801 This is more reliable that examining regs_ever_live[] because that
12802 will be set if the register is ever used in the function, not just if
12803 the register is used to hold a return value. */
12805 if (current_function_return_rtx != 0)
12806 mode = GET_MODE (current_function_return_rtx);
12808 mode = DECL_MODE (DECL_RESULT (current_function_decl));
12810 size = GET_MODE_SIZE (mode);
12812 /* The prolog may have pushed some high registers to use as
12813 work registers. e.g. the testsuite file:
12814 gcc/testsuite/gcc/gcc.c-torture/execute/complex-2.c
12815 compiles to produce:
12816 push {r4, r5, r6, r7, lr}
12820 as part of the prolog. We have to undo that pushing here. */
12822 if (high_regs_pushed)
12824 int mask = live_regs_mask & 0xff;
12827 /* The available low registers depend on the size of the value we are
12835 /* Oh dear! We have no low registers into which we can pop
12838 ("no low registers available for popping high registers");
12840 for (next_hi_reg = 8; next_hi_reg < 13; next_hi_reg++)
12841 if (live_regs_mask & (1 << next_hi_reg))
12844 while (high_regs_pushed)
12846 /* Find lo register(s) into which the high register(s) can
12848 for (regno = 0; regno <= LAST_LO_REGNUM; regno++)
12850 if (mask & (1 << regno))
12851 high_regs_pushed--;
12852 if (high_regs_pushed == 0)
12856 mask &= (2 << regno) - 1; /* A noop if regno == 8 */
12858 /* Pop the values into the low register(s). */
12859 thumb_pushpop (asm_out_file, mask, 0, NULL, mask);
12861 /* Move the value(s) into the high registers. */
12862 for (regno = 0; regno <= LAST_LO_REGNUM; regno++)
12864 if (mask & (1 << regno))
12866 asm_fprintf (asm_out_file, "\tmov\t%r, %r\n", next_hi_reg,
12869 for (next_hi_reg++; next_hi_reg < 13; next_hi_reg++)
12870 if (live_regs_mask & (1 << next_hi_reg))
12875 live_regs_mask &= ~0x0f00;
12878 had_to_push_lr = (live_regs_mask & (1 << LR_REGNUM)) != 0;
12879 live_regs_mask &= 0xff;
12881 if (current_function_pretend_args_size == 0 || TARGET_BACKTRACE)
12883 /* Pop the return address into the PC. */
12884 if (had_to_push_lr)
12885 live_regs_mask |= 1 << PC_REGNUM;
12887 /* Either no argument registers were pushed or a backtrace
12888 structure was created which includes an adjusted stack
12889 pointer, so just pop everything. */
12890 if (live_regs_mask)
12891 thumb_pushpop (asm_out_file, live_regs_mask, FALSE, NULL,
12894 /* We have either just popped the return address into the
12895 PC or it is was kept in LR for the entire function. */
12896 if (!had_to_push_lr)
12897 thumb_exit (asm_out_file, LR_REGNUM);
12901 /* Pop everything but the return address. */
12902 if (live_regs_mask)
12903 thumb_pushpop (asm_out_file, live_regs_mask, FALSE, NULL,
12906 if (had_to_push_lr)
12910 /* We have no free low regs, so save one. */
12911 asm_fprintf (asm_out_file, "\tmov\t%r, %r\n", IP_REGNUM,
12915 /* Get the return address into a temporary register. */
12916 thumb_pushpop (asm_out_file, 1 << LAST_ARG_REGNUM, 0, NULL,
12917 1 << LAST_ARG_REGNUM);
12921 /* Move the return address to lr. */
12922 asm_fprintf (asm_out_file, "\tmov\t%r, %r\n", LR_REGNUM,
12924 /* Restore the low register. */
12925 asm_fprintf (asm_out_file, "\tmov\t%r, %r\n", LAST_ARG_REGNUM,
12930 regno = LAST_ARG_REGNUM;
12935 /* Remove the argument registers that were pushed onto the stack. */
12936 asm_fprintf (asm_out_file, "\tadd\t%r, %r, #%d\n",
12937 SP_REGNUM, SP_REGNUM,
12938 current_function_pretend_args_size);
12940 thumb_exit (asm_out_file, regno);
12946 /* Functions to save and restore machine-specific function data. */
12947 static struct machine_function *
12948 arm_init_machine_status (void)
12950 struct machine_function *machine;
12951 machine = (machine_function *) ggc_alloc_cleared (sizeof (machine_function));
12953 #if ARM_FT_UNKNOWN != 0
12954 machine->func_type = ARM_FT_UNKNOWN;
12959 /* Return an RTX indicating where the return address to the
12960 calling function can be found. */
12962 arm_return_addr (int count, rtx frame ATTRIBUTE_UNUSED)
12967 return get_hard_reg_initial_val (Pmode, LR_REGNUM);
12970 /* Do anything needed before RTL is emitted for each function. */
12972 arm_init_expanders (void)
12974 /* Arrange to initialize and mark the machine per-function status. */
12975 init_machine_status = arm_init_machine_status;
12977 /* This is to stop the combine pass optimizing away the alignment
12978 adjustment of va_arg. */
12979 /* ??? It is claimed that this should not be necessary. */
12981 mark_reg_pointer (arg_pointer_rtx, PARM_BOUNDARY);
12985 /* Like arm_compute_initial_elimination offset. Simpler because
12986 THUMB_HARD_FRAME_POINTER isn't actually the ABI specified frame pointer. */
12989 thumb_compute_initial_elimination_offset (unsigned int from, unsigned int to)
12991 arm_stack_offsets *offsets;
12993 offsets = arm_get_frame_offsets ();
12997 case ARG_POINTER_REGNUM:
13000 case STACK_POINTER_REGNUM:
13001 return offsets->outgoing_args - offsets->saved_args;
13003 case FRAME_POINTER_REGNUM:
13004 return offsets->soft_frame - offsets->saved_args;
13006 case THUMB_HARD_FRAME_POINTER_REGNUM:
13007 case ARM_HARD_FRAME_POINTER_REGNUM:
13008 return offsets->saved_regs - offsets->saved_args;
13015 case FRAME_POINTER_REGNUM:
13018 case STACK_POINTER_REGNUM:
13019 return offsets->outgoing_args - offsets->soft_frame;
13021 case THUMB_HARD_FRAME_POINTER_REGNUM:
13022 case ARM_HARD_FRAME_POINTER_REGNUM:
13023 return offsets->saved_regs - offsets->soft_frame;
13036 /* Generate the rest of a function's prologue. */
13038 thumb_expand_prologue (void)
13042 HOST_WIDE_INT amount;
13043 arm_stack_offsets *offsets;
13044 unsigned long func_type;
13046 unsigned long live_regs_mask;
13048 func_type = arm_current_func_type ();
13050 /* Naked functions don't have prologues. */
13051 if (IS_NAKED (func_type))
13054 if (IS_INTERRUPT (func_type))
13056 error ("interrupt Service Routines cannot be coded in Thumb mode");
13060 live_regs_mask = thumb_compute_save_reg_mask ();
13061 /* Load the pic register before setting the frame pointer, so we can use r7
13062 as a temporary work register. */
13064 arm_load_pic_register (thumb_find_work_register (live_regs_mask));
13066 offsets = arm_get_frame_offsets ();
13068 if (frame_pointer_needed)
13070 insn = emit_insn (gen_movsi (hard_frame_pointer_rtx,
13071 stack_pointer_rtx));
13072 RTX_FRAME_RELATED_P (insn) = 1;
13074 else if (CALLER_INTERWORKING_SLOT_SIZE > 0)
13075 emit_move_insn (gen_rtx_REG (Pmode, ARM_HARD_FRAME_POINTER_REGNUM),
13076 stack_pointer_rtx);
13078 amount = offsets->outgoing_args - offsets->saved_regs;
13083 insn = emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,
13084 GEN_INT (- amount)));
13085 RTX_FRAME_RELATED_P (insn) = 1;
13091 /* The stack decrement is too big for an immediate value in a single
13092 insn. In theory we could issue multiple subtracts, but after
13093 three of them it becomes more space efficient to place the full
13094 value in the constant pool and load into a register. (Also the
13095 ARM debugger really likes to see only one stack decrement per
13096 function). So instead we look for a scratch register into which
13097 we can load the decrement, and then we subtract this from the
13098 stack pointer. Unfortunately on the thumb the only available
13099 scratch registers are the argument registers, and we cannot use
13100 these as they may hold arguments to the function. Instead we
13101 attempt to locate a call preserved register which is used by this
13102 function. If we can find one, then we know that it will have
13103 been pushed at the start of the prologue and so we can corrupt
13105 for (regno = LAST_ARG_REGNUM + 1; regno <= LAST_LO_REGNUM; regno++)
13106 if (live_regs_mask & (1 << regno)
13107 && !(frame_pointer_needed
13108 && (regno == THUMB_HARD_FRAME_POINTER_REGNUM)))
13111 if (regno > LAST_LO_REGNUM) /* Very unlikely. */
13113 rtx spare = gen_rtx_REG (SImode, IP_REGNUM);
13115 /* Choose an arbitrary, non-argument low register. */
13116 reg = gen_rtx_REG (SImode, LAST_LO_REGNUM);
13118 /* Save it by copying it into a high, scratch register. */
13119 emit_insn (gen_movsi (spare, reg));
13120 /* Add a USE to stop propagate_one_insn() from barfing. */
13121 emit_insn (gen_prologue_use (spare));
13123 /* Decrement the stack. */
13124 emit_insn (gen_movsi (reg, GEN_INT (- amount)));
13125 insn = emit_insn (gen_addsi3 (stack_pointer_rtx,
13126 stack_pointer_rtx, reg));
13127 RTX_FRAME_RELATED_P (insn) = 1;
13128 dwarf = gen_rtx_SET (SImode, stack_pointer_rtx,
13129 plus_constant (stack_pointer_rtx,
13131 RTX_FRAME_RELATED_P (dwarf) = 1;
13133 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, dwarf,
13136 /* Restore the low register's original value. */
13137 emit_insn (gen_movsi (reg, spare));
13139 /* Emit a USE of the restored scratch register, so that flow
13140 analysis will not consider the restore redundant. The
13141 register won't be used again in this function and isn't
13142 restored by the epilogue. */
13143 emit_insn (gen_prologue_use (reg));
13147 reg = gen_rtx_REG (SImode, regno);
13149 emit_insn (gen_movsi (reg, GEN_INT (- amount)));
13151 insn = emit_insn (gen_addsi3 (stack_pointer_rtx,
13152 stack_pointer_rtx, reg));
13153 RTX_FRAME_RELATED_P (insn) = 1;
13154 dwarf = gen_rtx_SET (SImode, stack_pointer_rtx,
13155 plus_constant (stack_pointer_rtx,
13157 RTX_FRAME_RELATED_P (dwarf) = 1;
13159 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, dwarf,
13163 /* If the frame pointer is needed, emit a special barrier that
13164 will prevent the scheduler from moving stores to the frame
13165 before the stack adjustment. */
13166 if (frame_pointer_needed)
13167 emit_insn (gen_stack_tie (stack_pointer_rtx,
13168 hard_frame_pointer_rtx));
13171 if (current_function_profile || TARGET_NO_SCHED_PRO)
13172 emit_insn (gen_blockage ());
13174 cfun->machine->lr_save_eliminated = !thumb_force_lr_save ();
13175 if (live_regs_mask & 0xff)
13176 cfun->machine->lr_save_eliminated = 0;
13178 /* If the link register is being kept alive, with the return address in it,
13179 then make sure that it does not get reused by the ce2 pass. */
13180 if (cfun->machine->lr_save_eliminated)
13181 emit_insn (gen_prologue_use (gen_rtx_REG (SImode, LR_REGNUM)));
13186 thumb_expand_epilogue (void)
13188 HOST_WIDE_INT amount;
13189 arm_stack_offsets *offsets;
13192 /* Naked functions don't have prologues. */
13193 if (IS_NAKED (arm_current_func_type ()))
13196 offsets = arm_get_frame_offsets ();
13197 amount = offsets->outgoing_args - offsets->saved_regs;
13199 if (frame_pointer_needed)
13200 emit_insn (gen_movsi (stack_pointer_rtx, hard_frame_pointer_rtx));
13204 emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,
13205 GEN_INT (amount)));
13208 /* r3 is always free in the epilogue. */
13209 rtx reg = gen_rtx_REG (SImode, LAST_ARG_REGNUM);
13211 emit_insn (gen_movsi (reg, GEN_INT (amount)));
13212 emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, reg));
13216 /* Emit a USE (stack_pointer_rtx), so that
13217 the stack adjustment will not be deleted. */
13218 emit_insn (gen_prologue_use (stack_pointer_rtx));
13220 if (current_function_profile || TARGET_NO_SCHED_PRO)
13221 emit_insn (gen_blockage ());
13223 /* Emit a clobber for each insn that will be restored in the epilogue,
13224 so that flow2 will get register lifetimes correct. */
13225 for (regno = 0; regno < 13; regno++)
13226 if (regs_ever_live[regno] && !call_used_regs[regno])
13227 emit_insn (gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, regno)));
13229 if (! regs_ever_live[LR_REGNUM])
13230 emit_insn (gen_rtx_USE (VOIDmode, gen_rtx_REG (SImode, LR_REGNUM)));
13234 thumb_output_function_prologue (FILE *f, HOST_WIDE_INT size ATTRIBUTE_UNUSED)
13236 int live_regs_mask = 0;
13238 int high_regs_pushed = 0;
13239 int cfa_offset = 0;
13242 if (IS_NAKED (arm_current_func_type ()))
13245 if (is_called_in_ARM_mode (current_function_decl))
13249 if (GET_CODE (DECL_RTL (current_function_decl)) != MEM)
13251 if (GET_CODE (XEXP (DECL_RTL (current_function_decl), 0)) != SYMBOL_REF)
13253 name = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
13255 /* Generate code sequence to switch us into Thumb mode. */
13256 /* The .code 32 directive has already been emitted by
13257 ASM_DECLARE_FUNCTION_NAME. */
13258 asm_fprintf (f, "\torr\t%r, %r, #1\n", IP_REGNUM, PC_REGNUM);
13259 asm_fprintf (f, "\tbx\t%r\n", IP_REGNUM);
13261 /* Generate a label, so that the debugger will notice the
13262 change in instruction sets. This label is also used by
13263 the assembler to bypass the ARM code when this function
13264 is called from a Thumb encoded function elsewhere in the
13265 same file. Hence the definition of STUB_NAME here must
13266 agree with the definition in gas/config/tc-arm.c. */
13268 #define STUB_NAME ".real_start_of"
13270 fprintf (f, "\t.code\t16\n");
13272 if (arm_dllexport_name_p (name))
13273 name = arm_strip_name_encoding (name);
13275 asm_fprintf (f, "\t.globl %s%U%s\n", STUB_NAME, name);
13276 fprintf (f, "\t.thumb_func\n");
13277 asm_fprintf (f, "%s%U%s:\n", STUB_NAME, name);
13280 if (current_function_pretend_args_size)
13282 if (cfun->machine->uses_anonymous_args)
13286 fprintf (f, "\tpush\t{");
13288 num_pushes = ARM_NUM_INTS (current_function_pretend_args_size);
13290 for (regno = LAST_ARG_REGNUM + 1 - num_pushes;
13291 regno <= LAST_ARG_REGNUM;
13293 asm_fprintf (f, "%r%s", regno,
13294 regno == LAST_ARG_REGNUM ? "" : ", ");
13296 fprintf (f, "}\n");
13299 asm_fprintf (f, "\tsub\t%r, %r, #%d\n",
13300 SP_REGNUM, SP_REGNUM,
13301 current_function_pretend_args_size);
13303 /* We don't need to record the stores for unwinding (would it
13304 help the debugger any if we did?), but record the change in
13305 the stack pointer. */
13306 if (dwarf2out_do_frame ())
13308 char *l = dwarf2out_cfi_label ();
13309 cfa_offset = cfa_offset + current_function_pretend_args_size;
13310 dwarf2out_def_cfa (l, SP_REGNUM, cfa_offset);
13314 live_regs_mask = thumb_compute_save_reg_mask ();
13315 /* Just low regs and lr. */
13316 l_mask = live_regs_mask & 0x40ff;
13318 if (TARGET_BACKTRACE)
13323 /* We have been asked to create a stack backtrace structure.
13324 The code looks like this:
13328 0 sub SP, #16 Reserve space for 4 registers.
13329 2 push {R7} Push low registers.
13330 4 add R7, SP, #20 Get the stack pointer before the push.
13331 6 str R7, [SP, #8] Store the stack pointer (before reserving the space).
13332 8 mov R7, PC Get hold of the start of this code plus 12.
13333 10 str R7, [SP, #16] Store it.
13334 12 mov R7, FP Get hold of the current frame pointer.
13335 14 str R7, [SP, #4] Store it.
13336 16 mov R7, LR Get hold of the current return address.
13337 18 str R7, [SP, #12] Store it.
13338 20 add R7, SP, #16 Point at the start of the backtrace structure.
13339 22 mov FP, R7 Put this value into the frame pointer. */
13341 work_register = thumb_find_work_register (live_regs_mask);
13344 (f, "\tsub\t%r, %r, #16\t%@ Create stack backtrace structure\n",
13345 SP_REGNUM, SP_REGNUM);
13347 if (dwarf2out_do_frame ())
13349 char *l = dwarf2out_cfi_label ();
13350 cfa_offset = cfa_offset + 16;
13351 dwarf2out_def_cfa (l, SP_REGNUM, cfa_offset);
13356 thumb_pushpop (f, l_mask, 1, &cfa_offset, l_mask);
13357 offset = bit_count (l_mask);
13362 asm_fprintf (f, "\tadd\t%r, %r, #%d\n", work_register, SP_REGNUM,
13363 offset + 16 + current_function_pretend_args_size);
13365 asm_fprintf (f, "\tstr\t%r, [%r, #%d]\n", work_register, SP_REGNUM,
13368 /* Make sure that the instruction fetching the PC is in the right place
13369 to calculate "start of backtrace creation code + 12". */
13372 asm_fprintf (f, "\tmov\t%r, %r\n", work_register, PC_REGNUM);
13373 asm_fprintf (f, "\tstr\t%r, [%r, #%d]\n", work_register, SP_REGNUM,
13375 asm_fprintf (f, "\tmov\t%r, %r\n", work_register,
13376 ARM_HARD_FRAME_POINTER_REGNUM);
13377 asm_fprintf (f, "\tstr\t%r, [%r, #%d]\n", work_register, SP_REGNUM,
13382 asm_fprintf (f, "\tmov\t%r, %r\n", work_register,
13383 ARM_HARD_FRAME_POINTER_REGNUM);
13384 asm_fprintf (f, "\tstr\t%r, [%r, #%d]\n", work_register, SP_REGNUM,
13386 asm_fprintf (f, "\tmov\t%r, %r\n", work_register, PC_REGNUM);
13387 asm_fprintf (f, "\tstr\t%r, [%r, #%d]\n", work_register, SP_REGNUM,
13391 asm_fprintf (f, "\tmov\t%r, %r\n", work_register, LR_REGNUM);
13392 asm_fprintf (f, "\tstr\t%r, [%r, #%d]\n", work_register, SP_REGNUM,
13394 asm_fprintf (f, "\tadd\t%r, %r, #%d\n", work_register, SP_REGNUM,
13396 asm_fprintf (f, "\tmov\t%r, %r\t\t%@ Backtrace structure created\n",
13397 ARM_HARD_FRAME_POINTER_REGNUM, work_register);
13400 thumb_pushpop (f, l_mask, 1, &cfa_offset, l_mask);
13402 high_regs_pushed = bit_count (live_regs_mask & 0x0f00);
13404 if (high_regs_pushed)
13406 int pushable_regs = 0;
13409 for (next_hi_reg = 12; next_hi_reg > LAST_LO_REGNUM; next_hi_reg--)
13410 if (live_regs_mask & (1 << next_hi_reg))
13413 pushable_regs = l_mask & 0xff;
13415 if (pushable_regs == 0)
13416 pushable_regs = 1 << thumb_find_work_register (live_regs_mask);
13418 while (high_regs_pushed > 0)
13420 int real_regs_mask = 0;
13422 for (regno = LAST_LO_REGNUM; regno >= 0; regno--)
13424 if (pushable_regs & (1 << regno))
13426 asm_fprintf (f, "\tmov\t%r, %r\n", regno, next_hi_reg);
13428 high_regs_pushed--;
13429 real_regs_mask |= (1 << next_hi_reg);
13431 if (high_regs_pushed)
13433 for (next_hi_reg--; next_hi_reg > LAST_LO_REGNUM;
13435 if (live_regs_mask & (1 << next_hi_reg))
13440 pushable_regs &= ~((1 << regno) - 1);
13446 thumb_pushpop (f, pushable_regs, 1, &cfa_offset, real_regs_mask);
13451 /* Handle the case of a double word load into a low register from
13452 a computed memory address. The computed address may involve a
13453 register which is overwritten by the load. */
13455 thumb_load_double_from_address (rtx *operands)
13463 if (GET_CODE (operands[0]) != REG)
13466 if (GET_CODE (operands[1]) != MEM)
13469 /* Get the memory address. */
13470 addr = XEXP (operands[1], 0);
13472 /* Work out how the memory address is computed. */
13473 switch (GET_CODE (addr))
13476 operands[2] = gen_rtx_MEM (SImode,
13477 plus_constant (XEXP (operands[1], 0), 4));
13479 if (REGNO (operands[0]) == REGNO (addr))
13481 output_asm_insn ("ldr\t%H0, %2", operands);
13482 output_asm_insn ("ldr\t%0, %1", operands);
13486 output_asm_insn ("ldr\t%0, %1", operands);
13487 output_asm_insn ("ldr\t%H0, %2", operands);
13492 /* Compute <address> + 4 for the high order load. */
13493 operands[2] = gen_rtx_MEM (SImode,
13494 plus_constant (XEXP (operands[1], 0), 4));
13496 output_asm_insn ("ldr\t%0, %1", operands);
13497 output_asm_insn ("ldr\t%H0, %2", operands);
13501 arg1 = XEXP (addr, 0);
13502 arg2 = XEXP (addr, 1);
13504 if (CONSTANT_P (arg1))
13505 base = arg2, offset = arg1;
13507 base = arg1, offset = arg2;
13509 if (GET_CODE (base) != REG)
13512 /* Catch the case of <address> = <reg> + <reg> */
13513 if (GET_CODE (offset) == REG)
13515 int reg_offset = REGNO (offset);
13516 int reg_base = REGNO (base);
13517 int reg_dest = REGNO (operands[0]);
13519 /* Add the base and offset registers together into the
13520 higher destination register. */
13521 asm_fprintf (asm_out_file, "\tadd\t%r, %r, %r",
13522 reg_dest + 1, reg_base, reg_offset);
13524 /* Load the lower destination register from the address in
13525 the higher destination register. */
13526 asm_fprintf (asm_out_file, "\tldr\t%r, [%r, #0]",
13527 reg_dest, reg_dest + 1);
13529 /* Load the higher destination register from its own address
13531 asm_fprintf (asm_out_file, "\tldr\t%r, [%r, #4]",
13532 reg_dest + 1, reg_dest + 1);
13536 /* Compute <address> + 4 for the high order load. */
13537 operands[2] = gen_rtx_MEM (SImode,
13538 plus_constant (XEXP (operands[1], 0), 4));
13540 /* If the computed address is held in the low order register
13541 then load the high order register first, otherwise always
13542 load the low order register first. */
13543 if (REGNO (operands[0]) == REGNO (base))
13545 output_asm_insn ("ldr\t%H0, %2", operands);
13546 output_asm_insn ("ldr\t%0, %1", operands);
13550 output_asm_insn ("ldr\t%0, %1", operands);
13551 output_asm_insn ("ldr\t%H0, %2", operands);
13557 /* With no registers to worry about we can just load the value
13559 operands[2] = gen_rtx_MEM (SImode,
13560 plus_constant (XEXP (operands[1], 0), 4));
13562 output_asm_insn ("ldr\t%H0, %2", operands);
13563 output_asm_insn ("ldr\t%0, %1", operands);
13575 thumb_output_move_mem_multiple (int n, rtx *operands)
13582 if (REGNO (operands[4]) > REGNO (operands[5]))
13585 operands[4] = operands[5];
13588 output_asm_insn ("ldmia\t%1!, {%4, %5}", operands);
13589 output_asm_insn ("stmia\t%0!, {%4, %5}", operands);
13593 if (REGNO (operands[4]) > REGNO (operands[5]))
13596 operands[4] = operands[5];
13599 if (REGNO (operands[5]) > REGNO (operands[6]))
13602 operands[5] = operands[6];
13605 if (REGNO (operands[4]) > REGNO (operands[5]))
13608 operands[4] = operands[5];
13612 output_asm_insn ("ldmia\t%1!, {%4, %5, %6}", operands);
13613 output_asm_insn ("stmia\t%0!, {%4, %5, %6}", operands);
13623 /* Routines for generating rtl. */
13625 thumb_expand_movmemqi (rtx *operands)
13627 rtx out = copy_to_mode_reg (SImode, XEXP (operands[0], 0));
13628 rtx in = copy_to_mode_reg (SImode, XEXP (operands[1], 0));
13629 HOST_WIDE_INT len = INTVAL (operands[2]);
13630 HOST_WIDE_INT offset = 0;
13634 emit_insn (gen_movmem12b (out, in, out, in));
13640 emit_insn (gen_movmem8b (out, in, out, in));
13646 rtx reg = gen_reg_rtx (SImode);
13647 emit_insn (gen_movsi (reg, gen_rtx_MEM (SImode, in)));
13648 emit_insn (gen_movsi (gen_rtx_MEM (SImode, out), reg));
13655 rtx reg = gen_reg_rtx (HImode);
13656 emit_insn (gen_movhi (reg, gen_rtx_MEM (HImode,
13657 plus_constant (in, offset))));
13658 emit_insn (gen_movhi (gen_rtx_MEM (HImode, plus_constant (out, offset)),
13666 rtx reg = gen_reg_rtx (QImode);
13667 emit_insn (gen_movqi (reg, gen_rtx_MEM (QImode,
13668 plus_constant (in, offset))));
13669 emit_insn (gen_movqi (gen_rtx_MEM (QImode, plus_constant (out, offset)),
13675 thumb_reload_out_hi (rtx *operands)
13677 emit_insn (gen_thumb_movhi_clobber (operands[0], operands[1], operands[2]));
13680 /* Handle reading a half-word from memory during reload. */
13682 thumb_reload_in_hi (rtx *operands ATTRIBUTE_UNUSED)
13687 /* Return the length of a function name prefix
13688 that starts with the character 'c'. */
13690 arm_get_strip_length (int c)
13694 ARM_NAME_ENCODING_LENGTHS
13699 /* Return a pointer to a function's name with any
13700 and all prefix encodings stripped from it. */
13702 arm_strip_name_encoding (const char *name)
13706 while ((skip = arm_get_strip_length (* name)))
13712 /* If there is a '*' anywhere in the name's prefix, then
13713 emit the stripped name verbatim, otherwise prepend an
13714 underscore if leading underscores are being used. */
13716 arm_asm_output_labelref (FILE *stream, const char *name)
13721 while ((skip = arm_get_strip_length (* name)))
13723 verbatim |= (*name == '*');
13728 fputs (name, stream);
13730 asm_fprintf (stream, "%U%s", name);
13735 #ifdef AOF_ASSEMBLER
13736 /* Special functions only needed when producing AOF syntax assembler. */
13740 struct pic_chain * next;
13741 const char * symname;
13744 static struct pic_chain * aof_pic_chain = NULL;
13747 aof_pic_entry (rtx x)
13749 struct pic_chain ** chainp;
13752 if (aof_pic_label == NULL_RTX)
13754 aof_pic_label = gen_rtx_SYMBOL_REF (Pmode, "x$adcons");
13757 for (offset = 0, chainp = &aof_pic_chain; *chainp;
13758 offset += 4, chainp = &(*chainp)->next)
13759 if ((*chainp)->symname == XSTR (x, 0))
13760 return plus_constant (aof_pic_label, offset);
13762 *chainp = (struct pic_chain *) xmalloc (sizeof (struct pic_chain));
13763 (*chainp)->next = NULL;
13764 (*chainp)->symname = XSTR (x, 0);
13765 return plus_constant (aof_pic_label, offset);
13769 aof_dump_pic_table (FILE *f)
13771 struct pic_chain * chain;
13773 if (aof_pic_chain == NULL)
13776 asm_fprintf (f, "\tAREA |%r$$adcons|, BASED %r\n",
13777 PIC_OFFSET_TABLE_REGNUM,
13778 PIC_OFFSET_TABLE_REGNUM);
13779 fputs ("|x$adcons|\n", f);
13781 for (chain = aof_pic_chain; chain; chain = chain->next)
13783 fputs ("\tDCD\t", f);
13784 assemble_name (f, chain->symname);
13789 int arm_text_section_count = 1;
13792 aof_text_section (void )
13794 static char buf[100];
13795 sprintf (buf, "\tAREA |C$$code%d|, CODE, READONLY",
13796 arm_text_section_count++);
13798 strcat (buf, ", PIC, REENTRANT");
13802 static int arm_data_section_count = 1;
13805 aof_data_section (void)
13807 static char buf[100];
13808 sprintf (buf, "\tAREA |C$$data%d|, DATA", arm_data_section_count++);
13812 /* The AOF assembler is religiously strict about declarations of
13813 imported and exported symbols, so that it is impossible to declare
13814 a function as imported near the beginning of the file, and then to
13815 export it later on. It is, however, possible to delay the decision
13816 until all the functions in the file have been compiled. To get
13817 around this, we maintain a list of the imports and exports, and
13818 delete from it any that are subsequently defined. At the end of
13819 compilation we spit the remainder of the list out before the END
13824 struct import * next;
13828 static struct import * imports_list = NULL;
13831 aof_add_import (const char *name)
13833 struct import * new;
13835 for (new = imports_list; new; new = new->next)
13836 if (new->name == name)
13839 new = (struct import *) xmalloc (sizeof (struct import));
13840 new->next = imports_list;
13841 imports_list = new;
13846 aof_delete_import (const char *name)
13848 struct import ** old;
13850 for (old = &imports_list; *old; old = & (*old)->next)
13852 if ((*old)->name == name)
13854 *old = (*old)->next;
13860 int arm_main_function = 0;
13863 aof_dump_imports (FILE *f)
13865 /* The AOF assembler needs this to cause the startup code to be extracted
13866 from the library. Brining in __main causes the whole thing to work
13868 if (arm_main_function)
13871 fputs ("\tIMPORT __main\n", f);
13872 fputs ("\tDCD __main\n", f);
13875 /* Now dump the remaining imports. */
13876 while (imports_list)
13878 fprintf (f, "\tIMPORT\t");
13879 assemble_name (f, imports_list->name);
13881 imports_list = imports_list->next;
13886 aof_globalize_label (FILE *stream, const char *name)
13888 default_globalize_label (stream, name);
13889 if (! strcmp (name, "main"))
13890 arm_main_function = 1;
13894 aof_file_start (void)
13896 fputs ("__r0\tRN\t0\n", asm_out_file);
13897 fputs ("__a1\tRN\t0\n", asm_out_file);
13898 fputs ("__a2\tRN\t1\n", asm_out_file);
13899 fputs ("__a3\tRN\t2\n", asm_out_file);
13900 fputs ("__a4\tRN\t3\n", asm_out_file);
13901 fputs ("__v1\tRN\t4\n", asm_out_file);
13902 fputs ("__v2\tRN\t5\n", asm_out_file);
13903 fputs ("__v3\tRN\t6\n", asm_out_file);
13904 fputs ("__v4\tRN\t7\n", asm_out_file);
13905 fputs ("__v5\tRN\t8\n", asm_out_file);
13906 fputs ("__v6\tRN\t9\n", asm_out_file);
13907 fputs ("__sl\tRN\t10\n", asm_out_file);
13908 fputs ("__fp\tRN\t11\n", asm_out_file);
13909 fputs ("__ip\tRN\t12\n", asm_out_file);
13910 fputs ("__sp\tRN\t13\n", asm_out_file);
13911 fputs ("__lr\tRN\t14\n", asm_out_file);
13912 fputs ("__pc\tRN\t15\n", asm_out_file);
13913 fputs ("__f0\tFN\t0\n", asm_out_file);
13914 fputs ("__f1\tFN\t1\n", asm_out_file);
13915 fputs ("__f2\tFN\t2\n", asm_out_file);
13916 fputs ("__f3\tFN\t3\n", asm_out_file);
13917 fputs ("__f4\tFN\t4\n", asm_out_file);
13918 fputs ("__f5\tFN\t5\n", asm_out_file);
13919 fputs ("__f6\tFN\t6\n", asm_out_file);
13920 fputs ("__f7\tFN\t7\n", asm_out_file);
13925 aof_file_end (void)
13928 aof_dump_pic_table (asm_out_file);
13929 aof_dump_imports (asm_out_file);
13930 fputs ("\tEND\n", asm_out_file);
13932 #endif /* AOF_ASSEMBLER */
13935 /* Symbols in the text segment can be accessed without indirecting via the
13936 constant pool; it may take an extra binary operation, but this is still
13937 faster than indirecting via memory. Don't do this when not optimizing,
13938 since we won't be calculating al of the offsets necessary to do this
13942 arm_encode_section_info (tree decl, rtx rtl, int first)
13944 /* This doesn't work with AOF syntax, since the string table may be in
13945 a different AREA. */
13946 #ifndef AOF_ASSEMBLER
13947 if (optimize > 0 && TREE_CONSTANT (decl))
13948 SYMBOL_REF_FLAG (XEXP (rtl, 0)) = 1;
13951 /* If we are referencing a function that is weak then encode a long call
13952 flag in the function name, otherwise if the function is static or
13953 or known to be defined in this file then encode a short call flag. */
13954 if (first && DECL_P (decl))
13956 if (TREE_CODE (decl) == FUNCTION_DECL && DECL_WEAK (decl))
13957 arm_encode_call_attribute (decl, LONG_CALL_FLAG_CHAR);
13958 else if (! TREE_PUBLIC (decl))
13959 arm_encode_call_attribute (decl, SHORT_CALL_FLAG_CHAR);
13962 #endif /* !ARM_PE */
13965 arm_internal_label (FILE *stream, const char *prefix, unsigned long labelno)
13967 if (arm_ccfsm_state == 3 && (unsigned) arm_target_label == labelno
13968 && !strcmp (prefix, "L"))
13970 arm_ccfsm_state = 0;
13971 arm_target_insn = NULL;
13973 default_internal_label (stream, prefix, labelno);
13976 /* Output code to add DELTA to the first argument, and then jump
13977 to FUNCTION. Used for C++ multiple inheritance. */
13979 arm_output_mi_thunk (FILE *file, tree thunk ATTRIBUTE_UNUSED,
13980 HOST_WIDE_INT delta,
13981 HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED,
13984 static int thunk_label = 0;
13986 int mi_delta = delta;
13987 const char *const mi_op = mi_delta < 0 ? "sub" : "add";
13989 int this_regno = (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function)
13992 mi_delta = - mi_delta;
13995 int labelno = thunk_label++;
13996 ASM_GENERATE_INTERNAL_LABEL (label, "LTHUMBFUNC", labelno);
13997 fputs ("\tldr\tr12, ", file);
13998 assemble_name (file, label);
13999 fputc ('\n', file);
14001 while (mi_delta != 0)
14003 if ((mi_delta & (3 << shift)) == 0)
14007 asm_fprintf (file, "\t%s\t%r, %r, #%d\n",
14008 mi_op, this_regno, this_regno,
14009 mi_delta & (0xff << shift));
14010 mi_delta &= ~(0xff << shift);
14016 fprintf (file, "\tbx\tr12\n");
14017 ASM_OUTPUT_ALIGN (file, 2);
14018 assemble_name (file, label);
14019 fputs (":\n", file);
14020 assemble_integer (XEXP (DECL_RTL (function), 0), 4, BITS_PER_WORD, 1);
14024 fputs ("\tb\t", file);
14025 assemble_name (file, XSTR (XEXP (DECL_RTL (function), 0), 0));
14026 if (NEED_PLT_RELOC)
14027 fputs ("(PLT)", file);
14028 fputc ('\n', file);
14033 arm_emit_vector_const (FILE *file, rtx x)
14036 const char * pattern;
14038 if (GET_CODE (x) != CONST_VECTOR)
14041 switch (GET_MODE (x))
14043 case V2SImode: pattern = "%08x"; break;
14044 case V4HImode: pattern = "%04x"; break;
14045 case V8QImode: pattern = "%02x"; break;
14049 fprintf (file, "0x");
14050 for (i = CONST_VECTOR_NUNITS (x); i--;)
14054 element = CONST_VECTOR_ELT (x, i);
14055 fprintf (file, pattern, INTVAL (element));
14062 arm_output_load_gr (rtx *operands)
14069 if (GET_CODE (operands [1]) != MEM
14070 || GET_CODE (sum = XEXP (operands [1], 0)) != PLUS
14071 || GET_CODE (reg = XEXP (sum, 0)) != REG
14072 || GET_CODE (offset = XEXP (sum, 1)) != CONST_INT
14073 || ((INTVAL (offset) < 1024) && (INTVAL (offset) > -1024)))
14074 return "wldrw%?\t%0, %1";
14076 /* Fix up an out-of-range load of a GR register. */
14077 output_asm_insn ("str%?\t%0, [sp, #-4]!\t@ Start of GR load expansion", & reg);
14078 wcgr = operands[0];
14080 output_asm_insn ("ldr%?\t%0, %1", operands);
14082 operands[0] = wcgr;
14084 output_asm_insn ("tmcr%?\t%0, %1", operands);
14085 output_asm_insn ("ldr%?\t%0, [sp], #4\t@ End of GR load expansion", & reg);
14091 arm_struct_value_rtx (tree fntype ATTRIBUTE_UNUSED,
14092 int incoming ATTRIBUTE_UNUSED)
14095 /* FIXME: The ARM backend has special code to handle structure
14096 returns, and will reserve its own hidden first argument. So
14097 if this macro is enabled a *second* hidden argument will be
14098 reserved, which will break binary compatibility with old
14099 toolchains and also thunk handling. One day this should be
14103 /* Register in which address to store a structure value
14104 is passed to a function. */
14105 return gen_rtx_REG (Pmode, ARG_REGISTER (1));
14109 /* Worker function for TARGET_SETUP_INCOMING_VARARGS.
14111 On the ARM, PRETEND_SIZE is set in order to have the prologue push the last
14112 named arg and all anonymous args onto the stack.
14113 XXX I know the prologue shouldn't be pushing registers, but it is faster
14117 arm_setup_incoming_varargs (CUMULATIVE_ARGS *cum,
14118 enum machine_mode mode ATTRIBUTE_UNUSED,
14119 tree type ATTRIBUTE_UNUSED,
14121 int second_time ATTRIBUTE_UNUSED)
14123 cfun->machine->uses_anonymous_args = 1;
14124 if (cum->nregs < NUM_ARG_REGS)
14125 *pretend_size = (NUM_ARG_REGS - cum->nregs) * UNITS_PER_WORD;
14128 /* Return nonzero if the CONSUMER instruction (a store) does not need
14129 PRODUCER's value to calculate the address. */
14132 arm_no_early_store_addr_dep (rtx producer, rtx consumer)
14134 rtx value = PATTERN (producer);
14135 rtx addr = PATTERN (consumer);
14137 if (GET_CODE (value) == COND_EXEC)
14138 value = COND_EXEC_CODE (value);
14139 if (GET_CODE (value) == PARALLEL)
14140 value = XVECEXP (value, 0, 0);
14141 value = XEXP (value, 0);
14142 if (GET_CODE (addr) == COND_EXEC)
14143 addr = COND_EXEC_CODE (addr);
14144 if (GET_CODE (addr) == PARALLEL)
14145 addr = XVECEXP (addr, 0, 0);
14146 addr = XEXP (addr, 0);
14148 return !reg_overlap_mentioned_p (value, addr);
14151 /* Return nonzero if the CONSUMER instruction (an ALU op) does not
14152 have an early register shift value or amount dependency on the
14153 result of PRODUCER. */
14156 arm_no_early_alu_shift_dep (rtx producer, rtx consumer)
14158 rtx value = PATTERN (producer);
14159 rtx op = PATTERN (consumer);
14162 if (GET_CODE (value) == COND_EXEC)
14163 value = COND_EXEC_CODE (value);
14164 if (GET_CODE (value) == PARALLEL)
14165 value = XVECEXP (value, 0, 0);
14166 value = XEXP (value, 0);
14167 if (GET_CODE (op) == COND_EXEC)
14168 op = COND_EXEC_CODE (op);
14169 if (GET_CODE (op) == PARALLEL)
14170 op = XVECEXP (op, 0, 0);
14173 early_op = XEXP (op, 0);
14174 /* This is either an actual independent shift, or a shift applied to
14175 the first operand of another operation. We want the whole shift
14177 if (GET_CODE (early_op) == REG)
14180 return !reg_overlap_mentioned_p (value, early_op);
14183 /* Return nonzero if the CONSUMER instruction (an ALU op) does not
14184 have an early register shift value dependency on the result of
14188 arm_no_early_alu_shift_value_dep (rtx producer, rtx consumer)
14190 rtx value = PATTERN (producer);
14191 rtx op = PATTERN (consumer);
14194 if (GET_CODE (value) == COND_EXEC)
14195 value = COND_EXEC_CODE (value);
14196 if (GET_CODE (value) == PARALLEL)
14197 value = XVECEXP (value, 0, 0);
14198 value = XEXP (value, 0);
14199 if (GET_CODE (op) == COND_EXEC)
14200 op = COND_EXEC_CODE (op);
14201 if (GET_CODE (op) == PARALLEL)
14202 op = XVECEXP (op, 0, 0);
14205 early_op = XEXP (op, 0);
14207 /* This is either an actual independent shift, or a shift applied to
14208 the first operand of another operation. We want the value being
14209 shifted, in either case. */
14210 if (GET_CODE (early_op) != REG)
14211 early_op = XEXP (early_op, 0);
14213 return !reg_overlap_mentioned_p (value, early_op);
14216 /* Return nonzero if the CONSUMER (a mul or mac op) does not
14217 have an early register mult dependency on the result of
14221 arm_no_early_mul_dep (rtx producer, rtx consumer)
14223 rtx value = PATTERN (producer);
14224 rtx op = PATTERN (consumer);
14226 if (GET_CODE (value) == COND_EXEC)
14227 value = COND_EXEC_CODE (value);
14228 if (GET_CODE (value) == PARALLEL)
14229 value = XVECEXP (value, 0, 0);
14230 value = XEXP (value, 0);
14231 if (GET_CODE (op) == COND_EXEC)
14232 op = COND_EXEC_CODE (op);
14233 if (GET_CODE (op) == PARALLEL)
14234 op = XVECEXP (op, 0, 0);
14237 return (GET_CODE (op) == PLUS
14238 && !reg_overlap_mentioned_p (value, XEXP (op, 0)));
14242 /* We can't rely on the caller doing the proper promotion when
14243 using APCS or ATPCS. */
14246 arm_promote_prototypes (tree t ATTRIBUTE_UNUSED)
14248 return !TARGET_AAPCS_BASED;
14252 /* AAPCS based ABIs use short enums by default. */
14255 arm_default_short_enums (void)
14257 return TARGET_AAPCS_BASED;
14261 /* AAPCS requires that anonymous bitfields affect structure alignment. */
14264 arm_align_anon_bitfield (void)
14266 return TARGET_AAPCS_BASED;
14270 /* The generic C++ ABI says 64-bit (long long). The EABI says 32-bit. */
14273 arm_cxx_guard_type (void)
14275 return TARGET_AAPCS_BASED ? integer_type_node : long_long_integer_type_node;
14279 /* The EABI says test the least significan bit of a guard variable. */
14282 arm_cxx_guard_mask_bit (void)
14284 return TARGET_AAPCS_BASED;
14288 /* The EABI specifies that all array cookies are 8 bytes long. */
14291 arm_get_cookie_size (tree type)
14295 if (!TARGET_AAPCS_BASED)
14296 return default_cxx_get_cookie_size (type);
14298 size = build_int_cst (sizetype, 8);
14303 /* The EABI says that array cookies should also contain the element size. */
14306 arm_cookie_has_size (void)
14308 return TARGET_AAPCS_BASED;
14312 /* The EABI says constructors and destructors should return a pointer to
14313 the object constructed/destroyed. */
14316 arm_cxx_cdtor_returns_this (void)
14318 return TARGET_AAPCS_BASED;
14321 /* The EABI says that an inline function may never be the key
14325 arm_cxx_key_method_may_be_inline (void)
14327 return !TARGET_AAPCS_BASED;
14330 /* The EABI says that the virtual table, etc., for a class must be
14331 exported if it has a key method. The EABI does not specific the
14332 behavior if there is no key method, but there is no harm in
14333 exporting the class data in that case too. */
14336 arm_cxx_export_class_data (void)
14338 return TARGET_AAPCS_BASED;
14342 arm_set_return_address (rtx source, rtx scratch)
14344 arm_stack_offsets *offsets;
14345 HOST_WIDE_INT delta;
14347 unsigned long saved_regs;
14349 saved_regs = arm_compute_save_reg_mask ();
14351 if ((saved_regs & (1 << LR_REGNUM)) == 0)
14352 emit_move_insn (gen_rtx_REG (Pmode, LR_REGNUM), source);
14355 if (frame_pointer_needed)
14356 addr = plus_constant(hard_frame_pointer_rtx, -4);
14359 /* LR will be the first saved register. */
14360 offsets = arm_get_frame_offsets ();
14361 delta = offsets->outgoing_args - (offsets->frame + 4);
14366 emit_insn (gen_addsi3 (scratch, stack_pointer_rtx,
14367 GEN_INT (delta & ~4095)));
14372 addr = stack_pointer_rtx;
14374 addr = plus_constant (addr, delta);
14376 emit_move_insn (gen_rtx_MEM (Pmode, addr), source);
14382 thumb_set_return_address (rtx source, rtx scratch)
14384 arm_stack_offsets *offsets;
14385 HOST_WIDE_INT delta;
14388 unsigned long mask;
14390 emit_insn (gen_rtx_USE (VOIDmode, source));
14392 mask = thumb_compute_save_reg_mask ();
14393 if (mask & (1 << LR_REGNUM))
14395 offsets = arm_get_frame_offsets ();
14397 /* Find the saved regs. */
14398 if (frame_pointer_needed)
14400 delta = offsets->soft_frame - offsets->saved_args;
14401 reg = THUMB_HARD_FRAME_POINTER_REGNUM;
14405 delta = offsets->outgoing_args - offsets->saved_args;
14408 /* Allow for the stack frame. */
14409 if (TARGET_BACKTRACE)
14411 /* The link register is always the first saved register. */
14414 /* Construct the address. */
14415 addr = gen_rtx_REG (SImode, reg);
14416 if ((reg != SP_REGNUM && delta >= 128)
14419 emit_insn (gen_movsi (scratch, GEN_INT (delta)));
14420 emit_insn (gen_addsi3 (scratch, scratch, stack_pointer_rtx));
14424 addr = plus_constant (addr, delta);
14426 emit_move_insn (gen_rtx_MEM (Pmode, addr), source);
14429 emit_move_insn (gen_rtx_REG (Pmode, LR_REGNUM), source);
14432 /* Implements target hook vector_mode_supported_p. */
14434 arm_vector_mode_supported_p (enum machine_mode mode)
14436 if ((mode == V2SImode)
14437 || (mode == V4HImode)
14438 || (mode == V8QImode))
14444 /* Implement TARGET_SHIFT_TRUNCATION_MASK. SImode shifts use normal
14445 ARM insns and therefore guarantee that the shift count is modulo 256.
14446 DImode shifts (those implemented by lib1funcs.asm or by optabs.c)
14447 guarantee no particular behavior for out-of-range counts. */
14449 static unsigned HOST_WIDE_INT
14450 arm_shift_truncation_mask (enum machine_mode mode)
14452 return mode == SImode ? 255 : 0;