1 ;; GCC machine description for Alpha synchronization instructions.
2 ;; Copyright (C) 2005, 2007, 2008, 2009 Free Software Foundation, Inc.
4 ;; This file is part of GCC.
6 ;; GCC is free software; you can redistribute it and/or modify
7 ;; it under the terms of the GNU General Public License as published by
8 ;; the Free Software Foundation; either version 3, or (at your option)
11 ;; GCC is distributed in the hope that it will be useful,
12 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
13 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 ;; GNU General Public License for more details.
16 ;; You should have received a copy of the GNU General Public License
17 ;; along with GCC; see the file COPYING3. If not see
18 ;; <http://www.gnu.org/licenses/>.
20 (define_code_iterator FETCHOP [plus minus ior xor and])
21 (define_code_attr fetchop_name
22 [(plus "add") (minus "sub") (ior "ior") (xor "xor") (and "and")])
23 (define_code_attr fetchop_pred
24 [(plus "add_operand") (minus "reg_or_8bit_operand")
25 (ior "or_operand") (xor "or_operand") (and "and_operand")])
26 (define_code_attr fetchop_constr
27 [(plus "rKL") (minus "rI") (ior "rIN") (xor "rIN") (and "riNHM")])
30 (define_expand "memory_barrier"
32 (unspec:BLK [(match_dup 0)] UNSPEC_MB))]
35 operands[0] = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode));
36 MEM_VOLATILE_P (operands[0]) = 1;
39 (define_insn "*memory_barrier"
40 [(set (match_operand:BLK 0 "" "")
41 (unspec:BLK [(match_dup 0)] UNSPEC_MB))]
44 [(set_attr "type" "mb")])
46 (define_insn "load_locked_<mode>"
47 [(set (match_operand:I48MODE 0 "register_operand" "=r")
48 (unspec_volatile:I48MODE
49 [(match_operand:I48MODE 1 "memory_operand" "m")]
52 "ld<modesuffix>_l %0,%1"
53 [(set_attr "type" "ld_l")])
55 (define_insn "store_conditional_<mode>"
56 [(set (match_operand:DI 0 "register_operand" "=r")
57 (unspec_volatile:DI [(const_int 0)] UNSPECV_SC))
58 (set (match_operand:I48MODE 1 "memory_operand" "=m")
59 (match_operand:I48MODE 2 "reg_or_0_operand" "0"))]
61 "st<modesuffix>_c %0,%1"
62 [(set_attr "type" "st_c")])
64 ;; The Alpha Architecture Handbook says that it is UNPREDICTABLE whether
65 ;; the lock is cleared by a TAKEN branch. This means that we can not
66 ;; expand a ll/sc sequence until after the final basic-block reordering pass.
68 (define_insn_and_split "sync_<fetchop_name><mode>"
69 [(set (match_operand:I48MODE 0 "memory_operand" "+m")
71 [(FETCHOP:I48MODE (match_dup 0)
72 (match_operand:I48MODE 1 "<fetchop_pred>" "<fetchop_constr>"))]
74 (clobber (match_scratch:I48MODE 2 "=&r"))]
80 alpha_split_atomic_op (<CODE>, operands[0], operands[1],
81 NULL, NULL, operands[2]);
84 [(set_attr "type" "multi")])
86 (define_insn_and_split "sync_nand<mode>"
87 [(set (match_operand:I48MODE 0 "memory_operand" "+m")
90 (and:I48MODE (match_dup 0)
91 (match_operand:I48MODE 1 "register_operand" "r")))]
93 (clobber (match_scratch:I48MODE 2 "=&r"))]
99 alpha_split_atomic_op (NOT, operands[0], operands[1],
100 NULL, NULL, operands[2]);
103 [(set_attr "type" "multi")])
105 (define_insn_and_split "sync_old_<fetchop_name><mode>"
106 [(set (match_operand:I48MODE 0 "register_operand" "=&r")
107 (match_operand:I48MODE 1 "memory_operand" "+m"))
110 [(FETCHOP:I48MODE (match_dup 1)
111 (match_operand:I48MODE 2 "<fetchop_pred>" "<fetchop_constr>"))]
113 (clobber (match_scratch:I48MODE 3 "=&r"))]
119 alpha_split_atomic_op (<CODE>, operands[1], operands[2],
120 operands[0], NULL, operands[3]);
123 [(set_attr "type" "multi")])
125 (define_insn_and_split "sync_old_nand<mode>"
126 [(set (match_operand:I48MODE 0 "register_operand" "=&r")
127 (match_operand:I48MODE 1 "memory_operand" "+m"))
131 (and:I48MODE (match_dup 1)
132 (match_operand:I48MODE 2 "register_operand" "r")))]
134 (clobber (match_scratch:I48MODE 3 "=&r"))]
140 alpha_split_atomic_op (NOT, operands[1], operands[2],
141 operands[0], NULL, operands[3]);
144 [(set_attr "type" "multi")])
146 (define_insn_and_split "sync_new_<fetchop_name><mode>"
147 [(set (match_operand:I48MODE 0 "register_operand" "=&r")
149 (match_operand:I48MODE 1 "memory_operand" "+m")
150 (match_operand:I48MODE 2 "<fetchop_pred>" "<fetchop_constr>")))
153 [(FETCHOP:I48MODE (match_dup 1) (match_dup 2))]
155 (clobber (match_scratch:I48MODE 3 "=&r"))]
161 alpha_split_atomic_op (<CODE>, operands[1], operands[2],
162 NULL, operands[0], operands[3]);
165 [(set_attr "type" "multi")])
167 (define_insn_and_split "sync_new_nand<mode>"
168 [(set (match_operand:I48MODE 0 "register_operand" "=&r")
170 (and:I48MODE (match_operand:I48MODE 1 "memory_operand" "+m")
171 (match_operand:I48MODE 2 "register_operand" "r"))))
174 [(not:I48MODE (and:I48MODE (match_dup 1) (match_dup 2)))]
176 (clobber (match_scratch:I48MODE 3 "=&r"))]
182 alpha_split_atomic_op (NOT, operands[1], operands[2],
183 NULL, operands[0], operands[3]);
186 [(set_attr "type" "multi")])
188 (define_expand "sync_compare_and_swap<mode>"
189 [(match_operand:I12MODE 0 "register_operand" "")
190 (match_operand:I12MODE 1 "memory_operand" "")
191 (match_operand:I12MODE 2 "register_operand" "")
192 (match_operand:I12MODE 3 "add_operand" "")]
195 alpha_expand_compare_and_swap_12 (operands[0], operands[1],
196 operands[2], operands[3]);
200 (define_insn_and_split "sync_compare_and_swap<mode>_1"
201 [(set (match_operand:DI 0 "register_operand" "=&r,&r")
203 (mem:I12MODE (match_operand:DI 1 "register_operand" "r,r"))))
204 (set (mem:I12MODE (match_dup 1))
206 [(match_operand:DI 2 "reg_or_8bit_operand" "J,rI")
207 (match_operand:DI 3 "register_operand" "r,r")
208 (match_operand:DI 4 "register_operand" "r,r")]
210 (clobber (match_scratch:DI 5 "=&r,&r"))
211 (clobber (match_scratch:DI 6 "=X,&r"))]
217 alpha_split_compare_and_swap_12 (<MODE>mode, operands[0], operands[1],
218 operands[2], operands[3], operands[4],
219 operands[5], operands[6]);
222 [(set_attr "type" "multi")])
224 (define_expand "sync_compare_and_swap<mode>"
226 [(set (match_operand:I48MODE 0 "register_operand" "")
227 (match_operand:I48MODE 1 "memory_operand" ""))
230 [(match_operand:I48MODE 2 "reg_or_8bit_operand" "")
231 (match_operand:I48MODE 3 "add_operand" "rKL")]
233 (clobber (match_scratch:I48MODE 4 "=&r"))])]
236 if (<MODE>mode == SImode)
237 operands[2] = convert_modes (DImode, SImode, operands[2], 0);
240 (define_insn_and_split "*sync_compare_and_swap<mode>"
241 [(set (match_operand:I48MODE 0 "register_operand" "=&r")
242 (match_operand:I48MODE 1 "memory_operand" "+m"))
245 [(match_operand:DI 2 "reg_or_8bit_operand" "rI")
246 (match_operand:I48MODE 3 "add_operand" "rKL")]
248 (clobber (match_scratch:I48MODE 4 "=&r"))]
254 alpha_split_compare_and_swap (operands[0], operands[1], operands[2],
255 operands[3], operands[4]);
258 [(set_attr "type" "multi")])
260 (define_expand "sync_lock_test_and_set<mode>"
261 [(match_operand:I12MODE 0 "register_operand" "")
262 (match_operand:I12MODE 1 "memory_operand" "")
263 (match_operand:I12MODE 2 "register_operand" "")]
266 alpha_expand_lock_test_and_set_12 (operands[0], operands[1], operands[2]);
270 (define_insn_and_split "sync_lock_test_and_set<mode>_1"
271 [(set (match_operand:DI 0 "register_operand" "=&r")
273 (mem:I12MODE (match_operand:DI 1 "register_operand" "r"))))
274 (set (mem:I12MODE (match_dup 1))
276 [(match_operand:DI 2 "reg_or_8bit_operand" "rI")
277 (match_operand:DI 3 "register_operand" "r")]
279 (clobber (match_scratch:DI 4 "=&r"))]
285 alpha_split_lock_test_and_set_12 (<MODE>mode, operands[0], operands[1],
286 operands[2], operands[3], operands[4]);
289 [(set_attr "type" "multi")])
291 (define_insn_and_split "sync_lock_test_and_set<mode>"
292 [(set (match_operand:I48MODE 0 "register_operand" "=&r")
293 (match_operand:I48MODE 1 "memory_operand" "+m"))
296 [(match_operand:I48MODE 2 "add_operand" "rKL")]
298 (clobber (match_scratch:I48MODE 3 "=&r"))]
304 alpha_split_lock_test_and_set (operands[0], operands[1],
305 operands[2], operands[3]);
308 [(set_attr "type" "multi")])