1 /* Definitions of target machine for GNU compiler, for DEC Alpha.
2 Copyright (C) 1992, 93-98, 1999 Free Software Foundation, Inc.
3 Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
5 This file is part of GNU CC.
7 GNU CC is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GNU CC is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GNU CC; see the file COPYING. If not, write to
19 the Free Software Foundation, 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
23 /* Write out the correct language type definition for the header files.
24 Unless we have assembler language, write out the symbols for C. */
27 %{.S:-D__LANGUAGE_ASSEMBLY__ -D__LANGUAGE_ASSEMBLY %{!ansi:-DLANGUAGE_ASSEMBLY }}\
28 %{.cc|.cxx|.C:-D__LANGUAGE_C_PLUS_PLUS__ -D__LANGUAGE_C_PLUS_PLUS -D__cplusplus }\
29 %{.m:-D__LANGUAGE_OBJECTIVE_C__ -D__LANGUAGE_OBJECTIVE_C }\
30 %{!.S:%{!.cc:%{!.cxx:%{!.C:%{!.m:-D__LANGUAGE_C__ -D__LANGUAGE_C %{!ansi:-DLANGUAGE_C }}}}}}\
32 %{mieee-with-inexact:-D_IEEE_FP -D_IEEE_FP_INEXACT }}\
33 %(cpp_cpu) %(cpp_subtarget)"
35 #ifndef CPP_SUBTARGET_SPEC
36 #define CPP_SUBTARGET_SPEC ""
39 /* Set the spec to use for signed char. The default tests the above macro
40 but DEC's compiler can't handle the conditional in a "constant"
43 #define SIGNED_CHAR_SPEC "%{funsigned-char:-D__CHAR_UNSIGNED__}"
45 #define WORD_SWITCH_TAKES_ARG(STR) \
46 (!strcmp (STR, "rpath") || !strcmp (STR, "include") \
47 || !strcmp (STR, "imacros") || !strcmp (STR, "aux-info") \
48 || !strcmp (STR, "idirafter") || !strcmp (STR, "iprefix") \
49 || !strcmp (STR, "iwithprefix") || !strcmp (STR, "iwithprefixbefore") \
50 || !strcmp (STR, "isystem"))
52 /* Print subsidiary information on the compiler version in use. */
53 #define TARGET_VERSION
55 /* Run-time compilation parameters selecting different hardware subsets. */
57 /* Which processor to schedule for. The cpu attribute defines a list that
58 mirrors this list, so changes to alpha.md must be made at the same time. */
61 {PROCESSOR_EV4, /* 2106[46]{a,} */
62 PROCESSOR_EV5, /* 21164{a,pc,} */
63 PROCESSOR_EV6}; /* 21264 */
65 extern enum processor_type alpha_cpu;
67 enum alpha_trap_precision
69 ALPHA_TP_PROG, /* No precision (default). */
70 ALPHA_TP_FUNC, /* Trap contained within originating function. */
71 ALPHA_TP_INSN /* Instruction accuracy and code is resumption safe. */
74 enum alpha_fp_rounding_mode
76 ALPHA_FPRM_NORM, /* Normal rounding mode. */
77 ALPHA_FPRM_MINF, /* Round towards minus-infinity. */
78 ALPHA_FPRM_CHOP, /* Chopped rounding mode (towards 0). */
79 ALPHA_FPRM_DYN /* Dynamic rounding mode. */
82 enum alpha_fp_trap_mode
84 ALPHA_FPTM_N, /* Normal trap mode. */
85 ALPHA_FPTM_U, /* Underflow traps enabled. */
86 ALPHA_FPTM_SU, /* Software completion, w/underflow traps */
87 ALPHA_FPTM_SUI /* Software completion, w/underflow & inexact traps */
90 extern int target_flags;
92 extern enum alpha_trap_precision alpha_tp;
93 extern enum alpha_fp_rounding_mode alpha_fprm;
94 extern enum alpha_fp_trap_mode alpha_fptm;
96 /* This means that floating-point support exists in the target implementation
97 of the Alpha architecture. This is usually the default. */
98 #define MASK_FP (1 << 0)
99 #define TARGET_FP (target_flags & MASK_FP)
101 /* This means that floating-point registers are allowed to be used. Note
102 that Alpha implementations without FP operations are required to
103 provide the FP registers. */
105 #define MASK_FPREGS (1 << 1)
106 #define TARGET_FPREGS (target_flags & MASK_FPREGS)
108 /* This means that gas is used to process the assembler file. */
110 #define MASK_GAS (1 << 2)
111 #define TARGET_GAS (target_flags & MASK_GAS)
113 /* This means that we should mark procedures as IEEE conformant. */
115 #define MASK_IEEE_CONFORMANT (1 << 3)
116 #define TARGET_IEEE_CONFORMANT (target_flags & MASK_IEEE_CONFORMANT)
118 /* This means we should be IEEE-compliant except for inexact. */
120 #define MASK_IEEE (1 << 4)
121 #define TARGET_IEEE (target_flags & MASK_IEEE)
123 /* This means we should be fully IEEE-compliant. */
125 #define MASK_IEEE_WITH_INEXACT (1 << 5)
126 #define TARGET_IEEE_WITH_INEXACT (target_flags & MASK_IEEE_WITH_INEXACT)
128 /* This means we must construct all constants rather than emitting
129 them as literal data. */
131 #define MASK_BUILD_CONSTANTS (1 << 6)
132 #define TARGET_BUILD_CONSTANTS (target_flags & MASK_BUILD_CONSTANTS)
134 /* This means we handle floating points in VAX F- (float)
135 or G- (double) Format. */
137 #define MASK_FLOAT_VAX (1 << 7)
138 #define TARGET_FLOAT_VAX (target_flags & MASK_FLOAT_VAX)
140 /* This means that the processor has byte and half word loads and stores
141 (the BWX extension). */
143 #define MASK_BWX (1 << 8)
144 #define TARGET_BWX (target_flags & MASK_BWX)
146 /* This means that the processor has the MAX extension. */
147 #define MASK_MAX (1 << 9)
148 #define TARGET_MAX (target_flags & MASK_MAX)
150 /* This means that the processor has the FIX extension. */
151 #define MASK_FIX (1 << 10)
152 #define TARGET_FIX (target_flags & MASK_FIX)
154 /* This means that the processor has the CIX extension. */
155 #define MASK_CIX (1 << 11)
156 #define TARGET_CIX (target_flags & MASK_CIX)
158 /* This means that the processor is an EV5, EV56, or PCA56. This is defined
159 only in TARGET_CPU_DEFAULT. */
160 #define MASK_CPU_EV5 (1 << 28)
162 /* Likewise for EV6. */
163 #define MASK_CPU_EV6 (1 << 29)
165 /* This means we support the .arch directive in the assembler. Only
166 defined in TARGET_CPU_DEFAULT. */
167 #define MASK_SUPPORT_ARCH (1 << 30)
168 #define TARGET_SUPPORT_ARCH (target_flags & MASK_SUPPORT_ARCH)
170 /* These are for target os support and cannot be changed at runtime. */
171 #ifndef TARGET_WINDOWS_NT
172 #define TARGET_WINDOWS_NT 0
174 #ifndef TARGET_OPEN_VMS
175 #define TARGET_OPEN_VMS 0
178 #ifndef TARGET_AS_CAN_SUBTRACT_LABELS
179 #define TARGET_AS_CAN_SUBTRACT_LABELS TARGET_GAS
181 #ifndef TARGET_CAN_FAULT_IN_PROLOGUE
182 #define TARGET_CAN_FAULT_IN_PROLOGUE 0
185 /* Macro to define tables used to set the flags.
186 This is a list in braces of pairs in braces,
187 each pair being { "NAME", VALUE }
188 where VALUE is the bits to set or minus the bits to clear.
189 An empty string NAME is used to identify the default VALUE. */
191 #define TARGET_SWITCHES \
192 { {"no-soft-float", MASK_FP, "Use hardware fp"}, \
193 {"soft-float", - MASK_FP, "Do not use hardware fp"}, \
194 {"fp-regs", MASK_FPREGS, "Use fp registers"}, \
195 {"no-fp-regs", - (MASK_FP|MASK_FPREGS), "Do not use fp registers"}, \
196 {"alpha-as", -MASK_GAS, "Do not assume GAS"}, \
197 {"gas", MASK_GAS, "Assume GAS"}, \
198 {"ieee-conformant", MASK_IEEE_CONFORMANT, \
199 "Request IEEE-conformant math library routines (OSF/1)"}, \
200 {"ieee", MASK_IEEE|MASK_IEEE_CONFORMANT, \
201 "Emit IEEE-conformant code, without inexact exceptions"}, \
202 {"ieee-with-inexact", MASK_IEEE_WITH_INEXACT|MASK_IEEE_CONFORMANT, \
203 "Emit IEEE-conformant code, with inexact exceptions"}, \
204 {"build-constants", MASK_BUILD_CONSTANTS, \
205 "Do not emit complex integer constants to read-only memory"}, \
206 {"float-vax", MASK_FLOAT_VAX, "Use VAX fp"}, \
207 {"float-ieee", -MASK_FLOAT_VAX, "Do not use VAX fp"}, \
208 {"bwx", MASK_BWX, "Emit code for the byte/word ISA extension"}, \
209 {"no-bwx", -MASK_BWX, ""}, \
210 {"max", MASK_MAX, "Emit code for the motion video ISA extension"}, \
211 {"no-max", -MASK_MAX, ""}, \
212 {"fix", MASK_FIX, "Emit code for the fp move and sqrt ISA extension"}, \
213 {"no-fix", -MASK_FIX, ""}, \
214 {"cix", MASK_CIX, "Emit code for the counting ISA extension"}, \
215 {"no-cix", -MASK_CIX, ""}, \
216 {"", TARGET_DEFAULT | TARGET_CPU_DEFAULT, ""} }
218 #define TARGET_DEFAULT MASK_FP|MASK_FPREGS
220 #ifndef TARGET_CPU_DEFAULT
221 #define TARGET_CPU_DEFAULT 0
224 /* This macro is similar to `TARGET_SWITCHES' but defines names of
225 command options that have values. Its definition is an initializer
226 with a subgrouping for each command option.
228 Each subgrouping contains a string constant, that defines the fixed
229 part of the option name, and the address of a variable. The
230 variable, type `char *', is set to the variable part of the given
231 option if the fixed part matches. The actual option name is made
232 by appending `-m' to the specified name.
234 Here is an example which defines `-mshort-data-NUMBER'. If the
235 given option is `-mshort-data-512', the variable `m88k_short_data'
236 will be set to the string `"512"'.
238 extern char *m88k_short_data;
239 #define TARGET_OPTIONS { { "short-data-", &m88k_short_data } } */
241 extern const char *alpha_cpu_string; /* For -mcpu= */
242 extern const char *alpha_fprm_string; /* For -mfp-rounding-mode=[n|m|c|d] */
243 extern const char *alpha_fptm_string; /* For -mfp-trap-mode=[n|u|su|sui] */
244 extern const char *alpha_tp_string; /* For -mtrap-precision=[p|f|i] */
245 extern const char *alpha_mlat_string; /* For -mmemory-latency= */
247 #define TARGET_OPTIONS \
249 {"cpu=", &alpha_cpu_string, \
250 "Generate code for a given CPU"}, \
251 {"fp-rounding-mode=", &alpha_fprm_string, \
252 "Control the generated fp rounding mode"}, \
253 {"fp-trap-mode=", &alpha_fptm_string, \
254 "Control the IEEE trap mode"}, \
255 {"trap-precision=", &alpha_tp_string, \
256 "Control the precision given to fp exceptions"}, \
257 {"memory-latency=", &alpha_mlat_string, \
258 "Tune expected memory latency"}, \
261 /* Attempt to describe CPU characteristics to the preprocessor. */
263 /* Corresponding to amask... */
264 #define CPP_AM_BWX_SPEC "-D__alpha_bwx__ -Acpu(bwx)"
265 #define CPP_AM_MAX_SPEC "-D__alpha_max__ -Acpu(max)"
266 #define CPP_AM_FIX_SPEC "-D__alpha_fix__ -Acpu(fix)"
267 #define CPP_AM_CIX_SPEC "-D__alpha_cix__ -Acpu(cix)"
269 /* Corresponding to implver... */
270 #define CPP_IM_EV4_SPEC "-D__alpha_ev4__ -Acpu(ev4)"
271 #define CPP_IM_EV5_SPEC "-D__alpha_ev5__ -Acpu(ev5)"
272 #define CPP_IM_EV6_SPEC "-D__alpha_ev6__ -Acpu(ev6)"
274 /* Common combinations. */
275 #define CPP_CPU_EV4_SPEC "%(cpp_im_ev4)"
276 #define CPP_CPU_EV5_SPEC "%(cpp_im_ev5)"
277 #define CPP_CPU_EV56_SPEC "%(cpp_im_ev5) %(cpp_am_bwx)"
278 #define CPP_CPU_PCA56_SPEC "%(cpp_im_ev5) %(cpp_am_bwx) %(cpp_am_max)"
279 #define CPP_CPU_EV6_SPEC "%(cpp_im_ev6) %(cpp_am_bwx) %(cpp_am_max) %(cpp_am_fix)"
281 #ifndef CPP_CPU_DEFAULT_SPEC
282 # if TARGET_CPU_DEFAULT & MASK_CPU_EV6
283 # define CPP_CPU_DEFAULT_SPEC CPP_CPU_EV6_SPEC
285 # if TARGET_CPU_DEFAULT & MASK_CPU_EV5
286 # if TARGET_CPU_DEFAULT & MASK_MAX
287 # define CPP_CPU_DEFAULT_SPEC CPP_CPU_PCA56_SPEC
289 # if TARGET_CPU_DEFAULT & MASK_BWX
290 # define CPP_CPU_DEFAULT_SPEC CPP_CPU_EV56_SPEC
292 # define CPP_CPU_DEFAULT_SPEC CPP_CPU_EV5_SPEC
296 # define CPP_CPU_DEFAULT_SPEC CPP_CPU_EV4_SPEC
299 #endif /* CPP_CPU_DEFAULT_SPEC */
302 #define CPP_CPU_SPEC "\
303 %{!undef:-Acpu(alpha) -Amachine(alpha) -D__alpha -D__alpha__ \
304 %{mcpu=ev4|mcpu=21064:%(cpp_cpu_ev4) }\
305 %{mcpu=ev5|mcpu=21164:%(cpp_cpu_ev5) }\
306 %{mcpu=ev56|mcpu=21164a:%(cpp_cpu_ev56) }\
307 %{mcpu=pca56|mcpu=21164pc|mcpu=21164PC:%(cpp_cpu_pca56) }\
308 %{mcpu=ev6|mcpu=21264:%(cpp_cpu_ev6) }\
309 %{!mcpu*:%(cpp_cpu_default) }}"
312 /* This macro defines names of additional specifications to put in the
313 specs that can be used in various specifications like CC1_SPEC. Its
314 definition is an initializer with a subgrouping for each command option.
316 Each subgrouping contains a string constant, that defines the
317 specification name, and a string constant that used by the GNU CC driver
320 Do not define this macro if it does not need to do anything. */
322 #ifndef SUBTARGET_EXTRA_SPECS
323 #define SUBTARGET_EXTRA_SPECS
326 #define EXTRA_SPECS \
327 { "cpp_am_bwx", CPP_AM_BWX_SPEC }, \
328 { "cpp_am_max", CPP_AM_MAX_SPEC }, \
329 { "cpp_am_fix", CPP_AM_FIX_SPEC }, \
330 { "cpp_am_cix", CPP_AM_CIX_SPEC }, \
331 { "cpp_im_ev4", CPP_IM_EV4_SPEC }, \
332 { "cpp_im_ev5", CPP_IM_EV5_SPEC }, \
333 { "cpp_im_ev6", CPP_IM_EV6_SPEC }, \
334 { "cpp_cpu_ev4", CPP_CPU_EV4_SPEC }, \
335 { "cpp_cpu_ev5", CPP_CPU_EV5_SPEC }, \
336 { "cpp_cpu_ev56", CPP_CPU_EV56_SPEC }, \
337 { "cpp_cpu_pca56", CPP_CPU_PCA56_SPEC }, \
338 { "cpp_cpu_ev6", CPP_CPU_EV6_SPEC }, \
339 { "cpp_cpu_default", CPP_CPU_DEFAULT_SPEC }, \
340 { "cpp_cpu", CPP_CPU_SPEC }, \
341 { "cpp_subtarget", CPP_SUBTARGET_SPEC }, \
342 SUBTARGET_EXTRA_SPECS
345 /* Sometimes certain combinations of command options do not make sense
346 on a particular target machine. You can define a macro
347 `OVERRIDE_OPTIONS' to take account of this. This macro, if
348 defined, is executed once just after all the command options have
351 On the Alpha, it is used to translate target-option strings into
354 #define OVERRIDE_OPTIONS override_options ()
357 /* Define this macro to change register usage conditional on target flags.
359 On the Alpha, we use this to disable the floating-point registers when
362 #define CONDITIONAL_REGISTER_USAGE \
363 if (! TARGET_FPREGS) \
364 for (i = 32; i < 63; i++) \
365 fixed_regs[i] = call_used_regs[i] = 1;
367 /* Show we can debug even without a frame pointer. */
368 #define CAN_DEBUG_WITHOUT_FP
370 /* target machine storage layout */
372 /* Define to enable software floating point emulation. */
373 #define REAL_ARITHMETIC
375 /* The following #defines are used when compiling the routines in
376 libgcc1.c. Since the Alpha calling conventions require single
377 precision floats to be passed in the floating-point registers
378 (rather than in the general registers) we have to build the
379 libgcc1.c routines in such a way that they know the actual types
380 of their formal arguments and the actual types of their return
381 values. Otherwise, gcc will generate calls to the libgcc1.c
382 routines, passing arguments in the floating-point registers,
383 but the libgcc1.c routines will expect their arguments on the
384 stack (where the Alpha calling conventions require structs &
385 unions to be passed). */
387 #define FLOAT_VALUE_TYPE double
388 #define INTIFY(FLOATVAL) (FLOATVAL)
389 #define FLOATIFY(INTVAL) (INTVAL)
390 #define FLOAT_ARG_TYPE double
392 /* Define the size of `int'. The default is the same as the word size. */
393 #define INT_TYPE_SIZE 32
395 /* Define the size of `long long'. The default is the twice the word size. */
396 #define LONG_LONG_TYPE_SIZE 64
398 /* The two floating-point formats we support are S-floating, which is
399 4 bytes, and T-floating, which is 8 bytes. `float' is S and `double'
400 and `long double' are T. */
402 #define FLOAT_TYPE_SIZE 32
403 #define DOUBLE_TYPE_SIZE 64
404 #define LONG_DOUBLE_TYPE_SIZE 64
406 #define WCHAR_TYPE "unsigned int"
407 #define WCHAR_TYPE_SIZE 32
409 /* Define this macro if it is advisable to hold scalars in registers
410 in a wider mode than that declared by the program. In such cases,
411 the value is constrained to be within the bounds of the declared
412 type, but kept valid in the wider mode. The signedness of the
413 extension may differ from that of the type.
415 For Alpha, we always store objects in a full register. 32-bit objects
416 are always sign-extended, but smaller objects retain their signedness. */
418 #define PROMOTE_MODE(MODE,UNSIGNEDP,TYPE) \
419 if (GET_MODE_CLASS (MODE) == MODE_INT \
420 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \
422 if ((MODE) == SImode) \
427 /* Define this if function arguments should also be promoted using the above
430 #define PROMOTE_FUNCTION_ARGS
432 /* Likewise, if the function return value is promoted. */
434 #define PROMOTE_FUNCTION_RETURN
436 /* Define this if most significant bit is lowest numbered
437 in instructions that operate on numbered bit-fields.
439 There are no such instructions on the Alpha, but the documentation
441 #define BITS_BIG_ENDIAN 0
443 /* Define this if most significant byte of a word is the lowest numbered.
444 This is false on the Alpha. */
445 #define BYTES_BIG_ENDIAN 0
447 /* Define this if most significant word of a multiword number is lowest
450 For Alpha we can decide arbitrarily since there are no machine instructions
451 for them. Might as well be consistent with bytes. */
452 #define WORDS_BIG_ENDIAN 0
454 /* number of bits in an addressable storage unit */
455 #define BITS_PER_UNIT 8
457 /* Width in bits of a "word", which is the contents of a machine register.
458 Note that this is not necessarily the width of data type `int';
459 if using 16-bit ints on a 68000, this would still be 32.
460 But on a machine with 16-bit registers, this would be 16. */
461 #define BITS_PER_WORD 64
463 /* Width of a word, in units (bytes). */
464 #define UNITS_PER_WORD 8
466 /* Width in bits of a pointer.
467 See also the macro `Pmode' defined below. */
468 #define POINTER_SIZE 64
470 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
471 #define PARM_BOUNDARY 64
473 /* Boundary (in *bits*) on which stack pointer should be aligned. */
474 #define STACK_BOUNDARY 64
476 /* Allocation boundary (in *bits*) for the code of a function. */
477 #define FUNCTION_BOUNDARY 256
479 /* Alignment of field after `int : 0' in a structure. */
480 #define EMPTY_FIELD_BOUNDARY 64
482 /* Every structure's size must be a multiple of this. */
483 #define STRUCTURE_SIZE_BOUNDARY 8
485 /* A bitfield declared as `int' forces `int' alignment for the struct. */
486 #define PCC_BITFIELD_TYPE_MATTERS 1
488 /* Align loop starts for optimal branching.
490 ??? Kludge this and the next macro for the moment by not doing anything if
491 we don't optimize and also if we are writing ECOFF symbols to work around
492 a bug in DEC's assembler. */
494 #define LOOP_ALIGN(LABEL) \
495 (optimize > 0 && write_symbols != SDB_DEBUG ? 4 : 0)
497 /* This is how to align an instruction for optimal branching. On
498 Alpha we'll get better performance by aligning on an octaword
501 #define LABEL_ALIGN_AFTER_BARRIER(FILE) \
502 (optimize > 0 && write_symbols != SDB_DEBUG ? 4 : 0)
504 /* No data type wants to be aligned rounder than this. */
505 #define BIGGEST_ALIGNMENT 64
507 /* For atomic access to objects, must have at least 32-bit alignment
508 unless the machine has byte operations. */
509 #define MINIMUM_ATOMIC_ALIGNMENT (TARGET_BWX ? 8 : 32)
511 /* Align all constants and variables to at least a word boundary so
512 we can pick up pieces of them faster. */
513 /* ??? Only if block-move stuff knows about different source/destination
516 #define CONSTANT_ALIGNMENT(EXP, ALIGN) MAX ((ALIGN), BITS_PER_WORD)
517 #define DATA_ALIGNMENT(EXP, ALIGN) MAX ((ALIGN), BITS_PER_WORD)
520 /* Set this non-zero if move instructions will actually fail to work
521 when given unaligned data.
523 Since we get an error message when we do one, call them invalid. */
525 #define STRICT_ALIGNMENT 1
527 /* Set this non-zero if unaligned move instructions are extremely slow.
529 On the Alpha, they trap. */
531 #define SLOW_UNALIGNED_ACCESS 1
533 /* Standard register usage. */
535 /* Number of actual hardware registers.
536 The hardware registers are assigned numbers for the compiler
537 from 0 to just below FIRST_PSEUDO_REGISTER.
538 All registers that the compiler knows about must be given numbers,
539 even those that are not normally considered general registers.
541 We define all 32 integer registers, even though $31 is always zero,
542 and all 32 floating-point registers, even though $f31 is also
543 always zero. We do not bother defining the FP status register and
544 there are no other registers.
546 Since $31 is always zero, we will use register number 31 as the
547 argument pointer. It will never appear in the generated code
548 because we will always be eliminating it in favor of the stack
549 pointer or hardware frame pointer.
551 Likewise, we use $f31 for the frame pointer, which will always
552 be eliminated in favor of the hardware frame pointer or the
555 #define FIRST_PSEUDO_REGISTER 64
557 /* 1 for registers that have pervasive standard uses
558 and are not available for the register allocator. */
560 #define FIXED_REGISTERS \
561 {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
562 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, \
563 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
564 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1 }
566 /* 1 for registers not available across function calls.
567 These must include the FIXED_REGISTERS and also any
568 registers that can be used without being saved.
569 The latter must include the registers where values are returned
570 and the register where structure-value addresses are passed.
571 Aside from that, you can include as many other registers as you like. */
572 #define CALL_USED_REGISTERS \
573 {1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, \
574 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, \
575 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, \
576 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 }
578 /* List the order in which to allocate registers. Each register must be
579 listed once, even those in FIXED_REGISTERS.
581 We allocate in the following order:
582 $f10-$f15 (nonsaved floating-point register)
584 $f21-$f16 (likewise, but input args)
585 $f0 (nonsaved, but return value)
586 $f1 (nonsaved, but immediate before saved)
587 $f2-$f9 (saved floating-point registers)
588 $1-$8 (nonsaved integer registers)
591 $0 (likewise, but return value)
592 $21-$16 (likewise, but input args)
593 $27 (procedure value in OSF, nonsaved in NT)
594 $9-$14 (saved integer registers)
598 $30, $31, $f31 (stack pointer and always zero/ap & fp) */
600 #define REG_ALLOC_ORDER \
601 {42, 43, 44, 45, 46, 47, \
602 54, 55, 56, 57, 58, 59, 60, 61, 62, \
603 53, 52, 51, 50, 49, 48, \
605 34, 35, 36, 37, 38, 39, 40, 41, \
606 1, 2, 3, 4, 5, 6, 7, 8, \
610 21, 20, 19, 18, 17, 16, \
612 9, 10, 11, 12, 13, 14, \
618 /* Return number of consecutive hard regs needed starting at reg REGNO
619 to hold something of mode MODE.
620 This is ordinarily the length in words of a value of mode MODE
621 but can be less for certain modes in special long registers. */
623 #define HARD_REGNO_NREGS(REGNO, MODE) \
624 ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
626 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
627 On Alpha, the integer registers can hold any mode. The floating-point
628 registers can hold 32-bit and 64-bit integers as well, but not 16-bit
631 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
632 ((REGNO) >= 32 && (REGNO) <= 62 \
633 ? GET_MODE_UNIT_SIZE (MODE) == 8 || GET_MODE_UNIT_SIZE (MODE) == 4 \
636 /* A C expression that is nonzero if a value of mode
637 MODE1 is accessible in mode MODE2 without copying.
639 This asymmetric test is true when MODE1 could be put
640 in an FP register but MODE2 could not. */
642 #define MODES_TIEABLE_P(MODE1, MODE2) \
643 (HARD_REGNO_MODE_OK (32, (MODE1)) \
644 ? HARD_REGNO_MODE_OK (32, (MODE2)) \
647 /* Specify the registers used for certain standard purposes.
648 The values of these macros are register numbers. */
650 /* Alpha pc isn't overloaded on a register that the compiler knows about. */
651 /* #define PC_REGNUM */
653 /* Register to use for pushing function arguments. */
654 #define STACK_POINTER_REGNUM 30
656 /* Base register for access to local variables of the function. */
657 #define HARD_FRAME_POINTER_REGNUM 15
659 /* Value should be nonzero if functions must have frame pointers.
660 Zero means the frame pointer need not be set up (and parms
661 may be accessed via the stack pointer) in functions that seem suitable.
662 This is computed in `reload', in reload1.c. */
663 #define FRAME_POINTER_REQUIRED 0
665 /* Base register for access to arguments of the function. */
666 #define ARG_POINTER_REGNUM 31
668 /* Base register for access to local variables of function. */
669 #define FRAME_POINTER_REGNUM 63
671 /* Register in which static-chain is passed to a function.
673 For the Alpha, this is based on an example; the calling sequence
674 doesn't seem to specify this. */
675 #define STATIC_CHAIN_REGNUM 1
677 /* Register in which address to store a structure value
678 arrives in the function. On the Alpha, the address is passed
679 as a hidden argument. */
680 #define STRUCT_VALUE 0
682 /* Define the classes of registers for register constraints in the
683 machine description. Also define ranges of constants.
685 One of the classes must always be named ALL_REGS and include all hard regs.
686 If there is more than one class, another class must be named NO_REGS
687 and contain no registers.
689 The name GENERAL_REGS must be the name of a class (or an alias for
690 another name such as ALL_REGS). This is the class of registers
691 that is allowed by "g" or "r" in a register constraint.
692 Also, registers outside this class are allocated only when
693 instructions express preferences for them.
695 The classes must be numbered in nondecreasing order; that is,
696 a larger-numbered class must never be contained completely
697 in a smaller-numbered class.
699 For any two classes, it is very desirable that there be another
700 class that represents their union. */
702 enum reg_class { NO_REGS, GENERAL_REGS, FLOAT_REGS, ALL_REGS,
705 #define N_REG_CLASSES (int) LIM_REG_CLASSES
707 /* Give names of register classes as strings for dump file. */
709 #define REG_CLASS_NAMES \
710 {"NO_REGS", "GENERAL_REGS", "FLOAT_REGS", "ALL_REGS" }
712 /* Define which registers fit in which classes.
713 This is an initializer for a vector of HARD_REG_SET
714 of length N_REG_CLASSES. */
716 #define REG_CLASS_CONTENTS \
717 { {0, 0}, {~0, 0x80000000}, {0, 0x7fffffff}, {~0, ~0} }
719 /* The same information, inverted:
720 Return the class number of the smallest class containing
721 reg number REGNO. This could be a conditional expression
722 or could index an array. */
724 #define REGNO_REG_CLASS(REGNO) \
725 ((REGNO) >= 32 && (REGNO) <= 62 ? FLOAT_REGS : GENERAL_REGS)
727 /* The class value for index registers, and the one for base regs. */
728 #define INDEX_REG_CLASS NO_REGS
729 #define BASE_REG_CLASS GENERAL_REGS
731 /* Get reg_class from a letter such as appears in the machine description. */
733 #define REG_CLASS_FROM_LETTER(C) \
734 ((C) == 'f' ? FLOAT_REGS : NO_REGS)
736 /* Define this macro to change register usage conditional on target flags. */
737 /* #define CONDITIONAL_REGISTER_USAGE */
739 /* The letters I, J, K, L, M, N, O, and P in a register constraint string
740 can be used to stand for particular ranges of immediate operands.
741 This macro defines what the ranges are.
742 C is the letter, and VALUE is a constant value.
743 Return 1 if VALUE is in the range specified by C.
746 `I' is used for the range of constants most insns can contain.
747 `J' is the constant zero.
748 `K' is used for the constant in an LDA insn.
749 `L' is used for the constant in a LDAH insn.
750 `M' is used for the constants that can be AND'ed with using a ZAP insn.
751 `N' is used for complemented 8-bit constants.
752 `O' is used for negated 8-bit constants.
753 `P' is used for the constants 1, 2 and 3. */
755 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
756 ((C) == 'I' ? (unsigned HOST_WIDE_INT) (VALUE) < 0x100 \
757 : (C) == 'J' ? (VALUE) == 0 \
758 : (C) == 'K' ? (unsigned HOST_WIDE_INT) ((VALUE) + 0x8000) < 0x10000 \
759 : (C) == 'L' ? (((VALUE) & 0xffff) == 0 \
760 && (((VALUE)) >> 31 == -1 || (VALUE) >> 31 == 0)) \
761 : (C) == 'M' ? zap_mask (VALUE) \
762 : (C) == 'N' ? (unsigned HOST_WIDE_INT) (~ (VALUE)) < 0x100 \
763 : (C) == 'O' ? (unsigned HOST_WIDE_INT) (- (VALUE)) < 0x100 \
764 : (C) == 'P' ? (VALUE) == 1 || (VALUE) == 2 || (VALUE) == 3 \
767 /* Similar, but for floating or large integer constants, and defining letters
768 G and H. Here VALUE is the CONST_DOUBLE rtx itself.
770 For Alpha, `G' is the floating-point constant zero. `H' is a CONST_DOUBLE
771 that is the operand of a ZAP insn. */
773 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
774 ((C) == 'G' ? (GET_MODE_CLASS (GET_MODE (VALUE)) == MODE_FLOAT \
775 && (VALUE) == CONST0_RTX (GET_MODE (VALUE))) \
776 : (C) == 'H' ? (GET_MODE (VALUE) == VOIDmode \
777 && zap_mask (CONST_DOUBLE_LOW (VALUE)) \
778 && zap_mask (CONST_DOUBLE_HIGH (VALUE))) \
781 /* Optional extra constraints for this machine.
783 For the Alpha, `Q' means that this is a memory operand but not a
784 reference to an unaligned location.
786 `R' is a SYMBOL_REF that has SYMBOL_REF_FLAG set or is the current
789 'S' is a 6-bit constant (valid for a shift insn). */
791 #define EXTRA_CONSTRAINT(OP, C) \
792 ((C) == 'Q' ? normal_memory_operand (OP, VOIDmode) \
793 : (C) == 'R' ? current_file_function_operand (OP, Pmode) \
794 : (C) == 'S' ? (GET_CODE (OP) == CONST_INT \
795 && (unsigned HOST_WIDE_INT) INTVAL (OP) < 64) \
798 /* Given an rtx X being reloaded into a reg required to be
799 in class CLASS, return the class of reg to actually use.
800 In general this is just CLASS; but on some machines
801 in some cases it is preferable to use a more restrictive class.
803 On the Alpha, all constants except zero go into a floating-point
804 register via memory. */
806 #define PREFERRED_RELOAD_CLASS(X, CLASS) \
807 (CONSTANT_P (X) && (X) != const0_rtx && (X) != CONST0_RTX (GET_MODE (X)) \
808 ? ((CLASS) == FLOAT_REGS || (CLASS) == NO_REGS ? NO_REGS : GENERAL_REGS)\
811 /* Loading and storing HImode or QImode values to and from memory
812 usually requires a scratch register. The exceptions are loading
813 QImode and HImode from an aligned address to a general register
814 unless byte instructions are permitted.
815 We also cannot load an unaligned address or a paradoxical SUBREG into an
818 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS,MODE,IN) \
819 (((GET_CODE (IN) == MEM \
820 || (GET_CODE (IN) == REG && REGNO (IN) >= FIRST_PSEUDO_REGISTER) \
821 || (GET_CODE (IN) == SUBREG \
822 && (GET_CODE (SUBREG_REG (IN)) == MEM \
823 || (GET_CODE (SUBREG_REG (IN)) == REG \
824 && REGNO (SUBREG_REG (IN)) >= FIRST_PSEUDO_REGISTER)))) \
825 && (((CLASS) == FLOAT_REGS \
826 && ((MODE) == SImode || (MODE) == HImode || (MODE) == QImode)) \
827 || (((MODE) == QImode || (MODE) == HImode) \
828 && ! TARGET_BWX && ! aligned_memory_operand (IN, MODE)))) \
830 : ((CLASS) == FLOAT_REGS && GET_CODE (IN) == MEM \
831 && GET_CODE (XEXP (IN, 0)) == AND) ? GENERAL_REGS \
832 : ((CLASS) == FLOAT_REGS && GET_CODE (IN) == SUBREG \
833 && (GET_MODE_SIZE (GET_MODE (IN)) \
834 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (IN))))) ? GENERAL_REGS \
837 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS,MODE,OUT) \
838 (((GET_CODE (OUT) == MEM \
839 || (GET_CODE (OUT) == REG && REGNO (OUT) >= FIRST_PSEUDO_REGISTER) \
840 || (GET_CODE (OUT) == SUBREG \
841 && (GET_CODE (SUBREG_REG (OUT)) == MEM \
842 || (GET_CODE (SUBREG_REG (OUT)) == REG \
843 && REGNO (SUBREG_REG (OUT)) >= FIRST_PSEUDO_REGISTER)))) \
844 && ((((MODE) == HImode || (MODE) == QImode) \
845 && (! TARGET_BWX || (CLASS) == FLOAT_REGS)) \
846 || ((MODE) == SImode && (CLASS) == FLOAT_REGS))) \
848 : ((CLASS) == FLOAT_REGS && GET_CODE (OUT) == MEM \
849 && GET_CODE (XEXP (OUT, 0)) == AND) ? GENERAL_REGS \
850 : ((CLASS) == FLOAT_REGS && GET_CODE (OUT) == SUBREG \
851 && (GET_MODE_SIZE (GET_MODE (OUT)) \
852 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (OUT))))) ? GENERAL_REGS \
855 /* If we are copying between general and FP registers, we need a memory
856 location unless the FIX extension is available. */
858 #define SECONDARY_MEMORY_NEEDED(CLASS1,CLASS2,MODE) \
859 (! TARGET_FIX && (CLASS1) != (CLASS2))
861 /* Specify the mode to be used for memory when a secondary memory
862 location is needed. If MODE is floating-point, use it. Otherwise,
863 widen to a word like the default. This is needed because we always
864 store integers in FP registers in quadword format. This whole
865 area is very tricky! */
866 #define SECONDARY_MEMORY_NEEDED_MODE(MODE) \
867 (GET_MODE_CLASS (MODE) == MODE_FLOAT ? (MODE) \
868 : GET_MODE_SIZE (MODE) >= 4 ? (MODE) \
869 : mode_for_size (BITS_PER_WORD, GET_MODE_CLASS (MODE), 0))
871 /* Return the maximum number of consecutive registers
872 needed to represent mode MODE in a register of class CLASS. */
874 #define CLASS_MAX_NREGS(CLASS, MODE) \
875 ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
877 /* If defined, gives a class of registers that cannot be used as the
878 operand of a SUBREG that changes the size of the object. */
880 #define CLASS_CANNOT_CHANGE_SIZE FLOAT_REGS
882 /* Define the cost of moving between registers of various classes. Moving
883 between FLOAT_REGS and anything else except float regs is expensive.
884 In fact, we make it quite expensive because we really don't want to
885 do these moves unless it is clearly worth it. Optimizations may
886 reduce the impact of not being able to allocate a pseudo to a
889 #define REGISTER_MOVE_COST(CLASS1, CLASS2) \
890 (((CLASS1) == FLOAT_REGS) == ((CLASS2) == FLOAT_REGS) \
892 : TARGET_FIX ? 3 : 4+2*alpha_memory_latency)
894 /* A C expressions returning the cost of moving data of MODE from a register to
897 On the Alpha, bump this up a bit. */
899 extern int alpha_memory_latency;
900 #define MEMORY_MOVE_COST(MODE,CLASS,IN) (2*alpha_memory_latency)
902 /* Provide the cost of a branch. Exact meaning under development. */
903 #define BRANCH_COST 5
905 /* Adjust the cost of dependencies. */
907 #define ADJUST_COST(INSN,LINK,DEP,COST) \
908 (COST) = alpha_adjust_cost (INSN, LINK, DEP, COST)
910 /* Stack layout; function entry, exit and calling. */
912 /* Define this if pushing a word on the stack
913 makes the stack pointer a smaller address. */
914 #define STACK_GROWS_DOWNWARD
916 /* Define this if the nominal address of the stack frame
917 is at the high-address end of the local variables;
918 that is, each additional local variable allocated
919 goes at a more negative offset in the frame. */
920 /* #define FRAME_GROWS_DOWNWARD */
922 /* Offset within stack frame to start allocating local variables at.
923 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
924 first local allocated. Otherwise, it is the offset to the BEGINNING
925 of the first local allocated. */
927 #define STARTING_FRAME_OFFSET 0
929 /* If we generate an insn to push BYTES bytes,
930 this says how many the stack pointer really advances by.
931 On Alpha, don't define this because there are no push insns. */
932 /* #define PUSH_ROUNDING(BYTES) */
934 /* Define this to be nonzero if stack checking is built into the ABI. */
935 #define STACK_CHECK_BUILTIN 1
937 /* Define this if the maximum size of all the outgoing args is to be
938 accumulated and pushed during the prologue. The amount can be
939 found in the variable current_function_outgoing_args_size. */
940 #define ACCUMULATE_OUTGOING_ARGS
942 /* Offset of first parameter from the argument pointer register value. */
944 #define FIRST_PARM_OFFSET(FNDECL) 0
946 /* Definitions for register eliminations.
948 We have two registers that can be eliminated on the Alpha. First, the
949 frame pointer register can often be eliminated in favor of the stack
950 pointer register. Secondly, the argument pointer register can always be
951 eliminated; it is replaced with either the stack or frame pointer. */
953 /* This is an array of structures. Each structure initializes one pair
954 of eliminable registers. The "from" register number is given first,
955 followed by "to". Eliminations of the same "from" register are listed
956 in order of preference. */
958 #define ELIMINABLE_REGS \
959 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
960 { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \
961 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
962 { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}}
964 /* Given FROM and TO register numbers, say whether this elimination is allowed.
965 Frame pointer elimination is automatically handled.
967 All eliminations are valid since the cases where FP can't be
968 eliminated are already handled. */
970 #define CAN_ELIMINATE(FROM, TO) 1
972 /* Round up to a multiple of 16 bytes. */
973 #define ALPHA_ROUND(X) (((X) + 15) & ~ 15)
975 /* Define the offset between two registers, one to be eliminated, and the other
976 its replacement, at the start of a routine. */
977 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
978 { if ((FROM) == FRAME_POINTER_REGNUM) \
979 (OFFSET) = (ALPHA_ROUND (current_function_outgoing_args_size) \
980 + alpha_sa_size ()); \
981 else if ((FROM) == ARG_POINTER_REGNUM) \
982 (OFFSET) = (ALPHA_ROUND (current_function_outgoing_args_size) \
984 + (ALPHA_ROUND (get_frame_size () \
985 + current_function_pretend_args_size) \
986 - current_function_pretend_args_size)); \
989 /* Define this if stack space is still allocated for a parameter passed
991 /* #define REG_PARM_STACK_SPACE */
993 /* Value is the number of bytes of arguments automatically
994 popped when returning from a subroutine call.
995 FUNDECL is the declaration node of the function (as a tree),
996 FUNTYPE is the data type of the function (as a tree),
997 or for a library call it is an identifier node for the subroutine name.
998 SIZE is the number of bytes of arguments passed on the stack. */
1000 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0
1002 /* Define how to find the value returned by a function.
1003 VALTYPE is the data type of the value (as a tree).
1004 If the precise function being called is known, FUNC is its FUNCTION_DECL;
1005 otherwise, FUNC is 0.
1007 On Alpha the value is found in $0 for integer functions and
1008 $f0 for floating-point functions. */
1010 #define FUNCTION_VALUE(VALTYPE, FUNC) \
1011 gen_rtx_REG (((INTEGRAL_TYPE_P (VALTYPE) \
1012 && TYPE_PRECISION (VALTYPE) < BITS_PER_WORD) \
1013 || POINTER_TYPE_P (VALTYPE)) \
1014 ? word_mode : TYPE_MODE (VALTYPE), \
1016 && (TREE_CODE (VALTYPE) == REAL_TYPE \
1017 || TREE_CODE (VALTYPE) == COMPLEX_TYPE)) \
1020 /* Define how to find the value returned by a library function
1021 assuming the value has mode MODE. */
1023 #define LIBCALL_VALUE(MODE) \
1024 gen_rtx_REG (MODE, \
1026 && (GET_MODE_CLASS (MODE) == MODE_FLOAT \
1027 || GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT) \
1030 /* The definition of this macro implies that there are cases where
1031 a scalar value cannot be returned in registers.
1033 For the Alpha, any structure or union type is returned in memory, as
1034 are integers whose size is larger than 64 bits. */
1036 #define RETURN_IN_MEMORY(TYPE) \
1037 (TYPE_MODE (TYPE) == BLKmode \
1038 || (TREE_CODE (TYPE) == INTEGER_TYPE && TYPE_PRECISION (TYPE) > 64))
1040 /* 1 if N is a possible register number for a function value
1041 as seen by the caller. */
1043 #define FUNCTION_VALUE_REGNO_P(N) \
1044 ((N) == 0 || (N) == 1 || (N) == 32 || (N) == 33)
1046 /* 1 if N is a possible register number for function argument passing.
1047 On Alpha, these are $16-$21 and $f16-$f21. */
1049 #define FUNCTION_ARG_REGNO_P(N) \
1050 (((N) >= 16 && (N) <= 21) || ((N) >= 16 + 32 && (N) <= 21 + 32))
1052 /* Define a data type for recording info about an argument list
1053 during the scan of that argument list. This data type should
1054 hold all necessary information about the function itself
1055 and about the args processed so far, enough to enable macros
1056 such as FUNCTION_ARG to determine where the next arg should go.
1058 On Alpha, this is a single integer, which is a number of words
1059 of arguments scanned so far.
1060 Thus 6 or more means all following args should go on the stack. */
1062 #define CUMULATIVE_ARGS int
1064 /* Initialize a variable CUM of type CUMULATIVE_ARGS
1065 for a call to a function whose data type is FNTYPE.
1066 For a library call, FNTYPE is 0. */
1068 #define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME,INDIRECT) (CUM) = 0
1070 /* Define intermediate macro to compute the size (in registers) of an argument
1073 #define ALPHA_ARG_SIZE(MODE, TYPE, NAMED) \
1074 ((MODE) != BLKmode \
1075 ? (GET_MODE_SIZE (MODE) + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD \
1076 : (int_size_in_bytes (TYPE) + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
1078 /* Update the data in CUM to advance over an argument
1079 of mode MODE and data type TYPE.
1080 (TYPE is null for libcalls where that information may not be available.) */
1082 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
1083 if (MUST_PASS_IN_STACK (MODE, TYPE)) \
1086 (CUM) += ALPHA_ARG_SIZE (MODE, TYPE, NAMED)
1088 /* Determine where to put an argument to a function.
1089 Value is zero to push the argument on the stack,
1090 or a hard register in which to store the argument.
1092 MODE is the argument's machine mode.
1093 TYPE is the data type of the argument (as a tree).
1094 This is null for libcalls where that information may
1096 CUM is a variable of type CUMULATIVE_ARGS which gives info about
1097 the preceding args and about the function being called.
1098 NAMED is nonzero if this argument is a named parameter
1099 (otherwise it is an extra parameter matching an ellipsis).
1101 On Alpha the first 6 words of args are normally in registers
1102 and the rest are pushed. */
1104 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
1105 ((CUM) < 6 && ! MUST_PASS_IN_STACK (MODE, TYPE) \
1106 ? gen_rtx_REG ((MODE), \
1109 && (GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT \
1110 || GET_MODE_CLASS (MODE) == MODE_FLOAT)) \
1114 /* Specify the padding direction of arguments.
1116 On the Alpha, we must pad upwards in order to be able to pass args in
1119 #define FUNCTION_ARG_PADDING(MODE, TYPE) upward
1121 /* For an arg passed partly in registers and partly in memory,
1122 this is the number of registers used.
1123 For args passed entirely in registers or entirely in memory, zero. */
1125 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
1126 ((CUM) < 6 && 6 < (CUM) + ALPHA_ARG_SIZE (MODE, TYPE, NAMED) \
1129 /* Perform any needed actions needed for a function that is receiving a
1130 variable number of arguments.
1134 MODE and TYPE are the mode and type of the current parameter.
1136 PRETEND_SIZE is a variable that should be set to the amount of stack
1137 that must be pushed by the prolog to pretend that our caller pushed
1140 Normally, this macro will push all remaining incoming registers on the
1141 stack and set PRETEND_SIZE to the length of the registers pushed.
1143 On the Alpha, we allocate space for all 12 arg registers, but only
1144 push those that are remaining.
1146 However, if NO registers need to be saved, don't allocate any space.
1147 This is not only because we won't need the space, but because AP includes
1148 the current_pretend_args_size and we don't want to mess up any
1149 ap-relative addresses already made.
1151 If we are not to use the floating-point registers, save the integer
1152 registers where we would put the floating-point registers. This is
1153 not the most efficient way to implement varargs with just one register
1154 class, but it isn't worth doing anything more efficient in this rare
1158 #define SETUP_INCOMING_VARARGS(CUM,MODE,TYPE,PRETEND_SIZE,NO_RTL) \
1163 rtx tmp; int set = get_varargs_alias_set (); \
1164 tmp = gen_rtx_MEM (BLKmode, \
1165 plus_constant (virtual_incoming_args_rtx, \
1166 ((CUM) + 6)* UNITS_PER_WORD)); \
1167 MEM_ALIAS_SET (tmp) = set; \
1168 move_block_from_reg \
1170 6 - (CUM), (6 - (CUM)) * UNITS_PER_WORD); \
1172 tmp = gen_rtx_MEM (BLKmode, \
1173 plus_constant (virtual_incoming_args_rtx, \
1174 (CUM) * UNITS_PER_WORD)); \
1175 MEM_ALIAS_SET (tmp) = set; \
1176 move_block_from_reg \
1177 (16 + (TARGET_FPREGS ? 32 : 0) + CUM, tmp, \
1178 6 - (CUM), (6 - (CUM)) * UNITS_PER_WORD); \
1180 PRETEND_SIZE = 12 * UNITS_PER_WORD; \
1184 /* Try to output insns to set TARGET equal to the constant C if it can be
1185 done in less than N insns. Do all computations in MODE. Returns the place
1186 where the output has been placed if it can be done and the insns have been
1187 emitted. If it would take more than N insns, zero is returned and no
1188 insns and emitted. */
1190 /* Define the information needed to generate branch and scc insns. This is
1191 stored from the compare operation. Note that we can't use "rtx" here
1192 since it hasn't been defined! */
1194 struct alpha_compare
1196 struct rtx_def *op0, *op1;
1200 extern struct alpha_compare alpha_compare;
1202 /* Machine specific function data. */
1204 struct machine_function
1206 /* An offset to apply to the stack pointer when unwinding from EH. */
1207 struct rtx_def *eh_epilogue_sp_ofs;
1209 /* If non-null, this rtx holds the return address for the function. */
1210 struct rtx_def *ra_rtx;
1213 /* Make (or fake) .linkage entry for function call.
1214 IS_LOCAL is 0 if name is used in call, 1 if name is used in definition. */
1216 /* This macro defines the start of an assembly comment. */
1218 #define ASM_COMMENT_START " #"
1220 /* This macro produces the initial definition of a function. */
1222 #define ASM_DECLARE_FUNCTION_NAME(FILE,NAME,DECL) \
1223 alpha_start_function(FILE,NAME,DECL);
1225 /* This macro closes up a function definition for the assembler. */
1227 #define ASM_DECLARE_FUNCTION_SIZE(FILE,NAME,DECL) \
1228 alpha_end_function(FILE,NAME,DECL)
1230 /* This macro notes the end of the prologue. */
1232 #define FUNCTION_END_PROLOGUE(FILE) output_end_prologue (FILE)
1234 /* Output any profiling code before the prologue. */
1236 #define PROFILE_BEFORE_PROLOGUE 1
1238 /* Output assembler code to FILE to increment profiler label # LABELNO
1239 for profiling a function entry. Under OSF/1, profiling is enabled
1240 by simply passing -pg to the assembler and linker. */
1242 #define FUNCTION_PROFILER(FILE, LABELNO)
1244 /* Output assembler code to FILE to initialize this source file's
1245 basic block profiling info, if that has not already been done.
1246 This assumes that __bb_init_func doesn't garble a1-a5. */
1248 #define FUNCTION_BLOCK_PROFILER(FILE, LABELNO) \
1250 ASM_OUTPUT_REG_PUSH (FILE, 16); \
1251 fputs ("\tlda $16,$PBX32\n", (FILE)); \
1252 fputs ("\tldq $26,0($16)\n", (FILE)); \
1253 fputs ("\tbne $26,1f\n", (FILE)); \
1254 fputs ("\tlda $27,__bb_init_func\n", (FILE)); \
1255 fputs ("\tjsr $26,($27),__bb_init_func\n", (FILE)); \
1256 fputs ("\tldgp $29,0($26)\n", (FILE)); \
1257 fputs ("1:\n", (FILE)); \
1258 ASM_OUTPUT_REG_POP (FILE, 16); \
1261 /* Output assembler code to FILE to increment the entry-count for
1262 the BLOCKNO'th basic block in this source file. */
1264 #define BLOCK_PROFILER(FILE, BLOCKNO) \
1266 int blockn = (BLOCKNO); \
1267 fputs ("\tsubq $30,16,$30\n", (FILE)); \
1268 fputs ("\tstq $26,0($30)\n", (FILE)); \
1269 fputs ("\tstq $27,8($30)\n", (FILE)); \
1270 fputs ("\tlda $26,$PBX34\n", (FILE)); \
1271 fprintf ((FILE), "\tldq $27,%d($26)\n", 8*blockn); \
1272 fputs ("\taddq $27,1,$27\n", (FILE)); \
1273 fprintf ((FILE), "\tstq $27,%d($26)\n", 8*blockn); \
1274 fputs ("\tldq $26,0($30)\n", (FILE)); \
1275 fputs ("\tldq $27,8($30)\n", (FILE)); \
1276 fputs ("\taddq $30,16,$30\n", (FILE)); \
1280 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
1281 the stack pointer does not matter. The value is tested only in
1282 functions that have frame pointers.
1283 No definition is equivalent to always zero. */
1285 #define EXIT_IGNORE_STACK 1
1287 /* Output assembler code for a block containing the constant parts
1288 of a trampoline, leaving space for the variable parts.
1290 The trampoline should set the static chain pointer to value placed
1291 into the trampoline and should branch to the specified routine.
1292 Note that $27 has been set to the address of the trampoline, so we can
1293 use it for addressability of the two data items. Trampolines are always
1294 aligned to FUNCTION_BOUNDARY, which is 64 bits. */
1296 #define TRAMPOLINE_TEMPLATE(FILE) \
1298 fprintf (FILE, "\tldq $1,24($27)\n"); \
1299 fprintf (FILE, "\tldq $27,16($27)\n"); \
1300 fprintf (FILE, "\tjmp $31,($27),0\n"); \
1301 fprintf (FILE, "\tnop\n"); \
1302 fprintf (FILE, "\t.quad 0,0\n"); \
1305 /* Section in which to place the trampoline. On Alpha, instructions
1306 may only be placed in a text segment. */
1308 #define TRAMPOLINE_SECTION text_section
1310 /* Length in units of the trampoline for entering a nested function. */
1312 #define TRAMPOLINE_SIZE 32
1314 /* Emit RTL insns to initialize the variable parts of a trampoline.
1315 FNADDR is an RTX for the address of the function's pure code.
1316 CXT is an RTX for the static chain value for the function. */
1318 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
1319 alpha_initialize_trampoline (TRAMP, FNADDR, CXT, 16, 24, 8)
1321 /* A C expression whose value is RTL representing the value of the return
1322 address for the frame COUNT steps up from the current frame.
1323 FRAMEADDR is the frame pointer of the COUNT frame, or the frame pointer of
1324 the COUNT-1 frame if RETURN_ADDR_IN_PREVIOUS_FRAME is defined. */
1326 #define RETURN_ADDR_RTX alpha_return_addr
1328 /* Before the prologue, RA lives in $26. */
1329 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, 26)
1331 /* Addressing modes, and classification of registers for them. */
1333 /* #define HAVE_POST_INCREMENT 0 */
1334 /* #define HAVE_POST_DECREMENT 0 */
1336 /* #define HAVE_PRE_DECREMENT 0 */
1337 /* #define HAVE_PRE_INCREMENT 0 */
1339 /* Macros to check register numbers against specific register classes. */
1341 /* These assume that REGNO is a hard or pseudo reg number.
1342 They give nonzero only if REGNO is a hard reg of the suitable class
1343 or a pseudo reg currently allocated to a suitable hard reg.
1344 Since they use reg_renumber, they are safe only once reg_renumber
1345 has been allocated, which happens in local-alloc.c. */
1347 #define REGNO_OK_FOR_INDEX_P(REGNO) 0
1348 #define REGNO_OK_FOR_BASE_P(REGNO) \
1349 ((REGNO) < 32 || (unsigned) reg_renumber[REGNO] < 32 \
1350 || (REGNO) == 63 || reg_renumber[REGNO] == 63)
1352 /* Maximum number of registers that can appear in a valid memory address. */
1353 #define MAX_REGS_PER_ADDRESS 1
1355 /* Recognize any constant value that is a valid address. For the Alpha,
1356 there are only constants none since we want to use LDA to load any
1357 symbolic addresses into registers. */
1359 #define CONSTANT_ADDRESS_P(X) \
1360 (GET_CODE (X) == CONST_INT \
1361 && (unsigned HOST_WIDE_INT) (INTVAL (X) + 0x8000) < 0x10000)
1363 /* Include all constant integers and constant doubles, but not
1364 floating-point, except for floating-point zero. */
1366 #define LEGITIMATE_CONSTANT_P(X) \
1367 (GET_MODE_CLASS (GET_MODE (X)) != MODE_FLOAT \
1368 || (X) == CONST0_RTX (GET_MODE (X)))
1370 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
1371 and check its validity for a certain class.
1372 We have two alternate definitions for each of them.
1373 The usual definition accepts all pseudo regs; the other rejects
1374 them unless they have been allocated suitable hard regs.
1375 The symbol REG_OK_STRICT causes the latter definition to be used.
1377 Most source files want to accept pseudo regs in the hope that
1378 they will get allocated to the class that the insn wants them to be in.
1379 Source files for reload pass need to be strict.
1380 After reload, it makes no difference, since pseudo regs have
1381 been eliminated by then. */
1383 #ifndef REG_OK_STRICT
1385 /* Nonzero if X is a hard reg that can be used as an index
1386 or if it is a pseudo reg. */
1387 #define REG_OK_FOR_INDEX_P(X) 0
1389 /* Nonzero if X is a hard reg that can be used as a base reg
1390 or if it is a pseudo reg. */
1391 #define REG_OK_FOR_BASE_P(X) \
1392 (REGNO (X) < 32 || REGNO (X) == 63 || REGNO (X) >= FIRST_PSEUDO_REGISTER)
1394 /* ??? Nonzero if X is the frame pointer, or some virtual register
1395 that may eliminate to the frame pointer. These will be allowed to
1396 have offsets greater than 32K. This is done because register
1397 elimination offsets will change the hi/lo split, and if we split
1398 before reload, we will require additional instructions. */
1399 #define REG_OK_FP_BASE_P(X) \
1400 (REGNO (X) == 31 || REGNO (X) == 63 \
1401 || (REGNO (X) >= FIRST_PSEUDO_REGISTER \
1402 && REGNO (X) < LAST_VIRTUAL_REGISTER))
1406 /* Nonzero if X is a hard reg that can be used as an index. */
1407 #define REG_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X))
1409 /* Nonzero if X is a hard reg that can be used as a base reg. */
1410 #define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X))
1412 #define REG_OK_FP_BASE_P(X) 0
1416 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
1417 that is a valid memory address for an instruction.
1418 The MODE argument is the machine mode for the MEM expression
1419 that wants to use this address.
1421 For Alpha, we have either a constant address or the sum of a register
1422 and a constant address, or just a register. For DImode, any of those
1423 forms can be surrounded with an AND that clear the low-order three bits;
1424 this is an "unaligned" access.
1426 First define the basic valid address. */
1428 #define GO_IF_LEGITIMATE_SIMPLE_ADDRESS(MODE, X, ADDR) \
1431 if (GET_CODE (tmp) == SUBREG \
1432 && (GET_MODE_SIZE (GET_MODE (tmp)) \
1433 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (tmp))))) \
1434 tmp = SUBREG_REG (tmp); \
1435 if (REG_P (tmp) && REG_OK_FOR_BASE_P (tmp)) \
1437 if (CONSTANT_ADDRESS_P (X)) \
1439 if (GET_CODE (X) == PLUS) \
1441 tmp = XEXP (X, 0); \
1442 if (GET_CODE (tmp) == SUBREG \
1443 && (GET_MODE_SIZE (GET_MODE (tmp)) \
1444 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (tmp))))) \
1445 tmp = SUBREG_REG (tmp); \
1448 if (REG_OK_FP_BASE_P (tmp) \
1449 && GET_CODE (XEXP (X, 1)) == CONST_INT) \
1451 if (REG_OK_FOR_BASE_P (tmp) \
1452 && CONSTANT_ADDRESS_P (XEXP (X, 1))) \
1455 else if (GET_CODE (tmp) == ADDRESSOF \
1456 && CONSTANT_ADDRESS_P (XEXP (X, 1))) \
1461 /* Now accept the simple address, or, for DImode only, an AND of a simple
1462 address that turns off the low three bits. */
1464 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
1465 { GO_IF_LEGITIMATE_SIMPLE_ADDRESS (MODE, X, ADDR); \
1466 if ((MODE) == DImode \
1467 && GET_CODE (X) == AND \
1468 && GET_CODE (XEXP (X, 1)) == CONST_INT \
1469 && INTVAL (XEXP (X, 1)) == -8) \
1470 GO_IF_LEGITIMATE_SIMPLE_ADDRESS (MODE, XEXP (X, 0), ADDR); \
1473 /* Try machine-dependent ways of modifying an illegitimate address
1474 to be legitimate. If we find one, return the new, valid address.
1475 This macro is used in only one place: `memory_address' in explow.c.
1477 OLDX is the address as it was before break_out_memory_refs was called.
1478 In some cases it is useful to look at this to decide what needs to be done.
1480 MODE and WIN are passed so that this macro can use
1481 GO_IF_LEGITIMATE_ADDRESS.
1483 It is always safe for this macro to do nothing. It exists to recognize
1484 opportunities to optimize the output.
1486 For the Alpha, there are three cases we handle:
1488 (1) If the address is (plus reg const_int) and the CONST_INT is not a
1489 valid offset, compute the high part of the constant and add it to the
1490 register. Then our address is (plus temp low-part-const).
1491 (2) If the address is (const (plus FOO const_int)), find the low-order
1492 part of the CONST_INT. Then load FOO plus any high-order part of the
1493 CONST_INT into a register. Our address is (plus reg low-part-const).
1494 This is done to reduce the number of GOT entries.
1495 (3) If we have a (plus reg const), emit the load as in (2), then add
1496 the two registers, and finally generate (plus reg low-part-const) as
1499 #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \
1500 { if (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 0)) == REG \
1501 && GET_CODE (XEXP (X, 1)) == CONST_INT \
1502 && ! CONSTANT_ADDRESS_P (XEXP (X, 1))) \
1504 HOST_WIDE_INT val = INTVAL (XEXP (X, 1)); \
1505 HOST_WIDE_INT lowpart = (val & 0xffff) - 2 * (val & 0x8000); \
1506 HOST_WIDE_INT highpart = val - lowpart; \
1507 rtx high = GEN_INT (highpart); \
1508 rtx temp = expand_binop (Pmode, add_optab, XEXP (x, 0), \
1509 high, NULL_RTX, 1, OPTAB_LIB_WIDEN); \
1511 (X) = plus_constant (temp, lowpart); \
1514 else if (GET_CODE (X) == CONST \
1515 && GET_CODE (XEXP (X, 0)) == PLUS \
1516 && GET_CODE (XEXP (XEXP (X, 0), 1)) == CONST_INT) \
1518 HOST_WIDE_INT val = INTVAL (XEXP (XEXP (X, 0), 1)); \
1519 HOST_WIDE_INT lowpart = (val & 0xffff) - 2 * (val & 0x8000); \
1520 HOST_WIDE_INT highpart = val - lowpart; \
1521 rtx high = XEXP (XEXP (X, 0), 0); \
1524 high = plus_constant (high, highpart); \
1526 (X) = plus_constant (force_reg (Pmode, high), lowpart); \
1529 else if (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 0)) == REG \
1530 && GET_CODE (XEXP (X, 1)) == CONST \
1531 && GET_CODE (XEXP (XEXP (X, 1), 0)) == PLUS \
1532 && GET_CODE (XEXP (XEXP (XEXP (X, 1), 0), 1)) == CONST_INT) \
1534 HOST_WIDE_INT val = INTVAL (XEXP (XEXP (XEXP (X, 1), 0), 1)); \
1535 HOST_WIDE_INT lowpart = (val & 0xffff) - 2 * (val & 0x8000); \
1536 HOST_WIDE_INT highpart = val - lowpart; \
1537 rtx high = XEXP (XEXP (XEXP (X, 1), 0), 0); \
1540 high = plus_constant (high, highpart); \
1542 high = expand_binop (Pmode, add_optab, XEXP (X, 0), \
1543 force_reg (Pmode, high), \
1544 high, 1, OPTAB_LIB_WIDEN); \
1545 (X) = plus_constant (high, lowpart); \
1550 /* Try a machine-dependent way of reloading an illegitimate address
1551 operand. If we find one, push the reload and jump to WIN. This
1552 macro is used in only one place: `find_reloads_address' in reload.c.
1554 For the Alpha, we wish to handle large displacements off a base
1555 register by splitting the addend across an ldah and the mem insn.
1556 This cuts number of extra insns needed from 3 to 1. */
1558 #define LEGITIMIZE_RELOAD_ADDRESS(X,MODE,OPNUM,TYPE,IND_LEVELS,WIN) \
1560 /* We must recognize output that we have already generated ourselves. */ \
1561 if (GET_CODE (X) == PLUS \
1562 && GET_CODE (XEXP (X, 0)) == PLUS \
1563 && GET_CODE (XEXP (XEXP (X, 0), 0)) == REG \
1564 && GET_CODE (XEXP (XEXP (X, 0), 1)) == CONST_INT \
1565 && GET_CODE (XEXP (X, 1)) == CONST_INT) \
1567 push_reload (XEXP (X, 0), NULL_RTX, &XEXP (X, 0), NULL_PTR, \
1568 BASE_REG_CLASS, GET_MODE (X), VOIDmode, 0, 0, \
1572 if (GET_CODE (X) == PLUS \
1573 && GET_CODE (XEXP (X, 0)) == REG \
1574 && REGNO (XEXP (X, 0)) < FIRST_PSEUDO_REGISTER \
1575 && REG_MODE_OK_FOR_BASE_P (XEXP (X, 0), MODE) \
1576 && GET_CODE (XEXP (X, 1)) == CONST_INT) \
1578 HOST_WIDE_INT val = INTVAL (XEXP (X, 1)); \
1579 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000; \
1580 HOST_WIDE_INT high \
1581 = (((val - low) & 0xffffffff) ^ 0x80000000) - 0x80000000; \
1583 /* Check for 32-bit overflow. */ \
1584 if (high + low != val) \
1587 /* Reload the high part into a base reg; leave the low part \
1588 in the mem directly. */ \
1590 X = gen_rtx_PLUS (GET_MODE (X), \
1591 gen_rtx_PLUS (GET_MODE (X), XEXP (X, 0), \
1595 push_reload (XEXP (X, 0), NULL_RTX, &XEXP (X, 0), NULL_PTR, \
1596 BASE_REG_CLASS, GET_MODE (X), VOIDmode, 0, 0, \
1602 /* Go to LABEL if ADDR (a legitimate address expression)
1603 has an effect that depends on the machine mode it is used for.
1604 On the Alpha this is true only for the unaligned modes. We can
1605 simplify this test since we know that the address must be valid. */
1607 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) \
1608 { if (GET_CODE (ADDR) == AND) goto LABEL; }
1610 /* Compute the cost of an address. For the Alpha, all valid addresses are
1613 #define ADDRESS_COST(X) 0
1615 /* Machine-dependent reorg pass. */
1616 #define MACHINE_DEPENDENT_REORG(X) alpha_reorg(X)
1618 /* Specify the machine mode that this machine uses
1619 for the index in the tablejump instruction. */
1620 #define CASE_VECTOR_MODE SImode
1622 /* Define as C expression which evaluates to nonzero if the tablejump
1623 instruction expects the table to contain offsets from the address of the
1626 Do not define this if the table should contain absolute addresses.
1627 On the Alpha, the table is really GP-relative, not relative to the PC
1628 of the table, but we pretend that it is PC-relative; this should be OK,
1629 but we should try to find some better way sometime. */
1630 #define CASE_VECTOR_PC_RELATIVE 1
1632 /* Specify the tree operation to be used to convert reals to integers. */
1633 #define IMPLICIT_FIX_EXPR FIX_ROUND_EXPR
1635 /* This is the kind of divide that is easiest to do in the general case. */
1636 #define EASY_DIV_EXPR TRUNC_DIV_EXPR
1638 /* Define this as 1 if `char' should by default be signed; else as 0. */
1639 #define DEFAULT_SIGNED_CHAR 1
1641 /* This flag, if defined, says the same insns that convert to a signed fixnum
1642 also convert validly to an unsigned one.
1644 We actually lie a bit here as overflow conditions are different. But
1645 they aren't being checked anyway. */
1647 #define FIXUNS_TRUNC_LIKE_FIX_TRUNC
1649 /* Max number of bytes we can move to or from memory
1650 in one reasonably fast instruction. */
1654 /* If a memory-to-memory move would take MOVE_RATIO or more simple
1655 move-instruction pairs, we will do a movstr or libcall instead.
1657 Without byte/word accesses, we want no more than four instructions;
1658 with, several single byte accesses are better. */
1660 #define MOVE_RATIO (TARGET_BWX ? 7 : 2)
1662 /* Largest number of bytes of an object that can be placed in a register.
1663 On the Alpha we have plenty of registers, so use TImode. */
1664 #define MAX_FIXED_MODE_SIZE GET_MODE_BITSIZE (TImode)
1666 /* Nonzero if access to memory by bytes is no faster than for words.
1667 Also non-zero if doing byte operations (specifically shifts) in registers
1670 On the Alpha, we want to not use the byte operation and instead use
1671 masking operations to access fields; these will save instructions. */
1673 #define SLOW_BYTE_ACCESS 1
1675 /* Define if operations between registers always perform the operation
1676 on the full register even if a narrower mode is specified. */
1677 #define WORD_REGISTER_OPERATIONS
1679 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
1680 will either zero-extend or sign-extend. The value of this macro should
1681 be the code that says which one of the two operations is implicitly
1682 done, NIL if none. */
1683 #define LOAD_EXTEND_OP(MODE) ((MODE) == SImode ? SIGN_EXTEND : ZERO_EXTEND)
1685 /* Define if loading short immediate values into registers sign extends. */
1686 #define SHORT_IMMEDIATES_SIGN_EXTEND
1688 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
1689 is done just by pretending it is already truncated. */
1690 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
1692 /* We assume that the store-condition-codes instructions store 0 for false
1693 and some other value for true. This is the value stored for true. */
1695 #define STORE_FLAG_VALUE 1
1697 /* Define the value returned by a floating-point comparison instruction. */
1699 #define FLOAT_STORE_FLAG_VALUE (TARGET_FLOAT_VAX ? 0.5 : 2.0)
1701 /* Canonicalize a comparison from one we don't have to one we do have. */
1703 #define CANONICALIZE_COMPARISON(CODE,OP0,OP1) \
1705 if (((CODE) == GE || (CODE) == GT || (CODE) == GEU || (CODE) == GTU) \
1706 && (GET_CODE (OP1) == REG || (OP1) == const0_rtx)) \
1711 (CODE) = swap_condition (CODE); \
1713 if (((CODE) == LT || (CODE) == LTU) \
1714 && GET_CODE (OP1) == CONST_INT && INTVAL (OP1) == 256) \
1716 (CODE) = (CODE) == LT ? LE : LEU; \
1717 (OP1) = GEN_INT (255); \
1721 /* Specify the machine mode that pointers have.
1722 After generation of rtl, the compiler makes no further distinction
1723 between pointers and any other objects of this machine mode. */
1724 #define Pmode DImode
1726 /* Mode of a function address in a call instruction (for indexing purposes). */
1728 #define FUNCTION_MODE Pmode
1730 /* Define this if addresses of constant functions
1731 shouldn't be put through pseudo regs where they can be cse'd.
1732 Desirable on machines where ordinary constants are expensive
1733 but a CALL with constant address is cheap.
1735 We define this on the Alpha so that gen_call and gen_call_value
1736 get to see the SYMBOL_REF (for the hint field of the jsr). It will
1737 then copy it into a register, thus actually letting the address be
1740 #define NO_FUNCTION_CSE
1742 /* Define this to be nonzero if shift instructions ignore all but the low-order
1744 #define SHIFT_COUNT_TRUNCATED 1
1746 /* The EV4 is dual issue; EV5/EV6 are quad issue. */
1747 #define ISSUE_RATE (alpha_cpu == PROCESSOR_EV4 ? 2 : 4)
1749 /* Describe the fact that MULTI instructions are multiple instructions
1750 and so to assume they don't pair with anything. */
1751 #define MD_SCHED_VARIABLE_ISSUE(DUMP, SCHED_VERBOSE, INSN, CAN_ISSUE_MORE) \
1752 if (recog_memoized (INSN) < 0 || get_attr_type (INSN) == TYPE_MULTI) \
1753 (CAN_ISSUE_MORE) = 0
1755 /* Compute the cost of computing a constant rtl expression RTX
1756 whose rtx-code is CODE. The body of this macro is a portion
1757 of a switch statement. If the code is computed here,
1758 return it with a return statement. Otherwise, break from the switch.
1760 If this is an 8-bit constant, return zero since it can be used
1761 nearly anywhere with no cost. If it is a valid operand for an
1762 ADD or AND, likewise return 0 if we know it will be used in that
1763 context. Otherwise, return 2 since it might be used there later.
1764 All other constants take at least two insns. */
1766 #define CONST_COSTS(RTX,CODE,OUTER_CODE) \
1768 if (INTVAL (RTX) >= 0 && INTVAL (RTX) < 256) \
1770 case CONST_DOUBLE: \
1771 if ((RTX) == CONST0_RTX (GET_MODE (RTX))) \
1773 else if (((OUTER_CODE) == PLUS && add_operand (RTX, VOIDmode)) \
1774 || ((OUTER_CODE) == AND && and_operand (RTX, VOIDmode))) \
1776 else if (add_operand (RTX, VOIDmode) || and_operand (RTX, VOIDmode)) \
1779 return COSTS_N_INSNS (2); \
1783 switch (alpha_cpu) \
1785 case PROCESSOR_EV4: \
1786 return COSTS_N_INSNS (3); \
1787 case PROCESSOR_EV5: \
1788 case PROCESSOR_EV6: \
1789 return COSTS_N_INSNS (2); \
1793 /* Provide the costs of a rtl expression. This is in the body of a
1796 #define RTX_COSTS(X,CODE,OUTER_CODE) \
1797 case PLUS: case MINUS: \
1798 if (FLOAT_MODE_P (GET_MODE (X))) \
1799 switch (alpha_cpu) \
1801 case PROCESSOR_EV4: \
1802 return COSTS_N_INSNS (6); \
1803 case PROCESSOR_EV5: \
1804 case PROCESSOR_EV6: \
1805 return COSTS_N_INSNS (4); \
1808 else if (GET_CODE (XEXP (X, 0)) == MULT \
1809 && const48_operand (XEXP (XEXP (X, 0), 1), VOIDmode)) \
1810 return (2 + rtx_cost (XEXP (XEXP (X, 0), 0), OUTER_CODE) \
1811 + rtx_cost (XEXP (X, 1), OUTER_CODE)); \
1814 switch (alpha_cpu) \
1816 case PROCESSOR_EV4: \
1817 if (FLOAT_MODE_P (GET_MODE (X))) \
1818 return COSTS_N_INSNS (6); \
1819 return COSTS_N_INSNS (23); \
1820 case PROCESSOR_EV5: \
1821 if (FLOAT_MODE_P (GET_MODE (X))) \
1822 return COSTS_N_INSNS (4); \
1823 else if (GET_MODE (X) == DImode) \
1824 return COSTS_N_INSNS (12); \
1826 return COSTS_N_INSNS (8); \
1827 case PROCESSOR_EV6: \
1828 if (FLOAT_MODE_P (GET_MODE (X))) \
1829 return COSTS_N_INSNS (4); \
1831 return COSTS_N_INSNS (7); \
1835 if (GET_CODE (XEXP (X, 1)) == CONST_INT \
1836 && INTVAL (XEXP (X, 1)) <= 3) \
1838 /* ... fall through ... */ \
1839 case ASHIFTRT: case LSHIFTRT: \
1840 switch (alpha_cpu) \
1842 case PROCESSOR_EV4: \
1843 return COSTS_N_INSNS (2); \
1844 case PROCESSOR_EV5: \
1845 case PROCESSOR_EV6: \
1846 return COSTS_N_INSNS (1); \
1849 case IF_THEN_ELSE: \
1850 switch (alpha_cpu) \
1852 case PROCESSOR_EV4: \
1853 case PROCESSOR_EV6: \
1854 return COSTS_N_INSNS (2); \
1855 case PROCESSOR_EV5: \
1856 return COSTS_N_INSNS (1); \
1859 case DIV: case UDIV: case MOD: case UMOD: \
1860 switch (alpha_cpu) \
1862 case PROCESSOR_EV4: \
1863 if (GET_MODE (X) == SFmode) \
1864 return COSTS_N_INSNS (34); \
1865 else if (GET_MODE (X) == DFmode) \
1866 return COSTS_N_INSNS (63); \
1868 return COSTS_N_INSNS (70); \
1869 case PROCESSOR_EV5: \
1870 if (GET_MODE (X) == SFmode) \
1871 return COSTS_N_INSNS (15); \
1872 else if (GET_MODE (X) == DFmode) \
1873 return COSTS_N_INSNS (22); \
1875 return COSTS_N_INSNS (70); /* ??? */ \
1876 case PROCESSOR_EV6: \
1877 if (GET_MODE (X) == SFmode) \
1878 return COSTS_N_INSNS (12); \
1879 else if (GET_MODE (X) == DFmode) \
1880 return COSTS_N_INSNS (15); \
1882 return COSTS_N_INSNS (70); /* ??? */ \
1886 switch (alpha_cpu) \
1888 case PROCESSOR_EV4: \
1889 case PROCESSOR_EV6: \
1890 return COSTS_N_INSNS (3); \
1891 case PROCESSOR_EV5: \
1892 return COSTS_N_INSNS (2); \
1895 case NEG: case ABS: \
1896 if (! FLOAT_MODE_P (GET_MODE (X))) \
1898 /* ... fall through ... */ \
1899 case FLOAT: case UNSIGNED_FLOAT: case FIX: case UNSIGNED_FIX: \
1900 case FLOAT_EXTEND: case FLOAT_TRUNCATE: \
1901 switch (alpha_cpu) \
1903 case PROCESSOR_EV4: \
1904 return COSTS_N_INSNS (6); \
1905 case PROCESSOR_EV5: \
1906 case PROCESSOR_EV6: \
1907 return COSTS_N_INSNS (4); \
1911 /* Control the assembler format that we output. */
1913 /* We don't emit these labels, so as to avoid getting linker errors about
1914 missing exception handling info. If we emit a gcc_compiled. label into
1915 text, and the file has no code, then the DEC assembler gives us a zero
1916 sized text section with no associated exception handling info. The
1917 DEC linker sees this text section, and gives a warning saying that
1918 the exception handling info is missing. */
1919 #define ASM_IDENTIFY_GCC(x)
1920 #define ASM_IDENTIFY_LANGUAGE(x)
1922 /* Output to assembler file text saying following lines
1923 may contain character constants, extra white space, comments, etc. */
1925 #define ASM_APP_ON ""
1927 /* Output to assembler file text saying following lines
1928 no longer contain unusual constructs. */
1930 #define ASM_APP_OFF ""
1932 #define TEXT_SECTION_ASM_OP ".text"
1934 /* Output before read-only data. */
1936 #define READONLY_DATA_SECTION_ASM_OP ".rdata"
1938 /* Output before writable data. */
1940 #define DATA_SECTION_ASM_OP ".data"
1942 /* Define an extra section for read-only data, a routine to enter it, and
1943 indicate that it is for read-only data.
1945 The first time we enter the readonly data section for a file, we write
1946 eight bytes of zero. This works around a bug in DEC's assembler in
1947 some versions of OSF/1 V3.x. */
1949 #define EXTRA_SECTIONS readonly_data
1951 #define EXTRA_SECTION_FUNCTIONS \
1953 literal_section () \
1955 if (in_section != readonly_data) \
1957 static int firsttime = 1; \
1959 fprintf (asm_out_file, "%s\n", READONLY_DATA_SECTION_ASM_OP); \
1963 ASM_OUTPUT_DOUBLE_INT (asm_out_file, const0_rtx); \
1966 in_section = readonly_data; \
1970 #define READONLY_DATA_SECTION literal_section
1972 /* If we are referencing a function that is static, make the SYMBOL_REF
1973 special. We use this to see indicate we can branch to this function
1974 without setting PV or restoring GP. */
1976 #define ENCODE_SECTION_INFO(DECL) \
1977 if (TREE_CODE (DECL) == FUNCTION_DECL && ! TREE_PUBLIC (DECL)) \
1978 SYMBOL_REF_FLAG (XEXP (DECL_RTL (DECL), 0)) = 1;
1980 /* How to refer to registers in assembler output.
1981 This sequence is indexed by compiler's hard-register-number (see above). */
1983 #define REGISTER_NAMES \
1984 {"$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7", "$8", \
1985 "$9", "$10", "$11", "$12", "$13", "$14", "$15", \
1986 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", \
1987 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "AP", \
1988 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", "$f8", \
1989 "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", \
1990 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23",\
1991 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "FP"}
1993 /* How to renumber registers for dbx and gdb. */
1995 #define DBX_REGISTER_NUMBER(REGNO) (REGNO)
1997 /* This is how to output the definition of a user-level label named NAME,
1998 such as the label on a static function or variable NAME. */
2000 #define ASM_OUTPUT_LABEL(FILE,NAME) \
2001 do { assemble_name (FILE, NAME); fputs (":\n", FILE); } while (0)
2003 /* This is how to output a command to make the user-level label named NAME
2004 defined for reference from other files. */
2006 #define ASM_GLOBALIZE_LABEL(FILE,NAME) \
2007 do { fputs ("\t.globl ", FILE); assemble_name (FILE, NAME); fputs ("\n", FILE);} while (0)
2009 /* The prefix to add to user-visible assembler symbols. */
2011 #define USER_LABEL_PREFIX ""
2013 /* This is how to output an internal numbered label where
2014 PREFIX is the class of label and NUM is the number within the class. */
2016 #define ASM_OUTPUT_INTERNAL_LABEL(FILE,PREFIX,NUM) \
2017 fprintf (FILE, "$%s%d:\n", PREFIX, NUM)
2019 /* This is how to output a label for a jump table. Arguments are the same as
2020 for ASM_OUTPUT_INTERNAL_LABEL, except the insn for the jump table is
2023 #define ASM_OUTPUT_CASE_LABEL(FILE,PREFIX,NUM,TABLEINSN) \
2024 { ASM_OUTPUT_ALIGN (FILE, 2); ASM_OUTPUT_INTERNAL_LABEL (FILE, PREFIX, NUM); }
2026 /* This is how to store into the string LABEL
2027 the symbol_ref name of an internal numbered label where
2028 PREFIX is the class of label and NUM is the number within the class.
2029 This is suitable for output with `assemble_name'. */
2031 #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \
2032 sprintf ((LABEL), "*$%s%ld", (PREFIX), (long)(NUM))
2034 /* Check a floating-point value for validity for a particular machine mode. */
2036 #define CHECK_FLOAT_VALUE(MODE, D, OVERFLOW) \
2037 ((OVERFLOW) = check_float_value (MODE, &D, OVERFLOW))
2039 /* This is how to output an assembler line defining a `double' constant. */
2041 #define ASM_OUTPUT_DOUBLE(FILE,VALUE) \
2043 if (REAL_VALUE_ISINF (VALUE) \
2044 || REAL_VALUE_ISNAN (VALUE) \
2045 || REAL_VALUE_MINUS_ZERO (VALUE)) \
2048 REAL_VALUE_TO_TARGET_DOUBLE ((VALUE), t); \
2049 fprintf (FILE, "\t.quad 0x%lx%08lx\n", \
2050 t[1] & 0xffffffff, t[0] & 0xffffffff); \
2055 REAL_VALUE_TO_DECIMAL (VALUE, "%.20e", str); \
2056 fprintf (FILE, "\t.%c_floating %s\n", (TARGET_FLOAT_VAX)?'g':'t', str); \
2060 /* This is how to output an assembler line defining a `float' constant. */
2062 #define ASM_OUTPUT_FLOAT(FILE,VALUE) \
2065 REAL_VALUE_TO_TARGET_SINGLE ((VALUE), t); \
2066 fprintf (FILE, "\t.long 0x%lx\n", t & 0xffffffff); \
2069 /* This is how to output an assembler line defining an `int' constant. */
2071 #define ASM_OUTPUT_INT(FILE,VALUE) \
2072 ( fprintf (FILE, "\t.long "), \
2073 output_addr_const (FILE, (VALUE)), \
2074 fprintf (FILE, "\n"))
2076 /* This is how to output an assembler line defining a `long' constant. */
2078 #define ASM_OUTPUT_DOUBLE_INT(FILE,VALUE) \
2079 ( fprintf (FILE, "\t.quad "), \
2080 output_addr_const (FILE, (VALUE)), \
2081 fprintf (FILE, "\n"))
2083 /* Likewise for `char' and `short' constants. */
2085 #define ASM_OUTPUT_SHORT(FILE,VALUE) \
2086 fprintf (FILE, "\t.word %d\n", \
2087 (int)(GET_CODE (VALUE) == CONST_INT \
2088 ? INTVAL (VALUE) & 0xffff : (abort (), 0)))
2090 #define ASM_OUTPUT_CHAR(FILE,VALUE) \
2091 fprintf (FILE, "\t.byte %d\n", \
2092 (int)(GET_CODE (VALUE) == CONST_INT \
2093 ? INTVAL (VALUE) & 0xff : (abort (), 0)))
2095 /* We use the default ASCII-output routine, except that we don't write more
2096 than 50 characters since the assembler doesn't support very long lines. */
2098 #define ASM_OUTPUT_ASCII(MYFILE, MYSTRING, MYLENGTH) \
2100 FILE *_hide_asm_out_file = (MYFILE); \
2101 const unsigned char *_hide_p = (const unsigned char *) (MYSTRING); \
2102 int _hide_thissize = (MYLENGTH); \
2103 int _size_so_far = 0; \
2105 FILE *asm_out_file = _hide_asm_out_file; \
2106 const unsigned char *p = _hide_p; \
2107 int thissize = _hide_thissize; \
2109 fprintf (asm_out_file, "\t.ascii \""); \
2111 for (i = 0; i < thissize; i++) \
2113 register int c = p[i]; \
2115 if (_size_so_far ++ > 50 && i < thissize - 4) \
2116 _size_so_far = 0, fprintf (asm_out_file, "\"\n\t.ascii \""); \
2118 if (c == '\"' || c == '\\') \
2119 putc ('\\', asm_out_file); \
2120 if (c >= ' ' && c < 0177) \
2121 putc (c, asm_out_file); \
2124 fprintf (asm_out_file, "\\%o", c); \
2125 /* After an octal-escape, if a digit follows, \
2126 terminate one string constant and start another. \
2127 The Vax assembler fails to stop reading the escape \
2128 after three digits, so this is the only way we \
2129 can get it to parse the data properly. */ \
2130 if (i < thissize - 1 \
2131 && p[i + 1] >= '0' && p[i + 1] <= '9') \
2132 _size_so_far = 0, fprintf (asm_out_file, "\"\n\t.ascii \""); \
2135 fprintf (asm_out_file, "\"\n"); \
2140 /* To get unaligned data, we have to turn off auto alignment. */
2141 #define UNALIGNED_SHORT_ASM_OP ".align 0\n\t.word"
2142 #define UNALIGNED_INT_ASM_OP ".align 0\n\t.long"
2143 #define UNALIGNED_DOUBLE_INT_ASM_OP ".align 0\n\t.quad"
2145 /* This is how to output an insn to push a register on the stack.
2146 It need not be very fast code. */
2148 #define ASM_OUTPUT_REG_PUSH(FILE,REGNO) \
2149 fprintf (FILE, "\tsubq $30,8,$30\n\tst%s $%s%d,0($30)\n", \
2150 (REGNO) > 32 ? "t" : "q", (REGNO) > 32 ? "f" : "", \
2153 /* This is how to output an insn to pop a register from the stack.
2154 It need not be very fast code. */
2156 #define ASM_OUTPUT_REG_POP(FILE,REGNO) \
2157 fprintf (FILE, "\tld%s $%s%d,0($30)\n\taddq $30,8,$30\n", \
2158 (REGNO) > 32 ? "t" : "q", (REGNO) > 32 ? "f" : "", \
2161 /* This is how to output an assembler line for a numeric constant byte. */
2163 #define ASM_OUTPUT_BYTE(FILE,VALUE) \
2164 fprintf (FILE, "\t.byte 0x%x\n", (int) ((VALUE) & 0xff))
2166 /* This is how to output an element of a case-vector that is absolute.
2167 (Alpha does not use such vectors, but we must define this macro anyway.) */
2169 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) abort ()
2171 /* This is how to output an element of a case-vector that is relative. */
2173 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
2174 fprintf (FILE, "\t.%s $L%d\n", TARGET_WINDOWS_NT ? "long" : "gprel32", \
2177 /* This is how to output an assembler line
2178 that says to advance the location counter
2179 to a multiple of 2**LOG bytes. */
2181 #define ASM_OUTPUT_ALIGN(FILE,LOG) \
2183 fprintf (FILE, "\t.align %d\n", LOG);
2185 /* This is how to advance the location counter by SIZE bytes. */
2187 #define ASM_OUTPUT_SKIP(FILE,SIZE) \
2188 fprintf (FILE, "\t.space %d\n", (SIZE))
2190 /* This says how to output an assembler line
2191 to define a global common symbol. */
2193 #define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED) \
2194 ( fputs ("\t.comm ", (FILE)), \
2195 assemble_name ((FILE), (NAME)), \
2196 fprintf ((FILE), ",%d\n", (SIZE)))
2198 /* This says how to output an assembler line
2199 to define a local common symbol. */
2201 #define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE,ROUNDED) \
2202 ( fputs ("\t.lcomm ", (FILE)), \
2203 assemble_name ((FILE), (NAME)), \
2204 fprintf ((FILE), ",%d\n", (SIZE)))
2206 /* Store in OUTPUT a string (made with alloca) containing
2207 an assembler-name for a local static variable named NAME.
2208 LABELNO is an integer which is different for each call. */
2210 #define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO) \
2211 ( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 10), \
2212 sprintf ((OUTPUT), "%s.%d", (NAME), (LABELNO)))
2214 /* Define the parentheses used to group arithmetic operations
2215 in assembler code. */
2217 #define ASM_OPEN_PAREN "("
2218 #define ASM_CLOSE_PAREN ")"
2220 /* Output code to add DELTA to the first argument, and then jump to FUNCTION.
2221 Used for C++ multiple inheritance. */
2223 #define ASM_OUTPUT_MI_THUNK(FILE, THUNK_FNDECL, DELTA, FUNCTION) \
2225 const char *fn_name = XSTR (XEXP (DECL_RTL (FUNCTION), 0), 0); \
2228 /* Mark end of prologue. */ \
2229 output_end_prologue (FILE); \
2231 /* Rely on the assembler to macro expand a large delta. */ \
2232 reg = aggregate_value_p (TREE_TYPE (TREE_TYPE (FUNCTION))) ? 17 : 16; \
2233 fprintf (FILE, "\tlda $%d,%ld($%d)\n", reg, (long)(DELTA), reg); \
2235 if (current_file_function_operand (XEXP (DECL_RTL (FUNCTION), 0), \
2238 fprintf (FILE, "\tbr $31,$"); \
2239 assemble_name (FILE, fn_name); \
2240 fprintf (FILE, "..ng\n"); \
2244 fprintf (FILE, "\tjmp $31,"); \
2245 assemble_name (FILE, fn_name); \
2246 fputc ('\n', FILE); \
2251 /* Define results of standard character escape sequences. */
2252 #define TARGET_BELL 007
2253 #define TARGET_BS 010
2254 #define TARGET_TAB 011
2255 #define TARGET_NEWLINE 012
2256 #define TARGET_VT 013
2257 #define TARGET_FF 014
2258 #define TARGET_CR 015
2260 /* Print operand X (an rtx) in assembler syntax to file FILE.
2261 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
2262 For `%' followed by punctuation, CODE is the punctuation and X is null. */
2264 #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE)
2266 /* Determine which codes are valid without a following integer. These must
2267 not be alphabetic (the characters are chosen so that
2268 PRINT_OPERAND_PUNCT_VALID_P translates into a simple range change when
2271 & Generates fp-rounding mode suffix: nothing for normal, 'c' for
2272 chopped, 'm' for minus-infinity, and 'd' for dynamic rounding
2273 mode. alpha_fprm controls which suffix is generated.
2275 ' Generates trap-mode suffix for instructions that accept the
2276 su suffix only (cmpt et al).
2278 ` Generates trap-mode suffix for instructions that accept the
2279 v and sv suffix. The only instruction that needs this is cvtql.
2281 ( Generates trap-mode suffix for instructions that accept the
2282 v, sv, and svi suffix. The only instruction that needs this
2285 ) Generates trap-mode suffix for instructions that accept the
2286 u, su, and sui suffix. This is the bulk of the IEEE floating
2287 point instructions (addt et al).
2289 + Generates trap-mode suffix for instructions that accept the
2290 sui suffix (cvtqt and cvtqs).
2292 , Generates single precision suffix for floating point
2293 instructions (s for IEEE, f for VAX)
2295 - Generates double precision suffix for floating point
2296 instructions (t for IEEE, g for VAX)
2299 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) \
2300 ((CODE) == '&' || (CODE) == '`' || (CODE) == '\'' || (CODE) == '(' \
2301 || (CODE) == ')' || (CODE) == '+' || (CODE) == ',' || (CODE) == '-')
2303 /* Print a memory address as an operand to reference that memory location. */
2305 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) \
2306 print_operand_address((FILE), (ADDR))
2308 /* Define the codes that are matched by predicates in alpha.c. */
2310 #define PREDICATE_CODES \
2311 {"reg_or_0_operand", {SUBREG, REG, CONST_INT}}, \
2312 {"reg_or_6bit_operand", {SUBREG, REG, CONST_INT}}, \
2313 {"reg_or_8bit_operand", {SUBREG, REG, CONST_INT}}, \
2314 {"cint8_operand", {CONST_INT}}, \
2315 {"reg_or_cint_operand", {SUBREG, REG, CONST_INT}}, \
2316 {"add_operand", {SUBREG, REG, CONST_INT}}, \
2317 {"sext_add_operand", {SUBREG, REG, CONST_INT}}, \
2318 {"const48_operand", {CONST_INT}}, \
2319 {"and_operand", {SUBREG, REG, CONST_INT}}, \
2320 {"or_operand", {SUBREG, REG, CONST_INT}}, \
2321 {"mode_mask_operand", {CONST_INT}}, \
2322 {"mul8_operand", {CONST_INT}}, \
2323 {"mode_width_operand", {CONST_INT}}, \
2324 {"reg_or_fp0_operand", {SUBREG, REG, CONST_DOUBLE}}, \
2325 {"alpha_comparison_operator", {EQ, LE, LT, LEU, LTU}}, \
2326 {"alpha_swapped_comparison_operator", {EQ, GE, GT, GEU, GTU}}, \
2327 {"signed_comparison_operator", {EQ, NE, LE, LT, GE, GT}}, \
2328 {"divmod_operator", {DIV, MOD, UDIV, UMOD}}, \
2329 {"fp0_operand", {CONST_DOUBLE}}, \
2330 {"current_file_function_operand", {SYMBOL_REF}}, \
2331 {"call_operand", {REG, SYMBOL_REF}}, \
2332 {"input_operand", {SUBREG, REG, MEM, CONST_INT, CONST_DOUBLE, \
2333 SYMBOL_REF, CONST, LABEL_REF}}, \
2334 {"some_operand", {SUBREG, REG, MEM, CONST_INT, CONST_DOUBLE, \
2335 SYMBOL_REF, CONST, LABEL_REF}}, \
2336 {"some_ni_operand", {SUBREG, REG, MEM}}, \
2337 {"aligned_memory_operand", {MEM}}, \
2338 {"unaligned_memory_operand", {MEM}}, \
2339 {"reg_or_unaligned_mem_operand", {SUBREG, REG, MEM}}, \
2340 {"any_memory_operand", {MEM}}, \
2341 {"hard_fp_register_operand", {SUBREG, REG}}, \
2342 {"reg_not_elim_operand", {SUBREG, REG}}, \
2343 {"reg_no_subreg_operand", {REG}},
2345 /* Define the `__builtin_va_list' type for the ABI. */
2346 #define BUILD_VA_LIST_TYPE(VALIST) \
2347 (VALIST) = alpha_build_va_list ()
2349 /* Implement `va_start' for varargs and stdarg. */
2350 #define EXPAND_BUILTIN_VA_START(stdarg, valist, nextarg) \
2351 alpha_va_start (stdarg, valist, nextarg)
2353 /* Implement `va_arg'. */
2354 #define EXPAND_BUILTIN_VA_ARG(valist, type) \
2355 alpha_va_arg (valist, type)
2357 /* Tell collect that the object format is ECOFF. */
2358 #define OBJECT_FORMAT_COFF
2359 #define EXTENDED_COFF
2361 /* If we use NM, pass -g to it so it only lists globals. */
2362 #define NM_FLAGS "-pg"
2364 /* Definitions for debugging. */
2366 #define SDB_DEBUGGING_INFO /* generate info for mips-tfile */
2367 #define DBX_DEBUGGING_INFO /* generate embedded stabs */
2368 #define MIPS_DEBUGGING_INFO /* MIPS specific debugging info */
2370 #ifndef PREFERRED_DEBUGGING_TYPE /* assume SDB_DEBUGGING_INFO */
2371 #define PREFERRED_DEBUGGING_TYPE SDB_DEBUG
2375 /* Correct the offset of automatic variables and arguments. Note that
2376 the Alpha debug format wants all automatic variables and arguments
2377 to be in terms of two different offsets from the virtual frame pointer,
2378 which is the stack pointer before any adjustment in the function.
2379 The offset for the argument pointer is fixed for the native compiler,
2380 it is either zero (for the no arguments case) or large enough to hold
2381 all argument registers.
2382 The offset for the auto pointer is the fourth argument to the .frame
2383 directive (local_offset).
2384 To stay compatible with the native tools we use the same offsets
2385 from the virtual frame pointer and adjust the debugger arg/auto offsets
2386 accordingly. These debugger offsets are set up in output_prolog. */
2388 extern long alpha_arg_offset;
2389 extern long alpha_auto_offset;
2390 #define DEBUGGER_AUTO_OFFSET(X) \
2391 ((GET_CODE (X) == PLUS ? INTVAL (XEXP (X, 1)) : 0) + alpha_auto_offset)
2392 #define DEBUGGER_ARG_OFFSET(OFFSET, X) (OFFSET + alpha_arg_offset)
2395 #define ASM_OUTPUT_SOURCE_LINE(STREAM, LINE) \
2396 alpha_output_lineno (STREAM, LINE)
2398 #define ASM_OUTPUT_SOURCE_FILENAME(STREAM, NAME) \
2399 alpha_output_filename (STREAM, NAME)
2401 /* mips-tfile.c limits us to strings of one page. We must underestimate this
2402 number, because the real length runs past this up to the next
2403 continuation point. This is really a dbxout.c bug. */
2404 #define DBX_CONTIN_LENGTH 3000
2406 /* By default, turn on GDB extensions. */
2407 #define DEFAULT_GDB_EXTENSIONS 1
2409 /* Stabs-in-ECOFF can't handle dbxout_function_end(). */
2410 #define NO_DBX_FUNCTION_END 1
2412 /* If we are smuggling stabs through the ALPHA ECOFF object
2413 format, put a comment in front of the .stab<x> operation so
2414 that the ALPHA assembler does not choke. The mips-tfile program
2415 will correctly put the stab into the object file. */
2417 #define ASM_STABS_OP ((TARGET_GAS) ? ".stabs" : " #.stabs")
2418 #define ASM_STABN_OP ((TARGET_GAS) ? ".stabn" : " #.stabn")
2419 #define ASM_STABD_OP ((TARGET_GAS) ? ".stabd" : " #.stabd")
2421 /* Forward references to tags are allowed. */
2422 #define SDB_ALLOW_FORWARD_REFERENCES
2424 /* Unknown tags are also allowed. */
2425 #define SDB_ALLOW_UNKNOWN_REFERENCES
2427 #define PUT_SDB_DEF(a) \
2429 fprintf (asm_out_file, "\t%s.def\t", \
2430 (TARGET_GAS) ? "" : "#"); \
2431 ASM_OUTPUT_LABELREF (asm_out_file, a); \
2432 fputc (';', asm_out_file); \
2435 #define PUT_SDB_PLAIN_DEF(a) \
2437 fprintf (asm_out_file, "\t%s.def\t.%s;", \
2438 (TARGET_GAS) ? "" : "#", (a)); \
2441 #define PUT_SDB_TYPE(a) \
2443 fprintf (asm_out_file, "\t.type\t0x%x;", (a)); \
2446 /* For block start and end, we create labels, so that
2447 later we can figure out where the correct offset is.
2448 The normal .ent/.end serve well enough for functions,
2449 so those are just commented out. */
2451 extern int sdb_label_count; /* block start/end next label # */
2453 #define PUT_SDB_BLOCK_START(LINE) \
2455 fprintf (asm_out_file, \
2456 "$Lb%d:\n\t%s.begin\t$Lb%d\t%d\n", \
2458 (TARGET_GAS) ? "" : "#", \
2461 sdb_label_count++; \
2464 #define PUT_SDB_BLOCK_END(LINE) \
2466 fprintf (asm_out_file, \
2467 "$Le%d:\n\t%s.bend\t$Le%d\t%d\n", \
2469 (TARGET_GAS) ? "" : "#", \
2472 sdb_label_count++; \
2475 #define PUT_SDB_FUNCTION_START(LINE)
2477 #define PUT_SDB_FUNCTION_END(LINE)
2479 #define PUT_SDB_EPILOGUE_END(NAME) ((void)(NAME))
2481 /* Macros for mips-tfile.c to encapsulate stabs in ECOFF, and for
2482 mips-tdump.c to print them out.
2484 These must match the corresponding definitions in gdb/mipsread.c.
2485 Unfortunately, gcc and gdb do not currently share any directories. */
2487 #define CODE_MASK 0x8F300
2488 #define MIPS_IS_STAB(sym) (((sym)->index & 0xFFF00) == CODE_MASK)
2489 #define MIPS_MARK_STAB(code) ((code)+CODE_MASK)
2490 #define MIPS_UNMARK_STAB(code) ((code)-CODE_MASK)
2492 /* Override some mips-tfile definitions. */
2494 #define SHASH_SIZE 511
2495 #define THASH_SIZE 55
2497 /* Align ecoff symbol tables to avoid OSF1/1.3 nm complaints. */
2499 #define ALIGN_SYMTABLE_OFFSET(OFFSET) (((OFFSET) + 7) & ~7)
2501 /* The linker will stick __main into the .init section. */
2502 #define HAS_INIT_SECTION
2503 #define LD_INIT_SWITCH "-init"
2504 #define LD_FINI_SWITCH "-fini"
2506 /* The system headers under Alpha systems are generally C++-aware. */
2507 #define NO_IMPLICIT_EXTERN_C
2509 /* Generate calls to memcpy, etc., not bcopy, etc. */
2510 #define TARGET_MEM_FUNCTIONS 1