1 /* Definitions of target machine for GNU compiler, for DEC Alpha.
2 Copyright (C) 1992, 93, 94, 95, 96, 97, 1998 Free Software Foundation, Inc.
3 Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
5 This file is part of GNU CC.
7 GNU CC is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GNU CC is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GNU CC; see the file COPYING. If not, write to
19 the Free Software Foundation, 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
23 /* Write out the correct language type definition for the header files.
24 Unless we have assembler language, write out the symbols for C. */
27 %{.S:-D__LANGUAGE_ASSEMBLY__ -D__LANGUAGE_ASSEMBLY %{!ansi:-DLANGUAGE_ASSEMBLY }}\
28 %{.cc|.cxx|.C:-D__LANGUAGE_C_PLUS_PLUS__ -D__LANGUAGE_C_PLUS_PLUS -D__cplusplus }\
29 %{.m:-D__LANGUAGE_OBJECTIVE_C__ -D__LANGUAGE_OBJECTIVE_C }\
30 %{!.S:%{!.cc:%{!.cxx:%{!.C:%{!.m:-D__LANGUAGE_C__ -D__LANGUAGE_C %{!ansi:-DLANGUAGE_C }}}}}}\
32 %{mieee-with-inexact:-D_IEEE_FP -D_IEEE_FP_INEXACT }}\
33 %(cpp_cpu) %(cpp_subtarget)"
35 #ifndef CPP_SUBTARGET_SPEC
36 #define CPP_SUBTARGET_SPEC ""
39 /* Set the spec to use for signed char. The default tests the above macro
40 but DEC's compiler can't handle the conditional in a "constant"
43 #define SIGNED_CHAR_SPEC "%{funsigned-char:-D__CHAR_UNSIGNED__}"
45 #define WORD_SWITCH_TAKES_ARG(STR) \
46 (!strcmp (STR, "rpath") || !strcmp (STR, "include") \
47 || !strcmp (STR, "imacros") || !strcmp (STR, "aux-info") \
48 || !strcmp (STR, "idirafter") || !strcmp (STR, "iprefix") \
49 || !strcmp (STR, "iwithprefix") || !strcmp (STR, "iwithprefixbefore") \
50 || !strcmp (STR, "isystem"))
52 /* Print subsidiary information on the compiler version in use. */
53 #define TARGET_VERSION
55 /* Run-time compilation parameters selecting different hardware subsets. */
57 /* Which processor to schedule for. The cpu attribute defines a list that
58 mirrors this list, so changes to alpha.md must be made at the same time. */
61 {PROCESSOR_EV4, /* 2106[46]{a,} */
62 PROCESSOR_EV5, /* 21164{a,pc,} */
63 PROCESSOR_EV6}; /* 21264 */
65 extern enum processor_type alpha_cpu;
67 enum alpha_trap_precision
69 ALPHA_TP_PROG, /* No precision (default). */
70 ALPHA_TP_FUNC, /* Trap contained within originating function. */
71 ALPHA_TP_INSN /* Instruction accuracy and code is resumption safe. */
74 enum alpha_fp_rounding_mode
76 ALPHA_FPRM_NORM, /* Normal rounding mode. */
77 ALPHA_FPRM_MINF, /* Round towards minus-infinity. */
78 ALPHA_FPRM_CHOP, /* Chopped rounding mode (towards 0). */
79 ALPHA_FPRM_DYN /* Dynamic rounding mode. */
82 enum alpha_fp_trap_mode
84 ALPHA_FPTM_N, /* Normal trap mode. */
85 ALPHA_FPTM_U, /* Underflow traps enabled. */
86 ALPHA_FPTM_SU, /* Software completion, w/underflow traps */
87 ALPHA_FPTM_SUI /* Software completion, w/underflow & inexact traps */
90 extern int target_flags;
92 extern enum alpha_trap_precision alpha_tp;
93 extern enum alpha_fp_rounding_mode alpha_fprm;
94 extern enum alpha_fp_trap_mode alpha_fptm;
96 /* This means that floating-point support exists in the target implementation
97 of the Alpha architecture. This is usually the default. */
100 #define TARGET_FP (target_flags & MASK_FP)
102 /* This means that floating-point registers are allowed to be used. Note
103 that Alpha implementations without FP operations are required to
104 provide the FP registers. */
106 #define MASK_FPREGS 2
107 #define TARGET_FPREGS (target_flags & MASK_FPREGS)
109 /* This means that gas is used to process the assembler file. */
112 #define TARGET_GAS (target_flags & MASK_GAS)
114 /* This means that we should mark procedures as IEEE conformant. */
116 #define MASK_IEEE_CONFORMANT 8
117 #define TARGET_IEEE_CONFORMANT (target_flags & MASK_IEEE_CONFORMANT)
119 /* This means we should be IEEE-compliant except for inexact. */
122 #define TARGET_IEEE (target_flags & MASK_IEEE)
124 /* This means we should be fully IEEE-compliant. */
126 #define MASK_IEEE_WITH_INEXACT 32
127 #define TARGET_IEEE_WITH_INEXACT (target_flags & MASK_IEEE_WITH_INEXACT)
129 /* This means we must construct all constants rather than emitting
130 them as literal data. */
132 #define MASK_BUILD_CONSTANTS 128
133 #define TARGET_BUILD_CONSTANTS (target_flags & MASK_BUILD_CONSTANTS)
135 /* This means we handle floating points in VAX F- (float)
136 or G- (double) Format. */
138 #define MASK_FLOAT_VAX 512
139 #define TARGET_FLOAT_VAX (target_flags & MASK_FLOAT_VAX)
141 /* This means that the processor has byte and half word loads and stores
142 (the BWX extension). */
144 #define MASK_BWX 1024
145 #define TARGET_BWX (target_flags & MASK_BWX)
147 /* This means that the processor has the CIX extension. */
148 #define MASK_CIX 2048
149 #define TARGET_CIX (target_flags & MASK_CIX)
151 /* This means that the processor has the MAX extension. */
152 #define MASK_MAX 4096
153 #define TARGET_MAX (target_flags & MASK_MAX)
155 /* This means that the processor is an EV5, EV56, or PCA56. This is defined
156 only in TARGET_CPU_DEFAULT. */
157 #define MASK_CPU_EV5 8192
159 /* Likewise for EV6. */
160 #define MASK_CPU_EV6 16384
162 /* This means we support the .arch directive in the assembler. Only
163 defined in TARGET_CPU_DEFAULT. */
164 #define MASK_SUPPORT_ARCH 32768
165 #define TARGET_SUPPORT_ARCH (target_flags & MASK_SUPPORT_ARCH)
167 /* These are for target os support and cannot be changed at runtime. */
168 #ifndef TARGET_WINDOWS_NT
169 #define TARGET_WINDOWS_NT 0
171 #ifndef TARGET_OPEN_VMS
172 #define TARGET_OPEN_VMS 0
175 #ifndef TARGET_AS_CAN_SUBTRACT_LABELS
176 #define TARGET_AS_CAN_SUBTRACT_LABELS TARGET_GAS
178 #ifndef TARGET_CAN_FAULT_IN_PROLOGUE
179 #define TARGET_CAN_FAULT_IN_PROLOGUE 0
182 /* Macro to define tables used to set the flags.
183 This is a list in braces of pairs in braces,
184 each pair being { "NAME", VALUE }
185 where VALUE is the bits to set or minus the bits to clear.
186 An empty string NAME is used to identify the default VALUE. */
188 #define TARGET_SWITCHES \
189 { {"no-soft-float", MASK_FP}, \
190 {"soft-float", - MASK_FP}, \
191 {"fp-regs", MASK_FPREGS}, \
192 {"no-fp-regs", - (MASK_FP|MASK_FPREGS)}, \
193 {"alpha-as", -MASK_GAS}, \
195 {"ieee-conformant", MASK_IEEE_CONFORMANT}, \
196 {"ieee", MASK_IEEE|MASK_IEEE_CONFORMANT}, \
197 {"ieee-with-inexact", MASK_IEEE_WITH_INEXACT|MASK_IEEE_CONFORMANT}, \
198 {"build-constants", MASK_BUILD_CONSTANTS}, \
199 {"float-vax", MASK_FLOAT_VAX}, \
200 {"float-ieee", -MASK_FLOAT_VAX}, \
202 {"no-bwx", -MASK_BWX}, \
204 {"no-cix", -MASK_CIX}, \
206 {"no-max", -MASK_MAX}, \
207 {"", TARGET_DEFAULT | TARGET_CPU_DEFAULT} }
209 #define TARGET_DEFAULT MASK_FP|MASK_FPREGS
211 #ifndef TARGET_CPU_DEFAULT
212 #define TARGET_CPU_DEFAULT 0
215 /* This macro is similar to `TARGET_SWITCHES' but defines names of
216 command options that have values. Its definition is an initializer
217 with a subgrouping for each command option.
219 Each subgrouping contains a string constant, that defines the fixed
220 part of the option name, and the address of a variable. The
221 variable, type `char *', is set to the variable part of the given
222 option if the fixed part matches. The actual option name is made
223 by appending `-m' to the specified name.
225 Here is an example which defines `-mshort-data-NUMBER'. If the
226 given option is `-mshort-data-512', the variable `m88k_short_data'
227 will be set to the string `"512"'.
229 extern char *m88k_short_data;
230 #define TARGET_OPTIONS { { "short-data-", &m88k_short_data } } */
232 extern char *alpha_cpu_string; /* For -mcpu= */
233 extern char *alpha_fprm_string; /* For -mfp-rounding-mode=[n|m|c|d] */
234 extern char *alpha_fptm_string; /* For -mfp-trap-mode=[n|u|su|sui] */
235 extern char *alpha_tp_string; /* For -mtrap-precision=[p|f|i] */
236 extern char *alpha_mlat_string; /* For -mmemory-latency= */
238 #define TARGET_OPTIONS \
240 {"cpu=", &alpha_cpu_string}, \
241 {"fp-rounding-mode=", &alpha_fprm_string}, \
242 {"fp-trap-mode=", &alpha_fptm_string}, \
243 {"trap-precision=", &alpha_tp_string}, \
244 {"memory-latency=", &alpha_mlat_string}, \
247 /* Attempt to describe CPU characteristics to the preprocessor. */
249 /* Corresponding to amask... */
250 #define CPP_AM_BWX_SPEC "-D__alpha_bwx__ -Acpu(bwx)"
251 #define CPP_AM_MAX_SPEC "-D__alpha_max__ -Acpu(max)"
252 #define CPP_AM_CIX_SPEC "-D__alpha_cix__ -Acpu(cix)"
254 /* Corresponding to implver... */
255 #define CPP_IM_EV4_SPEC "-D__alpha_ev4__ -Acpu(ev4)"
256 #define CPP_IM_EV5_SPEC "-D__alpha_ev5__ -Acpu(ev5)"
257 #define CPP_IM_EV6_SPEC "-D__alpha_ev6__ -Acpu(ev6)"
259 /* Common combinations. */
260 #define CPP_CPU_EV4_SPEC "%(cpp_im_ev4)"
261 #define CPP_CPU_EV5_SPEC "%(cpp_im_ev5)"
262 #define CPP_CPU_EV56_SPEC "%(cpp_im_ev5) %(cpp_am_bwx)"
263 #define CPP_CPU_PCA56_SPEC "%(cpp_im_ev5) %(cpp_am_bwx) %(cpp_am_max)"
264 #define CPP_CPU_EV6_SPEC "%(cpp_im_ev6) %(cpp_am_bwx) %(cpp_am_max) %(cpp_am_cix)"
266 #ifndef CPP_CPU_DEFAULT_SPEC
267 # if TARGET_CPU_DEFAULT & MASK_CPU_EV6
268 # define CPP_CPU_DEFAULT_SPEC CPP_CPU_EV6_SPEC
270 # if TARGET_CPU_DEFAULT & MASK_CPU_EV5
271 # if TARGET_CPU_DEFAULT & MASK_MAX
272 # define CPP_CPU_DEFAULT_SPEC CPP_CPU_PCA56_SPEC
274 # if TARGET_CPU_DEFAULT & MASK_BWX
275 # define CPP_CPU_DEFAULT_SPEC CPP_CPU_EV56_SPEC
277 # define CPP_CPU_DEFAULT_SPEC CPP_CPU_EV5_SPEC
281 # define CPP_CPU_DEFAULT_SPEC CPP_CPU_EV4_SPEC
284 #endif /* CPP_CPU_DEFAULT_SPEC */
287 #define CPP_CPU_SPEC "\
288 %{!undef:-Acpu(alpha) -Amachine(alpha) -D__alpha -D__alpha__ \
289 %{mcpu=ev4|mcpu=21064:%(cpp_cpu_ev4) }\
290 %{mcpu=ev5|mcpu=21164:%(cpp_cpu_ev5) }\
291 %{mcpu=ev56|mcpu=21164a:%(cpp_cpu_ev56) }\
292 %{mcpu=pca56|mcpu=21164pc|mcpu=21164PC:%(cpp_cpu_pca56) }\
293 %{mcpu=ev6|mcpu=21264:%(cpp_cpu_ev6) }\
294 %{!mcpu*:%(cpp_cpu_default) }}"
297 /* This macro defines names of additional specifications to put in the
298 specs that can be used in various specifications like CC1_SPEC. Its
299 definition is an initializer with a subgrouping for each command option.
301 Each subgrouping contains a string constant, that defines the
302 specification name, and a string constant that used by the GNU CC driver
305 Do not define this macro if it does not need to do anything. */
307 #ifndef SUBTARGET_EXTRA_SPECS
308 #define SUBTARGET_EXTRA_SPECS
311 #define EXTRA_SPECS \
312 { "cpp_am_bwx", CPP_AM_BWX_SPEC }, \
313 { "cpp_am_max", CPP_AM_MAX_SPEC }, \
314 { "cpp_am_cix", CPP_AM_CIX_SPEC }, \
315 { "cpp_im_ev4", CPP_IM_EV4_SPEC }, \
316 { "cpp_im_ev5", CPP_IM_EV5_SPEC }, \
317 { "cpp_im_ev6", CPP_IM_EV6_SPEC }, \
318 { "cpp_cpu_ev4", CPP_CPU_EV4_SPEC }, \
319 { "cpp_cpu_ev5", CPP_CPU_EV5_SPEC }, \
320 { "cpp_cpu_ev56", CPP_CPU_EV56_SPEC }, \
321 { "cpp_cpu_pca56", CPP_CPU_PCA56_SPEC }, \
322 { "cpp_cpu_ev6", CPP_CPU_EV6_SPEC }, \
323 { "cpp_cpu_default", CPP_CPU_DEFAULT_SPEC }, \
324 { "cpp_cpu", CPP_CPU_SPEC }, \
325 { "cpp_subtarget", CPP_SUBTARGET_SPEC }, \
326 SUBTARGET_EXTRA_SPECS
329 /* Sometimes certain combinations of command options do not make sense
330 on a particular target machine. You can define a macro
331 `OVERRIDE_OPTIONS' to take account of this. This macro, if
332 defined, is executed once just after all the command options have
335 On the Alpha, it is used to translate target-option strings into
338 extern void override_options ();
339 #define OVERRIDE_OPTIONS override_options ()
342 /* Define this macro to change register usage conditional on target flags.
344 On the Alpha, we use this to disable the floating-point registers when
347 #define CONDITIONAL_REGISTER_USAGE \
348 if (! TARGET_FPREGS) \
349 for (i = 32; i < 63; i++) \
350 fixed_regs[i] = call_used_regs[i] = 1;
352 /* Show we can debug even without a frame pointer. */
353 #define CAN_DEBUG_WITHOUT_FP
355 /* target machine storage layout */
357 /* Define to enable software floating point emulation. */
358 #define REAL_ARITHMETIC
360 /* The following #defines are used when compiling the routines in
361 libgcc1.c. Since the Alpha calling conventions require single
362 precision floats to be passed in the floating-point registers
363 (rather than in the general registers) we have to build the
364 libgcc1.c routines in such a way that they know the actual types
365 of their formal arguments and the actual types of their return
366 values. Otherwise, gcc will generate calls to the libgcc1.c
367 routines, passing arguments in the floating-point registers,
368 but the libgcc1.c routines will expect their arguments on the
369 stack (where the Alpha calling conventions require structs &
370 unions to be passed). */
372 #define FLOAT_VALUE_TYPE double
373 #define INTIFY(FLOATVAL) (FLOATVAL)
374 #define FLOATIFY(INTVAL) (INTVAL)
375 #define FLOAT_ARG_TYPE double
377 /* Define the size of `int'. The default is the same as the word size. */
378 #define INT_TYPE_SIZE 32
380 /* Define the size of `long long'. The default is the twice the word size. */
381 #define LONG_LONG_TYPE_SIZE 64
383 /* The two floating-point formats we support are S-floating, which is
384 4 bytes, and T-floating, which is 8 bytes. `float' is S and `double'
385 and `long double' are T. */
387 #define FLOAT_TYPE_SIZE 32
388 #define DOUBLE_TYPE_SIZE 64
389 #define LONG_DOUBLE_TYPE_SIZE 64
391 #define WCHAR_TYPE "unsigned int"
392 #define WCHAR_TYPE_SIZE 32
394 /* Define this macro if it is advisable to hold scalars in registers
395 in a wider mode than that declared by the program. In such cases,
396 the value is constrained to be within the bounds of the declared
397 type, but kept valid in the wider mode. The signedness of the
398 extension may differ from that of the type.
400 For Alpha, we always store objects in a full register. 32-bit objects
401 are always sign-extended, but smaller objects retain their signedness. */
403 #define PROMOTE_MODE(MODE,UNSIGNEDP,TYPE) \
404 if (GET_MODE_CLASS (MODE) == MODE_INT \
405 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \
407 if ((MODE) == SImode) \
412 /* Define this if function arguments should also be promoted using the above
415 #define PROMOTE_FUNCTION_ARGS
417 /* Likewise, if the function return value is promoted. */
419 #define PROMOTE_FUNCTION_RETURN
421 /* Define this if most significant bit is lowest numbered
422 in instructions that operate on numbered bit-fields.
424 There are no such instructions on the Alpha, but the documentation
426 #define BITS_BIG_ENDIAN 0
428 /* Define this if most significant byte of a word is the lowest numbered.
429 This is false on the Alpha. */
430 #define BYTES_BIG_ENDIAN 0
432 /* Define this if most significant word of a multiword number is lowest
435 For Alpha we can decide arbitrarily since there are no machine instructions
436 for them. Might as well be consistent with bytes. */
437 #define WORDS_BIG_ENDIAN 0
439 /* number of bits in an addressable storage unit */
440 #define BITS_PER_UNIT 8
442 /* Width in bits of a "word", which is the contents of a machine register.
443 Note that this is not necessarily the width of data type `int';
444 if using 16-bit ints on a 68000, this would still be 32.
445 But on a machine with 16-bit registers, this would be 16. */
446 #define BITS_PER_WORD 64
448 /* Width of a word, in units (bytes). */
449 #define UNITS_PER_WORD 8
451 /* Width in bits of a pointer.
452 See also the macro `Pmode' defined below. */
453 #define POINTER_SIZE 64
455 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
456 #define PARM_BOUNDARY 64
458 /* Boundary (in *bits*) on which stack pointer should be aligned. */
459 #define STACK_BOUNDARY 64
461 /* Allocation boundary (in *bits*) for the code of a function. */
462 #define FUNCTION_BOUNDARY 256
464 /* Alignment of field after `int : 0' in a structure. */
465 #define EMPTY_FIELD_BOUNDARY 64
467 /* Every structure's size must be a multiple of this. */
468 #define STRUCTURE_SIZE_BOUNDARY 8
470 /* A bitfield declared as `int' forces `int' alignment for the struct. */
471 #define PCC_BITFIELD_TYPE_MATTERS 1
473 /* Align loop starts for optimal branching.
475 ??? Kludge this and the next macro for the moment by not doing anything if
476 we don't optimize and also if we are writing ECOFF symbols to work around
477 a bug in DEC's assembler. */
479 #define LOOP_ALIGN(LABEL) \
480 (optimize > 0 && write_symbols != SDB_DEBUG ? 4 : 0)
482 /* This is how to align an instruction for optimal branching. On
483 Alpha we'll get better performance by aligning on an octaword
486 #define ALIGN_LABEL_AFTER_BARRIER(FILE) \
487 (optimize > 0 && write_symbols != SDB_DEBUG ? 4 : 0)
489 /* No data type wants to be aligned rounder than this. */
490 #define BIGGEST_ALIGNMENT 64
492 /* For atomic access to objects, must have at least 32-bit alignment
493 unless the machine has byte operations. */
494 #define MINIMUM_ATOMIC_ALIGNMENT (TARGET_BWX ? 8 : 32)
496 /* Align all constants and variables to at least a word boundary so
497 we can pick up pieces of them faster. */
498 /* ??? Only if block-move stuff knows about different source/destination
501 #define CONSTANT_ALIGNMENT(EXP, ALIGN) MAX ((ALIGN), BITS_PER_WORD)
502 #define DATA_ALIGNMENT(EXP, ALIGN) MAX ((ALIGN), BITS_PER_WORD)
505 /* Set this non-zero if move instructions will actually fail to work
506 when given unaligned data.
508 Since we get an error message when we do one, call them invalid. */
510 #define STRICT_ALIGNMENT 1
512 /* Set this non-zero if unaligned move instructions are extremely slow.
514 On the Alpha, they trap. */
516 #define SLOW_UNALIGNED_ACCESS 1
518 /* Standard register usage. */
520 /* Number of actual hardware registers.
521 The hardware registers are assigned numbers for the compiler
522 from 0 to just below FIRST_PSEUDO_REGISTER.
523 All registers that the compiler knows about must be given numbers,
524 even those that are not normally considered general registers.
526 We define all 32 integer registers, even though $31 is always zero,
527 and all 32 floating-point registers, even though $f31 is also
528 always zero. We do not bother defining the FP status register and
529 there are no other registers.
531 Since $31 is always zero, we will use register number 31 as the
532 argument pointer. It will never appear in the generated code
533 because we will always be eliminating it in favor of the stack
534 pointer or hardware frame pointer.
536 Likewise, we use $f31 for the frame pointer, which will always
537 be eliminated in favor of the hardware frame pointer or the
540 #define FIRST_PSEUDO_REGISTER 64
542 /* 1 for registers that have pervasive standard uses
543 and are not available for the register allocator. */
545 #define FIXED_REGISTERS \
546 {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
547 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, \
548 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
549 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1 }
551 /* 1 for registers not available across function calls.
552 These must include the FIXED_REGISTERS and also any
553 registers that can be used without being saved.
554 The latter must include the registers where values are returned
555 and the register where structure-value addresses are passed.
556 Aside from that, you can include as many other registers as you like. */
557 #define CALL_USED_REGISTERS \
558 {1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, \
559 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, \
560 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, \
561 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 }
563 /* List the order in which to allocate registers. Each register must be
564 listed once, even those in FIXED_REGISTERS.
566 We allocate in the following order:
567 $f10-$f15 (nonsaved floating-point register)
569 $f21-$f16 (likewise, but input args)
570 $f0 (nonsaved, but return value)
571 $f1 (nonsaved, but immediate before saved)
572 $f2-$f9 (saved floating-point registers)
573 $1-$8 (nonsaved integer registers)
576 $0 (likewise, but return value)
577 $21-$16 (likewise, but input args)
578 $27 (procedure value in OSF, nonsaved in NT)
579 $9-$14 (saved integer registers)
583 $30, $31, $f31 (stack pointer and always zero/ap & fp) */
585 #define REG_ALLOC_ORDER \
586 {42, 43, 44, 45, 46, 47, \
587 54, 55, 56, 57, 58, 59, 60, 61, 62, \
588 53, 52, 51, 50, 49, 48, \
590 34, 35, 36, 37, 38, 39, 40, 41, \
591 1, 2, 3, 4, 5, 6, 7, 8, \
595 21, 20, 19, 18, 17, 16, \
597 9, 10, 11, 12, 13, 14, \
603 /* Return number of consecutive hard regs needed starting at reg REGNO
604 to hold something of mode MODE.
605 This is ordinarily the length in words of a value of mode MODE
606 but can be less for certain modes in special long registers. */
608 #define HARD_REGNO_NREGS(REGNO, MODE) \
609 ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
611 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
612 On Alpha, the integer registers can hold any mode. The floating-point
613 registers can hold 32-bit and 64-bit integers as well, but not 16-bit
614 or 8-bit values. If we only allowed the larger integers into FP registers,
615 we'd have to say that QImode and SImode aren't tiable, which is a
616 pain. So say all registers can hold everything and see how that works. */
618 #define HARD_REGNO_MODE_OK(REGNO, MODE) 1
620 /* Value is 1 if it is a good idea to tie two pseudo registers
621 when one has mode MODE1 and one has mode MODE2.
622 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
623 for any hard reg, then this must be 0 for correct output. */
625 #define MODES_TIEABLE_P(MODE1, MODE2) 1
627 /* Specify the registers used for certain standard purposes.
628 The values of these macros are register numbers. */
630 /* Alpha pc isn't overloaded on a register that the compiler knows about. */
631 /* #define PC_REGNUM */
633 /* Register to use for pushing function arguments. */
634 #define STACK_POINTER_REGNUM 30
636 /* Base register for access to local variables of the function. */
637 #define HARD_FRAME_POINTER_REGNUM 15
639 /* Value should be nonzero if functions must have frame pointers.
640 Zero means the frame pointer need not be set up (and parms
641 may be accessed via the stack pointer) in functions that seem suitable.
642 This is computed in `reload', in reload1.c. */
643 #define FRAME_POINTER_REQUIRED 0
645 /* Base register for access to arguments of the function. */
646 #define ARG_POINTER_REGNUM 31
648 /* Base register for access to local variables of function. */
649 #define FRAME_POINTER_REGNUM 63
651 /* Register in which static-chain is passed to a function.
653 For the Alpha, this is based on an example; the calling sequence
654 doesn't seem to specify this. */
655 #define STATIC_CHAIN_REGNUM 1
657 /* Register in which address to store a structure value
658 arrives in the function. On the Alpha, the address is passed
659 as a hidden argument. */
660 #define STRUCT_VALUE 0
662 /* Define the classes of registers for register constraints in the
663 machine description. Also define ranges of constants.
665 One of the classes must always be named ALL_REGS and include all hard regs.
666 If there is more than one class, another class must be named NO_REGS
667 and contain no registers.
669 The name GENERAL_REGS must be the name of a class (or an alias for
670 another name such as ALL_REGS). This is the class of registers
671 that is allowed by "g" or "r" in a register constraint.
672 Also, registers outside this class are allocated only when
673 instructions express preferences for them.
675 The classes must be numbered in nondecreasing order; that is,
676 a larger-numbered class must never be contained completely
677 in a smaller-numbered class.
679 For any two classes, it is very desirable that there be another
680 class that represents their union. */
682 enum reg_class { NO_REGS, GENERAL_REGS, FLOAT_REGS, ALL_REGS,
685 #define N_REG_CLASSES (int) LIM_REG_CLASSES
687 /* Give names of register classes as strings for dump file. */
689 #define REG_CLASS_NAMES \
690 {"NO_REGS", "GENERAL_REGS", "FLOAT_REGS", "ALL_REGS" }
692 /* Define which registers fit in which classes.
693 This is an initializer for a vector of HARD_REG_SET
694 of length N_REG_CLASSES. */
696 #define REG_CLASS_CONTENTS \
697 { {0, 0}, {~0, 0x80000000}, {0, 0x7fffffff}, {~0, ~0} }
699 /* The same information, inverted:
700 Return the class number of the smallest class containing
701 reg number REGNO. This could be a conditional expression
702 or could index an array. */
704 #define REGNO_REG_CLASS(REGNO) \
705 ((REGNO) >= 32 && (REGNO) <= 62 ? FLOAT_REGS : GENERAL_REGS)
707 /* The class value for index registers, and the one for base regs. */
708 #define INDEX_REG_CLASS NO_REGS
709 #define BASE_REG_CLASS GENERAL_REGS
711 /* Get reg_class from a letter such as appears in the machine description. */
713 #define REG_CLASS_FROM_LETTER(C) \
714 ((C) == 'f' ? FLOAT_REGS : NO_REGS)
716 /* Define this macro to change register usage conditional on target flags. */
717 /* #define CONDITIONAL_REGISTER_USAGE */
719 /* The letters I, J, K, L, M, N, O, and P in a register constraint string
720 can be used to stand for particular ranges of immediate operands.
721 This macro defines what the ranges are.
722 C is the letter, and VALUE is a constant value.
723 Return 1 if VALUE is in the range specified by C.
726 `I' is used for the range of constants most insns can contain.
727 `J' is the constant zero.
728 `K' is used for the constant in an LDA insn.
729 `L' is used for the constant in a LDAH insn.
730 `M' is used for the constants that can be AND'ed with using a ZAP insn.
731 `N' is used for complemented 8-bit constants.
732 `O' is used for negated 8-bit constants.
733 `P' is used for the constants 1, 2 and 3. */
735 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
736 ((C) == 'I' ? (unsigned HOST_WIDE_INT) (VALUE) < 0x100 \
737 : (C) == 'J' ? (VALUE) == 0 \
738 : (C) == 'K' ? (unsigned HOST_WIDE_INT) ((VALUE) + 0x8000) < 0x10000 \
739 : (C) == 'L' ? (((VALUE) & 0xffff) == 0 \
740 && (((VALUE)) >> 31 == -1 || (VALUE) >> 31 == 0)) \
741 : (C) == 'M' ? zap_mask (VALUE) \
742 : (C) == 'N' ? (unsigned HOST_WIDE_INT) (~ (VALUE)) < 0x100 \
743 : (C) == 'O' ? (unsigned HOST_WIDE_INT) (- (VALUE)) < 0x100 \
744 : (C) == 'P' ? (VALUE) == 1 || (VALUE) == 2 || (VALUE) == 3 \
747 /* Similar, but for floating or large integer constants, and defining letters
748 G and H. Here VALUE is the CONST_DOUBLE rtx itself.
750 For Alpha, `G' is the floating-point constant zero. `H' is a CONST_DOUBLE
751 that is the operand of a ZAP insn. */
753 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
754 ((C) == 'G' ? (GET_MODE_CLASS (GET_MODE (VALUE)) == MODE_FLOAT \
755 && (VALUE) == CONST0_RTX (GET_MODE (VALUE))) \
756 : (C) == 'H' ? (GET_MODE (VALUE) == VOIDmode \
757 && zap_mask (CONST_DOUBLE_LOW (VALUE)) \
758 && zap_mask (CONST_DOUBLE_HIGH (VALUE))) \
761 /* Optional extra constraints for this machine.
763 For the Alpha, `Q' means that this is a memory operand but not a
764 reference to an unaligned location.
766 `R' is a SYMBOL_REF that has SYMBOL_REF_FLAG set or is the current
769 'S' is a 6-bit constant (valid for a shift insn). */
771 #define EXTRA_CONSTRAINT(OP, C) \
772 ((C) == 'Q' ? GET_CODE (OP) == MEM && GET_CODE (XEXP (OP, 0)) != AND \
773 : (C) == 'R' ? current_file_function_operand (OP, Pmode) \
774 : (C) == 'S' ? (GET_CODE (OP) == CONST_INT \
775 && (unsigned HOST_WIDE_INT) INTVAL (OP) < 64) \
778 /* Given an rtx X being reloaded into a reg required to be
779 in class CLASS, return the class of reg to actually use.
780 In general this is just CLASS; but on some machines
781 in some cases it is preferable to use a more restrictive class.
783 On the Alpha, all constants except zero go into a floating-point
784 register via memory. */
786 #define PREFERRED_RELOAD_CLASS(X, CLASS) \
787 (CONSTANT_P (X) && (X) != const0_rtx && (X) != CONST0_RTX (GET_MODE (X)) \
788 ? ((CLASS) == FLOAT_REGS || (CLASS) == NO_REGS ? NO_REGS : GENERAL_REGS)\
791 /* Loading and storing HImode or QImode values to and from memory
792 usually requires a scratch register. The exceptions are loading
793 QImode and HImode from an aligned address to a general register
794 unless byte instructions are permitted.
795 We also cannot load an unaligned address or a paradoxical SUBREG into an
798 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS,MODE,IN) \
799 (((GET_CODE (IN) == MEM \
800 || (GET_CODE (IN) == REG && REGNO (IN) >= FIRST_PSEUDO_REGISTER) \
801 || (GET_CODE (IN) == SUBREG \
802 && (GET_CODE (SUBREG_REG (IN)) == MEM \
803 || (GET_CODE (SUBREG_REG (IN)) == REG \
804 && REGNO (SUBREG_REG (IN)) >= FIRST_PSEUDO_REGISTER)))) \
805 && (((CLASS) == FLOAT_REGS \
806 && ((MODE) == SImode || (MODE) == HImode || (MODE) == QImode)) \
807 || (((MODE) == QImode || (MODE) == HImode) \
808 && ! TARGET_BWX && unaligned_memory_operand (IN, MODE)))) \
810 : ((CLASS) == FLOAT_REGS && GET_CODE (IN) == MEM \
811 && GET_CODE (XEXP (IN, 0)) == AND) ? GENERAL_REGS \
812 : ((CLASS) == FLOAT_REGS && GET_CODE (IN) == SUBREG \
813 && (GET_MODE_SIZE (GET_MODE (IN)) \
814 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (IN))))) ? GENERAL_REGS \
817 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS,MODE,OUT) \
818 (((GET_CODE (OUT) == MEM \
819 || (GET_CODE (OUT) == REG && REGNO (OUT) >= FIRST_PSEUDO_REGISTER) \
820 || (GET_CODE (OUT) == SUBREG \
821 && (GET_CODE (SUBREG_REG (OUT)) == MEM \
822 || (GET_CODE (SUBREG_REG (OUT)) == REG \
823 && REGNO (SUBREG_REG (OUT)) >= FIRST_PSEUDO_REGISTER)))) \
824 && ((((MODE) == HImode || (MODE) == QImode) \
825 && (! TARGET_BWX || (CLASS) == FLOAT_REGS)) \
826 || ((MODE) == SImode && (CLASS) == FLOAT_REGS))) \
828 : ((CLASS) == FLOAT_REGS && GET_CODE (OUT) == MEM \
829 && GET_CODE (XEXP (OUT, 0)) == AND) ? GENERAL_REGS \
830 : ((CLASS) == FLOAT_REGS && GET_CODE (OUT) == SUBREG \
831 && (GET_MODE_SIZE (GET_MODE (OUT)) \
832 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (OUT))))) ? GENERAL_REGS \
835 /* If we are copying between general and FP registers, we need a memory
836 location unless the CIX extension is available. */
838 #define SECONDARY_MEMORY_NEEDED(CLASS1,CLASS2,MODE) \
839 (! TARGET_CIX && (CLASS1) != (CLASS2))
841 /* Specify the mode to be used for memory when a secondary memory
842 location is needed. If MODE is floating-point, use it. Otherwise,
843 widen to a word like the default. This is needed because we always
844 store integers in FP registers in quadword format. This whole
845 area is very tricky! */
846 #define SECONDARY_MEMORY_NEEDED_MODE(MODE) \
847 (GET_MODE_CLASS (MODE) == MODE_FLOAT ? (MODE) \
848 : GET_MODE_SIZE (MODE) >= 4 ? (MODE) \
849 : mode_for_size (BITS_PER_WORD, GET_MODE_CLASS (MODE), 0))
851 /* Return the maximum number of consecutive registers
852 needed to represent mode MODE in a register of class CLASS. */
854 #define CLASS_MAX_NREGS(CLASS, MODE) \
855 ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
857 /* If defined, gives a class of registers that cannot be used as the
858 operand of a SUBREG that changes the size of the object. */
860 #define CLASS_CANNOT_CHANGE_SIZE FLOAT_REGS
862 /* Define the cost of moving between registers of various classes. Moving
863 between FLOAT_REGS and anything else except float regs is expensive.
864 In fact, we make it quite expensive because we really don't want to
865 do these moves unless it is clearly worth it. Optimizations may
866 reduce the impact of not being able to allocate a pseudo to a
869 #define REGISTER_MOVE_COST(CLASS1, CLASS2) \
870 (((CLASS1) == FLOAT_REGS) == ((CLASS2) == FLOAT_REGS) \
872 : TARGET_CIX ? 3 : 4+2*alpha_memory_latency)
874 /* A C expressions returning the cost of moving data of MODE from a register to
877 On the Alpha, bump this up a bit. */
879 extern int alpha_memory_latency;
880 #define MEMORY_MOVE_COST(MODE,CLASS,IN) (2*alpha_memory_latency)
882 /* Provide the cost of a branch. Exact meaning under development. */
883 #define BRANCH_COST 5
885 /* Adjust the cost of dependencies. */
887 #define ADJUST_COST(INSN,LINK,DEP,COST) \
888 (COST) = alpha_adjust_cost (INSN, LINK, DEP, COST)
890 /* Stack layout; function entry, exit and calling. */
892 /* Define this if pushing a word on the stack
893 makes the stack pointer a smaller address. */
894 #define STACK_GROWS_DOWNWARD
896 /* Define this if the nominal address of the stack frame
897 is at the high-address end of the local variables;
898 that is, each additional local variable allocated
899 goes at a more negative offset in the frame. */
900 /* #define FRAME_GROWS_DOWNWARD */
902 /* Offset within stack frame to start allocating local variables at.
903 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
904 first local allocated. Otherwise, it is the offset to the BEGINNING
905 of the first local allocated. */
907 #define STARTING_FRAME_OFFSET 0
909 /* If we generate an insn to push BYTES bytes,
910 this says how many the stack pointer really advances by.
911 On Alpha, don't define this because there are no push insns. */
912 /* #define PUSH_ROUNDING(BYTES) */
914 /* Define this to be nonzero if stack checking is built into the ABI. */
915 #define STACK_CHECK_BUILTIN 1
917 /* Define this if the maximum size of all the outgoing args is to be
918 accumulated and pushed during the prologue. The amount can be
919 found in the variable current_function_outgoing_args_size. */
920 #define ACCUMULATE_OUTGOING_ARGS
922 /* Offset of first parameter from the argument pointer register value. */
924 #define FIRST_PARM_OFFSET(FNDECL) 0
926 /* Definitions for register eliminations.
928 We have two registers that can be eliminated on the Alpha. First, the
929 frame pointer register can often be eliminated in favor of the stack
930 pointer register. Secondly, the argument pointer register can always be
931 eliminated; it is replaced with either the stack or frame pointer. */
933 /* This is an array of structures. Each structure initializes one pair
934 of eliminable registers. The "from" register number is given first,
935 followed by "to". Eliminations of the same "from" register are listed
936 in order of preference. */
938 #define ELIMINABLE_REGS \
939 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
940 { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \
941 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
942 { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}}
944 /* Given FROM and TO register numbers, say whether this elimination is allowed.
945 Frame pointer elimination is automatically handled.
947 All eliminations are valid since the cases where FP can't be
948 eliminated are already handled. */
950 #define CAN_ELIMINATE(FROM, TO) 1
952 /* Round up to a multiple of 16 bytes. */
953 #define ALPHA_ROUND(X) (((X) + 15) & ~ 15)
955 /* Define the offset between two registers, one to be eliminated, and the other
956 its replacement, at the start of a routine. */
957 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
958 { if ((FROM) == FRAME_POINTER_REGNUM) \
959 (OFFSET) = (ALPHA_ROUND (current_function_outgoing_args_size) \
960 + alpha_sa_size ()); \
961 else if ((FROM) == ARG_POINTER_REGNUM) \
962 (OFFSET) = (ALPHA_ROUND (current_function_outgoing_args_size) \
964 + (ALPHA_ROUND (get_frame_size () \
965 + current_function_pretend_args_size) \
966 - current_function_pretend_args_size)); \
969 /* Define this if stack space is still allocated for a parameter passed
971 /* #define REG_PARM_STACK_SPACE */
973 /* Value is the number of bytes of arguments automatically
974 popped when returning from a subroutine call.
975 FUNDECL is the declaration node of the function (as a tree),
976 FUNTYPE is the data type of the function (as a tree),
977 or for a library call it is an identifier node for the subroutine name.
978 SIZE is the number of bytes of arguments passed on the stack. */
980 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0
982 /* Define how to find the value returned by a function.
983 VALTYPE is the data type of the value (as a tree).
984 If the precise function being called is known, FUNC is its FUNCTION_DECL;
985 otherwise, FUNC is 0.
987 On Alpha the value is found in $0 for integer functions and
988 $f0 for floating-point functions. */
990 #define FUNCTION_VALUE(VALTYPE, FUNC) \
992 ((INTEGRAL_TYPE_P (VALTYPE) \
993 && TYPE_PRECISION (VALTYPE) < BITS_PER_WORD) \
994 || POINTER_TYPE_P (VALTYPE)) \
995 ? word_mode : TYPE_MODE (VALTYPE), \
997 && (TREE_CODE (VALTYPE) == REAL_TYPE \
998 || TREE_CODE (VALTYPE) == COMPLEX_TYPE)) \
1001 /* Define how to find the value returned by a library function
1002 assuming the value has mode MODE. */
1004 #define LIBCALL_VALUE(MODE) \
1005 gen_rtx (REG, MODE, \
1007 && (GET_MODE_CLASS (MODE) == MODE_FLOAT \
1008 || GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT) \
1011 /* The definition of this macro implies that there are cases where
1012 a scalar value cannot be returned in registers.
1014 For the Alpha, any structure or union type is returned in memory, as
1015 are integers whose size is larger than 64 bits. */
1017 #define RETURN_IN_MEMORY(TYPE) \
1018 (TYPE_MODE (TYPE) == BLKmode \
1019 || (TREE_CODE (TYPE) == INTEGER_TYPE && TYPE_PRECISION (TYPE) > 64))
1021 /* 1 if N is a possible register number for a function value
1022 as seen by the caller. */
1024 #define FUNCTION_VALUE_REGNO_P(N) \
1025 ((N) == 0 || (N) == 1 || (N) == 32 || (N) == 33)
1027 /* 1 if N is a possible register number for function argument passing.
1028 On Alpha, these are $16-$21 and $f16-$f21. */
1030 #define FUNCTION_ARG_REGNO_P(N) \
1031 (((N) >= 16 && (N) <= 21) || ((N) >= 16 + 32 && (N) <= 21 + 32))
1033 /* Define a data type for recording info about an argument list
1034 during the scan of that argument list. This data type should
1035 hold all necessary information about the function itself
1036 and about the args processed so far, enough to enable macros
1037 such as FUNCTION_ARG to determine where the next arg should go.
1039 On Alpha, this is a single integer, which is a number of words
1040 of arguments scanned so far.
1041 Thus 6 or more means all following args should go on the stack. */
1043 #define CUMULATIVE_ARGS int
1045 /* Initialize a variable CUM of type CUMULATIVE_ARGS
1046 for a call to a function whose data type is FNTYPE.
1047 For a library call, FNTYPE is 0. */
1049 #define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME,INDIRECT) (CUM) = 0
1051 /* Define intermediate macro to compute the size (in registers) of an argument
1054 #define ALPHA_ARG_SIZE(MODE, TYPE, NAMED) \
1055 ((MODE) != BLKmode \
1056 ? (GET_MODE_SIZE (MODE) + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD \
1057 : (int_size_in_bytes (TYPE) + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
1059 /* Update the data in CUM to advance over an argument
1060 of mode MODE and data type TYPE.
1061 (TYPE is null for libcalls where that information may not be available.) */
1063 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
1064 if (MUST_PASS_IN_STACK (MODE, TYPE)) \
1067 (CUM) += ALPHA_ARG_SIZE (MODE, TYPE, NAMED)
1069 /* Determine where to put an argument to a function.
1070 Value is zero to push the argument on the stack,
1071 or a hard register in which to store the argument.
1073 MODE is the argument's machine mode.
1074 TYPE is the data type of the argument (as a tree).
1075 This is null for libcalls where that information may
1077 CUM is a variable of type CUMULATIVE_ARGS which gives info about
1078 the preceding args and about the function being called.
1079 NAMED is nonzero if this argument is a named parameter
1080 (otherwise it is an extra parameter matching an ellipsis).
1082 On Alpha the first 6 words of args are normally in registers
1083 and the rest are pushed. */
1085 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
1086 ((CUM) < 6 && ! MUST_PASS_IN_STACK (MODE, TYPE) \
1087 ? gen_rtx(REG, (MODE), \
1088 (CUM) + 16 + ((TARGET_FPREGS \
1089 && (GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT \
1090 || GET_MODE_CLASS (MODE) == MODE_FLOAT)) \
1094 /* Specify the padding direction of arguments.
1096 On the Alpha, we must pad upwards in order to be able to pass args in
1099 #define FUNCTION_ARG_PADDING(MODE, TYPE) upward
1101 /* For an arg passed partly in registers and partly in memory,
1102 this is the number of registers used.
1103 For args passed entirely in registers or entirely in memory, zero. */
1105 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
1106 ((CUM) < 6 && 6 < (CUM) + ALPHA_ARG_SIZE (MODE, TYPE, NAMED) \
1109 /* Perform any needed actions needed for a function that is receiving a
1110 variable number of arguments.
1114 MODE and TYPE are the mode and type of the current parameter.
1116 PRETEND_SIZE is a variable that should be set to the amount of stack
1117 that must be pushed by the prolog to pretend that our caller pushed
1120 Normally, this macro will push all remaining incoming registers on the
1121 stack and set PRETEND_SIZE to the length of the registers pushed.
1123 On the Alpha, we allocate space for all 12 arg registers, but only
1124 push those that are remaining.
1126 However, if NO registers need to be saved, don't allocate any space.
1127 This is not only because we won't need the space, but because AP includes
1128 the current_pretend_args_size and we don't want to mess up any
1129 ap-relative addresses already made.
1131 If we are not to use the floating-point registers, save the integer
1132 registers where we would put the floating-point registers. This is
1133 not the most efficient way to implement varargs with just one register
1134 class, but it isn't worth doing anything more efficient in this rare
1138 #define SETUP_INCOMING_VARARGS(CUM,MODE,TYPE,PRETEND_SIZE,NO_RTL) \
1143 move_block_from_reg \
1145 gen_rtx (MEM, BLKmode, \
1146 plus_constant (virtual_incoming_args_rtx, \
1147 ((CUM) + 6)* UNITS_PER_WORD)), \
1148 6 - (CUM), (6 - (CUM)) * UNITS_PER_WORD); \
1149 move_block_from_reg \
1150 (16 + (TARGET_FPREGS ? 32 : 0) + CUM, \
1151 gen_rtx (MEM, BLKmode, \
1152 plus_constant (virtual_incoming_args_rtx, \
1153 (CUM) * UNITS_PER_WORD)), \
1154 6 - (CUM), (6 - (CUM)) * UNITS_PER_WORD); \
1155 emit_insn (gen_blockage ()); \
1157 PRETEND_SIZE = 12 * UNITS_PER_WORD; \
1161 /* Try to output insns to set TARGET equal to the constant C if it can be
1162 done in less than N insns. Do all computations in MODE. Returns the place
1163 where the output has been placed if it can be done and the insns have been
1164 emitted. If it would take more than N insns, zero is returned and no
1165 insns and emitted. */
1166 extern struct rtx_def *alpha_emit_set_const ();
1167 extern struct rtx_def *alpha_emit_set_long_const ();
1168 extern struct rtx_def *alpha_emit_conditional_branch ();
1169 extern struct rtx_def *alpha_emit_conditional_move ();
1171 /* Generate necessary RTL for __builtin_saveregs().
1172 ARGLIST is the argument list; see expr.c. */
1173 extern struct rtx_def *alpha_builtin_saveregs ();
1174 #define EXPAND_BUILTIN_SAVEREGS(ARGLIST) alpha_builtin_saveregs (ARGLIST)
1176 /* Define the information needed to generate branch and scc insns. This is
1177 stored from the compare operation. Note that we can't use "rtx" here
1178 since it hasn't been defined! */
1180 extern struct rtx_def *alpha_compare_op0, *alpha_compare_op1;
1181 extern int alpha_compare_fp_p;
1183 /* Make (or fake) .linkage entry for function call.
1184 IS_LOCAL is 0 if name is used in call, 1 if name is used in definition. */
1185 extern void alpha_need_linkage ();
1187 /* This macro defines the start of an assembly comment. */
1189 #define ASM_COMMENT_START " #"
1191 /* This macro produces the initial definition of a function. */
1193 #define ASM_DECLARE_FUNCTION_NAME(FILE,NAME,DECL) \
1194 alpha_start_function(FILE,NAME,DECL);
1195 extern void alpha_start_function ();
1197 /* This macro closes up a function definition for the assembler. */
1199 #define ASM_DECLARE_FUNCTION_SIZE(FILE,NAME,DECL) \
1200 alpha_end_function(FILE,NAME,DECL)
1201 extern void alpha_end_function ();
1203 /* This macro notes the end of the prologue. */
1205 #define FUNCTION_END_PROLOGUE(FILE) output_end_prologue (FILE)
1206 extern void output_end_prologue ();
1208 /* Output any profiling code before the prologue. */
1210 #define PROFILE_BEFORE_PROLOGUE 1
1212 /* Output assembler code to FILE to increment profiler label # LABELNO
1213 for profiling a function entry. Under OSF/1, profiling is enabled
1214 by simply passing -pg to the assembler and linker. */
1216 #define FUNCTION_PROFILER(FILE, LABELNO)
1218 /* Output assembler code to FILE to initialize this source file's
1219 basic block profiling info, if that has not already been done.
1220 This assumes that __bb_init_func doesn't garble a1-a5. */
1222 #define FUNCTION_BLOCK_PROFILER(FILE, LABELNO) \
1224 ASM_OUTPUT_REG_PUSH (FILE, 16); \
1225 fputs ("\tlda $16,$PBX32\n", (FILE)); \
1226 fputs ("\tldq $26,0($16)\n", (FILE)); \
1227 fputs ("\tbne $26,1f\n", (FILE)); \
1228 fputs ("\tlda $27,__bb_init_func\n", (FILE)); \
1229 fputs ("\tjsr $26,($27),__bb_init_func\n", (FILE)); \
1230 fputs ("\tldgp $29,0($26)\n", (FILE)); \
1231 fputs ("1:\n", (FILE)); \
1232 ASM_OUTPUT_REG_POP (FILE, 16); \
1235 /* Output assembler code to FILE to increment the entry-count for
1236 the BLOCKNO'th basic block in this source file. */
1238 #define BLOCK_PROFILER(FILE, BLOCKNO) \
1240 int blockn = (BLOCKNO); \
1241 fputs ("\tsubq $30,16,$30\n", (FILE)); \
1242 fputs ("\tstq $26,0($30)\n", (FILE)); \
1243 fputs ("\tstq $27,8($30)\n", (FILE)); \
1244 fputs ("\tlda $26,$PBX34\n", (FILE)); \
1245 fprintf ((FILE), "\tldq $27,%d($26)\n", 8*blockn); \
1246 fputs ("\taddq $27,1,$27\n", (FILE)); \
1247 fprintf ((FILE), "\tstq $27,%d($26)\n", 8*blockn); \
1248 fputs ("\tldq $26,0($30)\n", (FILE)); \
1249 fputs ("\tldq $27,8($30)\n", (FILE)); \
1250 fputs ("\taddq $30,16,$30\n", (FILE)); \
1254 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
1255 the stack pointer does not matter. The value is tested only in
1256 functions that have frame pointers.
1257 No definition is equivalent to always zero. */
1259 #define EXIT_IGNORE_STACK 1
1261 /* Output assembler code for a block containing the constant parts
1262 of a trampoline, leaving space for the variable parts.
1264 The trampoline should set the static chain pointer to value placed
1265 into the trampoline and should branch to the specified routine.
1266 Note that $27 has been set to the address of the trampoline, so we can
1267 use it for addressability of the two data items. Trampolines are always
1268 aligned to FUNCTION_BOUNDARY, which is 64 bits. */
1270 #define TRAMPOLINE_TEMPLATE(FILE) \
1272 fprintf (FILE, "\tldq $1,24($27)\n"); \
1273 fprintf (FILE, "\tldq $27,16($27)\n"); \
1274 fprintf (FILE, "\tjmp $31,($27),0\n"); \
1275 fprintf (FILE, "\tnop\n"); \
1276 fprintf (FILE, "\t.quad 0,0\n"); \
1279 /* Section in which to place the trampoline. On Alpha, instructions
1280 may only be placed in a text segment. */
1282 #define TRAMPOLINE_SECTION text_section
1284 /* Length in units of the trampoline for entering a nested function. */
1286 #define TRAMPOLINE_SIZE 32
1288 /* Emit RTL insns to initialize the variable parts of a trampoline.
1289 FNADDR is an RTX for the address of the function's pure code.
1290 CXT is an RTX for the static chain value for the function. */
1292 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
1293 alpha_initialize_trampoline (TRAMP, FNADDR, CXT, 16, 24, 8)
1295 /* A C expression whose value is RTL representing the value of the return
1296 address for the frame COUNT steps up from the current frame.
1297 FRAMEADDR is the frame pointer of the COUNT frame, or the frame pointer of
1298 the COUNT-1 frame if RETURN_ADDR_IN_PREVIOUS_FRAME is defined. */
1300 #define RETURN_ADDR_RTX alpha_return_addr
1301 extern struct rtx_def *alpha_return_addr ();
1303 /* Initialize data used by insn expanders. This is called from insn_emit,
1304 once for every function before code is generated. */
1306 #define INIT_EXPANDERS alpha_init_expanders ()
1307 extern void alpha_init_expanders ();
1309 /* Addressing modes, and classification of registers for them. */
1311 /* #define HAVE_POST_INCREMENT */
1312 /* #define HAVE_POST_DECREMENT */
1314 /* #define HAVE_PRE_DECREMENT */
1315 /* #define HAVE_PRE_INCREMENT */
1317 /* Macros to check register numbers against specific register classes. */
1319 /* These assume that REGNO is a hard or pseudo reg number.
1320 They give nonzero only if REGNO is a hard reg of the suitable class
1321 or a pseudo reg currently allocated to a suitable hard reg.
1322 Since they use reg_renumber, they are safe only once reg_renumber
1323 has been allocated, which happens in local-alloc.c. */
1325 #define REGNO_OK_FOR_INDEX_P(REGNO) 0
1326 #define REGNO_OK_FOR_BASE_P(REGNO) \
1327 ((REGNO) < 32 || (unsigned) reg_renumber[REGNO] < 32 \
1328 || (REGNO) == 63 || reg_renumber[REGNO] == 63)
1330 /* Maximum number of registers that can appear in a valid memory address. */
1331 #define MAX_REGS_PER_ADDRESS 1
1333 /* Recognize any constant value that is a valid address. For the Alpha,
1334 there are only constants none since we want to use LDA to load any
1335 symbolic addresses into registers. */
1337 #define CONSTANT_ADDRESS_P(X) \
1338 (GET_CODE (X) == CONST_INT \
1339 && (unsigned HOST_WIDE_INT) (INTVAL (X) + 0x8000) < 0x10000)
1341 /* Include all constant integers and constant doubles, but not
1342 floating-point, except for floating-point zero. */
1344 #define LEGITIMATE_CONSTANT_P(X) \
1345 (GET_MODE_CLASS (GET_MODE (X)) != MODE_FLOAT \
1346 || (X) == CONST0_RTX (GET_MODE (X)))
1348 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
1349 and check its validity for a certain class.
1350 We have two alternate definitions for each of them.
1351 The usual definition accepts all pseudo regs; the other rejects
1352 them unless they have been allocated suitable hard regs.
1353 The symbol REG_OK_STRICT causes the latter definition to be used.
1355 Most source files want to accept pseudo regs in the hope that
1356 they will get allocated to the class that the insn wants them to be in.
1357 Source files for reload pass need to be strict.
1358 After reload, it makes no difference, since pseudo regs have
1359 been eliminated by then. */
1361 #ifndef REG_OK_STRICT
1363 /* Nonzero if X is a hard reg that can be used as an index
1364 or if it is a pseudo reg. */
1365 #define REG_OK_FOR_INDEX_P(X) 0
1366 /* Nonzero if X is a hard reg that can be used as a base reg
1367 or if it is a pseudo reg. */
1368 #define REG_OK_FOR_BASE_P(X) \
1369 (REGNO (X) < 32 || REGNO (X) == 63 || REGNO (X) >= FIRST_PSEUDO_REGISTER)
1373 /* Nonzero if X is a hard reg that can be used as an index. */
1374 #define REG_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X))
1375 /* Nonzero if X is a hard reg that can be used as a base reg. */
1376 #define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X))
1380 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
1381 that is a valid memory address for an instruction.
1382 The MODE argument is the machine mode for the MEM expression
1383 that wants to use this address.
1385 For Alpha, we have either a constant address or the sum of a register
1386 and a constant address, or just a register. For DImode, any of those
1387 forms can be surrounded with an AND that clear the low-order three bits;
1388 this is an "unaligned" access.
1390 First define the basic valid address. */
1392 #define GO_IF_LEGITIMATE_SIMPLE_ADDRESS(MODE, X, ADDR) \
1393 { if (REG_P (X) && REG_OK_FOR_BASE_P (X)) \
1395 if (CONSTANT_ADDRESS_P (X)) \
1397 if (GET_CODE (X) == PLUS \
1398 && REG_P (XEXP (X, 0)) \
1399 && REG_OK_FOR_BASE_P (XEXP (X, 0)) \
1400 && CONSTANT_ADDRESS_P (XEXP (X, 1))) \
1404 /* Now accept the simple address, or, for DImode only, an AND of a simple
1405 address that turns off the low three bits. */
1407 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
1408 { GO_IF_LEGITIMATE_SIMPLE_ADDRESS (MODE, X, ADDR); \
1409 if ((MODE) == DImode \
1410 && GET_CODE (X) == AND \
1411 && GET_CODE (XEXP (X, 1)) == CONST_INT \
1412 && INTVAL (XEXP (X, 1)) == -8) \
1413 GO_IF_LEGITIMATE_SIMPLE_ADDRESS (MODE, XEXP (X, 0), ADDR); \
1416 /* Try machine-dependent ways of modifying an illegitimate address
1417 to be legitimate. If we find one, return the new, valid address.
1418 This macro is used in only one place: `memory_address' in explow.c.
1420 OLDX is the address as it was before break_out_memory_refs was called.
1421 In some cases it is useful to look at this to decide what needs to be done.
1423 MODE and WIN are passed so that this macro can use
1424 GO_IF_LEGITIMATE_ADDRESS.
1426 It is always safe for this macro to do nothing. It exists to recognize
1427 opportunities to optimize the output.
1429 For the Alpha, there are three cases we handle:
1431 (1) If the address is (plus reg const_int) and the CONST_INT is not a
1432 valid offset, compute the high part of the constant and add it to the
1433 register. Then our address is (plus temp low-part-const).
1434 (2) If the address is (const (plus FOO const_int)), find the low-order
1435 part of the CONST_INT. Then load FOO plus any high-order part of the
1436 CONST_INT into a register. Our address is (plus reg low-part-const).
1437 This is done to reduce the number of GOT entries.
1438 (3) If we have a (plus reg const), emit the load as in (2), then add
1439 the two registers, and finally generate (plus reg low-part-const) as
1442 #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \
1443 { if (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 0)) == REG \
1444 && GET_CODE (XEXP (X, 1)) == CONST_INT \
1445 && ! CONSTANT_ADDRESS_P (XEXP (X, 1))) \
1447 HOST_WIDE_INT val = INTVAL (XEXP (X, 1)); \
1448 HOST_WIDE_INT lowpart = (val & 0xffff) - 2 * (val & 0x8000); \
1449 HOST_WIDE_INT highpart = val - lowpart; \
1450 rtx high = GEN_INT (highpart); \
1451 rtx temp = expand_binop (Pmode, add_optab, XEXP (x, 0), \
1452 high, NULL_RTX, 1, OPTAB_LIB_WIDEN); \
1454 (X) = plus_constant (temp, lowpart); \
1457 else if (GET_CODE (X) == CONST \
1458 && GET_CODE (XEXP (X, 0)) == PLUS \
1459 && GET_CODE (XEXP (XEXP (X, 0), 1)) == CONST_INT) \
1461 HOST_WIDE_INT val = INTVAL (XEXP (XEXP (X, 0), 1)); \
1462 HOST_WIDE_INT lowpart = (val & 0xffff) - 2 * (val & 0x8000); \
1463 HOST_WIDE_INT highpart = val - lowpart; \
1464 rtx high = XEXP (XEXP (X, 0), 0); \
1467 high = plus_constant (high, highpart); \
1469 (X) = plus_constant (force_reg (Pmode, high), lowpart); \
1472 else if (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 0)) == REG \
1473 && GET_CODE (XEXP (X, 1)) == CONST \
1474 && GET_CODE (XEXP (XEXP (X, 1), 0)) == PLUS \
1475 && GET_CODE (XEXP (XEXP (XEXP (X, 1), 0), 1)) == CONST_INT) \
1477 HOST_WIDE_INT val = INTVAL (XEXP (XEXP (XEXP (X, 1), 0), 1)); \
1478 HOST_WIDE_INT lowpart = (val & 0xffff) - 2 * (val & 0x8000); \
1479 HOST_WIDE_INT highpart = val - lowpart; \
1480 rtx high = XEXP (XEXP (XEXP (X, 1), 0), 0); \
1483 high = plus_constant (high, highpart); \
1485 high = expand_binop (Pmode, add_optab, XEXP (X, 0), \
1486 force_reg (Pmode, high), \
1487 high, 1, OPTAB_LIB_WIDEN); \
1488 (X) = plus_constant (high, lowpart); \
1493 /* Try a machine-dependent way of reloading an illegitimate address
1494 operand. If we find one, push the reload and jump to WIN. This
1495 macro is used in only one place: `find_reloads_address' in reload.c.
1497 For the Alpha, we wish to handle large displacements off a base
1498 register by splitting the addend across an ldah and the mem insn.
1499 This cuts number of extra insns needed from 3 to 1. */
1501 #define LEGITIMIZE_RELOAD_ADDRESS(X,MODE,OPNUM,TYPE,IND_LEVELS,WIN) \
1503 if (GET_CODE (X) == PLUS \
1504 && GET_CODE (XEXP (X, 0)) == REG \
1505 && REGNO (XEXP (X, 0)) < FIRST_PSEUDO_REGISTER \
1506 && REG_MODE_OK_FOR_BASE_P (XEXP (X, 0), MODE) \
1507 && GET_CODE (XEXP (X, 1)) == CONST_INT) \
1509 HOST_WIDE_INT val = INTVAL (XEXP (X, 1)); \
1510 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000; \
1511 HOST_WIDE_INT high \
1512 = (((val - low) & 0xffffffff) ^ 0x80000000) - 0x80000000; \
1514 /* Check for 32-bit overflow. */ \
1515 if (high + low != val) \
1518 /* Reload the high part into a base reg; leave the low part \
1519 in the mem directly. */ \
1521 X = gen_rtx_PLUS (GET_MODE (X), \
1522 gen_rtx_PLUS (GET_MODE (X), XEXP (X, 0), \
1526 push_reload (XEXP (X, 0), NULL_RTX, &XEXP (X, 0), NULL_PTR, \
1527 BASE_REG_CLASS, GET_MODE (X), VOIDmode, 0, 0, \
1533 /* Go to LABEL if ADDR (a legitimate address expression)
1534 has an effect that depends on the machine mode it is used for.
1535 On the Alpha this is true only for the unaligned modes. We can
1536 simplify this test since we know that the address must be valid. */
1538 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) \
1539 { if (GET_CODE (ADDR) == AND) goto LABEL; }
1541 /* Compute the cost of an address. For the Alpha, all valid addresses are
1544 #define ADDRESS_COST(X) 0
1546 /* Machine-dependent reorg pass. */
1547 #define MACHINE_DEPENDENT_REORG(X) alpha_reorg(X)
1549 /* Specify the machine mode that this machine uses
1550 for the index in the tablejump instruction. */
1551 #define CASE_VECTOR_MODE SImode
1553 /* Define as C expression which evaluates to nonzero if the tablejump
1554 instruction expects the table to contain offsets from the address of the
1557 Do not define this if the table should contain absolute addresses.
1558 On the Alpha, the table is really GP-relative, not relative to the PC
1559 of the table, but we pretend that it is PC-relative; this should be OK,
1560 but we should try to find some better way sometime. */
1561 #define CASE_VECTOR_PC_RELATIVE 1
1563 /* Specify the tree operation to be used to convert reals to integers. */
1564 #define IMPLICIT_FIX_EXPR FIX_ROUND_EXPR
1566 /* This is the kind of divide that is easiest to do in the general case. */
1567 #define EASY_DIV_EXPR TRUNC_DIV_EXPR
1569 /* Define this as 1 if `char' should by default be signed; else as 0. */
1570 #define DEFAULT_SIGNED_CHAR 1
1572 /* This flag, if defined, says the same insns that convert to a signed fixnum
1573 also convert validly to an unsigned one.
1575 We actually lie a bit here as overflow conditions are different. But
1576 they aren't being checked anyway. */
1578 #define FIXUNS_TRUNC_LIKE_FIX_TRUNC
1580 /* Max number of bytes we can move to or from memory
1581 in one reasonably fast instruction. */
1585 /* Controls how many units are moved by expr.c before resorting to movstr.
1586 Without byte/word accesses, we want no more than one; with, several single
1587 byte accesses are better. */
1589 #define MOVE_RATIO (TARGET_BWX ? 7 : 2)
1591 /* Largest number of bytes of an object that can be placed in a register.
1592 On the Alpha we have plenty of registers, so use TImode. */
1593 #define MAX_FIXED_MODE_SIZE GET_MODE_BITSIZE (TImode)
1595 /* Nonzero if access to memory by bytes is no faster than for words.
1596 Also non-zero if doing byte operations (specifically shifts) in registers
1599 On the Alpha, we want to not use the byte operation and instead use
1600 masking operations to access fields; these will save instructions. */
1602 #define SLOW_BYTE_ACCESS 1
1604 /* Define if operations between registers always perform the operation
1605 on the full register even if a narrower mode is specified. */
1606 #define WORD_REGISTER_OPERATIONS
1608 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
1609 will either zero-extend or sign-extend. The value of this macro should
1610 be the code that says which one of the two operations is implicitly
1611 done, NIL if none. */
1612 #define LOAD_EXTEND_OP(MODE) ((MODE) == SImode ? SIGN_EXTEND : ZERO_EXTEND)
1614 /* Define if loading short immediate values into registers sign extends. */
1615 #define SHORT_IMMEDIATES_SIGN_EXTEND
1617 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
1618 is done just by pretending it is already truncated. */
1619 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
1621 /* We assume that the store-condition-codes instructions store 0 for false
1622 and some other value for true. This is the value stored for true. */
1624 #define STORE_FLAG_VALUE 1
1626 /* Define the value returned by a floating-point comparison instruction. */
1628 #define FLOAT_STORE_FLAG_VALUE (TARGET_FLOAT_VAX ? 0.5 : 2.0)
1630 /* Canonicalize a comparison from one we don't have to one we do have. */
1632 #define CANONICALIZE_COMPARISON(CODE,OP0,OP1) \
1634 if (((CODE) == GE || (CODE) == GT || (CODE) == GEU || (CODE) == GTU) \
1635 && (GET_CODE (OP1) == REG || (OP1) == const0_rtx)) \
1640 (CODE) = swap_condition (CODE); \
1642 if (((CODE) == LT || (CODE) == LTU) \
1643 && GET_CODE (OP1) == CONST_INT && INTVAL (OP1) == 256) \
1645 (CODE) = (CODE) == LT ? LE : LEU; \
1646 (OP1) = GEN_INT (255); \
1650 /* Specify the machine mode that pointers have.
1651 After generation of rtl, the compiler makes no further distinction
1652 between pointers and any other objects of this machine mode. */
1653 #define Pmode DImode
1655 /* Mode of a function address in a call instruction (for indexing purposes). */
1657 #define FUNCTION_MODE Pmode
1659 /* Define this if addresses of constant functions
1660 shouldn't be put through pseudo regs where they can be cse'd.
1661 Desirable on machines where ordinary constants are expensive
1662 but a CALL with constant address is cheap.
1664 We define this on the Alpha so that gen_call and gen_call_value
1665 get to see the SYMBOL_REF (for the hint field of the jsr). It will
1666 then copy it into a register, thus actually letting the address be
1669 #define NO_FUNCTION_CSE
1671 /* Define this to be nonzero if shift instructions ignore all but the low-order
1673 #define SHIFT_COUNT_TRUNCATED 1
1675 /* Use atexit for static constructors/destructors, instead of defining
1676 our own exit function. */
1679 /* The EV4 is dual issue; EV5/EV6 are quad issue. */
1680 #define ISSUE_RATE (alpha_cpu == PROCESSOR_EV4 ? 2 : 4)
1682 /* Compute the cost of computing a constant rtl expression RTX
1683 whose rtx-code is CODE. The body of this macro is a portion
1684 of a switch statement. If the code is computed here,
1685 return it with a return statement. Otherwise, break from the switch.
1687 If this is an 8-bit constant, return zero since it can be used
1688 nearly anywhere with no cost. If it is a valid operand for an
1689 ADD or AND, likewise return 0 if we know it will be used in that
1690 context. Otherwise, return 2 since it might be used there later.
1691 All other constants take at least two insns. */
1693 #define CONST_COSTS(RTX,CODE,OUTER_CODE) \
1695 if (INTVAL (RTX) >= 0 && INTVAL (RTX) < 256) \
1697 case CONST_DOUBLE: \
1698 if ((RTX) == CONST0_RTX (GET_MODE (RTX))) \
1700 else if (((OUTER_CODE) == PLUS && add_operand (RTX, VOIDmode)) \
1701 || ((OUTER_CODE) == AND && and_operand (RTX, VOIDmode))) \
1703 else if (add_operand (RTX, VOIDmode) || and_operand (RTX, VOIDmode)) \
1706 return COSTS_N_INSNS (2); \
1710 switch (alpha_cpu) \
1712 case PROCESSOR_EV4: \
1713 return COSTS_N_INSNS (3); \
1714 case PROCESSOR_EV5: \
1715 case PROCESSOR_EV6: \
1716 return COSTS_N_INSNS (2); \
1720 /* Provide the costs of a rtl expression. This is in the body of a
1723 #define RTX_COSTS(X,CODE,OUTER_CODE) \
1724 case PLUS: case MINUS: \
1725 if (FLOAT_MODE_P (GET_MODE (X))) \
1726 switch (alpha_cpu) \
1728 case PROCESSOR_EV4: \
1729 return COSTS_N_INSNS (6); \
1730 case PROCESSOR_EV5: \
1731 case PROCESSOR_EV6: \
1732 return COSTS_N_INSNS (4); \
1735 else if (GET_CODE (XEXP (X, 0)) == MULT \
1736 && const48_operand (XEXP (XEXP (X, 0), 1), VOIDmode)) \
1737 return (2 + rtx_cost (XEXP (XEXP (X, 0), 0), OUTER_CODE) \
1738 + rtx_cost (XEXP (X, 1), OUTER_CODE)); \
1741 switch (alpha_cpu) \
1743 case PROCESSOR_EV4: \
1744 if (FLOAT_MODE_P (GET_MODE (X))) \
1745 return COSTS_N_INSNS (6); \
1746 return COSTS_N_INSNS (23); \
1747 case PROCESSOR_EV5: \
1748 if (FLOAT_MODE_P (GET_MODE (X))) \
1749 return COSTS_N_INSNS (4); \
1750 else if (GET_MODE (X) == DImode) \
1751 return COSTS_N_INSNS (12); \
1753 return COSTS_N_INSNS (8); \
1754 case PROCESSOR_EV6: \
1755 if (FLOAT_MODE_P (GET_MODE (X))) \
1756 return COSTS_N_INSNS (4); \
1758 return COSTS_N_INSNS (7); \
1762 if (GET_CODE (XEXP (X, 1)) == CONST_INT \
1763 && INTVAL (XEXP (X, 1)) <= 3) \
1765 /* ... fall through ... */ \
1766 case ASHIFTRT: case LSHIFTRT: \
1767 switch (alpha_cpu) \
1769 case PROCESSOR_EV4: \
1770 return COSTS_N_INSNS (2); \
1771 case PROCESSOR_EV5: \
1772 case PROCESSOR_EV6: \
1773 return COSTS_N_INSNS (1); \
1776 case IF_THEN_ELSE: \
1777 switch (alpha_cpu) \
1779 case PROCESSOR_EV4: \
1780 case PROCESSOR_EV6: \
1781 return COSTS_N_INSNS (2); \
1782 case PROCESSOR_EV5: \
1783 return COSTS_N_INSNS (1); \
1786 case DIV: case UDIV: case MOD: case UMOD: \
1787 switch (alpha_cpu) \
1789 case PROCESSOR_EV4: \
1790 if (GET_MODE (X) == SFmode) \
1791 return COSTS_N_INSNS (34); \
1792 else if (GET_MODE (X) == DFmode) \
1793 return COSTS_N_INSNS (63); \
1795 return COSTS_N_INSNS (70); \
1796 case PROCESSOR_EV5: \
1797 if (GET_MODE (X) == SFmode) \
1798 return COSTS_N_INSNS (15); \
1799 else if (GET_MODE (X) == DFmode) \
1800 return COSTS_N_INSNS (22); \
1802 return COSTS_N_INSNS (70); /* ??? */ \
1803 case PROCESSOR_EV6: \
1804 if (GET_MODE (X) == SFmode) \
1805 return COSTS_N_INSNS (12); \
1806 else if (GET_MODE (X) == DFmode) \
1807 return COSTS_N_INSNS (15); \
1809 return COSTS_N_INSNS (70); /* ??? */ \
1813 switch (alpha_cpu) \
1815 case PROCESSOR_EV4: \
1816 case PROCESSOR_EV6: \
1817 return COSTS_N_INSNS (3); \
1818 case PROCESSOR_EV5: \
1819 return COSTS_N_INSNS (2); \
1822 case NEG: case ABS: \
1823 if (! FLOAT_MODE_P (GET_MODE (X))) \
1825 /* ... fall through ... */ \
1826 case FLOAT: case UNSIGNED_FLOAT: case FIX: case UNSIGNED_FIX: \
1827 case FLOAT_EXTEND: case FLOAT_TRUNCATE: \
1828 switch (alpha_cpu) \
1830 case PROCESSOR_EV4: \
1831 return COSTS_N_INSNS (6); \
1832 case PROCESSOR_EV5: \
1833 case PROCESSOR_EV6: \
1834 return COSTS_N_INSNS (4); \
1838 /* Control the assembler format that we output. */
1840 /* We don't emit these labels, so as to avoid getting linker errors about
1841 missing exception handling info. If we emit a gcc_compiled. label into
1842 text, and the file has no code, then the DEC assembler gives us a zero
1843 sized text section with no associated exception handling info. The
1844 DEC linker sees this text section, and gives a warning saying that
1845 the exception handling info is missing. */
1846 #define ASM_IDENTIFY_GCC(x)
1847 #define ASM_IDENTIFY_LANGUAGE(x)
1849 /* Output to assembler file text saying following lines
1850 may contain character constants, extra white space, comments, etc. */
1852 #define ASM_APP_ON ""
1854 /* Output to assembler file text saying following lines
1855 no longer contain unusual constructs. */
1857 #define ASM_APP_OFF ""
1859 #define TEXT_SECTION_ASM_OP ".text"
1861 /* Output before read-only data. */
1863 #define READONLY_DATA_SECTION_ASM_OP ".rdata"
1865 /* Output before writable data. */
1867 #define DATA_SECTION_ASM_OP ".data"
1869 /* Define an extra section for read-only data, a routine to enter it, and
1870 indicate that it is for read-only data.
1872 The first time we enter the readonly data section for a file, we write
1873 eight bytes of zero. This works around a bug in DEC's assembler in
1874 some versions of OSF/1 V3.x. */
1876 #define EXTRA_SECTIONS readonly_data
1878 #define EXTRA_SECTION_FUNCTIONS \
1880 literal_section () \
1882 if (in_section != readonly_data) \
1884 static int firsttime = 1; \
1886 fprintf (asm_out_file, "%s\n", READONLY_DATA_SECTION_ASM_OP); \
1890 ASM_OUTPUT_DOUBLE_INT (asm_out_file, const0_rtx); \
1893 in_section = readonly_data; \
1897 #define READONLY_DATA_SECTION literal_section
1899 /* If we are referencing a function that is static, make the SYMBOL_REF
1900 special. We use this to see indicate we can branch to this function
1901 without setting PV or restoring GP. */
1903 #define ENCODE_SECTION_INFO(DECL) \
1904 if (TREE_CODE (DECL) == FUNCTION_DECL && ! TREE_PUBLIC (DECL)) \
1905 SYMBOL_REF_FLAG (XEXP (DECL_RTL (DECL), 0)) = 1;
1907 /* How to refer to registers in assembler output.
1908 This sequence is indexed by compiler's hard-register-number (see above). */
1910 #define REGISTER_NAMES \
1911 {"$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7", "$8", \
1912 "$9", "$10", "$11", "$12", "$13", "$14", "$15", \
1913 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", \
1914 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "AP", \
1915 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", "$f8", \
1916 "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", \
1917 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23",\
1918 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "FP"}
1920 /* How to renumber registers for dbx and gdb. */
1922 #define DBX_REGISTER_NUMBER(REGNO) (REGNO)
1924 /* This is how to output the definition of a user-level label named NAME,
1925 such as the label on a static function or variable NAME. */
1927 #define ASM_OUTPUT_LABEL(FILE,NAME) \
1928 do { assemble_name (FILE, NAME); fputs (":\n", FILE); } while (0)
1930 /* This is how to output a command to make the user-level label named NAME
1931 defined for reference from other files. */
1933 #define ASM_GLOBALIZE_LABEL(FILE,NAME) \
1934 do { fputs ("\t.globl ", FILE); assemble_name (FILE, NAME); fputs ("\n", FILE);} while (0)
1936 /* The prefix to add to user-visible assembler symbols. */
1938 #define USER_LABEL_PREFIX ""
1940 /* This is how to output an internal numbered label where
1941 PREFIX is the class of label and NUM is the number within the class. */
1943 #define ASM_OUTPUT_INTERNAL_LABEL(FILE,PREFIX,NUM) \
1944 fprintf (FILE, "$%s%d:\n", PREFIX, NUM)
1946 /* This is how to output a label for a jump table. Arguments are the same as
1947 for ASM_OUTPUT_INTERNAL_LABEL, except the insn for the jump table is
1950 #define ASM_OUTPUT_CASE_LABEL(FILE,PREFIX,NUM,TABLEINSN) \
1951 { ASM_OUTPUT_ALIGN (FILE, 2); ASM_OUTPUT_INTERNAL_LABEL (FILE, PREFIX, NUM); }
1953 /* This is how to store into the string LABEL
1954 the symbol_ref name of an internal numbered label where
1955 PREFIX is the class of label and NUM is the number within the class.
1956 This is suitable for output with `assemble_name'. */
1958 #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \
1959 sprintf (LABEL, "*$%s%d", PREFIX, NUM)
1961 /* Check a floating-point value for validity for a particular machine mode. */
1963 #define CHECK_FLOAT_VALUE(MODE, D, OVERFLOW) \
1964 ((OVERFLOW) = check_float_value (MODE, &D, OVERFLOW))
1966 /* This is how to output an assembler line defining a `double' constant. */
1968 #define ASM_OUTPUT_DOUBLE(FILE,VALUE) \
1970 if (REAL_VALUE_ISINF (VALUE) \
1971 || REAL_VALUE_ISNAN (VALUE) \
1972 || REAL_VALUE_MINUS_ZERO (VALUE)) \
1975 REAL_VALUE_TO_TARGET_DOUBLE ((VALUE), t); \
1976 fprintf (FILE, "\t.quad 0x%lx%08lx\n", \
1977 t[1] & 0xffffffff, t[0] & 0xffffffff); \
1982 REAL_VALUE_TO_DECIMAL (VALUE, "%.20e", str); \
1983 fprintf (FILE, "\t.%c_floating %s\n", (TARGET_FLOAT_VAX)?'g':'t', str); \
1987 /* This is how to output an assembler line defining a `float' constant. */
1989 #define ASM_OUTPUT_FLOAT(FILE,VALUE) \
1992 REAL_VALUE_TO_TARGET_SINGLE ((VALUE), t); \
1993 fprintf (FILE, "\t.long 0x%lx\n", t & 0xffffffff); \
1996 /* This is how to output an assembler line defining an `int' constant. */
1998 #define ASM_OUTPUT_INT(FILE,VALUE) \
1999 ( fprintf (FILE, "\t.long "), \
2000 output_addr_const (FILE, (VALUE)), \
2001 fprintf (FILE, "\n"))
2003 /* This is how to output an assembler line defining a `long' constant. */
2005 #define ASM_OUTPUT_DOUBLE_INT(FILE,VALUE) \
2006 ( fprintf (FILE, "\t.quad "), \
2007 output_addr_const (FILE, (VALUE)), \
2008 fprintf (FILE, "\n"))
2010 /* Likewise for `char' and `short' constants. */
2012 #define ASM_OUTPUT_SHORT(FILE,VALUE) \
2013 fprintf (FILE, "\t.word %d\n", \
2014 (int)(GET_CODE (VALUE) == CONST_INT \
2015 ? INTVAL (VALUE) & 0xffff : (abort (), 0)))
2017 #define ASM_OUTPUT_CHAR(FILE,VALUE) \
2018 fprintf (FILE, "\t.byte %d\n", \
2019 (int)(GET_CODE (VALUE) == CONST_INT \
2020 ? INTVAL (VALUE) & 0xff : (abort (), 0)))
2022 /* We use the default ASCII-output routine, except that we don't write more
2023 than 50 characters since the assembler doesn't support very long lines. */
2025 #define ASM_OUTPUT_ASCII(MYFILE, MYSTRING, MYLENGTH) \
2027 FILE *_hide_asm_out_file = (MYFILE); \
2028 unsigned char *_hide_p = (unsigned char *) (MYSTRING); \
2029 int _hide_thissize = (MYLENGTH); \
2030 int _size_so_far = 0; \
2032 FILE *asm_out_file = _hide_asm_out_file; \
2033 unsigned char *p = _hide_p; \
2034 int thissize = _hide_thissize; \
2036 fprintf (asm_out_file, "\t.ascii \""); \
2038 for (i = 0; i < thissize; i++) \
2040 register int c = p[i]; \
2042 if (_size_so_far ++ > 50 && i < thissize - 4) \
2043 _size_so_far = 0, fprintf (asm_out_file, "\"\n\t.ascii \""); \
2045 if (c == '\"' || c == '\\') \
2046 putc ('\\', asm_out_file); \
2047 if (c >= ' ' && c < 0177) \
2048 putc (c, asm_out_file); \
2051 fprintf (asm_out_file, "\\%o", c); \
2052 /* After an octal-escape, if a digit follows, \
2053 terminate one string constant and start another. \
2054 The Vax assembler fails to stop reading the escape \
2055 after three digits, so this is the only way we \
2056 can get it to parse the data properly. */ \
2057 if (i < thissize - 1 \
2058 && p[i + 1] >= '0' && p[i + 1] <= '9') \
2059 _size_so_far = 0, fprintf (asm_out_file, "\"\n\t.ascii \""); \
2062 fprintf (asm_out_file, "\"\n"); \
2067 /* This is how to output an insn to push a register on the stack.
2068 It need not be very fast code. */
2070 #define ASM_OUTPUT_REG_PUSH(FILE,REGNO) \
2071 fprintf (FILE, "\tsubq $30,8,$30\n\tst%s $%s%d,0($30)\n", \
2072 (REGNO) > 32 ? "t" : "q", (REGNO) > 32 ? "f" : "", \
2075 /* This is how to output an insn to pop a register from the stack.
2076 It need not be very fast code. */
2078 #define ASM_OUTPUT_REG_POP(FILE,REGNO) \
2079 fprintf (FILE, "\tld%s $%s%d,0($30)\n\taddq $30,8,$30\n", \
2080 (REGNO) > 32 ? "t" : "q", (REGNO) > 32 ? "f" : "", \
2083 /* This is how to output an assembler line for a numeric constant byte. */
2085 #define ASM_OUTPUT_BYTE(FILE,VALUE) \
2086 fprintf (FILE, "\t.byte 0x%x\n", (int) ((VALUE) & 0xff))
2088 /* This is how to output an element of a case-vector that is absolute.
2089 (Alpha does not use such vectors, but we must define this macro anyway.) */
2091 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) abort ()
2093 /* This is how to output an element of a case-vector that is relative. */
2095 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
2096 fprintf (FILE, "\t.%s $L%d\n", TARGET_WINDOWS_NT ? "long" : "gprel32", \
2099 /* This is how to output an assembler line
2100 that says to advance the location counter
2101 to a multiple of 2**LOG bytes. */
2103 #define ASM_OUTPUT_ALIGN(FILE,LOG) \
2105 fprintf (FILE, "\t.align %d\n", LOG);
2107 /* This is how to advance the location counter by SIZE bytes. */
2109 #define ASM_OUTPUT_SKIP(FILE,SIZE) \
2110 fprintf (FILE, "\t.space %d\n", (SIZE))
2112 /* This says how to output an assembler line
2113 to define a global common symbol. */
2115 #define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED) \
2116 ( fputs ("\t.comm ", (FILE)), \
2117 assemble_name ((FILE), (NAME)), \
2118 fprintf ((FILE), ",%d\n", (SIZE)))
2120 /* This says how to output an assembler line
2121 to define a local common symbol. */
2123 #define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE,ROUNDED) \
2124 ( fputs ("\t.lcomm ", (FILE)), \
2125 assemble_name ((FILE), (NAME)), \
2126 fprintf ((FILE), ",%d\n", (SIZE)))
2128 /* Store in OUTPUT a string (made with alloca) containing
2129 an assembler-name for a local static variable named NAME.
2130 LABELNO is an integer which is different for each call. */
2132 #define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO) \
2133 ( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 10), \
2134 sprintf ((OUTPUT), "%s.%d", (NAME), (LABELNO)))
2136 /* Define the parentheses used to group arithmetic operations
2137 in assembler code. */
2139 #define ASM_OPEN_PAREN "("
2140 #define ASM_CLOSE_PAREN ")"
2142 /* Output code to add DELTA to the first argument, and then jump to FUNCTION.
2143 Used for C++ multiple inheritance. */
2145 #define ASM_OUTPUT_MI_THUNK(FILE, THUNK_FNDECL, DELTA, FUNCTION) \
2147 char *fn_name = XSTR (XEXP (DECL_RTL (FUNCTION), 0), 0); \
2150 /* Mark end of prologue. */ \
2151 output_end_prologue (FILE); \
2153 /* Rely on the assembler to macro expand a large delta. */ \
2154 reg = aggregate_value_p (TREE_TYPE (TREE_TYPE (FUNCTION))) ? 17 : 16; \
2155 fprintf (FILE, "\tlda $%d,%ld($%d)\n", reg, (long)(DELTA), reg); \
2157 if (current_file_function_operand (XEXP (DECL_RTL (FUNCTION), 0))) \
2159 fprintf (FILE, "\tbr $31,$"); \
2160 assemble_name (FILE, fn_name); \
2161 fprintf (FILE, "..ng\n"); \
2165 fprintf (FILE, "\tjmp $31,"); \
2166 assemble_name (FILE, fn_name); \
2167 fputc ('\n', FILE); \
2172 /* Define results of standard character escape sequences. */
2173 #define TARGET_BELL 007
2174 #define TARGET_BS 010
2175 #define TARGET_TAB 011
2176 #define TARGET_NEWLINE 012
2177 #define TARGET_VT 013
2178 #define TARGET_FF 014
2179 #define TARGET_CR 015
2181 /* Print operand X (an rtx) in assembler syntax to file FILE.
2182 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
2183 For `%' followed by punctuation, CODE is the punctuation and X is null. */
2185 #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE)
2187 /* Determine which codes are valid without a following integer. These must
2188 not be alphabetic (the characters are chosen so that
2189 PRINT_OPERAND_PUNCT_VALID_P translates into a simple range change when
2192 & Generates fp-rounding mode suffix: nothing for normal, 'c' for
2193 chopped, 'm' for minus-infinity, and 'd' for dynamic rounding
2194 mode. alpha_fprm controls which suffix is generated.
2196 ' Generates trap-mode suffix for instructions that accept the
2197 su suffix only (cmpt et al).
2199 ` Generates trap-mode suffix for instructions that accept the
2200 v and sv suffix. The only instruction that needs this is cvtql.
2202 ( Generates trap-mode suffix for instructions that accept the
2203 v, sv, and svi suffix. The only instruction that needs this
2206 ) Generates trap-mode suffix for instructions that accept the
2207 u, su, and sui suffix. This is the bulk of the IEEE floating
2208 point instructions (addt et al).
2210 + Generates trap-mode suffix for instructions that accept the
2211 sui suffix (cvtqt and cvtqs).
2213 , Generates single precision suffix for floating point
2214 instructions (s for IEEE, f for VAX)
2216 - Generates double precision suffix for floating point
2217 instructions (t for IEEE, g for VAX)
2220 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) \
2221 ((CODE) == '&' || (CODE) == '`' || (CODE) == '\'' || (CODE) == '(' \
2222 || (CODE) == ')' || (CODE) == '+' || (CODE) == ',' || (CODE) == '-')
2224 /* Print a memory address as an operand to reference that memory location. */
2226 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) \
2227 { rtx addr = (ADDR); \
2229 HOST_WIDE_INT offset = 0; \
2231 if (GET_CODE (addr) == AND) \
2232 addr = XEXP (addr, 0); \
2234 if (GET_CODE (addr) == REG) \
2235 basereg = REGNO (addr); \
2236 else if (GET_CODE (addr) == CONST_INT) \
2237 offset = INTVAL (addr); \
2238 else if (GET_CODE (addr) == PLUS \
2239 && GET_CODE (XEXP (addr, 0)) == REG \
2240 && GET_CODE (XEXP (addr, 1)) == CONST_INT) \
2241 basereg = REGNO (XEXP (addr, 0)), offset = INTVAL (XEXP (addr, 1)); \
2245 fprintf (FILE, HOST_WIDE_INT_PRINT_DEC, offset); \
2246 fprintf (FILE, "($%d)", basereg); \
2248 /* Define the codes that are matched by predicates in alpha.c. */
2250 #define PREDICATE_CODES \
2251 {"reg_or_0_operand", {SUBREG, REG, CONST_INT}}, \
2252 {"reg_or_6bit_operand", {SUBREG, REG, CONST_INT, CONSTANT_P_RTX}}, \
2253 {"reg_or_8bit_operand", {SUBREG, REG, CONST_INT, CONSTANT_P_RTX}}, \
2254 {"cint8_operand", {CONST_INT, CONSTANT_P_RTX}}, \
2255 {"reg_or_cint_operand", {SUBREG, REG, CONST_INT, CONSTANT_P_RTX}}, \
2256 {"add_operand", {SUBREG, REG, CONST_INT, CONSTANT_P_RTX}}, \
2257 {"sext_add_operand", {SUBREG, REG, CONST_INT, CONSTANT_P_RTX}}, \
2258 {"const48_operand", {CONST_INT}}, \
2259 {"and_operand", {SUBREG, REG, CONST_INT, CONSTANT_P_RTX}}, \
2260 {"or_operand", {SUBREG, REG, CONST_INT, CONSTANT_P_RTX}}, \
2261 {"mode_mask_operand", {CONST_INT}}, \
2262 {"mul8_operand", {CONST_INT}}, \
2263 {"mode_width_operand", {CONST_INT}}, \
2264 {"reg_or_fp0_operand", {SUBREG, REG, CONST_DOUBLE}}, \
2265 {"alpha_comparison_operator", {EQ, LE, LT, LEU, LTU}}, \
2266 {"alpha_swapped_comparison_operator", {EQ, GE, GT, GEU, GTU}}, \
2267 {"signed_comparison_operator", {EQ, NE, LE, LT, GE, GT}}, \
2268 {"divmod_operator", {DIV, MOD, UDIV, UMOD}}, \
2269 {"fp0_operand", {CONST_DOUBLE}}, \
2270 {"current_file_function_operand", {SYMBOL_REF}}, \
2271 {"call_operand", {REG, SYMBOL_REF}}, \
2272 {"input_operand", {SUBREG, REG, MEM, CONST_INT, CONST_DOUBLE, \
2273 SYMBOL_REF, CONST, LABEL_REF, CONSTANT_P_RTX}}, \
2274 {"some_operand", {SUBREG, REG, MEM, CONST_INT, CONST_DOUBLE, \
2275 SYMBOL_REF, CONST, LABEL_REF, CONSTANT_P_RTX}}, \
2276 {"aligned_memory_operand", {MEM}}, \
2277 {"unaligned_memory_operand", {MEM}}, \
2278 {"reg_or_unaligned_mem_operand", {SUBREG, REG, MEM}}, \
2279 {"any_memory_operand", {MEM}}, \
2280 {"hard_fp_register_operand", {SUBREG, REG}},
2282 /* Tell collect that the object format is ECOFF. */
2283 #define OBJECT_FORMAT_COFF
2284 #define EXTENDED_COFF
2286 /* If we use NM, pass -g to it so it only lists globals. */
2287 #define NM_FLAGS "-pg"
2289 /* Definitions for debugging. */
2291 #define SDB_DEBUGGING_INFO /* generate info for mips-tfile */
2292 #define DBX_DEBUGGING_INFO /* generate embedded stabs */
2293 #define MIPS_DEBUGGING_INFO /* MIPS specific debugging info */
2295 #ifndef PREFERRED_DEBUGGING_TYPE /* assume SDB_DEBUGGING_INFO */
2296 #define PREFERRED_DEBUGGING_TYPE SDB_DEBUG
2300 /* Correct the offset of automatic variables and arguments. Note that
2301 the Alpha debug format wants all automatic variables and arguments
2302 to be in terms of two different offsets from the virtual frame pointer,
2303 which is the stack pointer before any adjustment in the function.
2304 The offset for the argument pointer is fixed for the native compiler,
2305 it is either zero (for the no arguments case) or large enough to hold
2306 all argument registers.
2307 The offset for the auto pointer is the fourth argument to the .frame
2308 directive (local_offset).
2309 To stay compatible with the native tools we use the same offsets
2310 from the virtual frame pointer and adjust the debugger arg/auto offsets
2311 accordingly. These debugger offsets are set up in output_prolog. */
2313 extern long alpha_arg_offset;
2314 extern long alpha_auto_offset;
2315 #define DEBUGGER_AUTO_OFFSET(X) \
2316 ((GET_CODE (X) == PLUS ? INTVAL (XEXP (X, 1)) : 0) + alpha_auto_offset)
2317 #define DEBUGGER_ARG_OFFSET(OFFSET, X) (OFFSET + alpha_arg_offset)
2320 #define ASM_OUTPUT_SOURCE_LINE(STREAM, LINE) \
2321 alpha_output_lineno (STREAM, LINE)
2322 extern void alpha_output_lineno ();
2324 #define ASM_OUTPUT_SOURCE_FILENAME(STREAM, NAME) \
2325 alpha_output_filename (STREAM, NAME)
2326 extern void alpha_output_filename ();
2328 /* mips-tfile.c limits us to strings of one page. We must underestimate this
2329 number, because the real length runs past this up to the next
2330 continuation point. This is really a dbxout.c bug. */
2331 #define DBX_CONTIN_LENGTH 3000
2333 /* By default, turn on GDB extensions. */
2334 #define DEFAULT_GDB_EXTENSIONS 1
2336 /* Stabs-in-ECOFF can't handle dbxout_function_end(). */
2337 #define NO_DBX_FUNCTION_END 1
2339 /* If we are smuggling stabs through the ALPHA ECOFF object
2340 format, put a comment in front of the .stab<x> operation so
2341 that the ALPHA assembler does not choke. The mips-tfile program
2342 will correctly put the stab into the object file. */
2344 #define ASM_STABS_OP ((TARGET_GAS) ? ".stabs" : " #.stabs")
2345 #define ASM_STABN_OP ((TARGET_GAS) ? ".stabn" : " #.stabn")
2346 #define ASM_STABD_OP ((TARGET_GAS) ? ".stabd" : " #.stabd")
2348 /* Forward references to tags are allowed. */
2349 #define SDB_ALLOW_FORWARD_REFERENCES
2351 /* Unknown tags are also allowed. */
2352 #define SDB_ALLOW_UNKNOWN_REFERENCES
2354 #define PUT_SDB_DEF(a) \
2356 fprintf (asm_out_file, "\t%s.def\t", \
2357 (TARGET_GAS) ? "" : "#"); \
2358 ASM_OUTPUT_LABELREF (asm_out_file, a); \
2359 fputc (';', asm_out_file); \
2362 #define PUT_SDB_PLAIN_DEF(a) \
2364 fprintf (asm_out_file, "\t%s.def\t.%s;", \
2365 (TARGET_GAS) ? "" : "#", (a)); \
2368 #define PUT_SDB_TYPE(a) \
2370 fprintf (asm_out_file, "\t.type\t0x%x;", (a)); \
2373 /* For block start and end, we create labels, so that
2374 later we can figure out where the correct offset is.
2375 The normal .ent/.end serve well enough for functions,
2376 so those are just commented out. */
2378 extern int sdb_label_count; /* block start/end next label # */
2380 #define PUT_SDB_BLOCK_START(LINE) \
2382 fprintf (asm_out_file, \
2383 "$Lb%d:\n\t%s.begin\t$Lb%d\t%d\n", \
2385 (TARGET_GAS) ? "" : "#", \
2388 sdb_label_count++; \
2391 #define PUT_SDB_BLOCK_END(LINE) \
2393 fprintf (asm_out_file, \
2394 "$Le%d:\n\t%s.bend\t$Le%d\t%d\n", \
2396 (TARGET_GAS) ? "" : "#", \
2399 sdb_label_count++; \
2402 #define PUT_SDB_FUNCTION_START(LINE)
2404 #define PUT_SDB_FUNCTION_END(LINE)
2406 #define PUT_SDB_EPILOGUE_END(NAME) ((void)(NAME))
2408 /* Macros for mips-tfile.c to encapsulate stabs in ECOFF, and for
2409 mips-tdump.c to print them out.
2411 These must match the corresponding definitions in gdb/mipsread.c.
2412 Unfortunately, gcc and gdb do not currently share any directories. */
2414 #define CODE_MASK 0x8F300
2415 #define MIPS_IS_STAB(sym) (((sym)->index & 0xFFF00) == CODE_MASK)
2416 #define MIPS_MARK_STAB(code) ((code)+CODE_MASK)
2417 #define MIPS_UNMARK_STAB(code) ((code)-CODE_MASK)
2419 /* Override some mips-tfile definitions. */
2421 #define SHASH_SIZE 511
2422 #define THASH_SIZE 55
2424 /* Align ecoff symbol tables to avoid OSF1/1.3 nm complaints. */
2426 #define ALIGN_SYMTABLE_OFFSET(OFFSET) (((OFFSET) + 7) & ~7)
2428 /* The linker will stick __main into the .init section. */
2429 #define HAS_INIT_SECTION
2430 #define LD_INIT_SWITCH "-init"
2431 #define LD_FINI_SWITCH "-fini"
2433 /* The system headers under Alpha systems are generally C++-aware. */
2434 #define NO_IMPLICIT_EXTERN_C
2436 /* Prototypes for alpha.c functions used in the md file & elsewhere. */
2437 extern struct rtx_def *get_unaligned_address ();
2438 extern void alpha_write_verstamp ();
2439 extern void alpha_reorg ();
2440 extern int check_float_value ();
2441 extern int direct_return ();
2442 extern int const48_operand ();
2443 extern int add_operand ();
2444 extern int and_operand ();
2445 extern int unaligned_memory_operand ();
2446 extern int zap_mask ();
2447 extern int current_file_function_operand ();
2448 extern int alpha_sa_size ();
2449 extern int alpha_adjust_cost ();
2450 extern void print_operand ();
2451 extern int reg_or_0_operand ();
2452 extern int reg_or_8bit_operand ();
2453 extern int mul8_operand ();
2454 extern int reg_or_6bit_operand ();
2455 extern int alpha_comparison_operator ();
2456 extern int alpha_swapped_comparison_operator ();
2457 extern int sext_add_operand ();
2458 extern int cint8_operand ();
2459 extern int mode_mask_operand ();
2460 extern int or_operand ();
2461 extern int mode_width_operand ();
2462 extern int reg_or_fp0_operand ();
2463 extern int signed_comparison_operator ();
2464 extern int fp0_operand ();
2465 extern int some_operand ();
2466 extern int input_operand ();
2467 extern int divmod_operator ();
2468 extern int call_operand ();
2469 extern int reg_or_cint_operand ();
2470 extern int hard_fp_register_operand ();
2471 extern void alpha_set_memflags ();
2472 extern int aligned_memory_operand ();
2473 extern void get_aligned_mem ();
2474 extern void alpha_expand_unaligned_load ();
2475 extern void alpha_expand_unaligned_store ();
2476 extern int alpha_expand_block_move ();
2477 extern int alpha_expand_block_clear ();
2478 extern void alpha_expand_prologue ();
2479 extern void alpha_expand_epilogue ();
OSDN Git Service
