1 /* Subroutines used for code generation on the DEC Alpha.
2 Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002, 2003, 2004 Free Software Foundation, Inc.
4 Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
13 GCC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING. If not, write to
20 the Free Software Foundation, 59 Temple Place - Suite 330,
21 Boston, MA 02111-1307, USA. */
26 #include "coretypes.h"
31 #include "hard-reg-set.h"
33 #include "insn-config.h"
34 #include "conditions.h"
36 #include "insn-attr.h"
47 #include "integrate.h"
50 #include "target-def.h"
52 #include "langhooks.h"
53 #include <splay-tree.h>
54 #include "cfglayout.h"
56 /* Specify which cpu to schedule for. */
58 enum processor_type alpha_cpu;
59 static const char * const alpha_cpu_name[] =
64 /* Specify how accurate floating-point traps need to be. */
66 enum alpha_trap_precision alpha_tp;
68 /* Specify the floating-point rounding mode. */
70 enum alpha_fp_rounding_mode alpha_fprm;
72 /* Specify which things cause traps. */
74 enum alpha_fp_trap_mode alpha_fptm;
76 /* Specify bit size of immediate TLS offsets. */
78 int alpha_tls_size = 32;
80 /* Strings decoded into the above options. */
82 const char *alpha_cpu_string; /* -mcpu= */
83 const char *alpha_tune_string; /* -mtune= */
84 const char *alpha_tp_string; /* -mtrap-precision=[p|s|i] */
85 const char *alpha_fprm_string; /* -mfp-rounding-mode=[n|m|c|d] */
86 const char *alpha_fptm_string; /* -mfp-trap-mode=[n|u|su|sui] */
87 const char *alpha_mlat_string; /* -mmemory-latency= */
88 const char *alpha_tls_size_string; /* -mtls-size=[16|32|64] */
90 /* Save information from a "cmpxx" operation until the branch or scc is
93 struct alpha_compare alpha_compare;
95 /* Nonzero if inside of a function, because the Alpha asm can't
96 handle .files inside of functions. */
98 static int inside_function = FALSE;
100 /* The number of cycles of latency we should assume on memory reads. */
102 int alpha_memory_latency = 3;
104 /* Whether the function needs the GP. */
106 static int alpha_function_needs_gp;
108 /* The alias set for prologue/epilogue register save/restore. */
110 static GTY(()) int alpha_sr_alias_set;
112 /* The assembler name of the current function. */
114 static const char *alpha_fnname;
116 /* The next explicit relocation sequence number. */
117 extern GTY(()) int alpha_next_sequence_number;
118 int alpha_next_sequence_number = 1;
120 /* The literal and gpdisp sequence numbers for this insn, as printed
121 by %# and %* respectively. */
122 extern GTY(()) int alpha_this_literal_sequence_number;
123 extern GTY(()) int alpha_this_gpdisp_sequence_number;
124 int alpha_this_literal_sequence_number;
125 int alpha_this_gpdisp_sequence_number;
127 /* Costs of various operations on the different architectures. */
129 struct alpha_rtx_cost_data
131 unsigned char fp_add;
132 unsigned char fp_mult;
133 unsigned char fp_div_sf;
134 unsigned char fp_div_df;
135 unsigned char int_mult_si;
136 unsigned char int_mult_di;
137 unsigned char int_shift;
138 unsigned char int_cmov;
141 static struct alpha_rtx_cost_data const alpha_rtx_cost_data[PROCESSOR_MAX] =
144 COSTS_N_INSNS (6), /* fp_add */
145 COSTS_N_INSNS (6), /* fp_mult */
146 COSTS_N_INSNS (34), /* fp_div_sf */
147 COSTS_N_INSNS (63), /* fp_div_df */
148 COSTS_N_INSNS (23), /* int_mult_si */
149 COSTS_N_INSNS (23), /* int_mult_di */
150 COSTS_N_INSNS (2), /* int_shift */
151 COSTS_N_INSNS (2), /* int_cmov */
154 COSTS_N_INSNS (4), /* fp_add */
155 COSTS_N_INSNS (4), /* fp_mult */
156 COSTS_N_INSNS (15), /* fp_div_sf */
157 COSTS_N_INSNS (22), /* fp_div_df */
158 COSTS_N_INSNS (8), /* int_mult_si */
159 COSTS_N_INSNS (12), /* int_mult_di */
160 COSTS_N_INSNS (1) + 1, /* int_shift */
161 COSTS_N_INSNS (1), /* int_cmov */
164 COSTS_N_INSNS (4), /* fp_add */
165 COSTS_N_INSNS (4), /* fp_mult */
166 COSTS_N_INSNS (12), /* fp_div_sf */
167 COSTS_N_INSNS (15), /* fp_div_df */
168 COSTS_N_INSNS (7), /* int_mult_si */
169 COSTS_N_INSNS (7), /* int_mult_di */
170 COSTS_N_INSNS (1), /* int_shift */
171 COSTS_N_INSNS (2), /* int_cmov */
175 /* Get the number of args of a function in one of two ways. */
176 #if TARGET_ABI_OPEN_VMS || TARGET_ABI_UNICOSMK
177 #define NUM_ARGS current_function_args_info.num_args
179 #define NUM_ARGS current_function_args_info
185 /* Declarations of static functions. */
186 static struct machine_function *alpha_init_machine_status (void);
187 static rtx alpha_emit_xfloating_compare (enum rtx_code, rtx, rtx);
189 #if TARGET_ABI_OPEN_VMS
190 static void alpha_write_linkage (FILE *, const char *, tree);
193 static void unicosmk_output_deferred_case_vectors (FILE *);
194 static void unicosmk_gen_dsib (unsigned long *);
195 static void unicosmk_output_ssib (FILE *, const char *);
196 static int unicosmk_need_dex (rtx);
198 /* Parse target option strings. */
201 override_options (void)
204 static const struct cpu_table {
205 const char *const name;
206 const enum processor_type processor;
209 #define EV5_MASK (MASK_CPU_EV5)
210 #define EV6_MASK (MASK_CPU_EV6|MASK_BWX|MASK_MAX|MASK_FIX)
211 { "ev4", PROCESSOR_EV4, 0 },
212 { "ev45", PROCESSOR_EV4, 0 },
213 { "21064", PROCESSOR_EV4, 0 },
214 { "ev5", PROCESSOR_EV5, EV5_MASK },
215 { "21164", PROCESSOR_EV5, EV5_MASK },
216 { "ev56", PROCESSOR_EV5, EV5_MASK|MASK_BWX },
217 { "21164a", PROCESSOR_EV5, EV5_MASK|MASK_BWX },
218 { "pca56", PROCESSOR_EV5, EV5_MASK|MASK_BWX|MASK_MAX },
219 { "21164PC",PROCESSOR_EV5, EV5_MASK|MASK_BWX|MASK_MAX },
220 { "21164pc",PROCESSOR_EV5, EV5_MASK|MASK_BWX|MASK_MAX },
221 { "ev6", PROCESSOR_EV6, EV6_MASK },
222 { "21264", PROCESSOR_EV6, EV6_MASK },
223 { "ev67", PROCESSOR_EV6, EV6_MASK|MASK_CIX },
224 { "21264a", PROCESSOR_EV6, EV6_MASK|MASK_CIX },
228 /* Unicos/Mk doesn't have shared libraries. */
229 if (TARGET_ABI_UNICOSMK && flag_pic)
231 warning ("-f%s ignored for Unicos/Mk (not supported)",
232 (flag_pic > 1) ? "PIC" : "pic");
236 /* On Unicos/Mk, the native compiler consistently generates /d suffices for
237 floating-point instructions. Make that the default for this target. */
238 if (TARGET_ABI_UNICOSMK)
239 alpha_fprm = ALPHA_FPRM_DYN;
241 alpha_fprm = ALPHA_FPRM_NORM;
243 alpha_tp = ALPHA_TP_PROG;
244 alpha_fptm = ALPHA_FPTM_N;
246 /* We cannot use su and sui qualifiers for conversion instructions on
247 Unicos/Mk. I'm not sure if this is due to assembler or hardware
248 limitations. Right now, we issue a warning if -mieee is specified
249 and then ignore it; eventually, we should either get it right or
250 disable the option altogether. */
254 if (TARGET_ABI_UNICOSMK)
255 warning ("-mieee not supported on Unicos/Mk");
258 alpha_tp = ALPHA_TP_INSN;
259 alpha_fptm = ALPHA_FPTM_SU;
263 if (TARGET_IEEE_WITH_INEXACT)
265 if (TARGET_ABI_UNICOSMK)
266 warning ("-mieee-with-inexact not supported on Unicos/Mk");
269 alpha_tp = ALPHA_TP_INSN;
270 alpha_fptm = ALPHA_FPTM_SUI;
276 if (! strcmp (alpha_tp_string, "p"))
277 alpha_tp = ALPHA_TP_PROG;
278 else if (! strcmp (alpha_tp_string, "f"))
279 alpha_tp = ALPHA_TP_FUNC;
280 else if (! strcmp (alpha_tp_string, "i"))
281 alpha_tp = ALPHA_TP_INSN;
283 error ("bad value `%s' for -mtrap-precision switch", alpha_tp_string);
286 if (alpha_fprm_string)
288 if (! strcmp (alpha_fprm_string, "n"))
289 alpha_fprm = ALPHA_FPRM_NORM;
290 else if (! strcmp (alpha_fprm_string, "m"))
291 alpha_fprm = ALPHA_FPRM_MINF;
292 else if (! strcmp (alpha_fprm_string, "c"))
293 alpha_fprm = ALPHA_FPRM_CHOP;
294 else if (! strcmp (alpha_fprm_string,"d"))
295 alpha_fprm = ALPHA_FPRM_DYN;
297 error ("bad value `%s' for -mfp-rounding-mode switch",
301 if (alpha_fptm_string)
303 if (strcmp (alpha_fptm_string, "n") == 0)
304 alpha_fptm = ALPHA_FPTM_N;
305 else if (strcmp (alpha_fptm_string, "u") == 0)
306 alpha_fptm = ALPHA_FPTM_U;
307 else if (strcmp (alpha_fptm_string, "su") == 0)
308 alpha_fptm = ALPHA_FPTM_SU;
309 else if (strcmp (alpha_fptm_string, "sui") == 0)
310 alpha_fptm = ALPHA_FPTM_SUI;
312 error ("bad value `%s' for -mfp-trap-mode switch", alpha_fptm_string);
315 if (alpha_tls_size_string)
317 if (strcmp (alpha_tls_size_string, "16") == 0)
319 else if (strcmp (alpha_tls_size_string, "32") == 0)
321 else if (strcmp (alpha_tls_size_string, "64") == 0)
324 error ("bad value `%s' for -mtls-size switch", alpha_tls_size_string);
328 = TARGET_CPU_DEFAULT & MASK_CPU_EV6 ? PROCESSOR_EV6
329 : (TARGET_CPU_DEFAULT & MASK_CPU_EV5 ? PROCESSOR_EV5 : PROCESSOR_EV4);
331 if (alpha_cpu_string)
333 for (i = 0; cpu_table [i].name; i++)
334 if (! strcmp (alpha_cpu_string, cpu_table [i].name))
336 alpha_cpu = cpu_table [i].processor;
337 target_flags &= ~ (MASK_BWX | MASK_MAX | MASK_FIX | MASK_CIX
338 | MASK_CPU_EV5 | MASK_CPU_EV6);
339 target_flags |= cpu_table [i].flags;
342 if (! cpu_table [i].name)
343 error ("bad value `%s' for -mcpu switch", alpha_cpu_string);
346 if (alpha_tune_string)
348 for (i = 0; cpu_table [i].name; i++)
349 if (! strcmp (alpha_tune_string, cpu_table [i].name))
351 alpha_cpu = cpu_table [i].processor;
354 if (! cpu_table [i].name)
355 error ("bad value `%s' for -mcpu switch", alpha_tune_string);
358 /* Do some sanity checks on the above options. */
360 if (TARGET_ABI_UNICOSMK && alpha_fptm != ALPHA_FPTM_N)
362 warning ("trap mode not supported on Unicos/Mk");
363 alpha_fptm = ALPHA_FPTM_N;
366 if ((alpha_fptm == ALPHA_FPTM_SU || alpha_fptm == ALPHA_FPTM_SUI)
367 && alpha_tp != ALPHA_TP_INSN && ! TARGET_CPU_EV6)
369 warning ("fp software completion requires -mtrap-precision=i");
370 alpha_tp = ALPHA_TP_INSN;
375 /* Except for EV6 pass 1 (not released), we always have precise
376 arithmetic traps. Which means we can do software completion
377 without minding trap shadows. */
378 alpha_tp = ALPHA_TP_PROG;
381 if (TARGET_FLOAT_VAX)
383 if (alpha_fprm == ALPHA_FPRM_MINF || alpha_fprm == ALPHA_FPRM_DYN)
385 warning ("rounding mode not supported for VAX floats");
386 alpha_fprm = ALPHA_FPRM_NORM;
388 if (alpha_fptm == ALPHA_FPTM_SUI)
390 warning ("trap mode not supported for VAX floats");
391 alpha_fptm = ALPHA_FPTM_SU;
399 if (!alpha_mlat_string)
400 alpha_mlat_string = "L1";
402 if (ISDIGIT ((unsigned char)alpha_mlat_string[0])
403 && (lat = strtol (alpha_mlat_string, &end, 10), *end == '\0'))
405 else if ((alpha_mlat_string[0] == 'L' || alpha_mlat_string[0] == 'l')
406 && ISDIGIT ((unsigned char)alpha_mlat_string[1])
407 && alpha_mlat_string[2] == '\0')
409 static int const cache_latency[][4] =
411 { 3, 30, -1 }, /* ev4 -- Bcache is a guess */
412 { 2, 12, 38 }, /* ev5 -- Bcache from PC164 LMbench numbers */
413 { 3, 12, 30 }, /* ev6 -- Bcache from DS20 LMbench. */
416 lat = alpha_mlat_string[1] - '0';
417 if (lat <= 0 || lat > 3 || cache_latency[alpha_cpu][lat-1] == -1)
419 warning ("L%d cache latency unknown for %s",
420 lat, alpha_cpu_name[alpha_cpu]);
424 lat = cache_latency[alpha_cpu][lat-1];
426 else if (! strcmp (alpha_mlat_string, "main"))
428 /* Most current memories have about 370ns latency. This is
429 a reasonable guess for a fast cpu. */
434 warning ("bad value `%s' for -mmemory-latency", alpha_mlat_string);
438 alpha_memory_latency = lat;
441 /* Default the definition of "small data" to 8 bytes. */
445 /* Infer TARGET_SMALL_DATA from -fpic/-fPIC. */
447 target_flags |= MASK_SMALL_DATA;
448 else if (flag_pic == 2)
449 target_flags &= ~MASK_SMALL_DATA;
451 /* Align labels and loops for optimal branching. */
452 /* ??? Kludge these by not doing anything if we don't optimize and also if
453 we are writing ECOFF symbols to work around a bug in DEC's assembler. */
454 if (optimize > 0 && write_symbols != SDB_DEBUG)
456 if (align_loops <= 0)
458 if (align_jumps <= 0)
461 if (align_functions <= 0)
462 align_functions = 16;
464 /* Acquire a unique set number for our register saves and restores. */
465 alpha_sr_alias_set = new_alias_set ();
467 /* Register variables and functions with the garbage collector. */
469 /* Set up function hooks. */
470 init_machine_status = alpha_init_machine_status;
472 /* Tell the compiler when we're using VAX floating point. */
473 if (TARGET_FLOAT_VAX)
475 REAL_MODE_FORMAT (SFmode) = &vax_f_format;
476 REAL_MODE_FORMAT (DFmode) = &vax_g_format;
477 REAL_MODE_FORMAT (TFmode) = NULL;
481 /* Returns 1 if VALUE is a mask that contains full bytes of zero or ones. */
484 zap_mask (HOST_WIDE_INT value)
488 for (i = 0; i < HOST_BITS_PER_WIDE_INT / HOST_BITS_PER_CHAR;
490 if ((value & 0xff) != 0 && (value & 0xff) != 0xff)
496 /* Returns 1 if OP is either the constant zero or a register. If a
497 register, it must be in the proper mode unless MODE is VOIDmode. */
500 reg_or_0_operand (rtx op, enum machine_mode mode)
502 return op == CONST0_RTX (mode) || register_operand (op, mode);
505 /* Return 1 if OP is a constant in the range of 0-63 (for a shift) or
509 reg_or_6bit_operand (rtx op, enum machine_mode mode)
511 return ((GET_CODE (op) == CONST_INT
512 && (unsigned HOST_WIDE_INT) INTVAL (op) < 64)
513 || register_operand (op, mode));
517 /* Return 1 if OP is an 8-bit constant or any register. */
520 reg_or_8bit_operand (rtx op, enum machine_mode mode)
522 return ((GET_CODE (op) == CONST_INT
523 && (unsigned HOST_WIDE_INT) INTVAL (op) < 0x100)
524 || register_operand (op, mode));
527 /* Return 1 if OP is a constant or any register. */
530 reg_or_const_int_operand (rtx op, enum machine_mode mode)
532 return GET_CODE (op) == CONST_INT || register_operand (op, mode);
535 /* Return 1 if OP is an 8-bit constant. */
538 cint8_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
540 return ((GET_CODE (op) == CONST_INT
541 && (unsigned HOST_WIDE_INT) INTVAL (op) < 0x100));
544 /* Return 1 if the operand is a valid second operand to an add insn. */
547 add_operand (rtx op, enum machine_mode mode)
549 if (GET_CODE (op) == CONST_INT)
550 /* Constraints I, J, O and P are covered by K. */
551 return (CONST_OK_FOR_LETTER_P (INTVAL (op), 'K')
552 || CONST_OK_FOR_LETTER_P (INTVAL (op), 'L'));
554 return register_operand (op, mode);
557 /* Return 1 if the operand is a valid second operand to a sign-extending
561 sext_add_operand (rtx op, enum machine_mode mode)
563 if (GET_CODE (op) == CONST_INT)
564 return (CONST_OK_FOR_LETTER_P (INTVAL (op), 'I')
565 || CONST_OK_FOR_LETTER_P (INTVAL (op), 'O'));
567 return reg_not_elim_operand (op, mode);
570 /* Return 1 if OP is the constant 4 or 8. */
573 const48_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
575 return (GET_CODE (op) == CONST_INT
576 && (INTVAL (op) == 4 || INTVAL (op) == 8));
579 /* Return 1 if OP is a valid first operand to an AND insn. */
582 and_operand (rtx op, enum machine_mode mode)
584 if (GET_CODE (op) == CONST_DOUBLE && GET_MODE (op) == VOIDmode)
585 return (zap_mask (CONST_DOUBLE_LOW (op))
586 && zap_mask (CONST_DOUBLE_HIGH (op)));
588 if (GET_CODE (op) == CONST_INT)
589 return ((unsigned HOST_WIDE_INT) INTVAL (op) < 0x100
590 || (unsigned HOST_WIDE_INT) ~ INTVAL (op) < 0x100
591 || zap_mask (INTVAL (op)));
593 return register_operand (op, mode);
596 /* Return 1 if OP is a valid first operand to an IOR or XOR insn. */
599 or_operand (rtx op, enum machine_mode mode)
601 if (GET_CODE (op) == CONST_INT)
602 return ((unsigned HOST_WIDE_INT) INTVAL (op) < 0x100
603 || (unsigned HOST_WIDE_INT) ~ INTVAL (op) < 0x100);
605 return register_operand (op, mode);
608 /* Return 1 if OP is a constant that is the width, in bits, of an integral
609 mode smaller than DImode. */
612 mode_width_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
614 return (GET_CODE (op) == CONST_INT
615 && (INTVAL (op) == 8 || INTVAL (op) == 16
616 || INTVAL (op) == 32 || INTVAL (op) == 64));
619 /* Return 1 if OP is a constant that is the width of an integral machine mode
620 smaller than an integer. */
623 mode_mask_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
625 if (GET_CODE (op) == CONST_INT)
627 HOST_WIDE_INT value = INTVAL (op);
633 if (value == 0xffffffff)
638 else if (HOST_BITS_PER_WIDE_INT == 32 && GET_CODE (op) == CONST_DOUBLE)
640 if (CONST_DOUBLE_LOW (op) == 0xffffffff && CONST_DOUBLE_HIGH (op) == 0)
647 /* Return 1 if OP is a multiple of 8 less than 64. */
650 mul8_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
652 return (GET_CODE (op) == CONST_INT
653 && (unsigned HOST_WIDE_INT) INTVAL (op) < 64
654 && (INTVAL (op) & 7) == 0);
657 /* Return 1 if OP is the zero constant for MODE. */
660 const0_operand (rtx op, enum machine_mode mode)
662 return op == CONST0_RTX (mode);
665 /* Return 1 if OP is a hard floating-point register. */
668 hard_fp_register_operand (rtx op, enum machine_mode mode)
670 if (mode != VOIDmode && GET_MODE (op) != VOIDmode && mode != GET_MODE (op))
673 if (GET_CODE (op) == SUBREG)
674 op = SUBREG_REG (op);
675 return GET_CODE (op) == REG && REGNO_REG_CLASS (REGNO (op)) == FLOAT_REGS;
678 /* Return 1 if OP is a hard general register. */
681 hard_int_register_operand (rtx op, enum machine_mode mode)
683 if (mode != VOIDmode && GET_MODE (op) != VOIDmode && mode != GET_MODE (op))
686 if (GET_CODE (op) == SUBREG)
687 op = SUBREG_REG (op);
688 return GET_CODE (op) == REG && REGNO_REG_CLASS (REGNO (op)) == GENERAL_REGS;
691 /* Return 1 if OP is a register or a constant integer. */
695 reg_or_cint_operand (rtx op, enum machine_mode mode)
697 return (GET_CODE (op) == CONST_INT
698 || register_operand (op, mode));
701 /* Return 1 if OP is something that can be reloaded into a register;
702 if it is a MEM, it need not be valid. */
705 some_operand (rtx op, enum machine_mode mode)
707 if (mode != VOIDmode && GET_MODE (op) != VOIDmode && mode != GET_MODE (op))
710 switch (GET_CODE (op))
724 return some_operand (SUBREG_REG (op), VOIDmode);
733 /* Likewise, but don't accept constants. */
736 some_ni_operand (rtx op, enum machine_mode mode)
738 if (GET_MODE (op) != mode && mode != VOIDmode)
741 if (GET_CODE (op) == SUBREG)
742 op = SUBREG_REG (op);
744 return (GET_CODE (op) == REG || GET_CODE (op) == MEM);
747 /* Return 1 if OP is a valid operand for the source of a move insn. */
750 input_operand (rtx op, enum machine_mode mode)
752 if (mode != VOIDmode && GET_MODE (op) != VOIDmode && mode != GET_MODE (op))
755 if (GET_MODE_CLASS (mode) == MODE_FLOAT && GET_MODE (op) != mode)
758 switch (GET_CODE (op))
763 if (TARGET_EXPLICIT_RELOCS)
765 /* We don't split symbolic operands into something unintelligable
766 until after reload, but we do not wish non-small, non-global
767 symbolic operands to be reconstructed from their high/lo_sum
769 return (small_symbolic_operand (op, mode)
770 || global_symbolic_operand (op, mode)
771 || gotdtp_symbolic_operand (op, mode)
772 || gottp_symbolic_operand (op, mode));
775 /* This handles both the Windows/NT and OSF cases. */
776 return mode == ptr_mode || mode == DImode;
779 return (TARGET_EXPLICIT_RELOCS
780 && local_symbolic_operand (XEXP (op, 0), mode));
787 if (register_operand (op, mode))
789 /* ... fall through ... */
791 return ((TARGET_BWX || (mode != HImode && mode != QImode))
792 && general_operand (op, mode));
796 return op == CONST0_RTX (mode);
799 return mode == QImode || mode == HImode || add_operand (op, mode);
811 /* Return 1 if OP is a SYMBOL_REF for a function known to be in this
812 file, and in the same section as the current function. */
815 samegp_function_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
817 if (GET_CODE (op) != SYMBOL_REF)
820 /* Easy test for recursion. */
821 if (op == XEXP (DECL_RTL (current_function_decl), 0))
824 /* Functions that are not local can be overridden, and thus may
825 not share the same gp. */
826 if (! SYMBOL_REF_LOCAL_P (op))
829 /* If -msmall-data is in effect, assume that there is only one GP
830 for the module, and so any local symbol has this property. We
831 need explicit relocations to be able to enforce this for symbols
832 not defined in this unit of translation, however. */
833 if (TARGET_EXPLICIT_RELOCS && TARGET_SMALL_DATA)
836 /* Functions that are not external are defined in this UoT,
837 and thus must share the same gp. */
838 return ! SYMBOL_REF_EXTERNAL_P (op);
841 /* Return 1 if OP is a SYMBOL_REF for which we can make a call via bsr. */
844 direct_call_operand (rtx op, enum machine_mode mode)
846 tree op_decl, cfun_sec, op_sec;
848 /* Must share the same GP. */
849 if (!samegp_function_operand (op, mode))
852 /* If profiling is implemented via linker tricks, we can't jump
853 to the nogp alternate entry point. Note that current_function_profile
854 would not be correct, since that doesn't indicate if the target
855 function uses profiling. */
856 /* ??? TARGET_PROFILING_NEEDS_GP isn't really the right test,
857 but is approximately correct for the OSF ABIs. Don't know
858 what to do for VMS, NT, or UMK. */
859 if (!TARGET_PROFILING_NEEDS_GP && profile_flag)
862 /* Must be a function. In some cases folks create thunks in static
863 data structures and then make calls to them. If we allow the
864 direct call, we'll get an error from the linker about !samegp reloc
865 against a symbol without a .prologue directive. */
866 if (!SYMBOL_REF_FUNCTION_P (op))
869 /* Must be "near" so that the branch is assumed to reach. With
870 -msmall-text, this is assumed true of all local symbols. Since
871 we've already checked samegp, locality is already assured. */
872 if (TARGET_SMALL_TEXT)
875 /* Otherwise, a decl is "near" if it is defined in the same section. */
876 if (flag_function_sections)
879 op_decl = SYMBOL_REF_DECL (op);
880 if (DECL_ONE_ONLY (current_function_decl)
881 || (op_decl && DECL_ONE_ONLY (op_decl)))
884 cfun_sec = DECL_SECTION_NAME (current_function_decl);
885 op_sec = op_decl ? DECL_SECTION_NAME (op_decl) : NULL;
886 return ((!cfun_sec && !op_sec)
887 || (cfun_sec && op_sec
888 && strcmp (TREE_STRING_POINTER (cfun_sec),
889 TREE_STRING_POINTER (op_sec)) == 0));
892 /* Return true if OP is a LABEL_REF, or SYMBOL_REF or CONST referencing
893 a (non-tls) variable known to be defined in this file. */
896 local_symbolic_operand (rtx op, enum machine_mode mode)
898 if (mode != VOIDmode && GET_MODE (op) != VOIDmode && mode != GET_MODE (op))
901 if (GET_CODE (op) == LABEL_REF)
904 if (GET_CODE (op) == CONST
905 && GET_CODE (XEXP (op, 0)) == PLUS
906 && GET_CODE (XEXP (XEXP (op, 0), 1)) == CONST_INT)
907 op = XEXP (XEXP (op, 0), 0);
909 if (GET_CODE (op) != SYMBOL_REF)
912 return SYMBOL_REF_LOCAL_P (op) && !SYMBOL_REF_TLS_MODEL (op);
915 /* Return true if OP is a SYMBOL_REF or CONST referencing a variable
916 known to be defined in this file in the small data area. */
919 small_symbolic_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
921 if (! TARGET_SMALL_DATA)
924 if (mode != VOIDmode && GET_MODE (op) != VOIDmode && mode != GET_MODE (op))
927 if (GET_CODE (op) == CONST
928 && GET_CODE (XEXP (op, 0)) == PLUS
929 && GET_CODE (XEXP (XEXP (op, 0), 1)) == CONST_INT)
930 op = XEXP (XEXP (op, 0), 0);
932 if (GET_CODE (op) != SYMBOL_REF)
935 /* ??? There's no encode_section_info equivalent for the rtl
936 constant pool, so SYMBOL_FLAG_SMALL never gets set. */
937 if (CONSTANT_POOL_ADDRESS_P (op))
938 return GET_MODE_SIZE (get_pool_mode (op)) <= g_switch_value;
940 return (SYMBOL_REF_LOCAL_P (op)
941 && SYMBOL_REF_SMALL_P (op)
942 && SYMBOL_REF_TLS_MODEL (op) == 0);
945 /* Return true if OP is a SYMBOL_REF or CONST referencing a variable
946 not known (or known not) to be defined in this file. */
949 global_symbolic_operand (rtx op, enum machine_mode mode)
951 if (mode != VOIDmode && GET_MODE (op) != VOIDmode && mode != GET_MODE (op))
954 if (GET_CODE (op) == CONST
955 && GET_CODE (XEXP (op, 0)) == PLUS
956 && GET_CODE (XEXP (XEXP (op, 0), 1)) == CONST_INT)
957 op = XEXP (XEXP (op, 0), 0);
959 if (GET_CODE (op) != SYMBOL_REF)
962 return !SYMBOL_REF_LOCAL_P (op) && !SYMBOL_REF_TLS_MODEL (op);
965 /* Return 1 if OP is a valid operand for the MEM of a CALL insn. */
968 call_operand (rtx op, enum machine_mode mode)
973 if (GET_CODE (op) == REG)
977 /* Disallow virtual registers to cope with pathological test cases
978 such as compile/930117-1.c in which the virtual reg decomposes
979 to the frame pointer. Which is a hard reg that is not $27. */
980 return (REGNO (op) == 27 || REGNO (op) > LAST_VIRTUAL_REGISTER);
985 if (TARGET_ABI_UNICOSMK)
987 if (GET_CODE (op) == SYMBOL_REF)
993 /* Returns 1 if OP is a symbolic operand, i.e. a symbol_ref or a label_ref,
994 possibly with an offset. */
997 symbolic_operand (rtx op, enum machine_mode mode)
999 if (mode != VOIDmode && GET_MODE (op) != VOIDmode && mode != GET_MODE (op))
1001 if (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == LABEL_REF)
1003 if (GET_CODE (op) == CONST
1004 && GET_CODE (XEXP (op,0)) == PLUS
1005 && GET_CODE (XEXP (XEXP (op,0), 0)) == SYMBOL_REF
1006 && GET_CODE (XEXP (XEXP (op,0), 1)) == CONST_INT)
1011 /* Return true if OP is valid for a particular TLS relocation. */
1014 tls_symbolic_operand_1 (rtx op, enum machine_mode mode, int size, int unspec)
1016 if (mode != VOIDmode && GET_MODE (op) != VOIDmode && mode != GET_MODE (op))
1019 if (GET_CODE (op) != CONST)
1023 if (GET_CODE (op) != UNSPEC || XINT (op, 1) != unspec)
1025 op = XVECEXP (op, 0, 0);
1027 if (GET_CODE (op) != SYMBOL_REF)
1030 if (SYMBOL_REF_LOCAL_P (op))
1032 if (alpha_tls_size > size)
1041 switch (SYMBOL_REF_TLS_MODEL (op))
1043 case TLS_MODEL_LOCAL_DYNAMIC:
1044 return unspec == UNSPEC_DTPREL;
1045 case TLS_MODEL_INITIAL_EXEC:
1046 return unspec == UNSPEC_TPREL && size == 64;
1047 case TLS_MODEL_LOCAL_EXEC:
1048 return unspec == UNSPEC_TPREL;
1054 /* Return true if OP is valid for 16-bit DTP relative relocations. */
1057 dtp16_symbolic_operand (rtx op, enum machine_mode mode)
1059 return tls_symbolic_operand_1 (op, mode, 16, UNSPEC_DTPREL);
1062 /* Return true if OP is valid for 32-bit DTP relative relocations. */
1065 dtp32_symbolic_operand (rtx op, enum machine_mode mode)
1067 return tls_symbolic_operand_1 (op, mode, 32, UNSPEC_DTPREL);
1070 /* Return true if OP is valid for 64-bit DTP relative relocations. */
1073 gotdtp_symbolic_operand (rtx op, enum machine_mode mode)
1075 return tls_symbolic_operand_1 (op, mode, 64, UNSPEC_DTPREL);
1078 /* Return true if OP is valid for 16-bit TP relative relocations. */
1081 tp16_symbolic_operand (rtx op, enum machine_mode mode)
1083 return tls_symbolic_operand_1 (op, mode, 16, UNSPEC_TPREL);
1086 /* Return true if OP is valid for 32-bit TP relative relocations. */
1089 tp32_symbolic_operand (rtx op, enum machine_mode mode)
1091 return tls_symbolic_operand_1 (op, mode, 32, UNSPEC_TPREL);
1094 /* Return true if OP is valid for 64-bit TP relative relocations. */
1097 gottp_symbolic_operand (rtx op, enum machine_mode mode)
1099 return tls_symbolic_operand_1 (op, mode, 64, UNSPEC_TPREL);
1102 /* Return 1 if OP is a valid Alpha comparison operator. Here we know which
1103 comparisons are valid in which insn. */
1106 alpha_comparison_operator (rtx op, enum machine_mode mode)
1108 enum rtx_code code = GET_CODE (op);
1110 if (mode != GET_MODE (op) && mode != VOIDmode)
1113 return (code == EQ || code == LE || code == LT
1114 || code == LEU || code == LTU);
1117 /* Return 1 if OP is a valid Alpha comparison operator against zero.
1118 Here we know which comparisons are valid in which insn. */
1121 alpha_zero_comparison_operator (rtx op, enum machine_mode mode)
1123 enum rtx_code code = GET_CODE (op);
1125 if (mode != GET_MODE (op) && mode != VOIDmode)
1128 return (code == EQ || code == NE || code == LE || code == LT
1129 || code == LEU || code == LTU);
1132 /* Return 1 if OP is a valid Alpha swapped comparison operator. */
1135 alpha_swapped_comparison_operator (rtx op, enum machine_mode mode)
1137 enum rtx_code code = GET_CODE (op);
1139 if ((mode != GET_MODE (op) && mode != VOIDmode)
1140 || GET_RTX_CLASS (code) != '<')
1143 code = swap_condition (code);
1144 return (code == EQ || code == LE || code == LT
1145 || code == LEU || code == LTU);
1148 /* Return 1 if OP is a signed comparison operation. */
1151 signed_comparison_operator (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1153 enum rtx_code code = GET_CODE (op);
1155 if (mode != GET_MODE (op) && mode != VOIDmode)
1158 return (code == EQ || code == NE
1159 || code == LE || code == LT
1160 || code == GE || code == GT);
1163 /* Return 1 if OP is a valid Alpha floating point comparison operator.
1164 Here we know which comparisons are valid in which insn. */
1167 alpha_fp_comparison_operator (rtx op, enum machine_mode mode)
1169 enum rtx_code code = GET_CODE (op);
1171 if (mode != GET_MODE (op) && mode != VOIDmode)
1174 return (code == EQ || code == LE || code == LT || code == UNORDERED);
1177 /* Return 1 if this is a divide or modulus operator. */
1180 divmod_operator (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1182 enum rtx_code code = GET_CODE (op);
1184 return (code == DIV || code == MOD || code == UDIV || code == UMOD);
1187 /* Return 1 if this is a float->int conversion operator. */
1190 fix_operator (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1192 enum rtx_code code = GET_CODE (op);
1194 return (code == FIX || code == UNSIGNED_FIX);
1197 /* Return 1 if this memory address is a known aligned register plus
1198 a constant. It must be a valid address. This means that we can do
1199 this as an aligned reference plus some offset.
1201 Take into account what reload will do. */
1204 aligned_memory_operand (rtx op, enum machine_mode mode)
1208 if (reload_in_progress)
1211 if (GET_CODE (tmp) == SUBREG)
1212 tmp = SUBREG_REG (tmp);
1213 if (GET_CODE (tmp) == REG
1214 && REGNO (tmp) >= FIRST_PSEUDO_REGISTER)
1216 op = reg_equiv_memory_loc[REGNO (tmp)];
1222 if (GET_CODE (op) != MEM)
1224 if (MEM_ALIGN (op) >= 32)
1228 /* LEGITIMIZE_RELOAD_ADDRESS creates (plus (plus reg const_hi) const_lo)
1229 sorts of constructs. Dig for the real base register. */
1230 if (reload_in_progress
1231 && GET_CODE (op) == PLUS
1232 && GET_CODE (XEXP (op, 0)) == PLUS)
1233 base = XEXP (XEXP (op, 0), 0);
1236 if (! memory_address_p (mode, op))
1238 base = (GET_CODE (op) == PLUS ? XEXP (op, 0) : op);
1241 return (GET_CODE (base) == REG && REGNO_POINTER_ALIGN (REGNO (base)) >= 32);
1244 /* Similar, but return 1 if OP is a MEM which is not alignable. */
1247 unaligned_memory_operand (rtx op, enum machine_mode mode)
1251 if (reload_in_progress)
1254 if (GET_CODE (tmp) == SUBREG)
1255 tmp = SUBREG_REG (tmp);
1256 if (GET_CODE (tmp) == REG
1257 && REGNO (tmp) >= FIRST_PSEUDO_REGISTER)
1259 op = reg_equiv_memory_loc[REGNO (tmp)];
1265 if (GET_CODE (op) != MEM)
1267 if (MEM_ALIGN (op) >= 32)
1271 /* LEGITIMIZE_RELOAD_ADDRESS creates (plus (plus reg const_hi) const_lo)
1272 sorts of constructs. Dig for the real base register. */
1273 if (reload_in_progress
1274 && GET_CODE (op) == PLUS
1275 && GET_CODE (XEXP (op, 0)) == PLUS)
1276 base = XEXP (XEXP (op, 0), 0);
1279 if (! memory_address_p (mode, op))
1281 base = (GET_CODE (op) == PLUS ? XEXP (op, 0) : op);
1284 return (GET_CODE (base) == REG && REGNO_POINTER_ALIGN (REGNO (base)) < 32);
1287 /* Return 1 if OP is either a register or an unaligned memory location. */
1290 reg_or_unaligned_mem_operand (rtx op, enum machine_mode mode)
1292 return register_operand (op, mode) || unaligned_memory_operand (op, mode);
1295 /* Return 1 if OP is any memory location. During reload a pseudo matches. */
1298 any_memory_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1300 return (GET_CODE (op) == MEM
1301 || (GET_CODE (op) == SUBREG && GET_CODE (SUBREG_REG (op)) == REG)
1302 || (reload_in_progress && GET_CODE (op) == REG
1303 && REGNO (op) >= FIRST_PSEUDO_REGISTER)
1304 || (reload_in_progress && GET_CODE (op) == SUBREG
1305 && GET_CODE (SUBREG_REG (op)) == REG
1306 && REGNO (SUBREG_REG (op)) >= FIRST_PSEUDO_REGISTER));
1309 /* Returns 1 if OP is not an eliminable register.
1311 This exists to cure a pathological abort in the s8addq (et al) patterns,
1313 long foo () { long t; bar(); return (long) &t * 26107; }
1315 which run afoul of a hack in reload to cure a (presumably) similar
1316 problem with lea-type instructions on other targets. But there is
1317 one of us and many of them, so work around the problem by selectively
1318 preventing combine from making the optimization. */
1321 reg_not_elim_operand (rtx op, enum machine_mode mode)
1324 if (GET_CODE (op) == SUBREG)
1325 inner = SUBREG_REG (op);
1326 if (inner == frame_pointer_rtx || inner == arg_pointer_rtx)
1329 return register_operand (op, mode);
1332 /* Return 1 is OP is a memory location that is not a reference (using
1333 an AND) to an unaligned location. Take into account what reload
1337 normal_memory_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1339 if (reload_in_progress)
1342 if (GET_CODE (tmp) == SUBREG)
1343 tmp = SUBREG_REG (tmp);
1344 if (GET_CODE (tmp) == REG
1345 && REGNO (tmp) >= FIRST_PSEUDO_REGISTER)
1347 op = reg_equiv_memory_loc[REGNO (tmp)];
1349 /* This may not have been assigned an equivalent address if it will
1350 be eliminated. In that case, it doesn't matter what we do. */
1356 return GET_CODE (op) == MEM && GET_CODE (XEXP (op, 0)) != AND;
1359 /* Accept a register, but not a subreg of any kind. This allows us to
1360 avoid pathological cases in reload wrt data movement common in
1361 int->fp conversion. */
1364 reg_no_subreg_operand (rtx op, enum machine_mode mode)
1366 if (GET_CODE (op) != REG)
1368 return register_operand (op, mode);
1371 /* Recognize an addition operation that includes a constant. Used to
1372 convince reload to canonize (plus (plus reg c1) c2) during register
1376 addition_operation (rtx op, enum machine_mode mode)
1378 if (GET_MODE (op) != mode && mode != VOIDmode)
1380 if (GET_CODE (op) == PLUS
1381 && register_operand (XEXP (op, 0), mode)
1382 && GET_CODE (XEXP (op, 1)) == CONST_INT
1383 && CONST_OK_FOR_LETTER_P (INTVAL (XEXP (op, 1)), 'K'))
1388 /* Implements CONST_OK_FOR_LETTER_P. Return true if the value matches
1389 the range defined for C in [I-P]. */
1392 alpha_const_ok_for_letter_p (HOST_WIDE_INT value, int c)
1397 /* An unsigned 8 bit constant. */
1398 return (unsigned HOST_WIDE_INT) value < 0x100;
1400 /* The constant zero. */
1403 /* A signed 16 bit constant. */
1404 return (unsigned HOST_WIDE_INT) (value + 0x8000) < 0x10000;
1406 /* A shifted signed 16 bit constant appropriate for LDAH. */
1407 return ((value & 0xffff) == 0
1408 && ((value) >> 31 == -1 || value >> 31 == 0));
1410 /* A constant that can be AND'ed with using a ZAP insn. */
1411 return zap_mask (value);
1413 /* A complemented unsigned 8 bit constant. */
1414 return (unsigned HOST_WIDE_INT) (~ value) < 0x100;
1416 /* A negated unsigned 8 bit constant. */
1417 return (unsigned HOST_WIDE_INT) (- value) < 0x100;
1419 /* The constant 1, 2 or 3. */
1420 return value == 1 || value == 2 || value == 3;
1427 /* Implements CONST_DOUBLE_OK_FOR_LETTER_P. Return true if VALUE
1428 matches for C in [GH]. */
1431 alpha_const_double_ok_for_letter_p (rtx value, int c)
1436 /* The floating point zero constant. */
1437 return (GET_MODE_CLASS (GET_MODE (value)) == MODE_FLOAT
1438 && value == CONST0_RTX (GET_MODE (value)));
1441 /* A valid operand of a ZAP insn. */
1442 return (GET_MODE (value) == VOIDmode
1443 && zap_mask (CONST_DOUBLE_LOW (value))
1444 && zap_mask (CONST_DOUBLE_HIGH (value)));
1451 /* Implements CONST_DOUBLE_OK_FOR_LETTER_P. Return true if VALUE
1455 alpha_extra_constraint (rtx value, int c)
1460 return normal_memory_operand (value, VOIDmode);
1462 return direct_call_operand (value, Pmode);
1464 return (GET_CODE (value) == CONST_INT
1465 && (unsigned HOST_WIDE_INT) INTVAL (value) < 64);
1467 return GET_CODE (value) == HIGH;
1469 return TARGET_ABI_UNICOSMK && symbolic_operand (value, VOIDmode);
1471 return (GET_CODE (value) == CONST_VECTOR
1472 && value == CONST0_RTX (GET_MODE (value)));
1478 /* Return 1 if this function can directly return via $26. */
1481 direct_return (void)
1483 return (! TARGET_ABI_OPEN_VMS && ! TARGET_ABI_UNICOSMK
1485 && alpha_sa_size () == 0
1486 && get_frame_size () == 0
1487 && current_function_outgoing_args_size == 0
1488 && current_function_pretend_args_size == 0);
1491 /* Return the ADDR_VEC associated with a tablejump insn. */
1494 alpha_tablejump_addr_vec (rtx insn)
1498 tmp = JUMP_LABEL (insn);
1501 tmp = NEXT_INSN (tmp);
1504 if (GET_CODE (tmp) == JUMP_INSN
1505 && GET_CODE (PATTERN (tmp)) == ADDR_DIFF_VEC)
1506 return PATTERN (tmp);
1510 /* Return the label of the predicted edge, or CONST0_RTX if we don't know. */
1513 alpha_tablejump_best_label (rtx insn)
1515 rtx jump_table = alpha_tablejump_addr_vec (insn);
1516 rtx best_label = NULL_RTX;
1518 /* ??? Once the CFG doesn't keep getting completely rebuilt, look
1519 there for edge frequency counts from profile data. */
1523 int n_labels = XVECLEN (jump_table, 1);
1524 int best_count = -1;
1527 for (i = 0; i < n_labels; i++)
1531 for (j = i + 1; j < n_labels; j++)
1532 if (XEXP (XVECEXP (jump_table, 1, i), 0)
1533 == XEXP (XVECEXP (jump_table, 1, j), 0))
1536 if (count > best_count)
1537 best_count = count, best_label = XVECEXP (jump_table, 1, i);
1541 return best_label ? best_label : const0_rtx;
1544 /* Return the TLS model to use for SYMBOL. */
1546 static enum tls_model
1547 tls_symbolic_operand_type (rtx symbol)
1549 enum tls_model model;
1551 if (GET_CODE (symbol) != SYMBOL_REF)
1553 model = SYMBOL_REF_TLS_MODEL (symbol);
1555 /* Local-exec with a 64-bit size is the same code as initial-exec. */
1556 if (model == TLS_MODEL_LOCAL_EXEC && alpha_tls_size == 64)
1557 model = TLS_MODEL_INITIAL_EXEC;
1562 /* Return true if the function DECL will share the same GP as any
1563 function in the current unit of translation. */
1566 decl_has_samegp (tree decl)
1568 /* Functions that are not local can be overridden, and thus may
1569 not share the same gp. */
1570 if (!(*targetm.binds_local_p) (decl))
1573 /* If -msmall-data is in effect, assume that there is only one GP
1574 for the module, and so any local symbol has this property. We
1575 need explicit relocations to be able to enforce this for symbols
1576 not defined in this unit of translation, however. */
1577 if (TARGET_EXPLICIT_RELOCS && TARGET_SMALL_DATA)
1580 /* Functions that are not external are defined in this UoT. */
1581 /* ??? Irritatingly, static functions not yet emitted are still
1582 marked "external". Apply this to non-static functions only. */
1583 return !TREE_PUBLIC (decl) || !DECL_EXTERNAL (decl);
1586 /* Return true if EXP should be placed in the small data section. */
1589 alpha_in_small_data_p (tree exp)
1591 /* We want to merge strings, so we never consider them small data. */
1592 if (TREE_CODE (exp) == STRING_CST)
1595 if (TREE_CODE (exp) == VAR_DECL && DECL_SECTION_NAME (exp))
1597 const char *section = TREE_STRING_POINTER (DECL_SECTION_NAME (exp));
1598 if (strcmp (section, ".sdata") == 0
1599 || strcmp (section, ".sbss") == 0)
1604 HOST_WIDE_INT size = int_size_in_bytes (TREE_TYPE (exp));
1606 /* If this is an incomplete type with size 0, then we can't put it
1607 in sdata because it might be too big when completed. */
1608 if (size > 0 && (unsigned HOST_WIDE_INT) size <= g_switch_value)
1615 #if TARGET_ABI_OPEN_VMS
1617 alpha_linkage_symbol_p (const char *symname)
1619 int symlen = strlen (symname);
1622 return strcmp (&symname [symlen - 4], "..lk") == 0;
1627 #define LINKAGE_SYMBOL_REF_P(X) \
1628 ((GET_CODE (X) == SYMBOL_REF \
1629 && alpha_linkage_symbol_p (XSTR (X, 0))) \
1630 || (GET_CODE (X) == CONST \
1631 && GET_CODE (XEXP (X, 0)) == PLUS \
1632 && GET_CODE (XEXP (XEXP (X, 0), 0)) == SYMBOL_REF \
1633 && alpha_linkage_symbol_p (XSTR (XEXP (XEXP (X, 0), 0), 0))))
1636 /* legitimate_address_p recognizes an RTL expression that is a valid
1637 memory address for an instruction. The MODE argument is the
1638 machine mode for the MEM expression that wants to use this address.
1640 For Alpha, we have either a constant address or the sum of a
1641 register and a constant address, or just a register. For DImode,
1642 any of those forms can be surrounded with an AND that clear the
1643 low-order three bits; this is an "unaligned" access. */
1646 alpha_legitimate_address_p (enum machine_mode mode, rtx x, int strict)
1648 /* If this is an ldq_u type address, discard the outer AND. */
1650 && GET_CODE (x) == AND
1651 && GET_CODE (XEXP (x, 1)) == CONST_INT
1652 && INTVAL (XEXP (x, 1)) == -8)
1655 /* Discard non-paradoxical subregs. */
1656 if (GET_CODE (x) == SUBREG
1657 && (GET_MODE_SIZE (GET_MODE (x))
1658 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x)))))
1661 /* Unadorned general registers are valid. */
1664 ? STRICT_REG_OK_FOR_BASE_P (x)
1665 : NONSTRICT_REG_OK_FOR_BASE_P (x)))
1668 /* Constant addresses (i.e. +/- 32k) are valid. */
1669 if (CONSTANT_ADDRESS_P (x))
1672 #if TARGET_ABI_OPEN_VMS
1673 if (LINKAGE_SYMBOL_REF_P (x))
1677 /* Register plus a small constant offset is valid. */
1678 if (GET_CODE (x) == PLUS)
1680 rtx ofs = XEXP (x, 1);
1683 /* Discard non-paradoxical subregs. */
1684 if (GET_CODE (x) == SUBREG
1685 && (GET_MODE_SIZE (GET_MODE (x))
1686 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x)))))
1692 && NONSTRICT_REG_OK_FP_BASE_P (x)
1693 && GET_CODE (ofs) == CONST_INT)
1696 ? STRICT_REG_OK_FOR_BASE_P (x)
1697 : NONSTRICT_REG_OK_FOR_BASE_P (x))
1698 && CONSTANT_ADDRESS_P (ofs))
1701 else if (GET_CODE (x) == ADDRESSOF
1702 && GET_CODE (ofs) == CONST_INT)
1706 /* If we're managing explicit relocations, LO_SUM is valid, as
1707 are small data symbols. */
1708 else if (TARGET_EXPLICIT_RELOCS)
1710 if (small_symbolic_operand (x, Pmode))
1713 if (GET_CODE (x) == LO_SUM)
1715 rtx ofs = XEXP (x, 1);
1718 /* Discard non-paradoxical subregs. */
1719 if (GET_CODE (x) == SUBREG
1720 && (GET_MODE_SIZE (GET_MODE (x))
1721 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x)))))
1724 /* Must have a valid base register. */
1727 ? STRICT_REG_OK_FOR_BASE_P (x)
1728 : NONSTRICT_REG_OK_FOR_BASE_P (x))))
1731 /* The symbol must be local. */
1732 if (local_symbolic_operand (ofs, Pmode)
1733 || dtp32_symbolic_operand (ofs, Pmode)
1734 || tp32_symbolic_operand (ofs, Pmode))
1742 /* Build the SYMBOL_REF for __tls_get_addr. */
1744 static GTY(()) rtx tls_get_addr_libfunc;
1747 get_tls_get_addr (void)
1749 if (!tls_get_addr_libfunc)
1750 tls_get_addr_libfunc = init_one_libfunc ("__tls_get_addr");
1751 return tls_get_addr_libfunc;
1754 /* Try machine-dependent ways of modifying an illegitimate address
1755 to be legitimate. If we find one, return the new, valid address. */
1758 alpha_legitimize_address (rtx x, rtx scratch,
1759 enum machine_mode mode ATTRIBUTE_UNUSED)
1761 HOST_WIDE_INT addend;
1763 /* If the address is (plus reg const_int) and the CONST_INT is not a
1764 valid offset, compute the high part of the constant and add it to
1765 the register. Then our address is (plus temp low-part-const). */
1766 if (GET_CODE (x) == PLUS
1767 && GET_CODE (XEXP (x, 0)) == REG
1768 && GET_CODE (XEXP (x, 1)) == CONST_INT
1769 && ! CONSTANT_ADDRESS_P (XEXP (x, 1)))
1771 addend = INTVAL (XEXP (x, 1));
1776 /* If the address is (const (plus FOO const_int)), find the low-order
1777 part of the CONST_INT. Then load FOO plus any high-order part of the
1778 CONST_INT into a register. Our address is (plus reg low-part-const).
1779 This is done to reduce the number of GOT entries. */
1781 && GET_CODE (x) == CONST
1782 && GET_CODE (XEXP (x, 0)) == PLUS
1783 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT)
1785 addend = INTVAL (XEXP (XEXP (x, 0), 1));
1786 x = force_reg (Pmode, XEXP (XEXP (x, 0), 0));
1790 /* If we have a (plus reg const), emit the load as in (2), then add
1791 the two registers, and finally generate (plus reg low-part-const) as
1794 && GET_CODE (x) == PLUS
1795 && GET_CODE (XEXP (x, 0)) == REG
1796 && GET_CODE (XEXP (x, 1)) == CONST
1797 && GET_CODE (XEXP (XEXP (x, 1), 0)) == PLUS
1798 && GET_CODE (XEXP (XEXP (XEXP (x, 1), 0), 1)) == CONST_INT)
1800 addend = INTVAL (XEXP (XEXP (XEXP (x, 1), 0), 1));
1801 x = expand_simple_binop (Pmode, PLUS, XEXP (x, 0),
1802 XEXP (XEXP (XEXP (x, 1), 0), 0),
1803 NULL_RTX, 1, OPTAB_LIB_WIDEN);
1807 /* If this is a local symbol, split the address into HIGH/LO_SUM parts. */
1808 if (TARGET_EXPLICIT_RELOCS && symbolic_operand (x, Pmode))
1810 rtx r0, r16, eqv, tga, tp, insn, dest, seq;
1812 switch (tls_symbolic_operand_type (x))
1814 case TLS_MODEL_GLOBAL_DYNAMIC:
1817 r0 = gen_rtx_REG (Pmode, 0);
1818 r16 = gen_rtx_REG (Pmode, 16);
1819 tga = get_tls_get_addr ();
1820 dest = gen_reg_rtx (Pmode);
1821 seq = GEN_INT (alpha_next_sequence_number++);
1823 emit_insn (gen_movdi_er_tlsgd (r16, pic_offset_table_rtx, x, seq));
1824 insn = gen_call_value_osf_tlsgd (r0, tga, seq);
1825 insn = emit_call_insn (insn);
1826 CONST_OR_PURE_CALL_P (insn) = 1;
1827 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), r16);
1829 insn = get_insns ();
1832 emit_libcall_block (insn, dest, r0, x);
1835 case TLS_MODEL_LOCAL_DYNAMIC:
1838 r0 = gen_rtx_REG (Pmode, 0);
1839 r16 = gen_rtx_REG (Pmode, 16);
1840 tga = get_tls_get_addr ();
1841 scratch = gen_reg_rtx (Pmode);
1842 seq = GEN_INT (alpha_next_sequence_number++);
1844 emit_insn (gen_movdi_er_tlsldm (r16, pic_offset_table_rtx, seq));
1845 insn = gen_call_value_osf_tlsldm (r0, tga, seq);
1846 insn = emit_call_insn (insn);
1847 CONST_OR_PURE_CALL_P (insn) = 1;
1848 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), r16);
1850 insn = get_insns ();
1853 eqv = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx),
1854 UNSPEC_TLSLDM_CALL);
1855 emit_libcall_block (insn, scratch, r0, eqv);
1857 eqv = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, x), UNSPEC_DTPREL);
1858 eqv = gen_rtx_CONST (Pmode, eqv);
1860 if (alpha_tls_size == 64)
1862 dest = gen_reg_rtx (Pmode);
1863 emit_insn (gen_rtx_SET (VOIDmode, dest, eqv));
1864 emit_insn (gen_adddi3 (dest, dest, scratch));
1867 if (alpha_tls_size == 32)
1869 insn = gen_rtx_HIGH (Pmode, eqv);
1870 insn = gen_rtx_PLUS (Pmode, scratch, insn);
1871 scratch = gen_reg_rtx (Pmode);
1872 emit_insn (gen_rtx_SET (VOIDmode, scratch, insn));
1874 return gen_rtx_LO_SUM (Pmode, scratch, eqv);
1876 case TLS_MODEL_INITIAL_EXEC:
1877 eqv = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, x), UNSPEC_TPREL);
1878 eqv = gen_rtx_CONST (Pmode, eqv);
1879 tp = gen_reg_rtx (Pmode);
1880 scratch = gen_reg_rtx (Pmode);
1881 dest = gen_reg_rtx (Pmode);
1883 emit_insn (gen_load_tp (tp));
1884 emit_insn (gen_rtx_SET (VOIDmode, scratch, eqv));
1885 emit_insn (gen_adddi3 (dest, tp, scratch));
1888 case TLS_MODEL_LOCAL_EXEC:
1889 eqv = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, x), UNSPEC_TPREL);
1890 eqv = gen_rtx_CONST (Pmode, eqv);
1891 tp = gen_reg_rtx (Pmode);
1893 emit_insn (gen_load_tp (tp));
1894 if (alpha_tls_size == 32)
1896 insn = gen_rtx_HIGH (Pmode, eqv);
1897 insn = gen_rtx_PLUS (Pmode, tp, insn);
1898 tp = gen_reg_rtx (Pmode);
1899 emit_insn (gen_rtx_SET (VOIDmode, tp, insn));
1901 return gen_rtx_LO_SUM (Pmode, tp, eqv);
1904 if (local_symbolic_operand (x, Pmode))
1906 if (small_symbolic_operand (x, Pmode))
1910 if (!no_new_pseudos)
1911 scratch = gen_reg_rtx (Pmode);
1912 emit_insn (gen_rtx_SET (VOIDmode, scratch,
1913 gen_rtx_HIGH (Pmode, x)));
1914 return gen_rtx_LO_SUM (Pmode, scratch, x);
1923 HOST_WIDE_INT low, high;
1925 low = ((addend & 0xffff) ^ 0x8000) - 0x8000;
1927 high = ((addend & 0xffffffff) ^ 0x80000000) - 0x80000000;
1931 x = expand_simple_binop (Pmode, PLUS, x, GEN_INT (addend),
1932 (no_new_pseudos ? scratch : NULL_RTX),
1933 1, OPTAB_LIB_WIDEN);
1935 x = expand_simple_binop (Pmode, PLUS, x, GEN_INT (high),
1936 (no_new_pseudos ? scratch : NULL_RTX),
1937 1, OPTAB_LIB_WIDEN);
1939 return plus_constant (x, low);
1943 /* We do not allow indirect calls to be optimized into sibling calls, nor
1944 can we allow a call to a function with a different GP to be optimized
1948 alpha_function_ok_for_sibcall (tree decl, tree exp ATTRIBUTE_UNUSED)
1950 /* Can't do indirect tail calls, since we don't know if the target
1951 uses the same GP. */
1955 /* Otherwise, we can make a tail call if the target function shares
1957 return decl_has_samegp (decl);
1960 /* For TARGET_EXPLICIT_RELOCS, we don't obfuscate a SYMBOL_REF to a
1961 small symbolic operand until after reload. At which point we need
1962 to replace (mem (symbol_ref)) with (mem (lo_sum $29 symbol_ref))
1963 so that sched2 has the proper dependency information. */
1966 some_small_symbolic_operand_1 (rtx *px, void *data ATTRIBUTE_UNUSED)
1970 /* Don't re-split. */
1971 if (GET_CODE (x) == LO_SUM)
1974 return small_symbolic_operand (x, Pmode) != 0;
1978 some_small_symbolic_operand (rtx x, enum machine_mode mode ATTRIBUTE_UNUSED)
1980 return for_each_rtx (&x, some_small_symbolic_operand_1, NULL);
1984 split_small_symbolic_operand_1 (rtx *px, void *data ATTRIBUTE_UNUSED)
1988 /* Don't re-split. */
1989 if (GET_CODE (x) == LO_SUM)
1992 if (small_symbolic_operand (x, Pmode))
1994 x = gen_rtx_LO_SUM (Pmode, pic_offset_table_rtx, x);
2003 split_small_symbolic_operand (rtx x)
2006 for_each_rtx (&x, split_small_symbolic_operand_1, NULL);
2010 /* Indicate that INSN cannot be duplicated. This is true for any insn
2011 that we've marked with gpdisp relocs, since those have to stay in
2012 1-1 correspondence with one another.
2014 Technically we could copy them if we could set up a mapping from one
2015 sequence number to another, across the set of insns to be duplicated.
2016 This seems overly complicated and error-prone since interblock motion
2017 from sched-ebb could move one of the pair of insns to a different block.
2019 Also cannot allow jsr insns to be duplicated. If they throw exceptions,
2020 then they'll be in a different block from their ldgp. Which could lead
2021 the bb reorder code to think that it would be ok to copy just the block
2022 containing the call and branch to the block containing the ldgp. */
2025 alpha_cannot_copy_insn_p (rtx insn)
2027 if (!reload_completed || !TARGET_EXPLICIT_RELOCS)
2029 if (recog_memoized (insn) >= 0)
2030 return get_attr_cannot_copy (insn);
2036 /* Try a machine-dependent way of reloading an illegitimate address
2037 operand. If we find one, push the reload and return the new rtx. */
2040 alpha_legitimize_reload_address (rtx x,
2041 enum machine_mode mode ATTRIBUTE_UNUSED,
2042 int opnum, int type,
2043 int ind_levels ATTRIBUTE_UNUSED)
2045 /* We must recognize output that we have already generated ourselves. */
2046 if (GET_CODE (x) == PLUS
2047 && GET_CODE (XEXP (x, 0)) == PLUS
2048 && GET_CODE (XEXP (XEXP (x, 0), 0)) == REG
2049 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
2050 && GET_CODE (XEXP (x, 1)) == CONST_INT)
2052 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
2053 BASE_REG_CLASS, GET_MODE (x), VOIDmode, 0, 0,
2058 /* We wish to handle large displacements off a base register by
2059 splitting the addend across an ldah and the mem insn. This
2060 cuts number of extra insns needed from 3 to 1. */
2061 if (GET_CODE (x) == PLUS
2062 && GET_CODE (XEXP (x, 0)) == REG
2063 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2064 && REGNO_OK_FOR_BASE_P (REGNO (XEXP (x, 0)))
2065 && GET_CODE (XEXP (x, 1)) == CONST_INT)
2067 HOST_WIDE_INT val = INTVAL (XEXP (x, 1));
2068 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
2070 = (((val - low) & 0xffffffff) ^ 0x80000000) - 0x80000000;
2072 /* Check for 32-bit overflow. */
2073 if (high + low != val)
2076 /* Reload the high part into a base reg; leave the low part
2077 in the mem directly. */
2078 x = gen_rtx_PLUS (GET_MODE (x),
2079 gen_rtx_PLUS (GET_MODE (x), XEXP (x, 0),
2083 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
2084 BASE_REG_CLASS, GET_MODE (x), VOIDmode, 0, 0,
2092 /* Compute a (partial) cost for rtx X. Return true if the complete
2093 cost has been computed, and false if subexpressions should be
2094 scanned. In either case, *TOTAL contains the cost result. */
2097 alpha_rtx_costs (rtx x, int code, int outer_code, int *total)
2099 enum machine_mode mode = GET_MODE (x);
2100 bool float_mode_p = FLOAT_MODE_P (mode);
2104 /* If this is an 8-bit constant, return zero since it can be used
2105 nearly anywhere with no cost. If it is a valid operand for an
2106 ADD or AND, likewise return 0 if we know it will be used in that
2107 context. Otherwise, return 2 since it might be used there later.
2108 All other constants take at least two insns. */
2110 if (INTVAL (x) >= 0 && INTVAL (x) < 256)
2118 if (x == CONST0_RTX (mode))
2120 else if ((outer_code == PLUS && add_operand (x, VOIDmode))
2121 || (outer_code == AND && and_operand (x, VOIDmode)))
2123 else if (add_operand (x, VOIDmode) || and_operand (x, VOIDmode))
2126 *total = COSTS_N_INSNS (2);
2132 if (TARGET_EXPLICIT_RELOCS && small_symbolic_operand (x, VOIDmode))
2133 *total = COSTS_N_INSNS (outer_code != MEM);
2134 else if (TARGET_EXPLICIT_RELOCS && local_symbolic_operand (x, VOIDmode))
2135 *total = COSTS_N_INSNS (1 + (outer_code != MEM));
2136 else if (tls_symbolic_operand_type (x))
2137 /* Estimate of cost for call_pal rduniq. */
2138 *total = COSTS_N_INSNS (15);
2140 /* Otherwise we do a load from the GOT. */
2141 *total = COSTS_N_INSNS (alpha_memory_latency);
2147 *total = alpha_rtx_cost_data[alpha_cpu].fp_add;
2148 else if (GET_CODE (XEXP (x, 0)) == MULT
2149 && const48_operand (XEXP (XEXP (x, 0), 1), VOIDmode))
2151 *total = (rtx_cost (XEXP (XEXP (x, 0), 0), outer_code)
2152 + rtx_cost (XEXP (x, 1), outer_code) + 2);
2159 *total = alpha_rtx_cost_data[alpha_cpu].fp_mult;
2160 else if (mode == DImode)
2161 *total = alpha_rtx_cost_data[alpha_cpu].int_mult_di;
2163 *total = alpha_rtx_cost_data[alpha_cpu].int_mult_si;
2167 if (GET_CODE (XEXP (x, 1)) == CONST_INT
2168 && INTVAL (XEXP (x, 1)) <= 3)
2170 *total = COSTS_N_INSNS (1);
2177 *total = alpha_rtx_cost_data[alpha_cpu].int_shift;
2182 *total = alpha_rtx_cost_data[alpha_cpu].fp_add;
2184 *total = alpha_rtx_cost_data[alpha_cpu].int_cmov;
2192 *total = COSTS_N_INSNS (70); /* ??? */
2193 else if (mode == SFmode)
2194 *total = alpha_rtx_cost_data[alpha_cpu].fp_div_sf;
2196 *total = alpha_rtx_cost_data[alpha_cpu].fp_div_df;
2200 *total = COSTS_N_INSNS (alpha_memory_latency);
2206 *total = COSTS_N_INSNS (1);
2214 *total = COSTS_N_INSNS (1) + alpha_rtx_cost_data[alpha_cpu].int_cmov;
2220 case UNSIGNED_FLOAT:
2224 case FLOAT_TRUNCATE:
2225 *total = alpha_rtx_cost_data[alpha_cpu].fp_add;
2233 /* REF is an alignable memory location. Place an aligned SImode
2234 reference into *PALIGNED_MEM and the number of bits to shift into
2235 *PBITNUM. SCRATCH is a free register for use in reloading out
2236 of range stack slots. */
2239 get_aligned_mem (rtx ref, rtx *paligned_mem, rtx *pbitnum)
2242 HOST_WIDE_INT offset = 0;
2244 if (GET_CODE (ref) != MEM)
2247 if (reload_in_progress
2248 && ! memory_address_p (GET_MODE (ref), XEXP (ref, 0)))
2250 base = find_replacement (&XEXP (ref, 0));
2252 if (! memory_address_p (GET_MODE (ref), base))
2257 base = XEXP (ref, 0);
2260 if (GET_CODE (base) == PLUS)
2261 offset += INTVAL (XEXP (base, 1)), base = XEXP (base, 0);
2264 = widen_memory_access (ref, SImode, (offset & ~3) - offset);
2266 if (WORDS_BIG_ENDIAN)
2267 *pbitnum = GEN_INT (32 - (GET_MODE_BITSIZE (GET_MODE (ref))
2268 + (offset & 3) * 8));
2270 *pbitnum = GEN_INT ((offset & 3) * 8);
2273 /* Similar, but just get the address. Handle the two reload cases.
2274 Add EXTRA_OFFSET to the address we return. */
2277 get_unaligned_address (rtx ref, int extra_offset)
2280 HOST_WIDE_INT offset = 0;
2282 if (GET_CODE (ref) != MEM)
2285 if (reload_in_progress
2286 && ! memory_address_p (GET_MODE (ref), XEXP (ref, 0)))
2288 base = find_replacement (&XEXP (ref, 0));
2290 if (! memory_address_p (GET_MODE (ref), base))
2295 base = XEXP (ref, 0);
2298 if (GET_CODE (base) == PLUS)
2299 offset += INTVAL (XEXP (base, 1)), base = XEXP (base, 0);
2301 return plus_constant (base, offset + extra_offset);
2304 /* On the Alpha, all (non-symbolic) constants except zero go into
2305 a floating-point register via memory. Note that we cannot
2306 return anything that is not a subset of CLASS, and that some
2307 symbolic constants cannot be dropped to memory. */
2310 alpha_preferred_reload_class(rtx x, enum reg_class class)
2312 /* Zero is present in any register class. */
2313 if (x == CONST0_RTX (GET_MODE (x)))
2316 /* These sorts of constants we can easily drop to memory. */
2317 if (GET_CODE (x) == CONST_INT || GET_CODE (x) == CONST_DOUBLE)
2319 if (class == FLOAT_REGS)
2321 if (class == ALL_REGS)
2322 return GENERAL_REGS;
2326 /* All other kinds of constants should not (and in the case of HIGH
2327 cannot) be dropped to memory -- instead we use a GENERAL_REGS
2328 secondary reload. */
2330 return (class == ALL_REGS ? GENERAL_REGS : class);
2335 /* Loading and storing HImode or QImode values to and from memory
2336 usually requires a scratch register. The exceptions are loading
2337 QImode and HImode from an aligned address to a general register
2338 unless byte instructions are permitted.
2340 We also cannot load an unaligned address or a paradoxical SUBREG
2341 into an FP register.
2343 We also cannot do integral arithmetic into FP regs, as might result
2344 from register elimination into a DImode fp register. */
2347 secondary_reload_class (enum reg_class class, enum machine_mode mode,
2350 if ((mode == QImode || mode == HImode) && ! TARGET_BWX)
2352 if (GET_CODE (x) == MEM
2353 || (GET_CODE (x) == REG && REGNO (x) >= FIRST_PSEUDO_REGISTER)
2354 || (GET_CODE (x) == SUBREG
2355 && (GET_CODE (SUBREG_REG (x)) == MEM
2356 || (GET_CODE (SUBREG_REG (x)) == REG
2357 && REGNO (SUBREG_REG (x)) >= FIRST_PSEUDO_REGISTER))))
2359 if (!in || !aligned_memory_operand(x, mode))
2360 return GENERAL_REGS;
2364 if (class == FLOAT_REGS)
2366 if (GET_CODE (x) == MEM && GET_CODE (XEXP (x, 0)) == AND)
2367 return GENERAL_REGS;
2369 if (GET_CODE (x) == SUBREG
2370 && (GET_MODE_SIZE (GET_MODE (x))
2371 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x)))))
2372 return GENERAL_REGS;
2374 if (in && INTEGRAL_MODE_P (mode)
2375 && ! (memory_operand (x, mode) || x == const0_rtx))
2376 return GENERAL_REGS;
2382 /* Subfunction of the following function. Update the flags of any MEM
2383 found in part of X. */
2386 alpha_set_memflags_1 (rtx x, int in_struct_p, int volatile_p, int unchanging_p)
2390 switch (GET_CODE (x))
2396 for (i = XVECLEN (x, 0) - 1; i >= 0; i--)
2397 alpha_set_memflags_1 (XVECEXP (x, 0, i), in_struct_p, volatile_p,
2402 alpha_set_memflags_1 (PATTERN (x), in_struct_p, volatile_p,
2407 alpha_set_memflags_1 (SET_DEST (x), in_struct_p, volatile_p,
2409 alpha_set_memflags_1 (SET_SRC (x), in_struct_p, volatile_p,
2414 MEM_IN_STRUCT_P (x) = in_struct_p;
2415 MEM_VOLATILE_P (x) = volatile_p;
2416 RTX_UNCHANGING_P (x) = unchanging_p;
2417 /* Sadly, we cannot use alias sets because the extra aliasing
2418 produced by the AND interferes. Given that two-byte quantities
2419 are the only thing we would be able to differentiate anyway,
2420 there does not seem to be any point in convoluting the early
2421 out of the alias check. */
2429 /* Given INSN, which is an INSN list or the PATTERN of a single insn
2430 generated to perform a memory operation, look for any MEMs in either
2431 a SET_DEST or a SET_SRC and copy the in-struct, unchanging, and
2432 volatile flags from REF into each of the MEMs found. If REF is not
2433 a MEM, don't do anything. */
2436 alpha_set_memflags (rtx insn, rtx ref)
2438 int in_struct_p, volatile_p, unchanging_p;
2440 if (GET_CODE (ref) != MEM)
2443 in_struct_p = MEM_IN_STRUCT_P (ref);
2444 volatile_p = MEM_VOLATILE_P (ref);
2445 unchanging_p = RTX_UNCHANGING_P (ref);
2447 /* This is only called from alpha.md, after having had something
2448 generated from one of the insn patterns. So if everything is
2449 zero, the pattern is already up-to-date. */
2450 if (! in_struct_p && ! volatile_p && ! unchanging_p)
2453 alpha_set_memflags_1 (insn, in_struct_p, volatile_p, unchanging_p);
2456 /* Internal routine for alpha_emit_set_const to check for N or below insns. */
2459 alpha_emit_set_const_1 (rtx target, enum machine_mode mode,
2460 HOST_WIDE_INT c, int n)
2464 /* Use a pseudo if highly optimizing and still generating RTL. */
2466 = (flag_expensive_optimizations && !no_new_pseudos ? 0 : target);
2469 /* If this is a sign-extended 32-bit constant, we can do this in at most
2470 three insns, so do it if we have enough insns left. We always have
2471 a sign-extended 32-bit constant when compiling on a narrow machine. */
2473 if (HOST_BITS_PER_WIDE_INT != 64
2474 || c >> 31 == -1 || c >> 31 == 0)
2476 HOST_WIDE_INT low = ((c & 0xffff) ^ 0x8000) - 0x8000;
2477 HOST_WIDE_INT tmp1 = c - low;
2478 HOST_WIDE_INT high = (((tmp1 >> 16) & 0xffff) ^ 0x8000) - 0x8000;
2479 HOST_WIDE_INT extra = 0;
2481 /* If HIGH will be interpreted as negative but the constant is
2482 positive, we must adjust it to do two ldha insns. */
2484 if ((high & 0x8000) != 0 && c >= 0)
2488 high = ((tmp1 >> 16) & 0xffff) - 2 * ((tmp1 >> 16) & 0x8000);
2491 if (c == low || (low == 0 && extra == 0))
2493 /* We used to use copy_to_suggested_reg (GEN_INT (c), target, mode)
2494 but that meant that we can't handle INT_MIN on 32-bit machines
2495 (like NT/Alpha), because we recurse indefinitely through
2496 emit_move_insn to gen_movdi. So instead, since we know exactly
2497 what we want, create it explicitly. */
2500 target = gen_reg_rtx (mode);
2501 emit_insn (gen_rtx_SET (VOIDmode, target, GEN_INT (c)));
2504 else if (n >= 2 + (extra != 0))
2508 emit_insn (gen_rtx_SET (VOIDmode, target, GEN_INT (high << 16)));
2512 temp = copy_to_suggested_reg (GEN_INT (high << 16),
2515 /* As of 2002-02-23, addsi3 is only available when not optimizing.
2516 This means that if we go through expand_binop, we'll try to
2517 generate extensions, etc, which will require new pseudos, which
2518 will fail during some split phases. The SImode add patterns
2519 still exist, but are not named. So build the insns by hand. */
2524 subtarget = gen_reg_rtx (mode);
2525 insn = gen_rtx_PLUS (mode, temp, GEN_INT (extra << 16));
2526 insn = gen_rtx_SET (VOIDmode, subtarget, insn);
2532 target = gen_reg_rtx (mode);
2533 insn = gen_rtx_PLUS (mode, temp, GEN_INT (low));
2534 insn = gen_rtx_SET (VOIDmode, target, insn);
2540 /* If we couldn't do it that way, try some other methods. But if we have
2541 no instructions left, don't bother. Likewise, if this is SImode and
2542 we can't make pseudos, we can't do anything since the expand_binop
2543 and expand_unop calls will widen and try to make pseudos. */
2545 if (n == 1 || (mode == SImode && no_new_pseudos))
2548 /* Next, see if we can load a related constant and then shift and possibly
2549 negate it to get the constant we want. Try this once each increasing
2550 numbers of insns. */
2552 for (i = 1; i < n; i++)
2554 /* First, see if minus some low bits, we've an easy load of
2557 new = ((c & 0xffff) ^ 0x8000) - 0x8000;
2559 && (temp = alpha_emit_set_const (subtarget, mode, c - new, i)) != 0)
2560 return expand_binop (mode, add_optab, temp, GEN_INT (new),
2561 target, 0, OPTAB_WIDEN);
2563 /* Next try complementing. */
2564 if ((temp = alpha_emit_set_const (subtarget, mode, ~ c, i)) != 0)
2565 return expand_unop (mode, one_cmpl_optab, temp, target, 0);
2567 /* Next try to form a constant and do a left shift. We can do this
2568 if some low-order bits are zero; the exact_log2 call below tells
2569 us that information. The bits we are shifting out could be any
2570 value, but here we'll just try the 0- and sign-extended forms of
2571 the constant. To try to increase the chance of having the same
2572 constant in more than one insn, start at the highest number of
2573 bits to shift, but try all possibilities in case a ZAPNOT will
2576 if ((bits = exact_log2 (c & - c)) > 0)
2577 for (; bits > 0; bits--)
2578 if ((temp = (alpha_emit_set_const
2579 (subtarget, mode, c >> bits, i))) != 0
2580 || ((temp = (alpha_emit_set_const
2582 ((unsigned HOST_WIDE_INT) c) >> bits, i)))
2584 return expand_binop (mode, ashl_optab, temp, GEN_INT (bits),
2585 target, 0, OPTAB_WIDEN);
2587 /* Now try high-order zero bits. Here we try the shifted-in bits as
2588 all zero and all ones. Be careful to avoid shifting outside the
2589 mode and to avoid shifting outside the host wide int size. */
2590 /* On narrow hosts, don't shift a 1 into the high bit, since we'll
2591 confuse the recursive call and set all of the high 32 bits. */
2593 if ((bits = (MIN (HOST_BITS_PER_WIDE_INT, GET_MODE_SIZE (mode) * 8)
2594 - floor_log2 (c) - 1 - (HOST_BITS_PER_WIDE_INT < 64))) > 0)
2595 for (; bits > 0; bits--)
2596 if ((temp = alpha_emit_set_const (subtarget, mode,
2598 || ((temp = (alpha_emit_set_const
2600 ((c << bits) | (((HOST_WIDE_INT) 1 << bits) - 1)),
2603 return expand_binop (mode, lshr_optab, temp, GEN_INT (bits),
2604 target, 1, OPTAB_WIDEN);
2606 /* Now try high-order 1 bits. We get that with a sign-extension.
2607 But one bit isn't enough here. Be careful to avoid shifting outside
2608 the mode and to avoid shifting outside the host wide int size. */
2610 if ((bits = (MIN (HOST_BITS_PER_WIDE_INT, GET_MODE_SIZE (mode) * 8)
2611 - floor_log2 (~ c) - 2)) > 0)
2612 for (; bits > 0; bits--)
2613 if ((temp = alpha_emit_set_const (subtarget, mode,
2615 || ((temp = (alpha_emit_set_const
2617 ((c << bits) | (((HOST_WIDE_INT) 1 << bits) - 1)),
2620 return expand_binop (mode, ashr_optab, temp, GEN_INT (bits),
2621 target, 0, OPTAB_WIDEN);
2624 #if HOST_BITS_PER_WIDE_INT == 64
2625 /* Finally, see if can load a value into the target that is the same as the
2626 constant except that all bytes that are 0 are changed to be 0xff. If we
2627 can, then we can do a ZAPNOT to obtain the desired constant. */
2630 for (i = 0; i < 64; i += 8)
2631 if ((new & ((HOST_WIDE_INT) 0xff << i)) == 0)
2632 new |= (HOST_WIDE_INT) 0xff << i;
2634 /* We are only called for SImode and DImode. If this is SImode, ensure that
2635 we are sign extended to a full word. */
2638 new = ((new & 0xffffffff) ^ 0x80000000) - 0x80000000;
2640 if (new != c && new != -1
2641 && (temp = alpha_emit_set_const (subtarget, mode, new, n - 1)) != 0)
2642 return expand_binop (mode, and_optab, temp, GEN_INT (c | ~ new),
2643 target, 0, OPTAB_WIDEN);
2649 /* Try to output insns to set TARGET equal to the constant C if it can be
2650 done in less than N insns. Do all computations in MODE. Returns the place
2651 where the output has been placed if it can be done and the insns have been
2652 emitted. If it would take more than N insns, zero is returned and no
2653 insns and emitted. */
2656 alpha_emit_set_const (rtx target, enum machine_mode mode,
2657 HOST_WIDE_INT c, int n)
2660 rtx orig_target = target;
2663 /* If we can't make any pseudos, TARGET is an SImode hard register, we
2664 can't load this constant in one insn, do this in DImode. */
2665 if (no_new_pseudos && mode == SImode
2666 && GET_CODE (target) == REG && REGNO (target) < FIRST_PSEUDO_REGISTER
2667 && (result = alpha_emit_set_const_1 (target, mode, c, 1)) == 0)
2669 target = gen_lowpart (DImode, target);
2673 /* Try 1 insn, then 2, then up to N. */
2674 for (i = 1; i <= n; i++)
2676 result = alpha_emit_set_const_1 (target, mode, c, i);
2679 rtx insn = get_last_insn ();
2680 rtx set = single_set (insn);
2681 if (! CONSTANT_P (SET_SRC (set)))
2682 set_unique_reg_note (get_last_insn (), REG_EQUAL, GEN_INT (c));
2687 /* Allow for the case where we changed the mode of TARGET. */
2688 if (result == target)
2689 result = orig_target;
2694 /* Having failed to find a 3 insn sequence in alpha_emit_set_const,
2695 fall back to a straight forward decomposition. We do this to avoid
2696 exponential run times encountered when looking for longer sequences
2697 with alpha_emit_set_const. */
2700 alpha_emit_set_long_const (rtx target, HOST_WIDE_INT c1, HOST_WIDE_INT c2)
2702 HOST_WIDE_INT d1, d2, d3, d4;
2704 /* Decompose the entire word */
2705 #if HOST_BITS_PER_WIDE_INT >= 64
2706 if (c2 != -(c1 < 0))
2708 d1 = ((c1 & 0xffff) ^ 0x8000) - 0x8000;
2710 d2 = ((c1 & 0xffffffff) ^ 0x80000000) - 0x80000000;
2711 c1 = (c1 - d2) >> 32;
2712 d3 = ((c1 & 0xffff) ^ 0x8000) - 0x8000;
2714 d4 = ((c1 & 0xffffffff) ^ 0x80000000) - 0x80000000;
2718 d1 = ((c1 & 0xffff) ^ 0x8000) - 0x8000;
2720 d2 = ((c1 & 0xffffffff) ^ 0x80000000) - 0x80000000;
2724 d3 = ((c2 & 0xffff) ^ 0x8000) - 0x8000;
2726 d4 = ((c2 & 0xffffffff) ^ 0x80000000) - 0x80000000;
2731 /* Construct the high word */
2734 emit_move_insn (target, GEN_INT (d4));
2736 emit_move_insn (target, gen_rtx_PLUS (DImode, target, GEN_INT (d3)));
2739 emit_move_insn (target, GEN_INT (d3));
2741 /* Shift it into place */
2742 emit_move_insn (target, gen_rtx_ASHIFT (DImode, target, GEN_INT (32)));
2744 /* Add in the low bits. */
2746 emit_move_insn (target, gen_rtx_PLUS (DImode, target, GEN_INT (d2)));
2748 emit_move_insn (target, gen_rtx_PLUS (DImode, target, GEN_INT (d1)));
2753 /* Expand a move instruction; return true if all work is done.
2754 We don't handle non-bwx subword loads here. */
2757 alpha_expand_mov (enum machine_mode mode, rtx *operands)
2759 /* If the output is not a register, the input must be. */
2760 if (GET_CODE (operands[0]) == MEM
2761 && ! reg_or_0_operand (operands[1], mode))
2762 operands[1] = force_reg (mode, operands[1]);
2764 /* Allow legitimize_address to perform some simplifications. */
2765 if (mode == Pmode && symbolic_operand (operands[1], mode))
2769 /* With RTL inlining, at -O3, rtl is generated, stored, then actually
2770 compiled at the end of compilation. In the meantime, someone can
2771 re-encode-section-info on some symbol changing it e.g. from global
2772 to local-not-small. If this happens, we'd have emitted a plain
2773 load rather than a high+losum load and not recognize the insn.
2775 So if rtl inlining is in effect, we delay the global/not-global
2776 decision until rest_of_compilation by wrapping it in an
2778 if (TARGET_EXPLICIT_RELOCS && flag_inline_functions
2779 && rtx_equal_function_value_matters
2780 && global_symbolic_operand (operands[1], mode))
2782 emit_insn (gen_movdi_er_maybe_g (operands[0], operands[1]));
2786 tmp = alpha_legitimize_address (operands[1], operands[0], mode);
2789 if (tmp == operands[0])
2796 /* Early out for non-constants and valid constants. */
2797 if (! CONSTANT_P (operands[1]) || input_operand (operands[1], mode))
2800 /* Split large integers. */
2801 if (GET_CODE (operands[1]) == CONST_INT
2802 || GET_CODE (operands[1]) == CONST_DOUBLE)
2804 HOST_WIDE_INT i0, i1;
2805 rtx temp = NULL_RTX;
2807 if (GET_CODE (operands[1]) == CONST_INT)
2809 i0 = INTVAL (operands[1]);
2812 else if (HOST_BITS_PER_WIDE_INT >= 64)
2814 i0 = CONST_DOUBLE_LOW (operands[1]);
2819 i0 = CONST_DOUBLE_LOW (operands[1]);
2820 i1 = CONST_DOUBLE_HIGH (operands[1]);
2823 if (HOST_BITS_PER_WIDE_INT >= 64 || i1 == -(i0 < 0))
2824 temp = alpha_emit_set_const (operands[0], mode, i0, 3);
2826 if (!temp && TARGET_BUILD_CONSTANTS)
2827 temp = alpha_emit_set_long_const (operands[0], i0, i1);
2831 if (rtx_equal_p (operands[0], temp))
2838 /* Otherwise we've nothing left but to drop the thing to memory. */
2839 operands[1] = force_const_mem (mode, operands[1]);
2840 if (reload_in_progress)
2842 emit_move_insn (operands[0], XEXP (operands[1], 0));
2843 operands[1] = copy_rtx (operands[1]);
2844 XEXP (operands[1], 0) = operands[0];
2847 operands[1] = validize_mem (operands[1]);
2851 /* Expand a non-bwx QImode or HImode move instruction;
2852 return true if all work is done. */
2855 alpha_expand_mov_nobwx (enum machine_mode mode, rtx *operands)
2857 /* If the output is not a register, the input must be. */
2858 if (GET_CODE (operands[0]) == MEM)
2859 operands[1] = force_reg (mode, operands[1]);
2861 /* Handle four memory cases, unaligned and aligned for either the input
2862 or the output. The only case where we can be called during reload is
2863 for aligned loads; all other cases require temporaries. */
2865 if (GET_CODE (operands[1]) == MEM
2866 || (GET_CODE (operands[1]) == SUBREG
2867 && GET_CODE (SUBREG_REG (operands[1])) == MEM)
2868 || (reload_in_progress && GET_CODE (operands[1]) == REG
2869 && REGNO (operands[1]) >= FIRST_PSEUDO_REGISTER)
2870 || (reload_in_progress && GET_CODE (operands[1]) == SUBREG
2871 && GET_CODE (SUBREG_REG (operands[1])) == REG
2872 && REGNO (SUBREG_REG (operands[1])) >= FIRST_PSEUDO_REGISTER))
2874 if (aligned_memory_operand (operands[1], mode))
2876 if (reload_in_progress)
2878 emit_insn ((mode == QImode
2879 ? gen_reload_inqi_help
2880 : gen_reload_inhi_help)
2881 (operands[0], operands[1],
2882 gen_rtx_REG (SImode, REGNO (operands[0]))));
2886 rtx aligned_mem, bitnum;
2887 rtx scratch = gen_reg_rtx (SImode);
2891 get_aligned_mem (operands[1], &aligned_mem, &bitnum);
2893 subtarget = operands[0];
2894 if (GET_CODE (subtarget) == REG)
2895 subtarget = gen_lowpart (DImode, subtarget), copyout = false;
2897 subtarget = gen_reg_rtx (DImode), copyout = true;
2899 emit_insn ((mode == QImode
2900 ? gen_aligned_loadqi
2901 : gen_aligned_loadhi)
2902 (subtarget, aligned_mem, bitnum, scratch));
2905 emit_move_insn (operands[0], gen_lowpart (mode, subtarget));
2910 /* Don't pass these as parameters since that makes the generated
2911 code depend on parameter evaluation order which will cause
2912 bootstrap failures. */
2914 rtx temp1, temp2, seq, subtarget;
2917 temp1 = gen_reg_rtx (DImode);
2918 temp2 = gen_reg_rtx (DImode);
2920 subtarget = operands[0];
2921 if (GET_CODE (subtarget) == REG)
2922 subtarget = gen_lowpart (DImode, subtarget), copyout = false;
2924 subtarget = gen_reg_rtx (DImode), copyout = true;
2926 seq = ((mode == QImode
2927 ? gen_unaligned_loadqi
2928 : gen_unaligned_loadhi)
2929 (subtarget, get_unaligned_address (operands[1], 0),
2931 alpha_set_memflags (seq, operands[1]);
2935 emit_move_insn (operands[0], gen_lowpart (mode, subtarget));
2940 if (GET_CODE (operands[0]) == MEM
2941 || (GET_CODE (operands[0]) == SUBREG
2942 && GET_CODE (SUBREG_REG (operands[0])) == MEM)
2943 || (reload_in_progress && GET_CODE (operands[0]) == REG
2944 && REGNO (operands[0]) >= FIRST_PSEUDO_REGISTER)
2945 || (reload_in_progress && GET_CODE (operands[0]) == SUBREG
2946 && GET_CODE (SUBREG_REG (operands[0])) == REG
2947 && REGNO (operands[0]) >= FIRST_PSEUDO_REGISTER))
2949 if (aligned_memory_operand (operands[0], mode))
2951 rtx aligned_mem, bitnum;
2952 rtx temp1 = gen_reg_rtx (SImode);
2953 rtx temp2 = gen_reg_rtx (SImode);
2955 get_aligned_mem (operands[0], &aligned_mem, &bitnum);
2957 emit_insn (gen_aligned_store (aligned_mem, operands[1], bitnum,
2962 rtx temp1 = gen_reg_rtx (DImode);
2963 rtx temp2 = gen_reg_rtx (DImode);
2964 rtx temp3 = gen_reg_rtx (DImode);
2965 rtx seq = ((mode == QImode
2966 ? gen_unaligned_storeqi
2967 : gen_unaligned_storehi)
2968 (get_unaligned_address (operands[0], 0),
2969 operands[1], temp1, temp2, temp3));
2971 alpha_set_memflags (seq, operands[0]);
2980 /* Generate an unsigned DImode to FP conversion. This is the same code
2981 optabs would emit if we didn't have TFmode patterns.
2983 For SFmode, this is the only construction I've found that can pass
2984 gcc.c-torture/execute/ieee/rbug.c. No scenario that uses DFmode
2985 intermediates will work, because you'll get intermediate rounding
2986 that ruins the end result. Some of this could be fixed by turning
2987 on round-to-positive-infinity, but that requires diddling the fpsr,
2988 which kills performance. I tried turning this around and converting
2989 to a negative number, so that I could turn on /m, but either I did
2990 it wrong or there's something else cause I wound up with the exact
2991 same single-bit error. There is a branch-less form of this same code:
3002 fcmoveq $f10,$f11,$f0
3004 I'm not using it because it's the same number of instructions as
3005 this branch-full form, and it has more serialized long latency
3006 instructions on the critical path.
3008 For DFmode, we can avoid rounding errors by breaking up the word
3009 into two pieces, converting them separately, and adding them back:
3011 LC0: .long 0,0x5f800000
3016 cpyse $f11,$f31,$f10
3017 cpyse $f31,$f11,$f11
3025 This doesn't seem to be a clear-cut win over the optabs form.
3026 It probably all depends on the distribution of numbers being
3027 converted -- in the optabs form, all but high-bit-set has a
3028 much lower minimum execution time. */
3031 alpha_emit_floatuns (rtx operands[2])
3033 rtx neglab, donelab, i0, i1, f0, in, out;
3034 enum machine_mode mode;
3037 in = force_reg (DImode, operands[1]);
3038 mode = GET_MODE (out);
3039 neglab = gen_label_rtx ();
3040 donelab = gen_label_rtx ();
3041 i0 = gen_reg_rtx (DImode);
3042 i1 = gen_reg_rtx (DImode);
3043 f0 = gen_reg_rtx (mode);
3045 emit_cmp_and_jump_insns (in, const0_rtx, LT, const0_rtx, DImode, 0, neglab);
3047 emit_insn (gen_rtx_SET (VOIDmode, out, gen_rtx_FLOAT (mode, in)));
3048 emit_jump_insn (gen_jump (donelab));
3051 emit_label (neglab);
3053 emit_insn (gen_lshrdi3 (i0, in, const1_rtx));
3054 emit_insn (gen_anddi3 (i1, in, const1_rtx));
3055 emit_insn (gen_iordi3 (i0, i0, i1));
3056 emit_insn (gen_rtx_SET (VOIDmode, f0, gen_rtx_FLOAT (mode, i0)));
3057 emit_insn (gen_rtx_SET (VOIDmode, out, gen_rtx_PLUS (mode, f0, f0)));
3059 emit_label (donelab);
3062 /* Generate the comparison for a conditional branch. */
3065 alpha_emit_conditional_branch (enum rtx_code code)
3067 enum rtx_code cmp_code, branch_code;
3068 enum machine_mode cmp_mode, branch_mode = VOIDmode;
3069 rtx op0 = alpha_compare.op0, op1 = alpha_compare.op1;
3072 if (alpha_compare.fp_p && GET_MODE (op0) == TFmode)
3074 if (! TARGET_HAS_XFLOATING_LIBS)
3077 /* X_floating library comparison functions return
3081 Convert the compare against the raw return value. */
3103 op0 = alpha_emit_xfloating_compare (cmp_code, op0, op1);
3105 alpha_compare.fp_p = 0;
3108 /* The general case: fold the comparison code to the types of compares
3109 that we have, choosing the branch as necessary. */
3112 case EQ: case LE: case LT: case LEU: case LTU:
3114 /* We have these compares: */
3115 cmp_code = code, branch_code = NE;
3120 /* These must be reversed. */
3121 cmp_code = reverse_condition (code), branch_code = EQ;
3124 case GE: case GT: case GEU: case GTU:
3125 /* For FP, we swap them, for INT, we reverse them. */
3126 if (alpha_compare.fp_p)
3128 cmp_code = swap_condition (code);
3130 tem = op0, op0 = op1, op1 = tem;
3134 cmp_code = reverse_condition (code);
3143 if (alpha_compare.fp_p)
3146 if (flag_unsafe_math_optimizations)
3148 /* When we are not as concerned about non-finite values, and we
3149 are comparing against zero, we can branch directly. */
3150 if (op1 == CONST0_RTX (DFmode))
3151 cmp_code = NIL, branch_code = code;
3152 else if (op0 == CONST0_RTX (DFmode))
3154 /* Undo the swap we probably did just above. */
3155 tem = op0, op0 = op1, op1 = tem;
3156 branch_code = swap_condition (cmp_code);
3162 /* ??? We mark the branch mode to be CCmode to prevent the
3163 compare and branch from being combined, since the compare
3164 insn follows IEEE rules that the branch does not. */
3165 branch_mode = CCmode;
3172 /* The following optimizations are only for signed compares. */
3173 if (code != LEU && code != LTU && code != GEU && code != GTU)
3175 /* Whee. Compare and branch against 0 directly. */
3176 if (op1 == const0_rtx)
3177 cmp_code = NIL, branch_code = code;
3179 /* If the constants doesn't fit into an immediate, but can
3180 be generated by lda/ldah, we adjust the argument and
3181 compare against zero, so we can use beq/bne directly. */
3182 else if (GET_CODE (op1) == CONST_INT && (code == EQ || code == NE))
3184 HOST_WIDE_INT v = INTVAL (op1), n = -v;
3186 if (! CONST_OK_FOR_LETTER_P (v, 'I')
3187 && (CONST_OK_FOR_LETTER_P (n, 'K')
3188 || CONST_OK_FOR_LETTER_P (n, 'L')))
3190 cmp_code = PLUS, branch_code = code;
3196 if (!reg_or_0_operand (op0, DImode))
3197 op0 = force_reg (DImode, op0);
3198 if (cmp_code != PLUS && !reg_or_8bit_operand (op1, DImode))
3199 op1 = force_reg (DImode, op1);
3202 /* Emit an initial compare instruction, if necessary. */
3204 if (cmp_code != NIL)
3206 tem = gen_reg_rtx (cmp_mode);
3207 emit_move_insn (tem, gen_rtx_fmt_ee (cmp_code, cmp_mode, op0, op1));
3210 /* Zero the operands. */
3211 memset (&alpha_compare, 0, sizeof (alpha_compare));
3213 /* Return the branch comparison. */
3214 return gen_rtx_fmt_ee (branch_code, branch_mode, tem, CONST0_RTX (cmp_mode));
3217 /* Certain simplifications can be done to make invalid setcc operations
3218 valid. Return the final comparison, or NULL if we can't work. */
3221 alpha_emit_setcc (enum rtx_code code)
3223 enum rtx_code cmp_code;
3224 rtx op0 = alpha_compare.op0, op1 = alpha_compare.op1;
3225 int fp_p = alpha_compare.fp_p;
3228 /* Zero the operands. */
3229 memset (&alpha_compare, 0, sizeof (alpha_compare));
3231 if (fp_p && GET_MODE (op0) == TFmode)
3233 if (! TARGET_HAS_XFLOATING_LIBS)
3236 /* X_floating library comparison functions return
3240 Convert the compare against the raw return value. */
3242 if (code == UNORDERED || code == ORDERED)
3247 op0 = alpha_emit_xfloating_compare (cmp_code, op0, op1);
3251 if (code == UNORDERED)
3253 else if (code == ORDERED)
3259 if (fp_p && !TARGET_FIX)
3262 /* The general case: fold the comparison code to the types of compares
3263 that we have, choosing the branch as necessary. */
3268 case EQ: case LE: case LT: case LEU: case LTU:
3270 /* We have these compares. */
3272 cmp_code = code, code = NE;
3276 if (!fp_p && op1 == const0_rtx)
3281 cmp_code = reverse_condition (code);
3285 case GE: case GT: case GEU: case GTU:
3286 /* These normally need swapping, but for integer zero we have
3287 special patterns that recognize swapped operands. */
3288 if (!fp_p && op1 == const0_rtx)
3290 code = swap_condition (code);
3292 cmp_code = code, code = NE;
3293 tmp = op0, op0 = op1, op1 = tmp;
3302 if (!register_operand (op0, DImode))
3303 op0 = force_reg (DImode, op0);
3304 if (!reg_or_8bit_operand (op1, DImode))
3305 op1 = force_reg (DImode, op1);
3308 /* Emit an initial compare instruction, if necessary. */
3309 if (cmp_code != NIL)
3311 enum machine_mode mode = fp_p ? DFmode : DImode;
3313 tmp = gen_reg_rtx (mode);
3314 emit_insn (gen_rtx_SET (VOIDmode, tmp,
3315 gen_rtx_fmt_ee (cmp_code, mode, op0, op1)));
3317 op0 = fp_p ? gen_lowpart (DImode, tmp) : tmp;
3321 /* Return the setcc comparison. */
3322 return gen_rtx_fmt_ee (code, DImode, op0, op1);
3326 /* Rewrite a comparison against zero CMP of the form
3327 (CODE (cc0) (const_int 0)) so it can be written validly in
3328 a conditional move (if_then_else CMP ...).
3329 If both of the operands that set cc0 are nonzero we must emit
3330 an insn to perform the compare (it can't be done within
3331 the conditional move). */
3334 alpha_emit_conditional_move (rtx cmp, enum machine_mode mode)
3336 enum rtx_code code = GET_CODE (cmp);
3337 enum rtx_code cmov_code = NE;
3338 rtx op0 = alpha_compare.op0;
3339 rtx op1 = alpha_compare.op1;
3340 int fp_p = alpha_compare.fp_p;
3341 enum machine_mode cmp_mode
3342 = (GET_MODE (op0) == VOIDmode ? DImode : GET_MODE (op0));
3343 enum machine_mode cmp_op_mode = fp_p ? DFmode : DImode;
3344 enum machine_mode cmov_mode = VOIDmode;
3345 int local_fast_math = flag_unsafe_math_optimizations;
3348 /* Zero the operands. */
3349 memset (&alpha_compare, 0, sizeof (alpha_compare));
3351 if (fp_p != FLOAT_MODE_P (mode))
3353 enum rtx_code cmp_code;
3358 /* If we have fp<->int register move instructions, do a cmov by
3359 performing the comparison in fp registers, and move the
3360 zero/nonzero value to integer registers, where we can then
3361 use a normal cmov, or vice-versa. */
3365 case EQ: case LE: case LT: case LEU: case LTU:
3366 /* We have these compares. */
3367 cmp_code = code, code = NE;
3371 /* This must be reversed. */
3372 cmp_code = EQ, code = EQ;
3375 case GE: case GT: case GEU: case GTU:
3376 /* These normally need swapping, but for integer zero we have
3377 special patterns that recognize swapped operands. */
3378 if (!fp_p && op1 == const0_rtx)
3379 cmp_code = code, code = NE;
3382 cmp_code = swap_condition (code);
3384 tem = op0, op0 = op1, op1 = tem;
3392 tem = gen_reg_rtx (cmp_op_mode);
3393 emit_insn (gen_rtx_SET (VOIDmode, tem,
3394 gen_rtx_fmt_ee (cmp_code, cmp_op_mode,
3397 cmp_mode = cmp_op_mode = fp_p ? DImode : DFmode;
3398 op0 = gen_lowpart (cmp_op_mode, tem);
3399 op1 = CONST0_RTX (cmp_op_mode);
3401 local_fast_math = 1;
3404 /* We may be able to use a conditional move directly.
3405 This avoids emitting spurious compares. */
3406 if (signed_comparison_operator (cmp, VOIDmode)
3407 && (!fp_p || local_fast_math)
3408 && (op0 == CONST0_RTX (cmp_mode) || op1 == CONST0_RTX (cmp_mode)))
3409 return gen_rtx_fmt_ee (code, VOIDmode, op0, op1);
3411 /* We can't put the comparison inside the conditional move;
3412 emit a compare instruction and put that inside the
3413 conditional move. Make sure we emit only comparisons we have;
3414 swap or reverse as necessary. */
3421 case EQ: case LE: case LT: case LEU: case LTU:
3422 /* We have these compares: */
3426 /* This must be reversed. */
3427 code = reverse_condition (code);
3431 case GE: case GT: case GEU: case GTU:
3432 /* These must be swapped. */
3433 if (op1 != CONST0_RTX (cmp_mode))
3435 code = swap_condition (code);
3436 tem = op0, op0 = op1, op1 = tem;
3446 if (!reg_or_0_operand (op0, DImode))
3447 op0 = force_reg (DImode, op0);
3448 if (!reg_or_8bit_operand (op1, DImode))
3449 op1 = force_reg (DImode, op1);
3452 /* ??? We mark the branch mode to be CCmode to prevent the compare
3453 and cmov from being combined, since the compare insn follows IEEE
3454 rules that the cmov does not. */
3455 if (fp_p && !local_fast_math)
3458 tem = gen_reg_rtx (cmp_op_mode);
3459 emit_move_insn (tem, gen_rtx_fmt_ee (code, cmp_op_mode, op0, op1));
3460 return gen_rtx_fmt_ee (cmov_code, cmov_mode, tem, CONST0_RTX (cmp_op_mode));
3463 /* Simplify a conditional move of two constants into a setcc with
3464 arithmetic. This is done with a splitter since combine would
3465 just undo the work if done during code generation. It also catches
3466 cases we wouldn't have before cse. */
3469 alpha_split_conditional_move (enum rtx_code code, rtx dest, rtx cond,
3470 rtx t_rtx, rtx f_rtx)
3472 HOST_WIDE_INT t, f, diff;
3473 enum machine_mode mode;
3474 rtx target, subtarget, tmp;
3476 mode = GET_MODE (dest);
3481 if (((code == NE || code == EQ) && diff < 0)
3482 || (code == GE || code == GT))
3484 code = reverse_condition (code);
3485 diff = t, t = f, f = diff;
3489 subtarget = target = dest;
3492 target = gen_lowpart (DImode, dest);
3493 if (! no_new_pseudos)
3494 subtarget = gen_reg_rtx (DImode);
3498 /* Below, we must be careful to use copy_rtx on target and subtarget
3499 in intermediate insns, as they may be a subreg rtx, which may not
3502 if (f == 0 && exact_log2 (diff) > 0
3503 /* On EV6, we've got enough shifters to make non-arithmetic shifts
3504 viable over a longer latency cmove. On EV5, the E0 slot is a
3505 scarce resource, and on EV4 shift has the same latency as a cmove. */
3506 && (diff <= 8 || alpha_cpu == PROCESSOR_EV6))
3508 tmp = gen_rtx_fmt_ee (code, DImode, cond, const0_rtx);
3509 emit_insn (gen_rtx_SET (VOIDmode, copy_rtx (subtarget), tmp));
3511 tmp = gen_rtx_ASHIFT (DImode, copy_rtx (subtarget),
3512 GEN_INT (exact_log2 (t)));
3513 emit_insn (gen_rtx_SET (VOIDmode, target, tmp));
3515 else if (f == 0 && t == -1)
3517 tmp = gen_rtx_fmt_ee (code, DImode, cond, const0_rtx);
3518 emit_insn (gen_rtx_SET (VOIDmode, copy_rtx (subtarget), tmp));
3520 emit_insn (gen_negdi2 (target, copy_rtx (subtarget)));
3522 else if (diff == 1 || diff == 4 || diff == 8)
3526 tmp = gen_rtx_fmt_ee (code, DImode, cond, const0_rtx);
3527 emit_insn (gen_rtx_SET (VOIDmode, copy_rtx (subtarget), tmp));
3530 emit_insn (gen_adddi3 (target, copy_rtx (subtarget), GEN_INT (f)));
3533 add_op = GEN_INT (f);
3534 if (sext_add_operand (add_op, mode))
3536 tmp = gen_rtx_MULT (DImode, copy_rtx (subtarget),
3538 tmp = gen_rtx_PLUS (DImode, tmp, add_op);
3539 emit_insn (gen_rtx_SET (VOIDmode, target, tmp));
3551 /* Look up the function X_floating library function name for the
3555 alpha_lookup_xfloating_lib_func (enum rtx_code code)
3559 const enum rtx_code code;
3560 const char *const func;
3563 static const struct xfloating_op vms_xfloating_ops[] =
3565 { PLUS, "OTS$ADD_X" },
3566 { MINUS, "OTS$SUB_X" },
3567 { MULT, "OTS$MUL_X" },
3568 { DIV, "OTS$DIV_X" },
3569 { EQ, "OTS$EQL_X" },
3570 { NE, "OTS$NEQ_X" },
3571 { LT, "OTS$LSS_X" },
3572 { LE, "OTS$LEQ_X" },
3573 { GT, "OTS$GTR_X" },
3574 { GE, "OTS$GEQ_X" },
3575 { FIX, "OTS$CVTXQ" },
3576 { FLOAT, "OTS$CVTQX" },
3577 { UNSIGNED_FLOAT, "OTS$CVTQUX" },
3578 { FLOAT_EXTEND, "OTS$CVT_FLOAT_T_X" },
3579 { FLOAT_TRUNCATE, "OTS$CVT_FLOAT_X_T" },
3582 static const struct xfloating_op osf_xfloating_ops[] =
3584 { PLUS, "_OtsAddX" },
3585 { MINUS, "_OtsSubX" },
3586 { MULT, "_OtsMulX" },
3587 { DIV, "_OtsDivX" },
3594 { FIX, "_OtsCvtXQ" },
3595 { FLOAT, "_OtsCvtQX" },
3596 { UNSIGNED_FLOAT, "_OtsCvtQUX" },
3597 { FLOAT_EXTEND, "_OtsConvertFloatTX" },
3598 { FLOAT_TRUNCATE, "_OtsConvertFloatXT" },
3601 const struct xfloating_op *ops;
3602 const long n = ARRAY_SIZE (osf_xfloating_ops);
3605 /* How irritating. Nothing to key off for the table. Hardcode
3606 knowledge of the G_floating routines. */
3607 if (TARGET_FLOAT_VAX)
3609 if (TARGET_ABI_OPEN_VMS)
3611 if (code == FLOAT_EXTEND)
3612 return "OTS$CVT_FLOAT_G_X";
3613 if (code == FLOAT_TRUNCATE)
3614 return "OTS$CVT_FLOAT_X_G";
3618 if (code == FLOAT_EXTEND)
3619 return "_OtsConvertFloatGX";
3620 if (code == FLOAT_TRUNCATE)
3621 return "_OtsConvertFloatXG";
3625 if (TARGET_ABI_OPEN_VMS)
3626 ops = vms_xfloating_ops;
3628 ops = osf_xfloating_ops;
3630 for (i = 0; i < n; ++i)
3631 if (ops[i].code == code)
3637 /* Most X_floating operations take the rounding mode as an argument.
3638 Compute that here. */
3641 alpha_compute_xfloating_mode_arg (enum rtx_code code,
3642 enum alpha_fp_rounding_mode round)
3648 case ALPHA_FPRM_NORM:
3651 case ALPHA_FPRM_MINF:
3654 case ALPHA_FPRM_CHOP:
3657 case ALPHA_FPRM_DYN:
3663 /* XXX For reference, round to +inf is mode = 3. */
3666 if (code == FLOAT_TRUNCATE && alpha_fptm == ALPHA_FPTM_N)
3672 /* Emit an X_floating library function call.
3674 Note that these functions do not follow normal calling conventions:
3675 TFmode arguments are passed in two integer registers (as opposed to
3676 indirect); TFmode return values appear in R16+R17.
3678 FUNC is the function name to call.
3679 TARGET is where the output belongs.
3680 OPERANDS are the inputs.
3681 NOPERANDS is the count of inputs.
3682 EQUIV is the expression equivalent for the function.
3686 alpha_emit_xfloating_libcall (const char *func, rtx target, rtx operands[],
3687 int noperands, rtx equiv)
3689 rtx usage = NULL_RTX, tmp, reg;
3694 for (i = 0; i < noperands; ++i)
3696 switch (GET_MODE (operands[i]))
3699 reg = gen_rtx_REG (TFmode, regno);
3704 reg = gen_rtx_REG (DFmode, regno + 32);
3709 if (GET_CODE (operands[i]) != CONST_INT)
3713 reg = gen_rtx_REG (DImode, regno);
3721 emit_move_insn (reg, operands[i]);
3722 usage = alloc_EXPR_LIST (0, gen_rtx_USE (VOIDmode, reg), usage);
3725 switch (GET_MODE (target))
3728 reg = gen_rtx_REG (TFmode, 16);
3731 reg = gen_rtx_REG (DFmode, 32);
3734 reg = gen_rtx_REG (DImode, 0);
3740 tmp = gen_rtx_MEM (QImode, init_one_libfunc (func));
3741 tmp = emit_call_insn (GEN_CALL_VALUE (reg, tmp, const0_rtx,
3742 const0_rtx, const0_rtx));
3743 CALL_INSN_FUNCTION_USAGE (tmp) = usage;
3748 emit_libcall_block (tmp, target, reg, equiv);
3751 /* Emit an X_floating library function call for arithmetic (+,-,*,/). */
3754 alpha_emit_xfloating_arith (enum rtx_code code, rtx operands[])
3758 rtx out_operands[3];
3760 func = alpha_lookup_xfloating_lib_func (code);
3761 mode = alpha_compute_xfloating_mode_arg (code, alpha_fprm);
3763 out_operands[0] = operands[1];
3764 out_operands[1] = operands[2];
3765 out_operands[2] = GEN_INT (mode);
3766 alpha_emit_xfloating_libcall (func, operands[0], out_operands, 3,
3767 gen_rtx_fmt_ee (code, TFmode, operands[1],
3771 /* Emit an X_floating library function call for a comparison. */
3774 alpha_emit_xfloating_compare (enum rtx_code code, rtx op0, rtx op1)
3777 rtx out, operands[2];
3779 func = alpha_lookup_xfloating_lib_func (code);
3783 out = gen_reg_rtx (DImode);
3785 /* ??? Strange mode for equiv because what's actually returned
3786 is -1,0,1, not a proper boolean value. */
3787 alpha_emit_xfloating_libcall (func, out, operands, 2,
3788 gen_rtx_fmt_ee (code, CCmode, op0, op1));
3793 /* Emit an X_floating library function call for a conversion. */
3796 alpha_emit_xfloating_cvt (enum rtx_code orig_code, rtx operands[])
3798 int noperands = 1, mode;
3799 rtx out_operands[2];
3801 enum rtx_code code = orig_code;
3803 if (code == UNSIGNED_FIX)
3806 func = alpha_lookup_xfloating_lib_func (code);
3808 out_operands[0] = operands[1];
3813 mode = alpha_compute_xfloating_mode_arg (code, ALPHA_FPRM_CHOP);
3814 out_operands[1] = GEN_INT (mode);
3817 case FLOAT_TRUNCATE:
3818 mode = alpha_compute_xfloating_mode_arg (code, alpha_fprm);
3819 out_operands[1] = GEN_INT (mode);
3826 alpha_emit_xfloating_libcall (func, operands[0], out_operands, noperands,
3827 gen_rtx_fmt_e (orig_code,
3828 GET_MODE (operands[0]),
3832 /* Split a TFmode OP[1] into DImode OP[2,3] and likewise for
3833 OP[0] into OP[0,1]. Naturally, output operand ordering is
3837 alpha_split_tfmode_pair (rtx operands[4])
3839 if (GET_CODE (operands[1]) == REG)
3841 operands[3] = gen_rtx_REG (DImode, REGNO (operands[1]) + 1);
3842 operands[2] = gen_rtx_REG (DImode, REGNO (operands[1]));
3844 else if (GET_CODE (operands[1]) == MEM)
3846 operands[3] = adjust_address (operands[1], DImode, 8);
3847 operands[2] = adjust_address (operands[1], DImode, 0);
3849 else if (operands[1] == CONST0_RTX (TFmode))
3850 operands[2] = operands[3] = const0_rtx;
3854 if (GET_CODE (operands[0]) == REG)
3856 operands[1] = gen_rtx_REG (DImode, REGNO (operands[0]) + 1);
3857 operands[0] = gen_rtx_REG (DImode, REGNO (operands[0]));
3859 else if (GET_CODE (operands[0]) == MEM)
3861 operands[1] = adjust_address (operands[0], DImode, 8);
3862 operands[0] = adjust_address (operands[0], DImode, 0);
3868 /* Implement negtf2 or abstf2. Op0 is destination, op1 is source,
3869 op2 is a register containing the sign bit, operation is the
3870 logical operation to be performed. */
3873 alpha_split_tfmode_frobsign (rtx operands[3], rtx (*operation) (rtx, rtx, rtx))
3875 rtx high_bit = operands[2];
3879 alpha_split_tfmode_pair (operands);
3881 /* Detect three flavors of operand overlap. */
3883 if (rtx_equal_p (operands[0], operands[2]))
3885 else if (rtx_equal_p (operands[1], operands[2]))
3887 if (rtx_equal_p (operands[0], high_bit))
3894 emit_move_insn (operands[0], operands[2]);
3896 /* ??? If the destination overlaps both source tf and high_bit, then
3897 assume source tf is dead in its entirety and use the other half
3898 for a scratch register. Otherwise "scratch" is just the proper
3899 destination register. */
3900 scratch = operands[move < 2 ? 1 : 3];
3902 emit_insn ((*operation) (scratch, high_bit, operands[3]));
3906 emit_move_insn (operands[0], operands[2]);
3908 emit_move_insn (operands[1], scratch);
3912 /* Use ext[wlq][lh] as the Architecture Handbook describes for extracting
3916 word: ldq_u r1,X(r11) ldq_u r1,X(r11)
3917 ldq_u r2,X+1(r11) ldq_u r2,X+1(r11)
3918 lda r3,X(r11) lda r3,X+2(r11)
3919 extwl r1,r3,r1 extql r1,r3,r1
3920 extwh r2,r3,r2 extqh r2,r3,r2
3921 or r1.r2.r1 or r1,r2,r1
3924 long: ldq_u r1,X(r11) ldq_u r1,X(r11)
3925 ldq_u r2,X+3(r11) ldq_u r2,X+3(r11)
3926 lda r3,X(r11) lda r3,X(r11)
3927 extll r1,r3,r1 extll r1,r3,r1
3928 extlh r2,r3,r2 extlh r2,r3,r2
3929 or r1.r2.r1 addl r1,r2,r1
3931 quad: ldq_u r1,X(r11)
3940 alpha_expand_unaligned_load (rtx tgt, rtx mem, HOST_WIDE_INT size,
3941 HOST_WIDE_INT ofs, int sign)
3943 rtx meml, memh, addr, extl, exth, tmp, mema;
3944 enum machine_mode mode;
3946 meml = gen_reg_rtx (DImode);
3947 memh = gen_reg_rtx (DImode);
3948 addr = gen_reg_rtx (DImode);
3949 extl = gen_reg_rtx (DImode);
3950 exth = gen_reg_rtx (DImode);
3952 mema = XEXP (mem, 0);
3953 if (GET_CODE (mema) == LO_SUM)
3954 mema = force_reg (Pmode, mema);
3956 /* AND addresses cannot be in any alias set, since they may implicitly
3957 alias surrounding code. Ideally we'd have some alias set that
3958 covered all types except those with alignment 8 or higher. */
3960 tmp = change_address (mem, DImode,
3961 gen_rtx_AND (DImode,
3962 plus_constant (mema, ofs),
3964 set_mem_alias_set (tmp, 0);
3965 emit_move_insn (meml, tmp);
3967 tmp = change_address (mem, DImode,
3968 gen_rtx_AND (DImode,
3969 plus_constant (mema, ofs + size - 1),
3971 set_mem_alias_set (tmp, 0);
3972 emit_move_insn (memh, tmp);
3974 if (WORDS_BIG_ENDIAN && sign && (size == 2 || size == 4))
3976 emit_move_insn (addr, plus_constant (mema, -1));
3978 emit_insn (gen_extqh_be (extl, meml, addr));
3979 emit_insn (gen_extxl_be (exth, memh, GEN_INT (64), addr));
3981 addr = expand_binop (DImode, ior_optab, extl, exth, tgt, 1, OPTAB_WIDEN);
3982 addr = expand_binop (DImode, ashr_optab, addr, GEN_INT (64 - size*8),
3983 addr, 1, OPTAB_WIDEN);
3985 else if (sign && size == 2)
3987 emit_move_insn (addr, plus_constant (mema, ofs+2));
3989 emit_insn (gen_extxl_le (extl, meml, GEN_INT (64), addr));
3990 emit_insn (gen_extqh_le (exth, memh, addr));
3992 /* We must use tgt here for the target. Alpha-vms port fails if we use
3993 addr for the target, because addr is marked as a pointer and combine
3994 knows that pointers are always sign-extended 32 bit values. */
3995 addr = expand_binop (DImode, ior_optab, extl, exth, tgt, 1, OPTAB_WIDEN);
3996 addr = expand_binop (DImode, ashr_optab, addr, GEN_INT (48),
3997 addr, 1, OPTAB_WIDEN);
4001 if (WORDS_BIG_ENDIAN)
4003 emit_move_insn (addr, plus_constant (mema, ofs+size-1));
4007 emit_insn (gen_extwh_be (extl, meml, addr));
4012 emit_insn (gen_extlh_be (extl, meml, addr));
4017 emit_insn (gen_extqh_be (extl, meml, addr));
4024 emit_insn (gen_extxl_be (exth, memh, GEN_INT (size*8), addr));
4028 emit_move_insn (addr, plus_constant (mema, ofs));
4029 emit_insn (gen_extxl_le (extl, meml, GEN_INT (size*8), addr));
4033 emit_insn (gen_extwh_le (exth, memh, addr));
4038 emit_insn (gen_extlh_le (exth, memh, addr));
4043 emit_insn (gen_extqh_le (exth, memh, addr));
4052 addr = expand_binop (mode, ior_optab, gen_lowpart (mode, extl),
4053 gen_lowpart (mode, exth), gen_lowpart (mode, tgt),
4058 emit_move_insn (tgt, gen_lowpart(GET_MODE (tgt), addr));
4061 /* Similarly, use ins and msk instructions to perform unaligned stores. */
4064 alpha_expand_unaligned_store (rtx dst, rtx src,
4065 HOST_WIDE_INT size, HOST_WIDE_INT ofs)
4067 rtx dstl, dsth, addr, insl, insh, meml, memh, dsta;
4069 dstl = gen_reg_rtx (DImode);
4070 dsth = gen_reg_rtx (DImode);
4071 insl = gen_reg_rtx (DImode);
4072 insh = gen_reg_rtx (DImode);
4074 dsta = XEXP (dst, 0);
4075 if (GET_CODE (dsta) == LO_SUM)
4076 dsta = force_reg (Pmode, dsta);
4078 /* AND addresses cannot be in any alias set, since they may implicitly
4079 alias surrounding code. Ideally we'd have some alias set that
4080 covered all types except those with alignment 8 or higher. */
4082 meml = change_address (dst, DImode,
4083 gen_rtx_AND (DImode,
4084 plus_constant (dsta, ofs),
4086 set_mem_alias_set (meml, 0);
4088 memh = change_address (dst, DImode,
4089 gen_rtx_AND (DImode,
4090 plus_constant (dsta, ofs + size - 1),
4092 set_mem_alias_set (memh, 0);
4094 emit_move_insn (dsth, memh);
4095 emit_move_insn (dstl, meml);
4096 if (WORDS_BIG_ENDIAN)
4098 addr = copy_addr_to_reg (plus_constant (dsta, ofs+size-1));
4100 if (src != const0_rtx)
4105 emit_insn (gen_inswl_be (insh, gen_lowpart (HImode,src), addr));
4108 emit_insn (gen_insll_be (insh, gen_lowpart (SImode,src), addr));
4111 emit_insn (gen_insql_be (insh, gen_lowpart (DImode,src), addr));
4114 emit_insn (gen_insxh (insl, gen_lowpart (DImode, src),
4115 GEN_INT (size*8), addr));
4121 emit_insn (gen_mskxl_be (dsth, dsth, GEN_INT (0xffff), addr));
4125 rtx msk = immed_double_const (0xffffffff, 0, DImode);
4126 emit_insn (gen_mskxl_be (dsth, dsth, msk, addr));
4130 emit_insn (gen_mskxl_be (dsth, dsth, constm1_rtx, addr));
4134 emit_insn (gen_mskxh (dstl, dstl, GEN_INT (size*8), addr));
4138 addr = copy_addr_to_reg (plus_constant (dsta, ofs));
4140 if (src != const0_rtx)
4142 emit_insn (gen_insxh (insh, gen_lowpart (DImode, src),
4143 GEN_INT (size*8), addr));
4148 emit_insn (gen_inswl_le (insl, gen_lowpart (HImode, src), addr));
4151 emit_insn (gen_insll_le (insl, gen_lowpart (SImode, src), addr));
4154 emit_insn (gen_insql_le (insl, src, addr));
4159 emit_insn (gen_mskxh (dsth, dsth, GEN_INT (size*8), addr));
4164 emit_insn (gen_mskxl_le (dstl, dstl, GEN_INT (0xffff), addr));
4168 rtx msk = immed_double_const (0xffffffff, 0, DImode);
4169 emit_insn (gen_mskxl_le (dstl, dstl, msk, addr));
4173 emit_insn (gen_mskxl_le (dstl, dstl, constm1_rtx, addr));
4178 if (src != const0_rtx)
4180 dsth = expand_binop (DImode, ior_optab, insh, dsth, dsth, 0, OPTAB_WIDEN);
4181 dstl = expand_binop (DImode, ior_optab, insl, dstl, dstl, 0, OPTAB_WIDEN);
4184 if (WORDS_BIG_ENDIAN)
4186 emit_move_insn (meml, dstl);
4187 emit_move_insn (memh, dsth);
4191 /* Must store high before low for degenerate case of aligned. */
4192 emit_move_insn (memh, dsth);
4193 emit_move_insn (meml, dstl);
4197 /* The block move code tries to maximize speed by separating loads and
4198 stores at the expense of register pressure: we load all of the data
4199 before we store it back out. There are two secondary effects worth
4200 mentioning, that this speeds copying to/from aligned and unaligned
4201 buffers, and that it makes the code significantly easier to write. */
4203 #define MAX_MOVE_WORDS 8
4205 /* Load an integral number of consecutive unaligned quadwords. */
4208 alpha_expand_unaligned_load_words (rtx *out_regs, rtx smem,
4209 HOST_WIDE_INT words, HOST_WIDE_INT ofs)
4211 rtx const im8 = GEN_INT (-8);
4212 rtx const i64 = GEN_INT (64);
4213 rtx ext_tmps[MAX_MOVE_WORDS], data_regs[MAX_MOVE_WORDS+1];
4214 rtx sreg, areg, tmp, smema;
4217 smema = XEXP (smem, 0);
4218 if (GET_CODE (smema) == LO_SUM)
4219 smema = force_reg (Pmode, smema);
4221 /* Generate all the tmp registers we need. */
4222 for (i = 0; i < words; ++i)
4224 data_regs[i] = out_regs[i];
4225 ext_tmps[i] = gen_reg_rtx (DImode);
4227 data_regs[words] = gen_reg_rtx (DImode);
4230 smem = adjust_address (smem, GET_MODE (smem), ofs);
4232 /* Load up all of the source data. */
4233 for (i = 0; i < words; ++i)
4235 tmp = change_address (smem, DImode,
4236 gen_rtx_AND (DImode,
4237 plus_constant (smema, 8*i),
4239 set_mem_alias_set (tmp, 0);
4240 emit_move_insn (data_regs[i], tmp);
4243 tmp = change_address (smem, DImode,
4244 gen_rtx_AND (DImode,
4245 plus_constant (smema, 8*words - 1),
4247 set_mem_alias_set (tmp, 0);
4248 emit_move_insn (data_regs[words], tmp);
4250 /* Extract the half-word fragments. Unfortunately DEC decided to make
4251 extxh with offset zero a noop instead of zeroing the register, so
4252 we must take care of that edge condition ourselves with cmov. */
4254 sreg = copy_addr_to_reg (smema);
4255 areg = expand_binop (DImode, and_optab, sreg, GEN_INT (7), NULL,
4257 if (WORDS_BIG_ENDIAN)
4258 emit_move_insn (sreg, plus_constant (sreg, 7));
4259 for (i = 0; i < words; ++i)
4261 if (WORDS_BIG_ENDIAN)
4263 emit_insn (gen_extqh_be (data_regs[i], data_regs[i], sreg));
4264 emit_insn (gen_extxl_be (ext_tmps[i], data_regs[i+1], i64, sreg));
4268 emit_insn (gen_extxl_le (data_regs[i], data_regs[i], i64, sreg));
4269 emit_insn (gen_extqh_le (ext_tmps[i], data_regs[i+1], sreg));
4271 emit_insn (gen_rtx_SET (VOIDmode, ext_tmps[i],
4272 gen_rtx_IF_THEN_ELSE (DImode,
4273 gen_rtx_EQ (DImode, areg,
4275 const0_rtx, ext_tmps[i])));
4278 /* Merge the half-words into whole words. */
4279 for (i = 0; i < words; ++i)
4281 out_regs[i] = expand_binop (DImode, ior_optab, data_regs[i],
4282 ext_tmps[i], data_regs[i], 1, OPTAB_WIDEN);
4286 /* Store an integral number of consecutive unaligned quadwords. DATA_REGS
4287 may be NULL to store zeros. */
4290 alpha_expand_unaligned_store_words (rtx *data_regs, rtx dmem,
4291 HOST_WIDE_INT words, HOST_WIDE_INT ofs)
4293 rtx const im8 = GEN_INT (-8);
4294 rtx const i64 = GEN_INT (64);
4295 rtx ins_tmps[MAX_MOVE_WORDS];
4296 rtx st_tmp_1, st_tmp_2, dreg;
4297 rtx st_addr_1, st_addr_2, dmema;
4300 dmema = XEXP (dmem, 0);
4301 if (GET_CODE (dmema) == LO_SUM)
4302 dmema = force_reg (Pmode, dmema);
4304 /* Generate all the tmp registers we need. */
4305 if (data_regs != NULL)
4306 for (i = 0; i < words; ++i)
4307 ins_tmps[i] = gen_reg_rtx(DImode);
4308 st_tmp_1 = gen_reg_rtx(DImode);
4309 st_tmp_2 = gen_reg_rtx(DImode);
4312 dmem = adjust_address (dmem, GET_MODE (dmem), ofs);
4314 st_addr_2 = change_address (dmem, DImode,
4315 gen_rtx_AND (DImode,
4316 plus_constant (dmema, words*8 - 1),
4318 set_mem_alias_set (st_addr_2, 0);
4320 st_addr_1 = change_address (dmem, DImode,
4321 gen_rtx_AND (DImode, dmema, im8));
4322 set_mem_alias_set (st_addr_1, 0);
4324 /* Load up the destination end bits. */
4325 emit_move_insn (st_tmp_2, st_addr_2);
4326 emit_move_insn (st_tmp_1, st_addr_1);
4328 /* Shift the input data into place. */
4329 dreg = copy_addr_to_reg (dmema);
4330 if (WORDS_BIG_ENDIAN)
4331 emit_move_insn (dreg, plus_constant (dreg, 7));
4332 if (data_regs != NULL)
4334 for (i = words-1; i >= 0; --i)
4336 if (WORDS_BIG_ENDIAN)
4338 emit_insn (gen_insql_be (ins_tmps[i], data_regs[i], dreg));
4339 emit_insn (gen_insxh (data_regs[i], data_regs[i], i64, dreg));
4343 emit_insn (gen_insxh (ins_tmps[i], data_regs[i], i64, dreg));
4344 emit_insn (gen_insql_le (data_regs[i], data_regs[i], dreg));
4347 for (i = words-1; i > 0; --i)
4349 ins_tmps[i-1] = expand_binop (DImode, ior_optab, data_regs[i],
4350 ins_tmps[i-1], ins_tmps[i-1], 1,
4355 /* Split and merge the ends with the destination data. */
4356 if (WORDS_BIG_ENDIAN)
4358 emit_insn (gen_mskxl_be (st_tmp_2, st_tmp_2, constm1_rtx, dreg));
4359 emit_insn (gen_mskxh (st_tmp_1, st_tmp_1, i64, dreg));
4363 emit_insn (gen_mskxh (st_tmp_2, st_tmp_2, i64, dreg));
4364 emit_insn (gen_mskxl_le (st_tmp_1, st_tmp_1, constm1_rtx, dreg));
4367 if (data_regs != NULL)
4369 st_tmp_2 = expand_binop (DImode, ior_optab, st_tmp_2, ins_tmps[words-1],
4370 st_tmp_2, 1, OPTAB_WIDEN);
4371 st_tmp_1 = expand_binop (DImode, ior_optab, st_tmp_1, data_regs[0],
4372 st_tmp_1, 1, OPTAB_WIDEN);
4376 if (WORDS_BIG_ENDIAN)
4377 emit_move_insn (st_addr_1, st_tmp_1);
4379 emit_move_insn (st_addr_2, st_tmp_2);
4380 for (i = words-1; i > 0; --i)
4382 rtx tmp = change_address (dmem, DImode,
4383 gen_rtx_AND (DImode,
4384 plus_constant(dmema,
4385 WORDS_BIG_ENDIAN ? i*8-1 : i*8),
4387 set_mem_alias_set (tmp, 0);
4388 emit_move_insn (tmp, data_regs ? ins_tmps[i-1] : const0_rtx);
4390 if (WORDS_BIG_ENDIAN)
4391 emit_move_insn (st_addr_2, st_tmp_2);
4393 emit_move_insn (st_addr_1, st_tmp_1);
4397 /* Expand string/block move operations.
4399 operands[0] is the pointer to the destination.
4400 operands[1] is the pointer to the source.
4401 operands[2] is the number of bytes to move.
4402 operands[3] is the alignment. */
4405 alpha_expand_block_move (rtx operands[])
4407 rtx bytes_rtx = operands[2];
4408 rtx align_rtx = operands[3];
4409 HOST_WIDE_INT orig_bytes = INTVAL (bytes_rtx);
4410 HOST_WIDE_INT bytes = orig_bytes;
4411 HOST_WIDE_INT src_align = INTVAL (align_rtx) * BITS_PER_UNIT;
4412 HOST_WIDE_INT dst_align = src_align;
4413 rtx orig_src = operands[1];
4414 rtx orig_dst = operands[0];
4415 rtx data_regs[2 * MAX_MOVE_WORDS + 16];
4417 unsigned int i, words, ofs, nregs = 0;
4419 if (orig_bytes <= 0)
4421 else if (orig_bytes > MAX_MOVE_WORDS * UNITS_PER_WORD)
4424 /* Look for additional alignment information from recorded register info. */
4426 tmp = XEXP (orig_src, 0);
4427 if (GET_CODE (tmp) == REG)
4428 src_align = MAX (src_align, REGNO_POINTER_ALIGN (REGNO (tmp)));
4429 else if (GET_CODE (tmp) == PLUS
4430 && GET_CODE (XEXP (tmp, 0)) == REG
4431 && GET_CODE (XEXP (tmp, 1)) == CONST_INT)
4433 unsigned HOST_WIDE_INT c = INTVAL (XEXP (tmp, 1));
4434 unsigned int a = REGNO_POINTER_ALIGN (REGNO (XEXP (tmp, 0)));
4438 if (a >= 64 && c % 8 == 0)
4440 else if (a >= 32 && c % 4 == 0)
4442 else if (a >= 16 && c % 2 == 0)
4447 tmp = XEXP (orig_dst, 0);
4448 if (GET_CODE (tmp) == REG)
4449 dst_align = MAX (dst_align, REGNO_POINTER_ALIGN (REGNO (tmp)));
4450 else if (GET_CODE (tmp) == PLUS
4451 && GET_CODE (XEXP (tmp, 0)) == REG
4452 && GET_CODE (XEXP (tmp, 1)) == CONST_INT)
4454 unsigned HOST_WIDE_INT c = INTVAL (XEXP (tmp, 1));
4455 unsigned int a = REGNO_POINTER_ALIGN (REGNO (XEXP (tmp, 0)));
4459 if (a >= 64 && c % 8 == 0)
4461 else if (a >= 32 && c % 4 == 0)
4463 else if (a >= 16 && c % 2 == 0)
4468 /* Load the entire block into registers. */
4469 if (GET_CODE (XEXP (orig_src, 0)) == ADDRESSOF)
4471 enum machine_mode mode;
4473 tmp = XEXP (XEXP (orig_src, 0), 0);
4475 /* Don't use the existing register if we're reading more than
4476 is held in the register. Nor if there is not a mode that
4477 handles the exact size. */
4478 mode = mode_for_size (bytes * BITS_PER_UNIT, MODE_INT, 1);
4479 if (GET_CODE (tmp) == REG
4481 && GET_MODE_SIZE (GET_MODE (tmp)) >= bytes)
4485 data_regs[nregs] = gen_lowpart (DImode, tmp);
4486 data_regs[nregs + 1] = gen_highpart (DImode, tmp);
4490 data_regs[nregs++] = gen_lowpart (mode, tmp);
4495 /* No appropriate mode; fall back on memory. */
4496 orig_src = replace_equiv_address (orig_src,
4497 copy_addr_to_reg (XEXP (orig_src, 0)));
4498 src_align = GET_MODE_BITSIZE (GET_MODE (tmp));
4502 if (src_align >= 64 && bytes >= 8)
4506 for (i = 0; i < words; ++i)
4507 data_regs[nregs + i] = gen_reg_rtx (DImode);
4509 for (i = 0; i < words; ++i)
4510 emit_move_insn (data_regs[nregs + i],
4511 adjust_address (orig_src, DImode, ofs + i * 8));
4518 if (src_align >= 32 && bytes >= 4)
4522 for (i = 0; i < words; ++i)
4523 data_regs[nregs + i] = gen_reg_rtx (SImode);
4525 for (i = 0; i < words; ++i)
4526 emit_move_insn (data_regs[nregs + i],
4527 adjust_address (orig_src, SImode, ofs + i * 4));
4538 for (i = 0; i < words+1; ++i)
4539 data_regs[nregs + i] = gen_reg_rtx (DImode);
4541 alpha_expand_unaligned_load_words (data_regs + nregs, orig_src,
4549 if (! TARGET_BWX && bytes >= 4)
4551 data_regs[nregs++] = tmp = gen_reg_rtx (SImode);
4552 alpha_expand_unaligned_load (tmp, orig_src, 4, ofs, 0);
4559 if (src_align >= 16)
4562 data_regs[nregs++] = tmp = gen_reg_rtx (HImode);
4563 emit_move_insn (tmp, adjust_address (orig_src, HImode, ofs));
4566 } while (bytes >= 2);
4568 else if (! TARGET_BWX)
4570 data_regs[nregs++] = tmp = gen_reg_rtx (HImode);
4571 alpha_expand_unaligned_load (tmp, orig_src, 2, ofs, 0);
4579 data_regs[nregs++] = tmp = gen_reg_rtx (QImode);
4580 emit_move_insn (tmp, adjust_address (orig_src, QImode, ofs));
4587 if (nregs > ARRAY_SIZE (data_regs))
4590 /* Now save it back out again. */
4594 if (GET_CODE (XEXP (orig_dst, 0)) == ADDRESSOF)
4596 enum machine_mode mode;
4597 tmp = XEXP (XEXP (orig_dst, 0), 0);
4599 mode = mode_for_size (orig_bytes * BITS_PER_UNIT, MODE_INT, 1);
4600 if (GET_CODE (tmp) == REG && GET_MODE (tmp) == mode)
4604 emit_move_insn (tmp, data_regs[0]);
4609 else if (nregs == 2 && mode == TImode)
4611 /* Undo the subregging done above when copying between
4612 two TImode registers. */
4613 if (GET_CODE (data_regs[0]) == SUBREG
4614 && GET_MODE (SUBREG_REG (data_regs[0])) == TImode)
4615 emit_move_insn (tmp, SUBREG_REG (data_regs[0]));
4621 emit_move_insn (gen_lowpart (DImode, tmp), data_regs[0]);
4622 emit_move_insn (gen_highpart (DImode, tmp), data_regs[1]);
4626 emit_no_conflict_block (seq, tmp, data_regs[0],
4627 data_regs[1], NULL_RTX);
4635 /* ??? If nregs > 1, consider reconstructing the word in regs. */
4636 /* ??? Optimize mode < dst_mode with strict_low_part. */
4638 /* No appropriate mode; fall back on memory. We can speed things
4639 up by recognizing extra alignment information. */
4640 orig_dst = replace_equiv_address (orig_dst,
4641 copy_addr_to_reg (XEXP (orig_dst, 0)));
4642 dst_align = GET_MODE_BITSIZE (GET_MODE (tmp));
4645 /* Write out the data in whatever chunks reading the source allowed. */
4646 if (dst_align >= 64)
4648 while (i < nregs && GET_MODE (data_regs[i]) == DImode)
4650 emit_move_insn (adjust_address (orig_dst, DImode, ofs),
4657 if (dst_align >= 32)
4659 /* If the source has remaining DImode regs, write them out in
4661 while (i < nregs && GET_MODE (data_regs[i]) == DImode)
4663 tmp = expand_binop (DImode, lshr_optab, data_regs[i], GEN_INT (32),
4664 NULL_RTX, 1, OPTAB_WIDEN);
4666 emit_move_insn (adjust_address (orig_dst, SImode, ofs),
4667 gen_lowpart (SImode, data_regs[i]));
4668 emit_move_insn (adjust_address (orig_dst, SImode, ofs + 4),
4669 gen_lowpart (SImode, tmp));
4674 while (i < nregs && GET_MODE (data_regs[i]) == SImode)
4676 emit_move_insn (adjust_address (orig_dst, SImode, ofs),
4683 if (i < nregs && GET_MODE (data_regs[i]) == DImode)
4685 /* Write out a remaining block of words using unaligned methods. */
4687 for (words = 1; i + words < nregs; words++)
4688 if (GET_MODE (data_regs[i + words]) != DImode)
4692 alpha_expand_unaligned_store (orig_dst, data_regs[i], 8, ofs);
4694 alpha_expand_unaligned_store_words (data_regs + i, orig_dst,
4701 /* Due to the above, this won't be aligned. */
4702 /* ??? If we have more than one of these, consider constructing full
4703 words in registers and using alpha_expand_unaligned_store_words. */
4704 while (i < nregs && GET_MODE (data_regs[i]) == SImode)
4706 alpha_expand_unaligned_store (orig_dst, data_regs[i], 4, ofs);
4711 if (dst_align >= 16)
4712 while (i < nregs && GET_MODE (data_regs[i]) == HImode)
4714 emit_move_insn (adjust_address (orig_dst, HImode, ofs), data_regs[i]);
4719 while (i < nregs && GET_MODE (data_regs[i]) == HImode)
4721 alpha_expand_unaligned_store (orig_dst, data_regs[i], 2, ofs);
4726 while (i < nregs && GET_MODE (data_regs[i]) == QImode)
4728 emit_move_insn (adjust_address (orig_dst, QImode, ofs), data_regs[i]);
4742 alpha_expand_block_clear (rtx operands[])
4744 rtx bytes_rtx = operands[1];
4745 rtx align_rtx = operands[2];
4746 HOST_WIDE_INT orig_bytes = INTVAL (bytes_rtx);
4747 HOST_WIDE_INT bytes = orig_bytes;
4748 HOST_WIDE_INT align = INTVAL (align_rtx) * BITS_PER_UNIT;
4749 HOST_WIDE_INT alignofs = 0;
4750 rtx orig_dst = operands[0];
4752 int i, words, ofs = 0;
4754 if (orig_bytes <= 0)
4756 if (orig_bytes > MAX_MOVE_WORDS * UNITS_PER_WORD)
4759 /* Look for stricter alignment. */
4760 tmp = XEXP (orig_dst, 0);
4761 if (GET_CODE (tmp) == REG)
4762 align = MAX (align, REGNO_POINTER_ALIGN (REGNO (tmp)));
4763 else if (GET_CODE (tmp) == PLUS
4764 && GET_CODE (XEXP (tmp, 0)) == REG
4765 && GET_CODE (XEXP (tmp, 1)) == CONST_INT)
4767 HOST_WIDE_INT c = INTVAL (XEXP (tmp, 1));
4768 int a = REGNO_POINTER_ALIGN (REGNO (XEXP (tmp, 0)));
4773 align = a, alignofs = 8 - c % 8;
4775 align = a, alignofs = 4 - c % 4;
4777 align = a, alignofs = 2 - c % 2;
4780 else if (GET_CODE (tmp) == ADDRESSOF)
4782 enum machine_mode mode;
4784 mode = mode_for_size (bytes * BITS_PER_UNIT, MODE_INT, 1);
4785 if (GET_MODE (XEXP (tmp, 0)) == mode)
4787 emit_move_insn (XEXP (tmp, 0), const0_rtx);
4791 /* No appropriate mode; fall back on memory. */
4792 orig_dst = replace_equiv_address (orig_dst, copy_addr_to_reg (tmp));
4793 align = GET_MODE_BITSIZE (GET_MODE (XEXP (tmp, 0)));
4796 /* Handle an unaligned prefix first. */
4800 #if HOST_BITS_PER_WIDE_INT >= 64
4801 /* Given that alignofs is bounded by align, the only time BWX could
4802 generate three stores is for a 7 byte fill. Prefer two individual
4803 stores over a load/mask/store sequence. */
4804 if ((!TARGET_BWX || alignofs == 7)
4806 && !(alignofs == 4 && bytes >= 4))
4808 enum machine_mode mode = (align >= 64 ? DImode : SImode);
4809 int inv_alignofs = (align >= 64 ? 8 : 4) - alignofs;
4813 mem = adjust_address (orig_dst, mode, ofs - inv_alignofs);
4814 set_mem_alias_set (mem, 0);
4816 mask = ~(~(HOST_WIDE_INT)0 << (inv_alignofs * 8));
4817 if (bytes < alignofs)
4819 mask |= ~(HOST_WIDE_INT)0 << ((inv_alignofs + bytes) * 8);
4830 tmp = expand_binop (mode, and_optab, mem, GEN_INT (mask),
4831 NULL_RTX, 1, OPTAB_WIDEN);
4833 emit_move_insn (mem, tmp);
4837 if (TARGET_BWX && (alignofs & 1) && bytes >= 1)
4839 emit_move_insn (adjust_address (orig_dst, QImode, ofs), const0_rtx);
4844 if (TARGET_BWX && align >= 16 && (alignofs & 3) == 2 && bytes >= 2)
4846 emit_move_insn (adjust_address (orig_dst, HImode, ofs), const0_rtx);
4851 if (alignofs == 4 && bytes >= 4)
4853 emit_move_insn (adjust_address (orig_dst, SImode, ofs), const0_rtx);
4859 /* If we've not used the extra lead alignment information by now,
4860 we won't be able to. Downgrade align to match what's left over. */
4863 alignofs = alignofs & -alignofs;
4864 align = MIN (align, alignofs * BITS_PER_UNIT);
4868 /* Handle a block of contiguous long-words. */
4870 if (align >= 64 && bytes >= 8)
4874 for (i = 0; i < words; ++i)
4875 emit_move_insn (adjust_address (orig_dst, DImode, ofs + i * 8),
4882 /* If the block is large and appropriately aligned, emit a single
4883 store followed by a sequence of stq_u insns. */
4885 if (align >= 32 && bytes > 16)
4889 emit_move_insn (adjust_address (orig_dst, SImode, ofs), const0_rtx);
4893 orig_dsta = XEXP (orig_dst, 0);
4894 if (GET_CODE (orig_dsta) == LO_SUM)
4895 orig_dsta = force_reg (Pmode, orig_dsta);
4898 for (i = 0; i < words; ++i)
4901 = change_address (orig_dst, DImode,
4902 gen_rtx_AND (DImode,
4903 plus_constant (orig_dsta, ofs + i*8),
4905 set_mem_alias_set (mem, 0);
4906 emit_move_insn (mem, const0_rtx);
4909 /* Depending on the alignment, the first stq_u may have overlapped
4910 with the initial stl, which means that the last stq_u didn't
4911 write as much as it would appear. Leave those questionable bytes
4913 bytes -= words * 8 - 4;
4914 ofs += words * 8 - 4;
4917 /* Handle a smaller block of aligned words. */
4919 if ((align >= 64 && bytes == 4)
4920 || (align == 32 && bytes >= 4))
4924 for (i = 0; i < words; ++i)
4925 emit_move_insn (adjust_address (orig_dst, SImode, ofs + i * 4),
4932 /* An unaligned block uses stq_u stores for as many as possible. */
4938 alpha_expand_unaligned_store_words (NULL, orig_dst, words, ofs);
4944 /* Next clean up any trailing pieces. */
4946 #if HOST_BITS_PER_WIDE_INT >= 64
4947 /* Count the number of bits in BYTES for which aligned stores could
4950 for (i = (TARGET_BWX ? 1 : 4); i * BITS_PER_UNIT <= align ; i <<= 1)
4954 /* If we have appropriate alignment (and it wouldn't take too many
4955 instructions otherwise), mask out the bytes we need. */
4956 if (TARGET_BWX ? words > 2 : bytes > 0)
4963 mem = adjust_address (orig_dst, DImode, ofs);
4964 set_mem_alias_set (mem, 0);
4966 mask = ~(HOST_WIDE_INT)0 << (bytes * 8);
4968 tmp = expand_binop (DImode, and_optab, mem, GEN_INT (mask),
4969 NULL_RTX, 1, OPTAB_WIDEN);
4971 emit_move_insn (mem, tmp);
4974 else if (align >= 32 && bytes < 4)
4979 mem = adjust_address (orig_dst, SImode, ofs);
4980 set_mem_alias_set (mem, 0);
4982 mask = ~(HOST_WIDE_INT)0 << (bytes * 8);
4984 tmp = expand_binop (SImode, and_optab, mem, GEN_INT (mask),
4985 NULL_RTX, 1, OPTAB_WIDEN);
4987 emit_move_insn (mem, tmp);
4993 if (!TARGET_BWX && bytes >= 4)
4995 alpha_expand_unaligned_store (orig_dst, const0_rtx, 4, ofs);
5005 emit_move_insn (adjust_address (orig_dst, HImode, ofs),
5009 } while (bytes >= 2);
5011 else if (! TARGET_BWX)
5013 alpha_expand_unaligned_store (orig_dst, const0_rtx, 2, ofs);
5021 emit_move_insn (adjust_address (orig_dst, QImode, ofs), const0_rtx);
5029 /* Returns a mask so that zap(x, value) == x & mask. */
5032 alpha_expand_zap_mask (HOST_WIDE_INT value)
5037 if (HOST_BITS_PER_WIDE_INT >= 64)
5039 HOST_WIDE_INT mask = 0;
5041 for (i = 7; i >= 0; --i)
5044 if (!((value >> i) & 1))
5048 result = gen_int_mode (mask, DImode);
5050 else if (HOST_BITS_PER_WIDE_INT == 32)
5052 HOST_WIDE_INT mask_lo = 0, mask_hi = 0;
5054 for (i = 7; i >= 4; --i)
5057 if (!((value >> i) & 1))
5061 for (i = 3; i >= 0; --i)
5064 if (!((value >> i) & 1))
5068 result = immed_double_const (mask_lo, mask_hi, DImode);
5077 alpha_expand_builtin_vector_binop (rtx (*gen) (rtx, rtx, rtx),
5078 enum machine_mode mode,
5079 rtx op0, rtx op1, rtx op2)
5081 op0 = gen_lowpart (mode, op0);
5083 if (op1 == const0_rtx)
5084 op1 = CONST0_RTX (mode);
5086 op1 = gen_lowpart (mode, op1);
5088 if (op2 == const0_rtx)
5089 op2 = CONST0_RTX (mode);
5091 op2 = gen_lowpart (mode, op2);
5093 emit_insn ((*gen) (op0, op1, op2));
5096 /* Adjust the cost of a scheduling dependency. Return the new cost of
5097 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */
5100 alpha_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost)
5102 enum attr_type insn_type, dep_insn_type;
5104 /* If the dependence is an anti-dependence, there is no cost. For an
5105 output dependence, there is sometimes a cost, but it doesn't seem
5106 worth handling those few cases. */
5107 if (REG_NOTE_KIND (link) != 0)
5110 /* If we can't recognize the insns, we can't really do anything. */
5111 if (recog_memoized (insn) < 0 || recog_memoized (dep_insn) < 0)
5114 insn_type = get_attr_type (insn);
5115 dep_insn_type = get_attr_type (dep_insn);
5117 /* Bring in the user-defined memory latency. */
5118 if (dep_insn_type == TYPE_ILD
5119 || dep_insn_type == TYPE_FLD
5120 || dep_insn_type == TYPE_LDSYM)
5121 cost += alpha_memory_latency-1;
5123 /* Everything else handled in DFA bypasses now. */
5128 /* The number of instructions that can be issued per cycle. */
5131 alpha_issue_rate (void)
5133 return (alpha_cpu == PROCESSOR_EV4 ? 2 : 4);
5137 alpha_use_dfa_pipeline_interface (void)
5142 /* How many alternative schedules to try. This should be as wide as the
5143 scheduling freedom in the DFA, but no wider. Making this value too
5144 large results extra work for the scheduler.
5146 For EV4, loads can be issued to either IB0 or IB1, thus we have 2
5147 alternative schedules. For EV5, we can choose between E0/E1 and
5148 FA/FM. For EV6, an arithmetic insn can be issued to U0/U1/L0/L1. */
5151 alpha_multipass_dfa_lookahead (void)
5153 return (alpha_cpu == PROCESSOR_EV6 ? 4 : 2);
5156 /* Machine-specific function data. */
5158 struct machine_function GTY(())
5161 /* List of call information words for calls from this function. */
5162 struct rtx_def *first_ciw;
5163 struct rtx_def *last_ciw;
5166 /* List of deferred case vectors. */
5167 struct rtx_def *addr_list;
5170 const char *some_ld_name;
5173 /* How to allocate a 'struct machine_function'. */
5175 static struct machine_function *
5176 alpha_init_machine_status (void)
5178 return ((struct machine_function *)
5179 ggc_alloc_cleared (sizeof (struct machine_function)));
5182 /* Functions to save and restore alpha_return_addr_rtx. */
5184 /* Start the ball rolling with RETURN_ADDR_RTX. */
5187 alpha_return_addr (int count, rtx frame ATTRIBUTE_UNUSED)
5192 return get_hard_reg_initial_val (Pmode, REG_RA);
5195 /* Return or create a pseudo containing the gp value for the current
5196 function. Needed only if TARGET_LD_BUGGY_LDGP. */
5199 alpha_gp_save_rtx (void)
5201 rtx r = get_hard_reg_initial_val (DImode, 29);
5202 if (GET_CODE (r) != MEM)
5203 r = gen_mem_addressof (r, NULL_TREE, /*rescan=*/true);
5208 alpha_ra_ever_killed (void)
5212 if (!has_hard_reg_initial_val (Pmode, REG_RA))
5213 return regs_ever_live[REG_RA];
5215 push_topmost_sequence ();
5217 pop_topmost_sequence ();
5219 return reg_set_between_p (gen_rtx_REG (Pmode, REG_RA), top, NULL_RTX);
5223 /* Return the trap mode suffix applicable to the current
5224 instruction, or NULL. */
5227 get_trap_mode_suffix (void)
5229 enum attr_trap_suffix s = get_attr_trap_suffix (current_output_insn);
5233 case TRAP_SUFFIX_NONE:
5236 case TRAP_SUFFIX_SU:
5237 if (alpha_fptm >= ALPHA_FPTM_SU)
5241 case TRAP_SUFFIX_SUI:
5242 if (alpha_fptm >= ALPHA_FPTM_SUI)
5246 case TRAP_SUFFIX_V_SV:
5254 case ALPHA_FPTM_SUI:
5259 case TRAP_SUFFIX_V_SV_SVI:
5268 case ALPHA_FPTM_SUI:
5273 case TRAP_SUFFIX_U_SU_SUI:
5282 case ALPHA_FPTM_SUI:
5290 /* Return the rounding mode suffix applicable to the current
5291 instruction, or NULL. */
5294 get_round_mode_suffix (void)
5296 enum attr_round_suffix s = get_attr_round_suffix (current_output_insn);
5300 case ROUND_SUFFIX_NONE:
5302 case ROUND_SUFFIX_NORMAL:
5305 case ALPHA_FPRM_NORM:
5307 case ALPHA_FPRM_MINF:
5309 case ALPHA_FPRM_CHOP:
5311 case ALPHA_FPRM_DYN:
5316 case ROUND_SUFFIX_C:
5322 /* Locate some local-dynamic symbol still in use by this function
5323 so that we can print its name in some movdi_er_tlsldm pattern. */
5326 get_some_local_dynamic_name_1 (rtx *px, void *data ATTRIBUTE_UNUSED)
5330 if (GET_CODE (x) == SYMBOL_REF
5331 && SYMBOL_REF_TLS_MODEL (x) == TLS_MODEL_LOCAL_DYNAMIC)
5333 cfun->machine->some_ld_name = XSTR (x, 0);
5341 get_some_local_dynamic_name (void)
5345 if (cfun->machine->some_ld_name)
5346 return cfun->machine->some_ld_name;
5348 for (insn = get_insns (); insn ; insn = NEXT_INSN (insn))
5350 && for_each_rtx (&PATTERN (insn), get_some_local_dynamic_name_1, 0))
5351 return cfun->machine->some_ld_name;
5356 /* Print an operand. Recognize special options, documented below. */
5359 print_operand (FILE *file, rtx x, int code)
5366 /* Print the assembler name of the current function. */
5367 assemble_name (file, alpha_fnname);
5371 assemble_name (file, get_some_local_dynamic_name ());
5376 const char *trap = get_trap_mode_suffix ();
5377 const char *round = get_round_mode_suffix ();
5380 fprintf (file, (TARGET_AS_SLASH_BEFORE_SUFFIX ? "/%s%s" : "%s%s"),
5381 (trap ? trap : ""), (round ? round : ""));
5386 /* Generates single precision instruction suffix. */
5387 fputc ((TARGET_FLOAT_VAX ? 'f' : 's'), file);
5391 /* Generates double precision instruction suffix. */
5392 fputc ((TARGET_FLOAT_VAX ? 'g' : 't'), file);
5396 /* Generates a nop after a noreturn call at the very end of the
5398 if (next_real_insn (current_output_insn) == 0)
5399 fprintf (file, "\n\tnop");
5403 if (alpha_this_literal_sequence_number == 0)
5404 alpha_this_literal_sequence_number = alpha_next_sequence_number++;
5405 fprintf (file, "%d", alpha_this_literal_sequence_number);
5409 if (alpha_this_gpdisp_sequence_number == 0)
5410 alpha_this_gpdisp_sequence_number = alpha_next_sequence_number++;
5411 fprintf (file, "%d", alpha_this_gpdisp_sequence_number);
5415 if (GET_CODE (x) == HIGH)
5416 output_addr_const (file, XEXP (x, 0));
5418 output_operand_lossage ("invalid %%H value");
5425 if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_TLSGD_CALL)
5427 x = XVECEXP (x, 0, 0);
5428 lituse = "lituse_tlsgd";
5430 else if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_TLSLDM_CALL)
5432 x = XVECEXP (x, 0, 0);
5433 lituse = "lituse_tlsldm";
5435 else if (GET_CODE (x) == CONST_INT)
5436 lituse = "lituse_jsr";
5439 output_operand_lossage ("invalid %%J value");
5443 if (x != const0_rtx)
5444 fprintf (file, "\t\t!%s!%d", lituse, (int) INTVAL (x));
5449 /* If this operand is the constant zero, write it as "$31". */
5450 if (GET_CODE (x) == REG)
5451 fprintf (file, "%s", reg_names[REGNO (x)]);
5452 else if (x == CONST0_RTX (GET_MODE (x)))
5453 fprintf (file, "$31");
5455 output_operand_lossage ("invalid %%r value");
5459 /* Similar, but for floating-point. */
5460 if (GET_CODE (x) == REG)
5461 fprintf (file, "%s", reg_names[REGNO (x)]);
5462 else if (x == CONST0_RTX (GET_MODE (x)))
5463 fprintf (file, "$f31");
5465 output_operand_lossage ("invalid %%R value");
5469 /* Write the 1's complement of a constant. */
5470 if (GET_CODE (x) != CONST_INT)
5471 output_operand_lossage ("invalid %%N value");
5473 fprintf (file, HOST_WIDE_INT_PRINT_DEC, ~ INTVAL (x));
5477 /* Write 1 << C, for a constant C. */
5478 if (GET_CODE (x) != CONST_INT)
5479 output_operand_lossage ("invalid %%P value");
5481 fprintf (file, HOST_WIDE_INT_PRINT_DEC, (HOST_WIDE_INT) 1 << INTVAL (x));
5485 /* Write the high-order 16 bits of a constant, sign-extended. */
5486 if (GET_CODE (x) != CONST_INT)
5487 output_operand_lossage ("invalid %%h value");
5489 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x) >> 16);
5493 /* Write the low-order 16 bits of a constant, sign-extended. */
5494 if (GET_CODE (x) != CONST_INT)
5495 output_operand_lossage ("invalid %%L value");
5497 fprintf (file, HOST_WIDE_INT_PRINT_DEC,
5498 (INTVAL (x) & 0xffff) - 2 * (INTVAL (x) & 0x8000));
5502 /* Write mask for ZAP insn. */
5503 if (GET_CODE (x) == CONST_DOUBLE)
5505 HOST_WIDE_INT mask = 0;
5506 HOST_WIDE_INT value;
5508 value = CONST_DOUBLE_LOW (x);
5509 for (i = 0; i < HOST_BITS_PER_WIDE_INT / HOST_BITS_PER_CHAR;
5514 value = CONST_DOUBLE_HIGH (x);
5515 for (i = 0; i < HOST_BITS_PER_WIDE_INT / HOST_BITS_PER_CHAR;
5518 mask |= (1 << (i + sizeof (int)));
5520 fprintf (file, HOST_WIDE_INT_PRINT_DEC, mask & 0xff);
5523 else if (GET_CODE (x) == CONST_INT)
5525 HOST_WIDE_INT mask = 0, value = INTVAL (x);
5527 for (i = 0; i < 8; i++, value >>= 8)
5531 fprintf (file, HOST_WIDE_INT_PRINT_DEC, mask);
5534 output_operand_lossage ("invalid %%m value");
5538 /* 'b', 'w', 'l', or 'q' as the value of the constant. */
5539 if (GET_CODE (x) != CONST_INT
5540 || (INTVAL (x) != 8 && INTVAL (x) != 16
5541 && INTVAL (x) != 32 && INTVAL (x) != 64))
5542 output_operand_lossage ("invalid %%M value");
5544 fprintf (file, "%s",
5545 (INTVAL (x) == 8 ? "b"
5546 : INTVAL (x) == 16 ? "w"
5547 : INTVAL (x) == 32 ? "l"
5552 /* Similar, except do it from the mask. */
5553 if (GET_CODE (x) == CONST_INT)
5555 HOST_WIDE_INT value = INTVAL (x);
5562 if (value == 0xffff)
5567 if (value == 0xffffffff)
5578 else if (HOST_BITS_PER_WIDE_INT == 32
5579 && GET_CODE (x) == CONST_DOUBLE
5580 && CONST_DOUBLE_LOW (x) == 0xffffffff
5581 && CONST_DOUBLE_HIGH (x) == 0)
5586 output_operand_lossage ("invalid %%U value");
5590 /* Write the constant value divided by 8 for little-endian mode or
5591 (56 - value) / 8 for big-endian mode. */
5593 if (GET_CODE (x) != CONST_INT
5594 || (unsigned HOST_WIDE_INT) INTVAL (x) >= (WORDS_BIG_ENDIAN
5597 || (INTVAL (x) & 7) != 0)
5598 output_operand_lossage ("invalid %%s value");
5600 fprintf (file, HOST_WIDE_INT_PRINT_DEC,
5602 ? (56 - INTVAL (x)) / 8
5607 /* Same, except compute (64 - c) / 8 */
5609 if (GET_CODE (x) != CONST_INT
5610 && (unsigned HOST_WIDE_INT) INTVAL (x) >= 64
5611 && (INTVAL (x) & 7) != 8)
5612 output_operand_lossage ("invalid %%s value");
5614 fprintf (file, HOST_WIDE_INT_PRINT_DEC, (64 - INTVAL (x)) / 8);
5619 /* On Unicos/Mk systems: use a DEX expression if the symbol
5620 clashes with a register name. */
5621 int dex = unicosmk_need_dex (x);
5623 fprintf (file, "DEX(%d)", dex);
5625 output_addr_const (file, x);
5629 case 'C': case 'D': case 'c': case 'd':
5630 /* Write out comparison name. */
5632 enum rtx_code c = GET_CODE (x);
5634 if (GET_RTX_CLASS (c) != '<')
5635 output_operand_lossage ("invalid %%C value");
5637 else if (code == 'D')
5638 c = reverse_condition (c);
5639 else if (code == 'c')
5640 c = swap_condition (c);
5641 else if (code == 'd')
5642 c = swap_condition (reverse_condition (c));
5645 fprintf (file, "ule");
5647 fprintf (file, "ult");
5648 else if (c == UNORDERED)
5649 fprintf (file, "un");
5651 fprintf (file, "%s", GET_RTX_NAME (c));
5656 /* Write the divide or modulus operator. */
5657 switch (GET_CODE (x))
5660 fprintf (file, "div%s", GET_MODE (x) == SImode ? "l" : "q");
5663 fprintf (file, "div%su", GET_MODE (x) == SImode ? "l" : "q");
5666 fprintf (file, "rem%s", GET_MODE (x) == SImode ? "l" : "q");
5669 fprintf (file, "rem%su", GET_MODE (x) == SImode ? "l" : "q");
5672 output_operand_lossage ("invalid %%E value");
5678 /* Write "_u" for unaligned access. */
5679 if (GET_CODE (x) == MEM && GET_CODE (XEXP (x, 0)) == AND)
5680 fprintf (file, "_u");
5684 if (GET_CODE (x) == REG)
5685 fprintf (file, "%s", reg_names[REGNO (x)]);
5686 else if (GET_CODE (x) == MEM)
5687 output_address (XEXP (x, 0));
5688 else if (GET_CODE (x) == CONST && GET_CODE (XEXP (x, 0)) == UNSPEC)
5690 switch (XINT (XEXP (x, 0), 1))
5694 output_addr_const (file, XVECEXP (XEXP (x, 0), 0, 0));
5697 output_operand_lossage ("unknown relocation unspec");
5702 output_addr_const (file, x);
5706 output_operand_lossage ("invalid %%xn code");
5711 print_operand_address (FILE *file, rtx addr)
5714 HOST_WIDE_INT offset = 0;
5716 if (GET_CODE (addr) == AND)
5717 addr = XEXP (addr, 0);
5719 if (GET_CODE (addr) == PLUS
5720 && GET_CODE (XEXP (addr, 1)) == CONST_INT)
5722 offset = INTVAL (XEXP (addr, 1));
5723 addr = XEXP (addr, 0);
5726 if (GET_CODE (addr) == LO_SUM)
5728 const char *reloc16, *reloclo;
5729 rtx op1 = XEXP (addr, 1);
5731 if (GET_CODE (op1) == CONST && GET_CODE (XEXP (op1, 0)) == UNSPEC)
5733 op1 = XEXP (op1, 0);
5734 switch (XINT (op1, 1))
5738 reloclo = (alpha_tls_size == 16 ? "dtprel" : "dtprello");
5742 reloclo = (alpha_tls_size == 16 ? "tprel" : "tprello");
5745 output_operand_lossage ("unknown relocation unspec");
5749 output_addr_const (file, XVECEXP (op1, 0, 0));
5754 reloclo = "gprellow";
5755 output_addr_const (file, op1);
5759 fprintf (file, "+" HOST_WIDE_INT_PRINT_DEC, offset);
5761 addr = XEXP (addr, 0);
5762 if (GET_CODE (addr) == REG)
5763 basereg = REGNO (addr);
5764 else if (GET_CODE (addr) == SUBREG
5765 && GET_CODE (SUBREG_REG (addr)) == REG)
5766 basereg = subreg_regno (addr);
5770 fprintf (file, "($%d)\t\t!%s", basereg,
5771 (basereg == 29 ? reloc16 : reloclo));
5775 if (GET_CODE (addr) == REG)
5776 basereg = REGNO (addr);
5777 else if (GET_CODE (addr) == SUBREG
5778 && GET_CODE (SUBREG_REG (addr)) == REG)
5779 basereg = subreg_regno (addr);
5780 else if (GET_CODE (addr) == CONST_INT)
5781 offset = INTVAL (addr);
5783 #if TARGET_ABI_OPEN_VMS
5784 else if (GET_CODE (addr) == SYMBOL_REF)
5786 fprintf (file, "%s", XSTR (addr, 0));
5789 else if (GET_CODE (addr) == CONST
5790 && GET_CODE (XEXP (addr, 0)) == PLUS
5791 && GET_CODE (XEXP (XEXP (addr, 0), 0)) == SYMBOL_REF)
5793 fprintf (file, "%s+" HOST_WIDE_INT_PRINT_DEC,
5794 XSTR (XEXP (XEXP (addr, 0), 0), 0),
5795 INTVAL (XEXP (XEXP (addr, 0), 1)));
5803 fprintf (file, HOST_WIDE_INT_PRINT_DEC "($%d)", offset, basereg);
5806 /* Emit RTL insns to initialize the variable parts of a trampoline at
5807 TRAMP. FNADDR is an RTX for the address of the function's pure
5808 code. CXT is an RTX for the static chain value for the function.
5810 The three offset parameters are for the individual template's
5811 layout. A JMPOFS < 0 indicates that the trampoline does not
5812 contain instructions at all.
5814 We assume here that a function will be called many more times than
5815 its address is taken (e.g., it might be passed to qsort), so we
5816 take the trouble to initialize the "hint" field in the JMP insn.
5817 Note that the hint field is PC (new) + 4 * bits 13:0. */
5820 alpha_initialize_trampoline (rtx tramp, rtx fnaddr, rtx cxt,
5821 int fnofs, int cxtofs, int jmpofs)
5823 rtx temp, temp1, addr;
5824 /* VMS really uses DImode pointers in memory at this point. */
5825 enum machine_mode mode = TARGET_ABI_OPEN_VMS ? Pmode : ptr_mode;
5827 #ifdef POINTERS_EXTEND_UNSIGNED
5828 fnaddr = convert_memory_address (mode, fnaddr);
5829 cxt = convert_memory_address (mode, cxt);
5832 /* Store function address and CXT. */
5833 addr = memory_address (mode, plus_constant (tramp, fnofs));
5834 emit_move_insn (gen_rtx_MEM (mode, addr), fnaddr);
5835 addr = memory_address (mode, plus_constant (tramp, cxtofs));
5836 emit_move_insn (gen_rtx_MEM (mode, addr), cxt);
5838 /* This has been disabled since the hint only has a 32k range, and in
5839 no existing OS is the stack within 32k of the text segment. */
5840 if (0 && jmpofs >= 0)
5842 /* Compute hint value. */
5843 temp = force_operand (plus_constant (tramp, jmpofs+4), NULL_RTX);
5844 temp = expand_binop (DImode, sub_optab, fnaddr, temp, temp, 1,
5846 temp = expand_shift (RSHIFT_EXPR, Pmode, temp,
5847 build_int_2 (2, 0), NULL_RTX, 1);
5848 temp = expand_and (SImode, gen_lowpart (SImode, temp),
5849 GEN_INT (0x3fff), 0);
5851 /* Merge in the hint. */
5852 addr = memory_address (SImode, plus_constant (tramp, jmpofs));
5853 temp1 = force_reg (SImode, gen_rtx_MEM (SImode, addr));
5854 temp1 = expand_and (SImode, temp1, GEN_INT (0xffffc000), NULL_RTX);
5855 temp1 = expand_binop (SImode, ior_optab, temp1, temp, temp1, 1,
5857 emit_move_insn (gen_rtx_MEM (SImode, addr), temp1);
5860 #ifdef TRANSFER_FROM_TRAMPOLINE
5861 emit_library_call (init_one_libfunc ("__enable_execute_stack"),
5862 0, VOIDmode, 1, tramp, Pmode);
5866 emit_insn (gen_imb ());
5869 /* Determine where to put an argument to a function.
5870 Value is zero to push the argument on the stack,
5871 or a hard register in which to store the argument.
5873 MODE is the argument's machine mode.
5874 TYPE is the data type of the argument (as a tree).
5875 This is null for libcalls where that information may
5877 CUM is a variable of type CUMULATIVE_ARGS which gives info about
5878 the preceding args and about the function being called.
5879 NAMED is nonzero if this argument is a named parameter
5880 (otherwise it is an extra parameter matching an ellipsis).
5882 On Alpha the first 6 words of args are normally in registers
5883 and the rest are pushed. */
5886 function_arg (CUMULATIVE_ARGS cum, enum machine_mode mode, tree type,
5887 int named ATTRIBUTE_UNUSED)
5892 /* Don't get confused and pass small structures in FP registers. */
5893 if (type && AGGREGATE_TYPE_P (type))
5897 #ifdef ENABLE_CHECKING
5898 /* With SPLIT_COMPLEX_ARGS, we shouldn't see any raw complex
5900 if (COMPLEX_MODE_P (mode))
5904 /* Set up defaults for FP operands passed in FP registers, and
5905 integral operands passed in integer registers. */
5906 if (TARGET_FPREGS && GET_MODE_CLASS (mode) == MODE_FLOAT)
5912 /* ??? Irritatingly, the definition of CUMULATIVE_ARGS is different for
5913 the three platforms, so we can't avoid conditional compilation. */
5914 #if TARGET_ABI_OPEN_VMS
5916 if (mode == VOIDmode)
5917 return alpha_arg_info_reg_val (cum);
5919 num_args = cum.num_args;
5920 if (num_args >= 6 || MUST_PASS_IN_STACK (mode, type))
5923 #elif TARGET_ABI_UNICOSMK
5927 /* If this is the last argument, generate the call info word (CIW). */
5928 /* ??? We don't include the caller's line number in the CIW because
5929 I don't know how to determine it if debug infos are turned off. */
5930 if (mode == VOIDmode)
5939 for (i = 0; i < cum.num_reg_words && i < 5; i++)
5940 if (cum.reg_args_type[i])
5941 lo |= (1 << (7 - i));
5943 if (cum.num_reg_words == 6 && cum.reg_args_type[5])
5946 lo |= cum.num_reg_words;
5948 #if HOST_BITS_PER_WIDE_INT == 32
5949 hi = (cum.num_args << 20) | cum.num_arg_words;
5951 lo = lo | ((HOST_WIDE_INT) cum.num_args << 52)
5952 | ((HOST_WIDE_INT) cum.num_arg_words << 32);
5955 ciw = immed_double_const (lo, hi, DImode);
5957 return gen_rtx_UNSPEC (DImode, gen_rtvec (1, ciw),
5958 UNSPEC_UMK_LOAD_CIW);
5961 size = ALPHA_ARG_SIZE (mode, type, named);
5962 num_args = cum.num_reg_words;
5963 if (MUST_PASS_IN_STACK (mode, type)
5964 || cum.num_reg_words + size > 6 || cum.force_stack)
5966 else if (type && TYPE_MODE (type) == BLKmode)
5970 reg1 = gen_rtx_REG (DImode, num_args + 16);
5971 reg1 = gen_rtx_EXPR_LIST (DImode, reg1, const0_rtx);
5973 /* The argument fits in two registers. Note that we still need to
5974 reserve a register for empty structures. */
5978 return gen_rtx_PARALLEL (mode, gen_rtvec (1, reg1));
5981 reg2 = gen_rtx_REG (DImode, num_args + 17);
5982 reg2 = gen_rtx_EXPR_LIST (DImode, reg2, GEN_INT (8));
5983 return gen_rtx_PARALLEL (mode, gen_rtvec (2, reg1, reg2));
5987 #elif TARGET_ABI_OSF
5993 /* VOID is passed as a special flag for "last argument". */
5994 if (type == void_type_node)
5996 else if (MUST_PASS_IN_STACK (mode, type))
5998 else if (FUNCTION_ARG_PASS_BY_REFERENCE (cum, mode, type, named))
6002 #error Unhandled ABI
6005 return gen_rtx_REG (mode, num_args + basereg);
6008 /* Return true if TYPE must be returned in memory, instead of in registers. */
6011 alpha_return_in_memory (tree type, tree fndecl ATTRIBUTE_UNUSED)
6013 enum machine_mode mode = VOIDmode;
6018 mode = TYPE_MODE (type);
6020 /* All aggregates are returned in memory. */
6021 if (AGGREGATE_TYPE_P (type))
6025 size = GET_MODE_SIZE (mode);
6026 switch (GET_MODE_CLASS (mode))
6028 case MODE_VECTOR_FLOAT:
6029 /* Pass all float vectors in memory, like an aggregate. */
6032 case MODE_COMPLEX_FLOAT:
6033 /* We judge complex floats on the size of their element,
6034 not the size of the whole type. */
6035 size = GET_MODE_UNIT_SIZE (mode);
6040 case MODE_COMPLEX_INT:
6041 case MODE_VECTOR_INT:
6045 /* ??? We get called on all sorts of random stuff from
6046 aggregate_value_p. We can't abort, but it's not clear
6047 what's safe to return. Pretend it's a struct I guess. */
6051 /* Otherwise types must fit in one register. */
6052 return size > UNITS_PER_WORD;
6055 /* Define how to find the value returned by a function. VALTYPE is the
6056 data type of the value (as a tree). If the precise function being
6057 called is known, FUNC is its FUNCTION_DECL; otherwise, FUNC is 0.
6058 MODE is set instead of VALTYPE for libcalls.
6060 On Alpha the value is found in $0 for integer functions and
6061 $f0 for floating-point functions. */
6064 function_value (tree valtype, tree func ATTRIBUTE_UNUSED,
6065 enum machine_mode mode)
6067 unsigned int regnum;
6068 enum mode_class class;
6070 #ifdef ENABLE_CHECKING
6071 if (valtype && alpha_return_in_memory (valtype, func))
6076 mode = TYPE_MODE (valtype);
6078 class = GET_MODE_CLASS (mode);
6082 /* Do the same thing as PROMOTE_MODE. */
6086 case MODE_COMPLEX_INT:
6087 case MODE_VECTOR_INT:
6095 case MODE_COMPLEX_FLOAT:
6097 enum machine_mode cmode = GET_MODE_INNER (mode);
6099 return gen_rtx_PARALLEL
6102 gen_rtx_EXPR_LIST (VOIDmode, gen_rtx_REG (cmode, 32),
6104 gen_rtx_EXPR_LIST (VOIDmode, gen_rtx_REG (cmode, 33),
6105 GEN_INT (GET_MODE_SIZE (cmode)))));
6112 return gen_rtx_REG (mode, regnum);
6116 alpha_build_builtin_va_list (void)
6118 tree base, ofs, space, record, type_decl;
6120 if (TARGET_ABI_OPEN_VMS || TARGET_ABI_UNICOSMK)
6121 return ptr_type_node;
6123 record = (*lang_hooks.types.make_type) (RECORD_TYPE);
6124 type_decl = build_decl (TYPE_DECL, get_identifier ("__va_list_tag"), record);
6125 TREE_CHAIN (record) = type_decl;
6126 TYPE_NAME (record) = type_decl;
6128 /* C++? SET_IS_AGGR_TYPE (record, 1); */
6130 /* Dummy field to prevent alignment warnings. */
6131 space = build_decl (FIELD_DECL, NULL_TREE, integer_type_node);
6132 DECL_FIELD_CONTEXT (space) = record;
6133 DECL_ARTIFICIAL (space) = 1;
6134 DECL_IGNORED_P (space) = 1;
6136 ofs = build_decl (FIELD_DECL, get_identifier ("__offset"),
6138 DECL_FIELD_CONTEXT (ofs) = record;
6139 TREE_CHAIN (ofs) = space;
6141 base = build_decl (FIELD_DECL, get_identifier ("__base"),
6143 DECL_FIELD_CONTEXT (base) = record;
6144 TREE_CHAIN (base) = ofs;
6146 TYPE_FIELDS (record) = base;
6147 layout_type (record);
6152 /* Perform any needed actions needed for a function that is receiving a
6153 variable number of arguments. */
6156 alpha_setup_incoming_varargs (CUMULATIVE_ARGS *pcum,
6157 enum machine_mode mode ATTRIBUTE_UNUSED,
6158 tree type ATTRIBUTE_UNUSED,
6159 int *pretend_size, int no_rtl)
6161 #if TARGET_ABI_UNICOSMK
6162 /* On Unicos/Mk, the standard subroutine __T3E_MISMATCH stores all register
6163 arguments on the stack. Unfortunately, it doesn't always store the first
6164 one (i.e. the one that arrives in $16 or $f16). This is not a problem
6165 with stdargs as we always have at least one named argument there. */
6166 int num_reg_words = pcum->num_reg_words;
6167 if (num_reg_words < 6)
6171 emit_insn (gen_umk_mismatch_args (GEN_INT (num_reg_words + 1)));
6172 emit_insn (gen_arg_home_umk ());
6176 #elif TARGET_ABI_OPEN_VMS
6177 /* For VMS, we allocate space for all 6 arg registers plus a count.
6179 However, if NO registers need to be saved, don't allocate any space.
6180 This is not only because we won't need the space, but because AP
6181 includes the current_pretend_args_size and we don't want to mess up
6182 any ap-relative addresses already made. */
6183 if (pcum->num_args < 6)
6187 emit_move_insn (gen_rtx_REG (DImode, 1), virtual_incoming_args_rtx);
6188 emit_insn (gen_arg_home ());
6190 *pretend_size = 7 * UNITS_PER_WORD;
6193 /* On OSF/1 and friends, we allocate space for all 12 arg registers, but
6194 only push those that are remaining. However, if NO registers need to
6195 be saved, don't allocate any space. This is not only because we won't
6196 need the space, but because AP includes the current_pretend_args_size
6197 and we don't want to mess up any ap-relative addresses already made.
6199 If we are not to use the floating-point registers, save the integer
6200 registers where we would put the floating-point registers. This is
6201 not the most efficient way to implement varargs with just one register
6202 class, but it isn't worth doing anything more efficient in this rare
6204 CUMULATIVE_ARGS cum = *pcum;
6211 int set = get_varargs_alias_set ();
6214 tmp = gen_rtx_MEM (BLKmode,
6215 plus_constant (virtual_incoming_args_rtx,
6216 (cum + 6) * UNITS_PER_WORD));
6217 set_mem_alias_set (tmp, set);
6218 move_block_from_reg (16 + cum, tmp, 6 - cum);
6220 tmp = gen_rtx_MEM (BLKmode,
6221 plus_constant (virtual_incoming_args_rtx,
6222 cum * UNITS_PER_WORD));
6223 set_mem_alias_set (tmp, set);
6224 move_block_from_reg (16 + (TARGET_FPREGS ? 32 : 0) + cum, tmp,
6227 *pretend_size = 12 * UNITS_PER_WORD;
6232 alpha_va_start (tree valist, rtx nextarg ATTRIBUTE_UNUSED)
6234 HOST_WIDE_INT offset;
6235 tree t, offset_field, base_field;
6237 if (TREE_CODE (TREE_TYPE (valist)) == ERROR_MARK)
6240 if (TARGET_ABI_UNICOSMK)
6241 std_expand_builtin_va_start (valist, nextarg);
6243 /* For Unix, TARGET_SETUP_INCOMING_VARARGS moves the starting address base
6244 up by 48, storing fp arg registers in the first 48 bytes, and the
6245 integer arg registers in the next 48 bytes. This is only done,
6246 however, if any integer registers need to be stored.
6248 If no integer registers need be stored, then we must subtract 48
6249 in order to account for the integer arg registers which are counted
6250 in argsize above, but which are not actually stored on the stack.
6251 Must further be careful here about structures straddling the last
6252 integer argument register; that futzes with pretend_args_size,
6253 which changes the meaning of AP. */
6256 offset = TARGET_ABI_OPEN_VMS ? UNITS_PER_WORD : 6 * UNITS_PER_WORD;
6258 offset = -6 * UNITS_PER_WORD + current_function_pretend_args_size;
6260 if (TARGET_ABI_OPEN_VMS)
6262 nextarg = plus_constant (nextarg, offset);
6263 nextarg = plus_constant (nextarg, NUM_ARGS * UNITS_PER_WORD);
6264 t = build (MODIFY_EXPR, TREE_TYPE (valist), valist,
6265 make_tree (ptr_type_node, nextarg));
6266 TREE_SIDE_EFFECTS (t) = 1;
6268 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
6272 base_field = TYPE_FIELDS (TREE_TYPE (valist));
6273 offset_field = TREE_CHAIN (base_field);
6275 base_field = build (COMPONENT_REF, TREE_TYPE (base_field),
6276 valist, base_field);
6277 offset_field = build (COMPONENT_REF, TREE_TYPE (offset_field),
6278 valist, offset_field);
6280 t = make_tree (ptr_type_node, virtual_incoming_args_rtx);
6281 t = build (PLUS_EXPR, ptr_type_node, t, build_int_2 (offset, 0));
6282 t = build (MODIFY_EXPR, TREE_TYPE (base_field), base_field, t);
6283 TREE_SIDE_EFFECTS (t) = 1;
6284 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
6286 t = build_int_2 (NUM_ARGS * UNITS_PER_WORD, 0);
6287 t = build (MODIFY_EXPR, TREE_TYPE (offset_field), offset_field, t);
6288 TREE_SIDE_EFFECTS (t) = 1;
6289 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
6294 alpha_va_arg (tree valist, tree type)
6297 tree t, type_size, rounded_size;
6298 tree offset_field, base_field, addr_tree, addend;
6299 tree wide_type, wide_ofs;
6302 if (TARGET_ABI_OPEN_VMS || TARGET_ABI_UNICOSMK)
6303 return std_expand_builtin_va_arg (valist, type);
6305 if (type == error_mark_node
6306 || (type_size = TYPE_SIZE_UNIT (TYPE_MAIN_VARIANT (type))) == NULL
6307 || TREE_OVERFLOW (type_size))
6308 rounded_size = size_zero_node;
6310 rounded_size = fold (build (MULT_EXPR, sizetype,
6311 fold (build (TRUNC_DIV_EXPR, sizetype,
6312 fold (build (PLUS_EXPR, sizetype,
6318 base_field = TYPE_FIELDS (TREE_TYPE (valist));
6319 offset_field = TREE_CHAIN (base_field);
6321 base_field = build (COMPONENT_REF, TREE_TYPE (base_field),
6322 valist, base_field);
6323 offset_field = build (COMPONENT_REF, TREE_TYPE (offset_field),
6324 valist, offset_field);
6326 /* If the type could not be passed in registers, skip the block
6327 reserved for the registers. */
6328 if (MUST_PASS_IN_STACK (TYPE_MODE (type), type))
6330 t = build (MODIFY_EXPR, TREE_TYPE (offset_field), offset_field,
6331 build (MAX_EXPR, TREE_TYPE (offset_field),
6332 offset_field, build_int_2 (6*8, 0)));
6333 TREE_SIDE_EFFECTS (t) = 1;
6334 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
6337 wide_type = make_signed_type (64);
6338 wide_ofs = save_expr (build1 (CONVERT_EXPR, wide_type, offset_field));
6342 if (TYPE_MODE (type) == TFmode || TYPE_MODE (type) == TCmode)
6345 rounded_size = size_int (UNITS_PER_WORD);
6347 else if (TREE_CODE (type) == COMPLEX_TYPE)
6349 rtx real_part, imag_part, value, tmp;
6351 real_part = alpha_va_arg (valist, TREE_TYPE (type));
6352 imag_part = alpha_va_arg (valist, TREE_TYPE (type));
6354 /* ??? Most irritatingly, we're not returning the value here,
6355 but the address. Since real_part and imag_part are not
6356 necessarily contiguous, we must copy to local storage. */
6358 real_part = gen_rtx_MEM (TYPE_MODE (TREE_TYPE (type)), real_part);
6359 imag_part = gen_rtx_MEM (TYPE_MODE (TREE_TYPE (type)), imag_part);
6360 value = gen_rtx_CONCAT (TYPE_MODE (type), real_part, imag_part);
6362 tmp = assign_temp (type, 0, 1, 0);
6363 emit_move_insn (tmp, value);
6365 return XEXP (tmp, 0);
6367 else if (TREE_CODE (type) == REAL_TYPE)
6369 tree fpaddend, cond;
6371 fpaddend = fold (build (PLUS_EXPR, TREE_TYPE (addend),
6372 addend, build_int_2 (-6*8, 0)));
6374 cond = fold (build (LT_EXPR, integer_type_node,
6375 wide_ofs, build_int_2 (6*8, 0)));
6377 addend = fold (build (COND_EXPR, TREE_TYPE (addend), cond,
6381 addr_tree = build (PLUS_EXPR, TREE_TYPE (base_field),
6382 base_field, addend);
6384 addr = expand_expr (addr_tree, NULL_RTX, Pmode, EXPAND_NORMAL);
6385 addr = copy_to_reg (addr);
6387 t = build (MODIFY_EXPR, TREE_TYPE (offset_field), offset_field,
6388 build (PLUS_EXPR, TREE_TYPE (offset_field),
6389 offset_field, rounded_size));
6390 TREE_SIDE_EFFECTS (t) = 1;
6391 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
6395 addr = force_reg (Pmode, addr);
6396 addr = gen_rtx_MEM (Pmode, addr);
6406 ALPHA_BUILTIN_CMPBGE,
6407 ALPHA_BUILTIN_EXTBL,
6408 ALPHA_BUILTIN_EXTWL,
6409 ALPHA_BUILTIN_EXTLL,
6410 ALPHA_BUILTIN_EXTQL,
6411 ALPHA_BUILTIN_EXTWH,
6412 ALPHA_BUILTIN_EXTLH,
6413 ALPHA_BUILTIN_EXTQH,
6414 ALPHA_BUILTIN_INSBL,
6415 ALPHA_BUILTIN_INSWL,
6416 ALPHA_BUILTIN_INSLL,
6417 ALPHA_BUILTIN_INSQL,
6418 ALPHA_BUILTIN_INSWH,
6419 ALPHA_BUILTIN_INSLH,
6420 ALPHA_BUILTIN_INSQH,
6421 ALPHA_BUILTIN_MSKBL,
6422 ALPHA_BUILTIN_MSKWL,
6423 ALPHA_BUILTIN_MSKLL,
6424 ALPHA_BUILTIN_MSKQL,
6425 ALPHA_BUILTIN_MSKWH,
6426 ALPHA_BUILTIN_MSKLH,
6427 ALPHA_BUILTIN_MSKQH,
6428 ALPHA_BUILTIN_UMULH,
6430 ALPHA_BUILTIN_ZAPNOT,
6431 ALPHA_BUILTIN_AMASK,
6432 ALPHA_BUILTIN_IMPLVER,
6434 ALPHA_BUILTIN_THREAD_POINTER,
6435 ALPHA_BUILTIN_SET_THREAD_POINTER,
6438 ALPHA_BUILTIN_MINUB8,
6439 ALPHA_BUILTIN_MINSB8,
6440 ALPHA_BUILTIN_MINUW4,
6441 ALPHA_BUILTIN_MINSW4,
6442 ALPHA_BUILTIN_MAXUB8,
6443 ALPHA_BUILTIN_MAXSB8,
6444 ALPHA_BUILTIN_MAXUW4,
6445 ALPHA_BUILTIN_MAXSW4,
6449 ALPHA_BUILTIN_UNPKBL,
6450 ALPHA_BUILTIN_UNPKBW,
6455 ALPHA_BUILTIN_CTPOP,
6460 static unsigned int const code_for_builtin[ALPHA_BUILTIN_max] = {
6461 CODE_FOR_builtin_cmpbge,
6462 CODE_FOR_builtin_extbl,
6463 CODE_FOR_builtin_extwl,
6464 CODE_FOR_builtin_extll,
6465 CODE_FOR_builtin_extql,
6466 CODE_FOR_builtin_extwh,
6467 CODE_FOR_builtin_extlh,
6468 CODE_FOR_builtin_extqh,
6469 CODE_FOR_builtin_insbl,
6470 CODE_FOR_builtin_inswl,
6471 CODE_FOR_builtin_insll,
6472 CODE_FOR_builtin_insql,
6473 CODE_FOR_builtin_inswh,
6474 CODE_FOR_builtin_inslh,
6475 CODE_FOR_builtin_insqh,
6476 CODE_FOR_builtin_mskbl,
6477 CODE_FOR_builtin_mskwl,
6478 CODE_FOR_builtin_mskll,
6479 CODE_FOR_builtin_mskql,
6480 CODE_FOR_builtin_mskwh,
6481 CODE_FOR_builtin_msklh,
6482 CODE_FOR_builtin_mskqh,
6483 CODE_FOR_umuldi3_highpart,
6484 CODE_FOR_builtin_zap,
6485 CODE_FOR_builtin_zapnot,
6486 CODE_FOR_builtin_amask,
6487 CODE_FOR_builtin_implver,
6488 CODE_FOR_builtin_rpcc,
6493 CODE_FOR_builtin_minub8,
6494 CODE_FOR_builtin_minsb8,
6495 CODE_FOR_builtin_minuw4,
6496 CODE_FOR_builtin_minsw4,
6497 CODE_FOR_builtin_maxub8,
6498 CODE_FOR_builtin_maxsb8,
6499 CODE_FOR_builtin_maxuw4,
6500 CODE_FOR_builtin_maxsw4,
6501 CODE_FOR_builtin_perr,
6502 CODE_FOR_builtin_pklb,
6503 CODE_FOR_builtin_pkwb,
6504 CODE_FOR_builtin_unpkbl,
6505 CODE_FOR_builtin_unpkbw,
6508 CODE_FOR_builtin_cttz,
6509 CODE_FOR_builtin_ctlz,
6510 CODE_FOR_builtin_ctpop
6513 struct alpha_builtin_def
6516 enum alpha_builtin code;
6517 unsigned int target_mask;
6520 static struct alpha_builtin_def const zero_arg_builtins[] = {
6521 { "__builtin_alpha_implver", ALPHA_BUILTIN_IMPLVER, 0 },
6522 { "__builtin_alpha_rpcc", ALPHA_BUILTIN_RPCC, 0 }
6525 static struct alpha_builtin_def const one_arg_builtins[] = {
6526 { "__builtin_alpha_amask", ALPHA_BUILTIN_AMASK, 0 },
6527 { "__builtin_alpha_pklb", ALPHA_BUILTIN_PKLB, MASK_MAX },
6528 { "__builtin_alpha_pkwb", ALPHA_BUILTIN_PKWB, MASK_MAX },
6529 { "__builtin_alpha_unpkbl", ALPHA_BUILTIN_UNPKBL, MASK_MAX },
6530 { "__builtin_alpha_unpkbw", ALPHA_BUILTIN_UNPKBW, MASK_MAX },
6531 { "__builtin_alpha_cttz", ALPHA_BUILTIN_CTTZ, MASK_CIX },
6532 { "__builtin_alpha_ctlz", ALPHA_BUILTIN_CTLZ, MASK_CIX },
6533 { "__builtin_alpha_ctpop", ALPHA_BUILTIN_CTPOP, MASK_CIX }
6536 static struct alpha_builtin_def const two_arg_builtins[] = {
6537 { "__builtin_alpha_cmpbge", ALPHA_BUILTIN_CMPBGE, 0 },
6538 { "__builtin_alpha_extbl", ALPHA_BUILTIN_EXTBL, 0 },
6539 { "__builtin_alpha_extwl", ALPHA_BUILTIN_EXTWL, 0 },
6540 { "__builtin_alpha_extll", ALPHA_BUILTIN_EXTLL, 0 },
6541 { "__builtin_alpha_extql", ALPHA_BUILTIN_EXTQL, 0 },
6542 { "__builtin_alpha_extwh", ALPHA_BUILTIN_EXTWH, 0 },
6543 { "__builtin_alpha_extlh", ALPHA_BUILTIN_EXTLH, 0 },
6544 { "__builtin_alpha_extqh", ALPHA_BUILTIN_EXTQH, 0 },
6545 { "__builtin_alpha_insbl", ALPHA_BUILTIN_INSBL, 0 },
6546 { "__builtin_alpha_inswl", ALPHA_BUILTIN_INSWL, 0 },
6547 { "__builtin_alpha_insll", ALPHA_BUILTIN_INSLL, 0 },
6548 { "__builtin_alpha_insql", ALPHA_BUILTIN_INSQL, 0 },
6549 { "__builtin_alpha_inswh", ALPHA_BUILTIN_INSWH, 0 },
6550 { "__builtin_alpha_inslh", ALPHA_BUILTIN_INSLH, 0 },
6551 { "__builtin_alpha_insqh", ALPHA_BUILTIN_INSQH, 0 },
6552 { "__builtin_alpha_mskbl", ALPHA_BUILTIN_MSKBL, 0 },
6553 { "__builtin_alpha_mskwl", ALPHA_BUILTIN_MSKWL, 0 },
6554 { "__builtin_alpha_mskll", ALPHA_BUILTIN_MSKLL, 0 },
6555 { "__builtin_alpha_mskql", ALPHA_BUILTIN_MSKQL, 0 },
6556 { "__builtin_alpha_mskwh", ALPHA_BUILTIN_MSKWH, 0 },
6557 { "__builtin_alpha_msklh", ALPHA_BUILTIN_MSKLH, 0 },
6558 { "__builtin_alpha_mskqh", ALPHA_BUILTIN_MSKQH, 0 },
6559 { "__builtin_alpha_umulh", ALPHA_BUILTIN_UMULH, 0 },
6560 { "__builtin_alpha_zap", ALPHA_BUILTIN_ZAP, 0 },
6561 { "__builtin_alpha_zapnot", ALPHA_BUILTIN_ZAPNOT, 0 },
6562 { "__builtin_alpha_minub8", ALPHA_BUILTIN_MINUB8, MASK_MAX },
6563 { "__builtin_alpha_minsb8", ALPHA_BUILTIN_MINSB8, MASK_MAX },
6564 { "__builtin_alpha_minuw4", ALPHA_BUILTIN_MINUW4, MASK_MAX },
6565 { "__builtin_alpha_minsw4", ALPHA_BUILTIN_MINSW4, MASK_MAX },
6566 { "__builtin_alpha_maxub8", ALPHA_BUILTIN_MAXUB8, MASK_MAX },
6567 { "__builtin_alpha_maxsb8", ALPHA_BUILTIN_MAXSB8, MASK_MAX },
6568 { "__builtin_alpha_maxuw4", ALPHA_BUILTIN_MAXUW4, MASK_MAX },
6569 { "__builtin_alpha_maxsw4", ALPHA_BUILTIN_MAXSW4, MASK_MAX },
6570 { "__builtin_alpha_perr", ALPHA_BUILTIN_PERR, MASK_MAX }
6574 alpha_init_builtins (void)
6576 const struct alpha_builtin_def *p;
6580 ftype = build_function_type (long_integer_type_node, void_list_node);
6582 p = zero_arg_builtins;
6583 for (i = 0; i < ARRAY_SIZE (zero_arg_builtins); ++i, ++p)
6584 if ((target_flags & p->target_mask) == p->target_mask)
6585 builtin_function (p->name, ftype, p->code, BUILT_IN_MD,
6588 ftype = build_function_type_list (long_integer_type_node,
6589 long_integer_type_node, NULL_TREE);
6591 p = one_arg_builtins;
6592 for (i = 0; i < ARRAY_SIZE (one_arg_builtins); ++i, ++p)
6593 if ((target_flags & p->target_mask) == p->target_mask)
6594 builtin_function (p->name, ftype, p->code, BUILT_IN_MD,
6597 ftype = build_function_type_list (long_integer_type_node,
6598 long_integer_type_node,
6599 long_integer_type_node, NULL_TREE);
6601 p = two_arg_builtins;
6602 for (i = 0; i < ARRAY_SIZE (two_arg_builtins); ++i, ++p)
6603 if ((target_flags & p->target_mask) == p->target_mask)
6604 builtin_function (p->name, ftype, p->code, BUILT_IN_MD,
6607 ftype = build_function_type (ptr_type_node, void_list_node);
6608 builtin_function ("__builtin_thread_pointer", ftype,
6609 ALPHA_BUILTIN_THREAD_POINTER, BUILT_IN_MD,
6612 ftype = build_function_type_list (void_type_node, ptr_type_node, NULL_TREE);
6613 builtin_function ("__builtin_set_thread_pointer", ftype,
6614 ALPHA_BUILTIN_SET_THREAD_POINTER, BUILT_IN_MD,
6618 /* Expand an expression EXP that calls a built-in function,
6619 with result going to TARGET if that's convenient
6620 (and in mode MODE if that's convenient).
6621 SUBTARGET may be used as the target for computing one of EXP's operands.
6622 IGNORE is nonzero if the value is to be ignored. */
6625 alpha_expand_builtin (tree exp, rtx target,
6626 rtx subtarget ATTRIBUTE_UNUSED,
6627 enum machine_mode mode ATTRIBUTE_UNUSED,
6628 int ignore ATTRIBUTE_UNUSED)
6632 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
6633 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
6634 tree arglist = TREE_OPERAND (exp, 1);
6635 enum insn_code icode;
6636 rtx op[MAX_ARGS], pat;
6640 if (fcode >= ALPHA_BUILTIN_max)
6641 internal_error ("bad builtin fcode");
6642 icode = code_for_builtin[fcode];
6644 internal_error ("bad builtin fcode");
6646 nonvoid = TREE_TYPE (TREE_TYPE (fndecl)) != void_type_node;
6648 for (arglist = TREE_OPERAND (exp, 1), arity = 0;
6650 arglist = TREE_CHAIN (arglist), arity++)
6652 const struct insn_operand_data *insn_op;
6654 tree arg = TREE_VALUE (arglist);
6655 if (arg == error_mark_node)
6657 if (arity > MAX_ARGS)
6660 insn_op = &insn_data[icode].operand[arity + nonvoid];
6662 op[arity] = expand_expr (arg, NULL_RTX, insn_op->mode, 0);
6664 if (!(*insn_op->predicate) (op[arity], insn_op->mode))
6665 op[arity] = copy_to_mode_reg (insn_op->mode, op[arity]);
6670 enum machine_mode tmode = insn_data[icode].operand[0].mode;
6672 || GET_MODE (target) != tmode
6673 || !(*insn_data[icode].operand[0].predicate) (target, tmode))
6674 target = gen_reg_rtx (tmode);
6680 pat = GEN_FCN (icode) (target);
6684 pat = GEN_FCN (icode) (target, op[0]);
6686 pat = GEN_FCN (icode) (op[0]);
6689 pat = GEN_FCN (icode) (target, op[0], op[1]);
6704 /* This page contains routines that are used to determine what the function
6705 prologue and epilogue code will do and write them out. */
6707 /* Compute the size of the save area in the stack. */
6709 /* These variables are used for communication between the following functions.
6710 They indicate various things about the current function being compiled
6711 that are used to tell what kind of prologue, epilogue and procedure
6712 descriptor to generate. */
6714 /* Nonzero if we need a stack procedure. */
6715 enum alpha_procedure_types {PT_NULL = 0, PT_REGISTER = 1, PT_STACK = 2};
6716 static enum alpha_procedure_types alpha_procedure_type;
6718 /* Register number (either FP or SP) that is used to unwind the frame. */
6719 static int vms_unwind_regno;
6721 /* Register number used to save FP. We need not have one for RA since
6722 we don't modify it for register procedures. This is only defined
6723 for register frame procedures. */
6724 static int vms_save_fp_regno;
6726 /* Register number used to reference objects off our PV. */
6727 static int vms_base_regno;
6729 /* Compute register masks for saved registers. */
6732 alpha_sa_mask (unsigned long *imaskP, unsigned long *fmaskP)
6734 unsigned long imask = 0;
6735 unsigned long fmask = 0;
6738 /* When outputting a thunk, we don't have valid register life info,
6739 but assemble_start_function wants to output .frame and .mask
6741 if (current_function_is_thunk)
6748 if (TARGET_ABI_OPEN_VMS && alpha_procedure_type == PT_STACK)
6749 imask |= (1UL << HARD_FRAME_POINTER_REGNUM);
6751 /* One for every register we have to save. */
6752 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
6753 if (! fixed_regs[i] && ! call_used_regs[i]
6754 && regs_ever_live[i] && i != REG_RA
6755 && (!TARGET_ABI_UNICOSMK || i != HARD_FRAME_POINTER_REGNUM))
6758 imask |= (1UL << i);
6760 fmask |= (1UL << (i - 32));
6763 /* We need to restore these for the handler. */
6764 if (current_function_calls_eh_return)
6768 unsigned regno = EH_RETURN_DATA_REGNO (i);
6769 if (regno == INVALID_REGNUM)
6771 imask |= 1UL << regno;
6774 /* Glibc likes to use $31 as an unwind stopper for crt0. To
6775 avoid hackery in unwind-dw2.c, we need to actively store a
6776 zero in the prologue of _Unwind_RaiseException et al. */
6780 /* If any register spilled, then spill the return address also. */
6781 /* ??? This is required by the Digital stack unwind specification
6782 and isn't needed if we're doing Dwarf2 unwinding. */
6783 if (imask || fmask || alpha_ra_ever_killed ())
6784 imask |= (1UL << REG_RA);
6791 alpha_sa_size (void)
6793 unsigned long mask[2];
6797 alpha_sa_mask (&mask[0], &mask[1]);
6799 if (TARGET_ABI_UNICOSMK)
6801 if (mask[0] || mask[1])
6806 for (j = 0; j < 2; ++j)
6807 for (i = 0; i < 32; ++i)
6808 if ((mask[j] >> i) & 1)
6812 if (TARGET_ABI_UNICOSMK)
6814 /* We might not need to generate a frame if we don't make any calls
6815 (including calls to __T3E_MISMATCH if this is a vararg function),
6816 don't have any local variables which require stack slots, don't
6817 use alloca and have not determined that we need a frame for other
6820 alpha_procedure_type
6821 = (sa_size || get_frame_size() != 0
6822 || current_function_outgoing_args_size
6823 || current_function_stdarg || current_function_calls_alloca
6824 || frame_pointer_needed)
6825 ? PT_STACK : PT_REGISTER;
6827 /* Always reserve space for saving callee-saved registers if we
6828 need a frame as required by the calling convention. */
6829 if (alpha_procedure_type == PT_STACK)
6832 else if (TARGET_ABI_OPEN_VMS)
6834 /* Start by assuming we can use a register procedure if we don't
6835 make any calls (REG_RA not used) or need to save any
6836 registers and a stack procedure if we do. */
6837 if ((mask[0] >> REG_RA) & 1)
6838 alpha_procedure_type = PT_STACK;
6839 else if (get_frame_size() != 0)
6840 alpha_procedure_type = PT_REGISTER;
6842 alpha_procedure_type = PT_NULL;
6844 /* Don't reserve space for saving FP & RA yet. Do that later after we've
6845 made the final decision on stack procedure vs register procedure. */
6846 if (alpha_procedure_type == PT_STACK)
6849 /* Decide whether to refer to objects off our PV via FP or PV.
6850 If we need FP for something else or if we receive a nonlocal
6851 goto (which expects PV to contain the value), we must use PV.
6852 Otherwise, start by assuming we can use FP. */
6855 = (frame_pointer_needed
6856 || current_function_has_nonlocal_label
6857 || alpha_procedure_type == PT_STACK
6858 || current_function_outgoing_args_size)
6859 ? REG_PV : HARD_FRAME_POINTER_REGNUM;
6861 /* If we want to copy PV into FP, we need to find some register
6862 in which to save FP. */
6864 vms_save_fp_regno = -1;
6865 if (vms_base_regno == HARD_FRAME_POINTER_REGNUM)
6866 for (i = 0; i < 32; i++)
6867 if (! fixed_regs[i] && call_used_regs[i] && ! regs_ever_live[i])
6868 vms_save_fp_regno = i;
6870 if (vms_save_fp_regno == -1 && alpha_procedure_type == PT_REGISTER)
6871 vms_base_regno = REG_PV, alpha_procedure_type = PT_STACK;
6872 else if (alpha_procedure_type == PT_NULL)
6873 vms_base_regno = REG_PV;
6875 /* Stack unwinding should be done via FP unless we use it for PV. */
6876 vms_unwind_regno = (vms_base_regno == REG_PV
6877 ? HARD_FRAME_POINTER_REGNUM : STACK_POINTER_REGNUM);
6879 /* If this is a stack procedure, allow space for saving FP and RA. */
6880 if (alpha_procedure_type == PT_STACK)
6885 /* Our size must be even (multiple of 16 bytes). */
6893 /* Define the offset between two registers, one to be eliminated,
6894 and the other its replacement, at the start of a routine. */
6897 alpha_initial_elimination_offset (unsigned int from,
6898 unsigned int to ATTRIBUTE_UNUSED)
6902 ret = alpha_sa_size ();
6903 ret += ALPHA_ROUND (current_function_outgoing_args_size);
6905 if (from == FRAME_POINTER_REGNUM)
6907 else if (from == ARG_POINTER_REGNUM)
6908 ret += (ALPHA_ROUND (get_frame_size ()
6909 + current_function_pretend_args_size)
6910 - current_function_pretend_args_size);
6918 alpha_pv_save_size (void)
6921 return alpha_procedure_type == PT_STACK ? 8 : 0;
6925 alpha_using_fp (void)
6928 return vms_unwind_regno == HARD_FRAME_POINTER_REGNUM;
6931 #if TARGET_ABI_OPEN_VMS
6933 const struct attribute_spec vms_attribute_table[] =
6935 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
6936 { "overlaid", 0, 0, true, false, false, NULL },
6937 { "global", 0, 0, true, false, false, NULL },
6938 { "initialize", 0, 0, true, false, false, NULL },
6939 { NULL, 0, 0, false, false, false, NULL }
6945 find_lo_sum_using_gp (rtx *px, void *data ATTRIBUTE_UNUSED)
6947 return GET_CODE (*px) == LO_SUM && XEXP (*px, 0) == pic_offset_table_rtx;
6951 alpha_find_lo_sum_using_gp (rtx insn)
6953 return for_each_rtx (&PATTERN (insn), find_lo_sum_using_gp, NULL) > 0;
6957 alpha_does_function_need_gp (void)
6961 /* The GP being variable is an OSF abi thing. */
6962 if (! TARGET_ABI_OSF)
6965 /* We need the gp to load the address of __mcount. */
6966 if (TARGET_PROFILING_NEEDS_GP && current_function_profile)
6969 /* The code emitted by alpha_output_mi_thunk_osf uses the gp. */
6970 if (current_function_is_thunk)
6973 /* The nonlocal receiver pattern assumes that the gp is valid for
6974 the nested function. Reasonable because it's almost always set
6975 correctly already. For the cases where that's wrong, make sure
6976 the nested function loads its gp on entry. */
6977 if (current_function_has_nonlocal_goto)
6980 /* If we need a GP (we have a LDSYM insn or a CALL_INSN), load it first.
6981 Even if we are a static function, we still need to do this in case
6982 our address is taken and passed to something like qsort. */
6984 push_topmost_sequence ();
6985 insn = get_insns ();
6986 pop_topmost_sequence ();
6988 for (; insn; insn = NEXT_INSN (insn))
6990 && GET_CODE (PATTERN (insn)) != USE
6991 && GET_CODE (PATTERN (insn)) != CLOBBER
6992 && get_attr_usegp (insn))
6999 /* Helper function to set RTX_FRAME_RELATED_P on instructions, including
7003 set_frame_related_p (void)
7005 rtx seq = get_insns ();
7016 while (insn != NULL_RTX)
7018 RTX_FRAME_RELATED_P (insn) = 1;
7019 insn = NEXT_INSN (insn);
7021 seq = emit_insn (seq);
7025 seq = emit_insn (seq);
7026 RTX_FRAME_RELATED_P (seq) = 1;
7031 #define FRP(exp) (start_sequence (), exp, set_frame_related_p ())
7033 /* Write function prologue. */
7035 /* On vms we have two kinds of functions:
7037 - stack frame (PROC_STACK)
7038 these are 'normal' functions with local vars and which are
7039 calling other functions
7040 - register frame (PROC_REGISTER)
7041 keeps all data in registers, needs no stack
7043 We must pass this to the assembler so it can generate the
7044 proper pdsc (procedure descriptor)
7045 This is done with the '.pdesc' command.
7047 On not-vms, we don't really differentiate between the two, as we can
7048 simply allocate stack without saving registers. */
7051 alpha_expand_prologue (void)
7053 /* Registers to save. */
7054 unsigned long imask = 0;
7055 unsigned long fmask = 0;
7056 /* Stack space needed for pushing registers clobbered by us. */
7057 HOST_WIDE_INT sa_size;
7058 /* Complete stack size needed. */
7059 HOST_WIDE_INT frame_size;
7060 /* Offset from base reg to register save area. */
7061 HOST_WIDE_INT reg_offset;
7065 sa_size = alpha_sa_size ();
7067 frame_size = get_frame_size ();
7068 if (TARGET_ABI_OPEN_VMS)
7069 frame_size = ALPHA_ROUND (sa_size
7070 + (alpha_procedure_type == PT_STACK ? 8 : 0)
7072 + current_function_pretend_args_size);
7073 else if (TARGET_ABI_UNICOSMK)
7074 /* We have to allocate space for the DSIB if we generate a frame. */
7075 frame_size = ALPHA_ROUND (sa_size
7076 + (alpha_procedure_type == PT_STACK ? 48 : 0))
7077 + ALPHA_ROUND (frame_size
7078 + current_function_outgoing_args_size);
7080 frame_size = (ALPHA_ROUND (current_function_outgoing_args_size)
7082 + ALPHA_ROUND (frame_size
7083 + current_function_pretend_args_size));
7085 if (TARGET_ABI_OPEN_VMS)
7088 reg_offset = ALPHA_ROUND (current_function_outgoing_args_size);
7090 alpha_sa_mask (&imask, &fmask);
7092 /* Emit an insn to reload GP, if needed. */
7095 alpha_function_needs_gp = alpha_does_function_need_gp ();
7096 if (alpha_function_needs_gp)
7097 emit_insn (gen_prologue_ldgp ());
7100 /* TARGET_PROFILING_NEEDS_GP actually implies that we need to insert
7101 the call to mcount ourselves, rather than having the linker do it
7102 magically in response to -pg. Since _mcount has special linkage,
7103 don't represent the call as a call. */
7104 if (TARGET_PROFILING_NEEDS_GP && current_function_profile)
7105 emit_insn (gen_prologue_mcount ());
7107 if (TARGET_ABI_UNICOSMK)
7108 unicosmk_gen_dsib (&imask);
7110 /* Adjust the stack by the frame size. If the frame size is > 4096
7111 bytes, we need to be sure we probe somewhere in the first and last
7112 4096 bytes (we can probably get away without the latter test) and
7113 every 8192 bytes in between. If the frame size is > 32768, we
7114 do this in a loop. Otherwise, we generate the explicit probe
7117 Note that we are only allowed to adjust sp once in the prologue. */
7119 if (frame_size <= 32768)
7121 if (frame_size > 4096)
7126 emit_insn (gen_probe_stack (GEN_INT (TARGET_ABI_UNICOSMK
7129 while ((probed += 8192) < frame_size);
7131 /* We only have to do this probe if we aren't saving registers. */
7132 if (sa_size == 0 && probed + 4096 < frame_size)
7133 emit_insn (gen_probe_stack (GEN_INT (-frame_size)));
7136 if (frame_size != 0)
7137 FRP (emit_insn (gen_adddi3 (stack_pointer_rtx, stack_pointer_rtx,
7138 GEN_INT (TARGET_ABI_UNICOSMK
7144 /* Here we generate code to set R22 to SP + 4096 and set R23 to the
7145 number of 8192 byte blocks to probe. We then probe each block
7146 in the loop and then set SP to the proper location. If the
7147 amount remaining is > 4096, we have to do one more probe if we
7148 are not saving any registers. */
7150 HOST_WIDE_INT blocks = (frame_size + 4096) / 8192;
7151 HOST_WIDE_INT leftover = frame_size + 4096 - blocks * 8192;
7152 rtx ptr = gen_rtx_REG (DImode, 22);
7153 rtx count = gen_rtx_REG (DImode, 23);
7156 emit_move_insn (count, GEN_INT (blocks));
7157 emit_insn (gen_adddi3 (ptr, stack_pointer_rtx,
7158 GEN_INT (TARGET_ABI_UNICOSMK ? 4096 - 64 : 4096)));
7160 /* Because of the difficulty in emitting a new basic block this
7161 late in the compilation, generate the loop as a single insn. */
7162 emit_insn (gen_prologue_stack_probe_loop (count, ptr));
7164 if (leftover > 4096 && sa_size == 0)
7166 rtx last = gen_rtx_MEM (DImode, plus_constant (ptr, -leftover));
7167 MEM_VOLATILE_P (last) = 1;
7168 emit_move_insn (last, const0_rtx);
7171 if (TARGET_ABI_WINDOWS_NT)
7173 /* For NT stack unwind (done by 'reverse execution'), it's
7174 not OK to take the result of a loop, even though the value
7175 is already in ptr, so we reload it via a single operation
7176 and subtract it to sp.
7178 Yes, that's correct -- we have to reload the whole constant
7179 into a temporary via ldah+lda then subtract from sp. */
7181 HOST_WIDE_INT lo, hi;
7182 lo = ((frame_size & 0xffff) ^ 0x8000) - 0x8000;
7183 hi = frame_size - lo;
7185 emit_move_insn (ptr, GEN_INT (hi));
7186 emit_insn (gen_adddi3 (ptr, ptr, GEN_INT (lo)));
7187 seq = emit_insn (gen_subdi3 (stack_pointer_rtx, stack_pointer_rtx,
7192 seq = emit_insn (gen_adddi3 (stack_pointer_rtx, ptr,
7193 GEN_INT (-leftover)));
7196 /* This alternative is special, because the DWARF code cannot
7197 possibly intuit through the loop above. So we invent this
7198 note it looks at instead. */
7199 RTX_FRAME_RELATED_P (seq) = 1;
7201 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
7202 gen_rtx_SET (VOIDmode, stack_pointer_rtx,
7203 gen_rtx_PLUS (Pmode, stack_pointer_rtx,
7204 GEN_INT (TARGET_ABI_UNICOSMK
7210 if (!TARGET_ABI_UNICOSMK)
7212 /* Cope with very large offsets to the register save area. */
7213 sa_reg = stack_pointer_rtx;
7214 if (reg_offset + sa_size > 0x8000)
7216 int low = ((reg_offset & 0xffff) ^ 0x8000) - 0x8000;
7219 if (low + sa_size <= 0x8000)
7220 bias = reg_offset - low, reg_offset = low;
7222 bias = reg_offset, reg_offset = 0;
7224 sa_reg = gen_rtx_REG (DImode, 24);
7225 FRP (emit_insn (gen_adddi3 (sa_reg, stack_pointer_rtx,
7229 /* Save regs in stack order. Beginning with VMS PV. */
7230 if (TARGET_ABI_OPEN_VMS && alpha_procedure_type == PT_STACK)
7232 mem = gen_rtx_MEM (DImode, stack_pointer_rtx);
7233 set_mem_alias_set (mem, alpha_sr_alias_set);
7234 FRP (emit_move_insn (mem, gen_rtx_REG (DImode, REG_PV)));
7237 /* Save register RA next. */
7238 if (imask & (1UL << REG_RA))
7240 mem = gen_rtx_MEM (DImode, plus_constant (sa_reg, reg_offset));
7241 set_mem_alias_set (mem, alpha_sr_alias_set);
7242 FRP (emit_move_insn (mem, gen_rtx_REG (DImode, REG_RA)));
7243 imask &= ~(1UL << REG_RA);
7247 /* Now save any other registers required to be saved. */
7248 for (i = 0; i < 31; i++)
7249 if (imask & (1UL << i))
7251 mem = gen_rtx_MEM (DImode, plus_constant (sa_reg, reg_offset));
7252 set_mem_alias_set (mem, alpha_sr_alias_set);
7253 FRP (emit_move_insn (mem, gen_rtx_REG (DImode, i)));
7257 /* Store a zero if requested for unwinding. */
7258 if (imask & (1UL << 31))
7262 mem = gen_rtx_MEM (DImode, plus_constant (sa_reg, reg_offset));
7263 set_mem_alias_set (mem, alpha_sr_alias_set);
7264 insn = emit_move_insn (mem, const0_rtx);
7266 RTX_FRAME_RELATED_P (insn) = 1;
7267 t = gen_rtx_REG (Pmode, 31);
7268 t = gen_rtx_SET (VOIDmode, mem, t);
7269 t = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, t, REG_NOTES (insn));
7270 REG_NOTES (insn) = t;
7275 for (i = 0; i < 31; i++)
7276 if (fmask & (1UL << i))
7278 mem = gen_rtx_MEM (DFmode, plus_constant (sa_reg, reg_offset));
7279 set_mem_alias_set (mem, alpha_sr_alias_set);
7280 FRP (emit_move_insn (mem, gen_rtx_REG (DFmode, i+32)));
7284 else if (TARGET_ABI_UNICOSMK && alpha_procedure_type == PT_STACK)
7286 /* The standard frame on the T3E includes space for saving registers.
7287 We just have to use it. We don't have to save the return address and
7288 the old frame pointer here - they are saved in the DSIB. */
7291 for (i = 9; i < 15; i++)
7292 if (imask & (1UL << i))
7294 mem = gen_rtx_MEM (DImode, plus_constant(hard_frame_pointer_rtx,
7296 set_mem_alias_set (mem, alpha_sr_alias_set);
7297 FRP (emit_move_insn (mem, gen_rtx_REG (DImode, i)));
7300 for (i = 2; i < 10; i++)
7301 if (fmask & (1UL << i))
7303 mem = gen_rtx_MEM (DFmode, plus_constant (hard_frame_pointer_rtx,
7305 set_mem_alias_set (mem, alpha_sr_alias_set);
7306 FRP (emit_move_insn (mem, gen_rtx_REG (DFmode, i+32)));
7311 if (TARGET_ABI_OPEN_VMS)
7313 if (alpha_procedure_type == PT_REGISTER)
7314 /* Register frame procedures save the fp.
7315 ?? Ought to have a dwarf2 save for this. */
7316 emit_move_insn (gen_rtx_REG (DImode, vms_save_fp_regno),
7317 hard_frame_pointer_rtx);
7319 if (alpha_procedure_type != PT_NULL && vms_base_regno != REG_PV)
7320 emit_insn (gen_force_movdi (gen_rtx_REG (DImode, vms_base_regno),
7321 gen_rtx_REG (DImode, REG_PV)));
7323 if (alpha_procedure_type != PT_NULL
7324 && vms_unwind_regno == HARD_FRAME_POINTER_REGNUM)
7325 FRP (emit_move_insn (hard_frame_pointer_rtx, stack_pointer_rtx));
7327 /* If we have to allocate space for outgoing args, do it now. */
7328 if (current_function_outgoing_args_size != 0)
7331 = emit_move_insn (stack_pointer_rtx,
7333 (hard_frame_pointer_rtx,
7335 (current_function_outgoing_args_size))));
7337 /* Only set FRAME_RELATED_P on the stack adjustment we just emitted
7338 if ! frame_pointer_needed. Setting the bit will change the CFA
7339 computation rule to use sp again, which would be wrong if we had
7340 frame_pointer_needed, as this means sp might move unpredictably
7344 frame_pointer_needed
7345 => vms_unwind_regno == HARD_FRAME_POINTER_REGNUM
7347 current_function_outgoing_args_size != 0
7348 => alpha_procedure_type != PT_NULL,
7350 so when we are not setting the bit here, we are guaranteed to
7351 have emitted an FRP frame pointer update just before. */
7352 RTX_FRAME_RELATED_P (seq) = ! frame_pointer_needed;
7355 else if (!TARGET_ABI_UNICOSMK)
7357 /* If we need a frame pointer, set it from the stack pointer. */
7358 if (frame_pointer_needed)
7360 if (TARGET_CAN_FAULT_IN_PROLOGUE)
7361 FRP (emit_move_insn (hard_frame_pointer_rtx, stack_pointer_rtx));
7363 /* This must always be the last instruction in the
7364 prologue, thus we emit a special move + clobber. */
7365 FRP (emit_insn (gen_init_fp (hard_frame_pointer_rtx,
7366 stack_pointer_rtx, sa_reg)));
7370 /* The ABIs for VMS and OSF/1 say that while we can schedule insns into
7371 the prologue, for exception handling reasons, we cannot do this for
7372 any insn that might fault. We could prevent this for mems with a
7373 (clobber:BLK (scratch)), but this doesn't work for fp insns. So we
7374 have to prevent all such scheduling with a blockage.
7376 Linux, on the other hand, never bothered to implement OSF/1's
7377 exception handling, and so doesn't care about such things. Anyone
7378 planning to use dwarf2 frame-unwind info can also omit the blockage. */
7380 if (! TARGET_CAN_FAULT_IN_PROLOGUE)
7381 emit_insn (gen_blockage ());
7384 /* Output the textual info surrounding the prologue. */
7387 alpha_start_function (FILE *file, const char *fnname,
7388 tree decl ATTRIBUTE_UNUSED)
7390 unsigned long imask = 0;
7391 unsigned long fmask = 0;
7392 /* Stack space needed for pushing registers clobbered by us. */
7393 HOST_WIDE_INT sa_size;
7394 /* Complete stack size needed. */
7395 unsigned HOST_WIDE_INT frame_size;
7396 /* Offset from base reg to register save area. */
7397 HOST_WIDE_INT reg_offset;
7398 char *entry_label = (char *) alloca (strlen (fnname) + 6);
7401 /* Don't emit an extern directive for functions defined in the same file. */
7402 if (TARGET_ABI_UNICOSMK)
7405 name_tree = get_identifier (fnname);
7406 TREE_ASM_WRITTEN (name_tree) = 1;
7409 alpha_fnname = fnname;
7410 sa_size = alpha_sa_size ();
7412 frame_size = get_frame_size ();
7413 if (TARGET_ABI_OPEN_VMS)
7414 frame_size = ALPHA_ROUND (sa_size
7415 + (alpha_procedure_type == PT_STACK ? 8 : 0)
7417 + current_function_pretend_args_size);
7418 else if (TARGET_ABI_UNICOSMK)
7419 frame_size = ALPHA_ROUND (sa_size
7420 + (alpha_procedure_type == PT_STACK ? 48 : 0))
7421 + ALPHA_ROUND (frame_size
7422 + current_function_outgoing_args_size);
7424 frame_size = (ALPHA_ROUND (current_function_outgoing_args_size)
7426 + ALPHA_ROUND (frame_size
7427 + current_function_pretend_args_size));
7429 if (TARGET_ABI_OPEN_VMS)
7432 reg_offset = ALPHA_ROUND (current_function_outgoing_args_size);
7434 alpha_sa_mask (&imask, &fmask);
7436 /* Ecoff can handle multiple .file directives, so put out file and lineno.
7437 We have to do that before the .ent directive as we cannot switch
7438 files within procedures with native ecoff because line numbers are
7439 linked to procedure descriptors.
7440 Outputting the lineno helps debugging of one line functions as they
7441 would otherwise get no line number at all. Please note that we would
7442 like to put out last_linenum from final.c, but it is not accessible. */
7444 if (write_symbols == SDB_DEBUG)
7446 #ifdef ASM_OUTPUT_SOURCE_FILENAME
7447 ASM_OUTPUT_SOURCE_FILENAME (file,
7448 DECL_SOURCE_FILE (current_function_decl));
7450 #ifdef ASM_OUTPUT_SOURCE_LINE
7451 if (debug_info_level != DINFO_LEVEL_TERSE)
7452 ASM_OUTPUT_SOURCE_LINE (file,
7453 DECL_SOURCE_LINE (current_function_decl), 0);
7457 /* Issue function start and label. */
7458 if (TARGET_ABI_OPEN_VMS
7459 || (!TARGET_ABI_UNICOSMK && !flag_inhibit_size_directive))
7461 fputs ("\t.ent ", file);
7462 assemble_name (file, fnname);
7465 /* If the function needs GP, we'll write the "..ng" label there.
7466 Otherwise, do it here. */
7468 && ! alpha_function_needs_gp
7469 && ! current_function_is_thunk)
7472 assemble_name (file, fnname);
7473 fputs ("..ng:\n", file);
7477 strcpy (entry_label, fnname);
7478 if (TARGET_ABI_OPEN_VMS)
7479 strcat (entry_label, "..en");
7481 /* For public functions, the label must be globalized by appending an
7482 additional colon. */
7483 if (TARGET_ABI_UNICOSMK && TREE_PUBLIC (decl))
7484 strcat (entry_label, ":");
7486 ASM_OUTPUT_LABEL (file, entry_label);
7487 inside_function = TRUE;
7489 if (TARGET_ABI_OPEN_VMS)
7490 fprintf (file, "\t.base $%d\n", vms_base_regno);
7492 if (!TARGET_ABI_OPEN_VMS && !TARGET_ABI_UNICOSMK && TARGET_IEEE_CONFORMANT
7493 && !flag_inhibit_size_directive)
7495 /* Set flags in procedure descriptor to request IEEE-conformant
7496 math-library routines. The value we set it to is PDSC_EXC_IEEE
7497 (/usr/include/pdsc.h). */
7498 fputs ("\t.eflag 48\n", file);
7501 /* Set up offsets to alpha virtual arg/local debugging pointer. */
7502 alpha_auto_offset = -frame_size + current_function_pretend_args_size;
7503 alpha_arg_offset = -frame_size + 48;
7505 /* Describe our frame. If the frame size is larger than an integer,
7506 print it as zero to avoid an assembler error. We won't be
7507 properly describing such a frame, but that's the best we can do. */
7508 if (TARGET_ABI_UNICOSMK)
7510 else if (TARGET_ABI_OPEN_VMS)
7511 fprintf (file, "\t.frame $%d," HOST_WIDE_INT_PRINT_DEC ",$26,"
7512 HOST_WIDE_INT_PRINT_DEC "\n",
7514 frame_size >= (1UL << 31) ? 0 : frame_size,
7516 else if (!flag_inhibit_size_directive)
7517 fprintf (file, "\t.frame $%d," HOST_WIDE_INT_PRINT_DEC ",$26,%d\n",
7518 (frame_pointer_needed
7519 ? HARD_FRAME_POINTER_REGNUM : STACK_POINTER_REGNUM),
7520 frame_size >= (1UL << 31) ? 0 : frame_size,
7521 current_function_pretend_args_size);
7523 /* Describe which registers were spilled. */
7524 if (TARGET_ABI_UNICOSMK)
7526 else if (TARGET_ABI_OPEN_VMS)
7529 /* ??? Does VMS care if mask contains ra? The old code didn't
7530 set it, so I don't here. */
7531 fprintf (file, "\t.mask 0x%lx,0\n", imask & ~(1UL << REG_RA));
7533 fprintf (file, "\t.fmask 0x%lx,0\n", fmask);
7534 if (alpha_procedure_type == PT_REGISTER)
7535 fprintf (file, "\t.fp_save $%d\n", vms_save_fp_regno);
7537 else if (!flag_inhibit_size_directive)
7541 fprintf (file, "\t.mask 0x%lx," HOST_WIDE_INT_PRINT_DEC "\n", imask,
7542 frame_size >= (1UL << 31) ? 0 : reg_offset - frame_size);
7544 for (i = 0; i < 32; ++i)
7545 if (imask & (1UL << i))
7550 fprintf (file, "\t.fmask 0x%lx," HOST_WIDE_INT_PRINT_DEC "\n", fmask,
7551 frame_size >= (1UL << 31) ? 0 : reg_offset - frame_size);
7554 #if TARGET_ABI_OPEN_VMS
7555 /* Ifdef'ed cause link_section are only available then. */
7556 readonly_data_section ();
7557 fprintf (file, "\t.align 3\n");
7558 assemble_name (file, fnname); fputs ("..na:\n", file);
7559 fputs ("\t.ascii \"", file);
7560 assemble_name (file, fnname);
7561 fputs ("\\0\"\n", file);
7562 alpha_need_linkage (fnname, 1);
7567 /* Emit the .prologue note at the scheduled end of the prologue. */
7570 alpha_output_function_end_prologue (FILE *file)
7572 if (TARGET_ABI_UNICOSMK)
7574 else if (TARGET_ABI_OPEN_VMS)
7575 fputs ("\t.prologue\n", file);
7576 else if (TARGET_ABI_WINDOWS_NT)
7577 fputs ("\t.prologue 0\n", file);
7578 else if (!flag_inhibit_size_directive)
7579 fprintf (file, "\t.prologue %d\n",
7580 alpha_function_needs_gp || current_function_is_thunk);
7583 /* Write function epilogue. */
7585 /* ??? At some point we will want to support full unwind, and so will
7586 need to mark the epilogue as well. At the moment, we just confuse
7589 #define FRP(exp) exp
7592 alpha_expand_epilogue (void)
7594 /* Registers to save. */
7595 unsigned long imask = 0;
7596 unsigned long fmask = 0;
7597 /* Stack space needed for pushing registers clobbered by us. */
7598 HOST_WIDE_INT sa_size;
7599 /* Complete stack size needed. */
7600 HOST_WIDE_INT frame_size;
7601 /* Offset from base reg to register save area. */
7602 HOST_WIDE_INT reg_offset;
7603 int fp_is_frame_pointer, fp_offset;
7604 rtx sa_reg, sa_reg_exp = NULL;
7605 rtx sp_adj1, sp_adj2, mem;
7609 sa_size = alpha_sa_size ();
7611 frame_size = get_frame_size ();
7612 if (TARGET_ABI_OPEN_VMS)
7613 frame_size = ALPHA_ROUND (sa_size
7614 + (alpha_procedure_type == PT_STACK ? 8 : 0)
7616 + current_function_pretend_args_size);
7617 else if (TARGET_ABI_UNICOSMK)
7618 frame_size = ALPHA_ROUND (sa_size
7619 + (alpha_procedure_type == PT_STACK ? 48 : 0))
7620 + ALPHA_ROUND (frame_size
7621 + current_function_outgoing_args_size);
7623 frame_size = (ALPHA_ROUND (current_function_outgoing_args_size)
7625 + ALPHA_ROUND (frame_size
7626 + current_function_pretend_args_size));
7628 if (TARGET_ABI_OPEN_VMS)
7630 if (alpha_procedure_type == PT_STACK)
7636 reg_offset = ALPHA_ROUND (current_function_outgoing_args_size);
7638 alpha_sa_mask (&imask, &fmask);
7641 = ((TARGET_ABI_OPEN_VMS && alpha_procedure_type == PT_STACK)
7642 || (!TARGET_ABI_OPEN_VMS && frame_pointer_needed));
7644 sa_reg = stack_pointer_rtx;
7646 if (current_function_calls_eh_return)
7647 eh_ofs = EH_RETURN_STACKADJ_RTX;
7651 if (!TARGET_ABI_UNICOSMK && sa_size)
7653 /* If we have a frame pointer, restore SP from it. */
7654 if ((TARGET_ABI_OPEN_VMS
7655 && vms_unwind_regno == HARD_FRAME_POINTER_REGNUM)
7656 || (!TARGET_ABI_OPEN_VMS && frame_pointer_needed))
7657 FRP (emit_move_insn (stack_pointer_rtx, hard_frame_pointer_rtx));
7659 /* Cope with very large offsets to the register save area. */
7660 if (reg_offset + sa_size > 0x8000)
7662 int low = ((reg_offset & 0xffff) ^ 0x8000) - 0x8000;
7665 if (low + sa_size <= 0x8000)
7666 bias = reg_offset - low, reg_offset = low;
7668 bias = reg_offset, reg_offset = 0;
7670 sa_reg = gen_rtx_REG (DImode, 22);
7671 sa_reg_exp = plus_constant (stack_pointer_rtx, bias);
7673 FRP (emit_move_insn (sa_reg, sa_reg_exp));
7676 /* Restore registers in order, excepting a true frame pointer. */
7678 mem = gen_rtx_MEM (DImode, plus_constant (sa_reg, reg_offset));
7680 set_mem_alias_set (mem, alpha_sr_alias_set);
7681 FRP (emit_move_insn (gen_rtx_REG (DImode, REG_RA), mem));
7684 imask &= ~(1UL << REG_RA);
7686 for (i = 0; i < 31; ++i)
7687 if (imask & (1UL << i))
7689 if (i == HARD_FRAME_POINTER_REGNUM && fp_is_frame_pointer)
7690 fp_offset = reg_offset;
7693 mem = gen_rtx_MEM (DImode, plus_constant(sa_reg, reg_offset));
7694 set_mem_alias_set (mem, alpha_sr_alias_set);
7695 FRP (emit_move_insn (gen_rtx_REG (DImode, i), mem));
7700 if (imask & (1UL << 31))
7703 for (i = 0; i < 31; ++i)
7704 if (fmask & (1UL << i))
7706 mem = gen_rtx_MEM (DFmode, plus_constant(sa_reg, reg_offset));
7707 set_mem_alias_set (mem, alpha_sr_alias_set);
7708 FRP (emit_move_insn (gen_rtx_REG (DFmode, i+32), mem));
7712 else if (TARGET_ABI_UNICOSMK && alpha_procedure_type == PT_STACK)
7714 /* Restore callee-saved general-purpose registers. */
7718 for (i = 9; i < 15; i++)
7719 if (imask & (1UL << i))
7721 mem = gen_rtx_MEM (DImode, plus_constant(hard_frame_pointer_rtx,
7723 set_mem_alias_set (mem, alpha_sr_alias_set);
7724 FRP (emit_move_insn (gen_rtx_REG (DImode, i), mem));
7728 for (i = 2; i < 10; i++)
7729 if (fmask & (1UL << i))
7731 mem = gen_rtx_MEM (DFmode, plus_constant(hard_frame_pointer_rtx,
7733 set_mem_alias_set (mem, alpha_sr_alias_set);
7734 FRP (emit_move_insn (gen_rtx_REG (DFmode, i+32), mem));
7738 /* Restore the return address from the DSIB. */
7740 mem = gen_rtx_MEM (DImode, plus_constant(hard_frame_pointer_rtx, -8));
7741 set_mem_alias_set (mem, alpha_sr_alias_set);
7742 FRP (emit_move_insn (gen_rtx_REG (DImode, REG_RA), mem));
7745 if (frame_size || eh_ofs)
7747 sp_adj1 = stack_pointer_rtx;
7751 sp_adj1 = gen_rtx_REG (DImode, 23);
7752 emit_move_insn (sp_adj1,
7753 gen_rtx_PLUS (Pmode, stack_pointer_rtx, eh_ofs));
7756 /* If the stack size is large, begin computation into a temporary
7757 register so as not to interfere with a potential fp restore,
7758 which must be consecutive with an SP restore. */
7759 if (frame_size < 32768
7760 && ! (TARGET_ABI_UNICOSMK && current_function_calls_alloca))
7761 sp_adj2 = GEN_INT (frame_size);
7762 else if (TARGET_ABI_UNICOSMK)
7764 sp_adj1 = gen_rtx_REG (DImode, 23);
7765 FRP (emit_move_insn (sp_adj1, hard_frame_pointer_rtx));
7766 sp_adj2 = const0_rtx;
7768 else if (frame_size < 0x40007fffL)
7770 int low = ((frame_size & 0xffff) ^ 0x8000) - 0x8000;
7772 sp_adj2 = plus_constant (sp_adj1, frame_size - low);
7773 if (sa_reg_exp && rtx_equal_p (sa_reg_exp, sp_adj2))
7777 sp_adj1 = gen_rtx_REG (DImode, 23);
7778 FRP (emit_move_insn (sp_adj1, sp_adj2));
7780 sp_adj2 = GEN_INT (low);
7784 rtx tmp = gen_rtx_REG (DImode, 23);
7785 FRP (sp_adj2 = alpha_emit_set_const (tmp, DImode, frame_size, 3));
7788 /* We can't drop new things to memory this late, afaik,
7789 so build it up by pieces. */
7790 FRP (sp_adj2 = alpha_emit_set_long_const (tmp, frame_size,
7791 -(frame_size < 0)));
7797 /* From now on, things must be in order. So emit blockages. */
7799 /* Restore the frame pointer. */
7800 if (TARGET_ABI_UNICOSMK)
7802 emit_insn (gen_blockage ());
7803 mem = gen_rtx_MEM (DImode,
7804 plus_constant (hard_frame_pointer_rtx, -16));
7805 set_mem_alias_set (mem, alpha_sr_alias_set);
7806 FRP (emit_move_insn (hard_frame_pointer_rtx, mem));
7808 else if (fp_is_frame_pointer)
7810 emit_insn (gen_blockage ());
7811 mem = gen_rtx_MEM (DImode, plus_constant (sa_reg, fp_offset));
7812 set_mem_alias_set (mem, alpha_sr_alias_set);
7813 FRP (emit_move_insn (hard_frame_pointer_rtx, mem));
7815 else if (TARGET_ABI_OPEN_VMS)
7817 emit_insn (gen_blockage ());
7818 FRP (emit_move_insn (hard_frame_pointer_rtx,
7819 gen_rtx_REG (DImode, vms_save_fp_regno)));
7822 /* Restore the stack pointer. */
7823 emit_insn (gen_blockage ());
7824 if (sp_adj2 == const0_rtx)
7825 FRP (emit_move_insn (stack_pointer_rtx, sp_adj1));
7827 FRP (emit_move_insn (stack_pointer_rtx,
7828 gen_rtx_PLUS (DImode, sp_adj1, sp_adj2)));
7832 if (TARGET_ABI_OPEN_VMS && alpha_procedure_type == PT_REGISTER)
7834 emit_insn (gen_blockage ());
7835 FRP (emit_move_insn (hard_frame_pointer_rtx,
7836 gen_rtx_REG (DImode, vms_save_fp_regno)));
7838 else if (TARGET_ABI_UNICOSMK && alpha_procedure_type != PT_STACK)
7840 /* Decrement the frame pointer if the function does not have a
7843 emit_insn (gen_blockage ());
7844 FRP (emit_insn (gen_adddi3 (hard_frame_pointer_rtx,
7845 hard_frame_pointer_rtx, constm1_rtx)));
7850 /* Output the rest of the textual info surrounding the epilogue. */
7853 alpha_end_function (FILE *file, const char *fnname, tree decl ATTRIBUTE_UNUSED)
7855 /* End the function. */
7856 if (!TARGET_ABI_UNICOSMK && !flag_inhibit_size_directive)
7858 fputs ("\t.end ", file);
7859 assemble_name (file, fnname);
7862 inside_function = FALSE;
7864 #if TARGET_ABI_OPEN_VMS
7865 alpha_write_linkage (file, fnname, decl);
7868 /* Output jump tables and the static subroutine information block. */
7869 if (TARGET_ABI_UNICOSMK)
7871 unicosmk_output_ssib (file, fnname);
7872 unicosmk_output_deferred_case_vectors (file);
7877 /* Emit a tail call to FUNCTION after adjusting THIS by DELTA.
7879 In order to avoid the hordes of differences between generated code
7880 with and without TARGET_EXPLICIT_RELOCS, and to avoid duplicating
7881 lots of code loading up large constants, generate rtl and emit it
7882 instead of going straight to text.
7884 Not sure why this idea hasn't been explored before... */
7887 alpha_output_mi_thunk_osf (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED,
7888 HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset,
7891 HOST_WIDE_INT hi, lo;
7892 rtx this, insn, funexp;
7894 /* We always require a valid GP. */
7895 emit_insn (gen_prologue_ldgp ());
7896 emit_note (NOTE_INSN_PROLOGUE_END);
7898 /* Find the "this" pointer. If the function returns a structure,
7899 the structure return pointer is in $16. */
7900 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function))
7901 this = gen_rtx_REG (Pmode, 17);
7903 this = gen_rtx_REG (Pmode, 16);
7905 /* Add DELTA. When possible we use ldah+lda. Otherwise load the
7906 entire constant for the add. */
7907 lo = ((delta & 0xffff) ^ 0x8000) - 0x8000;
7908 hi = (((delta - lo) & 0xffffffff) ^ 0x80000000) - 0x80000000;
7909 if (hi + lo == delta)
7912 emit_insn (gen_adddi3 (this, this, GEN_INT (hi)));
7914 emit_insn (gen_adddi3 (this, this, GEN_INT (lo)));
7918 rtx tmp = alpha_emit_set_long_const (gen_rtx_REG (Pmode, 0),
7919 delta, -(delta < 0));
7920 emit_insn (gen_adddi3 (this, this, tmp));
7923 /* Add a delta stored in the vtable at VCALL_OFFSET. */
7928 tmp = gen_rtx_REG (Pmode, 0);
7929 emit_move_insn (tmp, gen_rtx_MEM (Pmode, this));
7931 lo = ((vcall_offset & 0xffff) ^ 0x8000) - 0x8000;
7932 hi = (((vcall_offset - lo) & 0xffffffff) ^ 0x80000000) - 0x80000000;
7933 if (hi + lo == vcall_offset)
7936 emit_insn (gen_adddi3 (tmp, tmp, GEN_INT (hi)));
7940 tmp2 = alpha_emit_set_long_const (gen_rtx_REG (Pmode, 1),
7941 vcall_offset, -(vcall_offset < 0));
7942 emit_insn (gen_adddi3 (tmp, tmp, tmp2));
7946 tmp2 = gen_rtx_PLUS (Pmode, tmp, GEN_INT (lo));
7949 emit_move_insn (tmp, gen_rtx_MEM (Pmode, tmp2));
7951 emit_insn (gen_adddi3 (this, this, tmp));
7954 /* Generate a tail call to the target function. */
7955 if (! TREE_USED (function))
7957 assemble_external (function);
7958 TREE_USED (function) = 1;
7960 funexp = XEXP (DECL_RTL (function), 0);
7961 funexp = gen_rtx_MEM (FUNCTION_MODE, funexp);
7962 insn = emit_call_insn (gen_sibcall (funexp, const0_rtx));
7963 SIBLING_CALL_P (insn) = 1;
7965 /* Run just enough of rest_of_compilation to get the insns emitted.
7966 There's not really enough bulk here to make other passes such as
7967 instruction scheduling worth while. Note that use_thunk calls
7968 assemble_start_function and assemble_end_function. */
7969 insn = get_insns ();
7970 insn_locators_initialize ();
7971 shorten_branches (insn);
7972 final_start_function (insn, file, 1);
7973 final (insn, file, 1, 0);
7974 final_end_function ();
7976 #endif /* TARGET_ABI_OSF */
7978 /* Debugging support. */
7982 /* Count the number of sdb related labels are generated (to find block
7983 start and end boundaries). */
7985 int sdb_label_count = 0;
7987 /* Next label # for each statement. */
7989 static int sym_lineno = 0;
7991 /* Count the number of .file directives, so that .loc is up to date. */
7993 static int num_source_filenames = 0;
7995 /* Name of the file containing the current function. */
7997 static const char *current_function_file = "";
7999 /* Offsets to alpha virtual arg/local debugging pointers. */
8001 long alpha_arg_offset;
8002 long alpha_auto_offset;
8004 /* Emit a new filename to a stream. */
8007 alpha_output_filename (FILE *stream, const char *name)
8009 static int first_time = TRUE;
8010 char ltext_label_name[100];
8015 ++num_source_filenames;
8016 current_function_file = name;
8017 fprintf (stream, "\t.file\t%d ", num_source_filenames);
8018 output_quoted_string (stream, name);
8019 fprintf (stream, "\n");
8020 if (!TARGET_GAS && write_symbols == DBX_DEBUG)
8021 fprintf (stream, "\t#@stabs\n");
8024 else if (write_symbols == DBX_DEBUG)
8026 ASM_GENERATE_INTERNAL_LABEL (ltext_label_name, "Ltext", 0);
8027 fprintf (stream, "%s", ASM_STABS_OP);
8028 output_quoted_string (stream, name);
8029 fprintf (stream, ",%d,0,0,%s\n", N_SOL, <ext_label_name[1]);
8032 else if (name != current_function_file
8033 && strcmp (name, current_function_file) != 0)
8035 if (inside_function && ! TARGET_GAS)
8036 fprintf (stream, "\t#.file\t%d ", num_source_filenames);
8039 ++num_source_filenames;
8040 current_function_file = name;
8041 fprintf (stream, "\t.file\t%d ", num_source_filenames);
8044 output_quoted_string (stream, name);
8045 fprintf (stream, "\n");
8049 /* Emit a linenumber to a stream. */
8052 alpha_output_lineno (FILE *stream, int line)
8054 if (write_symbols == DBX_DEBUG)
8056 /* mips-tfile doesn't understand .stabd directives. */
8058 fprintf (stream, "$LM%d:\n%s%d,0,%d,$LM%d\n",
8059 sym_lineno, ASM_STABN_OP, N_SLINE, line, sym_lineno);
8062 fprintf (stream, "\n\t.loc\t%d %d\n", num_source_filenames, line);
8065 /* Structure to show the current status of registers and memory. */
8067 struct shadow_summary
8070 unsigned int i : 31; /* Mask of int regs */
8071 unsigned int fp : 31; /* Mask of fp regs */
8072 unsigned int mem : 1; /* mem == imem | fpmem */
8076 /* Summary the effects of expression X on the machine. Update SUM, a pointer
8077 to the summary structure. SET is nonzero if the insn is setting the
8078 object, otherwise zero. */
8081 summarize_insn (rtx x, struct shadow_summary *sum, int set)
8083 const char *format_ptr;
8089 switch (GET_CODE (x))
8091 /* ??? Note that this case would be incorrect if the Alpha had a
8092 ZERO_EXTRACT in SET_DEST. */
8094 summarize_insn (SET_SRC (x), sum, 0);
8095 summarize_insn (SET_DEST (x), sum, 1);
8099 summarize_insn (XEXP (x, 0), sum, 1);
8103 summarize_insn (XEXP (x, 0), sum, 0);
8107 for (i = ASM_OPERANDS_INPUT_LENGTH (x) - 1; i >= 0; i--)
8108 summarize_insn (ASM_OPERANDS_INPUT (x, i), sum, 0);
8112 for (i = XVECLEN (x, 0) - 1; i >= 0; i--)
8113 summarize_insn (XVECEXP (x, 0, i), sum, 0);
8117 summarize_insn (SUBREG_REG (x), sum, 0);
8122 int regno = REGNO (x);
8123 unsigned long mask = ((unsigned long) 1) << (regno % 32);
8125 if (regno == 31 || regno == 63)
8131 sum->defd.i |= mask;
8133 sum->defd.fp |= mask;
8138 sum->used.i |= mask;
8140 sum->used.fp |= mask;
8151 /* Find the regs used in memory address computation: */
8152 summarize_insn (XEXP (x, 0), sum, 0);
8155 case CONST_INT: case CONST_DOUBLE:
8156 case SYMBOL_REF: case LABEL_REF: case CONST:
8157 case SCRATCH: case ASM_INPUT:
8160 /* Handle common unary and binary ops for efficiency. */
8161 case COMPARE: case PLUS: case MINUS: case MULT: case DIV:
8162 case MOD: case UDIV: case UMOD: case AND: case IOR:
8163 case XOR: case ASHIFT: case ROTATE: case ASHIFTRT: case LSHIFTRT:
8164 case ROTATERT: case SMIN: case SMAX: case UMIN: case UMAX:
8165 case NE: case EQ: case GE: case GT: case LE:
8166 case LT: case GEU: case GTU: case LEU: case LTU:
8167 summarize_insn (XEXP (x, 0), sum, 0);
8168 summarize_insn (XEXP (x, 1), sum, 0);
8171 case NEG: case NOT: case SIGN_EXTEND: case ZERO_EXTEND:
8172 case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE: case FLOAT:
8173 case FIX: case UNSIGNED_FLOAT: case UNSIGNED_FIX: case ABS:
8174 case SQRT: case FFS:
8175 summarize_insn (XEXP (x, 0), sum, 0);
8179 format_ptr = GET_RTX_FORMAT (GET_CODE (x));
8180 for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
8181 switch (format_ptr[i])
8184 summarize_insn (XEXP (x, i), sum, 0);
8188 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
8189 summarize_insn (XVECEXP (x, i, j), sum, 0);
8201 /* Ensure a sufficient number of `trapb' insns are in the code when
8202 the user requests code with a trap precision of functions or
8205 In naive mode, when the user requests a trap-precision of
8206 "instruction", a trapb is needed after every instruction that may
8207 generate a trap. This ensures that the code is resumption safe but
8210 When optimizations are turned on, we delay issuing a trapb as long
8211 as possible. In this context, a trap shadow is the sequence of
8212 instructions that starts with a (potentially) trap generating
8213 instruction and extends to the next trapb or call_pal instruction
8214 (but GCC never generates call_pal by itself). We can delay (and
8215 therefore sometimes omit) a trapb subject to the following
8218 (a) On entry to the trap shadow, if any Alpha register or memory
8219 location contains a value that is used as an operand value by some
8220 instruction in the trap shadow (live on entry), then no instruction
8221 in the trap shadow may modify the register or memory location.
8223 (b) Within the trap shadow, the computation of the base register
8224 for a memory load or store instruction may not involve using the
8225 result of an instruction that might generate an UNPREDICTABLE
8228 (c) Within the trap shadow, no register may be used more than once
8229 as a destination register. (This is to make life easier for the
8232 (d) The trap shadow may not include any branch instructions. */
8235 alpha_handle_trap_shadows (void)
8237 struct shadow_summary shadow;
8238 int trap_pending, exception_nesting;
8242 exception_nesting = 0;
8245 shadow.used.mem = 0;
8246 shadow.defd = shadow.used;
8248 for (i = get_insns (); i ; i = NEXT_INSN (i))
8250 if (GET_CODE (i) == NOTE)
8252 switch (NOTE_LINE_NUMBER (i))
8254 case NOTE_INSN_EH_REGION_BEG:
8255 exception_nesting++;
8260 case NOTE_INSN_EH_REGION_END:
8261 exception_nesting--;
8266 case NOTE_INSN_EPILOGUE_BEG:
8267 if (trap_pending && alpha_tp >= ALPHA_TP_FUNC)
8272 else if (trap_pending)
8274 if (alpha_tp == ALPHA_TP_FUNC)
8276 if (GET_CODE (i) == JUMP_INSN
8277 && GET_CODE (PATTERN (i)) == RETURN)
8280 else if (alpha_tp == ALPHA_TP_INSN)
8284 struct shadow_summary sum;
8289 sum.defd = sum.used;
8291 switch (GET_CODE (i))
8294 /* Annoyingly, get_attr_trap will abort on these. */
8295 if (GET_CODE (PATTERN (i)) == USE
8296 || GET_CODE (PATTERN (i)) == CLOBBER)
8299 summarize_insn (PATTERN (i), &sum, 0);
8301 if ((sum.defd.i & shadow.defd.i)
8302 || (sum.defd.fp & shadow.defd.fp))
8304 /* (c) would be violated */
8308 /* Combine shadow with summary of current insn: */
8309 shadow.used.i |= sum.used.i;
8310 shadow.used.fp |= sum.used.fp;
8311 shadow.used.mem |= sum.used.mem;
8312 shadow.defd.i |= sum.defd.i;
8313 shadow.defd.fp |= sum.defd.fp;
8314 shadow.defd.mem |= sum.defd.mem;
8316 if ((sum.defd.i & shadow.used.i)
8317 || (sum.defd.fp & shadow.used.fp)
8318 || (sum.defd.mem & shadow.used.mem))
8320 /* (a) would be violated (also takes care of (b)) */
8321 if (get_attr_trap (i) == TRAP_YES
8322 && ((sum.defd.i & sum.used.i)
8323 || (sum.defd.fp & sum.used.fp)))
8342 n = emit_insn_before (gen_trapb (), i);
8343 PUT_MODE (n, TImode);
8344 PUT_MODE (i, TImode);
8348 shadow.used.mem = 0;
8349 shadow.defd = shadow.used;
8354 if ((exception_nesting > 0 || alpha_tp >= ALPHA_TP_FUNC)
8355 && GET_CODE (i) == INSN
8356 && GET_CODE (PATTERN (i)) != USE
8357 && GET_CODE (PATTERN (i)) != CLOBBER
8358 && get_attr_trap (i) == TRAP_YES)
8360 if (optimize && !trap_pending)
8361 summarize_insn (PATTERN (i), &shadow, 0);
8367 /* Alpha can only issue instruction groups simultaneously if they are
8368 suitably aligned. This is very processor-specific. */
8370 enum alphaev4_pipe {
8377 enum alphaev5_pipe {
8388 static enum alphaev4_pipe
8389 alphaev4_insn_pipe (rtx insn)
8391 if (recog_memoized (insn) < 0)
8393 if (get_attr_length (insn) != 4)
8396 switch (get_attr_type (insn))
8430 static enum alphaev5_pipe
8431 alphaev5_insn_pipe (rtx insn)
8433 if (recog_memoized (insn) < 0)
8435 if (get_attr_length (insn) != 4)
8438 switch (get_attr_type (insn))
8479 /* IN_USE is a mask of the slots currently filled within the insn group.
8480 The mask bits come from alphaev4_pipe above. If EV4_IBX is set, then
8481 the insn in EV4_IB0 can be swapped by the hardware into EV4_IB1.
8483 LEN is, of course, the length of the group in bytes. */
8486 alphaev4_next_group (rtx insn, int *pin_use, int *plen)
8493 || GET_CODE (PATTERN (insn)) == CLOBBER
8494 || GET_CODE (PATTERN (insn)) == USE)
8499 enum alphaev4_pipe pipe;
8501 pipe = alphaev4_insn_pipe (insn);
8505 /* Force complex instructions to start new groups. */
8509 /* If this is a completely unrecognized insn, its an asm.
8510 We don't know how long it is, so record length as -1 to
8511 signal a needed realignment. */
8512 if (recog_memoized (insn) < 0)
8515 len = get_attr_length (insn);
8519 if (in_use & EV4_IB0)
8521 if (in_use & EV4_IB1)
8526 in_use |= EV4_IB0 | EV4_IBX;
8530 if (in_use & EV4_IB0)
8532 if (!(in_use & EV4_IBX) || (in_use & EV4_IB1))
8540 if (in_use & EV4_IB1)
8550 /* Haifa doesn't do well scheduling branches. */
8551 if (GET_CODE (insn) == JUMP_INSN)
8555 insn = next_nonnote_insn (insn);
8557 if (!insn || ! INSN_P (insn))
8560 /* Let Haifa tell us where it thinks insn group boundaries are. */
8561 if (GET_MODE (insn) == TImode)
8564 if (GET_CODE (insn) == CLOBBER || GET_CODE (insn) == USE)
8569 insn = next_nonnote_insn (insn);
8577 /* IN_USE is a mask of the slots currently filled within the insn group.
8578 The mask bits come from alphaev5_pipe above. If EV5_E01 is set, then
8579 the insn in EV5_E0 can be swapped by the hardware into EV5_E1.
8581 LEN is, of course, the length of the group in bytes. */
8584 alphaev5_next_group (rtx insn, int *pin_use, int *plen)
8591 || GET_CODE (PATTERN (insn)) == CLOBBER
8592 || GET_CODE (PATTERN (insn)) == USE)
8597 enum alphaev5_pipe pipe;
8599 pipe = alphaev5_insn_pipe (insn);
8603 /* Force complex instructions to start new groups. */
8607 /* If this is a completely unrecognized insn, its an asm.
8608 We don't know how long it is, so record length as -1 to
8609 signal a needed realignment. */
8610 if (recog_memoized (insn) < 0)
8613 len = get_attr_length (insn);
8616 /* ??? Most of the places below, we would like to abort, as
8617 it would indicate an error either in Haifa, or in the
8618 scheduling description. Unfortunately, Haifa never
8619 schedules the last instruction of the BB, so we don't
8620 have an accurate TI bit to go off. */
8622 if (in_use & EV5_E0)
8624 if (in_use & EV5_E1)
8629 in_use |= EV5_E0 | EV5_E01;
8633 if (in_use & EV5_E0)
8635 if (!(in_use & EV5_E01) || (in_use & EV5_E1))
8643 if (in_use & EV5_E1)
8649 if (in_use & EV5_FA)
8651 if (in_use & EV5_FM)
8656 in_use |= EV5_FA | EV5_FAM;
8660 if (in_use & EV5_FA)
8666 if (in_use & EV5_FM)
8679 /* Haifa doesn't do well scheduling branches. */
8680 /* ??? If this is predicted not-taken, slotting continues, except
8681 that no more IBR, FBR, or JSR insns may be slotted. */
8682 if (GET_CODE (insn) == JUMP_INSN)
8686 insn = next_nonnote_insn (insn);
8688 if (!insn || ! INSN_P (insn))
8691 /* Let Haifa tell us where it thinks insn group boundaries are. */
8692 if (GET_MODE (insn) == TImode)
8695 if (GET_CODE (insn) == CLOBBER || GET_CODE (insn) == USE)
8700 insn = next_nonnote_insn (insn);
8709 alphaev4_next_nop (int *pin_use)
8711 int in_use = *pin_use;
8714 if (!(in_use & EV4_IB0))
8719 else if ((in_use & (EV4_IBX|EV4_IB1)) == EV4_IBX)
8724 else if (TARGET_FP && !(in_use & EV4_IB1))
8737 alphaev5_next_nop (int *pin_use)
8739 int in_use = *pin_use;
8742 if (!(in_use & EV5_E1))
8747 else if (TARGET_FP && !(in_use & EV5_FA))
8752 else if (TARGET_FP && !(in_use & EV5_FM))
8764 /* The instruction group alignment main loop. */
8767 alpha_align_insns (unsigned int max_align,
8768 rtx (*next_group) (rtx, int *, int *),
8769 rtx (*next_nop) (int *))
8771 /* ALIGN is the known alignment for the insn group. */
8773 /* OFS is the offset of the current insn in the insn group. */
8775 int prev_in_use, in_use, len;
8778 /* Let shorten branches care for assigning alignments to code labels. */
8779 shorten_branches (get_insns ());
8781 if (align_functions < 4)
8783 else if ((unsigned int) align_functions < max_align)
8784 align = align_functions;
8788 ofs = prev_in_use = 0;
8790 if (GET_CODE (i) == NOTE)
8791 i = next_nonnote_insn (i);
8795 next = (*next_group) (i, &in_use, &len);
8797 /* When we see a label, resync alignment etc. */
8798 if (GET_CODE (i) == CODE_LABEL)
8800 unsigned int new_align = 1 << label_to_alignment (i);
8802 if (new_align >= align)
8804 align = new_align < max_align ? new_align : max_align;
8808 else if (ofs & (new_align-1))
8809 ofs = (ofs | (new_align-1)) + 1;
8814 /* Handle complex instructions special. */
8815 else if (in_use == 0)
8817 /* Asms will have length < 0. This is a signal that we have
8818 lost alignment knowledge. Assume, however, that the asm
8819 will not mis-align instructions. */
8828 /* If the known alignment is smaller than the recognized insn group,
8829 realign the output. */
8830 else if ((int) align < len)
8832 unsigned int new_log_align = len > 8 ? 4 : 3;
8835 where = prev = prev_nonnote_insn (i);
8836 if (!where || GET_CODE (where) != CODE_LABEL)
8839 /* Can't realign between a call and its gp reload. */
8840 if (! (TARGET_EXPLICIT_RELOCS
8841 && prev && GET_CODE (prev) == CALL_INSN))
8843 emit_insn_before (gen_realign (GEN_INT (new_log_align)), where);
8844 align = 1 << new_log_align;
8849 /* If the group won't fit in the same INT16 as the previous,
8850 we need to add padding to keep the group together. Rather
8851 than simply leaving the insn filling to the assembler, we
8852 can make use of the knowledge of what sorts of instructions
8853 were issued in the previous group to make sure that all of
8854 the added nops are really free. */
8855 else if (ofs + len > (int) align)
8857 int nop_count = (align - ofs) / 4;
8860 /* Insert nops before labels, branches, and calls to truly merge
8861 the execution of the nops with the previous instruction group. */
8862 where = prev_nonnote_insn (i);
8865 if (GET_CODE (where) == CODE_LABEL)
8867 rtx where2 = prev_nonnote_insn (where);
8868 if (where2 && GET_CODE (where2) == JUMP_INSN)
8871 else if (GET_CODE (where) == INSN)
8878 emit_insn_before ((*next_nop)(&prev_in_use), where);
8879 while (--nop_count);
8883 ofs = (ofs + len) & (align - 1);
8884 prev_in_use = in_use;
8889 /* Machine dependent reorg pass. */
8894 if (alpha_tp != ALPHA_TP_PROG || flag_exceptions)
8895 alpha_handle_trap_shadows ();
8897 /* Due to the number of extra trapb insns, don't bother fixing up
8898 alignment when trap precision is instruction. Moreover, we can
8899 only do our job when sched2 is run. */
8900 if (optimize && !optimize_size
8901 && alpha_tp != ALPHA_TP_INSN
8902 && flag_schedule_insns_after_reload)
8904 if (alpha_cpu == PROCESSOR_EV4)
8905 alpha_align_insns (8, alphaev4_next_group, alphaev4_next_nop);
8906 else if (alpha_cpu == PROCESSOR_EV5)
8907 alpha_align_insns (16, alphaev5_next_group, alphaev5_next_nop);
8911 #if !TARGET_ABI_UNICOSMK
8918 alpha_file_start (void)
8920 #ifdef OBJECT_FORMAT_ELF
8921 /* If emitting dwarf2 debug information, we cannot generate a .file
8922 directive to start the file, as it will conflict with dwarf2out
8923 file numbers. So it's only useful when emitting mdebug output. */
8924 targetm.file_start_file_directive = (write_symbols == DBX_DEBUG);
8927 default_file_start ();
8929 fprintf (asm_out_file, "\t.verstamp %d %d\n", MS_STAMP, LS_STAMP);
8932 fputs ("\t.set noreorder\n", asm_out_file);
8933 fputs ("\t.set volatile\n", asm_out_file);
8934 if (!TARGET_ABI_OPEN_VMS)
8935 fputs ("\t.set noat\n", asm_out_file);
8936 if (TARGET_EXPLICIT_RELOCS)
8937 fputs ("\t.set nomacro\n", asm_out_file);
8938 if (TARGET_SUPPORT_ARCH | TARGET_BWX | TARGET_MAX | TARGET_FIX | TARGET_CIX)
8939 fprintf (asm_out_file,
8941 TARGET_CPU_EV6 ? "ev6"
8943 ? (TARGET_MAX ? "pca56" : TARGET_BWX ? "ev56" : "ev5")
8948 #ifdef OBJECT_FORMAT_ELF
8950 /* Switch to the section to which we should output X. The only thing
8951 special we do here is to honor small data. */
8954 alpha_elf_select_rtx_section (enum machine_mode mode, rtx x,
8955 unsigned HOST_WIDE_INT align)
8957 if (TARGET_SMALL_DATA && GET_MODE_SIZE (mode) <= g_switch_value)
8958 /* ??? Consider using mergeable sdata sections. */
8961 default_elf_select_rtx_section (mode, x, align);
8964 #endif /* OBJECT_FORMAT_ELF */
8966 /* Structure to collect function names for final output in link section. */
8967 /* Note that items marked with GTY can't be ifdef'ed out. */
8969 enum links_kind {KIND_UNUSED, KIND_LOCAL, KIND_EXTERN};
8970 enum reloc_kind {KIND_LINKAGE, KIND_CODEADDR};
8972 struct alpha_links GTY(())
8976 enum links_kind lkind;
8977 enum reloc_kind rkind;
8980 struct alpha_funcs GTY(())
8983 splay_tree GTY ((param1_is (char *), param2_is (struct alpha_links *)))
8987 static GTY ((param1_is (char *), param2_is (struct alpha_links *)))
8988 splay_tree alpha_links_tree;
8989 static GTY ((param1_is (tree), param2_is (struct alpha_funcs *)))
8990 splay_tree alpha_funcs_tree;
8992 static GTY(()) int alpha_funcs_num;
8994 #if TARGET_ABI_OPEN_VMS
8996 /* Return the VMS argument type corresponding to MODE. */
8999 alpha_arg_type (enum machine_mode mode)
9004 return TARGET_FLOAT_VAX ? FF : FS;
9006 return TARGET_FLOAT_VAX ? FD : FT;
9012 /* Return an rtx for an integer representing the VMS Argument Information
9016 alpha_arg_info_reg_val (CUMULATIVE_ARGS cum)
9018 unsigned HOST_WIDE_INT regval = cum.num_args;
9021 for (i = 0; i < 6; i++)
9022 regval |= ((int) cum.atypes[i]) << (i * 3 + 8);
9024 return GEN_INT (regval);
9027 /* Make (or fake) .linkage entry for function call.
9029 IS_LOCAL is 0 if name is used in call, 1 if name is used in definition.
9031 Return an SYMBOL_REF rtx for the linkage. */
9034 alpha_need_linkage (const char *name, int is_local)
9036 splay_tree_node node;
9037 struct alpha_links *al;
9044 struct alpha_funcs *cfaf;
9046 if (!alpha_funcs_tree)
9047 alpha_funcs_tree = splay_tree_new_ggc ((splay_tree_compare_fn)
9048 splay_tree_compare_pointers);
9050 cfaf = (struct alpha_funcs *) ggc_alloc (sizeof (struct alpha_funcs));
9053 cfaf->num = ++alpha_funcs_num;
9055 splay_tree_insert (alpha_funcs_tree,
9056 (splay_tree_key) current_function_decl,
9057 (splay_tree_value) cfaf);
9060 if (alpha_links_tree)
9062 /* Is this name already defined? */
9064 node = splay_tree_lookup (alpha_links_tree, (splay_tree_key) name);
9067 al = (struct alpha_links *) node->value;
9070 /* Defined here but external assumed. */
9071 if (al->lkind == KIND_EXTERN)
9072 al->lkind = KIND_LOCAL;
9076 /* Used here but unused assumed. */
9077 if (al->lkind == KIND_UNUSED)
9078 al->lkind = KIND_LOCAL;
9084 alpha_links_tree = splay_tree_new_ggc ((splay_tree_compare_fn) strcmp);
9086 al = (struct alpha_links *) ggc_alloc (sizeof (struct alpha_links));
9087 name = ggc_strdup (name);
9089 /* Assume external if no definition. */
9090 al->lkind = (is_local ? KIND_UNUSED : KIND_EXTERN);
9092 /* Ensure we have an IDENTIFIER so assemble_name can mark it used. */
9093 get_identifier (name);
9095 /* Construct a SYMBOL_REF for us to call. */
9097 size_t name_len = strlen (name);
9098 char *linksym = alloca (name_len + 6);
9100 memcpy (linksym + 1, name, name_len);
9101 memcpy (linksym + 1 + name_len, "..lk", 5);
9102 al->linkage = gen_rtx_SYMBOL_REF (Pmode,
9103 ggc_alloc_string (linksym, name_len + 5));
9106 splay_tree_insert (alpha_links_tree, (splay_tree_key) name,
9107 (splay_tree_value) al);
9113 alpha_use_linkage (rtx linkage, tree cfundecl, int lflag, int rflag)
9115 splay_tree_node cfunnode;
9116 struct alpha_funcs *cfaf;
9117 struct alpha_links *al;
9118 const char *name = XSTR (linkage, 0);
9120 cfaf = (struct alpha_funcs *) 0;
9121 al = (struct alpha_links *) 0;
9123 cfunnode = splay_tree_lookup (alpha_funcs_tree, (splay_tree_key) cfundecl);
9124 cfaf = (struct alpha_funcs *) cfunnode->value;
9128 splay_tree_node lnode;
9130 /* Is this name already defined? */
9132 lnode = splay_tree_lookup (cfaf->links, (splay_tree_key) name);
9134 al = (struct alpha_links *) lnode->value;
9137 cfaf->links = splay_tree_new_ggc ((splay_tree_compare_fn) strcmp);
9145 splay_tree_node node = 0;
9146 struct alpha_links *anl;
9151 name_len = strlen (name);
9153 al = (struct alpha_links *) ggc_alloc (sizeof (struct alpha_links));
9154 al->num = cfaf->num;
9156 node = splay_tree_lookup (alpha_links_tree, (splay_tree_key) name);
9159 anl = (struct alpha_links *) node->value;
9160 al->lkind = anl->lkind;
9163 sprintf (buf, "$%d..%s..lk", cfaf->num, name);
9164 buflen = strlen (buf);
9165 linksym = alloca (buflen + 1);
9166 memcpy (linksym, buf, buflen + 1);
9168 al->linkage = gen_rtx_SYMBOL_REF
9169 (Pmode, ggc_alloc_string (linksym, buflen + 1));
9171 splay_tree_insert (cfaf->links, (splay_tree_key) name,
9172 (splay_tree_value) al);
9176 al->rkind = KIND_CODEADDR;
9178 al->rkind = KIND_LINKAGE;
9181 return gen_rtx_MEM (Pmode, plus_constant (al->linkage, 8));
9187 alpha_write_one_linkage (splay_tree_node node, void *data)
9189 const char *const name = (const char *) node->key;
9190 struct alpha_links *link = (struct alpha_links *) node->value;
9191 FILE *stream = (FILE *) data;
9193 fprintf (stream, "$%d..%s..lk:\n", link->num, name);
9194 if (link->rkind == KIND_CODEADDR)
9196 if (link->lkind == KIND_LOCAL)
9198 /* Local and used */
9199 fprintf (stream, "\t.quad %s..en\n", name);
9203 /* External and used, request code address. */
9204 fprintf (stream, "\t.code_address %s\n", name);
9209 if (link->lkind == KIND_LOCAL)
9211 /* Local and used, build linkage pair. */
9212 fprintf (stream, "\t.quad %s..en\n", name);
9213 fprintf (stream, "\t.quad %s\n", name);
9217 /* External and used, request linkage pair. */
9218 fprintf (stream, "\t.linkage %s\n", name);
9226 alpha_write_linkage (FILE *stream, const char *funname, tree fundecl)
9228 splay_tree_node node;
9229 struct alpha_funcs *func;
9232 fprintf (stream, "\t.align 3\n");
9233 node = splay_tree_lookup (alpha_funcs_tree, (splay_tree_key) fundecl);
9234 func = (struct alpha_funcs *) node->value;
9236 fputs ("\t.name ", stream);
9237 assemble_name (stream, funname);
9238 fputs ("..na\n", stream);
9239 ASM_OUTPUT_LABEL (stream, funname);
9240 fprintf (stream, "\t.pdesc ");
9241 assemble_name (stream, funname);
9242 fprintf (stream, "..en,%s\n",
9243 alpha_procedure_type == PT_STACK ? "stack"
9244 : alpha_procedure_type == PT_REGISTER ? "reg" : "null");
9248 splay_tree_foreach (func->links, alpha_write_one_linkage, stream);
9249 /* splay_tree_delete (func->links); */
9253 /* Given a decl, a section name, and whether the decl initializer
9254 has relocs, choose attributes for the section. */
9256 #define SECTION_VMS_OVERLAY SECTION_FORGET
9257 #define SECTION_VMS_GLOBAL SECTION_MACH_DEP
9258 #define SECTION_VMS_INITIALIZE (SECTION_VMS_GLOBAL << 1)
9261 vms_section_type_flags (tree decl, const char *name, int reloc)
9263 unsigned int flags = default_section_type_flags (decl, name, reloc);
9265 if (decl && DECL_ATTRIBUTES (decl)
9266 && lookup_attribute ("overlaid", DECL_ATTRIBUTES (decl)))
9267 flags |= SECTION_VMS_OVERLAY;
9268 if (decl && DECL_ATTRIBUTES (decl)
9269 && lookup_attribute ("global", DECL_ATTRIBUTES (decl)))
9270 flags |= SECTION_VMS_GLOBAL;
9271 if (decl && DECL_ATTRIBUTES (decl)
9272 && lookup_attribute ("initialize", DECL_ATTRIBUTES (decl)))
9273 flags |= SECTION_VMS_INITIALIZE;
9278 /* Switch to an arbitrary section NAME with attributes as specified
9279 by FLAGS. ALIGN specifies any known alignment requirements for
9280 the section; 0 if the default should be used. */
9283 vms_asm_named_section (const char *name, unsigned int flags)
9285 fputc ('\n', asm_out_file);
9286 fprintf (asm_out_file, ".section\t%s", name);
9288 if (flags & SECTION_VMS_OVERLAY)
9289 fprintf (asm_out_file, ",OVR");
9290 if (flags & SECTION_VMS_GLOBAL)
9291 fprintf (asm_out_file, ",GBL");
9292 if (flags & SECTION_VMS_INITIALIZE)
9293 fprintf (asm_out_file, ",NOMOD");
9294 if (flags & SECTION_DEBUG)
9295 fprintf (asm_out_file, ",NOWRT");
9297 fputc ('\n', asm_out_file);
9300 /* Record an element in the table of global constructors. SYMBOL is
9301 a SYMBOL_REF of the function to be called; PRIORITY is a number
9302 between 0 and MAX_INIT_PRIORITY.
9304 Differs from default_ctors_section_asm_out_constructor in that the
9305 width of the .ctors entry is always 64 bits, rather than the 32 bits
9306 used by a normal pointer. */
9309 vms_asm_out_constructor (rtx symbol, int priority ATTRIBUTE_UNUSED)
9312 assemble_align (BITS_PER_WORD);
9313 assemble_integer (symbol, UNITS_PER_WORD, BITS_PER_WORD, 1);
9317 vms_asm_out_destructor (rtx symbol, int priority ATTRIBUTE_UNUSED)
9320 assemble_align (BITS_PER_WORD);
9321 assemble_integer (symbol, UNITS_PER_WORD, BITS_PER_WORD, 1);
9326 alpha_need_linkage (const char *name ATTRIBUTE_UNUSED,
9327 int is_local ATTRIBUTE_UNUSED)
9333 alpha_use_linkage (rtx linkage ATTRIBUTE_UNUSED,
9334 tree cfundecl ATTRIBUTE_UNUSED,
9335 int lflag ATTRIBUTE_UNUSED,
9336 int rflag ATTRIBUTE_UNUSED)
9341 #endif /* TARGET_ABI_OPEN_VMS */
9343 #if TARGET_ABI_UNICOSMK
9345 /* Define the offset between two registers, one to be eliminated, and the
9346 other its replacement, at the start of a routine. */
9349 unicosmk_initial_elimination_offset (int from, int to)
9353 fixed_size = alpha_sa_size();
9354 if (fixed_size != 0)
9357 if (from == FRAME_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM)
9359 else if (from == ARG_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM)
9361 else if (from == FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
9362 return (ALPHA_ROUND (current_function_outgoing_args_size)
9363 + ALPHA_ROUND (get_frame_size()));
9364 else if (from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
9365 return (ALPHA_ROUND (fixed_size)
9366 + ALPHA_ROUND (get_frame_size()
9367 + current_function_outgoing_args_size));
9372 /* Output the module name for .ident and .end directives. We have to strip
9373 directories and add make sure that the module name starts with a letter
9377 unicosmk_output_module_name (FILE *file)
9379 const char *name = lbasename (main_input_filename);
9380 unsigned len = strlen (name);
9381 char *clean_name = alloca (len + 2);
9382 char *ptr = clean_name;
9384 /* CAM only accepts module names that start with a letter or '$'. We
9385 prefix the module name with a '$' if necessary. */
9387 if (!ISALPHA (*name))
9389 memcpy (ptr, name, len + 1);
9390 clean_symbol_name (clean_name);
9391 fputs (clean_name, file);
9394 /* Output the definition of a common variable. */
9397 unicosmk_output_common (FILE *file, const char *name, int size, int align)
9400 printf ("T3E__: common %s\n", name);
9403 fputs("\t.endp\n\n\t.psect ", file);
9404 assemble_name(file, name);
9405 fprintf(file, ",%d,common\n", floor_log2 (align / BITS_PER_UNIT));
9406 fprintf(file, "\t.byte\t0:%d\n", size);
9408 /* Mark the symbol as defined in this module. */
9409 name_tree = get_identifier (name);
9410 TREE_ASM_WRITTEN (name_tree) = 1;
9413 #define SECTION_PUBLIC SECTION_MACH_DEP
9414 #define SECTION_MAIN (SECTION_PUBLIC << 1)
9415 static int current_section_align;
9418 unicosmk_section_type_flags (tree decl, const char *name,
9419 int reloc ATTRIBUTE_UNUSED)
9421 unsigned int flags = default_section_type_flags (decl, name, reloc);
9426 if (TREE_CODE (decl) == FUNCTION_DECL)
9428 current_section_align = floor_log2 (FUNCTION_BOUNDARY / BITS_PER_UNIT);
9429 if (align_functions_log > current_section_align)
9430 current_section_align = align_functions_log;
9432 if (! strcmp (IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl)), "main"))
9433 flags |= SECTION_MAIN;
9436 current_section_align = floor_log2 (DECL_ALIGN (decl) / BITS_PER_UNIT);
9438 if (TREE_PUBLIC (decl))
9439 flags |= SECTION_PUBLIC;
9444 /* Generate a section name for decl and associate it with the
9448 unicosmk_unique_section (tree decl, int reloc ATTRIBUTE_UNUSED)
9456 name = IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl));
9457 name = default_strip_name_encoding (name);
9458 len = strlen (name);
9460 if (TREE_CODE (decl) == FUNCTION_DECL)
9464 /* It is essential that we prefix the section name here because
9465 otherwise the section names generated for constructors and
9466 destructors confuse collect2. */
9468 string = alloca (len + 6);
9469 sprintf (string, "code@%s", name);
9470 DECL_SECTION_NAME (decl) = build_string (len + 5, string);
9472 else if (TREE_PUBLIC (decl))
9473 DECL_SECTION_NAME (decl) = build_string (len, name);
9478 string = alloca (len + 6);
9479 sprintf (string, "data@%s", name);
9480 DECL_SECTION_NAME (decl) = build_string (len + 5, string);
9484 /* Switch to an arbitrary section NAME with attributes as specified
9485 by FLAGS. ALIGN specifies any known alignment requirements for
9486 the section; 0 if the default should be used. */
9489 unicosmk_asm_named_section (const char *name, unsigned int flags)
9493 /* Close the previous section. */
9495 fputs ("\t.endp\n\n", asm_out_file);
9497 /* Find out what kind of section we are opening. */
9499 if (flags & SECTION_MAIN)
9500 fputs ("\t.start\tmain\n", asm_out_file);
9502 if (flags & SECTION_CODE)
9504 else if (flags & SECTION_PUBLIC)
9509 if (current_section_align != 0)
9510 fprintf (asm_out_file, "\t.psect\t%s,%d,%s\n", name,
9511 current_section_align, kind);
9513 fprintf (asm_out_file, "\t.psect\t%s,%s\n", name, kind);
9517 unicosmk_insert_attributes (tree decl, tree *attr_ptr ATTRIBUTE_UNUSED)
9520 && (TREE_PUBLIC (decl) || TREE_CODE (decl) == FUNCTION_DECL))
9521 unicosmk_unique_section (decl, 0);
9524 /* Output an alignment directive. We have to use the macro 'gcc@code@align'
9525 in code sections because .align fill unused space with zeroes. */
9528 unicosmk_output_align (FILE *file, int align)
9530 if (inside_function)
9531 fprintf (file, "\tgcc@code@align\t%d\n", align);
9533 fprintf (file, "\t.align\t%d\n", align);
9536 /* Add a case vector to the current function's list of deferred case
9537 vectors. Case vectors have to be put into a separate section because CAM
9538 does not allow data definitions in code sections. */
9541 unicosmk_defer_case_vector (rtx lab, rtx vec)
9543 struct machine_function *machine = cfun->machine;
9545 vec = gen_rtx_EXPR_LIST (VOIDmode, lab, vec);
9546 machine->addr_list = gen_rtx_EXPR_LIST (VOIDmode, vec,
9547 machine->addr_list);
9550 /* Output a case vector. */
9553 unicosmk_output_addr_vec (FILE *file, rtx vec)
9555 rtx lab = XEXP (vec, 0);
9556 rtx body = XEXP (vec, 1);
9557 int vlen = XVECLEN (body, 0);
9560 (*targetm.asm_out.internal_label) (file, "L", CODE_LABEL_NUMBER (lab));
9562 for (idx = 0; idx < vlen; idx++)
9564 ASM_OUTPUT_ADDR_VEC_ELT
9565 (file, CODE_LABEL_NUMBER (XEXP (XVECEXP (body, 0, idx), 0)));
9569 /* Output current function's deferred case vectors. */
9572 unicosmk_output_deferred_case_vectors (FILE *file)
9574 struct machine_function *machine = cfun->machine;
9577 if (machine->addr_list == NULL_RTX)
9581 for (t = machine->addr_list; t; t = XEXP (t, 1))
9582 unicosmk_output_addr_vec (file, XEXP (t, 0));
9585 /* Generate the name of the SSIB section for the current function. */
9587 #define SSIB_PREFIX "__SSIB_"
9588 #define SSIB_PREFIX_LEN 7
9591 unicosmk_ssib_name (void)
9593 /* This is ok since CAM won't be able to deal with names longer than that
9596 static char name[256];
9602 x = DECL_RTL (cfun->decl);
9603 if (GET_CODE (x) != MEM)
9606 if (GET_CODE (x) != SYMBOL_REF)
9608 fnname = XSTR (x, 0);
9610 len = strlen (fnname);
9611 if (len + SSIB_PREFIX_LEN > 255)
9612 len = 255 - SSIB_PREFIX_LEN;
9614 strcpy (name, SSIB_PREFIX);
9615 strncpy (name + SSIB_PREFIX_LEN, fnname, len);
9616 name[len + SSIB_PREFIX_LEN] = 0;
9621 /* Set up the dynamic subprogram information block (DSIB) and update the
9622 frame pointer register ($15) for subroutines which have a frame. If the
9623 subroutine doesn't have a frame, simply increment $15. */
9626 unicosmk_gen_dsib (unsigned long *imaskP)
9628 if (alpha_procedure_type == PT_STACK)
9630 const char *ssib_name;
9633 /* Allocate 64 bytes for the DSIB. */
9635 FRP (emit_insn (gen_adddi3 (stack_pointer_rtx, stack_pointer_rtx,
9637 emit_insn (gen_blockage ());
9639 /* Save the return address. */
9641 mem = gen_rtx_MEM (DImode, plus_constant (stack_pointer_rtx, 56));
9642 set_mem_alias_set (mem, alpha_sr_alias_set);
9643 FRP (emit_move_insn (mem, gen_rtx_REG (DImode, REG_RA)));
9644 (*imaskP) &= ~(1UL << REG_RA);
9646 /* Save the old frame pointer. */
9648 mem = gen_rtx_MEM (DImode, plus_constant (stack_pointer_rtx, 48));
9649 set_mem_alias_set (mem, alpha_sr_alias_set);
9650 FRP (emit_move_insn (mem, hard_frame_pointer_rtx));
9651 (*imaskP) &= ~(1UL << HARD_FRAME_POINTER_REGNUM);
9653 emit_insn (gen_blockage ());
9655 /* Store the SSIB pointer. */
9657 ssib_name = ggc_strdup (unicosmk_ssib_name ());
9658 mem = gen_rtx_MEM (DImode, plus_constant (stack_pointer_rtx, 32));
9659 set_mem_alias_set (mem, alpha_sr_alias_set);
9661 FRP (emit_move_insn (gen_rtx_REG (DImode, 5),
9662 gen_rtx_SYMBOL_REF (Pmode, ssib_name)));
9663 FRP (emit_move_insn (mem, gen_rtx_REG (DImode, 5)));
9665 /* Save the CIW index. */
9667 mem = gen_rtx_MEM (DImode, plus_constant (stack_pointer_rtx, 24));
9668 set_mem_alias_set (mem, alpha_sr_alias_set);
9669 FRP (emit_move_insn (mem, gen_rtx_REG (DImode, 25)));
9671 emit_insn (gen_blockage ());
9673 /* Set the new frame pointer. */
9675 FRP (emit_insn (gen_adddi3 (hard_frame_pointer_rtx,
9676 stack_pointer_rtx, GEN_INT (64))));
9681 /* Increment the frame pointer register to indicate that we do not
9684 FRP (emit_insn (gen_adddi3 (hard_frame_pointer_rtx,
9685 hard_frame_pointer_rtx, const1_rtx)));
9689 /* Output the static subroutine information block for the current
9693 unicosmk_output_ssib (FILE *file, const char *fnname)
9699 struct machine_function *machine = cfun->machine;
9702 fprintf (file, "\t.endp\n\n\t.psect\t%s%s,data\n", user_label_prefix,
9703 unicosmk_ssib_name ());
9705 /* Some required stuff and the function name length. */
9707 len = strlen (fnname);
9708 fprintf (file, "\t.quad\t^X20008%2.2X28\n", len);
9711 ??? We don't do that yet. */
9713 fputs ("\t.quad\t0\n", file);
9715 /* Function address. */
9717 fputs ("\t.quad\t", file);
9718 assemble_name (file, fnname);
9721 fputs ("\t.quad\t0\n", file);
9722 fputs ("\t.quad\t0\n", file);
9725 ??? We do it the same way Cray CC does it but this could be
9728 for( i = 0; i < len; i++ )
9729 fprintf (file, "\t.byte\t%d\n", (int)(fnname[i]));
9730 if( (len % 8) == 0 )
9731 fputs ("\t.quad\t0\n", file);
9733 fprintf (file, "\t.bits\t%d : 0\n", (8 - (len % 8))*8);
9735 /* All call information words used in the function. */
9737 for (x = machine->first_ciw; x; x = XEXP (x, 1))
9740 #if HOST_BITS_PER_WIDE_INT == 32
9741 fprintf (file, "\t.quad\t" HOST_WIDE_INT_PRINT_DOUBLE_HEX "\n",
9742 CONST_DOUBLE_HIGH (ciw), CONST_DOUBLE_LOW (ciw));
9744 fprintf (file, "\t.quad\t" HOST_WIDE_INT_PRINT_HEX "\n", INTVAL (ciw));
9749 /* Add a call information word (CIW) to the list of the current function's
9750 CIWs and return its index.
9752 X is a CONST_INT or CONST_DOUBLE representing the CIW. */
9755 unicosmk_add_call_info_word (rtx x)
9758 struct machine_function *machine = cfun->machine;
9760 node = gen_rtx_EXPR_LIST (VOIDmode, x, NULL_RTX);
9761 if (machine->first_ciw == NULL_RTX)
9762 machine->first_ciw = node;
9764 XEXP (machine->last_ciw, 1) = node;
9766 machine->last_ciw = node;
9767 ++machine->ciw_count;
9769 return GEN_INT (machine->ciw_count
9770 + strlen (current_function_name ())/8 + 5);
9773 static char unicosmk_section_buf[100];
9776 unicosmk_text_section (void)
9778 static int count = 0;
9779 sprintf (unicosmk_section_buf, "\t.endp\n\n\t.psect\tgcc@text___%d,code",
9781 return unicosmk_section_buf;
9785 unicosmk_data_section (void)
9787 static int count = 1;
9788 sprintf (unicosmk_section_buf, "\t.endp\n\n\t.psect\tgcc@data___%d,data",
9790 return unicosmk_section_buf;
9793 /* The Cray assembler doesn't accept extern declarations for symbols which
9794 are defined in the same file. We have to keep track of all global
9795 symbols which are referenced and/or defined in a source file and output
9796 extern declarations for those which are referenced but not defined at
9799 /* List of identifiers for which an extern declaration might have to be
9801 /* FIXME: needs to use GC, so it can be saved and restored for PCH. */
9803 struct unicosmk_extern_list
9805 struct unicosmk_extern_list *next;
9809 static struct unicosmk_extern_list *unicosmk_extern_head = 0;
9811 /* Output extern declarations which are required for every asm file. */
9814 unicosmk_output_default_externs (FILE *file)
9816 static const char *const externs[] =
9817 { "__T3E_MISMATCH" };
9822 n = ARRAY_SIZE (externs);
9824 for (i = 0; i < n; i++)
9825 fprintf (file, "\t.extern\t%s\n", externs[i]);
9828 /* Output extern declarations for global symbols which are have been
9829 referenced but not defined. */
9832 unicosmk_output_externs (FILE *file)
9834 struct unicosmk_extern_list *p;
9835 const char *real_name;
9839 len = strlen (user_label_prefix);
9840 for (p = unicosmk_extern_head; p != 0; p = p->next)
9842 /* We have to strip the encoding and possibly remove user_label_prefix
9843 from the identifier in order to handle -fleading-underscore and
9844 explicit asm names correctly (cf. gcc.dg/asm-names-1.c). */
9845 real_name = default_strip_name_encoding (p->name);
9846 if (len && p->name[0] == '*'
9847 && !memcmp (real_name, user_label_prefix, len))
9850 name_tree = get_identifier (real_name);
9851 if (! TREE_ASM_WRITTEN (name_tree))
9853 TREE_ASM_WRITTEN (name_tree) = 1;
9854 fputs ("\t.extern\t", file);
9855 assemble_name (file, p->name);
9861 /* Record an extern. */
9864 unicosmk_add_extern (const char *name)
9866 struct unicosmk_extern_list *p;
9868 p = (struct unicosmk_extern_list *)
9869 xmalloc (sizeof (struct unicosmk_extern_list));
9870 p->next = unicosmk_extern_head;
9872 unicosmk_extern_head = p;
9875 /* The Cray assembler generates incorrect code if identifiers which
9876 conflict with register names are used as instruction operands. We have
9877 to replace such identifiers with DEX expressions. */
9879 /* Structure to collect identifiers which have been replaced by DEX
9881 /* FIXME: needs to use GC, so it can be saved and restored for PCH. */
9883 struct unicosmk_dex {
9884 struct unicosmk_dex *next;
9888 /* List of identifiers which have been replaced by DEX expressions. The DEX
9889 number is determined by the position in the list. */
9891 static struct unicosmk_dex *unicosmk_dex_list = NULL;
9893 /* The number of elements in the DEX list. */
9895 static int unicosmk_dex_count = 0;
9897 /* Check if NAME must be replaced by a DEX expression. */
9900 unicosmk_special_name (const char *name)
9908 if (name[0] != 'r' && name[0] != 'f' && name[0] != 'R' && name[0] != 'F')
9914 return (name[2] == '\0' || (ISDIGIT (name[2]) && name[3] == '\0'));
9917 return (name[2] == '\0'
9918 || ((name[2] == '0' || name[2] == '1') && name[3] == '\0'));
9921 return (ISDIGIT (name[1]) && name[2] == '\0');
9925 /* Return the DEX number if X must be replaced by a DEX expression and 0
9929 unicosmk_need_dex (rtx x)
9931 struct unicosmk_dex *dex;
9935 if (GET_CODE (x) != SYMBOL_REF)
9939 if (! unicosmk_special_name (name))
9942 i = unicosmk_dex_count;
9943 for (dex = unicosmk_dex_list; dex; dex = dex->next)
9945 if (! strcmp (name, dex->name))
9950 dex = (struct unicosmk_dex *) xmalloc (sizeof (struct unicosmk_dex));
9952 dex->next = unicosmk_dex_list;
9953 unicosmk_dex_list = dex;
9955 ++unicosmk_dex_count;
9956 return unicosmk_dex_count;
9959 /* Output the DEX definitions for this file. */
9962 unicosmk_output_dex (FILE *file)
9964 struct unicosmk_dex *dex;
9967 if (unicosmk_dex_list == NULL)
9970 fprintf (file, "\t.dexstart\n");
9972 i = unicosmk_dex_count;
9973 for (dex = unicosmk_dex_list; dex; dex = dex->next)
9975 fprintf (file, "\tDEX (%d) = ", i);
9976 assemble_name (file, dex->name);
9981 fprintf (file, "\t.dexend\n");
9984 /* Output text that to appear at the beginning of an assembler file. */
9987 unicosmk_file_start (void)
9991 fputs ("\t.ident\t", asm_out_file);
9992 unicosmk_output_module_name (asm_out_file);
9993 fputs ("\n\n", asm_out_file);
9995 /* The Unicos/Mk assembler uses different register names. Instead of trying
9996 to support them, we simply use micro definitions. */
9998 /* CAM has different register names: rN for the integer register N and fN
9999 for the floating-point register N. Instead of trying to use these in
10000 alpha.md, we define the symbols $N and $fN to refer to the appropriate
10003 for (i = 0; i < 32; ++i)
10004 fprintf (asm_out_file, "$%d <- r%d\n", i, i);
10006 for (i = 0; i < 32; ++i)
10007 fprintf (asm_out_file, "$f%d <- f%d\n", i, i);
10009 putc ('\n', asm_out_file);
10011 /* The .align directive fill unused space with zeroes which does not work
10012 in code sections. We define the macro 'gcc@code@align' which uses nops
10013 instead. Note that it assumes that code sections always have the
10014 biggest possible alignment since . refers to the current offset from
10015 the beginning of the section. */
10017 fputs ("\t.macro gcc@code@align n\n", asm_out_file);
10018 fputs ("gcc@n@bytes = 1 << n\n", asm_out_file);
10019 fputs ("gcc@here = . % gcc@n@bytes\n", asm_out_file);
10020 fputs ("\t.if ne, gcc@here, 0\n", asm_out_file);
10021 fputs ("\t.repeat (gcc@n@bytes - gcc@here) / 4\n", asm_out_file);
10022 fputs ("\tbis r31,r31,r31\n", asm_out_file);
10023 fputs ("\t.endr\n", asm_out_file);
10024 fputs ("\t.endif\n", asm_out_file);
10025 fputs ("\t.endm gcc@code@align\n\n", asm_out_file);
10027 /* Output extern declarations which should always be visible. */
10028 unicosmk_output_default_externs (asm_out_file);
10030 /* Open a dummy section. We always need to be inside a section for the
10031 section-switching code to work correctly.
10032 ??? This should be a module id or something like that. I still have to
10033 figure out what the rules for those are. */
10034 fputs ("\n\t.psect\t$SG00000,data\n", asm_out_file);
10037 /* Output text to appear at the end of an assembler file. This includes all
10038 pending extern declarations and DEX expressions. */
10041 unicosmk_file_end (void)
10043 fputs ("\t.endp\n\n", asm_out_file);
10045 /* Output all pending externs. */
10047 unicosmk_output_externs (asm_out_file);
10049 /* Output dex definitions used for functions whose names conflict with
10052 unicosmk_output_dex (asm_out_file);
10054 fputs ("\t.end\t", asm_out_file);
10055 unicosmk_output_module_name (asm_out_file);
10056 putc ('\n', asm_out_file);
10062 unicosmk_output_deferred_case_vectors (FILE *file ATTRIBUTE_UNUSED)
10066 unicosmk_gen_dsib (unsigned long *imaskP ATTRIBUTE_UNUSED)
10070 unicosmk_output_ssib (FILE * file ATTRIBUTE_UNUSED,
10071 const char * fnname ATTRIBUTE_UNUSED)
10075 unicosmk_add_call_info_word (rtx x ATTRIBUTE_UNUSED)
10081 unicosmk_need_dex (rtx x ATTRIBUTE_UNUSED)
10086 #endif /* TARGET_ABI_UNICOSMK */
10089 alpha_init_libfuncs (void)
10091 if (TARGET_ABI_UNICOSMK)
10093 /* Prevent gcc from generating calls to __divsi3. */
10094 set_optab_libfunc (sdiv_optab, SImode, 0);
10095 set_optab_libfunc (udiv_optab, SImode, 0);
10097 /* Use the functions provided by the system library
10098 for DImode integer division. */
10099 set_optab_libfunc (sdiv_optab, DImode, "$sldiv");
10100 set_optab_libfunc (udiv_optab, DImode, "$uldiv");
10102 else if (TARGET_ABI_OPEN_VMS)
10104 /* Use the VMS runtime library functions for division and
10106 set_optab_libfunc (sdiv_optab, SImode, "OTS$DIV_I");
10107 set_optab_libfunc (sdiv_optab, DImode, "OTS$DIV_L");
10108 set_optab_libfunc (udiv_optab, SImode, "OTS$DIV_UI");
10109 set_optab_libfunc (udiv_optab, DImode, "OTS$DIV_UL");
10110 set_optab_libfunc (smod_optab, SImode, "OTS$REM_I");
10111 set_optab_libfunc (smod_optab, DImode, "OTS$REM_L");
10112 set_optab_libfunc (umod_optab, SImode, "OTS$REM_UI");
10113 set_optab_libfunc (umod_optab, DImode, "OTS$REM_UL");
10118 /* Initialize the GCC target structure. */
10119 #if TARGET_ABI_OPEN_VMS
10120 # undef TARGET_ATTRIBUTE_TABLE
10121 # define TARGET_ATTRIBUTE_TABLE vms_attribute_table
10122 # undef TARGET_SECTION_TYPE_FLAGS
10123 # define TARGET_SECTION_TYPE_FLAGS vms_section_type_flags
10126 #undef TARGET_IN_SMALL_DATA_P
10127 #define TARGET_IN_SMALL_DATA_P alpha_in_small_data_p
10129 #if TARGET_ABI_UNICOSMK
10130 # undef TARGET_INSERT_ATTRIBUTES
10131 # define TARGET_INSERT_ATTRIBUTES unicosmk_insert_attributes
10132 # undef TARGET_SECTION_TYPE_FLAGS
10133 # define TARGET_SECTION_TYPE_FLAGS unicosmk_section_type_flags
10134 # undef TARGET_ASM_UNIQUE_SECTION
10135 # define TARGET_ASM_UNIQUE_SECTION unicosmk_unique_section
10136 # undef TARGET_ASM_GLOBALIZE_LABEL
10137 # define TARGET_ASM_GLOBALIZE_LABEL hook_void_FILEptr_constcharptr
10140 #undef TARGET_ASM_ALIGNED_HI_OP
10141 #define TARGET_ASM_ALIGNED_HI_OP "\t.word\t"
10142 #undef TARGET_ASM_ALIGNED_DI_OP
10143 #define TARGET_ASM_ALIGNED_DI_OP "\t.quad\t"
10145 /* Default unaligned ops are provided for ELF systems. To get unaligned
10146 data for non-ELF systems, we have to turn off auto alignment. */
10147 #ifndef OBJECT_FORMAT_ELF
10148 #undef TARGET_ASM_UNALIGNED_HI_OP
10149 #define TARGET_ASM_UNALIGNED_HI_OP "\t.align 0\n\t.word\t"
10150 #undef TARGET_ASM_UNALIGNED_SI_OP
10151 #define TARGET_ASM_UNALIGNED_SI_OP "\t.align 0\n\t.long\t"
10152 #undef TARGET_ASM_UNALIGNED_DI_OP
10153 #define TARGET_ASM_UNALIGNED_DI_OP "\t.align 0\n\t.quad\t"
10156 #ifdef OBJECT_FORMAT_ELF
10157 #undef TARGET_ASM_SELECT_RTX_SECTION
10158 #define TARGET_ASM_SELECT_RTX_SECTION alpha_elf_select_rtx_section
10161 #undef TARGET_ASM_FUNCTION_END_PROLOGUE
10162 #define TARGET_ASM_FUNCTION_END_PROLOGUE alpha_output_function_end_prologue
10164 #undef TARGET_INIT_LIBFUNCS
10165 #define TARGET_INIT_LIBFUNCS alpha_init_libfuncs
10167 #if TARGET_ABI_UNICOSMK
10168 #undef TARGET_ASM_FILE_START
10169 #define TARGET_ASM_FILE_START unicosmk_file_start
10170 #undef TARGET_ASM_FILE_END
10171 #define TARGET_ASM_FILE_END unicosmk_file_end
10173 #undef TARGET_ASM_FILE_START
10174 #define TARGET_ASM_FILE_START alpha_file_start
10175 #undef TARGET_ASM_FILE_START_FILE_DIRECTIVE
10176 #define TARGET_ASM_FILE_START_FILE_DIRECTIVE true
10179 #undef TARGET_SCHED_ADJUST_COST
10180 #define TARGET_SCHED_ADJUST_COST alpha_adjust_cost
10181 #undef TARGET_SCHED_ISSUE_RATE
10182 #define TARGET_SCHED_ISSUE_RATE alpha_issue_rate
10183 #undef TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE
10184 #define TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE \
10185 alpha_use_dfa_pipeline_interface
10186 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
10187 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \
10188 alpha_multipass_dfa_lookahead
10190 #undef TARGET_HAVE_TLS
10191 #define TARGET_HAVE_TLS HAVE_AS_TLS
10193 #undef TARGET_INIT_BUILTINS
10194 #define TARGET_INIT_BUILTINS alpha_init_builtins
10195 #undef TARGET_EXPAND_BUILTIN
10196 #define TARGET_EXPAND_BUILTIN alpha_expand_builtin
10198 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
10199 #define TARGET_FUNCTION_OK_FOR_SIBCALL alpha_function_ok_for_sibcall
10200 #undef TARGET_CANNOT_COPY_INSN_P
10201 #define TARGET_CANNOT_COPY_INSN_P alpha_cannot_copy_insn_p
10204 #undef TARGET_ASM_OUTPUT_MI_THUNK
10205 #define TARGET_ASM_OUTPUT_MI_THUNK alpha_output_mi_thunk_osf
10206 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
10207 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_tree_hwi_hwi_tree_true
10210 #undef TARGET_RTX_COSTS
10211 #define TARGET_RTX_COSTS alpha_rtx_costs
10212 #undef TARGET_ADDRESS_COST
10213 #define TARGET_ADDRESS_COST hook_int_rtx_0
10215 #undef TARGET_MACHINE_DEPENDENT_REORG
10216 #define TARGET_MACHINE_DEPENDENT_REORG alpha_reorg
10218 #undef TARGET_PROMOTE_FUNCTION_ARGS
10219 #define TARGET_PROMOTE_FUNCTION_ARGS hook_bool_tree_true
10220 #undef TARGET_PROMOTE_FUNCTION_RETURN
10221 #define TARGET_PROMOTE_FUNCTION_RETURN hook_bool_tree_true
10222 #undef TARGET_PROMOTE_PROTOTYPES
10223 #define TARGET_PROMOTE_PROTOTYPES hook_bool_tree_false
10224 #undef TARGET_STRUCT_VALUE_RTX
10225 #define TARGET_STRUCT_VALUE_RTX hook_rtx_tree_int_null
10226 #undef TARGET_RETURN_IN_MEMORY
10227 #define TARGET_RETURN_IN_MEMORY alpha_return_in_memory
10228 #undef TARGET_SETUP_INCOMING_VARARGS
10229 #define TARGET_SETUP_INCOMING_VARARGS alpha_setup_incoming_varargs
10230 #undef TARGET_STRICT_ARGUMENT_NAMING
10231 #define TARGET_STRICT_ARGUMENT_NAMING hook_bool_CUMULATIVE_ARGS_true
10232 #undef TARGET_PRETEND_OUTGOING_VARARGS_NAMED
10233 #define TARGET_PRETEND_OUTGOING_VARARGS_NAMED hook_bool_CUMULATIVE_ARGS_true
10235 #undef TARGET_BUILD_BUILTIN_VA_LIST
10236 #define TARGET_BUILD_BUILTIN_VA_LIST alpha_build_builtin_va_list
10238 struct gcc_target targetm = TARGET_INITIALIZER;
10241 #include "gt-alpha.h"