1 /* Subroutines used for code generation on the DEC Alpha.
2 Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002, 2003, 2004 Free Software Foundation, Inc.
4 Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
13 GCC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING. If not, write to
20 the Free Software Foundation, 59 Temple Place - Suite 330,
21 Boston, MA 02111-1307, USA. */
26 #include "coretypes.h"
31 #include "hard-reg-set.h"
33 #include "insn-config.h"
34 #include "conditions.h"
36 #include "insn-attr.h"
47 #include "integrate.h"
50 #include "target-def.h"
52 #include "langhooks.h"
53 #include <splay-tree.h>
54 #include "cfglayout.h"
55 #include "tree-gimple.h"
57 /* Specify which cpu to schedule for. */
59 enum processor_type alpha_cpu;
60 static const char * const alpha_cpu_name[] =
65 /* Specify how accurate floating-point traps need to be. */
67 enum alpha_trap_precision alpha_tp;
69 /* Specify the floating-point rounding mode. */
71 enum alpha_fp_rounding_mode alpha_fprm;
73 /* Specify which things cause traps. */
75 enum alpha_fp_trap_mode alpha_fptm;
77 /* Specify bit size of immediate TLS offsets. */
79 int alpha_tls_size = 32;
81 /* Strings decoded into the above options. */
83 const char *alpha_cpu_string; /* -mcpu= */
84 const char *alpha_tune_string; /* -mtune= */
85 const char *alpha_tp_string; /* -mtrap-precision=[p|s|i] */
86 const char *alpha_fprm_string; /* -mfp-rounding-mode=[n|m|c|d] */
87 const char *alpha_fptm_string; /* -mfp-trap-mode=[n|u|su|sui] */
88 const char *alpha_mlat_string; /* -mmemory-latency= */
89 const char *alpha_tls_size_string; /* -mtls-size=[16|32|64] */
91 /* Save information from a "cmpxx" operation until the branch or scc is
94 struct alpha_compare alpha_compare;
96 /* Nonzero if inside of a function, because the Alpha asm can't
97 handle .files inside of functions. */
99 static int inside_function = FALSE;
101 /* The number of cycles of latency we should assume on memory reads. */
103 int alpha_memory_latency = 3;
105 /* Whether the function needs the GP. */
107 static int alpha_function_needs_gp;
109 /* The alias set for prologue/epilogue register save/restore. */
111 static GTY(()) int alpha_sr_alias_set;
113 /* The assembler name of the current function. */
115 static const char *alpha_fnname;
117 /* The next explicit relocation sequence number. */
118 extern GTY(()) int alpha_next_sequence_number;
119 int alpha_next_sequence_number = 1;
121 /* The literal and gpdisp sequence numbers for this insn, as printed
122 by %# and %* respectively. */
123 extern GTY(()) int alpha_this_literal_sequence_number;
124 extern GTY(()) int alpha_this_gpdisp_sequence_number;
125 int alpha_this_literal_sequence_number;
126 int alpha_this_gpdisp_sequence_number;
128 /* Costs of various operations on the different architectures. */
130 struct alpha_rtx_cost_data
132 unsigned char fp_add;
133 unsigned char fp_mult;
134 unsigned char fp_div_sf;
135 unsigned char fp_div_df;
136 unsigned char int_mult_si;
137 unsigned char int_mult_di;
138 unsigned char int_shift;
139 unsigned char int_cmov;
140 unsigned short int_div;
143 static struct alpha_rtx_cost_data const alpha_rtx_cost_data[PROCESSOR_MAX] =
146 COSTS_N_INSNS (6), /* fp_add */
147 COSTS_N_INSNS (6), /* fp_mult */
148 COSTS_N_INSNS (34), /* fp_div_sf */
149 COSTS_N_INSNS (63), /* fp_div_df */
150 COSTS_N_INSNS (23), /* int_mult_si */
151 COSTS_N_INSNS (23), /* int_mult_di */
152 COSTS_N_INSNS (2), /* int_shift */
153 COSTS_N_INSNS (2), /* int_cmov */
154 COSTS_N_INSNS (97), /* int_div */
157 COSTS_N_INSNS (4), /* fp_add */
158 COSTS_N_INSNS (4), /* fp_mult */
159 COSTS_N_INSNS (15), /* fp_div_sf */
160 COSTS_N_INSNS (22), /* fp_div_df */
161 COSTS_N_INSNS (8), /* int_mult_si */
162 COSTS_N_INSNS (12), /* int_mult_di */
163 COSTS_N_INSNS (1) + 1, /* int_shift */
164 COSTS_N_INSNS (1), /* int_cmov */
165 COSTS_N_INSNS (83), /* int_div */
168 COSTS_N_INSNS (4), /* fp_add */
169 COSTS_N_INSNS (4), /* fp_mult */
170 COSTS_N_INSNS (12), /* fp_div_sf */
171 COSTS_N_INSNS (15), /* fp_div_df */
172 COSTS_N_INSNS (7), /* int_mult_si */
173 COSTS_N_INSNS (7), /* int_mult_di */
174 COSTS_N_INSNS (1), /* int_shift */
175 COSTS_N_INSNS (2), /* int_cmov */
176 COSTS_N_INSNS (86), /* int_div */
180 /* Similar but tuned for code size instead of execution latency. The
181 extra +N is fractional cost tuning based on latency. It's used to
182 encourage use of cheaper insns like shift, but only if there's just
185 static struct alpha_rtx_cost_data const alpha_rtx_cost_size =
187 COSTS_N_INSNS (1), /* fp_add */
188 COSTS_N_INSNS (1), /* fp_mult */
189 COSTS_N_INSNS (1), /* fp_div_sf */
190 COSTS_N_INSNS (1) + 1, /* fp_div_df */
191 COSTS_N_INSNS (1) + 1, /* int_mult_si */
192 COSTS_N_INSNS (1) + 2, /* int_mult_di */
193 COSTS_N_INSNS (1), /* int_shift */
194 COSTS_N_INSNS (1), /* int_cmov */
195 COSTS_N_INSNS (6), /* int_div */
198 /* Get the number of args of a function in one of two ways. */
199 #if TARGET_ABI_OPEN_VMS || TARGET_ABI_UNICOSMK
200 #define NUM_ARGS current_function_args_info.num_args
202 #define NUM_ARGS current_function_args_info
208 /* Declarations of static functions. */
209 static struct machine_function *alpha_init_machine_status (void);
210 static rtx alpha_emit_xfloating_compare (enum rtx_code, rtx, rtx);
212 #if TARGET_ABI_OPEN_VMS
213 static void alpha_write_linkage (FILE *, const char *, tree);
216 static void unicosmk_output_deferred_case_vectors (FILE *);
217 static void unicosmk_gen_dsib (unsigned long *);
218 static void unicosmk_output_ssib (FILE *, const char *);
219 static int unicosmk_need_dex (rtx);
221 /* Parse target option strings. */
224 override_options (void)
227 static const struct cpu_table {
228 const char *const name;
229 const enum processor_type processor;
232 #define EV5_MASK (MASK_CPU_EV5)
233 #define EV6_MASK (MASK_CPU_EV6|MASK_BWX|MASK_MAX|MASK_FIX)
234 { "ev4", PROCESSOR_EV4, 0 },
235 { "ev45", PROCESSOR_EV4, 0 },
236 { "21064", PROCESSOR_EV4, 0 },
237 { "ev5", PROCESSOR_EV5, EV5_MASK },
238 { "21164", PROCESSOR_EV5, EV5_MASK },
239 { "ev56", PROCESSOR_EV5, EV5_MASK|MASK_BWX },
240 { "21164a", PROCESSOR_EV5, EV5_MASK|MASK_BWX },
241 { "pca56", PROCESSOR_EV5, EV5_MASK|MASK_BWX|MASK_MAX },
242 { "21164PC",PROCESSOR_EV5, EV5_MASK|MASK_BWX|MASK_MAX },
243 { "21164pc",PROCESSOR_EV5, EV5_MASK|MASK_BWX|MASK_MAX },
244 { "ev6", PROCESSOR_EV6, EV6_MASK },
245 { "21264", PROCESSOR_EV6, EV6_MASK },
246 { "ev67", PROCESSOR_EV6, EV6_MASK|MASK_CIX },
247 { "21264a", PROCESSOR_EV6, EV6_MASK|MASK_CIX },
251 /* Unicos/Mk doesn't have shared libraries. */
252 if (TARGET_ABI_UNICOSMK && flag_pic)
254 warning ("-f%s ignored for Unicos/Mk (not supported)",
255 (flag_pic > 1) ? "PIC" : "pic");
259 /* On Unicos/Mk, the native compiler consistently generates /d suffices for
260 floating-point instructions. Make that the default for this target. */
261 if (TARGET_ABI_UNICOSMK)
262 alpha_fprm = ALPHA_FPRM_DYN;
264 alpha_fprm = ALPHA_FPRM_NORM;
266 alpha_tp = ALPHA_TP_PROG;
267 alpha_fptm = ALPHA_FPTM_N;
269 /* We cannot use su and sui qualifiers for conversion instructions on
270 Unicos/Mk. I'm not sure if this is due to assembler or hardware
271 limitations. Right now, we issue a warning if -mieee is specified
272 and then ignore it; eventually, we should either get it right or
273 disable the option altogether. */
277 if (TARGET_ABI_UNICOSMK)
278 warning ("-mieee not supported on Unicos/Mk");
281 alpha_tp = ALPHA_TP_INSN;
282 alpha_fptm = ALPHA_FPTM_SU;
286 if (TARGET_IEEE_WITH_INEXACT)
288 if (TARGET_ABI_UNICOSMK)
289 warning ("-mieee-with-inexact not supported on Unicos/Mk");
292 alpha_tp = ALPHA_TP_INSN;
293 alpha_fptm = ALPHA_FPTM_SUI;
299 if (! strcmp (alpha_tp_string, "p"))
300 alpha_tp = ALPHA_TP_PROG;
301 else if (! strcmp (alpha_tp_string, "f"))
302 alpha_tp = ALPHA_TP_FUNC;
303 else if (! strcmp (alpha_tp_string, "i"))
304 alpha_tp = ALPHA_TP_INSN;
306 error ("bad value %qs for -mtrap-precision switch", alpha_tp_string);
309 if (alpha_fprm_string)
311 if (! strcmp (alpha_fprm_string, "n"))
312 alpha_fprm = ALPHA_FPRM_NORM;
313 else if (! strcmp (alpha_fprm_string, "m"))
314 alpha_fprm = ALPHA_FPRM_MINF;
315 else if (! strcmp (alpha_fprm_string, "c"))
316 alpha_fprm = ALPHA_FPRM_CHOP;
317 else if (! strcmp (alpha_fprm_string,"d"))
318 alpha_fprm = ALPHA_FPRM_DYN;
320 error ("bad value %qs for -mfp-rounding-mode switch",
324 if (alpha_fptm_string)
326 if (strcmp (alpha_fptm_string, "n") == 0)
327 alpha_fptm = ALPHA_FPTM_N;
328 else if (strcmp (alpha_fptm_string, "u") == 0)
329 alpha_fptm = ALPHA_FPTM_U;
330 else if (strcmp (alpha_fptm_string, "su") == 0)
331 alpha_fptm = ALPHA_FPTM_SU;
332 else if (strcmp (alpha_fptm_string, "sui") == 0)
333 alpha_fptm = ALPHA_FPTM_SUI;
335 error ("bad value %qs for -mfp-trap-mode switch", alpha_fptm_string);
338 if (alpha_tls_size_string)
340 if (strcmp (alpha_tls_size_string, "16") == 0)
342 else if (strcmp (alpha_tls_size_string, "32") == 0)
344 else if (strcmp (alpha_tls_size_string, "64") == 0)
347 error ("bad value %qs for -mtls-size switch", alpha_tls_size_string);
351 = TARGET_CPU_DEFAULT & MASK_CPU_EV6 ? PROCESSOR_EV6
352 : (TARGET_CPU_DEFAULT & MASK_CPU_EV5 ? PROCESSOR_EV5 : PROCESSOR_EV4);
354 if (alpha_cpu_string)
356 for (i = 0; cpu_table [i].name; i++)
357 if (! strcmp (alpha_cpu_string, cpu_table [i].name))
359 alpha_cpu = cpu_table [i].processor;
360 target_flags &= ~ (MASK_BWX | MASK_MAX | MASK_FIX | MASK_CIX
361 | MASK_CPU_EV5 | MASK_CPU_EV6);
362 target_flags |= cpu_table [i].flags;
365 if (! cpu_table [i].name)
366 error ("bad value %qs for -mcpu switch", alpha_cpu_string);
369 if (alpha_tune_string)
371 for (i = 0; cpu_table [i].name; i++)
372 if (! strcmp (alpha_tune_string, cpu_table [i].name))
374 alpha_cpu = cpu_table [i].processor;
377 if (! cpu_table [i].name)
378 error ("bad value %qs for -mcpu switch", alpha_tune_string);
381 /* Do some sanity checks on the above options. */
383 if (TARGET_ABI_UNICOSMK && alpha_fptm != ALPHA_FPTM_N)
385 warning ("trap mode not supported on Unicos/Mk");
386 alpha_fptm = ALPHA_FPTM_N;
389 if ((alpha_fptm == ALPHA_FPTM_SU || alpha_fptm == ALPHA_FPTM_SUI)
390 && alpha_tp != ALPHA_TP_INSN && ! TARGET_CPU_EV6)
392 warning ("fp software completion requires -mtrap-precision=i");
393 alpha_tp = ALPHA_TP_INSN;
398 /* Except for EV6 pass 1 (not released), we always have precise
399 arithmetic traps. Which means we can do software completion
400 without minding trap shadows. */
401 alpha_tp = ALPHA_TP_PROG;
404 if (TARGET_FLOAT_VAX)
406 if (alpha_fprm == ALPHA_FPRM_MINF || alpha_fprm == ALPHA_FPRM_DYN)
408 warning ("rounding mode not supported for VAX floats");
409 alpha_fprm = ALPHA_FPRM_NORM;
411 if (alpha_fptm == ALPHA_FPTM_SUI)
413 warning ("trap mode not supported for VAX floats");
414 alpha_fptm = ALPHA_FPTM_SU;
416 if (target_flags_explicit & MASK_LONG_DOUBLE_128)
417 warning ("128-bit long double not supported for VAX floats");
418 target_flags &= ~MASK_LONG_DOUBLE_128;
425 if (!alpha_mlat_string)
426 alpha_mlat_string = "L1";
428 if (ISDIGIT ((unsigned char)alpha_mlat_string[0])
429 && (lat = strtol (alpha_mlat_string, &end, 10), *end == '\0'))
431 else if ((alpha_mlat_string[0] == 'L' || alpha_mlat_string[0] == 'l')
432 && ISDIGIT ((unsigned char)alpha_mlat_string[1])
433 && alpha_mlat_string[2] == '\0')
435 static int const cache_latency[][4] =
437 { 3, 30, -1 }, /* ev4 -- Bcache is a guess */
438 { 2, 12, 38 }, /* ev5 -- Bcache from PC164 LMbench numbers */
439 { 3, 12, 30 }, /* ev6 -- Bcache from DS20 LMbench. */
442 lat = alpha_mlat_string[1] - '0';
443 if (lat <= 0 || lat > 3 || cache_latency[alpha_cpu][lat-1] == -1)
445 warning ("L%d cache latency unknown for %s",
446 lat, alpha_cpu_name[alpha_cpu]);
450 lat = cache_latency[alpha_cpu][lat-1];
452 else if (! strcmp (alpha_mlat_string, "main"))
454 /* Most current memories have about 370ns latency. This is
455 a reasonable guess for a fast cpu. */
460 warning ("bad value %qs for -mmemory-latency", alpha_mlat_string);
464 alpha_memory_latency = lat;
467 /* Default the definition of "small data" to 8 bytes. */
471 /* Infer TARGET_SMALL_DATA from -fpic/-fPIC. */
473 target_flags |= MASK_SMALL_DATA;
474 else if (flag_pic == 2)
475 target_flags &= ~MASK_SMALL_DATA;
477 /* Align labels and loops for optimal branching. */
478 /* ??? Kludge these by not doing anything if we don't optimize and also if
479 we are writing ECOFF symbols to work around a bug in DEC's assembler. */
480 if (optimize > 0 && write_symbols != SDB_DEBUG)
482 if (align_loops <= 0)
484 if (align_jumps <= 0)
487 if (align_functions <= 0)
488 align_functions = 16;
490 /* Acquire a unique set number for our register saves and restores. */
491 alpha_sr_alias_set = new_alias_set ();
493 /* Register variables and functions with the garbage collector. */
495 /* Set up function hooks. */
496 init_machine_status = alpha_init_machine_status;
498 /* Tell the compiler when we're using VAX floating point. */
499 if (TARGET_FLOAT_VAX)
501 REAL_MODE_FORMAT (SFmode) = &vax_f_format;
502 REAL_MODE_FORMAT (DFmode) = &vax_g_format;
503 REAL_MODE_FORMAT (TFmode) = NULL;
507 /* Returns 1 if VALUE is a mask that contains full bytes of zero or ones. */
510 zap_mask (HOST_WIDE_INT value)
514 for (i = 0; i < HOST_BITS_PER_WIDE_INT / HOST_BITS_PER_CHAR;
516 if ((value & 0xff) != 0 && (value & 0xff) != 0xff)
522 /* Return true if OP is valid for a particular TLS relocation.
523 We are already guaranteed that OP is a CONST. */
526 tls_symbolic_operand_1 (rtx op, int size, int unspec)
530 if (GET_CODE (op) != UNSPEC || XINT (op, 1) != unspec)
532 op = XVECEXP (op, 0, 0);
534 if (GET_CODE (op) != SYMBOL_REF)
537 if (SYMBOL_REF_LOCAL_P (op))
539 if (alpha_tls_size > size)
548 switch (SYMBOL_REF_TLS_MODEL (op))
550 case TLS_MODEL_LOCAL_DYNAMIC:
551 return unspec == UNSPEC_DTPREL;
552 case TLS_MODEL_INITIAL_EXEC:
553 return unspec == UNSPEC_TPREL && size == 64;
554 case TLS_MODEL_LOCAL_EXEC:
555 return unspec == UNSPEC_TPREL;
561 /* Used by aligned_memory_operand and unaligned_memory_operand to
562 resolve what reload is going to do with OP if it's a register. */
565 resolve_reload_operand (rtx op)
567 if (reload_in_progress)
570 if (GET_CODE (tmp) == SUBREG)
571 tmp = SUBREG_REG (tmp);
572 if (GET_CODE (tmp) == REG
573 && REGNO (tmp) >= FIRST_PSEUDO_REGISTER)
575 op = reg_equiv_memory_loc[REGNO (tmp)];
583 /* Implements CONST_OK_FOR_LETTER_P. Return true if the value matches
584 the range defined for C in [I-P]. */
587 alpha_const_ok_for_letter_p (HOST_WIDE_INT value, int c)
592 /* An unsigned 8 bit constant. */
593 return (unsigned HOST_WIDE_INT) value < 0x100;
595 /* The constant zero. */
598 /* A signed 16 bit constant. */
599 return (unsigned HOST_WIDE_INT) (value + 0x8000) < 0x10000;
601 /* A shifted signed 16 bit constant appropriate for LDAH. */
602 return ((value & 0xffff) == 0
603 && ((value) >> 31 == -1 || value >> 31 == 0));
605 /* A constant that can be AND'ed with using a ZAP insn. */
606 return zap_mask (value);
608 /* A complemented unsigned 8 bit constant. */
609 return (unsigned HOST_WIDE_INT) (~ value) < 0x100;
611 /* A negated unsigned 8 bit constant. */
612 return (unsigned HOST_WIDE_INT) (- value) < 0x100;
614 /* The constant 1, 2 or 3. */
615 return value == 1 || value == 2 || value == 3;
622 /* Implements CONST_DOUBLE_OK_FOR_LETTER_P. Return true if VALUE
623 matches for C in [GH]. */
626 alpha_const_double_ok_for_letter_p (rtx value, int c)
631 /* The floating point zero constant. */
632 return (GET_MODE_CLASS (GET_MODE (value)) == MODE_FLOAT
633 && value == CONST0_RTX (GET_MODE (value)));
636 /* A valid operand of a ZAP insn. */
637 return (GET_MODE (value) == VOIDmode
638 && zap_mask (CONST_DOUBLE_LOW (value))
639 && zap_mask (CONST_DOUBLE_HIGH (value)));
646 /* Implements CONST_DOUBLE_OK_FOR_LETTER_P. Return true if VALUE
650 alpha_extra_constraint (rtx value, int c)
655 return normal_memory_operand (value, VOIDmode);
657 return direct_call_operand (value, Pmode);
659 return (GET_CODE (value) == CONST_INT
660 && (unsigned HOST_WIDE_INT) INTVAL (value) < 64);
662 return GET_CODE (value) == HIGH;
664 return TARGET_ABI_UNICOSMK && symbolic_operand (value, VOIDmode);
666 return (GET_CODE (value) == CONST_VECTOR
667 && value == CONST0_RTX (GET_MODE (value)));
673 /* The scalar modes supported differs from the default check-what-c-supports
674 version in that sometimes TFmode is available even when long double
675 indicates only DFmode. On unicosmk, we have the situation that HImode
676 doesn't map to any C type, but of course we still support that. */
679 alpha_scalar_mode_supported_p (enum machine_mode mode)
687 case TImode: /* via optabs.c */
695 return TARGET_HAS_XFLOATING_LIBS;
702 /* Alpha implements a couple of integer vector mode operations when
703 TARGET_MAX is enabled. We do not check TARGET_MAX here, however,
704 which allows the vectorizer to operate on e.g. move instructions,
705 or when expand_vector_operations can do something useful. */
708 alpha_vector_mode_supported_p (enum machine_mode mode)
710 return mode == V8QImode || mode == V4HImode || mode == V2SImode;
713 /* Return 1 if this function can directly return via $26. */
718 return (! TARGET_ABI_OPEN_VMS && ! TARGET_ABI_UNICOSMK
720 && alpha_sa_size () == 0
721 && get_frame_size () == 0
722 && current_function_outgoing_args_size == 0
723 && current_function_pretend_args_size == 0);
726 /* Return the ADDR_VEC associated with a tablejump insn. */
729 alpha_tablejump_addr_vec (rtx insn)
733 tmp = JUMP_LABEL (insn);
736 tmp = NEXT_INSN (tmp);
739 if (GET_CODE (tmp) == JUMP_INSN
740 && GET_CODE (PATTERN (tmp)) == ADDR_DIFF_VEC)
741 return PATTERN (tmp);
745 /* Return the label of the predicted edge, or CONST0_RTX if we don't know. */
748 alpha_tablejump_best_label (rtx insn)
750 rtx jump_table = alpha_tablejump_addr_vec (insn);
751 rtx best_label = NULL_RTX;
753 /* ??? Once the CFG doesn't keep getting completely rebuilt, look
754 there for edge frequency counts from profile data. */
758 int n_labels = XVECLEN (jump_table, 1);
762 for (i = 0; i < n_labels; i++)
766 for (j = i + 1; j < n_labels; j++)
767 if (XEXP (XVECEXP (jump_table, 1, i), 0)
768 == XEXP (XVECEXP (jump_table, 1, j), 0))
771 if (count > best_count)
772 best_count = count, best_label = XVECEXP (jump_table, 1, i);
776 return best_label ? best_label : const0_rtx;
779 /* Return the TLS model to use for SYMBOL. */
781 static enum tls_model
782 tls_symbolic_operand_type (rtx symbol)
784 enum tls_model model;
786 if (GET_CODE (symbol) != SYMBOL_REF)
788 model = SYMBOL_REF_TLS_MODEL (symbol);
790 /* Local-exec with a 64-bit size is the same code as initial-exec. */
791 if (model == TLS_MODEL_LOCAL_EXEC && alpha_tls_size == 64)
792 model = TLS_MODEL_INITIAL_EXEC;
797 /* Return true if the function DECL will share the same GP as any
798 function in the current unit of translation. */
801 decl_has_samegp (tree decl)
803 /* Functions that are not local can be overridden, and thus may
804 not share the same gp. */
805 if (!(*targetm.binds_local_p) (decl))
808 /* If -msmall-data is in effect, assume that there is only one GP
809 for the module, and so any local symbol has this property. We
810 need explicit relocations to be able to enforce this for symbols
811 not defined in this unit of translation, however. */
812 if (TARGET_EXPLICIT_RELOCS && TARGET_SMALL_DATA)
815 /* Functions that are not external are defined in this UoT. */
816 /* ??? Irritatingly, static functions not yet emitted are still
817 marked "external". Apply this to non-static functions only. */
818 return !TREE_PUBLIC (decl) || !DECL_EXTERNAL (decl);
821 /* Return true if EXP should be placed in the small data section. */
824 alpha_in_small_data_p (tree exp)
826 /* We want to merge strings, so we never consider them small data. */
827 if (TREE_CODE (exp) == STRING_CST)
830 /* Functions are never in the small data area. Duh. */
831 if (TREE_CODE (exp) == FUNCTION_DECL)
834 if (TREE_CODE (exp) == VAR_DECL && DECL_SECTION_NAME (exp))
836 const char *section = TREE_STRING_POINTER (DECL_SECTION_NAME (exp));
837 if (strcmp (section, ".sdata") == 0
838 || strcmp (section, ".sbss") == 0)
843 HOST_WIDE_INT size = int_size_in_bytes (TREE_TYPE (exp));
845 /* If this is an incomplete type with size 0, then we can't put it
846 in sdata because it might be too big when completed. */
847 if (size > 0 && (unsigned HOST_WIDE_INT) size <= g_switch_value)
854 #if TARGET_ABI_OPEN_VMS
856 alpha_linkage_symbol_p (const char *symname)
858 int symlen = strlen (symname);
861 return strcmp (&symname [symlen - 4], "..lk") == 0;
866 #define LINKAGE_SYMBOL_REF_P(X) \
867 ((GET_CODE (X) == SYMBOL_REF \
868 && alpha_linkage_symbol_p (XSTR (X, 0))) \
869 || (GET_CODE (X) == CONST \
870 && GET_CODE (XEXP (X, 0)) == PLUS \
871 && GET_CODE (XEXP (XEXP (X, 0), 0)) == SYMBOL_REF \
872 && alpha_linkage_symbol_p (XSTR (XEXP (XEXP (X, 0), 0), 0))))
875 /* legitimate_address_p recognizes an RTL expression that is a valid
876 memory address for an instruction. The MODE argument is the
877 machine mode for the MEM expression that wants to use this address.
879 For Alpha, we have either a constant address or the sum of a
880 register and a constant address, or just a register. For DImode,
881 any of those forms can be surrounded with an AND that clear the
882 low-order three bits; this is an "unaligned" access. */
885 alpha_legitimate_address_p (enum machine_mode mode, rtx x, int strict)
887 /* If this is an ldq_u type address, discard the outer AND. */
889 && GET_CODE (x) == AND
890 && GET_CODE (XEXP (x, 1)) == CONST_INT
891 && INTVAL (XEXP (x, 1)) == -8)
894 /* Discard non-paradoxical subregs. */
895 if (GET_CODE (x) == SUBREG
896 && (GET_MODE_SIZE (GET_MODE (x))
897 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x)))))
900 /* Unadorned general registers are valid. */
903 ? STRICT_REG_OK_FOR_BASE_P (x)
904 : NONSTRICT_REG_OK_FOR_BASE_P (x)))
907 /* Constant addresses (i.e. +/- 32k) are valid. */
908 if (CONSTANT_ADDRESS_P (x))
911 #if TARGET_ABI_OPEN_VMS
912 if (LINKAGE_SYMBOL_REF_P (x))
916 /* Register plus a small constant offset is valid. */
917 if (GET_CODE (x) == PLUS)
919 rtx ofs = XEXP (x, 1);
922 /* Discard non-paradoxical subregs. */
923 if (GET_CODE (x) == SUBREG
924 && (GET_MODE_SIZE (GET_MODE (x))
925 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x)))))
931 && NONSTRICT_REG_OK_FP_BASE_P (x)
932 && GET_CODE (ofs) == CONST_INT)
935 ? STRICT_REG_OK_FOR_BASE_P (x)
936 : NONSTRICT_REG_OK_FOR_BASE_P (x))
937 && CONSTANT_ADDRESS_P (ofs))
942 /* If we're managing explicit relocations, LO_SUM is valid, as
943 are small data symbols. */
944 else if (TARGET_EXPLICIT_RELOCS)
946 if (small_symbolic_operand (x, Pmode))
949 if (GET_CODE (x) == LO_SUM)
951 rtx ofs = XEXP (x, 1);
954 /* Discard non-paradoxical subregs. */
955 if (GET_CODE (x) == SUBREG
956 && (GET_MODE_SIZE (GET_MODE (x))
957 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x)))))
960 /* Must have a valid base register. */
963 ? STRICT_REG_OK_FOR_BASE_P (x)
964 : NONSTRICT_REG_OK_FOR_BASE_P (x))))
967 /* The symbol must be local. */
968 if (local_symbolic_operand (ofs, Pmode)
969 || dtp32_symbolic_operand (ofs, Pmode)
970 || tp32_symbolic_operand (ofs, Pmode))
978 /* Build the SYMBOL_REF for __tls_get_addr. */
980 static GTY(()) rtx tls_get_addr_libfunc;
983 get_tls_get_addr (void)
985 if (!tls_get_addr_libfunc)
986 tls_get_addr_libfunc = init_one_libfunc ("__tls_get_addr");
987 return tls_get_addr_libfunc;
990 /* Try machine-dependent ways of modifying an illegitimate address
991 to be legitimate. If we find one, return the new, valid address. */
994 alpha_legitimize_address (rtx x, rtx scratch,
995 enum machine_mode mode ATTRIBUTE_UNUSED)
997 HOST_WIDE_INT addend;
999 /* If the address is (plus reg const_int) and the CONST_INT is not a
1000 valid offset, compute the high part of the constant and add it to
1001 the register. Then our address is (plus temp low-part-const). */
1002 if (GET_CODE (x) == PLUS
1003 && GET_CODE (XEXP (x, 0)) == REG
1004 && GET_CODE (XEXP (x, 1)) == CONST_INT
1005 && ! CONSTANT_ADDRESS_P (XEXP (x, 1)))
1007 addend = INTVAL (XEXP (x, 1));
1012 /* If the address is (const (plus FOO const_int)), find the low-order
1013 part of the CONST_INT. Then load FOO plus any high-order part of the
1014 CONST_INT into a register. Our address is (plus reg low-part-const).
1015 This is done to reduce the number of GOT entries. */
1017 && GET_CODE (x) == CONST
1018 && GET_CODE (XEXP (x, 0)) == PLUS
1019 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT)
1021 addend = INTVAL (XEXP (XEXP (x, 0), 1));
1022 x = force_reg (Pmode, XEXP (XEXP (x, 0), 0));
1026 /* If we have a (plus reg const), emit the load as in (2), then add
1027 the two registers, and finally generate (plus reg low-part-const) as
1030 && GET_CODE (x) == PLUS
1031 && GET_CODE (XEXP (x, 0)) == REG
1032 && GET_CODE (XEXP (x, 1)) == CONST
1033 && GET_CODE (XEXP (XEXP (x, 1), 0)) == PLUS
1034 && GET_CODE (XEXP (XEXP (XEXP (x, 1), 0), 1)) == CONST_INT)
1036 addend = INTVAL (XEXP (XEXP (XEXP (x, 1), 0), 1));
1037 x = expand_simple_binop (Pmode, PLUS, XEXP (x, 0),
1038 XEXP (XEXP (XEXP (x, 1), 0), 0),
1039 NULL_RTX, 1, OPTAB_LIB_WIDEN);
1043 /* If this is a local symbol, split the address into HIGH/LO_SUM parts. */
1044 if (TARGET_EXPLICIT_RELOCS && symbolic_operand (x, Pmode))
1046 rtx r0, r16, eqv, tga, tp, insn, dest, seq;
1048 switch (tls_symbolic_operand_type (x))
1050 case TLS_MODEL_GLOBAL_DYNAMIC:
1053 r0 = gen_rtx_REG (Pmode, 0);
1054 r16 = gen_rtx_REG (Pmode, 16);
1055 tga = get_tls_get_addr ();
1056 dest = gen_reg_rtx (Pmode);
1057 seq = GEN_INT (alpha_next_sequence_number++);
1059 emit_insn (gen_movdi_er_tlsgd (r16, pic_offset_table_rtx, x, seq));
1060 insn = gen_call_value_osf_tlsgd (r0, tga, seq);
1061 insn = emit_call_insn (insn);
1062 CONST_OR_PURE_CALL_P (insn) = 1;
1063 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), r16);
1065 insn = get_insns ();
1068 emit_libcall_block (insn, dest, r0, x);
1071 case TLS_MODEL_LOCAL_DYNAMIC:
1074 r0 = gen_rtx_REG (Pmode, 0);
1075 r16 = gen_rtx_REG (Pmode, 16);
1076 tga = get_tls_get_addr ();
1077 scratch = gen_reg_rtx (Pmode);
1078 seq = GEN_INT (alpha_next_sequence_number++);
1080 emit_insn (gen_movdi_er_tlsldm (r16, pic_offset_table_rtx, seq));
1081 insn = gen_call_value_osf_tlsldm (r0, tga, seq);
1082 insn = emit_call_insn (insn);
1083 CONST_OR_PURE_CALL_P (insn) = 1;
1084 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), r16);
1086 insn = get_insns ();
1089 eqv = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx),
1090 UNSPEC_TLSLDM_CALL);
1091 emit_libcall_block (insn, scratch, r0, eqv);
1093 eqv = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, x), UNSPEC_DTPREL);
1094 eqv = gen_rtx_CONST (Pmode, eqv);
1096 if (alpha_tls_size == 64)
1098 dest = gen_reg_rtx (Pmode);
1099 emit_insn (gen_rtx_SET (VOIDmode, dest, eqv));
1100 emit_insn (gen_adddi3 (dest, dest, scratch));
1103 if (alpha_tls_size == 32)
1105 insn = gen_rtx_HIGH (Pmode, eqv);
1106 insn = gen_rtx_PLUS (Pmode, scratch, insn);
1107 scratch = gen_reg_rtx (Pmode);
1108 emit_insn (gen_rtx_SET (VOIDmode, scratch, insn));
1110 return gen_rtx_LO_SUM (Pmode, scratch, eqv);
1112 case TLS_MODEL_INITIAL_EXEC:
1113 eqv = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, x), UNSPEC_TPREL);
1114 eqv = gen_rtx_CONST (Pmode, eqv);
1115 tp = gen_reg_rtx (Pmode);
1116 scratch = gen_reg_rtx (Pmode);
1117 dest = gen_reg_rtx (Pmode);
1119 emit_insn (gen_load_tp (tp));
1120 emit_insn (gen_rtx_SET (VOIDmode, scratch, eqv));
1121 emit_insn (gen_adddi3 (dest, tp, scratch));
1124 case TLS_MODEL_LOCAL_EXEC:
1125 eqv = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, x), UNSPEC_TPREL);
1126 eqv = gen_rtx_CONST (Pmode, eqv);
1127 tp = gen_reg_rtx (Pmode);
1129 emit_insn (gen_load_tp (tp));
1130 if (alpha_tls_size == 32)
1132 insn = gen_rtx_HIGH (Pmode, eqv);
1133 insn = gen_rtx_PLUS (Pmode, tp, insn);
1134 tp = gen_reg_rtx (Pmode);
1135 emit_insn (gen_rtx_SET (VOIDmode, tp, insn));
1137 return gen_rtx_LO_SUM (Pmode, tp, eqv);
1140 if (local_symbolic_operand (x, Pmode))
1142 if (small_symbolic_operand (x, Pmode))
1146 if (!no_new_pseudos)
1147 scratch = gen_reg_rtx (Pmode);
1148 emit_insn (gen_rtx_SET (VOIDmode, scratch,
1149 gen_rtx_HIGH (Pmode, x)));
1150 return gen_rtx_LO_SUM (Pmode, scratch, x);
1159 HOST_WIDE_INT low, high;
1161 low = ((addend & 0xffff) ^ 0x8000) - 0x8000;
1163 high = ((addend & 0xffffffff) ^ 0x80000000) - 0x80000000;
1167 x = expand_simple_binop (Pmode, PLUS, x, GEN_INT (addend),
1168 (no_new_pseudos ? scratch : NULL_RTX),
1169 1, OPTAB_LIB_WIDEN);
1171 x = expand_simple_binop (Pmode, PLUS, x, GEN_INT (high),
1172 (no_new_pseudos ? scratch : NULL_RTX),
1173 1, OPTAB_LIB_WIDEN);
1175 return plus_constant (x, low);
1179 /* Primarily this is required for TLS symbols, but given that our move
1180 patterns *ought* to be able to handle any symbol at any time, we
1181 should never be spilling symbolic operands to the constant pool, ever. */
1184 alpha_cannot_force_const_mem (rtx x)
1186 enum rtx_code code = GET_CODE (x);
1187 return code == SYMBOL_REF || code == LABEL_REF || code == CONST;
1190 /* We do not allow indirect calls to be optimized into sibling calls, nor
1191 can we allow a call to a function with a different GP to be optimized
1195 alpha_function_ok_for_sibcall (tree decl, tree exp ATTRIBUTE_UNUSED)
1197 /* Can't do indirect tail calls, since we don't know if the target
1198 uses the same GP. */
1202 /* Otherwise, we can make a tail call if the target function shares
1204 return decl_has_samegp (decl);
1208 some_small_symbolic_operand_int (rtx *px, void *data ATTRIBUTE_UNUSED)
1212 /* Don't re-split. */
1213 if (GET_CODE (x) == LO_SUM)
1216 return small_symbolic_operand (x, Pmode) != 0;
1220 split_small_symbolic_operand_1 (rtx *px, void *data ATTRIBUTE_UNUSED)
1224 /* Don't re-split. */
1225 if (GET_CODE (x) == LO_SUM)
1228 if (small_symbolic_operand (x, Pmode))
1230 x = gen_rtx_LO_SUM (Pmode, pic_offset_table_rtx, x);
1239 split_small_symbolic_operand (rtx x)
1242 for_each_rtx (&x, split_small_symbolic_operand_1, NULL);
1246 /* Indicate that INSN cannot be duplicated. This is true for any insn
1247 that we've marked with gpdisp relocs, since those have to stay in
1248 1-1 correspondence with one another.
1250 Technically we could copy them if we could set up a mapping from one
1251 sequence number to another, across the set of insns to be duplicated.
1252 This seems overly complicated and error-prone since interblock motion
1253 from sched-ebb could move one of the pair of insns to a different block.
1255 Also cannot allow jsr insns to be duplicated. If they throw exceptions,
1256 then they'll be in a different block from their ldgp. Which could lead
1257 the bb reorder code to think that it would be ok to copy just the block
1258 containing the call and branch to the block containing the ldgp. */
1261 alpha_cannot_copy_insn_p (rtx insn)
1263 if (!reload_completed || !TARGET_EXPLICIT_RELOCS)
1265 if (recog_memoized (insn) >= 0)
1266 return get_attr_cannot_copy (insn);
1272 /* Try a machine-dependent way of reloading an illegitimate address
1273 operand. If we find one, push the reload and return the new rtx. */
1276 alpha_legitimize_reload_address (rtx x,
1277 enum machine_mode mode ATTRIBUTE_UNUSED,
1278 int opnum, int type,
1279 int ind_levels ATTRIBUTE_UNUSED)
1281 /* We must recognize output that we have already generated ourselves. */
1282 if (GET_CODE (x) == PLUS
1283 && GET_CODE (XEXP (x, 0)) == PLUS
1284 && GET_CODE (XEXP (XEXP (x, 0), 0)) == REG
1285 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
1286 && GET_CODE (XEXP (x, 1)) == CONST_INT)
1288 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
1289 BASE_REG_CLASS, GET_MODE (x), VOIDmode, 0, 0,
1294 /* We wish to handle large displacements off a base register by
1295 splitting the addend across an ldah and the mem insn. This
1296 cuts number of extra insns needed from 3 to 1. */
1297 if (GET_CODE (x) == PLUS
1298 && GET_CODE (XEXP (x, 0)) == REG
1299 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
1300 && REGNO_OK_FOR_BASE_P (REGNO (XEXP (x, 0)))
1301 && GET_CODE (XEXP (x, 1)) == CONST_INT)
1303 HOST_WIDE_INT val = INTVAL (XEXP (x, 1));
1304 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
1306 = (((val - low) & 0xffffffff) ^ 0x80000000) - 0x80000000;
1308 /* Check for 32-bit overflow. */
1309 if (high + low != val)
1312 /* Reload the high part into a base reg; leave the low part
1313 in the mem directly. */
1314 x = gen_rtx_PLUS (GET_MODE (x),
1315 gen_rtx_PLUS (GET_MODE (x), XEXP (x, 0),
1319 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
1320 BASE_REG_CLASS, GET_MODE (x), VOIDmode, 0, 0,
1328 /* Compute a (partial) cost for rtx X. Return true if the complete
1329 cost has been computed, and false if subexpressions should be
1330 scanned. In either case, *TOTAL contains the cost result. */
1333 alpha_rtx_costs (rtx x, int code, int outer_code, int *total)
1335 enum machine_mode mode = GET_MODE (x);
1336 bool float_mode_p = FLOAT_MODE_P (mode);
1337 const struct alpha_rtx_cost_data *cost_data;
1340 cost_data = &alpha_rtx_cost_size;
1342 cost_data = &alpha_rtx_cost_data[alpha_cpu];
1347 /* If this is an 8-bit constant, return zero since it can be used
1348 nearly anywhere with no cost. If it is a valid operand for an
1349 ADD or AND, likewise return 0 if we know it will be used in that
1350 context. Otherwise, return 2 since it might be used there later.
1351 All other constants take at least two insns. */
1352 if (INTVAL (x) >= 0 && INTVAL (x) < 256)
1360 if (x == CONST0_RTX (mode))
1362 else if ((outer_code == PLUS && add_operand (x, VOIDmode))
1363 || (outer_code == AND && and_operand (x, VOIDmode)))
1365 else if (add_operand (x, VOIDmode) || and_operand (x, VOIDmode))
1368 *total = COSTS_N_INSNS (2);
1374 if (TARGET_EXPLICIT_RELOCS && small_symbolic_operand (x, VOIDmode))
1375 *total = COSTS_N_INSNS (outer_code != MEM);
1376 else if (TARGET_EXPLICIT_RELOCS && local_symbolic_operand (x, VOIDmode))
1377 *total = COSTS_N_INSNS (1 + (outer_code != MEM));
1378 else if (tls_symbolic_operand_type (x))
1379 /* Estimate of cost for call_pal rduniq. */
1380 /* ??? How many insns do we emit here? More than one... */
1381 *total = COSTS_N_INSNS (15);
1383 /* Otherwise we do a load from the GOT. */
1384 *total = COSTS_N_INSNS (optimize_size ? 1 : alpha_memory_latency);
1390 *total = cost_data->fp_add;
1391 else if (GET_CODE (XEXP (x, 0)) == MULT
1392 && const48_operand (XEXP (XEXP (x, 0), 1), VOIDmode))
1394 *total = (rtx_cost (XEXP (XEXP (x, 0), 0), outer_code)
1395 + rtx_cost (XEXP (x, 1), outer_code) + COSTS_N_INSNS (1));
1402 *total = cost_data->fp_mult;
1403 else if (mode == DImode)
1404 *total = cost_data->int_mult_di;
1406 *total = cost_data->int_mult_si;
1410 if (GET_CODE (XEXP (x, 1)) == CONST_INT
1411 && INTVAL (XEXP (x, 1)) <= 3)
1413 *total = COSTS_N_INSNS (1);
1420 *total = cost_data->int_shift;
1425 *total = cost_data->fp_add;
1427 *total = cost_data->int_cmov;
1435 *total = cost_data->int_div;
1436 else if (mode == SFmode)
1437 *total = cost_data->fp_div_sf;
1439 *total = cost_data->fp_div_df;
1443 *total = COSTS_N_INSNS (optimize_size ? 1 : alpha_memory_latency);
1449 *total = COSTS_N_INSNS (1);
1457 *total = COSTS_N_INSNS (1) + cost_data->int_cmov;
1463 case UNSIGNED_FLOAT:
1467 case FLOAT_TRUNCATE:
1468 *total = cost_data->fp_add;
1476 /* REF is an alignable memory location. Place an aligned SImode
1477 reference into *PALIGNED_MEM and the number of bits to shift into
1478 *PBITNUM. SCRATCH is a free register for use in reloading out
1479 of range stack slots. */
1482 get_aligned_mem (rtx ref, rtx *paligned_mem, rtx *pbitnum)
1485 HOST_WIDE_INT offset = 0;
1487 if (GET_CODE (ref) != MEM)
1490 if (reload_in_progress
1491 && ! memory_address_p (GET_MODE (ref), XEXP (ref, 0)))
1493 base = find_replacement (&XEXP (ref, 0));
1495 if (! memory_address_p (GET_MODE (ref), base))
1500 base = XEXP (ref, 0);
1503 if (GET_CODE (base) == PLUS)
1504 offset += INTVAL (XEXP (base, 1)), base = XEXP (base, 0);
1507 = widen_memory_access (ref, SImode, (offset & ~3) - offset);
1509 if (WORDS_BIG_ENDIAN)
1510 *pbitnum = GEN_INT (32 - (GET_MODE_BITSIZE (GET_MODE (ref))
1511 + (offset & 3) * 8));
1513 *pbitnum = GEN_INT ((offset & 3) * 8);
1516 /* Similar, but just get the address. Handle the two reload cases.
1517 Add EXTRA_OFFSET to the address we return. */
1520 get_unaligned_address (rtx ref, int extra_offset)
1523 HOST_WIDE_INT offset = 0;
1525 if (GET_CODE (ref) != MEM)
1528 if (reload_in_progress
1529 && ! memory_address_p (GET_MODE (ref), XEXP (ref, 0)))
1531 base = find_replacement (&XEXP (ref, 0));
1533 if (! memory_address_p (GET_MODE (ref), base))
1538 base = XEXP (ref, 0);
1541 if (GET_CODE (base) == PLUS)
1542 offset += INTVAL (XEXP (base, 1)), base = XEXP (base, 0);
1544 return plus_constant (base, offset + extra_offset);
1547 /* On the Alpha, all (non-symbolic) constants except zero go into
1548 a floating-point register via memory. Note that we cannot
1549 return anything that is not a subset of CLASS, and that some
1550 symbolic constants cannot be dropped to memory. */
1553 alpha_preferred_reload_class(rtx x, enum reg_class class)
1555 /* Zero is present in any register class. */
1556 if (x == CONST0_RTX (GET_MODE (x)))
1559 /* These sorts of constants we can easily drop to memory. */
1560 if (GET_CODE (x) == CONST_INT || GET_CODE (x) == CONST_DOUBLE)
1562 if (class == FLOAT_REGS)
1564 if (class == ALL_REGS)
1565 return GENERAL_REGS;
1569 /* All other kinds of constants should not (and in the case of HIGH
1570 cannot) be dropped to memory -- instead we use a GENERAL_REGS
1571 secondary reload. */
1573 return (class == ALL_REGS ? GENERAL_REGS : class);
1578 /* Loading and storing HImode or QImode values to and from memory
1579 usually requires a scratch register. The exceptions are loading
1580 QImode and HImode from an aligned address to a general register
1581 unless byte instructions are permitted.
1583 We also cannot load an unaligned address or a paradoxical SUBREG
1584 into an FP register.
1586 We also cannot do integral arithmetic into FP regs, as might result
1587 from register elimination into a DImode fp register. */
1590 secondary_reload_class (enum reg_class class, enum machine_mode mode,
1593 if ((mode == QImode || mode == HImode) && ! TARGET_BWX)
1595 if (GET_CODE (x) == MEM
1596 || (GET_CODE (x) == REG && REGNO (x) >= FIRST_PSEUDO_REGISTER)
1597 || (GET_CODE (x) == SUBREG
1598 && (GET_CODE (SUBREG_REG (x)) == MEM
1599 || (GET_CODE (SUBREG_REG (x)) == REG
1600 && REGNO (SUBREG_REG (x)) >= FIRST_PSEUDO_REGISTER))))
1602 if (!in || !aligned_memory_operand(x, mode))
1603 return GENERAL_REGS;
1607 if (class == FLOAT_REGS)
1609 if (GET_CODE (x) == MEM && GET_CODE (XEXP (x, 0)) == AND)
1610 return GENERAL_REGS;
1612 if (GET_CODE (x) == SUBREG
1613 && (GET_MODE_SIZE (GET_MODE (x))
1614 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x)))))
1615 return GENERAL_REGS;
1617 if (in && INTEGRAL_MODE_P (mode)
1618 && ! (memory_operand (x, mode) || x == const0_rtx))
1619 return GENERAL_REGS;
1625 /* Subfunction of the following function. Update the flags of any MEM
1626 found in part of X. */
1629 alpha_set_memflags_1 (rtx *xp, void *data)
1631 rtx x = *xp, orig = (rtx) data;
1633 if (GET_CODE (x) != MEM)
1636 MEM_VOLATILE_P (x) = MEM_VOLATILE_P (orig);
1637 MEM_IN_STRUCT_P (x) = MEM_IN_STRUCT_P (orig);
1638 MEM_SCALAR_P (x) = MEM_SCALAR_P (orig);
1639 MEM_NOTRAP_P (x) = MEM_NOTRAP_P (orig);
1640 MEM_READONLY_P (x) = MEM_READONLY_P (orig);
1642 /* Sadly, we cannot use alias sets because the extra aliasing
1643 produced by the AND interferes. Given that two-byte quantities
1644 are the only thing we would be able to differentiate anyway,
1645 there does not seem to be any point in convoluting the early
1646 out of the alias check. */
1651 /* Given INSN, which is an INSN list or the PATTERN of a single insn
1652 generated to perform a memory operation, look for any MEMs in either
1653 a SET_DEST or a SET_SRC and copy the in-struct, unchanging, and
1654 volatile flags from REF into each of the MEMs found. If REF is not
1655 a MEM, don't do anything. */
1658 alpha_set_memflags (rtx insn, rtx ref)
1662 if (GET_CODE (ref) != MEM)
1665 /* This is only called from alpha.md, after having had something
1666 generated from one of the insn patterns. So if everything is
1667 zero, the pattern is already up-to-date. */
1668 if (!MEM_VOLATILE_P (ref)
1669 && !MEM_IN_STRUCT_P (ref)
1670 && !MEM_SCALAR_P (ref)
1671 && !MEM_NOTRAP_P (ref)
1672 && !MEM_READONLY_P (ref))
1676 base_ptr = &PATTERN (insn);
1679 for_each_rtx (base_ptr, alpha_set_memflags_1, (void *) ref);
1682 /* Internal routine for alpha_emit_set_const to check for N or below insns. */
1685 alpha_emit_set_const_1 (rtx target, enum machine_mode mode,
1686 HOST_WIDE_INT c, int n)
1690 /* Use a pseudo if highly optimizing and still generating RTL. */
1692 = (flag_expensive_optimizations && !no_new_pseudos ? 0 : target);
1695 /* If this is a sign-extended 32-bit constant, we can do this in at most
1696 three insns, so do it if we have enough insns left. We always have
1697 a sign-extended 32-bit constant when compiling on a narrow machine. */
1699 if (HOST_BITS_PER_WIDE_INT != 64
1700 || c >> 31 == -1 || c >> 31 == 0)
1702 HOST_WIDE_INT low = ((c & 0xffff) ^ 0x8000) - 0x8000;
1703 HOST_WIDE_INT tmp1 = c - low;
1704 HOST_WIDE_INT high = (((tmp1 >> 16) & 0xffff) ^ 0x8000) - 0x8000;
1705 HOST_WIDE_INT extra = 0;
1707 /* If HIGH will be interpreted as negative but the constant is
1708 positive, we must adjust it to do two ldha insns. */
1710 if ((high & 0x8000) != 0 && c >= 0)
1714 high = ((tmp1 >> 16) & 0xffff) - 2 * ((tmp1 >> 16) & 0x8000);
1717 if (c == low || (low == 0 && extra == 0))
1719 /* We used to use copy_to_suggested_reg (GEN_INT (c), target, mode)
1720 but that meant that we can't handle INT_MIN on 32-bit machines
1721 (like NT/Alpha), because we recurse indefinitely through
1722 emit_move_insn to gen_movdi. So instead, since we know exactly
1723 what we want, create it explicitly. */
1726 target = gen_reg_rtx (mode);
1727 emit_insn (gen_rtx_SET (VOIDmode, target, GEN_INT (c)));
1730 else if (n >= 2 + (extra != 0))
1734 emit_insn (gen_rtx_SET (VOIDmode, target, GEN_INT (high << 16)));
1738 temp = copy_to_suggested_reg (GEN_INT (high << 16),
1741 /* As of 2002-02-23, addsi3 is only available when not optimizing.
1742 This means that if we go through expand_binop, we'll try to
1743 generate extensions, etc, which will require new pseudos, which
1744 will fail during some split phases. The SImode add patterns
1745 still exist, but are not named. So build the insns by hand. */
1750 subtarget = gen_reg_rtx (mode);
1751 insn = gen_rtx_PLUS (mode, temp, GEN_INT (extra << 16));
1752 insn = gen_rtx_SET (VOIDmode, subtarget, insn);
1758 target = gen_reg_rtx (mode);
1759 insn = gen_rtx_PLUS (mode, temp, GEN_INT (low));
1760 insn = gen_rtx_SET (VOIDmode, target, insn);
1766 /* If we couldn't do it that way, try some other methods. But if we have
1767 no instructions left, don't bother. Likewise, if this is SImode and
1768 we can't make pseudos, we can't do anything since the expand_binop
1769 and expand_unop calls will widen and try to make pseudos. */
1771 if (n == 1 || (mode == SImode && no_new_pseudos))
1774 /* Next, see if we can load a related constant and then shift and possibly
1775 negate it to get the constant we want. Try this once each increasing
1776 numbers of insns. */
1778 for (i = 1; i < n; i++)
1780 /* First, see if minus some low bits, we've an easy load of
1783 new = ((c & 0xffff) ^ 0x8000) - 0x8000;
1785 && (temp = alpha_emit_set_const (subtarget, mode, c - new, i)) != 0)
1786 return expand_binop (mode, add_optab, temp, GEN_INT (new),
1787 target, 0, OPTAB_WIDEN);
1789 /* Next try complementing. */
1790 if ((temp = alpha_emit_set_const (subtarget, mode, ~ c, i)) != 0)
1791 return expand_unop (mode, one_cmpl_optab, temp, target, 0);
1793 /* Next try to form a constant and do a left shift. We can do this
1794 if some low-order bits are zero; the exact_log2 call below tells
1795 us that information. The bits we are shifting out could be any
1796 value, but here we'll just try the 0- and sign-extended forms of
1797 the constant. To try to increase the chance of having the same
1798 constant in more than one insn, start at the highest number of
1799 bits to shift, but try all possibilities in case a ZAPNOT will
1802 if ((bits = exact_log2 (c & - c)) > 0)
1803 for (; bits > 0; bits--)
1804 if ((temp = (alpha_emit_set_const
1805 (subtarget, mode, c >> bits, i))) != 0
1806 || ((temp = (alpha_emit_set_const
1808 ((unsigned HOST_WIDE_INT) c) >> bits, i)))
1810 return expand_binop (mode, ashl_optab, temp, GEN_INT (bits),
1811 target, 0, OPTAB_WIDEN);
1813 /* Now try high-order zero bits. Here we try the shifted-in bits as
1814 all zero and all ones. Be careful to avoid shifting outside the
1815 mode and to avoid shifting outside the host wide int size. */
1816 /* On narrow hosts, don't shift a 1 into the high bit, since we'll
1817 confuse the recursive call and set all of the high 32 bits. */
1819 if ((bits = (MIN (HOST_BITS_PER_WIDE_INT, GET_MODE_SIZE (mode) * 8)
1820 - floor_log2 (c) - 1 - (HOST_BITS_PER_WIDE_INT < 64))) > 0)
1821 for (; bits > 0; bits--)
1822 if ((temp = alpha_emit_set_const (subtarget, mode,
1824 || ((temp = (alpha_emit_set_const
1826 ((c << bits) | (((HOST_WIDE_INT) 1 << bits) - 1)),
1829 return expand_binop (mode, lshr_optab, temp, GEN_INT (bits),
1830 target, 1, OPTAB_WIDEN);
1832 /* Now try high-order 1 bits. We get that with a sign-extension.
1833 But one bit isn't enough here. Be careful to avoid shifting outside
1834 the mode and to avoid shifting outside the host wide int size. */
1836 if ((bits = (MIN (HOST_BITS_PER_WIDE_INT, GET_MODE_SIZE (mode) * 8)
1837 - floor_log2 (~ c) - 2)) > 0)
1838 for (; bits > 0; bits--)
1839 if ((temp = alpha_emit_set_const (subtarget, mode,
1841 || ((temp = (alpha_emit_set_const
1843 ((c << bits) | (((HOST_WIDE_INT) 1 << bits) - 1)),
1846 return expand_binop (mode, ashr_optab, temp, GEN_INT (bits),
1847 target, 0, OPTAB_WIDEN);
1850 #if HOST_BITS_PER_WIDE_INT == 64
1851 /* Finally, see if can load a value into the target that is the same as the
1852 constant except that all bytes that are 0 are changed to be 0xff. If we
1853 can, then we can do a ZAPNOT to obtain the desired constant. */
1856 for (i = 0; i < 64; i += 8)
1857 if ((new & ((HOST_WIDE_INT) 0xff << i)) == 0)
1858 new |= (HOST_WIDE_INT) 0xff << i;
1860 /* We are only called for SImode and DImode. If this is SImode, ensure that
1861 we are sign extended to a full word. */
1864 new = ((new & 0xffffffff) ^ 0x80000000) - 0x80000000;
1866 if (new != c && new != -1
1867 && (temp = alpha_emit_set_const (subtarget, mode, new, n - 1)) != 0)
1868 return expand_binop (mode, and_optab, temp, GEN_INT (c | ~ new),
1869 target, 0, OPTAB_WIDEN);
1875 /* Try to output insns to set TARGET equal to the constant C if it can be
1876 done in less than N insns. Do all computations in MODE. Returns the place
1877 where the output has been placed if it can be done and the insns have been
1878 emitted. If it would take more than N insns, zero is returned and no
1879 insns and emitted. */
1882 alpha_emit_set_const (rtx target, enum machine_mode mode,
1883 HOST_WIDE_INT c, int n)
1886 rtx orig_target = target;
1889 /* If we can't make any pseudos, TARGET is an SImode hard register, we
1890 can't load this constant in one insn, do this in DImode. */
1891 if (no_new_pseudos && mode == SImode
1892 && GET_CODE (target) == REG && REGNO (target) < FIRST_PSEUDO_REGISTER
1893 && (result = alpha_emit_set_const_1 (target, mode, c, 1)) == 0)
1895 target = gen_lowpart (DImode, target);
1899 /* Try 1 insn, then 2, then up to N. */
1900 for (i = 1; i <= n; i++)
1902 result = alpha_emit_set_const_1 (target, mode, c, i);
1905 rtx insn = get_last_insn ();
1906 rtx set = single_set (insn);
1907 if (! CONSTANT_P (SET_SRC (set)))
1908 set_unique_reg_note (get_last_insn (), REG_EQUAL, GEN_INT (c));
1913 /* Allow for the case where we changed the mode of TARGET. */
1914 if (result == target)
1915 result = orig_target;
1920 /* Having failed to find a 3 insn sequence in alpha_emit_set_const,
1921 fall back to a straight forward decomposition. We do this to avoid
1922 exponential run times encountered when looking for longer sequences
1923 with alpha_emit_set_const. */
1926 alpha_emit_set_long_const (rtx target, HOST_WIDE_INT c1, HOST_WIDE_INT c2)
1928 HOST_WIDE_INT d1, d2, d3, d4;
1930 /* Decompose the entire word */
1931 #if HOST_BITS_PER_WIDE_INT >= 64
1932 if (c2 != -(c1 < 0))
1934 d1 = ((c1 & 0xffff) ^ 0x8000) - 0x8000;
1936 d2 = ((c1 & 0xffffffff) ^ 0x80000000) - 0x80000000;
1937 c1 = (c1 - d2) >> 32;
1938 d3 = ((c1 & 0xffff) ^ 0x8000) - 0x8000;
1940 d4 = ((c1 & 0xffffffff) ^ 0x80000000) - 0x80000000;
1944 d1 = ((c1 & 0xffff) ^ 0x8000) - 0x8000;
1946 d2 = ((c1 & 0xffffffff) ^ 0x80000000) - 0x80000000;
1950 d3 = ((c2 & 0xffff) ^ 0x8000) - 0x8000;
1952 d4 = ((c2 & 0xffffffff) ^ 0x80000000) - 0x80000000;
1957 /* Construct the high word */
1960 emit_move_insn (target, GEN_INT (d4));
1962 emit_move_insn (target, gen_rtx_PLUS (DImode, target, GEN_INT (d3)));
1965 emit_move_insn (target, GEN_INT (d3));
1967 /* Shift it into place */
1968 emit_move_insn (target, gen_rtx_ASHIFT (DImode, target, GEN_INT (32)));
1970 /* Add in the low bits. */
1972 emit_move_insn (target, gen_rtx_PLUS (DImode, target, GEN_INT (d2)));
1974 emit_move_insn (target, gen_rtx_PLUS (DImode, target, GEN_INT (d1)));
1979 /* Expand a move instruction; return true if all work is done.
1980 We don't handle non-bwx subword loads here. */
1983 alpha_expand_mov (enum machine_mode mode, rtx *operands)
1985 /* Honor misaligned loads, for those we promised to do so. */
1986 if (GET_CODE (operands[1]) == MEM
1987 && alpha_vector_mode_supported_p (mode)
1988 && MEM_ALIGN (operands[1]) < GET_MODE_ALIGNMENT (mode))
1991 if (register_operand (operands[0], mode))
1994 tmp = gen_reg_rtx (mode);
1995 alpha_expand_unaligned_load (tmp, operands[1], 8, 0, 0);
1996 if (tmp == operands[0])
2001 /* If the output is not a register, the input must be. */
2002 if (GET_CODE (operands[0]) == MEM
2003 && ! reg_or_0_operand (operands[1], mode))
2004 operands[1] = force_reg (mode, operands[1]);
2006 /* Honor misaligned stores, for those we promised to do so. */
2007 if (GET_CODE (operands[0]) == MEM
2008 && alpha_vector_mode_supported_p (mode)
2009 && MEM_ALIGN (operands[0]) < GET_MODE_ALIGNMENT (mode))
2011 alpha_expand_unaligned_store (operands[0], operands[1], 8, 0);
2015 /* Allow legitimize_address to perform some simplifications. */
2016 if (mode == Pmode && symbolic_operand (operands[1], mode))
2020 tmp = alpha_legitimize_address (operands[1], operands[0], mode);
2023 if (tmp == operands[0])
2030 /* Early out for non-constants and valid constants. */
2031 if (! CONSTANT_P (operands[1]) || input_operand (operands[1], mode))
2034 /* Split large integers. */
2035 if (GET_CODE (operands[1]) == CONST_INT
2036 || GET_CODE (operands[1]) == CONST_DOUBLE)
2038 HOST_WIDE_INT i0, i1;
2039 rtx temp = NULL_RTX;
2041 if (GET_CODE (operands[1]) == CONST_INT)
2043 i0 = INTVAL (operands[1]);
2046 else if (HOST_BITS_PER_WIDE_INT >= 64)
2048 i0 = CONST_DOUBLE_LOW (operands[1]);
2053 i0 = CONST_DOUBLE_LOW (operands[1]);
2054 i1 = CONST_DOUBLE_HIGH (operands[1]);
2057 if (HOST_BITS_PER_WIDE_INT >= 64 || i1 == -(i0 < 0))
2058 temp = alpha_emit_set_const (operands[0], mode, i0, 3);
2060 if (!temp && TARGET_BUILD_CONSTANTS)
2061 temp = alpha_emit_set_long_const (operands[0], i0, i1);
2065 if (rtx_equal_p (operands[0], temp))
2072 /* Otherwise we've nothing left but to drop the thing to memory. */
2073 operands[1] = force_const_mem (mode, operands[1]);
2074 if (reload_in_progress)
2076 emit_move_insn (operands[0], XEXP (operands[1], 0));
2077 operands[1] = copy_rtx (operands[1]);
2078 XEXP (operands[1], 0) = operands[0];
2081 operands[1] = validize_mem (operands[1]);
2085 /* Expand a non-bwx QImode or HImode move instruction;
2086 return true if all work is done. */
2089 alpha_expand_mov_nobwx (enum machine_mode mode, rtx *operands)
2091 /* If the output is not a register, the input must be. */
2092 if (GET_CODE (operands[0]) == MEM)
2093 operands[1] = force_reg (mode, operands[1]);
2095 /* Handle four memory cases, unaligned and aligned for either the input
2096 or the output. The only case where we can be called during reload is
2097 for aligned loads; all other cases require temporaries. */
2099 if (GET_CODE (operands[1]) == MEM
2100 || (GET_CODE (operands[1]) == SUBREG
2101 && GET_CODE (SUBREG_REG (operands[1])) == MEM)
2102 || (reload_in_progress && GET_CODE (operands[1]) == REG
2103 && REGNO (operands[1]) >= FIRST_PSEUDO_REGISTER)
2104 || (reload_in_progress && GET_CODE (operands[1]) == SUBREG
2105 && GET_CODE (SUBREG_REG (operands[1])) == REG
2106 && REGNO (SUBREG_REG (operands[1])) >= FIRST_PSEUDO_REGISTER))
2108 if (aligned_memory_operand (operands[1], mode))
2110 if (reload_in_progress)
2112 emit_insn ((mode == QImode
2113 ? gen_reload_inqi_help
2114 : gen_reload_inhi_help)
2115 (operands[0], operands[1],
2116 gen_rtx_REG (SImode, REGNO (operands[0]))));
2120 rtx aligned_mem, bitnum;
2121 rtx scratch = gen_reg_rtx (SImode);
2125 get_aligned_mem (operands[1], &aligned_mem, &bitnum);
2127 subtarget = operands[0];
2128 if (GET_CODE (subtarget) == REG)
2129 subtarget = gen_lowpart (DImode, subtarget), copyout = false;
2131 subtarget = gen_reg_rtx (DImode), copyout = true;
2133 emit_insn ((mode == QImode
2134 ? gen_aligned_loadqi
2135 : gen_aligned_loadhi)
2136 (subtarget, aligned_mem, bitnum, scratch));
2139 emit_move_insn (operands[0], gen_lowpart (mode, subtarget));
2144 /* Don't pass these as parameters since that makes the generated
2145 code depend on parameter evaluation order which will cause
2146 bootstrap failures. */
2148 rtx temp1, temp2, seq, subtarget;
2151 temp1 = gen_reg_rtx (DImode);
2152 temp2 = gen_reg_rtx (DImode);
2154 subtarget = operands[0];
2155 if (GET_CODE (subtarget) == REG)
2156 subtarget = gen_lowpart (DImode, subtarget), copyout = false;
2158 subtarget = gen_reg_rtx (DImode), copyout = true;
2160 seq = ((mode == QImode
2161 ? gen_unaligned_loadqi
2162 : gen_unaligned_loadhi)
2163 (subtarget, get_unaligned_address (operands[1], 0),
2165 alpha_set_memflags (seq, operands[1]);
2169 emit_move_insn (operands[0], gen_lowpart (mode, subtarget));
2174 if (GET_CODE (operands[0]) == MEM
2175 || (GET_CODE (operands[0]) == SUBREG
2176 && GET_CODE (SUBREG_REG (operands[0])) == MEM)
2177 || (reload_in_progress && GET_CODE (operands[0]) == REG
2178 && REGNO (operands[0]) >= FIRST_PSEUDO_REGISTER)
2179 || (reload_in_progress && GET_CODE (operands[0]) == SUBREG
2180 && GET_CODE (SUBREG_REG (operands[0])) == REG
2181 && REGNO (operands[0]) >= FIRST_PSEUDO_REGISTER))
2183 if (aligned_memory_operand (operands[0], mode))
2185 rtx aligned_mem, bitnum;
2186 rtx temp1 = gen_reg_rtx (SImode);
2187 rtx temp2 = gen_reg_rtx (SImode);
2189 get_aligned_mem (operands[0], &aligned_mem, &bitnum);
2191 emit_insn (gen_aligned_store (aligned_mem, operands[1], bitnum,
2196 rtx temp1 = gen_reg_rtx (DImode);
2197 rtx temp2 = gen_reg_rtx (DImode);
2198 rtx temp3 = gen_reg_rtx (DImode);
2199 rtx seq = ((mode == QImode
2200 ? gen_unaligned_storeqi
2201 : gen_unaligned_storehi)
2202 (get_unaligned_address (operands[0], 0),
2203 operands[1], temp1, temp2, temp3));
2205 alpha_set_memflags (seq, operands[0]);
2214 /* Generate an unsigned DImode to FP conversion. This is the same code
2215 optabs would emit if we didn't have TFmode patterns.
2217 For SFmode, this is the only construction I've found that can pass
2218 gcc.c-torture/execute/ieee/rbug.c. No scenario that uses DFmode
2219 intermediates will work, because you'll get intermediate rounding
2220 that ruins the end result. Some of this could be fixed by turning
2221 on round-to-positive-infinity, but that requires diddling the fpsr,
2222 which kills performance. I tried turning this around and converting
2223 to a negative number, so that I could turn on /m, but either I did
2224 it wrong or there's something else cause I wound up with the exact
2225 same single-bit error. There is a branch-less form of this same code:
2236 fcmoveq $f10,$f11,$f0
2238 I'm not using it because it's the same number of instructions as
2239 this branch-full form, and it has more serialized long latency
2240 instructions on the critical path.
2242 For DFmode, we can avoid rounding errors by breaking up the word
2243 into two pieces, converting them separately, and adding them back:
2245 LC0: .long 0,0x5f800000
2250 cpyse $f11,$f31,$f10
2251 cpyse $f31,$f11,$f11
2259 This doesn't seem to be a clear-cut win over the optabs form.
2260 It probably all depends on the distribution of numbers being
2261 converted -- in the optabs form, all but high-bit-set has a
2262 much lower minimum execution time. */
2265 alpha_emit_floatuns (rtx operands[2])
2267 rtx neglab, donelab, i0, i1, f0, in, out;
2268 enum machine_mode mode;
2271 in = force_reg (DImode, operands[1]);
2272 mode = GET_MODE (out);
2273 neglab = gen_label_rtx ();
2274 donelab = gen_label_rtx ();
2275 i0 = gen_reg_rtx (DImode);
2276 i1 = gen_reg_rtx (DImode);
2277 f0 = gen_reg_rtx (mode);
2279 emit_cmp_and_jump_insns (in, const0_rtx, LT, const0_rtx, DImode, 0, neglab);
2281 emit_insn (gen_rtx_SET (VOIDmode, out, gen_rtx_FLOAT (mode, in)));
2282 emit_jump_insn (gen_jump (donelab));
2285 emit_label (neglab);
2287 emit_insn (gen_lshrdi3 (i0, in, const1_rtx));
2288 emit_insn (gen_anddi3 (i1, in, const1_rtx));
2289 emit_insn (gen_iordi3 (i0, i0, i1));
2290 emit_insn (gen_rtx_SET (VOIDmode, f0, gen_rtx_FLOAT (mode, i0)));
2291 emit_insn (gen_rtx_SET (VOIDmode, out, gen_rtx_PLUS (mode, f0, f0)));
2293 emit_label (donelab);
2296 /* Generate the comparison for a conditional branch. */
2299 alpha_emit_conditional_branch (enum rtx_code code)
2301 enum rtx_code cmp_code, branch_code;
2302 enum machine_mode cmp_mode, branch_mode = VOIDmode;
2303 rtx op0 = alpha_compare.op0, op1 = alpha_compare.op1;
2306 if (alpha_compare.fp_p && GET_MODE (op0) == TFmode)
2308 if (! TARGET_HAS_XFLOATING_LIBS)
2311 /* X_floating library comparison functions return
2315 Convert the compare against the raw return value. */
2337 op0 = alpha_emit_xfloating_compare (cmp_code, op0, op1);
2339 alpha_compare.fp_p = 0;
2342 /* The general case: fold the comparison code to the types of compares
2343 that we have, choosing the branch as necessary. */
2346 case EQ: case LE: case LT: case LEU: case LTU:
2348 /* We have these compares: */
2349 cmp_code = code, branch_code = NE;
2354 /* These must be reversed. */
2355 cmp_code = reverse_condition (code), branch_code = EQ;
2358 case GE: case GT: case GEU: case GTU:
2359 /* For FP, we swap them, for INT, we reverse them. */
2360 if (alpha_compare.fp_p)
2362 cmp_code = swap_condition (code);
2364 tem = op0, op0 = op1, op1 = tem;
2368 cmp_code = reverse_condition (code);
2377 if (alpha_compare.fp_p)
2380 if (flag_unsafe_math_optimizations)
2382 /* When we are not as concerned about non-finite values, and we
2383 are comparing against zero, we can branch directly. */
2384 if (op1 == CONST0_RTX (DFmode))
2385 cmp_code = UNKNOWN, branch_code = code;
2386 else if (op0 == CONST0_RTX (DFmode))
2388 /* Undo the swap we probably did just above. */
2389 tem = op0, op0 = op1, op1 = tem;
2390 branch_code = swap_condition (cmp_code);
2396 /* ??? We mark the branch mode to be CCmode to prevent the
2397 compare and branch from being combined, since the compare
2398 insn follows IEEE rules that the branch does not. */
2399 branch_mode = CCmode;
2406 /* The following optimizations are only for signed compares. */
2407 if (code != LEU && code != LTU && code != GEU && code != GTU)
2409 /* Whee. Compare and branch against 0 directly. */
2410 if (op1 == const0_rtx)
2411 cmp_code = UNKNOWN, branch_code = code;
2413 /* If the constants doesn't fit into an immediate, but can
2414 be generated by lda/ldah, we adjust the argument and
2415 compare against zero, so we can use beq/bne directly. */
2416 /* ??? Don't do this when comparing against symbols, otherwise
2417 we'll reduce (&x == 0x1234) to (&x-0x1234 == 0), which will
2418 be declared false out of hand (at least for non-weak). */
2419 else if (GET_CODE (op1) == CONST_INT
2420 && (code == EQ || code == NE)
2421 && !(symbolic_operand (op0, VOIDmode)
2422 || (GET_CODE (op0) == REG && REG_POINTER (op0))))
2424 HOST_WIDE_INT v = INTVAL (op1), n = -v;
2426 if (! CONST_OK_FOR_LETTER_P (v, 'I')
2427 && (CONST_OK_FOR_LETTER_P (n, 'K')
2428 || CONST_OK_FOR_LETTER_P (n, 'L')))
2430 cmp_code = PLUS, branch_code = code;
2436 if (!reg_or_0_operand (op0, DImode))
2437 op0 = force_reg (DImode, op0);
2438 if (cmp_code != PLUS && !reg_or_8bit_operand (op1, DImode))
2439 op1 = force_reg (DImode, op1);
2442 /* Emit an initial compare instruction, if necessary. */
2444 if (cmp_code != UNKNOWN)
2446 tem = gen_reg_rtx (cmp_mode);
2447 emit_move_insn (tem, gen_rtx_fmt_ee (cmp_code, cmp_mode, op0, op1));
2450 /* Zero the operands. */
2451 memset (&alpha_compare, 0, sizeof (alpha_compare));
2453 /* Return the branch comparison. */
2454 return gen_rtx_fmt_ee (branch_code, branch_mode, tem, CONST0_RTX (cmp_mode));
2457 /* Certain simplifications can be done to make invalid setcc operations
2458 valid. Return the final comparison, or NULL if we can't work. */
2461 alpha_emit_setcc (enum rtx_code code)
2463 enum rtx_code cmp_code;
2464 rtx op0 = alpha_compare.op0, op1 = alpha_compare.op1;
2465 int fp_p = alpha_compare.fp_p;
2468 /* Zero the operands. */
2469 memset (&alpha_compare, 0, sizeof (alpha_compare));
2471 if (fp_p && GET_MODE (op0) == TFmode)
2473 if (! TARGET_HAS_XFLOATING_LIBS)
2476 /* X_floating library comparison functions return
2480 Convert the compare against the raw return value. */
2482 if (code == UNORDERED || code == ORDERED)
2487 op0 = alpha_emit_xfloating_compare (cmp_code, op0, op1);
2491 if (code == UNORDERED)
2493 else if (code == ORDERED)
2499 if (fp_p && !TARGET_FIX)
2502 /* The general case: fold the comparison code to the types of compares
2503 that we have, choosing the branch as necessary. */
2508 case EQ: case LE: case LT: case LEU: case LTU:
2510 /* We have these compares. */
2512 cmp_code = code, code = NE;
2516 if (!fp_p && op1 == const0_rtx)
2521 cmp_code = reverse_condition (code);
2525 case GE: case GT: case GEU: case GTU:
2526 /* These normally need swapping, but for integer zero we have
2527 special patterns that recognize swapped operands. */
2528 if (!fp_p && op1 == const0_rtx)
2530 code = swap_condition (code);
2532 cmp_code = code, code = NE;
2533 tmp = op0, op0 = op1, op1 = tmp;
2542 if (!register_operand (op0, DImode))
2543 op0 = force_reg (DImode, op0);
2544 if (!reg_or_8bit_operand (op1, DImode))
2545 op1 = force_reg (DImode, op1);
2548 /* Emit an initial compare instruction, if necessary. */
2549 if (cmp_code != UNKNOWN)
2551 enum machine_mode mode = fp_p ? DFmode : DImode;
2553 tmp = gen_reg_rtx (mode);
2554 emit_insn (gen_rtx_SET (VOIDmode, tmp,
2555 gen_rtx_fmt_ee (cmp_code, mode, op0, op1)));
2557 op0 = fp_p ? gen_lowpart (DImode, tmp) : tmp;
2561 /* Return the setcc comparison. */
2562 return gen_rtx_fmt_ee (code, DImode, op0, op1);
2566 /* Rewrite a comparison against zero CMP of the form
2567 (CODE (cc0) (const_int 0)) so it can be written validly in
2568 a conditional move (if_then_else CMP ...).
2569 If both of the operands that set cc0 are nonzero we must emit
2570 an insn to perform the compare (it can't be done within
2571 the conditional move). */
2574 alpha_emit_conditional_move (rtx cmp, enum machine_mode mode)
2576 enum rtx_code code = GET_CODE (cmp);
2577 enum rtx_code cmov_code = NE;
2578 rtx op0 = alpha_compare.op0;
2579 rtx op1 = alpha_compare.op1;
2580 int fp_p = alpha_compare.fp_p;
2581 enum machine_mode cmp_mode
2582 = (GET_MODE (op0) == VOIDmode ? DImode : GET_MODE (op0));
2583 enum machine_mode cmp_op_mode = fp_p ? DFmode : DImode;
2584 enum machine_mode cmov_mode = VOIDmode;
2585 int local_fast_math = flag_unsafe_math_optimizations;
2588 /* Zero the operands. */
2589 memset (&alpha_compare, 0, sizeof (alpha_compare));
2591 if (fp_p != FLOAT_MODE_P (mode))
2593 enum rtx_code cmp_code;
2598 /* If we have fp<->int register move instructions, do a cmov by
2599 performing the comparison in fp registers, and move the
2600 zero/nonzero value to integer registers, where we can then
2601 use a normal cmov, or vice-versa. */
2605 case EQ: case LE: case LT: case LEU: case LTU:
2606 /* We have these compares. */
2607 cmp_code = code, code = NE;
2611 /* This must be reversed. */
2612 cmp_code = EQ, code = EQ;
2615 case GE: case GT: case GEU: case GTU:
2616 /* These normally need swapping, but for integer zero we have
2617 special patterns that recognize swapped operands. */
2618 if (!fp_p && op1 == const0_rtx)
2619 cmp_code = code, code = NE;
2622 cmp_code = swap_condition (code);
2624 tem = op0, op0 = op1, op1 = tem;
2632 tem = gen_reg_rtx (cmp_op_mode);
2633 emit_insn (gen_rtx_SET (VOIDmode, tem,
2634 gen_rtx_fmt_ee (cmp_code, cmp_op_mode,
2637 cmp_mode = cmp_op_mode = fp_p ? DImode : DFmode;
2638 op0 = gen_lowpart (cmp_op_mode, tem);
2639 op1 = CONST0_RTX (cmp_op_mode);
2641 local_fast_math = 1;
2644 /* We may be able to use a conditional move directly.
2645 This avoids emitting spurious compares. */
2646 if (signed_comparison_operator (cmp, VOIDmode)
2647 && (!fp_p || local_fast_math)
2648 && (op0 == CONST0_RTX (cmp_mode) || op1 == CONST0_RTX (cmp_mode)))
2649 return gen_rtx_fmt_ee (code, VOIDmode, op0, op1);
2651 /* We can't put the comparison inside the conditional move;
2652 emit a compare instruction and put that inside the
2653 conditional move. Make sure we emit only comparisons we have;
2654 swap or reverse as necessary. */
2661 case EQ: case LE: case LT: case LEU: case LTU:
2662 /* We have these compares: */
2666 /* This must be reversed. */
2667 code = reverse_condition (code);
2671 case GE: case GT: case GEU: case GTU:
2672 /* These must be swapped. */
2673 if (op1 != CONST0_RTX (cmp_mode))
2675 code = swap_condition (code);
2676 tem = op0, op0 = op1, op1 = tem;
2686 if (!reg_or_0_operand (op0, DImode))
2687 op0 = force_reg (DImode, op0);
2688 if (!reg_or_8bit_operand (op1, DImode))
2689 op1 = force_reg (DImode, op1);
2692 /* ??? We mark the branch mode to be CCmode to prevent the compare
2693 and cmov from being combined, since the compare insn follows IEEE
2694 rules that the cmov does not. */
2695 if (fp_p && !local_fast_math)
2698 tem = gen_reg_rtx (cmp_op_mode);
2699 emit_move_insn (tem, gen_rtx_fmt_ee (code, cmp_op_mode, op0, op1));
2700 return gen_rtx_fmt_ee (cmov_code, cmov_mode, tem, CONST0_RTX (cmp_op_mode));
2703 /* Simplify a conditional move of two constants into a setcc with
2704 arithmetic. This is done with a splitter since combine would
2705 just undo the work if done during code generation. It also catches
2706 cases we wouldn't have before cse. */
2709 alpha_split_conditional_move (enum rtx_code code, rtx dest, rtx cond,
2710 rtx t_rtx, rtx f_rtx)
2712 HOST_WIDE_INT t, f, diff;
2713 enum machine_mode mode;
2714 rtx target, subtarget, tmp;
2716 mode = GET_MODE (dest);
2721 if (((code == NE || code == EQ) && diff < 0)
2722 || (code == GE || code == GT))
2724 code = reverse_condition (code);
2725 diff = t, t = f, f = diff;
2729 subtarget = target = dest;
2732 target = gen_lowpart (DImode, dest);
2733 if (! no_new_pseudos)
2734 subtarget = gen_reg_rtx (DImode);
2738 /* Below, we must be careful to use copy_rtx on target and subtarget
2739 in intermediate insns, as they may be a subreg rtx, which may not
2742 if (f == 0 && exact_log2 (diff) > 0
2743 /* On EV6, we've got enough shifters to make non-arithmetic shifts
2744 viable over a longer latency cmove. On EV5, the E0 slot is a
2745 scarce resource, and on EV4 shift has the same latency as a cmove. */
2746 && (diff <= 8 || alpha_cpu == PROCESSOR_EV6))
2748 tmp = gen_rtx_fmt_ee (code, DImode, cond, const0_rtx);
2749 emit_insn (gen_rtx_SET (VOIDmode, copy_rtx (subtarget), tmp));
2751 tmp = gen_rtx_ASHIFT (DImode, copy_rtx (subtarget),
2752 GEN_INT (exact_log2 (t)));
2753 emit_insn (gen_rtx_SET (VOIDmode, target, tmp));
2755 else if (f == 0 && t == -1)
2757 tmp = gen_rtx_fmt_ee (code, DImode, cond, const0_rtx);
2758 emit_insn (gen_rtx_SET (VOIDmode, copy_rtx (subtarget), tmp));
2760 emit_insn (gen_negdi2 (target, copy_rtx (subtarget)));
2762 else if (diff == 1 || diff == 4 || diff == 8)
2766 tmp = gen_rtx_fmt_ee (code, DImode, cond, const0_rtx);
2767 emit_insn (gen_rtx_SET (VOIDmode, copy_rtx (subtarget), tmp));
2770 emit_insn (gen_adddi3 (target, copy_rtx (subtarget), GEN_INT (f)));
2773 add_op = GEN_INT (f);
2774 if (sext_add_operand (add_op, mode))
2776 tmp = gen_rtx_MULT (DImode, copy_rtx (subtarget),
2778 tmp = gen_rtx_PLUS (DImode, tmp, add_op);
2779 emit_insn (gen_rtx_SET (VOIDmode, target, tmp));
2791 /* Look up the function X_floating library function name for the
2794 struct xfloating_op GTY(())
2796 const enum rtx_code code;
2797 const char *const GTY((skip)) osf_func;
2798 const char *const GTY((skip)) vms_func;
2802 static GTY(()) struct xfloating_op xfloating_ops[] =
2804 { PLUS, "_OtsAddX", "OTS$ADD_X", 0 },
2805 { MINUS, "_OtsSubX", "OTS$SUB_X", 0 },
2806 { MULT, "_OtsMulX", "OTS$MUL_X", 0 },
2807 { DIV, "_OtsDivX", "OTS$DIV_X", 0 },
2808 { EQ, "_OtsEqlX", "OTS$EQL_X", 0 },
2809 { NE, "_OtsNeqX", "OTS$NEQ_X", 0 },
2810 { LT, "_OtsLssX", "OTS$LSS_X", 0 },
2811 { LE, "_OtsLeqX", "OTS$LEQ_X", 0 },
2812 { GT, "_OtsGtrX", "OTS$GTR_X", 0 },
2813 { GE, "_OtsGeqX", "OTS$GEQ_X", 0 },
2814 { FIX, "_OtsCvtXQ", "OTS$CVTXQ", 0 },
2815 { FLOAT, "_OtsCvtQX", "OTS$CVTQX", 0 },
2816 { UNSIGNED_FLOAT, "_OtsCvtQUX", "OTS$CVTQUX", 0 },
2817 { FLOAT_EXTEND, "_OtsConvertFloatTX", "OTS$CVT_FLOAT_T_X", 0 },
2818 { FLOAT_TRUNCATE, "_OtsConvertFloatXT", "OTS$CVT_FLOAT_X_T", 0 }
2821 static GTY(()) struct xfloating_op vax_cvt_ops[] =
2823 { FLOAT_EXTEND, "_OtsConvertFloatGX", "OTS$CVT_FLOAT_G_X", 0 },
2824 { FLOAT_TRUNCATE, "_OtsConvertFloatXG", "OTS$CVT_FLOAT_X_G", 0 }
2828 alpha_lookup_xfloating_lib_func (enum rtx_code code)
2830 struct xfloating_op *ops = xfloating_ops;
2831 long n = ARRAY_SIZE (xfloating_ops);
2834 /* How irritating. Nothing to key off for the main table. */
2835 if (TARGET_FLOAT_VAX && (code == FLOAT_EXTEND || code == FLOAT_TRUNCATE))
2838 n = ARRAY_SIZE (vax_cvt_ops);
2841 for (i = 0; i < n; ++i, ++ops)
2842 if (ops->code == code)
2844 rtx func = ops->libcall;
2847 func = init_one_libfunc (TARGET_ABI_OPEN_VMS
2848 ? ops->vms_func : ops->osf_func);
2849 ops->libcall = func;
2857 /* Most X_floating operations take the rounding mode as an argument.
2858 Compute that here. */
2861 alpha_compute_xfloating_mode_arg (enum rtx_code code,
2862 enum alpha_fp_rounding_mode round)
2868 case ALPHA_FPRM_NORM:
2871 case ALPHA_FPRM_MINF:
2874 case ALPHA_FPRM_CHOP:
2877 case ALPHA_FPRM_DYN:
2883 /* XXX For reference, round to +inf is mode = 3. */
2886 if (code == FLOAT_TRUNCATE && alpha_fptm == ALPHA_FPTM_N)
2892 /* Emit an X_floating library function call.
2894 Note that these functions do not follow normal calling conventions:
2895 TFmode arguments are passed in two integer registers (as opposed to
2896 indirect); TFmode return values appear in R16+R17.
2898 FUNC is the function to call.
2899 TARGET is where the output belongs.
2900 OPERANDS are the inputs.
2901 NOPERANDS is the count of inputs.
2902 EQUIV is the expression equivalent for the function.
2906 alpha_emit_xfloating_libcall (rtx func, rtx target, rtx operands[],
2907 int noperands, rtx equiv)
2909 rtx usage = NULL_RTX, tmp, reg;
2914 for (i = 0; i < noperands; ++i)
2916 switch (GET_MODE (operands[i]))
2919 reg = gen_rtx_REG (TFmode, regno);
2924 reg = gen_rtx_REG (DFmode, regno + 32);
2929 if (GET_CODE (operands[i]) != CONST_INT)
2933 reg = gen_rtx_REG (DImode, regno);
2941 emit_move_insn (reg, operands[i]);
2942 usage = alloc_EXPR_LIST (0, gen_rtx_USE (VOIDmode, reg), usage);
2945 switch (GET_MODE (target))
2948 reg = gen_rtx_REG (TFmode, 16);
2951 reg = gen_rtx_REG (DFmode, 32);
2954 reg = gen_rtx_REG (DImode, 0);
2960 tmp = gen_rtx_MEM (QImode, func);
2961 tmp = emit_call_insn (GEN_CALL_VALUE (reg, tmp, const0_rtx,
2962 const0_rtx, const0_rtx));
2963 CALL_INSN_FUNCTION_USAGE (tmp) = usage;
2964 CONST_OR_PURE_CALL_P (tmp) = 1;
2969 emit_libcall_block (tmp, target, reg, equiv);
2972 /* Emit an X_floating library function call for arithmetic (+,-,*,/). */
2975 alpha_emit_xfloating_arith (enum rtx_code code, rtx operands[])
2979 rtx out_operands[3];
2981 func = alpha_lookup_xfloating_lib_func (code);
2982 mode = alpha_compute_xfloating_mode_arg (code, alpha_fprm);
2984 out_operands[0] = operands[1];
2985 out_operands[1] = operands[2];
2986 out_operands[2] = GEN_INT (mode);
2987 alpha_emit_xfloating_libcall (func, operands[0], out_operands, 3,
2988 gen_rtx_fmt_ee (code, TFmode, operands[1],
2992 /* Emit an X_floating library function call for a comparison. */
2995 alpha_emit_xfloating_compare (enum rtx_code code, rtx op0, rtx op1)
2998 rtx out, operands[2];
3000 func = alpha_lookup_xfloating_lib_func (code);
3004 out = gen_reg_rtx (DImode);
3006 /* ??? Strange mode for equiv because what's actually returned
3007 is -1,0,1, not a proper boolean value. */
3008 alpha_emit_xfloating_libcall (func, out, operands, 2,
3009 gen_rtx_fmt_ee (code, CCmode, op0, op1));
3014 /* Emit an X_floating library function call for a conversion. */
3017 alpha_emit_xfloating_cvt (enum rtx_code orig_code, rtx operands[])
3019 int noperands = 1, mode;
3020 rtx out_operands[2];
3022 enum rtx_code code = orig_code;
3024 if (code == UNSIGNED_FIX)
3027 func = alpha_lookup_xfloating_lib_func (code);
3029 out_operands[0] = operands[1];
3034 mode = alpha_compute_xfloating_mode_arg (code, ALPHA_FPRM_CHOP);
3035 out_operands[1] = GEN_INT (mode);
3038 case FLOAT_TRUNCATE:
3039 mode = alpha_compute_xfloating_mode_arg (code, alpha_fprm);
3040 out_operands[1] = GEN_INT (mode);
3047 alpha_emit_xfloating_libcall (func, operands[0], out_operands, noperands,
3048 gen_rtx_fmt_e (orig_code,
3049 GET_MODE (operands[0]),
3053 /* Split a TFmode OP[1] into DImode OP[2,3] and likewise for
3054 OP[0] into OP[0,1]. Naturally, output operand ordering is
3058 alpha_split_tfmode_pair (rtx operands[4])
3060 if (GET_CODE (operands[1]) == REG)
3062 operands[3] = gen_rtx_REG (DImode, REGNO (operands[1]) + 1);
3063 operands[2] = gen_rtx_REG (DImode, REGNO (operands[1]));
3065 else if (GET_CODE (operands[1]) == MEM)
3067 operands[3] = adjust_address (operands[1], DImode, 8);
3068 operands[2] = adjust_address (operands[1], DImode, 0);
3070 else if (operands[1] == CONST0_RTX (TFmode))
3071 operands[2] = operands[3] = const0_rtx;
3075 if (GET_CODE (operands[0]) == REG)
3077 operands[1] = gen_rtx_REG (DImode, REGNO (operands[0]) + 1);
3078 operands[0] = gen_rtx_REG (DImode, REGNO (operands[0]));
3080 else if (GET_CODE (operands[0]) == MEM)
3082 operands[1] = adjust_address (operands[0], DImode, 8);
3083 operands[0] = adjust_address (operands[0], DImode, 0);
3089 /* Implement negtf2 or abstf2. Op0 is destination, op1 is source,
3090 op2 is a register containing the sign bit, operation is the
3091 logical operation to be performed. */
3094 alpha_split_tfmode_frobsign (rtx operands[3], rtx (*operation) (rtx, rtx, rtx))
3096 rtx high_bit = operands[2];
3100 alpha_split_tfmode_pair (operands);
3102 /* Detect three flavors of operand overlap. */
3104 if (rtx_equal_p (operands[0], operands[2]))
3106 else if (rtx_equal_p (operands[1], operands[2]))
3108 if (rtx_equal_p (operands[0], high_bit))
3115 emit_move_insn (operands[0], operands[2]);
3117 /* ??? If the destination overlaps both source tf and high_bit, then
3118 assume source tf is dead in its entirety and use the other half
3119 for a scratch register. Otherwise "scratch" is just the proper
3120 destination register. */
3121 scratch = operands[move < 2 ? 1 : 3];
3123 emit_insn ((*operation) (scratch, high_bit, operands[3]));
3127 emit_move_insn (operands[0], operands[2]);
3129 emit_move_insn (operands[1], scratch);
3133 /* Use ext[wlq][lh] as the Architecture Handbook describes for extracting
3137 word: ldq_u r1,X(r11) ldq_u r1,X(r11)
3138 ldq_u r2,X+1(r11) ldq_u r2,X+1(r11)
3139 lda r3,X(r11) lda r3,X+2(r11)
3140 extwl r1,r3,r1 extql r1,r3,r1
3141 extwh r2,r3,r2 extqh r2,r3,r2
3142 or r1.r2.r1 or r1,r2,r1
3145 long: ldq_u r1,X(r11) ldq_u r1,X(r11)
3146 ldq_u r2,X+3(r11) ldq_u r2,X+3(r11)
3147 lda r3,X(r11) lda r3,X(r11)
3148 extll r1,r3,r1 extll r1,r3,r1
3149 extlh r2,r3,r2 extlh r2,r3,r2
3150 or r1.r2.r1 addl r1,r2,r1
3152 quad: ldq_u r1,X(r11)
3161 alpha_expand_unaligned_load (rtx tgt, rtx mem, HOST_WIDE_INT size,
3162 HOST_WIDE_INT ofs, int sign)
3164 rtx meml, memh, addr, extl, exth, tmp, mema;
3165 enum machine_mode mode;
3167 if (TARGET_BWX && size == 2)
3169 meml = adjust_address (mem, QImode, 0);
3170 memh = adjust_address (mem, QImode, 1);
3171 if (BYTES_BIG_ENDIAN)
3172 tmp = meml, meml = memh, memh = tmp;
3173 extl = gen_reg_rtx (DImode);
3174 exth = gen_reg_rtx (DImode);
3175 emit_insn (gen_zero_extendqidi2 (extl, meml));
3176 emit_insn (gen_zero_extendqidi2 (exth, memh));
3177 exth = expand_simple_binop (DImode, ASHIFT, exth, GEN_INT (8),
3178 NULL, 1, OPTAB_LIB_WIDEN);
3179 addr = expand_simple_binop (DImode, IOR, extl, exth,
3180 NULL, 1, OPTAB_LIB_WIDEN);
3182 if (sign && GET_MODE (tgt) != HImode)
3184 addr = gen_lowpart (HImode, addr);
3185 emit_insn (gen_extend_insn (tgt, addr, GET_MODE (tgt), HImode, 0));
3189 if (GET_MODE (tgt) != DImode)
3190 addr = gen_lowpart (GET_MODE (tgt), addr);
3191 emit_move_insn (tgt, addr);
3196 meml = gen_reg_rtx (DImode);
3197 memh = gen_reg_rtx (DImode);
3198 addr = gen_reg_rtx (DImode);
3199 extl = gen_reg_rtx (DImode);
3200 exth = gen_reg_rtx (DImode);
3202 mema = XEXP (mem, 0);
3203 if (GET_CODE (mema) == LO_SUM)
3204 mema = force_reg (Pmode, mema);
3206 /* AND addresses cannot be in any alias set, since they may implicitly
3207 alias surrounding code. Ideally we'd have some alias set that
3208 covered all types except those with alignment 8 or higher. */
3210 tmp = change_address (mem, DImode,
3211 gen_rtx_AND (DImode,
3212 plus_constant (mema, ofs),
3214 set_mem_alias_set (tmp, 0);
3215 emit_move_insn (meml, tmp);
3217 tmp = change_address (mem, DImode,
3218 gen_rtx_AND (DImode,
3219 plus_constant (mema, ofs + size - 1),
3221 set_mem_alias_set (tmp, 0);
3222 emit_move_insn (memh, tmp);
3224 if (WORDS_BIG_ENDIAN && sign && (size == 2 || size == 4))
3226 emit_move_insn (addr, plus_constant (mema, -1));
3228 emit_insn (gen_extqh_be (extl, meml, addr));
3229 emit_insn (gen_extxl_be (exth, memh, GEN_INT (64), addr));
3231 addr = expand_binop (DImode, ior_optab, extl, exth, tgt, 1, OPTAB_WIDEN);
3232 addr = expand_binop (DImode, ashr_optab, addr, GEN_INT (64 - size*8),
3233 addr, 1, OPTAB_WIDEN);
3235 else if (sign && size == 2)
3237 emit_move_insn (addr, plus_constant (mema, ofs+2));
3239 emit_insn (gen_extxl_le (extl, meml, GEN_INT (64), addr));
3240 emit_insn (gen_extqh_le (exth, memh, addr));
3242 /* We must use tgt here for the target. Alpha-vms port fails if we use
3243 addr for the target, because addr is marked as a pointer and combine
3244 knows that pointers are always sign-extended 32 bit values. */
3245 addr = expand_binop (DImode, ior_optab, extl, exth, tgt, 1, OPTAB_WIDEN);
3246 addr = expand_binop (DImode, ashr_optab, addr, GEN_INT (48),
3247 addr, 1, OPTAB_WIDEN);
3251 if (WORDS_BIG_ENDIAN)
3253 emit_move_insn (addr, plus_constant (mema, ofs+size-1));
3257 emit_insn (gen_extwh_be (extl, meml, addr));
3262 emit_insn (gen_extlh_be (extl, meml, addr));
3267 emit_insn (gen_extqh_be (extl, meml, addr));
3274 emit_insn (gen_extxl_be (exth, memh, GEN_INT (size*8), addr));
3278 emit_move_insn (addr, plus_constant (mema, ofs));
3279 emit_insn (gen_extxl_le (extl, meml, GEN_INT (size*8), addr));
3283 emit_insn (gen_extwh_le (exth, memh, addr));
3288 emit_insn (gen_extlh_le (exth, memh, addr));
3293 emit_insn (gen_extqh_le (exth, memh, addr));
3302 addr = expand_binop (mode, ior_optab, gen_lowpart (mode, extl),
3303 gen_lowpart (mode, exth), gen_lowpart (mode, tgt),
3308 emit_move_insn (tgt, gen_lowpart (GET_MODE (tgt), addr));
3311 /* Similarly, use ins and msk instructions to perform unaligned stores. */
3314 alpha_expand_unaligned_store (rtx dst, rtx src,
3315 HOST_WIDE_INT size, HOST_WIDE_INT ofs)
3317 rtx dstl, dsth, addr, insl, insh, meml, memh, dsta;
3319 if (TARGET_BWX && size == 2)
3321 if (src != const0_rtx)
3323 dstl = gen_lowpart (QImode, src);
3324 dsth = expand_simple_binop (DImode, LSHIFTRT, src, GEN_INT (8),
3325 NULL, 1, OPTAB_LIB_WIDEN);
3326 dsth = gen_lowpart (QImode, dsth);
3329 dstl = dsth = const0_rtx;
3331 meml = adjust_address (dst, QImode, 0);
3332 memh = adjust_address (dst, QImode, 1);
3333 if (BYTES_BIG_ENDIAN)
3334 addr = meml, meml = memh, memh = addr;
3336 emit_move_insn (meml, dstl);
3337 emit_move_insn (memh, dsth);
3341 dstl = gen_reg_rtx (DImode);
3342 dsth = gen_reg_rtx (DImode);
3343 insl = gen_reg_rtx (DImode);
3344 insh = gen_reg_rtx (DImode);
3346 dsta = XEXP (dst, 0);
3347 if (GET_CODE (dsta) == LO_SUM)
3348 dsta = force_reg (Pmode, dsta);
3350 /* AND addresses cannot be in any alias set, since they may implicitly
3351 alias surrounding code. Ideally we'd have some alias set that
3352 covered all types except those with alignment 8 or higher. */
3354 meml = change_address (dst, DImode,
3355 gen_rtx_AND (DImode,
3356 plus_constant (dsta, ofs),
3358 set_mem_alias_set (meml, 0);
3360 memh = change_address (dst, DImode,
3361 gen_rtx_AND (DImode,
3362 plus_constant (dsta, ofs + size - 1),
3364 set_mem_alias_set (memh, 0);
3366 emit_move_insn (dsth, memh);
3367 emit_move_insn (dstl, meml);
3368 if (WORDS_BIG_ENDIAN)
3370 addr = copy_addr_to_reg (plus_constant (dsta, ofs+size-1));
3372 if (src != const0_rtx)
3377 emit_insn (gen_inswl_be (insh, gen_lowpart (HImode,src), addr));
3380 emit_insn (gen_insll_be (insh, gen_lowpart (SImode,src), addr));
3383 emit_insn (gen_insql_be (insh, gen_lowpart (DImode,src), addr));
3386 emit_insn (gen_insxh (insl, gen_lowpart (DImode, src),
3387 GEN_INT (size*8), addr));
3393 emit_insn (gen_mskxl_be (dsth, dsth, GEN_INT (0xffff), addr));
3397 rtx msk = immed_double_const (0xffffffff, 0, DImode);
3398 emit_insn (gen_mskxl_be (dsth, dsth, msk, addr));
3402 emit_insn (gen_mskxl_be (dsth, dsth, constm1_rtx, addr));
3406 emit_insn (gen_mskxh (dstl, dstl, GEN_INT (size*8), addr));
3410 addr = copy_addr_to_reg (plus_constant (dsta, ofs));
3412 if (src != CONST0_RTX (GET_MODE (src)))
3414 emit_insn (gen_insxh (insh, gen_lowpart (DImode, src),
3415 GEN_INT (size*8), addr));
3420 emit_insn (gen_inswl_le (insl, gen_lowpart (HImode, src), addr));
3423 emit_insn (gen_insll_le (insl, gen_lowpart (SImode, src), addr));
3426 emit_insn (gen_insql_le (insl, src, addr));
3431 emit_insn (gen_mskxh (dsth, dsth, GEN_INT (size*8), addr));
3436 emit_insn (gen_mskxl_le (dstl, dstl, GEN_INT (0xffff), addr));
3440 rtx msk = immed_double_const (0xffffffff, 0, DImode);
3441 emit_insn (gen_mskxl_le (dstl, dstl, msk, addr));
3445 emit_insn (gen_mskxl_le (dstl, dstl, constm1_rtx, addr));
3450 if (src != CONST0_RTX (GET_MODE (src)))
3452 dsth = expand_binop (DImode, ior_optab, insh, dsth, dsth, 0, OPTAB_WIDEN);
3453 dstl = expand_binop (DImode, ior_optab, insl, dstl, dstl, 0, OPTAB_WIDEN);
3456 if (WORDS_BIG_ENDIAN)
3458 emit_move_insn (meml, dstl);
3459 emit_move_insn (memh, dsth);
3463 /* Must store high before low for degenerate case of aligned. */
3464 emit_move_insn (memh, dsth);
3465 emit_move_insn (meml, dstl);
3469 /* The block move code tries to maximize speed by separating loads and
3470 stores at the expense of register pressure: we load all of the data
3471 before we store it back out. There are two secondary effects worth
3472 mentioning, that this speeds copying to/from aligned and unaligned
3473 buffers, and that it makes the code significantly easier to write. */
3475 #define MAX_MOVE_WORDS 8
3477 /* Load an integral number of consecutive unaligned quadwords. */
3480 alpha_expand_unaligned_load_words (rtx *out_regs, rtx smem,
3481 HOST_WIDE_INT words, HOST_WIDE_INT ofs)
3483 rtx const im8 = GEN_INT (-8);
3484 rtx const i64 = GEN_INT (64);
3485 rtx ext_tmps[MAX_MOVE_WORDS], data_regs[MAX_MOVE_WORDS+1];
3486 rtx sreg, areg, tmp, smema;
3489 smema = XEXP (smem, 0);
3490 if (GET_CODE (smema) == LO_SUM)
3491 smema = force_reg (Pmode, smema);
3493 /* Generate all the tmp registers we need. */
3494 for (i = 0; i < words; ++i)
3496 data_regs[i] = out_regs[i];
3497 ext_tmps[i] = gen_reg_rtx (DImode);
3499 data_regs[words] = gen_reg_rtx (DImode);
3502 smem = adjust_address (smem, GET_MODE (smem), ofs);
3504 /* Load up all of the source data. */
3505 for (i = 0; i < words; ++i)
3507 tmp = change_address (smem, DImode,
3508 gen_rtx_AND (DImode,
3509 plus_constant (smema, 8*i),
3511 set_mem_alias_set (tmp, 0);
3512 emit_move_insn (data_regs[i], tmp);
3515 tmp = change_address (smem, DImode,
3516 gen_rtx_AND (DImode,
3517 plus_constant (smema, 8*words - 1),
3519 set_mem_alias_set (tmp, 0);
3520 emit_move_insn (data_regs[words], tmp);
3522 /* Extract the half-word fragments. Unfortunately DEC decided to make
3523 extxh with offset zero a noop instead of zeroing the register, so
3524 we must take care of that edge condition ourselves with cmov. */
3526 sreg = copy_addr_to_reg (smema);
3527 areg = expand_binop (DImode, and_optab, sreg, GEN_INT (7), NULL,
3529 if (WORDS_BIG_ENDIAN)
3530 emit_move_insn (sreg, plus_constant (sreg, 7));
3531 for (i = 0; i < words; ++i)
3533 if (WORDS_BIG_ENDIAN)
3535 emit_insn (gen_extqh_be (data_regs[i], data_regs[i], sreg));
3536 emit_insn (gen_extxl_be (ext_tmps[i], data_regs[i+1], i64, sreg));
3540 emit_insn (gen_extxl_le (data_regs[i], data_regs[i], i64, sreg));
3541 emit_insn (gen_extqh_le (ext_tmps[i], data_regs[i+1], sreg));
3543 emit_insn (gen_rtx_SET (VOIDmode, ext_tmps[i],
3544 gen_rtx_IF_THEN_ELSE (DImode,
3545 gen_rtx_EQ (DImode, areg,
3547 const0_rtx, ext_tmps[i])));
3550 /* Merge the half-words into whole words. */
3551 for (i = 0; i < words; ++i)
3553 out_regs[i] = expand_binop (DImode, ior_optab, data_regs[i],
3554 ext_tmps[i], data_regs[i], 1, OPTAB_WIDEN);
3558 /* Store an integral number of consecutive unaligned quadwords. DATA_REGS
3559 may be NULL to store zeros. */
3562 alpha_expand_unaligned_store_words (rtx *data_regs, rtx dmem,
3563 HOST_WIDE_INT words, HOST_WIDE_INT ofs)
3565 rtx const im8 = GEN_INT (-8);
3566 rtx const i64 = GEN_INT (64);
3567 rtx ins_tmps[MAX_MOVE_WORDS];
3568 rtx st_tmp_1, st_tmp_2, dreg;
3569 rtx st_addr_1, st_addr_2, dmema;
3572 dmema = XEXP (dmem, 0);
3573 if (GET_CODE (dmema) == LO_SUM)
3574 dmema = force_reg (Pmode, dmema);
3576 /* Generate all the tmp registers we need. */
3577 if (data_regs != NULL)
3578 for (i = 0; i < words; ++i)
3579 ins_tmps[i] = gen_reg_rtx(DImode);
3580 st_tmp_1 = gen_reg_rtx(DImode);
3581 st_tmp_2 = gen_reg_rtx(DImode);
3584 dmem = adjust_address (dmem, GET_MODE (dmem), ofs);
3586 st_addr_2 = change_address (dmem, DImode,
3587 gen_rtx_AND (DImode,
3588 plus_constant (dmema, words*8 - 1),
3590 set_mem_alias_set (st_addr_2, 0);
3592 st_addr_1 = change_address (dmem, DImode,
3593 gen_rtx_AND (DImode, dmema, im8));
3594 set_mem_alias_set (st_addr_1, 0);
3596 /* Load up the destination end bits. */
3597 emit_move_insn (st_tmp_2, st_addr_2);
3598 emit_move_insn (st_tmp_1, st_addr_1);
3600 /* Shift the input data into place. */
3601 dreg = copy_addr_to_reg (dmema);
3602 if (WORDS_BIG_ENDIAN)
3603 emit_move_insn (dreg, plus_constant (dreg, 7));
3604 if (data_regs != NULL)
3606 for (i = words-1; i >= 0; --i)
3608 if (WORDS_BIG_ENDIAN)
3610 emit_insn (gen_insql_be (ins_tmps[i], data_regs[i], dreg));
3611 emit_insn (gen_insxh (data_regs[i], data_regs[i], i64, dreg));
3615 emit_insn (gen_insxh (ins_tmps[i], data_regs[i], i64, dreg));
3616 emit_insn (gen_insql_le (data_regs[i], data_regs[i], dreg));
3619 for (i = words-1; i > 0; --i)
3621 ins_tmps[i-1] = expand_binop (DImode, ior_optab, data_regs[i],
3622 ins_tmps[i-1], ins_tmps[i-1], 1,
3627 /* Split and merge the ends with the destination data. */
3628 if (WORDS_BIG_ENDIAN)
3630 emit_insn (gen_mskxl_be (st_tmp_2, st_tmp_2, constm1_rtx, dreg));
3631 emit_insn (gen_mskxh (st_tmp_1, st_tmp_1, i64, dreg));
3635 emit_insn (gen_mskxh (st_tmp_2, st_tmp_2, i64, dreg));
3636 emit_insn (gen_mskxl_le (st_tmp_1, st_tmp_1, constm1_rtx, dreg));
3639 if (data_regs != NULL)
3641 st_tmp_2 = expand_binop (DImode, ior_optab, st_tmp_2, ins_tmps[words-1],
3642 st_tmp_2, 1, OPTAB_WIDEN);
3643 st_tmp_1 = expand_binop (DImode, ior_optab, st_tmp_1, data_regs[0],
3644 st_tmp_1, 1, OPTAB_WIDEN);
3648 if (WORDS_BIG_ENDIAN)
3649 emit_move_insn (st_addr_1, st_tmp_1);
3651 emit_move_insn (st_addr_2, st_tmp_2);
3652 for (i = words-1; i > 0; --i)
3654 rtx tmp = change_address (dmem, DImode,
3655 gen_rtx_AND (DImode,
3656 plus_constant(dmema,
3657 WORDS_BIG_ENDIAN ? i*8-1 : i*8),
3659 set_mem_alias_set (tmp, 0);
3660 emit_move_insn (tmp, data_regs ? ins_tmps[i-1] : const0_rtx);
3662 if (WORDS_BIG_ENDIAN)
3663 emit_move_insn (st_addr_2, st_tmp_2);
3665 emit_move_insn (st_addr_1, st_tmp_1);
3669 /* Expand string/block move operations.
3671 operands[0] is the pointer to the destination.
3672 operands[1] is the pointer to the source.
3673 operands[2] is the number of bytes to move.
3674 operands[3] is the alignment. */
3677 alpha_expand_block_move (rtx operands[])
3679 rtx bytes_rtx = operands[2];
3680 rtx align_rtx = operands[3];
3681 HOST_WIDE_INT orig_bytes = INTVAL (bytes_rtx);
3682 HOST_WIDE_INT bytes = orig_bytes;
3683 HOST_WIDE_INT src_align = INTVAL (align_rtx) * BITS_PER_UNIT;
3684 HOST_WIDE_INT dst_align = src_align;
3685 rtx orig_src = operands[1];
3686 rtx orig_dst = operands[0];
3687 rtx data_regs[2 * MAX_MOVE_WORDS + 16];
3689 unsigned int i, words, ofs, nregs = 0;
3691 if (orig_bytes <= 0)
3693 else if (orig_bytes > MAX_MOVE_WORDS * UNITS_PER_WORD)
3696 /* Look for additional alignment information from recorded register info. */
3698 tmp = XEXP (orig_src, 0);
3699 if (GET_CODE (tmp) == REG)
3700 src_align = MAX (src_align, REGNO_POINTER_ALIGN (REGNO (tmp)));
3701 else if (GET_CODE (tmp) == PLUS
3702 && GET_CODE (XEXP (tmp, 0)) == REG
3703 && GET_CODE (XEXP (tmp, 1)) == CONST_INT)
3705 unsigned HOST_WIDE_INT c = INTVAL (XEXP (tmp, 1));
3706 unsigned int a = REGNO_POINTER_ALIGN (REGNO (XEXP (tmp, 0)));
3710 if (a >= 64 && c % 8 == 0)
3712 else if (a >= 32 && c % 4 == 0)
3714 else if (a >= 16 && c % 2 == 0)
3719 tmp = XEXP (orig_dst, 0);
3720 if (GET_CODE (tmp) == REG)
3721 dst_align = MAX (dst_align, REGNO_POINTER_ALIGN (REGNO (tmp)));
3722 else if (GET_CODE (tmp) == PLUS
3723 && GET_CODE (XEXP (tmp, 0)) == REG
3724 && GET_CODE (XEXP (tmp, 1)) == CONST_INT)
3726 unsigned HOST_WIDE_INT c = INTVAL (XEXP (tmp, 1));
3727 unsigned int a = REGNO_POINTER_ALIGN (REGNO (XEXP (tmp, 0)));
3731 if (a >= 64 && c % 8 == 0)
3733 else if (a >= 32 && c % 4 == 0)
3735 else if (a >= 16 && c % 2 == 0)
3741 if (src_align >= 64 && bytes >= 8)
3745 for (i = 0; i < words; ++i)
3746 data_regs[nregs + i] = gen_reg_rtx (DImode);
3748 for (i = 0; i < words; ++i)
3749 emit_move_insn (data_regs[nregs + i],
3750 adjust_address (orig_src, DImode, ofs + i * 8));
3757 if (src_align >= 32 && bytes >= 4)
3761 for (i = 0; i < words; ++i)
3762 data_regs[nregs + i] = gen_reg_rtx (SImode);
3764 for (i = 0; i < words; ++i)
3765 emit_move_insn (data_regs[nregs + i],
3766 adjust_address (orig_src, SImode, ofs + i * 4));
3777 for (i = 0; i < words+1; ++i)
3778 data_regs[nregs + i] = gen_reg_rtx (DImode);
3780 alpha_expand_unaligned_load_words (data_regs + nregs, orig_src,
3788 if (! TARGET_BWX && bytes >= 4)
3790 data_regs[nregs++] = tmp = gen_reg_rtx (SImode);
3791 alpha_expand_unaligned_load (tmp, orig_src, 4, ofs, 0);
3798 if (src_align >= 16)
3801 data_regs[nregs++] = tmp = gen_reg_rtx (HImode);
3802 emit_move_insn (tmp, adjust_address (orig_src, HImode, ofs));
3805 } while (bytes >= 2);
3807 else if (! TARGET_BWX)
3809 data_regs[nregs++] = tmp = gen_reg_rtx (HImode);
3810 alpha_expand_unaligned_load (tmp, orig_src, 2, ofs, 0);
3818 data_regs[nregs++] = tmp = gen_reg_rtx (QImode);
3819 emit_move_insn (tmp, adjust_address (orig_src, QImode, ofs));
3824 if (nregs > ARRAY_SIZE (data_regs))
3827 /* Now save it back out again. */
3831 /* Write out the data in whatever chunks reading the source allowed. */
3832 if (dst_align >= 64)
3834 while (i < nregs && GET_MODE (data_regs[i]) == DImode)
3836 emit_move_insn (adjust_address (orig_dst, DImode, ofs),
3843 if (dst_align >= 32)
3845 /* If the source has remaining DImode regs, write them out in
3847 while (i < nregs && GET_MODE (data_regs[i]) == DImode)
3849 tmp = expand_binop (DImode, lshr_optab, data_regs[i], GEN_INT (32),
3850 NULL_RTX, 1, OPTAB_WIDEN);
3852 emit_move_insn (adjust_address (orig_dst, SImode, ofs),
3853 gen_lowpart (SImode, data_regs[i]));
3854 emit_move_insn (adjust_address (orig_dst, SImode, ofs + 4),
3855 gen_lowpart (SImode, tmp));
3860 while (i < nregs && GET_MODE (data_regs[i]) == SImode)
3862 emit_move_insn (adjust_address (orig_dst, SImode, ofs),
3869 if (i < nregs && GET_MODE (data_regs[i]) == DImode)
3871 /* Write out a remaining block of words using unaligned methods. */
3873 for (words = 1; i + words < nregs; words++)
3874 if (GET_MODE (data_regs[i + words]) != DImode)
3878 alpha_expand_unaligned_store (orig_dst, data_regs[i], 8, ofs);
3880 alpha_expand_unaligned_store_words (data_regs + i, orig_dst,
3887 /* Due to the above, this won't be aligned. */
3888 /* ??? If we have more than one of these, consider constructing full
3889 words in registers and using alpha_expand_unaligned_store_words. */
3890 while (i < nregs && GET_MODE (data_regs[i]) == SImode)
3892 alpha_expand_unaligned_store (orig_dst, data_regs[i], 4, ofs);
3897 if (dst_align >= 16)
3898 while (i < nregs && GET_MODE (data_regs[i]) == HImode)
3900 emit_move_insn (adjust_address (orig_dst, HImode, ofs), data_regs[i]);
3905 while (i < nregs && GET_MODE (data_regs[i]) == HImode)
3907 alpha_expand_unaligned_store (orig_dst, data_regs[i], 2, ofs);
3912 while (i < nregs && GET_MODE (data_regs[i]) == QImode)
3914 emit_move_insn (adjust_address (orig_dst, QImode, ofs), data_regs[i]);
3926 alpha_expand_block_clear (rtx operands[])
3928 rtx bytes_rtx = operands[1];
3929 rtx align_rtx = operands[2];
3930 HOST_WIDE_INT orig_bytes = INTVAL (bytes_rtx);
3931 HOST_WIDE_INT bytes = orig_bytes;
3932 HOST_WIDE_INT align = INTVAL (align_rtx) * BITS_PER_UNIT;
3933 HOST_WIDE_INT alignofs = 0;
3934 rtx orig_dst = operands[0];
3936 int i, words, ofs = 0;
3938 if (orig_bytes <= 0)
3940 if (orig_bytes > MAX_MOVE_WORDS * UNITS_PER_WORD)
3943 /* Look for stricter alignment. */
3944 tmp = XEXP (orig_dst, 0);
3945 if (GET_CODE (tmp) == REG)
3946 align = MAX (align, REGNO_POINTER_ALIGN (REGNO (tmp)));
3947 else if (GET_CODE (tmp) == PLUS
3948 && GET_CODE (XEXP (tmp, 0)) == REG
3949 && GET_CODE (XEXP (tmp, 1)) == CONST_INT)
3951 HOST_WIDE_INT c = INTVAL (XEXP (tmp, 1));
3952 int a = REGNO_POINTER_ALIGN (REGNO (XEXP (tmp, 0)));
3957 align = a, alignofs = 8 - c % 8;
3959 align = a, alignofs = 4 - c % 4;
3961 align = a, alignofs = 2 - c % 2;
3965 /* Handle an unaligned prefix first. */
3969 #if HOST_BITS_PER_WIDE_INT >= 64
3970 /* Given that alignofs is bounded by align, the only time BWX could
3971 generate three stores is for a 7 byte fill. Prefer two individual
3972 stores over a load/mask/store sequence. */
3973 if ((!TARGET_BWX || alignofs == 7)
3975 && !(alignofs == 4 && bytes >= 4))
3977 enum machine_mode mode = (align >= 64 ? DImode : SImode);
3978 int inv_alignofs = (align >= 64 ? 8 : 4) - alignofs;
3982 mem = adjust_address (orig_dst, mode, ofs - inv_alignofs);
3983 set_mem_alias_set (mem, 0);
3985 mask = ~(~(HOST_WIDE_INT)0 << (inv_alignofs * 8));
3986 if (bytes < alignofs)
3988 mask |= ~(HOST_WIDE_INT)0 << ((inv_alignofs + bytes) * 8);
3999 tmp = expand_binop (mode, and_optab, mem, GEN_INT (mask),
4000 NULL_RTX, 1, OPTAB_WIDEN);
4002 emit_move_insn (mem, tmp);
4006 if (TARGET_BWX && (alignofs & 1) && bytes >= 1)
4008 emit_move_insn (adjust_address (orig_dst, QImode, ofs), const0_rtx);
4013 if (TARGET_BWX && align >= 16 && (alignofs & 3) == 2 && bytes >= 2)
4015 emit_move_insn (adjust_address (orig_dst, HImode, ofs), const0_rtx);
4020 if (alignofs == 4 && bytes >= 4)
4022 emit_move_insn (adjust_address (orig_dst, SImode, ofs), const0_rtx);
4028 /* If we've not used the extra lead alignment information by now,
4029 we won't be able to. Downgrade align to match what's left over. */
4032 alignofs = alignofs & -alignofs;
4033 align = MIN (align, alignofs * BITS_PER_UNIT);
4037 /* Handle a block of contiguous long-words. */
4039 if (align >= 64 && bytes >= 8)
4043 for (i = 0; i < words; ++i)
4044 emit_move_insn (adjust_address (orig_dst, DImode, ofs + i * 8),
4051 /* If the block is large and appropriately aligned, emit a single
4052 store followed by a sequence of stq_u insns. */
4054 if (align >= 32 && bytes > 16)
4058 emit_move_insn (adjust_address (orig_dst, SImode, ofs), const0_rtx);
4062 orig_dsta = XEXP (orig_dst, 0);
4063 if (GET_CODE (orig_dsta) == LO_SUM)
4064 orig_dsta = force_reg (Pmode, orig_dsta);
4067 for (i = 0; i < words; ++i)
4070 = change_address (orig_dst, DImode,
4071 gen_rtx_AND (DImode,
4072 plus_constant (orig_dsta, ofs + i*8),
4074 set_mem_alias_set (mem, 0);
4075 emit_move_insn (mem, const0_rtx);
4078 /* Depending on the alignment, the first stq_u may have overlapped
4079 with the initial stl, which means that the last stq_u didn't
4080 write as much as it would appear. Leave those questionable bytes
4082 bytes -= words * 8 - 4;
4083 ofs += words * 8 - 4;
4086 /* Handle a smaller block of aligned words. */
4088 if ((align >= 64 && bytes == 4)
4089 || (align == 32 && bytes >= 4))
4093 for (i = 0; i < words; ++i)
4094 emit_move_insn (adjust_address (orig_dst, SImode, ofs + i * 4),
4101 /* An unaligned block uses stq_u stores for as many as possible. */
4107 alpha_expand_unaligned_store_words (NULL, orig_dst, words, ofs);
4113 /* Next clean up any trailing pieces. */
4115 #if HOST_BITS_PER_WIDE_INT >= 64
4116 /* Count the number of bits in BYTES for which aligned stores could
4119 for (i = (TARGET_BWX ? 1 : 4); i * BITS_PER_UNIT <= align ; i <<= 1)
4123 /* If we have appropriate alignment (and it wouldn't take too many
4124 instructions otherwise), mask out the bytes we need. */
4125 if (TARGET_BWX ? words > 2 : bytes > 0)
4132 mem = adjust_address (orig_dst, DImode, ofs);
4133 set_mem_alias_set (mem, 0);
4135 mask = ~(HOST_WIDE_INT)0 << (bytes * 8);
4137 tmp = expand_binop (DImode, and_optab, mem, GEN_INT (mask),
4138 NULL_RTX, 1, OPTAB_WIDEN);
4140 emit_move_insn (mem, tmp);
4143 else if (align >= 32 && bytes < 4)
4148 mem = adjust_address (orig_dst, SImode, ofs);
4149 set_mem_alias_set (mem, 0);
4151 mask = ~(HOST_WIDE_INT)0 << (bytes * 8);
4153 tmp = expand_binop (SImode, and_optab, mem, GEN_INT (mask),
4154 NULL_RTX, 1, OPTAB_WIDEN);
4156 emit_move_insn (mem, tmp);
4162 if (!TARGET_BWX && bytes >= 4)
4164 alpha_expand_unaligned_store (orig_dst, const0_rtx, 4, ofs);
4174 emit_move_insn (adjust_address (orig_dst, HImode, ofs),
4178 } while (bytes >= 2);
4180 else if (! TARGET_BWX)
4182 alpha_expand_unaligned_store (orig_dst, const0_rtx, 2, ofs);
4190 emit_move_insn (adjust_address (orig_dst, QImode, ofs), const0_rtx);
4198 /* Returns a mask so that zap(x, value) == x & mask. */
4201 alpha_expand_zap_mask (HOST_WIDE_INT value)
4206 if (HOST_BITS_PER_WIDE_INT >= 64)
4208 HOST_WIDE_INT mask = 0;
4210 for (i = 7; i >= 0; --i)
4213 if (!((value >> i) & 1))
4217 result = gen_int_mode (mask, DImode);
4219 else if (HOST_BITS_PER_WIDE_INT == 32)
4221 HOST_WIDE_INT mask_lo = 0, mask_hi = 0;
4223 for (i = 7; i >= 4; --i)
4226 if (!((value >> i) & 1))
4230 for (i = 3; i >= 0; --i)
4233 if (!((value >> i) & 1))
4237 result = immed_double_const (mask_lo, mask_hi, DImode);
4246 alpha_expand_builtin_vector_binop (rtx (*gen) (rtx, rtx, rtx),
4247 enum machine_mode mode,
4248 rtx op0, rtx op1, rtx op2)
4250 op0 = gen_lowpart (mode, op0);
4252 if (op1 == const0_rtx)
4253 op1 = CONST0_RTX (mode);
4255 op1 = gen_lowpart (mode, op1);
4257 if (op2 == const0_rtx)
4258 op2 = CONST0_RTX (mode);
4260 op2 = gen_lowpart (mode, op2);
4262 emit_insn ((*gen) (op0, op1, op2));
4265 /* Adjust the cost of a scheduling dependency. Return the new cost of
4266 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */
4269 alpha_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost)
4271 enum attr_type insn_type, dep_insn_type;
4273 /* If the dependence is an anti-dependence, there is no cost. For an
4274 output dependence, there is sometimes a cost, but it doesn't seem
4275 worth handling those few cases. */
4276 if (REG_NOTE_KIND (link) != 0)
4279 /* If we can't recognize the insns, we can't really do anything. */
4280 if (recog_memoized (insn) < 0 || recog_memoized (dep_insn) < 0)
4283 insn_type = get_attr_type (insn);
4284 dep_insn_type = get_attr_type (dep_insn);
4286 /* Bring in the user-defined memory latency. */
4287 if (dep_insn_type == TYPE_ILD
4288 || dep_insn_type == TYPE_FLD
4289 || dep_insn_type == TYPE_LDSYM)
4290 cost += alpha_memory_latency-1;
4292 /* Everything else handled in DFA bypasses now. */
4297 /* The number of instructions that can be issued per cycle. */
4300 alpha_issue_rate (void)
4302 return (alpha_cpu == PROCESSOR_EV4 ? 2 : 4);
4305 /* How many alternative schedules to try. This should be as wide as the
4306 scheduling freedom in the DFA, but no wider. Making this value too
4307 large results extra work for the scheduler.
4309 For EV4, loads can be issued to either IB0 or IB1, thus we have 2
4310 alternative schedules. For EV5, we can choose between E0/E1 and
4311 FA/FM. For EV6, an arithmetic insn can be issued to U0/U1/L0/L1. */
4314 alpha_multipass_dfa_lookahead (void)
4316 return (alpha_cpu == PROCESSOR_EV6 ? 4 : 2);
4319 /* Machine-specific function data. */
4321 struct machine_function GTY(())
4324 /* List of call information words for calls from this function. */
4325 struct rtx_def *first_ciw;
4326 struct rtx_def *last_ciw;
4329 /* List of deferred case vectors. */
4330 struct rtx_def *addr_list;
4333 const char *some_ld_name;
4335 /* For TARGET_LD_BUGGY_LDGP. */
4336 struct rtx_def *gp_save_rtx;
4339 /* How to allocate a 'struct machine_function'. */
4341 static struct machine_function *
4342 alpha_init_machine_status (void)
4344 return ((struct machine_function *)
4345 ggc_alloc_cleared (sizeof (struct machine_function)));
4348 /* Functions to save and restore alpha_return_addr_rtx. */
4350 /* Start the ball rolling with RETURN_ADDR_RTX. */
4353 alpha_return_addr (int count, rtx frame ATTRIBUTE_UNUSED)
4358 return get_hard_reg_initial_val (Pmode, REG_RA);
4361 /* Return or create a memory slot containing the gp value for the current
4362 function. Needed only if TARGET_LD_BUGGY_LDGP. */
4365 alpha_gp_save_rtx (void)
4367 rtx seq, m = cfun->machine->gp_save_rtx;
4373 m = assign_stack_local (DImode, UNITS_PER_WORD, BITS_PER_WORD);
4374 m = validize_mem (m);
4375 emit_move_insn (m, pic_offset_table_rtx);
4379 emit_insn_after (seq, entry_of_function ());
4381 cfun->machine->gp_save_rtx = m;
4388 alpha_ra_ever_killed (void)
4392 if (!has_hard_reg_initial_val (Pmode, REG_RA))
4393 return regs_ever_live[REG_RA];
4395 push_topmost_sequence ();
4397 pop_topmost_sequence ();
4399 return reg_set_between_p (gen_rtx_REG (Pmode, REG_RA), top, NULL_RTX);
4403 /* Return the trap mode suffix applicable to the current
4404 instruction, or NULL. */
4407 get_trap_mode_suffix (void)
4409 enum attr_trap_suffix s = get_attr_trap_suffix (current_output_insn);
4413 case TRAP_SUFFIX_NONE:
4416 case TRAP_SUFFIX_SU:
4417 if (alpha_fptm >= ALPHA_FPTM_SU)
4421 case TRAP_SUFFIX_SUI:
4422 if (alpha_fptm >= ALPHA_FPTM_SUI)
4426 case TRAP_SUFFIX_V_SV:
4434 case ALPHA_FPTM_SUI:
4439 case TRAP_SUFFIX_V_SV_SVI:
4448 case ALPHA_FPTM_SUI:
4453 case TRAP_SUFFIX_U_SU_SUI:
4462 case ALPHA_FPTM_SUI:
4470 /* Return the rounding mode suffix applicable to the current
4471 instruction, or NULL. */
4474 get_round_mode_suffix (void)
4476 enum attr_round_suffix s = get_attr_round_suffix (current_output_insn);
4480 case ROUND_SUFFIX_NONE:
4482 case ROUND_SUFFIX_NORMAL:
4485 case ALPHA_FPRM_NORM:
4487 case ALPHA_FPRM_MINF:
4489 case ALPHA_FPRM_CHOP:
4491 case ALPHA_FPRM_DYN:
4496 case ROUND_SUFFIX_C:
4502 /* Locate some local-dynamic symbol still in use by this function
4503 so that we can print its name in some movdi_er_tlsldm pattern. */
4506 get_some_local_dynamic_name_1 (rtx *px, void *data ATTRIBUTE_UNUSED)
4510 if (GET_CODE (x) == SYMBOL_REF
4511 && SYMBOL_REF_TLS_MODEL (x) == TLS_MODEL_LOCAL_DYNAMIC)
4513 cfun->machine->some_ld_name = XSTR (x, 0);
4521 get_some_local_dynamic_name (void)
4525 if (cfun->machine->some_ld_name)
4526 return cfun->machine->some_ld_name;
4528 for (insn = get_insns (); insn ; insn = NEXT_INSN (insn))
4530 && for_each_rtx (&PATTERN (insn), get_some_local_dynamic_name_1, 0))
4531 return cfun->machine->some_ld_name;
4536 /* Print an operand. Recognize special options, documented below. */
4539 print_operand (FILE *file, rtx x, int code)
4546 /* Print the assembler name of the current function. */
4547 assemble_name (file, alpha_fnname);
4551 assemble_name (file, get_some_local_dynamic_name ());
4556 const char *trap = get_trap_mode_suffix ();
4557 const char *round = get_round_mode_suffix ();
4560 fprintf (file, (TARGET_AS_SLASH_BEFORE_SUFFIX ? "/%s%s" : "%s%s"),
4561 (trap ? trap : ""), (round ? round : ""));
4566 /* Generates single precision instruction suffix. */
4567 fputc ((TARGET_FLOAT_VAX ? 'f' : 's'), file);
4571 /* Generates double precision instruction suffix. */
4572 fputc ((TARGET_FLOAT_VAX ? 'g' : 't'), file);
4576 /* Generates a nop after a noreturn call at the very end of the
4578 if (next_real_insn (current_output_insn) == 0)
4579 fprintf (file, "\n\tnop");
4583 if (alpha_this_literal_sequence_number == 0)
4584 alpha_this_literal_sequence_number = alpha_next_sequence_number++;
4585 fprintf (file, "%d", alpha_this_literal_sequence_number);
4589 if (alpha_this_gpdisp_sequence_number == 0)
4590 alpha_this_gpdisp_sequence_number = alpha_next_sequence_number++;
4591 fprintf (file, "%d", alpha_this_gpdisp_sequence_number);
4595 if (GET_CODE (x) == HIGH)
4596 output_addr_const (file, XEXP (x, 0));
4598 output_operand_lossage ("invalid %%H value");
4605 if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_TLSGD_CALL)
4607 x = XVECEXP (x, 0, 0);
4608 lituse = "lituse_tlsgd";
4610 else if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_TLSLDM_CALL)
4612 x = XVECEXP (x, 0, 0);
4613 lituse = "lituse_tlsldm";
4615 else if (GET_CODE (x) == CONST_INT)
4616 lituse = "lituse_jsr";
4619 output_operand_lossage ("invalid %%J value");
4623 if (x != const0_rtx)
4624 fprintf (file, "\t\t!%s!%d", lituse, (int) INTVAL (x));
4629 /* If this operand is the constant zero, write it as "$31". */
4630 if (GET_CODE (x) == REG)
4631 fprintf (file, "%s", reg_names[REGNO (x)]);
4632 else if (x == CONST0_RTX (GET_MODE (x)))
4633 fprintf (file, "$31");
4635 output_operand_lossage ("invalid %%r value");
4639 /* Similar, but for floating-point. */
4640 if (GET_CODE (x) == REG)
4641 fprintf (file, "%s", reg_names[REGNO (x)]);
4642 else if (x == CONST0_RTX (GET_MODE (x)))
4643 fprintf (file, "$f31");
4645 output_operand_lossage ("invalid %%R value");
4649 /* Write the 1's complement of a constant. */
4650 if (GET_CODE (x) != CONST_INT)
4651 output_operand_lossage ("invalid %%N value");
4653 fprintf (file, HOST_WIDE_INT_PRINT_DEC, ~ INTVAL (x));
4657 /* Write 1 << C, for a constant C. */
4658 if (GET_CODE (x) != CONST_INT)
4659 output_operand_lossage ("invalid %%P value");
4661 fprintf (file, HOST_WIDE_INT_PRINT_DEC, (HOST_WIDE_INT) 1 << INTVAL (x));
4665 /* Write the high-order 16 bits of a constant, sign-extended. */
4666 if (GET_CODE (x) != CONST_INT)
4667 output_operand_lossage ("invalid %%h value");
4669 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x) >> 16);
4673 /* Write the low-order 16 bits of a constant, sign-extended. */
4674 if (GET_CODE (x) != CONST_INT)
4675 output_operand_lossage ("invalid %%L value");
4677 fprintf (file, HOST_WIDE_INT_PRINT_DEC,
4678 (INTVAL (x) & 0xffff) - 2 * (INTVAL (x) & 0x8000));
4682 /* Write mask for ZAP insn. */
4683 if (GET_CODE (x) == CONST_DOUBLE)
4685 HOST_WIDE_INT mask = 0;
4686 HOST_WIDE_INT value;
4688 value = CONST_DOUBLE_LOW (x);
4689 for (i = 0; i < HOST_BITS_PER_WIDE_INT / HOST_BITS_PER_CHAR;
4694 value = CONST_DOUBLE_HIGH (x);
4695 for (i = 0; i < HOST_BITS_PER_WIDE_INT / HOST_BITS_PER_CHAR;
4698 mask |= (1 << (i + sizeof (int)));
4700 fprintf (file, HOST_WIDE_INT_PRINT_DEC, mask & 0xff);
4703 else if (GET_CODE (x) == CONST_INT)
4705 HOST_WIDE_INT mask = 0, value = INTVAL (x);
4707 for (i = 0; i < 8; i++, value >>= 8)
4711 fprintf (file, HOST_WIDE_INT_PRINT_DEC, mask);
4714 output_operand_lossage ("invalid %%m value");
4718 /* 'b', 'w', 'l', or 'q' as the value of the constant. */
4719 if (GET_CODE (x) != CONST_INT
4720 || (INTVAL (x) != 8 && INTVAL (x) != 16
4721 && INTVAL (x) != 32 && INTVAL (x) != 64))
4722 output_operand_lossage ("invalid %%M value");
4724 fprintf (file, "%s",
4725 (INTVAL (x) == 8 ? "b"
4726 : INTVAL (x) == 16 ? "w"
4727 : INTVAL (x) == 32 ? "l"
4732 /* Similar, except do it from the mask. */
4733 if (GET_CODE (x) == CONST_INT)
4735 HOST_WIDE_INT value = INTVAL (x);
4742 if (value == 0xffff)
4747 if (value == 0xffffffff)
4758 else if (HOST_BITS_PER_WIDE_INT == 32
4759 && GET_CODE (x) == CONST_DOUBLE
4760 && CONST_DOUBLE_LOW (x) == 0xffffffff
4761 && CONST_DOUBLE_HIGH (x) == 0)
4766 output_operand_lossage ("invalid %%U value");
4770 /* Write the constant value divided by 8 for little-endian mode or
4771 (56 - value) / 8 for big-endian mode. */
4773 if (GET_CODE (x) != CONST_INT
4774 || (unsigned HOST_WIDE_INT) INTVAL (x) >= (WORDS_BIG_ENDIAN
4777 || (INTVAL (x) & 7) != 0)
4778 output_operand_lossage ("invalid %%s value");
4780 fprintf (file, HOST_WIDE_INT_PRINT_DEC,
4782 ? (56 - INTVAL (x)) / 8
4787 /* Same, except compute (64 - c) / 8 */
4789 if (GET_CODE (x) != CONST_INT
4790 && (unsigned HOST_WIDE_INT) INTVAL (x) >= 64
4791 && (INTVAL (x) & 7) != 8)
4792 output_operand_lossage ("invalid %%s value");
4794 fprintf (file, HOST_WIDE_INT_PRINT_DEC, (64 - INTVAL (x)) / 8);
4799 /* On Unicos/Mk systems: use a DEX expression if the symbol
4800 clashes with a register name. */
4801 int dex = unicosmk_need_dex (x);
4803 fprintf (file, "DEX(%d)", dex);
4805 output_addr_const (file, x);
4809 case 'C': case 'D': case 'c': case 'd':
4810 /* Write out comparison name. */
4812 enum rtx_code c = GET_CODE (x);
4814 if (!COMPARISON_P (x))
4815 output_operand_lossage ("invalid %%C value");
4817 else if (code == 'D')
4818 c = reverse_condition (c);
4819 else if (code == 'c')
4820 c = swap_condition (c);
4821 else if (code == 'd')
4822 c = swap_condition (reverse_condition (c));
4825 fprintf (file, "ule");
4827 fprintf (file, "ult");
4828 else if (c == UNORDERED)
4829 fprintf (file, "un");
4831 fprintf (file, "%s", GET_RTX_NAME (c));
4836 /* Write the divide or modulus operator. */
4837 switch (GET_CODE (x))
4840 fprintf (file, "div%s", GET_MODE (x) == SImode ? "l" : "q");
4843 fprintf (file, "div%su", GET_MODE (x) == SImode ? "l" : "q");
4846 fprintf (file, "rem%s", GET_MODE (x) == SImode ? "l" : "q");
4849 fprintf (file, "rem%su", GET_MODE (x) == SImode ? "l" : "q");
4852 output_operand_lossage ("invalid %%E value");
4858 /* Write "_u" for unaligned access. */
4859 if (GET_CODE (x) == MEM && GET_CODE (XEXP (x, 0)) == AND)
4860 fprintf (file, "_u");
4864 if (GET_CODE (x) == REG)
4865 fprintf (file, "%s", reg_names[REGNO (x)]);
4866 else if (GET_CODE (x) == MEM)
4867 output_address (XEXP (x, 0));
4868 else if (GET_CODE (x) == CONST && GET_CODE (XEXP (x, 0)) == UNSPEC)
4870 switch (XINT (XEXP (x, 0), 1))
4874 output_addr_const (file, XVECEXP (XEXP (x, 0), 0, 0));
4877 output_operand_lossage ("unknown relocation unspec");
4882 output_addr_const (file, x);
4886 output_operand_lossage ("invalid %%xn code");
4891 print_operand_address (FILE *file, rtx addr)
4894 HOST_WIDE_INT offset = 0;
4896 if (GET_CODE (addr) == AND)
4897 addr = XEXP (addr, 0);
4899 if (GET_CODE (addr) == PLUS
4900 && GET_CODE (XEXP (addr, 1)) == CONST_INT)
4902 offset = INTVAL (XEXP (addr, 1));
4903 addr = XEXP (addr, 0);
4906 if (GET_CODE (addr) == LO_SUM)
4908 const char *reloc16, *reloclo;
4909 rtx op1 = XEXP (addr, 1);
4911 if (GET_CODE (op1) == CONST && GET_CODE (XEXP (op1, 0)) == UNSPEC)
4913 op1 = XEXP (op1, 0);
4914 switch (XINT (op1, 1))
4918 reloclo = (alpha_tls_size == 16 ? "dtprel" : "dtprello");
4922 reloclo = (alpha_tls_size == 16 ? "tprel" : "tprello");
4925 output_operand_lossage ("unknown relocation unspec");
4929 output_addr_const (file, XVECEXP (op1, 0, 0));
4934 reloclo = "gprellow";
4935 output_addr_const (file, op1);
4939 fprintf (file, "+" HOST_WIDE_INT_PRINT_DEC, offset);
4941 addr = XEXP (addr, 0);
4942 if (GET_CODE (addr) == REG)
4943 basereg = REGNO (addr);
4944 else if (GET_CODE (addr) == SUBREG
4945 && GET_CODE (SUBREG_REG (addr)) == REG)
4946 basereg = subreg_regno (addr);
4950 fprintf (file, "($%d)\t\t!%s", basereg,
4951 (basereg == 29 ? reloc16 : reloclo));
4955 if (GET_CODE (addr) == REG)
4956 basereg = REGNO (addr);
4957 else if (GET_CODE (addr) == SUBREG
4958 && GET_CODE (SUBREG_REG (addr)) == REG)
4959 basereg = subreg_regno (addr);
4960 else if (GET_CODE (addr) == CONST_INT)
4961 offset = INTVAL (addr);
4963 #if TARGET_ABI_OPEN_VMS
4964 else if (GET_CODE (addr) == SYMBOL_REF)
4966 fprintf (file, "%s", XSTR (addr, 0));
4969 else if (GET_CODE (addr) == CONST
4970 && GET_CODE (XEXP (addr, 0)) == PLUS
4971 && GET_CODE (XEXP (XEXP (addr, 0), 0)) == SYMBOL_REF)
4973 fprintf (file, "%s+" HOST_WIDE_INT_PRINT_DEC,
4974 XSTR (XEXP (XEXP (addr, 0), 0), 0),
4975 INTVAL (XEXP (XEXP (addr, 0), 1)));
4983 fprintf (file, HOST_WIDE_INT_PRINT_DEC "($%d)", offset, basereg);
4986 /* Emit RTL insns to initialize the variable parts of a trampoline at
4987 TRAMP. FNADDR is an RTX for the address of the function's pure
4988 code. CXT is an RTX for the static chain value for the function.
4990 The three offset parameters are for the individual template's
4991 layout. A JMPOFS < 0 indicates that the trampoline does not
4992 contain instructions at all.
4994 We assume here that a function will be called many more times than
4995 its address is taken (e.g., it might be passed to qsort), so we
4996 take the trouble to initialize the "hint" field in the JMP insn.
4997 Note that the hint field is PC (new) + 4 * bits 13:0. */
5000 alpha_initialize_trampoline (rtx tramp, rtx fnaddr, rtx cxt,
5001 int fnofs, int cxtofs, int jmpofs)
5003 rtx temp, temp1, addr;
5004 /* VMS really uses DImode pointers in memory at this point. */
5005 enum machine_mode mode = TARGET_ABI_OPEN_VMS ? Pmode : ptr_mode;
5007 #ifdef POINTERS_EXTEND_UNSIGNED
5008 fnaddr = convert_memory_address (mode, fnaddr);
5009 cxt = convert_memory_address (mode, cxt);
5012 /* Store function address and CXT. */
5013 addr = memory_address (mode, plus_constant (tramp, fnofs));
5014 emit_move_insn (gen_rtx_MEM (mode, addr), fnaddr);
5015 addr = memory_address (mode, plus_constant (tramp, cxtofs));
5016 emit_move_insn (gen_rtx_MEM (mode, addr), cxt);
5018 /* This has been disabled since the hint only has a 32k range, and in
5019 no existing OS is the stack within 32k of the text segment. */
5020 if (0 && jmpofs >= 0)
5022 /* Compute hint value. */
5023 temp = force_operand (plus_constant (tramp, jmpofs+4), NULL_RTX);
5024 temp = expand_binop (DImode, sub_optab, fnaddr, temp, temp, 1,
5026 temp = expand_shift (RSHIFT_EXPR, Pmode, temp,
5027 build_int_cst (NULL_TREE, 2), NULL_RTX, 1);
5028 temp = expand_and (SImode, gen_lowpart (SImode, temp),
5029 GEN_INT (0x3fff), 0);
5031 /* Merge in the hint. */
5032 addr = memory_address (SImode, plus_constant (tramp, jmpofs));
5033 temp1 = force_reg (SImode, gen_rtx_MEM (SImode, addr));
5034 temp1 = expand_and (SImode, temp1, GEN_INT (0xffffc000), NULL_RTX);
5035 temp1 = expand_binop (SImode, ior_optab, temp1, temp, temp1, 1,
5037 emit_move_insn (gen_rtx_MEM (SImode, addr), temp1);
5040 #ifdef ENABLE_EXECUTE_STACK
5041 emit_library_call (init_one_libfunc ("__enable_execute_stack"),
5042 0, VOIDmode, 1, tramp, Pmode);
5046 emit_insn (gen_imb ());
5049 /* Determine where to put an argument to a function.
5050 Value is zero to push the argument on the stack,
5051 or a hard register in which to store the argument.
5053 MODE is the argument's machine mode.
5054 TYPE is the data type of the argument (as a tree).
5055 This is null for libcalls where that information may
5057 CUM is a variable of type CUMULATIVE_ARGS which gives info about
5058 the preceding args and about the function being called.
5059 NAMED is nonzero if this argument is a named parameter
5060 (otherwise it is an extra parameter matching an ellipsis).
5062 On Alpha the first 6 words of args are normally in registers
5063 and the rest are pushed. */
5066 function_arg (CUMULATIVE_ARGS cum, enum machine_mode mode, tree type,
5067 int named ATTRIBUTE_UNUSED)
5072 /* Don't get confused and pass small structures in FP registers. */
5073 if (type && AGGREGATE_TYPE_P (type))
5077 #ifdef ENABLE_CHECKING
5078 /* With alpha_split_complex_arg, we shouldn't see any raw complex
5080 if (COMPLEX_MODE_P (mode))
5084 /* Set up defaults for FP operands passed in FP registers, and
5085 integral operands passed in integer registers. */
5086 if (TARGET_FPREGS && GET_MODE_CLASS (mode) == MODE_FLOAT)
5092 /* ??? Irritatingly, the definition of CUMULATIVE_ARGS is different for
5093 the three platforms, so we can't avoid conditional compilation. */
5094 #if TARGET_ABI_OPEN_VMS
5096 if (mode == VOIDmode)
5097 return alpha_arg_info_reg_val (cum);
5099 num_args = cum.num_args;
5101 || targetm.calls.must_pass_in_stack (mode, type))
5104 #elif TARGET_ABI_UNICOSMK
5108 /* If this is the last argument, generate the call info word (CIW). */
5109 /* ??? We don't include the caller's line number in the CIW because
5110 I don't know how to determine it if debug infos are turned off. */
5111 if (mode == VOIDmode)
5120 for (i = 0; i < cum.num_reg_words && i < 5; i++)
5121 if (cum.reg_args_type[i])
5122 lo |= (1 << (7 - i));
5124 if (cum.num_reg_words == 6 && cum.reg_args_type[5])
5127 lo |= cum.num_reg_words;
5129 #if HOST_BITS_PER_WIDE_INT == 32
5130 hi = (cum.num_args << 20) | cum.num_arg_words;
5132 lo = lo | ((HOST_WIDE_INT) cum.num_args << 52)
5133 | ((HOST_WIDE_INT) cum.num_arg_words << 32);
5136 ciw = immed_double_const (lo, hi, DImode);
5138 return gen_rtx_UNSPEC (DImode, gen_rtvec (1, ciw),
5139 UNSPEC_UMK_LOAD_CIW);
5142 size = ALPHA_ARG_SIZE (mode, type, named);
5143 num_args = cum.num_reg_words;
5145 || cum.num_reg_words + size > 6
5146 || targetm.calls.must_pass_in_stack (mode, type))
5148 else if (type && TYPE_MODE (type) == BLKmode)
5152 reg1 = gen_rtx_REG (DImode, num_args + 16);
5153 reg1 = gen_rtx_EXPR_LIST (DImode, reg1, const0_rtx);
5155 /* The argument fits in two registers. Note that we still need to
5156 reserve a register for empty structures. */
5160 return gen_rtx_PARALLEL (mode, gen_rtvec (1, reg1));
5163 reg2 = gen_rtx_REG (DImode, num_args + 17);
5164 reg2 = gen_rtx_EXPR_LIST (DImode, reg2, GEN_INT (8));
5165 return gen_rtx_PARALLEL (mode, gen_rtvec (2, reg1, reg2));
5169 #elif TARGET_ABI_OSF
5175 /* VOID is passed as a special flag for "last argument". */
5176 if (type == void_type_node)
5178 else if (targetm.calls.must_pass_in_stack (mode, type))
5182 #error Unhandled ABI
5185 return gen_rtx_REG (mode, num_args + basereg);
5188 /* Return true if TYPE must be returned in memory, instead of in registers. */
5191 alpha_return_in_memory (tree type, tree fndecl ATTRIBUTE_UNUSED)
5193 enum machine_mode mode = VOIDmode;
5198 mode = TYPE_MODE (type);
5200 /* All aggregates are returned in memory. */
5201 if (AGGREGATE_TYPE_P (type))
5205 size = GET_MODE_SIZE (mode);
5206 switch (GET_MODE_CLASS (mode))
5208 case MODE_VECTOR_FLOAT:
5209 /* Pass all float vectors in memory, like an aggregate. */
5212 case MODE_COMPLEX_FLOAT:
5213 /* We judge complex floats on the size of their element,
5214 not the size of the whole type. */
5215 size = GET_MODE_UNIT_SIZE (mode);
5220 case MODE_COMPLEX_INT:
5221 case MODE_VECTOR_INT:
5225 /* ??? We get called on all sorts of random stuff from
5226 aggregate_value_p. We can't abort, but it's not clear
5227 what's safe to return. Pretend it's a struct I guess. */
5231 /* Otherwise types must fit in one register. */
5232 return size > UNITS_PER_WORD;
5235 /* Return true if TYPE should be passed by invisible reference. */
5238 alpha_pass_by_reference (CUMULATIVE_ARGS *ca ATTRIBUTE_UNUSED,
5239 enum machine_mode mode,
5240 tree type ATTRIBUTE_UNUSED,
5241 bool named ATTRIBUTE_UNUSED)
5243 return mode == TFmode || mode == TCmode;
5246 /* Define how to find the value returned by a function. VALTYPE is the
5247 data type of the value (as a tree). If the precise function being
5248 called is known, FUNC is its FUNCTION_DECL; otherwise, FUNC is 0.
5249 MODE is set instead of VALTYPE for libcalls.
5251 On Alpha the value is found in $0 for integer functions and
5252 $f0 for floating-point functions. */
5255 function_value (tree valtype, tree func ATTRIBUTE_UNUSED,
5256 enum machine_mode mode)
5258 unsigned int regnum, dummy;
5259 enum mode_class class;
5261 #ifdef ENABLE_CHECKING
5262 if (valtype && alpha_return_in_memory (valtype, func))
5267 mode = TYPE_MODE (valtype);
5269 class = GET_MODE_CLASS (mode);
5273 PROMOTE_MODE (mode, dummy, valtype);
5276 case MODE_COMPLEX_INT:
5277 case MODE_VECTOR_INT:
5285 case MODE_COMPLEX_FLOAT:
5287 enum machine_mode cmode = GET_MODE_INNER (mode);
5289 return gen_rtx_PARALLEL
5292 gen_rtx_EXPR_LIST (VOIDmode, gen_rtx_REG (cmode, 32),
5294 gen_rtx_EXPR_LIST (VOIDmode, gen_rtx_REG (cmode, 33),
5295 GEN_INT (GET_MODE_SIZE (cmode)))));
5302 return gen_rtx_REG (mode, regnum);
5305 /* TCmode complex values are passed by invisible reference. We
5306 should not split these values. */
5309 alpha_split_complex_arg (tree type)
5311 return TYPE_MODE (type) != TCmode;
5315 alpha_build_builtin_va_list (void)
5317 tree base, ofs, space, record, type_decl;
5319 if (TARGET_ABI_OPEN_VMS || TARGET_ABI_UNICOSMK)
5320 return ptr_type_node;
5322 record = (*lang_hooks.types.make_type) (RECORD_TYPE);
5323 type_decl = build_decl (TYPE_DECL, get_identifier ("__va_list_tag"), record);
5324 TREE_CHAIN (record) = type_decl;
5325 TYPE_NAME (record) = type_decl;
5327 /* C++? SET_IS_AGGR_TYPE (record, 1); */
5329 /* Dummy field to prevent alignment warnings. */
5330 space = build_decl (FIELD_DECL, NULL_TREE, integer_type_node);
5331 DECL_FIELD_CONTEXT (space) = record;
5332 DECL_ARTIFICIAL (space) = 1;
5333 DECL_IGNORED_P (space) = 1;
5335 ofs = build_decl (FIELD_DECL, get_identifier ("__offset"),
5337 DECL_FIELD_CONTEXT (ofs) = record;
5338 TREE_CHAIN (ofs) = space;
5340 base = build_decl (FIELD_DECL, get_identifier ("__base"),
5342 DECL_FIELD_CONTEXT (base) = record;
5343 TREE_CHAIN (base) = ofs;
5345 TYPE_FIELDS (record) = base;
5346 layout_type (record);
5351 /* Perform any needed actions needed for a function that is receiving a
5352 variable number of arguments. */
5355 alpha_setup_incoming_varargs (CUMULATIVE_ARGS *pcum,
5356 enum machine_mode mode ATTRIBUTE_UNUSED,
5357 tree type ATTRIBUTE_UNUSED,
5358 int *pretend_size, int no_rtl)
5360 #if TARGET_ABI_UNICOSMK
5361 /* On Unicos/Mk, the standard subroutine __T3E_MISMATCH stores all register
5362 arguments on the stack. Unfortunately, it doesn't always store the first
5363 one (i.e. the one that arrives in $16 or $f16). This is not a problem
5364 with stdargs as we always have at least one named argument there. */
5365 int num_reg_words = pcum->num_reg_words;
5366 if (num_reg_words < 6)
5370 emit_insn (gen_umk_mismatch_args (GEN_INT (num_reg_words + 1)));
5371 emit_insn (gen_arg_home_umk ());
5375 #elif TARGET_ABI_OPEN_VMS
5376 /* For VMS, we allocate space for all 6 arg registers plus a count.
5378 However, if NO registers need to be saved, don't allocate any space.
5379 This is not only because we won't need the space, but because AP
5380 includes the current_pretend_args_size and we don't want to mess up
5381 any ap-relative addresses already made. */
5382 if (pcum->num_args < 6)
5386 emit_move_insn (gen_rtx_REG (DImode, 1), virtual_incoming_args_rtx);
5387 emit_insn (gen_arg_home ());
5389 *pretend_size = 7 * UNITS_PER_WORD;
5392 /* On OSF/1 and friends, we allocate space for all 12 arg registers, but
5393 only push those that are remaining. However, if NO registers need to
5394 be saved, don't allocate any space. This is not only because we won't
5395 need the space, but because AP includes the current_pretend_args_size
5396 and we don't want to mess up any ap-relative addresses already made.
5398 If we are not to use the floating-point registers, save the integer
5399 registers where we would put the floating-point registers. This is
5400 not the most efficient way to implement varargs with just one register
5401 class, but it isn't worth doing anything more efficient in this rare
5403 CUMULATIVE_ARGS cum = *pcum;
5410 int set = get_varargs_alias_set ();
5413 tmp = gen_rtx_MEM (BLKmode,
5414 plus_constant (virtual_incoming_args_rtx,
5415 (cum + 6) * UNITS_PER_WORD));
5416 set_mem_alias_set (tmp, set);
5417 move_block_from_reg (16 + cum, tmp, 6 - cum);
5419 tmp = gen_rtx_MEM (BLKmode,
5420 plus_constant (virtual_incoming_args_rtx,
5421 cum * UNITS_PER_WORD));
5422 set_mem_alias_set (tmp, set);
5423 move_block_from_reg (16 + (TARGET_FPREGS ? 32 : 0) + cum, tmp,
5426 *pretend_size = 12 * UNITS_PER_WORD;
5431 alpha_va_start (tree valist, rtx nextarg ATTRIBUTE_UNUSED)
5433 HOST_WIDE_INT offset;
5434 tree t, offset_field, base_field;
5436 if (TREE_CODE (TREE_TYPE (valist)) == ERROR_MARK)
5439 if (TARGET_ABI_UNICOSMK)
5440 std_expand_builtin_va_start (valist, nextarg);
5442 /* For Unix, TARGET_SETUP_INCOMING_VARARGS moves the starting address base
5443 up by 48, storing fp arg registers in the first 48 bytes, and the
5444 integer arg registers in the next 48 bytes. This is only done,
5445 however, if any integer registers need to be stored.
5447 If no integer registers need be stored, then we must subtract 48
5448 in order to account for the integer arg registers which are counted
5449 in argsize above, but which are not actually stored on the stack.
5450 Must further be careful here about structures straddling the last
5451 integer argument register; that futzes with pretend_args_size,
5452 which changes the meaning of AP. */
5455 offset = TARGET_ABI_OPEN_VMS ? UNITS_PER_WORD : 6 * UNITS_PER_WORD;
5457 offset = -6 * UNITS_PER_WORD + current_function_pretend_args_size;
5459 if (TARGET_ABI_OPEN_VMS)
5461 nextarg = plus_constant (nextarg, offset);
5462 nextarg = plus_constant (nextarg, NUM_ARGS * UNITS_PER_WORD);
5463 t = build (MODIFY_EXPR, TREE_TYPE (valist), valist,
5464 make_tree (ptr_type_node, nextarg));
5465 TREE_SIDE_EFFECTS (t) = 1;
5467 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5471 base_field = TYPE_FIELDS (TREE_TYPE (valist));
5472 offset_field = TREE_CHAIN (base_field);
5474 base_field = build (COMPONENT_REF, TREE_TYPE (base_field),
5475 valist, base_field, NULL_TREE);
5476 offset_field = build (COMPONENT_REF, TREE_TYPE (offset_field),
5477 valist, offset_field, NULL_TREE);
5479 t = make_tree (ptr_type_node, virtual_incoming_args_rtx);
5480 t = build (PLUS_EXPR, ptr_type_node, t,
5481 build_int_cst (NULL_TREE, offset));
5482 t = build (MODIFY_EXPR, TREE_TYPE (base_field), base_field, t);
5483 TREE_SIDE_EFFECTS (t) = 1;
5484 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5486 t = build_int_cst (NULL_TREE, NUM_ARGS * UNITS_PER_WORD);
5487 t = build (MODIFY_EXPR, TREE_TYPE (offset_field), offset_field, t);
5488 TREE_SIDE_EFFECTS (t) = 1;
5489 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5494 alpha_gimplify_va_arg_1 (tree type, tree base, tree offset, tree *pre_p)
5496 tree type_size, ptr_type, addend, t, addr, internal_post;
5498 /* If the type could not be passed in registers, skip the block
5499 reserved for the registers. */
5500 if (targetm.calls.must_pass_in_stack (TYPE_MODE (type), type))
5502 t = build_int_cst (TREE_TYPE (offset), 6*8);
5503 t = build (MODIFY_EXPR, TREE_TYPE (offset), offset,
5504 build (MAX_EXPR, TREE_TYPE (offset), offset, t));
5505 gimplify_and_add (t, pre_p);
5509 ptr_type = build_pointer_type (type);
5511 if (TREE_CODE (type) == COMPLEX_TYPE)
5513 tree real_part, imag_part, real_temp;
5515 real_part = alpha_gimplify_va_arg_1 (TREE_TYPE (type), base,
5518 /* Copy the value into a new temporary, lest the formal temporary
5519 be reused out from under us. */
5520 real_temp = get_initialized_tmp_var (real_part, pre_p, NULL);
5522 imag_part = alpha_gimplify_va_arg_1 (TREE_TYPE (type), base,
5525 return build (COMPLEX_EXPR, type, real_temp, imag_part);
5527 else if (TREE_CODE (type) == REAL_TYPE)
5529 tree fpaddend, cond, fourtyeight;
5531 fourtyeight = build_int_cst (TREE_TYPE (addend), 6*8);
5532 fpaddend = fold (build (MINUS_EXPR, TREE_TYPE (addend),
5533 addend, fourtyeight));
5534 cond = fold (build (LT_EXPR, boolean_type_node, addend, fourtyeight));
5535 addend = fold (build (COND_EXPR, TREE_TYPE (addend), cond,
5539 /* Build the final address and force that value into a temporary. */
5540 addr = build (PLUS_EXPR, ptr_type, fold_convert (ptr_type, base),
5541 fold_convert (ptr_type, addend));
5542 internal_post = NULL;
5543 gimplify_expr (&addr, pre_p, &internal_post, is_gimple_val, fb_rvalue);
5544 append_to_statement_list (internal_post, pre_p);
5546 /* Update the offset field. */
5547 type_size = TYPE_SIZE_UNIT (TYPE_MAIN_VARIANT (type));
5548 if (type_size == NULL || TREE_OVERFLOW (type_size))
5552 t = size_binop (PLUS_EXPR, type_size, size_int (7));
5553 t = size_binop (TRUNC_DIV_EXPR, t, size_int (8));
5554 t = size_binop (MULT_EXPR, t, size_int (8));
5556 t = fold_convert (TREE_TYPE (offset), t);
5557 t = build (MODIFY_EXPR, void_type_node, offset,
5558 build (PLUS_EXPR, TREE_TYPE (offset), offset, t));
5559 gimplify_and_add (t, pre_p);
5561 return build_fold_indirect_ref (addr);
5565 alpha_gimplify_va_arg (tree valist, tree type, tree *pre_p, tree *post_p)
5567 tree offset_field, base_field, offset, base, t, r;
5570 if (TARGET_ABI_OPEN_VMS || TARGET_ABI_UNICOSMK)
5571 return std_gimplify_va_arg_expr (valist, type, pre_p, post_p);
5573 base_field = TYPE_FIELDS (va_list_type_node);
5574 offset_field = TREE_CHAIN (base_field);
5575 base_field = build (COMPONENT_REF, TREE_TYPE (base_field),
5576 valist, base_field, NULL_TREE);
5577 offset_field = build (COMPONENT_REF, TREE_TYPE (offset_field),
5578 valist, offset_field, NULL_TREE);
5580 /* Pull the fields of the structure out into temporaries. Since we never
5581 modify the base field, we can use a formal temporary. Sign-extend the
5582 offset field so that it's the proper width for pointer arithmetic. */
5583 base = get_formal_tmp_var (base_field, pre_p);
5585 t = fold_convert (lang_hooks.types.type_for_size (64, 0), offset_field);
5586 offset = get_initialized_tmp_var (t, pre_p, NULL);
5588 indirect = pass_by_reference (NULL, TYPE_MODE (type), type, false);
5590 type = build_pointer_type (type);
5592 /* Find the value. Note that this will be a stable indirection, or
5593 a composite of stable indirections in the case of complex. */
5594 r = alpha_gimplify_va_arg_1 (type, base, offset, pre_p);
5596 /* Stuff the offset temporary back into its field. */
5597 t = build (MODIFY_EXPR, void_type_node, offset_field,
5598 fold_convert (TREE_TYPE (offset_field), offset));
5599 gimplify_and_add (t, pre_p);
5602 r = build_fold_indirect_ref (r);
5611 ALPHA_BUILTIN_CMPBGE,
5612 ALPHA_BUILTIN_EXTBL,
5613 ALPHA_BUILTIN_EXTWL,
5614 ALPHA_BUILTIN_EXTLL,
5615 ALPHA_BUILTIN_EXTQL,
5616 ALPHA_BUILTIN_EXTWH,
5617 ALPHA_BUILTIN_EXTLH,
5618 ALPHA_BUILTIN_EXTQH,
5619 ALPHA_BUILTIN_INSBL,
5620 ALPHA_BUILTIN_INSWL,
5621 ALPHA_BUILTIN_INSLL,
5622 ALPHA_BUILTIN_INSQL,
5623 ALPHA_BUILTIN_INSWH,
5624 ALPHA_BUILTIN_INSLH,
5625 ALPHA_BUILTIN_INSQH,
5626 ALPHA_BUILTIN_MSKBL,
5627 ALPHA_BUILTIN_MSKWL,
5628 ALPHA_BUILTIN_MSKLL,
5629 ALPHA_BUILTIN_MSKQL,
5630 ALPHA_BUILTIN_MSKWH,
5631 ALPHA_BUILTIN_MSKLH,
5632 ALPHA_BUILTIN_MSKQH,
5633 ALPHA_BUILTIN_UMULH,
5635 ALPHA_BUILTIN_ZAPNOT,
5636 ALPHA_BUILTIN_AMASK,
5637 ALPHA_BUILTIN_IMPLVER,
5639 ALPHA_BUILTIN_THREAD_POINTER,
5640 ALPHA_BUILTIN_SET_THREAD_POINTER,
5643 ALPHA_BUILTIN_MINUB8,
5644 ALPHA_BUILTIN_MINSB8,
5645 ALPHA_BUILTIN_MINUW4,
5646 ALPHA_BUILTIN_MINSW4,
5647 ALPHA_BUILTIN_MAXUB8,
5648 ALPHA_BUILTIN_MAXSB8,
5649 ALPHA_BUILTIN_MAXUW4,
5650 ALPHA_BUILTIN_MAXSW4,
5654 ALPHA_BUILTIN_UNPKBL,
5655 ALPHA_BUILTIN_UNPKBW,
5660 ALPHA_BUILTIN_CTPOP,
5665 static unsigned int const code_for_builtin[ALPHA_BUILTIN_max] = {
5666 CODE_FOR_builtin_cmpbge,
5667 CODE_FOR_builtin_extbl,
5668 CODE_FOR_builtin_extwl,
5669 CODE_FOR_builtin_extll,
5670 CODE_FOR_builtin_extql,
5671 CODE_FOR_builtin_extwh,
5672 CODE_FOR_builtin_extlh,
5673 CODE_FOR_builtin_extqh,
5674 CODE_FOR_builtin_insbl,
5675 CODE_FOR_builtin_inswl,
5676 CODE_FOR_builtin_insll,
5677 CODE_FOR_builtin_insql,
5678 CODE_FOR_builtin_inswh,
5679 CODE_FOR_builtin_inslh,
5680 CODE_FOR_builtin_insqh,
5681 CODE_FOR_builtin_mskbl,
5682 CODE_FOR_builtin_mskwl,
5683 CODE_FOR_builtin_mskll,
5684 CODE_FOR_builtin_mskql,
5685 CODE_FOR_builtin_mskwh,
5686 CODE_FOR_builtin_msklh,
5687 CODE_FOR_builtin_mskqh,
5688 CODE_FOR_umuldi3_highpart,
5689 CODE_FOR_builtin_zap,
5690 CODE_FOR_builtin_zapnot,
5691 CODE_FOR_builtin_amask,
5692 CODE_FOR_builtin_implver,
5693 CODE_FOR_builtin_rpcc,
5698 CODE_FOR_builtin_minub8,
5699 CODE_FOR_builtin_minsb8,
5700 CODE_FOR_builtin_minuw4,
5701 CODE_FOR_builtin_minsw4,
5702 CODE_FOR_builtin_maxub8,
5703 CODE_FOR_builtin_maxsb8,
5704 CODE_FOR_builtin_maxuw4,
5705 CODE_FOR_builtin_maxsw4,
5706 CODE_FOR_builtin_perr,
5707 CODE_FOR_builtin_pklb,
5708 CODE_FOR_builtin_pkwb,
5709 CODE_FOR_builtin_unpkbl,
5710 CODE_FOR_builtin_unpkbw,
5713 CODE_FOR_builtin_cttz,
5714 CODE_FOR_builtin_ctlz,
5715 CODE_FOR_builtin_ctpop
5718 struct alpha_builtin_def
5721 enum alpha_builtin code;
5722 unsigned int target_mask;
5725 static struct alpha_builtin_def const zero_arg_builtins[] = {
5726 { "__builtin_alpha_implver", ALPHA_BUILTIN_IMPLVER, 0 },
5727 { "__builtin_alpha_rpcc", ALPHA_BUILTIN_RPCC, 0 }
5730 static struct alpha_builtin_def const one_arg_builtins[] = {
5731 { "__builtin_alpha_amask", ALPHA_BUILTIN_AMASK, 0 },
5732 { "__builtin_alpha_pklb", ALPHA_BUILTIN_PKLB, MASK_MAX },
5733 { "__builtin_alpha_pkwb", ALPHA_BUILTIN_PKWB, MASK_MAX },
5734 { "__builtin_alpha_unpkbl", ALPHA_BUILTIN_UNPKBL, MASK_MAX },
5735 { "__builtin_alpha_unpkbw", ALPHA_BUILTIN_UNPKBW, MASK_MAX },
5736 { "__builtin_alpha_cttz", ALPHA_BUILTIN_CTTZ, MASK_CIX },
5737 { "__builtin_alpha_ctlz", ALPHA_BUILTIN_CTLZ, MASK_CIX },
5738 { "__builtin_alpha_ctpop", ALPHA_BUILTIN_CTPOP, MASK_CIX }
5741 static struct alpha_builtin_def const two_arg_builtins[] = {
5742 { "__builtin_alpha_cmpbge", ALPHA_BUILTIN_CMPBGE, 0 },
5743 { "__builtin_alpha_extbl", ALPHA_BUILTIN_EXTBL, 0 },
5744 { "__builtin_alpha_extwl", ALPHA_BUILTIN_EXTWL, 0 },
5745 { "__builtin_alpha_extll", ALPHA_BUILTIN_EXTLL, 0 },
5746 { "__builtin_alpha_extql", ALPHA_BUILTIN_EXTQL, 0 },
5747 { "__builtin_alpha_extwh", ALPHA_BUILTIN_EXTWH, 0 },
5748 { "__builtin_alpha_extlh", ALPHA_BUILTIN_EXTLH, 0 },
5749 { "__builtin_alpha_extqh", ALPHA_BUILTIN_EXTQH, 0 },
5750 { "__builtin_alpha_insbl", ALPHA_BUILTIN_INSBL, 0 },
5751 { "__builtin_alpha_inswl", ALPHA_BUILTIN_INSWL, 0 },
5752 { "__builtin_alpha_insll", ALPHA_BUILTIN_INSLL, 0 },
5753 { "__builtin_alpha_insql", ALPHA_BUILTIN_INSQL, 0 },
5754 { "__builtin_alpha_inswh", ALPHA_BUILTIN_INSWH, 0 },
5755 { "__builtin_alpha_inslh", ALPHA_BUILTIN_INSLH, 0 },
5756 { "__builtin_alpha_insqh", ALPHA_BUILTIN_INSQH, 0 },
5757 { "__builtin_alpha_mskbl", ALPHA_BUILTIN_MSKBL, 0 },
5758 { "__builtin_alpha_mskwl", ALPHA_BUILTIN_MSKWL, 0 },
5759 { "__builtin_alpha_mskll", ALPHA_BUILTIN_MSKLL, 0 },
5760 { "__builtin_alpha_mskql", ALPHA_BUILTIN_MSKQL, 0 },
5761 { "__builtin_alpha_mskwh", ALPHA_BUILTIN_MSKWH, 0 },
5762 { "__builtin_alpha_msklh", ALPHA_BUILTIN_MSKLH, 0 },
5763 { "__builtin_alpha_mskqh", ALPHA_BUILTIN_MSKQH, 0 },
5764 { "__builtin_alpha_umulh", ALPHA_BUILTIN_UMULH, 0 },
5765 { "__builtin_alpha_zap", ALPHA_BUILTIN_ZAP, 0 },
5766 { "__builtin_alpha_zapnot", ALPHA_BUILTIN_ZAPNOT, 0 },
5767 { "__builtin_alpha_minub8", ALPHA_BUILTIN_MINUB8, MASK_MAX },
5768 { "__builtin_alpha_minsb8", ALPHA_BUILTIN_MINSB8, MASK_MAX },
5769 { "__builtin_alpha_minuw4", ALPHA_BUILTIN_MINUW4, MASK_MAX },
5770 { "__builtin_alpha_minsw4", ALPHA_BUILTIN_MINSW4, MASK_MAX },
5771 { "__builtin_alpha_maxub8", ALPHA_BUILTIN_MAXUB8, MASK_MAX },
5772 { "__builtin_alpha_maxsb8", ALPHA_BUILTIN_MAXSB8, MASK_MAX },
5773 { "__builtin_alpha_maxuw4", ALPHA_BUILTIN_MAXUW4, MASK_MAX },
5774 { "__builtin_alpha_maxsw4", ALPHA_BUILTIN_MAXSW4, MASK_MAX },
5775 { "__builtin_alpha_perr", ALPHA_BUILTIN_PERR, MASK_MAX }
5779 alpha_init_builtins (void)
5781 const struct alpha_builtin_def *p;
5785 ftype = build_function_type (long_integer_type_node, void_list_node);
5787 p = zero_arg_builtins;
5788 for (i = 0; i < ARRAY_SIZE (zero_arg_builtins); ++i, ++p)
5789 if ((target_flags & p->target_mask) == p->target_mask)
5790 lang_hooks.builtin_function (p->name, ftype, p->code, BUILT_IN_MD,
5793 ftype = build_function_type_list (long_integer_type_node,
5794 long_integer_type_node, NULL_TREE);
5796 p = one_arg_builtins;
5797 for (i = 0; i < ARRAY_SIZE (one_arg_builtins); ++i, ++p)
5798 if ((target_flags & p->target_mask) == p->target_mask)
5799 lang_hooks.builtin_function (p->name, ftype, p->code, BUILT_IN_MD,
5802 ftype = build_function_type_list (long_integer_type_node,
5803 long_integer_type_node,
5804 long_integer_type_node, NULL_TREE);
5806 p = two_arg_builtins;
5807 for (i = 0; i < ARRAY_SIZE (two_arg_builtins); ++i, ++p)
5808 if ((target_flags & p->target_mask) == p->target_mask)
5809 lang_hooks.builtin_function (p->name, ftype, p->code, BUILT_IN_MD,
5812 ftype = build_function_type (ptr_type_node, void_list_node);
5813 lang_hooks.builtin_function ("__builtin_thread_pointer", ftype,
5814 ALPHA_BUILTIN_THREAD_POINTER, BUILT_IN_MD,
5817 ftype = build_function_type_list (void_type_node, ptr_type_node, NULL_TREE);
5818 lang_hooks.builtin_function ("__builtin_set_thread_pointer", ftype,
5819 ALPHA_BUILTIN_SET_THREAD_POINTER, BUILT_IN_MD,
5823 /* Expand an expression EXP that calls a built-in function,
5824 with result going to TARGET if that's convenient
5825 (and in mode MODE if that's convenient).
5826 SUBTARGET may be used as the target for computing one of EXP's operands.
5827 IGNORE is nonzero if the value is to be ignored. */
5830 alpha_expand_builtin (tree exp, rtx target,
5831 rtx subtarget ATTRIBUTE_UNUSED,
5832 enum machine_mode mode ATTRIBUTE_UNUSED,
5833 int ignore ATTRIBUTE_UNUSED)
5837 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
5838 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
5839 tree arglist = TREE_OPERAND (exp, 1);
5840 enum insn_code icode;
5841 rtx op[MAX_ARGS], pat;
5845 if (fcode >= ALPHA_BUILTIN_max)
5846 internal_error ("bad builtin fcode");
5847 icode = code_for_builtin[fcode];
5849 internal_error ("bad builtin fcode");
5851 nonvoid = TREE_TYPE (TREE_TYPE (fndecl)) != void_type_node;
5853 for (arglist = TREE_OPERAND (exp, 1), arity = 0;
5855 arglist = TREE_CHAIN (arglist), arity++)
5857 const struct insn_operand_data *insn_op;
5859 tree arg = TREE_VALUE (arglist);
5860 if (arg == error_mark_node)
5862 if (arity > MAX_ARGS)
5865 insn_op = &insn_data[icode].operand[arity + nonvoid];
5867 op[arity] = expand_expr (arg, NULL_RTX, insn_op->mode, 0);
5869 if (!(*insn_op->predicate) (op[arity], insn_op->mode))
5870 op[arity] = copy_to_mode_reg (insn_op->mode, op[arity]);
5875 enum machine_mode tmode = insn_data[icode].operand[0].mode;
5877 || GET_MODE (target) != tmode
5878 || !(*insn_data[icode].operand[0].predicate) (target, tmode))
5879 target = gen_reg_rtx (tmode);
5885 pat = GEN_FCN (icode) (target);
5889 pat = GEN_FCN (icode) (target, op[0]);
5891 pat = GEN_FCN (icode) (op[0]);
5894 pat = GEN_FCN (icode) (target, op[0], op[1]);
5909 /* This page contains routines that are used to determine what the function
5910 prologue and epilogue code will do and write them out. */
5912 /* Compute the size of the save area in the stack. */
5914 /* These variables are used for communication between the following functions.
5915 They indicate various things about the current function being compiled
5916 that are used to tell what kind of prologue, epilogue and procedure
5917 descriptor to generate. */
5919 /* Nonzero if we need a stack procedure. */
5920 enum alpha_procedure_types {PT_NULL = 0, PT_REGISTER = 1, PT_STACK = 2};
5921 static enum alpha_procedure_types alpha_procedure_type;
5923 /* Register number (either FP or SP) that is used to unwind the frame. */
5924 static int vms_unwind_regno;
5926 /* Register number used to save FP. We need not have one for RA since
5927 we don't modify it for register procedures. This is only defined
5928 for register frame procedures. */
5929 static int vms_save_fp_regno;
5931 /* Register number used to reference objects off our PV. */
5932 static int vms_base_regno;
5934 /* Compute register masks for saved registers. */
5937 alpha_sa_mask (unsigned long *imaskP, unsigned long *fmaskP)
5939 unsigned long imask = 0;
5940 unsigned long fmask = 0;
5943 /* When outputting a thunk, we don't have valid register life info,
5944 but assemble_start_function wants to output .frame and .mask
5946 if (current_function_is_thunk)
5953 if (TARGET_ABI_OPEN_VMS && alpha_procedure_type == PT_STACK)
5954 imask |= (1UL << HARD_FRAME_POINTER_REGNUM);
5956 /* One for every register we have to save. */
5957 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
5958 if (! fixed_regs[i] && ! call_used_regs[i]
5959 && regs_ever_live[i] && i != REG_RA
5960 && (!TARGET_ABI_UNICOSMK || i != HARD_FRAME_POINTER_REGNUM))
5963 imask |= (1UL << i);
5965 fmask |= (1UL << (i - 32));
5968 /* We need to restore these for the handler. */
5969 if (current_function_calls_eh_return)
5973 unsigned regno = EH_RETURN_DATA_REGNO (i);
5974 if (regno == INVALID_REGNUM)
5976 imask |= 1UL << regno;
5980 /* If any register spilled, then spill the return address also. */
5981 /* ??? This is required by the Digital stack unwind specification
5982 and isn't needed if we're doing Dwarf2 unwinding. */
5983 if (imask || fmask || alpha_ra_ever_killed ())
5984 imask |= (1UL << REG_RA);
5991 alpha_sa_size (void)
5993 unsigned long mask[2];
5997 alpha_sa_mask (&mask[0], &mask[1]);
5999 if (TARGET_ABI_UNICOSMK)
6001 if (mask[0] || mask[1])
6006 for (j = 0; j < 2; ++j)
6007 for (i = 0; i < 32; ++i)
6008 if ((mask[j] >> i) & 1)
6012 if (TARGET_ABI_UNICOSMK)
6014 /* We might not need to generate a frame if we don't make any calls
6015 (including calls to __T3E_MISMATCH if this is a vararg function),
6016 don't have any local variables which require stack slots, don't
6017 use alloca and have not determined that we need a frame for other
6020 alpha_procedure_type
6021 = (sa_size || get_frame_size() != 0
6022 || current_function_outgoing_args_size
6023 || current_function_stdarg || current_function_calls_alloca
6024 || frame_pointer_needed)
6025 ? PT_STACK : PT_REGISTER;
6027 /* Always reserve space for saving callee-saved registers if we
6028 need a frame as required by the calling convention. */
6029 if (alpha_procedure_type == PT_STACK)
6032 else if (TARGET_ABI_OPEN_VMS)
6034 /* Start by assuming we can use a register procedure if we don't
6035 make any calls (REG_RA not used) or need to save any
6036 registers and a stack procedure if we do. */
6037 if ((mask[0] >> REG_RA) & 1)
6038 alpha_procedure_type = PT_STACK;
6039 else if (get_frame_size() != 0)
6040 alpha_procedure_type = PT_REGISTER;
6042 alpha_procedure_type = PT_NULL;
6044 /* Don't reserve space for saving FP & RA yet. Do that later after we've
6045 made the final decision on stack procedure vs register procedure. */
6046 if (alpha_procedure_type == PT_STACK)
6049 /* Decide whether to refer to objects off our PV via FP or PV.
6050 If we need FP for something else or if we receive a nonlocal
6051 goto (which expects PV to contain the value), we must use PV.
6052 Otherwise, start by assuming we can use FP. */
6055 = (frame_pointer_needed
6056 || current_function_has_nonlocal_label
6057 || alpha_procedure_type == PT_STACK
6058 || current_function_outgoing_args_size)
6059 ? REG_PV : HARD_FRAME_POINTER_REGNUM;
6061 /* If we want to copy PV into FP, we need to find some register
6062 in which to save FP. */
6064 vms_save_fp_regno = -1;
6065 if (vms_base_regno == HARD_FRAME_POINTER_REGNUM)
6066 for (i = 0; i < 32; i++)
6067 if (! fixed_regs[i] && call_used_regs[i] && ! regs_ever_live[i])
6068 vms_save_fp_regno = i;
6070 if (vms_save_fp_regno == -1 && alpha_procedure_type == PT_REGISTER)
6071 vms_base_regno = REG_PV, alpha_procedure_type = PT_STACK;
6072 else if (alpha_procedure_type == PT_NULL)
6073 vms_base_regno = REG_PV;
6075 /* Stack unwinding should be done via FP unless we use it for PV. */
6076 vms_unwind_regno = (vms_base_regno == REG_PV
6077 ? HARD_FRAME_POINTER_REGNUM : STACK_POINTER_REGNUM);
6079 /* If this is a stack procedure, allow space for saving FP and RA. */
6080 if (alpha_procedure_type == PT_STACK)
6085 /* Our size must be even (multiple of 16 bytes). */
6093 /* Define the offset between two registers, one to be eliminated,
6094 and the other its replacement, at the start of a routine. */
6097 alpha_initial_elimination_offset (unsigned int from,
6098 unsigned int to ATTRIBUTE_UNUSED)
6102 ret = alpha_sa_size ();
6103 ret += ALPHA_ROUND (current_function_outgoing_args_size);
6105 if (from == FRAME_POINTER_REGNUM)
6107 else if (from == ARG_POINTER_REGNUM)
6108 ret += (ALPHA_ROUND (get_frame_size ()
6109 + current_function_pretend_args_size)
6110 - current_function_pretend_args_size);
6118 alpha_pv_save_size (void)
6121 return alpha_procedure_type == PT_STACK ? 8 : 0;
6125 alpha_using_fp (void)
6128 return vms_unwind_regno == HARD_FRAME_POINTER_REGNUM;
6131 #if TARGET_ABI_OPEN_VMS
6133 const struct attribute_spec vms_attribute_table[] =
6135 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
6136 { "overlaid", 0, 0, true, false, false, NULL },
6137 { "global", 0, 0, true, false, false, NULL },
6138 { "initialize", 0, 0, true, false, false, NULL },
6139 { NULL, 0, 0, false, false, false, NULL }
6145 find_lo_sum_using_gp (rtx *px, void *data ATTRIBUTE_UNUSED)
6147 return GET_CODE (*px) == LO_SUM && XEXP (*px, 0) == pic_offset_table_rtx;
6151 alpha_find_lo_sum_using_gp (rtx insn)
6153 return for_each_rtx (&PATTERN (insn), find_lo_sum_using_gp, NULL) > 0;
6157 alpha_does_function_need_gp (void)
6161 /* The GP being variable is an OSF abi thing. */
6162 if (! TARGET_ABI_OSF)
6165 /* We need the gp to load the address of __mcount. */
6166 if (TARGET_PROFILING_NEEDS_GP && current_function_profile)
6169 /* The code emitted by alpha_output_mi_thunk_osf uses the gp. */
6170 if (current_function_is_thunk)
6173 /* The nonlocal receiver pattern assumes that the gp is valid for
6174 the nested function. Reasonable because it's almost always set
6175 correctly already. For the cases where that's wrong, make sure
6176 the nested function loads its gp on entry. */
6177 if (current_function_has_nonlocal_goto)
6180 /* If we need a GP (we have a LDSYM insn or a CALL_INSN), load it first.
6181 Even if we are a static function, we still need to do this in case
6182 our address is taken and passed to something like qsort. */
6184 push_topmost_sequence ();
6185 insn = get_insns ();
6186 pop_topmost_sequence ();
6188 for (; insn; insn = NEXT_INSN (insn))
6190 && GET_CODE (PATTERN (insn)) != USE
6191 && GET_CODE (PATTERN (insn)) != CLOBBER
6192 && get_attr_usegp (insn))
6199 /* Helper function to set RTX_FRAME_RELATED_P on instructions, including
6203 set_frame_related_p (void)
6205 rtx seq = get_insns ();
6216 while (insn != NULL_RTX)
6218 RTX_FRAME_RELATED_P (insn) = 1;
6219 insn = NEXT_INSN (insn);
6221 seq = emit_insn (seq);
6225 seq = emit_insn (seq);
6226 RTX_FRAME_RELATED_P (seq) = 1;
6231 #define FRP(exp) (start_sequence (), exp, set_frame_related_p ())
6233 /* Generates a store with the proper unwind info attached. VALUE is
6234 stored at BASE_REG+BASE_OFS. If FRAME_BIAS is nonzero, then BASE_REG
6235 contains SP+FRAME_BIAS, and that is the unwind info that should be
6236 generated. If FRAME_REG != VALUE, then VALUE is being stored on
6237 behalf of FRAME_REG, and FRAME_REG should be present in the unwind. */
6240 emit_frame_store_1 (rtx value, rtx base_reg, HOST_WIDE_INT frame_bias,
6241 HOST_WIDE_INT base_ofs, rtx frame_reg)
6243 rtx addr, mem, insn;
6245 addr = plus_constant (base_reg, base_ofs);
6246 mem = gen_rtx_MEM (DImode, addr);
6247 set_mem_alias_set (mem, alpha_sr_alias_set);
6249 insn = emit_move_insn (mem, value);
6250 RTX_FRAME_RELATED_P (insn) = 1;
6252 if (frame_bias || value != frame_reg)
6256 addr = plus_constant (stack_pointer_rtx, frame_bias + base_ofs);
6257 mem = gen_rtx_MEM (DImode, addr);
6261 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
6262 gen_rtx_SET (VOIDmode, mem, frame_reg),
6268 emit_frame_store (unsigned int regno, rtx base_reg,
6269 HOST_WIDE_INT frame_bias, HOST_WIDE_INT base_ofs)
6271 rtx reg = gen_rtx_REG (DImode, regno);
6272 emit_frame_store_1 (reg, base_reg, frame_bias, base_ofs, reg);
6275 /* Write function prologue. */
6277 /* On vms we have two kinds of functions:
6279 - stack frame (PROC_STACK)
6280 these are 'normal' functions with local vars and which are
6281 calling other functions
6282 - register frame (PROC_REGISTER)
6283 keeps all data in registers, needs no stack
6285 We must pass this to the assembler so it can generate the
6286 proper pdsc (procedure descriptor)
6287 This is done with the '.pdesc' command.
6289 On not-vms, we don't really differentiate between the two, as we can
6290 simply allocate stack without saving registers. */
6293 alpha_expand_prologue (void)
6295 /* Registers to save. */
6296 unsigned long imask = 0;
6297 unsigned long fmask = 0;
6298 /* Stack space needed for pushing registers clobbered by us. */
6299 HOST_WIDE_INT sa_size;
6300 /* Complete stack size needed. */
6301 HOST_WIDE_INT frame_size;
6302 /* Offset from base reg to register save area. */
6303 HOST_WIDE_INT reg_offset;
6307 sa_size = alpha_sa_size ();
6309 frame_size = get_frame_size ();
6310 if (TARGET_ABI_OPEN_VMS)
6311 frame_size = ALPHA_ROUND (sa_size
6312 + (alpha_procedure_type == PT_STACK ? 8 : 0)
6314 + current_function_pretend_args_size);
6315 else if (TARGET_ABI_UNICOSMK)
6316 /* We have to allocate space for the DSIB if we generate a frame. */
6317 frame_size = ALPHA_ROUND (sa_size
6318 + (alpha_procedure_type == PT_STACK ? 48 : 0))
6319 + ALPHA_ROUND (frame_size
6320 + current_function_outgoing_args_size);
6322 frame_size = (ALPHA_ROUND (current_function_outgoing_args_size)
6324 + ALPHA_ROUND (frame_size
6325 + current_function_pretend_args_size));
6327 if (TARGET_ABI_OPEN_VMS)
6330 reg_offset = ALPHA_ROUND (current_function_outgoing_args_size);
6332 alpha_sa_mask (&imask, &fmask);
6334 /* Emit an insn to reload GP, if needed. */
6337 alpha_function_needs_gp = alpha_does_function_need_gp ();
6338 if (alpha_function_needs_gp)
6339 emit_insn (gen_prologue_ldgp ());
6342 /* TARGET_PROFILING_NEEDS_GP actually implies that we need to insert
6343 the call to mcount ourselves, rather than having the linker do it
6344 magically in response to -pg. Since _mcount has special linkage,
6345 don't represent the call as a call. */
6346 if (TARGET_PROFILING_NEEDS_GP && current_function_profile)
6347 emit_insn (gen_prologue_mcount ());
6349 if (TARGET_ABI_UNICOSMK)
6350 unicosmk_gen_dsib (&imask);
6352 /* Adjust the stack by the frame size. If the frame size is > 4096
6353 bytes, we need to be sure we probe somewhere in the first and last
6354 4096 bytes (we can probably get away without the latter test) and
6355 every 8192 bytes in between. If the frame size is > 32768, we
6356 do this in a loop. Otherwise, we generate the explicit probe
6359 Note that we are only allowed to adjust sp once in the prologue. */
6361 if (frame_size <= 32768)
6363 if (frame_size > 4096)
6368 emit_insn (gen_probe_stack (GEN_INT (TARGET_ABI_UNICOSMK
6371 while ((probed += 8192) < frame_size);
6373 /* We only have to do this probe if we aren't saving registers. */
6374 if (sa_size == 0 && probed + 4096 < frame_size)
6375 emit_insn (gen_probe_stack (GEN_INT (-frame_size)));
6378 if (frame_size != 0)
6379 FRP (emit_insn (gen_adddi3 (stack_pointer_rtx, stack_pointer_rtx,
6380 GEN_INT (TARGET_ABI_UNICOSMK
6386 /* Here we generate code to set R22 to SP + 4096 and set R23 to the
6387 number of 8192 byte blocks to probe. We then probe each block
6388 in the loop and then set SP to the proper location. If the
6389 amount remaining is > 4096, we have to do one more probe if we
6390 are not saving any registers. */
6392 HOST_WIDE_INT blocks = (frame_size + 4096) / 8192;
6393 HOST_WIDE_INT leftover = frame_size + 4096 - blocks * 8192;
6394 rtx ptr = gen_rtx_REG (DImode, 22);
6395 rtx count = gen_rtx_REG (DImode, 23);
6398 emit_move_insn (count, GEN_INT (blocks));
6399 emit_insn (gen_adddi3 (ptr, stack_pointer_rtx,
6400 GEN_INT (TARGET_ABI_UNICOSMK ? 4096 - 64 : 4096)));
6402 /* Because of the difficulty in emitting a new basic block this
6403 late in the compilation, generate the loop as a single insn. */
6404 emit_insn (gen_prologue_stack_probe_loop (count, ptr));
6406 if (leftover > 4096 && sa_size == 0)
6408 rtx last = gen_rtx_MEM (DImode, plus_constant (ptr, -leftover));
6409 MEM_VOLATILE_P (last) = 1;
6410 emit_move_insn (last, const0_rtx);
6413 if (TARGET_ABI_WINDOWS_NT)
6415 /* For NT stack unwind (done by 'reverse execution'), it's
6416 not OK to take the result of a loop, even though the value
6417 is already in ptr, so we reload it via a single operation
6418 and subtract it to sp.
6420 Yes, that's correct -- we have to reload the whole constant
6421 into a temporary via ldah+lda then subtract from sp. */
6423 HOST_WIDE_INT lo, hi;
6424 lo = ((frame_size & 0xffff) ^ 0x8000) - 0x8000;
6425 hi = frame_size - lo;
6427 emit_move_insn (ptr, GEN_INT (hi));
6428 emit_insn (gen_adddi3 (ptr, ptr, GEN_INT (lo)));
6429 seq = emit_insn (gen_subdi3 (stack_pointer_rtx, stack_pointer_rtx,
6434 seq = emit_insn (gen_adddi3 (stack_pointer_rtx, ptr,
6435 GEN_INT (-leftover)));
6438 /* This alternative is special, because the DWARF code cannot
6439 possibly intuit through the loop above. So we invent this
6440 note it looks at instead. */
6441 RTX_FRAME_RELATED_P (seq) = 1;
6443 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
6444 gen_rtx_SET (VOIDmode, stack_pointer_rtx,
6445 gen_rtx_PLUS (Pmode, stack_pointer_rtx,
6446 GEN_INT (TARGET_ABI_UNICOSMK
6452 if (!TARGET_ABI_UNICOSMK)
6454 HOST_WIDE_INT sa_bias = 0;
6456 /* Cope with very large offsets to the register save area. */
6457 sa_reg = stack_pointer_rtx;
6458 if (reg_offset + sa_size > 0x8000)
6460 int low = ((reg_offset & 0xffff) ^ 0x8000) - 0x8000;
6463 if (low + sa_size <= 0x8000)
6464 sa_bias = reg_offset - low, reg_offset = low;
6466 sa_bias = reg_offset, reg_offset = 0;
6468 sa_reg = gen_rtx_REG (DImode, 24);
6469 sa_bias_rtx = GEN_INT (sa_bias);
6471 if (add_operand (sa_bias_rtx, DImode))
6472 emit_insn (gen_adddi3 (sa_reg, stack_pointer_rtx, sa_bias_rtx));
6475 emit_move_insn (sa_reg, sa_bias_rtx);
6476 emit_insn (gen_adddi3 (sa_reg, stack_pointer_rtx, sa_reg));
6480 /* Save regs in stack order. Beginning with VMS PV. */
6481 if (TARGET_ABI_OPEN_VMS && alpha_procedure_type == PT_STACK)
6482 emit_frame_store (REG_PV, stack_pointer_rtx, 0, 0);
6484 /* Save register RA next. */
6485 if (imask & (1UL << REG_RA))
6487 emit_frame_store (REG_RA, sa_reg, sa_bias, reg_offset);
6488 imask &= ~(1UL << REG_RA);
6492 /* Now save any other registers required to be saved. */
6493 for (i = 0; i < 31; i++)
6494 if (imask & (1UL << i))
6496 emit_frame_store (i, sa_reg, sa_bias, reg_offset);
6500 for (i = 0; i < 31; i++)
6501 if (fmask & (1UL << i))
6503 emit_frame_store (i+32, sa_reg, sa_bias, reg_offset);
6507 else if (TARGET_ABI_UNICOSMK && alpha_procedure_type == PT_STACK)
6509 /* The standard frame on the T3E includes space for saving registers.
6510 We just have to use it. We don't have to save the return address and
6511 the old frame pointer here - they are saved in the DSIB. */
6514 for (i = 9; i < 15; i++)
6515 if (imask & (1UL << i))
6517 emit_frame_store (i, hard_frame_pointer_rtx, 0, reg_offset);
6520 for (i = 2; i < 10; i++)
6521 if (fmask & (1UL << i))
6523 emit_frame_store (i+32, hard_frame_pointer_rtx, 0, reg_offset);
6528 if (TARGET_ABI_OPEN_VMS)
6530 if (alpha_procedure_type == PT_REGISTER)
6531 /* Register frame procedures save the fp.
6532 ?? Ought to have a dwarf2 save for this. */
6533 emit_move_insn (gen_rtx_REG (DImode, vms_save_fp_regno),
6534 hard_frame_pointer_rtx);
6536 if (alpha_procedure_type != PT_NULL && vms_base_regno != REG_PV)
6537 emit_insn (gen_force_movdi (gen_rtx_REG (DImode, vms_base_regno),
6538 gen_rtx_REG (DImode, REG_PV)));
6540 if (alpha_procedure_type != PT_NULL
6541 && vms_unwind_regno == HARD_FRAME_POINTER_REGNUM)
6542 FRP (emit_move_insn (hard_frame_pointer_rtx, stack_pointer_rtx));
6544 /* If we have to allocate space for outgoing args, do it now. */
6545 if (current_function_outgoing_args_size != 0)
6548 = emit_move_insn (stack_pointer_rtx,
6550 (hard_frame_pointer_rtx,
6552 (current_function_outgoing_args_size))));
6554 /* Only set FRAME_RELATED_P on the stack adjustment we just emitted
6555 if ! frame_pointer_needed. Setting the bit will change the CFA
6556 computation rule to use sp again, which would be wrong if we had
6557 frame_pointer_needed, as this means sp might move unpredictably
6561 frame_pointer_needed
6562 => vms_unwind_regno == HARD_FRAME_POINTER_REGNUM
6564 current_function_outgoing_args_size != 0
6565 => alpha_procedure_type != PT_NULL,
6567 so when we are not setting the bit here, we are guaranteed to
6568 have emitted an FRP frame pointer update just before. */
6569 RTX_FRAME_RELATED_P (seq) = ! frame_pointer_needed;
6572 else if (!TARGET_ABI_UNICOSMK)
6574 /* If we need a frame pointer, set it from the stack pointer. */
6575 if (frame_pointer_needed)
6577 if (TARGET_CAN_FAULT_IN_PROLOGUE)
6578 FRP (emit_move_insn (hard_frame_pointer_rtx, stack_pointer_rtx));
6580 /* This must always be the last instruction in the
6581 prologue, thus we emit a special move + clobber. */
6582 FRP (emit_insn (gen_init_fp (hard_frame_pointer_rtx,
6583 stack_pointer_rtx, sa_reg)));
6587 /* The ABIs for VMS and OSF/1 say that while we can schedule insns into
6588 the prologue, for exception handling reasons, we cannot do this for
6589 any insn that might fault. We could prevent this for mems with a
6590 (clobber:BLK (scratch)), but this doesn't work for fp insns. So we
6591 have to prevent all such scheduling with a blockage.
6593 Linux, on the other hand, never bothered to implement OSF/1's
6594 exception handling, and so doesn't care about such things. Anyone
6595 planning to use dwarf2 frame-unwind info can also omit the blockage. */
6597 if (! TARGET_CAN_FAULT_IN_PROLOGUE)
6598 emit_insn (gen_blockage ());
6601 /* Count the number of .file directives, so that .loc is up to date. */
6602 int num_source_filenames = 0;
6604 /* Output the textual info surrounding the prologue. */
6607 alpha_start_function (FILE *file, const char *fnname,
6608 tree decl ATTRIBUTE_UNUSED)
6610 unsigned long imask = 0;
6611 unsigned long fmask = 0;
6612 /* Stack space needed for pushing registers clobbered by us. */
6613 HOST_WIDE_INT sa_size;
6614 /* Complete stack size needed. */
6615 unsigned HOST_WIDE_INT frame_size;
6616 /* Offset from base reg to register save area. */
6617 HOST_WIDE_INT reg_offset;
6618 char *entry_label = (char *) alloca (strlen (fnname) + 6);
6621 /* Don't emit an extern directive for functions defined in the same file. */
6622 if (TARGET_ABI_UNICOSMK)
6625 name_tree = get_identifier (fnname);
6626 TREE_ASM_WRITTEN (name_tree) = 1;
6629 alpha_fnname = fnname;
6630 sa_size = alpha_sa_size ();
6632 frame_size = get_frame_size ();
6633 if (TARGET_ABI_OPEN_VMS)
6634 frame_size = ALPHA_ROUND (sa_size
6635 + (alpha_procedure_type == PT_STACK ? 8 : 0)
6637 + current_function_pretend_args_size);
6638 else if (TARGET_ABI_UNICOSMK)
6639 frame_size = ALPHA_ROUND (sa_size
6640 + (alpha_procedure_type == PT_STACK ? 48 : 0))
6641 + ALPHA_ROUND (frame_size
6642 + current_function_outgoing_args_size);
6644 frame_size = (ALPHA_ROUND (current_function_outgoing_args_size)
6646 + ALPHA_ROUND (frame_size
6647 + current_function_pretend_args_size));
6649 if (TARGET_ABI_OPEN_VMS)
6652 reg_offset = ALPHA_ROUND (current_function_outgoing_args_size);
6654 alpha_sa_mask (&imask, &fmask);
6656 /* Ecoff can handle multiple .file directives, so put out file and lineno.
6657 We have to do that before the .ent directive as we cannot switch
6658 files within procedures with native ecoff because line numbers are
6659 linked to procedure descriptors.
6660 Outputting the lineno helps debugging of one line functions as they
6661 would otherwise get no line number at all. Please note that we would
6662 like to put out last_linenum from final.c, but it is not accessible. */
6664 if (write_symbols == SDB_DEBUG)
6666 #ifdef ASM_OUTPUT_SOURCE_FILENAME
6667 ASM_OUTPUT_SOURCE_FILENAME (file,
6668 DECL_SOURCE_FILE (current_function_decl));
6670 #ifdef SDB_OUTPUT_SOURCE_LINE
6671 if (debug_info_level != DINFO_LEVEL_TERSE)
6672 SDB_OUTPUT_SOURCE_LINE (file,
6673 DECL_SOURCE_LINE (current_function_decl));
6677 /* Issue function start and label. */
6678 if (TARGET_ABI_OPEN_VMS
6679 || (!TARGET_ABI_UNICOSMK && !flag_inhibit_size_directive))
6681 fputs ("\t.ent ", file);
6682 assemble_name (file, fnname);
6685 /* If the function needs GP, we'll write the "..ng" label there.
6686 Otherwise, do it here. */
6688 && ! alpha_function_needs_gp
6689 && ! current_function_is_thunk)
6692 assemble_name (file, fnname);
6693 fputs ("..ng:\n", file);
6697 strcpy (entry_label, fnname);
6698 if (TARGET_ABI_OPEN_VMS)
6699 strcat (entry_label, "..en");
6701 /* For public functions, the label must be globalized by appending an
6702 additional colon. */
6703 if (TARGET_ABI_UNICOSMK && TREE_PUBLIC (decl))
6704 strcat (entry_label, ":");
6706 ASM_OUTPUT_LABEL (file, entry_label);
6707 inside_function = TRUE;
6709 if (TARGET_ABI_OPEN_VMS)
6710 fprintf (file, "\t.base $%d\n", vms_base_regno);
6712 if (!TARGET_ABI_OPEN_VMS && !TARGET_ABI_UNICOSMK && TARGET_IEEE_CONFORMANT
6713 && !flag_inhibit_size_directive)
6715 /* Set flags in procedure descriptor to request IEEE-conformant
6716 math-library routines. The value we set it to is PDSC_EXC_IEEE
6717 (/usr/include/pdsc.h). */
6718 fputs ("\t.eflag 48\n", file);
6721 /* Set up offsets to alpha virtual arg/local debugging pointer. */
6722 alpha_auto_offset = -frame_size + current_function_pretend_args_size;
6723 alpha_arg_offset = -frame_size + 48;
6725 /* Describe our frame. If the frame size is larger than an integer,
6726 print it as zero to avoid an assembler error. We won't be
6727 properly describing such a frame, but that's the best we can do. */
6728 if (TARGET_ABI_UNICOSMK)
6730 else if (TARGET_ABI_OPEN_VMS)
6731 fprintf (file, "\t.frame $%d," HOST_WIDE_INT_PRINT_DEC ",$26,"
6732 HOST_WIDE_INT_PRINT_DEC "\n",
6734 frame_size >= (1UL << 31) ? 0 : frame_size,
6736 else if (!flag_inhibit_size_directive)
6737 fprintf (file, "\t.frame $%d," HOST_WIDE_INT_PRINT_DEC ",$26,%d\n",
6738 (frame_pointer_needed
6739 ? HARD_FRAME_POINTER_REGNUM : STACK_POINTER_REGNUM),
6740 frame_size >= (1UL << 31) ? 0 : frame_size,
6741 current_function_pretend_args_size);
6743 /* Describe which registers were spilled. */
6744 if (TARGET_ABI_UNICOSMK)
6746 else if (TARGET_ABI_OPEN_VMS)
6749 /* ??? Does VMS care if mask contains ra? The old code didn't
6750 set it, so I don't here. */
6751 fprintf (file, "\t.mask 0x%lx,0\n", imask & ~(1UL << REG_RA));
6753 fprintf (file, "\t.fmask 0x%lx,0\n", fmask);
6754 if (alpha_procedure_type == PT_REGISTER)
6755 fprintf (file, "\t.fp_save $%d\n", vms_save_fp_regno);
6757 else if (!flag_inhibit_size_directive)
6761 fprintf (file, "\t.mask 0x%lx," HOST_WIDE_INT_PRINT_DEC "\n", imask,
6762 frame_size >= (1UL << 31) ? 0 : reg_offset - frame_size);
6764 for (i = 0; i < 32; ++i)
6765 if (imask & (1UL << i))
6770 fprintf (file, "\t.fmask 0x%lx," HOST_WIDE_INT_PRINT_DEC "\n", fmask,
6771 frame_size >= (1UL << 31) ? 0 : reg_offset - frame_size);
6774 #if TARGET_ABI_OPEN_VMS
6775 /* Ifdef'ed cause link_section are only available then. */
6776 readonly_data_section ();
6777 fprintf (file, "\t.align 3\n");
6778 assemble_name (file, fnname); fputs ("..na:\n", file);
6779 fputs ("\t.ascii \"", file);
6780 assemble_name (file, fnname);
6781 fputs ("\\0\"\n", file);
6782 alpha_need_linkage (fnname, 1);
6787 /* Emit the .prologue note at the scheduled end of the prologue. */
6790 alpha_output_function_end_prologue (FILE *file)
6792 if (TARGET_ABI_UNICOSMK)
6794 else if (TARGET_ABI_OPEN_VMS)
6795 fputs ("\t.prologue\n", file);
6796 else if (TARGET_ABI_WINDOWS_NT)
6797 fputs ("\t.prologue 0\n", file);
6798 else if (!flag_inhibit_size_directive)
6799 fprintf (file, "\t.prologue %d\n",
6800 alpha_function_needs_gp || current_function_is_thunk);
6803 /* Write function epilogue. */
6805 /* ??? At some point we will want to support full unwind, and so will
6806 need to mark the epilogue as well. At the moment, we just confuse
6809 #define FRP(exp) exp
6812 alpha_expand_epilogue (void)
6814 /* Registers to save. */
6815 unsigned long imask = 0;
6816 unsigned long fmask = 0;
6817 /* Stack space needed for pushing registers clobbered by us. */
6818 HOST_WIDE_INT sa_size;
6819 /* Complete stack size needed. */
6820 HOST_WIDE_INT frame_size;
6821 /* Offset from base reg to register save area. */
6822 HOST_WIDE_INT reg_offset;
6823 int fp_is_frame_pointer, fp_offset;
6824 rtx sa_reg, sa_reg_exp = NULL;
6825 rtx sp_adj1, sp_adj2, mem;
6829 sa_size = alpha_sa_size ();
6831 frame_size = get_frame_size ();
6832 if (TARGET_ABI_OPEN_VMS)
6833 frame_size = ALPHA_ROUND (sa_size
6834 + (alpha_procedure_type == PT_STACK ? 8 : 0)
6836 + current_function_pretend_args_size);
6837 else if (TARGET_ABI_UNICOSMK)
6838 frame_size = ALPHA_ROUND (sa_size
6839 + (alpha_procedure_type == PT_STACK ? 48 : 0))
6840 + ALPHA_ROUND (frame_size
6841 + current_function_outgoing_args_size);
6843 frame_size = (ALPHA_ROUND (current_function_outgoing_args_size)
6845 + ALPHA_ROUND (frame_size
6846 + current_function_pretend_args_size));
6848 if (TARGET_ABI_OPEN_VMS)
6850 if (alpha_procedure_type == PT_STACK)
6856 reg_offset = ALPHA_ROUND (current_function_outgoing_args_size);
6858 alpha_sa_mask (&imask, &fmask);
6861 = ((TARGET_ABI_OPEN_VMS && alpha_procedure_type == PT_STACK)
6862 || (!TARGET_ABI_OPEN_VMS && frame_pointer_needed));
6864 sa_reg = stack_pointer_rtx;
6866 if (current_function_calls_eh_return)
6867 eh_ofs = EH_RETURN_STACKADJ_RTX;
6871 if (!TARGET_ABI_UNICOSMK && sa_size)
6873 /* If we have a frame pointer, restore SP from it. */
6874 if ((TARGET_ABI_OPEN_VMS
6875 && vms_unwind_regno == HARD_FRAME_POINTER_REGNUM)
6876 || (!TARGET_ABI_OPEN_VMS && frame_pointer_needed))
6877 FRP (emit_move_insn (stack_pointer_rtx, hard_frame_pointer_rtx));
6879 /* Cope with very large offsets to the register save area. */
6880 if (reg_offset + sa_size > 0x8000)
6882 int low = ((reg_offset & 0xffff) ^ 0x8000) - 0x8000;
6885 if (low + sa_size <= 0x8000)
6886 bias = reg_offset - low, reg_offset = low;
6888 bias = reg_offset, reg_offset = 0;
6890 sa_reg = gen_rtx_REG (DImode, 22);
6891 sa_reg_exp = plus_constant (stack_pointer_rtx, bias);
6893 FRP (emit_move_insn (sa_reg, sa_reg_exp));
6896 /* Restore registers in order, excepting a true frame pointer. */
6898 mem = gen_rtx_MEM (DImode, plus_constant (sa_reg, reg_offset));
6900 set_mem_alias_set (mem, alpha_sr_alias_set);
6901 FRP (emit_move_insn (gen_rtx_REG (DImode, REG_RA), mem));
6904 imask &= ~(1UL << REG_RA);
6906 for (i = 0; i < 31; ++i)
6907 if (imask & (1UL << i))
6909 if (i == HARD_FRAME_POINTER_REGNUM && fp_is_frame_pointer)
6910 fp_offset = reg_offset;
6913 mem = gen_rtx_MEM (DImode, plus_constant(sa_reg, reg_offset));
6914 set_mem_alias_set (mem, alpha_sr_alias_set);
6915 FRP (emit_move_insn (gen_rtx_REG (DImode, i), mem));
6920 for (i = 0; i < 31; ++i)
6921 if (fmask & (1UL << i))
6923 mem = gen_rtx_MEM (DFmode, plus_constant(sa_reg, reg_offset));
6924 set_mem_alias_set (mem, alpha_sr_alias_set);
6925 FRP (emit_move_insn (gen_rtx_REG (DFmode, i+32), mem));
6929 else if (TARGET_ABI_UNICOSMK && alpha_procedure_type == PT_STACK)
6931 /* Restore callee-saved general-purpose registers. */
6935 for (i = 9; i < 15; i++)
6936 if (imask & (1UL << i))
6938 mem = gen_rtx_MEM (DImode, plus_constant(hard_frame_pointer_rtx,
6940 set_mem_alias_set (mem, alpha_sr_alias_set);
6941 FRP (emit_move_insn (gen_rtx_REG (DImode, i), mem));
6945 for (i = 2; i < 10; i++)
6946 if (fmask & (1UL << i))
6948 mem = gen_rtx_MEM (DFmode, plus_constant(hard_frame_pointer_rtx,
6950 set_mem_alias_set (mem, alpha_sr_alias_set);
6951 FRP (emit_move_insn (gen_rtx_REG (DFmode, i+32), mem));
6955 /* Restore the return address from the DSIB. */
6957 mem = gen_rtx_MEM (DImode, plus_constant(hard_frame_pointer_rtx, -8));
6958 set_mem_alias_set (mem, alpha_sr_alias_set);
6959 FRP (emit_move_insn (gen_rtx_REG (DImode, REG_RA), mem));
6962 if (frame_size || eh_ofs)
6964 sp_adj1 = stack_pointer_rtx;
6968 sp_adj1 = gen_rtx_REG (DImode, 23);
6969 emit_move_insn (sp_adj1,
6970 gen_rtx_PLUS (Pmode, stack_pointer_rtx, eh_ofs));
6973 /* If the stack size is large, begin computation into a temporary
6974 register so as not to interfere with a potential fp restore,
6975 which must be consecutive with an SP restore. */
6976 if (frame_size < 32768
6977 && ! (TARGET_ABI_UNICOSMK && current_function_calls_alloca))
6978 sp_adj2 = GEN_INT (frame_size);
6979 else if (TARGET_ABI_UNICOSMK)
6981 sp_adj1 = gen_rtx_REG (DImode, 23);
6982 FRP (emit_move_insn (sp_adj1, hard_frame_pointer_rtx));
6983 sp_adj2 = const0_rtx;
6985 else if (frame_size < 0x40007fffL)
6987 int low = ((frame_size & 0xffff) ^ 0x8000) - 0x8000;
6989 sp_adj2 = plus_constant (sp_adj1, frame_size - low);
6990 if (sa_reg_exp && rtx_equal_p (sa_reg_exp, sp_adj2))
6994 sp_adj1 = gen_rtx_REG (DImode, 23);
6995 FRP (emit_move_insn (sp_adj1, sp_adj2));
6997 sp_adj2 = GEN_INT (low);
7001 rtx tmp = gen_rtx_REG (DImode, 23);
7002 FRP (sp_adj2 = alpha_emit_set_const (tmp, DImode, frame_size, 3));
7005 /* We can't drop new things to memory this late, afaik,
7006 so build it up by pieces. */
7007 FRP (sp_adj2 = alpha_emit_set_long_const (tmp, frame_size,
7008 -(frame_size < 0)));
7014 /* From now on, things must be in order. So emit blockages. */
7016 /* Restore the frame pointer. */
7017 if (TARGET_ABI_UNICOSMK)
7019 emit_insn (gen_blockage ());
7020 mem = gen_rtx_MEM (DImode,
7021 plus_constant (hard_frame_pointer_rtx, -16));
7022 set_mem_alias_set (mem, alpha_sr_alias_set);
7023 FRP (emit_move_insn (hard_frame_pointer_rtx, mem));
7025 else if (fp_is_frame_pointer)
7027 emit_insn (gen_blockage ());
7028 mem = gen_rtx_MEM (DImode, plus_constant (sa_reg, fp_offset));
7029 set_mem_alias_set (mem, alpha_sr_alias_set);
7030 FRP (emit_move_insn (hard_frame_pointer_rtx, mem));
7032 else if (TARGET_ABI_OPEN_VMS)
7034 emit_insn (gen_blockage ());
7035 FRP (emit_move_insn (hard_frame_pointer_rtx,
7036 gen_rtx_REG (DImode, vms_save_fp_regno)));
7039 /* Restore the stack pointer. */
7040 emit_insn (gen_blockage ());
7041 if (sp_adj2 == const0_rtx)
7042 FRP (emit_move_insn (stack_pointer_rtx, sp_adj1));
7044 FRP (emit_move_insn (stack_pointer_rtx,
7045 gen_rtx_PLUS (DImode, sp_adj1, sp_adj2)));
7049 if (TARGET_ABI_OPEN_VMS && alpha_procedure_type == PT_REGISTER)
7051 emit_insn (gen_blockage ());
7052 FRP (emit_move_insn (hard_frame_pointer_rtx,
7053 gen_rtx_REG (DImode, vms_save_fp_regno)));
7055 else if (TARGET_ABI_UNICOSMK && alpha_procedure_type != PT_STACK)
7057 /* Decrement the frame pointer if the function does not have a
7060 emit_insn (gen_blockage ());
7061 FRP (emit_insn (gen_adddi3 (hard_frame_pointer_rtx,
7062 hard_frame_pointer_rtx, constm1_rtx)));
7067 /* Output the rest of the textual info surrounding the epilogue. */
7070 alpha_end_function (FILE *file, const char *fnname, tree decl ATTRIBUTE_UNUSED)
7072 #if TARGET_ABI_OPEN_VMS
7073 alpha_write_linkage (file, fnname, decl);
7076 /* End the function. */
7077 if (!TARGET_ABI_UNICOSMK && !flag_inhibit_size_directive)
7079 fputs ("\t.end ", file);
7080 assemble_name (file, fnname);
7083 inside_function = FALSE;
7085 /* Output jump tables and the static subroutine information block. */
7086 if (TARGET_ABI_UNICOSMK)
7088 unicosmk_output_ssib (file, fnname);
7089 unicosmk_output_deferred_case_vectors (file);
7094 /* Emit a tail call to FUNCTION after adjusting THIS by DELTA.
7096 In order to avoid the hordes of differences between generated code
7097 with and without TARGET_EXPLICIT_RELOCS, and to avoid duplicating
7098 lots of code loading up large constants, generate rtl and emit it
7099 instead of going straight to text.
7101 Not sure why this idea hasn't been explored before... */
7104 alpha_output_mi_thunk_osf (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED,
7105 HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset,
7108 HOST_WIDE_INT hi, lo;
7109 rtx this, insn, funexp;
7111 reset_block_changes ();
7113 /* We always require a valid GP. */
7114 emit_insn (gen_prologue_ldgp ());
7115 emit_note (NOTE_INSN_PROLOGUE_END);
7117 /* Find the "this" pointer. If the function returns a structure,
7118 the structure return pointer is in $16. */
7119 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function))
7120 this = gen_rtx_REG (Pmode, 17);
7122 this = gen_rtx_REG (Pmode, 16);
7124 /* Add DELTA. When possible we use ldah+lda. Otherwise load the
7125 entire constant for the add. */
7126 lo = ((delta & 0xffff) ^ 0x8000) - 0x8000;
7127 hi = (((delta - lo) & 0xffffffff) ^ 0x80000000) - 0x80000000;
7128 if (hi + lo == delta)
7131 emit_insn (gen_adddi3 (this, this, GEN_INT (hi)));
7133 emit_insn (gen_adddi3 (this, this, GEN_INT (lo)));
7137 rtx tmp = alpha_emit_set_long_const (gen_rtx_REG (Pmode, 0),
7138 delta, -(delta < 0));
7139 emit_insn (gen_adddi3 (this, this, tmp));
7142 /* Add a delta stored in the vtable at VCALL_OFFSET. */
7147 tmp = gen_rtx_REG (Pmode, 0);
7148 emit_move_insn (tmp, gen_rtx_MEM (Pmode, this));
7150 lo = ((vcall_offset & 0xffff) ^ 0x8000) - 0x8000;
7151 hi = (((vcall_offset - lo) & 0xffffffff) ^ 0x80000000) - 0x80000000;
7152 if (hi + lo == vcall_offset)
7155 emit_insn (gen_adddi3 (tmp, tmp, GEN_INT (hi)));
7159 tmp2 = alpha_emit_set_long_const (gen_rtx_REG (Pmode, 1),
7160 vcall_offset, -(vcall_offset < 0));
7161 emit_insn (gen_adddi3 (tmp, tmp, tmp2));
7165 tmp2 = gen_rtx_PLUS (Pmode, tmp, GEN_INT (lo));
7168 emit_move_insn (tmp, gen_rtx_MEM (Pmode, tmp2));
7170 emit_insn (gen_adddi3 (this, this, tmp));
7173 /* Generate a tail call to the target function. */
7174 if (! TREE_USED (function))
7176 assemble_external (function);
7177 TREE_USED (function) = 1;
7179 funexp = XEXP (DECL_RTL (function), 0);
7180 funexp = gen_rtx_MEM (FUNCTION_MODE, funexp);
7181 insn = emit_call_insn (gen_sibcall (funexp, const0_rtx));
7182 SIBLING_CALL_P (insn) = 1;
7184 /* Run just enough of rest_of_compilation to get the insns emitted.
7185 There's not really enough bulk here to make other passes such as
7186 instruction scheduling worth while. Note that use_thunk calls
7187 assemble_start_function and assemble_end_function. */
7188 insn = get_insns ();
7189 insn_locators_initialize ();
7190 shorten_branches (insn);
7191 final_start_function (insn, file, 1);
7192 final (insn, file, 1, 0);
7193 final_end_function ();
7195 #endif /* TARGET_ABI_OSF */
7197 /* Debugging support. */
7201 /* Count the number of sdb related labels are generated (to find block
7202 start and end boundaries). */
7204 int sdb_label_count = 0;
7206 /* Name of the file containing the current function. */
7208 static const char *current_function_file = "";
7210 /* Offsets to alpha virtual arg/local debugging pointers. */
7212 long alpha_arg_offset;
7213 long alpha_auto_offset;
7215 /* Emit a new filename to a stream. */
7218 alpha_output_filename (FILE *stream, const char *name)
7220 static int first_time = TRUE;
7225 ++num_source_filenames;
7226 current_function_file = name;
7227 fprintf (stream, "\t.file\t%d ", num_source_filenames);
7228 output_quoted_string (stream, name);
7229 fprintf (stream, "\n");
7230 if (!TARGET_GAS && write_symbols == DBX_DEBUG)
7231 fprintf (stream, "\t#@stabs\n");
7234 else if (write_symbols == DBX_DEBUG)
7235 /* dbxout.c will emit an appropriate .stabs directive. */
7238 else if (name != current_function_file
7239 && strcmp (name, current_function_file) != 0)
7241 if (inside_function && ! TARGET_GAS)
7242 fprintf (stream, "\t#.file\t%d ", num_source_filenames);
7245 ++num_source_filenames;
7246 current_function_file = name;
7247 fprintf (stream, "\t.file\t%d ", num_source_filenames);
7250 output_quoted_string (stream, name);
7251 fprintf (stream, "\n");
7255 /* Structure to show the current status of registers and memory. */
7257 struct shadow_summary
7260 unsigned int i : 31; /* Mask of int regs */
7261 unsigned int fp : 31; /* Mask of fp regs */
7262 unsigned int mem : 1; /* mem == imem | fpmem */
7266 /* Summary the effects of expression X on the machine. Update SUM, a pointer
7267 to the summary structure. SET is nonzero if the insn is setting the
7268 object, otherwise zero. */
7271 summarize_insn (rtx x, struct shadow_summary *sum, int set)
7273 const char *format_ptr;
7279 switch (GET_CODE (x))
7281 /* ??? Note that this case would be incorrect if the Alpha had a
7282 ZERO_EXTRACT in SET_DEST. */
7284 summarize_insn (SET_SRC (x), sum, 0);
7285 summarize_insn (SET_DEST (x), sum, 1);
7289 summarize_insn (XEXP (x, 0), sum, 1);
7293 summarize_insn (XEXP (x, 0), sum, 0);
7297 for (i = ASM_OPERANDS_INPUT_LENGTH (x) - 1; i >= 0; i--)
7298 summarize_insn (ASM_OPERANDS_INPUT (x, i), sum, 0);
7302 for (i = XVECLEN (x, 0) - 1; i >= 0; i--)
7303 summarize_insn (XVECEXP (x, 0, i), sum, 0);
7307 summarize_insn (SUBREG_REG (x), sum, 0);
7312 int regno = REGNO (x);
7313 unsigned long mask = ((unsigned long) 1) << (regno % 32);
7315 if (regno == 31 || regno == 63)
7321 sum->defd.i |= mask;
7323 sum->defd.fp |= mask;
7328 sum->used.i |= mask;
7330 sum->used.fp |= mask;
7341 /* Find the regs used in memory address computation: */
7342 summarize_insn (XEXP (x, 0), sum, 0);
7345 case CONST_INT: case CONST_DOUBLE:
7346 case SYMBOL_REF: case LABEL_REF: case CONST:
7347 case SCRATCH: case ASM_INPUT:
7350 /* Handle common unary and binary ops for efficiency. */
7351 case COMPARE: case PLUS: case MINUS: case MULT: case DIV:
7352 case MOD: case UDIV: case UMOD: case AND: case IOR:
7353 case XOR: case ASHIFT: case ROTATE: case ASHIFTRT: case LSHIFTRT:
7354 case ROTATERT: case SMIN: case SMAX: case UMIN: case UMAX:
7355 case NE: case EQ: case GE: case GT: case LE:
7356 case LT: case GEU: case GTU: case LEU: case LTU:
7357 summarize_insn (XEXP (x, 0), sum, 0);
7358 summarize_insn (XEXP (x, 1), sum, 0);
7361 case NEG: case NOT: case SIGN_EXTEND: case ZERO_EXTEND:
7362 case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE: case FLOAT:
7363 case FIX: case UNSIGNED_FLOAT: case UNSIGNED_FIX: case ABS:
7364 case SQRT: case FFS:
7365 summarize_insn (XEXP (x, 0), sum, 0);
7369 format_ptr = GET_RTX_FORMAT (GET_CODE (x));
7370 for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
7371 switch (format_ptr[i])
7374 summarize_insn (XEXP (x, i), sum, 0);
7378 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
7379 summarize_insn (XVECEXP (x, i, j), sum, 0);
7391 /* Ensure a sufficient number of `trapb' insns are in the code when
7392 the user requests code with a trap precision of functions or
7395 In naive mode, when the user requests a trap-precision of
7396 "instruction", a trapb is needed after every instruction that may
7397 generate a trap. This ensures that the code is resumption safe but
7400 When optimizations are turned on, we delay issuing a trapb as long
7401 as possible. In this context, a trap shadow is the sequence of
7402 instructions that starts with a (potentially) trap generating
7403 instruction and extends to the next trapb or call_pal instruction
7404 (but GCC never generates call_pal by itself). We can delay (and
7405 therefore sometimes omit) a trapb subject to the following
7408 (a) On entry to the trap shadow, if any Alpha register or memory
7409 location contains a value that is used as an operand value by some
7410 instruction in the trap shadow (live on entry), then no instruction
7411 in the trap shadow may modify the register or memory location.
7413 (b) Within the trap shadow, the computation of the base register
7414 for a memory load or store instruction may not involve using the
7415 result of an instruction that might generate an UNPREDICTABLE
7418 (c) Within the trap shadow, no register may be used more than once
7419 as a destination register. (This is to make life easier for the
7422 (d) The trap shadow may not include any branch instructions. */
7425 alpha_handle_trap_shadows (void)
7427 struct shadow_summary shadow;
7428 int trap_pending, exception_nesting;
7432 exception_nesting = 0;
7435 shadow.used.mem = 0;
7436 shadow.defd = shadow.used;
7438 for (i = get_insns (); i ; i = NEXT_INSN (i))
7440 if (GET_CODE (i) == NOTE)
7442 switch (NOTE_LINE_NUMBER (i))
7444 case NOTE_INSN_EH_REGION_BEG:
7445 exception_nesting++;
7450 case NOTE_INSN_EH_REGION_END:
7451 exception_nesting--;
7456 case NOTE_INSN_EPILOGUE_BEG:
7457 if (trap_pending && alpha_tp >= ALPHA_TP_FUNC)
7462 else if (trap_pending)
7464 if (alpha_tp == ALPHA_TP_FUNC)
7466 if (GET_CODE (i) == JUMP_INSN
7467 && GET_CODE (PATTERN (i)) == RETURN)
7470 else if (alpha_tp == ALPHA_TP_INSN)
7474 struct shadow_summary sum;
7479 sum.defd = sum.used;
7481 switch (GET_CODE (i))
7484 /* Annoyingly, get_attr_trap will abort on these. */
7485 if (GET_CODE (PATTERN (i)) == USE
7486 || GET_CODE (PATTERN (i)) == CLOBBER)
7489 summarize_insn (PATTERN (i), &sum, 0);
7491 if ((sum.defd.i & shadow.defd.i)
7492 || (sum.defd.fp & shadow.defd.fp))
7494 /* (c) would be violated */
7498 /* Combine shadow with summary of current insn: */
7499 shadow.used.i |= sum.used.i;
7500 shadow.used.fp |= sum.used.fp;
7501 shadow.used.mem |= sum.used.mem;
7502 shadow.defd.i |= sum.defd.i;
7503 shadow.defd.fp |= sum.defd.fp;
7504 shadow.defd.mem |= sum.defd.mem;
7506 if ((sum.defd.i & shadow.used.i)
7507 || (sum.defd.fp & shadow.used.fp)
7508 || (sum.defd.mem & shadow.used.mem))
7510 /* (a) would be violated (also takes care of (b)) */
7511 if (get_attr_trap (i) == TRAP_YES
7512 && ((sum.defd.i & sum.used.i)
7513 || (sum.defd.fp & sum.used.fp)))
7532 n = emit_insn_before (gen_trapb (), i);
7533 PUT_MODE (n, TImode);
7534 PUT_MODE (i, TImode);
7538 shadow.used.mem = 0;
7539 shadow.defd = shadow.used;
7544 if ((exception_nesting > 0 || alpha_tp >= ALPHA_TP_FUNC)
7545 && GET_CODE (i) == INSN
7546 && GET_CODE (PATTERN (i)) != USE
7547 && GET_CODE (PATTERN (i)) != CLOBBER
7548 && get_attr_trap (i) == TRAP_YES)
7550 if (optimize && !trap_pending)
7551 summarize_insn (PATTERN (i), &shadow, 0);
7557 /* Alpha can only issue instruction groups simultaneously if they are
7558 suitably aligned. This is very processor-specific. */
7560 enum alphaev4_pipe {
7567 enum alphaev5_pipe {
7578 static enum alphaev4_pipe
7579 alphaev4_insn_pipe (rtx insn)
7581 if (recog_memoized (insn) < 0)
7583 if (get_attr_length (insn) != 4)
7586 switch (get_attr_type (insn))
7620 static enum alphaev5_pipe
7621 alphaev5_insn_pipe (rtx insn)
7623 if (recog_memoized (insn) < 0)
7625 if (get_attr_length (insn) != 4)
7628 switch (get_attr_type (insn))
7669 /* IN_USE is a mask of the slots currently filled within the insn group.
7670 The mask bits come from alphaev4_pipe above. If EV4_IBX is set, then
7671 the insn in EV4_IB0 can be swapped by the hardware into EV4_IB1.
7673 LEN is, of course, the length of the group in bytes. */
7676 alphaev4_next_group (rtx insn, int *pin_use, int *plen)
7683 || GET_CODE (PATTERN (insn)) == CLOBBER
7684 || GET_CODE (PATTERN (insn)) == USE)
7689 enum alphaev4_pipe pipe;
7691 pipe = alphaev4_insn_pipe (insn);
7695 /* Force complex instructions to start new groups. */
7699 /* If this is a completely unrecognized insn, its an asm.
7700 We don't know how long it is, so record length as -1 to
7701 signal a needed realignment. */
7702 if (recog_memoized (insn) < 0)
7705 len = get_attr_length (insn);
7709 if (in_use & EV4_IB0)
7711 if (in_use & EV4_IB1)
7716 in_use |= EV4_IB0 | EV4_IBX;
7720 if (in_use & EV4_IB0)
7722 if (!(in_use & EV4_IBX) || (in_use & EV4_IB1))
7730 if (in_use & EV4_IB1)
7740 /* Haifa doesn't do well scheduling branches. */
7741 if (GET_CODE (insn) == JUMP_INSN)
7745 insn = next_nonnote_insn (insn);
7747 if (!insn || ! INSN_P (insn))
7750 /* Let Haifa tell us where it thinks insn group boundaries are. */
7751 if (GET_MODE (insn) == TImode)
7754 if (GET_CODE (insn) == CLOBBER || GET_CODE (insn) == USE)
7759 insn = next_nonnote_insn (insn);
7767 /* IN_USE is a mask of the slots currently filled within the insn group.
7768 The mask bits come from alphaev5_pipe above. If EV5_E01 is set, then
7769 the insn in EV5_E0 can be swapped by the hardware into EV5_E1.
7771 LEN is, of course, the length of the group in bytes. */
7774 alphaev5_next_group (rtx insn, int *pin_use, int *plen)
7781 || GET_CODE (PATTERN (insn)) == CLOBBER
7782 || GET_CODE (PATTERN (insn)) == USE)
7787 enum alphaev5_pipe pipe;
7789 pipe = alphaev5_insn_pipe (insn);
7793 /* Force complex instructions to start new groups. */
7797 /* If this is a completely unrecognized insn, its an asm.
7798 We don't know how long it is, so record length as -1 to
7799 signal a needed realignment. */
7800 if (recog_memoized (insn) < 0)
7803 len = get_attr_length (insn);
7806 /* ??? Most of the places below, we would like to abort, as
7807 it would indicate an error either in Haifa, or in the
7808 scheduling description. Unfortunately, Haifa never
7809 schedules the last instruction of the BB, so we don't
7810 have an accurate TI bit to go off. */
7812 if (in_use & EV5_E0)
7814 if (in_use & EV5_E1)
7819 in_use |= EV5_E0 | EV5_E01;
7823 if (in_use & EV5_E0)
7825 if (!(in_use & EV5_E01) || (in_use & EV5_E1))
7833 if (in_use & EV5_E1)
7839 if (in_use & EV5_FA)
7841 if (in_use & EV5_FM)
7846 in_use |= EV5_FA | EV5_FAM;
7850 if (in_use & EV5_FA)
7856 if (in_use & EV5_FM)
7869 /* Haifa doesn't do well scheduling branches. */
7870 /* ??? If this is predicted not-taken, slotting continues, except
7871 that no more IBR, FBR, or JSR insns may be slotted. */
7872 if (GET_CODE (insn) == JUMP_INSN)
7876 insn = next_nonnote_insn (insn);
7878 if (!insn || ! INSN_P (insn))
7881 /* Let Haifa tell us where it thinks insn group boundaries are. */
7882 if (GET_MODE (insn) == TImode)
7885 if (GET_CODE (insn) == CLOBBER || GET_CODE (insn) == USE)
7890 insn = next_nonnote_insn (insn);
7899 alphaev4_next_nop (int *pin_use)
7901 int in_use = *pin_use;
7904 if (!(in_use & EV4_IB0))
7909 else if ((in_use & (EV4_IBX|EV4_IB1)) == EV4_IBX)
7914 else if (TARGET_FP && !(in_use & EV4_IB1))
7927 alphaev5_next_nop (int *pin_use)
7929 int in_use = *pin_use;
7932 if (!(in_use & EV5_E1))
7937 else if (TARGET_FP && !(in_use & EV5_FA))
7942 else if (TARGET_FP && !(in_use & EV5_FM))
7954 /* The instruction group alignment main loop. */
7957 alpha_align_insns (unsigned int max_align,
7958 rtx (*next_group) (rtx, int *, int *),
7959 rtx (*next_nop) (int *))
7961 /* ALIGN is the known alignment for the insn group. */
7963 /* OFS is the offset of the current insn in the insn group. */
7965 int prev_in_use, in_use, len;
7968 /* Let shorten branches care for assigning alignments to code labels. */
7969 shorten_branches (get_insns ());
7971 if (align_functions < 4)
7973 else if ((unsigned int) align_functions < max_align)
7974 align = align_functions;
7978 ofs = prev_in_use = 0;
7980 if (GET_CODE (i) == NOTE)
7981 i = next_nonnote_insn (i);
7985 next = (*next_group) (i, &in_use, &len);
7987 /* When we see a label, resync alignment etc. */
7988 if (GET_CODE (i) == CODE_LABEL)
7990 unsigned int new_align = 1 << label_to_alignment (i);
7992 if (new_align >= align)
7994 align = new_align < max_align ? new_align : max_align;
7998 else if (ofs & (new_align-1))
7999 ofs = (ofs | (new_align-1)) + 1;
8004 /* Handle complex instructions special. */
8005 else if (in_use == 0)
8007 /* Asms will have length < 0. This is a signal that we have
8008 lost alignment knowledge. Assume, however, that the asm
8009 will not mis-align instructions. */
8018 /* If the known alignment is smaller than the recognized insn group,
8019 realign the output. */
8020 else if ((int) align < len)
8022 unsigned int new_log_align = len > 8 ? 4 : 3;
8025 where = prev = prev_nonnote_insn (i);
8026 if (!where || GET_CODE (where) != CODE_LABEL)
8029 /* Can't realign between a call and its gp reload. */
8030 if (! (TARGET_EXPLICIT_RELOCS
8031 && prev && GET_CODE (prev) == CALL_INSN))
8033 emit_insn_before (gen_realign (GEN_INT (new_log_align)), where);
8034 align = 1 << new_log_align;
8039 /* If the group won't fit in the same INT16 as the previous,
8040 we need to add padding to keep the group together. Rather
8041 than simply leaving the insn filling to the assembler, we
8042 can make use of the knowledge of what sorts of instructions
8043 were issued in the previous group to make sure that all of
8044 the added nops are really free. */
8045 else if (ofs + len > (int) align)
8047 int nop_count = (align - ofs) / 4;
8050 /* Insert nops before labels, branches, and calls to truly merge
8051 the execution of the nops with the previous instruction group. */
8052 where = prev_nonnote_insn (i);
8055 if (GET_CODE (where) == CODE_LABEL)
8057 rtx where2 = prev_nonnote_insn (where);
8058 if (where2 && GET_CODE (where2) == JUMP_INSN)
8061 else if (GET_CODE (where) == INSN)
8068 emit_insn_before ((*next_nop)(&prev_in_use), where);
8069 while (--nop_count);
8073 ofs = (ofs + len) & (align - 1);
8074 prev_in_use = in_use;
8079 /* Machine dependent reorg pass. */
8084 if (alpha_tp != ALPHA_TP_PROG || flag_exceptions)
8085 alpha_handle_trap_shadows ();
8087 /* Due to the number of extra trapb insns, don't bother fixing up
8088 alignment when trap precision is instruction. Moreover, we can
8089 only do our job when sched2 is run. */
8090 if (optimize && !optimize_size
8091 && alpha_tp != ALPHA_TP_INSN
8092 && flag_schedule_insns_after_reload)
8094 if (alpha_cpu == PROCESSOR_EV4)
8095 alpha_align_insns (8, alphaev4_next_group, alphaev4_next_nop);
8096 else if (alpha_cpu == PROCESSOR_EV5)
8097 alpha_align_insns (16, alphaev5_next_group, alphaev5_next_nop);
8101 #if !TARGET_ABI_UNICOSMK
8108 alpha_file_start (void)
8110 #ifdef OBJECT_FORMAT_ELF
8111 /* If emitting dwarf2 debug information, we cannot generate a .file
8112 directive to start the file, as it will conflict with dwarf2out
8113 file numbers. So it's only useful when emitting mdebug output. */
8114 targetm.file_start_file_directive = (write_symbols == DBX_DEBUG);
8117 default_file_start ();
8119 fprintf (asm_out_file, "\t.verstamp %d %d\n", MS_STAMP, LS_STAMP);
8122 fputs ("\t.set noreorder\n", asm_out_file);
8123 fputs ("\t.set volatile\n", asm_out_file);
8124 if (!TARGET_ABI_OPEN_VMS)
8125 fputs ("\t.set noat\n", asm_out_file);
8126 if (TARGET_EXPLICIT_RELOCS)
8127 fputs ("\t.set nomacro\n", asm_out_file);
8128 if (TARGET_SUPPORT_ARCH | TARGET_BWX | TARGET_MAX | TARGET_FIX | TARGET_CIX)
8129 fprintf (asm_out_file,
8131 TARGET_CPU_EV6 ? "ev6"
8133 ? (TARGET_MAX ? "pca56" : TARGET_BWX ? "ev56" : "ev5")
8138 #ifdef OBJECT_FORMAT_ELF
8140 /* Switch to the section to which we should output X. The only thing
8141 special we do here is to honor small data. */
8144 alpha_elf_select_rtx_section (enum machine_mode mode, rtx x,
8145 unsigned HOST_WIDE_INT align)
8147 if (TARGET_SMALL_DATA && GET_MODE_SIZE (mode) <= g_switch_value)
8148 /* ??? Consider using mergeable sdata sections. */
8151 default_elf_select_rtx_section (mode, x, align);
8154 #endif /* OBJECT_FORMAT_ELF */
8156 /* Structure to collect function names for final output in link section. */
8157 /* Note that items marked with GTY can't be ifdef'ed out. */
8159 enum links_kind {KIND_UNUSED, KIND_LOCAL, KIND_EXTERN};
8160 enum reloc_kind {KIND_LINKAGE, KIND_CODEADDR};
8162 struct alpha_links GTY(())
8166 enum links_kind lkind;
8167 enum reloc_kind rkind;
8170 struct alpha_funcs GTY(())
8173 splay_tree GTY ((param1_is (char *), param2_is (struct alpha_links *)))
8177 static GTY ((param1_is (char *), param2_is (struct alpha_links *)))
8178 splay_tree alpha_links_tree;
8179 static GTY ((param1_is (tree), param2_is (struct alpha_funcs *)))
8180 splay_tree alpha_funcs_tree;
8182 static GTY(()) int alpha_funcs_num;
8184 #if TARGET_ABI_OPEN_VMS
8186 /* Return the VMS argument type corresponding to MODE. */
8189 alpha_arg_type (enum machine_mode mode)
8194 return TARGET_FLOAT_VAX ? FF : FS;
8196 return TARGET_FLOAT_VAX ? FD : FT;
8202 /* Return an rtx for an integer representing the VMS Argument Information
8206 alpha_arg_info_reg_val (CUMULATIVE_ARGS cum)
8208 unsigned HOST_WIDE_INT regval = cum.num_args;
8211 for (i = 0; i < 6; i++)
8212 regval |= ((int) cum.atypes[i]) << (i * 3 + 8);
8214 return GEN_INT (regval);
8217 /* Make (or fake) .linkage entry for function call.
8219 IS_LOCAL is 0 if name is used in call, 1 if name is used in definition.
8221 Return an SYMBOL_REF rtx for the linkage. */
8224 alpha_need_linkage (const char *name, int is_local)
8226 splay_tree_node node;
8227 struct alpha_links *al;
8234 struct alpha_funcs *cfaf;
8236 if (!alpha_funcs_tree)
8237 alpha_funcs_tree = splay_tree_new_ggc ((splay_tree_compare_fn)
8238 splay_tree_compare_pointers);
8240 cfaf = (struct alpha_funcs *) ggc_alloc (sizeof (struct alpha_funcs));
8243 cfaf->num = ++alpha_funcs_num;
8245 splay_tree_insert (alpha_funcs_tree,
8246 (splay_tree_key) current_function_decl,
8247 (splay_tree_value) cfaf);
8250 if (alpha_links_tree)
8252 /* Is this name already defined? */
8254 node = splay_tree_lookup (alpha_links_tree, (splay_tree_key) name);
8257 al = (struct alpha_links *) node->value;
8260 /* Defined here but external assumed. */
8261 if (al->lkind == KIND_EXTERN)
8262 al->lkind = KIND_LOCAL;
8266 /* Used here but unused assumed. */
8267 if (al->lkind == KIND_UNUSED)
8268 al->lkind = KIND_LOCAL;
8274 alpha_links_tree = splay_tree_new_ggc ((splay_tree_compare_fn) strcmp);
8276 al = (struct alpha_links *) ggc_alloc (sizeof (struct alpha_links));
8277 name = ggc_strdup (name);
8279 /* Assume external if no definition. */
8280 al->lkind = (is_local ? KIND_UNUSED : KIND_EXTERN);
8282 /* Ensure we have an IDENTIFIER so assemble_name can mark it used. */
8283 get_identifier (name);
8285 /* Construct a SYMBOL_REF for us to call. */
8287 size_t name_len = strlen (name);
8288 char *linksym = alloca (name_len + 6);
8290 memcpy (linksym + 1, name, name_len);
8291 memcpy (linksym + 1 + name_len, "..lk", 5);
8292 al->linkage = gen_rtx_SYMBOL_REF (Pmode,
8293 ggc_alloc_string (linksym, name_len + 5));
8296 splay_tree_insert (alpha_links_tree, (splay_tree_key) name,
8297 (splay_tree_value) al);
8303 alpha_use_linkage (rtx linkage, tree cfundecl, int lflag, int rflag)
8305 splay_tree_node cfunnode;
8306 struct alpha_funcs *cfaf;
8307 struct alpha_links *al;
8308 const char *name = XSTR (linkage, 0);
8310 cfaf = (struct alpha_funcs *) 0;
8311 al = (struct alpha_links *) 0;
8313 cfunnode = splay_tree_lookup (alpha_funcs_tree, (splay_tree_key) cfundecl);
8314 cfaf = (struct alpha_funcs *) cfunnode->value;
8318 splay_tree_node lnode;
8320 /* Is this name already defined? */
8322 lnode = splay_tree_lookup (cfaf->links, (splay_tree_key) name);
8324 al = (struct alpha_links *) lnode->value;
8327 cfaf->links = splay_tree_new_ggc ((splay_tree_compare_fn) strcmp);
8335 splay_tree_node node = 0;
8336 struct alpha_links *anl;
8341 name_len = strlen (name);
8343 al = (struct alpha_links *) ggc_alloc (sizeof (struct alpha_links));
8344 al->num = cfaf->num;
8346 node = splay_tree_lookup (alpha_links_tree, (splay_tree_key) name);
8349 anl = (struct alpha_links *) node->value;
8350 al->lkind = anl->lkind;
8353 sprintf (buf, "$%d..%s..lk", cfaf->num, name);
8354 buflen = strlen (buf);
8355 linksym = alloca (buflen + 1);
8356 memcpy (linksym, buf, buflen + 1);
8358 al->linkage = gen_rtx_SYMBOL_REF
8359 (Pmode, ggc_alloc_string (linksym, buflen + 1));
8361 splay_tree_insert (cfaf->links, (splay_tree_key) name,
8362 (splay_tree_value) al);
8366 al->rkind = KIND_CODEADDR;
8368 al->rkind = KIND_LINKAGE;
8371 return gen_rtx_MEM (Pmode, plus_constant (al->linkage, 8));
8377 alpha_write_one_linkage (splay_tree_node node, void *data)
8379 const char *const name = (const char *) node->key;
8380 struct alpha_links *link = (struct alpha_links *) node->value;
8381 FILE *stream = (FILE *) data;
8383 fprintf (stream, "$%d..%s..lk:\n", link->num, name);
8384 if (link->rkind == KIND_CODEADDR)
8386 if (link->lkind == KIND_LOCAL)
8388 /* Local and used */
8389 fprintf (stream, "\t.quad %s..en\n", name);
8393 /* External and used, request code address. */
8394 fprintf (stream, "\t.code_address %s\n", name);
8399 if (link->lkind == KIND_LOCAL)
8401 /* Local and used, build linkage pair. */
8402 fprintf (stream, "\t.quad %s..en\n", name);
8403 fprintf (stream, "\t.quad %s\n", name);
8407 /* External and used, request linkage pair. */
8408 fprintf (stream, "\t.linkage %s\n", name);
8416 alpha_write_linkage (FILE *stream, const char *funname, tree fundecl)
8418 splay_tree_node node;
8419 struct alpha_funcs *func;
8422 fprintf (stream, "\t.align 3\n");
8423 node = splay_tree_lookup (alpha_funcs_tree, (splay_tree_key) fundecl);
8424 func = (struct alpha_funcs *) node->value;
8426 fputs ("\t.name ", stream);
8427 assemble_name (stream, funname);
8428 fputs ("..na\n", stream);
8429 ASM_OUTPUT_LABEL (stream, funname);
8430 fprintf (stream, "\t.pdesc ");
8431 assemble_name (stream, funname);
8432 fprintf (stream, "..en,%s\n",
8433 alpha_procedure_type == PT_STACK ? "stack"
8434 : alpha_procedure_type == PT_REGISTER ? "reg" : "null");
8438 splay_tree_foreach (func->links, alpha_write_one_linkage, stream);
8439 /* splay_tree_delete (func->links); */
8443 /* Given a decl, a section name, and whether the decl initializer
8444 has relocs, choose attributes for the section. */
8446 #define SECTION_VMS_OVERLAY SECTION_FORGET
8447 #define SECTION_VMS_GLOBAL SECTION_MACH_DEP
8448 #define SECTION_VMS_INITIALIZE (SECTION_VMS_GLOBAL << 1)
8451 vms_section_type_flags (tree decl, const char *name, int reloc)
8453 unsigned int flags = default_section_type_flags (decl, name, reloc);
8455 if (decl && DECL_ATTRIBUTES (decl)
8456 && lookup_attribute ("overlaid", DECL_ATTRIBUTES (decl)))
8457 flags |= SECTION_VMS_OVERLAY;
8458 if (decl && DECL_ATTRIBUTES (decl)
8459 && lookup_attribute ("global", DECL_ATTRIBUTES (decl)))
8460 flags |= SECTION_VMS_GLOBAL;
8461 if (decl && DECL_ATTRIBUTES (decl)
8462 && lookup_attribute ("initialize", DECL_ATTRIBUTES (decl)))
8463 flags |= SECTION_VMS_INITIALIZE;
8468 /* Switch to an arbitrary section NAME with attributes as specified
8469 by FLAGS. ALIGN specifies any known alignment requirements for
8470 the section; 0 if the default should be used. */
8473 vms_asm_named_section (const char *name, unsigned int flags,
8474 tree decl ATTRIBUTE_UNUSED)
8476 fputc ('\n', asm_out_file);
8477 fprintf (asm_out_file, ".section\t%s", name);
8479 if (flags & SECTION_VMS_OVERLAY)
8480 fprintf (asm_out_file, ",OVR");
8481 if (flags & SECTION_VMS_GLOBAL)
8482 fprintf (asm_out_file, ",GBL");
8483 if (flags & SECTION_VMS_INITIALIZE)
8484 fprintf (asm_out_file, ",NOMOD");
8485 if (flags & SECTION_DEBUG)
8486 fprintf (asm_out_file, ",NOWRT");
8488 fputc ('\n', asm_out_file);
8491 /* Record an element in the table of global constructors. SYMBOL is
8492 a SYMBOL_REF of the function to be called; PRIORITY is a number
8493 between 0 and MAX_INIT_PRIORITY.
8495 Differs from default_ctors_section_asm_out_constructor in that the
8496 width of the .ctors entry is always 64 bits, rather than the 32 bits
8497 used by a normal pointer. */
8500 vms_asm_out_constructor (rtx symbol, int priority ATTRIBUTE_UNUSED)
8503 assemble_align (BITS_PER_WORD);
8504 assemble_integer (symbol, UNITS_PER_WORD, BITS_PER_WORD, 1);
8508 vms_asm_out_destructor (rtx symbol, int priority ATTRIBUTE_UNUSED)
8511 assemble_align (BITS_PER_WORD);
8512 assemble_integer (symbol, UNITS_PER_WORD, BITS_PER_WORD, 1);
8517 alpha_need_linkage (const char *name ATTRIBUTE_UNUSED,
8518 int is_local ATTRIBUTE_UNUSED)
8524 alpha_use_linkage (rtx linkage ATTRIBUTE_UNUSED,
8525 tree cfundecl ATTRIBUTE_UNUSED,
8526 int lflag ATTRIBUTE_UNUSED,
8527 int rflag ATTRIBUTE_UNUSED)
8532 #endif /* TARGET_ABI_OPEN_VMS */
8534 #if TARGET_ABI_UNICOSMK
8536 /* This evaluates to true if we do not know how to pass TYPE solely in
8537 registers. This is the case for all arguments that do not fit in two
8541 unicosmk_must_pass_in_stack (enum machine_mode mode, tree type)
8546 if (TREE_CODE (TYPE_SIZE (type)) != INTEGER_CST)
8548 if (TREE_ADDRESSABLE (type))
8551 return ALPHA_ARG_SIZE (mode, type, 0) > 2;
8554 /* Define the offset between two registers, one to be eliminated, and the
8555 other its replacement, at the start of a routine. */
8558 unicosmk_initial_elimination_offset (int from, int to)
8562 fixed_size = alpha_sa_size();
8563 if (fixed_size != 0)
8566 if (from == FRAME_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM)
8568 else if (from == ARG_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM)
8570 else if (from == FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
8571 return (ALPHA_ROUND (current_function_outgoing_args_size)
8572 + ALPHA_ROUND (get_frame_size()));
8573 else if (from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
8574 return (ALPHA_ROUND (fixed_size)
8575 + ALPHA_ROUND (get_frame_size()
8576 + current_function_outgoing_args_size));
8581 /* Output the module name for .ident and .end directives. We have to strip
8582 directories and add make sure that the module name starts with a letter
8586 unicosmk_output_module_name (FILE *file)
8588 const char *name = lbasename (main_input_filename);
8589 unsigned len = strlen (name);
8590 char *clean_name = alloca (len + 2);
8591 char *ptr = clean_name;
8593 /* CAM only accepts module names that start with a letter or '$'. We
8594 prefix the module name with a '$' if necessary. */
8596 if (!ISALPHA (*name))
8598 memcpy (ptr, name, len + 1);
8599 clean_symbol_name (clean_name);
8600 fputs (clean_name, file);
8603 /* Output the definition of a common variable. */
8606 unicosmk_output_common (FILE *file, const char *name, int size, int align)
8609 printf ("T3E__: common %s\n", name);
8612 fputs("\t.endp\n\n\t.psect ", file);
8613 assemble_name(file, name);
8614 fprintf(file, ",%d,common\n", floor_log2 (align / BITS_PER_UNIT));
8615 fprintf(file, "\t.byte\t0:%d\n", size);
8617 /* Mark the symbol as defined in this module. */
8618 name_tree = get_identifier (name);
8619 TREE_ASM_WRITTEN (name_tree) = 1;
8622 #define SECTION_PUBLIC SECTION_MACH_DEP
8623 #define SECTION_MAIN (SECTION_PUBLIC << 1)
8624 static int current_section_align;
8627 unicosmk_section_type_flags (tree decl, const char *name,
8628 int reloc ATTRIBUTE_UNUSED)
8630 unsigned int flags = default_section_type_flags (decl, name, reloc);
8635 if (TREE_CODE (decl) == FUNCTION_DECL)
8637 current_section_align = floor_log2 (FUNCTION_BOUNDARY / BITS_PER_UNIT);
8638 if (align_functions_log > current_section_align)
8639 current_section_align = align_functions_log;
8641 if (! strcmp (IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl)), "main"))
8642 flags |= SECTION_MAIN;
8645 current_section_align = floor_log2 (DECL_ALIGN (decl) / BITS_PER_UNIT);
8647 if (TREE_PUBLIC (decl))
8648 flags |= SECTION_PUBLIC;
8653 /* Generate a section name for decl and associate it with the
8657 unicosmk_unique_section (tree decl, int reloc ATTRIBUTE_UNUSED)
8665 name = IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl));
8666 name = default_strip_name_encoding (name);
8667 len = strlen (name);
8669 if (TREE_CODE (decl) == FUNCTION_DECL)
8673 /* It is essential that we prefix the section name here because
8674 otherwise the section names generated for constructors and
8675 destructors confuse collect2. */
8677 string = alloca (len + 6);
8678 sprintf (string, "code@%s", name);
8679 DECL_SECTION_NAME (decl) = build_string (len + 5, string);
8681 else if (TREE_PUBLIC (decl))
8682 DECL_SECTION_NAME (decl) = build_string (len, name);
8687 string = alloca (len + 6);
8688 sprintf (string, "data@%s", name);
8689 DECL_SECTION_NAME (decl) = build_string (len + 5, string);
8693 /* Switch to an arbitrary section NAME with attributes as specified
8694 by FLAGS. ALIGN specifies any known alignment requirements for
8695 the section; 0 if the default should be used. */
8698 unicosmk_asm_named_section (const char *name, unsigned int flags,
8699 tree decl ATTRIBUTE_UNUSED)
8703 /* Close the previous section. */
8705 fputs ("\t.endp\n\n", asm_out_file);
8707 /* Find out what kind of section we are opening. */
8709 if (flags & SECTION_MAIN)
8710 fputs ("\t.start\tmain\n", asm_out_file);
8712 if (flags & SECTION_CODE)
8714 else if (flags & SECTION_PUBLIC)
8719 if (current_section_align != 0)
8720 fprintf (asm_out_file, "\t.psect\t%s,%d,%s\n", name,
8721 current_section_align, kind);
8723 fprintf (asm_out_file, "\t.psect\t%s,%s\n", name, kind);
8727 unicosmk_insert_attributes (tree decl, tree *attr_ptr ATTRIBUTE_UNUSED)
8730 && (TREE_PUBLIC (decl) || TREE_CODE (decl) == FUNCTION_DECL))
8731 unicosmk_unique_section (decl, 0);
8734 /* Output an alignment directive. We have to use the macro 'gcc@code@align'
8735 in code sections because .align fill unused space with zeroes. */
8738 unicosmk_output_align (FILE *file, int align)
8740 if (inside_function)
8741 fprintf (file, "\tgcc@code@align\t%d\n", align);
8743 fprintf (file, "\t.align\t%d\n", align);
8746 /* Add a case vector to the current function's list of deferred case
8747 vectors. Case vectors have to be put into a separate section because CAM
8748 does not allow data definitions in code sections. */
8751 unicosmk_defer_case_vector (rtx lab, rtx vec)
8753 struct machine_function *machine = cfun->machine;
8755 vec = gen_rtx_EXPR_LIST (VOIDmode, lab, vec);
8756 machine->addr_list = gen_rtx_EXPR_LIST (VOIDmode, vec,
8757 machine->addr_list);
8760 /* Output a case vector. */
8763 unicosmk_output_addr_vec (FILE *file, rtx vec)
8765 rtx lab = XEXP (vec, 0);
8766 rtx body = XEXP (vec, 1);
8767 int vlen = XVECLEN (body, 0);
8770 (*targetm.asm_out.internal_label) (file, "L", CODE_LABEL_NUMBER (lab));
8772 for (idx = 0; idx < vlen; idx++)
8774 ASM_OUTPUT_ADDR_VEC_ELT
8775 (file, CODE_LABEL_NUMBER (XEXP (XVECEXP (body, 0, idx), 0)));
8779 /* Output current function's deferred case vectors. */
8782 unicosmk_output_deferred_case_vectors (FILE *file)
8784 struct machine_function *machine = cfun->machine;
8787 if (machine->addr_list == NULL_RTX)
8791 for (t = machine->addr_list; t; t = XEXP (t, 1))
8792 unicosmk_output_addr_vec (file, XEXP (t, 0));
8795 /* Generate the name of the SSIB section for the current function. */
8797 #define SSIB_PREFIX "__SSIB_"
8798 #define SSIB_PREFIX_LEN 7
8801 unicosmk_ssib_name (void)
8803 /* This is ok since CAM won't be able to deal with names longer than that
8806 static char name[256];
8812 x = DECL_RTL (cfun->decl);
8813 if (GET_CODE (x) != MEM)
8816 if (GET_CODE (x) != SYMBOL_REF)
8818 fnname = XSTR (x, 0);
8820 len = strlen (fnname);
8821 if (len + SSIB_PREFIX_LEN > 255)
8822 len = 255 - SSIB_PREFIX_LEN;
8824 strcpy (name, SSIB_PREFIX);
8825 strncpy (name + SSIB_PREFIX_LEN, fnname, len);
8826 name[len + SSIB_PREFIX_LEN] = 0;
8831 /* Set up the dynamic subprogram information block (DSIB) and update the
8832 frame pointer register ($15) for subroutines which have a frame. If the
8833 subroutine doesn't have a frame, simply increment $15. */
8836 unicosmk_gen_dsib (unsigned long *imaskP)
8838 if (alpha_procedure_type == PT_STACK)
8840 const char *ssib_name;
8843 /* Allocate 64 bytes for the DSIB. */
8845 FRP (emit_insn (gen_adddi3 (stack_pointer_rtx, stack_pointer_rtx,
8847 emit_insn (gen_blockage ());
8849 /* Save the return address. */
8851 mem = gen_rtx_MEM (DImode, plus_constant (stack_pointer_rtx, 56));
8852 set_mem_alias_set (mem, alpha_sr_alias_set);
8853 FRP (emit_move_insn (mem, gen_rtx_REG (DImode, REG_RA)));
8854 (*imaskP) &= ~(1UL << REG_RA);
8856 /* Save the old frame pointer. */
8858 mem = gen_rtx_MEM (DImode, plus_constant (stack_pointer_rtx, 48));
8859 set_mem_alias_set (mem, alpha_sr_alias_set);
8860 FRP (emit_move_insn (mem, hard_frame_pointer_rtx));
8861 (*imaskP) &= ~(1UL << HARD_FRAME_POINTER_REGNUM);
8863 emit_insn (gen_blockage ());
8865 /* Store the SSIB pointer. */
8867 ssib_name = ggc_strdup (unicosmk_ssib_name ());
8868 mem = gen_rtx_MEM (DImode, plus_constant (stack_pointer_rtx, 32));
8869 set_mem_alias_set (mem, alpha_sr_alias_set);
8871 FRP (emit_move_insn (gen_rtx_REG (DImode, 5),
8872 gen_rtx_SYMBOL_REF (Pmode, ssib_name)));
8873 FRP (emit_move_insn (mem, gen_rtx_REG (DImode, 5)));
8875 /* Save the CIW index. */
8877 mem = gen_rtx_MEM (DImode, plus_constant (stack_pointer_rtx, 24));
8878 set_mem_alias_set (mem, alpha_sr_alias_set);
8879 FRP (emit_move_insn (mem, gen_rtx_REG (DImode, 25)));
8881 emit_insn (gen_blockage ());
8883 /* Set the new frame pointer. */
8885 FRP (emit_insn (gen_adddi3 (hard_frame_pointer_rtx,
8886 stack_pointer_rtx, GEN_INT (64))));
8891 /* Increment the frame pointer register to indicate that we do not
8894 FRP (emit_insn (gen_adddi3 (hard_frame_pointer_rtx,
8895 hard_frame_pointer_rtx, const1_rtx)));
8899 /* Output the static subroutine information block for the current
8903 unicosmk_output_ssib (FILE *file, const char *fnname)
8909 struct machine_function *machine = cfun->machine;
8912 fprintf (file, "\t.endp\n\n\t.psect\t%s%s,data\n", user_label_prefix,
8913 unicosmk_ssib_name ());
8915 /* Some required stuff and the function name length. */
8917 len = strlen (fnname);
8918 fprintf (file, "\t.quad\t^X20008%2.2X28\n", len);
8921 ??? We don't do that yet. */
8923 fputs ("\t.quad\t0\n", file);
8925 /* Function address. */
8927 fputs ("\t.quad\t", file);
8928 assemble_name (file, fnname);
8931 fputs ("\t.quad\t0\n", file);
8932 fputs ("\t.quad\t0\n", file);
8935 ??? We do it the same way Cray CC does it but this could be
8938 for( i = 0; i < len; i++ )
8939 fprintf (file, "\t.byte\t%d\n", (int)(fnname[i]));
8940 if( (len % 8) == 0 )
8941 fputs ("\t.quad\t0\n", file);
8943 fprintf (file, "\t.bits\t%d : 0\n", (8 - (len % 8))*8);
8945 /* All call information words used in the function. */
8947 for (x = machine->first_ciw; x; x = XEXP (x, 1))
8950 #if HOST_BITS_PER_WIDE_INT == 32
8951 fprintf (file, "\t.quad\t" HOST_WIDE_INT_PRINT_DOUBLE_HEX "\n",
8952 CONST_DOUBLE_HIGH (ciw), CONST_DOUBLE_LOW (ciw));
8954 fprintf (file, "\t.quad\t" HOST_WIDE_INT_PRINT_HEX "\n", INTVAL (ciw));
8959 /* Add a call information word (CIW) to the list of the current function's
8960 CIWs and return its index.
8962 X is a CONST_INT or CONST_DOUBLE representing the CIW. */
8965 unicosmk_add_call_info_word (rtx x)
8968 struct machine_function *machine = cfun->machine;
8970 node = gen_rtx_EXPR_LIST (VOIDmode, x, NULL_RTX);
8971 if (machine->first_ciw == NULL_RTX)
8972 machine->first_ciw = node;
8974 XEXP (machine->last_ciw, 1) = node;
8976 machine->last_ciw = node;
8977 ++machine->ciw_count;
8979 return GEN_INT (machine->ciw_count
8980 + strlen (current_function_name ())/8 + 5);
8983 static char unicosmk_section_buf[100];
8986 unicosmk_text_section (void)
8988 static int count = 0;
8989 sprintf (unicosmk_section_buf, "\t.endp\n\n\t.psect\tgcc@text___%d,code",
8991 return unicosmk_section_buf;
8995 unicosmk_data_section (void)
8997 static int count = 1;
8998 sprintf (unicosmk_section_buf, "\t.endp\n\n\t.psect\tgcc@data___%d,data",
9000 return unicosmk_section_buf;
9003 /* The Cray assembler doesn't accept extern declarations for symbols which
9004 are defined in the same file. We have to keep track of all global
9005 symbols which are referenced and/or defined in a source file and output
9006 extern declarations for those which are referenced but not defined at
9009 /* List of identifiers for which an extern declaration might have to be
9011 /* FIXME: needs to use GC, so it can be saved and restored for PCH. */
9013 struct unicosmk_extern_list
9015 struct unicosmk_extern_list *next;
9019 static struct unicosmk_extern_list *unicosmk_extern_head = 0;
9021 /* Output extern declarations which are required for every asm file. */
9024 unicosmk_output_default_externs (FILE *file)
9026 static const char *const externs[] =
9027 { "__T3E_MISMATCH" };
9032 n = ARRAY_SIZE (externs);
9034 for (i = 0; i < n; i++)
9035 fprintf (file, "\t.extern\t%s\n", externs[i]);
9038 /* Output extern declarations for global symbols which are have been
9039 referenced but not defined. */
9042 unicosmk_output_externs (FILE *file)
9044 struct unicosmk_extern_list *p;
9045 const char *real_name;
9049 len = strlen (user_label_prefix);
9050 for (p = unicosmk_extern_head; p != 0; p = p->next)
9052 /* We have to strip the encoding and possibly remove user_label_prefix
9053 from the identifier in order to handle -fleading-underscore and
9054 explicit asm names correctly (cf. gcc.dg/asm-names-1.c). */
9055 real_name = default_strip_name_encoding (p->name);
9056 if (len && p->name[0] == '*'
9057 && !memcmp (real_name, user_label_prefix, len))
9060 name_tree = get_identifier (real_name);
9061 if (! TREE_ASM_WRITTEN (name_tree))
9063 TREE_ASM_WRITTEN (name_tree) = 1;
9064 fputs ("\t.extern\t", file);
9065 assemble_name (file, p->name);
9071 /* Record an extern. */
9074 unicosmk_add_extern (const char *name)
9076 struct unicosmk_extern_list *p;
9078 p = (struct unicosmk_extern_list *)
9079 xmalloc (sizeof (struct unicosmk_extern_list));
9080 p->next = unicosmk_extern_head;
9082 unicosmk_extern_head = p;
9085 /* The Cray assembler generates incorrect code if identifiers which
9086 conflict with register names are used as instruction operands. We have
9087 to replace such identifiers with DEX expressions. */
9089 /* Structure to collect identifiers which have been replaced by DEX
9091 /* FIXME: needs to use GC, so it can be saved and restored for PCH. */
9093 struct unicosmk_dex {
9094 struct unicosmk_dex *next;
9098 /* List of identifiers which have been replaced by DEX expressions. The DEX
9099 number is determined by the position in the list. */
9101 static struct unicosmk_dex *unicosmk_dex_list = NULL;
9103 /* The number of elements in the DEX list. */
9105 static int unicosmk_dex_count = 0;
9107 /* Check if NAME must be replaced by a DEX expression. */
9110 unicosmk_special_name (const char *name)
9118 if (name[0] != 'r' && name[0] != 'f' && name[0] != 'R' && name[0] != 'F')
9124 return (name[2] == '\0' || (ISDIGIT (name[2]) && name[3] == '\0'));
9127 return (name[2] == '\0'
9128 || ((name[2] == '0' || name[2] == '1') && name[3] == '\0'));
9131 return (ISDIGIT (name[1]) && name[2] == '\0');
9135 /* Return the DEX number if X must be replaced by a DEX expression and 0
9139 unicosmk_need_dex (rtx x)
9141 struct unicosmk_dex *dex;
9145 if (GET_CODE (x) != SYMBOL_REF)
9149 if (! unicosmk_special_name (name))
9152 i = unicosmk_dex_count;
9153 for (dex = unicosmk_dex_list; dex; dex = dex->next)
9155 if (! strcmp (name, dex->name))
9160 dex = (struct unicosmk_dex *) xmalloc (sizeof (struct unicosmk_dex));
9162 dex->next = unicosmk_dex_list;
9163 unicosmk_dex_list = dex;
9165 ++unicosmk_dex_count;
9166 return unicosmk_dex_count;
9169 /* Output the DEX definitions for this file. */
9172 unicosmk_output_dex (FILE *file)
9174 struct unicosmk_dex *dex;
9177 if (unicosmk_dex_list == NULL)
9180 fprintf (file, "\t.dexstart\n");
9182 i = unicosmk_dex_count;
9183 for (dex = unicosmk_dex_list; dex; dex = dex->next)
9185 fprintf (file, "\tDEX (%d) = ", i);
9186 assemble_name (file, dex->name);
9191 fprintf (file, "\t.dexend\n");
9194 /* Output text that to appear at the beginning of an assembler file. */
9197 unicosmk_file_start (void)
9201 fputs ("\t.ident\t", asm_out_file);
9202 unicosmk_output_module_name (asm_out_file);
9203 fputs ("\n\n", asm_out_file);
9205 /* The Unicos/Mk assembler uses different register names. Instead of trying
9206 to support them, we simply use micro definitions. */
9208 /* CAM has different register names: rN for the integer register N and fN
9209 for the floating-point register N. Instead of trying to use these in
9210 alpha.md, we define the symbols $N and $fN to refer to the appropriate
9213 for (i = 0; i < 32; ++i)
9214 fprintf (asm_out_file, "$%d <- r%d\n", i, i);
9216 for (i = 0; i < 32; ++i)
9217 fprintf (asm_out_file, "$f%d <- f%d\n", i, i);
9219 putc ('\n', asm_out_file);
9221 /* The .align directive fill unused space with zeroes which does not work
9222 in code sections. We define the macro 'gcc@code@align' which uses nops
9223 instead. Note that it assumes that code sections always have the
9224 biggest possible alignment since . refers to the current offset from
9225 the beginning of the section. */
9227 fputs ("\t.macro gcc@code@align n\n", asm_out_file);
9228 fputs ("gcc@n@bytes = 1 << n\n", asm_out_file);
9229 fputs ("gcc@here = . % gcc@n@bytes\n", asm_out_file);
9230 fputs ("\t.if ne, gcc@here, 0\n", asm_out_file);
9231 fputs ("\t.repeat (gcc@n@bytes - gcc@here) / 4\n", asm_out_file);
9232 fputs ("\tbis r31,r31,r31\n", asm_out_file);
9233 fputs ("\t.endr\n", asm_out_file);
9234 fputs ("\t.endif\n", asm_out_file);
9235 fputs ("\t.endm gcc@code@align\n\n", asm_out_file);
9237 /* Output extern declarations which should always be visible. */
9238 unicosmk_output_default_externs (asm_out_file);
9240 /* Open a dummy section. We always need to be inside a section for the
9241 section-switching code to work correctly.
9242 ??? This should be a module id or something like that. I still have to
9243 figure out what the rules for those are. */
9244 fputs ("\n\t.psect\t$SG00000,data\n", asm_out_file);
9247 /* Output text to appear at the end of an assembler file. This includes all
9248 pending extern declarations and DEX expressions. */
9251 unicosmk_file_end (void)
9253 fputs ("\t.endp\n\n", asm_out_file);
9255 /* Output all pending externs. */
9257 unicosmk_output_externs (asm_out_file);
9259 /* Output dex definitions used for functions whose names conflict with
9262 unicosmk_output_dex (asm_out_file);
9264 fputs ("\t.end\t", asm_out_file);
9265 unicosmk_output_module_name (asm_out_file);
9266 putc ('\n', asm_out_file);
9272 unicosmk_output_deferred_case_vectors (FILE *file ATTRIBUTE_UNUSED)
9276 unicosmk_gen_dsib (unsigned long *imaskP ATTRIBUTE_UNUSED)
9280 unicosmk_output_ssib (FILE * file ATTRIBUTE_UNUSED,
9281 const char * fnname ATTRIBUTE_UNUSED)
9285 unicosmk_add_call_info_word (rtx x ATTRIBUTE_UNUSED)
9291 unicosmk_need_dex (rtx x ATTRIBUTE_UNUSED)
9296 #endif /* TARGET_ABI_UNICOSMK */
9299 alpha_init_libfuncs (void)
9301 if (TARGET_ABI_UNICOSMK)
9303 /* Prevent gcc from generating calls to __divsi3. */
9304 set_optab_libfunc (sdiv_optab, SImode, 0);
9305 set_optab_libfunc (udiv_optab, SImode, 0);
9307 /* Use the functions provided by the system library
9308 for DImode integer division. */
9309 set_optab_libfunc (sdiv_optab, DImode, "$sldiv");
9310 set_optab_libfunc (udiv_optab, DImode, "$uldiv");
9312 else if (TARGET_ABI_OPEN_VMS)
9314 /* Use the VMS runtime library functions for division and
9316 set_optab_libfunc (sdiv_optab, SImode, "OTS$DIV_I");
9317 set_optab_libfunc (sdiv_optab, DImode, "OTS$DIV_L");
9318 set_optab_libfunc (udiv_optab, SImode, "OTS$DIV_UI");
9319 set_optab_libfunc (udiv_optab, DImode, "OTS$DIV_UL");
9320 set_optab_libfunc (smod_optab, SImode, "OTS$REM_I");
9321 set_optab_libfunc (smod_optab, DImode, "OTS$REM_L");
9322 set_optab_libfunc (umod_optab, SImode, "OTS$REM_UI");
9323 set_optab_libfunc (umod_optab, DImode, "OTS$REM_UL");
9328 /* Initialize the GCC target structure. */
9329 #if TARGET_ABI_OPEN_VMS
9330 # undef TARGET_ATTRIBUTE_TABLE
9331 # define TARGET_ATTRIBUTE_TABLE vms_attribute_table
9332 # undef TARGET_SECTION_TYPE_FLAGS
9333 # define TARGET_SECTION_TYPE_FLAGS vms_section_type_flags
9336 #undef TARGET_IN_SMALL_DATA_P
9337 #define TARGET_IN_SMALL_DATA_P alpha_in_small_data_p
9339 #if TARGET_ABI_UNICOSMK
9340 # undef TARGET_INSERT_ATTRIBUTES
9341 # define TARGET_INSERT_ATTRIBUTES unicosmk_insert_attributes
9342 # undef TARGET_SECTION_TYPE_FLAGS
9343 # define TARGET_SECTION_TYPE_FLAGS unicosmk_section_type_flags
9344 # undef TARGET_ASM_UNIQUE_SECTION
9345 # define TARGET_ASM_UNIQUE_SECTION unicosmk_unique_section
9346 #undef TARGET_ASM_FUNCTION_RODATA_SECTION
9347 #define TARGET_ASM_FUNCTION_RODATA_SECTION default_no_function_rodata_section
9348 # undef TARGET_ASM_GLOBALIZE_LABEL
9349 # define TARGET_ASM_GLOBALIZE_LABEL hook_void_FILEptr_constcharptr
9350 # undef TARGET_MUST_PASS_IN_STACK
9351 # define TARGET_MUST_PASS_IN_STACK unicosmk_must_pass_in_stack
9354 #undef TARGET_ASM_ALIGNED_HI_OP
9355 #define TARGET_ASM_ALIGNED_HI_OP "\t.word\t"
9356 #undef TARGET_ASM_ALIGNED_DI_OP
9357 #define TARGET_ASM_ALIGNED_DI_OP "\t.quad\t"
9359 /* Default unaligned ops are provided for ELF systems. To get unaligned
9360 data for non-ELF systems, we have to turn off auto alignment. */
9361 #ifndef OBJECT_FORMAT_ELF
9362 #undef TARGET_ASM_UNALIGNED_HI_OP
9363 #define TARGET_ASM_UNALIGNED_HI_OP "\t.align 0\n\t.word\t"
9364 #undef TARGET_ASM_UNALIGNED_SI_OP
9365 #define TARGET_ASM_UNALIGNED_SI_OP "\t.align 0\n\t.long\t"
9366 #undef TARGET_ASM_UNALIGNED_DI_OP
9367 #define TARGET_ASM_UNALIGNED_DI_OP "\t.align 0\n\t.quad\t"
9370 #ifdef OBJECT_FORMAT_ELF
9371 #undef TARGET_ASM_SELECT_RTX_SECTION
9372 #define TARGET_ASM_SELECT_RTX_SECTION alpha_elf_select_rtx_section
9375 #undef TARGET_ASM_FUNCTION_END_PROLOGUE
9376 #define TARGET_ASM_FUNCTION_END_PROLOGUE alpha_output_function_end_prologue
9378 #undef TARGET_INIT_LIBFUNCS
9379 #define TARGET_INIT_LIBFUNCS alpha_init_libfuncs
9381 #if TARGET_ABI_UNICOSMK
9382 #undef TARGET_ASM_FILE_START
9383 #define TARGET_ASM_FILE_START unicosmk_file_start
9384 #undef TARGET_ASM_FILE_END
9385 #define TARGET_ASM_FILE_END unicosmk_file_end
9387 #undef TARGET_ASM_FILE_START
9388 #define TARGET_ASM_FILE_START alpha_file_start
9389 #undef TARGET_ASM_FILE_START_FILE_DIRECTIVE
9390 #define TARGET_ASM_FILE_START_FILE_DIRECTIVE true
9393 #undef TARGET_SCHED_ADJUST_COST
9394 #define TARGET_SCHED_ADJUST_COST alpha_adjust_cost
9395 #undef TARGET_SCHED_ISSUE_RATE
9396 #define TARGET_SCHED_ISSUE_RATE alpha_issue_rate
9397 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
9398 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \
9399 alpha_multipass_dfa_lookahead
9401 #undef TARGET_HAVE_TLS
9402 #define TARGET_HAVE_TLS HAVE_AS_TLS
9404 #undef TARGET_INIT_BUILTINS
9405 #define TARGET_INIT_BUILTINS alpha_init_builtins
9406 #undef TARGET_EXPAND_BUILTIN
9407 #define TARGET_EXPAND_BUILTIN alpha_expand_builtin
9409 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
9410 #define TARGET_FUNCTION_OK_FOR_SIBCALL alpha_function_ok_for_sibcall
9411 #undef TARGET_CANNOT_COPY_INSN_P
9412 #define TARGET_CANNOT_COPY_INSN_P alpha_cannot_copy_insn_p
9413 #undef TARGET_CANNOT_FORCE_CONST_MEM
9414 #define TARGET_CANNOT_FORCE_CONST_MEM alpha_cannot_force_const_mem
9417 #undef TARGET_ASM_OUTPUT_MI_THUNK
9418 #define TARGET_ASM_OUTPUT_MI_THUNK alpha_output_mi_thunk_osf
9419 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
9420 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_tree_hwi_hwi_tree_true
9423 #undef TARGET_RTX_COSTS
9424 #define TARGET_RTX_COSTS alpha_rtx_costs
9425 #undef TARGET_ADDRESS_COST
9426 #define TARGET_ADDRESS_COST hook_int_rtx_0
9428 #undef TARGET_MACHINE_DEPENDENT_REORG
9429 #define TARGET_MACHINE_DEPENDENT_REORG alpha_reorg
9431 #undef TARGET_PROMOTE_FUNCTION_ARGS
9432 #define TARGET_PROMOTE_FUNCTION_ARGS hook_bool_tree_true
9433 #undef TARGET_PROMOTE_FUNCTION_RETURN
9434 #define TARGET_PROMOTE_FUNCTION_RETURN hook_bool_tree_true
9435 #undef TARGET_PROMOTE_PROTOTYPES
9436 #define TARGET_PROMOTE_PROTOTYPES hook_bool_tree_false
9437 #undef TARGET_RETURN_IN_MEMORY
9438 #define TARGET_RETURN_IN_MEMORY alpha_return_in_memory
9439 #undef TARGET_PASS_BY_REFERENCE
9440 #define TARGET_PASS_BY_REFERENCE alpha_pass_by_reference
9441 #undef TARGET_SETUP_INCOMING_VARARGS
9442 #define TARGET_SETUP_INCOMING_VARARGS alpha_setup_incoming_varargs
9443 #undef TARGET_STRICT_ARGUMENT_NAMING
9444 #define TARGET_STRICT_ARGUMENT_NAMING hook_bool_CUMULATIVE_ARGS_true
9445 #undef TARGET_PRETEND_OUTGOING_VARARGS_NAMED
9446 #define TARGET_PRETEND_OUTGOING_VARARGS_NAMED hook_bool_CUMULATIVE_ARGS_true
9447 #undef TARGET_SPLIT_COMPLEX_ARG
9448 #define TARGET_SPLIT_COMPLEX_ARG alpha_split_complex_arg
9449 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
9450 #define TARGET_GIMPLIFY_VA_ARG_EXPR alpha_gimplify_va_arg
9452 #undef TARGET_SCALAR_MODE_SUPPORTED_P
9453 #define TARGET_SCALAR_MODE_SUPPORTED_P alpha_scalar_mode_supported_p
9454 #undef TARGET_VECTOR_MODE_SUPPORTED_P
9455 #define TARGET_VECTOR_MODE_SUPPORTED_P alpha_vector_mode_supported_p
9457 #undef TARGET_BUILD_BUILTIN_VA_LIST
9458 #define TARGET_BUILD_BUILTIN_VA_LIST alpha_build_builtin_va_list
9460 #undef TARGET_VECTORIZE_MISALIGNED_MEM_OK
9461 #define TARGET_VECTORIZE_MISALIGNED_MEM_OK alpha_vector_mode_supported_p
9463 struct gcc_target targetm = TARGET_INITIALIZER;
9466 #include "gt-alpha.h"