1 ;;- Machine description for GNU compiler
2 ;;- MIL-STD-1750A version.
3 ;; Copyright (C) 1994, 1995, 1996, 1997, 1998, 1999,
4 ;; 2000 Free Software Foundation, Inc.
5 ;; Contributed by O.M.Kellogg, DASA (oliver.kellogg@space.otn.dasa.de).
7 ;; This file is part of GNU CC.
9 ;; GNU CC is free software; you can redistribute it and/or modify
10 ;; it under the terms of the GNU General Public License as published by
11 ;; the Free Software Foundation; either version 2, or (at your option)
14 ;; GNU CC is distributed in the hope that it will be useful,
15 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
16 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 ;; GNU General Public License for more details.
19 ;; You should have received a copy of the GNU General Public License
20 ;; along with GNU CC; see the file COPYING. If not, write to
21 ;; the Free Software Foundation, 59 Temple Place - Suite 330,
22 ;; Boston, MA 02111-1307, USA.
25 ;;- instruction definitions
27 ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
29 ;;- When naming insn's (operand 0 of define_insn) be careful about using
30 ;;- names from other targets machine descriptions.
32 ;; MIL-STD-1750 specific remarks:
34 ;; 1) BITS_PER_UNIT = 16
36 ;; 2) GCC to MIL-STD-1750 data type mappings:
37 ;; QImode => single integer (16 bits or 1 reg).
38 ;; HImode => double integer (32 bits or 2 regs).
39 ;; HFmode => single precision float (32 bits or 2 regs).
40 ;; TQFmode => extended precision float (48 bits or 3 regs).
42 ;; 3) Immediate integer operands Constraints:
47 ;; 'M' -32768 .. 32767
48 ;; 'O' => 0 (for optimizations and GCC quirks)
51 ;;- Assembly output ending in ".M" are macros in file M1750.INC
56 [(set (match_operand:QI 0 "push_operand" "=<")
57 (match_operand:QI 1 "general_operand" "r"))]
62 [(set (match_operand:HI 0 "push_operand" "=<")
63 (match_operand:HI 1 "general_operand" "r"))]
68 [(set (match_operand:HF 0 "push_operand" "=<")
69 (match_operand:HF 1 "general_operand" "r"))]
74 [(set (match_operand:TQF 0 "push_operand" "=<")
75 (match_operand:TQF 1 "general_operand" "r"))]
81 [(set (match_operand:QI 0 "general_operand" "=r")
82 (match_operand:QI 1 "push_operand" ">"))]
87 [(set (match_operand:HI 0 "general_operand" "=r")
88 (match_operand:HI 1 "push_operand" ">"))]
93 [(set (match_operand:HF 0 "general_operand" "=r")
94 (match_operand:HF 1 "push_operand" ">"))]
99 [(set (match_operand:TQF 0 "general_operand" "=r")
100 (match_operand:TQF 1 "push_operand" ">"))]
109 (match_operand:QI 0 "register_operand" "r"))]
111 "lr r%0,r%0 ; from tstqi")
115 (match_operand:HI 0 "register_operand" "r"))]
117 "dlr r%0,r%0 ; from tsthi")
119 ; With 1750A floats, testing the most significant word suffices.
123 (match_operand:HF 0 "register_operand" "r"))]
125 "lr r%0,r%0 ; tsthf")
127 (define_insn "tsttqf"
129 (match_operand:TQF 0 "register_operand" "r"))]
131 "lr r%0,r%0 ; tsttqf")
136 (define_insn "movstrqi"
137 [(set (match_operand:BLK 0 "mov_memory_operand" "=m")
138 (match_operand:BLK 1 "mov_memory_operand" "m"))
139 (use (match_operand:QI 2 "general_operand" "r"))
140 (match_operand 3 "" "")
141 (clobber (match_dup 0))
142 (clobber (match_dup 1))
143 (clobber (match_dup 2))]
149 regops[0] = XEXP (operands[0], 0);
150 regops[1] = XEXP (operands[1], 0);
151 regops[2] = operands[2];
153 return movcnt_regno_adjust (regops);
157 ;; compare instructions.
161 (compare (match_operand:QI 0 "register_operand" "r,r,r,r,r")
162 (match_operand:QI 1 "general_operand" "I,J,i,r,m")))]
166 if (next_cc_user_is_unsigned (insn))
167 switch (which_alternative)
172 return \"ucim.m %0,%1\";
174 return \"ucr.m %0,%1\";
176 return \"uc.m %0,%1\";
181 switch (which_alternative)
184 return \"cisp r%0,%1\";
186 return \"cisn r%0,%J1\";
188 return \"cim r%0,%1\";
190 return \"cr r%0,r%1\";
200 (compare (match_operand:HI 0 "general_operand" "r,r")
201 (match_operand:HI 1 "general_operand" "r,m")))]
205 if (next_cc_user_is_unsigned (insn))
207 if (which_alternative == 0)
208 return \"ducr.m %0,%1\";
209 return \"duc.m %0,%1\";
213 if (which_alternative == 0)
214 return \"dcr r%0,r%1\";
215 return \"dc r%0,%1\";
221 (compare (match_operand:HF 0 "general_operand" "r,r")
222 (match_operand:HF 1 "general_operand" "r,m")))]
228 (define_insn "cmptqf"
230 (compare (match_operand:TQF 0 "general_operand" "r,r")
231 (match_operand:TQF 1 "general_operand" "r,m")))]
238 ;; truncation instructions
239 ;;- 1750: any needed?
241 (define_insn "trunchiqi2"
242 [(set (match_operand:QI 0 "register_operand" "=r")
243 (truncate:QI (match_operand:HI 1 "register_operand" "r")))]
248 ;; zero extension instructions: not defined, GCC can synthesize
250 ;; sign extension instructions
252 (define_insn "extendqihi2"
253 [(set (match_operand:HI 0 "register_operand" "=r,r")
254 (sign_extend:HI (match_operand:QI 1 "general_operand" "r,m")) )]
257 if (which_alternative == 0)
259 if (REGNO (operands [0]) != REGNO (operands [1]))
260 output_asm_insn (\"lr r%0,r%1\", operands);
263 output_asm_insn (\"l r%0,%1\", operands);
264 return \"dsra r%0,16 ;extendqihi2\";
268 ;; Conversions between float and double.
270 ; 1750 HF-to-TQF extend: just append 16 bits (least signif.) with all bits zero
271 (define_insn "extendhftqf2"
272 [(set (match_operand:TQF 0 "register_operand" "=r,r")
273 (float_extend:TQF (match_operand:HF 1 "general_operand" "r,m")))]
276 output_asm_insn(\"xorr r%t0,r%t0 ;extendhftqf2\", operands);
277 if (which_alternative == 0)
279 if (REGNO (operands[1]) != REGNO (operands[0]))
280 return \"dlr r%0,r%1\";
285 return \"dl r%0,%1\";
288 ; 1750 TQF-to-HF truncate is a no-op: just leave away the least signif. 16 bits
289 (define_insn "trunctqfhf2"
290 [(set (match_operand:HF 0 "register_operand" "=r,r")
292 (match_operand:TQF 1 "general_operand" "r,m")))]
295 dlr r%0,r%1 ;trunctqfhf2
296 dl r%0,%1 ;trunctqfhf2 ")
299 ;; Conversion between fixed point and floating point.
301 (define_insn "floatqihf2"
302 [(set (match_operand:HF 0 "register_operand" "=r")
303 (float:HF (match_operand:QI 1 "register_operand" "r")))]
307 (define_insn "floathitqf2"
308 [(set (match_operand:TQF 0 "register_operand" "=r")
309 (float:TQF (match_operand:HI 1 "register_operand" "r")))]
314 ;; Convert floats to ints
316 (define_insn "fix_trunchfqi2"
317 [(set (match_operand:QI 0 "register_operand" "=r")
318 (fix:QI (fix:HF (match_operand:HF 1 "register_operand" "r"))))]
322 (define_insn "fix_trunctqfhi2"
323 [(set (match_operand:HI 0 "register_operand" "=r")
324 (fix:HI (fix:TQF (match_operand:TQF 1 "register_operand" "r"))))]
331 ;; We can't deal with normal byte-size characters, only with WIDE characters!
332 ;; This may appear as a serious restriction, but it also opens the doors
337 ; memory indirect to reg
339 [(set (match_operand:QI 0 "register_operand" "=r")
340 (mem:QI (match_operand 1 "memory_operand" "m")))]
344 ; reg/const to memory indirect
346 [(set (mem:QI (match_operand 0 "memory_operand" "=m,m"))
347 (match_operand:QI 1 "nonmemory_operand" "r,K"))]
355 [(set (match_operand:QI 0 "general_operand" "=r,r,r,r,r,r,m,m")
356 (match_operand:QI 1 "general_operand" "O,I,J,i,r,m,r,K"))]
370 ; memory indirect to reg
372 [(set (match_operand:HI 0 "register_operand" "=r")
373 (mem:HI (match_operand 1 "memory_operand" "m")))]
377 ; reg to memory indirect
379 [(set (mem:HI (match_operand 0 "memory_operand" "=m"))
380 (match_operand:HI 1 "register_operand" "r"))]
386 [(set (match_operand:HI 0 "general_operand" "=r,r,r,r,r,m,m")
387 (match_operand:HI 1 "general_operand" "O,I,J,r,m,r,K"))]
390 xorr r%0,r%0\;xorr r%d0,r%d0
391 xorr r%0,r%0\;lisp r%d0,%1
392 lisn r%0,1 \;lisn r%d0,%J1
396 stc 0,%0 \;stc %1,%A0 ")
398 (define_expand "movhi"
399 [(set (match_operand:HI 0 "general_operand" "=g")
400 (match_operand:HI 1 "general_operand" "g"))]
404 rtx op1 = operands[1];
405 if (GET_CODE (operands[0]) == MEM)
407 if (GET_CODE (op1) == MEM
408 || (GET_CODE (op1) == CONST_INT
409 && (INTVAL (op1) < 0 || INTVAL (op1) > 15)))
410 operands[1] = force_reg (HImode, operands[1]);
412 else if (GET_CODE (op1) == CONST_INT
413 && (INTVAL (op1) < -16 || INTVAL (op1) > 16))
414 operands[1] = force_const_mem (HImode, operands[1]);
418 ;; Single-Float moves
421 [(set (match_operand:HF 0 "general_operand" "=r,r,m,m")
422 (match_operand:HF 1 "general_operand" "r,m,r,G"))]
428 stc 0,%0 \;stc 0,%A0 ")
430 (define_expand "movhf"
431 [(set (match_operand:HF 0 "general_operand" "")
432 (match_operand:HF 1 "general_operand" ""))]
436 enum rtx_code op1code = GET_CODE (operands[1]);
437 if (GET_CODE (operands[0]) == MEM)
439 if (op1code == MEM || (op1code == CONST_DOUBLE
440 && !rtx_equal_p (operands[1], CONST0_RTX (HFmode))))
441 operands[1] = force_reg (HFmode, operands[1]);
443 else if (op1code == CONST_DOUBLE)
444 operands[1] = force_const_mem (HFmode, operands[1]);
451 [(set (match_operand:TQF 0 "general_operand" "=r,r,m")
452 (match_operand:TQF 1 "general_operand" "r,m,r"))]
459 (define_expand "movtqf"
460 [(set (match_operand:TQF 0 "general_operand" "")
461 (match_operand:TQF 1 "general_operand" ""))]
465 enum rtx_code op1code = GET_CODE (operands[1]);
466 if (GET_CODE (operands[0]) == MEM)
468 if (op1code == MEM || op1code == CONST_DOUBLE)
469 operands[1] = force_reg (TQFmode, operands[1]);
471 else if (op1code == CONST_DOUBLE)
472 operands[1] = force_const_mem (TQFmode, operands[1]);
480 (define_insn "addqi3"
481 [(set (match_operand:QI 0 "general_operand" "=r,r,r,r,r,m,m")
482 (plus:QI (match_operand:QI 1 "general_operand" "%0,0,0,0,0,0,0")
483 (match_operand:QI 2 "general_operand" "I,J,i,r,m,I,J")))]
486 switch (which_alternative)
489 return \"aisp r%0,%2\";
491 return \"sisp r%0,%J2\";
493 if (INTVAL(operands[2]) < 0)
494 return \"sim r%0,%J2\";
496 return \"aim r%0,%2\";
498 return \"ar r%0,r%2\";
502 return \"incm %2,%0\";
504 return \"decm %J2,%0\";
510 (define_insn "addhi3"
511 [(set (match_operand:HI 0 "register_operand" "=r,r")
512 (plus:HI (match_operand:HI 1 "register_operand" "%0,0")
513 (match_operand:HI 2 "general_operand" "r,m")))]
519 (define_insn "addhf3"
520 [(set (match_operand:HF 0 "register_operand" "=r,r")
521 (plus:HF (match_operand:HF 1 "register_operand" "%0,0")
522 (match_operand:HF 2 "general_operand" "r,m")))]
528 (define_insn "addtqf3"
529 [(set (match_operand:TQF 0 "register_operand" "=r,r")
530 (plus:TQF (match_operand:TQF 1 "register_operand" "%0,0")
531 (match_operand:TQF 2 "general_operand" "r,m")))]
538 ;; subtract instructions
541 (define_insn "subqi3"
542 [(set (match_operand:QI 0 "general_operand" "=r,r,r,r,m")
543 (minus:QI (match_operand:QI 1 "general_operand" "0,0,0,0,0")
544 (match_operand:QI 2 "general_operand" "I,i,r,m,I")))]
554 (define_insn "subhi3"
555 [(set (match_operand:HI 0 "register_operand" "=r,r")
556 (minus:HI (match_operand:HI 1 "register_operand" "0,0")
557 (match_operand:HI 2 "general_operand" "r,m")))]
563 (define_insn "subhf3"
564 [(set (match_operand:HF 0 "register_operand" "=r,r")
565 (minus:HF (match_operand:HF 1 "register_operand" "0,0")
566 (match_operand:HF 2 "general_operand" "r,m")))]
572 (define_insn "subtqf3"
573 [(set (match_operand:TQF 0 "register_operand" "=r,r")
574 (minus:TQF (match_operand:TQF 1 "register_operand" "0,0")
575 (match_operand:TQF 2 "general_operand" "r,m")))]
582 ;; multiply instructions
584 (define_insn "mulqi3"
585 [(set (match_operand:QI 0 "register_operand" "=r,r,r,r,r")
586 (mult:QI (match_operand:QI 1 "register_operand" "%0,0,0,0,0")
587 (match_operand:QI 2 "general_operand" "I,J,M,r,m")))]
598 (define_insn "mulqihi3"
599 [(set (match_operand:HI 0 "register_operand" "=r,r,r")
600 (mult:HI (sign_extend:HI (match_operand:QI 1 "register_operand" "%r,r,r"))
601 (sign_extend:HI (match_operand:QI 2 "general_operand" "r,m,i"))))]
604 if (REGNO (operands[1]) != REGNO (operands[0]))
605 output_asm_insn (\"lr r%0,r%1\", operands);
607 switch (which_alternative)
610 return \"mr r%0,r%2\";
614 return \"mim r%0,%2\";
621 (define_insn "mulhi3"
622 [(set (match_operand:HI 0 "register_operand" "=r,r")
623 (mult:HI (match_operand:HI 1 "register_operand" "%0,0")
624 (match_operand:HI 2 "general_operand" "r,m")))]
630 ; not available on 1750: "umulhi3","umulhisi3","umulsi3" (unsigned multiply's)
632 (define_insn "mulhf3"
633 [(set (match_operand:HF 0 "register_operand" "=r,r")
634 (mult:HF (match_operand:HF 1 "register_operand" "%0,0")
635 (match_operand:HF 2 "general_operand" "r,m")))]
641 (define_insn "multqf3"
642 [(set (match_operand:TQF 0 "register_operand" "=r,r")
643 (mult:TQF (match_operand:TQF 1 "register_operand" "%0,0")
644 (match_operand:TQF 2 "general_operand" "r,m")))]
651 ;; divide instructions
652 ;; The 1750 16bit integer division instructions deliver a 16-bit
653 ;; quotient and a 16-bit remainder, where the remainder is in the next higher
654 ;; register number above the quotient. For now, we haven't found a way
655 ;; to give the reload pass knowledge of this property. So we make do with
656 ;; whatever registers the allocator wants, and willy-nilly output a pair of
657 ;; register-copy ops when needed. (See mod_regno_adjust() in file aux-output.c)
658 ;; A comment in the description of `divmodM4' suggests that one leave the divM3
659 ;; undefined when there is a divmodM4 available.
661 (define_insn "divmodqi4"
662 [(set (match_operand:QI 0 "register_operand" "=r,r,r,r,r")
663 (div:QI (match_operand:QI 1 "register_operand" "0,0,0,0,0")
664 (match_operand:QI 2 "general_operand" "I,J,M,r,m")))
665 (set (match_operand:QI 3 "register_operand" "=r,r,r,r,r")
666 (mod:QI (match_dup 1) (match_dup 2)))]
671 switch(which_alternative)
679 new_opnds[0] = operands[0];
680 new_opnds[1] = operands[1];
681 new_opnds[2] = GEN_INT (-INTVAL(operands[2]));
682 new_opnds[3] = operands[3];
684 return mod_regno_adjust (istr, new_opnds);
697 return mod_regno_adjust (istr, operands);
700 ;; Division for other types is straightforward.
702 (define_insn "divhi3"
703 [(set (match_operand:HI 0 "register_operand" "=r,r")
704 (div:HI (match_operand:HI 1 "register_operand" "0,0")
705 (match_operand:HI 2 "general_operand" "r,m")))]
711 (define_insn "divhf3"
712 [(set (match_operand:HF 0 "register_operand" "=r,r")
713 (div:HF (match_operand:HF 1 "register_operand" "0,0")
714 (match_operand:HF 2 "general_operand" "r,m")))]
720 (define_insn "divtqf3"
721 [(set (match_operand:TQF 0 "register_operand" "=r,r")
722 (div:TQF (match_operand:TQF 1 "register_operand" "0,0")
723 (match_operand:TQF 2 "general_operand" "r,m")))]
730 ;; Other arithmetic instructions:
734 (define_insn "absqi2"
735 [(set (match_operand:QI 0 "register_operand" "=r")
736 (abs:QI (match_operand:QI 1 "register_operand" "r")))]
740 (define_insn "abshi2"
741 [(set (match_operand:HI 0 "register_operand" "=r")
742 (abs:HI (match_operand:HI 1 "register_operand" "r")))]
746 (define_insn "abshf2"
747 [(set (match_operand:HF 0 "register_operand" "=r")
748 (abs:HF (match_operand:HF 1 "register_operand" "r")))]
755 (define_insn "negqi2"
756 [(set (match_operand:QI 0 "register_operand" "=r")
757 (neg:QI (match_operand:QI 1 "register_operand" "r")))]
761 (define_insn "neghi2"
762 [(set (match_operand:HI 0 "register_operand" "=r")
763 (neg:HI (match_operand:HI 1 "register_operand" "r")))]
767 (define_insn "neghf2"
768 [(set (match_operand:HF 0 "register_operand" "=r")
769 (neg:HF (match_operand:HF 1 "register_operand" "r")))]
773 ; The 1750A does not have an extended float negate instruction, so simulate.
774 (define_expand "negtqf2"
775 [(set (match_operand:TQF 0 "register_operand" "=&r")
776 (neg:TQF (match_operand:TQF 1 "register_operand" "r")))]
779 emit_insn (gen_rtx_SET (VOIDmode, operands[0], CONST0_RTX (TQFmode)));
780 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
781 gen_rtx_MINUS (TQFmode, operands[0], operands[1])));
786 ;; bit-logical instructions
790 [(set (match_operand:QI 0 "general_operand" "=r,m")
791 (ior:QI (match_operand:QI 1 "general_operand" "0,0")
792 (match_operand:QI 2 "const_int_operand" "i,i")))]
793 "one_bit_set_p (INTVAL (operands [2]))"
800 [(set (match_operand:QI 0 "general_operand" "=r,m")
801 (and:QI (match_operand:QI 1 "general_operand" "0,0")
802 (match_operand:QI 2 "const_int_operand" "i,i")))]
803 "one_bit_set_p ((~INTVAL (operands [2])) & 0xffff)"
810 [(set (match_operand:QI 0 "register_operand" "=r")
811 (ior:QI (match_operand:QI 1 "register_operand" "0")
812 (lshiftrt:QI (const_int 0x8000)
813 (match_operand:QI 2 "register_operand" "r"))))]
817 ;; Reset Variable Bit
819 [(set (match_operand:QI 0 "general_operand" "=r")
820 (and:QI (match_operand:QI 1 "general_operand" "0")
821 (not:QI (lshiftrt:QI (const_int 0x8000)
822 (match_operand:QI 2 "register_operand" "r")))))]
829 (define_insn "andqi3"
830 [(set (match_operand:QI 0 "general_operand" "=r,r,r")
831 (and:QI (match_operand:QI 1 "general_operand" "%0,0,0")
832 (match_operand:QI 2 "general_operand" "M,r,m")))]
839 ; This sets incorrect condition codes. See notice_update_cc()
840 (define_insn "andhi3"
841 [(set (match_operand:HI 0 "register_operand" "=r")
842 (and:HI (match_operand:HI 1 "register_operand" "%0")
843 (match_operand:HI 2 "register_operand" "r")))]
849 (define_insn "iorqi3"
850 [(set (match_operand:QI 0 "general_operand" "=r,r,r")
851 (ior:QI (match_operand:QI 1 "general_operand" "%0,0,0")
852 (match_operand:QI 2 "general_operand" "M,r,m")))]
859 ; This sets incorrect condition codes. See notice_update_cc()
860 (define_insn "iorhi3"
861 [(set (match_operand:HI 0 "register_operand" "=r")
862 (ior:HI (match_operand:HI 1 "register_operand" "%0")
863 (match_operand:HI 2 "register_operand" "r")))]
869 (define_insn "xorqi3"
870 [(set (match_operand:QI 0 "register_operand" "=r,r,r")
871 (xor:QI (match_operand:QI 1 "register_operand" "%0,0,0")
872 (match_operand:QI 2 "general_operand" "M,r,m")))]
879 ; This sets incorrect condition codes. See notice_update_cc()
880 (define_insn "xorhi3"
881 [(set (match_operand:HI 0 "register_operand" "=r")
882 (xor:HI (match_operand:HI 1 "register_operand" "%0")
883 (match_operand:HI 2 "register_operand" "r")))]
890 [(set (match_operand:QI 0 "register_operand" "=r,r,r")
891 (ior:QI (not:QI (match_operand:QI 1 "register_operand" "%0,0,0"))
892 (not:QI (match_operand:QI 2 "general_operand" "M,r,m"))))]
899 ; This sets incorrect condition codes. See notice_update_cc()
901 [(set (match_operand:HI 0 "register_operand" "=r")
902 (ior:HI (not:HI (match_operand:HI 1 "register_operand" "%0"))
903 (not:HI (match_operand:HI 2 "register_operand" "r"))))]
909 (define_insn "one_cmplqi2"
910 [(set (match_operand:QI 0 "register_operand" "=r")
911 (not:QI (match_operand:QI 1 "register_operand" "0")))]
915 ; This sets incorrect condition codes. See notice_update_cc()
916 (define_insn "one_cmplhi2"
917 [(set (match_operand:HI 0 "register_operand" "=r")
918 (not:HI (match_operand:HI 1 "register_operand" "0")))]
923 ;; Shift instructions
925 ; (What to the 1750 is logical-shift-left, GCC likes to call "arithmetic")
926 (define_insn "ashlqi3"
927 [(set (match_operand:QI 0 "register_operand" "=r,r")
928 (ashift:QI (match_operand:QI 1 "register_operand" "0,0")
929 (match_operand:QI 2 "nonmemory_operand" "I,r")))]
935 (define_insn "ashlhi3"
936 [(set (match_operand:HI 0 "register_operand" "=r,r")
937 (ashift:HI (match_operand:HI 1 "register_operand" "0,0")
938 (match_operand:QI 2 "nonmemory_operand" "L,r")))]
939 "" ; the 'L' constraint is a slight imprecise...
941 if (which_alternative == 1)
942 return \"dslr r%0,r%2\";
943 else if (INTVAL(operands[2]) <= 16)
944 return \"dsll r%0,%2\";
947 output_asm_insn (\"dsll r%0,16 ; ashlhi3 shiftcnt > 16\", operands);
948 return \"sll r%0,%w2\";
953 ;; Right shift by a variable shiftcount works by negating the shift count,
954 ;; then emitting a right shift with the shift count negated. This means
955 ;; that all actual shift counts in the RTL will be positive. This
956 ;; prevents converting shifts to ZERO_EXTRACTs with negative positions,
957 ;; which isn't valid.
958 (define_expand "lshrqi3"
959 [(set (match_operand:QI 0 "register_operand" "=r")
960 (lshiftrt:QI (match_operand:QI 1 "register_operand" "0")
961 (match_operand:QI 2 "nonmemory_operand" "g")))]
965 if (GET_CODE (operands[2]) != CONST_INT)
966 operands[2] = gen_rtx_NEG (QImode, negate_rtx (QImode, operands[2]));
970 [(set (match_operand:QI 0 "register_operand" "=r")
971 (lshiftrt:QI (match_operand:QI 1 "register_operand" "0")
972 (match_operand:QI 2 "immediate_operand" "I")))]
977 [(set (match_operand:QI 0 "register_operand" "=r")
978 (lshiftrt:QI (match_operand:QI 1 "register_operand" "0")
979 (neg:QI (match_operand:QI 2 "register_operand" "r"))))]
983 ;; Same thing for HImode.
985 (define_expand "lshrhi3"
986 [(set (match_operand:HI 0 "register_operand" "=r")
987 (lshiftrt:HI (match_operand:HI 1 "register_operand" "0")
988 (match_operand:QI 2 "nonmemory_operand" "g")))]
992 if (GET_CODE (operands[2]) != CONST_INT)
993 operands[2] = gen_rtx_NEG (QImode, negate_rtx (QImode, operands[2]));
997 [(set (match_operand:HI 0 "register_operand" "=r")
998 (lshiftrt:HI (match_operand:HI 1 "register_operand" "0")
999 (match_operand:QI 2 "immediate_operand" "L")))]
1002 if (INTVAL (operands[2]) <= 16)
1003 return \"dsrl r%0,%2\";
1004 output_asm_insn (\"dsrl r%0,16 ; lshrhi3 shiftcount > 16\", operands);
1005 return \"srl r%d0,%w2\";
1009 [(set (match_operand:HI 0 "register_operand" "=r")
1010 (lshiftrt:HI (match_operand:HI 1 "register_operand" "0")
1011 (neg:QI (match_operand:QI 2 "register_operand" "r"))))]
1015 ;; Same applies for arithmetic shift right.
1016 (define_expand "ashrqi3"
1017 [(set (match_operand:QI 0 "register_operand" "=r")
1018 (ashiftrt:QI (match_operand:QI 1 "register_operand" "0")
1019 (match_operand:QI 2 "nonmemory_operand" "g")))]
1023 if (GET_CODE (operands[2]) != CONST_INT)
1024 operands[2] = gen_rtx_NEG (QImode, negate_rtx (QImode, operands[2]));
1028 [(set (match_operand:QI 0 "register_operand" "=r")
1029 (ashiftrt:QI (match_operand:QI 1 "register_operand" "0")
1030 (match_operand:QI 2 "immediate_operand" "I")))]
1035 [(set (match_operand:QI 0 "register_operand" "=r")
1036 (ashiftrt:QI (match_operand:QI 1 "register_operand" "0")
1037 (neg:QI (match_operand:QI 2 "register_operand" "r"))))]
1041 ;; HImode arithmetic shift right.
1042 (define_expand "ashrhi3"
1043 [(set (match_operand:HI 0 "register_operand" "=r")
1044 (ashiftrt:HI (match_operand:HI 1 "register_operand" "0")
1045 (match_operand:QI 2 "nonmemory_operand" "g")))]
1049 if (GET_CODE (operands[2]) != CONST_INT)
1050 operands[2] = gen_rtx_NEG (QImode, negate_rtx (QImode, operands[2]));
1054 [(set (match_operand:HI 0 "register_operand" "=r")
1055 (ashiftrt:HI (match_operand:HI 1 "register_operand" "0")
1056 (match_operand:QI 2 "immediate_operand" "L")))]
1059 if (INTVAL (operands[2]) <= 16)
1060 return \"dsra r%0,%2\";
1061 output_asm_insn (\"dsra r%0,16 ; ashrhi3 shiftcount > 16\", operands);
1062 return \"sra r%d0,%w2\";
1066 [(set (match_operand:HI 0 "register_operand" "=r")
1067 (ashiftrt:HI (match_operand:HI 1 "register_operand" "0")
1068 (neg:QI (match_operand:QI 2 "register_operand" "r"))))]
1073 ;; rotate instructions
1075 (define_insn "rotlqi3"
1076 [(set (match_operand:QI 0 "register_operand" "=r,r")
1077 (rotate:QI (match_operand:QI 1 "register_operand" "0,0")
1078 (match_operand:QI 2 "nonmemory_operand" "I,r")))]
1084 (define_insn "rotlhi3"
1085 [(set (match_operand:HI 0 "register_operand" "=r,r")
1086 (rotate:HI (match_operand:HI 1 "register_operand" "0,0")
1087 (match_operand:QI 2 "nonmemory_operand" "I,r")))]
1093 (define_insn "rotrqi3"
1094 [(set (match_operand:QI 0 "register_operand" "=r")
1095 (rotatert:QI (match_operand:QI 1 "register_operand" "0")
1096 (match_operand:QI 2 "register_operand" "r")))]
1098 "neg r%2,r%2\;scr r%0,r%2 ")
1100 (define_insn "rotrhi3"
1101 [(set (match_operand:HI 0 "register_operand" "=r")
1102 (rotatert:HI (match_operand:HI 1 "register_operand" "0")
1103 (match_operand:QI 2 "nonmemory_operand" "r")))]
1105 "neg r%2,r%2\;dscr r%0,r%2 ")
1109 ;; Special cases of bit-field insns which we should
1110 ;; recognize in preference to the general case.
1111 ;; These handle aligned 8-bit and 16-bit fields,
1112 ;; which can usually be done with move instructions.
1114 ;********************
1116 ;; Bit field instructions, general cases.
1117 ;; "o,d" constraint causes a nonoffsettable memref to match the "o"
1118 ;; so that its address is reloaded.
1120 ;; (define_insn "extv" ...
1122 ;; (define_insn "extzv" ...
1124 ;; (define_insn "insv" ...
1126 ;; Now recognize bit field insns that operate on registers
1127 ;; (or at least were intended to do so).
1130 ;; Special patterns for optimizing bit-field instructions.
1131 ;**************************************
1133 ; cc status test ops n.a. on 1750 ......... e.g. "sleu" on 68k:
1134 ; [(set (match_operand:QI 0 "general_operand" "=d")
1135 ; (leu (cc0) (const_int 0)))]
1137 ; "* cc_status = cc_prev_status;
1138 ; return \"sls %0\"; ")
1141 ;; Basic conditional jump instructions.
1145 (if_then_else (eq (cc0)
1147 (label_ref (match_operand 0 "" ""))
1150 "* return branch_or_jump (\"ez\", CODE_LABEL_NUMBER (operands[0]));
1155 (if_then_else (ne (cc0)
1157 (label_ref (match_operand 0 "" ""))
1160 "* return branch_or_jump (\"nz\", CODE_LABEL_NUMBER (operands[0]));
1165 (if_then_else (gt (cc0)
1167 (label_ref (match_operand 0 "" ""))
1170 "* return branch_or_jump (\"gt\", CODE_LABEL_NUMBER (operands[0]));
1175 (if_then_else (lt (cc0)
1177 (label_ref (match_operand 0 "" ""))
1180 "* return branch_or_jump (\"lt\", CODE_LABEL_NUMBER (operands[0]));
1185 (if_then_else (ge (cc0)
1187 (label_ref (match_operand 0 "" ""))
1190 "* return branch_or_jump (\"ge\", CODE_LABEL_NUMBER (operands[0]));
1195 (if_then_else (le (cc0)
1197 (label_ref (match_operand 0 "" ""))
1200 "* return branch_or_jump (\"le\", CODE_LABEL_NUMBER (operands[0]));
1204 ; no unsigned branches available on 1750. But GCC still needs them, so faking:
1208 (if_then_else (gtu (cc0)
1210 (label_ref (match_operand 0 "" ""))
1213 "jc gt,%l0 ; Warning: this should be an *unsigned* test!")
1217 (if_then_else (ltu (cc0)
1219 (label_ref (match_operand 0 "" ""))
1222 "jc lt,%l0 ; Warning: this should be an *unsigned* test!")
1226 (if_then_else (geu (cc0)
1228 (label_ref (match_operand 0 "" ""))
1231 "jc ge,%l0 ; Warning: this should be an *unsigned* test!")
1235 (if_then_else (leu (cc0)
1237 (label_ref (match_operand 0 "" ""))
1240 "jc le,%l0 ; Warning: this should be an *unsigned* test!")
1243 ;; Negated conditional jump instructions.
1247 (if_then_else (eq (cc0)
1250 (label_ref (match_operand 0 "" ""))))]
1252 "* return branch_or_jump (\"nz\", CODE_LABEL_NUMBER (operands[0]));
1257 (if_then_else (ne (cc0)
1260 (label_ref (match_operand 0 "" ""))))]
1262 "* return branch_or_jump (\"ez\", CODE_LABEL_NUMBER (operands[0]));
1267 (if_then_else (gt (cc0)
1270 (label_ref (match_operand 0 "" ""))))]
1272 "* return branch_or_jump (\"le\", CODE_LABEL_NUMBER (operands[0]));
1277 (if_then_else (lt (cc0)
1280 (label_ref (match_operand 0 "" ""))))]
1282 "* return branch_or_jump (\"ge\", CODE_LABEL_NUMBER (operands[0]));
1287 (if_then_else (ge (cc0)
1290 (label_ref (match_operand 0 "" ""))))]
1292 "* return branch_or_jump (\"lt\", CODE_LABEL_NUMBER (operands[0]));
1297 (if_then_else (le (cc0)
1300 (label_ref (match_operand 0 "" ""))))]
1302 "* return branch_or_jump (\"gt\", CODE_LABEL_NUMBER (operands[0]));
1306 ;; Negated unsigned conditional jump instructions (faked for 1750).
1310 (if_then_else (gtu (cc0)
1313 (label_ref (match_operand 0 "" ""))))]
1315 "jc le,%l0 ;inv.cond. ;Warning: this should be an *unsigned* test!")
1319 (if_then_else (ltu (cc0)
1322 (label_ref (match_operand 0 "" ""))))]
1324 "jc ge,%l0 ;inv.cond. ;Warning: this should be an *unsigned* test!")
1328 (if_then_else (geu (cc0)
1331 (label_ref (match_operand 0 "" ""))))]
1333 "jc lt,%l0 ;inv.cond. ;Warning: this should be an *unsigned* test!")
1337 (if_then_else (leu (cc0)
1340 (label_ref (match_operand 0 "" ""))))]
1342 "jc gt,%l0 ;inv.cond. ;Warning: this should be an *unsigned* test!")
1345 ;; 1750 note: CASE_VECTOR_PC_RELATIVE is not defined
1346 (define_insn "tablejump"
1348 (match_operand:QI 0 "register_operand" "b"))
1349 (use (label_ref (match_operand 1 "" "")))]
1351 "jc 15,0,r%0 ; tablejump label_ref=%1")
1354 ;; Unconditional jump
1357 (label_ref (match_operand 0 "" "")))]
1361 ;; Call subroutine, returning value in operand 0
1362 ;; (which must be a hard register).
1363 (define_insn "call_value"
1364 [(set (match_operand 0 "register_operand" "=r")
1365 (call (match_operand:QI 1 "memory_operand" "m")
1366 (match_operand:QI 2 "general_operand" "g")))]
1367 ;; Operand 2 not really used for 1750.
1369 "sjs r15,%1 ; return value in R0")
1371 ;; Call subroutine with no return value.
1373 ;; Operand 1 not really used in MIL-STD-1750.
1375 [(call (match_operand:QI 0 "memory_operand" "mp")
1376 (match_operand:QI 1 "general_operand" ""))]
1378 "sjs r15,%0 ; no return value")
1380 ;;;;;;;;;;;; 1750: NOT READY YET.
1382 [(call (match_operand:QI 0 "" "")
1383 (match_operand:QI 1 "" ""))]
1387 (define_insn "indirect_jump"
1388 [(set (pc) (match_operand:QI 0 "address_operand" "p"))]
1398 ;; Subtract One and Jump (if non-zero)
1400 [(set (match_operand:QI 0 "register_operand" "=r")
1401 (plus:QI (match_operand:QI 1 "register_operand" "%0")
1402 (match_operand:QI 2 "immediate_operand" "J")))
1403 (set (cc0) (match_dup 0))
1405 (if_then_else (ne (cc0) (const_int 0))
1406 (label_ref (match_operand 3 "" ""))
1409 "INTVAL(operands[2]) == -1"
1412 ;; Combine a Load Register with subsequent increment/decrement into a LIM
1414 [(set (match_operand:QI 0 "register_operand" "=r")
1415 (match_operand:QI 1 "register_operand" "b"))
1417 (plus:QI (match_dup 0)
1418 (match_operand:QI 2 "immediate_operand" "i")))]
1419 "REGNO(operands[1]) > 0"
1420 "lim r%0,%2,r%1 ; LR,inc/dec peephole")
1422 ;; Eliminate the redundant load in a store/load sequence
1424 [(set (mem:QI (plus:QI (match_operand:QI 0 "register_operand" "r")
1425 (match_operand:QI 1 "immediate_operand" "i")))
1426 (match_operand:QI 2 "register_operand" "r"))
1427 (set (match_operand:QI 3 "register_operand" "=r")
1428 (mem:QI (plus:QI (match_dup 0)
1431 "REGNO(operands[2]) == REGNO(operands[3])"
1432 "st r%2,%1,r%0 ; eliminated previous redundant load")