1 /* Optimize by combining instructions for GNU compiler.
2 Copyright (C) 1987, 1988, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010,
4 2011 Free Software Foundation, Inc.
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify it under
9 the terms of the GNU General Public License as published by the Free
10 Software Foundation; either version 3, or (at your option) any later
13 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
14 WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
22 /* This module is essentially the "combiner" phase of the U. of Arizona
23 Portable Optimizer, but redone to work on our list-structured
24 representation for RTL instead of their string representation.
26 The LOG_LINKS of each insn identify the most recent assignment
27 to each REG used in the insn. It is a list of previous insns,
28 each of which contains a SET for a REG that is used in this insn
29 and not used or set in between. LOG_LINKs never cross basic blocks.
30 They were set up by the preceding pass (lifetime analysis).
32 We try to combine each pair of insns joined by a logical link.
33 We also try to combine triples of insns A, B and C when
34 C has a link back to B and B has a link back to A.
36 LOG_LINKS does not have links for use of the CC0. They don't
37 need to, because the insn that sets the CC0 is always immediately
38 before the insn that tests it. So we always regard a branch
39 insn as having a logical link to the preceding insn. The same is true
40 for an insn explicitly using CC0.
42 We check (with use_crosses_set_p) to avoid combining in such a way
43 as to move a computation to a place where its value would be different.
45 Combination is done by mathematically substituting the previous
46 insn(s) values for the regs they set into the expressions in
47 the later insns that refer to these regs. If the result is a valid insn
48 for our target machine, according to the machine description,
49 we install it, delete the earlier insns, and update the data flow
50 information (LOG_LINKS and REG_NOTES) for what we did.
52 There are a few exceptions where the dataflow information isn't
53 completely updated (however this is only a local issue since it is
54 regenerated before the next pass that uses it):
56 - reg_live_length is not updated
57 - reg_n_refs is not adjusted in the rare case when a register is
58 no longer required in a computation
59 - there are extremely rare cases (see distribute_notes) when a
61 - a LOG_LINKS entry that refers to an insn with multiple SETs may be
62 removed because there is no way to know which register it was
65 To simplify substitution, we combine only when the earlier insn(s)
66 consist of only a single assignment. To simplify updating afterward,
67 we never combine when a subroutine call appears in the middle.
69 Since we do not represent assignments to CC0 explicitly except when that
70 is all an insn does, there is no LOG_LINKS entry in an insn that uses
71 the condition code for the insn that set the condition code.
72 Fortunately, these two insns must be consecutive.
73 Therefore, every JUMP_INSN is taken to have an implicit logical link
74 to the preceding insn. This is not quite right, since non-jumps can
75 also use the condition code; but in practice such insns would not
80 #include "coretypes.h"
87 #include "hard-reg-set.h"
88 #include "basic-block.h"
89 #include "insn-config.h"
91 /* Include expr.h after insn-config.h so we get HAVE_conditional_move. */
93 #include "insn-attr.h"
95 #include "diagnostic-core.h"
98 #include "insn-codes.h"
99 #include "rtlhooks-def.h"
100 /* Include output.h for dump_file. */
104 #include "tree-pass.h"
109 /* Number of attempts to combine instructions in this function. */
111 static int combine_attempts;
113 /* Number of attempts that got as far as substitution in this function. */
115 static int combine_merges;
117 /* Number of instructions combined with added SETs in this function. */
119 static int combine_extras;
121 /* Number of instructions combined in this function. */
123 static int combine_successes;
125 /* Totals over entire compilation. */
127 static int total_attempts, total_merges, total_extras, total_successes;
129 /* combine_instructions may try to replace the right hand side of the
130 second instruction with the value of an associated REG_EQUAL note
131 before throwing it at try_combine. That is problematic when there
132 is a REG_DEAD note for a register used in the old right hand side
133 and can cause distribute_notes to do wrong things. This is the
134 second instruction if it has been so modified, null otherwise. */
138 /* When I2MOD is nonnull, this is a copy of the old right hand side. */
140 static rtx i2mod_old_rhs;
142 /* When I2MOD is nonnull, this is a copy of the new right hand side. */
144 static rtx i2mod_new_rhs;
146 typedef struct reg_stat_struct {
147 /* Record last point of death of (hard or pseudo) register n. */
150 /* Record last point of modification of (hard or pseudo) register n. */
153 /* The next group of fields allows the recording of the last value assigned
154 to (hard or pseudo) register n. We use this information to see if an
155 operation being processed is redundant given a prior operation performed
156 on the register. For example, an `and' with a constant is redundant if
157 all the zero bits are already known to be turned off.
159 We use an approach similar to that used by cse, but change it in the
162 (1) We do not want to reinitialize at each label.
163 (2) It is useful, but not critical, to know the actual value assigned
164 to a register. Often just its form is helpful.
166 Therefore, we maintain the following fields:
168 last_set_value the last value assigned
169 last_set_label records the value of label_tick when the
170 register was assigned
171 last_set_table_tick records the value of label_tick when a
172 value using the register is assigned
173 last_set_invalid set to nonzero when it is not valid
174 to use the value of this register in some
177 To understand the usage of these tables, it is important to understand
178 the distinction between the value in last_set_value being valid and
179 the register being validly contained in some other expression in the
182 (The next two parameters are out of date).
184 reg_stat[i].last_set_value is valid if it is nonzero, and either
185 reg_n_sets[i] is 1 or reg_stat[i].last_set_label == label_tick.
187 Register I may validly appear in any expression returned for the value
188 of another register if reg_n_sets[i] is 1. It may also appear in the
189 value for register J if reg_stat[j].last_set_invalid is zero, or
190 reg_stat[i].last_set_label < reg_stat[j].last_set_label.
192 If an expression is found in the table containing a register which may
193 not validly appear in an expression, the register is replaced by
194 something that won't match, (clobber (const_int 0)). */
196 /* Record last value assigned to (hard or pseudo) register n. */
200 /* Record the value of label_tick when an expression involving register n
201 is placed in last_set_value. */
203 int last_set_table_tick;
205 /* Record the value of label_tick when the value for register n is placed in
210 /* These fields are maintained in parallel with last_set_value and are
211 used to store the mode in which the register was last set, the bits
212 that were known to be zero when it was last set, and the number of
213 sign bits copies it was known to have when it was last set. */
215 unsigned HOST_WIDE_INT last_set_nonzero_bits;
216 char last_set_sign_bit_copies;
217 ENUM_BITFIELD(machine_mode) last_set_mode : 8;
219 /* Set nonzero if references to register n in expressions should not be
220 used. last_set_invalid is set nonzero when this register is being
221 assigned to and last_set_table_tick == label_tick. */
223 char last_set_invalid;
225 /* Some registers that are set more than once and used in more than one
226 basic block are nevertheless always set in similar ways. For example,
227 a QImode register may be loaded from memory in two places on a machine
228 where byte loads zero extend.
230 We record in the following fields if a register has some leading bits
231 that are always equal to the sign bit, and what we know about the
232 nonzero bits of a register, specifically which bits are known to be
235 If an entry is zero, it means that we don't know anything special. */
237 unsigned char sign_bit_copies;
239 unsigned HOST_WIDE_INT nonzero_bits;
241 /* Record the value of the label_tick when the last truncation
242 happened. The field truncated_to_mode is only valid if
243 truncation_label == label_tick. */
245 int truncation_label;
247 /* Record the last truncation seen for this register. If truncation
248 is not a nop to this mode we might be able to save an explicit
249 truncation if we know that value already contains a truncated
252 ENUM_BITFIELD(machine_mode) truncated_to_mode : 8;
255 DEF_VEC_O(reg_stat_type);
256 DEF_VEC_ALLOC_O(reg_stat_type,heap);
258 static VEC(reg_stat_type,heap) *reg_stat;
260 /* Record the luid of the last insn that invalidated memory
261 (anything that writes memory, and subroutine calls, but not pushes). */
263 static int mem_last_set;
265 /* Record the luid of the last CALL_INSN
266 so we can tell whether a potential combination crosses any calls. */
268 static int last_call_luid;
270 /* When `subst' is called, this is the insn that is being modified
271 (by combining in a previous insn). The PATTERN of this insn
272 is still the old pattern partially modified and it should not be
273 looked at, but this may be used to examine the successors of the insn
274 to judge whether a simplification is valid. */
276 static rtx subst_insn;
278 /* This is the lowest LUID that `subst' is currently dealing with.
279 get_last_value will not return a value if the register was set at or
280 after this LUID. If not for this mechanism, we could get confused if
281 I2 or I1 in try_combine were an insn that used the old value of a register
282 to obtain a new value. In that case, we might erroneously get the
283 new value of the register when we wanted the old one. */
285 static int subst_low_luid;
287 /* This contains any hard registers that are used in newpat; reg_dead_at_p
288 must consider all these registers to be always live. */
290 static HARD_REG_SET newpat_used_regs;
292 /* This is an insn to which a LOG_LINKS entry has been added. If this
293 insn is the earlier than I2 or I3, combine should rescan starting at
296 static rtx added_links_insn;
298 /* Basic block in which we are performing combines. */
299 static basic_block this_basic_block;
300 static bool optimize_this_for_speed_p;
303 /* Length of the currently allocated uid_insn_cost array. */
305 static int max_uid_known;
307 /* The following array records the insn_rtx_cost for every insn
308 in the instruction stream. */
310 static int *uid_insn_cost;
312 /* The following array records the LOG_LINKS for every insn in the
313 instruction stream as struct insn_link pointers. */
317 struct insn_link *next;
320 static struct insn_link **uid_log_links;
322 #define INSN_COST(INSN) (uid_insn_cost[INSN_UID (INSN)])
323 #define LOG_LINKS(INSN) (uid_log_links[INSN_UID (INSN)])
325 #define FOR_EACH_LOG_LINK(L, INSN) \
326 for ((L) = LOG_LINKS (INSN); (L); (L) = (L)->next)
328 /* Links for LOG_LINKS are allocated from this obstack. */
330 static struct obstack insn_link_obstack;
332 /* Allocate a link. */
334 static inline struct insn_link *
335 alloc_insn_link (rtx insn, struct insn_link *next)
338 = (struct insn_link *) obstack_alloc (&insn_link_obstack,
339 sizeof (struct insn_link));
345 /* Incremented for each basic block. */
347 static int label_tick;
349 /* Reset to label_tick for each extended basic block in scanning order. */
351 static int label_tick_ebb_start;
353 /* Mode used to compute significance in reg_stat[].nonzero_bits. It is the
354 largest integer mode that can fit in HOST_BITS_PER_WIDE_INT. */
356 static enum machine_mode nonzero_bits_mode;
358 /* Nonzero when reg_stat[].nonzero_bits and reg_stat[].sign_bit_copies can
359 be safely used. It is zero while computing them and after combine has
360 completed. This former test prevents propagating values based on
361 previously set values, which can be incorrect if a variable is modified
364 static int nonzero_sign_valid;
367 /* Record one modification to rtl structure
368 to be undone by storing old_contents into *where. */
370 enum undo_kind { UNDO_RTX, UNDO_INT, UNDO_MODE };
376 union { rtx r; int i; enum machine_mode m; } old_contents;
377 union { rtx *r; int *i; } where;
380 /* Record a bunch of changes to be undone, up to MAX_UNDO of them.
381 num_undo says how many are currently recorded.
383 other_insn is nonzero if we have modified some other insn in the process
384 of working on subst_insn. It must be verified too. */
393 static struct undobuf undobuf;
395 /* Number of times the pseudo being substituted for
396 was found and replaced. */
398 static int n_occurrences;
400 static rtx reg_nonzero_bits_for_combine (const_rtx, enum machine_mode, const_rtx,
402 unsigned HOST_WIDE_INT,
403 unsigned HOST_WIDE_INT *);
404 static rtx reg_num_sign_bit_copies_for_combine (const_rtx, enum machine_mode, const_rtx,
406 unsigned int, unsigned int *);
407 static void do_SUBST (rtx *, rtx);
408 static void do_SUBST_INT (int *, int);
409 static void init_reg_last (void);
410 static void setup_incoming_promotions (rtx);
411 static void set_nonzero_bits_and_sign_copies (rtx, const_rtx, void *);
412 static int cant_combine_insn_p (rtx);
413 static int can_combine_p (rtx, rtx, rtx, rtx, rtx, rtx, rtx *, rtx *);
414 static int combinable_i3pat (rtx, rtx *, rtx, rtx, rtx, int, int, rtx *);
415 static int contains_muldiv (rtx);
416 static rtx try_combine (rtx, rtx, rtx, rtx, int *, rtx);
417 static void undo_all (void);
418 static void undo_commit (void);
419 static rtx *find_split_point (rtx *, rtx, bool);
420 static rtx subst (rtx, rtx, rtx, int, int, int);
421 static rtx combine_simplify_rtx (rtx, enum machine_mode, int, int);
422 static rtx simplify_if_then_else (rtx);
423 static rtx simplify_set (rtx);
424 static rtx simplify_logical (rtx);
425 static rtx expand_compound_operation (rtx);
426 static const_rtx expand_field_assignment (const_rtx);
427 static rtx make_extraction (enum machine_mode, rtx, HOST_WIDE_INT,
428 rtx, unsigned HOST_WIDE_INT, int, int, int);
429 static rtx extract_left_shift (rtx, int);
430 static rtx make_compound_operation (rtx, enum rtx_code);
431 static int get_pos_from_mask (unsigned HOST_WIDE_INT,
432 unsigned HOST_WIDE_INT *);
433 static rtx canon_reg_for_combine (rtx, rtx);
434 static rtx force_to_mode (rtx, enum machine_mode,
435 unsigned HOST_WIDE_INT, int);
436 static rtx if_then_else_cond (rtx, rtx *, rtx *);
437 static rtx known_cond (rtx, enum rtx_code, rtx, rtx);
438 static int rtx_equal_for_field_assignment_p (rtx, rtx);
439 static rtx make_field_assignment (rtx);
440 static rtx apply_distributive_law (rtx);
441 static rtx distribute_and_simplify_rtx (rtx, int);
442 static rtx simplify_and_const_int_1 (enum machine_mode, rtx,
443 unsigned HOST_WIDE_INT);
444 static rtx simplify_and_const_int (rtx, enum machine_mode, rtx,
445 unsigned HOST_WIDE_INT);
446 static int merge_outer_ops (enum rtx_code *, HOST_WIDE_INT *, enum rtx_code,
447 HOST_WIDE_INT, enum machine_mode, int *);
448 static rtx simplify_shift_const_1 (enum rtx_code, enum machine_mode, rtx, int);
449 static rtx simplify_shift_const (rtx, enum rtx_code, enum machine_mode, rtx,
451 static int recog_for_combine (rtx *, rtx, rtx *);
452 static rtx gen_lowpart_for_combine (enum machine_mode, rtx);
453 static enum rtx_code simplify_compare_const (enum rtx_code, rtx, rtx *);
454 static enum rtx_code simplify_comparison (enum rtx_code, rtx *, rtx *);
455 static void update_table_tick (rtx);
456 static void record_value_for_reg (rtx, rtx, rtx);
457 static void check_promoted_subreg (rtx, rtx);
458 static void record_dead_and_set_regs_1 (rtx, const_rtx, void *);
459 static void record_dead_and_set_regs (rtx);
460 static int get_last_value_validate (rtx *, rtx, int, int);
461 static rtx get_last_value (const_rtx);
462 static int use_crosses_set_p (const_rtx, int);
463 static void reg_dead_at_p_1 (rtx, const_rtx, void *);
464 static int reg_dead_at_p (rtx, rtx);
465 static void move_deaths (rtx, rtx, int, rtx, rtx *);
466 static int reg_bitfield_target_p (rtx, rtx);
467 static void distribute_notes (rtx, rtx, rtx, rtx, rtx, rtx, rtx);
468 static void distribute_links (struct insn_link *);
469 static void mark_used_regs_combine (rtx);
470 static void record_promoted_value (rtx, rtx);
471 static int unmentioned_reg_p_1 (rtx *, void *);
472 static bool unmentioned_reg_p (rtx, rtx);
473 static int record_truncated_value (rtx *, void *);
474 static void record_truncated_values (rtx *, void *);
475 static bool reg_truncated_to_mode (enum machine_mode, const_rtx);
476 static rtx gen_lowpart_or_truncate (enum machine_mode, rtx);
479 /* It is not safe to use ordinary gen_lowpart in combine.
480 See comments in gen_lowpart_for_combine. */
481 #undef RTL_HOOKS_GEN_LOWPART
482 #define RTL_HOOKS_GEN_LOWPART gen_lowpart_for_combine
484 /* Our implementation of gen_lowpart never emits a new pseudo. */
485 #undef RTL_HOOKS_GEN_LOWPART_NO_EMIT
486 #define RTL_HOOKS_GEN_LOWPART_NO_EMIT gen_lowpart_for_combine
488 #undef RTL_HOOKS_REG_NONZERO_REG_BITS
489 #define RTL_HOOKS_REG_NONZERO_REG_BITS reg_nonzero_bits_for_combine
491 #undef RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES
492 #define RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES reg_num_sign_bit_copies_for_combine
494 #undef RTL_HOOKS_REG_TRUNCATED_TO_MODE
495 #define RTL_HOOKS_REG_TRUNCATED_TO_MODE reg_truncated_to_mode
497 static const struct rtl_hooks combine_rtl_hooks = RTL_HOOKS_INITIALIZER;
500 /* Try to split PATTERN found in INSN. This returns NULL_RTX if
501 PATTERN can not be split. Otherwise, it returns an insn sequence.
502 This is a wrapper around split_insns which ensures that the
503 reg_stat vector is made larger if the splitter creates a new
507 combine_split_insns (rtx pattern, rtx insn)
512 ret = split_insns (pattern, insn);
513 nregs = max_reg_num ();
514 if (nregs > VEC_length (reg_stat_type, reg_stat))
515 VEC_safe_grow_cleared (reg_stat_type, heap, reg_stat, nregs);
519 /* This is used by find_single_use to locate an rtx in LOC that
520 contains exactly one use of DEST, which is typically either a REG
521 or CC0. It returns a pointer to the innermost rtx expression
522 containing DEST. Appearances of DEST that are being used to
523 totally replace it are not counted. */
526 find_single_use_1 (rtx dest, rtx *loc)
529 enum rtx_code code = GET_CODE (x);
547 /* If the destination is anything other than CC0, PC, a REG or a SUBREG
548 of a REG that occupies all of the REG, the insn uses DEST if
549 it is mentioned in the destination or the source. Otherwise, we
550 need just check the source. */
551 if (GET_CODE (SET_DEST (x)) != CC0
552 && GET_CODE (SET_DEST (x)) != PC
553 && !REG_P (SET_DEST (x))
554 && ! (GET_CODE (SET_DEST (x)) == SUBREG
555 && REG_P (SUBREG_REG (SET_DEST (x)))
556 && (((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x))))
557 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
558 == ((GET_MODE_SIZE (GET_MODE (SET_DEST (x)))
559 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD))))
562 return find_single_use_1 (dest, &SET_SRC (x));
566 return find_single_use_1 (dest, &XEXP (x, 0));
572 /* If it wasn't one of the common cases above, check each expression and
573 vector of this code. Look for a unique usage of DEST. */
575 fmt = GET_RTX_FORMAT (code);
576 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
580 if (dest == XEXP (x, i)
581 || (REG_P (dest) && REG_P (XEXP (x, i))
582 && REGNO (dest) == REGNO (XEXP (x, i))))
585 this_result = find_single_use_1 (dest, &XEXP (x, i));
588 result = this_result;
589 else if (this_result)
590 /* Duplicate usage. */
593 else if (fmt[i] == 'E')
597 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
599 if (XVECEXP (x, i, j) == dest
601 && REG_P (XVECEXP (x, i, j))
602 && REGNO (XVECEXP (x, i, j)) == REGNO (dest)))
605 this_result = find_single_use_1 (dest, &XVECEXP (x, i, j));
608 result = this_result;
609 else if (this_result)
619 /* See if DEST, produced in INSN, is used only a single time in the
620 sequel. If so, return a pointer to the innermost rtx expression in which
623 If PLOC is nonzero, *PLOC is set to the insn containing the single use.
625 If DEST is cc0_rtx, we look only at the next insn. In that case, we don't
626 care about REG_DEAD notes or LOG_LINKS.
628 Otherwise, we find the single use by finding an insn that has a
629 LOG_LINKS pointing at INSN and has a REG_DEAD note for DEST. If DEST is
630 only referenced once in that insn, we know that it must be the first
631 and last insn referencing DEST. */
634 find_single_use (rtx dest, rtx insn, rtx *ploc)
639 struct insn_link *link;
644 next = NEXT_INSN (insn);
646 || (!NONJUMP_INSN_P (next) && !JUMP_P (next)))
649 result = find_single_use_1 (dest, &PATTERN (next));
659 bb = BLOCK_FOR_INSN (insn);
660 for (next = NEXT_INSN (insn);
661 next && BLOCK_FOR_INSN (next) == bb;
662 next = NEXT_INSN (next))
663 if (INSN_P (next) && dead_or_set_p (next, dest))
665 FOR_EACH_LOG_LINK (link, next)
666 if (link->insn == insn)
671 result = find_single_use_1 (dest, &PATTERN (next));
681 /* Substitute NEWVAL, an rtx expression, into INTO, a place in some
682 insn. The substitution can be undone by undo_all. If INTO is already
683 set to NEWVAL, do not record this change. Because computing NEWVAL might
684 also call SUBST, we have to compute it before we put anything into
688 do_SUBST (rtx *into, rtx newval)
693 if (oldval == newval)
696 /* We'd like to catch as many invalid transformations here as
697 possible. Unfortunately, there are way too many mode changes
698 that are perfectly valid, so we'd waste too much effort for
699 little gain doing the checks here. Focus on catching invalid
700 transformations involving integer constants. */
701 if (GET_MODE_CLASS (GET_MODE (oldval)) == MODE_INT
702 && CONST_INT_P (newval))
704 /* Sanity check that we're replacing oldval with a CONST_INT
705 that is a valid sign-extension for the original mode. */
706 gcc_assert (INTVAL (newval)
707 == trunc_int_for_mode (INTVAL (newval), GET_MODE (oldval)));
709 /* Replacing the operand of a SUBREG or a ZERO_EXTEND with a
710 CONST_INT is not valid, because after the replacement, the
711 original mode would be gone. Unfortunately, we can't tell
712 when do_SUBST is called to replace the operand thereof, so we
713 perform this test on oldval instead, checking whether an
714 invalid replacement took place before we got here. */
715 gcc_assert (!(GET_CODE (oldval) == SUBREG
716 && CONST_INT_P (SUBREG_REG (oldval))));
717 gcc_assert (!(GET_CODE (oldval) == ZERO_EXTEND
718 && CONST_INT_P (XEXP (oldval, 0))));
722 buf = undobuf.frees, undobuf.frees = buf->next;
724 buf = XNEW (struct undo);
726 buf->kind = UNDO_RTX;
728 buf->old_contents.r = oldval;
731 buf->next = undobuf.undos, undobuf.undos = buf;
734 #define SUBST(INTO, NEWVAL) do_SUBST(&(INTO), (NEWVAL))
736 /* Similar to SUBST, but NEWVAL is an int expression. Note that substitution
737 for the value of a HOST_WIDE_INT value (including CONST_INT) is
741 do_SUBST_INT (int *into, int newval)
746 if (oldval == newval)
750 buf = undobuf.frees, undobuf.frees = buf->next;
752 buf = XNEW (struct undo);
754 buf->kind = UNDO_INT;
756 buf->old_contents.i = oldval;
759 buf->next = undobuf.undos, undobuf.undos = buf;
762 #define SUBST_INT(INTO, NEWVAL) do_SUBST_INT(&(INTO), (NEWVAL))
764 /* Similar to SUBST, but just substitute the mode. This is used when
765 changing the mode of a pseudo-register, so that any other
766 references to the entry in the regno_reg_rtx array will change as
770 do_SUBST_MODE (rtx *into, enum machine_mode newval)
773 enum machine_mode oldval = GET_MODE (*into);
775 if (oldval == newval)
779 buf = undobuf.frees, undobuf.frees = buf->next;
781 buf = XNEW (struct undo);
783 buf->kind = UNDO_MODE;
785 buf->old_contents.m = oldval;
786 adjust_reg_mode (*into, newval);
788 buf->next = undobuf.undos, undobuf.undos = buf;
791 #define SUBST_MODE(INTO, NEWVAL) do_SUBST_MODE(&(INTO), (NEWVAL))
793 /* Subroutine of try_combine. Determine whether the replacement patterns
794 NEWPAT, NEWI2PAT and NEWOTHERPAT are cheaper according to insn_rtx_cost
795 than the original sequence I0, I1, I2, I3 and undobuf.other_insn. Note
796 that I0, I1 and/or NEWI2PAT may be NULL_RTX. Similarly, NEWOTHERPAT and
797 undobuf.other_insn may also both be NULL_RTX. Return false if the cost
798 of all the instructions can be estimated and the replacements are more
799 expensive than the original sequence. */
802 combine_validate_cost (rtx i0, rtx i1, rtx i2, rtx i3, rtx newpat,
803 rtx newi2pat, rtx newotherpat)
805 int i0_cost, i1_cost, i2_cost, i3_cost;
806 int new_i2_cost, new_i3_cost;
807 int old_cost, new_cost;
809 /* Lookup the original insn_rtx_costs. */
810 i2_cost = INSN_COST (i2);
811 i3_cost = INSN_COST (i3);
815 i1_cost = INSN_COST (i1);
818 i0_cost = INSN_COST (i0);
819 old_cost = (i0_cost > 0 && i1_cost > 0 && i2_cost > 0 && i3_cost > 0
820 ? i0_cost + i1_cost + i2_cost + i3_cost : 0);
824 old_cost = (i1_cost > 0 && i2_cost > 0 && i3_cost > 0
825 ? i1_cost + i2_cost + i3_cost : 0);
831 old_cost = (i2_cost > 0 && i3_cost > 0) ? i2_cost + i3_cost : 0;
832 i1_cost = i0_cost = 0;
835 /* Calculate the replacement insn_rtx_costs. */
836 new_i3_cost = insn_rtx_cost (newpat, optimize_this_for_speed_p);
839 new_i2_cost = insn_rtx_cost (newi2pat, optimize_this_for_speed_p);
840 new_cost = (new_i2_cost > 0 && new_i3_cost > 0)
841 ? new_i2_cost + new_i3_cost : 0;
845 new_cost = new_i3_cost;
849 if (undobuf.other_insn)
851 int old_other_cost, new_other_cost;
853 old_other_cost = INSN_COST (undobuf.other_insn);
854 new_other_cost = insn_rtx_cost (newotherpat, optimize_this_for_speed_p);
855 if (old_other_cost > 0 && new_other_cost > 0)
857 old_cost += old_other_cost;
858 new_cost += new_other_cost;
864 /* Disallow this combination if both new_cost and old_cost are greater than
865 zero, and new_cost is greater than old cost. */
866 if (old_cost > 0 && new_cost > old_cost)
873 "rejecting combination of insns %d, %d, %d and %d\n",
874 INSN_UID (i0), INSN_UID (i1), INSN_UID (i2),
876 fprintf (dump_file, "original costs %d + %d + %d + %d = %d\n",
877 i0_cost, i1_cost, i2_cost, i3_cost, old_cost);
882 "rejecting combination of insns %d, %d and %d\n",
883 INSN_UID (i1), INSN_UID (i2), INSN_UID (i3));
884 fprintf (dump_file, "original costs %d + %d + %d = %d\n",
885 i1_cost, i2_cost, i3_cost, old_cost);
890 "rejecting combination of insns %d and %d\n",
891 INSN_UID (i2), INSN_UID (i3));
892 fprintf (dump_file, "original costs %d + %d = %d\n",
893 i2_cost, i3_cost, old_cost);
898 fprintf (dump_file, "replacement costs %d + %d = %d\n",
899 new_i2_cost, new_i3_cost, new_cost);
902 fprintf (dump_file, "replacement cost %d\n", new_cost);
908 /* Update the uid_insn_cost array with the replacement costs. */
909 INSN_COST (i2) = new_i2_cost;
910 INSN_COST (i3) = new_i3_cost;
922 /* Delete any insns that copy a register to itself. */
925 delete_noop_moves (void)
932 for (insn = BB_HEAD (bb); insn != NEXT_INSN (BB_END (bb)); insn = next)
934 next = NEXT_INSN (insn);
935 if (INSN_P (insn) && noop_move_p (insn))
938 fprintf (dump_file, "deleting noop move %d\n", INSN_UID (insn));
940 delete_insn_and_edges (insn);
947 /* Fill in log links field for all insns. */
950 create_log_links (void)
954 df_ref *def_vec, *use_vec;
956 next_use = XCNEWVEC (rtx, max_reg_num ());
958 /* Pass through each block from the end, recording the uses of each
959 register and establishing log links when def is encountered.
960 Note that we do not clear next_use array in order to save time,
961 so we have to test whether the use is in the same basic block as def.
963 There are a few cases below when we do not consider the definition or
964 usage -- these are taken from original flow.c did. Don't ask me why it is
965 done this way; I don't know and if it works, I don't want to know. */
969 FOR_BB_INSNS_REVERSE (bb, insn)
971 if (!NONDEBUG_INSN_P (insn))
974 /* Log links are created only once. */
975 gcc_assert (!LOG_LINKS (insn));
977 for (def_vec = DF_INSN_DEFS (insn); *def_vec; def_vec++)
979 df_ref def = *def_vec;
980 int regno = DF_REF_REGNO (def);
983 if (!next_use[regno])
986 /* Do not consider if it is pre/post modification in MEM. */
987 if (DF_REF_FLAGS (def) & DF_REF_PRE_POST_MODIFY)
990 /* Do not make the log link for frame pointer. */
991 if ((regno == FRAME_POINTER_REGNUM
992 && (! reload_completed || frame_pointer_needed))
993 #if !HARD_FRAME_POINTER_IS_FRAME_POINTER
994 || (regno == HARD_FRAME_POINTER_REGNUM
995 && (! reload_completed || frame_pointer_needed))
997 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
998 || (regno == ARG_POINTER_REGNUM && fixed_regs[regno])
1003 use_insn = next_use[regno];
1004 if (BLOCK_FOR_INSN (use_insn) == bb)
1008 We don't build a LOG_LINK for hard registers contained
1009 in ASM_OPERANDs. If these registers get replaced,
1010 we might wind up changing the semantics of the insn,
1011 even if reload can make what appear to be valid
1012 assignments later. */
1013 if (regno >= FIRST_PSEUDO_REGISTER
1014 || asm_noperands (PATTERN (use_insn)) < 0)
1016 /* Don't add duplicate links between instructions. */
1017 struct insn_link *links;
1018 FOR_EACH_LOG_LINK (links, use_insn)
1019 if (insn == links->insn)
1023 LOG_LINKS (use_insn)
1024 = alloc_insn_link (insn, LOG_LINKS (use_insn));
1027 next_use[regno] = NULL_RTX;
1030 for (use_vec = DF_INSN_USES (insn); *use_vec; use_vec++)
1032 df_ref use = *use_vec;
1033 int regno = DF_REF_REGNO (use);
1035 /* Do not consider the usage of the stack pointer
1036 by function call. */
1037 if (DF_REF_FLAGS (use) & DF_REF_CALL_STACK_USAGE)
1040 next_use[regno] = insn;
1048 /* Walk the LOG_LINKS of insn B to see if we find a reference to A. Return
1049 true if we found a LOG_LINK that proves that A feeds B. This only works
1050 if there are no instructions between A and B which could have a link
1051 depending on A, since in that case we would not record a link for B.
1052 We also check the implicit dependency created by a cc0 setter/user
1056 insn_a_feeds_b (rtx a, rtx b)
1058 struct insn_link *links;
1059 FOR_EACH_LOG_LINK (links, b)
1060 if (links->insn == a)
1069 /* Main entry point for combiner. F is the first insn of the function.
1070 NREGS is the first unused pseudo-reg number.
1072 Return nonzero if the combiner has turned an indirect jump
1073 instruction into a direct jump. */
1075 combine_instructions (rtx f, unsigned int nregs)
1081 struct insn_link *links, *nextlinks;
1083 basic_block last_bb;
1085 int new_direct_jump_p = 0;
1087 for (first = f; first && !INSN_P (first); )
1088 first = NEXT_INSN (first);
1092 combine_attempts = 0;
1095 combine_successes = 0;
1097 rtl_hooks = combine_rtl_hooks;
1099 VEC_safe_grow_cleared (reg_stat_type, heap, reg_stat, nregs);
1101 init_recog_no_volatile ();
1103 /* Allocate array for insn info. */
1104 max_uid_known = get_max_uid ();
1105 uid_log_links = XCNEWVEC (struct insn_link *, max_uid_known + 1);
1106 uid_insn_cost = XCNEWVEC (int, max_uid_known + 1);
1107 gcc_obstack_init (&insn_link_obstack);
1109 nonzero_bits_mode = mode_for_size (HOST_BITS_PER_WIDE_INT, MODE_INT, 0);
1111 /* Don't use reg_stat[].nonzero_bits when computing it. This can cause
1112 problems when, for example, we have j <<= 1 in a loop. */
1114 nonzero_sign_valid = 0;
1115 label_tick = label_tick_ebb_start = 1;
1117 /* Scan all SETs and see if we can deduce anything about what
1118 bits are known to be zero for some registers and how many copies
1119 of the sign bit are known to exist for those registers.
1121 Also set any known values so that we can use it while searching
1122 for what bits are known to be set. */
1124 setup_incoming_promotions (first);
1125 /* Allow the entry block and the first block to fall into the same EBB.
1126 Conceptually the incoming promotions are assigned to the entry block. */
1127 last_bb = ENTRY_BLOCK_PTR;
1129 create_log_links ();
1130 FOR_EACH_BB (this_basic_block)
1132 optimize_this_for_speed_p = optimize_bb_for_speed_p (this_basic_block);
1137 if (!single_pred_p (this_basic_block)
1138 || single_pred (this_basic_block) != last_bb)
1139 label_tick_ebb_start = label_tick;
1140 last_bb = this_basic_block;
1142 FOR_BB_INSNS (this_basic_block, insn)
1143 if (INSN_P (insn) && BLOCK_FOR_INSN (insn))
1149 subst_low_luid = DF_INSN_LUID (insn);
1152 note_stores (PATTERN (insn), set_nonzero_bits_and_sign_copies,
1154 record_dead_and_set_regs (insn);
1157 for (links = REG_NOTES (insn); links; links = XEXP (links, 1))
1158 if (REG_NOTE_KIND (links) == REG_INC)
1159 set_nonzero_bits_and_sign_copies (XEXP (links, 0), NULL_RTX,
1163 /* Record the current insn_rtx_cost of this instruction. */
1164 if (NONJUMP_INSN_P (insn))
1165 INSN_COST (insn) = insn_rtx_cost (PATTERN (insn),
1166 optimize_this_for_speed_p);
1168 fprintf(dump_file, "insn_cost %d: %d\n",
1169 INSN_UID (insn), INSN_COST (insn));
1173 nonzero_sign_valid = 1;
1175 /* Now scan all the insns in forward order. */
1176 label_tick = label_tick_ebb_start = 1;
1178 setup_incoming_promotions (first);
1179 last_bb = ENTRY_BLOCK_PTR;
1181 FOR_EACH_BB (this_basic_block)
1183 rtx last_combined_insn = NULL_RTX;
1184 optimize_this_for_speed_p = optimize_bb_for_speed_p (this_basic_block);
1189 if (!single_pred_p (this_basic_block)
1190 || single_pred (this_basic_block) != last_bb)
1191 label_tick_ebb_start = label_tick;
1192 last_bb = this_basic_block;
1194 rtl_profile_for_bb (this_basic_block);
1195 for (insn = BB_HEAD (this_basic_block);
1196 insn != NEXT_INSN (BB_END (this_basic_block));
1197 insn = next ? next : NEXT_INSN (insn))
1200 if (NONDEBUG_INSN_P (insn))
1202 while (last_combined_insn
1203 && INSN_DELETED_P (last_combined_insn))
1204 last_combined_insn = PREV_INSN (last_combined_insn);
1205 if (last_combined_insn == NULL_RTX
1206 || BARRIER_P (last_combined_insn)
1207 || BLOCK_FOR_INSN (last_combined_insn) != this_basic_block
1208 || DF_INSN_LUID (last_combined_insn) <= DF_INSN_LUID (insn))
1209 last_combined_insn = insn;
1211 /* See if we know about function return values before this
1212 insn based upon SUBREG flags. */
1213 check_promoted_subreg (insn, PATTERN (insn));
1215 /* See if we can find hardregs and subreg of pseudos in
1216 narrower modes. This could help turning TRUNCATEs
1218 note_uses (&PATTERN (insn), record_truncated_values, NULL);
1220 /* Try this insn with each insn it links back to. */
1222 FOR_EACH_LOG_LINK (links, insn)
1223 if ((next = try_combine (insn, links->insn, NULL_RTX,
1224 NULL_RTX, &new_direct_jump_p,
1225 last_combined_insn)) != 0)
1228 /* Try each sequence of three linked insns ending with this one. */
1230 FOR_EACH_LOG_LINK (links, insn)
1232 rtx link = links->insn;
1234 /* If the linked insn has been replaced by a note, then there
1235 is no point in pursuing this chain any further. */
1239 FOR_EACH_LOG_LINK (nextlinks, link)
1240 if ((next = try_combine (insn, link, nextlinks->insn,
1241 NULL_RTX, &new_direct_jump_p,
1242 last_combined_insn)) != 0)
1247 /* Try to combine a jump insn that uses CC0
1248 with a preceding insn that sets CC0, and maybe with its
1249 logical predecessor as well.
1250 This is how we make decrement-and-branch insns.
1251 We need this special code because data flow connections
1252 via CC0 do not get entered in LOG_LINKS. */
1255 && (prev = prev_nonnote_insn (insn)) != 0
1256 && NONJUMP_INSN_P (prev)
1257 && sets_cc0_p (PATTERN (prev)))
1259 if ((next = try_combine (insn, prev, NULL_RTX, NULL_RTX,
1261 last_combined_insn)) != 0)
1264 FOR_EACH_LOG_LINK (nextlinks, prev)
1265 if ((next = try_combine (insn, prev, nextlinks->insn,
1266 NULL_RTX, &new_direct_jump_p,
1267 last_combined_insn)) != 0)
1271 /* Do the same for an insn that explicitly references CC0. */
1272 if (NONJUMP_INSN_P (insn)
1273 && (prev = prev_nonnote_insn (insn)) != 0
1274 && NONJUMP_INSN_P (prev)
1275 && sets_cc0_p (PATTERN (prev))
1276 && GET_CODE (PATTERN (insn)) == SET
1277 && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (insn))))
1279 if ((next = try_combine (insn, prev, NULL_RTX, NULL_RTX,
1281 last_combined_insn)) != 0)
1284 FOR_EACH_LOG_LINK (nextlinks, prev)
1285 if ((next = try_combine (insn, prev, nextlinks->insn,
1286 NULL_RTX, &new_direct_jump_p,
1287 last_combined_insn)) != 0)
1291 /* Finally, see if any of the insns that this insn links to
1292 explicitly references CC0. If so, try this insn, that insn,
1293 and its predecessor if it sets CC0. */
1294 FOR_EACH_LOG_LINK (links, insn)
1295 if (NONJUMP_INSN_P (links->insn)
1296 && GET_CODE (PATTERN (links->insn)) == SET
1297 && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (links->insn)))
1298 && (prev = prev_nonnote_insn (links->insn)) != 0
1299 && NONJUMP_INSN_P (prev)
1300 && sets_cc0_p (PATTERN (prev))
1301 && (next = try_combine (insn, links->insn,
1302 prev, NULL_RTX, &new_direct_jump_p,
1303 last_combined_insn)) != 0)
1307 /* Try combining an insn with two different insns whose results it
1309 FOR_EACH_LOG_LINK (links, insn)
1310 for (nextlinks = links->next; nextlinks;
1311 nextlinks = nextlinks->next)
1312 if ((next = try_combine (insn, links->insn,
1313 nextlinks->insn, NULL_RTX,
1315 last_combined_insn)) != 0)
1318 /* Try four-instruction combinations. */
1319 FOR_EACH_LOG_LINK (links, insn)
1321 struct insn_link *next1;
1322 rtx link = links->insn;
1324 /* If the linked insn has been replaced by a note, then there
1325 is no point in pursuing this chain any further. */
1329 FOR_EACH_LOG_LINK (next1, link)
1331 rtx link1 = next1->insn;
1334 /* I0 -> I1 -> I2 -> I3. */
1335 FOR_EACH_LOG_LINK (nextlinks, link1)
1336 if ((next = try_combine (insn, link, link1,
1339 last_combined_insn)) != 0)
1341 /* I0, I1 -> I2, I2 -> I3. */
1342 for (nextlinks = next1->next; nextlinks;
1343 nextlinks = nextlinks->next)
1344 if ((next = try_combine (insn, link, link1,
1347 last_combined_insn)) != 0)
1351 for (next1 = links->next; next1; next1 = next1->next)
1353 rtx link1 = next1->insn;
1356 /* I0 -> I2; I1, I2 -> I3. */
1357 FOR_EACH_LOG_LINK (nextlinks, link)
1358 if ((next = try_combine (insn, link, link1,
1361 last_combined_insn)) != 0)
1363 /* I0 -> I1; I1, I2 -> I3. */
1364 FOR_EACH_LOG_LINK (nextlinks, link1)
1365 if ((next = try_combine (insn, link, link1,
1368 last_combined_insn)) != 0)
1373 /* Try this insn with each REG_EQUAL note it links back to. */
1374 FOR_EACH_LOG_LINK (links, insn)
1377 rtx temp = links->insn;
1378 if ((set = single_set (temp)) != 0
1379 && (note = find_reg_equal_equiv_note (temp)) != 0
1380 && (note = XEXP (note, 0), GET_CODE (note)) != EXPR_LIST
1381 /* Avoid using a register that may already been marked
1382 dead by an earlier instruction. */
1383 && ! unmentioned_reg_p (note, SET_SRC (set))
1384 && (GET_MODE (note) == VOIDmode
1385 ? SCALAR_INT_MODE_P (GET_MODE (SET_DEST (set)))
1386 : GET_MODE (SET_DEST (set)) == GET_MODE (note)))
1388 /* Temporarily replace the set's source with the
1389 contents of the REG_EQUAL note. The insn will
1390 be deleted or recognized by try_combine. */
1391 rtx orig = SET_SRC (set);
1392 SET_SRC (set) = note;
1394 i2mod_old_rhs = copy_rtx (orig);
1395 i2mod_new_rhs = copy_rtx (note);
1396 next = try_combine (insn, i2mod, NULL_RTX, NULL_RTX,
1398 last_combined_insn);
1402 SET_SRC (set) = orig;
1407 record_dead_and_set_regs (insn);
1415 default_rtl_profile ();
1417 new_direct_jump_p |= purge_all_dead_edges ();
1418 delete_noop_moves ();
1421 obstack_free (&insn_link_obstack, NULL);
1422 free (uid_log_links);
1423 free (uid_insn_cost);
1424 VEC_free (reg_stat_type, heap, reg_stat);
1427 struct undo *undo, *next;
1428 for (undo = undobuf.frees; undo; undo = next)
1436 total_attempts += combine_attempts;
1437 total_merges += combine_merges;
1438 total_extras += combine_extras;
1439 total_successes += combine_successes;
1441 nonzero_sign_valid = 0;
1442 rtl_hooks = general_rtl_hooks;
1444 /* Make recognizer allow volatile MEMs again. */
1447 return new_direct_jump_p;
1450 /* Wipe the last_xxx fields of reg_stat in preparation for another pass. */
1453 init_reg_last (void)
1458 FOR_EACH_VEC_ELT (reg_stat_type, reg_stat, i, p)
1459 memset (p, 0, offsetof (reg_stat_type, sign_bit_copies));
1462 /* Set up any promoted values for incoming argument registers. */
1465 setup_incoming_promotions (rtx first)
1468 bool strictly_local = false;
1470 for (arg = DECL_ARGUMENTS (current_function_decl); arg;
1471 arg = DECL_CHAIN (arg))
1473 rtx x, reg = DECL_INCOMING_RTL (arg);
1475 enum machine_mode mode1, mode2, mode3, mode4;
1477 /* Only continue if the incoming argument is in a register. */
1481 /* Determine, if possible, whether all call sites of the current
1482 function lie within the current compilation unit. (This does
1483 take into account the exporting of a function via taking its
1484 address, and so forth.) */
1485 strictly_local = cgraph_local_info (current_function_decl)->local;
1487 /* The mode and signedness of the argument before any promotions happen
1488 (equal to the mode of the pseudo holding it at that stage). */
1489 mode1 = TYPE_MODE (TREE_TYPE (arg));
1490 uns1 = TYPE_UNSIGNED (TREE_TYPE (arg));
1492 /* The mode and signedness of the argument after any source language and
1493 TARGET_PROMOTE_PROTOTYPES-driven promotions. */
1494 mode2 = TYPE_MODE (DECL_ARG_TYPE (arg));
1495 uns3 = TYPE_UNSIGNED (DECL_ARG_TYPE (arg));
1497 /* The mode and signedness of the argument as it is actually passed,
1498 after any TARGET_PROMOTE_FUNCTION_ARGS-driven ABI promotions. */
1499 mode3 = promote_function_mode (DECL_ARG_TYPE (arg), mode2, &uns3,
1500 TREE_TYPE (cfun->decl), 0);
1502 /* The mode of the register in which the argument is being passed. */
1503 mode4 = GET_MODE (reg);
1505 /* Eliminate sign extensions in the callee when:
1506 (a) A mode promotion has occurred; */
1509 /* (b) The mode of the register is the same as the mode of
1510 the argument as it is passed; */
1513 /* (c) There's no language level extension; */
1516 /* (c.1) All callers are from the current compilation unit. If that's
1517 the case we don't have to rely on an ABI, we only have to know
1518 what we're generating right now, and we know that we will do the
1519 mode1 to mode2 promotion with the given sign. */
1520 else if (!strictly_local)
1522 /* (c.2) The combination of the two promotions is useful. This is
1523 true when the signs match, or if the first promotion is unsigned.
1524 In the later case, (sign_extend (zero_extend x)) is the same as
1525 (zero_extend (zero_extend x)), so make sure to force UNS3 true. */
1531 /* Record that the value was promoted from mode1 to mode3,
1532 so that any sign extension at the head of the current
1533 function may be eliminated. */
1534 x = gen_rtx_CLOBBER (mode1, const0_rtx);
1535 x = gen_rtx_fmt_e ((uns3 ? ZERO_EXTEND : SIGN_EXTEND), mode3, x);
1536 record_value_for_reg (reg, first, x);
1540 /* Called via note_stores. If X is a pseudo that is narrower than
1541 HOST_BITS_PER_WIDE_INT and is being set, record what bits are known zero.
1543 If we are setting only a portion of X and we can't figure out what
1544 portion, assume all bits will be used since we don't know what will
1547 Similarly, set how many bits of X are known to be copies of the sign bit
1548 at all locations in the function. This is the smallest number implied
1552 set_nonzero_bits_and_sign_copies (rtx x, const_rtx set, void *data)
1554 rtx insn = (rtx) data;
1558 && REGNO (x) >= FIRST_PSEUDO_REGISTER
1559 /* If this register is undefined at the start of the file, we can't
1560 say what its contents were. */
1561 && ! REGNO_REG_SET_P
1562 (DF_LR_IN (ENTRY_BLOCK_PTR->next_bb), REGNO (x))
1563 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT)
1565 reg_stat_type *rsp = VEC_index (reg_stat_type, reg_stat, REGNO (x));
1567 if (set == 0 || GET_CODE (set) == CLOBBER)
1569 rsp->nonzero_bits = GET_MODE_MASK (GET_MODE (x));
1570 rsp->sign_bit_copies = 1;
1574 /* If this register is being initialized using itself, and the
1575 register is uninitialized in this basic block, and there are
1576 no LOG_LINKS which set the register, then part of the
1577 register is uninitialized. In that case we can't assume
1578 anything about the number of nonzero bits.
1580 ??? We could do better if we checked this in
1581 reg_{nonzero_bits,num_sign_bit_copies}_for_combine. Then we
1582 could avoid making assumptions about the insn which initially
1583 sets the register, while still using the information in other
1584 insns. We would have to be careful to check every insn
1585 involved in the combination. */
1588 && reg_referenced_p (x, PATTERN (insn))
1589 && !REGNO_REG_SET_P (DF_LR_IN (BLOCK_FOR_INSN (insn)),
1592 struct insn_link *link;
1594 FOR_EACH_LOG_LINK (link, insn)
1595 if (dead_or_set_p (link->insn, x))
1599 rsp->nonzero_bits = GET_MODE_MASK (GET_MODE (x));
1600 rsp->sign_bit_copies = 1;
1605 /* If this is a complex assignment, see if we can convert it into a
1606 simple assignment. */
1607 set = expand_field_assignment (set);
1609 /* If this is a simple assignment, or we have a paradoxical SUBREG,
1610 set what we know about X. */
1612 if (SET_DEST (set) == x
1613 || (GET_CODE (SET_DEST (set)) == SUBREG
1614 && (GET_MODE_SIZE (GET_MODE (SET_DEST (set)))
1615 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (set)))))
1616 && SUBREG_REG (SET_DEST (set)) == x))
1618 rtx src = SET_SRC (set);
1620 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
1621 /* If X is narrower than a word and SRC is a non-negative
1622 constant that would appear negative in the mode of X,
1623 sign-extend it for use in reg_stat[].nonzero_bits because some
1624 machines (maybe most) will actually do the sign-extension
1625 and this is the conservative approach.
1627 ??? For 2.5, try to tighten up the MD files in this regard
1628 instead of this kludge. */
1630 if (GET_MODE_PRECISION (GET_MODE (x)) < BITS_PER_WORD
1631 && CONST_INT_P (src)
1633 && val_signbit_known_set_p (GET_MODE (x), INTVAL (src)))
1634 src = GEN_INT (INTVAL (src) | ~GET_MODE_MASK (GET_MODE (x)));
1637 /* Don't call nonzero_bits if it cannot change anything. */
1638 if (rsp->nonzero_bits != ~(unsigned HOST_WIDE_INT) 0)
1639 rsp->nonzero_bits |= nonzero_bits (src, nonzero_bits_mode);
1640 num = num_sign_bit_copies (SET_SRC (set), GET_MODE (x));
1641 if (rsp->sign_bit_copies == 0
1642 || rsp->sign_bit_copies > num)
1643 rsp->sign_bit_copies = num;
1647 rsp->nonzero_bits = GET_MODE_MASK (GET_MODE (x));
1648 rsp->sign_bit_copies = 1;
1653 /* See if INSN can be combined into I3. PRED, PRED2, SUCC and SUCC2 are
1654 optionally insns that were previously combined into I3 or that will be
1655 combined into the merger of INSN and I3. The order is PRED, PRED2,
1656 INSN, SUCC, SUCC2, I3.
1658 Return 0 if the combination is not allowed for any reason.
1660 If the combination is allowed, *PDEST will be set to the single
1661 destination of INSN and *PSRC to the single source, and this function
1665 can_combine_p (rtx insn, rtx i3, rtx pred ATTRIBUTE_UNUSED,
1666 rtx pred2 ATTRIBUTE_UNUSED, rtx succ, rtx succ2,
1667 rtx *pdest, rtx *psrc)
1676 bool all_adjacent = true;
1682 if (next_active_insn (succ2) != i3)
1683 all_adjacent = false;
1684 if (next_active_insn (succ) != succ2)
1685 all_adjacent = false;
1687 else if (next_active_insn (succ) != i3)
1688 all_adjacent = false;
1689 if (next_active_insn (insn) != succ)
1690 all_adjacent = false;
1692 else if (next_active_insn (insn) != i3)
1693 all_adjacent = false;
1695 /* Can combine only if previous insn is a SET of a REG, a SUBREG or CC0.
1696 or a PARALLEL consisting of such a SET and CLOBBERs.
1698 If INSN has CLOBBER parallel parts, ignore them for our processing.
1699 By definition, these happen during the execution of the insn. When it
1700 is merged with another insn, all bets are off. If they are, in fact,
1701 needed and aren't also supplied in I3, they may be added by
1702 recog_for_combine. Otherwise, it won't match.
1704 We can also ignore a SET whose SET_DEST is mentioned in a REG_UNUSED
1707 Get the source and destination of INSN. If more than one, can't
1710 if (GET_CODE (PATTERN (insn)) == SET)
1711 set = PATTERN (insn);
1712 else if (GET_CODE (PATTERN (insn)) == PARALLEL
1713 && GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == SET)
1715 for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
1717 rtx elt = XVECEXP (PATTERN (insn), 0, i);
1719 switch (GET_CODE (elt))
1721 /* This is important to combine floating point insns
1722 for the SH4 port. */
1724 /* Combining an isolated USE doesn't make sense.
1725 We depend here on combinable_i3pat to reject them. */
1726 /* The code below this loop only verifies that the inputs of
1727 the SET in INSN do not change. We call reg_set_between_p
1728 to verify that the REG in the USE does not change between
1730 If the USE in INSN was for a pseudo register, the matching
1731 insn pattern will likely match any register; combining this
1732 with any other USE would only be safe if we knew that the
1733 used registers have identical values, or if there was
1734 something to tell them apart, e.g. different modes. For
1735 now, we forgo such complicated tests and simply disallow
1736 combining of USES of pseudo registers with any other USE. */
1737 if (REG_P (XEXP (elt, 0))
1738 && GET_CODE (PATTERN (i3)) == PARALLEL)
1740 rtx i3pat = PATTERN (i3);
1741 int i = XVECLEN (i3pat, 0) - 1;
1742 unsigned int regno = REGNO (XEXP (elt, 0));
1746 rtx i3elt = XVECEXP (i3pat, 0, i);
1748 if (GET_CODE (i3elt) == USE
1749 && REG_P (XEXP (i3elt, 0))
1750 && (REGNO (XEXP (i3elt, 0)) == regno
1751 ? reg_set_between_p (XEXP (elt, 0),
1752 PREV_INSN (insn), i3)
1753 : regno >= FIRST_PSEUDO_REGISTER))
1760 /* We can ignore CLOBBERs. */
1765 /* Ignore SETs whose result isn't used but not those that
1766 have side-effects. */
1767 if (find_reg_note (insn, REG_UNUSED, SET_DEST (elt))
1768 && insn_nothrow_p (insn)
1769 && !side_effects_p (elt))
1772 /* If we have already found a SET, this is a second one and
1773 so we cannot combine with this insn. */
1781 /* Anything else means we can't combine. */
1787 /* If SET_SRC is an ASM_OPERANDS we can't throw away these CLOBBERs,
1788 so don't do anything with it. */
1789 || GET_CODE (SET_SRC (set)) == ASM_OPERANDS)
1798 set = expand_field_assignment (set);
1799 src = SET_SRC (set), dest = SET_DEST (set);
1801 /* Don't eliminate a store in the stack pointer. */
1802 if (dest == stack_pointer_rtx
1803 /* Don't combine with an insn that sets a register to itself if it has
1804 a REG_EQUAL note. This may be part of a LIBCALL sequence. */
1805 || (rtx_equal_p (src, dest) && find_reg_note (insn, REG_EQUAL, NULL_RTX))
1806 /* Can't merge an ASM_OPERANDS. */
1807 || GET_CODE (src) == ASM_OPERANDS
1808 /* Can't merge a function call. */
1809 || GET_CODE (src) == CALL
1810 /* Don't eliminate a function call argument. */
1812 && (find_reg_fusage (i3, USE, dest)
1814 && REGNO (dest) < FIRST_PSEUDO_REGISTER
1815 && global_regs[REGNO (dest)])))
1816 /* Don't substitute into an incremented register. */
1817 || FIND_REG_INC_NOTE (i3, dest)
1818 || (succ && FIND_REG_INC_NOTE (succ, dest))
1819 || (succ2 && FIND_REG_INC_NOTE (succ2, dest))
1820 /* Don't substitute into a non-local goto, this confuses CFG. */
1821 || (JUMP_P (i3) && find_reg_note (i3, REG_NON_LOCAL_GOTO, NULL_RTX))
1822 /* Make sure that DEST is not used after SUCC but before I3. */
1825 && (reg_used_between_p (dest, succ2, i3)
1826 || reg_used_between_p (dest, succ, succ2)))
1827 || (!succ2 && succ && reg_used_between_p (dest, succ, i3))))
1828 /* Make sure that the value that is to be substituted for the register
1829 does not use any registers whose values alter in between. However,
1830 If the insns are adjacent, a use can't cross a set even though we
1831 think it might (this can happen for a sequence of insns each setting
1832 the same destination; last_set of that register might point to
1833 a NOTE). If INSN has a REG_EQUIV note, the register is always
1834 equivalent to the memory so the substitution is valid even if there
1835 are intervening stores. Also, don't move a volatile asm or
1836 UNSPEC_VOLATILE across any other insns. */
1839 || ! find_reg_note (insn, REG_EQUIV, src))
1840 && use_crosses_set_p (src, DF_INSN_LUID (insn)))
1841 || (GET_CODE (src) == ASM_OPERANDS && MEM_VOLATILE_P (src))
1842 || GET_CODE (src) == UNSPEC_VOLATILE))
1843 /* Don't combine across a CALL_INSN, because that would possibly
1844 change whether the life span of some REGs crosses calls or not,
1845 and it is a pain to update that information.
1846 Exception: if source is a constant, moving it later can't hurt.
1847 Accept that as a special case. */
1848 || (DF_INSN_LUID (insn) < last_call_luid && ! CONSTANT_P (src)))
1851 /* DEST must either be a REG or CC0. */
1854 /* If register alignment is being enforced for multi-word items in all
1855 cases except for parameters, it is possible to have a register copy
1856 insn referencing a hard register that is not allowed to contain the
1857 mode being copied and which would not be valid as an operand of most
1858 insns. Eliminate this problem by not combining with such an insn.
1860 Also, on some machines we don't want to extend the life of a hard
1864 && ((REGNO (dest) < FIRST_PSEUDO_REGISTER
1865 && ! HARD_REGNO_MODE_OK (REGNO (dest), GET_MODE (dest)))
1866 /* Don't extend the life of a hard register unless it is
1867 user variable (if we have few registers) or it can't
1868 fit into the desired register (meaning something special
1870 Also avoid substituting a return register into I3, because
1871 reload can't handle a conflict with constraints of other
1873 || (REGNO (src) < FIRST_PSEUDO_REGISTER
1874 && ! HARD_REGNO_MODE_OK (REGNO (src), GET_MODE (src)))))
1877 else if (GET_CODE (dest) != CC0)
1881 if (GET_CODE (PATTERN (i3)) == PARALLEL)
1882 for (i = XVECLEN (PATTERN (i3), 0) - 1; i >= 0; i--)
1883 if (GET_CODE (XVECEXP (PATTERN (i3), 0, i)) == CLOBBER)
1885 /* Don't substitute for a register intended as a clobberable
1887 rtx reg = XEXP (XVECEXP (PATTERN (i3), 0, i), 0);
1888 if (rtx_equal_p (reg, dest))
1891 /* If the clobber represents an earlyclobber operand, we must not
1892 substitute an expression containing the clobbered register.
1893 As we do not analyze the constraint strings here, we have to
1894 make the conservative assumption. However, if the register is
1895 a fixed hard reg, the clobber cannot represent any operand;
1896 we leave it up to the machine description to either accept or
1897 reject use-and-clobber patterns. */
1899 || REGNO (reg) >= FIRST_PSEUDO_REGISTER
1900 || !fixed_regs[REGNO (reg)])
1901 if (reg_overlap_mentioned_p (reg, src))
1905 /* If INSN contains anything volatile, or is an `asm' (whether volatile
1906 or not), reject, unless nothing volatile comes between it and I3 */
1908 if (GET_CODE (src) == ASM_OPERANDS || volatile_refs_p (src))
1910 /* Make sure neither succ nor succ2 contains a volatile reference. */
1911 if (succ2 != 0 && volatile_refs_p (PATTERN (succ2)))
1913 if (succ != 0 && volatile_refs_p (PATTERN (succ)))
1915 /* We'll check insns between INSN and I3 below. */
1918 /* If INSN is an asm, and DEST is a hard register, reject, since it has
1919 to be an explicit register variable, and was chosen for a reason. */
1921 if (GET_CODE (src) == ASM_OPERANDS
1922 && REG_P (dest) && REGNO (dest) < FIRST_PSEUDO_REGISTER)
1925 /* If there are any volatile insns between INSN and I3, reject, because
1926 they might affect machine state. */
1928 for (p = NEXT_INSN (insn); p != i3; p = NEXT_INSN (p))
1929 if (INSN_P (p) && p != succ && p != succ2 && volatile_insn_p (PATTERN (p)))
1932 /* If INSN contains an autoincrement or autodecrement, make sure that
1933 register is not used between there and I3, and not already used in
1934 I3 either. Neither must it be used in PRED or SUCC, if they exist.
1935 Also insist that I3 not be a jump; if it were one
1936 and the incremented register were spilled, we would lose. */
1939 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
1940 if (REG_NOTE_KIND (link) == REG_INC
1942 || reg_used_between_p (XEXP (link, 0), insn, i3)
1943 || (pred != NULL_RTX
1944 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (pred)))
1945 || (pred2 != NULL_RTX
1946 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (pred2)))
1947 || (succ != NULL_RTX
1948 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (succ)))
1949 || (succ2 != NULL_RTX
1950 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (succ2)))
1951 || reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i3))))
1956 /* Don't combine an insn that follows a CC0-setting insn.
1957 An insn that uses CC0 must not be separated from the one that sets it.
1958 We do, however, allow I2 to follow a CC0-setting insn if that insn
1959 is passed as I1; in that case it will be deleted also.
1960 We also allow combining in this case if all the insns are adjacent
1961 because that would leave the two CC0 insns adjacent as well.
1962 It would be more logical to test whether CC0 occurs inside I1 or I2,
1963 but that would be much slower, and this ought to be equivalent. */
1965 p = prev_nonnote_insn (insn);
1966 if (p && p != pred && NONJUMP_INSN_P (p) && sets_cc0_p (PATTERN (p))
1971 /* If we get here, we have passed all the tests and the combination is
1980 /* LOC is the location within I3 that contains its pattern or the component
1981 of a PARALLEL of the pattern. We validate that it is valid for combining.
1983 One problem is if I3 modifies its output, as opposed to replacing it
1984 entirely, we can't allow the output to contain I2DEST, I1DEST or I0DEST as
1985 doing so would produce an insn that is not equivalent to the original insns.
1989 (set (reg:DI 101) (reg:DI 100))
1990 (set (subreg:SI (reg:DI 101) 0) <foo>)
1992 This is NOT equivalent to:
1994 (parallel [(set (subreg:SI (reg:DI 100) 0) <foo>)
1995 (set (reg:DI 101) (reg:DI 100))])
1997 Not only does this modify 100 (in which case it might still be valid
1998 if 100 were dead in I2), it sets 101 to the ORIGINAL value of 100.
2000 We can also run into a problem if I2 sets a register that I1
2001 uses and I1 gets directly substituted into I3 (not via I2). In that
2002 case, we would be getting the wrong value of I2DEST into I3, so we
2003 must reject the combination. This case occurs when I2 and I1 both
2004 feed into I3, rather than when I1 feeds into I2, which feeds into I3.
2005 If I1_NOT_IN_SRC is nonzero, it means that finding I1 in the source
2006 of a SET must prevent combination from occurring. The same situation
2007 can occur for I0, in which case I0_NOT_IN_SRC is set.
2009 Before doing the above check, we first try to expand a field assignment
2010 into a set of logical operations.
2012 If PI3_DEST_KILLED is nonzero, it is a pointer to a location in which
2013 we place a register that is both set and used within I3. If more than one
2014 such register is detected, we fail.
2016 Return 1 if the combination is valid, zero otherwise. */
2019 combinable_i3pat (rtx i3, rtx *loc, rtx i2dest, rtx i1dest, rtx i0dest,
2020 int i1_not_in_src, int i0_not_in_src, rtx *pi3dest_killed)
2024 if (GET_CODE (x) == SET)
2027 rtx dest = SET_DEST (set);
2028 rtx src = SET_SRC (set);
2029 rtx inner_dest = dest;
2032 while (GET_CODE (inner_dest) == STRICT_LOW_PART
2033 || GET_CODE (inner_dest) == SUBREG
2034 || GET_CODE (inner_dest) == ZERO_EXTRACT)
2035 inner_dest = XEXP (inner_dest, 0);
2037 /* Check for the case where I3 modifies its output, as discussed
2038 above. We don't want to prevent pseudos from being combined
2039 into the address of a MEM, so only prevent the combination if
2040 i1 or i2 set the same MEM. */
2041 if ((inner_dest != dest &&
2042 (!MEM_P (inner_dest)
2043 || rtx_equal_p (i2dest, inner_dest)
2044 || (i1dest && rtx_equal_p (i1dest, inner_dest))
2045 || (i0dest && rtx_equal_p (i0dest, inner_dest)))
2046 && (reg_overlap_mentioned_p (i2dest, inner_dest)
2047 || (i1dest && reg_overlap_mentioned_p (i1dest, inner_dest))
2048 || (i0dest && reg_overlap_mentioned_p (i0dest, inner_dest))))
2050 /* This is the same test done in can_combine_p except we can't test
2051 all_adjacent; we don't have to, since this instruction will stay
2052 in place, thus we are not considering increasing the lifetime of
2055 Also, if this insn sets a function argument, combining it with
2056 something that might need a spill could clobber a previous
2057 function argument; the all_adjacent test in can_combine_p also
2058 checks this; here, we do a more specific test for this case. */
2060 || (REG_P (inner_dest)
2061 && REGNO (inner_dest) < FIRST_PSEUDO_REGISTER
2062 && (! HARD_REGNO_MODE_OK (REGNO (inner_dest),
2063 GET_MODE (inner_dest))))
2064 || (i1_not_in_src && reg_overlap_mentioned_p (i1dest, src))
2065 || (i0_not_in_src && reg_overlap_mentioned_p (i0dest, src)))
2068 /* If DEST is used in I3, it is being killed in this insn, so
2069 record that for later. We have to consider paradoxical
2070 subregs here, since they kill the whole register, but we
2071 ignore partial subregs, STRICT_LOW_PART, etc.
2072 Never add REG_DEAD notes for the FRAME_POINTER_REGNUM or the
2073 STACK_POINTER_REGNUM, since these are always considered to be
2074 live. Similarly for ARG_POINTER_REGNUM if it is fixed. */
2076 if (GET_CODE (subdest) == SUBREG
2077 && (GET_MODE_SIZE (GET_MODE (subdest))
2078 >= GET_MODE_SIZE (GET_MODE (SUBREG_REG (subdest)))))
2079 subdest = SUBREG_REG (subdest);
2082 && reg_referenced_p (subdest, PATTERN (i3))
2083 && REGNO (subdest) != FRAME_POINTER_REGNUM
2084 #if !HARD_FRAME_POINTER_IS_FRAME_POINTER
2085 && REGNO (subdest) != HARD_FRAME_POINTER_REGNUM
2087 #if ARG_POINTER_REGNUM != FRAME_POINTER_REGNUM
2088 && (REGNO (subdest) != ARG_POINTER_REGNUM
2089 || ! fixed_regs [REGNO (subdest)])
2091 && REGNO (subdest) != STACK_POINTER_REGNUM)
2093 if (*pi3dest_killed)
2096 *pi3dest_killed = subdest;
2100 else if (GET_CODE (x) == PARALLEL)
2104 for (i = 0; i < XVECLEN (x, 0); i++)
2105 if (! combinable_i3pat (i3, &XVECEXP (x, 0, i), i2dest, i1dest, i0dest,
2106 i1_not_in_src, i0_not_in_src, pi3dest_killed))
2113 /* Return 1 if X is an arithmetic expression that contains a multiplication
2114 and division. We don't count multiplications by powers of two here. */
2117 contains_muldiv (rtx x)
2119 switch (GET_CODE (x))
2121 case MOD: case DIV: case UMOD: case UDIV:
2125 return ! (CONST_INT_P (XEXP (x, 1))
2126 && exact_log2 (UINTVAL (XEXP (x, 1))) >= 0);
2129 return contains_muldiv (XEXP (x, 0))
2130 || contains_muldiv (XEXP (x, 1));
2133 return contains_muldiv (XEXP (x, 0));
2139 /* Determine whether INSN can be used in a combination. Return nonzero if
2140 not. This is used in try_combine to detect early some cases where we
2141 can't perform combinations. */
2144 cant_combine_insn_p (rtx insn)
2149 /* If this isn't really an insn, we can't do anything.
2150 This can occur when flow deletes an insn that it has merged into an
2151 auto-increment address. */
2152 if (! INSN_P (insn))
2155 /* Never combine loads and stores involving hard regs that are likely
2156 to be spilled. The register allocator can usually handle such
2157 reg-reg moves by tying. If we allow the combiner to make
2158 substitutions of likely-spilled regs, reload might die.
2159 As an exception, we allow combinations involving fixed regs; these are
2160 not available to the register allocator so there's no risk involved. */
2162 set = single_set (insn);
2165 src = SET_SRC (set);
2166 dest = SET_DEST (set);
2167 if (GET_CODE (src) == SUBREG)
2168 src = SUBREG_REG (src);
2169 if (GET_CODE (dest) == SUBREG)
2170 dest = SUBREG_REG (dest);
2171 if (REG_P (src) && REG_P (dest)
2172 && ((HARD_REGISTER_P (src)
2173 && ! TEST_HARD_REG_BIT (fixed_reg_set, REGNO (src))
2174 && targetm.class_likely_spilled_p (REGNO_REG_CLASS (REGNO (src))))
2175 || (HARD_REGISTER_P (dest)
2176 && ! TEST_HARD_REG_BIT (fixed_reg_set, REGNO (dest))
2177 && targetm.class_likely_spilled_p (REGNO_REG_CLASS (REGNO (dest))))))
2183 struct likely_spilled_retval_info
2185 unsigned regno, nregs;
2189 /* Called via note_stores by likely_spilled_retval_p. Remove from info->mask
2190 hard registers that are known to be written to / clobbered in full. */
2192 likely_spilled_retval_1 (rtx x, const_rtx set, void *data)
2194 struct likely_spilled_retval_info *const info =
2195 (struct likely_spilled_retval_info *) data;
2196 unsigned regno, nregs;
2199 if (!REG_P (XEXP (set, 0)))
2202 if (regno >= info->regno + info->nregs)
2204 nregs = hard_regno_nregs[regno][GET_MODE (x)];
2205 if (regno + nregs <= info->regno)
2207 new_mask = (2U << (nregs - 1)) - 1;
2208 if (regno < info->regno)
2209 new_mask >>= info->regno - regno;
2211 new_mask <<= regno - info->regno;
2212 info->mask &= ~new_mask;
2215 /* Return nonzero iff part of the return value is live during INSN, and
2216 it is likely spilled. This can happen when more than one insn is needed
2217 to copy the return value, e.g. when we consider to combine into the
2218 second copy insn for a complex value. */
2221 likely_spilled_retval_p (rtx insn)
2223 rtx use = BB_END (this_basic_block);
2225 unsigned regno, nregs;
2226 /* We assume here that no machine mode needs more than
2227 32 hard registers when the value overlaps with a register
2228 for which TARGET_FUNCTION_VALUE_REGNO_P is true. */
2230 struct likely_spilled_retval_info info;
2232 if (!NONJUMP_INSN_P (use) || GET_CODE (PATTERN (use)) != USE || insn == use)
2234 reg = XEXP (PATTERN (use), 0);
2235 if (!REG_P (reg) || !targetm.calls.function_value_regno_p (REGNO (reg)))
2237 regno = REGNO (reg);
2238 nregs = hard_regno_nregs[regno][GET_MODE (reg)];
2241 mask = (2U << (nregs - 1)) - 1;
2243 /* Disregard parts of the return value that are set later. */
2247 for (p = PREV_INSN (use); info.mask && p != insn; p = PREV_INSN (p))
2249 note_stores (PATTERN (p), likely_spilled_retval_1, &info);
2252 /* Check if any of the (probably) live return value registers is
2257 if ((mask & 1 << nregs)
2258 && targetm.class_likely_spilled_p (REGNO_REG_CLASS (regno + nregs)))
2264 /* Adjust INSN after we made a change to its destination.
2266 Changing the destination can invalidate notes that say something about
2267 the results of the insn and a LOG_LINK pointing to the insn. */
2270 adjust_for_new_dest (rtx insn)
2272 /* For notes, be conservative and simply remove them. */
2273 remove_reg_equal_equiv_notes (insn);
2275 /* The new insn will have a destination that was previously the destination
2276 of an insn just above it. Call distribute_links to make a LOG_LINK from
2277 the next use of that destination. */
2278 distribute_links (alloc_insn_link (insn, NULL));
2280 df_insn_rescan (insn);
2283 /* Return TRUE if combine can reuse reg X in mode MODE.
2284 ADDED_SETS is nonzero if the original set is still required. */
2286 can_change_dest_mode (rtx x, int added_sets, enum machine_mode mode)
2294 /* Allow hard registers if the new mode is legal, and occupies no more
2295 registers than the old mode. */
2296 if (regno < FIRST_PSEUDO_REGISTER)
2297 return (HARD_REGNO_MODE_OK (regno, mode)
2298 && (hard_regno_nregs[regno][GET_MODE (x)]
2299 >= hard_regno_nregs[regno][mode]));
2301 /* Or a pseudo that is only used once. */
2302 return (REG_N_SETS (regno) == 1 && !added_sets
2303 && !REG_USERVAR_P (x));
2307 /* Check whether X, the destination of a set, refers to part of
2308 the register specified by REG. */
2311 reg_subword_p (rtx x, rtx reg)
2313 /* Check that reg is an integer mode register. */
2314 if (!REG_P (reg) || GET_MODE_CLASS (GET_MODE (reg)) != MODE_INT)
2317 if (GET_CODE (x) == STRICT_LOW_PART
2318 || GET_CODE (x) == ZERO_EXTRACT)
2321 return GET_CODE (x) == SUBREG
2322 && SUBREG_REG (x) == reg
2323 && GET_MODE_CLASS (GET_MODE (x)) == MODE_INT;
2327 /* Replace auto-increment addressing modes with explicit operations to access
2328 the same addresses without modifying the corresponding registers. */
2331 cleanup_auto_inc_dec (rtx src, enum machine_mode mem_mode)
2334 const RTX_CODE code = GET_CODE (x);
2350 /* SCRATCH must be shared because they represent distinct values. */
2353 if (REG_P (XEXP (x, 0)) && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER)
2358 if (shared_const_p (x))
2363 mem_mode = GET_MODE (x);
2368 gcc_assert (mem_mode != VOIDmode && mem_mode != BLKmode);
2369 return gen_rtx_PLUS (GET_MODE (x),
2370 cleanup_auto_inc_dec (XEXP (x, 0), mem_mode),
2371 GEN_INT (code == PRE_INC
2372 ? GET_MODE_SIZE (mem_mode)
2373 : -GET_MODE_SIZE (mem_mode)));
2379 return cleanup_auto_inc_dec (code == PRE_MODIFY
2380 ? XEXP (x, 1) : XEXP (x, 0),
2387 /* Copy the various flags, fields, and other information. We assume
2388 that all fields need copying, and then clear the fields that should
2389 not be copied. That is the sensible default behavior, and forces
2390 us to explicitly document why we are *not* copying a flag. */
2391 x = shallow_copy_rtx (x);
2393 /* We do not copy the USED flag, which is used as a mark bit during
2394 walks over the RTL. */
2395 RTX_FLAG (x, used) = 0;
2397 /* We do not copy FRAME_RELATED for INSNs. */
2399 RTX_FLAG (x, frame_related) = 0;
2401 fmt = GET_RTX_FORMAT (code);
2402 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
2404 XEXP (x, i) = cleanup_auto_inc_dec (XEXP (x, i), mem_mode);
2405 else if (fmt[i] == 'E' || fmt[i] == 'V')
2408 XVEC (x, i) = rtvec_alloc (XVECLEN (x, i));
2409 for (j = 0; j < XVECLEN (x, i); j++)
2411 = cleanup_auto_inc_dec (XVECEXP (src, i, j), mem_mode);
2418 /* Auxiliary data structure for propagate_for_debug_stmt. */
2420 struct rtx_subst_pair
2426 /* DATA points to an rtx_subst_pair. Return the value that should be
2430 propagate_for_debug_subst (rtx from, const_rtx old_rtx, void *data)
2432 struct rtx_subst_pair *pair = (struct rtx_subst_pair *)data;
2434 if (!rtx_equal_p (from, old_rtx))
2436 if (!pair->adjusted)
2438 pair->adjusted = true;
2440 pair->to = cleanup_auto_inc_dec (pair->to, VOIDmode);
2442 pair->to = copy_rtx (pair->to);
2444 pair->to = make_compound_operation (pair->to, SET);
2447 return copy_rtx (pair->to);
2450 /* Replace all the occurrences of DEST with SRC in DEBUG_INSNs between INSN
2451 and LAST, not including INSN, but including LAST. Also stop at the end
2452 of THIS_BASIC_BLOCK. */
2455 propagate_for_debug (rtx insn, rtx last, rtx dest, rtx src)
2457 rtx next, loc, end = NEXT_INSN (BB_END (this_basic_block));
2459 struct rtx_subst_pair p;
2463 next = NEXT_INSN (insn);
2464 last = NEXT_INSN (last);
2465 while (next != last && next != end)
2468 next = NEXT_INSN (insn);
2469 if (DEBUG_INSN_P (insn))
2471 loc = simplify_replace_fn_rtx (INSN_VAR_LOCATION_LOC (insn),
2472 dest, propagate_for_debug_subst, &p);
2473 if (loc == INSN_VAR_LOCATION_LOC (insn))
2475 INSN_VAR_LOCATION_LOC (insn) = loc;
2476 df_insn_rescan (insn);
2481 /* Delete the unconditional jump INSN and adjust the CFG correspondingly.
2482 Note that the INSN should be deleted *after* removing dead edges, so
2483 that the kept edge is the fallthrough edge for a (set (pc) (pc))
2484 but not for a (set (pc) (label_ref FOO)). */
2487 update_cfg_for_uncondjump (rtx insn)
2489 basic_block bb = BLOCK_FOR_INSN (insn);
2490 gcc_assert (BB_END (bb) == insn);
2492 purge_dead_edges (bb);
2495 if (EDGE_COUNT (bb->succs) == 1)
2499 single_succ_edge (bb)->flags |= EDGE_FALLTHRU;
2501 /* Remove barriers from the footer if there are any. */
2502 for (insn = bb->il.rtl->footer; insn; insn = NEXT_INSN (insn))
2503 if (BARRIER_P (insn))
2505 if (PREV_INSN (insn))
2506 NEXT_INSN (PREV_INSN (insn)) = NEXT_INSN (insn);
2508 bb->il.rtl->footer = NEXT_INSN (insn);
2509 if (NEXT_INSN (insn))
2510 PREV_INSN (NEXT_INSN (insn)) = PREV_INSN (insn);
2512 else if (LABEL_P (insn))
2517 /* Try to combine the insns I0, I1 and I2 into I3.
2518 Here I0, I1 and I2 appear earlier than I3.
2519 I0 and I1 can be zero; then we combine just I2 into I3, or I1 and I2 into
2522 If we are combining more than two insns and the resulting insn is not
2523 recognized, try splitting it into two insns. If that happens, I2 and I3
2524 are retained and I1/I0 are pseudo-deleted by turning them into a NOTE.
2525 Otherwise, I0, I1 and I2 are pseudo-deleted.
2527 Return 0 if the combination does not work. Then nothing is changed.
2528 If we did the combination, return the insn at which combine should
2531 Set NEW_DIRECT_JUMP_P to a nonzero value if try_combine creates a
2532 new direct jump instruction.
2534 LAST_COMBINED_INSN is either I3, or some insn after I3 that has
2535 been I3 passed to an earlier try_combine within the same basic
2539 try_combine (rtx i3, rtx i2, rtx i1, rtx i0, int *new_direct_jump_p,
2540 rtx last_combined_insn)
2542 /* New patterns for I3 and I2, respectively. */
2543 rtx newpat, newi2pat = 0;
2544 rtvec newpat_vec_with_clobbers = 0;
2545 int substed_i2 = 0, substed_i1 = 0, substed_i0 = 0;
2546 /* Indicates need to preserve SET in I0, I1 or I2 in I3 if it is not
2548 int added_sets_0, added_sets_1, added_sets_2;
2549 /* Total number of SETs to put into I3. */
2551 /* Nonzero if I2's or I1's body now appears in I3. */
2552 int i2_is_used = 0, i1_is_used = 0;
2553 /* INSN_CODEs for new I3, new I2, and user of condition code. */
2554 int insn_code_number, i2_code_number = 0, other_code_number = 0;
2555 /* Contains I3 if the destination of I3 is used in its source, which means
2556 that the old life of I3 is being killed. If that usage is placed into
2557 I2 and not in I3, a REG_DEAD note must be made. */
2558 rtx i3dest_killed = 0;
2559 /* SET_DEST and SET_SRC of I2, I1 and I0. */
2560 rtx i2dest = 0, i2src = 0, i1dest = 0, i1src = 0, i0dest = 0, i0src = 0;
2561 /* Copy of SET_SRC of I1, if needed. */
2563 /* Set if I2DEST was reused as a scratch register. */
2564 bool i2scratch = false;
2565 /* The PATTERNs of I0, I1, and I2, or a copy of them in certain cases. */
2566 rtx i0pat = 0, i1pat = 0, i2pat = 0;
2567 /* Indicates if I2DEST or I1DEST is in I2SRC or I1_SRC. */
2568 int i2dest_in_i2src = 0, i1dest_in_i1src = 0, i2dest_in_i1src = 0;
2569 int i0dest_in_i0src = 0, i1dest_in_i0src = 0, i2dest_in_i0src = 0;
2570 int i2dest_killed = 0, i1dest_killed = 0, i0dest_killed = 0;
2571 int i1_feeds_i2_n = 0, i0_feeds_i2_n = 0, i0_feeds_i1_n = 0;
2572 /* Notes that must be added to REG_NOTES in I3 and I2. */
2573 rtx new_i3_notes, new_i2_notes;
2574 /* Notes that we substituted I3 into I2 instead of the normal case. */
2575 int i3_subst_into_i2 = 0;
2576 /* Notes that I1, I2 or I3 is a MULT operation. */
2579 int changed_i3_dest = 0;
2583 struct insn_link *link;
2585 rtx new_other_notes;
2588 /* Only try four-insn combinations when there's high likelihood of
2589 success. Look for simple insns, such as loads of constants or
2590 binary operations involving a constant. */
2597 if (!flag_expensive_optimizations)
2600 for (i = 0; i < 4; i++)
2602 rtx insn = i == 0 ? i0 : i == 1 ? i1 : i == 2 ? i2 : i3;
2603 rtx set = single_set (insn);
2607 src = SET_SRC (set);
2608 if (CONSTANT_P (src))
2613 else if (BINARY_P (src) && CONSTANT_P (XEXP (src, 1)))
2615 else if (GET_CODE (src) == ASHIFT || GET_CODE (src) == ASHIFTRT
2616 || GET_CODE (src) == LSHIFTRT)
2619 if (ngood < 2 && nshift < 2)
2623 /* Exit early if one of the insns involved can't be used for
2625 if (cant_combine_insn_p (i3)
2626 || cant_combine_insn_p (i2)
2627 || (i1 && cant_combine_insn_p (i1))
2628 || (i0 && cant_combine_insn_p (i0))
2629 || likely_spilled_retval_p (i3))
2633 undobuf.other_insn = 0;
2635 /* Reset the hard register usage information. */
2636 CLEAR_HARD_REG_SET (newpat_used_regs);
2638 if (dump_file && (dump_flags & TDF_DETAILS))
2641 fprintf (dump_file, "\nTrying %d, %d, %d -> %d:\n",
2642 INSN_UID (i0), INSN_UID (i1), INSN_UID (i2), INSN_UID (i3));
2644 fprintf (dump_file, "\nTrying %d, %d -> %d:\n",
2645 INSN_UID (i1), INSN_UID (i2), INSN_UID (i3));
2647 fprintf (dump_file, "\nTrying %d -> %d:\n",
2648 INSN_UID (i2), INSN_UID (i3));
2651 /* If multiple insns feed into one of I2 or I3, they can be in any
2652 order. To simplify the code below, reorder them in sequence. */
2653 if (i0 && DF_INSN_LUID (i0) > DF_INSN_LUID (i2))
2654 temp = i2, i2 = i0, i0 = temp;
2655 if (i0 && DF_INSN_LUID (i0) > DF_INSN_LUID (i1))
2656 temp = i1, i1 = i0, i0 = temp;
2657 if (i1 && DF_INSN_LUID (i1) > DF_INSN_LUID (i2))
2658 temp = i1, i1 = i2, i2 = temp;
2660 added_links_insn = 0;
2662 /* First check for one important special case that the code below will
2663 not handle. Namely, the case where I1 is zero, I2 is a PARALLEL
2664 and I3 is a SET whose SET_SRC is a SET_DEST in I2. In that case,
2665 we may be able to replace that destination with the destination of I3.
2666 This occurs in the common code where we compute both a quotient and
2667 remainder into a structure, in which case we want to do the computation
2668 directly into the structure to avoid register-register copies.
2670 Note that this case handles both multiple sets in I2 and also cases
2671 where I2 has a number of CLOBBERs inside the PARALLEL.
2673 We make very conservative checks below and only try to handle the
2674 most common cases of this. For example, we only handle the case
2675 where I2 and I3 are adjacent to avoid making difficult register
2678 if (i1 == 0 && NONJUMP_INSN_P (i3) && GET_CODE (PATTERN (i3)) == SET
2679 && REG_P (SET_SRC (PATTERN (i3)))
2680 && REGNO (SET_SRC (PATTERN (i3))) >= FIRST_PSEUDO_REGISTER
2681 && find_reg_note (i3, REG_DEAD, SET_SRC (PATTERN (i3)))
2682 && GET_CODE (PATTERN (i2)) == PARALLEL
2683 && ! side_effects_p (SET_DEST (PATTERN (i3)))
2684 /* If the dest of I3 is a ZERO_EXTRACT or STRICT_LOW_PART, the code
2685 below would need to check what is inside (and reg_overlap_mentioned_p
2686 doesn't support those codes anyway). Don't allow those destinations;
2687 the resulting insn isn't likely to be recognized anyway. */
2688 && GET_CODE (SET_DEST (PATTERN (i3))) != ZERO_EXTRACT
2689 && GET_CODE (SET_DEST (PATTERN (i3))) != STRICT_LOW_PART
2690 && ! reg_overlap_mentioned_p (SET_SRC (PATTERN (i3)),
2691 SET_DEST (PATTERN (i3)))
2692 && next_active_insn (i2) == i3)
2694 rtx p2 = PATTERN (i2);
2696 /* Make sure that the destination of I3,
2697 which we are going to substitute into one output of I2,
2698 is not used within another output of I2. We must avoid making this:
2699 (parallel [(set (mem (reg 69)) ...)
2700 (set (reg 69) ...)])
2701 which is not well-defined as to order of actions.
2702 (Besides, reload can't handle output reloads for this.)
2704 The problem can also happen if the dest of I3 is a memory ref,
2705 if another dest in I2 is an indirect memory ref. */
2706 for (i = 0; i < XVECLEN (p2, 0); i++)
2707 if ((GET_CODE (XVECEXP (p2, 0, i)) == SET
2708 || GET_CODE (XVECEXP (p2, 0, i)) == CLOBBER)
2709 && reg_overlap_mentioned_p (SET_DEST (PATTERN (i3)),
2710 SET_DEST (XVECEXP (p2, 0, i))))
2713 if (i == XVECLEN (p2, 0))
2714 for (i = 0; i < XVECLEN (p2, 0); i++)
2715 if (GET_CODE (XVECEXP (p2, 0, i)) == SET
2716 && SET_DEST (XVECEXP (p2, 0, i)) == SET_SRC (PATTERN (i3)))
2721 subst_low_luid = DF_INSN_LUID (i2);
2723 added_sets_2 = added_sets_1 = added_sets_0 = 0;
2724 i2src = SET_SRC (XVECEXP (p2, 0, i));
2725 i2dest = SET_DEST (XVECEXP (p2, 0, i));
2726 i2dest_killed = dead_or_set_p (i2, i2dest);
2728 /* Replace the dest in I2 with our dest and make the resulting
2729 insn the new pattern for I3. Then skip to where we validate
2730 the pattern. Everything was set up above. */
2731 SUBST (SET_DEST (XVECEXP (p2, 0, i)), SET_DEST (PATTERN (i3)));
2733 i3_subst_into_i2 = 1;
2734 goto validate_replacement;
2738 /* If I2 is setting a pseudo to a constant and I3 is setting some
2739 sub-part of it to another constant, merge them by making a new
2742 && (temp = single_set (i2)) != 0
2743 && (CONST_INT_P (SET_SRC (temp))
2744 || GET_CODE (SET_SRC (temp)) == CONST_DOUBLE)
2745 && GET_CODE (PATTERN (i3)) == SET
2746 && (CONST_INT_P (SET_SRC (PATTERN (i3)))
2747 || GET_CODE (SET_SRC (PATTERN (i3))) == CONST_DOUBLE)
2748 && reg_subword_p (SET_DEST (PATTERN (i3)), SET_DEST (temp)))
2750 rtx dest = SET_DEST (PATTERN (i3));
2754 if (GET_CODE (dest) == ZERO_EXTRACT)
2756 if (CONST_INT_P (XEXP (dest, 1))
2757 && CONST_INT_P (XEXP (dest, 2)))
2759 width = INTVAL (XEXP (dest, 1));
2760 offset = INTVAL (XEXP (dest, 2));
2761 dest = XEXP (dest, 0);
2762 if (BITS_BIG_ENDIAN)
2763 offset = GET_MODE_BITSIZE (GET_MODE (dest)) - width - offset;
2768 if (GET_CODE (dest) == STRICT_LOW_PART)
2769 dest = XEXP (dest, 0);
2770 width = GET_MODE_BITSIZE (GET_MODE (dest));
2776 /* If this is the low part, we're done. */
2777 if (subreg_lowpart_p (dest))
2779 /* Handle the case where inner is twice the size of outer. */
2780 else if (GET_MODE_BITSIZE (GET_MODE (SET_DEST (temp)))
2781 == 2 * GET_MODE_BITSIZE (GET_MODE (dest)))
2782 offset += GET_MODE_BITSIZE (GET_MODE (dest));
2783 /* Otherwise give up for now. */
2789 && (GET_MODE_BITSIZE (GET_MODE (SET_DEST (temp)))
2790 <= HOST_BITS_PER_DOUBLE_INT))
2793 rtx inner = SET_SRC (PATTERN (i3));
2794 rtx outer = SET_SRC (temp);
2796 o = rtx_to_double_int (outer);
2797 i = rtx_to_double_int (inner);
2799 m = double_int_mask (width);
2800 i = double_int_and (i, m);
2801 m = double_int_lshift (m, offset, HOST_BITS_PER_DOUBLE_INT, false);
2802 i = double_int_lshift (i, offset, HOST_BITS_PER_DOUBLE_INT, false);
2803 o = double_int_ior (double_int_and_not (o, m), i);
2807 subst_low_luid = DF_INSN_LUID (i2);
2808 added_sets_2 = added_sets_1 = added_sets_0 = 0;
2809 i2dest = SET_DEST (temp);
2810 i2dest_killed = dead_or_set_p (i2, i2dest);
2812 /* Replace the source in I2 with the new constant and make the
2813 resulting insn the new pattern for I3. Then skip to where we
2814 validate the pattern. Everything was set up above. */
2815 SUBST (SET_SRC (temp),
2816 immed_double_int_const (o, GET_MODE (SET_DEST (temp))));
2818 newpat = PATTERN (i2);
2820 /* The dest of I3 has been replaced with the dest of I2. */
2821 changed_i3_dest = 1;
2822 goto validate_replacement;
2827 /* If we have no I1 and I2 looks like:
2828 (parallel [(set (reg:CC X) (compare:CC OP (const_int 0)))
2830 make up a dummy I1 that is
2833 (set (reg:CC X) (compare:CC Y (const_int 0)))
2835 (We can ignore any trailing CLOBBERs.)
2837 This undoes a previous combination and allows us to match a branch-and-
2840 if (i1 == 0 && GET_CODE (PATTERN (i2)) == PARALLEL
2841 && XVECLEN (PATTERN (i2), 0) >= 2
2842 && GET_CODE (XVECEXP (PATTERN (i2), 0, 0)) == SET
2843 && (GET_MODE_CLASS (GET_MODE (SET_DEST (XVECEXP (PATTERN (i2), 0, 0))))
2845 && GET_CODE (SET_SRC (XVECEXP (PATTERN (i2), 0, 0))) == COMPARE
2846 && XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 1) == const0_rtx
2847 && GET_CODE (XVECEXP (PATTERN (i2), 0, 1)) == SET
2848 && REG_P (SET_DEST (XVECEXP (PATTERN (i2), 0, 1)))
2849 && rtx_equal_p (XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 0),
2850 SET_SRC (XVECEXP (PATTERN (i2), 0, 1))))
2852 for (i = XVECLEN (PATTERN (i2), 0) - 1; i >= 2; i--)
2853 if (GET_CODE (XVECEXP (PATTERN (i2), 0, i)) != CLOBBER)
2858 /* We make I1 with the same INSN_UID as I2. This gives it
2859 the same DF_INSN_LUID for value tracking. Our fake I1 will
2860 never appear in the insn stream so giving it the same INSN_UID
2861 as I2 will not cause a problem. */
2863 i1 = gen_rtx_INSN (VOIDmode, INSN_UID (i2), NULL_RTX, i2,
2864 BLOCK_FOR_INSN (i2), XVECEXP (PATTERN (i2), 0, 1),
2865 INSN_LOCATOR (i2), -1, NULL_RTX);
2867 SUBST (PATTERN (i2), XVECEXP (PATTERN (i2), 0, 0));
2868 SUBST (XEXP (SET_SRC (PATTERN (i2)), 0),
2869 SET_DEST (PATTERN (i1)));
2874 /* Verify that I2 and I1 are valid for combining. */
2875 if (! can_combine_p (i2, i3, i0, i1, NULL_RTX, NULL_RTX, &i2dest, &i2src)
2876 || (i1 && ! can_combine_p (i1, i3, i0, NULL_RTX, i2, NULL_RTX,
2878 || (i0 && ! can_combine_p (i0, i3, NULL_RTX, NULL_RTX, i1, i2,
2885 /* Record whether I2DEST is used in I2SRC and similarly for the other
2886 cases. Knowing this will help in register status updating below. */
2887 i2dest_in_i2src = reg_overlap_mentioned_p (i2dest, i2src);
2888 i1dest_in_i1src = i1 && reg_overlap_mentioned_p (i1dest, i1src);
2889 i2dest_in_i1src = i1 && reg_overlap_mentioned_p (i2dest, i1src);
2890 i0dest_in_i0src = i0 && reg_overlap_mentioned_p (i0dest, i0src);
2891 i1dest_in_i0src = i0 && reg_overlap_mentioned_p (i1dest, i0src);
2892 i2dest_in_i0src = i0 && reg_overlap_mentioned_p (i2dest, i0src);
2893 i2dest_killed = dead_or_set_p (i2, i2dest);
2894 i1dest_killed = i1 && dead_or_set_p (i1, i1dest);
2895 i0dest_killed = i0 && dead_or_set_p (i0, i0dest);
2897 /* For the earlier insns, determine which of the subsequent ones they
2899 i1_feeds_i2_n = i1 && insn_a_feeds_b (i1, i2);
2900 i0_feeds_i1_n = i0 && insn_a_feeds_b (i0, i1);
2901 i0_feeds_i2_n = (i0 && (!i0_feeds_i1_n ? insn_a_feeds_b (i0, i2)
2902 : (!reg_overlap_mentioned_p (i1dest, i0dest)
2903 && reg_overlap_mentioned_p (i0dest, i2src))));
2905 /* Ensure that I3's pattern can be the destination of combines. */
2906 if (! combinable_i3pat (i3, &PATTERN (i3), i2dest, i1dest, i0dest,
2907 i1 && i2dest_in_i1src && !i1_feeds_i2_n,
2908 i0 && ((i2dest_in_i0src && !i0_feeds_i2_n)
2909 || (i1dest_in_i0src && !i0_feeds_i1_n)),
2916 /* See if any of the insns is a MULT operation. Unless one is, we will
2917 reject a combination that is, since it must be slower. Be conservative
2919 if (GET_CODE (i2src) == MULT
2920 || (i1 != 0 && GET_CODE (i1src) == MULT)
2921 || (i0 != 0 && GET_CODE (i0src) == MULT)
2922 || (GET_CODE (PATTERN (i3)) == SET
2923 && GET_CODE (SET_SRC (PATTERN (i3))) == MULT))
2926 /* If I3 has an inc, then give up if I1 or I2 uses the reg that is inc'd.
2927 We used to do this EXCEPT in one case: I3 has a post-inc in an
2928 output operand. However, that exception can give rise to insns like
2930 which is a famous insn on the PDP-11 where the value of r3 used as the
2931 source was model-dependent. Avoid this sort of thing. */
2934 if (!(GET_CODE (PATTERN (i3)) == SET
2935 && REG_P (SET_SRC (PATTERN (i3)))
2936 && MEM_P (SET_DEST (PATTERN (i3)))
2937 && (GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_INC
2938 || GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_DEC)))
2939 /* It's not the exception. */
2944 for (link = REG_NOTES (i3); link; link = XEXP (link, 1))
2945 if (REG_NOTE_KIND (link) == REG_INC
2946 && (reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i2))
2948 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i1)))))
2956 /* See if the SETs in I1 or I2 need to be kept around in the merged
2957 instruction: whenever the value set there is still needed past I3.
2958 For the SETs in I2, this is easy: we see if I2DEST dies or is set in I3.
2960 For the SET in I1, we have two cases: If I1 and I2 independently
2961 feed into I3, the set in I1 needs to be kept around if I1DEST dies
2962 or is set in I3. Otherwise (if I1 feeds I2 which feeds I3), the set
2963 in I1 needs to be kept around unless I1DEST dies or is set in either
2964 I2 or I3. The same consideration applies to I0. */
2966 added_sets_2 = !dead_or_set_p (i3, i2dest);
2969 added_sets_1 = !(dead_or_set_p (i3, i1dest)
2970 || (i1_feeds_i2_n && dead_or_set_p (i2, i1dest)));
2975 added_sets_0 = !(dead_or_set_p (i3, i0dest)
2976 || (i0_feeds_i2_n && dead_or_set_p (i2, i0dest))
2977 || (i0_feeds_i1_n && dead_or_set_p (i1, i0dest)));
2981 /* We are about to copy insns for the case where they need to be kept
2982 around. Check that they can be copied in the merged instruction. */
2984 if (targetm.cannot_copy_insn_p
2985 && ((added_sets_2 && targetm.cannot_copy_insn_p (i2))
2986 || (i1 && added_sets_1 && targetm.cannot_copy_insn_p (i1))
2987 || (i0 && added_sets_0 && targetm.cannot_copy_insn_p (i0))))
2993 /* If the set in I2 needs to be kept around, we must make a copy of
2994 PATTERN (I2), so that when we substitute I1SRC for I1DEST in
2995 PATTERN (I2), we are only substituting for the original I1DEST, not into
2996 an already-substituted copy. This also prevents making self-referential
2997 rtx. If I2 is a PARALLEL, we just need the piece that assigns I2SRC to
3002 if (GET_CODE (PATTERN (i2)) == PARALLEL)
3003 i2pat = gen_rtx_SET (VOIDmode, i2dest, copy_rtx (i2src));
3005 i2pat = copy_rtx (PATTERN (i2));
3010 if (GET_CODE (PATTERN (i1)) == PARALLEL)
3011 i1pat = gen_rtx_SET (VOIDmode, i1dest, copy_rtx (i1src));
3013 i1pat = copy_rtx (PATTERN (i1));
3018 if (GET_CODE (PATTERN (i0)) == PARALLEL)
3019 i0pat = gen_rtx_SET (VOIDmode, i0dest, copy_rtx (i0src));
3021 i0pat = copy_rtx (PATTERN (i0));
3026 /* Substitute in the latest insn for the regs set by the earlier ones. */
3028 maxreg = max_reg_num ();
3033 /* Many machines that don't use CC0 have insns that can both perform an
3034 arithmetic operation and set the condition code. These operations will
3035 be represented as a PARALLEL with the first element of the vector
3036 being a COMPARE of an arithmetic operation with the constant zero.
3037 The second element of the vector will set some pseudo to the result
3038 of the same arithmetic operation. If we simplify the COMPARE, we won't
3039 match such a pattern and so will generate an extra insn. Here we test
3040 for this case, where both the comparison and the operation result are
3041 needed, and make the PARALLEL by just replacing I2DEST in I3SRC with
3042 I2SRC. Later we will make the PARALLEL that contains I2. */
3044 if (i1 == 0 && added_sets_2 && GET_CODE (PATTERN (i3)) == SET
3045 && GET_CODE (SET_SRC (PATTERN (i3))) == COMPARE
3046 && CONST_INT_P (XEXP (SET_SRC (PATTERN (i3)), 1))
3047 && rtx_equal_p (XEXP (SET_SRC (PATTERN (i3)), 0), i2dest))
3050 rtx *cc_use_loc = NULL, cc_use_insn = NULL_RTX;
3051 rtx op0 = i2src, op1 = XEXP (SET_SRC (PATTERN (i3)), 1);
3052 enum machine_mode compare_mode, orig_compare_mode;
3053 enum rtx_code compare_code = UNKNOWN, orig_compare_code = UNKNOWN;
3055 newpat = PATTERN (i3);
3056 newpat_dest = SET_DEST (newpat);
3057 compare_mode = orig_compare_mode = GET_MODE (newpat_dest);
3059 if (undobuf.other_insn == 0
3060 && (cc_use_loc = find_single_use (SET_DEST (newpat), i3,
3063 compare_code = orig_compare_code = GET_CODE (*cc_use_loc);
3064 compare_code = simplify_compare_const (compare_code,
3066 #ifdef CANONICALIZE_COMPARISON
3067 CANONICALIZE_COMPARISON (compare_code, op0, op1);
3071 /* Do the rest only if op1 is const0_rtx, which may be the
3072 result of simplification. */
3073 if (op1 == const0_rtx)
3075 /* If a single use of the CC is found, prepare to modify it
3076 when SELECT_CC_MODE returns a new CC-class mode, or when
3077 the above simplify_compare_const() returned a new comparison
3078 operator. undobuf.other_insn is assigned the CC use insn
3079 when modifying it. */
3082 #ifdef SELECT_CC_MODE
3083 enum machine_mode new_mode
3084 = SELECT_CC_MODE (compare_code, op0, op1);
3085 if (new_mode != orig_compare_mode
3086 && can_change_dest_mode (SET_DEST (newpat),
3087 added_sets_2, new_mode))
3089 unsigned int regno = REGNO (newpat_dest);
3090 compare_mode = new_mode;
3091 if (regno < FIRST_PSEUDO_REGISTER)
3092 newpat_dest = gen_rtx_REG (compare_mode, regno);
3095 SUBST_MODE (regno_reg_rtx[regno], compare_mode);
3096 newpat_dest = regno_reg_rtx[regno];
3100 /* Cases for modifying the CC-using comparison. */
3101 if (compare_code != orig_compare_code
3102 /* ??? Do we need to verify the zero rtx? */
3103 && XEXP (*cc_use_loc, 1) == const0_rtx)
3105 /* Replace cc_use_loc with entire new RTX. */
3107 gen_rtx_fmt_ee (compare_code, compare_mode,
3108 newpat_dest, const0_rtx));
3109 undobuf.other_insn = cc_use_insn;
3111 else if (compare_mode != orig_compare_mode)
3113 /* Just replace the CC reg with a new mode. */
3114 SUBST (XEXP (*cc_use_loc, 0), newpat_dest);
3115 undobuf.other_insn = cc_use_insn;
3119 /* Now we modify the current newpat:
3120 First, SET_DEST(newpat) is updated if the CC mode has been
3121 altered. For targets without SELECT_CC_MODE, this should be
3123 if (compare_mode != orig_compare_mode)
3124 SUBST (SET_DEST (newpat), newpat_dest);
3125 /* This is always done to propagate i2src into newpat. */
3126 SUBST (SET_SRC (newpat),
3127 gen_rtx_COMPARE (compare_mode, op0, op1));
3128 /* Create new version of i2pat if needed; the below PARALLEL
3129 creation needs this to work correctly. */
3130 if (! rtx_equal_p (i2src, op0))
3131 i2pat = gen_rtx_SET (VOIDmode, i2dest, op0);
3137 if (i2_is_used == 0)
3139 /* It is possible that the source of I2 or I1 may be performing
3140 an unneeded operation, such as a ZERO_EXTEND of something
3141 that is known to have the high part zero. Handle that case
3142 by letting subst look at the inner insns.
3144 Another way to do this would be to have a function that tries
3145 to simplify a single insn instead of merging two or more
3146 insns. We don't do this because of the potential of infinite
3147 loops and because of the potential extra memory required.
3148 However, doing it the way we are is a bit of a kludge and
3149 doesn't catch all cases.
3151 But only do this if -fexpensive-optimizations since it slows
3152 things down and doesn't usually win.
3154 This is not done in the COMPARE case above because the
3155 unmodified I2PAT is used in the PARALLEL and so a pattern
3156 with a modified I2SRC would not match. */
3158 if (flag_expensive_optimizations)
3160 /* Pass pc_rtx so no substitutions are done, just
3164 subst_low_luid = DF_INSN_LUID (i1);
3165 i1src = subst (i1src, pc_rtx, pc_rtx, 0, 0, 0);
3168 subst_low_luid = DF_INSN_LUID (i2);
3169 i2src = subst (i2src, pc_rtx, pc_rtx, 0, 0, 0);
3172 n_occurrences = 0; /* `subst' counts here */
3173 subst_low_luid = DF_INSN_LUID (i2);
3175 /* If I1 feeds into I2 and I1DEST is in I1SRC, we need to make a unique
3176 copy of I2SRC each time we substitute it, in order to avoid creating
3177 self-referential RTL when we will be substituting I1SRC for I1DEST
3178 later. Likewise if I0 feeds into I2, either directly or indirectly
3179 through I1, and I0DEST is in I0SRC. */
3180 newpat = subst (PATTERN (i3), i2dest, i2src, 0, 0,
3181 (i1_feeds_i2_n && i1dest_in_i1src)
3182 || ((i0_feeds_i2_n || (i0_feeds_i1_n && i1_feeds_i2_n))
3183 && i0dest_in_i0src));
3186 /* Record whether I2's body now appears within I3's body. */
3187 i2_is_used = n_occurrences;
3190 /* If we already got a failure, don't try to do more. Otherwise, try to
3191 substitute I1 if we have it. */
3193 if (i1 && GET_CODE (newpat) != CLOBBER)
3195 /* Check that an autoincrement side-effect on I1 has not been lost.
3196 This happens if I1DEST is mentioned in I2 and dies there, and
3197 has disappeared from the new pattern. */
3198 if ((FIND_REG_INC_NOTE (i1, NULL_RTX) != 0
3200 && dead_or_set_p (i2, i1dest)
3201 && !reg_overlap_mentioned_p (i1dest, newpat))
3202 /* Before we can do this substitution, we must redo the test done
3203 above (see detailed comments there) that ensures I1DEST isn't
3204 mentioned in any SETs in NEWPAT that are field assignments. */
3205 || !combinable_i3pat (NULL_RTX, &newpat, i1dest, NULL_RTX, NULL_RTX,
3213 subst_low_luid = DF_INSN_LUID (i1);
3215 /* If I0 feeds into I1 and I0DEST is in I0SRC, we need to make a unique
3216 copy of I1SRC each time we substitute it, in order to avoid creating
3217 self-referential RTL when we will be substituting I0SRC for I0DEST
3219 newpat = subst (newpat, i1dest, i1src, 0, 0,
3220 i0_feeds_i1_n && i0dest_in_i0src);
3223 /* Record whether I1's body now appears within I3's body. */
3224 i1_is_used = n_occurrences;
3227 /* Likewise for I0 if we have it. */
3229 if (i0 && GET_CODE (newpat) != CLOBBER)
3231 if ((FIND_REG_INC_NOTE (i0, NULL_RTX) != 0
3232 && ((i0_feeds_i2_n && dead_or_set_p (i2, i0dest))
3233 || (i0_feeds_i1_n && dead_or_set_p (i1, i0dest)))
3234 && !reg_overlap_mentioned_p (i0dest, newpat))
3235 || !combinable_i3pat (NULL_RTX, &newpat, i0dest, NULL_RTX, NULL_RTX,
3242 /* If the following substitution will modify I1SRC, make a copy of it
3243 for the case where it is substituted for I1DEST in I2PAT later. */
3244 if (i0_feeds_i1_n && added_sets_2 && i1_feeds_i2_n)
3245 i1src_copy = copy_rtx (i1src);
3248 subst_low_luid = DF_INSN_LUID (i0);
3249 newpat = subst (newpat, i0dest, i0src, 0, 0, 0);
3253 /* Fail if an autoincrement side-effect has been duplicated. Be careful
3254 to count all the ways that I2SRC and I1SRC can be used. */
3255 if ((FIND_REG_INC_NOTE (i2, NULL_RTX) != 0
3256 && i2_is_used + added_sets_2 > 1)
3257 || (i1 != 0 && FIND_REG_INC_NOTE (i1, NULL_RTX) != 0
3258 && (i1_is_used + added_sets_1 + (added_sets_2 && i1_feeds_i2_n)
3260 || (i0 != 0 && FIND_REG_INC_NOTE (i0, NULL_RTX) != 0
3261 && (n_occurrences + added_sets_0
3262 + (added_sets_1 && i0_feeds_i1_n)
3263 + (added_sets_2 && i0_feeds_i2_n)
3265 /* Fail if we tried to make a new register. */
3266 || max_reg_num () != maxreg
3267 /* Fail if we couldn't do something and have a CLOBBER. */
3268 || GET_CODE (newpat) == CLOBBER
3269 /* Fail if this new pattern is a MULT and we didn't have one before
3270 at the outer level. */
3271 || (GET_CODE (newpat) == SET && GET_CODE (SET_SRC (newpat)) == MULT
3278 /* If the actions of the earlier insns must be kept
3279 in addition to substituting them into the latest one,
3280 we must make a new PARALLEL for the latest insn
3281 to hold additional the SETs. */
3283 if (added_sets_0 || added_sets_1 || added_sets_2)
3285 int extra_sets = added_sets_0 + added_sets_1 + added_sets_2;
3288 if (GET_CODE (newpat) == PARALLEL)
3290 rtvec old = XVEC (newpat, 0);
3291 total_sets = XVECLEN (newpat, 0) + extra_sets;
3292 newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (total_sets));
3293 memcpy (XVEC (newpat, 0)->elem, &old->elem[0],
3294 sizeof (old->elem[0]) * old->num_elem);
3299 total_sets = 1 + extra_sets;
3300 newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (total_sets));
3301 XVECEXP (newpat, 0, 0) = old;
3305 XVECEXP (newpat, 0, --total_sets) = i0pat;
3311 t = subst (t, i0dest, i0src, 0, 0, 0);
3313 XVECEXP (newpat, 0, --total_sets) = t;
3319 t = subst (t, i1dest, i1src_copy ? i1src_copy : i1src, 0, 0,
3320 i0_feeds_i1_n && i0dest_in_i0src);
3321 if ((i0_feeds_i1_n && i1_feeds_i2_n) || i0_feeds_i2_n)
3322 t = subst (t, i0dest, i0src, 0, 0, 0);
3324 XVECEXP (newpat, 0, --total_sets) = t;
3328 validate_replacement:
3330 /* Note which hard regs this insn has as inputs. */
3331 mark_used_regs_combine (newpat);
3333 /* If recog_for_combine fails, it strips existing clobbers. If we'll
3334 consider splitting this pattern, we might need these clobbers. */
3335 if (i1 && GET_CODE (newpat) == PARALLEL
3336 && GET_CODE (XVECEXP (newpat, 0, XVECLEN (newpat, 0) - 1)) == CLOBBER)
3338 int len = XVECLEN (newpat, 0);
3340 newpat_vec_with_clobbers = rtvec_alloc (len);
3341 for (i = 0; i < len; i++)
3342 RTVEC_ELT (newpat_vec_with_clobbers, i) = XVECEXP (newpat, 0, i);
3345 /* Is the result of combination a valid instruction? */
3346 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
3348 /* If the result isn't valid, see if it is a PARALLEL of two SETs where
3349 the second SET's destination is a register that is unused and isn't
3350 marked as an instruction that might trap in an EH region. In that case,
3351 we just need the first SET. This can occur when simplifying a divmod
3352 insn. We *must* test for this case here because the code below that
3353 splits two independent SETs doesn't handle this case correctly when it
3354 updates the register status.
3356 It's pointless doing this if we originally had two sets, one from
3357 i3, and one from i2. Combining then splitting the parallel results
3358 in the original i2 again plus an invalid insn (which we delete).
3359 The net effect is only to move instructions around, which makes
3360 debug info less accurate.
3362 Also check the case where the first SET's destination is unused.
3363 That would not cause incorrect code, but does cause an unneeded
3366 if (insn_code_number < 0
3367 && !(added_sets_2 && i1 == 0)
3368 && GET_CODE (newpat) == PARALLEL
3369 && XVECLEN (newpat, 0) == 2
3370 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
3371 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
3372 && asm_noperands (newpat) < 0)
3374 rtx set0 = XVECEXP (newpat, 0, 0);
3375 rtx set1 = XVECEXP (newpat, 0, 1);
3377 if (((REG_P (SET_DEST (set1))
3378 && find_reg_note (i3, REG_UNUSED, SET_DEST (set1)))
3379 || (GET_CODE (SET_DEST (set1)) == SUBREG
3380 && find_reg_note (i3, REG_UNUSED, SUBREG_REG (SET_DEST (set1)))))
3381 && insn_nothrow_p (i3)
3382 && !side_effects_p (SET_SRC (set1)))
3385 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
3388 else if (((REG_P (SET_DEST (set0))
3389 && find_reg_note (i3, REG_UNUSED, SET_DEST (set0)))
3390 || (GET_CODE (SET_DEST (set0)) == SUBREG
3391 && find_reg_note (i3, REG_UNUSED,
3392 SUBREG_REG (SET_DEST (set0)))))
3393 && insn_nothrow_p (i3)
3394 && !side_effects_p (SET_SRC (set0)))
3397 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
3399 if (insn_code_number >= 0)
3400 changed_i3_dest = 1;
3404 /* If we were combining three insns and the result is a simple SET
3405 with no ASM_OPERANDS that wasn't recognized, try to split it into two
3406 insns. There are two ways to do this. It can be split using a
3407 machine-specific method (like when you have an addition of a large
3408 constant) or by combine in the function find_split_point. */
3410 if (i1 && insn_code_number < 0 && GET_CODE (newpat) == SET
3411 && asm_noperands (newpat) < 0)
3413 rtx parallel, m_split, *split;
3415 /* See if the MD file can split NEWPAT. If it can't, see if letting it
3416 use I2DEST as a scratch register will help. In the latter case,
3417 convert I2DEST to the mode of the source of NEWPAT if we can. */
3419 m_split = combine_split_insns (newpat, i3);
3421 /* We can only use I2DEST as a scratch reg if it doesn't overlap any
3422 inputs of NEWPAT. */
3424 /* ??? If I2DEST is not safe, and I1DEST exists, then it would be
3425 possible to try that as a scratch reg. This would require adding
3426 more code to make it work though. */
3428 if (m_split == 0 && ! reg_overlap_mentioned_p (i2dest, newpat))
3430 enum machine_mode new_mode = GET_MODE (SET_DEST (newpat));
3432 /* First try to split using the original register as a
3433 scratch register. */
3434 parallel = gen_rtx_PARALLEL (VOIDmode,
3435 gen_rtvec (2, newpat,
3436 gen_rtx_CLOBBER (VOIDmode,
3438 m_split = combine_split_insns (parallel, i3);
3440 /* If that didn't work, try changing the mode of I2DEST if
3443 && new_mode != GET_MODE (i2dest)
3444 && new_mode != VOIDmode
3445 && can_change_dest_mode (i2dest, added_sets_2, new_mode))
3447 enum machine_mode old_mode = GET_MODE (i2dest);
3450 if (REGNO (i2dest) < FIRST_PSEUDO_REGISTER)
3451 ni2dest = gen_rtx_REG (new_mode, REGNO (i2dest));
3454 SUBST_MODE (regno_reg_rtx[REGNO (i2dest)], new_mode);
3455 ni2dest = regno_reg_rtx[REGNO (i2dest)];
3458 parallel = (gen_rtx_PARALLEL
3460 gen_rtvec (2, newpat,
3461 gen_rtx_CLOBBER (VOIDmode,
3463 m_split = combine_split_insns (parallel, i3);
3466 && REGNO (i2dest) >= FIRST_PSEUDO_REGISTER)
3470 adjust_reg_mode (regno_reg_rtx[REGNO (i2dest)], old_mode);
3471 buf = undobuf.undos;
3472 undobuf.undos = buf->next;
3473 buf->next = undobuf.frees;
3474 undobuf.frees = buf;
3478 i2scratch = m_split != 0;
3481 /* If recog_for_combine has discarded clobbers, try to use them
3482 again for the split. */
3483 if (m_split == 0 && newpat_vec_with_clobbers)
3485 parallel = gen_rtx_PARALLEL (VOIDmode, newpat_vec_with_clobbers);
3486 m_split = combine_split_insns (parallel, i3);
3489 if (m_split && NEXT_INSN (m_split) == NULL_RTX)
3491 m_split = PATTERN (m_split);
3492 insn_code_number = recog_for_combine (&m_split, i3, &new_i3_notes);
3493 if (insn_code_number >= 0)
3496 else if (m_split && NEXT_INSN (NEXT_INSN (m_split)) == NULL_RTX
3497 && (next_nonnote_nondebug_insn (i2) == i3
3498 || ! use_crosses_set_p (PATTERN (m_split), DF_INSN_LUID (i2))))
3501 rtx newi3pat = PATTERN (NEXT_INSN (m_split));
3502 newi2pat = PATTERN (m_split);
3504 i3set = single_set (NEXT_INSN (m_split));
3505 i2set = single_set (m_split);
3507 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
3509 /* If I2 or I3 has multiple SETs, we won't know how to track
3510 register status, so don't use these insns. If I2's destination
3511 is used between I2 and I3, we also can't use these insns. */
3513 if (i2_code_number >= 0 && i2set && i3set
3514 && (next_nonnote_nondebug_insn (i2) == i3
3515 || ! reg_used_between_p (SET_DEST (i2set), i2, i3)))
3516 insn_code_number = recog_for_combine (&newi3pat, i3,
3518 if (insn_code_number >= 0)
3521 /* It is possible that both insns now set the destination of I3.
3522 If so, we must show an extra use of it. */
3524 if (insn_code_number >= 0)
3526 rtx new_i3_dest = SET_DEST (i3set);
3527 rtx new_i2_dest = SET_DEST (i2set);
3529 while (GET_CODE (new_i3_dest) == ZERO_EXTRACT
3530 || GET_CODE (new_i3_dest) == STRICT_LOW_PART
3531 || GET_CODE (new_i3_dest) == SUBREG)
3532 new_i3_dest = XEXP (new_i3_dest, 0);
3534 while (GET_CODE (new_i2_dest) == ZERO_EXTRACT
3535 || GET_CODE (new_i2_dest) == STRICT_LOW_PART
3536 || GET_CODE (new_i2_dest) == SUBREG)
3537 new_i2_dest = XEXP (new_i2_dest, 0);
3539 if (REG_P (new_i3_dest)
3540 && REG_P (new_i2_dest)
3541 && REGNO (new_i3_dest) == REGNO (new_i2_dest))
3542 INC_REG_N_SETS (REGNO (new_i2_dest), 1);
3546 /* If we can split it and use I2DEST, go ahead and see if that
3547 helps things be recognized. Verify that none of the registers
3548 are set between I2 and I3. */
3549 if (insn_code_number < 0
3550 && (split = find_split_point (&newpat, i3, false)) != 0
3554 /* We need I2DEST in the proper mode. If it is a hard register
3555 or the only use of a pseudo, we can change its mode.
3556 Make sure we don't change a hard register to have a mode that
3557 isn't valid for it, or change the number of registers. */
3558 && (GET_MODE (*split) == GET_MODE (i2dest)
3559 || GET_MODE (*split) == VOIDmode
3560 || can_change_dest_mode (i2dest, added_sets_2,
3562 && (next_nonnote_nondebug_insn (i2) == i3
3563 || ! use_crosses_set_p (*split, DF_INSN_LUID (i2)))
3564 /* We can't overwrite I2DEST if its value is still used by
3566 && ! reg_referenced_p (i2dest, newpat))
3568 rtx newdest = i2dest;
3569 enum rtx_code split_code = GET_CODE (*split);
3570 enum machine_mode split_mode = GET_MODE (*split);
3571 bool subst_done = false;
3572 newi2pat = NULL_RTX;
3576 /* *SPLIT may be part of I2SRC, so make sure we have the
3577 original expression around for later debug processing.
3578 We should not need I2SRC any more in other cases. */
3579 if (MAY_HAVE_DEBUG_INSNS)
3580 i2src = copy_rtx (i2src);
3584 /* Get NEWDEST as a register in the proper mode. We have already
3585 validated that we can do this. */
3586 if (GET_MODE (i2dest) != split_mode && split_mode != VOIDmode)
3588 if (REGNO (i2dest) < FIRST_PSEUDO_REGISTER)
3589 newdest = gen_rtx_REG (split_mode, REGNO (i2dest));
3592 SUBST_MODE (regno_reg_rtx[REGNO (i2dest)], split_mode);
3593 newdest = regno_reg_rtx[REGNO (i2dest)];
3597 /* If *SPLIT is a (mult FOO (const_int pow2)), convert it to
3598 an ASHIFT. This can occur if it was inside a PLUS and hence
3599 appeared to be a memory address. This is a kludge. */
3600 if (split_code == MULT
3601 && CONST_INT_P (XEXP (*split, 1))
3602 && INTVAL (XEXP (*split, 1)) > 0
3603 && (i = exact_log2 (UINTVAL (XEXP (*split, 1)))) >= 0)
3605 SUBST (*split, gen_rtx_ASHIFT (split_mode,
3606 XEXP (*split, 0), GEN_INT (i)));
3607 /* Update split_code because we may not have a multiply
3609 split_code = GET_CODE (*split);
3612 #ifdef INSN_SCHEDULING
3613 /* If *SPLIT is a paradoxical SUBREG, when we split it, it should
3614 be written as a ZERO_EXTEND. */
3615 if (split_code == SUBREG && MEM_P (SUBREG_REG (*split)))
3617 #ifdef LOAD_EXTEND_OP
3618 /* Or as a SIGN_EXTEND if LOAD_EXTEND_OP says that that's
3619 what it really is. */
3620 if (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (*split)))
3622 SUBST (*split, gen_rtx_SIGN_EXTEND (split_mode,
3623 SUBREG_REG (*split)));
3626 SUBST (*split, gen_rtx_ZERO_EXTEND (split_mode,
3627 SUBREG_REG (*split)));
3631 /* Attempt to split binary operators using arithmetic identities. */
3632 if (BINARY_P (SET_SRC (newpat))
3633 && split_mode == GET_MODE (SET_SRC (newpat))
3634 && ! side_effects_p (SET_SRC (newpat)))
3636 rtx setsrc = SET_SRC (newpat);
3637 enum machine_mode mode = GET_MODE (setsrc);
3638 enum rtx_code code = GET_CODE (setsrc);
3639 rtx src_op0 = XEXP (setsrc, 0);
3640 rtx src_op1 = XEXP (setsrc, 1);
3642 /* Split "X = Y op Y" as "Z = Y; X = Z op Z". */
3643 if (rtx_equal_p (src_op0, src_op1))
3645 newi2pat = gen_rtx_SET (VOIDmode, newdest, src_op0);
3646 SUBST (XEXP (setsrc, 0), newdest);
3647 SUBST (XEXP (setsrc, 1), newdest);
3650 /* Split "((P op Q) op R) op S" where op is PLUS or MULT. */
3651 else if ((code == PLUS || code == MULT)
3652 && GET_CODE (src_op0) == code
3653 && GET_CODE (XEXP (src_op0, 0)) == code
3654 && (INTEGRAL_MODE_P (mode)
3655 || (FLOAT_MODE_P (mode)
3656 && flag_unsafe_math_optimizations)))
3658 rtx p = XEXP (XEXP (src_op0, 0), 0);
3659 rtx q = XEXP (XEXP (src_op0, 0), 1);
3660 rtx r = XEXP (src_op0, 1);
3663 /* Split both "((X op Y) op X) op Y" and
3664 "((X op Y) op Y) op X" as "T op T" where T is
3666 if ((rtx_equal_p (p,r) && rtx_equal_p (q,s))
3667 || (rtx_equal_p (p,s) && rtx_equal_p (q,r)))
3669 newi2pat = gen_rtx_SET (VOIDmode, newdest,
3671 SUBST (XEXP (setsrc, 0), newdest);
3672 SUBST (XEXP (setsrc, 1), newdest);
3675 /* Split "((X op X) op Y) op Y)" as "T op T" where
3677 else if (rtx_equal_p (p,q) && rtx_equal_p (r,s))
3679 rtx tmp = simplify_gen_binary (code, mode, p, r);
3680 newi2pat = gen_rtx_SET (VOIDmode, newdest, tmp);
3681 SUBST (XEXP (setsrc, 0), newdest);
3682 SUBST (XEXP (setsrc, 1), newdest);
3690 newi2pat = gen_rtx_SET (VOIDmode, newdest, *split);
3691 SUBST (*split, newdest);
3694 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
3696 /* recog_for_combine might have added CLOBBERs to newi2pat.
3697 Make sure NEWPAT does not depend on the clobbered regs. */
3698 if (GET_CODE (newi2pat) == PARALLEL)
3699 for (i = XVECLEN (newi2pat, 0) - 1; i >= 0; i--)
3700 if (GET_CODE (XVECEXP (newi2pat, 0, i)) == CLOBBER)
3702 rtx reg = XEXP (XVECEXP (newi2pat, 0, i), 0);
3703 if (reg_overlap_mentioned_p (reg, newpat))
3710 /* If the split point was a MULT and we didn't have one before,
3711 don't use one now. */
3712 if (i2_code_number >= 0 && ! (split_code == MULT && ! have_mult))
3713 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
3717 /* Check for a case where we loaded from memory in a narrow mode and
3718 then sign extended it, but we need both registers. In that case,
3719 we have a PARALLEL with both loads from the same memory location.
3720 We can split this into a load from memory followed by a register-register
3721 copy. This saves at least one insn, more if register allocation can
3724 We cannot do this if the destination of the first assignment is a
3725 condition code register or cc0. We eliminate this case by making sure
3726 the SET_DEST and SET_SRC have the same mode.
3728 We cannot do this if the destination of the second assignment is
3729 a register that we have already assumed is zero-extended. Similarly
3730 for a SUBREG of such a register. */
3732 else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0
3733 && GET_CODE (newpat) == PARALLEL
3734 && XVECLEN (newpat, 0) == 2
3735 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
3736 && GET_CODE (SET_SRC (XVECEXP (newpat, 0, 0))) == SIGN_EXTEND
3737 && (GET_MODE (SET_DEST (XVECEXP (newpat, 0, 0)))
3738 == GET_MODE (SET_SRC (XVECEXP (newpat, 0, 0))))
3739 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
3740 && rtx_equal_p (SET_SRC (XVECEXP (newpat, 0, 1)),
3741 XEXP (SET_SRC (XVECEXP (newpat, 0, 0)), 0))
3742 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)),
3744 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
3745 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
3746 && ! (temp = SET_DEST (XVECEXP (newpat, 0, 1)),
3748 && VEC_index (reg_stat_type, reg_stat,
3749 REGNO (temp))->nonzero_bits != 0
3750 && GET_MODE_BITSIZE (GET_MODE (temp)) < BITS_PER_WORD
3751 && GET_MODE_BITSIZE (GET_MODE (temp)) < HOST_BITS_PER_INT
3752 && (VEC_index (reg_stat_type, reg_stat,
3753 REGNO (temp))->nonzero_bits
3754 != GET_MODE_MASK (word_mode))))
3755 && ! (GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) == SUBREG
3756 && (temp = SUBREG_REG (SET_DEST (XVECEXP (newpat, 0, 1))),
3758 && VEC_index (reg_stat_type, reg_stat,
3759 REGNO (temp))->nonzero_bits != 0
3760 && GET_MODE_BITSIZE (GET_MODE (temp)) < BITS_PER_WORD
3761 && GET_MODE_BITSIZE (GET_MODE (temp)) < HOST_BITS_PER_INT
3762 && (VEC_index (reg_stat_type, reg_stat,
3763 REGNO (temp))->nonzero_bits
3764 != GET_MODE_MASK (word_mode)))))
3765 && ! reg_overlap_mentioned_p (SET_DEST (XVECEXP (newpat, 0, 1)),
3766 SET_SRC (XVECEXP (newpat, 0, 1)))
3767 && ! find_reg_note (i3, REG_UNUSED,
3768 SET_DEST (XVECEXP (newpat, 0, 0))))
3772 newi2pat = XVECEXP (newpat, 0, 0);
3773 ni2dest = SET_DEST (XVECEXP (newpat, 0, 0));
3774 newpat = XVECEXP (newpat, 0, 1);
3775 SUBST (SET_SRC (newpat),
3776 gen_lowpart (GET_MODE (SET_SRC (newpat)), ni2dest));
3777 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
3779 if (i2_code_number >= 0)
3780 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
3782 if (insn_code_number >= 0)
3786 /* Similarly, check for a case where we have a PARALLEL of two independent
3787 SETs but we started with three insns. In this case, we can do the sets
3788 as two separate insns. This case occurs when some SET allows two
3789 other insns to combine, but the destination of that SET is still live. */
3791 else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0
3792 && GET_CODE (newpat) == PARALLEL
3793 && XVECLEN (newpat, 0) == 2
3794 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
3795 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != ZERO_EXTRACT
3796 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != STRICT_LOW_PART
3797 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
3798 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
3799 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
3800 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 1)),
3801 XVECEXP (newpat, 0, 0))
3802 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 0)),
3803 XVECEXP (newpat, 0, 1))
3804 && ! (contains_muldiv (SET_SRC (XVECEXP (newpat, 0, 0)))
3805 && contains_muldiv (SET_SRC (XVECEXP (newpat, 0, 1)))))
3807 /* Normally, it doesn't matter which of the two is done first,
3808 but the one that references cc0 can't be the second, and
3809 one which uses any regs/memory set in between i2 and i3 can't
3811 if (!use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)),
3814 && !reg_referenced_p (cc0_rtx, XVECEXP (newpat, 0, 0))
3818 newi2pat = XVECEXP (newpat, 0, 1);
3819 newpat = XVECEXP (newpat, 0, 0);
3821 else if (!use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 0)),
3824 && !reg_referenced_p (cc0_rtx, XVECEXP (newpat, 0, 1))
3828 newi2pat = XVECEXP (newpat, 0, 0);
3829 newpat = XVECEXP (newpat, 0, 1);
3837 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
3839 if (i2_code_number >= 0)
3841 /* recog_for_combine might have added CLOBBERs to newi2pat.
3842 Make sure NEWPAT does not depend on the clobbered regs. */
3843 if (GET_CODE (newi2pat) == PARALLEL)
3845 for (i = XVECLEN (newi2pat, 0) - 1; i >= 0; i--)
3846 if (GET_CODE (XVECEXP (newi2pat, 0, i)) == CLOBBER)
3848 rtx reg = XEXP (XVECEXP (newi2pat, 0, i), 0);
3849 if (reg_overlap_mentioned_p (reg, newpat))
3857 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
3861 /* If it still isn't recognized, fail and change things back the way they
3863 if ((insn_code_number < 0
3864 /* Is the result a reasonable ASM_OPERANDS? */
3865 && (! check_asm_operands (newpat) || added_sets_1 || added_sets_2)))
3871 /* If we had to change another insn, make sure it is valid also. */
3872 if (undobuf.other_insn)
3874 CLEAR_HARD_REG_SET (newpat_used_regs);
3876 other_pat = PATTERN (undobuf.other_insn);
3877 other_code_number = recog_for_combine (&other_pat, undobuf.other_insn,
3880 if (other_code_number < 0 && ! check_asm_operands (other_pat))
3888 /* If I2 is the CC0 setter and I3 is the CC0 user then check whether
3889 they are adjacent to each other or not. */
3891 rtx p = prev_nonnote_insn (i3);
3892 if (p && p != i2 && NONJUMP_INSN_P (p) && newi2pat
3893 && sets_cc0_p (newi2pat))
3901 /* Only allow this combination if insn_rtx_costs reports that the
3902 replacement instructions are cheaper than the originals. */
3903 if (!combine_validate_cost (i0, i1, i2, i3, newpat, newi2pat, other_pat))
3909 if (MAY_HAVE_DEBUG_INSNS)
3913 for (undo = undobuf.undos; undo; undo = undo->next)
3914 if (undo->kind == UNDO_MODE)
3916 rtx reg = *undo->where.r;
3917 enum machine_mode new_mode = GET_MODE (reg);
3918 enum machine_mode old_mode = undo->old_contents.m;
3920 /* Temporarily revert mode back. */
3921 adjust_reg_mode (reg, old_mode);
3923 if (reg == i2dest && i2scratch)
3925 /* If we used i2dest as a scratch register with a
3926 different mode, substitute it for the original
3927 i2src while its original mode is temporarily
3928 restored, and then clear i2scratch so that we don't
3929 do it again later. */
3930 propagate_for_debug (i2, last_combined_insn, reg, i2src);
3932 /* Put back the new mode. */
3933 adjust_reg_mode (reg, new_mode);
3937 rtx tempreg = gen_raw_REG (old_mode, REGNO (reg));
3943 last = last_combined_insn;
3948 last = undobuf.other_insn;
3950 if (DF_INSN_LUID (last)
3951 < DF_INSN_LUID (last_combined_insn))
3952 last = last_combined_insn;
3955 /* We're dealing with a reg that changed mode but not
3956 meaning, so we want to turn it into a subreg for
3957 the new mode. However, because of REG sharing and
3958 because its mode had already changed, we have to do
3959 it in two steps. First, replace any debug uses of
3960 reg, with its original mode temporarily restored,
3961 with this copy we have created; then, replace the
3962 copy with the SUBREG of the original shared reg,
3963 once again changed to the new mode. */
3964 propagate_for_debug (first, last, reg, tempreg);
3965 adjust_reg_mode (reg, new_mode);
3966 propagate_for_debug (first, last, tempreg,
3967 lowpart_subreg (old_mode, reg, new_mode));
3972 /* If we will be able to accept this, we have made a
3973 change to the destination of I3. This requires us to
3974 do a few adjustments. */
3976 if (changed_i3_dest)
3978 PATTERN (i3) = newpat;
3979 adjust_for_new_dest (i3);
3982 /* We now know that we can do this combination. Merge the insns and
3983 update the status of registers and LOG_LINKS. */
3985 if (undobuf.other_insn)
3989 PATTERN (undobuf.other_insn) = other_pat;
3991 /* If any of the notes in OTHER_INSN were REG_UNUSED, ensure that they
3992 are still valid. Then add any non-duplicate notes added by
3993 recog_for_combine. */
3994 for (note = REG_NOTES (undobuf.other_insn); note; note = next)
3996 next = XEXP (note, 1);
3998 if (REG_NOTE_KIND (note) == REG_UNUSED
3999 && ! reg_set_p (XEXP (note, 0), PATTERN (undobuf.other_insn)))
4000 remove_note (undobuf.other_insn, note);
4003 distribute_notes (new_other_notes, undobuf.other_insn,
4004 undobuf.other_insn, NULL_RTX, NULL_RTX, NULL_RTX,
4011 struct insn_link *link;
4014 /* I3 now uses what used to be its destination and which is now
4015 I2's destination. This requires us to do a few adjustments. */
4016 PATTERN (i3) = newpat;
4017 adjust_for_new_dest (i3);
4019 /* We need a LOG_LINK from I3 to I2. But we used to have one,
4022 However, some later insn might be using I2's dest and have
4023 a LOG_LINK pointing at I3. We must remove this link.
4024 The simplest way to remove the link is to point it at I1,
4025 which we know will be a NOTE. */
4027 /* newi2pat is usually a SET here; however, recog_for_combine might
4028 have added some clobbers. */
4029 if (GET_CODE (newi2pat) == PARALLEL)
4030 ni2dest = SET_DEST (XVECEXP (newi2pat, 0, 0));
4032 ni2dest = SET_DEST (newi2pat);
4034 for (insn = NEXT_INSN (i3);
4035 insn && (this_basic_block->next_bb == EXIT_BLOCK_PTR
4036 || insn != BB_HEAD (this_basic_block->next_bb));
4037 insn = NEXT_INSN (insn))
4039 if (INSN_P (insn) && reg_referenced_p (ni2dest, PATTERN (insn)))
4041 FOR_EACH_LOG_LINK (link, insn)
4042 if (link->insn == i3)
4051 rtx i3notes, i2notes, i1notes = 0, i0notes = 0;
4052 struct insn_link *i3links, *i2links, *i1links = 0, *i0links = 0;
4055 /* Compute which registers we expect to eliminate. newi2pat may be setting
4056 either i3dest or i2dest, so we must check it. Also, i1dest may be the
4057 same as i3dest, in which case newi2pat may be setting i1dest. */
4058 rtx elim_i2 = ((newi2pat && reg_set_p (i2dest, newi2pat))
4059 || i2dest_in_i2src || i2dest_in_i1src || i2dest_in_i0src
4062 rtx elim_i1 = (i1 == 0 || i1dest_in_i1src || i1dest_in_i0src
4063 || (newi2pat && reg_set_p (i1dest, newi2pat))
4066 rtx elim_i0 = (i0 == 0 || i0dest_in_i0src
4067 || (newi2pat && reg_set_p (i0dest, newi2pat))
4071 /* Get the old REG_NOTES and LOG_LINKS from all our insns and
4073 i3notes = REG_NOTES (i3), i3links = LOG_LINKS (i3);
4074 i2notes = REG_NOTES (i2), i2links = LOG_LINKS (i2);
4076 i1notes = REG_NOTES (i1), i1links = LOG_LINKS (i1);
4078 i0notes = REG_NOTES (i0), i0links = LOG_LINKS (i0);
4080 /* Ensure that we do not have something that should not be shared but
4081 occurs multiple times in the new insns. Check this by first
4082 resetting all the `used' flags and then copying anything is shared. */
4084 reset_used_flags (i3notes);
4085 reset_used_flags (i2notes);
4086 reset_used_flags (i1notes);
4087 reset_used_flags (i0notes);
4088 reset_used_flags (newpat);
4089 reset_used_flags (newi2pat);
4090 if (undobuf.other_insn)
4091 reset_used_flags (PATTERN (undobuf.other_insn));
4093 i3notes = copy_rtx_if_shared (i3notes);
4094 i2notes = copy_rtx_if_shared (i2notes);
4095 i1notes = copy_rtx_if_shared (i1notes);
4096 i0notes = copy_rtx_if_shared (i0notes);
4097 newpat = copy_rtx_if_shared (newpat);
4098 newi2pat = copy_rtx_if_shared (newi2pat);
4099 if (undobuf.other_insn)
4100 reset_used_flags (PATTERN (undobuf.other_insn));
4102 INSN_CODE (i3) = insn_code_number;
4103 PATTERN (i3) = newpat;
4105 if (CALL_P (i3) && CALL_INSN_FUNCTION_USAGE (i3))
4107 rtx call_usage = CALL_INSN_FUNCTION_USAGE (i3);
4109 reset_used_flags (call_usage);
4110 call_usage = copy_rtx (call_usage);
4114 /* I2SRC must still be meaningful at this point. Some splitting
4115 operations can invalidate I2SRC, but those operations do not
4118 replace_rtx (call_usage, i2dest, i2src);
4122 replace_rtx (call_usage, i1dest, i1src);
4124 replace_rtx (call_usage, i0dest, i0src);
4126 CALL_INSN_FUNCTION_USAGE (i3) = call_usage;
4129 if (undobuf.other_insn)
4130 INSN_CODE (undobuf.other_insn) = other_code_number;
4132 /* We had one special case above where I2 had more than one set and
4133 we replaced a destination of one of those sets with the destination
4134 of I3. In that case, we have to update LOG_LINKS of insns later
4135 in this basic block. Note that this (expensive) case is rare.
4137 Also, in this case, we must pretend that all REG_NOTEs for I2
4138 actually came from I3, so that REG_UNUSED notes from I2 will be
4139 properly handled. */
4141 if (i3_subst_into_i2)
4143 for (i = 0; i < XVECLEN (PATTERN (i2), 0); i++)
4144 if ((GET_CODE (XVECEXP (PATTERN (i2), 0, i)) == SET
4145 || GET_CODE (XVECEXP (PATTERN (i2), 0, i)) == CLOBBER)
4146 && REG_P (SET_DEST (XVECEXP (PATTERN (i2), 0, i)))
4147 && SET_DEST (XVECEXP (PATTERN (i2), 0, i)) != i2dest
4148 && ! find_reg_note (i2, REG_UNUSED,
4149 SET_DEST (XVECEXP (PATTERN (i2), 0, i))))
4150 for (temp = NEXT_INSN (i2);
4151 temp && (this_basic_block->next_bb == EXIT_BLOCK_PTR
4152 || BB_HEAD (this_basic_block) != temp);
4153 temp = NEXT_INSN (temp))
4154 if (temp != i3 && INSN_P (temp))
4155 FOR_EACH_LOG_LINK (link, temp)
4156 if (link->insn == i2)
4162 while (XEXP (link, 1))
4163 link = XEXP (link, 1);
4164 XEXP (link, 1) = i2notes;
4171 LOG_LINKS (i3) = NULL;
4173 LOG_LINKS (i2) = NULL;
4178 if (MAY_HAVE_DEBUG_INSNS && i2scratch)
4179 propagate_for_debug (i2, last_combined_insn, i2dest, i2src);
4180 INSN_CODE (i2) = i2_code_number;
4181 PATTERN (i2) = newi2pat;
4185 if (MAY_HAVE_DEBUG_INSNS && i2src)
4186 propagate_for_debug (i2, last_combined_insn, i2dest, i2src);
4187 SET_INSN_DELETED (i2);
4192 LOG_LINKS (i1) = NULL;
4194 if (MAY_HAVE_DEBUG_INSNS)
4195 propagate_for_debug (i1, last_combined_insn, i1dest, i1src);
4196 SET_INSN_DELETED (i1);
4201 LOG_LINKS (i0) = NULL;
4203 if (MAY_HAVE_DEBUG_INSNS)
4204 propagate_for_debug (i0, last_combined_insn, i0dest, i0src);
4205 SET_INSN_DELETED (i0);
4208 /* Get death notes for everything that is now used in either I3 or
4209 I2 and used to die in a previous insn. If we built two new
4210 patterns, move from I1 to I2 then I2 to I3 so that we get the
4211 proper movement on registers that I2 modifies. */
4214 from_luid = DF_INSN_LUID (i0);
4216 from_luid = DF_INSN_LUID (i1);
4218 from_luid = DF_INSN_LUID (i2);
4220 move_deaths (newi2pat, NULL_RTX, from_luid, i2, &midnotes);
4221 move_deaths (newpat, newi2pat, from_luid, i3, &midnotes);
4223 /* Distribute all the LOG_LINKS and REG_NOTES from I1, I2, and I3. */
4225 distribute_notes (i3notes, i3, i3, newi2pat ? i2 : NULL_RTX,
4226 elim_i2, elim_i1, elim_i0);
4228 distribute_notes (i2notes, i2, i3, newi2pat ? i2 : NULL_RTX,
4229 elim_i2, elim_i1, elim_i0);
4231 distribute_notes (i1notes, i1, i3, newi2pat ? i2 : NULL_RTX,
4232 elim_i2, elim_i1, elim_i0);
4234 distribute_notes (i0notes, i0, i3, newi2pat ? i2 : NULL_RTX,
4235 elim_i2, elim_i1, elim_i0);
4237 distribute_notes (midnotes, NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
4238 elim_i2, elim_i1, elim_i0);
4240 /* Distribute any notes added to I2 or I3 by recog_for_combine. We
4241 know these are REG_UNUSED and want them to go to the desired insn,
4242 so we always pass it as i3. */
4244 if (newi2pat && new_i2_notes)
4245 distribute_notes (new_i2_notes, i2, i2, NULL_RTX, NULL_RTX, NULL_RTX,
4249 distribute_notes (new_i3_notes, i3, i3, NULL_RTX, NULL_RTX, NULL_RTX,
4252 /* If I3DEST was used in I3SRC, it really died in I3. We may need to
4253 put a REG_DEAD note for it somewhere. If NEWI2PAT exists and sets
4254 I3DEST, the death must be somewhere before I2, not I3. If we passed I3
4255 in that case, it might delete I2. Similarly for I2 and I1.
4256 Show an additional death due to the REG_DEAD note we make here. If
4257 we discard it in distribute_notes, we will decrement it again. */
4261 if (newi2pat && reg_set_p (i3dest_killed, newi2pat))
4262 distribute_notes (alloc_reg_note (REG_DEAD, i3dest_killed,
4264 NULL_RTX, i2, NULL_RTX, elim_i2, elim_i1, elim_i0);
4266 distribute_notes (alloc_reg_note (REG_DEAD, i3dest_killed,
4268 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
4269 elim_i2, elim_i1, elim_i0);
4272 if (i2dest_in_i2src)
4274 rtx new_note = alloc_reg_note (REG_DEAD, i2dest, NULL_RTX);
4275 if (newi2pat && reg_set_p (i2dest, newi2pat))
4276 distribute_notes (new_note, NULL_RTX, i2, NULL_RTX, NULL_RTX,
4277 NULL_RTX, NULL_RTX);
4279 distribute_notes (new_note, NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
4280 NULL_RTX, NULL_RTX, NULL_RTX);
4283 if (i1dest_in_i1src)
4285 rtx new_note = alloc_reg_note (REG_DEAD, i1dest, NULL_RTX);
4286 if (newi2pat && reg_set_p (i1dest, newi2pat))
4287 distribute_notes (new_note, NULL_RTX, i2, NULL_RTX, NULL_RTX,
4288 NULL_RTX, NULL_RTX);
4290 distribute_notes (new_note, NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
4291 NULL_RTX, NULL_RTX, NULL_RTX);
4294 if (i0dest_in_i0src)
4296 rtx new_note = alloc_reg_note (REG_DEAD, i0dest, NULL_RTX);
4297 if (newi2pat && reg_set_p (i0dest, newi2pat))
4298 distribute_notes (new_note, NULL_RTX, i2, NULL_RTX, NULL_RTX,
4299 NULL_RTX, NULL_RTX);
4301 distribute_notes (new_note, NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
4302 NULL_RTX, NULL_RTX, NULL_RTX);
4305 distribute_links (i3links);
4306 distribute_links (i2links);
4307 distribute_links (i1links);
4308 distribute_links (i0links);
4312 struct insn_link *link;
4313 rtx i2_insn = 0, i2_val = 0, set;
4315 /* The insn that used to set this register doesn't exist, and
4316 this life of the register may not exist either. See if one of
4317 I3's links points to an insn that sets I2DEST. If it does,
4318 that is now the last known value for I2DEST. If we don't update
4319 this and I2 set the register to a value that depended on its old
4320 contents, we will get confused. If this insn is used, thing
4321 will be set correctly in combine_instructions. */
4322 FOR_EACH_LOG_LINK (link, i3)
4323 if ((set = single_set (link->insn)) != 0
4324 && rtx_equal_p (i2dest, SET_DEST (set)))
4325 i2_insn = link->insn, i2_val = SET_SRC (set);
4327 record_value_for_reg (i2dest, i2_insn, i2_val);
4329 /* If the reg formerly set in I2 died only once and that was in I3,
4330 zero its use count so it won't make `reload' do any work. */
4332 && (newi2pat == 0 || ! reg_mentioned_p (i2dest, newi2pat))
4333 && ! i2dest_in_i2src)
4334 INC_REG_N_SETS (REGNO (i2dest), -1);
4337 if (i1 && REG_P (i1dest))
4339 struct insn_link *link;
4340 rtx i1_insn = 0, i1_val = 0, set;
4342 FOR_EACH_LOG_LINK (link, i3)
4343 if ((set = single_set (link->insn)) != 0
4344 && rtx_equal_p (i1dest, SET_DEST (set)))
4345 i1_insn = link->insn, i1_val = SET_SRC (set);
4347 record_value_for_reg (i1dest, i1_insn, i1_val);
4349 if (! added_sets_1 && ! i1dest_in_i1src)
4350 INC_REG_N_SETS (REGNO (i1dest), -1);
4353 if (i0 && REG_P (i0dest))
4355 struct insn_link *link;
4356 rtx i0_insn = 0, i0_val = 0, set;
4358 FOR_EACH_LOG_LINK (link, i3)
4359 if ((set = single_set (link->insn)) != 0
4360 && rtx_equal_p (i0dest, SET_DEST (set)))
4361 i0_insn = link->insn, i0_val = SET_SRC (set);
4363 record_value_for_reg (i0dest, i0_insn, i0_val);
4365 if (! added_sets_0 && ! i0dest_in_i0src)
4366 INC_REG_N_SETS (REGNO (i0dest), -1);
4369 /* Update reg_stat[].nonzero_bits et al for any changes that may have
4370 been made to this insn. The order of
4371 set_nonzero_bits_and_sign_copies() is important. Because newi2pat
4372 can affect nonzero_bits of newpat */
4374 note_stores (newi2pat, set_nonzero_bits_and_sign_copies, NULL);
4375 note_stores (newpat, set_nonzero_bits_and_sign_copies, NULL);
4378 if (undobuf.other_insn != NULL_RTX)
4382 fprintf (dump_file, "modifying other_insn ");
4383 dump_insn_slim (dump_file, undobuf.other_insn);
4385 df_insn_rescan (undobuf.other_insn);
4388 if (i0 && !(NOTE_P(i0) && (NOTE_KIND (i0) == NOTE_INSN_DELETED)))
4392 fprintf (dump_file, "modifying insn i1 ");
4393 dump_insn_slim (dump_file, i0);
4395 df_insn_rescan (i0);
4398 if (i1 && !(NOTE_P(i1) && (NOTE_KIND (i1) == NOTE_INSN_DELETED)))
4402 fprintf (dump_file, "modifying insn i1 ");
4403 dump_insn_slim (dump_file, i1);
4405 df_insn_rescan (i1);
4408 if (i2 && !(NOTE_P(i2) && (NOTE_KIND (i2) == NOTE_INSN_DELETED)))
4412 fprintf (dump_file, "modifying insn i2 ");
4413 dump_insn_slim (dump_file, i2);
4415 df_insn_rescan (i2);
4418 if (i3 && !(NOTE_P(i3) && (NOTE_KIND (i3) == NOTE_INSN_DELETED)))
4422 fprintf (dump_file, "modifying insn i3 ");
4423 dump_insn_slim (dump_file, i3);
4425 df_insn_rescan (i3);
4428 /* Set new_direct_jump_p if a new return or simple jump instruction
4429 has been created. Adjust the CFG accordingly. */
4431 if (returnjump_p (i3) || any_uncondjump_p (i3))
4433 *new_direct_jump_p = 1;
4434 mark_jump_label (PATTERN (i3), i3, 0);
4435 update_cfg_for_uncondjump (i3);
4438 if (undobuf.other_insn != NULL_RTX
4439 && (returnjump_p (undobuf.other_insn)
4440 || any_uncondjump_p (undobuf.other_insn)))
4442 *new_direct_jump_p = 1;
4443 update_cfg_for_uncondjump (undobuf.other_insn);
4446 /* A noop might also need cleaning up of CFG, if it comes from the
4447 simplification of a jump. */
4449 && GET_CODE (newpat) == SET
4450 && SET_SRC (newpat) == pc_rtx
4451 && SET_DEST (newpat) == pc_rtx)
4453 *new_direct_jump_p = 1;
4454 update_cfg_for_uncondjump (i3);
4457 if (undobuf.other_insn != NULL_RTX
4458 && JUMP_P (undobuf.other_insn)
4459 && GET_CODE (PATTERN (undobuf.other_insn)) == SET
4460 && SET_SRC (PATTERN (undobuf.other_insn)) == pc_rtx
4461 && SET_DEST (PATTERN (undobuf.other_insn)) == pc_rtx)
4463 *new_direct_jump_p = 1;
4464 update_cfg_for_uncondjump (undobuf.other_insn);
4467 combine_successes++;
4470 if (added_links_insn
4471 && (newi2pat == 0 || DF_INSN_LUID (added_links_insn) < DF_INSN_LUID (i2))
4472 && DF_INSN_LUID (added_links_insn) < DF_INSN_LUID (i3))
4473 return added_links_insn;
4475 return newi2pat ? i2 : i3;
4478 /* Undo all the modifications recorded in undobuf. */
4483 struct undo *undo, *next;
4485 for (undo = undobuf.undos; undo; undo = next)
4491 *undo->where.r = undo->old_contents.r;
4494 *undo->where.i = undo->old_contents.i;
4497 adjust_reg_mode (*undo->where.r, undo->old_contents.m);
4503 undo->next = undobuf.frees;
4504 undobuf.frees = undo;
4510 /* We've committed to accepting the changes we made. Move all
4511 of the undos to the free list. */
4516 struct undo *undo, *next;
4518 for (undo = undobuf.undos; undo; undo = next)
4521 undo->next = undobuf.frees;
4522 undobuf.frees = undo;
4527 /* Find the innermost point within the rtx at LOC, possibly LOC itself,
4528 where we have an arithmetic expression and return that point. LOC will
4531 try_combine will call this function to see if an insn can be split into
4535 find_split_point (rtx *loc, rtx insn, bool set_src)
4538 enum rtx_code code = GET_CODE (x);
4540 unsigned HOST_WIDE_INT len = 0;
4541 HOST_WIDE_INT pos = 0;
4543 rtx inner = NULL_RTX;
4545 /* First special-case some codes. */
4549 #ifdef INSN_SCHEDULING
4550 /* If we are making a paradoxical SUBREG invalid, it becomes a split
4552 if (MEM_P (SUBREG_REG (x)))
4555 return find_split_point (&SUBREG_REG (x), insn, false);
4559 /* If we have (mem (const ..)) or (mem (symbol_ref ...)), split it
4560 using LO_SUM and HIGH. */
4561 if (GET_CODE (XEXP (x, 0)) == CONST
4562 || GET_CODE (XEXP (x, 0)) == SYMBOL_REF)
4564 enum machine_mode address_mode
4565 = targetm.addr_space.address_mode (MEM_ADDR_SPACE (x));
4568 gen_rtx_LO_SUM (address_mode,
4569 gen_rtx_HIGH (address_mode, XEXP (x, 0)),
4571 return &XEXP (XEXP (x, 0), 0);
4575 /* If we have a PLUS whose second operand is a constant and the
4576 address is not valid, perhaps will can split it up using
4577 the machine-specific way to split large constants. We use
4578 the first pseudo-reg (one of the virtual regs) as a placeholder;
4579 it will not remain in the result. */
4580 if (GET_CODE (XEXP (x, 0)) == PLUS
4581 && CONST_INT_P (XEXP (XEXP (x, 0), 1))
4582 && ! memory_address_addr_space_p (GET_MODE (x), XEXP (x, 0),
4583 MEM_ADDR_SPACE (x)))
4585 rtx reg = regno_reg_rtx[FIRST_PSEUDO_REGISTER];
4586 rtx seq = combine_split_insns (gen_rtx_SET (VOIDmode, reg,
4590 /* This should have produced two insns, each of which sets our
4591 placeholder. If the source of the second is a valid address,
4592 we can make put both sources together and make a split point
4596 && NEXT_INSN (seq) != NULL_RTX
4597 && NEXT_INSN (NEXT_INSN (seq)) == NULL_RTX
4598 && NONJUMP_INSN_P (seq)
4599 && GET_CODE (PATTERN (seq)) == SET
4600 && SET_DEST (PATTERN (seq)) == reg
4601 && ! reg_mentioned_p (reg,
4602 SET_SRC (PATTERN (seq)))
4603 && NONJUMP_INSN_P (NEXT_INSN (seq))
4604 && GET_CODE (PATTERN (NEXT_INSN (seq))) == SET
4605 && SET_DEST (PATTERN (NEXT_INSN (seq))) == reg
4606 && memory_address_addr_space_p
4607 (GET_MODE (x), SET_SRC (PATTERN (NEXT_INSN (seq))),
4608 MEM_ADDR_SPACE (x)))
4610 rtx src1 = SET_SRC (PATTERN (seq));
4611 rtx src2 = SET_SRC (PATTERN (NEXT_INSN (seq)));
4613 /* Replace the placeholder in SRC2 with SRC1. If we can
4614 find where in SRC2 it was placed, that can become our
4615 split point and we can replace this address with SRC2.
4616 Just try two obvious places. */
4618 src2 = replace_rtx (src2, reg, src1);
4620 if (XEXP (src2, 0) == src1)
4621 split = &XEXP (src2, 0);
4622 else if (GET_RTX_FORMAT (GET_CODE (XEXP (src2, 0)))[0] == 'e'
4623 && XEXP (XEXP (src2, 0), 0) == src1)
4624 split = &XEXP (XEXP (src2, 0), 0);
4628 SUBST (XEXP (x, 0), src2);
4633 /* If that didn't work, perhaps the first operand is complex and
4634 needs to be computed separately, so make a split point there.
4635 This will occur on machines that just support REG + CONST
4636 and have a constant moved through some previous computation. */
4638 else if (!OBJECT_P (XEXP (XEXP (x, 0), 0))
4639 && ! (GET_CODE (XEXP (XEXP (x, 0), 0)) == SUBREG
4640 && OBJECT_P (SUBREG_REG (XEXP (XEXP (x, 0), 0)))))
4641 return &XEXP (XEXP (x, 0), 0);
4644 /* If we have a PLUS whose first operand is complex, try computing it
4645 separately by making a split there. */
4646 if (GET_CODE (XEXP (x, 0)) == PLUS
4647 && ! memory_address_addr_space_p (GET_MODE (x), XEXP (x, 0),
4649 && ! OBJECT_P (XEXP (XEXP (x, 0), 0))
4650 && ! (GET_CODE (XEXP (XEXP (x, 0), 0)) == SUBREG
4651 && OBJECT_P (SUBREG_REG (XEXP (XEXP (x, 0), 0)))))
4652 return &XEXP (XEXP (x, 0), 0);
4657 /* If SET_DEST is CC0 and SET_SRC is not an operand, a COMPARE, or a
4658 ZERO_EXTRACT, the most likely reason why this doesn't match is that
4659 we need to put the operand into a register. So split at that
4662 if (SET_DEST (x) == cc0_rtx
4663 && GET_CODE (SET_SRC (x)) != COMPARE
4664 && GET_CODE (SET_SRC (x)) != ZERO_EXTRACT
4665 && !OBJECT_P (SET_SRC (x))
4666 && ! (GET_CODE (SET_SRC (x)) == SUBREG
4667 && OBJECT_P (SUBREG_REG (SET_SRC (x)))))
4668 return &SET_SRC (x);
4671 /* See if we can split SET_SRC as it stands. */
4672 split = find_split_point (&SET_SRC (x), insn, true);
4673 if (split && split != &SET_SRC (x))
4676 /* See if we can split SET_DEST as it stands. */
4677 split = find_split_point (&SET_DEST (x), insn, false);
4678 if (split && split != &SET_DEST (x))
4681 /* See if this is a bitfield assignment with everything constant. If
4682 so, this is an IOR of an AND, so split it into that. */
4683 if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
4684 && (GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0)))
4685 <= HOST_BITS_PER_WIDE_INT)
4686 && CONST_INT_P (XEXP (SET_DEST (x), 1))
4687 && CONST_INT_P (XEXP (SET_DEST (x), 2))
4688 && CONST_INT_P (SET_SRC (x))
4689 && ((INTVAL (XEXP (SET_DEST (x), 1))
4690 + INTVAL (XEXP (SET_DEST (x), 2)))
4691 <= GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0))))
4692 && ! side_effects_p (XEXP (SET_DEST (x), 0)))
4694 HOST_WIDE_INT pos = INTVAL (XEXP (SET_DEST (x), 2));
4695 unsigned HOST_WIDE_INT len = INTVAL (XEXP (SET_DEST (x), 1));
4696 unsigned HOST_WIDE_INT src = INTVAL (SET_SRC (x));
4697 rtx dest = XEXP (SET_DEST (x), 0);
4698 enum machine_mode mode = GET_MODE (dest);
4699 unsigned HOST_WIDE_INT mask
4700 = ((unsigned HOST_WIDE_INT) 1 << len) - 1;
4703 if (BITS_BIG_ENDIAN)
4704 pos = GET_MODE_BITSIZE (mode) - len - pos;
4706 or_mask = gen_int_mode (src << pos, mode);
4709 simplify_gen_binary (IOR, mode, dest, or_mask));
4712 rtx negmask = gen_int_mode (~(mask << pos), mode);
4714 simplify_gen_binary (IOR, mode,
4715 simplify_gen_binary (AND, mode,
4720 SUBST (SET_DEST (x), dest);
4722 split = find_split_point (&SET_SRC (x), insn, true);
4723 if (split && split != &SET_SRC (x))
4727 /* Otherwise, see if this is an operation that we can split into two.
4728 If so, try to split that. */
4729 code = GET_CODE (SET_SRC (x));
4734 /* If we are AND'ing with a large constant that is only a single
4735 bit and the result is only being used in a context where we
4736 need to know if it is zero or nonzero, replace it with a bit
4737 extraction. This will avoid the large constant, which might
4738 have taken more than one insn to make. If the constant were
4739 not a valid argument to the AND but took only one insn to make,
4740 this is no worse, but if it took more than one insn, it will
4743 if (CONST_INT_P (XEXP (SET_SRC (x), 1))
4744 && REG_P (XEXP (SET_SRC (x), 0))
4745 && (pos = exact_log2 (UINTVAL (XEXP (SET_SRC (x), 1)))) >= 7
4746 && REG_P (SET_DEST (x))
4747 && (split = find_single_use (SET_DEST (x), insn, (rtx*) 0)) != 0
4748 && (GET_CODE (*split) == EQ || GET_CODE (*split) == NE)
4749 && XEXP (*split, 0) == SET_DEST (x)
4750 && XEXP (*split, 1) == const0_rtx)
4752 rtx extraction = make_extraction (GET_MODE (SET_DEST (x)),
4753 XEXP (SET_SRC (x), 0),
4754 pos, NULL_RTX, 1, 1, 0, 0);
4755 if (extraction != 0)
4757 SUBST (SET_SRC (x), extraction);
4758 return find_split_point (loc, insn, false);
4764 /* If STORE_FLAG_VALUE is -1, this is (NE X 0) and only one bit of X
4765 is known to be on, this can be converted into a NEG of a shift. */
4766 if (STORE_FLAG_VALUE == -1 && XEXP (SET_SRC (x), 1) == const0_rtx
4767 && GET_MODE (SET_SRC (x)) == GET_MODE (XEXP (SET_SRC (x), 0))
4768 && 1 <= (pos = exact_log2
4769 (nonzero_bits (XEXP (SET_SRC (x), 0),
4770 GET_MODE (XEXP (SET_SRC (x), 0))))))
4772 enum machine_mode mode = GET_MODE (XEXP (SET_SRC (x), 0));
4776 gen_rtx_LSHIFTRT (mode,
4777 XEXP (SET_SRC (x), 0),
4780 split = find_split_point (&SET_SRC (x), insn, true);
4781 if (split && split != &SET_SRC (x))
4787 inner = XEXP (SET_SRC (x), 0);
4789 /* We can't optimize if either mode is a partial integer
4790 mode as we don't know how many bits are significant
4792 if (GET_MODE_CLASS (GET_MODE (inner)) == MODE_PARTIAL_INT
4793 || GET_MODE_CLASS (GET_MODE (SET_SRC (x))) == MODE_PARTIAL_INT)
4797 len = GET_MODE_BITSIZE (GET_MODE (inner));
4803 if (CONST_INT_P (XEXP (SET_SRC (x), 1))
4804 && CONST_INT_P (XEXP (SET_SRC (x), 2)))
4806 inner = XEXP (SET_SRC (x), 0);
4807 len = INTVAL (XEXP (SET_SRC (x), 1));
4808 pos = INTVAL (XEXP (SET_SRC (x), 2));
4810 if (BITS_BIG_ENDIAN)
4811 pos = GET_MODE_BITSIZE (GET_MODE (inner)) - len - pos;
4812 unsignedp = (code == ZERO_EXTRACT);
4820 if (len && pos >= 0 && pos + len <= GET_MODE_BITSIZE (GET_MODE (inner)))
4822 enum machine_mode mode = GET_MODE (SET_SRC (x));
4824 /* For unsigned, we have a choice of a shift followed by an
4825 AND or two shifts. Use two shifts for field sizes where the
4826 constant might be too large. We assume here that we can
4827 always at least get 8-bit constants in an AND insn, which is
4828 true for every current RISC. */
4830 if (unsignedp && len <= 8)
4835 (mode, gen_lowpart (mode, inner),
4837 GEN_INT (((unsigned HOST_WIDE_INT) 1 << len)
4840 split = find_split_point (&SET_SRC (x), insn, true);
4841 if (split && split != &SET_SRC (x))
4848 (unsignedp ? LSHIFTRT : ASHIFTRT, mode,
4849 gen_rtx_ASHIFT (mode,
4850 gen_lowpart (mode, inner),
4851 GEN_INT (GET_MODE_BITSIZE (mode)
4853 GEN_INT (GET_MODE_BITSIZE (mode) - len)));
4855 split = find_split_point (&SET_SRC (x), insn, true);
4856 if (split && split != &SET_SRC (x))
4861 /* See if this is a simple operation with a constant as the second
4862 operand. It might be that this constant is out of range and hence
4863 could be used as a split point. */
4864 if (BINARY_P (SET_SRC (x))
4865 && CONSTANT_P (XEXP (SET_SRC (x), 1))
4866 && (OBJECT_P (XEXP (SET_SRC (x), 0))
4867 || (GET_CODE (XEXP (SET_SRC (x), 0)) == SUBREG
4868 && OBJECT_P (SUBREG_REG (XEXP (SET_SRC (x), 0))))))
4869 return &XEXP (SET_SRC (x), 1);
4871 /* Finally, see if this is a simple operation with its first operand
4872 not in a register. The operation might require this operand in a
4873 register, so return it as a split point. We can always do this
4874 because if the first operand were another operation, we would have
4875 already found it as a split point. */
4876 if ((BINARY_P (SET_SRC (x)) || UNARY_P (SET_SRC (x)))
4877 && ! register_operand (XEXP (SET_SRC (x), 0), VOIDmode))
4878 return &XEXP (SET_SRC (x), 0);
4884 /* We write NOR as (and (not A) (not B)), but if we don't have a NOR,
4885 it is better to write this as (not (ior A B)) so we can split it.
4886 Similarly for IOR. */
4887 if (GET_CODE (XEXP (x, 0)) == NOT && GET_CODE (XEXP (x, 1)) == NOT)
4890 gen_rtx_NOT (GET_MODE (x),
4891 gen_rtx_fmt_ee (code == IOR ? AND : IOR,
4893 XEXP (XEXP (x, 0), 0),
4894 XEXP (XEXP (x, 1), 0))));
4895 return find_split_point (loc, insn, set_src);
4898 /* Many RISC machines have a large set of logical insns. If the
4899 second operand is a NOT, put it first so we will try to split the
4900 other operand first. */
4901 if (GET_CODE (XEXP (x, 1)) == NOT)
4903 rtx tem = XEXP (x, 0);
4904 SUBST (XEXP (x, 0), XEXP (x, 1));
4905 SUBST (XEXP (x, 1), tem);
4911 /* Canonicalization can produce (minus A (mult B C)), where C is a
4912 constant. It may be better to try splitting (plus (mult B -C) A)
4913 instead if this isn't a multiply by a power of two. */
4914 if (set_src && code == MINUS && GET_CODE (XEXP (x, 1)) == MULT
4915 && GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT
4916 && exact_log2 (INTVAL (XEXP (XEXP (x, 1), 1))) < 0)
4918 enum machine_mode mode = GET_MODE (x);
4919 unsigned HOST_WIDE_INT this_int = INTVAL (XEXP (XEXP (x, 1), 1));
4920 HOST_WIDE_INT other_int = trunc_int_for_mode (-this_int, mode);
4921 SUBST (*loc, gen_rtx_PLUS (mode, gen_rtx_MULT (mode,
4922 XEXP (XEXP (x, 1), 0),
4923 GEN_INT (other_int)),
4925 return find_split_point (loc, insn, set_src);
4928 /* Split at a multiply-accumulate instruction. However if this is
4929 the SET_SRC, we likely do not have such an instruction and it's
4930 worthless to try this split. */
4931 if (!set_src && GET_CODE (XEXP (x, 0)) == MULT)
4938 /* Otherwise, select our actions depending on our rtx class. */
4939 switch (GET_RTX_CLASS (code))
4941 case RTX_BITFIELD_OPS: /* This is ZERO_EXTRACT and SIGN_EXTRACT. */
4943 split = find_split_point (&XEXP (x, 2), insn, false);
4946 /* ... fall through ... */
4948 case RTX_COMM_ARITH:
4950 case RTX_COMM_COMPARE:
4951 split = find_split_point (&XEXP (x, 1), insn, false);
4954 /* ... fall through ... */
4956 /* Some machines have (and (shift ...) ...) insns. If X is not
4957 an AND, but XEXP (X, 0) is, use it as our split point. */
4958 if (GET_CODE (x) != AND && GET_CODE (XEXP (x, 0)) == AND)
4959 return &XEXP (x, 0);
4961 split = find_split_point (&XEXP (x, 0), insn, false);
4967 /* Otherwise, we don't have a split point. */
4972 /* Throughout X, replace FROM with TO, and return the result.
4973 The result is TO if X is FROM;
4974 otherwise the result is X, but its contents may have been modified.
4975 If they were modified, a record was made in undobuf so that
4976 undo_all will (among other things) return X to its original state.
4978 If the number of changes necessary is too much to record to undo,
4979 the excess changes are not made, so the result is invalid.
4980 The changes already made can still be undone.
4981 undobuf.num_undo is incremented for such changes, so by testing that
4982 the caller can tell whether the result is valid.
4984 `n_occurrences' is incremented each time FROM is replaced.
4986 IN_DEST is nonzero if we are processing the SET_DEST of a SET.
4988 IN_COND is nonzero if we are at the top level of a condition.
4990 UNIQUE_COPY is nonzero if each substitution must be unique. We do this
4991 by copying if `n_occurrences' is nonzero. */
4994 subst (rtx x, rtx from, rtx to, int in_dest, int in_cond, int unique_copy)
4996 enum rtx_code code = GET_CODE (x);
4997 enum machine_mode op0_mode = VOIDmode;
5002 /* Two expressions are equal if they are identical copies of a shared
5003 RTX or if they are both registers with the same register number
5006 #define COMBINE_RTX_EQUAL_P(X,Y) \
5008 || (REG_P (X) && REG_P (Y) \
5009 && REGNO (X) == REGNO (Y) && GET_MODE (X) == GET_MODE (Y)))
5011 if (! in_dest && COMBINE_RTX_EQUAL_P (x, from))
5014 return (unique_copy && n_occurrences > 1 ? copy_rtx (to) : to);
5017 /* If X and FROM are the same register but different modes, they
5018 will not have been seen as equal above. However, the log links code
5019 will make a LOG_LINKS entry for that case. If we do nothing, we
5020 will try to rerecognize our original insn and, when it succeeds,
5021 we will delete the feeding insn, which is incorrect.
5023 So force this insn not to match in this (rare) case. */
5024 if (! in_dest && code == REG && REG_P (from)
5025 && reg_overlap_mentioned_p (x, from))
5026 return gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
5028 /* If this is an object, we are done unless it is a MEM or LO_SUM, both
5029 of which may contain things that can be combined. */
5030 if (code != MEM && code != LO_SUM && OBJECT_P (x))
5033 /* It is possible to have a subexpression appear twice in the insn.
5034 Suppose that FROM is a register that appears within TO.
5035 Then, after that subexpression has been scanned once by `subst',
5036 the second time it is scanned, TO may be found. If we were
5037 to scan TO here, we would find FROM within it and create a
5038 self-referent rtl structure which is completely wrong. */
5039 if (COMBINE_RTX_EQUAL_P (x, to))
5042 /* Parallel asm_operands need special attention because all of the
5043 inputs are shared across the arms. Furthermore, unsharing the
5044 rtl results in recognition failures. Failure to handle this case
5045 specially can result in circular rtl.
5047 Solve this by doing a normal pass across the first entry of the
5048 parallel, and only processing the SET_DESTs of the subsequent
5051 if (code == PARALLEL
5052 && GET_CODE (XVECEXP (x, 0, 0)) == SET
5053 && GET_CODE (SET_SRC (XVECEXP (x, 0, 0))) == ASM_OPERANDS)
5055 new_rtx = subst (XVECEXP (x, 0, 0), from, to, 0, 0, unique_copy);
5057 /* If this substitution failed, this whole thing fails. */
5058 if (GET_CODE (new_rtx) == CLOBBER
5059 && XEXP (new_rtx, 0) == const0_rtx)
5062 SUBST (XVECEXP (x, 0, 0), new_rtx);
5064 for (i = XVECLEN (x, 0) - 1; i >= 1; i--)
5066 rtx dest = SET_DEST (XVECEXP (x, 0, i));
5069 && GET_CODE (dest) != CC0
5070 && GET_CODE (dest) != PC)
5072 new_rtx = subst (dest, from, to, 0, 0, unique_copy);
5074 /* If this substitution failed, this whole thing fails. */
5075 if (GET_CODE (new_rtx) == CLOBBER
5076 && XEXP (new_rtx, 0) == const0_rtx)
5079 SUBST (SET_DEST (XVECEXP (x, 0, i)), new_rtx);
5085 len = GET_RTX_LENGTH (code);
5086 fmt = GET_RTX_FORMAT (code);
5088 /* We don't need to process a SET_DEST that is a register, CC0,
5089 or PC, so set up to skip this common case. All other cases
5090 where we want to suppress replacing something inside a
5091 SET_SRC are handled via the IN_DEST operand. */
5093 && (REG_P (SET_DEST (x))
5094 || GET_CODE (SET_DEST (x)) == CC0
5095 || GET_CODE (SET_DEST (x)) == PC))
5098 /* Get the mode of operand 0 in case X is now a SIGN_EXTEND of a
5101 op0_mode = GET_MODE (XEXP (x, 0));
5103 for (i = 0; i < len; i++)
5108 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
5110 if (COMBINE_RTX_EQUAL_P (XVECEXP (x, i, j), from))
5112 new_rtx = (unique_copy && n_occurrences
5113 ? copy_rtx (to) : to);
5118 new_rtx = subst (XVECEXP (x, i, j), from, to, 0, 0,
5121 /* If this substitution failed, this whole thing
5123 if (GET_CODE (new_rtx) == CLOBBER
5124 && XEXP (new_rtx, 0) == const0_rtx)
5128 SUBST (XVECEXP (x, i, j), new_rtx);
5131 else if (fmt[i] == 'e')
5133 /* If this is a register being set, ignore it. */
5134 new_rtx = XEXP (x, i);
5137 && (((code == SUBREG || code == ZERO_EXTRACT)
5139 || code == STRICT_LOW_PART))
5142 else if (COMBINE_RTX_EQUAL_P (XEXP (x, i), from))
5144 /* In general, don't install a subreg involving two
5145 modes not tieable. It can worsen register
5146 allocation, and can even make invalid reload
5147 insns, since the reg inside may need to be copied
5148 from in the outside mode, and that may be invalid
5149 if it is an fp reg copied in integer mode.
5151 We allow two exceptions to this: It is valid if
5152 it is inside another SUBREG and the mode of that
5153 SUBREG and the mode of the inside of TO is
5154 tieable and it is valid if X is a SET that copies
5157 if (GET_CODE (to) == SUBREG
5158 && ! MODES_TIEABLE_P (GET_MODE (to),
5159 GET_MODE (SUBREG_REG (to)))
5160 && ! (code == SUBREG
5161 && MODES_TIEABLE_P (GET_MODE (x),
5162 GET_MODE (SUBREG_REG (to))))
5164 && ! (code == SET && i == 1 && XEXP (x, 0) == cc0_rtx)
5167 return gen_rtx_CLOBBER (VOIDmode, const0_rtx);
5169 #ifdef CANNOT_CHANGE_MODE_CLASS
5172 && REGNO (to) < FIRST_PSEUDO_REGISTER
5173 && REG_CANNOT_CHANGE_MODE_P (REGNO (to),
5176 return gen_rtx_CLOBBER (VOIDmode, const0_rtx);
5179 new_rtx = (unique_copy && n_occurrences ? copy_rtx (to) : to);
5183 /* If we are in a SET_DEST, suppress most cases unless we
5184 have gone inside a MEM, in which case we want to
5185 simplify the address. We assume here that things that
5186 are actually part of the destination have their inner
5187 parts in the first expression. This is true for SUBREG,
5188 STRICT_LOW_PART, and ZERO_EXTRACT, which are the only
5189 things aside from REG and MEM that should appear in a
5191 new_rtx = subst (XEXP (x, i), from, to,
5193 && (code == SUBREG || code == STRICT_LOW_PART
5194 || code == ZERO_EXTRACT))
5197 code == IF_THEN_ELSE && i == 0,
5200 /* If we found that we will have to reject this combination,
5201 indicate that by returning the CLOBBER ourselves, rather than
5202 an expression containing it. This will speed things up as
5203 well as prevent accidents where two CLOBBERs are considered
5204 to be equal, thus producing an incorrect simplification. */
5206 if (GET_CODE (new_rtx) == CLOBBER && XEXP (new_rtx, 0) == const0_rtx)
5209 if (GET_CODE (x) == SUBREG
5210 && (CONST_INT_P (new_rtx)
5211 || GET_CODE (new_rtx) == CONST_DOUBLE))
5213 enum machine_mode mode = GET_MODE (x);
5215 x = simplify_subreg (GET_MODE (x), new_rtx,
5216 GET_MODE (SUBREG_REG (x)),
5219 x = gen_rtx_CLOBBER (mode, const0_rtx);
5221 else if (CONST_INT_P (new_rtx)
5222 && GET_CODE (x) == ZERO_EXTEND)
5224 x = simplify_unary_operation (ZERO_EXTEND, GET_MODE (x),
5225 new_rtx, GET_MODE (XEXP (x, 0)));
5229 SUBST (XEXP (x, i), new_rtx);
5234 /* Check if we are loading something from the constant pool via float
5235 extension; in this case we would undo compress_float_constant
5236 optimization and degenerate constant load to an immediate value. */
5237 if (GET_CODE (x) == FLOAT_EXTEND
5238 && MEM_P (XEXP (x, 0))
5239 && MEM_READONLY_P (XEXP (x, 0)))
5241 rtx tmp = avoid_constant_pool_reference (x);
5246 /* Try to simplify X. If the simplification changed the code, it is likely
5247 that further simplification will help, so loop, but limit the number
5248 of repetitions that will be performed. */
5250 for (i = 0; i < 4; i++)
5252 /* If X is sufficiently simple, don't bother trying to do anything
5254 if (code != CONST_INT && code != REG && code != CLOBBER)
5255 x = combine_simplify_rtx (x, op0_mode, in_dest, in_cond);
5257 if (GET_CODE (x) == code)
5260 code = GET_CODE (x);
5262 /* We no longer know the original mode of operand 0 since we
5263 have changed the form of X) */
5264 op0_mode = VOIDmode;
5270 /* Simplify X, a piece of RTL. We just operate on the expression at the
5271 outer level; call `subst' to simplify recursively. Return the new
5274 OP0_MODE is the original mode of XEXP (x, 0). IN_DEST is nonzero
5275 if we are inside a SET_DEST. IN_COND is nonzero if we are at the top level
5279 combine_simplify_rtx (rtx x, enum machine_mode op0_mode, int in_dest,
5282 enum rtx_code code = GET_CODE (x);
5283 enum machine_mode mode = GET_MODE (x);
5287 /* If this is a commutative operation, put a constant last and a complex
5288 expression first. We don't need to do this for comparisons here. */
5289 if (COMMUTATIVE_ARITH_P (x)
5290 && swap_commutative_operands_p (XEXP (x, 0), XEXP (x, 1)))
5293 SUBST (XEXP (x, 0), XEXP (x, 1));
5294 SUBST (XEXP (x, 1), temp);
5297 /* If this is a simple operation applied to an IF_THEN_ELSE, try
5298 applying it to the arms of the IF_THEN_ELSE. This often simplifies
5299 things. Check for cases where both arms are testing the same
5302 Don't do anything if all operands are very simple. */
5305 && ((!OBJECT_P (XEXP (x, 0))
5306 && ! (GET_CODE (XEXP (x, 0)) == SUBREG
5307 && OBJECT_P (SUBREG_REG (XEXP (x, 0)))))
5308 || (!OBJECT_P (XEXP (x, 1))
5309 && ! (GET_CODE (XEXP (x, 1)) == SUBREG
5310 && OBJECT_P (SUBREG_REG (XEXP (x, 1)))))))
5312 && (!OBJECT_P (XEXP (x, 0))
5313 && ! (GET_CODE (XEXP (x, 0)) == SUBREG
5314 && OBJECT_P (SUBREG_REG (XEXP (x, 0)))))))
5316 rtx cond, true_rtx, false_rtx;
5318 cond = if_then_else_cond (x, &true_rtx, &false_rtx);
5320 /* If everything is a comparison, what we have is highly unlikely
5321 to be simpler, so don't use it. */
5322 && ! (COMPARISON_P (x)
5323 && (COMPARISON_P (true_rtx) || COMPARISON_P (false_rtx))))
5325 rtx cop1 = const0_rtx;
5326 enum rtx_code cond_code = simplify_comparison (NE, &cond, &cop1);
5328 if (cond_code == NE && COMPARISON_P (cond))
5331 /* Simplify the alternative arms; this may collapse the true and
5332 false arms to store-flag values. Be careful to use copy_rtx
5333 here since true_rtx or false_rtx might share RTL with x as a
5334 result of the if_then_else_cond call above. */
5335 true_rtx = subst (copy_rtx (true_rtx), pc_rtx, pc_rtx, 0, 0, 0);
5336 false_rtx = subst (copy_rtx (false_rtx), pc_rtx, pc_rtx, 0, 0, 0);
5338 /* If true_rtx and false_rtx are not general_operands, an if_then_else
5339 is unlikely to be simpler. */
5340 if (general_operand (true_rtx, VOIDmode)
5341 && general_operand (false_rtx, VOIDmode))
5343 enum rtx_code reversed;
5345 /* Restarting if we generate a store-flag expression will cause
5346 us to loop. Just drop through in this case. */
5348 /* If the result values are STORE_FLAG_VALUE and zero, we can
5349 just make the comparison operation. */
5350 if (true_rtx == const_true_rtx && false_rtx == const0_rtx)
5351 x = simplify_gen_relational (cond_code, mode, VOIDmode,
5353 else if (true_rtx == const0_rtx && false_rtx == const_true_rtx
5354 && ((reversed = reversed_comparison_code_parts
5355 (cond_code, cond, cop1, NULL))
5357 x = simplify_gen_relational (reversed, mode, VOIDmode,
5360 /* Likewise, we can make the negate of a comparison operation
5361 if the result values are - STORE_FLAG_VALUE and zero. */
5362 else if (CONST_INT_P (true_rtx)
5363 && INTVAL (true_rtx) == - STORE_FLAG_VALUE
5364 && false_rtx == const0_rtx)
5365 x = simplify_gen_unary (NEG, mode,
5366 simplify_gen_relational (cond_code,
5370 else if (CONST_INT_P (false_rtx)
5371 && INTVAL (false_rtx) == - STORE_FLAG_VALUE
5372 && true_rtx == const0_rtx
5373 && ((reversed = reversed_comparison_code_parts
5374 (cond_code, cond, cop1, NULL))
5376 x = simplify_gen_unary (NEG, mode,
5377 simplify_gen_relational (reversed,
5382 return gen_rtx_IF_THEN_ELSE (mode,
5383 simplify_gen_relational (cond_code,
5388 true_rtx, false_rtx);
5390 code = GET_CODE (x);
5391 op0_mode = VOIDmode;
5396 /* Try to fold this expression in case we have constants that weren't
5399 switch (GET_RTX_CLASS (code))
5402 if (op0_mode == VOIDmode)
5403 op0_mode = GET_MODE (XEXP (x, 0));
5404 temp = simplify_unary_operation (code, mode, XEXP (x, 0), op0_mode);
5407 case RTX_COMM_COMPARE:
5409 enum machine_mode cmp_mode = GET_MODE (XEXP (x, 0));
5410 if (cmp_mode == VOIDmode)
5412 cmp_mode = GET_MODE (XEXP (x, 1));
5413 if (cmp_mode == VOIDmode)
5414 cmp_mode = op0_mode;
5416 temp = simplify_relational_operation (code, mode, cmp_mode,
5417 XEXP (x, 0), XEXP (x, 1));
5420 case RTX_COMM_ARITH:
5422 temp = simplify_binary_operation (code, mode, XEXP (x, 0), XEXP (x, 1));
5424 case RTX_BITFIELD_OPS:
5426 temp = simplify_ternary_operation (code, mode, op0_mode, XEXP (x, 0),
5427 XEXP (x, 1), XEXP (x, 2));
5436 code = GET_CODE (temp);
5437 op0_mode = VOIDmode;
5438 mode = GET_MODE (temp);
5441 /* First see if we can apply the inverse distributive law. */
5442 if (code == PLUS || code == MINUS
5443 || code == AND || code == IOR || code == XOR)
5445 x = apply_distributive_law (x);
5446 code = GET_CODE (x);
5447 op0_mode = VOIDmode;
5450 /* If CODE is an associative operation not otherwise handled, see if we
5451 can associate some operands. This can win if they are constants or
5452 if they are logically related (i.e. (a & b) & a). */
5453 if ((code == PLUS || code == MINUS || code == MULT || code == DIV
5454 || code == AND || code == IOR || code == XOR
5455 || code == SMAX || code == SMIN || code == UMAX || code == UMIN)
5456 && ((INTEGRAL_MODE_P (mode) && code != DIV)
5457 || (flag_associative_math && FLOAT_MODE_P (mode))))
5459 if (GET_CODE (XEXP (x, 0)) == code)
5461 rtx other = XEXP (XEXP (x, 0), 0);
5462 rtx inner_op0 = XEXP (XEXP (x, 0), 1);
5463 rtx inner_op1 = XEXP (x, 1);
5466 /* Make sure we pass the constant operand if any as the second
5467 one if this is a commutative operation. */
5468 if (CONSTANT_P (inner_op0) && COMMUTATIVE_ARITH_P (x))
5470 rtx tem = inner_op0;
5471 inner_op0 = inner_op1;
5474 inner = simplify_binary_operation (code == MINUS ? PLUS
5475 : code == DIV ? MULT
5477 mode, inner_op0, inner_op1);
5479 /* For commutative operations, try the other pair if that one
5481 if (inner == 0 && COMMUTATIVE_ARITH_P (x))
5483 other = XEXP (XEXP (x, 0), 1);
5484 inner = simplify_binary_operation (code, mode,
5485 XEXP (XEXP (x, 0), 0),
5490 return simplify_gen_binary (code, mode, other, inner);
5494 /* A little bit of algebraic simplification here. */
5498 /* Ensure that our address has any ASHIFTs converted to MULT in case
5499 address-recognizing predicates are called later. */
5500 temp = make_compound_operation (XEXP (x, 0), MEM);
5501 SUBST (XEXP (x, 0), temp);
5505 if (op0_mode == VOIDmode)
5506 op0_mode = GET_MODE (SUBREG_REG (x));
5508 /* See if this can be moved to simplify_subreg. */
5509 if (CONSTANT_P (SUBREG_REG (x))
5510 && subreg_lowpart_offset (mode, op0_mode) == SUBREG_BYTE (x)
5511 /* Don't call gen_lowpart if the inner mode
5512 is VOIDmode and we cannot simplify it, as SUBREG without
5513 inner mode is invalid. */
5514 && (GET_MODE (SUBREG_REG (x)) != VOIDmode
5515 || gen_lowpart_common (mode, SUBREG_REG (x))))
5516 return gen_lowpart (mode, SUBREG_REG (x));
5518 if (GET_MODE_CLASS (GET_MODE (SUBREG_REG (x))) == MODE_CC)
5522 temp = simplify_subreg (mode, SUBREG_REG (x), op0_mode,
5528 /* Don't change the mode of the MEM if that would change the meaning
5530 if (MEM_P (SUBREG_REG (x))
5531 && (MEM_VOLATILE_P (SUBREG_REG (x))
5532 || mode_dependent_address_p (XEXP (SUBREG_REG (x), 0))))
5533 return gen_rtx_CLOBBER (mode, const0_rtx);
5535 /* Note that we cannot do any narrowing for non-constants since
5536 we might have been counting on using the fact that some bits were
5537 zero. We now do this in the SET. */
5542 temp = expand_compound_operation (XEXP (x, 0));
5544 /* For C equal to the width of MODE minus 1, (neg (ashiftrt X C)) can be
5545 replaced by (lshiftrt X C). This will convert
5546 (neg (sign_extract X 1 Y)) to (zero_extract X 1 Y). */
5548 if (GET_CODE (temp) == ASHIFTRT
5549 && CONST_INT_P (XEXP (temp, 1))
5550 && INTVAL (XEXP (temp, 1)) == GET_MODE_BITSIZE (mode) - 1)
5551 return simplify_shift_const (NULL_RTX, LSHIFTRT, mode, XEXP (temp, 0),
5552 INTVAL (XEXP (temp, 1)));
5554 /* If X has only a single bit that might be nonzero, say, bit I, convert
5555 (neg X) to (ashiftrt (ashift X C-I) C-I) where C is the bitsize of
5556 MODE minus 1. This will convert (neg (zero_extract X 1 Y)) to
5557 (sign_extract X 1 Y). But only do this if TEMP isn't a register
5558 or a SUBREG of one since we'd be making the expression more
5559 complex if it was just a register. */
5562 && ! (GET_CODE (temp) == SUBREG
5563 && REG_P (SUBREG_REG (temp)))
5564 && (i = exact_log2 (nonzero_bits (temp, mode))) >= 0)
5566 rtx temp1 = simplify_shift_const
5567 (NULL_RTX, ASHIFTRT, mode,
5568 simplify_shift_const (NULL_RTX, ASHIFT, mode, temp,
5569 GET_MODE_BITSIZE (mode) - 1 - i),
5570 GET_MODE_BITSIZE (mode) - 1 - i);
5572 /* If all we did was surround TEMP with the two shifts, we
5573 haven't improved anything, so don't use it. Otherwise,
5574 we are better off with TEMP1. */
5575 if (GET_CODE (temp1) != ASHIFTRT
5576 || GET_CODE (XEXP (temp1, 0)) != ASHIFT
5577 || XEXP (XEXP (temp1, 0), 0) != temp)
5583 /* We can't handle truncation to a partial integer mode here
5584 because we don't know the real bitsize of the partial
5586 if (GET_MODE_CLASS (mode) == MODE_PARTIAL_INT)
5589 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
5591 force_to_mode (XEXP (x, 0), GET_MODE (XEXP (x, 0)),
5592 GET_MODE_MASK (mode), 0));
5594 /* We can truncate a constant value and return it. */
5595 if (CONST_INT_P (XEXP (x, 0)))
5596 return gen_int_mode (INTVAL (XEXP (x, 0)), mode);
5598 /* Similarly to what we do in simplify-rtx.c, a truncate of a register
5599 whose value is a comparison can be replaced with a subreg if
5600 STORE_FLAG_VALUE permits. */
5601 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5602 && (STORE_FLAG_VALUE & ~GET_MODE_MASK (mode)) == 0
5603 && (temp = get_last_value (XEXP (x, 0)))
5604 && COMPARISON_P (temp))
5605 return gen_lowpart (mode, XEXP (x, 0));
5609 /* (const (const X)) can become (const X). Do it this way rather than
5610 returning the inner CONST since CONST can be shared with a
5612 if (GET_CODE (XEXP (x, 0)) == CONST)
5613 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
5618 /* Convert (lo_sum (high FOO) FOO) to FOO. This is necessary so we
5619 can add in an offset. find_split_point will split this address up
5620 again if it doesn't match. */
5621 if (GET_CODE (XEXP (x, 0)) == HIGH
5622 && rtx_equal_p (XEXP (XEXP (x, 0), 0), XEXP (x, 1)))
5628 /* (plus (xor (and <foo> (const_int pow2 - 1)) <c>) <-c>)
5629 when c is (const_int (pow2 + 1) / 2) is a sign extension of a
5630 bit-field and can be replaced by either a sign_extend or a
5631 sign_extract. The `and' may be a zero_extend and the two
5632 <c>, -<c> constants may be reversed. */
5633 if (GET_CODE (XEXP (x, 0)) == XOR
5634 && CONST_INT_P (XEXP (x, 1))
5635 && CONST_INT_P (XEXP (XEXP (x, 0), 1))
5636 && INTVAL (XEXP (x, 1)) == -INTVAL (XEXP (XEXP (x, 0), 1))
5637 && ((i = exact_log2 (UINTVAL (XEXP (XEXP (x, 0), 1)))) >= 0
5638 || (i = exact_log2 (UINTVAL (XEXP (x, 1)))) >= 0)
5639 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5640 && ((GET_CODE (XEXP (XEXP (x, 0), 0)) == AND
5641 && CONST_INT_P (XEXP (XEXP (XEXP (x, 0), 0), 1))
5642 && (UINTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1))
5643 == ((unsigned HOST_WIDE_INT) 1 << (i + 1)) - 1))
5644 || (GET_CODE (XEXP (XEXP (x, 0), 0)) == ZERO_EXTEND
5645 && (GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)))
5646 == (unsigned int) i + 1))))
5647 return simplify_shift_const
5648 (NULL_RTX, ASHIFTRT, mode,
5649 simplify_shift_const (NULL_RTX, ASHIFT, mode,
5650 XEXP (XEXP (XEXP (x, 0), 0), 0),
5651 GET_MODE_BITSIZE (mode) - (i + 1)),
5652 GET_MODE_BITSIZE (mode) - (i + 1));
5654 /* If only the low-order bit of X is possibly nonzero, (plus x -1)
5655 can become (ashiftrt (ashift (xor x 1) C) C) where C is
5656 the bitsize of the mode - 1. This allows simplification of
5657 "a = (b & 8) == 0;" */
5658 if (XEXP (x, 1) == constm1_rtx
5659 && !REG_P (XEXP (x, 0))
5660 && ! (GET_CODE (XEXP (x, 0)) == SUBREG
5661 && REG_P (SUBREG_REG (XEXP (x, 0))))
5662 && nonzero_bits (XEXP (x, 0), mode) == 1)
5663 return simplify_shift_const (NULL_RTX, ASHIFTRT, mode,
5664 simplify_shift_const (NULL_RTX, ASHIFT, mode,
5665 gen_rtx_XOR (mode, XEXP (x, 0), const1_rtx),
5666 GET_MODE_BITSIZE (mode) - 1),
5667 GET_MODE_BITSIZE (mode) - 1);
5669 /* If we are adding two things that have no bits in common, convert
5670 the addition into an IOR. This will often be further simplified,
5671 for example in cases like ((a & 1) + (a & 2)), which can
5674 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5675 && (nonzero_bits (XEXP (x, 0), mode)
5676 & nonzero_bits (XEXP (x, 1), mode)) == 0)
5678 /* Try to simplify the expression further. */
5679 rtx tor = simplify_gen_binary (IOR, mode, XEXP (x, 0), XEXP (x, 1));
5680 temp = combine_simplify_rtx (tor, VOIDmode, in_dest, 0);
5682 /* If we could, great. If not, do not go ahead with the IOR
5683 replacement, since PLUS appears in many special purpose
5684 address arithmetic instructions. */
5685 if (GET_CODE (temp) != CLOBBER
5686 && (GET_CODE (temp) != IOR
5687 || ((XEXP (temp, 0) != XEXP (x, 0)
5688 || XEXP (temp, 1) != XEXP (x, 1))
5689 && (XEXP (temp, 0) != XEXP (x, 1)
5690 || XEXP (temp, 1) != XEXP (x, 0)))))
5696 /* (minus <foo> (and <foo> (const_int -pow2))) becomes
5697 (and <foo> (const_int pow2-1)) */
5698 if (GET_CODE (XEXP (x, 1)) == AND
5699 && CONST_INT_P (XEXP (XEXP (x, 1), 1))
5700 && exact_log2 (-UINTVAL (XEXP (XEXP (x, 1), 1))) >= 0
5701 && rtx_equal_p (XEXP (XEXP (x, 1), 0), XEXP (x, 0)))
5702 return simplify_and_const_int (NULL_RTX, mode, XEXP (x, 0),
5703 -INTVAL (XEXP (XEXP (x, 1), 1)) - 1);
5707 /* If we have (mult (plus A B) C), apply the distributive law and then
5708 the inverse distributive law to see if things simplify. This
5709 occurs mostly in addresses, often when unrolling loops. */
5711 if (GET_CODE (XEXP (x, 0)) == PLUS)
5713 rtx result = distribute_and_simplify_rtx (x, 0);
5718 /* Try simplify a*(b/c) as (a*b)/c. */
5719 if (FLOAT_MODE_P (mode) && flag_associative_math
5720 && GET_CODE (XEXP (x, 0)) == DIV)
5722 rtx tem = simplify_binary_operation (MULT, mode,
5723 XEXP (XEXP (x, 0), 0),
5726 return simplify_gen_binary (DIV, mode, tem, XEXP (XEXP (x, 0), 1));
5731 /* If this is a divide by a power of two, treat it as a shift if
5732 its first operand is a shift. */
5733 if (CONST_INT_P (XEXP (x, 1))
5734 && (i = exact_log2 (UINTVAL (XEXP (x, 1)))) >= 0
5735 && (GET_CODE (XEXP (x, 0)) == ASHIFT
5736 || GET_CODE (XEXP (x, 0)) == LSHIFTRT
5737 || GET_CODE (XEXP (x, 0)) == ASHIFTRT
5738 || GET_CODE (XEXP (x, 0)) == ROTATE
5739 || GET_CODE (XEXP (x, 0)) == ROTATERT))
5740 return simplify_shift_const (NULL_RTX, LSHIFTRT, mode, XEXP (x, 0), i);
5744 case GT: case GTU: case GE: case GEU:
5745 case LT: case LTU: case LE: case LEU:
5746 case UNEQ: case LTGT:
5747 case UNGT: case UNGE:
5748 case UNLT: case UNLE:
5749 case UNORDERED: case ORDERED:
5750 /* If the first operand is a condition code, we can't do anything
5752 if (GET_CODE (XEXP (x, 0)) == COMPARE
5753 || (GET_MODE_CLASS (GET_MODE (XEXP (x, 0))) != MODE_CC
5754 && ! CC0_P (XEXP (x, 0))))
5756 rtx op0 = XEXP (x, 0);
5757 rtx op1 = XEXP (x, 1);
5758 enum rtx_code new_code;
5760 if (GET_CODE (op0) == COMPARE)
5761 op1 = XEXP (op0, 1), op0 = XEXP (op0, 0);
5763 /* Simplify our comparison, if possible. */
5764 new_code = simplify_comparison (code, &op0, &op1);
5766 /* If STORE_FLAG_VALUE is 1, we can convert (ne x 0) to simply X
5767 if only the low-order bit is possibly nonzero in X (such as when
5768 X is a ZERO_EXTRACT of one bit). Similarly, we can convert EQ to
5769 (xor X 1) or (minus 1 X); we use the former. Finally, if X is
5770 known to be either 0 or -1, NE becomes a NEG and EQ becomes
5773 Remove any ZERO_EXTRACT we made when thinking this was a
5774 comparison. It may now be simpler to use, e.g., an AND. If a
5775 ZERO_EXTRACT is indeed appropriate, it will be placed back by
5776 the call to make_compound_operation in the SET case.
5778 Don't apply these optimizations if the caller would
5779 prefer a comparison rather than a value.
5780 E.g., for the condition in an IF_THEN_ELSE most targets need
5781 an explicit comparison. */
5786 else if (STORE_FLAG_VALUE == 1
5787 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
5788 && op1 == const0_rtx
5789 && mode == GET_MODE (op0)
5790 && nonzero_bits (op0, mode) == 1)
5791 return gen_lowpart (mode,
5792 expand_compound_operation (op0));
5794 else if (STORE_FLAG_VALUE == 1
5795 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
5796 && op1 == const0_rtx
5797 && mode == GET_MODE (op0)
5798 && (num_sign_bit_copies (op0, mode)
5799 == GET_MODE_BITSIZE (mode)))
5801 op0 = expand_compound_operation (op0);
5802 return simplify_gen_unary (NEG, mode,
5803 gen_lowpart (mode, op0),
5807 else if (STORE_FLAG_VALUE == 1
5808 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
5809 && op1 == const0_rtx
5810 && mode == GET_MODE (op0)
5811 && nonzero_bits (op0, mode) == 1)
5813 op0 = expand_compound_operation (op0);
5814 return simplify_gen_binary (XOR, mode,
5815 gen_lowpart (mode, op0),
5819 else if (STORE_FLAG_VALUE == 1
5820 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
5821 && op1 == const0_rtx
5822 && mode == GET_MODE (op0)
5823 && (num_sign_bit_copies (op0, mode)
5824 == GET_MODE_BITSIZE (mode)))
5826 op0 = expand_compound_operation (op0);
5827 return plus_constant (gen_lowpart (mode, op0), 1);
5830 /* If STORE_FLAG_VALUE is -1, we have cases similar to
5835 else if (STORE_FLAG_VALUE == -1
5836 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
5837 && op1 == const0_rtx
5838 && (num_sign_bit_copies (op0, mode)
5839 == GET_MODE_BITSIZE (mode)))
5840 return gen_lowpart (mode,
5841 expand_compound_operation (op0));
5843 else if (STORE_FLAG_VALUE == -1
5844 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
5845 && op1 == const0_rtx
5846 && mode == GET_MODE (op0)
5847 && nonzero_bits (op0, mode) == 1)
5849 op0 = expand_compound_operation (op0);
5850 return simplify_gen_unary (NEG, mode,
5851 gen_lowpart (mode, op0),
5855 else if (STORE_FLAG_VALUE == -1
5856 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
5857 && op1 == const0_rtx
5858 && mode == GET_MODE (op0)
5859 && (num_sign_bit_copies (op0, mode)
5860 == GET_MODE_BITSIZE (mode)))
5862 op0 = expand_compound_operation (op0);
5863 return simplify_gen_unary (NOT, mode,
5864 gen_lowpart (mode, op0),
5868 /* If X is 0/1, (eq X 0) is X-1. */
5869 else if (STORE_FLAG_VALUE == -1
5870 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
5871 && op1 == const0_rtx
5872 && mode == GET_MODE (op0)
5873 && nonzero_bits (op0, mode) == 1)
5875 op0 = expand_compound_operation (op0);
5876 return plus_constant (gen_lowpart (mode, op0), -1);
5879 /* If STORE_FLAG_VALUE says to just test the sign bit and X has just
5880 one bit that might be nonzero, we can convert (ne x 0) to
5881 (ashift x c) where C puts the bit in the sign bit. Remove any
5882 AND with STORE_FLAG_VALUE when we are done, since we are only
5883 going to test the sign bit. */
5884 if (new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
5885 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5886 && val_signbit_p (mode, STORE_FLAG_VALUE)
5887 && op1 == const0_rtx
5888 && mode == GET_MODE (op0)
5889 && (i = exact_log2 (nonzero_bits (op0, mode))) >= 0)
5891 x = simplify_shift_const (NULL_RTX, ASHIFT, mode,
5892 expand_compound_operation (op0),
5893 GET_MODE_BITSIZE (mode) - 1 - i);
5894 if (GET_CODE (x) == AND && XEXP (x, 1) == const_true_rtx)
5900 /* If the code changed, return a whole new comparison. */
5901 if (new_code != code)
5902 return gen_rtx_fmt_ee (new_code, mode, op0, op1);
5904 /* Otherwise, keep this operation, but maybe change its operands.
5905 This also converts (ne (compare FOO BAR) 0) to (ne FOO BAR). */
5906 SUBST (XEXP (x, 0), op0);
5907 SUBST (XEXP (x, 1), op1);
5912 return simplify_if_then_else (x);
5918 /* If we are processing SET_DEST, we are done. */
5922 return expand_compound_operation (x);
5925 return simplify_set (x);
5929 return simplify_logical (x);
5936 /* If this is a shift by a constant amount, simplify it. */
5937 if (CONST_INT_P (XEXP (x, 1)))
5938 return simplify_shift_const (x, code, mode, XEXP (x, 0),
5939 INTVAL (XEXP (x, 1)));
5941 else if (SHIFT_COUNT_TRUNCATED && !REG_P (XEXP (x, 1)))
5943 force_to_mode (XEXP (x, 1), GET_MODE (XEXP (x, 1)),
5944 targetm.shift_truncation_mask (GET_MODE (x)),
5955 /* Simplify X, an IF_THEN_ELSE expression. Return the new expression. */
5958 simplify_if_then_else (rtx x)
5960 enum machine_mode mode = GET_MODE (x);
5961 rtx cond = XEXP (x, 0);
5962 rtx true_rtx = XEXP (x, 1);
5963 rtx false_rtx = XEXP (x, 2);
5964 enum rtx_code true_code = GET_CODE (cond);
5965 int comparison_p = COMPARISON_P (cond);
5968 enum rtx_code false_code;
5971 /* Simplify storing of the truth value. */
5972 if (comparison_p && true_rtx == const_true_rtx && false_rtx == const0_rtx)
5973 return simplify_gen_relational (true_code, mode, VOIDmode,
5974 XEXP (cond, 0), XEXP (cond, 1));
5976 /* Also when the truth value has to be reversed. */
5978 && true_rtx == const0_rtx && false_rtx == const_true_rtx
5979 && (reversed = reversed_comparison (cond, mode)))
5982 /* Sometimes we can simplify the arm of an IF_THEN_ELSE if a register used
5983 in it is being compared against certain values. Get the true and false
5984 comparisons and see if that says anything about the value of each arm. */
5987 && ((false_code = reversed_comparison_code (cond, NULL))
5989 && REG_P (XEXP (cond, 0)))
5992 rtx from = XEXP (cond, 0);
5993 rtx true_val = XEXP (cond, 1);
5994 rtx false_val = true_val;
5997 /* If FALSE_CODE is EQ, swap the codes and arms. */
5999 if (false_code == EQ)
6001 swapped = 1, true_code = EQ, false_code = NE;
6002 temp = true_rtx, true_rtx = false_rtx, false_rtx = temp;
6005 /* If we are comparing against zero and the expression being tested has
6006 only a single bit that might be nonzero, that is its value when it is
6007 not equal to zero. Similarly if it is known to be -1 or 0. */
6009 if (true_code == EQ && true_val == const0_rtx
6010 && exact_log2 (nzb = nonzero_bits (from, GET_MODE (from))) >= 0)
6013 false_val = GEN_INT (trunc_int_for_mode (nzb, GET_MODE (from)));
6015 else if (true_code == EQ && true_val == const0_rtx
6016 && (num_sign_bit_copies (from, GET_MODE (from))
6017 == GET_MODE_BITSIZE (GET_MODE (from))))
6020 false_val = constm1_rtx;
6023 /* Now simplify an arm if we know the value of the register in the
6024 branch and it is used in the arm. Be careful due to the potential
6025 of locally-shared RTL. */
6027 if (reg_mentioned_p (from, true_rtx))
6028 true_rtx = subst (known_cond (copy_rtx (true_rtx), true_code,
6030 pc_rtx, pc_rtx, 0, 0, 0);
6031 if (reg_mentioned_p (from, false_rtx))
6032 false_rtx = subst (known_cond (copy_rtx (false_rtx), false_code,
6034 pc_rtx, pc_rtx, 0, 0, 0);
6036 SUBST (XEXP (x, 1), swapped ? false_rtx : true_rtx);
6037 SUBST (XEXP (x, 2), swapped ? true_rtx : false_rtx);
6039 true_rtx = XEXP (x, 1);
6040 false_rtx = XEXP (x, 2);
6041 true_code = GET_CODE (cond);
6044 /* If we have (if_then_else FOO (pc) (label_ref BAR)) and FOO can be
6045 reversed, do so to avoid needing two sets of patterns for
6046 subtract-and-branch insns. Similarly if we have a constant in the true
6047 arm, the false arm is the same as the first operand of the comparison, or
6048 the false arm is more complicated than the true arm. */
6051 && reversed_comparison_code (cond, NULL) != UNKNOWN
6052 && (true_rtx == pc_rtx
6053 || (CONSTANT_P (true_rtx)
6054 && !CONST_INT_P (false_rtx) && false_rtx != pc_rtx)
6055 || true_rtx == const0_rtx
6056 || (OBJECT_P (true_rtx) && !OBJECT_P (false_rtx))
6057 || (GET_CODE (true_rtx) == SUBREG && OBJECT_P (SUBREG_REG (true_rtx))
6058 && !OBJECT_P (false_rtx))
6059 || reg_mentioned_p (true_rtx, false_rtx)
6060 || rtx_equal_p (false_rtx, XEXP (cond, 0))))
6062 true_code = reversed_comparison_code (cond, NULL);
6063 SUBST (XEXP (x, 0), reversed_comparison (cond, GET_MODE (cond)));
6064 SUBST (XEXP (x, 1), false_rtx);
6065 SUBST (XEXP (x, 2), true_rtx);
6067 temp = true_rtx, true_rtx = false_rtx, false_rtx = temp;
6070 /* It is possible that the conditional has been simplified out. */
6071 true_code = GET_CODE (cond);
6072 comparison_p = COMPARISON_P (cond);
6075 /* If the two arms are identical, we don't need the comparison. */
6077 if (rtx_equal_p (true_rtx, false_rtx) && ! side_effects_p (cond))
6080 /* Convert a == b ? b : a to "a". */
6081 if (true_code == EQ && ! side_effects_p (cond)
6082 && !HONOR_NANS (mode)
6083 && rtx_equal_p (XEXP (cond, 0), false_rtx)
6084 && rtx_equal_p (XEXP (cond, 1), true_rtx))
6086 else if (true_code == NE && ! side_effects_p (cond)
6087 && !HONOR_NANS (mode)
6088 && rtx_equal_p (XEXP (cond, 0), true_rtx)
6089 && rtx_equal_p (XEXP (cond, 1), false_rtx))
6092 /* Look for cases where we have (abs x) or (neg (abs X)). */
6094 if (GET_MODE_CLASS (mode) == MODE_INT
6096 && XEXP (cond, 1) == const0_rtx
6097 && GET_CODE (false_rtx) == NEG
6098 && rtx_equal_p (true_rtx, XEXP (false_rtx, 0))
6099 && rtx_equal_p (true_rtx, XEXP (cond, 0))
6100 && ! side_effects_p (true_rtx))
6105 return simplify_gen_unary (ABS, mode, true_rtx, mode);
6109 simplify_gen_unary (NEG, mode,
6110 simplify_gen_unary (ABS, mode, true_rtx, mode),
6116 /* Look for MIN or MAX. */
6118 if ((! FLOAT_MODE_P (mode) || flag_unsafe_math_optimizations)
6120 && rtx_equal_p (XEXP (cond, 0), true_rtx)
6121 && rtx_equal_p (XEXP (cond, 1), false_rtx)
6122 && ! side_effects_p (cond))
6127 return simplify_gen_binary (SMAX, mode, true_rtx, false_rtx);
6130 return simplify_gen_binary (SMIN, mode, true_rtx, false_rtx);
6133 return simplify_gen_binary (UMAX, mode, true_rtx, false_rtx);
6136 return simplify_gen_binary (UMIN, mode, true_rtx, false_rtx);
6141 /* If we have (if_then_else COND (OP Z C1) Z) and OP is an identity when its
6142 second operand is zero, this can be done as (OP Z (mult COND C2)) where
6143 C2 = C1 * STORE_FLAG_VALUE. Similarly if OP has an outer ZERO_EXTEND or
6144 SIGN_EXTEND as long as Z is already extended (so we don't destroy it).
6145 We can do this kind of thing in some cases when STORE_FLAG_VALUE is
6146 neither 1 or -1, but it isn't worth checking for. */
6148 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
6150 && GET_MODE_CLASS (mode) == MODE_INT
6151 && ! side_effects_p (x))
6153 rtx t = make_compound_operation (true_rtx, SET);
6154 rtx f = make_compound_operation (false_rtx, SET);
6155 rtx cond_op0 = XEXP (cond, 0);
6156 rtx cond_op1 = XEXP (cond, 1);
6157 enum rtx_code op = UNKNOWN, extend_op = UNKNOWN;
6158 enum machine_mode m = mode;
6159 rtx z = 0, c1 = NULL_RTX;
6161 if ((GET_CODE (t) == PLUS || GET_CODE (t) == MINUS
6162 || GET_CODE (t) == IOR || GET_CODE (t) == XOR
6163 || GET_CODE (t) == ASHIFT
6164 || GET_CODE (t) == LSHIFTRT || GET_CODE (t) == ASHIFTRT)
6165 && rtx_equal_p (XEXP (t, 0), f))
6166 c1 = XEXP (t, 1), op = GET_CODE (t), z = f;
6168 /* If an identity-zero op is commutative, check whether there
6169 would be a match if we swapped the operands. */
6170 else if ((GET_CODE (t) == PLUS || GET_CODE (t) == IOR
6171 || GET_CODE (t) == XOR)
6172 && rtx_equal_p (XEXP (t, 1), f))
6173 c1 = XEXP (t, 0), op = GET_CODE (t), z = f;
6174 else if (GET_CODE (t) == SIGN_EXTEND
6175 && (GET_CODE (XEXP (t, 0)) == PLUS
6176 || GET_CODE (XEXP (t, 0)) == MINUS
6177 || GET_CODE (XEXP (t, 0)) == IOR
6178 || GET_CODE (XEXP (t, 0)) == XOR
6179 || GET_CODE (XEXP (t, 0)) == ASHIFT
6180 || GET_CODE (XEXP (t, 0)) == LSHIFTRT
6181 || GET_CODE (XEXP (t, 0)) == ASHIFTRT)
6182 && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG
6183 && subreg_lowpart_p (XEXP (XEXP (t, 0), 0))
6184 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f)
6185 && (num_sign_bit_copies (f, GET_MODE (f))
6187 (GET_MODE_BITSIZE (mode)
6188 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t, 0), 0))))))
6190 c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0));
6191 extend_op = SIGN_EXTEND;
6192 m = GET_MODE (XEXP (t, 0));
6194 else if (GET_CODE (t) == SIGN_EXTEND
6195 && (GET_CODE (XEXP (t, 0)) == PLUS
6196 || GET_CODE (XEXP (t, 0)) == IOR
6197 || GET_CODE (XEXP (t, 0)) == XOR)
6198 && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG
6199 && subreg_lowpart_p (XEXP (XEXP (t, 0), 1))
6200 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f)
6201 && (num_sign_bit_copies (f, GET_MODE (f))
6203 (GET_MODE_BITSIZE (mode)
6204 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t, 0), 1))))))
6206 c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0));
6207 extend_op = SIGN_EXTEND;
6208 m = GET_MODE (XEXP (t, 0));
6210 else if (GET_CODE (t) == ZERO_EXTEND
6211 && (GET_CODE (XEXP (t, 0)) == PLUS
6212 || GET_CODE (XEXP (t, 0)) == MINUS
6213 || GET_CODE (XEXP (t, 0)) == IOR
6214 || GET_CODE (XEXP (t, 0)) == XOR
6215 || GET_CODE (XEXP (t, 0)) == ASHIFT
6216 || GET_CODE (XEXP (t, 0)) == LSHIFTRT
6217 || GET_CODE (XEXP (t, 0)) == ASHIFTRT)
6218 && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG
6219 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
6220 && subreg_lowpart_p (XEXP (XEXP (t, 0), 0))
6221 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f)
6222 && ((nonzero_bits (f, GET_MODE (f))
6223 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t, 0), 0))))
6226 c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0));
6227 extend_op = ZERO_EXTEND;
6228 m = GET_MODE (XEXP (t, 0));
6230 else if (GET_CODE (t) == ZERO_EXTEND
6231 && (GET_CODE (XEXP (t, 0)) == PLUS
6232 || GET_CODE (XEXP (t, 0)) == IOR
6233 || GET_CODE (XEXP (t, 0)) == XOR)
6234 && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG
6235 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
6236 && subreg_lowpart_p (XEXP (XEXP (t, 0), 1))
6237 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f)
6238 && ((nonzero_bits (f, GET_MODE (f))
6239 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t, 0), 1))))
6242 c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0));
6243 extend_op = ZERO_EXTEND;
6244 m = GET_MODE (XEXP (t, 0));
6249 temp = subst (simplify_gen_relational (true_code, m, VOIDmode,
6250 cond_op0, cond_op1),
6251 pc_rtx, pc_rtx, 0, 0, 0);
6252 temp = simplify_gen_binary (MULT, m, temp,
6253 simplify_gen_binary (MULT, m, c1,
6255 temp = subst (temp, pc_rtx, pc_rtx, 0, 0, 0);
6256 temp = simplify_gen_binary (op, m, gen_lowpart (m, z), temp);
6258 if (extend_op != UNKNOWN)
6259 temp = simplify_gen_unary (extend_op, mode, temp, m);
6265 /* If we have (if_then_else (ne A 0) C1 0) and either A is known to be 0 or
6266 1 and C1 is a single bit or A is known to be 0 or -1 and C1 is the
6267 negation of a single bit, we can convert this operation to a shift. We
6268 can actually do this more generally, but it doesn't seem worth it. */
6270 if (true_code == NE && XEXP (cond, 1) == const0_rtx
6271 && false_rtx == const0_rtx && CONST_INT_P (true_rtx)
6272 && ((1 == nonzero_bits (XEXP (cond, 0), mode)
6273 && (i = exact_log2 (UINTVAL (true_rtx))) >= 0)
6274 || ((num_sign_bit_copies (XEXP (cond, 0), mode)
6275 == GET_MODE_BITSIZE (mode))
6276 && (i = exact_log2 (-UINTVAL (true_rtx))) >= 0)))
6278 simplify_shift_const (NULL_RTX, ASHIFT, mode,
6279 gen_lowpart (mode, XEXP (cond, 0)), i);
6281 /* (IF_THEN_ELSE (NE REG 0) (0) (8)) is REG for nonzero_bits (REG) == 8. */
6282 if (true_code == NE && XEXP (cond, 1) == const0_rtx
6283 && false_rtx == const0_rtx && CONST_INT_P (true_rtx)
6284 && GET_MODE (XEXP (cond, 0)) == mode
6285 && (UINTVAL (true_rtx) & GET_MODE_MASK (mode))
6286 == nonzero_bits (XEXP (cond, 0), mode)
6287 && (i = exact_log2 (UINTVAL (true_rtx) & GET_MODE_MASK (mode))) >= 0)
6288 return XEXP (cond, 0);
6293 /* Simplify X, a SET expression. Return the new expression. */
6296 simplify_set (rtx x)
6298 rtx src = SET_SRC (x);
6299 rtx dest = SET_DEST (x);
6300 enum machine_mode mode
6301 = GET_MODE (src) != VOIDmode ? GET_MODE (src) : GET_MODE (dest);
6305 /* (set (pc) (return)) gets written as (return). */
6306 if (GET_CODE (dest) == PC && GET_CODE (src) == RETURN)
6309 /* Now that we know for sure which bits of SRC we are using, see if we can
6310 simplify the expression for the object knowing that we only need the
6313 if (GET_MODE_CLASS (mode) == MODE_INT
6314 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
6316 src = force_to_mode (src, mode, ~(unsigned HOST_WIDE_INT) 0, 0);
6317 SUBST (SET_SRC (x), src);
6320 /* If we are setting CC0 or if the source is a COMPARE, look for the use of
6321 the comparison result and try to simplify it unless we already have used
6322 undobuf.other_insn. */
6323 if ((GET_MODE_CLASS (mode) == MODE_CC
6324 || GET_CODE (src) == COMPARE
6326 && (cc_use = find_single_use (dest, subst_insn, &other_insn)) != 0
6327 && (undobuf.other_insn == 0 || other_insn == undobuf.other_insn)
6328 && COMPARISON_P (*cc_use)
6329 && rtx_equal_p (XEXP (*cc_use, 0), dest))
6331 enum rtx_code old_code = GET_CODE (*cc_use);
6332 enum rtx_code new_code;
6334 int other_changed = 0;
6335 rtx inner_compare = NULL_RTX;
6336 enum machine_mode compare_mode = GET_MODE (dest);
6338 if (GET_CODE (src) == COMPARE)
6340 op0 = XEXP (src, 0), op1 = XEXP (src, 1);
6341 if (GET_CODE (op0) == COMPARE && op1 == const0_rtx)
6343 inner_compare = op0;
6344 op0 = XEXP (inner_compare, 0), op1 = XEXP (inner_compare, 1);
6348 op0 = src, op1 = CONST0_RTX (GET_MODE (src));
6350 tmp = simplify_relational_operation (old_code, compare_mode, VOIDmode,
6353 new_code = old_code;
6354 else if (!CONSTANT_P (tmp))
6356 new_code = GET_CODE (tmp);
6357 op0 = XEXP (tmp, 0);
6358 op1 = XEXP (tmp, 1);
6362 rtx pat = PATTERN (other_insn);
6363 undobuf.other_insn = other_insn;
6364 SUBST (*cc_use, tmp);
6366 /* Attempt to simplify CC user. */
6367 if (GET_CODE (pat) == SET)
6369 rtx new_rtx = simplify_rtx (SET_SRC (pat));
6370 if (new_rtx != NULL_RTX)
6371 SUBST (SET_SRC (pat), new_rtx);
6374 /* Convert X into a no-op move. */
6375 SUBST (SET_DEST (x), pc_rtx);
6376 SUBST (SET_SRC (x), pc_rtx);
6380 /* Simplify our comparison, if possible. */
6381 new_code = simplify_comparison (new_code, &op0, &op1);
6383 #ifdef SELECT_CC_MODE
6384 /* If this machine has CC modes other than CCmode, check to see if we
6385 need to use a different CC mode here. */
6386 if (GET_MODE_CLASS (GET_MODE (op0)) == MODE_CC)
6387 compare_mode = GET_MODE (op0);
6388 else if (inner_compare
6389 && GET_MODE_CLASS (GET_MODE (inner_compare)) == MODE_CC
6390 && new_code == old_code
6391 && op0 == XEXP (inner_compare, 0)
6392 && op1 == XEXP (inner_compare, 1))
6393 compare_mode = GET_MODE (inner_compare);
6395 compare_mode = SELECT_CC_MODE (new_code, op0, op1);
6398 /* If the mode changed, we have to change SET_DEST, the mode in the
6399 compare, and the mode in the place SET_DEST is used. If SET_DEST is
6400 a hard register, just build new versions with the proper mode. If it
6401 is a pseudo, we lose unless it is only time we set the pseudo, in
6402 which case we can safely change its mode. */
6403 if (compare_mode != GET_MODE (dest))
6405 if (can_change_dest_mode (dest, 0, compare_mode))
6407 unsigned int regno = REGNO (dest);
6410 if (regno < FIRST_PSEUDO_REGISTER)
6411 new_dest = gen_rtx_REG (compare_mode, regno);
6414 SUBST_MODE (regno_reg_rtx[regno], compare_mode);
6415 new_dest = regno_reg_rtx[regno];
6418 SUBST (SET_DEST (x), new_dest);
6419 SUBST (XEXP (*cc_use, 0), new_dest);
6426 #endif /* SELECT_CC_MODE */
6428 /* If the code changed, we have to build a new comparison in
6429 undobuf.other_insn. */
6430 if (new_code != old_code)
6432 int other_changed_previously = other_changed;
6433 unsigned HOST_WIDE_INT mask;
6434 rtx old_cc_use = *cc_use;
6436 SUBST (*cc_use, gen_rtx_fmt_ee (new_code, GET_MODE (*cc_use),
6440 /* If the only change we made was to change an EQ into an NE or
6441 vice versa, OP0 has only one bit that might be nonzero, and OP1
6442 is zero, check if changing the user of the condition code will
6443 produce a valid insn. If it won't, we can keep the original code
6444 in that insn by surrounding our operation with an XOR. */
6446 if (((old_code == NE && new_code == EQ)
6447 || (old_code == EQ && new_code == NE))
6448 && ! other_changed_previously && op1 == const0_rtx
6449 && GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
6450 && exact_log2 (mask = nonzero_bits (op0, GET_MODE (op0))) >= 0)
6452 rtx pat = PATTERN (other_insn), note = 0;
6454 if ((recog_for_combine (&pat, other_insn, ¬e) < 0
6455 && ! check_asm_operands (pat)))
6457 *cc_use = old_cc_use;
6460 op0 = simplify_gen_binary (XOR, GET_MODE (op0),
6461 op0, GEN_INT (mask));
6467 undobuf.other_insn = other_insn;
6469 /* Otherwise, if we didn't previously have a COMPARE in the
6470 correct mode, we need one. */
6471 if (GET_CODE (src) != COMPARE || GET_MODE (src) != compare_mode)
6473 SUBST (SET_SRC (x), gen_rtx_COMPARE (compare_mode, op0, op1));
6476 else if (GET_MODE (op0) == compare_mode && op1 == const0_rtx)
6478 SUBST (SET_SRC (x), op0);
6481 /* Otherwise, update the COMPARE if needed. */
6482 else if (XEXP (src, 0) != op0 || XEXP (src, 1) != op1)
6484 SUBST (SET_SRC (x), gen_rtx_COMPARE (compare_mode, op0, op1));
6490 /* Get SET_SRC in a form where we have placed back any
6491 compound expressions. Then do the checks below. */
6492 src = make_compound_operation (src, SET);
6493 SUBST (SET_SRC (x), src);
6496 /* If we have (set x (subreg:m1 (op:m2 ...) 0)) with OP being some operation,
6497 and X being a REG or (subreg (reg)), we may be able to convert this to
6498 (set (subreg:m2 x) (op)).
6500 We can always do this if M1 is narrower than M2 because that means that
6501 we only care about the low bits of the result.
6503 However, on machines without WORD_REGISTER_OPERATIONS defined, we cannot
6504 perform a narrower operation than requested since the high-order bits will
6505 be undefined. On machine where it is defined, this transformation is safe
6506 as long as M1 and M2 have the same number of words. */
6508 if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src)
6509 && !OBJECT_P (SUBREG_REG (src))
6510 && (((GET_MODE_SIZE (GET_MODE (src)) + (UNITS_PER_WORD - 1))
6512 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (src)))
6513 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD))
6514 #ifndef WORD_REGISTER_OPERATIONS
6515 && (GET_MODE_SIZE (GET_MODE (src))
6516 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (src))))
6518 #ifdef CANNOT_CHANGE_MODE_CLASS
6519 && ! (REG_P (dest) && REGNO (dest) < FIRST_PSEUDO_REGISTER
6520 && REG_CANNOT_CHANGE_MODE_P (REGNO (dest),
6521 GET_MODE (SUBREG_REG (src)),
6525 || (GET_CODE (dest) == SUBREG
6526 && REG_P (SUBREG_REG (dest)))))
6528 SUBST (SET_DEST (x),
6529 gen_lowpart (GET_MODE (SUBREG_REG (src)),
6531 SUBST (SET_SRC (x), SUBREG_REG (src));
6533 src = SET_SRC (x), dest = SET_DEST (x);
6537 /* If we have (set (cc0) (subreg ...)), we try to remove the subreg
6540 && GET_CODE (src) == SUBREG
6541 && subreg_lowpart_p (src)
6542 && (GET_MODE_BITSIZE (GET_MODE (src))
6543 < GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (src)))))
6545 rtx inner = SUBREG_REG (src);
6546 enum machine_mode inner_mode = GET_MODE (inner);
6548 /* Here we make sure that we don't have a sign bit on. */
6549 if (val_signbit_known_clear_p (GET_MODE (src),
6550 nonzero_bits (inner, inner_mode)))
6552 SUBST (SET_SRC (x), inner);
6558 #ifdef LOAD_EXTEND_OP
6559 /* If we have (set FOO (subreg:M (mem:N BAR) 0)) with M wider than N, this
6560 would require a paradoxical subreg. Replace the subreg with a
6561 zero_extend to avoid the reload that would otherwise be required. */
6563 if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src)
6564 && INTEGRAL_MODE_P (GET_MODE (SUBREG_REG (src)))
6565 && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src))) != UNKNOWN
6566 && SUBREG_BYTE (src) == 0
6567 && (GET_MODE_SIZE (GET_MODE (src))
6568 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (src))))
6569 && MEM_P (SUBREG_REG (src)))
6572 gen_rtx_fmt_e (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src))),
6573 GET_MODE (src), SUBREG_REG (src)));
6579 /* If we don't have a conditional move, SET_SRC is an IF_THEN_ELSE, and we
6580 are comparing an item known to be 0 or -1 against 0, use a logical
6581 operation instead. Check for one of the arms being an IOR of the other
6582 arm with some value. We compute three terms to be IOR'ed together. In
6583 practice, at most two will be nonzero. Then we do the IOR's. */
6585 if (GET_CODE (dest) != PC
6586 && GET_CODE (src) == IF_THEN_ELSE
6587 && GET_MODE_CLASS (GET_MODE (src)) == MODE_INT
6588 && (GET_CODE (XEXP (src, 0)) == EQ || GET_CODE (XEXP (src, 0)) == NE)
6589 && XEXP (XEXP (src, 0), 1) == const0_rtx
6590 && GET_MODE (src) == GET_MODE (XEXP (XEXP (src, 0), 0))
6591 #ifdef HAVE_conditional_move
6592 && ! can_conditionally_move_p (GET_MODE (src))
6594 && (num_sign_bit_copies (XEXP (XEXP (src, 0), 0),
6595 GET_MODE (XEXP (XEXP (src, 0), 0)))
6596 == GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (src, 0), 0))))
6597 && ! side_effects_p (src))
6599 rtx true_rtx = (GET_CODE (XEXP (src, 0)) == NE
6600 ? XEXP (src, 1) : XEXP (src, 2));
6601 rtx false_rtx = (GET_CODE (XEXP (src, 0)) == NE
6602 ? XEXP (src, 2) : XEXP (src, 1));
6603 rtx term1 = const0_rtx, term2, term3;
6605 if (GET_CODE (true_rtx) == IOR
6606 && rtx_equal_p (XEXP (true_rtx, 0), false_rtx))
6607 term1 = false_rtx, true_rtx = XEXP (true_rtx, 1), false_rtx = const0_rtx;
6608 else if (GET_CODE (true_rtx) == IOR
6609 && rtx_equal_p (XEXP (true_rtx, 1), false_rtx))
6610 term1 = false_rtx, true_rtx = XEXP (true_rtx, 0), false_rtx = const0_rtx;
6611 else if (GET_CODE (false_rtx) == IOR
6612 && rtx_equal_p (XEXP (false_rtx, 0), true_rtx))
6613 term1 = true_rtx, false_rtx = XEXP (false_rtx, 1), true_rtx = const0_rtx;
6614 else if (GET_CODE (false_rtx) == IOR
6615 && rtx_equal_p (XEXP (false_rtx, 1), true_rtx))
6616 term1 = true_rtx, false_rtx = XEXP (false_rtx, 0), true_rtx = const0_rtx;
6618 term2 = simplify_gen_binary (AND, GET_MODE (src),
6619 XEXP (XEXP (src, 0), 0), true_rtx);
6620 term3 = simplify_gen_binary (AND, GET_MODE (src),
6621 simplify_gen_unary (NOT, GET_MODE (src),
6622 XEXP (XEXP (src, 0), 0),
6627 simplify_gen_binary (IOR, GET_MODE (src),
6628 simplify_gen_binary (IOR, GET_MODE (src),
6635 /* If either SRC or DEST is a CLOBBER of (const_int 0), make this
6636 whole thing fail. */
6637 if (GET_CODE (src) == CLOBBER && XEXP (src, 0) == const0_rtx)
6639 else if (GET_CODE (dest) == CLOBBER && XEXP (dest, 0) == const0_rtx)
6642 /* Convert this into a field assignment operation, if possible. */
6643 return make_field_assignment (x);
6646 /* Simplify, X, and AND, IOR, or XOR operation, and return the simplified
6650 simplify_logical (rtx x)
6652 enum machine_mode mode = GET_MODE (x);
6653 rtx op0 = XEXP (x, 0);
6654 rtx op1 = XEXP (x, 1);
6656 switch (GET_CODE (x))
6659 /* We can call simplify_and_const_int only if we don't lose
6660 any (sign) bits when converting INTVAL (op1) to
6661 "unsigned HOST_WIDE_INT". */
6662 if (CONST_INT_P (op1)
6663 && (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
6664 || INTVAL (op1) > 0))
6666 x = simplify_and_const_int (x, mode, op0, INTVAL (op1));
6667 if (GET_CODE (x) != AND)
6674 /* If we have any of (and (ior A B) C) or (and (xor A B) C),
6675 apply the distributive law and then the inverse distributive
6676 law to see if things simplify. */
6677 if (GET_CODE (op0) == IOR || GET_CODE (op0) == XOR)
6679 rtx result = distribute_and_simplify_rtx (x, 0);
6683 if (GET_CODE (op1) == IOR || GET_CODE (op1) == XOR)
6685 rtx result = distribute_and_simplify_rtx (x, 1);
6692 /* If we have (ior (and A B) C), apply the distributive law and then
6693 the inverse distributive law to see if things simplify. */
6695 if (GET_CODE (op0) == AND)
6697 rtx result = distribute_and_simplify_rtx (x, 0);
6702 if (GET_CODE (op1) == AND)
6704 rtx result = distribute_and_simplify_rtx (x, 1);
6717 /* We consider ZERO_EXTRACT, SIGN_EXTRACT, and SIGN_EXTEND as "compound
6718 operations" because they can be replaced with two more basic operations.
6719 ZERO_EXTEND is also considered "compound" because it can be replaced with
6720 an AND operation, which is simpler, though only one operation.
6722 The function expand_compound_operation is called with an rtx expression
6723 and will convert it to the appropriate shifts and AND operations,
6724 simplifying at each stage.
6726 The function make_compound_operation is called to convert an expression
6727 consisting of shifts and ANDs into the equivalent compound expression.
6728 It is the inverse of this function, loosely speaking. */
6731 expand_compound_operation (rtx x)
6733 unsigned HOST_WIDE_INT pos = 0, len;
6735 unsigned int modewidth;
6738 switch (GET_CODE (x))
6743 /* We can't necessarily use a const_int for a multiword mode;
6744 it depends on implicitly extending the value.
6745 Since we don't know the right way to extend it,
6746 we can't tell whether the implicit way is right.
6748 Even for a mode that is no wider than a const_int,
6749 we can't win, because we need to sign extend one of its bits through
6750 the rest of it, and we don't know which bit. */
6751 if (CONST_INT_P (XEXP (x, 0)))
6754 /* Return if (subreg:MODE FROM 0) is not a safe replacement for
6755 (zero_extend:MODE FROM) or (sign_extend:MODE FROM). It is for any MEM
6756 because (SUBREG (MEM...)) is guaranteed to cause the MEM to be
6757 reloaded. If not for that, MEM's would very rarely be safe.
6759 Reject MODEs bigger than a word, because we might not be able
6760 to reference a two-register group starting with an arbitrary register
6761 (and currently gen_lowpart might crash for a SUBREG). */
6763 if (GET_MODE_SIZE (GET_MODE (XEXP (x, 0))) > UNITS_PER_WORD)
6766 /* Reject MODEs that aren't scalar integers because turning vector
6767 or complex modes into shifts causes problems. */
6769 if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x, 0))))
6772 len = GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)));
6773 /* If the inner object has VOIDmode (the only way this can happen
6774 is if it is an ASM_OPERANDS), we can't do anything since we don't
6775 know how much masking to do. */
6784 /* ... fall through ... */
6787 /* If the operand is a CLOBBER, just return it. */
6788 if (GET_CODE (XEXP (x, 0)) == CLOBBER)
6791 if (!CONST_INT_P (XEXP (x, 1))
6792 || !CONST_INT_P (XEXP (x, 2))
6793 || GET_MODE (XEXP (x, 0)) == VOIDmode)
6796 /* Reject MODEs that aren't scalar integers because turning vector
6797 or complex modes into shifts causes problems. */
6799 if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x, 0))))
6802 len = INTVAL (XEXP (x, 1));
6803 pos = INTVAL (XEXP (x, 2));
6805 /* This should stay within the object being extracted, fail otherwise. */
6806 if (len + pos > GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))))
6809 if (BITS_BIG_ENDIAN)
6810 pos = GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - len - pos;
6817 /* Convert sign extension to zero extension, if we know that the high
6818 bit is not set, as this is easier to optimize. It will be converted
6819 back to cheaper alternative in make_extraction. */
6820 if (GET_CODE (x) == SIGN_EXTEND
6821 && (GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
6822 && ((nonzero_bits (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
6823 & ~(((unsigned HOST_WIDE_INT)
6824 GET_MODE_MASK (GET_MODE (XEXP (x, 0))))
6828 rtx temp = gen_rtx_ZERO_EXTEND (GET_MODE (x), XEXP (x, 0));
6829 rtx temp2 = expand_compound_operation (temp);
6831 /* Make sure this is a profitable operation. */
6832 if (rtx_cost (x, SET, optimize_this_for_speed_p)
6833 > rtx_cost (temp2, SET, optimize_this_for_speed_p))
6835 else if (rtx_cost (x, SET, optimize_this_for_speed_p)
6836 > rtx_cost (temp, SET, optimize_this_for_speed_p))
6842 /* We can optimize some special cases of ZERO_EXTEND. */
6843 if (GET_CODE (x) == ZERO_EXTEND)
6845 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI if we
6846 know that the last value didn't have any inappropriate bits
6848 if (GET_CODE (XEXP (x, 0)) == TRUNCATE
6849 && GET_MODE (XEXP (XEXP (x, 0), 0)) == GET_MODE (x)
6850 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
6851 && (nonzero_bits (XEXP (XEXP (x, 0), 0), GET_MODE (x))
6852 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
6853 return XEXP (XEXP (x, 0), 0);
6855 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
6856 if (GET_CODE (XEXP (x, 0)) == SUBREG
6857 && GET_MODE (SUBREG_REG (XEXP (x, 0))) == GET_MODE (x)
6858 && subreg_lowpart_p (XEXP (x, 0))
6859 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
6860 && (nonzero_bits (SUBREG_REG (XEXP (x, 0)), GET_MODE (x))
6861 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
6862 return SUBREG_REG (XEXP (x, 0));
6864 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI when foo
6865 is a comparison and STORE_FLAG_VALUE permits. This is like
6866 the first case, but it works even when GET_MODE (x) is larger
6867 than HOST_WIDE_INT. */
6868 if (GET_CODE (XEXP (x, 0)) == TRUNCATE
6869 && GET_MODE (XEXP (XEXP (x, 0), 0)) == GET_MODE (x)
6870 && COMPARISON_P (XEXP (XEXP (x, 0), 0))
6871 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
6872 <= HOST_BITS_PER_WIDE_INT)
6873 && (STORE_FLAG_VALUE & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
6874 return XEXP (XEXP (x, 0), 0);
6876 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
6877 if (GET_CODE (XEXP (x, 0)) == SUBREG
6878 && GET_MODE (SUBREG_REG (XEXP (x, 0))) == GET_MODE (x)
6879 && subreg_lowpart_p (XEXP (x, 0))
6880 && COMPARISON_P (SUBREG_REG (XEXP (x, 0)))
6881 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
6882 <= HOST_BITS_PER_WIDE_INT)
6883 && (STORE_FLAG_VALUE & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
6884 return SUBREG_REG (XEXP (x, 0));
6888 /* If we reach here, we want to return a pair of shifts. The inner
6889 shift is a left shift of BITSIZE - POS - LEN bits. The outer
6890 shift is a right shift of BITSIZE - LEN bits. It is arithmetic or
6891 logical depending on the value of UNSIGNEDP.
6893 If this was a ZERO_EXTEND or ZERO_EXTRACT, this pair of shifts will be
6894 converted into an AND of a shift.
6896 We must check for the case where the left shift would have a negative
6897 count. This can happen in a case like (x >> 31) & 255 on machines
6898 that can't shift by a constant. On those machines, we would first
6899 combine the shift with the AND to produce a variable-position
6900 extraction. Then the constant of 31 would be substituted in
6901 to produce such a position. */
6903 modewidth = GET_MODE_BITSIZE (GET_MODE (x));
6904 if (modewidth >= pos + len)
6906 enum machine_mode mode = GET_MODE (x);
6907 tem = gen_lowpart (mode, XEXP (x, 0));
6908 if (!tem || GET_CODE (tem) == CLOBBER)
6910 tem = simplify_shift_const (NULL_RTX, ASHIFT, mode,
6911 tem, modewidth - pos - len);
6912 tem = simplify_shift_const (NULL_RTX, unsignedp ? LSHIFTRT : ASHIFTRT,
6913 mode, tem, modewidth - len);
6915 else if (unsignedp && len < HOST_BITS_PER_WIDE_INT)
6916 tem = simplify_and_const_int (NULL_RTX, GET_MODE (x),
6917 simplify_shift_const (NULL_RTX, LSHIFTRT,
6920 ((unsigned HOST_WIDE_INT) 1 << len) - 1);
6922 /* Any other cases we can't handle. */
6925 /* If we couldn't do this for some reason, return the original
6927 if (GET_CODE (tem) == CLOBBER)
6933 /* X is a SET which contains an assignment of one object into
6934 a part of another (such as a bit-field assignment, STRICT_LOW_PART,
6935 or certain SUBREGS). If possible, convert it into a series of
6938 We half-heartedly support variable positions, but do not at all
6939 support variable lengths. */
6942 expand_field_assignment (const_rtx x)
6945 rtx pos; /* Always counts from low bit. */
6947 rtx mask, cleared, masked;
6948 enum machine_mode compute_mode;
6950 /* Loop until we find something we can't simplify. */
6953 if (GET_CODE (SET_DEST (x)) == STRICT_LOW_PART
6954 && GET_CODE (XEXP (SET_DEST (x), 0)) == SUBREG)
6956 inner = SUBREG_REG (XEXP (SET_DEST (x), 0));
6957 len = GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0)));
6958 pos = GEN_INT (subreg_lsb (XEXP (SET_DEST (x), 0)));
6960 else if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
6961 && CONST_INT_P (XEXP (SET_DEST (x), 1)))
6963 inner = XEXP (SET_DEST (x), 0);
6964 len = INTVAL (XEXP (SET_DEST (x), 1));
6965 pos = XEXP (SET_DEST (x), 2);
6967 /* A constant position should stay within the width of INNER. */
6968 if (CONST_INT_P (pos)
6969 && INTVAL (pos) + len > GET_MODE_BITSIZE (GET_MODE (inner)))
6972 if (BITS_BIG_ENDIAN)
6974 if (CONST_INT_P (pos))
6975 pos = GEN_INT (GET_MODE_BITSIZE (GET_MODE (inner)) - len
6977 else if (GET_CODE (pos) == MINUS
6978 && CONST_INT_P (XEXP (pos, 1))
6979 && (INTVAL (XEXP (pos, 1))
6980 == GET_MODE_BITSIZE (GET_MODE (inner)) - len))
6981 /* If position is ADJUST - X, new position is X. */
6982 pos = XEXP (pos, 0);
6984 pos = simplify_gen_binary (MINUS, GET_MODE (pos),
6985 GEN_INT (GET_MODE_BITSIZE (
6992 /* A SUBREG between two modes that occupy the same numbers of words
6993 can be done by moving the SUBREG to the source. */
6994 else if (GET_CODE (SET_DEST (x)) == SUBREG
6995 /* We need SUBREGs to compute nonzero_bits properly. */
6996 && nonzero_sign_valid
6997 && (((GET_MODE_SIZE (GET_MODE (SET_DEST (x)))
6998 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
6999 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x))))
7000 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)))
7002 x = gen_rtx_SET (VOIDmode, SUBREG_REG (SET_DEST (x)),
7004 (GET_MODE (SUBREG_REG (SET_DEST (x))),
7011 while (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
7012 inner = SUBREG_REG (inner);
7014 compute_mode = GET_MODE (inner);
7016 /* Don't attempt bitwise arithmetic on non scalar integer modes. */
7017 if (! SCALAR_INT_MODE_P (compute_mode))
7019 enum machine_mode imode;
7021 /* Don't do anything for vector or complex integral types. */
7022 if (! FLOAT_MODE_P (compute_mode))
7025 /* Try to find an integral mode to pun with. */
7026 imode = mode_for_size (GET_MODE_BITSIZE (compute_mode), MODE_INT, 0);
7027 if (imode == BLKmode)
7030 compute_mode = imode;
7031 inner = gen_lowpart (imode, inner);
7034 /* Compute a mask of LEN bits, if we can do this on the host machine. */
7035 if (len >= HOST_BITS_PER_WIDE_INT)
7038 /* Now compute the equivalent expression. Make a copy of INNER
7039 for the SET_DEST in case it is a MEM into which we will substitute;
7040 we don't want shared RTL in that case. */
7041 mask = GEN_INT (((unsigned HOST_WIDE_INT) 1 << len) - 1);
7042 cleared = simplify_gen_binary (AND, compute_mode,
7043 simplify_gen_unary (NOT, compute_mode,
7044 simplify_gen_binary (ASHIFT,
7049 masked = simplify_gen_binary (ASHIFT, compute_mode,
7050 simplify_gen_binary (
7052 gen_lowpart (compute_mode, SET_SRC (x)),
7056 x = gen_rtx_SET (VOIDmode, copy_rtx (inner),
7057 simplify_gen_binary (IOR, compute_mode,
7064 /* Return an RTX for a reference to LEN bits of INNER. If POS_RTX is nonzero,
7065 it is an RTX that represents a variable starting position; otherwise,
7066 POS is the (constant) starting bit position (counted from the LSB).
7068 UNSIGNEDP is nonzero for an unsigned reference and zero for a
7071 IN_DEST is nonzero if this is a reference in the destination of a
7072 SET. This is used when a ZERO_ or SIGN_EXTRACT isn't needed. If nonzero,
7073 a STRICT_LOW_PART will be used, if zero, ZERO_EXTEND or SIGN_EXTEND will
7076 IN_COMPARE is nonzero if we are in a COMPARE. This means that a
7077 ZERO_EXTRACT should be built even for bits starting at bit 0.
7079 MODE is the desired mode of the result (if IN_DEST == 0).
7081 The result is an RTX for the extraction or NULL_RTX if the target
7085 make_extraction (enum machine_mode mode, rtx inner, HOST_WIDE_INT pos,
7086 rtx pos_rtx, unsigned HOST_WIDE_INT len, int unsignedp,
7087 int in_dest, int in_compare)
7089 /* This mode describes the size of the storage area
7090 to fetch the overall value from. Within that, we
7091 ignore the POS lowest bits, etc. */
7092 enum machine_mode is_mode = GET_MODE (inner);
7093 enum machine_mode inner_mode;
7094 enum machine_mode wanted_inner_mode;
7095 enum machine_mode wanted_inner_reg_mode = word_mode;
7096 enum machine_mode pos_mode = word_mode;
7097 enum machine_mode extraction_mode = word_mode;
7098 enum machine_mode tmode = mode_for_size (len, MODE_INT, 1);
7100 rtx orig_pos_rtx = pos_rtx;
7101 HOST_WIDE_INT orig_pos;
7103 if (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
7105 /* If going from (subreg:SI (mem:QI ...)) to (mem:QI ...),
7106 consider just the QI as the memory to extract from.
7107 The subreg adds or removes high bits; its mode is
7108 irrelevant to the meaning of this extraction,
7109 since POS and LEN count from the lsb. */
7110 if (MEM_P (SUBREG_REG (inner)))
7111 is_mode = GET_MODE (SUBREG_REG (inner));
7112 inner = SUBREG_REG (inner);
7114 else if (GET_CODE (inner) == ASHIFT
7115 && CONST_INT_P (XEXP (inner, 1))
7116 && pos_rtx == 0 && pos == 0
7117 && len > UINTVAL (XEXP (inner, 1)))
7119 /* We're extracting the least significant bits of an rtx
7120 (ashift X (const_int C)), where LEN > C. Extract the
7121 least significant (LEN - C) bits of X, giving an rtx
7122 whose mode is MODE, then shift it left C times. */
7123 new_rtx = make_extraction (mode, XEXP (inner, 0),
7124 0, 0, len - INTVAL (XEXP (inner, 1)),
7125 unsignedp, in_dest, in_compare);
7127 return gen_rtx_ASHIFT (mode, new_rtx, XEXP (inner, 1));
7130 inner_mode = GET_MODE (inner);
7132 if (pos_rtx && CONST_INT_P (pos_rtx))
7133 pos = INTVAL (pos_rtx), pos_rtx = 0;
7135 /* See if this can be done without an extraction. We never can if the
7136 width of the field is not the same as that of some integer mode. For
7137 registers, we can only avoid the extraction if the position is at the
7138 low-order bit and this is either not in the destination or we have the
7139 appropriate STRICT_LOW_PART operation available.
7141 For MEM, we can avoid an extract if the field starts on an appropriate
7142 boundary and we can change the mode of the memory reference. */
7144 if (tmode != BLKmode
7145 && ((pos_rtx == 0 && (pos % BITS_PER_WORD) == 0
7147 && (inner_mode == tmode
7149 || TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (tmode),
7150 GET_MODE_BITSIZE (inner_mode))
7151 || reg_truncated_to_mode (tmode, inner))
7154 && have_insn_for (STRICT_LOW_PART, tmode))))
7155 || (MEM_P (inner) && pos_rtx == 0
7157 % (STRICT_ALIGNMENT ? GET_MODE_ALIGNMENT (tmode)
7158 : BITS_PER_UNIT)) == 0
7159 /* We can't do this if we are widening INNER_MODE (it
7160 may not be aligned, for one thing). */
7161 && GET_MODE_BITSIZE (inner_mode) >= GET_MODE_BITSIZE (tmode)
7162 && (inner_mode == tmode
7163 || (! mode_dependent_address_p (XEXP (inner, 0))
7164 && ! MEM_VOLATILE_P (inner))))))
7166 /* If INNER is a MEM, make a new MEM that encompasses just the desired
7167 field. If the original and current mode are the same, we need not
7168 adjust the offset. Otherwise, we do if bytes big endian.
7170 If INNER is not a MEM, get a piece consisting of just the field
7171 of interest (in this case POS % BITS_PER_WORD must be 0). */
7175 HOST_WIDE_INT offset;
7177 /* POS counts from lsb, but make OFFSET count in memory order. */
7178 if (BYTES_BIG_ENDIAN)
7179 offset = (GET_MODE_BITSIZE (is_mode) - len - pos) / BITS_PER_UNIT;
7181 offset = pos / BITS_PER_UNIT;
7183 new_rtx = adjust_address_nv (inner, tmode, offset);
7185 else if (REG_P (inner))
7187 if (tmode != inner_mode)
7189 /* We can't call gen_lowpart in a DEST since we
7190 always want a SUBREG (see below) and it would sometimes
7191 return a new hard register. */
7194 HOST_WIDE_INT final_word = pos / BITS_PER_WORD;
7196 if (WORDS_BIG_ENDIAN
7197 && GET_MODE_SIZE (inner_mode) > UNITS_PER_WORD)
7198 final_word = ((GET_MODE_SIZE (inner_mode)
7199 - GET_MODE_SIZE (tmode))
7200 / UNITS_PER_WORD) - final_word;
7202 final_word *= UNITS_PER_WORD;
7203 if (BYTES_BIG_ENDIAN &&
7204 GET_MODE_SIZE (inner_mode) > GET_MODE_SIZE (tmode))
7205 final_word += (GET_MODE_SIZE (inner_mode)
7206 - GET_MODE_SIZE (tmode)) % UNITS_PER_WORD;
7208 /* Avoid creating invalid subregs, for example when
7209 simplifying (x>>32)&255. */
7210 if (!validate_subreg (tmode, inner_mode, inner, final_word))
7213 new_rtx = gen_rtx_SUBREG (tmode, inner, final_word);
7216 new_rtx = gen_lowpart (tmode, inner);
7222 new_rtx = force_to_mode (inner, tmode,
7223 len >= HOST_BITS_PER_WIDE_INT
7224 ? ~(unsigned HOST_WIDE_INT) 0
7225 : ((unsigned HOST_WIDE_INT) 1 << len) - 1,
7228 /* If this extraction is going into the destination of a SET,
7229 make a STRICT_LOW_PART unless we made a MEM. */
7232 return (MEM_P (new_rtx) ? new_rtx
7233 : (GET_CODE (new_rtx) != SUBREG
7234 ? gen_rtx_CLOBBER (tmode, const0_rtx)
7235 : gen_rtx_STRICT_LOW_PART (VOIDmode, new_rtx)));
7240 if (CONST_INT_P (new_rtx)
7241 || GET_CODE (new_rtx) == CONST_DOUBLE)
7242 return simplify_unary_operation (unsignedp ? ZERO_EXTEND : SIGN_EXTEND,
7243 mode, new_rtx, tmode);
7245 /* If we know that no extraneous bits are set, and that the high
7246 bit is not set, convert the extraction to the cheaper of
7247 sign and zero extension, that are equivalent in these cases. */
7248 if (flag_expensive_optimizations
7249 && (GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT
7250 && ((nonzero_bits (new_rtx, tmode)
7251 & ~(((unsigned HOST_WIDE_INT)
7252 GET_MODE_MASK (tmode))
7256 rtx temp = gen_rtx_ZERO_EXTEND (mode, new_rtx);
7257 rtx temp1 = gen_rtx_SIGN_EXTEND (mode, new_rtx);
7259 /* Prefer ZERO_EXTENSION, since it gives more information to
7261 if (rtx_cost (temp, SET, optimize_this_for_speed_p)
7262 <= rtx_cost (temp1, SET, optimize_this_for_speed_p))
7267 /* Otherwise, sign- or zero-extend unless we already are in the
7270 return (gen_rtx_fmt_e (unsignedp ? ZERO_EXTEND : SIGN_EXTEND,
7274 /* Unless this is a COMPARE or we have a funny memory reference,
7275 don't do anything with zero-extending field extracts starting at
7276 the low-order bit since they are simple AND operations. */
7277 if (pos_rtx == 0 && pos == 0 && ! in_dest
7278 && ! in_compare && unsignedp)
7281 /* Unless INNER is not MEM, reject this if we would be spanning bytes or
7282 if the position is not a constant and the length is not 1. In all
7283 other cases, we would only be going outside our object in cases when
7284 an original shift would have been undefined. */
7286 && ((pos_rtx == 0 && pos + len > GET_MODE_BITSIZE (is_mode))
7287 || (pos_rtx != 0 && len != 1)))
7290 /* Get the mode to use should INNER not be a MEM, the mode for the position,
7291 and the mode for the result. */
7292 if (in_dest && mode_for_extraction (EP_insv, -1) != MAX_MACHINE_MODE)
7294 wanted_inner_reg_mode = mode_for_extraction (EP_insv, 0);
7295 pos_mode = mode_for_extraction (EP_insv, 2);
7296 extraction_mode = mode_for_extraction (EP_insv, 3);
7299 if (! in_dest && unsignedp
7300 && mode_for_extraction (EP_extzv, -1) != MAX_MACHINE_MODE)
7302 wanted_inner_reg_mode = mode_for_extraction (EP_extzv, 1);
7303 pos_mode = mode_for_extraction (EP_extzv, 3);
7304 extraction_mode = mode_for_extraction (EP_extzv, 0);
7307 if (! in_dest && ! unsignedp
7308 && mode_for_extraction (EP_extv, -1) != MAX_MACHINE_MODE)
7310 wanted_inner_reg_mode = mode_for_extraction (EP_extv, 1);
7311 pos_mode = mode_for_extraction (EP_extv, 3);
7312 extraction_mode = mode_for_extraction (EP_extv, 0);
7315 /* Never narrow an object, since that might not be safe. */
7317 if (mode != VOIDmode
7318 && GET_MODE_SIZE (extraction_mode) < GET_MODE_SIZE (mode))
7319 extraction_mode = mode;
7321 if (pos_rtx && GET_MODE (pos_rtx) != VOIDmode
7322 && GET_MODE_SIZE (pos_mode) < GET_MODE_SIZE (GET_MODE (pos_rtx)))
7323 pos_mode = GET_MODE (pos_rtx);
7325 /* If this is not from memory, the desired mode is the preferred mode
7326 for an extraction pattern's first input operand, or word_mode if there
7329 wanted_inner_mode = wanted_inner_reg_mode;
7332 /* Be careful not to go beyond the extracted object and maintain the
7333 natural alignment of the memory. */
7334 wanted_inner_mode = smallest_mode_for_size (len, MODE_INT);
7335 while (pos % GET_MODE_BITSIZE (wanted_inner_mode) + len
7336 > GET_MODE_BITSIZE (wanted_inner_mode))
7338 wanted_inner_mode = GET_MODE_WIDER_MODE (wanted_inner_mode);
7339 gcc_assert (wanted_inner_mode != VOIDmode);
7342 /* If we have to change the mode of memory and cannot, the desired mode
7343 is EXTRACTION_MODE. */
7344 if (inner_mode != wanted_inner_mode
7345 && (mode_dependent_address_p (XEXP (inner, 0))
7346 || MEM_VOLATILE_P (inner)
7348 wanted_inner_mode = extraction_mode;
7353 if (BITS_BIG_ENDIAN)
7355 /* POS is passed as if BITS_BIG_ENDIAN == 0, so we need to convert it to
7356 BITS_BIG_ENDIAN style. If position is constant, compute new
7357 position. Otherwise, build subtraction.
7358 Note that POS is relative to the mode of the original argument.
7359 If it's a MEM we need to recompute POS relative to that.
7360 However, if we're extracting from (or inserting into) a register,
7361 we want to recompute POS relative to wanted_inner_mode. */
7362 int width = (MEM_P (inner)
7363 ? GET_MODE_BITSIZE (is_mode)
7364 : GET_MODE_BITSIZE (wanted_inner_mode));
7367 pos = width - len - pos;
7370 = gen_rtx_MINUS (GET_MODE (pos_rtx), GEN_INT (width - len), pos_rtx);
7371 /* POS may be less than 0 now, but we check for that below.
7372 Note that it can only be less than 0 if !MEM_P (inner). */
7375 /* If INNER has a wider mode, and this is a constant extraction, try to
7376 make it smaller and adjust the byte to point to the byte containing
7378 if (wanted_inner_mode != VOIDmode
7379 && inner_mode != wanted_inner_mode
7381 && GET_MODE_SIZE (wanted_inner_mode) < GET_MODE_SIZE (is_mode)
7383 && ! mode_dependent_address_p (XEXP (inner, 0))
7384 && ! MEM_VOLATILE_P (inner))
7388 /* The computations below will be correct if the machine is big
7389 endian in both bits and bytes or little endian in bits and bytes.
7390 If it is mixed, we must adjust. */
7392 /* If bytes are big endian and we had a paradoxical SUBREG, we must
7393 adjust OFFSET to compensate. */
7394 if (BYTES_BIG_ENDIAN
7395 && GET_MODE_SIZE (inner_mode) < GET_MODE_SIZE (is_mode))
7396 offset -= GET_MODE_SIZE (is_mode) - GET_MODE_SIZE (inner_mode);
7398 /* We can now move to the desired byte. */
7399 offset += (pos / GET_MODE_BITSIZE (wanted_inner_mode))
7400 * GET_MODE_SIZE (wanted_inner_mode);
7401 pos %= GET_MODE_BITSIZE (wanted_inner_mode);
7403 if (BYTES_BIG_ENDIAN != BITS_BIG_ENDIAN
7404 && is_mode != wanted_inner_mode)
7405 offset = (GET_MODE_SIZE (is_mode)
7406 - GET_MODE_SIZE (wanted_inner_mode) - offset);
7408 inner = adjust_address_nv (inner, wanted_inner_mode, offset);
7411 /* If INNER is not memory, get it into the proper mode. If we are changing
7412 its mode, POS must be a constant and smaller than the size of the new
7414 else if (!MEM_P (inner))
7416 /* On the LHS, don't create paradoxical subregs implicitely truncating
7417 the register unless TRULY_NOOP_TRUNCATION. */
7419 && !TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (GET_MODE (inner)),
7420 GET_MODE_BITSIZE (wanted_inner_mode)))
7423 if (GET_MODE (inner) != wanted_inner_mode
7425 || orig_pos + len > GET_MODE_BITSIZE (wanted_inner_mode)))
7431 inner = force_to_mode (inner, wanted_inner_mode,
7433 || len + orig_pos >= HOST_BITS_PER_WIDE_INT
7434 ? ~(unsigned HOST_WIDE_INT) 0
7435 : ((((unsigned HOST_WIDE_INT) 1 << len) - 1)
7440 /* Adjust mode of POS_RTX, if needed. If we want a wider mode, we
7441 have to zero extend. Otherwise, we can just use a SUBREG. */
7443 && GET_MODE_SIZE (pos_mode) > GET_MODE_SIZE (GET_MODE (pos_rtx)))
7445 rtx temp = gen_rtx_ZERO_EXTEND (pos_mode, pos_rtx);
7447 /* If we know that no extraneous bits are set, and that the high
7448 bit is not set, convert extraction to cheaper one - either
7449 SIGN_EXTENSION or ZERO_EXTENSION, that are equivalent in these
7451 if (flag_expensive_optimizations
7452 && (GET_MODE_BITSIZE (GET_MODE (pos_rtx)) <= HOST_BITS_PER_WIDE_INT
7453 && ((nonzero_bits (pos_rtx, GET_MODE (pos_rtx))
7454 & ~(((unsigned HOST_WIDE_INT)
7455 GET_MODE_MASK (GET_MODE (pos_rtx)))
7459 rtx temp1 = gen_rtx_SIGN_EXTEND (pos_mode, pos_rtx);
7461 /* Prefer ZERO_EXTENSION, since it gives more information to
7463 if (rtx_cost (temp1, SET, optimize_this_for_speed_p)
7464 < rtx_cost (temp, SET, optimize_this_for_speed_p))
7469 else if (pos_rtx != 0
7470 && GET_MODE_SIZE (pos_mode) < GET_MODE_SIZE (GET_MODE (pos_rtx)))
7471 pos_rtx = gen_lowpart (pos_mode, pos_rtx);
7473 /* Make POS_RTX unless we already have it and it is correct. If we don't
7474 have a POS_RTX but we do have an ORIG_POS_RTX, the latter must
7476 if (pos_rtx == 0 && orig_pos_rtx != 0 && INTVAL (orig_pos_rtx) == pos)
7477 pos_rtx = orig_pos_rtx;
7479 else if (pos_rtx == 0)
7480 pos_rtx = GEN_INT (pos);
7482 /* Make the required operation. See if we can use existing rtx. */
7483 new_rtx = gen_rtx_fmt_eee (unsignedp ? ZERO_EXTRACT : SIGN_EXTRACT,
7484 extraction_mode, inner, GEN_INT (len), pos_rtx);
7486 new_rtx = gen_lowpart (mode, new_rtx);
7491 /* See if X contains an ASHIFT of COUNT or more bits that can be commuted
7492 with any other operations in X. Return X without that shift if so. */
7495 extract_left_shift (rtx x, int count)
7497 enum rtx_code code = GET_CODE (x);
7498 enum machine_mode mode = GET_MODE (x);
7504 /* This is the shift itself. If it is wide enough, we will return
7505 either the value being shifted if the shift count is equal to
7506 COUNT or a shift for the difference. */
7507 if (CONST_INT_P (XEXP (x, 1))
7508 && INTVAL (XEXP (x, 1)) >= count)
7509 return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (x, 0),
7510 INTVAL (XEXP (x, 1)) - count);
7514 if ((tem = extract_left_shift (XEXP (x, 0), count)) != 0)
7515 return simplify_gen_unary (code, mode, tem, mode);
7519 case PLUS: case IOR: case XOR: case AND:
7520 /* If we can safely shift this constant and we find the inner shift,
7521 make a new operation. */
7522 if (CONST_INT_P (XEXP (x, 1))
7523 && (UINTVAL (XEXP (x, 1))
7524 & ((((unsigned HOST_WIDE_INT) 1 << count)) - 1)) == 0
7525 && (tem = extract_left_shift (XEXP (x, 0), count)) != 0)
7526 return simplify_gen_binary (code, mode, tem,
7527 GEN_INT (INTVAL (XEXP (x, 1)) >> count));
7538 /* Look at the expression rooted at X. Look for expressions
7539 equivalent to ZERO_EXTRACT, SIGN_EXTRACT, ZERO_EXTEND, SIGN_EXTEND.
7540 Form these expressions.
7542 Return the new rtx, usually just X.
7544 Also, for machines like the VAX that don't have logical shift insns,
7545 try to convert logical to arithmetic shift operations in cases where
7546 they are equivalent. This undoes the canonicalizations to logical
7547 shifts done elsewhere.
7549 We try, as much as possible, to re-use rtl expressions to save memory.
7551 IN_CODE says what kind of expression we are processing. Normally, it is
7552 SET. In a memory address (inside a MEM, PLUS or minus, the latter two
7553 being kludges), it is MEM. When processing the arguments of a comparison
7554 or a COMPARE against zero, it is COMPARE. */
7557 make_compound_operation (rtx x, enum rtx_code in_code)
7559 enum rtx_code code = GET_CODE (x);
7560 enum machine_mode mode = GET_MODE (x);
7561 int mode_width = GET_MODE_BITSIZE (mode);
7563 enum rtx_code next_code;
7569 /* Select the code to be used in recursive calls. Once we are inside an
7570 address, we stay there. If we have a comparison, set to COMPARE,
7571 but once inside, go back to our default of SET. */
7573 next_code = (code == MEM ? MEM
7574 : ((code == PLUS || code == MINUS)
7575 && SCALAR_INT_MODE_P (mode)) ? MEM
7576 : ((code == COMPARE || COMPARISON_P (x))
7577 && XEXP (x, 1) == const0_rtx) ? COMPARE
7578 : in_code == COMPARE ? SET : in_code);
7580 /* Process depending on the code of this operation. If NEW is set
7581 nonzero, it will be returned. */
7586 /* Convert shifts by constants into multiplications if inside
7588 if (in_code == MEM && CONST_INT_P (XEXP (x, 1))
7589 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT
7590 && INTVAL (XEXP (x, 1)) >= 0
7591 && SCALAR_INT_MODE_P (mode))
7593 HOST_WIDE_INT count = INTVAL (XEXP (x, 1));
7594 HOST_WIDE_INT multval = (HOST_WIDE_INT) 1 << count;
7596 new_rtx = make_compound_operation (XEXP (x, 0), next_code);
7597 if (GET_CODE (new_rtx) == NEG)
7599 new_rtx = XEXP (new_rtx, 0);
7602 multval = trunc_int_for_mode (multval, mode);
7603 new_rtx = gen_rtx_MULT (mode, new_rtx, GEN_INT (multval));
7610 lhs = make_compound_operation (lhs, next_code);
7611 rhs = make_compound_operation (rhs, next_code);
7612 if (GET_CODE (lhs) == MULT && GET_CODE (XEXP (lhs, 0)) == NEG
7613 && SCALAR_INT_MODE_P (mode))
7615 tem = simplify_gen_binary (MULT, mode, XEXP (XEXP (lhs, 0), 0),
7617 new_rtx = simplify_gen_binary (MINUS, mode, rhs, tem);
7619 else if (GET_CODE (lhs) == MULT
7620 && (CONST_INT_P (XEXP (lhs, 1)) && INTVAL (XEXP (lhs, 1)) < 0))
7622 tem = simplify_gen_binary (MULT, mode, XEXP (lhs, 0),
7623 simplify_gen_unary (NEG, mode,
7626 new_rtx = simplify_gen_binary (MINUS, mode, rhs, tem);
7630 SUBST (XEXP (x, 0), lhs);
7631 SUBST (XEXP (x, 1), rhs);
7634 x = gen_lowpart (mode, new_rtx);
7640 lhs = make_compound_operation (lhs, next_code);
7641 rhs = make_compound_operation (rhs, next_code);
7642 if (GET_CODE (rhs) == MULT && GET_CODE (XEXP (rhs, 0)) == NEG
7643 && SCALAR_INT_MODE_P (mode))
7645 tem = simplify_gen_binary (MULT, mode, XEXP (XEXP (rhs, 0), 0),
7647 new_rtx = simplify_gen_binary (PLUS, mode, tem, lhs);
7649 else if (GET_CODE (rhs) == MULT
7650 && (CONST_INT_P (XEXP (rhs, 1)) && INTVAL (XEXP (rhs, 1)) < 0))
7652 tem = simplify_gen_binary (MULT, mode, XEXP (rhs, 0),
7653 simplify_gen_unary (NEG, mode,
7656 new_rtx = simplify_gen_binary (PLUS, mode, tem, lhs);
7660 SUBST (XEXP (x, 0), lhs);
7661 SUBST (XEXP (x, 1), rhs);
7664 return gen_lowpart (mode, new_rtx);
7667 /* If the second operand is not a constant, we can't do anything
7669 if (!CONST_INT_P (XEXP (x, 1)))
7672 /* If the constant is a power of two minus one and the first operand
7673 is a logical right shift, make an extraction. */
7674 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
7675 && (i = exact_log2 (UINTVAL (XEXP (x, 1)) + 1)) >= 0)
7677 new_rtx = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code);
7678 new_rtx = make_extraction (mode, new_rtx, 0, XEXP (XEXP (x, 0), 1), i, 1,
7679 0, in_code == COMPARE);
7682 /* Same as previous, but for (subreg (lshiftrt ...)) in first op. */
7683 else if (GET_CODE (XEXP (x, 0)) == SUBREG
7684 && subreg_lowpart_p (XEXP (x, 0))
7685 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == LSHIFTRT
7686 && (i = exact_log2 (UINTVAL (XEXP (x, 1)) + 1)) >= 0)
7688 new_rtx = make_compound_operation (XEXP (SUBREG_REG (XEXP (x, 0)), 0),
7690 new_rtx = make_extraction (GET_MODE (SUBREG_REG (XEXP (x, 0))), new_rtx, 0,
7691 XEXP (SUBREG_REG (XEXP (x, 0)), 1), i, 1,
7692 0, in_code == COMPARE);
7694 /* Same as previous, but for (xor/ior (lshiftrt...) (lshiftrt...)). */
7695 else if ((GET_CODE (XEXP (x, 0)) == XOR
7696 || GET_CODE (XEXP (x, 0)) == IOR)
7697 && GET_CODE (XEXP (XEXP (x, 0), 0)) == LSHIFTRT
7698 && GET_CODE (XEXP (XEXP (x, 0), 1)) == LSHIFTRT
7699 && (i = exact_log2 (UINTVAL (XEXP (x, 1)) + 1)) >= 0)
7701 /* Apply the distributive law, and then try to make extractions. */
7702 new_rtx = gen_rtx_fmt_ee (GET_CODE (XEXP (x, 0)), mode,
7703 gen_rtx_AND (mode, XEXP (XEXP (x, 0), 0),
7705 gen_rtx_AND (mode, XEXP (XEXP (x, 0), 1),
7707 new_rtx = make_compound_operation (new_rtx, in_code);
7710 /* If we are have (and (rotate X C) M) and C is larger than the number
7711 of bits in M, this is an extraction. */
7713 else if (GET_CODE (XEXP (x, 0)) == ROTATE
7714 && CONST_INT_P (XEXP (XEXP (x, 0), 1))
7715 && (i = exact_log2 (UINTVAL (XEXP (x, 1)) + 1)) >= 0
7716 && i <= INTVAL (XEXP (XEXP (x, 0), 1)))
7718 new_rtx = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code);
7719 new_rtx = make_extraction (mode, new_rtx,
7720 (GET_MODE_BITSIZE (mode)
7721 - INTVAL (XEXP (XEXP (x, 0), 1))),
7722 NULL_RTX, i, 1, 0, in_code == COMPARE);
7725 /* On machines without logical shifts, if the operand of the AND is
7726 a logical shift and our mask turns off all the propagated sign
7727 bits, we can replace the logical shift with an arithmetic shift. */
7728 else if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
7729 && !have_insn_for (LSHIFTRT, mode)
7730 && have_insn_for (ASHIFTRT, mode)
7731 && CONST_INT_P (XEXP (XEXP (x, 0), 1))
7732 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
7733 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT
7734 && mode_width <= HOST_BITS_PER_WIDE_INT)
7736 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
7738 mask >>= INTVAL (XEXP (XEXP (x, 0), 1));
7739 if ((INTVAL (XEXP (x, 1)) & ~mask) == 0)
7741 gen_rtx_ASHIFTRT (mode,
7742 make_compound_operation
7743 (XEXP (XEXP (x, 0), 0), next_code),
7744 XEXP (XEXP (x, 0), 1)));
7747 /* If the constant is one less than a power of two, this might be
7748 representable by an extraction even if no shift is present.
7749 If it doesn't end up being a ZERO_EXTEND, we will ignore it unless
7750 we are in a COMPARE. */
7751 else if ((i = exact_log2 (UINTVAL (XEXP (x, 1)) + 1)) >= 0)
7752 new_rtx = make_extraction (mode,
7753 make_compound_operation (XEXP (x, 0),
7755 0, NULL_RTX, i, 1, 0, in_code == COMPARE);
7757 /* If we are in a comparison and this is an AND with a power of two,
7758 convert this into the appropriate bit extract. */
7759 else if (in_code == COMPARE
7760 && (i = exact_log2 (UINTVAL (XEXP (x, 1)))) >= 0)
7761 new_rtx = make_extraction (mode,
7762 make_compound_operation (XEXP (x, 0),
7764 i, NULL_RTX, 1, 1, 0, 1);
7769 /* If the sign bit is known to be zero, replace this with an
7770 arithmetic shift. */
7771 if (have_insn_for (ASHIFTRT, mode)
7772 && ! have_insn_for (LSHIFTRT, mode)
7773 && mode_width <= HOST_BITS_PER_WIDE_INT
7774 && (nonzero_bits (XEXP (x, 0), mode) & (1 << (mode_width - 1))) == 0)
7776 new_rtx = gen_rtx_ASHIFTRT (mode,
7777 make_compound_operation (XEXP (x, 0),
7783 /* ... fall through ... */
7789 /* If we have (ashiftrt (ashift foo C1) C2) with C2 >= C1,
7790 this is a SIGN_EXTRACT. */
7791 if (CONST_INT_P (rhs)
7792 && GET_CODE (lhs) == ASHIFT
7793 && CONST_INT_P (XEXP (lhs, 1))
7794 && INTVAL (rhs) >= INTVAL (XEXP (lhs, 1))
7795 && INTVAL (rhs) < mode_width)
7797 new_rtx = make_compound_operation (XEXP (lhs, 0), next_code);
7798 new_rtx = make_extraction (mode, new_rtx,
7799 INTVAL (rhs) - INTVAL (XEXP (lhs, 1)),
7800 NULL_RTX, mode_width - INTVAL (rhs),
7801 code == LSHIFTRT, 0, in_code == COMPARE);
7805 /* See if we have operations between an ASHIFTRT and an ASHIFT.
7806 If so, try to merge the shifts into a SIGN_EXTEND. We could
7807 also do this for some cases of SIGN_EXTRACT, but it doesn't
7808 seem worth the effort; the case checked for occurs on Alpha. */
7811 && ! (GET_CODE (lhs) == SUBREG
7812 && (OBJECT_P (SUBREG_REG (lhs))))
7813 && CONST_INT_P (rhs)
7814 && INTVAL (rhs) < HOST_BITS_PER_WIDE_INT
7815 && INTVAL (rhs) < mode_width
7816 && (new_rtx = extract_left_shift (lhs, INTVAL (rhs))) != 0)
7817 new_rtx = make_extraction (mode, make_compound_operation (new_rtx, next_code),
7818 0, NULL_RTX, mode_width - INTVAL (rhs),
7819 code == LSHIFTRT, 0, in_code == COMPARE);
7824 /* Call ourselves recursively on the inner expression. If we are
7825 narrowing the object and it has a different RTL code from
7826 what it originally did, do this SUBREG as a force_to_mode. */
7828 rtx inner = SUBREG_REG (x), simplified;
7830 tem = make_compound_operation (inner, in_code);
7833 = simplify_subreg (mode, tem, GET_MODE (inner), SUBREG_BYTE (x));
7837 if (GET_CODE (tem) != GET_CODE (inner)
7838 && GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (inner))
7839 && subreg_lowpart_p (x))
7842 = force_to_mode (tem, mode, ~(unsigned HOST_WIDE_INT) 0, 0);
7844 /* If we have something other than a SUBREG, we might have
7845 done an expansion, so rerun ourselves. */
7846 if (GET_CODE (newer) != SUBREG)
7847 newer = make_compound_operation (newer, in_code);
7849 /* force_to_mode can expand compounds. If it just re-expanded the
7850 compound, use gen_lowpart to convert to the desired mode. */
7851 if (rtx_equal_p (newer, x)
7852 /* Likewise if it re-expanded the compound only partially.
7853 This happens for SUBREG of ZERO_EXTRACT if they extract
7854 the same number of bits. */
7855 || (GET_CODE (newer) == SUBREG
7856 && (GET_CODE (SUBREG_REG (newer)) == LSHIFTRT
7857 || GET_CODE (SUBREG_REG (newer)) == ASHIFTRT)
7858 && GET_CODE (inner) == AND
7859 && rtx_equal_p (SUBREG_REG (newer), XEXP (inner, 0))))
7860 return gen_lowpart (GET_MODE (x), tem);
7876 x = gen_lowpart (mode, new_rtx);
7877 code = GET_CODE (x);
7880 /* Now recursively process each operand of this operation. We need to
7881 handle ZERO_EXTEND specially so that we don't lose track of the
7883 if (GET_CODE (x) == ZERO_EXTEND)
7885 new_rtx = make_compound_operation (XEXP (x, 0), next_code);
7886 tem = simplify_const_unary_operation (ZERO_EXTEND, GET_MODE (x),
7887 new_rtx, GET_MODE (XEXP (x, 0)));
7890 SUBST (XEXP (x, 0), new_rtx);
7894 fmt = GET_RTX_FORMAT (code);
7895 for (i = 0; i < GET_RTX_LENGTH (code); i++)
7898 new_rtx = make_compound_operation (XEXP (x, i), next_code);
7899 SUBST (XEXP (x, i), new_rtx);
7901 else if (fmt[i] == 'E')
7902 for (j = 0; j < XVECLEN (x, i); j++)
7904 new_rtx = make_compound_operation (XVECEXP (x, i, j), next_code);
7905 SUBST (XVECEXP (x, i, j), new_rtx);
7909 /* If this is a commutative operation, the changes to the operands
7910 may have made it noncanonical. */
7911 if (COMMUTATIVE_ARITH_P (x)
7912 && swap_commutative_operands_p (XEXP (x, 0), XEXP (x, 1)))
7915 SUBST (XEXP (x, 0), XEXP (x, 1));
7916 SUBST (XEXP (x, 1), tem);
7922 /* Given M see if it is a value that would select a field of bits
7923 within an item, but not the entire word. Return -1 if not.
7924 Otherwise, return the starting position of the field, where 0 is the
7927 *PLEN is set to the length of the field. */
7930 get_pos_from_mask (unsigned HOST_WIDE_INT m, unsigned HOST_WIDE_INT *plen)
7932 /* Get the bit number of the first 1 bit from the right, -1 if none. */
7933 int pos = m ? ctz_hwi (m) : -1;
7937 /* Now shift off the low-order zero bits and see if we have a
7938 power of two minus 1. */
7939 len = exact_log2 ((m >> pos) + 1);
7948 /* If X refers to a register that equals REG in value, replace these
7949 references with REG. */
7951 canon_reg_for_combine (rtx x, rtx reg)
7958 enum rtx_code code = GET_CODE (x);
7959 switch (GET_RTX_CLASS (code))
7962 op0 = canon_reg_for_combine (XEXP (x, 0), reg);
7963 if (op0 != XEXP (x, 0))
7964 return simplify_gen_unary (GET_CODE (x), GET_MODE (x), op0,
7969 case RTX_COMM_ARITH:
7970 op0 = canon_reg_for_combine (XEXP (x, 0), reg);
7971 op1 = canon_reg_for_combine (XEXP (x, 1), reg);
7972 if (op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
7973 return simplify_gen_binary (GET_CODE (x), GET_MODE (x), op0, op1);
7977 case RTX_COMM_COMPARE:
7978 op0 = canon_reg_for_combine (XEXP (x, 0), reg);
7979 op1 = canon_reg_for_combine (XEXP (x, 1), reg);
7980 if (op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
7981 return simplify_gen_relational (GET_CODE (x), GET_MODE (x),
7982 GET_MODE (op0), op0, op1);
7986 case RTX_BITFIELD_OPS:
7987 op0 = canon_reg_for_combine (XEXP (x, 0), reg);
7988 op1 = canon_reg_for_combine (XEXP (x, 1), reg);
7989 op2 = canon_reg_for_combine (XEXP (x, 2), reg);
7990 if (op0 != XEXP (x, 0) || op1 != XEXP (x, 1) || op2 != XEXP (x, 2))
7991 return simplify_gen_ternary (GET_CODE (x), GET_MODE (x),
7992 GET_MODE (op0), op0, op1, op2);
7997 if (rtx_equal_p (get_last_value (reg), x)
7998 || rtx_equal_p (reg, get_last_value (x)))
8007 fmt = GET_RTX_FORMAT (code);
8009 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
8012 rtx op = canon_reg_for_combine (XEXP (x, i), reg);
8013 if (op != XEXP (x, i))
8023 else if (fmt[i] == 'E')
8026 for (j = 0; j < XVECLEN (x, i); j++)
8028 rtx op = canon_reg_for_combine (XVECEXP (x, i, j), reg);
8029 if (op != XVECEXP (x, i, j))
8036 XVECEXP (x, i, j) = op;
8047 /* Return X converted to MODE. If the value is already truncated to
8048 MODE we can just return a subreg even though in the general case we
8049 would need an explicit truncation. */
8052 gen_lowpart_or_truncate (enum machine_mode mode, rtx x)
8054 if (!CONST_INT_P (x)
8055 && GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (x))
8056 && !TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode),
8057 GET_MODE_BITSIZE (GET_MODE (x)))
8058 && !(REG_P (x) && reg_truncated_to_mode (mode, x)))
8060 /* Bit-cast X into an integer mode. */
8061 if (!SCALAR_INT_MODE_P (GET_MODE (x)))
8062 x = gen_lowpart (int_mode_for_mode (GET_MODE (x)), x);
8063 x = simplify_gen_unary (TRUNCATE, int_mode_for_mode (mode),
8067 return gen_lowpart (mode, x);
8070 /* See if X can be simplified knowing that we will only refer to it in
8071 MODE and will only refer to those bits that are nonzero in MASK.
8072 If other bits are being computed or if masking operations are done
8073 that select a superset of the bits in MASK, they can sometimes be
8076 Return a possibly simplified expression, but always convert X to
8077 MODE. If X is a CONST_INT, AND the CONST_INT with MASK.
8079 If JUST_SELECT is nonzero, don't optimize by noticing that bits in MASK
8080 are all off in X. This is used when X will be complemented, by either
8081 NOT, NEG, or XOR. */
8084 force_to_mode (rtx x, enum machine_mode mode, unsigned HOST_WIDE_INT mask,
8087 enum rtx_code code = GET_CODE (x);
8088 int next_select = just_select || code == XOR || code == NOT || code == NEG;
8089 enum machine_mode op_mode;
8090 unsigned HOST_WIDE_INT fuller_mask, nonzero;
8093 /* If this is a CALL or ASM_OPERANDS, don't do anything. Some of the
8094 code below will do the wrong thing since the mode of such an
8095 expression is VOIDmode.
8097 Also do nothing if X is a CLOBBER; this can happen if X was
8098 the return value from a call to gen_lowpart. */
8099 if (code == CALL || code == ASM_OPERANDS || code == CLOBBER)
8102 /* We want to perform the operation is its present mode unless we know
8103 that the operation is valid in MODE, in which case we do the operation
8105 op_mode = ((GET_MODE_CLASS (mode) == GET_MODE_CLASS (GET_MODE (x))
8106 && have_insn_for (code, mode))
8107 ? mode : GET_MODE (x));
8109 /* It is not valid to do a right-shift in a narrower mode
8110 than the one it came in with. */
8111 if ((code == LSHIFTRT || code == ASHIFTRT)
8112 && GET_MODE_BITSIZE (mode) < GET_MODE_BITSIZE (GET_MODE (x)))
8113 op_mode = GET_MODE (x);
8115 /* Truncate MASK to fit OP_MODE. */
8117 mask &= GET_MODE_MASK (op_mode);
8119 /* When we have an arithmetic operation, or a shift whose count we
8120 do not know, we need to assume that all bits up to the highest-order
8121 bit in MASK will be needed. This is how we form such a mask. */
8122 if (mask & ((unsigned HOST_WIDE_INT) 1 << (HOST_BITS_PER_WIDE_INT - 1)))
8123 fuller_mask = ~(unsigned HOST_WIDE_INT) 0;
8125 fuller_mask = (((unsigned HOST_WIDE_INT) 1 << (floor_log2 (mask) + 1))
8128 /* Determine what bits of X are guaranteed to be (non)zero. */
8129 nonzero = nonzero_bits (x, mode);
8131 /* If none of the bits in X are needed, return a zero. */
8132 if (!just_select && (nonzero & mask) == 0 && !side_effects_p (x))
8135 /* If X is a CONST_INT, return a new one. Do this here since the
8136 test below will fail. */
8137 if (CONST_INT_P (x))
8139 if (SCALAR_INT_MODE_P (mode))
8140 return gen_int_mode (INTVAL (x) & mask, mode);
8143 x = GEN_INT (INTVAL (x) & mask);
8144 return gen_lowpart_common (mode, x);
8148 /* If X is narrower than MODE and we want all the bits in X's mode, just
8149 get X in the proper mode. */
8150 if (GET_MODE_SIZE (GET_MODE (x)) < GET_MODE_SIZE (mode)
8151 && (GET_MODE_MASK (GET_MODE (x)) & ~mask) == 0)
8152 return gen_lowpart (mode, x);
8154 /* We can ignore the effect of a SUBREG if it narrows the mode or
8155 if the constant masks to zero all the bits the mode doesn't have. */
8156 if (GET_CODE (x) == SUBREG
8157 && subreg_lowpart_p (x)
8158 && ((GET_MODE_SIZE (GET_MODE (x))
8159 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
8161 & GET_MODE_MASK (GET_MODE (x))
8162 & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (x)))))))
8163 return force_to_mode (SUBREG_REG (x), mode, mask, next_select);
8165 /* The arithmetic simplifications here only work for scalar integer modes. */
8166 if (!SCALAR_INT_MODE_P (mode) || !SCALAR_INT_MODE_P (GET_MODE (x)))
8167 return gen_lowpart_or_truncate (mode, x);
8172 /* If X is a (clobber (const_int)), return it since we know we are
8173 generating something that won't match. */
8180 x = expand_compound_operation (x);
8181 if (GET_CODE (x) != code)
8182 return force_to_mode (x, mode, mask, next_select);
8186 /* Similarly for a truncate. */
8187 return force_to_mode (XEXP (x, 0), mode, mask, next_select);
8190 /* If this is an AND with a constant, convert it into an AND
8191 whose constant is the AND of that constant with MASK. If it
8192 remains an AND of MASK, delete it since it is redundant. */
8194 if (CONST_INT_P (XEXP (x, 1)))
8196 x = simplify_and_const_int (x, op_mode, XEXP (x, 0),
8197 mask & INTVAL (XEXP (x, 1)));
8199 /* If X is still an AND, see if it is an AND with a mask that
8200 is just some low-order bits. If so, and it is MASK, we don't
8203 if (GET_CODE (x) == AND && CONST_INT_P (XEXP (x, 1))
8204 && ((INTVAL (XEXP (x, 1)) & GET_MODE_MASK (GET_MODE (x)))
8208 /* If it remains an AND, try making another AND with the bits
8209 in the mode mask that aren't in MASK turned on. If the
8210 constant in the AND is wide enough, this might make a
8211 cheaper constant. */
8213 if (GET_CODE (x) == AND && CONST_INT_P (XEXP (x, 1))
8214 && GET_MODE_MASK (GET_MODE (x)) != mask
8215 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT)
8217 unsigned HOST_WIDE_INT cval
8218 = UINTVAL (XEXP (x, 1))
8219 | (GET_MODE_MASK (GET_MODE (x)) & ~mask);
8220 int width = GET_MODE_BITSIZE (GET_MODE (x));
8223 /* If MODE is narrower than HOST_WIDE_INT and CVAL is a negative
8224 number, sign extend it. */
8225 if (width > 0 && width < HOST_BITS_PER_WIDE_INT
8226 && (cval & ((unsigned HOST_WIDE_INT) 1 << (width - 1))) != 0)
8227 cval |= (unsigned HOST_WIDE_INT) -1 << width;
8229 y = simplify_gen_binary (AND, GET_MODE (x),
8230 XEXP (x, 0), GEN_INT (cval));
8231 if (rtx_cost (y, SET, optimize_this_for_speed_p)
8232 < rtx_cost (x, SET, optimize_this_for_speed_p))
8242 /* In (and (plus FOO C1) M), if M is a mask that just turns off
8243 low-order bits (as in an alignment operation) and FOO is already
8244 aligned to that boundary, mask C1 to that boundary as well.
8245 This may eliminate that PLUS and, later, the AND. */
8248 unsigned int width = GET_MODE_BITSIZE (mode);
8249 unsigned HOST_WIDE_INT smask = mask;
8251 /* If MODE is narrower than HOST_WIDE_INT and mask is a negative
8252 number, sign extend it. */
8254 if (width < HOST_BITS_PER_WIDE_INT
8255 && (smask & ((unsigned HOST_WIDE_INT) 1 << (width - 1))) != 0)
8256 smask |= (unsigned HOST_WIDE_INT) (-1) << width;
8258 if (CONST_INT_P (XEXP (x, 1))
8259 && exact_log2 (- smask) >= 0
8260 && (nonzero_bits (XEXP (x, 0), mode) & ~smask) == 0
8261 && (INTVAL (XEXP (x, 1)) & ~smask) != 0)
8262 return force_to_mode (plus_constant (XEXP (x, 0),
8263 (INTVAL (XEXP (x, 1)) & smask)),
8264 mode, smask, next_select);
8267 /* ... fall through ... */
8270 /* For PLUS, MINUS and MULT, we need any bits less significant than the
8271 most significant bit in MASK since carries from those bits will
8272 affect the bits we are interested in. */
8277 /* If X is (minus C Y) where C's least set bit is larger than any bit
8278 in the mask, then we may replace with (neg Y). */
8279 if (CONST_INT_P (XEXP (x, 0))
8280 && (((unsigned HOST_WIDE_INT) (INTVAL (XEXP (x, 0))
8281 & -INTVAL (XEXP (x, 0))))
8284 x = simplify_gen_unary (NEG, GET_MODE (x), XEXP (x, 1),
8286 return force_to_mode (x, mode, mask, next_select);
8289 /* Similarly, if C contains every bit in the fuller_mask, then we may
8290 replace with (not Y). */
8291 if (CONST_INT_P (XEXP (x, 0))
8292 && ((UINTVAL (XEXP (x, 0)) | fuller_mask) == UINTVAL (XEXP (x, 0))))
8294 x = simplify_gen_unary (NOT, GET_MODE (x),
8295 XEXP (x, 1), GET_MODE (x));
8296 return force_to_mode (x, mode, mask, next_select);
8304 /* If X is (ior (lshiftrt FOO C1) C2), try to commute the IOR and
8305 LSHIFTRT so we end up with an (and (lshiftrt (ior ...) ...) ...)
8306 operation which may be a bitfield extraction. Ensure that the
8307 constant we form is not wider than the mode of X. */
8309 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
8310 && CONST_INT_P (XEXP (XEXP (x, 0), 1))
8311 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
8312 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT
8313 && CONST_INT_P (XEXP (x, 1))
8314 && ((INTVAL (XEXP (XEXP (x, 0), 1))
8315 + floor_log2 (INTVAL (XEXP (x, 1))))
8316 < GET_MODE_BITSIZE (GET_MODE (x)))
8317 && (UINTVAL (XEXP (x, 1))
8318 & ~nonzero_bits (XEXP (x, 0), GET_MODE (x))) == 0)
8320 temp = GEN_INT ((INTVAL (XEXP (x, 1)) & mask)
8321 << INTVAL (XEXP (XEXP (x, 0), 1)));
8322 temp = simplify_gen_binary (GET_CODE (x), GET_MODE (x),
8323 XEXP (XEXP (x, 0), 0), temp);
8324 x = simplify_gen_binary (LSHIFTRT, GET_MODE (x), temp,
8325 XEXP (XEXP (x, 0), 1));
8326 return force_to_mode (x, mode, mask, next_select);
8330 /* For most binary operations, just propagate into the operation and
8331 change the mode if we have an operation of that mode. */
8333 op0 = force_to_mode (XEXP (x, 0), mode, mask, next_select);
8334 op1 = force_to_mode (XEXP (x, 1), mode, mask, next_select);
8336 /* If we ended up truncating both operands, truncate the result of the
8337 operation instead. */
8338 if (GET_CODE (op0) == TRUNCATE
8339 && GET_CODE (op1) == TRUNCATE)
8341 op0 = XEXP (op0, 0);
8342 op1 = XEXP (op1, 0);
8345 op0 = gen_lowpart_or_truncate (op_mode, op0);
8346 op1 = gen_lowpart_or_truncate (op_mode, op1);
8348 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
8349 x = simplify_gen_binary (code, op_mode, op0, op1);
8353 /* For left shifts, do the same, but just for the first operand.
8354 However, we cannot do anything with shifts where we cannot
8355 guarantee that the counts are smaller than the size of the mode
8356 because such a count will have a different meaning in a
8359 if (! (CONST_INT_P (XEXP (x, 1))
8360 && INTVAL (XEXP (x, 1)) >= 0
8361 && INTVAL (XEXP (x, 1)) < GET_MODE_BITSIZE (mode))
8362 && ! (GET_MODE (XEXP (x, 1)) != VOIDmode
8363 && (nonzero_bits (XEXP (x, 1), GET_MODE (XEXP (x, 1)))
8364 < (unsigned HOST_WIDE_INT) GET_MODE_BITSIZE (mode))))
8367 /* If the shift count is a constant and we can do arithmetic in
8368 the mode of the shift, refine which bits we need. Otherwise, use the
8369 conservative form of the mask. */
8370 if (CONST_INT_P (XEXP (x, 1))
8371 && INTVAL (XEXP (x, 1)) >= 0
8372 && INTVAL (XEXP (x, 1)) < GET_MODE_BITSIZE (op_mode)
8373 && GET_MODE_BITSIZE (op_mode) <= HOST_BITS_PER_WIDE_INT)
8374 mask >>= INTVAL (XEXP (x, 1));
8378 op0 = gen_lowpart_or_truncate (op_mode,
8379 force_to_mode (XEXP (x, 0), op_mode,
8380 mask, next_select));
8382 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0))
8383 x = simplify_gen_binary (code, op_mode, op0, XEXP (x, 1));
8387 /* Here we can only do something if the shift count is a constant,
8388 this shift constant is valid for the host, and we can do arithmetic
8391 if (CONST_INT_P (XEXP (x, 1))
8392 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT
8393 && GET_MODE_BITSIZE (op_mode) <= HOST_BITS_PER_WIDE_INT)
8395 rtx inner = XEXP (x, 0);
8396 unsigned HOST_WIDE_INT inner_mask;
8398 /* Select the mask of the bits we need for the shift operand. */
8399 inner_mask = mask << INTVAL (XEXP (x, 1));
8401 /* We can only change the mode of the shift if we can do arithmetic
8402 in the mode of the shift and INNER_MASK is no wider than the
8403 width of X's mode. */
8404 if ((inner_mask & ~GET_MODE_MASK (GET_MODE (x))) != 0)
8405 op_mode = GET_MODE (x);
8407 inner = force_to_mode (inner, op_mode, inner_mask, next_select);
8409 if (GET_MODE (x) != op_mode || inner != XEXP (x, 0))
8410 x = simplify_gen_binary (LSHIFTRT, op_mode, inner, XEXP (x, 1));
8413 /* If we have (and (lshiftrt FOO C1) C2) where the combination of the
8414 shift and AND produces only copies of the sign bit (C2 is one less
8415 than a power of two), we can do this with just a shift. */
8417 if (GET_CODE (x) == LSHIFTRT
8418 && CONST_INT_P (XEXP (x, 1))
8419 /* The shift puts one of the sign bit copies in the least significant
8421 && ((INTVAL (XEXP (x, 1))
8422 + num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0))))
8423 >= GET_MODE_BITSIZE (GET_MODE (x)))
8424 && exact_log2 (mask + 1) >= 0
8425 /* Number of bits left after the shift must be more than the mask
8427 && ((INTVAL (XEXP (x, 1)) + exact_log2 (mask + 1))
8428 <= GET_MODE_BITSIZE (GET_MODE (x)))
8429 /* Must be more sign bit copies than the mask needs. */
8430 && ((int) num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
8431 >= exact_log2 (mask + 1)))
8432 x = simplify_gen_binary (LSHIFTRT, GET_MODE (x), XEXP (x, 0),
8433 GEN_INT (GET_MODE_BITSIZE (GET_MODE (x))
8434 - exact_log2 (mask + 1)));
8439 /* If we are just looking for the sign bit, we don't need this shift at
8440 all, even if it has a variable count. */
8441 if (val_signbit_p (GET_MODE (x), mask))
8442 return force_to_mode (XEXP (x, 0), mode, mask, next_select);
8444 /* If this is a shift by a constant, get a mask that contains those bits
8445 that are not copies of the sign bit. We then have two cases: If
8446 MASK only includes those bits, this can be a logical shift, which may
8447 allow simplifications. If MASK is a single-bit field not within
8448 those bits, we are requesting a copy of the sign bit and hence can
8449 shift the sign bit to the appropriate location. */
8451 if (CONST_INT_P (XEXP (x, 1)) && INTVAL (XEXP (x, 1)) >= 0
8452 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT)
8456 /* If the considered data is wider than HOST_WIDE_INT, we can't
8457 represent a mask for all its bits in a single scalar.
8458 But we only care about the lower bits, so calculate these. */
8460 if (GET_MODE_BITSIZE (GET_MODE (x)) > HOST_BITS_PER_WIDE_INT)
8462 nonzero = ~(unsigned HOST_WIDE_INT) 0;
8464 /* GET_MODE_BITSIZE (GET_MODE (x)) - INTVAL (XEXP (x, 1))
8465 is the number of bits a full-width mask would have set.
8466 We need only shift if these are fewer than nonzero can
8467 hold. If not, we must keep all bits set in nonzero. */
8469 if (GET_MODE_BITSIZE (GET_MODE (x)) - INTVAL (XEXP (x, 1))
8470 < HOST_BITS_PER_WIDE_INT)
8471 nonzero >>= INTVAL (XEXP (x, 1))
8472 + HOST_BITS_PER_WIDE_INT
8473 - GET_MODE_BITSIZE (GET_MODE (x)) ;
8477 nonzero = GET_MODE_MASK (GET_MODE (x));
8478 nonzero >>= INTVAL (XEXP (x, 1));
8481 if ((mask & ~nonzero) == 0)
8483 x = simplify_shift_const (NULL_RTX, LSHIFTRT, GET_MODE (x),
8484 XEXP (x, 0), INTVAL (XEXP (x, 1)));
8485 if (GET_CODE (x) != ASHIFTRT)
8486 return force_to_mode (x, mode, mask, next_select);
8489 else if ((i = exact_log2 (mask)) >= 0)
8491 x = simplify_shift_const
8492 (NULL_RTX, LSHIFTRT, GET_MODE (x), XEXP (x, 0),
8493 GET_MODE_BITSIZE (GET_MODE (x)) - 1 - i);
8495 if (GET_CODE (x) != ASHIFTRT)
8496 return force_to_mode (x, mode, mask, next_select);
8500 /* If MASK is 1, convert this to an LSHIFTRT. This can be done
8501 even if the shift count isn't a constant. */
8503 x = simplify_gen_binary (LSHIFTRT, GET_MODE (x),
8504 XEXP (x, 0), XEXP (x, 1));
8508 /* If this is a zero- or sign-extension operation that just affects bits
8509 we don't care about, remove it. Be sure the call above returned
8510 something that is still a shift. */
8512 if ((GET_CODE (x) == LSHIFTRT || GET_CODE (x) == ASHIFTRT)
8513 && CONST_INT_P (XEXP (x, 1))
8514 && INTVAL (XEXP (x, 1)) >= 0
8515 && (INTVAL (XEXP (x, 1))
8516 <= GET_MODE_BITSIZE (GET_MODE (x)) - (floor_log2 (mask) + 1))
8517 && GET_CODE (XEXP (x, 0)) == ASHIFT
8518 && XEXP (XEXP (x, 0), 1) == XEXP (x, 1))
8519 return force_to_mode (XEXP (XEXP (x, 0), 0), mode, mask,
8526 /* If the shift count is constant and we can do computations
8527 in the mode of X, compute where the bits we care about are.
8528 Otherwise, we can't do anything. Don't change the mode of
8529 the shift or propagate MODE into the shift, though. */
8530 if (CONST_INT_P (XEXP (x, 1))
8531 && INTVAL (XEXP (x, 1)) >= 0)
8533 temp = simplify_binary_operation (code == ROTATE ? ROTATERT : ROTATE,
8534 GET_MODE (x), GEN_INT (mask),
8536 if (temp && CONST_INT_P (temp))
8538 force_to_mode (XEXP (x, 0), GET_MODE (x),
8539 INTVAL (temp), next_select));
8544 /* If we just want the low-order bit, the NEG isn't needed since it
8545 won't change the low-order bit. */
8547 return force_to_mode (XEXP (x, 0), mode, mask, just_select);
8549 /* We need any bits less significant than the most significant bit in
8550 MASK since carries from those bits will affect the bits we are
8556 /* (not FOO) is (xor FOO CONST), so if FOO is an LSHIFTRT, we can do the
8557 same as the XOR case above. Ensure that the constant we form is not
8558 wider than the mode of X. */
8560 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
8561 && CONST_INT_P (XEXP (XEXP (x, 0), 1))
8562 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
8563 && (INTVAL (XEXP (XEXP (x, 0), 1)) + floor_log2 (mask)
8564 < GET_MODE_BITSIZE (GET_MODE (x)))
8565 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT)
8567 temp = gen_int_mode (mask << INTVAL (XEXP (XEXP (x, 0), 1)),
8569 temp = simplify_gen_binary (XOR, GET_MODE (x),
8570 XEXP (XEXP (x, 0), 0), temp);
8571 x = simplify_gen_binary (LSHIFTRT, GET_MODE (x),
8572 temp, XEXP (XEXP (x, 0), 1));
8574 return force_to_mode (x, mode, mask, next_select);
8577 /* (and (not FOO) CONST) is (not (or FOO (not CONST))), so we must
8578 use the full mask inside the NOT. */
8582 op0 = gen_lowpart_or_truncate (op_mode,
8583 force_to_mode (XEXP (x, 0), mode, mask,
8585 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0))
8586 x = simplify_gen_unary (code, op_mode, op0, op_mode);
8590 /* (and (ne FOO 0) CONST) can be (and FOO CONST) if CONST is included
8591 in STORE_FLAG_VALUE and FOO has a single bit that might be nonzero,
8592 which is equal to STORE_FLAG_VALUE. */
8593 if ((mask & ~STORE_FLAG_VALUE) == 0
8594 && XEXP (x, 1) == const0_rtx
8595 && GET_MODE (XEXP (x, 0)) == mode
8596 && exact_log2 (nonzero_bits (XEXP (x, 0), mode)) >= 0
8597 && (nonzero_bits (XEXP (x, 0), mode)
8598 == (unsigned HOST_WIDE_INT) STORE_FLAG_VALUE))
8599 return force_to_mode (XEXP (x, 0), mode, mask, next_select);
8604 /* We have no way of knowing if the IF_THEN_ELSE can itself be
8605 written in a narrower mode. We play it safe and do not do so. */
8608 gen_lowpart_or_truncate (GET_MODE (x),
8609 force_to_mode (XEXP (x, 1), mode,
8610 mask, next_select)));
8612 gen_lowpart_or_truncate (GET_MODE (x),
8613 force_to_mode (XEXP (x, 2), mode,
8614 mask, next_select)));
8621 /* Ensure we return a value of the proper mode. */
8622 return gen_lowpart_or_truncate (mode, x);
8625 /* Return nonzero if X is an expression that has one of two values depending on
8626 whether some other value is zero or nonzero. In that case, we return the
8627 value that is being tested, *PTRUE is set to the value if the rtx being
8628 returned has a nonzero value, and *PFALSE is set to the other alternative.
8630 If we return zero, we set *PTRUE and *PFALSE to X. */
8633 if_then_else_cond (rtx x, rtx *ptrue, rtx *pfalse)
8635 enum machine_mode mode = GET_MODE (x);
8636 enum rtx_code code = GET_CODE (x);
8637 rtx cond0, cond1, true0, true1, false0, false1;
8638 unsigned HOST_WIDE_INT nz;
8640 /* If we are comparing a value against zero, we are done. */
8641 if ((code == NE || code == EQ)
8642 && XEXP (x, 1) == const0_rtx)
8644 *ptrue = (code == NE) ? const_true_rtx : const0_rtx;
8645 *pfalse = (code == NE) ? const0_rtx : const_true_rtx;
8649 /* If this is a unary operation whose operand has one of two values, apply
8650 our opcode to compute those values. */
8651 else if (UNARY_P (x)
8652 && (cond0 = if_then_else_cond (XEXP (x, 0), &true0, &false0)) != 0)
8654 *ptrue = simplify_gen_unary (code, mode, true0, GET_MODE (XEXP (x, 0)));
8655 *pfalse = simplify_gen_unary (code, mode, false0,
8656 GET_MODE (XEXP (x, 0)));
8660 /* If this is a COMPARE, do nothing, since the IF_THEN_ELSE we would
8661 make can't possibly match and would suppress other optimizations. */
8662 else if (code == COMPARE)
8665 /* If this is a binary operation, see if either side has only one of two
8666 values. If either one does or if both do and they are conditional on
8667 the same value, compute the new true and false values. */
8668 else if (BINARY_P (x))
8670 cond0 = if_then_else_cond (XEXP (x, 0), &true0, &false0);
8671 cond1 = if_then_else_cond (XEXP (x, 1), &true1, &false1);
8673 if ((cond0 != 0 || cond1 != 0)
8674 && ! (cond0 != 0 && cond1 != 0 && ! rtx_equal_p (cond0, cond1)))
8676 /* If if_then_else_cond returned zero, then true/false are the
8677 same rtl. We must copy one of them to prevent invalid rtl
8680 true0 = copy_rtx (true0);
8681 else if (cond1 == 0)
8682 true1 = copy_rtx (true1);
8684 if (COMPARISON_P (x))
8686 *ptrue = simplify_gen_relational (code, mode, VOIDmode,
8688 *pfalse = simplify_gen_relational (code, mode, VOIDmode,
8693 *ptrue = simplify_gen_binary (code, mode, true0, true1);
8694 *pfalse = simplify_gen_binary (code, mode, false0, false1);
8697 return cond0 ? cond0 : cond1;
8700 /* See if we have PLUS, IOR, XOR, MINUS or UMAX, where one of the
8701 operands is zero when the other is nonzero, and vice-versa,
8702 and STORE_FLAG_VALUE is 1 or -1. */
8704 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
8705 && (code == PLUS || code == IOR || code == XOR || code == MINUS
8707 && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT)
8709 rtx op0 = XEXP (XEXP (x, 0), 1);
8710 rtx op1 = XEXP (XEXP (x, 1), 1);
8712 cond0 = XEXP (XEXP (x, 0), 0);
8713 cond1 = XEXP (XEXP (x, 1), 0);
8715 if (COMPARISON_P (cond0)
8716 && COMPARISON_P (cond1)
8717 && ((GET_CODE (cond0) == reversed_comparison_code (cond1, NULL)
8718 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0))
8719 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1)))
8720 || ((swap_condition (GET_CODE (cond0))
8721 == reversed_comparison_code (cond1, NULL))
8722 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1))
8723 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0))))
8724 && ! side_effects_p (x))
8726 *ptrue = simplify_gen_binary (MULT, mode, op0, const_true_rtx);
8727 *pfalse = simplify_gen_binary (MULT, mode,
8729 ? simplify_gen_unary (NEG, mode,
8737 /* Similarly for MULT, AND and UMIN, except that for these the result
8739 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
8740 && (code == MULT || code == AND || code == UMIN)
8741 && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT)
8743 cond0 = XEXP (XEXP (x, 0), 0);
8744 cond1 = XEXP (XEXP (x, 1), 0);
8746 if (COMPARISON_P (cond0)
8747 && COMPARISON_P (cond1)
8748 && ((GET_CODE (cond0) == reversed_comparison_code (cond1, NULL)
8749 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0))
8750 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1)))
8751 || ((swap_condition (GET_CODE (cond0))
8752 == reversed_comparison_code (cond1, NULL))
8753 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1))
8754 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0))))
8755 && ! side_effects_p (x))
8757 *ptrue = *pfalse = const0_rtx;
8763 else if (code == IF_THEN_ELSE)
8765 /* If we have IF_THEN_ELSE already, extract the condition and
8766 canonicalize it if it is NE or EQ. */
8767 cond0 = XEXP (x, 0);
8768 *ptrue = XEXP (x, 1), *pfalse = XEXP (x, 2);
8769 if (GET_CODE (cond0) == NE && XEXP (cond0, 1) == const0_rtx)
8770 return XEXP (cond0, 0);
8771 else if (GET_CODE (cond0) == EQ && XEXP (cond0, 1) == const0_rtx)
8773 *ptrue = XEXP (x, 2), *pfalse = XEXP (x, 1);
8774 return XEXP (cond0, 0);
8780 /* If X is a SUBREG, we can narrow both the true and false values
8781 if the inner expression, if there is a condition. */
8782 else if (code == SUBREG
8783 && 0 != (cond0 = if_then_else_cond (SUBREG_REG (x),
8786 true0 = simplify_gen_subreg (mode, true0,
8787 GET_MODE (SUBREG_REG (x)), SUBREG_BYTE (x));
8788 false0 = simplify_gen_subreg (mode, false0,
8789 GET_MODE (SUBREG_REG (x)), SUBREG_BYTE (x));
8790 if (true0 && false0)
8798 /* If X is a constant, this isn't special and will cause confusions
8799 if we treat it as such. Likewise if it is equivalent to a constant. */
8800 else if (CONSTANT_P (x)
8801 || ((cond0 = get_last_value (x)) != 0 && CONSTANT_P (cond0)))
8804 /* If we're in BImode, canonicalize on 0 and STORE_FLAG_VALUE, as that
8805 will be least confusing to the rest of the compiler. */
8806 else if (mode == BImode)
8808 *ptrue = GEN_INT (STORE_FLAG_VALUE), *pfalse = const0_rtx;
8812 /* If X is known to be either 0 or -1, those are the true and
8813 false values when testing X. */
8814 else if (x == constm1_rtx || x == const0_rtx
8815 || (mode != VOIDmode
8816 && num_sign_bit_copies (x, mode) == GET_MODE_BITSIZE (mode)))
8818 *ptrue = constm1_rtx, *pfalse = const0_rtx;
8822 /* Likewise for 0 or a single bit. */
8823 else if (SCALAR_INT_MODE_P (mode)
8824 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
8825 && exact_log2 (nz = nonzero_bits (x, mode)) >= 0)
8827 *ptrue = gen_int_mode (nz, mode), *pfalse = const0_rtx;
8831 /* Otherwise fail; show no condition with true and false values the same. */
8832 *ptrue = *pfalse = x;
8836 /* Return the value of expression X given the fact that condition COND
8837 is known to be true when applied to REG as its first operand and VAL
8838 as its second. X is known to not be shared and so can be modified in
8841 We only handle the simplest cases, and specifically those cases that
8842 arise with IF_THEN_ELSE expressions. */
8845 known_cond (rtx x, enum rtx_code cond, rtx reg, rtx val)
8847 enum rtx_code code = GET_CODE (x);
8852 if (side_effects_p (x))
8855 /* If either operand of the condition is a floating point value,
8856 then we have to avoid collapsing an EQ comparison. */
8858 && rtx_equal_p (x, reg)
8859 && ! FLOAT_MODE_P (GET_MODE (x))
8860 && ! FLOAT_MODE_P (GET_MODE (val)))
8863 if (cond == UNEQ && rtx_equal_p (x, reg))
8866 /* If X is (abs REG) and we know something about REG's relationship
8867 with zero, we may be able to simplify this. */
8869 if (code == ABS && rtx_equal_p (XEXP (x, 0), reg) && val == const0_rtx)
8872 case GE: case GT: case EQ:
8875 return simplify_gen_unary (NEG, GET_MODE (XEXP (x, 0)),
8877 GET_MODE (XEXP (x, 0)));
8882 /* The only other cases we handle are MIN, MAX, and comparisons if the
8883 operands are the same as REG and VAL. */
8885 else if (COMPARISON_P (x) || COMMUTATIVE_ARITH_P (x))
8887 if (rtx_equal_p (XEXP (x, 0), val))
8888 cond = swap_condition (cond), temp = val, val = reg, reg = temp;
8890 if (rtx_equal_p (XEXP (x, 0), reg) && rtx_equal_p (XEXP (x, 1), val))
8892 if (COMPARISON_P (x))
8894 if (comparison_dominates_p (cond, code))
8895 return const_true_rtx;
8897 code = reversed_comparison_code (x, NULL);
8899 && comparison_dominates_p (cond, code))
8904 else if (code == SMAX || code == SMIN
8905 || code == UMIN || code == UMAX)
8907 int unsignedp = (code == UMIN || code == UMAX);
8909 /* Do not reverse the condition when it is NE or EQ.
8910 This is because we cannot conclude anything about
8911 the value of 'SMAX (x, y)' when x is not equal to y,
8912 but we can when x equals y. */
8913 if ((code == SMAX || code == UMAX)
8914 && ! (cond == EQ || cond == NE))
8915 cond = reverse_condition (cond);
8920 return unsignedp ? x : XEXP (x, 1);
8922 return unsignedp ? x : XEXP (x, 0);
8924 return unsignedp ? XEXP (x, 1) : x;
8926 return unsignedp ? XEXP (x, 0) : x;
8933 else if (code == SUBREG)
8935 enum machine_mode inner_mode = GET_MODE (SUBREG_REG (x));
8936 rtx new_rtx, r = known_cond (SUBREG_REG (x), cond, reg, val);
8938 if (SUBREG_REG (x) != r)
8940 /* We must simplify subreg here, before we lose track of the
8941 original inner_mode. */
8942 new_rtx = simplify_subreg (GET_MODE (x), r,
8943 inner_mode, SUBREG_BYTE (x));
8947 SUBST (SUBREG_REG (x), r);
8952 /* We don't have to handle SIGN_EXTEND here, because even in the
8953 case of replacing something with a modeless CONST_INT, a
8954 CONST_INT is already (supposed to be) a valid sign extension for
8955 its narrower mode, which implies it's already properly
8956 sign-extended for the wider mode. Now, for ZERO_EXTEND, the
8957 story is different. */
8958 else if (code == ZERO_EXTEND)
8960 enum machine_mode inner_mode = GET_MODE (XEXP (x, 0));
8961 rtx new_rtx, r = known_cond (XEXP (x, 0), cond, reg, val);
8963 if (XEXP (x, 0) != r)
8965 /* We must simplify the zero_extend here, before we lose
8966 track of the original inner_mode. */
8967 new_rtx = simplify_unary_operation (ZERO_EXTEND, GET_MODE (x),
8972 SUBST (XEXP (x, 0), r);
8978 fmt = GET_RTX_FORMAT (code);
8979 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
8982 SUBST (XEXP (x, i), known_cond (XEXP (x, i), cond, reg, val));
8983 else if (fmt[i] == 'E')
8984 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
8985 SUBST (XVECEXP (x, i, j), known_cond (XVECEXP (x, i, j),
8992 /* See if X and Y are equal for the purposes of seeing if we can rewrite an
8993 assignment as a field assignment. */
8996 rtx_equal_for_field_assignment_p (rtx x, rtx y)
8998 if (x == y || rtx_equal_p (x, y))
9001 if (x == 0 || y == 0 || GET_MODE (x) != GET_MODE (y))
9004 /* Check for a paradoxical SUBREG of a MEM compared with the MEM.
9005 Note that all SUBREGs of MEM are paradoxical; otherwise they
9006 would have been rewritten. */
9007 if (MEM_P (x) && GET_CODE (y) == SUBREG
9008 && MEM_P (SUBREG_REG (y))
9009 && rtx_equal_p (SUBREG_REG (y),
9010 gen_lowpart (GET_MODE (SUBREG_REG (y)), x)))
9013 if (MEM_P (y) && GET_CODE (x) == SUBREG
9014 && MEM_P (SUBREG_REG (x))
9015 && rtx_equal_p (SUBREG_REG (x),
9016 gen_lowpart (GET_MODE (SUBREG_REG (x)), y)))
9019 /* We used to see if get_last_value of X and Y were the same but that's
9020 not correct. In one direction, we'll cause the assignment to have
9021 the wrong destination and in the case, we'll import a register into this
9022 insn that might have already have been dead. So fail if none of the
9023 above cases are true. */
9027 /* See if X, a SET operation, can be rewritten as a bit-field assignment.
9028 Return that assignment if so.
9030 We only handle the most common cases. */
9033 make_field_assignment (rtx x)
9035 rtx dest = SET_DEST (x);
9036 rtx src = SET_SRC (x);
9041 unsigned HOST_WIDE_INT len;
9043 enum machine_mode mode;
9045 /* If SRC was (and (not (ashift (const_int 1) POS)) DEST), this is
9046 a clear of a one-bit field. We will have changed it to
9047 (and (rotate (const_int -2) POS) DEST), so check for that. Also check
9050 if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == ROTATE
9051 && CONST_INT_P (XEXP (XEXP (src, 0), 0))
9052 && INTVAL (XEXP (XEXP (src, 0), 0)) == -2
9053 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
9055 assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1),
9058 return gen_rtx_SET (VOIDmode, assign, const0_rtx);
9062 if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == SUBREG
9063 && subreg_lowpart_p (XEXP (src, 0))
9064 && (GET_MODE_SIZE (GET_MODE (XEXP (src, 0)))
9065 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (src, 0)))))
9066 && GET_CODE (SUBREG_REG (XEXP (src, 0))) == ROTATE
9067 && CONST_INT_P (XEXP (SUBREG_REG (XEXP (src, 0)), 0))
9068 && INTVAL (XEXP (SUBREG_REG (XEXP (src, 0)), 0)) == -2
9069 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
9071 assign = make_extraction (VOIDmode, dest, 0,
9072 XEXP (SUBREG_REG (XEXP (src, 0)), 1),
9075 return gen_rtx_SET (VOIDmode, assign, const0_rtx);
9079 /* If SRC is (ior (ashift (const_int 1) POS) DEST), this is a set of a
9081 if (GET_CODE (src) == IOR && GET_CODE (XEXP (src, 0)) == ASHIFT
9082 && XEXP (XEXP (src, 0), 0) == const1_rtx
9083 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
9085 assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1),
9088 return gen_rtx_SET (VOIDmode, assign, const1_rtx);
9092 /* If DEST is already a field assignment, i.e. ZERO_EXTRACT, and the
9093 SRC is an AND with all bits of that field set, then we can discard
9095 if (GET_CODE (dest) == ZERO_EXTRACT
9096 && CONST_INT_P (XEXP (dest, 1))
9097 && GET_CODE (src) == AND
9098 && CONST_INT_P (XEXP (src, 1)))
9100 HOST_WIDE_INT width = INTVAL (XEXP (dest, 1));
9101 unsigned HOST_WIDE_INT and_mask = INTVAL (XEXP (src, 1));
9102 unsigned HOST_WIDE_INT ze_mask;
9104 if (width >= HOST_BITS_PER_WIDE_INT)
9107 ze_mask = ((unsigned HOST_WIDE_INT)1 << width) - 1;
9109 /* Complete overlap. We can remove the source AND. */
9110 if ((and_mask & ze_mask) == ze_mask)
9111 return gen_rtx_SET (VOIDmode, dest, XEXP (src, 0));
9113 /* Partial overlap. We can reduce the source AND. */
9114 if ((and_mask & ze_mask) != and_mask)
9116 mode = GET_MODE (src);
9117 src = gen_rtx_AND (mode, XEXP (src, 0),
9118 gen_int_mode (and_mask & ze_mask, mode));
9119 return gen_rtx_SET (VOIDmode, dest, src);
9123 /* The other case we handle is assignments into a constant-position
9124 field. They look like (ior/xor (and DEST C1) OTHER). If C1 represents
9125 a mask that has all one bits except for a group of zero bits and
9126 OTHER is known to have zeros where C1 has ones, this is such an
9127 assignment. Compute the position and length from C1. Shift OTHER
9128 to the appropriate position, force it to the required mode, and
9129 make the extraction. Check for the AND in both operands. */
9131 if (GET_CODE (src) != IOR && GET_CODE (src) != XOR)
9134 rhs = expand_compound_operation (XEXP (src, 0));
9135 lhs = expand_compound_operation (XEXP (src, 1));
9137 if (GET_CODE (rhs) == AND
9138 && CONST_INT_P (XEXP (rhs, 1))
9139 && rtx_equal_for_field_assignment_p (XEXP (rhs, 0), dest))
9140 c1 = INTVAL (XEXP (rhs, 1)), other = lhs;
9141 else if (GET_CODE (lhs) == AND
9142 && CONST_INT_P (XEXP (lhs, 1))
9143 && rtx_equal_for_field_assignment_p (XEXP (lhs, 0), dest))
9144 c1 = INTVAL (XEXP (lhs, 1)), other = rhs;
9148 pos = get_pos_from_mask ((~c1) & GET_MODE_MASK (GET_MODE (dest)), &len);
9149 if (pos < 0 || pos + len > GET_MODE_BITSIZE (GET_MODE (dest))
9150 || GET_MODE_BITSIZE (GET_MODE (dest)) > HOST_BITS_PER_WIDE_INT
9151 || (c1 & nonzero_bits (other, GET_MODE (dest))) != 0)
9154 assign = make_extraction (VOIDmode, dest, pos, NULL_RTX, len, 1, 1, 0);
9158 /* The mode to use for the source is the mode of the assignment, or of
9159 what is inside a possible STRICT_LOW_PART. */
9160 mode = (GET_CODE (assign) == STRICT_LOW_PART
9161 ? GET_MODE (XEXP (assign, 0)) : GET_MODE (assign));
9163 /* Shift OTHER right POS places and make it the source, restricting it
9164 to the proper length and mode. */
9166 src = canon_reg_for_combine (simplify_shift_const (NULL_RTX, LSHIFTRT,
9170 src = force_to_mode (src, mode,
9171 GET_MODE_BITSIZE (mode) >= HOST_BITS_PER_WIDE_INT
9172 ? ~(unsigned HOST_WIDE_INT) 0
9173 : ((unsigned HOST_WIDE_INT) 1 << len) - 1,
9176 /* If SRC is masked by an AND that does not make a difference in
9177 the value being stored, strip it. */
9178 if (GET_CODE (assign) == ZERO_EXTRACT
9179 && CONST_INT_P (XEXP (assign, 1))
9180 && INTVAL (XEXP (assign, 1)) < HOST_BITS_PER_WIDE_INT
9181 && GET_CODE (src) == AND
9182 && CONST_INT_P (XEXP (src, 1))
9183 && UINTVAL (XEXP (src, 1))
9184 == ((unsigned HOST_WIDE_INT) 1 << INTVAL (XEXP (assign, 1))) - 1)
9185 src = XEXP (src, 0);
9187 return gen_rtx_SET (VOIDmode, assign, src);
9190 /* See if X is of the form (+ (* a c) (* b c)) and convert to (* (+ a b) c)
9194 apply_distributive_law (rtx x)
9196 enum rtx_code code = GET_CODE (x);
9197 enum rtx_code inner_code;
9198 rtx lhs, rhs, other;
9201 /* Distributivity is not true for floating point as it can change the
9202 value. So we don't do it unless -funsafe-math-optimizations. */
9203 if (FLOAT_MODE_P (GET_MODE (x))
9204 && ! flag_unsafe_math_optimizations)
9207 /* The outer operation can only be one of the following: */
9208 if (code != IOR && code != AND && code != XOR
9209 && code != PLUS && code != MINUS)
9215 /* If either operand is a primitive we can't do anything, so get out
9217 if (OBJECT_P (lhs) || OBJECT_P (rhs))
9220 lhs = expand_compound_operation (lhs);
9221 rhs = expand_compound_operation (rhs);
9222 inner_code = GET_CODE (lhs);
9223 if (inner_code != GET_CODE (rhs))
9226 /* See if the inner and outer operations distribute. */
9233 /* These all distribute except over PLUS. */
9234 if (code == PLUS || code == MINUS)
9239 if (code != PLUS && code != MINUS)
9244 /* This is also a multiply, so it distributes over everything. */
9248 /* Non-paradoxical SUBREGs distributes over all operations,
9249 provided the inner modes and byte offsets are the same, this
9250 is an extraction of a low-order part, we don't convert an fp
9251 operation to int or vice versa, this is not a vector mode,
9252 and we would not be converting a single-word operation into a
9253 multi-word operation. The latter test is not required, but
9254 it prevents generating unneeded multi-word operations. Some
9255 of the previous tests are redundant given the latter test,
9256 but are retained because they are required for correctness.
9258 We produce the result slightly differently in this case. */
9260 if (GET_MODE (SUBREG_REG (lhs)) != GET_MODE (SUBREG_REG (rhs))
9261 || SUBREG_BYTE (lhs) != SUBREG_BYTE (rhs)
9262 || ! subreg_lowpart_p (lhs)
9263 || (GET_MODE_CLASS (GET_MODE (lhs))
9264 != GET_MODE_CLASS (GET_MODE (SUBREG_REG (lhs))))
9265 || (GET_MODE_SIZE (GET_MODE (lhs))
9266 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs))))
9267 || VECTOR_MODE_P (GET_MODE (lhs))
9268 || GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs))) > UNITS_PER_WORD
9269 /* Result might need to be truncated. Don't change mode if
9270 explicit truncation is needed. */
9271 || !TRULY_NOOP_TRUNCATION
9272 (GET_MODE_BITSIZE (GET_MODE (x)),
9273 GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (lhs)))))
9276 tem = simplify_gen_binary (code, GET_MODE (SUBREG_REG (lhs)),
9277 SUBREG_REG (lhs), SUBREG_REG (rhs));
9278 return gen_lowpart (GET_MODE (x), tem);
9284 /* Set LHS and RHS to the inner operands (A and B in the example
9285 above) and set OTHER to the common operand (C in the example).
9286 There is only one way to do this unless the inner operation is
9288 if (COMMUTATIVE_ARITH_P (lhs)
9289 && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 0)))
9290 other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 1);
9291 else if (COMMUTATIVE_ARITH_P (lhs)
9292 && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 1)))
9293 other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 0);
9294 else if (COMMUTATIVE_ARITH_P (lhs)
9295 && rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 0)))
9296 other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 1);
9297 else if (rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 1)))
9298 other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 0);
9302 /* Form the new inner operation, seeing if it simplifies first. */
9303 tem = simplify_gen_binary (code, GET_MODE (x), lhs, rhs);
9305 /* There is one exception to the general way of distributing:
9306 (a | c) ^ (b | c) -> (a ^ b) & ~c */
9307 if (code == XOR && inner_code == IOR)
9310 other = simplify_gen_unary (NOT, GET_MODE (x), other, GET_MODE (x));
9313 /* We may be able to continuing distributing the result, so call
9314 ourselves recursively on the inner operation before forming the
9315 outer operation, which we return. */
9316 return simplify_gen_binary (inner_code, GET_MODE (x),
9317 apply_distributive_law (tem), other);
9320 /* See if X is of the form (* (+ A B) C), and if so convert to
9321 (+ (* A C) (* B C)) and try to simplify.
9323 Most of the time, this results in no change. However, if some of
9324 the operands are the same or inverses of each other, simplifications
9327 For example, (and (ior A B) (not B)) can occur as the result of
9328 expanding a bit field assignment. When we apply the distributive
9329 law to this, we get (ior (and (A (not B))) (and (B (not B)))),
9330 which then simplifies to (and (A (not B))).
9332 Note that no checks happen on the validity of applying the inverse
9333 distributive law. This is pointless since we can do it in the
9334 few places where this routine is called.
9336 N is the index of the term that is decomposed (the arithmetic operation,
9337 i.e. (+ A B) in the first example above). !N is the index of the term that
9338 is distributed, i.e. of C in the first example above. */
9340 distribute_and_simplify_rtx (rtx x, int n)
9342 enum machine_mode mode;
9343 enum rtx_code outer_code, inner_code;
9344 rtx decomposed, distributed, inner_op0, inner_op1, new_op0, new_op1, tmp;
9346 /* Distributivity is not true for floating point as it can change the
9347 value. So we don't do it unless -funsafe-math-optimizations. */
9348 if (FLOAT_MODE_P (GET_MODE (x))
9349 && ! flag_unsafe_math_optimizations)
9352 decomposed = XEXP (x, n);
9353 if (!ARITHMETIC_P (decomposed))
9356 mode = GET_MODE (x);
9357 outer_code = GET_CODE (x);
9358 distributed = XEXP (x, !n);
9360 inner_code = GET_CODE (decomposed);
9361 inner_op0 = XEXP (decomposed, 0);
9362 inner_op1 = XEXP (decomposed, 1);
9364 /* Special case (and (xor B C) (not A)), which is equivalent to
9365 (xor (ior A B) (ior A C)) */
9366 if (outer_code == AND && inner_code == XOR && GET_CODE (distributed) == NOT)
9368 distributed = XEXP (distributed, 0);
9374 /* Distribute the second term. */
9375 new_op0 = simplify_gen_binary (outer_code, mode, inner_op0, distributed);
9376 new_op1 = simplify_gen_binary (outer_code, mode, inner_op1, distributed);
9380 /* Distribute the first term. */
9381 new_op0 = simplify_gen_binary (outer_code, mode, distributed, inner_op0);
9382 new_op1 = simplify_gen_binary (outer_code, mode, distributed, inner_op1);
9385 tmp = apply_distributive_law (simplify_gen_binary (inner_code, mode,
9387 if (GET_CODE (tmp) != outer_code
9388 && rtx_cost (tmp, SET, optimize_this_for_speed_p)
9389 < rtx_cost (x, SET, optimize_this_for_speed_p))
9395 /* Simplify a logical `and' of VAROP with the constant CONSTOP, to be done
9396 in MODE. Return an equivalent form, if different from (and VAROP
9397 (const_int CONSTOP)). Otherwise, return NULL_RTX. */
9400 simplify_and_const_int_1 (enum machine_mode mode, rtx varop,
9401 unsigned HOST_WIDE_INT constop)
9403 unsigned HOST_WIDE_INT nonzero;
9404 unsigned HOST_WIDE_INT orig_constop;
9409 orig_constop = constop;
9410 if (GET_CODE (varop) == CLOBBER)
9413 /* Simplify VAROP knowing that we will be only looking at some of the
9416 Note by passing in CONSTOP, we guarantee that the bits not set in
9417 CONSTOP are not significant and will never be examined. We must
9418 ensure that is the case by explicitly masking out those bits
9419 before returning. */
9420 varop = force_to_mode (varop, mode, constop, 0);
9422 /* If VAROP is a CLOBBER, we will fail so return it. */
9423 if (GET_CODE (varop) == CLOBBER)
9426 /* If VAROP is a CONST_INT, then we need to apply the mask in CONSTOP
9427 to VAROP and return the new constant. */
9428 if (CONST_INT_P (varop))
9429 return gen_int_mode (INTVAL (varop) & constop, mode);
9431 /* See what bits may be nonzero in VAROP. Unlike the general case of
9432 a call to nonzero_bits, here we don't care about bits outside
9435 nonzero = nonzero_bits (varop, mode) & GET_MODE_MASK (mode);
9437 /* Turn off all bits in the constant that are known to already be zero.
9438 Thus, if the AND isn't needed at all, we will have CONSTOP == NONZERO_BITS
9439 which is tested below. */
9443 /* If we don't have any bits left, return zero. */
9447 /* If VAROP is a NEG of something known to be zero or 1 and CONSTOP is
9448 a power of two, we can replace this with an ASHIFT. */
9449 if (GET_CODE (varop) == NEG && nonzero_bits (XEXP (varop, 0), mode) == 1
9450 && (i = exact_log2 (constop)) >= 0)
9451 return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (varop, 0), i);
9453 /* If VAROP is an IOR or XOR, apply the AND to both branches of the IOR
9454 or XOR, then try to apply the distributive law. This may eliminate
9455 operations if either branch can be simplified because of the AND.
9456 It may also make some cases more complex, but those cases probably
9457 won't match a pattern either with or without this. */
9459 if (GET_CODE (varop) == IOR || GET_CODE (varop) == XOR)
9463 apply_distributive_law
9464 (simplify_gen_binary (GET_CODE (varop), GET_MODE (varop),
9465 simplify_and_const_int (NULL_RTX,
9469 simplify_and_const_int (NULL_RTX,
9474 /* If VAROP is PLUS, and the constant is a mask of low bits, distribute
9475 the AND and see if one of the operands simplifies to zero. If so, we
9476 may eliminate it. */
9478 if (GET_CODE (varop) == PLUS
9479 && exact_log2 (constop + 1) >= 0)
9483 o0 = simplify_and_const_int (NULL_RTX, mode, XEXP (varop, 0), constop);
9484 o1 = simplify_and_const_int (NULL_RTX, mode, XEXP (varop, 1), constop);
9485 if (o0 == const0_rtx)
9487 if (o1 == const0_rtx)
9491 /* Make a SUBREG if necessary. If we can't make it, fail. */
9492 varop = gen_lowpart (mode, varop);
9493 if (varop == NULL_RTX || GET_CODE (varop) == CLOBBER)
9496 /* If we are only masking insignificant bits, return VAROP. */
9497 if (constop == nonzero)
9500 if (varop == orig_varop && constop == orig_constop)
9503 /* Otherwise, return an AND. */
9504 return simplify_gen_binary (AND, mode, varop, gen_int_mode (constop, mode));
9508 /* We have X, a logical `and' of VAROP with the constant CONSTOP, to be done
9511 Return an equivalent form, if different from X. Otherwise, return X. If
9512 X is zero, we are to always construct the equivalent form. */
9515 simplify_and_const_int (rtx x, enum machine_mode mode, rtx varop,
9516 unsigned HOST_WIDE_INT constop)
9518 rtx tem = simplify_and_const_int_1 (mode, varop, constop);
9523 x = simplify_gen_binary (AND, GET_MODE (varop), varop,
9524 gen_int_mode (constop, mode));
9525 if (GET_MODE (x) != mode)
9526 x = gen_lowpart (mode, x);
9530 /* Given a REG, X, compute which bits in X can be nonzero.
9531 We don't care about bits outside of those defined in MODE.
9533 For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is
9534 a shift, AND, or zero_extract, we can do better. */
9537 reg_nonzero_bits_for_combine (const_rtx x, enum machine_mode mode,
9538 const_rtx known_x ATTRIBUTE_UNUSED,
9539 enum machine_mode known_mode ATTRIBUTE_UNUSED,
9540 unsigned HOST_WIDE_INT known_ret ATTRIBUTE_UNUSED,
9541 unsigned HOST_WIDE_INT *nonzero)
9546 /* If X is a register whose nonzero bits value is current, use it.
9547 Otherwise, if X is a register whose value we can find, use that
9548 value. Otherwise, use the previously-computed global nonzero bits
9549 for this register. */
9551 rsp = VEC_index (reg_stat_type, reg_stat, REGNO (x));
9552 if (rsp->last_set_value != 0
9553 && (rsp->last_set_mode == mode
9554 || (GET_MODE_CLASS (rsp->last_set_mode) == MODE_INT
9555 && GET_MODE_CLASS (mode) == MODE_INT))
9556 && ((rsp->last_set_label >= label_tick_ebb_start
9557 && rsp->last_set_label < label_tick)
9558 || (rsp->last_set_label == label_tick
9559 && DF_INSN_LUID (rsp->last_set) < subst_low_luid)
9560 || (REGNO (x) >= FIRST_PSEUDO_REGISTER
9561 && REG_N_SETS (REGNO (x)) == 1
9563 (DF_LR_IN (ENTRY_BLOCK_PTR->next_bb), REGNO (x)))))
9565 *nonzero &= rsp->last_set_nonzero_bits;
9569 tem = get_last_value (x);
9573 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
9574 /* If X is narrower than MODE and TEM is a non-negative
9575 constant that would appear negative in the mode of X,
9576 sign-extend it for use in reg_nonzero_bits because some
9577 machines (maybe most) will actually do the sign-extension
9578 and this is the conservative approach.
9580 ??? For 2.5, try to tighten up the MD files in this regard
9581 instead of this kludge. */
9583 if (GET_MODE_PRECISION (GET_MODE (x)) < GET_MODE_PRECISION (mode)
9584 && CONST_INT_P (tem)
9586 && val_signbit_known_set_p (GET_MODE (x), INTVAL (tem)))
9587 tem = GEN_INT (INTVAL (tem) | ~GET_MODE_MASK (GET_MODE (x)));
9591 else if (nonzero_sign_valid && rsp->nonzero_bits)
9593 unsigned HOST_WIDE_INT mask = rsp->nonzero_bits;
9595 if (GET_MODE_BITSIZE (GET_MODE (x)) < GET_MODE_BITSIZE (mode))
9596 /* We don't know anything about the upper bits. */
9597 mask |= GET_MODE_MASK (mode) ^ GET_MODE_MASK (GET_MODE (x));
9604 /* Return the number of bits at the high-order end of X that are known to
9605 be equal to the sign bit. X will be used in mode MODE; if MODE is
9606 VOIDmode, X will be used in its own mode. The returned value will always
9607 be between 1 and the number of bits in MODE. */
9610 reg_num_sign_bit_copies_for_combine (const_rtx x, enum machine_mode mode,
9611 const_rtx known_x ATTRIBUTE_UNUSED,
9612 enum machine_mode known_mode
9614 unsigned int known_ret ATTRIBUTE_UNUSED,
9615 unsigned int *result)
9620 rsp = VEC_index (reg_stat_type, reg_stat, REGNO (x));
9621 if (rsp->last_set_value != 0
9622 && rsp->last_set_mode == mode
9623 && ((rsp->last_set_label >= label_tick_ebb_start
9624 && rsp->last_set_label < label_tick)
9625 || (rsp->last_set_label == label_tick
9626 && DF_INSN_LUID (rsp->last_set) < subst_low_luid)
9627 || (REGNO (x) >= FIRST_PSEUDO_REGISTER
9628 && REG_N_SETS (REGNO (x)) == 1
9630 (DF_LR_IN (ENTRY_BLOCK_PTR->next_bb), REGNO (x)))))
9632 *result = rsp->last_set_sign_bit_copies;
9636 tem = get_last_value (x);
9640 if (nonzero_sign_valid && rsp->sign_bit_copies != 0
9641 && GET_MODE_BITSIZE (GET_MODE (x)) == GET_MODE_BITSIZE (mode))
9642 *result = rsp->sign_bit_copies;
9647 /* Return the number of "extended" bits there are in X, when interpreted
9648 as a quantity in MODE whose signedness is indicated by UNSIGNEDP. For
9649 unsigned quantities, this is the number of high-order zero bits.
9650 For signed quantities, this is the number of copies of the sign bit
9651 minus 1. In both case, this function returns the number of "spare"
9652 bits. For example, if two quantities for which this function returns
9653 at least 1 are added, the addition is known not to overflow.
9655 This function will always return 0 unless called during combine, which
9656 implies that it must be called from a define_split. */
9659 extended_count (const_rtx x, enum machine_mode mode, int unsignedp)
9661 if (nonzero_sign_valid == 0)
9665 ? (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
9666 ? (unsigned int) (GET_MODE_BITSIZE (mode) - 1
9667 - floor_log2 (nonzero_bits (x, mode)))
9669 : num_sign_bit_copies (x, mode) - 1);
9672 /* This function is called from `simplify_shift_const' to merge two
9673 outer operations. Specifically, we have already found that we need
9674 to perform operation *POP0 with constant *PCONST0 at the outermost
9675 position. We would now like to also perform OP1 with constant CONST1
9676 (with *POP0 being done last).
9678 Return 1 if we can do the operation and update *POP0 and *PCONST0 with
9679 the resulting operation. *PCOMP_P is set to 1 if we would need to
9680 complement the innermost operand, otherwise it is unchanged.
9682 MODE is the mode in which the operation will be done. No bits outside
9683 the width of this mode matter. It is assumed that the width of this mode
9684 is smaller than or equal to HOST_BITS_PER_WIDE_INT.
9686 If *POP0 or OP1 are UNKNOWN, it means no operation is required. Only NEG, PLUS,
9687 IOR, XOR, and AND are supported. We may set *POP0 to SET if the proper
9688 result is simply *PCONST0.
9690 If the resulting operation cannot be expressed as one operation, we
9691 return 0 and do not change *POP0, *PCONST0, and *PCOMP_P. */
9694 merge_outer_ops (enum rtx_code *pop0, HOST_WIDE_INT *pconst0, enum rtx_code op1, HOST_WIDE_INT const1, enum machine_mode mode, int *pcomp_p)
9696 enum rtx_code op0 = *pop0;
9697 HOST_WIDE_INT const0 = *pconst0;
9699 const0 &= GET_MODE_MASK (mode);
9700 const1 &= GET_MODE_MASK (mode);
9702 /* If OP0 is an AND, clear unimportant bits in CONST1. */
9706 /* If OP0 or OP1 is UNKNOWN, this is easy. Similarly if they are the same or
9709 if (op1 == UNKNOWN || op0 == SET)
9712 else if (op0 == UNKNOWN)
9713 op0 = op1, const0 = const1;
9715 else if (op0 == op1)
9739 /* Otherwise, if either is a PLUS or NEG, we can't do anything. */
9740 else if (op0 == PLUS || op1 == PLUS || op0 == NEG || op1 == NEG)
9743 /* If the two constants aren't the same, we can't do anything. The
9744 remaining six cases can all be done. */
9745 else if (const0 != const1)
9753 /* (a & b) | b == b */
9755 else /* op1 == XOR */
9756 /* (a ^ b) | b == a | b */
9762 /* (a & b) ^ b == (~a) & b */
9763 op0 = AND, *pcomp_p = 1;
9764 else /* op1 == IOR */
9765 /* (a | b) ^ b == a & ~b */
9766 op0 = AND, const0 = ~const0;
9771 /* (a | b) & b == b */
9773 else /* op1 == XOR */
9774 /* (a ^ b) & b) == (~a) & b */
9781 /* Check for NO-OP cases. */
9782 const0 &= GET_MODE_MASK (mode);
9784 && (op0 == IOR || op0 == XOR || op0 == PLUS))
9786 else if (const0 == 0 && op0 == AND)
9788 else if ((unsigned HOST_WIDE_INT) const0 == GET_MODE_MASK (mode)
9794 /* ??? Slightly redundant with the above mask, but not entirely.
9795 Moving this above means we'd have to sign-extend the mode mask
9796 for the final test. */
9797 if (op0 != UNKNOWN && op0 != NEG)
9798 *pconst0 = trunc_int_for_mode (const0, mode);
9803 /* A helper to simplify_shift_const_1 to determine the mode we can perform
9804 the shift in. The original shift operation CODE is performed on OP in
9805 ORIG_MODE. Return the wider mode MODE if we can perform the operation
9806 in that mode. Return ORIG_MODE otherwise. We can also assume that the
9807 result of the shift is subject to operation OUTER_CODE with operand
9810 static enum machine_mode
9811 try_widen_shift_mode (enum rtx_code code, rtx op, int count,
9812 enum machine_mode orig_mode, enum machine_mode mode,
9813 enum rtx_code outer_code, HOST_WIDE_INT outer_const)
9815 if (orig_mode == mode)
9817 gcc_assert (GET_MODE_BITSIZE (mode) > GET_MODE_BITSIZE (orig_mode));
9819 /* In general we can't perform in wider mode for right shift and rotate. */
9823 /* We can still widen if the bits brought in from the left are identical
9824 to the sign bit of ORIG_MODE. */
9825 if (num_sign_bit_copies (op, mode)
9826 > (unsigned) (GET_MODE_BITSIZE (mode)
9827 - GET_MODE_BITSIZE (orig_mode)))
9832 /* Similarly here but with zero bits. */
9833 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
9834 && (nonzero_bits (op, mode) & ~GET_MODE_MASK (orig_mode)) == 0)
9837 /* We can also widen if the bits brought in will be masked off. This
9838 operation is performed in ORIG_MODE. */
9839 if (outer_code == AND)
9841 int care_bits = low_bitmask_len (orig_mode, outer_const);
9844 && GET_MODE_BITSIZE (orig_mode) - care_bits >= count)
9860 /* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift.
9861 The result of the shift is RESULT_MODE. Return NULL_RTX if we cannot
9862 simplify it. Otherwise, return a simplified value.
9864 The shift is normally computed in the widest mode we find in VAROP, as
9865 long as it isn't a different number of words than RESULT_MODE. Exceptions
9866 are ASHIFTRT and ROTATE, which are always done in their original mode. */
9869 simplify_shift_const_1 (enum rtx_code code, enum machine_mode result_mode,
9870 rtx varop, int orig_count)
9872 enum rtx_code orig_code = code;
9873 rtx orig_varop = varop;
9875 enum machine_mode mode = result_mode;
9876 enum machine_mode shift_mode, tmode;
9877 unsigned int mode_words
9878 = (GET_MODE_SIZE (mode) + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD;
9879 /* We form (outer_op (code varop count) (outer_const)). */
9880 enum rtx_code outer_op = UNKNOWN;
9881 HOST_WIDE_INT outer_const = 0;
9882 int complement_p = 0;
9885 /* Make sure and truncate the "natural" shift on the way in. We don't
9886 want to do this inside the loop as it makes it more difficult to
9888 if (SHIFT_COUNT_TRUNCATED)
9889 orig_count &= targetm.shift_truncation_mask (mode);
9891 /* If we were given an invalid count, don't do anything except exactly
9892 what was requested. */
9894 if (orig_count < 0 || orig_count >= (int) GET_MODE_BITSIZE (mode))
9899 /* Unless one of the branches of the `if' in this loop does a `continue',
9900 we will `break' the loop after the `if'. */
9904 /* If we have an operand of (clobber (const_int 0)), fail. */
9905 if (GET_CODE (varop) == CLOBBER)
9908 /* Convert ROTATERT to ROTATE. */
9909 if (code == ROTATERT)
9911 unsigned int bitsize = GET_MODE_BITSIZE (result_mode);;
9913 if (VECTOR_MODE_P (result_mode))
9914 count = bitsize / GET_MODE_NUNITS (result_mode) - count;
9916 count = bitsize - count;
9919 shift_mode = try_widen_shift_mode (code, varop, count, result_mode,
9920 mode, outer_op, outer_const);
9922 /* Handle cases where the count is greater than the size of the mode
9923 minus 1. For ASHIFT, use the size minus one as the count (this can
9924 occur when simplifying (lshiftrt (ashiftrt ..))). For rotates,
9925 take the count modulo the size. For other shifts, the result is
9928 Since these shifts are being produced by the compiler by combining
9929 multiple operations, each of which are defined, we know what the
9930 result is supposed to be. */
9932 if (count > (GET_MODE_BITSIZE (shift_mode) - 1))
9934 if (code == ASHIFTRT)
9935 count = GET_MODE_BITSIZE (shift_mode) - 1;
9936 else if (code == ROTATE || code == ROTATERT)
9937 count %= GET_MODE_BITSIZE (shift_mode);
9940 /* We can't simply return zero because there may be an
9948 /* If we discovered we had to complement VAROP, leave. Making a NOT
9949 here would cause an infinite loop. */
9953 /* An arithmetic right shift of a quantity known to be -1 or 0
9955 if (code == ASHIFTRT
9956 && (num_sign_bit_copies (varop, shift_mode)
9957 == GET_MODE_BITSIZE (shift_mode)))
9963 /* If we are doing an arithmetic right shift and discarding all but
9964 the sign bit copies, this is equivalent to doing a shift by the
9965 bitsize minus one. Convert it into that shift because it will often
9966 allow other simplifications. */
9968 if (code == ASHIFTRT
9969 && (count + num_sign_bit_copies (varop, shift_mode)
9970 >= GET_MODE_BITSIZE (shift_mode)))
9971 count = GET_MODE_BITSIZE (shift_mode) - 1;
9973 /* We simplify the tests below and elsewhere by converting
9974 ASHIFTRT to LSHIFTRT if we know the sign bit is clear.
9975 `make_compound_operation' will convert it to an ASHIFTRT for
9976 those machines (such as VAX) that don't have an LSHIFTRT. */
9977 if (code == ASHIFTRT
9978 && val_signbit_known_clear_p (shift_mode,
9979 nonzero_bits (varop, shift_mode)))
9982 if (((code == LSHIFTRT
9983 && GET_MODE_BITSIZE (shift_mode) <= HOST_BITS_PER_WIDE_INT
9984 && !(nonzero_bits (varop, shift_mode) >> count))
9986 && GET_MODE_BITSIZE (shift_mode) <= HOST_BITS_PER_WIDE_INT
9987 && !((nonzero_bits (varop, shift_mode) << count)
9988 & GET_MODE_MASK (shift_mode))))
9989 && !side_effects_p (varop))
9992 switch (GET_CODE (varop))
9998 new_rtx = expand_compound_operation (varop);
9999 if (new_rtx != varop)
10007 /* If we have (xshiftrt (mem ...) C) and C is MODE_WIDTH
10008 minus the width of a smaller mode, we can do this with a
10009 SIGN_EXTEND or ZERO_EXTEND from the narrower memory location. */
10010 if ((code == ASHIFTRT || code == LSHIFTRT)
10011 && ! mode_dependent_address_p (XEXP (varop, 0))
10012 && ! MEM_VOLATILE_P (varop)
10013 && (tmode = mode_for_size (GET_MODE_BITSIZE (mode) - count,
10014 MODE_INT, 1)) != BLKmode)
10016 new_rtx = adjust_address_nv (varop, tmode,
10017 BYTES_BIG_ENDIAN ? 0
10018 : count / BITS_PER_UNIT);
10020 varop = gen_rtx_fmt_e (code == ASHIFTRT ? SIGN_EXTEND
10021 : ZERO_EXTEND, mode, new_rtx);
10028 /* If VAROP is a SUBREG, strip it as long as the inner operand has
10029 the same number of words as what we've seen so far. Then store
10030 the widest mode in MODE. */
10031 if (subreg_lowpart_p (varop)
10032 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop)))
10033 > GET_MODE_SIZE (GET_MODE (varop)))
10034 && (unsigned int) ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop)))
10035 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
10037 && GET_MODE_CLASS (GET_MODE (varop)) == MODE_INT
10038 && GET_MODE_CLASS (GET_MODE (SUBREG_REG (varop))) == MODE_INT)
10040 varop = SUBREG_REG (varop);
10041 if (GET_MODE_SIZE (GET_MODE (varop)) > GET_MODE_SIZE (mode))
10042 mode = GET_MODE (varop);
10048 /* Some machines use MULT instead of ASHIFT because MULT
10049 is cheaper. But it is still better on those machines to
10050 merge two shifts into one. */
10051 if (CONST_INT_P (XEXP (varop, 1))
10052 && exact_log2 (UINTVAL (XEXP (varop, 1))) >= 0)
10055 = simplify_gen_binary (ASHIFT, GET_MODE (varop),
10057 GEN_INT (exact_log2 (
10058 UINTVAL (XEXP (varop, 1)))));
10064 /* Similar, for when divides are cheaper. */
10065 if (CONST_INT_P (XEXP (varop, 1))
10066 && exact_log2 (UINTVAL (XEXP (varop, 1))) >= 0)
10069 = simplify_gen_binary (LSHIFTRT, GET_MODE (varop),
10071 GEN_INT (exact_log2 (
10072 UINTVAL (XEXP (varop, 1)))));
10078 /* If we are extracting just the sign bit of an arithmetic
10079 right shift, that shift is not needed. However, the sign
10080 bit of a wider mode may be different from what would be
10081 interpreted as the sign bit in a narrower mode, so, if
10082 the result is narrower, don't discard the shift. */
10083 if (code == LSHIFTRT
10084 && count == (GET_MODE_BITSIZE (result_mode) - 1)
10085 && (GET_MODE_BITSIZE (result_mode)
10086 >= GET_MODE_BITSIZE (GET_MODE (varop))))
10088 varop = XEXP (varop, 0);
10092 /* ... fall through ... */
10097 /* Here we have two nested shifts. The result is usually the
10098 AND of a new shift with a mask. We compute the result below. */
10099 if (CONST_INT_P (XEXP (varop, 1))
10100 && INTVAL (XEXP (varop, 1)) >= 0
10101 && INTVAL (XEXP (varop, 1)) < GET_MODE_BITSIZE (GET_MODE (varop))
10102 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
10103 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
10104 && !VECTOR_MODE_P (result_mode))
10106 enum rtx_code first_code = GET_CODE (varop);
10107 unsigned int first_count = INTVAL (XEXP (varop, 1));
10108 unsigned HOST_WIDE_INT mask;
10111 /* We have one common special case. We can't do any merging if
10112 the inner code is an ASHIFTRT of a smaller mode. However, if
10113 we have (ashift:M1 (subreg:M1 (ashiftrt:M2 FOO C1) 0) C2)
10114 with C2 == GET_MODE_BITSIZE (M1) - GET_MODE_BITSIZE (M2),
10115 we can convert it to
10116 (ashiftrt:M1 (ashift:M1 (and:M1 (subreg:M1 FOO 0 C2) C3) C1).
10117 This simplifies certain SIGN_EXTEND operations. */
10118 if (code == ASHIFT && first_code == ASHIFTRT
10119 && count == (GET_MODE_BITSIZE (result_mode)
10120 - GET_MODE_BITSIZE (GET_MODE (varop))))
10122 /* C3 has the low-order C1 bits zero. */
10124 mask = GET_MODE_MASK (mode)
10125 & ~(((unsigned HOST_WIDE_INT) 1 << first_count) - 1);
10127 varop = simplify_and_const_int (NULL_RTX, result_mode,
10128 XEXP (varop, 0), mask);
10129 varop = simplify_shift_const (NULL_RTX, ASHIFT, result_mode,
10131 count = first_count;
10136 /* If this was (ashiftrt (ashift foo C1) C2) and FOO has more
10137 than C1 high-order bits equal to the sign bit, we can convert
10138 this to either an ASHIFT or an ASHIFTRT depending on the
10141 We cannot do this if VAROP's mode is not SHIFT_MODE. */
10143 if (code == ASHIFTRT && first_code == ASHIFT
10144 && GET_MODE (varop) == shift_mode
10145 && (num_sign_bit_copies (XEXP (varop, 0), shift_mode)
10148 varop = XEXP (varop, 0);
10149 count -= first_count;
10159 /* There are some cases we can't do. If CODE is ASHIFTRT,
10160 we can only do this if FIRST_CODE is also ASHIFTRT.
10162 We can't do the case when CODE is ROTATE and FIRST_CODE is
10165 If the mode of this shift is not the mode of the outer shift,
10166 we can't do this if either shift is a right shift or ROTATE.
10168 Finally, we can't do any of these if the mode is too wide
10169 unless the codes are the same.
10171 Handle the case where the shift codes are the same
10174 if (code == first_code)
10176 if (GET_MODE (varop) != result_mode
10177 && (code == ASHIFTRT || code == LSHIFTRT
10178 || code == ROTATE))
10181 count += first_count;
10182 varop = XEXP (varop, 0);
10186 if (code == ASHIFTRT
10187 || (code == ROTATE && first_code == ASHIFTRT)
10188 || GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT
10189 || (GET_MODE (varop) != result_mode
10190 && (first_code == ASHIFTRT || first_code == LSHIFTRT
10191 || first_code == ROTATE
10192 || code == ROTATE)))
10195 /* To compute the mask to apply after the shift, shift the
10196 nonzero bits of the inner shift the same way the
10197 outer shift will. */
10199 mask_rtx = GEN_INT (nonzero_bits (varop, GET_MODE (varop)));
10202 = simplify_const_binary_operation (code, result_mode, mask_rtx,
10205 /* Give up if we can't compute an outer operation to use. */
10207 || !CONST_INT_P (mask_rtx)
10208 || ! merge_outer_ops (&outer_op, &outer_const, AND,
10210 result_mode, &complement_p))
10213 /* If the shifts are in the same direction, we add the
10214 counts. Otherwise, we subtract them. */
10215 if ((code == ASHIFTRT || code == LSHIFTRT)
10216 == (first_code == ASHIFTRT || first_code == LSHIFTRT))
10217 count += first_count;
10219 count -= first_count;
10221 /* If COUNT is positive, the new shift is usually CODE,
10222 except for the two exceptions below, in which case it is
10223 FIRST_CODE. If the count is negative, FIRST_CODE should
10226 && ((first_code == ROTATE && code == ASHIFT)
10227 || (first_code == ASHIFTRT && code == LSHIFTRT)))
10229 else if (count < 0)
10230 code = first_code, count = -count;
10232 varop = XEXP (varop, 0);
10236 /* If we have (A << B << C) for any shift, we can convert this to
10237 (A << C << B). This wins if A is a constant. Only try this if
10238 B is not a constant. */
10240 else if (GET_CODE (varop) == code
10241 && CONST_INT_P (XEXP (varop, 0))
10242 && !CONST_INT_P (XEXP (varop, 1)))
10244 rtx new_rtx = simplify_const_binary_operation (code, mode,
10247 varop = gen_rtx_fmt_ee (code, mode, new_rtx, XEXP (varop, 1));
10254 if (VECTOR_MODE_P (mode))
10257 /* Make this fit the case below. */
10258 varop = gen_rtx_XOR (mode, XEXP (varop, 0),
10259 GEN_INT (GET_MODE_MASK (mode)));
10265 /* If we have (xshiftrt (ior (plus X (const_int -1)) X) C)
10266 with C the size of VAROP - 1 and the shift is logical if
10267 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
10268 we have an (le X 0) operation. If we have an arithmetic shift
10269 and STORE_FLAG_VALUE is 1 or we have a logical shift with
10270 STORE_FLAG_VALUE of -1, we have a (neg (le X 0)) operation. */
10272 if (GET_CODE (varop) == IOR && GET_CODE (XEXP (varop, 0)) == PLUS
10273 && XEXP (XEXP (varop, 0), 1) == constm1_rtx
10274 && (STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
10275 && (code == LSHIFTRT || code == ASHIFTRT)
10276 && count == (GET_MODE_BITSIZE (GET_MODE (varop)) - 1)
10277 && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
10280 varop = gen_rtx_LE (GET_MODE (varop), XEXP (varop, 1),
10283 if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
10284 varop = gen_rtx_NEG (GET_MODE (varop), varop);
10289 /* If we have (shift (logical)), move the logical to the outside
10290 to allow it to possibly combine with another logical and the
10291 shift to combine with another shift. This also canonicalizes to
10292 what a ZERO_EXTRACT looks like. Also, some machines have
10293 (and (shift)) insns. */
10295 if (CONST_INT_P (XEXP (varop, 1))
10296 /* We can't do this if we have (ashiftrt (xor)) and the
10297 constant has its sign bit set in shift_mode. */
10298 && !(code == ASHIFTRT && GET_CODE (varop) == XOR
10299 && 0 > trunc_int_for_mode (INTVAL (XEXP (varop, 1)),
10301 && (new_rtx = simplify_const_binary_operation (code, result_mode,
10303 GEN_INT (count))) != 0
10304 && CONST_INT_P (new_rtx)
10305 && merge_outer_ops (&outer_op, &outer_const, GET_CODE (varop),
10306 INTVAL (new_rtx), result_mode, &complement_p))
10308 varop = XEXP (varop, 0);
10312 /* If we can't do that, try to simplify the shift in each arm of the
10313 logical expression, make a new logical expression, and apply
10314 the inverse distributive law. This also can't be done
10315 for some (ashiftrt (xor)). */
10316 if (CONST_INT_P (XEXP (varop, 1))
10317 && !(code == ASHIFTRT && GET_CODE (varop) == XOR
10318 && 0 > trunc_int_for_mode (INTVAL (XEXP (varop, 1)),
10321 rtx lhs = simplify_shift_const (NULL_RTX, code, shift_mode,
10322 XEXP (varop, 0), count);
10323 rtx rhs = simplify_shift_const (NULL_RTX, code, shift_mode,
10324 XEXP (varop, 1), count);
10326 varop = simplify_gen_binary (GET_CODE (varop), shift_mode,
10328 varop = apply_distributive_law (varop);
10336 /* Convert (lshiftrt (eq FOO 0) C) to (xor FOO 1) if STORE_FLAG_VALUE
10337 says that the sign bit can be tested, FOO has mode MODE, C is
10338 GET_MODE_BITSIZE (MODE) - 1, and FOO has only its low-order bit
10339 that may be nonzero. */
10340 if (code == LSHIFTRT
10341 && XEXP (varop, 1) == const0_rtx
10342 && GET_MODE (XEXP (varop, 0)) == result_mode
10343 && count == (GET_MODE_BITSIZE (result_mode) - 1)
10344 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
10345 && STORE_FLAG_VALUE == -1
10346 && nonzero_bits (XEXP (varop, 0), result_mode) == 1
10347 && merge_outer_ops (&outer_op, &outer_const, XOR, 1, result_mode,
10350 varop = XEXP (varop, 0);
10357 /* (lshiftrt (neg A) C) where A is either 0 or 1 and C is one less
10358 than the number of bits in the mode is equivalent to A. */
10359 if (code == LSHIFTRT
10360 && count == (GET_MODE_BITSIZE (result_mode) - 1)
10361 && nonzero_bits (XEXP (varop, 0), result_mode) == 1)
10363 varop = XEXP (varop, 0);
10368 /* NEG commutes with ASHIFT since it is multiplication. Move the
10369 NEG outside to allow shifts to combine. */
10371 && merge_outer_ops (&outer_op, &outer_const, NEG, 0, result_mode,
10374 varop = XEXP (varop, 0);
10380 /* (lshiftrt (plus A -1) C) where A is either 0 or 1 and C
10381 is one less than the number of bits in the mode is
10382 equivalent to (xor A 1). */
10383 if (code == LSHIFTRT
10384 && count == (GET_MODE_BITSIZE (result_mode) - 1)
10385 && XEXP (varop, 1) == constm1_rtx
10386 && nonzero_bits (XEXP (varop, 0), result_mode) == 1
10387 && merge_outer_ops (&outer_op, &outer_const, XOR, 1, result_mode,
10391 varop = XEXP (varop, 0);
10395 /* If we have (xshiftrt (plus FOO BAR) C), and the only bits
10396 that might be nonzero in BAR are those being shifted out and those
10397 bits are known zero in FOO, we can replace the PLUS with FOO.
10398 Similarly in the other operand order. This code occurs when
10399 we are computing the size of a variable-size array. */
10401 if ((code == ASHIFTRT || code == LSHIFTRT)
10402 && count < HOST_BITS_PER_WIDE_INT
10403 && nonzero_bits (XEXP (varop, 1), result_mode) >> count == 0
10404 && (nonzero_bits (XEXP (varop, 1), result_mode)
10405 & nonzero_bits (XEXP (varop, 0), result_mode)) == 0)
10407 varop = XEXP (varop, 0);
10410 else if ((code == ASHIFTRT || code == LSHIFTRT)
10411 && count < HOST_BITS_PER_WIDE_INT
10412 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
10413 && 0 == (nonzero_bits (XEXP (varop, 0), result_mode)
10415 && 0 == (nonzero_bits (XEXP (varop, 0), result_mode)
10416 & nonzero_bits (XEXP (varop, 1),
10419 varop = XEXP (varop, 1);
10423 /* (ashift (plus foo C) N) is (plus (ashift foo N) C'). */
10425 && CONST_INT_P (XEXP (varop, 1))
10426 && (new_rtx = simplify_const_binary_operation (ASHIFT, result_mode,
10428 GEN_INT (count))) != 0
10429 && CONST_INT_P (new_rtx)
10430 && merge_outer_ops (&outer_op, &outer_const, PLUS,
10431 INTVAL (new_rtx), result_mode, &complement_p))
10433 varop = XEXP (varop, 0);
10437 /* Check for 'PLUS signbit', which is the canonical form of 'XOR
10438 signbit', and attempt to change the PLUS to an XOR and move it to
10439 the outer operation as is done above in the AND/IOR/XOR case
10440 leg for shift(logical). See details in logical handling above
10441 for reasoning in doing so. */
10442 if (code == LSHIFTRT
10443 && CONST_INT_P (XEXP (varop, 1))
10444 && mode_signbit_p (result_mode, XEXP (varop, 1))
10445 && (new_rtx = simplify_const_binary_operation (code, result_mode,
10447 GEN_INT (count))) != 0
10448 && CONST_INT_P (new_rtx)
10449 && merge_outer_ops (&outer_op, &outer_const, XOR,
10450 INTVAL (new_rtx), result_mode, &complement_p))
10452 varop = XEXP (varop, 0);
10459 /* If we have (xshiftrt (minus (ashiftrt X C)) X) C)
10460 with C the size of VAROP - 1 and the shift is logical if
10461 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
10462 we have a (gt X 0) operation. If the shift is arithmetic with
10463 STORE_FLAG_VALUE of 1 or logical with STORE_FLAG_VALUE == -1,
10464 we have a (neg (gt X 0)) operation. */
10466 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
10467 && GET_CODE (XEXP (varop, 0)) == ASHIFTRT
10468 && count == (GET_MODE_BITSIZE (GET_MODE (varop)) - 1)
10469 && (code == LSHIFTRT || code == ASHIFTRT)
10470 && CONST_INT_P (XEXP (XEXP (varop, 0), 1))
10471 && INTVAL (XEXP (XEXP (varop, 0), 1)) == count
10472 && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
10475 varop = gen_rtx_GT (GET_MODE (varop), XEXP (varop, 1),
10478 if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
10479 varop = gen_rtx_NEG (GET_MODE (varop), varop);
10486 /* Change (lshiftrt (truncate (lshiftrt))) to (truncate (lshiftrt))
10487 if the truncate does not affect the value. */
10488 if (code == LSHIFTRT
10489 && GET_CODE (XEXP (varop, 0)) == LSHIFTRT
10490 && CONST_INT_P (XEXP (XEXP (varop, 0), 1))
10491 && (INTVAL (XEXP (XEXP (varop, 0), 1))
10492 >= (GET_MODE_BITSIZE (GET_MODE (XEXP (varop, 0)))
10493 - GET_MODE_BITSIZE (GET_MODE (varop)))))
10495 rtx varop_inner = XEXP (varop, 0);
10498 = gen_rtx_LSHIFTRT (GET_MODE (varop_inner),
10499 XEXP (varop_inner, 0),
10501 (count + INTVAL (XEXP (varop_inner, 1))));
10502 varop = gen_rtx_TRUNCATE (GET_MODE (varop), varop_inner);
10515 shift_mode = try_widen_shift_mode (code, varop, count, result_mode, mode,
10516 outer_op, outer_const);
10518 /* We have now finished analyzing the shift. The result should be
10519 a shift of type CODE with SHIFT_MODE shifting VAROP COUNT places. If
10520 OUTER_OP is non-UNKNOWN, it is an operation that needs to be applied
10521 to the result of the shift. OUTER_CONST is the relevant constant,
10522 but we must turn off all bits turned off in the shift. */
10524 if (outer_op == UNKNOWN
10525 && orig_code == code && orig_count == count
10526 && varop == orig_varop
10527 && shift_mode == GET_MODE (varop))
10530 /* Make a SUBREG if necessary. If we can't make it, fail. */
10531 varop = gen_lowpart (shift_mode, varop);
10532 if (varop == NULL_RTX || GET_CODE (varop) == CLOBBER)
10535 /* If we have an outer operation and we just made a shift, it is
10536 possible that we could have simplified the shift were it not
10537 for the outer operation. So try to do the simplification
10540 if (outer_op != UNKNOWN)
10541 x = simplify_shift_const_1 (code, shift_mode, varop, count);
10546 x = simplify_gen_binary (code, shift_mode, varop, GEN_INT (count));
10548 /* If we were doing an LSHIFTRT in a wider mode than it was originally,
10549 turn off all the bits that the shift would have turned off. */
10550 if (orig_code == LSHIFTRT && result_mode != shift_mode)
10551 x = simplify_and_const_int (NULL_RTX, shift_mode, x,
10552 GET_MODE_MASK (result_mode) >> orig_count);
10554 /* Do the remainder of the processing in RESULT_MODE. */
10555 x = gen_lowpart_or_truncate (result_mode, x);
10557 /* If COMPLEMENT_P is set, we have to complement X before doing the outer
10560 x = simplify_gen_unary (NOT, result_mode, x, result_mode);
10562 if (outer_op != UNKNOWN)
10564 if (GET_RTX_CLASS (outer_op) != RTX_UNARY
10565 && GET_MODE_BITSIZE (result_mode) < HOST_BITS_PER_WIDE_INT)
10566 outer_const = trunc_int_for_mode (outer_const, result_mode);
10568 if (outer_op == AND)
10569 x = simplify_and_const_int (NULL_RTX, result_mode, x, outer_const);
10570 else if (outer_op == SET)
10572 /* This means that we have determined that the result is
10573 equivalent to a constant. This should be rare. */
10574 if (!side_effects_p (x))
10575 x = GEN_INT (outer_const);
10577 else if (GET_RTX_CLASS (outer_op) == RTX_UNARY)
10578 x = simplify_gen_unary (outer_op, result_mode, x, result_mode);
10580 x = simplify_gen_binary (outer_op, result_mode, x,
10581 GEN_INT (outer_const));
10587 /* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift.
10588 The result of the shift is RESULT_MODE. If we cannot simplify it,
10589 return X or, if it is NULL, synthesize the expression with
10590 simplify_gen_binary. Otherwise, return a simplified value.
10592 The shift is normally computed in the widest mode we find in VAROP, as
10593 long as it isn't a different number of words than RESULT_MODE. Exceptions
10594 are ASHIFTRT and ROTATE, which are always done in their original mode. */
10597 simplify_shift_const (rtx x, enum rtx_code code, enum machine_mode result_mode,
10598 rtx varop, int count)
10600 rtx tem = simplify_shift_const_1 (code, result_mode, varop, count);
10605 x = simplify_gen_binary (code, GET_MODE (varop), varop, GEN_INT (count));
10606 if (GET_MODE (x) != result_mode)
10607 x = gen_lowpart (result_mode, x);
10612 /* Like recog, but we receive the address of a pointer to a new pattern.
10613 We try to match the rtx that the pointer points to.
10614 If that fails, we may try to modify or replace the pattern,
10615 storing the replacement into the same pointer object.
10617 Modifications include deletion or addition of CLOBBERs.
10619 PNOTES is a pointer to a location where any REG_UNUSED notes added for
10620 the CLOBBERs are placed.
10622 The value is the final insn code from the pattern ultimately matched,
10626 recog_for_combine (rtx *pnewpat, rtx insn, rtx *pnotes)
10628 rtx pat = *pnewpat;
10629 int insn_code_number;
10630 int num_clobbers_to_add = 0;
10633 rtx old_notes, old_pat;
10635 /* If PAT is a PARALLEL, check to see if it contains the CLOBBER
10636 we use to indicate that something didn't match. If we find such a
10637 thing, force rejection. */
10638 if (GET_CODE (pat) == PARALLEL)
10639 for (i = XVECLEN (pat, 0) - 1; i >= 0; i--)
10640 if (GET_CODE (XVECEXP (pat, 0, i)) == CLOBBER
10641 && XEXP (XVECEXP (pat, 0, i), 0) == const0_rtx)
10644 old_pat = PATTERN (insn);
10645 old_notes = REG_NOTES (insn);
10646 PATTERN (insn) = pat;
10647 REG_NOTES (insn) = 0;
10649 insn_code_number = recog (pat, insn, &num_clobbers_to_add);
10650 if (dump_file && (dump_flags & TDF_DETAILS))
10652 if (insn_code_number < 0)
10653 fputs ("Failed to match this instruction:\n", dump_file);
10655 fputs ("Successfully matched this instruction:\n", dump_file);
10656 print_rtl_single (dump_file, pat);
10659 /* If it isn't, there is the possibility that we previously had an insn
10660 that clobbered some register as a side effect, but the combined
10661 insn doesn't need to do that. So try once more without the clobbers
10662 unless this represents an ASM insn. */
10664 if (insn_code_number < 0 && ! check_asm_operands (pat)
10665 && GET_CODE (pat) == PARALLEL)
10669 for (pos = 0, i = 0; i < XVECLEN (pat, 0); i++)
10670 if (GET_CODE (XVECEXP (pat, 0, i)) != CLOBBER)
10673 SUBST (XVECEXP (pat, 0, pos), XVECEXP (pat, 0, i));
10677 SUBST_INT (XVECLEN (pat, 0), pos);
10680 pat = XVECEXP (pat, 0, 0);
10682 PATTERN (insn) = pat;
10683 insn_code_number = recog (pat, insn, &num_clobbers_to_add);
10684 if (dump_file && (dump_flags & TDF_DETAILS))
10686 if (insn_code_number < 0)
10687 fputs ("Failed to match this instruction:\n", dump_file);
10689 fputs ("Successfully matched this instruction:\n", dump_file);
10690 print_rtl_single (dump_file, pat);
10693 PATTERN (insn) = old_pat;
10694 REG_NOTES (insn) = old_notes;
10696 /* Recognize all noop sets, these will be killed by followup pass. */
10697 if (insn_code_number < 0 && GET_CODE (pat) == SET && set_noop_p (pat))
10698 insn_code_number = NOOP_MOVE_INSN_CODE, num_clobbers_to_add = 0;
10700 /* If we had any clobbers to add, make a new pattern than contains
10701 them. Then check to make sure that all of them are dead. */
10702 if (num_clobbers_to_add)
10704 rtx newpat = gen_rtx_PARALLEL (VOIDmode,
10705 rtvec_alloc (GET_CODE (pat) == PARALLEL
10706 ? (XVECLEN (pat, 0)
10707 + num_clobbers_to_add)
10708 : num_clobbers_to_add + 1));
10710 if (GET_CODE (pat) == PARALLEL)
10711 for (i = 0; i < XVECLEN (pat, 0); i++)
10712 XVECEXP (newpat, 0, i) = XVECEXP (pat, 0, i);
10714 XVECEXP (newpat, 0, 0) = pat;
10716 add_clobbers (newpat, insn_code_number);
10718 for (i = XVECLEN (newpat, 0) - num_clobbers_to_add;
10719 i < XVECLEN (newpat, 0); i++)
10721 if (REG_P (XEXP (XVECEXP (newpat, 0, i), 0))
10722 && ! reg_dead_at_p (XEXP (XVECEXP (newpat, 0, i), 0), insn))
10724 if (GET_CODE (XEXP (XVECEXP (newpat, 0, i), 0)) != SCRATCH)
10726 gcc_assert (REG_P (XEXP (XVECEXP (newpat, 0, i), 0)));
10727 notes = alloc_reg_note (REG_UNUSED,
10728 XEXP (XVECEXP (newpat, 0, i), 0), notes);
10737 return insn_code_number;
10740 /* Like gen_lowpart_general but for use by combine. In combine it
10741 is not possible to create any new pseudoregs. However, it is
10742 safe to create invalid memory addresses, because combine will
10743 try to recognize them and all they will do is make the combine
10746 If for some reason this cannot do its job, an rtx
10747 (clobber (const_int 0)) is returned.
10748 An insn containing that will not be recognized. */
10751 gen_lowpart_for_combine (enum machine_mode omode, rtx x)
10753 enum machine_mode imode = GET_MODE (x);
10754 unsigned int osize = GET_MODE_SIZE (omode);
10755 unsigned int isize = GET_MODE_SIZE (imode);
10758 if (omode == imode)
10761 /* Return identity if this is a CONST or symbolic reference. */
10763 && (GET_CODE (x) == CONST
10764 || GET_CODE (x) == SYMBOL_REF
10765 || GET_CODE (x) == LABEL_REF))
10768 /* We can only support MODE being wider than a word if X is a
10769 constant integer or has a mode the same size. */
10770 if (GET_MODE_SIZE (omode) > UNITS_PER_WORD
10771 && ! ((imode == VOIDmode
10772 && (CONST_INT_P (x)
10773 || GET_CODE (x) == CONST_DOUBLE))
10774 || isize == osize))
10777 /* X might be a paradoxical (subreg (mem)). In that case, gen_lowpart
10778 won't know what to do. So we will strip off the SUBREG here and
10779 process normally. */
10780 if (GET_CODE (x) == SUBREG && MEM_P (SUBREG_REG (x)))
10782 x = SUBREG_REG (x);
10784 /* For use in case we fall down into the address adjustments
10785 further below, we need to adjust the known mode and size of
10786 x; imode and isize, since we just adjusted x. */
10787 imode = GET_MODE (x);
10789 if (imode == omode)
10792 isize = GET_MODE_SIZE (imode);
10795 result = gen_lowpart_common (omode, x);
10804 /* Refuse to work on a volatile memory ref or one with a mode-dependent
10806 if (MEM_VOLATILE_P (x) || mode_dependent_address_p (XEXP (x, 0)))
10809 /* If we want to refer to something bigger than the original memref,
10810 generate a paradoxical subreg instead. That will force a reload
10811 of the original memref X. */
10813 return gen_rtx_SUBREG (omode, x, 0);
10815 if (WORDS_BIG_ENDIAN)
10816 offset = MAX (isize, UNITS_PER_WORD) - MAX (osize, UNITS_PER_WORD);
10818 /* Adjust the address so that the address-after-the-data is
10820 if (BYTES_BIG_ENDIAN)
10821 offset -= MIN (UNITS_PER_WORD, osize) - MIN (UNITS_PER_WORD, isize);
10823 return adjust_address_nv (x, omode, offset);
10826 /* If X is a comparison operator, rewrite it in a new mode. This
10827 probably won't match, but may allow further simplifications. */
10828 else if (COMPARISON_P (x))
10829 return gen_rtx_fmt_ee (GET_CODE (x), omode, XEXP (x, 0), XEXP (x, 1));
10831 /* If we couldn't simplify X any other way, just enclose it in a
10832 SUBREG. Normally, this SUBREG won't match, but some patterns may
10833 include an explicit SUBREG or we may simplify it further in combine. */
10839 offset = subreg_lowpart_offset (omode, imode);
10840 if (imode == VOIDmode)
10842 imode = int_mode_for_mode (omode);
10843 x = gen_lowpart_common (imode, x);
10847 res = simplify_gen_subreg (omode, x, imode, offset);
10853 return gen_rtx_CLOBBER (omode, const0_rtx);
10856 /* Try to simplify a comparison between OP0 and a constant OP1,
10857 where CODE is the comparison code that will be tested, into a
10858 (CODE OP0 const0_rtx) form.
10860 The result is a possibly different comparison code to use.
10861 *POP1 may be updated. */
10863 static enum rtx_code
10864 simplify_compare_const (enum rtx_code code, rtx op0, rtx *pop1)
10866 enum machine_mode mode = GET_MODE (op0);
10867 unsigned int mode_width = GET_MODE_BITSIZE (mode);
10868 HOST_WIDE_INT const_op = INTVAL (*pop1);
10870 /* Get the constant we are comparing against and turn off all bits
10871 not on in our mode. */
10872 if (mode != VOIDmode)
10873 const_op = trunc_int_for_mode (const_op, mode);
10875 /* If we are comparing against a constant power of two and the value
10876 being compared can only have that single bit nonzero (e.g., it was
10877 `and'ed with that bit), we can replace this with a comparison
10880 && (code == EQ || code == NE || code == GE || code == GEU
10881 || code == LT || code == LTU)
10882 && mode_width <= HOST_BITS_PER_WIDE_INT
10883 && exact_log2 (const_op) >= 0
10884 && nonzero_bits (op0, mode) == (unsigned HOST_WIDE_INT) const_op)
10886 code = (code == EQ || code == GE || code == GEU ? NE : EQ);
10890 /* Similarly, if we are comparing a value known to be either -1 or
10891 0 with -1, change it to the opposite comparison against zero. */
10893 && (code == EQ || code == NE || code == GT || code == LE
10894 || code == GEU || code == LTU)
10895 && num_sign_bit_copies (op0, mode) == mode_width)
10897 code = (code == EQ || code == LE || code == GEU ? NE : EQ);
10901 /* Do some canonicalizations based on the comparison code. We prefer
10902 comparisons against zero and then prefer equality comparisons.
10903 If we can reduce the size of a constant, we will do that too. */
10907 /* < C is equivalent to <= (C - 1) */
10912 /* ... fall through to LE case below. */
10918 /* <= C is equivalent to < (C + 1); we do this for C < 0 */
10925 /* If we are doing a <= 0 comparison on a value known to have
10926 a zero sign bit, we can replace this with == 0. */
10927 else if (const_op == 0
10928 && mode_width <= HOST_BITS_PER_WIDE_INT
10929 && (nonzero_bits (op0, mode)
10930 & ((unsigned HOST_WIDE_INT) 1 << (mode_width - 1)))
10936 /* >= C is equivalent to > (C - 1). */
10941 /* ... fall through to GT below. */
10947 /* > C is equivalent to >= (C + 1); we do this for C < 0. */
10954 /* If we are doing a > 0 comparison on a value known to have
10955 a zero sign bit, we can replace this with != 0. */
10956 else if (const_op == 0
10957 && mode_width <= HOST_BITS_PER_WIDE_INT
10958 && (nonzero_bits (op0, mode)
10959 & ((unsigned HOST_WIDE_INT) 1 << (mode_width - 1)))
10965 /* < C is equivalent to <= (C - 1). */
10970 /* ... fall through ... */
10972 /* (unsigned) < 0x80000000 is equivalent to >= 0. */
10973 else if (mode_width <= HOST_BITS_PER_WIDE_INT
10974 && (unsigned HOST_WIDE_INT) const_op
10975 == (unsigned HOST_WIDE_INT) 1 << (mode_width - 1))
10985 /* unsigned <= 0 is equivalent to == 0 */
10988 /* (unsigned) <= 0x7fffffff is equivalent to >= 0. */
10989 else if (mode_width <= HOST_BITS_PER_WIDE_INT
10990 && (unsigned HOST_WIDE_INT) const_op
10991 == ((unsigned HOST_WIDE_INT) 1 << (mode_width - 1)) - 1)
10999 /* >= C is equivalent to > (C - 1). */
11004 /* ... fall through ... */
11007 /* (unsigned) >= 0x80000000 is equivalent to < 0. */
11008 else if (mode_width <= HOST_BITS_PER_WIDE_INT
11009 && (unsigned HOST_WIDE_INT) const_op
11010 == (unsigned HOST_WIDE_INT) 1 << (mode_width - 1))
11020 /* unsigned > 0 is equivalent to != 0 */
11023 /* (unsigned) > 0x7fffffff is equivalent to < 0. */
11024 else if (mode_width <= HOST_BITS_PER_WIDE_INT
11025 && (unsigned HOST_WIDE_INT) const_op
11026 == ((unsigned HOST_WIDE_INT) 1 << (mode_width - 1)) - 1)
11037 *pop1 = GEN_INT (const_op);
11041 /* Simplify a comparison between *POP0 and *POP1 where CODE is the
11042 comparison code that will be tested.
11044 The result is a possibly different comparison code to use. *POP0 and
11045 *POP1 may be updated.
11047 It is possible that we might detect that a comparison is either always
11048 true or always false. However, we do not perform general constant
11049 folding in combine, so this knowledge isn't useful. Such tautologies
11050 should have been detected earlier. Hence we ignore all such cases. */
11052 static enum rtx_code
11053 simplify_comparison (enum rtx_code code, rtx *pop0, rtx *pop1)
11059 enum machine_mode mode, tmode;
11061 /* Try a few ways of applying the same transformation to both operands. */
11064 #ifndef WORD_REGISTER_OPERATIONS
11065 /* The test below this one won't handle SIGN_EXTENDs on these machines,
11066 so check specially. */
11067 if (code != GTU && code != GEU && code != LTU && code != LEU
11068 && GET_CODE (op0) == ASHIFTRT && GET_CODE (op1) == ASHIFTRT
11069 && GET_CODE (XEXP (op0, 0)) == ASHIFT
11070 && GET_CODE (XEXP (op1, 0)) == ASHIFT
11071 && GET_CODE (XEXP (XEXP (op0, 0), 0)) == SUBREG
11072 && GET_CODE (XEXP (XEXP (op1, 0), 0)) == SUBREG
11073 && (GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0)))
11074 == GET_MODE (SUBREG_REG (XEXP (XEXP (op1, 0), 0))))
11075 && CONST_INT_P (XEXP (op0, 1))
11076 && XEXP (op0, 1) == XEXP (op1, 1)
11077 && XEXP (op0, 1) == XEXP (XEXP (op0, 0), 1)
11078 && XEXP (op0, 1) == XEXP (XEXP (op1, 0), 1)
11079 && (INTVAL (XEXP (op0, 1))
11080 == (GET_MODE_BITSIZE (GET_MODE (op0))
11081 - (GET_MODE_BITSIZE
11082 (GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0))))))))
11084 op0 = SUBREG_REG (XEXP (XEXP (op0, 0), 0));
11085 op1 = SUBREG_REG (XEXP (XEXP (op1, 0), 0));
11089 /* If both operands are the same constant shift, see if we can ignore the
11090 shift. We can if the shift is a rotate or if the bits shifted out of
11091 this shift are known to be zero for both inputs and if the type of
11092 comparison is compatible with the shift. */
11093 if (GET_CODE (op0) == GET_CODE (op1)
11094 && GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
11095 && ((GET_CODE (op0) == ROTATE && (code == NE || code == EQ))
11096 || ((GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFT)
11097 && (code != GT && code != LT && code != GE && code != LE))
11098 || (GET_CODE (op0) == ASHIFTRT
11099 && (code != GTU && code != LTU
11100 && code != GEU && code != LEU)))
11101 && CONST_INT_P (XEXP (op0, 1))
11102 && INTVAL (XEXP (op0, 1)) >= 0
11103 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT
11104 && XEXP (op0, 1) == XEXP (op1, 1))
11106 enum machine_mode mode = GET_MODE (op0);
11107 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
11108 int shift_count = INTVAL (XEXP (op0, 1));
11110 if (GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFTRT)
11111 mask &= (mask >> shift_count) << shift_count;
11112 else if (GET_CODE (op0) == ASHIFT)
11113 mask = (mask & (mask << shift_count)) >> shift_count;
11115 if ((nonzero_bits (XEXP (op0, 0), mode) & ~mask) == 0
11116 && (nonzero_bits (XEXP (op1, 0), mode) & ~mask) == 0)
11117 op0 = XEXP (op0, 0), op1 = XEXP (op1, 0);
11122 /* If both operands are AND's of a paradoxical SUBREG by constant, the
11123 SUBREGs are of the same mode, and, in both cases, the AND would
11124 be redundant if the comparison was done in the narrower mode,
11125 do the comparison in the narrower mode (e.g., we are AND'ing with 1
11126 and the operand's possibly nonzero bits are 0xffffff01; in that case
11127 if we only care about QImode, we don't need the AND). This case
11128 occurs if the output mode of an scc insn is not SImode and
11129 STORE_FLAG_VALUE == 1 (e.g., the 386).
11131 Similarly, check for a case where the AND's are ZERO_EXTEND
11132 operations from some narrower mode even though a SUBREG is not
11135 else if (GET_CODE (op0) == AND && GET_CODE (op1) == AND
11136 && CONST_INT_P (XEXP (op0, 1))
11137 && CONST_INT_P (XEXP (op1, 1)))
11139 rtx inner_op0 = XEXP (op0, 0);
11140 rtx inner_op1 = XEXP (op1, 0);
11141 HOST_WIDE_INT c0 = INTVAL (XEXP (op0, 1));
11142 HOST_WIDE_INT c1 = INTVAL (XEXP (op1, 1));
11145 if (GET_CODE (inner_op0) == SUBREG && GET_CODE (inner_op1) == SUBREG
11146 && (GET_MODE_SIZE (GET_MODE (inner_op0))
11147 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (inner_op0))))
11148 && (GET_MODE (SUBREG_REG (inner_op0))
11149 == GET_MODE (SUBREG_REG (inner_op1)))
11150 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (inner_op0)))
11151 <= HOST_BITS_PER_WIDE_INT)
11152 && (0 == ((~c0) & nonzero_bits (SUBREG_REG (inner_op0),
11153 GET_MODE (SUBREG_REG (inner_op0)))))
11154 && (0 == ((~c1) & nonzero_bits (SUBREG_REG (inner_op1),
11155 GET_MODE (SUBREG_REG (inner_op1))))))
11157 op0 = SUBREG_REG (inner_op0);
11158 op1 = SUBREG_REG (inner_op1);
11160 /* The resulting comparison is always unsigned since we masked
11161 off the original sign bit. */
11162 code = unsigned_condition (code);
11168 for (tmode = GET_CLASS_NARROWEST_MODE
11169 (GET_MODE_CLASS (GET_MODE (op0)));
11170 tmode != GET_MODE (op0); tmode = GET_MODE_WIDER_MODE (tmode))
11171 if ((unsigned HOST_WIDE_INT) c0 == GET_MODE_MASK (tmode))
11173 op0 = gen_lowpart (tmode, inner_op0);
11174 op1 = gen_lowpart (tmode, inner_op1);
11175 code = unsigned_condition (code);
11184 /* If both operands are NOT, we can strip off the outer operation
11185 and adjust the comparison code for swapped operands; similarly for
11186 NEG, except that this must be an equality comparison. */
11187 else if ((GET_CODE (op0) == NOT && GET_CODE (op1) == NOT)
11188 || (GET_CODE (op0) == NEG && GET_CODE (op1) == NEG
11189 && (code == EQ || code == NE)))
11190 op0 = XEXP (op0, 0), op1 = XEXP (op1, 0), code = swap_condition (code);
11196 /* If the first operand is a constant, swap the operands and adjust the
11197 comparison code appropriately, but don't do this if the second operand
11198 is already a constant integer. */
11199 if (swap_commutative_operands_p (op0, op1))
11201 tem = op0, op0 = op1, op1 = tem;
11202 code = swap_condition (code);
11205 /* We now enter a loop during which we will try to simplify the comparison.
11206 For the most part, we only are concerned with comparisons with zero,
11207 but some things may really be comparisons with zero but not start
11208 out looking that way. */
11210 while (CONST_INT_P (op1))
11212 enum machine_mode mode = GET_MODE (op0);
11213 unsigned int mode_width = GET_MODE_BITSIZE (mode);
11214 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
11215 int equality_comparison_p;
11216 int sign_bit_comparison_p;
11217 int unsigned_comparison_p;
11218 HOST_WIDE_INT const_op;
11220 /* We only want to handle integral modes. This catches VOIDmode,
11221 CCmode, and the floating-point modes. An exception is that we
11222 can handle VOIDmode if OP0 is a COMPARE or a comparison
11225 if (GET_MODE_CLASS (mode) != MODE_INT
11226 && ! (mode == VOIDmode
11227 && (GET_CODE (op0) == COMPARE || COMPARISON_P (op0))))
11230 /* Try to simplify the compare to constant, possibly changing the
11231 comparison op, and/or changing op1 to zero. */
11232 code = simplify_compare_const (code, op0, &op1);
11233 const_op = INTVAL (op1);
11235 /* Compute some predicates to simplify code below. */
11237 equality_comparison_p = (code == EQ || code == NE);
11238 sign_bit_comparison_p = ((code == LT || code == GE) && const_op == 0);
11239 unsigned_comparison_p = (code == LTU || code == LEU || code == GTU
11242 /* If this is a sign bit comparison and we can do arithmetic in
11243 MODE, say that we will only be needing the sign bit of OP0. */
11244 if (sign_bit_comparison_p
11245 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
11246 op0 = force_to_mode (op0, mode,
11247 (unsigned HOST_WIDE_INT) 1
11248 << (GET_MODE_BITSIZE (mode) - 1),
11251 /* Now try cases based on the opcode of OP0. If none of the cases
11252 does a "continue", we exit this loop immediately after the
11255 switch (GET_CODE (op0))
11258 /* If we are extracting a single bit from a variable position in
11259 a constant that has only a single bit set and are comparing it
11260 with zero, we can convert this into an equality comparison
11261 between the position and the location of the single bit. */
11262 /* Except we can't if SHIFT_COUNT_TRUNCATED is set, since we might
11263 have already reduced the shift count modulo the word size. */
11264 if (!SHIFT_COUNT_TRUNCATED
11265 && CONST_INT_P (XEXP (op0, 0))
11266 && XEXP (op0, 1) == const1_rtx
11267 && equality_comparison_p && const_op == 0
11268 && (i = exact_log2 (UINTVAL (XEXP (op0, 0)))) >= 0)
11270 if (BITS_BIG_ENDIAN)
11272 enum machine_mode new_mode
11273 = mode_for_extraction (EP_extzv, 1);
11274 if (new_mode == MAX_MACHINE_MODE)
11275 i = BITS_PER_WORD - 1 - i;
11279 i = (GET_MODE_BITSIZE (mode) - 1 - i);
11283 op0 = XEXP (op0, 2);
11287 /* Result is nonzero iff shift count is equal to I. */
11288 code = reverse_condition (code);
11292 /* ... fall through ... */
11295 tem = expand_compound_operation (op0);
11304 /* If testing for equality, we can take the NOT of the constant. */
11305 if (equality_comparison_p
11306 && (tem = simplify_unary_operation (NOT, mode, op1, mode)) != 0)
11308 op0 = XEXP (op0, 0);
11313 /* If just looking at the sign bit, reverse the sense of the
11315 if (sign_bit_comparison_p)
11317 op0 = XEXP (op0, 0);
11318 code = (code == GE ? LT : GE);
11324 /* If testing for equality, we can take the NEG of the constant. */
11325 if (equality_comparison_p
11326 && (tem = simplify_unary_operation (NEG, mode, op1, mode)) != 0)
11328 op0 = XEXP (op0, 0);
11333 /* The remaining cases only apply to comparisons with zero. */
11337 /* When X is ABS or is known positive,
11338 (neg X) is < 0 if and only if X != 0. */
11340 if (sign_bit_comparison_p
11341 && (GET_CODE (XEXP (op0, 0)) == ABS
11342 || (mode_width <= HOST_BITS_PER_WIDE_INT
11343 && (nonzero_bits (XEXP (op0, 0), mode)
11344 & ((unsigned HOST_WIDE_INT) 1 << (mode_width - 1)))
11347 op0 = XEXP (op0, 0);
11348 code = (code == LT ? NE : EQ);
11352 /* If we have NEG of something whose two high-order bits are the
11353 same, we know that "(-a) < 0" is equivalent to "a > 0". */
11354 if (num_sign_bit_copies (op0, mode) >= 2)
11356 op0 = XEXP (op0, 0);
11357 code = swap_condition (code);
11363 /* If we are testing equality and our count is a constant, we
11364 can perform the inverse operation on our RHS. */
11365 if (equality_comparison_p && CONST_INT_P (XEXP (op0, 1))
11366 && (tem = simplify_binary_operation (ROTATERT, mode,
11367 op1, XEXP (op0, 1))) != 0)
11369 op0 = XEXP (op0, 0);
11374 /* If we are doing a < 0 or >= 0 comparison, it means we are testing
11375 a particular bit. Convert it to an AND of a constant of that
11376 bit. This will be converted into a ZERO_EXTRACT. */
11377 if (const_op == 0 && sign_bit_comparison_p
11378 && CONST_INT_P (XEXP (op0, 1))
11379 && mode_width <= HOST_BITS_PER_WIDE_INT)
11381 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
11382 ((unsigned HOST_WIDE_INT) 1
11384 - INTVAL (XEXP (op0, 1)))));
11385 code = (code == LT ? NE : EQ);
11389 /* Fall through. */
11392 /* ABS is ignorable inside an equality comparison with zero. */
11393 if (const_op == 0 && equality_comparison_p)
11395 op0 = XEXP (op0, 0);
11401 /* Can simplify (compare (zero/sign_extend FOO) CONST) to
11402 (compare FOO CONST) if CONST fits in FOO's mode and we
11403 are either testing inequality or have an unsigned
11404 comparison with ZERO_EXTEND or a signed comparison with
11405 SIGN_EXTEND. But don't do it if we don't have a compare
11406 insn of the given mode, since we'd have to revert it
11407 later on, and then we wouldn't know whether to sign- or
11409 mode = GET_MODE (XEXP (op0, 0));
11410 if (mode != VOIDmode && GET_MODE_CLASS (mode) == MODE_INT
11411 && ! unsigned_comparison_p
11412 && val_signbit_known_clear_p (mode, const_op)
11413 && have_insn_for (COMPARE, mode))
11415 op0 = XEXP (op0, 0);
11421 /* Check for the case where we are comparing A - C1 with C2, that is
11423 (subreg:MODE (plus (A) (-C1))) op (C2)
11425 with C1 a constant, and try to lift the SUBREG, i.e. to do the
11426 comparison in the wider mode. One of the following two conditions
11427 must be true in order for this to be valid:
11429 1. The mode extension results in the same bit pattern being added
11430 on both sides and the comparison is equality or unsigned. As
11431 C2 has been truncated to fit in MODE, the pattern can only be
11434 2. The mode extension results in the sign bit being copied on
11437 The difficulty here is that we have predicates for A but not for
11438 (A - C1) so we need to check that C1 is within proper bounds so
11439 as to perturbate A as little as possible. */
11441 if (mode_width <= HOST_BITS_PER_WIDE_INT
11442 && subreg_lowpart_p (op0)
11443 && GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0))) > mode_width
11444 && GET_CODE (SUBREG_REG (op0)) == PLUS
11445 && CONST_INT_P (XEXP (SUBREG_REG (op0), 1)))
11447 enum machine_mode inner_mode = GET_MODE (SUBREG_REG (op0));
11448 rtx a = XEXP (SUBREG_REG (op0), 0);
11449 HOST_WIDE_INT c1 = -INTVAL (XEXP (SUBREG_REG (op0), 1));
11452 && (unsigned HOST_WIDE_INT) c1
11453 < (unsigned HOST_WIDE_INT) 1 << (mode_width - 1)
11454 && (equality_comparison_p || unsigned_comparison_p)
11455 /* (A - C1) zero-extends if it is positive and sign-extends
11456 if it is negative, C2 both zero- and sign-extends. */
11457 && ((0 == (nonzero_bits (a, inner_mode)
11458 & ~GET_MODE_MASK (mode))
11460 /* (A - C1) sign-extends if it is positive and 1-extends
11461 if it is negative, C2 both sign- and 1-extends. */
11462 || (num_sign_bit_copies (a, inner_mode)
11463 > (unsigned int) (GET_MODE_BITSIZE (inner_mode)
11466 || ((unsigned HOST_WIDE_INT) c1
11467 < (unsigned HOST_WIDE_INT) 1 << (mode_width - 2)
11468 /* (A - C1) always sign-extends, like C2. */
11469 && num_sign_bit_copies (a, inner_mode)
11470 > (unsigned int) (GET_MODE_BITSIZE (inner_mode)
11471 - (mode_width - 1))))
11473 op0 = SUBREG_REG (op0);
11478 /* If the inner mode is narrower and we are extracting the low part,
11479 we can treat the SUBREG as if it were a ZERO_EXTEND. */
11480 if (subreg_lowpart_p (op0)
11481 && GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0))) < mode_width)
11482 /* Fall through */ ;
11486 /* ... fall through ... */
11489 mode = GET_MODE (XEXP (op0, 0));
11490 if (mode != VOIDmode && GET_MODE_CLASS (mode) == MODE_INT
11491 && (unsigned_comparison_p || equality_comparison_p)
11492 && (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
11493 && ((unsigned HOST_WIDE_INT) const_op < GET_MODE_MASK (mode))
11494 && have_insn_for (COMPARE, mode))
11496 op0 = XEXP (op0, 0);
11502 /* (eq (plus X A) B) -> (eq X (minus B A)). We can only do
11503 this for equality comparisons due to pathological cases involving
11505 if (equality_comparison_p
11506 && 0 != (tem = simplify_binary_operation (MINUS, mode,
11507 op1, XEXP (op0, 1))))
11509 op0 = XEXP (op0, 0);
11514 /* (plus (abs X) (const_int -1)) is < 0 if and only if X == 0. */
11515 if (const_op == 0 && XEXP (op0, 1) == constm1_rtx
11516 && GET_CODE (XEXP (op0, 0)) == ABS && sign_bit_comparison_p)
11518 op0 = XEXP (XEXP (op0, 0), 0);
11519 code = (code == LT ? EQ : NE);
11525 /* We used to optimize signed comparisons against zero, but that
11526 was incorrect. Unsigned comparisons against zero (GTU, LEU)
11527 arrive here as equality comparisons, or (GEU, LTU) are
11528 optimized away. No need to special-case them. */
11530 /* (eq (minus A B) C) -> (eq A (plus B C)) or
11531 (eq B (minus A C)), whichever simplifies. We can only do
11532 this for equality comparisons due to pathological cases involving
11534 if (equality_comparison_p
11535 && 0 != (tem = simplify_binary_operation (PLUS, mode,
11536 XEXP (op0, 1), op1)))
11538 op0 = XEXP (op0, 0);
11543 if (equality_comparison_p
11544 && 0 != (tem = simplify_binary_operation (MINUS, mode,
11545 XEXP (op0, 0), op1)))
11547 op0 = XEXP (op0, 1);
11552 /* The sign bit of (minus (ashiftrt X C) X), where C is the number
11553 of bits in X minus 1, is one iff X > 0. */
11554 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == ASHIFTRT
11555 && CONST_INT_P (XEXP (XEXP (op0, 0), 1))
11556 && UINTVAL (XEXP (XEXP (op0, 0), 1)) == mode_width - 1
11557 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
11559 op0 = XEXP (op0, 1);
11560 code = (code == GE ? LE : GT);
11566 /* (eq (xor A B) C) -> (eq A (xor B C)). This is a simplification
11567 if C is zero or B is a constant. */
11568 if (equality_comparison_p
11569 && 0 != (tem = simplify_binary_operation (XOR, mode,
11570 XEXP (op0, 1), op1)))
11572 op0 = XEXP (op0, 0);
11579 case UNEQ: case LTGT:
11580 case LT: case LTU: case UNLT: case LE: case LEU: case UNLE:
11581 case GT: case GTU: case UNGT: case GE: case GEU: case UNGE:
11582 case UNORDERED: case ORDERED:
11583 /* We can't do anything if OP0 is a condition code value, rather
11584 than an actual data value. */
11586 || CC0_P (XEXP (op0, 0))
11587 || GET_MODE_CLASS (GET_MODE (XEXP (op0, 0))) == MODE_CC)
11590 /* Get the two operands being compared. */
11591 if (GET_CODE (XEXP (op0, 0)) == COMPARE)
11592 tem = XEXP (XEXP (op0, 0), 0), tem1 = XEXP (XEXP (op0, 0), 1);
11594 tem = XEXP (op0, 0), tem1 = XEXP (op0, 1);
11596 /* Check for the cases where we simply want the result of the
11597 earlier test or the opposite of that result. */
11598 if (code == NE || code == EQ
11599 || (val_signbit_known_set_p (GET_MODE (op0), STORE_FLAG_VALUE)
11600 && (code == LT || code == GE)))
11602 enum rtx_code new_code;
11603 if (code == LT || code == NE)
11604 new_code = GET_CODE (op0);
11606 new_code = reversed_comparison_code (op0, NULL);
11608 if (new_code != UNKNOWN)
11619 /* The sign bit of (ior (plus X (const_int -1)) X) is nonzero
11621 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == PLUS
11622 && XEXP (XEXP (op0, 0), 1) == constm1_rtx
11623 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
11625 op0 = XEXP (op0, 1);
11626 code = (code == GE ? GT : LE);
11632 /* Convert (and (xshift 1 X) Y) to (and (lshiftrt Y X) 1). This
11633 will be converted to a ZERO_EXTRACT later. */
11634 if (const_op == 0 && equality_comparison_p
11635 && GET_CODE (XEXP (op0, 0)) == ASHIFT
11636 && XEXP (XEXP (op0, 0), 0) == const1_rtx)
11638 op0 = gen_rtx_LSHIFTRT (mode, XEXP (op0, 1),
11639 XEXP (XEXP (op0, 0), 1));
11640 op0 = simplify_and_const_int (NULL_RTX, mode, op0, 1);
11644 /* If we are comparing (and (lshiftrt X C1) C2) for equality with
11645 zero and X is a comparison and C1 and C2 describe only bits set
11646 in STORE_FLAG_VALUE, we can compare with X. */
11647 if (const_op == 0 && equality_comparison_p
11648 && mode_width <= HOST_BITS_PER_WIDE_INT
11649 && CONST_INT_P (XEXP (op0, 1))
11650 && GET_CODE (XEXP (op0, 0)) == LSHIFTRT
11651 && CONST_INT_P (XEXP (XEXP (op0, 0), 1))
11652 && INTVAL (XEXP (XEXP (op0, 0), 1)) >= 0
11653 && INTVAL (XEXP (XEXP (op0, 0), 1)) < HOST_BITS_PER_WIDE_INT)
11655 mask = ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
11656 << INTVAL (XEXP (XEXP (op0, 0), 1)));
11657 if ((~STORE_FLAG_VALUE & mask) == 0
11658 && (COMPARISON_P (XEXP (XEXP (op0, 0), 0))
11659 || ((tem = get_last_value (XEXP (XEXP (op0, 0), 0))) != 0
11660 && COMPARISON_P (tem))))
11662 op0 = XEXP (XEXP (op0, 0), 0);
11667 /* If we are doing an equality comparison of an AND of a bit equal
11668 to the sign bit, replace this with a LT or GE comparison of
11669 the underlying value. */
11670 if (equality_comparison_p
11672 && CONST_INT_P (XEXP (op0, 1))
11673 && mode_width <= HOST_BITS_PER_WIDE_INT
11674 && ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
11675 == (unsigned HOST_WIDE_INT) 1 << (mode_width - 1)))
11677 op0 = XEXP (op0, 0);
11678 code = (code == EQ ? GE : LT);
11682 /* If this AND operation is really a ZERO_EXTEND from a narrower
11683 mode, the constant fits within that mode, and this is either an
11684 equality or unsigned comparison, try to do this comparison in
11689 (ne:DI (and:DI (reg:DI 4) (const_int 0xffffffff)) (const_int 0))
11690 -> (ne:DI (reg:SI 4) (const_int 0))
11692 unless TRULY_NOOP_TRUNCATION allows it or the register is
11693 known to hold a value of the required mode the
11694 transformation is invalid. */
11695 if ((equality_comparison_p || unsigned_comparison_p)
11696 && CONST_INT_P (XEXP (op0, 1))
11697 && (i = exact_log2 ((UINTVAL (XEXP (op0, 1))
11698 & GET_MODE_MASK (mode))
11700 && const_op >> i == 0
11701 && (tmode = mode_for_size (i, MODE_INT, 1)) != BLKmode
11702 && (TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (tmode),
11703 GET_MODE_BITSIZE (GET_MODE (op0)))
11704 || (REG_P (XEXP (op0, 0))
11705 && reg_truncated_to_mode (tmode, XEXP (op0, 0)))))
11707 op0 = gen_lowpart (tmode, XEXP (op0, 0));
11711 /* If this is (and:M1 (subreg:M2 X 0) (const_int C1)) where C1
11712 fits in both M1 and M2 and the SUBREG is either paradoxical
11713 or represents the low part, permute the SUBREG and the AND
11715 if (GET_CODE (XEXP (op0, 0)) == SUBREG)
11717 unsigned HOST_WIDE_INT c1;
11718 tmode = GET_MODE (SUBREG_REG (XEXP (op0, 0)));
11719 /* Require an integral mode, to avoid creating something like
11721 if (SCALAR_INT_MODE_P (tmode)
11722 /* It is unsafe to commute the AND into the SUBREG if the
11723 SUBREG is paradoxical and WORD_REGISTER_OPERATIONS is
11724 not defined. As originally written the upper bits
11725 have a defined value due to the AND operation.
11726 However, if we commute the AND inside the SUBREG then
11727 they no longer have defined values and the meaning of
11728 the code has been changed. */
11730 #ifdef WORD_REGISTER_OPERATIONS
11731 || (mode_width > GET_MODE_BITSIZE (tmode)
11732 && mode_width <= BITS_PER_WORD)
11734 || (mode_width <= GET_MODE_BITSIZE (tmode)
11735 && subreg_lowpart_p (XEXP (op0, 0))))
11736 && CONST_INT_P (XEXP (op0, 1))
11737 && mode_width <= HOST_BITS_PER_WIDE_INT
11738 && GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT
11739 && ((c1 = INTVAL (XEXP (op0, 1))) & ~mask) == 0
11740 && (c1 & ~GET_MODE_MASK (tmode)) == 0
11742 && c1 != GET_MODE_MASK (tmode))
11744 op0 = simplify_gen_binary (AND, tmode,
11745 SUBREG_REG (XEXP (op0, 0)),
11746 gen_int_mode (c1, tmode));
11747 op0 = gen_lowpart (mode, op0);
11752 /* Convert (ne (and (not X) 1) 0) to (eq (and X 1) 0). */
11753 if (const_op == 0 && equality_comparison_p
11754 && XEXP (op0, 1) == const1_rtx
11755 && GET_CODE (XEXP (op0, 0)) == NOT)
11757 op0 = simplify_and_const_int (NULL_RTX, mode,
11758 XEXP (XEXP (op0, 0), 0), 1);
11759 code = (code == NE ? EQ : NE);
11763 /* Convert (ne (and (lshiftrt (not X)) 1) 0) to
11764 (eq (and (lshiftrt X) 1) 0).
11765 Also handle the case where (not X) is expressed using xor. */
11766 if (const_op == 0 && equality_comparison_p
11767 && XEXP (op0, 1) == const1_rtx
11768 && GET_CODE (XEXP (op0, 0)) == LSHIFTRT)
11770 rtx shift_op = XEXP (XEXP (op0, 0), 0);
11771 rtx shift_count = XEXP (XEXP (op0, 0), 1);
11773 if (GET_CODE (shift_op) == NOT
11774 || (GET_CODE (shift_op) == XOR
11775 && CONST_INT_P (XEXP (shift_op, 1))
11776 && CONST_INT_P (shift_count)
11777 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
11778 && (UINTVAL (XEXP (shift_op, 1))
11779 == (unsigned HOST_WIDE_INT) 1
11780 << INTVAL (shift_count))))
11783 = gen_rtx_LSHIFTRT (mode, XEXP (shift_op, 0), shift_count);
11784 op0 = simplify_and_const_int (NULL_RTX, mode, op0, 1);
11785 code = (code == NE ? EQ : NE);
11792 /* If we have (compare (ashift FOO N) (const_int C)) and
11793 the high order N bits of FOO (N+1 if an inequality comparison)
11794 are known to be zero, we can do this by comparing FOO with C
11795 shifted right N bits so long as the low-order N bits of C are
11797 if (CONST_INT_P (XEXP (op0, 1))
11798 && INTVAL (XEXP (op0, 1)) >= 0
11799 && ((INTVAL (XEXP (op0, 1)) + ! equality_comparison_p)
11800 < HOST_BITS_PER_WIDE_INT)
11801 && (((unsigned HOST_WIDE_INT) const_op
11802 & (((unsigned HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1)))
11804 && mode_width <= HOST_BITS_PER_WIDE_INT
11805 && (nonzero_bits (XEXP (op0, 0), mode)
11806 & ~(mask >> (INTVAL (XEXP (op0, 1))
11807 + ! equality_comparison_p))) == 0)
11809 /* We must perform a logical shift, not an arithmetic one,
11810 as we want the top N bits of C to be zero. */
11811 unsigned HOST_WIDE_INT temp = const_op & GET_MODE_MASK (mode);
11813 temp >>= INTVAL (XEXP (op0, 1));
11814 op1 = gen_int_mode (temp, mode);
11815 op0 = XEXP (op0, 0);
11819 /* If we are doing a sign bit comparison, it means we are testing
11820 a particular bit. Convert it to the appropriate AND. */
11821 if (sign_bit_comparison_p && CONST_INT_P (XEXP (op0, 1))
11822 && mode_width <= HOST_BITS_PER_WIDE_INT)
11824 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
11825 ((unsigned HOST_WIDE_INT) 1
11827 - INTVAL (XEXP (op0, 1)))));
11828 code = (code == LT ? NE : EQ);
11832 /* If this an equality comparison with zero and we are shifting
11833 the low bit to the sign bit, we can convert this to an AND of the
11835 if (const_op == 0 && equality_comparison_p
11836 && CONST_INT_P (XEXP (op0, 1))
11837 && UINTVAL (XEXP (op0, 1)) == mode_width - 1)
11839 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0), 1);
11845 /* If this is an equality comparison with zero, we can do this
11846 as a logical shift, which might be much simpler. */
11847 if (equality_comparison_p && const_op == 0
11848 && CONST_INT_P (XEXP (op0, 1)))
11850 op0 = simplify_shift_const (NULL_RTX, LSHIFTRT, mode,
11852 INTVAL (XEXP (op0, 1)));
11856 /* If OP0 is a sign extension and CODE is not an unsigned comparison,
11857 do the comparison in a narrower mode. */
11858 if (! unsigned_comparison_p
11859 && CONST_INT_P (XEXP (op0, 1))
11860 && GET_CODE (XEXP (op0, 0)) == ASHIFT
11861 && XEXP (op0, 1) == XEXP (XEXP (op0, 0), 1)
11862 && (tmode = mode_for_size (mode_width - INTVAL (XEXP (op0, 1)),
11863 MODE_INT, 1)) != BLKmode
11864 && (((unsigned HOST_WIDE_INT) const_op
11865 + (GET_MODE_MASK (tmode) >> 1) + 1)
11866 <= GET_MODE_MASK (tmode)))
11868 op0 = gen_lowpart (tmode, XEXP (XEXP (op0, 0), 0));
11872 /* Likewise if OP0 is a PLUS of a sign extension with a
11873 constant, which is usually represented with the PLUS
11874 between the shifts. */
11875 if (! unsigned_comparison_p
11876 && CONST_INT_P (XEXP (op0, 1))
11877 && GET_CODE (XEXP (op0, 0)) == PLUS
11878 && CONST_INT_P (XEXP (XEXP (op0, 0), 1))
11879 && GET_CODE (XEXP (XEXP (op0, 0), 0)) == ASHIFT
11880 && XEXP (op0, 1) == XEXP (XEXP (XEXP (op0, 0), 0), 1)
11881 && (tmode = mode_for_size (mode_width - INTVAL (XEXP (op0, 1)),
11882 MODE_INT, 1)) != BLKmode
11883 && (((unsigned HOST_WIDE_INT) const_op
11884 + (GET_MODE_MASK (tmode) >> 1) + 1)
11885 <= GET_MODE_MASK (tmode)))
11887 rtx inner = XEXP (XEXP (XEXP (op0, 0), 0), 0);
11888 rtx add_const = XEXP (XEXP (op0, 0), 1);
11889 rtx new_const = simplify_gen_binary (ASHIFTRT, GET_MODE (op0),
11890 add_const, XEXP (op0, 1));
11892 op0 = simplify_gen_binary (PLUS, tmode,
11893 gen_lowpart (tmode, inner),
11898 /* ... fall through ... */
11900 /* If we have (compare (xshiftrt FOO N) (const_int C)) and
11901 the low order N bits of FOO are known to be zero, we can do this
11902 by comparing FOO with C shifted left N bits so long as no
11903 overflow occurs. Even if the low order N bits of FOO aren't known
11904 to be zero, if the comparison is >= or < we can use the same
11905 optimization and for > or <= by setting all the low
11906 order N bits in the comparison constant. */
11907 if (CONST_INT_P (XEXP (op0, 1))
11908 && INTVAL (XEXP (op0, 1)) > 0
11909 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT
11910 && mode_width <= HOST_BITS_PER_WIDE_INT
11911 && (((unsigned HOST_WIDE_INT) const_op
11912 + (GET_CODE (op0) != LSHIFTRT
11913 ? ((GET_MODE_MASK (mode) >> INTVAL (XEXP (op0, 1)) >> 1)
11916 <= GET_MODE_MASK (mode) >> INTVAL (XEXP (op0, 1))))
11918 unsigned HOST_WIDE_INT low_bits
11919 = (nonzero_bits (XEXP (op0, 0), mode)
11920 & (((unsigned HOST_WIDE_INT) 1
11921 << INTVAL (XEXP (op0, 1))) - 1));
11922 if (low_bits == 0 || !equality_comparison_p)
11924 /* If the shift was logical, then we must make the condition
11926 if (GET_CODE (op0) == LSHIFTRT)
11927 code = unsigned_condition (code);
11929 const_op <<= INTVAL (XEXP (op0, 1));
11931 && (code == GT || code == GTU
11932 || code == LE || code == LEU))
11934 |= (((HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1))) - 1);
11935 op1 = GEN_INT (const_op);
11936 op0 = XEXP (op0, 0);
11941 /* If we are using this shift to extract just the sign bit, we
11942 can replace this with an LT or GE comparison. */
11944 && (equality_comparison_p || sign_bit_comparison_p)
11945 && CONST_INT_P (XEXP (op0, 1))
11946 && UINTVAL (XEXP (op0, 1)) == mode_width - 1)
11948 op0 = XEXP (op0, 0);
11949 code = (code == NE || code == GT ? LT : GE);
11961 /* Now make any compound operations involved in this comparison. Then,
11962 check for an outmost SUBREG on OP0 that is not doing anything or is
11963 paradoxical. The latter transformation must only be performed when
11964 it is known that the "extra" bits will be the same in op0 and op1 or
11965 that they don't matter. There are three cases to consider:
11967 1. SUBREG_REG (op0) is a register. In this case the bits are don't
11968 care bits and we can assume they have any convenient value. So
11969 making the transformation is safe.
11971 2. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is not defined.
11972 In this case the upper bits of op0 are undefined. We should not make
11973 the simplification in that case as we do not know the contents of
11976 3. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is defined and not
11977 UNKNOWN. In that case we know those bits are zeros or ones. We must
11978 also be sure that they are the same as the upper bits of op1.
11980 We can never remove a SUBREG for a non-equality comparison because
11981 the sign bit is in a different place in the underlying object. */
11983 op0 = make_compound_operation (op0, op1 == const0_rtx ? COMPARE : SET);
11984 op1 = make_compound_operation (op1, SET);
11986 if (GET_CODE (op0) == SUBREG && subreg_lowpart_p (op0)
11987 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
11988 && GET_MODE_CLASS (GET_MODE (SUBREG_REG (op0))) == MODE_INT
11989 && (code == NE || code == EQ))
11991 if (GET_MODE_SIZE (GET_MODE (op0))
11992 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (op0))))
11994 /* For paradoxical subregs, allow case 1 as above. Case 3 isn't
11996 if (REG_P (SUBREG_REG (op0)))
11998 op0 = SUBREG_REG (op0);
11999 op1 = gen_lowpart (GET_MODE (op0), op1);
12002 else if ((GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0)))
12003 <= HOST_BITS_PER_WIDE_INT)
12004 && (nonzero_bits (SUBREG_REG (op0),
12005 GET_MODE (SUBREG_REG (op0)))
12006 & ~GET_MODE_MASK (GET_MODE (op0))) == 0)
12008 tem = gen_lowpart (GET_MODE (SUBREG_REG (op0)), op1);
12010 if ((nonzero_bits (tem, GET_MODE (SUBREG_REG (op0)))
12011 & ~GET_MODE_MASK (GET_MODE (op0))) == 0)
12012 op0 = SUBREG_REG (op0), op1 = tem;
12016 /* We now do the opposite procedure: Some machines don't have compare
12017 insns in all modes. If OP0's mode is an integer mode smaller than a
12018 word and we can't do a compare in that mode, see if there is a larger
12019 mode for which we can do the compare. There are a number of cases in
12020 which we can use the wider mode. */
12022 mode = GET_MODE (op0);
12023 if (mode != VOIDmode && GET_MODE_CLASS (mode) == MODE_INT
12024 && GET_MODE_SIZE (mode) < UNITS_PER_WORD
12025 && ! have_insn_for (COMPARE, mode))
12026 for (tmode = GET_MODE_WIDER_MODE (mode);
12028 && GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT);
12029 tmode = GET_MODE_WIDER_MODE (tmode))
12030 if (have_insn_for (COMPARE, tmode))
12034 /* If this is a test for negative, we can make an explicit
12035 test of the sign bit. Test this first so we can use
12036 a paradoxical subreg to extend OP0. */
12038 if (op1 == const0_rtx && (code == LT || code == GE)
12039 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
12041 op0 = simplify_gen_binary (AND, tmode,
12042 gen_lowpart (tmode, op0),
12043 GEN_INT ((unsigned HOST_WIDE_INT) 1
12044 << (GET_MODE_BITSIZE (mode)
12046 code = (code == LT) ? NE : EQ;
12050 /* If the only nonzero bits in OP0 and OP1 are those in the
12051 narrower mode and this is an equality or unsigned comparison,
12052 we can use the wider mode. Similarly for sign-extended
12053 values, in which case it is true for all comparisons. */
12054 zero_extended = ((code == EQ || code == NE
12055 || code == GEU || code == GTU
12056 || code == LEU || code == LTU)
12057 && (nonzero_bits (op0, tmode)
12058 & ~GET_MODE_MASK (mode)) == 0
12059 && ((CONST_INT_P (op1)
12060 || (nonzero_bits (op1, tmode)
12061 & ~GET_MODE_MASK (mode)) == 0)));
12064 || ((num_sign_bit_copies (op0, tmode)
12065 > (unsigned int) (GET_MODE_BITSIZE (tmode)
12066 - GET_MODE_BITSIZE (mode)))
12067 && (num_sign_bit_copies (op1, tmode)
12068 > (unsigned int) (GET_MODE_BITSIZE (tmode)
12069 - GET_MODE_BITSIZE (mode)))))
12071 /* If OP0 is an AND and we don't have an AND in MODE either,
12072 make a new AND in the proper mode. */
12073 if (GET_CODE (op0) == AND
12074 && !have_insn_for (AND, mode))
12075 op0 = simplify_gen_binary (AND, tmode,
12076 gen_lowpart (tmode,
12078 gen_lowpart (tmode,
12084 op0 = simplify_gen_unary (ZERO_EXTEND, tmode, op0, mode);
12085 op1 = simplify_gen_unary (ZERO_EXTEND, tmode, op1, mode);
12089 op0 = simplify_gen_unary (SIGN_EXTEND, tmode, op0, mode);
12090 op1 = simplify_gen_unary (SIGN_EXTEND, tmode, op1, mode);
12097 #ifdef CANONICALIZE_COMPARISON
12098 /* If this machine only supports a subset of valid comparisons, see if we
12099 can convert an unsupported one into a supported one. */
12100 CANONICALIZE_COMPARISON (code, op0, op1);
12109 /* Utility function for record_value_for_reg. Count number of
12114 enum rtx_code code = GET_CODE (x);
12118 if (GET_RTX_CLASS (code) == '2'
12119 || GET_RTX_CLASS (code) == 'c')
12121 rtx x0 = XEXP (x, 0);
12122 rtx x1 = XEXP (x, 1);
12125 return 1 + 2 * count_rtxs (x0);
12127 if ((GET_RTX_CLASS (GET_CODE (x1)) == '2'
12128 || GET_RTX_CLASS (GET_CODE (x1)) == 'c')
12129 && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1)))
12130 return 2 + 2 * count_rtxs (x0)
12131 + count_rtxs (x == XEXP (x1, 0)
12132 ? XEXP (x1, 1) : XEXP (x1, 0));
12134 if ((GET_RTX_CLASS (GET_CODE (x0)) == '2'
12135 || GET_RTX_CLASS (GET_CODE (x0)) == 'c')
12136 && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1)))
12137 return 2 + 2 * count_rtxs (x1)
12138 + count_rtxs (x == XEXP (x0, 0)
12139 ? XEXP (x0, 1) : XEXP (x0, 0));
12142 fmt = GET_RTX_FORMAT (code);
12143 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
12145 ret += count_rtxs (XEXP (x, i));
12146 else if (fmt[i] == 'E')
12147 for (j = 0; j < XVECLEN (x, i); j++)
12148 ret += count_rtxs (XVECEXP (x, i, j));
12153 /* Utility function for following routine. Called when X is part of a value
12154 being stored into last_set_value. Sets last_set_table_tick
12155 for each register mentioned. Similar to mention_regs in cse.c */
12158 update_table_tick (rtx x)
12160 enum rtx_code code = GET_CODE (x);
12161 const char *fmt = GET_RTX_FORMAT (code);
12166 unsigned int regno = REGNO (x);
12167 unsigned int endregno = END_REGNO (x);
12170 for (r = regno; r < endregno; r++)
12172 reg_stat_type *rsp = VEC_index (reg_stat_type, reg_stat, r);
12173 rsp->last_set_table_tick = label_tick;
12179 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
12182 /* Check for identical subexpressions. If x contains
12183 identical subexpression we only have to traverse one of
12185 if (i == 0 && ARITHMETIC_P (x))
12187 /* Note that at this point x1 has already been
12189 rtx x0 = XEXP (x, 0);
12190 rtx x1 = XEXP (x, 1);
12192 /* If x0 and x1 are identical then there is no need to
12197 /* If x0 is identical to a subexpression of x1 then while
12198 processing x1, x0 has already been processed. Thus we
12199 are done with x. */
12200 if (ARITHMETIC_P (x1)
12201 && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1)))
12204 /* If x1 is identical to a subexpression of x0 then we
12205 still have to process the rest of x0. */
12206 if (ARITHMETIC_P (x0)
12207 && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1)))
12209 update_table_tick (XEXP (x0, x1 == XEXP (x0, 0) ? 1 : 0));
12214 update_table_tick (XEXP (x, i));
12216 else if (fmt[i] == 'E')
12217 for (j = 0; j < XVECLEN (x, i); j++)
12218 update_table_tick (XVECEXP (x, i, j));
12221 /* Record that REG is set to VALUE in insn INSN. If VALUE is zero, we
12222 are saying that the register is clobbered and we no longer know its
12223 value. If INSN is zero, don't update reg_stat[].last_set; this is
12224 only permitted with VALUE also zero and is used to invalidate the
12228 record_value_for_reg (rtx reg, rtx insn, rtx value)
12230 unsigned int regno = REGNO (reg);
12231 unsigned int endregno = END_REGNO (reg);
12233 reg_stat_type *rsp;
12235 /* If VALUE contains REG and we have a previous value for REG, substitute
12236 the previous value. */
12237 if (value && insn && reg_overlap_mentioned_p (reg, value))
12241 /* Set things up so get_last_value is allowed to see anything set up to
12243 subst_low_luid = DF_INSN_LUID (insn);
12244 tem = get_last_value (reg);
12246 /* If TEM is simply a binary operation with two CLOBBERs as operands,
12247 it isn't going to be useful and will take a lot of time to process,
12248 so just use the CLOBBER. */
12252 if (ARITHMETIC_P (tem)
12253 && GET_CODE (XEXP (tem, 0)) == CLOBBER
12254 && GET_CODE (XEXP (tem, 1)) == CLOBBER)
12255 tem = XEXP (tem, 0);
12256 else if (count_occurrences (value, reg, 1) >= 2)
12258 /* If there are two or more occurrences of REG in VALUE,
12259 prevent the value from growing too much. */
12260 if (count_rtxs (tem) > MAX_LAST_VALUE_RTL)
12261 tem = gen_rtx_CLOBBER (GET_MODE (tem), const0_rtx);
12264 value = replace_rtx (copy_rtx (value), reg, tem);
12268 /* For each register modified, show we don't know its value, that
12269 we don't know about its bitwise content, that its value has been
12270 updated, and that we don't know the location of the death of the
12272 for (i = regno; i < endregno; i++)
12274 rsp = VEC_index (reg_stat_type, reg_stat, i);
12277 rsp->last_set = insn;
12279 rsp->last_set_value = 0;
12280 rsp->last_set_mode = VOIDmode;
12281 rsp->last_set_nonzero_bits = 0;
12282 rsp->last_set_sign_bit_copies = 0;
12283 rsp->last_death = 0;
12284 rsp->truncated_to_mode = VOIDmode;
12287 /* Mark registers that are being referenced in this value. */
12289 update_table_tick (value);
12291 /* Now update the status of each register being set.
12292 If someone is using this register in this block, set this register
12293 to invalid since we will get confused between the two lives in this
12294 basic block. This makes using this register always invalid. In cse, we
12295 scan the table to invalidate all entries using this register, but this
12296 is too much work for us. */
12298 for (i = regno; i < endregno; i++)
12300 rsp = VEC_index (reg_stat_type, reg_stat, i);
12301 rsp->last_set_label = label_tick;
12303 || (value && rsp->last_set_table_tick >= label_tick_ebb_start))
12304 rsp->last_set_invalid = 1;
12306 rsp->last_set_invalid = 0;
12309 /* The value being assigned might refer to X (like in "x++;"). In that
12310 case, we must replace it with (clobber (const_int 0)) to prevent
12312 rsp = VEC_index (reg_stat_type, reg_stat, regno);
12313 if (value && !get_last_value_validate (&value, insn, label_tick, 0))
12315 value = copy_rtx (value);
12316 if (!get_last_value_validate (&value, insn, label_tick, 1))
12320 /* For the main register being modified, update the value, the mode, the
12321 nonzero bits, and the number of sign bit copies. */
12323 rsp->last_set_value = value;
12327 enum machine_mode mode = GET_MODE (reg);
12328 subst_low_luid = DF_INSN_LUID (insn);
12329 rsp->last_set_mode = mode;
12330 if (GET_MODE_CLASS (mode) == MODE_INT
12331 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
12332 mode = nonzero_bits_mode;
12333 rsp->last_set_nonzero_bits = nonzero_bits (value, mode);
12334 rsp->last_set_sign_bit_copies
12335 = num_sign_bit_copies (value, GET_MODE (reg));
12339 /* Called via note_stores from record_dead_and_set_regs to handle one
12340 SET or CLOBBER in an insn. DATA is the instruction in which the
12341 set is occurring. */
12344 record_dead_and_set_regs_1 (rtx dest, const_rtx setter, void *data)
12346 rtx record_dead_insn = (rtx) data;
12348 if (GET_CODE (dest) == SUBREG)
12349 dest = SUBREG_REG (dest);
12351 if (!record_dead_insn)
12354 record_value_for_reg (dest, NULL_RTX, NULL_RTX);
12360 /* If we are setting the whole register, we know its value. Otherwise
12361 show that we don't know the value. We can handle SUBREG in
12363 if (GET_CODE (setter) == SET && dest == SET_DEST (setter))
12364 record_value_for_reg (dest, record_dead_insn, SET_SRC (setter));
12365 else if (GET_CODE (setter) == SET
12366 && GET_CODE (SET_DEST (setter)) == SUBREG
12367 && SUBREG_REG (SET_DEST (setter)) == dest
12368 && GET_MODE_BITSIZE (GET_MODE (dest)) <= BITS_PER_WORD
12369 && subreg_lowpart_p (SET_DEST (setter)))
12370 record_value_for_reg (dest, record_dead_insn,
12371 gen_lowpart (GET_MODE (dest),
12372 SET_SRC (setter)));
12374 record_value_for_reg (dest, record_dead_insn, NULL_RTX);
12376 else if (MEM_P (dest)
12377 /* Ignore pushes, they clobber nothing. */
12378 && ! push_operand (dest, GET_MODE (dest)))
12379 mem_last_set = DF_INSN_LUID (record_dead_insn);
12382 /* Update the records of when each REG was most recently set or killed
12383 for the things done by INSN. This is the last thing done in processing
12384 INSN in the combiner loop.
12386 We update reg_stat[], in particular fields last_set, last_set_value,
12387 last_set_mode, last_set_nonzero_bits, last_set_sign_bit_copies,
12388 last_death, and also the similar information mem_last_set (which insn
12389 most recently modified memory) and last_call_luid (which insn was the
12390 most recent subroutine call). */
12393 record_dead_and_set_regs (rtx insn)
12398 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
12400 if (REG_NOTE_KIND (link) == REG_DEAD
12401 && REG_P (XEXP (link, 0)))
12403 unsigned int regno = REGNO (XEXP (link, 0));
12404 unsigned int endregno = END_REGNO (XEXP (link, 0));
12406 for (i = regno; i < endregno; i++)
12408 reg_stat_type *rsp;
12410 rsp = VEC_index (reg_stat_type, reg_stat, i);
12411 rsp->last_death = insn;
12414 else if (REG_NOTE_KIND (link) == REG_INC)
12415 record_value_for_reg (XEXP (link, 0), insn, NULL_RTX);
12420 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
12421 if (TEST_HARD_REG_BIT (regs_invalidated_by_call, i))
12423 reg_stat_type *rsp;
12425 rsp = VEC_index (reg_stat_type, reg_stat, i);
12426 rsp->last_set_invalid = 1;
12427 rsp->last_set = insn;
12428 rsp->last_set_value = 0;
12429 rsp->last_set_mode = VOIDmode;
12430 rsp->last_set_nonzero_bits = 0;
12431 rsp->last_set_sign_bit_copies = 0;
12432 rsp->last_death = 0;
12433 rsp->truncated_to_mode = VOIDmode;
12436 last_call_luid = mem_last_set = DF_INSN_LUID (insn);
12438 /* We can't combine into a call pattern. Remember, though, that
12439 the return value register is set at this LUID. We could
12440 still replace a register with the return value from the
12441 wrong subroutine call! */
12442 note_stores (PATTERN (insn), record_dead_and_set_regs_1, NULL_RTX);
12445 note_stores (PATTERN (insn), record_dead_and_set_regs_1, insn);
12448 /* If a SUBREG has the promoted bit set, it is in fact a property of the
12449 register present in the SUBREG, so for each such SUBREG go back and
12450 adjust nonzero and sign bit information of the registers that are
12451 known to have some zero/sign bits set.
12453 This is needed because when combine blows the SUBREGs away, the
12454 information on zero/sign bits is lost and further combines can be
12455 missed because of that. */
12458 record_promoted_value (rtx insn, rtx subreg)
12460 struct insn_link *links;
12462 unsigned int regno = REGNO (SUBREG_REG (subreg));
12463 enum machine_mode mode = GET_MODE (subreg);
12465 if (GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT)
12468 for (links = LOG_LINKS (insn); links;)
12470 reg_stat_type *rsp;
12472 insn = links->insn;
12473 set = single_set (insn);
12475 if (! set || !REG_P (SET_DEST (set))
12476 || REGNO (SET_DEST (set)) != regno
12477 || GET_MODE (SET_DEST (set)) != GET_MODE (SUBREG_REG (subreg)))
12479 links = links->next;
12483 rsp = VEC_index (reg_stat_type, reg_stat, regno);
12484 if (rsp->last_set == insn)
12486 if (SUBREG_PROMOTED_UNSIGNED_P (subreg) > 0)
12487 rsp->last_set_nonzero_bits &= GET_MODE_MASK (mode);
12490 if (REG_P (SET_SRC (set)))
12492 regno = REGNO (SET_SRC (set));
12493 links = LOG_LINKS (insn);
12500 /* Check if X, a register, is known to contain a value already
12501 truncated to MODE. In this case we can use a subreg to refer to
12502 the truncated value even though in the generic case we would need
12503 an explicit truncation. */
12506 reg_truncated_to_mode (enum machine_mode mode, const_rtx x)
12508 reg_stat_type *rsp = VEC_index (reg_stat_type, reg_stat, REGNO (x));
12509 enum machine_mode truncated = rsp->truncated_to_mode;
12512 || rsp->truncation_label < label_tick_ebb_start)
12514 if (GET_MODE_SIZE (truncated) <= GET_MODE_SIZE (mode))
12516 if (TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode),
12517 GET_MODE_BITSIZE (truncated)))
12522 /* Callback for for_each_rtx. If *P is a hard reg or a subreg record the mode
12523 that the register is accessed in. For non-TRULY_NOOP_TRUNCATION targets we
12524 might be able to turn a truncate into a subreg using this information.
12525 Return -1 if traversing *P is complete or 0 otherwise. */
12528 record_truncated_value (rtx *p, void *data ATTRIBUTE_UNUSED)
12531 enum machine_mode truncated_mode;
12532 reg_stat_type *rsp;
12534 if (GET_CODE (x) == SUBREG && REG_P (SUBREG_REG (x)))
12536 enum machine_mode original_mode = GET_MODE (SUBREG_REG (x));
12537 truncated_mode = GET_MODE (x);
12539 if (GET_MODE_SIZE (original_mode) <= GET_MODE_SIZE (truncated_mode))
12542 if (TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (truncated_mode),
12543 GET_MODE_BITSIZE (original_mode)))
12546 x = SUBREG_REG (x);
12548 /* ??? For hard-regs we now record everything. We might be able to
12549 optimize this using last_set_mode. */
12550 else if (REG_P (x) && REGNO (x) < FIRST_PSEUDO_REGISTER)
12551 truncated_mode = GET_MODE (x);
12555 rsp = VEC_index (reg_stat_type, reg_stat, REGNO (x));
12556 if (rsp->truncated_to_mode == 0
12557 || rsp->truncation_label < label_tick_ebb_start
12558 || (GET_MODE_SIZE (truncated_mode)
12559 < GET_MODE_SIZE (rsp->truncated_to_mode)))
12561 rsp->truncated_to_mode = truncated_mode;
12562 rsp->truncation_label = label_tick;
12568 /* Callback for note_uses. Find hardregs and subregs of pseudos and
12569 the modes they are used in. This can help truning TRUNCATEs into
12573 record_truncated_values (rtx *x, void *data ATTRIBUTE_UNUSED)
12575 for_each_rtx (x, record_truncated_value, NULL);
12578 /* Scan X for promoted SUBREGs. For each one found,
12579 note what it implies to the registers used in it. */
12582 check_promoted_subreg (rtx insn, rtx x)
12584 if (GET_CODE (x) == SUBREG
12585 && SUBREG_PROMOTED_VAR_P (x)
12586 && REG_P (SUBREG_REG (x)))
12587 record_promoted_value (insn, x);
12590 const char *format = GET_RTX_FORMAT (GET_CODE (x));
12593 for (i = 0; i < GET_RTX_LENGTH (GET_CODE (x)); i++)
12597 check_promoted_subreg (insn, XEXP (x, i));
12601 if (XVEC (x, i) != 0)
12602 for (j = 0; j < XVECLEN (x, i); j++)
12603 check_promoted_subreg (insn, XVECEXP (x, i, j));
12609 /* Verify that all the registers and memory references mentioned in *LOC are
12610 still valid. *LOC was part of a value set in INSN when label_tick was
12611 equal to TICK. Return 0 if some are not. If REPLACE is nonzero, replace
12612 the invalid references with (clobber (const_int 0)) and return 1. This
12613 replacement is useful because we often can get useful information about
12614 the form of a value (e.g., if it was produced by a shift that always
12615 produces -1 or 0) even though we don't know exactly what registers it
12616 was produced from. */
12619 get_last_value_validate (rtx *loc, rtx insn, int tick, int replace)
12622 const char *fmt = GET_RTX_FORMAT (GET_CODE (x));
12623 int len = GET_RTX_LENGTH (GET_CODE (x));
12628 unsigned int regno = REGNO (x);
12629 unsigned int endregno = END_REGNO (x);
12632 for (j = regno; j < endregno; j++)
12634 reg_stat_type *rsp = VEC_index (reg_stat_type, reg_stat, j);
12635 if (rsp->last_set_invalid
12636 /* If this is a pseudo-register that was only set once and not
12637 live at the beginning of the function, it is always valid. */
12638 || (! (regno >= FIRST_PSEUDO_REGISTER
12639 && REG_N_SETS (regno) == 1
12640 && (!REGNO_REG_SET_P
12641 (DF_LR_IN (ENTRY_BLOCK_PTR->next_bb), regno)))
12642 && rsp->last_set_label > tick))
12645 *loc = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
12652 /* If this is a memory reference, make sure that there were no stores after
12653 it that might have clobbered the value. We don't have alias info, so we
12654 assume any store invalidates it. Moreover, we only have local UIDs, so
12655 we also assume that there were stores in the intervening basic blocks. */
12656 else if (MEM_P (x) && !MEM_READONLY_P (x)
12657 && (tick != label_tick || DF_INSN_LUID (insn) <= mem_last_set))
12660 *loc = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
12664 for (i = 0; i < len; i++)
12668 /* Check for identical subexpressions. If x contains
12669 identical subexpression we only have to traverse one of
12671 if (i == 1 && ARITHMETIC_P (x))
12673 /* Note that at this point x0 has already been checked
12674 and found valid. */
12675 rtx x0 = XEXP (x, 0);
12676 rtx x1 = XEXP (x, 1);
12678 /* If x0 and x1 are identical then x is also valid. */
12682 /* If x1 is identical to a subexpression of x0 then
12683 while checking x0, x1 has already been checked. Thus
12684 it is valid and so as x. */
12685 if (ARITHMETIC_P (x0)
12686 && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1)))
12689 /* If x0 is identical to a subexpression of x1 then x is
12690 valid iff the rest of x1 is valid. */
12691 if (ARITHMETIC_P (x1)
12692 && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1)))
12694 get_last_value_validate (&XEXP (x1,
12695 x0 == XEXP (x1, 0) ? 1 : 0),
12696 insn, tick, replace);
12699 if (get_last_value_validate (&XEXP (x, i), insn, tick,
12703 else if (fmt[i] == 'E')
12704 for (j = 0; j < XVECLEN (x, i); j++)
12705 if (get_last_value_validate (&XVECEXP (x, i, j),
12706 insn, tick, replace) == 0)
12710 /* If we haven't found a reason for it to be invalid, it is valid. */
12714 /* Get the last value assigned to X, if known. Some registers
12715 in the value may be replaced with (clobber (const_int 0)) if their value
12716 is known longer known reliably. */
12719 get_last_value (const_rtx x)
12721 unsigned int regno;
12723 reg_stat_type *rsp;
12725 /* If this is a non-paradoxical SUBREG, get the value of its operand and
12726 then convert it to the desired mode. If this is a paradoxical SUBREG,
12727 we cannot predict what values the "extra" bits might have. */
12728 if (GET_CODE (x) == SUBREG
12729 && subreg_lowpart_p (x)
12730 && (GET_MODE_SIZE (GET_MODE (x))
12731 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
12732 && (value = get_last_value (SUBREG_REG (x))) != 0)
12733 return gen_lowpart (GET_MODE (x), value);
12739 rsp = VEC_index (reg_stat_type, reg_stat, regno);
12740 value = rsp->last_set_value;
12742 /* If we don't have a value, or if it isn't for this basic block and
12743 it's either a hard register, set more than once, or it's a live
12744 at the beginning of the function, return 0.
12746 Because if it's not live at the beginning of the function then the reg
12747 is always set before being used (is never used without being set).
12748 And, if it's set only once, and it's always set before use, then all
12749 uses must have the same last value, even if it's not from this basic
12753 || (rsp->last_set_label < label_tick_ebb_start
12754 && (regno < FIRST_PSEUDO_REGISTER
12755 || REG_N_SETS (regno) != 1
12757 (DF_LR_IN (ENTRY_BLOCK_PTR->next_bb), regno))))
12760 /* If the value was set in a later insn than the ones we are processing,
12761 we can't use it even if the register was only set once. */
12762 if (rsp->last_set_label == label_tick
12763 && DF_INSN_LUID (rsp->last_set) >= subst_low_luid)
12766 /* If the value has all its registers valid, return it. */
12767 if (get_last_value_validate (&value, rsp->last_set, rsp->last_set_label, 0))
12770 /* Otherwise, make a copy and replace any invalid register with
12771 (clobber (const_int 0)). If that fails for some reason, return 0. */
12773 value = copy_rtx (value);
12774 if (get_last_value_validate (&value, rsp->last_set, rsp->last_set_label, 1))
12780 /* Return nonzero if expression X refers to a REG or to memory
12781 that is set in an instruction more recent than FROM_LUID. */
12784 use_crosses_set_p (const_rtx x, int from_luid)
12788 enum rtx_code code = GET_CODE (x);
12792 unsigned int regno = REGNO (x);
12793 unsigned endreg = END_REGNO (x);
12795 #ifdef PUSH_ROUNDING
12796 /* Don't allow uses of the stack pointer to be moved,
12797 because we don't know whether the move crosses a push insn. */
12798 if (regno == STACK_POINTER_REGNUM && PUSH_ARGS)
12801 for (; regno < endreg; regno++)
12803 reg_stat_type *rsp = VEC_index (reg_stat_type, reg_stat, regno);
12805 && rsp->last_set_label == label_tick
12806 && DF_INSN_LUID (rsp->last_set) > from_luid)
12812 if (code == MEM && mem_last_set > from_luid)
12815 fmt = GET_RTX_FORMAT (code);
12817 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
12822 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
12823 if (use_crosses_set_p (XVECEXP (x, i, j), from_luid))
12826 else if (fmt[i] == 'e'
12827 && use_crosses_set_p (XEXP (x, i), from_luid))
12833 /* Define three variables used for communication between the following
12836 static unsigned int reg_dead_regno, reg_dead_endregno;
12837 static int reg_dead_flag;
12839 /* Function called via note_stores from reg_dead_at_p.
12841 If DEST is within [reg_dead_regno, reg_dead_endregno), set
12842 reg_dead_flag to 1 if X is a CLOBBER and to -1 it is a SET. */
12845 reg_dead_at_p_1 (rtx dest, const_rtx x, void *data ATTRIBUTE_UNUSED)
12847 unsigned int regno, endregno;
12852 regno = REGNO (dest);
12853 endregno = END_REGNO (dest);
12854 if (reg_dead_endregno > regno && reg_dead_regno < endregno)
12855 reg_dead_flag = (GET_CODE (x) == CLOBBER) ? 1 : -1;
12858 /* Return nonzero if REG is known to be dead at INSN.
12860 We scan backwards from INSN. If we hit a REG_DEAD note or a CLOBBER
12861 referencing REG, it is dead. If we hit a SET referencing REG, it is
12862 live. Otherwise, see if it is live or dead at the start of the basic
12863 block we are in. Hard regs marked as being live in NEWPAT_USED_REGS
12864 must be assumed to be always live. */
12867 reg_dead_at_p (rtx reg, rtx insn)
12872 /* Set variables for reg_dead_at_p_1. */
12873 reg_dead_regno = REGNO (reg);
12874 reg_dead_endregno = END_REGNO (reg);
12878 /* Check that reg isn't mentioned in NEWPAT_USED_REGS. For fixed registers
12879 we allow the machine description to decide whether use-and-clobber
12880 patterns are OK. */
12881 if (reg_dead_regno < FIRST_PSEUDO_REGISTER)
12883 for (i = reg_dead_regno; i < reg_dead_endregno; i++)
12884 if (!fixed_regs[i] && TEST_HARD_REG_BIT (newpat_used_regs, i))
12888 /* Scan backwards until we find a REG_DEAD note, SET, CLOBBER, or
12889 beginning of basic block. */
12890 block = BLOCK_FOR_INSN (insn);
12895 note_stores (PATTERN (insn), reg_dead_at_p_1, NULL);
12897 return reg_dead_flag == 1 ? 1 : 0;
12899 if (find_regno_note (insn, REG_DEAD, reg_dead_regno))
12903 if (insn == BB_HEAD (block))
12906 insn = PREV_INSN (insn);
12909 /* Look at live-in sets for the basic block that we were in. */
12910 for (i = reg_dead_regno; i < reg_dead_endregno; i++)
12911 if (REGNO_REG_SET_P (df_get_live_in (block), i))
12917 /* Note hard registers in X that are used. */
12920 mark_used_regs_combine (rtx x)
12922 RTX_CODE code = GET_CODE (x);
12923 unsigned int regno;
12936 case ADDR_DIFF_VEC:
12939 /* CC0 must die in the insn after it is set, so we don't need to take
12940 special note of it here. */
12946 /* If we are clobbering a MEM, mark any hard registers inside the
12947 address as used. */
12948 if (MEM_P (XEXP (x, 0)))
12949 mark_used_regs_combine (XEXP (XEXP (x, 0), 0));
12954 /* A hard reg in a wide mode may really be multiple registers.
12955 If so, mark all of them just like the first. */
12956 if (regno < FIRST_PSEUDO_REGISTER)
12958 /* None of this applies to the stack, frame or arg pointers. */
12959 if (regno == STACK_POINTER_REGNUM
12960 #if !HARD_FRAME_POINTER_IS_FRAME_POINTER
12961 || regno == HARD_FRAME_POINTER_REGNUM
12963 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
12964 || (regno == ARG_POINTER_REGNUM && fixed_regs[regno])
12966 || regno == FRAME_POINTER_REGNUM)
12969 add_to_hard_reg_set (&newpat_used_regs, GET_MODE (x), regno);
12975 /* If setting a MEM, or a SUBREG of a MEM, then note any hard regs in
12977 rtx testreg = SET_DEST (x);
12979 while (GET_CODE (testreg) == SUBREG
12980 || GET_CODE (testreg) == ZERO_EXTRACT
12981 || GET_CODE (testreg) == STRICT_LOW_PART)
12982 testreg = XEXP (testreg, 0);
12984 if (MEM_P (testreg))
12985 mark_used_regs_combine (XEXP (testreg, 0));
12987 mark_used_regs_combine (SET_SRC (x));
12995 /* Recursively scan the operands of this expression. */
12998 const char *fmt = GET_RTX_FORMAT (code);
13000 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
13003 mark_used_regs_combine (XEXP (x, i));
13004 else if (fmt[i] == 'E')
13008 for (j = 0; j < XVECLEN (x, i); j++)
13009 mark_used_regs_combine (XVECEXP (x, i, j));
13015 /* Remove register number REGNO from the dead registers list of INSN.
13017 Return the note used to record the death, if there was one. */
13020 remove_death (unsigned int regno, rtx insn)
13022 rtx note = find_regno_note (insn, REG_DEAD, regno);
13025 remove_note (insn, note);
13030 /* For each register (hardware or pseudo) used within expression X, if its
13031 death is in an instruction with luid between FROM_LUID (inclusive) and
13032 TO_INSN (exclusive), put a REG_DEAD note for that register in the
13033 list headed by PNOTES.
13035 That said, don't move registers killed by maybe_kill_insn.
13037 This is done when X is being merged by combination into TO_INSN. These
13038 notes will then be distributed as needed. */
13041 move_deaths (rtx x, rtx maybe_kill_insn, int from_luid, rtx to_insn,
13046 enum rtx_code code = GET_CODE (x);
13050 unsigned int regno = REGNO (x);
13051 rtx where_dead = VEC_index (reg_stat_type, reg_stat, regno)->last_death;
13053 /* Don't move the register if it gets killed in between from and to. */
13054 if (maybe_kill_insn && reg_set_p (x, maybe_kill_insn)
13055 && ! reg_referenced_p (x, maybe_kill_insn))
13059 && BLOCK_FOR_INSN (where_dead) == BLOCK_FOR_INSN (to_insn)
13060 && DF_INSN_LUID (where_dead) >= from_luid
13061 && DF_INSN_LUID (where_dead) < DF_INSN_LUID (to_insn))
13063 rtx note = remove_death (regno, where_dead);
13065 /* It is possible for the call above to return 0. This can occur
13066 when last_death points to I2 or I1 that we combined with.
13067 In that case make a new note.
13069 We must also check for the case where X is a hard register
13070 and NOTE is a death note for a range of hard registers
13071 including X. In that case, we must put REG_DEAD notes for
13072 the remaining registers in place of NOTE. */
13074 if (note != 0 && regno < FIRST_PSEUDO_REGISTER
13075 && (GET_MODE_SIZE (GET_MODE (XEXP (note, 0)))
13076 > GET_MODE_SIZE (GET_MODE (x))))
13078 unsigned int deadregno = REGNO (XEXP (note, 0));
13079 unsigned int deadend = END_HARD_REGNO (XEXP (note, 0));
13080 unsigned int ourend = END_HARD_REGNO (x);
13083 for (i = deadregno; i < deadend; i++)
13084 if (i < regno || i >= ourend)
13085 add_reg_note (where_dead, REG_DEAD, regno_reg_rtx[i]);
13088 /* If we didn't find any note, or if we found a REG_DEAD note that
13089 covers only part of the given reg, and we have a multi-reg hard
13090 register, then to be safe we must check for REG_DEAD notes
13091 for each register other than the first. They could have
13092 their own REG_DEAD notes lying around. */
13093 else if ((note == 0
13095 && (GET_MODE_SIZE (GET_MODE (XEXP (note, 0)))
13096 < GET_MODE_SIZE (GET_MODE (x)))))
13097 && regno < FIRST_PSEUDO_REGISTER
13098 && hard_regno_nregs[regno][GET_MODE (x)] > 1)
13100 unsigned int ourend = END_HARD_REGNO (x);
13101 unsigned int i, offset;
13105 offset = hard_regno_nregs[regno][GET_MODE (XEXP (note, 0))];
13109 for (i = regno + offset; i < ourend; i++)
13110 move_deaths (regno_reg_rtx[i],
13111 maybe_kill_insn, from_luid, to_insn, &oldnotes);
13114 if (note != 0 && GET_MODE (XEXP (note, 0)) == GET_MODE (x))
13116 XEXP (note, 1) = *pnotes;
13120 *pnotes = alloc_reg_note (REG_DEAD, x, *pnotes);
13126 else if (GET_CODE (x) == SET)
13128 rtx dest = SET_DEST (x);
13130 move_deaths (SET_SRC (x), maybe_kill_insn, from_luid, to_insn, pnotes);
13132 /* In the case of a ZERO_EXTRACT, a STRICT_LOW_PART, or a SUBREG
13133 that accesses one word of a multi-word item, some
13134 piece of everything register in the expression is used by
13135 this insn, so remove any old death. */
13136 /* ??? So why do we test for equality of the sizes? */
13138 if (GET_CODE (dest) == ZERO_EXTRACT
13139 || GET_CODE (dest) == STRICT_LOW_PART
13140 || (GET_CODE (dest) == SUBREG
13141 && (((GET_MODE_SIZE (GET_MODE (dest))
13142 + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
13143 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (dest)))
13144 + UNITS_PER_WORD - 1) / UNITS_PER_WORD))))
13146 move_deaths (dest, maybe_kill_insn, from_luid, to_insn, pnotes);
13150 /* If this is some other SUBREG, we know it replaces the entire
13151 value, so use that as the destination. */
13152 if (GET_CODE (dest) == SUBREG)
13153 dest = SUBREG_REG (dest);
13155 /* If this is a MEM, adjust deaths of anything used in the address.
13156 For a REG (the only other possibility), the entire value is
13157 being replaced so the old value is not used in this insn. */
13160 move_deaths (XEXP (dest, 0), maybe_kill_insn, from_luid,
13165 else if (GET_CODE (x) == CLOBBER)
13168 len = GET_RTX_LENGTH (code);
13169 fmt = GET_RTX_FORMAT (code);
13171 for (i = 0; i < len; i++)
13176 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
13177 move_deaths (XVECEXP (x, i, j), maybe_kill_insn, from_luid,
13180 else if (fmt[i] == 'e')
13181 move_deaths (XEXP (x, i), maybe_kill_insn, from_luid, to_insn, pnotes);
13185 /* Return 1 if X is the target of a bit-field assignment in BODY, the
13186 pattern of an insn. X must be a REG. */
13189 reg_bitfield_target_p (rtx x, rtx body)
13193 if (GET_CODE (body) == SET)
13195 rtx dest = SET_DEST (body);
13197 unsigned int regno, tregno, endregno, endtregno;
13199 if (GET_CODE (dest) == ZERO_EXTRACT)
13200 target = XEXP (dest, 0);
13201 else if (GET_CODE (dest) == STRICT_LOW_PART)
13202 target = SUBREG_REG (XEXP (dest, 0));
13206 if (GET_CODE (target) == SUBREG)
13207 target = SUBREG_REG (target);
13209 if (!REG_P (target))
13212 tregno = REGNO (target), regno = REGNO (x);
13213 if (tregno >= FIRST_PSEUDO_REGISTER || regno >= FIRST_PSEUDO_REGISTER)
13214 return target == x;
13216 endtregno = end_hard_regno (GET_MODE (target), tregno);
13217 endregno = end_hard_regno (GET_MODE (x), regno);
13219 return endregno > tregno && regno < endtregno;
13222 else if (GET_CODE (body) == PARALLEL)
13223 for (i = XVECLEN (body, 0) - 1; i >= 0; i--)
13224 if (reg_bitfield_target_p (x, XVECEXP (body, 0, i)))
13230 /* Given a chain of REG_NOTES originally from FROM_INSN, try to place them
13231 as appropriate. I3 and I2 are the insns resulting from the combination
13232 insns including FROM (I2 may be zero).
13234 ELIM_I2 and ELIM_I1 are either zero or registers that we know will
13235 not need REG_DEAD notes because they are being substituted for. This
13236 saves searching in the most common cases.
13238 Each note in the list is either ignored or placed on some insns, depending
13239 on the type of note. */
13242 distribute_notes (rtx notes, rtx from_insn, rtx i3, rtx i2, rtx elim_i2,
13243 rtx elim_i1, rtx elim_i0)
13245 rtx note, next_note;
13248 for (note = notes; note; note = next_note)
13250 rtx place = 0, place2 = 0;
13252 next_note = XEXP (note, 1);
13253 switch (REG_NOTE_KIND (note))
13257 /* Doesn't matter much where we put this, as long as it's somewhere.
13258 It is preferable to keep these notes on branches, which is most
13259 likely to be i3. */
13263 case REG_NON_LOCAL_GOTO:
13268 gcc_assert (i2 && JUMP_P (i2));
13273 case REG_EH_REGION:
13274 /* These notes must remain with the call or trapping instruction. */
13277 else if (i2 && CALL_P (i2))
13281 gcc_assert (cfun->can_throw_non_call_exceptions);
13282 if (may_trap_p (i3))
13284 else if (i2 && may_trap_p (i2))
13286 /* ??? Otherwise assume we've combined things such that we
13287 can now prove that the instructions can't trap. Drop the
13288 note in this case. */
13294 /* These notes must remain with the call. It should not be
13295 possible for both I2 and I3 to be a call. */
13300 gcc_assert (i2 && CALL_P (i2));
13306 /* Any clobbers for i3 may still exist, and so we must process
13307 REG_UNUSED notes from that insn.
13309 Any clobbers from i2 or i1 can only exist if they were added by
13310 recog_for_combine. In that case, recog_for_combine created the
13311 necessary REG_UNUSED notes. Trying to keep any original
13312 REG_UNUSED notes from these insns can cause incorrect output
13313 if it is for the same register as the original i3 dest.
13314 In that case, we will notice that the register is set in i3,
13315 and then add a REG_UNUSED note for the destination of i3, which
13316 is wrong. However, it is possible to have REG_UNUSED notes from
13317 i2 or i1 for register which were both used and clobbered, so
13318 we keep notes from i2 or i1 if they will turn into REG_DEAD
13321 /* If this register is set or clobbered in I3, put the note there
13322 unless there is one already. */
13323 if (reg_set_p (XEXP (note, 0), PATTERN (i3)))
13325 if (from_insn != i3)
13328 if (! (REG_P (XEXP (note, 0))
13329 ? find_regno_note (i3, REG_UNUSED, REGNO (XEXP (note, 0)))
13330 : find_reg_note (i3, REG_UNUSED, XEXP (note, 0))))
13333 /* Otherwise, if this register is used by I3, then this register
13334 now dies here, so we must put a REG_DEAD note here unless there
13336 else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3))
13337 && ! (REG_P (XEXP (note, 0))
13338 ? find_regno_note (i3, REG_DEAD,
13339 REGNO (XEXP (note, 0)))
13340 : find_reg_note (i3, REG_DEAD, XEXP (note, 0))))
13342 PUT_REG_NOTE_KIND (note, REG_DEAD);
13350 /* These notes say something about results of an insn. We can
13351 only support them if they used to be on I3 in which case they
13352 remain on I3. Otherwise they are ignored.
13354 If the note refers to an expression that is not a constant, we
13355 must also ignore the note since we cannot tell whether the
13356 equivalence is still true. It might be possible to do
13357 slightly better than this (we only have a problem if I2DEST
13358 or I1DEST is present in the expression), but it doesn't
13359 seem worth the trouble. */
13361 if (from_insn == i3
13362 && (XEXP (note, 0) == 0 || CONSTANT_P (XEXP (note, 0))))
13367 /* These notes say something about how a register is used. They must
13368 be present on any use of the register in I2 or I3. */
13369 if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3)))
13372 if (i2 && reg_mentioned_p (XEXP (note, 0), PATTERN (i2)))
13381 case REG_LABEL_TARGET:
13382 case REG_LABEL_OPERAND:
13383 /* This can show up in several ways -- either directly in the
13384 pattern, or hidden off in the constant pool with (or without?)
13385 a REG_EQUAL note. */
13386 /* ??? Ignore the without-reg_equal-note problem for now. */
13387 if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3))
13388 || ((tem = find_reg_note (i3, REG_EQUAL, NULL_RTX))
13389 && GET_CODE (XEXP (tem, 0)) == LABEL_REF
13390 && XEXP (XEXP (tem, 0), 0) == XEXP (note, 0)))
13394 && (reg_mentioned_p (XEXP (note, 0), PATTERN (i2))
13395 || ((tem = find_reg_note (i2, REG_EQUAL, NULL_RTX))
13396 && GET_CODE (XEXP (tem, 0)) == LABEL_REF
13397 && XEXP (XEXP (tem, 0), 0) == XEXP (note, 0))))
13405 /* For REG_LABEL_TARGET on a JUMP_P, we prefer to put the note
13406 as a JUMP_LABEL or decrement LABEL_NUSES if it's already
13408 if (place && JUMP_P (place)
13409 && REG_NOTE_KIND (note) == REG_LABEL_TARGET
13410 && (JUMP_LABEL (place) == NULL
13411 || JUMP_LABEL (place) == XEXP (note, 0)))
13413 rtx label = JUMP_LABEL (place);
13416 JUMP_LABEL (place) = XEXP (note, 0);
13417 else if (LABEL_P (label))
13418 LABEL_NUSES (label)--;
13421 if (place2 && JUMP_P (place2)
13422 && REG_NOTE_KIND (note) == REG_LABEL_TARGET
13423 && (JUMP_LABEL (place2) == NULL
13424 || JUMP_LABEL (place2) == XEXP (note, 0)))
13426 rtx label = JUMP_LABEL (place2);
13429 JUMP_LABEL (place2) = XEXP (note, 0);
13430 else if (LABEL_P (label))
13431 LABEL_NUSES (label)--;
13437 /* This note says something about the value of a register prior
13438 to the execution of an insn. It is too much trouble to see
13439 if the note is still correct in all situations. It is better
13440 to simply delete it. */
13444 /* If we replaced the right hand side of FROM_INSN with a
13445 REG_EQUAL note, the original use of the dying register
13446 will not have been combined into I3 and I2. In such cases,
13447 FROM_INSN is guaranteed to be the first of the combined
13448 instructions, so we simply need to search back before
13449 FROM_INSN for the previous use or set of this register,
13450 then alter the notes there appropriately.
13452 If the register is used as an input in I3, it dies there.
13453 Similarly for I2, if it is nonzero and adjacent to I3.
13455 If the register is not used as an input in either I3 or I2
13456 and it is not one of the registers we were supposed to eliminate,
13457 there are two possibilities. We might have a non-adjacent I2
13458 or we might have somehow eliminated an additional register
13459 from a computation. For example, we might have had A & B where
13460 we discover that B will always be zero. In this case we will
13461 eliminate the reference to A.
13463 In both cases, we must search to see if we can find a previous
13464 use of A and put the death note there. */
13467 && from_insn == i2mod
13468 && !reg_overlap_mentioned_p (XEXP (note, 0), i2mod_new_rhs))
13473 && CALL_P (from_insn)
13474 && find_reg_fusage (from_insn, USE, XEXP (note, 0)))
13476 else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3)))
13478 else if (i2 != 0 && next_nonnote_nondebug_insn (i2) == i3
13479 && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
13481 else if ((rtx_equal_p (XEXP (note, 0), elim_i2)
13483 && reg_overlap_mentioned_p (XEXP (note, 0),
13485 || rtx_equal_p (XEXP (note, 0), elim_i1)
13486 || rtx_equal_p (XEXP (note, 0), elim_i0))
13493 basic_block bb = this_basic_block;
13495 for (tem = PREV_INSN (tem); place == 0; tem = PREV_INSN (tem))
13497 if (!NONDEBUG_INSN_P (tem))
13499 if (tem == BB_HEAD (bb))
13504 /* If the register is being set at TEM, see if that is all
13505 TEM is doing. If so, delete TEM. Otherwise, make this
13506 into a REG_UNUSED note instead. Don't delete sets to
13507 global register vars. */
13508 if ((REGNO (XEXP (note, 0)) >= FIRST_PSEUDO_REGISTER
13509 || !global_regs[REGNO (XEXP (note, 0))])
13510 && reg_set_p (XEXP (note, 0), PATTERN (tem)))
13512 rtx set = single_set (tem);
13513 rtx inner_dest = 0;
13515 rtx cc0_setter = NULL_RTX;
13519 for (inner_dest = SET_DEST (set);
13520 (GET_CODE (inner_dest) == STRICT_LOW_PART
13521 || GET_CODE (inner_dest) == SUBREG
13522 || GET_CODE (inner_dest) == ZERO_EXTRACT);
13523 inner_dest = XEXP (inner_dest, 0))
13526 /* Verify that it was the set, and not a clobber that
13527 modified the register.
13529 CC0 targets must be careful to maintain setter/user
13530 pairs. If we cannot delete the setter due to side
13531 effects, mark the user with an UNUSED note instead
13534 if (set != 0 && ! side_effects_p (SET_SRC (set))
13535 && rtx_equal_p (XEXP (note, 0), inner_dest)
13537 && (! reg_mentioned_p (cc0_rtx, SET_SRC (set))
13538 || ((cc0_setter = prev_cc0_setter (tem)) != NULL
13539 && sets_cc0_p (PATTERN (cc0_setter)) > 0))
13543 /* Move the notes and links of TEM elsewhere.
13544 This might delete other dead insns recursively.
13545 First set the pattern to something that won't use
13547 rtx old_notes = REG_NOTES (tem);
13549 PATTERN (tem) = pc_rtx;
13550 REG_NOTES (tem) = NULL;
13552 distribute_notes (old_notes, tem, tem, NULL_RTX,
13553 NULL_RTX, NULL_RTX, NULL_RTX);
13554 distribute_links (LOG_LINKS (tem));
13556 SET_INSN_DELETED (tem);
13561 /* Delete the setter too. */
13564 PATTERN (cc0_setter) = pc_rtx;
13565 old_notes = REG_NOTES (cc0_setter);
13566 REG_NOTES (cc0_setter) = NULL;
13568 distribute_notes (old_notes, cc0_setter,
13569 cc0_setter, NULL_RTX,
13570 NULL_RTX, NULL_RTX, NULL_RTX);
13571 distribute_links (LOG_LINKS (cc0_setter));
13573 SET_INSN_DELETED (cc0_setter);
13574 if (cc0_setter == i2)
13581 PUT_REG_NOTE_KIND (note, REG_UNUSED);
13583 /* If there isn't already a REG_UNUSED note, put one
13584 here. Do not place a REG_DEAD note, even if
13585 the register is also used here; that would not
13586 match the algorithm used in lifetime analysis
13587 and can cause the consistency check in the
13588 scheduler to fail. */
13589 if (! find_regno_note (tem, REG_UNUSED,
13590 REGNO (XEXP (note, 0))))
13595 else if (reg_referenced_p (XEXP (note, 0), PATTERN (tem))
13597 && find_reg_fusage (tem, USE, XEXP (note, 0))))
13601 /* If we are doing a 3->2 combination, and we have a
13602 register which formerly died in i3 and was not used
13603 by i2, which now no longer dies in i3 and is used in
13604 i2 but does not die in i2, and place is between i2
13605 and i3, then we may need to move a link from place to
13607 if (i2 && DF_INSN_LUID (place) > DF_INSN_LUID (i2)
13609 && DF_INSN_LUID (from_insn) > DF_INSN_LUID (i2)
13610 && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
13612 struct insn_link *links = LOG_LINKS (place);
13613 LOG_LINKS (place) = NULL;
13614 distribute_links (links);
13619 if (tem == BB_HEAD (bb))
13625 /* If the register is set or already dead at PLACE, we needn't do
13626 anything with this note if it is still a REG_DEAD note.
13627 We check here if it is set at all, not if is it totally replaced,
13628 which is what `dead_or_set_p' checks, so also check for it being
13631 if (place && REG_NOTE_KIND (note) == REG_DEAD)
13633 unsigned int regno = REGNO (XEXP (note, 0));
13634 reg_stat_type *rsp = VEC_index (reg_stat_type, reg_stat, regno);
13636 if (dead_or_set_p (place, XEXP (note, 0))
13637 || reg_bitfield_target_p (XEXP (note, 0), PATTERN (place)))
13639 /* Unless the register previously died in PLACE, clear
13640 last_death. [I no longer understand why this is
13642 if (rsp->last_death != place)
13643 rsp->last_death = 0;
13647 rsp->last_death = place;
13649 /* If this is a death note for a hard reg that is occupying
13650 multiple registers, ensure that we are still using all
13651 parts of the object. If we find a piece of the object
13652 that is unused, we must arrange for an appropriate REG_DEAD
13653 note to be added for it. However, we can't just emit a USE
13654 and tag the note to it, since the register might actually
13655 be dead; so we recourse, and the recursive call then finds
13656 the previous insn that used this register. */
13658 if (place && regno < FIRST_PSEUDO_REGISTER
13659 && hard_regno_nregs[regno][GET_MODE (XEXP (note, 0))] > 1)
13661 unsigned int endregno = END_HARD_REGNO (XEXP (note, 0));
13665 for (i = regno; i < endregno; i++)
13666 if ((! refers_to_regno_p (i, i + 1, PATTERN (place), 0)
13667 && ! find_regno_fusage (place, USE, i))
13668 || dead_or_set_regno_p (place, i))
13673 /* Put only REG_DEAD notes for pieces that are
13674 not already dead or set. */
13676 for (i = regno; i < endregno;
13677 i += hard_regno_nregs[i][reg_raw_mode[i]])
13679 rtx piece = regno_reg_rtx[i];
13680 basic_block bb = this_basic_block;
13682 if (! dead_or_set_p (place, piece)
13683 && ! reg_bitfield_target_p (piece,
13686 rtx new_note = alloc_reg_note (REG_DEAD, piece,
13689 distribute_notes (new_note, place, place,
13690 NULL_RTX, NULL_RTX, NULL_RTX,
13693 else if (! refers_to_regno_p (i, i + 1,
13694 PATTERN (place), 0)
13695 && ! find_regno_fusage (place, USE, i))
13696 for (tem = PREV_INSN (place); ;
13697 tem = PREV_INSN (tem))
13699 if (!NONDEBUG_INSN_P (tem))
13701 if (tem == BB_HEAD (bb))
13705 if (dead_or_set_p (tem, piece)
13706 || reg_bitfield_target_p (piece,
13709 add_reg_note (tem, REG_UNUSED, piece);
13723 /* Any other notes should not be present at this point in the
13725 gcc_unreachable ();
13730 XEXP (note, 1) = REG_NOTES (place);
13731 REG_NOTES (place) = note;
13735 add_reg_note (place2, REG_NOTE_KIND (note), XEXP (note, 0));
13739 /* Similarly to above, distribute the LOG_LINKS that used to be present on
13740 I3, I2, and I1 to new locations. This is also called to add a link
13741 pointing at I3 when I3's destination is changed. */
13744 distribute_links (struct insn_link *links)
13746 struct insn_link *link, *next_link;
13748 for (link = links; link; link = next_link)
13754 next_link = link->next;
13756 /* If the insn that this link points to is a NOTE or isn't a single
13757 set, ignore it. In the latter case, it isn't clear what we
13758 can do other than ignore the link, since we can't tell which
13759 register it was for. Such links wouldn't be used by combine
13762 It is not possible for the destination of the target of the link to
13763 have been changed by combine. The only potential of this is if we
13764 replace I3, I2, and I1 by I3 and I2. But in that case the
13765 destination of I2 also remains unchanged. */
13767 if (NOTE_P (link->insn)
13768 || (set = single_set (link->insn)) == 0)
13771 reg = SET_DEST (set);
13772 while (GET_CODE (reg) == SUBREG || GET_CODE (reg) == ZERO_EXTRACT
13773 || GET_CODE (reg) == STRICT_LOW_PART)
13774 reg = XEXP (reg, 0);
13776 /* A LOG_LINK is defined as being placed on the first insn that uses
13777 a register and points to the insn that sets the register. Start
13778 searching at the next insn after the target of the link and stop
13779 when we reach a set of the register or the end of the basic block.
13781 Note that this correctly handles the link that used to point from
13782 I3 to I2. Also note that not much searching is typically done here
13783 since most links don't point very far away. */
13785 for (insn = NEXT_INSN (link->insn);
13786 (insn && (this_basic_block->next_bb == EXIT_BLOCK_PTR
13787 || BB_HEAD (this_basic_block->next_bb) != insn));
13788 insn = NEXT_INSN (insn))
13789 if (DEBUG_INSN_P (insn))
13791 else if (INSN_P (insn) && reg_overlap_mentioned_p (reg, PATTERN (insn)))
13793 if (reg_referenced_p (reg, PATTERN (insn)))
13797 else if (CALL_P (insn)
13798 && find_reg_fusage (insn, USE, reg))
13803 else if (INSN_P (insn) && reg_set_p (reg, insn))
13806 /* If we found a place to put the link, place it there unless there
13807 is already a link to the same insn as LINK at that point. */
13811 struct insn_link *link2;
13813 FOR_EACH_LOG_LINK (link2, place)
13814 if (link2->insn == link->insn)
13819 link->next = LOG_LINKS (place);
13820 LOG_LINKS (place) = link;
13822 /* Set added_links_insn to the earliest insn we added a
13824 if (added_links_insn == 0
13825 || DF_INSN_LUID (added_links_insn) > DF_INSN_LUID (place))
13826 added_links_insn = place;
13832 /* Subroutine of unmentioned_reg_p and callback from for_each_rtx.
13833 Check whether the expression pointer to by LOC is a register or
13834 memory, and if so return 1 if it isn't mentioned in the rtx EXPR.
13835 Otherwise return zero. */
13838 unmentioned_reg_p_1 (rtx *loc, void *expr)
13843 && (REG_P (x) || MEM_P (x))
13844 && ! reg_mentioned_p (x, (rtx) expr))
13849 /* Check for any register or memory mentioned in EQUIV that is not
13850 mentioned in EXPR. This is used to restrict EQUIV to "specializations"
13851 of EXPR where some registers may have been replaced by constants. */
13854 unmentioned_reg_p (rtx equiv, rtx expr)
13856 return for_each_rtx (&equiv, unmentioned_reg_p_1, expr);
13860 dump_combine_stats (FILE *file)
13864 ";; Combiner statistics: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n\n",
13865 combine_attempts, combine_merges, combine_extras, combine_successes);
13869 dump_combine_total_stats (FILE *file)
13873 "\n;; Combiner totals: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n",
13874 total_attempts, total_merges, total_extras, total_successes);
13878 gate_handle_combine (void)
13880 return (optimize > 0);
13883 /* Try combining insns through substitution. */
13884 static unsigned int
13885 rest_of_handle_combine (void)
13887 int rebuild_jump_labels_after_combine;
13889 df_set_flags (DF_LR_RUN_DCE + DF_DEFER_INSN_RESCAN);
13890 df_note_add_problem ();
13893 regstat_init_n_sets_and_refs ();
13895 rebuild_jump_labels_after_combine
13896 = combine_instructions (get_insns (), max_reg_num ());
13898 /* Combining insns may have turned an indirect jump into a
13899 direct jump. Rebuild the JUMP_LABEL fields of jumping
13901 if (rebuild_jump_labels_after_combine)
13903 timevar_push (TV_JUMP);
13904 rebuild_jump_labels (get_insns ());
13906 timevar_pop (TV_JUMP);
13909 regstat_free_n_sets_and_refs ();
13913 struct rtl_opt_pass pass_combine =
13917 "combine", /* name */
13918 gate_handle_combine, /* gate */
13919 rest_of_handle_combine, /* execute */
13922 0, /* static_pass_number */
13923 TV_COMBINE, /* tv_id */
13924 PROP_cfglayout, /* properties_required */
13925 0, /* properties_provided */
13926 0, /* properties_destroyed */
13927 0, /* todo_flags_start */
13928 TODO_df_finish | TODO_verify_rtl_sharing |
13929 TODO_ggc_collect, /* todo_flags_finish */