1 /* Optimize by combining instructions for GNU compiler.
2 Copyright (C) 1987, 1988, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010
4 Free Software Foundation, Inc.
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify it under
9 the terms of the GNU General Public License as published by the Free
10 Software Foundation; either version 3, or (at your option) any later
13 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
14 WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
22 /* This module is essentially the "combiner" phase of the U. of Arizona
23 Portable Optimizer, but redone to work on our list-structured
24 representation for RTL instead of their string representation.
26 The LOG_LINKS of each insn identify the most recent assignment
27 to each REG used in the insn. It is a list of previous insns,
28 each of which contains a SET for a REG that is used in this insn
29 and not used or set in between. LOG_LINKs never cross basic blocks.
30 They were set up by the preceding pass (lifetime analysis).
32 We try to combine each pair of insns joined by a logical link.
33 We also try to combine triples of insns A, B and C when
34 C has a link back to B and B has a link back to A.
36 LOG_LINKS does not have links for use of the CC0. They don't
37 need to, because the insn that sets the CC0 is always immediately
38 before the insn that tests it. So we always regard a branch
39 insn as having a logical link to the preceding insn. The same is true
40 for an insn explicitly using CC0.
42 We check (with use_crosses_set_p) to avoid combining in such a way
43 as to move a computation to a place where its value would be different.
45 Combination is done by mathematically substituting the previous
46 insn(s) values for the regs they set into the expressions in
47 the later insns that refer to these regs. If the result is a valid insn
48 for our target machine, according to the machine description,
49 we install it, delete the earlier insns, and update the data flow
50 information (LOG_LINKS and REG_NOTES) for what we did.
52 There are a few exceptions where the dataflow information isn't
53 completely updated (however this is only a local issue since it is
54 regenerated before the next pass that uses it):
56 - reg_live_length is not updated
57 - reg_n_refs is not adjusted in the rare case when a register is
58 no longer required in a computation
59 - there are extremely rare cases (see distribute_notes) when a
61 - a LOG_LINKS entry that refers to an insn with multiple SETs may be
62 removed because there is no way to know which register it was
65 To simplify substitution, we combine only when the earlier insn(s)
66 consist of only a single assignment. To simplify updating afterward,
67 we never combine when a subroutine call appears in the middle.
69 Since we do not represent assignments to CC0 explicitly except when that
70 is all an insn does, there is no LOG_LINKS entry in an insn that uses
71 the condition code for the insn that set the condition code.
72 Fortunately, these two insns must be consecutive.
73 Therefore, every JUMP_INSN is taken to have an implicit logical link
74 to the preceding insn. This is not quite right, since non-jumps can
75 also use the condition code; but in practice such insns would not
80 #include "coretypes.h"
87 #include "hard-reg-set.h"
88 #include "basic-block.h"
89 #include "insn-config.h"
91 /* Include expr.h after insn-config.h so we get HAVE_conditional_move. */
93 #include "insn-attr.h"
95 #include "diagnostic-core.h"
99 #include "insn-codes.h"
100 #include "rtlhooks-def.h"
101 /* Include output.h for dump_file. */
105 #include "tree-pass.h"
109 /* Number of attempts to combine instructions in this function. */
111 static int combine_attempts;
113 /* Number of attempts that got as far as substitution in this function. */
115 static int combine_merges;
117 /* Number of instructions combined with added SETs in this function. */
119 static int combine_extras;
121 /* Number of instructions combined in this function. */
123 static int combine_successes;
125 /* Totals over entire compilation. */
127 static int total_attempts, total_merges, total_extras, total_successes;
129 /* combine_instructions may try to replace the right hand side of the
130 second instruction with the value of an associated REG_EQUAL note
131 before throwing it at try_combine. That is problematic when there
132 is a REG_DEAD note for a register used in the old right hand side
133 and can cause distribute_notes to do wrong things. This is the
134 second instruction if it has been so modified, null otherwise. */
138 /* When I2MOD is nonnull, this is a copy of the old right hand side. */
140 static rtx i2mod_old_rhs;
142 /* When I2MOD is nonnull, this is a copy of the new right hand side. */
144 static rtx i2mod_new_rhs;
146 typedef struct reg_stat_struct {
147 /* Record last point of death of (hard or pseudo) register n. */
150 /* Record last point of modification of (hard or pseudo) register n. */
153 /* The next group of fields allows the recording of the last value assigned
154 to (hard or pseudo) register n. We use this information to see if an
155 operation being processed is redundant given a prior operation performed
156 on the register. For example, an `and' with a constant is redundant if
157 all the zero bits are already known to be turned off.
159 We use an approach similar to that used by cse, but change it in the
162 (1) We do not want to reinitialize at each label.
163 (2) It is useful, but not critical, to know the actual value assigned
164 to a register. Often just its form is helpful.
166 Therefore, we maintain the following fields:
168 last_set_value the last value assigned
169 last_set_label records the value of label_tick when the
170 register was assigned
171 last_set_table_tick records the value of label_tick when a
172 value using the register is assigned
173 last_set_invalid set to nonzero when it is not valid
174 to use the value of this register in some
177 To understand the usage of these tables, it is important to understand
178 the distinction between the value in last_set_value being valid and
179 the register being validly contained in some other expression in the
182 (The next two parameters are out of date).
184 reg_stat[i].last_set_value is valid if it is nonzero, and either
185 reg_n_sets[i] is 1 or reg_stat[i].last_set_label == label_tick.
187 Register I may validly appear in any expression returned for the value
188 of another register if reg_n_sets[i] is 1. It may also appear in the
189 value for register J if reg_stat[j].last_set_invalid is zero, or
190 reg_stat[i].last_set_label < reg_stat[j].last_set_label.
192 If an expression is found in the table containing a register which may
193 not validly appear in an expression, the register is replaced by
194 something that won't match, (clobber (const_int 0)). */
196 /* Record last value assigned to (hard or pseudo) register n. */
200 /* Record the value of label_tick when an expression involving register n
201 is placed in last_set_value. */
203 int last_set_table_tick;
205 /* Record the value of label_tick when the value for register n is placed in
210 /* These fields are maintained in parallel with last_set_value and are
211 used to store the mode in which the register was last set, the bits
212 that were known to be zero when it was last set, and the number of
213 sign bits copies it was known to have when it was last set. */
215 unsigned HOST_WIDE_INT last_set_nonzero_bits;
216 char last_set_sign_bit_copies;
217 ENUM_BITFIELD(machine_mode) last_set_mode : 8;
219 /* Set nonzero if references to register n in expressions should not be
220 used. last_set_invalid is set nonzero when this register is being
221 assigned to and last_set_table_tick == label_tick. */
223 char last_set_invalid;
225 /* Some registers that are set more than once and used in more than one
226 basic block are nevertheless always set in similar ways. For example,
227 a QImode register may be loaded from memory in two places on a machine
228 where byte loads zero extend.
230 We record in the following fields if a register has some leading bits
231 that are always equal to the sign bit, and what we know about the
232 nonzero bits of a register, specifically which bits are known to be
235 If an entry is zero, it means that we don't know anything special. */
237 unsigned char sign_bit_copies;
239 unsigned HOST_WIDE_INT nonzero_bits;
241 /* Record the value of the label_tick when the last truncation
242 happened. The field truncated_to_mode is only valid if
243 truncation_label == label_tick. */
245 int truncation_label;
247 /* Record the last truncation seen for this register. If truncation
248 is not a nop to this mode we might be able to save an explicit
249 truncation if we know that value already contains a truncated
252 ENUM_BITFIELD(machine_mode) truncated_to_mode : 8;
255 DEF_VEC_O(reg_stat_type);
256 DEF_VEC_ALLOC_O(reg_stat_type,heap);
258 static VEC(reg_stat_type,heap) *reg_stat;
260 /* Record the luid of the last insn that invalidated memory
261 (anything that writes memory, and subroutine calls, but not pushes). */
263 static int mem_last_set;
265 /* Record the luid of the last CALL_INSN
266 so we can tell whether a potential combination crosses any calls. */
268 static int last_call_luid;
270 /* When `subst' is called, this is the insn that is being modified
271 (by combining in a previous insn). The PATTERN of this insn
272 is still the old pattern partially modified and it should not be
273 looked at, but this may be used to examine the successors of the insn
274 to judge whether a simplification is valid. */
276 static rtx subst_insn;
278 /* This is the lowest LUID that `subst' is currently dealing with.
279 get_last_value will not return a value if the register was set at or
280 after this LUID. If not for this mechanism, we could get confused if
281 I2 or I1 in try_combine were an insn that used the old value of a register
282 to obtain a new value. In that case, we might erroneously get the
283 new value of the register when we wanted the old one. */
285 static int subst_low_luid;
287 /* This contains any hard registers that are used in newpat; reg_dead_at_p
288 must consider all these registers to be always live. */
290 static HARD_REG_SET newpat_used_regs;
292 /* This is an insn to which a LOG_LINKS entry has been added. If this
293 insn is the earlier than I2 or I3, combine should rescan starting at
296 static rtx added_links_insn;
298 /* Basic block in which we are performing combines. */
299 static basic_block this_basic_block;
300 static bool optimize_this_for_speed_p;
303 /* Length of the currently allocated uid_insn_cost array. */
305 static int max_uid_known;
307 /* The following array records the insn_rtx_cost for every insn
308 in the instruction stream. */
310 static int *uid_insn_cost;
312 /* The following array records the LOG_LINKS for every insn in the
313 instruction stream as an INSN_LIST rtx. */
315 static rtx *uid_log_links;
317 #define INSN_COST(INSN) (uid_insn_cost[INSN_UID (INSN)])
318 #define LOG_LINKS(INSN) (uid_log_links[INSN_UID (INSN)])
320 /* Incremented for each basic block. */
322 static int label_tick;
324 /* Reset to label_tick for each extended basic block in scanning order. */
326 static int label_tick_ebb_start;
328 /* Mode used to compute significance in reg_stat[].nonzero_bits. It is the
329 largest integer mode that can fit in HOST_BITS_PER_WIDE_INT. */
331 static enum machine_mode nonzero_bits_mode;
333 /* Nonzero when reg_stat[].nonzero_bits and reg_stat[].sign_bit_copies can
334 be safely used. It is zero while computing them and after combine has
335 completed. This former test prevents propagating values based on
336 previously set values, which can be incorrect if a variable is modified
339 static int nonzero_sign_valid;
342 /* Record one modification to rtl structure
343 to be undone by storing old_contents into *where. */
345 enum undo_kind { UNDO_RTX, UNDO_INT, UNDO_MODE };
351 union { rtx r; int i; enum machine_mode m; } old_contents;
352 union { rtx *r; int *i; } where;
355 /* Record a bunch of changes to be undone, up to MAX_UNDO of them.
356 num_undo says how many are currently recorded.
358 other_insn is nonzero if we have modified some other insn in the process
359 of working on subst_insn. It must be verified too. */
368 static struct undobuf undobuf;
370 /* Number of times the pseudo being substituted for
371 was found and replaced. */
373 static int n_occurrences;
375 static rtx reg_nonzero_bits_for_combine (const_rtx, enum machine_mode, const_rtx,
377 unsigned HOST_WIDE_INT,
378 unsigned HOST_WIDE_INT *);
379 static rtx reg_num_sign_bit_copies_for_combine (const_rtx, enum machine_mode, const_rtx,
381 unsigned int, unsigned int *);
382 static void do_SUBST (rtx *, rtx);
383 static void do_SUBST_INT (int *, int);
384 static void init_reg_last (void);
385 static void setup_incoming_promotions (rtx);
386 static void set_nonzero_bits_and_sign_copies (rtx, const_rtx, void *);
387 static int cant_combine_insn_p (rtx);
388 static int can_combine_p (rtx, rtx, rtx, rtx, rtx, rtx, rtx *, rtx *);
389 static int combinable_i3pat (rtx, rtx *, rtx, rtx, rtx, int, int, rtx *);
390 static int contains_muldiv (rtx);
391 static rtx try_combine (rtx, rtx, rtx, rtx, int *);
392 static void undo_all (void);
393 static void undo_commit (void);
394 static rtx *find_split_point (rtx *, rtx, bool);
395 static rtx subst (rtx, rtx, rtx, int, int);
396 static rtx combine_simplify_rtx (rtx, enum machine_mode, int);
397 static rtx simplify_if_then_else (rtx);
398 static rtx simplify_set (rtx);
399 static rtx simplify_logical (rtx);
400 static rtx expand_compound_operation (rtx);
401 static const_rtx expand_field_assignment (const_rtx);
402 static rtx make_extraction (enum machine_mode, rtx, HOST_WIDE_INT,
403 rtx, unsigned HOST_WIDE_INT, int, int, int);
404 static rtx extract_left_shift (rtx, int);
405 static rtx make_compound_operation (rtx, enum rtx_code);
406 static int get_pos_from_mask (unsigned HOST_WIDE_INT,
407 unsigned HOST_WIDE_INT *);
408 static rtx canon_reg_for_combine (rtx, rtx);
409 static rtx force_to_mode (rtx, enum machine_mode,
410 unsigned HOST_WIDE_INT, int);
411 static rtx if_then_else_cond (rtx, rtx *, rtx *);
412 static rtx known_cond (rtx, enum rtx_code, rtx, rtx);
413 static int rtx_equal_for_field_assignment_p (rtx, rtx);
414 static rtx make_field_assignment (rtx);
415 static rtx apply_distributive_law (rtx);
416 static rtx distribute_and_simplify_rtx (rtx, int);
417 static rtx simplify_and_const_int_1 (enum machine_mode, rtx,
418 unsigned HOST_WIDE_INT);
419 static rtx simplify_and_const_int (rtx, enum machine_mode, rtx,
420 unsigned HOST_WIDE_INT);
421 static int merge_outer_ops (enum rtx_code *, HOST_WIDE_INT *, enum rtx_code,
422 HOST_WIDE_INT, enum machine_mode, int *);
423 static rtx simplify_shift_const_1 (enum rtx_code, enum machine_mode, rtx, int);
424 static rtx simplify_shift_const (rtx, enum rtx_code, enum machine_mode, rtx,
426 static int recog_for_combine (rtx *, rtx, rtx *);
427 static rtx gen_lowpart_for_combine (enum machine_mode, rtx);
428 static enum rtx_code simplify_comparison (enum rtx_code, rtx *, rtx *);
429 static void update_table_tick (rtx);
430 static void record_value_for_reg (rtx, rtx, rtx);
431 static void check_promoted_subreg (rtx, rtx);
432 static void record_dead_and_set_regs_1 (rtx, const_rtx, void *);
433 static void record_dead_and_set_regs (rtx);
434 static int get_last_value_validate (rtx *, rtx, int, int);
435 static rtx get_last_value (const_rtx);
436 static int use_crosses_set_p (const_rtx, int);
437 static void reg_dead_at_p_1 (rtx, const_rtx, void *);
438 static int reg_dead_at_p (rtx, rtx);
439 static void move_deaths (rtx, rtx, int, rtx, rtx *);
440 static int reg_bitfield_target_p (rtx, rtx);
441 static void distribute_notes (rtx, rtx, rtx, rtx, rtx, rtx, rtx);
442 static void distribute_links (rtx);
443 static void mark_used_regs_combine (rtx);
444 static void record_promoted_value (rtx, rtx);
445 static int unmentioned_reg_p_1 (rtx *, void *);
446 static bool unmentioned_reg_p (rtx, rtx);
447 static int record_truncated_value (rtx *, void *);
448 static void record_truncated_values (rtx *, void *);
449 static bool reg_truncated_to_mode (enum machine_mode, const_rtx);
450 static rtx gen_lowpart_or_truncate (enum machine_mode, rtx);
453 /* It is not safe to use ordinary gen_lowpart in combine.
454 See comments in gen_lowpart_for_combine. */
455 #undef RTL_HOOKS_GEN_LOWPART
456 #define RTL_HOOKS_GEN_LOWPART gen_lowpart_for_combine
458 /* Our implementation of gen_lowpart never emits a new pseudo. */
459 #undef RTL_HOOKS_GEN_LOWPART_NO_EMIT
460 #define RTL_HOOKS_GEN_LOWPART_NO_EMIT gen_lowpart_for_combine
462 #undef RTL_HOOKS_REG_NONZERO_REG_BITS
463 #define RTL_HOOKS_REG_NONZERO_REG_BITS reg_nonzero_bits_for_combine
465 #undef RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES
466 #define RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES reg_num_sign_bit_copies_for_combine
468 #undef RTL_HOOKS_REG_TRUNCATED_TO_MODE
469 #define RTL_HOOKS_REG_TRUNCATED_TO_MODE reg_truncated_to_mode
471 static const struct rtl_hooks combine_rtl_hooks = RTL_HOOKS_INITIALIZER;
474 /* Try to split PATTERN found in INSN. This returns NULL_RTX if
475 PATTERN can not be split. Otherwise, it returns an insn sequence.
476 This is a wrapper around split_insns which ensures that the
477 reg_stat vector is made larger if the splitter creates a new
481 combine_split_insns (rtx pattern, rtx insn)
486 ret = split_insns (pattern, insn);
487 nregs = max_reg_num ();
488 if (nregs > VEC_length (reg_stat_type, reg_stat))
489 VEC_safe_grow_cleared (reg_stat_type, heap, reg_stat, nregs);
493 /* This is used by find_single_use to locate an rtx in LOC that
494 contains exactly one use of DEST, which is typically either a REG
495 or CC0. It returns a pointer to the innermost rtx expression
496 containing DEST. Appearances of DEST that are being used to
497 totally replace it are not counted. */
500 find_single_use_1 (rtx dest, rtx *loc)
503 enum rtx_code code = GET_CODE (x);
521 /* If the destination is anything other than CC0, PC, a REG or a SUBREG
522 of a REG that occupies all of the REG, the insn uses DEST if
523 it is mentioned in the destination or the source. Otherwise, we
524 need just check the source. */
525 if (GET_CODE (SET_DEST (x)) != CC0
526 && GET_CODE (SET_DEST (x)) != PC
527 && !REG_P (SET_DEST (x))
528 && ! (GET_CODE (SET_DEST (x)) == SUBREG
529 && REG_P (SUBREG_REG (SET_DEST (x)))
530 && (((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x))))
531 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
532 == ((GET_MODE_SIZE (GET_MODE (SET_DEST (x)))
533 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD))))
536 return find_single_use_1 (dest, &SET_SRC (x));
540 return find_single_use_1 (dest, &XEXP (x, 0));
546 /* If it wasn't one of the common cases above, check each expression and
547 vector of this code. Look for a unique usage of DEST. */
549 fmt = GET_RTX_FORMAT (code);
550 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
554 if (dest == XEXP (x, i)
555 || (REG_P (dest) && REG_P (XEXP (x, i))
556 && REGNO (dest) == REGNO (XEXP (x, i))))
559 this_result = find_single_use_1 (dest, &XEXP (x, i));
562 result = this_result;
563 else if (this_result)
564 /* Duplicate usage. */
567 else if (fmt[i] == 'E')
571 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
573 if (XVECEXP (x, i, j) == dest
575 && REG_P (XVECEXP (x, i, j))
576 && REGNO (XVECEXP (x, i, j)) == REGNO (dest)))
579 this_result = find_single_use_1 (dest, &XVECEXP (x, i, j));
582 result = this_result;
583 else if (this_result)
593 /* See if DEST, produced in INSN, is used only a single time in the
594 sequel. If so, return a pointer to the innermost rtx expression in which
597 If PLOC is nonzero, *PLOC is set to the insn containing the single use.
599 If DEST is cc0_rtx, we look only at the next insn. In that case, we don't
600 care about REG_DEAD notes or LOG_LINKS.
602 Otherwise, we find the single use by finding an insn that has a
603 LOG_LINKS pointing at INSN and has a REG_DEAD note for DEST. If DEST is
604 only referenced once in that insn, we know that it must be the first
605 and last insn referencing DEST. */
608 find_single_use (rtx dest, rtx insn, rtx *ploc)
618 next = NEXT_INSN (insn);
620 || (!NONJUMP_INSN_P (next) && !JUMP_P (next)))
623 result = find_single_use_1 (dest, &PATTERN (next));
633 bb = BLOCK_FOR_INSN (insn);
634 for (next = NEXT_INSN (insn);
635 next && BLOCK_FOR_INSN (next) == bb;
636 next = NEXT_INSN (next))
637 if (INSN_P (next) && dead_or_set_p (next, dest))
639 for (link = LOG_LINKS (next); link; link = XEXP (link, 1))
640 if (XEXP (link, 0) == insn)
645 result = find_single_use_1 (dest, &PATTERN (next));
655 /* Substitute NEWVAL, an rtx expression, into INTO, a place in some
656 insn. The substitution can be undone by undo_all. If INTO is already
657 set to NEWVAL, do not record this change. Because computing NEWVAL might
658 also call SUBST, we have to compute it before we put anything into
662 do_SUBST (rtx *into, rtx newval)
667 if (oldval == newval)
670 /* We'd like to catch as many invalid transformations here as
671 possible. Unfortunately, there are way too many mode changes
672 that are perfectly valid, so we'd waste too much effort for
673 little gain doing the checks here. Focus on catching invalid
674 transformations involving integer constants. */
675 if (GET_MODE_CLASS (GET_MODE (oldval)) == MODE_INT
676 && CONST_INT_P (newval))
678 /* Sanity check that we're replacing oldval with a CONST_INT
679 that is a valid sign-extension for the original mode. */
680 gcc_assert (INTVAL (newval)
681 == trunc_int_for_mode (INTVAL (newval), GET_MODE (oldval)));
683 /* Replacing the operand of a SUBREG or a ZERO_EXTEND with a
684 CONST_INT is not valid, because after the replacement, the
685 original mode would be gone. Unfortunately, we can't tell
686 when do_SUBST is called to replace the operand thereof, so we
687 perform this test on oldval instead, checking whether an
688 invalid replacement took place before we got here. */
689 gcc_assert (!(GET_CODE (oldval) == SUBREG
690 && CONST_INT_P (SUBREG_REG (oldval))));
691 gcc_assert (!(GET_CODE (oldval) == ZERO_EXTEND
692 && CONST_INT_P (XEXP (oldval, 0))));
696 buf = undobuf.frees, undobuf.frees = buf->next;
698 buf = XNEW (struct undo);
700 buf->kind = UNDO_RTX;
702 buf->old_contents.r = oldval;
705 buf->next = undobuf.undos, undobuf.undos = buf;
708 #define SUBST(INTO, NEWVAL) do_SUBST(&(INTO), (NEWVAL))
710 /* Similar to SUBST, but NEWVAL is an int expression. Note that substitution
711 for the value of a HOST_WIDE_INT value (including CONST_INT) is
715 do_SUBST_INT (int *into, int newval)
720 if (oldval == newval)
724 buf = undobuf.frees, undobuf.frees = buf->next;
726 buf = XNEW (struct undo);
728 buf->kind = UNDO_INT;
730 buf->old_contents.i = oldval;
733 buf->next = undobuf.undos, undobuf.undos = buf;
736 #define SUBST_INT(INTO, NEWVAL) do_SUBST_INT(&(INTO), (NEWVAL))
738 /* Similar to SUBST, but just substitute the mode. This is used when
739 changing the mode of a pseudo-register, so that any other
740 references to the entry in the regno_reg_rtx array will change as
744 do_SUBST_MODE (rtx *into, enum machine_mode newval)
747 enum machine_mode oldval = GET_MODE (*into);
749 if (oldval == newval)
753 buf = undobuf.frees, undobuf.frees = buf->next;
755 buf = XNEW (struct undo);
757 buf->kind = UNDO_MODE;
759 buf->old_contents.m = oldval;
760 adjust_reg_mode (*into, newval);
762 buf->next = undobuf.undos, undobuf.undos = buf;
765 #define SUBST_MODE(INTO, NEWVAL) do_SUBST_MODE(&(INTO), (NEWVAL))
767 /* Subroutine of try_combine. Determine whether the combine replacement
768 patterns NEWPAT, NEWI2PAT and NEWOTHERPAT are cheaper according to
769 insn_rtx_cost that the original instruction sequence I0, I1, I2, I3 and
770 undobuf.other_insn. Note that I1 and/or NEWI2PAT may be NULL_RTX.
771 NEWOTHERPAT and undobuf.other_insn may also both be NULL_RTX. This
772 function returns false, if the costs of all instructions can be
773 estimated, and the replacements are more expensive than the original
777 combine_validate_cost (rtx i0, rtx i1, rtx i2, rtx i3, rtx newpat,
778 rtx newi2pat, rtx newotherpat)
780 int i0_cost, i1_cost, i2_cost, i3_cost;
781 int new_i2_cost, new_i3_cost;
782 int old_cost, new_cost;
784 /* Lookup the original insn_rtx_costs. */
785 i2_cost = INSN_COST (i2);
786 i3_cost = INSN_COST (i3);
790 i1_cost = INSN_COST (i1);
793 i0_cost = INSN_COST (i0);
794 old_cost = (i0_cost > 0 && i1_cost > 0 && i2_cost > 0 && i3_cost > 0
795 ? i0_cost + i1_cost + i2_cost + i3_cost : 0);
799 old_cost = (i1_cost > 0 && i2_cost > 0 && i3_cost > 0
800 ? i1_cost + i2_cost + i3_cost : 0);
806 old_cost = (i2_cost > 0 && i3_cost > 0) ? i2_cost + i3_cost : 0;
807 i1_cost = i0_cost = 0;
810 /* Calculate the replacement insn_rtx_costs. */
811 new_i3_cost = insn_rtx_cost (newpat, optimize_this_for_speed_p);
814 new_i2_cost = insn_rtx_cost (newi2pat, optimize_this_for_speed_p);
815 new_cost = (new_i2_cost > 0 && new_i3_cost > 0)
816 ? new_i2_cost + new_i3_cost : 0;
820 new_cost = new_i3_cost;
824 if (undobuf.other_insn)
826 int old_other_cost, new_other_cost;
828 old_other_cost = INSN_COST (undobuf.other_insn);
829 new_other_cost = insn_rtx_cost (newotherpat, optimize_this_for_speed_p);
830 if (old_other_cost > 0 && new_other_cost > 0)
832 old_cost += old_other_cost;
833 new_cost += new_other_cost;
839 /* Disallow this recombination if both new_cost and old_cost are
840 greater than zero, and new_cost is greater than old cost. */
842 && new_cost > old_cost)
849 "rejecting combination of insns %d, %d, %d and %d\n",
850 INSN_UID (i0), INSN_UID (i1), INSN_UID (i2),
852 fprintf (dump_file, "original costs %d + %d + %d + %d = %d\n",
853 i0_cost, i1_cost, i2_cost, i3_cost, old_cost);
858 "rejecting combination of insns %d, %d and %d\n",
859 INSN_UID (i1), INSN_UID (i2), INSN_UID (i3));
860 fprintf (dump_file, "original costs %d + %d + %d = %d\n",
861 i1_cost, i2_cost, i3_cost, old_cost);
866 "rejecting combination of insns %d and %d\n",
867 INSN_UID (i2), INSN_UID (i3));
868 fprintf (dump_file, "original costs %d + %d = %d\n",
869 i2_cost, i3_cost, old_cost);
874 fprintf (dump_file, "replacement costs %d + %d = %d\n",
875 new_i2_cost, new_i3_cost, new_cost);
878 fprintf (dump_file, "replacement cost %d\n", new_cost);
884 /* Update the uid_insn_cost array with the replacement costs. */
885 INSN_COST (i2) = new_i2_cost;
886 INSN_COST (i3) = new_i3_cost;
894 /* Delete any insns that copy a register to itself. */
897 delete_noop_moves (void)
904 for (insn = BB_HEAD (bb); insn != NEXT_INSN (BB_END (bb)); insn = next)
906 next = NEXT_INSN (insn);
907 if (INSN_P (insn) && noop_move_p (insn))
910 fprintf (dump_file, "deleting noop move %d\n", INSN_UID (insn));
912 delete_insn_and_edges (insn);
919 /* Fill in log links field for all insns. */
922 create_log_links (void)
926 df_ref *def_vec, *use_vec;
928 next_use = XCNEWVEC (rtx, max_reg_num ());
930 /* Pass through each block from the end, recording the uses of each
931 register and establishing log links when def is encountered.
932 Note that we do not clear next_use array in order to save time,
933 so we have to test whether the use is in the same basic block as def.
935 There are a few cases below when we do not consider the definition or
936 usage -- these are taken from original flow.c did. Don't ask me why it is
937 done this way; I don't know and if it works, I don't want to know. */
941 FOR_BB_INSNS_REVERSE (bb, insn)
943 if (!NONDEBUG_INSN_P (insn))
946 /* Log links are created only once. */
947 gcc_assert (!LOG_LINKS (insn));
949 for (def_vec = DF_INSN_DEFS (insn); *def_vec; def_vec++)
951 df_ref def = *def_vec;
952 int regno = DF_REF_REGNO (def);
955 if (!next_use[regno])
958 /* Do not consider if it is pre/post modification in MEM. */
959 if (DF_REF_FLAGS (def) & DF_REF_PRE_POST_MODIFY)
962 /* Do not make the log link for frame pointer. */
963 if ((regno == FRAME_POINTER_REGNUM
964 && (! reload_completed || frame_pointer_needed))
965 #if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM
966 || (regno == HARD_FRAME_POINTER_REGNUM
967 && (! reload_completed || frame_pointer_needed))
969 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
970 || (regno == ARG_POINTER_REGNUM && fixed_regs[regno])
975 use_insn = next_use[regno];
976 if (BLOCK_FOR_INSN (use_insn) == bb)
980 We don't build a LOG_LINK for hard registers contained
981 in ASM_OPERANDs. If these registers get replaced,
982 we might wind up changing the semantics of the insn,
983 even if reload can make what appear to be valid
984 assignments later. */
985 if (regno >= FIRST_PSEUDO_REGISTER
986 || asm_noperands (PATTERN (use_insn)) < 0)
988 /* Don't add duplicate links between instructions. */
990 for (links = LOG_LINKS (use_insn); links;
991 links = XEXP (links, 1))
992 if (insn == XEXP (links, 0))
996 LOG_LINKS (use_insn) =
997 alloc_INSN_LIST (insn, LOG_LINKS (use_insn));
1000 next_use[regno] = NULL_RTX;
1003 for (use_vec = DF_INSN_USES (insn); *use_vec; use_vec++)
1005 df_ref use = *use_vec;
1006 int regno = DF_REF_REGNO (use);
1008 /* Do not consider the usage of the stack pointer
1009 by function call. */
1010 if (DF_REF_FLAGS (use) & DF_REF_CALL_STACK_USAGE)
1013 next_use[regno] = insn;
1021 /* Clear LOG_LINKS fields of insns. */
1024 clear_log_links (void)
1028 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
1030 free_INSN_LIST_list (&LOG_LINKS (insn));
1033 /* Walk the LOG_LINKS of insn B to see if we find a reference to A. Return
1034 true if we found a LOG_LINK that proves that A feeds B. This only works
1035 if there are no instructions between A and B which could have a link
1036 depending on A, since in that case we would not record a link for B. */
1039 insn_a_feeds_b (rtx a, rtx b)
1042 for (links = LOG_LINKS (b); links; links = XEXP (links, 1))
1043 if (XEXP (links, 0) == a)
1048 /* Main entry point for combiner. F is the first insn of the function.
1049 NREGS is the first unused pseudo-reg number.
1051 Return nonzero if the combiner has turned an indirect jump
1052 instruction into a direct jump. */
1054 combine_instructions (rtx f, unsigned int nregs)
1060 rtx links, nextlinks;
1062 basic_block last_bb;
1064 int new_direct_jump_p = 0;
1066 for (first = f; first && !INSN_P (first); )
1067 first = NEXT_INSN (first);
1071 combine_attempts = 0;
1074 combine_successes = 0;
1076 rtl_hooks = combine_rtl_hooks;
1078 VEC_safe_grow_cleared (reg_stat_type, heap, reg_stat, nregs);
1080 init_recog_no_volatile ();
1082 /* Allocate array for insn info. */
1083 max_uid_known = get_max_uid ();
1084 uid_log_links = XCNEWVEC (rtx, max_uid_known + 1);
1085 uid_insn_cost = XCNEWVEC (int, max_uid_known + 1);
1087 nonzero_bits_mode = mode_for_size (HOST_BITS_PER_WIDE_INT, MODE_INT, 0);
1089 /* Don't use reg_stat[].nonzero_bits when computing it. This can cause
1090 problems when, for example, we have j <<= 1 in a loop. */
1092 nonzero_sign_valid = 0;
1093 label_tick = label_tick_ebb_start = 1;
1095 /* Scan all SETs and see if we can deduce anything about what
1096 bits are known to be zero for some registers and how many copies
1097 of the sign bit are known to exist for those registers.
1099 Also set any known values so that we can use it while searching
1100 for what bits are known to be set. */
1102 setup_incoming_promotions (first);
1103 /* Allow the entry block and the first block to fall into the same EBB.
1104 Conceptually the incoming promotions are assigned to the entry block. */
1105 last_bb = ENTRY_BLOCK_PTR;
1107 create_log_links ();
1108 FOR_EACH_BB (this_basic_block)
1110 optimize_this_for_speed_p = optimize_bb_for_speed_p (this_basic_block);
1115 if (!single_pred_p (this_basic_block)
1116 || single_pred (this_basic_block) != last_bb)
1117 label_tick_ebb_start = label_tick;
1118 last_bb = this_basic_block;
1120 FOR_BB_INSNS (this_basic_block, insn)
1121 if (INSN_P (insn) && BLOCK_FOR_INSN (insn))
1123 subst_low_luid = DF_INSN_LUID (insn);
1126 note_stores (PATTERN (insn), set_nonzero_bits_and_sign_copies,
1128 record_dead_and_set_regs (insn);
1131 for (links = REG_NOTES (insn); links; links = XEXP (links, 1))
1132 if (REG_NOTE_KIND (links) == REG_INC)
1133 set_nonzero_bits_and_sign_copies (XEXP (links, 0), NULL_RTX,
1137 /* Record the current insn_rtx_cost of this instruction. */
1138 if (NONJUMP_INSN_P (insn))
1139 INSN_COST (insn) = insn_rtx_cost (PATTERN (insn),
1140 optimize_this_for_speed_p);
1142 fprintf(dump_file, "insn_cost %d: %d\n",
1143 INSN_UID (insn), INSN_COST (insn));
1147 nonzero_sign_valid = 1;
1149 /* Now scan all the insns in forward order. */
1150 label_tick = label_tick_ebb_start = 1;
1152 setup_incoming_promotions (first);
1153 last_bb = ENTRY_BLOCK_PTR;
1155 FOR_EACH_BB (this_basic_block)
1157 optimize_this_for_speed_p = optimize_bb_for_speed_p (this_basic_block);
1162 if (!single_pred_p (this_basic_block)
1163 || single_pred (this_basic_block) != last_bb)
1164 label_tick_ebb_start = label_tick;
1165 last_bb = this_basic_block;
1167 rtl_profile_for_bb (this_basic_block);
1168 for (insn = BB_HEAD (this_basic_block);
1169 insn != NEXT_INSN (BB_END (this_basic_block));
1170 insn = next ? next : NEXT_INSN (insn))
1173 if (NONDEBUG_INSN_P (insn))
1175 /* See if we know about function return values before this
1176 insn based upon SUBREG flags. */
1177 check_promoted_subreg (insn, PATTERN (insn));
1179 /* See if we can find hardregs and subreg of pseudos in
1180 narrower modes. This could help turning TRUNCATEs
1182 note_uses (&PATTERN (insn), record_truncated_values, NULL);
1184 /* Try this insn with each insn it links back to. */
1186 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
1187 if ((next = try_combine (insn, XEXP (links, 0), NULL_RTX,
1188 NULL_RTX, &new_direct_jump_p)) != 0)
1191 /* Try each sequence of three linked insns ending with this one. */
1193 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
1195 rtx link = XEXP (links, 0);
1197 /* If the linked insn has been replaced by a note, then there
1198 is no point in pursuing this chain any further. */
1202 for (nextlinks = LOG_LINKS (link);
1204 nextlinks = XEXP (nextlinks, 1))
1205 if ((next = try_combine (insn, link, XEXP (nextlinks, 0),
1207 &new_direct_jump_p)) != 0)
1212 /* Try to combine a jump insn that uses CC0
1213 with a preceding insn that sets CC0, and maybe with its
1214 logical predecessor as well.
1215 This is how we make decrement-and-branch insns.
1216 We need this special code because data flow connections
1217 via CC0 do not get entered in LOG_LINKS. */
1220 && (prev = prev_nonnote_insn (insn)) != 0
1221 && NONJUMP_INSN_P (prev)
1222 && sets_cc0_p (PATTERN (prev)))
1224 if ((next = try_combine (insn, prev, NULL_RTX, NULL_RTX,
1225 &new_direct_jump_p)) != 0)
1228 for (nextlinks = LOG_LINKS (prev); nextlinks;
1229 nextlinks = XEXP (nextlinks, 1))
1230 if ((next = try_combine (insn, prev, XEXP (nextlinks, 0),
1232 &new_direct_jump_p)) != 0)
1236 /* Do the same for an insn that explicitly references CC0. */
1237 if (NONJUMP_INSN_P (insn)
1238 && (prev = prev_nonnote_insn (insn)) != 0
1239 && NONJUMP_INSN_P (prev)
1240 && sets_cc0_p (PATTERN (prev))
1241 && GET_CODE (PATTERN (insn)) == SET
1242 && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (insn))))
1244 if ((next = try_combine (insn, prev, NULL_RTX, NULL_RTX,
1245 &new_direct_jump_p)) != 0)
1248 for (nextlinks = LOG_LINKS (prev); nextlinks;
1249 nextlinks = XEXP (nextlinks, 1))
1250 if ((next = try_combine (insn, prev, XEXP (nextlinks, 0),
1252 &new_direct_jump_p)) != 0)
1256 /* Finally, see if any of the insns that this insn links to
1257 explicitly references CC0. If so, try this insn, that insn,
1258 and its predecessor if it sets CC0. */
1259 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
1260 if (NONJUMP_INSN_P (XEXP (links, 0))
1261 && GET_CODE (PATTERN (XEXP (links, 0))) == SET
1262 && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (XEXP (links, 0))))
1263 && (prev = prev_nonnote_insn (XEXP (links, 0))) != 0
1264 && NONJUMP_INSN_P (prev)
1265 && sets_cc0_p (PATTERN (prev))
1266 && (next = try_combine (insn, XEXP (links, 0),
1268 &new_direct_jump_p)) != 0)
1272 /* Try combining an insn with two different insns whose results it
1274 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
1275 for (nextlinks = XEXP (links, 1); nextlinks;
1276 nextlinks = XEXP (nextlinks, 1))
1277 if ((next = try_combine (insn, XEXP (links, 0),
1278 XEXP (nextlinks, 0), NULL_RTX,
1279 &new_direct_jump_p)) != 0)
1282 /* Try four-instruction combinations. */
1283 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
1286 rtx link = XEXP (links, 0);
1288 /* If the linked insn has been replaced by a note, then there
1289 is no point in pursuing this chain any further. */
1293 for (next1 = LOG_LINKS (link); next1; next1 = XEXP (next1, 1))
1295 rtx link1 = XEXP (next1, 0);
1298 /* I0 -> I1 -> I2 -> I3. */
1299 for (nextlinks = LOG_LINKS (link1); nextlinks;
1300 nextlinks = XEXP (nextlinks, 1))
1301 if ((next = try_combine (insn, link, link1,
1302 XEXP (nextlinks, 0),
1303 &new_direct_jump_p)) != 0)
1305 /* I0, I1 -> I2, I2 -> I3. */
1306 for (nextlinks = XEXP (next1, 1); nextlinks;
1307 nextlinks = XEXP (nextlinks, 1))
1308 if ((next = try_combine (insn, link, link1,
1309 XEXP (nextlinks, 0),
1310 &new_direct_jump_p)) != 0)
1314 for (next1 = XEXP (links, 1); next1; next1 = XEXP (next1, 1))
1316 rtx link1 = XEXP (next1, 0);
1319 /* I0 -> I2; I1, I2 -> I3. */
1320 for (nextlinks = LOG_LINKS (link); nextlinks;
1321 nextlinks = XEXP (nextlinks, 1))
1322 if ((next = try_combine (insn, link, link1,
1323 XEXP (nextlinks, 0),
1324 &new_direct_jump_p)) != 0)
1326 /* I0 -> I1; I1, I2 -> I3. */
1327 for (nextlinks = LOG_LINKS (link1); nextlinks;
1328 nextlinks = XEXP (nextlinks, 1))
1329 if ((next = try_combine (insn, link, link1,
1330 XEXP (nextlinks, 0),
1331 &new_direct_jump_p)) != 0)
1336 /* Try this insn with each REG_EQUAL note it links back to. */
1337 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
1340 rtx temp = XEXP (links, 0);
1341 if ((set = single_set (temp)) != 0
1342 && (note = find_reg_equal_equiv_note (temp)) != 0
1343 && (note = XEXP (note, 0), GET_CODE (note)) != EXPR_LIST
1344 /* Avoid using a register that may already been marked
1345 dead by an earlier instruction. */
1346 && ! unmentioned_reg_p (note, SET_SRC (set))
1347 && (GET_MODE (note) == VOIDmode
1348 ? SCALAR_INT_MODE_P (GET_MODE (SET_DEST (set)))
1349 : GET_MODE (SET_DEST (set)) == GET_MODE (note)))
1351 /* Temporarily replace the set's source with the
1352 contents of the REG_EQUAL note. The insn will
1353 be deleted or recognized by try_combine. */
1354 rtx orig = SET_SRC (set);
1355 SET_SRC (set) = note;
1357 i2mod_old_rhs = copy_rtx (orig);
1358 i2mod_new_rhs = copy_rtx (note);
1359 next = try_combine (insn, i2mod, NULL_RTX, NULL_RTX,
1360 &new_direct_jump_p);
1364 SET_SRC (set) = orig;
1369 record_dead_and_set_regs (insn);
1377 default_rtl_profile ();
1380 new_direct_jump_p |= purge_all_dead_edges ();
1381 delete_noop_moves ();
1384 free (uid_log_links);
1385 free (uid_insn_cost);
1386 VEC_free (reg_stat_type, heap, reg_stat);
1389 struct undo *undo, *next;
1390 for (undo = undobuf.frees; undo; undo = next)
1398 total_attempts += combine_attempts;
1399 total_merges += combine_merges;
1400 total_extras += combine_extras;
1401 total_successes += combine_successes;
1403 nonzero_sign_valid = 0;
1404 rtl_hooks = general_rtl_hooks;
1406 /* Make recognizer allow volatile MEMs again. */
1409 return new_direct_jump_p;
1412 /* Wipe the last_xxx fields of reg_stat in preparation for another pass. */
1415 init_reg_last (void)
1420 for (i = 0; VEC_iterate (reg_stat_type, reg_stat, i, p); ++i)
1421 memset (p, 0, offsetof (reg_stat_type, sign_bit_copies));
1424 /* Set up any promoted values for incoming argument registers. */
1427 setup_incoming_promotions (rtx first)
1430 bool strictly_local = false;
1432 for (arg = DECL_ARGUMENTS (current_function_decl); arg;
1433 arg = DECL_CHAIN (arg))
1435 rtx x, reg = DECL_INCOMING_RTL (arg);
1437 enum machine_mode mode1, mode2, mode3, mode4;
1439 /* Only continue if the incoming argument is in a register. */
1443 /* Determine, if possible, whether all call sites of the current
1444 function lie within the current compilation unit. (This does
1445 take into account the exporting of a function via taking its
1446 address, and so forth.) */
1447 strictly_local = cgraph_local_info (current_function_decl)->local;
1449 /* The mode and signedness of the argument before any promotions happen
1450 (equal to the mode of the pseudo holding it at that stage). */
1451 mode1 = TYPE_MODE (TREE_TYPE (arg));
1452 uns1 = TYPE_UNSIGNED (TREE_TYPE (arg));
1454 /* The mode and signedness of the argument after any source language and
1455 TARGET_PROMOTE_PROTOTYPES-driven promotions. */
1456 mode2 = TYPE_MODE (DECL_ARG_TYPE (arg));
1457 uns3 = TYPE_UNSIGNED (DECL_ARG_TYPE (arg));
1459 /* The mode and signedness of the argument as it is actually passed,
1460 after any TARGET_PROMOTE_FUNCTION_ARGS-driven ABI promotions. */
1461 mode3 = promote_function_mode (DECL_ARG_TYPE (arg), mode2, &uns3,
1462 TREE_TYPE (cfun->decl), 0);
1464 /* The mode of the register in which the argument is being passed. */
1465 mode4 = GET_MODE (reg);
1467 /* Eliminate sign extensions in the callee when:
1468 (a) A mode promotion has occurred; */
1471 /* (b) The mode of the register is the same as the mode of
1472 the argument as it is passed; */
1475 /* (c) There's no language level extension; */
1478 /* (c.1) All callers are from the current compilation unit. If that's
1479 the case we don't have to rely on an ABI, we only have to know
1480 what we're generating right now, and we know that we will do the
1481 mode1 to mode2 promotion with the given sign. */
1482 else if (!strictly_local)
1484 /* (c.2) The combination of the two promotions is useful. This is
1485 true when the signs match, or if the first promotion is unsigned.
1486 In the later case, (sign_extend (zero_extend x)) is the same as
1487 (zero_extend (zero_extend x)), so make sure to force UNS3 true. */
1493 /* Record that the value was promoted from mode1 to mode3,
1494 so that any sign extension at the head of the current
1495 function may be eliminated. */
1496 x = gen_rtx_CLOBBER (mode1, const0_rtx);
1497 x = gen_rtx_fmt_e ((uns3 ? ZERO_EXTEND : SIGN_EXTEND), mode3, x);
1498 record_value_for_reg (reg, first, x);
1502 /* Called via note_stores. If X is a pseudo that is narrower than
1503 HOST_BITS_PER_WIDE_INT and is being set, record what bits are known zero.
1505 If we are setting only a portion of X and we can't figure out what
1506 portion, assume all bits will be used since we don't know what will
1509 Similarly, set how many bits of X are known to be copies of the sign bit
1510 at all locations in the function. This is the smallest number implied
1514 set_nonzero_bits_and_sign_copies (rtx x, const_rtx set, void *data)
1516 rtx insn = (rtx) data;
1520 && REGNO (x) >= FIRST_PSEUDO_REGISTER
1521 /* If this register is undefined at the start of the file, we can't
1522 say what its contents were. */
1523 && ! REGNO_REG_SET_P
1524 (DF_LR_IN (ENTRY_BLOCK_PTR->next_bb), REGNO (x))
1525 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT)
1527 reg_stat_type *rsp = VEC_index (reg_stat_type, reg_stat, REGNO (x));
1529 if (set == 0 || GET_CODE (set) == CLOBBER)
1531 rsp->nonzero_bits = GET_MODE_MASK (GET_MODE (x));
1532 rsp->sign_bit_copies = 1;
1536 /* If this register is being initialized using itself, and the
1537 register is uninitialized in this basic block, and there are
1538 no LOG_LINKS which set the register, then part of the
1539 register is uninitialized. In that case we can't assume
1540 anything about the number of nonzero bits.
1542 ??? We could do better if we checked this in
1543 reg_{nonzero_bits,num_sign_bit_copies}_for_combine. Then we
1544 could avoid making assumptions about the insn which initially
1545 sets the register, while still using the information in other
1546 insns. We would have to be careful to check every insn
1547 involved in the combination. */
1550 && reg_referenced_p (x, PATTERN (insn))
1551 && !REGNO_REG_SET_P (DF_LR_IN (BLOCK_FOR_INSN (insn)),
1556 for (link = LOG_LINKS (insn); link; link = XEXP (link, 1))
1558 if (dead_or_set_p (XEXP (link, 0), x))
1563 rsp->nonzero_bits = GET_MODE_MASK (GET_MODE (x));
1564 rsp->sign_bit_copies = 1;
1569 /* If this is a complex assignment, see if we can convert it into a
1570 simple assignment. */
1571 set = expand_field_assignment (set);
1573 /* If this is a simple assignment, or we have a paradoxical SUBREG,
1574 set what we know about X. */
1576 if (SET_DEST (set) == x
1577 || (GET_CODE (SET_DEST (set)) == SUBREG
1578 && (GET_MODE_SIZE (GET_MODE (SET_DEST (set)))
1579 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (set)))))
1580 && SUBREG_REG (SET_DEST (set)) == x))
1582 rtx src = SET_SRC (set);
1584 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
1585 /* If X is narrower than a word and SRC is a non-negative
1586 constant that would appear negative in the mode of X,
1587 sign-extend it for use in reg_stat[].nonzero_bits because some
1588 machines (maybe most) will actually do the sign-extension
1589 and this is the conservative approach.
1591 ??? For 2.5, try to tighten up the MD files in this regard
1592 instead of this kludge. */
1594 if (GET_MODE_BITSIZE (GET_MODE (x)) < BITS_PER_WORD
1595 && CONST_INT_P (src)
1597 && 0 != (INTVAL (src)
1598 & ((HOST_WIDE_INT) 1
1599 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
1600 src = GEN_INT (INTVAL (src)
1601 | ((HOST_WIDE_INT) (-1)
1602 << GET_MODE_BITSIZE (GET_MODE (x))));
1605 /* Don't call nonzero_bits if it cannot change anything. */
1606 if (rsp->nonzero_bits != ~(unsigned HOST_WIDE_INT) 0)
1607 rsp->nonzero_bits |= nonzero_bits (src, nonzero_bits_mode);
1608 num = num_sign_bit_copies (SET_SRC (set), GET_MODE (x));
1609 if (rsp->sign_bit_copies == 0
1610 || rsp->sign_bit_copies > num)
1611 rsp->sign_bit_copies = num;
1615 rsp->nonzero_bits = GET_MODE_MASK (GET_MODE (x));
1616 rsp->sign_bit_copies = 1;
1621 /* See if INSN can be combined into I3. PRED, PRED2, SUCC and SUCC2 are
1622 optionally insns that were previously combined into I3 or that will be
1623 combined into the merger of INSN and I3. The order is PRED, PRED2,
1624 INSN, SUCC, SUCC2, I3.
1626 Return 0 if the combination is not allowed for any reason.
1628 If the combination is allowed, *PDEST will be set to the single
1629 destination of INSN and *PSRC to the single source, and this function
1633 can_combine_p (rtx insn, rtx i3, rtx pred ATTRIBUTE_UNUSED,
1634 rtx pred2 ATTRIBUTE_UNUSED, rtx succ, rtx succ2,
1635 rtx *pdest, rtx *psrc)
1644 bool all_adjacent = true;
1650 if (next_active_insn (succ2) != i3)
1651 all_adjacent = false;
1652 if (next_active_insn (succ) != succ2)
1653 all_adjacent = false;
1655 else if (next_active_insn (succ) != i3)
1656 all_adjacent = false;
1657 if (next_active_insn (insn) != succ)
1658 all_adjacent = false;
1660 else if (next_active_insn (insn) != i3)
1661 all_adjacent = false;
1663 /* Can combine only if previous insn is a SET of a REG, a SUBREG or CC0.
1664 or a PARALLEL consisting of such a SET and CLOBBERs.
1666 If INSN has CLOBBER parallel parts, ignore them for our processing.
1667 By definition, these happen during the execution of the insn. When it
1668 is merged with another insn, all bets are off. If they are, in fact,
1669 needed and aren't also supplied in I3, they may be added by
1670 recog_for_combine. Otherwise, it won't match.
1672 We can also ignore a SET whose SET_DEST is mentioned in a REG_UNUSED
1675 Get the source and destination of INSN. If more than one, can't
1678 if (GET_CODE (PATTERN (insn)) == SET)
1679 set = PATTERN (insn);
1680 else if (GET_CODE (PATTERN (insn)) == PARALLEL
1681 && GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == SET)
1683 for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
1685 rtx elt = XVECEXP (PATTERN (insn), 0, i);
1687 switch (GET_CODE (elt))
1689 /* This is important to combine floating point insns
1690 for the SH4 port. */
1692 /* Combining an isolated USE doesn't make sense.
1693 We depend here on combinable_i3pat to reject them. */
1694 /* The code below this loop only verifies that the inputs of
1695 the SET in INSN do not change. We call reg_set_between_p
1696 to verify that the REG in the USE does not change between
1698 If the USE in INSN was for a pseudo register, the matching
1699 insn pattern will likely match any register; combining this
1700 with any other USE would only be safe if we knew that the
1701 used registers have identical values, or if there was
1702 something to tell them apart, e.g. different modes. For
1703 now, we forgo such complicated tests and simply disallow
1704 combining of USES of pseudo registers with any other USE. */
1705 if (REG_P (XEXP (elt, 0))
1706 && GET_CODE (PATTERN (i3)) == PARALLEL)
1708 rtx i3pat = PATTERN (i3);
1709 int i = XVECLEN (i3pat, 0) - 1;
1710 unsigned int regno = REGNO (XEXP (elt, 0));
1714 rtx i3elt = XVECEXP (i3pat, 0, i);
1716 if (GET_CODE (i3elt) == USE
1717 && REG_P (XEXP (i3elt, 0))
1718 && (REGNO (XEXP (i3elt, 0)) == regno
1719 ? reg_set_between_p (XEXP (elt, 0),
1720 PREV_INSN (insn), i3)
1721 : regno >= FIRST_PSEUDO_REGISTER))
1728 /* We can ignore CLOBBERs. */
1733 /* Ignore SETs whose result isn't used but not those that
1734 have side-effects. */
1735 if (find_reg_note (insn, REG_UNUSED, SET_DEST (elt))
1736 && insn_nothrow_p (insn)
1737 && !side_effects_p (elt))
1740 /* If we have already found a SET, this is a second one and
1741 so we cannot combine with this insn. */
1749 /* Anything else means we can't combine. */
1755 /* If SET_SRC is an ASM_OPERANDS we can't throw away these CLOBBERs,
1756 so don't do anything with it. */
1757 || GET_CODE (SET_SRC (set)) == ASM_OPERANDS)
1766 set = expand_field_assignment (set);
1767 src = SET_SRC (set), dest = SET_DEST (set);
1769 /* Don't eliminate a store in the stack pointer. */
1770 if (dest == stack_pointer_rtx
1771 /* Don't combine with an insn that sets a register to itself if it has
1772 a REG_EQUAL note. This may be part of a LIBCALL sequence. */
1773 || (rtx_equal_p (src, dest) && find_reg_note (insn, REG_EQUAL, NULL_RTX))
1774 /* Can't merge an ASM_OPERANDS. */
1775 || GET_CODE (src) == ASM_OPERANDS
1776 /* Can't merge a function call. */
1777 || GET_CODE (src) == CALL
1778 /* Don't eliminate a function call argument. */
1780 && (find_reg_fusage (i3, USE, dest)
1782 && REGNO (dest) < FIRST_PSEUDO_REGISTER
1783 && global_regs[REGNO (dest)])))
1784 /* Don't substitute into an incremented register. */
1785 || FIND_REG_INC_NOTE (i3, dest)
1786 || (succ && FIND_REG_INC_NOTE (succ, dest))
1787 || (succ2 && FIND_REG_INC_NOTE (succ2, dest))
1788 /* Don't substitute into a non-local goto, this confuses CFG. */
1789 || (JUMP_P (i3) && find_reg_note (i3, REG_NON_LOCAL_GOTO, NULL_RTX))
1790 /* Make sure that DEST is not used after SUCC but before I3. */
1793 && (reg_used_between_p (dest, succ2, i3)
1794 || reg_used_between_p (dest, succ, succ2)))
1795 || (!succ2 && succ && reg_used_between_p (dest, succ, i3))))
1796 /* Make sure that the value that is to be substituted for the register
1797 does not use any registers whose values alter in between. However,
1798 If the insns are adjacent, a use can't cross a set even though we
1799 think it might (this can happen for a sequence of insns each setting
1800 the same destination; last_set of that register might point to
1801 a NOTE). If INSN has a REG_EQUIV note, the register is always
1802 equivalent to the memory so the substitution is valid even if there
1803 are intervening stores. Also, don't move a volatile asm or
1804 UNSPEC_VOLATILE across any other insns. */
1807 || ! find_reg_note (insn, REG_EQUIV, src))
1808 && use_crosses_set_p (src, DF_INSN_LUID (insn)))
1809 || (GET_CODE (src) == ASM_OPERANDS && MEM_VOLATILE_P (src))
1810 || GET_CODE (src) == UNSPEC_VOLATILE))
1811 /* Don't combine across a CALL_INSN, because that would possibly
1812 change whether the life span of some REGs crosses calls or not,
1813 and it is a pain to update that information.
1814 Exception: if source is a constant, moving it later can't hurt.
1815 Accept that as a special case. */
1816 || (DF_INSN_LUID (insn) < last_call_luid && ! CONSTANT_P (src)))
1819 /* DEST must either be a REG or CC0. */
1822 /* If register alignment is being enforced for multi-word items in all
1823 cases except for parameters, it is possible to have a register copy
1824 insn referencing a hard register that is not allowed to contain the
1825 mode being copied and which would not be valid as an operand of most
1826 insns. Eliminate this problem by not combining with such an insn.
1828 Also, on some machines we don't want to extend the life of a hard
1832 && ((REGNO (dest) < FIRST_PSEUDO_REGISTER
1833 && ! HARD_REGNO_MODE_OK (REGNO (dest), GET_MODE (dest)))
1834 /* Don't extend the life of a hard register unless it is
1835 user variable (if we have few registers) or it can't
1836 fit into the desired register (meaning something special
1838 Also avoid substituting a return register into I3, because
1839 reload can't handle a conflict with constraints of other
1841 || (REGNO (src) < FIRST_PSEUDO_REGISTER
1842 && ! HARD_REGNO_MODE_OK (REGNO (src), GET_MODE (src)))))
1845 else if (GET_CODE (dest) != CC0)
1849 if (GET_CODE (PATTERN (i3)) == PARALLEL)
1850 for (i = XVECLEN (PATTERN (i3), 0) - 1; i >= 0; i--)
1851 if (GET_CODE (XVECEXP (PATTERN (i3), 0, i)) == CLOBBER)
1853 /* Don't substitute for a register intended as a clobberable
1855 rtx reg = XEXP (XVECEXP (PATTERN (i3), 0, i), 0);
1856 if (rtx_equal_p (reg, dest))
1859 /* If the clobber represents an earlyclobber operand, we must not
1860 substitute an expression containing the clobbered register.
1861 As we do not analyze the constraint strings here, we have to
1862 make the conservative assumption. However, if the register is
1863 a fixed hard reg, the clobber cannot represent any operand;
1864 we leave it up to the machine description to either accept or
1865 reject use-and-clobber patterns. */
1867 || REGNO (reg) >= FIRST_PSEUDO_REGISTER
1868 || !fixed_regs[REGNO (reg)])
1869 if (reg_overlap_mentioned_p (reg, src))
1873 /* If INSN contains anything volatile, or is an `asm' (whether volatile
1874 or not), reject, unless nothing volatile comes between it and I3 */
1876 if (GET_CODE (src) == ASM_OPERANDS || volatile_refs_p (src))
1878 /* Make sure neither succ nor succ2 contains a volatile reference. */
1879 if (succ2 != 0 && volatile_refs_p (PATTERN (succ2)))
1881 if (succ != 0 && volatile_refs_p (PATTERN (succ)))
1883 /* We'll check insns between INSN and I3 below. */
1886 /* If INSN is an asm, and DEST is a hard register, reject, since it has
1887 to be an explicit register variable, and was chosen for a reason. */
1889 if (GET_CODE (src) == ASM_OPERANDS
1890 && REG_P (dest) && REGNO (dest) < FIRST_PSEUDO_REGISTER)
1893 /* If there are any volatile insns between INSN and I3, reject, because
1894 they might affect machine state. */
1896 for (p = NEXT_INSN (insn); p != i3; p = NEXT_INSN (p))
1897 if (INSN_P (p) && p != succ && p != succ2 && volatile_insn_p (PATTERN (p)))
1900 /* If INSN contains an autoincrement or autodecrement, make sure that
1901 register is not used between there and I3, and not already used in
1902 I3 either. Neither must it be used in PRED or SUCC, if they exist.
1903 Also insist that I3 not be a jump; if it were one
1904 and the incremented register were spilled, we would lose. */
1907 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
1908 if (REG_NOTE_KIND (link) == REG_INC
1910 || reg_used_between_p (XEXP (link, 0), insn, i3)
1911 || (pred != NULL_RTX
1912 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (pred)))
1913 || (pred2 != NULL_RTX
1914 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (pred2)))
1915 || (succ != NULL_RTX
1916 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (succ)))
1917 || (succ2 != NULL_RTX
1918 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (succ2)))
1919 || reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i3))))
1924 /* Don't combine an insn that follows a CC0-setting insn.
1925 An insn that uses CC0 must not be separated from the one that sets it.
1926 We do, however, allow I2 to follow a CC0-setting insn if that insn
1927 is passed as I1; in that case it will be deleted also.
1928 We also allow combining in this case if all the insns are adjacent
1929 because that would leave the two CC0 insns adjacent as well.
1930 It would be more logical to test whether CC0 occurs inside I1 or I2,
1931 but that would be much slower, and this ought to be equivalent. */
1933 p = prev_nonnote_insn (insn);
1934 if (p && p != pred && NONJUMP_INSN_P (p) && sets_cc0_p (PATTERN (p))
1939 /* If we get here, we have passed all the tests and the combination is
1948 /* LOC is the location within I3 that contains its pattern or the component
1949 of a PARALLEL of the pattern. We validate that it is valid for combining.
1951 One problem is if I3 modifies its output, as opposed to replacing it
1952 entirely, we can't allow the output to contain I2DEST, I1DEST or I0DEST as
1953 doing so would produce an insn that is not equivalent to the original insns.
1957 (set (reg:DI 101) (reg:DI 100))
1958 (set (subreg:SI (reg:DI 101) 0) <foo>)
1960 This is NOT equivalent to:
1962 (parallel [(set (subreg:SI (reg:DI 100) 0) <foo>)
1963 (set (reg:DI 101) (reg:DI 100))])
1965 Not only does this modify 100 (in which case it might still be valid
1966 if 100 were dead in I2), it sets 101 to the ORIGINAL value of 100.
1968 We can also run into a problem if I2 sets a register that I1
1969 uses and I1 gets directly substituted into I3 (not via I2). In that
1970 case, we would be getting the wrong value of I2DEST into I3, so we
1971 must reject the combination. This case occurs when I2 and I1 both
1972 feed into I3, rather than when I1 feeds into I2, which feeds into I3.
1973 If I1_NOT_IN_SRC is nonzero, it means that finding I1 in the source
1974 of a SET must prevent combination from occurring. The same situation
1975 can occur for I0, in which case I0_NOT_IN_SRC is set.
1977 Before doing the above check, we first try to expand a field assignment
1978 into a set of logical operations.
1980 If PI3_DEST_KILLED is nonzero, it is a pointer to a location in which
1981 we place a register that is both set and used within I3. If more than one
1982 such register is detected, we fail.
1984 Return 1 if the combination is valid, zero otherwise. */
1987 combinable_i3pat (rtx i3, rtx *loc, rtx i2dest, rtx i1dest, rtx i0dest,
1988 int i1_not_in_src, int i0_not_in_src, rtx *pi3dest_killed)
1992 if (GET_CODE (x) == SET)
1995 rtx dest = SET_DEST (set);
1996 rtx src = SET_SRC (set);
1997 rtx inner_dest = dest;
2000 while (GET_CODE (inner_dest) == STRICT_LOW_PART
2001 || GET_CODE (inner_dest) == SUBREG
2002 || GET_CODE (inner_dest) == ZERO_EXTRACT)
2003 inner_dest = XEXP (inner_dest, 0);
2005 /* Check for the case where I3 modifies its output, as discussed
2006 above. We don't want to prevent pseudos from being combined
2007 into the address of a MEM, so only prevent the combination if
2008 i1 or i2 set the same MEM. */
2009 if ((inner_dest != dest &&
2010 (!MEM_P (inner_dest)
2011 || rtx_equal_p (i2dest, inner_dest)
2012 || (i1dest && rtx_equal_p (i1dest, inner_dest))
2013 || (i0dest && rtx_equal_p (i0dest, inner_dest)))
2014 && (reg_overlap_mentioned_p (i2dest, inner_dest)
2015 || (i1dest && reg_overlap_mentioned_p (i1dest, inner_dest))
2016 || (i0dest && reg_overlap_mentioned_p (i0dest, inner_dest))))
2018 /* This is the same test done in can_combine_p except we can't test
2019 all_adjacent; we don't have to, since this instruction will stay
2020 in place, thus we are not considering increasing the lifetime of
2023 Also, if this insn sets a function argument, combining it with
2024 something that might need a spill could clobber a previous
2025 function argument; the all_adjacent test in can_combine_p also
2026 checks this; here, we do a more specific test for this case. */
2028 || (REG_P (inner_dest)
2029 && REGNO (inner_dest) < FIRST_PSEUDO_REGISTER
2030 && (! HARD_REGNO_MODE_OK (REGNO (inner_dest),
2031 GET_MODE (inner_dest))))
2032 || (i1_not_in_src && reg_overlap_mentioned_p (i1dest, src))
2033 || (i0_not_in_src && reg_overlap_mentioned_p (i0dest, src)))
2036 /* If DEST is used in I3, it is being killed in this insn, so
2037 record that for later. We have to consider paradoxical
2038 subregs here, since they kill the whole register, but we
2039 ignore partial subregs, STRICT_LOW_PART, etc.
2040 Never add REG_DEAD notes for the FRAME_POINTER_REGNUM or the
2041 STACK_POINTER_REGNUM, since these are always considered to be
2042 live. Similarly for ARG_POINTER_REGNUM if it is fixed. */
2044 if (GET_CODE (subdest) == SUBREG
2045 && (GET_MODE_SIZE (GET_MODE (subdest))
2046 >= GET_MODE_SIZE (GET_MODE (SUBREG_REG (subdest)))))
2047 subdest = SUBREG_REG (subdest);
2050 && reg_referenced_p (subdest, PATTERN (i3))
2051 && REGNO (subdest) != FRAME_POINTER_REGNUM
2052 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
2053 && REGNO (subdest) != HARD_FRAME_POINTER_REGNUM
2055 #if ARG_POINTER_REGNUM != FRAME_POINTER_REGNUM
2056 && (REGNO (subdest) != ARG_POINTER_REGNUM
2057 || ! fixed_regs [REGNO (subdest)])
2059 && REGNO (subdest) != STACK_POINTER_REGNUM)
2061 if (*pi3dest_killed)
2064 *pi3dest_killed = subdest;
2068 else if (GET_CODE (x) == PARALLEL)
2072 for (i = 0; i < XVECLEN (x, 0); i++)
2073 if (! combinable_i3pat (i3, &XVECEXP (x, 0, i), i2dest, i1dest, i0dest,
2074 i1_not_in_src, i0_not_in_src, pi3dest_killed))
2081 /* Return 1 if X is an arithmetic expression that contains a multiplication
2082 and division. We don't count multiplications by powers of two here. */
2085 contains_muldiv (rtx x)
2087 switch (GET_CODE (x))
2089 case MOD: case DIV: case UMOD: case UDIV:
2093 return ! (CONST_INT_P (XEXP (x, 1))
2094 && exact_log2 (INTVAL (XEXP (x, 1))) >= 0);
2097 return contains_muldiv (XEXP (x, 0))
2098 || contains_muldiv (XEXP (x, 1));
2101 return contains_muldiv (XEXP (x, 0));
2107 /* Determine whether INSN can be used in a combination. Return nonzero if
2108 not. This is used in try_combine to detect early some cases where we
2109 can't perform combinations. */
2112 cant_combine_insn_p (rtx insn)
2117 /* If this isn't really an insn, we can't do anything.
2118 This can occur when flow deletes an insn that it has merged into an
2119 auto-increment address. */
2120 if (! INSN_P (insn))
2123 /* Never combine loads and stores involving hard regs that are likely
2124 to be spilled. The register allocator can usually handle such
2125 reg-reg moves by tying. If we allow the combiner to make
2126 substitutions of likely-spilled regs, reload might die.
2127 As an exception, we allow combinations involving fixed regs; these are
2128 not available to the register allocator so there's no risk involved. */
2130 set = single_set (insn);
2133 src = SET_SRC (set);
2134 dest = SET_DEST (set);
2135 if (GET_CODE (src) == SUBREG)
2136 src = SUBREG_REG (src);
2137 if (GET_CODE (dest) == SUBREG)
2138 dest = SUBREG_REG (dest);
2139 if (REG_P (src) && REG_P (dest)
2140 && ((REGNO (src) < FIRST_PSEUDO_REGISTER
2141 && ! fixed_regs[REGNO (src)]
2142 && CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (REGNO (src))))
2143 || (REGNO (dest) < FIRST_PSEUDO_REGISTER
2144 && ! fixed_regs[REGNO (dest)]
2145 && CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (REGNO (dest))))))
2151 struct likely_spilled_retval_info
2153 unsigned regno, nregs;
2157 /* Called via note_stores by likely_spilled_retval_p. Remove from info->mask
2158 hard registers that are known to be written to / clobbered in full. */
2160 likely_spilled_retval_1 (rtx x, const_rtx set, void *data)
2162 struct likely_spilled_retval_info *const info =
2163 (struct likely_spilled_retval_info *) data;
2164 unsigned regno, nregs;
2167 if (!REG_P (XEXP (set, 0)))
2170 if (regno >= info->regno + info->nregs)
2172 nregs = hard_regno_nregs[regno][GET_MODE (x)];
2173 if (regno + nregs <= info->regno)
2175 new_mask = (2U << (nregs - 1)) - 1;
2176 if (regno < info->regno)
2177 new_mask >>= info->regno - regno;
2179 new_mask <<= regno - info->regno;
2180 info->mask &= ~new_mask;
2183 /* Return nonzero iff part of the return value is live during INSN, and
2184 it is likely spilled. This can happen when more than one insn is needed
2185 to copy the return value, e.g. when we consider to combine into the
2186 second copy insn for a complex value. */
2189 likely_spilled_retval_p (rtx insn)
2191 rtx use = BB_END (this_basic_block);
2193 unsigned regno, nregs;
2194 /* We assume here that no machine mode needs more than
2195 32 hard registers when the value overlaps with a register
2196 for which TARGET_FUNCTION_VALUE_REGNO_P is true. */
2198 struct likely_spilled_retval_info info;
2200 if (!NONJUMP_INSN_P (use) || GET_CODE (PATTERN (use)) != USE || insn == use)
2202 reg = XEXP (PATTERN (use), 0);
2203 if (!REG_P (reg) || !targetm.calls.function_value_regno_p (REGNO (reg)))
2205 regno = REGNO (reg);
2206 nregs = hard_regno_nregs[regno][GET_MODE (reg)];
2209 mask = (2U << (nregs - 1)) - 1;
2211 /* Disregard parts of the return value that are set later. */
2215 for (p = PREV_INSN (use); info.mask && p != insn; p = PREV_INSN (p))
2217 note_stores (PATTERN (p), likely_spilled_retval_1, &info);
2220 /* Check if any of the (probably) live return value registers is
2225 if ((mask & 1 << nregs)
2226 && CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (regno + nregs)))
2232 /* Adjust INSN after we made a change to its destination.
2234 Changing the destination can invalidate notes that say something about
2235 the results of the insn and a LOG_LINK pointing to the insn. */
2238 adjust_for_new_dest (rtx insn)
2240 /* For notes, be conservative and simply remove them. */
2241 remove_reg_equal_equiv_notes (insn);
2243 /* The new insn will have a destination that was previously the destination
2244 of an insn just above it. Call distribute_links to make a LOG_LINK from
2245 the next use of that destination. */
2246 distribute_links (gen_rtx_INSN_LIST (VOIDmode, insn, NULL_RTX));
2248 df_insn_rescan (insn);
2251 /* Return TRUE if combine can reuse reg X in mode MODE.
2252 ADDED_SETS is nonzero if the original set is still required. */
2254 can_change_dest_mode (rtx x, int added_sets, enum machine_mode mode)
2262 /* Allow hard registers if the new mode is legal, and occupies no more
2263 registers than the old mode. */
2264 if (regno < FIRST_PSEUDO_REGISTER)
2265 return (HARD_REGNO_MODE_OK (regno, mode)
2266 && (hard_regno_nregs[regno][GET_MODE (x)]
2267 >= hard_regno_nregs[regno][mode]));
2269 /* Or a pseudo that is only used once. */
2270 return (REG_N_SETS (regno) == 1 && !added_sets
2271 && !REG_USERVAR_P (x));
2275 /* Check whether X, the destination of a set, refers to part of
2276 the register specified by REG. */
2279 reg_subword_p (rtx x, rtx reg)
2281 /* Check that reg is an integer mode register. */
2282 if (!REG_P (reg) || GET_MODE_CLASS (GET_MODE (reg)) != MODE_INT)
2285 if (GET_CODE (x) == STRICT_LOW_PART
2286 || GET_CODE (x) == ZERO_EXTRACT)
2289 return GET_CODE (x) == SUBREG
2290 && SUBREG_REG (x) == reg
2291 && GET_MODE_CLASS (GET_MODE (x)) == MODE_INT;
2295 /* Replace auto-increment addressing modes with explicit operations to
2296 access the same addresses without modifying the corresponding
2297 registers. If AFTER holds, SRC is meant to be reused after the
2298 side effect, otherwise it is to be reused before that. */
2301 cleanup_auto_inc_dec (rtx src, bool after, enum machine_mode mem_mode)
2304 const RTX_CODE code = GET_CODE (x);
2320 /* SCRATCH must be shared because they represent distinct values. */
2323 if (REG_P (XEXP (x, 0)) && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER)
2328 if (shared_const_p (x))
2333 mem_mode = GET_MODE (x);
2340 gcc_assert (mem_mode != VOIDmode && mem_mode != BLKmode);
2341 if (after == (code == PRE_INC || code == PRE_DEC))
2342 x = cleanup_auto_inc_dec (XEXP (x, 0), after, mem_mode);
2344 x = gen_rtx_PLUS (GET_MODE (x),
2345 cleanup_auto_inc_dec (XEXP (x, 0), after, mem_mode),
2346 GEN_INT ((code == PRE_INC || code == POST_INC)
2347 ? GET_MODE_SIZE (mem_mode)
2348 : -GET_MODE_SIZE (mem_mode)));
2353 if (after == (code == PRE_MODIFY))
2357 return cleanup_auto_inc_dec (x, after, mem_mode);
2363 /* Copy the various flags, fields, and other information. We assume
2364 that all fields need copying, and then clear the fields that should
2365 not be copied. That is the sensible default behavior, and forces
2366 us to explicitly document why we are *not* copying a flag. */
2367 x = shallow_copy_rtx (x);
2369 /* We do not copy the USED flag, which is used as a mark bit during
2370 walks over the RTL. */
2371 RTX_FLAG (x, used) = 0;
2373 /* We do not copy FRAME_RELATED for INSNs. */
2375 RTX_FLAG (x, frame_related) = 0;
2377 fmt = GET_RTX_FORMAT (code);
2378 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
2380 XEXP (x, i) = cleanup_auto_inc_dec (XEXP (x, i), after, mem_mode);
2381 else if (fmt[i] == 'E' || fmt[i] == 'V')
2384 XVEC (x, i) = rtvec_alloc (XVECLEN (x, i));
2385 for (j = 0; j < XVECLEN (x, i); j++)
2387 = cleanup_auto_inc_dec (XVECEXP (src, i, j), after, mem_mode);
2394 /* Auxiliary data structure for propagate_for_debug_stmt. */
2396 struct rtx_subst_pair
2403 /* DATA points to an rtx_subst_pair. Return the value that should be
2407 propagate_for_debug_subst (rtx from, const_rtx old_rtx, void *data)
2409 struct rtx_subst_pair *pair = (struct rtx_subst_pair *)data;
2411 if (!rtx_equal_p (from, old_rtx))
2413 if (!pair->adjusted)
2415 pair->adjusted = true;
2417 pair->to = cleanup_auto_inc_dec (pair->to, pair->after, VOIDmode);
2419 pair->to = copy_rtx (pair->to);
2421 pair->to = make_compound_operation (pair->to, SET);
2424 return copy_rtx (pair->to);
2427 /* Replace occurrences of DEST with SRC in DEBUG_INSNs between INSN
2428 and LAST. If MOVE holds, debug insns must also be moved past
2432 propagate_for_debug (rtx insn, rtx last, rtx dest, rtx src, bool move)
2434 rtx next, move_pos = move ? last : NULL_RTX, loc;
2436 struct rtx_subst_pair p;
2441 next = NEXT_INSN (insn);
2442 while (next != last)
2445 next = NEXT_INSN (insn);
2446 if (DEBUG_INSN_P (insn))
2448 loc = simplify_replace_fn_rtx (INSN_VAR_LOCATION_LOC (insn),
2449 dest, propagate_for_debug_subst, &p);
2450 if (loc == INSN_VAR_LOCATION_LOC (insn))
2452 INSN_VAR_LOCATION_LOC (insn) = loc;
2456 PREV_INSN (insn) = NEXT_INSN (insn) = NULL_RTX;
2457 move_pos = emit_debug_insn_after (insn, move_pos);
2460 df_insn_rescan (insn);
2465 /* Delete the unconditional jump INSN and adjust the CFG correspondingly.
2466 Note that the INSN should be deleted *after* removing dead edges, so
2467 that the kept edge is the fallthrough edge for a (set (pc) (pc))
2468 but not for a (set (pc) (label_ref FOO)). */
2471 update_cfg_for_uncondjump (rtx insn)
2473 basic_block bb = BLOCK_FOR_INSN (insn);
2474 bool at_end = (BB_END (bb) == insn);
2477 purge_dead_edges (bb);
2480 if (at_end && EDGE_COUNT (bb->succs) == 1)
2481 single_succ_edge (bb)->flags |= EDGE_FALLTHRU;
2484 /* Try to combine the insns I0, I1 and I2 into I3.
2485 Here I0, I1 and I2 appear earlier than I3.
2486 I0 and I1 can be zero; then we combine just I2 into I3, or I1 and I2 into
2489 If we are combining more than two insns and the resulting insn is not
2490 recognized, try splitting it into two insns. If that happens, I2 and I3
2491 are retained and I1/I0 are pseudo-deleted by turning them into a NOTE.
2492 Otherwise, I0, I1 and I2 are pseudo-deleted.
2494 Return 0 if the combination does not work. Then nothing is changed.
2495 If we did the combination, return the insn at which combine should
2498 Set NEW_DIRECT_JUMP_P to a nonzero value if try_combine creates a
2499 new direct jump instruction. */
2502 try_combine (rtx i3, rtx i2, rtx i1, rtx i0, int *new_direct_jump_p)
2504 /* New patterns for I3 and I2, respectively. */
2505 rtx newpat, newi2pat = 0;
2506 rtvec newpat_vec_with_clobbers = 0;
2507 int substed_i2 = 0, substed_i1 = 0, substed_i0 = 0;
2508 /* Indicates need to preserve SET in I0, I1 or I2 in I3 if it is not
2510 int added_sets_0, added_sets_1, added_sets_2;
2511 /* Total number of SETs to put into I3. */
2513 /* Nonzero if I2's or I1's body now appears in I3. */
2514 int i2_is_used = 0, i1_is_used = 0;
2515 /* INSN_CODEs for new I3, new I2, and user of condition code. */
2516 int insn_code_number, i2_code_number = 0, other_code_number = 0;
2517 /* Contains I3 if the destination of I3 is used in its source, which means
2518 that the old life of I3 is being killed. If that usage is placed into
2519 I2 and not in I3, a REG_DEAD note must be made. */
2520 rtx i3dest_killed = 0;
2521 /* SET_DEST and SET_SRC of I2, I1 and I0. */
2522 rtx i2dest = 0, i2src = 0, i1dest = 0, i1src = 0, i0dest = 0, i0src = 0;
2523 /* Set if I2DEST was reused as a scratch register. */
2524 bool i2scratch = false;
2525 /* The PATTERNs of I0, I1, and I2, or a copy of them in certain cases. */
2526 rtx i0pat = 0, i1pat = 0, i2pat = 0;
2527 /* Indicates if I2DEST or I1DEST is in I2SRC or I1_SRC. */
2528 int i2dest_in_i2src = 0, i1dest_in_i1src = 0, i2dest_in_i1src = 0;
2529 int i0dest_in_i0src = 0, i1dest_in_i0src = 0, i2dest_in_i0src = 0;
2530 int i2dest_killed = 0, i1dest_killed = 0, i0dest_killed = 0;
2531 int i1_feeds_i2_n = 0, i0_feeds_i2_n = 0, i0_feeds_i1_n = 0;
2532 /* Notes that must be added to REG_NOTES in I3 and I2. */
2533 rtx new_i3_notes, new_i2_notes;
2534 /* Notes that we substituted I3 into I2 instead of the normal case. */
2535 int i3_subst_into_i2 = 0;
2536 /* Notes that I1, I2 or I3 is a MULT operation. */
2539 int changed_i3_dest = 0;
2545 rtx new_other_notes;
2548 /* Only try four-insn combinations when there's high likelihood of
2549 success. Look for simple insns, such as loads of constants or
2550 binary operations involving a constant. */
2557 if (!flag_expensive_optimizations)
2560 for (i = 0; i < 4; i++)
2562 rtx insn = i == 0 ? i0 : i == 1 ? i1 : i == 2 ? i2 : i3;
2563 rtx set = single_set (insn);
2567 src = SET_SRC (set);
2568 if (CONSTANT_P (src))
2573 else if (BINARY_P (src) && CONSTANT_P (XEXP (src, 1)))
2575 else if (GET_CODE (src) == ASHIFT || GET_CODE (src) == ASHIFTRT
2576 || GET_CODE (src) == LSHIFTRT)
2579 if (ngood < 2 && nshift < 2)
2583 /* Exit early if one of the insns involved can't be used for
2585 if (cant_combine_insn_p (i3)
2586 || cant_combine_insn_p (i2)
2587 || (i1 && cant_combine_insn_p (i1))
2588 || (i0 && cant_combine_insn_p (i0))
2589 || likely_spilled_retval_p (i3))
2593 undobuf.other_insn = 0;
2595 /* Reset the hard register usage information. */
2596 CLEAR_HARD_REG_SET (newpat_used_regs);
2598 if (dump_file && (dump_flags & TDF_DETAILS))
2601 fprintf (dump_file, "\nTrying %d, %d, %d -> %d:\n",
2602 INSN_UID (i0), INSN_UID (i1), INSN_UID (i2), INSN_UID (i3));
2604 fprintf (dump_file, "\nTrying %d, %d -> %d:\n",
2605 INSN_UID (i1), INSN_UID (i2), INSN_UID (i3));
2607 fprintf (dump_file, "\nTrying %d -> %d:\n",
2608 INSN_UID (i2), INSN_UID (i3));
2611 /* If multiple insns feed into one of I2 or I3, they can be in any
2612 order. To simplify the code below, reorder them in sequence. */
2613 if (i0 && DF_INSN_LUID (i0) > DF_INSN_LUID (i2))
2614 temp = i2, i2 = i0, i0 = temp;
2615 if (i0 && DF_INSN_LUID (i0) > DF_INSN_LUID (i1))
2616 temp = i1, i1 = i0, i0 = temp;
2617 if (i1 && DF_INSN_LUID (i1) > DF_INSN_LUID (i2))
2618 temp = i1, i1 = i2, i2 = temp;
2620 added_links_insn = 0;
2622 /* First check for one important special-case that the code below will
2623 not handle. Namely, the case where I1 is zero, I2 is a PARALLEL
2624 and I3 is a SET whose SET_SRC is a SET_DEST in I2. In that case,
2625 we may be able to replace that destination with the destination of I3.
2626 This occurs in the common code where we compute both a quotient and
2627 remainder into a structure, in which case we want to do the computation
2628 directly into the structure to avoid register-register copies.
2630 Note that this case handles both multiple sets in I2 and also
2631 cases where I2 has a number of CLOBBER or PARALLELs.
2633 We make very conservative checks below and only try to handle the
2634 most common cases of this. For example, we only handle the case
2635 where I2 and I3 are adjacent to avoid making difficult register
2638 if (i1 == 0 && NONJUMP_INSN_P (i3) && GET_CODE (PATTERN (i3)) == SET
2639 && REG_P (SET_SRC (PATTERN (i3)))
2640 && REGNO (SET_SRC (PATTERN (i3))) >= FIRST_PSEUDO_REGISTER
2641 && find_reg_note (i3, REG_DEAD, SET_SRC (PATTERN (i3)))
2642 && GET_CODE (PATTERN (i2)) == PARALLEL
2643 && ! side_effects_p (SET_DEST (PATTERN (i3)))
2644 /* If the dest of I3 is a ZERO_EXTRACT or STRICT_LOW_PART, the code
2645 below would need to check what is inside (and reg_overlap_mentioned_p
2646 doesn't support those codes anyway). Don't allow those destinations;
2647 the resulting insn isn't likely to be recognized anyway. */
2648 && GET_CODE (SET_DEST (PATTERN (i3))) != ZERO_EXTRACT
2649 && GET_CODE (SET_DEST (PATTERN (i3))) != STRICT_LOW_PART
2650 && ! reg_overlap_mentioned_p (SET_SRC (PATTERN (i3)),
2651 SET_DEST (PATTERN (i3)))
2652 && next_active_insn (i2) == i3)
2654 rtx p2 = PATTERN (i2);
2656 /* Make sure that the destination of I3,
2657 which we are going to substitute into one output of I2,
2658 is not used within another output of I2. We must avoid making this:
2659 (parallel [(set (mem (reg 69)) ...)
2660 (set (reg 69) ...)])
2661 which is not well-defined as to order of actions.
2662 (Besides, reload can't handle output reloads for this.)
2664 The problem can also happen if the dest of I3 is a memory ref,
2665 if another dest in I2 is an indirect memory ref. */
2666 for (i = 0; i < XVECLEN (p2, 0); i++)
2667 if ((GET_CODE (XVECEXP (p2, 0, i)) == SET
2668 || GET_CODE (XVECEXP (p2, 0, i)) == CLOBBER)
2669 && reg_overlap_mentioned_p (SET_DEST (PATTERN (i3)),
2670 SET_DEST (XVECEXP (p2, 0, i))))
2673 if (i == XVECLEN (p2, 0))
2674 for (i = 0; i < XVECLEN (p2, 0); i++)
2675 if ((GET_CODE (XVECEXP (p2, 0, i)) == SET
2676 || GET_CODE (XVECEXP (p2, 0, i)) == CLOBBER)
2677 && SET_DEST (XVECEXP (p2, 0, i)) == SET_SRC (PATTERN (i3)))
2682 subst_low_luid = DF_INSN_LUID (i2);
2684 added_sets_2 = added_sets_1 = added_sets_0 = 0;
2685 i2src = SET_DEST (PATTERN (i3));
2686 i2dest = SET_SRC (PATTERN (i3));
2687 i2dest_killed = dead_or_set_p (i2, i2dest);
2689 /* Replace the dest in I2 with our dest and make the resulting
2690 insn the new pattern for I3. Then skip to where we
2691 validate the pattern. Everything was set up above. */
2692 SUBST (SET_DEST (XVECEXP (p2, 0, i)),
2693 SET_DEST (PATTERN (i3)));
2696 i3_subst_into_i2 = 1;
2697 goto validate_replacement;
2701 /* If I2 is setting a pseudo to a constant and I3 is setting some
2702 sub-part of it to another constant, merge them by making a new
2705 && (temp = single_set (i2)) != 0
2706 && (CONST_INT_P (SET_SRC (temp))
2707 || GET_CODE (SET_SRC (temp)) == CONST_DOUBLE)
2708 && GET_CODE (PATTERN (i3)) == SET
2709 && (CONST_INT_P (SET_SRC (PATTERN (i3)))
2710 || GET_CODE (SET_SRC (PATTERN (i3))) == CONST_DOUBLE)
2711 && reg_subword_p (SET_DEST (PATTERN (i3)), SET_DEST (temp)))
2713 rtx dest = SET_DEST (PATTERN (i3));
2717 if (GET_CODE (dest) == ZERO_EXTRACT)
2719 if (CONST_INT_P (XEXP (dest, 1))
2720 && CONST_INT_P (XEXP (dest, 2)))
2722 width = INTVAL (XEXP (dest, 1));
2723 offset = INTVAL (XEXP (dest, 2));
2724 dest = XEXP (dest, 0);
2725 if (BITS_BIG_ENDIAN)
2726 offset = GET_MODE_BITSIZE (GET_MODE (dest)) - width - offset;
2731 if (GET_CODE (dest) == STRICT_LOW_PART)
2732 dest = XEXP (dest, 0);
2733 width = GET_MODE_BITSIZE (GET_MODE (dest));
2739 /* If this is the low part, we're done. */
2740 if (subreg_lowpart_p (dest))
2742 /* Handle the case where inner is twice the size of outer. */
2743 else if (GET_MODE_BITSIZE (GET_MODE (SET_DEST (temp)))
2744 == 2 * GET_MODE_BITSIZE (GET_MODE (dest)))
2745 offset += GET_MODE_BITSIZE (GET_MODE (dest));
2746 /* Otherwise give up for now. */
2752 && (GET_MODE_BITSIZE (GET_MODE (SET_DEST (temp)))
2753 <= HOST_BITS_PER_DOUBLE_INT))
2756 rtx inner = SET_SRC (PATTERN (i3));
2757 rtx outer = SET_SRC (temp);
2759 o = rtx_to_double_int (outer);
2760 i = rtx_to_double_int (inner);
2762 m = double_int_mask (width);
2763 i = double_int_and (i, m);
2764 m = double_int_lshift (m, offset, HOST_BITS_PER_DOUBLE_INT, false);
2765 i = double_int_lshift (i, offset, HOST_BITS_PER_DOUBLE_INT, false);
2766 o = double_int_ior (double_int_and_not (o, m), i);
2770 subst_low_luid = DF_INSN_LUID (i2);
2771 added_sets_2 = added_sets_1 = added_sets_0 = 0;
2772 i2dest = SET_DEST (temp);
2773 i2dest_killed = dead_or_set_p (i2, i2dest);
2775 /* Replace the source in I2 with the new constant and make the
2776 resulting insn the new pattern for I3. Then skip to where we
2777 validate the pattern. Everything was set up above. */
2778 SUBST (SET_SRC (temp),
2779 immed_double_int_const (o, GET_MODE (SET_DEST (temp))));
2781 newpat = PATTERN (i2);
2783 /* The dest of I3 has been replaced with the dest of I2. */
2784 changed_i3_dest = 1;
2785 goto validate_replacement;
2790 /* If we have no I1 and I2 looks like:
2791 (parallel [(set (reg:CC X) (compare:CC OP (const_int 0)))
2793 make up a dummy I1 that is
2796 (set (reg:CC X) (compare:CC Y (const_int 0)))
2798 (We can ignore any trailing CLOBBERs.)
2800 This undoes a previous combination and allows us to match a branch-and-
2803 if (i1 == 0 && GET_CODE (PATTERN (i2)) == PARALLEL
2804 && XVECLEN (PATTERN (i2), 0) >= 2
2805 && GET_CODE (XVECEXP (PATTERN (i2), 0, 0)) == SET
2806 && (GET_MODE_CLASS (GET_MODE (SET_DEST (XVECEXP (PATTERN (i2), 0, 0))))
2808 && GET_CODE (SET_SRC (XVECEXP (PATTERN (i2), 0, 0))) == COMPARE
2809 && XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 1) == const0_rtx
2810 && GET_CODE (XVECEXP (PATTERN (i2), 0, 1)) == SET
2811 && REG_P (SET_DEST (XVECEXP (PATTERN (i2), 0, 1)))
2812 && rtx_equal_p (XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 0),
2813 SET_SRC (XVECEXP (PATTERN (i2), 0, 1))))
2815 for (i = XVECLEN (PATTERN (i2), 0) - 1; i >= 2; i--)
2816 if (GET_CODE (XVECEXP (PATTERN (i2), 0, i)) != CLOBBER)
2821 /* We make I1 with the same INSN_UID as I2. This gives it
2822 the same DF_INSN_LUID for value tracking. Our fake I1 will
2823 never appear in the insn stream so giving it the same INSN_UID
2824 as I2 will not cause a problem. */
2826 i1 = gen_rtx_INSN (VOIDmode, INSN_UID (i2), NULL_RTX, i2,
2827 BLOCK_FOR_INSN (i2), XVECEXP (PATTERN (i2), 0, 1),
2828 INSN_LOCATOR (i2), -1, NULL_RTX);
2830 SUBST (PATTERN (i2), XVECEXP (PATTERN (i2), 0, 0));
2831 SUBST (XEXP (SET_SRC (PATTERN (i2)), 0),
2832 SET_DEST (PATTERN (i1)));
2837 /* Verify that I2 and I1 are valid for combining. */
2838 if (! can_combine_p (i2, i3, i0, i1, NULL_RTX, NULL_RTX, &i2dest, &i2src)
2839 || (i1 && ! can_combine_p (i1, i3, i0, NULL_RTX, i2, NULL_RTX,
2841 || (i0 && ! can_combine_p (i0, i3, NULL_RTX, NULL_RTX, i1, i2,
2848 /* Record whether I2DEST is used in I2SRC and similarly for the other
2849 cases. Knowing this will help in register status updating below. */
2850 i2dest_in_i2src = reg_overlap_mentioned_p (i2dest, i2src);
2851 i1dest_in_i1src = i1 && reg_overlap_mentioned_p (i1dest, i1src);
2852 i2dest_in_i1src = i1 && reg_overlap_mentioned_p (i2dest, i1src);
2853 i0dest_in_i0src = i0 && reg_overlap_mentioned_p (i0dest, i0src);
2854 i1dest_in_i0src = i0 && reg_overlap_mentioned_p (i1dest, i0src);
2855 i2dest_in_i0src = i0 && reg_overlap_mentioned_p (i2dest, i0src);
2856 i2dest_killed = dead_or_set_p (i2, i2dest);
2857 i1dest_killed = i1 && dead_or_set_p (i1, i1dest);
2858 i0dest_killed = i0 && dead_or_set_p (i0, i0dest);
2860 /* For the earlier insns, determine which of the subsequent ones they
2862 i1_feeds_i2_n = i1 && insn_a_feeds_b (i1, i2);
2863 i0_feeds_i1_n = i0 && insn_a_feeds_b (i0, i1);
2864 i0_feeds_i2_n = (i0 && (!i0_feeds_i1_n ? insn_a_feeds_b (i0, i2)
2865 : (!dead_or_set_p (i1, i0dest)
2866 && reg_overlap_mentioned_p (i0dest, i2src))));
2868 /* Ensure that I3's pattern can be the destination of combines. */
2869 if (! combinable_i3pat (i3, &PATTERN (i3), i2dest, i1dest, i0dest,
2870 i1 && i2dest_in_i1src && !i1_feeds_i2_n,
2871 i0 && ((i2dest_in_i0src && !i0_feeds_i2_n)
2872 || (i1dest_in_i0src && !i0_feeds_i1_n)),
2879 /* See if any of the insns is a MULT operation. Unless one is, we will
2880 reject a combination that is, since it must be slower. Be conservative
2882 if (GET_CODE (i2src) == MULT
2883 || (i1 != 0 && GET_CODE (i1src) == MULT)
2884 || (i0 != 0 && GET_CODE (i0src) == MULT)
2885 || (GET_CODE (PATTERN (i3)) == SET
2886 && GET_CODE (SET_SRC (PATTERN (i3))) == MULT))
2889 /* If I3 has an inc, then give up if I1 or I2 uses the reg that is inc'd.
2890 We used to do this EXCEPT in one case: I3 has a post-inc in an
2891 output operand. However, that exception can give rise to insns like
2893 which is a famous insn on the PDP-11 where the value of r3 used as the
2894 source was model-dependent. Avoid this sort of thing. */
2897 if (!(GET_CODE (PATTERN (i3)) == SET
2898 && REG_P (SET_SRC (PATTERN (i3)))
2899 && MEM_P (SET_DEST (PATTERN (i3)))
2900 && (GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_INC
2901 || GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_DEC)))
2902 /* It's not the exception. */
2905 for (link = REG_NOTES (i3); link; link = XEXP (link, 1))
2906 if (REG_NOTE_KIND (link) == REG_INC
2907 && (reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i2))
2909 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i1)))))
2916 /* See if the SETs in I1 or I2 need to be kept around in the merged
2917 instruction: whenever the value set there is still needed past I3.
2918 For the SETs in I2, this is easy: we see if I2DEST dies or is set in I3.
2920 For the SET in I1, we have two cases: If I1 and I2 independently
2921 feed into I3, the set in I1 needs to be kept around if I1DEST dies
2922 or is set in I3. Otherwise (if I1 feeds I2 which feeds I3), the set
2923 in I1 needs to be kept around unless I1DEST dies or is set in either
2924 I2 or I3. The same consideration applies to I0. */
2926 added_sets_2 = !dead_or_set_p (i3, i2dest);
2929 added_sets_1 = !(dead_or_set_p (i3, i1dest)
2930 || (i1_feeds_i2_n && dead_or_set_p (i2, i1dest)));
2935 added_sets_0 = !(dead_or_set_p (i3, i0dest)
2936 || (i0_feeds_i2_n && dead_or_set_p (i2, i0dest))
2937 || (i0_feeds_i1_n && dead_or_set_p (i1, i0dest)));
2941 /* If the set in I2 needs to be kept around, we must make a copy of
2942 PATTERN (I2), so that when we substitute I1SRC for I1DEST in
2943 PATTERN (I2), we are only substituting for the original I1DEST, not into
2944 an already-substituted copy. This also prevents making self-referential
2945 rtx. If I2 is a PARALLEL, we just need the piece that assigns I2SRC to
2950 if (GET_CODE (PATTERN (i2)) == PARALLEL)
2951 i2pat = gen_rtx_SET (VOIDmode, i2dest, copy_rtx (i2src));
2953 i2pat = copy_rtx (PATTERN (i2));
2958 if (GET_CODE (PATTERN (i1)) == PARALLEL)
2959 i1pat = gen_rtx_SET (VOIDmode, i1dest, copy_rtx (i1src));
2961 i1pat = copy_rtx (PATTERN (i1));
2966 if (GET_CODE (PATTERN (i0)) == PARALLEL)
2967 i0pat = gen_rtx_SET (VOIDmode, i0dest, copy_rtx (i0src));
2969 i0pat = copy_rtx (PATTERN (i0));
2974 /* Substitute in the latest insn for the regs set by the earlier ones. */
2976 maxreg = max_reg_num ();
2981 /* Many machines that don't use CC0 have insns that can both perform an
2982 arithmetic operation and set the condition code. These operations will
2983 be represented as a PARALLEL with the first element of the vector
2984 being a COMPARE of an arithmetic operation with the constant zero.
2985 The second element of the vector will set some pseudo to the result
2986 of the same arithmetic operation. If we simplify the COMPARE, we won't
2987 match such a pattern and so will generate an extra insn. Here we test
2988 for this case, where both the comparison and the operation result are
2989 needed, and make the PARALLEL by just replacing I2DEST in I3SRC with
2990 I2SRC. Later we will make the PARALLEL that contains I2. */
2992 if (i1 == 0 && added_sets_2 && GET_CODE (PATTERN (i3)) == SET
2993 && GET_CODE (SET_SRC (PATTERN (i3))) == COMPARE
2994 && XEXP (SET_SRC (PATTERN (i3)), 1) == const0_rtx
2995 && rtx_equal_p (XEXP (SET_SRC (PATTERN (i3)), 0), i2dest))
2997 #ifdef SELECT_CC_MODE
2999 enum machine_mode compare_mode;
3002 newpat = PATTERN (i3);
3003 SUBST (XEXP (SET_SRC (newpat), 0), i2src);
3007 #ifdef SELECT_CC_MODE
3008 /* See if a COMPARE with the operand we substituted in should be done
3009 with the mode that is currently being used. If not, do the same
3010 processing we do in `subst' for a SET; namely, if the destination
3011 is used only once, try to replace it with a register of the proper
3012 mode and also replace the COMPARE. */
3013 if (undobuf.other_insn == 0
3014 && (cc_use = find_single_use (SET_DEST (newpat), i3,
3015 &undobuf.other_insn))
3016 && ((compare_mode = SELECT_CC_MODE (GET_CODE (*cc_use),
3018 != GET_MODE (SET_DEST (newpat))))
3020 if (can_change_dest_mode (SET_DEST (newpat), added_sets_2,
3023 unsigned int regno = REGNO (SET_DEST (newpat));
3026 if (regno < FIRST_PSEUDO_REGISTER)
3027 new_dest = gen_rtx_REG (compare_mode, regno);
3030 SUBST_MODE (regno_reg_rtx[regno], compare_mode);
3031 new_dest = regno_reg_rtx[regno];
3034 SUBST (SET_DEST (newpat), new_dest);
3035 SUBST (XEXP (*cc_use, 0), new_dest);
3036 SUBST (SET_SRC (newpat),
3037 gen_rtx_COMPARE (compare_mode, i2src, const0_rtx));
3040 undobuf.other_insn = 0;
3047 /* It is possible that the source of I2 or I1 may be performing
3048 an unneeded operation, such as a ZERO_EXTEND of something
3049 that is known to have the high part zero. Handle that case
3050 by letting subst look at the innermost one of them.
3052 Another way to do this would be to have a function that tries
3053 to simplify a single insn instead of merging two or more
3054 insns. We don't do this because of the potential of infinite
3055 loops and because of the potential extra memory required.
3056 However, doing it the way we are is a bit of a kludge and
3057 doesn't catch all cases.
3059 But only do this if -fexpensive-optimizations since it slows
3060 things down and doesn't usually win.
3062 This is not done in the COMPARE case above because the
3063 unmodified I2PAT is used in the PARALLEL and so a pattern
3064 with a modified I2SRC would not match. */
3066 if (flag_expensive_optimizations)
3068 /* Pass pc_rtx so no substitutions are done, just
3072 subst_low_luid = DF_INSN_LUID (i1);
3073 i1src = subst (i1src, pc_rtx, pc_rtx, 0, 0);
3077 subst_low_luid = DF_INSN_LUID (i2);
3078 i2src = subst (i2src, pc_rtx, pc_rtx, 0, 0);
3082 n_occurrences = 0; /* `subst' counts here */
3084 /* If I1 feeds into I2 and I1DEST is in I1SRC, we need to make a
3085 unique copy of I2SRC each time we substitute it to avoid
3086 self-referential rtl. */
3088 subst_low_luid = DF_INSN_LUID (i2);
3089 newpat = subst (PATTERN (i3), i2dest, i2src, 0,
3090 ((i1_feeds_i2_n && i1dest_in_i1src)
3091 || (i0_feeds_i2_n && i0dest_in_i0src)));
3094 /* Record whether i2's body now appears within i3's body. */
3095 i2_is_used = n_occurrences;
3098 /* If we already got a failure, don't try to do more. Otherwise,
3099 try to substitute in I1 if we have it. */
3101 if (i1 && GET_CODE (newpat) != CLOBBER)
3103 /* Check that an autoincrement side-effect on I1 has not been lost.
3104 This happens if I1DEST is mentioned in I2 and dies there, and
3105 has disappeared from the new pattern. */
3106 if ((FIND_REG_INC_NOTE (i1, NULL_RTX) != 0
3108 && dead_or_set_p (i2, i1dest)
3109 && !reg_overlap_mentioned_p (i1dest, newpat))
3110 /* Before we can do this substitution, we must redo the test done
3111 above (see detailed comments there) that ensures that I1DEST
3112 isn't mentioned in any SETs in NEWPAT that are field assignments. */
3113 || !combinable_i3pat (NULL_RTX, &newpat, i1dest, NULL_RTX, NULL_RTX,
3121 subst_low_luid = DF_INSN_LUID (i1);
3122 newpat = subst (newpat, i1dest, i1src, 0,
3123 i0_feeds_i1_n && i0dest_in_i0src);
3125 i1_is_used = n_occurrences;
3127 if (i0 && GET_CODE (newpat) != CLOBBER)
3129 if ((FIND_REG_INC_NOTE (i0, NULL_RTX) != 0
3130 && ((i0_feeds_i2_n && dead_or_set_p (i2, i0dest))
3131 || (i0_feeds_i1_n && dead_or_set_p (i1, i0dest)))
3132 && !reg_overlap_mentioned_p (i0dest, newpat))
3133 || !combinable_i3pat (NULL_RTX, &newpat, i0dest, NULL_RTX, NULL_RTX,
3141 subst_low_luid = DF_INSN_LUID (i1);
3142 newpat = subst (newpat, i0dest, i0src, 0,
3143 i0_feeds_i1_n && i0dest_in_i0src);
3147 /* Fail if an autoincrement side-effect has been duplicated. Be careful
3148 to count all the ways that I2SRC and I1SRC can be used. */
3149 if ((FIND_REG_INC_NOTE (i2, NULL_RTX) != 0
3150 && i2_is_used + added_sets_2 > 1)
3151 || (i1 != 0 && FIND_REG_INC_NOTE (i1, NULL_RTX) != 0
3152 && (i1_is_used + added_sets_1 + (added_sets_2 && i1_feeds_i2_n)
3154 || (i0 != 0 && FIND_REG_INC_NOTE (i0, NULL_RTX) != 0
3155 && (n_occurrences + added_sets_0
3156 + (added_sets_1 && i0_feeds_i1_n)
3157 + (added_sets_2 && i0_feeds_i2_n)
3159 /* Fail if we tried to make a new register. */
3160 || max_reg_num () != maxreg
3161 /* Fail if we couldn't do something and have a CLOBBER. */
3162 || GET_CODE (newpat) == CLOBBER
3163 /* Fail if this new pattern is a MULT and we didn't have one before
3164 at the outer level. */
3165 || (GET_CODE (newpat) == SET && GET_CODE (SET_SRC (newpat)) == MULT
3172 /* If the actions of the earlier insns must be kept
3173 in addition to substituting them into the latest one,
3174 we must make a new PARALLEL for the latest insn
3175 to hold additional the SETs. */
3177 if (added_sets_0 || added_sets_1 || added_sets_2)
3179 int extra_sets = added_sets_0 + added_sets_1 + added_sets_2;
3182 if (GET_CODE (newpat) == PARALLEL)
3184 rtvec old = XVEC (newpat, 0);
3185 total_sets = XVECLEN (newpat, 0) + extra_sets;
3186 newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (total_sets));
3187 memcpy (XVEC (newpat, 0)->elem, &old->elem[0],
3188 sizeof (old->elem[0]) * old->num_elem);
3193 total_sets = 1 + extra_sets;
3194 newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (total_sets));
3195 XVECEXP (newpat, 0, 0) = old;
3199 XVECEXP (newpat, 0, --total_sets) = i0pat;
3205 t = subst (t, i0dest, i0src, 0, 0);
3207 XVECEXP (newpat, 0, --total_sets) = t;
3213 t = subst (t, i0dest, i0src, 0, 0);
3215 t = subst (t, i1dest, i1src, 0, 0);
3217 XVECEXP (newpat, 0, --total_sets) = t;
3221 validate_replacement:
3223 /* Note which hard regs this insn has as inputs. */
3224 mark_used_regs_combine (newpat);
3226 /* If recog_for_combine fails, it strips existing clobbers. If we'll
3227 consider splitting this pattern, we might need these clobbers. */
3228 if (i1 && GET_CODE (newpat) == PARALLEL
3229 && GET_CODE (XVECEXP (newpat, 0, XVECLEN (newpat, 0) - 1)) == CLOBBER)
3231 int len = XVECLEN (newpat, 0);
3233 newpat_vec_with_clobbers = rtvec_alloc (len);
3234 for (i = 0; i < len; i++)
3235 RTVEC_ELT (newpat_vec_with_clobbers, i) = XVECEXP (newpat, 0, i);
3238 /* Is the result of combination a valid instruction? */
3239 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
3241 /* If the result isn't valid, see if it is a PARALLEL of two SETs where
3242 the second SET's destination is a register that is unused and isn't
3243 marked as an instruction that might trap in an EH region. In that case,
3244 we just need the first SET. This can occur when simplifying a divmod
3245 insn. We *must* test for this case here because the code below that
3246 splits two independent SETs doesn't handle this case correctly when it
3247 updates the register status.
3249 It's pointless doing this if we originally had two sets, one from
3250 i3, and one from i2. Combining then splitting the parallel results
3251 in the original i2 again plus an invalid insn (which we delete).
3252 The net effect is only to move instructions around, which makes
3253 debug info less accurate.
3255 Also check the case where the first SET's destination is unused.
3256 That would not cause incorrect code, but does cause an unneeded
3259 if (insn_code_number < 0
3260 && !(added_sets_2 && i1 == 0)
3261 && GET_CODE (newpat) == PARALLEL
3262 && XVECLEN (newpat, 0) == 2
3263 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
3264 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
3265 && asm_noperands (newpat) < 0)
3267 rtx set0 = XVECEXP (newpat, 0, 0);
3268 rtx set1 = XVECEXP (newpat, 0, 1);
3270 if (((REG_P (SET_DEST (set1))
3271 && find_reg_note (i3, REG_UNUSED, SET_DEST (set1)))
3272 || (GET_CODE (SET_DEST (set1)) == SUBREG
3273 && find_reg_note (i3, REG_UNUSED, SUBREG_REG (SET_DEST (set1)))))
3274 && insn_nothrow_p (i3)
3275 && !side_effects_p (SET_SRC (set1)))
3278 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
3281 else if (((REG_P (SET_DEST (set0))
3282 && find_reg_note (i3, REG_UNUSED, SET_DEST (set0)))
3283 || (GET_CODE (SET_DEST (set0)) == SUBREG
3284 && find_reg_note (i3, REG_UNUSED,
3285 SUBREG_REG (SET_DEST (set0)))))
3286 && insn_nothrow_p (i3)
3287 && !side_effects_p (SET_SRC (set0)))
3290 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
3292 if (insn_code_number >= 0)
3293 changed_i3_dest = 1;
3297 /* If we were combining three insns and the result is a simple SET
3298 with no ASM_OPERANDS that wasn't recognized, try to split it into two
3299 insns. There are two ways to do this. It can be split using a
3300 machine-specific method (like when you have an addition of a large
3301 constant) or by combine in the function find_split_point. */
3303 if (i1 && insn_code_number < 0 && GET_CODE (newpat) == SET
3304 && asm_noperands (newpat) < 0)
3306 rtx parallel, m_split, *split;
3308 /* See if the MD file can split NEWPAT. If it can't, see if letting it
3309 use I2DEST as a scratch register will help. In the latter case,
3310 convert I2DEST to the mode of the source of NEWPAT if we can. */
3312 m_split = combine_split_insns (newpat, i3);
3314 /* We can only use I2DEST as a scratch reg if it doesn't overlap any
3315 inputs of NEWPAT. */
3317 /* ??? If I2DEST is not safe, and I1DEST exists, then it would be
3318 possible to try that as a scratch reg. This would require adding
3319 more code to make it work though. */
3321 if (m_split == 0 && ! reg_overlap_mentioned_p (i2dest, newpat))
3323 enum machine_mode new_mode = GET_MODE (SET_DEST (newpat));
3325 /* First try to split using the original register as a
3326 scratch register. */
3327 parallel = gen_rtx_PARALLEL (VOIDmode,
3328 gen_rtvec (2, newpat,
3329 gen_rtx_CLOBBER (VOIDmode,
3331 m_split = combine_split_insns (parallel, i3);
3333 /* If that didn't work, try changing the mode of I2DEST if
3336 && new_mode != GET_MODE (i2dest)
3337 && new_mode != VOIDmode
3338 && can_change_dest_mode (i2dest, added_sets_2, new_mode))
3340 enum machine_mode old_mode = GET_MODE (i2dest);
3343 if (REGNO (i2dest) < FIRST_PSEUDO_REGISTER)
3344 ni2dest = gen_rtx_REG (new_mode, REGNO (i2dest));
3347 SUBST_MODE (regno_reg_rtx[REGNO (i2dest)], new_mode);
3348 ni2dest = regno_reg_rtx[REGNO (i2dest)];
3351 parallel = (gen_rtx_PARALLEL
3353 gen_rtvec (2, newpat,
3354 gen_rtx_CLOBBER (VOIDmode,
3356 m_split = combine_split_insns (parallel, i3);
3359 && REGNO (i2dest) >= FIRST_PSEUDO_REGISTER)
3363 adjust_reg_mode (regno_reg_rtx[REGNO (i2dest)], old_mode);
3364 buf = undobuf.undos;
3365 undobuf.undos = buf->next;
3366 buf->next = undobuf.frees;
3367 undobuf.frees = buf;
3371 i2scratch = m_split != 0;
3374 /* If recog_for_combine has discarded clobbers, try to use them
3375 again for the split. */
3376 if (m_split == 0 && newpat_vec_with_clobbers)
3378 parallel = gen_rtx_PARALLEL (VOIDmode, newpat_vec_with_clobbers);
3379 m_split = combine_split_insns (parallel, i3);
3382 if (m_split && NEXT_INSN (m_split) == NULL_RTX)
3384 m_split = PATTERN (m_split);
3385 insn_code_number = recog_for_combine (&m_split, i3, &new_i3_notes);
3386 if (insn_code_number >= 0)
3389 else if (m_split && NEXT_INSN (NEXT_INSN (m_split)) == NULL_RTX
3390 && (next_real_insn (i2) == i3
3391 || ! use_crosses_set_p (PATTERN (m_split), DF_INSN_LUID (i2))))
3394 rtx newi3pat = PATTERN (NEXT_INSN (m_split));
3395 newi2pat = PATTERN (m_split);
3397 i3set = single_set (NEXT_INSN (m_split));
3398 i2set = single_set (m_split);
3400 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
3402 /* If I2 or I3 has multiple SETs, we won't know how to track
3403 register status, so don't use these insns. If I2's destination
3404 is used between I2 and I3, we also can't use these insns. */
3406 if (i2_code_number >= 0 && i2set && i3set
3407 && (next_real_insn (i2) == i3
3408 || ! reg_used_between_p (SET_DEST (i2set), i2, i3)))
3409 insn_code_number = recog_for_combine (&newi3pat, i3,
3411 if (insn_code_number >= 0)
3414 /* It is possible that both insns now set the destination of I3.
3415 If so, we must show an extra use of it. */
3417 if (insn_code_number >= 0)
3419 rtx new_i3_dest = SET_DEST (i3set);
3420 rtx new_i2_dest = SET_DEST (i2set);
3422 while (GET_CODE (new_i3_dest) == ZERO_EXTRACT
3423 || GET_CODE (new_i3_dest) == STRICT_LOW_PART
3424 || GET_CODE (new_i3_dest) == SUBREG)
3425 new_i3_dest = XEXP (new_i3_dest, 0);
3427 while (GET_CODE (new_i2_dest) == ZERO_EXTRACT
3428 || GET_CODE (new_i2_dest) == STRICT_LOW_PART
3429 || GET_CODE (new_i2_dest) == SUBREG)
3430 new_i2_dest = XEXP (new_i2_dest, 0);
3432 if (REG_P (new_i3_dest)
3433 && REG_P (new_i2_dest)
3434 && REGNO (new_i3_dest) == REGNO (new_i2_dest))
3435 INC_REG_N_SETS (REGNO (new_i2_dest), 1);
3439 /* If we can split it and use I2DEST, go ahead and see if that
3440 helps things be recognized. Verify that none of the registers
3441 are set between I2 and I3. */
3442 if (insn_code_number < 0
3443 && (split = find_split_point (&newpat, i3, false)) != 0
3447 /* We need I2DEST in the proper mode. If it is a hard register
3448 or the only use of a pseudo, we can change its mode.
3449 Make sure we don't change a hard register to have a mode that
3450 isn't valid for it, or change the number of registers. */
3451 && (GET_MODE (*split) == GET_MODE (i2dest)
3452 || GET_MODE (*split) == VOIDmode
3453 || can_change_dest_mode (i2dest, added_sets_2,
3455 && (next_real_insn (i2) == i3
3456 || ! use_crosses_set_p (*split, DF_INSN_LUID (i2)))
3457 /* We can't overwrite I2DEST if its value is still used by
3459 && ! reg_referenced_p (i2dest, newpat))
3461 rtx newdest = i2dest;
3462 enum rtx_code split_code = GET_CODE (*split);
3463 enum machine_mode split_mode = GET_MODE (*split);
3464 bool subst_done = false;
3465 newi2pat = NULL_RTX;
3469 /* *SPLIT may be part of I2SRC, so make sure we have the
3470 original expression around for later debug processing.
3471 We should not need I2SRC any more in other cases. */
3472 if (MAY_HAVE_DEBUG_INSNS)
3473 i2src = copy_rtx (i2src);
3477 /* Get NEWDEST as a register in the proper mode. We have already
3478 validated that we can do this. */
3479 if (GET_MODE (i2dest) != split_mode && split_mode != VOIDmode)
3481 if (REGNO (i2dest) < FIRST_PSEUDO_REGISTER)
3482 newdest = gen_rtx_REG (split_mode, REGNO (i2dest));
3485 SUBST_MODE (regno_reg_rtx[REGNO (i2dest)], split_mode);
3486 newdest = regno_reg_rtx[REGNO (i2dest)];
3490 /* If *SPLIT is a (mult FOO (const_int pow2)), convert it to
3491 an ASHIFT. This can occur if it was inside a PLUS and hence
3492 appeared to be a memory address. This is a kludge. */
3493 if (split_code == MULT
3494 && CONST_INT_P (XEXP (*split, 1))
3495 && INTVAL (XEXP (*split, 1)) > 0
3496 && (i = exact_log2 (INTVAL (XEXP (*split, 1)))) >= 0)
3498 SUBST (*split, gen_rtx_ASHIFT (split_mode,
3499 XEXP (*split, 0), GEN_INT (i)));
3500 /* Update split_code because we may not have a multiply
3502 split_code = GET_CODE (*split);
3505 #ifdef INSN_SCHEDULING
3506 /* If *SPLIT is a paradoxical SUBREG, when we split it, it should
3507 be written as a ZERO_EXTEND. */
3508 if (split_code == SUBREG && MEM_P (SUBREG_REG (*split)))
3510 #ifdef LOAD_EXTEND_OP
3511 /* Or as a SIGN_EXTEND if LOAD_EXTEND_OP says that that's
3512 what it really is. */
3513 if (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (*split)))
3515 SUBST (*split, gen_rtx_SIGN_EXTEND (split_mode,
3516 SUBREG_REG (*split)));
3519 SUBST (*split, gen_rtx_ZERO_EXTEND (split_mode,
3520 SUBREG_REG (*split)));
3524 /* Attempt to split binary operators using arithmetic identities. */
3525 if (BINARY_P (SET_SRC (newpat))
3526 && split_mode == GET_MODE (SET_SRC (newpat))
3527 && ! side_effects_p (SET_SRC (newpat)))
3529 rtx setsrc = SET_SRC (newpat);
3530 enum machine_mode mode = GET_MODE (setsrc);
3531 enum rtx_code code = GET_CODE (setsrc);
3532 rtx src_op0 = XEXP (setsrc, 0);
3533 rtx src_op1 = XEXP (setsrc, 1);
3535 /* Split "X = Y op Y" as "Z = Y; X = Z op Z". */
3536 if (rtx_equal_p (src_op0, src_op1))
3538 newi2pat = gen_rtx_SET (VOIDmode, newdest, src_op0);
3539 SUBST (XEXP (setsrc, 0), newdest);
3540 SUBST (XEXP (setsrc, 1), newdest);
3543 /* Split "((P op Q) op R) op S" where op is PLUS or MULT. */
3544 else if ((code == PLUS || code == MULT)
3545 && GET_CODE (src_op0) == code
3546 && GET_CODE (XEXP (src_op0, 0)) == code
3547 && (INTEGRAL_MODE_P (mode)
3548 || (FLOAT_MODE_P (mode)
3549 && flag_unsafe_math_optimizations)))
3551 rtx p = XEXP (XEXP (src_op0, 0), 0);
3552 rtx q = XEXP (XEXP (src_op0, 0), 1);
3553 rtx r = XEXP (src_op0, 1);
3556 /* Split both "((X op Y) op X) op Y" and
3557 "((X op Y) op Y) op X" as "T op T" where T is
3559 if ((rtx_equal_p (p,r) && rtx_equal_p (q,s))
3560 || (rtx_equal_p (p,s) && rtx_equal_p (q,r)))
3562 newi2pat = gen_rtx_SET (VOIDmode, newdest,
3564 SUBST (XEXP (setsrc, 0), newdest);
3565 SUBST (XEXP (setsrc, 1), newdest);
3568 /* Split "((X op X) op Y) op Y)" as "T op T" where
3570 else if (rtx_equal_p (p,q) && rtx_equal_p (r,s))
3572 rtx tmp = simplify_gen_binary (code, mode, p, r);
3573 newi2pat = gen_rtx_SET (VOIDmode, newdest, tmp);
3574 SUBST (XEXP (setsrc, 0), newdest);
3575 SUBST (XEXP (setsrc, 1), newdest);
3583 newi2pat = gen_rtx_SET (VOIDmode, newdest, *split);
3584 SUBST (*split, newdest);
3587 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
3589 /* recog_for_combine might have added CLOBBERs to newi2pat.
3590 Make sure NEWPAT does not depend on the clobbered regs. */
3591 if (GET_CODE (newi2pat) == PARALLEL)
3592 for (i = XVECLEN (newi2pat, 0) - 1; i >= 0; i--)
3593 if (GET_CODE (XVECEXP (newi2pat, 0, i)) == CLOBBER)
3595 rtx reg = XEXP (XVECEXP (newi2pat, 0, i), 0);
3596 if (reg_overlap_mentioned_p (reg, newpat))
3603 /* If the split point was a MULT and we didn't have one before,
3604 don't use one now. */
3605 if (i2_code_number >= 0 && ! (split_code == MULT && ! have_mult))
3606 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
3610 /* Check for a case where we loaded from memory in a narrow mode and
3611 then sign extended it, but we need both registers. In that case,
3612 we have a PARALLEL with both loads from the same memory location.
3613 We can split this into a load from memory followed by a register-register
3614 copy. This saves at least one insn, more if register allocation can
3617 We cannot do this if the destination of the first assignment is a
3618 condition code register or cc0. We eliminate this case by making sure
3619 the SET_DEST and SET_SRC have the same mode.
3621 We cannot do this if the destination of the second assignment is
3622 a register that we have already assumed is zero-extended. Similarly
3623 for a SUBREG of such a register. */
3625 else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0
3626 && GET_CODE (newpat) == PARALLEL
3627 && XVECLEN (newpat, 0) == 2
3628 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
3629 && GET_CODE (SET_SRC (XVECEXP (newpat, 0, 0))) == SIGN_EXTEND
3630 && (GET_MODE (SET_DEST (XVECEXP (newpat, 0, 0)))
3631 == GET_MODE (SET_SRC (XVECEXP (newpat, 0, 0))))
3632 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
3633 && rtx_equal_p (SET_SRC (XVECEXP (newpat, 0, 1)),
3634 XEXP (SET_SRC (XVECEXP (newpat, 0, 0)), 0))
3635 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)),
3637 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
3638 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
3639 && ! (temp = SET_DEST (XVECEXP (newpat, 0, 1)),
3641 && VEC_index (reg_stat_type, reg_stat,
3642 REGNO (temp))->nonzero_bits != 0
3643 && GET_MODE_BITSIZE (GET_MODE (temp)) < BITS_PER_WORD
3644 && GET_MODE_BITSIZE (GET_MODE (temp)) < HOST_BITS_PER_INT
3645 && (VEC_index (reg_stat_type, reg_stat,
3646 REGNO (temp))->nonzero_bits
3647 != GET_MODE_MASK (word_mode))))
3648 && ! (GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) == SUBREG
3649 && (temp = SUBREG_REG (SET_DEST (XVECEXP (newpat, 0, 1))),
3651 && VEC_index (reg_stat_type, reg_stat,
3652 REGNO (temp))->nonzero_bits != 0
3653 && GET_MODE_BITSIZE (GET_MODE (temp)) < BITS_PER_WORD
3654 && GET_MODE_BITSIZE (GET_MODE (temp)) < HOST_BITS_PER_INT
3655 && (VEC_index (reg_stat_type, reg_stat,
3656 REGNO (temp))->nonzero_bits
3657 != GET_MODE_MASK (word_mode)))))
3658 && ! reg_overlap_mentioned_p (SET_DEST (XVECEXP (newpat, 0, 1)),
3659 SET_SRC (XVECEXP (newpat, 0, 1)))
3660 && ! find_reg_note (i3, REG_UNUSED,
3661 SET_DEST (XVECEXP (newpat, 0, 0))))
3665 newi2pat = XVECEXP (newpat, 0, 0);
3666 ni2dest = SET_DEST (XVECEXP (newpat, 0, 0));
3667 newpat = XVECEXP (newpat, 0, 1);
3668 SUBST (SET_SRC (newpat),
3669 gen_lowpart (GET_MODE (SET_SRC (newpat)), ni2dest));
3670 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
3672 if (i2_code_number >= 0)
3673 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
3675 if (insn_code_number >= 0)
3679 /* Similarly, check for a case where we have a PARALLEL of two independent
3680 SETs but we started with three insns. In this case, we can do the sets
3681 as two separate insns. This case occurs when some SET allows two
3682 other insns to combine, but the destination of that SET is still live. */
3684 else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0
3685 && GET_CODE (newpat) == PARALLEL
3686 && XVECLEN (newpat, 0) == 2
3687 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
3688 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != ZERO_EXTRACT
3689 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != STRICT_LOW_PART
3690 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
3691 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
3692 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
3693 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)),
3695 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 1)),
3696 XVECEXP (newpat, 0, 0))
3697 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 0)),
3698 XVECEXP (newpat, 0, 1))
3699 && ! (contains_muldiv (SET_SRC (XVECEXP (newpat, 0, 0)))
3700 && contains_muldiv (SET_SRC (XVECEXP (newpat, 0, 1))))
3702 /* We cannot split the parallel into two sets if both sets
3704 && ! (reg_referenced_p (cc0_rtx, XVECEXP (newpat, 0, 0))
3705 && reg_referenced_p (cc0_rtx, XVECEXP (newpat, 0, 1)))
3709 /* Normally, it doesn't matter which of the two is done first,
3710 but it does if one references cc0. In that case, it has to
3713 if (reg_referenced_p (cc0_rtx, XVECEXP (newpat, 0, 0)))
3715 newi2pat = XVECEXP (newpat, 0, 0);
3716 newpat = XVECEXP (newpat, 0, 1);
3721 newi2pat = XVECEXP (newpat, 0, 1);
3722 newpat = XVECEXP (newpat, 0, 0);
3725 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
3727 if (i2_code_number >= 0)
3728 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
3731 /* If it still isn't recognized, fail and change things back the way they
3733 if ((insn_code_number < 0
3734 /* Is the result a reasonable ASM_OPERANDS? */
3735 && (! check_asm_operands (newpat) || added_sets_1 || added_sets_2)))
3741 /* If we had to change another insn, make sure it is valid also. */
3742 if (undobuf.other_insn)
3744 CLEAR_HARD_REG_SET (newpat_used_regs);
3746 other_pat = PATTERN (undobuf.other_insn);
3747 other_code_number = recog_for_combine (&other_pat, undobuf.other_insn,
3750 if (other_code_number < 0 && ! check_asm_operands (other_pat))
3758 /* If I2 is the CC0 setter and I3 is the CC0 user then check whether
3759 they are adjacent to each other or not. */
3761 rtx p = prev_nonnote_insn (i3);
3762 if (p && p != i2 && NONJUMP_INSN_P (p) && newi2pat
3763 && sets_cc0_p (newi2pat))
3771 /* Only allow this combination if insn_rtx_costs reports that the
3772 replacement instructions are cheaper than the originals. */
3773 if (!combine_validate_cost (i0, i1, i2, i3, newpat, newi2pat, other_pat))
3779 if (MAY_HAVE_DEBUG_INSNS)
3783 for (undo = undobuf.undos; undo; undo = undo->next)
3784 if (undo->kind == UNDO_MODE)
3786 rtx reg = *undo->where.r;
3787 enum machine_mode new_mode = GET_MODE (reg);
3788 enum machine_mode old_mode = undo->old_contents.m;
3790 /* Temporarily revert mode back. */
3791 adjust_reg_mode (reg, old_mode);
3793 if (reg == i2dest && i2scratch)
3795 /* If we used i2dest as a scratch register with a
3796 different mode, substitute it for the original
3797 i2src while its original mode is temporarily
3798 restored, and then clear i2scratch so that we don't
3799 do it again later. */
3800 propagate_for_debug (i2, i3, reg, i2src, false);
3802 /* Put back the new mode. */
3803 adjust_reg_mode (reg, new_mode);
3807 rtx tempreg = gen_raw_REG (old_mode, REGNO (reg));
3818 last = undobuf.other_insn;
3822 /* We're dealing with a reg that changed mode but not
3823 meaning, so we want to turn it into a subreg for
3824 the new mode. However, because of REG sharing and
3825 because its mode had already changed, we have to do
3826 it in two steps. First, replace any debug uses of
3827 reg, with its original mode temporarily restored,
3828 with this copy we have created; then, replace the
3829 copy with the SUBREG of the original shared reg,
3830 once again changed to the new mode. */
3831 propagate_for_debug (first, last, reg, tempreg, false);
3832 adjust_reg_mode (reg, new_mode);
3833 propagate_for_debug (first, last, tempreg,
3834 lowpart_subreg (old_mode, reg, new_mode),
3840 /* If we will be able to accept this, we have made a
3841 change to the destination of I3. This requires us to
3842 do a few adjustments. */
3844 if (changed_i3_dest)
3846 PATTERN (i3) = newpat;
3847 adjust_for_new_dest (i3);
3850 /* We now know that we can do this combination. Merge the insns and
3851 update the status of registers and LOG_LINKS. */
3853 if (undobuf.other_insn)
3857 PATTERN (undobuf.other_insn) = other_pat;
3859 /* If any of the notes in OTHER_INSN were REG_UNUSED, ensure that they
3860 are still valid. Then add any non-duplicate notes added by
3861 recog_for_combine. */
3862 for (note = REG_NOTES (undobuf.other_insn); note; note = next)
3864 next = XEXP (note, 1);
3866 if (REG_NOTE_KIND (note) == REG_UNUSED
3867 && ! reg_set_p (XEXP (note, 0), PATTERN (undobuf.other_insn)))
3868 remove_note (undobuf.other_insn, note);
3871 distribute_notes (new_other_notes, undobuf.other_insn,
3872 undobuf.other_insn, NULL_RTX, NULL_RTX, NULL_RTX,
3882 /* I3 now uses what used to be its destination and which is now
3883 I2's destination. This requires us to do a few adjustments. */
3884 PATTERN (i3) = newpat;
3885 adjust_for_new_dest (i3);
3887 /* We need a LOG_LINK from I3 to I2. But we used to have one,
3890 However, some later insn might be using I2's dest and have
3891 a LOG_LINK pointing at I3. We must remove this link.
3892 The simplest way to remove the link is to point it at I1,
3893 which we know will be a NOTE. */
3895 /* newi2pat is usually a SET here; however, recog_for_combine might
3896 have added some clobbers. */
3897 if (GET_CODE (newi2pat) == PARALLEL)
3898 ni2dest = SET_DEST (XVECEXP (newi2pat, 0, 0));
3900 ni2dest = SET_DEST (newi2pat);
3902 for (insn = NEXT_INSN (i3);
3903 insn && (this_basic_block->next_bb == EXIT_BLOCK_PTR
3904 || insn != BB_HEAD (this_basic_block->next_bb));
3905 insn = NEXT_INSN (insn))
3907 if (INSN_P (insn) && reg_referenced_p (ni2dest, PATTERN (insn)))
3909 for (link = LOG_LINKS (insn); link;
3910 link = XEXP (link, 1))
3911 if (XEXP (link, 0) == i3)
3912 XEXP (link, 0) = i1;
3920 rtx i3notes, i2notes, i1notes = 0, i0notes = 0;
3921 rtx i3links, i2links, i1links = 0, i0links = 0;
3925 /* Compute which registers we expect to eliminate. newi2pat may be setting
3926 either i3dest or i2dest, so we must check it. Also, i1dest may be the
3927 same as i3dest, in which case newi2pat may be setting i1dest. */
3928 rtx elim_i2 = ((newi2pat && reg_set_p (i2dest, newi2pat))
3929 || i2dest_in_i2src || i2dest_in_i1src || i2dest_in_i0src
3932 rtx elim_i1 = (i1 == 0 || i1dest_in_i1src || i1dest_in_i0src
3933 || (newi2pat && reg_set_p (i1dest, newi2pat))
3936 rtx elim_i0 = (i0 == 0 || i0dest_in_i0src
3937 || (newi2pat && reg_set_p (i0dest, newi2pat))
3941 /* Get the old REG_NOTES and LOG_LINKS from all our insns and
3943 i3notes = REG_NOTES (i3), i3links = LOG_LINKS (i3);
3944 i2notes = REG_NOTES (i2), i2links = LOG_LINKS (i2);
3946 i1notes = REG_NOTES (i1), i1links = LOG_LINKS (i1);
3948 i0notes = REG_NOTES (i0), i0links = LOG_LINKS (i0);
3950 /* Ensure that we do not have something that should not be shared but
3951 occurs multiple times in the new insns. Check this by first
3952 resetting all the `used' flags and then copying anything is shared. */
3954 reset_used_flags (i3notes);
3955 reset_used_flags (i2notes);
3956 reset_used_flags (i1notes);
3957 reset_used_flags (i0notes);
3958 reset_used_flags (newpat);
3959 reset_used_flags (newi2pat);
3960 if (undobuf.other_insn)
3961 reset_used_flags (PATTERN (undobuf.other_insn));
3963 i3notes = copy_rtx_if_shared (i3notes);
3964 i2notes = copy_rtx_if_shared (i2notes);
3965 i1notes = copy_rtx_if_shared (i1notes);
3966 i0notes = copy_rtx_if_shared (i0notes);
3967 newpat = copy_rtx_if_shared (newpat);
3968 newi2pat = copy_rtx_if_shared (newi2pat);
3969 if (undobuf.other_insn)
3970 reset_used_flags (PATTERN (undobuf.other_insn));
3972 INSN_CODE (i3) = insn_code_number;
3973 PATTERN (i3) = newpat;
3975 if (CALL_P (i3) && CALL_INSN_FUNCTION_USAGE (i3))
3977 rtx call_usage = CALL_INSN_FUNCTION_USAGE (i3);
3979 reset_used_flags (call_usage);
3980 call_usage = copy_rtx (call_usage);
3984 /* I2SRC must still be meaningful at this point. Some splitting
3985 operations can invalidate I2SRC, but those operations do not
3988 replace_rtx (call_usage, i2dest, i2src);
3992 replace_rtx (call_usage, i1dest, i1src);
3994 replace_rtx (call_usage, i0dest, i0src);
3996 CALL_INSN_FUNCTION_USAGE (i3) = call_usage;
3999 if (undobuf.other_insn)
4000 INSN_CODE (undobuf.other_insn) = other_code_number;
4002 /* We had one special case above where I2 had more than one set and
4003 we replaced a destination of one of those sets with the destination
4004 of I3. In that case, we have to update LOG_LINKS of insns later
4005 in this basic block. Note that this (expensive) case is rare.
4007 Also, in this case, we must pretend that all REG_NOTEs for I2
4008 actually came from I3, so that REG_UNUSED notes from I2 will be
4009 properly handled. */
4011 if (i3_subst_into_i2)
4013 for (i = 0; i < XVECLEN (PATTERN (i2), 0); i++)
4014 if ((GET_CODE (XVECEXP (PATTERN (i2), 0, i)) == SET
4015 || GET_CODE (XVECEXP (PATTERN (i2), 0, i)) == CLOBBER)
4016 && REG_P (SET_DEST (XVECEXP (PATTERN (i2), 0, i)))
4017 && SET_DEST (XVECEXP (PATTERN (i2), 0, i)) != i2dest
4018 && ! find_reg_note (i2, REG_UNUSED,
4019 SET_DEST (XVECEXP (PATTERN (i2), 0, i))))
4020 for (temp = NEXT_INSN (i2);
4021 temp && (this_basic_block->next_bb == EXIT_BLOCK_PTR
4022 || BB_HEAD (this_basic_block) != temp);
4023 temp = NEXT_INSN (temp))
4024 if (temp != i3 && INSN_P (temp))
4025 for (link = LOG_LINKS (temp); link; link = XEXP (link, 1))
4026 if (XEXP (link, 0) == i2)
4027 XEXP (link, 0) = i3;
4032 while (XEXP (link, 1))
4033 link = XEXP (link, 1);
4034 XEXP (link, 1) = i2notes;
4048 if (MAY_HAVE_DEBUG_INSNS && i2scratch)
4049 propagate_for_debug (i2, i3, i2dest, i2src, false);
4050 INSN_CODE (i2) = i2_code_number;
4051 PATTERN (i2) = newi2pat;
4055 if (MAY_HAVE_DEBUG_INSNS && i2src)
4056 propagate_for_debug (i2, i3, i2dest, i2src, i3_subst_into_i2);
4057 SET_INSN_DELETED (i2);
4064 if (MAY_HAVE_DEBUG_INSNS)
4065 propagate_for_debug (i1, i3, i1dest, i1src, false);
4066 SET_INSN_DELETED (i1);
4073 if (MAY_HAVE_DEBUG_INSNS)
4074 propagate_for_debug (i0, i3, i0dest, i0src, false);
4075 SET_INSN_DELETED (i0);
4078 /* Get death notes for everything that is now used in either I3 or
4079 I2 and used to die in a previous insn. If we built two new
4080 patterns, move from I1 to I2 then I2 to I3 so that we get the
4081 proper movement on registers that I2 modifies. */
4084 from_luid = DF_INSN_LUID (i0);
4086 from_luid = DF_INSN_LUID (i1);
4088 from_luid = DF_INSN_LUID (i2);
4090 move_deaths (newi2pat, NULL_RTX, from_luid, i2, &midnotes);
4091 move_deaths (newpat, newi2pat, from_luid, i3, &midnotes);
4093 /* Distribute all the LOG_LINKS and REG_NOTES from I1, I2, and I3. */
4095 distribute_notes (i3notes, i3, i3, newi2pat ? i2 : NULL_RTX,
4096 elim_i2, elim_i1, elim_i0);
4098 distribute_notes (i2notes, i2, i3, newi2pat ? i2 : NULL_RTX,
4099 elim_i2, elim_i1, elim_i0);
4101 distribute_notes (i1notes, i1, i3, newi2pat ? i2 : NULL_RTX,
4102 elim_i2, elim_i1, elim_i0);
4104 distribute_notes (i0notes, i0, i3, newi2pat ? i2 : NULL_RTX,
4105 elim_i2, elim_i1, elim_i0);
4107 distribute_notes (midnotes, NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
4108 elim_i2, elim_i1, elim_i0);
4110 /* Distribute any notes added to I2 or I3 by recog_for_combine. We
4111 know these are REG_UNUSED and want them to go to the desired insn,
4112 so we always pass it as i3. */
4114 if (newi2pat && new_i2_notes)
4115 distribute_notes (new_i2_notes, i2, i2, NULL_RTX, NULL_RTX, NULL_RTX,
4119 distribute_notes (new_i3_notes, i3, i3, NULL_RTX, NULL_RTX, NULL_RTX,
4122 /* If I3DEST was used in I3SRC, it really died in I3. We may need to
4123 put a REG_DEAD note for it somewhere. If NEWI2PAT exists and sets
4124 I3DEST, the death must be somewhere before I2, not I3. If we passed I3
4125 in that case, it might delete I2. Similarly for I2 and I1.
4126 Show an additional death due to the REG_DEAD note we make here. If
4127 we discard it in distribute_notes, we will decrement it again. */
4131 if (newi2pat && reg_set_p (i3dest_killed, newi2pat))
4132 distribute_notes (alloc_reg_note (REG_DEAD, i3dest_killed,
4134 NULL_RTX, i2, NULL_RTX, elim_i2, elim_i1, elim_i0);
4136 distribute_notes (alloc_reg_note (REG_DEAD, i3dest_killed,
4138 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
4139 elim_i2, elim_i1, elim_i0);
4142 if (i2dest_in_i2src)
4144 rtx new_note = alloc_reg_note (REG_DEAD, i2dest, NULL_RTX);
4145 if (newi2pat && reg_set_p (i2dest, newi2pat))
4146 distribute_notes (new_note, NULL_RTX, i2, NULL_RTX, NULL_RTX,
4147 NULL_RTX, NULL_RTX);
4149 distribute_notes (new_note, NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
4150 NULL_RTX, NULL_RTX, NULL_RTX);
4153 if (i1dest_in_i1src)
4155 rtx new_note = alloc_reg_note (REG_DEAD, i1dest, NULL_RTX);
4156 if (newi2pat && reg_set_p (i1dest, newi2pat))
4157 distribute_notes (new_note, NULL_RTX, i2, NULL_RTX, NULL_RTX,
4158 NULL_RTX, NULL_RTX);
4160 distribute_notes (new_note, NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
4161 NULL_RTX, NULL_RTX, NULL_RTX);
4164 if (i0dest_in_i0src)
4166 rtx new_note = alloc_reg_note (REG_DEAD, i0dest, NULL_RTX);
4167 if (newi2pat && reg_set_p (i0dest, newi2pat))
4168 distribute_notes (new_note, NULL_RTX, i2, NULL_RTX, NULL_RTX,
4169 NULL_RTX, NULL_RTX);
4171 distribute_notes (new_note, NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
4172 NULL_RTX, NULL_RTX, NULL_RTX);
4175 distribute_links (i3links);
4176 distribute_links (i2links);
4177 distribute_links (i1links);
4178 distribute_links (i0links);
4183 rtx i2_insn = 0, i2_val = 0, set;
4185 /* The insn that used to set this register doesn't exist, and
4186 this life of the register may not exist either. See if one of
4187 I3's links points to an insn that sets I2DEST. If it does,
4188 that is now the last known value for I2DEST. If we don't update
4189 this and I2 set the register to a value that depended on its old
4190 contents, we will get confused. If this insn is used, thing
4191 will be set correctly in combine_instructions. */
4193 for (link = LOG_LINKS (i3); link; link = XEXP (link, 1))
4194 if ((set = single_set (XEXP (link, 0))) != 0
4195 && rtx_equal_p (i2dest, SET_DEST (set)))
4196 i2_insn = XEXP (link, 0), i2_val = SET_SRC (set);
4198 record_value_for_reg (i2dest, i2_insn, i2_val);
4200 /* If the reg formerly set in I2 died only once and that was in I3,
4201 zero its use count so it won't make `reload' do any work. */
4203 && (newi2pat == 0 || ! reg_mentioned_p (i2dest, newi2pat))
4204 && ! i2dest_in_i2src)
4206 regno = REGNO (i2dest);
4207 INC_REG_N_SETS (regno, -1);
4211 if (i1 && REG_P (i1dest))
4214 rtx i1_insn = 0, i1_val = 0, set;
4216 for (link = LOG_LINKS (i3); link; link = XEXP (link, 1))
4217 if ((set = single_set (XEXP (link, 0))) != 0
4218 && rtx_equal_p (i1dest, SET_DEST (set)))
4219 i1_insn = XEXP (link, 0), i1_val = SET_SRC (set);
4221 record_value_for_reg (i1dest, i1_insn, i1_val);
4223 regno = REGNO (i1dest);
4224 if (! added_sets_1 && ! i1dest_in_i1src)
4225 INC_REG_N_SETS (regno, -1);
4228 if (i0 && REG_P (i0dest))
4231 rtx i0_insn = 0, i0_val = 0, set;
4233 for (link = LOG_LINKS (i3); link; link = XEXP (link, 1))
4234 if ((set = single_set (XEXP (link, 0))) != 0
4235 && rtx_equal_p (i0dest, SET_DEST (set)))
4236 i0_insn = XEXP (link, 0), i0_val = SET_SRC (set);
4238 record_value_for_reg (i0dest, i0_insn, i0_val);
4240 regno = REGNO (i0dest);
4241 if (! added_sets_0 && ! i0dest_in_i0src)
4242 INC_REG_N_SETS (regno, -1);
4245 /* Update reg_stat[].nonzero_bits et al for any changes that may have
4246 been made to this insn. The order of
4247 set_nonzero_bits_and_sign_copies() is important. Because newi2pat
4248 can affect nonzero_bits of newpat */
4250 note_stores (newi2pat, set_nonzero_bits_and_sign_copies, NULL);
4251 note_stores (newpat, set_nonzero_bits_and_sign_copies, NULL);
4254 if (undobuf.other_insn != NULL_RTX)
4258 fprintf (dump_file, "modifying other_insn ");
4259 dump_insn_slim (dump_file, undobuf.other_insn);
4261 df_insn_rescan (undobuf.other_insn);
4264 if (i0 && !(NOTE_P(i0) && (NOTE_KIND (i0) == NOTE_INSN_DELETED)))
4268 fprintf (dump_file, "modifying insn i1 ");
4269 dump_insn_slim (dump_file, i0);
4271 df_insn_rescan (i0);
4274 if (i1 && !(NOTE_P(i1) && (NOTE_KIND (i1) == NOTE_INSN_DELETED)))
4278 fprintf (dump_file, "modifying insn i1 ");
4279 dump_insn_slim (dump_file, i1);
4281 df_insn_rescan (i1);
4284 if (i2 && !(NOTE_P(i2) && (NOTE_KIND (i2) == NOTE_INSN_DELETED)))
4288 fprintf (dump_file, "modifying insn i2 ");
4289 dump_insn_slim (dump_file, i2);
4291 df_insn_rescan (i2);
4294 if (i3 && !(NOTE_P(i3) && (NOTE_KIND (i3) == NOTE_INSN_DELETED)))
4298 fprintf (dump_file, "modifying insn i3 ");
4299 dump_insn_slim (dump_file, i3);
4301 df_insn_rescan (i3);
4304 /* Set new_direct_jump_p if a new return or simple jump instruction
4305 has been created. Adjust the CFG accordingly. */
4307 if (returnjump_p (i3) || any_uncondjump_p (i3))
4309 *new_direct_jump_p = 1;
4310 mark_jump_label (PATTERN (i3), i3, 0);
4311 update_cfg_for_uncondjump (i3);
4314 if (undobuf.other_insn != NULL_RTX
4315 && (returnjump_p (undobuf.other_insn)
4316 || any_uncondjump_p (undobuf.other_insn)))
4318 *new_direct_jump_p = 1;
4319 update_cfg_for_uncondjump (undobuf.other_insn);
4322 /* A noop might also need cleaning up of CFG, if it comes from the
4323 simplification of a jump. */
4324 if (GET_CODE (newpat) == SET
4325 && SET_SRC (newpat) == pc_rtx
4326 && SET_DEST (newpat) == pc_rtx)
4328 *new_direct_jump_p = 1;
4329 update_cfg_for_uncondjump (i3);
4332 combine_successes++;
4335 if (added_links_insn
4336 && (newi2pat == 0 || DF_INSN_LUID (added_links_insn) < DF_INSN_LUID (i2))
4337 && DF_INSN_LUID (added_links_insn) < DF_INSN_LUID (i3))
4338 return added_links_insn;
4340 return newi2pat ? i2 : i3;
4343 /* Undo all the modifications recorded in undobuf. */
4348 struct undo *undo, *next;
4350 for (undo = undobuf.undos; undo; undo = next)
4356 *undo->where.r = undo->old_contents.r;
4359 *undo->where.i = undo->old_contents.i;
4362 adjust_reg_mode (*undo->where.r, undo->old_contents.m);
4368 undo->next = undobuf.frees;
4369 undobuf.frees = undo;
4375 /* We've committed to accepting the changes we made. Move all
4376 of the undos to the free list. */
4381 struct undo *undo, *next;
4383 for (undo = undobuf.undos; undo; undo = next)
4386 undo->next = undobuf.frees;
4387 undobuf.frees = undo;
4392 /* Find the innermost point within the rtx at LOC, possibly LOC itself,
4393 where we have an arithmetic expression and return that point. LOC will
4396 try_combine will call this function to see if an insn can be split into
4400 find_split_point (rtx *loc, rtx insn, bool set_src)
4403 enum rtx_code code = GET_CODE (x);
4405 unsigned HOST_WIDE_INT len = 0;
4406 HOST_WIDE_INT pos = 0;
4408 rtx inner = NULL_RTX;
4410 /* First special-case some codes. */
4414 #ifdef INSN_SCHEDULING
4415 /* If we are making a paradoxical SUBREG invalid, it becomes a split
4417 if (MEM_P (SUBREG_REG (x)))
4420 return find_split_point (&SUBREG_REG (x), insn, false);
4424 /* If we have (mem (const ..)) or (mem (symbol_ref ...)), split it
4425 using LO_SUM and HIGH. */
4426 if (GET_CODE (XEXP (x, 0)) == CONST
4427 || GET_CODE (XEXP (x, 0)) == SYMBOL_REF)
4429 enum machine_mode address_mode
4430 = targetm.addr_space.address_mode (MEM_ADDR_SPACE (x));
4433 gen_rtx_LO_SUM (address_mode,
4434 gen_rtx_HIGH (address_mode, XEXP (x, 0)),
4436 return &XEXP (XEXP (x, 0), 0);
4440 /* If we have a PLUS whose second operand is a constant and the
4441 address is not valid, perhaps will can split it up using
4442 the machine-specific way to split large constants. We use
4443 the first pseudo-reg (one of the virtual regs) as a placeholder;
4444 it will not remain in the result. */
4445 if (GET_CODE (XEXP (x, 0)) == PLUS
4446 && CONST_INT_P (XEXP (XEXP (x, 0), 1))
4447 && ! memory_address_addr_space_p (GET_MODE (x), XEXP (x, 0),
4448 MEM_ADDR_SPACE (x)))
4450 rtx reg = regno_reg_rtx[FIRST_PSEUDO_REGISTER];
4451 rtx seq = combine_split_insns (gen_rtx_SET (VOIDmode, reg,
4455 /* This should have produced two insns, each of which sets our
4456 placeholder. If the source of the second is a valid address,
4457 we can make put both sources together and make a split point
4461 && NEXT_INSN (seq) != NULL_RTX
4462 && NEXT_INSN (NEXT_INSN (seq)) == NULL_RTX
4463 && NONJUMP_INSN_P (seq)
4464 && GET_CODE (PATTERN (seq)) == SET
4465 && SET_DEST (PATTERN (seq)) == reg
4466 && ! reg_mentioned_p (reg,
4467 SET_SRC (PATTERN (seq)))
4468 && NONJUMP_INSN_P (NEXT_INSN (seq))
4469 && GET_CODE (PATTERN (NEXT_INSN (seq))) == SET
4470 && SET_DEST (PATTERN (NEXT_INSN (seq))) == reg
4471 && memory_address_addr_space_p
4472 (GET_MODE (x), SET_SRC (PATTERN (NEXT_INSN (seq))),
4473 MEM_ADDR_SPACE (x)))
4475 rtx src1 = SET_SRC (PATTERN (seq));
4476 rtx src2 = SET_SRC (PATTERN (NEXT_INSN (seq)));
4478 /* Replace the placeholder in SRC2 with SRC1. If we can
4479 find where in SRC2 it was placed, that can become our
4480 split point and we can replace this address with SRC2.
4481 Just try two obvious places. */
4483 src2 = replace_rtx (src2, reg, src1);
4485 if (XEXP (src2, 0) == src1)
4486 split = &XEXP (src2, 0);
4487 else if (GET_RTX_FORMAT (GET_CODE (XEXP (src2, 0)))[0] == 'e'
4488 && XEXP (XEXP (src2, 0), 0) == src1)
4489 split = &XEXP (XEXP (src2, 0), 0);
4493 SUBST (XEXP (x, 0), src2);
4498 /* If that didn't work, perhaps the first operand is complex and
4499 needs to be computed separately, so make a split point there.
4500 This will occur on machines that just support REG + CONST
4501 and have a constant moved through some previous computation. */
4503 else if (!OBJECT_P (XEXP (XEXP (x, 0), 0))
4504 && ! (GET_CODE (XEXP (XEXP (x, 0), 0)) == SUBREG
4505 && OBJECT_P (SUBREG_REG (XEXP (XEXP (x, 0), 0)))))
4506 return &XEXP (XEXP (x, 0), 0);
4509 /* If we have a PLUS whose first operand is complex, try computing it
4510 separately by making a split there. */
4511 if (GET_CODE (XEXP (x, 0)) == PLUS
4512 && ! memory_address_addr_space_p (GET_MODE (x), XEXP (x, 0),
4514 && ! OBJECT_P (XEXP (XEXP (x, 0), 0))
4515 && ! (GET_CODE (XEXP (XEXP (x, 0), 0)) == SUBREG
4516 && OBJECT_P (SUBREG_REG (XEXP (XEXP (x, 0), 0)))))
4517 return &XEXP (XEXP (x, 0), 0);
4522 /* If SET_DEST is CC0 and SET_SRC is not an operand, a COMPARE, or a
4523 ZERO_EXTRACT, the most likely reason why this doesn't match is that
4524 we need to put the operand into a register. So split at that
4527 if (SET_DEST (x) == cc0_rtx
4528 && GET_CODE (SET_SRC (x)) != COMPARE
4529 && GET_CODE (SET_SRC (x)) != ZERO_EXTRACT
4530 && !OBJECT_P (SET_SRC (x))
4531 && ! (GET_CODE (SET_SRC (x)) == SUBREG
4532 && OBJECT_P (SUBREG_REG (SET_SRC (x)))))
4533 return &SET_SRC (x);
4536 /* See if we can split SET_SRC as it stands. */
4537 split = find_split_point (&SET_SRC (x), insn, true);
4538 if (split && split != &SET_SRC (x))
4541 /* See if we can split SET_DEST as it stands. */
4542 split = find_split_point (&SET_DEST (x), insn, false);
4543 if (split && split != &SET_DEST (x))
4546 /* See if this is a bitfield assignment with everything constant. If
4547 so, this is an IOR of an AND, so split it into that. */
4548 if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
4549 && (GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0)))
4550 <= HOST_BITS_PER_WIDE_INT)
4551 && CONST_INT_P (XEXP (SET_DEST (x), 1))
4552 && CONST_INT_P (XEXP (SET_DEST (x), 2))
4553 && CONST_INT_P (SET_SRC (x))
4554 && ((INTVAL (XEXP (SET_DEST (x), 1))
4555 + INTVAL (XEXP (SET_DEST (x), 2)))
4556 <= GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0))))
4557 && ! side_effects_p (XEXP (SET_DEST (x), 0)))
4559 HOST_WIDE_INT pos = INTVAL (XEXP (SET_DEST (x), 2));
4560 unsigned HOST_WIDE_INT len = INTVAL (XEXP (SET_DEST (x), 1));
4561 unsigned HOST_WIDE_INT src = INTVAL (SET_SRC (x));
4562 rtx dest = XEXP (SET_DEST (x), 0);
4563 enum machine_mode mode = GET_MODE (dest);
4564 unsigned HOST_WIDE_INT mask = ((HOST_WIDE_INT) 1 << len) - 1;
4567 if (BITS_BIG_ENDIAN)
4568 pos = GET_MODE_BITSIZE (mode) - len - pos;
4570 or_mask = gen_int_mode (src << pos, mode);
4573 simplify_gen_binary (IOR, mode, dest, or_mask));
4576 rtx negmask = gen_int_mode (~(mask << pos), mode);
4578 simplify_gen_binary (IOR, mode,
4579 simplify_gen_binary (AND, mode,
4584 SUBST (SET_DEST (x), dest);
4586 split = find_split_point (&SET_SRC (x), insn, true);
4587 if (split && split != &SET_SRC (x))
4591 /* Otherwise, see if this is an operation that we can split into two.
4592 If so, try to split that. */
4593 code = GET_CODE (SET_SRC (x));
4598 /* If we are AND'ing with a large constant that is only a single
4599 bit and the result is only being used in a context where we
4600 need to know if it is zero or nonzero, replace it with a bit
4601 extraction. This will avoid the large constant, which might
4602 have taken more than one insn to make. If the constant were
4603 not a valid argument to the AND but took only one insn to make,
4604 this is no worse, but if it took more than one insn, it will
4607 if (CONST_INT_P (XEXP (SET_SRC (x), 1))
4608 && REG_P (XEXP (SET_SRC (x), 0))
4609 && (pos = exact_log2 (INTVAL (XEXP (SET_SRC (x), 1)))) >= 7
4610 && REG_P (SET_DEST (x))
4611 && (split = find_single_use (SET_DEST (x), insn, (rtx*) 0)) != 0
4612 && (GET_CODE (*split) == EQ || GET_CODE (*split) == NE)
4613 && XEXP (*split, 0) == SET_DEST (x)
4614 && XEXP (*split, 1) == const0_rtx)
4616 rtx extraction = make_extraction (GET_MODE (SET_DEST (x)),
4617 XEXP (SET_SRC (x), 0),
4618 pos, NULL_RTX, 1, 1, 0, 0);
4619 if (extraction != 0)
4621 SUBST (SET_SRC (x), extraction);
4622 return find_split_point (loc, insn, false);
4628 /* If STORE_FLAG_VALUE is -1, this is (NE X 0) and only one bit of X
4629 is known to be on, this can be converted into a NEG of a shift. */
4630 if (STORE_FLAG_VALUE == -1 && XEXP (SET_SRC (x), 1) == const0_rtx
4631 && GET_MODE (SET_SRC (x)) == GET_MODE (XEXP (SET_SRC (x), 0))
4632 && 1 <= (pos = exact_log2
4633 (nonzero_bits (XEXP (SET_SRC (x), 0),
4634 GET_MODE (XEXP (SET_SRC (x), 0))))))
4636 enum machine_mode mode = GET_MODE (XEXP (SET_SRC (x), 0));
4640 gen_rtx_LSHIFTRT (mode,
4641 XEXP (SET_SRC (x), 0),
4644 split = find_split_point (&SET_SRC (x), insn, true);
4645 if (split && split != &SET_SRC (x))
4651 inner = XEXP (SET_SRC (x), 0);
4653 /* We can't optimize if either mode is a partial integer
4654 mode as we don't know how many bits are significant
4656 if (GET_MODE_CLASS (GET_MODE (inner)) == MODE_PARTIAL_INT
4657 || GET_MODE_CLASS (GET_MODE (SET_SRC (x))) == MODE_PARTIAL_INT)
4661 len = GET_MODE_BITSIZE (GET_MODE (inner));
4667 if (CONST_INT_P (XEXP (SET_SRC (x), 1))
4668 && CONST_INT_P (XEXP (SET_SRC (x), 2)))
4670 inner = XEXP (SET_SRC (x), 0);
4671 len = INTVAL (XEXP (SET_SRC (x), 1));
4672 pos = INTVAL (XEXP (SET_SRC (x), 2));
4674 if (BITS_BIG_ENDIAN)
4675 pos = GET_MODE_BITSIZE (GET_MODE (inner)) - len - pos;
4676 unsignedp = (code == ZERO_EXTRACT);
4684 if (len && pos >= 0 && pos + len <= GET_MODE_BITSIZE (GET_MODE (inner)))
4686 enum machine_mode mode = GET_MODE (SET_SRC (x));
4688 /* For unsigned, we have a choice of a shift followed by an
4689 AND or two shifts. Use two shifts for field sizes where the
4690 constant might be too large. We assume here that we can
4691 always at least get 8-bit constants in an AND insn, which is
4692 true for every current RISC. */
4694 if (unsignedp && len <= 8)
4699 (mode, gen_lowpart (mode, inner),
4701 GEN_INT (((HOST_WIDE_INT) 1 << len) - 1)));
4703 split = find_split_point (&SET_SRC (x), insn, true);
4704 if (split && split != &SET_SRC (x))
4711 (unsignedp ? LSHIFTRT : ASHIFTRT, mode,
4712 gen_rtx_ASHIFT (mode,
4713 gen_lowpart (mode, inner),
4714 GEN_INT (GET_MODE_BITSIZE (mode)
4716 GEN_INT (GET_MODE_BITSIZE (mode) - len)));
4718 split = find_split_point (&SET_SRC (x), insn, true);
4719 if (split && split != &SET_SRC (x))
4724 /* See if this is a simple operation with a constant as the second
4725 operand. It might be that this constant is out of range and hence
4726 could be used as a split point. */
4727 if (BINARY_P (SET_SRC (x))
4728 && CONSTANT_P (XEXP (SET_SRC (x), 1))
4729 && (OBJECT_P (XEXP (SET_SRC (x), 0))
4730 || (GET_CODE (XEXP (SET_SRC (x), 0)) == SUBREG
4731 && OBJECT_P (SUBREG_REG (XEXP (SET_SRC (x), 0))))))
4732 return &XEXP (SET_SRC (x), 1);
4734 /* Finally, see if this is a simple operation with its first operand
4735 not in a register. The operation might require this operand in a
4736 register, so return it as a split point. We can always do this
4737 because if the first operand were another operation, we would have
4738 already found it as a split point. */
4739 if ((BINARY_P (SET_SRC (x)) || UNARY_P (SET_SRC (x)))
4740 && ! register_operand (XEXP (SET_SRC (x), 0), VOIDmode))
4741 return &XEXP (SET_SRC (x), 0);
4747 /* We write NOR as (and (not A) (not B)), but if we don't have a NOR,
4748 it is better to write this as (not (ior A B)) so we can split it.
4749 Similarly for IOR. */
4750 if (GET_CODE (XEXP (x, 0)) == NOT && GET_CODE (XEXP (x, 1)) == NOT)
4753 gen_rtx_NOT (GET_MODE (x),
4754 gen_rtx_fmt_ee (code == IOR ? AND : IOR,
4756 XEXP (XEXP (x, 0), 0),
4757 XEXP (XEXP (x, 1), 0))));
4758 return find_split_point (loc, insn, set_src);
4761 /* Many RISC machines have a large set of logical insns. If the
4762 second operand is a NOT, put it first so we will try to split the
4763 other operand first. */
4764 if (GET_CODE (XEXP (x, 1)) == NOT)
4766 rtx tem = XEXP (x, 0);
4767 SUBST (XEXP (x, 0), XEXP (x, 1));
4768 SUBST (XEXP (x, 1), tem);
4774 /* Split at a multiply-accumulate instruction. However if this is
4775 the SET_SRC, we likely do not have such an instruction and it's
4776 worthless to try this split. */
4777 if (!set_src && GET_CODE (XEXP (x, 0)) == MULT)
4784 /* Otherwise, select our actions depending on our rtx class. */
4785 switch (GET_RTX_CLASS (code))
4787 case RTX_BITFIELD_OPS: /* This is ZERO_EXTRACT and SIGN_EXTRACT. */
4789 split = find_split_point (&XEXP (x, 2), insn, false);
4792 /* ... fall through ... */
4794 case RTX_COMM_ARITH:
4796 case RTX_COMM_COMPARE:
4797 split = find_split_point (&XEXP (x, 1), insn, false);
4800 /* ... fall through ... */
4802 /* Some machines have (and (shift ...) ...) insns. If X is not
4803 an AND, but XEXP (X, 0) is, use it as our split point. */
4804 if (GET_CODE (x) != AND && GET_CODE (XEXP (x, 0)) == AND)
4805 return &XEXP (x, 0);
4807 split = find_split_point (&XEXP (x, 0), insn, false);
4813 /* Otherwise, we don't have a split point. */
4818 /* Throughout X, replace FROM with TO, and return the result.
4819 The result is TO if X is FROM;
4820 otherwise the result is X, but its contents may have been modified.
4821 If they were modified, a record was made in undobuf so that
4822 undo_all will (among other things) return X to its original state.
4824 If the number of changes necessary is too much to record to undo,
4825 the excess changes are not made, so the result is invalid.
4826 The changes already made can still be undone.
4827 undobuf.num_undo is incremented for such changes, so by testing that
4828 the caller can tell whether the result is valid.
4830 `n_occurrences' is incremented each time FROM is replaced.
4832 IN_DEST is nonzero if we are processing the SET_DEST of a SET.
4834 UNIQUE_COPY is nonzero if each substitution must be unique. We do this
4835 by copying if `n_occurrences' is nonzero. */
4838 subst (rtx x, rtx from, rtx to, int in_dest, int unique_copy)
4840 enum rtx_code code = GET_CODE (x);
4841 enum machine_mode op0_mode = VOIDmode;
4846 /* Two expressions are equal if they are identical copies of a shared
4847 RTX or if they are both registers with the same register number
4850 #define COMBINE_RTX_EQUAL_P(X,Y) \
4852 || (REG_P (X) && REG_P (Y) \
4853 && REGNO (X) == REGNO (Y) && GET_MODE (X) == GET_MODE (Y)))
4855 if (! in_dest && COMBINE_RTX_EQUAL_P (x, from))
4858 return (unique_copy && n_occurrences > 1 ? copy_rtx (to) : to);
4861 /* If X and FROM are the same register but different modes, they
4862 will not have been seen as equal above. However, the log links code
4863 will make a LOG_LINKS entry for that case. If we do nothing, we
4864 will try to rerecognize our original insn and, when it succeeds,
4865 we will delete the feeding insn, which is incorrect.
4867 So force this insn not to match in this (rare) case. */
4868 if (! in_dest && code == REG && REG_P (from)
4869 && reg_overlap_mentioned_p (x, from))
4870 return gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
4872 /* If this is an object, we are done unless it is a MEM or LO_SUM, both
4873 of which may contain things that can be combined. */
4874 if (code != MEM && code != LO_SUM && OBJECT_P (x))
4877 /* It is possible to have a subexpression appear twice in the insn.
4878 Suppose that FROM is a register that appears within TO.
4879 Then, after that subexpression has been scanned once by `subst',
4880 the second time it is scanned, TO may be found. If we were
4881 to scan TO here, we would find FROM within it and create a
4882 self-referent rtl structure which is completely wrong. */
4883 if (COMBINE_RTX_EQUAL_P (x, to))
4886 /* Parallel asm_operands need special attention because all of the
4887 inputs are shared across the arms. Furthermore, unsharing the
4888 rtl results in recognition failures. Failure to handle this case
4889 specially can result in circular rtl.
4891 Solve this by doing a normal pass across the first entry of the
4892 parallel, and only processing the SET_DESTs of the subsequent
4895 if (code == PARALLEL
4896 && GET_CODE (XVECEXP (x, 0, 0)) == SET
4897 && GET_CODE (SET_SRC (XVECEXP (x, 0, 0))) == ASM_OPERANDS)
4899 new_rtx = subst (XVECEXP (x, 0, 0), from, to, 0, unique_copy);
4901 /* If this substitution failed, this whole thing fails. */
4902 if (GET_CODE (new_rtx) == CLOBBER
4903 && XEXP (new_rtx, 0) == const0_rtx)
4906 SUBST (XVECEXP (x, 0, 0), new_rtx);
4908 for (i = XVECLEN (x, 0) - 1; i >= 1; i--)
4910 rtx dest = SET_DEST (XVECEXP (x, 0, i));
4913 && GET_CODE (dest) != CC0
4914 && GET_CODE (dest) != PC)
4916 new_rtx = subst (dest, from, to, 0, unique_copy);
4918 /* If this substitution failed, this whole thing fails. */
4919 if (GET_CODE (new_rtx) == CLOBBER
4920 && XEXP (new_rtx, 0) == const0_rtx)
4923 SUBST (SET_DEST (XVECEXP (x, 0, i)), new_rtx);
4929 len = GET_RTX_LENGTH (code);
4930 fmt = GET_RTX_FORMAT (code);
4932 /* We don't need to process a SET_DEST that is a register, CC0,
4933 or PC, so set up to skip this common case. All other cases
4934 where we want to suppress replacing something inside a
4935 SET_SRC are handled via the IN_DEST operand. */
4937 && (REG_P (SET_DEST (x))
4938 || GET_CODE (SET_DEST (x)) == CC0
4939 || GET_CODE (SET_DEST (x)) == PC))
4942 /* Get the mode of operand 0 in case X is now a SIGN_EXTEND of a
4945 op0_mode = GET_MODE (XEXP (x, 0));
4947 for (i = 0; i < len; i++)
4952 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
4954 if (COMBINE_RTX_EQUAL_P (XVECEXP (x, i, j), from))
4956 new_rtx = (unique_copy && n_occurrences
4957 ? copy_rtx (to) : to);
4962 new_rtx = subst (XVECEXP (x, i, j), from, to, 0,
4965 /* If this substitution failed, this whole thing
4967 if (GET_CODE (new_rtx) == CLOBBER
4968 && XEXP (new_rtx, 0) == const0_rtx)
4972 SUBST (XVECEXP (x, i, j), new_rtx);
4975 else if (fmt[i] == 'e')
4977 /* If this is a register being set, ignore it. */
4978 new_rtx = XEXP (x, i);
4981 && (((code == SUBREG || code == ZERO_EXTRACT)
4983 || code == STRICT_LOW_PART))
4986 else if (COMBINE_RTX_EQUAL_P (XEXP (x, i), from))
4988 /* In general, don't install a subreg involving two
4989 modes not tieable. It can worsen register
4990 allocation, and can even make invalid reload
4991 insns, since the reg inside may need to be copied
4992 from in the outside mode, and that may be invalid
4993 if it is an fp reg copied in integer mode.
4995 We allow two exceptions to this: It is valid if
4996 it is inside another SUBREG and the mode of that
4997 SUBREG and the mode of the inside of TO is
4998 tieable and it is valid if X is a SET that copies
5001 if (GET_CODE (to) == SUBREG
5002 && ! MODES_TIEABLE_P (GET_MODE (to),
5003 GET_MODE (SUBREG_REG (to)))
5004 && ! (code == SUBREG
5005 && MODES_TIEABLE_P (GET_MODE (x),
5006 GET_MODE (SUBREG_REG (to))))
5008 && ! (code == SET && i == 1 && XEXP (x, 0) == cc0_rtx)
5011 return gen_rtx_CLOBBER (VOIDmode, const0_rtx);
5013 #ifdef CANNOT_CHANGE_MODE_CLASS
5016 && REGNO (to) < FIRST_PSEUDO_REGISTER
5017 && REG_CANNOT_CHANGE_MODE_P (REGNO (to),
5020 return gen_rtx_CLOBBER (VOIDmode, const0_rtx);
5023 new_rtx = (unique_copy && n_occurrences ? copy_rtx (to) : to);
5027 /* If we are in a SET_DEST, suppress most cases unless we
5028 have gone inside a MEM, in which case we want to
5029 simplify the address. We assume here that things that
5030 are actually part of the destination have their inner
5031 parts in the first expression. This is true for SUBREG,
5032 STRICT_LOW_PART, and ZERO_EXTRACT, which are the only
5033 things aside from REG and MEM that should appear in a
5035 new_rtx = subst (XEXP (x, i), from, to,
5037 && (code == SUBREG || code == STRICT_LOW_PART
5038 || code == ZERO_EXTRACT))
5040 && i == 0), unique_copy);
5042 /* If we found that we will have to reject this combination,
5043 indicate that by returning the CLOBBER ourselves, rather than
5044 an expression containing it. This will speed things up as
5045 well as prevent accidents where two CLOBBERs are considered
5046 to be equal, thus producing an incorrect simplification. */
5048 if (GET_CODE (new_rtx) == CLOBBER && XEXP (new_rtx, 0) == const0_rtx)
5051 if (GET_CODE (x) == SUBREG
5052 && (CONST_INT_P (new_rtx)
5053 || GET_CODE (new_rtx) == CONST_DOUBLE))
5055 enum machine_mode mode = GET_MODE (x);
5057 x = simplify_subreg (GET_MODE (x), new_rtx,
5058 GET_MODE (SUBREG_REG (x)),
5061 x = gen_rtx_CLOBBER (mode, const0_rtx);
5063 else if (CONST_INT_P (new_rtx)
5064 && GET_CODE (x) == ZERO_EXTEND)
5066 x = simplify_unary_operation (ZERO_EXTEND, GET_MODE (x),
5067 new_rtx, GET_MODE (XEXP (x, 0)));
5071 SUBST (XEXP (x, i), new_rtx);
5076 /* Check if we are loading something from the constant pool via float
5077 extension; in this case we would undo compress_float_constant
5078 optimization and degenerate constant load to an immediate value. */
5079 if (GET_CODE (x) == FLOAT_EXTEND
5080 && MEM_P (XEXP (x, 0))
5081 && MEM_READONLY_P (XEXP (x, 0)))
5083 rtx tmp = avoid_constant_pool_reference (x);
5088 /* Try to simplify X. If the simplification changed the code, it is likely
5089 that further simplification will help, so loop, but limit the number
5090 of repetitions that will be performed. */
5092 for (i = 0; i < 4; i++)
5094 /* If X is sufficiently simple, don't bother trying to do anything
5096 if (code != CONST_INT && code != REG && code != CLOBBER)
5097 x = combine_simplify_rtx (x, op0_mode, in_dest);
5099 if (GET_CODE (x) == code)
5102 code = GET_CODE (x);
5104 /* We no longer know the original mode of operand 0 since we
5105 have changed the form of X) */
5106 op0_mode = VOIDmode;
5112 /* Simplify X, a piece of RTL. We just operate on the expression at the
5113 outer level; call `subst' to simplify recursively. Return the new
5116 OP0_MODE is the original mode of XEXP (x, 0). IN_DEST is nonzero
5117 if we are inside a SET_DEST. */
5120 combine_simplify_rtx (rtx x, enum machine_mode op0_mode, int in_dest)
5122 enum rtx_code code = GET_CODE (x);
5123 enum machine_mode mode = GET_MODE (x);
5127 /* If this is a commutative operation, put a constant last and a complex
5128 expression first. We don't need to do this for comparisons here. */
5129 if (COMMUTATIVE_ARITH_P (x)
5130 && swap_commutative_operands_p (XEXP (x, 0), XEXP (x, 1)))
5133 SUBST (XEXP (x, 0), XEXP (x, 1));
5134 SUBST (XEXP (x, 1), temp);
5137 /* If this is a simple operation applied to an IF_THEN_ELSE, try
5138 applying it to the arms of the IF_THEN_ELSE. This often simplifies
5139 things. Check for cases where both arms are testing the same
5142 Don't do anything if all operands are very simple. */
5145 && ((!OBJECT_P (XEXP (x, 0))
5146 && ! (GET_CODE (XEXP (x, 0)) == SUBREG
5147 && OBJECT_P (SUBREG_REG (XEXP (x, 0)))))
5148 || (!OBJECT_P (XEXP (x, 1))
5149 && ! (GET_CODE (XEXP (x, 1)) == SUBREG
5150 && OBJECT_P (SUBREG_REG (XEXP (x, 1)))))))
5152 && (!OBJECT_P (XEXP (x, 0))
5153 && ! (GET_CODE (XEXP (x, 0)) == SUBREG
5154 && OBJECT_P (SUBREG_REG (XEXP (x, 0)))))))
5156 rtx cond, true_rtx, false_rtx;
5158 cond = if_then_else_cond (x, &true_rtx, &false_rtx);
5160 /* If everything is a comparison, what we have is highly unlikely
5161 to be simpler, so don't use it. */
5162 && ! (COMPARISON_P (x)
5163 && (COMPARISON_P (true_rtx) || COMPARISON_P (false_rtx))))
5165 rtx cop1 = const0_rtx;
5166 enum rtx_code cond_code = simplify_comparison (NE, &cond, &cop1);
5168 if (cond_code == NE && COMPARISON_P (cond))
5171 /* Simplify the alternative arms; this may collapse the true and
5172 false arms to store-flag values. Be careful to use copy_rtx
5173 here since true_rtx or false_rtx might share RTL with x as a
5174 result of the if_then_else_cond call above. */
5175 true_rtx = subst (copy_rtx (true_rtx), pc_rtx, pc_rtx, 0, 0);
5176 false_rtx = subst (copy_rtx (false_rtx), pc_rtx, pc_rtx, 0, 0);
5178 /* If true_rtx and false_rtx are not general_operands, an if_then_else
5179 is unlikely to be simpler. */
5180 if (general_operand (true_rtx, VOIDmode)
5181 && general_operand (false_rtx, VOIDmode))
5183 enum rtx_code reversed;
5185 /* Restarting if we generate a store-flag expression will cause
5186 us to loop. Just drop through in this case. */
5188 /* If the result values are STORE_FLAG_VALUE and zero, we can
5189 just make the comparison operation. */
5190 if (true_rtx == const_true_rtx && false_rtx == const0_rtx)
5191 x = simplify_gen_relational (cond_code, mode, VOIDmode,
5193 else if (true_rtx == const0_rtx && false_rtx == const_true_rtx
5194 && ((reversed = reversed_comparison_code_parts
5195 (cond_code, cond, cop1, NULL))
5197 x = simplify_gen_relational (reversed, mode, VOIDmode,
5200 /* Likewise, we can make the negate of a comparison operation
5201 if the result values are - STORE_FLAG_VALUE and zero. */
5202 else if (CONST_INT_P (true_rtx)
5203 && INTVAL (true_rtx) == - STORE_FLAG_VALUE
5204 && false_rtx == const0_rtx)
5205 x = simplify_gen_unary (NEG, mode,
5206 simplify_gen_relational (cond_code,
5210 else if (CONST_INT_P (false_rtx)
5211 && INTVAL (false_rtx) == - STORE_FLAG_VALUE
5212 && true_rtx == const0_rtx
5213 && ((reversed = reversed_comparison_code_parts
5214 (cond_code, cond, cop1, NULL))
5216 x = simplify_gen_unary (NEG, mode,
5217 simplify_gen_relational (reversed,
5222 return gen_rtx_IF_THEN_ELSE (mode,
5223 simplify_gen_relational (cond_code,
5228 true_rtx, false_rtx);
5230 code = GET_CODE (x);
5231 op0_mode = VOIDmode;
5236 /* Try to fold this expression in case we have constants that weren't
5239 switch (GET_RTX_CLASS (code))
5242 if (op0_mode == VOIDmode)
5243 op0_mode = GET_MODE (XEXP (x, 0));
5244 temp = simplify_unary_operation (code, mode, XEXP (x, 0), op0_mode);
5247 case RTX_COMM_COMPARE:
5249 enum machine_mode cmp_mode = GET_MODE (XEXP (x, 0));
5250 if (cmp_mode == VOIDmode)
5252 cmp_mode = GET_MODE (XEXP (x, 1));
5253 if (cmp_mode == VOIDmode)
5254 cmp_mode = op0_mode;
5256 temp = simplify_relational_operation (code, mode, cmp_mode,
5257 XEXP (x, 0), XEXP (x, 1));
5260 case RTX_COMM_ARITH:
5262 temp = simplify_binary_operation (code, mode, XEXP (x, 0), XEXP (x, 1));
5264 case RTX_BITFIELD_OPS:
5266 temp = simplify_ternary_operation (code, mode, op0_mode, XEXP (x, 0),
5267 XEXP (x, 1), XEXP (x, 2));
5276 code = GET_CODE (temp);
5277 op0_mode = VOIDmode;
5278 mode = GET_MODE (temp);
5281 /* First see if we can apply the inverse distributive law. */
5282 if (code == PLUS || code == MINUS
5283 || code == AND || code == IOR || code == XOR)
5285 x = apply_distributive_law (x);
5286 code = GET_CODE (x);
5287 op0_mode = VOIDmode;
5290 /* If CODE is an associative operation not otherwise handled, see if we
5291 can associate some operands. This can win if they are constants or
5292 if they are logically related (i.e. (a & b) & a). */
5293 if ((code == PLUS || code == MINUS || code == MULT || code == DIV
5294 || code == AND || code == IOR || code == XOR
5295 || code == SMAX || code == SMIN || code == UMAX || code == UMIN)
5296 && ((INTEGRAL_MODE_P (mode) && code != DIV)
5297 || (flag_associative_math && FLOAT_MODE_P (mode))))
5299 if (GET_CODE (XEXP (x, 0)) == code)
5301 rtx other = XEXP (XEXP (x, 0), 0);
5302 rtx inner_op0 = XEXP (XEXP (x, 0), 1);
5303 rtx inner_op1 = XEXP (x, 1);
5306 /* Make sure we pass the constant operand if any as the second
5307 one if this is a commutative operation. */
5308 if (CONSTANT_P (inner_op0) && COMMUTATIVE_ARITH_P (x))
5310 rtx tem = inner_op0;
5311 inner_op0 = inner_op1;
5314 inner = simplify_binary_operation (code == MINUS ? PLUS
5315 : code == DIV ? MULT
5317 mode, inner_op0, inner_op1);
5319 /* For commutative operations, try the other pair if that one
5321 if (inner == 0 && COMMUTATIVE_ARITH_P (x))
5323 other = XEXP (XEXP (x, 0), 1);
5324 inner = simplify_binary_operation (code, mode,
5325 XEXP (XEXP (x, 0), 0),
5330 return simplify_gen_binary (code, mode, other, inner);
5334 /* A little bit of algebraic simplification here. */
5338 /* Ensure that our address has any ASHIFTs converted to MULT in case
5339 address-recognizing predicates are called later. */
5340 temp = make_compound_operation (XEXP (x, 0), MEM);
5341 SUBST (XEXP (x, 0), temp);
5345 if (op0_mode == VOIDmode)
5346 op0_mode = GET_MODE (SUBREG_REG (x));
5348 /* See if this can be moved to simplify_subreg. */
5349 if (CONSTANT_P (SUBREG_REG (x))
5350 && subreg_lowpart_offset (mode, op0_mode) == SUBREG_BYTE (x)
5351 /* Don't call gen_lowpart if the inner mode
5352 is VOIDmode and we cannot simplify it, as SUBREG without
5353 inner mode is invalid. */
5354 && (GET_MODE (SUBREG_REG (x)) != VOIDmode
5355 || gen_lowpart_common (mode, SUBREG_REG (x))))
5356 return gen_lowpart (mode, SUBREG_REG (x));
5358 if (GET_MODE_CLASS (GET_MODE (SUBREG_REG (x))) == MODE_CC)
5362 temp = simplify_subreg (mode, SUBREG_REG (x), op0_mode,
5368 /* Don't change the mode of the MEM if that would change the meaning
5370 if (MEM_P (SUBREG_REG (x))
5371 && (MEM_VOLATILE_P (SUBREG_REG (x))
5372 || mode_dependent_address_p (XEXP (SUBREG_REG (x), 0))))
5373 return gen_rtx_CLOBBER (mode, const0_rtx);
5375 /* Note that we cannot do any narrowing for non-constants since
5376 we might have been counting on using the fact that some bits were
5377 zero. We now do this in the SET. */
5382 temp = expand_compound_operation (XEXP (x, 0));
5384 /* For C equal to the width of MODE minus 1, (neg (ashiftrt X C)) can be
5385 replaced by (lshiftrt X C). This will convert
5386 (neg (sign_extract X 1 Y)) to (zero_extract X 1 Y). */
5388 if (GET_CODE (temp) == ASHIFTRT
5389 && CONST_INT_P (XEXP (temp, 1))
5390 && INTVAL (XEXP (temp, 1)) == GET_MODE_BITSIZE (mode) - 1)
5391 return simplify_shift_const (NULL_RTX, LSHIFTRT, mode, XEXP (temp, 0),
5392 INTVAL (XEXP (temp, 1)));
5394 /* If X has only a single bit that might be nonzero, say, bit I, convert
5395 (neg X) to (ashiftrt (ashift X C-I) C-I) where C is the bitsize of
5396 MODE minus 1. This will convert (neg (zero_extract X 1 Y)) to
5397 (sign_extract X 1 Y). But only do this if TEMP isn't a register
5398 or a SUBREG of one since we'd be making the expression more
5399 complex if it was just a register. */
5402 && ! (GET_CODE (temp) == SUBREG
5403 && REG_P (SUBREG_REG (temp)))
5404 && (i = exact_log2 (nonzero_bits (temp, mode))) >= 0)
5406 rtx temp1 = simplify_shift_const
5407 (NULL_RTX, ASHIFTRT, mode,
5408 simplify_shift_const (NULL_RTX, ASHIFT, mode, temp,
5409 GET_MODE_BITSIZE (mode) - 1 - i),
5410 GET_MODE_BITSIZE (mode) - 1 - i);
5412 /* If all we did was surround TEMP with the two shifts, we
5413 haven't improved anything, so don't use it. Otherwise,
5414 we are better off with TEMP1. */
5415 if (GET_CODE (temp1) != ASHIFTRT
5416 || GET_CODE (XEXP (temp1, 0)) != ASHIFT
5417 || XEXP (XEXP (temp1, 0), 0) != temp)
5423 /* We can't handle truncation to a partial integer mode here
5424 because we don't know the real bitsize of the partial
5426 if (GET_MODE_CLASS (mode) == MODE_PARTIAL_INT)
5429 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
5431 force_to_mode (XEXP (x, 0), GET_MODE (XEXP (x, 0)),
5432 GET_MODE_MASK (mode), 0));
5434 /* We can truncate a constant value and return it. */
5435 if (CONST_INT_P (XEXP (x, 0)))
5436 return gen_int_mode (INTVAL (XEXP (x, 0)), mode);
5438 /* Similarly to what we do in simplify-rtx.c, a truncate of a register
5439 whose value is a comparison can be replaced with a subreg if
5440 STORE_FLAG_VALUE permits. */
5441 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5442 && ((HOST_WIDE_INT) STORE_FLAG_VALUE & ~GET_MODE_MASK (mode)) == 0
5443 && (temp = get_last_value (XEXP (x, 0)))
5444 && COMPARISON_P (temp))
5445 return gen_lowpart (mode, XEXP (x, 0));
5449 /* (const (const X)) can become (const X). Do it this way rather than
5450 returning the inner CONST since CONST can be shared with a
5452 if (GET_CODE (XEXP (x, 0)) == CONST)
5453 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
5458 /* Convert (lo_sum (high FOO) FOO) to FOO. This is necessary so we
5459 can add in an offset. find_split_point will split this address up
5460 again if it doesn't match. */
5461 if (GET_CODE (XEXP (x, 0)) == HIGH
5462 && rtx_equal_p (XEXP (XEXP (x, 0), 0), XEXP (x, 1)))
5468 /* (plus (xor (and <foo> (const_int pow2 - 1)) <c>) <-c>)
5469 when c is (const_int (pow2 + 1) / 2) is a sign extension of a
5470 bit-field and can be replaced by either a sign_extend or a
5471 sign_extract. The `and' may be a zero_extend and the two
5472 <c>, -<c> constants may be reversed. */
5473 if (GET_CODE (XEXP (x, 0)) == XOR
5474 && CONST_INT_P (XEXP (x, 1))
5475 && CONST_INT_P (XEXP (XEXP (x, 0), 1))
5476 && INTVAL (XEXP (x, 1)) == -INTVAL (XEXP (XEXP (x, 0), 1))
5477 && ((i = exact_log2 (INTVAL (XEXP (XEXP (x, 0), 1)))) >= 0
5478 || (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0)
5479 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5480 && ((GET_CODE (XEXP (XEXP (x, 0), 0)) == AND
5481 && CONST_INT_P (XEXP (XEXP (XEXP (x, 0), 0), 1))
5482 && (INTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1))
5483 == ((HOST_WIDE_INT) 1 << (i + 1)) - 1))
5484 || (GET_CODE (XEXP (XEXP (x, 0), 0)) == ZERO_EXTEND
5485 && (GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)))
5486 == (unsigned int) i + 1))))
5487 return simplify_shift_const
5488 (NULL_RTX, ASHIFTRT, mode,
5489 simplify_shift_const (NULL_RTX, ASHIFT, mode,
5490 XEXP (XEXP (XEXP (x, 0), 0), 0),
5491 GET_MODE_BITSIZE (mode) - (i + 1)),
5492 GET_MODE_BITSIZE (mode) - (i + 1));
5494 /* If only the low-order bit of X is possibly nonzero, (plus x -1)
5495 can become (ashiftrt (ashift (xor x 1) C) C) where C is
5496 the bitsize of the mode - 1. This allows simplification of
5497 "a = (b & 8) == 0;" */
5498 if (XEXP (x, 1) == constm1_rtx
5499 && !REG_P (XEXP (x, 0))
5500 && ! (GET_CODE (XEXP (x, 0)) == SUBREG
5501 && REG_P (SUBREG_REG (XEXP (x, 0))))
5502 && nonzero_bits (XEXP (x, 0), mode) == 1)
5503 return simplify_shift_const (NULL_RTX, ASHIFTRT, mode,
5504 simplify_shift_const (NULL_RTX, ASHIFT, mode,
5505 gen_rtx_XOR (mode, XEXP (x, 0), const1_rtx),
5506 GET_MODE_BITSIZE (mode) - 1),
5507 GET_MODE_BITSIZE (mode) - 1);
5509 /* If we are adding two things that have no bits in common, convert
5510 the addition into an IOR. This will often be further simplified,
5511 for example in cases like ((a & 1) + (a & 2)), which can
5514 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5515 && (nonzero_bits (XEXP (x, 0), mode)
5516 & nonzero_bits (XEXP (x, 1), mode)) == 0)
5518 /* Try to simplify the expression further. */
5519 rtx tor = simplify_gen_binary (IOR, mode, XEXP (x, 0), XEXP (x, 1));
5520 temp = combine_simplify_rtx (tor, mode, in_dest);
5522 /* If we could, great. If not, do not go ahead with the IOR
5523 replacement, since PLUS appears in many special purpose
5524 address arithmetic instructions. */
5525 if (GET_CODE (temp) != CLOBBER && temp != tor)
5531 /* (minus <foo> (and <foo> (const_int -pow2))) becomes
5532 (and <foo> (const_int pow2-1)) */
5533 if (GET_CODE (XEXP (x, 1)) == AND
5534 && CONST_INT_P (XEXP (XEXP (x, 1), 1))
5535 && exact_log2 (-INTVAL (XEXP (XEXP (x, 1), 1))) >= 0
5536 && rtx_equal_p (XEXP (XEXP (x, 1), 0), XEXP (x, 0)))
5537 return simplify_and_const_int (NULL_RTX, mode, XEXP (x, 0),
5538 -INTVAL (XEXP (XEXP (x, 1), 1)) - 1);
5542 /* If we have (mult (plus A B) C), apply the distributive law and then
5543 the inverse distributive law to see if things simplify. This
5544 occurs mostly in addresses, often when unrolling loops. */
5546 if (GET_CODE (XEXP (x, 0)) == PLUS)
5548 rtx result = distribute_and_simplify_rtx (x, 0);
5553 /* Try simplify a*(b/c) as (a*b)/c. */
5554 if (FLOAT_MODE_P (mode) && flag_associative_math
5555 && GET_CODE (XEXP (x, 0)) == DIV)
5557 rtx tem = simplify_binary_operation (MULT, mode,
5558 XEXP (XEXP (x, 0), 0),
5561 return simplify_gen_binary (DIV, mode, tem, XEXP (XEXP (x, 0), 1));
5566 /* If this is a divide by a power of two, treat it as a shift if
5567 its first operand is a shift. */
5568 if (CONST_INT_P (XEXP (x, 1))
5569 && (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0
5570 && (GET_CODE (XEXP (x, 0)) == ASHIFT
5571 || GET_CODE (XEXP (x, 0)) == LSHIFTRT
5572 || GET_CODE (XEXP (x, 0)) == ASHIFTRT
5573 || GET_CODE (XEXP (x, 0)) == ROTATE
5574 || GET_CODE (XEXP (x, 0)) == ROTATERT))
5575 return simplify_shift_const (NULL_RTX, LSHIFTRT, mode, XEXP (x, 0), i);
5579 case GT: case GTU: case GE: case GEU:
5580 case LT: case LTU: case LE: case LEU:
5581 case UNEQ: case LTGT:
5582 case UNGT: case UNGE:
5583 case UNLT: case UNLE:
5584 case UNORDERED: case ORDERED:
5585 /* If the first operand is a condition code, we can't do anything
5587 if (GET_CODE (XEXP (x, 0)) == COMPARE
5588 || (GET_MODE_CLASS (GET_MODE (XEXP (x, 0))) != MODE_CC
5589 && ! CC0_P (XEXP (x, 0))))
5591 rtx op0 = XEXP (x, 0);
5592 rtx op1 = XEXP (x, 1);
5593 enum rtx_code new_code;
5595 if (GET_CODE (op0) == COMPARE)
5596 op1 = XEXP (op0, 1), op0 = XEXP (op0, 0);
5598 /* Simplify our comparison, if possible. */
5599 new_code = simplify_comparison (code, &op0, &op1);
5601 /* If STORE_FLAG_VALUE is 1, we can convert (ne x 0) to simply X
5602 if only the low-order bit is possibly nonzero in X (such as when
5603 X is a ZERO_EXTRACT of one bit). Similarly, we can convert EQ to
5604 (xor X 1) or (minus 1 X); we use the former. Finally, if X is
5605 known to be either 0 or -1, NE becomes a NEG and EQ becomes
5608 Remove any ZERO_EXTRACT we made when thinking this was a
5609 comparison. It may now be simpler to use, e.g., an AND. If a
5610 ZERO_EXTRACT is indeed appropriate, it will be placed back by
5611 the call to make_compound_operation in the SET case. */
5613 if (STORE_FLAG_VALUE == 1
5614 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
5615 && op1 == const0_rtx
5616 && mode == GET_MODE (op0)
5617 && nonzero_bits (op0, mode) == 1)
5618 return gen_lowpart (mode,
5619 expand_compound_operation (op0));
5621 else if (STORE_FLAG_VALUE == 1
5622 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
5623 && op1 == const0_rtx
5624 && mode == GET_MODE (op0)
5625 && (num_sign_bit_copies (op0, mode)
5626 == GET_MODE_BITSIZE (mode)))
5628 op0 = expand_compound_operation (op0);
5629 return simplify_gen_unary (NEG, mode,
5630 gen_lowpart (mode, op0),
5634 else if (STORE_FLAG_VALUE == 1
5635 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
5636 && op1 == const0_rtx
5637 && mode == GET_MODE (op0)
5638 && nonzero_bits (op0, mode) == 1)
5640 op0 = expand_compound_operation (op0);
5641 return simplify_gen_binary (XOR, mode,
5642 gen_lowpart (mode, op0),
5646 else if (STORE_FLAG_VALUE == 1
5647 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
5648 && op1 == const0_rtx
5649 && mode == GET_MODE (op0)
5650 && (num_sign_bit_copies (op0, mode)
5651 == GET_MODE_BITSIZE (mode)))
5653 op0 = expand_compound_operation (op0);
5654 return plus_constant (gen_lowpart (mode, op0), 1);
5657 /* If STORE_FLAG_VALUE is -1, we have cases similar to
5659 if (STORE_FLAG_VALUE == -1
5660 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
5661 && op1 == const0_rtx
5662 && (num_sign_bit_copies (op0, mode)
5663 == GET_MODE_BITSIZE (mode)))
5664 return gen_lowpart (mode,
5665 expand_compound_operation (op0));
5667 else if (STORE_FLAG_VALUE == -1
5668 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
5669 && op1 == const0_rtx
5670 && mode == GET_MODE (op0)
5671 && nonzero_bits (op0, mode) == 1)
5673 op0 = expand_compound_operation (op0);
5674 return simplify_gen_unary (NEG, mode,
5675 gen_lowpart (mode, op0),
5679 else if (STORE_FLAG_VALUE == -1
5680 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
5681 && op1 == const0_rtx
5682 && mode == GET_MODE (op0)
5683 && (num_sign_bit_copies (op0, mode)
5684 == GET_MODE_BITSIZE (mode)))
5686 op0 = expand_compound_operation (op0);
5687 return simplify_gen_unary (NOT, mode,
5688 gen_lowpart (mode, op0),
5692 /* If X is 0/1, (eq X 0) is X-1. */
5693 else if (STORE_FLAG_VALUE == -1
5694 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
5695 && op1 == const0_rtx
5696 && mode == GET_MODE (op0)
5697 && nonzero_bits (op0, mode) == 1)
5699 op0 = expand_compound_operation (op0);
5700 return plus_constant (gen_lowpart (mode, op0), -1);
5703 /* If STORE_FLAG_VALUE says to just test the sign bit and X has just
5704 one bit that might be nonzero, we can convert (ne x 0) to
5705 (ashift x c) where C puts the bit in the sign bit. Remove any
5706 AND with STORE_FLAG_VALUE when we are done, since we are only
5707 going to test the sign bit. */
5708 if (new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
5709 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5710 && ((STORE_FLAG_VALUE & GET_MODE_MASK (mode))
5711 == (unsigned HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (mode) - 1))
5712 && op1 == const0_rtx
5713 && mode == GET_MODE (op0)
5714 && (i = exact_log2 (nonzero_bits (op0, mode))) >= 0)
5716 x = simplify_shift_const (NULL_RTX, ASHIFT, mode,
5717 expand_compound_operation (op0),
5718 GET_MODE_BITSIZE (mode) - 1 - i);
5719 if (GET_CODE (x) == AND && XEXP (x, 1) == const_true_rtx)
5725 /* If the code changed, return a whole new comparison. */
5726 if (new_code != code)
5727 return gen_rtx_fmt_ee (new_code, mode, op0, op1);
5729 /* Otherwise, keep this operation, but maybe change its operands.
5730 This also converts (ne (compare FOO BAR) 0) to (ne FOO BAR). */
5731 SUBST (XEXP (x, 0), op0);
5732 SUBST (XEXP (x, 1), op1);
5737 return simplify_if_then_else (x);
5743 /* If we are processing SET_DEST, we are done. */
5747 return expand_compound_operation (x);
5750 return simplify_set (x);
5754 return simplify_logical (x);
5761 /* If this is a shift by a constant amount, simplify it. */
5762 if (CONST_INT_P (XEXP (x, 1)))
5763 return simplify_shift_const (x, code, mode, XEXP (x, 0),
5764 INTVAL (XEXP (x, 1)));
5766 else if (SHIFT_COUNT_TRUNCATED && !REG_P (XEXP (x, 1)))
5768 force_to_mode (XEXP (x, 1), GET_MODE (XEXP (x, 1)),
5770 << exact_log2 (GET_MODE_BITSIZE (GET_MODE (x))))
5782 /* Simplify X, an IF_THEN_ELSE expression. Return the new expression. */
5785 simplify_if_then_else (rtx x)
5787 enum machine_mode mode = GET_MODE (x);
5788 rtx cond = XEXP (x, 0);
5789 rtx true_rtx = XEXP (x, 1);
5790 rtx false_rtx = XEXP (x, 2);
5791 enum rtx_code true_code = GET_CODE (cond);
5792 int comparison_p = COMPARISON_P (cond);
5795 enum rtx_code false_code;
5798 /* Simplify storing of the truth value. */
5799 if (comparison_p && true_rtx == const_true_rtx && false_rtx == const0_rtx)
5800 return simplify_gen_relational (true_code, mode, VOIDmode,
5801 XEXP (cond, 0), XEXP (cond, 1));
5803 /* Also when the truth value has to be reversed. */
5805 && true_rtx == const0_rtx && false_rtx == const_true_rtx
5806 && (reversed = reversed_comparison (cond, mode)))
5809 /* Sometimes we can simplify the arm of an IF_THEN_ELSE if a register used
5810 in it is being compared against certain values. Get the true and false
5811 comparisons and see if that says anything about the value of each arm. */
5814 && ((false_code = reversed_comparison_code (cond, NULL))
5816 && REG_P (XEXP (cond, 0)))
5819 rtx from = XEXP (cond, 0);
5820 rtx true_val = XEXP (cond, 1);
5821 rtx false_val = true_val;
5824 /* If FALSE_CODE is EQ, swap the codes and arms. */
5826 if (false_code == EQ)
5828 swapped = 1, true_code = EQ, false_code = NE;
5829 temp = true_rtx, true_rtx = false_rtx, false_rtx = temp;
5832 /* If we are comparing against zero and the expression being tested has
5833 only a single bit that might be nonzero, that is its value when it is
5834 not equal to zero. Similarly if it is known to be -1 or 0. */
5836 if (true_code == EQ && true_val == const0_rtx
5837 && exact_log2 (nzb = nonzero_bits (from, GET_MODE (from))) >= 0)
5840 false_val = GEN_INT (trunc_int_for_mode (nzb, GET_MODE (from)));
5842 else if (true_code == EQ && true_val == const0_rtx
5843 && (num_sign_bit_copies (from, GET_MODE (from))
5844 == GET_MODE_BITSIZE (GET_MODE (from))))
5847 false_val = constm1_rtx;
5850 /* Now simplify an arm if we know the value of the register in the
5851 branch and it is used in the arm. Be careful due to the potential
5852 of locally-shared RTL. */
5854 if (reg_mentioned_p (from, true_rtx))
5855 true_rtx = subst (known_cond (copy_rtx (true_rtx), true_code,
5857 pc_rtx, pc_rtx, 0, 0);
5858 if (reg_mentioned_p (from, false_rtx))
5859 false_rtx = subst (known_cond (copy_rtx (false_rtx), false_code,
5861 pc_rtx, pc_rtx, 0, 0);
5863 SUBST (XEXP (x, 1), swapped ? false_rtx : true_rtx);
5864 SUBST (XEXP (x, 2), swapped ? true_rtx : false_rtx);
5866 true_rtx = XEXP (x, 1);
5867 false_rtx = XEXP (x, 2);
5868 true_code = GET_CODE (cond);
5871 /* If we have (if_then_else FOO (pc) (label_ref BAR)) and FOO can be
5872 reversed, do so to avoid needing two sets of patterns for
5873 subtract-and-branch insns. Similarly if we have a constant in the true
5874 arm, the false arm is the same as the first operand of the comparison, or
5875 the false arm is more complicated than the true arm. */
5878 && reversed_comparison_code (cond, NULL) != UNKNOWN
5879 && (true_rtx == pc_rtx
5880 || (CONSTANT_P (true_rtx)
5881 && !CONST_INT_P (false_rtx) && false_rtx != pc_rtx)
5882 || true_rtx == const0_rtx
5883 || (OBJECT_P (true_rtx) && !OBJECT_P (false_rtx))
5884 || (GET_CODE (true_rtx) == SUBREG && OBJECT_P (SUBREG_REG (true_rtx))
5885 && !OBJECT_P (false_rtx))
5886 || reg_mentioned_p (true_rtx, false_rtx)
5887 || rtx_equal_p (false_rtx, XEXP (cond, 0))))
5889 true_code = reversed_comparison_code (cond, NULL);
5890 SUBST (XEXP (x, 0), reversed_comparison (cond, GET_MODE (cond)));
5891 SUBST (XEXP (x, 1), false_rtx);
5892 SUBST (XEXP (x, 2), true_rtx);
5894 temp = true_rtx, true_rtx = false_rtx, false_rtx = temp;
5897 /* It is possible that the conditional has been simplified out. */
5898 true_code = GET_CODE (cond);
5899 comparison_p = COMPARISON_P (cond);
5902 /* If the two arms are identical, we don't need the comparison. */
5904 if (rtx_equal_p (true_rtx, false_rtx) && ! side_effects_p (cond))
5907 /* Convert a == b ? b : a to "a". */
5908 if (true_code == EQ && ! side_effects_p (cond)
5909 && !HONOR_NANS (mode)
5910 && rtx_equal_p (XEXP (cond, 0), false_rtx)
5911 && rtx_equal_p (XEXP (cond, 1), true_rtx))
5913 else if (true_code == NE && ! side_effects_p (cond)
5914 && !HONOR_NANS (mode)
5915 && rtx_equal_p (XEXP (cond, 0), true_rtx)
5916 && rtx_equal_p (XEXP (cond, 1), false_rtx))
5919 /* Look for cases where we have (abs x) or (neg (abs X)). */
5921 if (GET_MODE_CLASS (mode) == MODE_INT
5923 && XEXP (cond, 1) == const0_rtx
5924 && GET_CODE (false_rtx) == NEG
5925 && rtx_equal_p (true_rtx, XEXP (false_rtx, 0))
5926 && rtx_equal_p (true_rtx, XEXP (cond, 0))
5927 && ! side_effects_p (true_rtx))
5932 return simplify_gen_unary (ABS, mode, true_rtx, mode);
5936 simplify_gen_unary (NEG, mode,
5937 simplify_gen_unary (ABS, mode, true_rtx, mode),
5943 /* Look for MIN or MAX. */
5945 if ((! FLOAT_MODE_P (mode) || flag_unsafe_math_optimizations)
5947 && rtx_equal_p (XEXP (cond, 0), true_rtx)
5948 && rtx_equal_p (XEXP (cond, 1), false_rtx)
5949 && ! side_effects_p (cond))
5954 return simplify_gen_binary (SMAX, mode, true_rtx, false_rtx);
5957 return simplify_gen_binary (SMIN, mode, true_rtx, false_rtx);
5960 return simplify_gen_binary (UMAX, mode, true_rtx, false_rtx);
5963 return simplify_gen_binary (UMIN, mode, true_rtx, false_rtx);
5968 /* If we have (if_then_else COND (OP Z C1) Z) and OP is an identity when its
5969 second operand is zero, this can be done as (OP Z (mult COND C2)) where
5970 C2 = C1 * STORE_FLAG_VALUE. Similarly if OP has an outer ZERO_EXTEND or
5971 SIGN_EXTEND as long as Z is already extended (so we don't destroy it).
5972 We can do this kind of thing in some cases when STORE_FLAG_VALUE is
5973 neither 1 or -1, but it isn't worth checking for. */
5975 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
5977 && GET_MODE_CLASS (mode) == MODE_INT
5978 && ! side_effects_p (x))
5980 rtx t = make_compound_operation (true_rtx, SET);
5981 rtx f = make_compound_operation (false_rtx, SET);
5982 rtx cond_op0 = XEXP (cond, 0);
5983 rtx cond_op1 = XEXP (cond, 1);
5984 enum rtx_code op = UNKNOWN, extend_op = UNKNOWN;
5985 enum machine_mode m = mode;
5986 rtx z = 0, c1 = NULL_RTX;
5988 if ((GET_CODE (t) == PLUS || GET_CODE (t) == MINUS
5989 || GET_CODE (t) == IOR || GET_CODE (t) == XOR
5990 || GET_CODE (t) == ASHIFT
5991 || GET_CODE (t) == LSHIFTRT || GET_CODE (t) == ASHIFTRT)
5992 && rtx_equal_p (XEXP (t, 0), f))
5993 c1 = XEXP (t, 1), op = GET_CODE (t), z = f;
5995 /* If an identity-zero op is commutative, check whether there
5996 would be a match if we swapped the operands. */
5997 else if ((GET_CODE (t) == PLUS || GET_CODE (t) == IOR
5998 || GET_CODE (t) == XOR)
5999 && rtx_equal_p (XEXP (t, 1), f))
6000 c1 = XEXP (t, 0), op = GET_CODE (t), z = f;
6001 else if (GET_CODE (t) == SIGN_EXTEND
6002 && (GET_CODE (XEXP (t, 0)) == PLUS
6003 || GET_CODE (XEXP (t, 0)) == MINUS
6004 || GET_CODE (XEXP (t, 0)) == IOR
6005 || GET_CODE (XEXP (t, 0)) == XOR
6006 || GET_CODE (XEXP (t, 0)) == ASHIFT
6007 || GET_CODE (XEXP (t, 0)) == LSHIFTRT
6008 || GET_CODE (XEXP (t, 0)) == ASHIFTRT)
6009 && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG
6010 && subreg_lowpart_p (XEXP (XEXP (t, 0), 0))
6011 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f)
6012 && (num_sign_bit_copies (f, GET_MODE (f))
6014 (GET_MODE_BITSIZE (mode)
6015 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t, 0), 0))))))
6017 c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0));
6018 extend_op = SIGN_EXTEND;
6019 m = GET_MODE (XEXP (t, 0));
6021 else if (GET_CODE (t) == SIGN_EXTEND
6022 && (GET_CODE (XEXP (t, 0)) == PLUS
6023 || GET_CODE (XEXP (t, 0)) == IOR
6024 || GET_CODE (XEXP (t, 0)) == XOR)
6025 && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG
6026 && subreg_lowpart_p (XEXP (XEXP (t, 0), 1))
6027 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f)
6028 && (num_sign_bit_copies (f, GET_MODE (f))
6030 (GET_MODE_BITSIZE (mode)
6031 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t, 0), 1))))))
6033 c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0));
6034 extend_op = SIGN_EXTEND;
6035 m = GET_MODE (XEXP (t, 0));
6037 else if (GET_CODE (t) == ZERO_EXTEND
6038 && (GET_CODE (XEXP (t, 0)) == PLUS
6039 || GET_CODE (XEXP (t, 0)) == MINUS
6040 || GET_CODE (XEXP (t, 0)) == IOR
6041 || GET_CODE (XEXP (t, 0)) == XOR
6042 || GET_CODE (XEXP (t, 0)) == ASHIFT
6043 || GET_CODE (XEXP (t, 0)) == LSHIFTRT
6044 || GET_CODE (XEXP (t, 0)) == ASHIFTRT)
6045 && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG
6046 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
6047 && subreg_lowpart_p (XEXP (XEXP (t, 0), 0))
6048 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f)
6049 && ((nonzero_bits (f, GET_MODE (f))
6050 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t, 0), 0))))
6053 c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0));
6054 extend_op = ZERO_EXTEND;
6055 m = GET_MODE (XEXP (t, 0));
6057 else if (GET_CODE (t) == ZERO_EXTEND
6058 && (GET_CODE (XEXP (t, 0)) == PLUS
6059 || GET_CODE (XEXP (t, 0)) == IOR
6060 || GET_CODE (XEXP (t, 0)) == XOR)
6061 && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG
6062 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
6063 && subreg_lowpart_p (XEXP (XEXP (t, 0), 1))
6064 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f)
6065 && ((nonzero_bits (f, GET_MODE (f))
6066 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t, 0), 1))))
6069 c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0));
6070 extend_op = ZERO_EXTEND;
6071 m = GET_MODE (XEXP (t, 0));
6076 temp = subst (simplify_gen_relational (true_code, m, VOIDmode,
6077 cond_op0, cond_op1),
6078 pc_rtx, pc_rtx, 0, 0);
6079 temp = simplify_gen_binary (MULT, m, temp,
6080 simplify_gen_binary (MULT, m, c1,
6082 temp = subst (temp, pc_rtx, pc_rtx, 0, 0);
6083 temp = simplify_gen_binary (op, m, gen_lowpart (m, z), temp);
6085 if (extend_op != UNKNOWN)
6086 temp = simplify_gen_unary (extend_op, mode, temp, m);
6092 /* If we have (if_then_else (ne A 0) C1 0) and either A is known to be 0 or
6093 1 and C1 is a single bit or A is known to be 0 or -1 and C1 is the
6094 negation of a single bit, we can convert this operation to a shift. We
6095 can actually do this more generally, but it doesn't seem worth it. */
6097 if (true_code == NE && XEXP (cond, 1) == const0_rtx
6098 && false_rtx == const0_rtx && CONST_INT_P (true_rtx)
6099 && ((1 == nonzero_bits (XEXP (cond, 0), mode)
6100 && (i = exact_log2 (INTVAL (true_rtx))) >= 0)
6101 || ((num_sign_bit_copies (XEXP (cond, 0), mode)
6102 == GET_MODE_BITSIZE (mode))
6103 && (i = exact_log2 (-INTVAL (true_rtx))) >= 0)))
6105 simplify_shift_const (NULL_RTX, ASHIFT, mode,
6106 gen_lowpart (mode, XEXP (cond, 0)), i);
6108 /* (IF_THEN_ELSE (NE REG 0) (0) (8)) is REG for nonzero_bits (REG) == 8. */
6109 if (true_code == NE && XEXP (cond, 1) == const0_rtx
6110 && false_rtx == const0_rtx && CONST_INT_P (true_rtx)
6111 && GET_MODE (XEXP (cond, 0)) == mode
6112 && (INTVAL (true_rtx) & GET_MODE_MASK (mode))
6113 == nonzero_bits (XEXP (cond, 0), mode)
6114 && (i = exact_log2 (INTVAL (true_rtx) & GET_MODE_MASK (mode))) >= 0)
6115 return XEXP (cond, 0);
6120 /* Simplify X, a SET expression. Return the new expression. */
6123 simplify_set (rtx x)
6125 rtx src = SET_SRC (x);
6126 rtx dest = SET_DEST (x);
6127 enum machine_mode mode
6128 = GET_MODE (src) != VOIDmode ? GET_MODE (src) : GET_MODE (dest);
6132 /* (set (pc) (return)) gets written as (return). */
6133 if (GET_CODE (dest) == PC && GET_CODE (src) == RETURN)
6136 /* Now that we know for sure which bits of SRC we are using, see if we can
6137 simplify the expression for the object knowing that we only need the
6140 if (GET_MODE_CLASS (mode) == MODE_INT
6141 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
6143 src = force_to_mode (src, mode, ~(HOST_WIDE_INT) 0, 0);
6144 SUBST (SET_SRC (x), src);
6147 /* If we are setting CC0 or if the source is a COMPARE, look for the use of
6148 the comparison result and try to simplify it unless we already have used
6149 undobuf.other_insn. */
6150 if ((GET_MODE_CLASS (mode) == MODE_CC
6151 || GET_CODE (src) == COMPARE
6153 && (cc_use = find_single_use (dest, subst_insn, &other_insn)) != 0
6154 && (undobuf.other_insn == 0 || other_insn == undobuf.other_insn)
6155 && COMPARISON_P (*cc_use)
6156 && rtx_equal_p (XEXP (*cc_use, 0), dest))
6158 enum rtx_code old_code = GET_CODE (*cc_use);
6159 enum rtx_code new_code;
6161 int other_changed = 0;
6162 enum machine_mode compare_mode = GET_MODE (dest);
6164 if (GET_CODE (src) == COMPARE)
6165 op0 = XEXP (src, 0), op1 = XEXP (src, 1);
6167 op0 = src, op1 = CONST0_RTX (GET_MODE (src));
6169 tmp = simplify_relational_operation (old_code, compare_mode, VOIDmode,
6172 new_code = old_code;
6173 else if (!CONSTANT_P (tmp))
6175 new_code = GET_CODE (tmp);
6176 op0 = XEXP (tmp, 0);
6177 op1 = XEXP (tmp, 1);
6181 rtx pat = PATTERN (other_insn);
6182 undobuf.other_insn = other_insn;
6183 SUBST (*cc_use, tmp);
6185 /* Attempt to simplify CC user. */
6186 if (GET_CODE (pat) == SET)
6188 rtx new_rtx = simplify_rtx (SET_SRC (pat));
6189 if (new_rtx != NULL_RTX)
6190 SUBST (SET_SRC (pat), new_rtx);
6193 /* Convert X into a no-op move. */
6194 SUBST (SET_DEST (x), pc_rtx);
6195 SUBST (SET_SRC (x), pc_rtx);
6199 /* Simplify our comparison, if possible. */
6200 new_code = simplify_comparison (new_code, &op0, &op1);
6202 #ifdef SELECT_CC_MODE
6203 /* If this machine has CC modes other than CCmode, check to see if we
6204 need to use a different CC mode here. */
6205 if (GET_MODE_CLASS (GET_MODE (op0)) == MODE_CC)
6206 compare_mode = GET_MODE (op0);
6208 compare_mode = SELECT_CC_MODE (new_code, op0, op1);
6211 /* If the mode changed, we have to change SET_DEST, the mode in the
6212 compare, and the mode in the place SET_DEST is used. If SET_DEST is
6213 a hard register, just build new versions with the proper mode. If it
6214 is a pseudo, we lose unless it is only time we set the pseudo, in
6215 which case we can safely change its mode. */
6216 if (compare_mode != GET_MODE (dest))
6218 if (can_change_dest_mode (dest, 0, compare_mode))
6220 unsigned int regno = REGNO (dest);
6223 if (regno < FIRST_PSEUDO_REGISTER)
6224 new_dest = gen_rtx_REG (compare_mode, regno);
6227 SUBST_MODE (regno_reg_rtx[regno], compare_mode);
6228 new_dest = regno_reg_rtx[regno];
6231 SUBST (SET_DEST (x), new_dest);
6232 SUBST (XEXP (*cc_use, 0), new_dest);
6239 #endif /* SELECT_CC_MODE */
6241 /* If the code changed, we have to build a new comparison in
6242 undobuf.other_insn. */
6243 if (new_code != old_code)
6245 int other_changed_previously = other_changed;
6246 unsigned HOST_WIDE_INT mask;
6247 rtx old_cc_use = *cc_use;
6249 SUBST (*cc_use, gen_rtx_fmt_ee (new_code, GET_MODE (*cc_use),
6253 /* If the only change we made was to change an EQ into an NE or
6254 vice versa, OP0 has only one bit that might be nonzero, and OP1
6255 is zero, check if changing the user of the condition code will
6256 produce a valid insn. If it won't, we can keep the original code
6257 in that insn by surrounding our operation with an XOR. */
6259 if (((old_code == NE && new_code == EQ)
6260 || (old_code == EQ && new_code == NE))
6261 && ! other_changed_previously && op1 == const0_rtx
6262 && GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
6263 && exact_log2 (mask = nonzero_bits (op0, GET_MODE (op0))) >= 0)
6265 rtx pat = PATTERN (other_insn), note = 0;
6267 if ((recog_for_combine (&pat, other_insn, ¬e) < 0
6268 && ! check_asm_operands (pat)))
6270 *cc_use = old_cc_use;
6273 op0 = simplify_gen_binary (XOR, GET_MODE (op0),
6274 op0, GEN_INT (mask));
6280 undobuf.other_insn = other_insn;
6282 /* Otherwise, if we didn't previously have a COMPARE in the
6283 correct mode, we need one. */
6284 if (GET_CODE (src) != COMPARE || GET_MODE (src) != compare_mode)
6286 SUBST (SET_SRC (x), gen_rtx_COMPARE (compare_mode, op0, op1));
6289 else if (GET_MODE (op0) == compare_mode && op1 == const0_rtx)
6291 SUBST (SET_SRC (x), op0);
6294 /* Otherwise, update the COMPARE if needed. */
6295 else if (XEXP (src, 0) != op0 || XEXP (src, 1) != op1)
6297 SUBST (SET_SRC (x), gen_rtx_COMPARE (compare_mode, op0, op1));
6303 /* Get SET_SRC in a form where we have placed back any
6304 compound expressions. Then do the checks below. */
6305 src = make_compound_operation (src, SET);
6306 SUBST (SET_SRC (x), src);
6309 /* If we have (set x (subreg:m1 (op:m2 ...) 0)) with OP being some operation,
6310 and X being a REG or (subreg (reg)), we may be able to convert this to
6311 (set (subreg:m2 x) (op)).
6313 We can always do this if M1 is narrower than M2 because that means that
6314 we only care about the low bits of the result.
6316 However, on machines without WORD_REGISTER_OPERATIONS defined, we cannot
6317 perform a narrower operation than requested since the high-order bits will
6318 be undefined. On machine where it is defined, this transformation is safe
6319 as long as M1 and M2 have the same number of words. */
6321 if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src)
6322 && !OBJECT_P (SUBREG_REG (src))
6323 && (((GET_MODE_SIZE (GET_MODE (src)) + (UNITS_PER_WORD - 1))
6325 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (src)))
6326 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD))
6327 #ifndef WORD_REGISTER_OPERATIONS
6328 && (GET_MODE_SIZE (GET_MODE (src))
6329 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (src))))
6331 #ifdef CANNOT_CHANGE_MODE_CLASS
6332 && ! (REG_P (dest) && REGNO (dest) < FIRST_PSEUDO_REGISTER
6333 && REG_CANNOT_CHANGE_MODE_P (REGNO (dest),
6334 GET_MODE (SUBREG_REG (src)),
6338 || (GET_CODE (dest) == SUBREG
6339 && REG_P (SUBREG_REG (dest)))))
6341 SUBST (SET_DEST (x),
6342 gen_lowpart (GET_MODE (SUBREG_REG (src)),
6344 SUBST (SET_SRC (x), SUBREG_REG (src));
6346 src = SET_SRC (x), dest = SET_DEST (x);
6350 /* If we have (set (cc0) (subreg ...)), we try to remove the subreg
6353 && GET_CODE (src) == SUBREG
6354 && subreg_lowpart_p (src)
6355 && (GET_MODE_BITSIZE (GET_MODE (src))
6356 < GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (src)))))
6358 rtx inner = SUBREG_REG (src);
6359 enum machine_mode inner_mode = GET_MODE (inner);
6361 /* Here we make sure that we don't have a sign bit on. */
6362 if (GET_MODE_BITSIZE (inner_mode) <= HOST_BITS_PER_WIDE_INT
6363 && (nonzero_bits (inner, inner_mode)
6364 < ((unsigned HOST_WIDE_INT) 1
6365 << (GET_MODE_BITSIZE (GET_MODE (src)) - 1))))
6367 SUBST (SET_SRC (x), inner);
6373 #ifdef LOAD_EXTEND_OP
6374 /* If we have (set FOO (subreg:M (mem:N BAR) 0)) with M wider than N, this
6375 would require a paradoxical subreg. Replace the subreg with a
6376 zero_extend to avoid the reload that would otherwise be required. */
6378 if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src)
6379 && INTEGRAL_MODE_P (GET_MODE (SUBREG_REG (src)))
6380 && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src))) != UNKNOWN
6381 && SUBREG_BYTE (src) == 0
6382 && (GET_MODE_SIZE (GET_MODE (src))
6383 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (src))))
6384 && MEM_P (SUBREG_REG (src)))
6387 gen_rtx_fmt_e (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src))),
6388 GET_MODE (src), SUBREG_REG (src)));
6394 /* If we don't have a conditional move, SET_SRC is an IF_THEN_ELSE, and we
6395 are comparing an item known to be 0 or -1 against 0, use a logical
6396 operation instead. Check for one of the arms being an IOR of the other
6397 arm with some value. We compute three terms to be IOR'ed together. In
6398 practice, at most two will be nonzero. Then we do the IOR's. */
6400 if (GET_CODE (dest) != PC
6401 && GET_CODE (src) == IF_THEN_ELSE
6402 && GET_MODE_CLASS (GET_MODE (src)) == MODE_INT
6403 && (GET_CODE (XEXP (src, 0)) == EQ || GET_CODE (XEXP (src, 0)) == NE)
6404 && XEXP (XEXP (src, 0), 1) == const0_rtx
6405 && GET_MODE (src) == GET_MODE (XEXP (XEXP (src, 0), 0))
6406 #ifdef HAVE_conditional_move
6407 && ! can_conditionally_move_p (GET_MODE (src))
6409 && (num_sign_bit_copies (XEXP (XEXP (src, 0), 0),
6410 GET_MODE (XEXP (XEXP (src, 0), 0)))
6411 == GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (src, 0), 0))))
6412 && ! side_effects_p (src))
6414 rtx true_rtx = (GET_CODE (XEXP (src, 0)) == NE
6415 ? XEXP (src, 1) : XEXP (src, 2));
6416 rtx false_rtx = (GET_CODE (XEXP (src, 0)) == NE
6417 ? XEXP (src, 2) : XEXP (src, 1));
6418 rtx term1 = const0_rtx, term2, term3;
6420 if (GET_CODE (true_rtx) == IOR
6421 && rtx_equal_p (XEXP (true_rtx, 0), false_rtx))
6422 term1 = false_rtx, true_rtx = XEXP (true_rtx, 1), false_rtx = const0_rtx;
6423 else if (GET_CODE (true_rtx) == IOR
6424 && rtx_equal_p (XEXP (true_rtx, 1), false_rtx))
6425 term1 = false_rtx, true_rtx = XEXP (true_rtx, 0), false_rtx = const0_rtx;
6426 else if (GET_CODE (false_rtx) == IOR
6427 && rtx_equal_p (XEXP (false_rtx, 0), true_rtx))
6428 term1 = true_rtx, false_rtx = XEXP (false_rtx, 1), true_rtx = const0_rtx;
6429 else if (GET_CODE (false_rtx) == IOR
6430 && rtx_equal_p (XEXP (false_rtx, 1), true_rtx))
6431 term1 = true_rtx, false_rtx = XEXP (false_rtx, 0), true_rtx = const0_rtx;
6433 term2 = simplify_gen_binary (AND, GET_MODE (src),
6434 XEXP (XEXP (src, 0), 0), true_rtx);
6435 term3 = simplify_gen_binary (AND, GET_MODE (src),
6436 simplify_gen_unary (NOT, GET_MODE (src),
6437 XEXP (XEXP (src, 0), 0),
6442 simplify_gen_binary (IOR, GET_MODE (src),
6443 simplify_gen_binary (IOR, GET_MODE (src),
6450 /* If either SRC or DEST is a CLOBBER of (const_int 0), make this
6451 whole thing fail. */
6452 if (GET_CODE (src) == CLOBBER && XEXP (src, 0) == const0_rtx)
6454 else if (GET_CODE (dest) == CLOBBER && XEXP (dest, 0) == const0_rtx)
6457 /* Convert this into a field assignment operation, if possible. */
6458 return make_field_assignment (x);
6461 /* Simplify, X, and AND, IOR, or XOR operation, and return the simplified
6465 simplify_logical (rtx x)
6467 enum machine_mode mode = GET_MODE (x);
6468 rtx op0 = XEXP (x, 0);
6469 rtx op1 = XEXP (x, 1);
6471 switch (GET_CODE (x))
6474 /* We can call simplify_and_const_int only if we don't lose
6475 any (sign) bits when converting INTVAL (op1) to
6476 "unsigned HOST_WIDE_INT". */
6477 if (CONST_INT_P (op1)
6478 && (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
6479 || INTVAL (op1) > 0))
6481 x = simplify_and_const_int (x, mode, op0, INTVAL (op1));
6482 if (GET_CODE (x) != AND)
6489 /* If we have any of (and (ior A B) C) or (and (xor A B) C),
6490 apply the distributive law and then the inverse distributive
6491 law to see if things simplify. */
6492 if (GET_CODE (op0) == IOR || GET_CODE (op0) == XOR)
6494 rtx result = distribute_and_simplify_rtx (x, 0);
6498 if (GET_CODE (op1) == IOR || GET_CODE (op1) == XOR)
6500 rtx result = distribute_and_simplify_rtx (x, 1);
6507 /* If we have (ior (and A B) C), apply the distributive law and then
6508 the inverse distributive law to see if things simplify. */
6510 if (GET_CODE (op0) == AND)
6512 rtx result = distribute_and_simplify_rtx (x, 0);
6517 if (GET_CODE (op1) == AND)
6519 rtx result = distribute_and_simplify_rtx (x, 1);
6532 /* We consider ZERO_EXTRACT, SIGN_EXTRACT, and SIGN_EXTEND as "compound
6533 operations" because they can be replaced with two more basic operations.
6534 ZERO_EXTEND is also considered "compound" because it can be replaced with
6535 an AND operation, which is simpler, though only one operation.
6537 The function expand_compound_operation is called with an rtx expression
6538 and will convert it to the appropriate shifts and AND operations,
6539 simplifying at each stage.
6541 The function make_compound_operation is called to convert an expression
6542 consisting of shifts and ANDs into the equivalent compound expression.
6543 It is the inverse of this function, loosely speaking. */
6546 expand_compound_operation (rtx x)
6548 unsigned HOST_WIDE_INT pos = 0, len;
6550 unsigned int modewidth;
6553 switch (GET_CODE (x))
6558 /* We can't necessarily use a const_int for a multiword mode;
6559 it depends on implicitly extending the value.
6560 Since we don't know the right way to extend it,
6561 we can't tell whether the implicit way is right.
6563 Even for a mode that is no wider than a const_int,
6564 we can't win, because we need to sign extend one of its bits through
6565 the rest of it, and we don't know which bit. */
6566 if (CONST_INT_P (XEXP (x, 0)))
6569 /* Return if (subreg:MODE FROM 0) is not a safe replacement for
6570 (zero_extend:MODE FROM) or (sign_extend:MODE FROM). It is for any MEM
6571 because (SUBREG (MEM...)) is guaranteed to cause the MEM to be
6572 reloaded. If not for that, MEM's would very rarely be safe.
6574 Reject MODEs bigger than a word, because we might not be able
6575 to reference a two-register group starting with an arbitrary register
6576 (and currently gen_lowpart might crash for a SUBREG). */
6578 if (GET_MODE_SIZE (GET_MODE (XEXP (x, 0))) > UNITS_PER_WORD)
6581 /* Reject MODEs that aren't scalar integers because turning vector
6582 or complex modes into shifts causes problems. */
6584 if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x, 0))))
6587 len = GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)));
6588 /* If the inner object has VOIDmode (the only way this can happen
6589 is if it is an ASM_OPERANDS), we can't do anything since we don't
6590 know how much masking to do. */
6599 /* ... fall through ... */
6602 /* If the operand is a CLOBBER, just return it. */
6603 if (GET_CODE (XEXP (x, 0)) == CLOBBER)
6606 if (!CONST_INT_P (XEXP (x, 1))
6607 || !CONST_INT_P (XEXP (x, 2))
6608 || GET_MODE (XEXP (x, 0)) == VOIDmode)
6611 /* Reject MODEs that aren't scalar integers because turning vector
6612 or complex modes into shifts causes problems. */
6614 if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x, 0))))
6617 len = INTVAL (XEXP (x, 1));
6618 pos = INTVAL (XEXP (x, 2));
6620 /* This should stay within the object being extracted, fail otherwise. */
6621 if (len + pos > GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))))
6624 if (BITS_BIG_ENDIAN)
6625 pos = GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - len - pos;
6632 /* Convert sign extension to zero extension, if we know that the high
6633 bit is not set, as this is easier to optimize. It will be converted
6634 back to cheaper alternative in make_extraction. */
6635 if (GET_CODE (x) == SIGN_EXTEND
6636 && (GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
6637 && ((nonzero_bits (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
6638 & ~(((unsigned HOST_WIDE_INT)
6639 GET_MODE_MASK (GET_MODE (XEXP (x, 0))))
6643 rtx temp = gen_rtx_ZERO_EXTEND (GET_MODE (x), XEXP (x, 0));
6644 rtx temp2 = expand_compound_operation (temp);
6646 /* Make sure this is a profitable operation. */
6647 if (rtx_cost (x, SET, optimize_this_for_speed_p)
6648 > rtx_cost (temp2, SET, optimize_this_for_speed_p))
6650 else if (rtx_cost (x, SET, optimize_this_for_speed_p)
6651 > rtx_cost (temp, SET, optimize_this_for_speed_p))
6657 /* We can optimize some special cases of ZERO_EXTEND. */
6658 if (GET_CODE (x) == ZERO_EXTEND)
6660 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI if we
6661 know that the last value didn't have any inappropriate bits
6663 if (GET_CODE (XEXP (x, 0)) == TRUNCATE
6664 && GET_MODE (XEXP (XEXP (x, 0), 0)) == GET_MODE (x)
6665 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
6666 && (nonzero_bits (XEXP (XEXP (x, 0), 0), GET_MODE (x))
6667 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
6668 return XEXP (XEXP (x, 0), 0);
6670 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
6671 if (GET_CODE (XEXP (x, 0)) == SUBREG
6672 && GET_MODE (SUBREG_REG (XEXP (x, 0))) == GET_MODE (x)
6673 && subreg_lowpart_p (XEXP (x, 0))
6674 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
6675 && (nonzero_bits (SUBREG_REG (XEXP (x, 0)), GET_MODE (x))
6676 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
6677 return SUBREG_REG (XEXP (x, 0));
6679 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI when foo
6680 is a comparison and STORE_FLAG_VALUE permits. This is like
6681 the first case, but it works even when GET_MODE (x) is larger
6682 than HOST_WIDE_INT. */
6683 if (GET_CODE (XEXP (x, 0)) == TRUNCATE
6684 && GET_MODE (XEXP (XEXP (x, 0), 0)) == GET_MODE (x)
6685 && COMPARISON_P (XEXP (XEXP (x, 0), 0))
6686 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
6687 <= HOST_BITS_PER_WIDE_INT)
6688 && ((HOST_WIDE_INT) STORE_FLAG_VALUE
6689 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
6690 return XEXP (XEXP (x, 0), 0);
6692 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
6693 if (GET_CODE (XEXP (x, 0)) == SUBREG
6694 && GET_MODE (SUBREG_REG (XEXP (x, 0))) == GET_MODE (x)
6695 && subreg_lowpart_p (XEXP (x, 0))
6696 && COMPARISON_P (SUBREG_REG (XEXP (x, 0)))
6697 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
6698 <= HOST_BITS_PER_WIDE_INT)
6699 && ((HOST_WIDE_INT) STORE_FLAG_VALUE
6700 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
6701 return SUBREG_REG (XEXP (x, 0));
6705 /* If we reach here, we want to return a pair of shifts. The inner
6706 shift is a left shift of BITSIZE - POS - LEN bits. The outer
6707 shift is a right shift of BITSIZE - LEN bits. It is arithmetic or
6708 logical depending on the value of UNSIGNEDP.
6710 If this was a ZERO_EXTEND or ZERO_EXTRACT, this pair of shifts will be
6711 converted into an AND of a shift.
6713 We must check for the case where the left shift would have a negative
6714 count. This can happen in a case like (x >> 31) & 255 on machines
6715 that can't shift by a constant. On those machines, we would first
6716 combine the shift with the AND to produce a variable-position
6717 extraction. Then the constant of 31 would be substituted in to produce
6718 a such a position. */
6720 modewidth = GET_MODE_BITSIZE (GET_MODE (x));
6721 if (modewidth + len >= pos)
6723 enum machine_mode mode = GET_MODE (x);
6724 tem = gen_lowpart (mode, XEXP (x, 0));
6725 if (!tem || GET_CODE (tem) == CLOBBER)
6727 tem = simplify_shift_const (NULL_RTX, ASHIFT, mode,
6728 tem, modewidth - pos - len);
6729 tem = simplify_shift_const (NULL_RTX, unsignedp ? LSHIFTRT : ASHIFTRT,
6730 mode, tem, modewidth - len);
6732 else if (unsignedp && len < HOST_BITS_PER_WIDE_INT)
6733 tem = simplify_and_const_int (NULL_RTX, GET_MODE (x),
6734 simplify_shift_const (NULL_RTX, LSHIFTRT,
6737 ((HOST_WIDE_INT) 1 << len) - 1);
6739 /* Any other cases we can't handle. */
6742 /* If we couldn't do this for some reason, return the original
6744 if (GET_CODE (tem) == CLOBBER)
6750 /* X is a SET which contains an assignment of one object into
6751 a part of another (such as a bit-field assignment, STRICT_LOW_PART,
6752 or certain SUBREGS). If possible, convert it into a series of
6755 We half-heartedly support variable positions, but do not at all
6756 support variable lengths. */
6759 expand_field_assignment (const_rtx x)
6762 rtx pos; /* Always counts from low bit. */
6764 rtx mask, cleared, masked;
6765 enum machine_mode compute_mode;
6767 /* Loop until we find something we can't simplify. */
6770 if (GET_CODE (SET_DEST (x)) == STRICT_LOW_PART
6771 && GET_CODE (XEXP (SET_DEST (x), 0)) == SUBREG)
6773 inner = SUBREG_REG (XEXP (SET_DEST (x), 0));
6774 len = GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0)));
6775 pos = GEN_INT (subreg_lsb (XEXP (SET_DEST (x), 0)));
6777 else if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
6778 && CONST_INT_P (XEXP (SET_DEST (x), 1)))
6780 inner = XEXP (SET_DEST (x), 0);
6781 len = INTVAL (XEXP (SET_DEST (x), 1));
6782 pos = XEXP (SET_DEST (x), 2);
6784 /* A constant position should stay within the width of INNER. */
6785 if (CONST_INT_P (pos)
6786 && INTVAL (pos) + len > GET_MODE_BITSIZE (GET_MODE (inner)))
6789 if (BITS_BIG_ENDIAN)
6791 if (CONST_INT_P (pos))
6792 pos = GEN_INT (GET_MODE_BITSIZE (GET_MODE (inner)) - len
6794 else if (GET_CODE (pos) == MINUS
6795 && CONST_INT_P (XEXP (pos, 1))
6796 && (INTVAL (XEXP (pos, 1))
6797 == GET_MODE_BITSIZE (GET_MODE (inner)) - len))
6798 /* If position is ADJUST - X, new position is X. */
6799 pos = XEXP (pos, 0);
6801 pos = simplify_gen_binary (MINUS, GET_MODE (pos),
6802 GEN_INT (GET_MODE_BITSIZE (
6809 /* A SUBREG between two modes that occupy the same numbers of words
6810 can be done by moving the SUBREG to the source. */
6811 else if (GET_CODE (SET_DEST (x)) == SUBREG
6812 /* We need SUBREGs to compute nonzero_bits properly. */
6813 && nonzero_sign_valid
6814 && (((GET_MODE_SIZE (GET_MODE (SET_DEST (x)))
6815 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
6816 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x))))
6817 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)))
6819 x = gen_rtx_SET (VOIDmode, SUBREG_REG (SET_DEST (x)),
6821 (GET_MODE (SUBREG_REG (SET_DEST (x))),
6828 while (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
6829 inner = SUBREG_REG (inner);
6831 compute_mode = GET_MODE (inner);
6833 /* Don't attempt bitwise arithmetic on non scalar integer modes. */
6834 if (! SCALAR_INT_MODE_P (compute_mode))
6836 enum machine_mode imode;
6838 /* Don't do anything for vector or complex integral types. */
6839 if (! FLOAT_MODE_P (compute_mode))
6842 /* Try to find an integral mode to pun with. */
6843 imode = mode_for_size (GET_MODE_BITSIZE (compute_mode), MODE_INT, 0);
6844 if (imode == BLKmode)
6847 compute_mode = imode;
6848 inner = gen_lowpart (imode, inner);
6851 /* Compute a mask of LEN bits, if we can do this on the host machine. */
6852 if (len >= HOST_BITS_PER_WIDE_INT)
6855 /* Now compute the equivalent expression. Make a copy of INNER
6856 for the SET_DEST in case it is a MEM into which we will substitute;
6857 we don't want shared RTL in that case. */
6858 mask = GEN_INT (((HOST_WIDE_INT) 1 << len) - 1);
6859 cleared = simplify_gen_binary (AND, compute_mode,
6860 simplify_gen_unary (NOT, compute_mode,
6861 simplify_gen_binary (ASHIFT,
6866 masked = simplify_gen_binary (ASHIFT, compute_mode,
6867 simplify_gen_binary (
6869 gen_lowpart (compute_mode, SET_SRC (x)),
6873 x = gen_rtx_SET (VOIDmode, copy_rtx (inner),
6874 simplify_gen_binary (IOR, compute_mode,
6881 /* Return an RTX for a reference to LEN bits of INNER. If POS_RTX is nonzero,
6882 it is an RTX that represents a variable starting position; otherwise,
6883 POS is the (constant) starting bit position (counted from the LSB).
6885 UNSIGNEDP is nonzero for an unsigned reference and zero for a
6888 IN_DEST is nonzero if this is a reference in the destination of a
6889 SET. This is used when a ZERO_ or SIGN_EXTRACT isn't needed. If nonzero,
6890 a STRICT_LOW_PART will be used, if zero, ZERO_EXTEND or SIGN_EXTEND will
6893 IN_COMPARE is nonzero if we are in a COMPARE. This means that a
6894 ZERO_EXTRACT should be built even for bits starting at bit 0.
6896 MODE is the desired mode of the result (if IN_DEST == 0).
6898 The result is an RTX for the extraction or NULL_RTX if the target
6902 make_extraction (enum machine_mode mode, rtx inner, HOST_WIDE_INT pos,
6903 rtx pos_rtx, unsigned HOST_WIDE_INT len, int unsignedp,
6904 int in_dest, int in_compare)
6906 /* This mode describes the size of the storage area
6907 to fetch the overall value from. Within that, we
6908 ignore the POS lowest bits, etc. */
6909 enum machine_mode is_mode = GET_MODE (inner);
6910 enum machine_mode inner_mode;
6911 enum machine_mode wanted_inner_mode;
6912 enum machine_mode wanted_inner_reg_mode = word_mode;
6913 enum machine_mode pos_mode = word_mode;
6914 enum machine_mode extraction_mode = word_mode;
6915 enum machine_mode tmode = mode_for_size (len, MODE_INT, 1);
6917 rtx orig_pos_rtx = pos_rtx;
6918 HOST_WIDE_INT orig_pos;
6920 if (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
6922 /* If going from (subreg:SI (mem:QI ...)) to (mem:QI ...),
6923 consider just the QI as the memory to extract from.
6924 The subreg adds or removes high bits; its mode is
6925 irrelevant to the meaning of this extraction,
6926 since POS and LEN count from the lsb. */
6927 if (MEM_P (SUBREG_REG (inner)))
6928 is_mode = GET_MODE (SUBREG_REG (inner));
6929 inner = SUBREG_REG (inner);
6931 else if (GET_CODE (inner) == ASHIFT
6932 && CONST_INT_P (XEXP (inner, 1))
6933 && pos_rtx == 0 && pos == 0
6934 && len > (unsigned HOST_WIDE_INT) INTVAL (XEXP (inner, 1)))
6936 /* We're extracting the least significant bits of an rtx
6937 (ashift X (const_int C)), where LEN > C. Extract the
6938 least significant (LEN - C) bits of X, giving an rtx
6939 whose mode is MODE, then shift it left C times. */
6940 new_rtx = make_extraction (mode, XEXP (inner, 0),
6941 0, 0, len - INTVAL (XEXP (inner, 1)),
6942 unsignedp, in_dest, in_compare);
6944 return gen_rtx_ASHIFT (mode, new_rtx, XEXP (inner, 1));
6947 inner_mode = GET_MODE (inner);
6949 if (pos_rtx && CONST_INT_P (pos_rtx))
6950 pos = INTVAL (pos_rtx), pos_rtx = 0;
6952 /* See if this can be done without an extraction. We never can if the
6953 width of the field is not the same as that of some integer mode. For
6954 registers, we can only avoid the extraction if the position is at the
6955 low-order bit and this is either not in the destination or we have the
6956 appropriate STRICT_LOW_PART operation available.
6958 For MEM, we can avoid an extract if the field starts on an appropriate
6959 boundary and we can change the mode of the memory reference. */
6961 if (tmode != BLKmode
6962 && ((pos_rtx == 0 && (pos % BITS_PER_WORD) == 0
6964 && (inner_mode == tmode
6966 || TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (tmode),
6967 GET_MODE_BITSIZE (inner_mode))
6968 || reg_truncated_to_mode (tmode, inner))
6971 && have_insn_for (STRICT_LOW_PART, tmode))))
6972 || (MEM_P (inner) && pos_rtx == 0
6974 % (STRICT_ALIGNMENT ? GET_MODE_ALIGNMENT (tmode)
6975 : BITS_PER_UNIT)) == 0
6976 /* We can't do this if we are widening INNER_MODE (it
6977 may not be aligned, for one thing). */
6978 && GET_MODE_BITSIZE (inner_mode) >= GET_MODE_BITSIZE (tmode)
6979 && (inner_mode == tmode
6980 || (! mode_dependent_address_p (XEXP (inner, 0))
6981 && ! MEM_VOLATILE_P (inner))))))
6983 /* If INNER is a MEM, make a new MEM that encompasses just the desired
6984 field. If the original and current mode are the same, we need not
6985 adjust the offset. Otherwise, we do if bytes big endian.
6987 If INNER is not a MEM, get a piece consisting of just the field
6988 of interest (in this case POS % BITS_PER_WORD must be 0). */
6992 HOST_WIDE_INT offset;
6994 /* POS counts from lsb, but make OFFSET count in memory order. */
6995 if (BYTES_BIG_ENDIAN)
6996 offset = (GET_MODE_BITSIZE (is_mode) - len - pos) / BITS_PER_UNIT;
6998 offset = pos / BITS_PER_UNIT;
7000 new_rtx = adjust_address_nv (inner, tmode, offset);
7002 else if (REG_P (inner))
7004 if (tmode != inner_mode)
7006 /* We can't call gen_lowpart in a DEST since we
7007 always want a SUBREG (see below) and it would sometimes
7008 return a new hard register. */
7011 HOST_WIDE_INT final_word = pos / BITS_PER_WORD;
7013 if (WORDS_BIG_ENDIAN
7014 && GET_MODE_SIZE (inner_mode) > UNITS_PER_WORD)
7015 final_word = ((GET_MODE_SIZE (inner_mode)
7016 - GET_MODE_SIZE (tmode))
7017 / UNITS_PER_WORD) - final_word;
7019 final_word *= UNITS_PER_WORD;
7020 if (BYTES_BIG_ENDIAN &&
7021 GET_MODE_SIZE (inner_mode) > GET_MODE_SIZE (tmode))
7022 final_word += (GET_MODE_SIZE (inner_mode)
7023 - GET_MODE_SIZE (tmode)) % UNITS_PER_WORD;
7025 /* Avoid creating invalid subregs, for example when
7026 simplifying (x>>32)&255. */
7027 if (!validate_subreg (tmode, inner_mode, inner, final_word))
7030 new_rtx = gen_rtx_SUBREG (tmode, inner, final_word);
7033 new_rtx = gen_lowpart (tmode, inner);
7039 new_rtx = force_to_mode (inner, tmode,
7040 len >= HOST_BITS_PER_WIDE_INT
7041 ? ~(unsigned HOST_WIDE_INT) 0
7042 : ((unsigned HOST_WIDE_INT) 1 << len) - 1,
7045 /* If this extraction is going into the destination of a SET,
7046 make a STRICT_LOW_PART unless we made a MEM. */
7049 return (MEM_P (new_rtx) ? new_rtx
7050 : (GET_CODE (new_rtx) != SUBREG
7051 ? gen_rtx_CLOBBER (tmode, const0_rtx)
7052 : gen_rtx_STRICT_LOW_PART (VOIDmode, new_rtx)));
7057 if (CONST_INT_P (new_rtx)
7058 || GET_CODE (new_rtx) == CONST_DOUBLE)
7059 return simplify_unary_operation (unsignedp ? ZERO_EXTEND : SIGN_EXTEND,
7060 mode, new_rtx, tmode);
7062 /* If we know that no extraneous bits are set, and that the high
7063 bit is not set, convert the extraction to the cheaper of
7064 sign and zero extension, that are equivalent in these cases. */
7065 if (flag_expensive_optimizations
7066 && (GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT
7067 && ((nonzero_bits (new_rtx, tmode)
7068 & ~(((unsigned HOST_WIDE_INT)
7069 GET_MODE_MASK (tmode))
7073 rtx temp = gen_rtx_ZERO_EXTEND (mode, new_rtx);
7074 rtx temp1 = gen_rtx_SIGN_EXTEND (mode, new_rtx);
7076 /* Prefer ZERO_EXTENSION, since it gives more information to
7078 if (rtx_cost (temp, SET, optimize_this_for_speed_p)
7079 <= rtx_cost (temp1, SET, optimize_this_for_speed_p))
7084 /* Otherwise, sign- or zero-extend unless we already are in the
7087 return (gen_rtx_fmt_e (unsignedp ? ZERO_EXTEND : SIGN_EXTEND,
7091 /* Unless this is a COMPARE or we have a funny memory reference,
7092 don't do anything with zero-extending field extracts starting at
7093 the low-order bit since they are simple AND operations. */
7094 if (pos_rtx == 0 && pos == 0 && ! in_dest
7095 && ! in_compare && unsignedp)
7098 /* Unless INNER is not MEM, reject this if we would be spanning bytes or
7099 if the position is not a constant and the length is not 1. In all
7100 other cases, we would only be going outside our object in cases when
7101 an original shift would have been undefined. */
7103 && ((pos_rtx == 0 && pos + len > GET_MODE_BITSIZE (is_mode))
7104 || (pos_rtx != 0 && len != 1)))
7107 /* Get the mode to use should INNER not be a MEM, the mode for the position,
7108 and the mode for the result. */
7109 if (in_dest && mode_for_extraction (EP_insv, -1) != MAX_MACHINE_MODE)
7111 wanted_inner_reg_mode = mode_for_extraction (EP_insv, 0);
7112 pos_mode = mode_for_extraction (EP_insv, 2);
7113 extraction_mode = mode_for_extraction (EP_insv, 3);
7116 if (! in_dest && unsignedp
7117 && mode_for_extraction (EP_extzv, -1) != MAX_MACHINE_MODE)
7119 wanted_inner_reg_mode = mode_for_extraction (EP_extzv, 1);
7120 pos_mode = mode_for_extraction (EP_extzv, 3);
7121 extraction_mode = mode_for_extraction (EP_extzv, 0);
7124 if (! in_dest && ! unsignedp
7125 && mode_for_extraction (EP_extv, -1) != MAX_MACHINE_MODE)
7127 wanted_inner_reg_mode = mode_for_extraction (EP_extv, 1);
7128 pos_mode = mode_for_extraction (EP_extv, 3);
7129 extraction_mode = mode_for_extraction (EP_extv, 0);
7132 /* Never narrow an object, since that might not be safe. */
7134 if (mode != VOIDmode
7135 && GET_MODE_SIZE (extraction_mode) < GET_MODE_SIZE (mode))
7136 extraction_mode = mode;
7138 if (pos_rtx && GET_MODE (pos_rtx) != VOIDmode
7139 && GET_MODE_SIZE (pos_mode) < GET_MODE_SIZE (GET_MODE (pos_rtx)))
7140 pos_mode = GET_MODE (pos_rtx);
7142 /* If this is not from memory, the desired mode is the preferred mode
7143 for an extraction pattern's first input operand, or word_mode if there
7146 wanted_inner_mode = wanted_inner_reg_mode;
7149 /* Be careful not to go beyond the extracted object and maintain the
7150 natural alignment of the memory. */
7151 wanted_inner_mode = smallest_mode_for_size (len, MODE_INT);
7152 while (pos % GET_MODE_BITSIZE (wanted_inner_mode) + len
7153 > GET_MODE_BITSIZE (wanted_inner_mode))
7155 wanted_inner_mode = GET_MODE_WIDER_MODE (wanted_inner_mode);
7156 gcc_assert (wanted_inner_mode != VOIDmode);
7159 /* If we have to change the mode of memory and cannot, the desired mode
7160 is EXTRACTION_MODE. */
7161 if (inner_mode != wanted_inner_mode
7162 && (mode_dependent_address_p (XEXP (inner, 0))
7163 || MEM_VOLATILE_P (inner)
7165 wanted_inner_mode = extraction_mode;
7170 if (BITS_BIG_ENDIAN)
7172 /* POS is passed as if BITS_BIG_ENDIAN == 0, so we need to convert it to
7173 BITS_BIG_ENDIAN style. If position is constant, compute new
7174 position. Otherwise, build subtraction.
7175 Note that POS is relative to the mode of the original argument.
7176 If it's a MEM we need to recompute POS relative to that.
7177 However, if we're extracting from (or inserting into) a register,
7178 we want to recompute POS relative to wanted_inner_mode. */
7179 int width = (MEM_P (inner)
7180 ? GET_MODE_BITSIZE (is_mode)
7181 : GET_MODE_BITSIZE (wanted_inner_mode));
7184 pos = width - len - pos;
7187 = gen_rtx_MINUS (GET_MODE (pos_rtx), GEN_INT (width - len), pos_rtx);
7188 /* POS may be less than 0 now, but we check for that below.
7189 Note that it can only be less than 0 if !MEM_P (inner). */
7192 /* If INNER has a wider mode, and this is a constant extraction, try to
7193 make it smaller and adjust the byte to point to the byte containing
7195 if (wanted_inner_mode != VOIDmode
7196 && inner_mode != wanted_inner_mode
7198 && GET_MODE_SIZE (wanted_inner_mode) < GET_MODE_SIZE (is_mode)
7200 && ! mode_dependent_address_p (XEXP (inner, 0))
7201 && ! MEM_VOLATILE_P (inner))
7205 /* The computations below will be correct if the machine is big
7206 endian in both bits and bytes or little endian in bits and bytes.
7207 If it is mixed, we must adjust. */
7209 /* If bytes are big endian and we had a paradoxical SUBREG, we must
7210 adjust OFFSET to compensate. */
7211 if (BYTES_BIG_ENDIAN
7212 && GET_MODE_SIZE (inner_mode) < GET_MODE_SIZE (is_mode))
7213 offset -= GET_MODE_SIZE (is_mode) - GET_MODE_SIZE (inner_mode);
7215 /* We can now move to the desired byte. */
7216 offset += (pos / GET_MODE_BITSIZE (wanted_inner_mode))
7217 * GET_MODE_SIZE (wanted_inner_mode);
7218 pos %= GET_MODE_BITSIZE (wanted_inner_mode);
7220 if (BYTES_BIG_ENDIAN != BITS_BIG_ENDIAN
7221 && is_mode != wanted_inner_mode)
7222 offset = (GET_MODE_SIZE (is_mode)
7223 - GET_MODE_SIZE (wanted_inner_mode) - offset);
7225 inner = adjust_address_nv (inner, wanted_inner_mode, offset);
7228 /* If INNER is not memory, get it into the proper mode. If we are changing
7229 its mode, POS must be a constant and smaller than the size of the new
7231 else if (!MEM_P (inner))
7233 /* On the LHS, don't create paradoxical subregs implicitely truncating
7234 the register unless TRULY_NOOP_TRUNCATION. */
7236 && !TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (GET_MODE (inner)),
7237 GET_MODE_BITSIZE (wanted_inner_mode)))
7240 if (GET_MODE (inner) != wanted_inner_mode
7242 || orig_pos + len > GET_MODE_BITSIZE (wanted_inner_mode)))
7248 inner = force_to_mode (inner, wanted_inner_mode,
7250 || len + orig_pos >= HOST_BITS_PER_WIDE_INT
7251 ? ~(unsigned HOST_WIDE_INT) 0
7252 : ((((unsigned HOST_WIDE_INT) 1 << len) - 1)
7257 /* Adjust mode of POS_RTX, if needed. If we want a wider mode, we
7258 have to zero extend. Otherwise, we can just use a SUBREG. */
7260 && GET_MODE_SIZE (pos_mode) > GET_MODE_SIZE (GET_MODE (pos_rtx)))
7262 rtx temp = gen_rtx_ZERO_EXTEND (pos_mode, pos_rtx);
7264 /* If we know that no extraneous bits are set, and that the high
7265 bit is not set, convert extraction to cheaper one - either
7266 SIGN_EXTENSION or ZERO_EXTENSION, that are equivalent in these
7268 if (flag_expensive_optimizations
7269 && (GET_MODE_BITSIZE (GET_MODE (pos_rtx)) <= HOST_BITS_PER_WIDE_INT
7270 && ((nonzero_bits (pos_rtx, GET_MODE (pos_rtx))
7271 & ~(((unsigned HOST_WIDE_INT)
7272 GET_MODE_MASK (GET_MODE (pos_rtx)))
7276 rtx temp1 = gen_rtx_SIGN_EXTEND (pos_mode, pos_rtx);
7278 /* Prefer ZERO_EXTENSION, since it gives more information to
7280 if (rtx_cost (temp1, SET, optimize_this_for_speed_p)
7281 < rtx_cost (temp, SET, optimize_this_for_speed_p))
7286 else if (pos_rtx != 0
7287 && GET_MODE_SIZE (pos_mode) < GET_MODE_SIZE (GET_MODE (pos_rtx)))
7288 pos_rtx = gen_lowpart (pos_mode, pos_rtx);
7290 /* Make POS_RTX unless we already have it and it is correct. If we don't
7291 have a POS_RTX but we do have an ORIG_POS_RTX, the latter must
7293 if (pos_rtx == 0 && orig_pos_rtx != 0 && INTVAL (orig_pos_rtx) == pos)
7294 pos_rtx = orig_pos_rtx;
7296 else if (pos_rtx == 0)
7297 pos_rtx = GEN_INT (pos);
7299 /* Make the required operation. See if we can use existing rtx. */
7300 new_rtx = gen_rtx_fmt_eee (unsignedp ? ZERO_EXTRACT : SIGN_EXTRACT,
7301 extraction_mode, inner, GEN_INT (len), pos_rtx);
7303 new_rtx = gen_lowpart (mode, new_rtx);
7308 /* See if X contains an ASHIFT of COUNT or more bits that can be commuted
7309 with any other operations in X. Return X without that shift if so. */
7312 extract_left_shift (rtx x, int count)
7314 enum rtx_code code = GET_CODE (x);
7315 enum machine_mode mode = GET_MODE (x);
7321 /* This is the shift itself. If it is wide enough, we will return
7322 either the value being shifted if the shift count is equal to
7323 COUNT or a shift for the difference. */
7324 if (CONST_INT_P (XEXP (x, 1))
7325 && INTVAL (XEXP (x, 1)) >= count)
7326 return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (x, 0),
7327 INTVAL (XEXP (x, 1)) - count);
7331 if ((tem = extract_left_shift (XEXP (x, 0), count)) != 0)
7332 return simplify_gen_unary (code, mode, tem, mode);
7336 case PLUS: case IOR: case XOR: case AND:
7337 /* If we can safely shift this constant and we find the inner shift,
7338 make a new operation. */
7339 if (CONST_INT_P (XEXP (x, 1))
7340 && (INTVAL (XEXP (x, 1)) & ((((HOST_WIDE_INT) 1 << count)) - 1)) == 0
7341 && (tem = extract_left_shift (XEXP (x, 0), count)) != 0)
7342 return simplify_gen_binary (code, mode, tem,
7343 GEN_INT (INTVAL (XEXP (x, 1)) >> count));
7354 /* Look at the expression rooted at X. Look for expressions
7355 equivalent to ZERO_EXTRACT, SIGN_EXTRACT, ZERO_EXTEND, SIGN_EXTEND.
7356 Form these expressions.
7358 Return the new rtx, usually just X.
7360 Also, for machines like the VAX that don't have logical shift insns,
7361 try to convert logical to arithmetic shift operations in cases where
7362 they are equivalent. This undoes the canonicalizations to logical
7363 shifts done elsewhere.
7365 We try, as much as possible, to re-use rtl expressions to save memory.
7367 IN_CODE says what kind of expression we are processing. Normally, it is
7368 SET. In a memory address (inside a MEM, PLUS or minus, the latter two
7369 being kludges), it is MEM. When processing the arguments of a comparison
7370 or a COMPARE against zero, it is COMPARE. */
7373 make_compound_operation (rtx x, enum rtx_code in_code)
7375 enum rtx_code code = GET_CODE (x);
7376 enum machine_mode mode = GET_MODE (x);
7377 int mode_width = GET_MODE_BITSIZE (mode);
7379 enum rtx_code next_code;
7385 /* Select the code to be used in recursive calls. Once we are inside an
7386 address, we stay there. If we have a comparison, set to COMPARE,
7387 but once inside, go back to our default of SET. */
7389 next_code = (code == MEM ? MEM
7390 : ((code == PLUS || code == MINUS)
7391 && SCALAR_INT_MODE_P (mode)) ? MEM
7392 : ((code == COMPARE || COMPARISON_P (x))
7393 && XEXP (x, 1) == const0_rtx) ? COMPARE
7394 : in_code == COMPARE ? SET : in_code);
7396 /* Process depending on the code of this operation. If NEW is set
7397 nonzero, it will be returned. */
7402 /* Convert shifts by constants into multiplications if inside
7404 if (in_code == MEM && CONST_INT_P (XEXP (x, 1))
7405 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT
7406 && INTVAL (XEXP (x, 1)) >= 0)
7408 HOST_WIDE_INT count = INTVAL (XEXP (x, 1));
7409 HOST_WIDE_INT multval = (HOST_WIDE_INT) 1 << count;
7411 new_rtx = make_compound_operation (XEXP (x, 0), next_code);
7412 if (GET_CODE (new_rtx) == NEG)
7414 new_rtx = XEXP (new_rtx, 0);
7417 multval = trunc_int_for_mode (multval, mode);
7418 new_rtx = gen_rtx_MULT (mode, new_rtx, GEN_INT (multval));
7425 lhs = make_compound_operation (lhs, next_code);
7426 rhs = make_compound_operation (rhs, next_code);
7427 if (GET_CODE (lhs) == MULT && GET_CODE (XEXP (lhs, 0)) == NEG
7428 && SCALAR_INT_MODE_P (mode))
7430 tem = simplify_gen_binary (MULT, mode, XEXP (XEXP (lhs, 0), 0),
7432 new_rtx = simplify_gen_binary (MINUS, mode, rhs, tem);
7434 else if (GET_CODE (lhs) == MULT
7435 && (CONST_INT_P (XEXP (lhs, 1)) && INTVAL (XEXP (lhs, 1)) < 0))
7437 tem = simplify_gen_binary (MULT, mode, XEXP (lhs, 0),
7438 simplify_gen_unary (NEG, mode,
7441 new_rtx = simplify_gen_binary (MINUS, mode, rhs, tem);
7445 SUBST (XEXP (x, 0), lhs);
7446 SUBST (XEXP (x, 1), rhs);
7449 x = gen_lowpart (mode, new_rtx);
7455 lhs = make_compound_operation (lhs, next_code);
7456 rhs = make_compound_operation (rhs, next_code);
7457 if (GET_CODE (rhs) == MULT && GET_CODE (XEXP (rhs, 0)) == NEG
7458 && SCALAR_INT_MODE_P (mode))
7460 tem = simplify_gen_binary (MULT, mode, XEXP (XEXP (rhs, 0), 0),
7462 new_rtx = simplify_gen_binary (PLUS, mode, tem, lhs);
7464 else if (GET_CODE (rhs) == MULT
7465 && (CONST_INT_P (XEXP (rhs, 1)) && INTVAL (XEXP (rhs, 1)) < 0))
7467 tem = simplify_gen_binary (MULT, mode, XEXP (rhs, 0),
7468 simplify_gen_unary (NEG, mode,
7471 new_rtx = simplify_gen_binary (PLUS, mode, tem, lhs);
7475 SUBST (XEXP (x, 0), lhs);
7476 SUBST (XEXP (x, 1), rhs);
7479 return gen_lowpart (mode, new_rtx);
7482 /* If the second operand is not a constant, we can't do anything
7484 if (!CONST_INT_P (XEXP (x, 1)))
7487 /* If the constant is a power of two minus one and the first operand
7488 is a logical right shift, make an extraction. */
7489 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
7490 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
7492 new_rtx = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code);
7493 new_rtx = make_extraction (mode, new_rtx, 0, XEXP (XEXP (x, 0), 1), i, 1,
7494 0, in_code == COMPARE);
7497 /* Same as previous, but for (subreg (lshiftrt ...)) in first op. */
7498 else if (GET_CODE (XEXP (x, 0)) == SUBREG
7499 && subreg_lowpart_p (XEXP (x, 0))
7500 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == LSHIFTRT
7501 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
7503 new_rtx = make_compound_operation (XEXP (SUBREG_REG (XEXP (x, 0)), 0),
7505 new_rtx = make_extraction (GET_MODE (SUBREG_REG (XEXP (x, 0))), new_rtx, 0,
7506 XEXP (SUBREG_REG (XEXP (x, 0)), 1), i, 1,
7507 0, in_code == COMPARE);
7509 /* Same as previous, but for (xor/ior (lshiftrt...) (lshiftrt...)). */
7510 else if ((GET_CODE (XEXP (x, 0)) == XOR
7511 || GET_CODE (XEXP (x, 0)) == IOR)
7512 && GET_CODE (XEXP (XEXP (x, 0), 0)) == LSHIFTRT
7513 && GET_CODE (XEXP (XEXP (x, 0), 1)) == LSHIFTRT
7514 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
7516 /* Apply the distributive law, and then try to make extractions. */
7517 new_rtx = gen_rtx_fmt_ee (GET_CODE (XEXP (x, 0)), mode,
7518 gen_rtx_AND (mode, XEXP (XEXP (x, 0), 0),
7520 gen_rtx_AND (mode, XEXP (XEXP (x, 0), 1),
7522 new_rtx = make_compound_operation (new_rtx, in_code);
7525 /* If we are have (and (rotate X C) M) and C is larger than the number
7526 of bits in M, this is an extraction. */
7528 else if (GET_CODE (XEXP (x, 0)) == ROTATE
7529 && CONST_INT_P (XEXP (XEXP (x, 0), 1))
7530 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0
7531 && i <= INTVAL (XEXP (XEXP (x, 0), 1)))
7533 new_rtx = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code);
7534 new_rtx = make_extraction (mode, new_rtx,
7535 (GET_MODE_BITSIZE (mode)
7536 - INTVAL (XEXP (XEXP (x, 0), 1))),
7537 NULL_RTX, i, 1, 0, in_code == COMPARE);
7540 /* On machines without logical shifts, if the operand of the AND is
7541 a logical shift and our mask turns off all the propagated sign
7542 bits, we can replace the logical shift with an arithmetic shift. */
7543 else if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
7544 && !have_insn_for (LSHIFTRT, mode)
7545 && have_insn_for (ASHIFTRT, mode)
7546 && CONST_INT_P (XEXP (XEXP (x, 0), 1))
7547 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
7548 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT
7549 && mode_width <= HOST_BITS_PER_WIDE_INT)
7551 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
7553 mask >>= INTVAL (XEXP (XEXP (x, 0), 1));
7554 if ((INTVAL (XEXP (x, 1)) & ~mask) == 0)
7556 gen_rtx_ASHIFTRT (mode,
7557 make_compound_operation
7558 (XEXP (XEXP (x, 0), 0), next_code),
7559 XEXP (XEXP (x, 0), 1)));
7562 /* If the constant is one less than a power of two, this might be
7563 representable by an extraction even if no shift is present.
7564 If it doesn't end up being a ZERO_EXTEND, we will ignore it unless
7565 we are in a COMPARE. */
7566 else if ((i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
7567 new_rtx = make_extraction (mode,
7568 make_compound_operation (XEXP (x, 0),
7570 0, NULL_RTX, i, 1, 0, in_code == COMPARE);
7572 /* If we are in a comparison and this is an AND with a power of two,
7573 convert this into the appropriate bit extract. */
7574 else if (in_code == COMPARE
7575 && (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0)
7576 new_rtx = make_extraction (mode,
7577 make_compound_operation (XEXP (x, 0),
7579 i, NULL_RTX, 1, 1, 0, 1);
7584 /* If the sign bit is known to be zero, replace this with an
7585 arithmetic shift. */
7586 if (have_insn_for (ASHIFTRT, mode)
7587 && ! have_insn_for (LSHIFTRT, mode)
7588 && mode_width <= HOST_BITS_PER_WIDE_INT
7589 && (nonzero_bits (XEXP (x, 0), mode) & (1 << (mode_width - 1))) == 0)
7591 new_rtx = gen_rtx_ASHIFTRT (mode,
7592 make_compound_operation (XEXP (x, 0),
7598 /* ... fall through ... */
7604 /* If we have (ashiftrt (ashift foo C1) C2) with C2 >= C1,
7605 this is a SIGN_EXTRACT. */
7606 if (CONST_INT_P (rhs)
7607 && GET_CODE (lhs) == ASHIFT
7608 && CONST_INT_P (XEXP (lhs, 1))
7609 && INTVAL (rhs) >= INTVAL (XEXP (lhs, 1))
7610 && INTVAL (rhs) < mode_width)
7612 new_rtx = make_compound_operation (XEXP (lhs, 0), next_code);
7613 new_rtx = make_extraction (mode, new_rtx,
7614 INTVAL (rhs) - INTVAL (XEXP (lhs, 1)),
7615 NULL_RTX, mode_width - INTVAL (rhs),
7616 code == LSHIFTRT, 0, in_code == COMPARE);
7620 /* See if we have operations between an ASHIFTRT and an ASHIFT.
7621 If so, try to merge the shifts into a SIGN_EXTEND. We could
7622 also do this for some cases of SIGN_EXTRACT, but it doesn't
7623 seem worth the effort; the case checked for occurs on Alpha. */
7626 && ! (GET_CODE (lhs) == SUBREG
7627 && (OBJECT_P (SUBREG_REG (lhs))))
7628 && CONST_INT_P (rhs)
7629 && INTVAL (rhs) < HOST_BITS_PER_WIDE_INT
7630 && INTVAL (rhs) < mode_width
7631 && (new_rtx = extract_left_shift (lhs, INTVAL (rhs))) != 0)
7632 new_rtx = make_extraction (mode, make_compound_operation (new_rtx, next_code),
7633 0, NULL_RTX, mode_width - INTVAL (rhs),
7634 code == LSHIFTRT, 0, in_code == COMPARE);
7639 /* Call ourselves recursively on the inner expression. If we are
7640 narrowing the object and it has a different RTL code from
7641 what it originally did, do this SUBREG as a force_to_mode. */
7643 rtx inner = SUBREG_REG (x), simplified;
7645 tem = make_compound_operation (inner, in_code);
7648 = simplify_subreg (mode, tem, GET_MODE (inner), SUBREG_BYTE (x));
7652 if (GET_CODE (tem) != GET_CODE (inner)
7653 && GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (inner))
7654 && subreg_lowpart_p (x))
7656 rtx newer = force_to_mode (tem, mode, ~(HOST_WIDE_INT) 0, 0);
7658 /* If we have something other than a SUBREG, we might have
7659 done an expansion, so rerun ourselves. */
7660 if (GET_CODE (newer) != SUBREG)
7661 newer = make_compound_operation (newer, in_code);
7663 /* force_to_mode can expand compounds. If it just re-expanded the
7664 compound, use gen_lowpart to convert to the desired mode. */
7665 if (rtx_equal_p (newer, x)
7666 /* Likewise if it re-expanded the compound only partially.
7667 This happens for SUBREG of ZERO_EXTRACT if they extract
7668 the same number of bits. */
7669 || (GET_CODE (newer) == SUBREG
7670 && (GET_CODE (SUBREG_REG (newer)) == LSHIFTRT
7671 || GET_CODE (SUBREG_REG (newer)) == ASHIFTRT)
7672 && GET_CODE (inner) == AND
7673 && rtx_equal_p (SUBREG_REG (newer), XEXP (inner, 0))))
7674 return gen_lowpart (GET_MODE (x), tem);
7690 x = gen_lowpart (mode, new_rtx);
7691 code = GET_CODE (x);
7694 /* Now recursively process each operand of this operation. */
7695 fmt = GET_RTX_FORMAT (code);
7696 for (i = 0; i < GET_RTX_LENGTH (code); i++)
7699 new_rtx = make_compound_operation (XEXP (x, i), next_code);
7700 SUBST (XEXP (x, i), new_rtx);
7702 else if (fmt[i] == 'E')
7703 for (j = 0; j < XVECLEN (x, i); j++)
7705 new_rtx = make_compound_operation (XVECEXP (x, i, j), next_code);
7706 SUBST (XVECEXP (x, i, j), new_rtx);
7710 /* If this is a commutative operation, the changes to the operands
7711 may have made it noncanonical. */
7712 if (COMMUTATIVE_ARITH_P (x)
7713 && swap_commutative_operands_p (XEXP (x, 0), XEXP (x, 1)))
7716 SUBST (XEXP (x, 0), XEXP (x, 1));
7717 SUBST (XEXP (x, 1), tem);
7723 /* Given M see if it is a value that would select a field of bits
7724 within an item, but not the entire word. Return -1 if not.
7725 Otherwise, return the starting position of the field, where 0 is the
7728 *PLEN is set to the length of the field. */
7731 get_pos_from_mask (unsigned HOST_WIDE_INT m, unsigned HOST_WIDE_INT *plen)
7733 /* Get the bit number of the first 1 bit from the right, -1 if none. */
7734 int pos = m ? ctz_hwi (m) : -1;
7738 /* Now shift off the low-order zero bits and see if we have a
7739 power of two minus 1. */
7740 len = exact_log2 ((m >> pos) + 1);
7749 /* If X refers to a register that equals REG in value, replace these
7750 references with REG. */
7752 canon_reg_for_combine (rtx x, rtx reg)
7759 enum rtx_code code = GET_CODE (x);
7760 switch (GET_RTX_CLASS (code))
7763 op0 = canon_reg_for_combine (XEXP (x, 0), reg);
7764 if (op0 != XEXP (x, 0))
7765 return simplify_gen_unary (GET_CODE (x), GET_MODE (x), op0,
7770 case RTX_COMM_ARITH:
7771 op0 = canon_reg_for_combine (XEXP (x, 0), reg);
7772 op1 = canon_reg_for_combine (XEXP (x, 1), reg);
7773 if (op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
7774 return simplify_gen_binary (GET_CODE (x), GET_MODE (x), op0, op1);
7778 case RTX_COMM_COMPARE:
7779 op0 = canon_reg_for_combine (XEXP (x, 0), reg);
7780 op1 = canon_reg_for_combine (XEXP (x, 1), reg);
7781 if (op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
7782 return simplify_gen_relational (GET_CODE (x), GET_MODE (x),
7783 GET_MODE (op0), op0, op1);
7787 case RTX_BITFIELD_OPS:
7788 op0 = canon_reg_for_combine (XEXP (x, 0), reg);
7789 op1 = canon_reg_for_combine (XEXP (x, 1), reg);
7790 op2 = canon_reg_for_combine (XEXP (x, 2), reg);
7791 if (op0 != XEXP (x, 0) || op1 != XEXP (x, 1) || op2 != XEXP (x, 2))
7792 return simplify_gen_ternary (GET_CODE (x), GET_MODE (x),
7793 GET_MODE (op0), op0, op1, op2);
7798 if (rtx_equal_p (get_last_value (reg), x)
7799 || rtx_equal_p (reg, get_last_value (x)))
7808 fmt = GET_RTX_FORMAT (code);
7810 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
7813 rtx op = canon_reg_for_combine (XEXP (x, i), reg);
7814 if (op != XEXP (x, i))
7824 else if (fmt[i] == 'E')
7827 for (j = 0; j < XVECLEN (x, i); j++)
7829 rtx op = canon_reg_for_combine (XVECEXP (x, i, j), reg);
7830 if (op != XVECEXP (x, i, j))
7837 XVECEXP (x, i, j) = op;
7848 /* Return X converted to MODE. If the value is already truncated to
7849 MODE we can just return a subreg even though in the general case we
7850 would need an explicit truncation. */
7853 gen_lowpart_or_truncate (enum machine_mode mode, rtx x)
7855 if (!CONST_INT_P (x)
7856 && GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (x))
7857 && !TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode),
7858 GET_MODE_BITSIZE (GET_MODE (x)))
7859 && !(REG_P (x) && reg_truncated_to_mode (mode, x)))
7861 /* Bit-cast X into an integer mode. */
7862 if (!SCALAR_INT_MODE_P (GET_MODE (x)))
7863 x = gen_lowpart (int_mode_for_mode (GET_MODE (x)), x);
7864 x = simplify_gen_unary (TRUNCATE, int_mode_for_mode (mode),
7868 return gen_lowpart (mode, x);
7871 /* See if X can be simplified knowing that we will only refer to it in
7872 MODE and will only refer to those bits that are nonzero in MASK.
7873 If other bits are being computed or if masking operations are done
7874 that select a superset of the bits in MASK, they can sometimes be
7877 Return a possibly simplified expression, but always convert X to
7878 MODE. If X is a CONST_INT, AND the CONST_INT with MASK.
7880 If JUST_SELECT is nonzero, don't optimize by noticing that bits in MASK
7881 are all off in X. This is used when X will be complemented, by either
7882 NOT, NEG, or XOR. */
7885 force_to_mode (rtx x, enum machine_mode mode, unsigned HOST_WIDE_INT mask,
7888 enum rtx_code code = GET_CODE (x);
7889 int next_select = just_select || code == XOR || code == NOT || code == NEG;
7890 enum machine_mode op_mode;
7891 unsigned HOST_WIDE_INT fuller_mask, nonzero;
7894 /* If this is a CALL or ASM_OPERANDS, don't do anything. Some of the
7895 code below will do the wrong thing since the mode of such an
7896 expression is VOIDmode.
7898 Also do nothing if X is a CLOBBER; this can happen if X was
7899 the return value from a call to gen_lowpart. */
7900 if (code == CALL || code == ASM_OPERANDS || code == CLOBBER)
7903 /* We want to perform the operation is its present mode unless we know
7904 that the operation is valid in MODE, in which case we do the operation
7906 op_mode = ((GET_MODE_CLASS (mode) == GET_MODE_CLASS (GET_MODE (x))
7907 && have_insn_for (code, mode))
7908 ? mode : GET_MODE (x));
7910 /* It is not valid to do a right-shift in a narrower mode
7911 than the one it came in with. */
7912 if ((code == LSHIFTRT || code == ASHIFTRT)
7913 && GET_MODE_BITSIZE (mode) < GET_MODE_BITSIZE (GET_MODE (x)))
7914 op_mode = GET_MODE (x);
7916 /* Truncate MASK to fit OP_MODE. */
7918 mask &= GET_MODE_MASK (op_mode);
7920 /* When we have an arithmetic operation, or a shift whose count we
7921 do not know, we need to assume that all bits up to the highest-order
7922 bit in MASK will be needed. This is how we form such a mask. */
7923 if (mask & ((unsigned HOST_WIDE_INT) 1 << (HOST_BITS_PER_WIDE_INT - 1)))
7924 fuller_mask = ~(unsigned HOST_WIDE_INT) 0;
7926 fuller_mask = (((unsigned HOST_WIDE_INT) 1 << (floor_log2 (mask) + 1))
7929 /* Determine what bits of X are guaranteed to be (non)zero. */
7930 nonzero = nonzero_bits (x, mode);
7932 /* If none of the bits in X are needed, return a zero. */
7933 if (!just_select && (nonzero & mask) == 0 && !side_effects_p (x))
7936 /* If X is a CONST_INT, return a new one. Do this here since the
7937 test below will fail. */
7938 if (CONST_INT_P (x))
7940 if (SCALAR_INT_MODE_P (mode))
7941 return gen_int_mode (INTVAL (x) & mask, mode);
7944 x = GEN_INT (INTVAL (x) & mask);
7945 return gen_lowpart_common (mode, x);
7949 /* If X is narrower than MODE and we want all the bits in X's mode, just
7950 get X in the proper mode. */
7951 if (GET_MODE_SIZE (GET_MODE (x)) < GET_MODE_SIZE (mode)
7952 && (GET_MODE_MASK (GET_MODE (x)) & ~mask) == 0)
7953 return gen_lowpart (mode, x);
7955 /* We can ignore the effect of a SUBREG if it narrows the mode or
7956 if the constant masks to zero all the bits the mode doesn't have. */
7957 if (GET_CODE (x) == SUBREG
7958 && subreg_lowpart_p (x)
7959 && ((GET_MODE_SIZE (GET_MODE (x))
7960 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
7962 & GET_MODE_MASK (GET_MODE (x))
7963 & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (x)))))))
7964 return force_to_mode (SUBREG_REG (x), mode, mask, next_select);
7966 /* The arithmetic simplifications here only work for scalar integer modes. */
7967 if (!SCALAR_INT_MODE_P (mode) || !SCALAR_INT_MODE_P (GET_MODE (x)))
7968 return gen_lowpart_or_truncate (mode, x);
7973 /* If X is a (clobber (const_int)), return it since we know we are
7974 generating something that won't match. */
7981 x = expand_compound_operation (x);
7982 if (GET_CODE (x) != code)
7983 return force_to_mode (x, mode, mask, next_select);
7987 /* Similarly for a truncate. */
7988 return force_to_mode (XEXP (x, 0), mode, mask, next_select);
7991 /* If this is an AND with a constant, convert it into an AND
7992 whose constant is the AND of that constant with MASK. If it
7993 remains an AND of MASK, delete it since it is redundant. */
7995 if (CONST_INT_P (XEXP (x, 1)))
7997 x = simplify_and_const_int (x, op_mode, XEXP (x, 0),
7998 mask & INTVAL (XEXP (x, 1)));
8000 /* If X is still an AND, see if it is an AND with a mask that
8001 is just some low-order bits. If so, and it is MASK, we don't
8004 if (GET_CODE (x) == AND && CONST_INT_P (XEXP (x, 1))
8005 && ((INTVAL (XEXP (x, 1)) & GET_MODE_MASK (GET_MODE (x)))
8009 /* If it remains an AND, try making another AND with the bits
8010 in the mode mask that aren't in MASK turned on. If the
8011 constant in the AND is wide enough, this might make a
8012 cheaper constant. */
8014 if (GET_CODE (x) == AND && CONST_INT_P (XEXP (x, 1))
8015 && GET_MODE_MASK (GET_MODE (x)) != mask
8016 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT)
8018 HOST_WIDE_INT cval = (INTVAL (XEXP (x, 1))
8019 | (GET_MODE_MASK (GET_MODE (x)) & ~mask));
8020 int width = GET_MODE_BITSIZE (GET_MODE (x));
8023 /* If MODE is narrower than HOST_WIDE_INT and CVAL is a negative
8024 number, sign extend it. */
8025 if (width > 0 && width < HOST_BITS_PER_WIDE_INT
8026 && (cval & ((HOST_WIDE_INT) 1 << (width - 1))) != 0)
8027 cval |= (HOST_WIDE_INT) -1 << width;
8029 y = simplify_gen_binary (AND, GET_MODE (x),
8030 XEXP (x, 0), GEN_INT (cval));
8031 if (rtx_cost (y, SET, optimize_this_for_speed_p)
8032 < rtx_cost (x, SET, optimize_this_for_speed_p))
8042 /* In (and (plus FOO C1) M), if M is a mask that just turns off
8043 low-order bits (as in an alignment operation) and FOO is already
8044 aligned to that boundary, mask C1 to that boundary as well.
8045 This may eliminate that PLUS and, later, the AND. */
8048 unsigned int width = GET_MODE_BITSIZE (mode);
8049 unsigned HOST_WIDE_INT smask = mask;
8051 /* If MODE is narrower than HOST_WIDE_INT and mask is a negative
8052 number, sign extend it. */
8054 if (width < HOST_BITS_PER_WIDE_INT
8055 && (smask & ((HOST_WIDE_INT) 1 << (width - 1))) != 0)
8056 smask |= (HOST_WIDE_INT) -1 << width;
8058 if (CONST_INT_P (XEXP (x, 1))
8059 && exact_log2 (- smask) >= 0
8060 && (nonzero_bits (XEXP (x, 0), mode) & ~smask) == 0
8061 && (INTVAL (XEXP (x, 1)) & ~smask) != 0)
8062 return force_to_mode (plus_constant (XEXP (x, 0),
8063 (INTVAL (XEXP (x, 1)) & smask)),
8064 mode, smask, next_select);
8067 /* ... fall through ... */
8070 /* For PLUS, MINUS and MULT, we need any bits less significant than the
8071 most significant bit in MASK since carries from those bits will
8072 affect the bits we are interested in. */
8077 /* If X is (minus C Y) where C's least set bit is larger than any bit
8078 in the mask, then we may replace with (neg Y). */
8079 if (CONST_INT_P (XEXP (x, 0))
8080 && (((unsigned HOST_WIDE_INT) (INTVAL (XEXP (x, 0))
8081 & -INTVAL (XEXP (x, 0))))
8084 x = simplify_gen_unary (NEG, GET_MODE (x), XEXP (x, 1),
8086 return force_to_mode (x, mode, mask, next_select);
8089 /* Similarly, if C contains every bit in the fuller_mask, then we may
8090 replace with (not Y). */
8091 if (CONST_INT_P (XEXP (x, 0))
8092 && ((INTVAL (XEXP (x, 0)) | (HOST_WIDE_INT) fuller_mask)
8093 == INTVAL (XEXP (x, 0))))
8095 x = simplify_gen_unary (NOT, GET_MODE (x),
8096 XEXP (x, 1), GET_MODE (x));
8097 return force_to_mode (x, mode, mask, next_select);
8105 /* If X is (ior (lshiftrt FOO C1) C2), try to commute the IOR and
8106 LSHIFTRT so we end up with an (and (lshiftrt (ior ...) ...) ...)
8107 operation which may be a bitfield extraction. Ensure that the
8108 constant we form is not wider than the mode of X. */
8110 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
8111 && CONST_INT_P (XEXP (XEXP (x, 0), 1))
8112 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
8113 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT
8114 && CONST_INT_P (XEXP (x, 1))
8115 && ((INTVAL (XEXP (XEXP (x, 0), 1))
8116 + floor_log2 (INTVAL (XEXP (x, 1))))
8117 < GET_MODE_BITSIZE (GET_MODE (x)))
8118 && (INTVAL (XEXP (x, 1))
8119 & ~nonzero_bits (XEXP (x, 0), GET_MODE (x))) == 0)
8121 temp = GEN_INT ((INTVAL (XEXP (x, 1)) & mask)
8122 << INTVAL (XEXP (XEXP (x, 0), 1)));
8123 temp = simplify_gen_binary (GET_CODE (x), GET_MODE (x),
8124 XEXP (XEXP (x, 0), 0), temp);
8125 x = simplify_gen_binary (LSHIFTRT, GET_MODE (x), temp,
8126 XEXP (XEXP (x, 0), 1));
8127 return force_to_mode (x, mode, mask, next_select);
8131 /* For most binary operations, just propagate into the operation and
8132 change the mode if we have an operation of that mode. */
8134 op0 = force_to_mode (XEXP (x, 0), mode, mask, next_select);
8135 op1 = force_to_mode (XEXP (x, 1), mode, mask, next_select);
8137 /* If we ended up truncating both operands, truncate the result of the
8138 operation instead. */
8139 if (GET_CODE (op0) == TRUNCATE
8140 && GET_CODE (op1) == TRUNCATE)
8142 op0 = XEXP (op0, 0);
8143 op1 = XEXP (op1, 0);
8146 op0 = gen_lowpart_or_truncate (op_mode, op0);
8147 op1 = gen_lowpart_or_truncate (op_mode, op1);
8149 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
8150 x = simplify_gen_binary (code, op_mode, op0, op1);
8154 /* For left shifts, do the same, but just for the first operand.
8155 However, we cannot do anything with shifts where we cannot
8156 guarantee that the counts are smaller than the size of the mode
8157 because such a count will have a different meaning in a
8160 if (! (CONST_INT_P (XEXP (x, 1))
8161 && INTVAL (XEXP (x, 1)) >= 0
8162 && INTVAL (XEXP (x, 1)) < GET_MODE_BITSIZE (mode))
8163 && ! (GET_MODE (XEXP (x, 1)) != VOIDmode
8164 && (nonzero_bits (XEXP (x, 1), GET_MODE (XEXP (x, 1)))
8165 < (unsigned HOST_WIDE_INT) GET_MODE_BITSIZE (mode))))
8168 /* If the shift count is a constant and we can do arithmetic in
8169 the mode of the shift, refine which bits we need. Otherwise, use the
8170 conservative form of the mask. */
8171 if (CONST_INT_P (XEXP (x, 1))
8172 && INTVAL (XEXP (x, 1)) >= 0
8173 && INTVAL (XEXP (x, 1)) < GET_MODE_BITSIZE (op_mode)
8174 && GET_MODE_BITSIZE (op_mode) <= HOST_BITS_PER_WIDE_INT)
8175 mask >>= INTVAL (XEXP (x, 1));
8179 op0 = gen_lowpart_or_truncate (op_mode,
8180 force_to_mode (XEXP (x, 0), op_mode,
8181 mask, next_select));
8183 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0))
8184 x = simplify_gen_binary (code, op_mode, op0, XEXP (x, 1));
8188 /* Here we can only do something if the shift count is a constant,
8189 this shift constant is valid for the host, and we can do arithmetic
8192 if (CONST_INT_P (XEXP (x, 1))
8193 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT
8194 && GET_MODE_BITSIZE (op_mode) <= HOST_BITS_PER_WIDE_INT)
8196 rtx inner = XEXP (x, 0);
8197 unsigned HOST_WIDE_INT inner_mask;
8199 /* Select the mask of the bits we need for the shift operand. */
8200 inner_mask = mask << INTVAL (XEXP (x, 1));
8202 /* We can only change the mode of the shift if we can do arithmetic
8203 in the mode of the shift and INNER_MASK is no wider than the
8204 width of X's mode. */
8205 if ((inner_mask & ~GET_MODE_MASK (GET_MODE (x))) != 0)
8206 op_mode = GET_MODE (x);
8208 inner = force_to_mode (inner, op_mode, inner_mask, next_select);
8210 if (GET_MODE (x) != op_mode || inner != XEXP (x, 0))
8211 x = simplify_gen_binary (LSHIFTRT, op_mode, inner, XEXP (x, 1));
8214 /* If we have (and (lshiftrt FOO C1) C2) where the combination of the
8215 shift and AND produces only copies of the sign bit (C2 is one less
8216 than a power of two), we can do this with just a shift. */
8218 if (GET_CODE (x) == LSHIFTRT
8219 && CONST_INT_P (XEXP (x, 1))
8220 /* The shift puts one of the sign bit copies in the least significant
8222 && ((INTVAL (XEXP (x, 1))
8223 + num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0))))
8224 >= GET_MODE_BITSIZE (GET_MODE (x)))
8225 && exact_log2 (mask + 1) >= 0
8226 /* Number of bits left after the shift must be more than the mask
8228 && ((INTVAL (XEXP (x, 1)) + exact_log2 (mask + 1))
8229 <= GET_MODE_BITSIZE (GET_MODE (x)))
8230 /* Must be more sign bit copies than the mask needs. */
8231 && ((int) num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
8232 >= exact_log2 (mask + 1)))
8233 x = simplify_gen_binary (LSHIFTRT, GET_MODE (x), XEXP (x, 0),
8234 GEN_INT (GET_MODE_BITSIZE (GET_MODE (x))
8235 - exact_log2 (mask + 1)));
8240 /* If we are just looking for the sign bit, we don't need this shift at
8241 all, even if it has a variable count. */
8242 if (GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
8243 && (mask == ((unsigned HOST_WIDE_INT) 1
8244 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
8245 return force_to_mode (XEXP (x, 0), mode, mask, next_select);
8247 /* If this is a shift by a constant, get a mask that contains those bits
8248 that are not copies of the sign bit. We then have two cases: If
8249 MASK only includes those bits, this can be a logical shift, which may
8250 allow simplifications. If MASK is a single-bit field not within
8251 those bits, we are requesting a copy of the sign bit and hence can
8252 shift the sign bit to the appropriate location. */
8254 if (CONST_INT_P (XEXP (x, 1)) && INTVAL (XEXP (x, 1)) >= 0
8255 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT)
8259 /* If the considered data is wider than HOST_WIDE_INT, we can't
8260 represent a mask for all its bits in a single scalar.
8261 But we only care about the lower bits, so calculate these. */
8263 if (GET_MODE_BITSIZE (GET_MODE (x)) > HOST_BITS_PER_WIDE_INT)
8265 nonzero = ~(HOST_WIDE_INT) 0;
8267 /* GET_MODE_BITSIZE (GET_MODE (x)) - INTVAL (XEXP (x, 1))
8268 is the number of bits a full-width mask would have set.
8269 We need only shift if these are fewer than nonzero can
8270 hold. If not, we must keep all bits set in nonzero. */
8272 if (GET_MODE_BITSIZE (GET_MODE (x)) - INTVAL (XEXP (x, 1))
8273 < HOST_BITS_PER_WIDE_INT)
8274 nonzero >>= INTVAL (XEXP (x, 1))
8275 + HOST_BITS_PER_WIDE_INT
8276 - GET_MODE_BITSIZE (GET_MODE (x)) ;
8280 nonzero = GET_MODE_MASK (GET_MODE (x));
8281 nonzero >>= INTVAL (XEXP (x, 1));
8284 if ((mask & ~nonzero) == 0)
8286 x = simplify_shift_const (NULL_RTX, LSHIFTRT, GET_MODE (x),
8287 XEXP (x, 0), INTVAL (XEXP (x, 1)));
8288 if (GET_CODE (x) != ASHIFTRT)
8289 return force_to_mode (x, mode, mask, next_select);
8292 else if ((i = exact_log2 (mask)) >= 0)
8294 x = simplify_shift_const
8295 (NULL_RTX, LSHIFTRT, GET_MODE (x), XEXP (x, 0),
8296 GET_MODE_BITSIZE (GET_MODE (x)) - 1 - i);
8298 if (GET_CODE (x) != ASHIFTRT)
8299 return force_to_mode (x, mode, mask, next_select);
8303 /* If MASK is 1, convert this to an LSHIFTRT. This can be done
8304 even if the shift count isn't a constant. */
8306 x = simplify_gen_binary (LSHIFTRT, GET_MODE (x),
8307 XEXP (x, 0), XEXP (x, 1));
8311 /* If this is a zero- or sign-extension operation that just affects bits
8312 we don't care about, remove it. Be sure the call above returned
8313 something that is still a shift. */
8315 if ((GET_CODE (x) == LSHIFTRT || GET_CODE (x) == ASHIFTRT)
8316 && CONST_INT_P (XEXP (x, 1))
8317 && INTVAL (XEXP (x, 1)) >= 0
8318 && (INTVAL (XEXP (x, 1))
8319 <= GET_MODE_BITSIZE (GET_MODE (x)) - (floor_log2 (mask) + 1))
8320 && GET_CODE (XEXP (x, 0)) == ASHIFT
8321 && XEXP (XEXP (x, 0), 1) == XEXP (x, 1))
8322 return force_to_mode (XEXP (XEXP (x, 0), 0), mode, mask,
8329 /* If the shift count is constant and we can do computations
8330 in the mode of X, compute where the bits we care about are.
8331 Otherwise, we can't do anything. Don't change the mode of
8332 the shift or propagate MODE into the shift, though. */
8333 if (CONST_INT_P (XEXP (x, 1))
8334 && INTVAL (XEXP (x, 1)) >= 0)
8336 temp = simplify_binary_operation (code == ROTATE ? ROTATERT : ROTATE,
8337 GET_MODE (x), GEN_INT (mask),
8339 if (temp && CONST_INT_P (temp))
8341 force_to_mode (XEXP (x, 0), GET_MODE (x),
8342 INTVAL (temp), next_select));
8347 /* If we just want the low-order bit, the NEG isn't needed since it
8348 won't change the low-order bit. */
8350 return force_to_mode (XEXP (x, 0), mode, mask, just_select);
8352 /* We need any bits less significant than the most significant bit in
8353 MASK since carries from those bits will affect the bits we are
8359 /* (not FOO) is (xor FOO CONST), so if FOO is an LSHIFTRT, we can do the
8360 same as the XOR case above. Ensure that the constant we form is not
8361 wider than the mode of X. */
8363 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
8364 && CONST_INT_P (XEXP (XEXP (x, 0), 1))
8365 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
8366 && (INTVAL (XEXP (XEXP (x, 0), 1)) + floor_log2 (mask)
8367 < GET_MODE_BITSIZE (GET_MODE (x)))
8368 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT)
8370 temp = gen_int_mode (mask << INTVAL (XEXP (XEXP (x, 0), 1)),
8372 temp = simplify_gen_binary (XOR, GET_MODE (x),
8373 XEXP (XEXP (x, 0), 0), temp);
8374 x = simplify_gen_binary (LSHIFTRT, GET_MODE (x),
8375 temp, XEXP (XEXP (x, 0), 1));
8377 return force_to_mode (x, mode, mask, next_select);
8380 /* (and (not FOO) CONST) is (not (or FOO (not CONST))), so we must
8381 use the full mask inside the NOT. */
8385 op0 = gen_lowpart_or_truncate (op_mode,
8386 force_to_mode (XEXP (x, 0), mode, mask,
8388 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0))
8389 x = simplify_gen_unary (code, op_mode, op0, op_mode);
8393 /* (and (ne FOO 0) CONST) can be (and FOO CONST) if CONST is included
8394 in STORE_FLAG_VALUE and FOO has a single bit that might be nonzero,
8395 which is equal to STORE_FLAG_VALUE. */
8396 if ((mask & ~STORE_FLAG_VALUE) == 0 && XEXP (x, 1) == const0_rtx
8397 && GET_MODE (XEXP (x, 0)) == mode
8398 && exact_log2 (nonzero_bits (XEXP (x, 0), mode)) >= 0
8399 && (nonzero_bits (XEXP (x, 0), mode)
8400 == (unsigned HOST_WIDE_INT) STORE_FLAG_VALUE))
8401 return force_to_mode (XEXP (x, 0), mode, mask, next_select);
8406 /* We have no way of knowing if the IF_THEN_ELSE can itself be
8407 written in a narrower mode. We play it safe and do not do so. */
8410 gen_lowpart_or_truncate (GET_MODE (x),
8411 force_to_mode (XEXP (x, 1), mode,
8412 mask, next_select)));
8414 gen_lowpart_or_truncate (GET_MODE (x),
8415 force_to_mode (XEXP (x, 2), mode,
8416 mask, next_select)));
8423 /* Ensure we return a value of the proper mode. */
8424 return gen_lowpart_or_truncate (mode, x);
8427 /* Return nonzero if X is an expression that has one of two values depending on
8428 whether some other value is zero or nonzero. In that case, we return the
8429 value that is being tested, *PTRUE is set to the value if the rtx being
8430 returned has a nonzero value, and *PFALSE is set to the other alternative.
8432 If we return zero, we set *PTRUE and *PFALSE to X. */
8435 if_then_else_cond (rtx x, rtx *ptrue, rtx *pfalse)
8437 enum machine_mode mode = GET_MODE (x);
8438 enum rtx_code code = GET_CODE (x);
8439 rtx cond0, cond1, true0, true1, false0, false1;
8440 unsigned HOST_WIDE_INT nz;
8442 /* If we are comparing a value against zero, we are done. */
8443 if ((code == NE || code == EQ)
8444 && XEXP (x, 1) == const0_rtx)
8446 *ptrue = (code == NE) ? const_true_rtx : const0_rtx;
8447 *pfalse = (code == NE) ? const0_rtx : const_true_rtx;
8451 /* If this is a unary operation whose operand has one of two values, apply
8452 our opcode to compute those values. */
8453 else if (UNARY_P (x)
8454 && (cond0 = if_then_else_cond (XEXP (x, 0), &true0, &false0)) != 0)
8456 *ptrue = simplify_gen_unary (code, mode, true0, GET_MODE (XEXP (x, 0)));
8457 *pfalse = simplify_gen_unary (code, mode, false0,
8458 GET_MODE (XEXP (x, 0)));
8462 /* If this is a COMPARE, do nothing, since the IF_THEN_ELSE we would
8463 make can't possibly match and would suppress other optimizations. */
8464 else if (code == COMPARE)
8467 /* If this is a binary operation, see if either side has only one of two
8468 values. If either one does or if both do and they are conditional on
8469 the same value, compute the new true and false values. */
8470 else if (BINARY_P (x))
8472 cond0 = if_then_else_cond (XEXP (x, 0), &true0, &false0);
8473 cond1 = if_then_else_cond (XEXP (x, 1), &true1, &false1);
8475 if ((cond0 != 0 || cond1 != 0)
8476 && ! (cond0 != 0 && cond1 != 0 && ! rtx_equal_p (cond0, cond1)))
8478 /* If if_then_else_cond returned zero, then true/false are the
8479 same rtl. We must copy one of them to prevent invalid rtl
8482 true0 = copy_rtx (true0);
8483 else if (cond1 == 0)
8484 true1 = copy_rtx (true1);
8486 if (COMPARISON_P (x))
8488 *ptrue = simplify_gen_relational (code, mode, VOIDmode,
8490 *pfalse = simplify_gen_relational (code, mode, VOIDmode,
8495 *ptrue = simplify_gen_binary (code, mode, true0, true1);
8496 *pfalse = simplify_gen_binary (code, mode, false0, false1);
8499 return cond0 ? cond0 : cond1;
8502 /* See if we have PLUS, IOR, XOR, MINUS or UMAX, where one of the
8503 operands is zero when the other is nonzero, and vice-versa,
8504 and STORE_FLAG_VALUE is 1 or -1. */
8506 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
8507 && (code == PLUS || code == IOR || code == XOR || code == MINUS
8509 && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT)
8511 rtx op0 = XEXP (XEXP (x, 0), 1);
8512 rtx op1 = XEXP (XEXP (x, 1), 1);
8514 cond0 = XEXP (XEXP (x, 0), 0);
8515 cond1 = XEXP (XEXP (x, 1), 0);
8517 if (COMPARISON_P (cond0)
8518 && COMPARISON_P (cond1)
8519 && ((GET_CODE (cond0) == reversed_comparison_code (cond1, NULL)
8520 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0))
8521 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1)))
8522 || ((swap_condition (GET_CODE (cond0))
8523 == reversed_comparison_code (cond1, NULL))
8524 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1))
8525 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0))))
8526 && ! side_effects_p (x))
8528 *ptrue = simplify_gen_binary (MULT, mode, op0, const_true_rtx);
8529 *pfalse = simplify_gen_binary (MULT, mode,
8531 ? simplify_gen_unary (NEG, mode,
8539 /* Similarly for MULT, AND and UMIN, except that for these the result
8541 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
8542 && (code == MULT || code == AND || code == UMIN)
8543 && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT)
8545 cond0 = XEXP (XEXP (x, 0), 0);
8546 cond1 = XEXP (XEXP (x, 1), 0);
8548 if (COMPARISON_P (cond0)
8549 && COMPARISON_P (cond1)
8550 && ((GET_CODE (cond0) == reversed_comparison_code (cond1, NULL)
8551 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0))
8552 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1)))
8553 || ((swap_condition (GET_CODE (cond0))
8554 == reversed_comparison_code (cond1, NULL))
8555 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1))
8556 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0))))
8557 && ! side_effects_p (x))
8559 *ptrue = *pfalse = const0_rtx;
8565 else if (code == IF_THEN_ELSE)
8567 /* If we have IF_THEN_ELSE already, extract the condition and
8568 canonicalize it if it is NE or EQ. */
8569 cond0 = XEXP (x, 0);
8570 *ptrue = XEXP (x, 1), *pfalse = XEXP (x, 2);
8571 if (GET_CODE (cond0) == NE && XEXP (cond0, 1) == const0_rtx)
8572 return XEXP (cond0, 0);
8573 else if (GET_CODE (cond0) == EQ && XEXP (cond0, 1) == const0_rtx)
8575 *ptrue = XEXP (x, 2), *pfalse = XEXP (x, 1);
8576 return XEXP (cond0, 0);
8582 /* If X is a SUBREG, we can narrow both the true and false values
8583 if the inner expression, if there is a condition. */
8584 else if (code == SUBREG
8585 && 0 != (cond0 = if_then_else_cond (SUBREG_REG (x),
8588 true0 = simplify_gen_subreg (mode, true0,
8589 GET_MODE (SUBREG_REG (x)), SUBREG_BYTE (x));
8590 false0 = simplify_gen_subreg (mode, false0,
8591 GET_MODE (SUBREG_REG (x)), SUBREG_BYTE (x));
8592 if (true0 && false0)
8600 /* If X is a constant, this isn't special and will cause confusions
8601 if we treat it as such. Likewise if it is equivalent to a constant. */
8602 else if (CONSTANT_P (x)
8603 || ((cond0 = get_last_value (x)) != 0 && CONSTANT_P (cond0)))
8606 /* If we're in BImode, canonicalize on 0 and STORE_FLAG_VALUE, as that
8607 will be least confusing to the rest of the compiler. */
8608 else if (mode == BImode)
8610 *ptrue = GEN_INT (STORE_FLAG_VALUE), *pfalse = const0_rtx;
8614 /* If X is known to be either 0 or -1, those are the true and
8615 false values when testing X. */
8616 else if (x == constm1_rtx || x == const0_rtx
8617 || (mode != VOIDmode
8618 && num_sign_bit_copies (x, mode) == GET_MODE_BITSIZE (mode)))
8620 *ptrue = constm1_rtx, *pfalse = const0_rtx;
8624 /* Likewise for 0 or a single bit. */
8625 else if (SCALAR_INT_MODE_P (mode)
8626 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
8627 && exact_log2 (nz = nonzero_bits (x, mode)) >= 0)
8629 *ptrue = gen_int_mode (nz, mode), *pfalse = const0_rtx;
8633 /* Otherwise fail; show no condition with true and false values the same. */
8634 *ptrue = *pfalse = x;
8638 /* Return the value of expression X given the fact that condition COND
8639 is known to be true when applied to REG as its first operand and VAL
8640 as its second. X is known to not be shared and so can be modified in
8643 We only handle the simplest cases, and specifically those cases that
8644 arise with IF_THEN_ELSE expressions. */
8647 known_cond (rtx x, enum rtx_code cond, rtx reg, rtx val)
8649 enum rtx_code code = GET_CODE (x);
8654 if (side_effects_p (x))
8657 /* If either operand of the condition is a floating point value,
8658 then we have to avoid collapsing an EQ comparison. */
8660 && rtx_equal_p (x, reg)
8661 && ! FLOAT_MODE_P (GET_MODE (x))
8662 && ! FLOAT_MODE_P (GET_MODE (val)))
8665 if (cond == UNEQ && rtx_equal_p (x, reg))
8668 /* If X is (abs REG) and we know something about REG's relationship
8669 with zero, we may be able to simplify this. */
8671 if (code == ABS && rtx_equal_p (XEXP (x, 0), reg) && val == const0_rtx)
8674 case GE: case GT: case EQ:
8677 return simplify_gen_unary (NEG, GET_MODE (XEXP (x, 0)),
8679 GET_MODE (XEXP (x, 0)));
8684 /* The only other cases we handle are MIN, MAX, and comparisons if the
8685 operands are the same as REG and VAL. */
8687 else if (COMPARISON_P (x) || COMMUTATIVE_ARITH_P (x))
8689 if (rtx_equal_p (XEXP (x, 0), val))
8690 cond = swap_condition (cond), temp = val, val = reg, reg = temp;
8692 if (rtx_equal_p (XEXP (x, 0), reg) && rtx_equal_p (XEXP (x, 1), val))
8694 if (COMPARISON_P (x))
8696 if (comparison_dominates_p (cond, code))
8697 return const_true_rtx;
8699 code = reversed_comparison_code (x, NULL);
8701 && comparison_dominates_p (cond, code))
8706 else if (code == SMAX || code == SMIN
8707 || code == UMIN || code == UMAX)
8709 int unsignedp = (code == UMIN || code == UMAX);
8711 /* Do not reverse the condition when it is NE or EQ.
8712 This is because we cannot conclude anything about
8713 the value of 'SMAX (x, y)' when x is not equal to y,
8714 but we can when x equals y. */
8715 if ((code == SMAX || code == UMAX)
8716 && ! (cond == EQ || cond == NE))
8717 cond = reverse_condition (cond);
8722 return unsignedp ? x : XEXP (x, 1);
8724 return unsignedp ? x : XEXP (x, 0);
8726 return unsignedp ? XEXP (x, 1) : x;
8728 return unsignedp ? XEXP (x, 0) : x;
8735 else if (code == SUBREG)
8737 enum machine_mode inner_mode = GET_MODE (SUBREG_REG (x));
8738 rtx new_rtx, r = known_cond (SUBREG_REG (x), cond, reg, val);
8740 if (SUBREG_REG (x) != r)
8742 /* We must simplify subreg here, before we lose track of the
8743 original inner_mode. */
8744 new_rtx = simplify_subreg (GET_MODE (x), r,
8745 inner_mode, SUBREG_BYTE (x));
8749 SUBST (SUBREG_REG (x), r);
8754 /* We don't have to handle SIGN_EXTEND here, because even in the
8755 case of replacing something with a modeless CONST_INT, a
8756 CONST_INT is already (supposed to be) a valid sign extension for
8757 its narrower mode, which implies it's already properly
8758 sign-extended for the wider mode. Now, for ZERO_EXTEND, the
8759 story is different. */
8760 else if (code == ZERO_EXTEND)
8762 enum machine_mode inner_mode = GET_MODE (XEXP (x, 0));
8763 rtx new_rtx, r = known_cond (XEXP (x, 0), cond, reg, val);
8765 if (XEXP (x, 0) != r)
8767 /* We must simplify the zero_extend here, before we lose
8768 track of the original inner_mode. */
8769 new_rtx = simplify_unary_operation (ZERO_EXTEND, GET_MODE (x),
8774 SUBST (XEXP (x, 0), r);
8780 fmt = GET_RTX_FORMAT (code);
8781 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
8784 SUBST (XEXP (x, i), known_cond (XEXP (x, i), cond, reg, val));
8785 else if (fmt[i] == 'E')
8786 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
8787 SUBST (XVECEXP (x, i, j), known_cond (XVECEXP (x, i, j),
8794 /* See if X and Y are equal for the purposes of seeing if we can rewrite an
8795 assignment as a field assignment. */
8798 rtx_equal_for_field_assignment_p (rtx x, rtx y)
8800 if (x == y || rtx_equal_p (x, y))
8803 if (x == 0 || y == 0 || GET_MODE (x) != GET_MODE (y))
8806 /* Check for a paradoxical SUBREG of a MEM compared with the MEM.
8807 Note that all SUBREGs of MEM are paradoxical; otherwise they
8808 would have been rewritten. */
8809 if (MEM_P (x) && GET_CODE (y) == SUBREG
8810 && MEM_P (SUBREG_REG (y))
8811 && rtx_equal_p (SUBREG_REG (y),
8812 gen_lowpart (GET_MODE (SUBREG_REG (y)), x)))
8815 if (MEM_P (y) && GET_CODE (x) == SUBREG
8816 && MEM_P (SUBREG_REG (x))
8817 && rtx_equal_p (SUBREG_REG (x),
8818 gen_lowpart (GET_MODE (SUBREG_REG (x)), y)))
8821 /* We used to see if get_last_value of X and Y were the same but that's
8822 not correct. In one direction, we'll cause the assignment to have
8823 the wrong destination and in the case, we'll import a register into this
8824 insn that might have already have been dead. So fail if none of the
8825 above cases are true. */
8829 /* See if X, a SET operation, can be rewritten as a bit-field assignment.
8830 Return that assignment if so.
8832 We only handle the most common cases. */
8835 make_field_assignment (rtx x)
8837 rtx dest = SET_DEST (x);
8838 rtx src = SET_SRC (x);
8843 unsigned HOST_WIDE_INT len;
8845 enum machine_mode mode;
8847 /* If SRC was (and (not (ashift (const_int 1) POS)) DEST), this is
8848 a clear of a one-bit field. We will have changed it to
8849 (and (rotate (const_int -2) POS) DEST), so check for that. Also check
8852 if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == ROTATE
8853 && CONST_INT_P (XEXP (XEXP (src, 0), 0))
8854 && INTVAL (XEXP (XEXP (src, 0), 0)) == -2
8855 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
8857 assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1),
8860 return gen_rtx_SET (VOIDmode, assign, const0_rtx);
8864 if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == SUBREG
8865 && subreg_lowpart_p (XEXP (src, 0))
8866 && (GET_MODE_SIZE (GET_MODE (XEXP (src, 0)))
8867 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (src, 0)))))
8868 && GET_CODE (SUBREG_REG (XEXP (src, 0))) == ROTATE
8869 && CONST_INT_P (XEXP (SUBREG_REG (XEXP (src, 0)), 0))
8870 && INTVAL (XEXP (SUBREG_REG (XEXP (src, 0)), 0)) == -2
8871 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
8873 assign = make_extraction (VOIDmode, dest, 0,
8874 XEXP (SUBREG_REG (XEXP (src, 0)), 1),
8877 return gen_rtx_SET (VOIDmode, assign, const0_rtx);
8881 /* If SRC is (ior (ashift (const_int 1) POS) DEST), this is a set of a
8883 if (GET_CODE (src) == IOR && GET_CODE (XEXP (src, 0)) == ASHIFT
8884 && XEXP (XEXP (src, 0), 0) == const1_rtx
8885 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
8887 assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1),
8890 return gen_rtx_SET (VOIDmode, assign, const1_rtx);
8894 /* If DEST is already a field assignment, i.e. ZERO_EXTRACT, and the
8895 SRC is an AND with all bits of that field set, then we can discard
8897 if (GET_CODE (dest) == ZERO_EXTRACT
8898 && CONST_INT_P (XEXP (dest, 1))
8899 && GET_CODE (src) == AND
8900 && CONST_INT_P (XEXP (src, 1)))
8902 HOST_WIDE_INT width = INTVAL (XEXP (dest, 1));
8903 unsigned HOST_WIDE_INT and_mask = INTVAL (XEXP (src, 1));
8904 unsigned HOST_WIDE_INT ze_mask;
8906 if (width >= HOST_BITS_PER_WIDE_INT)
8909 ze_mask = ((unsigned HOST_WIDE_INT)1 << width) - 1;
8911 /* Complete overlap. We can remove the source AND. */
8912 if ((and_mask & ze_mask) == ze_mask)
8913 return gen_rtx_SET (VOIDmode, dest, XEXP (src, 0));
8915 /* Partial overlap. We can reduce the source AND. */
8916 if ((and_mask & ze_mask) != and_mask)
8918 mode = GET_MODE (src);
8919 src = gen_rtx_AND (mode, XEXP (src, 0),
8920 gen_int_mode (and_mask & ze_mask, mode));
8921 return gen_rtx_SET (VOIDmode, dest, src);
8925 /* The other case we handle is assignments into a constant-position
8926 field. They look like (ior/xor (and DEST C1) OTHER). If C1 represents
8927 a mask that has all one bits except for a group of zero bits and
8928 OTHER is known to have zeros where C1 has ones, this is such an
8929 assignment. Compute the position and length from C1. Shift OTHER
8930 to the appropriate position, force it to the required mode, and
8931 make the extraction. Check for the AND in both operands. */
8933 if (GET_CODE (src) != IOR && GET_CODE (src) != XOR)
8936 rhs = expand_compound_operation (XEXP (src, 0));
8937 lhs = expand_compound_operation (XEXP (src, 1));
8939 if (GET_CODE (rhs) == AND
8940 && CONST_INT_P (XEXP (rhs, 1))
8941 && rtx_equal_for_field_assignment_p (XEXP (rhs, 0), dest))
8942 c1 = INTVAL (XEXP (rhs, 1)), other = lhs;
8943 else if (GET_CODE (lhs) == AND
8944 && CONST_INT_P (XEXP (lhs, 1))
8945 && rtx_equal_for_field_assignment_p (XEXP (lhs, 0), dest))
8946 c1 = INTVAL (XEXP (lhs, 1)), other = rhs;
8950 pos = get_pos_from_mask ((~c1) & GET_MODE_MASK (GET_MODE (dest)), &len);
8951 if (pos < 0 || pos + len > GET_MODE_BITSIZE (GET_MODE (dest))
8952 || GET_MODE_BITSIZE (GET_MODE (dest)) > HOST_BITS_PER_WIDE_INT
8953 || (c1 & nonzero_bits (other, GET_MODE (dest))) != 0)
8956 assign = make_extraction (VOIDmode, dest, pos, NULL_RTX, len, 1, 1, 0);
8960 /* The mode to use for the source is the mode of the assignment, or of
8961 what is inside a possible STRICT_LOW_PART. */
8962 mode = (GET_CODE (assign) == STRICT_LOW_PART
8963 ? GET_MODE (XEXP (assign, 0)) : GET_MODE (assign));
8965 /* Shift OTHER right POS places and make it the source, restricting it
8966 to the proper length and mode. */
8968 src = canon_reg_for_combine (simplify_shift_const (NULL_RTX, LSHIFTRT,
8972 src = force_to_mode (src, mode,
8973 GET_MODE_BITSIZE (mode) >= HOST_BITS_PER_WIDE_INT
8974 ? ~(unsigned HOST_WIDE_INT) 0
8975 : ((unsigned HOST_WIDE_INT) 1 << len) - 1,
8978 /* If SRC is masked by an AND that does not make a difference in
8979 the value being stored, strip it. */
8980 if (GET_CODE (assign) == ZERO_EXTRACT
8981 && CONST_INT_P (XEXP (assign, 1))
8982 && INTVAL (XEXP (assign, 1)) < HOST_BITS_PER_WIDE_INT
8983 && GET_CODE (src) == AND
8984 && CONST_INT_P (XEXP (src, 1))
8985 && ((unsigned HOST_WIDE_INT) INTVAL (XEXP (src, 1))
8986 == ((unsigned HOST_WIDE_INT) 1 << INTVAL (XEXP (assign, 1))) - 1))
8987 src = XEXP (src, 0);
8989 return gen_rtx_SET (VOIDmode, assign, src);
8992 /* See if X is of the form (+ (* a c) (* b c)) and convert to (* (+ a b) c)
8996 apply_distributive_law (rtx x)
8998 enum rtx_code code = GET_CODE (x);
8999 enum rtx_code inner_code;
9000 rtx lhs, rhs, other;
9003 /* Distributivity is not true for floating point as it can change the
9004 value. So we don't do it unless -funsafe-math-optimizations. */
9005 if (FLOAT_MODE_P (GET_MODE (x))
9006 && ! flag_unsafe_math_optimizations)
9009 /* The outer operation can only be one of the following: */
9010 if (code != IOR && code != AND && code != XOR
9011 && code != PLUS && code != MINUS)
9017 /* If either operand is a primitive we can't do anything, so get out
9019 if (OBJECT_P (lhs) || OBJECT_P (rhs))
9022 lhs = expand_compound_operation (lhs);
9023 rhs = expand_compound_operation (rhs);
9024 inner_code = GET_CODE (lhs);
9025 if (inner_code != GET_CODE (rhs))
9028 /* See if the inner and outer operations distribute. */
9035 /* These all distribute except over PLUS. */
9036 if (code == PLUS || code == MINUS)
9041 if (code != PLUS && code != MINUS)
9046 /* This is also a multiply, so it distributes over everything. */
9050 /* Non-paradoxical SUBREGs distributes over all operations,
9051 provided the inner modes and byte offsets are the same, this
9052 is an extraction of a low-order part, we don't convert an fp
9053 operation to int or vice versa, this is not a vector mode,
9054 and we would not be converting a single-word operation into a
9055 multi-word operation. The latter test is not required, but
9056 it prevents generating unneeded multi-word operations. Some
9057 of the previous tests are redundant given the latter test,
9058 but are retained because they are required for correctness.
9060 We produce the result slightly differently in this case. */
9062 if (GET_MODE (SUBREG_REG (lhs)) != GET_MODE (SUBREG_REG (rhs))
9063 || SUBREG_BYTE (lhs) != SUBREG_BYTE (rhs)
9064 || ! subreg_lowpart_p (lhs)
9065 || (GET_MODE_CLASS (GET_MODE (lhs))
9066 != GET_MODE_CLASS (GET_MODE (SUBREG_REG (lhs))))
9067 || (GET_MODE_SIZE (GET_MODE (lhs))
9068 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs))))
9069 || VECTOR_MODE_P (GET_MODE (lhs))
9070 || GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs))) > UNITS_PER_WORD
9071 /* Result might need to be truncated. Don't change mode if
9072 explicit truncation is needed. */
9073 || !TRULY_NOOP_TRUNCATION
9074 (GET_MODE_BITSIZE (GET_MODE (x)),
9075 GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (lhs)))))
9078 tem = simplify_gen_binary (code, GET_MODE (SUBREG_REG (lhs)),
9079 SUBREG_REG (lhs), SUBREG_REG (rhs));
9080 return gen_lowpart (GET_MODE (x), tem);
9086 /* Set LHS and RHS to the inner operands (A and B in the example
9087 above) and set OTHER to the common operand (C in the example).
9088 There is only one way to do this unless the inner operation is
9090 if (COMMUTATIVE_ARITH_P (lhs)
9091 && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 0)))
9092 other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 1);
9093 else if (COMMUTATIVE_ARITH_P (lhs)
9094 && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 1)))
9095 other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 0);
9096 else if (COMMUTATIVE_ARITH_P (lhs)
9097 && rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 0)))
9098 other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 1);
9099 else if (rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 1)))
9100 other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 0);
9104 /* Form the new inner operation, seeing if it simplifies first. */
9105 tem = simplify_gen_binary (code, GET_MODE (x), lhs, rhs);
9107 /* There is one exception to the general way of distributing:
9108 (a | c) ^ (b | c) -> (a ^ b) & ~c */
9109 if (code == XOR && inner_code == IOR)
9112 other = simplify_gen_unary (NOT, GET_MODE (x), other, GET_MODE (x));
9115 /* We may be able to continuing distributing the result, so call
9116 ourselves recursively on the inner operation before forming the
9117 outer operation, which we return. */
9118 return simplify_gen_binary (inner_code, GET_MODE (x),
9119 apply_distributive_law (tem), other);
9122 /* See if X is of the form (* (+ A B) C), and if so convert to
9123 (+ (* A C) (* B C)) and try to simplify.
9125 Most of the time, this results in no change. However, if some of
9126 the operands are the same or inverses of each other, simplifications
9129 For example, (and (ior A B) (not B)) can occur as the result of
9130 expanding a bit field assignment. When we apply the distributive
9131 law to this, we get (ior (and (A (not B))) (and (B (not B)))),
9132 which then simplifies to (and (A (not B))).
9134 Note that no checks happen on the validity of applying the inverse
9135 distributive law. This is pointless since we can do it in the
9136 few places where this routine is called.
9138 N is the index of the term that is decomposed (the arithmetic operation,
9139 i.e. (+ A B) in the first example above). !N is the index of the term that
9140 is distributed, i.e. of C in the first example above. */
9142 distribute_and_simplify_rtx (rtx x, int n)
9144 enum machine_mode mode;
9145 enum rtx_code outer_code, inner_code;
9146 rtx decomposed, distributed, inner_op0, inner_op1, new_op0, new_op1, tmp;
9148 /* Distributivity is not true for floating point as it can change the
9149 value. So we don't do it unless -funsafe-math-optimizations. */
9150 if (FLOAT_MODE_P (GET_MODE (x))
9151 && ! flag_unsafe_math_optimizations)
9154 decomposed = XEXP (x, n);
9155 if (!ARITHMETIC_P (decomposed))
9158 mode = GET_MODE (x);
9159 outer_code = GET_CODE (x);
9160 distributed = XEXP (x, !n);
9162 inner_code = GET_CODE (decomposed);
9163 inner_op0 = XEXP (decomposed, 0);
9164 inner_op1 = XEXP (decomposed, 1);
9166 /* Special case (and (xor B C) (not A)), which is equivalent to
9167 (xor (ior A B) (ior A C)) */
9168 if (outer_code == AND && inner_code == XOR && GET_CODE (distributed) == NOT)
9170 distributed = XEXP (distributed, 0);
9176 /* Distribute the second term. */
9177 new_op0 = simplify_gen_binary (outer_code, mode, inner_op0, distributed);
9178 new_op1 = simplify_gen_binary (outer_code, mode, inner_op1, distributed);
9182 /* Distribute the first term. */
9183 new_op0 = simplify_gen_binary (outer_code, mode, distributed, inner_op0);
9184 new_op1 = simplify_gen_binary (outer_code, mode, distributed, inner_op1);
9187 tmp = apply_distributive_law (simplify_gen_binary (inner_code, mode,
9189 if (GET_CODE (tmp) != outer_code
9190 && rtx_cost (tmp, SET, optimize_this_for_speed_p)
9191 < rtx_cost (x, SET, optimize_this_for_speed_p))
9197 /* Simplify a logical `and' of VAROP with the constant CONSTOP, to be done
9198 in MODE. Return an equivalent form, if different from (and VAROP
9199 (const_int CONSTOP)). Otherwise, return NULL_RTX. */
9202 simplify_and_const_int_1 (enum machine_mode mode, rtx varop,
9203 unsigned HOST_WIDE_INT constop)
9205 unsigned HOST_WIDE_INT nonzero;
9206 unsigned HOST_WIDE_INT orig_constop;
9211 orig_constop = constop;
9212 if (GET_CODE (varop) == CLOBBER)
9215 /* Simplify VAROP knowing that we will be only looking at some of the
9218 Note by passing in CONSTOP, we guarantee that the bits not set in
9219 CONSTOP are not significant and will never be examined. We must
9220 ensure that is the case by explicitly masking out those bits
9221 before returning. */
9222 varop = force_to_mode (varop, mode, constop, 0);
9224 /* If VAROP is a CLOBBER, we will fail so return it. */
9225 if (GET_CODE (varop) == CLOBBER)
9228 /* If VAROP is a CONST_INT, then we need to apply the mask in CONSTOP
9229 to VAROP and return the new constant. */
9230 if (CONST_INT_P (varop))
9231 return gen_int_mode (INTVAL (varop) & constop, mode);
9233 /* See what bits may be nonzero in VAROP. Unlike the general case of
9234 a call to nonzero_bits, here we don't care about bits outside
9237 nonzero = nonzero_bits (varop, mode) & GET_MODE_MASK (mode);
9239 /* Turn off all bits in the constant that are known to already be zero.
9240 Thus, if the AND isn't needed at all, we will have CONSTOP == NONZERO_BITS
9241 which is tested below. */
9245 /* If we don't have any bits left, return zero. */
9249 /* If VAROP is a NEG of something known to be zero or 1 and CONSTOP is
9250 a power of two, we can replace this with an ASHIFT. */
9251 if (GET_CODE (varop) == NEG && nonzero_bits (XEXP (varop, 0), mode) == 1
9252 && (i = exact_log2 (constop)) >= 0)
9253 return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (varop, 0), i);
9255 /* If VAROP is an IOR or XOR, apply the AND to both branches of the IOR
9256 or XOR, then try to apply the distributive law. This may eliminate
9257 operations if either branch can be simplified because of the AND.
9258 It may also make some cases more complex, but those cases probably
9259 won't match a pattern either with or without this. */
9261 if (GET_CODE (varop) == IOR || GET_CODE (varop) == XOR)
9265 apply_distributive_law
9266 (simplify_gen_binary (GET_CODE (varop), GET_MODE (varop),
9267 simplify_and_const_int (NULL_RTX,
9271 simplify_and_const_int (NULL_RTX,
9276 /* If VAROP is PLUS, and the constant is a mask of low bits, distribute
9277 the AND and see if one of the operands simplifies to zero. If so, we
9278 may eliminate it. */
9280 if (GET_CODE (varop) == PLUS
9281 && exact_log2 (constop + 1) >= 0)
9285 o0 = simplify_and_const_int (NULL_RTX, mode, XEXP (varop, 0), constop);
9286 o1 = simplify_and_const_int (NULL_RTX, mode, XEXP (varop, 1), constop);
9287 if (o0 == const0_rtx)
9289 if (o1 == const0_rtx)
9293 /* Make a SUBREG if necessary. If we can't make it, fail. */
9294 varop = gen_lowpart (mode, varop);
9295 if (varop == NULL_RTX || GET_CODE (varop) == CLOBBER)
9298 /* If we are only masking insignificant bits, return VAROP. */
9299 if (constop == nonzero)
9302 if (varop == orig_varop && constop == orig_constop)
9305 /* Otherwise, return an AND. */
9306 return simplify_gen_binary (AND, mode, varop, gen_int_mode (constop, mode));
9310 /* We have X, a logical `and' of VAROP with the constant CONSTOP, to be done
9313 Return an equivalent form, if different from X. Otherwise, return X. If
9314 X is zero, we are to always construct the equivalent form. */
9317 simplify_and_const_int (rtx x, enum machine_mode mode, rtx varop,
9318 unsigned HOST_WIDE_INT constop)
9320 rtx tem = simplify_and_const_int_1 (mode, varop, constop);
9325 x = simplify_gen_binary (AND, GET_MODE (varop), varop,
9326 gen_int_mode (constop, mode));
9327 if (GET_MODE (x) != mode)
9328 x = gen_lowpart (mode, x);
9332 /* Given a REG, X, compute which bits in X can be nonzero.
9333 We don't care about bits outside of those defined in MODE.
9335 For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is
9336 a shift, AND, or zero_extract, we can do better. */
9339 reg_nonzero_bits_for_combine (const_rtx x, enum machine_mode mode,
9340 const_rtx known_x ATTRIBUTE_UNUSED,
9341 enum machine_mode known_mode ATTRIBUTE_UNUSED,
9342 unsigned HOST_WIDE_INT known_ret ATTRIBUTE_UNUSED,
9343 unsigned HOST_WIDE_INT *nonzero)
9348 /* If X is a register whose nonzero bits value is current, use it.
9349 Otherwise, if X is a register whose value we can find, use that
9350 value. Otherwise, use the previously-computed global nonzero bits
9351 for this register. */
9353 rsp = VEC_index (reg_stat_type, reg_stat, REGNO (x));
9354 if (rsp->last_set_value != 0
9355 && (rsp->last_set_mode == mode
9356 || (GET_MODE_CLASS (rsp->last_set_mode) == MODE_INT
9357 && GET_MODE_CLASS (mode) == MODE_INT))
9358 && ((rsp->last_set_label >= label_tick_ebb_start
9359 && rsp->last_set_label < label_tick)
9360 || (rsp->last_set_label == label_tick
9361 && DF_INSN_LUID (rsp->last_set) < subst_low_luid)
9362 || (REGNO (x) >= FIRST_PSEUDO_REGISTER
9363 && REG_N_SETS (REGNO (x)) == 1
9365 (DF_LR_IN (ENTRY_BLOCK_PTR->next_bb), REGNO (x)))))
9367 *nonzero &= rsp->last_set_nonzero_bits;
9371 tem = get_last_value (x);
9375 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
9376 /* If X is narrower than MODE and TEM is a non-negative
9377 constant that would appear negative in the mode of X,
9378 sign-extend it for use in reg_nonzero_bits because some
9379 machines (maybe most) will actually do the sign-extension
9380 and this is the conservative approach.
9382 ??? For 2.5, try to tighten up the MD files in this regard
9383 instead of this kludge. */
9385 if (GET_MODE_BITSIZE (GET_MODE (x)) < GET_MODE_BITSIZE (mode)
9386 && CONST_INT_P (tem)
9388 && 0 != (INTVAL (tem)
9389 & ((HOST_WIDE_INT) 1
9390 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
9391 tem = GEN_INT (INTVAL (tem)
9392 | ((HOST_WIDE_INT) (-1)
9393 << GET_MODE_BITSIZE (GET_MODE (x))));
9397 else if (nonzero_sign_valid && rsp->nonzero_bits)
9399 unsigned HOST_WIDE_INT mask = rsp->nonzero_bits;
9401 if (GET_MODE_BITSIZE (GET_MODE (x)) < GET_MODE_BITSIZE (mode))
9402 /* We don't know anything about the upper bits. */
9403 mask |= GET_MODE_MASK (mode) ^ GET_MODE_MASK (GET_MODE (x));
9410 /* Return the number of bits at the high-order end of X that are known to
9411 be equal to the sign bit. X will be used in mode MODE; if MODE is
9412 VOIDmode, X will be used in its own mode. The returned value will always
9413 be between 1 and the number of bits in MODE. */
9416 reg_num_sign_bit_copies_for_combine (const_rtx x, enum machine_mode mode,
9417 const_rtx known_x ATTRIBUTE_UNUSED,
9418 enum machine_mode known_mode
9420 unsigned int known_ret ATTRIBUTE_UNUSED,
9421 unsigned int *result)
9426 rsp = VEC_index (reg_stat_type, reg_stat, REGNO (x));
9427 if (rsp->last_set_value != 0
9428 && rsp->last_set_mode == mode
9429 && ((rsp->last_set_label >= label_tick_ebb_start
9430 && rsp->last_set_label < label_tick)
9431 || (rsp->last_set_label == label_tick
9432 && DF_INSN_LUID (rsp->last_set) < subst_low_luid)
9433 || (REGNO (x) >= FIRST_PSEUDO_REGISTER
9434 && REG_N_SETS (REGNO (x)) == 1
9436 (DF_LR_IN (ENTRY_BLOCK_PTR->next_bb), REGNO (x)))))
9438 *result = rsp->last_set_sign_bit_copies;
9442 tem = get_last_value (x);
9446 if (nonzero_sign_valid && rsp->sign_bit_copies != 0
9447 && GET_MODE_BITSIZE (GET_MODE (x)) == GET_MODE_BITSIZE (mode))
9448 *result = rsp->sign_bit_copies;
9453 /* Return the number of "extended" bits there are in X, when interpreted
9454 as a quantity in MODE whose signedness is indicated by UNSIGNEDP. For
9455 unsigned quantities, this is the number of high-order zero bits.
9456 For signed quantities, this is the number of copies of the sign bit
9457 minus 1. In both case, this function returns the number of "spare"
9458 bits. For example, if two quantities for which this function returns
9459 at least 1 are added, the addition is known not to overflow.
9461 This function will always return 0 unless called during combine, which
9462 implies that it must be called from a define_split. */
9465 extended_count (const_rtx x, enum machine_mode mode, int unsignedp)
9467 if (nonzero_sign_valid == 0)
9471 ? (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
9472 ? (unsigned int) (GET_MODE_BITSIZE (mode) - 1
9473 - floor_log2 (nonzero_bits (x, mode)))
9475 : num_sign_bit_copies (x, mode) - 1);
9478 /* This function is called from `simplify_shift_const' to merge two
9479 outer operations. Specifically, we have already found that we need
9480 to perform operation *POP0 with constant *PCONST0 at the outermost
9481 position. We would now like to also perform OP1 with constant CONST1
9482 (with *POP0 being done last).
9484 Return 1 if we can do the operation and update *POP0 and *PCONST0 with
9485 the resulting operation. *PCOMP_P is set to 1 if we would need to
9486 complement the innermost operand, otherwise it is unchanged.
9488 MODE is the mode in which the operation will be done. No bits outside
9489 the width of this mode matter. It is assumed that the width of this mode
9490 is smaller than or equal to HOST_BITS_PER_WIDE_INT.
9492 If *POP0 or OP1 are UNKNOWN, it means no operation is required. Only NEG, PLUS,
9493 IOR, XOR, and AND are supported. We may set *POP0 to SET if the proper
9494 result is simply *PCONST0.
9496 If the resulting operation cannot be expressed as one operation, we
9497 return 0 and do not change *POP0, *PCONST0, and *PCOMP_P. */
9500 merge_outer_ops (enum rtx_code *pop0, HOST_WIDE_INT *pconst0, enum rtx_code op1, HOST_WIDE_INT const1, enum machine_mode mode, int *pcomp_p)
9502 enum rtx_code op0 = *pop0;
9503 HOST_WIDE_INT const0 = *pconst0;
9505 const0 &= GET_MODE_MASK (mode);
9506 const1 &= GET_MODE_MASK (mode);
9508 /* If OP0 is an AND, clear unimportant bits in CONST1. */
9512 /* If OP0 or OP1 is UNKNOWN, this is easy. Similarly if they are the same or
9515 if (op1 == UNKNOWN || op0 == SET)
9518 else if (op0 == UNKNOWN)
9519 op0 = op1, const0 = const1;
9521 else if (op0 == op1)
9545 /* Otherwise, if either is a PLUS or NEG, we can't do anything. */
9546 else if (op0 == PLUS || op1 == PLUS || op0 == NEG || op1 == NEG)
9549 /* If the two constants aren't the same, we can't do anything. The
9550 remaining six cases can all be done. */
9551 else if (const0 != const1)
9559 /* (a & b) | b == b */
9561 else /* op1 == XOR */
9562 /* (a ^ b) | b == a | b */
9568 /* (a & b) ^ b == (~a) & b */
9569 op0 = AND, *pcomp_p = 1;
9570 else /* op1 == IOR */
9571 /* (a | b) ^ b == a & ~b */
9572 op0 = AND, const0 = ~const0;
9577 /* (a | b) & b == b */
9579 else /* op1 == XOR */
9580 /* (a ^ b) & b) == (~a) & b */
9587 /* Check for NO-OP cases. */
9588 const0 &= GET_MODE_MASK (mode);
9590 && (op0 == IOR || op0 == XOR || op0 == PLUS))
9592 else if (const0 == 0 && op0 == AND)
9594 else if ((unsigned HOST_WIDE_INT) const0 == GET_MODE_MASK (mode)
9600 /* ??? Slightly redundant with the above mask, but not entirely.
9601 Moving this above means we'd have to sign-extend the mode mask
9602 for the final test. */
9603 if (op0 != UNKNOWN && op0 != NEG)
9604 *pconst0 = trunc_int_for_mode (const0, mode);
9609 /* A helper to simplify_shift_const_1 to determine the mode we can perform
9610 the shift in. The original shift operation CODE is performed on OP in
9611 ORIG_MODE. Return the wider mode MODE if we can perform the operation
9612 in that mode. Return ORIG_MODE otherwise. We can also assume that the
9613 result of the shift is subject to operation OUTER_CODE with operand
9616 static enum machine_mode
9617 try_widen_shift_mode (enum rtx_code code, rtx op, int count,
9618 enum machine_mode orig_mode, enum machine_mode mode,
9619 enum rtx_code outer_code, HOST_WIDE_INT outer_const)
9621 if (orig_mode == mode)
9623 gcc_assert (GET_MODE_BITSIZE (mode) > GET_MODE_BITSIZE (orig_mode));
9625 /* In general we can't perform in wider mode for right shift and rotate. */
9629 /* We can still widen if the bits brought in from the left are identical
9630 to the sign bit of ORIG_MODE. */
9631 if (num_sign_bit_copies (op, mode)
9632 > (unsigned) (GET_MODE_BITSIZE (mode)
9633 - GET_MODE_BITSIZE (orig_mode)))
9638 /* Similarly here but with zero bits. */
9639 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
9640 && (nonzero_bits (op, mode) & ~GET_MODE_MASK (orig_mode)) == 0)
9643 /* We can also widen if the bits brought in will be masked off. This
9644 operation is performed in ORIG_MODE. */
9645 if (outer_code == AND)
9647 int care_bits = low_bitmask_len (orig_mode, outer_const);
9650 && GET_MODE_BITSIZE (orig_mode) - care_bits >= count)
9666 /* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift.
9667 The result of the shift is RESULT_MODE. Return NULL_RTX if we cannot
9668 simplify it. Otherwise, return a simplified value.
9670 The shift is normally computed in the widest mode we find in VAROP, as
9671 long as it isn't a different number of words than RESULT_MODE. Exceptions
9672 are ASHIFTRT and ROTATE, which are always done in their original mode. */
9675 simplify_shift_const_1 (enum rtx_code code, enum machine_mode result_mode,
9676 rtx varop, int orig_count)
9678 enum rtx_code orig_code = code;
9679 rtx orig_varop = varop;
9681 enum machine_mode mode = result_mode;
9682 enum machine_mode shift_mode, tmode;
9683 unsigned int mode_words
9684 = (GET_MODE_SIZE (mode) + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD;
9685 /* We form (outer_op (code varop count) (outer_const)). */
9686 enum rtx_code outer_op = UNKNOWN;
9687 HOST_WIDE_INT outer_const = 0;
9688 int complement_p = 0;
9691 /* Make sure and truncate the "natural" shift on the way in. We don't
9692 want to do this inside the loop as it makes it more difficult to
9694 if (SHIFT_COUNT_TRUNCATED)
9695 orig_count &= GET_MODE_BITSIZE (mode) - 1;
9697 /* If we were given an invalid count, don't do anything except exactly
9698 what was requested. */
9700 if (orig_count < 0 || orig_count >= (int) GET_MODE_BITSIZE (mode))
9705 /* Unless one of the branches of the `if' in this loop does a `continue',
9706 we will `break' the loop after the `if'. */
9710 /* If we have an operand of (clobber (const_int 0)), fail. */
9711 if (GET_CODE (varop) == CLOBBER)
9714 /* Convert ROTATERT to ROTATE. */
9715 if (code == ROTATERT)
9717 unsigned int bitsize = GET_MODE_BITSIZE (result_mode);;
9719 if (VECTOR_MODE_P (result_mode))
9720 count = bitsize / GET_MODE_NUNITS (result_mode) - count;
9722 count = bitsize - count;
9725 shift_mode = try_widen_shift_mode (code, varop, count, result_mode,
9726 mode, outer_op, outer_const);
9728 /* Handle cases where the count is greater than the size of the mode
9729 minus 1. For ASHIFT, use the size minus one as the count (this can
9730 occur when simplifying (lshiftrt (ashiftrt ..))). For rotates,
9731 take the count modulo the size. For other shifts, the result is
9734 Since these shifts are being produced by the compiler by combining
9735 multiple operations, each of which are defined, we know what the
9736 result is supposed to be. */
9738 if (count > (GET_MODE_BITSIZE (shift_mode) - 1))
9740 if (code == ASHIFTRT)
9741 count = GET_MODE_BITSIZE (shift_mode) - 1;
9742 else if (code == ROTATE || code == ROTATERT)
9743 count %= GET_MODE_BITSIZE (shift_mode);
9746 /* We can't simply return zero because there may be an
9754 /* If we discovered we had to complement VAROP, leave. Making a NOT
9755 here would cause an infinite loop. */
9759 /* An arithmetic right shift of a quantity known to be -1 or 0
9761 if (code == ASHIFTRT
9762 && (num_sign_bit_copies (varop, shift_mode)
9763 == GET_MODE_BITSIZE (shift_mode)))
9769 /* If we are doing an arithmetic right shift and discarding all but
9770 the sign bit copies, this is equivalent to doing a shift by the
9771 bitsize minus one. Convert it into that shift because it will often
9772 allow other simplifications. */
9774 if (code == ASHIFTRT
9775 && (count + num_sign_bit_copies (varop, shift_mode)
9776 >= GET_MODE_BITSIZE (shift_mode)))
9777 count = GET_MODE_BITSIZE (shift_mode) - 1;
9779 /* We simplify the tests below and elsewhere by converting
9780 ASHIFTRT to LSHIFTRT if we know the sign bit is clear.
9781 `make_compound_operation' will convert it to an ASHIFTRT for
9782 those machines (such as VAX) that don't have an LSHIFTRT. */
9783 if (GET_MODE_BITSIZE (shift_mode) <= HOST_BITS_PER_WIDE_INT
9785 && ((nonzero_bits (varop, shift_mode)
9786 & ((HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (shift_mode) - 1)))
9790 if (((code == LSHIFTRT
9791 && GET_MODE_BITSIZE (shift_mode) <= HOST_BITS_PER_WIDE_INT
9792 && !(nonzero_bits (varop, shift_mode) >> count))
9794 && GET_MODE_BITSIZE (shift_mode) <= HOST_BITS_PER_WIDE_INT
9795 && !((nonzero_bits (varop, shift_mode) << count)
9796 & GET_MODE_MASK (shift_mode))))
9797 && !side_effects_p (varop))
9800 switch (GET_CODE (varop))
9806 new_rtx = expand_compound_operation (varop);
9807 if (new_rtx != varop)
9815 /* If we have (xshiftrt (mem ...) C) and C is MODE_WIDTH
9816 minus the width of a smaller mode, we can do this with a
9817 SIGN_EXTEND or ZERO_EXTEND from the narrower memory location. */
9818 if ((code == ASHIFTRT || code == LSHIFTRT)
9819 && ! mode_dependent_address_p (XEXP (varop, 0))
9820 && ! MEM_VOLATILE_P (varop)
9821 && (tmode = mode_for_size (GET_MODE_BITSIZE (mode) - count,
9822 MODE_INT, 1)) != BLKmode)
9824 new_rtx = adjust_address_nv (varop, tmode,
9825 BYTES_BIG_ENDIAN ? 0
9826 : count / BITS_PER_UNIT);
9828 varop = gen_rtx_fmt_e (code == ASHIFTRT ? SIGN_EXTEND
9829 : ZERO_EXTEND, mode, new_rtx);
9836 /* If VAROP is a SUBREG, strip it as long as the inner operand has
9837 the same number of words as what we've seen so far. Then store
9838 the widest mode in MODE. */
9839 if (subreg_lowpart_p (varop)
9840 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop)))
9841 > GET_MODE_SIZE (GET_MODE (varop)))
9842 && (unsigned int) ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop)))
9843 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
9846 varop = SUBREG_REG (varop);
9847 if (GET_MODE_SIZE (GET_MODE (varop)) > GET_MODE_SIZE (mode))
9848 mode = GET_MODE (varop);
9854 /* Some machines use MULT instead of ASHIFT because MULT
9855 is cheaper. But it is still better on those machines to
9856 merge two shifts into one. */
9857 if (CONST_INT_P (XEXP (varop, 1))
9858 && exact_log2 (INTVAL (XEXP (varop, 1))) >= 0)
9861 = simplify_gen_binary (ASHIFT, GET_MODE (varop),
9863 GEN_INT (exact_log2 (
9864 INTVAL (XEXP (varop, 1)))));
9870 /* Similar, for when divides are cheaper. */
9871 if (CONST_INT_P (XEXP (varop, 1))
9872 && exact_log2 (INTVAL (XEXP (varop, 1))) >= 0)
9875 = simplify_gen_binary (LSHIFTRT, GET_MODE (varop),
9877 GEN_INT (exact_log2 (
9878 INTVAL (XEXP (varop, 1)))));
9884 /* If we are extracting just the sign bit of an arithmetic
9885 right shift, that shift is not needed. However, the sign
9886 bit of a wider mode may be different from what would be
9887 interpreted as the sign bit in a narrower mode, so, if
9888 the result is narrower, don't discard the shift. */
9889 if (code == LSHIFTRT
9890 && count == (GET_MODE_BITSIZE (result_mode) - 1)
9891 && (GET_MODE_BITSIZE (result_mode)
9892 >= GET_MODE_BITSIZE (GET_MODE (varop))))
9894 varop = XEXP (varop, 0);
9898 /* ... fall through ... */
9903 /* Here we have two nested shifts. The result is usually the
9904 AND of a new shift with a mask. We compute the result below. */
9905 if (CONST_INT_P (XEXP (varop, 1))
9906 && INTVAL (XEXP (varop, 1)) >= 0
9907 && INTVAL (XEXP (varop, 1)) < GET_MODE_BITSIZE (GET_MODE (varop))
9908 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
9909 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
9910 && !VECTOR_MODE_P (result_mode))
9912 enum rtx_code first_code = GET_CODE (varop);
9913 unsigned int first_count = INTVAL (XEXP (varop, 1));
9914 unsigned HOST_WIDE_INT mask;
9917 /* We have one common special case. We can't do any merging if
9918 the inner code is an ASHIFTRT of a smaller mode. However, if
9919 we have (ashift:M1 (subreg:M1 (ashiftrt:M2 FOO C1) 0) C2)
9920 with C2 == GET_MODE_BITSIZE (M1) - GET_MODE_BITSIZE (M2),
9921 we can convert it to
9922 (ashiftrt:M1 (ashift:M1 (and:M1 (subreg:M1 FOO 0 C2) C3) C1).
9923 This simplifies certain SIGN_EXTEND operations. */
9924 if (code == ASHIFT && first_code == ASHIFTRT
9925 && count == (GET_MODE_BITSIZE (result_mode)
9926 - GET_MODE_BITSIZE (GET_MODE (varop))))
9928 /* C3 has the low-order C1 bits zero. */
9930 mask = (GET_MODE_MASK (mode)
9931 & ~(((HOST_WIDE_INT) 1 << first_count) - 1));
9933 varop = simplify_and_const_int (NULL_RTX, result_mode,
9934 XEXP (varop, 0), mask);
9935 varop = simplify_shift_const (NULL_RTX, ASHIFT, result_mode,
9937 count = first_count;
9942 /* If this was (ashiftrt (ashift foo C1) C2) and FOO has more
9943 than C1 high-order bits equal to the sign bit, we can convert
9944 this to either an ASHIFT or an ASHIFTRT depending on the
9947 We cannot do this if VAROP's mode is not SHIFT_MODE. */
9949 if (code == ASHIFTRT && first_code == ASHIFT
9950 && GET_MODE (varop) == shift_mode
9951 && (num_sign_bit_copies (XEXP (varop, 0), shift_mode)
9954 varop = XEXP (varop, 0);
9955 count -= first_count;
9965 /* There are some cases we can't do. If CODE is ASHIFTRT,
9966 we can only do this if FIRST_CODE is also ASHIFTRT.
9968 We can't do the case when CODE is ROTATE and FIRST_CODE is
9971 If the mode of this shift is not the mode of the outer shift,
9972 we can't do this if either shift is a right shift or ROTATE.
9974 Finally, we can't do any of these if the mode is too wide
9975 unless the codes are the same.
9977 Handle the case where the shift codes are the same
9980 if (code == first_code)
9982 if (GET_MODE (varop) != result_mode
9983 && (code == ASHIFTRT || code == LSHIFTRT
9987 count += first_count;
9988 varop = XEXP (varop, 0);
9992 if (code == ASHIFTRT
9993 || (code == ROTATE && first_code == ASHIFTRT)
9994 || GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT
9995 || (GET_MODE (varop) != result_mode
9996 && (first_code == ASHIFTRT || first_code == LSHIFTRT
9997 || first_code == ROTATE
9998 || code == ROTATE)))
10001 /* To compute the mask to apply after the shift, shift the
10002 nonzero bits of the inner shift the same way the
10003 outer shift will. */
10005 mask_rtx = GEN_INT (nonzero_bits (varop, GET_MODE (varop)));
10008 = simplify_const_binary_operation (code, result_mode, mask_rtx,
10011 /* Give up if we can't compute an outer operation to use. */
10013 || !CONST_INT_P (mask_rtx)
10014 || ! merge_outer_ops (&outer_op, &outer_const, AND,
10016 result_mode, &complement_p))
10019 /* If the shifts are in the same direction, we add the
10020 counts. Otherwise, we subtract them. */
10021 if ((code == ASHIFTRT || code == LSHIFTRT)
10022 == (first_code == ASHIFTRT || first_code == LSHIFTRT))
10023 count += first_count;
10025 count -= first_count;
10027 /* If COUNT is positive, the new shift is usually CODE,
10028 except for the two exceptions below, in which case it is
10029 FIRST_CODE. If the count is negative, FIRST_CODE should
10032 && ((first_code == ROTATE && code == ASHIFT)
10033 || (first_code == ASHIFTRT && code == LSHIFTRT)))
10035 else if (count < 0)
10036 code = first_code, count = -count;
10038 varop = XEXP (varop, 0);
10042 /* If we have (A << B << C) for any shift, we can convert this to
10043 (A << C << B). This wins if A is a constant. Only try this if
10044 B is not a constant. */
10046 else if (GET_CODE (varop) == code
10047 && CONST_INT_P (XEXP (varop, 0))
10048 && !CONST_INT_P (XEXP (varop, 1)))
10050 rtx new_rtx = simplify_const_binary_operation (code, mode,
10053 varop = gen_rtx_fmt_ee (code, mode, new_rtx, XEXP (varop, 1));
10060 if (VECTOR_MODE_P (mode))
10063 /* Make this fit the case below. */
10064 varop = gen_rtx_XOR (mode, XEXP (varop, 0),
10065 GEN_INT (GET_MODE_MASK (mode)));
10071 /* If we have (xshiftrt (ior (plus X (const_int -1)) X) C)
10072 with C the size of VAROP - 1 and the shift is logical if
10073 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
10074 we have an (le X 0) operation. If we have an arithmetic shift
10075 and STORE_FLAG_VALUE is 1 or we have a logical shift with
10076 STORE_FLAG_VALUE of -1, we have a (neg (le X 0)) operation. */
10078 if (GET_CODE (varop) == IOR && GET_CODE (XEXP (varop, 0)) == PLUS
10079 && XEXP (XEXP (varop, 0), 1) == constm1_rtx
10080 && (STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
10081 && (code == LSHIFTRT || code == ASHIFTRT)
10082 && count == (GET_MODE_BITSIZE (GET_MODE (varop)) - 1)
10083 && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
10086 varop = gen_rtx_LE (GET_MODE (varop), XEXP (varop, 1),
10089 if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
10090 varop = gen_rtx_NEG (GET_MODE (varop), varop);
10095 /* If we have (shift (logical)), move the logical to the outside
10096 to allow it to possibly combine with another logical and the
10097 shift to combine with another shift. This also canonicalizes to
10098 what a ZERO_EXTRACT looks like. Also, some machines have
10099 (and (shift)) insns. */
10101 if (CONST_INT_P (XEXP (varop, 1))
10102 /* We can't do this if we have (ashiftrt (xor)) and the
10103 constant has its sign bit set in shift_mode. */
10104 && !(code == ASHIFTRT && GET_CODE (varop) == XOR
10105 && 0 > trunc_int_for_mode (INTVAL (XEXP (varop, 1)),
10107 && (new_rtx = simplify_const_binary_operation (code, result_mode,
10109 GEN_INT (count))) != 0
10110 && CONST_INT_P (new_rtx)
10111 && merge_outer_ops (&outer_op, &outer_const, GET_CODE (varop),
10112 INTVAL (new_rtx), result_mode, &complement_p))
10114 varop = XEXP (varop, 0);
10118 /* If we can't do that, try to simplify the shift in each arm of the
10119 logical expression, make a new logical expression, and apply
10120 the inverse distributive law. This also can't be done
10121 for some (ashiftrt (xor)). */
10122 if (CONST_INT_P (XEXP (varop, 1))
10123 && !(code == ASHIFTRT && GET_CODE (varop) == XOR
10124 && 0 > trunc_int_for_mode (INTVAL (XEXP (varop, 1)),
10127 rtx lhs = simplify_shift_const (NULL_RTX, code, shift_mode,
10128 XEXP (varop, 0), count);
10129 rtx rhs = simplify_shift_const (NULL_RTX, code, shift_mode,
10130 XEXP (varop, 1), count);
10132 varop = simplify_gen_binary (GET_CODE (varop), shift_mode,
10134 varop = apply_distributive_law (varop);
10142 /* Convert (lshiftrt (eq FOO 0) C) to (xor FOO 1) if STORE_FLAG_VALUE
10143 says that the sign bit can be tested, FOO has mode MODE, C is
10144 GET_MODE_BITSIZE (MODE) - 1, and FOO has only its low-order bit
10145 that may be nonzero. */
10146 if (code == LSHIFTRT
10147 && XEXP (varop, 1) == const0_rtx
10148 && GET_MODE (XEXP (varop, 0)) == result_mode
10149 && count == (GET_MODE_BITSIZE (result_mode) - 1)
10150 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
10151 && STORE_FLAG_VALUE == -1
10152 && nonzero_bits (XEXP (varop, 0), result_mode) == 1
10153 && merge_outer_ops (&outer_op, &outer_const, XOR,
10154 (HOST_WIDE_INT) 1, result_mode,
10157 varop = XEXP (varop, 0);
10164 /* (lshiftrt (neg A) C) where A is either 0 or 1 and C is one less
10165 than the number of bits in the mode is equivalent to A. */
10166 if (code == LSHIFTRT
10167 && count == (GET_MODE_BITSIZE (result_mode) - 1)
10168 && nonzero_bits (XEXP (varop, 0), result_mode) == 1)
10170 varop = XEXP (varop, 0);
10175 /* NEG commutes with ASHIFT since it is multiplication. Move the
10176 NEG outside to allow shifts to combine. */
10178 && merge_outer_ops (&outer_op, &outer_const, NEG,
10179 (HOST_WIDE_INT) 0, result_mode,
10182 varop = XEXP (varop, 0);
10188 /* (lshiftrt (plus A -1) C) where A is either 0 or 1 and C
10189 is one less than the number of bits in the mode is
10190 equivalent to (xor A 1). */
10191 if (code == LSHIFTRT
10192 && count == (GET_MODE_BITSIZE (result_mode) - 1)
10193 && XEXP (varop, 1) == constm1_rtx
10194 && nonzero_bits (XEXP (varop, 0), result_mode) == 1
10195 && merge_outer_ops (&outer_op, &outer_const, XOR,
10196 (HOST_WIDE_INT) 1, result_mode,
10200 varop = XEXP (varop, 0);
10204 /* If we have (xshiftrt (plus FOO BAR) C), and the only bits
10205 that might be nonzero in BAR are those being shifted out and those
10206 bits are known zero in FOO, we can replace the PLUS with FOO.
10207 Similarly in the other operand order. This code occurs when
10208 we are computing the size of a variable-size array. */
10210 if ((code == ASHIFTRT || code == LSHIFTRT)
10211 && count < HOST_BITS_PER_WIDE_INT
10212 && nonzero_bits (XEXP (varop, 1), result_mode) >> count == 0
10213 && (nonzero_bits (XEXP (varop, 1), result_mode)
10214 & nonzero_bits (XEXP (varop, 0), result_mode)) == 0)
10216 varop = XEXP (varop, 0);
10219 else if ((code == ASHIFTRT || code == LSHIFTRT)
10220 && count < HOST_BITS_PER_WIDE_INT
10221 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
10222 && 0 == (nonzero_bits (XEXP (varop, 0), result_mode)
10224 && 0 == (nonzero_bits (XEXP (varop, 0), result_mode)
10225 & nonzero_bits (XEXP (varop, 1),
10228 varop = XEXP (varop, 1);
10232 /* (ashift (plus foo C) N) is (plus (ashift foo N) C'). */
10234 && CONST_INT_P (XEXP (varop, 1))
10235 && (new_rtx = simplify_const_binary_operation (ASHIFT, result_mode,
10237 GEN_INT (count))) != 0
10238 && CONST_INT_P (new_rtx)
10239 && merge_outer_ops (&outer_op, &outer_const, PLUS,
10240 INTVAL (new_rtx), result_mode, &complement_p))
10242 varop = XEXP (varop, 0);
10246 /* Check for 'PLUS signbit', which is the canonical form of 'XOR
10247 signbit', and attempt to change the PLUS to an XOR and move it to
10248 the outer operation as is done above in the AND/IOR/XOR case
10249 leg for shift(logical). See details in logical handling above
10250 for reasoning in doing so. */
10251 if (code == LSHIFTRT
10252 && CONST_INT_P (XEXP (varop, 1))
10253 && mode_signbit_p (result_mode, XEXP (varop, 1))
10254 && (new_rtx = simplify_const_binary_operation (code, result_mode,
10256 GEN_INT (count))) != 0
10257 && CONST_INT_P (new_rtx)
10258 && merge_outer_ops (&outer_op, &outer_const, XOR,
10259 INTVAL (new_rtx), result_mode, &complement_p))
10261 varop = XEXP (varop, 0);
10268 /* If we have (xshiftrt (minus (ashiftrt X C)) X) C)
10269 with C the size of VAROP - 1 and the shift is logical if
10270 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
10271 we have a (gt X 0) operation. If the shift is arithmetic with
10272 STORE_FLAG_VALUE of 1 or logical with STORE_FLAG_VALUE == -1,
10273 we have a (neg (gt X 0)) operation. */
10275 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
10276 && GET_CODE (XEXP (varop, 0)) == ASHIFTRT
10277 && count == (GET_MODE_BITSIZE (GET_MODE (varop)) - 1)
10278 && (code == LSHIFTRT || code == ASHIFTRT)
10279 && CONST_INT_P (XEXP (XEXP (varop, 0), 1))
10280 && INTVAL (XEXP (XEXP (varop, 0), 1)) == count
10281 && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
10284 varop = gen_rtx_GT (GET_MODE (varop), XEXP (varop, 1),
10287 if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
10288 varop = gen_rtx_NEG (GET_MODE (varop), varop);
10295 /* Change (lshiftrt (truncate (lshiftrt))) to (truncate (lshiftrt))
10296 if the truncate does not affect the value. */
10297 if (code == LSHIFTRT
10298 && GET_CODE (XEXP (varop, 0)) == LSHIFTRT
10299 && CONST_INT_P (XEXP (XEXP (varop, 0), 1))
10300 && (INTVAL (XEXP (XEXP (varop, 0), 1))
10301 >= (GET_MODE_BITSIZE (GET_MODE (XEXP (varop, 0)))
10302 - GET_MODE_BITSIZE (GET_MODE (varop)))))
10304 rtx varop_inner = XEXP (varop, 0);
10307 = gen_rtx_LSHIFTRT (GET_MODE (varop_inner),
10308 XEXP (varop_inner, 0),
10310 (count + INTVAL (XEXP (varop_inner, 1))));
10311 varop = gen_rtx_TRUNCATE (GET_MODE (varop), varop_inner);
10324 shift_mode = try_widen_shift_mode (code, varop, count, result_mode, mode,
10325 outer_op, outer_const);
10327 /* We have now finished analyzing the shift. The result should be
10328 a shift of type CODE with SHIFT_MODE shifting VAROP COUNT places. If
10329 OUTER_OP is non-UNKNOWN, it is an operation that needs to be applied
10330 to the result of the shift. OUTER_CONST is the relevant constant,
10331 but we must turn off all bits turned off in the shift. */
10333 if (outer_op == UNKNOWN
10334 && orig_code == code && orig_count == count
10335 && varop == orig_varop
10336 && shift_mode == GET_MODE (varop))
10339 /* Make a SUBREG if necessary. If we can't make it, fail. */
10340 varop = gen_lowpart (shift_mode, varop);
10341 if (varop == NULL_RTX || GET_CODE (varop) == CLOBBER)
10344 /* If we have an outer operation and we just made a shift, it is
10345 possible that we could have simplified the shift were it not
10346 for the outer operation. So try to do the simplification
10349 if (outer_op != UNKNOWN)
10350 x = simplify_shift_const_1 (code, shift_mode, varop, count);
10355 x = simplify_gen_binary (code, shift_mode, varop, GEN_INT (count));
10357 /* If we were doing an LSHIFTRT in a wider mode than it was originally,
10358 turn off all the bits that the shift would have turned off. */
10359 if (orig_code == LSHIFTRT && result_mode != shift_mode)
10360 x = simplify_and_const_int (NULL_RTX, shift_mode, x,
10361 GET_MODE_MASK (result_mode) >> orig_count);
10363 /* Do the remainder of the processing in RESULT_MODE. */
10364 x = gen_lowpart_or_truncate (result_mode, x);
10366 /* If COMPLEMENT_P is set, we have to complement X before doing the outer
10369 x = simplify_gen_unary (NOT, result_mode, x, result_mode);
10371 if (outer_op != UNKNOWN)
10373 if (GET_RTX_CLASS (outer_op) != RTX_UNARY
10374 && GET_MODE_BITSIZE (result_mode) < HOST_BITS_PER_WIDE_INT)
10375 outer_const = trunc_int_for_mode (outer_const, result_mode);
10377 if (outer_op == AND)
10378 x = simplify_and_const_int (NULL_RTX, result_mode, x, outer_const);
10379 else if (outer_op == SET)
10381 /* This means that we have determined that the result is
10382 equivalent to a constant. This should be rare. */
10383 if (!side_effects_p (x))
10384 x = GEN_INT (outer_const);
10386 else if (GET_RTX_CLASS (outer_op) == RTX_UNARY)
10387 x = simplify_gen_unary (outer_op, result_mode, x, result_mode);
10389 x = simplify_gen_binary (outer_op, result_mode, x,
10390 GEN_INT (outer_const));
10396 /* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift.
10397 The result of the shift is RESULT_MODE. If we cannot simplify it,
10398 return X or, if it is NULL, synthesize the expression with
10399 simplify_gen_binary. Otherwise, return a simplified value.
10401 The shift is normally computed in the widest mode we find in VAROP, as
10402 long as it isn't a different number of words than RESULT_MODE. Exceptions
10403 are ASHIFTRT and ROTATE, which are always done in their original mode. */
10406 simplify_shift_const (rtx x, enum rtx_code code, enum machine_mode result_mode,
10407 rtx varop, int count)
10409 rtx tem = simplify_shift_const_1 (code, result_mode, varop, count);
10414 x = simplify_gen_binary (code, GET_MODE (varop), varop, GEN_INT (count));
10415 if (GET_MODE (x) != result_mode)
10416 x = gen_lowpart (result_mode, x);
10421 /* Like recog, but we receive the address of a pointer to a new pattern.
10422 We try to match the rtx that the pointer points to.
10423 If that fails, we may try to modify or replace the pattern,
10424 storing the replacement into the same pointer object.
10426 Modifications include deletion or addition of CLOBBERs.
10428 PNOTES is a pointer to a location where any REG_UNUSED notes added for
10429 the CLOBBERs are placed.
10431 The value is the final insn code from the pattern ultimately matched,
10435 recog_for_combine (rtx *pnewpat, rtx insn, rtx *pnotes)
10437 rtx pat = *pnewpat;
10438 int insn_code_number;
10439 int num_clobbers_to_add = 0;
10442 rtx old_notes, old_pat;
10444 /* If PAT is a PARALLEL, check to see if it contains the CLOBBER
10445 we use to indicate that something didn't match. If we find such a
10446 thing, force rejection. */
10447 if (GET_CODE (pat) == PARALLEL)
10448 for (i = XVECLEN (pat, 0) - 1; i >= 0; i--)
10449 if (GET_CODE (XVECEXP (pat, 0, i)) == CLOBBER
10450 && XEXP (XVECEXP (pat, 0, i), 0) == const0_rtx)
10453 old_pat = PATTERN (insn);
10454 old_notes = REG_NOTES (insn);
10455 PATTERN (insn) = pat;
10456 REG_NOTES (insn) = 0;
10458 insn_code_number = recog (pat, insn, &num_clobbers_to_add);
10459 if (dump_file && (dump_flags & TDF_DETAILS))
10461 if (insn_code_number < 0)
10462 fputs ("Failed to match this instruction:\n", dump_file);
10464 fputs ("Successfully matched this instruction:\n", dump_file);
10465 print_rtl_single (dump_file, pat);
10468 /* If it isn't, there is the possibility that we previously had an insn
10469 that clobbered some register as a side effect, but the combined
10470 insn doesn't need to do that. So try once more without the clobbers
10471 unless this represents an ASM insn. */
10473 if (insn_code_number < 0 && ! check_asm_operands (pat)
10474 && GET_CODE (pat) == PARALLEL)
10478 for (pos = 0, i = 0; i < XVECLEN (pat, 0); i++)
10479 if (GET_CODE (XVECEXP (pat, 0, i)) != CLOBBER)
10482 SUBST (XVECEXP (pat, 0, pos), XVECEXP (pat, 0, i));
10486 SUBST_INT (XVECLEN (pat, 0), pos);
10489 pat = XVECEXP (pat, 0, 0);
10491 PATTERN (insn) = pat;
10492 insn_code_number = recog (pat, insn, &num_clobbers_to_add);
10493 if (dump_file && (dump_flags & TDF_DETAILS))
10495 if (insn_code_number < 0)
10496 fputs ("Failed to match this instruction:\n", dump_file);
10498 fputs ("Successfully matched this instruction:\n", dump_file);
10499 print_rtl_single (dump_file, pat);
10502 PATTERN (insn) = old_pat;
10503 REG_NOTES (insn) = old_notes;
10505 /* Recognize all noop sets, these will be killed by followup pass. */
10506 if (insn_code_number < 0 && GET_CODE (pat) == SET && set_noop_p (pat))
10507 insn_code_number = NOOP_MOVE_INSN_CODE, num_clobbers_to_add = 0;
10509 /* If we had any clobbers to add, make a new pattern than contains
10510 them. Then check to make sure that all of them are dead. */
10511 if (num_clobbers_to_add)
10513 rtx newpat = gen_rtx_PARALLEL (VOIDmode,
10514 rtvec_alloc (GET_CODE (pat) == PARALLEL
10515 ? (XVECLEN (pat, 0)
10516 + num_clobbers_to_add)
10517 : num_clobbers_to_add + 1));
10519 if (GET_CODE (pat) == PARALLEL)
10520 for (i = 0; i < XVECLEN (pat, 0); i++)
10521 XVECEXP (newpat, 0, i) = XVECEXP (pat, 0, i);
10523 XVECEXP (newpat, 0, 0) = pat;
10525 add_clobbers (newpat, insn_code_number);
10527 for (i = XVECLEN (newpat, 0) - num_clobbers_to_add;
10528 i < XVECLEN (newpat, 0); i++)
10530 if (REG_P (XEXP (XVECEXP (newpat, 0, i), 0))
10531 && ! reg_dead_at_p (XEXP (XVECEXP (newpat, 0, i), 0), insn))
10533 if (GET_CODE (XEXP (XVECEXP (newpat, 0, i), 0)) != SCRATCH)
10535 gcc_assert (REG_P (XEXP (XVECEXP (newpat, 0, i), 0)));
10536 notes = alloc_reg_note (REG_UNUSED,
10537 XEXP (XVECEXP (newpat, 0, i), 0), notes);
10546 return insn_code_number;
10549 /* Like gen_lowpart_general but for use by combine. In combine it
10550 is not possible to create any new pseudoregs. However, it is
10551 safe to create invalid memory addresses, because combine will
10552 try to recognize them and all they will do is make the combine
10555 If for some reason this cannot do its job, an rtx
10556 (clobber (const_int 0)) is returned.
10557 An insn containing that will not be recognized. */
10560 gen_lowpart_for_combine (enum machine_mode omode, rtx x)
10562 enum machine_mode imode = GET_MODE (x);
10563 unsigned int osize = GET_MODE_SIZE (omode);
10564 unsigned int isize = GET_MODE_SIZE (imode);
10567 if (omode == imode)
10570 /* Return identity if this is a CONST or symbolic reference. */
10572 && (GET_CODE (x) == CONST
10573 || GET_CODE (x) == SYMBOL_REF
10574 || GET_CODE (x) == LABEL_REF))
10577 /* We can only support MODE being wider than a word if X is a
10578 constant integer or has a mode the same size. */
10579 if (GET_MODE_SIZE (omode) > UNITS_PER_WORD
10580 && ! ((imode == VOIDmode
10581 && (CONST_INT_P (x)
10582 || GET_CODE (x) == CONST_DOUBLE))
10583 || isize == osize))
10586 /* X might be a paradoxical (subreg (mem)). In that case, gen_lowpart
10587 won't know what to do. So we will strip off the SUBREG here and
10588 process normally. */
10589 if (GET_CODE (x) == SUBREG && MEM_P (SUBREG_REG (x)))
10591 x = SUBREG_REG (x);
10593 /* For use in case we fall down into the address adjustments
10594 further below, we need to adjust the known mode and size of
10595 x; imode and isize, since we just adjusted x. */
10596 imode = GET_MODE (x);
10598 if (imode == omode)
10601 isize = GET_MODE_SIZE (imode);
10604 result = gen_lowpart_common (omode, x);
10613 /* Refuse to work on a volatile memory ref or one with a mode-dependent
10615 if (MEM_VOLATILE_P (x) || mode_dependent_address_p (XEXP (x, 0)))
10618 /* If we want to refer to something bigger than the original memref,
10619 generate a paradoxical subreg instead. That will force a reload
10620 of the original memref X. */
10622 return gen_rtx_SUBREG (omode, x, 0);
10624 if (WORDS_BIG_ENDIAN)
10625 offset = MAX (isize, UNITS_PER_WORD) - MAX (osize, UNITS_PER_WORD);
10627 /* Adjust the address so that the address-after-the-data is
10629 if (BYTES_BIG_ENDIAN)
10630 offset -= MIN (UNITS_PER_WORD, osize) - MIN (UNITS_PER_WORD, isize);
10632 return adjust_address_nv (x, omode, offset);
10635 /* If X is a comparison operator, rewrite it in a new mode. This
10636 probably won't match, but may allow further simplifications. */
10637 else if (COMPARISON_P (x))
10638 return gen_rtx_fmt_ee (GET_CODE (x), omode, XEXP (x, 0), XEXP (x, 1));
10640 /* If we couldn't simplify X any other way, just enclose it in a
10641 SUBREG. Normally, this SUBREG won't match, but some patterns may
10642 include an explicit SUBREG or we may simplify it further in combine. */
10648 offset = subreg_lowpart_offset (omode, imode);
10649 if (imode == VOIDmode)
10651 imode = int_mode_for_mode (omode);
10652 x = gen_lowpart_common (imode, x);
10656 res = simplify_gen_subreg (omode, x, imode, offset);
10662 return gen_rtx_CLOBBER (omode, const0_rtx);
10665 /* Simplify a comparison between *POP0 and *POP1 where CODE is the
10666 comparison code that will be tested.
10668 The result is a possibly different comparison code to use. *POP0 and
10669 *POP1 may be updated.
10671 It is possible that we might detect that a comparison is either always
10672 true or always false. However, we do not perform general constant
10673 folding in combine, so this knowledge isn't useful. Such tautologies
10674 should have been detected earlier. Hence we ignore all such cases. */
10676 static enum rtx_code
10677 simplify_comparison (enum rtx_code code, rtx *pop0, rtx *pop1)
10683 enum machine_mode mode, tmode;
10685 /* Try a few ways of applying the same transformation to both operands. */
10688 #ifndef WORD_REGISTER_OPERATIONS
10689 /* The test below this one won't handle SIGN_EXTENDs on these machines,
10690 so check specially. */
10691 if (code != GTU && code != GEU && code != LTU && code != LEU
10692 && GET_CODE (op0) == ASHIFTRT && GET_CODE (op1) == ASHIFTRT
10693 && GET_CODE (XEXP (op0, 0)) == ASHIFT
10694 && GET_CODE (XEXP (op1, 0)) == ASHIFT
10695 && GET_CODE (XEXP (XEXP (op0, 0), 0)) == SUBREG
10696 && GET_CODE (XEXP (XEXP (op1, 0), 0)) == SUBREG
10697 && (GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0)))
10698 == GET_MODE (SUBREG_REG (XEXP (XEXP (op1, 0), 0))))
10699 && CONST_INT_P (XEXP (op0, 1))
10700 && XEXP (op0, 1) == XEXP (op1, 1)
10701 && XEXP (op0, 1) == XEXP (XEXP (op0, 0), 1)
10702 && XEXP (op0, 1) == XEXP (XEXP (op1, 0), 1)
10703 && (INTVAL (XEXP (op0, 1))
10704 == (GET_MODE_BITSIZE (GET_MODE (op0))
10705 - (GET_MODE_BITSIZE
10706 (GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0))))))))
10708 op0 = SUBREG_REG (XEXP (XEXP (op0, 0), 0));
10709 op1 = SUBREG_REG (XEXP (XEXP (op1, 0), 0));
10713 /* If both operands are the same constant shift, see if we can ignore the
10714 shift. We can if the shift is a rotate or if the bits shifted out of
10715 this shift are known to be zero for both inputs and if the type of
10716 comparison is compatible with the shift. */
10717 if (GET_CODE (op0) == GET_CODE (op1)
10718 && GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
10719 && ((GET_CODE (op0) == ROTATE && (code == NE || code == EQ))
10720 || ((GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFT)
10721 && (code != GT && code != LT && code != GE && code != LE))
10722 || (GET_CODE (op0) == ASHIFTRT
10723 && (code != GTU && code != LTU
10724 && code != GEU && code != LEU)))
10725 && CONST_INT_P (XEXP (op0, 1))
10726 && INTVAL (XEXP (op0, 1)) >= 0
10727 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT
10728 && XEXP (op0, 1) == XEXP (op1, 1))
10730 enum machine_mode mode = GET_MODE (op0);
10731 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
10732 int shift_count = INTVAL (XEXP (op0, 1));
10734 if (GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFTRT)
10735 mask &= (mask >> shift_count) << shift_count;
10736 else if (GET_CODE (op0) == ASHIFT)
10737 mask = (mask & (mask << shift_count)) >> shift_count;
10739 if ((nonzero_bits (XEXP (op0, 0), mode) & ~mask) == 0
10740 && (nonzero_bits (XEXP (op1, 0), mode) & ~mask) == 0)
10741 op0 = XEXP (op0, 0), op1 = XEXP (op1, 0);
10746 /* If both operands are AND's of a paradoxical SUBREG by constant, the
10747 SUBREGs are of the same mode, and, in both cases, the AND would
10748 be redundant if the comparison was done in the narrower mode,
10749 do the comparison in the narrower mode (e.g., we are AND'ing with 1
10750 and the operand's possibly nonzero bits are 0xffffff01; in that case
10751 if we only care about QImode, we don't need the AND). This case
10752 occurs if the output mode of an scc insn is not SImode and
10753 STORE_FLAG_VALUE == 1 (e.g., the 386).
10755 Similarly, check for a case where the AND's are ZERO_EXTEND
10756 operations from some narrower mode even though a SUBREG is not
10759 else if (GET_CODE (op0) == AND && GET_CODE (op1) == AND
10760 && CONST_INT_P (XEXP (op0, 1))
10761 && CONST_INT_P (XEXP (op1, 1)))
10763 rtx inner_op0 = XEXP (op0, 0);
10764 rtx inner_op1 = XEXP (op1, 0);
10765 HOST_WIDE_INT c0 = INTVAL (XEXP (op0, 1));
10766 HOST_WIDE_INT c1 = INTVAL (XEXP (op1, 1));
10769 if (GET_CODE (inner_op0) == SUBREG && GET_CODE (inner_op1) == SUBREG
10770 && (GET_MODE_SIZE (GET_MODE (inner_op0))
10771 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (inner_op0))))
10772 && (GET_MODE (SUBREG_REG (inner_op0))
10773 == GET_MODE (SUBREG_REG (inner_op1)))
10774 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (inner_op0)))
10775 <= HOST_BITS_PER_WIDE_INT)
10776 && (0 == ((~c0) & nonzero_bits (SUBREG_REG (inner_op0),
10777 GET_MODE (SUBREG_REG (inner_op0)))))
10778 && (0 == ((~c1) & nonzero_bits (SUBREG_REG (inner_op1),
10779 GET_MODE (SUBREG_REG (inner_op1))))))
10781 op0 = SUBREG_REG (inner_op0);
10782 op1 = SUBREG_REG (inner_op1);
10784 /* The resulting comparison is always unsigned since we masked
10785 off the original sign bit. */
10786 code = unsigned_condition (code);
10792 for (tmode = GET_CLASS_NARROWEST_MODE
10793 (GET_MODE_CLASS (GET_MODE (op0)));
10794 tmode != GET_MODE (op0); tmode = GET_MODE_WIDER_MODE (tmode))
10795 if ((unsigned HOST_WIDE_INT) c0 == GET_MODE_MASK (tmode))
10797 op0 = gen_lowpart (tmode, inner_op0);
10798 op1 = gen_lowpart (tmode, inner_op1);
10799 code = unsigned_condition (code);
10808 /* If both operands are NOT, we can strip off the outer operation
10809 and adjust the comparison code for swapped operands; similarly for
10810 NEG, except that this must be an equality comparison. */
10811 else if ((GET_CODE (op0) == NOT && GET_CODE (op1) == NOT)
10812 || (GET_CODE (op0) == NEG && GET_CODE (op1) == NEG
10813 && (code == EQ || code == NE)))
10814 op0 = XEXP (op0, 0), op1 = XEXP (op1, 0), code = swap_condition (code);
10820 /* If the first operand is a constant, swap the operands and adjust the
10821 comparison code appropriately, but don't do this if the second operand
10822 is already a constant integer. */
10823 if (swap_commutative_operands_p (op0, op1))
10825 tem = op0, op0 = op1, op1 = tem;
10826 code = swap_condition (code);
10829 /* We now enter a loop during which we will try to simplify the comparison.
10830 For the most part, we only are concerned with comparisons with zero,
10831 but some things may really be comparisons with zero but not start
10832 out looking that way. */
10834 while (CONST_INT_P (op1))
10836 enum machine_mode mode = GET_MODE (op0);
10837 unsigned int mode_width = GET_MODE_BITSIZE (mode);
10838 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
10839 int equality_comparison_p;
10840 int sign_bit_comparison_p;
10841 int unsigned_comparison_p;
10842 HOST_WIDE_INT const_op;
10844 /* We only want to handle integral modes. This catches VOIDmode,
10845 CCmode, and the floating-point modes. An exception is that we
10846 can handle VOIDmode if OP0 is a COMPARE or a comparison
10849 if (GET_MODE_CLASS (mode) != MODE_INT
10850 && ! (mode == VOIDmode
10851 && (GET_CODE (op0) == COMPARE || COMPARISON_P (op0))))
10854 /* Get the constant we are comparing against and turn off all bits
10855 not on in our mode. */
10856 const_op = INTVAL (op1);
10857 if (mode != VOIDmode)
10858 const_op = trunc_int_for_mode (const_op, mode);
10859 op1 = GEN_INT (const_op);
10861 /* If we are comparing against a constant power of two and the value
10862 being compared can only have that single bit nonzero (e.g., it was
10863 `and'ed with that bit), we can replace this with a comparison
10866 && (code == EQ || code == NE || code == GE || code == GEU
10867 || code == LT || code == LTU)
10868 && mode_width <= HOST_BITS_PER_WIDE_INT
10869 && exact_log2 (const_op) >= 0
10870 && nonzero_bits (op0, mode) == (unsigned HOST_WIDE_INT) const_op)
10872 code = (code == EQ || code == GE || code == GEU ? NE : EQ);
10873 op1 = const0_rtx, const_op = 0;
10876 /* Similarly, if we are comparing a value known to be either -1 or
10877 0 with -1, change it to the opposite comparison against zero. */
10880 && (code == EQ || code == NE || code == GT || code == LE
10881 || code == GEU || code == LTU)
10882 && num_sign_bit_copies (op0, mode) == mode_width)
10884 code = (code == EQ || code == LE || code == GEU ? NE : EQ);
10885 op1 = const0_rtx, const_op = 0;
10888 /* Do some canonicalizations based on the comparison code. We prefer
10889 comparisons against zero and then prefer equality comparisons.
10890 If we can reduce the size of a constant, we will do that too. */
10895 /* < C is equivalent to <= (C - 1) */
10899 op1 = GEN_INT (const_op);
10901 /* ... fall through to LE case below. */
10907 /* <= C is equivalent to < (C + 1); we do this for C < 0 */
10911 op1 = GEN_INT (const_op);
10915 /* If we are doing a <= 0 comparison on a value known to have
10916 a zero sign bit, we can replace this with == 0. */
10917 else if (const_op == 0
10918 && mode_width <= HOST_BITS_PER_WIDE_INT
10919 && (nonzero_bits (op0, mode)
10920 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)
10925 /* >= C is equivalent to > (C - 1). */
10929 op1 = GEN_INT (const_op);
10931 /* ... fall through to GT below. */
10937 /* > C is equivalent to >= (C + 1); we do this for C < 0. */
10941 op1 = GEN_INT (const_op);
10945 /* If we are doing a > 0 comparison on a value known to have
10946 a zero sign bit, we can replace this with != 0. */
10947 else if (const_op == 0
10948 && mode_width <= HOST_BITS_PER_WIDE_INT
10949 && (nonzero_bits (op0, mode)
10950 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)
10955 /* < C is equivalent to <= (C - 1). */
10959 op1 = GEN_INT (const_op);
10961 /* ... fall through ... */
10964 /* (unsigned) < 0x80000000 is equivalent to >= 0. */
10965 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
10966 && (const_op == (HOST_WIDE_INT) 1 << (mode_width - 1)))
10968 const_op = 0, op1 = const0_rtx;
10976 /* unsigned <= 0 is equivalent to == 0 */
10980 /* (unsigned) <= 0x7fffffff is equivalent to >= 0. */
10981 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
10982 && (const_op == ((HOST_WIDE_INT) 1 << (mode_width - 1)) - 1))
10984 const_op = 0, op1 = const0_rtx;
10990 /* >= C is equivalent to > (C - 1). */
10994 op1 = GEN_INT (const_op);
10996 /* ... fall through ... */
10999 /* (unsigned) >= 0x80000000 is equivalent to < 0. */
11000 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
11001 && (const_op == (HOST_WIDE_INT) 1 << (mode_width - 1)))
11003 const_op = 0, op1 = const0_rtx;
11011 /* unsigned > 0 is equivalent to != 0 */
11015 /* (unsigned) > 0x7fffffff is equivalent to < 0. */
11016 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
11017 && (const_op == ((HOST_WIDE_INT) 1 << (mode_width - 1)) - 1))
11019 const_op = 0, op1 = const0_rtx;
11028 /* Compute some predicates to simplify code below. */
11030 equality_comparison_p = (code == EQ || code == NE);
11031 sign_bit_comparison_p = ((code == LT || code == GE) && const_op == 0);
11032 unsigned_comparison_p = (code == LTU || code == LEU || code == GTU
11035 /* If this is a sign bit comparison and we can do arithmetic in
11036 MODE, say that we will only be needing the sign bit of OP0. */
11037 if (sign_bit_comparison_p
11038 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
11039 op0 = force_to_mode (op0, mode,
11041 << (GET_MODE_BITSIZE (mode) - 1)),
11044 /* Now try cases based on the opcode of OP0. If none of the cases
11045 does a "continue", we exit this loop immediately after the
11048 switch (GET_CODE (op0))
11051 /* If we are extracting a single bit from a variable position in
11052 a constant that has only a single bit set and are comparing it
11053 with zero, we can convert this into an equality comparison
11054 between the position and the location of the single bit. */
11055 /* Except we can't if SHIFT_COUNT_TRUNCATED is set, since we might
11056 have already reduced the shift count modulo the word size. */
11057 if (!SHIFT_COUNT_TRUNCATED
11058 && CONST_INT_P (XEXP (op0, 0))
11059 && XEXP (op0, 1) == const1_rtx
11060 && equality_comparison_p && const_op == 0
11061 && (i = exact_log2 (INTVAL (XEXP (op0, 0)))) >= 0)
11063 if (BITS_BIG_ENDIAN)
11065 enum machine_mode new_mode
11066 = mode_for_extraction (EP_extzv, 1);
11067 if (new_mode == MAX_MACHINE_MODE)
11068 i = BITS_PER_WORD - 1 - i;
11072 i = (GET_MODE_BITSIZE (mode) - 1 - i);
11076 op0 = XEXP (op0, 2);
11080 /* Result is nonzero iff shift count is equal to I. */
11081 code = reverse_condition (code);
11085 /* ... fall through ... */
11088 tem = expand_compound_operation (op0);
11097 /* If testing for equality, we can take the NOT of the constant. */
11098 if (equality_comparison_p
11099 && (tem = simplify_unary_operation (NOT, mode, op1, mode)) != 0)
11101 op0 = XEXP (op0, 0);
11106 /* If just looking at the sign bit, reverse the sense of the
11108 if (sign_bit_comparison_p)
11110 op0 = XEXP (op0, 0);
11111 code = (code == GE ? LT : GE);
11117 /* If testing for equality, we can take the NEG of the constant. */
11118 if (equality_comparison_p
11119 && (tem = simplify_unary_operation (NEG, mode, op1, mode)) != 0)
11121 op0 = XEXP (op0, 0);
11126 /* The remaining cases only apply to comparisons with zero. */
11130 /* When X is ABS or is known positive,
11131 (neg X) is < 0 if and only if X != 0. */
11133 if (sign_bit_comparison_p
11134 && (GET_CODE (XEXP (op0, 0)) == ABS
11135 || (mode_width <= HOST_BITS_PER_WIDE_INT
11136 && (nonzero_bits (XEXP (op0, 0), mode)
11137 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)))
11139 op0 = XEXP (op0, 0);
11140 code = (code == LT ? NE : EQ);
11144 /* If we have NEG of something whose two high-order bits are the
11145 same, we know that "(-a) < 0" is equivalent to "a > 0". */
11146 if (num_sign_bit_copies (op0, mode) >= 2)
11148 op0 = XEXP (op0, 0);
11149 code = swap_condition (code);
11155 /* If we are testing equality and our count is a constant, we
11156 can perform the inverse operation on our RHS. */
11157 if (equality_comparison_p && CONST_INT_P (XEXP (op0, 1))
11158 && (tem = simplify_binary_operation (ROTATERT, mode,
11159 op1, XEXP (op0, 1))) != 0)
11161 op0 = XEXP (op0, 0);
11166 /* If we are doing a < 0 or >= 0 comparison, it means we are testing
11167 a particular bit. Convert it to an AND of a constant of that
11168 bit. This will be converted into a ZERO_EXTRACT. */
11169 if (const_op == 0 && sign_bit_comparison_p
11170 && CONST_INT_P (XEXP (op0, 1))
11171 && mode_width <= HOST_BITS_PER_WIDE_INT)
11173 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
11176 - INTVAL (XEXP (op0, 1)))));
11177 code = (code == LT ? NE : EQ);
11181 /* Fall through. */
11184 /* ABS is ignorable inside an equality comparison with zero. */
11185 if (const_op == 0 && equality_comparison_p)
11187 op0 = XEXP (op0, 0);
11193 /* Can simplify (compare (zero/sign_extend FOO) CONST) to
11194 (compare FOO CONST) if CONST fits in FOO's mode and we
11195 are either testing inequality or have an unsigned
11196 comparison with ZERO_EXTEND or a signed comparison with
11197 SIGN_EXTEND. But don't do it if we don't have a compare
11198 insn of the given mode, since we'd have to revert it
11199 later on, and then we wouldn't know whether to sign- or
11201 mode = GET_MODE (XEXP (op0, 0));
11202 if (mode != VOIDmode && GET_MODE_CLASS (mode) == MODE_INT
11203 && ! unsigned_comparison_p
11204 && (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
11205 && ((unsigned HOST_WIDE_INT) const_op
11206 < (((unsigned HOST_WIDE_INT) 1
11207 << (GET_MODE_BITSIZE (mode) - 1))))
11208 && have_insn_for (COMPARE, mode))
11210 op0 = XEXP (op0, 0);
11216 /* Check for the case where we are comparing A - C1 with C2, that is
11218 (subreg:MODE (plus (A) (-C1))) op (C2)
11220 with C1 a constant, and try to lift the SUBREG, i.e. to do the
11221 comparison in the wider mode. One of the following two conditions
11222 must be true in order for this to be valid:
11224 1. The mode extension results in the same bit pattern being added
11225 on both sides and the comparison is equality or unsigned. As
11226 C2 has been truncated to fit in MODE, the pattern can only be
11229 2. The mode extension results in the sign bit being copied on
11232 The difficulty here is that we have predicates for A but not for
11233 (A - C1) so we need to check that C1 is within proper bounds so
11234 as to perturbate A as little as possible. */
11236 if (mode_width <= HOST_BITS_PER_WIDE_INT
11237 && subreg_lowpart_p (op0)
11238 && GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0))) > mode_width
11239 && GET_CODE (SUBREG_REG (op0)) == PLUS
11240 && CONST_INT_P (XEXP (SUBREG_REG (op0), 1)))
11242 enum machine_mode inner_mode = GET_MODE (SUBREG_REG (op0));
11243 rtx a = XEXP (SUBREG_REG (op0), 0);
11244 HOST_WIDE_INT c1 = -INTVAL (XEXP (SUBREG_REG (op0), 1));
11247 && (unsigned HOST_WIDE_INT) c1
11248 < (unsigned HOST_WIDE_INT) 1 << (mode_width - 1)
11249 && (equality_comparison_p || unsigned_comparison_p)
11250 /* (A - C1) zero-extends if it is positive and sign-extends
11251 if it is negative, C2 both zero- and sign-extends. */
11252 && ((0 == (nonzero_bits (a, inner_mode)
11253 & ~GET_MODE_MASK (mode))
11255 /* (A - C1) sign-extends if it is positive and 1-extends
11256 if it is negative, C2 both sign- and 1-extends. */
11257 || (num_sign_bit_copies (a, inner_mode)
11258 > (unsigned int) (GET_MODE_BITSIZE (inner_mode)
11261 || ((unsigned HOST_WIDE_INT) c1
11262 < (unsigned HOST_WIDE_INT) 1 << (mode_width - 2)
11263 /* (A - C1) always sign-extends, like C2. */
11264 && num_sign_bit_copies (a, inner_mode)
11265 > (unsigned int) (GET_MODE_BITSIZE (inner_mode)
11266 - (mode_width - 1))))
11268 op0 = SUBREG_REG (op0);
11273 /* If the inner mode is narrower and we are extracting the low part,
11274 we can treat the SUBREG as if it were a ZERO_EXTEND. */
11275 if (subreg_lowpart_p (op0)
11276 && GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0))) < mode_width)
11277 /* Fall through */ ;
11281 /* ... fall through ... */
11284 mode = GET_MODE (XEXP (op0, 0));
11285 if (mode != VOIDmode && GET_MODE_CLASS (mode) == MODE_INT
11286 && (unsigned_comparison_p || equality_comparison_p)
11287 && (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
11288 && ((unsigned HOST_WIDE_INT) const_op < GET_MODE_MASK (mode))
11289 && have_insn_for (COMPARE, mode))
11291 op0 = XEXP (op0, 0);
11297 /* (eq (plus X A) B) -> (eq X (minus B A)). We can only do
11298 this for equality comparisons due to pathological cases involving
11300 if (equality_comparison_p
11301 && 0 != (tem = simplify_binary_operation (MINUS, mode,
11302 op1, XEXP (op0, 1))))
11304 op0 = XEXP (op0, 0);
11309 /* (plus (abs X) (const_int -1)) is < 0 if and only if X == 0. */
11310 if (const_op == 0 && XEXP (op0, 1) == constm1_rtx
11311 && GET_CODE (XEXP (op0, 0)) == ABS && sign_bit_comparison_p)
11313 op0 = XEXP (XEXP (op0, 0), 0);
11314 code = (code == LT ? EQ : NE);
11320 /* We used to optimize signed comparisons against zero, but that
11321 was incorrect. Unsigned comparisons against zero (GTU, LEU)
11322 arrive here as equality comparisons, or (GEU, LTU) are
11323 optimized away. No need to special-case them. */
11325 /* (eq (minus A B) C) -> (eq A (plus B C)) or
11326 (eq B (minus A C)), whichever simplifies. We can only do
11327 this for equality comparisons due to pathological cases involving
11329 if (equality_comparison_p
11330 && 0 != (tem = simplify_binary_operation (PLUS, mode,
11331 XEXP (op0, 1), op1)))
11333 op0 = XEXP (op0, 0);
11338 if (equality_comparison_p
11339 && 0 != (tem = simplify_binary_operation (MINUS, mode,
11340 XEXP (op0, 0), op1)))
11342 op0 = XEXP (op0, 1);
11347 /* The sign bit of (minus (ashiftrt X C) X), where C is the number
11348 of bits in X minus 1, is one iff X > 0. */
11349 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == ASHIFTRT
11350 && CONST_INT_P (XEXP (XEXP (op0, 0), 1))
11351 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (XEXP (op0, 0), 1))
11353 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
11355 op0 = XEXP (op0, 1);
11356 code = (code == GE ? LE : GT);
11362 /* (eq (xor A B) C) -> (eq A (xor B C)). This is a simplification
11363 if C is zero or B is a constant. */
11364 if (equality_comparison_p
11365 && 0 != (tem = simplify_binary_operation (XOR, mode,
11366 XEXP (op0, 1), op1)))
11368 op0 = XEXP (op0, 0);
11375 case UNEQ: case LTGT:
11376 case LT: case LTU: case UNLT: case LE: case LEU: case UNLE:
11377 case GT: case GTU: case UNGT: case GE: case GEU: case UNGE:
11378 case UNORDERED: case ORDERED:
11379 /* We can't do anything if OP0 is a condition code value, rather
11380 than an actual data value. */
11382 || CC0_P (XEXP (op0, 0))
11383 || GET_MODE_CLASS (GET_MODE (XEXP (op0, 0))) == MODE_CC)
11386 /* Get the two operands being compared. */
11387 if (GET_CODE (XEXP (op0, 0)) == COMPARE)
11388 tem = XEXP (XEXP (op0, 0), 0), tem1 = XEXP (XEXP (op0, 0), 1);
11390 tem = XEXP (op0, 0), tem1 = XEXP (op0, 1);
11392 /* Check for the cases where we simply want the result of the
11393 earlier test or the opposite of that result. */
11394 if (code == NE || code == EQ
11395 || (GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
11396 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
11397 && (STORE_FLAG_VALUE
11398 & (((HOST_WIDE_INT) 1
11399 << (GET_MODE_BITSIZE (GET_MODE (op0)) - 1))))
11400 && (code == LT || code == GE)))
11402 enum rtx_code new_code;
11403 if (code == LT || code == NE)
11404 new_code = GET_CODE (op0);
11406 new_code = reversed_comparison_code (op0, NULL);
11408 if (new_code != UNKNOWN)
11419 /* The sign bit of (ior (plus X (const_int -1)) X) is nonzero
11421 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == PLUS
11422 && XEXP (XEXP (op0, 0), 1) == constm1_rtx
11423 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
11425 op0 = XEXP (op0, 1);
11426 code = (code == GE ? GT : LE);
11432 /* Convert (and (xshift 1 X) Y) to (and (lshiftrt Y X) 1). This
11433 will be converted to a ZERO_EXTRACT later. */
11434 if (const_op == 0 && equality_comparison_p
11435 && GET_CODE (XEXP (op0, 0)) == ASHIFT
11436 && XEXP (XEXP (op0, 0), 0) == const1_rtx)
11438 op0 = simplify_and_const_int
11439 (NULL_RTX, mode, gen_rtx_LSHIFTRT (mode,
11441 XEXP (XEXP (op0, 0), 1)),
11442 (HOST_WIDE_INT) 1);
11446 /* If we are comparing (and (lshiftrt X C1) C2) for equality with
11447 zero and X is a comparison and C1 and C2 describe only bits set
11448 in STORE_FLAG_VALUE, we can compare with X. */
11449 if (const_op == 0 && equality_comparison_p
11450 && mode_width <= HOST_BITS_PER_WIDE_INT
11451 && CONST_INT_P (XEXP (op0, 1))
11452 && GET_CODE (XEXP (op0, 0)) == LSHIFTRT
11453 && CONST_INT_P (XEXP (XEXP (op0, 0), 1))
11454 && INTVAL (XEXP (XEXP (op0, 0), 1)) >= 0
11455 && INTVAL (XEXP (XEXP (op0, 0), 1)) < HOST_BITS_PER_WIDE_INT)
11457 mask = ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
11458 << INTVAL (XEXP (XEXP (op0, 0), 1)));
11459 if ((~STORE_FLAG_VALUE & mask) == 0
11460 && (COMPARISON_P (XEXP (XEXP (op0, 0), 0))
11461 || ((tem = get_last_value (XEXP (XEXP (op0, 0), 0))) != 0
11462 && COMPARISON_P (tem))))
11464 op0 = XEXP (XEXP (op0, 0), 0);
11469 /* If we are doing an equality comparison of an AND of a bit equal
11470 to the sign bit, replace this with a LT or GE comparison of
11471 the underlying value. */
11472 if (equality_comparison_p
11474 && CONST_INT_P (XEXP (op0, 1))
11475 && mode_width <= HOST_BITS_PER_WIDE_INT
11476 && ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
11477 == (unsigned HOST_WIDE_INT) 1 << (mode_width - 1)))
11479 op0 = XEXP (op0, 0);
11480 code = (code == EQ ? GE : LT);
11484 /* If this AND operation is really a ZERO_EXTEND from a narrower
11485 mode, the constant fits within that mode, and this is either an
11486 equality or unsigned comparison, try to do this comparison in
11491 (ne:DI (and:DI (reg:DI 4) (const_int 0xffffffff)) (const_int 0))
11492 -> (ne:DI (reg:SI 4) (const_int 0))
11494 unless TRULY_NOOP_TRUNCATION allows it or the register is
11495 known to hold a value of the required mode the
11496 transformation is invalid. */
11497 if ((equality_comparison_p || unsigned_comparison_p)
11498 && CONST_INT_P (XEXP (op0, 1))
11499 && (i = exact_log2 ((INTVAL (XEXP (op0, 1))
11500 & GET_MODE_MASK (mode))
11502 && const_op >> i == 0
11503 && (tmode = mode_for_size (i, MODE_INT, 1)) != BLKmode
11504 && (TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (tmode),
11505 GET_MODE_BITSIZE (GET_MODE (op0)))
11506 || (REG_P (XEXP (op0, 0))
11507 && reg_truncated_to_mode (tmode, XEXP (op0, 0)))))
11509 op0 = gen_lowpart (tmode, XEXP (op0, 0));
11513 /* If this is (and:M1 (subreg:M2 X 0) (const_int C1)) where C1
11514 fits in both M1 and M2 and the SUBREG is either paradoxical
11515 or represents the low part, permute the SUBREG and the AND
11517 if (GET_CODE (XEXP (op0, 0)) == SUBREG)
11519 unsigned HOST_WIDE_INT c1;
11520 tmode = GET_MODE (SUBREG_REG (XEXP (op0, 0)));
11521 /* Require an integral mode, to avoid creating something like
11523 if (SCALAR_INT_MODE_P (tmode)
11524 /* It is unsafe to commute the AND into the SUBREG if the
11525 SUBREG is paradoxical and WORD_REGISTER_OPERATIONS is
11526 not defined. As originally written the upper bits
11527 have a defined value due to the AND operation.
11528 However, if we commute the AND inside the SUBREG then
11529 they no longer have defined values and the meaning of
11530 the code has been changed. */
11532 #ifdef WORD_REGISTER_OPERATIONS
11533 || (mode_width > GET_MODE_BITSIZE (tmode)
11534 && mode_width <= BITS_PER_WORD)
11536 || (mode_width <= GET_MODE_BITSIZE (tmode)
11537 && subreg_lowpart_p (XEXP (op0, 0))))
11538 && CONST_INT_P (XEXP (op0, 1))
11539 && mode_width <= HOST_BITS_PER_WIDE_INT
11540 && GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT
11541 && ((c1 = INTVAL (XEXP (op0, 1))) & ~mask) == 0
11542 && (c1 & ~GET_MODE_MASK (tmode)) == 0
11544 && c1 != GET_MODE_MASK (tmode))
11546 op0 = simplify_gen_binary (AND, tmode,
11547 SUBREG_REG (XEXP (op0, 0)),
11548 gen_int_mode (c1, tmode));
11549 op0 = gen_lowpart (mode, op0);
11554 /* Convert (ne (and (not X) 1) 0) to (eq (and X 1) 0). */
11555 if (const_op == 0 && equality_comparison_p
11556 && XEXP (op0, 1) == const1_rtx
11557 && GET_CODE (XEXP (op0, 0)) == NOT)
11559 op0 = simplify_and_const_int
11560 (NULL_RTX, mode, XEXP (XEXP (op0, 0), 0), (HOST_WIDE_INT) 1);
11561 code = (code == NE ? EQ : NE);
11565 /* Convert (ne (and (lshiftrt (not X)) 1) 0) to
11566 (eq (and (lshiftrt X) 1) 0).
11567 Also handle the case where (not X) is expressed using xor. */
11568 if (const_op == 0 && equality_comparison_p
11569 && XEXP (op0, 1) == const1_rtx
11570 && GET_CODE (XEXP (op0, 0)) == LSHIFTRT)
11572 rtx shift_op = XEXP (XEXP (op0, 0), 0);
11573 rtx shift_count = XEXP (XEXP (op0, 0), 1);
11575 if (GET_CODE (shift_op) == NOT
11576 || (GET_CODE (shift_op) == XOR
11577 && CONST_INT_P (XEXP (shift_op, 1))
11578 && CONST_INT_P (shift_count)
11579 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
11580 && (INTVAL (XEXP (shift_op, 1))
11581 == (HOST_WIDE_INT) 1 << INTVAL (shift_count))))
11583 op0 = simplify_and_const_int
11585 gen_rtx_LSHIFTRT (mode, XEXP (shift_op, 0), shift_count),
11586 (HOST_WIDE_INT) 1);
11587 code = (code == NE ? EQ : NE);
11594 /* If we have (compare (ashift FOO N) (const_int C)) and
11595 the high order N bits of FOO (N+1 if an inequality comparison)
11596 are known to be zero, we can do this by comparing FOO with C
11597 shifted right N bits so long as the low-order N bits of C are
11599 if (CONST_INT_P (XEXP (op0, 1))
11600 && INTVAL (XEXP (op0, 1)) >= 0
11601 && ((INTVAL (XEXP (op0, 1)) + ! equality_comparison_p)
11602 < HOST_BITS_PER_WIDE_INT)
11604 & (((HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1))) - 1)) == 0)
11605 && mode_width <= HOST_BITS_PER_WIDE_INT
11606 && (nonzero_bits (XEXP (op0, 0), mode)
11607 & ~(mask >> (INTVAL (XEXP (op0, 1))
11608 + ! equality_comparison_p))) == 0)
11610 /* We must perform a logical shift, not an arithmetic one,
11611 as we want the top N bits of C to be zero. */
11612 unsigned HOST_WIDE_INT temp = const_op & GET_MODE_MASK (mode);
11614 temp >>= INTVAL (XEXP (op0, 1));
11615 op1 = gen_int_mode (temp, mode);
11616 op0 = XEXP (op0, 0);
11620 /* If we are doing a sign bit comparison, it means we are testing
11621 a particular bit. Convert it to the appropriate AND. */
11622 if (sign_bit_comparison_p && CONST_INT_P (XEXP (op0, 1))
11623 && mode_width <= HOST_BITS_PER_WIDE_INT)
11625 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
11628 - INTVAL (XEXP (op0, 1)))));
11629 code = (code == LT ? NE : EQ);
11633 /* If this an equality comparison with zero and we are shifting
11634 the low bit to the sign bit, we can convert this to an AND of the
11636 if (const_op == 0 && equality_comparison_p
11637 && CONST_INT_P (XEXP (op0, 1))
11638 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (op0, 1))
11641 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
11642 (HOST_WIDE_INT) 1);
11648 /* If this is an equality comparison with zero, we can do this
11649 as a logical shift, which might be much simpler. */
11650 if (equality_comparison_p && const_op == 0
11651 && CONST_INT_P (XEXP (op0, 1)))
11653 op0 = simplify_shift_const (NULL_RTX, LSHIFTRT, mode,
11655 INTVAL (XEXP (op0, 1)));
11659 /* If OP0 is a sign extension and CODE is not an unsigned comparison,
11660 do the comparison in a narrower mode. */
11661 if (! unsigned_comparison_p
11662 && CONST_INT_P (XEXP (op0, 1))
11663 && GET_CODE (XEXP (op0, 0)) == ASHIFT
11664 && XEXP (op0, 1) == XEXP (XEXP (op0, 0), 1)
11665 && (tmode = mode_for_size (mode_width - INTVAL (XEXP (op0, 1)),
11666 MODE_INT, 1)) != BLKmode
11667 && (((unsigned HOST_WIDE_INT) const_op
11668 + (GET_MODE_MASK (tmode) >> 1) + 1)
11669 <= GET_MODE_MASK (tmode)))
11671 op0 = gen_lowpart (tmode, XEXP (XEXP (op0, 0), 0));
11675 /* Likewise if OP0 is a PLUS of a sign extension with a
11676 constant, which is usually represented with the PLUS
11677 between the shifts. */
11678 if (! unsigned_comparison_p
11679 && CONST_INT_P (XEXP (op0, 1))
11680 && GET_CODE (XEXP (op0, 0)) == PLUS
11681 && CONST_INT_P (XEXP (XEXP (op0, 0), 1))
11682 && GET_CODE (XEXP (XEXP (op0, 0), 0)) == ASHIFT
11683 && XEXP (op0, 1) == XEXP (XEXP (XEXP (op0, 0), 0), 1)
11684 && (tmode = mode_for_size (mode_width - INTVAL (XEXP (op0, 1)),
11685 MODE_INT, 1)) != BLKmode
11686 && (((unsigned HOST_WIDE_INT) const_op
11687 + (GET_MODE_MASK (tmode) >> 1) + 1)
11688 <= GET_MODE_MASK (tmode)))
11690 rtx inner = XEXP (XEXP (XEXP (op0, 0), 0), 0);
11691 rtx add_const = XEXP (XEXP (op0, 0), 1);
11692 rtx new_const = simplify_gen_binary (ASHIFTRT, GET_MODE (op0),
11693 add_const, XEXP (op0, 1));
11695 op0 = simplify_gen_binary (PLUS, tmode,
11696 gen_lowpart (tmode, inner),
11701 /* ... fall through ... */
11703 /* If we have (compare (xshiftrt FOO N) (const_int C)) and
11704 the low order N bits of FOO are known to be zero, we can do this
11705 by comparing FOO with C shifted left N bits so long as no
11706 overflow occurs. */
11707 if (CONST_INT_P (XEXP (op0, 1))
11708 && INTVAL (XEXP (op0, 1)) >= 0
11709 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT
11710 && mode_width <= HOST_BITS_PER_WIDE_INT
11711 && (nonzero_bits (XEXP (op0, 0), mode)
11712 & (((HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1))) - 1)) == 0
11713 && (((unsigned HOST_WIDE_INT) const_op
11714 + (GET_CODE (op0) != LSHIFTRT
11715 ? ((GET_MODE_MASK (mode) >> INTVAL (XEXP (op0, 1)) >> 1)
11718 <= GET_MODE_MASK (mode) >> INTVAL (XEXP (op0, 1))))
11720 /* If the shift was logical, then we must make the condition
11722 if (GET_CODE (op0) == LSHIFTRT)
11723 code = unsigned_condition (code);
11725 const_op <<= INTVAL (XEXP (op0, 1));
11726 op1 = GEN_INT (const_op);
11727 op0 = XEXP (op0, 0);
11731 /* If we are using this shift to extract just the sign bit, we
11732 can replace this with an LT or GE comparison. */
11734 && (equality_comparison_p || sign_bit_comparison_p)
11735 && CONST_INT_P (XEXP (op0, 1))
11736 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (op0, 1))
11739 op0 = XEXP (op0, 0);
11740 code = (code == NE || code == GT ? LT : GE);
11752 /* Now make any compound operations involved in this comparison. Then,
11753 check for an outmost SUBREG on OP0 that is not doing anything or is
11754 paradoxical. The latter transformation must only be performed when
11755 it is known that the "extra" bits will be the same in op0 and op1 or
11756 that they don't matter. There are three cases to consider:
11758 1. SUBREG_REG (op0) is a register. In this case the bits are don't
11759 care bits and we can assume they have any convenient value. So
11760 making the transformation is safe.
11762 2. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is not defined.
11763 In this case the upper bits of op0 are undefined. We should not make
11764 the simplification in that case as we do not know the contents of
11767 3. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is defined and not
11768 UNKNOWN. In that case we know those bits are zeros or ones. We must
11769 also be sure that they are the same as the upper bits of op1.
11771 We can never remove a SUBREG for a non-equality comparison because
11772 the sign bit is in a different place in the underlying object. */
11774 op0 = make_compound_operation (op0, op1 == const0_rtx ? COMPARE : SET);
11775 op1 = make_compound_operation (op1, SET);
11777 if (GET_CODE (op0) == SUBREG && subreg_lowpart_p (op0)
11778 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
11779 && GET_MODE_CLASS (GET_MODE (SUBREG_REG (op0))) == MODE_INT
11780 && (code == NE || code == EQ))
11782 if (GET_MODE_SIZE (GET_MODE (op0))
11783 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (op0))))
11785 /* For paradoxical subregs, allow case 1 as above. Case 3 isn't
11787 if (REG_P (SUBREG_REG (op0)))
11789 op0 = SUBREG_REG (op0);
11790 op1 = gen_lowpart (GET_MODE (op0), op1);
11793 else if ((GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0)))
11794 <= HOST_BITS_PER_WIDE_INT)
11795 && (nonzero_bits (SUBREG_REG (op0),
11796 GET_MODE (SUBREG_REG (op0)))
11797 & ~GET_MODE_MASK (GET_MODE (op0))) == 0)
11799 tem = gen_lowpart (GET_MODE (SUBREG_REG (op0)), op1);
11801 if ((nonzero_bits (tem, GET_MODE (SUBREG_REG (op0)))
11802 & ~GET_MODE_MASK (GET_MODE (op0))) == 0)
11803 op0 = SUBREG_REG (op0), op1 = tem;
11807 /* We now do the opposite procedure: Some machines don't have compare
11808 insns in all modes. If OP0's mode is an integer mode smaller than a
11809 word and we can't do a compare in that mode, see if there is a larger
11810 mode for which we can do the compare. There are a number of cases in
11811 which we can use the wider mode. */
11813 mode = GET_MODE (op0);
11814 if (mode != VOIDmode && GET_MODE_CLASS (mode) == MODE_INT
11815 && GET_MODE_SIZE (mode) < UNITS_PER_WORD
11816 && ! have_insn_for (COMPARE, mode))
11817 for (tmode = GET_MODE_WIDER_MODE (mode);
11819 && GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT);
11820 tmode = GET_MODE_WIDER_MODE (tmode))
11821 if (have_insn_for (COMPARE, tmode))
11825 /* If this is a test for negative, we can make an explicit
11826 test of the sign bit. Test this first so we can use
11827 a paradoxical subreg to extend OP0. */
11829 if (op1 == const0_rtx && (code == LT || code == GE)
11830 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
11832 op0 = simplify_gen_binary (AND, tmode,
11833 gen_lowpart (tmode, op0),
11834 GEN_INT ((HOST_WIDE_INT) 1
11835 << (GET_MODE_BITSIZE (mode)
11837 code = (code == LT) ? NE : EQ;
11841 /* If the only nonzero bits in OP0 and OP1 are those in the
11842 narrower mode and this is an equality or unsigned comparison,
11843 we can use the wider mode. Similarly for sign-extended
11844 values, in which case it is true for all comparisons. */
11845 zero_extended = ((code == EQ || code == NE
11846 || code == GEU || code == GTU
11847 || code == LEU || code == LTU)
11848 && (nonzero_bits (op0, tmode)
11849 & ~GET_MODE_MASK (mode)) == 0
11850 && ((CONST_INT_P (op1)
11851 || (nonzero_bits (op1, tmode)
11852 & ~GET_MODE_MASK (mode)) == 0)));
11855 || ((num_sign_bit_copies (op0, tmode)
11856 > (unsigned int) (GET_MODE_BITSIZE (tmode)
11857 - GET_MODE_BITSIZE (mode)))
11858 && (num_sign_bit_copies (op1, tmode)
11859 > (unsigned int) (GET_MODE_BITSIZE (tmode)
11860 - GET_MODE_BITSIZE (mode)))))
11862 /* If OP0 is an AND and we don't have an AND in MODE either,
11863 make a new AND in the proper mode. */
11864 if (GET_CODE (op0) == AND
11865 && !have_insn_for (AND, mode))
11866 op0 = simplify_gen_binary (AND, tmode,
11867 gen_lowpart (tmode,
11869 gen_lowpart (tmode,
11875 op0 = simplify_gen_unary (ZERO_EXTEND, tmode, op0, mode);
11876 op1 = simplify_gen_unary (ZERO_EXTEND, tmode, op1, mode);
11880 op0 = simplify_gen_unary (SIGN_EXTEND, tmode, op0, mode);
11881 op1 = simplify_gen_unary (SIGN_EXTEND, tmode, op1, mode);
11888 #ifdef CANONICALIZE_COMPARISON
11889 /* If this machine only supports a subset of valid comparisons, see if we
11890 can convert an unsupported one into a supported one. */
11891 CANONICALIZE_COMPARISON (code, op0, op1);
11900 /* Utility function for record_value_for_reg. Count number of
11905 enum rtx_code code = GET_CODE (x);
11909 if (GET_RTX_CLASS (code) == '2'
11910 || GET_RTX_CLASS (code) == 'c')
11912 rtx x0 = XEXP (x, 0);
11913 rtx x1 = XEXP (x, 1);
11916 return 1 + 2 * count_rtxs (x0);
11918 if ((GET_RTX_CLASS (GET_CODE (x1)) == '2'
11919 || GET_RTX_CLASS (GET_CODE (x1)) == 'c')
11920 && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1)))
11921 return 2 + 2 * count_rtxs (x0)
11922 + count_rtxs (x == XEXP (x1, 0)
11923 ? XEXP (x1, 1) : XEXP (x1, 0));
11925 if ((GET_RTX_CLASS (GET_CODE (x0)) == '2'
11926 || GET_RTX_CLASS (GET_CODE (x0)) == 'c')
11927 && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1)))
11928 return 2 + 2 * count_rtxs (x1)
11929 + count_rtxs (x == XEXP (x0, 0)
11930 ? XEXP (x0, 1) : XEXP (x0, 0));
11933 fmt = GET_RTX_FORMAT (code);
11934 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
11936 ret += count_rtxs (XEXP (x, i));
11937 else if (fmt[i] == 'E')
11938 for (j = 0; j < XVECLEN (x, i); j++)
11939 ret += count_rtxs (XVECEXP (x, i, j));
11944 /* Utility function for following routine. Called when X is part of a value
11945 being stored into last_set_value. Sets last_set_table_tick
11946 for each register mentioned. Similar to mention_regs in cse.c */
11949 update_table_tick (rtx x)
11951 enum rtx_code code = GET_CODE (x);
11952 const char *fmt = GET_RTX_FORMAT (code);
11957 unsigned int regno = REGNO (x);
11958 unsigned int endregno = END_REGNO (x);
11961 for (r = regno; r < endregno; r++)
11963 reg_stat_type *rsp = VEC_index (reg_stat_type, reg_stat, r);
11964 rsp->last_set_table_tick = label_tick;
11970 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
11973 /* Check for identical subexpressions. If x contains
11974 identical subexpression we only have to traverse one of
11976 if (i == 0 && ARITHMETIC_P (x))
11978 /* Note that at this point x1 has already been
11980 rtx x0 = XEXP (x, 0);
11981 rtx x1 = XEXP (x, 1);
11983 /* If x0 and x1 are identical then there is no need to
11988 /* If x0 is identical to a subexpression of x1 then while
11989 processing x1, x0 has already been processed. Thus we
11990 are done with x. */
11991 if (ARITHMETIC_P (x1)
11992 && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1)))
11995 /* If x1 is identical to a subexpression of x0 then we
11996 still have to process the rest of x0. */
11997 if (ARITHMETIC_P (x0)
11998 && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1)))
12000 update_table_tick (XEXP (x0, x1 == XEXP (x0, 0) ? 1 : 0));
12005 update_table_tick (XEXP (x, i));
12007 else if (fmt[i] == 'E')
12008 for (j = 0; j < XVECLEN (x, i); j++)
12009 update_table_tick (XVECEXP (x, i, j));
12012 /* Record that REG is set to VALUE in insn INSN. If VALUE is zero, we
12013 are saying that the register is clobbered and we no longer know its
12014 value. If INSN is zero, don't update reg_stat[].last_set; this is
12015 only permitted with VALUE also zero and is used to invalidate the
12019 record_value_for_reg (rtx reg, rtx insn, rtx value)
12021 unsigned int regno = REGNO (reg);
12022 unsigned int endregno = END_REGNO (reg);
12024 reg_stat_type *rsp;
12026 /* If VALUE contains REG and we have a previous value for REG, substitute
12027 the previous value. */
12028 if (value && insn && reg_overlap_mentioned_p (reg, value))
12032 /* Set things up so get_last_value is allowed to see anything set up to
12034 subst_low_luid = DF_INSN_LUID (insn);
12035 tem = get_last_value (reg);
12037 /* If TEM is simply a binary operation with two CLOBBERs as operands,
12038 it isn't going to be useful and will take a lot of time to process,
12039 so just use the CLOBBER. */
12043 if (ARITHMETIC_P (tem)
12044 && GET_CODE (XEXP (tem, 0)) == CLOBBER
12045 && GET_CODE (XEXP (tem, 1)) == CLOBBER)
12046 tem = XEXP (tem, 0);
12047 else if (count_occurrences (value, reg, 1) >= 2)
12049 /* If there are two or more occurrences of REG in VALUE,
12050 prevent the value from growing too much. */
12051 if (count_rtxs (tem) > MAX_LAST_VALUE_RTL)
12052 tem = gen_rtx_CLOBBER (GET_MODE (tem), const0_rtx);
12055 value = replace_rtx (copy_rtx (value), reg, tem);
12059 /* For each register modified, show we don't know its value, that
12060 we don't know about its bitwise content, that its value has been
12061 updated, and that we don't know the location of the death of the
12063 for (i = regno; i < endregno; i++)
12065 rsp = VEC_index (reg_stat_type, reg_stat, i);
12068 rsp->last_set = insn;
12070 rsp->last_set_value = 0;
12071 rsp->last_set_mode = VOIDmode;
12072 rsp->last_set_nonzero_bits = 0;
12073 rsp->last_set_sign_bit_copies = 0;
12074 rsp->last_death = 0;
12075 rsp->truncated_to_mode = VOIDmode;
12078 /* Mark registers that are being referenced in this value. */
12080 update_table_tick (value);
12082 /* Now update the status of each register being set.
12083 If someone is using this register in this block, set this register
12084 to invalid since we will get confused between the two lives in this
12085 basic block. This makes using this register always invalid. In cse, we
12086 scan the table to invalidate all entries using this register, but this
12087 is too much work for us. */
12089 for (i = regno; i < endregno; i++)
12091 rsp = VEC_index (reg_stat_type, reg_stat, i);
12092 rsp->last_set_label = label_tick;
12094 || (value && rsp->last_set_table_tick >= label_tick_ebb_start))
12095 rsp->last_set_invalid = 1;
12097 rsp->last_set_invalid = 0;
12100 /* The value being assigned might refer to X (like in "x++;"). In that
12101 case, we must replace it with (clobber (const_int 0)) to prevent
12103 rsp = VEC_index (reg_stat_type, reg_stat, regno);
12104 if (value && !get_last_value_validate (&value, insn, label_tick, 0))
12106 value = copy_rtx (value);
12107 if (!get_last_value_validate (&value, insn, label_tick, 1))
12111 /* For the main register being modified, update the value, the mode, the
12112 nonzero bits, and the number of sign bit copies. */
12114 rsp->last_set_value = value;
12118 enum machine_mode mode = GET_MODE (reg);
12119 subst_low_luid = DF_INSN_LUID (insn);
12120 rsp->last_set_mode = mode;
12121 if (GET_MODE_CLASS (mode) == MODE_INT
12122 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
12123 mode = nonzero_bits_mode;
12124 rsp->last_set_nonzero_bits = nonzero_bits (value, mode);
12125 rsp->last_set_sign_bit_copies
12126 = num_sign_bit_copies (value, GET_MODE (reg));
12130 /* Called via note_stores from record_dead_and_set_regs to handle one
12131 SET or CLOBBER in an insn. DATA is the instruction in which the
12132 set is occurring. */
12135 record_dead_and_set_regs_1 (rtx dest, const_rtx setter, void *data)
12137 rtx record_dead_insn = (rtx) data;
12139 if (GET_CODE (dest) == SUBREG)
12140 dest = SUBREG_REG (dest);
12142 if (!record_dead_insn)
12145 record_value_for_reg (dest, NULL_RTX, NULL_RTX);
12151 /* If we are setting the whole register, we know its value. Otherwise
12152 show that we don't know the value. We can handle SUBREG in
12154 if (GET_CODE (setter) == SET && dest == SET_DEST (setter))
12155 record_value_for_reg (dest, record_dead_insn, SET_SRC (setter));
12156 else if (GET_CODE (setter) == SET
12157 && GET_CODE (SET_DEST (setter)) == SUBREG
12158 && SUBREG_REG (SET_DEST (setter)) == dest
12159 && GET_MODE_BITSIZE (GET_MODE (dest)) <= BITS_PER_WORD
12160 && subreg_lowpart_p (SET_DEST (setter)))
12161 record_value_for_reg (dest, record_dead_insn,
12162 gen_lowpart (GET_MODE (dest),
12163 SET_SRC (setter)));
12165 record_value_for_reg (dest, record_dead_insn, NULL_RTX);
12167 else if (MEM_P (dest)
12168 /* Ignore pushes, they clobber nothing. */
12169 && ! push_operand (dest, GET_MODE (dest)))
12170 mem_last_set = DF_INSN_LUID (record_dead_insn);
12173 /* Update the records of when each REG was most recently set or killed
12174 for the things done by INSN. This is the last thing done in processing
12175 INSN in the combiner loop.
12177 We update reg_stat[], in particular fields last_set, last_set_value,
12178 last_set_mode, last_set_nonzero_bits, last_set_sign_bit_copies,
12179 last_death, and also the similar information mem_last_set (which insn
12180 most recently modified memory) and last_call_luid (which insn was the
12181 most recent subroutine call). */
12184 record_dead_and_set_regs (rtx insn)
12189 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
12191 if (REG_NOTE_KIND (link) == REG_DEAD
12192 && REG_P (XEXP (link, 0)))
12194 unsigned int regno = REGNO (XEXP (link, 0));
12195 unsigned int endregno = END_REGNO (XEXP (link, 0));
12197 for (i = regno; i < endregno; i++)
12199 reg_stat_type *rsp;
12201 rsp = VEC_index (reg_stat_type, reg_stat, i);
12202 rsp->last_death = insn;
12205 else if (REG_NOTE_KIND (link) == REG_INC)
12206 record_value_for_reg (XEXP (link, 0), insn, NULL_RTX);
12211 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
12212 if (TEST_HARD_REG_BIT (regs_invalidated_by_call, i))
12214 reg_stat_type *rsp;
12216 rsp = VEC_index (reg_stat_type, reg_stat, i);
12217 rsp->last_set_invalid = 1;
12218 rsp->last_set = insn;
12219 rsp->last_set_value = 0;
12220 rsp->last_set_mode = VOIDmode;
12221 rsp->last_set_nonzero_bits = 0;
12222 rsp->last_set_sign_bit_copies = 0;
12223 rsp->last_death = 0;
12224 rsp->truncated_to_mode = VOIDmode;
12227 last_call_luid = mem_last_set = DF_INSN_LUID (insn);
12229 /* We can't combine into a call pattern. Remember, though, that
12230 the return value register is set at this LUID. We could
12231 still replace a register with the return value from the
12232 wrong subroutine call! */
12233 note_stores (PATTERN (insn), record_dead_and_set_regs_1, NULL_RTX);
12236 note_stores (PATTERN (insn), record_dead_and_set_regs_1, insn);
12239 /* If a SUBREG has the promoted bit set, it is in fact a property of the
12240 register present in the SUBREG, so for each such SUBREG go back and
12241 adjust nonzero and sign bit information of the registers that are
12242 known to have some zero/sign bits set.
12244 This is needed because when combine blows the SUBREGs away, the
12245 information on zero/sign bits is lost and further combines can be
12246 missed because of that. */
12249 record_promoted_value (rtx insn, rtx subreg)
12252 unsigned int regno = REGNO (SUBREG_REG (subreg));
12253 enum machine_mode mode = GET_MODE (subreg);
12255 if (GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT)
12258 for (links = LOG_LINKS (insn); links;)
12260 reg_stat_type *rsp;
12262 insn = XEXP (links, 0);
12263 set = single_set (insn);
12265 if (! set || !REG_P (SET_DEST (set))
12266 || REGNO (SET_DEST (set)) != regno
12267 || GET_MODE (SET_DEST (set)) != GET_MODE (SUBREG_REG (subreg)))
12269 links = XEXP (links, 1);
12273 rsp = VEC_index (reg_stat_type, reg_stat, regno);
12274 if (rsp->last_set == insn)
12276 if (SUBREG_PROMOTED_UNSIGNED_P (subreg) > 0)
12277 rsp->last_set_nonzero_bits &= GET_MODE_MASK (mode);
12280 if (REG_P (SET_SRC (set)))
12282 regno = REGNO (SET_SRC (set));
12283 links = LOG_LINKS (insn);
12290 /* Check if X, a register, is known to contain a value already
12291 truncated to MODE. In this case we can use a subreg to refer to
12292 the truncated value even though in the generic case we would need
12293 an explicit truncation. */
12296 reg_truncated_to_mode (enum machine_mode mode, const_rtx x)
12298 reg_stat_type *rsp = VEC_index (reg_stat_type, reg_stat, REGNO (x));
12299 enum machine_mode truncated = rsp->truncated_to_mode;
12302 || rsp->truncation_label < label_tick_ebb_start)
12304 if (GET_MODE_SIZE (truncated) <= GET_MODE_SIZE (mode))
12306 if (TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode),
12307 GET_MODE_BITSIZE (truncated)))
12312 /* Callback for for_each_rtx. If *P is a hard reg or a subreg record the mode
12313 that the register is accessed in. For non-TRULY_NOOP_TRUNCATION targets we
12314 might be able to turn a truncate into a subreg using this information.
12315 Return -1 if traversing *P is complete or 0 otherwise. */
12318 record_truncated_value (rtx *p, void *data ATTRIBUTE_UNUSED)
12321 enum machine_mode truncated_mode;
12322 reg_stat_type *rsp;
12324 if (GET_CODE (x) == SUBREG && REG_P (SUBREG_REG (x)))
12326 enum machine_mode original_mode = GET_MODE (SUBREG_REG (x));
12327 truncated_mode = GET_MODE (x);
12329 if (GET_MODE_SIZE (original_mode) <= GET_MODE_SIZE (truncated_mode))
12332 if (TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (truncated_mode),
12333 GET_MODE_BITSIZE (original_mode)))
12336 x = SUBREG_REG (x);
12338 /* ??? For hard-regs we now record everything. We might be able to
12339 optimize this using last_set_mode. */
12340 else if (REG_P (x) && REGNO (x) < FIRST_PSEUDO_REGISTER)
12341 truncated_mode = GET_MODE (x);
12345 rsp = VEC_index (reg_stat_type, reg_stat, REGNO (x));
12346 if (rsp->truncated_to_mode == 0
12347 || rsp->truncation_label < label_tick_ebb_start
12348 || (GET_MODE_SIZE (truncated_mode)
12349 < GET_MODE_SIZE (rsp->truncated_to_mode)))
12351 rsp->truncated_to_mode = truncated_mode;
12352 rsp->truncation_label = label_tick;
12358 /* Callback for note_uses. Find hardregs and subregs of pseudos and
12359 the modes they are used in. This can help truning TRUNCATEs into
12363 record_truncated_values (rtx *x, void *data ATTRIBUTE_UNUSED)
12365 for_each_rtx (x, record_truncated_value, NULL);
12368 /* Scan X for promoted SUBREGs. For each one found,
12369 note what it implies to the registers used in it. */
12372 check_promoted_subreg (rtx insn, rtx x)
12374 if (GET_CODE (x) == SUBREG
12375 && SUBREG_PROMOTED_VAR_P (x)
12376 && REG_P (SUBREG_REG (x)))
12377 record_promoted_value (insn, x);
12380 const char *format = GET_RTX_FORMAT (GET_CODE (x));
12383 for (i = 0; i < GET_RTX_LENGTH (GET_CODE (x)); i++)
12387 check_promoted_subreg (insn, XEXP (x, i));
12391 if (XVEC (x, i) != 0)
12392 for (j = 0; j < XVECLEN (x, i); j++)
12393 check_promoted_subreg (insn, XVECEXP (x, i, j));
12399 /* Verify that all the registers and memory references mentioned in *LOC are
12400 still valid. *LOC was part of a value set in INSN when label_tick was
12401 equal to TICK. Return 0 if some are not. If REPLACE is nonzero, replace
12402 the invalid references with (clobber (const_int 0)) and return 1. This
12403 replacement is useful because we often can get useful information about
12404 the form of a value (e.g., if it was produced by a shift that always
12405 produces -1 or 0) even though we don't know exactly what registers it
12406 was produced from. */
12409 get_last_value_validate (rtx *loc, rtx insn, int tick, int replace)
12412 const char *fmt = GET_RTX_FORMAT (GET_CODE (x));
12413 int len = GET_RTX_LENGTH (GET_CODE (x));
12418 unsigned int regno = REGNO (x);
12419 unsigned int endregno = END_REGNO (x);
12422 for (j = regno; j < endregno; j++)
12424 reg_stat_type *rsp = VEC_index (reg_stat_type, reg_stat, j);
12425 if (rsp->last_set_invalid
12426 /* If this is a pseudo-register that was only set once and not
12427 live at the beginning of the function, it is always valid. */
12428 || (! (regno >= FIRST_PSEUDO_REGISTER
12429 && REG_N_SETS (regno) == 1
12430 && (!REGNO_REG_SET_P
12431 (DF_LR_IN (ENTRY_BLOCK_PTR->next_bb), regno)))
12432 && rsp->last_set_label > tick))
12435 *loc = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
12442 /* If this is a memory reference, make sure that there were no stores after
12443 it that might have clobbered the value. We don't have alias info, so we
12444 assume any store invalidates it. Moreover, we only have local UIDs, so
12445 we also assume that there were stores in the intervening basic blocks. */
12446 else if (MEM_P (x) && !MEM_READONLY_P (x)
12447 && (tick != label_tick || DF_INSN_LUID (insn) <= mem_last_set))
12450 *loc = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
12454 for (i = 0; i < len; i++)
12458 /* Check for identical subexpressions. If x contains
12459 identical subexpression we only have to traverse one of
12461 if (i == 1 && ARITHMETIC_P (x))
12463 /* Note that at this point x0 has already been checked
12464 and found valid. */
12465 rtx x0 = XEXP (x, 0);
12466 rtx x1 = XEXP (x, 1);
12468 /* If x0 and x1 are identical then x is also valid. */
12472 /* If x1 is identical to a subexpression of x0 then
12473 while checking x0, x1 has already been checked. Thus
12474 it is valid and so as x. */
12475 if (ARITHMETIC_P (x0)
12476 && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1)))
12479 /* If x0 is identical to a subexpression of x1 then x is
12480 valid iff the rest of x1 is valid. */
12481 if (ARITHMETIC_P (x1)
12482 && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1)))
12484 get_last_value_validate (&XEXP (x1,
12485 x0 == XEXP (x1, 0) ? 1 : 0),
12486 insn, tick, replace);
12489 if (get_last_value_validate (&XEXP (x, i), insn, tick,
12493 else if (fmt[i] == 'E')
12494 for (j = 0; j < XVECLEN (x, i); j++)
12495 if (get_last_value_validate (&XVECEXP (x, i, j),
12496 insn, tick, replace) == 0)
12500 /* If we haven't found a reason for it to be invalid, it is valid. */
12504 /* Get the last value assigned to X, if known. Some registers
12505 in the value may be replaced with (clobber (const_int 0)) if their value
12506 is known longer known reliably. */
12509 get_last_value (const_rtx x)
12511 unsigned int regno;
12513 reg_stat_type *rsp;
12515 /* If this is a non-paradoxical SUBREG, get the value of its operand and
12516 then convert it to the desired mode. If this is a paradoxical SUBREG,
12517 we cannot predict what values the "extra" bits might have. */
12518 if (GET_CODE (x) == SUBREG
12519 && subreg_lowpart_p (x)
12520 && (GET_MODE_SIZE (GET_MODE (x))
12521 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
12522 && (value = get_last_value (SUBREG_REG (x))) != 0)
12523 return gen_lowpart (GET_MODE (x), value);
12529 rsp = VEC_index (reg_stat_type, reg_stat, regno);
12530 value = rsp->last_set_value;
12532 /* If we don't have a value, or if it isn't for this basic block and
12533 it's either a hard register, set more than once, or it's a live
12534 at the beginning of the function, return 0.
12536 Because if it's not live at the beginning of the function then the reg
12537 is always set before being used (is never used without being set).
12538 And, if it's set only once, and it's always set before use, then all
12539 uses must have the same last value, even if it's not from this basic
12543 || (rsp->last_set_label < label_tick_ebb_start
12544 && (regno < FIRST_PSEUDO_REGISTER
12545 || REG_N_SETS (regno) != 1
12547 (DF_LR_IN (ENTRY_BLOCK_PTR->next_bb), regno))))
12550 /* If the value was set in a later insn than the ones we are processing,
12551 we can't use it even if the register was only set once. */
12552 if (rsp->last_set_label == label_tick
12553 && DF_INSN_LUID (rsp->last_set) >= subst_low_luid)
12556 /* If the value has all its registers valid, return it. */
12557 if (get_last_value_validate (&value, rsp->last_set, rsp->last_set_label, 0))
12560 /* Otherwise, make a copy and replace any invalid register with
12561 (clobber (const_int 0)). If that fails for some reason, return 0. */
12563 value = copy_rtx (value);
12564 if (get_last_value_validate (&value, rsp->last_set, rsp->last_set_label, 1))
12570 /* Return nonzero if expression X refers to a REG or to memory
12571 that is set in an instruction more recent than FROM_LUID. */
12574 use_crosses_set_p (const_rtx x, int from_luid)
12578 enum rtx_code code = GET_CODE (x);
12582 unsigned int regno = REGNO (x);
12583 unsigned endreg = END_REGNO (x);
12585 #ifdef PUSH_ROUNDING
12586 /* Don't allow uses of the stack pointer to be moved,
12587 because we don't know whether the move crosses a push insn. */
12588 if (regno == STACK_POINTER_REGNUM && PUSH_ARGS)
12591 for (; regno < endreg; regno++)
12593 reg_stat_type *rsp = VEC_index (reg_stat_type, reg_stat, regno);
12595 && rsp->last_set_label == label_tick
12596 && DF_INSN_LUID (rsp->last_set) > from_luid)
12602 if (code == MEM && mem_last_set > from_luid)
12605 fmt = GET_RTX_FORMAT (code);
12607 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
12612 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
12613 if (use_crosses_set_p (XVECEXP (x, i, j), from_luid))
12616 else if (fmt[i] == 'e'
12617 && use_crosses_set_p (XEXP (x, i), from_luid))
12623 /* Define three variables used for communication between the following
12626 static unsigned int reg_dead_regno, reg_dead_endregno;
12627 static int reg_dead_flag;
12629 /* Function called via note_stores from reg_dead_at_p.
12631 If DEST is within [reg_dead_regno, reg_dead_endregno), set
12632 reg_dead_flag to 1 if X is a CLOBBER and to -1 it is a SET. */
12635 reg_dead_at_p_1 (rtx dest, const_rtx x, void *data ATTRIBUTE_UNUSED)
12637 unsigned int regno, endregno;
12642 regno = REGNO (dest);
12643 endregno = END_REGNO (dest);
12644 if (reg_dead_endregno > regno && reg_dead_regno < endregno)
12645 reg_dead_flag = (GET_CODE (x) == CLOBBER) ? 1 : -1;
12648 /* Return nonzero if REG is known to be dead at INSN.
12650 We scan backwards from INSN. If we hit a REG_DEAD note or a CLOBBER
12651 referencing REG, it is dead. If we hit a SET referencing REG, it is
12652 live. Otherwise, see if it is live or dead at the start of the basic
12653 block we are in. Hard regs marked as being live in NEWPAT_USED_REGS
12654 must be assumed to be always live. */
12657 reg_dead_at_p (rtx reg, rtx insn)
12662 /* Set variables for reg_dead_at_p_1. */
12663 reg_dead_regno = REGNO (reg);
12664 reg_dead_endregno = END_REGNO (reg);
12668 /* Check that reg isn't mentioned in NEWPAT_USED_REGS. For fixed registers
12669 we allow the machine description to decide whether use-and-clobber
12670 patterns are OK. */
12671 if (reg_dead_regno < FIRST_PSEUDO_REGISTER)
12673 for (i = reg_dead_regno; i < reg_dead_endregno; i++)
12674 if (!fixed_regs[i] && TEST_HARD_REG_BIT (newpat_used_regs, i))
12678 /* Scan backwards until we find a REG_DEAD note, SET, CLOBBER, or
12679 beginning of basic block. */
12680 block = BLOCK_FOR_INSN (insn);
12685 note_stores (PATTERN (insn), reg_dead_at_p_1, NULL);
12687 return reg_dead_flag == 1 ? 1 : 0;
12689 if (find_regno_note (insn, REG_DEAD, reg_dead_regno))
12693 if (insn == BB_HEAD (block))
12696 insn = PREV_INSN (insn);
12699 /* Look at live-in sets for the basic block that we were in. */
12700 for (i = reg_dead_regno; i < reg_dead_endregno; i++)
12701 if (REGNO_REG_SET_P (df_get_live_in (block), i))
12707 /* Note hard registers in X that are used. */
12710 mark_used_regs_combine (rtx x)
12712 RTX_CODE code = GET_CODE (x);
12713 unsigned int regno;
12726 case ADDR_DIFF_VEC:
12729 /* CC0 must die in the insn after it is set, so we don't need to take
12730 special note of it here. */
12736 /* If we are clobbering a MEM, mark any hard registers inside the
12737 address as used. */
12738 if (MEM_P (XEXP (x, 0)))
12739 mark_used_regs_combine (XEXP (XEXP (x, 0), 0));
12744 /* A hard reg in a wide mode may really be multiple registers.
12745 If so, mark all of them just like the first. */
12746 if (regno < FIRST_PSEUDO_REGISTER)
12748 /* None of this applies to the stack, frame or arg pointers. */
12749 if (regno == STACK_POINTER_REGNUM
12750 #if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM
12751 || regno == HARD_FRAME_POINTER_REGNUM
12753 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
12754 || (regno == ARG_POINTER_REGNUM && fixed_regs[regno])
12756 || regno == FRAME_POINTER_REGNUM)
12759 add_to_hard_reg_set (&newpat_used_regs, GET_MODE (x), regno);
12765 /* If setting a MEM, or a SUBREG of a MEM, then note any hard regs in
12767 rtx testreg = SET_DEST (x);
12769 while (GET_CODE (testreg) == SUBREG
12770 || GET_CODE (testreg) == ZERO_EXTRACT
12771 || GET_CODE (testreg) == STRICT_LOW_PART)
12772 testreg = XEXP (testreg, 0);
12774 if (MEM_P (testreg))
12775 mark_used_regs_combine (XEXP (testreg, 0));
12777 mark_used_regs_combine (SET_SRC (x));
12785 /* Recursively scan the operands of this expression. */
12788 const char *fmt = GET_RTX_FORMAT (code);
12790 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
12793 mark_used_regs_combine (XEXP (x, i));
12794 else if (fmt[i] == 'E')
12798 for (j = 0; j < XVECLEN (x, i); j++)
12799 mark_used_regs_combine (XVECEXP (x, i, j));
12805 /* Remove register number REGNO from the dead registers list of INSN.
12807 Return the note used to record the death, if there was one. */
12810 remove_death (unsigned int regno, rtx insn)
12812 rtx note = find_regno_note (insn, REG_DEAD, regno);
12815 remove_note (insn, note);
12820 /* For each register (hardware or pseudo) used within expression X, if its
12821 death is in an instruction with luid between FROM_LUID (inclusive) and
12822 TO_INSN (exclusive), put a REG_DEAD note for that register in the
12823 list headed by PNOTES.
12825 That said, don't move registers killed by maybe_kill_insn.
12827 This is done when X is being merged by combination into TO_INSN. These
12828 notes will then be distributed as needed. */
12831 move_deaths (rtx x, rtx maybe_kill_insn, int from_luid, rtx to_insn,
12836 enum rtx_code code = GET_CODE (x);
12840 unsigned int regno = REGNO (x);
12841 rtx where_dead = VEC_index (reg_stat_type, reg_stat, regno)->last_death;
12843 /* Don't move the register if it gets killed in between from and to. */
12844 if (maybe_kill_insn && reg_set_p (x, maybe_kill_insn)
12845 && ! reg_referenced_p (x, maybe_kill_insn))
12849 && BLOCK_FOR_INSN (where_dead) == BLOCK_FOR_INSN (to_insn)
12850 && DF_INSN_LUID (where_dead) >= from_luid
12851 && DF_INSN_LUID (where_dead) < DF_INSN_LUID (to_insn))
12853 rtx note = remove_death (regno, where_dead);
12855 /* It is possible for the call above to return 0. This can occur
12856 when last_death points to I2 or I1 that we combined with.
12857 In that case make a new note.
12859 We must also check for the case where X is a hard register
12860 and NOTE is a death note for a range of hard registers
12861 including X. In that case, we must put REG_DEAD notes for
12862 the remaining registers in place of NOTE. */
12864 if (note != 0 && regno < FIRST_PSEUDO_REGISTER
12865 && (GET_MODE_SIZE (GET_MODE (XEXP (note, 0)))
12866 > GET_MODE_SIZE (GET_MODE (x))))
12868 unsigned int deadregno = REGNO (XEXP (note, 0));
12869 unsigned int deadend = END_HARD_REGNO (XEXP (note, 0));
12870 unsigned int ourend = END_HARD_REGNO (x);
12873 for (i = deadregno; i < deadend; i++)
12874 if (i < regno || i >= ourend)
12875 add_reg_note (where_dead, REG_DEAD, regno_reg_rtx[i]);
12878 /* If we didn't find any note, or if we found a REG_DEAD note that
12879 covers only part of the given reg, and we have a multi-reg hard
12880 register, then to be safe we must check for REG_DEAD notes
12881 for each register other than the first. They could have
12882 their own REG_DEAD notes lying around. */
12883 else if ((note == 0
12885 && (GET_MODE_SIZE (GET_MODE (XEXP (note, 0)))
12886 < GET_MODE_SIZE (GET_MODE (x)))))
12887 && regno < FIRST_PSEUDO_REGISTER
12888 && hard_regno_nregs[regno][GET_MODE (x)] > 1)
12890 unsigned int ourend = END_HARD_REGNO (x);
12891 unsigned int i, offset;
12895 offset = hard_regno_nregs[regno][GET_MODE (XEXP (note, 0))];
12899 for (i = regno + offset; i < ourend; i++)
12900 move_deaths (regno_reg_rtx[i],
12901 maybe_kill_insn, from_luid, to_insn, &oldnotes);
12904 if (note != 0 && GET_MODE (XEXP (note, 0)) == GET_MODE (x))
12906 XEXP (note, 1) = *pnotes;
12910 *pnotes = alloc_reg_note (REG_DEAD, x, *pnotes);
12916 else if (GET_CODE (x) == SET)
12918 rtx dest = SET_DEST (x);
12920 move_deaths (SET_SRC (x), maybe_kill_insn, from_luid, to_insn, pnotes);
12922 /* In the case of a ZERO_EXTRACT, a STRICT_LOW_PART, or a SUBREG
12923 that accesses one word of a multi-word item, some
12924 piece of everything register in the expression is used by
12925 this insn, so remove any old death. */
12926 /* ??? So why do we test for equality of the sizes? */
12928 if (GET_CODE (dest) == ZERO_EXTRACT
12929 || GET_CODE (dest) == STRICT_LOW_PART
12930 || (GET_CODE (dest) == SUBREG
12931 && (((GET_MODE_SIZE (GET_MODE (dest))
12932 + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
12933 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (dest)))
12934 + UNITS_PER_WORD - 1) / UNITS_PER_WORD))))
12936 move_deaths (dest, maybe_kill_insn, from_luid, to_insn, pnotes);
12940 /* If this is some other SUBREG, we know it replaces the entire
12941 value, so use that as the destination. */
12942 if (GET_CODE (dest) == SUBREG)
12943 dest = SUBREG_REG (dest);
12945 /* If this is a MEM, adjust deaths of anything used in the address.
12946 For a REG (the only other possibility), the entire value is
12947 being replaced so the old value is not used in this insn. */
12950 move_deaths (XEXP (dest, 0), maybe_kill_insn, from_luid,
12955 else if (GET_CODE (x) == CLOBBER)
12958 len = GET_RTX_LENGTH (code);
12959 fmt = GET_RTX_FORMAT (code);
12961 for (i = 0; i < len; i++)
12966 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
12967 move_deaths (XVECEXP (x, i, j), maybe_kill_insn, from_luid,
12970 else if (fmt[i] == 'e')
12971 move_deaths (XEXP (x, i), maybe_kill_insn, from_luid, to_insn, pnotes);
12975 /* Return 1 if X is the target of a bit-field assignment in BODY, the
12976 pattern of an insn. X must be a REG. */
12979 reg_bitfield_target_p (rtx x, rtx body)
12983 if (GET_CODE (body) == SET)
12985 rtx dest = SET_DEST (body);
12987 unsigned int regno, tregno, endregno, endtregno;
12989 if (GET_CODE (dest) == ZERO_EXTRACT)
12990 target = XEXP (dest, 0);
12991 else if (GET_CODE (dest) == STRICT_LOW_PART)
12992 target = SUBREG_REG (XEXP (dest, 0));
12996 if (GET_CODE (target) == SUBREG)
12997 target = SUBREG_REG (target);
12999 if (!REG_P (target))
13002 tregno = REGNO (target), regno = REGNO (x);
13003 if (tregno >= FIRST_PSEUDO_REGISTER || regno >= FIRST_PSEUDO_REGISTER)
13004 return target == x;
13006 endtregno = end_hard_regno (GET_MODE (target), tregno);
13007 endregno = end_hard_regno (GET_MODE (x), regno);
13009 return endregno > tregno && regno < endtregno;
13012 else if (GET_CODE (body) == PARALLEL)
13013 for (i = XVECLEN (body, 0) - 1; i >= 0; i--)
13014 if (reg_bitfield_target_p (x, XVECEXP (body, 0, i)))
13020 /* Given a chain of REG_NOTES originally from FROM_INSN, try to place them
13021 as appropriate. I3 and I2 are the insns resulting from the combination
13022 insns including FROM (I2 may be zero).
13024 ELIM_I2 and ELIM_I1 are either zero or registers that we know will
13025 not need REG_DEAD notes because they are being substituted for. This
13026 saves searching in the most common cases.
13028 Each note in the list is either ignored or placed on some insns, depending
13029 on the type of note. */
13032 distribute_notes (rtx notes, rtx from_insn, rtx i3, rtx i2, rtx elim_i2,
13033 rtx elim_i1, rtx elim_i0)
13035 rtx note, next_note;
13038 for (note = notes; note; note = next_note)
13040 rtx place = 0, place2 = 0;
13042 next_note = XEXP (note, 1);
13043 switch (REG_NOTE_KIND (note))
13047 /* Doesn't matter much where we put this, as long as it's somewhere.
13048 It is preferable to keep these notes on branches, which is most
13049 likely to be i3. */
13053 case REG_VALUE_PROFILE:
13054 /* Just get rid of this note, as it is unused later anyway. */
13057 case REG_NON_LOCAL_GOTO:
13062 gcc_assert (i2 && JUMP_P (i2));
13067 case REG_EH_REGION:
13068 /* These notes must remain with the call or trapping instruction. */
13071 else if (i2 && CALL_P (i2))
13075 gcc_assert (cfun->can_throw_non_call_exceptions);
13076 if (may_trap_p (i3))
13078 else if (i2 && may_trap_p (i2))
13080 /* ??? Otherwise assume we've combined things such that we
13081 can now prove that the instructions can't trap. Drop the
13082 note in this case. */
13088 /* These notes must remain with the call. It should not be
13089 possible for both I2 and I3 to be a call. */
13094 gcc_assert (i2 && CALL_P (i2));
13100 /* Any clobbers for i3 may still exist, and so we must process
13101 REG_UNUSED notes from that insn.
13103 Any clobbers from i2 or i1 can only exist if they were added by
13104 recog_for_combine. In that case, recog_for_combine created the
13105 necessary REG_UNUSED notes. Trying to keep any original
13106 REG_UNUSED notes from these insns can cause incorrect output
13107 if it is for the same register as the original i3 dest.
13108 In that case, we will notice that the register is set in i3,
13109 and then add a REG_UNUSED note for the destination of i3, which
13110 is wrong. However, it is possible to have REG_UNUSED notes from
13111 i2 or i1 for register which were both used and clobbered, so
13112 we keep notes from i2 or i1 if they will turn into REG_DEAD
13115 /* If this register is set or clobbered in I3, put the note there
13116 unless there is one already. */
13117 if (reg_set_p (XEXP (note, 0), PATTERN (i3)))
13119 if (from_insn != i3)
13122 if (! (REG_P (XEXP (note, 0))
13123 ? find_regno_note (i3, REG_UNUSED, REGNO (XEXP (note, 0)))
13124 : find_reg_note (i3, REG_UNUSED, XEXP (note, 0))))
13127 /* Otherwise, if this register is used by I3, then this register
13128 now dies here, so we must put a REG_DEAD note here unless there
13130 else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3))
13131 && ! (REG_P (XEXP (note, 0))
13132 ? find_regno_note (i3, REG_DEAD,
13133 REGNO (XEXP (note, 0)))
13134 : find_reg_note (i3, REG_DEAD, XEXP (note, 0))))
13136 PUT_REG_NOTE_KIND (note, REG_DEAD);
13144 /* These notes say something about results of an insn. We can
13145 only support them if they used to be on I3 in which case they
13146 remain on I3. Otherwise they are ignored.
13148 If the note refers to an expression that is not a constant, we
13149 must also ignore the note since we cannot tell whether the
13150 equivalence is still true. It might be possible to do
13151 slightly better than this (we only have a problem if I2DEST
13152 or I1DEST is present in the expression), but it doesn't
13153 seem worth the trouble. */
13155 if (from_insn == i3
13156 && (XEXP (note, 0) == 0 || CONSTANT_P (XEXP (note, 0))))
13161 /* These notes say something about how a register is used. They must
13162 be present on any use of the register in I2 or I3. */
13163 if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3)))
13166 if (i2 && reg_mentioned_p (XEXP (note, 0), PATTERN (i2)))
13175 case REG_LABEL_TARGET:
13176 case REG_LABEL_OPERAND:
13177 /* This can show up in several ways -- either directly in the
13178 pattern, or hidden off in the constant pool with (or without?)
13179 a REG_EQUAL note. */
13180 /* ??? Ignore the without-reg_equal-note problem for now. */
13181 if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3))
13182 || ((tem = find_reg_note (i3, REG_EQUAL, NULL_RTX))
13183 && GET_CODE (XEXP (tem, 0)) == LABEL_REF
13184 && XEXP (XEXP (tem, 0), 0) == XEXP (note, 0)))
13188 && (reg_mentioned_p (XEXP (note, 0), PATTERN (i2))
13189 || ((tem = find_reg_note (i2, REG_EQUAL, NULL_RTX))
13190 && GET_CODE (XEXP (tem, 0)) == LABEL_REF
13191 && XEXP (XEXP (tem, 0), 0) == XEXP (note, 0))))
13199 /* For REG_LABEL_TARGET on a JUMP_P, we prefer to put the note
13200 as a JUMP_LABEL or decrement LABEL_NUSES if it's already
13202 if (place && JUMP_P (place)
13203 && REG_NOTE_KIND (note) == REG_LABEL_TARGET
13204 && (JUMP_LABEL (place) == NULL
13205 || JUMP_LABEL (place) == XEXP (note, 0)))
13207 rtx label = JUMP_LABEL (place);
13210 JUMP_LABEL (place) = XEXP (note, 0);
13211 else if (LABEL_P (label))
13212 LABEL_NUSES (label)--;
13215 if (place2 && JUMP_P (place2)
13216 && REG_NOTE_KIND (note) == REG_LABEL_TARGET
13217 && (JUMP_LABEL (place2) == NULL
13218 || JUMP_LABEL (place2) == XEXP (note, 0)))
13220 rtx label = JUMP_LABEL (place2);
13223 JUMP_LABEL (place2) = XEXP (note, 0);
13224 else if (LABEL_P (label))
13225 LABEL_NUSES (label)--;
13231 /* This note says something about the value of a register prior
13232 to the execution of an insn. It is too much trouble to see
13233 if the note is still correct in all situations. It is better
13234 to simply delete it. */
13238 /* If we replaced the right hand side of FROM_INSN with a
13239 REG_EQUAL note, the original use of the dying register
13240 will not have been combined into I3 and I2. In such cases,
13241 FROM_INSN is guaranteed to be the first of the combined
13242 instructions, so we simply need to search back before
13243 FROM_INSN for the previous use or set of this register,
13244 then alter the notes there appropriately.
13246 If the register is used as an input in I3, it dies there.
13247 Similarly for I2, if it is nonzero and adjacent to I3.
13249 If the register is not used as an input in either I3 or I2
13250 and it is not one of the registers we were supposed to eliminate,
13251 there are two possibilities. We might have a non-adjacent I2
13252 or we might have somehow eliminated an additional register
13253 from a computation. For example, we might have had A & B where
13254 we discover that B will always be zero. In this case we will
13255 eliminate the reference to A.
13257 In both cases, we must search to see if we can find a previous
13258 use of A and put the death note there. */
13261 && from_insn == i2mod
13262 && !reg_overlap_mentioned_p (XEXP (note, 0), i2mod_new_rhs))
13267 && CALL_P (from_insn)
13268 && find_reg_fusage (from_insn, USE, XEXP (note, 0)))
13270 else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3)))
13272 else if (i2 != 0 && next_nonnote_nondebug_insn (i2) == i3
13273 && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
13275 else if ((rtx_equal_p (XEXP (note, 0), elim_i2)
13277 && reg_overlap_mentioned_p (XEXP (note, 0),
13279 || rtx_equal_p (XEXP (note, 0), elim_i1)
13280 || rtx_equal_p (XEXP (note, 0), elim_i0))
13287 basic_block bb = this_basic_block;
13289 for (tem = PREV_INSN (tem); place == 0; tem = PREV_INSN (tem))
13291 if (!NONDEBUG_INSN_P (tem))
13293 if (tem == BB_HEAD (bb))
13298 /* If the register is being set at TEM, see if that is all
13299 TEM is doing. If so, delete TEM. Otherwise, make this
13300 into a REG_UNUSED note instead. Don't delete sets to
13301 global register vars. */
13302 if ((REGNO (XEXP (note, 0)) >= FIRST_PSEUDO_REGISTER
13303 || !global_regs[REGNO (XEXP (note, 0))])
13304 && reg_set_p (XEXP (note, 0), PATTERN (tem)))
13306 rtx set = single_set (tem);
13307 rtx inner_dest = 0;
13309 rtx cc0_setter = NULL_RTX;
13313 for (inner_dest = SET_DEST (set);
13314 (GET_CODE (inner_dest) == STRICT_LOW_PART
13315 || GET_CODE (inner_dest) == SUBREG
13316 || GET_CODE (inner_dest) == ZERO_EXTRACT);
13317 inner_dest = XEXP (inner_dest, 0))
13320 /* Verify that it was the set, and not a clobber that
13321 modified the register.
13323 CC0 targets must be careful to maintain setter/user
13324 pairs. If we cannot delete the setter due to side
13325 effects, mark the user with an UNUSED note instead
13328 if (set != 0 && ! side_effects_p (SET_SRC (set))
13329 && rtx_equal_p (XEXP (note, 0), inner_dest)
13331 && (! reg_mentioned_p (cc0_rtx, SET_SRC (set))
13332 || ((cc0_setter = prev_cc0_setter (tem)) != NULL
13333 && sets_cc0_p (PATTERN (cc0_setter)) > 0))
13337 /* Move the notes and links of TEM elsewhere.
13338 This might delete other dead insns recursively.
13339 First set the pattern to something that won't use
13341 rtx old_notes = REG_NOTES (tem);
13343 PATTERN (tem) = pc_rtx;
13344 REG_NOTES (tem) = NULL;
13346 distribute_notes (old_notes, tem, tem, NULL_RTX,
13347 NULL_RTX, NULL_RTX, NULL_RTX);
13348 distribute_links (LOG_LINKS (tem));
13350 SET_INSN_DELETED (tem);
13355 /* Delete the setter too. */
13358 PATTERN (cc0_setter) = pc_rtx;
13359 old_notes = REG_NOTES (cc0_setter);
13360 REG_NOTES (cc0_setter) = NULL;
13362 distribute_notes (old_notes, cc0_setter,
13363 cc0_setter, NULL_RTX,
13364 NULL_RTX, NULL_RTX, NULL_RTX);
13365 distribute_links (LOG_LINKS (cc0_setter));
13367 SET_INSN_DELETED (cc0_setter);
13368 if (cc0_setter == i2)
13375 PUT_REG_NOTE_KIND (note, REG_UNUSED);
13377 /* If there isn't already a REG_UNUSED note, put one
13378 here. Do not place a REG_DEAD note, even if
13379 the register is also used here; that would not
13380 match the algorithm used in lifetime analysis
13381 and can cause the consistency check in the
13382 scheduler to fail. */
13383 if (! find_regno_note (tem, REG_UNUSED,
13384 REGNO (XEXP (note, 0))))
13389 else if (reg_referenced_p (XEXP (note, 0), PATTERN (tem))
13391 && find_reg_fusage (tem, USE, XEXP (note, 0))))
13395 /* If we are doing a 3->2 combination, and we have a
13396 register which formerly died in i3 and was not used
13397 by i2, which now no longer dies in i3 and is used in
13398 i2 but does not die in i2, and place is between i2
13399 and i3, then we may need to move a link from place to
13401 if (i2 && DF_INSN_LUID (place) > DF_INSN_LUID (i2)
13403 && DF_INSN_LUID (from_insn) > DF_INSN_LUID (i2)
13404 && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
13406 rtx links = LOG_LINKS (place);
13407 LOG_LINKS (place) = 0;
13408 distribute_links (links);
13413 if (tem == BB_HEAD (bb))
13419 /* If the register is set or already dead at PLACE, we needn't do
13420 anything with this note if it is still a REG_DEAD note.
13421 We check here if it is set at all, not if is it totally replaced,
13422 which is what `dead_or_set_p' checks, so also check for it being
13425 if (place && REG_NOTE_KIND (note) == REG_DEAD)
13427 unsigned int regno = REGNO (XEXP (note, 0));
13428 reg_stat_type *rsp = VEC_index (reg_stat_type, reg_stat, regno);
13430 if (dead_or_set_p (place, XEXP (note, 0))
13431 || reg_bitfield_target_p (XEXP (note, 0), PATTERN (place)))
13433 /* Unless the register previously died in PLACE, clear
13434 last_death. [I no longer understand why this is
13436 if (rsp->last_death != place)
13437 rsp->last_death = 0;
13441 rsp->last_death = place;
13443 /* If this is a death note for a hard reg that is occupying
13444 multiple registers, ensure that we are still using all
13445 parts of the object. If we find a piece of the object
13446 that is unused, we must arrange for an appropriate REG_DEAD
13447 note to be added for it. However, we can't just emit a USE
13448 and tag the note to it, since the register might actually
13449 be dead; so we recourse, and the recursive call then finds
13450 the previous insn that used this register. */
13452 if (place && regno < FIRST_PSEUDO_REGISTER
13453 && hard_regno_nregs[regno][GET_MODE (XEXP (note, 0))] > 1)
13455 unsigned int endregno = END_HARD_REGNO (XEXP (note, 0));
13459 for (i = regno; i < endregno; i++)
13460 if ((! refers_to_regno_p (i, i + 1, PATTERN (place), 0)
13461 && ! find_regno_fusage (place, USE, i))
13462 || dead_or_set_regno_p (place, i))
13467 /* Put only REG_DEAD notes for pieces that are
13468 not already dead or set. */
13470 for (i = regno; i < endregno;
13471 i += hard_regno_nregs[i][reg_raw_mode[i]])
13473 rtx piece = regno_reg_rtx[i];
13474 basic_block bb = this_basic_block;
13476 if (! dead_or_set_p (place, piece)
13477 && ! reg_bitfield_target_p (piece,
13480 rtx new_note = alloc_reg_note (REG_DEAD, piece,
13483 distribute_notes (new_note, place, place,
13484 NULL_RTX, NULL_RTX, NULL_RTX,
13487 else if (! refers_to_regno_p (i, i + 1,
13488 PATTERN (place), 0)
13489 && ! find_regno_fusage (place, USE, i))
13490 for (tem = PREV_INSN (place); ;
13491 tem = PREV_INSN (tem))
13493 if (!NONDEBUG_INSN_P (tem))
13495 if (tem == BB_HEAD (bb))
13499 if (dead_or_set_p (tem, piece)
13500 || reg_bitfield_target_p (piece,
13503 add_reg_note (tem, REG_UNUSED, piece);
13517 /* Any other notes should not be present at this point in the
13519 gcc_unreachable ();
13524 XEXP (note, 1) = REG_NOTES (place);
13525 REG_NOTES (place) = note;
13529 add_reg_note (place2, REG_NOTE_KIND (note), XEXP (note, 0));
13533 /* Similarly to above, distribute the LOG_LINKS that used to be present on
13534 I3, I2, and I1 to new locations. This is also called to add a link
13535 pointing at I3 when I3's destination is changed. */
13538 distribute_links (rtx links)
13540 rtx link, next_link;
13542 for (link = links; link; link = next_link)
13548 next_link = XEXP (link, 1);
13550 /* If the insn that this link points to is a NOTE or isn't a single
13551 set, ignore it. In the latter case, it isn't clear what we
13552 can do other than ignore the link, since we can't tell which
13553 register it was for. Such links wouldn't be used by combine
13556 It is not possible for the destination of the target of the link to
13557 have been changed by combine. The only potential of this is if we
13558 replace I3, I2, and I1 by I3 and I2. But in that case the
13559 destination of I2 also remains unchanged. */
13561 if (NOTE_P (XEXP (link, 0))
13562 || (set = single_set (XEXP (link, 0))) == 0)
13565 reg = SET_DEST (set);
13566 while (GET_CODE (reg) == SUBREG || GET_CODE (reg) == ZERO_EXTRACT
13567 || GET_CODE (reg) == STRICT_LOW_PART)
13568 reg = XEXP (reg, 0);
13570 /* A LOG_LINK is defined as being placed on the first insn that uses
13571 a register and points to the insn that sets the register. Start
13572 searching at the next insn after the target of the link and stop
13573 when we reach a set of the register or the end of the basic block.
13575 Note that this correctly handles the link that used to point from
13576 I3 to I2. Also note that not much searching is typically done here
13577 since most links don't point very far away. */
13579 for (insn = NEXT_INSN (XEXP (link, 0));
13580 (insn && (this_basic_block->next_bb == EXIT_BLOCK_PTR
13581 || BB_HEAD (this_basic_block->next_bb) != insn));
13582 insn = NEXT_INSN (insn))
13583 if (DEBUG_INSN_P (insn))
13585 else if (INSN_P (insn) && reg_overlap_mentioned_p (reg, PATTERN (insn)))
13587 if (reg_referenced_p (reg, PATTERN (insn)))
13591 else if (CALL_P (insn)
13592 && find_reg_fusage (insn, USE, reg))
13597 else if (INSN_P (insn) && reg_set_p (reg, insn))
13600 /* If we found a place to put the link, place it there unless there
13601 is already a link to the same insn as LINK at that point. */
13607 for (link2 = LOG_LINKS (place); link2; link2 = XEXP (link2, 1))
13608 if (XEXP (link2, 0) == XEXP (link, 0))
13613 XEXP (link, 1) = LOG_LINKS (place);
13614 LOG_LINKS (place) = link;
13616 /* Set added_links_insn to the earliest insn we added a
13618 if (added_links_insn == 0
13619 || DF_INSN_LUID (added_links_insn) > DF_INSN_LUID (place))
13620 added_links_insn = place;
13626 /* Subroutine of unmentioned_reg_p and callback from for_each_rtx.
13627 Check whether the expression pointer to by LOC is a register or
13628 memory, and if so return 1 if it isn't mentioned in the rtx EXPR.
13629 Otherwise return zero. */
13632 unmentioned_reg_p_1 (rtx *loc, void *expr)
13637 && (REG_P (x) || MEM_P (x))
13638 && ! reg_mentioned_p (x, (rtx) expr))
13643 /* Check for any register or memory mentioned in EQUIV that is not
13644 mentioned in EXPR. This is used to restrict EQUIV to "specializations"
13645 of EXPR where some registers may have been replaced by constants. */
13648 unmentioned_reg_p (rtx equiv, rtx expr)
13650 return for_each_rtx (&equiv, unmentioned_reg_p_1, expr);
13654 dump_combine_stats (FILE *file)
13658 ";; Combiner statistics: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n\n",
13659 combine_attempts, combine_merges, combine_extras, combine_successes);
13663 dump_combine_total_stats (FILE *file)
13667 "\n;; Combiner totals: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n",
13668 total_attempts, total_merges, total_extras, total_successes);
13672 gate_handle_combine (void)
13674 return (optimize > 0);
13677 /* Try combining insns through substitution. */
13678 static unsigned int
13679 rest_of_handle_combine (void)
13681 int rebuild_jump_labels_after_combine;
13683 df_set_flags (DF_LR_RUN_DCE + DF_DEFER_INSN_RESCAN);
13684 df_note_add_problem ();
13687 regstat_init_n_sets_and_refs ();
13689 rebuild_jump_labels_after_combine
13690 = combine_instructions (get_insns (), max_reg_num ());
13692 /* Combining insns may have turned an indirect jump into a
13693 direct jump. Rebuild the JUMP_LABEL fields of jumping
13695 if (rebuild_jump_labels_after_combine)
13697 timevar_push (TV_JUMP);
13698 rebuild_jump_labels (get_insns ());
13700 timevar_pop (TV_JUMP);
13703 regstat_free_n_sets_and_refs ();
13707 struct rtl_opt_pass pass_combine =
13711 "combine", /* name */
13712 gate_handle_combine, /* gate */
13713 rest_of_handle_combine, /* execute */
13716 0, /* static_pass_number */
13717 TV_COMBINE, /* tv_id */
13718 PROP_cfglayout, /* properties_required */
13719 0, /* properties_provided */
13720 0, /* properties_destroyed */
13721 0, /* todo_flags_start */
13723 TODO_df_finish | TODO_verify_rtl_sharing |
13724 TODO_ggc_collect, /* todo_flags_finish */
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