1 /* Optimize by combining instructions for GNU compiler.
2 Copyright (C) 1987, 1988, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009
4 Free Software Foundation, Inc.
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify it under
9 the terms of the GNU General Public License as published by the Free
10 Software Foundation; either version 3, or (at your option) any later
13 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
14 WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
22 /* This module is essentially the "combiner" phase of the U. of Arizona
23 Portable Optimizer, but redone to work on our list-structured
24 representation for RTL instead of their string representation.
26 The LOG_LINKS of each insn identify the most recent assignment
27 to each REG used in the insn. It is a list of previous insns,
28 each of which contains a SET for a REG that is used in this insn
29 and not used or set in between. LOG_LINKs never cross basic blocks.
30 They were set up by the preceding pass (lifetime analysis).
32 We try to combine each pair of insns joined by a logical link.
33 We also try to combine triples of insns A, B and C when
34 C has a link back to B and B has a link back to A.
36 LOG_LINKS does not have links for use of the CC0. They don't
37 need to, because the insn that sets the CC0 is always immediately
38 before the insn that tests it. So we always regard a branch
39 insn as having a logical link to the preceding insn. The same is true
40 for an insn explicitly using CC0.
42 We check (with use_crosses_set_p) to avoid combining in such a way
43 as to move a computation to a place where its value would be different.
45 Combination is done by mathematically substituting the previous
46 insn(s) values for the regs they set into the expressions in
47 the later insns that refer to these regs. If the result is a valid insn
48 for our target machine, according to the machine description,
49 we install it, delete the earlier insns, and update the data flow
50 information (LOG_LINKS and REG_NOTES) for what we did.
52 There are a few exceptions where the dataflow information isn't
53 completely updated (however this is only a local issue since it is
54 regenerated before the next pass that uses it):
56 - reg_live_length is not updated
57 - reg_n_refs is not adjusted in the rare case when a register is
58 no longer required in a computation
59 - there are extremely rare cases (see distribute_notes) when a
61 - a LOG_LINKS entry that refers to an insn with multiple SETs may be
62 removed because there is no way to know which register it was
65 To simplify substitution, we combine only when the earlier insn(s)
66 consist of only a single assignment. To simplify updating afterward,
67 we never combine when a subroutine call appears in the middle.
69 Since we do not represent assignments to CC0 explicitly except when that
70 is all an insn does, there is no LOG_LINKS entry in an insn that uses
71 the condition code for the insn that set the condition code.
72 Fortunately, these two insns must be consecutive.
73 Therefore, every JUMP_INSN is taken to have an implicit logical link
74 to the preceding insn. This is not quite right, since non-jumps can
75 also use the condition code; but in practice such insns would not
80 #include "coretypes.h"
87 #include "hard-reg-set.h"
88 #include "basic-block.h"
89 #include "insn-config.h"
91 /* Include expr.h after insn-config.h so we get HAVE_conditional_move. */
93 #include "insn-attr.h"
99 #include "insn-codes.h"
100 #include "rtlhooks-def.h"
101 /* Include output.h for dump_file. */
105 #include "tree-pass.h"
109 /* Number of attempts to combine instructions in this function. */
111 static int combine_attempts;
113 /* Number of attempts that got as far as substitution in this function. */
115 static int combine_merges;
117 /* Number of instructions combined with added SETs in this function. */
119 static int combine_extras;
121 /* Number of instructions combined in this function. */
123 static int combine_successes;
125 /* Totals over entire compilation. */
127 static int total_attempts, total_merges, total_extras, total_successes;
129 /* combine_instructions may try to replace the right hand side of the
130 second instruction with the value of an associated REG_EQUAL note
131 before throwing it at try_combine. That is problematic when there
132 is a REG_DEAD note for a register used in the old right hand side
133 and can cause distribute_notes to do wrong things. This is the
134 second instruction if it has been so modified, null otherwise. */
138 /* When I2MOD is nonnull, this is a copy of the old right hand side. */
140 static rtx i2mod_old_rhs;
142 /* When I2MOD is nonnull, this is a copy of the new right hand side. */
144 static rtx i2mod_new_rhs;
146 typedef struct reg_stat_struct {
147 /* Record last point of death of (hard or pseudo) register n. */
150 /* Record last point of modification of (hard or pseudo) register n. */
153 /* The next group of fields allows the recording of the last value assigned
154 to (hard or pseudo) register n. We use this information to see if an
155 operation being processed is redundant given a prior operation performed
156 on the register. For example, an `and' with a constant is redundant if
157 all the zero bits are already known to be turned off.
159 We use an approach similar to that used by cse, but change it in the
162 (1) We do not want to reinitialize at each label.
163 (2) It is useful, but not critical, to know the actual value assigned
164 to a register. Often just its form is helpful.
166 Therefore, we maintain the following fields:
168 last_set_value the last value assigned
169 last_set_label records the value of label_tick when the
170 register was assigned
171 last_set_table_tick records the value of label_tick when a
172 value using the register is assigned
173 last_set_invalid set to nonzero when it is not valid
174 to use the value of this register in some
177 To understand the usage of these tables, it is important to understand
178 the distinction between the value in last_set_value being valid and
179 the register being validly contained in some other expression in the
182 (The next two parameters are out of date).
184 reg_stat[i].last_set_value is valid if it is nonzero, and either
185 reg_n_sets[i] is 1 or reg_stat[i].last_set_label == label_tick.
187 Register I may validly appear in any expression returned for the value
188 of another register if reg_n_sets[i] is 1. It may also appear in the
189 value for register J if reg_stat[j].last_set_invalid is zero, or
190 reg_stat[i].last_set_label < reg_stat[j].last_set_label.
192 If an expression is found in the table containing a register which may
193 not validly appear in an expression, the register is replaced by
194 something that won't match, (clobber (const_int 0)). */
196 /* Record last value assigned to (hard or pseudo) register n. */
200 /* Record the value of label_tick when an expression involving register n
201 is placed in last_set_value. */
203 int last_set_table_tick;
205 /* Record the value of label_tick when the value for register n is placed in
210 /* These fields are maintained in parallel with last_set_value and are
211 used to store the mode in which the register was last set, the bits
212 that were known to be zero when it was last set, and the number of
213 sign bits copies it was known to have when it was last set. */
215 unsigned HOST_WIDE_INT last_set_nonzero_bits;
216 char last_set_sign_bit_copies;
217 ENUM_BITFIELD(machine_mode) last_set_mode : 8;
219 /* Set nonzero if references to register n in expressions should not be
220 used. last_set_invalid is set nonzero when this register is being
221 assigned to and last_set_table_tick == label_tick. */
223 char last_set_invalid;
225 /* Some registers that are set more than once and used in more than one
226 basic block are nevertheless always set in similar ways. For example,
227 a QImode register may be loaded from memory in two places on a machine
228 where byte loads zero extend.
230 We record in the following fields if a register has some leading bits
231 that are always equal to the sign bit, and what we know about the
232 nonzero bits of a register, specifically which bits are known to be
235 If an entry is zero, it means that we don't know anything special. */
237 unsigned char sign_bit_copies;
239 unsigned HOST_WIDE_INT nonzero_bits;
241 /* Record the value of the label_tick when the last truncation
242 happened. The field truncated_to_mode is only valid if
243 truncation_label == label_tick. */
245 int truncation_label;
247 /* Record the last truncation seen for this register. If truncation
248 is not a nop to this mode we might be able to save an explicit
249 truncation if we know that value already contains a truncated
252 ENUM_BITFIELD(machine_mode) truncated_to_mode : 8;
255 DEF_VEC_O(reg_stat_type);
256 DEF_VEC_ALLOC_O(reg_stat_type,heap);
258 static VEC(reg_stat_type,heap) *reg_stat;
260 /* Record the luid of the last insn that invalidated memory
261 (anything that writes memory, and subroutine calls, but not pushes). */
263 static int mem_last_set;
265 /* Record the luid of the last CALL_INSN
266 so we can tell whether a potential combination crosses any calls. */
268 static int last_call_luid;
270 /* When `subst' is called, this is the insn that is being modified
271 (by combining in a previous insn). The PATTERN of this insn
272 is still the old pattern partially modified and it should not be
273 looked at, but this may be used to examine the successors of the insn
274 to judge whether a simplification is valid. */
276 static rtx subst_insn;
278 /* This is the lowest LUID that `subst' is currently dealing with.
279 get_last_value will not return a value if the register was set at or
280 after this LUID. If not for this mechanism, we could get confused if
281 I2 or I1 in try_combine were an insn that used the old value of a register
282 to obtain a new value. In that case, we might erroneously get the
283 new value of the register when we wanted the old one. */
285 static int subst_low_luid;
287 /* This contains any hard registers that are used in newpat; reg_dead_at_p
288 must consider all these registers to be always live. */
290 static HARD_REG_SET newpat_used_regs;
292 /* This is an insn to which a LOG_LINKS entry has been added. If this
293 insn is the earlier than I2 or I3, combine should rescan starting at
296 static rtx added_links_insn;
298 /* Basic block in which we are performing combines. */
299 static basic_block this_basic_block;
300 static bool optimize_this_for_speed_p;
303 /* Length of the currently allocated uid_insn_cost array. */
305 static int max_uid_known;
307 /* The following array records the insn_rtx_cost for every insn
308 in the instruction stream. */
310 static int *uid_insn_cost;
312 /* The following array records the LOG_LINKS for every insn in the
313 instruction stream as an INSN_LIST rtx. */
315 static rtx *uid_log_links;
317 #define INSN_COST(INSN) (uid_insn_cost[INSN_UID (INSN)])
318 #define LOG_LINKS(INSN) (uid_log_links[INSN_UID (INSN)])
320 /* Incremented for each basic block. */
322 static int label_tick;
324 /* Reset to label_tick for each extended basic block in scanning order. */
326 static int label_tick_ebb_start;
328 /* Mode used to compute significance in reg_stat[].nonzero_bits. It is the
329 largest integer mode that can fit in HOST_BITS_PER_WIDE_INT. */
331 static enum machine_mode nonzero_bits_mode;
333 /* Nonzero when reg_stat[].nonzero_bits and reg_stat[].sign_bit_copies can
334 be safely used. It is zero while computing them and after combine has
335 completed. This former test prevents propagating values based on
336 previously set values, which can be incorrect if a variable is modified
339 static int nonzero_sign_valid;
342 /* Record one modification to rtl structure
343 to be undone by storing old_contents into *where. */
345 enum undo_kind { UNDO_RTX, UNDO_INT, UNDO_MODE };
351 union { rtx r; int i; enum machine_mode m; } old_contents;
352 union { rtx *r; int *i; } where;
355 /* Record a bunch of changes to be undone, up to MAX_UNDO of them.
356 num_undo says how many are currently recorded.
358 other_insn is nonzero if we have modified some other insn in the process
359 of working on subst_insn. It must be verified too. */
368 static struct undobuf undobuf;
370 /* Number of times the pseudo being substituted for
371 was found and replaced. */
373 static int n_occurrences;
375 static rtx reg_nonzero_bits_for_combine (const_rtx, enum machine_mode, const_rtx,
377 unsigned HOST_WIDE_INT,
378 unsigned HOST_WIDE_INT *);
379 static rtx reg_num_sign_bit_copies_for_combine (const_rtx, enum machine_mode, const_rtx,
381 unsigned int, unsigned int *);
382 static void do_SUBST (rtx *, rtx);
383 static void do_SUBST_INT (int *, int);
384 static void init_reg_last (void);
385 static void setup_incoming_promotions (rtx);
386 static void set_nonzero_bits_and_sign_copies (rtx, const_rtx, void *);
387 static int cant_combine_insn_p (rtx);
388 static int can_combine_p (rtx, rtx, rtx, rtx, rtx *, rtx *);
389 static int combinable_i3pat (rtx, rtx *, rtx, rtx, int, rtx *);
390 static int contains_muldiv (rtx);
391 static rtx try_combine (rtx, rtx, rtx, int *);
392 static void undo_all (void);
393 static void undo_commit (void);
394 static rtx *find_split_point (rtx *, rtx);
395 static rtx subst (rtx, rtx, rtx, int, int);
396 static rtx combine_simplify_rtx (rtx, enum machine_mode, int);
397 static rtx simplify_if_then_else (rtx);
398 static rtx simplify_set (rtx);
399 static rtx simplify_logical (rtx);
400 static rtx expand_compound_operation (rtx);
401 static const_rtx expand_field_assignment (const_rtx);
402 static rtx make_extraction (enum machine_mode, rtx, HOST_WIDE_INT,
403 rtx, unsigned HOST_WIDE_INT, int, int, int);
404 static rtx extract_left_shift (rtx, int);
405 static rtx make_compound_operation (rtx, enum rtx_code);
406 static int get_pos_from_mask (unsigned HOST_WIDE_INT,
407 unsigned HOST_WIDE_INT *);
408 static rtx canon_reg_for_combine (rtx, rtx);
409 static rtx force_to_mode (rtx, enum machine_mode,
410 unsigned HOST_WIDE_INT, int);
411 static rtx if_then_else_cond (rtx, rtx *, rtx *);
412 static rtx known_cond (rtx, enum rtx_code, rtx, rtx);
413 static int rtx_equal_for_field_assignment_p (rtx, rtx);
414 static rtx make_field_assignment (rtx);
415 static rtx apply_distributive_law (rtx);
416 static rtx distribute_and_simplify_rtx (rtx, int);
417 static rtx simplify_and_const_int_1 (enum machine_mode, rtx,
418 unsigned HOST_WIDE_INT);
419 static rtx simplify_and_const_int (rtx, enum machine_mode, rtx,
420 unsigned HOST_WIDE_INT);
421 static int merge_outer_ops (enum rtx_code *, HOST_WIDE_INT *, enum rtx_code,
422 HOST_WIDE_INT, enum machine_mode, int *);
423 static rtx simplify_shift_const_1 (enum rtx_code, enum machine_mode, rtx, int);
424 static rtx simplify_shift_const (rtx, enum rtx_code, enum machine_mode, rtx,
426 static int recog_for_combine (rtx *, rtx, rtx *);
427 static rtx gen_lowpart_for_combine (enum machine_mode, rtx);
428 static enum rtx_code simplify_comparison (enum rtx_code, rtx *, rtx *);
429 static void update_table_tick (rtx);
430 static void record_value_for_reg (rtx, rtx, rtx);
431 static void check_promoted_subreg (rtx, rtx);
432 static void record_dead_and_set_regs_1 (rtx, const_rtx, void *);
433 static void record_dead_and_set_regs (rtx);
434 static int get_last_value_validate (rtx *, rtx, int, int);
435 static rtx get_last_value (const_rtx);
436 static int use_crosses_set_p (const_rtx, int);
437 static void reg_dead_at_p_1 (rtx, const_rtx, void *);
438 static int reg_dead_at_p (rtx, rtx);
439 static void move_deaths (rtx, rtx, int, rtx, rtx *);
440 static int reg_bitfield_target_p (rtx, rtx);
441 static void distribute_notes (rtx, rtx, rtx, rtx, rtx, rtx);
442 static void distribute_links (rtx);
443 static void mark_used_regs_combine (rtx);
444 static void record_promoted_value (rtx, rtx);
445 static int unmentioned_reg_p_1 (rtx *, void *);
446 static bool unmentioned_reg_p (rtx, rtx);
447 static int record_truncated_value (rtx *, void *);
448 static void record_truncated_values (rtx *, void *);
449 static bool reg_truncated_to_mode (enum machine_mode, const_rtx);
450 static rtx gen_lowpart_or_truncate (enum machine_mode, rtx);
453 /* It is not safe to use ordinary gen_lowpart in combine.
454 See comments in gen_lowpart_for_combine. */
455 #undef RTL_HOOKS_GEN_LOWPART
456 #define RTL_HOOKS_GEN_LOWPART gen_lowpart_for_combine
458 /* Our implementation of gen_lowpart never emits a new pseudo. */
459 #undef RTL_HOOKS_GEN_LOWPART_NO_EMIT
460 #define RTL_HOOKS_GEN_LOWPART_NO_EMIT gen_lowpart_for_combine
462 #undef RTL_HOOKS_REG_NONZERO_REG_BITS
463 #define RTL_HOOKS_REG_NONZERO_REG_BITS reg_nonzero_bits_for_combine
465 #undef RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES
466 #define RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES reg_num_sign_bit_copies_for_combine
468 #undef RTL_HOOKS_REG_TRUNCATED_TO_MODE
469 #define RTL_HOOKS_REG_TRUNCATED_TO_MODE reg_truncated_to_mode
471 static const struct rtl_hooks combine_rtl_hooks = RTL_HOOKS_INITIALIZER;
474 /* Try to split PATTERN found in INSN. This returns NULL_RTX if
475 PATTERN can not be split. Otherwise, it returns an insn sequence.
476 This is a wrapper around split_insns which ensures that the
477 reg_stat vector is made larger if the splitter creates a new
481 combine_split_insns (rtx pattern, rtx insn)
486 ret = split_insns (pattern, insn);
487 nregs = max_reg_num ();
488 if (nregs > VEC_length (reg_stat_type, reg_stat))
489 VEC_safe_grow_cleared (reg_stat_type, heap, reg_stat, nregs);
493 /* This is used by find_single_use to locate an rtx in LOC that
494 contains exactly one use of DEST, which is typically either a REG
495 or CC0. It returns a pointer to the innermost rtx expression
496 containing DEST. Appearances of DEST that are being used to
497 totally replace it are not counted. */
500 find_single_use_1 (rtx dest, rtx *loc)
503 enum rtx_code code = GET_CODE (x);
521 /* If the destination is anything other than CC0, PC, a REG or a SUBREG
522 of a REG that occupies all of the REG, the insn uses DEST if
523 it is mentioned in the destination or the source. Otherwise, we
524 need just check the source. */
525 if (GET_CODE (SET_DEST (x)) != CC0
526 && GET_CODE (SET_DEST (x)) != PC
527 && !REG_P (SET_DEST (x))
528 && ! (GET_CODE (SET_DEST (x)) == SUBREG
529 && REG_P (SUBREG_REG (SET_DEST (x)))
530 && (((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x))))
531 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
532 == ((GET_MODE_SIZE (GET_MODE (SET_DEST (x)))
533 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD))))
536 return find_single_use_1 (dest, &SET_SRC (x));
540 return find_single_use_1 (dest, &XEXP (x, 0));
546 /* If it wasn't one of the common cases above, check each expression and
547 vector of this code. Look for a unique usage of DEST. */
549 fmt = GET_RTX_FORMAT (code);
550 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
554 if (dest == XEXP (x, i)
555 || (REG_P (dest) && REG_P (XEXP (x, i))
556 && REGNO (dest) == REGNO (XEXP (x, i))))
559 this_result = find_single_use_1 (dest, &XEXP (x, i));
562 result = this_result;
563 else if (this_result)
564 /* Duplicate usage. */
567 else if (fmt[i] == 'E')
571 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
573 if (XVECEXP (x, i, j) == dest
575 && REG_P (XVECEXP (x, i, j))
576 && REGNO (XVECEXP (x, i, j)) == REGNO (dest)))
579 this_result = find_single_use_1 (dest, &XVECEXP (x, i, j));
582 result = this_result;
583 else if (this_result)
593 /* See if DEST, produced in INSN, is used only a single time in the
594 sequel. If so, return a pointer to the innermost rtx expression in which
597 If PLOC is nonzero, *PLOC is set to the insn containing the single use.
599 If DEST is cc0_rtx, we look only at the next insn. In that case, we don't
600 care about REG_DEAD notes or LOG_LINKS.
602 Otherwise, we find the single use by finding an insn that has a
603 LOG_LINKS pointing at INSN and has a REG_DEAD note for DEST. If DEST is
604 only referenced once in that insn, we know that it must be the first
605 and last insn referencing DEST. */
608 find_single_use (rtx dest, rtx insn, rtx *ploc)
618 next = NEXT_INSN (insn);
620 || (!NONJUMP_INSN_P (next) && !JUMP_P (next)))
623 result = find_single_use_1 (dest, &PATTERN (next));
633 bb = BLOCK_FOR_INSN (insn);
634 for (next = NEXT_INSN (insn);
635 next && BLOCK_FOR_INSN (next) == bb;
636 next = NEXT_INSN (next))
637 if (INSN_P (next) && dead_or_set_p (next, dest))
639 for (link = LOG_LINKS (next); link; link = XEXP (link, 1))
640 if (XEXP (link, 0) == insn)
645 result = find_single_use_1 (dest, &PATTERN (next));
655 /* Substitute NEWVAL, an rtx expression, into INTO, a place in some
656 insn. The substitution can be undone by undo_all. If INTO is already
657 set to NEWVAL, do not record this change. Because computing NEWVAL might
658 also call SUBST, we have to compute it before we put anything into
662 do_SUBST (rtx *into, rtx newval)
667 if (oldval == newval)
670 /* We'd like to catch as many invalid transformations here as
671 possible. Unfortunately, there are way too many mode changes
672 that are perfectly valid, so we'd waste too much effort for
673 little gain doing the checks here. Focus on catching invalid
674 transformations involving integer constants. */
675 if (GET_MODE_CLASS (GET_MODE (oldval)) == MODE_INT
676 && CONST_INT_P (newval))
678 /* Sanity check that we're replacing oldval with a CONST_INT
679 that is a valid sign-extension for the original mode. */
680 gcc_assert (INTVAL (newval)
681 == trunc_int_for_mode (INTVAL (newval), GET_MODE (oldval)));
683 /* Replacing the operand of a SUBREG or a ZERO_EXTEND with a
684 CONST_INT is not valid, because after the replacement, the
685 original mode would be gone. Unfortunately, we can't tell
686 when do_SUBST is called to replace the operand thereof, so we
687 perform this test on oldval instead, checking whether an
688 invalid replacement took place before we got here. */
689 gcc_assert (!(GET_CODE (oldval) == SUBREG
690 && CONST_INT_P (SUBREG_REG (oldval))));
691 gcc_assert (!(GET_CODE (oldval) == ZERO_EXTEND
692 && CONST_INT_P (XEXP (oldval, 0))));
696 buf = undobuf.frees, undobuf.frees = buf->next;
698 buf = XNEW (struct undo);
700 buf->kind = UNDO_RTX;
702 buf->old_contents.r = oldval;
705 buf->next = undobuf.undos, undobuf.undos = buf;
708 #define SUBST(INTO, NEWVAL) do_SUBST(&(INTO), (NEWVAL))
710 /* Similar to SUBST, but NEWVAL is an int expression. Note that substitution
711 for the value of a HOST_WIDE_INT value (including CONST_INT) is
715 do_SUBST_INT (int *into, int newval)
720 if (oldval == newval)
724 buf = undobuf.frees, undobuf.frees = buf->next;
726 buf = XNEW (struct undo);
728 buf->kind = UNDO_INT;
730 buf->old_contents.i = oldval;
733 buf->next = undobuf.undos, undobuf.undos = buf;
736 #define SUBST_INT(INTO, NEWVAL) do_SUBST_INT(&(INTO), (NEWVAL))
738 /* Similar to SUBST, but just substitute the mode. This is used when
739 changing the mode of a pseudo-register, so that any other
740 references to the entry in the regno_reg_rtx array will change as
744 do_SUBST_MODE (rtx *into, enum machine_mode newval)
747 enum machine_mode oldval = GET_MODE (*into);
749 if (oldval == newval)
753 buf = undobuf.frees, undobuf.frees = buf->next;
755 buf = XNEW (struct undo);
757 buf->kind = UNDO_MODE;
759 buf->old_contents.m = oldval;
760 adjust_reg_mode (*into, newval);
762 buf->next = undobuf.undos, undobuf.undos = buf;
765 #define SUBST_MODE(INTO, NEWVAL) do_SUBST_MODE(&(INTO), (NEWVAL))
767 /* Subroutine of try_combine. Determine whether the combine replacement
768 patterns NEWPAT, NEWI2PAT and NEWOTHERPAT are cheaper according to
769 insn_rtx_cost that the original instruction sequence I1, I2, I3 and
770 undobuf.other_insn. Note that I1 and/or NEWI2PAT may be NULL_RTX.
771 NEWOTHERPAT and undobuf.other_insn may also both be NULL_RTX. This
772 function returns false, if the costs of all instructions can be
773 estimated, and the replacements are more expensive than the original
777 combine_validate_cost (rtx i1, rtx i2, rtx i3, rtx newpat, rtx newi2pat,
780 int i1_cost, i2_cost, i3_cost;
781 int new_i2_cost, new_i3_cost;
782 int old_cost, new_cost;
784 /* Lookup the original insn_rtx_costs. */
785 i2_cost = INSN_COST (i2);
786 i3_cost = INSN_COST (i3);
790 i1_cost = INSN_COST (i1);
791 old_cost = (i1_cost > 0 && i2_cost > 0 && i3_cost > 0)
792 ? i1_cost + i2_cost + i3_cost : 0;
796 old_cost = (i2_cost > 0 && i3_cost > 0) ? i2_cost + i3_cost : 0;
800 /* Calculate the replacement insn_rtx_costs. */
801 new_i3_cost = insn_rtx_cost (newpat, optimize_this_for_speed_p);
804 new_i2_cost = insn_rtx_cost (newi2pat, optimize_this_for_speed_p);
805 new_cost = (new_i2_cost > 0 && new_i3_cost > 0)
806 ? new_i2_cost + new_i3_cost : 0;
810 new_cost = new_i3_cost;
814 if (undobuf.other_insn)
816 int old_other_cost, new_other_cost;
818 old_other_cost = INSN_COST (undobuf.other_insn);
819 new_other_cost = insn_rtx_cost (newotherpat, optimize_this_for_speed_p);
820 if (old_other_cost > 0 && new_other_cost > 0)
822 old_cost += old_other_cost;
823 new_cost += new_other_cost;
829 /* Disallow this recombination if both new_cost and old_cost are
830 greater than zero, and new_cost is greater than old cost. */
832 && new_cost > old_cost)
839 "rejecting combination of insns %d, %d and %d\n",
840 INSN_UID (i1), INSN_UID (i2), INSN_UID (i3));
841 fprintf (dump_file, "original costs %d + %d + %d = %d\n",
842 i1_cost, i2_cost, i3_cost, old_cost);
847 "rejecting combination of insns %d and %d\n",
848 INSN_UID (i2), INSN_UID (i3));
849 fprintf (dump_file, "original costs %d + %d = %d\n",
850 i2_cost, i3_cost, old_cost);
855 fprintf (dump_file, "replacement costs %d + %d = %d\n",
856 new_i2_cost, new_i3_cost, new_cost);
859 fprintf (dump_file, "replacement cost %d\n", new_cost);
865 /* Update the uid_insn_cost array with the replacement costs. */
866 INSN_COST (i2) = new_i2_cost;
867 INSN_COST (i3) = new_i3_cost;
875 /* Delete any insns that copy a register to itself. */
878 delete_noop_moves (void)
885 for (insn = BB_HEAD (bb); insn != NEXT_INSN (BB_END (bb)); insn = next)
887 next = NEXT_INSN (insn);
888 if (INSN_P (insn) && noop_move_p (insn))
891 fprintf (dump_file, "deleting noop move %d\n", INSN_UID (insn));
893 delete_insn_and_edges (insn);
900 /* Fill in log links field for all insns. */
903 create_log_links (void)
907 df_ref *def_vec, *use_vec;
909 next_use = XCNEWVEC (rtx, max_reg_num ());
911 /* Pass through each block from the end, recording the uses of each
912 register and establishing log links when def is encountered.
913 Note that we do not clear next_use array in order to save time,
914 so we have to test whether the use is in the same basic block as def.
916 There are a few cases below when we do not consider the definition or
917 usage -- these are taken from original flow.c did. Don't ask me why it is
918 done this way; I don't know and if it works, I don't want to know. */
922 FOR_BB_INSNS_REVERSE (bb, insn)
924 if (!NONDEBUG_INSN_P (insn))
927 /* Log links are created only once. */
928 gcc_assert (!LOG_LINKS (insn));
930 for (def_vec = DF_INSN_DEFS (insn); *def_vec; def_vec++)
932 df_ref def = *def_vec;
933 int regno = DF_REF_REGNO (def);
936 if (!next_use[regno])
939 /* Do not consider if it is pre/post modification in MEM. */
940 if (DF_REF_FLAGS (def) & DF_REF_PRE_POST_MODIFY)
943 /* Do not make the log link for frame pointer. */
944 if ((regno == FRAME_POINTER_REGNUM
945 && (! reload_completed || frame_pointer_needed))
946 #if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM
947 || (regno == HARD_FRAME_POINTER_REGNUM
948 && (! reload_completed || frame_pointer_needed))
950 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
951 || (regno == ARG_POINTER_REGNUM && fixed_regs[regno])
956 use_insn = next_use[regno];
957 if (BLOCK_FOR_INSN (use_insn) == bb)
961 We don't build a LOG_LINK for hard registers contained
962 in ASM_OPERANDs. If these registers get replaced,
963 we might wind up changing the semantics of the insn,
964 even if reload can make what appear to be valid
965 assignments later. */
966 if (regno >= FIRST_PSEUDO_REGISTER
967 || asm_noperands (PATTERN (use_insn)) < 0)
969 /* Don't add duplicate links between instructions. */
971 for (links = LOG_LINKS (use_insn); links;
972 links = XEXP (links, 1))
973 if (insn == XEXP (links, 0))
977 LOG_LINKS (use_insn) =
978 alloc_INSN_LIST (insn, LOG_LINKS (use_insn));
981 next_use[regno] = NULL_RTX;
984 for (use_vec = DF_INSN_USES (insn); *use_vec; use_vec++)
986 df_ref use = *use_vec;
987 int regno = DF_REF_REGNO (use);
989 /* Do not consider the usage of the stack pointer
991 if (DF_REF_FLAGS (use) & DF_REF_CALL_STACK_USAGE)
994 next_use[regno] = insn;
1002 /* Clear LOG_LINKS fields of insns. */
1005 clear_log_links (void)
1009 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
1011 free_INSN_LIST_list (&LOG_LINKS (insn));
1014 /* Main entry point for combiner. F is the first insn of the function.
1015 NREGS is the first unused pseudo-reg number.
1017 Return nonzero if the combiner has turned an indirect jump
1018 instruction into a direct jump. */
1020 combine_instructions (rtx f, unsigned int nregs)
1026 rtx links, nextlinks;
1028 basic_block last_bb;
1030 int new_direct_jump_p = 0;
1032 for (first = f; first && !INSN_P (first); )
1033 first = NEXT_INSN (first);
1037 combine_attempts = 0;
1040 combine_successes = 0;
1042 rtl_hooks = combine_rtl_hooks;
1044 VEC_safe_grow_cleared (reg_stat_type, heap, reg_stat, nregs);
1046 init_recog_no_volatile ();
1048 /* Allocate array for insn info. */
1049 max_uid_known = get_max_uid ();
1050 uid_log_links = XCNEWVEC (rtx, max_uid_known + 1);
1051 uid_insn_cost = XCNEWVEC (int, max_uid_known + 1);
1053 nonzero_bits_mode = mode_for_size (HOST_BITS_PER_WIDE_INT, MODE_INT, 0);
1055 /* Don't use reg_stat[].nonzero_bits when computing it. This can cause
1056 problems when, for example, we have j <<= 1 in a loop. */
1058 nonzero_sign_valid = 0;
1059 label_tick = label_tick_ebb_start = 1;
1061 /* Scan all SETs and see if we can deduce anything about what
1062 bits are known to be zero for some registers and how many copies
1063 of the sign bit are known to exist for those registers.
1065 Also set any known values so that we can use it while searching
1066 for what bits are known to be set. */
1068 setup_incoming_promotions (first);
1069 /* Allow the entry block and the first block to fall into the same EBB.
1070 Conceptually the incoming promotions are assigned to the entry block. */
1071 last_bb = ENTRY_BLOCK_PTR;
1073 create_log_links ();
1074 FOR_EACH_BB (this_basic_block)
1076 optimize_this_for_speed_p = optimize_bb_for_speed_p (this_basic_block);
1081 if (!single_pred_p (this_basic_block)
1082 || single_pred (this_basic_block) != last_bb)
1083 label_tick_ebb_start = label_tick;
1084 last_bb = this_basic_block;
1086 FOR_BB_INSNS (this_basic_block, insn)
1087 if (INSN_P (insn) && BLOCK_FOR_INSN (insn))
1089 subst_low_luid = DF_INSN_LUID (insn);
1092 note_stores (PATTERN (insn), set_nonzero_bits_and_sign_copies,
1094 record_dead_and_set_regs (insn);
1097 for (links = REG_NOTES (insn); links; links = XEXP (links, 1))
1098 if (REG_NOTE_KIND (links) == REG_INC)
1099 set_nonzero_bits_and_sign_copies (XEXP (links, 0), NULL_RTX,
1103 /* Record the current insn_rtx_cost of this instruction. */
1104 if (NONJUMP_INSN_P (insn))
1105 INSN_COST (insn) = insn_rtx_cost (PATTERN (insn),
1106 optimize_this_for_speed_p);
1108 fprintf(dump_file, "insn_cost %d: %d\n",
1109 INSN_UID (insn), INSN_COST (insn));
1113 nonzero_sign_valid = 1;
1115 /* Now scan all the insns in forward order. */
1116 label_tick = label_tick_ebb_start = 1;
1118 setup_incoming_promotions (first);
1119 last_bb = ENTRY_BLOCK_PTR;
1121 FOR_EACH_BB (this_basic_block)
1123 optimize_this_for_speed_p = optimize_bb_for_speed_p (this_basic_block);
1128 if (!single_pred_p (this_basic_block)
1129 || single_pred (this_basic_block) != last_bb)
1130 label_tick_ebb_start = label_tick;
1131 last_bb = this_basic_block;
1133 rtl_profile_for_bb (this_basic_block);
1134 for (insn = BB_HEAD (this_basic_block);
1135 insn != NEXT_INSN (BB_END (this_basic_block));
1136 insn = next ? next : NEXT_INSN (insn))
1139 if (NONDEBUG_INSN_P (insn))
1141 /* See if we know about function return values before this
1142 insn based upon SUBREG flags. */
1143 check_promoted_subreg (insn, PATTERN (insn));
1145 /* See if we can find hardregs and subreg of pseudos in
1146 narrower modes. This could help turning TRUNCATEs
1148 note_uses (&PATTERN (insn), record_truncated_values, NULL);
1150 /* Try this insn with each insn it links back to. */
1152 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
1153 if ((next = try_combine (insn, XEXP (links, 0),
1154 NULL_RTX, &new_direct_jump_p)) != 0)
1157 /* Try each sequence of three linked insns ending with this one. */
1159 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
1161 rtx link = XEXP (links, 0);
1163 /* If the linked insn has been replaced by a note, then there
1164 is no point in pursuing this chain any further. */
1168 for (nextlinks = LOG_LINKS (link);
1170 nextlinks = XEXP (nextlinks, 1))
1171 if ((next = try_combine (insn, link,
1172 XEXP (nextlinks, 0),
1173 &new_direct_jump_p)) != 0)
1178 /* Try to combine a jump insn that uses CC0
1179 with a preceding insn that sets CC0, and maybe with its
1180 logical predecessor as well.
1181 This is how we make decrement-and-branch insns.
1182 We need this special code because data flow connections
1183 via CC0 do not get entered in LOG_LINKS. */
1186 && (prev = prev_nonnote_insn (insn)) != 0
1187 && NONJUMP_INSN_P (prev)
1188 && sets_cc0_p (PATTERN (prev)))
1190 if ((next = try_combine (insn, prev,
1191 NULL_RTX, &new_direct_jump_p)) != 0)
1194 for (nextlinks = LOG_LINKS (prev); nextlinks;
1195 nextlinks = XEXP (nextlinks, 1))
1196 if ((next = try_combine (insn, prev,
1197 XEXP (nextlinks, 0),
1198 &new_direct_jump_p)) != 0)
1202 /* Do the same for an insn that explicitly references CC0. */
1203 if (NONJUMP_INSN_P (insn)
1204 && (prev = prev_nonnote_insn (insn)) != 0
1205 && NONJUMP_INSN_P (prev)
1206 && sets_cc0_p (PATTERN (prev))
1207 && GET_CODE (PATTERN (insn)) == SET
1208 && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (insn))))
1210 if ((next = try_combine (insn, prev,
1211 NULL_RTX, &new_direct_jump_p)) != 0)
1214 for (nextlinks = LOG_LINKS (prev); nextlinks;
1215 nextlinks = XEXP (nextlinks, 1))
1216 if ((next = try_combine (insn, prev,
1217 XEXP (nextlinks, 0),
1218 &new_direct_jump_p)) != 0)
1222 /* Finally, see if any of the insns that this insn links to
1223 explicitly references CC0. If so, try this insn, that insn,
1224 and its predecessor if it sets CC0. */
1225 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
1226 if (NONJUMP_INSN_P (XEXP (links, 0))
1227 && GET_CODE (PATTERN (XEXP (links, 0))) == SET
1228 && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (XEXP (links, 0))))
1229 && (prev = prev_nonnote_insn (XEXP (links, 0))) != 0
1230 && NONJUMP_INSN_P (prev)
1231 && sets_cc0_p (PATTERN (prev))
1232 && (next = try_combine (insn, XEXP (links, 0),
1233 prev, &new_direct_jump_p)) != 0)
1237 /* Try combining an insn with two different insns whose results it
1239 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
1240 for (nextlinks = XEXP (links, 1); nextlinks;
1241 nextlinks = XEXP (nextlinks, 1))
1242 if ((next = try_combine (insn, XEXP (links, 0),
1243 XEXP (nextlinks, 0),
1244 &new_direct_jump_p)) != 0)
1247 /* Try this insn with each REG_EQUAL note it links back to. */
1248 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
1251 rtx temp = XEXP (links, 0);
1252 if ((set = single_set (temp)) != 0
1253 && (note = find_reg_equal_equiv_note (temp)) != 0
1254 && (note = XEXP (note, 0), GET_CODE (note)) != EXPR_LIST
1255 /* Avoid using a register that may already been marked
1256 dead by an earlier instruction. */
1257 && ! unmentioned_reg_p (note, SET_SRC (set))
1258 && (GET_MODE (note) == VOIDmode
1259 ? SCALAR_INT_MODE_P (GET_MODE (SET_DEST (set)))
1260 : GET_MODE (SET_DEST (set)) == GET_MODE (note)))
1262 /* Temporarily replace the set's source with the
1263 contents of the REG_EQUAL note. The insn will
1264 be deleted or recognized by try_combine. */
1265 rtx orig = SET_SRC (set);
1266 SET_SRC (set) = note;
1268 i2mod_old_rhs = copy_rtx (orig);
1269 i2mod_new_rhs = copy_rtx (note);
1270 next = try_combine (insn, i2mod, NULL_RTX,
1271 &new_direct_jump_p);
1275 SET_SRC (set) = orig;
1280 record_dead_and_set_regs (insn);
1288 default_rtl_profile ();
1291 new_direct_jump_p |= purge_all_dead_edges ();
1292 delete_noop_moves ();
1295 free (uid_log_links);
1296 free (uid_insn_cost);
1297 VEC_free (reg_stat_type, heap, reg_stat);
1300 struct undo *undo, *next;
1301 for (undo = undobuf.frees; undo; undo = next)
1309 total_attempts += combine_attempts;
1310 total_merges += combine_merges;
1311 total_extras += combine_extras;
1312 total_successes += combine_successes;
1314 nonzero_sign_valid = 0;
1315 rtl_hooks = general_rtl_hooks;
1317 /* Make recognizer allow volatile MEMs again. */
1320 return new_direct_jump_p;
1323 /* Wipe the last_xxx fields of reg_stat in preparation for another pass. */
1326 init_reg_last (void)
1331 for (i = 0; VEC_iterate (reg_stat_type, reg_stat, i, p); ++i)
1332 memset (p, 0, offsetof (reg_stat_type, sign_bit_copies));
1335 /* Set up any promoted values for incoming argument registers. */
1338 setup_incoming_promotions (rtx first)
1341 bool strictly_local = false;
1343 for (arg = DECL_ARGUMENTS (current_function_decl); arg;
1344 arg = TREE_CHAIN (arg))
1346 rtx reg = DECL_INCOMING_RTL (arg);
1348 enum machine_mode mode1, mode2, mode3, mode4;
1350 /* Only continue if the incoming argument is in a register. */
1354 /* Determine, if possible, whether all call sites of the current
1355 function lie within the current compilation unit. (This does
1356 take into account the exporting of a function via taking its
1357 address, and so forth.) */
1358 strictly_local = cgraph_local_info (current_function_decl)->local;
1360 /* The mode and signedness of the argument before any promotions happen
1361 (equal to the mode of the pseudo holding it at that stage). */
1362 mode1 = TYPE_MODE (TREE_TYPE (arg));
1363 uns1 = TYPE_UNSIGNED (TREE_TYPE (arg));
1365 /* The mode and signedness of the argument after any source language and
1366 TARGET_PROMOTE_PROTOTYPES-driven promotions. */
1367 mode2 = TYPE_MODE (DECL_ARG_TYPE (arg));
1368 uns3 = TYPE_UNSIGNED (DECL_ARG_TYPE (arg));
1370 /* The mode and signedness of the argument as it is actually passed,
1371 after any TARGET_PROMOTE_FUNCTION_ARGS-driven ABI promotions. */
1372 mode3 = promote_function_mode (DECL_ARG_TYPE (arg), mode2, &uns3,
1373 TREE_TYPE (cfun->decl), 0);
1375 /* The mode of the register in which the argument is being passed. */
1376 mode4 = GET_MODE (reg);
1378 /* Eliminate sign extensions in the callee when possible. Only
1380 (a) a mode promotion has occurred;
1381 (b) the mode of the register is the same as the mode of
1382 the argument as it is passed; and
1383 (c) the signedness does not change across any of the promotions; and
1384 (d) when no language-level promotions (which we cannot guarantee
1385 will have been done by an external caller) are necessary,
1386 unless we know that this function is only ever called from
1387 the current compilation unit -- all of whose call sites will
1388 do the mode1 --> mode2 promotion. */
1392 && (mode1 == mode2 || strictly_local))
1394 /* Record that the value was promoted from mode1 to mode3,
1395 so that any sign extension at the head of the current
1396 function may be eliminated. */
1398 x = gen_rtx_CLOBBER (mode1, const0_rtx);
1399 x = gen_rtx_fmt_e ((uns3 ? ZERO_EXTEND : SIGN_EXTEND), mode3, x);
1400 record_value_for_reg (reg, first, x);
1405 /* Called via note_stores. If X is a pseudo that is narrower than
1406 HOST_BITS_PER_WIDE_INT and is being set, record what bits are known zero.
1408 If we are setting only a portion of X and we can't figure out what
1409 portion, assume all bits will be used since we don't know what will
1412 Similarly, set how many bits of X are known to be copies of the sign bit
1413 at all locations in the function. This is the smallest number implied
1417 set_nonzero_bits_and_sign_copies (rtx x, const_rtx set, void *data)
1419 rtx insn = (rtx) data;
1423 && REGNO (x) >= FIRST_PSEUDO_REGISTER
1424 /* If this register is undefined at the start of the file, we can't
1425 say what its contents were. */
1426 && ! REGNO_REG_SET_P
1427 (DF_LR_IN (ENTRY_BLOCK_PTR->next_bb), REGNO (x))
1428 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT)
1430 reg_stat_type *rsp = VEC_index (reg_stat_type, reg_stat, REGNO (x));
1432 if (set == 0 || GET_CODE (set) == CLOBBER)
1434 rsp->nonzero_bits = GET_MODE_MASK (GET_MODE (x));
1435 rsp->sign_bit_copies = 1;
1439 /* If this register is being initialized using itself, and the
1440 register is uninitialized in this basic block, and there are
1441 no LOG_LINKS which set the register, then part of the
1442 register is uninitialized. In that case we can't assume
1443 anything about the number of nonzero bits.
1445 ??? We could do better if we checked this in
1446 reg_{nonzero_bits,num_sign_bit_copies}_for_combine. Then we
1447 could avoid making assumptions about the insn which initially
1448 sets the register, while still using the information in other
1449 insns. We would have to be careful to check every insn
1450 involved in the combination. */
1453 && reg_referenced_p (x, PATTERN (insn))
1454 && !REGNO_REG_SET_P (DF_LR_IN (BLOCK_FOR_INSN (insn)),
1459 for (link = LOG_LINKS (insn); link; link = XEXP (link, 1))
1461 if (dead_or_set_p (XEXP (link, 0), x))
1466 rsp->nonzero_bits = GET_MODE_MASK (GET_MODE (x));
1467 rsp->sign_bit_copies = 1;
1472 /* If this is a complex assignment, see if we can convert it into a
1473 simple assignment. */
1474 set = expand_field_assignment (set);
1476 /* If this is a simple assignment, or we have a paradoxical SUBREG,
1477 set what we know about X. */
1479 if (SET_DEST (set) == x
1480 || (GET_CODE (SET_DEST (set)) == SUBREG
1481 && (GET_MODE_SIZE (GET_MODE (SET_DEST (set)))
1482 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (set)))))
1483 && SUBREG_REG (SET_DEST (set)) == x))
1485 rtx src = SET_SRC (set);
1487 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
1488 /* If X is narrower than a word and SRC is a non-negative
1489 constant that would appear negative in the mode of X,
1490 sign-extend it for use in reg_stat[].nonzero_bits because some
1491 machines (maybe most) will actually do the sign-extension
1492 and this is the conservative approach.
1494 ??? For 2.5, try to tighten up the MD files in this regard
1495 instead of this kludge. */
1497 if (GET_MODE_BITSIZE (GET_MODE (x)) < BITS_PER_WORD
1498 && CONST_INT_P (src)
1500 && 0 != (INTVAL (src)
1501 & ((HOST_WIDE_INT) 1
1502 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
1503 src = GEN_INT (INTVAL (src)
1504 | ((HOST_WIDE_INT) (-1)
1505 << GET_MODE_BITSIZE (GET_MODE (x))));
1508 /* Don't call nonzero_bits if it cannot change anything. */
1509 if (rsp->nonzero_bits != ~(unsigned HOST_WIDE_INT) 0)
1510 rsp->nonzero_bits |= nonzero_bits (src, nonzero_bits_mode);
1511 num = num_sign_bit_copies (SET_SRC (set), GET_MODE (x));
1512 if (rsp->sign_bit_copies == 0
1513 || rsp->sign_bit_copies > num)
1514 rsp->sign_bit_copies = num;
1518 rsp->nonzero_bits = GET_MODE_MASK (GET_MODE (x));
1519 rsp->sign_bit_copies = 1;
1524 /* See if INSN can be combined into I3. PRED and SUCC are optionally
1525 insns that were previously combined into I3 or that will be combined
1526 into the merger of INSN and I3.
1528 Return 0 if the combination is not allowed for any reason.
1530 If the combination is allowed, *PDEST will be set to the single
1531 destination of INSN and *PSRC to the single source, and this function
1535 can_combine_p (rtx insn, rtx i3, rtx pred ATTRIBUTE_UNUSED, rtx succ,
1536 rtx *pdest, rtx *psrc)
1545 int all_adjacent = (succ ? (next_active_insn (insn) == succ
1546 && next_active_insn (succ) == i3)
1547 : next_active_insn (insn) == i3);
1549 /* Can combine only if previous insn is a SET of a REG, a SUBREG or CC0.
1550 or a PARALLEL consisting of such a SET and CLOBBERs.
1552 If INSN has CLOBBER parallel parts, ignore them for our processing.
1553 By definition, these happen during the execution of the insn. When it
1554 is merged with another insn, all bets are off. If they are, in fact,
1555 needed and aren't also supplied in I3, they may be added by
1556 recog_for_combine. Otherwise, it won't match.
1558 We can also ignore a SET whose SET_DEST is mentioned in a REG_UNUSED
1561 Get the source and destination of INSN. If more than one, can't
1564 if (GET_CODE (PATTERN (insn)) == SET)
1565 set = PATTERN (insn);
1566 else if (GET_CODE (PATTERN (insn)) == PARALLEL
1567 && GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == SET)
1569 for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
1571 rtx elt = XVECEXP (PATTERN (insn), 0, i);
1573 switch (GET_CODE (elt))
1575 /* This is important to combine floating point insns
1576 for the SH4 port. */
1578 /* Combining an isolated USE doesn't make sense.
1579 We depend here on combinable_i3pat to reject them. */
1580 /* The code below this loop only verifies that the inputs of
1581 the SET in INSN do not change. We call reg_set_between_p
1582 to verify that the REG in the USE does not change between
1584 If the USE in INSN was for a pseudo register, the matching
1585 insn pattern will likely match any register; combining this
1586 with any other USE would only be safe if we knew that the
1587 used registers have identical values, or if there was
1588 something to tell them apart, e.g. different modes. For
1589 now, we forgo such complicated tests and simply disallow
1590 combining of USES of pseudo registers with any other USE. */
1591 if (REG_P (XEXP (elt, 0))
1592 && GET_CODE (PATTERN (i3)) == PARALLEL)
1594 rtx i3pat = PATTERN (i3);
1595 int i = XVECLEN (i3pat, 0) - 1;
1596 unsigned int regno = REGNO (XEXP (elt, 0));
1600 rtx i3elt = XVECEXP (i3pat, 0, i);
1602 if (GET_CODE (i3elt) == USE
1603 && REG_P (XEXP (i3elt, 0))
1604 && (REGNO (XEXP (i3elt, 0)) == regno
1605 ? reg_set_between_p (XEXP (elt, 0),
1606 PREV_INSN (insn), i3)
1607 : regno >= FIRST_PSEUDO_REGISTER))
1614 /* We can ignore CLOBBERs. */
1619 /* Ignore SETs whose result isn't used but not those that
1620 have side-effects. */
1621 if (find_reg_note (insn, REG_UNUSED, SET_DEST (elt))
1622 && insn_nothrow_p (insn)
1623 && !side_effects_p (elt))
1626 /* If we have already found a SET, this is a second one and
1627 so we cannot combine with this insn. */
1635 /* Anything else means we can't combine. */
1641 /* If SET_SRC is an ASM_OPERANDS we can't throw away these CLOBBERs,
1642 so don't do anything with it. */
1643 || GET_CODE (SET_SRC (set)) == ASM_OPERANDS)
1652 set = expand_field_assignment (set);
1653 src = SET_SRC (set), dest = SET_DEST (set);
1655 /* Don't eliminate a store in the stack pointer. */
1656 if (dest == stack_pointer_rtx
1657 /* Don't combine with an insn that sets a register to itself if it has
1658 a REG_EQUAL note. This may be part of a LIBCALL sequence. */
1659 || (rtx_equal_p (src, dest) && find_reg_note (insn, REG_EQUAL, NULL_RTX))
1660 /* Can't merge an ASM_OPERANDS. */
1661 || GET_CODE (src) == ASM_OPERANDS
1662 /* Can't merge a function call. */
1663 || GET_CODE (src) == CALL
1664 /* Don't eliminate a function call argument. */
1666 && (find_reg_fusage (i3, USE, dest)
1668 && REGNO (dest) < FIRST_PSEUDO_REGISTER
1669 && global_regs[REGNO (dest)])))
1670 /* Don't substitute into an incremented register. */
1671 || FIND_REG_INC_NOTE (i3, dest)
1672 || (succ && FIND_REG_INC_NOTE (succ, dest))
1673 /* Don't substitute into a non-local goto, this confuses CFG. */
1674 || (JUMP_P (i3) && find_reg_note (i3, REG_NON_LOCAL_GOTO, NULL_RTX))
1675 /* Make sure that DEST is not used after SUCC but before I3. */
1676 || (succ && ! all_adjacent
1677 && reg_used_between_p (dest, succ, i3))
1678 /* Make sure that the value that is to be substituted for the register
1679 does not use any registers whose values alter in between. However,
1680 If the insns are adjacent, a use can't cross a set even though we
1681 think it might (this can happen for a sequence of insns each setting
1682 the same destination; last_set of that register might point to
1683 a NOTE). If INSN has a REG_EQUIV note, the register is always
1684 equivalent to the memory so the substitution is valid even if there
1685 are intervening stores. Also, don't move a volatile asm or
1686 UNSPEC_VOLATILE across any other insns. */
1689 || ! find_reg_note (insn, REG_EQUIV, src))
1690 && use_crosses_set_p (src, DF_INSN_LUID (insn)))
1691 || (GET_CODE (src) == ASM_OPERANDS && MEM_VOLATILE_P (src))
1692 || GET_CODE (src) == UNSPEC_VOLATILE))
1693 /* Don't combine across a CALL_INSN, because that would possibly
1694 change whether the life span of some REGs crosses calls or not,
1695 and it is a pain to update that information.
1696 Exception: if source is a constant, moving it later can't hurt.
1697 Accept that as a special case. */
1698 || (DF_INSN_LUID (insn) < last_call_luid && ! CONSTANT_P (src)))
1701 /* DEST must either be a REG or CC0. */
1704 /* If register alignment is being enforced for multi-word items in all
1705 cases except for parameters, it is possible to have a register copy
1706 insn referencing a hard register that is not allowed to contain the
1707 mode being copied and which would not be valid as an operand of most
1708 insns. Eliminate this problem by not combining with such an insn.
1710 Also, on some machines we don't want to extend the life of a hard
1714 && ((REGNO (dest) < FIRST_PSEUDO_REGISTER
1715 && ! HARD_REGNO_MODE_OK (REGNO (dest), GET_MODE (dest)))
1716 /* Don't extend the life of a hard register unless it is
1717 user variable (if we have few registers) or it can't
1718 fit into the desired register (meaning something special
1720 Also avoid substituting a return register into I3, because
1721 reload can't handle a conflict with constraints of other
1723 || (REGNO (src) < FIRST_PSEUDO_REGISTER
1724 && ! HARD_REGNO_MODE_OK (REGNO (src), GET_MODE (src)))))
1727 else if (GET_CODE (dest) != CC0)
1731 if (GET_CODE (PATTERN (i3)) == PARALLEL)
1732 for (i = XVECLEN (PATTERN (i3), 0) - 1; i >= 0; i--)
1733 if (GET_CODE (XVECEXP (PATTERN (i3), 0, i)) == CLOBBER)
1735 /* Don't substitute for a register intended as a clobberable
1737 rtx reg = XEXP (XVECEXP (PATTERN (i3), 0, i), 0);
1738 if (rtx_equal_p (reg, dest))
1741 /* If the clobber represents an earlyclobber operand, we must not
1742 substitute an expression containing the clobbered register.
1743 As we do not analyze the constraint strings here, we have to
1744 make the conservative assumption. However, if the register is
1745 a fixed hard reg, the clobber cannot represent any operand;
1746 we leave it up to the machine description to either accept or
1747 reject use-and-clobber patterns. */
1749 || REGNO (reg) >= FIRST_PSEUDO_REGISTER
1750 || !fixed_regs[REGNO (reg)])
1751 if (reg_overlap_mentioned_p (reg, src))
1755 /* If INSN contains anything volatile, or is an `asm' (whether volatile
1756 or not), reject, unless nothing volatile comes between it and I3 */
1758 if (GET_CODE (src) == ASM_OPERANDS || volatile_refs_p (src))
1760 /* Make sure succ doesn't contain a volatile reference. */
1761 if (succ != 0 && volatile_refs_p (PATTERN (succ)))
1764 for (p = NEXT_INSN (insn); p != i3; p = NEXT_INSN (p))
1765 if (INSN_P (p) && p != succ && volatile_refs_p (PATTERN (p)))
1769 /* If INSN is an asm, and DEST is a hard register, reject, since it has
1770 to be an explicit register variable, and was chosen for a reason. */
1772 if (GET_CODE (src) == ASM_OPERANDS
1773 && REG_P (dest) && REGNO (dest) < FIRST_PSEUDO_REGISTER)
1776 /* If there are any volatile insns between INSN and I3, reject, because
1777 they might affect machine state. */
1779 for (p = NEXT_INSN (insn); p != i3; p = NEXT_INSN (p))
1780 if (INSN_P (p) && p != succ && volatile_insn_p (PATTERN (p)))
1783 /* If INSN contains an autoincrement or autodecrement, make sure that
1784 register is not used between there and I3, and not already used in
1785 I3 either. Neither must it be used in PRED or SUCC, if they exist.
1786 Also insist that I3 not be a jump; if it were one
1787 and the incremented register were spilled, we would lose. */
1790 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
1791 if (REG_NOTE_KIND (link) == REG_INC
1793 || reg_used_between_p (XEXP (link, 0), insn, i3)
1794 || (pred != NULL_RTX
1795 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (pred)))
1796 || (succ != NULL_RTX
1797 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (succ)))
1798 || reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i3))))
1803 /* Don't combine an insn that follows a CC0-setting insn.
1804 An insn that uses CC0 must not be separated from the one that sets it.
1805 We do, however, allow I2 to follow a CC0-setting insn if that insn
1806 is passed as I1; in that case it will be deleted also.
1807 We also allow combining in this case if all the insns are adjacent
1808 because that would leave the two CC0 insns adjacent as well.
1809 It would be more logical to test whether CC0 occurs inside I1 or I2,
1810 but that would be much slower, and this ought to be equivalent. */
1812 p = prev_nonnote_insn (insn);
1813 if (p && p != pred && NONJUMP_INSN_P (p) && sets_cc0_p (PATTERN (p))
1818 /* If we get here, we have passed all the tests and the combination is
1827 /* LOC is the location within I3 that contains its pattern or the component
1828 of a PARALLEL of the pattern. We validate that it is valid for combining.
1830 One problem is if I3 modifies its output, as opposed to replacing it
1831 entirely, we can't allow the output to contain I2DEST or I1DEST as doing
1832 so would produce an insn that is not equivalent to the original insns.
1836 (set (reg:DI 101) (reg:DI 100))
1837 (set (subreg:SI (reg:DI 101) 0) <foo>)
1839 This is NOT equivalent to:
1841 (parallel [(set (subreg:SI (reg:DI 100) 0) <foo>)
1842 (set (reg:DI 101) (reg:DI 100))])
1844 Not only does this modify 100 (in which case it might still be valid
1845 if 100 were dead in I2), it sets 101 to the ORIGINAL value of 100.
1847 We can also run into a problem if I2 sets a register that I1
1848 uses and I1 gets directly substituted into I3 (not via I2). In that
1849 case, we would be getting the wrong value of I2DEST into I3, so we
1850 must reject the combination. This case occurs when I2 and I1 both
1851 feed into I3, rather than when I1 feeds into I2, which feeds into I3.
1852 If I1_NOT_IN_SRC is nonzero, it means that finding I1 in the source
1853 of a SET must prevent combination from occurring.
1855 Before doing the above check, we first try to expand a field assignment
1856 into a set of logical operations.
1858 If PI3_DEST_KILLED is nonzero, it is a pointer to a location in which
1859 we place a register that is both set and used within I3. If more than one
1860 such register is detected, we fail.
1862 Return 1 if the combination is valid, zero otherwise. */
1865 combinable_i3pat (rtx i3, rtx *loc, rtx i2dest, rtx i1dest,
1866 int i1_not_in_src, rtx *pi3dest_killed)
1870 if (GET_CODE (x) == SET)
1873 rtx dest = SET_DEST (set);
1874 rtx src = SET_SRC (set);
1875 rtx inner_dest = dest;
1878 while (GET_CODE (inner_dest) == STRICT_LOW_PART
1879 || GET_CODE (inner_dest) == SUBREG
1880 || GET_CODE (inner_dest) == ZERO_EXTRACT)
1881 inner_dest = XEXP (inner_dest, 0);
1883 /* Check for the case where I3 modifies its output, as discussed
1884 above. We don't want to prevent pseudos from being combined
1885 into the address of a MEM, so only prevent the combination if
1886 i1 or i2 set the same MEM. */
1887 if ((inner_dest != dest &&
1888 (!MEM_P (inner_dest)
1889 || rtx_equal_p (i2dest, inner_dest)
1890 || (i1dest && rtx_equal_p (i1dest, inner_dest)))
1891 && (reg_overlap_mentioned_p (i2dest, inner_dest)
1892 || (i1dest && reg_overlap_mentioned_p (i1dest, inner_dest))))
1894 /* This is the same test done in can_combine_p except we can't test
1895 all_adjacent; we don't have to, since this instruction will stay
1896 in place, thus we are not considering increasing the lifetime of
1899 Also, if this insn sets a function argument, combining it with
1900 something that might need a spill could clobber a previous
1901 function argument; the all_adjacent test in can_combine_p also
1902 checks this; here, we do a more specific test for this case. */
1904 || (REG_P (inner_dest)
1905 && REGNO (inner_dest) < FIRST_PSEUDO_REGISTER
1906 && (! HARD_REGNO_MODE_OK (REGNO (inner_dest),
1907 GET_MODE (inner_dest))))
1908 || (i1_not_in_src && reg_overlap_mentioned_p (i1dest, src)))
1911 /* If DEST is used in I3, it is being killed in this insn, so
1912 record that for later. We have to consider paradoxical
1913 subregs here, since they kill the whole register, but we
1914 ignore partial subregs, STRICT_LOW_PART, etc.
1915 Never add REG_DEAD notes for the FRAME_POINTER_REGNUM or the
1916 STACK_POINTER_REGNUM, since these are always considered to be
1917 live. Similarly for ARG_POINTER_REGNUM if it is fixed. */
1919 if (GET_CODE (subdest) == SUBREG
1920 && (GET_MODE_SIZE (GET_MODE (subdest))
1921 >= GET_MODE_SIZE (GET_MODE (SUBREG_REG (subdest)))))
1922 subdest = SUBREG_REG (subdest);
1925 && reg_referenced_p (subdest, PATTERN (i3))
1926 && REGNO (subdest) != FRAME_POINTER_REGNUM
1927 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
1928 && REGNO (subdest) != HARD_FRAME_POINTER_REGNUM
1930 #if ARG_POINTER_REGNUM != FRAME_POINTER_REGNUM
1931 && (REGNO (subdest) != ARG_POINTER_REGNUM
1932 || ! fixed_regs [REGNO (subdest)])
1934 && REGNO (subdest) != STACK_POINTER_REGNUM)
1936 if (*pi3dest_killed)
1939 *pi3dest_killed = subdest;
1943 else if (GET_CODE (x) == PARALLEL)
1947 for (i = 0; i < XVECLEN (x, 0); i++)
1948 if (! combinable_i3pat (i3, &XVECEXP (x, 0, i), i2dest, i1dest,
1949 i1_not_in_src, pi3dest_killed))
1956 /* Return 1 if X is an arithmetic expression that contains a multiplication
1957 and division. We don't count multiplications by powers of two here. */
1960 contains_muldiv (rtx x)
1962 switch (GET_CODE (x))
1964 case MOD: case DIV: case UMOD: case UDIV:
1968 return ! (CONST_INT_P (XEXP (x, 1))
1969 && exact_log2 (INTVAL (XEXP (x, 1))) >= 0);
1972 return contains_muldiv (XEXP (x, 0))
1973 || contains_muldiv (XEXP (x, 1));
1976 return contains_muldiv (XEXP (x, 0));
1982 /* Determine whether INSN can be used in a combination. Return nonzero if
1983 not. This is used in try_combine to detect early some cases where we
1984 can't perform combinations. */
1987 cant_combine_insn_p (rtx insn)
1992 /* If this isn't really an insn, we can't do anything.
1993 This can occur when flow deletes an insn that it has merged into an
1994 auto-increment address. */
1995 if (! INSN_P (insn))
1998 /* Never combine loads and stores involving hard regs that are likely
1999 to be spilled. The register allocator can usually handle such
2000 reg-reg moves by tying. If we allow the combiner to make
2001 substitutions of likely-spilled regs, reload might die.
2002 As an exception, we allow combinations involving fixed regs; these are
2003 not available to the register allocator so there's no risk involved. */
2005 set = single_set (insn);
2008 src = SET_SRC (set);
2009 dest = SET_DEST (set);
2010 if (GET_CODE (src) == SUBREG)
2011 src = SUBREG_REG (src);
2012 if (GET_CODE (dest) == SUBREG)
2013 dest = SUBREG_REG (dest);
2014 if (REG_P (src) && REG_P (dest)
2015 && ((REGNO (src) < FIRST_PSEUDO_REGISTER
2016 && ! fixed_regs[REGNO (src)]
2017 && CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (REGNO (src))))
2018 || (REGNO (dest) < FIRST_PSEUDO_REGISTER
2019 && ! fixed_regs[REGNO (dest)]
2020 && CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (REGNO (dest))))))
2026 struct likely_spilled_retval_info
2028 unsigned regno, nregs;
2032 /* Called via note_stores by likely_spilled_retval_p. Remove from info->mask
2033 hard registers that are known to be written to / clobbered in full. */
2035 likely_spilled_retval_1 (rtx x, const_rtx set, void *data)
2037 struct likely_spilled_retval_info *const info =
2038 (struct likely_spilled_retval_info *) data;
2039 unsigned regno, nregs;
2042 if (!REG_P (XEXP (set, 0)))
2045 if (regno >= info->regno + info->nregs)
2047 nregs = hard_regno_nregs[regno][GET_MODE (x)];
2048 if (regno + nregs <= info->regno)
2050 new_mask = (2U << (nregs - 1)) - 1;
2051 if (regno < info->regno)
2052 new_mask >>= info->regno - regno;
2054 new_mask <<= regno - info->regno;
2055 info->mask &= ~new_mask;
2058 /* Return nonzero iff part of the return value is live during INSN, and
2059 it is likely spilled. This can happen when more than one insn is needed
2060 to copy the return value, e.g. when we consider to combine into the
2061 second copy insn for a complex value. */
2064 likely_spilled_retval_p (rtx insn)
2066 rtx use = BB_END (this_basic_block);
2068 unsigned regno, nregs;
2069 /* We assume here that no machine mode needs more than
2070 32 hard registers when the value overlaps with a register
2071 for which FUNCTION_VALUE_REGNO_P is true. */
2073 struct likely_spilled_retval_info info;
2075 if (!NONJUMP_INSN_P (use) || GET_CODE (PATTERN (use)) != USE || insn == use)
2077 reg = XEXP (PATTERN (use), 0);
2078 if (!REG_P (reg) || !FUNCTION_VALUE_REGNO_P (REGNO (reg)))
2080 regno = REGNO (reg);
2081 nregs = hard_regno_nregs[regno][GET_MODE (reg)];
2084 mask = (2U << (nregs - 1)) - 1;
2086 /* Disregard parts of the return value that are set later. */
2090 for (p = PREV_INSN (use); info.mask && p != insn; p = PREV_INSN (p))
2092 note_stores (PATTERN (p), likely_spilled_retval_1, &info);
2095 /* Check if any of the (probably) live return value registers is
2100 if ((mask & 1 << nregs)
2101 && CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (regno + nregs)))
2107 /* Adjust INSN after we made a change to its destination.
2109 Changing the destination can invalidate notes that say something about
2110 the results of the insn and a LOG_LINK pointing to the insn. */
2113 adjust_for_new_dest (rtx insn)
2115 /* For notes, be conservative and simply remove them. */
2116 remove_reg_equal_equiv_notes (insn);
2118 /* The new insn will have a destination that was previously the destination
2119 of an insn just above it. Call distribute_links to make a LOG_LINK from
2120 the next use of that destination. */
2121 distribute_links (gen_rtx_INSN_LIST (VOIDmode, insn, NULL_RTX));
2123 df_insn_rescan (insn);
2126 /* Return TRUE if combine can reuse reg X in mode MODE.
2127 ADDED_SETS is nonzero if the original set is still required. */
2129 can_change_dest_mode (rtx x, int added_sets, enum machine_mode mode)
2137 /* Allow hard registers if the new mode is legal, and occupies no more
2138 registers than the old mode. */
2139 if (regno < FIRST_PSEUDO_REGISTER)
2140 return (HARD_REGNO_MODE_OK (regno, mode)
2141 && (hard_regno_nregs[regno][GET_MODE (x)]
2142 >= hard_regno_nregs[regno][mode]));
2144 /* Or a pseudo that is only used once. */
2145 return (REG_N_SETS (regno) == 1 && !added_sets
2146 && !REG_USERVAR_P (x));
2150 /* Check whether X, the destination of a set, refers to part of
2151 the register specified by REG. */
2154 reg_subword_p (rtx x, rtx reg)
2156 /* Check that reg is an integer mode register. */
2157 if (!REG_P (reg) || GET_MODE_CLASS (GET_MODE (reg)) != MODE_INT)
2160 if (GET_CODE (x) == STRICT_LOW_PART
2161 || GET_CODE (x) == ZERO_EXTRACT)
2164 return GET_CODE (x) == SUBREG
2165 && SUBREG_REG (x) == reg
2166 && GET_MODE_CLASS (GET_MODE (x)) == MODE_INT;
2170 /* Replace auto-increment addressing modes with explicit operations to
2171 access the same addresses without modifying the corresponding
2172 registers. If AFTER holds, SRC is meant to be reused after the
2173 side effect, otherwise it is to be reused before that. */
2176 cleanup_auto_inc_dec (rtx src, bool after, enum machine_mode mem_mode)
2179 const RTX_CODE code = GET_CODE (x);
2195 /* SCRATCH must be shared because they represent distinct values. */
2198 if (REG_P (XEXP (x, 0)) && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER)
2203 if (shared_const_p (x))
2208 mem_mode = GET_MODE (x);
2215 gcc_assert (mem_mode != VOIDmode && mem_mode != BLKmode);
2216 if (after == (code == PRE_INC || code == PRE_DEC))
2217 x = cleanup_auto_inc_dec (XEXP (x, 0), after, mem_mode);
2219 x = gen_rtx_PLUS (GET_MODE (x),
2220 cleanup_auto_inc_dec (XEXP (x, 0), after, mem_mode),
2221 GEN_INT ((code == PRE_INC || code == POST_INC)
2222 ? GET_MODE_SIZE (mem_mode)
2223 : -GET_MODE_SIZE (mem_mode)));
2228 if (after == (code == PRE_MODIFY))
2232 return cleanup_auto_inc_dec (x, after, mem_mode);
2238 /* Copy the various flags, fields, and other information. We assume
2239 that all fields need copying, and then clear the fields that should
2240 not be copied. That is the sensible default behavior, and forces
2241 us to explicitly document why we are *not* copying a flag. */
2242 x = shallow_copy_rtx (x);
2244 /* We do not copy the USED flag, which is used as a mark bit during
2245 walks over the RTL. */
2246 RTX_FLAG (x, used) = 0;
2248 /* We do not copy FRAME_RELATED for INSNs. */
2250 RTX_FLAG (x, frame_related) = 0;
2252 fmt = GET_RTX_FORMAT (code);
2253 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
2255 XEXP (x, i) = cleanup_auto_inc_dec (XEXP (x, i), after, mem_mode);
2256 else if (fmt[i] == 'E' || fmt[i] == 'V')
2259 XVEC (x, i) = rtvec_alloc (XVECLEN (x, i));
2260 for (j = 0; j < XVECLEN (x, i); j++)
2262 = cleanup_auto_inc_dec (XVECEXP (src, i, j), after, mem_mode);
2268 /* Auxiliary data structure for propagate_for_debug_stmt. */
2270 struct rtx_subst_pair
2277 /* DATA points to an rtx_subst_pair. Return the value that should be
2281 propagate_for_debug_subst (rtx from ATTRIBUTE_UNUSED, void *data)
2283 struct rtx_subst_pair *pair = (struct rtx_subst_pair *)data;
2285 if (!pair->adjusted)
2287 pair->adjusted = true;
2288 pair->to = cleanup_auto_inc_dec (pair->to, pair->after, VOIDmode);
2291 return copy_rtx (pair->to);
2295 /* Replace occurrences of DEST with SRC in DEBUG_INSNs between INSN
2296 and LAST. If MOVE holds, debug insns must also be moved past
2300 propagate_for_debug (rtx insn, rtx last, rtx dest, rtx src, bool move)
2302 rtx next, move_pos = move ? last : NULL_RTX, loc;
2305 struct rtx_subst_pair p;
2311 next = NEXT_INSN (insn);
2312 while (next != last)
2315 next = NEXT_INSN (insn);
2316 if (DEBUG_INSN_P (insn))
2319 loc = simplify_replace_fn_rtx (INSN_VAR_LOCATION_LOC (insn),
2320 dest, propagate_for_debug_subst, &p);
2322 loc = simplify_replace_rtx (INSN_VAR_LOCATION_LOC (insn), dest, src);
2324 if (loc == INSN_VAR_LOCATION_LOC (insn))
2326 INSN_VAR_LOCATION_LOC (insn) = loc;
2330 PREV_INSN (insn) = NEXT_INSN (insn) = NULL_RTX;
2331 move_pos = emit_debug_insn_after (insn, move_pos);
2334 df_insn_rescan (insn);
2339 /* Delete the unconditional jump INSN and adjust the CFG correspondingly.
2340 Note that the INSN should be deleted *after* removing dead edges, so
2341 that the kept edge is the fallthrough edge for a (set (pc) (pc))
2342 but not for a (set (pc) (label_ref FOO)). */
2345 update_cfg_for_uncondjump (rtx insn)
2347 basic_block bb = BLOCK_FOR_INSN (insn);
2348 bool at_end = (BB_END (bb) == insn);
2351 purge_dead_edges (bb);
2354 if (at_end && EDGE_COUNT (bb->succs) == 1)
2355 single_succ_edge (bb)->flags |= EDGE_FALLTHRU;
2359 /* Try to combine the insns I1 and I2 into I3.
2360 Here I1 and I2 appear earlier than I3.
2361 I1 can be zero; then we combine just I2 into I3.
2363 If we are combining three insns and the resulting insn is not recognized,
2364 try splitting it into two insns. If that happens, I2 and I3 are retained
2365 and I1 is pseudo-deleted by turning it into a NOTE. Otherwise, I1 and I2
2368 Return 0 if the combination does not work. Then nothing is changed.
2369 If we did the combination, return the insn at which combine should
2372 Set NEW_DIRECT_JUMP_P to a nonzero value if try_combine creates a
2373 new direct jump instruction. */
2376 try_combine (rtx i3, rtx i2, rtx i1, int *new_direct_jump_p)
2378 /* New patterns for I3 and I2, respectively. */
2379 rtx newpat, newi2pat = 0;
2380 rtvec newpat_vec_with_clobbers = 0;
2381 int substed_i2 = 0, substed_i1 = 0;
2382 /* Indicates need to preserve SET in I1 or I2 in I3 if it is not dead. */
2383 int added_sets_1, added_sets_2;
2384 /* Total number of SETs to put into I3. */
2386 /* Nonzero if I2's body now appears in I3. */
2388 /* INSN_CODEs for new I3, new I2, and user of condition code. */
2389 int insn_code_number, i2_code_number = 0, other_code_number = 0;
2390 /* Contains I3 if the destination of I3 is used in its source, which means
2391 that the old life of I3 is being killed. If that usage is placed into
2392 I2 and not in I3, a REG_DEAD note must be made. */
2393 rtx i3dest_killed = 0;
2394 /* SET_DEST and SET_SRC of I2 and I1. */
2395 rtx i2dest = 0, i2src = 0, i1dest = 0, i1src = 0;
2396 /* Set if I2DEST was reused as a scratch register. */
2397 bool i2scratch = false;
2398 /* PATTERN (I1) and PATTERN (I2), or a copy of it in certain cases. */
2399 rtx i1pat = 0, i2pat = 0;
2400 /* Indicates if I2DEST or I1DEST is in I2SRC or I1_SRC. */
2401 int i2dest_in_i2src = 0, i1dest_in_i1src = 0, i2dest_in_i1src = 0;
2402 int i2dest_killed = 0, i1dest_killed = 0;
2403 int i1_feeds_i3 = 0;
2404 /* Notes that must be added to REG_NOTES in I3 and I2. */
2405 rtx new_i3_notes, new_i2_notes;
2406 /* Notes that we substituted I3 into I2 instead of the normal case. */
2407 int i3_subst_into_i2 = 0;
2408 /* Notes that I1, I2 or I3 is a MULT operation. */
2411 int changed_i3_dest = 0;
2417 rtx new_other_notes;
2420 /* Exit early if one of the insns involved can't be used for
2422 if (cant_combine_insn_p (i3)
2423 || cant_combine_insn_p (i2)
2424 || (i1 && cant_combine_insn_p (i1))
2425 || likely_spilled_retval_p (i3))
2429 undobuf.other_insn = 0;
2431 /* Reset the hard register usage information. */
2432 CLEAR_HARD_REG_SET (newpat_used_regs);
2434 if (dump_file && (dump_flags & TDF_DETAILS))
2437 fprintf (dump_file, "\nTrying %d, %d -> %d:\n",
2438 INSN_UID (i1), INSN_UID (i2), INSN_UID (i3));
2440 fprintf (dump_file, "\nTrying %d -> %d:\n",
2441 INSN_UID (i2), INSN_UID (i3));
2444 /* If I1 and I2 both feed I3, they can be in any order. To simplify the
2445 code below, set I1 to be the earlier of the two insns. */
2446 if (i1 && DF_INSN_LUID (i1) > DF_INSN_LUID (i2))
2447 temp = i1, i1 = i2, i2 = temp;
2449 added_links_insn = 0;
2451 /* First check for one important special-case that the code below will
2452 not handle. Namely, the case where I1 is zero, I2 is a PARALLEL
2453 and I3 is a SET whose SET_SRC is a SET_DEST in I2. In that case,
2454 we may be able to replace that destination with the destination of I3.
2455 This occurs in the common code where we compute both a quotient and
2456 remainder into a structure, in which case we want to do the computation
2457 directly into the structure to avoid register-register copies.
2459 Note that this case handles both multiple sets in I2 and also
2460 cases where I2 has a number of CLOBBER or PARALLELs.
2462 We make very conservative checks below and only try to handle the
2463 most common cases of this. For example, we only handle the case
2464 where I2 and I3 are adjacent to avoid making difficult register
2467 if (i1 == 0 && NONJUMP_INSN_P (i3) && GET_CODE (PATTERN (i3)) == SET
2468 && REG_P (SET_SRC (PATTERN (i3)))
2469 && REGNO (SET_SRC (PATTERN (i3))) >= FIRST_PSEUDO_REGISTER
2470 && find_reg_note (i3, REG_DEAD, SET_SRC (PATTERN (i3)))
2471 && GET_CODE (PATTERN (i2)) == PARALLEL
2472 && ! side_effects_p (SET_DEST (PATTERN (i3)))
2473 /* If the dest of I3 is a ZERO_EXTRACT or STRICT_LOW_PART, the code
2474 below would need to check what is inside (and reg_overlap_mentioned_p
2475 doesn't support those codes anyway). Don't allow those destinations;
2476 the resulting insn isn't likely to be recognized anyway. */
2477 && GET_CODE (SET_DEST (PATTERN (i3))) != ZERO_EXTRACT
2478 && GET_CODE (SET_DEST (PATTERN (i3))) != STRICT_LOW_PART
2479 && ! reg_overlap_mentioned_p (SET_SRC (PATTERN (i3)),
2480 SET_DEST (PATTERN (i3)))
2481 && next_active_insn (i2) == i3)
2483 rtx p2 = PATTERN (i2);
2485 /* Make sure that the destination of I3,
2486 which we are going to substitute into one output of I2,
2487 is not used within another output of I2. We must avoid making this:
2488 (parallel [(set (mem (reg 69)) ...)
2489 (set (reg 69) ...)])
2490 which is not well-defined as to order of actions.
2491 (Besides, reload can't handle output reloads for this.)
2493 The problem can also happen if the dest of I3 is a memory ref,
2494 if another dest in I2 is an indirect memory ref. */
2495 for (i = 0; i < XVECLEN (p2, 0); i++)
2496 if ((GET_CODE (XVECEXP (p2, 0, i)) == SET
2497 || GET_CODE (XVECEXP (p2, 0, i)) == CLOBBER)
2498 && reg_overlap_mentioned_p (SET_DEST (PATTERN (i3)),
2499 SET_DEST (XVECEXP (p2, 0, i))))
2502 if (i == XVECLEN (p2, 0))
2503 for (i = 0; i < XVECLEN (p2, 0); i++)
2504 if ((GET_CODE (XVECEXP (p2, 0, i)) == SET
2505 || GET_CODE (XVECEXP (p2, 0, i)) == CLOBBER)
2506 && SET_DEST (XVECEXP (p2, 0, i)) == SET_SRC (PATTERN (i3)))
2511 subst_low_luid = DF_INSN_LUID (i2);
2513 added_sets_2 = added_sets_1 = 0;
2514 i2src = SET_DEST (PATTERN (i3));
2515 i2dest = SET_SRC (PATTERN (i3));
2516 i2dest_killed = dead_or_set_p (i2, i2dest);
2518 /* Replace the dest in I2 with our dest and make the resulting
2519 insn the new pattern for I3. Then skip to where we
2520 validate the pattern. Everything was set up above. */
2521 SUBST (SET_DEST (XVECEXP (p2, 0, i)),
2522 SET_DEST (PATTERN (i3)));
2525 i3_subst_into_i2 = 1;
2526 goto validate_replacement;
2530 /* If I2 is setting a pseudo to a constant and I3 is setting some
2531 sub-part of it to another constant, merge them by making a new
2534 && (temp = single_set (i2)) != 0
2535 && (CONST_INT_P (SET_SRC (temp))
2536 || GET_CODE (SET_SRC (temp)) == CONST_DOUBLE)
2537 && GET_CODE (PATTERN (i3)) == SET
2538 && (CONST_INT_P (SET_SRC (PATTERN (i3)))
2539 || GET_CODE (SET_SRC (PATTERN (i3))) == CONST_DOUBLE)
2540 && reg_subword_p (SET_DEST (PATTERN (i3)), SET_DEST (temp)))
2542 rtx dest = SET_DEST (PATTERN (i3));
2546 if (GET_CODE (dest) == ZERO_EXTRACT)
2548 if (CONST_INT_P (XEXP (dest, 1))
2549 && CONST_INT_P (XEXP (dest, 2)))
2551 width = INTVAL (XEXP (dest, 1));
2552 offset = INTVAL (XEXP (dest, 2));
2553 dest = XEXP (dest, 0);
2554 if (BITS_BIG_ENDIAN)
2555 offset = GET_MODE_BITSIZE (GET_MODE (dest)) - width - offset;
2560 if (GET_CODE (dest) == STRICT_LOW_PART)
2561 dest = XEXP (dest, 0);
2562 width = GET_MODE_BITSIZE (GET_MODE (dest));
2568 /* If this is the low part, we're done. */
2569 if (subreg_lowpart_p (dest))
2571 /* Handle the case where inner is twice the size of outer. */
2572 else if (GET_MODE_BITSIZE (GET_MODE (SET_DEST (temp)))
2573 == 2 * GET_MODE_BITSIZE (GET_MODE (dest)))
2574 offset += GET_MODE_BITSIZE (GET_MODE (dest));
2575 /* Otherwise give up for now. */
2581 && (GET_MODE_BITSIZE (GET_MODE (SET_DEST (temp)))
2582 <= HOST_BITS_PER_WIDE_INT * 2))
2584 HOST_WIDE_INT mhi, ohi, ihi;
2585 HOST_WIDE_INT mlo, olo, ilo;
2586 rtx inner = SET_SRC (PATTERN (i3));
2587 rtx outer = SET_SRC (temp);
2589 if (CONST_INT_P (outer))
2591 olo = INTVAL (outer);
2592 ohi = olo < 0 ? -1 : 0;
2596 olo = CONST_DOUBLE_LOW (outer);
2597 ohi = CONST_DOUBLE_HIGH (outer);
2600 if (CONST_INT_P (inner))
2602 ilo = INTVAL (inner);
2603 ihi = ilo < 0 ? -1 : 0;
2607 ilo = CONST_DOUBLE_LOW (inner);
2608 ihi = CONST_DOUBLE_HIGH (inner);
2611 if (width < HOST_BITS_PER_WIDE_INT)
2613 mlo = ((unsigned HOST_WIDE_INT) 1 << width) - 1;
2616 else if (width < HOST_BITS_PER_WIDE_INT * 2)
2618 mhi = ((unsigned HOST_WIDE_INT) 1
2619 << (width - HOST_BITS_PER_WIDE_INT)) - 1;
2631 if (offset >= HOST_BITS_PER_WIDE_INT)
2633 mhi = mlo << (offset - HOST_BITS_PER_WIDE_INT);
2635 ihi = ilo << (offset - HOST_BITS_PER_WIDE_INT);
2638 else if (offset > 0)
2640 mhi = (mhi << offset) | ((unsigned HOST_WIDE_INT) mlo
2641 >> (HOST_BITS_PER_WIDE_INT - offset));
2642 mlo = mlo << offset;
2643 ihi = (ihi << offset) | ((unsigned HOST_WIDE_INT) ilo
2644 >> (HOST_BITS_PER_WIDE_INT - offset));
2645 ilo = ilo << offset;
2648 olo = (olo & ~mlo) | ilo;
2649 ohi = (ohi & ~mhi) | ihi;
2653 subst_low_luid = DF_INSN_LUID (i2);
2654 added_sets_2 = added_sets_1 = 0;
2655 i2dest = SET_DEST (temp);
2656 i2dest_killed = dead_or_set_p (i2, i2dest);
2658 SUBST (SET_SRC (temp),
2659 immed_double_const (olo, ohi, GET_MODE (SET_DEST (temp))));
2661 newpat = PATTERN (i2);
2662 goto validate_replacement;
2667 /* If we have no I1 and I2 looks like:
2668 (parallel [(set (reg:CC X) (compare:CC OP (const_int 0)))
2670 make up a dummy I1 that is
2673 (set (reg:CC X) (compare:CC Y (const_int 0)))
2675 (We can ignore any trailing CLOBBERs.)
2677 This undoes a previous combination and allows us to match a branch-and-
2680 if (i1 == 0 && GET_CODE (PATTERN (i2)) == PARALLEL
2681 && XVECLEN (PATTERN (i2), 0) >= 2
2682 && GET_CODE (XVECEXP (PATTERN (i2), 0, 0)) == SET
2683 && (GET_MODE_CLASS (GET_MODE (SET_DEST (XVECEXP (PATTERN (i2), 0, 0))))
2685 && GET_CODE (SET_SRC (XVECEXP (PATTERN (i2), 0, 0))) == COMPARE
2686 && XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 1) == const0_rtx
2687 && GET_CODE (XVECEXP (PATTERN (i2), 0, 1)) == SET
2688 && REG_P (SET_DEST (XVECEXP (PATTERN (i2), 0, 1)))
2689 && rtx_equal_p (XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 0),
2690 SET_SRC (XVECEXP (PATTERN (i2), 0, 1))))
2692 for (i = XVECLEN (PATTERN (i2), 0) - 1; i >= 2; i--)
2693 if (GET_CODE (XVECEXP (PATTERN (i2), 0, i)) != CLOBBER)
2698 /* We make I1 with the same INSN_UID as I2. This gives it
2699 the same DF_INSN_LUID for value tracking. Our fake I1 will
2700 never appear in the insn stream so giving it the same INSN_UID
2701 as I2 will not cause a problem. */
2703 i1 = gen_rtx_INSN (VOIDmode, INSN_UID (i2), NULL_RTX, i2,
2704 BLOCK_FOR_INSN (i2), INSN_LOCATOR (i2),
2705 XVECEXP (PATTERN (i2), 0, 1), -1, NULL_RTX);
2707 SUBST (PATTERN (i2), XVECEXP (PATTERN (i2), 0, 0));
2708 SUBST (XEXP (SET_SRC (PATTERN (i2)), 0),
2709 SET_DEST (PATTERN (i1)));
2714 /* Verify that I2 and I1 are valid for combining. */
2715 if (! can_combine_p (i2, i3, i1, NULL_RTX, &i2dest, &i2src)
2716 || (i1 && ! can_combine_p (i1, i3, NULL_RTX, i2, &i1dest, &i1src)))
2722 /* Record whether I2DEST is used in I2SRC and similarly for the other
2723 cases. Knowing this will help in register status updating below. */
2724 i2dest_in_i2src = reg_overlap_mentioned_p (i2dest, i2src);
2725 i1dest_in_i1src = i1 && reg_overlap_mentioned_p (i1dest, i1src);
2726 i2dest_in_i1src = i1 && reg_overlap_mentioned_p (i2dest, i1src);
2727 i2dest_killed = dead_or_set_p (i2, i2dest);
2728 i1dest_killed = i1 && dead_or_set_p (i1, i1dest);
2730 /* See if I1 directly feeds into I3. It does if I1DEST is not used
2732 i1_feeds_i3 = i1 && ! reg_overlap_mentioned_p (i1dest, i2src);
2734 /* Ensure that I3's pattern can be the destination of combines. */
2735 if (! combinable_i3pat (i3, &PATTERN (i3), i2dest, i1dest,
2736 i1 && i2dest_in_i1src && i1_feeds_i3,
2743 /* See if any of the insns is a MULT operation. Unless one is, we will
2744 reject a combination that is, since it must be slower. Be conservative
2746 if (GET_CODE (i2src) == MULT
2747 || (i1 != 0 && GET_CODE (i1src) == MULT)
2748 || (GET_CODE (PATTERN (i3)) == SET
2749 && GET_CODE (SET_SRC (PATTERN (i3))) == MULT))
2752 /* If I3 has an inc, then give up if I1 or I2 uses the reg that is inc'd.
2753 We used to do this EXCEPT in one case: I3 has a post-inc in an
2754 output operand. However, that exception can give rise to insns like
2756 which is a famous insn on the PDP-11 where the value of r3 used as the
2757 source was model-dependent. Avoid this sort of thing. */
2760 if (!(GET_CODE (PATTERN (i3)) == SET
2761 && REG_P (SET_SRC (PATTERN (i3)))
2762 && MEM_P (SET_DEST (PATTERN (i3)))
2763 && (GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_INC
2764 || GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_DEC)))
2765 /* It's not the exception. */
2768 for (link = REG_NOTES (i3); link; link = XEXP (link, 1))
2769 if (REG_NOTE_KIND (link) == REG_INC
2770 && (reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i2))
2772 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i1)))))
2779 /* See if the SETs in I1 or I2 need to be kept around in the merged
2780 instruction: whenever the value set there is still needed past I3.
2781 For the SETs in I2, this is easy: we see if I2DEST dies or is set in I3.
2783 For the SET in I1, we have two cases: If I1 and I2 independently
2784 feed into I3, the set in I1 needs to be kept around if I1DEST dies
2785 or is set in I3. Otherwise (if I1 feeds I2 which feeds I3), the set
2786 in I1 needs to be kept around unless I1DEST dies or is set in either
2787 I2 or I3. We can distinguish these cases by seeing if I2SRC mentions
2788 I1DEST. If so, we know I1 feeds into I2. */
2790 added_sets_2 = ! dead_or_set_p (i3, i2dest);
2793 = i1 && ! (i1_feeds_i3 ? dead_or_set_p (i3, i1dest)
2794 : (dead_or_set_p (i3, i1dest) || dead_or_set_p (i2, i1dest)));
2796 /* If the set in I2 needs to be kept around, we must make a copy of
2797 PATTERN (I2), so that when we substitute I1SRC for I1DEST in
2798 PATTERN (I2), we are only substituting for the original I1DEST, not into
2799 an already-substituted copy. This also prevents making self-referential
2800 rtx. If I2 is a PARALLEL, we just need the piece that assigns I2SRC to
2805 if (GET_CODE (PATTERN (i2)) == PARALLEL)
2806 i2pat = gen_rtx_SET (VOIDmode, i2dest, copy_rtx (i2src));
2808 i2pat = copy_rtx (PATTERN (i2));
2813 if (GET_CODE (PATTERN (i1)) == PARALLEL)
2814 i1pat = gen_rtx_SET (VOIDmode, i1dest, copy_rtx (i1src));
2816 i1pat = copy_rtx (PATTERN (i1));
2821 /* Substitute in the latest insn for the regs set by the earlier ones. */
2823 maxreg = max_reg_num ();
2828 /* Many machines that don't use CC0 have insns that can both perform an
2829 arithmetic operation and set the condition code. These operations will
2830 be represented as a PARALLEL with the first element of the vector
2831 being a COMPARE of an arithmetic operation with the constant zero.
2832 The second element of the vector will set some pseudo to the result
2833 of the same arithmetic operation. If we simplify the COMPARE, we won't
2834 match such a pattern and so will generate an extra insn. Here we test
2835 for this case, where both the comparison and the operation result are
2836 needed, and make the PARALLEL by just replacing I2DEST in I3SRC with
2837 I2SRC. Later we will make the PARALLEL that contains I2. */
2839 if (i1 == 0 && added_sets_2 && GET_CODE (PATTERN (i3)) == SET
2840 && GET_CODE (SET_SRC (PATTERN (i3))) == COMPARE
2841 && XEXP (SET_SRC (PATTERN (i3)), 1) == const0_rtx
2842 && rtx_equal_p (XEXP (SET_SRC (PATTERN (i3)), 0), i2dest))
2844 #ifdef SELECT_CC_MODE
2846 enum machine_mode compare_mode;
2849 newpat = PATTERN (i3);
2850 SUBST (XEXP (SET_SRC (newpat), 0), i2src);
2854 #ifdef SELECT_CC_MODE
2855 /* See if a COMPARE with the operand we substituted in should be done
2856 with the mode that is currently being used. If not, do the same
2857 processing we do in `subst' for a SET; namely, if the destination
2858 is used only once, try to replace it with a register of the proper
2859 mode and also replace the COMPARE. */
2860 if (undobuf.other_insn == 0
2861 && (cc_use = find_single_use (SET_DEST (newpat), i3,
2862 &undobuf.other_insn))
2863 && ((compare_mode = SELECT_CC_MODE (GET_CODE (*cc_use),
2865 != GET_MODE (SET_DEST (newpat))))
2867 if (can_change_dest_mode(SET_DEST (newpat), added_sets_2,
2870 unsigned int regno = REGNO (SET_DEST (newpat));
2873 if (regno < FIRST_PSEUDO_REGISTER)
2874 new_dest = gen_rtx_REG (compare_mode, regno);
2877 SUBST_MODE (regno_reg_rtx[regno], compare_mode);
2878 new_dest = regno_reg_rtx[regno];
2881 SUBST (SET_DEST (newpat), new_dest);
2882 SUBST (XEXP (*cc_use, 0), new_dest);
2883 SUBST (SET_SRC (newpat),
2884 gen_rtx_COMPARE (compare_mode, i2src, const0_rtx));
2887 undobuf.other_insn = 0;
2894 /* It is possible that the source of I2 or I1 may be performing
2895 an unneeded operation, such as a ZERO_EXTEND of something
2896 that is known to have the high part zero. Handle that case
2897 by letting subst look at the innermost one of them.
2899 Another way to do this would be to have a function that tries
2900 to simplify a single insn instead of merging two or more
2901 insns. We don't do this because of the potential of infinite
2902 loops and because of the potential extra memory required.
2903 However, doing it the way we are is a bit of a kludge and
2904 doesn't catch all cases.
2906 But only do this if -fexpensive-optimizations since it slows
2907 things down and doesn't usually win.
2909 This is not done in the COMPARE case above because the
2910 unmodified I2PAT is used in the PARALLEL and so a pattern
2911 with a modified I2SRC would not match. */
2913 if (flag_expensive_optimizations)
2915 /* Pass pc_rtx so no substitutions are done, just
2919 subst_low_luid = DF_INSN_LUID (i1);
2920 i1src = subst (i1src, pc_rtx, pc_rtx, 0, 0);
2924 subst_low_luid = DF_INSN_LUID (i2);
2925 i2src = subst (i2src, pc_rtx, pc_rtx, 0, 0);
2929 n_occurrences = 0; /* `subst' counts here */
2931 /* If I1 feeds into I2 (not into I3) and I1DEST is in I1SRC, we
2932 need to make a unique copy of I2SRC each time we substitute it
2933 to avoid self-referential rtl. */
2935 subst_low_luid = DF_INSN_LUID (i2);
2936 newpat = subst (PATTERN (i3), i2dest, i2src, 0,
2937 ! i1_feeds_i3 && i1dest_in_i1src);
2940 /* Record whether i2's body now appears within i3's body. */
2941 i2_is_used = n_occurrences;
2944 /* If we already got a failure, don't try to do more. Otherwise,
2945 try to substitute in I1 if we have it. */
2947 if (i1 && GET_CODE (newpat) != CLOBBER)
2949 /* Check that an autoincrement side-effect on I1 has not been lost.
2950 This happens if I1DEST is mentioned in I2 and dies there, and
2951 has disappeared from the new pattern. */
2952 if ((FIND_REG_INC_NOTE (i1, NULL_RTX) != 0
2954 && dead_or_set_p (i2, i1dest)
2955 && !reg_overlap_mentioned_p (i1dest, newpat))
2956 /* Before we can do this substitution, we must redo the test done
2957 above (see detailed comments there) that ensures that I1DEST
2958 isn't mentioned in any SETs in NEWPAT that are field assignments. */
2959 || !combinable_i3pat (NULL_RTX, &newpat, i1dest, NULL_RTX, 0, 0))
2966 subst_low_luid = DF_INSN_LUID (i1);
2967 newpat = subst (newpat, i1dest, i1src, 0, 0);
2971 /* Fail if an autoincrement side-effect has been duplicated. Be careful
2972 to count all the ways that I2SRC and I1SRC can be used. */
2973 if ((FIND_REG_INC_NOTE (i2, NULL_RTX) != 0
2974 && i2_is_used + added_sets_2 > 1)
2975 || (i1 != 0 && FIND_REG_INC_NOTE (i1, NULL_RTX) != 0
2976 && (n_occurrences + added_sets_1 + (added_sets_2 && ! i1_feeds_i3)
2978 /* Fail if we tried to make a new register. */
2979 || max_reg_num () != maxreg
2980 /* Fail if we couldn't do something and have a CLOBBER. */
2981 || GET_CODE (newpat) == CLOBBER
2982 /* Fail if this new pattern is a MULT and we didn't have one before
2983 at the outer level. */
2984 || (GET_CODE (newpat) == SET && GET_CODE (SET_SRC (newpat)) == MULT
2991 /* If the actions of the earlier insns must be kept
2992 in addition to substituting them into the latest one,
2993 we must make a new PARALLEL for the latest insn
2994 to hold additional the SETs. */
2996 if (added_sets_1 || added_sets_2)
3000 if (GET_CODE (newpat) == PARALLEL)
3002 rtvec old = XVEC (newpat, 0);
3003 total_sets = XVECLEN (newpat, 0) + added_sets_1 + added_sets_2;
3004 newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (total_sets));
3005 memcpy (XVEC (newpat, 0)->elem, &old->elem[0],
3006 sizeof (old->elem[0]) * old->num_elem);
3011 total_sets = 1 + added_sets_1 + added_sets_2;
3012 newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (total_sets));
3013 XVECEXP (newpat, 0, 0) = old;
3017 XVECEXP (newpat, 0, --total_sets) = i1pat;
3021 /* If there is no I1, use I2's body as is. We used to also not do
3022 the subst call below if I2 was substituted into I3,
3023 but that could lose a simplification. */
3025 XVECEXP (newpat, 0, --total_sets) = i2pat;
3027 /* See comment where i2pat is assigned. */
3028 XVECEXP (newpat, 0, --total_sets)
3029 = subst (i2pat, i1dest, i1src, 0, 0);
3033 /* We come here when we are replacing a destination in I2 with the
3034 destination of I3. */
3035 validate_replacement:
3037 /* Note which hard regs this insn has as inputs. */
3038 mark_used_regs_combine (newpat);
3040 /* If recog_for_combine fails, it strips existing clobbers. If we'll
3041 consider splitting this pattern, we might need these clobbers. */
3042 if (i1 && GET_CODE (newpat) == PARALLEL
3043 && GET_CODE (XVECEXP (newpat, 0, XVECLEN (newpat, 0) - 1)) == CLOBBER)
3045 int len = XVECLEN (newpat, 0);
3047 newpat_vec_with_clobbers = rtvec_alloc (len);
3048 for (i = 0; i < len; i++)
3049 RTVEC_ELT (newpat_vec_with_clobbers, i) = XVECEXP (newpat, 0, i);
3052 /* Is the result of combination a valid instruction? */
3053 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
3055 /* If the result isn't valid, see if it is a PARALLEL of two SETs where
3056 the second SET's destination is a register that is unused and isn't
3057 marked as an instruction that might trap in an EH region. In that case,
3058 we just need the first SET. This can occur when simplifying a divmod
3059 insn. We *must* test for this case here because the code below that
3060 splits two independent SETs doesn't handle this case correctly when it
3061 updates the register status.
3063 It's pointless doing this if we originally had two sets, one from
3064 i3, and one from i2. Combining then splitting the parallel results
3065 in the original i2 again plus an invalid insn (which we delete).
3066 The net effect is only to move instructions around, which makes
3067 debug info less accurate.
3069 Also check the case where the first SET's destination is unused.
3070 That would not cause incorrect code, but does cause an unneeded
3073 if (insn_code_number < 0
3074 && !(added_sets_2 && i1 == 0)
3075 && GET_CODE (newpat) == PARALLEL
3076 && XVECLEN (newpat, 0) == 2
3077 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
3078 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
3079 && asm_noperands (newpat) < 0)
3081 rtx set0 = XVECEXP (newpat, 0, 0);
3082 rtx set1 = XVECEXP (newpat, 0, 1);
3084 if (((REG_P (SET_DEST (set1))
3085 && find_reg_note (i3, REG_UNUSED, SET_DEST (set1)))
3086 || (GET_CODE (SET_DEST (set1)) == SUBREG
3087 && find_reg_note (i3, REG_UNUSED, SUBREG_REG (SET_DEST (set1)))))
3088 && insn_nothrow_p (i3)
3089 && !side_effects_p (SET_SRC (set1)))
3092 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
3095 else if (((REG_P (SET_DEST (set0))
3096 && find_reg_note (i3, REG_UNUSED, SET_DEST (set0)))
3097 || (GET_CODE (SET_DEST (set0)) == SUBREG
3098 && find_reg_note (i3, REG_UNUSED,
3099 SUBREG_REG (SET_DEST (set0)))))
3100 && insn_nothrow_p (i3)
3101 && !side_effects_p (SET_SRC (set0)))
3104 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
3106 if (insn_code_number >= 0)
3107 changed_i3_dest = 1;
3111 /* If we were combining three insns and the result is a simple SET
3112 with no ASM_OPERANDS that wasn't recognized, try to split it into two
3113 insns. There are two ways to do this. It can be split using a
3114 machine-specific method (like when you have an addition of a large
3115 constant) or by combine in the function find_split_point. */
3117 if (i1 && insn_code_number < 0 && GET_CODE (newpat) == SET
3118 && asm_noperands (newpat) < 0)
3120 rtx parallel, m_split, *split;
3122 /* See if the MD file can split NEWPAT. If it can't, see if letting it
3123 use I2DEST as a scratch register will help. In the latter case,
3124 convert I2DEST to the mode of the source of NEWPAT if we can. */
3126 m_split = combine_split_insns (newpat, i3);
3128 /* We can only use I2DEST as a scratch reg if it doesn't overlap any
3129 inputs of NEWPAT. */
3131 /* ??? If I2DEST is not safe, and I1DEST exists, then it would be
3132 possible to try that as a scratch reg. This would require adding
3133 more code to make it work though. */
3135 if (m_split == 0 && ! reg_overlap_mentioned_p (i2dest, newpat))
3137 enum machine_mode new_mode = GET_MODE (SET_DEST (newpat));
3139 /* First try to split using the original register as a
3140 scratch register. */
3141 parallel = gen_rtx_PARALLEL (VOIDmode,
3142 gen_rtvec (2, newpat,
3143 gen_rtx_CLOBBER (VOIDmode,
3145 m_split = combine_split_insns (parallel, i3);
3147 /* If that didn't work, try changing the mode of I2DEST if
3150 && new_mode != GET_MODE (i2dest)
3151 && new_mode != VOIDmode
3152 && can_change_dest_mode (i2dest, added_sets_2, new_mode))
3154 enum machine_mode old_mode = GET_MODE (i2dest);
3157 if (REGNO (i2dest) < FIRST_PSEUDO_REGISTER)
3158 ni2dest = gen_rtx_REG (new_mode, REGNO (i2dest));
3161 SUBST_MODE (regno_reg_rtx[REGNO (i2dest)], new_mode);
3162 ni2dest = regno_reg_rtx[REGNO (i2dest)];
3165 parallel = (gen_rtx_PARALLEL
3167 gen_rtvec (2, newpat,
3168 gen_rtx_CLOBBER (VOIDmode,
3170 m_split = combine_split_insns (parallel, i3);
3173 && REGNO (i2dest) >= FIRST_PSEUDO_REGISTER)
3177 adjust_reg_mode (regno_reg_rtx[REGNO (i2dest)], old_mode);
3178 buf = undobuf.undos;
3179 undobuf.undos = buf->next;
3180 buf->next = undobuf.frees;
3181 undobuf.frees = buf;
3185 i2scratch = m_split != 0;
3188 /* If recog_for_combine has discarded clobbers, try to use them
3189 again for the split. */
3190 if (m_split == 0 && newpat_vec_with_clobbers)
3192 parallel = gen_rtx_PARALLEL (VOIDmode, newpat_vec_with_clobbers);
3193 m_split = combine_split_insns (parallel, i3);
3196 if (m_split && NEXT_INSN (m_split) == NULL_RTX)
3198 m_split = PATTERN (m_split);
3199 insn_code_number = recog_for_combine (&m_split, i3, &new_i3_notes);
3200 if (insn_code_number >= 0)
3203 else if (m_split && NEXT_INSN (NEXT_INSN (m_split)) == NULL_RTX
3204 && (next_real_insn (i2) == i3
3205 || ! use_crosses_set_p (PATTERN (m_split), DF_INSN_LUID (i2))))
3208 rtx newi3pat = PATTERN (NEXT_INSN (m_split));
3209 newi2pat = PATTERN (m_split);
3211 i3set = single_set (NEXT_INSN (m_split));
3212 i2set = single_set (m_split);
3214 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
3216 /* If I2 or I3 has multiple SETs, we won't know how to track
3217 register status, so don't use these insns. If I2's destination
3218 is used between I2 and I3, we also can't use these insns. */
3220 if (i2_code_number >= 0 && i2set && i3set
3221 && (next_real_insn (i2) == i3
3222 || ! reg_used_between_p (SET_DEST (i2set), i2, i3)))
3223 insn_code_number = recog_for_combine (&newi3pat, i3,
3225 if (insn_code_number >= 0)
3228 /* It is possible that both insns now set the destination of I3.
3229 If so, we must show an extra use of it. */
3231 if (insn_code_number >= 0)
3233 rtx new_i3_dest = SET_DEST (i3set);
3234 rtx new_i2_dest = SET_DEST (i2set);
3236 while (GET_CODE (new_i3_dest) == ZERO_EXTRACT
3237 || GET_CODE (new_i3_dest) == STRICT_LOW_PART
3238 || GET_CODE (new_i3_dest) == SUBREG)
3239 new_i3_dest = XEXP (new_i3_dest, 0);
3241 while (GET_CODE (new_i2_dest) == ZERO_EXTRACT
3242 || GET_CODE (new_i2_dest) == STRICT_LOW_PART
3243 || GET_CODE (new_i2_dest) == SUBREG)
3244 new_i2_dest = XEXP (new_i2_dest, 0);
3246 if (REG_P (new_i3_dest)
3247 && REG_P (new_i2_dest)
3248 && REGNO (new_i3_dest) == REGNO (new_i2_dest))
3249 INC_REG_N_SETS (REGNO (new_i2_dest), 1);
3253 /* If we can split it and use I2DEST, go ahead and see if that
3254 helps things be recognized. Verify that none of the registers
3255 are set between I2 and I3. */
3256 if (insn_code_number < 0 && (split = find_split_point (&newpat, i3)) != 0
3260 /* We need I2DEST in the proper mode. If it is a hard register
3261 or the only use of a pseudo, we can change its mode.
3262 Make sure we don't change a hard register to have a mode that
3263 isn't valid for it, or change the number of registers. */
3264 && (GET_MODE (*split) == GET_MODE (i2dest)
3265 || GET_MODE (*split) == VOIDmode
3266 || can_change_dest_mode (i2dest, added_sets_2,
3268 && (next_real_insn (i2) == i3
3269 || ! use_crosses_set_p (*split, DF_INSN_LUID (i2)))
3270 /* We can't overwrite I2DEST if its value is still used by
3272 && ! reg_referenced_p (i2dest, newpat))
3274 rtx newdest = i2dest;
3275 enum rtx_code split_code = GET_CODE (*split);
3276 enum machine_mode split_mode = GET_MODE (*split);
3277 bool subst_done = false;
3278 newi2pat = NULL_RTX;
3282 /* Get NEWDEST as a register in the proper mode. We have already
3283 validated that we can do this. */
3284 if (GET_MODE (i2dest) != split_mode && split_mode != VOIDmode)
3286 if (REGNO (i2dest) < FIRST_PSEUDO_REGISTER)
3287 newdest = gen_rtx_REG (split_mode, REGNO (i2dest));
3290 SUBST_MODE (regno_reg_rtx[REGNO (i2dest)], split_mode);
3291 newdest = regno_reg_rtx[REGNO (i2dest)];
3295 /* If *SPLIT is a (mult FOO (const_int pow2)), convert it to
3296 an ASHIFT. This can occur if it was inside a PLUS and hence
3297 appeared to be a memory address. This is a kludge. */
3298 if (split_code == MULT
3299 && CONST_INT_P (XEXP (*split, 1))
3300 && INTVAL (XEXP (*split, 1)) > 0
3301 && (i = exact_log2 (INTVAL (XEXP (*split, 1)))) >= 0)
3303 SUBST (*split, gen_rtx_ASHIFT (split_mode,
3304 XEXP (*split, 0), GEN_INT (i)));
3305 /* Update split_code because we may not have a multiply
3307 split_code = GET_CODE (*split);
3310 #ifdef INSN_SCHEDULING
3311 /* If *SPLIT is a paradoxical SUBREG, when we split it, it should
3312 be written as a ZERO_EXTEND. */
3313 if (split_code == SUBREG && MEM_P (SUBREG_REG (*split)))
3315 #ifdef LOAD_EXTEND_OP
3316 /* Or as a SIGN_EXTEND if LOAD_EXTEND_OP says that that's
3317 what it really is. */
3318 if (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (*split)))
3320 SUBST (*split, gen_rtx_SIGN_EXTEND (split_mode,
3321 SUBREG_REG (*split)));
3324 SUBST (*split, gen_rtx_ZERO_EXTEND (split_mode,
3325 SUBREG_REG (*split)));
3329 /* Attempt to split binary operators using arithmetic identities. */
3330 if (BINARY_P (SET_SRC (newpat))
3331 && split_mode == GET_MODE (SET_SRC (newpat))
3332 && ! side_effects_p (SET_SRC (newpat)))
3334 rtx setsrc = SET_SRC (newpat);
3335 enum machine_mode mode = GET_MODE (setsrc);
3336 enum rtx_code code = GET_CODE (setsrc);
3337 rtx src_op0 = XEXP (setsrc, 0);
3338 rtx src_op1 = XEXP (setsrc, 1);
3340 /* Split "X = Y op Y" as "Z = Y; X = Z op Z". */
3341 if (rtx_equal_p (src_op0, src_op1))
3343 newi2pat = gen_rtx_SET (VOIDmode, newdest, src_op0);
3344 SUBST (XEXP (setsrc, 0), newdest);
3345 SUBST (XEXP (setsrc, 1), newdest);
3348 /* Split "((P op Q) op R) op S" where op is PLUS or MULT. */
3349 else if ((code == PLUS || code == MULT)
3350 && GET_CODE (src_op0) == code
3351 && GET_CODE (XEXP (src_op0, 0)) == code
3352 && (INTEGRAL_MODE_P (mode)
3353 || (FLOAT_MODE_P (mode)
3354 && flag_unsafe_math_optimizations)))
3356 rtx p = XEXP (XEXP (src_op0, 0), 0);
3357 rtx q = XEXP (XEXP (src_op0, 0), 1);
3358 rtx r = XEXP (src_op0, 1);
3361 /* Split both "((X op Y) op X) op Y" and
3362 "((X op Y) op Y) op X" as "T op T" where T is
3364 if ((rtx_equal_p (p,r) && rtx_equal_p (q,s))
3365 || (rtx_equal_p (p,s) && rtx_equal_p (q,r)))
3367 newi2pat = gen_rtx_SET (VOIDmode, newdest,
3369 SUBST (XEXP (setsrc, 0), newdest);
3370 SUBST (XEXP (setsrc, 1), newdest);
3373 /* Split "((X op X) op Y) op Y)" as "T op T" where
3375 else if (rtx_equal_p (p,q) && rtx_equal_p (r,s))
3377 rtx tmp = simplify_gen_binary (code, mode, p, r);
3378 newi2pat = gen_rtx_SET (VOIDmode, newdest, tmp);
3379 SUBST (XEXP (setsrc, 0), newdest);
3380 SUBST (XEXP (setsrc, 1), newdest);
3388 newi2pat = gen_rtx_SET (VOIDmode, newdest, *split);
3389 SUBST (*split, newdest);
3392 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
3394 /* recog_for_combine might have added CLOBBERs to newi2pat.
3395 Make sure NEWPAT does not depend on the clobbered regs. */
3396 if (GET_CODE (newi2pat) == PARALLEL)
3397 for (i = XVECLEN (newi2pat, 0) - 1; i >= 0; i--)
3398 if (GET_CODE (XVECEXP (newi2pat, 0, i)) == CLOBBER)
3400 rtx reg = XEXP (XVECEXP (newi2pat, 0, i), 0);
3401 if (reg_overlap_mentioned_p (reg, newpat))
3408 /* If the split point was a MULT and we didn't have one before,
3409 don't use one now. */
3410 if (i2_code_number >= 0 && ! (split_code == MULT && ! have_mult))
3411 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
3415 /* Check for a case where we loaded from memory in a narrow mode and
3416 then sign extended it, but we need both registers. In that case,
3417 we have a PARALLEL with both loads from the same memory location.
3418 We can split this into a load from memory followed by a register-register
3419 copy. This saves at least one insn, more if register allocation can
3422 We cannot do this if the destination of the first assignment is a
3423 condition code register or cc0. We eliminate this case by making sure
3424 the SET_DEST and SET_SRC have the same mode.
3426 We cannot do this if the destination of the second assignment is
3427 a register that we have already assumed is zero-extended. Similarly
3428 for a SUBREG of such a register. */
3430 else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0
3431 && GET_CODE (newpat) == PARALLEL
3432 && XVECLEN (newpat, 0) == 2
3433 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
3434 && GET_CODE (SET_SRC (XVECEXP (newpat, 0, 0))) == SIGN_EXTEND
3435 && (GET_MODE (SET_DEST (XVECEXP (newpat, 0, 0)))
3436 == GET_MODE (SET_SRC (XVECEXP (newpat, 0, 0))))
3437 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
3438 && rtx_equal_p (SET_SRC (XVECEXP (newpat, 0, 1)),
3439 XEXP (SET_SRC (XVECEXP (newpat, 0, 0)), 0))
3440 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)),
3442 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
3443 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
3444 && ! (temp = SET_DEST (XVECEXP (newpat, 0, 1)),
3446 && VEC_index (reg_stat_type, reg_stat,
3447 REGNO (temp))->nonzero_bits != 0
3448 && GET_MODE_BITSIZE (GET_MODE (temp)) < BITS_PER_WORD
3449 && GET_MODE_BITSIZE (GET_MODE (temp)) < HOST_BITS_PER_INT
3450 && (VEC_index (reg_stat_type, reg_stat,
3451 REGNO (temp))->nonzero_bits
3452 != GET_MODE_MASK (word_mode))))
3453 && ! (GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) == SUBREG
3454 && (temp = SUBREG_REG (SET_DEST (XVECEXP (newpat, 0, 1))),
3456 && VEC_index (reg_stat_type, reg_stat,
3457 REGNO (temp))->nonzero_bits != 0
3458 && GET_MODE_BITSIZE (GET_MODE (temp)) < BITS_PER_WORD
3459 && GET_MODE_BITSIZE (GET_MODE (temp)) < HOST_BITS_PER_INT
3460 && (VEC_index (reg_stat_type, reg_stat,
3461 REGNO (temp))->nonzero_bits
3462 != GET_MODE_MASK (word_mode)))))
3463 && ! reg_overlap_mentioned_p (SET_DEST (XVECEXP (newpat, 0, 1)),
3464 SET_SRC (XVECEXP (newpat, 0, 1)))
3465 && ! find_reg_note (i3, REG_UNUSED,
3466 SET_DEST (XVECEXP (newpat, 0, 0))))
3470 newi2pat = XVECEXP (newpat, 0, 0);
3471 ni2dest = SET_DEST (XVECEXP (newpat, 0, 0));
3472 newpat = XVECEXP (newpat, 0, 1);
3473 SUBST (SET_SRC (newpat),
3474 gen_lowpart (GET_MODE (SET_SRC (newpat)), ni2dest));
3475 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
3477 if (i2_code_number >= 0)
3478 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
3480 if (insn_code_number >= 0)
3484 /* Similarly, check for a case where we have a PARALLEL of two independent
3485 SETs but we started with three insns. In this case, we can do the sets
3486 as two separate insns. This case occurs when some SET allows two
3487 other insns to combine, but the destination of that SET is still live. */
3489 else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0
3490 && GET_CODE (newpat) == PARALLEL
3491 && XVECLEN (newpat, 0) == 2
3492 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
3493 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != ZERO_EXTRACT
3494 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != STRICT_LOW_PART
3495 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
3496 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
3497 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
3498 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)),
3500 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 1)),
3501 XVECEXP (newpat, 0, 0))
3502 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 0)),
3503 XVECEXP (newpat, 0, 1))
3504 && ! (contains_muldiv (SET_SRC (XVECEXP (newpat, 0, 0)))
3505 && contains_muldiv (SET_SRC (XVECEXP (newpat, 0, 1))))
3507 /* We cannot split the parallel into two sets if both sets
3509 && ! (reg_referenced_p (cc0_rtx, XVECEXP (newpat, 0, 0))
3510 && reg_referenced_p (cc0_rtx, XVECEXP (newpat, 0, 1)))
3514 /* Normally, it doesn't matter which of the two is done first,
3515 but it does if one references cc0. In that case, it has to
3518 if (reg_referenced_p (cc0_rtx, XVECEXP (newpat, 0, 0)))
3520 newi2pat = XVECEXP (newpat, 0, 0);
3521 newpat = XVECEXP (newpat, 0, 1);
3526 newi2pat = XVECEXP (newpat, 0, 1);
3527 newpat = XVECEXP (newpat, 0, 0);
3530 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
3532 if (i2_code_number >= 0)
3533 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
3536 /* If it still isn't recognized, fail and change things back the way they
3538 if ((insn_code_number < 0
3539 /* Is the result a reasonable ASM_OPERANDS? */
3540 && (! check_asm_operands (newpat) || added_sets_1 || added_sets_2)))
3546 /* If we had to change another insn, make sure it is valid also. */
3547 if (undobuf.other_insn)
3549 CLEAR_HARD_REG_SET (newpat_used_regs);
3551 other_pat = PATTERN (undobuf.other_insn);
3552 other_code_number = recog_for_combine (&other_pat, undobuf.other_insn,
3555 if (other_code_number < 0 && ! check_asm_operands (other_pat))
3563 /* If I2 is the CC0 setter and I3 is the CC0 user then check whether
3564 they are adjacent to each other or not. */
3566 rtx p = prev_nonnote_insn (i3);
3567 if (p && p != i2 && NONJUMP_INSN_P (p) && newi2pat
3568 && sets_cc0_p (newi2pat))
3576 /* Only allow this combination if insn_rtx_costs reports that the
3577 replacement instructions are cheaper than the originals. */
3578 if (!combine_validate_cost (i1, i2, i3, newpat, newi2pat, other_pat))
3584 if (MAY_HAVE_DEBUG_INSNS)
3588 for (undo = undobuf.undos; undo; undo = undo->next)
3589 if (undo->kind == UNDO_MODE)
3591 rtx reg = *undo->where.r;
3592 enum machine_mode new_mode = GET_MODE (reg);
3593 enum machine_mode old_mode = undo->old_contents.m;
3595 /* Temporarily revert mode back. */
3596 adjust_reg_mode (reg, old_mode);
3598 if (reg == i2dest && i2scratch)
3600 /* If we used i2dest as a scratch register with a
3601 different mode, substitute it for the original
3602 i2src while its original mode is temporarily
3603 restored, and then clear i2scratch so that we don't
3604 do it again later. */
3605 propagate_for_debug (i2, i3, reg, i2src, false);
3607 /* Put back the new mode. */
3608 adjust_reg_mode (reg, new_mode);
3612 rtx tempreg = gen_raw_REG (old_mode, REGNO (reg));
3623 last = undobuf.other_insn;
3627 /* We're dealing with a reg that changed mode but not
3628 meaning, so we want to turn it into a subreg for
3629 the new mode. However, because of REG sharing and
3630 because its mode had already changed, we have to do
3631 it in two steps. First, replace any debug uses of
3632 reg, with its original mode temporarily restored,
3633 with this copy we have created; then, replace the
3634 copy with the SUBREG of the original shared reg,
3635 once again changed to the new mode. */
3636 propagate_for_debug (first, last, reg, tempreg, false);
3637 adjust_reg_mode (reg, new_mode);
3638 propagate_for_debug (first, last, tempreg,
3639 lowpart_subreg (old_mode, reg, new_mode),
3645 /* If we will be able to accept this, we have made a
3646 change to the destination of I3. This requires us to
3647 do a few adjustments. */
3649 if (changed_i3_dest)
3651 PATTERN (i3) = newpat;
3652 adjust_for_new_dest (i3);
3655 /* We now know that we can do this combination. Merge the insns and
3656 update the status of registers and LOG_LINKS. */
3658 if (undobuf.other_insn)
3662 PATTERN (undobuf.other_insn) = other_pat;
3664 /* If any of the notes in OTHER_INSN were REG_UNUSED, ensure that they
3665 are still valid. Then add any non-duplicate notes added by
3666 recog_for_combine. */
3667 for (note = REG_NOTES (undobuf.other_insn); note; note = next)
3669 next = XEXP (note, 1);
3671 if (REG_NOTE_KIND (note) == REG_UNUSED
3672 && ! reg_set_p (XEXP (note, 0), PATTERN (undobuf.other_insn)))
3673 remove_note (undobuf.other_insn, note);
3676 distribute_notes (new_other_notes, undobuf.other_insn,
3677 undobuf.other_insn, NULL_RTX, NULL_RTX, NULL_RTX);
3686 /* I3 now uses what used to be its destination and which is now
3687 I2's destination. This requires us to do a few adjustments. */
3688 PATTERN (i3) = newpat;
3689 adjust_for_new_dest (i3);
3691 /* We need a LOG_LINK from I3 to I2. But we used to have one,
3694 However, some later insn might be using I2's dest and have
3695 a LOG_LINK pointing at I3. We must remove this link.
3696 The simplest way to remove the link is to point it at I1,
3697 which we know will be a NOTE. */
3699 /* newi2pat is usually a SET here; however, recog_for_combine might
3700 have added some clobbers. */
3701 if (GET_CODE (newi2pat) == PARALLEL)
3702 ni2dest = SET_DEST (XVECEXP (newi2pat, 0, 0));
3704 ni2dest = SET_DEST (newi2pat);
3706 for (insn = NEXT_INSN (i3);
3707 insn && (this_basic_block->next_bb == EXIT_BLOCK_PTR
3708 || insn != BB_HEAD (this_basic_block->next_bb));
3709 insn = NEXT_INSN (insn))
3711 if (INSN_P (insn) && reg_referenced_p (ni2dest, PATTERN (insn)))
3713 for (link = LOG_LINKS (insn); link;
3714 link = XEXP (link, 1))
3715 if (XEXP (link, 0) == i3)
3716 XEXP (link, 0) = i1;
3724 rtx i3notes, i2notes, i1notes = 0;
3725 rtx i3links, i2links, i1links = 0;
3728 /* Compute which registers we expect to eliminate. newi2pat may be setting
3729 either i3dest or i2dest, so we must check it. Also, i1dest may be the
3730 same as i3dest, in which case newi2pat may be setting i1dest. */
3731 rtx elim_i2 = ((newi2pat && reg_set_p (i2dest, newi2pat))
3732 || i2dest_in_i2src || i2dest_in_i1src
3735 rtx elim_i1 = (i1 == 0 || i1dest_in_i1src
3736 || (newi2pat && reg_set_p (i1dest, newi2pat))
3740 /* Get the old REG_NOTES and LOG_LINKS from all our insns and
3742 i3notes = REG_NOTES (i3), i3links = LOG_LINKS (i3);
3743 i2notes = REG_NOTES (i2), i2links = LOG_LINKS (i2);
3745 i1notes = REG_NOTES (i1), i1links = LOG_LINKS (i1);
3747 /* Ensure that we do not have something that should not be shared but
3748 occurs multiple times in the new insns. Check this by first
3749 resetting all the `used' flags and then copying anything is shared. */
3751 reset_used_flags (i3notes);
3752 reset_used_flags (i2notes);
3753 reset_used_flags (i1notes);
3754 reset_used_flags (newpat);
3755 reset_used_flags (newi2pat);
3756 if (undobuf.other_insn)
3757 reset_used_flags (PATTERN (undobuf.other_insn));
3759 i3notes = copy_rtx_if_shared (i3notes);
3760 i2notes = copy_rtx_if_shared (i2notes);
3761 i1notes = copy_rtx_if_shared (i1notes);
3762 newpat = copy_rtx_if_shared (newpat);
3763 newi2pat = copy_rtx_if_shared (newi2pat);
3764 if (undobuf.other_insn)
3765 reset_used_flags (PATTERN (undobuf.other_insn));
3767 INSN_CODE (i3) = insn_code_number;
3768 PATTERN (i3) = newpat;
3770 if (CALL_P (i3) && CALL_INSN_FUNCTION_USAGE (i3))
3772 rtx call_usage = CALL_INSN_FUNCTION_USAGE (i3);
3774 reset_used_flags (call_usage);
3775 call_usage = copy_rtx (call_usage);
3778 replace_rtx (call_usage, i2dest, i2src);
3781 replace_rtx (call_usage, i1dest, i1src);
3783 CALL_INSN_FUNCTION_USAGE (i3) = call_usage;
3786 if (undobuf.other_insn)
3787 INSN_CODE (undobuf.other_insn) = other_code_number;
3789 /* We had one special case above where I2 had more than one set and
3790 we replaced a destination of one of those sets with the destination
3791 of I3. In that case, we have to update LOG_LINKS of insns later
3792 in this basic block. Note that this (expensive) case is rare.
3794 Also, in this case, we must pretend that all REG_NOTEs for I2
3795 actually came from I3, so that REG_UNUSED notes from I2 will be
3796 properly handled. */
3798 if (i3_subst_into_i2)
3800 for (i = 0; i < XVECLEN (PATTERN (i2), 0); i++)
3801 if ((GET_CODE (XVECEXP (PATTERN (i2), 0, i)) == SET
3802 || GET_CODE (XVECEXP (PATTERN (i2), 0, i)) == CLOBBER)
3803 && REG_P (SET_DEST (XVECEXP (PATTERN (i2), 0, i)))
3804 && SET_DEST (XVECEXP (PATTERN (i2), 0, i)) != i2dest
3805 && ! find_reg_note (i2, REG_UNUSED,
3806 SET_DEST (XVECEXP (PATTERN (i2), 0, i))))
3807 for (temp = NEXT_INSN (i2);
3808 temp && (this_basic_block->next_bb == EXIT_BLOCK_PTR
3809 || BB_HEAD (this_basic_block) != temp);
3810 temp = NEXT_INSN (temp))
3811 if (temp != i3 && INSN_P (temp))
3812 for (link = LOG_LINKS (temp); link; link = XEXP (link, 1))
3813 if (XEXP (link, 0) == i2)
3814 XEXP (link, 0) = i3;
3819 while (XEXP (link, 1))
3820 link = XEXP (link, 1);
3821 XEXP (link, 1) = i2notes;
3835 if (MAY_HAVE_DEBUG_INSNS && i2scratch)
3836 propagate_for_debug (i2, i3, i2dest, i2src, false);
3837 INSN_CODE (i2) = i2_code_number;
3838 PATTERN (i2) = newi2pat;
3842 if (MAY_HAVE_DEBUG_INSNS && i2src)
3843 propagate_for_debug (i2, i3, i2dest, i2src, i3_subst_into_i2);
3844 SET_INSN_DELETED (i2);
3851 if (MAY_HAVE_DEBUG_INSNS)
3852 propagate_for_debug (i1, i3, i1dest, i1src, false);
3853 SET_INSN_DELETED (i1);
3856 /* Get death notes for everything that is now used in either I3 or
3857 I2 and used to die in a previous insn. If we built two new
3858 patterns, move from I1 to I2 then I2 to I3 so that we get the
3859 proper movement on registers that I2 modifies. */
3863 move_deaths (newi2pat, NULL_RTX, DF_INSN_LUID (i1), i2, &midnotes);
3864 move_deaths (newpat, newi2pat, DF_INSN_LUID (i1), i3, &midnotes);
3867 move_deaths (newpat, NULL_RTX, i1 ? DF_INSN_LUID (i1) : DF_INSN_LUID (i2),
3870 /* Distribute all the LOG_LINKS and REG_NOTES from I1, I2, and I3. */
3872 distribute_notes (i3notes, i3, i3, newi2pat ? i2 : NULL_RTX,
3875 distribute_notes (i2notes, i2, i3, newi2pat ? i2 : NULL_RTX,
3878 distribute_notes (i1notes, i1, i3, newi2pat ? i2 : NULL_RTX,
3881 distribute_notes (midnotes, NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
3884 /* Distribute any notes added to I2 or I3 by recog_for_combine. We
3885 know these are REG_UNUSED and want them to go to the desired insn,
3886 so we always pass it as i3. */
3888 if (newi2pat && new_i2_notes)
3889 distribute_notes (new_i2_notes, i2, i2, NULL_RTX, NULL_RTX, NULL_RTX);
3892 distribute_notes (new_i3_notes, i3, i3, NULL_RTX, NULL_RTX, NULL_RTX);
3894 /* If I3DEST was used in I3SRC, it really died in I3. We may need to
3895 put a REG_DEAD note for it somewhere. If NEWI2PAT exists and sets
3896 I3DEST, the death must be somewhere before I2, not I3. If we passed I3
3897 in that case, it might delete I2. Similarly for I2 and I1.
3898 Show an additional death due to the REG_DEAD note we make here. If
3899 we discard it in distribute_notes, we will decrement it again. */
3903 if (newi2pat && reg_set_p (i3dest_killed, newi2pat))
3904 distribute_notes (alloc_reg_note (REG_DEAD, i3dest_killed,
3906 NULL_RTX, i2, NULL_RTX, elim_i2, elim_i1);
3908 distribute_notes (alloc_reg_note (REG_DEAD, i3dest_killed,
3910 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
3914 if (i2dest_in_i2src)
3916 if (newi2pat && reg_set_p (i2dest, newi2pat))
3917 distribute_notes (alloc_reg_note (REG_DEAD, i2dest, NULL_RTX),
3918 NULL_RTX, i2, NULL_RTX, NULL_RTX, NULL_RTX);
3920 distribute_notes (alloc_reg_note (REG_DEAD, i2dest, NULL_RTX),
3921 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
3922 NULL_RTX, NULL_RTX);
3925 if (i1dest_in_i1src)
3927 if (newi2pat && reg_set_p (i1dest, newi2pat))
3928 distribute_notes (alloc_reg_note (REG_DEAD, i1dest, NULL_RTX),
3929 NULL_RTX, i2, NULL_RTX, NULL_RTX, NULL_RTX);
3931 distribute_notes (alloc_reg_note (REG_DEAD, i1dest, NULL_RTX),
3932 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
3933 NULL_RTX, NULL_RTX);
3936 distribute_links (i3links);
3937 distribute_links (i2links);
3938 distribute_links (i1links);
3943 rtx i2_insn = 0, i2_val = 0, set;
3945 /* The insn that used to set this register doesn't exist, and
3946 this life of the register may not exist either. See if one of
3947 I3's links points to an insn that sets I2DEST. If it does,
3948 that is now the last known value for I2DEST. If we don't update
3949 this and I2 set the register to a value that depended on its old
3950 contents, we will get confused. If this insn is used, thing
3951 will be set correctly in combine_instructions. */
3953 for (link = LOG_LINKS (i3); link; link = XEXP (link, 1))
3954 if ((set = single_set (XEXP (link, 0))) != 0
3955 && rtx_equal_p (i2dest, SET_DEST (set)))
3956 i2_insn = XEXP (link, 0), i2_val = SET_SRC (set);
3958 record_value_for_reg (i2dest, i2_insn, i2_val);
3960 /* If the reg formerly set in I2 died only once and that was in I3,
3961 zero its use count so it won't make `reload' do any work. */
3963 && (newi2pat == 0 || ! reg_mentioned_p (i2dest, newi2pat))
3964 && ! i2dest_in_i2src)
3966 regno = REGNO (i2dest);
3967 INC_REG_N_SETS (regno, -1);
3971 if (i1 && REG_P (i1dest))
3974 rtx i1_insn = 0, i1_val = 0, set;
3976 for (link = LOG_LINKS (i3); link; link = XEXP (link, 1))
3977 if ((set = single_set (XEXP (link, 0))) != 0
3978 && rtx_equal_p (i1dest, SET_DEST (set)))
3979 i1_insn = XEXP (link, 0), i1_val = SET_SRC (set);
3981 record_value_for_reg (i1dest, i1_insn, i1_val);
3983 regno = REGNO (i1dest);
3984 if (! added_sets_1 && ! i1dest_in_i1src)
3985 INC_REG_N_SETS (regno, -1);
3988 /* Update reg_stat[].nonzero_bits et al for any changes that may have
3989 been made to this insn. The order of
3990 set_nonzero_bits_and_sign_copies() is important. Because newi2pat
3991 can affect nonzero_bits of newpat */
3993 note_stores (newi2pat, set_nonzero_bits_and_sign_copies, NULL);
3994 note_stores (newpat, set_nonzero_bits_and_sign_copies, NULL);
3997 if (undobuf.other_insn != NULL_RTX)
4001 fprintf (dump_file, "modifying other_insn ");
4002 dump_insn_slim (dump_file, undobuf.other_insn);
4004 df_insn_rescan (undobuf.other_insn);
4007 if (i1 && !(NOTE_P(i1) && (NOTE_KIND (i1) == NOTE_INSN_DELETED)))
4011 fprintf (dump_file, "modifying insn i1 ");
4012 dump_insn_slim (dump_file, i1);
4014 df_insn_rescan (i1);
4017 if (i2 && !(NOTE_P(i2) && (NOTE_KIND (i2) == NOTE_INSN_DELETED)))
4021 fprintf (dump_file, "modifying insn i2 ");
4022 dump_insn_slim (dump_file, i2);
4024 df_insn_rescan (i2);
4027 if (i3 && !(NOTE_P(i3) && (NOTE_KIND (i3) == NOTE_INSN_DELETED)))
4031 fprintf (dump_file, "modifying insn i3 ");
4032 dump_insn_slim (dump_file, i3);
4034 df_insn_rescan (i3);
4037 /* Set new_direct_jump_p if a new return or simple jump instruction
4038 has been created. Adjust the CFG accordingly. */
4040 if (returnjump_p (i3) || any_uncondjump_p (i3))
4042 *new_direct_jump_p = 1;
4043 mark_jump_label (PATTERN (i3), i3, 0);
4044 update_cfg_for_uncondjump (i3);
4047 if (undobuf.other_insn != NULL_RTX
4048 && (returnjump_p (undobuf.other_insn)
4049 || any_uncondjump_p (undobuf.other_insn)))
4051 *new_direct_jump_p = 1;
4052 update_cfg_for_uncondjump (undobuf.other_insn);
4055 /* A noop might also need cleaning up of CFG, if it comes from the
4056 simplification of a jump. */
4057 if (GET_CODE (newpat) == SET
4058 && SET_SRC (newpat) == pc_rtx
4059 && SET_DEST (newpat) == pc_rtx)
4061 *new_direct_jump_p = 1;
4062 update_cfg_for_uncondjump (i3);
4065 combine_successes++;
4068 if (added_links_insn
4069 && (newi2pat == 0 || DF_INSN_LUID (added_links_insn) < DF_INSN_LUID (i2))
4070 && DF_INSN_LUID (added_links_insn) < DF_INSN_LUID (i3))
4071 return added_links_insn;
4073 return newi2pat ? i2 : i3;
4076 /* Undo all the modifications recorded in undobuf. */
4081 struct undo *undo, *next;
4083 for (undo = undobuf.undos; undo; undo = next)
4089 *undo->where.r = undo->old_contents.r;
4092 *undo->where.i = undo->old_contents.i;
4095 adjust_reg_mode (*undo->where.r, undo->old_contents.m);
4101 undo->next = undobuf.frees;
4102 undobuf.frees = undo;
4108 /* We've committed to accepting the changes we made. Move all
4109 of the undos to the free list. */
4114 struct undo *undo, *next;
4116 for (undo = undobuf.undos; undo; undo = next)
4119 undo->next = undobuf.frees;
4120 undobuf.frees = undo;
4125 /* Find the innermost point within the rtx at LOC, possibly LOC itself,
4126 where we have an arithmetic expression and return that point. LOC will
4129 try_combine will call this function to see if an insn can be split into
4133 find_split_point (rtx *loc, rtx insn)
4136 enum rtx_code code = GET_CODE (x);
4138 unsigned HOST_WIDE_INT len = 0;
4139 HOST_WIDE_INT pos = 0;
4141 rtx inner = NULL_RTX;
4143 /* First special-case some codes. */
4147 #ifdef INSN_SCHEDULING
4148 /* If we are making a paradoxical SUBREG invalid, it becomes a split
4150 if (MEM_P (SUBREG_REG (x)))
4153 return find_split_point (&SUBREG_REG (x), insn);
4157 /* If we have (mem (const ..)) or (mem (symbol_ref ...)), split it
4158 using LO_SUM and HIGH. */
4159 if (GET_CODE (XEXP (x, 0)) == CONST
4160 || GET_CODE (XEXP (x, 0)) == SYMBOL_REF)
4162 enum machine_mode address_mode
4163 = targetm.addr_space.address_mode (MEM_ADDR_SPACE (x));
4166 gen_rtx_LO_SUM (address_mode,
4167 gen_rtx_HIGH (address_mode, XEXP (x, 0)),
4169 return &XEXP (XEXP (x, 0), 0);
4173 /* If we have a PLUS whose second operand is a constant and the
4174 address is not valid, perhaps will can split it up using
4175 the machine-specific way to split large constants. We use
4176 the first pseudo-reg (one of the virtual regs) as a placeholder;
4177 it will not remain in the result. */
4178 if (GET_CODE (XEXP (x, 0)) == PLUS
4179 && CONST_INT_P (XEXP (XEXP (x, 0), 1))
4180 && ! memory_address_addr_space_p (GET_MODE (x), XEXP (x, 0),
4181 MEM_ADDR_SPACE (x)))
4183 rtx reg = regno_reg_rtx[FIRST_PSEUDO_REGISTER];
4184 rtx seq = combine_split_insns (gen_rtx_SET (VOIDmode, reg,
4188 /* This should have produced two insns, each of which sets our
4189 placeholder. If the source of the second is a valid address,
4190 we can make put both sources together and make a split point
4194 && NEXT_INSN (seq) != NULL_RTX
4195 && NEXT_INSN (NEXT_INSN (seq)) == NULL_RTX
4196 && NONJUMP_INSN_P (seq)
4197 && GET_CODE (PATTERN (seq)) == SET
4198 && SET_DEST (PATTERN (seq)) == reg
4199 && ! reg_mentioned_p (reg,
4200 SET_SRC (PATTERN (seq)))
4201 && NONJUMP_INSN_P (NEXT_INSN (seq))
4202 && GET_CODE (PATTERN (NEXT_INSN (seq))) == SET
4203 && SET_DEST (PATTERN (NEXT_INSN (seq))) == reg
4204 && memory_address_addr_space_p
4205 (GET_MODE (x), SET_SRC (PATTERN (NEXT_INSN (seq))),
4206 MEM_ADDR_SPACE (x)))
4208 rtx src1 = SET_SRC (PATTERN (seq));
4209 rtx src2 = SET_SRC (PATTERN (NEXT_INSN (seq)));
4211 /* Replace the placeholder in SRC2 with SRC1. If we can
4212 find where in SRC2 it was placed, that can become our
4213 split point and we can replace this address with SRC2.
4214 Just try two obvious places. */
4216 src2 = replace_rtx (src2, reg, src1);
4218 if (XEXP (src2, 0) == src1)
4219 split = &XEXP (src2, 0);
4220 else if (GET_RTX_FORMAT (GET_CODE (XEXP (src2, 0)))[0] == 'e'
4221 && XEXP (XEXP (src2, 0), 0) == src1)
4222 split = &XEXP (XEXP (src2, 0), 0);
4226 SUBST (XEXP (x, 0), src2);
4231 /* If that didn't work, perhaps the first operand is complex and
4232 needs to be computed separately, so make a split point there.
4233 This will occur on machines that just support REG + CONST
4234 and have a constant moved through some previous computation. */
4236 else if (!OBJECT_P (XEXP (XEXP (x, 0), 0))
4237 && ! (GET_CODE (XEXP (XEXP (x, 0), 0)) == SUBREG
4238 && OBJECT_P (SUBREG_REG (XEXP (XEXP (x, 0), 0)))))
4239 return &XEXP (XEXP (x, 0), 0);
4242 /* If we have a PLUS whose first operand is complex, try computing it
4243 separately by making a split there. */
4244 if (GET_CODE (XEXP (x, 0)) == PLUS
4245 && ! memory_address_addr_space_p (GET_MODE (x), XEXP (x, 0),
4247 && ! OBJECT_P (XEXP (XEXP (x, 0), 0))
4248 && ! (GET_CODE (XEXP (XEXP (x, 0), 0)) == SUBREG
4249 && OBJECT_P (SUBREG_REG (XEXP (XEXP (x, 0), 0)))))
4250 return &XEXP (XEXP (x, 0), 0);
4255 /* If SET_DEST is CC0 and SET_SRC is not an operand, a COMPARE, or a
4256 ZERO_EXTRACT, the most likely reason why this doesn't match is that
4257 we need to put the operand into a register. So split at that
4260 if (SET_DEST (x) == cc0_rtx
4261 && GET_CODE (SET_SRC (x)) != COMPARE
4262 && GET_CODE (SET_SRC (x)) != ZERO_EXTRACT
4263 && !OBJECT_P (SET_SRC (x))
4264 && ! (GET_CODE (SET_SRC (x)) == SUBREG
4265 && OBJECT_P (SUBREG_REG (SET_SRC (x)))))
4266 return &SET_SRC (x);
4269 /* See if we can split SET_SRC as it stands. */
4270 split = find_split_point (&SET_SRC (x), insn);
4271 if (split && split != &SET_SRC (x))
4274 /* See if we can split SET_DEST as it stands. */
4275 split = find_split_point (&SET_DEST (x), insn);
4276 if (split && split != &SET_DEST (x))
4279 /* See if this is a bitfield assignment with everything constant. If
4280 so, this is an IOR of an AND, so split it into that. */
4281 if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
4282 && (GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0)))
4283 <= HOST_BITS_PER_WIDE_INT)
4284 && CONST_INT_P (XEXP (SET_DEST (x), 1))
4285 && CONST_INT_P (XEXP (SET_DEST (x), 2))
4286 && CONST_INT_P (SET_SRC (x))
4287 && ((INTVAL (XEXP (SET_DEST (x), 1))
4288 + INTVAL (XEXP (SET_DEST (x), 2)))
4289 <= GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0))))
4290 && ! side_effects_p (XEXP (SET_DEST (x), 0)))
4292 HOST_WIDE_INT pos = INTVAL (XEXP (SET_DEST (x), 2));
4293 unsigned HOST_WIDE_INT len = INTVAL (XEXP (SET_DEST (x), 1));
4294 unsigned HOST_WIDE_INT src = INTVAL (SET_SRC (x));
4295 rtx dest = XEXP (SET_DEST (x), 0);
4296 enum machine_mode mode = GET_MODE (dest);
4297 unsigned HOST_WIDE_INT mask = ((HOST_WIDE_INT) 1 << len) - 1;
4300 if (BITS_BIG_ENDIAN)
4301 pos = GET_MODE_BITSIZE (mode) - len - pos;
4303 or_mask = gen_int_mode (src << pos, mode);
4306 simplify_gen_binary (IOR, mode, dest, or_mask));
4309 rtx negmask = gen_int_mode (~(mask << pos), mode);
4311 simplify_gen_binary (IOR, mode,
4312 simplify_gen_binary (AND, mode,
4317 SUBST (SET_DEST (x), dest);
4319 split = find_split_point (&SET_SRC (x), insn);
4320 if (split && split != &SET_SRC (x))
4324 /* Otherwise, see if this is an operation that we can split into two.
4325 If so, try to split that. */
4326 code = GET_CODE (SET_SRC (x));
4331 /* If we are AND'ing with a large constant that is only a single
4332 bit and the result is only being used in a context where we
4333 need to know if it is zero or nonzero, replace it with a bit
4334 extraction. This will avoid the large constant, which might
4335 have taken more than one insn to make. If the constant were
4336 not a valid argument to the AND but took only one insn to make,
4337 this is no worse, but if it took more than one insn, it will
4340 if (CONST_INT_P (XEXP (SET_SRC (x), 1))
4341 && REG_P (XEXP (SET_SRC (x), 0))
4342 && (pos = exact_log2 (INTVAL (XEXP (SET_SRC (x), 1)))) >= 7
4343 && REG_P (SET_DEST (x))
4344 && (split = find_single_use (SET_DEST (x), insn, (rtx*) 0)) != 0
4345 && (GET_CODE (*split) == EQ || GET_CODE (*split) == NE)
4346 && XEXP (*split, 0) == SET_DEST (x)
4347 && XEXP (*split, 1) == const0_rtx)
4349 rtx extraction = make_extraction (GET_MODE (SET_DEST (x)),
4350 XEXP (SET_SRC (x), 0),
4351 pos, NULL_RTX, 1, 1, 0, 0);
4352 if (extraction != 0)
4354 SUBST (SET_SRC (x), extraction);
4355 return find_split_point (loc, insn);
4361 /* If STORE_FLAG_VALUE is -1, this is (NE X 0) and only one bit of X
4362 is known to be on, this can be converted into a NEG of a shift. */
4363 if (STORE_FLAG_VALUE == -1 && XEXP (SET_SRC (x), 1) == const0_rtx
4364 && GET_MODE (SET_SRC (x)) == GET_MODE (XEXP (SET_SRC (x), 0))
4365 && 1 <= (pos = exact_log2
4366 (nonzero_bits (XEXP (SET_SRC (x), 0),
4367 GET_MODE (XEXP (SET_SRC (x), 0))))))
4369 enum machine_mode mode = GET_MODE (XEXP (SET_SRC (x), 0));
4373 gen_rtx_LSHIFTRT (mode,
4374 XEXP (SET_SRC (x), 0),
4377 split = find_split_point (&SET_SRC (x), insn);
4378 if (split && split != &SET_SRC (x))
4384 inner = XEXP (SET_SRC (x), 0);
4386 /* We can't optimize if either mode is a partial integer
4387 mode as we don't know how many bits are significant
4389 if (GET_MODE_CLASS (GET_MODE (inner)) == MODE_PARTIAL_INT
4390 || GET_MODE_CLASS (GET_MODE (SET_SRC (x))) == MODE_PARTIAL_INT)
4394 len = GET_MODE_BITSIZE (GET_MODE (inner));
4400 if (CONST_INT_P (XEXP (SET_SRC (x), 1))
4401 && CONST_INT_P (XEXP (SET_SRC (x), 2)))
4403 inner = XEXP (SET_SRC (x), 0);
4404 len = INTVAL (XEXP (SET_SRC (x), 1));
4405 pos = INTVAL (XEXP (SET_SRC (x), 2));
4407 if (BITS_BIG_ENDIAN)
4408 pos = GET_MODE_BITSIZE (GET_MODE (inner)) - len - pos;
4409 unsignedp = (code == ZERO_EXTRACT);
4417 if (len && pos >= 0 && pos + len <= GET_MODE_BITSIZE (GET_MODE (inner)))
4419 enum machine_mode mode = GET_MODE (SET_SRC (x));
4421 /* For unsigned, we have a choice of a shift followed by an
4422 AND or two shifts. Use two shifts for field sizes where the
4423 constant might be too large. We assume here that we can
4424 always at least get 8-bit constants in an AND insn, which is
4425 true for every current RISC. */
4427 if (unsignedp && len <= 8)
4432 (mode, gen_lowpart (mode, inner),
4434 GEN_INT (((HOST_WIDE_INT) 1 << len) - 1)));
4436 split = find_split_point (&SET_SRC (x), insn);
4437 if (split && split != &SET_SRC (x))
4444 (unsignedp ? LSHIFTRT : ASHIFTRT, mode,
4445 gen_rtx_ASHIFT (mode,
4446 gen_lowpart (mode, inner),
4447 GEN_INT (GET_MODE_BITSIZE (mode)
4449 GEN_INT (GET_MODE_BITSIZE (mode) - len)));
4451 split = find_split_point (&SET_SRC (x), insn);
4452 if (split && split != &SET_SRC (x))
4457 /* See if this is a simple operation with a constant as the second
4458 operand. It might be that this constant is out of range and hence
4459 could be used as a split point. */
4460 if (BINARY_P (SET_SRC (x))
4461 && CONSTANT_P (XEXP (SET_SRC (x), 1))
4462 && (OBJECT_P (XEXP (SET_SRC (x), 0))
4463 || (GET_CODE (XEXP (SET_SRC (x), 0)) == SUBREG
4464 && OBJECT_P (SUBREG_REG (XEXP (SET_SRC (x), 0))))))
4465 return &XEXP (SET_SRC (x), 1);
4467 /* Finally, see if this is a simple operation with its first operand
4468 not in a register. The operation might require this operand in a
4469 register, so return it as a split point. We can always do this
4470 because if the first operand were another operation, we would have
4471 already found it as a split point. */
4472 if ((BINARY_P (SET_SRC (x)) || UNARY_P (SET_SRC (x)))
4473 && ! register_operand (XEXP (SET_SRC (x), 0), VOIDmode))
4474 return &XEXP (SET_SRC (x), 0);
4480 /* We write NOR as (and (not A) (not B)), but if we don't have a NOR,
4481 it is better to write this as (not (ior A B)) so we can split it.
4482 Similarly for IOR. */
4483 if (GET_CODE (XEXP (x, 0)) == NOT && GET_CODE (XEXP (x, 1)) == NOT)
4486 gen_rtx_NOT (GET_MODE (x),
4487 gen_rtx_fmt_ee (code == IOR ? AND : IOR,
4489 XEXP (XEXP (x, 0), 0),
4490 XEXP (XEXP (x, 1), 0))));
4491 return find_split_point (loc, insn);
4494 /* Many RISC machines have a large set of logical insns. If the
4495 second operand is a NOT, put it first so we will try to split the
4496 other operand first. */
4497 if (GET_CODE (XEXP (x, 1)) == NOT)
4499 rtx tem = XEXP (x, 0);
4500 SUBST (XEXP (x, 0), XEXP (x, 1));
4501 SUBST (XEXP (x, 1), tem);
4509 /* Otherwise, select our actions depending on our rtx class. */
4510 switch (GET_RTX_CLASS (code))
4512 case RTX_BITFIELD_OPS: /* This is ZERO_EXTRACT and SIGN_EXTRACT. */
4514 split = find_split_point (&XEXP (x, 2), insn);
4517 /* ... fall through ... */
4519 case RTX_COMM_ARITH:
4521 case RTX_COMM_COMPARE:
4522 split = find_split_point (&XEXP (x, 1), insn);
4525 /* ... fall through ... */
4527 /* Some machines have (and (shift ...) ...) insns. If X is not
4528 an AND, but XEXP (X, 0) is, use it as our split point. */
4529 if (GET_CODE (x) != AND && GET_CODE (XEXP (x, 0)) == AND)
4530 return &XEXP (x, 0);
4532 split = find_split_point (&XEXP (x, 0), insn);
4538 /* Otherwise, we don't have a split point. */
4543 /* Throughout X, replace FROM with TO, and return the result.
4544 The result is TO if X is FROM;
4545 otherwise the result is X, but its contents may have been modified.
4546 If they were modified, a record was made in undobuf so that
4547 undo_all will (among other things) return X to its original state.
4549 If the number of changes necessary is too much to record to undo,
4550 the excess changes are not made, so the result is invalid.
4551 The changes already made can still be undone.
4552 undobuf.num_undo is incremented for such changes, so by testing that
4553 the caller can tell whether the result is valid.
4555 `n_occurrences' is incremented each time FROM is replaced.
4557 IN_DEST is nonzero if we are processing the SET_DEST of a SET.
4559 UNIQUE_COPY is nonzero if each substitution must be unique. We do this
4560 by copying if `n_occurrences' is nonzero. */
4563 subst (rtx x, rtx from, rtx to, int in_dest, int unique_copy)
4565 enum rtx_code code = GET_CODE (x);
4566 enum machine_mode op0_mode = VOIDmode;
4571 /* Two expressions are equal if they are identical copies of a shared
4572 RTX or if they are both registers with the same register number
4575 #define COMBINE_RTX_EQUAL_P(X,Y) \
4577 || (REG_P (X) && REG_P (Y) \
4578 && REGNO (X) == REGNO (Y) && GET_MODE (X) == GET_MODE (Y)))
4580 if (! in_dest && COMBINE_RTX_EQUAL_P (x, from))
4583 return (unique_copy && n_occurrences > 1 ? copy_rtx (to) : to);
4586 /* If X and FROM are the same register but different modes, they
4587 will not have been seen as equal above. However, the log links code
4588 will make a LOG_LINKS entry for that case. If we do nothing, we
4589 will try to rerecognize our original insn and, when it succeeds,
4590 we will delete the feeding insn, which is incorrect.
4592 So force this insn not to match in this (rare) case. */
4593 if (! in_dest && code == REG && REG_P (from)
4594 && reg_overlap_mentioned_p (x, from))
4595 return gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
4597 /* If this is an object, we are done unless it is a MEM or LO_SUM, both
4598 of which may contain things that can be combined. */
4599 if (code != MEM && code != LO_SUM && OBJECT_P (x))
4602 /* It is possible to have a subexpression appear twice in the insn.
4603 Suppose that FROM is a register that appears within TO.
4604 Then, after that subexpression has been scanned once by `subst',
4605 the second time it is scanned, TO may be found. If we were
4606 to scan TO here, we would find FROM within it and create a
4607 self-referent rtl structure which is completely wrong. */
4608 if (COMBINE_RTX_EQUAL_P (x, to))
4611 /* Parallel asm_operands need special attention because all of the
4612 inputs are shared across the arms. Furthermore, unsharing the
4613 rtl results in recognition failures. Failure to handle this case
4614 specially can result in circular rtl.
4616 Solve this by doing a normal pass across the first entry of the
4617 parallel, and only processing the SET_DESTs of the subsequent
4620 if (code == PARALLEL
4621 && GET_CODE (XVECEXP (x, 0, 0)) == SET
4622 && GET_CODE (SET_SRC (XVECEXP (x, 0, 0))) == ASM_OPERANDS)
4624 new_rtx = subst (XVECEXP (x, 0, 0), from, to, 0, unique_copy);
4626 /* If this substitution failed, this whole thing fails. */
4627 if (GET_CODE (new_rtx) == CLOBBER
4628 && XEXP (new_rtx, 0) == const0_rtx)
4631 SUBST (XVECEXP (x, 0, 0), new_rtx);
4633 for (i = XVECLEN (x, 0) - 1; i >= 1; i--)
4635 rtx dest = SET_DEST (XVECEXP (x, 0, i));
4638 && GET_CODE (dest) != CC0
4639 && GET_CODE (dest) != PC)
4641 new_rtx = subst (dest, from, to, 0, unique_copy);
4643 /* If this substitution failed, this whole thing fails. */
4644 if (GET_CODE (new_rtx) == CLOBBER
4645 && XEXP (new_rtx, 0) == const0_rtx)
4648 SUBST (SET_DEST (XVECEXP (x, 0, i)), new_rtx);
4654 len = GET_RTX_LENGTH (code);
4655 fmt = GET_RTX_FORMAT (code);
4657 /* We don't need to process a SET_DEST that is a register, CC0,
4658 or PC, so set up to skip this common case. All other cases
4659 where we want to suppress replacing something inside a
4660 SET_SRC are handled via the IN_DEST operand. */
4662 && (REG_P (SET_DEST (x))
4663 || GET_CODE (SET_DEST (x)) == CC0
4664 || GET_CODE (SET_DEST (x)) == PC))
4667 /* Get the mode of operand 0 in case X is now a SIGN_EXTEND of a
4670 op0_mode = GET_MODE (XEXP (x, 0));
4672 for (i = 0; i < len; i++)
4677 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
4679 if (COMBINE_RTX_EQUAL_P (XVECEXP (x, i, j), from))
4681 new_rtx = (unique_copy && n_occurrences
4682 ? copy_rtx (to) : to);
4687 new_rtx = subst (XVECEXP (x, i, j), from, to, 0,
4690 /* If this substitution failed, this whole thing
4692 if (GET_CODE (new_rtx) == CLOBBER
4693 && XEXP (new_rtx, 0) == const0_rtx)
4697 SUBST (XVECEXP (x, i, j), new_rtx);
4700 else if (fmt[i] == 'e')
4702 /* If this is a register being set, ignore it. */
4703 new_rtx = XEXP (x, i);
4706 && (((code == SUBREG || code == ZERO_EXTRACT)
4708 || code == STRICT_LOW_PART))
4711 else if (COMBINE_RTX_EQUAL_P (XEXP (x, i), from))
4713 /* In general, don't install a subreg involving two
4714 modes not tieable. It can worsen register
4715 allocation, and can even make invalid reload
4716 insns, since the reg inside may need to be copied
4717 from in the outside mode, and that may be invalid
4718 if it is an fp reg copied in integer mode.
4720 We allow two exceptions to this: It is valid if
4721 it is inside another SUBREG and the mode of that
4722 SUBREG and the mode of the inside of TO is
4723 tieable and it is valid if X is a SET that copies
4726 if (GET_CODE (to) == SUBREG
4727 && ! MODES_TIEABLE_P (GET_MODE (to),
4728 GET_MODE (SUBREG_REG (to)))
4729 && ! (code == SUBREG
4730 && MODES_TIEABLE_P (GET_MODE (x),
4731 GET_MODE (SUBREG_REG (to))))
4733 && ! (code == SET && i == 1 && XEXP (x, 0) == cc0_rtx)
4736 return gen_rtx_CLOBBER (VOIDmode, const0_rtx);
4738 #ifdef CANNOT_CHANGE_MODE_CLASS
4741 && REGNO (to) < FIRST_PSEUDO_REGISTER
4742 && REG_CANNOT_CHANGE_MODE_P (REGNO (to),
4745 return gen_rtx_CLOBBER (VOIDmode, const0_rtx);
4748 new_rtx = (unique_copy && n_occurrences ? copy_rtx (to) : to);
4752 /* If we are in a SET_DEST, suppress most cases unless we
4753 have gone inside a MEM, in which case we want to
4754 simplify the address. We assume here that things that
4755 are actually part of the destination have their inner
4756 parts in the first expression. This is true for SUBREG,
4757 STRICT_LOW_PART, and ZERO_EXTRACT, which are the only
4758 things aside from REG and MEM that should appear in a
4760 new_rtx = subst (XEXP (x, i), from, to,
4762 && (code == SUBREG || code == STRICT_LOW_PART
4763 || code == ZERO_EXTRACT))
4765 && i == 0), unique_copy);
4767 /* If we found that we will have to reject this combination,
4768 indicate that by returning the CLOBBER ourselves, rather than
4769 an expression containing it. This will speed things up as
4770 well as prevent accidents where two CLOBBERs are considered
4771 to be equal, thus producing an incorrect simplification. */
4773 if (GET_CODE (new_rtx) == CLOBBER && XEXP (new_rtx, 0) == const0_rtx)
4776 if (GET_CODE (x) == SUBREG
4777 && (CONST_INT_P (new_rtx)
4778 || GET_CODE (new_rtx) == CONST_DOUBLE))
4780 enum machine_mode mode = GET_MODE (x);
4782 x = simplify_subreg (GET_MODE (x), new_rtx,
4783 GET_MODE (SUBREG_REG (x)),
4786 x = gen_rtx_CLOBBER (mode, const0_rtx);
4788 else if (CONST_INT_P (new_rtx)
4789 && GET_CODE (x) == ZERO_EXTEND)
4791 x = simplify_unary_operation (ZERO_EXTEND, GET_MODE (x),
4792 new_rtx, GET_MODE (XEXP (x, 0)));
4796 SUBST (XEXP (x, i), new_rtx);
4801 /* Check if we are loading something from the constant pool via float
4802 extension; in this case we would undo compress_float_constant
4803 optimization and degenerate constant load to an immediate value. */
4804 if (GET_CODE (x) == FLOAT_EXTEND
4805 && MEM_P (XEXP (x, 0))
4806 && MEM_READONLY_P (XEXP (x, 0)))
4808 rtx tmp = avoid_constant_pool_reference (x);
4813 /* Try to simplify X. If the simplification changed the code, it is likely
4814 that further simplification will help, so loop, but limit the number
4815 of repetitions that will be performed. */
4817 for (i = 0; i < 4; i++)
4819 /* If X is sufficiently simple, don't bother trying to do anything
4821 if (code != CONST_INT && code != REG && code != CLOBBER)
4822 x = combine_simplify_rtx (x, op0_mode, in_dest);
4824 if (GET_CODE (x) == code)
4827 code = GET_CODE (x);
4829 /* We no longer know the original mode of operand 0 since we
4830 have changed the form of X) */
4831 op0_mode = VOIDmode;
4837 /* Simplify X, a piece of RTL. We just operate on the expression at the
4838 outer level; call `subst' to simplify recursively. Return the new
4841 OP0_MODE is the original mode of XEXP (x, 0). IN_DEST is nonzero
4842 if we are inside a SET_DEST. */
4845 combine_simplify_rtx (rtx x, enum machine_mode op0_mode, int in_dest)
4847 enum rtx_code code = GET_CODE (x);
4848 enum machine_mode mode = GET_MODE (x);
4852 /* If this is a commutative operation, put a constant last and a complex
4853 expression first. We don't need to do this for comparisons here. */
4854 if (COMMUTATIVE_ARITH_P (x)
4855 && swap_commutative_operands_p (XEXP (x, 0), XEXP (x, 1)))
4858 SUBST (XEXP (x, 0), XEXP (x, 1));
4859 SUBST (XEXP (x, 1), temp);
4862 /* If this is a simple operation applied to an IF_THEN_ELSE, try
4863 applying it to the arms of the IF_THEN_ELSE. This often simplifies
4864 things. Check for cases where both arms are testing the same
4867 Don't do anything if all operands are very simple. */
4870 && ((!OBJECT_P (XEXP (x, 0))
4871 && ! (GET_CODE (XEXP (x, 0)) == SUBREG
4872 && OBJECT_P (SUBREG_REG (XEXP (x, 0)))))
4873 || (!OBJECT_P (XEXP (x, 1))
4874 && ! (GET_CODE (XEXP (x, 1)) == SUBREG
4875 && OBJECT_P (SUBREG_REG (XEXP (x, 1)))))))
4877 && (!OBJECT_P (XEXP (x, 0))
4878 && ! (GET_CODE (XEXP (x, 0)) == SUBREG
4879 && OBJECT_P (SUBREG_REG (XEXP (x, 0)))))))
4881 rtx cond, true_rtx, false_rtx;
4883 cond = if_then_else_cond (x, &true_rtx, &false_rtx);
4885 /* If everything is a comparison, what we have is highly unlikely
4886 to be simpler, so don't use it. */
4887 && ! (COMPARISON_P (x)
4888 && (COMPARISON_P (true_rtx) || COMPARISON_P (false_rtx))))
4890 rtx cop1 = const0_rtx;
4891 enum rtx_code cond_code = simplify_comparison (NE, &cond, &cop1);
4893 if (cond_code == NE && COMPARISON_P (cond))
4896 /* Simplify the alternative arms; this may collapse the true and
4897 false arms to store-flag values. Be careful to use copy_rtx
4898 here since true_rtx or false_rtx might share RTL with x as a
4899 result of the if_then_else_cond call above. */
4900 true_rtx = subst (copy_rtx (true_rtx), pc_rtx, pc_rtx, 0, 0);
4901 false_rtx = subst (copy_rtx (false_rtx), pc_rtx, pc_rtx, 0, 0);
4903 /* If true_rtx and false_rtx are not general_operands, an if_then_else
4904 is unlikely to be simpler. */
4905 if (general_operand (true_rtx, VOIDmode)
4906 && general_operand (false_rtx, VOIDmode))
4908 enum rtx_code reversed;
4910 /* Restarting if we generate a store-flag expression will cause
4911 us to loop. Just drop through in this case. */
4913 /* If the result values are STORE_FLAG_VALUE and zero, we can
4914 just make the comparison operation. */
4915 if (true_rtx == const_true_rtx && false_rtx == const0_rtx)
4916 x = simplify_gen_relational (cond_code, mode, VOIDmode,
4918 else if (true_rtx == const0_rtx && false_rtx == const_true_rtx
4919 && ((reversed = reversed_comparison_code_parts
4920 (cond_code, cond, cop1, NULL))
4922 x = simplify_gen_relational (reversed, mode, VOIDmode,
4925 /* Likewise, we can make the negate of a comparison operation
4926 if the result values are - STORE_FLAG_VALUE and zero. */
4927 else if (CONST_INT_P (true_rtx)
4928 && INTVAL (true_rtx) == - STORE_FLAG_VALUE
4929 && false_rtx == const0_rtx)
4930 x = simplify_gen_unary (NEG, mode,
4931 simplify_gen_relational (cond_code,
4935 else if (CONST_INT_P (false_rtx)
4936 && INTVAL (false_rtx) == - STORE_FLAG_VALUE
4937 && true_rtx == const0_rtx
4938 && ((reversed = reversed_comparison_code_parts
4939 (cond_code, cond, cop1, NULL))
4941 x = simplify_gen_unary (NEG, mode,
4942 simplify_gen_relational (reversed,
4947 return gen_rtx_IF_THEN_ELSE (mode,
4948 simplify_gen_relational (cond_code,
4953 true_rtx, false_rtx);
4955 code = GET_CODE (x);
4956 op0_mode = VOIDmode;
4961 /* Try to fold this expression in case we have constants that weren't
4964 switch (GET_RTX_CLASS (code))
4967 if (op0_mode == VOIDmode)
4968 op0_mode = GET_MODE (XEXP (x, 0));
4969 temp = simplify_unary_operation (code, mode, XEXP (x, 0), op0_mode);
4972 case RTX_COMM_COMPARE:
4974 enum machine_mode cmp_mode = GET_MODE (XEXP (x, 0));
4975 if (cmp_mode == VOIDmode)
4977 cmp_mode = GET_MODE (XEXP (x, 1));
4978 if (cmp_mode == VOIDmode)
4979 cmp_mode = op0_mode;
4981 temp = simplify_relational_operation (code, mode, cmp_mode,
4982 XEXP (x, 0), XEXP (x, 1));
4985 case RTX_COMM_ARITH:
4987 temp = simplify_binary_operation (code, mode, XEXP (x, 0), XEXP (x, 1));
4989 case RTX_BITFIELD_OPS:
4991 temp = simplify_ternary_operation (code, mode, op0_mode, XEXP (x, 0),
4992 XEXP (x, 1), XEXP (x, 2));
5001 code = GET_CODE (temp);
5002 op0_mode = VOIDmode;
5003 mode = GET_MODE (temp);
5006 /* First see if we can apply the inverse distributive law. */
5007 if (code == PLUS || code == MINUS
5008 || code == AND || code == IOR || code == XOR)
5010 x = apply_distributive_law (x);
5011 code = GET_CODE (x);
5012 op0_mode = VOIDmode;
5015 /* If CODE is an associative operation not otherwise handled, see if we
5016 can associate some operands. This can win if they are constants or
5017 if they are logically related (i.e. (a & b) & a). */
5018 if ((code == PLUS || code == MINUS || code == MULT || code == DIV
5019 || code == AND || code == IOR || code == XOR
5020 || code == SMAX || code == SMIN || code == UMAX || code == UMIN)
5021 && ((INTEGRAL_MODE_P (mode) && code != DIV)
5022 || (flag_associative_math && FLOAT_MODE_P (mode))))
5024 if (GET_CODE (XEXP (x, 0)) == code)
5026 rtx other = XEXP (XEXP (x, 0), 0);
5027 rtx inner_op0 = XEXP (XEXP (x, 0), 1);
5028 rtx inner_op1 = XEXP (x, 1);
5031 /* Make sure we pass the constant operand if any as the second
5032 one if this is a commutative operation. */
5033 if (CONSTANT_P (inner_op0) && COMMUTATIVE_ARITH_P (x))
5035 rtx tem = inner_op0;
5036 inner_op0 = inner_op1;
5039 inner = simplify_binary_operation (code == MINUS ? PLUS
5040 : code == DIV ? MULT
5042 mode, inner_op0, inner_op1);
5044 /* For commutative operations, try the other pair if that one
5046 if (inner == 0 && COMMUTATIVE_ARITH_P (x))
5048 other = XEXP (XEXP (x, 0), 1);
5049 inner = simplify_binary_operation (code, mode,
5050 XEXP (XEXP (x, 0), 0),
5055 return simplify_gen_binary (code, mode, other, inner);
5059 /* A little bit of algebraic simplification here. */
5063 /* Ensure that our address has any ASHIFTs converted to MULT in case
5064 address-recognizing predicates are called later. */
5065 temp = make_compound_operation (XEXP (x, 0), MEM);
5066 SUBST (XEXP (x, 0), temp);
5070 if (op0_mode == VOIDmode)
5071 op0_mode = GET_MODE (SUBREG_REG (x));
5073 /* See if this can be moved to simplify_subreg. */
5074 if (CONSTANT_P (SUBREG_REG (x))
5075 && subreg_lowpart_offset (mode, op0_mode) == SUBREG_BYTE (x)
5076 /* Don't call gen_lowpart if the inner mode
5077 is VOIDmode and we cannot simplify it, as SUBREG without
5078 inner mode is invalid. */
5079 && (GET_MODE (SUBREG_REG (x)) != VOIDmode
5080 || gen_lowpart_common (mode, SUBREG_REG (x))))
5081 return gen_lowpart (mode, SUBREG_REG (x));
5083 if (GET_MODE_CLASS (GET_MODE (SUBREG_REG (x))) == MODE_CC)
5087 temp = simplify_subreg (mode, SUBREG_REG (x), op0_mode,
5093 /* Don't change the mode of the MEM if that would change the meaning
5095 if (MEM_P (SUBREG_REG (x))
5096 && (MEM_VOLATILE_P (SUBREG_REG (x))
5097 || mode_dependent_address_p (XEXP (SUBREG_REG (x), 0))))
5098 return gen_rtx_CLOBBER (mode, const0_rtx);
5100 /* Note that we cannot do any narrowing for non-constants since
5101 we might have been counting on using the fact that some bits were
5102 zero. We now do this in the SET. */
5107 temp = expand_compound_operation (XEXP (x, 0));
5109 /* For C equal to the width of MODE minus 1, (neg (ashiftrt X C)) can be
5110 replaced by (lshiftrt X C). This will convert
5111 (neg (sign_extract X 1 Y)) to (zero_extract X 1 Y). */
5113 if (GET_CODE (temp) == ASHIFTRT
5114 && CONST_INT_P (XEXP (temp, 1))
5115 && INTVAL (XEXP (temp, 1)) == GET_MODE_BITSIZE (mode) - 1)
5116 return simplify_shift_const (NULL_RTX, LSHIFTRT, mode, XEXP (temp, 0),
5117 INTVAL (XEXP (temp, 1)));
5119 /* If X has only a single bit that might be nonzero, say, bit I, convert
5120 (neg X) to (ashiftrt (ashift X C-I) C-I) where C is the bitsize of
5121 MODE minus 1. This will convert (neg (zero_extract X 1 Y)) to
5122 (sign_extract X 1 Y). But only do this if TEMP isn't a register
5123 or a SUBREG of one since we'd be making the expression more
5124 complex if it was just a register. */
5127 && ! (GET_CODE (temp) == SUBREG
5128 && REG_P (SUBREG_REG (temp)))
5129 && (i = exact_log2 (nonzero_bits (temp, mode))) >= 0)
5131 rtx temp1 = simplify_shift_const
5132 (NULL_RTX, ASHIFTRT, mode,
5133 simplify_shift_const (NULL_RTX, ASHIFT, mode, temp,
5134 GET_MODE_BITSIZE (mode) - 1 - i),
5135 GET_MODE_BITSIZE (mode) - 1 - i);
5137 /* If all we did was surround TEMP with the two shifts, we
5138 haven't improved anything, so don't use it. Otherwise,
5139 we are better off with TEMP1. */
5140 if (GET_CODE (temp1) != ASHIFTRT
5141 || GET_CODE (XEXP (temp1, 0)) != ASHIFT
5142 || XEXP (XEXP (temp1, 0), 0) != temp)
5148 /* We can't handle truncation to a partial integer mode here
5149 because we don't know the real bitsize of the partial
5151 if (GET_MODE_CLASS (mode) == MODE_PARTIAL_INT)
5154 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
5156 force_to_mode (XEXP (x, 0), GET_MODE (XEXP (x, 0)),
5157 GET_MODE_MASK (mode), 0));
5159 /* We can truncate a constant value and return it. */
5160 if (CONST_INT_P (XEXP (x, 0)))
5161 return gen_int_mode (INTVAL (XEXP (x, 0)), mode);
5163 /* Similarly to what we do in simplify-rtx.c, a truncate of a register
5164 whose value is a comparison can be replaced with a subreg if
5165 STORE_FLAG_VALUE permits. */
5166 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5167 && ((HOST_WIDE_INT) STORE_FLAG_VALUE & ~GET_MODE_MASK (mode)) == 0
5168 && (temp = get_last_value (XEXP (x, 0)))
5169 && COMPARISON_P (temp))
5170 return gen_lowpart (mode, XEXP (x, 0));
5174 /* (const (const X)) can become (const X). Do it this way rather than
5175 returning the inner CONST since CONST can be shared with a
5177 if (GET_CODE (XEXP (x, 0)) == CONST)
5178 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
5183 /* Convert (lo_sum (high FOO) FOO) to FOO. This is necessary so we
5184 can add in an offset. find_split_point will split this address up
5185 again if it doesn't match. */
5186 if (GET_CODE (XEXP (x, 0)) == HIGH
5187 && rtx_equal_p (XEXP (XEXP (x, 0), 0), XEXP (x, 1)))
5193 /* (plus (xor (and <foo> (const_int pow2 - 1)) <c>) <-c>)
5194 when c is (const_int (pow2 + 1) / 2) is a sign extension of a
5195 bit-field and can be replaced by either a sign_extend or a
5196 sign_extract. The `and' may be a zero_extend and the two
5197 <c>, -<c> constants may be reversed. */
5198 if (GET_CODE (XEXP (x, 0)) == XOR
5199 && CONST_INT_P (XEXP (x, 1))
5200 && CONST_INT_P (XEXP (XEXP (x, 0), 1))
5201 && INTVAL (XEXP (x, 1)) == -INTVAL (XEXP (XEXP (x, 0), 1))
5202 && ((i = exact_log2 (INTVAL (XEXP (XEXP (x, 0), 1)))) >= 0
5203 || (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0)
5204 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5205 && ((GET_CODE (XEXP (XEXP (x, 0), 0)) == AND
5206 && CONST_INT_P (XEXP (XEXP (XEXP (x, 0), 0), 1))
5207 && (INTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1))
5208 == ((HOST_WIDE_INT) 1 << (i + 1)) - 1))
5209 || (GET_CODE (XEXP (XEXP (x, 0), 0)) == ZERO_EXTEND
5210 && (GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)))
5211 == (unsigned int) i + 1))))
5212 return simplify_shift_const
5213 (NULL_RTX, ASHIFTRT, mode,
5214 simplify_shift_const (NULL_RTX, ASHIFT, mode,
5215 XEXP (XEXP (XEXP (x, 0), 0), 0),
5216 GET_MODE_BITSIZE (mode) - (i + 1)),
5217 GET_MODE_BITSIZE (mode) - (i + 1));
5219 /* If only the low-order bit of X is possibly nonzero, (plus x -1)
5220 can become (ashiftrt (ashift (xor x 1) C) C) where C is
5221 the bitsize of the mode - 1. This allows simplification of
5222 "a = (b & 8) == 0;" */
5223 if (XEXP (x, 1) == constm1_rtx
5224 && !REG_P (XEXP (x, 0))
5225 && ! (GET_CODE (XEXP (x, 0)) == SUBREG
5226 && REG_P (SUBREG_REG (XEXP (x, 0))))
5227 && nonzero_bits (XEXP (x, 0), mode) == 1)
5228 return simplify_shift_const (NULL_RTX, ASHIFTRT, mode,
5229 simplify_shift_const (NULL_RTX, ASHIFT, mode,
5230 gen_rtx_XOR (mode, XEXP (x, 0), const1_rtx),
5231 GET_MODE_BITSIZE (mode) - 1),
5232 GET_MODE_BITSIZE (mode) - 1);
5234 /* If we are adding two things that have no bits in common, convert
5235 the addition into an IOR. This will often be further simplified,
5236 for example in cases like ((a & 1) + (a & 2)), which can
5239 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5240 && (nonzero_bits (XEXP (x, 0), mode)
5241 & nonzero_bits (XEXP (x, 1), mode)) == 0)
5243 /* Try to simplify the expression further. */
5244 rtx tor = simplify_gen_binary (IOR, mode, XEXP (x, 0), XEXP (x, 1));
5245 temp = combine_simplify_rtx (tor, mode, in_dest);
5247 /* If we could, great. If not, do not go ahead with the IOR
5248 replacement, since PLUS appears in many special purpose
5249 address arithmetic instructions. */
5250 if (GET_CODE (temp) != CLOBBER && temp != tor)
5256 /* (minus <foo> (and <foo> (const_int -pow2))) becomes
5257 (and <foo> (const_int pow2-1)) */
5258 if (GET_CODE (XEXP (x, 1)) == AND
5259 && CONST_INT_P (XEXP (XEXP (x, 1), 1))
5260 && exact_log2 (-INTVAL (XEXP (XEXP (x, 1), 1))) >= 0
5261 && rtx_equal_p (XEXP (XEXP (x, 1), 0), XEXP (x, 0)))
5262 return simplify_and_const_int (NULL_RTX, mode, XEXP (x, 0),
5263 -INTVAL (XEXP (XEXP (x, 1), 1)) - 1);
5267 /* If we have (mult (plus A B) C), apply the distributive law and then
5268 the inverse distributive law to see if things simplify. This
5269 occurs mostly in addresses, often when unrolling loops. */
5271 if (GET_CODE (XEXP (x, 0)) == PLUS)
5273 rtx result = distribute_and_simplify_rtx (x, 0);
5278 /* Try simplify a*(b/c) as (a*b)/c. */
5279 if (FLOAT_MODE_P (mode) && flag_associative_math
5280 && GET_CODE (XEXP (x, 0)) == DIV)
5282 rtx tem = simplify_binary_operation (MULT, mode,
5283 XEXP (XEXP (x, 0), 0),
5286 return simplify_gen_binary (DIV, mode, tem, XEXP (XEXP (x, 0), 1));
5291 /* If this is a divide by a power of two, treat it as a shift if
5292 its first operand is a shift. */
5293 if (CONST_INT_P (XEXP (x, 1))
5294 && (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0
5295 && (GET_CODE (XEXP (x, 0)) == ASHIFT
5296 || GET_CODE (XEXP (x, 0)) == LSHIFTRT
5297 || GET_CODE (XEXP (x, 0)) == ASHIFTRT
5298 || GET_CODE (XEXP (x, 0)) == ROTATE
5299 || GET_CODE (XEXP (x, 0)) == ROTATERT))
5300 return simplify_shift_const (NULL_RTX, LSHIFTRT, mode, XEXP (x, 0), i);
5304 case GT: case GTU: case GE: case GEU:
5305 case LT: case LTU: case LE: case LEU:
5306 case UNEQ: case LTGT:
5307 case UNGT: case UNGE:
5308 case UNLT: case UNLE:
5309 case UNORDERED: case ORDERED:
5310 /* If the first operand is a condition code, we can't do anything
5312 if (GET_CODE (XEXP (x, 0)) == COMPARE
5313 || (GET_MODE_CLASS (GET_MODE (XEXP (x, 0))) != MODE_CC
5314 && ! CC0_P (XEXP (x, 0))))
5316 rtx op0 = XEXP (x, 0);
5317 rtx op1 = XEXP (x, 1);
5318 enum rtx_code new_code;
5320 if (GET_CODE (op0) == COMPARE)
5321 op1 = XEXP (op0, 1), op0 = XEXP (op0, 0);
5323 /* Simplify our comparison, if possible. */
5324 new_code = simplify_comparison (code, &op0, &op1);
5326 /* If STORE_FLAG_VALUE is 1, we can convert (ne x 0) to simply X
5327 if only the low-order bit is possibly nonzero in X (such as when
5328 X is a ZERO_EXTRACT of one bit). Similarly, we can convert EQ to
5329 (xor X 1) or (minus 1 X); we use the former. Finally, if X is
5330 known to be either 0 or -1, NE becomes a NEG and EQ becomes
5333 Remove any ZERO_EXTRACT we made when thinking this was a
5334 comparison. It may now be simpler to use, e.g., an AND. If a
5335 ZERO_EXTRACT is indeed appropriate, it will be placed back by
5336 the call to make_compound_operation in the SET case. */
5338 if (STORE_FLAG_VALUE == 1
5339 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
5340 && op1 == const0_rtx
5341 && mode == GET_MODE (op0)
5342 && nonzero_bits (op0, mode) == 1)
5343 return gen_lowpart (mode,
5344 expand_compound_operation (op0));
5346 else if (STORE_FLAG_VALUE == 1
5347 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
5348 && op1 == const0_rtx
5349 && mode == GET_MODE (op0)
5350 && (num_sign_bit_copies (op0, mode)
5351 == GET_MODE_BITSIZE (mode)))
5353 op0 = expand_compound_operation (op0);
5354 return simplify_gen_unary (NEG, mode,
5355 gen_lowpart (mode, op0),
5359 else if (STORE_FLAG_VALUE == 1
5360 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
5361 && op1 == const0_rtx
5362 && mode == GET_MODE (op0)
5363 && nonzero_bits (op0, mode) == 1)
5365 op0 = expand_compound_operation (op0);
5366 return simplify_gen_binary (XOR, mode,
5367 gen_lowpart (mode, op0),
5371 else if (STORE_FLAG_VALUE == 1
5372 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
5373 && op1 == const0_rtx
5374 && mode == GET_MODE (op0)
5375 && (num_sign_bit_copies (op0, mode)
5376 == GET_MODE_BITSIZE (mode)))
5378 op0 = expand_compound_operation (op0);
5379 return plus_constant (gen_lowpart (mode, op0), 1);
5382 /* If STORE_FLAG_VALUE is -1, we have cases similar to
5384 if (STORE_FLAG_VALUE == -1
5385 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
5386 && op1 == const0_rtx
5387 && (num_sign_bit_copies (op0, mode)
5388 == GET_MODE_BITSIZE (mode)))
5389 return gen_lowpart (mode,
5390 expand_compound_operation (op0));
5392 else if (STORE_FLAG_VALUE == -1
5393 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
5394 && op1 == const0_rtx
5395 && mode == GET_MODE (op0)
5396 && nonzero_bits (op0, mode) == 1)
5398 op0 = expand_compound_operation (op0);
5399 return simplify_gen_unary (NEG, mode,
5400 gen_lowpart (mode, op0),
5404 else if (STORE_FLAG_VALUE == -1
5405 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
5406 && op1 == const0_rtx
5407 && mode == GET_MODE (op0)
5408 && (num_sign_bit_copies (op0, mode)
5409 == GET_MODE_BITSIZE (mode)))
5411 op0 = expand_compound_operation (op0);
5412 return simplify_gen_unary (NOT, mode,
5413 gen_lowpart (mode, op0),
5417 /* If X is 0/1, (eq X 0) is X-1. */
5418 else if (STORE_FLAG_VALUE == -1
5419 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
5420 && op1 == const0_rtx
5421 && mode == GET_MODE (op0)
5422 && nonzero_bits (op0, mode) == 1)
5424 op0 = expand_compound_operation (op0);
5425 return plus_constant (gen_lowpart (mode, op0), -1);
5428 /* If STORE_FLAG_VALUE says to just test the sign bit and X has just
5429 one bit that might be nonzero, we can convert (ne x 0) to
5430 (ashift x c) where C puts the bit in the sign bit. Remove any
5431 AND with STORE_FLAG_VALUE when we are done, since we are only
5432 going to test the sign bit. */
5433 if (new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
5434 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5435 && ((STORE_FLAG_VALUE & GET_MODE_MASK (mode))
5436 == (unsigned HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (mode) - 1))
5437 && op1 == const0_rtx
5438 && mode == GET_MODE (op0)
5439 && (i = exact_log2 (nonzero_bits (op0, mode))) >= 0)
5441 x = simplify_shift_const (NULL_RTX, ASHIFT, mode,
5442 expand_compound_operation (op0),
5443 GET_MODE_BITSIZE (mode) - 1 - i);
5444 if (GET_CODE (x) == AND && XEXP (x, 1) == const_true_rtx)
5450 /* If the code changed, return a whole new comparison. */
5451 if (new_code != code)
5452 return gen_rtx_fmt_ee (new_code, mode, op0, op1);
5454 /* Otherwise, keep this operation, but maybe change its operands.
5455 This also converts (ne (compare FOO BAR) 0) to (ne FOO BAR). */
5456 SUBST (XEXP (x, 0), op0);
5457 SUBST (XEXP (x, 1), op1);
5462 return simplify_if_then_else (x);
5468 /* If we are processing SET_DEST, we are done. */
5472 return expand_compound_operation (x);
5475 return simplify_set (x);
5479 return simplify_logical (x);
5486 /* If this is a shift by a constant amount, simplify it. */
5487 if (CONST_INT_P (XEXP (x, 1)))
5488 return simplify_shift_const (x, code, mode, XEXP (x, 0),
5489 INTVAL (XEXP (x, 1)));
5491 else if (SHIFT_COUNT_TRUNCATED && !REG_P (XEXP (x, 1)))
5493 force_to_mode (XEXP (x, 1), GET_MODE (XEXP (x, 1)),
5495 << exact_log2 (GET_MODE_BITSIZE (GET_MODE (x))))
5507 /* Simplify X, an IF_THEN_ELSE expression. Return the new expression. */
5510 simplify_if_then_else (rtx x)
5512 enum machine_mode mode = GET_MODE (x);
5513 rtx cond = XEXP (x, 0);
5514 rtx true_rtx = XEXP (x, 1);
5515 rtx false_rtx = XEXP (x, 2);
5516 enum rtx_code true_code = GET_CODE (cond);
5517 int comparison_p = COMPARISON_P (cond);
5520 enum rtx_code false_code;
5523 /* Simplify storing of the truth value. */
5524 if (comparison_p && true_rtx == const_true_rtx && false_rtx == const0_rtx)
5525 return simplify_gen_relational (true_code, mode, VOIDmode,
5526 XEXP (cond, 0), XEXP (cond, 1));
5528 /* Also when the truth value has to be reversed. */
5530 && true_rtx == const0_rtx && false_rtx == const_true_rtx
5531 && (reversed = reversed_comparison (cond, mode)))
5534 /* Sometimes we can simplify the arm of an IF_THEN_ELSE if a register used
5535 in it is being compared against certain values. Get the true and false
5536 comparisons and see if that says anything about the value of each arm. */
5539 && ((false_code = reversed_comparison_code (cond, NULL))
5541 && REG_P (XEXP (cond, 0)))
5544 rtx from = XEXP (cond, 0);
5545 rtx true_val = XEXP (cond, 1);
5546 rtx false_val = true_val;
5549 /* If FALSE_CODE is EQ, swap the codes and arms. */
5551 if (false_code == EQ)
5553 swapped = 1, true_code = EQ, false_code = NE;
5554 temp = true_rtx, true_rtx = false_rtx, false_rtx = temp;
5557 /* If we are comparing against zero and the expression being tested has
5558 only a single bit that might be nonzero, that is its value when it is
5559 not equal to zero. Similarly if it is known to be -1 or 0. */
5561 if (true_code == EQ && true_val == const0_rtx
5562 && exact_log2 (nzb = nonzero_bits (from, GET_MODE (from))) >= 0)
5565 false_val = GEN_INT (trunc_int_for_mode (nzb, GET_MODE (from)));
5567 else if (true_code == EQ && true_val == const0_rtx
5568 && (num_sign_bit_copies (from, GET_MODE (from))
5569 == GET_MODE_BITSIZE (GET_MODE (from))))
5572 false_val = constm1_rtx;
5575 /* Now simplify an arm if we know the value of the register in the
5576 branch and it is used in the arm. Be careful due to the potential
5577 of locally-shared RTL. */
5579 if (reg_mentioned_p (from, true_rtx))
5580 true_rtx = subst (known_cond (copy_rtx (true_rtx), true_code,
5582 pc_rtx, pc_rtx, 0, 0);
5583 if (reg_mentioned_p (from, false_rtx))
5584 false_rtx = subst (known_cond (copy_rtx (false_rtx), false_code,
5586 pc_rtx, pc_rtx, 0, 0);
5588 SUBST (XEXP (x, 1), swapped ? false_rtx : true_rtx);
5589 SUBST (XEXP (x, 2), swapped ? true_rtx : false_rtx);
5591 true_rtx = XEXP (x, 1);
5592 false_rtx = XEXP (x, 2);
5593 true_code = GET_CODE (cond);
5596 /* If we have (if_then_else FOO (pc) (label_ref BAR)) and FOO can be
5597 reversed, do so to avoid needing two sets of patterns for
5598 subtract-and-branch insns. Similarly if we have a constant in the true
5599 arm, the false arm is the same as the first operand of the comparison, or
5600 the false arm is more complicated than the true arm. */
5603 && reversed_comparison_code (cond, NULL) != UNKNOWN
5604 && (true_rtx == pc_rtx
5605 || (CONSTANT_P (true_rtx)
5606 && !CONST_INT_P (false_rtx) && false_rtx != pc_rtx)
5607 || true_rtx == const0_rtx
5608 || (OBJECT_P (true_rtx) && !OBJECT_P (false_rtx))
5609 || (GET_CODE (true_rtx) == SUBREG && OBJECT_P (SUBREG_REG (true_rtx))
5610 && !OBJECT_P (false_rtx))
5611 || reg_mentioned_p (true_rtx, false_rtx)
5612 || rtx_equal_p (false_rtx, XEXP (cond, 0))))
5614 true_code = reversed_comparison_code (cond, NULL);
5615 SUBST (XEXP (x, 0), reversed_comparison (cond, GET_MODE (cond)));
5616 SUBST (XEXP (x, 1), false_rtx);
5617 SUBST (XEXP (x, 2), true_rtx);
5619 temp = true_rtx, true_rtx = false_rtx, false_rtx = temp;
5622 /* It is possible that the conditional has been simplified out. */
5623 true_code = GET_CODE (cond);
5624 comparison_p = COMPARISON_P (cond);
5627 /* If the two arms are identical, we don't need the comparison. */
5629 if (rtx_equal_p (true_rtx, false_rtx) && ! side_effects_p (cond))
5632 /* Convert a == b ? b : a to "a". */
5633 if (true_code == EQ && ! side_effects_p (cond)
5634 && !HONOR_NANS (mode)
5635 && rtx_equal_p (XEXP (cond, 0), false_rtx)
5636 && rtx_equal_p (XEXP (cond, 1), true_rtx))
5638 else if (true_code == NE && ! side_effects_p (cond)
5639 && !HONOR_NANS (mode)
5640 && rtx_equal_p (XEXP (cond, 0), true_rtx)
5641 && rtx_equal_p (XEXP (cond, 1), false_rtx))
5644 /* Look for cases where we have (abs x) or (neg (abs X)). */
5646 if (GET_MODE_CLASS (mode) == MODE_INT
5648 && XEXP (cond, 1) == const0_rtx
5649 && GET_CODE (false_rtx) == NEG
5650 && rtx_equal_p (true_rtx, XEXP (false_rtx, 0))
5651 && rtx_equal_p (true_rtx, XEXP (cond, 0))
5652 && ! side_effects_p (true_rtx))
5657 return simplify_gen_unary (ABS, mode, true_rtx, mode);
5661 simplify_gen_unary (NEG, mode,
5662 simplify_gen_unary (ABS, mode, true_rtx, mode),
5668 /* Look for MIN or MAX. */
5670 if ((! FLOAT_MODE_P (mode) || flag_unsafe_math_optimizations)
5672 && rtx_equal_p (XEXP (cond, 0), true_rtx)
5673 && rtx_equal_p (XEXP (cond, 1), false_rtx)
5674 && ! side_effects_p (cond))
5679 return simplify_gen_binary (SMAX, mode, true_rtx, false_rtx);
5682 return simplify_gen_binary (SMIN, mode, true_rtx, false_rtx);
5685 return simplify_gen_binary (UMAX, mode, true_rtx, false_rtx);
5688 return simplify_gen_binary (UMIN, mode, true_rtx, false_rtx);
5693 /* If we have (if_then_else COND (OP Z C1) Z) and OP is an identity when its
5694 second operand is zero, this can be done as (OP Z (mult COND C2)) where
5695 C2 = C1 * STORE_FLAG_VALUE. Similarly if OP has an outer ZERO_EXTEND or
5696 SIGN_EXTEND as long as Z is already extended (so we don't destroy it).
5697 We can do this kind of thing in some cases when STORE_FLAG_VALUE is
5698 neither 1 or -1, but it isn't worth checking for. */
5700 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
5702 && GET_MODE_CLASS (mode) == MODE_INT
5703 && ! side_effects_p (x))
5705 rtx t = make_compound_operation (true_rtx, SET);
5706 rtx f = make_compound_operation (false_rtx, SET);
5707 rtx cond_op0 = XEXP (cond, 0);
5708 rtx cond_op1 = XEXP (cond, 1);
5709 enum rtx_code op = UNKNOWN, extend_op = UNKNOWN;
5710 enum machine_mode m = mode;
5711 rtx z = 0, c1 = NULL_RTX;
5713 if ((GET_CODE (t) == PLUS || GET_CODE (t) == MINUS
5714 || GET_CODE (t) == IOR || GET_CODE (t) == XOR
5715 || GET_CODE (t) == ASHIFT
5716 || GET_CODE (t) == LSHIFTRT || GET_CODE (t) == ASHIFTRT)
5717 && rtx_equal_p (XEXP (t, 0), f))
5718 c1 = XEXP (t, 1), op = GET_CODE (t), z = f;
5720 /* If an identity-zero op is commutative, check whether there
5721 would be a match if we swapped the operands. */
5722 else if ((GET_CODE (t) == PLUS || GET_CODE (t) == IOR
5723 || GET_CODE (t) == XOR)
5724 && rtx_equal_p (XEXP (t, 1), f))
5725 c1 = XEXP (t, 0), op = GET_CODE (t), z = f;
5726 else if (GET_CODE (t) == SIGN_EXTEND
5727 && (GET_CODE (XEXP (t, 0)) == PLUS
5728 || GET_CODE (XEXP (t, 0)) == MINUS
5729 || GET_CODE (XEXP (t, 0)) == IOR
5730 || GET_CODE (XEXP (t, 0)) == XOR
5731 || GET_CODE (XEXP (t, 0)) == ASHIFT
5732 || GET_CODE (XEXP (t, 0)) == LSHIFTRT
5733 || GET_CODE (XEXP (t, 0)) == ASHIFTRT)
5734 && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG
5735 && subreg_lowpart_p (XEXP (XEXP (t, 0), 0))
5736 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f)
5737 && (num_sign_bit_copies (f, GET_MODE (f))
5739 (GET_MODE_BITSIZE (mode)
5740 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t, 0), 0))))))
5742 c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0));
5743 extend_op = SIGN_EXTEND;
5744 m = GET_MODE (XEXP (t, 0));
5746 else if (GET_CODE (t) == SIGN_EXTEND
5747 && (GET_CODE (XEXP (t, 0)) == PLUS
5748 || GET_CODE (XEXP (t, 0)) == IOR
5749 || GET_CODE (XEXP (t, 0)) == XOR)
5750 && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG
5751 && subreg_lowpart_p (XEXP (XEXP (t, 0), 1))
5752 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f)
5753 && (num_sign_bit_copies (f, GET_MODE (f))
5755 (GET_MODE_BITSIZE (mode)
5756 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t, 0), 1))))))
5758 c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0));
5759 extend_op = SIGN_EXTEND;
5760 m = GET_MODE (XEXP (t, 0));
5762 else if (GET_CODE (t) == ZERO_EXTEND
5763 && (GET_CODE (XEXP (t, 0)) == PLUS
5764 || GET_CODE (XEXP (t, 0)) == MINUS
5765 || GET_CODE (XEXP (t, 0)) == IOR
5766 || GET_CODE (XEXP (t, 0)) == XOR
5767 || GET_CODE (XEXP (t, 0)) == ASHIFT
5768 || GET_CODE (XEXP (t, 0)) == LSHIFTRT
5769 || GET_CODE (XEXP (t, 0)) == ASHIFTRT)
5770 && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG
5771 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5772 && subreg_lowpart_p (XEXP (XEXP (t, 0), 0))
5773 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f)
5774 && ((nonzero_bits (f, GET_MODE (f))
5775 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t, 0), 0))))
5778 c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0));
5779 extend_op = ZERO_EXTEND;
5780 m = GET_MODE (XEXP (t, 0));
5782 else if (GET_CODE (t) == ZERO_EXTEND
5783 && (GET_CODE (XEXP (t, 0)) == PLUS
5784 || GET_CODE (XEXP (t, 0)) == IOR
5785 || GET_CODE (XEXP (t, 0)) == XOR)
5786 && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG
5787 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5788 && subreg_lowpart_p (XEXP (XEXP (t, 0), 1))
5789 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f)
5790 && ((nonzero_bits (f, GET_MODE (f))
5791 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t, 0), 1))))
5794 c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0));
5795 extend_op = ZERO_EXTEND;
5796 m = GET_MODE (XEXP (t, 0));
5801 temp = subst (simplify_gen_relational (true_code, m, VOIDmode,
5802 cond_op0, cond_op1),
5803 pc_rtx, pc_rtx, 0, 0);
5804 temp = simplify_gen_binary (MULT, m, temp,
5805 simplify_gen_binary (MULT, m, c1,
5807 temp = subst (temp, pc_rtx, pc_rtx, 0, 0);
5808 temp = simplify_gen_binary (op, m, gen_lowpart (m, z), temp);
5810 if (extend_op != UNKNOWN)
5811 temp = simplify_gen_unary (extend_op, mode, temp, m);
5817 /* If we have (if_then_else (ne A 0) C1 0) and either A is known to be 0 or
5818 1 and C1 is a single bit or A is known to be 0 or -1 and C1 is the
5819 negation of a single bit, we can convert this operation to a shift. We
5820 can actually do this more generally, but it doesn't seem worth it. */
5822 if (true_code == NE && XEXP (cond, 1) == const0_rtx
5823 && false_rtx == const0_rtx && CONST_INT_P (true_rtx)
5824 && ((1 == nonzero_bits (XEXP (cond, 0), mode)
5825 && (i = exact_log2 (INTVAL (true_rtx))) >= 0)
5826 || ((num_sign_bit_copies (XEXP (cond, 0), mode)
5827 == GET_MODE_BITSIZE (mode))
5828 && (i = exact_log2 (-INTVAL (true_rtx))) >= 0)))
5830 simplify_shift_const (NULL_RTX, ASHIFT, mode,
5831 gen_lowpart (mode, XEXP (cond, 0)), i);
5833 /* (IF_THEN_ELSE (NE REG 0) (0) (8)) is REG for nonzero_bits (REG) == 8. */
5834 if (true_code == NE && XEXP (cond, 1) == const0_rtx
5835 && false_rtx == const0_rtx && CONST_INT_P (true_rtx)
5836 && GET_MODE (XEXP (cond, 0)) == mode
5837 && (INTVAL (true_rtx) & GET_MODE_MASK (mode))
5838 == nonzero_bits (XEXP (cond, 0), mode)
5839 && (i = exact_log2 (INTVAL (true_rtx) & GET_MODE_MASK (mode))) >= 0)
5840 return XEXP (cond, 0);
5845 /* Simplify X, a SET expression. Return the new expression. */
5848 simplify_set (rtx x)
5850 rtx src = SET_SRC (x);
5851 rtx dest = SET_DEST (x);
5852 enum machine_mode mode
5853 = GET_MODE (src) != VOIDmode ? GET_MODE (src) : GET_MODE (dest);
5857 /* (set (pc) (return)) gets written as (return). */
5858 if (GET_CODE (dest) == PC && GET_CODE (src) == RETURN)
5861 /* Now that we know for sure which bits of SRC we are using, see if we can
5862 simplify the expression for the object knowing that we only need the
5865 if (GET_MODE_CLASS (mode) == MODE_INT
5866 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
5868 src = force_to_mode (src, mode, ~(HOST_WIDE_INT) 0, 0);
5869 SUBST (SET_SRC (x), src);
5872 /* If we are setting CC0 or if the source is a COMPARE, look for the use of
5873 the comparison result and try to simplify it unless we already have used
5874 undobuf.other_insn. */
5875 if ((GET_MODE_CLASS (mode) == MODE_CC
5876 || GET_CODE (src) == COMPARE
5878 && (cc_use = find_single_use (dest, subst_insn, &other_insn)) != 0
5879 && (undobuf.other_insn == 0 || other_insn == undobuf.other_insn)
5880 && COMPARISON_P (*cc_use)
5881 && rtx_equal_p (XEXP (*cc_use, 0), dest))
5883 enum rtx_code old_code = GET_CODE (*cc_use);
5884 enum rtx_code new_code;
5886 int other_changed = 0;
5887 enum machine_mode compare_mode = GET_MODE (dest);
5889 if (GET_CODE (src) == COMPARE)
5890 op0 = XEXP (src, 0), op1 = XEXP (src, 1);
5892 op0 = src, op1 = CONST0_RTX (GET_MODE (src));
5894 tmp = simplify_relational_operation (old_code, compare_mode, VOIDmode,
5897 new_code = old_code;
5898 else if (!CONSTANT_P (tmp))
5900 new_code = GET_CODE (tmp);
5901 op0 = XEXP (tmp, 0);
5902 op1 = XEXP (tmp, 1);
5906 rtx pat = PATTERN (other_insn);
5907 undobuf.other_insn = other_insn;
5908 SUBST (*cc_use, tmp);
5910 /* Attempt to simplify CC user. */
5911 if (GET_CODE (pat) == SET)
5913 rtx new_rtx = simplify_rtx (SET_SRC (pat));
5914 if (new_rtx != NULL_RTX)
5915 SUBST (SET_SRC (pat), new_rtx);
5918 /* Convert X into a no-op move. */
5919 SUBST (SET_DEST (x), pc_rtx);
5920 SUBST (SET_SRC (x), pc_rtx);
5924 /* Simplify our comparison, if possible. */
5925 new_code = simplify_comparison (new_code, &op0, &op1);
5927 #ifdef SELECT_CC_MODE
5928 /* If this machine has CC modes other than CCmode, check to see if we
5929 need to use a different CC mode here. */
5930 if (GET_MODE_CLASS (GET_MODE (op0)) == MODE_CC)
5931 compare_mode = GET_MODE (op0);
5933 compare_mode = SELECT_CC_MODE (new_code, op0, op1);
5936 /* If the mode changed, we have to change SET_DEST, the mode in the
5937 compare, and the mode in the place SET_DEST is used. If SET_DEST is
5938 a hard register, just build new versions with the proper mode. If it
5939 is a pseudo, we lose unless it is only time we set the pseudo, in
5940 which case we can safely change its mode. */
5941 if (compare_mode != GET_MODE (dest))
5943 if (can_change_dest_mode (dest, 0, compare_mode))
5945 unsigned int regno = REGNO (dest);
5948 if (regno < FIRST_PSEUDO_REGISTER)
5949 new_dest = gen_rtx_REG (compare_mode, regno);
5952 SUBST_MODE (regno_reg_rtx[regno], compare_mode);
5953 new_dest = regno_reg_rtx[regno];
5956 SUBST (SET_DEST (x), new_dest);
5957 SUBST (XEXP (*cc_use, 0), new_dest);
5964 #endif /* SELECT_CC_MODE */
5966 /* If the code changed, we have to build a new comparison in
5967 undobuf.other_insn. */
5968 if (new_code != old_code)
5970 int other_changed_previously = other_changed;
5971 unsigned HOST_WIDE_INT mask;
5972 rtx old_cc_use = *cc_use;
5974 SUBST (*cc_use, gen_rtx_fmt_ee (new_code, GET_MODE (*cc_use),
5978 /* If the only change we made was to change an EQ into an NE or
5979 vice versa, OP0 has only one bit that might be nonzero, and OP1
5980 is zero, check if changing the user of the condition code will
5981 produce a valid insn. If it won't, we can keep the original code
5982 in that insn by surrounding our operation with an XOR. */
5984 if (((old_code == NE && new_code == EQ)
5985 || (old_code == EQ && new_code == NE))
5986 && ! other_changed_previously && op1 == const0_rtx
5987 && GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
5988 && exact_log2 (mask = nonzero_bits (op0, GET_MODE (op0))) >= 0)
5990 rtx pat = PATTERN (other_insn), note = 0;
5992 if ((recog_for_combine (&pat, other_insn, ¬e) < 0
5993 && ! check_asm_operands (pat)))
5995 *cc_use = old_cc_use;
5998 op0 = simplify_gen_binary (XOR, GET_MODE (op0),
5999 op0, GEN_INT (mask));
6005 undobuf.other_insn = other_insn;
6007 /* Otherwise, if we didn't previously have a COMPARE in the
6008 correct mode, we need one. */
6009 if (GET_CODE (src) != COMPARE || GET_MODE (src) != compare_mode)
6011 SUBST (SET_SRC (x), gen_rtx_COMPARE (compare_mode, op0, op1));
6014 else if (GET_MODE (op0) == compare_mode && op1 == const0_rtx)
6016 SUBST (SET_SRC (x), op0);
6019 /* Otherwise, update the COMPARE if needed. */
6020 else if (XEXP (src, 0) != op0 || XEXP (src, 1) != op1)
6022 SUBST (SET_SRC (x), gen_rtx_COMPARE (compare_mode, op0, op1));
6028 /* Get SET_SRC in a form where we have placed back any
6029 compound expressions. Then do the checks below. */
6030 src = make_compound_operation (src, SET);
6031 SUBST (SET_SRC (x), src);
6034 /* If we have (set x (subreg:m1 (op:m2 ...) 0)) with OP being some operation,
6035 and X being a REG or (subreg (reg)), we may be able to convert this to
6036 (set (subreg:m2 x) (op)).
6038 We can always do this if M1 is narrower than M2 because that means that
6039 we only care about the low bits of the result.
6041 However, on machines without WORD_REGISTER_OPERATIONS defined, we cannot
6042 perform a narrower operation than requested since the high-order bits will
6043 be undefined. On machine where it is defined, this transformation is safe
6044 as long as M1 and M2 have the same number of words. */
6046 if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src)
6047 && !OBJECT_P (SUBREG_REG (src))
6048 && (((GET_MODE_SIZE (GET_MODE (src)) + (UNITS_PER_WORD - 1))
6050 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (src)))
6051 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD))
6052 #ifndef WORD_REGISTER_OPERATIONS
6053 && (GET_MODE_SIZE (GET_MODE (src))
6054 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (src))))
6056 #ifdef CANNOT_CHANGE_MODE_CLASS
6057 && ! (REG_P (dest) && REGNO (dest) < FIRST_PSEUDO_REGISTER
6058 && REG_CANNOT_CHANGE_MODE_P (REGNO (dest),
6059 GET_MODE (SUBREG_REG (src)),
6063 || (GET_CODE (dest) == SUBREG
6064 && REG_P (SUBREG_REG (dest)))))
6066 SUBST (SET_DEST (x),
6067 gen_lowpart (GET_MODE (SUBREG_REG (src)),
6069 SUBST (SET_SRC (x), SUBREG_REG (src));
6071 src = SET_SRC (x), dest = SET_DEST (x);
6075 /* If we have (set (cc0) (subreg ...)), we try to remove the subreg
6078 && GET_CODE (src) == SUBREG
6079 && subreg_lowpart_p (src)
6080 && (GET_MODE_BITSIZE (GET_MODE (src))
6081 < GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (src)))))
6083 rtx inner = SUBREG_REG (src);
6084 enum machine_mode inner_mode = GET_MODE (inner);
6086 /* Here we make sure that we don't have a sign bit on. */
6087 if (GET_MODE_BITSIZE (inner_mode) <= HOST_BITS_PER_WIDE_INT
6088 && (nonzero_bits (inner, inner_mode)
6089 < ((unsigned HOST_WIDE_INT) 1
6090 << (GET_MODE_BITSIZE (GET_MODE (src)) - 1))))
6092 SUBST (SET_SRC (x), inner);
6098 #ifdef LOAD_EXTEND_OP
6099 /* If we have (set FOO (subreg:M (mem:N BAR) 0)) with M wider than N, this
6100 would require a paradoxical subreg. Replace the subreg with a
6101 zero_extend to avoid the reload that would otherwise be required. */
6103 if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src)
6104 && INTEGRAL_MODE_P (GET_MODE (SUBREG_REG (src)))
6105 && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src))) != UNKNOWN
6106 && SUBREG_BYTE (src) == 0
6107 && (GET_MODE_SIZE (GET_MODE (src))
6108 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (src))))
6109 && MEM_P (SUBREG_REG (src)))
6112 gen_rtx_fmt_e (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src))),
6113 GET_MODE (src), SUBREG_REG (src)));
6119 /* If we don't have a conditional move, SET_SRC is an IF_THEN_ELSE, and we
6120 are comparing an item known to be 0 or -1 against 0, use a logical
6121 operation instead. Check for one of the arms being an IOR of the other
6122 arm with some value. We compute three terms to be IOR'ed together. In
6123 practice, at most two will be nonzero. Then we do the IOR's. */
6125 if (GET_CODE (dest) != PC
6126 && GET_CODE (src) == IF_THEN_ELSE
6127 && GET_MODE_CLASS (GET_MODE (src)) == MODE_INT
6128 && (GET_CODE (XEXP (src, 0)) == EQ || GET_CODE (XEXP (src, 0)) == NE)
6129 && XEXP (XEXP (src, 0), 1) == const0_rtx
6130 && GET_MODE (src) == GET_MODE (XEXP (XEXP (src, 0), 0))
6131 #ifdef HAVE_conditional_move
6132 && ! can_conditionally_move_p (GET_MODE (src))
6134 && (num_sign_bit_copies (XEXP (XEXP (src, 0), 0),
6135 GET_MODE (XEXP (XEXP (src, 0), 0)))
6136 == GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (src, 0), 0))))
6137 && ! side_effects_p (src))
6139 rtx true_rtx = (GET_CODE (XEXP (src, 0)) == NE
6140 ? XEXP (src, 1) : XEXP (src, 2));
6141 rtx false_rtx = (GET_CODE (XEXP (src, 0)) == NE
6142 ? XEXP (src, 2) : XEXP (src, 1));
6143 rtx term1 = const0_rtx, term2, term3;
6145 if (GET_CODE (true_rtx) == IOR
6146 && rtx_equal_p (XEXP (true_rtx, 0), false_rtx))
6147 term1 = false_rtx, true_rtx = XEXP (true_rtx, 1), false_rtx = const0_rtx;
6148 else if (GET_CODE (true_rtx) == IOR
6149 && rtx_equal_p (XEXP (true_rtx, 1), false_rtx))
6150 term1 = false_rtx, true_rtx = XEXP (true_rtx, 0), false_rtx = const0_rtx;
6151 else if (GET_CODE (false_rtx) == IOR
6152 && rtx_equal_p (XEXP (false_rtx, 0), true_rtx))
6153 term1 = true_rtx, false_rtx = XEXP (false_rtx, 1), true_rtx = const0_rtx;
6154 else if (GET_CODE (false_rtx) == IOR
6155 && rtx_equal_p (XEXP (false_rtx, 1), true_rtx))
6156 term1 = true_rtx, false_rtx = XEXP (false_rtx, 0), true_rtx = const0_rtx;
6158 term2 = simplify_gen_binary (AND, GET_MODE (src),
6159 XEXP (XEXP (src, 0), 0), true_rtx);
6160 term3 = simplify_gen_binary (AND, GET_MODE (src),
6161 simplify_gen_unary (NOT, GET_MODE (src),
6162 XEXP (XEXP (src, 0), 0),
6167 simplify_gen_binary (IOR, GET_MODE (src),
6168 simplify_gen_binary (IOR, GET_MODE (src),
6175 /* If either SRC or DEST is a CLOBBER of (const_int 0), make this
6176 whole thing fail. */
6177 if (GET_CODE (src) == CLOBBER && XEXP (src, 0) == const0_rtx)
6179 else if (GET_CODE (dest) == CLOBBER && XEXP (dest, 0) == const0_rtx)
6182 /* Convert this into a field assignment operation, if possible. */
6183 return make_field_assignment (x);
6186 /* Simplify, X, and AND, IOR, or XOR operation, and return the simplified
6190 simplify_logical (rtx x)
6192 enum machine_mode mode = GET_MODE (x);
6193 rtx op0 = XEXP (x, 0);
6194 rtx op1 = XEXP (x, 1);
6196 switch (GET_CODE (x))
6199 /* We can call simplify_and_const_int only if we don't lose
6200 any (sign) bits when converting INTVAL (op1) to
6201 "unsigned HOST_WIDE_INT". */
6202 if (CONST_INT_P (op1)
6203 && (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
6204 || INTVAL (op1) > 0))
6206 x = simplify_and_const_int (x, mode, op0, INTVAL (op1));
6207 if (GET_CODE (x) != AND)
6214 /* If we have any of (and (ior A B) C) or (and (xor A B) C),
6215 apply the distributive law and then the inverse distributive
6216 law to see if things simplify. */
6217 if (GET_CODE (op0) == IOR || GET_CODE (op0) == XOR)
6219 rtx result = distribute_and_simplify_rtx (x, 0);
6223 if (GET_CODE (op1) == IOR || GET_CODE (op1) == XOR)
6225 rtx result = distribute_and_simplify_rtx (x, 1);
6232 /* If we have (ior (and A B) C), apply the distributive law and then
6233 the inverse distributive law to see if things simplify. */
6235 if (GET_CODE (op0) == AND)
6237 rtx result = distribute_and_simplify_rtx (x, 0);
6242 if (GET_CODE (op1) == AND)
6244 rtx result = distribute_and_simplify_rtx (x, 1);
6257 /* We consider ZERO_EXTRACT, SIGN_EXTRACT, and SIGN_EXTEND as "compound
6258 operations" because they can be replaced with two more basic operations.
6259 ZERO_EXTEND is also considered "compound" because it can be replaced with
6260 an AND operation, which is simpler, though only one operation.
6262 The function expand_compound_operation is called with an rtx expression
6263 and will convert it to the appropriate shifts and AND operations,
6264 simplifying at each stage.
6266 The function make_compound_operation is called to convert an expression
6267 consisting of shifts and ANDs into the equivalent compound expression.
6268 It is the inverse of this function, loosely speaking. */
6271 expand_compound_operation (rtx x)
6273 unsigned HOST_WIDE_INT pos = 0, len;
6275 unsigned int modewidth;
6278 switch (GET_CODE (x))
6283 /* We can't necessarily use a const_int for a multiword mode;
6284 it depends on implicitly extending the value.
6285 Since we don't know the right way to extend it,
6286 we can't tell whether the implicit way is right.
6288 Even for a mode that is no wider than a const_int,
6289 we can't win, because we need to sign extend one of its bits through
6290 the rest of it, and we don't know which bit. */
6291 if (CONST_INT_P (XEXP (x, 0)))
6294 /* Return if (subreg:MODE FROM 0) is not a safe replacement for
6295 (zero_extend:MODE FROM) or (sign_extend:MODE FROM). It is for any MEM
6296 because (SUBREG (MEM...)) is guaranteed to cause the MEM to be
6297 reloaded. If not for that, MEM's would very rarely be safe.
6299 Reject MODEs bigger than a word, because we might not be able
6300 to reference a two-register group starting with an arbitrary register
6301 (and currently gen_lowpart might crash for a SUBREG). */
6303 if (GET_MODE_SIZE (GET_MODE (XEXP (x, 0))) > UNITS_PER_WORD)
6306 /* Reject MODEs that aren't scalar integers because turning vector
6307 or complex modes into shifts causes problems. */
6309 if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x, 0))))
6312 len = GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)));
6313 /* If the inner object has VOIDmode (the only way this can happen
6314 is if it is an ASM_OPERANDS), we can't do anything since we don't
6315 know how much masking to do. */
6324 /* ... fall through ... */
6327 /* If the operand is a CLOBBER, just return it. */
6328 if (GET_CODE (XEXP (x, 0)) == CLOBBER)
6331 if (!CONST_INT_P (XEXP (x, 1))
6332 || !CONST_INT_P (XEXP (x, 2))
6333 || GET_MODE (XEXP (x, 0)) == VOIDmode)
6336 /* Reject MODEs that aren't scalar integers because turning vector
6337 or complex modes into shifts causes problems. */
6339 if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x, 0))))
6342 len = INTVAL (XEXP (x, 1));
6343 pos = INTVAL (XEXP (x, 2));
6345 /* This should stay within the object being extracted, fail otherwise. */
6346 if (len + pos > GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))))
6349 if (BITS_BIG_ENDIAN)
6350 pos = GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - len - pos;
6357 /* Convert sign extension to zero extension, if we know that the high
6358 bit is not set, as this is easier to optimize. It will be converted
6359 back to cheaper alternative in make_extraction. */
6360 if (GET_CODE (x) == SIGN_EXTEND
6361 && (GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
6362 && ((nonzero_bits (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
6363 & ~(((unsigned HOST_WIDE_INT)
6364 GET_MODE_MASK (GET_MODE (XEXP (x, 0))))
6368 rtx temp = gen_rtx_ZERO_EXTEND (GET_MODE (x), XEXP (x, 0));
6369 rtx temp2 = expand_compound_operation (temp);
6371 /* Make sure this is a profitable operation. */
6372 if (rtx_cost (x, SET, optimize_this_for_speed_p)
6373 > rtx_cost (temp2, SET, optimize_this_for_speed_p))
6375 else if (rtx_cost (x, SET, optimize_this_for_speed_p)
6376 > rtx_cost (temp, SET, optimize_this_for_speed_p))
6382 /* We can optimize some special cases of ZERO_EXTEND. */
6383 if (GET_CODE (x) == ZERO_EXTEND)
6385 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI if we
6386 know that the last value didn't have any inappropriate bits
6388 if (GET_CODE (XEXP (x, 0)) == TRUNCATE
6389 && GET_MODE (XEXP (XEXP (x, 0), 0)) == GET_MODE (x)
6390 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
6391 && (nonzero_bits (XEXP (XEXP (x, 0), 0), GET_MODE (x))
6392 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
6393 return XEXP (XEXP (x, 0), 0);
6395 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
6396 if (GET_CODE (XEXP (x, 0)) == SUBREG
6397 && GET_MODE (SUBREG_REG (XEXP (x, 0))) == GET_MODE (x)
6398 && subreg_lowpart_p (XEXP (x, 0))
6399 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
6400 && (nonzero_bits (SUBREG_REG (XEXP (x, 0)), GET_MODE (x))
6401 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
6402 return SUBREG_REG (XEXP (x, 0));
6404 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI when foo
6405 is a comparison and STORE_FLAG_VALUE permits. This is like
6406 the first case, but it works even when GET_MODE (x) is larger
6407 than HOST_WIDE_INT. */
6408 if (GET_CODE (XEXP (x, 0)) == TRUNCATE
6409 && GET_MODE (XEXP (XEXP (x, 0), 0)) == GET_MODE (x)
6410 && COMPARISON_P (XEXP (XEXP (x, 0), 0))
6411 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
6412 <= HOST_BITS_PER_WIDE_INT)
6413 && ((HOST_WIDE_INT) STORE_FLAG_VALUE
6414 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
6415 return XEXP (XEXP (x, 0), 0);
6417 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
6418 if (GET_CODE (XEXP (x, 0)) == SUBREG
6419 && GET_MODE (SUBREG_REG (XEXP (x, 0))) == GET_MODE (x)
6420 && subreg_lowpart_p (XEXP (x, 0))
6421 && COMPARISON_P (SUBREG_REG (XEXP (x, 0)))
6422 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
6423 <= HOST_BITS_PER_WIDE_INT)
6424 && ((HOST_WIDE_INT) STORE_FLAG_VALUE
6425 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
6426 return SUBREG_REG (XEXP (x, 0));
6430 /* If we reach here, we want to return a pair of shifts. The inner
6431 shift is a left shift of BITSIZE - POS - LEN bits. The outer
6432 shift is a right shift of BITSIZE - LEN bits. It is arithmetic or
6433 logical depending on the value of UNSIGNEDP.
6435 If this was a ZERO_EXTEND or ZERO_EXTRACT, this pair of shifts will be
6436 converted into an AND of a shift.
6438 We must check for the case where the left shift would have a negative
6439 count. This can happen in a case like (x >> 31) & 255 on machines
6440 that can't shift by a constant. On those machines, we would first
6441 combine the shift with the AND to produce a variable-position
6442 extraction. Then the constant of 31 would be substituted in to produce
6443 a such a position. */
6445 modewidth = GET_MODE_BITSIZE (GET_MODE (x));
6446 if (modewidth + len >= pos)
6448 enum machine_mode mode = GET_MODE (x);
6449 tem = gen_lowpart (mode, XEXP (x, 0));
6450 if (!tem || GET_CODE (tem) == CLOBBER)
6452 tem = simplify_shift_const (NULL_RTX, ASHIFT, mode,
6453 tem, modewidth - pos - len);
6454 tem = simplify_shift_const (NULL_RTX, unsignedp ? LSHIFTRT : ASHIFTRT,
6455 mode, tem, modewidth - len);
6457 else if (unsignedp && len < HOST_BITS_PER_WIDE_INT)
6458 tem = simplify_and_const_int (NULL_RTX, GET_MODE (x),
6459 simplify_shift_const (NULL_RTX, LSHIFTRT,
6462 ((HOST_WIDE_INT) 1 << len) - 1);
6464 /* Any other cases we can't handle. */
6467 /* If we couldn't do this for some reason, return the original
6469 if (GET_CODE (tem) == CLOBBER)
6475 /* X is a SET which contains an assignment of one object into
6476 a part of another (such as a bit-field assignment, STRICT_LOW_PART,
6477 or certain SUBREGS). If possible, convert it into a series of
6480 We half-heartedly support variable positions, but do not at all
6481 support variable lengths. */
6484 expand_field_assignment (const_rtx x)
6487 rtx pos; /* Always counts from low bit. */
6489 rtx mask, cleared, masked;
6490 enum machine_mode compute_mode;
6492 /* Loop until we find something we can't simplify. */
6495 if (GET_CODE (SET_DEST (x)) == STRICT_LOW_PART
6496 && GET_CODE (XEXP (SET_DEST (x), 0)) == SUBREG)
6498 inner = SUBREG_REG (XEXP (SET_DEST (x), 0));
6499 len = GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0)));
6500 pos = GEN_INT (subreg_lsb (XEXP (SET_DEST (x), 0)));
6502 else if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
6503 && CONST_INT_P (XEXP (SET_DEST (x), 1)))
6505 inner = XEXP (SET_DEST (x), 0);
6506 len = INTVAL (XEXP (SET_DEST (x), 1));
6507 pos = XEXP (SET_DEST (x), 2);
6509 /* A constant position should stay within the width of INNER. */
6510 if (CONST_INT_P (pos)
6511 && INTVAL (pos) + len > GET_MODE_BITSIZE (GET_MODE (inner)))
6514 if (BITS_BIG_ENDIAN)
6516 if (CONST_INT_P (pos))
6517 pos = GEN_INT (GET_MODE_BITSIZE (GET_MODE (inner)) - len
6519 else if (GET_CODE (pos) == MINUS
6520 && CONST_INT_P (XEXP (pos, 1))
6521 && (INTVAL (XEXP (pos, 1))
6522 == GET_MODE_BITSIZE (GET_MODE (inner)) - len))
6523 /* If position is ADJUST - X, new position is X. */
6524 pos = XEXP (pos, 0);
6526 pos = simplify_gen_binary (MINUS, GET_MODE (pos),
6527 GEN_INT (GET_MODE_BITSIZE (
6534 /* A SUBREG between two modes that occupy the same numbers of words
6535 can be done by moving the SUBREG to the source. */
6536 else if (GET_CODE (SET_DEST (x)) == SUBREG
6537 /* We need SUBREGs to compute nonzero_bits properly. */
6538 && nonzero_sign_valid
6539 && (((GET_MODE_SIZE (GET_MODE (SET_DEST (x)))
6540 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
6541 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x))))
6542 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)))
6544 x = gen_rtx_SET (VOIDmode, SUBREG_REG (SET_DEST (x)),
6546 (GET_MODE (SUBREG_REG (SET_DEST (x))),
6553 while (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
6554 inner = SUBREG_REG (inner);
6556 compute_mode = GET_MODE (inner);
6558 /* Don't attempt bitwise arithmetic on non scalar integer modes. */
6559 if (! SCALAR_INT_MODE_P (compute_mode))
6561 enum machine_mode imode;
6563 /* Don't do anything for vector or complex integral types. */
6564 if (! FLOAT_MODE_P (compute_mode))
6567 /* Try to find an integral mode to pun with. */
6568 imode = mode_for_size (GET_MODE_BITSIZE (compute_mode), MODE_INT, 0);
6569 if (imode == BLKmode)
6572 compute_mode = imode;
6573 inner = gen_lowpart (imode, inner);
6576 /* Compute a mask of LEN bits, if we can do this on the host machine. */
6577 if (len >= HOST_BITS_PER_WIDE_INT)
6580 /* Now compute the equivalent expression. Make a copy of INNER
6581 for the SET_DEST in case it is a MEM into which we will substitute;
6582 we don't want shared RTL in that case. */
6583 mask = GEN_INT (((HOST_WIDE_INT) 1 << len) - 1);
6584 cleared = simplify_gen_binary (AND, compute_mode,
6585 simplify_gen_unary (NOT, compute_mode,
6586 simplify_gen_binary (ASHIFT,
6591 masked = simplify_gen_binary (ASHIFT, compute_mode,
6592 simplify_gen_binary (
6594 gen_lowpart (compute_mode, SET_SRC (x)),
6598 x = gen_rtx_SET (VOIDmode, copy_rtx (inner),
6599 simplify_gen_binary (IOR, compute_mode,
6606 /* Return an RTX for a reference to LEN bits of INNER. If POS_RTX is nonzero,
6607 it is an RTX that represents a variable starting position; otherwise,
6608 POS is the (constant) starting bit position (counted from the LSB).
6610 UNSIGNEDP is nonzero for an unsigned reference and zero for a
6613 IN_DEST is nonzero if this is a reference in the destination of a
6614 SET. This is used when a ZERO_ or SIGN_EXTRACT isn't needed. If nonzero,
6615 a STRICT_LOW_PART will be used, if zero, ZERO_EXTEND or SIGN_EXTEND will
6618 IN_COMPARE is nonzero if we are in a COMPARE. This means that a
6619 ZERO_EXTRACT should be built even for bits starting at bit 0.
6621 MODE is the desired mode of the result (if IN_DEST == 0).
6623 The result is an RTX for the extraction or NULL_RTX if the target
6627 make_extraction (enum machine_mode mode, rtx inner, HOST_WIDE_INT pos,
6628 rtx pos_rtx, unsigned HOST_WIDE_INT len, int unsignedp,
6629 int in_dest, int in_compare)
6631 /* This mode describes the size of the storage area
6632 to fetch the overall value from. Within that, we
6633 ignore the POS lowest bits, etc. */
6634 enum machine_mode is_mode = GET_MODE (inner);
6635 enum machine_mode inner_mode;
6636 enum machine_mode wanted_inner_mode;
6637 enum machine_mode wanted_inner_reg_mode = word_mode;
6638 enum machine_mode pos_mode = word_mode;
6639 enum machine_mode extraction_mode = word_mode;
6640 enum machine_mode tmode = mode_for_size (len, MODE_INT, 1);
6642 rtx orig_pos_rtx = pos_rtx;
6643 HOST_WIDE_INT orig_pos;
6645 if (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
6647 /* If going from (subreg:SI (mem:QI ...)) to (mem:QI ...),
6648 consider just the QI as the memory to extract from.
6649 The subreg adds or removes high bits; its mode is
6650 irrelevant to the meaning of this extraction,
6651 since POS and LEN count from the lsb. */
6652 if (MEM_P (SUBREG_REG (inner)))
6653 is_mode = GET_MODE (SUBREG_REG (inner));
6654 inner = SUBREG_REG (inner);
6656 else if (GET_CODE (inner) == ASHIFT
6657 && CONST_INT_P (XEXP (inner, 1))
6658 && pos_rtx == 0 && pos == 0
6659 && len > (unsigned HOST_WIDE_INT) INTVAL (XEXP (inner, 1)))
6661 /* We're extracting the least significant bits of an rtx
6662 (ashift X (const_int C)), where LEN > C. Extract the
6663 least significant (LEN - C) bits of X, giving an rtx
6664 whose mode is MODE, then shift it left C times. */
6665 new_rtx = make_extraction (mode, XEXP (inner, 0),
6666 0, 0, len - INTVAL (XEXP (inner, 1)),
6667 unsignedp, in_dest, in_compare);
6669 return gen_rtx_ASHIFT (mode, new_rtx, XEXP (inner, 1));
6672 inner_mode = GET_MODE (inner);
6674 if (pos_rtx && CONST_INT_P (pos_rtx))
6675 pos = INTVAL (pos_rtx), pos_rtx = 0;
6677 /* See if this can be done without an extraction. We never can if the
6678 width of the field is not the same as that of some integer mode. For
6679 registers, we can only avoid the extraction if the position is at the
6680 low-order bit and this is either not in the destination or we have the
6681 appropriate STRICT_LOW_PART operation available.
6683 For MEM, we can avoid an extract if the field starts on an appropriate
6684 boundary and we can change the mode of the memory reference. */
6686 if (tmode != BLKmode
6687 && ((pos_rtx == 0 && (pos % BITS_PER_WORD) == 0
6689 && (inner_mode == tmode
6691 || TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (tmode),
6692 GET_MODE_BITSIZE (inner_mode))
6693 || reg_truncated_to_mode (tmode, inner))
6696 && have_insn_for (STRICT_LOW_PART, tmode))))
6697 || (MEM_P (inner) && pos_rtx == 0
6699 % (STRICT_ALIGNMENT ? GET_MODE_ALIGNMENT (tmode)
6700 : BITS_PER_UNIT)) == 0
6701 /* We can't do this if we are widening INNER_MODE (it
6702 may not be aligned, for one thing). */
6703 && GET_MODE_BITSIZE (inner_mode) >= GET_MODE_BITSIZE (tmode)
6704 && (inner_mode == tmode
6705 || (! mode_dependent_address_p (XEXP (inner, 0))
6706 && ! MEM_VOLATILE_P (inner))))))
6708 /* If INNER is a MEM, make a new MEM that encompasses just the desired
6709 field. If the original and current mode are the same, we need not
6710 adjust the offset. Otherwise, we do if bytes big endian.
6712 If INNER is not a MEM, get a piece consisting of just the field
6713 of interest (in this case POS % BITS_PER_WORD must be 0). */
6717 HOST_WIDE_INT offset;
6719 /* POS counts from lsb, but make OFFSET count in memory order. */
6720 if (BYTES_BIG_ENDIAN)
6721 offset = (GET_MODE_BITSIZE (is_mode) - len - pos) / BITS_PER_UNIT;
6723 offset = pos / BITS_PER_UNIT;
6725 new_rtx = adjust_address_nv (inner, tmode, offset);
6727 else if (REG_P (inner))
6729 if (tmode != inner_mode)
6731 /* We can't call gen_lowpart in a DEST since we
6732 always want a SUBREG (see below) and it would sometimes
6733 return a new hard register. */
6736 HOST_WIDE_INT final_word = pos / BITS_PER_WORD;
6738 if (WORDS_BIG_ENDIAN
6739 && GET_MODE_SIZE (inner_mode) > UNITS_PER_WORD)
6740 final_word = ((GET_MODE_SIZE (inner_mode)
6741 - GET_MODE_SIZE (tmode))
6742 / UNITS_PER_WORD) - final_word;
6744 final_word *= UNITS_PER_WORD;
6745 if (BYTES_BIG_ENDIAN &&
6746 GET_MODE_SIZE (inner_mode) > GET_MODE_SIZE (tmode))
6747 final_word += (GET_MODE_SIZE (inner_mode)
6748 - GET_MODE_SIZE (tmode)) % UNITS_PER_WORD;
6750 /* Avoid creating invalid subregs, for example when
6751 simplifying (x>>32)&255. */
6752 if (!validate_subreg (tmode, inner_mode, inner, final_word))
6755 new_rtx = gen_rtx_SUBREG (tmode, inner, final_word);
6758 new_rtx = gen_lowpart (tmode, inner);
6764 new_rtx = force_to_mode (inner, tmode,
6765 len >= HOST_BITS_PER_WIDE_INT
6766 ? ~(unsigned HOST_WIDE_INT) 0
6767 : ((unsigned HOST_WIDE_INT) 1 << len) - 1,
6770 /* If this extraction is going into the destination of a SET,
6771 make a STRICT_LOW_PART unless we made a MEM. */
6774 return (MEM_P (new_rtx) ? new_rtx
6775 : (GET_CODE (new_rtx) != SUBREG
6776 ? gen_rtx_CLOBBER (tmode, const0_rtx)
6777 : gen_rtx_STRICT_LOW_PART (VOIDmode, new_rtx)));
6782 if (CONST_INT_P (new_rtx))
6783 return gen_int_mode (INTVAL (new_rtx), mode);
6785 /* If we know that no extraneous bits are set, and that the high
6786 bit is not set, convert the extraction to the cheaper of
6787 sign and zero extension, that are equivalent in these cases. */
6788 if (flag_expensive_optimizations
6789 && (GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT
6790 && ((nonzero_bits (new_rtx, tmode)
6791 & ~(((unsigned HOST_WIDE_INT)
6792 GET_MODE_MASK (tmode))
6796 rtx temp = gen_rtx_ZERO_EXTEND (mode, new_rtx);
6797 rtx temp1 = gen_rtx_SIGN_EXTEND (mode, new_rtx);
6799 /* Prefer ZERO_EXTENSION, since it gives more information to
6801 if (rtx_cost (temp, SET, optimize_this_for_speed_p)
6802 <= rtx_cost (temp1, SET, optimize_this_for_speed_p))
6807 /* Otherwise, sign- or zero-extend unless we already are in the
6810 return (gen_rtx_fmt_e (unsignedp ? ZERO_EXTEND : SIGN_EXTEND,
6814 /* Unless this is a COMPARE or we have a funny memory reference,
6815 don't do anything with zero-extending field extracts starting at
6816 the low-order bit since they are simple AND operations. */
6817 if (pos_rtx == 0 && pos == 0 && ! in_dest
6818 && ! in_compare && unsignedp)
6821 /* Unless INNER is not MEM, reject this if we would be spanning bytes or
6822 if the position is not a constant and the length is not 1. In all
6823 other cases, we would only be going outside our object in cases when
6824 an original shift would have been undefined. */
6826 && ((pos_rtx == 0 && pos + len > GET_MODE_BITSIZE (is_mode))
6827 || (pos_rtx != 0 && len != 1)))
6830 /* Get the mode to use should INNER not be a MEM, the mode for the position,
6831 and the mode for the result. */
6832 if (in_dest && mode_for_extraction (EP_insv, -1) != MAX_MACHINE_MODE)
6834 wanted_inner_reg_mode = mode_for_extraction (EP_insv, 0);
6835 pos_mode = mode_for_extraction (EP_insv, 2);
6836 extraction_mode = mode_for_extraction (EP_insv, 3);
6839 if (! in_dest && unsignedp
6840 && mode_for_extraction (EP_extzv, -1) != MAX_MACHINE_MODE)
6842 wanted_inner_reg_mode = mode_for_extraction (EP_extzv, 1);
6843 pos_mode = mode_for_extraction (EP_extzv, 3);
6844 extraction_mode = mode_for_extraction (EP_extzv, 0);
6847 if (! in_dest && ! unsignedp
6848 && mode_for_extraction (EP_extv, -1) != MAX_MACHINE_MODE)
6850 wanted_inner_reg_mode = mode_for_extraction (EP_extv, 1);
6851 pos_mode = mode_for_extraction (EP_extv, 3);
6852 extraction_mode = mode_for_extraction (EP_extv, 0);
6855 /* Never narrow an object, since that might not be safe. */
6857 if (mode != VOIDmode
6858 && GET_MODE_SIZE (extraction_mode) < GET_MODE_SIZE (mode))
6859 extraction_mode = mode;
6861 if (pos_rtx && GET_MODE (pos_rtx) != VOIDmode
6862 && GET_MODE_SIZE (pos_mode) < GET_MODE_SIZE (GET_MODE (pos_rtx)))
6863 pos_mode = GET_MODE (pos_rtx);
6865 /* If this is not from memory, the desired mode is the preferred mode
6866 for an extraction pattern's first input operand, or word_mode if there
6869 wanted_inner_mode = wanted_inner_reg_mode;
6872 /* Be careful not to go beyond the extracted object and maintain the
6873 natural alignment of the memory. */
6874 wanted_inner_mode = smallest_mode_for_size (len, MODE_INT);
6875 while (pos % GET_MODE_BITSIZE (wanted_inner_mode) + len
6876 > GET_MODE_BITSIZE (wanted_inner_mode))
6878 wanted_inner_mode = GET_MODE_WIDER_MODE (wanted_inner_mode);
6879 gcc_assert (wanted_inner_mode != VOIDmode);
6882 /* If we have to change the mode of memory and cannot, the desired mode
6883 is EXTRACTION_MODE. */
6884 if (inner_mode != wanted_inner_mode
6885 && (mode_dependent_address_p (XEXP (inner, 0))
6886 || MEM_VOLATILE_P (inner)
6888 wanted_inner_mode = extraction_mode;
6893 if (BITS_BIG_ENDIAN)
6895 /* POS is passed as if BITS_BIG_ENDIAN == 0, so we need to convert it to
6896 BITS_BIG_ENDIAN style. If position is constant, compute new
6897 position. Otherwise, build subtraction.
6898 Note that POS is relative to the mode of the original argument.
6899 If it's a MEM we need to recompute POS relative to that.
6900 However, if we're extracting from (or inserting into) a register,
6901 we want to recompute POS relative to wanted_inner_mode. */
6902 int width = (MEM_P (inner)
6903 ? GET_MODE_BITSIZE (is_mode)
6904 : GET_MODE_BITSIZE (wanted_inner_mode));
6907 pos = width - len - pos;
6910 = gen_rtx_MINUS (GET_MODE (pos_rtx), GEN_INT (width - len), pos_rtx);
6911 /* POS may be less than 0 now, but we check for that below.
6912 Note that it can only be less than 0 if !MEM_P (inner). */
6915 /* If INNER has a wider mode, and this is a constant extraction, try to
6916 make it smaller and adjust the byte to point to the byte containing
6918 if (wanted_inner_mode != VOIDmode
6919 && inner_mode != wanted_inner_mode
6921 && GET_MODE_SIZE (wanted_inner_mode) < GET_MODE_SIZE (is_mode)
6923 && ! mode_dependent_address_p (XEXP (inner, 0))
6924 && ! MEM_VOLATILE_P (inner))
6928 /* The computations below will be correct if the machine is big
6929 endian in both bits and bytes or little endian in bits and bytes.
6930 If it is mixed, we must adjust. */
6932 /* If bytes are big endian and we had a paradoxical SUBREG, we must
6933 adjust OFFSET to compensate. */
6934 if (BYTES_BIG_ENDIAN
6935 && GET_MODE_SIZE (inner_mode) < GET_MODE_SIZE (is_mode))
6936 offset -= GET_MODE_SIZE (is_mode) - GET_MODE_SIZE (inner_mode);
6938 /* We can now move to the desired byte. */
6939 offset += (pos / GET_MODE_BITSIZE (wanted_inner_mode))
6940 * GET_MODE_SIZE (wanted_inner_mode);
6941 pos %= GET_MODE_BITSIZE (wanted_inner_mode);
6943 if (BYTES_BIG_ENDIAN != BITS_BIG_ENDIAN
6944 && is_mode != wanted_inner_mode)
6945 offset = (GET_MODE_SIZE (is_mode)
6946 - GET_MODE_SIZE (wanted_inner_mode) - offset);
6948 inner = adjust_address_nv (inner, wanted_inner_mode, offset);
6951 /* If INNER is not memory, get it into the proper mode. If we are changing
6952 its mode, POS must be a constant and smaller than the size of the new
6954 else if (!MEM_P (inner))
6956 /* On the LHS, don't create paradoxical subregs implicitely truncating
6957 the register unless TRULY_NOOP_TRUNCATION. */
6959 && !TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (GET_MODE (inner)),
6960 GET_MODE_BITSIZE (wanted_inner_mode)))
6963 if (GET_MODE (inner) != wanted_inner_mode
6965 || orig_pos + len > GET_MODE_BITSIZE (wanted_inner_mode)))
6971 inner = force_to_mode (inner, wanted_inner_mode,
6973 || len + orig_pos >= HOST_BITS_PER_WIDE_INT
6974 ? ~(unsigned HOST_WIDE_INT) 0
6975 : ((((unsigned HOST_WIDE_INT) 1 << len) - 1)
6980 /* Adjust mode of POS_RTX, if needed. If we want a wider mode, we
6981 have to zero extend. Otherwise, we can just use a SUBREG. */
6983 && GET_MODE_SIZE (pos_mode) > GET_MODE_SIZE (GET_MODE (pos_rtx)))
6985 rtx temp = gen_rtx_ZERO_EXTEND (pos_mode, pos_rtx);
6987 /* If we know that no extraneous bits are set, and that the high
6988 bit is not set, convert extraction to cheaper one - either
6989 SIGN_EXTENSION or ZERO_EXTENSION, that are equivalent in these
6991 if (flag_expensive_optimizations
6992 && (GET_MODE_BITSIZE (GET_MODE (pos_rtx)) <= HOST_BITS_PER_WIDE_INT
6993 && ((nonzero_bits (pos_rtx, GET_MODE (pos_rtx))
6994 & ~(((unsigned HOST_WIDE_INT)
6995 GET_MODE_MASK (GET_MODE (pos_rtx)))
6999 rtx temp1 = gen_rtx_SIGN_EXTEND (pos_mode, pos_rtx);
7001 /* Prefer ZERO_EXTENSION, since it gives more information to
7003 if (rtx_cost (temp1, SET, optimize_this_for_speed_p)
7004 < rtx_cost (temp, SET, optimize_this_for_speed_p))
7009 else if (pos_rtx != 0
7010 && GET_MODE_SIZE (pos_mode) < GET_MODE_SIZE (GET_MODE (pos_rtx)))
7011 pos_rtx = gen_lowpart (pos_mode, pos_rtx);
7013 /* Make POS_RTX unless we already have it and it is correct. If we don't
7014 have a POS_RTX but we do have an ORIG_POS_RTX, the latter must
7016 if (pos_rtx == 0 && orig_pos_rtx != 0 && INTVAL (orig_pos_rtx) == pos)
7017 pos_rtx = orig_pos_rtx;
7019 else if (pos_rtx == 0)
7020 pos_rtx = GEN_INT (pos);
7022 /* Make the required operation. See if we can use existing rtx. */
7023 new_rtx = gen_rtx_fmt_eee (unsignedp ? ZERO_EXTRACT : SIGN_EXTRACT,
7024 extraction_mode, inner, GEN_INT (len), pos_rtx);
7026 new_rtx = gen_lowpart (mode, new_rtx);
7031 /* See if X contains an ASHIFT of COUNT or more bits that can be commuted
7032 with any other operations in X. Return X without that shift if so. */
7035 extract_left_shift (rtx x, int count)
7037 enum rtx_code code = GET_CODE (x);
7038 enum machine_mode mode = GET_MODE (x);
7044 /* This is the shift itself. If it is wide enough, we will return
7045 either the value being shifted if the shift count is equal to
7046 COUNT or a shift for the difference. */
7047 if (CONST_INT_P (XEXP (x, 1))
7048 && INTVAL (XEXP (x, 1)) >= count)
7049 return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (x, 0),
7050 INTVAL (XEXP (x, 1)) - count);
7054 if ((tem = extract_left_shift (XEXP (x, 0), count)) != 0)
7055 return simplify_gen_unary (code, mode, tem, mode);
7059 case PLUS: case IOR: case XOR: case AND:
7060 /* If we can safely shift this constant and we find the inner shift,
7061 make a new operation. */
7062 if (CONST_INT_P (XEXP (x, 1))
7063 && (INTVAL (XEXP (x, 1)) & ((((HOST_WIDE_INT) 1 << count)) - 1)) == 0
7064 && (tem = extract_left_shift (XEXP (x, 0), count)) != 0)
7065 return simplify_gen_binary (code, mode, tem,
7066 GEN_INT (INTVAL (XEXP (x, 1)) >> count));
7077 /* Look at the expression rooted at X. Look for expressions
7078 equivalent to ZERO_EXTRACT, SIGN_EXTRACT, ZERO_EXTEND, SIGN_EXTEND.
7079 Form these expressions.
7081 Return the new rtx, usually just X.
7083 Also, for machines like the VAX that don't have logical shift insns,
7084 try to convert logical to arithmetic shift operations in cases where
7085 they are equivalent. This undoes the canonicalizations to logical
7086 shifts done elsewhere.
7088 We try, as much as possible, to re-use rtl expressions to save memory.
7090 IN_CODE says what kind of expression we are processing. Normally, it is
7091 SET. In a memory address (inside a MEM, PLUS or minus, the latter two
7092 being kludges), it is MEM. When processing the arguments of a comparison
7093 or a COMPARE against zero, it is COMPARE. */
7096 make_compound_operation (rtx x, enum rtx_code in_code)
7098 enum rtx_code code = GET_CODE (x);
7099 enum machine_mode mode = GET_MODE (x);
7100 int mode_width = GET_MODE_BITSIZE (mode);
7102 enum rtx_code next_code;
7108 /* Select the code to be used in recursive calls. Once we are inside an
7109 address, we stay there. If we have a comparison, set to COMPARE,
7110 but once inside, go back to our default of SET. */
7112 next_code = (code == MEM || code == PLUS || code == MINUS ? MEM
7113 : ((code == COMPARE || COMPARISON_P (x))
7114 && XEXP (x, 1) == const0_rtx) ? COMPARE
7115 : in_code == COMPARE ? SET : in_code);
7117 /* Process depending on the code of this operation. If NEW is set
7118 nonzero, it will be returned. */
7123 /* Convert shifts by constants into multiplications if inside
7125 if (in_code == MEM && CONST_INT_P (XEXP (x, 1))
7126 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT
7127 && INTVAL (XEXP (x, 1)) >= 0)
7129 new_rtx = make_compound_operation (XEXP (x, 0), next_code);
7130 new_rtx = gen_rtx_MULT (mode, new_rtx,
7131 GEN_INT ((HOST_WIDE_INT) 1
7132 << INTVAL (XEXP (x, 1))));
7137 /* If the second operand is not a constant, we can't do anything
7139 if (!CONST_INT_P (XEXP (x, 1)))
7142 /* If the constant is a power of two minus one and the first operand
7143 is a logical right shift, make an extraction. */
7144 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
7145 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
7147 new_rtx = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code);
7148 new_rtx = make_extraction (mode, new_rtx, 0, XEXP (XEXP (x, 0), 1), i, 1,
7149 0, in_code == COMPARE);
7152 /* Same as previous, but for (subreg (lshiftrt ...)) in first op. */
7153 else if (GET_CODE (XEXP (x, 0)) == SUBREG
7154 && subreg_lowpart_p (XEXP (x, 0))
7155 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == LSHIFTRT
7156 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
7158 new_rtx = make_compound_operation (XEXP (SUBREG_REG (XEXP (x, 0)), 0),
7160 new_rtx = make_extraction (GET_MODE (SUBREG_REG (XEXP (x, 0))), new_rtx, 0,
7161 XEXP (SUBREG_REG (XEXP (x, 0)), 1), i, 1,
7162 0, in_code == COMPARE);
7164 /* Same as previous, but for (xor/ior (lshiftrt...) (lshiftrt...)). */
7165 else if ((GET_CODE (XEXP (x, 0)) == XOR
7166 || GET_CODE (XEXP (x, 0)) == IOR)
7167 && GET_CODE (XEXP (XEXP (x, 0), 0)) == LSHIFTRT
7168 && GET_CODE (XEXP (XEXP (x, 0), 1)) == LSHIFTRT
7169 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
7171 /* Apply the distributive law, and then try to make extractions. */
7172 new_rtx = gen_rtx_fmt_ee (GET_CODE (XEXP (x, 0)), mode,
7173 gen_rtx_AND (mode, XEXP (XEXP (x, 0), 0),
7175 gen_rtx_AND (mode, XEXP (XEXP (x, 0), 1),
7177 new_rtx = make_compound_operation (new_rtx, in_code);
7180 /* If we are have (and (rotate X C) M) and C is larger than the number
7181 of bits in M, this is an extraction. */
7183 else if (GET_CODE (XEXP (x, 0)) == ROTATE
7184 && CONST_INT_P (XEXP (XEXP (x, 0), 1))
7185 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0
7186 && i <= INTVAL (XEXP (XEXP (x, 0), 1)))
7188 new_rtx = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code);
7189 new_rtx = make_extraction (mode, new_rtx,
7190 (GET_MODE_BITSIZE (mode)
7191 - INTVAL (XEXP (XEXP (x, 0), 1))),
7192 NULL_RTX, i, 1, 0, in_code == COMPARE);
7195 /* On machines without logical shifts, if the operand of the AND is
7196 a logical shift and our mask turns off all the propagated sign
7197 bits, we can replace the logical shift with an arithmetic shift. */
7198 else if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
7199 && !have_insn_for (LSHIFTRT, mode)
7200 && have_insn_for (ASHIFTRT, mode)
7201 && CONST_INT_P (XEXP (XEXP (x, 0), 1))
7202 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
7203 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT
7204 && mode_width <= HOST_BITS_PER_WIDE_INT)
7206 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
7208 mask >>= INTVAL (XEXP (XEXP (x, 0), 1));
7209 if ((INTVAL (XEXP (x, 1)) & ~mask) == 0)
7211 gen_rtx_ASHIFTRT (mode,
7212 make_compound_operation
7213 (XEXP (XEXP (x, 0), 0), next_code),
7214 XEXP (XEXP (x, 0), 1)));
7217 /* If the constant is one less than a power of two, this might be
7218 representable by an extraction even if no shift is present.
7219 If it doesn't end up being a ZERO_EXTEND, we will ignore it unless
7220 we are in a COMPARE. */
7221 else if ((i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
7222 new_rtx = make_extraction (mode,
7223 make_compound_operation (XEXP (x, 0),
7225 0, NULL_RTX, i, 1, 0, in_code == COMPARE);
7227 /* If we are in a comparison and this is an AND with a power of two,
7228 convert this into the appropriate bit extract. */
7229 else if (in_code == COMPARE
7230 && (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0)
7231 new_rtx = make_extraction (mode,
7232 make_compound_operation (XEXP (x, 0),
7234 i, NULL_RTX, 1, 1, 0, 1);
7239 /* If the sign bit is known to be zero, replace this with an
7240 arithmetic shift. */
7241 if (have_insn_for (ASHIFTRT, mode)
7242 && ! have_insn_for (LSHIFTRT, mode)
7243 && mode_width <= HOST_BITS_PER_WIDE_INT
7244 && (nonzero_bits (XEXP (x, 0), mode) & (1 << (mode_width - 1))) == 0)
7246 new_rtx = gen_rtx_ASHIFTRT (mode,
7247 make_compound_operation (XEXP (x, 0),
7253 /* ... fall through ... */
7259 /* If we have (ashiftrt (ashift foo C1) C2) with C2 >= C1,
7260 this is a SIGN_EXTRACT. */
7261 if (CONST_INT_P (rhs)
7262 && GET_CODE (lhs) == ASHIFT
7263 && CONST_INT_P (XEXP (lhs, 1))
7264 && INTVAL (rhs) >= INTVAL (XEXP (lhs, 1))
7265 && INTVAL (rhs) < mode_width)
7267 new_rtx = make_compound_operation (XEXP (lhs, 0), next_code);
7268 new_rtx = make_extraction (mode, new_rtx,
7269 INTVAL (rhs) - INTVAL (XEXP (lhs, 1)),
7270 NULL_RTX, mode_width - INTVAL (rhs),
7271 code == LSHIFTRT, 0, in_code == COMPARE);
7275 /* See if we have operations between an ASHIFTRT and an ASHIFT.
7276 If so, try to merge the shifts into a SIGN_EXTEND. We could
7277 also do this for some cases of SIGN_EXTRACT, but it doesn't
7278 seem worth the effort; the case checked for occurs on Alpha. */
7281 && ! (GET_CODE (lhs) == SUBREG
7282 && (OBJECT_P (SUBREG_REG (lhs))))
7283 && CONST_INT_P (rhs)
7284 && INTVAL (rhs) < HOST_BITS_PER_WIDE_INT
7285 && INTVAL (rhs) < mode_width
7286 && (new_rtx = extract_left_shift (lhs, INTVAL (rhs))) != 0)
7287 new_rtx = make_extraction (mode, make_compound_operation (new_rtx, next_code),
7288 0, NULL_RTX, mode_width - INTVAL (rhs),
7289 code == LSHIFTRT, 0, in_code == COMPARE);
7294 /* Call ourselves recursively on the inner expression. If we are
7295 narrowing the object and it has a different RTL code from
7296 what it originally did, do this SUBREG as a force_to_mode. */
7298 tem = make_compound_operation (SUBREG_REG (x), in_code);
7302 simplified = simplify_subreg (GET_MODE (x), tem, GET_MODE (tem),
7308 if (GET_CODE (tem) != GET_CODE (SUBREG_REG (x))
7309 && GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (tem))
7310 && subreg_lowpart_p (x))
7312 rtx newer = force_to_mode (tem, mode, ~(HOST_WIDE_INT) 0,
7315 /* If we have something other than a SUBREG, we might have
7316 done an expansion, so rerun ourselves. */
7317 if (GET_CODE (newer) != SUBREG)
7318 newer = make_compound_operation (newer, in_code);
7320 /* force_to_mode can expand compounds. If it just re-expanded the
7321 compound use gen_lowpart instead to convert to the desired
7323 if (rtx_equal_p (newer, x))
7324 return gen_lowpart (GET_MODE (x), tem);
7340 x = gen_lowpart (mode, new_rtx);
7341 code = GET_CODE (x);
7344 /* Now recursively process each operand of this operation. */
7345 fmt = GET_RTX_FORMAT (code);
7346 for (i = 0; i < GET_RTX_LENGTH (code); i++)
7349 new_rtx = make_compound_operation (XEXP (x, i), next_code);
7350 SUBST (XEXP (x, i), new_rtx);
7352 else if (fmt[i] == 'E')
7353 for (j = 0; j < XVECLEN (x, i); j++)
7355 new_rtx = make_compound_operation (XVECEXP (x, i, j), next_code);
7356 SUBST (XVECEXP (x, i, j), new_rtx);
7359 /* If this is a commutative operation, the changes to the operands
7360 may have made it noncanonical. */
7361 if (COMMUTATIVE_ARITH_P (x)
7362 && swap_commutative_operands_p (XEXP (x, 0), XEXP (x, 1)))
7365 SUBST (XEXP (x, 0), XEXP (x, 1));
7366 SUBST (XEXP (x, 1), tem);
7372 /* Given M see if it is a value that would select a field of bits
7373 within an item, but not the entire word. Return -1 if not.
7374 Otherwise, return the starting position of the field, where 0 is the
7377 *PLEN is set to the length of the field. */
7380 get_pos_from_mask (unsigned HOST_WIDE_INT m, unsigned HOST_WIDE_INT *plen)
7382 /* Get the bit number of the first 1 bit from the right, -1 if none. */
7383 int pos = exact_log2 (m & -m);
7387 /* Now shift off the low-order zero bits and see if we have a
7388 power of two minus 1. */
7389 len = exact_log2 ((m >> pos) + 1);
7398 /* If X refers to a register that equals REG in value, replace these
7399 references with REG. */
7401 canon_reg_for_combine (rtx x, rtx reg)
7408 enum rtx_code code = GET_CODE (x);
7409 switch (GET_RTX_CLASS (code))
7412 op0 = canon_reg_for_combine (XEXP (x, 0), reg);
7413 if (op0 != XEXP (x, 0))
7414 return simplify_gen_unary (GET_CODE (x), GET_MODE (x), op0,
7419 case RTX_COMM_ARITH:
7420 op0 = canon_reg_for_combine (XEXP (x, 0), reg);
7421 op1 = canon_reg_for_combine (XEXP (x, 1), reg);
7422 if (op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
7423 return simplify_gen_binary (GET_CODE (x), GET_MODE (x), op0, op1);
7427 case RTX_COMM_COMPARE:
7428 op0 = canon_reg_for_combine (XEXP (x, 0), reg);
7429 op1 = canon_reg_for_combine (XEXP (x, 1), reg);
7430 if (op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
7431 return simplify_gen_relational (GET_CODE (x), GET_MODE (x),
7432 GET_MODE (op0), op0, op1);
7436 case RTX_BITFIELD_OPS:
7437 op0 = canon_reg_for_combine (XEXP (x, 0), reg);
7438 op1 = canon_reg_for_combine (XEXP (x, 1), reg);
7439 op2 = canon_reg_for_combine (XEXP (x, 2), reg);
7440 if (op0 != XEXP (x, 0) || op1 != XEXP (x, 1) || op2 != XEXP (x, 2))
7441 return simplify_gen_ternary (GET_CODE (x), GET_MODE (x),
7442 GET_MODE (op0), op0, op1, op2);
7447 if (rtx_equal_p (get_last_value (reg), x)
7448 || rtx_equal_p (reg, get_last_value (x)))
7457 fmt = GET_RTX_FORMAT (code);
7459 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
7462 rtx op = canon_reg_for_combine (XEXP (x, i), reg);
7463 if (op != XEXP (x, i))
7473 else if (fmt[i] == 'E')
7476 for (j = 0; j < XVECLEN (x, i); j++)
7478 rtx op = canon_reg_for_combine (XVECEXP (x, i, j), reg);
7479 if (op != XVECEXP (x, i, j))
7486 XVECEXP (x, i, j) = op;
7497 /* Return X converted to MODE. If the value is already truncated to
7498 MODE we can just return a subreg even though in the general case we
7499 would need an explicit truncation. */
7502 gen_lowpart_or_truncate (enum machine_mode mode, rtx x)
7504 if (!CONST_INT_P (x)
7505 && GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (x))
7506 && !TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode),
7507 GET_MODE_BITSIZE (GET_MODE (x)))
7508 && !(REG_P (x) && reg_truncated_to_mode (mode, x)))
7510 /* Bit-cast X into an integer mode. */
7511 if (!SCALAR_INT_MODE_P (GET_MODE (x)))
7512 x = gen_lowpart (int_mode_for_mode (GET_MODE (x)), x);
7513 x = simplify_gen_unary (TRUNCATE, int_mode_for_mode (mode),
7517 return gen_lowpart (mode, x);
7520 /* See if X can be simplified knowing that we will only refer to it in
7521 MODE and will only refer to those bits that are nonzero in MASK.
7522 If other bits are being computed or if masking operations are done
7523 that select a superset of the bits in MASK, they can sometimes be
7526 Return a possibly simplified expression, but always convert X to
7527 MODE. If X is a CONST_INT, AND the CONST_INT with MASK.
7529 If JUST_SELECT is nonzero, don't optimize by noticing that bits in MASK
7530 are all off in X. This is used when X will be complemented, by either
7531 NOT, NEG, or XOR. */
7534 force_to_mode (rtx x, enum machine_mode mode, unsigned HOST_WIDE_INT mask,
7537 enum rtx_code code = GET_CODE (x);
7538 int next_select = just_select || code == XOR || code == NOT || code == NEG;
7539 enum machine_mode op_mode;
7540 unsigned HOST_WIDE_INT fuller_mask, nonzero;
7543 /* If this is a CALL or ASM_OPERANDS, don't do anything. Some of the
7544 code below will do the wrong thing since the mode of such an
7545 expression is VOIDmode.
7547 Also do nothing if X is a CLOBBER; this can happen if X was
7548 the return value from a call to gen_lowpart. */
7549 if (code == CALL || code == ASM_OPERANDS || code == CLOBBER)
7552 /* We want to perform the operation is its present mode unless we know
7553 that the operation is valid in MODE, in which case we do the operation
7555 op_mode = ((GET_MODE_CLASS (mode) == GET_MODE_CLASS (GET_MODE (x))
7556 && have_insn_for (code, mode))
7557 ? mode : GET_MODE (x));
7559 /* It is not valid to do a right-shift in a narrower mode
7560 than the one it came in with. */
7561 if ((code == LSHIFTRT || code == ASHIFTRT)
7562 && GET_MODE_BITSIZE (mode) < GET_MODE_BITSIZE (GET_MODE (x)))
7563 op_mode = GET_MODE (x);
7565 /* Truncate MASK to fit OP_MODE. */
7567 mask &= GET_MODE_MASK (op_mode);
7569 /* When we have an arithmetic operation, or a shift whose count we
7570 do not know, we need to assume that all bits up to the highest-order
7571 bit in MASK will be needed. This is how we form such a mask. */
7572 if (mask & ((unsigned HOST_WIDE_INT) 1 << (HOST_BITS_PER_WIDE_INT - 1)))
7573 fuller_mask = ~(unsigned HOST_WIDE_INT) 0;
7575 fuller_mask = (((unsigned HOST_WIDE_INT) 1 << (floor_log2 (mask) + 1))
7578 /* Determine what bits of X are guaranteed to be (non)zero. */
7579 nonzero = nonzero_bits (x, mode);
7581 /* If none of the bits in X are needed, return a zero. */
7582 if (!just_select && (nonzero & mask) == 0 && !side_effects_p (x))
7585 /* If X is a CONST_INT, return a new one. Do this here since the
7586 test below will fail. */
7587 if (CONST_INT_P (x))
7589 if (SCALAR_INT_MODE_P (mode))
7590 return gen_int_mode (INTVAL (x) & mask, mode);
7593 x = GEN_INT (INTVAL (x) & mask);
7594 return gen_lowpart_common (mode, x);
7598 /* If X is narrower than MODE and we want all the bits in X's mode, just
7599 get X in the proper mode. */
7600 if (GET_MODE_SIZE (GET_MODE (x)) < GET_MODE_SIZE (mode)
7601 && (GET_MODE_MASK (GET_MODE (x)) & ~mask) == 0)
7602 return gen_lowpart (mode, x);
7604 /* We can ignore the effect of a SUBREG if it narrows the mode or
7605 if the constant masks to zero all the bits the mode doesn't have. */
7606 if (GET_CODE (x) == SUBREG
7607 && subreg_lowpart_p (x)
7608 && ((GET_MODE_SIZE (GET_MODE (x))
7609 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
7611 & GET_MODE_MASK (GET_MODE (x))
7612 & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (x)))))))
7613 return force_to_mode (SUBREG_REG (x), mode, mask, next_select);
7615 /* The arithmetic simplifications here only work for scalar integer modes. */
7616 if (!SCALAR_INT_MODE_P (mode) || !SCALAR_INT_MODE_P (GET_MODE (x)))
7617 return gen_lowpart_or_truncate (mode, x);
7622 /* If X is a (clobber (const_int)), return it since we know we are
7623 generating something that won't match. */
7630 x = expand_compound_operation (x);
7631 if (GET_CODE (x) != code)
7632 return force_to_mode (x, mode, mask, next_select);
7636 /* Similarly for a truncate. */
7637 return force_to_mode (XEXP (x, 0), mode, mask, next_select);
7640 /* If this is an AND with a constant, convert it into an AND
7641 whose constant is the AND of that constant with MASK. If it
7642 remains an AND of MASK, delete it since it is redundant. */
7644 if (CONST_INT_P (XEXP (x, 1)))
7646 x = simplify_and_const_int (x, op_mode, XEXP (x, 0),
7647 mask & INTVAL (XEXP (x, 1)));
7649 /* If X is still an AND, see if it is an AND with a mask that
7650 is just some low-order bits. If so, and it is MASK, we don't
7653 if (GET_CODE (x) == AND && CONST_INT_P (XEXP (x, 1))
7654 && ((INTVAL (XEXP (x, 1)) & GET_MODE_MASK (GET_MODE (x)))
7658 /* If it remains an AND, try making another AND with the bits
7659 in the mode mask that aren't in MASK turned on. If the
7660 constant in the AND is wide enough, this might make a
7661 cheaper constant. */
7663 if (GET_CODE (x) == AND && CONST_INT_P (XEXP (x, 1))
7664 && GET_MODE_MASK (GET_MODE (x)) != mask
7665 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT)
7667 HOST_WIDE_INT cval = (INTVAL (XEXP (x, 1))
7668 | (GET_MODE_MASK (GET_MODE (x)) & ~mask));
7669 int width = GET_MODE_BITSIZE (GET_MODE (x));
7672 /* If MODE is narrower than HOST_WIDE_INT and CVAL is a negative
7673 number, sign extend it. */
7674 if (width > 0 && width < HOST_BITS_PER_WIDE_INT
7675 && (cval & ((HOST_WIDE_INT) 1 << (width - 1))) != 0)
7676 cval |= (HOST_WIDE_INT) -1 << width;
7678 y = simplify_gen_binary (AND, GET_MODE (x),
7679 XEXP (x, 0), GEN_INT (cval));
7680 if (rtx_cost (y, SET, optimize_this_for_speed_p)
7681 < rtx_cost (x, SET, optimize_this_for_speed_p))
7691 /* In (and (plus FOO C1) M), if M is a mask that just turns off
7692 low-order bits (as in an alignment operation) and FOO is already
7693 aligned to that boundary, mask C1 to that boundary as well.
7694 This may eliminate that PLUS and, later, the AND. */
7697 unsigned int width = GET_MODE_BITSIZE (mode);
7698 unsigned HOST_WIDE_INT smask = mask;
7700 /* If MODE is narrower than HOST_WIDE_INT and mask is a negative
7701 number, sign extend it. */
7703 if (width < HOST_BITS_PER_WIDE_INT
7704 && (smask & ((HOST_WIDE_INT) 1 << (width - 1))) != 0)
7705 smask |= (HOST_WIDE_INT) -1 << width;
7707 if (CONST_INT_P (XEXP (x, 1))
7708 && exact_log2 (- smask) >= 0
7709 && (nonzero_bits (XEXP (x, 0), mode) & ~smask) == 0
7710 && (INTVAL (XEXP (x, 1)) & ~smask) != 0)
7711 return force_to_mode (plus_constant (XEXP (x, 0),
7712 (INTVAL (XEXP (x, 1)) & smask)),
7713 mode, smask, next_select);
7716 /* ... fall through ... */
7719 /* For PLUS, MINUS and MULT, we need any bits less significant than the
7720 most significant bit in MASK since carries from those bits will
7721 affect the bits we are interested in. */
7726 /* If X is (minus C Y) where C's least set bit is larger than any bit
7727 in the mask, then we may replace with (neg Y). */
7728 if (CONST_INT_P (XEXP (x, 0))
7729 && (((unsigned HOST_WIDE_INT) (INTVAL (XEXP (x, 0))
7730 & -INTVAL (XEXP (x, 0))))
7733 x = simplify_gen_unary (NEG, GET_MODE (x), XEXP (x, 1),
7735 return force_to_mode (x, mode, mask, next_select);
7738 /* Similarly, if C contains every bit in the fuller_mask, then we may
7739 replace with (not Y). */
7740 if (CONST_INT_P (XEXP (x, 0))
7741 && ((INTVAL (XEXP (x, 0)) | (HOST_WIDE_INT) fuller_mask)
7742 == INTVAL (XEXP (x, 0))))
7744 x = simplify_gen_unary (NOT, GET_MODE (x),
7745 XEXP (x, 1), GET_MODE (x));
7746 return force_to_mode (x, mode, mask, next_select);
7754 /* If X is (ior (lshiftrt FOO C1) C2), try to commute the IOR and
7755 LSHIFTRT so we end up with an (and (lshiftrt (ior ...) ...) ...)
7756 operation which may be a bitfield extraction. Ensure that the
7757 constant we form is not wider than the mode of X. */
7759 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
7760 && CONST_INT_P (XEXP (XEXP (x, 0), 1))
7761 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
7762 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT
7763 && CONST_INT_P (XEXP (x, 1))
7764 && ((INTVAL (XEXP (XEXP (x, 0), 1))
7765 + floor_log2 (INTVAL (XEXP (x, 1))))
7766 < GET_MODE_BITSIZE (GET_MODE (x)))
7767 && (INTVAL (XEXP (x, 1))
7768 & ~nonzero_bits (XEXP (x, 0), GET_MODE (x))) == 0)
7770 temp = GEN_INT ((INTVAL (XEXP (x, 1)) & mask)
7771 << INTVAL (XEXP (XEXP (x, 0), 1)));
7772 temp = simplify_gen_binary (GET_CODE (x), GET_MODE (x),
7773 XEXP (XEXP (x, 0), 0), temp);
7774 x = simplify_gen_binary (LSHIFTRT, GET_MODE (x), temp,
7775 XEXP (XEXP (x, 0), 1));
7776 return force_to_mode (x, mode, mask, next_select);
7780 /* For most binary operations, just propagate into the operation and
7781 change the mode if we have an operation of that mode. */
7783 op0 = force_to_mode (XEXP (x, 0), mode, mask, next_select);
7784 op1 = force_to_mode (XEXP (x, 1), mode, mask, next_select);
7786 /* If we ended up truncating both operands, truncate the result of the
7787 operation instead. */
7788 if (GET_CODE (op0) == TRUNCATE
7789 && GET_CODE (op1) == TRUNCATE)
7791 op0 = XEXP (op0, 0);
7792 op1 = XEXP (op1, 0);
7795 op0 = gen_lowpart_or_truncate (op_mode, op0);
7796 op1 = gen_lowpart_or_truncate (op_mode, op1);
7798 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
7799 x = simplify_gen_binary (code, op_mode, op0, op1);
7803 /* For left shifts, do the same, but just for the first operand.
7804 However, we cannot do anything with shifts where we cannot
7805 guarantee that the counts are smaller than the size of the mode
7806 because such a count will have a different meaning in a
7809 if (! (CONST_INT_P (XEXP (x, 1))
7810 && INTVAL (XEXP (x, 1)) >= 0
7811 && INTVAL (XEXP (x, 1)) < GET_MODE_BITSIZE (mode))
7812 && ! (GET_MODE (XEXP (x, 1)) != VOIDmode
7813 && (nonzero_bits (XEXP (x, 1), GET_MODE (XEXP (x, 1)))
7814 < (unsigned HOST_WIDE_INT) GET_MODE_BITSIZE (mode))))
7817 /* If the shift count is a constant and we can do arithmetic in
7818 the mode of the shift, refine which bits we need. Otherwise, use the
7819 conservative form of the mask. */
7820 if (CONST_INT_P (XEXP (x, 1))
7821 && INTVAL (XEXP (x, 1)) >= 0
7822 && INTVAL (XEXP (x, 1)) < GET_MODE_BITSIZE (op_mode)
7823 && GET_MODE_BITSIZE (op_mode) <= HOST_BITS_PER_WIDE_INT)
7824 mask >>= INTVAL (XEXP (x, 1));
7828 op0 = gen_lowpart_or_truncate (op_mode,
7829 force_to_mode (XEXP (x, 0), op_mode,
7830 mask, next_select));
7832 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0))
7833 x = simplify_gen_binary (code, op_mode, op0, XEXP (x, 1));
7837 /* Here we can only do something if the shift count is a constant,
7838 this shift constant is valid for the host, and we can do arithmetic
7841 if (CONST_INT_P (XEXP (x, 1))
7842 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT
7843 && GET_MODE_BITSIZE (op_mode) <= HOST_BITS_PER_WIDE_INT)
7845 rtx inner = XEXP (x, 0);
7846 unsigned HOST_WIDE_INT inner_mask;
7848 /* Select the mask of the bits we need for the shift operand. */
7849 inner_mask = mask << INTVAL (XEXP (x, 1));
7851 /* We can only change the mode of the shift if we can do arithmetic
7852 in the mode of the shift and INNER_MASK is no wider than the
7853 width of X's mode. */
7854 if ((inner_mask & ~GET_MODE_MASK (GET_MODE (x))) != 0)
7855 op_mode = GET_MODE (x);
7857 inner = force_to_mode (inner, op_mode, inner_mask, next_select);
7859 if (GET_MODE (x) != op_mode || inner != XEXP (x, 0))
7860 x = simplify_gen_binary (LSHIFTRT, op_mode, inner, XEXP (x, 1));
7863 /* If we have (and (lshiftrt FOO C1) C2) where the combination of the
7864 shift and AND produces only copies of the sign bit (C2 is one less
7865 than a power of two), we can do this with just a shift. */
7867 if (GET_CODE (x) == LSHIFTRT
7868 && CONST_INT_P (XEXP (x, 1))
7869 /* The shift puts one of the sign bit copies in the least significant
7871 && ((INTVAL (XEXP (x, 1))
7872 + num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0))))
7873 >= GET_MODE_BITSIZE (GET_MODE (x)))
7874 && exact_log2 (mask + 1) >= 0
7875 /* Number of bits left after the shift must be more than the mask
7877 && ((INTVAL (XEXP (x, 1)) + exact_log2 (mask + 1))
7878 <= GET_MODE_BITSIZE (GET_MODE (x)))
7879 /* Must be more sign bit copies than the mask needs. */
7880 && ((int) num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
7881 >= exact_log2 (mask + 1)))
7882 x = simplify_gen_binary (LSHIFTRT, GET_MODE (x), XEXP (x, 0),
7883 GEN_INT (GET_MODE_BITSIZE (GET_MODE (x))
7884 - exact_log2 (mask + 1)));
7889 /* If we are just looking for the sign bit, we don't need this shift at
7890 all, even if it has a variable count. */
7891 if (GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
7892 && (mask == ((unsigned HOST_WIDE_INT) 1
7893 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
7894 return force_to_mode (XEXP (x, 0), mode, mask, next_select);
7896 /* If this is a shift by a constant, get a mask that contains those bits
7897 that are not copies of the sign bit. We then have two cases: If
7898 MASK only includes those bits, this can be a logical shift, which may
7899 allow simplifications. If MASK is a single-bit field not within
7900 those bits, we are requesting a copy of the sign bit and hence can
7901 shift the sign bit to the appropriate location. */
7903 if (CONST_INT_P (XEXP (x, 1)) && INTVAL (XEXP (x, 1)) >= 0
7904 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT)
7908 /* If the considered data is wider than HOST_WIDE_INT, we can't
7909 represent a mask for all its bits in a single scalar.
7910 But we only care about the lower bits, so calculate these. */
7912 if (GET_MODE_BITSIZE (GET_MODE (x)) > HOST_BITS_PER_WIDE_INT)
7914 nonzero = ~(HOST_WIDE_INT) 0;
7916 /* GET_MODE_BITSIZE (GET_MODE (x)) - INTVAL (XEXP (x, 1))
7917 is the number of bits a full-width mask would have set.
7918 We need only shift if these are fewer than nonzero can
7919 hold. If not, we must keep all bits set in nonzero. */
7921 if (GET_MODE_BITSIZE (GET_MODE (x)) - INTVAL (XEXP (x, 1))
7922 < HOST_BITS_PER_WIDE_INT)
7923 nonzero >>= INTVAL (XEXP (x, 1))
7924 + HOST_BITS_PER_WIDE_INT
7925 - GET_MODE_BITSIZE (GET_MODE (x)) ;
7929 nonzero = GET_MODE_MASK (GET_MODE (x));
7930 nonzero >>= INTVAL (XEXP (x, 1));
7933 if ((mask & ~nonzero) == 0)
7935 x = simplify_shift_const (NULL_RTX, LSHIFTRT, GET_MODE (x),
7936 XEXP (x, 0), INTVAL (XEXP (x, 1)));
7937 if (GET_CODE (x) != ASHIFTRT)
7938 return force_to_mode (x, mode, mask, next_select);
7941 else if ((i = exact_log2 (mask)) >= 0)
7943 x = simplify_shift_const
7944 (NULL_RTX, LSHIFTRT, GET_MODE (x), XEXP (x, 0),
7945 GET_MODE_BITSIZE (GET_MODE (x)) - 1 - i);
7947 if (GET_CODE (x) != ASHIFTRT)
7948 return force_to_mode (x, mode, mask, next_select);
7952 /* If MASK is 1, convert this to an LSHIFTRT. This can be done
7953 even if the shift count isn't a constant. */
7955 x = simplify_gen_binary (LSHIFTRT, GET_MODE (x),
7956 XEXP (x, 0), XEXP (x, 1));
7960 /* If this is a zero- or sign-extension operation that just affects bits
7961 we don't care about, remove it. Be sure the call above returned
7962 something that is still a shift. */
7964 if ((GET_CODE (x) == LSHIFTRT || GET_CODE (x) == ASHIFTRT)
7965 && CONST_INT_P (XEXP (x, 1))
7966 && INTVAL (XEXP (x, 1)) >= 0
7967 && (INTVAL (XEXP (x, 1))
7968 <= GET_MODE_BITSIZE (GET_MODE (x)) - (floor_log2 (mask) + 1))
7969 && GET_CODE (XEXP (x, 0)) == ASHIFT
7970 && XEXP (XEXP (x, 0), 1) == XEXP (x, 1))
7971 return force_to_mode (XEXP (XEXP (x, 0), 0), mode, mask,
7978 /* If the shift count is constant and we can do computations
7979 in the mode of X, compute where the bits we care about are.
7980 Otherwise, we can't do anything. Don't change the mode of
7981 the shift or propagate MODE into the shift, though. */
7982 if (CONST_INT_P (XEXP (x, 1))
7983 && INTVAL (XEXP (x, 1)) >= 0)
7985 temp = simplify_binary_operation (code == ROTATE ? ROTATERT : ROTATE,
7986 GET_MODE (x), GEN_INT (mask),
7988 if (temp && CONST_INT_P (temp))
7990 force_to_mode (XEXP (x, 0), GET_MODE (x),
7991 INTVAL (temp), next_select));
7996 /* If we just want the low-order bit, the NEG isn't needed since it
7997 won't change the low-order bit. */
7999 return force_to_mode (XEXP (x, 0), mode, mask, just_select);
8001 /* We need any bits less significant than the most significant bit in
8002 MASK since carries from those bits will affect the bits we are
8008 /* (not FOO) is (xor FOO CONST), so if FOO is an LSHIFTRT, we can do the
8009 same as the XOR case above. Ensure that the constant we form is not
8010 wider than the mode of X. */
8012 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
8013 && CONST_INT_P (XEXP (XEXP (x, 0), 1))
8014 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
8015 && (INTVAL (XEXP (XEXP (x, 0), 1)) + floor_log2 (mask)
8016 < GET_MODE_BITSIZE (GET_MODE (x)))
8017 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT)
8019 temp = gen_int_mode (mask << INTVAL (XEXP (XEXP (x, 0), 1)),
8021 temp = simplify_gen_binary (XOR, GET_MODE (x),
8022 XEXP (XEXP (x, 0), 0), temp);
8023 x = simplify_gen_binary (LSHIFTRT, GET_MODE (x),
8024 temp, XEXP (XEXP (x, 0), 1));
8026 return force_to_mode (x, mode, mask, next_select);
8029 /* (and (not FOO) CONST) is (not (or FOO (not CONST))), so we must
8030 use the full mask inside the NOT. */
8034 op0 = gen_lowpart_or_truncate (op_mode,
8035 force_to_mode (XEXP (x, 0), mode, mask,
8037 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0))
8038 x = simplify_gen_unary (code, op_mode, op0, op_mode);
8042 /* (and (ne FOO 0) CONST) can be (and FOO CONST) if CONST is included
8043 in STORE_FLAG_VALUE and FOO has a single bit that might be nonzero,
8044 which is equal to STORE_FLAG_VALUE. */
8045 if ((mask & ~STORE_FLAG_VALUE) == 0 && XEXP (x, 1) == const0_rtx
8046 && GET_MODE (XEXP (x, 0)) == mode
8047 && exact_log2 (nonzero_bits (XEXP (x, 0), mode)) >= 0
8048 && (nonzero_bits (XEXP (x, 0), mode)
8049 == (unsigned HOST_WIDE_INT) STORE_FLAG_VALUE))
8050 return force_to_mode (XEXP (x, 0), mode, mask, next_select);
8055 /* We have no way of knowing if the IF_THEN_ELSE can itself be
8056 written in a narrower mode. We play it safe and do not do so. */
8059 gen_lowpart_or_truncate (GET_MODE (x),
8060 force_to_mode (XEXP (x, 1), mode,
8061 mask, next_select)));
8063 gen_lowpart_or_truncate (GET_MODE (x),
8064 force_to_mode (XEXP (x, 2), mode,
8065 mask, next_select)));
8072 /* Ensure we return a value of the proper mode. */
8073 return gen_lowpart_or_truncate (mode, x);
8076 /* Return nonzero if X is an expression that has one of two values depending on
8077 whether some other value is zero or nonzero. In that case, we return the
8078 value that is being tested, *PTRUE is set to the value if the rtx being
8079 returned has a nonzero value, and *PFALSE is set to the other alternative.
8081 If we return zero, we set *PTRUE and *PFALSE to X. */
8084 if_then_else_cond (rtx x, rtx *ptrue, rtx *pfalse)
8086 enum machine_mode mode = GET_MODE (x);
8087 enum rtx_code code = GET_CODE (x);
8088 rtx cond0, cond1, true0, true1, false0, false1;
8089 unsigned HOST_WIDE_INT nz;
8091 /* If we are comparing a value against zero, we are done. */
8092 if ((code == NE || code == EQ)
8093 && XEXP (x, 1) == const0_rtx)
8095 *ptrue = (code == NE) ? const_true_rtx : const0_rtx;
8096 *pfalse = (code == NE) ? const0_rtx : const_true_rtx;
8100 /* If this is a unary operation whose operand has one of two values, apply
8101 our opcode to compute those values. */
8102 else if (UNARY_P (x)
8103 && (cond0 = if_then_else_cond (XEXP (x, 0), &true0, &false0)) != 0)
8105 *ptrue = simplify_gen_unary (code, mode, true0, GET_MODE (XEXP (x, 0)));
8106 *pfalse = simplify_gen_unary (code, mode, false0,
8107 GET_MODE (XEXP (x, 0)));
8111 /* If this is a COMPARE, do nothing, since the IF_THEN_ELSE we would
8112 make can't possibly match and would suppress other optimizations. */
8113 else if (code == COMPARE)
8116 /* If this is a binary operation, see if either side has only one of two
8117 values. If either one does or if both do and they are conditional on
8118 the same value, compute the new true and false values. */
8119 else if (BINARY_P (x))
8121 cond0 = if_then_else_cond (XEXP (x, 0), &true0, &false0);
8122 cond1 = if_then_else_cond (XEXP (x, 1), &true1, &false1);
8124 if ((cond0 != 0 || cond1 != 0)
8125 && ! (cond0 != 0 && cond1 != 0 && ! rtx_equal_p (cond0, cond1)))
8127 /* If if_then_else_cond returned zero, then true/false are the
8128 same rtl. We must copy one of them to prevent invalid rtl
8131 true0 = copy_rtx (true0);
8132 else if (cond1 == 0)
8133 true1 = copy_rtx (true1);
8135 if (COMPARISON_P (x))
8137 *ptrue = simplify_gen_relational (code, mode, VOIDmode,
8139 *pfalse = simplify_gen_relational (code, mode, VOIDmode,
8144 *ptrue = simplify_gen_binary (code, mode, true0, true1);
8145 *pfalse = simplify_gen_binary (code, mode, false0, false1);
8148 return cond0 ? cond0 : cond1;
8151 /* See if we have PLUS, IOR, XOR, MINUS or UMAX, where one of the
8152 operands is zero when the other is nonzero, and vice-versa,
8153 and STORE_FLAG_VALUE is 1 or -1. */
8155 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
8156 && (code == PLUS || code == IOR || code == XOR || code == MINUS
8158 && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT)
8160 rtx op0 = XEXP (XEXP (x, 0), 1);
8161 rtx op1 = XEXP (XEXP (x, 1), 1);
8163 cond0 = XEXP (XEXP (x, 0), 0);
8164 cond1 = XEXP (XEXP (x, 1), 0);
8166 if (COMPARISON_P (cond0)
8167 && COMPARISON_P (cond1)
8168 && ((GET_CODE (cond0) == reversed_comparison_code (cond1, NULL)
8169 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0))
8170 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1)))
8171 || ((swap_condition (GET_CODE (cond0))
8172 == reversed_comparison_code (cond1, NULL))
8173 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1))
8174 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0))))
8175 && ! side_effects_p (x))
8177 *ptrue = simplify_gen_binary (MULT, mode, op0, const_true_rtx);
8178 *pfalse = simplify_gen_binary (MULT, mode,
8180 ? simplify_gen_unary (NEG, mode,
8188 /* Similarly for MULT, AND and UMIN, except that for these the result
8190 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
8191 && (code == MULT || code == AND || code == UMIN)
8192 && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT)
8194 cond0 = XEXP (XEXP (x, 0), 0);
8195 cond1 = XEXP (XEXP (x, 1), 0);
8197 if (COMPARISON_P (cond0)
8198 && COMPARISON_P (cond1)
8199 && ((GET_CODE (cond0) == reversed_comparison_code (cond1, NULL)
8200 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0))
8201 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1)))
8202 || ((swap_condition (GET_CODE (cond0))
8203 == reversed_comparison_code (cond1, NULL))
8204 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1))
8205 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0))))
8206 && ! side_effects_p (x))
8208 *ptrue = *pfalse = const0_rtx;
8214 else if (code == IF_THEN_ELSE)
8216 /* If we have IF_THEN_ELSE already, extract the condition and
8217 canonicalize it if it is NE or EQ. */
8218 cond0 = XEXP (x, 0);
8219 *ptrue = XEXP (x, 1), *pfalse = XEXP (x, 2);
8220 if (GET_CODE (cond0) == NE && XEXP (cond0, 1) == const0_rtx)
8221 return XEXP (cond0, 0);
8222 else if (GET_CODE (cond0) == EQ && XEXP (cond0, 1) == const0_rtx)
8224 *ptrue = XEXP (x, 2), *pfalse = XEXP (x, 1);
8225 return XEXP (cond0, 0);
8231 /* If X is a SUBREG, we can narrow both the true and false values
8232 if the inner expression, if there is a condition. */
8233 else if (code == SUBREG
8234 && 0 != (cond0 = if_then_else_cond (SUBREG_REG (x),
8237 true0 = simplify_gen_subreg (mode, true0,
8238 GET_MODE (SUBREG_REG (x)), SUBREG_BYTE (x));
8239 false0 = simplify_gen_subreg (mode, false0,
8240 GET_MODE (SUBREG_REG (x)), SUBREG_BYTE (x));
8241 if (true0 && false0)
8249 /* If X is a constant, this isn't special and will cause confusions
8250 if we treat it as such. Likewise if it is equivalent to a constant. */
8251 else if (CONSTANT_P (x)
8252 || ((cond0 = get_last_value (x)) != 0 && CONSTANT_P (cond0)))
8255 /* If we're in BImode, canonicalize on 0 and STORE_FLAG_VALUE, as that
8256 will be least confusing to the rest of the compiler. */
8257 else if (mode == BImode)
8259 *ptrue = GEN_INT (STORE_FLAG_VALUE), *pfalse = const0_rtx;
8263 /* If X is known to be either 0 or -1, those are the true and
8264 false values when testing X. */
8265 else if (x == constm1_rtx || x == const0_rtx
8266 || (mode != VOIDmode
8267 && num_sign_bit_copies (x, mode) == GET_MODE_BITSIZE (mode)))
8269 *ptrue = constm1_rtx, *pfalse = const0_rtx;
8273 /* Likewise for 0 or a single bit. */
8274 else if (SCALAR_INT_MODE_P (mode)
8275 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
8276 && exact_log2 (nz = nonzero_bits (x, mode)) >= 0)
8278 *ptrue = gen_int_mode (nz, mode), *pfalse = const0_rtx;
8282 /* Otherwise fail; show no condition with true and false values the same. */
8283 *ptrue = *pfalse = x;
8287 /* Return the value of expression X given the fact that condition COND
8288 is known to be true when applied to REG as its first operand and VAL
8289 as its second. X is known to not be shared and so can be modified in
8292 We only handle the simplest cases, and specifically those cases that
8293 arise with IF_THEN_ELSE expressions. */
8296 known_cond (rtx x, enum rtx_code cond, rtx reg, rtx val)
8298 enum rtx_code code = GET_CODE (x);
8303 if (side_effects_p (x))
8306 /* If either operand of the condition is a floating point value,
8307 then we have to avoid collapsing an EQ comparison. */
8309 && rtx_equal_p (x, reg)
8310 && ! FLOAT_MODE_P (GET_MODE (x))
8311 && ! FLOAT_MODE_P (GET_MODE (val)))
8314 if (cond == UNEQ && rtx_equal_p (x, reg))
8317 /* If X is (abs REG) and we know something about REG's relationship
8318 with zero, we may be able to simplify this. */
8320 if (code == ABS && rtx_equal_p (XEXP (x, 0), reg) && val == const0_rtx)
8323 case GE: case GT: case EQ:
8326 return simplify_gen_unary (NEG, GET_MODE (XEXP (x, 0)),
8328 GET_MODE (XEXP (x, 0)));
8333 /* The only other cases we handle are MIN, MAX, and comparisons if the
8334 operands are the same as REG and VAL. */
8336 else if (COMPARISON_P (x) || COMMUTATIVE_ARITH_P (x))
8338 if (rtx_equal_p (XEXP (x, 0), val))
8339 cond = swap_condition (cond), temp = val, val = reg, reg = temp;
8341 if (rtx_equal_p (XEXP (x, 0), reg) && rtx_equal_p (XEXP (x, 1), val))
8343 if (COMPARISON_P (x))
8345 if (comparison_dominates_p (cond, code))
8346 return const_true_rtx;
8348 code = reversed_comparison_code (x, NULL);
8350 && comparison_dominates_p (cond, code))
8355 else if (code == SMAX || code == SMIN
8356 || code == UMIN || code == UMAX)
8358 int unsignedp = (code == UMIN || code == UMAX);
8360 /* Do not reverse the condition when it is NE or EQ.
8361 This is because we cannot conclude anything about
8362 the value of 'SMAX (x, y)' when x is not equal to y,
8363 but we can when x equals y. */
8364 if ((code == SMAX || code == UMAX)
8365 && ! (cond == EQ || cond == NE))
8366 cond = reverse_condition (cond);
8371 return unsignedp ? x : XEXP (x, 1);
8373 return unsignedp ? x : XEXP (x, 0);
8375 return unsignedp ? XEXP (x, 1) : x;
8377 return unsignedp ? XEXP (x, 0) : x;
8384 else if (code == SUBREG)
8386 enum machine_mode inner_mode = GET_MODE (SUBREG_REG (x));
8387 rtx new_rtx, r = known_cond (SUBREG_REG (x), cond, reg, val);
8389 if (SUBREG_REG (x) != r)
8391 /* We must simplify subreg here, before we lose track of the
8392 original inner_mode. */
8393 new_rtx = simplify_subreg (GET_MODE (x), r,
8394 inner_mode, SUBREG_BYTE (x));
8398 SUBST (SUBREG_REG (x), r);
8403 /* We don't have to handle SIGN_EXTEND here, because even in the
8404 case of replacing something with a modeless CONST_INT, a
8405 CONST_INT is already (supposed to be) a valid sign extension for
8406 its narrower mode, which implies it's already properly
8407 sign-extended for the wider mode. Now, for ZERO_EXTEND, the
8408 story is different. */
8409 else if (code == ZERO_EXTEND)
8411 enum machine_mode inner_mode = GET_MODE (XEXP (x, 0));
8412 rtx new_rtx, r = known_cond (XEXP (x, 0), cond, reg, val);
8414 if (XEXP (x, 0) != r)
8416 /* We must simplify the zero_extend here, before we lose
8417 track of the original inner_mode. */
8418 new_rtx = simplify_unary_operation (ZERO_EXTEND, GET_MODE (x),
8423 SUBST (XEXP (x, 0), r);
8429 fmt = GET_RTX_FORMAT (code);
8430 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
8433 SUBST (XEXP (x, i), known_cond (XEXP (x, i), cond, reg, val));
8434 else if (fmt[i] == 'E')
8435 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
8436 SUBST (XVECEXP (x, i, j), known_cond (XVECEXP (x, i, j),
8443 /* See if X and Y are equal for the purposes of seeing if we can rewrite an
8444 assignment as a field assignment. */
8447 rtx_equal_for_field_assignment_p (rtx x, rtx y)
8449 if (x == y || rtx_equal_p (x, y))
8452 if (x == 0 || y == 0 || GET_MODE (x) != GET_MODE (y))
8455 /* Check for a paradoxical SUBREG of a MEM compared with the MEM.
8456 Note that all SUBREGs of MEM are paradoxical; otherwise they
8457 would have been rewritten. */
8458 if (MEM_P (x) && GET_CODE (y) == SUBREG
8459 && MEM_P (SUBREG_REG (y))
8460 && rtx_equal_p (SUBREG_REG (y),
8461 gen_lowpart (GET_MODE (SUBREG_REG (y)), x)))
8464 if (MEM_P (y) && GET_CODE (x) == SUBREG
8465 && MEM_P (SUBREG_REG (x))
8466 && rtx_equal_p (SUBREG_REG (x),
8467 gen_lowpart (GET_MODE (SUBREG_REG (x)), y)))
8470 /* We used to see if get_last_value of X and Y were the same but that's
8471 not correct. In one direction, we'll cause the assignment to have
8472 the wrong destination and in the case, we'll import a register into this
8473 insn that might have already have been dead. So fail if none of the
8474 above cases are true. */
8478 /* See if X, a SET operation, can be rewritten as a bit-field assignment.
8479 Return that assignment if so.
8481 We only handle the most common cases. */
8484 make_field_assignment (rtx x)
8486 rtx dest = SET_DEST (x);
8487 rtx src = SET_SRC (x);
8492 unsigned HOST_WIDE_INT len;
8494 enum machine_mode mode;
8496 /* If SRC was (and (not (ashift (const_int 1) POS)) DEST), this is
8497 a clear of a one-bit field. We will have changed it to
8498 (and (rotate (const_int -2) POS) DEST), so check for that. Also check
8501 if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == ROTATE
8502 && CONST_INT_P (XEXP (XEXP (src, 0), 0))
8503 && INTVAL (XEXP (XEXP (src, 0), 0)) == -2
8504 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
8506 assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1),
8509 return gen_rtx_SET (VOIDmode, assign, const0_rtx);
8513 if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == SUBREG
8514 && subreg_lowpart_p (XEXP (src, 0))
8515 && (GET_MODE_SIZE (GET_MODE (XEXP (src, 0)))
8516 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (src, 0)))))
8517 && GET_CODE (SUBREG_REG (XEXP (src, 0))) == ROTATE
8518 && CONST_INT_P (XEXP (SUBREG_REG (XEXP (src, 0)), 0))
8519 && INTVAL (XEXP (SUBREG_REG (XEXP (src, 0)), 0)) == -2
8520 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
8522 assign = make_extraction (VOIDmode, dest, 0,
8523 XEXP (SUBREG_REG (XEXP (src, 0)), 1),
8526 return gen_rtx_SET (VOIDmode, assign, const0_rtx);
8530 /* If SRC is (ior (ashift (const_int 1) POS) DEST), this is a set of a
8532 if (GET_CODE (src) == IOR && GET_CODE (XEXP (src, 0)) == ASHIFT
8533 && XEXP (XEXP (src, 0), 0) == const1_rtx
8534 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
8536 assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1),
8539 return gen_rtx_SET (VOIDmode, assign, const1_rtx);
8543 /* If DEST is already a field assignment, i.e. ZERO_EXTRACT, and the
8544 SRC is an AND with all bits of that field set, then we can discard
8546 if (GET_CODE (dest) == ZERO_EXTRACT
8547 && CONST_INT_P (XEXP (dest, 1))
8548 && GET_CODE (src) == AND
8549 && CONST_INT_P (XEXP (src, 1)))
8551 HOST_WIDE_INT width = INTVAL (XEXP (dest, 1));
8552 unsigned HOST_WIDE_INT and_mask = INTVAL (XEXP (src, 1));
8553 unsigned HOST_WIDE_INT ze_mask;
8555 if (width >= HOST_BITS_PER_WIDE_INT)
8558 ze_mask = ((unsigned HOST_WIDE_INT)1 << width) - 1;
8560 /* Complete overlap. We can remove the source AND. */
8561 if ((and_mask & ze_mask) == ze_mask)
8562 return gen_rtx_SET (VOIDmode, dest, XEXP (src, 0));
8564 /* Partial overlap. We can reduce the source AND. */
8565 if ((and_mask & ze_mask) != and_mask)
8567 mode = GET_MODE (src);
8568 src = gen_rtx_AND (mode, XEXP (src, 0),
8569 gen_int_mode (and_mask & ze_mask, mode));
8570 return gen_rtx_SET (VOIDmode, dest, src);
8574 /* The other case we handle is assignments into a constant-position
8575 field. They look like (ior/xor (and DEST C1) OTHER). If C1 represents
8576 a mask that has all one bits except for a group of zero bits and
8577 OTHER is known to have zeros where C1 has ones, this is such an
8578 assignment. Compute the position and length from C1. Shift OTHER
8579 to the appropriate position, force it to the required mode, and
8580 make the extraction. Check for the AND in both operands. */
8582 if (GET_CODE (src) != IOR && GET_CODE (src) != XOR)
8585 rhs = expand_compound_operation (XEXP (src, 0));
8586 lhs = expand_compound_operation (XEXP (src, 1));
8588 if (GET_CODE (rhs) == AND
8589 && CONST_INT_P (XEXP (rhs, 1))
8590 && rtx_equal_for_field_assignment_p (XEXP (rhs, 0), dest))
8591 c1 = INTVAL (XEXP (rhs, 1)), other = lhs;
8592 else if (GET_CODE (lhs) == AND
8593 && CONST_INT_P (XEXP (lhs, 1))
8594 && rtx_equal_for_field_assignment_p (XEXP (lhs, 0), dest))
8595 c1 = INTVAL (XEXP (lhs, 1)), other = rhs;
8599 pos = get_pos_from_mask ((~c1) & GET_MODE_MASK (GET_MODE (dest)), &len);
8600 if (pos < 0 || pos + len > GET_MODE_BITSIZE (GET_MODE (dest))
8601 || GET_MODE_BITSIZE (GET_MODE (dest)) > HOST_BITS_PER_WIDE_INT
8602 || (c1 & nonzero_bits (other, GET_MODE (dest))) != 0)
8605 assign = make_extraction (VOIDmode, dest, pos, NULL_RTX, len, 1, 1, 0);
8609 /* The mode to use for the source is the mode of the assignment, or of
8610 what is inside a possible STRICT_LOW_PART. */
8611 mode = (GET_CODE (assign) == STRICT_LOW_PART
8612 ? GET_MODE (XEXP (assign, 0)) : GET_MODE (assign));
8614 /* Shift OTHER right POS places and make it the source, restricting it
8615 to the proper length and mode. */
8617 src = canon_reg_for_combine (simplify_shift_const (NULL_RTX, LSHIFTRT,
8621 src = force_to_mode (src, mode,
8622 GET_MODE_BITSIZE (mode) >= HOST_BITS_PER_WIDE_INT
8623 ? ~(unsigned HOST_WIDE_INT) 0
8624 : ((unsigned HOST_WIDE_INT) 1 << len) - 1,
8627 /* If SRC is masked by an AND that does not make a difference in
8628 the value being stored, strip it. */
8629 if (GET_CODE (assign) == ZERO_EXTRACT
8630 && CONST_INT_P (XEXP (assign, 1))
8631 && INTVAL (XEXP (assign, 1)) < HOST_BITS_PER_WIDE_INT
8632 && GET_CODE (src) == AND
8633 && CONST_INT_P (XEXP (src, 1))
8634 && ((unsigned HOST_WIDE_INT) INTVAL (XEXP (src, 1))
8635 == ((unsigned HOST_WIDE_INT) 1 << INTVAL (XEXP (assign, 1))) - 1))
8636 src = XEXP (src, 0);
8638 return gen_rtx_SET (VOIDmode, assign, src);
8641 /* See if X is of the form (+ (* a c) (* b c)) and convert to (* (+ a b) c)
8645 apply_distributive_law (rtx x)
8647 enum rtx_code code = GET_CODE (x);
8648 enum rtx_code inner_code;
8649 rtx lhs, rhs, other;
8652 /* Distributivity is not true for floating point as it can change the
8653 value. So we don't do it unless -funsafe-math-optimizations. */
8654 if (FLOAT_MODE_P (GET_MODE (x))
8655 && ! flag_unsafe_math_optimizations)
8658 /* The outer operation can only be one of the following: */
8659 if (code != IOR && code != AND && code != XOR
8660 && code != PLUS && code != MINUS)
8666 /* If either operand is a primitive we can't do anything, so get out
8668 if (OBJECT_P (lhs) || OBJECT_P (rhs))
8671 lhs = expand_compound_operation (lhs);
8672 rhs = expand_compound_operation (rhs);
8673 inner_code = GET_CODE (lhs);
8674 if (inner_code != GET_CODE (rhs))
8677 /* See if the inner and outer operations distribute. */
8684 /* These all distribute except over PLUS. */
8685 if (code == PLUS || code == MINUS)
8690 if (code != PLUS && code != MINUS)
8695 /* This is also a multiply, so it distributes over everything. */
8699 /* Non-paradoxical SUBREGs distributes over all operations,
8700 provided the inner modes and byte offsets are the same, this
8701 is an extraction of a low-order part, we don't convert an fp
8702 operation to int or vice versa, this is not a vector mode,
8703 and we would not be converting a single-word operation into a
8704 multi-word operation. The latter test is not required, but
8705 it prevents generating unneeded multi-word operations. Some
8706 of the previous tests are redundant given the latter test,
8707 but are retained because they are required for correctness.
8709 We produce the result slightly differently in this case. */
8711 if (GET_MODE (SUBREG_REG (lhs)) != GET_MODE (SUBREG_REG (rhs))
8712 || SUBREG_BYTE (lhs) != SUBREG_BYTE (rhs)
8713 || ! subreg_lowpart_p (lhs)
8714 || (GET_MODE_CLASS (GET_MODE (lhs))
8715 != GET_MODE_CLASS (GET_MODE (SUBREG_REG (lhs))))
8716 || (GET_MODE_SIZE (GET_MODE (lhs))
8717 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs))))
8718 || VECTOR_MODE_P (GET_MODE (lhs))
8719 || GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs))) > UNITS_PER_WORD
8720 /* Result might need to be truncated. Don't change mode if
8721 explicit truncation is needed. */
8722 || !TRULY_NOOP_TRUNCATION
8723 (GET_MODE_BITSIZE (GET_MODE (x)),
8724 GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (lhs)))))
8727 tem = simplify_gen_binary (code, GET_MODE (SUBREG_REG (lhs)),
8728 SUBREG_REG (lhs), SUBREG_REG (rhs));
8729 return gen_lowpart (GET_MODE (x), tem);
8735 /* Set LHS and RHS to the inner operands (A and B in the example
8736 above) and set OTHER to the common operand (C in the example).
8737 There is only one way to do this unless the inner operation is
8739 if (COMMUTATIVE_ARITH_P (lhs)
8740 && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 0)))
8741 other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 1);
8742 else if (COMMUTATIVE_ARITH_P (lhs)
8743 && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 1)))
8744 other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 0);
8745 else if (COMMUTATIVE_ARITH_P (lhs)
8746 && rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 0)))
8747 other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 1);
8748 else if (rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 1)))
8749 other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 0);
8753 /* Form the new inner operation, seeing if it simplifies first. */
8754 tem = simplify_gen_binary (code, GET_MODE (x), lhs, rhs);
8756 /* There is one exception to the general way of distributing:
8757 (a | c) ^ (b | c) -> (a ^ b) & ~c */
8758 if (code == XOR && inner_code == IOR)
8761 other = simplify_gen_unary (NOT, GET_MODE (x), other, GET_MODE (x));
8764 /* We may be able to continuing distributing the result, so call
8765 ourselves recursively on the inner operation before forming the
8766 outer operation, which we return. */
8767 return simplify_gen_binary (inner_code, GET_MODE (x),
8768 apply_distributive_law (tem), other);
8771 /* See if X is of the form (* (+ A B) C), and if so convert to
8772 (+ (* A C) (* B C)) and try to simplify.
8774 Most of the time, this results in no change. However, if some of
8775 the operands are the same or inverses of each other, simplifications
8778 For example, (and (ior A B) (not B)) can occur as the result of
8779 expanding a bit field assignment. When we apply the distributive
8780 law to this, we get (ior (and (A (not B))) (and (B (not B)))),
8781 which then simplifies to (and (A (not B))).
8783 Note that no checks happen on the validity of applying the inverse
8784 distributive law. This is pointless since we can do it in the
8785 few places where this routine is called.
8787 N is the index of the term that is decomposed (the arithmetic operation,
8788 i.e. (+ A B) in the first example above). !N is the index of the term that
8789 is distributed, i.e. of C in the first example above. */
8791 distribute_and_simplify_rtx (rtx x, int n)
8793 enum machine_mode mode;
8794 enum rtx_code outer_code, inner_code;
8795 rtx decomposed, distributed, inner_op0, inner_op1, new_op0, new_op1, tmp;
8797 /* Distributivity is not true for floating point as it can change the
8798 value. So we don't do it unless -funsafe-math-optimizations. */
8799 if (FLOAT_MODE_P (GET_MODE (x))
8800 && ! flag_unsafe_math_optimizations)
8803 decomposed = XEXP (x, n);
8804 if (!ARITHMETIC_P (decomposed))
8807 mode = GET_MODE (x);
8808 outer_code = GET_CODE (x);
8809 distributed = XEXP (x, !n);
8811 inner_code = GET_CODE (decomposed);
8812 inner_op0 = XEXP (decomposed, 0);
8813 inner_op1 = XEXP (decomposed, 1);
8815 /* Special case (and (xor B C) (not A)), which is equivalent to
8816 (xor (ior A B) (ior A C)) */
8817 if (outer_code == AND && inner_code == XOR && GET_CODE (distributed) == NOT)
8819 distributed = XEXP (distributed, 0);
8825 /* Distribute the second term. */
8826 new_op0 = simplify_gen_binary (outer_code, mode, inner_op0, distributed);
8827 new_op1 = simplify_gen_binary (outer_code, mode, inner_op1, distributed);
8831 /* Distribute the first term. */
8832 new_op0 = simplify_gen_binary (outer_code, mode, distributed, inner_op0);
8833 new_op1 = simplify_gen_binary (outer_code, mode, distributed, inner_op1);
8836 tmp = apply_distributive_law (simplify_gen_binary (inner_code, mode,
8838 if (GET_CODE (tmp) != outer_code
8839 && rtx_cost (tmp, SET, optimize_this_for_speed_p)
8840 < rtx_cost (x, SET, optimize_this_for_speed_p))
8846 /* Simplify a logical `and' of VAROP with the constant CONSTOP, to be done
8847 in MODE. Return an equivalent form, if different from (and VAROP
8848 (const_int CONSTOP)). Otherwise, return NULL_RTX. */
8851 simplify_and_const_int_1 (enum machine_mode mode, rtx varop,
8852 unsigned HOST_WIDE_INT constop)
8854 unsigned HOST_WIDE_INT nonzero;
8855 unsigned HOST_WIDE_INT orig_constop;
8860 orig_constop = constop;
8861 if (GET_CODE (varop) == CLOBBER)
8864 /* Simplify VAROP knowing that we will be only looking at some of the
8867 Note by passing in CONSTOP, we guarantee that the bits not set in
8868 CONSTOP are not significant and will never be examined. We must
8869 ensure that is the case by explicitly masking out those bits
8870 before returning. */
8871 varop = force_to_mode (varop, mode, constop, 0);
8873 /* If VAROP is a CLOBBER, we will fail so return it. */
8874 if (GET_CODE (varop) == CLOBBER)
8877 /* If VAROP is a CONST_INT, then we need to apply the mask in CONSTOP
8878 to VAROP and return the new constant. */
8879 if (CONST_INT_P (varop))
8880 return gen_int_mode (INTVAL (varop) & constop, mode);
8882 /* See what bits may be nonzero in VAROP. Unlike the general case of
8883 a call to nonzero_bits, here we don't care about bits outside
8886 nonzero = nonzero_bits (varop, mode) & GET_MODE_MASK (mode);
8888 /* Turn off all bits in the constant that are known to already be zero.
8889 Thus, if the AND isn't needed at all, we will have CONSTOP == NONZERO_BITS
8890 which is tested below. */
8894 /* If we don't have any bits left, return zero. */
8898 /* If VAROP is a NEG of something known to be zero or 1 and CONSTOP is
8899 a power of two, we can replace this with an ASHIFT. */
8900 if (GET_CODE (varop) == NEG && nonzero_bits (XEXP (varop, 0), mode) == 1
8901 && (i = exact_log2 (constop)) >= 0)
8902 return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (varop, 0), i);
8904 /* If VAROP is an IOR or XOR, apply the AND to both branches of the IOR
8905 or XOR, then try to apply the distributive law. This may eliminate
8906 operations if either branch can be simplified because of the AND.
8907 It may also make some cases more complex, but those cases probably
8908 won't match a pattern either with or without this. */
8910 if (GET_CODE (varop) == IOR || GET_CODE (varop) == XOR)
8914 apply_distributive_law
8915 (simplify_gen_binary (GET_CODE (varop), GET_MODE (varop),
8916 simplify_and_const_int (NULL_RTX,
8920 simplify_and_const_int (NULL_RTX,
8925 /* If VAROP is PLUS, and the constant is a mask of low bits, distribute
8926 the AND and see if one of the operands simplifies to zero. If so, we
8927 may eliminate it. */
8929 if (GET_CODE (varop) == PLUS
8930 && exact_log2 (constop + 1) >= 0)
8934 o0 = simplify_and_const_int (NULL_RTX, mode, XEXP (varop, 0), constop);
8935 o1 = simplify_and_const_int (NULL_RTX, mode, XEXP (varop, 1), constop);
8936 if (o0 == const0_rtx)
8938 if (o1 == const0_rtx)
8942 /* Make a SUBREG if necessary. If we can't make it, fail. */
8943 varop = gen_lowpart (mode, varop);
8944 if (varop == NULL_RTX || GET_CODE (varop) == CLOBBER)
8947 /* If we are only masking insignificant bits, return VAROP. */
8948 if (constop == nonzero)
8951 if (varop == orig_varop && constop == orig_constop)
8954 /* Otherwise, return an AND. */
8955 return simplify_gen_binary (AND, mode, varop, gen_int_mode (constop, mode));
8959 /* We have X, a logical `and' of VAROP with the constant CONSTOP, to be done
8962 Return an equivalent form, if different from X. Otherwise, return X. If
8963 X is zero, we are to always construct the equivalent form. */
8966 simplify_and_const_int (rtx x, enum machine_mode mode, rtx varop,
8967 unsigned HOST_WIDE_INT constop)
8969 rtx tem = simplify_and_const_int_1 (mode, varop, constop);
8974 x = simplify_gen_binary (AND, GET_MODE (varop), varop,
8975 gen_int_mode (constop, mode));
8976 if (GET_MODE (x) != mode)
8977 x = gen_lowpart (mode, x);
8981 /* Given a REG, X, compute which bits in X can be nonzero.
8982 We don't care about bits outside of those defined in MODE.
8984 For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is
8985 a shift, AND, or zero_extract, we can do better. */
8988 reg_nonzero_bits_for_combine (const_rtx x, enum machine_mode mode,
8989 const_rtx known_x ATTRIBUTE_UNUSED,
8990 enum machine_mode known_mode ATTRIBUTE_UNUSED,
8991 unsigned HOST_WIDE_INT known_ret ATTRIBUTE_UNUSED,
8992 unsigned HOST_WIDE_INT *nonzero)
8997 /* If X is a register whose nonzero bits value is current, use it.
8998 Otherwise, if X is a register whose value we can find, use that
8999 value. Otherwise, use the previously-computed global nonzero bits
9000 for this register. */
9002 rsp = VEC_index (reg_stat_type, reg_stat, REGNO (x));
9003 if (rsp->last_set_value != 0
9004 && (rsp->last_set_mode == mode
9005 || (GET_MODE_CLASS (rsp->last_set_mode) == MODE_INT
9006 && GET_MODE_CLASS (mode) == MODE_INT))
9007 && ((rsp->last_set_label >= label_tick_ebb_start
9008 && rsp->last_set_label < label_tick)
9009 || (rsp->last_set_label == label_tick
9010 && DF_INSN_LUID (rsp->last_set) < subst_low_luid)
9011 || (REGNO (x) >= FIRST_PSEUDO_REGISTER
9012 && REG_N_SETS (REGNO (x)) == 1
9014 (DF_LR_IN (ENTRY_BLOCK_PTR->next_bb), REGNO (x)))))
9016 *nonzero &= rsp->last_set_nonzero_bits;
9020 tem = get_last_value (x);
9024 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
9025 /* If X is narrower than MODE and TEM is a non-negative
9026 constant that would appear negative in the mode of X,
9027 sign-extend it for use in reg_nonzero_bits because some
9028 machines (maybe most) will actually do the sign-extension
9029 and this is the conservative approach.
9031 ??? For 2.5, try to tighten up the MD files in this regard
9032 instead of this kludge. */
9034 if (GET_MODE_BITSIZE (GET_MODE (x)) < GET_MODE_BITSIZE (mode)
9035 && CONST_INT_P (tem)
9037 && 0 != (INTVAL (tem)
9038 & ((HOST_WIDE_INT) 1
9039 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
9040 tem = GEN_INT (INTVAL (tem)
9041 | ((HOST_WIDE_INT) (-1)
9042 << GET_MODE_BITSIZE (GET_MODE (x))));
9046 else if (nonzero_sign_valid && rsp->nonzero_bits)
9048 unsigned HOST_WIDE_INT mask = rsp->nonzero_bits;
9050 if (GET_MODE_BITSIZE (GET_MODE (x)) < GET_MODE_BITSIZE (mode))
9051 /* We don't know anything about the upper bits. */
9052 mask |= GET_MODE_MASK (mode) ^ GET_MODE_MASK (GET_MODE (x));
9059 /* Return the number of bits at the high-order end of X that are known to
9060 be equal to the sign bit. X will be used in mode MODE; if MODE is
9061 VOIDmode, X will be used in its own mode. The returned value will always
9062 be between 1 and the number of bits in MODE. */
9065 reg_num_sign_bit_copies_for_combine (const_rtx x, enum machine_mode mode,
9066 const_rtx known_x ATTRIBUTE_UNUSED,
9067 enum machine_mode known_mode
9069 unsigned int known_ret ATTRIBUTE_UNUSED,
9070 unsigned int *result)
9075 rsp = VEC_index (reg_stat_type, reg_stat, REGNO (x));
9076 if (rsp->last_set_value != 0
9077 && rsp->last_set_mode == mode
9078 && ((rsp->last_set_label >= label_tick_ebb_start
9079 && rsp->last_set_label < label_tick)
9080 || (rsp->last_set_label == label_tick
9081 && DF_INSN_LUID (rsp->last_set) < subst_low_luid)
9082 || (REGNO (x) >= FIRST_PSEUDO_REGISTER
9083 && REG_N_SETS (REGNO (x)) == 1
9085 (DF_LR_IN (ENTRY_BLOCK_PTR->next_bb), REGNO (x)))))
9087 *result = rsp->last_set_sign_bit_copies;
9091 tem = get_last_value (x);
9095 if (nonzero_sign_valid && rsp->sign_bit_copies != 0
9096 && GET_MODE_BITSIZE (GET_MODE (x)) == GET_MODE_BITSIZE (mode))
9097 *result = rsp->sign_bit_copies;
9102 /* Return the number of "extended" bits there are in X, when interpreted
9103 as a quantity in MODE whose signedness is indicated by UNSIGNEDP. For
9104 unsigned quantities, this is the number of high-order zero bits.
9105 For signed quantities, this is the number of copies of the sign bit
9106 minus 1. In both case, this function returns the number of "spare"
9107 bits. For example, if two quantities for which this function returns
9108 at least 1 are added, the addition is known not to overflow.
9110 This function will always return 0 unless called during combine, which
9111 implies that it must be called from a define_split. */
9114 extended_count (const_rtx x, enum machine_mode mode, int unsignedp)
9116 if (nonzero_sign_valid == 0)
9120 ? (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
9121 ? (unsigned int) (GET_MODE_BITSIZE (mode) - 1
9122 - floor_log2 (nonzero_bits (x, mode)))
9124 : num_sign_bit_copies (x, mode) - 1);
9127 /* This function is called from `simplify_shift_const' to merge two
9128 outer operations. Specifically, we have already found that we need
9129 to perform operation *POP0 with constant *PCONST0 at the outermost
9130 position. We would now like to also perform OP1 with constant CONST1
9131 (with *POP0 being done last).
9133 Return 1 if we can do the operation and update *POP0 and *PCONST0 with
9134 the resulting operation. *PCOMP_P is set to 1 if we would need to
9135 complement the innermost operand, otherwise it is unchanged.
9137 MODE is the mode in which the operation will be done. No bits outside
9138 the width of this mode matter. It is assumed that the width of this mode
9139 is smaller than or equal to HOST_BITS_PER_WIDE_INT.
9141 If *POP0 or OP1 are UNKNOWN, it means no operation is required. Only NEG, PLUS,
9142 IOR, XOR, and AND are supported. We may set *POP0 to SET if the proper
9143 result is simply *PCONST0.
9145 If the resulting operation cannot be expressed as one operation, we
9146 return 0 and do not change *POP0, *PCONST0, and *PCOMP_P. */
9149 merge_outer_ops (enum rtx_code *pop0, HOST_WIDE_INT *pconst0, enum rtx_code op1, HOST_WIDE_INT const1, enum machine_mode mode, int *pcomp_p)
9151 enum rtx_code op0 = *pop0;
9152 HOST_WIDE_INT const0 = *pconst0;
9154 const0 &= GET_MODE_MASK (mode);
9155 const1 &= GET_MODE_MASK (mode);
9157 /* If OP0 is an AND, clear unimportant bits in CONST1. */
9161 /* If OP0 or OP1 is UNKNOWN, this is easy. Similarly if they are the same or
9164 if (op1 == UNKNOWN || op0 == SET)
9167 else if (op0 == UNKNOWN)
9168 op0 = op1, const0 = const1;
9170 else if (op0 == op1)
9194 /* Otherwise, if either is a PLUS or NEG, we can't do anything. */
9195 else if (op0 == PLUS || op1 == PLUS || op0 == NEG || op1 == NEG)
9198 /* If the two constants aren't the same, we can't do anything. The
9199 remaining six cases can all be done. */
9200 else if (const0 != const1)
9208 /* (a & b) | b == b */
9210 else /* op1 == XOR */
9211 /* (a ^ b) | b == a | b */
9217 /* (a & b) ^ b == (~a) & b */
9218 op0 = AND, *pcomp_p = 1;
9219 else /* op1 == IOR */
9220 /* (a | b) ^ b == a & ~b */
9221 op0 = AND, const0 = ~const0;
9226 /* (a | b) & b == b */
9228 else /* op1 == XOR */
9229 /* (a ^ b) & b) == (~a) & b */
9236 /* Check for NO-OP cases. */
9237 const0 &= GET_MODE_MASK (mode);
9239 && (op0 == IOR || op0 == XOR || op0 == PLUS))
9241 else if (const0 == 0 && op0 == AND)
9243 else if ((unsigned HOST_WIDE_INT) const0 == GET_MODE_MASK (mode)
9249 /* ??? Slightly redundant with the above mask, but not entirely.
9250 Moving this above means we'd have to sign-extend the mode mask
9251 for the final test. */
9252 if (op0 != UNKNOWN && op0 != NEG)
9253 *pconst0 = trunc_int_for_mode (const0, mode);
9258 /* A helper to simplify_shift_const_1 to determine the mode we can perform
9259 the shift in. The original shift operation CODE is performed on OP in
9260 ORIG_MODE. Return the wider mode MODE if we can perform the operation
9261 in that mode. Return ORIG_MODE otherwise. We can also assume that the
9262 result of the shift is subject to operation OUTER_CODE with operand
9265 static enum machine_mode
9266 try_widen_shift_mode (enum rtx_code code, rtx op, int count,
9267 enum machine_mode orig_mode, enum machine_mode mode,
9268 enum rtx_code outer_code, HOST_WIDE_INT outer_const)
9270 if (orig_mode == mode)
9272 gcc_assert (GET_MODE_BITSIZE (mode) > GET_MODE_BITSIZE (orig_mode));
9274 /* In general we can't perform in wider mode for right shift and rotate. */
9278 /* We can still widen if the bits brought in from the left are identical
9279 to the sign bit of ORIG_MODE. */
9280 if (num_sign_bit_copies (op, mode)
9281 > (unsigned) (GET_MODE_BITSIZE (mode)
9282 - GET_MODE_BITSIZE (orig_mode)))
9287 /* Similarly here but with zero bits. */
9288 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
9289 && (nonzero_bits (op, mode) & ~GET_MODE_MASK (orig_mode)) == 0)
9292 /* We can also widen if the bits brought in will be masked off. This
9293 operation is performed in ORIG_MODE. */
9294 if (outer_code == AND)
9296 int care_bits = low_bitmask_len (orig_mode, outer_const);
9299 && GET_MODE_BITSIZE (orig_mode) - care_bits >= count)
9315 /* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift.
9316 The result of the shift is RESULT_MODE. Return NULL_RTX if we cannot
9317 simplify it. Otherwise, return a simplified value.
9319 The shift is normally computed in the widest mode we find in VAROP, as
9320 long as it isn't a different number of words than RESULT_MODE. Exceptions
9321 are ASHIFTRT and ROTATE, which are always done in their original mode. */
9324 simplify_shift_const_1 (enum rtx_code code, enum machine_mode result_mode,
9325 rtx varop, int orig_count)
9327 enum rtx_code orig_code = code;
9328 rtx orig_varop = varop;
9330 enum machine_mode mode = result_mode;
9331 enum machine_mode shift_mode, tmode;
9332 unsigned int mode_words
9333 = (GET_MODE_SIZE (mode) + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD;
9334 /* We form (outer_op (code varop count) (outer_const)). */
9335 enum rtx_code outer_op = UNKNOWN;
9336 HOST_WIDE_INT outer_const = 0;
9337 int complement_p = 0;
9340 /* Make sure and truncate the "natural" shift on the way in. We don't
9341 want to do this inside the loop as it makes it more difficult to
9343 if (SHIFT_COUNT_TRUNCATED)
9344 orig_count &= GET_MODE_BITSIZE (mode) - 1;
9346 /* If we were given an invalid count, don't do anything except exactly
9347 what was requested. */
9349 if (orig_count < 0 || orig_count >= (int) GET_MODE_BITSIZE (mode))
9354 /* Unless one of the branches of the `if' in this loop does a `continue',
9355 we will `break' the loop after the `if'. */
9359 /* If we have an operand of (clobber (const_int 0)), fail. */
9360 if (GET_CODE (varop) == CLOBBER)
9363 /* Convert ROTATERT to ROTATE. */
9364 if (code == ROTATERT)
9366 unsigned int bitsize = GET_MODE_BITSIZE (result_mode);;
9368 if (VECTOR_MODE_P (result_mode))
9369 count = bitsize / GET_MODE_NUNITS (result_mode) - count;
9371 count = bitsize - count;
9374 shift_mode = try_widen_shift_mode (code, varop, count, result_mode,
9375 mode, outer_op, outer_const);
9377 /* Handle cases where the count is greater than the size of the mode
9378 minus 1. For ASHIFT, use the size minus one as the count (this can
9379 occur when simplifying (lshiftrt (ashiftrt ..))). For rotates,
9380 take the count modulo the size. For other shifts, the result is
9383 Since these shifts are being produced by the compiler by combining
9384 multiple operations, each of which are defined, we know what the
9385 result is supposed to be. */
9387 if (count > (GET_MODE_BITSIZE (shift_mode) - 1))
9389 if (code == ASHIFTRT)
9390 count = GET_MODE_BITSIZE (shift_mode) - 1;
9391 else if (code == ROTATE || code == ROTATERT)
9392 count %= GET_MODE_BITSIZE (shift_mode);
9395 /* We can't simply return zero because there may be an
9403 /* If we discovered we had to complement VAROP, leave. Making a NOT
9404 here would cause an infinite loop. */
9408 /* An arithmetic right shift of a quantity known to be -1 or 0
9410 if (code == ASHIFTRT
9411 && (num_sign_bit_copies (varop, shift_mode)
9412 == GET_MODE_BITSIZE (shift_mode)))
9418 /* If we are doing an arithmetic right shift and discarding all but
9419 the sign bit copies, this is equivalent to doing a shift by the
9420 bitsize minus one. Convert it into that shift because it will often
9421 allow other simplifications. */
9423 if (code == ASHIFTRT
9424 && (count + num_sign_bit_copies (varop, shift_mode)
9425 >= GET_MODE_BITSIZE (shift_mode)))
9426 count = GET_MODE_BITSIZE (shift_mode) - 1;
9428 /* We simplify the tests below and elsewhere by converting
9429 ASHIFTRT to LSHIFTRT if we know the sign bit is clear.
9430 `make_compound_operation' will convert it to an ASHIFTRT for
9431 those machines (such as VAX) that don't have an LSHIFTRT. */
9432 if (GET_MODE_BITSIZE (shift_mode) <= HOST_BITS_PER_WIDE_INT
9434 && ((nonzero_bits (varop, shift_mode)
9435 & ((HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (shift_mode) - 1)))
9439 if (((code == LSHIFTRT
9440 && GET_MODE_BITSIZE (shift_mode) <= HOST_BITS_PER_WIDE_INT
9441 && !(nonzero_bits (varop, shift_mode) >> count))
9443 && GET_MODE_BITSIZE (shift_mode) <= HOST_BITS_PER_WIDE_INT
9444 && !((nonzero_bits (varop, shift_mode) << count)
9445 & GET_MODE_MASK (shift_mode))))
9446 && !side_effects_p (varop))
9449 switch (GET_CODE (varop))
9455 new_rtx = expand_compound_operation (varop);
9456 if (new_rtx != varop)
9464 /* If we have (xshiftrt (mem ...) C) and C is MODE_WIDTH
9465 minus the width of a smaller mode, we can do this with a
9466 SIGN_EXTEND or ZERO_EXTEND from the narrower memory location. */
9467 if ((code == ASHIFTRT || code == LSHIFTRT)
9468 && ! mode_dependent_address_p (XEXP (varop, 0))
9469 && ! MEM_VOLATILE_P (varop)
9470 && (tmode = mode_for_size (GET_MODE_BITSIZE (mode) - count,
9471 MODE_INT, 1)) != BLKmode)
9473 new_rtx = adjust_address_nv (varop, tmode,
9474 BYTES_BIG_ENDIAN ? 0
9475 : count / BITS_PER_UNIT);
9477 varop = gen_rtx_fmt_e (code == ASHIFTRT ? SIGN_EXTEND
9478 : ZERO_EXTEND, mode, new_rtx);
9485 /* If VAROP is a SUBREG, strip it as long as the inner operand has
9486 the same number of words as what we've seen so far. Then store
9487 the widest mode in MODE. */
9488 if (subreg_lowpart_p (varop)
9489 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop)))
9490 > GET_MODE_SIZE (GET_MODE (varop)))
9491 && (unsigned int) ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop)))
9492 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
9495 varop = SUBREG_REG (varop);
9496 if (GET_MODE_SIZE (GET_MODE (varop)) > GET_MODE_SIZE (mode))
9497 mode = GET_MODE (varop);
9503 /* Some machines use MULT instead of ASHIFT because MULT
9504 is cheaper. But it is still better on those machines to
9505 merge two shifts into one. */
9506 if (CONST_INT_P (XEXP (varop, 1))
9507 && exact_log2 (INTVAL (XEXP (varop, 1))) >= 0)
9510 = simplify_gen_binary (ASHIFT, GET_MODE (varop),
9512 GEN_INT (exact_log2 (
9513 INTVAL (XEXP (varop, 1)))));
9519 /* Similar, for when divides are cheaper. */
9520 if (CONST_INT_P (XEXP (varop, 1))
9521 && exact_log2 (INTVAL (XEXP (varop, 1))) >= 0)
9524 = simplify_gen_binary (LSHIFTRT, GET_MODE (varop),
9526 GEN_INT (exact_log2 (
9527 INTVAL (XEXP (varop, 1)))));
9533 /* If we are extracting just the sign bit of an arithmetic
9534 right shift, that shift is not needed. However, the sign
9535 bit of a wider mode may be different from what would be
9536 interpreted as the sign bit in a narrower mode, so, if
9537 the result is narrower, don't discard the shift. */
9538 if (code == LSHIFTRT
9539 && count == (GET_MODE_BITSIZE (result_mode) - 1)
9540 && (GET_MODE_BITSIZE (result_mode)
9541 >= GET_MODE_BITSIZE (GET_MODE (varop))))
9543 varop = XEXP (varop, 0);
9547 /* ... fall through ... */
9552 /* Here we have two nested shifts. The result is usually the
9553 AND of a new shift with a mask. We compute the result below. */
9554 if (CONST_INT_P (XEXP (varop, 1))
9555 && INTVAL (XEXP (varop, 1)) >= 0
9556 && INTVAL (XEXP (varop, 1)) < GET_MODE_BITSIZE (GET_MODE (varop))
9557 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
9558 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
9559 && !VECTOR_MODE_P (result_mode))
9561 enum rtx_code first_code = GET_CODE (varop);
9562 unsigned int first_count = INTVAL (XEXP (varop, 1));
9563 unsigned HOST_WIDE_INT mask;
9566 /* We have one common special case. We can't do any merging if
9567 the inner code is an ASHIFTRT of a smaller mode. However, if
9568 we have (ashift:M1 (subreg:M1 (ashiftrt:M2 FOO C1) 0) C2)
9569 with C2 == GET_MODE_BITSIZE (M1) - GET_MODE_BITSIZE (M2),
9570 we can convert it to
9571 (ashiftrt:M1 (ashift:M1 (and:M1 (subreg:M1 FOO 0 C2) C3) C1).
9572 This simplifies certain SIGN_EXTEND operations. */
9573 if (code == ASHIFT && first_code == ASHIFTRT
9574 && count == (GET_MODE_BITSIZE (result_mode)
9575 - GET_MODE_BITSIZE (GET_MODE (varop))))
9577 /* C3 has the low-order C1 bits zero. */
9579 mask = (GET_MODE_MASK (mode)
9580 & ~(((HOST_WIDE_INT) 1 << first_count) - 1));
9582 varop = simplify_and_const_int (NULL_RTX, result_mode,
9583 XEXP (varop, 0), mask);
9584 varop = simplify_shift_const (NULL_RTX, ASHIFT, result_mode,
9586 count = first_count;
9591 /* If this was (ashiftrt (ashift foo C1) C2) and FOO has more
9592 than C1 high-order bits equal to the sign bit, we can convert
9593 this to either an ASHIFT or an ASHIFTRT depending on the
9596 We cannot do this if VAROP's mode is not SHIFT_MODE. */
9598 if (code == ASHIFTRT && first_code == ASHIFT
9599 && GET_MODE (varop) == shift_mode
9600 && (num_sign_bit_copies (XEXP (varop, 0), shift_mode)
9603 varop = XEXP (varop, 0);
9604 count -= first_count;
9614 /* There are some cases we can't do. If CODE is ASHIFTRT,
9615 we can only do this if FIRST_CODE is also ASHIFTRT.
9617 We can't do the case when CODE is ROTATE and FIRST_CODE is
9620 If the mode of this shift is not the mode of the outer shift,
9621 we can't do this if either shift is a right shift or ROTATE.
9623 Finally, we can't do any of these if the mode is too wide
9624 unless the codes are the same.
9626 Handle the case where the shift codes are the same
9629 if (code == first_code)
9631 if (GET_MODE (varop) != result_mode
9632 && (code == ASHIFTRT || code == LSHIFTRT
9636 count += first_count;
9637 varop = XEXP (varop, 0);
9641 if (code == ASHIFTRT
9642 || (code == ROTATE && first_code == ASHIFTRT)
9643 || GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT
9644 || (GET_MODE (varop) != result_mode
9645 && (first_code == ASHIFTRT || first_code == LSHIFTRT
9646 || first_code == ROTATE
9647 || code == ROTATE)))
9650 /* To compute the mask to apply after the shift, shift the
9651 nonzero bits of the inner shift the same way the
9652 outer shift will. */
9654 mask_rtx = GEN_INT (nonzero_bits (varop, GET_MODE (varop)));
9657 = simplify_const_binary_operation (code, result_mode, mask_rtx,
9660 /* Give up if we can't compute an outer operation to use. */
9662 || !CONST_INT_P (mask_rtx)
9663 || ! merge_outer_ops (&outer_op, &outer_const, AND,
9665 result_mode, &complement_p))
9668 /* If the shifts are in the same direction, we add the
9669 counts. Otherwise, we subtract them. */
9670 if ((code == ASHIFTRT || code == LSHIFTRT)
9671 == (first_code == ASHIFTRT || first_code == LSHIFTRT))
9672 count += first_count;
9674 count -= first_count;
9676 /* If COUNT is positive, the new shift is usually CODE,
9677 except for the two exceptions below, in which case it is
9678 FIRST_CODE. If the count is negative, FIRST_CODE should
9681 && ((first_code == ROTATE && code == ASHIFT)
9682 || (first_code == ASHIFTRT && code == LSHIFTRT)))
9685 code = first_code, count = -count;
9687 varop = XEXP (varop, 0);
9691 /* If we have (A << B << C) for any shift, we can convert this to
9692 (A << C << B). This wins if A is a constant. Only try this if
9693 B is not a constant. */
9695 else if (GET_CODE (varop) == code
9696 && CONST_INT_P (XEXP (varop, 0))
9697 && !CONST_INT_P (XEXP (varop, 1)))
9699 rtx new_rtx = simplify_const_binary_operation (code, mode,
9702 varop = gen_rtx_fmt_ee (code, mode, new_rtx, XEXP (varop, 1));
9709 if (VECTOR_MODE_P (mode))
9712 /* Make this fit the case below. */
9713 varop = gen_rtx_XOR (mode, XEXP (varop, 0),
9714 GEN_INT (GET_MODE_MASK (mode)));
9720 /* If we have (xshiftrt (ior (plus X (const_int -1)) X) C)
9721 with C the size of VAROP - 1 and the shift is logical if
9722 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
9723 we have an (le X 0) operation. If we have an arithmetic shift
9724 and STORE_FLAG_VALUE is 1 or we have a logical shift with
9725 STORE_FLAG_VALUE of -1, we have a (neg (le X 0)) operation. */
9727 if (GET_CODE (varop) == IOR && GET_CODE (XEXP (varop, 0)) == PLUS
9728 && XEXP (XEXP (varop, 0), 1) == constm1_rtx
9729 && (STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
9730 && (code == LSHIFTRT || code == ASHIFTRT)
9731 && count == (GET_MODE_BITSIZE (GET_MODE (varop)) - 1)
9732 && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
9735 varop = gen_rtx_LE (GET_MODE (varop), XEXP (varop, 1),
9738 if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
9739 varop = gen_rtx_NEG (GET_MODE (varop), varop);
9744 /* If we have (shift (logical)), move the logical to the outside
9745 to allow it to possibly combine with another logical and the
9746 shift to combine with another shift. This also canonicalizes to
9747 what a ZERO_EXTRACT looks like. Also, some machines have
9748 (and (shift)) insns. */
9750 if (CONST_INT_P (XEXP (varop, 1))
9751 /* We can't do this if we have (ashiftrt (xor)) and the
9752 constant has its sign bit set in shift_mode. */
9753 && !(code == ASHIFTRT && GET_CODE (varop) == XOR
9754 && 0 > trunc_int_for_mode (INTVAL (XEXP (varop, 1)),
9756 && (new_rtx = simplify_const_binary_operation (code, result_mode,
9758 GEN_INT (count))) != 0
9759 && CONST_INT_P (new_rtx)
9760 && merge_outer_ops (&outer_op, &outer_const, GET_CODE (varop),
9761 INTVAL (new_rtx), result_mode, &complement_p))
9763 varop = XEXP (varop, 0);
9767 /* If we can't do that, try to simplify the shift in each arm of the
9768 logical expression, make a new logical expression, and apply
9769 the inverse distributive law. This also can't be done
9770 for some (ashiftrt (xor)). */
9771 if (CONST_INT_P (XEXP (varop, 1))
9772 && !(code == ASHIFTRT && GET_CODE (varop) == XOR
9773 && 0 > trunc_int_for_mode (INTVAL (XEXP (varop, 1)),
9776 rtx lhs = simplify_shift_const (NULL_RTX, code, shift_mode,
9777 XEXP (varop, 0), count);
9778 rtx rhs = simplify_shift_const (NULL_RTX, code, shift_mode,
9779 XEXP (varop, 1), count);
9781 varop = simplify_gen_binary (GET_CODE (varop), shift_mode,
9783 varop = apply_distributive_law (varop);
9791 /* Convert (lshiftrt (eq FOO 0) C) to (xor FOO 1) if STORE_FLAG_VALUE
9792 says that the sign bit can be tested, FOO has mode MODE, C is
9793 GET_MODE_BITSIZE (MODE) - 1, and FOO has only its low-order bit
9794 that may be nonzero. */
9795 if (code == LSHIFTRT
9796 && XEXP (varop, 1) == const0_rtx
9797 && GET_MODE (XEXP (varop, 0)) == result_mode
9798 && count == (GET_MODE_BITSIZE (result_mode) - 1)
9799 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
9800 && STORE_FLAG_VALUE == -1
9801 && nonzero_bits (XEXP (varop, 0), result_mode) == 1
9802 && merge_outer_ops (&outer_op, &outer_const, XOR,
9803 (HOST_WIDE_INT) 1, result_mode,
9806 varop = XEXP (varop, 0);
9813 /* (lshiftrt (neg A) C) where A is either 0 or 1 and C is one less
9814 than the number of bits in the mode is equivalent to A. */
9815 if (code == LSHIFTRT
9816 && count == (GET_MODE_BITSIZE (result_mode) - 1)
9817 && nonzero_bits (XEXP (varop, 0), result_mode) == 1)
9819 varop = XEXP (varop, 0);
9824 /* NEG commutes with ASHIFT since it is multiplication. Move the
9825 NEG outside to allow shifts to combine. */
9827 && merge_outer_ops (&outer_op, &outer_const, NEG,
9828 (HOST_WIDE_INT) 0, result_mode,
9831 varop = XEXP (varop, 0);
9837 /* (lshiftrt (plus A -1) C) where A is either 0 or 1 and C
9838 is one less than the number of bits in the mode is
9839 equivalent to (xor A 1). */
9840 if (code == LSHIFTRT
9841 && count == (GET_MODE_BITSIZE (result_mode) - 1)
9842 && XEXP (varop, 1) == constm1_rtx
9843 && nonzero_bits (XEXP (varop, 0), result_mode) == 1
9844 && merge_outer_ops (&outer_op, &outer_const, XOR,
9845 (HOST_WIDE_INT) 1, result_mode,
9849 varop = XEXP (varop, 0);
9853 /* If we have (xshiftrt (plus FOO BAR) C), and the only bits
9854 that might be nonzero in BAR are those being shifted out and those
9855 bits are known zero in FOO, we can replace the PLUS with FOO.
9856 Similarly in the other operand order. This code occurs when
9857 we are computing the size of a variable-size array. */
9859 if ((code == ASHIFTRT || code == LSHIFTRT)
9860 && count < HOST_BITS_PER_WIDE_INT
9861 && nonzero_bits (XEXP (varop, 1), result_mode) >> count == 0
9862 && (nonzero_bits (XEXP (varop, 1), result_mode)
9863 & nonzero_bits (XEXP (varop, 0), result_mode)) == 0)
9865 varop = XEXP (varop, 0);
9868 else if ((code == ASHIFTRT || code == LSHIFTRT)
9869 && count < HOST_BITS_PER_WIDE_INT
9870 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
9871 && 0 == (nonzero_bits (XEXP (varop, 0), result_mode)
9873 && 0 == (nonzero_bits (XEXP (varop, 0), result_mode)
9874 & nonzero_bits (XEXP (varop, 1),
9877 varop = XEXP (varop, 1);
9881 /* (ashift (plus foo C) N) is (plus (ashift foo N) C'). */
9883 && CONST_INT_P (XEXP (varop, 1))
9884 && (new_rtx = simplify_const_binary_operation (ASHIFT, result_mode,
9886 GEN_INT (count))) != 0
9887 && CONST_INT_P (new_rtx)
9888 && merge_outer_ops (&outer_op, &outer_const, PLUS,
9889 INTVAL (new_rtx), result_mode, &complement_p))
9891 varop = XEXP (varop, 0);
9895 /* Check for 'PLUS signbit', which is the canonical form of 'XOR
9896 signbit', and attempt to change the PLUS to an XOR and move it to
9897 the outer operation as is done above in the AND/IOR/XOR case
9898 leg for shift(logical). See details in logical handling above
9899 for reasoning in doing so. */
9900 if (code == LSHIFTRT
9901 && CONST_INT_P (XEXP (varop, 1))
9902 && mode_signbit_p (result_mode, XEXP (varop, 1))
9903 && (new_rtx = simplify_const_binary_operation (code, result_mode,
9905 GEN_INT (count))) != 0
9906 && CONST_INT_P (new_rtx)
9907 && merge_outer_ops (&outer_op, &outer_const, XOR,
9908 INTVAL (new_rtx), result_mode, &complement_p))
9910 varop = XEXP (varop, 0);
9917 /* If we have (xshiftrt (minus (ashiftrt X C)) X) C)
9918 with C the size of VAROP - 1 and the shift is logical if
9919 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
9920 we have a (gt X 0) operation. If the shift is arithmetic with
9921 STORE_FLAG_VALUE of 1 or logical with STORE_FLAG_VALUE == -1,
9922 we have a (neg (gt X 0)) operation. */
9924 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
9925 && GET_CODE (XEXP (varop, 0)) == ASHIFTRT
9926 && count == (GET_MODE_BITSIZE (GET_MODE (varop)) - 1)
9927 && (code == LSHIFTRT || code == ASHIFTRT)
9928 && CONST_INT_P (XEXP (XEXP (varop, 0), 1))
9929 && INTVAL (XEXP (XEXP (varop, 0), 1)) == count
9930 && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
9933 varop = gen_rtx_GT (GET_MODE (varop), XEXP (varop, 1),
9936 if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
9937 varop = gen_rtx_NEG (GET_MODE (varop), varop);
9944 /* Change (lshiftrt (truncate (lshiftrt))) to (truncate (lshiftrt))
9945 if the truncate does not affect the value. */
9946 if (code == LSHIFTRT
9947 && GET_CODE (XEXP (varop, 0)) == LSHIFTRT
9948 && CONST_INT_P (XEXP (XEXP (varop, 0), 1))
9949 && (INTVAL (XEXP (XEXP (varop, 0), 1))
9950 >= (GET_MODE_BITSIZE (GET_MODE (XEXP (varop, 0)))
9951 - GET_MODE_BITSIZE (GET_MODE (varop)))))
9953 rtx varop_inner = XEXP (varop, 0);
9956 = gen_rtx_LSHIFTRT (GET_MODE (varop_inner),
9957 XEXP (varop_inner, 0),
9959 (count + INTVAL (XEXP (varop_inner, 1))));
9960 varop = gen_rtx_TRUNCATE (GET_MODE (varop), varop_inner);
9973 shift_mode = try_widen_shift_mode (code, varop, count, result_mode, mode,
9974 outer_op, outer_const);
9976 /* We have now finished analyzing the shift. The result should be
9977 a shift of type CODE with SHIFT_MODE shifting VAROP COUNT places. If
9978 OUTER_OP is non-UNKNOWN, it is an operation that needs to be applied
9979 to the result of the shift. OUTER_CONST is the relevant constant,
9980 but we must turn off all bits turned off in the shift. */
9982 if (outer_op == UNKNOWN
9983 && orig_code == code && orig_count == count
9984 && varop == orig_varop
9985 && shift_mode == GET_MODE (varop))
9988 /* Make a SUBREG if necessary. If we can't make it, fail. */
9989 varop = gen_lowpart (shift_mode, varop);
9990 if (varop == NULL_RTX || GET_CODE (varop) == CLOBBER)
9993 /* If we have an outer operation and we just made a shift, it is
9994 possible that we could have simplified the shift were it not
9995 for the outer operation. So try to do the simplification
9998 if (outer_op != UNKNOWN)
9999 x = simplify_shift_const_1 (code, shift_mode, varop, count);
10004 x = simplify_gen_binary (code, shift_mode, varop, GEN_INT (count));
10006 /* If we were doing an LSHIFTRT in a wider mode than it was originally,
10007 turn off all the bits that the shift would have turned off. */
10008 if (orig_code == LSHIFTRT && result_mode != shift_mode)
10009 x = simplify_and_const_int (NULL_RTX, shift_mode, x,
10010 GET_MODE_MASK (result_mode) >> orig_count);
10012 /* Do the remainder of the processing in RESULT_MODE. */
10013 x = gen_lowpart_or_truncate (result_mode, x);
10015 /* If COMPLEMENT_P is set, we have to complement X before doing the outer
10018 x = simplify_gen_unary (NOT, result_mode, x, result_mode);
10020 if (outer_op != UNKNOWN)
10022 if (GET_RTX_CLASS (outer_op) != RTX_UNARY
10023 && GET_MODE_BITSIZE (result_mode) < HOST_BITS_PER_WIDE_INT)
10024 outer_const = trunc_int_for_mode (outer_const, result_mode);
10026 if (outer_op == AND)
10027 x = simplify_and_const_int (NULL_RTX, result_mode, x, outer_const);
10028 else if (outer_op == SET)
10030 /* This means that we have determined that the result is
10031 equivalent to a constant. This should be rare. */
10032 if (!side_effects_p (x))
10033 x = GEN_INT (outer_const);
10035 else if (GET_RTX_CLASS (outer_op) == RTX_UNARY)
10036 x = simplify_gen_unary (outer_op, result_mode, x, result_mode);
10038 x = simplify_gen_binary (outer_op, result_mode, x,
10039 GEN_INT (outer_const));
10045 /* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift.
10046 The result of the shift is RESULT_MODE. If we cannot simplify it,
10047 return X or, if it is NULL, synthesize the expression with
10048 simplify_gen_binary. Otherwise, return a simplified value.
10050 The shift is normally computed in the widest mode we find in VAROP, as
10051 long as it isn't a different number of words than RESULT_MODE. Exceptions
10052 are ASHIFTRT and ROTATE, which are always done in their original mode. */
10055 simplify_shift_const (rtx x, enum rtx_code code, enum machine_mode result_mode,
10056 rtx varop, int count)
10058 rtx tem = simplify_shift_const_1 (code, result_mode, varop, count);
10063 x = simplify_gen_binary (code, GET_MODE (varop), varop, GEN_INT (count));
10064 if (GET_MODE (x) != result_mode)
10065 x = gen_lowpart (result_mode, x);
10070 /* Like recog, but we receive the address of a pointer to a new pattern.
10071 We try to match the rtx that the pointer points to.
10072 If that fails, we may try to modify or replace the pattern,
10073 storing the replacement into the same pointer object.
10075 Modifications include deletion or addition of CLOBBERs.
10077 PNOTES is a pointer to a location where any REG_UNUSED notes added for
10078 the CLOBBERs are placed.
10080 The value is the final insn code from the pattern ultimately matched,
10084 recog_for_combine (rtx *pnewpat, rtx insn, rtx *pnotes)
10086 rtx pat = *pnewpat;
10087 int insn_code_number;
10088 int num_clobbers_to_add = 0;
10091 rtx old_notes, old_pat;
10093 /* If PAT is a PARALLEL, check to see if it contains the CLOBBER
10094 we use to indicate that something didn't match. If we find such a
10095 thing, force rejection. */
10096 if (GET_CODE (pat) == PARALLEL)
10097 for (i = XVECLEN (pat, 0) - 1; i >= 0; i--)
10098 if (GET_CODE (XVECEXP (pat, 0, i)) == CLOBBER
10099 && XEXP (XVECEXP (pat, 0, i), 0) == const0_rtx)
10102 old_pat = PATTERN (insn);
10103 old_notes = REG_NOTES (insn);
10104 PATTERN (insn) = pat;
10105 REG_NOTES (insn) = 0;
10107 insn_code_number = recog (pat, insn, &num_clobbers_to_add);
10108 if (dump_file && (dump_flags & TDF_DETAILS))
10110 if (insn_code_number < 0)
10111 fputs ("Failed to match this instruction:\n", dump_file);
10113 fputs ("Successfully matched this instruction:\n", dump_file);
10114 print_rtl_single (dump_file, pat);
10117 /* If it isn't, there is the possibility that we previously had an insn
10118 that clobbered some register as a side effect, but the combined
10119 insn doesn't need to do that. So try once more without the clobbers
10120 unless this represents an ASM insn. */
10122 if (insn_code_number < 0 && ! check_asm_operands (pat)
10123 && GET_CODE (pat) == PARALLEL)
10127 for (pos = 0, i = 0; i < XVECLEN (pat, 0); i++)
10128 if (GET_CODE (XVECEXP (pat, 0, i)) != CLOBBER)
10131 SUBST (XVECEXP (pat, 0, pos), XVECEXP (pat, 0, i));
10135 SUBST_INT (XVECLEN (pat, 0), pos);
10138 pat = XVECEXP (pat, 0, 0);
10140 PATTERN (insn) = pat;
10141 insn_code_number = recog (pat, insn, &num_clobbers_to_add);
10142 if (dump_file && (dump_flags & TDF_DETAILS))
10144 if (insn_code_number < 0)
10145 fputs ("Failed to match this instruction:\n", dump_file);
10147 fputs ("Successfully matched this instruction:\n", dump_file);
10148 print_rtl_single (dump_file, pat);
10151 PATTERN (insn) = old_pat;
10152 REG_NOTES (insn) = old_notes;
10154 /* Recognize all noop sets, these will be killed by followup pass. */
10155 if (insn_code_number < 0 && GET_CODE (pat) == SET && set_noop_p (pat))
10156 insn_code_number = NOOP_MOVE_INSN_CODE, num_clobbers_to_add = 0;
10158 /* If we had any clobbers to add, make a new pattern than contains
10159 them. Then check to make sure that all of them are dead. */
10160 if (num_clobbers_to_add)
10162 rtx newpat = gen_rtx_PARALLEL (VOIDmode,
10163 rtvec_alloc (GET_CODE (pat) == PARALLEL
10164 ? (XVECLEN (pat, 0)
10165 + num_clobbers_to_add)
10166 : num_clobbers_to_add + 1));
10168 if (GET_CODE (pat) == PARALLEL)
10169 for (i = 0; i < XVECLEN (pat, 0); i++)
10170 XVECEXP (newpat, 0, i) = XVECEXP (pat, 0, i);
10172 XVECEXP (newpat, 0, 0) = pat;
10174 add_clobbers (newpat, insn_code_number);
10176 for (i = XVECLEN (newpat, 0) - num_clobbers_to_add;
10177 i < XVECLEN (newpat, 0); i++)
10179 if (REG_P (XEXP (XVECEXP (newpat, 0, i), 0))
10180 && ! reg_dead_at_p (XEXP (XVECEXP (newpat, 0, i), 0), insn))
10182 if (GET_CODE (XEXP (XVECEXP (newpat, 0, i), 0)) != SCRATCH)
10184 gcc_assert (REG_P (XEXP (XVECEXP (newpat, 0, i), 0)));
10185 notes = alloc_reg_note (REG_UNUSED,
10186 XEXP (XVECEXP (newpat, 0, i), 0), notes);
10195 return insn_code_number;
10198 /* Like gen_lowpart_general but for use by combine. In combine it
10199 is not possible to create any new pseudoregs. However, it is
10200 safe to create invalid memory addresses, because combine will
10201 try to recognize them and all they will do is make the combine
10204 If for some reason this cannot do its job, an rtx
10205 (clobber (const_int 0)) is returned.
10206 An insn containing that will not be recognized. */
10209 gen_lowpart_for_combine (enum machine_mode omode, rtx x)
10211 enum machine_mode imode = GET_MODE (x);
10212 unsigned int osize = GET_MODE_SIZE (omode);
10213 unsigned int isize = GET_MODE_SIZE (imode);
10216 if (omode == imode)
10219 /* Return identity if this is a CONST or symbolic reference. */
10221 && (GET_CODE (x) == CONST
10222 || GET_CODE (x) == SYMBOL_REF
10223 || GET_CODE (x) == LABEL_REF))
10226 /* We can only support MODE being wider than a word if X is a
10227 constant integer or has a mode the same size. */
10228 if (GET_MODE_SIZE (omode) > UNITS_PER_WORD
10229 && ! ((imode == VOIDmode
10230 && (CONST_INT_P (x)
10231 || GET_CODE (x) == CONST_DOUBLE))
10232 || isize == osize))
10235 /* X might be a paradoxical (subreg (mem)). In that case, gen_lowpart
10236 won't know what to do. So we will strip off the SUBREG here and
10237 process normally. */
10238 if (GET_CODE (x) == SUBREG && MEM_P (SUBREG_REG (x)))
10240 x = SUBREG_REG (x);
10242 /* For use in case we fall down into the address adjustments
10243 further below, we need to adjust the known mode and size of
10244 x; imode and isize, since we just adjusted x. */
10245 imode = GET_MODE (x);
10247 if (imode == omode)
10250 isize = GET_MODE_SIZE (imode);
10253 result = gen_lowpart_common (omode, x);
10262 /* Refuse to work on a volatile memory ref or one with a mode-dependent
10264 if (MEM_VOLATILE_P (x) || mode_dependent_address_p (XEXP (x, 0)))
10267 /* If we want to refer to something bigger than the original memref,
10268 generate a paradoxical subreg instead. That will force a reload
10269 of the original memref X. */
10271 return gen_rtx_SUBREG (omode, x, 0);
10273 if (WORDS_BIG_ENDIAN)
10274 offset = MAX (isize, UNITS_PER_WORD) - MAX (osize, UNITS_PER_WORD);
10276 /* Adjust the address so that the address-after-the-data is
10278 if (BYTES_BIG_ENDIAN)
10279 offset -= MIN (UNITS_PER_WORD, osize) - MIN (UNITS_PER_WORD, isize);
10281 return adjust_address_nv (x, omode, offset);
10284 /* If X is a comparison operator, rewrite it in a new mode. This
10285 probably won't match, but may allow further simplifications. */
10286 else if (COMPARISON_P (x))
10287 return gen_rtx_fmt_ee (GET_CODE (x), omode, XEXP (x, 0), XEXP (x, 1));
10289 /* If we couldn't simplify X any other way, just enclose it in a
10290 SUBREG. Normally, this SUBREG won't match, but some patterns may
10291 include an explicit SUBREG or we may simplify it further in combine. */
10297 offset = subreg_lowpart_offset (omode, imode);
10298 if (imode == VOIDmode)
10300 imode = int_mode_for_mode (omode);
10301 x = gen_lowpart_common (imode, x);
10305 res = simplify_gen_subreg (omode, x, imode, offset);
10311 return gen_rtx_CLOBBER (omode, const0_rtx);
10314 /* Simplify a comparison between *POP0 and *POP1 where CODE is the
10315 comparison code that will be tested.
10317 The result is a possibly different comparison code to use. *POP0 and
10318 *POP1 may be updated.
10320 It is possible that we might detect that a comparison is either always
10321 true or always false. However, we do not perform general constant
10322 folding in combine, so this knowledge isn't useful. Such tautologies
10323 should have been detected earlier. Hence we ignore all such cases. */
10325 static enum rtx_code
10326 simplify_comparison (enum rtx_code code, rtx *pop0, rtx *pop1)
10332 enum machine_mode mode, tmode;
10334 /* Try a few ways of applying the same transformation to both operands. */
10337 #ifndef WORD_REGISTER_OPERATIONS
10338 /* The test below this one won't handle SIGN_EXTENDs on these machines,
10339 so check specially. */
10340 if (code != GTU && code != GEU && code != LTU && code != LEU
10341 && GET_CODE (op0) == ASHIFTRT && GET_CODE (op1) == ASHIFTRT
10342 && GET_CODE (XEXP (op0, 0)) == ASHIFT
10343 && GET_CODE (XEXP (op1, 0)) == ASHIFT
10344 && GET_CODE (XEXP (XEXP (op0, 0), 0)) == SUBREG
10345 && GET_CODE (XEXP (XEXP (op1, 0), 0)) == SUBREG
10346 && (GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0)))
10347 == GET_MODE (SUBREG_REG (XEXP (XEXP (op1, 0), 0))))
10348 && CONST_INT_P (XEXP (op0, 1))
10349 && XEXP (op0, 1) == XEXP (op1, 1)
10350 && XEXP (op0, 1) == XEXP (XEXP (op0, 0), 1)
10351 && XEXP (op0, 1) == XEXP (XEXP (op1, 0), 1)
10352 && (INTVAL (XEXP (op0, 1))
10353 == (GET_MODE_BITSIZE (GET_MODE (op0))
10354 - (GET_MODE_BITSIZE
10355 (GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0))))))))
10357 op0 = SUBREG_REG (XEXP (XEXP (op0, 0), 0));
10358 op1 = SUBREG_REG (XEXP (XEXP (op1, 0), 0));
10362 /* If both operands are the same constant shift, see if we can ignore the
10363 shift. We can if the shift is a rotate or if the bits shifted out of
10364 this shift are known to be zero for both inputs and if the type of
10365 comparison is compatible with the shift. */
10366 if (GET_CODE (op0) == GET_CODE (op1)
10367 && GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
10368 && ((GET_CODE (op0) == ROTATE && (code == NE || code == EQ))
10369 || ((GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFT)
10370 && (code != GT && code != LT && code != GE && code != LE))
10371 || (GET_CODE (op0) == ASHIFTRT
10372 && (code != GTU && code != LTU
10373 && code != GEU && code != LEU)))
10374 && CONST_INT_P (XEXP (op0, 1))
10375 && INTVAL (XEXP (op0, 1)) >= 0
10376 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT
10377 && XEXP (op0, 1) == XEXP (op1, 1))
10379 enum machine_mode mode = GET_MODE (op0);
10380 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
10381 int shift_count = INTVAL (XEXP (op0, 1));
10383 if (GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFTRT)
10384 mask &= (mask >> shift_count) << shift_count;
10385 else if (GET_CODE (op0) == ASHIFT)
10386 mask = (mask & (mask << shift_count)) >> shift_count;
10388 if ((nonzero_bits (XEXP (op0, 0), mode) & ~mask) == 0
10389 && (nonzero_bits (XEXP (op1, 0), mode) & ~mask) == 0)
10390 op0 = XEXP (op0, 0), op1 = XEXP (op1, 0);
10395 /* If both operands are AND's of a paradoxical SUBREG by constant, the
10396 SUBREGs are of the same mode, and, in both cases, the AND would
10397 be redundant if the comparison was done in the narrower mode,
10398 do the comparison in the narrower mode (e.g., we are AND'ing with 1
10399 and the operand's possibly nonzero bits are 0xffffff01; in that case
10400 if we only care about QImode, we don't need the AND). This case
10401 occurs if the output mode of an scc insn is not SImode and
10402 STORE_FLAG_VALUE == 1 (e.g., the 386).
10404 Similarly, check for a case where the AND's are ZERO_EXTEND
10405 operations from some narrower mode even though a SUBREG is not
10408 else if (GET_CODE (op0) == AND && GET_CODE (op1) == AND
10409 && CONST_INT_P (XEXP (op0, 1))
10410 && CONST_INT_P (XEXP (op1, 1)))
10412 rtx inner_op0 = XEXP (op0, 0);
10413 rtx inner_op1 = XEXP (op1, 0);
10414 HOST_WIDE_INT c0 = INTVAL (XEXP (op0, 1));
10415 HOST_WIDE_INT c1 = INTVAL (XEXP (op1, 1));
10418 if (GET_CODE (inner_op0) == SUBREG && GET_CODE (inner_op1) == SUBREG
10419 && (GET_MODE_SIZE (GET_MODE (inner_op0))
10420 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (inner_op0))))
10421 && (GET_MODE (SUBREG_REG (inner_op0))
10422 == GET_MODE (SUBREG_REG (inner_op1)))
10423 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (inner_op0)))
10424 <= HOST_BITS_PER_WIDE_INT)
10425 && (0 == ((~c0) & nonzero_bits (SUBREG_REG (inner_op0),
10426 GET_MODE (SUBREG_REG (inner_op0)))))
10427 && (0 == ((~c1) & nonzero_bits (SUBREG_REG (inner_op1),
10428 GET_MODE (SUBREG_REG (inner_op1))))))
10430 op0 = SUBREG_REG (inner_op0);
10431 op1 = SUBREG_REG (inner_op1);
10433 /* The resulting comparison is always unsigned since we masked
10434 off the original sign bit. */
10435 code = unsigned_condition (code);
10441 for (tmode = GET_CLASS_NARROWEST_MODE
10442 (GET_MODE_CLASS (GET_MODE (op0)));
10443 tmode != GET_MODE (op0); tmode = GET_MODE_WIDER_MODE (tmode))
10444 if ((unsigned HOST_WIDE_INT) c0 == GET_MODE_MASK (tmode))
10446 op0 = gen_lowpart (tmode, inner_op0);
10447 op1 = gen_lowpart (tmode, inner_op1);
10448 code = unsigned_condition (code);
10457 /* If both operands are NOT, we can strip off the outer operation
10458 and adjust the comparison code for swapped operands; similarly for
10459 NEG, except that this must be an equality comparison. */
10460 else if ((GET_CODE (op0) == NOT && GET_CODE (op1) == NOT)
10461 || (GET_CODE (op0) == NEG && GET_CODE (op1) == NEG
10462 && (code == EQ || code == NE)))
10463 op0 = XEXP (op0, 0), op1 = XEXP (op1, 0), code = swap_condition (code);
10469 /* If the first operand is a constant, swap the operands and adjust the
10470 comparison code appropriately, but don't do this if the second operand
10471 is already a constant integer. */
10472 if (swap_commutative_operands_p (op0, op1))
10474 tem = op0, op0 = op1, op1 = tem;
10475 code = swap_condition (code);
10478 /* We now enter a loop during which we will try to simplify the comparison.
10479 For the most part, we only are concerned with comparisons with zero,
10480 but some things may really be comparisons with zero but not start
10481 out looking that way. */
10483 while (CONST_INT_P (op1))
10485 enum machine_mode mode = GET_MODE (op0);
10486 unsigned int mode_width = GET_MODE_BITSIZE (mode);
10487 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
10488 int equality_comparison_p;
10489 int sign_bit_comparison_p;
10490 int unsigned_comparison_p;
10491 HOST_WIDE_INT const_op;
10493 /* We only want to handle integral modes. This catches VOIDmode,
10494 CCmode, and the floating-point modes. An exception is that we
10495 can handle VOIDmode if OP0 is a COMPARE or a comparison
10498 if (GET_MODE_CLASS (mode) != MODE_INT
10499 && ! (mode == VOIDmode
10500 && (GET_CODE (op0) == COMPARE || COMPARISON_P (op0))))
10503 /* Get the constant we are comparing against and turn off all bits
10504 not on in our mode. */
10505 const_op = INTVAL (op1);
10506 if (mode != VOIDmode)
10507 const_op = trunc_int_for_mode (const_op, mode);
10508 op1 = GEN_INT (const_op);
10510 /* If we are comparing against a constant power of two and the value
10511 being compared can only have that single bit nonzero (e.g., it was
10512 `and'ed with that bit), we can replace this with a comparison
10515 && (code == EQ || code == NE || code == GE || code == GEU
10516 || code == LT || code == LTU)
10517 && mode_width <= HOST_BITS_PER_WIDE_INT
10518 && exact_log2 (const_op) >= 0
10519 && nonzero_bits (op0, mode) == (unsigned HOST_WIDE_INT) const_op)
10521 code = (code == EQ || code == GE || code == GEU ? NE : EQ);
10522 op1 = const0_rtx, const_op = 0;
10525 /* Similarly, if we are comparing a value known to be either -1 or
10526 0 with -1, change it to the opposite comparison against zero. */
10529 && (code == EQ || code == NE || code == GT || code == LE
10530 || code == GEU || code == LTU)
10531 && num_sign_bit_copies (op0, mode) == mode_width)
10533 code = (code == EQ || code == LE || code == GEU ? NE : EQ);
10534 op1 = const0_rtx, const_op = 0;
10537 /* Do some canonicalizations based on the comparison code. We prefer
10538 comparisons against zero and then prefer equality comparisons.
10539 If we can reduce the size of a constant, we will do that too. */
10544 /* < C is equivalent to <= (C - 1) */
10548 op1 = GEN_INT (const_op);
10550 /* ... fall through to LE case below. */
10556 /* <= C is equivalent to < (C + 1); we do this for C < 0 */
10560 op1 = GEN_INT (const_op);
10564 /* If we are doing a <= 0 comparison on a value known to have
10565 a zero sign bit, we can replace this with == 0. */
10566 else if (const_op == 0
10567 && mode_width <= HOST_BITS_PER_WIDE_INT
10568 && (nonzero_bits (op0, mode)
10569 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)
10574 /* >= C is equivalent to > (C - 1). */
10578 op1 = GEN_INT (const_op);
10580 /* ... fall through to GT below. */
10586 /* > C is equivalent to >= (C + 1); we do this for C < 0. */
10590 op1 = GEN_INT (const_op);
10594 /* If we are doing a > 0 comparison on a value known to have
10595 a zero sign bit, we can replace this with != 0. */
10596 else if (const_op == 0
10597 && mode_width <= HOST_BITS_PER_WIDE_INT
10598 && (nonzero_bits (op0, mode)
10599 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)
10604 /* < C is equivalent to <= (C - 1). */
10608 op1 = GEN_INT (const_op);
10610 /* ... fall through ... */
10613 /* (unsigned) < 0x80000000 is equivalent to >= 0. */
10614 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
10615 && (const_op == (HOST_WIDE_INT) 1 << (mode_width - 1)))
10617 const_op = 0, op1 = const0_rtx;
10625 /* unsigned <= 0 is equivalent to == 0 */
10629 /* (unsigned) <= 0x7fffffff is equivalent to >= 0. */
10630 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
10631 && (const_op == ((HOST_WIDE_INT) 1 << (mode_width - 1)) - 1))
10633 const_op = 0, op1 = const0_rtx;
10639 /* >= C is equivalent to > (C - 1). */
10643 op1 = GEN_INT (const_op);
10645 /* ... fall through ... */
10648 /* (unsigned) >= 0x80000000 is equivalent to < 0. */
10649 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
10650 && (const_op == (HOST_WIDE_INT) 1 << (mode_width - 1)))
10652 const_op = 0, op1 = const0_rtx;
10660 /* unsigned > 0 is equivalent to != 0 */
10664 /* (unsigned) > 0x7fffffff is equivalent to < 0. */
10665 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
10666 && (const_op == ((HOST_WIDE_INT) 1 << (mode_width - 1)) - 1))
10668 const_op = 0, op1 = const0_rtx;
10677 /* Compute some predicates to simplify code below. */
10679 equality_comparison_p = (code == EQ || code == NE);
10680 sign_bit_comparison_p = ((code == LT || code == GE) && const_op == 0);
10681 unsigned_comparison_p = (code == LTU || code == LEU || code == GTU
10684 /* If this is a sign bit comparison and we can do arithmetic in
10685 MODE, say that we will only be needing the sign bit of OP0. */
10686 if (sign_bit_comparison_p
10687 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
10688 op0 = force_to_mode (op0, mode,
10690 << (GET_MODE_BITSIZE (mode) - 1)),
10693 /* Now try cases based on the opcode of OP0. If none of the cases
10694 does a "continue", we exit this loop immediately after the
10697 switch (GET_CODE (op0))
10700 /* If we are extracting a single bit from a variable position in
10701 a constant that has only a single bit set and are comparing it
10702 with zero, we can convert this into an equality comparison
10703 between the position and the location of the single bit. */
10704 /* Except we can't if SHIFT_COUNT_TRUNCATED is set, since we might
10705 have already reduced the shift count modulo the word size. */
10706 if (!SHIFT_COUNT_TRUNCATED
10707 && CONST_INT_P (XEXP (op0, 0))
10708 && XEXP (op0, 1) == const1_rtx
10709 && equality_comparison_p && const_op == 0
10710 && (i = exact_log2 (INTVAL (XEXP (op0, 0)))) >= 0)
10712 if (BITS_BIG_ENDIAN)
10714 enum machine_mode new_mode
10715 = mode_for_extraction (EP_extzv, 1);
10716 if (new_mode == MAX_MACHINE_MODE)
10717 i = BITS_PER_WORD - 1 - i;
10721 i = (GET_MODE_BITSIZE (mode) - 1 - i);
10725 op0 = XEXP (op0, 2);
10729 /* Result is nonzero iff shift count is equal to I. */
10730 code = reverse_condition (code);
10734 /* ... fall through ... */
10737 tem = expand_compound_operation (op0);
10746 /* If testing for equality, we can take the NOT of the constant. */
10747 if (equality_comparison_p
10748 && (tem = simplify_unary_operation (NOT, mode, op1, mode)) != 0)
10750 op0 = XEXP (op0, 0);
10755 /* If just looking at the sign bit, reverse the sense of the
10757 if (sign_bit_comparison_p)
10759 op0 = XEXP (op0, 0);
10760 code = (code == GE ? LT : GE);
10766 /* If testing for equality, we can take the NEG of the constant. */
10767 if (equality_comparison_p
10768 && (tem = simplify_unary_operation (NEG, mode, op1, mode)) != 0)
10770 op0 = XEXP (op0, 0);
10775 /* The remaining cases only apply to comparisons with zero. */
10779 /* When X is ABS or is known positive,
10780 (neg X) is < 0 if and only if X != 0. */
10782 if (sign_bit_comparison_p
10783 && (GET_CODE (XEXP (op0, 0)) == ABS
10784 || (mode_width <= HOST_BITS_PER_WIDE_INT
10785 && (nonzero_bits (XEXP (op0, 0), mode)
10786 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)))
10788 op0 = XEXP (op0, 0);
10789 code = (code == LT ? NE : EQ);
10793 /* If we have NEG of something whose two high-order bits are the
10794 same, we know that "(-a) < 0" is equivalent to "a > 0". */
10795 if (num_sign_bit_copies (op0, mode) >= 2)
10797 op0 = XEXP (op0, 0);
10798 code = swap_condition (code);
10804 /* If we are testing equality and our count is a constant, we
10805 can perform the inverse operation on our RHS. */
10806 if (equality_comparison_p && CONST_INT_P (XEXP (op0, 1))
10807 && (tem = simplify_binary_operation (ROTATERT, mode,
10808 op1, XEXP (op0, 1))) != 0)
10810 op0 = XEXP (op0, 0);
10815 /* If we are doing a < 0 or >= 0 comparison, it means we are testing
10816 a particular bit. Convert it to an AND of a constant of that
10817 bit. This will be converted into a ZERO_EXTRACT. */
10818 if (const_op == 0 && sign_bit_comparison_p
10819 && CONST_INT_P (XEXP (op0, 1))
10820 && mode_width <= HOST_BITS_PER_WIDE_INT)
10822 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
10825 - INTVAL (XEXP (op0, 1)))));
10826 code = (code == LT ? NE : EQ);
10830 /* Fall through. */
10833 /* ABS is ignorable inside an equality comparison with zero. */
10834 if (const_op == 0 && equality_comparison_p)
10836 op0 = XEXP (op0, 0);
10842 /* Can simplify (compare (zero/sign_extend FOO) CONST) to
10843 (compare FOO CONST) if CONST fits in FOO's mode and we
10844 are either testing inequality or have an unsigned
10845 comparison with ZERO_EXTEND or a signed comparison with
10846 SIGN_EXTEND. But don't do it if we don't have a compare
10847 insn of the given mode, since we'd have to revert it
10848 later on, and then we wouldn't know whether to sign- or
10850 mode = GET_MODE (XEXP (op0, 0));
10851 if (mode != VOIDmode && GET_MODE_CLASS (mode) == MODE_INT
10852 && ! unsigned_comparison_p
10853 && (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
10854 && ((unsigned HOST_WIDE_INT) const_op
10855 < (((unsigned HOST_WIDE_INT) 1
10856 << (GET_MODE_BITSIZE (mode) - 1))))
10857 && have_insn_for (COMPARE, mode))
10859 op0 = XEXP (op0, 0);
10865 /* Check for the case where we are comparing A - C1 with C2, that is
10867 (subreg:MODE (plus (A) (-C1))) op (C2)
10869 with C1 a constant, and try to lift the SUBREG, i.e. to do the
10870 comparison in the wider mode. One of the following two conditions
10871 must be true in order for this to be valid:
10873 1. The mode extension results in the same bit pattern being added
10874 on both sides and the comparison is equality or unsigned. As
10875 C2 has been truncated to fit in MODE, the pattern can only be
10878 2. The mode extension results in the sign bit being copied on
10881 The difficulty here is that we have predicates for A but not for
10882 (A - C1) so we need to check that C1 is within proper bounds so
10883 as to perturbate A as little as possible. */
10885 if (mode_width <= HOST_BITS_PER_WIDE_INT
10886 && subreg_lowpart_p (op0)
10887 && GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0))) > mode_width
10888 && GET_CODE (SUBREG_REG (op0)) == PLUS
10889 && CONST_INT_P (XEXP (SUBREG_REG (op0), 1)))
10891 enum machine_mode inner_mode = GET_MODE (SUBREG_REG (op0));
10892 rtx a = XEXP (SUBREG_REG (op0), 0);
10893 HOST_WIDE_INT c1 = -INTVAL (XEXP (SUBREG_REG (op0), 1));
10896 && (unsigned HOST_WIDE_INT) c1
10897 < (unsigned HOST_WIDE_INT) 1 << (mode_width - 1)
10898 && (equality_comparison_p || unsigned_comparison_p)
10899 /* (A - C1) zero-extends if it is positive and sign-extends
10900 if it is negative, C2 both zero- and sign-extends. */
10901 && ((0 == (nonzero_bits (a, inner_mode)
10902 & ~GET_MODE_MASK (mode))
10904 /* (A - C1) sign-extends if it is positive and 1-extends
10905 if it is negative, C2 both sign- and 1-extends. */
10906 || (num_sign_bit_copies (a, inner_mode)
10907 > (unsigned int) (GET_MODE_BITSIZE (inner_mode)
10910 || ((unsigned HOST_WIDE_INT) c1
10911 < (unsigned HOST_WIDE_INT) 1 << (mode_width - 2)
10912 /* (A - C1) always sign-extends, like C2. */
10913 && num_sign_bit_copies (a, inner_mode)
10914 > (unsigned int) (GET_MODE_BITSIZE (inner_mode)
10915 - (mode_width - 1))))
10917 op0 = SUBREG_REG (op0);
10922 /* If the inner mode is narrower and we are extracting the low part,
10923 we can treat the SUBREG as if it were a ZERO_EXTEND. */
10924 if (subreg_lowpart_p (op0)
10925 && GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0))) < mode_width)
10926 /* Fall through */ ;
10930 /* ... fall through ... */
10933 mode = GET_MODE (XEXP (op0, 0));
10934 if (mode != VOIDmode && GET_MODE_CLASS (mode) == MODE_INT
10935 && (unsigned_comparison_p || equality_comparison_p)
10936 && (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
10937 && ((unsigned HOST_WIDE_INT) const_op < GET_MODE_MASK (mode))
10938 && have_insn_for (COMPARE, mode))
10940 op0 = XEXP (op0, 0);
10946 /* (eq (plus X A) B) -> (eq X (minus B A)). We can only do
10947 this for equality comparisons due to pathological cases involving
10949 if (equality_comparison_p
10950 && 0 != (tem = simplify_binary_operation (MINUS, mode,
10951 op1, XEXP (op0, 1))))
10953 op0 = XEXP (op0, 0);
10958 /* (plus (abs X) (const_int -1)) is < 0 if and only if X == 0. */
10959 if (const_op == 0 && XEXP (op0, 1) == constm1_rtx
10960 && GET_CODE (XEXP (op0, 0)) == ABS && sign_bit_comparison_p)
10962 op0 = XEXP (XEXP (op0, 0), 0);
10963 code = (code == LT ? EQ : NE);
10969 /* We used to optimize signed comparisons against zero, but that
10970 was incorrect. Unsigned comparisons against zero (GTU, LEU)
10971 arrive here as equality comparisons, or (GEU, LTU) are
10972 optimized away. No need to special-case them. */
10974 /* (eq (minus A B) C) -> (eq A (plus B C)) or
10975 (eq B (minus A C)), whichever simplifies. We can only do
10976 this for equality comparisons due to pathological cases involving
10978 if (equality_comparison_p
10979 && 0 != (tem = simplify_binary_operation (PLUS, mode,
10980 XEXP (op0, 1), op1)))
10982 op0 = XEXP (op0, 0);
10987 if (equality_comparison_p
10988 && 0 != (tem = simplify_binary_operation (MINUS, mode,
10989 XEXP (op0, 0), op1)))
10991 op0 = XEXP (op0, 1);
10996 /* The sign bit of (minus (ashiftrt X C) X), where C is the number
10997 of bits in X minus 1, is one iff X > 0. */
10998 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == ASHIFTRT
10999 && CONST_INT_P (XEXP (XEXP (op0, 0), 1))
11000 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (XEXP (op0, 0), 1))
11002 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
11004 op0 = XEXP (op0, 1);
11005 code = (code == GE ? LE : GT);
11011 /* (eq (xor A B) C) -> (eq A (xor B C)). This is a simplification
11012 if C is zero or B is a constant. */
11013 if (equality_comparison_p
11014 && 0 != (tem = simplify_binary_operation (XOR, mode,
11015 XEXP (op0, 1), op1)))
11017 op0 = XEXP (op0, 0);
11024 case UNEQ: case LTGT:
11025 case LT: case LTU: case UNLT: case LE: case LEU: case UNLE:
11026 case GT: case GTU: case UNGT: case GE: case GEU: case UNGE:
11027 case UNORDERED: case ORDERED:
11028 /* We can't do anything if OP0 is a condition code value, rather
11029 than an actual data value. */
11031 || CC0_P (XEXP (op0, 0))
11032 || GET_MODE_CLASS (GET_MODE (XEXP (op0, 0))) == MODE_CC)
11035 /* Get the two operands being compared. */
11036 if (GET_CODE (XEXP (op0, 0)) == COMPARE)
11037 tem = XEXP (XEXP (op0, 0), 0), tem1 = XEXP (XEXP (op0, 0), 1);
11039 tem = XEXP (op0, 0), tem1 = XEXP (op0, 1);
11041 /* Check for the cases where we simply want the result of the
11042 earlier test or the opposite of that result. */
11043 if (code == NE || code == EQ
11044 || (GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
11045 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
11046 && (STORE_FLAG_VALUE
11047 & (((HOST_WIDE_INT) 1
11048 << (GET_MODE_BITSIZE (GET_MODE (op0)) - 1))))
11049 && (code == LT || code == GE)))
11051 enum rtx_code new_code;
11052 if (code == LT || code == NE)
11053 new_code = GET_CODE (op0);
11055 new_code = reversed_comparison_code (op0, NULL);
11057 if (new_code != UNKNOWN)
11068 /* The sign bit of (ior (plus X (const_int -1)) X) is nonzero
11070 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == PLUS
11071 && XEXP (XEXP (op0, 0), 1) == constm1_rtx
11072 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
11074 op0 = XEXP (op0, 1);
11075 code = (code == GE ? GT : LE);
11081 /* Convert (and (xshift 1 X) Y) to (and (lshiftrt Y X) 1). This
11082 will be converted to a ZERO_EXTRACT later. */
11083 if (const_op == 0 && equality_comparison_p
11084 && GET_CODE (XEXP (op0, 0)) == ASHIFT
11085 && XEXP (XEXP (op0, 0), 0) == const1_rtx)
11087 op0 = simplify_and_const_int
11088 (NULL_RTX, mode, gen_rtx_LSHIFTRT (mode,
11090 XEXP (XEXP (op0, 0), 1)),
11091 (HOST_WIDE_INT) 1);
11095 /* If we are comparing (and (lshiftrt X C1) C2) for equality with
11096 zero and X is a comparison and C1 and C2 describe only bits set
11097 in STORE_FLAG_VALUE, we can compare with X. */
11098 if (const_op == 0 && equality_comparison_p
11099 && mode_width <= HOST_BITS_PER_WIDE_INT
11100 && CONST_INT_P (XEXP (op0, 1))
11101 && GET_CODE (XEXP (op0, 0)) == LSHIFTRT
11102 && CONST_INT_P (XEXP (XEXP (op0, 0), 1))
11103 && INTVAL (XEXP (XEXP (op0, 0), 1)) >= 0
11104 && INTVAL (XEXP (XEXP (op0, 0), 1)) < HOST_BITS_PER_WIDE_INT)
11106 mask = ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
11107 << INTVAL (XEXP (XEXP (op0, 0), 1)));
11108 if ((~STORE_FLAG_VALUE & mask) == 0
11109 && (COMPARISON_P (XEXP (XEXP (op0, 0), 0))
11110 || ((tem = get_last_value (XEXP (XEXP (op0, 0), 0))) != 0
11111 && COMPARISON_P (tem))))
11113 op0 = XEXP (XEXP (op0, 0), 0);
11118 /* If we are doing an equality comparison of an AND of a bit equal
11119 to the sign bit, replace this with a LT or GE comparison of
11120 the underlying value. */
11121 if (equality_comparison_p
11123 && CONST_INT_P (XEXP (op0, 1))
11124 && mode_width <= HOST_BITS_PER_WIDE_INT
11125 && ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
11126 == (unsigned HOST_WIDE_INT) 1 << (mode_width - 1)))
11128 op0 = XEXP (op0, 0);
11129 code = (code == EQ ? GE : LT);
11133 /* If this AND operation is really a ZERO_EXTEND from a narrower
11134 mode, the constant fits within that mode, and this is either an
11135 equality or unsigned comparison, try to do this comparison in
11140 (ne:DI (and:DI (reg:DI 4) (const_int 0xffffffff)) (const_int 0))
11141 -> (ne:DI (reg:SI 4) (const_int 0))
11143 unless TRULY_NOOP_TRUNCATION allows it or the register is
11144 known to hold a value of the required mode the
11145 transformation is invalid. */
11146 if ((equality_comparison_p || unsigned_comparison_p)
11147 && CONST_INT_P (XEXP (op0, 1))
11148 && (i = exact_log2 ((INTVAL (XEXP (op0, 1))
11149 & GET_MODE_MASK (mode))
11151 && const_op >> i == 0
11152 && (tmode = mode_for_size (i, MODE_INT, 1)) != BLKmode
11153 && (TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (tmode),
11154 GET_MODE_BITSIZE (GET_MODE (op0)))
11155 || (REG_P (XEXP (op0, 0))
11156 && reg_truncated_to_mode (tmode, XEXP (op0, 0)))))
11158 op0 = gen_lowpart (tmode, XEXP (op0, 0));
11162 /* If this is (and:M1 (subreg:M2 X 0) (const_int C1)) where C1
11163 fits in both M1 and M2 and the SUBREG is either paradoxical
11164 or represents the low part, permute the SUBREG and the AND
11166 if (GET_CODE (XEXP (op0, 0)) == SUBREG)
11168 unsigned HOST_WIDE_INT c1;
11169 tmode = GET_MODE (SUBREG_REG (XEXP (op0, 0)));
11170 /* Require an integral mode, to avoid creating something like
11172 if (SCALAR_INT_MODE_P (tmode)
11173 /* It is unsafe to commute the AND into the SUBREG if the
11174 SUBREG is paradoxical and WORD_REGISTER_OPERATIONS is
11175 not defined. As originally written the upper bits
11176 have a defined value due to the AND operation.
11177 However, if we commute the AND inside the SUBREG then
11178 they no longer have defined values and the meaning of
11179 the code has been changed. */
11181 #ifdef WORD_REGISTER_OPERATIONS
11182 || (mode_width > GET_MODE_BITSIZE (tmode)
11183 && mode_width <= BITS_PER_WORD)
11185 || (mode_width <= GET_MODE_BITSIZE (tmode)
11186 && subreg_lowpart_p (XEXP (op0, 0))))
11187 && CONST_INT_P (XEXP (op0, 1))
11188 && mode_width <= HOST_BITS_PER_WIDE_INT
11189 && GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT
11190 && ((c1 = INTVAL (XEXP (op0, 1))) & ~mask) == 0
11191 && (c1 & ~GET_MODE_MASK (tmode)) == 0
11193 && c1 != GET_MODE_MASK (tmode))
11195 op0 = simplify_gen_binary (AND, tmode,
11196 SUBREG_REG (XEXP (op0, 0)),
11197 gen_int_mode (c1, tmode));
11198 op0 = gen_lowpart (mode, op0);
11203 /* Convert (ne (and (not X) 1) 0) to (eq (and X 1) 0). */
11204 if (const_op == 0 && equality_comparison_p
11205 && XEXP (op0, 1) == const1_rtx
11206 && GET_CODE (XEXP (op0, 0)) == NOT)
11208 op0 = simplify_and_const_int
11209 (NULL_RTX, mode, XEXP (XEXP (op0, 0), 0), (HOST_WIDE_INT) 1);
11210 code = (code == NE ? EQ : NE);
11214 /* Convert (ne (and (lshiftrt (not X)) 1) 0) to
11215 (eq (and (lshiftrt X) 1) 0).
11216 Also handle the case where (not X) is expressed using xor. */
11217 if (const_op == 0 && equality_comparison_p
11218 && XEXP (op0, 1) == const1_rtx
11219 && GET_CODE (XEXP (op0, 0)) == LSHIFTRT)
11221 rtx shift_op = XEXP (XEXP (op0, 0), 0);
11222 rtx shift_count = XEXP (XEXP (op0, 0), 1);
11224 if (GET_CODE (shift_op) == NOT
11225 || (GET_CODE (shift_op) == XOR
11226 && CONST_INT_P (XEXP (shift_op, 1))
11227 && CONST_INT_P (shift_count)
11228 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
11229 && (INTVAL (XEXP (shift_op, 1))
11230 == (HOST_WIDE_INT) 1 << INTVAL (shift_count))))
11232 op0 = simplify_and_const_int
11234 gen_rtx_LSHIFTRT (mode, XEXP (shift_op, 0), shift_count),
11235 (HOST_WIDE_INT) 1);
11236 code = (code == NE ? EQ : NE);
11243 /* If we have (compare (ashift FOO N) (const_int C)) and
11244 the high order N bits of FOO (N+1 if an inequality comparison)
11245 are known to be zero, we can do this by comparing FOO with C
11246 shifted right N bits so long as the low-order N bits of C are
11248 if (CONST_INT_P (XEXP (op0, 1))
11249 && INTVAL (XEXP (op0, 1)) >= 0
11250 && ((INTVAL (XEXP (op0, 1)) + ! equality_comparison_p)
11251 < HOST_BITS_PER_WIDE_INT)
11253 & (((HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1))) - 1)) == 0)
11254 && mode_width <= HOST_BITS_PER_WIDE_INT
11255 && (nonzero_bits (XEXP (op0, 0), mode)
11256 & ~(mask >> (INTVAL (XEXP (op0, 1))
11257 + ! equality_comparison_p))) == 0)
11259 /* We must perform a logical shift, not an arithmetic one,
11260 as we want the top N bits of C to be zero. */
11261 unsigned HOST_WIDE_INT temp = const_op & GET_MODE_MASK (mode);
11263 temp >>= INTVAL (XEXP (op0, 1));
11264 op1 = gen_int_mode (temp, mode);
11265 op0 = XEXP (op0, 0);
11269 /* If we are doing a sign bit comparison, it means we are testing
11270 a particular bit. Convert it to the appropriate AND. */
11271 if (sign_bit_comparison_p && CONST_INT_P (XEXP (op0, 1))
11272 && mode_width <= HOST_BITS_PER_WIDE_INT)
11274 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
11277 - INTVAL (XEXP (op0, 1)))));
11278 code = (code == LT ? NE : EQ);
11282 /* If this an equality comparison with zero and we are shifting
11283 the low bit to the sign bit, we can convert this to an AND of the
11285 if (const_op == 0 && equality_comparison_p
11286 && CONST_INT_P (XEXP (op0, 1))
11287 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (op0, 1))
11290 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
11291 (HOST_WIDE_INT) 1);
11297 /* If this is an equality comparison with zero, we can do this
11298 as a logical shift, which might be much simpler. */
11299 if (equality_comparison_p && const_op == 0
11300 && CONST_INT_P (XEXP (op0, 1)))
11302 op0 = simplify_shift_const (NULL_RTX, LSHIFTRT, mode,
11304 INTVAL (XEXP (op0, 1)));
11308 /* If OP0 is a sign extension and CODE is not an unsigned comparison,
11309 do the comparison in a narrower mode. */
11310 if (! unsigned_comparison_p
11311 && CONST_INT_P (XEXP (op0, 1))
11312 && GET_CODE (XEXP (op0, 0)) == ASHIFT
11313 && XEXP (op0, 1) == XEXP (XEXP (op0, 0), 1)
11314 && (tmode = mode_for_size (mode_width - INTVAL (XEXP (op0, 1)),
11315 MODE_INT, 1)) != BLKmode
11316 && (((unsigned HOST_WIDE_INT) const_op
11317 + (GET_MODE_MASK (tmode) >> 1) + 1)
11318 <= GET_MODE_MASK (tmode)))
11320 op0 = gen_lowpart (tmode, XEXP (XEXP (op0, 0), 0));
11324 /* Likewise if OP0 is a PLUS of a sign extension with a
11325 constant, which is usually represented with the PLUS
11326 between the shifts. */
11327 if (! unsigned_comparison_p
11328 && CONST_INT_P (XEXP (op0, 1))
11329 && GET_CODE (XEXP (op0, 0)) == PLUS
11330 && CONST_INT_P (XEXP (XEXP (op0, 0), 1))
11331 && GET_CODE (XEXP (XEXP (op0, 0), 0)) == ASHIFT
11332 && XEXP (op0, 1) == XEXP (XEXP (XEXP (op0, 0), 0), 1)
11333 && (tmode = mode_for_size (mode_width - INTVAL (XEXP (op0, 1)),
11334 MODE_INT, 1)) != BLKmode
11335 && (((unsigned HOST_WIDE_INT) const_op
11336 + (GET_MODE_MASK (tmode) >> 1) + 1)
11337 <= GET_MODE_MASK (tmode)))
11339 rtx inner = XEXP (XEXP (XEXP (op0, 0), 0), 0);
11340 rtx add_const = XEXP (XEXP (op0, 0), 1);
11341 rtx new_const = simplify_gen_binary (ASHIFTRT, GET_MODE (op0),
11342 add_const, XEXP (op0, 1));
11344 op0 = simplify_gen_binary (PLUS, tmode,
11345 gen_lowpart (tmode, inner),
11350 /* ... fall through ... */
11352 /* If we have (compare (xshiftrt FOO N) (const_int C)) and
11353 the low order N bits of FOO are known to be zero, we can do this
11354 by comparing FOO with C shifted left N bits so long as no
11355 overflow occurs. */
11356 if (CONST_INT_P (XEXP (op0, 1))
11357 && INTVAL (XEXP (op0, 1)) >= 0
11358 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT
11359 && mode_width <= HOST_BITS_PER_WIDE_INT
11360 && (nonzero_bits (XEXP (op0, 0), mode)
11361 & (((HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1))) - 1)) == 0
11362 && (((unsigned HOST_WIDE_INT) const_op
11363 + (GET_CODE (op0) != LSHIFTRT
11364 ? ((GET_MODE_MASK (mode) >> INTVAL (XEXP (op0, 1)) >> 1)
11367 <= GET_MODE_MASK (mode) >> INTVAL (XEXP (op0, 1))))
11369 /* If the shift was logical, then we must make the condition
11371 if (GET_CODE (op0) == LSHIFTRT)
11372 code = unsigned_condition (code);
11374 const_op <<= INTVAL (XEXP (op0, 1));
11375 op1 = GEN_INT (const_op);
11376 op0 = XEXP (op0, 0);
11380 /* If we are using this shift to extract just the sign bit, we
11381 can replace this with an LT or GE comparison. */
11383 && (equality_comparison_p || sign_bit_comparison_p)
11384 && CONST_INT_P (XEXP (op0, 1))
11385 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (op0, 1))
11388 op0 = XEXP (op0, 0);
11389 code = (code == NE || code == GT ? LT : GE);
11401 /* Now make any compound operations involved in this comparison. Then,
11402 check for an outmost SUBREG on OP0 that is not doing anything or is
11403 paradoxical. The latter transformation must only be performed when
11404 it is known that the "extra" bits will be the same in op0 and op1 or
11405 that they don't matter. There are three cases to consider:
11407 1. SUBREG_REG (op0) is a register. In this case the bits are don't
11408 care bits and we can assume they have any convenient value. So
11409 making the transformation is safe.
11411 2. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is not defined.
11412 In this case the upper bits of op0 are undefined. We should not make
11413 the simplification in that case as we do not know the contents of
11416 3. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is defined and not
11417 UNKNOWN. In that case we know those bits are zeros or ones. We must
11418 also be sure that they are the same as the upper bits of op1.
11420 We can never remove a SUBREG for a non-equality comparison because
11421 the sign bit is in a different place in the underlying object. */
11423 op0 = make_compound_operation (op0, op1 == const0_rtx ? COMPARE : SET);
11424 op1 = make_compound_operation (op1, SET);
11426 if (GET_CODE (op0) == SUBREG && subreg_lowpart_p (op0)
11427 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
11428 && GET_MODE_CLASS (GET_MODE (SUBREG_REG (op0))) == MODE_INT
11429 && (code == NE || code == EQ))
11431 if (GET_MODE_SIZE (GET_MODE (op0))
11432 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (op0))))
11434 /* For paradoxical subregs, allow case 1 as above. Case 3 isn't
11436 if (REG_P (SUBREG_REG (op0)))
11438 op0 = SUBREG_REG (op0);
11439 op1 = gen_lowpart (GET_MODE (op0), op1);
11442 else if ((GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0)))
11443 <= HOST_BITS_PER_WIDE_INT)
11444 && (nonzero_bits (SUBREG_REG (op0),
11445 GET_MODE (SUBREG_REG (op0)))
11446 & ~GET_MODE_MASK (GET_MODE (op0))) == 0)
11448 tem = gen_lowpart (GET_MODE (SUBREG_REG (op0)), op1);
11450 if ((nonzero_bits (tem, GET_MODE (SUBREG_REG (op0)))
11451 & ~GET_MODE_MASK (GET_MODE (op0))) == 0)
11452 op0 = SUBREG_REG (op0), op1 = tem;
11456 /* We now do the opposite procedure: Some machines don't have compare
11457 insns in all modes. If OP0's mode is an integer mode smaller than a
11458 word and we can't do a compare in that mode, see if there is a larger
11459 mode for which we can do the compare. There are a number of cases in
11460 which we can use the wider mode. */
11462 mode = GET_MODE (op0);
11463 if (mode != VOIDmode && GET_MODE_CLASS (mode) == MODE_INT
11464 && GET_MODE_SIZE (mode) < UNITS_PER_WORD
11465 && ! have_insn_for (COMPARE, mode))
11466 for (tmode = GET_MODE_WIDER_MODE (mode);
11468 && GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT);
11469 tmode = GET_MODE_WIDER_MODE (tmode))
11470 if (have_insn_for (COMPARE, tmode))
11474 /* If this is a test for negative, we can make an explicit
11475 test of the sign bit. Test this first so we can use
11476 a paradoxical subreg to extend OP0. */
11478 if (op1 == const0_rtx && (code == LT || code == GE)
11479 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
11481 op0 = simplify_gen_binary (AND, tmode,
11482 gen_lowpart (tmode, op0),
11483 GEN_INT ((HOST_WIDE_INT) 1
11484 << (GET_MODE_BITSIZE (mode)
11486 code = (code == LT) ? NE : EQ;
11490 /* If the only nonzero bits in OP0 and OP1 are those in the
11491 narrower mode and this is an equality or unsigned comparison,
11492 we can use the wider mode. Similarly for sign-extended
11493 values, in which case it is true for all comparisons. */
11494 zero_extended = ((code == EQ || code == NE
11495 || code == GEU || code == GTU
11496 || code == LEU || code == LTU)
11497 && (nonzero_bits (op0, tmode)
11498 & ~GET_MODE_MASK (mode)) == 0
11499 && ((CONST_INT_P (op1)
11500 || (nonzero_bits (op1, tmode)
11501 & ~GET_MODE_MASK (mode)) == 0)));
11504 || ((num_sign_bit_copies (op0, tmode)
11505 > (unsigned int) (GET_MODE_BITSIZE (tmode)
11506 - GET_MODE_BITSIZE (mode)))
11507 && (num_sign_bit_copies (op1, tmode)
11508 > (unsigned int) (GET_MODE_BITSIZE (tmode)
11509 - GET_MODE_BITSIZE (mode)))))
11511 /* If OP0 is an AND and we don't have an AND in MODE either,
11512 make a new AND in the proper mode. */
11513 if (GET_CODE (op0) == AND
11514 && !have_insn_for (AND, mode))
11515 op0 = simplify_gen_binary (AND, tmode,
11516 gen_lowpart (tmode,
11518 gen_lowpart (tmode,
11524 op0 = simplify_gen_unary (ZERO_EXTEND, tmode, op0, mode);
11525 op1 = simplify_gen_unary (ZERO_EXTEND, tmode, op1, mode);
11529 op0 = simplify_gen_unary (SIGN_EXTEND, tmode, op0, mode);
11530 op1 = simplify_gen_unary (SIGN_EXTEND, tmode, op1, mode);
11537 #ifdef CANONICALIZE_COMPARISON
11538 /* If this machine only supports a subset of valid comparisons, see if we
11539 can convert an unsupported one into a supported one. */
11540 CANONICALIZE_COMPARISON (code, op0, op1);
11549 /* Utility function for record_value_for_reg. Count number of
11554 enum rtx_code code = GET_CODE (x);
11558 if (GET_RTX_CLASS (code) == '2'
11559 || GET_RTX_CLASS (code) == 'c')
11561 rtx x0 = XEXP (x, 0);
11562 rtx x1 = XEXP (x, 1);
11565 return 1 + 2 * count_rtxs (x0);
11567 if ((GET_RTX_CLASS (GET_CODE (x1)) == '2'
11568 || GET_RTX_CLASS (GET_CODE (x1)) == 'c')
11569 && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1)))
11570 return 2 + 2 * count_rtxs (x0)
11571 + count_rtxs (x == XEXP (x1, 0)
11572 ? XEXP (x1, 1) : XEXP (x1, 0));
11574 if ((GET_RTX_CLASS (GET_CODE (x0)) == '2'
11575 || GET_RTX_CLASS (GET_CODE (x0)) == 'c')
11576 && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1)))
11577 return 2 + 2 * count_rtxs (x1)
11578 + count_rtxs (x == XEXP (x0, 0)
11579 ? XEXP (x0, 1) : XEXP (x0, 0));
11582 fmt = GET_RTX_FORMAT (code);
11583 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
11585 ret += count_rtxs (XEXP (x, i));
11586 else if (fmt[i] == 'E')
11587 for (j = 0; j < XVECLEN (x, i); j++)
11588 ret += count_rtxs (XVECEXP (x, i, j));
11593 /* Utility function for following routine. Called when X is part of a value
11594 being stored into last_set_value. Sets last_set_table_tick
11595 for each register mentioned. Similar to mention_regs in cse.c */
11598 update_table_tick (rtx x)
11600 enum rtx_code code = GET_CODE (x);
11601 const char *fmt = GET_RTX_FORMAT (code);
11606 unsigned int regno = REGNO (x);
11607 unsigned int endregno = END_REGNO (x);
11610 for (r = regno; r < endregno; r++)
11612 reg_stat_type *rsp = VEC_index (reg_stat_type, reg_stat, r);
11613 rsp->last_set_table_tick = label_tick;
11619 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
11622 /* Check for identical subexpressions. If x contains
11623 identical subexpression we only have to traverse one of
11625 if (i == 0 && ARITHMETIC_P (x))
11627 /* Note that at this point x1 has already been
11629 rtx x0 = XEXP (x, 0);
11630 rtx x1 = XEXP (x, 1);
11632 /* If x0 and x1 are identical then there is no need to
11637 /* If x0 is identical to a subexpression of x1 then while
11638 processing x1, x0 has already been processed. Thus we
11639 are done with x. */
11640 if (ARITHMETIC_P (x1)
11641 && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1)))
11644 /* If x1 is identical to a subexpression of x0 then we
11645 still have to process the rest of x0. */
11646 if (ARITHMETIC_P (x0)
11647 && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1)))
11649 update_table_tick (XEXP (x0, x1 == XEXP (x0, 0) ? 1 : 0));
11654 update_table_tick (XEXP (x, i));
11656 else if (fmt[i] == 'E')
11657 for (j = 0; j < XVECLEN (x, i); j++)
11658 update_table_tick (XVECEXP (x, i, j));
11661 /* Record that REG is set to VALUE in insn INSN. If VALUE is zero, we
11662 are saying that the register is clobbered and we no longer know its
11663 value. If INSN is zero, don't update reg_stat[].last_set; this is
11664 only permitted with VALUE also zero and is used to invalidate the
11668 record_value_for_reg (rtx reg, rtx insn, rtx value)
11670 unsigned int regno = REGNO (reg);
11671 unsigned int endregno = END_REGNO (reg);
11673 reg_stat_type *rsp;
11675 /* If VALUE contains REG and we have a previous value for REG, substitute
11676 the previous value. */
11677 if (value && insn && reg_overlap_mentioned_p (reg, value))
11681 /* Set things up so get_last_value is allowed to see anything set up to
11683 subst_low_luid = DF_INSN_LUID (insn);
11684 tem = get_last_value (reg);
11686 /* If TEM is simply a binary operation with two CLOBBERs as operands,
11687 it isn't going to be useful and will take a lot of time to process,
11688 so just use the CLOBBER. */
11692 if (ARITHMETIC_P (tem)
11693 && GET_CODE (XEXP (tem, 0)) == CLOBBER
11694 && GET_CODE (XEXP (tem, 1)) == CLOBBER)
11695 tem = XEXP (tem, 0);
11696 else if (count_occurrences (value, reg, 1) >= 2)
11698 /* If there are two or more occurrences of REG in VALUE,
11699 prevent the value from growing too much. */
11700 if (count_rtxs (tem) > MAX_LAST_VALUE_RTL)
11701 tem = gen_rtx_CLOBBER (GET_MODE (tem), const0_rtx);
11704 value = replace_rtx (copy_rtx (value), reg, tem);
11708 /* For each register modified, show we don't know its value, that
11709 we don't know about its bitwise content, that its value has been
11710 updated, and that we don't know the location of the death of the
11712 for (i = regno; i < endregno; i++)
11714 rsp = VEC_index (reg_stat_type, reg_stat, i);
11717 rsp->last_set = insn;
11719 rsp->last_set_value = 0;
11720 rsp->last_set_mode = VOIDmode;
11721 rsp->last_set_nonzero_bits = 0;
11722 rsp->last_set_sign_bit_copies = 0;
11723 rsp->last_death = 0;
11724 rsp->truncated_to_mode = VOIDmode;
11727 /* Mark registers that are being referenced in this value. */
11729 update_table_tick (value);
11731 /* Now update the status of each register being set.
11732 If someone is using this register in this block, set this register
11733 to invalid since we will get confused between the two lives in this
11734 basic block. This makes using this register always invalid. In cse, we
11735 scan the table to invalidate all entries using this register, but this
11736 is too much work for us. */
11738 for (i = regno; i < endregno; i++)
11740 rsp = VEC_index (reg_stat_type, reg_stat, i);
11741 rsp->last_set_label = label_tick;
11743 || (value && rsp->last_set_table_tick >= label_tick_ebb_start))
11744 rsp->last_set_invalid = 1;
11746 rsp->last_set_invalid = 0;
11749 /* The value being assigned might refer to X (like in "x++;"). In that
11750 case, we must replace it with (clobber (const_int 0)) to prevent
11752 rsp = VEC_index (reg_stat_type, reg_stat, regno);
11753 if (value && !get_last_value_validate (&value, insn, label_tick, 0))
11755 value = copy_rtx (value);
11756 if (!get_last_value_validate (&value, insn, label_tick, 1))
11760 /* For the main register being modified, update the value, the mode, the
11761 nonzero bits, and the number of sign bit copies. */
11763 rsp->last_set_value = value;
11767 enum machine_mode mode = GET_MODE (reg);
11768 subst_low_luid = DF_INSN_LUID (insn);
11769 rsp->last_set_mode = mode;
11770 if (GET_MODE_CLASS (mode) == MODE_INT
11771 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
11772 mode = nonzero_bits_mode;
11773 rsp->last_set_nonzero_bits = nonzero_bits (value, mode);
11774 rsp->last_set_sign_bit_copies
11775 = num_sign_bit_copies (value, GET_MODE (reg));
11779 /* Called via note_stores from record_dead_and_set_regs to handle one
11780 SET or CLOBBER in an insn. DATA is the instruction in which the
11781 set is occurring. */
11784 record_dead_and_set_regs_1 (rtx dest, const_rtx setter, void *data)
11786 rtx record_dead_insn = (rtx) data;
11788 if (GET_CODE (dest) == SUBREG)
11789 dest = SUBREG_REG (dest);
11791 if (!record_dead_insn)
11794 record_value_for_reg (dest, NULL_RTX, NULL_RTX);
11800 /* If we are setting the whole register, we know its value. Otherwise
11801 show that we don't know the value. We can handle SUBREG in
11803 if (GET_CODE (setter) == SET && dest == SET_DEST (setter))
11804 record_value_for_reg (dest, record_dead_insn, SET_SRC (setter));
11805 else if (GET_CODE (setter) == SET
11806 && GET_CODE (SET_DEST (setter)) == SUBREG
11807 && SUBREG_REG (SET_DEST (setter)) == dest
11808 && GET_MODE_BITSIZE (GET_MODE (dest)) <= BITS_PER_WORD
11809 && subreg_lowpart_p (SET_DEST (setter)))
11810 record_value_for_reg (dest, record_dead_insn,
11811 gen_lowpart (GET_MODE (dest),
11812 SET_SRC (setter)));
11814 record_value_for_reg (dest, record_dead_insn, NULL_RTX);
11816 else if (MEM_P (dest)
11817 /* Ignore pushes, they clobber nothing. */
11818 && ! push_operand (dest, GET_MODE (dest)))
11819 mem_last_set = DF_INSN_LUID (record_dead_insn);
11822 /* Update the records of when each REG was most recently set or killed
11823 for the things done by INSN. This is the last thing done in processing
11824 INSN in the combiner loop.
11826 We update reg_stat[], in particular fields last_set, last_set_value,
11827 last_set_mode, last_set_nonzero_bits, last_set_sign_bit_copies,
11828 last_death, and also the similar information mem_last_set (which insn
11829 most recently modified memory) and last_call_luid (which insn was the
11830 most recent subroutine call). */
11833 record_dead_and_set_regs (rtx insn)
11838 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
11840 if (REG_NOTE_KIND (link) == REG_DEAD
11841 && REG_P (XEXP (link, 0)))
11843 unsigned int regno = REGNO (XEXP (link, 0));
11844 unsigned int endregno = END_REGNO (XEXP (link, 0));
11846 for (i = regno; i < endregno; i++)
11848 reg_stat_type *rsp;
11850 rsp = VEC_index (reg_stat_type, reg_stat, i);
11851 rsp->last_death = insn;
11854 else if (REG_NOTE_KIND (link) == REG_INC)
11855 record_value_for_reg (XEXP (link, 0), insn, NULL_RTX);
11860 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
11861 if (TEST_HARD_REG_BIT (regs_invalidated_by_call, i))
11863 reg_stat_type *rsp;
11865 rsp = VEC_index (reg_stat_type, reg_stat, i);
11866 rsp->last_set_invalid = 1;
11867 rsp->last_set = insn;
11868 rsp->last_set_value = 0;
11869 rsp->last_set_mode = VOIDmode;
11870 rsp->last_set_nonzero_bits = 0;
11871 rsp->last_set_sign_bit_copies = 0;
11872 rsp->last_death = 0;
11873 rsp->truncated_to_mode = VOIDmode;
11876 last_call_luid = mem_last_set = DF_INSN_LUID (insn);
11878 /* We can't combine into a call pattern. Remember, though, that
11879 the return value register is set at this LUID. We could
11880 still replace a register with the return value from the
11881 wrong subroutine call! */
11882 note_stores (PATTERN (insn), record_dead_and_set_regs_1, NULL_RTX);
11885 note_stores (PATTERN (insn), record_dead_and_set_regs_1, insn);
11888 /* If a SUBREG has the promoted bit set, it is in fact a property of the
11889 register present in the SUBREG, so for each such SUBREG go back and
11890 adjust nonzero and sign bit information of the registers that are
11891 known to have some zero/sign bits set.
11893 This is needed because when combine blows the SUBREGs away, the
11894 information on zero/sign bits is lost and further combines can be
11895 missed because of that. */
11898 record_promoted_value (rtx insn, rtx subreg)
11901 unsigned int regno = REGNO (SUBREG_REG (subreg));
11902 enum machine_mode mode = GET_MODE (subreg);
11904 if (GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT)
11907 for (links = LOG_LINKS (insn); links;)
11909 reg_stat_type *rsp;
11911 insn = XEXP (links, 0);
11912 set = single_set (insn);
11914 if (! set || !REG_P (SET_DEST (set))
11915 || REGNO (SET_DEST (set)) != regno
11916 || GET_MODE (SET_DEST (set)) != GET_MODE (SUBREG_REG (subreg)))
11918 links = XEXP (links, 1);
11922 rsp = VEC_index (reg_stat_type, reg_stat, regno);
11923 if (rsp->last_set == insn)
11925 if (SUBREG_PROMOTED_UNSIGNED_P (subreg) > 0)
11926 rsp->last_set_nonzero_bits &= GET_MODE_MASK (mode);
11929 if (REG_P (SET_SRC (set)))
11931 regno = REGNO (SET_SRC (set));
11932 links = LOG_LINKS (insn);
11939 /* Check if X, a register, is known to contain a value already
11940 truncated to MODE. In this case we can use a subreg to refer to
11941 the truncated value even though in the generic case we would need
11942 an explicit truncation. */
11945 reg_truncated_to_mode (enum machine_mode mode, const_rtx x)
11947 reg_stat_type *rsp = VEC_index (reg_stat_type, reg_stat, REGNO (x));
11948 enum machine_mode truncated = rsp->truncated_to_mode;
11951 || rsp->truncation_label < label_tick_ebb_start)
11953 if (GET_MODE_SIZE (truncated) <= GET_MODE_SIZE (mode))
11955 if (TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode),
11956 GET_MODE_BITSIZE (truncated)))
11961 /* Callback for for_each_rtx. If *P is a hard reg or a subreg record the mode
11962 that the register is accessed in. For non-TRULY_NOOP_TRUNCATION targets we
11963 might be able to turn a truncate into a subreg using this information.
11964 Return -1 if traversing *P is complete or 0 otherwise. */
11967 record_truncated_value (rtx *p, void *data ATTRIBUTE_UNUSED)
11970 enum machine_mode truncated_mode;
11971 reg_stat_type *rsp;
11973 if (GET_CODE (x) == SUBREG && REG_P (SUBREG_REG (x)))
11975 enum machine_mode original_mode = GET_MODE (SUBREG_REG (x));
11976 truncated_mode = GET_MODE (x);
11978 if (GET_MODE_SIZE (original_mode) <= GET_MODE_SIZE (truncated_mode))
11981 if (TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (truncated_mode),
11982 GET_MODE_BITSIZE (original_mode)))
11985 x = SUBREG_REG (x);
11987 /* ??? For hard-regs we now record everything. We might be able to
11988 optimize this using last_set_mode. */
11989 else if (REG_P (x) && REGNO (x) < FIRST_PSEUDO_REGISTER)
11990 truncated_mode = GET_MODE (x);
11994 rsp = VEC_index (reg_stat_type, reg_stat, REGNO (x));
11995 if (rsp->truncated_to_mode == 0
11996 || rsp->truncation_label < label_tick_ebb_start
11997 || (GET_MODE_SIZE (truncated_mode)
11998 < GET_MODE_SIZE (rsp->truncated_to_mode)))
12000 rsp->truncated_to_mode = truncated_mode;
12001 rsp->truncation_label = label_tick;
12007 /* Callback for note_uses. Find hardregs and subregs of pseudos and
12008 the modes they are used in. This can help truning TRUNCATEs into
12012 record_truncated_values (rtx *x, void *data ATTRIBUTE_UNUSED)
12014 for_each_rtx (x, record_truncated_value, NULL);
12017 /* Scan X for promoted SUBREGs. For each one found,
12018 note what it implies to the registers used in it. */
12021 check_promoted_subreg (rtx insn, rtx x)
12023 if (GET_CODE (x) == SUBREG
12024 && SUBREG_PROMOTED_VAR_P (x)
12025 && REG_P (SUBREG_REG (x)))
12026 record_promoted_value (insn, x);
12029 const char *format = GET_RTX_FORMAT (GET_CODE (x));
12032 for (i = 0; i < GET_RTX_LENGTH (GET_CODE (x)); i++)
12036 check_promoted_subreg (insn, XEXP (x, i));
12040 if (XVEC (x, i) != 0)
12041 for (j = 0; j < XVECLEN (x, i); j++)
12042 check_promoted_subreg (insn, XVECEXP (x, i, j));
12048 /* Verify that all the registers and memory references mentioned in *LOC are
12049 still valid. *LOC was part of a value set in INSN when label_tick was
12050 equal to TICK. Return 0 if some are not. If REPLACE is nonzero, replace
12051 the invalid references with (clobber (const_int 0)) and return 1. This
12052 replacement is useful because we often can get useful information about
12053 the form of a value (e.g., if it was produced by a shift that always
12054 produces -1 or 0) even though we don't know exactly what registers it
12055 was produced from. */
12058 get_last_value_validate (rtx *loc, rtx insn, int tick, int replace)
12061 const char *fmt = GET_RTX_FORMAT (GET_CODE (x));
12062 int len = GET_RTX_LENGTH (GET_CODE (x));
12067 unsigned int regno = REGNO (x);
12068 unsigned int endregno = END_REGNO (x);
12071 for (j = regno; j < endregno; j++)
12073 reg_stat_type *rsp = VEC_index (reg_stat_type, reg_stat, j);
12074 if (rsp->last_set_invalid
12075 /* If this is a pseudo-register that was only set once and not
12076 live at the beginning of the function, it is always valid. */
12077 || (! (regno >= FIRST_PSEUDO_REGISTER
12078 && REG_N_SETS (regno) == 1
12079 && (!REGNO_REG_SET_P
12080 (DF_LR_IN (ENTRY_BLOCK_PTR->next_bb), regno)))
12081 && rsp->last_set_label > tick))
12084 *loc = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
12091 /* If this is a memory reference, make sure that there were no stores after
12092 it that might have clobbered the value. We don't have alias info, so we
12093 assume any store invalidates it. Moreover, we only have local UIDs, so
12094 we also assume that there were stores in the intervening basic blocks. */
12095 else if (MEM_P (x) && !MEM_READONLY_P (x)
12096 && (tick != label_tick || DF_INSN_LUID (insn) <= mem_last_set))
12099 *loc = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
12103 for (i = 0; i < len; i++)
12107 /* Check for identical subexpressions. If x contains
12108 identical subexpression we only have to traverse one of
12110 if (i == 1 && ARITHMETIC_P (x))
12112 /* Note that at this point x0 has already been checked
12113 and found valid. */
12114 rtx x0 = XEXP (x, 0);
12115 rtx x1 = XEXP (x, 1);
12117 /* If x0 and x1 are identical then x is also valid. */
12121 /* If x1 is identical to a subexpression of x0 then
12122 while checking x0, x1 has already been checked. Thus
12123 it is valid and so as x. */
12124 if (ARITHMETIC_P (x0)
12125 && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1)))
12128 /* If x0 is identical to a subexpression of x1 then x is
12129 valid iff the rest of x1 is valid. */
12130 if (ARITHMETIC_P (x1)
12131 && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1)))
12133 get_last_value_validate (&XEXP (x1,
12134 x0 == XEXP (x1, 0) ? 1 : 0),
12135 insn, tick, replace);
12138 if (get_last_value_validate (&XEXP (x, i), insn, tick,
12142 else if (fmt[i] == 'E')
12143 for (j = 0; j < XVECLEN (x, i); j++)
12144 if (get_last_value_validate (&XVECEXP (x, i, j),
12145 insn, tick, replace) == 0)
12149 /* If we haven't found a reason for it to be invalid, it is valid. */
12153 /* Get the last value assigned to X, if known. Some registers
12154 in the value may be replaced with (clobber (const_int 0)) if their value
12155 is known longer known reliably. */
12158 get_last_value (const_rtx x)
12160 unsigned int regno;
12162 reg_stat_type *rsp;
12164 /* If this is a non-paradoxical SUBREG, get the value of its operand and
12165 then convert it to the desired mode. If this is a paradoxical SUBREG,
12166 we cannot predict what values the "extra" bits might have. */
12167 if (GET_CODE (x) == SUBREG
12168 && subreg_lowpart_p (x)
12169 && (GET_MODE_SIZE (GET_MODE (x))
12170 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
12171 && (value = get_last_value (SUBREG_REG (x))) != 0)
12172 return gen_lowpart (GET_MODE (x), value);
12178 rsp = VEC_index (reg_stat_type, reg_stat, regno);
12179 value = rsp->last_set_value;
12181 /* If we don't have a value, or if it isn't for this basic block and
12182 it's either a hard register, set more than once, or it's a live
12183 at the beginning of the function, return 0.
12185 Because if it's not live at the beginning of the function then the reg
12186 is always set before being used (is never used without being set).
12187 And, if it's set only once, and it's always set before use, then all
12188 uses must have the same last value, even if it's not from this basic
12192 || (rsp->last_set_label < label_tick_ebb_start
12193 && (regno < FIRST_PSEUDO_REGISTER
12194 || REG_N_SETS (regno) != 1
12196 (DF_LR_IN (ENTRY_BLOCK_PTR->next_bb), regno))))
12199 /* If the value was set in a later insn than the ones we are processing,
12200 we can't use it even if the register was only set once. */
12201 if (rsp->last_set_label == label_tick
12202 && DF_INSN_LUID (rsp->last_set) >= subst_low_luid)
12205 /* If the value has all its registers valid, return it. */
12206 if (get_last_value_validate (&value, rsp->last_set, rsp->last_set_label, 0))
12209 /* Otherwise, make a copy and replace any invalid register with
12210 (clobber (const_int 0)). If that fails for some reason, return 0. */
12212 value = copy_rtx (value);
12213 if (get_last_value_validate (&value, rsp->last_set, rsp->last_set_label, 1))
12219 /* Return nonzero if expression X refers to a REG or to memory
12220 that is set in an instruction more recent than FROM_LUID. */
12223 use_crosses_set_p (const_rtx x, int from_luid)
12227 enum rtx_code code = GET_CODE (x);
12231 unsigned int regno = REGNO (x);
12232 unsigned endreg = END_REGNO (x);
12234 #ifdef PUSH_ROUNDING
12235 /* Don't allow uses of the stack pointer to be moved,
12236 because we don't know whether the move crosses a push insn. */
12237 if (regno == STACK_POINTER_REGNUM && PUSH_ARGS)
12240 for (; regno < endreg; regno++)
12242 reg_stat_type *rsp = VEC_index (reg_stat_type, reg_stat, regno);
12244 && rsp->last_set_label == label_tick
12245 && DF_INSN_LUID (rsp->last_set) > from_luid)
12251 if (code == MEM && mem_last_set > from_luid)
12254 fmt = GET_RTX_FORMAT (code);
12256 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
12261 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
12262 if (use_crosses_set_p (XVECEXP (x, i, j), from_luid))
12265 else if (fmt[i] == 'e'
12266 && use_crosses_set_p (XEXP (x, i), from_luid))
12272 /* Define three variables used for communication between the following
12275 static unsigned int reg_dead_regno, reg_dead_endregno;
12276 static int reg_dead_flag;
12278 /* Function called via note_stores from reg_dead_at_p.
12280 If DEST is within [reg_dead_regno, reg_dead_endregno), set
12281 reg_dead_flag to 1 if X is a CLOBBER and to -1 it is a SET. */
12284 reg_dead_at_p_1 (rtx dest, const_rtx x, void *data ATTRIBUTE_UNUSED)
12286 unsigned int regno, endregno;
12291 regno = REGNO (dest);
12292 endregno = END_REGNO (dest);
12293 if (reg_dead_endregno > regno && reg_dead_regno < endregno)
12294 reg_dead_flag = (GET_CODE (x) == CLOBBER) ? 1 : -1;
12297 /* Return nonzero if REG is known to be dead at INSN.
12299 We scan backwards from INSN. If we hit a REG_DEAD note or a CLOBBER
12300 referencing REG, it is dead. If we hit a SET referencing REG, it is
12301 live. Otherwise, see if it is live or dead at the start of the basic
12302 block we are in. Hard regs marked as being live in NEWPAT_USED_REGS
12303 must be assumed to be always live. */
12306 reg_dead_at_p (rtx reg, rtx insn)
12311 /* Set variables for reg_dead_at_p_1. */
12312 reg_dead_regno = REGNO (reg);
12313 reg_dead_endregno = END_REGNO (reg);
12317 /* Check that reg isn't mentioned in NEWPAT_USED_REGS. For fixed registers
12318 we allow the machine description to decide whether use-and-clobber
12319 patterns are OK. */
12320 if (reg_dead_regno < FIRST_PSEUDO_REGISTER)
12322 for (i = reg_dead_regno; i < reg_dead_endregno; i++)
12323 if (!fixed_regs[i] && TEST_HARD_REG_BIT (newpat_used_regs, i))
12327 /* Scan backwards until we find a REG_DEAD note, SET, CLOBBER, or
12328 beginning of basic block. */
12329 block = BLOCK_FOR_INSN (insn);
12334 note_stores (PATTERN (insn), reg_dead_at_p_1, NULL);
12336 return reg_dead_flag == 1 ? 1 : 0;
12338 if (find_regno_note (insn, REG_DEAD, reg_dead_regno))
12342 if (insn == BB_HEAD (block))
12345 insn = PREV_INSN (insn);
12348 /* Look at live-in sets for the basic block that we were in. */
12349 for (i = reg_dead_regno; i < reg_dead_endregno; i++)
12350 if (REGNO_REG_SET_P (df_get_live_in (block), i))
12356 /* Note hard registers in X that are used. */
12359 mark_used_regs_combine (rtx x)
12361 RTX_CODE code = GET_CODE (x);
12362 unsigned int regno;
12375 case ADDR_DIFF_VEC:
12378 /* CC0 must die in the insn after it is set, so we don't need to take
12379 special note of it here. */
12385 /* If we are clobbering a MEM, mark any hard registers inside the
12386 address as used. */
12387 if (MEM_P (XEXP (x, 0)))
12388 mark_used_regs_combine (XEXP (XEXP (x, 0), 0));
12393 /* A hard reg in a wide mode may really be multiple registers.
12394 If so, mark all of them just like the first. */
12395 if (regno < FIRST_PSEUDO_REGISTER)
12397 /* None of this applies to the stack, frame or arg pointers. */
12398 if (regno == STACK_POINTER_REGNUM
12399 #if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM
12400 || regno == HARD_FRAME_POINTER_REGNUM
12402 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
12403 || (regno == ARG_POINTER_REGNUM && fixed_regs[regno])
12405 || regno == FRAME_POINTER_REGNUM)
12408 add_to_hard_reg_set (&newpat_used_regs, GET_MODE (x), regno);
12414 /* If setting a MEM, or a SUBREG of a MEM, then note any hard regs in
12416 rtx testreg = SET_DEST (x);
12418 while (GET_CODE (testreg) == SUBREG
12419 || GET_CODE (testreg) == ZERO_EXTRACT
12420 || GET_CODE (testreg) == STRICT_LOW_PART)
12421 testreg = XEXP (testreg, 0);
12423 if (MEM_P (testreg))
12424 mark_used_regs_combine (XEXP (testreg, 0));
12426 mark_used_regs_combine (SET_SRC (x));
12434 /* Recursively scan the operands of this expression. */
12437 const char *fmt = GET_RTX_FORMAT (code);
12439 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
12442 mark_used_regs_combine (XEXP (x, i));
12443 else if (fmt[i] == 'E')
12447 for (j = 0; j < XVECLEN (x, i); j++)
12448 mark_used_regs_combine (XVECEXP (x, i, j));
12454 /* Remove register number REGNO from the dead registers list of INSN.
12456 Return the note used to record the death, if there was one. */
12459 remove_death (unsigned int regno, rtx insn)
12461 rtx note = find_regno_note (insn, REG_DEAD, regno);
12464 remove_note (insn, note);
12469 /* For each register (hardware or pseudo) used within expression X, if its
12470 death is in an instruction with luid between FROM_LUID (inclusive) and
12471 TO_INSN (exclusive), put a REG_DEAD note for that register in the
12472 list headed by PNOTES.
12474 That said, don't move registers killed by maybe_kill_insn.
12476 This is done when X is being merged by combination into TO_INSN. These
12477 notes will then be distributed as needed. */
12480 move_deaths (rtx x, rtx maybe_kill_insn, int from_luid, rtx to_insn,
12485 enum rtx_code code = GET_CODE (x);
12489 unsigned int regno = REGNO (x);
12490 rtx where_dead = VEC_index (reg_stat_type, reg_stat, regno)->last_death;
12492 /* Don't move the register if it gets killed in between from and to. */
12493 if (maybe_kill_insn && reg_set_p (x, maybe_kill_insn)
12494 && ! reg_referenced_p (x, maybe_kill_insn))
12498 && BLOCK_FOR_INSN (where_dead) == BLOCK_FOR_INSN (to_insn)
12499 && DF_INSN_LUID (where_dead) >= from_luid
12500 && DF_INSN_LUID (where_dead) < DF_INSN_LUID (to_insn))
12502 rtx note = remove_death (regno, where_dead);
12504 /* It is possible for the call above to return 0. This can occur
12505 when last_death points to I2 or I1 that we combined with.
12506 In that case make a new note.
12508 We must also check for the case where X is a hard register
12509 and NOTE is a death note for a range of hard registers
12510 including X. In that case, we must put REG_DEAD notes for
12511 the remaining registers in place of NOTE. */
12513 if (note != 0 && regno < FIRST_PSEUDO_REGISTER
12514 && (GET_MODE_SIZE (GET_MODE (XEXP (note, 0)))
12515 > GET_MODE_SIZE (GET_MODE (x))))
12517 unsigned int deadregno = REGNO (XEXP (note, 0));
12518 unsigned int deadend = END_HARD_REGNO (XEXP (note, 0));
12519 unsigned int ourend = END_HARD_REGNO (x);
12522 for (i = deadregno; i < deadend; i++)
12523 if (i < regno || i >= ourend)
12524 add_reg_note (where_dead, REG_DEAD, regno_reg_rtx[i]);
12527 /* If we didn't find any note, or if we found a REG_DEAD note that
12528 covers only part of the given reg, and we have a multi-reg hard
12529 register, then to be safe we must check for REG_DEAD notes
12530 for each register other than the first. They could have
12531 their own REG_DEAD notes lying around. */
12532 else if ((note == 0
12534 && (GET_MODE_SIZE (GET_MODE (XEXP (note, 0)))
12535 < GET_MODE_SIZE (GET_MODE (x)))))
12536 && regno < FIRST_PSEUDO_REGISTER
12537 && hard_regno_nregs[regno][GET_MODE (x)] > 1)
12539 unsigned int ourend = END_HARD_REGNO (x);
12540 unsigned int i, offset;
12544 offset = hard_regno_nregs[regno][GET_MODE (XEXP (note, 0))];
12548 for (i = regno + offset; i < ourend; i++)
12549 move_deaths (regno_reg_rtx[i],
12550 maybe_kill_insn, from_luid, to_insn, &oldnotes);
12553 if (note != 0 && GET_MODE (XEXP (note, 0)) == GET_MODE (x))
12555 XEXP (note, 1) = *pnotes;
12559 *pnotes = alloc_reg_note (REG_DEAD, x, *pnotes);
12565 else if (GET_CODE (x) == SET)
12567 rtx dest = SET_DEST (x);
12569 move_deaths (SET_SRC (x), maybe_kill_insn, from_luid, to_insn, pnotes);
12571 /* In the case of a ZERO_EXTRACT, a STRICT_LOW_PART, or a SUBREG
12572 that accesses one word of a multi-word item, some
12573 piece of everything register in the expression is used by
12574 this insn, so remove any old death. */
12575 /* ??? So why do we test for equality of the sizes? */
12577 if (GET_CODE (dest) == ZERO_EXTRACT
12578 || GET_CODE (dest) == STRICT_LOW_PART
12579 || (GET_CODE (dest) == SUBREG
12580 && (((GET_MODE_SIZE (GET_MODE (dest))
12581 + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
12582 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (dest)))
12583 + UNITS_PER_WORD - 1) / UNITS_PER_WORD))))
12585 move_deaths (dest, maybe_kill_insn, from_luid, to_insn, pnotes);
12589 /* If this is some other SUBREG, we know it replaces the entire
12590 value, so use that as the destination. */
12591 if (GET_CODE (dest) == SUBREG)
12592 dest = SUBREG_REG (dest);
12594 /* If this is a MEM, adjust deaths of anything used in the address.
12595 For a REG (the only other possibility), the entire value is
12596 being replaced so the old value is not used in this insn. */
12599 move_deaths (XEXP (dest, 0), maybe_kill_insn, from_luid,
12604 else if (GET_CODE (x) == CLOBBER)
12607 len = GET_RTX_LENGTH (code);
12608 fmt = GET_RTX_FORMAT (code);
12610 for (i = 0; i < len; i++)
12615 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
12616 move_deaths (XVECEXP (x, i, j), maybe_kill_insn, from_luid,
12619 else if (fmt[i] == 'e')
12620 move_deaths (XEXP (x, i), maybe_kill_insn, from_luid, to_insn, pnotes);
12624 /* Return 1 if X is the target of a bit-field assignment in BODY, the
12625 pattern of an insn. X must be a REG. */
12628 reg_bitfield_target_p (rtx x, rtx body)
12632 if (GET_CODE (body) == SET)
12634 rtx dest = SET_DEST (body);
12636 unsigned int regno, tregno, endregno, endtregno;
12638 if (GET_CODE (dest) == ZERO_EXTRACT)
12639 target = XEXP (dest, 0);
12640 else if (GET_CODE (dest) == STRICT_LOW_PART)
12641 target = SUBREG_REG (XEXP (dest, 0));
12645 if (GET_CODE (target) == SUBREG)
12646 target = SUBREG_REG (target);
12648 if (!REG_P (target))
12651 tregno = REGNO (target), regno = REGNO (x);
12652 if (tregno >= FIRST_PSEUDO_REGISTER || regno >= FIRST_PSEUDO_REGISTER)
12653 return target == x;
12655 endtregno = end_hard_regno (GET_MODE (target), tregno);
12656 endregno = end_hard_regno (GET_MODE (x), regno);
12658 return endregno > tregno && regno < endtregno;
12661 else if (GET_CODE (body) == PARALLEL)
12662 for (i = XVECLEN (body, 0) - 1; i >= 0; i--)
12663 if (reg_bitfield_target_p (x, XVECEXP (body, 0, i)))
12669 /* Return the next insn after INSN that is neither a NOTE nor a
12670 DEBUG_INSN. This routine does not look inside SEQUENCEs. */
12673 next_nonnote_nondebug_insn (rtx insn)
12677 insn = NEXT_INSN (insn);
12682 if (DEBUG_INSN_P (insn))
12692 /* Given a chain of REG_NOTES originally from FROM_INSN, try to place them
12693 as appropriate. I3 and I2 are the insns resulting from the combination
12694 insns including FROM (I2 may be zero).
12696 ELIM_I2 and ELIM_I1 are either zero or registers that we know will
12697 not need REG_DEAD notes because they are being substituted for. This
12698 saves searching in the most common cases.
12700 Each note in the list is either ignored or placed on some insns, depending
12701 on the type of note. */
12704 distribute_notes (rtx notes, rtx from_insn, rtx i3, rtx i2, rtx elim_i2,
12707 rtx note, next_note;
12710 for (note = notes; note; note = next_note)
12712 rtx place = 0, place2 = 0;
12714 next_note = XEXP (note, 1);
12715 switch (REG_NOTE_KIND (note))
12719 /* Doesn't matter much where we put this, as long as it's somewhere.
12720 It is preferable to keep these notes on branches, which is most
12721 likely to be i3. */
12725 case REG_VALUE_PROFILE:
12726 /* Just get rid of this note, as it is unused later anyway. */
12729 case REG_NON_LOCAL_GOTO:
12734 gcc_assert (i2 && JUMP_P (i2));
12739 case REG_EH_REGION:
12740 /* These notes must remain with the call or trapping instruction. */
12743 else if (i2 && CALL_P (i2))
12747 gcc_assert (flag_non_call_exceptions);
12748 if (may_trap_p (i3))
12750 else if (i2 && may_trap_p (i2))
12752 /* ??? Otherwise assume we've combined things such that we
12753 can now prove that the instructions can't trap. Drop the
12754 note in this case. */
12760 /* These notes must remain with the call. It should not be
12761 possible for both I2 and I3 to be a call. */
12766 gcc_assert (i2 && CALL_P (i2));
12772 /* Any clobbers for i3 may still exist, and so we must process
12773 REG_UNUSED notes from that insn.
12775 Any clobbers from i2 or i1 can only exist if they were added by
12776 recog_for_combine. In that case, recog_for_combine created the
12777 necessary REG_UNUSED notes. Trying to keep any original
12778 REG_UNUSED notes from these insns can cause incorrect output
12779 if it is for the same register as the original i3 dest.
12780 In that case, we will notice that the register is set in i3,
12781 and then add a REG_UNUSED note for the destination of i3, which
12782 is wrong. However, it is possible to have REG_UNUSED notes from
12783 i2 or i1 for register which were both used and clobbered, so
12784 we keep notes from i2 or i1 if they will turn into REG_DEAD
12787 /* If this register is set or clobbered in I3, put the note there
12788 unless there is one already. */
12789 if (reg_set_p (XEXP (note, 0), PATTERN (i3)))
12791 if (from_insn != i3)
12794 if (! (REG_P (XEXP (note, 0))
12795 ? find_regno_note (i3, REG_UNUSED, REGNO (XEXP (note, 0)))
12796 : find_reg_note (i3, REG_UNUSED, XEXP (note, 0))))
12799 /* Otherwise, if this register is used by I3, then this register
12800 now dies here, so we must put a REG_DEAD note here unless there
12802 else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3))
12803 && ! (REG_P (XEXP (note, 0))
12804 ? find_regno_note (i3, REG_DEAD,
12805 REGNO (XEXP (note, 0)))
12806 : find_reg_note (i3, REG_DEAD, XEXP (note, 0))))
12808 PUT_REG_NOTE_KIND (note, REG_DEAD);
12816 /* These notes say something about results of an insn. We can
12817 only support them if they used to be on I3 in which case they
12818 remain on I3. Otherwise they are ignored.
12820 If the note refers to an expression that is not a constant, we
12821 must also ignore the note since we cannot tell whether the
12822 equivalence is still true. It might be possible to do
12823 slightly better than this (we only have a problem if I2DEST
12824 or I1DEST is present in the expression), but it doesn't
12825 seem worth the trouble. */
12827 if (from_insn == i3
12828 && (XEXP (note, 0) == 0 || CONSTANT_P (XEXP (note, 0))))
12833 /* These notes say something about how a register is used. They must
12834 be present on any use of the register in I2 or I3. */
12835 if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3)))
12838 if (i2 && reg_mentioned_p (XEXP (note, 0), PATTERN (i2)))
12847 case REG_LABEL_TARGET:
12848 case REG_LABEL_OPERAND:
12849 /* This can show up in several ways -- either directly in the
12850 pattern, or hidden off in the constant pool with (or without?)
12851 a REG_EQUAL note. */
12852 /* ??? Ignore the without-reg_equal-note problem for now. */
12853 if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3))
12854 || ((tem = find_reg_note (i3, REG_EQUAL, NULL_RTX))
12855 && GET_CODE (XEXP (tem, 0)) == LABEL_REF
12856 && XEXP (XEXP (tem, 0), 0) == XEXP (note, 0)))
12860 && (reg_mentioned_p (XEXP (note, 0), PATTERN (i2))
12861 || ((tem = find_reg_note (i2, REG_EQUAL, NULL_RTX))
12862 && GET_CODE (XEXP (tem, 0)) == LABEL_REF
12863 && XEXP (XEXP (tem, 0), 0) == XEXP (note, 0))))
12871 /* For REG_LABEL_TARGET on a JUMP_P, we prefer to put the note
12872 as a JUMP_LABEL or decrement LABEL_NUSES if it's already
12874 if (place && JUMP_P (place)
12875 && REG_NOTE_KIND (note) == REG_LABEL_TARGET
12876 && (JUMP_LABEL (place) == NULL
12877 || JUMP_LABEL (place) == XEXP (note, 0)))
12879 rtx label = JUMP_LABEL (place);
12882 JUMP_LABEL (place) = XEXP (note, 0);
12883 else if (LABEL_P (label))
12884 LABEL_NUSES (label)--;
12887 if (place2 && JUMP_P (place2)
12888 && REG_NOTE_KIND (note) == REG_LABEL_TARGET
12889 && (JUMP_LABEL (place2) == NULL
12890 || JUMP_LABEL (place2) == XEXP (note, 0)))
12892 rtx label = JUMP_LABEL (place2);
12895 JUMP_LABEL (place2) = XEXP (note, 0);
12896 else if (LABEL_P (label))
12897 LABEL_NUSES (label)--;
12903 /* This note says something about the value of a register prior
12904 to the execution of an insn. It is too much trouble to see
12905 if the note is still correct in all situations. It is better
12906 to simply delete it. */
12910 /* If we replaced the right hand side of FROM_INSN with a
12911 REG_EQUAL note, the original use of the dying register
12912 will not have been combined into I3 and I2. In such cases,
12913 FROM_INSN is guaranteed to be the first of the combined
12914 instructions, so we simply need to search back before
12915 FROM_INSN for the previous use or set of this register,
12916 then alter the notes there appropriately.
12918 If the register is used as an input in I3, it dies there.
12919 Similarly for I2, if it is nonzero and adjacent to I3.
12921 If the register is not used as an input in either I3 or I2
12922 and it is not one of the registers we were supposed to eliminate,
12923 there are two possibilities. We might have a non-adjacent I2
12924 or we might have somehow eliminated an additional register
12925 from a computation. For example, we might have had A & B where
12926 we discover that B will always be zero. In this case we will
12927 eliminate the reference to A.
12929 In both cases, we must search to see if we can find a previous
12930 use of A and put the death note there. */
12933 && from_insn == i2mod
12934 && !reg_overlap_mentioned_p (XEXP (note, 0), i2mod_new_rhs))
12939 && CALL_P (from_insn)
12940 && find_reg_fusage (from_insn, USE, XEXP (note, 0)))
12942 else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3)))
12944 else if (i2 != 0 && next_nonnote_nondebug_insn (i2) == i3
12945 && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
12947 else if ((rtx_equal_p (XEXP (note, 0), elim_i2)
12949 && reg_overlap_mentioned_p (XEXP (note, 0),
12951 || rtx_equal_p (XEXP (note, 0), elim_i1))
12958 basic_block bb = this_basic_block;
12960 for (tem = PREV_INSN (tem); place == 0; tem = PREV_INSN (tem))
12962 if (!NONDEBUG_INSN_P (tem))
12964 if (tem == BB_HEAD (bb))
12969 /* If the register is being set at TEM, see if that is all
12970 TEM is doing. If so, delete TEM. Otherwise, make this
12971 into a REG_UNUSED note instead. Don't delete sets to
12972 global register vars. */
12973 if ((REGNO (XEXP (note, 0)) >= FIRST_PSEUDO_REGISTER
12974 || !global_regs[REGNO (XEXP (note, 0))])
12975 && reg_set_p (XEXP (note, 0), PATTERN (tem)))
12977 rtx set = single_set (tem);
12978 rtx inner_dest = 0;
12980 rtx cc0_setter = NULL_RTX;
12984 for (inner_dest = SET_DEST (set);
12985 (GET_CODE (inner_dest) == STRICT_LOW_PART
12986 || GET_CODE (inner_dest) == SUBREG
12987 || GET_CODE (inner_dest) == ZERO_EXTRACT);
12988 inner_dest = XEXP (inner_dest, 0))
12991 /* Verify that it was the set, and not a clobber that
12992 modified the register.
12994 CC0 targets must be careful to maintain setter/user
12995 pairs. If we cannot delete the setter due to side
12996 effects, mark the user with an UNUSED note instead
12999 if (set != 0 && ! side_effects_p (SET_SRC (set))
13000 && rtx_equal_p (XEXP (note, 0), inner_dest)
13002 && (! reg_mentioned_p (cc0_rtx, SET_SRC (set))
13003 || ((cc0_setter = prev_cc0_setter (tem)) != NULL
13004 && sets_cc0_p (PATTERN (cc0_setter)) > 0))
13008 /* Move the notes and links of TEM elsewhere.
13009 This might delete other dead insns recursively.
13010 First set the pattern to something that won't use
13012 rtx old_notes = REG_NOTES (tem);
13014 PATTERN (tem) = pc_rtx;
13015 REG_NOTES (tem) = NULL;
13017 distribute_notes (old_notes, tem, tem, NULL_RTX,
13018 NULL_RTX, NULL_RTX);
13019 distribute_links (LOG_LINKS (tem));
13021 SET_INSN_DELETED (tem);
13026 /* Delete the setter too. */
13029 PATTERN (cc0_setter) = pc_rtx;
13030 old_notes = REG_NOTES (cc0_setter);
13031 REG_NOTES (cc0_setter) = NULL;
13033 distribute_notes (old_notes, cc0_setter,
13034 cc0_setter, NULL_RTX,
13035 NULL_RTX, NULL_RTX);
13036 distribute_links (LOG_LINKS (cc0_setter));
13038 SET_INSN_DELETED (cc0_setter);
13039 if (cc0_setter == i2)
13046 PUT_REG_NOTE_KIND (note, REG_UNUSED);
13048 /* If there isn't already a REG_UNUSED note, put one
13049 here. Do not place a REG_DEAD note, even if
13050 the register is also used here; that would not
13051 match the algorithm used in lifetime analysis
13052 and can cause the consistency check in the
13053 scheduler to fail. */
13054 if (! find_regno_note (tem, REG_UNUSED,
13055 REGNO (XEXP (note, 0))))
13060 else if (reg_referenced_p (XEXP (note, 0), PATTERN (tem))
13062 && find_reg_fusage (tem, USE, XEXP (note, 0))))
13066 /* If we are doing a 3->2 combination, and we have a
13067 register which formerly died in i3 and was not used
13068 by i2, which now no longer dies in i3 and is used in
13069 i2 but does not die in i2, and place is between i2
13070 and i3, then we may need to move a link from place to
13072 if (i2 && DF_INSN_LUID (place) > DF_INSN_LUID (i2)
13074 && DF_INSN_LUID (from_insn) > DF_INSN_LUID (i2)
13075 && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
13077 rtx links = LOG_LINKS (place);
13078 LOG_LINKS (place) = 0;
13079 distribute_links (links);
13084 if (tem == BB_HEAD (bb))
13090 /* If the register is set or already dead at PLACE, we needn't do
13091 anything with this note if it is still a REG_DEAD note.
13092 We check here if it is set at all, not if is it totally replaced,
13093 which is what `dead_or_set_p' checks, so also check for it being
13096 if (place && REG_NOTE_KIND (note) == REG_DEAD)
13098 unsigned int regno = REGNO (XEXP (note, 0));
13099 reg_stat_type *rsp = VEC_index (reg_stat_type, reg_stat, regno);
13101 if (dead_or_set_p (place, XEXP (note, 0))
13102 || reg_bitfield_target_p (XEXP (note, 0), PATTERN (place)))
13104 /* Unless the register previously died in PLACE, clear
13105 last_death. [I no longer understand why this is
13107 if (rsp->last_death != place)
13108 rsp->last_death = 0;
13112 rsp->last_death = place;
13114 /* If this is a death note for a hard reg that is occupying
13115 multiple registers, ensure that we are still using all
13116 parts of the object. If we find a piece of the object
13117 that is unused, we must arrange for an appropriate REG_DEAD
13118 note to be added for it. However, we can't just emit a USE
13119 and tag the note to it, since the register might actually
13120 be dead; so we recourse, and the recursive call then finds
13121 the previous insn that used this register. */
13123 if (place && regno < FIRST_PSEUDO_REGISTER
13124 && hard_regno_nregs[regno][GET_MODE (XEXP (note, 0))] > 1)
13126 unsigned int endregno = END_HARD_REGNO (XEXP (note, 0));
13130 for (i = regno; i < endregno; i++)
13131 if ((! refers_to_regno_p (i, i + 1, PATTERN (place), 0)
13132 && ! find_regno_fusage (place, USE, i))
13133 || dead_or_set_regno_p (place, i))
13138 /* Put only REG_DEAD notes for pieces that are
13139 not already dead or set. */
13141 for (i = regno; i < endregno;
13142 i += hard_regno_nregs[i][reg_raw_mode[i]])
13144 rtx piece = regno_reg_rtx[i];
13145 basic_block bb = this_basic_block;
13147 if (! dead_or_set_p (place, piece)
13148 && ! reg_bitfield_target_p (piece,
13151 rtx new_note = alloc_reg_note (REG_DEAD, piece,
13154 distribute_notes (new_note, place, place,
13155 NULL_RTX, NULL_RTX, NULL_RTX);
13157 else if (! refers_to_regno_p (i, i + 1,
13158 PATTERN (place), 0)
13159 && ! find_regno_fusage (place, USE, i))
13160 for (tem = PREV_INSN (place); ;
13161 tem = PREV_INSN (tem))
13163 if (!NONDEBUG_INSN_P (tem))
13165 if (tem == BB_HEAD (bb))
13169 if (dead_or_set_p (tem, piece)
13170 || reg_bitfield_target_p (piece,
13173 add_reg_note (tem, REG_UNUSED, piece);
13187 /* Any other notes should not be present at this point in the
13189 gcc_unreachable ();
13194 XEXP (note, 1) = REG_NOTES (place);
13195 REG_NOTES (place) = note;
13199 add_reg_note (place2, REG_NOTE_KIND (note), XEXP (note, 0));
13203 /* Similarly to above, distribute the LOG_LINKS that used to be present on
13204 I3, I2, and I1 to new locations. This is also called to add a link
13205 pointing at I3 when I3's destination is changed. */
13208 distribute_links (rtx links)
13210 rtx link, next_link;
13212 for (link = links; link; link = next_link)
13218 next_link = XEXP (link, 1);
13220 /* If the insn that this link points to is a NOTE or isn't a single
13221 set, ignore it. In the latter case, it isn't clear what we
13222 can do other than ignore the link, since we can't tell which
13223 register it was for. Such links wouldn't be used by combine
13226 It is not possible for the destination of the target of the link to
13227 have been changed by combine. The only potential of this is if we
13228 replace I3, I2, and I1 by I3 and I2. But in that case the
13229 destination of I2 also remains unchanged. */
13231 if (NOTE_P (XEXP (link, 0))
13232 || (set = single_set (XEXP (link, 0))) == 0)
13235 reg = SET_DEST (set);
13236 while (GET_CODE (reg) == SUBREG || GET_CODE (reg) == ZERO_EXTRACT
13237 || GET_CODE (reg) == STRICT_LOW_PART)
13238 reg = XEXP (reg, 0);
13240 /* A LOG_LINK is defined as being placed on the first insn that uses
13241 a register and points to the insn that sets the register. Start
13242 searching at the next insn after the target of the link and stop
13243 when we reach a set of the register or the end of the basic block.
13245 Note that this correctly handles the link that used to point from
13246 I3 to I2. Also note that not much searching is typically done here
13247 since most links don't point very far away. */
13249 for (insn = NEXT_INSN (XEXP (link, 0));
13250 (insn && (this_basic_block->next_bb == EXIT_BLOCK_PTR
13251 || BB_HEAD (this_basic_block->next_bb) != insn));
13252 insn = NEXT_INSN (insn))
13253 if (DEBUG_INSN_P (insn))
13255 else if (INSN_P (insn) && reg_overlap_mentioned_p (reg, PATTERN (insn)))
13257 if (reg_referenced_p (reg, PATTERN (insn)))
13261 else if (CALL_P (insn)
13262 && find_reg_fusage (insn, USE, reg))
13267 else if (INSN_P (insn) && reg_set_p (reg, insn))
13270 /* If we found a place to put the link, place it there unless there
13271 is already a link to the same insn as LINK at that point. */
13277 for (link2 = LOG_LINKS (place); link2; link2 = XEXP (link2, 1))
13278 if (XEXP (link2, 0) == XEXP (link, 0))
13283 XEXP (link, 1) = LOG_LINKS (place);
13284 LOG_LINKS (place) = link;
13286 /* Set added_links_insn to the earliest insn we added a
13288 if (added_links_insn == 0
13289 || DF_INSN_LUID (added_links_insn) > DF_INSN_LUID (place))
13290 added_links_insn = place;
13296 /* Subroutine of unmentioned_reg_p and callback from for_each_rtx.
13297 Check whether the expression pointer to by LOC is a register or
13298 memory, and if so return 1 if it isn't mentioned in the rtx EXPR.
13299 Otherwise return zero. */
13302 unmentioned_reg_p_1 (rtx *loc, void *expr)
13307 && (REG_P (x) || MEM_P (x))
13308 && ! reg_mentioned_p (x, (rtx) expr))
13313 /* Check for any register or memory mentioned in EQUIV that is not
13314 mentioned in EXPR. This is used to restrict EQUIV to "specializations"
13315 of EXPR where some registers may have been replaced by constants. */
13318 unmentioned_reg_p (rtx equiv, rtx expr)
13320 return for_each_rtx (&equiv, unmentioned_reg_p_1, expr);
13324 dump_combine_stats (FILE *file)
13328 ";; Combiner statistics: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n\n",
13329 combine_attempts, combine_merges, combine_extras, combine_successes);
13333 dump_combine_total_stats (FILE *file)
13337 "\n;; Combiner totals: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n",
13338 total_attempts, total_merges, total_extras, total_successes);
13342 gate_handle_combine (void)
13344 return (optimize > 0);
13347 /* Try combining insns through substitution. */
13348 static unsigned int
13349 rest_of_handle_combine (void)
13351 int rebuild_jump_labels_after_combine;
13353 df_set_flags (DF_LR_RUN_DCE + DF_DEFER_INSN_RESCAN);
13354 df_note_add_problem ();
13357 regstat_init_n_sets_and_refs ();
13359 rebuild_jump_labels_after_combine
13360 = combine_instructions (get_insns (), max_reg_num ());
13362 /* Combining insns may have turned an indirect jump into a
13363 direct jump. Rebuild the JUMP_LABEL fields of jumping
13365 if (rebuild_jump_labels_after_combine)
13367 timevar_push (TV_JUMP);
13368 rebuild_jump_labels (get_insns ());
13370 timevar_pop (TV_JUMP);
13373 regstat_free_n_sets_and_refs ();
13377 struct rtl_opt_pass pass_combine =
13381 "combine", /* name */
13382 gate_handle_combine, /* gate */
13383 rest_of_handle_combine, /* execute */
13386 0, /* static_pass_number */
13387 TV_COMBINE, /* tv_id */
13388 PROP_cfglayout, /* properties_required */
13389 0, /* properties_provided */
13390 0, /* properties_destroyed */
13391 0, /* todo_flags_start */
13393 TODO_df_finish | TODO_verify_rtl_sharing |
13394 TODO_ggc_collect, /* todo_flags_finish */
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