1 /* Optimize by combining instructions for GNU compiler.
2 Copyright (C) 1987, 1988, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010
4 Free Software Foundation, Inc.
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify it under
9 the terms of the GNU General Public License as published by the Free
10 Software Foundation; either version 3, or (at your option) any later
13 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
14 WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
22 /* This module is essentially the "combiner" phase of the U. of Arizona
23 Portable Optimizer, but redone to work on our list-structured
24 representation for RTL instead of their string representation.
26 The LOG_LINKS of each insn identify the most recent assignment
27 to each REG used in the insn. It is a list of previous insns,
28 each of which contains a SET for a REG that is used in this insn
29 and not used or set in between. LOG_LINKs never cross basic blocks.
30 They were set up by the preceding pass (lifetime analysis).
32 We try to combine each pair of insns joined by a logical link.
33 We also try to combine triples of insns A, B and C when
34 C has a link back to B and B has a link back to A.
36 LOG_LINKS does not have links for use of the CC0. They don't
37 need to, because the insn that sets the CC0 is always immediately
38 before the insn that tests it. So we always regard a branch
39 insn as having a logical link to the preceding insn. The same is true
40 for an insn explicitly using CC0.
42 We check (with use_crosses_set_p) to avoid combining in such a way
43 as to move a computation to a place where its value would be different.
45 Combination is done by mathematically substituting the previous
46 insn(s) values for the regs they set into the expressions in
47 the later insns that refer to these regs. If the result is a valid insn
48 for our target machine, according to the machine description,
49 we install it, delete the earlier insns, and update the data flow
50 information (LOG_LINKS and REG_NOTES) for what we did.
52 There are a few exceptions where the dataflow information isn't
53 completely updated (however this is only a local issue since it is
54 regenerated before the next pass that uses it):
56 - reg_live_length is not updated
57 - reg_n_refs is not adjusted in the rare case when a register is
58 no longer required in a computation
59 - there are extremely rare cases (see distribute_notes) when a
61 - a LOG_LINKS entry that refers to an insn with multiple SETs may be
62 removed because there is no way to know which register it was
65 To simplify substitution, we combine only when the earlier insn(s)
66 consist of only a single assignment. To simplify updating afterward,
67 we never combine when a subroutine call appears in the middle.
69 Since we do not represent assignments to CC0 explicitly except when that
70 is all an insn does, there is no LOG_LINKS entry in an insn that uses
71 the condition code for the insn that set the condition code.
72 Fortunately, these two insns must be consecutive.
73 Therefore, every JUMP_INSN is taken to have an implicit logical link
74 to the preceding insn. This is not quite right, since non-jumps can
75 also use the condition code; but in practice such insns would not
80 #include "coretypes.h"
87 #include "hard-reg-set.h"
88 #include "basic-block.h"
89 #include "insn-config.h"
91 /* Include expr.h after insn-config.h so we get HAVE_conditional_move. */
93 #include "insn-attr.h"
98 #include "insn-codes.h"
99 #include "rtlhooks-def.h"
100 /* Include output.h for dump_file. */
104 #include "tree-pass.h"
108 /* Number of attempts to combine instructions in this function. */
110 static int combine_attempts;
112 /* Number of attempts that got as far as substitution in this function. */
114 static int combine_merges;
116 /* Number of instructions combined with added SETs in this function. */
118 static int combine_extras;
120 /* Number of instructions combined in this function. */
122 static int combine_successes;
124 /* Totals over entire compilation. */
126 static int total_attempts, total_merges, total_extras, total_successes;
128 /* combine_instructions may try to replace the right hand side of the
129 second instruction with the value of an associated REG_EQUAL note
130 before throwing it at try_combine. That is problematic when there
131 is a REG_DEAD note for a register used in the old right hand side
132 and can cause distribute_notes to do wrong things. This is the
133 second instruction if it has been so modified, null otherwise. */
137 /* When I2MOD is nonnull, this is a copy of the old right hand side. */
139 static rtx i2mod_old_rhs;
141 /* When I2MOD is nonnull, this is a copy of the new right hand side. */
143 static rtx i2mod_new_rhs;
145 typedef struct reg_stat_struct {
146 /* Record last point of death of (hard or pseudo) register n. */
149 /* Record last point of modification of (hard or pseudo) register n. */
152 /* The next group of fields allows the recording of the last value assigned
153 to (hard or pseudo) register n. We use this information to see if an
154 operation being processed is redundant given a prior operation performed
155 on the register. For example, an `and' with a constant is redundant if
156 all the zero bits are already known to be turned off.
158 We use an approach similar to that used by cse, but change it in the
161 (1) We do not want to reinitialize at each label.
162 (2) It is useful, but not critical, to know the actual value assigned
163 to a register. Often just its form is helpful.
165 Therefore, we maintain the following fields:
167 last_set_value the last value assigned
168 last_set_label records the value of label_tick when the
169 register was assigned
170 last_set_table_tick records the value of label_tick when a
171 value using the register is assigned
172 last_set_invalid set to nonzero when it is not valid
173 to use the value of this register in some
176 To understand the usage of these tables, it is important to understand
177 the distinction between the value in last_set_value being valid and
178 the register being validly contained in some other expression in the
181 (The next two parameters are out of date).
183 reg_stat[i].last_set_value is valid if it is nonzero, and either
184 reg_n_sets[i] is 1 or reg_stat[i].last_set_label == label_tick.
186 Register I may validly appear in any expression returned for the value
187 of another register if reg_n_sets[i] is 1. It may also appear in the
188 value for register J if reg_stat[j].last_set_invalid is zero, or
189 reg_stat[i].last_set_label < reg_stat[j].last_set_label.
191 If an expression is found in the table containing a register which may
192 not validly appear in an expression, the register is replaced by
193 something that won't match, (clobber (const_int 0)). */
195 /* Record last value assigned to (hard or pseudo) register n. */
199 /* Record the value of label_tick when an expression involving register n
200 is placed in last_set_value. */
202 int last_set_table_tick;
204 /* Record the value of label_tick when the value for register n is placed in
209 /* These fields are maintained in parallel with last_set_value and are
210 used to store the mode in which the register was last set, the bits
211 that were known to be zero when it was last set, and the number of
212 sign bits copies it was known to have when it was last set. */
214 unsigned HOST_WIDE_INT last_set_nonzero_bits;
215 char last_set_sign_bit_copies;
216 ENUM_BITFIELD(machine_mode) last_set_mode : 8;
218 /* Set nonzero if references to register n in expressions should not be
219 used. last_set_invalid is set nonzero when this register is being
220 assigned to and last_set_table_tick == label_tick. */
222 char last_set_invalid;
224 /* Some registers that are set more than once and used in more than one
225 basic block are nevertheless always set in similar ways. For example,
226 a QImode register may be loaded from memory in two places on a machine
227 where byte loads zero extend.
229 We record in the following fields if a register has some leading bits
230 that are always equal to the sign bit, and what we know about the
231 nonzero bits of a register, specifically which bits are known to be
234 If an entry is zero, it means that we don't know anything special. */
236 unsigned char sign_bit_copies;
238 unsigned HOST_WIDE_INT nonzero_bits;
240 /* Record the value of the label_tick when the last truncation
241 happened. The field truncated_to_mode is only valid if
242 truncation_label == label_tick. */
244 int truncation_label;
246 /* Record the last truncation seen for this register. If truncation
247 is not a nop to this mode we might be able to save an explicit
248 truncation if we know that value already contains a truncated
251 ENUM_BITFIELD(machine_mode) truncated_to_mode : 8;
254 DEF_VEC_O(reg_stat_type);
255 DEF_VEC_ALLOC_O(reg_stat_type,heap);
257 static VEC(reg_stat_type,heap) *reg_stat;
259 /* Record the luid of the last insn that invalidated memory
260 (anything that writes memory, and subroutine calls, but not pushes). */
262 static int mem_last_set;
264 /* Record the luid of the last CALL_INSN
265 so we can tell whether a potential combination crosses any calls. */
267 static int last_call_luid;
269 /* When `subst' is called, this is the insn that is being modified
270 (by combining in a previous insn). The PATTERN of this insn
271 is still the old pattern partially modified and it should not be
272 looked at, but this may be used to examine the successors of the insn
273 to judge whether a simplification is valid. */
275 static rtx subst_insn;
277 /* This is the lowest LUID that `subst' is currently dealing with.
278 get_last_value will not return a value if the register was set at or
279 after this LUID. If not for this mechanism, we could get confused if
280 I2 or I1 in try_combine were an insn that used the old value of a register
281 to obtain a new value. In that case, we might erroneously get the
282 new value of the register when we wanted the old one. */
284 static int subst_low_luid;
286 /* This contains any hard registers that are used in newpat; reg_dead_at_p
287 must consider all these registers to be always live. */
289 static HARD_REG_SET newpat_used_regs;
291 /* This is an insn to which a LOG_LINKS entry has been added. If this
292 insn is the earlier than I2 or I3, combine should rescan starting at
295 static rtx added_links_insn;
297 /* Basic block in which we are performing combines. */
298 static basic_block this_basic_block;
299 static bool optimize_this_for_speed_p;
302 /* Length of the currently allocated uid_insn_cost array. */
304 static int max_uid_known;
306 /* The following array records the insn_rtx_cost for every insn
307 in the instruction stream. */
309 static int *uid_insn_cost;
311 /* The following array records the LOG_LINKS for every insn in the
312 instruction stream as an INSN_LIST rtx. */
314 static rtx *uid_log_links;
316 #define INSN_COST(INSN) (uid_insn_cost[INSN_UID (INSN)])
317 #define LOG_LINKS(INSN) (uid_log_links[INSN_UID (INSN)])
319 /* Incremented for each basic block. */
321 static int label_tick;
323 /* Reset to label_tick for each extended basic block in scanning order. */
325 static int label_tick_ebb_start;
327 /* Mode used to compute significance in reg_stat[].nonzero_bits. It is the
328 largest integer mode that can fit in HOST_BITS_PER_WIDE_INT. */
330 static enum machine_mode nonzero_bits_mode;
332 /* Nonzero when reg_stat[].nonzero_bits and reg_stat[].sign_bit_copies can
333 be safely used. It is zero while computing them and after combine has
334 completed. This former test prevents propagating values based on
335 previously set values, which can be incorrect if a variable is modified
338 static int nonzero_sign_valid;
341 /* Record one modification to rtl structure
342 to be undone by storing old_contents into *where. */
344 enum undo_kind { UNDO_RTX, UNDO_INT, UNDO_MODE };
350 union { rtx r; int i; enum machine_mode m; } old_contents;
351 union { rtx *r; int *i; } where;
354 /* Record a bunch of changes to be undone, up to MAX_UNDO of them.
355 num_undo says how many are currently recorded.
357 other_insn is nonzero if we have modified some other insn in the process
358 of working on subst_insn. It must be verified too. */
367 static struct undobuf undobuf;
369 /* Number of times the pseudo being substituted for
370 was found and replaced. */
372 static int n_occurrences;
374 static rtx reg_nonzero_bits_for_combine (const_rtx, enum machine_mode, const_rtx,
376 unsigned HOST_WIDE_INT,
377 unsigned HOST_WIDE_INT *);
378 static rtx reg_num_sign_bit_copies_for_combine (const_rtx, enum machine_mode, const_rtx,
380 unsigned int, unsigned int *);
381 static void do_SUBST (rtx *, rtx);
382 static void do_SUBST_INT (int *, int);
383 static void init_reg_last (void);
384 static void setup_incoming_promotions (rtx);
385 static void set_nonzero_bits_and_sign_copies (rtx, const_rtx, void *);
386 static int cant_combine_insn_p (rtx);
387 static int can_combine_p (rtx, rtx, rtx, rtx, rtx *, rtx *);
388 static int combinable_i3pat (rtx, rtx *, rtx, rtx, int, rtx *);
389 static int contains_muldiv (rtx);
390 static rtx try_combine (rtx, rtx, rtx, int *);
391 static void undo_all (void);
392 static void undo_commit (void);
393 static rtx *find_split_point (rtx *, rtx, bool);
394 static rtx subst (rtx, rtx, rtx, int, int);
395 static rtx combine_simplify_rtx (rtx, enum machine_mode, int);
396 static rtx simplify_if_then_else (rtx);
397 static rtx simplify_set (rtx);
398 static rtx simplify_logical (rtx);
399 static rtx expand_compound_operation (rtx);
400 static const_rtx expand_field_assignment (const_rtx);
401 static rtx make_extraction (enum machine_mode, rtx, HOST_WIDE_INT,
402 rtx, unsigned HOST_WIDE_INT, int, int, int);
403 static rtx extract_left_shift (rtx, int);
404 static rtx make_compound_operation (rtx, enum rtx_code);
405 static int get_pos_from_mask (unsigned HOST_WIDE_INT,
406 unsigned HOST_WIDE_INT *);
407 static rtx canon_reg_for_combine (rtx, rtx);
408 static rtx force_to_mode (rtx, enum machine_mode,
409 unsigned HOST_WIDE_INT, int);
410 static rtx if_then_else_cond (rtx, rtx *, rtx *);
411 static rtx known_cond (rtx, enum rtx_code, rtx, rtx);
412 static int rtx_equal_for_field_assignment_p (rtx, rtx);
413 static rtx make_field_assignment (rtx);
414 static rtx apply_distributive_law (rtx);
415 static rtx distribute_and_simplify_rtx (rtx, int);
416 static rtx simplify_and_const_int_1 (enum machine_mode, rtx,
417 unsigned HOST_WIDE_INT);
418 static rtx simplify_and_const_int (rtx, enum machine_mode, rtx,
419 unsigned HOST_WIDE_INT);
420 static int merge_outer_ops (enum rtx_code *, HOST_WIDE_INT *, enum rtx_code,
421 HOST_WIDE_INT, enum machine_mode, int *);
422 static rtx simplify_shift_const_1 (enum rtx_code, enum machine_mode, rtx, int);
423 static rtx simplify_shift_const (rtx, enum rtx_code, enum machine_mode, rtx,
425 static int recog_for_combine (rtx *, rtx, rtx *);
426 static rtx gen_lowpart_for_combine (enum machine_mode, rtx);
427 static enum rtx_code simplify_comparison (enum rtx_code, rtx *, rtx *);
428 static void update_table_tick (rtx);
429 static void record_value_for_reg (rtx, rtx, rtx);
430 static void check_promoted_subreg (rtx, rtx);
431 static void record_dead_and_set_regs_1 (rtx, const_rtx, void *);
432 static void record_dead_and_set_regs (rtx);
433 static int get_last_value_validate (rtx *, rtx, int, int);
434 static rtx get_last_value (const_rtx);
435 static int use_crosses_set_p (const_rtx, int);
436 static void reg_dead_at_p_1 (rtx, const_rtx, void *);
437 static int reg_dead_at_p (rtx, rtx);
438 static void move_deaths (rtx, rtx, int, rtx, rtx *);
439 static int reg_bitfield_target_p (rtx, rtx);
440 static void distribute_notes (rtx, rtx, rtx, rtx, rtx, rtx);
441 static void distribute_links (rtx);
442 static void mark_used_regs_combine (rtx);
443 static void record_promoted_value (rtx, rtx);
444 static int unmentioned_reg_p_1 (rtx *, void *);
445 static bool unmentioned_reg_p (rtx, rtx);
446 static int record_truncated_value (rtx *, void *);
447 static void record_truncated_values (rtx *, void *);
448 static bool reg_truncated_to_mode (enum machine_mode, const_rtx);
449 static rtx gen_lowpart_or_truncate (enum machine_mode, rtx);
452 /* It is not safe to use ordinary gen_lowpart in combine.
453 See comments in gen_lowpart_for_combine. */
454 #undef RTL_HOOKS_GEN_LOWPART
455 #define RTL_HOOKS_GEN_LOWPART gen_lowpart_for_combine
457 /* Our implementation of gen_lowpart never emits a new pseudo. */
458 #undef RTL_HOOKS_GEN_LOWPART_NO_EMIT
459 #define RTL_HOOKS_GEN_LOWPART_NO_EMIT gen_lowpart_for_combine
461 #undef RTL_HOOKS_REG_NONZERO_REG_BITS
462 #define RTL_HOOKS_REG_NONZERO_REG_BITS reg_nonzero_bits_for_combine
464 #undef RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES
465 #define RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES reg_num_sign_bit_copies_for_combine
467 #undef RTL_HOOKS_REG_TRUNCATED_TO_MODE
468 #define RTL_HOOKS_REG_TRUNCATED_TO_MODE reg_truncated_to_mode
470 static const struct rtl_hooks combine_rtl_hooks = RTL_HOOKS_INITIALIZER;
473 /* Try to split PATTERN found in INSN. This returns NULL_RTX if
474 PATTERN can not be split. Otherwise, it returns an insn sequence.
475 This is a wrapper around split_insns which ensures that the
476 reg_stat vector is made larger if the splitter creates a new
480 combine_split_insns (rtx pattern, rtx insn)
485 ret = split_insns (pattern, insn);
486 nregs = max_reg_num ();
487 if (nregs > VEC_length (reg_stat_type, reg_stat))
488 VEC_safe_grow_cleared (reg_stat_type, heap, reg_stat, nregs);
492 /* This is used by find_single_use to locate an rtx in LOC that
493 contains exactly one use of DEST, which is typically either a REG
494 or CC0. It returns a pointer to the innermost rtx expression
495 containing DEST. Appearances of DEST that are being used to
496 totally replace it are not counted. */
499 find_single_use_1 (rtx dest, rtx *loc)
502 enum rtx_code code = GET_CODE (x);
520 /* If the destination is anything other than CC0, PC, a REG or a SUBREG
521 of a REG that occupies all of the REG, the insn uses DEST if
522 it is mentioned in the destination or the source. Otherwise, we
523 need just check the source. */
524 if (GET_CODE (SET_DEST (x)) != CC0
525 && GET_CODE (SET_DEST (x)) != PC
526 && !REG_P (SET_DEST (x))
527 && ! (GET_CODE (SET_DEST (x)) == SUBREG
528 && REG_P (SUBREG_REG (SET_DEST (x)))
529 && (((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x))))
530 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
531 == ((GET_MODE_SIZE (GET_MODE (SET_DEST (x)))
532 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD))))
535 return find_single_use_1 (dest, &SET_SRC (x));
539 return find_single_use_1 (dest, &XEXP (x, 0));
545 /* If it wasn't one of the common cases above, check each expression and
546 vector of this code. Look for a unique usage of DEST. */
548 fmt = GET_RTX_FORMAT (code);
549 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
553 if (dest == XEXP (x, i)
554 || (REG_P (dest) && REG_P (XEXP (x, i))
555 && REGNO (dest) == REGNO (XEXP (x, i))))
558 this_result = find_single_use_1 (dest, &XEXP (x, i));
561 result = this_result;
562 else if (this_result)
563 /* Duplicate usage. */
566 else if (fmt[i] == 'E')
570 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
572 if (XVECEXP (x, i, j) == dest
574 && REG_P (XVECEXP (x, i, j))
575 && REGNO (XVECEXP (x, i, j)) == REGNO (dest)))
578 this_result = find_single_use_1 (dest, &XVECEXP (x, i, j));
581 result = this_result;
582 else if (this_result)
592 /* See if DEST, produced in INSN, is used only a single time in the
593 sequel. If so, return a pointer to the innermost rtx expression in which
596 If PLOC is nonzero, *PLOC is set to the insn containing the single use.
598 If DEST is cc0_rtx, we look only at the next insn. In that case, we don't
599 care about REG_DEAD notes or LOG_LINKS.
601 Otherwise, we find the single use by finding an insn that has a
602 LOG_LINKS pointing at INSN and has a REG_DEAD note for DEST. If DEST is
603 only referenced once in that insn, we know that it must be the first
604 and last insn referencing DEST. */
607 find_single_use (rtx dest, rtx insn, rtx *ploc)
617 next = NEXT_INSN (insn);
619 || (!NONJUMP_INSN_P (next) && !JUMP_P (next)))
622 result = find_single_use_1 (dest, &PATTERN (next));
632 bb = BLOCK_FOR_INSN (insn);
633 for (next = NEXT_INSN (insn);
634 next && BLOCK_FOR_INSN (next) == bb;
635 next = NEXT_INSN (next))
636 if (INSN_P (next) && dead_or_set_p (next, dest))
638 for (link = LOG_LINKS (next); link; link = XEXP (link, 1))
639 if (XEXP (link, 0) == insn)
644 result = find_single_use_1 (dest, &PATTERN (next));
654 /* Substitute NEWVAL, an rtx expression, into INTO, a place in some
655 insn. The substitution can be undone by undo_all. If INTO is already
656 set to NEWVAL, do not record this change. Because computing NEWVAL might
657 also call SUBST, we have to compute it before we put anything into
661 do_SUBST (rtx *into, rtx newval)
666 if (oldval == newval)
669 /* We'd like to catch as many invalid transformations here as
670 possible. Unfortunately, there are way too many mode changes
671 that are perfectly valid, so we'd waste too much effort for
672 little gain doing the checks here. Focus on catching invalid
673 transformations involving integer constants. */
674 if (GET_MODE_CLASS (GET_MODE (oldval)) == MODE_INT
675 && CONST_INT_P (newval))
677 /* Sanity check that we're replacing oldval with a CONST_INT
678 that is a valid sign-extension for the original mode. */
679 gcc_assert (INTVAL (newval)
680 == trunc_int_for_mode (INTVAL (newval), GET_MODE (oldval)));
682 /* Replacing the operand of a SUBREG or a ZERO_EXTEND with a
683 CONST_INT is not valid, because after the replacement, the
684 original mode would be gone. Unfortunately, we can't tell
685 when do_SUBST is called to replace the operand thereof, so we
686 perform this test on oldval instead, checking whether an
687 invalid replacement took place before we got here. */
688 gcc_assert (!(GET_CODE (oldval) == SUBREG
689 && CONST_INT_P (SUBREG_REG (oldval))));
690 gcc_assert (!(GET_CODE (oldval) == ZERO_EXTEND
691 && CONST_INT_P (XEXP (oldval, 0))));
695 buf = undobuf.frees, undobuf.frees = buf->next;
697 buf = XNEW (struct undo);
699 buf->kind = UNDO_RTX;
701 buf->old_contents.r = oldval;
704 buf->next = undobuf.undos, undobuf.undos = buf;
707 #define SUBST(INTO, NEWVAL) do_SUBST(&(INTO), (NEWVAL))
709 /* Similar to SUBST, but NEWVAL is an int expression. Note that substitution
710 for the value of a HOST_WIDE_INT value (including CONST_INT) is
714 do_SUBST_INT (int *into, int newval)
719 if (oldval == newval)
723 buf = undobuf.frees, undobuf.frees = buf->next;
725 buf = XNEW (struct undo);
727 buf->kind = UNDO_INT;
729 buf->old_contents.i = oldval;
732 buf->next = undobuf.undos, undobuf.undos = buf;
735 #define SUBST_INT(INTO, NEWVAL) do_SUBST_INT(&(INTO), (NEWVAL))
737 /* Similar to SUBST, but just substitute the mode. This is used when
738 changing the mode of a pseudo-register, so that any other
739 references to the entry in the regno_reg_rtx array will change as
743 do_SUBST_MODE (rtx *into, enum machine_mode newval)
746 enum machine_mode oldval = GET_MODE (*into);
748 if (oldval == newval)
752 buf = undobuf.frees, undobuf.frees = buf->next;
754 buf = XNEW (struct undo);
756 buf->kind = UNDO_MODE;
758 buf->old_contents.m = oldval;
759 adjust_reg_mode (*into, newval);
761 buf->next = undobuf.undos, undobuf.undos = buf;
764 #define SUBST_MODE(INTO, NEWVAL) do_SUBST_MODE(&(INTO), (NEWVAL))
766 /* Subroutine of try_combine. Determine whether the combine replacement
767 patterns NEWPAT, NEWI2PAT and NEWOTHERPAT are cheaper according to
768 insn_rtx_cost that the original instruction sequence I1, I2, I3 and
769 undobuf.other_insn. Note that I1 and/or NEWI2PAT may be NULL_RTX.
770 NEWOTHERPAT and undobuf.other_insn may also both be NULL_RTX. This
771 function returns false, if the costs of all instructions can be
772 estimated, and the replacements are more expensive than the original
776 combine_validate_cost (rtx i1, rtx i2, rtx i3, rtx newpat, rtx newi2pat,
779 int i1_cost, i2_cost, i3_cost;
780 int new_i2_cost, new_i3_cost;
781 int old_cost, new_cost;
783 /* Lookup the original insn_rtx_costs. */
784 i2_cost = INSN_COST (i2);
785 i3_cost = INSN_COST (i3);
789 i1_cost = INSN_COST (i1);
790 old_cost = (i1_cost > 0 && i2_cost > 0 && i3_cost > 0)
791 ? i1_cost + i2_cost + i3_cost : 0;
795 old_cost = (i2_cost > 0 && i3_cost > 0) ? i2_cost + i3_cost : 0;
799 /* Calculate the replacement insn_rtx_costs. */
800 new_i3_cost = insn_rtx_cost (newpat, optimize_this_for_speed_p);
803 new_i2_cost = insn_rtx_cost (newi2pat, optimize_this_for_speed_p);
804 new_cost = (new_i2_cost > 0 && new_i3_cost > 0)
805 ? new_i2_cost + new_i3_cost : 0;
809 new_cost = new_i3_cost;
813 if (undobuf.other_insn)
815 int old_other_cost, new_other_cost;
817 old_other_cost = INSN_COST (undobuf.other_insn);
818 new_other_cost = insn_rtx_cost (newotherpat, optimize_this_for_speed_p);
819 if (old_other_cost > 0 && new_other_cost > 0)
821 old_cost += old_other_cost;
822 new_cost += new_other_cost;
828 /* Disallow this recombination if both new_cost and old_cost are
829 greater than zero, and new_cost is greater than old cost. */
831 && new_cost > old_cost)
838 "rejecting combination of insns %d, %d and %d\n",
839 INSN_UID (i1), INSN_UID (i2), INSN_UID (i3));
840 fprintf (dump_file, "original costs %d + %d + %d = %d\n",
841 i1_cost, i2_cost, i3_cost, old_cost);
846 "rejecting combination of insns %d and %d\n",
847 INSN_UID (i2), INSN_UID (i3));
848 fprintf (dump_file, "original costs %d + %d = %d\n",
849 i2_cost, i3_cost, old_cost);
854 fprintf (dump_file, "replacement costs %d + %d = %d\n",
855 new_i2_cost, new_i3_cost, new_cost);
858 fprintf (dump_file, "replacement cost %d\n", new_cost);
864 /* Update the uid_insn_cost array with the replacement costs. */
865 INSN_COST (i2) = new_i2_cost;
866 INSN_COST (i3) = new_i3_cost;
874 /* Delete any insns that copy a register to itself. */
877 delete_noop_moves (void)
884 for (insn = BB_HEAD (bb); insn != NEXT_INSN (BB_END (bb)); insn = next)
886 next = NEXT_INSN (insn);
887 if (INSN_P (insn) && noop_move_p (insn))
890 fprintf (dump_file, "deleting noop move %d\n", INSN_UID (insn));
892 delete_insn_and_edges (insn);
899 /* Fill in log links field for all insns. */
902 create_log_links (void)
906 df_ref *def_vec, *use_vec;
908 next_use = XCNEWVEC (rtx, max_reg_num ());
910 /* Pass through each block from the end, recording the uses of each
911 register and establishing log links when def is encountered.
912 Note that we do not clear next_use array in order to save time,
913 so we have to test whether the use is in the same basic block as def.
915 There are a few cases below when we do not consider the definition or
916 usage -- these are taken from original flow.c did. Don't ask me why it is
917 done this way; I don't know and if it works, I don't want to know. */
921 FOR_BB_INSNS_REVERSE (bb, insn)
923 if (!NONDEBUG_INSN_P (insn))
926 /* Log links are created only once. */
927 gcc_assert (!LOG_LINKS (insn));
929 for (def_vec = DF_INSN_DEFS (insn); *def_vec; def_vec++)
931 df_ref def = *def_vec;
932 int regno = DF_REF_REGNO (def);
935 if (!next_use[regno])
938 /* Do not consider if it is pre/post modification in MEM. */
939 if (DF_REF_FLAGS (def) & DF_REF_PRE_POST_MODIFY)
942 /* Do not make the log link for frame pointer. */
943 if ((regno == FRAME_POINTER_REGNUM
944 && (! reload_completed || frame_pointer_needed))
945 #if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM
946 || (regno == HARD_FRAME_POINTER_REGNUM
947 && (! reload_completed || frame_pointer_needed))
949 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
950 || (regno == ARG_POINTER_REGNUM && fixed_regs[regno])
955 use_insn = next_use[regno];
956 if (BLOCK_FOR_INSN (use_insn) == bb)
960 We don't build a LOG_LINK for hard registers contained
961 in ASM_OPERANDs. If these registers get replaced,
962 we might wind up changing the semantics of the insn,
963 even if reload can make what appear to be valid
964 assignments later. */
965 if (regno >= FIRST_PSEUDO_REGISTER
966 || asm_noperands (PATTERN (use_insn)) < 0)
968 /* Don't add duplicate links between instructions. */
970 for (links = LOG_LINKS (use_insn); links;
971 links = XEXP (links, 1))
972 if (insn == XEXP (links, 0))
976 LOG_LINKS (use_insn) =
977 alloc_INSN_LIST (insn, LOG_LINKS (use_insn));
980 next_use[regno] = NULL_RTX;
983 for (use_vec = DF_INSN_USES (insn); *use_vec; use_vec++)
985 df_ref use = *use_vec;
986 int regno = DF_REF_REGNO (use);
988 /* Do not consider the usage of the stack pointer
990 if (DF_REF_FLAGS (use) & DF_REF_CALL_STACK_USAGE)
993 next_use[regno] = insn;
1001 /* Clear LOG_LINKS fields of insns. */
1004 clear_log_links (void)
1008 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
1010 free_INSN_LIST_list (&LOG_LINKS (insn));
1013 /* Main entry point for combiner. F is the first insn of the function.
1014 NREGS is the first unused pseudo-reg number.
1016 Return nonzero if the combiner has turned an indirect jump
1017 instruction into a direct jump. */
1019 combine_instructions (rtx f, unsigned int nregs)
1025 rtx links, nextlinks;
1027 basic_block last_bb;
1029 int new_direct_jump_p = 0;
1031 for (first = f; first && !INSN_P (first); )
1032 first = NEXT_INSN (first);
1036 combine_attempts = 0;
1039 combine_successes = 0;
1041 rtl_hooks = combine_rtl_hooks;
1043 VEC_safe_grow_cleared (reg_stat_type, heap, reg_stat, nregs);
1045 init_recog_no_volatile ();
1047 /* Allocate array for insn info. */
1048 max_uid_known = get_max_uid ();
1049 uid_log_links = XCNEWVEC (rtx, max_uid_known + 1);
1050 uid_insn_cost = XCNEWVEC (int, max_uid_known + 1);
1052 nonzero_bits_mode = mode_for_size (HOST_BITS_PER_WIDE_INT, MODE_INT, 0);
1054 /* Don't use reg_stat[].nonzero_bits when computing it. This can cause
1055 problems when, for example, we have j <<= 1 in a loop. */
1057 nonzero_sign_valid = 0;
1058 label_tick = label_tick_ebb_start = 1;
1060 /* Scan all SETs and see if we can deduce anything about what
1061 bits are known to be zero for some registers and how many copies
1062 of the sign bit are known to exist for those registers.
1064 Also set any known values so that we can use it while searching
1065 for what bits are known to be set. */
1067 setup_incoming_promotions (first);
1068 /* Allow the entry block and the first block to fall into the same EBB.
1069 Conceptually the incoming promotions are assigned to the entry block. */
1070 last_bb = ENTRY_BLOCK_PTR;
1072 create_log_links ();
1073 FOR_EACH_BB (this_basic_block)
1075 optimize_this_for_speed_p = optimize_bb_for_speed_p (this_basic_block);
1080 if (!single_pred_p (this_basic_block)
1081 || single_pred (this_basic_block) != last_bb)
1082 label_tick_ebb_start = label_tick;
1083 last_bb = this_basic_block;
1085 FOR_BB_INSNS (this_basic_block, insn)
1086 if (INSN_P (insn) && BLOCK_FOR_INSN (insn))
1088 subst_low_luid = DF_INSN_LUID (insn);
1091 note_stores (PATTERN (insn), set_nonzero_bits_and_sign_copies,
1093 record_dead_and_set_regs (insn);
1096 for (links = REG_NOTES (insn); links; links = XEXP (links, 1))
1097 if (REG_NOTE_KIND (links) == REG_INC)
1098 set_nonzero_bits_and_sign_copies (XEXP (links, 0), NULL_RTX,
1102 /* Record the current insn_rtx_cost of this instruction. */
1103 if (NONJUMP_INSN_P (insn))
1104 INSN_COST (insn) = insn_rtx_cost (PATTERN (insn),
1105 optimize_this_for_speed_p);
1107 fprintf(dump_file, "insn_cost %d: %d\n",
1108 INSN_UID (insn), INSN_COST (insn));
1112 nonzero_sign_valid = 1;
1114 /* Now scan all the insns in forward order. */
1115 label_tick = label_tick_ebb_start = 1;
1117 setup_incoming_promotions (first);
1118 last_bb = ENTRY_BLOCK_PTR;
1120 FOR_EACH_BB (this_basic_block)
1122 optimize_this_for_speed_p = optimize_bb_for_speed_p (this_basic_block);
1127 if (!single_pred_p (this_basic_block)
1128 || single_pred (this_basic_block) != last_bb)
1129 label_tick_ebb_start = label_tick;
1130 last_bb = this_basic_block;
1132 rtl_profile_for_bb (this_basic_block);
1133 for (insn = BB_HEAD (this_basic_block);
1134 insn != NEXT_INSN (BB_END (this_basic_block));
1135 insn = next ? next : NEXT_INSN (insn))
1138 if (NONDEBUG_INSN_P (insn))
1140 /* See if we know about function return values before this
1141 insn based upon SUBREG flags. */
1142 check_promoted_subreg (insn, PATTERN (insn));
1144 /* See if we can find hardregs and subreg of pseudos in
1145 narrower modes. This could help turning TRUNCATEs
1147 note_uses (&PATTERN (insn), record_truncated_values, NULL);
1149 /* Try this insn with each insn it links back to. */
1151 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
1152 if ((next = try_combine (insn, XEXP (links, 0),
1153 NULL_RTX, &new_direct_jump_p)) != 0)
1156 /* Try each sequence of three linked insns ending with this one. */
1158 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
1160 rtx link = XEXP (links, 0);
1162 /* If the linked insn has been replaced by a note, then there
1163 is no point in pursuing this chain any further. */
1167 for (nextlinks = LOG_LINKS (link);
1169 nextlinks = XEXP (nextlinks, 1))
1170 if ((next = try_combine (insn, link,
1171 XEXP (nextlinks, 0),
1172 &new_direct_jump_p)) != 0)
1177 /* Try to combine a jump insn that uses CC0
1178 with a preceding insn that sets CC0, and maybe with its
1179 logical predecessor as well.
1180 This is how we make decrement-and-branch insns.
1181 We need this special code because data flow connections
1182 via CC0 do not get entered in LOG_LINKS. */
1185 && (prev = prev_nonnote_insn (insn)) != 0
1186 && NONJUMP_INSN_P (prev)
1187 && sets_cc0_p (PATTERN (prev)))
1189 if ((next = try_combine (insn, prev,
1190 NULL_RTX, &new_direct_jump_p)) != 0)
1193 for (nextlinks = LOG_LINKS (prev); nextlinks;
1194 nextlinks = XEXP (nextlinks, 1))
1195 if ((next = try_combine (insn, prev,
1196 XEXP (nextlinks, 0),
1197 &new_direct_jump_p)) != 0)
1201 /* Do the same for an insn that explicitly references CC0. */
1202 if (NONJUMP_INSN_P (insn)
1203 && (prev = prev_nonnote_insn (insn)) != 0
1204 && NONJUMP_INSN_P (prev)
1205 && sets_cc0_p (PATTERN (prev))
1206 && GET_CODE (PATTERN (insn)) == SET
1207 && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (insn))))
1209 if ((next = try_combine (insn, prev,
1210 NULL_RTX, &new_direct_jump_p)) != 0)
1213 for (nextlinks = LOG_LINKS (prev); nextlinks;
1214 nextlinks = XEXP (nextlinks, 1))
1215 if ((next = try_combine (insn, prev,
1216 XEXP (nextlinks, 0),
1217 &new_direct_jump_p)) != 0)
1221 /* Finally, see if any of the insns that this insn links to
1222 explicitly references CC0. If so, try this insn, that insn,
1223 and its predecessor if it sets CC0. */
1224 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
1225 if (NONJUMP_INSN_P (XEXP (links, 0))
1226 && GET_CODE (PATTERN (XEXP (links, 0))) == SET
1227 && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (XEXP (links, 0))))
1228 && (prev = prev_nonnote_insn (XEXP (links, 0))) != 0
1229 && NONJUMP_INSN_P (prev)
1230 && sets_cc0_p (PATTERN (prev))
1231 && (next = try_combine (insn, XEXP (links, 0),
1232 prev, &new_direct_jump_p)) != 0)
1236 /* Try combining an insn with two different insns whose results it
1238 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
1239 for (nextlinks = XEXP (links, 1); nextlinks;
1240 nextlinks = XEXP (nextlinks, 1))
1241 if ((next = try_combine (insn, XEXP (links, 0),
1242 XEXP (nextlinks, 0),
1243 &new_direct_jump_p)) != 0)
1246 /* Try this insn with each REG_EQUAL note it links back to. */
1247 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
1250 rtx temp = XEXP (links, 0);
1251 if ((set = single_set (temp)) != 0
1252 && (note = find_reg_equal_equiv_note (temp)) != 0
1253 && (note = XEXP (note, 0), GET_CODE (note)) != EXPR_LIST
1254 /* Avoid using a register that may already been marked
1255 dead by an earlier instruction. */
1256 && ! unmentioned_reg_p (note, SET_SRC (set))
1257 && (GET_MODE (note) == VOIDmode
1258 ? SCALAR_INT_MODE_P (GET_MODE (SET_DEST (set)))
1259 : GET_MODE (SET_DEST (set)) == GET_MODE (note)))
1261 /* Temporarily replace the set's source with the
1262 contents of the REG_EQUAL note. The insn will
1263 be deleted or recognized by try_combine. */
1264 rtx orig = SET_SRC (set);
1265 SET_SRC (set) = note;
1267 i2mod_old_rhs = copy_rtx (orig);
1268 i2mod_new_rhs = copy_rtx (note);
1269 next = try_combine (insn, i2mod, NULL_RTX,
1270 &new_direct_jump_p);
1274 SET_SRC (set) = orig;
1279 record_dead_and_set_regs (insn);
1287 default_rtl_profile ();
1290 new_direct_jump_p |= purge_all_dead_edges ();
1291 delete_noop_moves ();
1294 free (uid_log_links);
1295 free (uid_insn_cost);
1296 VEC_free (reg_stat_type, heap, reg_stat);
1299 struct undo *undo, *next;
1300 for (undo = undobuf.frees; undo; undo = next)
1308 total_attempts += combine_attempts;
1309 total_merges += combine_merges;
1310 total_extras += combine_extras;
1311 total_successes += combine_successes;
1313 nonzero_sign_valid = 0;
1314 rtl_hooks = general_rtl_hooks;
1316 /* Make recognizer allow volatile MEMs again. */
1319 return new_direct_jump_p;
1322 /* Wipe the last_xxx fields of reg_stat in preparation for another pass. */
1325 init_reg_last (void)
1330 for (i = 0; VEC_iterate (reg_stat_type, reg_stat, i, p); ++i)
1331 memset (p, 0, offsetof (reg_stat_type, sign_bit_copies));
1334 /* Set up any promoted values for incoming argument registers. */
1337 setup_incoming_promotions (rtx first)
1340 bool strictly_local = false;
1342 for (arg = DECL_ARGUMENTS (current_function_decl); arg;
1343 arg = TREE_CHAIN (arg))
1345 rtx x, reg = DECL_INCOMING_RTL (arg);
1347 enum machine_mode mode1, mode2, mode3, mode4;
1349 /* Only continue if the incoming argument is in a register. */
1353 /* Determine, if possible, whether all call sites of the current
1354 function lie within the current compilation unit. (This does
1355 take into account the exporting of a function via taking its
1356 address, and so forth.) */
1357 strictly_local = cgraph_local_info (current_function_decl)->local;
1359 /* The mode and signedness of the argument before any promotions happen
1360 (equal to the mode of the pseudo holding it at that stage). */
1361 mode1 = TYPE_MODE (TREE_TYPE (arg));
1362 uns1 = TYPE_UNSIGNED (TREE_TYPE (arg));
1364 /* The mode and signedness of the argument after any source language and
1365 TARGET_PROMOTE_PROTOTYPES-driven promotions. */
1366 mode2 = TYPE_MODE (DECL_ARG_TYPE (arg));
1367 uns3 = TYPE_UNSIGNED (DECL_ARG_TYPE (arg));
1369 /* The mode and signedness of the argument as it is actually passed,
1370 after any TARGET_PROMOTE_FUNCTION_ARGS-driven ABI promotions. */
1371 mode3 = promote_function_mode (DECL_ARG_TYPE (arg), mode2, &uns3,
1372 TREE_TYPE (cfun->decl), 0);
1374 /* The mode of the register in which the argument is being passed. */
1375 mode4 = GET_MODE (reg);
1377 /* Eliminate sign extensions in the callee when:
1378 (a) A mode promotion has occurred; */
1381 /* (b) The mode of the register is the same as the mode of
1382 the argument as it is passed; */
1385 /* (c) There's no language level extension; */
1388 /* (c.1) All callers are from the current compilation unit. If that's
1389 the case we don't have to rely on an ABI, we only have to know
1390 what we're generating right now, and we know that we will do the
1391 mode1 to mode2 promotion with the given sign. */
1392 else if (!strictly_local)
1394 /* (c.2) The combination of the two promotions is useful. This is
1395 true when the signs match, or if the first promotion is unsigned.
1396 In the later case, (sign_extend (zero_extend x)) is the same as
1397 (zero_extend (zero_extend x)), so make sure to force UNS3 true. */
1403 /* Record that the value was promoted from mode1 to mode3,
1404 so that any sign extension at the head of the current
1405 function may be eliminated. */
1406 x = gen_rtx_CLOBBER (mode1, const0_rtx);
1407 x = gen_rtx_fmt_e ((uns3 ? ZERO_EXTEND : SIGN_EXTEND), mode3, x);
1408 record_value_for_reg (reg, first, x);
1412 /* Called via note_stores. If X is a pseudo that is narrower than
1413 HOST_BITS_PER_WIDE_INT and is being set, record what bits are known zero.
1415 If we are setting only a portion of X and we can't figure out what
1416 portion, assume all bits will be used since we don't know what will
1419 Similarly, set how many bits of X are known to be copies of the sign bit
1420 at all locations in the function. This is the smallest number implied
1424 set_nonzero_bits_and_sign_copies (rtx x, const_rtx set, void *data)
1426 rtx insn = (rtx) data;
1430 && REGNO (x) >= FIRST_PSEUDO_REGISTER
1431 /* If this register is undefined at the start of the file, we can't
1432 say what its contents were. */
1433 && ! REGNO_REG_SET_P
1434 (DF_LR_IN (ENTRY_BLOCK_PTR->next_bb), REGNO (x))
1435 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT)
1437 reg_stat_type *rsp = VEC_index (reg_stat_type, reg_stat, REGNO (x));
1439 if (set == 0 || GET_CODE (set) == CLOBBER)
1441 rsp->nonzero_bits = GET_MODE_MASK (GET_MODE (x));
1442 rsp->sign_bit_copies = 1;
1446 /* If this register is being initialized using itself, and the
1447 register is uninitialized in this basic block, and there are
1448 no LOG_LINKS which set the register, then part of the
1449 register is uninitialized. In that case we can't assume
1450 anything about the number of nonzero bits.
1452 ??? We could do better if we checked this in
1453 reg_{nonzero_bits,num_sign_bit_copies}_for_combine. Then we
1454 could avoid making assumptions about the insn which initially
1455 sets the register, while still using the information in other
1456 insns. We would have to be careful to check every insn
1457 involved in the combination. */
1460 && reg_referenced_p (x, PATTERN (insn))
1461 && !REGNO_REG_SET_P (DF_LR_IN (BLOCK_FOR_INSN (insn)),
1466 for (link = LOG_LINKS (insn); link; link = XEXP (link, 1))
1468 if (dead_or_set_p (XEXP (link, 0), x))
1473 rsp->nonzero_bits = GET_MODE_MASK (GET_MODE (x));
1474 rsp->sign_bit_copies = 1;
1479 /* If this is a complex assignment, see if we can convert it into a
1480 simple assignment. */
1481 set = expand_field_assignment (set);
1483 /* If this is a simple assignment, or we have a paradoxical SUBREG,
1484 set what we know about X. */
1486 if (SET_DEST (set) == x
1487 || (GET_CODE (SET_DEST (set)) == SUBREG
1488 && (GET_MODE_SIZE (GET_MODE (SET_DEST (set)))
1489 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (set)))))
1490 && SUBREG_REG (SET_DEST (set)) == x))
1492 rtx src = SET_SRC (set);
1494 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
1495 /* If X is narrower than a word and SRC is a non-negative
1496 constant that would appear negative in the mode of X,
1497 sign-extend it for use in reg_stat[].nonzero_bits because some
1498 machines (maybe most) will actually do the sign-extension
1499 and this is the conservative approach.
1501 ??? For 2.5, try to tighten up the MD files in this regard
1502 instead of this kludge. */
1504 if (GET_MODE_BITSIZE (GET_MODE (x)) < BITS_PER_WORD
1505 && CONST_INT_P (src)
1507 && 0 != (INTVAL (src)
1508 & ((HOST_WIDE_INT) 1
1509 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
1510 src = GEN_INT (INTVAL (src)
1511 | ((HOST_WIDE_INT) (-1)
1512 << GET_MODE_BITSIZE (GET_MODE (x))));
1515 /* Don't call nonzero_bits if it cannot change anything. */
1516 if (rsp->nonzero_bits != ~(unsigned HOST_WIDE_INT) 0)
1517 rsp->nonzero_bits |= nonzero_bits (src, nonzero_bits_mode);
1518 num = num_sign_bit_copies (SET_SRC (set), GET_MODE (x));
1519 if (rsp->sign_bit_copies == 0
1520 || rsp->sign_bit_copies > num)
1521 rsp->sign_bit_copies = num;
1525 rsp->nonzero_bits = GET_MODE_MASK (GET_MODE (x));
1526 rsp->sign_bit_copies = 1;
1531 /* See if INSN can be combined into I3. PRED and SUCC are optionally
1532 insns that were previously combined into I3 or that will be combined
1533 into the merger of INSN and I3.
1535 Return 0 if the combination is not allowed for any reason.
1537 If the combination is allowed, *PDEST will be set to the single
1538 destination of INSN and *PSRC to the single source, and this function
1542 can_combine_p (rtx insn, rtx i3, rtx pred ATTRIBUTE_UNUSED, rtx succ,
1543 rtx *pdest, rtx *psrc)
1552 int all_adjacent = (succ ? (next_active_insn (insn) == succ
1553 && next_active_insn (succ) == i3)
1554 : next_active_insn (insn) == i3);
1556 /* Can combine only if previous insn is a SET of a REG, a SUBREG or CC0.
1557 or a PARALLEL consisting of such a SET and CLOBBERs.
1559 If INSN has CLOBBER parallel parts, ignore them for our processing.
1560 By definition, these happen during the execution of the insn. When it
1561 is merged with another insn, all bets are off. If they are, in fact,
1562 needed and aren't also supplied in I3, they may be added by
1563 recog_for_combine. Otherwise, it won't match.
1565 We can also ignore a SET whose SET_DEST is mentioned in a REG_UNUSED
1568 Get the source and destination of INSN. If more than one, can't
1571 if (GET_CODE (PATTERN (insn)) == SET)
1572 set = PATTERN (insn);
1573 else if (GET_CODE (PATTERN (insn)) == PARALLEL
1574 && GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == SET)
1576 for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
1578 rtx elt = XVECEXP (PATTERN (insn), 0, i);
1580 switch (GET_CODE (elt))
1582 /* This is important to combine floating point insns
1583 for the SH4 port. */
1585 /* Combining an isolated USE doesn't make sense.
1586 We depend here on combinable_i3pat to reject them. */
1587 /* The code below this loop only verifies that the inputs of
1588 the SET in INSN do not change. We call reg_set_between_p
1589 to verify that the REG in the USE does not change between
1591 If the USE in INSN was for a pseudo register, the matching
1592 insn pattern will likely match any register; combining this
1593 with any other USE would only be safe if we knew that the
1594 used registers have identical values, or if there was
1595 something to tell them apart, e.g. different modes. For
1596 now, we forgo such complicated tests and simply disallow
1597 combining of USES of pseudo registers with any other USE. */
1598 if (REG_P (XEXP (elt, 0))
1599 && GET_CODE (PATTERN (i3)) == PARALLEL)
1601 rtx i3pat = PATTERN (i3);
1602 int i = XVECLEN (i3pat, 0) - 1;
1603 unsigned int regno = REGNO (XEXP (elt, 0));
1607 rtx i3elt = XVECEXP (i3pat, 0, i);
1609 if (GET_CODE (i3elt) == USE
1610 && REG_P (XEXP (i3elt, 0))
1611 && (REGNO (XEXP (i3elt, 0)) == regno
1612 ? reg_set_between_p (XEXP (elt, 0),
1613 PREV_INSN (insn), i3)
1614 : regno >= FIRST_PSEUDO_REGISTER))
1621 /* We can ignore CLOBBERs. */
1626 /* Ignore SETs whose result isn't used but not those that
1627 have side-effects. */
1628 if (find_reg_note (insn, REG_UNUSED, SET_DEST (elt))
1629 && insn_nothrow_p (insn)
1630 && !side_effects_p (elt))
1633 /* If we have already found a SET, this is a second one and
1634 so we cannot combine with this insn. */
1642 /* Anything else means we can't combine. */
1648 /* If SET_SRC is an ASM_OPERANDS we can't throw away these CLOBBERs,
1649 so don't do anything with it. */
1650 || GET_CODE (SET_SRC (set)) == ASM_OPERANDS)
1659 set = expand_field_assignment (set);
1660 src = SET_SRC (set), dest = SET_DEST (set);
1662 /* Don't eliminate a store in the stack pointer. */
1663 if (dest == stack_pointer_rtx
1664 /* Don't combine with an insn that sets a register to itself if it has
1665 a REG_EQUAL note. This may be part of a LIBCALL sequence. */
1666 || (rtx_equal_p (src, dest) && find_reg_note (insn, REG_EQUAL, NULL_RTX))
1667 /* Can't merge an ASM_OPERANDS. */
1668 || GET_CODE (src) == ASM_OPERANDS
1669 /* Can't merge a function call. */
1670 || GET_CODE (src) == CALL
1671 /* Don't eliminate a function call argument. */
1673 && (find_reg_fusage (i3, USE, dest)
1675 && REGNO (dest) < FIRST_PSEUDO_REGISTER
1676 && global_regs[REGNO (dest)])))
1677 /* Don't substitute into an incremented register. */
1678 || FIND_REG_INC_NOTE (i3, dest)
1679 || (succ && FIND_REG_INC_NOTE (succ, dest))
1680 /* Don't substitute into a non-local goto, this confuses CFG. */
1681 || (JUMP_P (i3) && find_reg_note (i3, REG_NON_LOCAL_GOTO, NULL_RTX))
1682 /* Make sure that DEST is not used after SUCC but before I3. */
1683 || (succ && ! all_adjacent
1684 && reg_used_between_p (dest, succ, i3))
1685 /* Make sure that the value that is to be substituted for the register
1686 does not use any registers whose values alter in between. However,
1687 If the insns are adjacent, a use can't cross a set even though we
1688 think it might (this can happen for a sequence of insns each setting
1689 the same destination; last_set of that register might point to
1690 a NOTE). If INSN has a REG_EQUIV note, the register is always
1691 equivalent to the memory so the substitution is valid even if there
1692 are intervening stores. Also, don't move a volatile asm or
1693 UNSPEC_VOLATILE across any other insns. */
1696 || ! find_reg_note (insn, REG_EQUIV, src))
1697 && use_crosses_set_p (src, DF_INSN_LUID (insn)))
1698 || (GET_CODE (src) == ASM_OPERANDS && MEM_VOLATILE_P (src))
1699 || GET_CODE (src) == UNSPEC_VOLATILE))
1700 /* Don't combine across a CALL_INSN, because that would possibly
1701 change whether the life span of some REGs crosses calls or not,
1702 and it is a pain to update that information.
1703 Exception: if source is a constant, moving it later can't hurt.
1704 Accept that as a special case. */
1705 || (DF_INSN_LUID (insn) < last_call_luid && ! CONSTANT_P (src)))
1708 /* DEST must either be a REG or CC0. */
1711 /* If register alignment is being enforced for multi-word items in all
1712 cases except for parameters, it is possible to have a register copy
1713 insn referencing a hard register that is not allowed to contain the
1714 mode being copied and which would not be valid as an operand of most
1715 insns. Eliminate this problem by not combining with such an insn.
1717 Also, on some machines we don't want to extend the life of a hard
1721 && ((REGNO (dest) < FIRST_PSEUDO_REGISTER
1722 && ! HARD_REGNO_MODE_OK (REGNO (dest), GET_MODE (dest)))
1723 /* Don't extend the life of a hard register unless it is
1724 user variable (if we have few registers) or it can't
1725 fit into the desired register (meaning something special
1727 Also avoid substituting a return register into I3, because
1728 reload can't handle a conflict with constraints of other
1730 || (REGNO (src) < FIRST_PSEUDO_REGISTER
1731 && ! HARD_REGNO_MODE_OK (REGNO (src), GET_MODE (src)))))
1734 else if (GET_CODE (dest) != CC0)
1738 if (GET_CODE (PATTERN (i3)) == PARALLEL)
1739 for (i = XVECLEN (PATTERN (i3), 0) - 1; i >= 0; i--)
1740 if (GET_CODE (XVECEXP (PATTERN (i3), 0, i)) == CLOBBER)
1742 /* Don't substitute for a register intended as a clobberable
1744 rtx reg = XEXP (XVECEXP (PATTERN (i3), 0, i), 0);
1745 if (rtx_equal_p (reg, dest))
1748 /* If the clobber represents an earlyclobber operand, we must not
1749 substitute an expression containing the clobbered register.
1750 As we do not analyze the constraint strings here, we have to
1751 make the conservative assumption. However, if the register is
1752 a fixed hard reg, the clobber cannot represent any operand;
1753 we leave it up to the machine description to either accept or
1754 reject use-and-clobber patterns. */
1756 || REGNO (reg) >= FIRST_PSEUDO_REGISTER
1757 || !fixed_regs[REGNO (reg)])
1758 if (reg_overlap_mentioned_p (reg, src))
1762 /* If INSN contains anything volatile, or is an `asm' (whether volatile
1763 or not), reject, unless nothing volatile comes between it and I3 */
1765 if (GET_CODE (src) == ASM_OPERANDS || volatile_refs_p (src))
1767 /* Make sure succ doesn't contain a volatile reference. */
1768 if (succ != 0 && volatile_refs_p (PATTERN (succ)))
1771 for (p = NEXT_INSN (insn); p != i3; p = NEXT_INSN (p))
1772 if (INSN_P (p) && p != succ && volatile_refs_p (PATTERN (p)))
1776 /* If INSN is an asm, and DEST is a hard register, reject, since it has
1777 to be an explicit register variable, and was chosen for a reason. */
1779 if (GET_CODE (src) == ASM_OPERANDS
1780 && REG_P (dest) && REGNO (dest) < FIRST_PSEUDO_REGISTER)
1783 /* If there are any volatile insns between INSN and I3, reject, because
1784 they might affect machine state. */
1786 for (p = NEXT_INSN (insn); p != i3; p = NEXT_INSN (p))
1787 if (INSN_P (p) && p != succ && volatile_insn_p (PATTERN (p)))
1790 /* If INSN contains an autoincrement or autodecrement, make sure that
1791 register is not used between there and I3, and not already used in
1792 I3 either. Neither must it be used in PRED or SUCC, if they exist.
1793 Also insist that I3 not be a jump; if it were one
1794 and the incremented register were spilled, we would lose. */
1797 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
1798 if (REG_NOTE_KIND (link) == REG_INC
1800 || reg_used_between_p (XEXP (link, 0), insn, i3)
1801 || (pred != NULL_RTX
1802 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (pred)))
1803 || (succ != NULL_RTX
1804 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (succ)))
1805 || reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i3))))
1810 /* Don't combine an insn that follows a CC0-setting insn.
1811 An insn that uses CC0 must not be separated from the one that sets it.
1812 We do, however, allow I2 to follow a CC0-setting insn if that insn
1813 is passed as I1; in that case it will be deleted also.
1814 We also allow combining in this case if all the insns are adjacent
1815 because that would leave the two CC0 insns adjacent as well.
1816 It would be more logical to test whether CC0 occurs inside I1 or I2,
1817 but that would be much slower, and this ought to be equivalent. */
1819 p = prev_nonnote_insn (insn);
1820 if (p && p != pred && NONJUMP_INSN_P (p) && sets_cc0_p (PATTERN (p))
1825 /* If we get here, we have passed all the tests and the combination is
1834 /* LOC is the location within I3 that contains its pattern or the component
1835 of a PARALLEL of the pattern. We validate that it is valid for combining.
1837 One problem is if I3 modifies its output, as opposed to replacing it
1838 entirely, we can't allow the output to contain I2DEST or I1DEST as doing
1839 so would produce an insn that is not equivalent to the original insns.
1843 (set (reg:DI 101) (reg:DI 100))
1844 (set (subreg:SI (reg:DI 101) 0) <foo>)
1846 This is NOT equivalent to:
1848 (parallel [(set (subreg:SI (reg:DI 100) 0) <foo>)
1849 (set (reg:DI 101) (reg:DI 100))])
1851 Not only does this modify 100 (in which case it might still be valid
1852 if 100 were dead in I2), it sets 101 to the ORIGINAL value of 100.
1854 We can also run into a problem if I2 sets a register that I1
1855 uses and I1 gets directly substituted into I3 (not via I2). In that
1856 case, we would be getting the wrong value of I2DEST into I3, so we
1857 must reject the combination. This case occurs when I2 and I1 both
1858 feed into I3, rather than when I1 feeds into I2, which feeds into I3.
1859 If I1_NOT_IN_SRC is nonzero, it means that finding I1 in the source
1860 of a SET must prevent combination from occurring.
1862 Before doing the above check, we first try to expand a field assignment
1863 into a set of logical operations.
1865 If PI3_DEST_KILLED is nonzero, it is a pointer to a location in which
1866 we place a register that is both set and used within I3. If more than one
1867 such register is detected, we fail.
1869 Return 1 if the combination is valid, zero otherwise. */
1872 combinable_i3pat (rtx i3, rtx *loc, rtx i2dest, rtx i1dest,
1873 int i1_not_in_src, rtx *pi3dest_killed)
1877 if (GET_CODE (x) == SET)
1880 rtx dest = SET_DEST (set);
1881 rtx src = SET_SRC (set);
1882 rtx inner_dest = dest;
1885 while (GET_CODE (inner_dest) == STRICT_LOW_PART
1886 || GET_CODE (inner_dest) == SUBREG
1887 || GET_CODE (inner_dest) == ZERO_EXTRACT)
1888 inner_dest = XEXP (inner_dest, 0);
1890 /* Check for the case where I3 modifies its output, as discussed
1891 above. We don't want to prevent pseudos from being combined
1892 into the address of a MEM, so only prevent the combination if
1893 i1 or i2 set the same MEM. */
1894 if ((inner_dest != dest &&
1895 (!MEM_P (inner_dest)
1896 || rtx_equal_p (i2dest, inner_dest)
1897 || (i1dest && rtx_equal_p (i1dest, inner_dest)))
1898 && (reg_overlap_mentioned_p (i2dest, inner_dest)
1899 || (i1dest && reg_overlap_mentioned_p (i1dest, inner_dest))))
1901 /* This is the same test done in can_combine_p except we can't test
1902 all_adjacent; we don't have to, since this instruction will stay
1903 in place, thus we are not considering increasing the lifetime of
1906 Also, if this insn sets a function argument, combining it with
1907 something that might need a spill could clobber a previous
1908 function argument; the all_adjacent test in can_combine_p also
1909 checks this; here, we do a more specific test for this case. */
1911 || (REG_P (inner_dest)
1912 && REGNO (inner_dest) < FIRST_PSEUDO_REGISTER
1913 && (! HARD_REGNO_MODE_OK (REGNO (inner_dest),
1914 GET_MODE (inner_dest))))
1915 || (i1_not_in_src && reg_overlap_mentioned_p (i1dest, src)))
1918 /* If DEST is used in I3, it is being killed in this insn, so
1919 record that for later. We have to consider paradoxical
1920 subregs here, since they kill the whole register, but we
1921 ignore partial subregs, STRICT_LOW_PART, etc.
1922 Never add REG_DEAD notes for the FRAME_POINTER_REGNUM or the
1923 STACK_POINTER_REGNUM, since these are always considered to be
1924 live. Similarly for ARG_POINTER_REGNUM if it is fixed. */
1926 if (GET_CODE (subdest) == SUBREG
1927 && (GET_MODE_SIZE (GET_MODE (subdest))
1928 >= GET_MODE_SIZE (GET_MODE (SUBREG_REG (subdest)))))
1929 subdest = SUBREG_REG (subdest);
1932 && reg_referenced_p (subdest, PATTERN (i3))
1933 && REGNO (subdest) != FRAME_POINTER_REGNUM
1934 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
1935 && REGNO (subdest) != HARD_FRAME_POINTER_REGNUM
1937 #if ARG_POINTER_REGNUM != FRAME_POINTER_REGNUM
1938 && (REGNO (subdest) != ARG_POINTER_REGNUM
1939 || ! fixed_regs [REGNO (subdest)])
1941 && REGNO (subdest) != STACK_POINTER_REGNUM)
1943 if (*pi3dest_killed)
1946 *pi3dest_killed = subdest;
1950 else if (GET_CODE (x) == PARALLEL)
1954 for (i = 0; i < XVECLEN (x, 0); i++)
1955 if (! combinable_i3pat (i3, &XVECEXP (x, 0, i), i2dest, i1dest,
1956 i1_not_in_src, pi3dest_killed))
1963 /* Return 1 if X is an arithmetic expression that contains a multiplication
1964 and division. We don't count multiplications by powers of two here. */
1967 contains_muldiv (rtx x)
1969 switch (GET_CODE (x))
1971 case MOD: case DIV: case UMOD: case UDIV:
1975 return ! (CONST_INT_P (XEXP (x, 1))
1976 && exact_log2 (INTVAL (XEXP (x, 1))) >= 0);
1979 return contains_muldiv (XEXP (x, 0))
1980 || contains_muldiv (XEXP (x, 1));
1983 return contains_muldiv (XEXP (x, 0));
1989 /* Determine whether INSN can be used in a combination. Return nonzero if
1990 not. This is used in try_combine to detect early some cases where we
1991 can't perform combinations. */
1994 cant_combine_insn_p (rtx insn)
1999 /* If this isn't really an insn, we can't do anything.
2000 This can occur when flow deletes an insn that it has merged into an
2001 auto-increment address. */
2002 if (! INSN_P (insn))
2005 /* Never combine loads and stores involving hard regs that are likely
2006 to be spilled. The register allocator can usually handle such
2007 reg-reg moves by tying. If we allow the combiner to make
2008 substitutions of likely-spilled regs, reload might die.
2009 As an exception, we allow combinations involving fixed regs; these are
2010 not available to the register allocator so there's no risk involved. */
2012 set = single_set (insn);
2015 src = SET_SRC (set);
2016 dest = SET_DEST (set);
2017 if (GET_CODE (src) == SUBREG)
2018 src = SUBREG_REG (src);
2019 if (GET_CODE (dest) == SUBREG)
2020 dest = SUBREG_REG (dest);
2021 if (REG_P (src) && REG_P (dest)
2022 && ((REGNO (src) < FIRST_PSEUDO_REGISTER
2023 && ! fixed_regs[REGNO (src)]
2024 && CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (REGNO (src))))
2025 || (REGNO (dest) < FIRST_PSEUDO_REGISTER
2026 && ! fixed_regs[REGNO (dest)]
2027 && CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (REGNO (dest))))))
2033 struct likely_spilled_retval_info
2035 unsigned regno, nregs;
2039 /* Called via note_stores by likely_spilled_retval_p. Remove from info->mask
2040 hard registers that are known to be written to / clobbered in full. */
2042 likely_spilled_retval_1 (rtx x, const_rtx set, void *data)
2044 struct likely_spilled_retval_info *const info =
2045 (struct likely_spilled_retval_info *) data;
2046 unsigned regno, nregs;
2049 if (!REG_P (XEXP (set, 0)))
2052 if (regno >= info->regno + info->nregs)
2054 nregs = hard_regno_nregs[regno][GET_MODE (x)];
2055 if (regno + nregs <= info->regno)
2057 new_mask = (2U << (nregs - 1)) - 1;
2058 if (regno < info->regno)
2059 new_mask >>= info->regno - regno;
2061 new_mask <<= regno - info->regno;
2062 info->mask &= ~new_mask;
2065 /* Return nonzero iff part of the return value is live during INSN, and
2066 it is likely spilled. This can happen when more than one insn is needed
2067 to copy the return value, e.g. when we consider to combine into the
2068 second copy insn for a complex value. */
2071 likely_spilled_retval_p (rtx insn)
2073 rtx use = BB_END (this_basic_block);
2075 unsigned regno, nregs;
2076 /* We assume here that no machine mode needs more than
2077 32 hard registers when the value overlaps with a register
2078 for which TARGET_FUNCTION_VALUE_REGNO_P is true. */
2080 struct likely_spilled_retval_info info;
2082 if (!NONJUMP_INSN_P (use) || GET_CODE (PATTERN (use)) != USE || insn == use)
2084 reg = XEXP (PATTERN (use), 0);
2085 if (!REG_P (reg) || !targetm.calls.function_value_regno_p (REGNO (reg)))
2087 regno = REGNO (reg);
2088 nregs = hard_regno_nregs[regno][GET_MODE (reg)];
2091 mask = (2U << (nregs - 1)) - 1;
2093 /* Disregard parts of the return value that are set later. */
2097 for (p = PREV_INSN (use); info.mask && p != insn; p = PREV_INSN (p))
2099 note_stores (PATTERN (p), likely_spilled_retval_1, &info);
2102 /* Check if any of the (probably) live return value registers is
2107 if ((mask & 1 << nregs)
2108 && CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (regno + nregs)))
2114 /* Adjust INSN after we made a change to its destination.
2116 Changing the destination can invalidate notes that say something about
2117 the results of the insn and a LOG_LINK pointing to the insn. */
2120 adjust_for_new_dest (rtx insn)
2122 /* For notes, be conservative and simply remove them. */
2123 remove_reg_equal_equiv_notes (insn);
2125 /* The new insn will have a destination that was previously the destination
2126 of an insn just above it. Call distribute_links to make a LOG_LINK from
2127 the next use of that destination. */
2128 distribute_links (gen_rtx_INSN_LIST (VOIDmode, insn, NULL_RTX));
2130 df_insn_rescan (insn);
2133 /* Return TRUE if combine can reuse reg X in mode MODE.
2134 ADDED_SETS is nonzero if the original set is still required. */
2136 can_change_dest_mode (rtx x, int added_sets, enum machine_mode mode)
2144 /* Allow hard registers if the new mode is legal, and occupies no more
2145 registers than the old mode. */
2146 if (regno < FIRST_PSEUDO_REGISTER)
2147 return (HARD_REGNO_MODE_OK (regno, mode)
2148 && (hard_regno_nregs[regno][GET_MODE (x)]
2149 >= hard_regno_nregs[regno][mode]));
2151 /* Or a pseudo that is only used once. */
2152 return (REG_N_SETS (regno) == 1 && !added_sets
2153 && !REG_USERVAR_P (x));
2157 /* Check whether X, the destination of a set, refers to part of
2158 the register specified by REG. */
2161 reg_subword_p (rtx x, rtx reg)
2163 /* Check that reg is an integer mode register. */
2164 if (!REG_P (reg) || GET_MODE_CLASS (GET_MODE (reg)) != MODE_INT)
2167 if (GET_CODE (x) == STRICT_LOW_PART
2168 || GET_CODE (x) == ZERO_EXTRACT)
2171 return GET_CODE (x) == SUBREG
2172 && SUBREG_REG (x) == reg
2173 && GET_MODE_CLASS (GET_MODE (x)) == MODE_INT;
2177 /* Replace auto-increment addressing modes with explicit operations to
2178 access the same addresses without modifying the corresponding
2179 registers. If AFTER holds, SRC is meant to be reused after the
2180 side effect, otherwise it is to be reused before that. */
2183 cleanup_auto_inc_dec (rtx src, bool after, enum machine_mode mem_mode)
2186 const RTX_CODE code = GET_CODE (x);
2202 /* SCRATCH must be shared because they represent distinct values. */
2205 if (REG_P (XEXP (x, 0)) && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER)
2210 if (shared_const_p (x))
2215 mem_mode = GET_MODE (x);
2222 gcc_assert (mem_mode != VOIDmode && mem_mode != BLKmode);
2223 if (after == (code == PRE_INC || code == PRE_DEC))
2224 x = cleanup_auto_inc_dec (XEXP (x, 0), after, mem_mode);
2226 x = gen_rtx_PLUS (GET_MODE (x),
2227 cleanup_auto_inc_dec (XEXP (x, 0), after, mem_mode),
2228 GEN_INT ((code == PRE_INC || code == POST_INC)
2229 ? GET_MODE_SIZE (mem_mode)
2230 : -GET_MODE_SIZE (mem_mode)));
2235 if (after == (code == PRE_MODIFY))
2239 return cleanup_auto_inc_dec (x, after, mem_mode);
2245 /* Copy the various flags, fields, and other information. We assume
2246 that all fields need copying, and then clear the fields that should
2247 not be copied. That is the sensible default behavior, and forces
2248 us to explicitly document why we are *not* copying a flag. */
2249 x = shallow_copy_rtx (x);
2251 /* We do not copy the USED flag, which is used as a mark bit during
2252 walks over the RTL. */
2253 RTX_FLAG (x, used) = 0;
2255 /* We do not copy FRAME_RELATED for INSNs. */
2257 RTX_FLAG (x, frame_related) = 0;
2259 fmt = GET_RTX_FORMAT (code);
2260 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
2262 XEXP (x, i) = cleanup_auto_inc_dec (XEXP (x, i), after, mem_mode);
2263 else if (fmt[i] == 'E' || fmt[i] == 'V')
2266 XVEC (x, i) = rtvec_alloc (XVECLEN (x, i));
2267 for (j = 0; j < XVECLEN (x, i); j++)
2269 = cleanup_auto_inc_dec (XVECEXP (src, i, j), after, mem_mode);
2276 /* Auxiliary data structure for propagate_for_debug_stmt. */
2278 struct rtx_subst_pair
2285 /* DATA points to an rtx_subst_pair. Return the value that should be
2289 propagate_for_debug_subst (rtx from, const_rtx old_rtx, void *data)
2291 struct rtx_subst_pair *pair = (struct rtx_subst_pair *)data;
2293 if (!rtx_equal_p (from, old_rtx))
2295 if (!pair->adjusted)
2297 pair->adjusted = true;
2299 pair->to = cleanup_auto_inc_dec (pair->to, pair->after, VOIDmode);
2301 pair->to = copy_rtx (pair->to);
2303 pair->to = make_compound_operation (pair->to, SET);
2306 return copy_rtx (pair->to);
2309 /* Replace occurrences of DEST with SRC in DEBUG_INSNs between INSN
2310 and LAST. If MOVE holds, debug insns must also be moved past
2314 propagate_for_debug (rtx insn, rtx last, rtx dest, rtx src, bool move)
2316 rtx next, move_pos = move ? last : NULL_RTX, loc;
2318 struct rtx_subst_pair p;
2323 next = NEXT_INSN (insn);
2324 while (next != last)
2327 next = NEXT_INSN (insn);
2328 if (DEBUG_INSN_P (insn))
2330 loc = simplify_replace_fn_rtx (INSN_VAR_LOCATION_LOC (insn),
2331 dest, propagate_for_debug_subst, &p);
2332 if (loc == INSN_VAR_LOCATION_LOC (insn))
2334 INSN_VAR_LOCATION_LOC (insn) = loc;
2338 PREV_INSN (insn) = NEXT_INSN (insn) = NULL_RTX;
2339 move_pos = emit_debug_insn_after (insn, move_pos);
2342 df_insn_rescan (insn);
2347 /* Delete the unconditional jump INSN and adjust the CFG correspondingly.
2348 Note that the INSN should be deleted *after* removing dead edges, so
2349 that the kept edge is the fallthrough edge for a (set (pc) (pc))
2350 but not for a (set (pc) (label_ref FOO)). */
2353 update_cfg_for_uncondjump (rtx insn)
2355 basic_block bb = BLOCK_FOR_INSN (insn);
2356 bool at_end = (BB_END (bb) == insn);
2359 purge_dead_edges (bb);
2362 if (at_end && EDGE_COUNT (bb->succs) == 1)
2363 single_succ_edge (bb)->flags |= EDGE_FALLTHRU;
2367 /* Try to combine the insns I1 and I2 into I3.
2368 Here I1 and I2 appear earlier than I3.
2369 I1 can be zero; then we combine just I2 into I3.
2371 If we are combining three insns and the resulting insn is not recognized,
2372 try splitting it into two insns. If that happens, I2 and I3 are retained
2373 and I1 is pseudo-deleted by turning it into a NOTE. Otherwise, I1 and I2
2376 Return 0 if the combination does not work. Then nothing is changed.
2377 If we did the combination, return the insn at which combine should
2380 Set NEW_DIRECT_JUMP_P to a nonzero value if try_combine creates a
2381 new direct jump instruction. */
2384 try_combine (rtx i3, rtx i2, rtx i1, int *new_direct_jump_p)
2386 /* New patterns for I3 and I2, respectively. */
2387 rtx newpat, newi2pat = 0;
2388 rtvec newpat_vec_with_clobbers = 0;
2389 int substed_i2 = 0, substed_i1 = 0;
2390 /* Indicates need to preserve SET in I1 or I2 in I3 if it is not dead. */
2391 int added_sets_1, added_sets_2;
2392 /* Total number of SETs to put into I3. */
2394 /* Nonzero if I2's body now appears in I3. */
2396 /* INSN_CODEs for new I3, new I2, and user of condition code. */
2397 int insn_code_number, i2_code_number = 0, other_code_number = 0;
2398 /* Contains I3 if the destination of I3 is used in its source, which means
2399 that the old life of I3 is being killed. If that usage is placed into
2400 I2 and not in I3, a REG_DEAD note must be made. */
2401 rtx i3dest_killed = 0;
2402 /* SET_DEST and SET_SRC of I2 and I1. */
2403 rtx i2dest = 0, i2src = 0, i1dest = 0, i1src = 0;
2404 /* Set if I2DEST was reused as a scratch register. */
2405 bool i2scratch = false;
2406 /* PATTERN (I1) and PATTERN (I2), or a copy of it in certain cases. */
2407 rtx i1pat = 0, i2pat = 0;
2408 /* Indicates if I2DEST or I1DEST is in I2SRC or I1_SRC. */
2409 int i2dest_in_i2src = 0, i1dest_in_i1src = 0, i2dest_in_i1src = 0;
2410 int i2dest_killed = 0, i1dest_killed = 0;
2411 int i1_feeds_i3 = 0;
2412 /* Notes that must be added to REG_NOTES in I3 and I2. */
2413 rtx new_i3_notes, new_i2_notes;
2414 /* Notes that we substituted I3 into I2 instead of the normal case. */
2415 int i3_subst_into_i2 = 0;
2416 /* Notes that I1, I2 or I3 is a MULT operation. */
2419 int changed_i3_dest = 0;
2425 rtx new_other_notes;
2428 /* Exit early if one of the insns involved can't be used for
2430 if (cant_combine_insn_p (i3)
2431 || cant_combine_insn_p (i2)
2432 || (i1 && cant_combine_insn_p (i1))
2433 || likely_spilled_retval_p (i3))
2437 undobuf.other_insn = 0;
2439 /* Reset the hard register usage information. */
2440 CLEAR_HARD_REG_SET (newpat_used_regs);
2442 if (dump_file && (dump_flags & TDF_DETAILS))
2445 fprintf (dump_file, "\nTrying %d, %d -> %d:\n",
2446 INSN_UID (i1), INSN_UID (i2), INSN_UID (i3));
2448 fprintf (dump_file, "\nTrying %d -> %d:\n",
2449 INSN_UID (i2), INSN_UID (i3));
2452 /* If I1 and I2 both feed I3, they can be in any order. To simplify the
2453 code below, set I1 to be the earlier of the two insns. */
2454 if (i1 && DF_INSN_LUID (i1) > DF_INSN_LUID (i2))
2455 temp = i1, i1 = i2, i2 = temp;
2457 added_links_insn = 0;
2459 /* First check for one important special-case that the code below will
2460 not handle. Namely, the case where I1 is zero, I2 is a PARALLEL
2461 and I3 is a SET whose SET_SRC is a SET_DEST in I2. In that case,
2462 we may be able to replace that destination with the destination of I3.
2463 This occurs in the common code where we compute both a quotient and
2464 remainder into a structure, in which case we want to do the computation
2465 directly into the structure to avoid register-register copies.
2467 Note that this case handles both multiple sets in I2 and also
2468 cases where I2 has a number of CLOBBER or PARALLELs.
2470 We make very conservative checks below and only try to handle the
2471 most common cases of this. For example, we only handle the case
2472 where I2 and I3 are adjacent to avoid making difficult register
2475 if (i1 == 0 && NONJUMP_INSN_P (i3) && GET_CODE (PATTERN (i3)) == SET
2476 && REG_P (SET_SRC (PATTERN (i3)))
2477 && REGNO (SET_SRC (PATTERN (i3))) >= FIRST_PSEUDO_REGISTER
2478 && find_reg_note (i3, REG_DEAD, SET_SRC (PATTERN (i3)))
2479 && GET_CODE (PATTERN (i2)) == PARALLEL
2480 && ! side_effects_p (SET_DEST (PATTERN (i3)))
2481 /* If the dest of I3 is a ZERO_EXTRACT or STRICT_LOW_PART, the code
2482 below would need to check what is inside (and reg_overlap_mentioned_p
2483 doesn't support those codes anyway). Don't allow those destinations;
2484 the resulting insn isn't likely to be recognized anyway. */
2485 && GET_CODE (SET_DEST (PATTERN (i3))) != ZERO_EXTRACT
2486 && GET_CODE (SET_DEST (PATTERN (i3))) != STRICT_LOW_PART
2487 && ! reg_overlap_mentioned_p (SET_SRC (PATTERN (i3)),
2488 SET_DEST (PATTERN (i3)))
2489 && next_active_insn (i2) == i3)
2491 rtx p2 = PATTERN (i2);
2493 /* Make sure that the destination of I3,
2494 which we are going to substitute into one output of I2,
2495 is not used within another output of I2. We must avoid making this:
2496 (parallel [(set (mem (reg 69)) ...)
2497 (set (reg 69) ...)])
2498 which is not well-defined as to order of actions.
2499 (Besides, reload can't handle output reloads for this.)
2501 The problem can also happen if the dest of I3 is a memory ref,
2502 if another dest in I2 is an indirect memory ref. */
2503 for (i = 0; i < XVECLEN (p2, 0); i++)
2504 if ((GET_CODE (XVECEXP (p2, 0, i)) == SET
2505 || GET_CODE (XVECEXP (p2, 0, i)) == CLOBBER)
2506 && reg_overlap_mentioned_p (SET_DEST (PATTERN (i3)),
2507 SET_DEST (XVECEXP (p2, 0, i))))
2510 if (i == XVECLEN (p2, 0))
2511 for (i = 0; i < XVECLEN (p2, 0); i++)
2512 if ((GET_CODE (XVECEXP (p2, 0, i)) == SET
2513 || GET_CODE (XVECEXP (p2, 0, i)) == CLOBBER)
2514 && SET_DEST (XVECEXP (p2, 0, i)) == SET_SRC (PATTERN (i3)))
2519 subst_low_luid = DF_INSN_LUID (i2);
2521 added_sets_2 = added_sets_1 = 0;
2522 i2src = SET_DEST (PATTERN (i3));
2523 i2dest = SET_SRC (PATTERN (i3));
2524 i2dest_killed = dead_or_set_p (i2, i2dest);
2526 /* Replace the dest in I2 with our dest and make the resulting
2527 insn the new pattern for I3. Then skip to where we
2528 validate the pattern. Everything was set up above. */
2529 SUBST (SET_DEST (XVECEXP (p2, 0, i)),
2530 SET_DEST (PATTERN (i3)));
2533 i3_subst_into_i2 = 1;
2534 goto validate_replacement;
2538 /* If I2 is setting a pseudo to a constant and I3 is setting some
2539 sub-part of it to another constant, merge them by making a new
2542 && (temp = single_set (i2)) != 0
2543 && (CONST_INT_P (SET_SRC (temp))
2544 || GET_CODE (SET_SRC (temp)) == CONST_DOUBLE)
2545 && GET_CODE (PATTERN (i3)) == SET
2546 && (CONST_INT_P (SET_SRC (PATTERN (i3)))
2547 || GET_CODE (SET_SRC (PATTERN (i3))) == CONST_DOUBLE)
2548 && reg_subword_p (SET_DEST (PATTERN (i3)), SET_DEST (temp)))
2550 rtx dest = SET_DEST (PATTERN (i3));
2554 if (GET_CODE (dest) == ZERO_EXTRACT)
2556 if (CONST_INT_P (XEXP (dest, 1))
2557 && CONST_INT_P (XEXP (dest, 2)))
2559 width = INTVAL (XEXP (dest, 1));
2560 offset = INTVAL (XEXP (dest, 2));
2561 dest = XEXP (dest, 0);
2562 if (BITS_BIG_ENDIAN)
2563 offset = GET_MODE_BITSIZE (GET_MODE (dest)) - width - offset;
2568 if (GET_CODE (dest) == STRICT_LOW_PART)
2569 dest = XEXP (dest, 0);
2570 width = GET_MODE_BITSIZE (GET_MODE (dest));
2576 /* If this is the low part, we're done. */
2577 if (subreg_lowpart_p (dest))
2579 /* Handle the case where inner is twice the size of outer. */
2580 else if (GET_MODE_BITSIZE (GET_MODE (SET_DEST (temp)))
2581 == 2 * GET_MODE_BITSIZE (GET_MODE (dest)))
2582 offset += GET_MODE_BITSIZE (GET_MODE (dest));
2583 /* Otherwise give up for now. */
2589 && (GET_MODE_BITSIZE (GET_MODE (SET_DEST (temp)))
2590 <= HOST_BITS_PER_DOUBLE_INT))
2593 rtx inner = SET_SRC (PATTERN (i3));
2594 rtx outer = SET_SRC (temp);
2596 o = rtx_to_double_int (outer);
2597 i = rtx_to_double_int (inner);
2599 m = double_int_mask (width);
2600 i = double_int_and (i, m);
2601 m = double_int_lshift (m, offset, HOST_BITS_PER_DOUBLE_INT, false);
2602 i = double_int_lshift (i, offset, HOST_BITS_PER_DOUBLE_INT, false);
2603 o = double_int_ior (double_int_and (o, double_int_not (m)), i);
2607 subst_low_luid = DF_INSN_LUID (i2);
2608 added_sets_2 = added_sets_1 = 0;
2609 i2dest = SET_DEST (temp);
2610 i2dest_killed = dead_or_set_p (i2, i2dest);
2612 /* Replace the source in I2 with the new constant and make the
2613 resulting insn the new pattern for I3. Then skip to where we
2614 validate the pattern. Everything was set up above. */
2615 SUBST (SET_SRC (temp),
2616 immed_double_int_const (o, GET_MODE (SET_DEST (temp))));
2618 newpat = PATTERN (i2);
2620 /* The dest of I3 has been replaced with the dest of I2. */
2621 changed_i3_dest = 1;
2622 goto validate_replacement;
2627 /* If we have no I1 and I2 looks like:
2628 (parallel [(set (reg:CC X) (compare:CC OP (const_int 0)))
2630 make up a dummy I1 that is
2633 (set (reg:CC X) (compare:CC Y (const_int 0)))
2635 (We can ignore any trailing CLOBBERs.)
2637 This undoes a previous combination and allows us to match a branch-and-
2640 if (i1 == 0 && GET_CODE (PATTERN (i2)) == PARALLEL
2641 && XVECLEN (PATTERN (i2), 0) >= 2
2642 && GET_CODE (XVECEXP (PATTERN (i2), 0, 0)) == SET
2643 && (GET_MODE_CLASS (GET_MODE (SET_DEST (XVECEXP (PATTERN (i2), 0, 0))))
2645 && GET_CODE (SET_SRC (XVECEXP (PATTERN (i2), 0, 0))) == COMPARE
2646 && XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 1) == const0_rtx
2647 && GET_CODE (XVECEXP (PATTERN (i2), 0, 1)) == SET
2648 && REG_P (SET_DEST (XVECEXP (PATTERN (i2), 0, 1)))
2649 && rtx_equal_p (XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 0),
2650 SET_SRC (XVECEXP (PATTERN (i2), 0, 1))))
2652 for (i = XVECLEN (PATTERN (i2), 0) - 1; i >= 2; i--)
2653 if (GET_CODE (XVECEXP (PATTERN (i2), 0, i)) != CLOBBER)
2658 /* We make I1 with the same INSN_UID as I2. This gives it
2659 the same DF_INSN_LUID for value tracking. Our fake I1 will
2660 never appear in the insn stream so giving it the same INSN_UID
2661 as I2 will not cause a problem. */
2663 i1 = gen_rtx_INSN (VOIDmode, INSN_UID (i2), NULL_RTX, i2,
2664 BLOCK_FOR_INSN (i2), INSN_LOCATOR (i2),
2665 XVECEXP (PATTERN (i2), 0, 1), -1, NULL_RTX);
2667 SUBST (PATTERN (i2), XVECEXP (PATTERN (i2), 0, 0));
2668 SUBST (XEXP (SET_SRC (PATTERN (i2)), 0),
2669 SET_DEST (PATTERN (i1)));
2674 /* Verify that I2 and I1 are valid for combining. */
2675 if (! can_combine_p (i2, i3, i1, NULL_RTX, &i2dest, &i2src)
2676 || (i1 && ! can_combine_p (i1, i3, NULL_RTX, i2, &i1dest, &i1src)))
2682 /* Record whether I2DEST is used in I2SRC and similarly for the other
2683 cases. Knowing this will help in register status updating below. */
2684 i2dest_in_i2src = reg_overlap_mentioned_p (i2dest, i2src);
2685 i1dest_in_i1src = i1 && reg_overlap_mentioned_p (i1dest, i1src);
2686 i2dest_in_i1src = i1 && reg_overlap_mentioned_p (i2dest, i1src);
2687 i2dest_killed = dead_or_set_p (i2, i2dest);
2688 i1dest_killed = i1 && dead_or_set_p (i1, i1dest);
2690 /* See if I1 directly feeds into I3. It does if I1DEST is not used
2692 i1_feeds_i3 = i1 && ! reg_overlap_mentioned_p (i1dest, i2src);
2694 /* Ensure that I3's pattern can be the destination of combines. */
2695 if (! combinable_i3pat (i3, &PATTERN (i3), i2dest, i1dest,
2696 i1 && i2dest_in_i1src && i1_feeds_i3,
2703 /* See if any of the insns is a MULT operation. Unless one is, we will
2704 reject a combination that is, since it must be slower. Be conservative
2706 if (GET_CODE (i2src) == MULT
2707 || (i1 != 0 && GET_CODE (i1src) == MULT)
2708 || (GET_CODE (PATTERN (i3)) == SET
2709 && GET_CODE (SET_SRC (PATTERN (i3))) == MULT))
2712 /* If I3 has an inc, then give up if I1 or I2 uses the reg that is inc'd.
2713 We used to do this EXCEPT in one case: I3 has a post-inc in an
2714 output operand. However, that exception can give rise to insns like
2716 which is a famous insn on the PDP-11 where the value of r3 used as the
2717 source was model-dependent. Avoid this sort of thing. */
2720 if (!(GET_CODE (PATTERN (i3)) == SET
2721 && REG_P (SET_SRC (PATTERN (i3)))
2722 && MEM_P (SET_DEST (PATTERN (i3)))
2723 && (GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_INC
2724 || GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_DEC)))
2725 /* It's not the exception. */
2728 for (link = REG_NOTES (i3); link; link = XEXP (link, 1))
2729 if (REG_NOTE_KIND (link) == REG_INC
2730 && (reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i2))
2732 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i1)))))
2739 /* See if the SETs in I1 or I2 need to be kept around in the merged
2740 instruction: whenever the value set there is still needed past I3.
2741 For the SETs in I2, this is easy: we see if I2DEST dies or is set in I3.
2743 For the SET in I1, we have two cases: If I1 and I2 independently
2744 feed into I3, the set in I1 needs to be kept around if I1DEST dies
2745 or is set in I3. Otherwise (if I1 feeds I2 which feeds I3), the set
2746 in I1 needs to be kept around unless I1DEST dies or is set in either
2747 I2 or I3. We can distinguish these cases by seeing if I2SRC mentions
2748 I1DEST. If so, we know I1 feeds into I2. */
2750 added_sets_2 = ! dead_or_set_p (i3, i2dest);
2753 = i1 && ! (i1_feeds_i3 ? dead_or_set_p (i3, i1dest)
2754 : (dead_or_set_p (i3, i1dest) || dead_or_set_p (i2, i1dest)));
2756 /* If the set in I2 needs to be kept around, we must make a copy of
2757 PATTERN (I2), so that when we substitute I1SRC for I1DEST in
2758 PATTERN (I2), we are only substituting for the original I1DEST, not into
2759 an already-substituted copy. This also prevents making self-referential
2760 rtx. If I2 is a PARALLEL, we just need the piece that assigns I2SRC to
2765 if (GET_CODE (PATTERN (i2)) == PARALLEL)
2766 i2pat = gen_rtx_SET (VOIDmode, i2dest, copy_rtx (i2src));
2768 i2pat = copy_rtx (PATTERN (i2));
2773 if (GET_CODE (PATTERN (i1)) == PARALLEL)
2774 i1pat = gen_rtx_SET (VOIDmode, i1dest, copy_rtx (i1src));
2776 i1pat = copy_rtx (PATTERN (i1));
2781 /* Substitute in the latest insn for the regs set by the earlier ones. */
2783 maxreg = max_reg_num ();
2788 /* Many machines that don't use CC0 have insns that can both perform an
2789 arithmetic operation and set the condition code. These operations will
2790 be represented as a PARALLEL with the first element of the vector
2791 being a COMPARE of an arithmetic operation with the constant zero.
2792 The second element of the vector will set some pseudo to the result
2793 of the same arithmetic operation. If we simplify the COMPARE, we won't
2794 match such a pattern and so will generate an extra insn. Here we test
2795 for this case, where both the comparison and the operation result are
2796 needed, and make the PARALLEL by just replacing I2DEST in I3SRC with
2797 I2SRC. Later we will make the PARALLEL that contains I2. */
2799 if (i1 == 0 && added_sets_2 && GET_CODE (PATTERN (i3)) == SET
2800 && GET_CODE (SET_SRC (PATTERN (i3))) == COMPARE
2801 && XEXP (SET_SRC (PATTERN (i3)), 1) == const0_rtx
2802 && rtx_equal_p (XEXP (SET_SRC (PATTERN (i3)), 0), i2dest))
2804 #ifdef SELECT_CC_MODE
2806 enum machine_mode compare_mode;
2809 newpat = PATTERN (i3);
2810 SUBST (XEXP (SET_SRC (newpat), 0), i2src);
2814 #ifdef SELECT_CC_MODE
2815 /* See if a COMPARE with the operand we substituted in should be done
2816 with the mode that is currently being used. If not, do the same
2817 processing we do in `subst' for a SET; namely, if the destination
2818 is used only once, try to replace it with a register of the proper
2819 mode and also replace the COMPARE. */
2820 if (undobuf.other_insn == 0
2821 && (cc_use = find_single_use (SET_DEST (newpat), i3,
2822 &undobuf.other_insn))
2823 && ((compare_mode = SELECT_CC_MODE (GET_CODE (*cc_use),
2825 != GET_MODE (SET_DEST (newpat))))
2827 if (can_change_dest_mode(SET_DEST (newpat), added_sets_2,
2830 unsigned int regno = REGNO (SET_DEST (newpat));
2833 if (regno < FIRST_PSEUDO_REGISTER)
2834 new_dest = gen_rtx_REG (compare_mode, regno);
2837 SUBST_MODE (regno_reg_rtx[regno], compare_mode);
2838 new_dest = regno_reg_rtx[regno];
2841 SUBST (SET_DEST (newpat), new_dest);
2842 SUBST (XEXP (*cc_use, 0), new_dest);
2843 SUBST (SET_SRC (newpat),
2844 gen_rtx_COMPARE (compare_mode, i2src, const0_rtx));
2847 undobuf.other_insn = 0;
2854 /* It is possible that the source of I2 or I1 may be performing
2855 an unneeded operation, such as a ZERO_EXTEND of something
2856 that is known to have the high part zero. Handle that case
2857 by letting subst look at the innermost one of them.
2859 Another way to do this would be to have a function that tries
2860 to simplify a single insn instead of merging two or more
2861 insns. We don't do this because of the potential of infinite
2862 loops and because of the potential extra memory required.
2863 However, doing it the way we are is a bit of a kludge and
2864 doesn't catch all cases.
2866 But only do this if -fexpensive-optimizations since it slows
2867 things down and doesn't usually win.
2869 This is not done in the COMPARE case above because the
2870 unmodified I2PAT is used in the PARALLEL and so a pattern
2871 with a modified I2SRC would not match. */
2873 if (flag_expensive_optimizations)
2875 /* Pass pc_rtx so no substitutions are done, just
2879 subst_low_luid = DF_INSN_LUID (i1);
2880 i1src = subst (i1src, pc_rtx, pc_rtx, 0, 0);
2884 subst_low_luid = DF_INSN_LUID (i2);
2885 i2src = subst (i2src, pc_rtx, pc_rtx, 0, 0);
2889 n_occurrences = 0; /* `subst' counts here */
2891 /* If I1 feeds into I2 (not into I3) and I1DEST is in I1SRC, we
2892 need to make a unique copy of I2SRC each time we substitute it
2893 to avoid self-referential rtl. */
2895 subst_low_luid = DF_INSN_LUID (i2);
2896 newpat = subst (PATTERN (i3), i2dest, i2src, 0,
2897 ! i1_feeds_i3 && i1dest_in_i1src);
2900 /* Record whether i2's body now appears within i3's body. */
2901 i2_is_used = n_occurrences;
2904 /* If we already got a failure, don't try to do more. Otherwise,
2905 try to substitute in I1 if we have it. */
2907 if (i1 && GET_CODE (newpat) != CLOBBER)
2909 /* Check that an autoincrement side-effect on I1 has not been lost.
2910 This happens if I1DEST is mentioned in I2 and dies there, and
2911 has disappeared from the new pattern. */
2912 if ((FIND_REG_INC_NOTE (i1, NULL_RTX) != 0
2914 && dead_or_set_p (i2, i1dest)
2915 && !reg_overlap_mentioned_p (i1dest, newpat))
2916 /* Before we can do this substitution, we must redo the test done
2917 above (see detailed comments there) that ensures that I1DEST
2918 isn't mentioned in any SETs in NEWPAT that are field assignments. */
2919 || !combinable_i3pat (NULL_RTX, &newpat, i1dest, NULL_RTX, 0, 0))
2926 subst_low_luid = DF_INSN_LUID (i1);
2927 newpat = subst (newpat, i1dest, i1src, 0, 0);
2931 /* Fail if an autoincrement side-effect has been duplicated. Be careful
2932 to count all the ways that I2SRC and I1SRC can be used. */
2933 if ((FIND_REG_INC_NOTE (i2, NULL_RTX) != 0
2934 && i2_is_used + added_sets_2 > 1)
2935 || (i1 != 0 && FIND_REG_INC_NOTE (i1, NULL_RTX) != 0
2936 && (n_occurrences + added_sets_1 + (added_sets_2 && ! i1_feeds_i3)
2938 /* Fail if we tried to make a new register. */
2939 || max_reg_num () != maxreg
2940 /* Fail if we couldn't do something and have a CLOBBER. */
2941 || GET_CODE (newpat) == CLOBBER
2942 /* Fail if this new pattern is a MULT and we didn't have one before
2943 at the outer level. */
2944 || (GET_CODE (newpat) == SET && GET_CODE (SET_SRC (newpat)) == MULT
2951 /* If the actions of the earlier insns must be kept
2952 in addition to substituting them into the latest one,
2953 we must make a new PARALLEL for the latest insn
2954 to hold additional the SETs. */
2956 if (added_sets_1 || added_sets_2)
2960 if (GET_CODE (newpat) == PARALLEL)
2962 rtvec old = XVEC (newpat, 0);
2963 total_sets = XVECLEN (newpat, 0) + added_sets_1 + added_sets_2;
2964 newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (total_sets));
2965 memcpy (XVEC (newpat, 0)->elem, &old->elem[0],
2966 sizeof (old->elem[0]) * old->num_elem);
2971 total_sets = 1 + added_sets_1 + added_sets_2;
2972 newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (total_sets));
2973 XVECEXP (newpat, 0, 0) = old;
2977 XVECEXP (newpat, 0, --total_sets) = i1pat;
2981 /* If there is no I1, use I2's body as is. We used to also not do
2982 the subst call below if I2 was substituted into I3,
2983 but that could lose a simplification. */
2985 XVECEXP (newpat, 0, --total_sets) = i2pat;
2987 /* See comment where i2pat is assigned. */
2988 XVECEXP (newpat, 0, --total_sets)
2989 = subst (i2pat, i1dest, i1src, 0, 0);
2993 validate_replacement:
2995 /* Note which hard regs this insn has as inputs. */
2996 mark_used_regs_combine (newpat);
2998 /* If recog_for_combine fails, it strips existing clobbers. If we'll
2999 consider splitting this pattern, we might need these clobbers. */
3000 if (i1 && GET_CODE (newpat) == PARALLEL
3001 && GET_CODE (XVECEXP (newpat, 0, XVECLEN (newpat, 0) - 1)) == CLOBBER)
3003 int len = XVECLEN (newpat, 0);
3005 newpat_vec_with_clobbers = rtvec_alloc (len);
3006 for (i = 0; i < len; i++)
3007 RTVEC_ELT (newpat_vec_with_clobbers, i) = XVECEXP (newpat, 0, i);
3010 /* Is the result of combination a valid instruction? */
3011 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
3013 /* If the result isn't valid, see if it is a PARALLEL of two SETs where
3014 the second SET's destination is a register that is unused and isn't
3015 marked as an instruction that might trap in an EH region. In that case,
3016 we just need the first SET. This can occur when simplifying a divmod
3017 insn. We *must* test for this case here because the code below that
3018 splits two independent SETs doesn't handle this case correctly when it
3019 updates the register status.
3021 It's pointless doing this if we originally had two sets, one from
3022 i3, and one from i2. Combining then splitting the parallel results
3023 in the original i2 again plus an invalid insn (which we delete).
3024 The net effect is only to move instructions around, which makes
3025 debug info less accurate.
3027 Also check the case where the first SET's destination is unused.
3028 That would not cause incorrect code, but does cause an unneeded
3031 if (insn_code_number < 0
3032 && !(added_sets_2 && i1 == 0)
3033 && GET_CODE (newpat) == PARALLEL
3034 && XVECLEN (newpat, 0) == 2
3035 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
3036 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
3037 && asm_noperands (newpat) < 0)
3039 rtx set0 = XVECEXP (newpat, 0, 0);
3040 rtx set1 = XVECEXP (newpat, 0, 1);
3042 if (((REG_P (SET_DEST (set1))
3043 && find_reg_note (i3, REG_UNUSED, SET_DEST (set1)))
3044 || (GET_CODE (SET_DEST (set1)) == SUBREG
3045 && find_reg_note (i3, REG_UNUSED, SUBREG_REG (SET_DEST (set1)))))
3046 && insn_nothrow_p (i3)
3047 && !side_effects_p (SET_SRC (set1)))
3050 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
3053 else if (((REG_P (SET_DEST (set0))
3054 && find_reg_note (i3, REG_UNUSED, SET_DEST (set0)))
3055 || (GET_CODE (SET_DEST (set0)) == SUBREG
3056 && find_reg_note (i3, REG_UNUSED,
3057 SUBREG_REG (SET_DEST (set0)))))
3058 && insn_nothrow_p (i3)
3059 && !side_effects_p (SET_SRC (set0)))
3062 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
3064 if (insn_code_number >= 0)
3065 changed_i3_dest = 1;
3069 /* If we were combining three insns and the result is a simple SET
3070 with no ASM_OPERANDS that wasn't recognized, try to split it into two
3071 insns. There are two ways to do this. It can be split using a
3072 machine-specific method (like when you have an addition of a large
3073 constant) or by combine in the function find_split_point. */
3075 if (i1 && insn_code_number < 0 && GET_CODE (newpat) == SET
3076 && asm_noperands (newpat) < 0)
3078 rtx parallel, m_split, *split;
3080 /* See if the MD file can split NEWPAT. If it can't, see if letting it
3081 use I2DEST as a scratch register will help. In the latter case,
3082 convert I2DEST to the mode of the source of NEWPAT if we can. */
3084 m_split = combine_split_insns (newpat, i3);
3086 /* We can only use I2DEST as a scratch reg if it doesn't overlap any
3087 inputs of NEWPAT. */
3089 /* ??? If I2DEST is not safe, and I1DEST exists, then it would be
3090 possible to try that as a scratch reg. This would require adding
3091 more code to make it work though. */
3093 if (m_split == 0 && ! reg_overlap_mentioned_p (i2dest, newpat))
3095 enum machine_mode new_mode = GET_MODE (SET_DEST (newpat));
3097 /* First try to split using the original register as a
3098 scratch register. */
3099 parallel = gen_rtx_PARALLEL (VOIDmode,
3100 gen_rtvec (2, newpat,
3101 gen_rtx_CLOBBER (VOIDmode,
3103 m_split = combine_split_insns (parallel, i3);
3105 /* If that didn't work, try changing the mode of I2DEST if
3108 && new_mode != GET_MODE (i2dest)
3109 && new_mode != VOIDmode
3110 && can_change_dest_mode (i2dest, added_sets_2, new_mode))
3112 enum machine_mode old_mode = GET_MODE (i2dest);
3115 if (REGNO (i2dest) < FIRST_PSEUDO_REGISTER)
3116 ni2dest = gen_rtx_REG (new_mode, REGNO (i2dest));
3119 SUBST_MODE (regno_reg_rtx[REGNO (i2dest)], new_mode);
3120 ni2dest = regno_reg_rtx[REGNO (i2dest)];
3123 parallel = (gen_rtx_PARALLEL
3125 gen_rtvec (2, newpat,
3126 gen_rtx_CLOBBER (VOIDmode,
3128 m_split = combine_split_insns (parallel, i3);
3131 && REGNO (i2dest) >= FIRST_PSEUDO_REGISTER)
3135 adjust_reg_mode (regno_reg_rtx[REGNO (i2dest)], old_mode);
3136 buf = undobuf.undos;
3137 undobuf.undos = buf->next;
3138 buf->next = undobuf.frees;
3139 undobuf.frees = buf;
3143 i2scratch = m_split != 0;
3146 /* If recog_for_combine has discarded clobbers, try to use them
3147 again for the split. */
3148 if (m_split == 0 && newpat_vec_with_clobbers)
3150 parallel = gen_rtx_PARALLEL (VOIDmode, newpat_vec_with_clobbers);
3151 m_split = combine_split_insns (parallel, i3);
3154 if (m_split && NEXT_INSN (m_split) == NULL_RTX)
3156 m_split = PATTERN (m_split);
3157 insn_code_number = recog_for_combine (&m_split, i3, &new_i3_notes);
3158 if (insn_code_number >= 0)
3161 else if (m_split && NEXT_INSN (NEXT_INSN (m_split)) == NULL_RTX
3162 && (next_real_insn (i2) == i3
3163 || ! use_crosses_set_p (PATTERN (m_split), DF_INSN_LUID (i2))))
3166 rtx newi3pat = PATTERN (NEXT_INSN (m_split));
3167 newi2pat = PATTERN (m_split);
3169 i3set = single_set (NEXT_INSN (m_split));
3170 i2set = single_set (m_split);
3172 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
3174 /* If I2 or I3 has multiple SETs, we won't know how to track
3175 register status, so don't use these insns. If I2's destination
3176 is used between I2 and I3, we also can't use these insns. */
3178 if (i2_code_number >= 0 && i2set && i3set
3179 && (next_real_insn (i2) == i3
3180 || ! reg_used_between_p (SET_DEST (i2set), i2, i3)))
3181 insn_code_number = recog_for_combine (&newi3pat, i3,
3183 if (insn_code_number >= 0)
3186 /* It is possible that both insns now set the destination of I3.
3187 If so, we must show an extra use of it. */
3189 if (insn_code_number >= 0)
3191 rtx new_i3_dest = SET_DEST (i3set);
3192 rtx new_i2_dest = SET_DEST (i2set);
3194 while (GET_CODE (new_i3_dest) == ZERO_EXTRACT
3195 || GET_CODE (new_i3_dest) == STRICT_LOW_PART
3196 || GET_CODE (new_i3_dest) == SUBREG)
3197 new_i3_dest = XEXP (new_i3_dest, 0);
3199 while (GET_CODE (new_i2_dest) == ZERO_EXTRACT
3200 || GET_CODE (new_i2_dest) == STRICT_LOW_PART
3201 || GET_CODE (new_i2_dest) == SUBREG)
3202 new_i2_dest = XEXP (new_i2_dest, 0);
3204 if (REG_P (new_i3_dest)
3205 && REG_P (new_i2_dest)
3206 && REGNO (new_i3_dest) == REGNO (new_i2_dest))
3207 INC_REG_N_SETS (REGNO (new_i2_dest), 1);
3211 /* If we can split it and use I2DEST, go ahead and see if that
3212 helps things be recognized. Verify that none of the registers
3213 are set between I2 and I3. */
3214 if (insn_code_number < 0
3215 && (split = find_split_point (&newpat, i3, false)) != 0
3219 /* We need I2DEST in the proper mode. If it is a hard register
3220 or the only use of a pseudo, we can change its mode.
3221 Make sure we don't change a hard register to have a mode that
3222 isn't valid for it, or change the number of registers. */
3223 && (GET_MODE (*split) == GET_MODE (i2dest)
3224 || GET_MODE (*split) == VOIDmode
3225 || can_change_dest_mode (i2dest, added_sets_2,
3227 && (next_real_insn (i2) == i3
3228 || ! use_crosses_set_p (*split, DF_INSN_LUID (i2)))
3229 /* We can't overwrite I2DEST if its value is still used by
3231 && ! reg_referenced_p (i2dest, newpat))
3233 rtx newdest = i2dest;
3234 enum rtx_code split_code = GET_CODE (*split);
3235 enum machine_mode split_mode = GET_MODE (*split);
3236 bool subst_done = false;
3237 newi2pat = NULL_RTX;
3241 /* *SPLIT may be part of I2SRC, so make sure we have the
3242 original expression around for later debug processing.
3243 We should not need I2SRC any more in other cases. */
3244 if (MAY_HAVE_DEBUG_INSNS)
3245 i2src = copy_rtx (i2src);
3249 /* Get NEWDEST as a register in the proper mode. We have already
3250 validated that we can do this. */
3251 if (GET_MODE (i2dest) != split_mode && split_mode != VOIDmode)
3253 if (REGNO (i2dest) < FIRST_PSEUDO_REGISTER)
3254 newdest = gen_rtx_REG (split_mode, REGNO (i2dest));
3257 SUBST_MODE (regno_reg_rtx[REGNO (i2dest)], split_mode);
3258 newdest = regno_reg_rtx[REGNO (i2dest)];
3262 /* If *SPLIT is a (mult FOO (const_int pow2)), convert it to
3263 an ASHIFT. This can occur if it was inside a PLUS and hence
3264 appeared to be a memory address. This is a kludge. */
3265 if (split_code == MULT
3266 && CONST_INT_P (XEXP (*split, 1))
3267 && INTVAL (XEXP (*split, 1)) > 0
3268 && (i = exact_log2 (INTVAL (XEXP (*split, 1)))) >= 0)
3270 SUBST (*split, gen_rtx_ASHIFT (split_mode,
3271 XEXP (*split, 0), GEN_INT (i)));
3272 /* Update split_code because we may not have a multiply
3274 split_code = GET_CODE (*split);
3277 #ifdef INSN_SCHEDULING
3278 /* If *SPLIT is a paradoxical SUBREG, when we split it, it should
3279 be written as a ZERO_EXTEND. */
3280 if (split_code == SUBREG && MEM_P (SUBREG_REG (*split)))
3282 #ifdef LOAD_EXTEND_OP
3283 /* Or as a SIGN_EXTEND if LOAD_EXTEND_OP says that that's
3284 what it really is. */
3285 if (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (*split)))
3287 SUBST (*split, gen_rtx_SIGN_EXTEND (split_mode,
3288 SUBREG_REG (*split)));
3291 SUBST (*split, gen_rtx_ZERO_EXTEND (split_mode,
3292 SUBREG_REG (*split)));
3296 /* Attempt to split binary operators using arithmetic identities. */
3297 if (BINARY_P (SET_SRC (newpat))
3298 && split_mode == GET_MODE (SET_SRC (newpat))
3299 && ! side_effects_p (SET_SRC (newpat)))
3301 rtx setsrc = SET_SRC (newpat);
3302 enum machine_mode mode = GET_MODE (setsrc);
3303 enum rtx_code code = GET_CODE (setsrc);
3304 rtx src_op0 = XEXP (setsrc, 0);
3305 rtx src_op1 = XEXP (setsrc, 1);
3307 /* Split "X = Y op Y" as "Z = Y; X = Z op Z". */
3308 if (rtx_equal_p (src_op0, src_op1))
3310 newi2pat = gen_rtx_SET (VOIDmode, newdest, src_op0);
3311 SUBST (XEXP (setsrc, 0), newdest);
3312 SUBST (XEXP (setsrc, 1), newdest);
3315 /* Split "((P op Q) op R) op S" where op is PLUS or MULT. */
3316 else if ((code == PLUS || code == MULT)
3317 && GET_CODE (src_op0) == code
3318 && GET_CODE (XEXP (src_op0, 0)) == code
3319 && (INTEGRAL_MODE_P (mode)
3320 || (FLOAT_MODE_P (mode)
3321 && flag_unsafe_math_optimizations)))
3323 rtx p = XEXP (XEXP (src_op0, 0), 0);
3324 rtx q = XEXP (XEXP (src_op0, 0), 1);
3325 rtx r = XEXP (src_op0, 1);
3328 /* Split both "((X op Y) op X) op Y" and
3329 "((X op Y) op Y) op X" as "T op T" where T is
3331 if ((rtx_equal_p (p,r) && rtx_equal_p (q,s))
3332 || (rtx_equal_p (p,s) && rtx_equal_p (q,r)))
3334 newi2pat = gen_rtx_SET (VOIDmode, newdest,
3336 SUBST (XEXP (setsrc, 0), newdest);
3337 SUBST (XEXP (setsrc, 1), newdest);
3340 /* Split "((X op X) op Y) op Y)" as "T op T" where
3342 else if (rtx_equal_p (p,q) && rtx_equal_p (r,s))
3344 rtx tmp = simplify_gen_binary (code, mode, p, r);
3345 newi2pat = gen_rtx_SET (VOIDmode, newdest, tmp);
3346 SUBST (XEXP (setsrc, 0), newdest);
3347 SUBST (XEXP (setsrc, 1), newdest);
3355 newi2pat = gen_rtx_SET (VOIDmode, newdest, *split);
3356 SUBST (*split, newdest);
3359 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
3361 /* recog_for_combine might have added CLOBBERs to newi2pat.
3362 Make sure NEWPAT does not depend on the clobbered regs. */
3363 if (GET_CODE (newi2pat) == PARALLEL)
3364 for (i = XVECLEN (newi2pat, 0) - 1; i >= 0; i--)
3365 if (GET_CODE (XVECEXP (newi2pat, 0, i)) == CLOBBER)
3367 rtx reg = XEXP (XVECEXP (newi2pat, 0, i), 0);
3368 if (reg_overlap_mentioned_p (reg, newpat))
3375 /* If the split point was a MULT and we didn't have one before,
3376 don't use one now. */
3377 if (i2_code_number >= 0 && ! (split_code == MULT && ! have_mult))
3378 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
3382 /* Check for a case where we loaded from memory in a narrow mode and
3383 then sign extended it, but we need both registers. In that case,
3384 we have a PARALLEL with both loads from the same memory location.
3385 We can split this into a load from memory followed by a register-register
3386 copy. This saves at least one insn, more if register allocation can
3389 We cannot do this if the destination of the first assignment is a
3390 condition code register or cc0. We eliminate this case by making sure
3391 the SET_DEST and SET_SRC have the same mode.
3393 We cannot do this if the destination of the second assignment is
3394 a register that we have already assumed is zero-extended. Similarly
3395 for a SUBREG of such a register. */
3397 else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0
3398 && GET_CODE (newpat) == PARALLEL
3399 && XVECLEN (newpat, 0) == 2
3400 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
3401 && GET_CODE (SET_SRC (XVECEXP (newpat, 0, 0))) == SIGN_EXTEND
3402 && (GET_MODE (SET_DEST (XVECEXP (newpat, 0, 0)))
3403 == GET_MODE (SET_SRC (XVECEXP (newpat, 0, 0))))
3404 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
3405 && rtx_equal_p (SET_SRC (XVECEXP (newpat, 0, 1)),
3406 XEXP (SET_SRC (XVECEXP (newpat, 0, 0)), 0))
3407 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)),
3409 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
3410 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
3411 && ! (temp = SET_DEST (XVECEXP (newpat, 0, 1)),
3413 && VEC_index (reg_stat_type, reg_stat,
3414 REGNO (temp))->nonzero_bits != 0
3415 && GET_MODE_BITSIZE (GET_MODE (temp)) < BITS_PER_WORD
3416 && GET_MODE_BITSIZE (GET_MODE (temp)) < HOST_BITS_PER_INT
3417 && (VEC_index (reg_stat_type, reg_stat,
3418 REGNO (temp))->nonzero_bits
3419 != GET_MODE_MASK (word_mode))))
3420 && ! (GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) == SUBREG
3421 && (temp = SUBREG_REG (SET_DEST (XVECEXP (newpat, 0, 1))),
3423 && VEC_index (reg_stat_type, reg_stat,
3424 REGNO (temp))->nonzero_bits != 0
3425 && GET_MODE_BITSIZE (GET_MODE (temp)) < BITS_PER_WORD
3426 && GET_MODE_BITSIZE (GET_MODE (temp)) < HOST_BITS_PER_INT
3427 && (VEC_index (reg_stat_type, reg_stat,
3428 REGNO (temp))->nonzero_bits
3429 != GET_MODE_MASK (word_mode)))))
3430 && ! reg_overlap_mentioned_p (SET_DEST (XVECEXP (newpat, 0, 1)),
3431 SET_SRC (XVECEXP (newpat, 0, 1)))
3432 && ! find_reg_note (i3, REG_UNUSED,
3433 SET_DEST (XVECEXP (newpat, 0, 0))))
3437 newi2pat = XVECEXP (newpat, 0, 0);
3438 ni2dest = SET_DEST (XVECEXP (newpat, 0, 0));
3439 newpat = XVECEXP (newpat, 0, 1);
3440 SUBST (SET_SRC (newpat),
3441 gen_lowpart (GET_MODE (SET_SRC (newpat)), ni2dest));
3442 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
3444 if (i2_code_number >= 0)
3445 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
3447 if (insn_code_number >= 0)
3451 /* Similarly, check for a case where we have a PARALLEL of two independent
3452 SETs but we started with three insns. In this case, we can do the sets
3453 as two separate insns. This case occurs when some SET allows two
3454 other insns to combine, but the destination of that SET is still live. */
3456 else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0
3457 && GET_CODE (newpat) == PARALLEL
3458 && XVECLEN (newpat, 0) == 2
3459 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
3460 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != ZERO_EXTRACT
3461 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != STRICT_LOW_PART
3462 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
3463 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
3464 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
3465 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)),
3467 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 1)),
3468 XVECEXP (newpat, 0, 0))
3469 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 0)),
3470 XVECEXP (newpat, 0, 1))
3471 && ! (contains_muldiv (SET_SRC (XVECEXP (newpat, 0, 0)))
3472 && contains_muldiv (SET_SRC (XVECEXP (newpat, 0, 1))))
3474 /* We cannot split the parallel into two sets if both sets
3476 && ! (reg_referenced_p (cc0_rtx, XVECEXP (newpat, 0, 0))
3477 && reg_referenced_p (cc0_rtx, XVECEXP (newpat, 0, 1)))
3481 /* Normally, it doesn't matter which of the two is done first,
3482 but it does if one references cc0. In that case, it has to
3485 if (reg_referenced_p (cc0_rtx, XVECEXP (newpat, 0, 0)))
3487 newi2pat = XVECEXP (newpat, 0, 0);
3488 newpat = XVECEXP (newpat, 0, 1);
3493 newi2pat = XVECEXP (newpat, 0, 1);
3494 newpat = XVECEXP (newpat, 0, 0);
3497 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
3499 if (i2_code_number >= 0)
3500 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
3503 /* If it still isn't recognized, fail and change things back the way they
3505 if ((insn_code_number < 0
3506 /* Is the result a reasonable ASM_OPERANDS? */
3507 && (! check_asm_operands (newpat) || added_sets_1 || added_sets_2)))
3513 /* If we had to change another insn, make sure it is valid also. */
3514 if (undobuf.other_insn)
3516 CLEAR_HARD_REG_SET (newpat_used_regs);
3518 other_pat = PATTERN (undobuf.other_insn);
3519 other_code_number = recog_for_combine (&other_pat, undobuf.other_insn,
3522 if (other_code_number < 0 && ! check_asm_operands (other_pat))
3530 /* If I2 is the CC0 setter and I3 is the CC0 user then check whether
3531 they are adjacent to each other or not. */
3533 rtx p = prev_nonnote_insn (i3);
3534 if (p && p != i2 && NONJUMP_INSN_P (p) && newi2pat
3535 && sets_cc0_p (newi2pat))
3543 /* Only allow this combination if insn_rtx_costs reports that the
3544 replacement instructions are cheaper than the originals. */
3545 if (!combine_validate_cost (i1, i2, i3, newpat, newi2pat, other_pat))
3551 if (MAY_HAVE_DEBUG_INSNS)
3555 for (undo = undobuf.undos; undo; undo = undo->next)
3556 if (undo->kind == UNDO_MODE)
3558 rtx reg = *undo->where.r;
3559 enum machine_mode new_mode = GET_MODE (reg);
3560 enum machine_mode old_mode = undo->old_contents.m;
3562 /* Temporarily revert mode back. */
3563 adjust_reg_mode (reg, old_mode);
3565 if (reg == i2dest && i2scratch)
3567 /* If we used i2dest as a scratch register with a
3568 different mode, substitute it for the original
3569 i2src while its original mode is temporarily
3570 restored, and then clear i2scratch so that we don't
3571 do it again later. */
3572 propagate_for_debug (i2, i3, reg, i2src, false);
3574 /* Put back the new mode. */
3575 adjust_reg_mode (reg, new_mode);
3579 rtx tempreg = gen_raw_REG (old_mode, REGNO (reg));
3590 last = undobuf.other_insn;
3594 /* We're dealing with a reg that changed mode but not
3595 meaning, so we want to turn it into a subreg for
3596 the new mode. However, because of REG sharing and
3597 because its mode had already changed, we have to do
3598 it in two steps. First, replace any debug uses of
3599 reg, with its original mode temporarily restored,
3600 with this copy we have created; then, replace the
3601 copy with the SUBREG of the original shared reg,
3602 once again changed to the new mode. */
3603 propagate_for_debug (first, last, reg, tempreg, false);
3604 adjust_reg_mode (reg, new_mode);
3605 propagate_for_debug (first, last, tempreg,
3606 lowpart_subreg (old_mode, reg, new_mode),
3612 /* If we will be able to accept this, we have made a
3613 change to the destination of I3. This requires us to
3614 do a few adjustments. */
3616 if (changed_i3_dest)
3618 PATTERN (i3) = newpat;
3619 adjust_for_new_dest (i3);
3622 /* We now know that we can do this combination. Merge the insns and
3623 update the status of registers and LOG_LINKS. */
3625 if (undobuf.other_insn)
3629 PATTERN (undobuf.other_insn) = other_pat;
3631 /* If any of the notes in OTHER_INSN were REG_UNUSED, ensure that they
3632 are still valid. Then add any non-duplicate notes added by
3633 recog_for_combine. */
3634 for (note = REG_NOTES (undobuf.other_insn); note; note = next)
3636 next = XEXP (note, 1);
3638 if (REG_NOTE_KIND (note) == REG_UNUSED
3639 && ! reg_set_p (XEXP (note, 0), PATTERN (undobuf.other_insn)))
3640 remove_note (undobuf.other_insn, note);
3643 distribute_notes (new_other_notes, undobuf.other_insn,
3644 undobuf.other_insn, NULL_RTX, NULL_RTX, NULL_RTX);
3653 /* I3 now uses what used to be its destination and which is now
3654 I2's destination. This requires us to do a few adjustments. */
3655 PATTERN (i3) = newpat;
3656 adjust_for_new_dest (i3);
3658 /* We need a LOG_LINK from I3 to I2. But we used to have one,
3661 However, some later insn might be using I2's dest and have
3662 a LOG_LINK pointing at I3. We must remove this link.
3663 The simplest way to remove the link is to point it at I1,
3664 which we know will be a NOTE. */
3666 /* newi2pat is usually a SET here; however, recog_for_combine might
3667 have added some clobbers. */
3668 if (GET_CODE (newi2pat) == PARALLEL)
3669 ni2dest = SET_DEST (XVECEXP (newi2pat, 0, 0));
3671 ni2dest = SET_DEST (newi2pat);
3673 for (insn = NEXT_INSN (i3);
3674 insn && (this_basic_block->next_bb == EXIT_BLOCK_PTR
3675 || insn != BB_HEAD (this_basic_block->next_bb));
3676 insn = NEXT_INSN (insn))
3678 if (INSN_P (insn) && reg_referenced_p (ni2dest, PATTERN (insn)))
3680 for (link = LOG_LINKS (insn); link;
3681 link = XEXP (link, 1))
3682 if (XEXP (link, 0) == i3)
3683 XEXP (link, 0) = i1;
3691 rtx i3notes, i2notes, i1notes = 0;
3692 rtx i3links, i2links, i1links = 0;
3695 /* Compute which registers we expect to eliminate. newi2pat may be setting
3696 either i3dest or i2dest, so we must check it. Also, i1dest may be the
3697 same as i3dest, in which case newi2pat may be setting i1dest. */
3698 rtx elim_i2 = ((newi2pat && reg_set_p (i2dest, newi2pat))
3699 || i2dest_in_i2src || i2dest_in_i1src
3702 rtx elim_i1 = (i1 == 0 || i1dest_in_i1src
3703 || (newi2pat && reg_set_p (i1dest, newi2pat))
3707 /* Get the old REG_NOTES and LOG_LINKS from all our insns and
3709 i3notes = REG_NOTES (i3), i3links = LOG_LINKS (i3);
3710 i2notes = REG_NOTES (i2), i2links = LOG_LINKS (i2);
3712 i1notes = REG_NOTES (i1), i1links = LOG_LINKS (i1);
3714 /* Ensure that we do not have something that should not be shared but
3715 occurs multiple times in the new insns. Check this by first
3716 resetting all the `used' flags and then copying anything is shared. */
3718 reset_used_flags (i3notes);
3719 reset_used_flags (i2notes);
3720 reset_used_flags (i1notes);
3721 reset_used_flags (newpat);
3722 reset_used_flags (newi2pat);
3723 if (undobuf.other_insn)
3724 reset_used_flags (PATTERN (undobuf.other_insn));
3726 i3notes = copy_rtx_if_shared (i3notes);
3727 i2notes = copy_rtx_if_shared (i2notes);
3728 i1notes = copy_rtx_if_shared (i1notes);
3729 newpat = copy_rtx_if_shared (newpat);
3730 newi2pat = copy_rtx_if_shared (newi2pat);
3731 if (undobuf.other_insn)
3732 reset_used_flags (PATTERN (undobuf.other_insn));
3734 INSN_CODE (i3) = insn_code_number;
3735 PATTERN (i3) = newpat;
3737 if (CALL_P (i3) && CALL_INSN_FUNCTION_USAGE (i3))
3739 rtx call_usage = CALL_INSN_FUNCTION_USAGE (i3);
3741 reset_used_flags (call_usage);
3742 call_usage = copy_rtx (call_usage);
3746 /* I2SRC must still be meaningful at this point. Some splitting
3747 operations can invalidate I2SRC, but those operations do not
3750 replace_rtx (call_usage, i2dest, i2src);
3754 replace_rtx (call_usage, i1dest, i1src);
3756 CALL_INSN_FUNCTION_USAGE (i3) = call_usage;
3759 if (undobuf.other_insn)
3760 INSN_CODE (undobuf.other_insn) = other_code_number;
3762 /* We had one special case above where I2 had more than one set and
3763 we replaced a destination of one of those sets with the destination
3764 of I3. In that case, we have to update LOG_LINKS of insns later
3765 in this basic block. Note that this (expensive) case is rare.
3767 Also, in this case, we must pretend that all REG_NOTEs for I2
3768 actually came from I3, so that REG_UNUSED notes from I2 will be
3769 properly handled. */
3771 if (i3_subst_into_i2)
3773 for (i = 0; i < XVECLEN (PATTERN (i2), 0); i++)
3774 if ((GET_CODE (XVECEXP (PATTERN (i2), 0, i)) == SET
3775 || GET_CODE (XVECEXP (PATTERN (i2), 0, i)) == CLOBBER)
3776 && REG_P (SET_DEST (XVECEXP (PATTERN (i2), 0, i)))
3777 && SET_DEST (XVECEXP (PATTERN (i2), 0, i)) != i2dest
3778 && ! find_reg_note (i2, REG_UNUSED,
3779 SET_DEST (XVECEXP (PATTERN (i2), 0, i))))
3780 for (temp = NEXT_INSN (i2);
3781 temp && (this_basic_block->next_bb == EXIT_BLOCK_PTR
3782 || BB_HEAD (this_basic_block) != temp);
3783 temp = NEXT_INSN (temp))
3784 if (temp != i3 && INSN_P (temp))
3785 for (link = LOG_LINKS (temp); link; link = XEXP (link, 1))
3786 if (XEXP (link, 0) == i2)
3787 XEXP (link, 0) = i3;
3792 while (XEXP (link, 1))
3793 link = XEXP (link, 1);
3794 XEXP (link, 1) = i2notes;
3808 if (MAY_HAVE_DEBUG_INSNS && i2scratch)
3809 propagate_for_debug (i2, i3, i2dest, i2src, false);
3810 INSN_CODE (i2) = i2_code_number;
3811 PATTERN (i2) = newi2pat;
3815 if (MAY_HAVE_DEBUG_INSNS && i2src)
3816 propagate_for_debug (i2, i3, i2dest, i2src, i3_subst_into_i2);
3817 SET_INSN_DELETED (i2);
3824 if (MAY_HAVE_DEBUG_INSNS)
3825 propagate_for_debug (i1, i3, i1dest, i1src, false);
3826 SET_INSN_DELETED (i1);
3829 /* Get death notes for everything that is now used in either I3 or
3830 I2 and used to die in a previous insn. If we built two new
3831 patterns, move from I1 to I2 then I2 to I3 so that we get the
3832 proper movement on registers that I2 modifies. */
3836 move_deaths (newi2pat, NULL_RTX, DF_INSN_LUID (i1), i2, &midnotes);
3837 move_deaths (newpat, newi2pat, DF_INSN_LUID (i1), i3, &midnotes);
3840 move_deaths (newpat, NULL_RTX, i1 ? DF_INSN_LUID (i1) : DF_INSN_LUID (i2),
3843 /* Distribute all the LOG_LINKS and REG_NOTES from I1, I2, and I3. */
3845 distribute_notes (i3notes, i3, i3, newi2pat ? i2 : NULL_RTX,
3848 distribute_notes (i2notes, i2, i3, newi2pat ? i2 : NULL_RTX,
3851 distribute_notes (i1notes, i1, i3, newi2pat ? i2 : NULL_RTX,
3854 distribute_notes (midnotes, NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
3857 /* Distribute any notes added to I2 or I3 by recog_for_combine. We
3858 know these are REG_UNUSED and want them to go to the desired insn,
3859 so we always pass it as i3. */
3861 if (newi2pat && new_i2_notes)
3862 distribute_notes (new_i2_notes, i2, i2, NULL_RTX, NULL_RTX, NULL_RTX);
3865 distribute_notes (new_i3_notes, i3, i3, NULL_RTX, NULL_RTX, NULL_RTX);
3867 /* If I3DEST was used in I3SRC, it really died in I3. We may need to
3868 put a REG_DEAD note for it somewhere. If NEWI2PAT exists and sets
3869 I3DEST, the death must be somewhere before I2, not I3. If we passed I3
3870 in that case, it might delete I2. Similarly for I2 and I1.
3871 Show an additional death due to the REG_DEAD note we make here. If
3872 we discard it in distribute_notes, we will decrement it again. */
3876 if (newi2pat && reg_set_p (i3dest_killed, newi2pat))
3877 distribute_notes (alloc_reg_note (REG_DEAD, i3dest_killed,
3879 NULL_RTX, i2, NULL_RTX, elim_i2, elim_i1);
3881 distribute_notes (alloc_reg_note (REG_DEAD, i3dest_killed,
3883 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
3887 if (i2dest_in_i2src)
3889 if (newi2pat && reg_set_p (i2dest, newi2pat))
3890 distribute_notes (alloc_reg_note (REG_DEAD, i2dest, NULL_RTX),
3891 NULL_RTX, i2, NULL_RTX, NULL_RTX, NULL_RTX);
3893 distribute_notes (alloc_reg_note (REG_DEAD, i2dest, NULL_RTX),
3894 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
3895 NULL_RTX, NULL_RTX);
3898 if (i1dest_in_i1src)
3900 if (newi2pat && reg_set_p (i1dest, newi2pat))
3901 distribute_notes (alloc_reg_note (REG_DEAD, i1dest, NULL_RTX),
3902 NULL_RTX, i2, NULL_RTX, NULL_RTX, NULL_RTX);
3904 distribute_notes (alloc_reg_note (REG_DEAD, i1dest, NULL_RTX),
3905 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
3906 NULL_RTX, NULL_RTX);
3909 distribute_links (i3links);
3910 distribute_links (i2links);
3911 distribute_links (i1links);
3916 rtx i2_insn = 0, i2_val = 0, set;
3918 /* The insn that used to set this register doesn't exist, and
3919 this life of the register may not exist either. See if one of
3920 I3's links points to an insn that sets I2DEST. If it does,
3921 that is now the last known value for I2DEST. If we don't update
3922 this and I2 set the register to a value that depended on its old
3923 contents, we will get confused. If this insn is used, thing
3924 will be set correctly in combine_instructions. */
3926 for (link = LOG_LINKS (i3); link; link = XEXP (link, 1))
3927 if ((set = single_set (XEXP (link, 0))) != 0
3928 && rtx_equal_p (i2dest, SET_DEST (set)))
3929 i2_insn = XEXP (link, 0), i2_val = SET_SRC (set);
3931 record_value_for_reg (i2dest, i2_insn, i2_val);
3933 /* If the reg formerly set in I2 died only once and that was in I3,
3934 zero its use count so it won't make `reload' do any work. */
3936 && (newi2pat == 0 || ! reg_mentioned_p (i2dest, newi2pat))
3937 && ! i2dest_in_i2src)
3939 regno = REGNO (i2dest);
3940 INC_REG_N_SETS (regno, -1);
3944 if (i1 && REG_P (i1dest))
3947 rtx i1_insn = 0, i1_val = 0, set;
3949 for (link = LOG_LINKS (i3); link; link = XEXP (link, 1))
3950 if ((set = single_set (XEXP (link, 0))) != 0
3951 && rtx_equal_p (i1dest, SET_DEST (set)))
3952 i1_insn = XEXP (link, 0), i1_val = SET_SRC (set);
3954 record_value_for_reg (i1dest, i1_insn, i1_val);
3956 regno = REGNO (i1dest);
3957 if (! added_sets_1 && ! i1dest_in_i1src)
3958 INC_REG_N_SETS (regno, -1);
3961 /* Update reg_stat[].nonzero_bits et al for any changes that may have
3962 been made to this insn. The order of
3963 set_nonzero_bits_and_sign_copies() is important. Because newi2pat
3964 can affect nonzero_bits of newpat */
3966 note_stores (newi2pat, set_nonzero_bits_and_sign_copies, NULL);
3967 note_stores (newpat, set_nonzero_bits_and_sign_copies, NULL);
3970 if (undobuf.other_insn != NULL_RTX)
3974 fprintf (dump_file, "modifying other_insn ");
3975 dump_insn_slim (dump_file, undobuf.other_insn);
3977 df_insn_rescan (undobuf.other_insn);
3980 if (i1 && !(NOTE_P(i1) && (NOTE_KIND (i1) == NOTE_INSN_DELETED)))
3984 fprintf (dump_file, "modifying insn i1 ");
3985 dump_insn_slim (dump_file, i1);
3987 df_insn_rescan (i1);
3990 if (i2 && !(NOTE_P(i2) && (NOTE_KIND (i2) == NOTE_INSN_DELETED)))
3994 fprintf (dump_file, "modifying insn i2 ");
3995 dump_insn_slim (dump_file, i2);
3997 df_insn_rescan (i2);
4000 if (i3 && !(NOTE_P(i3) && (NOTE_KIND (i3) == NOTE_INSN_DELETED)))
4004 fprintf (dump_file, "modifying insn i3 ");
4005 dump_insn_slim (dump_file, i3);
4007 df_insn_rescan (i3);
4010 /* Set new_direct_jump_p if a new return or simple jump instruction
4011 has been created. Adjust the CFG accordingly. */
4013 if (returnjump_p (i3) || any_uncondjump_p (i3))
4015 *new_direct_jump_p = 1;
4016 mark_jump_label (PATTERN (i3), i3, 0);
4017 update_cfg_for_uncondjump (i3);
4020 if (undobuf.other_insn != NULL_RTX
4021 && (returnjump_p (undobuf.other_insn)
4022 || any_uncondjump_p (undobuf.other_insn)))
4024 *new_direct_jump_p = 1;
4025 update_cfg_for_uncondjump (undobuf.other_insn);
4028 /* A noop might also need cleaning up of CFG, if it comes from the
4029 simplification of a jump. */
4030 if (GET_CODE (newpat) == SET
4031 && SET_SRC (newpat) == pc_rtx
4032 && SET_DEST (newpat) == pc_rtx)
4034 *new_direct_jump_p = 1;
4035 update_cfg_for_uncondjump (i3);
4038 combine_successes++;
4041 if (added_links_insn
4042 && (newi2pat == 0 || DF_INSN_LUID (added_links_insn) < DF_INSN_LUID (i2))
4043 && DF_INSN_LUID (added_links_insn) < DF_INSN_LUID (i3))
4044 return added_links_insn;
4046 return newi2pat ? i2 : i3;
4049 /* Undo all the modifications recorded in undobuf. */
4054 struct undo *undo, *next;
4056 for (undo = undobuf.undos; undo; undo = next)
4062 *undo->where.r = undo->old_contents.r;
4065 *undo->where.i = undo->old_contents.i;
4068 adjust_reg_mode (*undo->where.r, undo->old_contents.m);
4074 undo->next = undobuf.frees;
4075 undobuf.frees = undo;
4081 /* We've committed to accepting the changes we made. Move all
4082 of the undos to the free list. */
4087 struct undo *undo, *next;
4089 for (undo = undobuf.undos; undo; undo = next)
4092 undo->next = undobuf.frees;
4093 undobuf.frees = undo;
4098 /* Find the innermost point within the rtx at LOC, possibly LOC itself,
4099 where we have an arithmetic expression and return that point. LOC will
4102 try_combine will call this function to see if an insn can be split into
4106 find_split_point (rtx *loc, rtx insn, bool set_src)
4109 enum rtx_code code = GET_CODE (x);
4111 unsigned HOST_WIDE_INT len = 0;
4112 HOST_WIDE_INT pos = 0;
4114 rtx inner = NULL_RTX;
4116 /* First special-case some codes. */
4120 #ifdef INSN_SCHEDULING
4121 /* If we are making a paradoxical SUBREG invalid, it becomes a split
4123 if (MEM_P (SUBREG_REG (x)))
4126 return find_split_point (&SUBREG_REG (x), insn, false);
4130 /* If we have (mem (const ..)) or (mem (symbol_ref ...)), split it
4131 using LO_SUM and HIGH. */
4132 if (GET_CODE (XEXP (x, 0)) == CONST
4133 || GET_CODE (XEXP (x, 0)) == SYMBOL_REF)
4135 enum machine_mode address_mode
4136 = targetm.addr_space.address_mode (MEM_ADDR_SPACE (x));
4139 gen_rtx_LO_SUM (address_mode,
4140 gen_rtx_HIGH (address_mode, XEXP (x, 0)),
4142 return &XEXP (XEXP (x, 0), 0);
4146 /* If we have a PLUS whose second operand is a constant and the
4147 address is not valid, perhaps will can split it up using
4148 the machine-specific way to split large constants. We use
4149 the first pseudo-reg (one of the virtual regs) as a placeholder;
4150 it will not remain in the result. */
4151 if (GET_CODE (XEXP (x, 0)) == PLUS
4152 && CONST_INT_P (XEXP (XEXP (x, 0), 1))
4153 && ! memory_address_addr_space_p (GET_MODE (x), XEXP (x, 0),
4154 MEM_ADDR_SPACE (x)))
4156 rtx reg = regno_reg_rtx[FIRST_PSEUDO_REGISTER];
4157 rtx seq = combine_split_insns (gen_rtx_SET (VOIDmode, reg,
4161 /* This should have produced two insns, each of which sets our
4162 placeholder. If the source of the second is a valid address,
4163 we can make put both sources together and make a split point
4167 && NEXT_INSN (seq) != NULL_RTX
4168 && NEXT_INSN (NEXT_INSN (seq)) == NULL_RTX
4169 && NONJUMP_INSN_P (seq)
4170 && GET_CODE (PATTERN (seq)) == SET
4171 && SET_DEST (PATTERN (seq)) == reg
4172 && ! reg_mentioned_p (reg,
4173 SET_SRC (PATTERN (seq)))
4174 && NONJUMP_INSN_P (NEXT_INSN (seq))
4175 && GET_CODE (PATTERN (NEXT_INSN (seq))) == SET
4176 && SET_DEST (PATTERN (NEXT_INSN (seq))) == reg
4177 && memory_address_addr_space_p
4178 (GET_MODE (x), SET_SRC (PATTERN (NEXT_INSN (seq))),
4179 MEM_ADDR_SPACE (x)))
4181 rtx src1 = SET_SRC (PATTERN (seq));
4182 rtx src2 = SET_SRC (PATTERN (NEXT_INSN (seq)));
4184 /* Replace the placeholder in SRC2 with SRC1. If we can
4185 find where in SRC2 it was placed, that can become our
4186 split point and we can replace this address with SRC2.
4187 Just try two obvious places. */
4189 src2 = replace_rtx (src2, reg, src1);
4191 if (XEXP (src2, 0) == src1)
4192 split = &XEXP (src2, 0);
4193 else if (GET_RTX_FORMAT (GET_CODE (XEXP (src2, 0)))[0] == 'e'
4194 && XEXP (XEXP (src2, 0), 0) == src1)
4195 split = &XEXP (XEXP (src2, 0), 0);
4199 SUBST (XEXP (x, 0), src2);
4204 /* If that didn't work, perhaps the first operand is complex and
4205 needs to be computed separately, so make a split point there.
4206 This will occur on machines that just support REG + CONST
4207 and have a constant moved through some previous computation. */
4209 else if (!OBJECT_P (XEXP (XEXP (x, 0), 0))
4210 && ! (GET_CODE (XEXP (XEXP (x, 0), 0)) == SUBREG
4211 && OBJECT_P (SUBREG_REG (XEXP (XEXP (x, 0), 0)))))
4212 return &XEXP (XEXP (x, 0), 0);
4215 /* If we have a PLUS whose first operand is complex, try computing it
4216 separately by making a split there. */
4217 if (GET_CODE (XEXP (x, 0)) == PLUS
4218 && ! memory_address_addr_space_p (GET_MODE (x), XEXP (x, 0),
4220 && ! OBJECT_P (XEXP (XEXP (x, 0), 0))
4221 && ! (GET_CODE (XEXP (XEXP (x, 0), 0)) == SUBREG
4222 && OBJECT_P (SUBREG_REG (XEXP (XEXP (x, 0), 0)))))
4223 return &XEXP (XEXP (x, 0), 0);
4228 /* If SET_DEST is CC0 and SET_SRC is not an operand, a COMPARE, or a
4229 ZERO_EXTRACT, the most likely reason why this doesn't match is that
4230 we need to put the operand into a register. So split at that
4233 if (SET_DEST (x) == cc0_rtx
4234 && GET_CODE (SET_SRC (x)) != COMPARE
4235 && GET_CODE (SET_SRC (x)) != ZERO_EXTRACT
4236 && !OBJECT_P (SET_SRC (x))
4237 && ! (GET_CODE (SET_SRC (x)) == SUBREG
4238 && OBJECT_P (SUBREG_REG (SET_SRC (x)))))
4239 return &SET_SRC (x);
4242 /* See if we can split SET_SRC as it stands. */
4243 split = find_split_point (&SET_SRC (x), insn, true);
4244 if (split && split != &SET_SRC (x))
4247 /* See if we can split SET_DEST as it stands. */
4248 split = find_split_point (&SET_DEST (x), insn, false);
4249 if (split && split != &SET_DEST (x))
4252 /* See if this is a bitfield assignment with everything constant. If
4253 so, this is an IOR of an AND, so split it into that. */
4254 if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
4255 && (GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0)))
4256 <= HOST_BITS_PER_WIDE_INT)
4257 && CONST_INT_P (XEXP (SET_DEST (x), 1))
4258 && CONST_INT_P (XEXP (SET_DEST (x), 2))
4259 && CONST_INT_P (SET_SRC (x))
4260 && ((INTVAL (XEXP (SET_DEST (x), 1))
4261 + INTVAL (XEXP (SET_DEST (x), 2)))
4262 <= GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0))))
4263 && ! side_effects_p (XEXP (SET_DEST (x), 0)))
4265 HOST_WIDE_INT pos = INTVAL (XEXP (SET_DEST (x), 2));
4266 unsigned HOST_WIDE_INT len = INTVAL (XEXP (SET_DEST (x), 1));
4267 unsigned HOST_WIDE_INT src = INTVAL (SET_SRC (x));
4268 rtx dest = XEXP (SET_DEST (x), 0);
4269 enum machine_mode mode = GET_MODE (dest);
4270 unsigned HOST_WIDE_INT mask = ((HOST_WIDE_INT) 1 << len) - 1;
4273 if (BITS_BIG_ENDIAN)
4274 pos = GET_MODE_BITSIZE (mode) - len - pos;
4276 or_mask = gen_int_mode (src << pos, mode);
4279 simplify_gen_binary (IOR, mode, dest, or_mask));
4282 rtx negmask = gen_int_mode (~(mask << pos), mode);
4284 simplify_gen_binary (IOR, mode,
4285 simplify_gen_binary (AND, mode,
4290 SUBST (SET_DEST (x), dest);
4292 split = find_split_point (&SET_SRC (x), insn, true);
4293 if (split && split != &SET_SRC (x))
4297 /* Otherwise, see if this is an operation that we can split into two.
4298 If so, try to split that. */
4299 code = GET_CODE (SET_SRC (x));
4304 /* If we are AND'ing with a large constant that is only a single
4305 bit and the result is only being used in a context where we
4306 need to know if it is zero or nonzero, replace it with a bit
4307 extraction. This will avoid the large constant, which might
4308 have taken more than one insn to make. If the constant were
4309 not a valid argument to the AND but took only one insn to make,
4310 this is no worse, but if it took more than one insn, it will
4313 if (CONST_INT_P (XEXP (SET_SRC (x), 1))
4314 && REG_P (XEXP (SET_SRC (x), 0))
4315 && (pos = exact_log2 (INTVAL (XEXP (SET_SRC (x), 1)))) >= 7
4316 && REG_P (SET_DEST (x))
4317 && (split = find_single_use (SET_DEST (x), insn, (rtx*) 0)) != 0
4318 && (GET_CODE (*split) == EQ || GET_CODE (*split) == NE)
4319 && XEXP (*split, 0) == SET_DEST (x)
4320 && XEXP (*split, 1) == const0_rtx)
4322 rtx extraction = make_extraction (GET_MODE (SET_DEST (x)),
4323 XEXP (SET_SRC (x), 0),
4324 pos, NULL_RTX, 1, 1, 0, 0);
4325 if (extraction != 0)
4327 SUBST (SET_SRC (x), extraction);
4328 return find_split_point (loc, insn, false);
4334 /* If STORE_FLAG_VALUE is -1, this is (NE X 0) and only one bit of X
4335 is known to be on, this can be converted into a NEG of a shift. */
4336 if (STORE_FLAG_VALUE == -1 && XEXP (SET_SRC (x), 1) == const0_rtx
4337 && GET_MODE (SET_SRC (x)) == GET_MODE (XEXP (SET_SRC (x), 0))
4338 && 1 <= (pos = exact_log2
4339 (nonzero_bits (XEXP (SET_SRC (x), 0),
4340 GET_MODE (XEXP (SET_SRC (x), 0))))))
4342 enum machine_mode mode = GET_MODE (XEXP (SET_SRC (x), 0));
4346 gen_rtx_LSHIFTRT (mode,
4347 XEXP (SET_SRC (x), 0),
4350 split = find_split_point (&SET_SRC (x), insn, true);
4351 if (split && split != &SET_SRC (x))
4357 inner = XEXP (SET_SRC (x), 0);
4359 /* We can't optimize if either mode is a partial integer
4360 mode as we don't know how many bits are significant
4362 if (GET_MODE_CLASS (GET_MODE (inner)) == MODE_PARTIAL_INT
4363 || GET_MODE_CLASS (GET_MODE (SET_SRC (x))) == MODE_PARTIAL_INT)
4367 len = GET_MODE_BITSIZE (GET_MODE (inner));
4373 if (CONST_INT_P (XEXP (SET_SRC (x), 1))
4374 && CONST_INT_P (XEXP (SET_SRC (x), 2)))
4376 inner = XEXP (SET_SRC (x), 0);
4377 len = INTVAL (XEXP (SET_SRC (x), 1));
4378 pos = INTVAL (XEXP (SET_SRC (x), 2));
4380 if (BITS_BIG_ENDIAN)
4381 pos = GET_MODE_BITSIZE (GET_MODE (inner)) - len - pos;
4382 unsignedp = (code == ZERO_EXTRACT);
4390 if (len && pos >= 0 && pos + len <= GET_MODE_BITSIZE (GET_MODE (inner)))
4392 enum machine_mode mode = GET_MODE (SET_SRC (x));
4394 /* For unsigned, we have a choice of a shift followed by an
4395 AND or two shifts. Use two shifts for field sizes where the
4396 constant might be too large. We assume here that we can
4397 always at least get 8-bit constants in an AND insn, which is
4398 true for every current RISC. */
4400 if (unsignedp && len <= 8)
4405 (mode, gen_lowpart (mode, inner),
4407 GEN_INT (((HOST_WIDE_INT) 1 << len) - 1)));
4409 split = find_split_point (&SET_SRC (x), insn, true);
4410 if (split && split != &SET_SRC (x))
4417 (unsignedp ? LSHIFTRT : ASHIFTRT, mode,
4418 gen_rtx_ASHIFT (mode,
4419 gen_lowpart (mode, inner),
4420 GEN_INT (GET_MODE_BITSIZE (mode)
4422 GEN_INT (GET_MODE_BITSIZE (mode) - len)));
4424 split = find_split_point (&SET_SRC (x), insn, true);
4425 if (split && split != &SET_SRC (x))
4430 /* See if this is a simple operation with a constant as the second
4431 operand. It might be that this constant is out of range and hence
4432 could be used as a split point. */
4433 if (BINARY_P (SET_SRC (x))
4434 && CONSTANT_P (XEXP (SET_SRC (x), 1))
4435 && (OBJECT_P (XEXP (SET_SRC (x), 0))
4436 || (GET_CODE (XEXP (SET_SRC (x), 0)) == SUBREG
4437 && OBJECT_P (SUBREG_REG (XEXP (SET_SRC (x), 0))))))
4438 return &XEXP (SET_SRC (x), 1);
4440 /* Finally, see if this is a simple operation with its first operand
4441 not in a register. The operation might require this operand in a
4442 register, so return it as a split point. We can always do this
4443 because if the first operand were another operation, we would have
4444 already found it as a split point. */
4445 if ((BINARY_P (SET_SRC (x)) || UNARY_P (SET_SRC (x)))
4446 && ! register_operand (XEXP (SET_SRC (x), 0), VOIDmode))
4447 return &XEXP (SET_SRC (x), 0);
4453 /* We write NOR as (and (not A) (not B)), but if we don't have a NOR,
4454 it is better to write this as (not (ior A B)) so we can split it.
4455 Similarly for IOR. */
4456 if (GET_CODE (XEXP (x, 0)) == NOT && GET_CODE (XEXP (x, 1)) == NOT)
4459 gen_rtx_NOT (GET_MODE (x),
4460 gen_rtx_fmt_ee (code == IOR ? AND : IOR,
4462 XEXP (XEXP (x, 0), 0),
4463 XEXP (XEXP (x, 1), 0))));
4464 return find_split_point (loc, insn, set_src);
4467 /* Many RISC machines have a large set of logical insns. If the
4468 second operand is a NOT, put it first so we will try to split the
4469 other operand first. */
4470 if (GET_CODE (XEXP (x, 1)) == NOT)
4472 rtx tem = XEXP (x, 0);
4473 SUBST (XEXP (x, 0), XEXP (x, 1));
4474 SUBST (XEXP (x, 1), tem);
4480 /* Split at a multiply-accumulate instruction. However if this is
4481 the SET_SRC, we likely do not have such an instruction and it's
4482 worthless to try this split. */
4483 if (!set_src && GET_CODE (XEXP (x, 0)) == MULT)
4490 /* Otherwise, select our actions depending on our rtx class. */
4491 switch (GET_RTX_CLASS (code))
4493 case RTX_BITFIELD_OPS: /* This is ZERO_EXTRACT and SIGN_EXTRACT. */
4495 split = find_split_point (&XEXP (x, 2), insn, false);
4498 /* ... fall through ... */
4500 case RTX_COMM_ARITH:
4502 case RTX_COMM_COMPARE:
4503 split = find_split_point (&XEXP (x, 1), insn, false);
4506 /* ... fall through ... */
4508 /* Some machines have (and (shift ...) ...) insns. If X is not
4509 an AND, but XEXP (X, 0) is, use it as our split point. */
4510 if (GET_CODE (x) != AND && GET_CODE (XEXP (x, 0)) == AND)
4511 return &XEXP (x, 0);
4513 split = find_split_point (&XEXP (x, 0), insn, false);
4519 /* Otherwise, we don't have a split point. */
4524 /* Throughout X, replace FROM with TO, and return the result.
4525 The result is TO if X is FROM;
4526 otherwise the result is X, but its contents may have been modified.
4527 If they were modified, a record was made in undobuf so that
4528 undo_all will (among other things) return X to its original state.
4530 If the number of changes necessary is too much to record to undo,
4531 the excess changes are not made, so the result is invalid.
4532 The changes already made can still be undone.
4533 undobuf.num_undo is incremented for such changes, so by testing that
4534 the caller can tell whether the result is valid.
4536 `n_occurrences' is incremented each time FROM is replaced.
4538 IN_DEST is nonzero if we are processing the SET_DEST of a SET.
4540 UNIQUE_COPY is nonzero if each substitution must be unique. We do this
4541 by copying if `n_occurrences' is nonzero. */
4544 subst (rtx x, rtx from, rtx to, int in_dest, int unique_copy)
4546 enum rtx_code code = GET_CODE (x);
4547 enum machine_mode op0_mode = VOIDmode;
4552 /* Two expressions are equal if they are identical copies of a shared
4553 RTX or if they are both registers with the same register number
4556 #define COMBINE_RTX_EQUAL_P(X,Y) \
4558 || (REG_P (X) && REG_P (Y) \
4559 && REGNO (X) == REGNO (Y) && GET_MODE (X) == GET_MODE (Y)))
4561 if (! in_dest && COMBINE_RTX_EQUAL_P (x, from))
4564 return (unique_copy && n_occurrences > 1 ? copy_rtx (to) : to);
4567 /* If X and FROM are the same register but different modes, they
4568 will not have been seen as equal above. However, the log links code
4569 will make a LOG_LINKS entry for that case. If we do nothing, we
4570 will try to rerecognize our original insn and, when it succeeds,
4571 we will delete the feeding insn, which is incorrect.
4573 So force this insn not to match in this (rare) case. */
4574 if (! in_dest && code == REG && REG_P (from)
4575 && reg_overlap_mentioned_p (x, from))
4576 return gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
4578 /* If this is an object, we are done unless it is a MEM or LO_SUM, both
4579 of which may contain things that can be combined. */
4580 if (code != MEM && code != LO_SUM && OBJECT_P (x))
4583 /* It is possible to have a subexpression appear twice in the insn.
4584 Suppose that FROM is a register that appears within TO.
4585 Then, after that subexpression has been scanned once by `subst',
4586 the second time it is scanned, TO may be found. If we were
4587 to scan TO here, we would find FROM within it and create a
4588 self-referent rtl structure which is completely wrong. */
4589 if (COMBINE_RTX_EQUAL_P (x, to))
4592 /* Parallel asm_operands need special attention because all of the
4593 inputs are shared across the arms. Furthermore, unsharing the
4594 rtl results in recognition failures. Failure to handle this case
4595 specially can result in circular rtl.
4597 Solve this by doing a normal pass across the first entry of the
4598 parallel, and only processing the SET_DESTs of the subsequent
4601 if (code == PARALLEL
4602 && GET_CODE (XVECEXP (x, 0, 0)) == SET
4603 && GET_CODE (SET_SRC (XVECEXP (x, 0, 0))) == ASM_OPERANDS)
4605 new_rtx = subst (XVECEXP (x, 0, 0), from, to, 0, unique_copy);
4607 /* If this substitution failed, this whole thing fails. */
4608 if (GET_CODE (new_rtx) == CLOBBER
4609 && XEXP (new_rtx, 0) == const0_rtx)
4612 SUBST (XVECEXP (x, 0, 0), new_rtx);
4614 for (i = XVECLEN (x, 0) - 1; i >= 1; i--)
4616 rtx dest = SET_DEST (XVECEXP (x, 0, i));
4619 && GET_CODE (dest) != CC0
4620 && GET_CODE (dest) != PC)
4622 new_rtx = subst (dest, from, to, 0, unique_copy);
4624 /* If this substitution failed, this whole thing fails. */
4625 if (GET_CODE (new_rtx) == CLOBBER
4626 && XEXP (new_rtx, 0) == const0_rtx)
4629 SUBST (SET_DEST (XVECEXP (x, 0, i)), new_rtx);
4635 len = GET_RTX_LENGTH (code);
4636 fmt = GET_RTX_FORMAT (code);
4638 /* We don't need to process a SET_DEST that is a register, CC0,
4639 or PC, so set up to skip this common case. All other cases
4640 where we want to suppress replacing something inside a
4641 SET_SRC are handled via the IN_DEST operand. */
4643 && (REG_P (SET_DEST (x))
4644 || GET_CODE (SET_DEST (x)) == CC0
4645 || GET_CODE (SET_DEST (x)) == PC))
4648 /* Get the mode of operand 0 in case X is now a SIGN_EXTEND of a
4651 op0_mode = GET_MODE (XEXP (x, 0));
4653 for (i = 0; i < len; i++)
4658 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
4660 if (COMBINE_RTX_EQUAL_P (XVECEXP (x, i, j), from))
4662 new_rtx = (unique_copy && n_occurrences
4663 ? copy_rtx (to) : to);
4668 new_rtx = subst (XVECEXP (x, i, j), from, to, 0,
4671 /* If this substitution failed, this whole thing
4673 if (GET_CODE (new_rtx) == CLOBBER
4674 && XEXP (new_rtx, 0) == const0_rtx)
4678 SUBST (XVECEXP (x, i, j), new_rtx);
4681 else if (fmt[i] == 'e')
4683 /* If this is a register being set, ignore it. */
4684 new_rtx = XEXP (x, i);
4687 && (((code == SUBREG || code == ZERO_EXTRACT)
4689 || code == STRICT_LOW_PART))
4692 else if (COMBINE_RTX_EQUAL_P (XEXP (x, i), from))
4694 /* In general, don't install a subreg involving two
4695 modes not tieable. It can worsen register
4696 allocation, and can even make invalid reload
4697 insns, since the reg inside may need to be copied
4698 from in the outside mode, and that may be invalid
4699 if it is an fp reg copied in integer mode.
4701 We allow two exceptions to this: It is valid if
4702 it is inside another SUBREG and the mode of that
4703 SUBREG and the mode of the inside of TO is
4704 tieable and it is valid if X is a SET that copies
4707 if (GET_CODE (to) == SUBREG
4708 && ! MODES_TIEABLE_P (GET_MODE (to),
4709 GET_MODE (SUBREG_REG (to)))
4710 && ! (code == SUBREG
4711 && MODES_TIEABLE_P (GET_MODE (x),
4712 GET_MODE (SUBREG_REG (to))))
4714 && ! (code == SET && i == 1 && XEXP (x, 0) == cc0_rtx)
4717 return gen_rtx_CLOBBER (VOIDmode, const0_rtx);
4719 #ifdef CANNOT_CHANGE_MODE_CLASS
4722 && REGNO (to) < FIRST_PSEUDO_REGISTER
4723 && REG_CANNOT_CHANGE_MODE_P (REGNO (to),
4726 return gen_rtx_CLOBBER (VOIDmode, const0_rtx);
4729 new_rtx = (unique_copy && n_occurrences ? copy_rtx (to) : to);
4733 /* If we are in a SET_DEST, suppress most cases unless we
4734 have gone inside a MEM, in which case we want to
4735 simplify the address. We assume here that things that
4736 are actually part of the destination have their inner
4737 parts in the first expression. This is true for SUBREG,
4738 STRICT_LOW_PART, and ZERO_EXTRACT, which are the only
4739 things aside from REG and MEM that should appear in a
4741 new_rtx = subst (XEXP (x, i), from, to,
4743 && (code == SUBREG || code == STRICT_LOW_PART
4744 || code == ZERO_EXTRACT))
4746 && i == 0), unique_copy);
4748 /* If we found that we will have to reject this combination,
4749 indicate that by returning the CLOBBER ourselves, rather than
4750 an expression containing it. This will speed things up as
4751 well as prevent accidents where two CLOBBERs are considered
4752 to be equal, thus producing an incorrect simplification. */
4754 if (GET_CODE (new_rtx) == CLOBBER && XEXP (new_rtx, 0) == const0_rtx)
4757 if (GET_CODE (x) == SUBREG
4758 && (CONST_INT_P (new_rtx)
4759 || GET_CODE (new_rtx) == CONST_DOUBLE))
4761 enum machine_mode mode = GET_MODE (x);
4763 x = simplify_subreg (GET_MODE (x), new_rtx,
4764 GET_MODE (SUBREG_REG (x)),
4767 x = gen_rtx_CLOBBER (mode, const0_rtx);
4769 else if (CONST_INT_P (new_rtx)
4770 && GET_CODE (x) == ZERO_EXTEND)
4772 x = simplify_unary_operation (ZERO_EXTEND, GET_MODE (x),
4773 new_rtx, GET_MODE (XEXP (x, 0)));
4777 SUBST (XEXP (x, i), new_rtx);
4782 /* Check if we are loading something from the constant pool via float
4783 extension; in this case we would undo compress_float_constant
4784 optimization and degenerate constant load to an immediate value. */
4785 if (GET_CODE (x) == FLOAT_EXTEND
4786 && MEM_P (XEXP (x, 0))
4787 && MEM_READONLY_P (XEXP (x, 0)))
4789 rtx tmp = avoid_constant_pool_reference (x);
4794 /* Try to simplify X. If the simplification changed the code, it is likely
4795 that further simplification will help, so loop, but limit the number
4796 of repetitions that will be performed. */
4798 for (i = 0; i < 4; i++)
4800 /* If X is sufficiently simple, don't bother trying to do anything
4802 if (code != CONST_INT && code != REG && code != CLOBBER)
4803 x = combine_simplify_rtx (x, op0_mode, in_dest);
4805 if (GET_CODE (x) == code)
4808 code = GET_CODE (x);
4810 /* We no longer know the original mode of operand 0 since we
4811 have changed the form of X) */
4812 op0_mode = VOIDmode;
4818 /* Simplify X, a piece of RTL. We just operate on the expression at the
4819 outer level; call `subst' to simplify recursively. Return the new
4822 OP0_MODE is the original mode of XEXP (x, 0). IN_DEST is nonzero
4823 if we are inside a SET_DEST. */
4826 combine_simplify_rtx (rtx x, enum machine_mode op0_mode, int in_dest)
4828 enum rtx_code code = GET_CODE (x);
4829 enum machine_mode mode = GET_MODE (x);
4833 /* If this is a commutative operation, put a constant last and a complex
4834 expression first. We don't need to do this for comparisons here. */
4835 if (COMMUTATIVE_ARITH_P (x)
4836 && swap_commutative_operands_p (XEXP (x, 0), XEXP (x, 1)))
4839 SUBST (XEXP (x, 0), XEXP (x, 1));
4840 SUBST (XEXP (x, 1), temp);
4843 /* If this is a simple operation applied to an IF_THEN_ELSE, try
4844 applying it to the arms of the IF_THEN_ELSE. This often simplifies
4845 things. Check for cases where both arms are testing the same
4848 Don't do anything if all operands are very simple. */
4851 && ((!OBJECT_P (XEXP (x, 0))
4852 && ! (GET_CODE (XEXP (x, 0)) == SUBREG
4853 && OBJECT_P (SUBREG_REG (XEXP (x, 0)))))
4854 || (!OBJECT_P (XEXP (x, 1))
4855 && ! (GET_CODE (XEXP (x, 1)) == SUBREG
4856 && OBJECT_P (SUBREG_REG (XEXP (x, 1)))))))
4858 && (!OBJECT_P (XEXP (x, 0))
4859 && ! (GET_CODE (XEXP (x, 0)) == SUBREG
4860 && OBJECT_P (SUBREG_REG (XEXP (x, 0)))))))
4862 rtx cond, true_rtx, false_rtx;
4864 cond = if_then_else_cond (x, &true_rtx, &false_rtx);
4866 /* If everything is a comparison, what we have is highly unlikely
4867 to be simpler, so don't use it. */
4868 && ! (COMPARISON_P (x)
4869 && (COMPARISON_P (true_rtx) || COMPARISON_P (false_rtx))))
4871 rtx cop1 = const0_rtx;
4872 enum rtx_code cond_code = simplify_comparison (NE, &cond, &cop1);
4874 if (cond_code == NE && COMPARISON_P (cond))
4877 /* Simplify the alternative arms; this may collapse the true and
4878 false arms to store-flag values. Be careful to use copy_rtx
4879 here since true_rtx or false_rtx might share RTL with x as a
4880 result of the if_then_else_cond call above. */
4881 true_rtx = subst (copy_rtx (true_rtx), pc_rtx, pc_rtx, 0, 0);
4882 false_rtx = subst (copy_rtx (false_rtx), pc_rtx, pc_rtx, 0, 0);
4884 /* If true_rtx and false_rtx are not general_operands, an if_then_else
4885 is unlikely to be simpler. */
4886 if (general_operand (true_rtx, VOIDmode)
4887 && general_operand (false_rtx, VOIDmode))
4889 enum rtx_code reversed;
4891 /* Restarting if we generate a store-flag expression will cause
4892 us to loop. Just drop through in this case. */
4894 /* If the result values are STORE_FLAG_VALUE and zero, we can
4895 just make the comparison operation. */
4896 if (true_rtx == const_true_rtx && false_rtx == const0_rtx)
4897 x = simplify_gen_relational (cond_code, mode, VOIDmode,
4899 else if (true_rtx == const0_rtx && false_rtx == const_true_rtx
4900 && ((reversed = reversed_comparison_code_parts
4901 (cond_code, cond, cop1, NULL))
4903 x = simplify_gen_relational (reversed, mode, VOIDmode,
4906 /* Likewise, we can make the negate of a comparison operation
4907 if the result values are - STORE_FLAG_VALUE and zero. */
4908 else if (CONST_INT_P (true_rtx)
4909 && INTVAL (true_rtx) == - STORE_FLAG_VALUE
4910 && false_rtx == const0_rtx)
4911 x = simplify_gen_unary (NEG, mode,
4912 simplify_gen_relational (cond_code,
4916 else if (CONST_INT_P (false_rtx)
4917 && INTVAL (false_rtx) == - STORE_FLAG_VALUE
4918 && true_rtx == const0_rtx
4919 && ((reversed = reversed_comparison_code_parts
4920 (cond_code, cond, cop1, NULL))
4922 x = simplify_gen_unary (NEG, mode,
4923 simplify_gen_relational (reversed,
4928 return gen_rtx_IF_THEN_ELSE (mode,
4929 simplify_gen_relational (cond_code,
4934 true_rtx, false_rtx);
4936 code = GET_CODE (x);
4937 op0_mode = VOIDmode;
4942 /* Try to fold this expression in case we have constants that weren't
4945 switch (GET_RTX_CLASS (code))
4948 if (op0_mode == VOIDmode)
4949 op0_mode = GET_MODE (XEXP (x, 0));
4950 temp = simplify_unary_operation (code, mode, XEXP (x, 0), op0_mode);
4953 case RTX_COMM_COMPARE:
4955 enum machine_mode cmp_mode = GET_MODE (XEXP (x, 0));
4956 if (cmp_mode == VOIDmode)
4958 cmp_mode = GET_MODE (XEXP (x, 1));
4959 if (cmp_mode == VOIDmode)
4960 cmp_mode = op0_mode;
4962 temp = simplify_relational_operation (code, mode, cmp_mode,
4963 XEXP (x, 0), XEXP (x, 1));
4966 case RTX_COMM_ARITH:
4968 temp = simplify_binary_operation (code, mode, XEXP (x, 0), XEXP (x, 1));
4970 case RTX_BITFIELD_OPS:
4972 temp = simplify_ternary_operation (code, mode, op0_mode, XEXP (x, 0),
4973 XEXP (x, 1), XEXP (x, 2));
4982 code = GET_CODE (temp);
4983 op0_mode = VOIDmode;
4984 mode = GET_MODE (temp);
4987 /* First see if we can apply the inverse distributive law. */
4988 if (code == PLUS || code == MINUS
4989 || code == AND || code == IOR || code == XOR)
4991 x = apply_distributive_law (x);
4992 code = GET_CODE (x);
4993 op0_mode = VOIDmode;
4996 /* If CODE is an associative operation not otherwise handled, see if we
4997 can associate some operands. This can win if they are constants or
4998 if they are logically related (i.e. (a & b) & a). */
4999 if ((code == PLUS || code == MINUS || code == MULT || code == DIV
5000 || code == AND || code == IOR || code == XOR
5001 || code == SMAX || code == SMIN || code == UMAX || code == UMIN)
5002 && ((INTEGRAL_MODE_P (mode) && code != DIV)
5003 || (flag_associative_math && FLOAT_MODE_P (mode))))
5005 if (GET_CODE (XEXP (x, 0)) == code)
5007 rtx other = XEXP (XEXP (x, 0), 0);
5008 rtx inner_op0 = XEXP (XEXP (x, 0), 1);
5009 rtx inner_op1 = XEXP (x, 1);
5012 /* Make sure we pass the constant operand if any as the second
5013 one if this is a commutative operation. */
5014 if (CONSTANT_P (inner_op0) && COMMUTATIVE_ARITH_P (x))
5016 rtx tem = inner_op0;
5017 inner_op0 = inner_op1;
5020 inner = simplify_binary_operation (code == MINUS ? PLUS
5021 : code == DIV ? MULT
5023 mode, inner_op0, inner_op1);
5025 /* For commutative operations, try the other pair if that one
5027 if (inner == 0 && COMMUTATIVE_ARITH_P (x))
5029 other = XEXP (XEXP (x, 0), 1);
5030 inner = simplify_binary_operation (code, mode,
5031 XEXP (XEXP (x, 0), 0),
5036 return simplify_gen_binary (code, mode, other, inner);
5040 /* A little bit of algebraic simplification here. */
5044 /* Ensure that our address has any ASHIFTs converted to MULT in case
5045 address-recognizing predicates are called later. */
5046 temp = make_compound_operation (XEXP (x, 0), MEM);
5047 SUBST (XEXP (x, 0), temp);
5051 if (op0_mode == VOIDmode)
5052 op0_mode = GET_MODE (SUBREG_REG (x));
5054 /* See if this can be moved to simplify_subreg. */
5055 if (CONSTANT_P (SUBREG_REG (x))
5056 && subreg_lowpart_offset (mode, op0_mode) == SUBREG_BYTE (x)
5057 /* Don't call gen_lowpart if the inner mode
5058 is VOIDmode and we cannot simplify it, as SUBREG without
5059 inner mode is invalid. */
5060 && (GET_MODE (SUBREG_REG (x)) != VOIDmode
5061 || gen_lowpart_common (mode, SUBREG_REG (x))))
5062 return gen_lowpart (mode, SUBREG_REG (x));
5064 if (GET_MODE_CLASS (GET_MODE (SUBREG_REG (x))) == MODE_CC)
5068 temp = simplify_subreg (mode, SUBREG_REG (x), op0_mode,
5074 /* Don't change the mode of the MEM if that would change the meaning
5076 if (MEM_P (SUBREG_REG (x))
5077 && (MEM_VOLATILE_P (SUBREG_REG (x))
5078 || mode_dependent_address_p (XEXP (SUBREG_REG (x), 0))))
5079 return gen_rtx_CLOBBER (mode, const0_rtx);
5081 /* Note that we cannot do any narrowing for non-constants since
5082 we might have been counting on using the fact that some bits were
5083 zero. We now do this in the SET. */
5088 temp = expand_compound_operation (XEXP (x, 0));
5090 /* For C equal to the width of MODE minus 1, (neg (ashiftrt X C)) can be
5091 replaced by (lshiftrt X C). This will convert
5092 (neg (sign_extract X 1 Y)) to (zero_extract X 1 Y). */
5094 if (GET_CODE (temp) == ASHIFTRT
5095 && CONST_INT_P (XEXP (temp, 1))
5096 && INTVAL (XEXP (temp, 1)) == GET_MODE_BITSIZE (mode) - 1)
5097 return simplify_shift_const (NULL_RTX, LSHIFTRT, mode, XEXP (temp, 0),
5098 INTVAL (XEXP (temp, 1)));
5100 /* If X has only a single bit that might be nonzero, say, bit I, convert
5101 (neg X) to (ashiftrt (ashift X C-I) C-I) where C is the bitsize of
5102 MODE minus 1. This will convert (neg (zero_extract X 1 Y)) to
5103 (sign_extract X 1 Y). But only do this if TEMP isn't a register
5104 or a SUBREG of one since we'd be making the expression more
5105 complex if it was just a register. */
5108 && ! (GET_CODE (temp) == SUBREG
5109 && REG_P (SUBREG_REG (temp)))
5110 && (i = exact_log2 (nonzero_bits (temp, mode))) >= 0)
5112 rtx temp1 = simplify_shift_const
5113 (NULL_RTX, ASHIFTRT, mode,
5114 simplify_shift_const (NULL_RTX, ASHIFT, mode, temp,
5115 GET_MODE_BITSIZE (mode) - 1 - i),
5116 GET_MODE_BITSIZE (mode) - 1 - i);
5118 /* If all we did was surround TEMP with the two shifts, we
5119 haven't improved anything, so don't use it. Otherwise,
5120 we are better off with TEMP1. */
5121 if (GET_CODE (temp1) != ASHIFTRT
5122 || GET_CODE (XEXP (temp1, 0)) != ASHIFT
5123 || XEXP (XEXP (temp1, 0), 0) != temp)
5129 /* We can't handle truncation to a partial integer mode here
5130 because we don't know the real bitsize of the partial
5132 if (GET_MODE_CLASS (mode) == MODE_PARTIAL_INT)
5135 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
5137 force_to_mode (XEXP (x, 0), GET_MODE (XEXP (x, 0)),
5138 GET_MODE_MASK (mode), 0));
5140 /* We can truncate a constant value and return it. */
5141 if (CONST_INT_P (XEXP (x, 0)))
5142 return gen_int_mode (INTVAL (XEXP (x, 0)), mode);
5144 /* Similarly to what we do in simplify-rtx.c, a truncate of a register
5145 whose value is a comparison can be replaced with a subreg if
5146 STORE_FLAG_VALUE permits. */
5147 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5148 && ((HOST_WIDE_INT) STORE_FLAG_VALUE & ~GET_MODE_MASK (mode)) == 0
5149 && (temp = get_last_value (XEXP (x, 0)))
5150 && COMPARISON_P (temp))
5151 return gen_lowpart (mode, XEXP (x, 0));
5155 /* (const (const X)) can become (const X). Do it this way rather than
5156 returning the inner CONST since CONST can be shared with a
5158 if (GET_CODE (XEXP (x, 0)) == CONST)
5159 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
5164 /* Convert (lo_sum (high FOO) FOO) to FOO. This is necessary so we
5165 can add in an offset. find_split_point will split this address up
5166 again if it doesn't match. */
5167 if (GET_CODE (XEXP (x, 0)) == HIGH
5168 && rtx_equal_p (XEXP (XEXP (x, 0), 0), XEXP (x, 1)))
5174 /* (plus (xor (and <foo> (const_int pow2 - 1)) <c>) <-c>)
5175 when c is (const_int (pow2 + 1) / 2) is a sign extension of a
5176 bit-field and can be replaced by either a sign_extend or a
5177 sign_extract. The `and' may be a zero_extend and the two
5178 <c>, -<c> constants may be reversed. */
5179 if (GET_CODE (XEXP (x, 0)) == XOR
5180 && CONST_INT_P (XEXP (x, 1))
5181 && CONST_INT_P (XEXP (XEXP (x, 0), 1))
5182 && INTVAL (XEXP (x, 1)) == -INTVAL (XEXP (XEXP (x, 0), 1))
5183 && ((i = exact_log2 (INTVAL (XEXP (XEXP (x, 0), 1)))) >= 0
5184 || (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0)
5185 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5186 && ((GET_CODE (XEXP (XEXP (x, 0), 0)) == AND
5187 && CONST_INT_P (XEXP (XEXP (XEXP (x, 0), 0), 1))
5188 && (INTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1))
5189 == ((HOST_WIDE_INT) 1 << (i + 1)) - 1))
5190 || (GET_CODE (XEXP (XEXP (x, 0), 0)) == ZERO_EXTEND
5191 && (GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)))
5192 == (unsigned int) i + 1))))
5193 return simplify_shift_const
5194 (NULL_RTX, ASHIFTRT, mode,
5195 simplify_shift_const (NULL_RTX, ASHIFT, mode,
5196 XEXP (XEXP (XEXP (x, 0), 0), 0),
5197 GET_MODE_BITSIZE (mode) - (i + 1)),
5198 GET_MODE_BITSIZE (mode) - (i + 1));
5200 /* If only the low-order bit of X is possibly nonzero, (plus x -1)
5201 can become (ashiftrt (ashift (xor x 1) C) C) where C is
5202 the bitsize of the mode - 1. This allows simplification of
5203 "a = (b & 8) == 0;" */
5204 if (XEXP (x, 1) == constm1_rtx
5205 && !REG_P (XEXP (x, 0))
5206 && ! (GET_CODE (XEXP (x, 0)) == SUBREG
5207 && REG_P (SUBREG_REG (XEXP (x, 0))))
5208 && nonzero_bits (XEXP (x, 0), mode) == 1)
5209 return simplify_shift_const (NULL_RTX, ASHIFTRT, mode,
5210 simplify_shift_const (NULL_RTX, ASHIFT, mode,
5211 gen_rtx_XOR (mode, XEXP (x, 0), const1_rtx),
5212 GET_MODE_BITSIZE (mode) - 1),
5213 GET_MODE_BITSIZE (mode) - 1);
5215 /* If we are adding two things that have no bits in common, convert
5216 the addition into an IOR. This will often be further simplified,
5217 for example in cases like ((a & 1) + (a & 2)), which can
5220 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5221 && (nonzero_bits (XEXP (x, 0), mode)
5222 & nonzero_bits (XEXP (x, 1), mode)) == 0)
5224 /* Try to simplify the expression further. */
5225 rtx tor = simplify_gen_binary (IOR, mode, XEXP (x, 0), XEXP (x, 1));
5226 temp = combine_simplify_rtx (tor, mode, in_dest);
5228 /* If we could, great. If not, do not go ahead with the IOR
5229 replacement, since PLUS appears in many special purpose
5230 address arithmetic instructions. */
5231 if (GET_CODE (temp) != CLOBBER && temp != tor)
5237 /* (minus <foo> (and <foo> (const_int -pow2))) becomes
5238 (and <foo> (const_int pow2-1)) */
5239 if (GET_CODE (XEXP (x, 1)) == AND
5240 && CONST_INT_P (XEXP (XEXP (x, 1), 1))
5241 && exact_log2 (-INTVAL (XEXP (XEXP (x, 1), 1))) >= 0
5242 && rtx_equal_p (XEXP (XEXP (x, 1), 0), XEXP (x, 0)))
5243 return simplify_and_const_int (NULL_RTX, mode, XEXP (x, 0),
5244 -INTVAL (XEXP (XEXP (x, 1), 1)) - 1);
5248 /* If we have (mult (plus A B) C), apply the distributive law and then
5249 the inverse distributive law to see if things simplify. This
5250 occurs mostly in addresses, often when unrolling loops. */
5252 if (GET_CODE (XEXP (x, 0)) == PLUS)
5254 rtx result = distribute_and_simplify_rtx (x, 0);
5259 /* Try simplify a*(b/c) as (a*b)/c. */
5260 if (FLOAT_MODE_P (mode) && flag_associative_math
5261 && GET_CODE (XEXP (x, 0)) == DIV)
5263 rtx tem = simplify_binary_operation (MULT, mode,
5264 XEXP (XEXP (x, 0), 0),
5267 return simplify_gen_binary (DIV, mode, tem, XEXP (XEXP (x, 0), 1));
5272 /* If this is a divide by a power of two, treat it as a shift if
5273 its first operand is a shift. */
5274 if (CONST_INT_P (XEXP (x, 1))
5275 && (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0
5276 && (GET_CODE (XEXP (x, 0)) == ASHIFT
5277 || GET_CODE (XEXP (x, 0)) == LSHIFTRT
5278 || GET_CODE (XEXP (x, 0)) == ASHIFTRT
5279 || GET_CODE (XEXP (x, 0)) == ROTATE
5280 || GET_CODE (XEXP (x, 0)) == ROTATERT))
5281 return simplify_shift_const (NULL_RTX, LSHIFTRT, mode, XEXP (x, 0), i);
5285 case GT: case GTU: case GE: case GEU:
5286 case LT: case LTU: case LE: case LEU:
5287 case UNEQ: case LTGT:
5288 case UNGT: case UNGE:
5289 case UNLT: case UNLE:
5290 case UNORDERED: case ORDERED:
5291 /* If the first operand is a condition code, we can't do anything
5293 if (GET_CODE (XEXP (x, 0)) == COMPARE
5294 || (GET_MODE_CLASS (GET_MODE (XEXP (x, 0))) != MODE_CC
5295 && ! CC0_P (XEXP (x, 0))))
5297 rtx op0 = XEXP (x, 0);
5298 rtx op1 = XEXP (x, 1);
5299 enum rtx_code new_code;
5301 if (GET_CODE (op0) == COMPARE)
5302 op1 = XEXP (op0, 1), op0 = XEXP (op0, 0);
5304 /* Simplify our comparison, if possible. */
5305 new_code = simplify_comparison (code, &op0, &op1);
5307 /* If STORE_FLAG_VALUE is 1, we can convert (ne x 0) to simply X
5308 if only the low-order bit is possibly nonzero in X (such as when
5309 X is a ZERO_EXTRACT of one bit). Similarly, we can convert EQ to
5310 (xor X 1) or (minus 1 X); we use the former. Finally, if X is
5311 known to be either 0 or -1, NE becomes a NEG and EQ becomes
5314 Remove any ZERO_EXTRACT we made when thinking this was a
5315 comparison. It may now be simpler to use, e.g., an AND. If a
5316 ZERO_EXTRACT is indeed appropriate, it will be placed back by
5317 the call to make_compound_operation in the SET case. */
5319 if (STORE_FLAG_VALUE == 1
5320 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
5321 && op1 == const0_rtx
5322 && mode == GET_MODE (op0)
5323 && nonzero_bits (op0, mode) == 1)
5324 return gen_lowpart (mode,
5325 expand_compound_operation (op0));
5327 else if (STORE_FLAG_VALUE == 1
5328 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
5329 && op1 == const0_rtx
5330 && mode == GET_MODE (op0)
5331 && (num_sign_bit_copies (op0, mode)
5332 == GET_MODE_BITSIZE (mode)))
5334 op0 = expand_compound_operation (op0);
5335 return simplify_gen_unary (NEG, mode,
5336 gen_lowpart (mode, op0),
5340 else if (STORE_FLAG_VALUE == 1
5341 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
5342 && op1 == const0_rtx
5343 && mode == GET_MODE (op0)
5344 && nonzero_bits (op0, mode) == 1)
5346 op0 = expand_compound_operation (op0);
5347 return simplify_gen_binary (XOR, mode,
5348 gen_lowpart (mode, op0),
5352 else if (STORE_FLAG_VALUE == 1
5353 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
5354 && op1 == const0_rtx
5355 && mode == GET_MODE (op0)
5356 && (num_sign_bit_copies (op0, mode)
5357 == GET_MODE_BITSIZE (mode)))
5359 op0 = expand_compound_operation (op0);
5360 return plus_constant (gen_lowpart (mode, op0), 1);
5363 /* If STORE_FLAG_VALUE is -1, we have cases similar to
5365 if (STORE_FLAG_VALUE == -1
5366 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
5367 && op1 == const0_rtx
5368 && (num_sign_bit_copies (op0, mode)
5369 == GET_MODE_BITSIZE (mode)))
5370 return gen_lowpart (mode,
5371 expand_compound_operation (op0));
5373 else if (STORE_FLAG_VALUE == -1
5374 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
5375 && op1 == const0_rtx
5376 && mode == GET_MODE (op0)
5377 && nonzero_bits (op0, mode) == 1)
5379 op0 = expand_compound_operation (op0);
5380 return simplify_gen_unary (NEG, mode,
5381 gen_lowpart (mode, op0),
5385 else if (STORE_FLAG_VALUE == -1
5386 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
5387 && op1 == const0_rtx
5388 && mode == GET_MODE (op0)
5389 && (num_sign_bit_copies (op0, mode)
5390 == GET_MODE_BITSIZE (mode)))
5392 op0 = expand_compound_operation (op0);
5393 return simplify_gen_unary (NOT, mode,
5394 gen_lowpart (mode, op0),
5398 /* If X is 0/1, (eq X 0) is X-1. */
5399 else if (STORE_FLAG_VALUE == -1
5400 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
5401 && op1 == const0_rtx
5402 && mode == GET_MODE (op0)
5403 && nonzero_bits (op0, mode) == 1)
5405 op0 = expand_compound_operation (op0);
5406 return plus_constant (gen_lowpart (mode, op0), -1);
5409 /* If STORE_FLAG_VALUE says to just test the sign bit and X has just
5410 one bit that might be nonzero, we can convert (ne x 0) to
5411 (ashift x c) where C puts the bit in the sign bit. Remove any
5412 AND with STORE_FLAG_VALUE when we are done, since we are only
5413 going to test the sign bit. */
5414 if (new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
5415 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5416 && ((STORE_FLAG_VALUE & GET_MODE_MASK (mode))
5417 == (unsigned HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (mode) - 1))
5418 && op1 == const0_rtx
5419 && mode == GET_MODE (op0)
5420 && (i = exact_log2 (nonzero_bits (op0, mode))) >= 0)
5422 x = simplify_shift_const (NULL_RTX, ASHIFT, mode,
5423 expand_compound_operation (op0),
5424 GET_MODE_BITSIZE (mode) - 1 - i);
5425 if (GET_CODE (x) == AND && XEXP (x, 1) == const_true_rtx)
5431 /* If the code changed, return a whole new comparison. */
5432 if (new_code != code)
5433 return gen_rtx_fmt_ee (new_code, mode, op0, op1);
5435 /* Otherwise, keep this operation, but maybe change its operands.
5436 This also converts (ne (compare FOO BAR) 0) to (ne FOO BAR). */
5437 SUBST (XEXP (x, 0), op0);
5438 SUBST (XEXP (x, 1), op1);
5443 return simplify_if_then_else (x);
5449 /* If we are processing SET_DEST, we are done. */
5453 return expand_compound_operation (x);
5456 return simplify_set (x);
5460 return simplify_logical (x);
5467 /* If this is a shift by a constant amount, simplify it. */
5468 if (CONST_INT_P (XEXP (x, 1)))
5469 return simplify_shift_const (x, code, mode, XEXP (x, 0),
5470 INTVAL (XEXP (x, 1)));
5472 else if (SHIFT_COUNT_TRUNCATED && !REG_P (XEXP (x, 1)))
5474 force_to_mode (XEXP (x, 1), GET_MODE (XEXP (x, 1)),
5476 << exact_log2 (GET_MODE_BITSIZE (GET_MODE (x))))
5488 /* Simplify X, an IF_THEN_ELSE expression. Return the new expression. */
5491 simplify_if_then_else (rtx x)
5493 enum machine_mode mode = GET_MODE (x);
5494 rtx cond = XEXP (x, 0);
5495 rtx true_rtx = XEXP (x, 1);
5496 rtx false_rtx = XEXP (x, 2);
5497 enum rtx_code true_code = GET_CODE (cond);
5498 int comparison_p = COMPARISON_P (cond);
5501 enum rtx_code false_code;
5504 /* Simplify storing of the truth value. */
5505 if (comparison_p && true_rtx == const_true_rtx && false_rtx == const0_rtx)
5506 return simplify_gen_relational (true_code, mode, VOIDmode,
5507 XEXP (cond, 0), XEXP (cond, 1));
5509 /* Also when the truth value has to be reversed. */
5511 && true_rtx == const0_rtx && false_rtx == const_true_rtx
5512 && (reversed = reversed_comparison (cond, mode)))
5515 /* Sometimes we can simplify the arm of an IF_THEN_ELSE if a register used
5516 in it is being compared against certain values. Get the true and false
5517 comparisons and see if that says anything about the value of each arm. */
5520 && ((false_code = reversed_comparison_code (cond, NULL))
5522 && REG_P (XEXP (cond, 0)))
5525 rtx from = XEXP (cond, 0);
5526 rtx true_val = XEXP (cond, 1);
5527 rtx false_val = true_val;
5530 /* If FALSE_CODE is EQ, swap the codes and arms. */
5532 if (false_code == EQ)
5534 swapped = 1, true_code = EQ, false_code = NE;
5535 temp = true_rtx, true_rtx = false_rtx, false_rtx = temp;
5538 /* If we are comparing against zero and the expression being tested has
5539 only a single bit that might be nonzero, that is its value when it is
5540 not equal to zero. Similarly if it is known to be -1 or 0. */
5542 if (true_code == EQ && true_val == const0_rtx
5543 && exact_log2 (nzb = nonzero_bits (from, GET_MODE (from))) >= 0)
5546 false_val = GEN_INT (trunc_int_for_mode (nzb, GET_MODE (from)));
5548 else if (true_code == EQ && true_val == const0_rtx
5549 && (num_sign_bit_copies (from, GET_MODE (from))
5550 == GET_MODE_BITSIZE (GET_MODE (from))))
5553 false_val = constm1_rtx;
5556 /* Now simplify an arm if we know the value of the register in the
5557 branch and it is used in the arm. Be careful due to the potential
5558 of locally-shared RTL. */
5560 if (reg_mentioned_p (from, true_rtx))
5561 true_rtx = subst (known_cond (copy_rtx (true_rtx), true_code,
5563 pc_rtx, pc_rtx, 0, 0);
5564 if (reg_mentioned_p (from, false_rtx))
5565 false_rtx = subst (known_cond (copy_rtx (false_rtx), false_code,
5567 pc_rtx, pc_rtx, 0, 0);
5569 SUBST (XEXP (x, 1), swapped ? false_rtx : true_rtx);
5570 SUBST (XEXP (x, 2), swapped ? true_rtx : false_rtx);
5572 true_rtx = XEXP (x, 1);
5573 false_rtx = XEXP (x, 2);
5574 true_code = GET_CODE (cond);
5577 /* If we have (if_then_else FOO (pc) (label_ref BAR)) and FOO can be
5578 reversed, do so to avoid needing two sets of patterns for
5579 subtract-and-branch insns. Similarly if we have a constant in the true
5580 arm, the false arm is the same as the first operand of the comparison, or
5581 the false arm is more complicated than the true arm. */
5584 && reversed_comparison_code (cond, NULL) != UNKNOWN
5585 && (true_rtx == pc_rtx
5586 || (CONSTANT_P (true_rtx)
5587 && !CONST_INT_P (false_rtx) && false_rtx != pc_rtx)
5588 || true_rtx == const0_rtx
5589 || (OBJECT_P (true_rtx) && !OBJECT_P (false_rtx))
5590 || (GET_CODE (true_rtx) == SUBREG && OBJECT_P (SUBREG_REG (true_rtx))
5591 && !OBJECT_P (false_rtx))
5592 || reg_mentioned_p (true_rtx, false_rtx)
5593 || rtx_equal_p (false_rtx, XEXP (cond, 0))))
5595 true_code = reversed_comparison_code (cond, NULL);
5596 SUBST (XEXP (x, 0), reversed_comparison (cond, GET_MODE (cond)));
5597 SUBST (XEXP (x, 1), false_rtx);
5598 SUBST (XEXP (x, 2), true_rtx);
5600 temp = true_rtx, true_rtx = false_rtx, false_rtx = temp;
5603 /* It is possible that the conditional has been simplified out. */
5604 true_code = GET_CODE (cond);
5605 comparison_p = COMPARISON_P (cond);
5608 /* If the two arms are identical, we don't need the comparison. */
5610 if (rtx_equal_p (true_rtx, false_rtx) && ! side_effects_p (cond))
5613 /* Convert a == b ? b : a to "a". */
5614 if (true_code == EQ && ! side_effects_p (cond)
5615 && !HONOR_NANS (mode)
5616 && rtx_equal_p (XEXP (cond, 0), false_rtx)
5617 && rtx_equal_p (XEXP (cond, 1), true_rtx))
5619 else if (true_code == NE && ! side_effects_p (cond)
5620 && !HONOR_NANS (mode)
5621 && rtx_equal_p (XEXP (cond, 0), true_rtx)
5622 && rtx_equal_p (XEXP (cond, 1), false_rtx))
5625 /* Look for cases where we have (abs x) or (neg (abs X)). */
5627 if (GET_MODE_CLASS (mode) == MODE_INT
5629 && XEXP (cond, 1) == const0_rtx
5630 && GET_CODE (false_rtx) == NEG
5631 && rtx_equal_p (true_rtx, XEXP (false_rtx, 0))
5632 && rtx_equal_p (true_rtx, XEXP (cond, 0))
5633 && ! side_effects_p (true_rtx))
5638 return simplify_gen_unary (ABS, mode, true_rtx, mode);
5642 simplify_gen_unary (NEG, mode,
5643 simplify_gen_unary (ABS, mode, true_rtx, mode),
5649 /* Look for MIN or MAX. */
5651 if ((! FLOAT_MODE_P (mode) || flag_unsafe_math_optimizations)
5653 && rtx_equal_p (XEXP (cond, 0), true_rtx)
5654 && rtx_equal_p (XEXP (cond, 1), false_rtx)
5655 && ! side_effects_p (cond))
5660 return simplify_gen_binary (SMAX, mode, true_rtx, false_rtx);
5663 return simplify_gen_binary (SMIN, mode, true_rtx, false_rtx);
5666 return simplify_gen_binary (UMAX, mode, true_rtx, false_rtx);
5669 return simplify_gen_binary (UMIN, mode, true_rtx, false_rtx);
5674 /* If we have (if_then_else COND (OP Z C1) Z) and OP is an identity when its
5675 second operand is zero, this can be done as (OP Z (mult COND C2)) where
5676 C2 = C1 * STORE_FLAG_VALUE. Similarly if OP has an outer ZERO_EXTEND or
5677 SIGN_EXTEND as long as Z is already extended (so we don't destroy it).
5678 We can do this kind of thing in some cases when STORE_FLAG_VALUE is
5679 neither 1 or -1, but it isn't worth checking for. */
5681 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
5683 && GET_MODE_CLASS (mode) == MODE_INT
5684 && ! side_effects_p (x))
5686 rtx t = make_compound_operation (true_rtx, SET);
5687 rtx f = make_compound_operation (false_rtx, SET);
5688 rtx cond_op0 = XEXP (cond, 0);
5689 rtx cond_op1 = XEXP (cond, 1);
5690 enum rtx_code op = UNKNOWN, extend_op = UNKNOWN;
5691 enum machine_mode m = mode;
5692 rtx z = 0, c1 = NULL_RTX;
5694 if ((GET_CODE (t) == PLUS || GET_CODE (t) == MINUS
5695 || GET_CODE (t) == IOR || GET_CODE (t) == XOR
5696 || GET_CODE (t) == ASHIFT
5697 || GET_CODE (t) == LSHIFTRT || GET_CODE (t) == ASHIFTRT)
5698 && rtx_equal_p (XEXP (t, 0), f))
5699 c1 = XEXP (t, 1), op = GET_CODE (t), z = f;
5701 /* If an identity-zero op is commutative, check whether there
5702 would be a match if we swapped the operands. */
5703 else if ((GET_CODE (t) == PLUS || GET_CODE (t) == IOR
5704 || GET_CODE (t) == XOR)
5705 && rtx_equal_p (XEXP (t, 1), f))
5706 c1 = XEXP (t, 0), op = GET_CODE (t), z = f;
5707 else if (GET_CODE (t) == SIGN_EXTEND
5708 && (GET_CODE (XEXP (t, 0)) == PLUS
5709 || GET_CODE (XEXP (t, 0)) == MINUS
5710 || GET_CODE (XEXP (t, 0)) == IOR
5711 || GET_CODE (XEXP (t, 0)) == XOR
5712 || GET_CODE (XEXP (t, 0)) == ASHIFT
5713 || GET_CODE (XEXP (t, 0)) == LSHIFTRT
5714 || GET_CODE (XEXP (t, 0)) == ASHIFTRT)
5715 && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG
5716 && subreg_lowpart_p (XEXP (XEXP (t, 0), 0))
5717 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f)
5718 && (num_sign_bit_copies (f, GET_MODE (f))
5720 (GET_MODE_BITSIZE (mode)
5721 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t, 0), 0))))))
5723 c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0));
5724 extend_op = SIGN_EXTEND;
5725 m = GET_MODE (XEXP (t, 0));
5727 else if (GET_CODE (t) == SIGN_EXTEND
5728 && (GET_CODE (XEXP (t, 0)) == PLUS
5729 || GET_CODE (XEXP (t, 0)) == IOR
5730 || GET_CODE (XEXP (t, 0)) == XOR)
5731 && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG
5732 && subreg_lowpart_p (XEXP (XEXP (t, 0), 1))
5733 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f)
5734 && (num_sign_bit_copies (f, GET_MODE (f))
5736 (GET_MODE_BITSIZE (mode)
5737 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t, 0), 1))))))
5739 c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0));
5740 extend_op = SIGN_EXTEND;
5741 m = GET_MODE (XEXP (t, 0));
5743 else if (GET_CODE (t) == ZERO_EXTEND
5744 && (GET_CODE (XEXP (t, 0)) == PLUS
5745 || GET_CODE (XEXP (t, 0)) == MINUS
5746 || GET_CODE (XEXP (t, 0)) == IOR
5747 || GET_CODE (XEXP (t, 0)) == XOR
5748 || GET_CODE (XEXP (t, 0)) == ASHIFT
5749 || GET_CODE (XEXP (t, 0)) == LSHIFTRT
5750 || GET_CODE (XEXP (t, 0)) == ASHIFTRT)
5751 && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG
5752 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5753 && subreg_lowpart_p (XEXP (XEXP (t, 0), 0))
5754 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f)
5755 && ((nonzero_bits (f, GET_MODE (f))
5756 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t, 0), 0))))
5759 c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0));
5760 extend_op = ZERO_EXTEND;
5761 m = GET_MODE (XEXP (t, 0));
5763 else if (GET_CODE (t) == ZERO_EXTEND
5764 && (GET_CODE (XEXP (t, 0)) == PLUS
5765 || GET_CODE (XEXP (t, 0)) == IOR
5766 || GET_CODE (XEXP (t, 0)) == XOR)
5767 && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG
5768 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5769 && subreg_lowpart_p (XEXP (XEXP (t, 0), 1))
5770 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f)
5771 && ((nonzero_bits (f, GET_MODE (f))
5772 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t, 0), 1))))
5775 c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0));
5776 extend_op = ZERO_EXTEND;
5777 m = GET_MODE (XEXP (t, 0));
5782 temp = subst (simplify_gen_relational (true_code, m, VOIDmode,
5783 cond_op0, cond_op1),
5784 pc_rtx, pc_rtx, 0, 0);
5785 temp = simplify_gen_binary (MULT, m, temp,
5786 simplify_gen_binary (MULT, m, c1,
5788 temp = subst (temp, pc_rtx, pc_rtx, 0, 0);
5789 temp = simplify_gen_binary (op, m, gen_lowpart (m, z), temp);
5791 if (extend_op != UNKNOWN)
5792 temp = simplify_gen_unary (extend_op, mode, temp, m);
5798 /* If we have (if_then_else (ne A 0) C1 0) and either A is known to be 0 or
5799 1 and C1 is a single bit or A is known to be 0 or -1 and C1 is the
5800 negation of a single bit, we can convert this operation to a shift. We
5801 can actually do this more generally, but it doesn't seem worth it. */
5803 if (true_code == NE && XEXP (cond, 1) == const0_rtx
5804 && false_rtx == const0_rtx && CONST_INT_P (true_rtx)
5805 && ((1 == nonzero_bits (XEXP (cond, 0), mode)
5806 && (i = exact_log2 (INTVAL (true_rtx))) >= 0)
5807 || ((num_sign_bit_copies (XEXP (cond, 0), mode)
5808 == GET_MODE_BITSIZE (mode))
5809 && (i = exact_log2 (-INTVAL (true_rtx))) >= 0)))
5811 simplify_shift_const (NULL_RTX, ASHIFT, mode,
5812 gen_lowpart (mode, XEXP (cond, 0)), i);
5814 /* (IF_THEN_ELSE (NE REG 0) (0) (8)) is REG for nonzero_bits (REG) == 8. */
5815 if (true_code == NE && XEXP (cond, 1) == const0_rtx
5816 && false_rtx == const0_rtx && CONST_INT_P (true_rtx)
5817 && GET_MODE (XEXP (cond, 0)) == mode
5818 && (INTVAL (true_rtx) & GET_MODE_MASK (mode))
5819 == nonzero_bits (XEXP (cond, 0), mode)
5820 && (i = exact_log2 (INTVAL (true_rtx) & GET_MODE_MASK (mode))) >= 0)
5821 return XEXP (cond, 0);
5826 /* Simplify X, a SET expression. Return the new expression. */
5829 simplify_set (rtx x)
5831 rtx src = SET_SRC (x);
5832 rtx dest = SET_DEST (x);
5833 enum machine_mode mode
5834 = GET_MODE (src) != VOIDmode ? GET_MODE (src) : GET_MODE (dest);
5838 /* (set (pc) (return)) gets written as (return). */
5839 if (GET_CODE (dest) == PC && GET_CODE (src) == RETURN)
5842 /* Now that we know for sure which bits of SRC we are using, see if we can
5843 simplify the expression for the object knowing that we only need the
5846 if (GET_MODE_CLASS (mode) == MODE_INT
5847 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
5849 src = force_to_mode (src, mode, ~(HOST_WIDE_INT) 0, 0);
5850 SUBST (SET_SRC (x), src);
5853 /* If we are setting CC0 or if the source is a COMPARE, look for the use of
5854 the comparison result and try to simplify it unless we already have used
5855 undobuf.other_insn. */
5856 if ((GET_MODE_CLASS (mode) == MODE_CC
5857 || GET_CODE (src) == COMPARE
5859 && (cc_use = find_single_use (dest, subst_insn, &other_insn)) != 0
5860 && (undobuf.other_insn == 0 || other_insn == undobuf.other_insn)
5861 && COMPARISON_P (*cc_use)
5862 && rtx_equal_p (XEXP (*cc_use, 0), dest))
5864 enum rtx_code old_code = GET_CODE (*cc_use);
5865 enum rtx_code new_code;
5867 int other_changed = 0;
5868 enum machine_mode compare_mode = GET_MODE (dest);
5870 if (GET_CODE (src) == COMPARE)
5871 op0 = XEXP (src, 0), op1 = XEXP (src, 1);
5873 op0 = src, op1 = CONST0_RTX (GET_MODE (src));
5875 tmp = simplify_relational_operation (old_code, compare_mode, VOIDmode,
5878 new_code = old_code;
5879 else if (!CONSTANT_P (tmp))
5881 new_code = GET_CODE (tmp);
5882 op0 = XEXP (tmp, 0);
5883 op1 = XEXP (tmp, 1);
5887 rtx pat = PATTERN (other_insn);
5888 undobuf.other_insn = other_insn;
5889 SUBST (*cc_use, tmp);
5891 /* Attempt to simplify CC user. */
5892 if (GET_CODE (pat) == SET)
5894 rtx new_rtx = simplify_rtx (SET_SRC (pat));
5895 if (new_rtx != NULL_RTX)
5896 SUBST (SET_SRC (pat), new_rtx);
5899 /* Convert X into a no-op move. */
5900 SUBST (SET_DEST (x), pc_rtx);
5901 SUBST (SET_SRC (x), pc_rtx);
5905 /* Simplify our comparison, if possible. */
5906 new_code = simplify_comparison (new_code, &op0, &op1);
5908 #ifdef SELECT_CC_MODE
5909 /* If this machine has CC modes other than CCmode, check to see if we
5910 need to use a different CC mode here. */
5911 if (GET_MODE_CLASS (GET_MODE (op0)) == MODE_CC)
5912 compare_mode = GET_MODE (op0);
5914 compare_mode = SELECT_CC_MODE (new_code, op0, op1);
5917 /* If the mode changed, we have to change SET_DEST, the mode in the
5918 compare, and the mode in the place SET_DEST is used. If SET_DEST is
5919 a hard register, just build new versions with the proper mode. If it
5920 is a pseudo, we lose unless it is only time we set the pseudo, in
5921 which case we can safely change its mode. */
5922 if (compare_mode != GET_MODE (dest))
5924 if (can_change_dest_mode (dest, 0, compare_mode))
5926 unsigned int regno = REGNO (dest);
5929 if (regno < FIRST_PSEUDO_REGISTER)
5930 new_dest = gen_rtx_REG (compare_mode, regno);
5933 SUBST_MODE (regno_reg_rtx[regno], compare_mode);
5934 new_dest = regno_reg_rtx[regno];
5937 SUBST (SET_DEST (x), new_dest);
5938 SUBST (XEXP (*cc_use, 0), new_dest);
5945 #endif /* SELECT_CC_MODE */
5947 /* If the code changed, we have to build a new comparison in
5948 undobuf.other_insn. */
5949 if (new_code != old_code)
5951 int other_changed_previously = other_changed;
5952 unsigned HOST_WIDE_INT mask;
5953 rtx old_cc_use = *cc_use;
5955 SUBST (*cc_use, gen_rtx_fmt_ee (new_code, GET_MODE (*cc_use),
5959 /* If the only change we made was to change an EQ into an NE or
5960 vice versa, OP0 has only one bit that might be nonzero, and OP1
5961 is zero, check if changing the user of the condition code will
5962 produce a valid insn. If it won't, we can keep the original code
5963 in that insn by surrounding our operation with an XOR. */
5965 if (((old_code == NE && new_code == EQ)
5966 || (old_code == EQ && new_code == NE))
5967 && ! other_changed_previously && op1 == const0_rtx
5968 && GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
5969 && exact_log2 (mask = nonzero_bits (op0, GET_MODE (op0))) >= 0)
5971 rtx pat = PATTERN (other_insn), note = 0;
5973 if ((recog_for_combine (&pat, other_insn, ¬e) < 0
5974 && ! check_asm_operands (pat)))
5976 *cc_use = old_cc_use;
5979 op0 = simplify_gen_binary (XOR, GET_MODE (op0),
5980 op0, GEN_INT (mask));
5986 undobuf.other_insn = other_insn;
5988 /* Otherwise, if we didn't previously have a COMPARE in the
5989 correct mode, we need one. */
5990 if (GET_CODE (src) != COMPARE || GET_MODE (src) != compare_mode)
5992 SUBST (SET_SRC (x), gen_rtx_COMPARE (compare_mode, op0, op1));
5995 else if (GET_MODE (op0) == compare_mode && op1 == const0_rtx)
5997 SUBST (SET_SRC (x), op0);
6000 /* Otherwise, update the COMPARE if needed. */
6001 else if (XEXP (src, 0) != op0 || XEXP (src, 1) != op1)
6003 SUBST (SET_SRC (x), gen_rtx_COMPARE (compare_mode, op0, op1));
6009 /* Get SET_SRC in a form where we have placed back any
6010 compound expressions. Then do the checks below. */
6011 src = make_compound_operation (src, SET);
6012 SUBST (SET_SRC (x), src);
6015 /* If we have (set x (subreg:m1 (op:m2 ...) 0)) with OP being some operation,
6016 and X being a REG or (subreg (reg)), we may be able to convert this to
6017 (set (subreg:m2 x) (op)).
6019 We can always do this if M1 is narrower than M2 because that means that
6020 we only care about the low bits of the result.
6022 However, on machines without WORD_REGISTER_OPERATIONS defined, we cannot
6023 perform a narrower operation than requested since the high-order bits will
6024 be undefined. On machine where it is defined, this transformation is safe
6025 as long as M1 and M2 have the same number of words. */
6027 if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src)
6028 && !OBJECT_P (SUBREG_REG (src))
6029 && (((GET_MODE_SIZE (GET_MODE (src)) + (UNITS_PER_WORD - 1))
6031 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (src)))
6032 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD))
6033 #ifndef WORD_REGISTER_OPERATIONS
6034 && (GET_MODE_SIZE (GET_MODE (src))
6035 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (src))))
6037 #ifdef CANNOT_CHANGE_MODE_CLASS
6038 && ! (REG_P (dest) && REGNO (dest) < FIRST_PSEUDO_REGISTER
6039 && REG_CANNOT_CHANGE_MODE_P (REGNO (dest),
6040 GET_MODE (SUBREG_REG (src)),
6044 || (GET_CODE (dest) == SUBREG
6045 && REG_P (SUBREG_REG (dest)))))
6047 SUBST (SET_DEST (x),
6048 gen_lowpart (GET_MODE (SUBREG_REG (src)),
6050 SUBST (SET_SRC (x), SUBREG_REG (src));
6052 src = SET_SRC (x), dest = SET_DEST (x);
6056 /* If we have (set (cc0) (subreg ...)), we try to remove the subreg
6059 && GET_CODE (src) == SUBREG
6060 && subreg_lowpart_p (src)
6061 && (GET_MODE_BITSIZE (GET_MODE (src))
6062 < GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (src)))))
6064 rtx inner = SUBREG_REG (src);
6065 enum machine_mode inner_mode = GET_MODE (inner);
6067 /* Here we make sure that we don't have a sign bit on. */
6068 if (GET_MODE_BITSIZE (inner_mode) <= HOST_BITS_PER_WIDE_INT
6069 && (nonzero_bits (inner, inner_mode)
6070 < ((unsigned HOST_WIDE_INT) 1
6071 << (GET_MODE_BITSIZE (GET_MODE (src)) - 1))))
6073 SUBST (SET_SRC (x), inner);
6079 #ifdef LOAD_EXTEND_OP
6080 /* If we have (set FOO (subreg:M (mem:N BAR) 0)) with M wider than N, this
6081 would require a paradoxical subreg. Replace the subreg with a
6082 zero_extend to avoid the reload that would otherwise be required. */
6084 if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src)
6085 && INTEGRAL_MODE_P (GET_MODE (SUBREG_REG (src)))
6086 && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src))) != UNKNOWN
6087 && SUBREG_BYTE (src) == 0
6088 && (GET_MODE_SIZE (GET_MODE (src))
6089 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (src))))
6090 && MEM_P (SUBREG_REG (src)))
6093 gen_rtx_fmt_e (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src))),
6094 GET_MODE (src), SUBREG_REG (src)));
6100 /* If we don't have a conditional move, SET_SRC is an IF_THEN_ELSE, and we
6101 are comparing an item known to be 0 or -1 against 0, use a logical
6102 operation instead. Check for one of the arms being an IOR of the other
6103 arm with some value. We compute three terms to be IOR'ed together. In
6104 practice, at most two will be nonzero. Then we do the IOR's. */
6106 if (GET_CODE (dest) != PC
6107 && GET_CODE (src) == IF_THEN_ELSE
6108 && GET_MODE_CLASS (GET_MODE (src)) == MODE_INT
6109 && (GET_CODE (XEXP (src, 0)) == EQ || GET_CODE (XEXP (src, 0)) == NE)
6110 && XEXP (XEXP (src, 0), 1) == const0_rtx
6111 && GET_MODE (src) == GET_MODE (XEXP (XEXP (src, 0), 0))
6112 #ifdef HAVE_conditional_move
6113 && ! can_conditionally_move_p (GET_MODE (src))
6115 && (num_sign_bit_copies (XEXP (XEXP (src, 0), 0),
6116 GET_MODE (XEXP (XEXP (src, 0), 0)))
6117 == GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (src, 0), 0))))
6118 && ! side_effects_p (src))
6120 rtx true_rtx = (GET_CODE (XEXP (src, 0)) == NE
6121 ? XEXP (src, 1) : XEXP (src, 2));
6122 rtx false_rtx = (GET_CODE (XEXP (src, 0)) == NE
6123 ? XEXP (src, 2) : XEXP (src, 1));
6124 rtx term1 = const0_rtx, term2, term3;
6126 if (GET_CODE (true_rtx) == IOR
6127 && rtx_equal_p (XEXP (true_rtx, 0), false_rtx))
6128 term1 = false_rtx, true_rtx = XEXP (true_rtx, 1), false_rtx = const0_rtx;
6129 else if (GET_CODE (true_rtx) == IOR
6130 && rtx_equal_p (XEXP (true_rtx, 1), false_rtx))
6131 term1 = false_rtx, true_rtx = XEXP (true_rtx, 0), false_rtx = const0_rtx;
6132 else if (GET_CODE (false_rtx) == IOR
6133 && rtx_equal_p (XEXP (false_rtx, 0), true_rtx))
6134 term1 = true_rtx, false_rtx = XEXP (false_rtx, 1), true_rtx = const0_rtx;
6135 else if (GET_CODE (false_rtx) == IOR
6136 && rtx_equal_p (XEXP (false_rtx, 1), true_rtx))
6137 term1 = true_rtx, false_rtx = XEXP (false_rtx, 0), true_rtx = const0_rtx;
6139 term2 = simplify_gen_binary (AND, GET_MODE (src),
6140 XEXP (XEXP (src, 0), 0), true_rtx);
6141 term3 = simplify_gen_binary (AND, GET_MODE (src),
6142 simplify_gen_unary (NOT, GET_MODE (src),
6143 XEXP (XEXP (src, 0), 0),
6148 simplify_gen_binary (IOR, GET_MODE (src),
6149 simplify_gen_binary (IOR, GET_MODE (src),
6156 /* If either SRC or DEST is a CLOBBER of (const_int 0), make this
6157 whole thing fail. */
6158 if (GET_CODE (src) == CLOBBER && XEXP (src, 0) == const0_rtx)
6160 else if (GET_CODE (dest) == CLOBBER && XEXP (dest, 0) == const0_rtx)
6163 /* Convert this into a field assignment operation, if possible. */
6164 return make_field_assignment (x);
6167 /* Simplify, X, and AND, IOR, or XOR operation, and return the simplified
6171 simplify_logical (rtx x)
6173 enum machine_mode mode = GET_MODE (x);
6174 rtx op0 = XEXP (x, 0);
6175 rtx op1 = XEXP (x, 1);
6177 switch (GET_CODE (x))
6180 /* We can call simplify_and_const_int only if we don't lose
6181 any (sign) bits when converting INTVAL (op1) to
6182 "unsigned HOST_WIDE_INT". */
6183 if (CONST_INT_P (op1)
6184 && (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
6185 || INTVAL (op1) > 0))
6187 x = simplify_and_const_int (x, mode, op0, INTVAL (op1));
6188 if (GET_CODE (x) != AND)
6195 /* If we have any of (and (ior A B) C) or (and (xor A B) C),
6196 apply the distributive law and then the inverse distributive
6197 law to see if things simplify. */
6198 if (GET_CODE (op0) == IOR || GET_CODE (op0) == XOR)
6200 rtx result = distribute_and_simplify_rtx (x, 0);
6204 if (GET_CODE (op1) == IOR || GET_CODE (op1) == XOR)
6206 rtx result = distribute_and_simplify_rtx (x, 1);
6213 /* If we have (ior (and A B) C), apply the distributive law and then
6214 the inverse distributive law to see if things simplify. */
6216 if (GET_CODE (op0) == AND)
6218 rtx result = distribute_and_simplify_rtx (x, 0);
6223 if (GET_CODE (op1) == AND)
6225 rtx result = distribute_and_simplify_rtx (x, 1);
6238 /* We consider ZERO_EXTRACT, SIGN_EXTRACT, and SIGN_EXTEND as "compound
6239 operations" because they can be replaced with two more basic operations.
6240 ZERO_EXTEND is also considered "compound" because it can be replaced with
6241 an AND operation, which is simpler, though only one operation.
6243 The function expand_compound_operation is called with an rtx expression
6244 and will convert it to the appropriate shifts and AND operations,
6245 simplifying at each stage.
6247 The function make_compound_operation is called to convert an expression
6248 consisting of shifts and ANDs into the equivalent compound expression.
6249 It is the inverse of this function, loosely speaking. */
6252 expand_compound_operation (rtx x)
6254 unsigned HOST_WIDE_INT pos = 0, len;
6256 unsigned int modewidth;
6259 switch (GET_CODE (x))
6264 /* We can't necessarily use a const_int for a multiword mode;
6265 it depends on implicitly extending the value.
6266 Since we don't know the right way to extend it,
6267 we can't tell whether the implicit way is right.
6269 Even for a mode that is no wider than a const_int,
6270 we can't win, because we need to sign extend one of its bits through
6271 the rest of it, and we don't know which bit. */
6272 if (CONST_INT_P (XEXP (x, 0)))
6275 /* Return if (subreg:MODE FROM 0) is not a safe replacement for
6276 (zero_extend:MODE FROM) or (sign_extend:MODE FROM). It is for any MEM
6277 because (SUBREG (MEM...)) is guaranteed to cause the MEM to be
6278 reloaded. If not for that, MEM's would very rarely be safe.
6280 Reject MODEs bigger than a word, because we might not be able
6281 to reference a two-register group starting with an arbitrary register
6282 (and currently gen_lowpart might crash for a SUBREG). */
6284 if (GET_MODE_SIZE (GET_MODE (XEXP (x, 0))) > UNITS_PER_WORD)
6287 /* Reject MODEs that aren't scalar integers because turning vector
6288 or complex modes into shifts causes problems. */
6290 if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x, 0))))
6293 len = GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)));
6294 /* If the inner object has VOIDmode (the only way this can happen
6295 is if it is an ASM_OPERANDS), we can't do anything since we don't
6296 know how much masking to do. */
6305 /* ... fall through ... */
6308 /* If the operand is a CLOBBER, just return it. */
6309 if (GET_CODE (XEXP (x, 0)) == CLOBBER)
6312 if (!CONST_INT_P (XEXP (x, 1))
6313 || !CONST_INT_P (XEXP (x, 2))
6314 || GET_MODE (XEXP (x, 0)) == VOIDmode)
6317 /* Reject MODEs that aren't scalar integers because turning vector
6318 or complex modes into shifts causes problems. */
6320 if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x, 0))))
6323 len = INTVAL (XEXP (x, 1));
6324 pos = INTVAL (XEXP (x, 2));
6326 /* This should stay within the object being extracted, fail otherwise. */
6327 if (len + pos > GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))))
6330 if (BITS_BIG_ENDIAN)
6331 pos = GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - len - pos;
6338 /* Convert sign extension to zero extension, if we know that the high
6339 bit is not set, as this is easier to optimize. It will be converted
6340 back to cheaper alternative in make_extraction. */
6341 if (GET_CODE (x) == SIGN_EXTEND
6342 && (GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
6343 && ((nonzero_bits (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
6344 & ~(((unsigned HOST_WIDE_INT)
6345 GET_MODE_MASK (GET_MODE (XEXP (x, 0))))
6349 rtx temp = gen_rtx_ZERO_EXTEND (GET_MODE (x), XEXP (x, 0));
6350 rtx temp2 = expand_compound_operation (temp);
6352 /* Make sure this is a profitable operation. */
6353 if (rtx_cost (x, SET, optimize_this_for_speed_p)
6354 > rtx_cost (temp2, SET, optimize_this_for_speed_p))
6356 else if (rtx_cost (x, SET, optimize_this_for_speed_p)
6357 > rtx_cost (temp, SET, optimize_this_for_speed_p))
6363 /* We can optimize some special cases of ZERO_EXTEND. */
6364 if (GET_CODE (x) == ZERO_EXTEND)
6366 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI if we
6367 know that the last value didn't have any inappropriate bits
6369 if (GET_CODE (XEXP (x, 0)) == TRUNCATE
6370 && GET_MODE (XEXP (XEXP (x, 0), 0)) == GET_MODE (x)
6371 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
6372 && (nonzero_bits (XEXP (XEXP (x, 0), 0), GET_MODE (x))
6373 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
6374 return XEXP (XEXP (x, 0), 0);
6376 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
6377 if (GET_CODE (XEXP (x, 0)) == SUBREG
6378 && GET_MODE (SUBREG_REG (XEXP (x, 0))) == GET_MODE (x)
6379 && subreg_lowpart_p (XEXP (x, 0))
6380 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
6381 && (nonzero_bits (SUBREG_REG (XEXP (x, 0)), GET_MODE (x))
6382 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
6383 return SUBREG_REG (XEXP (x, 0));
6385 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI when foo
6386 is a comparison and STORE_FLAG_VALUE permits. This is like
6387 the first case, but it works even when GET_MODE (x) is larger
6388 than HOST_WIDE_INT. */
6389 if (GET_CODE (XEXP (x, 0)) == TRUNCATE
6390 && GET_MODE (XEXP (XEXP (x, 0), 0)) == GET_MODE (x)
6391 && COMPARISON_P (XEXP (XEXP (x, 0), 0))
6392 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
6393 <= HOST_BITS_PER_WIDE_INT)
6394 && ((HOST_WIDE_INT) STORE_FLAG_VALUE
6395 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
6396 return XEXP (XEXP (x, 0), 0);
6398 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
6399 if (GET_CODE (XEXP (x, 0)) == SUBREG
6400 && GET_MODE (SUBREG_REG (XEXP (x, 0))) == GET_MODE (x)
6401 && subreg_lowpart_p (XEXP (x, 0))
6402 && COMPARISON_P (SUBREG_REG (XEXP (x, 0)))
6403 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
6404 <= HOST_BITS_PER_WIDE_INT)
6405 && ((HOST_WIDE_INT) STORE_FLAG_VALUE
6406 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
6407 return SUBREG_REG (XEXP (x, 0));
6411 /* If we reach here, we want to return a pair of shifts. The inner
6412 shift is a left shift of BITSIZE - POS - LEN bits. The outer
6413 shift is a right shift of BITSIZE - LEN bits. It is arithmetic or
6414 logical depending on the value of UNSIGNEDP.
6416 If this was a ZERO_EXTEND or ZERO_EXTRACT, this pair of shifts will be
6417 converted into an AND of a shift.
6419 We must check for the case where the left shift would have a negative
6420 count. This can happen in a case like (x >> 31) & 255 on machines
6421 that can't shift by a constant. On those machines, we would first
6422 combine the shift with the AND to produce a variable-position
6423 extraction. Then the constant of 31 would be substituted in to produce
6424 a such a position. */
6426 modewidth = GET_MODE_BITSIZE (GET_MODE (x));
6427 if (modewidth + len >= pos)
6429 enum machine_mode mode = GET_MODE (x);
6430 tem = gen_lowpart (mode, XEXP (x, 0));
6431 if (!tem || GET_CODE (tem) == CLOBBER)
6433 tem = simplify_shift_const (NULL_RTX, ASHIFT, mode,
6434 tem, modewidth - pos - len);
6435 tem = simplify_shift_const (NULL_RTX, unsignedp ? LSHIFTRT : ASHIFTRT,
6436 mode, tem, modewidth - len);
6438 else if (unsignedp && len < HOST_BITS_PER_WIDE_INT)
6439 tem = simplify_and_const_int (NULL_RTX, GET_MODE (x),
6440 simplify_shift_const (NULL_RTX, LSHIFTRT,
6443 ((HOST_WIDE_INT) 1 << len) - 1);
6445 /* Any other cases we can't handle. */
6448 /* If we couldn't do this for some reason, return the original
6450 if (GET_CODE (tem) == CLOBBER)
6456 /* X is a SET which contains an assignment of one object into
6457 a part of another (such as a bit-field assignment, STRICT_LOW_PART,
6458 or certain SUBREGS). If possible, convert it into a series of
6461 We half-heartedly support variable positions, but do not at all
6462 support variable lengths. */
6465 expand_field_assignment (const_rtx x)
6468 rtx pos; /* Always counts from low bit. */
6470 rtx mask, cleared, masked;
6471 enum machine_mode compute_mode;
6473 /* Loop until we find something we can't simplify. */
6476 if (GET_CODE (SET_DEST (x)) == STRICT_LOW_PART
6477 && GET_CODE (XEXP (SET_DEST (x), 0)) == SUBREG)
6479 inner = SUBREG_REG (XEXP (SET_DEST (x), 0));
6480 len = GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0)));
6481 pos = GEN_INT (subreg_lsb (XEXP (SET_DEST (x), 0)));
6483 else if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
6484 && CONST_INT_P (XEXP (SET_DEST (x), 1)))
6486 inner = XEXP (SET_DEST (x), 0);
6487 len = INTVAL (XEXP (SET_DEST (x), 1));
6488 pos = XEXP (SET_DEST (x), 2);
6490 /* A constant position should stay within the width of INNER. */
6491 if (CONST_INT_P (pos)
6492 && INTVAL (pos) + len > GET_MODE_BITSIZE (GET_MODE (inner)))
6495 if (BITS_BIG_ENDIAN)
6497 if (CONST_INT_P (pos))
6498 pos = GEN_INT (GET_MODE_BITSIZE (GET_MODE (inner)) - len
6500 else if (GET_CODE (pos) == MINUS
6501 && CONST_INT_P (XEXP (pos, 1))
6502 && (INTVAL (XEXP (pos, 1))
6503 == GET_MODE_BITSIZE (GET_MODE (inner)) - len))
6504 /* If position is ADJUST - X, new position is X. */
6505 pos = XEXP (pos, 0);
6507 pos = simplify_gen_binary (MINUS, GET_MODE (pos),
6508 GEN_INT (GET_MODE_BITSIZE (
6515 /* A SUBREG between two modes that occupy the same numbers of words
6516 can be done by moving the SUBREG to the source. */
6517 else if (GET_CODE (SET_DEST (x)) == SUBREG
6518 /* We need SUBREGs to compute nonzero_bits properly. */
6519 && nonzero_sign_valid
6520 && (((GET_MODE_SIZE (GET_MODE (SET_DEST (x)))
6521 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
6522 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x))))
6523 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)))
6525 x = gen_rtx_SET (VOIDmode, SUBREG_REG (SET_DEST (x)),
6527 (GET_MODE (SUBREG_REG (SET_DEST (x))),
6534 while (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
6535 inner = SUBREG_REG (inner);
6537 compute_mode = GET_MODE (inner);
6539 /* Don't attempt bitwise arithmetic on non scalar integer modes. */
6540 if (! SCALAR_INT_MODE_P (compute_mode))
6542 enum machine_mode imode;
6544 /* Don't do anything for vector or complex integral types. */
6545 if (! FLOAT_MODE_P (compute_mode))
6548 /* Try to find an integral mode to pun with. */
6549 imode = mode_for_size (GET_MODE_BITSIZE (compute_mode), MODE_INT, 0);
6550 if (imode == BLKmode)
6553 compute_mode = imode;
6554 inner = gen_lowpart (imode, inner);
6557 /* Compute a mask of LEN bits, if we can do this on the host machine. */
6558 if (len >= HOST_BITS_PER_WIDE_INT)
6561 /* Now compute the equivalent expression. Make a copy of INNER
6562 for the SET_DEST in case it is a MEM into which we will substitute;
6563 we don't want shared RTL in that case. */
6564 mask = GEN_INT (((HOST_WIDE_INT) 1 << len) - 1);
6565 cleared = simplify_gen_binary (AND, compute_mode,
6566 simplify_gen_unary (NOT, compute_mode,
6567 simplify_gen_binary (ASHIFT,
6572 masked = simplify_gen_binary (ASHIFT, compute_mode,
6573 simplify_gen_binary (
6575 gen_lowpart (compute_mode, SET_SRC (x)),
6579 x = gen_rtx_SET (VOIDmode, copy_rtx (inner),
6580 simplify_gen_binary (IOR, compute_mode,
6587 /* Return an RTX for a reference to LEN bits of INNER. If POS_RTX is nonzero,
6588 it is an RTX that represents a variable starting position; otherwise,
6589 POS is the (constant) starting bit position (counted from the LSB).
6591 UNSIGNEDP is nonzero for an unsigned reference and zero for a
6594 IN_DEST is nonzero if this is a reference in the destination of a
6595 SET. This is used when a ZERO_ or SIGN_EXTRACT isn't needed. If nonzero,
6596 a STRICT_LOW_PART will be used, if zero, ZERO_EXTEND or SIGN_EXTEND will
6599 IN_COMPARE is nonzero if we are in a COMPARE. This means that a
6600 ZERO_EXTRACT should be built even for bits starting at bit 0.
6602 MODE is the desired mode of the result (if IN_DEST == 0).
6604 The result is an RTX for the extraction or NULL_RTX if the target
6608 make_extraction (enum machine_mode mode, rtx inner, HOST_WIDE_INT pos,
6609 rtx pos_rtx, unsigned HOST_WIDE_INT len, int unsignedp,
6610 int in_dest, int in_compare)
6612 /* This mode describes the size of the storage area
6613 to fetch the overall value from. Within that, we
6614 ignore the POS lowest bits, etc. */
6615 enum machine_mode is_mode = GET_MODE (inner);
6616 enum machine_mode inner_mode;
6617 enum machine_mode wanted_inner_mode;
6618 enum machine_mode wanted_inner_reg_mode = word_mode;
6619 enum machine_mode pos_mode = word_mode;
6620 enum machine_mode extraction_mode = word_mode;
6621 enum machine_mode tmode = mode_for_size (len, MODE_INT, 1);
6623 rtx orig_pos_rtx = pos_rtx;
6624 HOST_WIDE_INT orig_pos;
6626 if (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
6628 /* If going from (subreg:SI (mem:QI ...)) to (mem:QI ...),
6629 consider just the QI as the memory to extract from.
6630 The subreg adds or removes high bits; its mode is
6631 irrelevant to the meaning of this extraction,
6632 since POS and LEN count from the lsb. */
6633 if (MEM_P (SUBREG_REG (inner)))
6634 is_mode = GET_MODE (SUBREG_REG (inner));
6635 inner = SUBREG_REG (inner);
6637 else if (GET_CODE (inner) == ASHIFT
6638 && CONST_INT_P (XEXP (inner, 1))
6639 && pos_rtx == 0 && pos == 0
6640 && len > (unsigned HOST_WIDE_INT) INTVAL (XEXP (inner, 1)))
6642 /* We're extracting the least significant bits of an rtx
6643 (ashift X (const_int C)), where LEN > C. Extract the
6644 least significant (LEN - C) bits of X, giving an rtx
6645 whose mode is MODE, then shift it left C times. */
6646 new_rtx = make_extraction (mode, XEXP (inner, 0),
6647 0, 0, len - INTVAL (XEXP (inner, 1)),
6648 unsignedp, in_dest, in_compare);
6650 return gen_rtx_ASHIFT (mode, new_rtx, XEXP (inner, 1));
6653 inner_mode = GET_MODE (inner);
6655 if (pos_rtx && CONST_INT_P (pos_rtx))
6656 pos = INTVAL (pos_rtx), pos_rtx = 0;
6658 /* See if this can be done without an extraction. We never can if the
6659 width of the field is not the same as that of some integer mode. For
6660 registers, we can only avoid the extraction if the position is at the
6661 low-order bit and this is either not in the destination or we have the
6662 appropriate STRICT_LOW_PART operation available.
6664 For MEM, we can avoid an extract if the field starts on an appropriate
6665 boundary and we can change the mode of the memory reference. */
6667 if (tmode != BLKmode
6668 && ((pos_rtx == 0 && (pos % BITS_PER_WORD) == 0
6670 && (inner_mode == tmode
6672 || TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (tmode),
6673 GET_MODE_BITSIZE (inner_mode))
6674 || reg_truncated_to_mode (tmode, inner))
6677 && have_insn_for (STRICT_LOW_PART, tmode))))
6678 || (MEM_P (inner) && pos_rtx == 0
6680 % (STRICT_ALIGNMENT ? GET_MODE_ALIGNMENT (tmode)
6681 : BITS_PER_UNIT)) == 0
6682 /* We can't do this if we are widening INNER_MODE (it
6683 may not be aligned, for one thing). */
6684 && GET_MODE_BITSIZE (inner_mode) >= GET_MODE_BITSIZE (tmode)
6685 && (inner_mode == tmode
6686 || (! mode_dependent_address_p (XEXP (inner, 0))
6687 && ! MEM_VOLATILE_P (inner))))))
6689 /* If INNER is a MEM, make a new MEM that encompasses just the desired
6690 field. If the original and current mode are the same, we need not
6691 adjust the offset. Otherwise, we do if bytes big endian.
6693 If INNER is not a MEM, get a piece consisting of just the field
6694 of interest (in this case POS % BITS_PER_WORD must be 0). */
6698 HOST_WIDE_INT offset;
6700 /* POS counts from lsb, but make OFFSET count in memory order. */
6701 if (BYTES_BIG_ENDIAN)
6702 offset = (GET_MODE_BITSIZE (is_mode) - len - pos) / BITS_PER_UNIT;
6704 offset = pos / BITS_PER_UNIT;
6706 new_rtx = adjust_address_nv (inner, tmode, offset);
6708 else if (REG_P (inner))
6710 if (tmode != inner_mode)
6712 /* We can't call gen_lowpart in a DEST since we
6713 always want a SUBREG (see below) and it would sometimes
6714 return a new hard register. */
6717 HOST_WIDE_INT final_word = pos / BITS_PER_WORD;
6719 if (WORDS_BIG_ENDIAN
6720 && GET_MODE_SIZE (inner_mode) > UNITS_PER_WORD)
6721 final_word = ((GET_MODE_SIZE (inner_mode)
6722 - GET_MODE_SIZE (tmode))
6723 / UNITS_PER_WORD) - final_word;
6725 final_word *= UNITS_PER_WORD;
6726 if (BYTES_BIG_ENDIAN &&
6727 GET_MODE_SIZE (inner_mode) > GET_MODE_SIZE (tmode))
6728 final_word += (GET_MODE_SIZE (inner_mode)
6729 - GET_MODE_SIZE (tmode)) % UNITS_PER_WORD;
6731 /* Avoid creating invalid subregs, for example when
6732 simplifying (x>>32)&255. */
6733 if (!validate_subreg (tmode, inner_mode, inner, final_word))
6736 new_rtx = gen_rtx_SUBREG (tmode, inner, final_word);
6739 new_rtx = gen_lowpart (tmode, inner);
6745 new_rtx = force_to_mode (inner, tmode,
6746 len >= HOST_BITS_PER_WIDE_INT
6747 ? ~(unsigned HOST_WIDE_INT) 0
6748 : ((unsigned HOST_WIDE_INT) 1 << len) - 1,
6751 /* If this extraction is going into the destination of a SET,
6752 make a STRICT_LOW_PART unless we made a MEM. */
6755 return (MEM_P (new_rtx) ? new_rtx
6756 : (GET_CODE (new_rtx) != SUBREG
6757 ? gen_rtx_CLOBBER (tmode, const0_rtx)
6758 : gen_rtx_STRICT_LOW_PART (VOIDmode, new_rtx)));
6763 if (CONST_INT_P (new_rtx)
6764 || GET_CODE (new_rtx) == CONST_DOUBLE)
6765 return simplify_unary_operation (unsignedp ? ZERO_EXTEND : SIGN_EXTEND,
6766 mode, new_rtx, tmode);
6768 /* If we know that no extraneous bits are set, and that the high
6769 bit is not set, convert the extraction to the cheaper of
6770 sign and zero extension, that are equivalent in these cases. */
6771 if (flag_expensive_optimizations
6772 && (GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT
6773 && ((nonzero_bits (new_rtx, tmode)
6774 & ~(((unsigned HOST_WIDE_INT)
6775 GET_MODE_MASK (tmode))
6779 rtx temp = gen_rtx_ZERO_EXTEND (mode, new_rtx);
6780 rtx temp1 = gen_rtx_SIGN_EXTEND (mode, new_rtx);
6782 /* Prefer ZERO_EXTENSION, since it gives more information to
6784 if (rtx_cost (temp, SET, optimize_this_for_speed_p)
6785 <= rtx_cost (temp1, SET, optimize_this_for_speed_p))
6790 /* Otherwise, sign- or zero-extend unless we already are in the
6793 return (gen_rtx_fmt_e (unsignedp ? ZERO_EXTEND : SIGN_EXTEND,
6797 /* Unless this is a COMPARE or we have a funny memory reference,
6798 don't do anything with zero-extending field extracts starting at
6799 the low-order bit since they are simple AND operations. */
6800 if (pos_rtx == 0 && pos == 0 && ! in_dest
6801 && ! in_compare && unsignedp)
6804 /* Unless INNER is not MEM, reject this if we would be spanning bytes or
6805 if the position is not a constant and the length is not 1. In all
6806 other cases, we would only be going outside our object in cases when
6807 an original shift would have been undefined. */
6809 && ((pos_rtx == 0 && pos + len > GET_MODE_BITSIZE (is_mode))
6810 || (pos_rtx != 0 && len != 1)))
6813 /* Get the mode to use should INNER not be a MEM, the mode for the position,
6814 and the mode for the result. */
6815 if (in_dest && mode_for_extraction (EP_insv, -1) != MAX_MACHINE_MODE)
6817 wanted_inner_reg_mode = mode_for_extraction (EP_insv, 0);
6818 pos_mode = mode_for_extraction (EP_insv, 2);
6819 extraction_mode = mode_for_extraction (EP_insv, 3);
6822 if (! in_dest && unsignedp
6823 && mode_for_extraction (EP_extzv, -1) != MAX_MACHINE_MODE)
6825 wanted_inner_reg_mode = mode_for_extraction (EP_extzv, 1);
6826 pos_mode = mode_for_extraction (EP_extzv, 3);
6827 extraction_mode = mode_for_extraction (EP_extzv, 0);
6830 if (! in_dest && ! unsignedp
6831 && mode_for_extraction (EP_extv, -1) != MAX_MACHINE_MODE)
6833 wanted_inner_reg_mode = mode_for_extraction (EP_extv, 1);
6834 pos_mode = mode_for_extraction (EP_extv, 3);
6835 extraction_mode = mode_for_extraction (EP_extv, 0);
6838 /* Never narrow an object, since that might not be safe. */
6840 if (mode != VOIDmode
6841 && GET_MODE_SIZE (extraction_mode) < GET_MODE_SIZE (mode))
6842 extraction_mode = mode;
6844 if (pos_rtx && GET_MODE (pos_rtx) != VOIDmode
6845 && GET_MODE_SIZE (pos_mode) < GET_MODE_SIZE (GET_MODE (pos_rtx)))
6846 pos_mode = GET_MODE (pos_rtx);
6848 /* If this is not from memory, the desired mode is the preferred mode
6849 for an extraction pattern's first input operand, or word_mode if there
6852 wanted_inner_mode = wanted_inner_reg_mode;
6855 /* Be careful not to go beyond the extracted object and maintain the
6856 natural alignment of the memory. */
6857 wanted_inner_mode = smallest_mode_for_size (len, MODE_INT);
6858 while (pos % GET_MODE_BITSIZE (wanted_inner_mode) + len
6859 > GET_MODE_BITSIZE (wanted_inner_mode))
6861 wanted_inner_mode = GET_MODE_WIDER_MODE (wanted_inner_mode);
6862 gcc_assert (wanted_inner_mode != VOIDmode);
6865 /* If we have to change the mode of memory and cannot, the desired mode
6866 is EXTRACTION_MODE. */
6867 if (inner_mode != wanted_inner_mode
6868 && (mode_dependent_address_p (XEXP (inner, 0))
6869 || MEM_VOLATILE_P (inner)
6871 wanted_inner_mode = extraction_mode;
6876 if (BITS_BIG_ENDIAN)
6878 /* POS is passed as if BITS_BIG_ENDIAN == 0, so we need to convert it to
6879 BITS_BIG_ENDIAN style. If position is constant, compute new
6880 position. Otherwise, build subtraction.
6881 Note that POS is relative to the mode of the original argument.
6882 If it's a MEM we need to recompute POS relative to that.
6883 However, if we're extracting from (or inserting into) a register,
6884 we want to recompute POS relative to wanted_inner_mode. */
6885 int width = (MEM_P (inner)
6886 ? GET_MODE_BITSIZE (is_mode)
6887 : GET_MODE_BITSIZE (wanted_inner_mode));
6890 pos = width - len - pos;
6893 = gen_rtx_MINUS (GET_MODE (pos_rtx), GEN_INT (width - len), pos_rtx);
6894 /* POS may be less than 0 now, but we check for that below.
6895 Note that it can only be less than 0 if !MEM_P (inner). */
6898 /* If INNER has a wider mode, and this is a constant extraction, try to
6899 make it smaller and adjust the byte to point to the byte containing
6901 if (wanted_inner_mode != VOIDmode
6902 && inner_mode != wanted_inner_mode
6904 && GET_MODE_SIZE (wanted_inner_mode) < GET_MODE_SIZE (is_mode)
6906 && ! mode_dependent_address_p (XEXP (inner, 0))
6907 && ! MEM_VOLATILE_P (inner))
6911 /* The computations below will be correct if the machine is big
6912 endian in both bits and bytes or little endian in bits and bytes.
6913 If it is mixed, we must adjust. */
6915 /* If bytes are big endian and we had a paradoxical SUBREG, we must
6916 adjust OFFSET to compensate. */
6917 if (BYTES_BIG_ENDIAN
6918 && GET_MODE_SIZE (inner_mode) < GET_MODE_SIZE (is_mode))
6919 offset -= GET_MODE_SIZE (is_mode) - GET_MODE_SIZE (inner_mode);
6921 /* We can now move to the desired byte. */
6922 offset += (pos / GET_MODE_BITSIZE (wanted_inner_mode))
6923 * GET_MODE_SIZE (wanted_inner_mode);
6924 pos %= GET_MODE_BITSIZE (wanted_inner_mode);
6926 if (BYTES_BIG_ENDIAN != BITS_BIG_ENDIAN
6927 && is_mode != wanted_inner_mode)
6928 offset = (GET_MODE_SIZE (is_mode)
6929 - GET_MODE_SIZE (wanted_inner_mode) - offset);
6931 inner = adjust_address_nv (inner, wanted_inner_mode, offset);
6934 /* If INNER is not memory, get it into the proper mode. If we are changing
6935 its mode, POS must be a constant and smaller than the size of the new
6937 else if (!MEM_P (inner))
6939 /* On the LHS, don't create paradoxical subregs implicitely truncating
6940 the register unless TRULY_NOOP_TRUNCATION. */
6942 && !TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (GET_MODE (inner)),
6943 GET_MODE_BITSIZE (wanted_inner_mode)))
6946 if (GET_MODE (inner) != wanted_inner_mode
6948 || orig_pos + len > GET_MODE_BITSIZE (wanted_inner_mode)))
6954 inner = force_to_mode (inner, wanted_inner_mode,
6956 || len + orig_pos >= HOST_BITS_PER_WIDE_INT
6957 ? ~(unsigned HOST_WIDE_INT) 0
6958 : ((((unsigned HOST_WIDE_INT) 1 << len) - 1)
6963 /* Adjust mode of POS_RTX, if needed. If we want a wider mode, we
6964 have to zero extend. Otherwise, we can just use a SUBREG. */
6966 && GET_MODE_SIZE (pos_mode) > GET_MODE_SIZE (GET_MODE (pos_rtx)))
6968 rtx temp = gen_rtx_ZERO_EXTEND (pos_mode, pos_rtx);
6970 /* If we know that no extraneous bits are set, and that the high
6971 bit is not set, convert extraction to cheaper one - either
6972 SIGN_EXTENSION or ZERO_EXTENSION, that are equivalent in these
6974 if (flag_expensive_optimizations
6975 && (GET_MODE_BITSIZE (GET_MODE (pos_rtx)) <= HOST_BITS_PER_WIDE_INT
6976 && ((nonzero_bits (pos_rtx, GET_MODE (pos_rtx))
6977 & ~(((unsigned HOST_WIDE_INT)
6978 GET_MODE_MASK (GET_MODE (pos_rtx)))
6982 rtx temp1 = gen_rtx_SIGN_EXTEND (pos_mode, pos_rtx);
6984 /* Prefer ZERO_EXTENSION, since it gives more information to
6986 if (rtx_cost (temp1, SET, optimize_this_for_speed_p)
6987 < rtx_cost (temp, SET, optimize_this_for_speed_p))
6992 else if (pos_rtx != 0
6993 && GET_MODE_SIZE (pos_mode) < GET_MODE_SIZE (GET_MODE (pos_rtx)))
6994 pos_rtx = gen_lowpart (pos_mode, pos_rtx);
6996 /* Make POS_RTX unless we already have it and it is correct. If we don't
6997 have a POS_RTX but we do have an ORIG_POS_RTX, the latter must
6999 if (pos_rtx == 0 && orig_pos_rtx != 0 && INTVAL (orig_pos_rtx) == pos)
7000 pos_rtx = orig_pos_rtx;
7002 else if (pos_rtx == 0)
7003 pos_rtx = GEN_INT (pos);
7005 /* Make the required operation. See if we can use existing rtx. */
7006 new_rtx = gen_rtx_fmt_eee (unsignedp ? ZERO_EXTRACT : SIGN_EXTRACT,
7007 extraction_mode, inner, GEN_INT (len), pos_rtx);
7009 new_rtx = gen_lowpart (mode, new_rtx);
7014 /* See if X contains an ASHIFT of COUNT or more bits that can be commuted
7015 with any other operations in X. Return X without that shift if so. */
7018 extract_left_shift (rtx x, int count)
7020 enum rtx_code code = GET_CODE (x);
7021 enum machine_mode mode = GET_MODE (x);
7027 /* This is the shift itself. If it is wide enough, we will return
7028 either the value being shifted if the shift count is equal to
7029 COUNT or a shift for the difference. */
7030 if (CONST_INT_P (XEXP (x, 1))
7031 && INTVAL (XEXP (x, 1)) >= count)
7032 return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (x, 0),
7033 INTVAL (XEXP (x, 1)) - count);
7037 if ((tem = extract_left_shift (XEXP (x, 0), count)) != 0)
7038 return simplify_gen_unary (code, mode, tem, mode);
7042 case PLUS: case IOR: case XOR: case AND:
7043 /* If we can safely shift this constant and we find the inner shift,
7044 make a new operation. */
7045 if (CONST_INT_P (XEXP (x, 1))
7046 && (INTVAL (XEXP (x, 1)) & ((((HOST_WIDE_INT) 1 << count)) - 1)) == 0
7047 && (tem = extract_left_shift (XEXP (x, 0), count)) != 0)
7048 return simplify_gen_binary (code, mode, tem,
7049 GEN_INT (INTVAL (XEXP (x, 1)) >> count));
7060 /* Look at the expression rooted at X. Look for expressions
7061 equivalent to ZERO_EXTRACT, SIGN_EXTRACT, ZERO_EXTEND, SIGN_EXTEND.
7062 Form these expressions.
7064 Return the new rtx, usually just X.
7066 Also, for machines like the VAX that don't have logical shift insns,
7067 try to convert logical to arithmetic shift operations in cases where
7068 they are equivalent. This undoes the canonicalizations to logical
7069 shifts done elsewhere.
7071 We try, as much as possible, to re-use rtl expressions to save memory.
7073 IN_CODE says what kind of expression we are processing. Normally, it is
7074 SET. In a memory address (inside a MEM, PLUS or minus, the latter two
7075 being kludges), it is MEM. When processing the arguments of a comparison
7076 or a COMPARE against zero, it is COMPARE. */
7079 make_compound_operation (rtx x, enum rtx_code in_code)
7081 enum rtx_code code = GET_CODE (x);
7082 enum machine_mode mode = GET_MODE (x);
7083 int mode_width = GET_MODE_BITSIZE (mode);
7085 enum rtx_code next_code;
7091 /* Select the code to be used in recursive calls. Once we are inside an
7092 address, we stay there. If we have a comparison, set to COMPARE,
7093 but once inside, go back to our default of SET. */
7095 next_code = (code == MEM || code == PLUS || code == MINUS ? MEM
7096 : ((code == COMPARE || COMPARISON_P (x))
7097 && XEXP (x, 1) == const0_rtx) ? COMPARE
7098 : in_code == COMPARE ? SET : in_code);
7100 /* Process depending on the code of this operation. If NEW is set
7101 nonzero, it will be returned. */
7106 /* Convert shifts by constants into multiplications if inside
7108 if (in_code == MEM && CONST_INT_P (XEXP (x, 1))
7109 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT
7110 && INTVAL (XEXP (x, 1)) >= 0)
7112 new_rtx = make_compound_operation (XEXP (x, 0), next_code);
7113 new_rtx = gen_rtx_MULT (mode, new_rtx,
7114 GEN_INT ((HOST_WIDE_INT) 1
7115 << INTVAL (XEXP (x, 1))));
7120 /* If the second operand is not a constant, we can't do anything
7122 if (!CONST_INT_P (XEXP (x, 1)))
7125 /* If the constant is a power of two minus one and the first operand
7126 is a logical right shift, make an extraction. */
7127 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
7128 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
7130 new_rtx = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code);
7131 new_rtx = make_extraction (mode, new_rtx, 0, XEXP (XEXP (x, 0), 1), i, 1,
7132 0, in_code == COMPARE);
7135 /* Same as previous, but for (subreg (lshiftrt ...)) in first op. */
7136 else if (GET_CODE (XEXP (x, 0)) == SUBREG
7137 && subreg_lowpart_p (XEXP (x, 0))
7138 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == LSHIFTRT
7139 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
7141 new_rtx = make_compound_operation (XEXP (SUBREG_REG (XEXP (x, 0)), 0),
7143 new_rtx = make_extraction (GET_MODE (SUBREG_REG (XEXP (x, 0))), new_rtx, 0,
7144 XEXP (SUBREG_REG (XEXP (x, 0)), 1), i, 1,
7145 0, in_code == COMPARE);
7147 /* Same as previous, but for (xor/ior (lshiftrt...) (lshiftrt...)). */
7148 else if ((GET_CODE (XEXP (x, 0)) == XOR
7149 || GET_CODE (XEXP (x, 0)) == IOR)
7150 && GET_CODE (XEXP (XEXP (x, 0), 0)) == LSHIFTRT
7151 && GET_CODE (XEXP (XEXP (x, 0), 1)) == LSHIFTRT
7152 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
7154 /* Apply the distributive law, and then try to make extractions. */
7155 new_rtx = gen_rtx_fmt_ee (GET_CODE (XEXP (x, 0)), mode,
7156 gen_rtx_AND (mode, XEXP (XEXP (x, 0), 0),
7158 gen_rtx_AND (mode, XEXP (XEXP (x, 0), 1),
7160 new_rtx = make_compound_operation (new_rtx, in_code);
7163 /* If we are have (and (rotate X C) M) and C is larger than the number
7164 of bits in M, this is an extraction. */
7166 else if (GET_CODE (XEXP (x, 0)) == ROTATE
7167 && CONST_INT_P (XEXP (XEXP (x, 0), 1))
7168 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0
7169 && i <= INTVAL (XEXP (XEXP (x, 0), 1)))
7171 new_rtx = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code);
7172 new_rtx = make_extraction (mode, new_rtx,
7173 (GET_MODE_BITSIZE (mode)
7174 - INTVAL (XEXP (XEXP (x, 0), 1))),
7175 NULL_RTX, i, 1, 0, in_code == COMPARE);
7178 /* On machines without logical shifts, if the operand of the AND is
7179 a logical shift and our mask turns off all the propagated sign
7180 bits, we can replace the logical shift with an arithmetic shift. */
7181 else if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
7182 && !have_insn_for (LSHIFTRT, mode)
7183 && have_insn_for (ASHIFTRT, mode)
7184 && CONST_INT_P (XEXP (XEXP (x, 0), 1))
7185 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
7186 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT
7187 && mode_width <= HOST_BITS_PER_WIDE_INT)
7189 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
7191 mask >>= INTVAL (XEXP (XEXP (x, 0), 1));
7192 if ((INTVAL (XEXP (x, 1)) & ~mask) == 0)
7194 gen_rtx_ASHIFTRT (mode,
7195 make_compound_operation
7196 (XEXP (XEXP (x, 0), 0), next_code),
7197 XEXP (XEXP (x, 0), 1)));
7200 /* If the constant is one less than a power of two, this might be
7201 representable by an extraction even if no shift is present.
7202 If it doesn't end up being a ZERO_EXTEND, we will ignore it unless
7203 we are in a COMPARE. */
7204 else if ((i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
7205 new_rtx = make_extraction (mode,
7206 make_compound_operation (XEXP (x, 0),
7208 0, NULL_RTX, i, 1, 0, in_code == COMPARE);
7210 /* If we are in a comparison and this is an AND with a power of two,
7211 convert this into the appropriate bit extract. */
7212 else if (in_code == COMPARE
7213 && (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0)
7214 new_rtx = make_extraction (mode,
7215 make_compound_operation (XEXP (x, 0),
7217 i, NULL_RTX, 1, 1, 0, 1);
7222 /* If the sign bit is known to be zero, replace this with an
7223 arithmetic shift. */
7224 if (have_insn_for (ASHIFTRT, mode)
7225 && ! have_insn_for (LSHIFTRT, mode)
7226 && mode_width <= HOST_BITS_PER_WIDE_INT
7227 && (nonzero_bits (XEXP (x, 0), mode) & (1 << (mode_width - 1))) == 0)
7229 new_rtx = gen_rtx_ASHIFTRT (mode,
7230 make_compound_operation (XEXP (x, 0),
7236 /* ... fall through ... */
7242 /* If we have (ashiftrt (ashift foo C1) C2) with C2 >= C1,
7243 this is a SIGN_EXTRACT. */
7244 if (CONST_INT_P (rhs)
7245 && GET_CODE (lhs) == ASHIFT
7246 && CONST_INT_P (XEXP (lhs, 1))
7247 && INTVAL (rhs) >= INTVAL (XEXP (lhs, 1))
7248 && INTVAL (rhs) < mode_width)
7250 new_rtx = make_compound_operation (XEXP (lhs, 0), next_code);
7251 new_rtx = make_extraction (mode, new_rtx,
7252 INTVAL (rhs) - INTVAL (XEXP (lhs, 1)),
7253 NULL_RTX, mode_width - INTVAL (rhs),
7254 code == LSHIFTRT, 0, in_code == COMPARE);
7258 /* See if we have operations between an ASHIFTRT and an ASHIFT.
7259 If so, try to merge the shifts into a SIGN_EXTEND. We could
7260 also do this for some cases of SIGN_EXTRACT, but it doesn't
7261 seem worth the effort; the case checked for occurs on Alpha. */
7264 && ! (GET_CODE (lhs) == SUBREG
7265 && (OBJECT_P (SUBREG_REG (lhs))))
7266 && CONST_INT_P (rhs)
7267 && INTVAL (rhs) < HOST_BITS_PER_WIDE_INT
7268 && INTVAL (rhs) < mode_width
7269 && (new_rtx = extract_left_shift (lhs, INTVAL (rhs))) != 0)
7270 new_rtx = make_extraction (mode, make_compound_operation (new_rtx, next_code),
7271 0, NULL_RTX, mode_width - INTVAL (rhs),
7272 code == LSHIFTRT, 0, in_code == COMPARE);
7277 /* Call ourselves recursively on the inner expression. If we are
7278 narrowing the object and it has a different RTL code from
7279 what it originally did, do this SUBREG as a force_to_mode. */
7281 rtx inner = SUBREG_REG (x), simplified;
7283 tem = make_compound_operation (inner, in_code);
7286 = simplify_subreg (mode, tem, GET_MODE (inner), SUBREG_BYTE (x));
7290 if (GET_CODE (tem) != GET_CODE (inner)
7291 && GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (inner))
7292 && subreg_lowpart_p (x))
7294 rtx newer = force_to_mode (tem, mode, ~(HOST_WIDE_INT) 0, 0);
7296 /* If we have something other than a SUBREG, we might have
7297 done an expansion, so rerun ourselves. */
7298 if (GET_CODE (newer) != SUBREG)
7299 newer = make_compound_operation (newer, in_code);
7301 /* force_to_mode can expand compounds. If it just re-expanded the
7302 compound, use gen_lowpart to convert to the desired mode. */
7303 if (rtx_equal_p (newer, x)
7304 /* Likewise if it re-expanded the compound only partially.
7305 This happens for SUBREG of ZERO_EXTRACT if they extract
7306 the same number of bits. */
7307 || (GET_CODE (newer) == SUBREG
7308 && (GET_CODE (SUBREG_REG (newer)) == LSHIFTRT
7309 || GET_CODE (SUBREG_REG (newer)) == ASHIFTRT)
7310 && GET_CODE (inner) == AND
7311 && rtx_equal_p (SUBREG_REG (newer), XEXP (inner, 0))))
7312 return gen_lowpart (GET_MODE (x), tem);
7328 x = gen_lowpart (mode, new_rtx);
7329 code = GET_CODE (x);
7332 /* Now recursively process each operand of this operation. */
7333 fmt = GET_RTX_FORMAT (code);
7334 for (i = 0; i < GET_RTX_LENGTH (code); i++)
7337 new_rtx = make_compound_operation (XEXP (x, i), next_code);
7338 SUBST (XEXP (x, i), new_rtx);
7340 else if (fmt[i] == 'E')
7341 for (j = 0; j < XVECLEN (x, i); j++)
7343 new_rtx = make_compound_operation (XVECEXP (x, i, j), next_code);
7344 SUBST (XVECEXP (x, i, j), new_rtx);
7347 /* If this is a commutative operation, the changes to the operands
7348 may have made it noncanonical. */
7349 if (COMMUTATIVE_ARITH_P (x)
7350 && swap_commutative_operands_p (XEXP (x, 0), XEXP (x, 1)))
7353 SUBST (XEXP (x, 0), XEXP (x, 1));
7354 SUBST (XEXP (x, 1), tem);
7360 /* Given M see if it is a value that would select a field of bits
7361 within an item, but not the entire word. Return -1 if not.
7362 Otherwise, return the starting position of the field, where 0 is the
7365 *PLEN is set to the length of the field. */
7368 get_pos_from_mask (unsigned HOST_WIDE_INT m, unsigned HOST_WIDE_INT *plen)
7370 /* Get the bit number of the first 1 bit from the right, -1 if none. */
7371 int pos = exact_log2 (m & -m);
7375 /* Now shift off the low-order zero bits and see if we have a
7376 power of two minus 1. */
7377 len = exact_log2 ((m >> pos) + 1);
7386 /* If X refers to a register that equals REG in value, replace these
7387 references with REG. */
7389 canon_reg_for_combine (rtx x, rtx reg)
7396 enum rtx_code code = GET_CODE (x);
7397 switch (GET_RTX_CLASS (code))
7400 op0 = canon_reg_for_combine (XEXP (x, 0), reg);
7401 if (op0 != XEXP (x, 0))
7402 return simplify_gen_unary (GET_CODE (x), GET_MODE (x), op0,
7407 case RTX_COMM_ARITH:
7408 op0 = canon_reg_for_combine (XEXP (x, 0), reg);
7409 op1 = canon_reg_for_combine (XEXP (x, 1), reg);
7410 if (op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
7411 return simplify_gen_binary (GET_CODE (x), GET_MODE (x), op0, op1);
7415 case RTX_COMM_COMPARE:
7416 op0 = canon_reg_for_combine (XEXP (x, 0), reg);
7417 op1 = canon_reg_for_combine (XEXP (x, 1), reg);
7418 if (op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
7419 return simplify_gen_relational (GET_CODE (x), GET_MODE (x),
7420 GET_MODE (op0), op0, op1);
7424 case RTX_BITFIELD_OPS:
7425 op0 = canon_reg_for_combine (XEXP (x, 0), reg);
7426 op1 = canon_reg_for_combine (XEXP (x, 1), reg);
7427 op2 = canon_reg_for_combine (XEXP (x, 2), reg);
7428 if (op0 != XEXP (x, 0) || op1 != XEXP (x, 1) || op2 != XEXP (x, 2))
7429 return simplify_gen_ternary (GET_CODE (x), GET_MODE (x),
7430 GET_MODE (op0), op0, op1, op2);
7435 if (rtx_equal_p (get_last_value (reg), x)
7436 || rtx_equal_p (reg, get_last_value (x)))
7445 fmt = GET_RTX_FORMAT (code);
7447 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
7450 rtx op = canon_reg_for_combine (XEXP (x, i), reg);
7451 if (op != XEXP (x, i))
7461 else if (fmt[i] == 'E')
7464 for (j = 0; j < XVECLEN (x, i); j++)
7466 rtx op = canon_reg_for_combine (XVECEXP (x, i, j), reg);
7467 if (op != XVECEXP (x, i, j))
7474 XVECEXP (x, i, j) = op;
7485 /* Return X converted to MODE. If the value is already truncated to
7486 MODE we can just return a subreg even though in the general case we
7487 would need an explicit truncation. */
7490 gen_lowpart_or_truncate (enum machine_mode mode, rtx x)
7492 if (!CONST_INT_P (x)
7493 && GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (x))
7494 && !TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode),
7495 GET_MODE_BITSIZE (GET_MODE (x)))
7496 && !(REG_P (x) && reg_truncated_to_mode (mode, x)))
7498 /* Bit-cast X into an integer mode. */
7499 if (!SCALAR_INT_MODE_P (GET_MODE (x)))
7500 x = gen_lowpart (int_mode_for_mode (GET_MODE (x)), x);
7501 x = simplify_gen_unary (TRUNCATE, int_mode_for_mode (mode),
7505 return gen_lowpart (mode, x);
7508 /* See if X can be simplified knowing that we will only refer to it in
7509 MODE and will only refer to those bits that are nonzero in MASK.
7510 If other bits are being computed or if masking operations are done
7511 that select a superset of the bits in MASK, they can sometimes be
7514 Return a possibly simplified expression, but always convert X to
7515 MODE. If X is a CONST_INT, AND the CONST_INT with MASK.
7517 If JUST_SELECT is nonzero, don't optimize by noticing that bits in MASK
7518 are all off in X. This is used when X will be complemented, by either
7519 NOT, NEG, or XOR. */
7522 force_to_mode (rtx x, enum machine_mode mode, unsigned HOST_WIDE_INT mask,
7525 enum rtx_code code = GET_CODE (x);
7526 int next_select = just_select || code == XOR || code == NOT || code == NEG;
7527 enum machine_mode op_mode;
7528 unsigned HOST_WIDE_INT fuller_mask, nonzero;
7531 /* If this is a CALL or ASM_OPERANDS, don't do anything. Some of the
7532 code below will do the wrong thing since the mode of such an
7533 expression is VOIDmode.
7535 Also do nothing if X is a CLOBBER; this can happen if X was
7536 the return value from a call to gen_lowpart. */
7537 if (code == CALL || code == ASM_OPERANDS || code == CLOBBER)
7540 /* We want to perform the operation is its present mode unless we know
7541 that the operation is valid in MODE, in which case we do the operation
7543 op_mode = ((GET_MODE_CLASS (mode) == GET_MODE_CLASS (GET_MODE (x))
7544 && have_insn_for (code, mode))
7545 ? mode : GET_MODE (x));
7547 /* It is not valid to do a right-shift in a narrower mode
7548 than the one it came in with. */
7549 if ((code == LSHIFTRT || code == ASHIFTRT)
7550 && GET_MODE_BITSIZE (mode) < GET_MODE_BITSIZE (GET_MODE (x)))
7551 op_mode = GET_MODE (x);
7553 /* Truncate MASK to fit OP_MODE. */
7555 mask &= GET_MODE_MASK (op_mode);
7557 /* When we have an arithmetic operation, or a shift whose count we
7558 do not know, we need to assume that all bits up to the highest-order
7559 bit in MASK will be needed. This is how we form such a mask. */
7560 if (mask & ((unsigned HOST_WIDE_INT) 1 << (HOST_BITS_PER_WIDE_INT - 1)))
7561 fuller_mask = ~(unsigned HOST_WIDE_INT) 0;
7563 fuller_mask = (((unsigned HOST_WIDE_INT) 1 << (floor_log2 (mask) + 1))
7566 /* Determine what bits of X are guaranteed to be (non)zero. */
7567 nonzero = nonzero_bits (x, mode);
7569 /* If none of the bits in X are needed, return a zero. */
7570 if (!just_select && (nonzero & mask) == 0 && !side_effects_p (x))
7573 /* If X is a CONST_INT, return a new one. Do this here since the
7574 test below will fail. */
7575 if (CONST_INT_P (x))
7577 if (SCALAR_INT_MODE_P (mode))
7578 return gen_int_mode (INTVAL (x) & mask, mode);
7581 x = GEN_INT (INTVAL (x) & mask);
7582 return gen_lowpart_common (mode, x);
7586 /* If X is narrower than MODE and we want all the bits in X's mode, just
7587 get X in the proper mode. */
7588 if (GET_MODE_SIZE (GET_MODE (x)) < GET_MODE_SIZE (mode)
7589 && (GET_MODE_MASK (GET_MODE (x)) & ~mask) == 0)
7590 return gen_lowpart (mode, x);
7592 /* We can ignore the effect of a SUBREG if it narrows the mode or
7593 if the constant masks to zero all the bits the mode doesn't have. */
7594 if (GET_CODE (x) == SUBREG
7595 && subreg_lowpart_p (x)
7596 && ((GET_MODE_SIZE (GET_MODE (x))
7597 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
7599 & GET_MODE_MASK (GET_MODE (x))
7600 & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (x)))))))
7601 return force_to_mode (SUBREG_REG (x), mode, mask, next_select);
7603 /* The arithmetic simplifications here only work for scalar integer modes. */
7604 if (!SCALAR_INT_MODE_P (mode) || !SCALAR_INT_MODE_P (GET_MODE (x)))
7605 return gen_lowpart_or_truncate (mode, x);
7610 /* If X is a (clobber (const_int)), return it since we know we are
7611 generating something that won't match. */
7618 x = expand_compound_operation (x);
7619 if (GET_CODE (x) != code)
7620 return force_to_mode (x, mode, mask, next_select);
7624 /* Similarly for a truncate. */
7625 return force_to_mode (XEXP (x, 0), mode, mask, next_select);
7628 /* If this is an AND with a constant, convert it into an AND
7629 whose constant is the AND of that constant with MASK. If it
7630 remains an AND of MASK, delete it since it is redundant. */
7632 if (CONST_INT_P (XEXP (x, 1)))
7634 x = simplify_and_const_int (x, op_mode, XEXP (x, 0),
7635 mask & INTVAL (XEXP (x, 1)));
7637 /* If X is still an AND, see if it is an AND with a mask that
7638 is just some low-order bits. If so, and it is MASK, we don't
7641 if (GET_CODE (x) == AND && CONST_INT_P (XEXP (x, 1))
7642 && ((INTVAL (XEXP (x, 1)) & GET_MODE_MASK (GET_MODE (x)))
7646 /* If it remains an AND, try making another AND with the bits
7647 in the mode mask that aren't in MASK turned on. If the
7648 constant in the AND is wide enough, this might make a
7649 cheaper constant. */
7651 if (GET_CODE (x) == AND && CONST_INT_P (XEXP (x, 1))
7652 && GET_MODE_MASK (GET_MODE (x)) != mask
7653 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT)
7655 HOST_WIDE_INT cval = (INTVAL (XEXP (x, 1))
7656 | (GET_MODE_MASK (GET_MODE (x)) & ~mask));
7657 int width = GET_MODE_BITSIZE (GET_MODE (x));
7660 /* If MODE is narrower than HOST_WIDE_INT and CVAL is a negative
7661 number, sign extend it. */
7662 if (width > 0 && width < HOST_BITS_PER_WIDE_INT
7663 && (cval & ((HOST_WIDE_INT) 1 << (width - 1))) != 0)
7664 cval |= (HOST_WIDE_INT) -1 << width;
7666 y = simplify_gen_binary (AND, GET_MODE (x),
7667 XEXP (x, 0), GEN_INT (cval));
7668 if (rtx_cost (y, SET, optimize_this_for_speed_p)
7669 < rtx_cost (x, SET, optimize_this_for_speed_p))
7679 /* In (and (plus FOO C1) M), if M is a mask that just turns off
7680 low-order bits (as in an alignment operation) and FOO is already
7681 aligned to that boundary, mask C1 to that boundary as well.
7682 This may eliminate that PLUS and, later, the AND. */
7685 unsigned int width = GET_MODE_BITSIZE (mode);
7686 unsigned HOST_WIDE_INT smask = mask;
7688 /* If MODE is narrower than HOST_WIDE_INT and mask is a negative
7689 number, sign extend it. */
7691 if (width < HOST_BITS_PER_WIDE_INT
7692 && (smask & ((HOST_WIDE_INT) 1 << (width - 1))) != 0)
7693 smask |= (HOST_WIDE_INT) -1 << width;
7695 if (CONST_INT_P (XEXP (x, 1))
7696 && exact_log2 (- smask) >= 0
7697 && (nonzero_bits (XEXP (x, 0), mode) & ~smask) == 0
7698 && (INTVAL (XEXP (x, 1)) & ~smask) != 0)
7699 return force_to_mode (plus_constant (XEXP (x, 0),
7700 (INTVAL (XEXP (x, 1)) & smask)),
7701 mode, smask, next_select);
7704 /* ... fall through ... */
7707 /* For PLUS, MINUS and MULT, we need any bits less significant than the
7708 most significant bit in MASK since carries from those bits will
7709 affect the bits we are interested in. */
7714 /* If X is (minus C Y) where C's least set bit is larger than any bit
7715 in the mask, then we may replace with (neg Y). */
7716 if (CONST_INT_P (XEXP (x, 0))
7717 && (((unsigned HOST_WIDE_INT) (INTVAL (XEXP (x, 0))
7718 & -INTVAL (XEXP (x, 0))))
7721 x = simplify_gen_unary (NEG, GET_MODE (x), XEXP (x, 1),
7723 return force_to_mode (x, mode, mask, next_select);
7726 /* Similarly, if C contains every bit in the fuller_mask, then we may
7727 replace with (not Y). */
7728 if (CONST_INT_P (XEXP (x, 0))
7729 && ((INTVAL (XEXP (x, 0)) | (HOST_WIDE_INT) fuller_mask)
7730 == INTVAL (XEXP (x, 0))))
7732 x = simplify_gen_unary (NOT, GET_MODE (x),
7733 XEXP (x, 1), GET_MODE (x));
7734 return force_to_mode (x, mode, mask, next_select);
7742 /* If X is (ior (lshiftrt FOO C1) C2), try to commute the IOR and
7743 LSHIFTRT so we end up with an (and (lshiftrt (ior ...) ...) ...)
7744 operation which may be a bitfield extraction. Ensure that the
7745 constant we form is not wider than the mode of X. */
7747 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
7748 && CONST_INT_P (XEXP (XEXP (x, 0), 1))
7749 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
7750 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT
7751 && CONST_INT_P (XEXP (x, 1))
7752 && ((INTVAL (XEXP (XEXP (x, 0), 1))
7753 + floor_log2 (INTVAL (XEXP (x, 1))))
7754 < GET_MODE_BITSIZE (GET_MODE (x)))
7755 && (INTVAL (XEXP (x, 1))
7756 & ~nonzero_bits (XEXP (x, 0), GET_MODE (x))) == 0)
7758 temp = GEN_INT ((INTVAL (XEXP (x, 1)) & mask)
7759 << INTVAL (XEXP (XEXP (x, 0), 1)));
7760 temp = simplify_gen_binary (GET_CODE (x), GET_MODE (x),
7761 XEXP (XEXP (x, 0), 0), temp);
7762 x = simplify_gen_binary (LSHIFTRT, GET_MODE (x), temp,
7763 XEXP (XEXP (x, 0), 1));
7764 return force_to_mode (x, mode, mask, next_select);
7768 /* For most binary operations, just propagate into the operation and
7769 change the mode if we have an operation of that mode. */
7771 op0 = force_to_mode (XEXP (x, 0), mode, mask, next_select);
7772 op1 = force_to_mode (XEXP (x, 1), mode, mask, next_select);
7774 /* If we ended up truncating both operands, truncate the result of the
7775 operation instead. */
7776 if (GET_CODE (op0) == TRUNCATE
7777 && GET_CODE (op1) == TRUNCATE)
7779 op0 = XEXP (op0, 0);
7780 op1 = XEXP (op1, 0);
7783 op0 = gen_lowpart_or_truncate (op_mode, op0);
7784 op1 = gen_lowpart_or_truncate (op_mode, op1);
7786 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
7787 x = simplify_gen_binary (code, op_mode, op0, op1);
7791 /* For left shifts, do the same, but just for the first operand.
7792 However, we cannot do anything with shifts where we cannot
7793 guarantee that the counts are smaller than the size of the mode
7794 because such a count will have a different meaning in a
7797 if (! (CONST_INT_P (XEXP (x, 1))
7798 && INTVAL (XEXP (x, 1)) >= 0
7799 && INTVAL (XEXP (x, 1)) < GET_MODE_BITSIZE (mode))
7800 && ! (GET_MODE (XEXP (x, 1)) != VOIDmode
7801 && (nonzero_bits (XEXP (x, 1), GET_MODE (XEXP (x, 1)))
7802 < (unsigned HOST_WIDE_INT) GET_MODE_BITSIZE (mode))))
7805 /* If the shift count is a constant and we can do arithmetic in
7806 the mode of the shift, refine which bits we need. Otherwise, use the
7807 conservative form of the mask. */
7808 if (CONST_INT_P (XEXP (x, 1))
7809 && INTVAL (XEXP (x, 1)) >= 0
7810 && INTVAL (XEXP (x, 1)) < GET_MODE_BITSIZE (op_mode)
7811 && GET_MODE_BITSIZE (op_mode) <= HOST_BITS_PER_WIDE_INT)
7812 mask >>= INTVAL (XEXP (x, 1));
7816 op0 = gen_lowpart_or_truncate (op_mode,
7817 force_to_mode (XEXP (x, 0), op_mode,
7818 mask, next_select));
7820 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0))
7821 x = simplify_gen_binary (code, op_mode, op0, XEXP (x, 1));
7825 /* Here we can only do something if the shift count is a constant,
7826 this shift constant is valid for the host, and we can do arithmetic
7829 if (CONST_INT_P (XEXP (x, 1))
7830 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT
7831 && GET_MODE_BITSIZE (op_mode) <= HOST_BITS_PER_WIDE_INT)
7833 rtx inner = XEXP (x, 0);
7834 unsigned HOST_WIDE_INT inner_mask;
7836 /* Select the mask of the bits we need for the shift operand. */
7837 inner_mask = mask << INTVAL (XEXP (x, 1));
7839 /* We can only change the mode of the shift if we can do arithmetic
7840 in the mode of the shift and INNER_MASK is no wider than the
7841 width of X's mode. */
7842 if ((inner_mask & ~GET_MODE_MASK (GET_MODE (x))) != 0)
7843 op_mode = GET_MODE (x);
7845 inner = force_to_mode (inner, op_mode, inner_mask, next_select);
7847 if (GET_MODE (x) != op_mode || inner != XEXP (x, 0))
7848 x = simplify_gen_binary (LSHIFTRT, op_mode, inner, XEXP (x, 1));
7851 /* If we have (and (lshiftrt FOO C1) C2) where the combination of the
7852 shift and AND produces only copies of the sign bit (C2 is one less
7853 than a power of two), we can do this with just a shift. */
7855 if (GET_CODE (x) == LSHIFTRT
7856 && CONST_INT_P (XEXP (x, 1))
7857 /* The shift puts one of the sign bit copies in the least significant
7859 && ((INTVAL (XEXP (x, 1))
7860 + num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0))))
7861 >= GET_MODE_BITSIZE (GET_MODE (x)))
7862 && exact_log2 (mask + 1) >= 0
7863 /* Number of bits left after the shift must be more than the mask
7865 && ((INTVAL (XEXP (x, 1)) + exact_log2 (mask + 1))
7866 <= GET_MODE_BITSIZE (GET_MODE (x)))
7867 /* Must be more sign bit copies than the mask needs. */
7868 && ((int) num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
7869 >= exact_log2 (mask + 1)))
7870 x = simplify_gen_binary (LSHIFTRT, GET_MODE (x), XEXP (x, 0),
7871 GEN_INT (GET_MODE_BITSIZE (GET_MODE (x))
7872 - exact_log2 (mask + 1)));
7877 /* If we are just looking for the sign bit, we don't need this shift at
7878 all, even if it has a variable count. */
7879 if (GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
7880 && (mask == ((unsigned HOST_WIDE_INT) 1
7881 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
7882 return force_to_mode (XEXP (x, 0), mode, mask, next_select);
7884 /* If this is a shift by a constant, get a mask that contains those bits
7885 that are not copies of the sign bit. We then have two cases: If
7886 MASK only includes those bits, this can be a logical shift, which may
7887 allow simplifications. If MASK is a single-bit field not within
7888 those bits, we are requesting a copy of the sign bit and hence can
7889 shift the sign bit to the appropriate location. */
7891 if (CONST_INT_P (XEXP (x, 1)) && INTVAL (XEXP (x, 1)) >= 0
7892 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT)
7896 /* If the considered data is wider than HOST_WIDE_INT, we can't
7897 represent a mask for all its bits in a single scalar.
7898 But we only care about the lower bits, so calculate these. */
7900 if (GET_MODE_BITSIZE (GET_MODE (x)) > HOST_BITS_PER_WIDE_INT)
7902 nonzero = ~(HOST_WIDE_INT) 0;
7904 /* GET_MODE_BITSIZE (GET_MODE (x)) - INTVAL (XEXP (x, 1))
7905 is the number of bits a full-width mask would have set.
7906 We need only shift if these are fewer than nonzero can
7907 hold. If not, we must keep all bits set in nonzero. */
7909 if (GET_MODE_BITSIZE (GET_MODE (x)) - INTVAL (XEXP (x, 1))
7910 < HOST_BITS_PER_WIDE_INT)
7911 nonzero >>= INTVAL (XEXP (x, 1))
7912 + HOST_BITS_PER_WIDE_INT
7913 - GET_MODE_BITSIZE (GET_MODE (x)) ;
7917 nonzero = GET_MODE_MASK (GET_MODE (x));
7918 nonzero >>= INTVAL (XEXP (x, 1));
7921 if ((mask & ~nonzero) == 0)
7923 x = simplify_shift_const (NULL_RTX, LSHIFTRT, GET_MODE (x),
7924 XEXP (x, 0), INTVAL (XEXP (x, 1)));
7925 if (GET_CODE (x) != ASHIFTRT)
7926 return force_to_mode (x, mode, mask, next_select);
7929 else if ((i = exact_log2 (mask)) >= 0)
7931 x = simplify_shift_const
7932 (NULL_RTX, LSHIFTRT, GET_MODE (x), XEXP (x, 0),
7933 GET_MODE_BITSIZE (GET_MODE (x)) - 1 - i);
7935 if (GET_CODE (x) != ASHIFTRT)
7936 return force_to_mode (x, mode, mask, next_select);
7940 /* If MASK is 1, convert this to an LSHIFTRT. This can be done
7941 even if the shift count isn't a constant. */
7943 x = simplify_gen_binary (LSHIFTRT, GET_MODE (x),
7944 XEXP (x, 0), XEXP (x, 1));
7948 /* If this is a zero- or sign-extension operation that just affects bits
7949 we don't care about, remove it. Be sure the call above returned
7950 something that is still a shift. */
7952 if ((GET_CODE (x) == LSHIFTRT || GET_CODE (x) == ASHIFTRT)
7953 && CONST_INT_P (XEXP (x, 1))
7954 && INTVAL (XEXP (x, 1)) >= 0
7955 && (INTVAL (XEXP (x, 1))
7956 <= GET_MODE_BITSIZE (GET_MODE (x)) - (floor_log2 (mask) + 1))
7957 && GET_CODE (XEXP (x, 0)) == ASHIFT
7958 && XEXP (XEXP (x, 0), 1) == XEXP (x, 1))
7959 return force_to_mode (XEXP (XEXP (x, 0), 0), mode, mask,
7966 /* If the shift count is constant and we can do computations
7967 in the mode of X, compute where the bits we care about are.
7968 Otherwise, we can't do anything. Don't change the mode of
7969 the shift or propagate MODE into the shift, though. */
7970 if (CONST_INT_P (XEXP (x, 1))
7971 && INTVAL (XEXP (x, 1)) >= 0)
7973 temp = simplify_binary_operation (code == ROTATE ? ROTATERT : ROTATE,
7974 GET_MODE (x), GEN_INT (mask),
7976 if (temp && CONST_INT_P (temp))
7978 force_to_mode (XEXP (x, 0), GET_MODE (x),
7979 INTVAL (temp), next_select));
7984 /* If we just want the low-order bit, the NEG isn't needed since it
7985 won't change the low-order bit. */
7987 return force_to_mode (XEXP (x, 0), mode, mask, just_select);
7989 /* We need any bits less significant than the most significant bit in
7990 MASK since carries from those bits will affect the bits we are
7996 /* (not FOO) is (xor FOO CONST), so if FOO is an LSHIFTRT, we can do the
7997 same as the XOR case above. Ensure that the constant we form is not
7998 wider than the mode of X. */
8000 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
8001 && CONST_INT_P (XEXP (XEXP (x, 0), 1))
8002 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
8003 && (INTVAL (XEXP (XEXP (x, 0), 1)) + floor_log2 (mask)
8004 < GET_MODE_BITSIZE (GET_MODE (x)))
8005 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT)
8007 temp = gen_int_mode (mask << INTVAL (XEXP (XEXP (x, 0), 1)),
8009 temp = simplify_gen_binary (XOR, GET_MODE (x),
8010 XEXP (XEXP (x, 0), 0), temp);
8011 x = simplify_gen_binary (LSHIFTRT, GET_MODE (x),
8012 temp, XEXP (XEXP (x, 0), 1));
8014 return force_to_mode (x, mode, mask, next_select);
8017 /* (and (not FOO) CONST) is (not (or FOO (not CONST))), so we must
8018 use the full mask inside the NOT. */
8022 op0 = gen_lowpart_or_truncate (op_mode,
8023 force_to_mode (XEXP (x, 0), mode, mask,
8025 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0))
8026 x = simplify_gen_unary (code, op_mode, op0, op_mode);
8030 /* (and (ne FOO 0) CONST) can be (and FOO CONST) if CONST is included
8031 in STORE_FLAG_VALUE and FOO has a single bit that might be nonzero,
8032 which is equal to STORE_FLAG_VALUE. */
8033 if ((mask & ~STORE_FLAG_VALUE) == 0 && XEXP (x, 1) == const0_rtx
8034 && GET_MODE (XEXP (x, 0)) == mode
8035 && exact_log2 (nonzero_bits (XEXP (x, 0), mode)) >= 0
8036 && (nonzero_bits (XEXP (x, 0), mode)
8037 == (unsigned HOST_WIDE_INT) STORE_FLAG_VALUE))
8038 return force_to_mode (XEXP (x, 0), mode, mask, next_select);
8043 /* We have no way of knowing if the IF_THEN_ELSE can itself be
8044 written in a narrower mode. We play it safe and do not do so. */
8047 gen_lowpart_or_truncate (GET_MODE (x),
8048 force_to_mode (XEXP (x, 1), mode,
8049 mask, next_select)));
8051 gen_lowpart_or_truncate (GET_MODE (x),
8052 force_to_mode (XEXP (x, 2), mode,
8053 mask, next_select)));
8060 /* Ensure we return a value of the proper mode. */
8061 return gen_lowpart_or_truncate (mode, x);
8064 /* Return nonzero if X is an expression that has one of two values depending on
8065 whether some other value is zero or nonzero. In that case, we return the
8066 value that is being tested, *PTRUE is set to the value if the rtx being
8067 returned has a nonzero value, and *PFALSE is set to the other alternative.
8069 If we return zero, we set *PTRUE and *PFALSE to X. */
8072 if_then_else_cond (rtx x, rtx *ptrue, rtx *pfalse)
8074 enum machine_mode mode = GET_MODE (x);
8075 enum rtx_code code = GET_CODE (x);
8076 rtx cond0, cond1, true0, true1, false0, false1;
8077 unsigned HOST_WIDE_INT nz;
8079 /* If we are comparing a value against zero, we are done. */
8080 if ((code == NE || code == EQ)
8081 && XEXP (x, 1) == const0_rtx)
8083 *ptrue = (code == NE) ? const_true_rtx : const0_rtx;
8084 *pfalse = (code == NE) ? const0_rtx : const_true_rtx;
8088 /* If this is a unary operation whose operand has one of two values, apply
8089 our opcode to compute those values. */
8090 else if (UNARY_P (x)
8091 && (cond0 = if_then_else_cond (XEXP (x, 0), &true0, &false0)) != 0)
8093 *ptrue = simplify_gen_unary (code, mode, true0, GET_MODE (XEXP (x, 0)));
8094 *pfalse = simplify_gen_unary (code, mode, false0,
8095 GET_MODE (XEXP (x, 0)));
8099 /* If this is a COMPARE, do nothing, since the IF_THEN_ELSE we would
8100 make can't possibly match and would suppress other optimizations. */
8101 else if (code == COMPARE)
8104 /* If this is a binary operation, see if either side has only one of two
8105 values. If either one does or if both do and they are conditional on
8106 the same value, compute the new true and false values. */
8107 else if (BINARY_P (x))
8109 cond0 = if_then_else_cond (XEXP (x, 0), &true0, &false0);
8110 cond1 = if_then_else_cond (XEXP (x, 1), &true1, &false1);
8112 if ((cond0 != 0 || cond1 != 0)
8113 && ! (cond0 != 0 && cond1 != 0 && ! rtx_equal_p (cond0, cond1)))
8115 /* If if_then_else_cond returned zero, then true/false are the
8116 same rtl. We must copy one of them to prevent invalid rtl
8119 true0 = copy_rtx (true0);
8120 else if (cond1 == 0)
8121 true1 = copy_rtx (true1);
8123 if (COMPARISON_P (x))
8125 *ptrue = simplify_gen_relational (code, mode, VOIDmode,
8127 *pfalse = simplify_gen_relational (code, mode, VOIDmode,
8132 *ptrue = simplify_gen_binary (code, mode, true0, true1);
8133 *pfalse = simplify_gen_binary (code, mode, false0, false1);
8136 return cond0 ? cond0 : cond1;
8139 /* See if we have PLUS, IOR, XOR, MINUS or UMAX, where one of the
8140 operands is zero when the other is nonzero, and vice-versa,
8141 and STORE_FLAG_VALUE is 1 or -1. */
8143 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
8144 && (code == PLUS || code == IOR || code == XOR || code == MINUS
8146 && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT)
8148 rtx op0 = XEXP (XEXP (x, 0), 1);
8149 rtx op1 = XEXP (XEXP (x, 1), 1);
8151 cond0 = XEXP (XEXP (x, 0), 0);
8152 cond1 = XEXP (XEXP (x, 1), 0);
8154 if (COMPARISON_P (cond0)
8155 && COMPARISON_P (cond1)
8156 && ((GET_CODE (cond0) == reversed_comparison_code (cond1, NULL)
8157 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0))
8158 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1)))
8159 || ((swap_condition (GET_CODE (cond0))
8160 == reversed_comparison_code (cond1, NULL))
8161 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1))
8162 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0))))
8163 && ! side_effects_p (x))
8165 *ptrue = simplify_gen_binary (MULT, mode, op0, const_true_rtx);
8166 *pfalse = simplify_gen_binary (MULT, mode,
8168 ? simplify_gen_unary (NEG, mode,
8176 /* Similarly for MULT, AND and UMIN, except that for these the result
8178 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
8179 && (code == MULT || code == AND || code == UMIN)
8180 && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT)
8182 cond0 = XEXP (XEXP (x, 0), 0);
8183 cond1 = XEXP (XEXP (x, 1), 0);
8185 if (COMPARISON_P (cond0)
8186 && COMPARISON_P (cond1)
8187 && ((GET_CODE (cond0) == reversed_comparison_code (cond1, NULL)
8188 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0))
8189 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1)))
8190 || ((swap_condition (GET_CODE (cond0))
8191 == reversed_comparison_code (cond1, NULL))
8192 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1))
8193 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0))))
8194 && ! side_effects_p (x))
8196 *ptrue = *pfalse = const0_rtx;
8202 else if (code == IF_THEN_ELSE)
8204 /* If we have IF_THEN_ELSE already, extract the condition and
8205 canonicalize it if it is NE or EQ. */
8206 cond0 = XEXP (x, 0);
8207 *ptrue = XEXP (x, 1), *pfalse = XEXP (x, 2);
8208 if (GET_CODE (cond0) == NE && XEXP (cond0, 1) == const0_rtx)
8209 return XEXP (cond0, 0);
8210 else if (GET_CODE (cond0) == EQ && XEXP (cond0, 1) == const0_rtx)
8212 *ptrue = XEXP (x, 2), *pfalse = XEXP (x, 1);
8213 return XEXP (cond0, 0);
8219 /* If X is a SUBREG, we can narrow both the true and false values
8220 if the inner expression, if there is a condition. */
8221 else if (code == SUBREG
8222 && 0 != (cond0 = if_then_else_cond (SUBREG_REG (x),
8225 true0 = simplify_gen_subreg (mode, true0,
8226 GET_MODE (SUBREG_REG (x)), SUBREG_BYTE (x));
8227 false0 = simplify_gen_subreg (mode, false0,
8228 GET_MODE (SUBREG_REG (x)), SUBREG_BYTE (x));
8229 if (true0 && false0)
8237 /* If X is a constant, this isn't special and will cause confusions
8238 if we treat it as such. Likewise if it is equivalent to a constant. */
8239 else if (CONSTANT_P (x)
8240 || ((cond0 = get_last_value (x)) != 0 && CONSTANT_P (cond0)))
8243 /* If we're in BImode, canonicalize on 0 and STORE_FLAG_VALUE, as that
8244 will be least confusing to the rest of the compiler. */
8245 else if (mode == BImode)
8247 *ptrue = GEN_INT (STORE_FLAG_VALUE), *pfalse = const0_rtx;
8251 /* If X is known to be either 0 or -1, those are the true and
8252 false values when testing X. */
8253 else if (x == constm1_rtx || x == const0_rtx
8254 || (mode != VOIDmode
8255 && num_sign_bit_copies (x, mode) == GET_MODE_BITSIZE (mode)))
8257 *ptrue = constm1_rtx, *pfalse = const0_rtx;
8261 /* Likewise for 0 or a single bit. */
8262 else if (SCALAR_INT_MODE_P (mode)
8263 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
8264 && exact_log2 (nz = nonzero_bits (x, mode)) >= 0)
8266 *ptrue = gen_int_mode (nz, mode), *pfalse = const0_rtx;
8270 /* Otherwise fail; show no condition with true and false values the same. */
8271 *ptrue = *pfalse = x;
8275 /* Return the value of expression X given the fact that condition COND
8276 is known to be true when applied to REG as its first operand and VAL
8277 as its second. X is known to not be shared and so can be modified in
8280 We only handle the simplest cases, and specifically those cases that
8281 arise with IF_THEN_ELSE expressions. */
8284 known_cond (rtx x, enum rtx_code cond, rtx reg, rtx val)
8286 enum rtx_code code = GET_CODE (x);
8291 if (side_effects_p (x))
8294 /* If either operand of the condition is a floating point value,
8295 then we have to avoid collapsing an EQ comparison. */
8297 && rtx_equal_p (x, reg)
8298 && ! FLOAT_MODE_P (GET_MODE (x))
8299 && ! FLOAT_MODE_P (GET_MODE (val)))
8302 if (cond == UNEQ && rtx_equal_p (x, reg))
8305 /* If X is (abs REG) and we know something about REG's relationship
8306 with zero, we may be able to simplify this. */
8308 if (code == ABS && rtx_equal_p (XEXP (x, 0), reg) && val == const0_rtx)
8311 case GE: case GT: case EQ:
8314 return simplify_gen_unary (NEG, GET_MODE (XEXP (x, 0)),
8316 GET_MODE (XEXP (x, 0)));
8321 /* The only other cases we handle are MIN, MAX, and comparisons if the
8322 operands are the same as REG and VAL. */
8324 else if (COMPARISON_P (x) || COMMUTATIVE_ARITH_P (x))
8326 if (rtx_equal_p (XEXP (x, 0), val))
8327 cond = swap_condition (cond), temp = val, val = reg, reg = temp;
8329 if (rtx_equal_p (XEXP (x, 0), reg) && rtx_equal_p (XEXP (x, 1), val))
8331 if (COMPARISON_P (x))
8333 if (comparison_dominates_p (cond, code))
8334 return const_true_rtx;
8336 code = reversed_comparison_code (x, NULL);
8338 && comparison_dominates_p (cond, code))
8343 else if (code == SMAX || code == SMIN
8344 || code == UMIN || code == UMAX)
8346 int unsignedp = (code == UMIN || code == UMAX);
8348 /* Do not reverse the condition when it is NE or EQ.
8349 This is because we cannot conclude anything about
8350 the value of 'SMAX (x, y)' when x is not equal to y,
8351 but we can when x equals y. */
8352 if ((code == SMAX || code == UMAX)
8353 && ! (cond == EQ || cond == NE))
8354 cond = reverse_condition (cond);
8359 return unsignedp ? x : XEXP (x, 1);
8361 return unsignedp ? x : XEXP (x, 0);
8363 return unsignedp ? XEXP (x, 1) : x;
8365 return unsignedp ? XEXP (x, 0) : x;
8372 else if (code == SUBREG)
8374 enum machine_mode inner_mode = GET_MODE (SUBREG_REG (x));
8375 rtx new_rtx, r = known_cond (SUBREG_REG (x), cond, reg, val);
8377 if (SUBREG_REG (x) != r)
8379 /* We must simplify subreg here, before we lose track of the
8380 original inner_mode. */
8381 new_rtx = simplify_subreg (GET_MODE (x), r,
8382 inner_mode, SUBREG_BYTE (x));
8386 SUBST (SUBREG_REG (x), r);
8391 /* We don't have to handle SIGN_EXTEND here, because even in the
8392 case of replacing something with a modeless CONST_INT, a
8393 CONST_INT is already (supposed to be) a valid sign extension for
8394 its narrower mode, which implies it's already properly
8395 sign-extended for the wider mode. Now, for ZERO_EXTEND, the
8396 story is different. */
8397 else if (code == ZERO_EXTEND)
8399 enum machine_mode inner_mode = GET_MODE (XEXP (x, 0));
8400 rtx new_rtx, r = known_cond (XEXP (x, 0), cond, reg, val);
8402 if (XEXP (x, 0) != r)
8404 /* We must simplify the zero_extend here, before we lose
8405 track of the original inner_mode. */
8406 new_rtx = simplify_unary_operation (ZERO_EXTEND, GET_MODE (x),
8411 SUBST (XEXP (x, 0), r);
8417 fmt = GET_RTX_FORMAT (code);
8418 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
8421 SUBST (XEXP (x, i), known_cond (XEXP (x, i), cond, reg, val));
8422 else if (fmt[i] == 'E')
8423 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
8424 SUBST (XVECEXP (x, i, j), known_cond (XVECEXP (x, i, j),
8431 /* See if X and Y are equal for the purposes of seeing if we can rewrite an
8432 assignment as a field assignment. */
8435 rtx_equal_for_field_assignment_p (rtx x, rtx y)
8437 if (x == y || rtx_equal_p (x, y))
8440 if (x == 0 || y == 0 || GET_MODE (x) != GET_MODE (y))
8443 /* Check for a paradoxical SUBREG of a MEM compared with the MEM.
8444 Note that all SUBREGs of MEM are paradoxical; otherwise they
8445 would have been rewritten. */
8446 if (MEM_P (x) && GET_CODE (y) == SUBREG
8447 && MEM_P (SUBREG_REG (y))
8448 && rtx_equal_p (SUBREG_REG (y),
8449 gen_lowpart (GET_MODE (SUBREG_REG (y)), x)))
8452 if (MEM_P (y) && GET_CODE (x) == SUBREG
8453 && MEM_P (SUBREG_REG (x))
8454 && rtx_equal_p (SUBREG_REG (x),
8455 gen_lowpart (GET_MODE (SUBREG_REG (x)), y)))
8458 /* We used to see if get_last_value of X and Y were the same but that's
8459 not correct. In one direction, we'll cause the assignment to have
8460 the wrong destination and in the case, we'll import a register into this
8461 insn that might have already have been dead. So fail if none of the
8462 above cases are true. */
8466 /* See if X, a SET operation, can be rewritten as a bit-field assignment.
8467 Return that assignment if so.
8469 We only handle the most common cases. */
8472 make_field_assignment (rtx x)
8474 rtx dest = SET_DEST (x);
8475 rtx src = SET_SRC (x);
8480 unsigned HOST_WIDE_INT len;
8482 enum machine_mode mode;
8484 /* If SRC was (and (not (ashift (const_int 1) POS)) DEST), this is
8485 a clear of a one-bit field. We will have changed it to
8486 (and (rotate (const_int -2) POS) DEST), so check for that. Also check
8489 if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == ROTATE
8490 && CONST_INT_P (XEXP (XEXP (src, 0), 0))
8491 && INTVAL (XEXP (XEXP (src, 0), 0)) == -2
8492 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
8494 assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1),
8497 return gen_rtx_SET (VOIDmode, assign, const0_rtx);
8501 if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == SUBREG
8502 && subreg_lowpart_p (XEXP (src, 0))
8503 && (GET_MODE_SIZE (GET_MODE (XEXP (src, 0)))
8504 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (src, 0)))))
8505 && GET_CODE (SUBREG_REG (XEXP (src, 0))) == ROTATE
8506 && CONST_INT_P (XEXP (SUBREG_REG (XEXP (src, 0)), 0))
8507 && INTVAL (XEXP (SUBREG_REG (XEXP (src, 0)), 0)) == -2
8508 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
8510 assign = make_extraction (VOIDmode, dest, 0,
8511 XEXP (SUBREG_REG (XEXP (src, 0)), 1),
8514 return gen_rtx_SET (VOIDmode, assign, const0_rtx);
8518 /* If SRC is (ior (ashift (const_int 1) POS) DEST), this is a set of a
8520 if (GET_CODE (src) == IOR && GET_CODE (XEXP (src, 0)) == ASHIFT
8521 && XEXP (XEXP (src, 0), 0) == const1_rtx
8522 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
8524 assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1),
8527 return gen_rtx_SET (VOIDmode, assign, const1_rtx);
8531 /* If DEST is already a field assignment, i.e. ZERO_EXTRACT, and the
8532 SRC is an AND with all bits of that field set, then we can discard
8534 if (GET_CODE (dest) == ZERO_EXTRACT
8535 && CONST_INT_P (XEXP (dest, 1))
8536 && GET_CODE (src) == AND
8537 && CONST_INT_P (XEXP (src, 1)))
8539 HOST_WIDE_INT width = INTVAL (XEXP (dest, 1));
8540 unsigned HOST_WIDE_INT and_mask = INTVAL (XEXP (src, 1));
8541 unsigned HOST_WIDE_INT ze_mask;
8543 if (width >= HOST_BITS_PER_WIDE_INT)
8546 ze_mask = ((unsigned HOST_WIDE_INT)1 << width) - 1;
8548 /* Complete overlap. We can remove the source AND. */
8549 if ((and_mask & ze_mask) == ze_mask)
8550 return gen_rtx_SET (VOIDmode, dest, XEXP (src, 0));
8552 /* Partial overlap. We can reduce the source AND. */
8553 if ((and_mask & ze_mask) != and_mask)
8555 mode = GET_MODE (src);
8556 src = gen_rtx_AND (mode, XEXP (src, 0),
8557 gen_int_mode (and_mask & ze_mask, mode));
8558 return gen_rtx_SET (VOIDmode, dest, src);
8562 /* The other case we handle is assignments into a constant-position
8563 field. They look like (ior/xor (and DEST C1) OTHER). If C1 represents
8564 a mask that has all one bits except for a group of zero bits and
8565 OTHER is known to have zeros where C1 has ones, this is such an
8566 assignment. Compute the position and length from C1. Shift OTHER
8567 to the appropriate position, force it to the required mode, and
8568 make the extraction. Check for the AND in both operands. */
8570 if (GET_CODE (src) != IOR && GET_CODE (src) != XOR)
8573 rhs = expand_compound_operation (XEXP (src, 0));
8574 lhs = expand_compound_operation (XEXP (src, 1));
8576 if (GET_CODE (rhs) == AND
8577 && CONST_INT_P (XEXP (rhs, 1))
8578 && rtx_equal_for_field_assignment_p (XEXP (rhs, 0), dest))
8579 c1 = INTVAL (XEXP (rhs, 1)), other = lhs;
8580 else if (GET_CODE (lhs) == AND
8581 && CONST_INT_P (XEXP (lhs, 1))
8582 && rtx_equal_for_field_assignment_p (XEXP (lhs, 0), dest))
8583 c1 = INTVAL (XEXP (lhs, 1)), other = rhs;
8587 pos = get_pos_from_mask ((~c1) & GET_MODE_MASK (GET_MODE (dest)), &len);
8588 if (pos < 0 || pos + len > GET_MODE_BITSIZE (GET_MODE (dest))
8589 || GET_MODE_BITSIZE (GET_MODE (dest)) > HOST_BITS_PER_WIDE_INT
8590 || (c1 & nonzero_bits (other, GET_MODE (dest))) != 0)
8593 assign = make_extraction (VOIDmode, dest, pos, NULL_RTX, len, 1, 1, 0);
8597 /* The mode to use for the source is the mode of the assignment, or of
8598 what is inside a possible STRICT_LOW_PART. */
8599 mode = (GET_CODE (assign) == STRICT_LOW_PART
8600 ? GET_MODE (XEXP (assign, 0)) : GET_MODE (assign));
8602 /* Shift OTHER right POS places and make it the source, restricting it
8603 to the proper length and mode. */
8605 src = canon_reg_for_combine (simplify_shift_const (NULL_RTX, LSHIFTRT,
8609 src = force_to_mode (src, mode,
8610 GET_MODE_BITSIZE (mode) >= HOST_BITS_PER_WIDE_INT
8611 ? ~(unsigned HOST_WIDE_INT) 0
8612 : ((unsigned HOST_WIDE_INT) 1 << len) - 1,
8615 /* If SRC is masked by an AND that does not make a difference in
8616 the value being stored, strip it. */
8617 if (GET_CODE (assign) == ZERO_EXTRACT
8618 && CONST_INT_P (XEXP (assign, 1))
8619 && INTVAL (XEXP (assign, 1)) < HOST_BITS_PER_WIDE_INT
8620 && GET_CODE (src) == AND
8621 && CONST_INT_P (XEXP (src, 1))
8622 && ((unsigned HOST_WIDE_INT) INTVAL (XEXP (src, 1))
8623 == ((unsigned HOST_WIDE_INT) 1 << INTVAL (XEXP (assign, 1))) - 1))
8624 src = XEXP (src, 0);
8626 return gen_rtx_SET (VOIDmode, assign, src);
8629 /* See if X is of the form (+ (* a c) (* b c)) and convert to (* (+ a b) c)
8633 apply_distributive_law (rtx x)
8635 enum rtx_code code = GET_CODE (x);
8636 enum rtx_code inner_code;
8637 rtx lhs, rhs, other;
8640 /* Distributivity is not true for floating point as it can change the
8641 value. So we don't do it unless -funsafe-math-optimizations. */
8642 if (FLOAT_MODE_P (GET_MODE (x))
8643 && ! flag_unsafe_math_optimizations)
8646 /* The outer operation can only be one of the following: */
8647 if (code != IOR && code != AND && code != XOR
8648 && code != PLUS && code != MINUS)
8654 /* If either operand is a primitive we can't do anything, so get out
8656 if (OBJECT_P (lhs) || OBJECT_P (rhs))
8659 lhs = expand_compound_operation (lhs);
8660 rhs = expand_compound_operation (rhs);
8661 inner_code = GET_CODE (lhs);
8662 if (inner_code != GET_CODE (rhs))
8665 /* See if the inner and outer operations distribute. */
8672 /* These all distribute except over PLUS. */
8673 if (code == PLUS || code == MINUS)
8678 if (code != PLUS && code != MINUS)
8683 /* This is also a multiply, so it distributes over everything. */
8687 /* Non-paradoxical SUBREGs distributes over all operations,
8688 provided the inner modes and byte offsets are the same, this
8689 is an extraction of a low-order part, we don't convert an fp
8690 operation to int or vice versa, this is not a vector mode,
8691 and we would not be converting a single-word operation into a
8692 multi-word operation. The latter test is not required, but
8693 it prevents generating unneeded multi-word operations. Some
8694 of the previous tests are redundant given the latter test,
8695 but are retained because they are required for correctness.
8697 We produce the result slightly differently in this case. */
8699 if (GET_MODE (SUBREG_REG (lhs)) != GET_MODE (SUBREG_REG (rhs))
8700 || SUBREG_BYTE (lhs) != SUBREG_BYTE (rhs)
8701 || ! subreg_lowpart_p (lhs)
8702 || (GET_MODE_CLASS (GET_MODE (lhs))
8703 != GET_MODE_CLASS (GET_MODE (SUBREG_REG (lhs))))
8704 || (GET_MODE_SIZE (GET_MODE (lhs))
8705 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs))))
8706 || VECTOR_MODE_P (GET_MODE (lhs))
8707 || GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs))) > UNITS_PER_WORD
8708 /* Result might need to be truncated. Don't change mode if
8709 explicit truncation is needed. */
8710 || !TRULY_NOOP_TRUNCATION
8711 (GET_MODE_BITSIZE (GET_MODE (x)),
8712 GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (lhs)))))
8715 tem = simplify_gen_binary (code, GET_MODE (SUBREG_REG (lhs)),
8716 SUBREG_REG (lhs), SUBREG_REG (rhs));
8717 return gen_lowpart (GET_MODE (x), tem);
8723 /* Set LHS and RHS to the inner operands (A and B in the example
8724 above) and set OTHER to the common operand (C in the example).
8725 There is only one way to do this unless the inner operation is
8727 if (COMMUTATIVE_ARITH_P (lhs)
8728 && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 0)))
8729 other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 1);
8730 else if (COMMUTATIVE_ARITH_P (lhs)
8731 && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 1)))
8732 other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 0);
8733 else if (COMMUTATIVE_ARITH_P (lhs)
8734 && rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 0)))
8735 other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 1);
8736 else if (rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 1)))
8737 other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 0);
8741 /* Form the new inner operation, seeing if it simplifies first. */
8742 tem = simplify_gen_binary (code, GET_MODE (x), lhs, rhs);
8744 /* There is one exception to the general way of distributing:
8745 (a | c) ^ (b | c) -> (a ^ b) & ~c */
8746 if (code == XOR && inner_code == IOR)
8749 other = simplify_gen_unary (NOT, GET_MODE (x), other, GET_MODE (x));
8752 /* We may be able to continuing distributing the result, so call
8753 ourselves recursively on the inner operation before forming the
8754 outer operation, which we return. */
8755 return simplify_gen_binary (inner_code, GET_MODE (x),
8756 apply_distributive_law (tem), other);
8759 /* See if X is of the form (* (+ A B) C), and if so convert to
8760 (+ (* A C) (* B C)) and try to simplify.
8762 Most of the time, this results in no change. However, if some of
8763 the operands are the same or inverses of each other, simplifications
8766 For example, (and (ior A B) (not B)) can occur as the result of
8767 expanding a bit field assignment. When we apply the distributive
8768 law to this, we get (ior (and (A (not B))) (and (B (not B)))),
8769 which then simplifies to (and (A (not B))).
8771 Note that no checks happen on the validity of applying the inverse
8772 distributive law. This is pointless since we can do it in the
8773 few places where this routine is called.
8775 N is the index of the term that is decomposed (the arithmetic operation,
8776 i.e. (+ A B) in the first example above). !N is the index of the term that
8777 is distributed, i.e. of C in the first example above. */
8779 distribute_and_simplify_rtx (rtx x, int n)
8781 enum machine_mode mode;
8782 enum rtx_code outer_code, inner_code;
8783 rtx decomposed, distributed, inner_op0, inner_op1, new_op0, new_op1, tmp;
8785 /* Distributivity is not true for floating point as it can change the
8786 value. So we don't do it unless -funsafe-math-optimizations. */
8787 if (FLOAT_MODE_P (GET_MODE (x))
8788 && ! flag_unsafe_math_optimizations)
8791 decomposed = XEXP (x, n);
8792 if (!ARITHMETIC_P (decomposed))
8795 mode = GET_MODE (x);
8796 outer_code = GET_CODE (x);
8797 distributed = XEXP (x, !n);
8799 inner_code = GET_CODE (decomposed);
8800 inner_op0 = XEXP (decomposed, 0);
8801 inner_op1 = XEXP (decomposed, 1);
8803 /* Special case (and (xor B C) (not A)), which is equivalent to
8804 (xor (ior A B) (ior A C)) */
8805 if (outer_code == AND && inner_code == XOR && GET_CODE (distributed) == NOT)
8807 distributed = XEXP (distributed, 0);
8813 /* Distribute the second term. */
8814 new_op0 = simplify_gen_binary (outer_code, mode, inner_op0, distributed);
8815 new_op1 = simplify_gen_binary (outer_code, mode, inner_op1, distributed);
8819 /* Distribute the first term. */
8820 new_op0 = simplify_gen_binary (outer_code, mode, distributed, inner_op0);
8821 new_op1 = simplify_gen_binary (outer_code, mode, distributed, inner_op1);
8824 tmp = apply_distributive_law (simplify_gen_binary (inner_code, mode,
8826 if (GET_CODE (tmp) != outer_code
8827 && rtx_cost (tmp, SET, optimize_this_for_speed_p)
8828 < rtx_cost (x, SET, optimize_this_for_speed_p))
8834 /* Simplify a logical `and' of VAROP with the constant CONSTOP, to be done
8835 in MODE. Return an equivalent form, if different from (and VAROP
8836 (const_int CONSTOP)). Otherwise, return NULL_RTX. */
8839 simplify_and_const_int_1 (enum machine_mode mode, rtx varop,
8840 unsigned HOST_WIDE_INT constop)
8842 unsigned HOST_WIDE_INT nonzero;
8843 unsigned HOST_WIDE_INT orig_constop;
8848 orig_constop = constop;
8849 if (GET_CODE (varop) == CLOBBER)
8852 /* Simplify VAROP knowing that we will be only looking at some of the
8855 Note by passing in CONSTOP, we guarantee that the bits not set in
8856 CONSTOP are not significant and will never be examined. We must
8857 ensure that is the case by explicitly masking out those bits
8858 before returning. */
8859 varop = force_to_mode (varop, mode, constop, 0);
8861 /* If VAROP is a CLOBBER, we will fail so return it. */
8862 if (GET_CODE (varop) == CLOBBER)
8865 /* If VAROP is a CONST_INT, then we need to apply the mask in CONSTOP
8866 to VAROP and return the new constant. */
8867 if (CONST_INT_P (varop))
8868 return gen_int_mode (INTVAL (varop) & constop, mode);
8870 /* See what bits may be nonzero in VAROP. Unlike the general case of
8871 a call to nonzero_bits, here we don't care about bits outside
8874 nonzero = nonzero_bits (varop, mode) & GET_MODE_MASK (mode);
8876 /* Turn off all bits in the constant that are known to already be zero.
8877 Thus, if the AND isn't needed at all, we will have CONSTOP == NONZERO_BITS
8878 which is tested below. */
8882 /* If we don't have any bits left, return zero. */
8886 /* If VAROP is a NEG of something known to be zero or 1 and CONSTOP is
8887 a power of two, we can replace this with an ASHIFT. */
8888 if (GET_CODE (varop) == NEG && nonzero_bits (XEXP (varop, 0), mode) == 1
8889 && (i = exact_log2 (constop)) >= 0)
8890 return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (varop, 0), i);
8892 /* If VAROP is an IOR or XOR, apply the AND to both branches of the IOR
8893 or XOR, then try to apply the distributive law. This may eliminate
8894 operations if either branch can be simplified because of the AND.
8895 It may also make some cases more complex, but those cases probably
8896 won't match a pattern either with or without this. */
8898 if (GET_CODE (varop) == IOR || GET_CODE (varop) == XOR)
8902 apply_distributive_law
8903 (simplify_gen_binary (GET_CODE (varop), GET_MODE (varop),
8904 simplify_and_const_int (NULL_RTX,
8908 simplify_and_const_int (NULL_RTX,
8913 /* If VAROP is PLUS, and the constant is a mask of low bits, distribute
8914 the AND and see if one of the operands simplifies to zero. If so, we
8915 may eliminate it. */
8917 if (GET_CODE (varop) == PLUS
8918 && exact_log2 (constop + 1) >= 0)
8922 o0 = simplify_and_const_int (NULL_RTX, mode, XEXP (varop, 0), constop);
8923 o1 = simplify_and_const_int (NULL_RTX, mode, XEXP (varop, 1), constop);
8924 if (o0 == const0_rtx)
8926 if (o1 == const0_rtx)
8930 /* Make a SUBREG if necessary. If we can't make it, fail. */
8931 varop = gen_lowpart (mode, varop);
8932 if (varop == NULL_RTX || GET_CODE (varop) == CLOBBER)
8935 /* If we are only masking insignificant bits, return VAROP. */
8936 if (constop == nonzero)
8939 if (varop == orig_varop && constop == orig_constop)
8942 /* Otherwise, return an AND. */
8943 return simplify_gen_binary (AND, mode, varop, gen_int_mode (constop, mode));
8947 /* We have X, a logical `and' of VAROP with the constant CONSTOP, to be done
8950 Return an equivalent form, if different from X. Otherwise, return X. If
8951 X is zero, we are to always construct the equivalent form. */
8954 simplify_and_const_int (rtx x, enum machine_mode mode, rtx varop,
8955 unsigned HOST_WIDE_INT constop)
8957 rtx tem = simplify_and_const_int_1 (mode, varop, constop);
8962 x = simplify_gen_binary (AND, GET_MODE (varop), varop,
8963 gen_int_mode (constop, mode));
8964 if (GET_MODE (x) != mode)
8965 x = gen_lowpart (mode, x);
8969 /* Given a REG, X, compute which bits in X can be nonzero.
8970 We don't care about bits outside of those defined in MODE.
8972 For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is
8973 a shift, AND, or zero_extract, we can do better. */
8976 reg_nonzero_bits_for_combine (const_rtx x, enum machine_mode mode,
8977 const_rtx known_x ATTRIBUTE_UNUSED,
8978 enum machine_mode known_mode ATTRIBUTE_UNUSED,
8979 unsigned HOST_WIDE_INT known_ret ATTRIBUTE_UNUSED,
8980 unsigned HOST_WIDE_INT *nonzero)
8985 /* If X is a register whose nonzero bits value is current, use it.
8986 Otherwise, if X is a register whose value we can find, use that
8987 value. Otherwise, use the previously-computed global nonzero bits
8988 for this register. */
8990 rsp = VEC_index (reg_stat_type, reg_stat, REGNO (x));
8991 if (rsp->last_set_value != 0
8992 && (rsp->last_set_mode == mode
8993 || (GET_MODE_CLASS (rsp->last_set_mode) == MODE_INT
8994 && GET_MODE_CLASS (mode) == MODE_INT))
8995 && ((rsp->last_set_label >= label_tick_ebb_start
8996 && rsp->last_set_label < label_tick)
8997 || (rsp->last_set_label == label_tick
8998 && DF_INSN_LUID (rsp->last_set) < subst_low_luid)
8999 || (REGNO (x) >= FIRST_PSEUDO_REGISTER
9000 && REG_N_SETS (REGNO (x)) == 1
9002 (DF_LR_IN (ENTRY_BLOCK_PTR->next_bb), REGNO (x)))))
9004 *nonzero &= rsp->last_set_nonzero_bits;
9008 tem = get_last_value (x);
9012 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
9013 /* If X is narrower than MODE and TEM is a non-negative
9014 constant that would appear negative in the mode of X,
9015 sign-extend it for use in reg_nonzero_bits because some
9016 machines (maybe most) will actually do the sign-extension
9017 and this is the conservative approach.
9019 ??? For 2.5, try to tighten up the MD files in this regard
9020 instead of this kludge. */
9022 if (GET_MODE_BITSIZE (GET_MODE (x)) < GET_MODE_BITSIZE (mode)
9023 && CONST_INT_P (tem)
9025 && 0 != (INTVAL (tem)
9026 & ((HOST_WIDE_INT) 1
9027 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
9028 tem = GEN_INT (INTVAL (tem)
9029 | ((HOST_WIDE_INT) (-1)
9030 << GET_MODE_BITSIZE (GET_MODE (x))));
9034 else if (nonzero_sign_valid && rsp->nonzero_bits)
9036 unsigned HOST_WIDE_INT mask = rsp->nonzero_bits;
9038 if (GET_MODE_BITSIZE (GET_MODE (x)) < GET_MODE_BITSIZE (mode))
9039 /* We don't know anything about the upper bits. */
9040 mask |= GET_MODE_MASK (mode) ^ GET_MODE_MASK (GET_MODE (x));
9047 /* Return the number of bits at the high-order end of X that are known to
9048 be equal to the sign bit. X will be used in mode MODE; if MODE is
9049 VOIDmode, X will be used in its own mode. The returned value will always
9050 be between 1 and the number of bits in MODE. */
9053 reg_num_sign_bit_copies_for_combine (const_rtx x, enum machine_mode mode,
9054 const_rtx known_x ATTRIBUTE_UNUSED,
9055 enum machine_mode known_mode
9057 unsigned int known_ret ATTRIBUTE_UNUSED,
9058 unsigned int *result)
9063 rsp = VEC_index (reg_stat_type, reg_stat, REGNO (x));
9064 if (rsp->last_set_value != 0
9065 && rsp->last_set_mode == mode
9066 && ((rsp->last_set_label >= label_tick_ebb_start
9067 && rsp->last_set_label < label_tick)
9068 || (rsp->last_set_label == label_tick
9069 && DF_INSN_LUID (rsp->last_set) < subst_low_luid)
9070 || (REGNO (x) >= FIRST_PSEUDO_REGISTER
9071 && REG_N_SETS (REGNO (x)) == 1
9073 (DF_LR_IN (ENTRY_BLOCK_PTR->next_bb), REGNO (x)))))
9075 *result = rsp->last_set_sign_bit_copies;
9079 tem = get_last_value (x);
9083 if (nonzero_sign_valid && rsp->sign_bit_copies != 0
9084 && GET_MODE_BITSIZE (GET_MODE (x)) == GET_MODE_BITSIZE (mode))
9085 *result = rsp->sign_bit_copies;
9090 /* Return the number of "extended" bits there are in X, when interpreted
9091 as a quantity in MODE whose signedness is indicated by UNSIGNEDP. For
9092 unsigned quantities, this is the number of high-order zero bits.
9093 For signed quantities, this is the number of copies of the sign bit
9094 minus 1. In both case, this function returns the number of "spare"
9095 bits. For example, if two quantities for which this function returns
9096 at least 1 are added, the addition is known not to overflow.
9098 This function will always return 0 unless called during combine, which
9099 implies that it must be called from a define_split. */
9102 extended_count (const_rtx x, enum machine_mode mode, int unsignedp)
9104 if (nonzero_sign_valid == 0)
9108 ? (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
9109 ? (unsigned int) (GET_MODE_BITSIZE (mode) - 1
9110 - floor_log2 (nonzero_bits (x, mode)))
9112 : num_sign_bit_copies (x, mode) - 1);
9115 /* This function is called from `simplify_shift_const' to merge two
9116 outer operations. Specifically, we have already found that we need
9117 to perform operation *POP0 with constant *PCONST0 at the outermost
9118 position. We would now like to also perform OP1 with constant CONST1
9119 (with *POP0 being done last).
9121 Return 1 if we can do the operation and update *POP0 and *PCONST0 with
9122 the resulting operation. *PCOMP_P is set to 1 if we would need to
9123 complement the innermost operand, otherwise it is unchanged.
9125 MODE is the mode in which the operation will be done. No bits outside
9126 the width of this mode matter. It is assumed that the width of this mode
9127 is smaller than or equal to HOST_BITS_PER_WIDE_INT.
9129 If *POP0 or OP1 are UNKNOWN, it means no operation is required. Only NEG, PLUS,
9130 IOR, XOR, and AND are supported. We may set *POP0 to SET if the proper
9131 result is simply *PCONST0.
9133 If the resulting operation cannot be expressed as one operation, we
9134 return 0 and do not change *POP0, *PCONST0, and *PCOMP_P. */
9137 merge_outer_ops (enum rtx_code *pop0, HOST_WIDE_INT *pconst0, enum rtx_code op1, HOST_WIDE_INT const1, enum machine_mode mode, int *pcomp_p)
9139 enum rtx_code op0 = *pop0;
9140 HOST_WIDE_INT const0 = *pconst0;
9142 const0 &= GET_MODE_MASK (mode);
9143 const1 &= GET_MODE_MASK (mode);
9145 /* If OP0 is an AND, clear unimportant bits in CONST1. */
9149 /* If OP0 or OP1 is UNKNOWN, this is easy. Similarly if they are the same or
9152 if (op1 == UNKNOWN || op0 == SET)
9155 else if (op0 == UNKNOWN)
9156 op0 = op1, const0 = const1;
9158 else if (op0 == op1)
9182 /* Otherwise, if either is a PLUS or NEG, we can't do anything. */
9183 else if (op0 == PLUS || op1 == PLUS || op0 == NEG || op1 == NEG)
9186 /* If the two constants aren't the same, we can't do anything. The
9187 remaining six cases can all be done. */
9188 else if (const0 != const1)
9196 /* (a & b) | b == b */
9198 else /* op1 == XOR */
9199 /* (a ^ b) | b == a | b */
9205 /* (a & b) ^ b == (~a) & b */
9206 op0 = AND, *pcomp_p = 1;
9207 else /* op1 == IOR */
9208 /* (a | b) ^ b == a & ~b */
9209 op0 = AND, const0 = ~const0;
9214 /* (a | b) & b == b */
9216 else /* op1 == XOR */
9217 /* (a ^ b) & b) == (~a) & b */
9224 /* Check for NO-OP cases. */
9225 const0 &= GET_MODE_MASK (mode);
9227 && (op0 == IOR || op0 == XOR || op0 == PLUS))
9229 else if (const0 == 0 && op0 == AND)
9231 else if ((unsigned HOST_WIDE_INT) const0 == GET_MODE_MASK (mode)
9237 /* ??? Slightly redundant with the above mask, but not entirely.
9238 Moving this above means we'd have to sign-extend the mode mask
9239 for the final test. */
9240 if (op0 != UNKNOWN && op0 != NEG)
9241 *pconst0 = trunc_int_for_mode (const0, mode);
9246 /* A helper to simplify_shift_const_1 to determine the mode we can perform
9247 the shift in. The original shift operation CODE is performed on OP in
9248 ORIG_MODE. Return the wider mode MODE if we can perform the operation
9249 in that mode. Return ORIG_MODE otherwise. We can also assume that the
9250 result of the shift is subject to operation OUTER_CODE with operand
9253 static enum machine_mode
9254 try_widen_shift_mode (enum rtx_code code, rtx op, int count,
9255 enum machine_mode orig_mode, enum machine_mode mode,
9256 enum rtx_code outer_code, HOST_WIDE_INT outer_const)
9258 if (orig_mode == mode)
9260 gcc_assert (GET_MODE_BITSIZE (mode) > GET_MODE_BITSIZE (orig_mode));
9262 /* In general we can't perform in wider mode for right shift and rotate. */
9266 /* We can still widen if the bits brought in from the left are identical
9267 to the sign bit of ORIG_MODE. */
9268 if (num_sign_bit_copies (op, mode)
9269 > (unsigned) (GET_MODE_BITSIZE (mode)
9270 - GET_MODE_BITSIZE (orig_mode)))
9275 /* Similarly here but with zero bits. */
9276 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
9277 && (nonzero_bits (op, mode) & ~GET_MODE_MASK (orig_mode)) == 0)
9280 /* We can also widen if the bits brought in will be masked off. This
9281 operation is performed in ORIG_MODE. */
9282 if (outer_code == AND)
9284 int care_bits = low_bitmask_len (orig_mode, outer_const);
9287 && GET_MODE_BITSIZE (orig_mode) - care_bits >= count)
9303 /* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift.
9304 The result of the shift is RESULT_MODE. Return NULL_RTX if we cannot
9305 simplify it. Otherwise, return a simplified value.
9307 The shift is normally computed in the widest mode we find in VAROP, as
9308 long as it isn't a different number of words than RESULT_MODE. Exceptions
9309 are ASHIFTRT and ROTATE, which are always done in their original mode. */
9312 simplify_shift_const_1 (enum rtx_code code, enum machine_mode result_mode,
9313 rtx varop, int orig_count)
9315 enum rtx_code orig_code = code;
9316 rtx orig_varop = varop;
9318 enum machine_mode mode = result_mode;
9319 enum machine_mode shift_mode, tmode;
9320 unsigned int mode_words
9321 = (GET_MODE_SIZE (mode) + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD;
9322 /* We form (outer_op (code varop count) (outer_const)). */
9323 enum rtx_code outer_op = UNKNOWN;
9324 HOST_WIDE_INT outer_const = 0;
9325 int complement_p = 0;
9328 /* Make sure and truncate the "natural" shift on the way in. We don't
9329 want to do this inside the loop as it makes it more difficult to
9331 if (SHIFT_COUNT_TRUNCATED)
9332 orig_count &= GET_MODE_BITSIZE (mode) - 1;
9334 /* If we were given an invalid count, don't do anything except exactly
9335 what was requested. */
9337 if (orig_count < 0 || orig_count >= (int) GET_MODE_BITSIZE (mode))
9342 /* Unless one of the branches of the `if' in this loop does a `continue',
9343 we will `break' the loop after the `if'. */
9347 /* If we have an operand of (clobber (const_int 0)), fail. */
9348 if (GET_CODE (varop) == CLOBBER)
9351 /* Convert ROTATERT to ROTATE. */
9352 if (code == ROTATERT)
9354 unsigned int bitsize = GET_MODE_BITSIZE (result_mode);;
9356 if (VECTOR_MODE_P (result_mode))
9357 count = bitsize / GET_MODE_NUNITS (result_mode) - count;
9359 count = bitsize - count;
9362 shift_mode = try_widen_shift_mode (code, varop, count, result_mode,
9363 mode, outer_op, outer_const);
9365 /* Handle cases where the count is greater than the size of the mode
9366 minus 1. For ASHIFT, use the size minus one as the count (this can
9367 occur when simplifying (lshiftrt (ashiftrt ..))). For rotates,
9368 take the count modulo the size. For other shifts, the result is
9371 Since these shifts are being produced by the compiler by combining
9372 multiple operations, each of which are defined, we know what the
9373 result is supposed to be. */
9375 if (count > (GET_MODE_BITSIZE (shift_mode) - 1))
9377 if (code == ASHIFTRT)
9378 count = GET_MODE_BITSIZE (shift_mode) - 1;
9379 else if (code == ROTATE || code == ROTATERT)
9380 count %= GET_MODE_BITSIZE (shift_mode);
9383 /* We can't simply return zero because there may be an
9391 /* If we discovered we had to complement VAROP, leave. Making a NOT
9392 here would cause an infinite loop. */
9396 /* An arithmetic right shift of a quantity known to be -1 or 0
9398 if (code == ASHIFTRT
9399 && (num_sign_bit_copies (varop, shift_mode)
9400 == GET_MODE_BITSIZE (shift_mode)))
9406 /* If we are doing an arithmetic right shift and discarding all but
9407 the sign bit copies, this is equivalent to doing a shift by the
9408 bitsize minus one. Convert it into that shift because it will often
9409 allow other simplifications. */
9411 if (code == ASHIFTRT
9412 && (count + num_sign_bit_copies (varop, shift_mode)
9413 >= GET_MODE_BITSIZE (shift_mode)))
9414 count = GET_MODE_BITSIZE (shift_mode) - 1;
9416 /* We simplify the tests below and elsewhere by converting
9417 ASHIFTRT to LSHIFTRT if we know the sign bit is clear.
9418 `make_compound_operation' will convert it to an ASHIFTRT for
9419 those machines (such as VAX) that don't have an LSHIFTRT. */
9420 if (GET_MODE_BITSIZE (shift_mode) <= HOST_BITS_PER_WIDE_INT
9422 && ((nonzero_bits (varop, shift_mode)
9423 & ((HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (shift_mode) - 1)))
9427 if (((code == LSHIFTRT
9428 && GET_MODE_BITSIZE (shift_mode) <= HOST_BITS_PER_WIDE_INT
9429 && !(nonzero_bits (varop, shift_mode) >> count))
9431 && GET_MODE_BITSIZE (shift_mode) <= HOST_BITS_PER_WIDE_INT
9432 && !((nonzero_bits (varop, shift_mode) << count)
9433 & GET_MODE_MASK (shift_mode))))
9434 && !side_effects_p (varop))
9437 switch (GET_CODE (varop))
9443 new_rtx = expand_compound_operation (varop);
9444 if (new_rtx != varop)
9452 /* If we have (xshiftrt (mem ...) C) and C is MODE_WIDTH
9453 minus the width of a smaller mode, we can do this with a
9454 SIGN_EXTEND or ZERO_EXTEND from the narrower memory location. */
9455 if ((code == ASHIFTRT || code == LSHIFTRT)
9456 && ! mode_dependent_address_p (XEXP (varop, 0))
9457 && ! MEM_VOLATILE_P (varop)
9458 && (tmode = mode_for_size (GET_MODE_BITSIZE (mode) - count,
9459 MODE_INT, 1)) != BLKmode)
9461 new_rtx = adjust_address_nv (varop, tmode,
9462 BYTES_BIG_ENDIAN ? 0
9463 : count / BITS_PER_UNIT);
9465 varop = gen_rtx_fmt_e (code == ASHIFTRT ? SIGN_EXTEND
9466 : ZERO_EXTEND, mode, new_rtx);
9473 /* If VAROP is a SUBREG, strip it as long as the inner operand has
9474 the same number of words as what we've seen so far. Then store
9475 the widest mode in MODE. */
9476 if (subreg_lowpart_p (varop)
9477 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop)))
9478 > GET_MODE_SIZE (GET_MODE (varop)))
9479 && (unsigned int) ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop)))
9480 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
9483 varop = SUBREG_REG (varop);
9484 if (GET_MODE_SIZE (GET_MODE (varop)) > GET_MODE_SIZE (mode))
9485 mode = GET_MODE (varop);
9491 /* Some machines use MULT instead of ASHIFT because MULT
9492 is cheaper. But it is still better on those machines to
9493 merge two shifts into one. */
9494 if (CONST_INT_P (XEXP (varop, 1))
9495 && exact_log2 (INTVAL (XEXP (varop, 1))) >= 0)
9498 = simplify_gen_binary (ASHIFT, GET_MODE (varop),
9500 GEN_INT (exact_log2 (
9501 INTVAL (XEXP (varop, 1)))));
9507 /* Similar, for when divides are cheaper. */
9508 if (CONST_INT_P (XEXP (varop, 1))
9509 && exact_log2 (INTVAL (XEXP (varop, 1))) >= 0)
9512 = simplify_gen_binary (LSHIFTRT, GET_MODE (varop),
9514 GEN_INT (exact_log2 (
9515 INTVAL (XEXP (varop, 1)))));
9521 /* If we are extracting just the sign bit of an arithmetic
9522 right shift, that shift is not needed. However, the sign
9523 bit of a wider mode may be different from what would be
9524 interpreted as the sign bit in a narrower mode, so, if
9525 the result is narrower, don't discard the shift. */
9526 if (code == LSHIFTRT
9527 && count == (GET_MODE_BITSIZE (result_mode) - 1)
9528 && (GET_MODE_BITSIZE (result_mode)
9529 >= GET_MODE_BITSIZE (GET_MODE (varop))))
9531 varop = XEXP (varop, 0);
9535 /* ... fall through ... */
9540 /* Here we have two nested shifts. The result is usually the
9541 AND of a new shift with a mask. We compute the result below. */
9542 if (CONST_INT_P (XEXP (varop, 1))
9543 && INTVAL (XEXP (varop, 1)) >= 0
9544 && INTVAL (XEXP (varop, 1)) < GET_MODE_BITSIZE (GET_MODE (varop))
9545 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
9546 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
9547 && !VECTOR_MODE_P (result_mode))
9549 enum rtx_code first_code = GET_CODE (varop);
9550 unsigned int first_count = INTVAL (XEXP (varop, 1));
9551 unsigned HOST_WIDE_INT mask;
9554 /* We have one common special case. We can't do any merging if
9555 the inner code is an ASHIFTRT of a smaller mode. However, if
9556 we have (ashift:M1 (subreg:M1 (ashiftrt:M2 FOO C1) 0) C2)
9557 with C2 == GET_MODE_BITSIZE (M1) - GET_MODE_BITSIZE (M2),
9558 we can convert it to
9559 (ashiftrt:M1 (ashift:M1 (and:M1 (subreg:M1 FOO 0 C2) C3) C1).
9560 This simplifies certain SIGN_EXTEND operations. */
9561 if (code == ASHIFT && first_code == ASHIFTRT
9562 && count == (GET_MODE_BITSIZE (result_mode)
9563 - GET_MODE_BITSIZE (GET_MODE (varop))))
9565 /* C3 has the low-order C1 bits zero. */
9567 mask = (GET_MODE_MASK (mode)
9568 & ~(((HOST_WIDE_INT) 1 << first_count) - 1));
9570 varop = simplify_and_const_int (NULL_RTX, result_mode,
9571 XEXP (varop, 0), mask);
9572 varop = simplify_shift_const (NULL_RTX, ASHIFT, result_mode,
9574 count = first_count;
9579 /* If this was (ashiftrt (ashift foo C1) C2) and FOO has more
9580 than C1 high-order bits equal to the sign bit, we can convert
9581 this to either an ASHIFT or an ASHIFTRT depending on the
9584 We cannot do this if VAROP's mode is not SHIFT_MODE. */
9586 if (code == ASHIFTRT && first_code == ASHIFT
9587 && GET_MODE (varop) == shift_mode
9588 && (num_sign_bit_copies (XEXP (varop, 0), shift_mode)
9591 varop = XEXP (varop, 0);
9592 count -= first_count;
9602 /* There are some cases we can't do. If CODE is ASHIFTRT,
9603 we can only do this if FIRST_CODE is also ASHIFTRT.
9605 We can't do the case when CODE is ROTATE and FIRST_CODE is
9608 If the mode of this shift is not the mode of the outer shift,
9609 we can't do this if either shift is a right shift or ROTATE.
9611 Finally, we can't do any of these if the mode is too wide
9612 unless the codes are the same.
9614 Handle the case where the shift codes are the same
9617 if (code == first_code)
9619 if (GET_MODE (varop) != result_mode
9620 && (code == ASHIFTRT || code == LSHIFTRT
9624 count += first_count;
9625 varop = XEXP (varop, 0);
9629 if (code == ASHIFTRT
9630 || (code == ROTATE && first_code == ASHIFTRT)
9631 || GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT
9632 || (GET_MODE (varop) != result_mode
9633 && (first_code == ASHIFTRT || first_code == LSHIFTRT
9634 || first_code == ROTATE
9635 || code == ROTATE)))
9638 /* To compute the mask to apply after the shift, shift the
9639 nonzero bits of the inner shift the same way the
9640 outer shift will. */
9642 mask_rtx = GEN_INT (nonzero_bits (varop, GET_MODE (varop)));
9645 = simplify_const_binary_operation (code, result_mode, mask_rtx,
9648 /* Give up if we can't compute an outer operation to use. */
9650 || !CONST_INT_P (mask_rtx)
9651 || ! merge_outer_ops (&outer_op, &outer_const, AND,
9653 result_mode, &complement_p))
9656 /* If the shifts are in the same direction, we add the
9657 counts. Otherwise, we subtract them. */
9658 if ((code == ASHIFTRT || code == LSHIFTRT)
9659 == (first_code == ASHIFTRT || first_code == LSHIFTRT))
9660 count += first_count;
9662 count -= first_count;
9664 /* If COUNT is positive, the new shift is usually CODE,
9665 except for the two exceptions below, in which case it is
9666 FIRST_CODE. If the count is negative, FIRST_CODE should
9669 && ((first_code == ROTATE && code == ASHIFT)
9670 || (first_code == ASHIFTRT && code == LSHIFTRT)))
9673 code = first_code, count = -count;
9675 varop = XEXP (varop, 0);
9679 /* If we have (A << B << C) for any shift, we can convert this to
9680 (A << C << B). This wins if A is a constant. Only try this if
9681 B is not a constant. */
9683 else if (GET_CODE (varop) == code
9684 && CONST_INT_P (XEXP (varop, 0))
9685 && !CONST_INT_P (XEXP (varop, 1)))
9687 rtx new_rtx = simplify_const_binary_operation (code, mode,
9690 varop = gen_rtx_fmt_ee (code, mode, new_rtx, XEXP (varop, 1));
9697 if (VECTOR_MODE_P (mode))
9700 /* Make this fit the case below. */
9701 varop = gen_rtx_XOR (mode, XEXP (varop, 0),
9702 GEN_INT (GET_MODE_MASK (mode)));
9708 /* If we have (xshiftrt (ior (plus X (const_int -1)) X) C)
9709 with C the size of VAROP - 1 and the shift is logical if
9710 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
9711 we have an (le X 0) operation. If we have an arithmetic shift
9712 and STORE_FLAG_VALUE is 1 or we have a logical shift with
9713 STORE_FLAG_VALUE of -1, we have a (neg (le X 0)) operation. */
9715 if (GET_CODE (varop) == IOR && GET_CODE (XEXP (varop, 0)) == PLUS
9716 && XEXP (XEXP (varop, 0), 1) == constm1_rtx
9717 && (STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
9718 && (code == LSHIFTRT || code == ASHIFTRT)
9719 && count == (GET_MODE_BITSIZE (GET_MODE (varop)) - 1)
9720 && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
9723 varop = gen_rtx_LE (GET_MODE (varop), XEXP (varop, 1),
9726 if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
9727 varop = gen_rtx_NEG (GET_MODE (varop), varop);
9732 /* If we have (shift (logical)), move the logical to the outside
9733 to allow it to possibly combine with another logical and the
9734 shift to combine with another shift. This also canonicalizes to
9735 what a ZERO_EXTRACT looks like. Also, some machines have
9736 (and (shift)) insns. */
9738 if (CONST_INT_P (XEXP (varop, 1))
9739 /* We can't do this if we have (ashiftrt (xor)) and the
9740 constant has its sign bit set in shift_mode. */
9741 && !(code == ASHIFTRT && GET_CODE (varop) == XOR
9742 && 0 > trunc_int_for_mode (INTVAL (XEXP (varop, 1)),
9744 && (new_rtx = simplify_const_binary_operation (code, result_mode,
9746 GEN_INT (count))) != 0
9747 && CONST_INT_P (new_rtx)
9748 && merge_outer_ops (&outer_op, &outer_const, GET_CODE (varop),
9749 INTVAL (new_rtx), result_mode, &complement_p))
9751 varop = XEXP (varop, 0);
9755 /* If we can't do that, try to simplify the shift in each arm of the
9756 logical expression, make a new logical expression, and apply
9757 the inverse distributive law. This also can't be done
9758 for some (ashiftrt (xor)). */
9759 if (CONST_INT_P (XEXP (varop, 1))
9760 && !(code == ASHIFTRT && GET_CODE (varop) == XOR
9761 && 0 > trunc_int_for_mode (INTVAL (XEXP (varop, 1)),
9764 rtx lhs = simplify_shift_const (NULL_RTX, code, shift_mode,
9765 XEXP (varop, 0), count);
9766 rtx rhs = simplify_shift_const (NULL_RTX, code, shift_mode,
9767 XEXP (varop, 1), count);
9769 varop = simplify_gen_binary (GET_CODE (varop), shift_mode,
9771 varop = apply_distributive_law (varop);
9779 /* Convert (lshiftrt (eq FOO 0) C) to (xor FOO 1) if STORE_FLAG_VALUE
9780 says that the sign bit can be tested, FOO has mode MODE, C is
9781 GET_MODE_BITSIZE (MODE) - 1, and FOO has only its low-order bit
9782 that may be nonzero. */
9783 if (code == LSHIFTRT
9784 && XEXP (varop, 1) == const0_rtx
9785 && GET_MODE (XEXP (varop, 0)) == result_mode
9786 && count == (GET_MODE_BITSIZE (result_mode) - 1)
9787 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
9788 && STORE_FLAG_VALUE == -1
9789 && nonzero_bits (XEXP (varop, 0), result_mode) == 1
9790 && merge_outer_ops (&outer_op, &outer_const, XOR,
9791 (HOST_WIDE_INT) 1, result_mode,
9794 varop = XEXP (varop, 0);
9801 /* (lshiftrt (neg A) C) where A is either 0 or 1 and C is one less
9802 than the number of bits in the mode is equivalent to A. */
9803 if (code == LSHIFTRT
9804 && count == (GET_MODE_BITSIZE (result_mode) - 1)
9805 && nonzero_bits (XEXP (varop, 0), result_mode) == 1)
9807 varop = XEXP (varop, 0);
9812 /* NEG commutes with ASHIFT since it is multiplication. Move the
9813 NEG outside to allow shifts to combine. */
9815 && merge_outer_ops (&outer_op, &outer_const, NEG,
9816 (HOST_WIDE_INT) 0, result_mode,
9819 varop = XEXP (varop, 0);
9825 /* (lshiftrt (plus A -1) C) where A is either 0 or 1 and C
9826 is one less than the number of bits in the mode is
9827 equivalent to (xor A 1). */
9828 if (code == LSHIFTRT
9829 && count == (GET_MODE_BITSIZE (result_mode) - 1)
9830 && XEXP (varop, 1) == constm1_rtx
9831 && nonzero_bits (XEXP (varop, 0), result_mode) == 1
9832 && merge_outer_ops (&outer_op, &outer_const, XOR,
9833 (HOST_WIDE_INT) 1, result_mode,
9837 varop = XEXP (varop, 0);
9841 /* If we have (xshiftrt (plus FOO BAR) C), and the only bits
9842 that might be nonzero in BAR are those being shifted out and those
9843 bits are known zero in FOO, we can replace the PLUS with FOO.
9844 Similarly in the other operand order. This code occurs when
9845 we are computing the size of a variable-size array. */
9847 if ((code == ASHIFTRT || code == LSHIFTRT)
9848 && count < HOST_BITS_PER_WIDE_INT
9849 && nonzero_bits (XEXP (varop, 1), result_mode) >> count == 0
9850 && (nonzero_bits (XEXP (varop, 1), result_mode)
9851 & nonzero_bits (XEXP (varop, 0), result_mode)) == 0)
9853 varop = XEXP (varop, 0);
9856 else if ((code == ASHIFTRT || code == LSHIFTRT)
9857 && count < HOST_BITS_PER_WIDE_INT
9858 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
9859 && 0 == (nonzero_bits (XEXP (varop, 0), result_mode)
9861 && 0 == (nonzero_bits (XEXP (varop, 0), result_mode)
9862 & nonzero_bits (XEXP (varop, 1),
9865 varop = XEXP (varop, 1);
9869 /* (ashift (plus foo C) N) is (plus (ashift foo N) C'). */
9871 && CONST_INT_P (XEXP (varop, 1))
9872 && (new_rtx = simplify_const_binary_operation (ASHIFT, result_mode,
9874 GEN_INT (count))) != 0
9875 && CONST_INT_P (new_rtx)
9876 && merge_outer_ops (&outer_op, &outer_const, PLUS,
9877 INTVAL (new_rtx), result_mode, &complement_p))
9879 varop = XEXP (varop, 0);
9883 /* Check for 'PLUS signbit', which is the canonical form of 'XOR
9884 signbit', and attempt to change the PLUS to an XOR and move it to
9885 the outer operation as is done above in the AND/IOR/XOR case
9886 leg for shift(logical). See details in logical handling above
9887 for reasoning in doing so. */
9888 if (code == LSHIFTRT
9889 && CONST_INT_P (XEXP (varop, 1))
9890 && mode_signbit_p (result_mode, XEXP (varop, 1))
9891 && (new_rtx = simplify_const_binary_operation (code, result_mode,
9893 GEN_INT (count))) != 0
9894 && CONST_INT_P (new_rtx)
9895 && merge_outer_ops (&outer_op, &outer_const, XOR,
9896 INTVAL (new_rtx), result_mode, &complement_p))
9898 varop = XEXP (varop, 0);
9905 /* If we have (xshiftrt (minus (ashiftrt X C)) X) C)
9906 with C the size of VAROP - 1 and the shift is logical if
9907 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
9908 we have a (gt X 0) operation. If the shift is arithmetic with
9909 STORE_FLAG_VALUE of 1 or logical with STORE_FLAG_VALUE == -1,
9910 we have a (neg (gt X 0)) operation. */
9912 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
9913 && GET_CODE (XEXP (varop, 0)) == ASHIFTRT
9914 && count == (GET_MODE_BITSIZE (GET_MODE (varop)) - 1)
9915 && (code == LSHIFTRT || code == ASHIFTRT)
9916 && CONST_INT_P (XEXP (XEXP (varop, 0), 1))
9917 && INTVAL (XEXP (XEXP (varop, 0), 1)) == count
9918 && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
9921 varop = gen_rtx_GT (GET_MODE (varop), XEXP (varop, 1),
9924 if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
9925 varop = gen_rtx_NEG (GET_MODE (varop), varop);
9932 /* Change (lshiftrt (truncate (lshiftrt))) to (truncate (lshiftrt))
9933 if the truncate does not affect the value. */
9934 if (code == LSHIFTRT
9935 && GET_CODE (XEXP (varop, 0)) == LSHIFTRT
9936 && CONST_INT_P (XEXP (XEXP (varop, 0), 1))
9937 && (INTVAL (XEXP (XEXP (varop, 0), 1))
9938 >= (GET_MODE_BITSIZE (GET_MODE (XEXP (varop, 0)))
9939 - GET_MODE_BITSIZE (GET_MODE (varop)))))
9941 rtx varop_inner = XEXP (varop, 0);
9944 = gen_rtx_LSHIFTRT (GET_MODE (varop_inner),
9945 XEXP (varop_inner, 0),
9947 (count + INTVAL (XEXP (varop_inner, 1))));
9948 varop = gen_rtx_TRUNCATE (GET_MODE (varop), varop_inner);
9961 shift_mode = try_widen_shift_mode (code, varop, count, result_mode, mode,
9962 outer_op, outer_const);
9964 /* We have now finished analyzing the shift. The result should be
9965 a shift of type CODE with SHIFT_MODE shifting VAROP COUNT places. If
9966 OUTER_OP is non-UNKNOWN, it is an operation that needs to be applied
9967 to the result of the shift. OUTER_CONST is the relevant constant,
9968 but we must turn off all bits turned off in the shift. */
9970 if (outer_op == UNKNOWN
9971 && orig_code == code && orig_count == count
9972 && varop == orig_varop
9973 && shift_mode == GET_MODE (varop))
9976 /* Make a SUBREG if necessary. If we can't make it, fail. */
9977 varop = gen_lowpart (shift_mode, varop);
9978 if (varop == NULL_RTX || GET_CODE (varop) == CLOBBER)
9981 /* If we have an outer operation and we just made a shift, it is
9982 possible that we could have simplified the shift were it not
9983 for the outer operation. So try to do the simplification
9986 if (outer_op != UNKNOWN)
9987 x = simplify_shift_const_1 (code, shift_mode, varop, count);
9992 x = simplify_gen_binary (code, shift_mode, varop, GEN_INT (count));
9994 /* If we were doing an LSHIFTRT in a wider mode than it was originally,
9995 turn off all the bits that the shift would have turned off. */
9996 if (orig_code == LSHIFTRT && result_mode != shift_mode)
9997 x = simplify_and_const_int (NULL_RTX, shift_mode, x,
9998 GET_MODE_MASK (result_mode) >> orig_count);
10000 /* Do the remainder of the processing in RESULT_MODE. */
10001 x = gen_lowpart_or_truncate (result_mode, x);
10003 /* If COMPLEMENT_P is set, we have to complement X before doing the outer
10006 x = simplify_gen_unary (NOT, result_mode, x, result_mode);
10008 if (outer_op != UNKNOWN)
10010 if (GET_RTX_CLASS (outer_op) != RTX_UNARY
10011 && GET_MODE_BITSIZE (result_mode) < HOST_BITS_PER_WIDE_INT)
10012 outer_const = trunc_int_for_mode (outer_const, result_mode);
10014 if (outer_op == AND)
10015 x = simplify_and_const_int (NULL_RTX, result_mode, x, outer_const);
10016 else if (outer_op == SET)
10018 /* This means that we have determined that the result is
10019 equivalent to a constant. This should be rare. */
10020 if (!side_effects_p (x))
10021 x = GEN_INT (outer_const);
10023 else if (GET_RTX_CLASS (outer_op) == RTX_UNARY)
10024 x = simplify_gen_unary (outer_op, result_mode, x, result_mode);
10026 x = simplify_gen_binary (outer_op, result_mode, x,
10027 GEN_INT (outer_const));
10033 /* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift.
10034 The result of the shift is RESULT_MODE. If we cannot simplify it,
10035 return X or, if it is NULL, synthesize the expression with
10036 simplify_gen_binary. Otherwise, return a simplified value.
10038 The shift is normally computed in the widest mode we find in VAROP, as
10039 long as it isn't a different number of words than RESULT_MODE. Exceptions
10040 are ASHIFTRT and ROTATE, which are always done in their original mode. */
10043 simplify_shift_const (rtx x, enum rtx_code code, enum machine_mode result_mode,
10044 rtx varop, int count)
10046 rtx tem = simplify_shift_const_1 (code, result_mode, varop, count);
10051 x = simplify_gen_binary (code, GET_MODE (varop), varop, GEN_INT (count));
10052 if (GET_MODE (x) != result_mode)
10053 x = gen_lowpart (result_mode, x);
10058 /* Like recog, but we receive the address of a pointer to a new pattern.
10059 We try to match the rtx that the pointer points to.
10060 If that fails, we may try to modify or replace the pattern,
10061 storing the replacement into the same pointer object.
10063 Modifications include deletion or addition of CLOBBERs.
10065 PNOTES is a pointer to a location where any REG_UNUSED notes added for
10066 the CLOBBERs are placed.
10068 The value is the final insn code from the pattern ultimately matched,
10072 recog_for_combine (rtx *pnewpat, rtx insn, rtx *pnotes)
10074 rtx pat = *pnewpat;
10075 int insn_code_number;
10076 int num_clobbers_to_add = 0;
10079 rtx old_notes, old_pat;
10081 /* If PAT is a PARALLEL, check to see if it contains the CLOBBER
10082 we use to indicate that something didn't match. If we find such a
10083 thing, force rejection. */
10084 if (GET_CODE (pat) == PARALLEL)
10085 for (i = XVECLEN (pat, 0) - 1; i >= 0; i--)
10086 if (GET_CODE (XVECEXP (pat, 0, i)) == CLOBBER
10087 && XEXP (XVECEXP (pat, 0, i), 0) == const0_rtx)
10090 old_pat = PATTERN (insn);
10091 old_notes = REG_NOTES (insn);
10092 PATTERN (insn) = pat;
10093 REG_NOTES (insn) = 0;
10095 insn_code_number = recog (pat, insn, &num_clobbers_to_add);
10096 if (dump_file && (dump_flags & TDF_DETAILS))
10098 if (insn_code_number < 0)
10099 fputs ("Failed to match this instruction:\n", dump_file);
10101 fputs ("Successfully matched this instruction:\n", dump_file);
10102 print_rtl_single (dump_file, pat);
10105 /* If it isn't, there is the possibility that we previously had an insn
10106 that clobbered some register as a side effect, but the combined
10107 insn doesn't need to do that. So try once more without the clobbers
10108 unless this represents an ASM insn. */
10110 if (insn_code_number < 0 && ! check_asm_operands (pat)
10111 && GET_CODE (pat) == PARALLEL)
10115 for (pos = 0, i = 0; i < XVECLEN (pat, 0); i++)
10116 if (GET_CODE (XVECEXP (pat, 0, i)) != CLOBBER)
10119 SUBST (XVECEXP (pat, 0, pos), XVECEXP (pat, 0, i));
10123 SUBST_INT (XVECLEN (pat, 0), pos);
10126 pat = XVECEXP (pat, 0, 0);
10128 PATTERN (insn) = pat;
10129 insn_code_number = recog (pat, insn, &num_clobbers_to_add);
10130 if (dump_file && (dump_flags & TDF_DETAILS))
10132 if (insn_code_number < 0)
10133 fputs ("Failed to match this instruction:\n", dump_file);
10135 fputs ("Successfully matched this instruction:\n", dump_file);
10136 print_rtl_single (dump_file, pat);
10139 PATTERN (insn) = old_pat;
10140 REG_NOTES (insn) = old_notes;
10142 /* Recognize all noop sets, these will be killed by followup pass. */
10143 if (insn_code_number < 0 && GET_CODE (pat) == SET && set_noop_p (pat))
10144 insn_code_number = NOOP_MOVE_INSN_CODE, num_clobbers_to_add = 0;
10146 /* If we had any clobbers to add, make a new pattern than contains
10147 them. Then check to make sure that all of them are dead. */
10148 if (num_clobbers_to_add)
10150 rtx newpat = gen_rtx_PARALLEL (VOIDmode,
10151 rtvec_alloc (GET_CODE (pat) == PARALLEL
10152 ? (XVECLEN (pat, 0)
10153 + num_clobbers_to_add)
10154 : num_clobbers_to_add + 1));
10156 if (GET_CODE (pat) == PARALLEL)
10157 for (i = 0; i < XVECLEN (pat, 0); i++)
10158 XVECEXP (newpat, 0, i) = XVECEXP (pat, 0, i);
10160 XVECEXP (newpat, 0, 0) = pat;
10162 add_clobbers (newpat, insn_code_number);
10164 for (i = XVECLEN (newpat, 0) - num_clobbers_to_add;
10165 i < XVECLEN (newpat, 0); i++)
10167 if (REG_P (XEXP (XVECEXP (newpat, 0, i), 0))
10168 && ! reg_dead_at_p (XEXP (XVECEXP (newpat, 0, i), 0), insn))
10170 if (GET_CODE (XEXP (XVECEXP (newpat, 0, i), 0)) != SCRATCH)
10172 gcc_assert (REG_P (XEXP (XVECEXP (newpat, 0, i), 0)));
10173 notes = alloc_reg_note (REG_UNUSED,
10174 XEXP (XVECEXP (newpat, 0, i), 0), notes);
10183 return insn_code_number;
10186 /* Like gen_lowpart_general but for use by combine. In combine it
10187 is not possible to create any new pseudoregs. However, it is
10188 safe to create invalid memory addresses, because combine will
10189 try to recognize them and all they will do is make the combine
10192 If for some reason this cannot do its job, an rtx
10193 (clobber (const_int 0)) is returned.
10194 An insn containing that will not be recognized. */
10197 gen_lowpart_for_combine (enum machine_mode omode, rtx x)
10199 enum machine_mode imode = GET_MODE (x);
10200 unsigned int osize = GET_MODE_SIZE (omode);
10201 unsigned int isize = GET_MODE_SIZE (imode);
10204 if (omode == imode)
10207 /* Return identity if this is a CONST or symbolic reference. */
10209 && (GET_CODE (x) == CONST
10210 || GET_CODE (x) == SYMBOL_REF
10211 || GET_CODE (x) == LABEL_REF))
10214 /* We can only support MODE being wider than a word if X is a
10215 constant integer or has a mode the same size. */
10216 if (GET_MODE_SIZE (omode) > UNITS_PER_WORD
10217 && ! ((imode == VOIDmode
10218 && (CONST_INT_P (x)
10219 || GET_CODE (x) == CONST_DOUBLE))
10220 || isize == osize))
10223 /* X might be a paradoxical (subreg (mem)). In that case, gen_lowpart
10224 won't know what to do. So we will strip off the SUBREG here and
10225 process normally. */
10226 if (GET_CODE (x) == SUBREG && MEM_P (SUBREG_REG (x)))
10228 x = SUBREG_REG (x);
10230 /* For use in case we fall down into the address adjustments
10231 further below, we need to adjust the known mode and size of
10232 x; imode and isize, since we just adjusted x. */
10233 imode = GET_MODE (x);
10235 if (imode == omode)
10238 isize = GET_MODE_SIZE (imode);
10241 result = gen_lowpart_common (omode, x);
10250 /* Refuse to work on a volatile memory ref or one with a mode-dependent
10252 if (MEM_VOLATILE_P (x) || mode_dependent_address_p (XEXP (x, 0)))
10255 /* If we want to refer to something bigger than the original memref,
10256 generate a paradoxical subreg instead. That will force a reload
10257 of the original memref X. */
10259 return gen_rtx_SUBREG (omode, x, 0);
10261 if (WORDS_BIG_ENDIAN)
10262 offset = MAX (isize, UNITS_PER_WORD) - MAX (osize, UNITS_PER_WORD);
10264 /* Adjust the address so that the address-after-the-data is
10266 if (BYTES_BIG_ENDIAN)
10267 offset -= MIN (UNITS_PER_WORD, osize) - MIN (UNITS_PER_WORD, isize);
10269 return adjust_address_nv (x, omode, offset);
10272 /* If X is a comparison operator, rewrite it in a new mode. This
10273 probably won't match, but may allow further simplifications. */
10274 else if (COMPARISON_P (x))
10275 return gen_rtx_fmt_ee (GET_CODE (x), omode, XEXP (x, 0), XEXP (x, 1));
10277 /* If we couldn't simplify X any other way, just enclose it in a
10278 SUBREG. Normally, this SUBREG won't match, but some patterns may
10279 include an explicit SUBREG or we may simplify it further in combine. */
10285 offset = subreg_lowpart_offset (omode, imode);
10286 if (imode == VOIDmode)
10288 imode = int_mode_for_mode (omode);
10289 x = gen_lowpart_common (imode, x);
10293 res = simplify_gen_subreg (omode, x, imode, offset);
10299 return gen_rtx_CLOBBER (omode, const0_rtx);
10302 /* Simplify a comparison between *POP0 and *POP1 where CODE is the
10303 comparison code that will be tested.
10305 The result is a possibly different comparison code to use. *POP0 and
10306 *POP1 may be updated.
10308 It is possible that we might detect that a comparison is either always
10309 true or always false. However, we do not perform general constant
10310 folding in combine, so this knowledge isn't useful. Such tautologies
10311 should have been detected earlier. Hence we ignore all such cases. */
10313 static enum rtx_code
10314 simplify_comparison (enum rtx_code code, rtx *pop0, rtx *pop1)
10320 enum machine_mode mode, tmode;
10322 /* Try a few ways of applying the same transformation to both operands. */
10325 #ifndef WORD_REGISTER_OPERATIONS
10326 /* The test below this one won't handle SIGN_EXTENDs on these machines,
10327 so check specially. */
10328 if (code != GTU && code != GEU && code != LTU && code != LEU
10329 && GET_CODE (op0) == ASHIFTRT && GET_CODE (op1) == ASHIFTRT
10330 && GET_CODE (XEXP (op0, 0)) == ASHIFT
10331 && GET_CODE (XEXP (op1, 0)) == ASHIFT
10332 && GET_CODE (XEXP (XEXP (op0, 0), 0)) == SUBREG
10333 && GET_CODE (XEXP (XEXP (op1, 0), 0)) == SUBREG
10334 && (GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0)))
10335 == GET_MODE (SUBREG_REG (XEXP (XEXP (op1, 0), 0))))
10336 && CONST_INT_P (XEXP (op0, 1))
10337 && XEXP (op0, 1) == XEXP (op1, 1)
10338 && XEXP (op0, 1) == XEXP (XEXP (op0, 0), 1)
10339 && XEXP (op0, 1) == XEXP (XEXP (op1, 0), 1)
10340 && (INTVAL (XEXP (op0, 1))
10341 == (GET_MODE_BITSIZE (GET_MODE (op0))
10342 - (GET_MODE_BITSIZE
10343 (GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0))))))))
10345 op0 = SUBREG_REG (XEXP (XEXP (op0, 0), 0));
10346 op1 = SUBREG_REG (XEXP (XEXP (op1, 0), 0));
10350 /* If both operands are the same constant shift, see if we can ignore the
10351 shift. We can if the shift is a rotate or if the bits shifted out of
10352 this shift are known to be zero for both inputs and if the type of
10353 comparison is compatible with the shift. */
10354 if (GET_CODE (op0) == GET_CODE (op1)
10355 && GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
10356 && ((GET_CODE (op0) == ROTATE && (code == NE || code == EQ))
10357 || ((GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFT)
10358 && (code != GT && code != LT && code != GE && code != LE))
10359 || (GET_CODE (op0) == ASHIFTRT
10360 && (code != GTU && code != LTU
10361 && code != GEU && code != LEU)))
10362 && CONST_INT_P (XEXP (op0, 1))
10363 && INTVAL (XEXP (op0, 1)) >= 0
10364 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT
10365 && XEXP (op0, 1) == XEXP (op1, 1))
10367 enum machine_mode mode = GET_MODE (op0);
10368 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
10369 int shift_count = INTVAL (XEXP (op0, 1));
10371 if (GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFTRT)
10372 mask &= (mask >> shift_count) << shift_count;
10373 else if (GET_CODE (op0) == ASHIFT)
10374 mask = (mask & (mask << shift_count)) >> shift_count;
10376 if ((nonzero_bits (XEXP (op0, 0), mode) & ~mask) == 0
10377 && (nonzero_bits (XEXP (op1, 0), mode) & ~mask) == 0)
10378 op0 = XEXP (op0, 0), op1 = XEXP (op1, 0);
10383 /* If both operands are AND's of a paradoxical SUBREG by constant, the
10384 SUBREGs are of the same mode, and, in both cases, the AND would
10385 be redundant if the comparison was done in the narrower mode,
10386 do the comparison in the narrower mode (e.g., we are AND'ing with 1
10387 and the operand's possibly nonzero bits are 0xffffff01; in that case
10388 if we only care about QImode, we don't need the AND). This case
10389 occurs if the output mode of an scc insn is not SImode and
10390 STORE_FLAG_VALUE == 1 (e.g., the 386).
10392 Similarly, check for a case where the AND's are ZERO_EXTEND
10393 operations from some narrower mode even though a SUBREG is not
10396 else if (GET_CODE (op0) == AND && GET_CODE (op1) == AND
10397 && CONST_INT_P (XEXP (op0, 1))
10398 && CONST_INT_P (XEXP (op1, 1)))
10400 rtx inner_op0 = XEXP (op0, 0);
10401 rtx inner_op1 = XEXP (op1, 0);
10402 HOST_WIDE_INT c0 = INTVAL (XEXP (op0, 1));
10403 HOST_WIDE_INT c1 = INTVAL (XEXP (op1, 1));
10406 if (GET_CODE (inner_op0) == SUBREG && GET_CODE (inner_op1) == SUBREG
10407 && (GET_MODE_SIZE (GET_MODE (inner_op0))
10408 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (inner_op0))))
10409 && (GET_MODE (SUBREG_REG (inner_op0))
10410 == GET_MODE (SUBREG_REG (inner_op1)))
10411 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (inner_op0)))
10412 <= HOST_BITS_PER_WIDE_INT)
10413 && (0 == ((~c0) & nonzero_bits (SUBREG_REG (inner_op0),
10414 GET_MODE (SUBREG_REG (inner_op0)))))
10415 && (0 == ((~c1) & nonzero_bits (SUBREG_REG (inner_op1),
10416 GET_MODE (SUBREG_REG (inner_op1))))))
10418 op0 = SUBREG_REG (inner_op0);
10419 op1 = SUBREG_REG (inner_op1);
10421 /* The resulting comparison is always unsigned since we masked
10422 off the original sign bit. */
10423 code = unsigned_condition (code);
10429 for (tmode = GET_CLASS_NARROWEST_MODE
10430 (GET_MODE_CLASS (GET_MODE (op0)));
10431 tmode != GET_MODE (op0); tmode = GET_MODE_WIDER_MODE (tmode))
10432 if ((unsigned HOST_WIDE_INT) c0 == GET_MODE_MASK (tmode))
10434 op0 = gen_lowpart (tmode, inner_op0);
10435 op1 = gen_lowpart (tmode, inner_op1);
10436 code = unsigned_condition (code);
10445 /* If both operands are NOT, we can strip off the outer operation
10446 and adjust the comparison code for swapped operands; similarly for
10447 NEG, except that this must be an equality comparison. */
10448 else if ((GET_CODE (op0) == NOT && GET_CODE (op1) == NOT)
10449 || (GET_CODE (op0) == NEG && GET_CODE (op1) == NEG
10450 && (code == EQ || code == NE)))
10451 op0 = XEXP (op0, 0), op1 = XEXP (op1, 0), code = swap_condition (code);
10457 /* If the first operand is a constant, swap the operands and adjust the
10458 comparison code appropriately, but don't do this if the second operand
10459 is already a constant integer. */
10460 if (swap_commutative_operands_p (op0, op1))
10462 tem = op0, op0 = op1, op1 = tem;
10463 code = swap_condition (code);
10466 /* We now enter a loop during which we will try to simplify the comparison.
10467 For the most part, we only are concerned with comparisons with zero,
10468 but some things may really be comparisons with zero but not start
10469 out looking that way. */
10471 while (CONST_INT_P (op1))
10473 enum machine_mode mode = GET_MODE (op0);
10474 unsigned int mode_width = GET_MODE_BITSIZE (mode);
10475 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
10476 int equality_comparison_p;
10477 int sign_bit_comparison_p;
10478 int unsigned_comparison_p;
10479 HOST_WIDE_INT const_op;
10481 /* We only want to handle integral modes. This catches VOIDmode,
10482 CCmode, and the floating-point modes. An exception is that we
10483 can handle VOIDmode if OP0 is a COMPARE or a comparison
10486 if (GET_MODE_CLASS (mode) != MODE_INT
10487 && ! (mode == VOIDmode
10488 && (GET_CODE (op0) == COMPARE || COMPARISON_P (op0))))
10491 /* Get the constant we are comparing against and turn off all bits
10492 not on in our mode. */
10493 const_op = INTVAL (op1);
10494 if (mode != VOIDmode)
10495 const_op = trunc_int_for_mode (const_op, mode);
10496 op1 = GEN_INT (const_op);
10498 /* If we are comparing against a constant power of two and the value
10499 being compared can only have that single bit nonzero (e.g., it was
10500 `and'ed with that bit), we can replace this with a comparison
10503 && (code == EQ || code == NE || code == GE || code == GEU
10504 || code == LT || code == LTU)
10505 && mode_width <= HOST_BITS_PER_WIDE_INT
10506 && exact_log2 (const_op) >= 0
10507 && nonzero_bits (op0, mode) == (unsigned HOST_WIDE_INT) const_op)
10509 code = (code == EQ || code == GE || code == GEU ? NE : EQ);
10510 op1 = const0_rtx, const_op = 0;
10513 /* Similarly, if we are comparing a value known to be either -1 or
10514 0 with -1, change it to the opposite comparison against zero. */
10517 && (code == EQ || code == NE || code == GT || code == LE
10518 || code == GEU || code == LTU)
10519 && num_sign_bit_copies (op0, mode) == mode_width)
10521 code = (code == EQ || code == LE || code == GEU ? NE : EQ);
10522 op1 = const0_rtx, const_op = 0;
10525 /* Do some canonicalizations based on the comparison code. We prefer
10526 comparisons against zero and then prefer equality comparisons.
10527 If we can reduce the size of a constant, we will do that too. */
10532 /* < C is equivalent to <= (C - 1) */
10536 op1 = GEN_INT (const_op);
10538 /* ... fall through to LE case below. */
10544 /* <= C is equivalent to < (C + 1); we do this for C < 0 */
10548 op1 = GEN_INT (const_op);
10552 /* If we are doing a <= 0 comparison on a value known to have
10553 a zero sign bit, we can replace this with == 0. */
10554 else if (const_op == 0
10555 && mode_width <= HOST_BITS_PER_WIDE_INT
10556 && (nonzero_bits (op0, mode)
10557 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)
10562 /* >= C is equivalent to > (C - 1). */
10566 op1 = GEN_INT (const_op);
10568 /* ... fall through to GT below. */
10574 /* > C is equivalent to >= (C + 1); we do this for C < 0. */
10578 op1 = GEN_INT (const_op);
10582 /* If we are doing a > 0 comparison on a value known to have
10583 a zero sign bit, we can replace this with != 0. */
10584 else if (const_op == 0
10585 && mode_width <= HOST_BITS_PER_WIDE_INT
10586 && (nonzero_bits (op0, mode)
10587 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)
10592 /* < C is equivalent to <= (C - 1). */
10596 op1 = GEN_INT (const_op);
10598 /* ... fall through ... */
10601 /* (unsigned) < 0x80000000 is equivalent to >= 0. */
10602 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
10603 && (const_op == (HOST_WIDE_INT) 1 << (mode_width - 1)))
10605 const_op = 0, op1 = const0_rtx;
10613 /* unsigned <= 0 is equivalent to == 0 */
10617 /* (unsigned) <= 0x7fffffff is equivalent to >= 0. */
10618 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
10619 && (const_op == ((HOST_WIDE_INT) 1 << (mode_width - 1)) - 1))
10621 const_op = 0, op1 = const0_rtx;
10627 /* >= C is equivalent to > (C - 1). */
10631 op1 = GEN_INT (const_op);
10633 /* ... fall through ... */
10636 /* (unsigned) >= 0x80000000 is equivalent to < 0. */
10637 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
10638 && (const_op == (HOST_WIDE_INT) 1 << (mode_width - 1)))
10640 const_op = 0, op1 = const0_rtx;
10648 /* unsigned > 0 is equivalent to != 0 */
10652 /* (unsigned) > 0x7fffffff is equivalent to < 0. */
10653 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
10654 && (const_op == ((HOST_WIDE_INT) 1 << (mode_width - 1)) - 1))
10656 const_op = 0, op1 = const0_rtx;
10665 /* Compute some predicates to simplify code below. */
10667 equality_comparison_p = (code == EQ || code == NE);
10668 sign_bit_comparison_p = ((code == LT || code == GE) && const_op == 0);
10669 unsigned_comparison_p = (code == LTU || code == LEU || code == GTU
10672 /* If this is a sign bit comparison and we can do arithmetic in
10673 MODE, say that we will only be needing the sign bit of OP0. */
10674 if (sign_bit_comparison_p
10675 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
10676 op0 = force_to_mode (op0, mode,
10678 << (GET_MODE_BITSIZE (mode) - 1)),
10681 /* Now try cases based on the opcode of OP0. If none of the cases
10682 does a "continue", we exit this loop immediately after the
10685 switch (GET_CODE (op0))
10688 /* If we are extracting a single bit from a variable position in
10689 a constant that has only a single bit set and are comparing it
10690 with zero, we can convert this into an equality comparison
10691 between the position and the location of the single bit. */
10692 /* Except we can't if SHIFT_COUNT_TRUNCATED is set, since we might
10693 have already reduced the shift count modulo the word size. */
10694 if (!SHIFT_COUNT_TRUNCATED
10695 && CONST_INT_P (XEXP (op0, 0))
10696 && XEXP (op0, 1) == const1_rtx
10697 && equality_comparison_p && const_op == 0
10698 && (i = exact_log2 (INTVAL (XEXP (op0, 0)))) >= 0)
10700 if (BITS_BIG_ENDIAN)
10702 enum machine_mode new_mode
10703 = mode_for_extraction (EP_extzv, 1);
10704 if (new_mode == MAX_MACHINE_MODE)
10705 i = BITS_PER_WORD - 1 - i;
10709 i = (GET_MODE_BITSIZE (mode) - 1 - i);
10713 op0 = XEXP (op0, 2);
10717 /* Result is nonzero iff shift count is equal to I. */
10718 code = reverse_condition (code);
10722 /* ... fall through ... */
10725 tem = expand_compound_operation (op0);
10734 /* If testing for equality, we can take the NOT of the constant. */
10735 if (equality_comparison_p
10736 && (tem = simplify_unary_operation (NOT, mode, op1, mode)) != 0)
10738 op0 = XEXP (op0, 0);
10743 /* If just looking at the sign bit, reverse the sense of the
10745 if (sign_bit_comparison_p)
10747 op0 = XEXP (op0, 0);
10748 code = (code == GE ? LT : GE);
10754 /* If testing for equality, we can take the NEG of the constant. */
10755 if (equality_comparison_p
10756 && (tem = simplify_unary_operation (NEG, mode, op1, mode)) != 0)
10758 op0 = XEXP (op0, 0);
10763 /* The remaining cases only apply to comparisons with zero. */
10767 /* When X is ABS or is known positive,
10768 (neg X) is < 0 if and only if X != 0. */
10770 if (sign_bit_comparison_p
10771 && (GET_CODE (XEXP (op0, 0)) == ABS
10772 || (mode_width <= HOST_BITS_PER_WIDE_INT
10773 && (nonzero_bits (XEXP (op0, 0), mode)
10774 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)))
10776 op0 = XEXP (op0, 0);
10777 code = (code == LT ? NE : EQ);
10781 /* If we have NEG of something whose two high-order bits are the
10782 same, we know that "(-a) < 0" is equivalent to "a > 0". */
10783 if (num_sign_bit_copies (op0, mode) >= 2)
10785 op0 = XEXP (op0, 0);
10786 code = swap_condition (code);
10792 /* If we are testing equality and our count is a constant, we
10793 can perform the inverse operation on our RHS. */
10794 if (equality_comparison_p && CONST_INT_P (XEXP (op0, 1))
10795 && (tem = simplify_binary_operation (ROTATERT, mode,
10796 op1, XEXP (op0, 1))) != 0)
10798 op0 = XEXP (op0, 0);
10803 /* If we are doing a < 0 or >= 0 comparison, it means we are testing
10804 a particular bit. Convert it to an AND of a constant of that
10805 bit. This will be converted into a ZERO_EXTRACT. */
10806 if (const_op == 0 && sign_bit_comparison_p
10807 && CONST_INT_P (XEXP (op0, 1))
10808 && mode_width <= HOST_BITS_PER_WIDE_INT)
10810 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
10813 - INTVAL (XEXP (op0, 1)))));
10814 code = (code == LT ? NE : EQ);
10818 /* Fall through. */
10821 /* ABS is ignorable inside an equality comparison with zero. */
10822 if (const_op == 0 && equality_comparison_p)
10824 op0 = XEXP (op0, 0);
10830 /* Can simplify (compare (zero/sign_extend FOO) CONST) to
10831 (compare FOO CONST) if CONST fits in FOO's mode and we
10832 are either testing inequality or have an unsigned
10833 comparison with ZERO_EXTEND or a signed comparison with
10834 SIGN_EXTEND. But don't do it if we don't have a compare
10835 insn of the given mode, since we'd have to revert it
10836 later on, and then we wouldn't know whether to sign- or
10838 mode = GET_MODE (XEXP (op0, 0));
10839 if (mode != VOIDmode && GET_MODE_CLASS (mode) == MODE_INT
10840 && ! unsigned_comparison_p
10841 && (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
10842 && ((unsigned HOST_WIDE_INT) const_op
10843 < (((unsigned HOST_WIDE_INT) 1
10844 << (GET_MODE_BITSIZE (mode) - 1))))
10845 && have_insn_for (COMPARE, mode))
10847 op0 = XEXP (op0, 0);
10853 /* Check for the case where we are comparing A - C1 with C2, that is
10855 (subreg:MODE (plus (A) (-C1))) op (C2)
10857 with C1 a constant, and try to lift the SUBREG, i.e. to do the
10858 comparison in the wider mode. One of the following two conditions
10859 must be true in order for this to be valid:
10861 1. The mode extension results in the same bit pattern being added
10862 on both sides and the comparison is equality or unsigned. As
10863 C2 has been truncated to fit in MODE, the pattern can only be
10866 2. The mode extension results in the sign bit being copied on
10869 The difficulty here is that we have predicates for A but not for
10870 (A - C1) so we need to check that C1 is within proper bounds so
10871 as to perturbate A as little as possible. */
10873 if (mode_width <= HOST_BITS_PER_WIDE_INT
10874 && subreg_lowpart_p (op0)
10875 && GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0))) > mode_width
10876 && GET_CODE (SUBREG_REG (op0)) == PLUS
10877 && CONST_INT_P (XEXP (SUBREG_REG (op0), 1)))
10879 enum machine_mode inner_mode = GET_MODE (SUBREG_REG (op0));
10880 rtx a = XEXP (SUBREG_REG (op0), 0);
10881 HOST_WIDE_INT c1 = -INTVAL (XEXP (SUBREG_REG (op0), 1));
10884 && (unsigned HOST_WIDE_INT) c1
10885 < (unsigned HOST_WIDE_INT) 1 << (mode_width - 1)
10886 && (equality_comparison_p || unsigned_comparison_p)
10887 /* (A - C1) zero-extends if it is positive and sign-extends
10888 if it is negative, C2 both zero- and sign-extends. */
10889 && ((0 == (nonzero_bits (a, inner_mode)
10890 & ~GET_MODE_MASK (mode))
10892 /* (A - C1) sign-extends if it is positive and 1-extends
10893 if it is negative, C2 both sign- and 1-extends. */
10894 || (num_sign_bit_copies (a, inner_mode)
10895 > (unsigned int) (GET_MODE_BITSIZE (inner_mode)
10898 || ((unsigned HOST_WIDE_INT) c1
10899 < (unsigned HOST_WIDE_INT) 1 << (mode_width - 2)
10900 /* (A - C1) always sign-extends, like C2. */
10901 && num_sign_bit_copies (a, inner_mode)
10902 > (unsigned int) (GET_MODE_BITSIZE (inner_mode)
10903 - (mode_width - 1))))
10905 op0 = SUBREG_REG (op0);
10910 /* If the inner mode is narrower and we are extracting the low part,
10911 we can treat the SUBREG as if it were a ZERO_EXTEND. */
10912 if (subreg_lowpart_p (op0)
10913 && GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0))) < mode_width)
10914 /* Fall through */ ;
10918 /* ... fall through ... */
10921 mode = GET_MODE (XEXP (op0, 0));
10922 if (mode != VOIDmode && GET_MODE_CLASS (mode) == MODE_INT
10923 && (unsigned_comparison_p || equality_comparison_p)
10924 && (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
10925 && ((unsigned HOST_WIDE_INT) const_op < GET_MODE_MASK (mode))
10926 && have_insn_for (COMPARE, mode))
10928 op0 = XEXP (op0, 0);
10934 /* (eq (plus X A) B) -> (eq X (minus B A)). We can only do
10935 this for equality comparisons due to pathological cases involving
10937 if (equality_comparison_p
10938 && 0 != (tem = simplify_binary_operation (MINUS, mode,
10939 op1, XEXP (op0, 1))))
10941 op0 = XEXP (op0, 0);
10946 /* (plus (abs X) (const_int -1)) is < 0 if and only if X == 0. */
10947 if (const_op == 0 && XEXP (op0, 1) == constm1_rtx
10948 && GET_CODE (XEXP (op0, 0)) == ABS && sign_bit_comparison_p)
10950 op0 = XEXP (XEXP (op0, 0), 0);
10951 code = (code == LT ? EQ : NE);
10957 /* We used to optimize signed comparisons against zero, but that
10958 was incorrect. Unsigned comparisons against zero (GTU, LEU)
10959 arrive here as equality comparisons, or (GEU, LTU) are
10960 optimized away. No need to special-case them. */
10962 /* (eq (minus A B) C) -> (eq A (plus B C)) or
10963 (eq B (minus A C)), whichever simplifies. We can only do
10964 this for equality comparisons due to pathological cases involving
10966 if (equality_comparison_p
10967 && 0 != (tem = simplify_binary_operation (PLUS, mode,
10968 XEXP (op0, 1), op1)))
10970 op0 = XEXP (op0, 0);
10975 if (equality_comparison_p
10976 && 0 != (tem = simplify_binary_operation (MINUS, mode,
10977 XEXP (op0, 0), op1)))
10979 op0 = XEXP (op0, 1);
10984 /* The sign bit of (minus (ashiftrt X C) X), where C is the number
10985 of bits in X minus 1, is one iff X > 0. */
10986 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == ASHIFTRT
10987 && CONST_INT_P (XEXP (XEXP (op0, 0), 1))
10988 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (XEXP (op0, 0), 1))
10990 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
10992 op0 = XEXP (op0, 1);
10993 code = (code == GE ? LE : GT);
10999 /* (eq (xor A B) C) -> (eq A (xor B C)). This is a simplification
11000 if C is zero or B is a constant. */
11001 if (equality_comparison_p
11002 && 0 != (tem = simplify_binary_operation (XOR, mode,
11003 XEXP (op0, 1), op1)))
11005 op0 = XEXP (op0, 0);
11012 case UNEQ: case LTGT:
11013 case LT: case LTU: case UNLT: case LE: case LEU: case UNLE:
11014 case GT: case GTU: case UNGT: case GE: case GEU: case UNGE:
11015 case UNORDERED: case ORDERED:
11016 /* We can't do anything if OP0 is a condition code value, rather
11017 than an actual data value. */
11019 || CC0_P (XEXP (op0, 0))
11020 || GET_MODE_CLASS (GET_MODE (XEXP (op0, 0))) == MODE_CC)
11023 /* Get the two operands being compared. */
11024 if (GET_CODE (XEXP (op0, 0)) == COMPARE)
11025 tem = XEXP (XEXP (op0, 0), 0), tem1 = XEXP (XEXP (op0, 0), 1);
11027 tem = XEXP (op0, 0), tem1 = XEXP (op0, 1);
11029 /* Check for the cases where we simply want the result of the
11030 earlier test or the opposite of that result. */
11031 if (code == NE || code == EQ
11032 || (GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
11033 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
11034 && (STORE_FLAG_VALUE
11035 & (((HOST_WIDE_INT) 1
11036 << (GET_MODE_BITSIZE (GET_MODE (op0)) - 1))))
11037 && (code == LT || code == GE)))
11039 enum rtx_code new_code;
11040 if (code == LT || code == NE)
11041 new_code = GET_CODE (op0);
11043 new_code = reversed_comparison_code (op0, NULL);
11045 if (new_code != UNKNOWN)
11056 /* The sign bit of (ior (plus X (const_int -1)) X) is nonzero
11058 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == PLUS
11059 && XEXP (XEXP (op0, 0), 1) == constm1_rtx
11060 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
11062 op0 = XEXP (op0, 1);
11063 code = (code == GE ? GT : LE);
11069 /* Convert (and (xshift 1 X) Y) to (and (lshiftrt Y X) 1). This
11070 will be converted to a ZERO_EXTRACT later. */
11071 if (const_op == 0 && equality_comparison_p
11072 && GET_CODE (XEXP (op0, 0)) == ASHIFT
11073 && XEXP (XEXP (op0, 0), 0) == const1_rtx)
11075 op0 = simplify_and_const_int
11076 (NULL_RTX, mode, gen_rtx_LSHIFTRT (mode,
11078 XEXP (XEXP (op0, 0), 1)),
11079 (HOST_WIDE_INT) 1);
11083 /* If we are comparing (and (lshiftrt X C1) C2) for equality with
11084 zero and X is a comparison and C1 and C2 describe only bits set
11085 in STORE_FLAG_VALUE, we can compare with X. */
11086 if (const_op == 0 && equality_comparison_p
11087 && mode_width <= HOST_BITS_PER_WIDE_INT
11088 && CONST_INT_P (XEXP (op0, 1))
11089 && GET_CODE (XEXP (op0, 0)) == LSHIFTRT
11090 && CONST_INT_P (XEXP (XEXP (op0, 0), 1))
11091 && INTVAL (XEXP (XEXP (op0, 0), 1)) >= 0
11092 && INTVAL (XEXP (XEXP (op0, 0), 1)) < HOST_BITS_PER_WIDE_INT)
11094 mask = ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
11095 << INTVAL (XEXP (XEXP (op0, 0), 1)));
11096 if ((~STORE_FLAG_VALUE & mask) == 0
11097 && (COMPARISON_P (XEXP (XEXP (op0, 0), 0))
11098 || ((tem = get_last_value (XEXP (XEXP (op0, 0), 0))) != 0
11099 && COMPARISON_P (tem))))
11101 op0 = XEXP (XEXP (op0, 0), 0);
11106 /* If we are doing an equality comparison of an AND of a bit equal
11107 to the sign bit, replace this with a LT or GE comparison of
11108 the underlying value. */
11109 if (equality_comparison_p
11111 && CONST_INT_P (XEXP (op0, 1))
11112 && mode_width <= HOST_BITS_PER_WIDE_INT
11113 && ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
11114 == (unsigned HOST_WIDE_INT) 1 << (mode_width - 1)))
11116 op0 = XEXP (op0, 0);
11117 code = (code == EQ ? GE : LT);
11121 /* If this AND operation is really a ZERO_EXTEND from a narrower
11122 mode, the constant fits within that mode, and this is either an
11123 equality or unsigned comparison, try to do this comparison in
11128 (ne:DI (and:DI (reg:DI 4) (const_int 0xffffffff)) (const_int 0))
11129 -> (ne:DI (reg:SI 4) (const_int 0))
11131 unless TRULY_NOOP_TRUNCATION allows it or the register is
11132 known to hold a value of the required mode the
11133 transformation is invalid. */
11134 if ((equality_comparison_p || unsigned_comparison_p)
11135 && CONST_INT_P (XEXP (op0, 1))
11136 && (i = exact_log2 ((INTVAL (XEXP (op0, 1))
11137 & GET_MODE_MASK (mode))
11139 && const_op >> i == 0
11140 && (tmode = mode_for_size (i, MODE_INT, 1)) != BLKmode
11141 && (TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (tmode),
11142 GET_MODE_BITSIZE (GET_MODE (op0)))
11143 || (REG_P (XEXP (op0, 0))
11144 && reg_truncated_to_mode (tmode, XEXP (op0, 0)))))
11146 op0 = gen_lowpart (tmode, XEXP (op0, 0));
11150 /* If this is (and:M1 (subreg:M2 X 0) (const_int C1)) where C1
11151 fits in both M1 and M2 and the SUBREG is either paradoxical
11152 or represents the low part, permute the SUBREG and the AND
11154 if (GET_CODE (XEXP (op0, 0)) == SUBREG)
11156 unsigned HOST_WIDE_INT c1;
11157 tmode = GET_MODE (SUBREG_REG (XEXP (op0, 0)));
11158 /* Require an integral mode, to avoid creating something like
11160 if (SCALAR_INT_MODE_P (tmode)
11161 /* It is unsafe to commute the AND into the SUBREG if the
11162 SUBREG is paradoxical and WORD_REGISTER_OPERATIONS is
11163 not defined. As originally written the upper bits
11164 have a defined value due to the AND operation.
11165 However, if we commute the AND inside the SUBREG then
11166 they no longer have defined values and the meaning of
11167 the code has been changed. */
11169 #ifdef WORD_REGISTER_OPERATIONS
11170 || (mode_width > GET_MODE_BITSIZE (tmode)
11171 && mode_width <= BITS_PER_WORD)
11173 || (mode_width <= GET_MODE_BITSIZE (tmode)
11174 && subreg_lowpart_p (XEXP (op0, 0))))
11175 && CONST_INT_P (XEXP (op0, 1))
11176 && mode_width <= HOST_BITS_PER_WIDE_INT
11177 && GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT
11178 && ((c1 = INTVAL (XEXP (op0, 1))) & ~mask) == 0
11179 && (c1 & ~GET_MODE_MASK (tmode)) == 0
11181 && c1 != GET_MODE_MASK (tmode))
11183 op0 = simplify_gen_binary (AND, tmode,
11184 SUBREG_REG (XEXP (op0, 0)),
11185 gen_int_mode (c1, tmode));
11186 op0 = gen_lowpart (mode, op0);
11191 /* Convert (ne (and (not X) 1) 0) to (eq (and X 1) 0). */
11192 if (const_op == 0 && equality_comparison_p
11193 && XEXP (op0, 1) == const1_rtx
11194 && GET_CODE (XEXP (op0, 0)) == NOT)
11196 op0 = simplify_and_const_int
11197 (NULL_RTX, mode, XEXP (XEXP (op0, 0), 0), (HOST_WIDE_INT) 1);
11198 code = (code == NE ? EQ : NE);
11202 /* Convert (ne (and (lshiftrt (not X)) 1) 0) to
11203 (eq (and (lshiftrt X) 1) 0).
11204 Also handle the case where (not X) is expressed using xor. */
11205 if (const_op == 0 && equality_comparison_p
11206 && XEXP (op0, 1) == const1_rtx
11207 && GET_CODE (XEXP (op0, 0)) == LSHIFTRT)
11209 rtx shift_op = XEXP (XEXP (op0, 0), 0);
11210 rtx shift_count = XEXP (XEXP (op0, 0), 1);
11212 if (GET_CODE (shift_op) == NOT
11213 || (GET_CODE (shift_op) == XOR
11214 && CONST_INT_P (XEXP (shift_op, 1))
11215 && CONST_INT_P (shift_count)
11216 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
11217 && (INTVAL (XEXP (shift_op, 1))
11218 == (HOST_WIDE_INT) 1 << INTVAL (shift_count))))
11220 op0 = simplify_and_const_int
11222 gen_rtx_LSHIFTRT (mode, XEXP (shift_op, 0), shift_count),
11223 (HOST_WIDE_INT) 1);
11224 code = (code == NE ? EQ : NE);
11231 /* If we have (compare (ashift FOO N) (const_int C)) and
11232 the high order N bits of FOO (N+1 if an inequality comparison)
11233 are known to be zero, we can do this by comparing FOO with C
11234 shifted right N bits so long as the low-order N bits of C are
11236 if (CONST_INT_P (XEXP (op0, 1))
11237 && INTVAL (XEXP (op0, 1)) >= 0
11238 && ((INTVAL (XEXP (op0, 1)) + ! equality_comparison_p)
11239 < HOST_BITS_PER_WIDE_INT)
11241 & (((HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1))) - 1)) == 0)
11242 && mode_width <= HOST_BITS_PER_WIDE_INT
11243 && (nonzero_bits (XEXP (op0, 0), mode)
11244 & ~(mask >> (INTVAL (XEXP (op0, 1))
11245 + ! equality_comparison_p))) == 0)
11247 /* We must perform a logical shift, not an arithmetic one,
11248 as we want the top N bits of C to be zero. */
11249 unsigned HOST_WIDE_INT temp = const_op & GET_MODE_MASK (mode);
11251 temp >>= INTVAL (XEXP (op0, 1));
11252 op1 = gen_int_mode (temp, mode);
11253 op0 = XEXP (op0, 0);
11257 /* If we are doing a sign bit comparison, it means we are testing
11258 a particular bit. Convert it to the appropriate AND. */
11259 if (sign_bit_comparison_p && CONST_INT_P (XEXP (op0, 1))
11260 && mode_width <= HOST_BITS_PER_WIDE_INT)
11262 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
11265 - INTVAL (XEXP (op0, 1)))));
11266 code = (code == LT ? NE : EQ);
11270 /* If this an equality comparison with zero and we are shifting
11271 the low bit to the sign bit, we can convert this to an AND of the
11273 if (const_op == 0 && equality_comparison_p
11274 && CONST_INT_P (XEXP (op0, 1))
11275 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (op0, 1))
11278 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
11279 (HOST_WIDE_INT) 1);
11285 /* If this is an equality comparison with zero, we can do this
11286 as a logical shift, which might be much simpler. */
11287 if (equality_comparison_p && const_op == 0
11288 && CONST_INT_P (XEXP (op0, 1)))
11290 op0 = simplify_shift_const (NULL_RTX, LSHIFTRT, mode,
11292 INTVAL (XEXP (op0, 1)));
11296 /* If OP0 is a sign extension and CODE is not an unsigned comparison,
11297 do the comparison in a narrower mode. */
11298 if (! unsigned_comparison_p
11299 && CONST_INT_P (XEXP (op0, 1))
11300 && GET_CODE (XEXP (op0, 0)) == ASHIFT
11301 && XEXP (op0, 1) == XEXP (XEXP (op0, 0), 1)
11302 && (tmode = mode_for_size (mode_width - INTVAL (XEXP (op0, 1)),
11303 MODE_INT, 1)) != BLKmode
11304 && (((unsigned HOST_WIDE_INT) const_op
11305 + (GET_MODE_MASK (tmode) >> 1) + 1)
11306 <= GET_MODE_MASK (tmode)))
11308 op0 = gen_lowpart (tmode, XEXP (XEXP (op0, 0), 0));
11312 /* Likewise if OP0 is a PLUS of a sign extension with a
11313 constant, which is usually represented with the PLUS
11314 between the shifts. */
11315 if (! unsigned_comparison_p
11316 && CONST_INT_P (XEXP (op0, 1))
11317 && GET_CODE (XEXP (op0, 0)) == PLUS
11318 && CONST_INT_P (XEXP (XEXP (op0, 0), 1))
11319 && GET_CODE (XEXP (XEXP (op0, 0), 0)) == ASHIFT
11320 && XEXP (op0, 1) == XEXP (XEXP (XEXP (op0, 0), 0), 1)
11321 && (tmode = mode_for_size (mode_width - INTVAL (XEXP (op0, 1)),
11322 MODE_INT, 1)) != BLKmode
11323 && (((unsigned HOST_WIDE_INT) const_op
11324 + (GET_MODE_MASK (tmode) >> 1) + 1)
11325 <= GET_MODE_MASK (tmode)))
11327 rtx inner = XEXP (XEXP (XEXP (op0, 0), 0), 0);
11328 rtx add_const = XEXP (XEXP (op0, 0), 1);
11329 rtx new_const = simplify_gen_binary (ASHIFTRT, GET_MODE (op0),
11330 add_const, XEXP (op0, 1));
11332 op0 = simplify_gen_binary (PLUS, tmode,
11333 gen_lowpart (tmode, inner),
11338 /* ... fall through ... */
11340 /* If we have (compare (xshiftrt FOO N) (const_int C)) and
11341 the low order N bits of FOO are known to be zero, we can do this
11342 by comparing FOO with C shifted left N bits so long as no
11343 overflow occurs. */
11344 if (CONST_INT_P (XEXP (op0, 1))
11345 && INTVAL (XEXP (op0, 1)) >= 0
11346 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT
11347 && mode_width <= HOST_BITS_PER_WIDE_INT
11348 && (nonzero_bits (XEXP (op0, 0), mode)
11349 & (((HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1))) - 1)) == 0
11350 && (((unsigned HOST_WIDE_INT) const_op
11351 + (GET_CODE (op0) != LSHIFTRT
11352 ? ((GET_MODE_MASK (mode) >> INTVAL (XEXP (op0, 1)) >> 1)
11355 <= GET_MODE_MASK (mode) >> INTVAL (XEXP (op0, 1))))
11357 /* If the shift was logical, then we must make the condition
11359 if (GET_CODE (op0) == LSHIFTRT)
11360 code = unsigned_condition (code);
11362 const_op <<= INTVAL (XEXP (op0, 1));
11363 op1 = GEN_INT (const_op);
11364 op0 = XEXP (op0, 0);
11368 /* If we are using this shift to extract just the sign bit, we
11369 can replace this with an LT or GE comparison. */
11371 && (equality_comparison_p || sign_bit_comparison_p)
11372 && CONST_INT_P (XEXP (op0, 1))
11373 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (op0, 1))
11376 op0 = XEXP (op0, 0);
11377 code = (code == NE || code == GT ? LT : GE);
11389 /* Now make any compound operations involved in this comparison. Then,
11390 check for an outmost SUBREG on OP0 that is not doing anything or is
11391 paradoxical. The latter transformation must only be performed when
11392 it is known that the "extra" bits will be the same in op0 and op1 or
11393 that they don't matter. There are three cases to consider:
11395 1. SUBREG_REG (op0) is a register. In this case the bits are don't
11396 care bits and we can assume they have any convenient value. So
11397 making the transformation is safe.
11399 2. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is not defined.
11400 In this case the upper bits of op0 are undefined. We should not make
11401 the simplification in that case as we do not know the contents of
11404 3. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is defined and not
11405 UNKNOWN. In that case we know those bits are zeros or ones. We must
11406 also be sure that they are the same as the upper bits of op1.
11408 We can never remove a SUBREG for a non-equality comparison because
11409 the sign bit is in a different place in the underlying object. */
11411 op0 = make_compound_operation (op0, op1 == const0_rtx ? COMPARE : SET);
11412 op1 = make_compound_operation (op1, SET);
11414 if (GET_CODE (op0) == SUBREG && subreg_lowpart_p (op0)
11415 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
11416 && GET_MODE_CLASS (GET_MODE (SUBREG_REG (op0))) == MODE_INT
11417 && (code == NE || code == EQ))
11419 if (GET_MODE_SIZE (GET_MODE (op0))
11420 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (op0))))
11422 /* For paradoxical subregs, allow case 1 as above. Case 3 isn't
11424 if (REG_P (SUBREG_REG (op0)))
11426 op0 = SUBREG_REG (op0);
11427 op1 = gen_lowpart (GET_MODE (op0), op1);
11430 else if ((GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0)))
11431 <= HOST_BITS_PER_WIDE_INT)
11432 && (nonzero_bits (SUBREG_REG (op0),
11433 GET_MODE (SUBREG_REG (op0)))
11434 & ~GET_MODE_MASK (GET_MODE (op0))) == 0)
11436 tem = gen_lowpart (GET_MODE (SUBREG_REG (op0)), op1);
11438 if ((nonzero_bits (tem, GET_MODE (SUBREG_REG (op0)))
11439 & ~GET_MODE_MASK (GET_MODE (op0))) == 0)
11440 op0 = SUBREG_REG (op0), op1 = tem;
11444 /* We now do the opposite procedure: Some machines don't have compare
11445 insns in all modes. If OP0's mode is an integer mode smaller than a
11446 word and we can't do a compare in that mode, see if there is a larger
11447 mode for which we can do the compare. There are a number of cases in
11448 which we can use the wider mode. */
11450 mode = GET_MODE (op0);
11451 if (mode != VOIDmode && GET_MODE_CLASS (mode) == MODE_INT
11452 && GET_MODE_SIZE (mode) < UNITS_PER_WORD
11453 && ! have_insn_for (COMPARE, mode))
11454 for (tmode = GET_MODE_WIDER_MODE (mode);
11456 && GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT);
11457 tmode = GET_MODE_WIDER_MODE (tmode))
11458 if (have_insn_for (COMPARE, tmode))
11462 /* If this is a test for negative, we can make an explicit
11463 test of the sign bit. Test this first so we can use
11464 a paradoxical subreg to extend OP0. */
11466 if (op1 == const0_rtx && (code == LT || code == GE)
11467 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
11469 op0 = simplify_gen_binary (AND, tmode,
11470 gen_lowpart (tmode, op0),
11471 GEN_INT ((HOST_WIDE_INT) 1
11472 << (GET_MODE_BITSIZE (mode)
11474 code = (code == LT) ? NE : EQ;
11478 /* If the only nonzero bits in OP0 and OP1 are those in the
11479 narrower mode and this is an equality or unsigned comparison,
11480 we can use the wider mode. Similarly for sign-extended
11481 values, in which case it is true for all comparisons. */
11482 zero_extended = ((code == EQ || code == NE
11483 || code == GEU || code == GTU
11484 || code == LEU || code == LTU)
11485 && (nonzero_bits (op0, tmode)
11486 & ~GET_MODE_MASK (mode)) == 0
11487 && ((CONST_INT_P (op1)
11488 || (nonzero_bits (op1, tmode)
11489 & ~GET_MODE_MASK (mode)) == 0)));
11492 || ((num_sign_bit_copies (op0, tmode)
11493 > (unsigned int) (GET_MODE_BITSIZE (tmode)
11494 - GET_MODE_BITSIZE (mode)))
11495 && (num_sign_bit_copies (op1, tmode)
11496 > (unsigned int) (GET_MODE_BITSIZE (tmode)
11497 - GET_MODE_BITSIZE (mode)))))
11499 /* If OP0 is an AND and we don't have an AND in MODE either,
11500 make a new AND in the proper mode. */
11501 if (GET_CODE (op0) == AND
11502 && !have_insn_for (AND, mode))
11503 op0 = simplify_gen_binary (AND, tmode,
11504 gen_lowpart (tmode,
11506 gen_lowpart (tmode,
11512 op0 = simplify_gen_unary (ZERO_EXTEND, tmode, op0, mode);
11513 op1 = simplify_gen_unary (ZERO_EXTEND, tmode, op1, mode);
11517 op0 = simplify_gen_unary (SIGN_EXTEND, tmode, op0, mode);
11518 op1 = simplify_gen_unary (SIGN_EXTEND, tmode, op1, mode);
11525 #ifdef CANONICALIZE_COMPARISON
11526 /* If this machine only supports a subset of valid comparisons, see if we
11527 can convert an unsupported one into a supported one. */
11528 CANONICALIZE_COMPARISON (code, op0, op1);
11537 /* Utility function for record_value_for_reg. Count number of
11542 enum rtx_code code = GET_CODE (x);
11546 if (GET_RTX_CLASS (code) == '2'
11547 || GET_RTX_CLASS (code) == 'c')
11549 rtx x0 = XEXP (x, 0);
11550 rtx x1 = XEXP (x, 1);
11553 return 1 + 2 * count_rtxs (x0);
11555 if ((GET_RTX_CLASS (GET_CODE (x1)) == '2'
11556 || GET_RTX_CLASS (GET_CODE (x1)) == 'c')
11557 && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1)))
11558 return 2 + 2 * count_rtxs (x0)
11559 + count_rtxs (x == XEXP (x1, 0)
11560 ? XEXP (x1, 1) : XEXP (x1, 0));
11562 if ((GET_RTX_CLASS (GET_CODE (x0)) == '2'
11563 || GET_RTX_CLASS (GET_CODE (x0)) == 'c')
11564 && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1)))
11565 return 2 + 2 * count_rtxs (x1)
11566 + count_rtxs (x == XEXP (x0, 0)
11567 ? XEXP (x0, 1) : XEXP (x0, 0));
11570 fmt = GET_RTX_FORMAT (code);
11571 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
11573 ret += count_rtxs (XEXP (x, i));
11574 else if (fmt[i] == 'E')
11575 for (j = 0; j < XVECLEN (x, i); j++)
11576 ret += count_rtxs (XVECEXP (x, i, j));
11581 /* Utility function for following routine. Called when X is part of a value
11582 being stored into last_set_value. Sets last_set_table_tick
11583 for each register mentioned. Similar to mention_regs in cse.c */
11586 update_table_tick (rtx x)
11588 enum rtx_code code = GET_CODE (x);
11589 const char *fmt = GET_RTX_FORMAT (code);
11594 unsigned int regno = REGNO (x);
11595 unsigned int endregno = END_REGNO (x);
11598 for (r = regno; r < endregno; r++)
11600 reg_stat_type *rsp = VEC_index (reg_stat_type, reg_stat, r);
11601 rsp->last_set_table_tick = label_tick;
11607 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
11610 /* Check for identical subexpressions. If x contains
11611 identical subexpression we only have to traverse one of
11613 if (i == 0 && ARITHMETIC_P (x))
11615 /* Note that at this point x1 has already been
11617 rtx x0 = XEXP (x, 0);
11618 rtx x1 = XEXP (x, 1);
11620 /* If x0 and x1 are identical then there is no need to
11625 /* If x0 is identical to a subexpression of x1 then while
11626 processing x1, x0 has already been processed. Thus we
11627 are done with x. */
11628 if (ARITHMETIC_P (x1)
11629 && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1)))
11632 /* If x1 is identical to a subexpression of x0 then we
11633 still have to process the rest of x0. */
11634 if (ARITHMETIC_P (x0)
11635 && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1)))
11637 update_table_tick (XEXP (x0, x1 == XEXP (x0, 0) ? 1 : 0));
11642 update_table_tick (XEXP (x, i));
11644 else if (fmt[i] == 'E')
11645 for (j = 0; j < XVECLEN (x, i); j++)
11646 update_table_tick (XVECEXP (x, i, j));
11649 /* Record that REG is set to VALUE in insn INSN. If VALUE is zero, we
11650 are saying that the register is clobbered and we no longer know its
11651 value. If INSN is zero, don't update reg_stat[].last_set; this is
11652 only permitted with VALUE also zero and is used to invalidate the
11656 record_value_for_reg (rtx reg, rtx insn, rtx value)
11658 unsigned int regno = REGNO (reg);
11659 unsigned int endregno = END_REGNO (reg);
11661 reg_stat_type *rsp;
11663 /* If VALUE contains REG and we have a previous value for REG, substitute
11664 the previous value. */
11665 if (value && insn && reg_overlap_mentioned_p (reg, value))
11669 /* Set things up so get_last_value is allowed to see anything set up to
11671 subst_low_luid = DF_INSN_LUID (insn);
11672 tem = get_last_value (reg);
11674 /* If TEM is simply a binary operation with two CLOBBERs as operands,
11675 it isn't going to be useful and will take a lot of time to process,
11676 so just use the CLOBBER. */
11680 if (ARITHMETIC_P (tem)
11681 && GET_CODE (XEXP (tem, 0)) == CLOBBER
11682 && GET_CODE (XEXP (tem, 1)) == CLOBBER)
11683 tem = XEXP (tem, 0);
11684 else if (count_occurrences (value, reg, 1) >= 2)
11686 /* If there are two or more occurrences of REG in VALUE,
11687 prevent the value from growing too much. */
11688 if (count_rtxs (tem) > MAX_LAST_VALUE_RTL)
11689 tem = gen_rtx_CLOBBER (GET_MODE (tem), const0_rtx);
11692 value = replace_rtx (copy_rtx (value), reg, tem);
11696 /* For each register modified, show we don't know its value, that
11697 we don't know about its bitwise content, that its value has been
11698 updated, and that we don't know the location of the death of the
11700 for (i = regno; i < endregno; i++)
11702 rsp = VEC_index (reg_stat_type, reg_stat, i);
11705 rsp->last_set = insn;
11707 rsp->last_set_value = 0;
11708 rsp->last_set_mode = VOIDmode;
11709 rsp->last_set_nonzero_bits = 0;
11710 rsp->last_set_sign_bit_copies = 0;
11711 rsp->last_death = 0;
11712 rsp->truncated_to_mode = VOIDmode;
11715 /* Mark registers that are being referenced in this value. */
11717 update_table_tick (value);
11719 /* Now update the status of each register being set.
11720 If someone is using this register in this block, set this register
11721 to invalid since we will get confused between the two lives in this
11722 basic block. This makes using this register always invalid. In cse, we
11723 scan the table to invalidate all entries using this register, but this
11724 is too much work for us. */
11726 for (i = regno; i < endregno; i++)
11728 rsp = VEC_index (reg_stat_type, reg_stat, i);
11729 rsp->last_set_label = label_tick;
11731 || (value && rsp->last_set_table_tick >= label_tick_ebb_start))
11732 rsp->last_set_invalid = 1;
11734 rsp->last_set_invalid = 0;
11737 /* The value being assigned might refer to X (like in "x++;"). In that
11738 case, we must replace it with (clobber (const_int 0)) to prevent
11740 rsp = VEC_index (reg_stat_type, reg_stat, regno);
11741 if (value && !get_last_value_validate (&value, insn, label_tick, 0))
11743 value = copy_rtx (value);
11744 if (!get_last_value_validate (&value, insn, label_tick, 1))
11748 /* For the main register being modified, update the value, the mode, the
11749 nonzero bits, and the number of sign bit copies. */
11751 rsp->last_set_value = value;
11755 enum machine_mode mode = GET_MODE (reg);
11756 subst_low_luid = DF_INSN_LUID (insn);
11757 rsp->last_set_mode = mode;
11758 if (GET_MODE_CLASS (mode) == MODE_INT
11759 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
11760 mode = nonzero_bits_mode;
11761 rsp->last_set_nonzero_bits = nonzero_bits (value, mode);
11762 rsp->last_set_sign_bit_copies
11763 = num_sign_bit_copies (value, GET_MODE (reg));
11767 /* Called via note_stores from record_dead_and_set_regs to handle one
11768 SET or CLOBBER in an insn. DATA is the instruction in which the
11769 set is occurring. */
11772 record_dead_and_set_regs_1 (rtx dest, const_rtx setter, void *data)
11774 rtx record_dead_insn = (rtx) data;
11776 if (GET_CODE (dest) == SUBREG)
11777 dest = SUBREG_REG (dest);
11779 if (!record_dead_insn)
11782 record_value_for_reg (dest, NULL_RTX, NULL_RTX);
11788 /* If we are setting the whole register, we know its value. Otherwise
11789 show that we don't know the value. We can handle SUBREG in
11791 if (GET_CODE (setter) == SET && dest == SET_DEST (setter))
11792 record_value_for_reg (dest, record_dead_insn, SET_SRC (setter));
11793 else if (GET_CODE (setter) == SET
11794 && GET_CODE (SET_DEST (setter)) == SUBREG
11795 && SUBREG_REG (SET_DEST (setter)) == dest
11796 && GET_MODE_BITSIZE (GET_MODE (dest)) <= BITS_PER_WORD
11797 && subreg_lowpart_p (SET_DEST (setter)))
11798 record_value_for_reg (dest, record_dead_insn,
11799 gen_lowpart (GET_MODE (dest),
11800 SET_SRC (setter)));
11802 record_value_for_reg (dest, record_dead_insn, NULL_RTX);
11804 else if (MEM_P (dest)
11805 /* Ignore pushes, they clobber nothing. */
11806 && ! push_operand (dest, GET_MODE (dest)))
11807 mem_last_set = DF_INSN_LUID (record_dead_insn);
11810 /* Update the records of when each REG was most recently set or killed
11811 for the things done by INSN. This is the last thing done in processing
11812 INSN in the combiner loop.
11814 We update reg_stat[], in particular fields last_set, last_set_value,
11815 last_set_mode, last_set_nonzero_bits, last_set_sign_bit_copies,
11816 last_death, and also the similar information mem_last_set (which insn
11817 most recently modified memory) and last_call_luid (which insn was the
11818 most recent subroutine call). */
11821 record_dead_and_set_regs (rtx insn)
11826 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
11828 if (REG_NOTE_KIND (link) == REG_DEAD
11829 && REG_P (XEXP (link, 0)))
11831 unsigned int regno = REGNO (XEXP (link, 0));
11832 unsigned int endregno = END_REGNO (XEXP (link, 0));
11834 for (i = regno; i < endregno; i++)
11836 reg_stat_type *rsp;
11838 rsp = VEC_index (reg_stat_type, reg_stat, i);
11839 rsp->last_death = insn;
11842 else if (REG_NOTE_KIND (link) == REG_INC)
11843 record_value_for_reg (XEXP (link, 0), insn, NULL_RTX);
11848 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
11849 if (TEST_HARD_REG_BIT (regs_invalidated_by_call, i))
11851 reg_stat_type *rsp;
11853 rsp = VEC_index (reg_stat_type, reg_stat, i);
11854 rsp->last_set_invalid = 1;
11855 rsp->last_set = insn;
11856 rsp->last_set_value = 0;
11857 rsp->last_set_mode = VOIDmode;
11858 rsp->last_set_nonzero_bits = 0;
11859 rsp->last_set_sign_bit_copies = 0;
11860 rsp->last_death = 0;
11861 rsp->truncated_to_mode = VOIDmode;
11864 last_call_luid = mem_last_set = DF_INSN_LUID (insn);
11866 /* We can't combine into a call pattern. Remember, though, that
11867 the return value register is set at this LUID. We could
11868 still replace a register with the return value from the
11869 wrong subroutine call! */
11870 note_stores (PATTERN (insn), record_dead_and_set_regs_1, NULL_RTX);
11873 note_stores (PATTERN (insn), record_dead_and_set_regs_1, insn);
11876 /* If a SUBREG has the promoted bit set, it is in fact a property of the
11877 register present in the SUBREG, so for each such SUBREG go back and
11878 adjust nonzero and sign bit information of the registers that are
11879 known to have some zero/sign bits set.
11881 This is needed because when combine blows the SUBREGs away, the
11882 information on zero/sign bits is lost and further combines can be
11883 missed because of that. */
11886 record_promoted_value (rtx insn, rtx subreg)
11889 unsigned int regno = REGNO (SUBREG_REG (subreg));
11890 enum machine_mode mode = GET_MODE (subreg);
11892 if (GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT)
11895 for (links = LOG_LINKS (insn); links;)
11897 reg_stat_type *rsp;
11899 insn = XEXP (links, 0);
11900 set = single_set (insn);
11902 if (! set || !REG_P (SET_DEST (set))
11903 || REGNO (SET_DEST (set)) != regno
11904 || GET_MODE (SET_DEST (set)) != GET_MODE (SUBREG_REG (subreg)))
11906 links = XEXP (links, 1);
11910 rsp = VEC_index (reg_stat_type, reg_stat, regno);
11911 if (rsp->last_set == insn)
11913 if (SUBREG_PROMOTED_UNSIGNED_P (subreg) > 0)
11914 rsp->last_set_nonzero_bits &= GET_MODE_MASK (mode);
11917 if (REG_P (SET_SRC (set)))
11919 regno = REGNO (SET_SRC (set));
11920 links = LOG_LINKS (insn);
11927 /* Check if X, a register, is known to contain a value already
11928 truncated to MODE. In this case we can use a subreg to refer to
11929 the truncated value even though in the generic case we would need
11930 an explicit truncation. */
11933 reg_truncated_to_mode (enum machine_mode mode, const_rtx x)
11935 reg_stat_type *rsp = VEC_index (reg_stat_type, reg_stat, REGNO (x));
11936 enum machine_mode truncated = rsp->truncated_to_mode;
11939 || rsp->truncation_label < label_tick_ebb_start)
11941 if (GET_MODE_SIZE (truncated) <= GET_MODE_SIZE (mode))
11943 if (TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode),
11944 GET_MODE_BITSIZE (truncated)))
11949 /* Callback for for_each_rtx. If *P is a hard reg or a subreg record the mode
11950 that the register is accessed in. For non-TRULY_NOOP_TRUNCATION targets we
11951 might be able to turn a truncate into a subreg using this information.
11952 Return -1 if traversing *P is complete or 0 otherwise. */
11955 record_truncated_value (rtx *p, void *data ATTRIBUTE_UNUSED)
11958 enum machine_mode truncated_mode;
11959 reg_stat_type *rsp;
11961 if (GET_CODE (x) == SUBREG && REG_P (SUBREG_REG (x)))
11963 enum machine_mode original_mode = GET_MODE (SUBREG_REG (x));
11964 truncated_mode = GET_MODE (x);
11966 if (GET_MODE_SIZE (original_mode) <= GET_MODE_SIZE (truncated_mode))
11969 if (TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (truncated_mode),
11970 GET_MODE_BITSIZE (original_mode)))
11973 x = SUBREG_REG (x);
11975 /* ??? For hard-regs we now record everything. We might be able to
11976 optimize this using last_set_mode. */
11977 else if (REG_P (x) && REGNO (x) < FIRST_PSEUDO_REGISTER)
11978 truncated_mode = GET_MODE (x);
11982 rsp = VEC_index (reg_stat_type, reg_stat, REGNO (x));
11983 if (rsp->truncated_to_mode == 0
11984 || rsp->truncation_label < label_tick_ebb_start
11985 || (GET_MODE_SIZE (truncated_mode)
11986 < GET_MODE_SIZE (rsp->truncated_to_mode)))
11988 rsp->truncated_to_mode = truncated_mode;
11989 rsp->truncation_label = label_tick;
11995 /* Callback for note_uses. Find hardregs and subregs of pseudos and
11996 the modes they are used in. This can help truning TRUNCATEs into
12000 record_truncated_values (rtx *x, void *data ATTRIBUTE_UNUSED)
12002 for_each_rtx (x, record_truncated_value, NULL);
12005 /* Scan X for promoted SUBREGs. For each one found,
12006 note what it implies to the registers used in it. */
12009 check_promoted_subreg (rtx insn, rtx x)
12011 if (GET_CODE (x) == SUBREG
12012 && SUBREG_PROMOTED_VAR_P (x)
12013 && REG_P (SUBREG_REG (x)))
12014 record_promoted_value (insn, x);
12017 const char *format = GET_RTX_FORMAT (GET_CODE (x));
12020 for (i = 0; i < GET_RTX_LENGTH (GET_CODE (x)); i++)
12024 check_promoted_subreg (insn, XEXP (x, i));
12028 if (XVEC (x, i) != 0)
12029 for (j = 0; j < XVECLEN (x, i); j++)
12030 check_promoted_subreg (insn, XVECEXP (x, i, j));
12036 /* Verify that all the registers and memory references mentioned in *LOC are
12037 still valid. *LOC was part of a value set in INSN when label_tick was
12038 equal to TICK. Return 0 if some are not. If REPLACE is nonzero, replace
12039 the invalid references with (clobber (const_int 0)) and return 1. This
12040 replacement is useful because we often can get useful information about
12041 the form of a value (e.g., if it was produced by a shift that always
12042 produces -1 or 0) even though we don't know exactly what registers it
12043 was produced from. */
12046 get_last_value_validate (rtx *loc, rtx insn, int tick, int replace)
12049 const char *fmt = GET_RTX_FORMAT (GET_CODE (x));
12050 int len = GET_RTX_LENGTH (GET_CODE (x));
12055 unsigned int regno = REGNO (x);
12056 unsigned int endregno = END_REGNO (x);
12059 for (j = regno; j < endregno; j++)
12061 reg_stat_type *rsp = VEC_index (reg_stat_type, reg_stat, j);
12062 if (rsp->last_set_invalid
12063 /* If this is a pseudo-register that was only set once and not
12064 live at the beginning of the function, it is always valid. */
12065 || (! (regno >= FIRST_PSEUDO_REGISTER
12066 && REG_N_SETS (regno) == 1
12067 && (!REGNO_REG_SET_P
12068 (DF_LR_IN (ENTRY_BLOCK_PTR->next_bb), regno)))
12069 && rsp->last_set_label > tick))
12072 *loc = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
12079 /* If this is a memory reference, make sure that there were no stores after
12080 it that might have clobbered the value. We don't have alias info, so we
12081 assume any store invalidates it. Moreover, we only have local UIDs, so
12082 we also assume that there were stores in the intervening basic blocks. */
12083 else if (MEM_P (x) && !MEM_READONLY_P (x)
12084 && (tick != label_tick || DF_INSN_LUID (insn) <= mem_last_set))
12087 *loc = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
12091 for (i = 0; i < len; i++)
12095 /* Check for identical subexpressions. If x contains
12096 identical subexpression we only have to traverse one of
12098 if (i == 1 && ARITHMETIC_P (x))
12100 /* Note that at this point x0 has already been checked
12101 and found valid. */
12102 rtx x0 = XEXP (x, 0);
12103 rtx x1 = XEXP (x, 1);
12105 /* If x0 and x1 are identical then x is also valid. */
12109 /* If x1 is identical to a subexpression of x0 then
12110 while checking x0, x1 has already been checked. Thus
12111 it is valid and so as x. */
12112 if (ARITHMETIC_P (x0)
12113 && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1)))
12116 /* If x0 is identical to a subexpression of x1 then x is
12117 valid iff the rest of x1 is valid. */
12118 if (ARITHMETIC_P (x1)
12119 && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1)))
12121 get_last_value_validate (&XEXP (x1,
12122 x0 == XEXP (x1, 0) ? 1 : 0),
12123 insn, tick, replace);
12126 if (get_last_value_validate (&XEXP (x, i), insn, tick,
12130 else if (fmt[i] == 'E')
12131 for (j = 0; j < XVECLEN (x, i); j++)
12132 if (get_last_value_validate (&XVECEXP (x, i, j),
12133 insn, tick, replace) == 0)
12137 /* If we haven't found a reason for it to be invalid, it is valid. */
12141 /* Get the last value assigned to X, if known. Some registers
12142 in the value may be replaced with (clobber (const_int 0)) if their value
12143 is known longer known reliably. */
12146 get_last_value (const_rtx x)
12148 unsigned int regno;
12150 reg_stat_type *rsp;
12152 /* If this is a non-paradoxical SUBREG, get the value of its operand and
12153 then convert it to the desired mode. If this is a paradoxical SUBREG,
12154 we cannot predict what values the "extra" bits might have. */
12155 if (GET_CODE (x) == SUBREG
12156 && subreg_lowpart_p (x)
12157 && (GET_MODE_SIZE (GET_MODE (x))
12158 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
12159 && (value = get_last_value (SUBREG_REG (x))) != 0)
12160 return gen_lowpart (GET_MODE (x), value);
12166 rsp = VEC_index (reg_stat_type, reg_stat, regno);
12167 value = rsp->last_set_value;
12169 /* If we don't have a value, or if it isn't for this basic block and
12170 it's either a hard register, set more than once, or it's a live
12171 at the beginning of the function, return 0.
12173 Because if it's not live at the beginning of the function then the reg
12174 is always set before being used (is never used without being set).
12175 And, if it's set only once, and it's always set before use, then all
12176 uses must have the same last value, even if it's not from this basic
12180 || (rsp->last_set_label < label_tick_ebb_start
12181 && (regno < FIRST_PSEUDO_REGISTER
12182 || REG_N_SETS (regno) != 1
12184 (DF_LR_IN (ENTRY_BLOCK_PTR->next_bb), regno))))
12187 /* If the value was set in a later insn than the ones we are processing,
12188 we can't use it even if the register was only set once. */
12189 if (rsp->last_set_label == label_tick
12190 && DF_INSN_LUID (rsp->last_set) >= subst_low_luid)
12193 /* If the value has all its registers valid, return it. */
12194 if (get_last_value_validate (&value, rsp->last_set, rsp->last_set_label, 0))
12197 /* Otherwise, make a copy and replace any invalid register with
12198 (clobber (const_int 0)). If that fails for some reason, return 0. */
12200 value = copy_rtx (value);
12201 if (get_last_value_validate (&value, rsp->last_set, rsp->last_set_label, 1))
12207 /* Return nonzero if expression X refers to a REG or to memory
12208 that is set in an instruction more recent than FROM_LUID. */
12211 use_crosses_set_p (const_rtx x, int from_luid)
12215 enum rtx_code code = GET_CODE (x);
12219 unsigned int regno = REGNO (x);
12220 unsigned endreg = END_REGNO (x);
12222 #ifdef PUSH_ROUNDING
12223 /* Don't allow uses of the stack pointer to be moved,
12224 because we don't know whether the move crosses a push insn. */
12225 if (regno == STACK_POINTER_REGNUM && PUSH_ARGS)
12228 for (; regno < endreg; regno++)
12230 reg_stat_type *rsp = VEC_index (reg_stat_type, reg_stat, regno);
12232 && rsp->last_set_label == label_tick
12233 && DF_INSN_LUID (rsp->last_set) > from_luid)
12239 if (code == MEM && mem_last_set > from_luid)
12242 fmt = GET_RTX_FORMAT (code);
12244 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
12249 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
12250 if (use_crosses_set_p (XVECEXP (x, i, j), from_luid))
12253 else if (fmt[i] == 'e'
12254 && use_crosses_set_p (XEXP (x, i), from_luid))
12260 /* Define three variables used for communication between the following
12263 static unsigned int reg_dead_regno, reg_dead_endregno;
12264 static int reg_dead_flag;
12266 /* Function called via note_stores from reg_dead_at_p.
12268 If DEST is within [reg_dead_regno, reg_dead_endregno), set
12269 reg_dead_flag to 1 if X is a CLOBBER and to -1 it is a SET. */
12272 reg_dead_at_p_1 (rtx dest, const_rtx x, void *data ATTRIBUTE_UNUSED)
12274 unsigned int regno, endregno;
12279 regno = REGNO (dest);
12280 endregno = END_REGNO (dest);
12281 if (reg_dead_endregno > regno && reg_dead_regno < endregno)
12282 reg_dead_flag = (GET_CODE (x) == CLOBBER) ? 1 : -1;
12285 /* Return nonzero if REG is known to be dead at INSN.
12287 We scan backwards from INSN. If we hit a REG_DEAD note or a CLOBBER
12288 referencing REG, it is dead. If we hit a SET referencing REG, it is
12289 live. Otherwise, see if it is live or dead at the start of the basic
12290 block we are in. Hard regs marked as being live in NEWPAT_USED_REGS
12291 must be assumed to be always live. */
12294 reg_dead_at_p (rtx reg, rtx insn)
12299 /* Set variables for reg_dead_at_p_1. */
12300 reg_dead_regno = REGNO (reg);
12301 reg_dead_endregno = END_REGNO (reg);
12305 /* Check that reg isn't mentioned in NEWPAT_USED_REGS. For fixed registers
12306 we allow the machine description to decide whether use-and-clobber
12307 patterns are OK. */
12308 if (reg_dead_regno < FIRST_PSEUDO_REGISTER)
12310 for (i = reg_dead_regno; i < reg_dead_endregno; i++)
12311 if (!fixed_regs[i] && TEST_HARD_REG_BIT (newpat_used_regs, i))
12315 /* Scan backwards until we find a REG_DEAD note, SET, CLOBBER, or
12316 beginning of basic block. */
12317 block = BLOCK_FOR_INSN (insn);
12322 note_stores (PATTERN (insn), reg_dead_at_p_1, NULL);
12324 return reg_dead_flag == 1 ? 1 : 0;
12326 if (find_regno_note (insn, REG_DEAD, reg_dead_regno))
12330 if (insn == BB_HEAD (block))
12333 insn = PREV_INSN (insn);
12336 /* Look at live-in sets for the basic block that we were in. */
12337 for (i = reg_dead_regno; i < reg_dead_endregno; i++)
12338 if (REGNO_REG_SET_P (df_get_live_in (block), i))
12344 /* Note hard registers in X that are used. */
12347 mark_used_regs_combine (rtx x)
12349 RTX_CODE code = GET_CODE (x);
12350 unsigned int regno;
12363 case ADDR_DIFF_VEC:
12366 /* CC0 must die in the insn after it is set, so we don't need to take
12367 special note of it here. */
12373 /* If we are clobbering a MEM, mark any hard registers inside the
12374 address as used. */
12375 if (MEM_P (XEXP (x, 0)))
12376 mark_used_regs_combine (XEXP (XEXP (x, 0), 0));
12381 /* A hard reg in a wide mode may really be multiple registers.
12382 If so, mark all of them just like the first. */
12383 if (regno < FIRST_PSEUDO_REGISTER)
12385 /* None of this applies to the stack, frame or arg pointers. */
12386 if (regno == STACK_POINTER_REGNUM
12387 #if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM
12388 || regno == HARD_FRAME_POINTER_REGNUM
12390 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
12391 || (regno == ARG_POINTER_REGNUM && fixed_regs[regno])
12393 || regno == FRAME_POINTER_REGNUM)
12396 add_to_hard_reg_set (&newpat_used_regs, GET_MODE (x), regno);
12402 /* If setting a MEM, or a SUBREG of a MEM, then note any hard regs in
12404 rtx testreg = SET_DEST (x);
12406 while (GET_CODE (testreg) == SUBREG
12407 || GET_CODE (testreg) == ZERO_EXTRACT
12408 || GET_CODE (testreg) == STRICT_LOW_PART)
12409 testreg = XEXP (testreg, 0);
12411 if (MEM_P (testreg))
12412 mark_used_regs_combine (XEXP (testreg, 0));
12414 mark_used_regs_combine (SET_SRC (x));
12422 /* Recursively scan the operands of this expression. */
12425 const char *fmt = GET_RTX_FORMAT (code);
12427 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
12430 mark_used_regs_combine (XEXP (x, i));
12431 else if (fmt[i] == 'E')
12435 for (j = 0; j < XVECLEN (x, i); j++)
12436 mark_used_regs_combine (XVECEXP (x, i, j));
12442 /* Remove register number REGNO from the dead registers list of INSN.
12444 Return the note used to record the death, if there was one. */
12447 remove_death (unsigned int regno, rtx insn)
12449 rtx note = find_regno_note (insn, REG_DEAD, regno);
12452 remove_note (insn, note);
12457 /* For each register (hardware or pseudo) used within expression X, if its
12458 death is in an instruction with luid between FROM_LUID (inclusive) and
12459 TO_INSN (exclusive), put a REG_DEAD note for that register in the
12460 list headed by PNOTES.
12462 That said, don't move registers killed by maybe_kill_insn.
12464 This is done when X is being merged by combination into TO_INSN. These
12465 notes will then be distributed as needed. */
12468 move_deaths (rtx x, rtx maybe_kill_insn, int from_luid, rtx to_insn,
12473 enum rtx_code code = GET_CODE (x);
12477 unsigned int regno = REGNO (x);
12478 rtx where_dead = VEC_index (reg_stat_type, reg_stat, regno)->last_death;
12480 /* Don't move the register if it gets killed in between from and to. */
12481 if (maybe_kill_insn && reg_set_p (x, maybe_kill_insn)
12482 && ! reg_referenced_p (x, maybe_kill_insn))
12486 && BLOCK_FOR_INSN (where_dead) == BLOCK_FOR_INSN (to_insn)
12487 && DF_INSN_LUID (where_dead) >= from_luid
12488 && DF_INSN_LUID (where_dead) < DF_INSN_LUID (to_insn))
12490 rtx note = remove_death (regno, where_dead);
12492 /* It is possible for the call above to return 0. This can occur
12493 when last_death points to I2 or I1 that we combined with.
12494 In that case make a new note.
12496 We must also check for the case where X is a hard register
12497 and NOTE is a death note for a range of hard registers
12498 including X. In that case, we must put REG_DEAD notes for
12499 the remaining registers in place of NOTE. */
12501 if (note != 0 && regno < FIRST_PSEUDO_REGISTER
12502 && (GET_MODE_SIZE (GET_MODE (XEXP (note, 0)))
12503 > GET_MODE_SIZE (GET_MODE (x))))
12505 unsigned int deadregno = REGNO (XEXP (note, 0));
12506 unsigned int deadend = END_HARD_REGNO (XEXP (note, 0));
12507 unsigned int ourend = END_HARD_REGNO (x);
12510 for (i = deadregno; i < deadend; i++)
12511 if (i < regno || i >= ourend)
12512 add_reg_note (where_dead, REG_DEAD, regno_reg_rtx[i]);
12515 /* If we didn't find any note, or if we found a REG_DEAD note that
12516 covers only part of the given reg, and we have a multi-reg hard
12517 register, then to be safe we must check for REG_DEAD notes
12518 for each register other than the first. They could have
12519 their own REG_DEAD notes lying around. */
12520 else if ((note == 0
12522 && (GET_MODE_SIZE (GET_MODE (XEXP (note, 0)))
12523 < GET_MODE_SIZE (GET_MODE (x)))))
12524 && regno < FIRST_PSEUDO_REGISTER
12525 && hard_regno_nregs[regno][GET_MODE (x)] > 1)
12527 unsigned int ourend = END_HARD_REGNO (x);
12528 unsigned int i, offset;
12532 offset = hard_regno_nregs[regno][GET_MODE (XEXP (note, 0))];
12536 for (i = regno + offset; i < ourend; i++)
12537 move_deaths (regno_reg_rtx[i],
12538 maybe_kill_insn, from_luid, to_insn, &oldnotes);
12541 if (note != 0 && GET_MODE (XEXP (note, 0)) == GET_MODE (x))
12543 XEXP (note, 1) = *pnotes;
12547 *pnotes = alloc_reg_note (REG_DEAD, x, *pnotes);
12553 else if (GET_CODE (x) == SET)
12555 rtx dest = SET_DEST (x);
12557 move_deaths (SET_SRC (x), maybe_kill_insn, from_luid, to_insn, pnotes);
12559 /* In the case of a ZERO_EXTRACT, a STRICT_LOW_PART, or a SUBREG
12560 that accesses one word of a multi-word item, some
12561 piece of everything register in the expression is used by
12562 this insn, so remove any old death. */
12563 /* ??? So why do we test for equality of the sizes? */
12565 if (GET_CODE (dest) == ZERO_EXTRACT
12566 || GET_CODE (dest) == STRICT_LOW_PART
12567 || (GET_CODE (dest) == SUBREG
12568 && (((GET_MODE_SIZE (GET_MODE (dest))
12569 + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
12570 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (dest)))
12571 + UNITS_PER_WORD - 1) / UNITS_PER_WORD))))
12573 move_deaths (dest, maybe_kill_insn, from_luid, to_insn, pnotes);
12577 /* If this is some other SUBREG, we know it replaces the entire
12578 value, so use that as the destination. */
12579 if (GET_CODE (dest) == SUBREG)
12580 dest = SUBREG_REG (dest);
12582 /* If this is a MEM, adjust deaths of anything used in the address.
12583 For a REG (the only other possibility), the entire value is
12584 being replaced so the old value is not used in this insn. */
12587 move_deaths (XEXP (dest, 0), maybe_kill_insn, from_luid,
12592 else if (GET_CODE (x) == CLOBBER)
12595 len = GET_RTX_LENGTH (code);
12596 fmt = GET_RTX_FORMAT (code);
12598 for (i = 0; i < len; i++)
12603 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
12604 move_deaths (XVECEXP (x, i, j), maybe_kill_insn, from_luid,
12607 else if (fmt[i] == 'e')
12608 move_deaths (XEXP (x, i), maybe_kill_insn, from_luid, to_insn, pnotes);
12612 /* Return 1 if X is the target of a bit-field assignment in BODY, the
12613 pattern of an insn. X must be a REG. */
12616 reg_bitfield_target_p (rtx x, rtx body)
12620 if (GET_CODE (body) == SET)
12622 rtx dest = SET_DEST (body);
12624 unsigned int regno, tregno, endregno, endtregno;
12626 if (GET_CODE (dest) == ZERO_EXTRACT)
12627 target = XEXP (dest, 0);
12628 else if (GET_CODE (dest) == STRICT_LOW_PART)
12629 target = SUBREG_REG (XEXP (dest, 0));
12633 if (GET_CODE (target) == SUBREG)
12634 target = SUBREG_REG (target);
12636 if (!REG_P (target))
12639 tregno = REGNO (target), regno = REGNO (x);
12640 if (tregno >= FIRST_PSEUDO_REGISTER || regno >= FIRST_PSEUDO_REGISTER)
12641 return target == x;
12643 endtregno = end_hard_regno (GET_MODE (target), tregno);
12644 endregno = end_hard_regno (GET_MODE (x), regno);
12646 return endregno > tregno && regno < endtregno;
12649 else if (GET_CODE (body) == PARALLEL)
12650 for (i = XVECLEN (body, 0) - 1; i >= 0; i--)
12651 if (reg_bitfield_target_p (x, XVECEXP (body, 0, i)))
12657 /* Return the next insn after INSN that is neither a NOTE nor a
12658 DEBUG_INSN. This routine does not look inside SEQUENCEs. */
12661 next_nonnote_nondebug_insn (rtx insn)
12665 insn = NEXT_INSN (insn);
12670 if (DEBUG_INSN_P (insn))
12680 /* Given a chain of REG_NOTES originally from FROM_INSN, try to place them
12681 as appropriate. I3 and I2 are the insns resulting from the combination
12682 insns including FROM (I2 may be zero).
12684 ELIM_I2 and ELIM_I1 are either zero or registers that we know will
12685 not need REG_DEAD notes because they are being substituted for. This
12686 saves searching in the most common cases.
12688 Each note in the list is either ignored or placed on some insns, depending
12689 on the type of note. */
12692 distribute_notes (rtx notes, rtx from_insn, rtx i3, rtx i2, rtx elim_i2,
12695 rtx note, next_note;
12698 for (note = notes; note; note = next_note)
12700 rtx place = 0, place2 = 0;
12702 next_note = XEXP (note, 1);
12703 switch (REG_NOTE_KIND (note))
12707 /* Doesn't matter much where we put this, as long as it's somewhere.
12708 It is preferable to keep these notes on branches, which is most
12709 likely to be i3. */
12713 case REG_VALUE_PROFILE:
12714 /* Just get rid of this note, as it is unused later anyway. */
12717 case REG_NON_LOCAL_GOTO:
12722 gcc_assert (i2 && JUMP_P (i2));
12727 case REG_EH_REGION:
12728 /* These notes must remain with the call or trapping instruction. */
12731 else if (i2 && CALL_P (i2))
12735 gcc_assert (cfun->can_throw_non_call_exceptions);
12736 if (may_trap_p (i3))
12738 else if (i2 && may_trap_p (i2))
12740 /* ??? Otherwise assume we've combined things such that we
12741 can now prove that the instructions can't trap. Drop the
12742 note in this case. */
12748 /* These notes must remain with the call. It should not be
12749 possible for both I2 and I3 to be a call. */
12754 gcc_assert (i2 && CALL_P (i2));
12760 /* Any clobbers for i3 may still exist, and so we must process
12761 REG_UNUSED notes from that insn.
12763 Any clobbers from i2 or i1 can only exist if they were added by
12764 recog_for_combine. In that case, recog_for_combine created the
12765 necessary REG_UNUSED notes. Trying to keep any original
12766 REG_UNUSED notes from these insns can cause incorrect output
12767 if it is for the same register as the original i3 dest.
12768 In that case, we will notice that the register is set in i3,
12769 and then add a REG_UNUSED note for the destination of i3, which
12770 is wrong. However, it is possible to have REG_UNUSED notes from
12771 i2 or i1 for register which were both used and clobbered, so
12772 we keep notes from i2 or i1 if they will turn into REG_DEAD
12775 /* If this register is set or clobbered in I3, put the note there
12776 unless there is one already. */
12777 if (reg_set_p (XEXP (note, 0), PATTERN (i3)))
12779 if (from_insn != i3)
12782 if (! (REG_P (XEXP (note, 0))
12783 ? find_regno_note (i3, REG_UNUSED, REGNO (XEXP (note, 0)))
12784 : find_reg_note (i3, REG_UNUSED, XEXP (note, 0))))
12787 /* Otherwise, if this register is used by I3, then this register
12788 now dies here, so we must put a REG_DEAD note here unless there
12790 else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3))
12791 && ! (REG_P (XEXP (note, 0))
12792 ? find_regno_note (i3, REG_DEAD,
12793 REGNO (XEXP (note, 0)))
12794 : find_reg_note (i3, REG_DEAD, XEXP (note, 0))))
12796 PUT_REG_NOTE_KIND (note, REG_DEAD);
12804 /* These notes say something about results of an insn. We can
12805 only support them if they used to be on I3 in which case they
12806 remain on I3. Otherwise they are ignored.
12808 If the note refers to an expression that is not a constant, we
12809 must also ignore the note since we cannot tell whether the
12810 equivalence is still true. It might be possible to do
12811 slightly better than this (we only have a problem if I2DEST
12812 or I1DEST is present in the expression), but it doesn't
12813 seem worth the trouble. */
12815 if (from_insn == i3
12816 && (XEXP (note, 0) == 0 || CONSTANT_P (XEXP (note, 0))))
12821 /* These notes say something about how a register is used. They must
12822 be present on any use of the register in I2 or I3. */
12823 if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3)))
12826 if (i2 && reg_mentioned_p (XEXP (note, 0), PATTERN (i2)))
12835 case REG_LABEL_TARGET:
12836 case REG_LABEL_OPERAND:
12837 /* This can show up in several ways -- either directly in the
12838 pattern, or hidden off in the constant pool with (or without?)
12839 a REG_EQUAL note. */
12840 /* ??? Ignore the without-reg_equal-note problem for now. */
12841 if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3))
12842 || ((tem = find_reg_note (i3, REG_EQUAL, NULL_RTX))
12843 && GET_CODE (XEXP (tem, 0)) == LABEL_REF
12844 && XEXP (XEXP (tem, 0), 0) == XEXP (note, 0)))
12848 && (reg_mentioned_p (XEXP (note, 0), PATTERN (i2))
12849 || ((tem = find_reg_note (i2, REG_EQUAL, NULL_RTX))
12850 && GET_CODE (XEXP (tem, 0)) == LABEL_REF
12851 && XEXP (XEXP (tem, 0), 0) == XEXP (note, 0))))
12859 /* For REG_LABEL_TARGET on a JUMP_P, we prefer to put the note
12860 as a JUMP_LABEL or decrement LABEL_NUSES if it's already
12862 if (place && JUMP_P (place)
12863 && REG_NOTE_KIND (note) == REG_LABEL_TARGET
12864 && (JUMP_LABEL (place) == NULL
12865 || JUMP_LABEL (place) == XEXP (note, 0)))
12867 rtx label = JUMP_LABEL (place);
12870 JUMP_LABEL (place) = XEXP (note, 0);
12871 else if (LABEL_P (label))
12872 LABEL_NUSES (label)--;
12875 if (place2 && JUMP_P (place2)
12876 && REG_NOTE_KIND (note) == REG_LABEL_TARGET
12877 && (JUMP_LABEL (place2) == NULL
12878 || JUMP_LABEL (place2) == XEXP (note, 0)))
12880 rtx label = JUMP_LABEL (place2);
12883 JUMP_LABEL (place2) = XEXP (note, 0);
12884 else if (LABEL_P (label))
12885 LABEL_NUSES (label)--;
12891 /* This note says something about the value of a register prior
12892 to the execution of an insn. It is too much trouble to see
12893 if the note is still correct in all situations. It is better
12894 to simply delete it. */
12898 /* If we replaced the right hand side of FROM_INSN with a
12899 REG_EQUAL note, the original use of the dying register
12900 will not have been combined into I3 and I2. In such cases,
12901 FROM_INSN is guaranteed to be the first of the combined
12902 instructions, so we simply need to search back before
12903 FROM_INSN for the previous use or set of this register,
12904 then alter the notes there appropriately.
12906 If the register is used as an input in I3, it dies there.
12907 Similarly for I2, if it is nonzero and adjacent to I3.
12909 If the register is not used as an input in either I3 or I2
12910 and it is not one of the registers we were supposed to eliminate,
12911 there are two possibilities. We might have a non-adjacent I2
12912 or we might have somehow eliminated an additional register
12913 from a computation. For example, we might have had A & B where
12914 we discover that B will always be zero. In this case we will
12915 eliminate the reference to A.
12917 In both cases, we must search to see if we can find a previous
12918 use of A and put the death note there. */
12921 && from_insn == i2mod
12922 && !reg_overlap_mentioned_p (XEXP (note, 0), i2mod_new_rhs))
12927 && CALL_P (from_insn)
12928 && find_reg_fusage (from_insn, USE, XEXP (note, 0)))
12930 else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3)))
12932 else if (i2 != 0 && next_nonnote_nondebug_insn (i2) == i3
12933 && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
12935 else if ((rtx_equal_p (XEXP (note, 0), elim_i2)
12937 && reg_overlap_mentioned_p (XEXP (note, 0),
12939 || rtx_equal_p (XEXP (note, 0), elim_i1))
12946 basic_block bb = this_basic_block;
12948 for (tem = PREV_INSN (tem); place == 0; tem = PREV_INSN (tem))
12950 if (!NONDEBUG_INSN_P (tem))
12952 if (tem == BB_HEAD (bb))
12957 /* If the register is being set at TEM, see if that is all
12958 TEM is doing. If so, delete TEM. Otherwise, make this
12959 into a REG_UNUSED note instead. Don't delete sets to
12960 global register vars. */
12961 if ((REGNO (XEXP (note, 0)) >= FIRST_PSEUDO_REGISTER
12962 || !global_regs[REGNO (XEXP (note, 0))])
12963 && reg_set_p (XEXP (note, 0), PATTERN (tem)))
12965 rtx set = single_set (tem);
12966 rtx inner_dest = 0;
12968 rtx cc0_setter = NULL_RTX;
12972 for (inner_dest = SET_DEST (set);
12973 (GET_CODE (inner_dest) == STRICT_LOW_PART
12974 || GET_CODE (inner_dest) == SUBREG
12975 || GET_CODE (inner_dest) == ZERO_EXTRACT);
12976 inner_dest = XEXP (inner_dest, 0))
12979 /* Verify that it was the set, and not a clobber that
12980 modified the register.
12982 CC0 targets must be careful to maintain setter/user
12983 pairs. If we cannot delete the setter due to side
12984 effects, mark the user with an UNUSED note instead
12987 if (set != 0 && ! side_effects_p (SET_SRC (set))
12988 && rtx_equal_p (XEXP (note, 0), inner_dest)
12990 && (! reg_mentioned_p (cc0_rtx, SET_SRC (set))
12991 || ((cc0_setter = prev_cc0_setter (tem)) != NULL
12992 && sets_cc0_p (PATTERN (cc0_setter)) > 0))
12996 /* Move the notes and links of TEM elsewhere.
12997 This might delete other dead insns recursively.
12998 First set the pattern to something that won't use
13000 rtx old_notes = REG_NOTES (tem);
13002 PATTERN (tem) = pc_rtx;
13003 REG_NOTES (tem) = NULL;
13005 distribute_notes (old_notes, tem, tem, NULL_RTX,
13006 NULL_RTX, NULL_RTX);
13007 distribute_links (LOG_LINKS (tem));
13009 SET_INSN_DELETED (tem);
13014 /* Delete the setter too. */
13017 PATTERN (cc0_setter) = pc_rtx;
13018 old_notes = REG_NOTES (cc0_setter);
13019 REG_NOTES (cc0_setter) = NULL;
13021 distribute_notes (old_notes, cc0_setter,
13022 cc0_setter, NULL_RTX,
13023 NULL_RTX, NULL_RTX);
13024 distribute_links (LOG_LINKS (cc0_setter));
13026 SET_INSN_DELETED (cc0_setter);
13027 if (cc0_setter == i2)
13034 PUT_REG_NOTE_KIND (note, REG_UNUSED);
13036 /* If there isn't already a REG_UNUSED note, put one
13037 here. Do not place a REG_DEAD note, even if
13038 the register is also used here; that would not
13039 match the algorithm used in lifetime analysis
13040 and can cause the consistency check in the
13041 scheduler to fail. */
13042 if (! find_regno_note (tem, REG_UNUSED,
13043 REGNO (XEXP (note, 0))))
13048 else if (reg_referenced_p (XEXP (note, 0), PATTERN (tem))
13050 && find_reg_fusage (tem, USE, XEXP (note, 0))))
13054 /* If we are doing a 3->2 combination, and we have a
13055 register which formerly died in i3 and was not used
13056 by i2, which now no longer dies in i3 and is used in
13057 i2 but does not die in i2, and place is between i2
13058 and i3, then we may need to move a link from place to
13060 if (i2 && DF_INSN_LUID (place) > DF_INSN_LUID (i2)
13062 && DF_INSN_LUID (from_insn) > DF_INSN_LUID (i2)
13063 && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
13065 rtx links = LOG_LINKS (place);
13066 LOG_LINKS (place) = 0;
13067 distribute_links (links);
13072 if (tem == BB_HEAD (bb))
13078 /* If the register is set or already dead at PLACE, we needn't do
13079 anything with this note if it is still a REG_DEAD note.
13080 We check here if it is set at all, not if is it totally replaced,
13081 which is what `dead_or_set_p' checks, so also check for it being
13084 if (place && REG_NOTE_KIND (note) == REG_DEAD)
13086 unsigned int regno = REGNO (XEXP (note, 0));
13087 reg_stat_type *rsp = VEC_index (reg_stat_type, reg_stat, regno);
13089 if (dead_or_set_p (place, XEXP (note, 0))
13090 || reg_bitfield_target_p (XEXP (note, 0), PATTERN (place)))
13092 /* Unless the register previously died in PLACE, clear
13093 last_death. [I no longer understand why this is
13095 if (rsp->last_death != place)
13096 rsp->last_death = 0;
13100 rsp->last_death = place;
13102 /* If this is a death note for a hard reg that is occupying
13103 multiple registers, ensure that we are still using all
13104 parts of the object. If we find a piece of the object
13105 that is unused, we must arrange for an appropriate REG_DEAD
13106 note to be added for it. However, we can't just emit a USE
13107 and tag the note to it, since the register might actually
13108 be dead; so we recourse, and the recursive call then finds
13109 the previous insn that used this register. */
13111 if (place && regno < FIRST_PSEUDO_REGISTER
13112 && hard_regno_nregs[regno][GET_MODE (XEXP (note, 0))] > 1)
13114 unsigned int endregno = END_HARD_REGNO (XEXP (note, 0));
13118 for (i = regno; i < endregno; i++)
13119 if ((! refers_to_regno_p (i, i + 1, PATTERN (place), 0)
13120 && ! find_regno_fusage (place, USE, i))
13121 || dead_or_set_regno_p (place, i))
13126 /* Put only REG_DEAD notes for pieces that are
13127 not already dead or set. */
13129 for (i = regno; i < endregno;
13130 i += hard_regno_nregs[i][reg_raw_mode[i]])
13132 rtx piece = regno_reg_rtx[i];
13133 basic_block bb = this_basic_block;
13135 if (! dead_or_set_p (place, piece)
13136 && ! reg_bitfield_target_p (piece,
13139 rtx new_note = alloc_reg_note (REG_DEAD, piece,
13142 distribute_notes (new_note, place, place,
13143 NULL_RTX, NULL_RTX, NULL_RTX);
13145 else if (! refers_to_regno_p (i, i + 1,
13146 PATTERN (place), 0)
13147 && ! find_regno_fusage (place, USE, i))
13148 for (tem = PREV_INSN (place); ;
13149 tem = PREV_INSN (tem))
13151 if (!NONDEBUG_INSN_P (tem))
13153 if (tem == BB_HEAD (bb))
13157 if (dead_or_set_p (tem, piece)
13158 || reg_bitfield_target_p (piece,
13161 add_reg_note (tem, REG_UNUSED, piece);
13175 /* Any other notes should not be present at this point in the
13177 gcc_unreachable ();
13182 XEXP (note, 1) = REG_NOTES (place);
13183 REG_NOTES (place) = note;
13187 add_reg_note (place2, REG_NOTE_KIND (note), XEXP (note, 0));
13191 /* Similarly to above, distribute the LOG_LINKS that used to be present on
13192 I3, I2, and I1 to new locations. This is also called to add a link
13193 pointing at I3 when I3's destination is changed. */
13196 distribute_links (rtx links)
13198 rtx link, next_link;
13200 for (link = links; link; link = next_link)
13206 next_link = XEXP (link, 1);
13208 /* If the insn that this link points to is a NOTE or isn't a single
13209 set, ignore it. In the latter case, it isn't clear what we
13210 can do other than ignore the link, since we can't tell which
13211 register it was for. Such links wouldn't be used by combine
13214 It is not possible for the destination of the target of the link to
13215 have been changed by combine. The only potential of this is if we
13216 replace I3, I2, and I1 by I3 and I2. But in that case the
13217 destination of I2 also remains unchanged. */
13219 if (NOTE_P (XEXP (link, 0))
13220 || (set = single_set (XEXP (link, 0))) == 0)
13223 reg = SET_DEST (set);
13224 while (GET_CODE (reg) == SUBREG || GET_CODE (reg) == ZERO_EXTRACT
13225 || GET_CODE (reg) == STRICT_LOW_PART)
13226 reg = XEXP (reg, 0);
13228 /* A LOG_LINK is defined as being placed on the first insn that uses
13229 a register and points to the insn that sets the register. Start
13230 searching at the next insn after the target of the link and stop
13231 when we reach a set of the register or the end of the basic block.
13233 Note that this correctly handles the link that used to point from
13234 I3 to I2. Also note that not much searching is typically done here
13235 since most links don't point very far away. */
13237 for (insn = NEXT_INSN (XEXP (link, 0));
13238 (insn && (this_basic_block->next_bb == EXIT_BLOCK_PTR
13239 || BB_HEAD (this_basic_block->next_bb) != insn));
13240 insn = NEXT_INSN (insn))
13241 if (DEBUG_INSN_P (insn))
13243 else if (INSN_P (insn) && reg_overlap_mentioned_p (reg, PATTERN (insn)))
13245 if (reg_referenced_p (reg, PATTERN (insn)))
13249 else if (CALL_P (insn)
13250 && find_reg_fusage (insn, USE, reg))
13255 else if (INSN_P (insn) && reg_set_p (reg, insn))
13258 /* If we found a place to put the link, place it there unless there
13259 is already a link to the same insn as LINK at that point. */
13265 for (link2 = LOG_LINKS (place); link2; link2 = XEXP (link2, 1))
13266 if (XEXP (link2, 0) == XEXP (link, 0))
13271 XEXP (link, 1) = LOG_LINKS (place);
13272 LOG_LINKS (place) = link;
13274 /* Set added_links_insn to the earliest insn we added a
13276 if (added_links_insn == 0
13277 || DF_INSN_LUID (added_links_insn) > DF_INSN_LUID (place))
13278 added_links_insn = place;
13284 /* Subroutine of unmentioned_reg_p and callback from for_each_rtx.
13285 Check whether the expression pointer to by LOC is a register or
13286 memory, and if so return 1 if it isn't mentioned in the rtx EXPR.
13287 Otherwise return zero. */
13290 unmentioned_reg_p_1 (rtx *loc, void *expr)
13295 && (REG_P (x) || MEM_P (x))
13296 && ! reg_mentioned_p (x, (rtx) expr))
13301 /* Check for any register or memory mentioned in EQUIV that is not
13302 mentioned in EXPR. This is used to restrict EQUIV to "specializations"
13303 of EXPR where some registers may have been replaced by constants. */
13306 unmentioned_reg_p (rtx equiv, rtx expr)
13308 return for_each_rtx (&equiv, unmentioned_reg_p_1, expr);
13312 dump_combine_stats (FILE *file)
13316 ";; Combiner statistics: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n\n",
13317 combine_attempts, combine_merges, combine_extras, combine_successes);
13321 dump_combine_total_stats (FILE *file)
13325 "\n;; Combiner totals: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n",
13326 total_attempts, total_merges, total_extras, total_successes);
13330 gate_handle_combine (void)
13332 return (optimize > 0);
13335 /* Try combining insns through substitution. */
13336 static unsigned int
13337 rest_of_handle_combine (void)
13339 int rebuild_jump_labels_after_combine;
13341 df_set_flags (DF_LR_RUN_DCE + DF_DEFER_INSN_RESCAN);
13342 df_note_add_problem ();
13345 regstat_init_n_sets_and_refs ();
13347 rebuild_jump_labels_after_combine
13348 = combine_instructions (get_insns (), max_reg_num ());
13350 /* Combining insns may have turned an indirect jump into a
13351 direct jump. Rebuild the JUMP_LABEL fields of jumping
13353 if (rebuild_jump_labels_after_combine)
13355 timevar_push (TV_JUMP);
13356 rebuild_jump_labels (get_insns ());
13358 timevar_pop (TV_JUMP);
13361 regstat_free_n_sets_and_refs ();
13365 struct rtl_opt_pass pass_combine =
13369 "combine", /* name */
13370 gate_handle_combine, /* gate */
13371 rest_of_handle_combine, /* execute */
13374 0, /* static_pass_number */
13375 TV_COMBINE, /* tv_id */
13376 PROP_cfglayout, /* properties_required */
13377 0, /* properties_provided */
13378 0, /* properties_destroyed */
13379 0, /* todo_flags_start */
13381 TODO_df_finish | TODO_verify_rtl_sharing |
13382 TODO_ggc_collect, /* todo_flags_finish */
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