1 /* Optimize by combining instructions for GNU compiler.
2 Copyright (C) 1987, 1988, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009
4 Free Software Foundation, Inc.
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify it under
9 the terms of the GNU General Public License as published by the Free
10 Software Foundation; either version 3, or (at your option) any later
13 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
14 WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
22 /* This module is essentially the "combiner" phase of the U. of Arizona
23 Portable Optimizer, but redone to work on our list-structured
24 representation for RTL instead of their string representation.
26 The LOG_LINKS of each insn identify the most recent assignment
27 to each REG used in the insn. It is a list of previous insns,
28 each of which contains a SET for a REG that is used in this insn
29 and not used or set in between. LOG_LINKs never cross basic blocks.
30 They were set up by the preceding pass (lifetime analysis).
32 We try to combine each pair of insns joined by a logical link.
33 We also try to combine triples of insns A, B and C when
34 C has a link back to B and B has a link back to A.
36 LOG_LINKS does not have links for use of the CC0. They don't
37 need to, because the insn that sets the CC0 is always immediately
38 before the insn that tests it. So we always regard a branch
39 insn as having a logical link to the preceding insn. The same is true
40 for an insn explicitly using CC0.
42 We check (with use_crosses_set_p) to avoid combining in such a way
43 as to move a computation to a place where its value would be different.
45 Combination is done by mathematically substituting the previous
46 insn(s) values for the regs they set into the expressions in
47 the later insns that refer to these regs. If the result is a valid insn
48 for our target machine, according to the machine description,
49 we install it, delete the earlier insns, and update the data flow
50 information (LOG_LINKS and REG_NOTES) for what we did.
52 There are a few exceptions where the dataflow information isn't
53 completely updated (however this is only a local issue since it is
54 regenerated before the next pass that uses it):
56 - reg_live_length is not updated
57 - reg_n_refs is not adjusted in the rare case when a register is
58 no longer required in a computation
59 - there are extremely rare cases (see distribute_notes) when a
61 - a LOG_LINKS entry that refers to an insn with multiple SETs may be
62 removed because there is no way to know which register it was
65 To simplify substitution, we combine only when the earlier insn(s)
66 consist of only a single assignment. To simplify updating afterward,
67 we never combine when a subroutine call appears in the middle.
69 Since we do not represent assignments to CC0 explicitly except when that
70 is all an insn does, there is no LOG_LINKS entry in an insn that uses
71 the condition code for the insn that set the condition code.
72 Fortunately, these two insns must be consecutive.
73 Therefore, every JUMP_INSN is taken to have an implicit logical link
74 to the preceding insn. This is not quite right, since non-jumps can
75 also use the condition code; but in practice such insns would not
80 #include "coretypes.h"
87 #include "hard-reg-set.h"
88 #include "basic-block.h"
89 #include "insn-config.h"
91 /* Include expr.h after insn-config.h so we get HAVE_conditional_move. */
93 #include "insn-attr.h"
99 #include "insn-codes.h"
100 #include "rtlhooks-def.h"
101 /* Include output.h for dump_file. */
105 #include "tree-pass.h"
109 /* Number of attempts to combine instructions in this function. */
111 static int combine_attempts;
113 /* Number of attempts that got as far as substitution in this function. */
115 static int combine_merges;
117 /* Number of instructions combined with added SETs in this function. */
119 static int combine_extras;
121 /* Number of instructions combined in this function. */
123 static int combine_successes;
125 /* Totals over entire compilation. */
127 static int total_attempts, total_merges, total_extras, total_successes;
129 /* combine_instructions may try to replace the right hand side of the
130 second instruction with the value of an associated REG_EQUAL note
131 before throwing it at try_combine. That is problematic when there
132 is a REG_DEAD note for a register used in the old right hand side
133 and can cause distribute_notes to do wrong things. This is the
134 second instruction if it has been so modified, null otherwise. */
138 /* When I2MOD is nonnull, this is a copy of the old right hand side. */
140 static rtx i2mod_old_rhs;
142 /* When I2MOD is nonnull, this is a copy of the new right hand side. */
144 static rtx i2mod_new_rhs;
146 typedef struct reg_stat_struct {
147 /* Record last point of death of (hard or pseudo) register n. */
150 /* Record last point of modification of (hard or pseudo) register n. */
153 /* The next group of fields allows the recording of the last value assigned
154 to (hard or pseudo) register n. We use this information to see if an
155 operation being processed is redundant given a prior operation performed
156 on the register. For example, an `and' with a constant is redundant if
157 all the zero bits are already known to be turned off.
159 We use an approach similar to that used by cse, but change it in the
162 (1) We do not want to reinitialize at each label.
163 (2) It is useful, but not critical, to know the actual value assigned
164 to a register. Often just its form is helpful.
166 Therefore, we maintain the following fields:
168 last_set_value the last value assigned
169 last_set_label records the value of label_tick when the
170 register was assigned
171 last_set_table_tick records the value of label_tick when a
172 value using the register is assigned
173 last_set_invalid set to nonzero when it is not valid
174 to use the value of this register in some
177 To understand the usage of these tables, it is important to understand
178 the distinction between the value in last_set_value being valid and
179 the register being validly contained in some other expression in the
182 (The next two parameters are out of date).
184 reg_stat[i].last_set_value is valid if it is nonzero, and either
185 reg_n_sets[i] is 1 or reg_stat[i].last_set_label == label_tick.
187 Register I may validly appear in any expression returned for the value
188 of another register if reg_n_sets[i] is 1. It may also appear in the
189 value for register J if reg_stat[j].last_set_invalid is zero, or
190 reg_stat[i].last_set_label < reg_stat[j].last_set_label.
192 If an expression is found in the table containing a register which may
193 not validly appear in an expression, the register is replaced by
194 something that won't match, (clobber (const_int 0)). */
196 /* Record last value assigned to (hard or pseudo) register n. */
200 /* Record the value of label_tick when an expression involving register n
201 is placed in last_set_value. */
203 int last_set_table_tick;
205 /* Record the value of label_tick when the value for register n is placed in
210 /* These fields are maintained in parallel with last_set_value and are
211 used to store the mode in which the register was last set, the bits
212 that were known to be zero when it was last set, and the number of
213 sign bits copies it was known to have when it was last set. */
215 unsigned HOST_WIDE_INT last_set_nonzero_bits;
216 char last_set_sign_bit_copies;
217 ENUM_BITFIELD(machine_mode) last_set_mode : 8;
219 /* Set nonzero if references to register n in expressions should not be
220 used. last_set_invalid is set nonzero when this register is being
221 assigned to and last_set_table_tick == label_tick. */
223 char last_set_invalid;
225 /* Some registers that are set more than once and used in more than one
226 basic block are nevertheless always set in similar ways. For example,
227 a QImode register may be loaded from memory in two places on a machine
228 where byte loads zero extend.
230 We record in the following fields if a register has some leading bits
231 that are always equal to the sign bit, and what we know about the
232 nonzero bits of a register, specifically which bits are known to be
235 If an entry is zero, it means that we don't know anything special. */
237 unsigned char sign_bit_copies;
239 unsigned HOST_WIDE_INT nonzero_bits;
241 /* Record the value of the label_tick when the last truncation
242 happened. The field truncated_to_mode is only valid if
243 truncation_label == label_tick. */
245 int truncation_label;
247 /* Record the last truncation seen for this register. If truncation
248 is not a nop to this mode we might be able to save an explicit
249 truncation if we know that value already contains a truncated
252 ENUM_BITFIELD(machine_mode) truncated_to_mode : 8;
255 DEF_VEC_O(reg_stat_type);
256 DEF_VEC_ALLOC_O(reg_stat_type,heap);
258 static VEC(reg_stat_type,heap) *reg_stat;
260 /* Record the luid of the last insn that invalidated memory
261 (anything that writes memory, and subroutine calls, but not pushes). */
263 static int mem_last_set;
265 /* Record the luid of the last CALL_INSN
266 so we can tell whether a potential combination crosses any calls. */
268 static int last_call_luid;
270 /* When `subst' is called, this is the insn that is being modified
271 (by combining in a previous insn). The PATTERN of this insn
272 is still the old pattern partially modified and it should not be
273 looked at, but this may be used to examine the successors of the insn
274 to judge whether a simplification is valid. */
276 static rtx subst_insn;
278 /* This is the lowest LUID that `subst' is currently dealing with.
279 get_last_value will not return a value if the register was set at or
280 after this LUID. If not for this mechanism, we could get confused if
281 I2 or I1 in try_combine were an insn that used the old value of a register
282 to obtain a new value. In that case, we might erroneously get the
283 new value of the register when we wanted the old one. */
285 static int subst_low_luid;
287 /* This contains any hard registers that are used in newpat; reg_dead_at_p
288 must consider all these registers to be always live. */
290 static HARD_REG_SET newpat_used_regs;
292 /* This is an insn to which a LOG_LINKS entry has been added. If this
293 insn is the earlier than I2 or I3, combine should rescan starting at
296 static rtx added_links_insn;
298 /* Basic block in which we are performing combines. */
299 static basic_block this_basic_block;
300 static bool optimize_this_for_speed_p;
303 /* Length of the currently allocated uid_insn_cost array. */
305 static int max_uid_known;
307 /* The following array records the insn_rtx_cost for every insn
308 in the instruction stream. */
310 static int *uid_insn_cost;
312 /* The following array records the LOG_LINKS for every insn in the
313 instruction stream as an INSN_LIST rtx. */
315 static rtx *uid_log_links;
317 #define INSN_COST(INSN) (uid_insn_cost[INSN_UID (INSN)])
318 #define LOG_LINKS(INSN) (uid_log_links[INSN_UID (INSN)])
320 /* Incremented for each basic block. */
322 static int label_tick;
324 /* Reset to label_tick for each extended basic block in scanning order. */
326 static int label_tick_ebb_start;
328 /* Mode used to compute significance in reg_stat[].nonzero_bits. It is the
329 largest integer mode that can fit in HOST_BITS_PER_WIDE_INT. */
331 static enum machine_mode nonzero_bits_mode;
333 /* Nonzero when reg_stat[].nonzero_bits and reg_stat[].sign_bit_copies can
334 be safely used. It is zero while computing them and after combine has
335 completed. This former test prevents propagating values based on
336 previously set values, which can be incorrect if a variable is modified
339 static int nonzero_sign_valid;
342 /* Record one modification to rtl structure
343 to be undone by storing old_contents into *where. */
345 enum undo_kind { UNDO_RTX, UNDO_INT, UNDO_MODE };
351 union { rtx r; int i; enum machine_mode m; } old_contents;
352 union { rtx *r; int *i; } where;
355 /* Record a bunch of changes to be undone, up to MAX_UNDO of them.
356 num_undo says how many are currently recorded.
358 other_insn is nonzero if we have modified some other insn in the process
359 of working on subst_insn. It must be verified too. */
368 static struct undobuf undobuf;
370 /* Number of times the pseudo being substituted for
371 was found and replaced. */
373 static int n_occurrences;
375 static rtx reg_nonzero_bits_for_combine (const_rtx, enum machine_mode, const_rtx,
377 unsigned HOST_WIDE_INT,
378 unsigned HOST_WIDE_INT *);
379 static rtx reg_num_sign_bit_copies_for_combine (const_rtx, enum machine_mode, const_rtx,
381 unsigned int, unsigned int *);
382 static void do_SUBST (rtx *, rtx);
383 static void do_SUBST_INT (int *, int);
384 static void init_reg_last (void);
385 static void setup_incoming_promotions (rtx);
386 static void set_nonzero_bits_and_sign_copies (rtx, const_rtx, void *);
387 static int cant_combine_insn_p (rtx);
388 static int can_combine_p (rtx, rtx, rtx, rtx, rtx *, rtx *);
389 static int combinable_i3pat (rtx, rtx *, rtx, rtx, int, rtx *);
390 static int contains_muldiv (rtx);
391 static rtx try_combine (rtx, rtx, rtx, int *);
392 static void undo_all (void);
393 static void undo_commit (void);
394 static rtx *find_split_point (rtx *, rtx);
395 static rtx subst (rtx, rtx, rtx, int, int);
396 static rtx combine_simplify_rtx (rtx, enum machine_mode, int);
397 static rtx simplify_if_then_else (rtx);
398 static rtx simplify_set (rtx);
399 static rtx simplify_logical (rtx);
400 static rtx expand_compound_operation (rtx);
401 static const_rtx expand_field_assignment (const_rtx);
402 static rtx make_extraction (enum machine_mode, rtx, HOST_WIDE_INT,
403 rtx, unsigned HOST_WIDE_INT, int, int, int);
404 static rtx extract_left_shift (rtx, int);
405 static rtx make_compound_operation (rtx, enum rtx_code);
406 static int get_pos_from_mask (unsigned HOST_WIDE_INT,
407 unsigned HOST_WIDE_INT *);
408 static rtx canon_reg_for_combine (rtx, rtx);
409 static rtx force_to_mode (rtx, enum machine_mode,
410 unsigned HOST_WIDE_INT, int);
411 static rtx if_then_else_cond (rtx, rtx *, rtx *);
412 static rtx known_cond (rtx, enum rtx_code, rtx, rtx);
413 static int rtx_equal_for_field_assignment_p (rtx, rtx);
414 static rtx make_field_assignment (rtx);
415 static rtx apply_distributive_law (rtx);
416 static rtx distribute_and_simplify_rtx (rtx, int);
417 static rtx simplify_and_const_int_1 (enum machine_mode, rtx,
418 unsigned HOST_WIDE_INT);
419 static rtx simplify_and_const_int (rtx, enum machine_mode, rtx,
420 unsigned HOST_WIDE_INT);
421 static int merge_outer_ops (enum rtx_code *, HOST_WIDE_INT *, enum rtx_code,
422 HOST_WIDE_INT, enum machine_mode, int *);
423 static rtx simplify_shift_const_1 (enum rtx_code, enum machine_mode, rtx, int);
424 static rtx simplify_shift_const (rtx, enum rtx_code, enum machine_mode, rtx,
426 static int recog_for_combine (rtx *, rtx, rtx *);
427 static rtx gen_lowpart_for_combine (enum machine_mode, rtx);
428 static enum rtx_code simplify_comparison (enum rtx_code, rtx *, rtx *);
429 static void update_table_tick (rtx);
430 static void record_value_for_reg (rtx, rtx, rtx);
431 static void check_promoted_subreg (rtx, rtx);
432 static void record_dead_and_set_regs_1 (rtx, const_rtx, void *);
433 static void record_dead_and_set_regs (rtx);
434 static int get_last_value_validate (rtx *, rtx, int, int);
435 static rtx get_last_value (const_rtx);
436 static int use_crosses_set_p (const_rtx, int);
437 static void reg_dead_at_p_1 (rtx, const_rtx, void *);
438 static int reg_dead_at_p (rtx, rtx);
439 static void move_deaths (rtx, rtx, int, rtx, rtx *);
440 static int reg_bitfield_target_p (rtx, rtx);
441 static void distribute_notes (rtx, rtx, rtx, rtx, rtx, rtx);
442 static void distribute_links (rtx);
443 static void mark_used_regs_combine (rtx);
444 static void record_promoted_value (rtx, rtx);
445 static int unmentioned_reg_p_1 (rtx *, void *);
446 static bool unmentioned_reg_p (rtx, rtx);
447 static int record_truncated_value (rtx *, void *);
448 static void record_truncated_values (rtx *, void *);
449 static bool reg_truncated_to_mode (enum machine_mode, const_rtx);
450 static rtx gen_lowpart_or_truncate (enum machine_mode, rtx);
453 /* It is not safe to use ordinary gen_lowpart in combine.
454 See comments in gen_lowpart_for_combine. */
455 #undef RTL_HOOKS_GEN_LOWPART
456 #define RTL_HOOKS_GEN_LOWPART gen_lowpart_for_combine
458 /* Our implementation of gen_lowpart never emits a new pseudo. */
459 #undef RTL_HOOKS_GEN_LOWPART_NO_EMIT
460 #define RTL_HOOKS_GEN_LOWPART_NO_EMIT gen_lowpart_for_combine
462 #undef RTL_HOOKS_REG_NONZERO_REG_BITS
463 #define RTL_HOOKS_REG_NONZERO_REG_BITS reg_nonzero_bits_for_combine
465 #undef RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES
466 #define RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES reg_num_sign_bit_copies_for_combine
468 #undef RTL_HOOKS_REG_TRUNCATED_TO_MODE
469 #define RTL_HOOKS_REG_TRUNCATED_TO_MODE reg_truncated_to_mode
471 static const struct rtl_hooks combine_rtl_hooks = RTL_HOOKS_INITIALIZER;
474 /* Try to split PATTERN found in INSN. This returns NULL_RTX if
475 PATTERN can not be split. Otherwise, it returns an insn sequence.
476 This is a wrapper around split_insns which ensures that the
477 reg_stat vector is made larger if the splitter creates a new
481 combine_split_insns (rtx pattern, rtx insn)
486 ret = split_insns (pattern, insn);
487 nregs = max_reg_num ();
488 if (nregs > VEC_length (reg_stat_type, reg_stat))
489 VEC_safe_grow_cleared (reg_stat_type, heap, reg_stat, nregs);
493 /* This is used by find_single_use to locate an rtx in LOC that
494 contains exactly one use of DEST, which is typically either a REG
495 or CC0. It returns a pointer to the innermost rtx expression
496 containing DEST. Appearances of DEST that are being used to
497 totally replace it are not counted. */
500 find_single_use_1 (rtx dest, rtx *loc)
503 enum rtx_code code = GET_CODE (x);
521 /* If the destination is anything other than CC0, PC, a REG or a SUBREG
522 of a REG that occupies all of the REG, the insn uses DEST if
523 it is mentioned in the destination or the source. Otherwise, we
524 need just check the source. */
525 if (GET_CODE (SET_DEST (x)) != CC0
526 && GET_CODE (SET_DEST (x)) != PC
527 && !REG_P (SET_DEST (x))
528 && ! (GET_CODE (SET_DEST (x)) == SUBREG
529 && REG_P (SUBREG_REG (SET_DEST (x)))
530 && (((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x))))
531 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
532 == ((GET_MODE_SIZE (GET_MODE (SET_DEST (x)))
533 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD))))
536 return find_single_use_1 (dest, &SET_SRC (x));
540 return find_single_use_1 (dest, &XEXP (x, 0));
546 /* If it wasn't one of the common cases above, check each expression and
547 vector of this code. Look for a unique usage of DEST. */
549 fmt = GET_RTX_FORMAT (code);
550 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
554 if (dest == XEXP (x, i)
555 || (REG_P (dest) && REG_P (XEXP (x, i))
556 && REGNO (dest) == REGNO (XEXP (x, i))))
559 this_result = find_single_use_1 (dest, &XEXP (x, i));
562 result = this_result;
563 else if (this_result)
564 /* Duplicate usage. */
567 else if (fmt[i] == 'E')
571 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
573 if (XVECEXP (x, i, j) == dest
575 && REG_P (XVECEXP (x, i, j))
576 && REGNO (XVECEXP (x, i, j)) == REGNO (dest)))
579 this_result = find_single_use_1 (dest, &XVECEXP (x, i, j));
582 result = this_result;
583 else if (this_result)
593 /* See if DEST, produced in INSN, is used only a single time in the
594 sequel. If so, return a pointer to the innermost rtx expression in which
597 If PLOC is nonzero, *PLOC is set to the insn containing the single use.
599 If DEST is cc0_rtx, we look only at the next insn. In that case, we don't
600 care about REG_DEAD notes or LOG_LINKS.
602 Otherwise, we find the single use by finding an insn that has a
603 LOG_LINKS pointing at INSN and has a REG_DEAD note for DEST. If DEST is
604 only referenced once in that insn, we know that it must be the first
605 and last insn referencing DEST. */
608 find_single_use (rtx dest, rtx insn, rtx *ploc)
618 next = NEXT_INSN (insn);
620 || (!NONJUMP_INSN_P (next) && !JUMP_P (next)))
623 result = find_single_use_1 (dest, &PATTERN (next));
633 bb = BLOCK_FOR_INSN (insn);
634 for (next = NEXT_INSN (insn);
635 next && BLOCK_FOR_INSN (next) == bb;
636 next = NEXT_INSN (next))
637 if (INSN_P (next) && dead_or_set_p (next, dest))
639 for (link = LOG_LINKS (next); link; link = XEXP (link, 1))
640 if (XEXP (link, 0) == insn)
645 result = find_single_use_1 (dest, &PATTERN (next));
655 /* Substitute NEWVAL, an rtx expression, into INTO, a place in some
656 insn. The substitution can be undone by undo_all. If INTO is already
657 set to NEWVAL, do not record this change. Because computing NEWVAL might
658 also call SUBST, we have to compute it before we put anything into
662 do_SUBST (rtx *into, rtx newval)
667 if (oldval == newval)
670 /* We'd like to catch as many invalid transformations here as
671 possible. Unfortunately, there are way too many mode changes
672 that are perfectly valid, so we'd waste too much effort for
673 little gain doing the checks here. Focus on catching invalid
674 transformations involving integer constants. */
675 if (GET_MODE_CLASS (GET_MODE (oldval)) == MODE_INT
676 && CONST_INT_P (newval))
678 /* Sanity check that we're replacing oldval with a CONST_INT
679 that is a valid sign-extension for the original mode. */
680 gcc_assert (INTVAL (newval)
681 == trunc_int_for_mode (INTVAL (newval), GET_MODE (oldval)));
683 /* Replacing the operand of a SUBREG or a ZERO_EXTEND with a
684 CONST_INT is not valid, because after the replacement, the
685 original mode would be gone. Unfortunately, we can't tell
686 when do_SUBST is called to replace the operand thereof, so we
687 perform this test on oldval instead, checking whether an
688 invalid replacement took place before we got here. */
689 gcc_assert (!(GET_CODE (oldval) == SUBREG
690 && CONST_INT_P (SUBREG_REG (oldval))));
691 gcc_assert (!(GET_CODE (oldval) == ZERO_EXTEND
692 && CONST_INT_P (XEXP (oldval, 0))));
696 buf = undobuf.frees, undobuf.frees = buf->next;
698 buf = XNEW (struct undo);
700 buf->kind = UNDO_RTX;
702 buf->old_contents.r = oldval;
705 buf->next = undobuf.undos, undobuf.undos = buf;
708 #define SUBST(INTO, NEWVAL) do_SUBST(&(INTO), (NEWVAL))
710 /* Similar to SUBST, but NEWVAL is an int expression. Note that substitution
711 for the value of a HOST_WIDE_INT value (including CONST_INT) is
715 do_SUBST_INT (int *into, int newval)
720 if (oldval == newval)
724 buf = undobuf.frees, undobuf.frees = buf->next;
726 buf = XNEW (struct undo);
728 buf->kind = UNDO_INT;
730 buf->old_contents.i = oldval;
733 buf->next = undobuf.undos, undobuf.undos = buf;
736 #define SUBST_INT(INTO, NEWVAL) do_SUBST_INT(&(INTO), (NEWVAL))
738 /* Similar to SUBST, but just substitute the mode. This is used when
739 changing the mode of a pseudo-register, so that any other
740 references to the entry in the regno_reg_rtx array will change as
744 do_SUBST_MODE (rtx *into, enum machine_mode newval)
747 enum machine_mode oldval = GET_MODE (*into);
749 if (oldval == newval)
753 buf = undobuf.frees, undobuf.frees = buf->next;
755 buf = XNEW (struct undo);
757 buf->kind = UNDO_MODE;
759 buf->old_contents.m = oldval;
760 adjust_reg_mode (*into, newval);
762 buf->next = undobuf.undos, undobuf.undos = buf;
765 #define SUBST_MODE(INTO, NEWVAL) do_SUBST_MODE(&(INTO), (NEWVAL))
767 /* Subroutine of try_combine. Determine whether the combine replacement
768 patterns NEWPAT, NEWI2PAT and NEWOTHERPAT are cheaper according to
769 insn_rtx_cost that the original instruction sequence I1, I2, I3 and
770 undobuf.other_insn. Note that I1 and/or NEWI2PAT may be NULL_RTX.
771 NEWOTHERPAT and undobuf.other_insn may also both be NULL_RTX. This
772 function returns false, if the costs of all instructions can be
773 estimated, and the replacements are more expensive than the original
777 combine_validate_cost (rtx i1, rtx i2, rtx i3, rtx newpat, rtx newi2pat,
780 int i1_cost, i2_cost, i3_cost;
781 int new_i2_cost, new_i3_cost;
782 int old_cost, new_cost;
784 /* Lookup the original insn_rtx_costs. */
785 i2_cost = INSN_COST (i2);
786 i3_cost = INSN_COST (i3);
790 i1_cost = INSN_COST (i1);
791 old_cost = (i1_cost > 0 && i2_cost > 0 && i3_cost > 0)
792 ? i1_cost + i2_cost + i3_cost : 0;
796 old_cost = (i2_cost > 0 && i3_cost > 0) ? i2_cost + i3_cost : 0;
800 /* Calculate the replacement insn_rtx_costs. */
801 new_i3_cost = insn_rtx_cost (newpat, optimize_this_for_speed_p);
804 new_i2_cost = insn_rtx_cost (newi2pat, optimize_this_for_speed_p);
805 new_cost = (new_i2_cost > 0 && new_i3_cost > 0)
806 ? new_i2_cost + new_i3_cost : 0;
810 new_cost = new_i3_cost;
814 if (undobuf.other_insn)
816 int old_other_cost, new_other_cost;
818 old_other_cost = INSN_COST (undobuf.other_insn);
819 new_other_cost = insn_rtx_cost (newotherpat, optimize_this_for_speed_p);
820 if (old_other_cost > 0 && new_other_cost > 0)
822 old_cost += old_other_cost;
823 new_cost += new_other_cost;
829 /* Disallow this recombination if both new_cost and old_cost are
830 greater than zero, and new_cost is greater than old cost. */
832 && new_cost > old_cost)
839 "rejecting combination of insns %d, %d and %d\n",
840 INSN_UID (i1), INSN_UID (i2), INSN_UID (i3));
841 fprintf (dump_file, "original costs %d + %d + %d = %d\n",
842 i1_cost, i2_cost, i3_cost, old_cost);
847 "rejecting combination of insns %d and %d\n",
848 INSN_UID (i2), INSN_UID (i3));
849 fprintf (dump_file, "original costs %d + %d = %d\n",
850 i2_cost, i3_cost, old_cost);
855 fprintf (dump_file, "replacement costs %d + %d = %d\n",
856 new_i2_cost, new_i3_cost, new_cost);
859 fprintf (dump_file, "replacement cost %d\n", new_cost);
865 /* Update the uid_insn_cost array with the replacement costs. */
866 INSN_COST (i2) = new_i2_cost;
867 INSN_COST (i3) = new_i3_cost;
875 /* Delete any insns that copy a register to itself. */
878 delete_noop_moves (void)
885 for (insn = BB_HEAD (bb); insn != NEXT_INSN (BB_END (bb)); insn = next)
887 next = NEXT_INSN (insn);
888 if (INSN_P (insn) && noop_move_p (insn))
891 fprintf (dump_file, "deleting noop move %d\n", INSN_UID (insn));
893 delete_insn_and_edges (insn);
900 /* Fill in log links field for all insns. */
903 create_log_links (void)
907 df_ref *def_vec, *use_vec;
909 next_use = XCNEWVEC (rtx, max_reg_num ());
911 /* Pass through each block from the end, recording the uses of each
912 register and establishing log links when def is encountered.
913 Note that we do not clear next_use array in order to save time,
914 so we have to test whether the use is in the same basic block as def.
916 There are a few cases below when we do not consider the definition or
917 usage -- these are taken from original flow.c did. Don't ask me why it is
918 done this way; I don't know and if it works, I don't want to know. */
922 FOR_BB_INSNS_REVERSE (bb, insn)
924 if (!NONDEBUG_INSN_P (insn))
927 /* Log links are created only once. */
928 gcc_assert (!LOG_LINKS (insn));
930 for (def_vec = DF_INSN_DEFS (insn); *def_vec; def_vec++)
932 df_ref def = *def_vec;
933 int regno = DF_REF_REGNO (def);
936 if (!next_use[regno])
939 /* Do not consider if it is pre/post modification in MEM. */
940 if (DF_REF_FLAGS (def) & DF_REF_PRE_POST_MODIFY)
943 /* Do not make the log link for frame pointer. */
944 if ((regno == FRAME_POINTER_REGNUM
945 && (! reload_completed || frame_pointer_needed))
946 #if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM
947 || (regno == HARD_FRAME_POINTER_REGNUM
948 && (! reload_completed || frame_pointer_needed))
950 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
951 || (regno == ARG_POINTER_REGNUM && fixed_regs[regno])
956 use_insn = next_use[regno];
957 if (BLOCK_FOR_INSN (use_insn) == bb)
961 We don't build a LOG_LINK for hard registers contained
962 in ASM_OPERANDs. If these registers get replaced,
963 we might wind up changing the semantics of the insn,
964 even if reload can make what appear to be valid
965 assignments later. */
966 if (regno >= FIRST_PSEUDO_REGISTER
967 || asm_noperands (PATTERN (use_insn)) < 0)
969 /* Don't add duplicate links between instructions. */
971 for (links = LOG_LINKS (use_insn); links;
972 links = XEXP (links, 1))
973 if (insn == XEXP (links, 0))
977 LOG_LINKS (use_insn) =
978 alloc_INSN_LIST (insn, LOG_LINKS (use_insn));
981 next_use[regno] = NULL_RTX;
984 for (use_vec = DF_INSN_USES (insn); *use_vec; use_vec++)
986 df_ref use = *use_vec;
987 int regno = DF_REF_REGNO (use);
989 /* Do not consider the usage of the stack pointer
991 if (DF_REF_FLAGS (use) & DF_REF_CALL_STACK_USAGE)
994 next_use[regno] = insn;
1002 /* Clear LOG_LINKS fields of insns. */
1005 clear_log_links (void)
1009 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
1011 free_INSN_LIST_list (&LOG_LINKS (insn));
1014 /* Main entry point for combiner. F is the first insn of the function.
1015 NREGS is the first unused pseudo-reg number.
1017 Return nonzero if the combiner has turned an indirect jump
1018 instruction into a direct jump. */
1020 combine_instructions (rtx f, unsigned int nregs)
1026 rtx links, nextlinks;
1028 basic_block last_bb;
1030 int new_direct_jump_p = 0;
1032 for (first = f; first && !INSN_P (first); )
1033 first = NEXT_INSN (first);
1037 combine_attempts = 0;
1040 combine_successes = 0;
1042 rtl_hooks = combine_rtl_hooks;
1044 VEC_safe_grow_cleared (reg_stat_type, heap, reg_stat, nregs);
1046 init_recog_no_volatile ();
1048 /* Allocate array for insn info. */
1049 max_uid_known = get_max_uid ();
1050 uid_log_links = XCNEWVEC (rtx, max_uid_known + 1);
1051 uid_insn_cost = XCNEWVEC (int, max_uid_known + 1);
1053 nonzero_bits_mode = mode_for_size (HOST_BITS_PER_WIDE_INT, MODE_INT, 0);
1055 /* Don't use reg_stat[].nonzero_bits when computing it. This can cause
1056 problems when, for example, we have j <<= 1 in a loop. */
1058 nonzero_sign_valid = 0;
1059 label_tick = label_tick_ebb_start = 1;
1061 /* Scan all SETs and see if we can deduce anything about what
1062 bits are known to be zero for some registers and how many copies
1063 of the sign bit are known to exist for those registers.
1065 Also set any known values so that we can use it while searching
1066 for what bits are known to be set. */
1068 setup_incoming_promotions (first);
1069 /* Allow the entry block and the first block to fall into the same EBB.
1070 Conceptually the incoming promotions are assigned to the entry block. */
1071 last_bb = ENTRY_BLOCK_PTR;
1073 create_log_links ();
1074 FOR_EACH_BB (this_basic_block)
1076 optimize_this_for_speed_p = optimize_bb_for_speed_p (this_basic_block);
1081 if (!single_pred_p (this_basic_block)
1082 || single_pred (this_basic_block) != last_bb)
1083 label_tick_ebb_start = label_tick;
1084 last_bb = this_basic_block;
1086 FOR_BB_INSNS (this_basic_block, insn)
1087 if (INSN_P (insn) && BLOCK_FOR_INSN (insn))
1089 subst_low_luid = DF_INSN_LUID (insn);
1092 note_stores (PATTERN (insn), set_nonzero_bits_and_sign_copies,
1094 record_dead_and_set_regs (insn);
1097 for (links = REG_NOTES (insn); links; links = XEXP (links, 1))
1098 if (REG_NOTE_KIND (links) == REG_INC)
1099 set_nonzero_bits_and_sign_copies (XEXP (links, 0), NULL_RTX,
1103 /* Record the current insn_rtx_cost of this instruction. */
1104 if (NONJUMP_INSN_P (insn))
1105 INSN_COST (insn) = insn_rtx_cost (PATTERN (insn),
1106 optimize_this_for_speed_p);
1108 fprintf(dump_file, "insn_cost %d: %d\n",
1109 INSN_UID (insn), INSN_COST (insn));
1113 nonzero_sign_valid = 1;
1115 /* Now scan all the insns in forward order. */
1116 label_tick = label_tick_ebb_start = 1;
1118 setup_incoming_promotions (first);
1119 last_bb = ENTRY_BLOCK_PTR;
1121 FOR_EACH_BB (this_basic_block)
1123 optimize_this_for_speed_p = optimize_bb_for_speed_p (this_basic_block);
1128 if (!single_pred_p (this_basic_block)
1129 || single_pred (this_basic_block) != last_bb)
1130 label_tick_ebb_start = label_tick;
1131 last_bb = this_basic_block;
1133 rtl_profile_for_bb (this_basic_block);
1134 for (insn = BB_HEAD (this_basic_block);
1135 insn != NEXT_INSN (BB_END (this_basic_block));
1136 insn = next ? next : NEXT_INSN (insn))
1139 if (NONDEBUG_INSN_P (insn))
1141 /* See if we know about function return values before this
1142 insn based upon SUBREG flags. */
1143 check_promoted_subreg (insn, PATTERN (insn));
1145 /* See if we can find hardregs and subreg of pseudos in
1146 narrower modes. This could help turning TRUNCATEs
1148 note_uses (&PATTERN (insn), record_truncated_values, NULL);
1150 /* Try this insn with each insn it links back to. */
1152 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
1153 if ((next = try_combine (insn, XEXP (links, 0),
1154 NULL_RTX, &new_direct_jump_p)) != 0)
1157 /* Try each sequence of three linked insns ending with this one. */
1159 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
1161 rtx link = XEXP (links, 0);
1163 /* If the linked insn has been replaced by a note, then there
1164 is no point in pursuing this chain any further. */
1168 for (nextlinks = LOG_LINKS (link);
1170 nextlinks = XEXP (nextlinks, 1))
1171 if ((next = try_combine (insn, link,
1172 XEXP (nextlinks, 0),
1173 &new_direct_jump_p)) != 0)
1178 /* Try to combine a jump insn that uses CC0
1179 with a preceding insn that sets CC0, and maybe with its
1180 logical predecessor as well.
1181 This is how we make decrement-and-branch insns.
1182 We need this special code because data flow connections
1183 via CC0 do not get entered in LOG_LINKS. */
1186 && (prev = prev_nonnote_insn (insn)) != 0
1187 && NONJUMP_INSN_P (prev)
1188 && sets_cc0_p (PATTERN (prev)))
1190 if ((next = try_combine (insn, prev,
1191 NULL_RTX, &new_direct_jump_p)) != 0)
1194 for (nextlinks = LOG_LINKS (prev); nextlinks;
1195 nextlinks = XEXP (nextlinks, 1))
1196 if ((next = try_combine (insn, prev,
1197 XEXP (nextlinks, 0),
1198 &new_direct_jump_p)) != 0)
1202 /* Do the same for an insn that explicitly references CC0. */
1203 if (NONJUMP_INSN_P (insn)
1204 && (prev = prev_nonnote_insn (insn)) != 0
1205 && NONJUMP_INSN_P (prev)
1206 && sets_cc0_p (PATTERN (prev))
1207 && GET_CODE (PATTERN (insn)) == SET
1208 && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (insn))))
1210 if ((next = try_combine (insn, prev,
1211 NULL_RTX, &new_direct_jump_p)) != 0)
1214 for (nextlinks = LOG_LINKS (prev); nextlinks;
1215 nextlinks = XEXP (nextlinks, 1))
1216 if ((next = try_combine (insn, prev,
1217 XEXP (nextlinks, 0),
1218 &new_direct_jump_p)) != 0)
1222 /* Finally, see if any of the insns that this insn links to
1223 explicitly references CC0. If so, try this insn, that insn,
1224 and its predecessor if it sets CC0. */
1225 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
1226 if (NONJUMP_INSN_P (XEXP (links, 0))
1227 && GET_CODE (PATTERN (XEXP (links, 0))) == SET
1228 && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (XEXP (links, 0))))
1229 && (prev = prev_nonnote_insn (XEXP (links, 0))) != 0
1230 && NONJUMP_INSN_P (prev)
1231 && sets_cc0_p (PATTERN (prev))
1232 && (next = try_combine (insn, XEXP (links, 0),
1233 prev, &new_direct_jump_p)) != 0)
1237 /* Try combining an insn with two different insns whose results it
1239 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
1240 for (nextlinks = XEXP (links, 1); nextlinks;
1241 nextlinks = XEXP (nextlinks, 1))
1242 if ((next = try_combine (insn, XEXP (links, 0),
1243 XEXP (nextlinks, 0),
1244 &new_direct_jump_p)) != 0)
1247 /* Try this insn with each REG_EQUAL note it links back to. */
1248 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
1251 rtx temp = XEXP (links, 0);
1252 if ((set = single_set (temp)) != 0
1253 && (note = find_reg_equal_equiv_note (temp)) != 0
1254 && (note = XEXP (note, 0), GET_CODE (note)) != EXPR_LIST
1255 /* Avoid using a register that may already been marked
1256 dead by an earlier instruction. */
1257 && ! unmentioned_reg_p (note, SET_SRC (set))
1258 && (GET_MODE (note) == VOIDmode
1259 ? SCALAR_INT_MODE_P (GET_MODE (SET_DEST (set)))
1260 : GET_MODE (SET_DEST (set)) == GET_MODE (note)))
1262 /* Temporarily replace the set's source with the
1263 contents of the REG_EQUAL note. The insn will
1264 be deleted or recognized by try_combine. */
1265 rtx orig = SET_SRC (set);
1266 SET_SRC (set) = note;
1268 i2mod_old_rhs = copy_rtx (orig);
1269 i2mod_new_rhs = copy_rtx (note);
1270 next = try_combine (insn, i2mod, NULL_RTX,
1271 &new_direct_jump_p);
1275 SET_SRC (set) = orig;
1280 record_dead_and_set_regs (insn);
1288 default_rtl_profile ();
1291 new_direct_jump_p |= purge_all_dead_edges ();
1292 delete_noop_moves ();
1295 free (uid_log_links);
1296 free (uid_insn_cost);
1297 VEC_free (reg_stat_type, heap, reg_stat);
1300 struct undo *undo, *next;
1301 for (undo = undobuf.frees; undo; undo = next)
1309 total_attempts += combine_attempts;
1310 total_merges += combine_merges;
1311 total_extras += combine_extras;
1312 total_successes += combine_successes;
1314 nonzero_sign_valid = 0;
1315 rtl_hooks = general_rtl_hooks;
1317 /* Make recognizer allow volatile MEMs again. */
1320 return new_direct_jump_p;
1323 /* Wipe the last_xxx fields of reg_stat in preparation for another pass. */
1326 init_reg_last (void)
1331 for (i = 0; VEC_iterate (reg_stat_type, reg_stat, i, p); ++i)
1332 memset (p, 0, offsetof (reg_stat_type, sign_bit_copies));
1335 /* Set up any promoted values for incoming argument registers. */
1338 setup_incoming_promotions (rtx first)
1341 bool strictly_local = false;
1343 for (arg = DECL_ARGUMENTS (current_function_decl); arg;
1344 arg = TREE_CHAIN (arg))
1346 rtx x, reg = DECL_INCOMING_RTL (arg);
1348 enum machine_mode mode1, mode2, mode3, mode4;
1350 /* Only continue if the incoming argument is in a register. */
1354 /* Determine, if possible, whether all call sites of the current
1355 function lie within the current compilation unit. (This does
1356 take into account the exporting of a function via taking its
1357 address, and so forth.) */
1358 strictly_local = cgraph_local_info (current_function_decl)->local;
1360 /* The mode and signedness of the argument before any promotions happen
1361 (equal to the mode of the pseudo holding it at that stage). */
1362 mode1 = TYPE_MODE (TREE_TYPE (arg));
1363 uns1 = TYPE_UNSIGNED (TREE_TYPE (arg));
1365 /* The mode and signedness of the argument after any source language and
1366 TARGET_PROMOTE_PROTOTYPES-driven promotions. */
1367 mode2 = TYPE_MODE (DECL_ARG_TYPE (arg));
1368 uns3 = TYPE_UNSIGNED (DECL_ARG_TYPE (arg));
1370 /* The mode and signedness of the argument as it is actually passed,
1371 after any TARGET_PROMOTE_FUNCTION_ARGS-driven ABI promotions. */
1372 mode3 = promote_function_mode (DECL_ARG_TYPE (arg), mode2, &uns3,
1373 TREE_TYPE (cfun->decl), 0);
1375 /* The mode of the register in which the argument is being passed. */
1376 mode4 = GET_MODE (reg);
1378 /* Eliminate sign extensions in the callee when:
1379 (a) A mode promotion has occurred; */
1382 /* (b) The mode of the register is the same as the mode of
1383 the argument as it is passed; */
1386 /* (c) There's no language level extension; */
1389 /* (c.1) All callers are from the current compilation unit. If that's
1390 the case we don't have to rely on an ABI, we only have to know
1391 what we're generating right now, and we know that we will do the
1392 mode1 to mode2 promotion with the given sign. */
1393 else if (!strictly_local)
1395 /* (c.2) The combination of the two promotions is useful. This is
1396 true when the signs match, or if the first promotion is unsigned.
1397 In the later case, (sign_extend (zero_extend x)) is the same as
1398 (zero_extend (zero_extend x)), so make sure to force UNS3 true. */
1404 /* Record that the value was promoted from mode1 to mode3,
1405 so that any sign extension at the head of the current
1406 function may be eliminated. */
1407 x = gen_rtx_CLOBBER (mode1, const0_rtx);
1408 x = gen_rtx_fmt_e ((uns3 ? ZERO_EXTEND : SIGN_EXTEND), mode3, x);
1409 record_value_for_reg (reg, first, x);
1413 /* Called via note_stores. If X is a pseudo that is narrower than
1414 HOST_BITS_PER_WIDE_INT and is being set, record what bits are known zero.
1416 If we are setting only a portion of X and we can't figure out what
1417 portion, assume all bits will be used since we don't know what will
1420 Similarly, set how many bits of X are known to be copies of the sign bit
1421 at all locations in the function. This is the smallest number implied
1425 set_nonzero_bits_and_sign_copies (rtx x, const_rtx set, void *data)
1427 rtx insn = (rtx) data;
1431 && REGNO (x) >= FIRST_PSEUDO_REGISTER
1432 /* If this register is undefined at the start of the file, we can't
1433 say what its contents were. */
1434 && ! REGNO_REG_SET_P
1435 (DF_LR_IN (ENTRY_BLOCK_PTR->next_bb), REGNO (x))
1436 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT)
1438 reg_stat_type *rsp = VEC_index (reg_stat_type, reg_stat, REGNO (x));
1440 if (set == 0 || GET_CODE (set) == CLOBBER)
1442 rsp->nonzero_bits = GET_MODE_MASK (GET_MODE (x));
1443 rsp->sign_bit_copies = 1;
1447 /* If this register is being initialized using itself, and the
1448 register is uninitialized in this basic block, and there are
1449 no LOG_LINKS which set the register, then part of the
1450 register is uninitialized. In that case we can't assume
1451 anything about the number of nonzero bits.
1453 ??? We could do better if we checked this in
1454 reg_{nonzero_bits,num_sign_bit_copies}_for_combine. Then we
1455 could avoid making assumptions about the insn which initially
1456 sets the register, while still using the information in other
1457 insns. We would have to be careful to check every insn
1458 involved in the combination. */
1461 && reg_referenced_p (x, PATTERN (insn))
1462 && !REGNO_REG_SET_P (DF_LR_IN (BLOCK_FOR_INSN (insn)),
1467 for (link = LOG_LINKS (insn); link; link = XEXP (link, 1))
1469 if (dead_or_set_p (XEXP (link, 0), x))
1474 rsp->nonzero_bits = GET_MODE_MASK (GET_MODE (x));
1475 rsp->sign_bit_copies = 1;
1480 /* If this is a complex assignment, see if we can convert it into a
1481 simple assignment. */
1482 set = expand_field_assignment (set);
1484 /* If this is a simple assignment, or we have a paradoxical SUBREG,
1485 set what we know about X. */
1487 if (SET_DEST (set) == x
1488 || (GET_CODE (SET_DEST (set)) == SUBREG
1489 && (GET_MODE_SIZE (GET_MODE (SET_DEST (set)))
1490 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (set)))))
1491 && SUBREG_REG (SET_DEST (set)) == x))
1493 rtx src = SET_SRC (set);
1495 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
1496 /* If X is narrower than a word and SRC is a non-negative
1497 constant that would appear negative in the mode of X,
1498 sign-extend it for use in reg_stat[].nonzero_bits because some
1499 machines (maybe most) will actually do the sign-extension
1500 and this is the conservative approach.
1502 ??? For 2.5, try to tighten up the MD files in this regard
1503 instead of this kludge. */
1505 if (GET_MODE_BITSIZE (GET_MODE (x)) < BITS_PER_WORD
1506 && CONST_INT_P (src)
1508 && 0 != (INTVAL (src)
1509 & ((HOST_WIDE_INT) 1
1510 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
1511 src = GEN_INT (INTVAL (src)
1512 | ((HOST_WIDE_INT) (-1)
1513 << GET_MODE_BITSIZE (GET_MODE (x))));
1516 /* Don't call nonzero_bits if it cannot change anything. */
1517 if (rsp->nonzero_bits != ~(unsigned HOST_WIDE_INT) 0)
1518 rsp->nonzero_bits |= nonzero_bits (src, nonzero_bits_mode);
1519 num = num_sign_bit_copies (SET_SRC (set), GET_MODE (x));
1520 if (rsp->sign_bit_copies == 0
1521 || rsp->sign_bit_copies > num)
1522 rsp->sign_bit_copies = num;
1526 rsp->nonzero_bits = GET_MODE_MASK (GET_MODE (x));
1527 rsp->sign_bit_copies = 1;
1532 /* See if INSN can be combined into I3. PRED and SUCC are optionally
1533 insns that were previously combined into I3 or that will be combined
1534 into the merger of INSN and I3.
1536 Return 0 if the combination is not allowed for any reason.
1538 If the combination is allowed, *PDEST will be set to the single
1539 destination of INSN and *PSRC to the single source, and this function
1543 can_combine_p (rtx insn, rtx i3, rtx pred ATTRIBUTE_UNUSED, rtx succ,
1544 rtx *pdest, rtx *psrc)
1553 int all_adjacent = (succ ? (next_active_insn (insn) == succ
1554 && next_active_insn (succ) == i3)
1555 : next_active_insn (insn) == i3);
1557 /* Can combine only if previous insn is a SET of a REG, a SUBREG or CC0.
1558 or a PARALLEL consisting of such a SET and CLOBBERs.
1560 If INSN has CLOBBER parallel parts, ignore them for our processing.
1561 By definition, these happen during the execution of the insn. When it
1562 is merged with another insn, all bets are off. If they are, in fact,
1563 needed and aren't also supplied in I3, they may be added by
1564 recog_for_combine. Otherwise, it won't match.
1566 We can also ignore a SET whose SET_DEST is mentioned in a REG_UNUSED
1569 Get the source and destination of INSN. If more than one, can't
1572 if (GET_CODE (PATTERN (insn)) == SET)
1573 set = PATTERN (insn);
1574 else if (GET_CODE (PATTERN (insn)) == PARALLEL
1575 && GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == SET)
1577 for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
1579 rtx elt = XVECEXP (PATTERN (insn), 0, i);
1581 switch (GET_CODE (elt))
1583 /* This is important to combine floating point insns
1584 for the SH4 port. */
1586 /* Combining an isolated USE doesn't make sense.
1587 We depend here on combinable_i3pat to reject them. */
1588 /* The code below this loop only verifies that the inputs of
1589 the SET in INSN do not change. We call reg_set_between_p
1590 to verify that the REG in the USE does not change between
1592 If the USE in INSN was for a pseudo register, the matching
1593 insn pattern will likely match any register; combining this
1594 with any other USE would only be safe if we knew that the
1595 used registers have identical values, or if there was
1596 something to tell them apart, e.g. different modes. For
1597 now, we forgo such complicated tests and simply disallow
1598 combining of USES of pseudo registers with any other USE. */
1599 if (REG_P (XEXP (elt, 0))
1600 && GET_CODE (PATTERN (i3)) == PARALLEL)
1602 rtx i3pat = PATTERN (i3);
1603 int i = XVECLEN (i3pat, 0) - 1;
1604 unsigned int regno = REGNO (XEXP (elt, 0));
1608 rtx i3elt = XVECEXP (i3pat, 0, i);
1610 if (GET_CODE (i3elt) == USE
1611 && REG_P (XEXP (i3elt, 0))
1612 && (REGNO (XEXP (i3elt, 0)) == regno
1613 ? reg_set_between_p (XEXP (elt, 0),
1614 PREV_INSN (insn), i3)
1615 : regno >= FIRST_PSEUDO_REGISTER))
1622 /* We can ignore CLOBBERs. */
1627 /* Ignore SETs whose result isn't used but not those that
1628 have side-effects. */
1629 if (find_reg_note (insn, REG_UNUSED, SET_DEST (elt))
1630 && insn_nothrow_p (insn)
1631 && !side_effects_p (elt))
1634 /* If we have already found a SET, this is a second one and
1635 so we cannot combine with this insn. */
1643 /* Anything else means we can't combine. */
1649 /* If SET_SRC is an ASM_OPERANDS we can't throw away these CLOBBERs,
1650 so don't do anything with it. */
1651 || GET_CODE (SET_SRC (set)) == ASM_OPERANDS)
1660 set = expand_field_assignment (set);
1661 src = SET_SRC (set), dest = SET_DEST (set);
1663 /* Don't eliminate a store in the stack pointer. */
1664 if (dest == stack_pointer_rtx
1665 /* Don't combine with an insn that sets a register to itself if it has
1666 a REG_EQUAL note. This may be part of a LIBCALL sequence. */
1667 || (rtx_equal_p (src, dest) && find_reg_note (insn, REG_EQUAL, NULL_RTX))
1668 /* Can't merge an ASM_OPERANDS. */
1669 || GET_CODE (src) == ASM_OPERANDS
1670 /* Can't merge a function call. */
1671 || GET_CODE (src) == CALL
1672 /* Don't eliminate a function call argument. */
1674 && (find_reg_fusage (i3, USE, dest)
1676 && REGNO (dest) < FIRST_PSEUDO_REGISTER
1677 && global_regs[REGNO (dest)])))
1678 /* Don't substitute into an incremented register. */
1679 || FIND_REG_INC_NOTE (i3, dest)
1680 || (succ && FIND_REG_INC_NOTE (succ, dest))
1681 /* Don't substitute into a non-local goto, this confuses CFG. */
1682 || (JUMP_P (i3) && find_reg_note (i3, REG_NON_LOCAL_GOTO, NULL_RTX))
1683 /* Make sure that DEST is not used after SUCC but before I3. */
1684 || (succ && ! all_adjacent
1685 && reg_used_between_p (dest, succ, i3))
1686 /* Make sure that the value that is to be substituted for the register
1687 does not use any registers whose values alter in between. However,
1688 If the insns are adjacent, a use can't cross a set even though we
1689 think it might (this can happen for a sequence of insns each setting
1690 the same destination; last_set of that register might point to
1691 a NOTE). If INSN has a REG_EQUIV note, the register is always
1692 equivalent to the memory so the substitution is valid even if there
1693 are intervening stores. Also, don't move a volatile asm or
1694 UNSPEC_VOLATILE across any other insns. */
1697 || ! find_reg_note (insn, REG_EQUIV, src))
1698 && use_crosses_set_p (src, DF_INSN_LUID (insn)))
1699 || (GET_CODE (src) == ASM_OPERANDS && MEM_VOLATILE_P (src))
1700 || GET_CODE (src) == UNSPEC_VOLATILE))
1701 /* Don't combine across a CALL_INSN, because that would possibly
1702 change whether the life span of some REGs crosses calls or not,
1703 and it is a pain to update that information.
1704 Exception: if source is a constant, moving it later can't hurt.
1705 Accept that as a special case. */
1706 || (DF_INSN_LUID (insn) < last_call_luid && ! CONSTANT_P (src)))
1709 /* DEST must either be a REG or CC0. */
1712 /* If register alignment is being enforced for multi-word items in all
1713 cases except for parameters, it is possible to have a register copy
1714 insn referencing a hard register that is not allowed to contain the
1715 mode being copied and which would not be valid as an operand of most
1716 insns. Eliminate this problem by not combining with such an insn.
1718 Also, on some machines we don't want to extend the life of a hard
1722 && ((REGNO (dest) < FIRST_PSEUDO_REGISTER
1723 && ! HARD_REGNO_MODE_OK (REGNO (dest), GET_MODE (dest)))
1724 /* Don't extend the life of a hard register unless it is
1725 user variable (if we have few registers) or it can't
1726 fit into the desired register (meaning something special
1728 Also avoid substituting a return register into I3, because
1729 reload can't handle a conflict with constraints of other
1731 || (REGNO (src) < FIRST_PSEUDO_REGISTER
1732 && ! HARD_REGNO_MODE_OK (REGNO (src), GET_MODE (src)))))
1735 else if (GET_CODE (dest) != CC0)
1739 if (GET_CODE (PATTERN (i3)) == PARALLEL)
1740 for (i = XVECLEN (PATTERN (i3), 0) - 1; i >= 0; i--)
1741 if (GET_CODE (XVECEXP (PATTERN (i3), 0, i)) == CLOBBER)
1743 /* Don't substitute for a register intended as a clobberable
1745 rtx reg = XEXP (XVECEXP (PATTERN (i3), 0, i), 0);
1746 if (rtx_equal_p (reg, dest))
1749 /* If the clobber represents an earlyclobber operand, we must not
1750 substitute an expression containing the clobbered register.
1751 As we do not analyze the constraint strings here, we have to
1752 make the conservative assumption. However, if the register is
1753 a fixed hard reg, the clobber cannot represent any operand;
1754 we leave it up to the machine description to either accept or
1755 reject use-and-clobber patterns. */
1757 || REGNO (reg) >= FIRST_PSEUDO_REGISTER
1758 || !fixed_regs[REGNO (reg)])
1759 if (reg_overlap_mentioned_p (reg, src))
1763 /* If INSN contains anything volatile, or is an `asm' (whether volatile
1764 or not), reject, unless nothing volatile comes between it and I3 */
1766 if (GET_CODE (src) == ASM_OPERANDS || volatile_refs_p (src))
1768 /* Make sure succ doesn't contain a volatile reference. */
1769 if (succ != 0 && volatile_refs_p (PATTERN (succ)))
1772 for (p = NEXT_INSN (insn); p != i3; p = NEXT_INSN (p))
1773 if (INSN_P (p) && p != succ && volatile_refs_p (PATTERN (p)))
1777 /* If INSN is an asm, and DEST is a hard register, reject, since it has
1778 to be an explicit register variable, and was chosen for a reason. */
1780 if (GET_CODE (src) == ASM_OPERANDS
1781 && REG_P (dest) && REGNO (dest) < FIRST_PSEUDO_REGISTER)
1784 /* If there are any volatile insns between INSN and I3, reject, because
1785 they might affect machine state. */
1787 for (p = NEXT_INSN (insn); p != i3; p = NEXT_INSN (p))
1788 if (INSN_P (p) && p != succ && volatile_insn_p (PATTERN (p)))
1791 /* If INSN contains an autoincrement or autodecrement, make sure that
1792 register is not used between there and I3, and not already used in
1793 I3 either. Neither must it be used in PRED or SUCC, if they exist.
1794 Also insist that I3 not be a jump; if it were one
1795 and the incremented register were spilled, we would lose. */
1798 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
1799 if (REG_NOTE_KIND (link) == REG_INC
1801 || reg_used_between_p (XEXP (link, 0), insn, i3)
1802 || (pred != NULL_RTX
1803 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (pred)))
1804 || (succ != NULL_RTX
1805 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (succ)))
1806 || reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i3))))
1811 /* Don't combine an insn that follows a CC0-setting insn.
1812 An insn that uses CC0 must not be separated from the one that sets it.
1813 We do, however, allow I2 to follow a CC0-setting insn if that insn
1814 is passed as I1; in that case it will be deleted also.
1815 We also allow combining in this case if all the insns are adjacent
1816 because that would leave the two CC0 insns adjacent as well.
1817 It would be more logical to test whether CC0 occurs inside I1 or I2,
1818 but that would be much slower, and this ought to be equivalent. */
1820 p = prev_nonnote_insn (insn);
1821 if (p && p != pred && NONJUMP_INSN_P (p) && sets_cc0_p (PATTERN (p))
1826 /* If we get here, we have passed all the tests and the combination is
1835 /* LOC is the location within I3 that contains its pattern or the component
1836 of a PARALLEL of the pattern. We validate that it is valid for combining.
1838 One problem is if I3 modifies its output, as opposed to replacing it
1839 entirely, we can't allow the output to contain I2DEST or I1DEST as doing
1840 so would produce an insn that is not equivalent to the original insns.
1844 (set (reg:DI 101) (reg:DI 100))
1845 (set (subreg:SI (reg:DI 101) 0) <foo>)
1847 This is NOT equivalent to:
1849 (parallel [(set (subreg:SI (reg:DI 100) 0) <foo>)
1850 (set (reg:DI 101) (reg:DI 100))])
1852 Not only does this modify 100 (in which case it might still be valid
1853 if 100 were dead in I2), it sets 101 to the ORIGINAL value of 100.
1855 We can also run into a problem if I2 sets a register that I1
1856 uses and I1 gets directly substituted into I3 (not via I2). In that
1857 case, we would be getting the wrong value of I2DEST into I3, so we
1858 must reject the combination. This case occurs when I2 and I1 both
1859 feed into I3, rather than when I1 feeds into I2, which feeds into I3.
1860 If I1_NOT_IN_SRC is nonzero, it means that finding I1 in the source
1861 of a SET must prevent combination from occurring.
1863 Before doing the above check, we first try to expand a field assignment
1864 into a set of logical operations.
1866 If PI3_DEST_KILLED is nonzero, it is a pointer to a location in which
1867 we place a register that is both set and used within I3. If more than one
1868 such register is detected, we fail.
1870 Return 1 if the combination is valid, zero otherwise. */
1873 combinable_i3pat (rtx i3, rtx *loc, rtx i2dest, rtx i1dest,
1874 int i1_not_in_src, rtx *pi3dest_killed)
1878 if (GET_CODE (x) == SET)
1881 rtx dest = SET_DEST (set);
1882 rtx src = SET_SRC (set);
1883 rtx inner_dest = dest;
1886 while (GET_CODE (inner_dest) == STRICT_LOW_PART
1887 || GET_CODE (inner_dest) == SUBREG
1888 || GET_CODE (inner_dest) == ZERO_EXTRACT)
1889 inner_dest = XEXP (inner_dest, 0);
1891 /* Check for the case where I3 modifies its output, as discussed
1892 above. We don't want to prevent pseudos from being combined
1893 into the address of a MEM, so only prevent the combination if
1894 i1 or i2 set the same MEM. */
1895 if ((inner_dest != dest &&
1896 (!MEM_P (inner_dest)
1897 || rtx_equal_p (i2dest, inner_dest)
1898 || (i1dest && rtx_equal_p (i1dest, inner_dest)))
1899 && (reg_overlap_mentioned_p (i2dest, inner_dest)
1900 || (i1dest && reg_overlap_mentioned_p (i1dest, inner_dest))))
1902 /* This is the same test done in can_combine_p except we can't test
1903 all_adjacent; we don't have to, since this instruction will stay
1904 in place, thus we are not considering increasing the lifetime of
1907 Also, if this insn sets a function argument, combining it with
1908 something that might need a spill could clobber a previous
1909 function argument; the all_adjacent test in can_combine_p also
1910 checks this; here, we do a more specific test for this case. */
1912 || (REG_P (inner_dest)
1913 && REGNO (inner_dest) < FIRST_PSEUDO_REGISTER
1914 && (! HARD_REGNO_MODE_OK (REGNO (inner_dest),
1915 GET_MODE (inner_dest))))
1916 || (i1_not_in_src && reg_overlap_mentioned_p (i1dest, src)))
1919 /* If DEST is used in I3, it is being killed in this insn, so
1920 record that for later. We have to consider paradoxical
1921 subregs here, since they kill the whole register, but we
1922 ignore partial subregs, STRICT_LOW_PART, etc.
1923 Never add REG_DEAD notes for the FRAME_POINTER_REGNUM or the
1924 STACK_POINTER_REGNUM, since these are always considered to be
1925 live. Similarly for ARG_POINTER_REGNUM if it is fixed. */
1927 if (GET_CODE (subdest) == SUBREG
1928 && (GET_MODE_SIZE (GET_MODE (subdest))
1929 >= GET_MODE_SIZE (GET_MODE (SUBREG_REG (subdest)))))
1930 subdest = SUBREG_REG (subdest);
1933 && reg_referenced_p (subdest, PATTERN (i3))
1934 && REGNO (subdest) != FRAME_POINTER_REGNUM
1935 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
1936 && REGNO (subdest) != HARD_FRAME_POINTER_REGNUM
1938 #if ARG_POINTER_REGNUM != FRAME_POINTER_REGNUM
1939 && (REGNO (subdest) != ARG_POINTER_REGNUM
1940 || ! fixed_regs [REGNO (subdest)])
1942 && REGNO (subdest) != STACK_POINTER_REGNUM)
1944 if (*pi3dest_killed)
1947 *pi3dest_killed = subdest;
1951 else if (GET_CODE (x) == PARALLEL)
1955 for (i = 0; i < XVECLEN (x, 0); i++)
1956 if (! combinable_i3pat (i3, &XVECEXP (x, 0, i), i2dest, i1dest,
1957 i1_not_in_src, pi3dest_killed))
1964 /* Return 1 if X is an arithmetic expression that contains a multiplication
1965 and division. We don't count multiplications by powers of two here. */
1968 contains_muldiv (rtx x)
1970 switch (GET_CODE (x))
1972 case MOD: case DIV: case UMOD: case UDIV:
1976 return ! (CONST_INT_P (XEXP (x, 1))
1977 && exact_log2 (INTVAL (XEXP (x, 1))) >= 0);
1980 return contains_muldiv (XEXP (x, 0))
1981 || contains_muldiv (XEXP (x, 1));
1984 return contains_muldiv (XEXP (x, 0));
1990 /* Determine whether INSN can be used in a combination. Return nonzero if
1991 not. This is used in try_combine to detect early some cases where we
1992 can't perform combinations. */
1995 cant_combine_insn_p (rtx insn)
2000 /* If this isn't really an insn, we can't do anything.
2001 This can occur when flow deletes an insn that it has merged into an
2002 auto-increment address. */
2003 if (! INSN_P (insn))
2006 /* Never combine loads and stores involving hard regs that are likely
2007 to be spilled. The register allocator can usually handle such
2008 reg-reg moves by tying. If we allow the combiner to make
2009 substitutions of likely-spilled regs, reload might die.
2010 As an exception, we allow combinations involving fixed regs; these are
2011 not available to the register allocator so there's no risk involved. */
2013 set = single_set (insn);
2016 src = SET_SRC (set);
2017 dest = SET_DEST (set);
2018 if (GET_CODE (src) == SUBREG)
2019 src = SUBREG_REG (src);
2020 if (GET_CODE (dest) == SUBREG)
2021 dest = SUBREG_REG (dest);
2022 if (REG_P (src) && REG_P (dest)
2023 && ((REGNO (src) < FIRST_PSEUDO_REGISTER
2024 && ! fixed_regs[REGNO (src)]
2025 && CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (REGNO (src))))
2026 || (REGNO (dest) < FIRST_PSEUDO_REGISTER
2027 && ! fixed_regs[REGNO (dest)]
2028 && CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (REGNO (dest))))))
2034 struct likely_spilled_retval_info
2036 unsigned regno, nregs;
2040 /* Called via note_stores by likely_spilled_retval_p. Remove from info->mask
2041 hard registers that are known to be written to / clobbered in full. */
2043 likely_spilled_retval_1 (rtx x, const_rtx set, void *data)
2045 struct likely_spilled_retval_info *const info =
2046 (struct likely_spilled_retval_info *) data;
2047 unsigned regno, nregs;
2050 if (!REG_P (XEXP (set, 0)))
2053 if (regno >= info->regno + info->nregs)
2055 nregs = hard_regno_nregs[regno][GET_MODE (x)];
2056 if (regno + nregs <= info->regno)
2058 new_mask = (2U << (nregs - 1)) - 1;
2059 if (regno < info->regno)
2060 new_mask >>= info->regno - regno;
2062 new_mask <<= regno - info->regno;
2063 info->mask &= ~new_mask;
2066 /* Return nonzero iff part of the return value is live during INSN, and
2067 it is likely spilled. This can happen when more than one insn is needed
2068 to copy the return value, e.g. when we consider to combine into the
2069 second copy insn for a complex value. */
2072 likely_spilled_retval_p (rtx insn)
2074 rtx use = BB_END (this_basic_block);
2076 unsigned regno, nregs;
2077 /* We assume here that no machine mode needs more than
2078 32 hard registers when the value overlaps with a register
2079 for which FUNCTION_VALUE_REGNO_P is true. */
2081 struct likely_spilled_retval_info info;
2083 if (!NONJUMP_INSN_P (use) || GET_CODE (PATTERN (use)) != USE || insn == use)
2085 reg = XEXP (PATTERN (use), 0);
2086 if (!REG_P (reg) || !FUNCTION_VALUE_REGNO_P (REGNO (reg)))
2088 regno = REGNO (reg);
2089 nregs = hard_regno_nregs[regno][GET_MODE (reg)];
2092 mask = (2U << (nregs - 1)) - 1;
2094 /* Disregard parts of the return value that are set later. */
2098 for (p = PREV_INSN (use); info.mask && p != insn; p = PREV_INSN (p))
2100 note_stores (PATTERN (p), likely_spilled_retval_1, &info);
2103 /* Check if any of the (probably) live return value registers is
2108 if ((mask & 1 << nregs)
2109 && CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (regno + nregs)))
2115 /* Adjust INSN after we made a change to its destination.
2117 Changing the destination can invalidate notes that say something about
2118 the results of the insn and a LOG_LINK pointing to the insn. */
2121 adjust_for_new_dest (rtx insn)
2123 /* For notes, be conservative and simply remove them. */
2124 remove_reg_equal_equiv_notes (insn);
2126 /* The new insn will have a destination that was previously the destination
2127 of an insn just above it. Call distribute_links to make a LOG_LINK from
2128 the next use of that destination. */
2129 distribute_links (gen_rtx_INSN_LIST (VOIDmode, insn, NULL_RTX));
2131 df_insn_rescan (insn);
2134 /* Return TRUE if combine can reuse reg X in mode MODE.
2135 ADDED_SETS is nonzero if the original set is still required. */
2137 can_change_dest_mode (rtx x, int added_sets, enum machine_mode mode)
2145 /* Allow hard registers if the new mode is legal, and occupies no more
2146 registers than the old mode. */
2147 if (regno < FIRST_PSEUDO_REGISTER)
2148 return (HARD_REGNO_MODE_OK (regno, mode)
2149 && (hard_regno_nregs[regno][GET_MODE (x)]
2150 >= hard_regno_nregs[regno][mode]));
2152 /* Or a pseudo that is only used once. */
2153 return (REG_N_SETS (regno) == 1 && !added_sets
2154 && !REG_USERVAR_P (x));
2158 /* Check whether X, the destination of a set, refers to part of
2159 the register specified by REG. */
2162 reg_subword_p (rtx x, rtx reg)
2164 /* Check that reg is an integer mode register. */
2165 if (!REG_P (reg) || GET_MODE_CLASS (GET_MODE (reg)) != MODE_INT)
2168 if (GET_CODE (x) == STRICT_LOW_PART
2169 || GET_CODE (x) == ZERO_EXTRACT)
2172 return GET_CODE (x) == SUBREG
2173 && SUBREG_REG (x) == reg
2174 && GET_MODE_CLASS (GET_MODE (x)) == MODE_INT;
2178 /* Replace auto-increment addressing modes with explicit operations to
2179 access the same addresses without modifying the corresponding
2180 registers. If AFTER holds, SRC is meant to be reused after the
2181 side effect, otherwise it is to be reused before that. */
2184 cleanup_auto_inc_dec (rtx src, bool after, enum machine_mode mem_mode)
2187 const RTX_CODE code = GET_CODE (x);
2203 /* SCRATCH must be shared because they represent distinct values. */
2206 if (REG_P (XEXP (x, 0)) && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER)
2211 if (shared_const_p (x))
2216 mem_mode = GET_MODE (x);
2223 gcc_assert (mem_mode != VOIDmode && mem_mode != BLKmode);
2224 if (after == (code == PRE_INC || code == PRE_DEC))
2225 x = cleanup_auto_inc_dec (XEXP (x, 0), after, mem_mode);
2227 x = gen_rtx_PLUS (GET_MODE (x),
2228 cleanup_auto_inc_dec (XEXP (x, 0), after, mem_mode),
2229 GEN_INT ((code == PRE_INC || code == POST_INC)
2230 ? GET_MODE_SIZE (mem_mode)
2231 : -GET_MODE_SIZE (mem_mode)));
2236 if (after == (code == PRE_MODIFY))
2240 return cleanup_auto_inc_dec (x, after, mem_mode);
2246 /* Copy the various flags, fields, and other information. We assume
2247 that all fields need copying, and then clear the fields that should
2248 not be copied. That is the sensible default behavior, and forces
2249 us to explicitly document why we are *not* copying a flag. */
2250 x = shallow_copy_rtx (x);
2252 /* We do not copy the USED flag, which is used as a mark bit during
2253 walks over the RTL. */
2254 RTX_FLAG (x, used) = 0;
2256 /* We do not copy FRAME_RELATED for INSNs. */
2258 RTX_FLAG (x, frame_related) = 0;
2260 fmt = GET_RTX_FORMAT (code);
2261 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
2263 XEXP (x, i) = cleanup_auto_inc_dec (XEXP (x, i), after, mem_mode);
2264 else if (fmt[i] == 'E' || fmt[i] == 'V')
2267 XVEC (x, i) = rtvec_alloc (XVECLEN (x, i));
2268 for (j = 0; j < XVECLEN (x, i); j++)
2270 = cleanup_auto_inc_dec (XVECEXP (src, i, j), after, mem_mode);
2276 /* Auxiliary data structure for propagate_for_debug_stmt. */
2278 struct rtx_subst_pair
2285 /* DATA points to an rtx_subst_pair. Return the value that should be
2289 propagate_for_debug_subst (rtx from ATTRIBUTE_UNUSED, void *data)
2291 struct rtx_subst_pair *pair = (struct rtx_subst_pair *)data;
2293 if (!pair->adjusted)
2295 pair->adjusted = true;
2296 pair->to = cleanup_auto_inc_dec (pair->to, pair->after, VOIDmode);
2299 return copy_rtx (pair->to);
2303 /* Replace occurrences of DEST with SRC in DEBUG_INSNs between INSN
2304 and LAST. If MOVE holds, debug insns must also be moved past
2308 propagate_for_debug (rtx insn, rtx last, rtx dest, rtx src, bool move)
2310 rtx next, move_pos = move ? last : NULL_RTX, loc;
2313 struct rtx_subst_pair p;
2319 next = NEXT_INSN (insn);
2320 while (next != last)
2323 next = NEXT_INSN (insn);
2324 if (DEBUG_INSN_P (insn))
2327 loc = simplify_replace_fn_rtx (INSN_VAR_LOCATION_LOC (insn),
2328 dest, propagate_for_debug_subst, &p);
2330 loc = simplify_replace_rtx (INSN_VAR_LOCATION_LOC (insn), dest, src);
2332 if (loc == INSN_VAR_LOCATION_LOC (insn))
2334 INSN_VAR_LOCATION_LOC (insn) = loc;
2338 PREV_INSN (insn) = NEXT_INSN (insn) = NULL_RTX;
2339 move_pos = emit_debug_insn_after (insn, move_pos);
2342 df_insn_rescan (insn);
2347 /* Delete the unconditional jump INSN and adjust the CFG correspondingly.
2348 Note that the INSN should be deleted *after* removing dead edges, so
2349 that the kept edge is the fallthrough edge for a (set (pc) (pc))
2350 but not for a (set (pc) (label_ref FOO)). */
2353 update_cfg_for_uncondjump (rtx insn)
2355 basic_block bb = BLOCK_FOR_INSN (insn);
2356 bool at_end = (BB_END (bb) == insn);
2359 purge_dead_edges (bb);
2362 if (at_end && EDGE_COUNT (bb->succs) == 1)
2363 single_succ_edge (bb)->flags |= EDGE_FALLTHRU;
2367 /* Try to combine the insns I1 and I2 into I3.
2368 Here I1 and I2 appear earlier than I3.
2369 I1 can be zero; then we combine just I2 into I3.
2371 If we are combining three insns and the resulting insn is not recognized,
2372 try splitting it into two insns. If that happens, I2 and I3 are retained
2373 and I1 is pseudo-deleted by turning it into a NOTE. Otherwise, I1 and I2
2376 Return 0 if the combination does not work. Then nothing is changed.
2377 If we did the combination, return the insn at which combine should
2380 Set NEW_DIRECT_JUMP_P to a nonzero value if try_combine creates a
2381 new direct jump instruction. */
2384 try_combine (rtx i3, rtx i2, rtx i1, int *new_direct_jump_p)
2386 /* New patterns for I3 and I2, respectively. */
2387 rtx newpat, newi2pat = 0;
2388 rtvec newpat_vec_with_clobbers = 0;
2389 int substed_i2 = 0, substed_i1 = 0;
2390 /* Indicates need to preserve SET in I1 or I2 in I3 if it is not dead. */
2391 int added_sets_1, added_sets_2;
2392 /* Total number of SETs to put into I3. */
2394 /* Nonzero if I2's body now appears in I3. */
2396 /* INSN_CODEs for new I3, new I2, and user of condition code. */
2397 int insn_code_number, i2_code_number = 0, other_code_number = 0;
2398 /* Contains I3 if the destination of I3 is used in its source, which means
2399 that the old life of I3 is being killed. If that usage is placed into
2400 I2 and not in I3, a REG_DEAD note must be made. */
2401 rtx i3dest_killed = 0;
2402 /* SET_DEST and SET_SRC of I2 and I1. */
2403 rtx i2dest = 0, i2src = 0, i1dest = 0, i1src = 0;
2404 /* Set if I2DEST was reused as a scratch register. */
2405 bool i2scratch = false;
2406 /* PATTERN (I1) and PATTERN (I2), or a copy of it in certain cases. */
2407 rtx i1pat = 0, i2pat = 0;
2408 /* Indicates if I2DEST or I1DEST is in I2SRC or I1_SRC. */
2409 int i2dest_in_i2src = 0, i1dest_in_i1src = 0, i2dest_in_i1src = 0;
2410 int i2dest_killed = 0, i1dest_killed = 0;
2411 int i1_feeds_i3 = 0;
2412 /* Notes that must be added to REG_NOTES in I3 and I2. */
2413 rtx new_i3_notes, new_i2_notes;
2414 /* Notes that we substituted I3 into I2 instead of the normal case. */
2415 int i3_subst_into_i2 = 0;
2416 /* Notes that I1, I2 or I3 is a MULT operation. */
2419 int changed_i3_dest = 0;
2425 rtx new_other_notes;
2428 /* Exit early if one of the insns involved can't be used for
2430 if (cant_combine_insn_p (i3)
2431 || cant_combine_insn_p (i2)
2432 || (i1 && cant_combine_insn_p (i1))
2433 || likely_spilled_retval_p (i3))
2437 undobuf.other_insn = 0;
2439 /* Reset the hard register usage information. */
2440 CLEAR_HARD_REG_SET (newpat_used_regs);
2442 if (dump_file && (dump_flags & TDF_DETAILS))
2445 fprintf (dump_file, "\nTrying %d, %d -> %d:\n",
2446 INSN_UID (i1), INSN_UID (i2), INSN_UID (i3));
2448 fprintf (dump_file, "\nTrying %d -> %d:\n",
2449 INSN_UID (i2), INSN_UID (i3));
2452 /* If I1 and I2 both feed I3, they can be in any order. To simplify the
2453 code below, set I1 to be the earlier of the two insns. */
2454 if (i1 && DF_INSN_LUID (i1) > DF_INSN_LUID (i2))
2455 temp = i1, i1 = i2, i2 = temp;
2457 added_links_insn = 0;
2459 /* First check for one important special-case that the code below will
2460 not handle. Namely, the case where I1 is zero, I2 is a PARALLEL
2461 and I3 is a SET whose SET_SRC is a SET_DEST in I2. In that case,
2462 we may be able to replace that destination with the destination of I3.
2463 This occurs in the common code where we compute both a quotient and
2464 remainder into a structure, in which case we want to do the computation
2465 directly into the structure to avoid register-register copies.
2467 Note that this case handles both multiple sets in I2 and also
2468 cases where I2 has a number of CLOBBER or PARALLELs.
2470 We make very conservative checks below and only try to handle the
2471 most common cases of this. For example, we only handle the case
2472 where I2 and I3 are adjacent to avoid making difficult register
2475 if (i1 == 0 && NONJUMP_INSN_P (i3) && GET_CODE (PATTERN (i3)) == SET
2476 && REG_P (SET_SRC (PATTERN (i3)))
2477 && REGNO (SET_SRC (PATTERN (i3))) >= FIRST_PSEUDO_REGISTER
2478 && find_reg_note (i3, REG_DEAD, SET_SRC (PATTERN (i3)))
2479 && GET_CODE (PATTERN (i2)) == PARALLEL
2480 && ! side_effects_p (SET_DEST (PATTERN (i3)))
2481 /* If the dest of I3 is a ZERO_EXTRACT or STRICT_LOW_PART, the code
2482 below would need to check what is inside (and reg_overlap_mentioned_p
2483 doesn't support those codes anyway). Don't allow those destinations;
2484 the resulting insn isn't likely to be recognized anyway. */
2485 && GET_CODE (SET_DEST (PATTERN (i3))) != ZERO_EXTRACT
2486 && GET_CODE (SET_DEST (PATTERN (i3))) != STRICT_LOW_PART
2487 && ! reg_overlap_mentioned_p (SET_SRC (PATTERN (i3)),
2488 SET_DEST (PATTERN (i3)))
2489 && next_active_insn (i2) == i3)
2491 rtx p2 = PATTERN (i2);
2493 /* Make sure that the destination of I3,
2494 which we are going to substitute into one output of I2,
2495 is not used within another output of I2. We must avoid making this:
2496 (parallel [(set (mem (reg 69)) ...)
2497 (set (reg 69) ...)])
2498 which is not well-defined as to order of actions.
2499 (Besides, reload can't handle output reloads for this.)
2501 The problem can also happen if the dest of I3 is a memory ref,
2502 if another dest in I2 is an indirect memory ref. */
2503 for (i = 0; i < XVECLEN (p2, 0); i++)
2504 if ((GET_CODE (XVECEXP (p2, 0, i)) == SET
2505 || GET_CODE (XVECEXP (p2, 0, i)) == CLOBBER)
2506 && reg_overlap_mentioned_p (SET_DEST (PATTERN (i3)),
2507 SET_DEST (XVECEXP (p2, 0, i))))
2510 if (i == XVECLEN (p2, 0))
2511 for (i = 0; i < XVECLEN (p2, 0); i++)
2512 if ((GET_CODE (XVECEXP (p2, 0, i)) == SET
2513 || GET_CODE (XVECEXP (p2, 0, i)) == CLOBBER)
2514 && SET_DEST (XVECEXP (p2, 0, i)) == SET_SRC (PATTERN (i3)))
2519 subst_low_luid = DF_INSN_LUID (i2);
2521 added_sets_2 = added_sets_1 = 0;
2522 i2src = SET_DEST (PATTERN (i3));
2523 i2dest = SET_SRC (PATTERN (i3));
2524 i2dest_killed = dead_or_set_p (i2, i2dest);
2526 /* Replace the dest in I2 with our dest and make the resulting
2527 insn the new pattern for I3. Then skip to where we
2528 validate the pattern. Everything was set up above. */
2529 SUBST (SET_DEST (XVECEXP (p2, 0, i)),
2530 SET_DEST (PATTERN (i3)));
2533 i3_subst_into_i2 = 1;
2534 goto validate_replacement;
2538 /* If I2 is setting a pseudo to a constant and I3 is setting some
2539 sub-part of it to another constant, merge them by making a new
2542 && (temp = single_set (i2)) != 0
2543 && (CONST_INT_P (SET_SRC (temp))
2544 || GET_CODE (SET_SRC (temp)) == CONST_DOUBLE)
2545 && GET_CODE (PATTERN (i3)) == SET
2546 && (CONST_INT_P (SET_SRC (PATTERN (i3)))
2547 || GET_CODE (SET_SRC (PATTERN (i3))) == CONST_DOUBLE)
2548 && reg_subword_p (SET_DEST (PATTERN (i3)), SET_DEST (temp)))
2550 rtx dest = SET_DEST (PATTERN (i3));
2554 if (GET_CODE (dest) == ZERO_EXTRACT)
2556 if (CONST_INT_P (XEXP (dest, 1))
2557 && CONST_INT_P (XEXP (dest, 2)))
2559 width = INTVAL (XEXP (dest, 1));
2560 offset = INTVAL (XEXP (dest, 2));
2561 dest = XEXP (dest, 0);
2562 if (BITS_BIG_ENDIAN)
2563 offset = GET_MODE_BITSIZE (GET_MODE (dest)) - width - offset;
2568 if (GET_CODE (dest) == STRICT_LOW_PART)
2569 dest = XEXP (dest, 0);
2570 width = GET_MODE_BITSIZE (GET_MODE (dest));
2576 /* If this is the low part, we're done. */
2577 if (subreg_lowpart_p (dest))
2579 /* Handle the case where inner is twice the size of outer. */
2580 else if (GET_MODE_BITSIZE (GET_MODE (SET_DEST (temp)))
2581 == 2 * GET_MODE_BITSIZE (GET_MODE (dest)))
2582 offset += GET_MODE_BITSIZE (GET_MODE (dest));
2583 /* Otherwise give up for now. */
2589 && (GET_MODE_BITSIZE (GET_MODE (SET_DEST (temp)))
2590 <= HOST_BITS_PER_WIDE_INT * 2))
2592 HOST_WIDE_INT mhi, ohi, ihi;
2593 HOST_WIDE_INT mlo, olo, ilo;
2594 rtx inner = SET_SRC (PATTERN (i3));
2595 rtx outer = SET_SRC (temp);
2597 if (CONST_INT_P (outer))
2599 olo = INTVAL (outer);
2600 ohi = olo < 0 ? -1 : 0;
2604 olo = CONST_DOUBLE_LOW (outer);
2605 ohi = CONST_DOUBLE_HIGH (outer);
2608 if (CONST_INT_P (inner))
2610 ilo = INTVAL (inner);
2611 ihi = ilo < 0 ? -1 : 0;
2615 ilo = CONST_DOUBLE_LOW (inner);
2616 ihi = CONST_DOUBLE_HIGH (inner);
2619 if (width < HOST_BITS_PER_WIDE_INT)
2621 mlo = ((unsigned HOST_WIDE_INT) 1 << width) - 1;
2624 else if (width < HOST_BITS_PER_WIDE_INT * 2)
2626 mhi = ((unsigned HOST_WIDE_INT) 1
2627 << (width - HOST_BITS_PER_WIDE_INT)) - 1;
2639 if (offset >= HOST_BITS_PER_WIDE_INT)
2641 mhi = mlo << (offset - HOST_BITS_PER_WIDE_INT);
2643 ihi = ilo << (offset - HOST_BITS_PER_WIDE_INT);
2646 else if (offset > 0)
2648 mhi = (mhi << offset) | ((unsigned HOST_WIDE_INT) mlo
2649 >> (HOST_BITS_PER_WIDE_INT - offset));
2650 mlo = mlo << offset;
2651 ihi = (ihi << offset) | ((unsigned HOST_WIDE_INT) ilo
2652 >> (HOST_BITS_PER_WIDE_INT - offset));
2653 ilo = ilo << offset;
2656 olo = (olo & ~mlo) | ilo;
2657 ohi = (ohi & ~mhi) | ihi;
2661 subst_low_luid = DF_INSN_LUID (i2);
2662 added_sets_2 = added_sets_1 = 0;
2663 i2dest = SET_DEST (temp);
2664 i2dest_killed = dead_or_set_p (i2, i2dest);
2666 SUBST (SET_SRC (temp),
2667 immed_double_const (olo, ohi, GET_MODE (SET_DEST (temp))));
2669 newpat = PATTERN (i2);
2670 goto validate_replacement;
2675 /* If we have no I1 and I2 looks like:
2676 (parallel [(set (reg:CC X) (compare:CC OP (const_int 0)))
2678 make up a dummy I1 that is
2681 (set (reg:CC X) (compare:CC Y (const_int 0)))
2683 (We can ignore any trailing CLOBBERs.)
2685 This undoes a previous combination and allows us to match a branch-and-
2688 if (i1 == 0 && GET_CODE (PATTERN (i2)) == PARALLEL
2689 && XVECLEN (PATTERN (i2), 0) >= 2
2690 && GET_CODE (XVECEXP (PATTERN (i2), 0, 0)) == SET
2691 && (GET_MODE_CLASS (GET_MODE (SET_DEST (XVECEXP (PATTERN (i2), 0, 0))))
2693 && GET_CODE (SET_SRC (XVECEXP (PATTERN (i2), 0, 0))) == COMPARE
2694 && XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 1) == const0_rtx
2695 && GET_CODE (XVECEXP (PATTERN (i2), 0, 1)) == SET
2696 && REG_P (SET_DEST (XVECEXP (PATTERN (i2), 0, 1)))
2697 && rtx_equal_p (XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 0),
2698 SET_SRC (XVECEXP (PATTERN (i2), 0, 1))))
2700 for (i = XVECLEN (PATTERN (i2), 0) - 1; i >= 2; i--)
2701 if (GET_CODE (XVECEXP (PATTERN (i2), 0, i)) != CLOBBER)
2706 /* We make I1 with the same INSN_UID as I2. This gives it
2707 the same DF_INSN_LUID for value tracking. Our fake I1 will
2708 never appear in the insn stream so giving it the same INSN_UID
2709 as I2 will not cause a problem. */
2711 i1 = gen_rtx_INSN (VOIDmode, INSN_UID (i2), NULL_RTX, i2,
2712 BLOCK_FOR_INSN (i2), INSN_LOCATOR (i2),
2713 XVECEXP (PATTERN (i2), 0, 1), -1, NULL_RTX);
2715 SUBST (PATTERN (i2), XVECEXP (PATTERN (i2), 0, 0));
2716 SUBST (XEXP (SET_SRC (PATTERN (i2)), 0),
2717 SET_DEST (PATTERN (i1)));
2722 /* Verify that I2 and I1 are valid for combining. */
2723 if (! can_combine_p (i2, i3, i1, NULL_RTX, &i2dest, &i2src)
2724 || (i1 && ! can_combine_p (i1, i3, NULL_RTX, i2, &i1dest, &i1src)))
2730 /* Record whether I2DEST is used in I2SRC and similarly for the other
2731 cases. Knowing this will help in register status updating below. */
2732 i2dest_in_i2src = reg_overlap_mentioned_p (i2dest, i2src);
2733 i1dest_in_i1src = i1 && reg_overlap_mentioned_p (i1dest, i1src);
2734 i2dest_in_i1src = i1 && reg_overlap_mentioned_p (i2dest, i1src);
2735 i2dest_killed = dead_or_set_p (i2, i2dest);
2736 i1dest_killed = i1 && dead_or_set_p (i1, i1dest);
2738 /* See if I1 directly feeds into I3. It does if I1DEST is not used
2740 i1_feeds_i3 = i1 && ! reg_overlap_mentioned_p (i1dest, i2src);
2742 /* Ensure that I3's pattern can be the destination of combines. */
2743 if (! combinable_i3pat (i3, &PATTERN (i3), i2dest, i1dest,
2744 i1 && i2dest_in_i1src && i1_feeds_i3,
2751 /* See if any of the insns is a MULT operation. Unless one is, we will
2752 reject a combination that is, since it must be slower. Be conservative
2754 if (GET_CODE (i2src) == MULT
2755 || (i1 != 0 && GET_CODE (i1src) == MULT)
2756 || (GET_CODE (PATTERN (i3)) == SET
2757 && GET_CODE (SET_SRC (PATTERN (i3))) == MULT))
2760 /* If I3 has an inc, then give up if I1 or I2 uses the reg that is inc'd.
2761 We used to do this EXCEPT in one case: I3 has a post-inc in an
2762 output operand. However, that exception can give rise to insns like
2764 which is a famous insn on the PDP-11 where the value of r3 used as the
2765 source was model-dependent. Avoid this sort of thing. */
2768 if (!(GET_CODE (PATTERN (i3)) == SET
2769 && REG_P (SET_SRC (PATTERN (i3)))
2770 && MEM_P (SET_DEST (PATTERN (i3)))
2771 && (GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_INC
2772 || GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_DEC)))
2773 /* It's not the exception. */
2776 for (link = REG_NOTES (i3); link; link = XEXP (link, 1))
2777 if (REG_NOTE_KIND (link) == REG_INC
2778 && (reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i2))
2780 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i1)))))
2787 /* See if the SETs in I1 or I2 need to be kept around in the merged
2788 instruction: whenever the value set there is still needed past I3.
2789 For the SETs in I2, this is easy: we see if I2DEST dies or is set in I3.
2791 For the SET in I1, we have two cases: If I1 and I2 independently
2792 feed into I3, the set in I1 needs to be kept around if I1DEST dies
2793 or is set in I3. Otherwise (if I1 feeds I2 which feeds I3), the set
2794 in I1 needs to be kept around unless I1DEST dies or is set in either
2795 I2 or I3. We can distinguish these cases by seeing if I2SRC mentions
2796 I1DEST. If so, we know I1 feeds into I2. */
2798 added_sets_2 = ! dead_or_set_p (i3, i2dest);
2801 = i1 && ! (i1_feeds_i3 ? dead_or_set_p (i3, i1dest)
2802 : (dead_or_set_p (i3, i1dest) || dead_or_set_p (i2, i1dest)));
2804 /* If the set in I2 needs to be kept around, we must make a copy of
2805 PATTERN (I2), so that when we substitute I1SRC for I1DEST in
2806 PATTERN (I2), we are only substituting for the original I1DEST, not into
2807 an already-substituted copy. This also prevents making self-referential
2808 rtx. If I2 is a PARALLEL, we just need the piece that assigns I2SRC to
2813 if (GET_CODE (PATTERN (i2)) == PARALLEL)
2814 i2pat = gen_rtx_SET (VOIDmode, i2dest, copy_rtx (i2src));
2816 i2pat = copy_rtx (PATTERN (i2));
2821 if (GET_CODE (PATTERN (i1)) == PARALLEL)
2822 i1pat = gen_rtx_SET (VOIDmode, i1dest, copy_rtx (i1src));
2824 i1pat = copy_rtx (PATTERN (i1));
2829 /* Substitute in the latest insn for the regs set by the earlier ones. */
2831 maxreg = max_reg_num ();
2836 /* Many machines that don't use CC0 have insns that can both perform an
2837 arithmetic operation and set the condition code. These operations will
2838 be represented as a PARALLEL with the first element of the vector
2839 being a COMPARE of an arithmetic operation with the constant zero.
2840 The second element of the vector will set some pseudo to the result
2841 of the same arithmetic operation. If we simplify the COMPARE, we won't
2842 match such a pattern and so will generate an extra insn. Here we test
2843 for this case, where both the comparison and the operation result are
2844 needed, and make the PARALLEL by just replacing I2DEST in I3SRC with
2845 I2SRC. Later we will make the PARALLEL that contains I2. */
2847 if (i1 == 0 && added_sets_2 && GET_CODE (PATTERN (i3)) == SET
2848 && GET_CODE (SET_SRC (PATTERN (i3))) == COMPARE
2849 && XEXP (SET_SRC (PATTERN (i3)), 1) == const0_rtx
2850 && rtx_equal_p (XEXP (SET_SRC (PATTERN (i3)), 0), i2dest))
2852 #ifdef SELECT_CC_MODE
2854 enum machine_mode compare_mode;
2857 newpat = PATTERN (i3);
2858 SUBST (XEXP (SET_SRC (newpat), 0), i2src);
2862 #ifdef SELECT_CC_MODE
2863 /* See if a COMPARE with the operand we substituted in should be done
2864 with the mode that is currently being used. If not, do the same
2865 processing we do in `subst' for a SET; namely, if the destination
2866 is used only once, try to replace it with a register of the proper
2867 mode and also replace the COMPARE. */
2868 if (undobuf.other_insn == 0
2869 && (cc_use = find_single_use (SET_DEST (newpat), i3,
2870 &undobuf.other_insn))
2871 && ((compare_mode = SELECT_CC_MODE (GET_CODE (*cc_use),
2873 != GET_MODE (SET_DEST (newpat))))
2875 if (can_change_dest_mode(SET_DEST (newpat), added_sets_2,
2878 unsigned int regno = REGNO (SET_DEST (newpat));
2881 if (regno < FIRST_PSEUDO_REGISTER)
2882 new_dest = gen_rtx_REG (compare_mode, regno);
2885 SUBST_MODE (regno_reg_rtx[regno], compare_mode);
2886 new_dest = regno_reg_rtx[regno];
2889 SUBST (SET_DEST (newpat), new_dest);
2890 SUBST (XEXP (*cc_use, 0), new_dest);
2891 SUBST (SET_SRC (newpat),
2892 gen_rtx_COMPARE (compare_mode, i2src, const0_rtx));
2895 undobuf.other_insn = 0;
2902 /* It is possible that the source of I2 or I1 may be performing
2903 an unneeded operation, such as a ZERO_EXTEND of something
2904 that is known to have the high part zero. Handle that case
2905 by letting subst look at the innermost one of them.
2907 Another way to do this would be to have a function that tries
2908 to simplify a single insn instead of merging two or more
2909 insns. We don't do this because of the potential of infinite
2910 loops and because of the potential extra memory required.
2911 However, doing it the way we are is a bit of a kludge and
2912 doesn't catch all cases.
2914 But only do this if -fexpensive-optimizations since it slows
2915 things down and doesn't usually win.
2917 This is not done in the COMPARE case above because the
2918 unmodified I2PAT is used in the PARALLEL and so a pattern
2919 with a modified I2SRC would not match. */
2921 if (flag_expensive_optimizations)
2923 /* Pass pc_rtx so no substitutions are done, just
2927 subst_low_luid = DF_INSN_LUID (i1);
2928 i1src = subst (i1src, pc_rtx, pc_rtx, 0, 0);
2932 subst_low_luid = DF_INSN_LUID (i2);
2933 i2src = subst (i2src, pc_rtx, pc_rtx, 0, 0);
2937 n_occurrences = 0; /* `subst' counts here */
2939 /* If I1 feeds into I2 (not into I3) and I1DEST is in I1SRC, we
2940 need to make a unique copy of I2SRC each time we substitute it
2941 to avoid self-referential rtl. */
2943 subst_low_luid = DF_INSN_LUID (i2);
2944 newpat = subst (PATTERN (i3), i2dest, i2src, 0,
2945 ! i1_feeds_i3 && i1dest_in_i1src);
2948 /* Record whether i2's body now appears within i3's body. */
2949 i2_is_used = n_occurrences;
2952 /* If we already got a failure, don't try to do more. Otherwise,
2953 try to substitute in I1 if we have it. */
2955 if (i1 && GET_CODE (newpat) != CLOBBER)
2957 /* Check that an autoincrement side-effect on I1 has not been lost.
2958 This happens if I1DEST is mentioned in I2 and dies there, and
2959 has disappeared from the new pattern. */
2960 if ((FIND_REG_INC_NOTE (i1, NULL_RTX) != 0
2962 && dead_or_set_p (i2, i1dest)
2963 && !reg_overlap_mentioned_p (i1dest, newpat))
2964 /* Before we can do this substitution, we must redo the test done
2965 above (see detailed comments there) that ensures that I1DEST
2966 isn't mentioned in any SETs in NEWPAT that are field assignments. */
2967 || !combinable_i3pat (NULL_RTX, &newpat, i1dest, NULL_RTX, 0, 0))
2974 subst_low_luid = DF_INSN_LUID (i1);
2975 newpat = subst (newpat, i1dest, i1src, 0, 0);
2979 /* Fail if an autoincrement side-effect has been duplicated. Be careful
2980 to count all the ways that I2SRC and I1SRC can be used. */
2981 if ((FIND_REG_INC_NOTE (i2, NULL_RTX) != 0
2982 && i2_is_used + added_sets_2 > 1)
2983 || (i1 != 0 && FIND_REG_INC_NOTE (i1, NULL_RTX) != 0
2984 && (n_occurrences + added_sets_1 + (added_sets_2 && ! i1_feeds_i3)
2986 /* Fail if we tried to make a new register. */
2987 || max_reg_num () != maxreg
2988 /* Fail if we couldn't do something and have a CLOBBER. */
2989 || GET_CODE (newpat) == CLOBBER
2990 /* Fail if this new pattern is a MULT and we didn't have one before
2991 at the outer level. */
2992 || (GET_CODE (newpat) == SET && GET_CODE (SET_SRC (newpat)) == MULT
2999 /* If the actions of the earlier insns must be kept
3000 in addition to substituting them into the latest one,
3001 we must make a new PARALLEL for the latest insn
3002 to hold additional the SETs. */
3004 if (added_sets_1 || added_sets_2)
3008 if (GET_CODE (newpat) == PARALLEL)
3010 rtvec old = XVEC (newpat, 0);
3011 total_sets = XVECLEN (newpat, 0) + added_sets_1 + added_sets_2;
3012 newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (total_sets));
3013 memcpy (XVEC (newpat, 0)->elem, &old->elem[0],
3014 sizeof (old->elem[0]) * old->num_elem);
3019 total_sets = 1 + added_sets_1 + added_sets_2;
3020 newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (total_sets));
3021 XVECEXP (newpat, 0, 0) = old;
3025 XVECEXP (newpat, 0, --total_sets) = i1pat;
3029 /* If there is no I1, use I2's body as is. We used to also not do
3030 the subst call below if I2 was substituted into I3,
3031 but that could lose a simplification. */
3033 XVECEXP (newpat, 0, --total_sets) = i2pat;
3035 /* See comment where i2pat is assigned. */
3036 XVECEXP (newpat, 0, --total_sets)
3037 = subst (i2pat, i1dest, i1src, 0, 0);
3041 /* We come here when we are replacing a destination in I2 with the
3042 destination of I3. */
3043 validate_replacement:
3045 /* Note which hard regs this insn has as inputs. */
3046 mark_used_regs_combine (newpat);
3048 /* If recog_for_combine fails, it strips existing clobbers. If we'll
3049 consider splitting this pattern, we might need these clobbers. */
3050 if (i1 && GET_CODE (newpat) == PARALLEL
3051 && GET_CODE (XVECEXP (newpat, 0, XVECLEN (newpat, 0) - 1)) == CLOBBER)
3053 int len = XVECLEN (newpat, 0);
3055 newpat_vec_with_clobbers = rtvec_alloc (len);
3056 for (i = 0; i < len; i++)
3057 RTVEC_ELT (newpat_vec_with_clobbers, i) = XVECEXP (newpat, 0, i);
3060 /* Is the result of combination a valid instruction? */
3061 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
3063 /* If the result isn't valid, see if it is a PARALLEL of two SETs where
3064 the second SET's destination is a register that is unused and isn't
3065 marked as an instruction that might trap in an EH region. In that case,
3066 we just need the first SET. This can occur when simplifying a divmod
3067 insn. We *must* test for this case here because the code below that
3068 splits two independent SETs doesn't handle this case correctly when it
3069 updates the register status.
3071 It's pointless doing this if we originally had two sets, one from
3072 i3, and one from i2. Combining then splitting the parallel results
3073 in the original i2 again plus an invalid insn (which we delete).
3074 The net effect is only to move instructions around, which makes
3075 debug info less accurate.
3077 Also check the case where the first SET's destination is unused.
3078 That would not cause incorrect code, but does cause an unneeded
3081 if (insn_code_number < 0
3082 && !(added_sets_2 && i1 == 0)
3083 && GET_CODE (newpat) == PARALLEL
3084 && XVECLEN (newpat, 0) == 2
3085 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
3086 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
3087 && asm_noperands (newpat) < 0)
3089 rtx set0 = XVECEXP (newpat, 0, 0);
3090 rtx set1 = XVECEXP (newpat, 0, 1);
3092 if (((REG_P (SET_DEST (set1))
3093 && find_reg_note (i3, REG_UNUSED, SET_DEST (set1)))
3094 || (GET_CODE (SET_DEST (set1)) == SUBREG
3095 && find_reg_note (i3, REG_UNUSED, SUBREG_REG (SET_DEST (set1)))))
3096 && insn_nothrow_p (i3)
3097 && !side_effects_p (SET_SRC (set1)))
3100 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
3103 else if (((REG_P (SET_DEST (set0))
3104 && find_reg_note (i3, REG_UNUSED, SET_DEST (set0)))
3105 || (GET_CODE (SET_DEST (set0)) == SUBREG
3106 && find_reg_note (i3, REG_UNUSED,
3107 SUBREG_REG (SET_DEST (set0)))))
3108 && insn_nothrow_p (i3)
3109 && !side_effects_p (SET_SRC (set0)))
3112 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
3114 if (insn_code_number >= 0)
3115 changed_i3_dest = 1;
3119 /* If we were combining three insns and the result is a simple SET
3120 with no ASM_OPERANDS that wasn't recognized, try to split it into two
3121 insns. There are two ways to do this. It can be split using a
3122 machine-specific method (like when you have an addition of a large
3123 constant) or by combine in the function find_split_point. */
3125 if (i1 && insn_code_number < 0 && GET_CODE (newpat) == SET
3126 && asm_noperands (newpat) < 0)
3128 rtx parallel, m_split, *split;
3130 /* See if the MD file can split NEWPAT. If it can't, see if letting it
3131 use I2DEST as a scratch register will help. In the latter case,
3132 convert I2DEST to the mode of the source of NEWPAT if we can. */
3134 m_split = combine_split_insns (newpat, i3);
3136 /* We can only use I2DEST as a scratch reg if it doesn't overlap any
3137 inputs of NEWPAT. */
3139 /* ??? If I2DEST is not safe, and I1DEST exists, then it would be
3140 possible to try that as a scratch reg. This would require adding
3141 more code to make it work though. */
3143 if (m_split == 0 && ! reg_overlap_mentioned_p (i2dest, newpat))
3145 enum machine_mode new_mode = GET_MODE (SET_DEST (newpat));
3147 /* First try to split using the original register as a
3148 scratch register. */
3149 parallel = gen_rtx_PARALLEL (VOIDmode,
3150 gen_rtvec (2, newpat,
3151 gen_rtx_CLOBBER (VOIDmode,
3153 m_split = combine_split_insns (parallel, i3);
3155 /* If that didn't work, try changing the mode of I2DEST if
3158 && new_mode != GET_MODE (i2dest)
3159 && new_mode != VOIDmode
3160 && can_change_dest_mode (i2dest, added_sets_2, new_mode))
3162 enum machine_mode old_mode = GET_MODE (i2dest);
3165 if (REGNO (i2dest) < FIRST_PSEUDO_REGISTER)
3166 ni2dest = gen_rtx_REG (new_mode, REGNO (i2dest));
3169 SUBST_MODE (regno_reg_rtx[REGNO (i2dest)], new_mode);
3170 ni2dest = regno_reg_rtx[REGNO (i2dest)];
3173 parallel = (gen_rtx_PARALLEL
3175 gen_rtvec (2, newpat,
3176 gen_rtx_CLOBBER (VOIDmode,
3178 m_split = combine_split_insns (parallel, i3);
3181 && REGNO (i2dest) >= FIRST_PSEUDO_REGISTER)
3185 adjust_reg_mode (regno_reg_rtx[REGNO (i2dest)], old_mode);
3186 buf = undobuf.undos;
3187 undobuf.undos = buf->next;
3188 buf->next = undobuf.frees;
3189 undobuf.frees = buf;
3193 i2scratch = m_split != 0;
3196 /* If recog_for_combine has discarded clobbers, try to use them
3197 again for the split. */
3198 if (m_split == 0 && newpat_vec_with_clobbers)
3200 parallel = gen_rtx_PARALLEL (VOIDmode, newpat_vec_with_clobbers);
3201 m_split = combine_split_insns (parallel, i3);
3204 if (m_split && NEXT_INSN (m_split) == NULL_RTX)
3206 m_split = PATTERN (m_split);
3207 insn_code_number = recog_for_combine (&m_split, i3, &new_i3_notes);
3208 if (insn_code_number >= 0)
3211 else if (m_split && NEXT_INSN (NEXT_INSN (m_split)) == NULL_RTX
3212 && (next_real_insn (i2) == i3
3213 || ! use_crosses_set_p (PATTERN (m_split), DF_INSN_LUID (i2))))
3216 rtx newi3pat = PATTERN (NEXT_INSN (m_split));
3217 newi2pat = PATTERN (m_split);
3219 i3set = single_set (NEXT_INSN (m_split));
3220 i2set = single_set (m_split);
3222 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
3224 /* If I2 or I3 has multiple SETs, we won't know how to track
3225 register status, so don't use these insns. If I2's destination
3226 is used between I2 and I3, we also can't use these insns. */
3228 if (i2_code_number >= 0 && i2set && i3set
3229 && (next_real_insn (i2) == i3
3230 || ! reg_used_between_p (SET_DEST (i2set), i2, i3)))
3231 insn_code_number = recog_for_combine (&newi3pat, i3,
3233 if (insn_code_number >= 0)
3236 /* It is possible that both insns now set the destination of I3.
3237 If so, we must show an extra use of it. */
3239 if (insn_code_number >= 0)
3241 rtx new_i3_dest = SET_DEST (i3set);
3242 rtx new_i2_dest = SET_DEST (i2set);
3244 while (GET_CODE (new_i3_dest) == ZERO_EXTRACT
3245 || GET_CODE (new_i3_dest) == STRICT_LOW_PART
3246 || GET_CODE (new_i3_dest) == SUBREG)
3247 new_i3_dest = XEXP (new_i3_dest, 0);
3249 while (GET_CODE (new_i2_dest) == ZERO_EXTRACT
3250 || GET_CODE (new_i2_dest) == STRICT_LOW_PART
3251 || GET_CODE (new_i2_dest) == SUBREG)
3252 new_i2_dest = XEXP (new_i2_dest, 0);
3254 if (REG_P (new_i3_dest)
3255 && REG_P (new_i2_dest)
3256 && REGNO (new_i3_dest) == REGNO (new_i2_dest))
3257 INC_REG_N_SETS (REGNO (new_i2_dest), 1);
3261 /* If we can split it and use I2DEST, go ahead and see if that
3262 helps things be recognized. Verify that none of the registers
3263 are set between I2 and I3. */
3264 if (insn_code_number < 0 && (split = find_split_point (&newpat, i3)) != 0
3268 /* We need I2DEST in the proper mode. If it is a hard register
3269 or the only use of a pseudo, we can change its mode.
3270 Make sure we don't change a hard register to have a mode that
3271 isn't valid for it, or change the number of registers. */
3272 && (GET_MODE (*split) == GET_MODE (i2dest)
3273 || GET_MODE (*split) == VOIDmode
3274 || can_change_dest_mode (i2dest, added_sets_2,
3276 && (next_real_insn (i2) == i3
3277 || ! use_crosses_set_p (*split, DF_INSN_LUID (i2)))
3278 /* We can't overwrite I2DEST if its value is still used by
3280 && ! reg_referenced_p (i2dest, newpat))
3282 rtx newdest = i2dest;
3283 enum rtx_code split_code = GET_CODE (*split);
3284 enum machine_mode split_mode = GET_MODE (*split);
3285 bool subst_done = false;
3286 newi2pat = NULL_RTX;
3290 /* Get NEWDEST as a register in the proper mode. We have already
3291 validated that we can do this. */
3292 if (GET_MODE (i2dest) != split_mode && split_mode != VOIDmode)
3294 if (REGNO (i2dest) < FIRST_PSEUDO_REGISTER)
3295 newdest = gen_rtx_REG (split_mode, REGNO (i2dest));
3298 SUBST_MODE (regno_reg_rtx[REGNO (i2dest)], split_mode);
3299 newdest = regno_reg_rtx[REGNO (i2dest)];
3303 /* If *SPLIT is a (mult FOO (const_int pow2)), convert it to
3304 an ASHIFT. This can occur if it was inside a PLUS and hence
3305 appeared to be a memory address. This is a kludge. */
3306 if (split_code == MULT
3307 && CONST_INT_P (XEXP (*split, 1))
3308 && INTVAL (XEXP (*split, 1)) > 0
3309 && (i = exact_log2 (INTVAL (XEXP (*split, 1)))) >= 0)
3311 SUBST (*split, gen_rtx_ASHIFT (split_mode,
3312 XEXP (*split, 0), GEN_INT (i)));
3313 /* Update split_code because we may not have a multiply
3315 split_code = GET_CODE (*split);
3318 #ifdef INSN_SCHEDULING
3319 /* If *SPLIT is a paradoxical SUBREG, when we split it, it should
3320 be written as a ZERO_EXTEND. */
3321 if (split_code == SUBREG && MEM_P (SUBREG_REG (*split)))
3323 #ifdef LOAD_EXTEND_OP
3324 /* Or as a SIGN_EXTEND if LOAD_EXTEND_OP says that that's
3325 what it really is. */
3326 if (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (*split)))
3328 SUBST (*split, gen_rtx_SIGN_EXTEND (split_mode,
3329 SUBREG_REG (*split)));
3332 SUBST (*split, gen_rtx_ZERO_EXTEND (split_mode,
3333 SUBREG_REG (*split)));
3337 /* Attempt to split binary operators using arithmetic identities. */
3338 if (BINARY_P (SET_SRC (newpat))
3339 && split_mode == GET_MODE (SET_SRC (newpat))
3340 && ! side_effects_p (SET_SRC (newpat)))
3342 rtx setsrc = SET_SRC (newpat);
3343 enum machine_mode mode = GET_MODE (setsrc);
3344 enum rtx_code code = GET_CODE (setsrc);
3345 rtx src_op0 = XEXP (setsrc, 0);
3346 rtx src_op1 = XEXP (setsrc, 1);
3348 /* Split "X = Y op Y" as "Z = Y; X = Z op Z". */
3349 if (rtx_equal_p (src_op0, src_op1))
3351 newi2pat = gen_rtx_SET (VOIDmode, newdest, src_op0);
3352 SUBST (XEXP (setsrc, 0), newdest);
3353 SUBST (XEXP (setsrc, 1), newdest);
3356 /* Split "((P op Q) op R) op S" where op is PLUS or MULT. */
3357 else if ((code == PLUS || code == MULT)
3358 && GET_CODE (src_op0) == code
3359 && GET_CODE (XEXP (src_op0, 0)) == code
3360 && (INTEGRAL_MODE_P (mode)
3361 || (FLOAT_MODE_P (mode)
3362 && flag_unsafe_math_optimizations)))
3364 rtx p = XEXP (XEXP (src_op0, 0), 0);
3365 rtx q = XEXP (XEXP (src_op0, 0), 1);
3366 rtx r = XEXP (src_op0, 1);
3369 /* Split both "((X op Y) op X) op Y" and
3370 "((X op Y) op Y) op X" as "T op T" where T is
3372 if ((rtx_equal_p (p,r) && rtx_equal_p (q,s))
3373 || (rtx_equal_p (p,s) && rtx_equal_p (q,r)))
3375 newi2pat = gen_rtx_SET (VOIDmode, newdest,
3377 SUBST (XEXP (setsrc, 0), newdest);
3378 SUBST (XEXP (setsrc, 1), newdest);
3381 /* Split "((X op X) op Y) op Y)" as "T op T" where
3383 else if (rtx_equal_p (p,q) && rtx_equal_p (r,s))
3385 rtx tmp = simplify_gen_binary (code, mode, p, r);
3386 newi2pat = gen_rtx_SET (VOIDmode, newdest, tmp);
3387 SUBST (XEXP (setsrc, 0), newdest);
3388 SUBST (XEXP (setsrc, 1), newdest);
3396 newi2pat = gen_rtx_SET (VOIDmode, newdest, *split);
3397 SUBST (*split, newdest);
3400 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
3402 /* recog_for_combine might have added CLOBBERs to newi2pat.
3403 Make sure NEWPAT does not depend on the clobbered regs. */
3404 if (GET_CODE (newi2pat) == PARALLEL)
3405 for (i = XVECLEN (newi2pat, 0) - 1; i >= 0; i--)
3406 if (GET_CODE (XVECEXP (newi2pat, 0, i)) == CLOBBER)
3408 rtx reg = XEXP (XVECEXP (newi2pat, 0, i), 0);
3409 if (reg_overlap_mentioned_p (reg, newpat))
3416 /* If the split point was a MULT and we didn't have one before,
3417 don't use one now. */
3418 if (i2_code_number >= 0 && ! (split_code == MULT && ! have_mult))
3419 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
3423 /* Check for a case where we loaded from memory in a narrow mode and
3424 then sign extended it, but we need both registers. In that case,
3425 we have a PARALLEL with both loads from the same memory location.
3426 We can split this into a load from memory followed by a register-register
3427 copy. This saves at least one insn, more if register allocation can
3430 We cannot do this if the destination of the first assignment is a
3431 condition code register or cc0. We eliminate this case by making sure
3432 the SET_DEST and SET_SRC have the same mode.
3434 We cannot do this if the destination of the second assignment is
3435 a register that we have already assumed is zero-extended. Similarly
3436 for a SUBREG of such a register. */
3438 else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0
3439 && GET_CODE (newpat) == PARALLEL
3440 && XVECLEN (newpat, 0) == 2
3441 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
3442 && GET_CODE (SET_SRC (XVECEXP (newpat, 0, 0))) == SIGN_EXTEND
3443 && (GET_MODE (SET_DEST (XVECEXP (newpat, 0, 0)))
3444 == GET_MODE (SET_SRC (XVECEXP (newpat, 0, 0))))
3445 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
3446 && rtx_equal_p (SET_SRC (XVECEXP (newpat, 0, 1)),
3447 XEXP (SET_SRC (XVECEXP (newpat, 0, 0)), 0))
3448 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)),
3450 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
3451 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
3452 && ! (temp = SET_DEST (XVECEXP (newpat, 0, 1)),
3454 && VEC_index (reg_stat_type, reg_stat,
3455 REGNO (temp))->nonzero_bits != 0
3456 && GET_MODE_BITSIZE (GET_MODE (temp)) < BITS_PER_WORD
3457 && GET_MODE_BITSIZE (GET_MODE (temp)) < HOST_BITS_PER_INT
3458 && (VEC_index (reg_stat_type, reg_stat,
3459 REGNO (temp))->nonzero_bits
3460 != GET_MODE_MASK (word_mode))))
3461 && ! (GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) == SUBREG
3462 && (temp = SUBREG_REG (SET_DEST (XVECEXP (newpat, 0, 1))),
3464 && VEC_index (reg_stat_type, reg_stat,
3465 REGNO (temp))->nonzero_bits != 0
3466 && GET_MODE_BITSIZE (GET_MODE (temp)) < BITS_PER_WORD
3467 && GET_MODE_BITSIZE (GET_MODE (temp)) < HOST_BITS_PER_INT
3468 && (VEC_index (reg_stat_type, reg_stat,
3469 REGNO (temp))->nonzero_bits
3470 != GET_MODE_MASK (word_mode)))))
3471 && ! reg_overlap_mentioned_p (SET_DEST (XVECEXP (newpat, 0, 1)),
3472 SET_SRC (XVECEXP (newpat, 0, 1)))
3473 && ! find_reg_note (i3, REG_UNUSED,
3474 SET_DEST (XVECEXP (newpat, 0, 0))))
3478 newi2pat = XVECEXP (newpat, 0, 0);
3479 ni2dest = SET_DEST (XVECEXP (newpat, 0, 0));
3480 newpat = XVECEXP (newpat, 0, 1);
3481 SUBST (SET_SRC (newpat),
3482 gen_lowpart (GET_MODE (SET_SRC (newpat)), ni2dest));
3483 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
3485 if (i2_code_number >= 0)
3486 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
3488 if (insn_code_number >= 0)
3492 /* Similarly, check for a case where we have a PARALLEL of two independent
3493 SETs but we started with three insns. In this case, we can do the sets
3494 as two separate insns. This case occurs when some SET allows two
3495 other insns to combine, but the destination of that SET is still live. */
3497 else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0
3498 && GET_CODE (newpat) == PARALLEL
3499 && XVECLEN (newpat, 0) == 2
3500 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
3501 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != ZERO_EXTRACT
3502 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != STRICT_LOW_PART
3503 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
3504 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
3505 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
3506 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)),
3508 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 1)),
3509 XVECEXP (newpat, 0, 0))
3510 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 0)),
3511 XVECEXP (newpat, 0, 1))
3512 && ! (contains_muldiv (SET_SRC (XVECEXP (newpat, 0, 0)))
3513 && contains_muldiv (SET_SRC (XVECEXP (newpat, 0, 1))))
3515 /* We cannot split the parallel into two sets if both sets
3517 && ! (reg_referenced_p (cc0_rtx, XVECEXP (newpat, 0, 0))
3518 && reg_referenced_p (cc0_rtx, XVECEXP (newpat, 0, 1)))
3522 /* Normally, it doesn't matter which of the two is done first,
3523 but it does if one references cc0. In that case, it has to
3526 if (reg_referenced_p (cc0_rtx, XVECEXP (newpat, 0, 0)))
3528 newi2pat = XVECEXP (newpat, 0, 0);
3529 newpat = XVECEXP (newpat, 0, 1);
3534 newi2pat = XVECEXP (newpat, 0, 1);
3535 newpat = XVECEXP (newpat, 0, 0);
3538 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
3540 if (i2_code_number >= 0)
3541 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
3544 /* If it still isn't recognized, fail and change things back the way they
3546 if ((insn_code_number < 0
3547 /* Is the result a reasonable ASM_OPERANDS? */
3548 && (! check_asm_operands (newpat) || added_sets_1 || added_sets_2)))
3554 /* If we had to change another insn, make sure it is valid also. */
3555 if (undobuf.other_insn)
3557 CLEAR_HARD_REG_SET (newpat_used_regs);
3559 other_pat = PATTERN (undobuf.other_insn);
3560 other_code_number = recog_for_combine (&other_pat, undobuf.other_insn,
3563 if (other_code_number < 0 && ! check_asm_operands (other_pat))
3571 /* If I2 is the CC0 setter and I3 is the CC0 user then check whether
3572 they are adjacent to each other or not. */
3574 rtx p = prev_nonnote_insn (i3);
3575 if (p && p != i2 && NONJUMP_INSN_P (p) && newi2pat
3576 && sets_cc0_p (newi2pat))
3584 /* Only allow this combination if insn_rtx_costs reports that the
3585 replacement instructions are cheaper than the originals. */
3586 if (!combine_validate_cost (i1, i2, i3, newpat, newi2pat, other_pat))
3592 if (MAY_HAVE_DEBUG_INSNS)
3596 for (undo = undobuf.undos; undo; undo = undo->next)
3597 if (undo->kind == UNDO_MODE)
3599 rtx reg = *undo->where.r;
3600 enum machine_mode new_mode = GET_MODE (reg);
3601 enum machine_mode old_mode = undo->old_contents.m;
3603 /* Temporarily revert mode back. */
3604 adjust_reg_mode (reg, old_mode);
3606 if (reg == i2dest && i2scratch)
3608 /* If we used i2dest as a scratch register with a
3609 different mode, substitute it for the original
3610 i2src while its original mode is temporarily
3611 restored, and then clear i2scratch so that we don't
3612 do it again later. */
3613 propagate_for_debug (i2, i3, reg, i2src, false);
3615 /* Put back the new mode. */
3616 adjust_reg_mode (reg, new_mode);
3620 rtx tempreg = gen_raw_REG (old_mode, REGNO (reg));
3631 last = undobuf.other_insn;
3635 /* We're dealing with a reg that changed mode but not
3636 meaning, so we want to turn it into a subreg for
3637 the new mode. However, because of REG sharing and
3638 because its mode had already changed, we have to do
3639 it in two steps. First, replace any debug uses of
3640 reg, with its original mode temporarily restored,
3641 with this copy we have created; then, replace the
3642 copy with the SUBREG of the original shared reg,
3643 once again changed to the new mode. */
3644 propagate_for_debug (first, last, reg, tempreg, false);
3645 adjust_reg_mode (reg, new_mode);
3646 propagate_for_debug (first, last, tempreg,
3647 lowpart_subreg (old_mode, reg, new_mode),
3653 /* If we will be able to accept this, we have made a
3654 change to the destination of I3. This requires us to
3655 do a few adjustments. */
3657 if (changed_i3_dest)
3659 PATTERN (i3) = newpat;
3660 adjust_for_new_dest (i3);
3663 /* We now know that we can do this combination. Merge the insns and
3664 update the status of registers and LOG_LINKS. */
3666 if (undobuf.other_insn)
3670 PATTERN (undobuf.other_insn) = other_pat;
3672 /* If any of the notes in OTHER_INSN were REG_UNUSED, ensure that they
3673 are still valid. Then add any non-duplicate notes added by
3674 recog_for_combine. */
3675 for (note = REG_NOTES (undobuf.other_insn); note; note = next)
3677 next = XEXP (note, 1);
3679 if (REG_NOTE_KIND (note) == REG_UNUSED
3680 && ! reg_set_p (XEXP (note, 0), PATTERN (undobuf.other_insn)))
3681 remove_note (undobuf.other_insn, note);
3684 distribute_notes (new_other_notes, undobuf.other_insn,
3685 undobuf.other_insn, NULL_RTX, NULL_RTX, NULL_RTX);
3694 /* I3 now uses what used to be its destination and which is now
3695 I2's destination. This requires us to do a few adjustments. */
3696 PATTERN (i3) = newpat;
3697 adjust_for_new_dest (i3);
3699 /* We need a LOG_LINK from I3 to I2. But we used to have one,
3702 However, some later insn might be using I2's dest and have
3703 a LOG_LINK pointing at I3. We must remove this link.
3704 The simplest way to remove the link is to point it at I1,
3705 which we know will be a NOTE. */
3707 /* newi2pat is usually a SET here; however, recog_for_combine might
3708 have added some clobbers. */
3709 if (GET_CODE (newi2pat) == PARALLEL)
3710 ni2dest = SET_DEST (XVECEXP (newi2pat, 0, 0));
3712 ni2dest = SET_DEST (newi2pat);
3714 for (insn = NEXT_INSN (i3);
3715 insn && (this_basic_block->next_bb == EXIT_BLOCK_PTR
3716 || insn != BB_HEAD (this_basic_block->next_bb));
3717 insn = NEXT_INSN (insn))
3719 if (INSN_P (insn) && reg_referenced_p (ni2dest, PATTERN (insn)))
3721 for (link = LOG_LINKS (insn); link;
3722 link = XEXP (link, 1))
3723 if (XEXP (link, 0) == i3)
3724 XEXP (link, 0) = i1;
3732 rtx i3notes, i2notes, i1notes = 0;
3733 rtx i3links, i2links, i1links = 0;
3736 /* Compute which registers we expect to eliminate. newi2pat may be setting
3737 either i3dest or i2dest, so we must check it. Also, i1dest may be the
3738 same as i3dest, in which case newi2pat may be setting i1dest. */
3739 rtx elim_i2 = ((newi2pat && reg_set_p (i2dest, newi2pat))
3740 || i2dest_in_i2src || i2dest_in_i1src
3743 rtx elim_i1 = (i1 == 0 || i1dest_in_i1src
3744 || (newi2pat && reg_set_p (i1dest, newi2pat))
3748 /* Get the old REG_NOTES and LOG_LINKS from all our insns and
3750 i3notes = REG_NOTES (i3), i3links = LOG_LINKS (i3);
3751 i2notes = REG_NOTES (i2), i2links = LOG_LINKS (i2);
3753 i1notes = REG_NOTES (i1), i1links = LOG_LINKS (i1);
3755 /* Ensure that we do not have something that should not be shared but
3756 occurs multiple times in the new insns. Check this by first
3757 resetting all the `used' flags and then copying anything is shared. */
3759 reset_used_flags (i3notes);
3760 reset_used_flags (i2notes);
3761 reset_used_flags (i1notes);
3762 reset_used_flags (newpat);
3763 reset_used_flags (newi2pat);
3764 if (undobuf.other_insn)
3765 reset_used_flags (PATTERN (undobuf.other_insn));
3767 i3notes = copy_rtx_if_shared (i3notes);
3768 i2notes = copy_rtx_if_shared (i2notes);
3769 i1notes = copy_rtx_if_shared (i1notes);
3770 newpat = copy_rtx_if_shared (newpat);
3771 newi2pat = copy_rtx_if_shared (newi2pat);
3772 if (undobuf.other_insn)
3773 reset_used_flags (PATTERN (undobuf.other_insn));
3775 INSN_CODE (i3) = insn_code_number;
3776 PATTERN (i3) = newpat;
3778 if (CALL_P (i3) && CALL_INSN_FUNCTION_USAGE (i3))
3780 rtx call_usage = CALL_INSN_FUNCTION_USAGE (i3);
3782 reset_used_flags (call_usage);
3783 call_usage = copy_rtx (call_usage);
3786 replace_rtx (call_usage, i2dest, i2src);
3789 replace_rtx (call_usage, i1dest, i1src);
3791 CALL_INSN_FUNCTION_USAGE (i3) = call_usage;
3794 if (undobuf.other_insn)
3795 INSN_CODE (undobuf.other_insn) = other_code_number;
3797 /* We had one special case above where I2 had more than one set and
3798 we replaced a destination of one of those sets with the destination
3799 of I3. In that case, we have to update LOG_LINKS of insns later
3800 in this basic block. Note that this (expensive) case is rare.
3802 Also, in this case, we must pretend that all REG_NOTEs for I2
3803 actually came from I3, so that REG_UNUSED notes from I2 will be
3804 properly handled. */
3806 if (i3_subst_into_i2)
3808 for (i = 0; i < XVECLEN (PATTERN (i2), 0); i++)
3809 if ((GET_CODE (XVECEXP (PATTERN (i2), 0, i)) == SET
3810 || GET_CODE (XVECEXP (PATTERN (i2), 0, i)) == CLOBBER)
3811 && REG_P (SET_DEST (XVECEXP (PATTERN (i2), 0, i)))
3812 && SET_DEST (XVECEXP (PATTERN (i2), 0, i)) != i2dest
3813 && ! find_reg_note (i2, REG_UNUSED,
3814 SET_DEST (XVECEXP (PATTERN (i2), 0, i))))
3815 for (temp = NEXT_INSN (i2);
3816 temp && (this_basic_block->next_bb == EXIT_BLOCK_PTR
3817 || BB_HEAD (this_basic_block) != temp);
3818 temp = NEXT_INSN (temp))
3819 if (temp != i3 && INSN_P (temp))
3820 for (link = LOG_LINKS (temp); link; link = XEXP (link, 1))
3821 if (XEXP (link, 0) == i2)
3822 XEXP (link, 0) = i3;
3827 while (XEXP (link, 1))
3828 link = XEXP (link, 1);
3829 XEXP (link, 1) = i2notes;
3843 if (MAY_HAVE_DEBUG_INSNS && i2scratch)
3844 propagate_for_debug (i2, i3, i2dest, i2src, false);
3845 INSN_CODE (i2) = i2_code_number;
3846 PATTERN (i2) = newi2pat;
3850 if (MAY_HAVE_DEBUG_INSNS && i2src)
3851 propagate_for_debug (i2, i3, i2dest, i2src, i3_subst_into_i2);
3852 SET_INSN_DELETED (i2);
3859 if (MAY_HAVE_DEBUG_INSNS)
3860 propagate_for_debug (i1, i3, i1dest, i1src, false);
3861 SET_INSN_DELETED (i1);
3864 /* Get death notes for everything that is now used in either I3 or
3865 I2 and used to die in a previous insn. If we built two new
3866 patterns, move from I1 to I2 then I2 to I3 so that we get the
3867 proper movement on registers that I2 modifies. */
3871 move_deaths (newi2pat, NULL_RTX, DF_INSN_LUID (i1), i2, &midnotes);
3872 move_deaths (newpat, newi2pat, DF_INSN_LUID (i1), i3, &midnotes);
3875 move_deaths (newpat, NULL_RTX, i1 ? DF_INSN_LUID (i1) : DF_INSN_LUID (i2),
3878 /* Distribute all the LOG_LINKS and REG_NOTES from I1, I2, and I3. */
3880 distribute_notes (i3notes, i3, i3, newi2pat ? i2 : NULL_RTX,
3883 distribute_notes (i2notes, i2, i3, newi2pat ? i2 : NULL_RTX,
3886 distribute_notes (i1notes, i1, i3, newi2pat ? i2 : NULL_RTX,
3889 distribute_notes (midnotes, NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
3892 /* Distribute any notes added to I2 or I3 by recog_for_combine. We
3893 know these are REG_UNUSED and want them to go to the desired insn,
3894 so we always pass it as i3. */
3896 if (newi2pat && new_i2_notes)
3897 distribute_notes (new_i2_notes, i2, i2, NULL_RTX, NULL_RTX, NULL_RTX);
3900 distribute_notes (new_i3_notes, i3, i3, NULL_RTX, NULL_RTX, NULL_RTX);
3902 /* If I3DEST was used in I3SRC, it really died in I3. We may need to
3903 put a REG_DEAD note for it somewhere. If NEWI2PAT exists and sets
3904 I3DEST, the death must be somewhere before I2, not I3. If we passed I3
3905 in that case, it might delete I2. Similarly for I2 and I1.
3906 Show an additional death due to the REG_DEAD note we make here. If
3907 we discard it in distribute_notes, we will decrement it again. */
3911 if (newi2pat && reg_set_p (i3dest_killed, newi2pat))
3912 distribute_notes (alloc_reg_note (REG_DEAD, i3dest_killed,
3914 NULL_RTX, i2, NULL_RTX, elim_i2, elim_i1);
3916 distribute_notes (alloc_reg_note (REG_DEAD, i3dest_killed,
3918 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
3922 if (i2dest_in_i2src)
3924 if (newi2pat && reg_set_p (i2dest, newi2pat))
3925 distribute_notes (alloc_reg_note (REG_DEAD, i2dest, NULL_RTX),
3926 NULL_RTX, i2, NULL_RTX, NULL_RTX, NULL_RTX);
3928 distribute_notes (alloc_reg_note (REG_DEAD, i2dest, NULL_RTX),
3929 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
3930 NULL_RTX, NULL_RTX);
3933 if (i1dest_in_i1src)
3935 if (newi2pat && reg_set_p (i1dest, newi2pat))
3936 distribute_notes (alloc_reg_note (REG_DEAD, i1dest, NULL_RTX),
3937 NULL_RTX, i2, NULL_RTX, NULL_RTX, NULL_RTX);
3939 distribute_notes (alloc_reg_note (REG_DEAD, i1dest, NULL_RTX),
3940 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
3941 NULL_RTX, NULL_RTX);
3944 distribute_links (i3links);
3945 distribute_links (i2links);
3946 distribute_links (i1links);
3951 rtx i2_insn = 0, i2_val = 0, set;
3953 /* The insn that used to set this register doesn't exist, and
3954 this life of the register may not exist either. See if one of
3955 I3's links points to an insn that sets I2DEST. If it does,
3956 that is now the last known value for I2DEST. If we don't update
3957 this and I2 set the register to a value that depended on its old
3958 contents, we will get confused. If this insn is used, thing
3959 will be set correctly in combine_instructions. */
3961 for (link = LOG_LINKS (i3); link; link = XEXP (link, 1))
3962 if ((set = single_set (XEXP (link, 0))) != 0
3963 && rtx_equal_p (i2dest, SET_DEST (set)))
3964 i2_insn = XEXP (link, 0), i2_val = SET_SRC (set);
3966 record_value_for_reg (i2dest, i2_insn, i2_val);
3968 /* If the reg formerly set in I2 died only once and that was in I3,
3969 zero its use count so it won't make `reload' do any work. */
3971 && (newi2pat == 0 || ! reg_mentioned_p (i2dest, newi2pat))
3972 && ! i2dest_in_i2src)
3974 regno = REGNO (i2dest);
3975 INC_REG_N_SETS (regno, -1);
3979 if (i1 && REG_P (i1dest))
3982 rtx i1_insn = 0, i1_val = 0, set;
3984 for (link = LOG_LINKS (i3); link; link = XEXP (link, 1))
3985 if ((set = single_set (XEXP (link, 0))) != 0
3986 && rtx_equal_p (i1dest, SET_DEST (set)))
3987 i1_insn = XEXP (link, 0), i1_val = SET_SRC (set);
3989 record_value_for_reg (i1dest, i1_insn, i1_val);
3991 regno = REGNO (i1dest);
3992 if (! added_sets_1 && ! i1dest_in_i1src)
3993 INC_REG_N_SETS (regno, -1);
3996 /* Update reg_stat[].nonzero_bits et al for any changes that may have
3997 been made to this insn. The order of
3998 set_nonzero_bits_and_sign_copies() is important. Because newi2pat
3999 can affect nonzero_bits of newpat */
4001 note_stores (newi2pat, set_nonzero_bits_and_sign_copies, NULL);
4002 note_stores (newpat, set_nonzero_bits_and_sign_copies, NULL);
4005 if (undobuf.other_insn != NULL_RTX)
4009 fprintf (dump_file, "modifying other_insn ");
4010 dump_insn_slim (dump_file, undobuf.other_insn);
4012 df_insn_rescan (undobuf.other_insn);
4015 if (i1 && !(NOTE_P(i1) && (NOTE_KIND (i1) == NOTE_INSN_DELETED)))
4019 fprintf (dump_file, "modifying insn i1 ");
4020 dump_insn_slim (dump_file, i1);
4022 df_insn_rescan (i1);
4025 if (i2 && !(NOTE_P(i2) && (NOTE_KIND (i2) == NOTE_INSN_DELETED)))
4029 fprintf (dump_file, "modifying insn i2 ");
4030 dump_insn_slim (dump_file, i2);
4032 df_insn_rescan (i2);
4035 if (i3 && !(NOTE_P(i3) && (NOTE_KIND (i3) == NOTE_INSN_DELETED)))
4039 fprintf (dump_file, "modifying insn i3 ");
4040 dump_insn_slim (dump_file, i3);
4042 df_insn_rescan (i3);
4045 /* Set new_direct_jump_p if a new return or simple jump instruction
4046 has been created. Adjust the CFG accordingly. */
4048 if (returnjump_p (i3) || any_uncondjump_p (i3))
4050 *new_direct_jump_p = 1;
4051 mark_jump_label (PATTERN (i3), i3, 0);
4052 update_cfg_for_uncondjump (i3);
4055 if (undobuf.other_insn != NULL_RTX
4056 && (returnjump_p (undobuf.other_insn)
4057 || any_uncondjump_p (undobuf.other_insn)))
4059 *new_direct_jump_p = 1;
4060 update_cfg_for_uncondjump (undobuf.other_insn);
4063 /* A noop might also need cleaning up of CFG, if it comes from the
4064 simplification of a jump. */
4065 if (GET_CODE (newpat) == SET
4066 && SET_SRC (newpat) == pc_rtx
4067 && SET_DEST (newpat) == pc_rtx)
4069 *new_direct_jump_p = 1;
4070 update_cfg_for_uncondjump (i3);
4073 combine_successes++;
4076 if (added_links_insn
4077 && (newi2pat == 0 || DF_INSN_LUID (added_links_insn) < DF_INSN_LUID (i2))
4078 && DF_INSN_LUID (added_links_insn) < DF_INSN_LUID (i3))
4079 return added_links_insn;
4081 return newi2pat ? i2 : i3;
4084 /* Undo all the modifications recorded in undobuf. */
4089 struct undo *undo, *next;
4091 for (undo = undobuf.undos; undo; undo = next)
4097 *undo->where.r = undo->old_contents.r;
4100 *undo->where.i = undo->old_contents.i;
4103 adjust_reg_mode (*undo->where.r, undo->old_contents.m);
4109 undo->next = undobuf.frees;
4110 undobuf.frees = undo;
4116 /* We've committed to accepting the changes we made. Move all
4117 of the undos to the free list. */
4122 struct undo *undo, *next;
4124 for (undo = undobuf.undos; undo; undo = next)
4127 undo->next = undobuf.frees;
4128 undobuf.frees = undo;
4133 /* Find the innermost point within the rtx at LOC, possibly LOC itself,
4134 where we have an arithmetic expression and return that point. LOC will
4137 try_combine will call this function to see if an insn can be split into
4141 find_split_point (rtx *loc, rtx insn)
4144 enum rtx_code code = GET_CODE (x);
4146 unsigned HOST_WIDE_INT len = 0;
4147 HOST_WIDE_INT pos = 0;
4149 rtx inner = NULL_RTX;
4151 /* First special-case some codes. */
4155 #ifdef INSN_SCHEDULING
4156 /* If we are making a paradoxical SUBREG invalid, it becomes a split
4158 if (MEM_P (SUBREG_REG (x)))
4161 return find_split_point (&SUBREG_REG (x), insn);
4165 /* If we have (mem (const ..)) or (mem (symbol_ref ...)), split it
4166 using LO_SUM and HIGH. */
4167 if (GET_CODE (XEXP (x, 0)) == CONST
4168 || GET_CODE (XEXP (x, 0)) == SYMBOL_REF)
4170 enum machine_mode address_mode
4171 = targetm.addr_space.address_mode (MEM_ADDR_SPACE (x));
4174 gen_rtx_LO_SUM (address_mode,
4175 gen_rtx_HIGH (address_mode, XEXP (x, 0)),
4177 return &XEXP (XEXP (x, 0), 0);
4181 /* If we have a PLUS whose second operand is a constant and the
4182 address is not valid, perhaps will can split it up using
4183 the machine-specific way to split large constants. We use
4184 the first pseudo-reg (one of the virtual regs) as a placeholder;
4185 it will not remain in the result. */
4186 if (GET_CODE (XEXP (x, 0)) == PLUS
4187 && CONST_INT_P (XEXP (XEXP (x, 0), 1))
4188 && ! memory_address_addr_space_p (GET_MODE (x), XEXP (x, 0),
4189 MEM_ADDR_SPACE (x)))
4191 rtx reg = regno_reg_rtx[FIRST_PSEUDO_REGISTER];
4192 rtx seq = combine_split_insns (gen_rtx_SET (VOIDmode, reg,
4196 /* This should have produced two insns, each of which sets our
4197 placeholder. If the source of the second is a valid address,
4198 we can make put both sources together and make a split point
4202 && NEXT_INSN (seq) != NULL_RTX
4203 && NEXT_INSN (NEXT_INSN (seq)) == NULL_RTX
4204 && NONJUMP_INSN_P (seq)
4205 && GET_CODE (PATTERN (seq)) == SET
4206 && SET_DEST (PATTERN (seq)) == reg
4207 && ! reg_mentioned_p (reg,
4208 SET_SRC (PATTERN (seq)))
4209 && NONJUMP_INSN_P (NEXT_INSN (seq))
4210 && GET_CODE (PATTERN (NEXT_INSN (seq))) == SET
4211 && SET_DEST (PATTERN (NEXT_INSN (seq))) == reg
4212 && memory_address_addr_space_p
4213 (GET_MODE (x), SET_SRC (PATTERN (NEXT_INSN (seq))),
4214 MEM_ADDR_SPACE (x)))
4216 rtx src1 = SET_SRC (PATTERN (seq));
4217 rtx src2 = SET_SRC (PATTERN (NEXT_INSN (seq)));
4219 /* Replace the placeholder in SRC2 with SRC1. If we can
4220 find where in SRC2 it was placed, that can become our
4221 split point and we can replace this address with SRC2.
4222 Just try two obvious places. */
4224 src2 = replace_rtx (src2, reg, src1);
4226 if (XEXP (src2, 0) == src1)
4227 split = &XEXP (src2, 0);
4228 else if (GET_RTX_FORMAT (GET_CODE (XEXP (src2, 0)))[0] == 'e'
4229 && XEXP (XEXP (src2, 0), 0) == src1)
4230 split = &XEXP (XEXP (src2, 0), 0);
4234 SUBST (XEXP (x, 0), src2);
4239 /* If that didn't work, perhaps the first operand is complex and
4240 needs to be computed separately, so make a split point there.
4241 This will occur on machines that just support REG + CONST
4242 and have a constant moved through some previous computation. */
4244 else if (!OBJECT_P (XEXP (XEXP (x, 0), 0))
4245 && ! (GET_CODE (XEXP (XEXP (x, 0), 0)) == SUBREG
4246 && OBJECT_P (SUBREG_REG (XEXP (XEXP (x, 0), 0)))))
4247 return &XEXP (XEXP (x, 0), 0);
4250 /* If we have a PLUS whose first operand is complex, try computing it
4251 separately by making a split there. */
4252 if (GET_CODE (XEXP (x, 0)) == PLUS
4253 && ! memory_address_addr_space_p (GET_MODE (x), XEXP (x, 0),
4255 && ! OBJECT_P (XEXP (XEXP (x, 0), 0))
4256 && ! (GET_CODE (XEXP (XEXP (x, 0), 0)) == SUBREG
4257 && OBJECT_P (SUBREG_REG (XEXP (XEXP (x, 0), 0)))))
4258 return &XEXP (XEXP (x, 0), 0);
4263 /* If SET_DEST is CC0 and SET_SRC is not an operand, a COMPARE, or a
4264 ZERO_EXTRACT, the most likely reason why this doesn't match is that
4265 we need to put the operand into a register. So split at that
4268 if (SET_DEST (x) == cc0_rtx
4269 && GET_CODE (SET_SRC (x)) != COMPARE
4270 && GET_CODE (SET_SRC (x)) != ZERO_EXTRACT
4271 && !OBJECT_P (SET_SRC (x))
4272 && ! (GET_CODE (SET_SRC (x)) == SUBREG
4273 && OBJECT_P (SUBREG_REG (SET_SRC (x)))))
4274 return &SET_SRC (x);
4277 /* See if we can split SET_SRC as it stands. */
4278 split = find_split_point (&SET_SRC (x), insn);
4279 if (split && split != &SET_SRC (x))
4282 /* See if we can split SET_DEST as it stands. */
4283 split = find_split_point (&SET_DEST (x), insn);
4284 if (split && split != &SET_DEST (x))
4287 /* See if this is a bitfield assignment with everything constant. If
4288 so, this is an IOR of an AND, so split it into that. */
4289 if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
4290 && (GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0)))
4291 <= HOST_BITS_PER_WIDE_INT)
4292 && CONST_INT_P (XEXP (SET_DEST (x), 1))
4293 && CONST_INT_P (XEXP (SET_DEST (x), 2))
4294 && CONST_INT_P (SET_SRC (x))
4295 && ((INTVAL (XEXP (SET_DEST (x), 1))
4296 + INTVAL (XEXP (SET_DEST (x), 2)))
4297 <= GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0))))
4298 && ! side_effects_p (XEXP (SET_DEST (x), 0)))
4300 HOST_WIDE_INT pos = INTVAL (XEXP (SET_DEST (x), 2));
4301 unsigned HOST_WIDE_INT len = INTVAL (XEXP (SET_DEST (x), 1));
4302 unsigned HOST_WIDE_INT src = INTVAL (SET_SRC (x));
4303 rtx dest = XEXP (SET_DEST (x), 0);
4304 enum machine_mode mode = GET_MODE (dest);
4305 unsigned HOST_WIDE_INT mask = ((HOST_WIDE_INT) 1 << len) - 1;
4308 if (BITS_BIG_ENDIAN)
4309 pos = GET_MODE_BITSIZE (mode) - len - pos;
4311 or_mask = gen_int_mode (src << pos, mode);
4314 simplify_gen_binary (IOR, mode, dest, or_mask));
4317 rtx negmask = gen_int_mode (~(mask << pos), mode);
4319 simplify_gen_binary (IOR, mode,
4320 simplify_gen_binary (AND, mode,
4325 SUBST (SET_DEST (x), dest);
4327 split = find_split_point (&SET_SRC (x), insn);
4328 if (split && split != &SET_SRC (x))
4332 /* Otherwise, see if this is an operation that we can split into two.
4333 If so, try to split that. */
4334 code = GET_CODE (SET_SRC (x));
4339 /* If we are AND'ing with a large constant that is only a single
4340 bit and the result is only being used in a context where we
4341 need to know if it is zero or nonzero, replace it with a bit
4342 extraction. This will avoid the large constant, which might
4343 have taken more than one insn to make. If the constant were
4344 not a valid argument to the AND but took only one insn to make,
4345 this is no worse, but if it took more than one insn, it will
4348 if (CONST_INT_P (XEXP (SET_SRC (x), 1))
4349 && REG_P (XEXP (SET_SRC (x), 0))
4350 && (pos = exact_log2 (INTVAL (XEXP (SET_SRC (x), 1)))) >= 7
4351 && REG_P (SET_DEST (x))
4352 && (split = find_single_use (SET_DEST (x), insn, (rtx*) 0)) != 0
4353 && (GET_CODE (*split) == EQ || GET_CODE (*split) == NE)
4354 && XEXP (*split, 0) == SET_DEST (x)
4355 && XEXP (*split, 1) == const0_rtx)
4357 rtx extraction = make_extraction (GET_MODE (SET_DEST (x)),
4358 XEXP (SET_SRC (x), 0),
4359 pos, NULL_RTX, 1, 1, 0, 0);
4360 if (extraction != 0)
4362 SUBST (SET_SRC (x), extraction);
4363 return find_split_point (loc, insn);
4369 /* If STORE_FLAG_VALUE is -1, this is (NE X 0) and only one bit of X
4370 is known to be on, this can be converted into a NEG of a shift. */
4371 if (STORE_FLAG_VALUE == -1 && XEXP (SET_SRC (x), 1) == const0_rtx
4372 && GET_MODE (SET_SRC (x)) == GET_MODE (XEXP (SET_SRC (x), 0))
4373 && 1 <= (pos = exact_log2
4374 (nonzero_bits (XEXP (SET_SRC (x), 0),
4375 GET_MODE (XEXP (SET_SRC (x), 0))))))
4377 enum machine_mode mode = GET_MODE (XEXP (SET_SRC (x), 0));
4381 gen_rtx_LSHIFTRT (mode,
4382 XEXP (SET_SRC (x), 0),
4385 split = find_split_point (&SET_SRC (x), insn);
4386 if (split && split != &SET_SRC (x))
4392 inner = XEXP (SET_SRC (x), 0);
4394 /* We can't optimize if either mode is a partial integer
4395 mode as we don't know how many bits are significant
4397 if (GET_MODE_CLASS (GET_MODE (inner)) == MODE_PARTIAL_INT
4398 || GET_MODE_CLASS (GET_MODE (SET_SRC (x))) == MODE_PARTIAL_INT)
4402 len = GET_MODE_BITSIZE (GET_MODE (inner));
4408 if (CONST_INT_P (XEXP (SET_SRC (x), 1))
4409 && CONST_INT_P (XEXP (SET_SRC (x), 2)))
4411 inner = XEXP (SET_SRC (x), 0);
4412 len = INTVAL (XEXP (SET_SRC (x), 1));
4413 pos = INTVAL (XEXP (SET_SRC (x), 2));
4415 if (BITS_BIG_ENDIAN)
4416 pos = GET_MODE_BITSIZE (GET_MODE (inner)) - len - pos;
4417 unsignedp = (code == ZERO_EXTRACT);
4425 if (len && pos >= 0 && pos + len <= GET_MODE_BITSIZE (GET_MODE (inner)))
4427 enum machine_mode mode = GET_MODE (SET_SRC (x));
4429 /* For unsigned, we have a choice of a shift followed by an
4430 AND or two shifts. Use two shifts for field sizes where the
4431 constant might be too large. We assume here that we can
4432 always at least get 8-bit constants in an AND insn, which is
4433 true for every current RISC. */
4435 if (unsignedp && len <= 8)
4440 (mode, gen_lowpart (mode, inner),
4442 GEN_INT (((HOST_WIDE_INT) 1 << len) - 1)));
4444 split = find_split_point (&SET_SRC (x), insn);
4445 if (split && split != &SET_SRC (x))
4452 (unsignedp ? LSHIFTRT : ASHIFTRT, mode,
4453 gen_rtx_ASHIFT (mode,
4454 gen_lowpart (mode, inner),
4455 GEN_INT (GET_MODE_BITSIZE (mode)
4457 GEN_INT (GET_MODE_BITSIZE (mode) - len)));
4459 split = find_split_point (&SET_SRC (x), insn);
4460 if (split && split != &SET_SRC (x))
4465 /* See if this is a simple operation with a constant as the second
4466 operand. It might be that this constant is out of range and hence
4467 could be used as a split point. */
4468 if (BINARY_P (SET_SRC (x))
4469 && CONSTANT_P (XEXP (SET_SRC (x), 1))
4470 && (OBJECT_P (XEXP (SET_SRC (x), 0))
4471 || (GET_CODE (XEXP (SET_SRC (x), 0)) == SUBREG
4472 && OBJECT_P (SUBREG_REG (XEXP (SET_SRC (x), 0))))))
4473 return &XEXP (SET_SRC (x), 1);
4475 /* Finally, see if this is a simple operation with its first operand
4476 not in a register. The operation might require this operand in a
4477 register, so return it as a split point. We can always do this
4478 because if the first operand were another operation, we would have
4479 already found it as a split point. */
4480 if ((BINARY_P (SET_SRC (x)) || UNARY_P (SET_SRC (x)))
4481 && ! register_operand (XEXP (SET_SRC (x), 0), VOIDmode))
4482 return &XEXP (SET_SRC (x), 0);
4488 /* We write NOR as (and (not A) (not B)), but if we don't have a NOR,
4489 it is better to write this as (not (ior A B)) so we can split it.
4490 Similarly for IOR. */
4491 if (GET_CODE (XEXP (x, 0)) == NOT && GET_CODE (XEXP (x, 1)) == NOT)
4494 gen_rtx_NOT (GET_MODE (x),
4495 gen_rtx_fmt_ee (code == IOR ? AND : IOR,
4497 XEXP (XEXP (x, 0), 0),
4498 XEXP (XEXP (x, 1), 0))));
4499 return find_split_point (loc, insn);
4502 /* Many RISC machines have a large set of logical insns. If the
4503 second operand is a NOT, put it first so we will try to split the
4504 other operand first. */
4505 if (GET_CODE (XEXP (x, 1)) == NOT)
4507 rtx tem = XEXP (x, 0);
4508 SUBST (XEXP (x, 0), XEXP (x, 1));
4509 SUBST (XEXP (x, 1), tem);
4517 /* Otherwise, select our actions depending on our rtx class. */
4518 switch (GET_RTX_CLASS (code))
4520 case RTX_BITFIELD_OPS: /* This is ZERO_EXTRACT and SIGN_EXTRACT. */
4522 split = find_split_point (&XEXP (x, 2), insn);
4525 /* ... fall through ... */
4527 case RTX_COMM_ARITH:
4529 case RTX_COMM_COMPARE:
4530 split = find_split_point (&XEXP (x, 1), insn);
4533 /* ... fall through ... */
4535 /* Some machines have (and (shift ...) ...) insns. If X is not
4536 an AND, but XEXP (X, 0) is, use it as our split point. */
4537 if (GET_CODE (x) != AND && GET_CODE (XEXP (x, 0)) == AND)
4538 return &XEXP (x, 0);
4540 split = find_split_point (&XEXP (x, 0), insn);
4546 /* Otherwise, we don't have a split point. */
4551 /* Throughout X, replace FROM with TO, and return the result.
4552 The result is TO if X is FROM;
4553 otherwise the result is X, but its contents may have been modified.
4554 If they were modified, a record was made in undobuf so that
4555 undo_all will (among other things) return X to its original state.
4557 If the number of changes necessary is too much to record to undo,
4558 the excess changes are not made, so the result is invalid.
4559 The changes already made can still be undone.
4560 undobuf.num_undo is incremented for such changes, so by testing that
4561 the caller can tell whether the result is valid.
4563 `n_occurrences' is incremented each time FROM is replaced.
4565 IN_DEST is nonzero if we are processing the SET_DEST of a SET.
4567 UNIQUE_COPY is nonzero if each substitution must be unique. We do this
4568 by copying if `n_occurrences' is nonzero. */
4571 subst (rtx x, rtx from, rtx to, int in_dest, int unique_copy)
4573 enum rtx_code code = GET_CODE (x);
4574 enum machine_mode op0_mode = VOIDmode;
4579 /* Two expressions are equal if they are identical copies of a shared
4580 RTX or if they are both registers with the same register number
4583 #define COMBINE_RTX_EQUAL_P(X,Y) \
4585 || (REG_P (X) && REG_P (Y) \
4586 && REGNO (X) == REGNO (Y) && GET_MODE (X) == GET_MODE (Y)))
4588 if (! in_dest && COMBINE_RTX_EQUAL_P (x, from))
4591 return (unique_copy && n_occurrences > 1 ? copy_rtx (to) : to);
4594 /* If X and FROM are the same register but different modes, they
4595 will not have been seen as equal above. However, the log links code
4596 will make a LOG_LINKS entry for that case. If we do nothing, we
4597 will try to rerecognize our original insn and, when it succeeds,
4598 we will delete the feeding insn, which is incorrect.
4600 So force this insn not to match in this (rare) case. */
4601 if (! in_dest && code == REG && REG_P (from)
4602 && reg_overlap_mentioned_p (x, from))
4603 return gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
4605 /* If this is an object, we are done unless it is a MEM or LO_SUM, both
4606 of which may contain things that can be combined. */
4607 if (code != MEM && code != LO_SUM && OBJECT_P (x))
4610 /* It is possible to have a subexpression appear twice in the insn.
4611 Suppose that FROM is a register that appears within TO.
4612 Then, after that subexpression has been scanned once by `subst',
4613 the second time it is scanned, TO may be found. If we were
4614 to scan TO here, we would find FROM within it and create a
4615 self-referent rtl structure which is completely wrong. */
4616 if (COMBINE_RTX_EQUAL_P (x, to))
4619 /* Parallel asm_operands need special attention because all of the
4620 inputs are shared across the arms. Furthermore, unsharing the
4621 rtl results in recognition failures. Failure to handle this case
4622 specially can result in circular rtl.
4624 Solve this by doing a normal pass across the first entry of the
4625 parallel, and only processing the SET_DESTs of the subsequent
4628 if (code == PARALLEL
4629 && GET_CODE (XVECEXP (x, 0, 0)) == SET
4630 && GET_CODE (SET_SRC (XVECEXP (x, 0, 0))) == ASM_OPERANDS)
4632 new_rtx = subst (XVECEXP (x, 0, 0), from, to, 0, unique_copy);
4634 /* If this substitution failed, this whole thing fails. */
4635 if (GET_CODE (new_rtx) == CLOBBER
4636 && XEXP (new_rtx, 0) == const0_rtx)
4639 SUBST (XVECEXP (x, 0, 0), new_rtx);
4641 for (i = XVECLEN (x, 0) - 1; i >= 1; i--)
4643 rtx dest = SET_DEST (XVECEXP (x, 0, i));
4646 && GET_CODE (dest) != CC0
4647 && GET_CODE (dest) != PC)
4649 new_rtx = subst (dest, from, to, 0, unique_copy);
4651 /* If this substitution failed, this whole thing fails. */
4652 if (GET_CODE (new_rtx) == CLOBBER
4653 && XEXP (new_rtx, 0) == const0_rtx)
4656 SUBST (SET_DEST (XVECEXP (x, 0, i)), new_rtx);
4662 len = GET_RTX_LENGTH (code);
4663 fmt = GET_RTX_FORMAT (code);
4665 /* We don't need to process a SET_DEST that is a register, CC0,
4666 or PC, so set up to skip this common case. All other cases
4667 where we want to suppress replacing something inside a
4668 SET_SRC are handled via the IN_DEST operand. */
4670 && (REG_P (SET_DEST (x))
4671 || GET_CODE (SET_DEST (x)) == CC0
4672 || GET_CODE (SET_DEST (x)) == PC))
4675 /* Get the mode of operand 0 in case X is now a SIGN_EXTEND of a
4678 op0_mode = GET_MODE (XEXP (x, 0));
4680 for (i = 0; i < len; i++)
4685 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
4687 if (COMBINE_RTX_EQUAL_P (XVECEXP (x, i, j), from))
4689 new_rtx = (unique_copy && n_occurrences
4690 ? copy_rtx (to) : to);
4695 new_rtx = subst (XVECEXP (x, i, j), from, to, 0,
4698 /* If this substitution failed, this whole thing
4700 if (GET_CODE (new_rtx) == CLOBBER
4701 && XEXP (new_rtx, 0) == const0_rtx)
4705 SUBST (XVECEXP (x, i, j), new_rtx);
4708 else if (fmt[i] == 'e')
4710 /* If this is a register being set, ignore it. */
4711 new_rtx = XEXP (x, i);
4714 && (((code == SUBREG || code == ZERO_EXTRACT)
4716 || code == STRICT_LOW_PART))
4719 else if (COMBINE_RTX_EQUAL_P (XEXP (x, i), from))
4721 /* In general, don't install a subreg involving two
4722 modes not tieable. It can worsen register
4723 allocation, and can even make invalid reload
4724 insns, since the reg inside may need to be copied
4725 from in the outside mode, and that may be invalid
4726 if it is an fp reg copied in integer mode.
4728 We allow two exceptions to this: It is valid if
4729 it is inside another SUBREG and the mode of that
4730 SUBREG and the mode of the inside of TO is
4731 tieable and it is valid if X is a SET that copies
4734 if (GET_CODE (to) == SUBREG
4735 && ! MODES_TIEABLE_P (GET_MODE (to),
4736 GET_MODE (SUBREG_REG (to)))
4737 && ! (code == SUBREG
4738 && MODES_TIEABLE_P (GET_MODE (x),
4739 GET_MODE (SUBREG_REG (to))))
4741 && ! (code == SET && i == 1 && XEXP (x, 0) == cc0_rtx)
4744 return gen_rtx_CLOBBER (VOIDmode, const0_rtx);
4746 #ifdef CANNOT_CHANGE_MODE_CLASS
4749 && REGNO (to) < FIRST_PSEUDO_REGISTER
4750 && REG_CANNOT_CHANGE_MODE_P (REGNO (to),
4753 return gen_rtx_CLOBBER (VOIDmode, const0_rtx);
4756 new_rtx = (unique_copy && n_occurrences ? copy_rtx (to) : to);
4760 /* If we are in a SET_DEST, suppress most cases unless we
4761 have gone inside a MEM, in which case we want to
4762 simplify the address. We assume here that things that
4763 are actually part of the destination have their inner
4764 parts in the first expression. This is true for SUBREG,
4765 STRICT_LOW_PART, and ZERO_EXTRACT, which are the only
4766 things aside from REG and MEM that should appear in a
4768 new_rtx = subst (XEXP (x, i), from, to,
4770 && (code == SUBREG || code == STRICT_LOW_PART
4771 || code == ZERO_EXTRACT))
4773 && i == 0), unique_copy);
4775 /* If we found that we will have to reject this combination,
4776 indicate that by returning the CLOBBER ourselves, rather than
4777 an expression containing it. This will speed things up as
4778 well as prevent accidents where two CLOBBERs are considered
4779 to be equal, thus producing an incorrect simplification. */
4781 if (GET_CODE (new_rtx) == CLOBBER && XEXP (new_rtx, 0) == const0_rtx)
4784 if (GET_CODE (x) == SUBREG
4785 && (CONST_INT_P (new_rtx)
4786 || GET_CODE (new_rtx) == CONST_DOUBLE))
4788 enum machine_mode mode = GET_MODE (x);
4790 x = simplify_subreg (GET_MODE (x), new_rtx,
4791 GET_MODE (SUBREG_REG (x)),
4794 x = gen_rtx_CLOBBER (mode, const0_rtx);
4796 else if (CONST_INT_P (new_rtx)
4797 && GET_CODE (x) == ZERO_EXTEND)
4799 x = simplify_unary_operation (ZERO_EXTEND, GET_MODE (x),
4800 new_rtx, GET_MODE (XEXP (x, 0)));
4804 SUBST (XEXP (x, i), new_rtx);
4809 /* Check if we are loading something from the constant pool via float
4810 extension; in this case we would undo compress_float_constant
4811 optimization and degenerate constant load to an immediate value. */
4812 if (GET_CODE (x) == FLOAT_EXTEND
4813 && MEM_P (XEXP (x, 0))
4814 && MEM_READONLY_P (XEXP (x, 0)))
4816 rtx tmp = avoid_constant_pool_reference (x);
4821 /* Try to simplify X. If the simplification changed the code, it is likely
4822 that further simplification will help, so loop, but limit the number
4823 of repetitions that will be performed. */
4825 for (i = 0; i < 4; i++)
4827 /* If X is sufficiently simple, don't bother trying to do anything
4829 if (code != CONST_INT && code != REG && code != CLOBBER)
4830 x = combine_simplify_rtx (x, op0_mode, in_dest);
4832 if (GET_CODE (x) == code)
4835 code = GET_CODE (x);
4837 /* We no longer know the original mode of operand 0 since we
4838 have changed the form of X) */
4839 op0_mode = VOIDmode;
4845 /* Simplify X, a piece of RTL. We just operate on the expression at the
4846 outer level; call `subst' to simplify recursively. Return the new
4849 OP0_MODE is the original mode of XEXP (x, 0). IN_DEST is nonzero
4850 if we are inside a SET_DEST. */
4853 combine_simplify_rtx (rtx x, enum machine_mode op0_mode, int in_dest)
4855 enum rtx_code code = GET_CODE (x);
4856 enum machine_mode mode = GET_MODE (x);
4860 /* If this is a commutative operation, put a constant last and a complex
4861 expression first. We don't need to do this for comparisons here. */
4862 if (COMMUTATIVE_ARITH_P (x)
4863 && swap_commutative_operands_p (XEXP (x, 0), XEXP (x, 1)))
4866 SUBST (XEXP (x, 0), XEXP (x, 1));
4867 SUBST (XEXP (x, 1), temp);
4870 /* If this is a simple operation applied to an IF_THEN_ELSE, try
4871 applying it to the arms of the IF_THEN_ELSE. This often simplifies
4872 things. Check for cases where both arms are testing the same
4875 Don't do anything if all operands are very simple. */
4878 && ((!OBJECT_P (XEXP (x, 0))
4879 && ! (GET_CODE (XEXP (x, 0)) == SUBREG
4880 && OBJECT_P (SUBREG_REG (XEXP (x, 0)))))
4881 || (!OBJECT_P (XEXP (x, 1))
4882 && ! (GET_CODE (XEXP (x, 1)) == SUBREG
4883 && OBJECT_P (SUBREG_REG (XEXP (x, 1)))))))
4885 && (!OBJECT_P (XEXP (x, 0))
4886 && ! (GET_CODE (XEXP (x, 0)) == SUBREG
4887 && OBJECT_P (SUBREG_REG (XEXP (x, 0)))))))
4889 rtx cond, true_rtx, false_rtx;
4891 cond = if_then_else_cond (x, &true_rtx, &false_rtx);
4893 /* If everything is a comparison, what we have is highly unlikely
4894 to be simpler, so don't use it. */
4895 && ! (COMPARISON_P (x)
4896 && (COMPARISON_P (true_rtx) || COMPARISON_P (false_rtx))))
4898 rtx cop1 = const0_rtx;
4899 enum rtx_code cond_code = simplify_comparison (NE, &cond, &cop1);
4901 if (cond_code == NE && COMPARISON_P (cond))
4904 /* Simplify the alternative arms; this may collapse the true and
4905 false arms to store-flag values. Be careful to use copy_rtx
4906 here since true_rtx or false_rtx might share RTL with x as a
4907 result of the if_then_else_cond call above. */
4908 true_rtx = subst (copy_rtx (true_rtx), pc_rtx, pc_rtx, 0, 0);
4909 false_rtx = subst (copy_rtx (false_rtx), pc_rtx, pc_rtx, 0, 0);
4911 /* If true_rtx and false_rtx are not general_operands, an if_then_else
4912 is unlikely to be simpler. */
4913 if (general_operand (true_rtx, VOIDmode)
4914 && general_operand (false_rtx, VOIDmode))
4916 enum rtx_code reversed;
4918 /* Restarting if we generate a store-flag expression will cause
4919 us to loop. Just drop through in this case. */
4921 /* If the result values are STORE_FLAG_VALUE and zero, we can
4922 just make the comparison operation. */
4923 if (true_rtx == const_true_rtx && false_rtx == const0_rtx)
4924 x = simplify_gen_relational (cond_code, mode, VOIDmode,
4926 else if (true_rtx == const0_rtx && false_rtx == const_true_rtx
4927 && ((reversed = reversed_comparison_code_parts
4928 (cond_code, cond, cop1, NULL))
4930 x = simplify_gen_relational (reversed, mode, VOIDmode,
4933 /* Likewise, we can make the negate of a comparison operation
4934 if the result values are - STORE_FLAG_VALUE and zero. */
4935 else if (CONST_INT_P (true_rtx)
4936 && INTVAL (true_rtx) == - STORE_FLAG_VALUE
4937 && false_rtx == const0_rtx)
4938 x = simplify_gen_unary (NEG, mode,
4939 simplify_gen_relational (cond_code,
4943 else if (CONST_INT_P (false_rtx)
4944 && INTVAL (false_rtx) == - STORE_FLAG_VALUE
4945 && true_rtx == const0_rtx
4946 && ((reversed = reversed_comparison_code_parts
4947 (cond_code, cond, cop1, NULL))
4949 x = simplify_gen_unary (NEG, mode,
4950 simplify_gen_relational (reversed,
4955 return gen_rtx_IF_THEN_ELSE (mode,
4956 simplify_gen_relational (cond_code,
4961 true_rtx, false_rtx);
4963 code = GET_CODE (x);
4964 op0_mode = VOIDmode;
4969 /* Try to fold this expression in case we have constants that weren't
4972 switch (GET_RTX_CLASS (code))
4975 if (op0_mode == VOIDmode)
4976 op0_mode = GET_MODE (XEXP (x, 0));
4977 temp = simplify_unary_operation (code, mode, XEXP (x, 0), op0_mode);
4980 case RTX_COMM_COMPARE:
4982 enum machine_mode cmp_mode = GET_MODE (XEXP (x, 0));
4983 if (cmp_mode == VOIDmode)
4985 cmp_mode = GET_MODE (XEXP (x, 1));
4986 if (cmp_mode == VOIDmode)
4987 cmp_mode = op0_mode;
4989 temp = simplify_relational_operation (code, mode, cmp_mode,
4990 XEXP (x, 0), XEXP (x, 1));
4993 case RTX_COMM_ARITH:
4995 temp = simplify_binary_operation (code, mode, XEXP (x, 0), XEXP (x, 1));
4997 case RTX_BITFIELD_OPS:
4999 temp = simplify_ternary_operation (code, mode, op0_mode, XEXP (x, 0),
5000 XEXP (x, 1), XEXP (x, 2));
5009 code = GET_CODE (temp);
5010 op0_mode = VOIDmode;
5011 mode = GET_MODE (temp);
5014 /* First see if we can apply the inverse distributive law. */
5015 if (code == PLUS || code == MINUS
5016 || code == AND || code == IOR || code == XOR)
5018 x = apply_distributive_law (x);
5019 code = GET_CODE (x);
5020 op0_mode = VOIDmode;
5023 /* If CODE is an associative operation not otherwise handled, see if we
5024 can associate some operands. This can win if they are constants or
5025 if they are logically related (i.e. (a & b) & a). */
5026 if ((code == PLUS || code == MINUS || code == MULT || code == DIV
5027 || code == AND || code == IOR || code == XOR
5028 || code == SMAX || code == SMIN || code == UMAX || code == UMIN)
5029 && ((INTEGRAL_MODE_P (mode) && code != DIV)
5030 || (flag_associative_math && FLOAT_MODE_P (mode))))
5032 if (GET_CODE (XEXP (x, 0)) == code)
5034 rtx other = XEXP (XEXP (x, 0), 0);
5035 rtx inner_op0 = XEXP (XEXP (x, 0), 1);
5036 rtx inner_op1 = XEXP (x, 1);
5039 /* Make sure we pass the constant operand if any as the second
5040 one if this is a commutative operation. */
5041 if (CONSTANT_P (inner_op0) && COMMUTATIVE_ARITH_P (x))
5043 rtx tem = inner_op0;
5044 inner_op0 = inner_op1;
5047 inner = simplify_binary_operation (code == MINUS ? PLUS
5048 : code == DIV ? MULT
5050 mode, inner_op0, inner_op1);
5052 /* For commutative operations, try the other pair if that one
5054 if (inner == 0 && COMMUTATIVE_ARITH_P (x))
5056 other = XEXP (XEXP (x, 0), 1);
5057 inner = simplify_binary_operation (code, mode,
5058 XEXP (XEXP (x, 0), 0),
5063 return simplify_gen_binary (code, mode, other, inner);
5067 /* A little bit of algebraic simplification here. */
5071 /* Ensure that our address has any ASHIFTs converted to MULT in case
5072 address-recognizing predicates are called later. */
5073 temp = make_compound_operation (XEXP (x, 0), MEM);
5074 SUBST (XEXP (x, 0), temp);
5078 if (op0_mode == VOIDmode)
5079 op0_mode = GET_MODE (SUBREG_REG (x));
5081 /* See if this can be moved to simplify_subreg. */
5082 if (CONSTANT_P (SUBREG_REG (x))
5083 && subreg_lowpart_offset (mode, op0_mode) == SUBREG_BYTE (x)
5084 /* Don't call gen_lowpart if the inner mode
5085 is VOIDmode and we cannot simplify it, as SUBREG without
5086 inner mode is invalid. */
5087 && (GET_MODE (SUBREG_REG (x)) != VOIDmode
5088 || gen_lowpart_common (mode, SUBREG_REG (x))))
5089 return gen_lowpart (mode, SUBREG_REG (x));
5091 if (GET_MODE_CLASS (GET_MODE (SUBREG_REG (x))) == MODE_CC)
5095 temp = simplify_subreg (mode, SUBREG_REG (x), op0_mode,
5101 /* Don't change the mode of the MEM if that would change the meaning
5103 if (MEM_P (SUBREG_REG (x))
5104 && (MEM_VOLATILE_P (SUBREG_REG (x))
5105 || mode_dependent_address_p (XEXP (SUBREG_REG (x), 0))))
5106 return gen_rtx_CLOBBER (mode, const0_rtx);
5108 /* Note that we cannot do any narrowing for non-constants since
5109 we might have been counting on using the fact that some bits were
5110 zero. We now do this in the SET. */
5115 temp = expand_compound_operation (XEXP (x, 0));
5117 /* For C equal to the width of MODE minus 1, (neg (ashiftrt X C)) can be
5118 replaced by (lshiftrt X C). This will convert
5119 (neg (sign_extract X 1 Y)) to (zero_extract X 1 Y). */
5121 if (GET_CODE (temp) == ASHIFTRT
5122 && CONST_INT_P (XEXP (temp, 1))
5123 && INTVAL (XEXP (temp, 1)) == GET_MODE_BITSIZE (mode) - 1)
5124 return simplify_shift_const (NULL_RTX, LSHIFTRT, mode, XEXP (temp, 0),
5125 INTVAL (XEXP (temp, 1)));
5127 /* If X has only a single bit that might be nonzero, say, bit I, convert
5128 (neg X) to (ashiftrt (ashift X C-I) C-I) where C is the bitsize of
5129 MODE minus 1. This will convert (neg (zero_extract X 1 Y)) to
5130 (sign_extract X 1 Y). But only do this if TEMP isn't a register
5131 or a SUBREG of one since we'd be making the expression more
5132 complex if it was just a register. */
5135 && ! (GET_CODE (temp) == SUBREG
5136 && REG_P (SUBREG_REG (temp)))
5137 && (i = exact_log2 (nonzero_bits (temp, mode))) >= 0)
5139 rtx temp1 = simplify_shift_const
5140 (NULL_RTX, ASHIFTRT, mode,
5141 simplify_shift_const (NULL_RTX, ASHIFT, mode, temp,
5142 GET_MODE_BITSIZE (mode) - 1 - i),
5143 GET_MODE_BITSIZE (mode) - 1 - i);
5145 /* If all we did was surround TEMP with the two shifts, we
5146 haven't improved anything, so don't use it. Otherwise,
5147 we are better off with TEMP1. */
5148 if (GET_CODE (temp1) != ASHIFTRT
5149 || GET_CODE (XEXP (temp1, 0)) != ASHIFT
5150 || XEXP (XEXP (temp1, 0), 0) != temp)
5156 /* We can't handle truncation to a partial integer mode here
5157 because we don't know the real bitsize of the partial
5159 if (GET_MODE_CLASS (mode) == MODE_PARTIAL_INT)
5162 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
5164 force_to_mode (XEXP (x, 0), GET_MODE (XEXP (x, 0)),
5165 GET_MODE_MASK (mode), 0));
5167 /* We can truncate a constant value and return it. */
5168 if (CONST_INT_P (XEXP (x, 0)))
5169 return gen_int_mode (INTVAL (XEXP (x, 0)), mode);
5171 /* Similarly to what we do in simplify-rtx.c, a truncate of a register
5172 whose value is a comparison can be replaced with a subreg if
5173 STORE_FLAG_VALUE permits. */
5174 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5175 && ((HOST_WIDE_INT) STORE_FLAG_VALUE & ~GET_MODE_MASK (mode)) == 0
5176 && (temp = get_last_value (XEXP (x, 0)))
5177 && COMPARISON_P (temp))
5178 return gen_lowpart (mode, XEXP (x, 0));
5182 /* (const (const X)) can become (const X). Do it this way rather than
5183 returning the inner CONST since CONST can be shared with a
5185 if (GET_CODE (XEXP (x, 0)) == CONST)
5186 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
5191 /* Convert (lo_sum (high FOO) FOO) to FOO. This is necessary so we
5192 can add in an offset. find_split_point will split this address up
5193 again if it doesn't match. */
5194 if (GET_CODE (XEXP (x, 0)) == HIGH
5195 && rtx_equal_p (XEXP (XEXP (x, 0), 0), XEXP (x, 1)))
5201 /* (plus (xor (and <foo> (const_int pow2 - 1)) <c>) <-c>)
5202 when c is (const_int (pow2 + 1) / 2) is a sign extension of a
5203 bit-field and can be replaced by either a sign_extend or a
5204 sign_extract. The `and' may be a zero_extend and the two
5205 <c>, -<c> constants may be reversed. */
5206 if (GET_CODE (XEXP (x, 0)) == XOR
5207 && CONST_INT_P (XEXP (x, 1))
5208 && CONST_INT_P (XEXP (XEXP (x, 0), 1))
5209 && INTVAL (XEXP (x, 1)) == -INTVAL (XEXP (XEXP (x, 0), 1))
5210 && ((i = exact_log2 (INTVAL (XEXP (XEXP (x, 0), 1)))) >= 0
5211 || (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0)
5212 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5213 && ((GET_CODE (XEXP (XEXP (x, 0), 0)) == AND
5214 && CONST_INT_P (XEXP (XEXP (XEXP (x, 0), 0), 1))
5215 && (INTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1))
5216 == ((HOST_WIDE_INT) 1 << (i + 1)) - 1))
5217 || (GET_CODE (XEXP (XEXP (x, 0), 0)) == ZERO_EXTEND
5218 && (GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)))
5219 == (unsigned int) i + 1))))
5220 return simplify_shift_const
5221 (NULL_RTX, ASHIFTRT, mode,
5222 simplify_shift_const (NULL_RTX, ASHIFT, mode,
5223 XEXP (XEXP (XEXP (x, 0), 0), 0),
5224 GET_MODE_BITSIZE (mode) - (i + 1)),
5225 GET_MODE_BITSIZE (mode) - (i + 1));
5227 /* If only the low-order bit of X is possibly nonzero, (plus x -1)
5228 can become (ashiftrt (ashift (xor x 1) C) C) where C is
5229 the bitsize of the mode - 1. This allows simplification of
5230 "a = (b & 8) == 0;" */
5231 if (XEXP (x, 1) == constm1_rtx
5232 && !REG_P (XEXP (x, 0))
5233 && ! (GET_CODE (XEXP (x, 0)) == SUBREG
5234 && REG_P (SUBREG_REG (XEXP (x, 0))))
5235 && nonzero_bits (XEXP (x, 0), mode) == 1)
5236 return simplify_shift_const (NULL_RTX, ASHIFTRT, mode,
5237 simplify_shift_const (NULL_RTX, ASHIFT, mode,
5238 gen_rtx_XOR (mode, XEXP (x, 0), const1_rtx),
5239 GET_MODE_BITSIZE (mode) - 1),
5240 GET_MODE_BITSIZE (mode) - 1);
5242 /* If we are adding two things that have no bits in common, convert
5243 the addition into an IOR. This will often be further simplified,
5244 for example in cases like ((a & 1) + (a & 2)), which can
5247 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5248 && (nonzero_bits (XEXP (x, 0), mode)
5249 & nonzero_bits (XEXP (x, 1), mode)) == 0)
5251 /* Try to simplify the expression further. */
5252 rtx tor = simplify_gen_binary (IOR, mode, XEXP (x, 0), XEXP (x, 1));
5253 temp = combine_simplify_rtx (tor, mode, in_dest);
5255 /* If we could, great. If not, do not go ahead with the IOR
5256 replacement, since PLUS appears in many special purpose
5257 address arithmetic instructions. */
5258 if (GET_CODE (temp) != CLOBBER && temp != tor)
5264 /* (minus <foo> (and <foo> (const_int -pow2))) becomes
5265 (and <foo> (const_int pow2-1)) */
5266 if (GET_CODE (XEXP (x, 1)) == AND
5267 && CONST_INT_P (XEXP (XEXP (x, 1), 1))
5268 && exact_log2 (-INTVAL (XEXP (XEXP (x, 1), 1))) >= 0
5269 && rtx_equal_p (XEXP (XEXP (x, 1), 0), XEXP (x, 0)))
5270 return simplify_and_const_int (NULL_RTX, mode, XEXP (x, 0),
5271 -INTVAL (XEXP (XEXP (x, 1), 1)) - 1);
5275 /* If we have (mult (plus A B) C), apply the distributive law and then
5276 the inverse distributive law to see if things simplify. This
5277 occurs mostly in addresses, often when unrolling loops. */
5279 if (GET_CODE (XEXP (x, 0)) == PLUS)
5281 rtx result = distribute_and_simplify_rtx (x, 0);
5286 /* Try simplify a*(b/c) as (a*b)/c. */
5287 if (FLOAT_MODE_P (mode) && flag_associative_math
5288 && GET_CODE (XEXP (x, 0)) == DIV)
5290 rtx tem = simplify_binary_operation (MULT, mode,
5291 XEXP (XEXP (x, 0), 0),
5294 return simplify_gen_binary (DIV, mode, tem, XEXP (XEXP (x, 0), 1));
5299 /* If this is a divide by a power of two, treat it as a shift if
5300 its first operand is a shift. */
5301 if (CONST_INT_P (XEXP (x, 1))
5302 && (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0
5303 && (GET_CODE (XEXP (x, 0)) == ASHIFT
5304 || GET_CODE (XEXP (x, 0)) == LSHIFTRT
5305 || GET_CODE (XEXP (x, 0)) == ASHIFTRT
5306 || GET_CODE (XEXP (x, 0)) == ROTATE
5307 || GET_CODE (XEXP (x, 0)) == ROTATERT))
5308 return simplify_shift_const (NULL_RTX, LSHIFTRT, mode, XEXP (x, 0), i);
5312 case GT: case GTU: case GE: case GEU:
5313 case LT: case LTU: case LE: case LEU:
5314 case UNEQ: case LTGT:
5315 case UNGT: case UNGE:
5316 case UNLT: case UNLE:
5317 case UNORDERED: case ORDERED:
5318 /* If the first operand is a condition code, we can't do anything
5320 if (GET_CODE (XEXP (x, 0)) == COMPARE
5321 || (GET_MODE_CLASS (GET_MODE (XEXP (x, 0))) != MODE_CC
5322 && ! CC0_P (XEXP (x, 0))))
5324 rtx op0 = XEXP (x, 0);
5325 rtx op1 = XEXP (x, 1);
5326 enum rtx_code new_code;
5328 if (GET_CODE (op0) == COMPARE)
5329 op1 = XEXP (op0, 1), op0 = XEXP (op0, 0);
5331 /* Simplify our comparison, if possible. */
5332 new_code = simplify_comparison (code, &op0, &op1);
5334 /* If STORE_FLAG_VALUE is 1, we can convert (ne x 0) to simply X
5335 if only the low-order bit is possibly nonzero in X (such as when
5336 X is a ZERO_EXTRACT of one bit). Similarly, we can convert EQ to
5337 (xor X 1) or (minus 1 X); we use the former. Finally, if X is
5338 known to be either 0 or -1, NE becomes a NEG and EQ becomes
5341 Remove any ZERO_EXTRACT we made when thinking this was a
5342 comparison. It may now be simpler to use, e.g., an AND. If a
5343 ZERO_EXTRACT is indeed appropriate, it will be placed back by
5344 the call to make_compound_operation in the SET case. */
5346 if (STORE_FLAG_VALUE == 1
5347 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
5348 && op1 == const0_rtx
5349 && mode == GET_MODE (op0)
5350 && nonzero_bits (op0, mode) == 1)
5351 return gen_lowpart (mode,
5352 expand_compound_operation (op0));
5354 else if (STORE_FLAG_VALUE == 1
5355 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
5356 && op1 == const0_rtx
5357 && mode == GET_MODE (op0)
5358 && (num_sign_bit_copies (op0, mode)
5359 == GET_MODE_BITSIZE (mode)))
5361 op0 = expand_compound_operation (op0);
5362 return simplify_gen_unary (NEG, mode,
5363 gen_lowpart (mode, op0),
5367 else if (STORE_FLAG_VALUE == 1
5368 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
5369 && op1 == const0_rtx
5370 && mode == GET_MODE (op0)
5371 && nonzero_bits (op0, mode) == 1)
5373 op0 = expand_compound_operation (op0);
5374 return simplify_gen_binary (XOR, mode,
5375 gen_lowpart (mode, op0),
5379 else if (STORE_FLAG_VALUE == 1
5380 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
5381 && op1 == const0_rtx
5382 && mode == GET_MODE (op0)
5383 && (num_sign_bit_copies (op0, mode)
5384 == GET_MODE_BITSIZE (mode)))
5386 op0 = expand_compound_operation (op0);
5387 return plus_constant (gen_lowpart (mode, op0), 1);
5390 /* If STORE_FLAG_VALUE is -1, we have cases similar to
5392 if (STORE_FLAG_VALUE == -1
5393 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
5394 && op1 == const0_rtx
5395 && (num_sign_bit_copies (op0, mode)
5396 == GET_MODE_BITSIZE (mode)))
5397 return gen_lowpart (mode,
5398 expand_compound_operation (op0));
5400 else if (STORE_FLAG_VALUE == -1
5401 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
5402 && op1 == const0_rtx
5403 && mode == GET_MODE (op0)
5404 && nonzero_bits (op0, mode) == 1)
5406 op0 = expand_compound_operation (op0);
5407 return simplify_gen_unary (NEG, mode,
5408 gen_lowpart (mode, op0),
5412 else if (STORE_FLAG_VALUE == -1
5413 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
5414 && op1 == const0_rtx
5415 && mode == GET_MODE (op0)
5416 && (num_sign_bit_copies (op0, mode)
5417 == GET_MODE_BITSIZE (mode)))
5419 op0 = expand_compound_operation (op0);
5420 return simplify_gen_unary (NOT, mode,
5421 gen_lowpart (mode, op0),
5425 /* If X is 0/1, (eq X 0) is X-1. */
5426 else if (STORE_FLAG_VALUE == -1
5427 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
5428 && op1 == const0_rtx
5429 && mode == GET_MODE (op0)
5430 && nonzero_bits (op0, mode) == 1)
5432 op0 = expand_compound_operation (op0);
5433 return plus_constant (gen_lowpart (mode, op0), -1);
5436 /* If STORE_FLAG_VALUE says to just test the sign bit and X has just
5437 one bit that might be nonzero, we can convert (ne x 0) to
5438 (ashift x c) where C puts the bit in the sign bit. Remove any
5439 AND with STORE_FLAG_VALUE when we are done, since we are only
5440 going to test the sign bit. */
5441 if (new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
5442 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5443 && ((STORE_FLAG_VALUE & GET_MODE_MASK (mode))
5444 == (unsigned HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (mode) - 1))
5445 && op1 == const0_rtx
5446 && mode == GET_MODE (op0)
5447 && (i = exact_log2 (nonzero_bits (op0, mode))) >= 0)
5449 x = simplify_shift_const (NULL_RTX, ASHIFT, mode,
5450 expand_compound_operation (op0),
5451 GET_MODE_BITSIZE (mode) - 1 - i);
5452 if (GET_CODE (x) == AND && XEXP (x, 1) == const_true_rtx)
5458 /* If the code changed, return a whole new comparison. */
5459 if (new_code != code)
5460 return gen_rtx_fmt_ee (new_code, mode, op0, op1);
5462 /* Otherwise, keep this operation, but maybe change its operands.
5463 This also converts (ne (compare FOO BAR) 0) to (ne FOO BAR). */
5464 SUBST (XEXP (x, 0), op0);
5465 SUBST (XEXP (x, 1), op1);
5470 return simplify_if_then_else (x);
5476 /* If we are processing SET_DEST, we are done. */
5480 return expand_compound_operation (x);
5483 return simplify_set (x);
5487 return simplify_logical (x);
5494 /* If this is a shift by a constant amount, simplify it. */
5495 if (CONST_INT_P (XEXP (x, 1)))
5496 return simplify_shift_const (x, code, mode, XEXP (x, 0),
5497 INTVAL (XEXP (x, 1)));
5499 else if (SHIFT_COUNT_TRUNCATED && !REG_P (XEXP (x, 1)))
5501 force_to_mode (XEXP (x, 1), GET_MODE (XEXP (x, 1)),
5503 << exact_log2 (GET_MODE_BITSIZE (GET_MODE (x))))
5515 /* Simplify X, an IF_THEN_ELSE expression. Return the new expression. */
5518 simplify_if_then_else (rtx x)
5520 enum machine_mode mode = GET_MODE (x);
5521 rtx cond = XEXP (x, 0);
5522 rtx true_rtx = XEXP (x, 1);
5523 rtx false_rtx = XEXP (x, 2);
5524 enum rtx_code true_code = GET_CODE (cond);
5525 int comparison_p = COMPARISON_P (cond);
5528 enum rtx_code false_code;
5531 /* Simplify storing of the truth value. */
5532 if (comparison_p && true_rtx == const_true_rtx && false_rtx == const0_rtx)
5533 return simplify_gen_relational (true_code, mode, VOIDmode,
5534 XEXP (cond, 0), XEXP (cond, 1));
5536 /* Also when the truth value has to be reversed. */
5538 && true_rtx == const0_rtx && false_rtx == const_true_rtx
5539 && (reversed = reversed_comparison (cond, mode)))
5542 /* Sometimes we can simplify the arm of an IF_THEN_ELSE if a register used
5543 in it is being compared against certain values. Get the true and false
5544 comparisons and see if that says anything about the value of each arm. */
5547 && ((false_code = reversed_comparison_code (cond, NULL))
5549 && REG_P (XEXP (cond, 0)))
5552 rtx from = XEXP (cond, 0);
5553 rtx true_val = XEXP (cond, 1);
5554 rtx false_val = true_val;
5557 /* If FALSE_CODE is EQ, swap the codes and arms. */
5559 if (false_code == EQ)
5561 swapped = 1, true_code = EQ, false_code = NE;
5562 temp = true_rtx, true_rtx = false_rtx, false_rtx = temp;
5565 /* If we are comparing against zero and the expression being tested has
5566 only a single bit that might be nonzero, that is its value when it is
5567 not equal to zero. Similarly if it is known to be -1 or 0. */
5569 if (true_code == EQ && true_val == const0_rtx
5570 && exact_log2 (nzb = nonzero_bits (from, GET_MODE (from))) >= 0)
5573 false_val = GEN_INT (trunc_int_for_mode (nzb, GET_MODE (from)));
5575 else if (true_code == EQ && true_val == const0_rtx
5576 && (num_sign_bit_copies (from, GET_MODE (from))
5577 == GET_MODE_BITSIZE (GET_MODE (from))))
5580 false_val = constm1_rtx;
5583 /* Now simplify an arm if we know the value of the register in the
5584 branch and it is used in the arm. Be careful due to the potential
5585 of locally-shared RTL. */
5587 if (reg_mentioned_p (from, true_rtx))
5588 true_rtx = subst (known_cond (copy_rtx (true_rtx), true_code,
5590 pc_rtx, pc_rtx, 0, 0);
5591 if (reg_mentioned_p (from, false_rtx))
5592 false_rtx = subst (known_cond (copy_rtx (false_rtx), false_code,
5594 pc_rtx, pc_rtx, 0, 0);
5596 SUBST (XEXP (x, 1), swapped ? false_rtx : true_rtx);
5597 SUBST (XEXP (x, 2), swapped ? true_rtx : false_rtx);
5599 true_rtx = XEXP (x, 1);
5600 false_rtx = XEXP (x, 2);
5601 true_code = GET_CODE (cond);
5604 /* If we have (if_then_else FOO (pc) (label_ref BAR)) and FOO can be
5605 reversed, do so to avoid needing two sets of patterns for
5606 subtract-and-branch insns. Similarly if we have a constant in the true
5607 arm, the false arm is the same as the first operand of the comparison, or
5608 the false arm is more complicated than the true arm. */
5611 && reversed_comparison_code (cond, NULL) != UNKNOWN
5612 && (true_rtx == pc_rtx
5613 || (CONSTANT_P (true_rtx)
5614 && !CONST_INT_P (false_rtx) && false_rtx != pc_rtx)
5615 || true_rtx == const0_rtx
5616 || (OBJECT_P (true_rtx) && !OBJECT_P (false_rtx))
5617 || (GET_CODE (true_rtx) == SUBREG && OBJECT_P (SUBREG_REG (true_rtx))
5618 && !OBJECT_P (false_rtx))
5619 || reg_mentioned_p (true_rtx, false_rtx)
5620 || rtx_equal_p (false_rtx, XEXP (cond, 0))))
5622 true_code = reversed_comparison_code (cond, NULL);
5623 SUBST (XEXP (x, 0), reversed_comparison (cond, GET_MODE (cond)));
5624 SUBST (XEXP (x, 1), false_rtx);
5625 SUBST (XEXP (x, 2), true_rtx);
5627 temp = true_rtx, true_rtx = false_rtx, false_rtx = temp;
5630 /* It is possible that the conditional has been simplified out. */
5631 true_code = GET_CODE (cond);
5632 comparison_p = COMPARISON_P (cond);
5635 /* If the two arms are identical, we don't need the comparison. */
5637 if (rtx_equal_p (true_rtx, false_rtx) && ! side_effects_p (cond))
5640 /* Convert a == b ? b : a to "a". */
5641 if (true_code == EQ && ! side_effects_p (cond)
5642 && !HONOR_NANS (mode)
5643 && rtx_equal_p (XEXP (cond, 0), false_rtx)
5644 && rtx_equal_p (XEXP (cond, 1), true_rtx))
5646 else if (true_code == NE && ! side_effects_p (cond)
5647 && !HONOR_NANS (mode)
5648 && rtx_equal_p (XEXP (cond, 0), true_rtx)
5649 && rtx_equal_p (XEXP (cond, 1), false_rtx))
5652 /* Look for cases where we have (abs x) or (neg (abs X)). */
5654 if (GET_MODE_CLASS (mode) == MODE_INT
5656 && XEXP (cond, 1) == const0_rtx
5657 && GET_CODE (false_rtx) == NEG
5658 && rtx_equal_p (true_rtx, XEXP (false_rtx, 0))
5659 && rtx_equal_p (true_rtx, XEXP (cond, 0))
5660 && ! side_effects_p (true_rtx))
5665 return simplify_gen_unary (ABS, mode, true_rtx, mode);
5669 simplify_gen_unary (NEG, mode,
5670 simplify_gen_unary (ABS, mode, true_rtx, mode),
5676 /* Look for MIN or MAX. */
5678 if ((! FLOAT_MODE_P (mode) || flag_unsafe_math_optimizations)
5680 && rtx_equal_p (XEXP (cond, 0), true_rtx)
5681 && rtx_equal_p (XEXP (cond, 1), false_rtx)
5682 && ! side_effects_p (cond))
5687 return simplify_gen_binary (SMAX, mode, true_rtx, false_rtx);
5690 return simplify_gen_binary (SMIN, mode, true_rtx, false_rtx);
5693 return simplify_gen_binary (UMAX, mode, true_rtx, false_rtx);
5696 return simplify_gen_binary (UMIN, mode, true_rtx, false_rtx);
5701 /* If we have (if_then_else COND (OP Z C1) Z) and OP is an identity when its
5702 second operand is zero, this can be done as (OP Z (mult COND C2)) where
5703 C2 = C1 * STORE_FLAG_VALUE. Similarly if OP has an outer ZERO_EXTEND or
5704 SIGN_EXTEND as long as Z is already extended (so we don't destroy it).
5705 We can do this kind of thing in some cases when STORE_FLAG_VALUE is
5706 neither 1 or -1, but it isn't worth checking for. */
5708 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
5710 && GET_MODE_CLASS (mode) == MODE_INT
5711 && ! side_effects_p (x))
5713 rtx t = make_compound_operation (true_rtx, SET);
5714 rtx f = make_compound_operation (false_rtx, SET);
5715 rtx cond_op0 = XEXP (cond, 0);
5716 rtx cond_op1 = XEXP (cond, 1);
5717 enum rtx_code op = UNKNOWN, extend_op = UNKNOWN;
5718 enum machine_mode m = mode;
5719 rtx z = 0, c1 = NULL_RTX;
5721 if ((GET_CODE (t) == PLUS || GET_CODE (t) == MINUS
5722 || GET_CODE (t) == IOR || GET_CODE (t) == XOR
5723 || GET_CODE (t) == ASHIFT
5724 || GET_CODE (t) == LSHIFTRT || GET_CODE (t) == ASHIFTRT)
5725 && rtx_equal_p (XEXP (t, 0), f))
5726 c1 = XEXP (t, 1), op = GET_CODE (t), z = f;
5728 /* If an identity-zero op is commutative, check whether there
5729 would be a match if we swapped the operands. */
5730 else if ((GET_CODE (t) == PLUS || GET_CODE (t) == IOR
5731 || GET_CODE (t) == XOR)
5732 && rtx_equal_p (XEXP (t, 1), f))
5733 c1 = XEXP (t, 0), op = GET_CODE (t), z = f;
5734 else if (GET_CODE (t) == SIGN_EXTEND
5735 && (GET_CODE (XEXP (t, 0)) == PLUS
5736 || GET_CODE (XEXP (t, 0)) == MINUS
5737 || GET_CODE (XEXP (t, 0)) == IOR
5738 || GET_CODE (XEXP (t, 0)) == XOR
5739 || GET_CODE (XEXP (t, 0)) == ASHIFT
5740 || GET_CODE (XEXP (t, 0)) == LSHIFTRT
5741 || GET_CODE (XEXP (t, 0)) == ASHIFTRT)
5742 && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG
5743 && subreg_lowpart_p (XEXP (XEXP (t, 0), 0))
5744 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f)
5745 && (num_sign_bit_copies (f, GET_MODE (f))
5747 (GET_MODE_BITSIZE (mode)
5748 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t, 0), 0))))))
5750 c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0));
5751 extend_op = SIGN_EXTEND;
5752 m = GET_MODE (XEXP (t, 0));
5754 else if (GET_CODE (t) == SIGN_EXTEND
5755 && (GET_CODE (XEXP (t, 0)) == PLUS
5756 || GET_CODE (XEXP (t, 0)) == IOR
5757 || GET_CODE (XEXP (t, 0)) == XOR)
5758 && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG
5759 && subreg_lowpart_p (XEXP (XEXP (t, 0), 1))
5760 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f)
5761 && (num_sign_bit_copies (f, GET_MODE (f))
5763 (GET_MODE_BITSIZE (mode)
5764 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t, 0), 1))))))
5766 c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0));
5767 extend_op = SIGN_EXTEND;
5768 m = GET_MODE (XEXP (t, 0));
5770 else if (GET_CODE (t) == ZERO_EXTEND
5771 && (GET_CODE (XEXP (t, 0)) == PLUS
5772 || GET_CODE (XEXP (t, 0)) == MINUS
5773 || GET_CODE (XEXP (t, 0)) == IOR
5774 || GET_CODE (XEXP (t, 0)) == XOR
5775 || GET_CODE (XEXP (t, 0)) == ASHIFT
5776 || GET_CODE (XEXP (t, 0)) == LSHIFTRT
5777 || GET_CODE (XEXP (t, 0)) == ASHIFTRT)
5778 && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG
5779 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5780 && subreg_lowpart_p (XEXP (XEXP (t, 0), 0))
5781 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f)
5782 && ((nonzero_bits (f, GET_MODE (f))
5783 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t, 0), 0))))
5786 c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0));
5787 extend_op = ZERO_EXTEND;
5788 m = GET_MODE (XEXP (t, 0));
5790 else if (GET_CODE (t) == ZERO_EXTEND
5791 && (GET_CODE (XEXP (t, 0)) == PLUS
5792 || GET_CODE (XEXP (t, 0)) == IOR
5793 || GET_CODE (XEXP (t, 0)) == XOR)
5794 && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG
5795 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5796 && subreg_lowpart_p (XEXP (XEXP (t, 0), 1))
5797 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f)
5798 && ((nonzero_bits (f, GET_MODE (f))
5799 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t, 0), 1))))
5802 c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0));
5803 extend_op = ZERO_EXTEND;
5804 m = GET_MODE (XEXP (t, 0));
5809 temp = subst (simplify_gen_relational (true_code, m, VOIDmode,
5810 cond_op0, cond_op1),
5811 pc_rtx, pc_rtx, 0, 0);
5812 temp = simplify_gen_binary (MULT, m, temp,
5813 simplify_gen_binary (MULT, m, c1,
5815 temp = subst (temp, pc_rtx, pc_rtx, 0, 0);
5816 temp = simplify_gen_binary (op, m, gen_lowpart (m, z), temp);
5818 if (extend_op != UNKNOWN)
5819 temp = simplify_gen_unary (extend_op, mode, temp, m);
5825 /* If we have (if_then_else (ne A 0) C1 0) and either A is known to be 0 or
5826 1 and C1 is a single bit or A is known to be 0 or -1 and C1 is the
5827 negation of a single bit, we can convert this operation to a shift. We
5828 can actually do this more generally, but it doesn't seem worth it. */
5830 if (true_code == NE && XEXP (cond, 1) == const0_rtx
5831 && false_rtx == const0_rtx && CONST_INT_P (true_rtx)
5832 && ((1 == nonzero_bits (XEXP (cond, 0), mode)
5833 && (i = exact_log2 (INTVAL (true_rtx))) >= 0)
5834 || ((num_sign_bit_copies (XEXP (cond, 0), mode)
5835 == GET_MODE_BITSIZE (mode))
5836 && (i = exact_log2 (-INTVAL (true_rtx))) >= 0)))
5838 simplify_shift_const (NULL_RTX, ASHIFT, mode,
5839 gen_lowpart (mode, XEXP (cond, 0)), i);
5841 /* (IF_THEN_ELSE (NE REG 0) (0) (8)) is REG for nonzero_bits (REG) == 8. */
5842 if (true_code == NE && XEXP (cond, 1) == const0_rtx
5843 && false_rtx == const0_rtx && CONST_INT_P (true_rtx)
5844 && GET_MODE (XEXP (cond, 0)) == mode
5845 && (INTVAL (true_rtx) & GET_MODE_MASK (mode))
5846 == nonzero_bits (XEXP (cond, 0), mode)
5847 && (i = exact_log2 (INTVAL (true_rtx) & GET_MODE_MASK (mode))) >= 0)
5848 return XEXP (cond, 0);
5853 /* Simplify X, a SET expression. Return the new expression. */
5856 simplify_set (rtx x)
5858 rtx src = SET_SRC (x);
5859 rtx dest = SET_DEST (x);
5860 enum machine_mode mode
5861 = GET_MODE (src) != VOIDmode ? GET_MODE (src) : GET_MODE (dest);
5865 /* (set (pc) (return)) gets written as (return). */
5866 if (GET_CODE (dest) == PC && GET_CODE (src) == RETURN)
5869 /* Now that we know for sure which bits of SRC we are using, see if we can
5870 simplify the expression for the object knowing that we only need the
5873 if (GET_MODE_CLASS (mode) == MODE_INT
5874 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
5876 src = force_to_mode (src, mode, ~(HOST_WIDE_INT) 0, 0);
5877 SUBST (SET_SRC (x), src);
5880 /* If we are setting CC0 or if the source is a COMPARE, look for the use of
5881 the comparison result and try to simplify it unless we already have used
5882 undobuf.other_insn. */
5883 if ((GET_MODE_CLASS (mode) == MODE_CC
5884 || GET_CODE (src) == COMPARE
5886 && (cc_use = find_single_use (dest, subst_insn, &other_insn)) != 0
5887 && (undobuf.other_insn == 0 || other_insn == undobuf.other_insn)
5888 && COMPARISON_P (*cc_use)
5889 && rtx_equal_p (XEXP (*cc_use, 0), dest))
5891 enum rtx_code old_code = GET_CODE (*cc_use);
5892 enum rtx_code new_code;
5894 int other_changed = 0;
5895 enum machine_mode compare_mode = GET_MODE (dest);
5897 if (GET_CODE (src) == COMPARE)
5898 op0 = XEXP (src, 0), op1 = XEXP (src, 1);
5900 op0 = src, op1 = CONST0_RTX (GET_MODE (src));
5902 tmp = simplify_relational_operation (old_code, compare_mode, VOIDmode,
5905 new_code = old_code;
5906 else if (!CONSTANT_P (tmp))
5908 new_code = GET_CODE (tmp);
5909 op0 = XEXP (tmp, 0);
5910 op1 = XEXP (tmp, 1);
5914 rtx pat = PATTERN (other_insn);
5915 undobuf.other_insn = other_insn;
5916 SUBST (*cc_use, tmp);
5918 /* Attempt to simplify CC user. */
5919 if (GET_CODE (pat) == SET)
5921 rtx new_rtx = simplify_rtx (SET_SRC (pat));
5922 if (new_rtx != NULL_RTX)
5923 SUBST (SET_SRC (pat), new_rtx);
5926 /* Convert X into a no-op move. */
5927 SUBST (SET_DEST (x), pc_rtx);
5928 SUBST (SET_SRC (x), pc_rtx);
5932 /* Simplify our comparison, if possible. */
5933 new_code = simplify_comparison (new_code, &op0, &op1);
5935 #ifdef SELECT_CC_MODE
5936 /* If this machine has CC modes other than CCmode, check to see if we
5937 need to use a different CC mode here. */
5938 if (GET_MODE_CLASS (GET_MODE (op0)) == MODE_CC)
5939 compare_mode = GET_MODE (op0);
5941 compare_mode = SELECT_CC_MODE (new_code, op0, op1);
5944 /* If the mode changed, we have to change SET_DEST, the mode in the
5945 compare, and the mode in the place SET_DEST is used. If SET_DEST is
5946 a hard register, just build new versions with the proper mode. If it
5947 is a pseudo, we lose unless it is only time we set the pseudo, in
5948 which case we can safely change its mode. */
5949 if (compare_mode != GET_MODE (dest))
5951 if (can_change_dest_mode (dest, 0, compare_mode))
5953 unsigned int regno = REGNO (dest);
5956 if (regno < FIRST_PSEUDO_REGISTER)
5957 new_dest = gen_rtx_REG (compare_mode, regno);
5960 SUBST_MODE (regno_reg_rtx[regno], compare_mode);
5961 new_dest = regno_reg_rtx[regno];
5964 SUBST (SET_DEST (x), new_dest);
5965 SUBST (XEXP (*cc_use, 0), new_dest);
5972 #endif /* SELECT_CC_MODE */
5974 /* If the code changed, we have to build a new comparison in
5975 undobuf.other_insn. */
5976 if (new_code != old_code)
5978 int other_changed_previously = other_changed;
5979 unsigned HOST_WIDE_INT mask;
5980 rtx old_cc_use = *cc_use;
5982 SUBST (*cc_use, gen_rtx_fmt_ee (new_code, GET_MODE (*cc_use),
5986 /* If the only change we made was to change an EQ into an NE or
5987 vice versa, OP0 has only one bit that might be nonzero, and OP1
5988 is zero, check if changing the user of the condition code will
5989 produce a valid insn. If it won't, we can keep the original code
5990 in that insn by surrounding our operation with an XOR. */
5992 if (((old_code == NE && new_code == EQ)
5993 || (old_code == EQ && new_code == NE))
5994 && ! other_changed_previously && op1 == const0_rtx
5995 && GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
5996 && exact_log2 (mask = nonzero_bits (op0, GET_MODE (op0))) >= 0)
5998 rtx pat = PATTERN (other_insn), note = 0;
6000 if ((recog_for_combine (&pat, other_insn, ¬e) < 0
6001 && ! check_asm_operands (pat)))
6003 *cc_use = old_cc_use;
6006 op0 = simplify_gen_binary (XOR, GET_MODE (op0),
6007 op0, GEN_INT (mask));
6013 undobuf.other_insn = other_insn;
6015 /* Otherwise, if we didn't previously have a COMPARE in the
6016 correct mode, we need one. */
6017 if (GET_CODE (src) != COMPARE || GET_MODE (src) != compare_mode)
6019 SUBST (SET_SRC (x), gen_rtx_COMPARE (compare_mode, op0, op1));
6022 else if (GET_MODE (op0) == compare_mode && op1 == const0_rtx)
6024 SUBST (SET_SRC (x), op0);
6027 /* Otherwise, update the COMPARE if needed. */
6028 else if (XEXP (src, 0) != op0 || XEXP (src, 1) != op1)
6030 SUBST (SET_SRC (x), gen_rtx_COMPARE (compare_mode, op0, op1));
6036 /* Get SET_SRC in a form where we have placed back any
6037 compound expressions. Then do the checks below. */
6038 src = make_compound_operation (src, SET);
6039 SUBST (SET_SRC (x), src);
6042 /* If we have (set x (subreg:m1 (op:m2 ...) 0)) with OP being some operation,
6043 and X being a REG or (subreg (reg)), we may be able to convert this to
6044 (set (subreg:m2 x) (op)).
6046 We can always do this if M1 is narrower than M2 because that means that
6047 we only care about the low bits of the result.
6049 However, on machines without WORD_REGISTER_OPERATIONS defined, we cannot
6050 perform a narrower operation than requested since the high-order bits will
6051 be undefined. On machine where it is defined, this transformation is safe
6052 as long as M1 and M2 have the same number of words. */
6054 if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src)
6055 && !OBJECT_P (SUBREG_REG (src))
6056 && (((GET_MODE_SIZE (GET_MODE (src)) + (UNITS_PER_WORD - 1))
6058 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (src)))
6059 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD))
6060 #ifndef WORD_REGISTER_OPERATIONS
6061 && (GET_MODE_SIZE (GET_MODE (src))
6062 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (src))))
6064 #ifdef CANNOT_CHANGE_MODE_CLASS
6065 && ! (REG_P (dest) && REGNO (dest) < FIRST_PSEUDO_REGISTER
6066 && REG_CANNOT_CHANGE_MODE_P (REGNO (dest),
6067 GET_MODE (SUBREG_REG (src)),
6071 || (GET_CODE (dest) == SUBREG
6072 && REG_P (SUBREG_REG (dest)))))
6074 SUBST (SET_DEST (x),
6075 gen_lowpart (GET_MODE (SUBREG_REG (src)),
6077 SUBST (SET_SRC (x), SUBREG_REG (src));
6079 src = SET_SRC (x), dest = SET_DEST (x);
6083 /* If we have (set (cc0) (subreg ...)), we try to remove the subreg
6086 && GET_CODE (src) == SUBREG
6087 && subreg_lowpart_p (src)
6088 && (GET_MODE_BITSIZE (GET_MODE (src))
6089 < GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (src)))))
6091 rtx inner = SUBREG_REG (src);
6092 enum machine_mode inner_mode = GET_MODE (inner);
6094 /* Here we make sure that we don't have a sign bit on. */
6095 if (GET_MODE_BITSIZE (inner_mode) <= HOST_BITS_PER_WIDE_INT
6096 && (nonzero_bits (inner, inner_mode)
6097 < ((unsigned HOST_WIDE_INT) 1
6098 << (GET_MODE_BITSIZE (GET_MODE (src)) - 1))))
6100 SUBST (SET_SRC (x), inner);
6106 #ifdef LOAD_EXTEND_OP
6107 /* If we have (set FOO (subreg:M (mem:N BAR) 0)) with M wider than N, this
6108 would require a paradoxical subreg. Replace the subreg with a
6109 zero_extend to avoid the reload that would otherwise be required. */
6111 if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src)
6112 && INTEGRAL_MODE_P (GET_MODE (SUBREG_REG (src)))
6113 && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src))) != UNKNOWN
6114 && SUBREG_BYTE (src) == 0
6115 && (GET_MODE_SIZE (GET_MODE (src))
6116 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (src))))
6117 && MEM_P (SUBREG_REG (src)))
6120 gen_rtx_fmt_e (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src))),
6121 GET_MODE (src), SUBREG_REG (src)));
6127 /* If we don't have a conditional move, SET_SRC is an IF_THEN_ELSE, and we
6128 are comparing an item known to be 0 or -1 against 0, use a logical
6129 operation instead. Check for one of the arms being an IOR of the other
6130 arm with some value. We compute three terms to be IOR'ed together. In
6131 practice, at most two will be nonzero. Then we do the IOR's. */
6133 if (GET_CODE (dest) != PC
6134 && GET_CODE (src) == IF_THEN_ELSE
6135 && GET_MODE_CLASS (GET_MODE (src)) == MODE_INT
6136 && (GET_CODE (XEXP (src, 0)) == EQ || GET_CODE (XEXP (src, 0)) == NE)
6137 && XEXP (XEXP (src, 0), 1) == const0_rtx
6138 && GET_MODE (src) == GET_MODE (XEXP (XEXP (src, 0), 0))
6139 #ifdef HAVE_conditional_move
6140 && ! can_conditionally_move_p (GET_MODE (src))
6142 && (num_sign_bit_copies (XEXP (XEXP (src, 0), 0),
6143 GET_MODE (XEXP (XEXP (src, 0), 0)))
6144 == GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (src, 0), 0))))
6145 && ! side_effects_p (src))
6147 rtx true_rtx = (GET_CODE (XEXP (src, 0)) == NE
6148 ? XEXP (src, 1) : XEXP (src, 2));
6149 rtx false_rtx = (GET_CODE (XEXP (src, 0)) == NE
6150 ? XEXP (src, 2) : XEXP (src, 1));
6151 rtx term1 = const0_rtx, term2, term3;
6153 if (GET_CODE (true_rtx) == IOR
6154 && rtx_equal_p (XEXP (true_rtx, 0), false_rtx))
6155 term1 = false_rtx, true_rtx = XEXP (true_rtx, 1), false_rtx = const0_rtx;
6156 else if (GET_CODE (true_rtx) == IOR
6157 && rtx_equal_p (XEXP (true_rtx, 1), false_rtx))
6158 term1 = false_rtx, true_rtx = XEXP (true_rtx, 0), false_rtx = const0_rtx;
6159 else if (GET_CODE (false_rtx) == IOR
6160 && rtx_equal_p (XEXP (false_rtx, 0), true_rtx))
6161 term1 = true_rtx, false_rtx = XEXP (false_rtx, 1), true_rtx = const0_rtx;
6162 else if (GET_CODE (false_rtx) == IOR
6163 && rtx_equal_p (XEXP (false_rtx, 1), true_rtx))
6164 term1 = true_rtx, false_rtx = XEXP (false_rtx, 0), true_rtx = const0_rtx;
6166 term2 = simplify_gen_binary (AND, GET_MODE (src),
6167 XEXP (XEXP (src, 0), 0), true_rtx);
6168 term3 = simplify_gen_binary (AND, GET_MODE (src),
6169 simplify_gen_unary (NOT, GET_MODE (src),
6170 XEXP (XEXP (src, 0), 0),
6175 simplify_gen_binary (IOR, GET_MODE (src),
6176 simplify_gen_binary (IOR, GET_MODE (src),
6183 /* If either SRC or DEST is a CLOBBER of (const_int 0), make this
6184 whole thing fail. */
6185 if (GET_CODE (src) == CLOBBER && XEXP (src, 0) == const0_rtx)
6187 else if (GET_CODE (dest) == CLOBBER && XEXP (dest, 0) == const0_rtx)
6190 /* Convert this into a field assignment operation, if possible. */
6191 return make_field_assignment (x);
6194 /* Simplify, X, and AND, IOR, or XOR operation, and return the simplified
6198 simplify_logical (rtx x)
6200 enum machine_mode mode = GET_MODE (x);
6201 rtx op0 = XEXP (x, 0);
6202 rtx op1 = XEXP (x, 1);
6204 switch (GET_CODE (x))
6207 /* We can call simplify_and_const_int only if we don't lose
6208 any (sign) bits when converting INTVAL (op1) to
6209 "unsigned HOST_WIDE_INT". */
6210 if (CONST_INT_P (op1)
6211 && (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
6212 || INTVAL (op1) > 0))
6214 x = simplify_and_const_int (x, mode, op0, INTVAL (op1));
6215 if (GET_CODE (x) != AND)
6222 /* If we have any of (and (ior A B) C) or (and (xor A B) C),
6223 apply the distributive law and then the inverse distributive
6224 law to see if things simplify. */
6225 if (GET_CODE (op0) == IOR || GET_CODE (op0) == XOR)
6227 rtx result = distribute_and_simplify_rtx (x, 0);
6231 if (GET_CODE (op1) == IOR || GET_CODE (op1) == XOR)
6233 rtx result = distribute_and_simplify_rtx (x, 1);
6240 /* If we have (ior (and A B) C), apply the distributive law and then
6241 the inverse distributive law to see if things simplify. */
6243 if (GET_CODE (op0) == AND)
6245 rtx result = distribute_and_simplify_rtx (x, 0);
6250 if (GET_CODE (op1) == AND)
6252 rtx result = distribute_and_simplify_rtx (x, 1);
6265 /* We consider ZERO_EXTRACT, SIGN_EXTRACT, and SIGN_EXTEND as "compound
6266 operations" because they can be replaced with two more basic operations.
6267 ZERO_EXTEND is also considered "compound" because it can be replaced with
6268 an AND operation, which is simpler, though only one operation.
6270 The function expand_compound_operation is called with an rtx expression
6271 and will convert it to the appropriate shifts and AND operations,
6272 simplifying at each stage.
6274 The function make_compound_operation is called to convert an expression
6275 consisting of shifts and ANDs into the equivalent compound expression.
6276 It is the inverse of this function, loosely speaking. */
6279 expand_compound_operation (rtx x)
6281 unsigned HOST_WIDE_INT pos = 0, len;
6283 unsigned int modewidth;
6286 switch (GET_CODE (x))
6291 /* We can't necessarily use a const_int for a multiword mode;
6292 it depends on implicitly extending the value.
6293 Since we don't know the right way to extend it,
6294 we can't tell whether the implicit way is right.
6296 Even for a mode that is no wider than a const_int,
6297 we can't win, because we need to sign extend one of its bits through
6298 the rest of it, and we don't know which bit. */
6299 if (CONST_INT_P (XEXP (x, 0)))
6302 /* Return if (subreg:MODE FROM 0) is not a safe replacement for
6303 (zero_extend:MODE FROM) or (sign_extend:MODE FROM). It is for any MEM
6304 because (SUBREG (MEM...)) is guaranteed to cause the MEM to be
6305 reloaded. If not for that, MEM's would very rarely be safe.
6307 Reject MODEs bigger than a word, because we might not be able
6308 to reference a two-register group starting with an arbitrary register
6309 (and currently gen_lowpart might crash for a SUBREG). */
6311 if (GET_MODE_SIZE (GET_MODE (XEXP (x, 0))) > UNITS_PER_WORD)
6314 /* Reject MODEs that aren't scalar integers because turning vector
6315 or complex modes into shifts causes problems. */
6317 if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x, 0))))
6320 len = GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)));
6321 /* If the inner object has VOIDmode (the only way this can happen
6322 is if it is an ASM_OPERANDS), we can't do anything since we don't
6323 know how much masking to do. */
6332 /* ... fall through ... */
6335 /* If the operand is a CLOBBER, just return it. */
6336 if (GET_CODE (XEXP (x, 0)) == CLOBBER)
6339 if (!CONST_INT_P (XEXP (x, 1))
6340 || !CONST_INT_P (XEXP (x, 2))
6341 || GET_MODE (XEXP (x, 0)) == VOIDmode)
6344 /* Reject MODEs that aren't scalar integers because turning vector
6345 or complex modes into shifts causes problems. */
6347 if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x, 0))))
6350 len = INTVAL (XEXP (x, 1));
6351 pos = INTVAL (XEXP (x, 2));
6353 /* This should stay within the object being extracted, fail otherwise. */
6354 if (len + pos > GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))))
6357 if (BITS_BIG_ENDIAN)
6358 pos = GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - len - pos;
6365 /* Convert sign extension to zero extension, if we know that the high
6366 bit is not set, as this is easier to optimize. It will be converted
6367 back to cheaper alternative in make_extraction. */
6368 if (GET_CODE (x) == SIGN_EXTEND
6369 && (GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
6370 && ((nonzero_bits (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
6371 & ~(((unsigned HOST_WIDE_INT)
6372 GET_MODE_MASK (GET_MODE (XEXP (x, 0))))
6376 rtx temp = gen_rtx_ZERO_EXTEND (GET_MODE (x), XEXP (x, 0));
6377 rtx temp2 = expand_compound_operation (temp);
6379 /* Make sure this is a profitable operation. */
6380 if (rtx_cost (x, SET, optimize_this_for_speed_p)
6381 > rtx_cost (temp2, SET, optimize_this_for_speed_p))
6383 else if (rtx_cost (x, SET, optimize_this_for_speed_p)
6384 > rtx_cost (temp, SET, optimize_this_for_speed_p))
6390 /* We can optimize some special cases of ZERO_EXTEND. */
6391 if (GET_CODE (x) == ZERO_EXTEND)
6393 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI if we
6394 know that the last value didn't have any inappropriate bits
6396 if (GET_CODE (XEXP (x, 0)) == TRUNCATE
6397 && GET_MODE (XEXP (XEXP (x, 0), 0)) == GET_MODE (x)
6398 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
6399 && (nonzero_bits (XEXP (XEXP (x, 0), 0), GET_MODE (x))
6400 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
6401 return XEXP (XEXP (x, 0), 0);
6403 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
6404 if (GET_CODE (XEXP (x, 0)) == SUBREG
6405 && GET_MODE (SUBREG_REG (XEXP (x, 0))) == GET_MODE (x)
6406 && subreg_lowpart_p (XEXP (x, 0))
6407 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
6408 && (nonzero_bits (SUBREG_REG (XEXP (x, 0)), GET_MODE (x))
6409 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
6410 return SUBREG_REG (XEXP (x, 0));
6412 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI when foo
6413 is a comparison and STORE_FLAG_VALUE permits. This is like
6414 the first case, but it works even when GET_MODE (x) is larger
6415 than HOST_WIDE_INT. */
6416 if (GET_CODE (XEXP (x, 0)) == TRUNCATE
6417 && GET_MODE (XEXP (XEXP (x, 0), 0)) == GET_MODE (x)
6418 && COMPARISON_P (XEXP (XEXP (x, 0), 0))
6419 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
6420 <= HOST_BITS_PER_WIDE_INT)
6421 && ((HOST_WIDE_INT) STORE_FLAG_VALUE
6422 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
6423 return XEXP (XEXP (x, 0), 0);
6425 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
6426 if (GET_CODE (XEXP (x, 0)) == SUBREG
6427 && GET_MODE (SUBREG_REG (XEXP (x, 0))) == GET_MODE (x)
6428 && subreg_lowpart_p (XEXP (x, 0))
6429 && COMPARISON_P (SUBREG_REG (XEXP (x, 0)))
6430 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
6431 <= HOST_BITS_PER_WIDE_INT)
6432 && ((HOST_WIDE_INT) STORE_FLAG_VALUE
6433 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
6434 return SUBREG_REG (XEXP (x, 0));
6438 /* If we reach here, we want to return a pair of shifts. The inner
6439 shift is a left shift of BITSIZE - POS - LEN bits. The outer
6440 shift is a right shift of BITSIZE - LEN bits. It is arithmetic or
6441 logical depending on the value of UNSIGNEDP.
6443 If this was a ZERO_EXTEND or ZERO_EXTRACT, this pair of shifts will be
6444 converted into an AND of a shift.
6446 We must check for the case where the left shift would have a negative
6447 count. This can happen in a case like (x >> 31) & 255 on machines
6448 that can't shift by a constant. On those machines, we would first
6449 combine the shift with the AND to produce a variable-position
6450 extraction. Then the constant of 31 would be substituted in to produce
6451 a such a position. */
6453 modewidth = GET_MODE_BITSIZE (GET_MODE (x));
6454 if (modewidth + len >= pos)
6456 enum machine_mode mode = GET_MODE (x);
6457 tem = gen_lowpart (mode, XEXP (x, 0));
6458 if (!tem || GET_CODE (tem) == CLOBBER)
6460 tem = simplify_shift_const (NULL_RTX, ASHIFT, mode,
6461 tem, modewidth - pos - len);
6462 tem = simplify_shift_const (NULL_RTX, unsignedp ? LSHIFTRT : ASHIFTRT,
6463 mode, tem, modewidth - len);
6465 else if (unsignedp && len < HOST_BITS_PER_WIDE_INT)
6466 tem = simplify_and_const_int (NULL_RTX, GET_MODE (x),
6467 simplify_shift_const (NULL_RTX, LSHIFTRT,
6470 ((HOST_WIDE_INT) 1 << len) - 1);
6472 /* Any other cases we can't handle. */
6475 /* If we couldn't do this for some reason, return the original
6477 if (GET_CODE (tem) == CLOBBER)
6483 /* X is a SET which contains an assignment of one object into
6484 a part of another (such as a bit-field assignment, STRICT_LOW_PART,
6485 or certain SUBREGS). If possible, convert it into a series of
6488 We half-heartedly support variable positions, but do not at all
6489 support variable lengths. */
6492 expand_field_assignment (const_rtx x)
6495 rtx pos; /* Always counts from low bit. */
6497 rtx mask, cleared, masked;
6498 enum machine_mode compute_mode;
6500 /* Loop until we find something we can't simplify. */
6503 if (GET_CODE (SET_DEST (x)) == STRICT_LOW_PART
6504 && GET_CODE (XEXP (SET_DEST (x), 0)) == SUBREG)
6506 inner = SUBREG_REG (XEXP (SET_DEST (x), 0));
6507 len = GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0)));
6508 pos = GEN_INT (subreg_lsb (XEXP (SET_DEST (x), 0)));
6510 else if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
6511 && CONST_INT_P (XEXP (SET_DEST (x), 1)))
6513 inner = XEXP (SET_DEST (x), 0);
6514 len = INTVAL (XEXP (SET_DEST (x), 1));
6515 pos = XEXP (SET_DEST (x), 2);
6517 /* A constant position should stay within the width of INNER. */
6518 if (CONST_INT_P (pos)
6519 && INTVAL (pos) + len > GET_MODE_BITSIZE (GET_MODE (inner)))
6522 if (BITS_BIG_ENDIAN)
6524 if (CONST_INT_P (pos))
6525 pos = GEN_INT (GET_MODE_BITSIZE (GET_MODE (inner)) - len
6527 else if (GET_CODE (pos) == MINUS
6528 && CONST_INT_P (XEXP (pos, 1))
6529 && (INTVAL (XEXP (pos, 1))
6530 == GET_MODE_BITSIZE (GET_MODE (inner)) - len))
6531 /* If position is ADJUST - X, new position is X. */
6532 pos = XEXP (pos, 0);
6534 pos = simplify_gen_binary (MINUS, GET_MODE (pos),
6535 GEN_INT (GET_MODE_BITSIZE (
6542 /* A SUBREG between two modes that occupy the same numbers of words
6543 can be done by moving the SUBREG to the source. */
6544 else if (GET_CODE (SET_DEST (x)) == SUBREG
6545 /* We need SUBREGs to compute nonzero_bits properly. */
6546 && nonzero_sign_valid
6547 && (((GET_MODE_SIZE (GET_MODE (SET_DEST (x)))
6548 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
6549 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x))))
6550 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)))
6552 x = gen_rtx_SET (VOIDmode, SUBREG_REG (SET_DEST (x)),
6554 (GET_MODE (SUBREG_REG (SET_DEST (x))),
6561 while (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
6562 inner = SUBREG_REG (inner);
6564 compute_mode = GET_MODE (inner);
6566 /* Don't attempt bitwise arithmetic on non scalar integer modes. */
6567 if (! SCALAR_INT_MODE_P (compute_mode))
6569 enum machine_mode imode;
6571 /* Don't do anything for vector or complex integral types. */
6572 if (! FLOAT_MODE_P (compute_mode))
6575 /* Try to find an integral mode to pun with. */
6576 imode = mode_for_size (GET_MODE_BITSIZE (compute_mode), MODE_INT, 0);
6577 if (imode == BLKmode)
6580 compute_mode = imode;
6581 inner = gen_lowpart (imode, inner);
6584 /* Compute a mask of LEN bits, if we can do this on the host machine. */
6585 if (len >= HOST_BITS_PER_WIDE_INT)
6588 /* Now compute the equivalent expression. Make a copy of INNER
6589 for the SET_DEST in case it is a MEM into which we will substitute;
6590 we don't want shared RTL in that case. */
6591 mask = GEN_INT (((HOST_WIDE_INT) 1 << len) - 1);
6592 cleared = simplify_gen_binary (AND, compute_mode,
6593 simplify_gen_unary (NOT, compute_mode,
6594 simplify_gen_binary (ASHIFT,
6599 masked = simplify_gen_binary (ASHIFT, compute_mode,
6600 simplify_gen_binary (
6602 gen_lowpart (compute_mode, SET_SRC (x)),
6606 x = gen_rtx_SET (VOIDmode, copy_rtx (inner),
6607 simplify_gen_binary (IOR, compute_mode,
6614 /* Return an RTX for a reference to LEN bits of INNER. If POS_RTX is nonzero,
6615 it is an RTX that represents a variable starting position; otherwise,
6616 POS is the (constant) starting bit position (counted from the LSB).
6618 UNSIGNEDP is nonzero for an unsigned reference and zero for a
6621 IN_DEST is nonzero if this is a reference in the destination of a
6622 SET. This is used when a ZERO_ or SIGN_EXTRACT isn't needed. If nonzero,
6623 a STRICT_LOW_PART will be used, if zero, ZERO_EXTEND or SIGN_EXTEND will
6626 IN_COMPARE is nonzero if we are in a COMPARE. This means that a
6627 ZERO_EXTRACT should be built even for bits starting at bit 0.
6629 MODE is the desired mode of the result (if IN_DEST == 0).
6631 The result is an RTX for the extraction or NULL_RTX if the target
6635 make_extraction (enum machine_mode mode, rtx inner, HOST_WIDE_INT pos,
6636 rtx pos_rtx, unsigned HOST_WIDE_INT len, int unsignedp,
6637 int in_dest, int in_compare)
6639 /* This mode describes the size of the storage area
6640 to fetch the overall value from. Within that, we
6641 ignore the POS lowest bits, etc. */
6642 enum machine_mode is_mode = GET_MODE (inner);
6643 enum machine_mode inner_mode;
6644 enum machine_mode wanted_inner_mode;
6645 enum machine_mode wanted_inner_reg_mode = word_mode;
6646 enum machine_mode pos_mode = word_mode;
6647 enum machine_mode extraction_mode = word_mode;
6648 enum machine_mode tmode = mode_for_size (len, MODE_INT, 1);
6650 rtx orig_pos_rtx = pos_rtx;
6651 HOST_WIDE_INT orig_pos;
6653 if (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
6655 /* If going from (subreg:SI (mem:QI ...)) to (mem:QI ...),
6656 consider just the QI as the memory to extract from.
6657 The subreg adds or removes high bits; its mode is
6658 irrelevant to the meaning of this extraction,
6659 since POS and LEN count from the lsb. */
6660 if (MEM_P (SUBREG_REG (inner)))
6661 is_mode = GET_MODE (SUBREG_REG (inner));
6662 inner = SUBREG_REG (inner);
6664 else if (GET_CODE (inner) == ASHIFT
6665 && CONST_INT_P (XEXP (inner, 1))
6666 && pos_rtx == 0 && pos == 0
6667 && len > (unsigned HOST_WIDE_INT) INTVAL (XEXP (inner, 1)))
6669 /* We're extracting the least significant bits of an rtx
6670 (ashift X (const_int C)), where LEN > C. Extract the
6671 least significant (LEN - C) bits of X, giving an rtx
6672 whose mode is MODE, then shift it left C times. */
6673 new_rtx = make_extraction (mode, XEXP (inner, 0),
6674 0, 0, len - INTVAL (XEXP (inner, 1)),
6675 unsignedp, in_dest, in_compare);
6677 return gen_rtx_ASHIFT (mode, new_rtx, XEXP (inner, 1));
6680 inner_mode = GET_MODE (inner);
6682 if (pos_rtx && CONST_INT_P (pos_rtx))
6683 pos = INTVAL (pos_rtx), pos_rtx = 0;
6685 /* See if this can be done without an extraction. We never can if the
6686 width of the field is not the same as that of some integer mode. For
6687 registers, we can only avoid the extraction if the position is at the
6688 low-order bit and this is either not in the destination or we have the
6689 appropriate STRICT_LOW_PART operation available.
6691 For MEM, we can avoid an extract if the field starts on an appropriate
6692 boundary and we can change the mode of the memory reference. */
6694 if (tmode != BLKmode
6695 && ((pos_rtx == 0 && (pos % BITS_PER_WORD) == 0
6697 && (inner_mode == tmode
6699 || TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (tmode),
6700 GET_MODE_BITSIZE (inner_mode))
6701 || reg_truncated_to_mode (tmode, inner))
6704 && have_insn_for (STRICT_LOW_PART, tmode))))
6705 || (MEM_P (inner) && pos_rtx == 0
6707 % (STRICT_ALIGNMENT ? GET_MODE_ALIGNMENT (tmode)
6708 : BITS_PER_UNIT)) == 0
6709 /* We can't do this if we are widening INNER_MODE (it
6710 may not be aligned, for one thing). */
6711 && GET_MODE_BITSIZE (inner_mode) >= GET_MODE_BITSIZE (tmode)
6712 && (inner_mode == tmode
6713 || (! mode_dependent_address_p (XEXP (inner, 0))
6714 && ! MEM_VOLATILE_P (inner))))))
6716 /* If INNER is a MEM, make a new MEM that encompasses just the desired
6717 field. If the original and current mode are the same, we need not
6718 adjust the offset. Otherwise, we do if bytes big endian.
6720 If INNER is not a MEM, get a piece consisting of just the field
6721 of interest (in this case POS % BITS_PER_WORD must be 0). */
6725 HOST_WIDE_INT offset;
6727 /* POS counts from lsb, but make OFFSET count in memory order. */
6728 if (BYTES_BIG_ENDIAN)
6729 offset = (GET_MODE_BITSIZE (is_mode) - len - pos) / BITS_PER_UNIT;
6731 offset = pos / BITS_PER_UNIT;
6733 new_rtx = adjust_address_nv (inner, tmode, offset);
6735 else if (REG_P (inner))
6737 if (tmode != inner_mode)
6739 /* We can't call gen_lowpart in a DEST since we
6740 always want a SUBREG (see below) and it would sometimes
6741 return a new hard register. */
6744 HOST_WIDE_INT final_word = pos / BITS_PER_WORD;
6746 if (WORDS_BIG_ENDIAN
6747 && GET_MODE_SIZE (inner_mode) > UNITS_PER_WORD)
6748 final_word = ((GET_MODE_SIZE (inner_mode)
6749 - GET_MODE_SIZE (tmode))
6750 / UNITS_PER_WORD) - final_word;
6752 final_word *= UNITS_PER_WORD;
6753 if (BYTES_BIG_ENDIAN &&
6754 GET_MODE_SIZE (inner_mode) > GET_MODE_SIZE (tmode))
6755 final_word += (GET_MODE_SIZE (inner_mode)
6756 - GET_MODE_SIZE (tmode)) % UNITS_PER_WORD;
6758 /* Avoid creating invalid subregs, for example when
6759 simplifying (x>>32)&255. */
6760 if (!validate_subreg (tmode, inner_mode, inner, final_word))
6763 new_rtx = gen_rtx_SUBREG (tmode, inner, final_word);
6766 new_rtx = gen_lowpart (tmode, inner);
6772 new_rtx = force_to_mode (inner, tmode,
6773 len >= HOST_BITS_PER_WIDE_INT
6774 ? ~(unsigned HOST_WIDE_INT) 0
6775 : ((unsigned HOST_WIDE_INT) 1 << len) - 1,
6778 /* If this extraction is going into the destination of a SET,
6779 make a STRICT_LOW_PART unless we made a MEM. */
6782 return (MEM_P (new_rtx) ? new_rtx
6783 : (GET_CODE (new_rtx) != SUBREG
6784 ? gen_rtx_CLOBBER (tmode, const0_rtx)
6785 : gen_rtx_STRICT_LOW_PART (VOIDmode, new_rtx)));
6790 if (CONST_INT_P (new_rtx))
6791 return gen_int_mode (INTVAL (new_rtx), mode);
6793 /* If we know that no extraneous bits are set, and that the high
6794 bit is not set, convert the extraction to the cheaper of
6795 sign and zero extension, that are equivalent in these cases. */
6796 if (flag_expensive_optimizations
6797 && (GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT
6798 && ((nonzero_bits (new_rtx, tmode)
6799 & ~(((unsigned HOST_WIDE_INT)
6800 GET_MODE_MASK (tmode))
6804 rtx temp = gen_rtx_ZERO_EXTEND (mode, new_rtx);
6805 rtx temp1 = gen_rtx_SIGN_EXTEND (mode, new_rtx);
6807 /* Prefer ZERO_EXTENSION, since it gives more information to
6809 if (rtx_cost (temp, SET, optimize_this_for_speed_p)
6810 <= rtx_cost (temp1, SET, optimize_this_for_speed_p))
6815 /* Otherwise, sign- or zero-extend unless we already are in the
6818 return (gen_rtx_fmt_e (unsignedp ? ZERO_EXTEND : SIGN_EXTEND,
6822 /* Unless this is a COMPARE or we have a funny memory reference,
6823 don't do anything with zero-extending field extracts starting at
6824 the low-order bit since they are simple AND operations. */
6825 if (pos_rtx == 0 && pos == 0 && ! in_dest
6826 && ! in_compare && unsignedp)
6829 /* Unless INNER is not MEM, reject this if we would be spanning bytes or
6830 if the position is not a constant and the length is not 1. In all
6831 other cases, we would only be going outside our object in cases when
6832 an original shift would have been undefined. */
6834 && ((pos_rtx == 0 && pos + len > GET_MODE_BITSIZE (is_mode))
6835 || (pos_rtx != 0 && len != 1)))
6838 /* Get the mode to use should INNER not be a MEM, the mode for the position,
6839 and the mode for the result. */
6840 if (in_dest && mode_for_extraction (EP_insv, -1) != MAX_MACHINE_MODE)
6842 wanted_inner_reg_mode = mode_for_extraction (EP_insv, 0);
6843 pos_mode = mode_for_extraction (EP_insv, 2);
6844 extraction_mode = mode_for_extraction (EP_insv, 3);
6847 if (! in_dest && unsignedp
6848 && mode_for_extraction (EP_extzv, -1) != MAX_MACHINE_MODE)
6850 wanted_inner_reg_mode = mode_for_extraction (EP_extzv, 1);
6851 pos_mode = mode_for_extraction (EP_extzv, 3);
6852 extraction_mode = mode_for_extraction (EP_extzv, 0);
6855 if (! in_dest && ! unsignedp
6856 && mode_for_extraction (EP_extv, -1) != MAX_MACHINE_MODE)
6858 wanted_inner_reg_mode = mode_for_extraction (EP_extv, 1);
6859 pos_mode = mode_for_extraction (EP_extv, 3);
6860 extraction_mode = mode_for_extraction (EP_extv, 0);
6863 /* Never narrow an object, since that might not be safe. */
6865 if (mode != VOIDmode
6866 && GET_MODE_SIZE (extraction_mode) < GET_MODE_SIZE (mode))
6867 extraction_mode = mode;
6869 if (pos_rtx && GET_MODE (pos_rtx) != VOIDmode
6870 && GET_MODE_SIZE (pos_mode) < GET_MODE_SIZE (GET_MODE (pos_rtx)))
6871 pos_mode = GET_MODE (pos_rtx);
6873 /* If this is not from memory, the desired mode is the preferred mode
6874 for an extraction pattern's first input operand, or word_mode if there
6877 wanted_inner_mode = wanted_inner_reg_mode;
6880 /* Be careful not to go beyond the extracted object and maintain the
6881 natural alignment of the memory. */
6882 wanted_inner_mode = smallest_mode_for_size (len, MODE_INT);
6883 while (pos % GET_MODE_BITSIZE (wanted_inner_mode) + len
6884 > GET_MODE_BITSIZE (wanted_inner_mode))
6886 wanted_inner_mode = GET_MODE_WIDER_MODE (wanted_inner_mode);
6887 gcc_assert (wanted_inner_mode != VOIDmode);
6890 /* If we have to change the mode of memory and cannot, the desired mode
6891 is EXTRACTION_MODE. */
6892 if (inner_mode != wanted_inner_mode
6893 && (mode_dependent_address_p (XEXP (inner, 0))
6894 || MEM_VOLATILE_P (inner)
6896 wanted_inner_mode = extraction_mode;
6901 if (BITS_BIG_ENDIAN)
6903 /* POS is passed as if BITS_BIG_ENDIAN == 0, so we need to convert it to
6904 BITS_BIG_ENDIAN style. If position is constant, compute new
6905 position. Otherwise, build subtraction.
6906 Note that POS is relative to the mode of the original argument.
6907 If it's a MEM we need to recompute POS relative to that.
6908 However, if we're extracting from (or inserting into) a register,
6909 we want to recompute POS relative to wanted_inner_mode. */
6910 int width = (MEM_P (inner)
6911 ? GET_MODE_BITSIZE (is_mode)
6912 : GET_MODE_BITSIZE (wanted_inner_mode));
6915 pos = width - len - pos;
6918 = gen_rtx_MINUS (GET_MODE (pos_rtx), GEN_INT (width - len), pos_rtx);
6919 /* POS may be less than 0 now, but we check for that below.
6920 Note that it can only be less than 0 if !MEM_P (inner). */
6923 /* If INNER has a wider mode, and this is a constant extraction, try to
6924 make it smaller and adjust the byte to point to the byte containing
6926 if (wanted_inner_mode != VOIDmode
6927 && inner_mode != wanted_inner_mode
6929 && GET_MODE_SIZE (wanted_inner_mode) < GET_MODE_SIZE (is_mode)
6931 && ! mode_dependent_address_p (XEXP (inner, 0))
6932 && ! MEM_VOLATILE_P (inner))
6936 /* The computations below will be correct if the machine is big
6937 endian in both bits and bytes or little endian in bits and bytes.
6938 If it is mixed, we must adjust. */
6940 /* If bytes are big endian and we had a paradoxical SUBREG, we must
6941 adjust OFFSET to compensate. */
6942 if (BYTES_BIG_ENDIAN
6943 && GET_MODE_SIZE (inner_mode) < GET_MODE_SIZE (is_mode))
6944 offset -= GET_MODE_SIZE (is_mode) - GET_MODE_SIZE (inner_mode);
6946 /* We can now move to the desired byte. */
6947 offset += (pos / GET_MODE_BITSIZE (wanted_inner_mode))
6948 * GET_MODE_SIZE (wanted_inner_mode);
6949 pos %= GET_MODE_BITSIZE (wanted_inner_mode);
6951 if (BYTES_BIG_ENDIAN != BITS_BIG_ENDIAN
6952 && is_mode != wanted_inner_mode)
6953 offset = (GET_MODE_SIZE (is_mode)
6954 - GET_MODE_SIZE (wanted_inner_mode) - offset);
6956 inner = adjust_address_nv (inner, wanted_inner_mode, offset);
6959 /* If INNER is not memory, get it into the proper mode. If we are changing
6960 its mode, POS must be a constant and smaller than the size of the new
6962 else if (!MEM_P (inner))
6964 /* On the LHS, don't create paradoxical subregs implicitely truncating
6965 the register unless TRULY_NOOP_TRUNCATION. */
6967 && !TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (GET_MODE (inner)),
6968 GET_MODE_BITSIZE (wanted_inner_mode)))
6971 if (GET_MODE (inner) != wanted_inner_mode
6973 || orig_pos + len > GET_MODE_BITSIZE (wanted_inner_mode)))
6979 inner = force_to_mode (inner, wanted_inner_mode,
6981 || len + orig_pos >= HOST_BITS_PER_WIDE_INT
6982 ? ~(unsigned HOST_WIDE_INT) 0
6983 : ((((unsigned HOST_WIDE_INT) 1 << len) - 1)
6988 /* Adjust mode of POS_RTX, if needed. If we want a wider mode, we
6989 have to zero extend. Otherwise, we can just use a SUBREG. */
6991 && GET_MODE_SIZE (pos_mode) > GET_MODE_SIZE (GET_MODE (pos_rtx)))
6993 rtx temp = gen_rtx_ZERO_EXTEND (pos_mode, pos_rtx);
6995 /* If we know that no extraneous bits are set, and that the high
6996 bit is not set, convert extraction to cheaper one - either
6997 SIGN_EXTENSION or ZERO_EXTENSION, that are equivalent in these
6999 if (flag_expensive_optimizations
7000 && (GET_MODE_BITSIZE (GET_MODE (pos_rtx)) <= HOST_BITS_PER_WIDE_INT
7001 && ((nonzero_bits (pos_rtx, GET_MODE (pos_rtx))
7002 & ~(((unsigned HOST_WIDE_INT)
7003 GET_MODE_MASK (GET_MODE (pos_rtx)))
7007 rtx temp1 = gen_rtx_SIGN_EXTEND (pos_mode, pos_rtx);
7009 /* Prefer ZERO_EXTENSION, since it gives more information to
7011 if (rtx_cost (temp1, SET, optimize_this_for_speed_p)
7012 < rtx_cost (temp, SET, optimize_this_for_speed_p))
7017 else if (pos_rtx != 0
7018 && GET_MODE_SIZE (pos_mode) < GET_MODE_SIZE (GET_MODE (pos_rtx)))
7019 pos_rtx = gen_lowpart (pos_mode, pos_rtx);
7021 /* Make POS_RTX unless we already have it and it is correct. If we don't
7022 have a POS_RTX but we do have an ORIG_POS_RTX, the latter must
7024 if (pos_rtx == 0 && orig_pos_rtx != 0 && INTVAL (orig_pos_rtx) == pos)
7025 pos_rtx = orig_pos_rtx;
7027 else if (pos_rtx == 0)
7028 pos_rtx = GEN_INT (pos);
7030 /* Make the required operation. See if we can use existing rtx. */
7031 new_rtx = gen_rtx_fmt_eee (unsignedp ? ZERO_EXTRACT : SIGN_EXTRACT,
7032 extraction_mode, inner, GEN_INT (len), pos_rtx);
7034 new_rtx = gen_lowpart (mode, new_rtx);
7039 /* See if X contains an ASHIFT of COUNT or more bits that can be commuted
7040 with any other operations in X. Return X without that shift if so. */
7043 extract_left_shift (rtx x, int count)
7045 enum rtx_code code = GET_CODE (x);
7046 enum machine_mode mode = GET_MODE (x);
7052 /* This is the shift itself. If it is wide enough, we will return
7053 either the value being shifted if the shift count is equal to
7054 COUNT or a shift for the difference. */
7055 if (CONST_INT_P (XEXP (x, 1))
7056 && INTVAL (XEXP (x, 1)) >= count)
7057 return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (x, 0),
7058 INTVAL (XEXP (x, 1)) - count);
7062 if ((tem = extract_left_shift (XEXP (x, 0), count)) != 0)
7063 return simplify_gen_unary (code, mode, tem, mode);
7067 case PLUS: case IOR: case XOR: case AND:
7068 /* If we can safely shift this constant and we find the inner shift,
7069 make a new operation. */
7070 if (CONST_INT_P (XEXP (x, 1))
7071 && (INTVAL (XEXP (x, 1)) & ((((HOST_WIDE_INT) 1 << count)) - 1)) == 0
7072 && (tem = extract_left_shift (XEXP (x, 0), count)) != 0)
7073 return simplify_gen_binary (code, mode, tem,
7074 GEN_INT (INTVAL (XEXP (x, 1)) >> count));
7085 /* Look at the expression rooted at X. Look for expressions
7086 equivalent to ZERO_EXTRACT, SIGN_EXTRACT, ZERO_EXTEND, SIGN_EXTEND.
7087 Form these expressions.
7089 Return the new rtx, usually just X.
7091 Also, for machines like the VAX that don't have logical shift insns,
7092 try to convert logical to arithmetic shift operations in cases where
7093 they are equivalent. This undoes the canonicalizations to logical
7094 shifts done elsewhere.
7096 We try, as much as possible, to re-use rtl expressions to save memory.
7098 IN_CODE says what kind of expression we are processing. Normally, it is
7099 SET. In a memory address (inside a MEM, PLUS or minus, the latter two
7100 being kludges), it is MEM. When processing the arguments of a comparison
7101 or a COMPARE against zero, it is COMPARE. */
7104 make_compound_operation (rtx x, enum rtx_code in_code)
7106 enum rtx_code code = GET_CODE (x);
7107 enum machine_mode mode = GET_MODE (x);
7108 int mode_width = GET_MODE_BITSIZE (mode);
7110 enum rtx_code next_code;
7116 /* Select the code to be used in recursive calls. Once we are inside an
7117 address, we stay there. If we have a comparison, set to COMPARE,
7118 but once inside, go back to our default of SET. */
7120 next_code = (code == MEM || code == PLUS || code == MINUS ? MEM
7121 : ((code == COMPARE || COMPARISON_P (x))
7122 && XEXP (x, 1) == const0_rtx) ? COMPARE
7123 : in_code == COMPARE ? SET : in_code);
7125 /* Process depending on the code of this operation. If NEW is set
7126 nonzero, it will be returned. */
7131 /* Convert shifts by constants into multiplications if inside
7133 if (in_code == MEM && CONST_INT_P (XEXP (x, 1))
7134 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT
7135 && INTVAL (XEXP (x, 1)) >= 0)
7137 new_rtx = make_compound_operation (XEXP (x, 0), next_code);
7138 new_rtx = gen_rtx_MULT (mode, new_rtx,
7139 GEN_INT ((HOST_WIDE_INT) 1
7140 << INTVAL (XEXP (x, 1))));
7145 /* If the second operand is not a constant, we can't do anything
7147 if (!CONST_INT_P (XEXP (x, 1)))
7150 /* If the constant is a power of two minus one and the first operand
7151 is a logical right shift, make an extraction. */
7152 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
7153 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
7155 new_rtx = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code);
7156 new_rtx = make_extraction (mode, new_rtx, 0, XEXP (XEXP (x, 0), 1), i, 1,
7157 0, in_code == COMPARE);
7160 /* Same as previous, but for (subreg (lshiftrt ...)) in first op. */
7161 else if (GET_CODE (XEXP (x, 0)) == SUBREG
7162 && subreg_lowpart_p (XEXP (x, 0))
7163 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == LSHIFTRT
7164 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
7166 new_rtx = make_compound_operation (XEXP (SUBREG_REG (XEXP (x, 0)), 0),
7168 new_rtx = make_extraction (GET_MODE (SUBREG_REG (XEXP (x, 0))), new_rtx, 0,
7169 XEXP (SUBREG_REG (XEXP (x, 0)), 1), i, 1,
7170 0, in_code == COMPARE);
7172 /* Same as previous, but for (xor/ior (lshiftrt...) (lshiftrt...)). */
7173 else if ((GET_CODE (XEXP (x, 0)) == XOR
7174 || GET_CODE (XEXP (x, 0)) == IOR)
7175 && GET_CODE (XEXP (XEXP (x, 0), 0)) == LSHIFTRT
7176 && GET_CODE (XEXP (XEXP (x, 0), 1)) == LSHIFTRT
7177 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
7179 /* Apply the distributive law, and then try to make extractions. */
7180 new_rtx = gen_rtx_fmt_ee (GET_CODE (XEXP (x, 0)), mode,
7181 gen_rtx_AND (mode, XEXP (XEXP (x, 0), 0),
7183 gen_rtx_AND (mode, XEXP (XEXP (x, 0), 1),
7185 new_rtx = make_compound_operation (new_rtx, in_code);
7188 /* If we are have (and (rotate X C) M) and C is larger than the number
7189 of bits in M, this is an extraction. */
7191 else if (GET_CODE (XEXP (x, 0)) == ROTATE
7192 && CONST_INT_P (XEXP (XEXP (x, 0), 1))
7193 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0
7194 && i <= INTVAL (XEXP (XEXP (x, 0), 1)))
7196 new_rtx = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code);
7197 new_rtx = make_extraction (mode, new_rtx,
7198 (GET_MODE_BITSIZE (mode)
7199 - INTVAL (XEXP (XEXP (x, 0), 1))),
7200 NULL_RTX, i, 1, 0, in_code == COMPARE);
7203 /* On machines without logical shifts, if the operand of the AND is
7204 a logical shift and our mask turns off all the propagated sign
7205 bits, we can replace the logical shift with an arithmetic shift. */
7206 else if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
7207 && !have_insn_for (LSHIFTRT, mode)
7208 && have_insn_for (ASHIFTRT, mode)
7209 && CONST_INT_P (XEXP (XEXP (x, 0), 1))
7210 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
7211 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT
7212 && mode_width <= HOST_BITS_PER_WIDE_INT)
7214 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
7216 mask >>= INTVAL (XEXP (XEXP (x, 0), 1));
7217 if ((INTVAL (XEXP (x, 1)) & ~mask) == 0)
7219 gen_rtx_ASHIFTRT (mode,
7220 make_compound_operation
7221 (XEXP (XEXP (x, 0), 0), next_code),
7222 XEXP (XEXP (x, 0), 1)));
7225 /* If the constant is one less than a power of two, this might be
7226 representable by an extraction even if no shift is present.
7227 If it doesn't end up being a ZERO_EXTEND, we will ignore it unless
7228 we are in a COMPARE. */
7229 else if ((i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
7230 new_rtx = make_extraction (mode,
7231 make_compound_operation (XEXP (x, 0),
7233 0, NULL_RTX, i, 1, 0, in_code == COMPARE);
7235 /* If we are in a comparison and this is an AND with a power of two,
7236 convert this into the appropriate bit extract. */
7237 else if (in_code == COMPARE
7238 && (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0)
7239 new_rtx = make_extraction (mode,
7240 make_compound_operation (XEXP (x, 0),
7242 i, NULL_RTX, 1, 1, 0, 1);
7247 /* If the sign bit is known to be zero, replace this with an
7248 arithmetic shift. */
7249 if (have_insn_for (ASHIFTRT, mode)
7250 && ! have_insn_for (LSHIFTRT, mode)
7251 && mode_width <= HOST_BITS_PER_WIDE_INT
7252 && (nonzero_bits (XEXP (x, 0), mode) & (1 << (mode_width - 1))) == 0)
7254 new_rtx = gen_rtx_ASHIFTRT (mode,
7255 make_compound_operation (XEXP (x, 0),
7261 /* ... fall through ... */
7267 /* If we have (ashiftrt (ashift foo C1) C2) with C2 >= C1,
7268 this is a SIGN_EXTRACT. */
7269 if (CONST_INT_P (rhs)
7270 && GET_CODE (lhs) == ASHIFT
7271 && CONST_INT_P (XEXP (lhs, 1))
7272 && INTVAL (rhs) >= INTVAL (XEXP (lhs, 1))
7273 && INTVAL (rhs) < mode_width)
7275 new_rtx = make_compound_operation (XEXP (lhs, 0), next_code);
7276 new_rtx = make_extraction (mode, new_rtx,
7277 INTVAL (rhs) - INTVAL (XEXP (lhs, 1)),
7278 NULL_RTX, mode_width - INTVAL (rhs),
7279 code == LSHIFTRT, 0, in_code == COMPARE);
7283 /* See if we have operations between an ASHIFTRT and an ASHIFT.
7284 If so, try to merge the shifts into a SIGN_EXTEND. We could
7285 also do this for some cases of SIGN_EXTRACT, but it doesn't
7286 seem worth the effort; the case checked for occurs on Alpha. */
7289 && ! (GET_CODE (lhs) == SUBREG
7290 && (OBJECT_P (SUBREG_REG (lhs))))
7291 && CONST_INT_P (rhs)
7292 && INTVAL (rhs) < HOST_BITS_PER_WIDE_INT
7293 && INTVAL (rhs) < mode_width
7294 && (new_rtx = extract_left_shift (lhs, INTVAL (rhs))) != 0)
7295 new_rtx = make_extraction (mode, make_compound_operation (new_rtx, next_code),
7296 0, NULL_RTX, mode_width - INTVAL (rhs),
7297 code == LSHIFTRT, 0, in_code == COMPARE);
7302 /* Call ourselves recursively on the inner expression. If we are
7303 narrowing the object and it has a different RTL code from
7304 what it originally did, do this SUBREG as a force_to_mode. */
7306 tem = make_compound_operation (SUBREG_REG (x), in_code);
7309 rtx simplified = simplify_subreg (mode, tem, GET_MODE (SUBREG_REG (x)),
7315 if (GET_CODE (tem) != GET_CODE (SUBREG_REG (x))
7316 && GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x)))
7317 && subreg_lowpart_p (x))
7319 rtx newer = force_to_mode (tem, mode, ~(HOST_WIDE_INT) 0,
7322 /* If we have something other than a SUBREG, we might have
7323 done an expansion, so rerun ourselves. */
7324 if (GET_CODE (newer) != SUBREG)
7325 newer = make_compound_operation (newer, in_code);
7327 /* force_to_mode can expand compounds. If it just re-expanded the
7328 compound use gen_lowpart instead to convert to the desired
7330 if (rtx_equal_p (newer, x))
7331 return gen_lowpart (GET_MODE (x), tem);
7347 x = gen_lowpart (mode, new_rtx);
7348 code = GET_CODE (x);
7351 /* Now recursively process each operand of this operation. */
7352 fmt = GET_RTX_FORMAT (code);
7353 for (i = 0; i < GET_RTX_LENGTH (code); i++)
7356 new_rtx = make_compound_operation (XEXP (x, i), next_code);
7357 SUBST (XEXP (x, i), new_rtx);
7359 else if (fmt[i] == 'E')
7360 for (j = 0; j < XVECLEN (x, i); j++)
7362 new_rtx = make_compound_operation (XVECEXP (x, i, j), next_code);
7363 SUBST (XVECEXP (x, i, j), new_rtx);
7366 /* If this is a commutative operation, the changes to the operands
7367 may have made it noncanonical. */
7368 if (COMMUTATIVE_ARITH_P (x)
7369 && swap_commutative_operands_p (XEXP (x, 0), XEXP (x, 1)))
7372 SUBST (XEXP (x, 0), XEXP (x, 1));
7373 SUBST (XEXP (x, 1), tem);
7379 /* Given M see if it is a value that would select a field of bits
7380 within an item, but not the entire word. Return -1 if not.
7381 Otherwise, return the starting position of the field, where 0 is the
7384 *PLEN is set to the length of the field. */
7387 get_pos_from_mask (unsigned HOST_WIDE_INT m, unsigned HOST_WIDE_INT *plen)
7389 /* Get the bit number of the first 1 bit from the right, -1 if none. */
7390 int pos = exact_log2 (m & -m);
7394 /* Now shift off the low-order zero bits and see if we have a
7395 power of two minus 1. */
7396 len = exact_log2 ((m >> pos) + 1);
7405 /* If X refers to a register that equals REG in value, replace these
7406 references with REG. */
7408 canon_reg_for_combine (rtx x, rtx reg)
7415 enum rtx_code code = GET_CODE (x);
7416 switch (GET_RTX_CLASS (code))
7419 op0 = canon_reg_for_combine (XEXP (x, 0), reg);
7420 if (op0 != XEXP (x, 0))
7421 return simplify_gen_unary (GET_CODE (x), GET_MODE (x), op0,
7426 case RTX_COMM_ARITH:
7427 op0 = canon_reg_for_combine (XEXP (x, 0), reg);
7428 op1 = canon_reg_for_combine (XEXP (x, 1), reg);
7429 if (op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
7430 return simplify_gen_binary (GET_CODE (x), GET_MODE (x), op0, op1);
7434 case RTX_COMM_COMPARE:
7435 op0 = canon_reg_for_combine (XEXP (x, 0), reg);
7436 op1 = canon_reg_for_combine (XEXP (x, 1), reg);
7437 if (op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
7438 return simplify_gen_relational (GET_CODE (x), GET_MODE (x),
7439 GET_MODE (op0), op0, op1);
7443 case RTX_BITFIELD_OPS:
7444 op0 = canon_reg_for_combine (XEXP (x, 0), reg);
7445 op1 = canon_reg_for_combine (XEXP (x, 1), reg);
7446 op2 = canon_reg_for_combine (XEXP (x, 2), reg);
7447 if (op0 != XEXP (x, 0) || op1 != XEXP (x, 1) || op2 != XEXP (x, 2))
7448 return simplify_gen_ternary (GET_CODE (x), GET_MODE (x),
7449 GET_MODE (op0), op0, op1, op2);
7454 if (rtx_equal_p (get_last_value (reg), x)
7455 || rtx_equal_p (reg, get_last_value (x)))
7464 fmt = GET_RTX_FORMAT (code);
7466 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
7469 rtx op = canon_reg_for_combine (XEXP (x, i), reg);
7470 if (op != XEXP (x, i))
7480 else if (fmt[i] == 'E')
7483 for (j = 0; j < XVECLEN (x, i); j++)
7485 rtx op = canon_reg_for_combine (XVECEXP (x, i, j), reg);
7486 if (op != XVECEXP (x, i, j))
7493 XVECEXP (x, i, j) = op;
7504 /* Return X converted to MODE. If the value is already truncated to
7505 MODE we can just return a subreg even though in the general case we
7506 would need an explicit truncation. */
7509 gen_lowpart_or_truncate (enum machine_mode mode, rtx x)
7511 if (!CONST_INT_P (x)
7512 && GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (x))
7513 && !TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode),
7514 GET_MODE_BITSIZE (GET_MODE (x)))
7515 && !(REG_P (x) && reg_truncated_to_mode (mode, x)))
7517 /* Bit-cast X into an integer mode. */
7518 if (!SCALAR_INT_MODE_P (GET_MODE (x)))
7519 x = gen_lowpart (int_mode_for_mode (GET_MODE (x)), x);
7520 x = simplify_gen_unary (TRUNCATE, int_mode_for_mode (mode),
7524 return gen_lowpart (mode, x);
7527 /* See if X can be simplified knowing that we will only refer to it in
7528 MODE and will only refer to those bits that are nonzero in MASK.
7529 If other bits are being computed or if masking operations are done
7530 that select a superset of the bits in MASK, they can sometimes be
7533 Return a possibly simplified expression, but always convert X to
7534 MODE. If X is a CONST_INT, AND the CONST_INT with MASK.
7536 If JUST_SELECT is nonzero, don't optimize by noticing that bits in MASK
7537 are all off in X. This is used when X will be complemented, by either
7538 NOT, NEG, or XOR. */
7541 force_to_mode (rtx x, enum machine_mode mode, unsigned HOST_WIDE_INT mask,
7544 enum rtx_code code = GET_CODE (x);
7545 int next_select = just_select || code == XOR || code == NOT || code == NEG;
7546 enum machine_mode op_mode;
7547 unsigned HOST_WIDE_INT fuller_mask, nonzero;
7550 /* If this is a CALL or ASM_OPERANDS, don't do anything. Some of the
7551 code below will do the wrong thing since the mode of such an
7552 expression is VOIDmode.
7554 Also do nothing if X is a CLOBBER; this can happen if X was
7555 the return value from a call to gen_lowpart. */
7556 if (code == CALL || code == ASM_OPERANDS || code == CLOBBER)
7559 /* We want to perform the operation is its present mode unless we know
7560 that the operation is valid in MODE, in which case we do the operation
7562 op_mode = ((GET_MODE_CLASS (mode) == GET_MODE_CLASS (GET_MODE (x))
7563 && have_insn_for (code, mode))
7564 ? mode : GET_MODE (x));
7566 /* It is not valid to do a right-shift in a narrower mode
7567 than the one it came in with. */
7568 if ((code == LSHIFTRT || code == ASHIFTRT)
7569 && GET_MODE_BITSIZE (mode) < GET_MODE_BITSIZE (GET_MODE (x)))
7570 op_mode = GET_MODE (x);
7572 /* Truncate MASK to fit OP_MODE. */
7574 mask &= GET_MODE_MASK (op_mode);
7576 /* When we have an arithmetic operation, or a shift whose count we
7577 do not know, we need to assume that all bits up to the highest-order
7578 bit in MASK will be needed. This is how we form such a mask. */
7579 if (mask & ((unsigned HOST_WIDE_INT) 1 << (HOST_BITS_PER_WIDE_INT - 1)))
7580 fuller_mask = ~(unsigned HOST_WIDE_INT) 0;
7582 fuller_mask = (((unsigned HOST_WIDE_INT) 1 << (floor_log2 (mask) + 1))
7585 /* Determine what bits of X are guaranteed to be (non)zero. */
7586 nonzero = nonzero_bits (x, mode);
7588 /* If none of the bits in X are needed, return a zero. */
7589 if (!just_select && (nonzero & mask) == 0 && !side_effects_p (x))
7592 /* If X is a CONST_INT, return a new one. Do this here since the
7593 test below will fail. */
7594 if (CONST_INT_P (x))
7596 if (SCALAR_INT_MODE_P (mode))
7597 return gen_int_mode (INTVAL (x) & mask, mode);
7600 x = GEN_INT (INTVAL (x) & mask);
7601 return gen_lowpart_common (mode, x);
7605 /* If X is narrower than MODE and we want all the bits in X's mode, just
7606 get X in the proper mode. */
7607 if (GET_MODE_SIZE (GET_MODE (x)) < GET_MODE_SIZE (mode)
7608 && (GET_MODE_MASK (GET_MODE (x)) & ~mask) == 0)
7609 return gen_lowpart (mode, x);
7611 /* We can ignore the effect of a SUBREG if it narrows the mode or
7612 if the constant masks to zero all the bits the mode doesn't have. */
7613 if (GET_CODE (x) == SUBREG
7614 && subreg_lowpart_p (x)
7615 && ((GET_MODE_SIZE (GET_MODE (x))
7616 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
7618 & GET_MODE_MASK (GET_MODE (x))
7619 & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (x)))))))
7620 return force_to_mode (SUBREG_REG (x), mode, mask, next_select);
7622 /* The arithmetic simplifications here only work for scalar integer modes. */
7623 if (!SCALAR_INT_MODE_P (mode) || !SCALAR_INT_MODE_P (GET_MODE (x)))
7624 return gen_lowpart_or_truncate (mode, x);
7629 /* If X is a (clobber (const_int)), return it since we know we are
7630 generating something that won't match. */
7637 x = expand_compound_operation (x);
7638 if (GET_CODE (x) != code)
7639 return force_to_mode (x, mode, mask, next_select);
7643 /* Similarly for a truncate. */
7644 return force_to_mode (XEXP (x, 0), mode, mask, next_select);
7647 /* If this is an AND with a constant, convert it into an AND
7648 whose constant is the AND of that constant with MASK. If it
7649 remains an AND of MASK, delete it since it is redundant. */
7651 if (CONST_INT_P (XEXP (x, 1)))
7653 x = simplify_and_const_int (x, op_mode, XEXP (x, 0),
7654 mask & INTVAL (XEXP (x, 1)));
7656 /* If X is still an AND, see if it is an AND with a mask that
7657 is just some low-order bits. If so, and it is MASK, we don't
7660 if (GET_CODE (x) == AND && CONST_INT_P (XEXP (x, 1))
7661 && ((INTVAL (XEXP (x, 1)) & GET_MODE_MASK (GET_MODE (x)))
7665 /* If it remains an AND, try making another AND with the bits
7666 in the mode mask that aren't in MASK turned on. If the
7667 constant in the AND is wide enough, this might make a
7668 cheaper constant. */
7670 if (GET_CODE (x) == AND && CONST_INT_P (XEXP (x, 1))
7671 && GET_MODE_MASK (GET_MODE (x)) != mask
7672 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT)
7674 HOST_WIDE_INT cval = (INTVAL (XEXP (x, 1))
7675 | (GET_MODE_MASK (GET_MODE (x)) & ~mask));
7676 int width = GET_MODE_BITSIZE (GET_MODE (x));
7679 /* If MODE is narrower than HOST_WIDE_INT and CVAL is a negative
7680 number, sign extend it. */
7681 if (width > 0 && width < HOST_BITS_PER_WIDE_INT
7682 && (cval & ((HOST_WIDE_INT) 1 << (width - 1))) != 0)
7683 cval |= (HOST_WIDE_INT) -1 << width;
7685 y = simplify_gen_binary (AND, GET_MODE (x),
7686 XEXP (x, 0), GEN_INT (cval));
7687 if (rtx_cost (y, SET, optimize_this_for_speed_p)
7688 < rtx_cost (x, SET, optimize_this_for_speed_p))
7698 /* In (and (plus FOO C1) M), if M is a mask that just turns off
7699 low-order bits (as in an alignment operation) and FOO is already
7700 aligned to that boundary, mask C1 to that boundary as well.
7701 This may eliminate that PLUS and, later, the AND. */
7704 unsigned int width = GET_MODE_BITSIZE (mode);
7705 unsigned HOST_WIDE_INT smask = mask;
7707 /* If MODE is narrower than HOST_WIDE_INT and mask is a negative
7708 number, sign extend it. */
7710 if (width < HOST_BITS_PER_WIDE_INT
7711 && (smask & ((HOST_WIDE_INT) 1 << (width - 1))) != 0)
7712 smask |= (HOST_WIDE_INT) -1 << width;
7714 if (CONST_INT_P (XEXP (x, 1))
7715 && exact_log2 (- smask) >= 0
7716 && (nonzero_bits (XEXP (x, 0), mode) & ~smask) == 0
7717 && (INTVAL (XEXP (x, 1)) & ~smask) != 0)
7718 return force_to_mode (plus_constant (XEXP (x, 0),
7719 (INTVAL (XEXP (x, 1)) & smask)),
7720 mode, smask, next_select);
7723 /* ... fall through ... */
7726 /* For PLUS, MINUS and MULT, we need any bits less significant than the
7727 most significant bit in MASK since carries from those bits will
7728 affect the bits we are interested in. */
7733 /* If X is (minus C Y) where C's least set bit is larger than any bit
7734 in the mask, then we may replace with (neg Y). */
7735 if (CONST_INT_P (XEXP (x, 0))
7736 && (((unsigned HOST_WIDE_INT) (INTVAL (XEXP (x, 0))
7737 & -INTVAL (XEXP (x, 0))))
7740 x = simplify_gen_unary (NEG, GET_MODE (x), XEXP (x, 1),
7742 return force_to_mode (x, mode, mask, next_select);
7745 /* Similarly, if C contains every bit in the fuller_mask, then we may
7746 replace with (not Y). */
7747 if (CONST_INT_P (XEXP (x, 0))
7748 && ((INTVAL (XEXP (x, 0)) | (HOST_WIDE_INT) fuller_mask)
7749 == INTVAL (XEXP (x, 0))))
7751 x = simplify_gen_unary (NOT, GET_MODE (x),
7752 XEXP (x, 1), GET_MODE (x));
7753 return force_to_mode (x, mode, mask, next_select);
7761 /* If X is (ior (lshiftrt FOO C1) C2), try to commute the IOR and
7762 LSHIFTRT so we end up with an (and (lshiftrt (ior ...) ...) ...)
7763 operation which may be a bitfield extraction. Ensure that the
7764 constant we form is not wider than the mode of X. */
7766 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
7767 && CONST_INT_P (XEXP (XEXP (x, 0), 1))
7768 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
7769 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT
7770 && CONST_INT_P (XEXP (x, 1))
7771 && ((INTVAL (XEXP (XEXP (x, 0), 1))
7772 + floor_log2 (INTVAL (XEXP (x, 1))))
7773 < GET_MODE_BITSIZE (GET_MODE (x)))
7774 && (INTVAL (XEXP (x, 1))
7775 & ~nonzero_bits (XEXP (x, 0), GET_MODE (x))) == 0)
7777 temp = GEN_INT ((INTVAL (XEXP (x, 1)) & mask)
7778 << INTVAL (XEXP (XEXP (x, 0), 1)));
7779 temp = simplify_gen_binary (GET_CODE (x), GET_MODE (x),
7780 XEXP (XEXP (x, 0), 0), temp);
7781 x = simplify_gen_binary (LSHIFTRT, GET_MODE (x), temp,
7782 XEXP (XEXP (x, 0), 1));
7783 return force_to_mode (x, mode, mask, next_select);
7787 /* For most binary operations, just propagate into the operation and
7788 change the mode if we have an operation of that mode. */
7790 op0 = force_to_mode (XEXP (x, 0), mode, mask, next_select);
7791 op1 = force_to_mode (XEXP (x, 1), mode, mask, next_select);
7793 /* If we ended up truncating both operands, truncate the result of the
7794 operation instead. */
7795 if (GET_CODE (op0) == TRUNCATE
7796 && GET_CODE (op1) == TRUNCATE)
7798 op0 = XEXP (op0, 0);
7799 op1 = XEXP (op1, 0);
7802 op0 = gen_lowpart_or_truncate (op_mode, op0);
7803 op1 = gen_lowpart_or_truncate (op_mode, op1);
7805 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
7806 x = simplify_gen_binary (code, op_mode, op0, op1);
7810 /* For left shifts, do the same, but just for the first operand.
7811 However, we cannot do anything with shifts where we cannot
7812 guarantee that the counts are smaller than the size of the mode
7813 because such a count will have a different meaning in a
7816 if (! (CONST_INT_P (XEXP (x, 1))
7817 && INTVAL (XEXP (x, 1)) >= 0
7818 && INTVAL (XEXP (x, 1)) < GET_MODE_BITSIZE (mode))
7819 && ! (GET_MODE (XEXP (x, 1)) != VOIDmode
7820 && (nonzero_bits (XEXP (x, 1), GET_MODE (XEXP (x, 1)))
7821 < (unsigned HOST_WIDE_INT) GET_MODE_BITSIZE (mode))))
7824 /* If the shift count is a constant and we can do arithmetic in
7825 the mode of the shift, refine which bits we need. Otherwise, use the
7826 conservative form of the mask. */
7827 if (CONST_INT_P (XEXP (x, 1))
7828 && INTVAL (XEXP (x, 1)) >= 0
7829 && INTVAL (XEXP (x, 1)) < GET_MODE_BITSIZE (op_mode)
7830 && GET_MODE_BITSIZE (op_mode) <= HOST_BITS_PER_WIDE_INT)
7831 mask >>= INTVAL (XEXP (x, 1));
7835 op0 = gen_lowpart_or_truncate (op_mode,
7836 force_to_mode (XEXP (x, 0), op_mode,
7837 mask, next_select));
7839 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0))
7840 x = simplify_gen_binary (code, op_mode, op0, XEXP (x, 1));
7844 /* Here we can only do something if the shift count is a constant,
7845 this shift constant is valid for the host, and we can do arithmetic
7848 if (CONST_INT_P (XEXP (x, 1))
7849 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT
7850 && GET_MODE_BITSIZE (op_mode) <= HOST_BITS_PER_WIDE_INT)
7852 rtx inner = XEXP (x, 0);
7853 unsigned HOST_WIDE_INT inner_mask;
7855 /* Select the mask of the bits we need for the shift operand. */
7856 inner_mask = mask << INTVAL (XEXP (x, 1));
7858 /* We can only change the mode of the shift if we can do arithmetic
7859 in the mode of the shift and INNER_MASK is no wider than the
7860 width of X's mode. */
7861 if ((inner_mask & ~GET_MODE_MASK (GET_MODE (x))) != 0)
7862 op_mode = GET_MODE (x);
7864 inner = force_to_mode (inner, op_mode, inner_mask, next_select);
7866 if (GET_MODE (x) != op_mode || inner != XEXP (x, 0))
7867 x = simplify_gen_binary (LSHIFTRT, op_mode, inner, XEXP (x, 1));
7870 /* If we have (and (lshiftrt FOO C1) C2) where the combination of the
7871 shift and AND produces only copies of the sign bit (C2 is one less
7872 than a power of two), we can do this with just a shift. */
7874 if (GET_CODE (x) == LSHIFTRT
7875 && CONST_INT_P (XEXP (x, 1))
7876 /* The shift puts one of the sign bit copies in the least significant
7878 && ((INTVAL (XEXP (x, 1))
7879 + num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0))))
7880 >= GET_MODE_BITSIZE (GET_MODE (x)))
7881 && exact_log2 (mask + 1) >= 0
7882 /* Number of bits left after the shift must be more than the mask
7884 && ((INTVAL (XEXP (x, 1)) + exact_log2 (mask + 1))
7885 <= GET_MODE_BITSIZE (GET_MODE (x)))
7886 /* Must be more sign bit copies than the mask needs. */
7887 && ((int) num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
7888 >= exact_log2 (mask + 1)))
7889 x = simplify_gen_binary (LSHIFTRT, GET_MODE (x), XEXP (x, 0),
7890 GEN_INT (GET_MODE_BITSIZE (GET_MODE (x))
7891 - exact_log2 (mask + 1)));
7896 /* If we are just looking for the sign bit, we don't need this shift at
7897 all, even if it has a variable count. */
7898 if (GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
7899 && (mask == ((unsigned HOST_WIDE_INT) 1
7900 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
7901 return force_to_mode (XEXP (x, 0), mode, mask, next_select);
7903 /* If this is a shift by a constant, get a mask that contains those bits
7904 that are not copies of the sign bit. We then have two cases: If
7905 MASK only includes those bits, this can be a logical shift, which may
7906 allow simplifications. If MASK is a single-bit field not within
7907 those bits, we are requesting a copy of the sign bit and hence can
7908 shift the sign bit to the appropriate location. */
7910 if (CONST_INT_P (XEXP (x, 1)) && INTVAL (XEXP (x, 1)) >= 0
7911 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT)
7915 /* If the considered data is wider than HOST_WIDE_INT, we can't
7916 represent a mask for all its bits in a single scalar.
7917 But we only care about the lower bits, so calculate these. */
7919 if (GET_MODE_BITSIZE (GET_MODE (x)) > HOST_BITS_PER_WIDE_INT)
7921 nonzero = ~(HOST_WIDE_INT) 0;
7923 /* GET_MODE_BITSIZE (GET_MODE (x)) - INTVAL (XEXP (x, 1))
7924 is the number of bits a full-width mask would have set.
7925 We need only shift if these are fewer than nonzero can
7926 hold. If not, we must keep all bits set in nonzero. */
7928 if (GET_MODE_BITSIZE (GET_MODE (x)) - INTVAL (XEXP (x, 1))
7929 < HOST_BITS_PER_WIDE_INT)
7930 nonzero >>= INTVAL (XEXP (x, 1))
7931 + HOST_BITS_PER_WIDE_INT
7932 - GET_MODE_BITSIZE (GET_MODE (x)) ;
7936 nonzero = GET_MODE_MASK (GET_MODE (x));
7937 nonzero >>= INTVAL (XEXP (x, 1));
7940 if ((mask & ~nonzero) == 0)
7942 x = simplify_shift_const (NULL_RTX, LSHIFTRT, GET_MODE (x),
7943 XEXP (x, 0), INTVAL (XEXP (x, 1)));
7944 if (GET_CODE (x) != ASHIFTRT)
7945 return force_to_mode (x, mode, mask, next_select);
7948 else if ((i = exact_log2 (mask)) >= 0)
7950 x = simplify_shift_const
7951 (NULL_RTX, LSHIFTRT, GET_MODE (x), XEXP (x, 0),
7952 GET_MODE_BITSIZE (GET_MODE (x)) - 1 - i);
7954 if (GET_CODE (x) != ASHIFTRT)
7955 return force_to_mode (x, mode, mask, next_select);
7959 /* If MASK is 1, convert this to an LSHIFTRT. This can be done
7960 even if the shift count isn't a constant. */
7962 x = simplify_gen_binary (LSHIFTRT, GET_MODE (x),
7963 XEXP (x, 0), XEXP (x, 1));
7967 /* If this is a zero- or sign-extension operation that just affects bits
7968 we don't care about, remove it. Be sure the call above returned
7969 something that is still a shift. */
7971 if ((GET_CODE (x) == LSHIFTRT || GET_CODE (x) == ASHIFTRT)
7972 && CONST_INT_P (XEXP (x, 1))
7973 && INTVAL (XEXP (x, 1)) >= 0
7974 && (INTVAL (XEXP (x, 1))
7975 <= GET_MODE_BITSIZE (GET_MODE (x)) - (floor_log2 (mask) + 1))
7976 && GET_CODE (XEXP (x, 0)) == ASHIFT
7977 && XEXP (XEXP (x, 0), 1) == XEXP (x, 1))
7978 return force_to_mode (XEXP (XEXP (x, 0), 0), mode, mask,
7985 /* If the shift count is constant and we can do computations
7986 in the mode of X, compute where the bits we care about are.
7987 Otherwise, we can't do anything. Don't change the mode of
7988 the shift or propagate MODE into the shift, though. */
7989 if (CONST_INT_P (XEXP (x, 1))
7990 && INTVAL (XEXP (x, 1)) >= 0)
7992 temp = simplify_binary_operation (code == ROTATE ? ROTATERT : ROTATE,
7993 GET_MODE (x), GEN_INT (mask),
7995 if (temp && CONST_INT_P (temp))
7997 force_to_mode (XEXP (x, 0), GET_MODE (x),
7998 INTVAL (temp), next_select));
8003 /* If we just want the low-order bit, the NEG isn't needed since it
8004 won't change the low-order bit. */
8006 return force_to_mode (XEXP (x, 0), mode, mask, just_select);
8008 /* We need any bits less significant than the most significant bit in
8009 MASK since carries from those bits will affect the bits we are
8015 /* (not FOO) is (xor FOO CONST), so if FOO is an LSHIFTRT, we can do the
8016 same as the XOR case above. Ensure that the constant we form is not
8017 wider than the mode of X. */
8019 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
8020 && CONST_INT_P (XEXP (XEXP (x, 0), 1))
8021 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
8022 && (INTVAL (XEXP (XEXP (x, 0), 1)) + floor_log2 (mask)
8023 < GET_MODE_BITSIZE (GET_MODE (x)))
8024 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT)
8026 temp = gen_int_mode (mask << INTVAL (XEXP (XEXP (x, 0), 1)),
8028 temp = simplify_gen_binary (XOR, GET_MODE (x),
8029 XEXP (XEXP (x, 0), 0), temp);
8030 x = simplify_gen_binary (LSHIFTRT, GET_MODE (x),
8031 temp, XEXP (XEXP (x, 0), 1));
8033 return force_to_mode (x, mode, mask, next_select);
8036 /* (and (not FOO) CONST) is (not (or FOO (not CONST))), so we must
8037 use the full mask inside the NOT. */
8041 op0 = gen_lowpart_or_truncate (op_mode,
8042 force_to_mode (XEXP (x, 0), mode, mask,
8044 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0))
8045 x = simplify_gen_unary (code, op_mode, op0, op_mode);
8049 /* (and (ne FOO 0) CONST) can be (and FOO CONST) if CONST is included
8050 in STORE_FLAG_VALUE and FOO has a single bit that might be nonzero,
8051 which is equal to STORE_FLAG_VALUE. */
8052 if ((mask & ~STORE_FLAG_VALUE) == 0 && XEXP (x, 1) == const0_rtx
8053 && GET_MODE (XEXP (x, 0)) == mode
8054 && exact_log2 (nonzero_bits (XEXP (x, 0), mode)) >= 0
8055 && (nonzero_bits (XEXP (x, 0), mode)
8056 == (unsigned HOST_WIDE_INT) STORE_FLAG_VALUE))
8057 return force_to_mode (XEXP (x, 0), mode, mask, next_select);
8062 /* We have no way of knowing if the IF_THEN_ELSE can itself be
8063 written in a narrower mode. We play it safe and do not do so. */
8066 gen_lowpart_or_truncate (GET_MODE (x),
8067 force_to_mode (XEXP (x, 1), mode,
8068 mask, next_select)));
8070 gen_lowpart_or_truncate (GET_MODE (x),
8071 force_to_mode (XEXP (x, 2), mode,
8072 mask, next_select)));
8079 /* Ensure we return a value of the proper mode. */
8080 return gen_lowpart_or_truncate (mode, x);
8083 /* Return nonzero if X is an expression that has one of two values depending on
8084 whether some other value is zero or nonzero. In that case, we return the
8085 value that is being tested, *PTRUE is set to the value if the rtx being
8086 returned has a nonzero value, and *PFALSE is set to the other alternative.
8088 If we return zero, we set *PTRUE and *PFALSE to X. */
8091 if_then_else_cond (rtx x, rtx *ptrue, rtx *pfalse)
8093 enum machine_mode mode = GET_MODE (x);
8094 enum rtx_code code = GET_CODE (x);
8095 rtx cond0, cond1, true0, true1, false0, false1;
8096 unsigned HOST_WIDE_INT nz;
8098 /* If we are comparing a value against zero, we are done. */
8099 if ((code == NE || code == EQ)
8100 && XEXP (x, 1) == const0_rtx)
8102 *ptrue = (code == NE) ? const_true_rtx : const0_rtx;
8103 *pfalse = (code == NE) ? const0_rtx : const_true_rtx;
8107 /* If this is a unary operation whose operand has one of two values, apply
8108 our opcode to compute those values. */
8109 else if (UNARY_P (x)
8110 && (cond0 = if_then_else_cond (XEXP (x, 0), &true0, &false0)) != 0)
8112 *ptrue = simplify_gen_unary (code, mode, true0, GET_MODE (XEXP (x, 0)));
8113 *pfalse = simplify_gen_unary (code, mode, false0,
8114 GET_MODE (XEXP (x, 0)));
8118 /* If this is a COMPARE, do nothing, since the IF_THEN_ELSE we would
8119 make can't possibly match and would suppress other optimizations. */
8120 else if (code == COMPARE)
8123 /* If this is a binary operation, see if either side has only one of two
8124 values. If either one does or if both do and they are conditional on
8125 the same value, compute the new true and false values. */
8126 else if (BINARY_P (x))
8128 cond0 = if_then_else_cond (XEXP (x, 0), &true0, &false0);
8129 cond1 = if_then_else_cond (XEXP (x, 1), &true1, &false1);
8131 if ((cond0 != 0 || cond1 != 0)
8132 && ! (cond0 != 0 && cond1 != 0 && ! rtx_equal_p (cond0, cond1)))
8134 /* If if_then_else_cond returned zero, then true/false are the
8135 same rtl. We must copy one of them to prevent invalid rtl
8138 true0 = copy_rtx (true0);
8139 else if (cond1 == 0)
8140 true1 = copy_rtx (true1);
8142 if (COMPARISON_P (x))
8144 *ptrue = simplify_gen_relational (code, mode, VOIDmode,
8146 *pfalse = simplify_gen_relational (code, mode, VOIDmode,
8151 *ptrue = simplify_gen_binary (code, mode, true0, true1);
8152 *pfalse = simplify_gen_binary (code, mode, false0, false1);
8155 return cond0 ? cond0 : cond1;
8158 /* See if we have PLUS, IOR, XOR, MINUS or UMAX, where one of the
8159 operands is zero when the other is nonzero, and vice-versa,
8160 and STORE_FLAG_VALUE is 1 or -1. */
8162 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
8163 && (code == PLUS || code == IOR || code == XOR || code == MINUS
8165 && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT)
8167 rtx op0 = XEXP (XEXP (x, 0), 1);
8168 rtx op1 = XEXP (XEXP (x, 1), 1);
8170 cond0 = XEXP (XEXP (x, 0), 0);
8171 cond1 = XEXP (XEXP (x, 1), 0);
8173 if (COMPARISON_P (cond0)
8174 && COMPARISON_P (cond1)
8175 && ((GET_CODE (cond0) == reversed_comparison_code (cond1, NULL)
8176 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0))
8177 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1)))
8178 || ((swap_condition (GET_CODE (cond0))
8179 == reversed_comparison_code (cond1, NULL))
8180 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1))
8181 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0))))
8182 && ! side_effects_p (x))
8184 *ptrue = simplify_gen_binary (MULT, mode, op0, const_true_rtx);
8185 *pfalse = simplify_gen_binary (MULT, mode,
8187 ? simplify_gen_unary (NEG, mode,
8195 /* Similarly for MULT, AND and UMIN, except that for these the result
8197 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
8198 && (code == MULT || code == AND || code == UMIN)
8199 && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT)
8201 cond0 = XEXP (XEXP (x, 0), 0);
8202 cond1 = XEXP (XEXP (x, 1), 0);
8204 if (COMPARISON_P (cond0)
8205 && COMPARISON_P (cond1)
8206 && ((GET_CODE (cond0) == reversed_comparison_code (cond1, NULL)
8207 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0))
8208 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1)))
8209 || ((swap_condition (GET_CODE (cond0))
8210 == reversed_comparison_code (cond1, NULL))
8211 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1))
8212 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0))))
8213 && ! side_effects_p (x))
8215 *ptrue = *pfalse = const0_rtx;
8221 else if (code == IF_THEN_ELSE)
8223 /* If we have IF_THEN_ELSE already, extract the condition and
8224 canonicalize it if it is NE or EQ. */
8225 cond0 = XEXP (x, 0);
8226 *ptrue = XEXP (x, 1), *pfalse = XEXP (x, 2);
8227 if (GET_CODE (cond0) == NE && XEXP (cond0, 1) == const0_rtx)
8228 return XEXP (cond0, 0);
8229 else if (GET_CODE (cond0) == EQ && XEXP (cond0, 1) == const0_rtx)
8231 *ptrue = XEXP (x, 2), *pfalse = XEXP (x, 1);
8232 return XEXP (cond0, 0);
8238 /* If X is a SUBREG, we can narrow both the true and false values
8239 if the inner expression, if there is a condition. */
8240 else if (code == SUBREG
8241 && 0 != (cond0 = if_then_else_cond (SUBREG_REG (x),
8244 true0 = simplify_gen_subreg (mode, true0,
8245 GET_MODE (SUBREG_REG (x)), SUBREG_BYTE (x));
8246 false0 = simplify_gen_subreg (mode, false0,
8247 GET_MODE (SUBREG_REG (x)), SUBREG_BYTE (x));
8248 if (true0 && false0)
8256 /* If X is a constant, this isn't special and will cause confusions
8257 if we treat it as such. Likewise if it is equivalent to a constant. */
8258 else if (CONSTANT_P (x)
8259 || ((cond0 = get_last_value (x)) != 0 && CONSTANT_P (cond0)))
8262 /* If we're in BImode, canonicalize on 0 and STORE_FLAG_VALUE, as that
8263 will be least confusing to the rest of the compiler. */
8264 else if (mode == BImode)
8266 *ptrue = GEN_INT (STORE_FLAG_VALUE), *pfalse = const0_rtx;
8270 /* If X is known to be either 0 or -1, those are the true and
8271 false values when testing X. */
8272 else if (x == constm1_rtx || x == const0_rtx
8273 || (mode != VOIDmode
8274 && num_sign_bit_copies (x, mode) == GET_MODE_BITSIZE (mode)))
8276 *ptrue = constm1_rtx, *pfalse = const0_rtx;
8280 /* Likewise for 0 or a single bit. */
8281 else if (SCALAR_INT_MODE_P (mode)
8282 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
8283 && exact_log2 (nz = nonzero_bits (x, mode)) >= 0)
8285 *ptrue = gen_int_mode (nz, mode), *pfalse = const0_rtx;
8289 /* Otherwise fail; show no condition with true and false values the same. */
8290 *ptrue = *pfalse = x;
8294 /* Return the value of expression X given the fact that condition COND
8295 is known to be true when applied to REG as its first operand and VAL
8296 as its second. X is known to not be shared and so can be modified in
8299 We only handle the simplest cases, and specifically those cases that
8300 arise with IF_THEN_ELSE expressions. */
8303 known_cond (rtx x, enum rtx_code cond, rtx reg, rtx val)
8305 enum rtx_code code = GET_CODE (x);
8310 if (side_effects_p (x))
8313 /* If either operand of the condition is a floating point value,
8314 then we have to avoid collapsing an EQ comparison. */
8316 && rtx_equal_p (x, reg)
8317 && ! FLOAT_MODE_P (GET_MODE (x))
8318 && ! FLOAT_MODE_P (GET_MODE (val)))
8321 if (cond == UNEQ && rtx_equal_p (x, reg))
8324 /* If X is (abs REG) and we know something about REG's relationship
8325 with zero, we may be able to simplify this. */
8327 if (code == ABS && rtx_equal_p (XEXP (x, 0), reg) && val == const0_rtx)
8330 case GE: case GT: case EQ:
8333 return simplify_gen_unary (NEG, GET_MODE (XEXP (x, 0)),
8335 GET_MODE (XEXP (x, 0)));
8340 /* The only other cases we handle are MIN, MAX, and comparisons if the
8341 operands are the same as REG and VAL. */
8343 else if (COMPARISON_P (x) || COMMUTATIVE_ARITH_P (x))
8345 if (rtx_equal_p (XEXP (x, 0), val))
8346 cond = swap_condition (cond), temp = val, val = reg, reg = temp;
8348 if (rtx_equal_p (XEXP (x, 0), reg) && rtx_equal_p (XEXP (x, 1), val))
8350 if (COMPARISON_P (x))
8352 if (comparison_dominates_p (cond, code))
8353 return const_true_rtx;
8355 code = reversed_comparison_code (x, NULL);
8357 && comparison_dominates_p (cond, code))
8362 else if (code == SMAX || code == SMIN
8363 || code == UMIN || code == UMAX)
8365 int unsignedp = (code == UMIN || code == UMAX);
8367 /* Do not reverse the condition when it is NE or EQ.
8368 This is because we cannot conclude anything about
8369 the value of 'SMAX (x, y)' when x is not equal to y,
8370 but we can when x equals y. */
8371 if ((code == SMAX || code == UMAX)
8372 && ! (cond == EQ || cond == NE))
8373 cond = reverse_condition (cond);
8378 return unsignedp ? x : XEXP (x, 1);
8380 return unsignedp ? x : XEXP (x, 0);
8382 return unsignedp ? XEXP (x, 1) : x;
8384 return unsignedp ? XEXP (x, 0) : x;
8391 else if (code == SUBREG)
8393 enum machine_mode inner_mode = GET_MODE (SUBREG_REG (x));
8394 rtx new_rtx, r = known_cond (SUBREG_REG (x), cond, reg, val);
8396 if (SUBREG_REG (x) != r)
8398 /* We must simplify subreg here, before we lose track of the
8399 original inner_mode. */
8400 new_rtx = simplify_subreg (GET_MODE (x), r,
8401 inner_mode, SUBREG_BYTE (x));
8405 SUBST (SUBREG_REG (x), r);
8410 /* We don't have to handle SIGN_EXTEND here, because even in the
8411 case of replacing something with a modeless CONST_INT, a
8412 CONST_INT is already (supposed to be) a valid sign extension for
8413 its narrower mode, which implies it's already properly
8414 sign-extended for the wider mode. Now, for ZERO_EXTEND, the
8415 story is different. */
8416 else if (code == ZERO_EXTEND)
8418 enum machine_mode inner_mode = GET_MODE (XEXP (x, 0));
8419 rtx new_rtx, r = known_cond (XEXP (x, 0), cond, reg, val);
8421 if (XEXP (x, 0) != r)
8423 /* We must simplify the zero_extend here, before we lose
8424 track of the original inner_mode. */
8425 new_rtx = simplify_unary_operation (ZERO_EXTEND, GET_MODE (x),
8430 SUBST (XEXP (x, 0), r);
8436 fmt = GET_RTX_FORMAT (code);
8437 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
8440 SUBST (XEXP (x, i), known_cond (XEXP (x, i), cond, reg, val));
8441 else if (fmt[i] == 'E')
8442 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
8443 SUBST (XVECEXP (x, i, j), known_cond (XVECEXP (x, i, j),
8450 /* See if X and Y are equal for the purposes of seeing if we can rewrite an
8451 assignment as a field assignment. */
8454 rtx_equal_for_field_assignment_p (rtx x, rtx y)
8456 if (x == y || rtx_equal_p (x, y))
8459 if (x == 0 || y == 0 || GET_MODE (x) != GET_MODE (y))
8462 /* Check for a paradoxical SUBREG of a MEM compared with the MEM.
8463 Note that all SUBREGs of MEM are paradoxical; otherwise they
8464 would have been rewritten. */
8465 if (MEM_P (x) && GET_CODE (y) == SUBREG
8466 && MEM_P (SUBREG_REG (y))
8467 && rtx_equal_p (SUBREG_REG (y),
8468 gen_lowpart (GET_MODE (SUBREG_REG (y)), x)))
8471 if (MEM_P (y) && GET_CODE (x) == SUBREG
8472 && MEM_P (SUBREG_REG (x))
8473 && rtx_equal_p (SUBREG_REG (x),
8474 gen_lowpart (GET_MODE (SUBREG_REG (x)), y)))
8477 /* We used to see if get_last_value of X and Y were the same but that's
8478 not correct. In one direction, we'll cause the assignment to have
8479 the wrong destination and in the case, we'll import a register into this
8480 insn that might have already have been dead. So fail if none of the
8481 above cases are true. */
8485 /* See if X, a SET operation, can be rewritten as a bit-field assignment.
8486 Return that assignment if so.
8488 We only handle the most common cases. */
8491 make_field_assignment (rtx x)
8493 rtx dest = SET_DEST (x);
8494 rtx src = SET_SRC (x);
8499 unsigned HOST_WIDE_INT len;
8501 enum machine_mode mode;
8503 /* If SRC was (and (not (ashift (const_int 1) POS)) DEST), this is
8504 a clear of a one-bit field. We will have changed it to
8505 (and (rotate (const_int -2) POS) DEST), so check for that. Also check
8508 if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == ROTATE
8509 && CONST_INT_P (XEXP (XEXP (src, 0), 0))
8510 && INTVAL (XEXP (XEXP (src, 0), 0)) == -2
8511 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
8513 assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1),
8516 return gen_rtx_SET (VOIDmode, assign, const0_rtx);
8520 if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == SUBREG
8521 && subreg_lowpart_p (XEXP (src, 0))
8522 && (GET_MODE_SIZE (GET_MODE (XEXP (src, 0)))
8523 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (src, 0)))))
8524 && GET_CODE (SUBREG_REG (XEXP (src, 0))) == ROTATE
8525 && CONST_INT_P (XEXP (SUBREG_REG (XEXP (src, 0)), 0))
8526 && INTVAL (XEXP (SUBREG_REG (XEXP (src, 0)), 0)) == -2
8527 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
8529 assign = make_extraction (VOIDmode, dest, 0,
8530 XEXP (SUBREG_REG (XEXP (src, 0)), 1),
8533 return gen_rtx_SET (VOIDmode, assign, const0_rtx);
8537 /* If SRC is (ior (ashift (const_int 1) POS) DEST), this is a set of a
8539 if (GET_CODE (src) == IOR && GET_CODE (XEXP (src, 0)) == ASHIFT
8540 && XEXP (XEXP (src, 0), 0) == const1_rtx
8541 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
8543 assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1),
8546 return gen_rtx_SET (VOIDmode, assign, const1_rtx);
8550 /* If DEST is already a field assignment, i.e. ZERO_EXTRACT, and the
8551 SRC is an AND with all bits of that field set, then we can discard
8553 if (GET_CODE (dest) == ZERO_EXTRACT
8554 && CONST_INT_P (XEXP (dest, 1))
8555 && GET_CODE (src) == AND
8556 && CONST_INT_P (XEXP (src, 1)))
8558 HOST_WIDE_INT width = INTVAL (XEXP (dest, 1));
8559 unsigned HOST_WIDE_INT and_mask = INTVAL (XEXP (src, 1));
8560 unsigned HOST_WIDE_INT ze_mask;
8562 if (width >= HOST_BITS_PER_WIDE_INT)
8565 ze_mask = ((unsigned HOST_WIDE_INT)1 << width) - 1;
8567 /* Complete overlap. We can remove the source AND. */
8568 if ((and_mask & ze_mask) == ze_mask)
8569 return gen_rtx_SET (VOIDmode, dest, XEXP (src, 0));
8571 /* Partial overlap. We can reduce the source AND. */
8572 if ((and_mask & ze_mask) != and_mask)
8574 mode = GET_MODE (src);
8575 src = gen_rtx_AND (mode, XEXP (src, 0),
8576 gen_int_mode (and_mask & ze_mask, mode));
8577 return gen_rtx_SET (VOIDmode, dest, src);
8581 /* The other case we handle is assignments into a constant-position
8582 field. They look like (ior/xor (and DEST C1) OTHER). If C1 represents
8583 a mask that has all one bits except for a group of zero bits and
8584 OTHER is known to have zeros where C1 has ones, this is such an
8585 assignment. Compute the position and length from C1. Shift OTHER
8586 to the appropriate position, force it to the required mode, and
8587 make the extraction. Check for the AND in both operands. */
8589 if (GET_CODE (src) != IOR && GET_CODE (src) != XOR)
8592 rhs = expand_compound_operation (XEXP (src, 0));
8593 lhs = expand_compound_operation (XEXP (src, 1));
8595 if (GET_CODE (rhs) == AND
8596 && CONST_INT_P (XEXP (rhs, 1))
8597 && rtx_equal_for_field_assignment_p (XEXP (rhs, 0), dest))
8598 c1 = INTVAL (XEXP (rhs, 1)), other = lhs;
8599 else if (GET_CODE (lhs) == AND
8600 && CONST_INT_P (XEXP (lhs, 1))
8601 && rtx_equal_for_field_assignment_p (XEXP (lhs, 0), dest))
8602 c1 = INTVAL (XEXP (lhs, 1)), other = rhs;
8606 pos = get_pos_from_mask ((~c1) & GET_MODE_MASK (GET_MODE (dest)), &len);
8607 if (pos < 0 || pos + len > GET_MODE_BITSIZE (GET_MODE (dest))
8608 || GET_MODE_BITSIZE (GET_MODE (dest)) > HOST_BITS_PER_WIDE_INT
8609 || (c1 & nonzero_bits (other, GET_MODE (dest))) != 0)
8612 assign = make_extraction (VOIDmode, dest, pos, NULL_RTX, len, 1, 1, 0);
8616 /* The mode to use for the source is the mode of the assignment, or of
8617 what is inside a possible STRICT_LOW_PART. */
8618 mode = (GET_CODE (assign) == STRICT_LOW_PART
8619 ? GET_MODE (XEXP (assign, 0)) : GET_MODE (assign));
8621 /* Shift OTHER right POS places and make it the source, restricting it
8622 to the proper length and mode. */
8624 src = canon_reg_for_combine (simplify_shift_const (NULL_RTX, LSHIFTRT,
8628 src = force_to_mode (src, mode,
8629 GET_MODE_BITSIZE (mode) >= HOST_BITS_PER_WIDE_INT
8630 ? ~(unsigned HOST_WIDE_INT) 0
8631 : ((unsigned HOST_WIDE_INT) 1 << len) - 1,
8634 /* If SRC is masked by an AND that does not make a difference in
8635 the value being stored, strip it. */
8636 if (GET_CODE (assign) == ZERO_EXTRACT
8637 && CONST_INT_P (XEXP (assign, 1))
8638 && INTVAL (XEXP (assign, 1)) < HOST_BITS_PER_WIDE_INT
8639 && GET_CODE (src) == AND
8640 && CONST_INT_P (XEXP (src, 1))
8641 && ((unsigned HOST_WIDE_INT) INTVAL (XEXP (src, 1))
8642 == ((unsigned HOST_WIDE_INT) 1 << INTVAL (XEXP (assign, 1))) - 1))
8643 src = XEXP (src, 0);
8645 return gen_rtx_SET (VOIDmode, assign, src);
8648 /* See if X is of the form (+ (* a c) (* b c)) and convert to (* (+ a b) c)
8652 apply_distributive_law (rtx x)
8654 enum rtx_code code = GET_CODE (x);
8655 enum rtx_code inner_code;
8656 rtx lhs, rhs, other;
8659 /* Distributivity is not true for floating point as it can change the
8660 value. So we don't do it unless -funsafe-math-optimizations. */
8661 if (FLOAT_MODE_P (GET_MODE (x))
8662 && ! flag_unsafe_math_optimizations)
8665 /* The outer operation can only be one of the following: */
8666 if (code != IOR && code != AND && code != XOR
8667 && code != PLUS && code != MINUS)
8673 /* If either operand is a primitive we can't do anything, so get out
8675 if (OBJECT_P (lhs) || OBJECT_P (rhs))
8678 lhs = expand_compound_operation (lhs);
8679 rhs = expand_compound_operation (rhs);
8680 inner_code = GET_CODE (lhs);
8681 if (inner_code != GET_CODE (rhs))
8684 /* See if the inner and outer operations distribute. */
8691 /* These all distribute except over PLUS. */
8692 if (code == PLUS || code == MINUS)
8697 if (code != PLUS && code != MINUS)
8702 /* This is also a multiply, so it distributes over everything. */
8706 /* Non-paradoxical SUBREGs distributes over all operations,
8707 provided the inner modes and byte offsets are the same, this
8708 is an extraction of a low-order part, we don't convert an fp
8709 operation to int or vice versa, this is not a vector mode,
8710 and we would not be converting a single-word operation into a
8711 multi-word operation. The latter test is not required, but
8712 it prevents generating unneeded multi-word operations. Some
8713 of the previous tests are redundant given the latter test,
8714 but are retained because they are required for correctness.
8716 We produce the result slightly differently in this case. */
8718 if (GET_MODE (SUBREG_REG (lhs)) != GET_MODE (SUBREG_REG (rhs))
8719 || SUBREG_BYTE (lhs) != SUBREG_BYTE (rhs)
8720 || ! subreg_lowpart_p (lhs)
8721 || (GET_MODE_CLASS (GET_MODE (lhs))
8722 != GET_MODE_CLASS (GET_MODE (SUBREG_REG (lhs))))
8723 || (GET_MODE_SIZE (GET_MODE (lhs))
8724 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs))))
8725 || VECTOR_MODE_P (GET_MODE (lhs))
8726 || GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs))) > UNITS_PER_WORD
8727 /* Result might need to be truncated. Don't change mode if
8728 explicit truncation is needed. */
8729 || !TRULY_NOOP_TRUNCATION
8730 (GET_MODE_BITSIZE (GET_MODE (x)),
8731 GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (lhs)))))
8734 tem = simplify_gen_binary (code, GET_MODE (SUBREG_REG (lhs)),
8735 SUBREG_REG (lhs), SUBREG_REG (rhs));
8736 return gen_lowpart (GET_MODE (x), tem);
8742 /* Set LHS and RHS to the inner operands (A and B in the example
8743 above) and set OTHER to the common operand (C in the example).
8744 There is only one way to do this unless the inner operation is
8746 if (COMMUTATIVE_ARITH_P (lhs)
8747 && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 0)))
8748 other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 1);
8749 else if (COMMUTATIVE_ARITH_P (lhs)
8750 && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 1)))
8751 other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 0);
8752 else if (COMMUTATIVE_ARITH_P (lhs)
8753 && rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 0)))
8754 other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 1);
8755 else if (rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 1)))
8756 other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 0);
8760 /* Form the new inner operation, seeing if it simplifies first. */
8761 tem = simplify_gen_binary (code, GET_MODE (x), lhs, rhs);
8763 /* There is one exception to the general way of distributing:
8764 (a | c) ^ (b | c) -> (a ^ b) & ~c */
8765 if (code == XOR && inner_code == IOR)
8768 other = simplify_gen_unary (NOT, GET_MODE (x), other, GET_MODE (x));
8771 /* We may be able to continuing distributing the result, so call
8772 ourselves recursively on the inner operation before forming the
8773 outer operation, which we return. */
8774 return simplify_gen_binary (inner_code, GET_MODE (x),
8775 apply_distributive_law (tem), other);
8778 /* See if X is of the form (* (+ A B) C), and if so convert to
8779 (+ (* A C) (* B C)) and try to simplify.
8781 Most of the time, this results in no change. However, if some of
8782 the operands are the same or inverses of each other, simplifications
8785 For example, (and (ior A B) (not B)) can occur as the result of
8786 expanding a bit field assignment. When we apply the distributive
8787 law to this, we get (ior (and (A (not B))) (and (B (not B)))),
8788 which then simplifies to (and (A (not B))).
8790 Note that no checks happen on the validity of applying the inverse
8791 distributive law. This is pointless since we can do it in the
8792 few places where this routine is called.
8794 N is the index of the term that is decomposed (the arithmetic operation,
8795 i.e. (+ A B) in the first example above). !N is the index of the term that
8796 is distributed, i.e. of C in the first example above. */
8798 distribute_and_simplify_rtx (rtx x, int n)
8800 enum machine_mode mode;
8801 enum rtx_code outer_code, inner_code;
8802 rtx decomposed, distributed, inner_op0, inner_op1, new_op0, new_op1, tmp;
8804 /* Distributivity is not true for floating point as it can change the
8805 value. So we don't do it unless -funsafe-math-optimizations. */
8806 if (FLOAT_MODE_P (GET_MODE (x))
8807 && ! flag_unsafe_math_optimizations)
8810 decomposed = XEXP (x, n);
8811 if (!ARITHMETIC_P (decomposed))
8814 mode = GET_MODE (x);
8815 outer_code = GET_CODE (x);
8816 distributed = XEXP (x, !n);
8818 inner_code = GET_CODE (decomposed);
8819 inner_op0 = XEXP (decomposed, 0);
8820 inner_op1 = XEXP (decomposed, 1);
8822 /* Special case (and (xor B C) (not A)), which is equivalent to
8823 (xor (ior A B) (ior A C)) */
8824 if (outer_code == AND && inner_code == XOR && GET_CODE (distributed) == NOT)
8826 distributed = XEXP (distributed, 0);
8832 /* Distribute the second term. */
8833 new_op0 = simplify_gen_binary (outer_code, mode, inner_op0, distributed);
8834 new_op1 = simplify_gen_binary (outer_code, mode, inner_op1, distributed);
8838 /* Distribute the first term. */
8839 new_op0 = simplify_gen_binary (outer_code, mode, distributed, inner_op0);
8840 new_op1 = simplify_gen_binary (outer_code, mode, distributed, inner_op1);
8843 tmp = apply_distributive_law (simplify_gen_binary (inner_code, mode,
8845 if (GET_CODE (tmp) != outer_code
8846 && rtx_cost (tmp, SET, optimize_this_for_speed_p)
8847 < rtx_cost (x, SET, optimize_this_for_speed_p))
8853 /* Simplify a logical `and' of VAROP with the constant CONSTOP, to be done
8854 in MODE. Return an equivalent form, if different from (and VAROP
8855 (const_int CONSTOP)). Otherwise, return NULL_RTX. */
8858 simplify_and_const_int_1 (enum machine_mode mode, rtx varop,
8859 unsigned HOST_WIDE_INT constop)
8861 unsigned HOST_WIDE_INT nonzero;
8862 unsigned HOST_WIDE_INT orig_constop;
8867 orig_constop = constop;
8868 if (GET_CODE (varop) == CLOBBER)
8871 /* Simplify VAROP knowing that we will be only looking at some of the
8874 Note by passing in CONSTOP, we guarantee that the bits not set in
8875 CONSTOP are not significant and will never be examined. We must
8876 ensure that is the case by explicitly masking out those bits
8877 before returning. */
8878 varop = force_to_mode (varop, mode, constop, 0);
8880 /* If VAROP is a CLOBBER, we will fail so return it. */
8881 if (GET_CODE (varop) == CLOBBER)
8884 /* If VAROP is a CONST_INT, then we need to apply the mask in CONSTOP
8885 to VAROP and return the new constant. */
8886 if (CONST_INT_P (varop))
8887 return gen_int_mode (INTVAL (varop) & constop, mode);
8889 /* See what bits may be nonzero in VAROP. Unlike the general case of
8890 a call to nonzero_bits, here we don't care about bits outside
8893 nonzero = nonzero_bits (varop, mode) & GET_MODE_MASK (mode);
8895 /* Turn off all bits in the constant that are known to already be zero.
8896 Thus, if the AND isn't needed at all, we will have CONSTOP == NONZERO_BITS
8897 which is tested below. */
8901 /* If we don't have any bits left, return zero. */
8905 /* If VAROP is a NEG of something known to be zero or 1 and CONSTOP is
8906 a power of two, we can replace this with an ASHIFT. */
8907 if (GET_CODE (varop) == NEG && nonzero_bits (XEXP (varop, 0), mode) == 1
8908 && (i = exact_log2 (constop)) >= 0)
8909 return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (varop, 0), i);
8911 /* If VAROP is an IOR or XOR, apply the AND to both branches of the IOR
8912 or XOR, then try to apply the distributive law. This may eliminate
8913 operations if either branch can be simplified because of the AND.
8914 It may also make some cases more complex, but those cases probably
8915 won't match a pattern either with or without this. */
8917 if (GET_CODE (varop) == IOR || GET_CODE (varop) == XOR)
8921 apply_distributive_law
8922 (simplify_gen_binary (GET_CODE (varop), GET_MODE (varop),
8923 simplify_and_const_int (NULL_RTX,
8927 simplify_and_const_int (NULL_RTX,
8932 /* If VAROP is PLUS, and the constant is a mask of low bits, distribute
8933 the AND and see if one of the operands simplifies to zero. If so, we
8934 may eliminate it. */
8936 if (GET_CODE (varop) == PLUS
8937 && exact_log2 (constop + 1) >= 0)
8941 o0 = simplify_and_const_int (NULL_RTX, mode, XEXP (varop, 0), constop);
8942 o1 = simplify_and_const_int (NULL_RTX, mode, XEXP (varop, 1), constop);
8943 if (o0 == const0_rtx)
8945 if (o1 == const0_rtx)
8949 /* Make a SUBREG if necessary. If we can't make it, fail. */
8950 varop = gen_lowpart (mode, varop);
8951 if (varop == NULL_RTX || GET_CODE (varop) == CLOBBER)
8954 /* If we are only masking insignificant bits, return VAROP. */
8955 if (constop == nonzero)
8958 if (varop == orig_varop && constop == orig_constop)
8961 /* Otherwise, return an AND. */
8962 return simplify_gen_binary (AND, mode, varop, gen_int_mode (constop, mode));
8966 /* We have X, a logical `and' of VAROP with the constant CONSTOP, to be done
8969 Return an equivalent form, if different from X. Otherwise, return X. If
8970 X is zero, we are to always construct the equivalent form. */
8973 simplify_and_const_int (rtx x, enum machine_mode mode, rtx varop,
8974 unsigned HOST_WIDE_INT constop)
8976 rtx tem = simplify_and_const_int_1 (mode, varop, constop);
8981 x = simplify_gen_binary (AND, GET_MODE (varop), varop,
8982 gen_int_mode (constop, mode));
8983 if (GET_MODE (x) != mode)
8984 x = gen_lowpart (mode, x);
8988 /* Given a REG, X, compute which bits in X can be nonzero.
8989 We don't care about bits outside of those defined in MODE.
8991 For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is
8992 a shift, AND, or zero_extract, we can do better. */
8995 reg_nonzero_bits_for_combine (const_rtx x, enum machine_mode mode,
8996 const_rtx known_x ATTRIBUTE_UNUSED,
8997 enum machine_mode known_mode ATTRIBUTE_UNUSED,
8998 unsigned HOST_WIDE_INT known_ret ATTRIBUTE_UNUSED,
8999 unsigned HOST_WIDE_INT *nonzero)
9004 /* If X is a register whose nonzero bits value is current, use it.
9005 Otherwise, if X is a register whose value we can find, use that
9006 value. Otherwise, use the previously-computed global nonzero bits
9007 for this register. */
9009 rsp = VEC_index (reg_stat_type, reg_stat, REGNO (x));
9010 if (rsp->last_set_value != 0
9011 && (rsp->last_set_mode == mode
9012 || (GET_MODE_CLASS (rsp->last_set_mode) == MODE_INT
9013 && GET_MODE_CLASS (mode) == MODE_INT))
9014 && ((rsp->last_set_label >= label_tick_ebb_start
9015 && rsp->last_set_label < label_tick)
9016 || (rsp->last_set_label == label_tick
9017 && DF_INSN_LUID (rsp->last_set) < subst_low_luid)
9018 || (REGNO (x) >= FIRST_PSEUDO_REGISTER
9019 && REG_N_SETS (REGNO (x)) == 1
9021 (DF_LR_IN (ENTRY_BLOCK_PTR->next_bb), REGNO (x)))))
9023 *nonzero &= rsp->last_set_nonzero_bits;
9027 tem = get_last_value (x);
9031 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
9032 /* If X is narrower than MODE and TEM is a non-negative
9033 constant that would appear negative in the mode of X,
9034 sign-extend it for use in reg_nonzero_bits because some
9035 machines (maybe most) will actually do the sign-extension
9036 and this is the conservative approach.
9038 ??? For 2.5, try to tighten up the MD files in this regard
9039 instead of this kludge. */
9041 if (GET_MODE_BITSIZE (GET_MODE (x)) < GET_MODE_BITSIZE (mode)
9042 && CONST_INT_P (tem)
9044 && 0 != (INTVAL (tem)
9045 & ((HOST_WIDE_INT) 1
9046 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
9047 tem = GEN_INT (INTVAL (tem)
9048 | ((HOST_WIDE_INT) (-1)
9049 << GET_MODE_BITSIZE (GET_MODE (x))));
9053 else if (nonzero_sign_valid && rsp->nonzero_bits)
9055 unsigned HOST_WIDE_INT mask = rsp->nonzero_bits;
9057 if (GET_MODE_BITSIZE (GET_MODE (x)) < GET_MODE_BITSIZE (mode))
9058 /* We don't know anything about the upper bits. */
9059 mask |= GET_MODE_MASK (mode) ^ GET_MODE_MASK (GET_MODE (x));
9066 /* Return the number of bits at the high-order end of X that are known to
9067 be equal to the sign bit. X will be used in mode MODE; if MODE is
9068 VOIDmode, X will be used in its own mode. The returned value will always
9069 be between 1 and the number of bits in MODE. */
9072 reg_num_sign_bit_copies_for_combine (const_rtx x, enum machine_mode mode,
9073 const_rtx known_x ATTRIBUTE_UNUSED,
9074 enum machine_mode known_mode
9076 unsigned int known_ret ATTRIBUTE_UNUSED,
9077 unsigned int *result)
9082 rsp = VEC_index (reg_stat_type, reg_stat, REGNO (x));
9083 if (rsp->last_set_value != 0
9084 && rsp->last_set_mode == mode
9085 && ((rsp->last_set_label >= label_tick_ebb_start
9086 && rsp->last_set_label < label_tick)
9087 || (rsp->last_set_label == label_tick
9088 && DF_INSN_LUID (rsp->last_set) < subst_low_luid)
9089 || (REGNO (x) >= FIRST_PSEUDO_REGISTER
9090 && REG_N_SETS (REGNO (x)) == 1
9092 (DF_LR_IN (ENTRY_BLOCK_PTR->next_bb), REGNO (x)))))
9094 *result = rsp->last_set_sign_bit_copies;
9098 tem = get_last_value (x);
9102 if (nonzero_sign_valid && rsp->sign_bit_copies != 0
9103 && GET_MODE_BITSIZE (GET_MODE (x)) == GET_MODE_BITSIZE (mode))
9104 *result = rsp->sign_bit_copies;
9109 /* Return the number of "extended" bits there are in X, when interpreted
9110 as a quantity in MODE whose signedness is indicated by UNSIGNEDP. For
9111 unsigned quantities, this is the number of high-order zero bits.
9112 For signed quantities, this is the number of copies of the sign bit
9113 minus 1. In both case, this function returns the number of "spare"
9114 bits. For example, if two quantities for which this function returns
9115 at least 1 are added, the addition is known not to overflow.
9117 This function will always return 0 unless called during combine, which
9118 implies that it must be called from a define_split. */
9121 extended_count (const_rtx x, enum machine_mode mode, int unsignedp)
9123 if (nonzero_sign_valid == 0)
9127 ? (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
9128 ? (unsigned int) (GET_MODE_BITSIZE (mode) - 1
9129 - floor_log2 (nonzero_bits (x, mode)))
9131 : num_sign_bit_copies (x, mode) - 1);
9134 /* This function is called from `simplify_shift_const' to merge two
9135 outer operations. Specifically, we have already found that we need
9136 to perform operation *POP0 with constant *PCONST0 at the outermost
9137 position. We would now like to also perform OP1 with constant CONST1
9138 (with *POP0 being done last).
9140 Return 1 if we can do the operation and update *POP0 and *PCONST0 with
9141 the resulting operation. *PCOMP_P is set to 1 if we would need to
9142 complement the innermost operand, otherwise it is unchanged.
9144 MODE is the mode in which the operation will be done. No bits outside
9145 the width of this mode matter. It is assumed that the width of this mode
9146 is smaller than or equal to HOST_BITS_PER_WIDE_INT.
9148 If *POP0 or OP1 are UNKNOWN, it means no operation is required. Only NEG, PLUS,
9149 IOR, XOR, and AND are supported. We may set *POP0 to SET if the proper
9150 result is simply *PCONST0.
9152 If the resulting operation cannot be expressed as one operation, we
9153 return 0 and do not change *POP0, *PCONST0, and *PCOMP_P. */
9156 merge_outer_ops (enum rtx_code *pop0, HOST_WIDE_INT *pconst0, enum rtx_code op1, HOST_WIDE_INT const1, enum machine_mode mode, int *pcomp_p)
9158 enum rtx_code op0 = *pop0;
9159 HOST_WIDE_INT const0 = *pconst0;
9161 const0 &= GET_MODE_MASK (mode);
9162 const1 &= GET_MODE_MASK (mode);
9164 /* If OP0 is an AND, clear unimportant bits in CONST1. */
9168 /* If OP0 or OP1 is UNKNOWN, this is easy. Similarly if they are the same or
9171 if (op1 == UNKNOWN || op0 == SET)
9174 else if (op0 == UNKNOWN)
9175 op0 = op1, const0 = const1;
9177 else if (op0 == op1)
9201 /* Otherwise, if either is a PLUS or NEG, we can't do anything. */
9202 else if (op0 == PLUS || op1 == PLUS || op0 == NEG || op1 == NEG)
9205 /* If the two constants aren't the same, we can't do anything. The
9206 remaining six cases can all be done. */
9207 else if (const0 != const1)
9215 /* (a & b) | b == b */
9217 else /* op1 == XOR */
9218 /* (a ^ b) | b == a | b */
9224 /* (a & b) ^ b == (~a) & b */
9225 op0 = AND, *pcomp_p = 1;
9226 else /* op1 == IOR */
9227 /* (a | b) ^ b == a & ~b */
9228 op0 = AND, const0 = ~const0;
9233 /* (a | b) & b == b */
9235 else /* op1 == XOR */
9236 /* (a ^ b) & b) == (~a) & b */
9243 /* Check for NO-OP cases. */
9244 const0 &= GET_MODE_MASK (mode);
9246 && (op0 == IOR || op0 == XOR || op0 == PLUS))
9248 else if (const0 == 0 && op0 == AND)
9250 else if ((unsigned HOST_WIDE_INT) const0 == GET_MODE_MASK (mode)
9256 /* ??? Slightly redundant with the above mask, but not entirely.
9257 Moving this above means we'd have to sign-extend the mode mask
9258 for the final test. */
9259 if (op0 != UNKNOWN && op0 != NEG)
9260 *pconst0 = trunc_int_for_mode (const0, mode);
9265 /* A helper to simplify_shift_const_1 to determine the mode we can perform
9266 the shift in. The original shift operation CODE is performed on OP in
9267 ORIG_MODE. Return the wider mode MODE if we can perform the operation
9268 in that mode. Return ORIG_MODE otherwise. We can also assume that the
9269 result of the shift is subject to operation OUTER_CODE with operand
9272 static enum machine_mode
9273 try_widen_shift_mode (enum rtx_code code, rtx op, int count,
9274 enum machine_mode orig_mode, enum machine_mode mode,
9275 enum rtx_code outer_code, HOST_WIDE_INT outer_const)
9277 if (orig_mode == mode)
9279 gcc_assert (GET_MODE_BITSIZE (mode) > GET_MODE_BITSIZE (orig_mode));
9281 /* In general we can't perform in wider mode for right shift and rotate. */
9285 /* We can still widen if the bits brought in from the left are identical
9286 to the sign bit of ORIG_MODE. */
9287 if (num_sign_bit_copies (op, mode)
9288 > (unsigned) (GET_MODE_BITSIZE (mode)
9289 - GET_MODE_BITSIZE (orig_mode)))
9294 /* Similarly here but with zero bits. */
9295 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
9296 && (nonzero_bits (op, mode) & ~GET_MODE_MASK (orig_mode)) == 0)
9299 /* We can also widen if the bits brought in will be masked off. This
9300 operation is performed in ORIG_MODE. */
9301 if (outer_code == AND)
9303 int care_bits = low_bitmask_len (orig_mode, outer_const);
9306 && GET_MODE_BITSIZE (orig_mode) - care_bits >= count)
9322 /* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift.
9323 The result of the shift is RESULT_MODE. Return NULL_RTX if we cannot
9324 simplify it. Otherwise, return a simplified value.
9326 The shift is normally computed in the widest mode we find in VAROP, as
9327 long as it isn't a different number of words than RESULT_MODE. Exceptions
9328 are ASHIFTRT and ROTATE, which are always done in their original mode. */
9331 simplify_shift_const_1 (enum rtx_code code, enum machine_mode result_mode,
9332 rtx varop, int orig_count)
9334 enum rtx_code orig_code = code;
9335 rtx orig_varop = varop;
9337 enum machine_mode mode = result_mode;
9338 enum machine_mode shift_mode, tmode;
9339 unsigned int mode_words
9340 = (GET_MODE_SIZE (mode) + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD;
9341 /* We form (outer_op (code varop count) (outer_const)). */
9342 enum rtx_code outer_op = UNKNOWN;
9343 HOST_WIDE_INT outer_const = 0;
9344 int complement_p = 0;
9347 /* Make sure and truncate the "natural" shift on the way in. We don't
9348 want to do this inside the loop as it makes it more difficult to
9350 if (SHIFT_COUNT_TRUNCATED)
9351 orig_count &= GET_MODE_BITSIZE (mode) - 1;
9353 /* If we were given an invalid count, don't do anything except exactly
9354 what was requested. */
9356 if (orig_count < 0 || orig_count >= (int) GET_MODE_BITSIZE (mode))
9361 /* Unless one of the branches of the `if' in this loop does a `continue',
9362 we will `break' the loop after the `if'. */
9366 /* If we have an operand of (clobber (const_int 0)), fail. */
9367 if (GET_CODE (varop) == CLOBBER)
9370 /* Convert ROTATERT to ROTATE. */
9371 if (code == ROTATERT)
9373 unsigned int bitsize = GET_MODE_BITSIZE (result_mode);;
9375 if (VECTOR_MODE_P (result_mode))
9376 count = bitsize / GET_MODE_NUNITS (result_mode) - count;
9378 count = bitsize - count;
9381 shift_mode = try_widen_shift_mode (code, varop, count, result_mode,
9382 mode, outer_op, outer_const);
9384 /* Handle cases where the count is greater than the size of the mode
9385 minus 1. For ASHIFT, use the size minus one as the count (this can
9386 occur when simplifying (lshiftrt (ashiftrt ..))). For rotates,
9387 take the count modulo the size. For other shifts, the result is
9390 Since these shifts are being produced by the compiler by combining
9391 multiple operations, each of which are defined, we know what the
9392 result is supposed to be. */
9394 if (count > (GET_MODE_BITSIZE (shift_mode) - 1))
9396 if (code == ASHIFTRT)
9397 count = GET_MODE_BITSIZE (shift_mode) - 1;
9398 else if (code == ROTATE || code == ROTATERT)
9399 count %= GET_MODE_BITSIZE (shift_mode);
9402 /* We can't simply return zero because there may be an
9410 /* If we discovered we had to complement VAROP, leave. Making a NOT
9411 here would cause an infinite loop. */
9415 /* An arithmetic right shift of a quantity known to be -1 or 0
9417 if (code == ASHIFTRT
9418 && (num_sign_bit_copies (varop, shift_mode)
9419 == GET_MODE_BITSIZE (shift_mode)))
9425 /* If we are doing an arithmetic right shift and discarding all but
9426 the sign bit copies, this is equivalent to doing a shift by the
9427 bitsize minus one. Convert it into that shift because it will often
9428 allow other simplifications. */
9430 if (code == ASHIFTRT
9431 && (count + num_sign_bit_copies (varop, shift_mode)
9432 >= GET_MODE_BITSIZE (shift_mode)))
9433 count = GET_MODE_BITSIZE (shift_mode) - 1;
9435 /* We simplify the tests below and elsewhere by converting
9436 ASHIFTRT to LSHIFTRT if we know the sign bit is clear.
9437 `make_compound_operation' will convert it to an ASHIFTRT for
9438 those machines (such as VAX) that don't have an LSHIFTRT. */
9439 if (GET_MODE_BITSIZE (shift_mode) <= HOST_BITS_PER_WIDE_INT
9441 && ((nonzero_bits (varop, shift_mode)
9442 & ((HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (shift_mode) - 1)))
9446 if (((code == LSHIFTRT
9447 && GET_MODE_BITSIZE (shift_mode) <= HOST_BITS_PER_WIDE_INT
9448 && !(nonzero_bits (varop, shift_mode) >> count))
9450 && GET_MODE_BITSIZE (shift_mode) <= HOST_BITS_PER_WIDE_INT
9451 && !((nonzero_bits (varop, shift_mode) << count)
9452 & GET_MODE_MASK (shift_mode))))
9453 && !side_effects_p (varop))
9456 switch (GET_CODE (varop))
9462 new_rtx = expand_compound_operation (varop);
9463 if (new_rtx != varop)
9471 /* If we have (xshiftrt (mem ...) C) and C is MODE_WIDTH
9472 minus the width of a smaller mode, we can do this with a
9473 SIGN_EXTEND or ZERO_EXTEND from the narrower memory location. */
9474 if ((code == ASHIFTRT || code == LSHIFTRT)
9475 && ! mode_dependent_address_p (XEXP (varop, 0))
9476 && ! MEM_VOLATILE_P (varop)
9477 && (tmode = mode_for_size (GET_MODE_BITSIZE (mode) - count,
9478 MODE_INT, 1)) != BLKmode)
9480 new_rtx = adjust_address_nv (varop, tmode,
9481 BYTES_BIG_ENDIAN ? 0
9482 : count / BITS_PER_UNIT);
9484 varop = gen_rtx_fmt_e (code == ASHIFTRT ? SIGN_EXTEND
9485 : ZERO_EXTEND, mode, new_rtx);
9492 /* If VAROP is a SUBREG, strip it as long as the inner operand has
9493 the same number of words as what we've seen so far. Then store
9494 the widest mode in MODE. */
9495 if (subreg_lowpart_p (varop)
9496 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop)))
9497 > GET_MODE_SIZE (GET_MODE (varop)))
9498 && (unsigned int) ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop)))
9499 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
9502 varop = SUBREG_REG (varop);
9503 if (GET_MODE_SIZE (GET_MODE (varop)) > GET_MODE_SIZE (mode))
9504 mode = GET_MODE (varop);
9510 /* Some machines use MULT instead of ASHIFT because MULT
9511 is cheaper. But it is still better on those machines to
9512 merge two shifts into one. */
9513 if (CONST_INT_P (XEXP (varop, 1))
9514 && exact_log2 (INTVAL (XEXP (varop, 1))) >= 0)
9517 = simplify_gen_binary (ASHIFT, GET_MODE (varop),
9519 GEN_INT (exact_log2 (
9520 INTVAL (XEXP (varop, 1)))));
9526 /* Similar, for when divides are cheaper. */
9527 if (CONST_INT_P (XEXP (varop, 1))
9528 && exact_log2 (INTVAL (XEXP (varop, 1))) >= 0)
9531 = simplify_gen_binary (LSHIFTRT, GET_MODE (varop),
9533 GEN_INT (exact_log2 (
9534 INTVAL (XEXP (varop, 1)))));
9540 /* If we are extracting just the sign bit of an arithmetic
9541 right shift, that shift is not needed. However, the sign
9542 bit of a wider mode may be different from what would be
9543 interpreted as the sign bit in a narrower mode, so, if
9544 the result is narrower, don't discard the shift. */
9545 if (code == LSHIFTRT
9546 && count == (GET_MODE_BITSIZE (result_mode) - 1)
9547 && (GET_MODE_BITSIZE (result_mode)
9548 >= GET_MODE_BITSIZE (GET_MODE (varop))))
9550 varop = XEXP (varop, 0);
9554 /* ... fall through ... */
9559 /* Here we have two nested shifts. The result is usually the
9560 AND of a new shift with a mask. We compute the result below. */
9561 if (CONST_INT_P (XEXP (varop, 1))
9562 && INTVAL (XEXP (varop, 1)) >= 0
9563 && INTVAL (XEXP (varop, 1)) < GET_MODE_BITSIZE (GET_MODE (varop))
9564 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
9565 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
9566 && !VECTOR_MODE_P (result_mode))
9568 enum rtx_code first_code = GET_CODE (varop);
9569 unsigned int first_count = INTVAL (XEXP (varop, 1));
9570 unsigned HOST_WIDE_INT mask;
9573 /* We have one common special case. We can't do any merging if
9574 the inner code is an ASHIFTRT of a smaller mode. However, if
9575 we have (ashift:M1 (subreg:M1 (ashiftrt:M2 FOO C1) 0) C2)
9576 with C2 == GET_MODE_BITSIZE (M1) - GET_MODE_BITSIZE (M2),
9577 we can convert it to
9578 (ashiftrt:M1 (ashift:M1 (and:M1 (subreg:M1 FOO 0 C2) C3) C1).
9579 This simplifies certain SIGN_EXTEND operations. */
9580 if (code == ASHIFT && first_code == ASHIFTRT
9581 && count == (GET_MODE_BITSIZE (result_mode)
9582 - GET_MODE_BITSIZE (GET_MODE (varop))))
9584 /* C3 has the low-order C1 bits zero. */
9586 mask = (GET_MODE_MASK (mode)
9587 & ~(((HOST_WIDE_INT) 1 << first_count) - 1));
9589 varop = simplify_and_const_int (NULL_RTX, result_mode,
9590 XEXP (varop, 0), mask);
9591 varop = simplify_shift_const (NULL_RTX, ASHIFT, result_mode,
9593 count = first_count;
9598 /* If this was (ashiftrt (ashift foo C1) C2) and FOO has more
9599 than C1 high-order bits equal to the sign bit, we can convert
9600 this to either an ASHIFT or an ASHIFTRT depending on the
9603 We cannot do this if VAROP's mode is not SHIFT_MODE. */
9605 if (code == ASHIFTRT && first_code == ASHIFT
9606 && GET_MODE (varop) == shift_mode
9607 && (num_sign_bit_copies (XEXP (varop, 0), shift_mode)
9610 varop = XEXP (varop, 0);
9611 count -= first_count;
9621 /* There are some cases we can't do. If CODE is ASHIFTRT,
9622 we can only do this if FIRST_CODE is also ASHIFTRT.
9624 We can't do the case when CODE is ROTATE and FIRST_CODE is
9627 If the mode of this shift is not the mode of the outer shift,
9628 we can't do this if either shift is a right shift or ROTATE.
9630 Finally, we can't do any of these if the mode is too wide
9631 unless the codes are the same.
9633 Handle the case where the shift codes are the same
9636 if (code == first_code)
9638 if (GET_MODE (varop) != result_mode
9639 && (code == ASHIFTRT || code == LSHIFTRT
9643 count += first_count;
9644 varop = XEXP (varop, 0);
9648 if (code == ASHIFTRT
9649 || (code == ROTATE && first_code == ASHIFTRT)
9650 || GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT
9651 || (GET_MODE (varop) != result_mode
9652 && (first_code == ASHIFTRT || first_code == LSHIFTRT
9653 || first_code == ROTATE
9654 || code == ROTATE)))
9657 /* To compute the mask to apply after the shift, shift the
9658 nonzero bits of the inner shift the same way the
9659 outer shift will. */
9661 mask_rtx = GEN_INT (nonzero_bits (varop, GET_MODE (varop)));
9664 = simplify_const_binary_operation (code, result_mode, mask_rtx,
9667 /* Give up if we can't compute an outer operation to use. */
9669 || !CONST_INT_P (mask_rtx)
9670 || ! merge_outer_ops (&outer_op, &outer_const, AND,
9672 result_mode, &complement_p))
9675 /* If the shifts are in the same direction, we add the
9676 counts. Otherwise, we subtract them. */
9677 if ((code == ASHIFTRT || code == LSHIFTRT)
9678 == (first_code == ASHIFTRT || first_code == LSHIFTRT))
9679 count += first_count;
9681 count -= first_count;
9683 /* If COUNT is positive, the new shift is usually CODE,
9684 except for the two exceptions below, in which case it is
9685 FIRST_CODE. If the count is negative, FIRST_CODE should
9688 && ((first_code == ROTATE && code == ASHIFT)
9689 || (first_code == ASHIFTRT && code == LSHIFTRT)))
9692 code = first_code, count = -count;
9694 varop = XEXP (varop, 0);
9698 /* If we have (A << B << C) for any shift, we can convert this to
9699 (A << C << B). This wins if A is a constant. Only try this if
9700 B is not a constant. */
9702 else if (GET_CODE (varop) == code
9703 && CONST_INT_P (XEXP (varop, 0))
9704 && !CONST_INT_P (XEXP (varop, 1)))
9706 rtx new_rtx = simplify_const_binary_operation (code, mode,
9709 varop = gen_rtx_fmt_ee (code, mode, new_rtx, XEXP (varop, 1));
9716 if (VECTOR_MODE_P (mode))
9719 /* Make this fit the case below. */
9720 varop = gen_rtx_XOR (mode, XEXP (varop, 0),
9721 GEN_INT (GET_MODE_MASK (mode)));
9727 /* If we have (xshiftrt (ior (plus X (const_int -1)) X) C)
9728 with C the size of VAROP - 1 and the shift is logical if
9729 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
9730 we have an (le X 0) operation. If we have an arithmetic shift
9731 and STORE_FLAG_VALUE is 1 or we have a logical shift with
9732 STORE_FLAG_VALUE of -1, we have a (neg (le X 0)) operation. */
9734 if (GET_CODE (varop) == IOR && GET_CODE (XEXP (varop, 0)) == PLUS
9735 && XEXP (XEXP (varop, 0), 1) == constm1_rtx
9736 && (STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
9737 && (code == LSHIFTRT || code == ASHIFTRT)
9738 && count == (GET_MODE_BITSIZE (GET_MODE (varop)) - 1)
9739 && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
9742 varop = gen_rtx_LE (GET_MODE (varop), XEXP (varop, 1),
9745 if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
9746 varop = gen_rtx_NEG (GET_MODE (varop), varop);
9751 /* If we have (shift (logical)), move the logical to the outside
9752 to allow it to possibly combine with another logical and the
9753 shift to combine with another shift. This also canonicalizes to
9754 what a ZERO_EXTRACT looks like. Also, some machines have
9755 (and (shift)) insns. */
9757 if (CONST_INT_P (XEXP (varop, 1))
9758 /* We can't do this if we have (ashiftrt (xor)) and the
9759 constant has its sign bit set in shift_mode. */
9760 && !(code == ASHIFTRT && GET_CODE (varop) == XOR
9761 && 0 > trunc_int_for_mode (INTVAL (XEXP (varop, 1)),
9763 && (new_rtx = simplify_const_binary_operation (code, result_mode,
9765 GEN_INT (count))) != 0
9766 && CONST_INT_P (new_rtx)
9767 && merge_outer_ops (&outer_op, &outer_const, GET_CODE (varop),
9768 INTVAL (new_rtx), result_mode, &complement_p))
9770 varop = XEXP (varop, 0);
9774 /* If we can't do that, try to simplify the shift in each arm of the
9775 logical expression, make a new logical expression, and apply
9776 the inverse distributive law. This also can't be done
9777 for some (ashiftrt (xor)). */
9778 if (CONST_INT_P (XEXP (varop, 1))
9779 && !(code == ASHIFTRT && GET_CODE (varop) == XOR
9780 && 0 > trunc_int_for_mode (INTVAL (XEXP (varop, 1)),
9783 rtx lhs = simplify_shift_const (NULL_RTX, code, shift_mode,
9784 XEXP (varop, 0), count);
9785 rtx rhs = simplify_shift_const (NULL_RTX, code, shift_mode,
9786 XEXP (varop, 1), count);
9788 varop = simplify_gen_binary (GET_CODE (varop), shift_mode,
9790 varop = apply_distributive_law (varop);
9798 /* Convert (lshiftrt (eq FOO 0) C) to (xor FOO 1) if STORE_FLAG_VALUE
9799 says that the sign bit can be tested, FOO has mode MODE, C is
9800 GET_MODE_BITSIZE (MODE) - 1, and FOO has only its low-order bit
9801 that may be nonzero. */
9802 if (code == LSHIFTRT
9803 && XEXP (varop, 1) == const0_rtx
9804 && GET_MODE (XEXP (varop, 0)) == result_mode
9805 && count == (GET_MODE_BITSIZE (result_mode) - 1)
9806 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
9807 && STORE_FLAG_VALUE == -1
9808 && nonzero_bits (XEXP (varop, 0), result_mode) == 1
9809 && merge_outer_ops (&outer_op, &outer_const, XOR,
9810 (HOST_WIDE_INT) 1, result_mode,
9813 varop = XEXP (varop, 0);
9820 /* (lshiftrt (neg A) C) where A is either 0 or 1 and C is one less
9821 than the number of bits in the mode is equivalent to A. */
9822 if (code == LSHIFTRT
9823 && count == (GET_MODE_BITSIZE (result_mode) - 1)
9824 && nonzero_bits (XEXP (varop, 0), result_mode) == 1)
9826 varop = XEXP (varop, 0);
9831 /* NEG commutes with ASHIFT since it is multiplication. Move the
9832 NEG outside to allow shifts to combine. */
9834 && merge_outer_ops (&outer_op, &outer_const, NEG,
9835 (HOST_WIDE_INT) 0, result_mode,
9838 varop = XEXP (varop, 0);
9844 /* (lshiftrt (plus A -1) C) where A is either 0 or 1 and C
9845 is one less than the number of bits in the mode is
9846 equivalent to (xor A 1). */
9847 if (code == LSHIFTRT
9848 && count == (GET_MODE_BITSIZE (result_mode) - 1)
9849 && XEXP (varop, 1) == constm1_rtx
9850 && nonzero_bits (XEXP (varop, 0), result_mode) == 1
9851 && merge_outer_ops (&outer_op, &outer_const, XOR,
9852 (HOST_WIDE_INT) 1, result_mode,
9856 varop = XEXP (varop, 0);
9860 /* If we have (xshiftrt (plus FOO BAR) C), and the only bits
9861 that might be nonzero in BAR are those being shifted out and those
9862 bits are known zero in FOO, we can replace the PLUS with FOO.
9863 Similarly in the other operand order. This code occurs when
9864 we are computing the size of a variable-size array. */
9866 if ((code == ASHIFTRT || code == LSHIFTRT)
9867 && count < HOST_BITS_PER_WIDE_INT
9868 && nonzero_bits (XEXP (varop, 1), result_mode) >> count == 0
9869 && (nonzero_bits (XEXP (varop, 1), result_mode)
9870 & nonzero_bits (XEXP (varop, 0), result_mode)) == 0)
9872 varop = XEXP (varop, 0);
9875 else if ((code == ASHIFTRT || code == LSHIFTRT)
9876 && count < HOST_BITS_PER_WIDE_INT
9877 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
9878 && 0 == (nonzero_bits (XEXP (varop, 0), result_mode)
9880 && 0 == (nonzero_bits (XEXP (varop, 0), result_mode)
9881 & nonzero_bits (XEXP (varop, 1),
9884 varop = XEXP (varop, 1);
9888 /* (ashift (plus foo C) N) is (plus (ashift foo N) C'). */
9890 && CONST_INT_P (XEXP (varop, 1))
9891 && (new_rtx = simplify_const_binary_operation (ASHIFT, result_mode,
9893 GEN_INT (count))) != 0
9894 && CONST_INT_P (new_rtx)
9895 && merge_outer_ops (&outer_op, &outer_const, PLUS,
9896 INTVAL (new_rtx), result_mode, &complement_p))
9898 varop = XEXP (varop, 0);
9902 /* Check for 'PLUS signbit', which is the canonical form of 'XOR
9903 signbit', and attempt to change the PLUS to an XOR and move it to
9904 the outer operation as is done above in the AND/IOR/XOR case
9905 leg for shift(logical). See details in logical handling above
9906 for reasoning in doing so. */
9907 if (code == LSHIFTRT
9908 && CONST_INT_P (XEXP (varop, 1))
9909 && mode_signbit_p (result_mode, XEXP (varop, 1))
9910 && (new_rtx = simplify_const_binary_operation (code, result_mode,
9912 GEN_INT (count))) != 0
9913 && CONST_INT_P (new_rtx)
9914 && merge_outer_ops (&outer_op, &outer_const, XOR,
9915 INTVAL (new_rtx), result_mode, &complement_p))
9917 varop = XEXP (varop, 0);
9924 /* If we have (xshiftrt (minus (ashiftrt X C)) X) C)
9925 with C the size of VAROP - 1 and the shift is logical if
9926 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
9927 we have a (gt X 0) operation. If the shift is arithmetic with
9928 STORE_FLAG_VALUE of 1 or logical with STORE_FLAG_VALUE == -1,
9929 we have a (neg (gt X 0)) operation. */
9931 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
9932 && GET_CODE (XEXP (varop, 0)) == ASHIFTRT
9933 && count == (GET_MODE_BITSIZE (GET_MODE (varop)) - 1)
9934 && (code == LSHIFTRT || code == ASHIFTRT)
9935 && CONST_INT_P (XEXP (XEXP (varop, 0), 1))
9936 && INTVAL (XEXP (XEXP (varop, 0), 1)) == count
9937 && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
9940 varop = gen_rtx_GT (GET_MODE (varop), XEXP (varop, 1),
9943 if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
9944 varop = gen_rtx_NEG (GET_MODE (varop), varop);
9951 /* Change (lshiftrt (truncate (lshiftrt))) to (truncate (lshiftrt))
9952 if the truncate does not affect the value. */
9953 if (code == LSHIFTRT
9954 && GET_CODE (XEXP (varop, 0)) == LSHIFTRT
9955 && CONST_INT_P (XEXP (XEXP (varop, 0), 1))
9956 && (INTVAL (XEXP (XEXP (varop, 0), 1))
9957 >= (GET_MODE_BITSIZE (GET_MODE (XEXP (varop, 0)))
9958 - GET_MODE_BITSIZE (GET_MODE (varop)))))
9960 rtx varop_inner = XEXP (varop, 0);
9963 = gen_rtx_LSHIFTRT (GET_MODE (varop_inner),
9964 XEXP (varop_inner, 0),
9966 (count + INTVAL (XEXP (varop_inner, 1))));
9967 varop = gen_rtx_TRUNCATE (GET_MODE (varop), varop_inner);
9980 shift_mode = try_widen_shift_mode (code, varop, count, result_mode, mode,
9981 outer_op, outer_const);
9983 /* We have now finished analyzing the shift. The result should be
9984 a shift of type CODE with SHIFT_MODE shifting VAROP COUNT places. If
9985 OUTER_OP is non-UNKNOWN, it is an operation that needs to be applied
9986 to the result of the shift. OUTER_CONST is the relevant constant,
9987 but we must turn off all bits turned off in the shift. */
9989 if (outer_op == UNKNOWN
9990 && orig_code == code && orig_count == count
9991 && varop == orig_varop
9992 && shift_mode == GET_MODE (varop))
9995 /* Make a SUBREG if necessary. If we can't make it, fail. */
9996 varop = gen_lowpart (shift_mode, varop);
9997 if (varop == NULL_RTX || GET_CODE (varop) == CLOBBER)
10000 /* If we have an outer operation and we just made a shift, it is
10001 possible that we could have simplified the shift were it not
10002 for the outer operation. So try to do the simplification
10005 if (outer_op != UNKNOWN)
10006 x = simplify_shift_const_1 (code, shift_mode, varop, count);
10011 x = simplify_gen_binary (code, shift_mode, varop, GEN_INT (count));
10013 /* If we were doing an LSHIFTRT in a wider mode than it was originally,
10014 turn off all the bits that the shift would have turned off. */
10015 if (orig_code == LSHIFTRT && result_mode != shift_mode)
10016 x = simplify_and_const_int (NULL_RTX, shift_mode, x,
10017 GET_MODE_MASK (result_mode) >> orig_count);
10019 /* Do the remainder of the processing in RESULT_MODE. */
10020 x = gen_lowpart_or_truncate (result_mode, x);
10022 /* If COMPLEMENT_P is set, we have to complement X before doing the outer
10025 x = simplify_gen_unary (NOT, result_mode, x, result_mode);
10027 if (outer_op != UNKNOWN)
10029 if (GET_RTX_CLASS (outer_op) != RTX_UNARY
10030 && GET_MODE_BITSIZE (result_mode) < HOST_BITS_PER_WIDE_INT)
10031 outer_const = trunc_int_for_mode (outer_const, result_mode);
10033 if (outer_op == AND)
10034 x = simplify_and_const_int (NULL_RTX, result_mode, x, outer_const);
10035 else if (outer_op == SET)
10037 /* This means that we have determined that the result is
10038 equivalent to a constant. This should be rare. */
10039 if (!side_effects_p (x))
10040 x = GEN_INT (outer_const);
10042 else if (GET_RTX_CLASS (outer_op) == RTX_UNARY)
10043 x = simplify_gen_unary (outer_op, result_mode, x, result_mode);
10045 x = simplify_gen_binary (outer_op, result_mode, x,
10046 GEN_INT (outer_const));
10052 /* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift.
10053 The result of the shift is RESULT_MODE. If we cannot simplify it,
10054 return X or, if it is NULL, synthesize the expression with
10055 simplify_gen_binary. Otherwise, return a simplified value.
10057 The shift is normally computed in the widest mode we find in VAROP, as
10058 long as it isn't a different number of words than RESULT_MODE. Exceptions
10059 are ASHIFTRT and ROTATE, which are always done in their original mode. */
10062 simplify_shift_const (rtx x, enum rtx_code code, enum machine_mode result_mode,
10063 rtx varop, int count)
10065 rtx tem = simplify_shift_const_1 (code, result_mode, varop, count);
10070 x = simplify_gen_binary (code, GET_MODE (varop), varop, GEN_INT (count));
10071 if (GET_MODE (x) != result_mode)
10072 x = gen_lowpart (result_mode, x);
10077 /* Like recog, but we receive the address of a pointer to a new pattern.
10078 We try to match the rtx that the pointer points to.
10079 If that fails, we may try to modify or replace the pattern,
10080 storing the replacement into the same pointer object.
10082 Modifications include deletion or addition of CLOBBERs.
10084 PNOTES is a pointer to a location where any REG_UNUSED notes added for
10085 the CLOBBERs are placed.
10087 The value is the final insn code from the pattern ultimately matched,
10091 recog_for_combine (rtx *pnewpat, rtx insn, rtx *pnotes)
10093 rtx pat = *pnewpat;
10094 int insn_code_number;
10095 int num_clobbers_to_add = 0;
10098 rtx old_notes, old_pat;
10100 /* If PAT is a PARALLEL, check to see if it contains the CLOBBER
10101 we use to indicate that something didn't match. If we find such a
10102 thing, force rejection. */
10103 if (GET_CODE (pat) == PARALLEL)
10104 for (i = XVECLEN (pat, 0) - 1; i >= 0; i--)
10105 if (GET_CODE (XVECEXP (pat, 0, i)) == CLOBBER
10106 && XEXP (XVECEXP (pat, 0, i), 0) == const0_rtx)
10109 old_pat = PATTERN (insn);
10110 old_notes = REG_NOTES (insn);
10111 PATTERN (insn) = pat;
10112 REG_NOTES (insn) = 0;
10114 insn_code_number = recog (pat, insn, &num_clobbers_to_add);
10115 if (dump_file && (dump_flags & TDF_DETAILS))
10117 if (insn_code_number < 0)
10118 fputs ("Failed to match this instruction:\n", dump_file);
10120 fputs ("Successfully matched this instruction:\n", dump_file);
10121 print_rtl_single (dump_file, pat);
10124 /* If it isn't, there is the possibility that we previously had an insn
10125 that clobbered some register as a side effect, but the combined
10126 insn doesn't need to do that. So try once more without the clobbers
10127 unless this represents an ASM insn. */
10129 if (insn_code_number < 0 && ! check_asm_operands (pat)
10130 && GET_CODE (pat) == PARALLEL)
10134 for (pos = 0, i = 0; i < XVECLEN (pat, 0); i++)
10135 if (GET_CODE (XVECEXP (pat, 0, i)) != CLOBBER)
10138 SUBST (XVECEXP (pat, 0, pos), XVECEXP (pat, 0, i));
10142 SUBST_INT (XVECLEN (pat, 0), pos);
10145 pat = XVECEXP (pat, 0, 0);
10147 PATTERN (insn) = pat;
10148 insn_code_number = recog (pat, insn, &num_clobbers_to_add);
10149 if (dump_file && (dump_flags & TDF_DETAILS))
10151 if (insn_code_number < 0)
10152 fputs ("Failed to match this instruction:\n", dump_file);
10154 fputs ("Successfully matched this instruction:\n", dump_file);
10155 print_rtl_single (dump_file, pat);
10158 PATTERN (insn) = old_pat;
10159 REG_NOTES (insn) = old_notes;
10161 /* Recognize all noop sets, these will be killed by followup pass. */
10162 if (insn_code_number < 0 && GET_CODE (pat) == SET && set_noop_p (pat))
10163 insn_code_number = NOOP_MOVE_INSN_CODE, num_clobbers_to_add = 0;
10165 /* If we had any clobbers to add, make a new pattern than contains
10166 them. Then check to make sure that all of them are dead. */
10167 if (num_clobbers_to_add)
10169 rtx newpat = gen_rtx_PARALLEL (VOIDmode,
10170 rtvec_alloc (GET_CODE (pat) == PARALLEL
10171 ? (XVECLEN (pat, 0)
10172 + num_clobbers_to_add)
10173 : num_clobbers_to_add + 1));
10175 if (GET_CODE (pat) == PARALLEL)
10176 for (i = 0; i < XVECLEN (pat, 0); i++)
10177 XVECEXP (newpat, 0, i) = XVECEXP (pat, 0, i);
10179 XVECEXP (newpat, 0, 0) = pat;
10181 add_clobbers (newpat, insn_code_number);
10183 for (i = XVECLEN (newpat, 0) - num_clobbers_to_add;
10184 i < XVECLEN (newpat, 0); i++)
10186 if (REG_P (XEXP (XVECEXP (newpat, 0, i), 0))
10187 && ! reg_dead_at_p (XEXP (XVECEXP (newpat, 0, i), 0), insn))
10189 if (GET_CODE (XEXP (XVECEXP (newpat, 0, i), 0)) != SCRATCH)
10191 gcc_assert (REG_P (XEXP (XVECEXP (newpat, 0, i), 0)));
10192 notes = alloc_reg_note (REG_UNUSED,
10193 XEXP (XVECEXP (newpat, 0, i), 0), notes);
10202 return insn_code_number;
10205 /* Like gen_lowpart_general but for use by combine. In combine it
10206 is not possible to create any new pseudoregs. However, it is
10207 safe to create invalid memory addresses, because combine will
10208 try to recognize them and all they will do is make the combine
10211 If for some reason this cannot do its job, an rtx
10212 (clobber (const_int 0)) is returned.
10213 An insn containing that will not be recognized. */
10216 gen_lowpart_for_combine (enum machine_mode omode, rtx x)
10218 enum machine_mode imode = GET_MODE (x);
10219 unsigned int osize = GET_MODE_SIZE (omode);
10220 unsigned int isize = GET_MODE_SIZE (imode);
10223 if (omode == imode)
10226 /* Return identity if this is a CONST or symbolic reference. */
10228 && (GET_CODE (x) == CONST
10229 || GET_CODE (x) == SYMBOL_REF
10230 || GET_CODE (x) == LABEL_REF))
10233 /* We can only support MODE being wider than a word if X is a
10234 constant integer or has a mode the same size. */
10235 if (GET_MODE_SIZE (omode) > UNITS_PER_WORD
10236 && ! ((imode == VOIDmode
10237 && (CONST_INT_P (x)
10238 || GET_CODE (x) == CONST_DOUBLE))
10239 || isize == osize))
10242 /* X might be a paradoxical (subreg (mem)). In that case, gen_lowpart
10243 won't know what to do. So we will strip off the SUBREG here and
10244 process normally. */
10245 if (GET_CODE (x) == SUBREG && MEM_P (SUBREG_REG (x)))
10247 x = SUBREG_REG (x);
10249 /* For use in case we fall down into the address adjustments
10250 further below, we need to adjust the known mode and size of
10251 x; imode and isize, since we just adjusted x. */
10252 imode = GET_MODE (x);
10254 if (imode == omode)
10257 isize = GET_MODE_SIZE (imode);
10260 result = gen_lowpart_common (omode, x);
10269 /* Refuse to work on a volatile memory ref or one with a mode-dependent
10271 if (MEM_VOLATILE_P (x) || mode_dependent_address_p (XEXP (x, 0)))
10274 /* If we want to refer to something bigger than the original memref,
10275 generate a paradoxical subreg instead. That will force a reload
10276 of the original memref X. */
10278 return gen_rtx_SUBREG (omode, x, 0);
10280 if (WORDS_BIG_ENDIAN)
10281 offset = MAX (isize, UNITS_PER_WORD) - MAX (osize, UNITS_PER_WORD);
10283 /* Adjust the address so that the address-after-the-data is
10285 if (BYTES_BIG_ENDIAN)
10286 offset -= MIN (UNITS_PER_WORD, osize) - MIN (UNITS_PER_WORD, isize);
10288 return adjust_address_nv (x, omode, offset);
10291 /* If X is a comparison operator, rewrite it in a new mode. This
10292 probably won't match, but may allow further simplifications. */
10293 else if (COMPARISON_P (x))
10294 return gen_rtx_fmt_ee (GET_CODE (x), omode, XEXP (x, 0), XEXP (x, 1));
10296 /* If we couldn't simplify X any other way, just enclose it in a
10297 SUBREG. Normally, this SUBREG won't match, but some patterns may
10298 include an explicit SUBREG or we may simplify it further in combine. */
10304 offset = subreg_lowpart_offset (omode, imode);
10305 if (imode == VOIDmode)
10307 imode = int_mode_for_mode (omode);
10308 x = gen_lowpart_common (imode, x);
10312 res = simplify_gen_subreg (omode, x, imode, offset);
10318 return gen_rtx_CLOBBER (omode, const0_rtx);
10321 /* Simplify a comparison between *POP0 and *POP1 where CODE is the
10322 comparison code that will be tested.
10324 The result is a possibly different comparison code to use. *POP0 and
10325 *POP1 may be updated.
10327 It is possible that we might detect that a comparison is either always
10328 true or always false. However, we do not perform general constant
10329 folding in combine, so this knowledge isn't useful. Such tautologies
10330 should have been detected earlier. Hence we ignore all such cases. */
10332 static enum rtx_code
10333 simplify_comparison (enum rtx_code code, rtx *pop0, rtx *pop1)
10339 enum machine_mode mode, tmode;
10341 /* Try a few ways of applying the same transformation to both operands. */
10344 #ifndef WORD_REGISTER_OPERATIONS
10345 /* The test below this one won't handle SIGN_EXTENDs on these machines,
10346 so check specially. */
10347 if (code != GTU && code != GEU && code != LTU && code != LEU
10348 && GET_CODE (op0) == ASHIFTRT && GET_CODE (op1) == ASHIFTRT
10349 && GET_CODE (XEXP (op0, 0)) == ASHIFT
10350 && GET_CODE (XEXP (op1, 0)) == ASHIFT
10351 && GET_CODE (XEXP (XEXP (op0, 0), 0)) == SUBREG
10352 && GET_CODE (XEXP (XEXP (op1, 0), 0)) == SUBREG
10353 && (GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0)))
10354 == GET_MODE (SUBREG_REG (XEXP (XEXP (op1, 0), 0))))
10355 && CONST_INT_P (XEXP (op0, 1))
10356 && XEXP (op0, 1) == XEXP (op1, 1)
10357 && XEXP (op0, 1) == XEXP (XEXP (op0, 0), 1)
10358 && XEXP (op0, 1) == XEXP (XEXP (op1, 0), 1)
10359 && (INTVAL (XEXP (op0, 1))
10360 == (GET_MODE_BITSIZE (GET_MODE (op0))
10361 - (GET_MODE_BITSIZE
10362 (GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0))))))))
10364 op0 = SUBREG_REG (XEXP (XEXP (op0, 0), 0));
10365 op1 = SUBREG_REG (XEXP (XEXP (op1, 0), 0));
10369 /* If both operands are the same constant shift, see if we can ignore the
10370 shift. We can if the shift is a rotate or if the bits shifted out of
10371 this shift are known to be zero for both inputs and if the type of
10372 comparison is compatible with the shift. */
10373 if (GET_CODE (op0) == GET_CODE (op1)
10374 && GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
10375 && ((GET_CODE (op0) == ROTATE && (code == NE || code == EQ))
10376 || ((GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFT)
10377 && (code != GT && code != LT && code != GE && code != LE))
10378 || (GET_CODE (op0) == ASHIFTRT
10379 && (code != GTU && code != LTU
10380 && code != GEU && code != LEU)))
10381 && CONST_INT_P (XEXP (op0, 1))
10382 && INTVAL (XEXP (op0, 1)) >= 0
10383 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT
10384 && XEXP (op0, 1) == XEXP (op1, 1))
10386 enum machine_mode mode = GET_MODE (op0);
10387 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
10388 int shift_count = INTVAL (XEXP (op0, 1));
10390 if (GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFTRT)
10391 mask &= (mask >> shift_count) << shift_count;
10392 else if (GET_CODE (op0) == ASHIFT)
10393 mask = (mask & (mask << shift_count)) >> shift_count;
10395 if ((nonzero_bits (XEXP (op0, 0), mode) & ~mask) == 0
10396 && (nonzero_bits (XEXP (op1, 0), mode) & ~mask) == 0)
10397 op0 = XEXP (op0, 0), op1 = XEXP (op1, 0);
10402 /* If both operands are AND's of a paradoxical SUBREG by constant, the
10403 SUBREGs are of the same mode, and, in both cases, the AND would
10404 be redundant if the comparison was done in the narrower mode,
10405 do the comparison in the narrower mode (e.g., we are AND'ing with 1
10406 and the operand's possibly nonzero bits are 0xffffff01; in that case
10407 if we only care about QImode, we don't need the AND). This case
10408 occurs if the output mode of an scc insn is not SImode and
10409 STORE_FLAG_VALUE == 1 (e.g., the 386).
10411 Similarly, check for a case where the AND's are ZERO_EXTEND
10412 operations from some narrower mode even though a SUBREG is not
10415 else if (GET_CODE (op0) == AND && GET_CODE (op1) == AND
10416 && CONST_INT_P (XEXP (op0, 1))
10417 && CONST_INT_P (XEXP (op1, 1)))
10419 rtx inner_op0 = XEXP (op0, 0);
10420 rtx inner_op1 = XEXP (op1, 0);
10421 HOST_WIDE_INT c0 = INTVAL (XEXP (op0, 1));
10422 HOST_WIDE_INT c1 = INTVAL (XEXP (op1, 1));
10425 if (GET_CODE (inner_op0) == SUBREG && GET_CODE (inner_op1) == SUBREG
10426 && (GET_MODE_SIZE (GET_MODE (inner_op0))
10427 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (inner_op0))))
10428 && (GET_MODE (SUBREG_REG (inner_op0))
10429 == GET_MODE (SUBREG_REG (inner_op1)))
10430 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (inner_op0)))
10431 <= HOST_BITS_PER_WIDE_INT)
10432 && (0 == ((~c0) & nonzero_bits (SUBREG_REG (inner_op0),
10433 GET_MODE (SUBREG_REG (inner_op0)))))
10434 && (0 == ((~c1) & nonzero_bits (SUBREG_REG (inner_op1),
10435 GET_MODE (SUBREG_REG (inner_op1))))))
10437 op0 = SUBREG_REG (inner_op0);
10438 op1 = SUBREG_REG (inner_op1);
10440 /* The resulting comparison is always unsigned since we masked
10441 off the original sign bit. */
10442 code = unsigned_condition (code);
10448 for (tmode = GET_CLASS_NARROWEST_MODE
10449 (GET_MODE_CLASS (GET_MODE (op0)));
10450 tmode != GET_MODE (op0); tmode = GET_MODE_WIDER_MODE (tmode))
10451 if ((unsigned HOST_WIDE_INT) c0 == GET_MODE_MASK (tmode))
10453 op0 = gen_lowpart (tmode, inner_op0);
10454 op1 = gen_lowpart (tmode, inner_op1);
10455 code = unsigned_condition (code);
10464 /* If both operands are NOT, we can strip off the outer operation
10465 and adjust the comparison code for swapped operands; similarly for
10466 NEG, except that this must be an equality comparison. */
10467 else if ((GET_CODE (op0) == NOT && GET_CODE (op1) == NOT)
10468 || (GET_CODE (op0) == NEG && GET_CODE (op1) == NEG
10469 && (code == EQ || code == NE)))
10470 op0 = XEXP (op0, 0), op1 = XEXP (op1, 0), code = swap_condition (code);
10476 /* If the first operand is a constant, swap the operands and adjust the
10477 comparison code appropriately, but don't do this if the second operand
10478 is already a constant integer. */
10479 if (swap_commutative_operands_p (op0, op1))
10481 tem = op0, op0 = op1, op1 = tem;
10482 code = swap_condition (code);
10485 /* We now enter a loop during which we will try to simplify the comparison.
10486 For the most part, we only are concerned with comparisons with zero,
10487 but some things may really be comparisons with zero but not start
10488 out looking that way. */
10490 while (CONST_INT_P (op1))
10492 enum machine_mode mode = GET_MODE (op0);
10493 unsigned int mode_width = GET_MODE_BITSIZE (mode);
10494 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
10495 int equality_comparison_p;
10496 int sign_bit_comparison_p;
10497 int unsigned_comparison_p;
10498 HOST_WIDE_INT const_op;
10500 /* We only want to handle integral modes. This catches VOIDmode,
10501 CCmode, and the floating-point modes. An exception is that we
10502 can handle VOIDmode if OP0 is a COMPARE or a comparison
10505 if (GET_MODE_CLASS (mode) != MODE_INT
10506 && ! (mode == VOIDmode
10507 && (GET_CODE (op0) == COMPARE || COMPARISON_P (op0))))
10510 /* Get the constant we are comparing against and turn off all bits
10511 not on in our mode. */
10512 const_op = INTVAL (op1);
10513 if (mode != VOIDmode)
10514 const_op = trunc_int_for_mode (const_op, mode);
10515 op1 = GEN_INT (const_op);
10517 /* If we are comparing against a constant power of two and the value
10518 being compared can only have that single bit nonzero (e.g., it was
10519 `and'ed with that bit), we can replace this with a comparison
10522 && (code == EQ || code == NE || code == GE || code == GEU
10523 || code == LT || code == LTU)
10524 && mode_width <= HOST_BITS_PER_WIDE_INT
10525 && exact_log2 (const_op) >= 0
10526 && nonzero_bits (op0, mode) == (unsigned HOST_WIDE_INT) const_op)
10528 code = (code == EQ || code == GE || code == GEU ? NE : EQ);
10529 op1 = const0_rtx, const_op = 0;
10532 /* Similarly, if we are comparing a value known to be either -1 or
10533 0 with -1, change it to the opposite comparison against zero. */
10536 && (code == EQ || code == NE || code == GT || code == LE
10537 || code == GEU || code == LTU)
10538 && num_sign_bit_copies (op0, mode) == mode_width)
10540 code = (code == EQ || code == LE || code == GEU ? NE : EQ);
10541 op1 = const0_rtx, const_op = 0;
10544 /* Do some canonicalizations based on the comparison code. We prefer
10545 comparisons against zero and then prefer equality comparisons.
10546 If we can reduce the size of a constant, we will do that too. */
10551 /* < C is equivalent to <= (C - 1) */
10555 op1 = GEN_INT (const_op);
10557 /* ... fall through to LE case below. */
10563 /* <= C is equivalent to < (C + 1); we do this for C < 0 */
10567 op1 = GEN_INT (const_op);
10571 /* If we are doing a <= 0 comparison on a value known to have
10572 a zero sign bit, we can replace this with == 0. */
10573 else if (const_op == 0
10574 && mode_width <= HOST_BITS_PER_WIDE_INT
10575 && (nonzero_bits (op0, mode)
10576 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)
10581 /* >= C is equivalent to > (C - 1). */
10585 op1 = GEN_INT (const_op);
10587 /* ... fall through to GT below. */
10593 /* > C is equivalent to >= (C + 1); we do this for C < 0. */
10597 op1 = GEN_INT (const_op);
10601 /* If we are doing a > 0 comparison on a value known to have
10602 a zero sign bit, we can replace this with != 0. */
10603 else if (const_op == 0
10604 && mode_width <= HOST_BITS_PER_WIDE_INT
10605 && (nonzero_bits (op0, mode)
10606 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)
10611 /* < C is equivalent to <= (C - 1). */
10615 op1 = GEN_INT (const_op);
10617 /* ... fall through ... */
10620 /* (unsigned) < 0x80000000 is equivalent to >= 0. */
10621 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
10622 && (const_op == (HOST_WIDE_INT) 1 << (mode_width - 1)))
10624 const_op = 0, op1 = const0_rtx;
10632 /* unsigned <= 0 is equivalent to == 0 */
10636 /* (unsigned) <= 0x7fffffff is equivalent to >= 0. */
10637 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
10638 && (const_op == ((HOST_WIDE_INT) 1 << (mode_width - 1)) - 1))
10640 const_op = 0, op1 = const0_rtx;
10646 /* >= C is equivalent to > (C - 1). */
10650 op1 = GEN_INT (const_op);
10652 /* ... fall through ... */
10655 /* (unsigned) >= 0x80000000 is equivalent to < 0. */
10656 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
10657 && (const_op == (HOST_WIDE_INT) 1 << (mode_width - 1)))
10659 const_op = 0, op1 = const0_rtx;
10667 /* unsigned > 0 is equivalent to != 0 */
10671 /* (unsigned) > 0x7fffffff is equivalent to < 0. */
10672 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
10673 && (const_op == ((HOST_WIDE_INT) 1 << (mode_width - 1)) - 1))
10675 const_op = 0, op1 = const0_rtx;
10684 /* Compute some predicates to simplify code below. */
10686 equality_comparison_p = (code == EQ || code == NE);
10687 sign_bit_comparison_p = ((code == LT || code == GE) && const_op == 0);
10688 unsigned_comparison_p = (code == LTU || code == LEU || code == GTU
10691 /* If this is a sign bit comparison and we can do arithmetic in
10692 MODE, say that we will only be needing the sign bit of OP0. */
10693 if (sign_bit_comparison_p
10694 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
10695 op0 = force_to_mode (op0, mode,
10697 << (GET_MODE_BITSIZE (mode) - 1)),
10700 /* Now try cases based on the opcode of OP0. If none of the cases
10701 does a "continue", we exit this loop immediately after the
10704 switch (GET_CODE (op0))
10707 /* If we are extracting a single bit from a variable position in
10708 a constant that has only a single bit set and are comparing it
10709 with zero, we can convert this into an equality comparison
10710 between the position and the location of the single bit. */
10711 /* Except we can't if SHIFT_COUNT_TRUNCATED is set, since we might
10712 have already reduced the shift count modulo the word size. */
10713 if (!SHIFT_COUNT_TRUNCATED
10714 && CONST_INT_P (XEXP (op0, 0))
10715 && XEXP (op0, 1) == const1_rtx
10716 && equality_comparison_p && const_op == 0
10717 && (i = exact_log2 (INTVAL (XEXP (op0, 0)))) >= 0)
10719 if (BITS_BIG_ENDIAN)
10721 enum machine_mode new_mode
10722 = mode_for_extraction (EP_extzv, 1);
10723 if (new_mode == MAX_MACHINE_MODE)
10724 i = BITS_PER_WORD - 1 - i;
10728 i = (GET_MODE_BITSIZE (mode) - 1 - i);
10732 op0 = XEXP (op0, 2);
10736 /* Result is nonzero iff shift count is equal to I. */
10737 code = reverse_condition (code);
10741 /* ... fall through ... */
10744 tem = expand_compound_operation (op0);
10753 /* If testing for equality, we can take the NOT of the constant. */
10754 if (equality_comparison_p
10755 && (tem = simplify_unary_operation (NOT, mode, op1, mode)) != 0)
10757 op0 = XEXP (op0, 0);
10762 /* If just looking at the sign bit, reverse the sense of the
10764 if (sign_bit_comparison_p)
10766 op0 = XEXP (op0, 0);
10767 code = (code == GE ? LT : GE);
10773 /* If testing for equality, we can take the NEG of the constant. */
10774 if (equality_comparison_p
10775 && (tem = simplify_unary_operation (NEG, mode, op1, mode)) != 0)
10777 op0 = XEXP (op0, 0);
10782 /* The remaining cases only apply to comparisons with zero. */
10786 /* When X is ABS or is known positive,
10787 (neg X) is < 0 if and only if X != 0. */
10789 if (sign_bit_comparison_p
10790 && (GET_CODE (XEXP (op0, 0)) == ABS
10791 || (mode_width <= HOST_BITS_PER_WIDE_INT
10792 && (nonzero_bits (XEXP (op0, 0), mode)
10793 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)))
10795 op0 = XEXP (op0, 0);
10796 code = (code == LT ? NE : EQ);
10800 /* If we have NEG of something whose two high-order bits are the
10801 same, we know that "(-a) < 0" is equivalent to "a > 0". */
10802 if (num_sign_bit_copies (op0, mode) >= 2)
10804 op0 = XEXP (op0, 0);
10805 code = swap_condition (code);
10811 /* If we are testing equality and our count is a constant, we
10812 can perform the inverse operation on our RHS. */
10813 if (equality_comparison_p && CONST_INT_P (XEXP (op0, 1))
10814 && (tem = simplify_binary_operation (ROTATERT, mode,
10815 op1, XEXP (op0, 1))) != 0)
10817 op0 = XEXP (op0, 0);
10822 /* If we are doing a < 0 or >= 0 comparison, it means we are testing
10823 a particular bit. Convert it to an AND of a constant of that
10824 bit. This will be converted into a ZERO_EXTRACT. */
10825 if (const_op == 0 && sign_bit_comparison_p
10826 && CONST_INT_P (XEXP (op0, 1))
10827 && mode_width <= HOST_BITS_PER_WIDE_INT)
10829 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
10832 - INTVAL (XEXP (op0, 1)))));
10833 code = (code == LT ? NE : EQ);
10837 /* Fall through. */
10840 /* ABS is ignorable inside an equality comparison with zero. */
10841 if (const_op == 0 && equality_comparison_p)
10843 op0 = XEXP (op0, 0);
10849 /* Can simplify (compare (zero/sign_extend FOO) CONST) to
10850 (compare FOO CONST) if CONST fits in FOO's mode and we
10851 are either testing inequality or have an unsigned
10852 comparison with ZERO_EXTEND or a signed comparison with
10853 SIGN_EXTEND. But don't do it if we don't have a compare
10854 insn of the given mode, since we'd have to revert it
10855 later on, and then we wouldn't know whether to sign- or
10857 mode = GET_MODE (XEXP (op0, 0));
10858 if (mode != VOIDmode && GET_MODE_CLASS (mode) == MODE_INT
10859 && ! unsigned_comparison_p
10860 && (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
10861 && ((unsigned HOST_WIDE_INT) const_op
10862 < (((unsigned HOST_WIDE_INT) 1
10863 << (GET_MODE_BITSIZE (mode) - 1))))
10864 && have_insn_for (COMPARE, mode))
10866 op0 = XEXP (op0, 0);
10872 /* Check for the case where we are comparing A - C1 with C2, that is
10874 (subreg:MODE (plus (A) (-C1))) op (C2)
10876 with C1 a constant, and try to lift the SUBREG, i.e. to do the
10877 comparison in the wider mode. One of the following two conditions
10878 must be true in order for this to be valid:
10880 1. The mode extension results in the same bit pattern being added
10881 on both sides and the comparison is equality or unsigned. As
10882 C2 has been truncated to fit in MODE, the pattern can only be
10885 2. The mode extension results in the sign bit being copied on
10888 The difficulty here is that we have predicates for A but not for
10889 (A - C1) so we need to check that C1 is within proper bounds so
10890 as to perturbate A as little as possible. */
10892 if (mode_width <= HOST_BITS_PER_WIDE_INT
10893 && subreg_lowpart_p (op0)
10894 && GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0))) > mode_width
10895 && GET_CODE (SUBREG_REG (op0)) == PLUS
10896 && CONST_INT_P (XEXP (SUBREG_REG (op0), 1)))
10898 enum machine_mode inner_mode = GET_MODE (SUBREG_REG (op0));
10899 rtx a = XEXP (SUBREG_REG (op0), 0);
10900 HOST_WIDE_INT c1 = -INTVAL (XEXP (SUBREG_REG (op0), 1));
10903 && (unsigned HOST_WIDE_INT) c1
10904 < (unsigned HOST_WIDE_INT) 1 << (mode_width - 1)
10905 && (equality_comparison_p || unsigned_comparison_p)
10906 /* (A - C1) zero-extends if it is positive and sign-extends
10907 if it is negative, C2 both zero- and sign-extends. */
10908 && ((0 == (nonzero_bits (a, inner_mode)
10909 & ~GET_MODE_MASK (mode))
10911 /* (A - C1) sign-extends if it is positive and 1-extends
10912 if it is negative, C2 both sign- and 1-extends. */
10913 || (num_sign_bit_copies (a, inner_mode)
10914 > (unsigned int) (GET_MODE_BITSIZE (inner_mode)
10917 || ((unsigned HOST_WIDE_INT) c1
10918 < (unsigned HOST_WIDE_INT) 1 << (mode_width - 2)
10919 /* (A - C1) always sign-extends, like C2. */
10920 && num_sign_bit_copies (a, inner_mode)
10921 > (unsigned int) (GET_MODE_BITSIZE (inner_mode)
10922 - (mode_width - 1))))
10924 op0 = SUBREG_REG (op0);
10929 /* If the inner mode is narrower and we are extracting the low part,
10930 we can treat the SUBREG as if it were a ZERO_EXTEND. */
10931 if (subreg_lowpart_p (op0)
10932 && GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0))) < mode_width)
10933 /* Fall through */ ;
10937 /* ... fall through ... */
10940 mode = GET_MODE (XEXP (op0, 0));
10941 if (mode != VOIDmode && GET_MODE_CLASS (mode) == MODE_INT
10942 && (unsigned_comparison_p || equality_comparison_p)
10943 && (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
10944 && ((unsigned HOST_WIDE_INT) const_op < GET_MODE_MASK (mode))
10945 && have_insn_for (COMPARE, mode))
10947 op0 = XEXP (op0, 0);
10953 /* (eq (plus X A) B) -> (eq X (minus B A)). We can only do
10954 this for equality comparisons due to pathological cases involving
10956 if (equality_comparison_p
10957 && 0 != (tem = simplify_binary_operation (MINUS, mode,
10958 op1, XEXP (op0, 1))))
10960 op0 = XEXP (op0, 0);
10965 /* (plus (abs X) (const_int -1)) is < 0 if and only if X == 0. */
10966 if (const_op == 0 && XEXP (op0, 1) == constm1_rtx
10967 && GET_CODE (XEXP (op0, 0)) == ABS && sign_bit_comparison_p)
10969 op0 = XEXP (XEXP (op0, 0), 0);
10970 code = (code == LT ? EQ : NE);
10976 /* We used to optimize signed comparisons against zero, but that
10977 was incorrect. Unsigned comparisons against zero (GTU, LEU)
10978 arrive here as equality comparisons, or (GEU, LTU) are
10979 optimized away. No need to special-case them. */
10981 /* (eq (minus A B) C) -> (eq A (plus B C)) or
10982 (eq B (minus A C)), whichever simplifies. We can only do
10983 this for equality comparisons due to pathological cases involving
10985 if (equality_comparison_p
10986 && 0 != (tem = simplify_binary_operation (PLUS, mode,
10987 XEXP (op0, 1), op1)))
10989 op0 = XEXP (op0, 0);
10994 if (equality_comparison_p
10995 && 0 != (tem = simplify_binary_operation (MINUS, mode,
10996 XEXP (op0, 0), op1)))
10998 op0 = XEXP (op0, 1);
11003 /* The sign bit of (minus (ashiftrt X C) X), where C is the number
11004 of bits in X minus 1, is one iff X > 0. */
11005 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == ASHIFTRT
11006 && CONST_INT_P (XEXP (XEXP (op0, 0), 1))
11007 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (XEXP (op0, 0), 1))
11009 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
11011 op0 = XEXP (op0, 1);
11012 code = (code == GE ? LE : GT);
11018 /* (eq (xor A B) C) -> (eq A (xor B C)). This is a simplification
11019 if C is zero or B is a constant. */
11020 if (equality_comparison_p
11021 && 0 != (tem = simplify_binary_operation (XOR, mode,
11022 XEXP (op0, 1), op1)))
11024 op0 = XEXP (op0, 0);
11031 case UNEQ: case LTGT:
11032 case LT: case LTU: case UNLT: case LE: case LEU: case UNLE:
11033 case GT: case GTU: case UNGT: case GE: case GEU: case UNGE:
11034 case UNORDERED: case ORDERED:
11035 /* We can't do anything if OP0 is a condition code value, rather
11036 than an actual data value. */
11038 || CC0_P (XEXP (op0, 0))
11039 || GET_MODE_CLASS (GET_MODE (XEXP (op0, 0))) == MODE_CC)
11042 /* Get the two operands being compared. */
11043 if (GET_CODE (XEXP (op0, 0)) == COMPARE)
11044 tem = XEXP (XEXP (op0, 0), 0), tem1 = XEXP (XEXP (op0, 0), 1);
11046 tem = XEXP (op0, 0), tem1 = XEXP (op0, 1);
11048 /* Check for the cases where we simply want the result of the
11049 earlier test or the opposite of that result. */
11050 if (code == NE || code == EQ
11051 || (GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
11052 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
11053 && (STORE_FLAG_VALUE
11054 & (((HOST_WIDE_INT) 1
11055 << (GET_MODE_BITSIZE (GET_MODE (op0)) - 1))))
11056 && (code == LT || code == GE)))
11058 enum rtx_code new_code;
11059 if (code == LT || code == NE)
11060 new_code = GET_CODE (op0);
11062 new_code = reversed_comparison_code (op0, NULL);
11064 if (new_code != UNKNOWN)
11075 /* The sign bit of (ior (plus X (const_int -1)) X) is nonzero
11077 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == PLUS
11078 && XEXP (XEXP (op0, 0), 1) == constm1_rtx
11079 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
11081 op0 = XEXP (op0, 1);
11082 code = (code == GE ? GT : LE);
11088 /* Convert (and (xshift 1 X) Y) to (and (lshiftrt Y X) 1). This
11089 will be converted to a ZERO_EXTRACT later. */
11090 if (const_op == 0 && equality_comparison_p
11091 && GET_CODE (XEXP (op0, 0)) == ASHIFT
11092 && XEXP (XEXP (op0, 0), 0) == const1_rtx)
11094 op0 = simplify_and_const_int
11095 (NULL_RTX, mode, gen_rtx_LSHIFTRT (mode,
11097 XEXP (XEXP (op0, 0), 1)),
11098 (HOST_WIDE_INT) 1);
11102 /* If we are comparing (and (lshiftrt X C1) C2) for equality with
11103 zero and X is a comparison and C1 and C2 describe only bits set
11104 in STORE_FLAG_VALUE, we can compare with X. */
11105 if (const_op == 0 && equality_comparison_p
11106 && mode_width <= HOST_BITS_PER_WIDE_INT
11107 && CONST_INT_P (XEXP (op0, 1))
11108 && GET_CODE (XEXP (op0, 0)) == LSHIFTRT
11109 && CONST_INT_P (XEXP (XEXP (op0, 0), 1))
11110 && INTVAL (XEXP (XEXP (op0, 0), 1)) >= 0
11111 && INTVAL (XEXP (XEXP (op0, 0), 1)) < HOST_BITS_PER_WIDE_INT)
11113 mask = ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
11114 << INTVAL (XEXP (XEXP (op0, 0), 1)));
11115 if ((~STORE_FLAG_VALUE & mask) == 0
11116 && (COMPARISON_P (XEXP (XEXP (op0, 0), 0))
11117 || ((tem = get_last_value (XEXP (XEXP (op0, 0), 0))) != 0
11118 && COMPARISON_P (tem))))
11120 op0 = XEXP (XEXP (op0, 0), 0);
11125 /* If we are doing an equality comparison of an AND of a bit equal
11126 to the sign bit, replace this with a LT or GE comparison of
11127 the underlying value. */
11128 if (equality_comparison_p
11130 && CONST_INT_P (XEXP (op0, 1))
11131 && mode_width <= HOST_BITS_PER_WIDE_INT
11132 && ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
11133 == (unsigned HOST_WIDE_INT) 1 << (mode_width - 1)))
11135 op0 = XEXP (op0, 0);
11136 code = (code == EQ ? GE : LT);
11140 /* If this AND operation is really a ZERO_EXTEND from a narrower
11141 mode, the constant fits within that mode, and this is either an
11142 equality or unsigned comparison, try to do this comparison in
11147 (ne:DI (and:DI (reg:DI 4) (const_int 0xffffffff)) (const_int 0))
11148 -> (ne:DI (reg:SI 4) (const_int 0))
11150 unless TRULY_NOOP_TRUNCATION allows it or the register is
11151 known to hold a value of the required mode the
11152 transformation is invalid. */
11153 if ((equality_comparison_p || unsigned_comparison_p)
11154 && CONST_INT_P (XEXP (op0, 1))
11155 && (i = exact_log2 ((INTVAL (XEXP (op0, 1))
11156 & GET_MODE_MASK (mode))
11158 && const_op >> i == 0
11159 && (tmode = mode_for_size (i, MODE_INT, 1)) != BLKmode
11160 && (TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (tmode),
11161 GET_MODE_BITSIZE (GET_MODE (op0)))
11162 || (REG_P (XEXP (op0, 0))
11163 && reg_truncated_to_mode (tmode, XEXP (op0, 0)))))
11165 op0 = gen_lowpart (tmode, XEXP (op0, 0));
11169 /* If this is (and:M1 (subreg:M2 X 0) (const_int C1)) where C1
11170 fits in both M1 and M2 and the SUBREG is either paradoxical
11171 or represents the low part, permute the SUBREG and the AND
11173 if (GET_CODE (XEXP (op0, 0)) == SUBREG)
11175 unsigned HOST_WIDE_INT c1;
11176 tmode = GET_MODE (SUBREG_REG (XEXP (op0, 0)));
11177 /* Require an integral mode, to avoid creating something like
11179 if (SCALAR_INT_MODE_P (tmode)
11180 /* It is unsafe to commute the AND into the SUBREG if the
11181 SUBREG is paradoxical and WORD_REGISTER_OPERATIONS is
11182 not defined. As originally written the upper bits
11183 have a defined value due to the AND operation.
11184 However, if we commute the AND inside the SUBREG then
11185 they no longer have defined values and the meaning of
11186 the code has been changed. */
11188 #ifdef WORD_REGISTER_OPERATIONS
11189 || (mode_width > GET_MODE_BITSIZE (tmode)
11190 && mode_width <= BITS_PER_WORD)
11192 || (mode_width <= GET_MODE_BITSIZE (tmode)
11193 && subreg_lowpart_p (XEXP (op0, 0))))
11194 && CONST_INT_P (XEXP (op0, 1))
11195 && mode_width <= HOST_BITS_PER_WIDE_INT
11196 && GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT
11197 && ((c1 = INTVAL (XEXP (op0, 1))) & ~mask) == 0
11198 && (c1 & ~GET_MODE_MASK (tmode)) == 0
11200 && c1 != GET_MODE_MASK (tmode))
11202 op0 = simplify_gen_binary (AND, tmode,
11203 SUBREG_REG (XEXP (op0, 0)),
11204 gen_int_mode (c1, tmode));
11205 op0 = gen_lowpart (mode, op0);
11210 /* Convert (ne (and (not X) 1) 0) to (eq (and X 1) 0). */
11211 if (const_op == 0 && equality_comparison_p
11212 && XEXP (op0, 1) == const1_rtx
11213 && GET_CODE (XEXP (op0, 0)) == NOT)
11215 op0 = simplify_and_const_int
11216 (NULL_RTX, mode, XEXP (XEXP (op0, 0), 0), (HOST_WIDE_INT) 1);
11217 code = (code == NE ? EQ : NE);
11221 /* Convert (ne (and (lshiftrt (not X)) 1) 0) to
11222 (eq (and (lshiftrt X) 1) 0).
11223 Also handle the case where (not X) is expressed using xor. */
11224 if (const_op == 0 && equality_comparison_p
11225 && XEXP (op0, 1) == const1_rtx
11226 && GET_CODE (XEXP (op0, 0)) == LSHIFTRT)
11228 rtx shift_op = XEXP (XEXP (op0, 0), 0);
11229 rtx shift_count = XEXP (XEXP (op0, 0), 1);
11231 if (GET_CODE (shift_op) == NOT
11232 || (GET_CODE (shift_op) == XOR
11233 && CONST_INT_P (XEXP (shift_op, 1))
11234 && CONST_INT_P (shift_count)
11235 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
11236 && (INTVAL (XEXP (shift_op, 1))
11237 == (HOST_WIDE_INT) 1 << INTVAL (shift_count))))
11239 op0 = simplify_and_const_int
11241 gen_rtx_LSHIFTRT (mode, XEXP (shift_op, 0), shift_count),
11242 (HOST_WIDE_INT) 1);
11243 code = (code == NE ? EQ : NE);
11250 /* If we have (compare (ashift FOO N) (const_int C)) and
11251 the high order N bits of FOO (N+1 if an inequality comparison)
11252 are known to be zero, we can do this by comparing FOO with C
11253 shifted right N bits so long as the low-order N bits of C are
11255 if (CONST_INT_P (XEXP (op0, 1))
11256 && INTVAL (XEXP (op0, 1)) >= 0
11257 && ((INTVAL (XEXP (op0, 1)) + ! equality_comparison_p)
11258 < HOST_BITS_PER_WIDE_INT)
11260 & (((HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1))) - 1)) == 0)
11261 && mode_width <= HOST_BITS_PER_WIDE_INT
11262 && (nonzero_bits (XEXP (op0, 0), mode)
11263 & ~(mask >> (INTVAL (XEXP (op0, 1))
11264 + ! equality_comparison_p))) == 0)
11266 /* We must perform a logical shift, not an arithmetic one,
11267 as we want the top N bits of C to be zero. */
11268 unsigned HOST_WIDE_INT temp = const_op & GET_MODE_MASK (mode);
11270 temp >>= INTVAL (XEXP (op0, 1));
11271 op1 = gen_int_mode (temp, mode);
11272 op0 = XEXP (op0, 0);
11276 /* If we are doing a sign bit comparison, it means we are testing
11277 a particular bit. Convert it to the appropriate AND. */
11278 if (sign_bit_comparison_p && CONST_INT_P (XEXP (op0, 1))
11279 && mode_width <= HOST_BITS_PER_WIDE_INT)
11281 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
11284 - INTVAL (XEXP (op0, 1)))));
11285 code = (code == LT ? NE : EQ);
11289 /* If this an equality comparison with zero and we are shifting
11290 the low bit to the sign bit, we can convert this to an AND of the
11292 if (const_op == 0 && equality_comparison_p
11293 && CONST_INT_P (XEXP (op0, 1))
11294 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (op0, 1))
11297 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
11298 (HOST_WIDE_INT) 1);
11304 /* If this is an equality comparison with zero, we can do this
11305 as a logical shift, which might be much simpler. */
11306 if (equality_comparison_p && const_op == 0
11307 && CONST_INT_P (XEXP (op0, 1)))
11309 op0 = simplify_shift_const (NULL_RTX, LSHIFTRT, mode,
11311 INTVAL (XEXP (op0, 1)));
11315 /* If OP0 is a sign extension and CODE is not an unsigned comparison,
11316 do the comparison in a narrower mode. */
11317 if (! unsigned_comparison_p
11318 && CONST_INT_P (XEXP (op0, 1))
11319 && GET_CODE (XEXP (op0, 0)) == ASHIFT
11320 && XEXP (op0, 1) == XEXP (XEXP (op0, 0), 1)
11321 && (tmode = mode_for_size (mode_width - INTVAL (XEXP (op0, 1)),
11322 MODE_INT, 1)) != BLKmode
11323 && (((unsigned HOST_WIDE_INT) const_op
11324 + (GET_MODE_MASK (tmode) >> 1) + 1)
11325 <= GET_MODE_MASK (tmode)))
11327 op0 = gen_lowpart (tmode, XEXP (XEXP (op0, 0), 0));
11331 /* Likewise if OP0 is a PLUS of a sign extension with a
11332 constant, which is usually represented with the PLUS
11333 between the shifts. */
11334 if (! unsigned_comparison_p
11335 && CONST_INT_P (XEXP (op0, 1))
11336 && GET_CODE (XEXP (op0, 0)) == PLUS
11337 && CONST_INT_P (XEXP (XEXP (op0, 0), 1))
11338 && GET_CODE (XEXP (XEXP (op0, 0), 0)) == ASHIFT
11339 && XEXP (op0, 1) == XEXP (XEXP (XEXP (op0, 0), 0), 1)
11340 && (tmode = mode_for_size (mode_width - INTVAL (XEXP (op0, 1)),
11341 MODE_INT, 1)) != BLKmode
11342 && (((unsigned HOST_WIDE_INT) const_op
11343 + (GET_MODE_MASK (tmode) >> 1) + 1)
11344 <= GET_MODE_MASK (tmode)))
11346 rtx inner = XEXP (XEXP (XEXP (op0, 0), 0), 0);
11347 rtx add_const = XEXP (XEXP (op0, 0), 1);
11348 rtx new_const = simplify_gen_binary (ASHIFTRT, GET_MODE (op0),
11349 add_const, XEXP (op0, 1));
11351 op0 = simplify_gen_binary (PLUS, tmode,
11352 gen_lowpart (tmode, inner),
11357 /* ... fall through ... */
11359 /* If we have (compare (xshiftrt FOO N) (const_int C)) and
11360 the low order N bits of FOO are known to be zero, we can do this
11361 by comparing FOO with C shifted left N bits so long as no
11362 overflow occurs. */
11363 if (CONST_INT_P (XEXP (op0, 1))
11364 && INTVAL (XEXP (op0, 1)) >= 0
11365 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT
11366 && mode_width <= HOST_BITS_PER_WIDE_INT
11367 && (nonzero_bits (XEXP (op0, 0), mode)
11368 & (((HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1))) - 1)) == 0
11369 && (((unsigned HOST_WIDE_INT) const_op
11370 + (GET_CODE (op0) != LSHIFTRT
11371 ? ((GET_MODE_MASK (mode) >> INTVAL (XEXP (op0, 1)) >> 1)
11374 <= GET_MODE_MASK (mode) >> INTVAL (XEXP (op0, 1))))
11376 /* If the shift was logical, then we must make the condition
11378 if (GET_CODE (op0) == LSHIFTRT)
11379 code = unsigned_condition (code);
11381 const_op <<= INTVAL (XEXP (op0, 1));
11382 op1 = GEN_INT (const_op);
11383 op0 = XEXP (op0, 0);
11387 /* If we are using this shift to extract just the sign bit, we
11388 can replace this with an LT or GE comparison. */
11390 && (equality_comparison_p || sign_bit_comparison_p)
11391 && CONST_INT_P (XEXP (op0, 1))
11392 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (op0, 1))
11395 op0 = XEXP (op0, 0);
11396 code = (code == NE || code == GT ? LT : GE);
11408 /* Now make any compound operations involved in this comparison. Then,
11409 check for an outmost SUBREG on OP0 that is not doing anything or is
11410 paradoxical. The latter transformation must only be performed when
11411 it is known that the "extra" bits will be the same in op0 and op1 or
11412 that they don't matter. There are three cases to consider:
11414 1. SUBREG_REG (op0) is a register. In this case the bits are don't
11415 care bits and we can assume they have any convenient value. So
11416 making the transformation is safe.
11418 2. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is not defined.
11419 In this case the upper bits of op0 are undefined. We should not make
11420 the simplification in that case as we do not know the contents of
11423 3. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is defined and not
11424 UNKNOWN. In that case we know those bits are zeros or ones. We must
11425 also be sure that they are the same as the upper bits of op1.
11427 We can never remove a SUBREG for a non-equality comparison because
11428 the sign bit is in a different place in the underlying object. */
11430 op0 = make_compound_operation (op0, op1 == const0_rtx ? COMPARE : SET);
11431 op1 = make_compound_operation (op1, SET);
11433 if (GET_CODE (op0) == SUBREG && subreg_lowpart_p (op0)
11434 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
11435 && GET_MODE_CLASS (GET_MODE (SUBREG_REG (op0))) == MODE_INT
11436 && (code == NE || code == EQ))
11438 if (GET_MODE_SIZE (GET_MODE (op0))
11439 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (op0))))
11441 /* For paradoxical subregs, allow case 1 as above. Case 3 isn't
11443 if (REG_P (SUBREG_REG (op0)))
11445 op0 = SUBREG_REG (op0);
11446 op1 = gen_lowpart (GET_MODE (op0), op1);
11449 else if ((GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0)))
11450 <= HOST_BITS_PER_WIDE_INT)
11451 && (nonzero_bits (SUBREG_REG (op0),
11452 GET_MODE (SUBREG_REG (op0)))
11453 & ~GET_MODE_MASK (GET_MODE (op0))) == 0)
11455 tem = gen_lowpart (GET_MODE (SUBREG_REG (op0)), op1);
11457 if ((nonzero_bits (tem, GET_MODE (SUBREG_REG (op0)))
11458 & ~GET_MODE_MASK (GET_MODE (op0))) == 0)
11459 op0 = SUBREG_REG (op0), op1 = tem;
11463 /* We now do the opposite procedure: Some machines don't have compare
11464 insns in all modes. If OP0's mode is an integer mode smaller than a
11465 word and we can't do a compare in that mode, see if there is a larger
11466 mode for which we can do the compare. There are a number of cases in
11467 which we can use the wider mode. */
11469 mode = GET_MODE (op0);
11470 if (mode != VOIDmode && GET_MODE_CLASS (mode) == MODE_INT
11471 && GET_MODE_SIZE (mode) < UNITS_PER_WORD
11472 && ! have_insn_for (COMPARE, mode))
11473 for (tmode = GET_MODE_WIDER_MODE (mode);
11475 && GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT);
11476 tmode = GET_MODE_WIDER_MODE (tmode))
11477 if (have_insn_for (COMPARE, tmode))
11481 /* If this is a test for negative, we can make an explicit
11482 test of the sign bit. Test this first so we can use
11483 a paradoxical subreg to extend OP0. */
11485 if (op1 == const0_rtx && (code == LT || code == GE)
11486 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
11488 op0 = simplify_gen_binary (AND, tmode,
11489 gen_lowpart (tmode, op0),
11490 GEN_INT ((HOST_WIDE_INT) 1
11491 << (GET_MODE_BITSIZE (mode)
11493 code = (code == LT) ? NE : EQ;
11497 /* If the only nonzero bits in OP0 and OP1 are those in the
11498 narrower mode and this is an equality or unsigned comparison,
11499 we can use the wider mode. Similarly for sign-extended
11500 values, in which case it is true for all comparisons. */
11501 zero_extended = ((code == EQ || code == NE
11502 || code == GEU || code == GTU
11503 || code == LEU || code == LTU)
11504 && (nonzero_bits (op0, tmode)
11505 & ~GET_MODE_MASK (mode)) == 0
11506 && ((CONST_INT_P (op1)
11507 || (nonzero_bits (op1, tmode)
11508 & ~GET_MODE_MASK (mode)) == 0)));
11511 || ((num_sign_bit_copies (op0, tmode)
11512 > (unsigned int) (GET_MODE_BITSIZE (tmode)
11513 - GET_MODE_BITSIZE (mode)))
11514 && (num_sign_bit_copies (op1, tmode)
11515 > (unsigned int) (GET_MODE_BITSIZE (tmode)
11516 - GET_MODE_BITSIZE (mode)))))
11518 /* If OP0 is an AND and we don't have an AND in MODE either,
11519 make a new AND in the proper mode. */
11520 if (GET_CODE (op0) == AND
11521 && !have_insn_for (AND, mode))
11522 op0 = simplify_gen_binary (AND, tmode,
11523 gen_lowpart (tmode,
11525 gen_lowpart (tmode,
11531 op0 = simplify_gen_unary (ZERO_EXTEND, tmode, op0, mode);
11532 op1 = simplify_gen_unary (ZERO_EXTEND, tmode, op1, mode);
11536 op0 = simplify_gen_unary (SIGN_EXTEND, tmode, op0, mode);
11537 op1 = simplify_gen_unary (SIGN_EXTEND, tmode, op1, mode);
11544 #ifdef CANONICALIZE_COMPARISON
11545 /* If this machine only supports a subset of valid comparisons, see if we
11546 can convert an unsupported one into a supported one. */
11547 CANONICALIZE_COMPARISON (code, op0, op1);
11556 /* Utility function for record_value_for_reg. Count number of
11561 enum rtx_code code = GET_CODE (x);
11565 if (GET_RTX_CLASS (code) == '2'
11566 || GET_RTX_CLASS (code) == 'c')
11568 rtx x0 = XEXP (x, 0);
11569 rtx x1 = XEXP (x, 1);
11572 return 1 + 2 * count_rtxs (x0);
11574 if ((GET_RTX_CLASS (GET_CODE (x1)) == '2'
11575 || GET_RTX_CLASS (GET_CODE (x1)) == 'c')
11576 && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1)))
11577 return 2 + 2 * count_rtxs (x0)
11578 + count_rtxs (x == XEXP (x1, 0)
11579 ? XEXP (x1, 1) : XEXP (x1, 0));
11581 if ((GET_RTX_CLASS (GET_CODE (x0)) == '2'
11582 || GET_RTX_CLASS (GET_CODE (x0)) == 'c')
11583 && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1)))
11584 return 2 + 2 * count_rtxs (x1)
11585 + count_rtxs (x == XEXP (x0, 0)
11586 ? XEXP (x0, 1) : XEXP (x0, 0));
11589 fmt = GET_RTX_FORMAT (code);
11590 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
11592 ret += count_rtxs (XEXP (x, i));
11593 else if (fmt[i] == 'E')
11594 for (j = 0; j < XVECLEN (x, i); j++)
11595 ret += count_rtxs (XVECEXP (x, i, j));
11600 /* Utility function for following routine. Called when X is part of a value
11601 being stored into last_set_value. Sets last_set_table_tick
11602 for each register mentioned. Similar to mention_regs in cse.c */
11605 update_table_tick (rtx x)
11607 enum rtx_code code = GET_CODE (x);
11608 const char *fmt = GET_RTX_FORMAT (code);
11613 unsigned int regno = REGNO (x);
11614 unsigned int endregno = END_REGNO (x);
11617 for (r = regno; r < endregno; r++)
11619 reg_stat_type *rsp = VEC_index (reg_stat_type, reg_stat, r);
11620 rsp->last_set_table_tick = label_tick;
11626 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
11629 /* Check for identical subexpressions. If x contains
11630 identical subexpression we only have to traverse one of
11632 if (i == 0 && ARITHMETIC_P (x))
11634 /* Note that at this point x1 has already been
11636 rtx x0 = XEXP (x, 0);
11637 rtx x1 = XEXP (x, 1);
11639 /* If x0 and x1 are identical then there is no need to
11644 /* If x0 is identical to a subexpression of x1 then while
11645 processing x1, x0 has already been processed. Thus we
11646 are done with x. */
11647 if (ARITHMETIC_P (x1)
11648 && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1)))
11651 /* If x1 is identical to a subexpression of x0 then we
11652 still have to process the rest of x0. */
11653 if (ARITHMETIC_P (x0)
11654 && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1)))
11656 update_table_tick (XEXP (x0, x1 == XEXP (x0, 0) ? 1 : 0));
11661 update_table_tick (XEXP (x, i));
11663 else if (fmt[i] == 'E')
11664 for (j = 0; j < XVECLEN (x, i); j++)
11665 update_table_tick (XVECEXP (x, i, j));
11668 /* Record that REG is set to VALUE in insn INSN. If VALUE is zero, we
11669 are saying that the register is clobbered and we no longer know its
11670 value. If INSN is zero, don't update reg_stat[].last_set; this is
11671 only permitted with VALUE also zero and is used to invalidate the
11675 record_value_for_reg (rtx reg, rtx insn, rtx value)
11677 unsigned int regno = REGNO (reg);
11678 unsigned int endregno = END_REGNO (reg);
11680 reg_stat_type *rsp;
11682 /* If VALUE contains REG and we have a previous value for REG, substitute
11683 the previous value. */
11684 if (value && insn && reg_overlap_mentioned_p (reg, value))
11688 /* Set things up so get_last_value is allowed to see anything set up to
11690 subst_low_luid = DF_INSN_LUID (insn);
11691 tem = get_last_value (reg);
11693 /* If TEM is simply a binary operation with two CLOBBERs as operands,
11694 it isn't going to be useful and will take a lot of time to process,
11695 so just use the CLOBBER. */
11699 if (ARITHMETIC_P (tem)
11700 && GET_CODE (XEXP (tem, 0)) == CLOBBER
11701 && GET_CODE (XEXP (tem, 1)) == CLOBBER)
11702 tem = XEXP (tem, 0);
11703 else if (count_occurrences (value, reg, 1) >= 2)
11705 /* If there are two or more occurrences of REG in VALUE,
11706 prevent the value from growing too much. */
11707 if (count_rtxs (tem) > MAX_LAST_VALUE_RTL)
11708 tem = gen_rtx_CLOBBER (GET_MODE (tem), const0_rtx);
11711 value = replace_rtx (copy_rtx (value), reg, tem);
11715 /* For each register modified, show we don't know its value, that
11716 we don't know about its bitwise content, that its value has been
11717 updated, and that we don't know the location of the death of the
11719 for (i = regno; i < endregno; i++)
11721 rsp = VEC_index (reg_stat_type, reg_stat, i);
11724 rsp->last_set = insn;
11726 rsp->last_set_value = 0;
11727 rsp->last_set_mode = VOIDmode;
11728 rsp->last_set_nonzero_bits = 0;
11729 rsp->last_set_sign_bit_copies = 0;
11730 rsp->last_death = 0;
11731 rsp->truncated_to_mode = VOIDmode;
11734 /* Mark registers that are being referenced in this value. */
11736 update_table_tick (value);
11738 /* Now update the status of each register being set.
11739 If someone is using this register in this block, set this register
11740 to invalid since we will get confused between the two lives in this
11741 basic block. This makes using this register always invalid. In cse, we
11742 scan the table to invalidate all entries using this register, but this
11743 is too much work for us. */
11745 for (i = regno; i < endregno; i++)
11747 rsp = VEC_index (reg_stat_type, reg_stat, i);
11748 rsp->last_set_label = label_tick;
11750 || (value && rsp->last_set_table_tick >= label_tick_ebb_start))
11751 rsp->last_set_invalid = 1;
11753 rsp->last_set_invalid = 0;
11756 /* The value being assigned might refer to X (like in "x++;"). In that
11757 case, we must replace it with (clobber (const_int 0)) to prevent
11759 rsp = VEC_index (reg_stat_type, reg_stat, regno);
11760 if (value && !get_last_value_validate (&value, insn, label_tick, 0))
11762 value = copy_rtx (value);
11763 if (!get_last_value_validate (&value, insn, label_tick, 1))
11767 /* For the main register being modified, update the value, the mode, the
11768 nonzero bits, and the number of sign bit copies. */
11770 rsp->last_set_value = value;
11774 enum machine_mode mode = GET_MODE (reg);
11775 subst_low_luid = DF_INSN_LUID (insn);
11776 rsp->last_set_mode = mode;
11777 if (GET_MODE_CLASS (mode) == MODE_INT
11778 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
11779 mode = nonzero_bits_mode;
11780 rsp->last_set_nonzero_bits = nonzero_bits (value, mode);
11781 rsp->last_set_sign_bit_copies
11782 = num_sign_bit_copies (value, GET_MODE (reg));
11786 /* Called via note_stores from record_dead_and_set_regs to handle one
11787 SET or CLOBBER in an insn. DATA is the instruction in which the
11788 set is occurring. */
11791 record_dead_and_set_regs_1 (rtx dest, const_rtx setter, void *data)
11793 rtx record_dead_insn = (rtx) data;
11795 if (GET_CODE (dest) == SUBREG)
11796 dest = SUBREG_REG (dest);
11798 if (!record_dead_insn)
11801 record_value_for_reg (dest, NULL_RTX, NULL_RTX);
11807 /* If we are setting the whole register, we know its value. Otherwise
11808 show that we don't know the value. We can handle SUBREG in
11810 if (GET_CODE (setter) == SET && dest == SET_DEST (setter))
11811 record_value_for_reg (dest, record_dead_insn, SET_SRC (setter));
11812 else if (GET_CODE (setter) == SET
11813 && GET_CODE (SET_DEST (setter)) == SUBREG
11814 && SUBREG_REG (SET_DEST (setter)) == dest
11815 && GET_MODE_BITSIZE (GET_MODE (dest)) <= BITS_PER_WORD
11816 && subreg_lowpart_p (SET_DEST (setter)))
11817 record_value_for_reg (dest, record_dead_insn,
11818 gen_lowpart (GET_MODE (dest),
11819 SET_SRC (setter)));
11821 record_value_for_reg (dest, record_dead_insn, NULL_RTX);
11823 else if (MEM_P (dest)
11824 /* Ignore pushes, they clobber nothing. */
11825 && ! push_operand (dest, GET_MODE (dest)))
11826 mem_last_set = DF_INSN_LUID (record_dead_insn);
11829 /* Update the records of when each REG was most recently set or killed
11830 for the things done by INSN. This is the last thing done in processing
11831 INSN in the combiner loop.
11833 We update reg_stat[], in particular fields last_set, last_set_value,
11834 last_set_mode, last_set_nonzero_bits, last_set_sign_bit_copies,
11835 last_death, and also the similar information mem_last_set (which insn
11836 most recently modified memory) and last_call_luid (which insn was the
11837 most recent subroutine call). */
11840 record_dead_and_set_regs (rtx insn)
11845 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
11847 if (REG_NOTE_KIND (link) == REG_DEAD
11848 && REG_P (XEXP (link, 0)))
11850 unsigned int regno = REGNO (XEXP (link, 0));
11851 unsigned int endregno = END_REGNO (XEXP (link, 0));
11853 for (i = regno; i < endregno; i++)
11855 reg_stat_type *rsp;
11857 rsp = VEC_index (reg_stat_type, reg_stat, i);
11858 rsp->last_death = insn;
11861 else if (REG_NOTE_KIND (link) == REG_INC)
11862 record_value_for_reg (XEXP (link, 0), insn, NULL_RTX);
11867 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
11868 if (TEST_HARD_REG_BIT (regs_invalidated_by_call, i))
11870 reg_stat_type *rsp;
11872 rsp = VEC_index (reg_stat_type, reg_stat, i);
11873 rsp->last_set_invalid = 1;
11874 rsp->last_set = insn;
11875 rsp->last_set_value = 0;
11876 rsp->last_set_mode = VOIDmode;
11877 rsp->last_set_nonzero_bits = 0;
11878 rsp->last_set_sign_bit_copies = 0;
11879 rsp->last_death = 0;
11880 rsp->truncated_to_mode = VOIDmode;
11883 last_call_luid = mem_last_set = DF_INSN_LUID (insn);
11885 /* We can't combine into a call pattern. Remember, though, that
11886 the return value register is set at this LUID. We could
11887 still replace a register with the return value from the
11888 wrong subroutine call! */
11889 note_stores (PATTERN (insn), record_dead_and_set_regs_1, NULL_RTX);
11892 note_stores (PATTERN (insn), record_dead_and_set_regs_1, insn);
11895 /* If a SUBREG has the promoted bit set, it is in fact a property of the
11896 register present in the SUBREG, so for each such SUBREG go back and
11897 adjust nonzero and sign bit information of the registers that are
11898 known to have some zero/sign bits set.
11900 This is needed because when combine blows the SUBREGs away, the
11901 information on zero/sign bits is lost and further combines can be
11902 missed because of that. */
11905 record_promoted_value (rtx insn, rtx subreg)
11908 unsigned int regno = REGNO (SUBREG_REG (subreg));
11909 enum machine_mode mode = GET_MODE (subreg);
11911 if (GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT)
11914 for (links = LOG_LINKS (insn); links;)
11916 reg_stat_type *rsp;
11918 insn = XEXP (links, 0);
11919 set = single_set (insn);
11921 if (! set || !REG_P (SET_DEST (set))
11922 || REGNO (SET_DEST (set)) != regno
11923 || GET_MODE (SET_DEST (set)) != GET_MODE (SUBREG_REG (subreg)))
11925 links = XEXP (links, 1);
11929 rsp = VEC_index (reg_stat_type, reg_stat, regno);
11930 if (rsp->last_set == insn)
11932 if (SUBREG_PROMOTED_UNSIGNED_P (subreg) > 0)
11933 rsp->last_set_nonzero_bits &= GET_MODE_MASK (mode);
11936 if (REG_P (SET_SRC (set)))
11938 regno = REGNO (SET_SRC (set));
11939 links = LOG_LINKS (insn);
11946 /* Check if X, a register, is known to contain a value already
11947 truncated to MODE. In this case we can use a subreg to refer to
11948 the truncated value even though in the generic case we would need
11949 an explicit truncation. */
11952 reg_truncated_to_mode (enum machine_mode mode, const_rtx x)
11954 reg_stat_type *rsp = VEC_index (reg_stat_type, reg_stat, REGNO (x));
11955 enum machine_mode truncated = rsp->truncated_to_mode;
11958 || rsp->truncation_label < label_tick_ebb_start)
11960 if (GET_MODE_SIZE (truncated) <= GET_MODE_SIZE (mode))
11962 if (TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode),
11963 GET_MODE_BITSIZE (truncated)))
11968 /* Callback for for_each_rtx. If *P is a hard reg or a subreg record the mode
11969 that the register is accessed in. For non-TRULY_NOOP_TRUNCATION targets we
11970 might be able to turn a truncate into a subreg using this information.
11971 Return -1 if traversing *P is complete or 0 otherwise. */
11974 record_truncated_value (rtx *p, void *data ATTRIBUTE_UNUSED)
11977 enum machine_mode truncated_mode;
11978 reg_stat_type *rsp;
11980 if (GET_CODE (x) == SUBREG && REG_P (SUBREG_REG (x)))
11982 enum machine_mode original_mode = GET_MODE (SUBREG_REG (x));
11983 truncated_mode = GET_MODE (x);
11985 if (GET_MODE_SIZE (original_mode) <= GET_MODE_SIZE (truncated_mode))
11988 if (TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (truncated_mode),
11989 GET_MODE_BITSIZE (original_mode)))
11992 x = SUBREG_REG (x);
11994 /* ??? For hard-regs we now record everything. We might be able to
11995 optimize this using last_set_mode. */
11996 else if (REG_P (x) && REGNO (x) < FIRST_PSEUDO_REGISTER)
11997 truncated_mode = GET_MODE (x);
12001 rsp = VEC_index (reg_stat_type, reg_stat, REGNO (x));
12002 if (rsp->truncated_to_mode == 0
12003 || rsp->truncation_label < label_tick_ebb_start
12004 || (GET_MODE_SIZE (truncated_mode)
12005 < GET_MODE_SIZE (rsp->truncated_to_mode)))
12007 rsp->truncated_to_mode = truncated_mode;
12008 rsp->truncation_label = label_tick;
12014 /* Callback for note_uses. Find hardregs and subregs of pseudos and
12015 the modes they are used in. This can help truning TRUNCATEs into
12019 record_truncated_values (rtx *x, void *data ATTRIBUTE_UNUSED)
12021 for_each_rtx (x, record_truncated_value, NULL);
12024 /* Scan X for promoted SUBREGs. For each one found,
12025 note what it implies to the registers used in it. */
12028 check_promoted_subreg (rtx insn, rtx x)
12030 if (GET_CODE (x) == SUBREG
12031 && SUBREG_PROMOTED_VAR_P (x)
12032 && REG_P (SUBREG_REG (x)))
12033 record_promoted_value (insn, x);
12036 const char *format = GET_RTX_FORMAT (GET_CODE (x));
12039 for (i = 0; i < GET_RTX_LENGTH (GET_CODE (x)); i++)
12043 check_promoted_subreg (insn, XEXP (x, i));
12047 if (XVEC (x, i) != 0)
12048 for (j = 0; j < XVECLEN (x, i); j++)
12049 check_promoted_subreg (insn, XVECEXP (x, i, j));
12055 /* Verify that all the registers and memory references mentioned in *LOC are
12056 still valid. *LOC was part of a value set in INSN when label_tick was
12057 equal to TICK. Return 0 if some are not. If REPLACE is nonzero, replace
12058 the invalid references with (clobber (const_int 0)) and return 1. This
12059 replacement is useful because we often can get useful information about
12060 the form of a value (e.g., if it was produced by a shift that always
12061 produces -1 or 0) even though we don't know exactly what registers it
12062 was produced from. */
12065 get_last_value_validate (rtx *loc, rtx insn, int tick, int replace)
12068 const char *fmt = GET_RTX_FORMAT (GET_CODE (x));
12069 int len = GET_RTX_LENGTH (GET_CODE (x));
12074 unsigned int regno = REGNO (x);
12075 unsigned int endregno = END_REGNO (x);
12078 for (j = regno; j < endregno; j++)
12080 reg_stat_type *rsp = VEC_index (reg_stat_type, reg_stat, j);
12081 if (rsp->last_set_invalid
12082 /* If this is a pseudo-register that was only set once and not
12083 live at the beginning of the function, it is always valid. */
12084 || (! (regno >= FIRST_PSEUDO_REGISTER
12085 && REG_N_SETS (regno) == 1
12086 && (!REGNO_REG_SET_P
12087 (DF_LR_IN (ENTRY_BLOCK_PTR->next_bb), regno)))
12088 && rsp->last_set_label > tick))
12091 *loc = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
12098 /* If this is a memory reference, make sure that there were no stores after
12099 it that might have clobbered the value. We don't have alias info, so we
12100 assume any store invalidates it. Moreover, we only have local UIDs, so
12101 we also assume that there were stores in the intervening basic blocks. */
12102 else if (MEM_P (x) && !MEM_READONLY_P (x)
12103 && (tick != label_tick || DF_INSN_LUID (insn) <= mem_last_set))
12106 *loc = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
12110 for (i = 0; i < len; i++)
12114 /* Check for identical subexpressions. If x contains
12115 identical subexpression we only have to traverse one of
12117 if (i == 1 && ARITHMETIC_P (x))
12119 /* Note that at this point x0 has already been checked
12120 and found valid. */
12121 rtx x0 = XEXP (x, 0);
12122 rtx x1 = XEXP (x, 1);
12124 /* If x0 and x1 are identical then x is also valid. */
12128 /* If x1 is identical to a subexpression of x0 then
12129 while checking x0, x1 has already been checked. Thus
12130 it is valid and so as x. */
12131 if (ARITHMETIC_P (x0)
12132 && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1)))
12135 /* If x0 is identical to a subexpression of x1 then x is
12136 valid iff the rest of x1 is valid. */
12137 if (ARITHMETIC_P (x1)
12138 && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1)))
12140 get_last_value_validate (&XEXP (x1,
12141 x0 == XEXP (x1, 0) ? 1 : 0),
12142 insn, tick, replace);
12145 if (get_last_value_validate (&XEXP (x, i), insn, tick,
12149 else if (fmt[i] == 'E')
12150 for (j = 0; j < XVECLEN (x, i); j++)
12151 if (get_last_value_validate (&XVECEXP (x, i, j),
12152 insn, tick, replace) == 0)
12156 /* If we haven't found a reason for it to be invalid, it is valid. */
12160 /* Get the last value assigned to X, if known. Some registers
12161 in the value may be replaced with (clobber (const_int 0)) if their value
12162 is known longer known reliably. */
12165 get_last_value (const_rtx x)
12167 unsigned int regno;
12169 reg_stat_type *rsp;
12171 /* If this is a non-paradoxical SUBREG, get the value of its operand and
12172 then convert it to the desired mode. If this is a paradoxical SUBREG,
12173 we cannot predict what values the "extra" bits might have. */
12174 if (GET_CODE (x) == SUBREG
12175 && subreg_lowpart_p (x)
12176 && (GET_MODE_SIZE (GET_MODE (x))
12177 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
12178 && (value = get_last_value (SUBREG_REG (x))) != 0)
12179 return gen_lowpart (GET_MODE (x), value);
12185 rsp = VEC_index (reg_stat_type, reg_stat, regno);
12186 value = rsp->last_set_value;
12188 /* If we don't have a value, or if it isn't for this basic block and
12189 it's either a hard register, set more than once, or it's a live
12190 at the beginning of the function, return 0.
12192 Because if it's not live at the beginning of the function then the reg
12193 is always set before being used (is never used without being set).
12194 And, if it's set only once, and it's always set before use, then all
12195 uses must have the same last value, even if it's not from this basic
12199 || (rsp->last_set_label < label_tick_ebb_start
12200 && (regno < FIRST_PSEUDO_REGISTER
12201 || REG_N_SETS (regno) != 1
12203 (DF_LR_IN (ENTRY_BLOCK_PTR->next_bb), regno))))
12206 /* If the value was set in a later insn than the ones we are processing,
12207 we can't use it even if the register was only set once. */
12208 if (rsp->last_set_label == label_tick
12209 && DF_INSN_LUID (rsp->last_set) >= subst_low_luid)
12212 /* If the value has all its registers valid, return it. */
12213 if (get_last_value_validate (&value, rsp->last_set, rsp->last_set_label, 0))
12216 /* Otherwise, make a copy and replace any invalid register with
12217 (clobber (const_int 0)). If that fails for some reason, return 0. */
12219 value = copy_rtx (value);
12220 if (get_last_value_validate (&value, rsp->last_set, rsp->last_set_label, 1))
12226 /* Return nonzero if expression X refers to a REG or to memory
12227 that is set in an instruction more recent than FROM_LUID. */
12230 use_crosses_set_p (const_rtx x, int from_luid)
12234 enum rtx_code code = GET_CODE (x);
12238 unsigned int regno = REGNO (x);
12239 unsigned endreg = END_REGNO (x);
12241 #ifdef PUSH_ROUNDING
12242 /* Don't allow uses of the stack pointer to be moved,
12243 because we don't know whether the move crosses a push insn. */
12244 if (regno == STACK_POINTER_REGNUM && PUSH_ARGS)
12247 for (; regno < endreg; regno++)
12249 reg_stat_type *rsp = VEC_index (reg_stat_type, reg_stat, regno);
12251 && rsp->last_set_label == label_tick
12252 && DF_INSN_LUID (rsp->last_set) > from_luid)
12258 if (code == MEM && mem_last_set > from_luid)
12261 fmt = GET_RTX_FORMAT (code);
12263 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
12268 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
12269 if (use_crosses_set_p (XVECEXP (x, i, j), from_luid))
12272 else if (fmt[i] == 'e'
12273 && use_crosses_set_p (XEXP (x, i), from_luid))
12279 /* Define three variables used for communication between the following
12282 static unsigned int reg_dead_regno, reg_dead_endregno;
12283 static int reg_dead_flag;
12285 /* Function called via note_stores from reg_dead_at_p.
12287 If DEST is within [reg_dead_regno, reg_dead_endregno), set
12288 reg_dead_flag to 1 if X is a CLOBBER and to -1 it is a SET. */
12291 reg_dead_at_p_1 (rtx dest, const_rtx x, void *data ATTRIBUTE_UNUSED)
12293 unsigned int regno, endregno;
12298 regno = REGNO (dest);
12299 endregno = END_REGNO (dest);
12300 if (reg_dead_endregno > regno && reg_dead_regno < endregno)
12301 reg_dead_flag = (GET_CODE (x) == CLOBBER) ? 1 : -1;
12304 /* Return nonzero if REG is known to be dead at INSN.
12306 We scan backwards from INSN. If we hit a REG_DEAD note or a CLOBBER
12307 referencing REG, it is dead. If we hit a SET referencing REG, it is
12308 live. Otherwise, see if it is live or dead at the start of the basic
12309 block we are in. Hard regs marked as being live in NEWPAT_USED_REGS
12310 must be assumed to be always live. */
12313 reg_dead_at_p (rtx reg, rtx insn)
12318 /* Set variables for reg_dead_at_p_1. */
12319 reg_dead_regno = REGNO (reg);
12320 reg_dead_endregno = END_REGNO (reg);
12324 /* Check that reg isn't mentioned in NEWPAT_USED_REGS. For fixed registers
12325 we allow the machine description to decide whether use-and-clobber
12326 patterns are OK. */
12327 if (reg_dead_regno < FIRST_PSEUDO_REGISTER)
12329 for (i = reg_dead_regno; i < reg_dead_endregno; i++)
12330 if (!fixed_regs[i] && TEST_HARD_REG_BIT (newpat_used_regs, i))
12334 /* Scan backwards until we find a REG_DEAD note, SET, CLOBBER, or
12335 beginning of basic block. */
12336 block = BLOCK_FOR_INSN (insn);
12341 note_stores (PATTERN (insn), reg_dead_at_p_1, NULL);
12343 return reg_dead_flag == 1 ? 1 : 0;
12345 if (find_regno_note (insn, REG_DEAD, reg_dead_regno))
12349 if (insn == BB_HEAD (block))
12352 insn = PREV_INSN (insn);
12355 /* Look at live-in sets for the basic block that we were in. */
12356 for (i = reg_dead_regno; i < reg_dead_endregno; i++)
12357 if (REGNO_REG_SET_P (df_get_live_in (block), i))
12363 /* Note hard registers in X that are used. */
12366 mark_used_regs_combine (rtx x)
12368 RTX_CODE code = GET_CODE (x);
12369 unsigned int regno;
12382 case ADDR_DIFF_VEC:
12385 /* CC0 must die in the insn after it is set, so we don't need to take
12386 special note of it here. */
12392 /* If we are clobbering a MEM, mark any hard registers inside the
12393 address as used. */
12394 if (MEM_P (XEXP (x, 0)))
12395 mark_used_regs_combine (XEXP (XEXP (x, 0), 0));
12400 /* A hard reg in a wide mode may really be multiple registers.
12401 If so, mark all of them just like the first. */
12402 if (regno < FIRST_PSEUDO_REGISTER)
12404 /* None of this applies to the stack, frame or arg pointers. */
12405 if (regno == STACK_POINTER_REGNUM
12406 #if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM
12407 || regno == HARD_FRAME_POINTER_REGNUM
12409 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
12410 || (regno == ARG_POINTER_REGNUM && fixed_regs[regno])
12412 || regno == FRAME_POINTER_REGNUM)
12415 add_to_hard_reg_set (&newpat_used_regs, GET_MODE (x), regno);
12421 /* If setting a MEM, or a SUBREG of a MEM, then note any hard regs in
12423 rtx testreg = SET_DEST (x);
12425 while (GET_CODE (testreg) == SUBREG
12426 || GET_CODE (testreg) == ZERO_EXTRACT
12427 || GET_CODE (testreg) == STRICT_LOW_PART)
12428 testreg = XEXP (testreg, 0);
12430 if (MEM_P (testreg))
12431 mark_used_regs_combine (XEXP (testreg, 0));
12433 mark_used_regs_combine (SET_SRC (x));
12441 /* Recursively scan the operands of this expression. */
12444 const char *fmt = GET_RTX_FORMAT (code);
12446 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
12449 mark_used_regs_combine (XEXP (x, i));
12450 else if (fmt[i] == 'E')
12454 for (j = 0; j < XVECLEN (x, i); j++)
12455 mark_used_regs_combine (XVECEXP (x, i, j));
12461 /* Remove register number REGNO from the dead registers list of INSN.
12463 Return the note used to record the death, if there was one. */
12466 remove_death (unsigned int regno, rtx insn)
12468 rtx note = find_regno_note (insn, REG_DEAD, regno);
12471 remove_note (insn, note);
12476 /* For each register (hardware or pseudo) used within expression X, if its
12477 death is in an instruction with luid between FROM_LUID (inclusive) and
12478 TO_INSN (exclusive), put a REG_DEAD note for that register in the
12479 list headed by PNOTES.
12481 That said, don't move registers killed by maybe_kill_insn.
12483 This is done when X is being merged by combination into TO_INSN. These
12484 notes will then be distributed as needed. */
12487 move_deaths (rtx x, rtx maybe_kill_insn, int from_luid, rtx to_insn,
12492 enum rtx_code code = GET_CODE (x);
12496 unsigned int regno = REGNO (x);
12497 rtx where_dead = VEC_index (reg_stat_type, reg_stat, regno)->last_death;
12499 /* Don't move the register if it gets killed in between from and to. */
12500 if (maybe_kill_insn && reg_set_p (x, maybe_kill_insn)
12501 && ! reg_referenced_p (x, maybe_kill_insn))
12505 && BLOCK_FOR_INSN (where_dead) == BLOCK_FOR_INSN (to_insn)
12506 && DF_INSN_LUID (where_dead) >= from_luid
12507 && DF_INSN_LUID (where_dead) < DF_INSN_LUID (to_insn))
12509 rtx note = remove_death (regno, where_dead);
12511 /* It is possible for the call above to return 0. This can occur
12512 when last_death points to I2 or I1 that we combined with.
12513 In that case make a new note.
12515 We must also check for the case where X is a hard register
12516 and NOTE is a death note for a range of hard registers
12517 including X. In that case, we must put REG_DEAD notes for
12518 the remaining registers in place of NOTE. */
12520 if (note != 0 && regno < FIRST_PSEUDO_REGISTER
12521 && (GET_MODE_SIZE (GET_MODE (XEXP (note, 0)))
12522 > GET_MODE_SIZE (GET_MODE (x))))
12524 unsigned int deadregno = REGNO (XEXP (note, 0));
12525 unsigned int deadend = END_HARD_REGNO (XEXP (note, 0));
12526 unsigned int ourend = END_HARD_REGNO (x);
12529 for (i = deadregno; i < deadend; i++)
12530 if (i < regno || i >= ourend)
12531 add_reg_note (where_dead, REG_DEAD, regno_reg_rtx[i]);
12534 /* If we didn't find any note, or if we found a REG_DEAD note that
12535 covers only part of the given reg, and we have a multi-reg hard
12536 register, then to be safe we must check for REG_DEAD notes
12537 for each register other than the first. They could have
12538 their own REG_DEAD notes lying around. */
12539 else if ((note == 0
12541 && (GET_MODE_SIZE (GET_MODE (XEXP (note, 0)))
12542 < GET_MODE_SIZE (GET_MODE (x)))))
12543 && regno < FIRST_PSEUDO_REGISTER
12544 && hard_regno_nregs[regno][GET_MODE (x)] > 1)
12546 unsigned int ourend = END_HARD_REGNO (x);
12547 unsigned int i, offset;
12551 offset = hard_regno_nregs[regno][GET_MODE (XEXP (note, 0))];
12555 for (i = regno + offset; i < ourend; i++)
12556 move_deaths (regno_reg_rtx[i],
12557 maybe_kill_insn, from_luid, to_insn, &oldnotes);
12560 if (note != 0 && GET_MODE (XEXP (note, 0)) == GET_MODE (x))
12562 XEXP (note, 1) = *pnotes;
12566 *pnotes = alloc_reg_note (REG_DEAD, x, *pnotes);
12572 else if (GET_CODE (x) == SET)
12574 rtx dest = SET_DEST (x);
12576 move_deaths (SET_SRC (x), maybe_kill_insn, from_luid, to_insn, pnotes);
12578 /* In the case of a ZERO_EXTRACT, a STRICT_LOW_PART, or a SUBREG
12579 that accesses one word of a multi-word item, some
12580 piece of everything register in the expression is used by
12581 this insn, so remove any old death. */
12582 /* ??? So why do we test for equality of the sizes? */
12584 if (GET_CODE (dest) == ZERO_EXTRACT
12585 || GET_CODE (dest) == STRICT_LOW_PART
12586 || (GET_CODE (dest) == SUBREG
12587 && (((GET_MODE_SIZE (GET_MODE (dest))
12588 + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
12589 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (dest)))
12590 + UNITS_PER_WORD - 1) / UNITS_PER_WORD))))
12592 move_deaths (dest, maybe_kill_insn, from_luid, to_insn, pnotes);
12596 /* If this is some other SUBREG, we know it replaces the entire
12597 value, so use that as the destination. */
12598 if (GET_CODE (dest) == SUBREG)
12599 dest = SUBREG_REG (dest);
12601 /* If this is a MEM, adjust deaths of anything used in the address.
12602 For a REG (the only other possibility), the entire value is
12603 being replaced so the old value is not used in this insn. */
12606 move_deaths (XEXP (dest, 0), maybe_kill_insn, from_luid,
12611 else if (GET_CODE (x) == CLOBBER)
12614 len = GET_RTX_LENGTH (code);
12615 fmt = GET_RTX_FORMAT (code);
12617 for (i = 0; i < len; i++)
12622 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
12623 move_deaths (XVECEXP (x, i, j), maybe_kill_insn, from_luid,
12626 else if (fmt[i] == 'e')
12627 move_deaths (XEXP (x, i), maybe_kill_insn, from_luid, to_insn, pnotes);
12631 /* Return 1 if X is the target of a bit-field assignment in BODY, the
12632 pattern of an insn. X must be a REG. */
12635 reg_bitfield_target_p (rtx x, rtx body)
12639 if (GET_CODE (body) == SET)
12641 rtx dest = SET_DEST (body);
12643 unsigned int regno, tregno, endregno, endtregno;
12645 if (GET_CODE (dest) == ZERO_EXTRACT)
12646 target = XEXP (dest, 0);
12647 else if (GET_CODE (dest) == STRICT_LOW_PART)
12648 target = SUBREG_REG (XEXP (dest, 0));
12652 if (GET_CODE (target) == SUBREG)
12653 target = SUBREG_REG (target);
12655 if (!REG_P (target))
12658 tregno = REGNO (target), regno = REGNO (x);
12659 if (tregno >= FIRST_PSEUDO_REGISTER || regno >= FIRST_PSEUDO_REGISTER)
12660 return target == x;
12662 endtregno = end_hard_regno (GET_MODE (target), tregno);
12663 endregno = end_hard_regno (GET_MODE (x), regno);
12665 return endregno > tregno && regno < endtregno;
12668 else if (GET_CODE (body) == PARALLEL)
12669 for (i = XVECLEN (body, 0) - 1; i >= 0; i--)
12670 if (reg_bitfield_target_p (x, XVECEXP (body, 0, i)))
12676 /* Return the next insn after INSN that is neither a NOTE nor a
12677 DEBUG_INSN. This routine does not look inside SEQUENCEs. */
12680 next_nonnote_nondebug_insn (rtx insn)
12684 insn = NEXT_INSN (insn);
12689 if (DEBUG_INSN_P (insn))
12699 /* Given a chain of REG_NOTES originally from FROM_INSN, try to place them
12700 as appropriate. I3 and I2 are the insns resulting from the combination
12701 insns including FROM (I2 may be zero).
12703 ELIM_I2 and ELIM_I1 are either zero or registers that we know will
12704 not need REG_DEAD notes because they are being substituted for. This
12705 saves searching in the most common cases.
12707 Each note in the list is either ignored or placed on some insns, depending
12708 on the type of note. */
12711 distribute_notes (rtx notes, rtx from_insn, rtx i3, rtx i2, rtx elim_i2,
12714 rtx note, next_note;
12717 for (note = notes; note; note = next_note)
12719 rtx place = 0, place2 = 0;
12721 next_note = XEXP (note, 1);
12722 switch (REG_NOTE_KIND (note))
12726 /* Doesn't matter much where we put this, as long as it's somewhere.
12727 It is preferable to keep these notes on branches, which is most
12728 likely to be i3. */
12732 case REG_VALUE_PROFILE:
12733 /* Just get rid of this note, as it is unused later anyway. */
12736 case REG_NON_LOCAL_GOTO:
12741 gcc_assert (i2 && JUMP_P (i2));
12746 case REG_EH_REGION:
12747 /* These notes must remain with the call or trapping instruction. */
12750 else if (i2 && CALL_P (i2))
12754 gcc_assert (flag_non_call_exceptions);
12755 if (may_trap_p (i3))
12757 else if (i2 && may_trap_p (i2))
12759 /* ??? Otherwise assume we've combined things such that we
12760 can now prove that the instructions can't trap. Drop the
12761 note in this case. */
12767 /* These notes must remain with the call. It should not be
12768 possible for both I2 and I3 to be a call. */
12773 gcc_assert (i2 && CALL_P (i2));
12779 /* Any clobbers for i3 may still exist, and so we must process
12780 REG_UNUSED notes from that insn.
12782 Any clobbers from i2 or i1 can only exist if they were added by
12783 recog_for_combine. In that case, recog_for_combine created the
12784 necessary REG_UNUSED notes. Trying to keep any original
12785 REG_UNUSED notes from these insns can cause incorrect output
12786 if it is for the same register as the original i3 dest.
12787 In that case, we will notice that the register is set in i3,
12788 and then add a REG_UNUSED note for the destination of i3, which
12789 is wrong. However, it is possible to have REG_UNUSED notes from
12790 i2 or i1 for register which were both used and clobbered, so
12791 we keep notes from i2 or i1 if they will turn into REG_DEAD
12794 /* If this register is set or clobbered in I3, put the note there
12795 unless there is one already. */
12796 if (reg_set_p (XEXP (note, 0), PATTERN (i3)))
12798 if (from_insn != i3)
12801 if (! (REG_P (XEXP (note, 0))
12802 ? find_regno_note (i3, REG_UNUSED, REGNO (XEXP (note, 0)))
12803 : find_reg_note (i3, REG_UNUSED, XEXP (note, 0))))
12806 /* Otherwise, if this register is used by I3, then this register
12807 now dies here, so we must put a REG_DEAD note here unless there
12809 else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3))
12810 && ! (REG_P (XEXP (note, 0))
12811 ? find_regno_note (i3, REG_DEAD,
12812 REGNO (XEXP (note, 0)))
12813 : find_reg_note (i3, REG_DEAD, XEXP (note, 0))))
12815 PUT_REG_NOTE_KIND (note, REG_DEAD);
12823 /* These notes say something about results of an insn. We can
12824 only support them if they used to be on I3 in which case they
12825 remain on I3. Otherwise they are ignored.
12827 If the note refers to an expression that is not a constant, we
12828 must also ignore the note since we cannot tell whether the
12829 equivalence is still true. It might be possible to do
12830 slightly better than this (we only have a problem if I2DEST
12831 or I1DEST is present in the expression), but it doesn't
12832 seem worth the trouble. */
12834 if (from_insn == i3
12835 && (XEXP (note, 0) == 0 || CONSTANT_P (XEXP (note, 0))))
12840 /* These notes say something about how a register is used. They must
12841 be present on any use of the register in I2 or I3. */
12842 if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3)))
12845 if (i2 && reg_mentioned_p (XEXP (note, 0), PATTERN (i2)))
12854 case REG_LABEL_TARGET:
12855 case REG_LABEL_OPERAND:
12856 /* This can show up in several ways -- either directly in the
12857 pattern, or hidden off in the constant pool with (or without?)
12858 a REG_EQUAL note. */
12859 /* ??? Ignore the without-reg_equal-note problem for now. */
12860 if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3))
12861 || ((tem = find_reg_note (i3, REG_EQUAL, NULL_RTX))
12862 && GET_CODE (XEXP (tem, 0)) == LABEL_REF
12863 && XEXP (XEXP (tem, 0), 0) == XEXP (note, 0)))
12867 && (reg_mentioned_p (XEXP (note, 0), PATTERN (i2))
12868 || ((tem = find_reg_note (i2, REG_EQUAL, NULL_RTX))
12869 && GET_CODE (XEXP (tem, 0)) == LABEL_REF
12870 && XEXP (XEXP (tem, 0), 0) == XEXP (note, 0))))
12878 /* For REG_LABEL_TARGET on a JUMP_P, we prefer to put the note
12879 as a JUMP_LABEL or decrement LABEL_NUSES if it's already
12881 if (place && JUMP_P (place)
12882 && REG_NOTE_KIND (note) == REG_LABEL_TARGET
12883 && (JUMP_LABEL (place) == NULL
12884 || JUMP_LABEL (place) == XEXP (note, 0)))
12886 rtx label = JUMP_LABEL (place);
12889 JUMP_LABEL (place) = XEXP (note, 0);
12890 else if (LABEL_P (label))
12891 LABEL_NUSES (label)--;
12894 if (place2 && JUMP_P (place2)
12895 && REG_NOTE_KIND (note) == REG_LABEL_TARGET
12896 && (JUMP_LABEL (place2) == NULL
12897 || JUMP_LABEL (place2) == XEXP (note, 0)))
12899 rtx label = JUMP_LABEL (place2);
12902 JUMP_LABEL (place2) = XEXP (note, 0);
12903 else if (LABEL_P (label))
12904 LABEL_NUSES (label)--;
12910 /* This note says something about the value of a register prior
12911 to the execution of an insn. It is too much trouble to see
12912 if the note is still correct in all situations. It is better
12913 to simply delete it. */
12917 /* If we replaced the right hand side of FROM_INSN with a
12918 REG_EQUAL note, the original use of the dying register
12919 will not have been combined into I3 and I2. In such cases,
12920 FROM_INSN is guaranteed to be the first of the combined
12921 instructions, so we simply need to search back before
12922 FROM_INSN for the previous use or set of this register,
12923 then alter the notes there appropriately.
12925 If the register is used as an input in I3, it dies there.
12926 Similarly for I2, if it is nonzero and adjacent to I3.
12928 If the register is not used as an input in either I3 or I2
12929 and it is not one of the registers we were supposed to eliminate,
12930 there are two possibilities. We might have a non-adjacent I2
12931 or we might have somehow eliminated an additional register
12932 from a computation. For example, we might have had A & B where
12933 we discover that B will always be zero. In this case we will
12934 eliminate the reference to A.
12936 In both cases, we must search to see if we can find a previous
12937 use of A and put the death note there. */
12940 && from_insn == i2mod
12941 && !reg_overlap_mentioned_p (XEXP (note, 0), i2mod_new_rhs))
12946 && CALL_P (from_insn)
12947 && find_reg_fusage (from_insn, USE, XEXP (note, 0)))
12949 else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3)))
12951 else if (i2 != 0 && next_nonnote_nondebug_insn (i2) == i3
12952 && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
12954 else if ((rtx_equal_p (XEXP (note, 0), elim_i2)
12956 && reg_overlap_mentioned_p (XEXP (note, 0),
12958 || rtx_equal_p (XEXP (note, 0), elim_i1))
12965 basic_block bb = this_basic_block;
12967 for (tem = PREV_INSN (tem); place == 0; tem = PREV_INSN (tem))
12969 if (!NONDEBUG_INSN_P (tem))
12971 if (tem == BB_HEAD (bb))
12976 /* If the register is being set at TEM, see if that is all
12977 TEM is doing. If so, delete TEM. Otherwise, make this
12978 into a REG_UNUSED note instead. Don't delete sets to
12979 global register vars. */
12980 if ((REGNO (XEXP (note, 0)) >= FIRST_PSEUDO_REGISTER
12981 || !global_regs[REGNO (XEXP (note, 0))])
12982 && reg_set_p (XEXP (note, 0), PATTERN (tem)))
12984 rtx set = single_set (tem);
12985 rtx inner_dest = 0;
12987 rtx cc0_setter = NULL_RTX;
12991 for (inner_dest = SET_DEST (set);
12992 (GET_CODE (inner_dest) == STRICT_LOW_PART
12993 || GET_CODE (inner_dest) == SUBREG
12994 || GET_CODE (inner_dest) == ZERO_EXTRACT);
12995 inner_dest = XEXP (inner_dest, 0))
12998 /* Verify that it was the set, and not a clobber that
12999 modified the register.
13001 CC0 targets must be careful to maintain setter/user
13002 pairs. If we cannot delete the setter due to side
13003 effects, mark the user with an UNUSED note instead
13006 if (set != 0 && ! side_effects_p (SET_SRC (set))
13007 && rtx_equal_p (XEXP (note, 0), inner_dest)
13009 && (! reg_mentioned_p (cc0_rtx, SET_SRC (set))
13010 || ((cc0_setter = prev_cc0_setter (tem)) != NULL
13011 && sets_cc0_p (PATTERN (cc0_setter)) > 0))
13015 /* Move the notes and links of TEM elsewhere.
13016 This might delete other dead insns recursively.
13017 First set the pattern to something that won't use
13019 rtx old_notes = REG_NOTES (tem);
13021 PATTERN (tem) = pc_rtx;
13022 REG_NOTES (tem) = NULL;
13024 distribute_notes (old_notes, tem, tem, NULL_RTX,
13025 NULL_RTX, NULL_RTX);
13026 distribute_links (LOG_LINKS (tem));
13028 SET_INSN_DELETED (tem);
13033 /* Delete the setter too. */
13036 PATTERN (cc0_setter) = pc_rtx;
13037 old_notes = REG_NOTES (cc0_setter);
13038 REG_NOTES (cc0_setter) = NULL;
13040 distribute_notes (old_notes, cc0_setter,
13041 cc0_setter, NULL_RTX,
13042 NULL_RTX, NULL_RTX);
13043 distribute_links (LOG_LINKS (cc0_setter));
13045 SET_INSN_DELETED (cc0_setter);
13046 if (cc0_setter == i2)
13053 PUT_REG_NOTE_KIND (note, REG_UNUSED);
13055 /* If there isn't already a REG_UNUSED note, put one
13056 here. Do not place a REG_DEAD note, even if
13057 the register is also used here; that would not
13058 match the algorithm used in lifetime analysis
13059 and can cause the consistency check in the
13060 scheduler to fail. */
13061 if (! find_regno_note (tem, REG_UNUSED,
13062 REGNO (XEXP (note, 0))))
13067 else if (reg_referenced_p (XEXP (note, 0), PATTERN (tem))
13069 && find_reg_fusage (tem, USE, XEXP (note, 0))))
13073 /* If we are doing a 3->2 combination, and we have a
13074 register which formerly died in i3 and was not used
13075 by i2, which now no longer dies in i3 and is used in
13076 i2 but does not die in i2, and place is between i2
13077 and i3, then we may need to move a link from place to
13079 if (i2 && DF_INSN_LUID (place) > DF_INSN_LUID (i2)
13081 && DF_INSN_LUID (from_insn) > DF_INSN_LUID (i2)
13082 && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
13084 rtx links = LOG_LINKS (place);
13085 LOG_LINKS (place) = 0;
13086 distribute_links (links);
13091 if (tem == BB_HEAD (bb))
13097 /* If the register is set or already dead at PLACE, we needn't do
13098 anything with this note if it is still a REG_DEAD note.
13099 We check here if it is set at all, not if is it totally replaced,
13100 which is what `dead_or_set_p' checks, so also check for it being
13103 if (place && REG_NOTE_KIND (note) == REG_DEAD)
13105 unsigned int regno = REGNO (XEXP (note, 0));
13106 reg_stat_type *rsp = VEC_index (reg_stat_type, reg_stat, regno);
13108 if (dead_or_set_p (place, XEXP (note, 0))
13109 || reg_bitfield_target_p (XEXP (note, 0), PATTERN (place)))
13111 /* Unless the register previously died in PLACE, clear
13112 last_death. [I no longer understand why this is
13114 if (rsp->last_death != place)
13115 rsp->last_death = 0;
13119 rsp->last_death = place;
13121 /* If this is a death note for a hard reg that is occupying
13122 multiple registers, ensure that we are still using all
13123 parts of the object. If we find a piece of the object
13124 that is unused, we must arrange for an appropriate REG_DEAD
13125 note to be added for it. However, we can't just emit a USE
13126 and tag the note to it, since the register might actually
13127 be dead; so we recourse, and the recursive call then finds
13128 the previous insn that used this register. */
13130 if (place && regno < FIRST_PSEUDO_REGISTER
13131 && hard_regno_nregs[regno][GET_MODE (XEXP (note, 0))] > 1)
13133 unsigned int endregno = END_HARD_REGNO (XEXP (note, 0));
13137 for (i = regno; i < endregno; i++)
13138 if ((! refers_to_regno_p (i, i + 1, PATTERN (place), 0)
13139 && ! find_regno_fusage (place, USE, i))
13140 || dead_or_set_regno_p (place, i))
13145 /* Put only REG_DEAD notes for pieces that are
13146 not already dead or set. */
13148 for (i = regno; i < endregno;
13149 i += hard_regno_nregs[i][reg_raw_mode[i]])
13151 rtx piece = regno_reg_rtx[i];
13152 basic_block bb = this_basic_block;
13154 if (! dead_or_set_p (place, piece)
13155 && ! reg_bitfield_target_p (piece,
13158 rtx new_note = alloc_reg_note (REG_DEAD, piece,
13161 distribute_notes (new_note, place, place,
13162 NULL_RTX, NULL_RTX, NULL_RTX);
13164 else if (! refers_to_regno_p (i, i + 1,
13165 PATTERN (place), 0)
13166 && ! find_regno_fusage (place, USE, i))
13167 for (tem = PREV_INSN (place); ;
13168 tem = PREV_INSN (tem))
13170 if (!NONDEBUG_INSN_P (tem))
13172 if (tem == BB_HEAD (bb))
13176 if (dead_or_set_p (tem, piece)
13177 || reg_bitfield_target_p (piece,
13180 add_reg_note (tem, REG_UNUSED, piece);
13194 /* Any other notes should not be present at this point in the
13196 gcc_unreachable ();
13201 XEXP (note, 1) = REG_NOTES (place);
13202 REG_NOTES (place) = note;
13206 add_reg_note (place2, REG_NOTE_KIND (note), XEXP (note, 0));
13210 /* Similarly to above, distribute the LOG_LINKS that used to be present on
13211 I3, I2, and I1 to new locations. This is also called to add a link
13212 pointing at I3 when I3's destination is changed. */
13215 distribute_links (rtx links)
13217 rtx link, next_link;
13219 for (link = links; link; link = next_link)
13225 next_link = XEXP (link, 1);
13227 /* If the insn that this link points to is a NOTE or isn't a single
13228 set, ignore it. In the latter case, it isn't clear what we
13229 can do other than ignore the link, since we can't tell which
13230 register it was for. Such links wouldn't be used by combine
13233 It is not possible for the destination of the target of the link to
13234 have been changed by combine. The only potential of this is if we
13235 replace I3, I2, and I1 by I3 and I2. But in that case the
13236 destination of I2 also remains unchanged. */
13238 if (NOTE_P (XEXP (link, 0))
13239 || (set = single_set (XEXP (link, 0))) == 0)
13242 reg = SET_DEST (set);
13243 while (GET_CODE (reg) == SUBREG || GET_CODE (reg) == ZERO_EXTRACT
13244 || GET_CODE (reg) == STRICT_LOW_PART)
13245 reg = XEXP (reg, 0);
13247 /* A LOG_LINK is defined as being placed on the first insn that uses
13248 a register and points to the insn that sets the register. Start
13249 searching at the next insn after the target of the link and stop
13250 when we reach a set of the register or the end of the basic block.
13252 Note that this correctly handles the link that used to point from
13253 I3 to I2. Also note that not much searching is typically done here
13254 since most links don't point very far away. */
13256 for (insn = NEXT_INSN (XEXP (link, 0));
13257 (insn && (this_basic_block->next_bb == EXIT_BLOCK_PTR
13258 || BB_HEAD (this_basic_block->next_bb) != insn));
13259 insn = NEXT_INSN (insn))
13260 if (DEBUG_INSN_P (insn))
13262 else if (INSN_P (insn) && reg_overlap_mentioned_p (reg, PATTERN (insn)))
13264 if (reg_referenced_p (reg, PATTERN (insn)))
13268 else if (CALL_P (insn)
13269 && find_reg_fusage (insn, USE, reg))
13274 else if (INSN_P (insn) && reg_set_p (reg, insn))
13277 /* If we found a place to put the link, place it there unless there
13278 is already a link to the same insn as LINK at that point. */
13284 for (link2 = LOG_LINKS (place); link2; link2 = XEXP (link2, 1))
13285 if (XEXP (link2, 0) == XEXP (link, 0))
13290 XEXP (link, 1) = LOG_LINKS (place);
13291 LOG_LINKS (place) = link;
13293 /* Set added_links_insn to the earliest insn we added a
13295 if (added_links_insn == 0
13296 || DF_INSN_LUID (added_links_insn) > DF_INSN_LUID (place))
13297 added_links_insn = place;
13303 /* Subroutine of unmentioned_reg_p and callback from for_each_rtx.
13304 Check whether the expression pointer to by LOC is a register or
13305 memory, and if so return 1 if it isn't mentioned in the rtx EXPR.
13306 Otherwise return zero. */
13309 unmentioned_reg_p_1 (rtx *loc, void *expr)
13314 && (REG_P (x) || MEM_P (x))
13315 && ! reg_mentioned_p (x, (rtx) expr))
13320 /* Check for any register or memory mentioned in EQUIV that is not
13321 mentioned in EXPR. This is used to restrict EQUIV to "specializations"
13322 of EXPR where some registers may have been replaced by constants. */
13325 unmentioned_reg_p (rtx equiv, rtx expr)
13327 return for_each_rtx (&equiv, unmentioned_reg_p_1, expr);
13331 dump_combine_stats (FILE *file)
13335 ";; Combiner statistics: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n\n",
13336 combine_attempts, combine_merges, combine_extras, combine_successes);
13340 dump_combine_total_stats (FILE *file)
13344 "\n;; Combiner totals: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n",
13345 total_attempts, total_merges, total_extras, total_successes);
13349 gate_handle_combine (void)
13351 return (optimize > 0);
13354 /* Try combining insns through substitution. */
13355 static unsigned int
13356 rest_of_handle_combine (void)
13358 int rebuild_jump_labels_after_combine;
13360 df_set_flags (DF_LR_RUN_DCE + DF_DEFER_INSN_RESCAN);
13361 df_note_add_problem ();
13364 regstat_init_n_sets_and_refs ();
13366 rebuild_jump_labels_after_combine
13367 = combine_instructions (get_insns (), max_reg_num ());
13369 /* Combining insns may have turned an indirect jump into a
13370 direct jump. Rebuild the JUMP_LABEL fields of jumping
13372 if (rebuild_jump_labels_after_combine)
13374 timevar_push (TV_JUMP);
13375 rebuild_jump_labels (get_insns ());
13377 timevar_pop (TV_JUMP);
13380 regstat_free_n_sets_and_refs ();
13384 struct rtl_opt_pass pass_combine =
13388 "combine", /* name */
13389 gate_handle_combine, /* gate */
13390 rest_of_handle_combine, /* execute */
13393 0, /* static_pass_number */
13394 TV_COMBINE, /* tv_id */
13395 PROP_cfglayout, /* properties_required */
13396 0, /* properties_provided */
13397 0, /* properties_destroyed */
13398 0, /* todo_flags_start */
13400 TODO_df_finish | TODO_verify_rtl_sharing |
13401 TODO_ggc_collect, /* todo_flags_finish */