1 /* Optimize by combining instructions for GNU compiler.
2 Copyright (C) 1987, 1988, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it under
8 the terms of the GNU General Public License as published by the Free
9 Software Foundation; either version 2, or (at your option) any later
12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING. If not, write to the Free
19 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
22 /* This module is essentially the "combiner" phase of the U. of Arizona
23 Portable Optimizer, but redone to work on our list-structured
24 representation for RTL instead of their string representation.
26 The LOG_LINKS of each insn identify the most recent assignment
27 to each REG used in the insn. It is a list of previous insns,
28 each of which contains a SET for a REG that is used in this insn
29 and not used or set in between. LOG_LINKs never cross basic blocks.
30 They were set up by the preceding pass (lifetime analysis).
32 We try to combine each pair of insns joined by a logical link.
33 We also try to combine triples of insns A, B and C when
34 C has a link back to B and B has a link back to A.
36 LOG_LINKS does not have links for use of the CC0. They don't
37 need to, because the insn that sets the CC0 is always immediately
38 before the insn that tests it. So we always regard a branch
39 insn as having a logical link to the preceding insn. The same is true
40 for an insn explicitly using CC0.
42 We check (with use_crosses_set_p) to avoid combining in such a way
43 as to move a computation to a place where its value would be different.
45 Combination is done by mathematically substituting the previous
46 insn(s) values for the regs they set into the expressions in
47 the later insns that refer to these regs. If the result is a valid insn
48 for our target machine, according to the machine description,
49 we install it, delete the earlier insns, and update the data flow
50 information (LOG_LINKS and REG_NOTES) for what we did.
52 There are a few exceptions where the dataflow information created by
53 flow.c aren't completely updated:
55 - reg_live_length is not updated
56 - reg_n_refs is not adjusted in the rare case when a register is
57 no longer required in a computation
58 - there are extremely rare cases (see distribute_regnotes) when a
60 - a LOG_LINKS entry that refers to an insn with multiple SETs may be
61 removed because there is no way to know which register it was
64 To simplify substitution, we combine only when the earlier insn(s)
65 consist of only a single assignment. To simplify updating afterward,
66 we never combine when a subroutine call appears in the middle.
68 Since we do not represent assignments to CC0 explicitly except when that
69 is all an insn does, there is no LOG_LINKS entry in an insn that uses
70 the condition code for the insn that set the condition code.
71 Fortunately, these two insns must be consecutive.
72 Therefore, every JUMP_INSN is taken to have an implicit logical link
73 to the preceding insn. This is not quite right, since non-jumps can
74 also use the condition code; but in practice such insns would not
83 #include "hard-reg-set.h"
84 #include "basic-block.h"
85 #include "insn-config.h"
87 /* Include expr.h after insn-config.h so we get HAVE_conditional_move. */
89 #include "insn-attr.h"
94 /* It is not safe to use ordinary gen_lowpart in combine.
95 Use gen_lowpart_for_combine instead. See comments there. */
96 #define gen_lowpart dont_use_gen_lowpart_you_dummy
98 /* Number of attempts to combine instructions in this function. */
100 static int combine_attempts;
102 /* Number of attempts that got as far as substitution in this function. */
104 static int combine_merges;
106 /* Number of instructions combined with added SETs in this function. */
108 static int combine_extras;
110 /* Number of instructions combined in this function. */
112 static int combine_successes;
114 /* Totals over entire compilation. */
116 static int total_attempts, total_merges, total_extras, total_successes;
119 /* Vector mapping INSN_UIDs to cuids.
120 The cuids are like uids but increase monotonically always.
121 Combine always uses cuids so that it can compare them.
122 But actually renumbering the uids, which we used to do,
123 proves to be a bad idea because it makes it hard to compare
124 the dumps produced by earlier passes with those from later passes. */
126 static int *uid_cuid;
127 static int max_uid_cuid;
129 /* Get the cuid of an insn. */
131 #define INSN_CUID(INSN) \
132 (INSN_UID (INSN) > max_uid_cuid ? insn_cuid (INSN) : uid_cuid[INSN_UID (INSN)])
134 /* In case BITS_PER_WORD == HOST_BITS_PER_WIDE_INT, shifting by
135 BITS_PER_WORD would invoke undefined behavior. Work around it. */
137 #define UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD(val) \
138 (((unsigned HOST_WIDE_INT) (val) << (BITS_PER_WORD - 1)) << 1)
140 /* Maximum register number, which is the size of the tables below. */
142 static unsigned int combine_max_regno;
144 /* Record last point of death of (hard or pseudo) register n. */
146 static rtx *reg_last_death;
148 /* Record last point of modification of (hard or pseudo) register n. */
150 static rtx *reg_last_set;
152 /* Record the cuid of the last insn that invalidated memory
153 (anything that writes memory, and subroutine calls, but not pushes). */
155 static int mem_last_set;
157 /* Record the cuid of the last CALL_INSN
158 so we can tell whether a potential combination crosses any calls. */
160 static int last_call_cuid;
162 /* When `subst' is called, this is the insn that is being modified
163 (by combining in a previous insn). The PATTERN of this insn
164 is still the old pattern partially modified and it should not be
165 looked at, but this may be used to examine the successors of the insn
166 to judge whether a simplification is valid. */
168 static rtx subst_insn;
170 /* This is an insn that belongs before subst_insn, but is not currently
171 on the insn chain. */
173 static rtx subst_prev_insn;
175 /* This is the lowest CUID that `subst' is currently dealing with.
176 get_last_value will not return a value if the register was set at or
177 after this CUID. If not for this mechanism, we could get confused if
178 I2 or I1 in try_combine were an insn that used the old value of a register
179 to obtain a new value. In that case, we might erroneously get the
180 new value of the register when we wanted the old one. */
182 static int subst_low_cuid;
184 /* This contains any hard registers that are used in newpat; reg_dead_at_p
185 must consider all these registers to be always live. */
187 static HARD_REG_SET newpat_used_regs;
189 /* This is an insn to which a LOG_LINKS entry has been added. If this
190 insn is the earlier than I2 or I3, combine should rescan starting at
193 static rtx added_links_insn;
195 /* Basic block number of the block in which we are performing combines. */
196 static int this_basic_block;
198 /* A bitmap indicating which blocks had registers go dead at entry.
199 After combine, we'll need to re-do global life analysis with
200 those blocks as starting points. */
201 static sbitmap refresh_blocks;
202 static int need_refresh;
204 /* The next group of arrays allows the recording of the last value assigned
205 to (hard or pseudo) register n. We use this information to see if a
206 operation being processed is redundant given a prior operation performed
207 on the register. For example, an `and' with a constant is redundant if
208 all the zero bits are already known to be turned off.
210 We use an approach similar to that used by cse, but change it in the
213 (1) We do not want to reinitialize at each label.
214 (2) It is useful, but not critical, to know the actual value assigned
215 to a register. Often just its form is helpful.
217 Therefore, we maintain the following arrays:
219 reg_last_set_value the last value assigned
220 reg_last_set_label records the value of label_tick when the
221 register was assigned
222 reg_last_set_table_tick records the value of label_tick when a
223 value using the register is assigned
224 reg_last_set_invalid set to non-zero when it is not valid
225 to use the value of this register in some
228 To understand the usage of these tables, it is important to understand
229 the distinction between the value in reg_last_set_value being valid
230 and the register being validly contained in some other expression in the
233 Entry I in reg_last_set_value is valid if it is non-zero, and either
234 reg_n_sets[i] is 1 or reg_last_set_label[i] == label_tick.
236 Register I may validly appear in any expression returned for the value
237 of another register if reg_n_sets[i] is 1. It may also appear in the
238 value for register J if reg_last_set_label[i] < reg_last_set_label[j] or
239 reg_last_set_invalid[j] is zero.
241 If an expression is found in the table containing a register which may
242 not validly appear in an expression, the register is replaced by
243 something that won't match, (clobber (const_int 0)).
245 reg_last_set_invalid[i] is set non-zero when register I is being assigned
246 to and reg_last_set_table_tick[i] == label_tick. */
248 /* Record last value assigned to (hard or pseudo) register n. */
250 static rtx *reg_last_set_value;
252 /* Record the value of label_tick when the value for register n is placed in
253 reg_last_set_value[n]. */
255 static int *reg_last_set_label;
257 /* Record the value of label_tick when an expression involving register n
258 is placed in reg_last_set_value. */
260 static int *reg_last_set_table_tick;
262 /* Set non-zero if references to register n in expressions should not be
265 static char *reg_last_set_invalid;
267 /* Incremented for each label. */
269 static int label_tick;
271 /* Some registers that are set more than once and used in more than one
272 basic block are nevertheless always set in similar ways. For example,
273 a QImode register may be loaded from memory in two places on a machine
274 where byte loads zero extend.
276 We record in the following array what we know about the nonzero
277 bits of a register, specifically which bits are known to be zero.
279 If an entry is zero, it means that we don't know anything special. */
281 static unsigned HOST_WIDE_INT *reg_nonzero_bits;
283 /* Mode used to compute significance in reg_nonzero_bits. It is the largest
284 integer mode that can fit in HOST_BITS_PER_WIDE_INT. */
286 static enum machine_mode nonzero_bits_mode;
288 /* Nonzero if we know that a register has some leading bits that are always
289 equal to the sign bit. */
291 static unsigned char *reg_sign_bit_copies;
293 /* Nonzero when reg_nonzero_bits and reg_sign_bit_copies can be safely used.
294 It is zero while computing them and after combine has completed. This
295 former test prevents propagating values based on previously set values,
296 which can be incorrect if a variable is modified in a loop. */
298 static int nonzero_sign_valid;
300 /* These arrays are maintained in parallel with reg_last_set_value
301 and are used to store the mode in which the register was last set,
302 the bits that were known to be zero when it was last set, and the
303 number of sign bits copies it was known to have when it was last set. */
305 static enum machine_mode *reg_last_set_mode;
306 static unsigned HOST_WIDE_INT *reg_last_set_nonzero_bits;
307 static char *reg_last_set_sign_bit_copies;
309 /* Record one modification to rtl structure
310 to be undone by storing old_contents into *where.
311 is_int is 1 if the contents are an int. */
317 union {rtx r; unsigned int i;} old_contents;
318 union {rtx *r; unsigned int *i;} where;
321 /* Record a bunch of changes to be undone, up to MAX_UNDO of them.
322 num_undo says how many are currently recorded.
324 other_insn is nonzero if we have modified some other insn in the process
325 of working on subst_insn. It must be verified too. */
334 static struct undobuf undobuf;
336 /* Number of times the pseudo being substituted for
337 was found and replaced. */
339 static int n_occurrences;
341 static void do_SUBST PARAMS ((rtx *, rtx));
342 static void do_SUBST_INT PARAMS ((unsigned int *,
344 static void init_reg_last_arrays PARAMS ((void));
345 static void setup_incoming_promotions PARAMS ((void));
346 static void set_nonzero_bits_and_sign_copies PARAMS ((rtx, rtx, void *));
347 static int cant_combine_insn_p PARAMS ((rtx));
348 static int can_combine_p PARAMS ((rtx, rtx, rtx, rtx, rtx *, rtx *));
349 static int sets_function_arg_p PARAMS ((rtx));
350 static int combinable_i3pat PARAMS ((rtx, rtx *, rtx, rtx, int, rtx *));
351 static int contains_muldiv PARAMS ((rtx));
352 static rtx try_combine PARAMS ((rtx, rtx, rtx, int *));
353 static void undo_all PARAMS ((void));
354 static void undo_commit PARAMS ((void));
355 static rtx *find_split_point PARAMS ((rtx *, rtx));
356 static rtx subst PARAMS ((rtx, rtx, rtx, int, int));
357 static rtx combine_simplify_rtx PARAMS ((rtx, enum machine_mode, int, int));
358 static rtx simplify_if_then_else PARAMS ((rtx));
359 static rtx simplify_set PARAMS ((rtx));
360 static rtx simplify_logical PARAMS ((rtx, int));
361 static rtx expand_compound_operation PARAMS ((rtx));
362 static rtx expand_field_assignment PARAMS ((rtx));
363 static rtx make_extraction PARAMS ((enum machine_mode, rtx, HOST_WIDE_INT,
364 rtx, unsigned HOST_WIDE_INT, int,
366 static rtx extract_left_shift PARAMS ((rtx, int));
367 static rtx make_compound_operation PARAMS ((rtx, enum rtx_code));
368 static int get_pos_from_mask PARAMS ((unsigned HOST_WIDE_INT,
369 unsigned HOST_WIDE_INT *));
370 static rtx force_to_mode PARAMS ((rtx, enum machine_mode,
371 unsigned HOST_WIDE_INT, rtx, int));
372 static rtx if_then_else_cond PARAMS ((rtx, rtx *, rtx *));
373 static rtx known_cond PARAMS ((rtx, enum rtx_code, rtx, rtx));
374 static int rtx_equal_for_field_assignment_p PARAMS ((rtx, rtx));
375 static rtx make_field_assignment PARAMS ((rtx));
376 static rtx apply_distributive_law PARAMS ((rtx));
377 static rtx simplify_and_const_int PARAMS ((rtx, enum machine_mode, rtx,
378 unsigned HOST_WIDE_INT));
379 static unsigned HOST_WIDE_INT nonzero_bits PARAMS ((rtx, enum machine_mode));
380 static unsigned int num_sign_bit_copies PARAMS ((rtx, enum machine_mode));
381 static int merge_outer_ops PARAMS ((enum rtx_code *, HOST_WIDE_INT *,
382 enum rtx_code, HOST_WIDE_INT,
383 enum machine_mode, int *));
384 static rtx simplify_shift_const PARAMS ((rtx, enum rtx_code, enum machine_mode,
386 static int recog_for_combine PARAMS ((rtx *, rtx, rtx *));
387 static rtx gen_lowpart_for_combine PARAMS ((enum machine_mode, rtx));
388 static rtx gen_binary PARAMS ((enum rtx_code, enum machine_mode,
390 static enum rtx_code simplify_comparison PARAMS ((enum rtx_code, rtx *, rtx *));
391 static void update_table_tick PARAMS ((rtx));
392 static void record_value_for_reg PARAMS ((rtx, rtx, rtx));
393 static void check_promoted_subreg PARAMS ((rtx, rtx));
394 static void record_dead_and_set_regs_1 PARAMS ((rtx, rtx, void *));
395 static void record_dead_and_set_regs PARAMS ((rtx));
396 static int get_last_value_validate PARAMS ((rtx *, rtx, int, int));
397 static rtx get_last_value PARAMS ((rtx));
398 static int use_crosses_set_p PARAMS ((rtx, int));
399 static void reg_dead_at_p_1 PARAMS ((rtx, rtx, void *));
400 static int reg_dead_at_p PARAMS ((rtx, rtx));
401 static void move_deaths PARAMS ((rtx, rtx, int, rtx, rtx *));
402 static int reg_bitfield_target_p PARAMS ((rtx, rtx));
403 static void distribute_notes PARAMS ((rtx, rtx, rtx, rtx, rtx, rtx));
404 static void distribute_links PARAMS ((rtx));
405 static void mark_used_regs_combine PARAMS ((rtx));
406 static int insn_cuid PARAMS ((rtx));
407 static void record_promoted_value PARAMS ((rtx, rtx));
408 static rtx reversed_comparison PARAMS ((rtx, enum machine_mode, rtx, rtx));
409 static enum rtx_code combine_reversed_comparison_code PARAMS ((rtx));
411 /* Substitute NEWVAL, an rtx expression, into INTO, a place in some
412 insn. The substitution can be undone by undo_all. If INTO is already
413 set to NEWVAL, do not record this change. Because computing NEWVAL might
414 also call SUBST, we have to compute it before we put anything into
418 do_SUBST (into, newval)
424 if (oldval == newval)
427 /* We'd like to catch as many invalid transformations here as
428 possible. Unfortunately, there are way too many mode changes
429 that are perfectly valid, so we'd waste too much effort for
430 little gain doing the checks here. Focus on catching invalid
431 transformations involving integer constants. */
432 if (GET_MODE_CLASS (GET_MODE (oldval)) == MODE_INT
433 && GET_CODE (newval) == CONST_INT)
435 /* Sanity check that we're replacing oldval with a CONST_INT
436 that is a valid sign-extension for the original mode. */
437 if (INTVAL (newval) != trunc_int_for_mode (INTVAL (newval),
441 /* Replacing the operand of a SUBREG or a ZERO_EXTEND with a
442 CONST_INT is not valid, because after the replacement, the
443 original mode would be gone. Unfortunately, we can't tell
444 when do_SUBST is called to replace the operand thereof, so we
445 perform this test on oldval instead, checking whether an
446 invalid replacement took place before we got here. */
447 if ((GET_CODE (oldval) == SUBREG
448 && GET_CODE (SUBREG_REG (oldval)) == CONST_INT)
449 || (GET_CODE (oldval) == ZERO_EXTEND
450 && GET_CODE (XEXP (oldval, 0)) == CONST_INT))
455 buf = undobuf.frees, undobuf.frees = buf->next;
457 buf = (struct undo *) xmalloc (sizeof (struct undo));
461 buf->old_contents.r = oldval;
464 buf->next = undobuf.undos, undobuf.undos = buf;
467 #define SUBST(INTO, NEWVAL) do_SUBST(&(INTO), (NEWVAL))
469 /* Similar to SUBST, but NEWVAL is an int expression. Note that substitution
470 for the value of a HOST_WIDE_INT value (including CONST_INT) is
474 do_SUBST_INT (into, newval)
475 unsigned int *into, newval;
478 unsigned int oldval = *into;
480 if (oldval == newval)
484 buf = undobuf.frees, undobuf.frees = buf->next;
486 buf = (struct undo *) xmalloc (sizeof (struct undo));
490 buf->old_contents.i = oldval;
493 buf->next = undobuf.undos, undobuf.undos = buf;
496 #define SUBST_INT(INTO, NEWVAL) do_SUBST_INT(&(INTO), (NEWVAL))
498 /* Main entry point for combiner. F is the first insn of the function.
499 NREGS is the first unused pseudo-reg number.
501 Return non-zero if the combiner has turned an indirect jump
502 instruction into a direct jump. */
504 combine_instructions (f, nregs)
513 rtx links, nextlinks;
515 int new_direct_jump_p = 0;
517 combine_attempts = 0;
520 combine_successes = 0;
522 combine_max_regno = nregs;
524 reg_nonzero_bits = ((unsigned HOST_WIDE_INT *)
525 xcalloc (nregs, sizeof (unsigned HOST_WIDE_INT)));
527 = (unsigned char *) xcalloc (nregs, sizeof (unsigned char));
529 reg_last_death = (rtx *) xmalloc (nregs * sizeof (rtx));
530 reg_last_set = (rtx *) xmalloc (nregs * sizeof (rtx));
531 reg_last_set_value = (rtx *) xmalloc (nregs * sizeof (rtx));
532 reg_last_set_table_tick = (int *) xmalloc (nregs * sizeof (int));
533 reg_last_set_label = (int *) xmalloc (nregs * sizeof (int));
534 reg_last_set_invalid = (char *) xmalloc (nregs * sizeof (char));
536 = (enum machine_mode *) xmalloc (nregs * sizeof (enum machine_mode));
537 reg_last_set_nonzero_bits
538 = (unsigned HOST_WIDE_INT *) xmalloc (nregs * sizeof (HOST_WIDE_INT));
539 reg_last_set_sign_bit_copies
540 = (char *) xmalloc (nregs * sizeof (char));
542 init_reg_last_arrays ();
544 init_recog_no_volatile ();
546 /* Compute maximum uid value so uid_cuid can be allocated. */
548 for (insn = f, i = 0; insn; insn = NEXT_INSN (insn))
549 if (INSN_UID (insn) > i)
552 uid_cuid = (int *) xmalloc ((i + 1) * sizeof (int));
555 nonzero_bits_mode = mode_for_size (HOST_BITS_PER_WIDE_INT, MODE_INT, 0);
557 /* Don't use reg_nonzero_bits when computing it. This can cause problems
558 when, for example, we have j <<= 1 in a loop. */
560 nonzero_sign_valid = 0;
562 /* Compute the mapping from uids to cuids.
563 Cuids are numbers assigned to insns, like uids,
564 except that cuids increase monotonically through the code.
566 Scan all SETs and see if we can deduce anything about what
567 bits are known to be zero for some registers and how many copies
568 of the sign bit are known to exist for those registers.
570 Also set any known values so that we can use it while searching
571 for what bits are known to be set. */
575 /* We need to initialize it here, because record_dead_and_set_regs may call
577 subst_prev_insn = NULL_RTX;
579 setup_incoming_promotions ();
581 refresh_blocks = sbitmap_alloc (n_basic_blocks);
582 sbitmap_zero (refresh_blocks);
585 for (insn = f, i = 0; insn; insn = NEXT_INSN (insn))
587 uid_cuid[INSN_UID (insn)] = ++i;
593 note_stores (PATTERN (insn), set_nonzero_bits_and_sign_copies,
595 record_dead_and_set_regs (insn);
598 for (links = REG_NOTES (insn); links; links = XEXP (links, 1))
599 if (REG_NOTE_KIND (links) == REG_INC)
600 set_nonzero_bits_and_sign_copies (XEXP (links, 0), NULL_RTX,
605 if (GET_CODE (insn) == CODE_LABEL)
609 nonzero_sign_valid = 1;
611 /* Now scan all the insns in forward order. */
613 this_basic_block = -1;
617 init_reg_last_arrays ();
618 setup_incoming_promotions ();
620 for (insn = f; insn; insn = next ? next : NEXT_INSN (insn))
624 /* If INSN starts a new basic block, update our basic block number. */
625 if (this_basic_block + 1 < n_basic_blocks
626 && BLOCK_HEAD (this_basic_block + 1) == insn)
629 if (GET_CODE (insn) == CODE_LABEL)
632 else if (INSN_P (insn))
634 /* See if we know about function return values before this
635 insn based upon SUBREG flags. */
636 check_promoted_subreg (insn, PATTERN (insn));
638 /* Try this insn with each insn it links back to. */
640 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
641 if ((next = try_combine (insn, XEXP (links, 0),
642 NULL_RTX, &new_direct_jump_p)) != 0)
645 /* Try each sequence of three linked insns ending with this one. */
647 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
649 rtx link = XEXP (links, 0);
651 /* If the linked insn has been replaced by a note, then there
652 is no point in pursuing this chain any further. */
653 if (GET_CODE (link) == NOTE)
656 for (nextlinks = LOG_LINKS (link);
658 nextlinks = XEXP (nextlinks, 1))
659 if ((next = try_combine (insn, link,
661 &new_direct_jump_p)) != 0)
666 /* Try to combine a jump insn that uses CC0
667 with a preceding insn that sets CC0, and maybe with its
668 logical predecessor as well.
669 This is how we make decrement-and-branch insns.
670 We need this special code because data flow connections
671 via CC0 do not get entered in LOG_LINKS. */
673 if (GET_CODE (insn) == JUMP_INSN
674 && (prev = prev_nonnote_insn (insn)) != 0
675 && GET_CODE (prev) == INSN
676 && sets_cc0_p (PATTERN (prev)))
678 if ((next = try_combine (insn, prev,
679 NULL_RTX, &new_direct_jump_p)) != 0)
682 for (nextlinks = LOG_LINKS (prev); nextlinks;
683 nextlinks = XEXP (nextlinks, 1))
684 if ((next = try_combine (insn, prev,
686 &new_direct_jump_p)) != 0)
690 /* Do the same for an insn that explicitly references CC0. */
691 if (GET_CODE (insn) == INSN
692 && (prev = prev_nonnote_insn (insn)) != 0
693 && GET_CODE (prev) == INSN
694 && sets_cc0_p (PATTERN (prev))
695 && GET_CODE (PATTERN (insn)) == SET
696 && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (insn))))
698 if ((next = try_combine (insn, prev,
699 NULL_RTX, &new_direct_jump_p)) != 0)
702 for (nextlinks = LOG_LINKS (prev); nextlinks;
703 nextlinks = XEXP (nextlinks, 1))
704 if ((next = try_combine (insn, prev,
706 &new_direct_jump_p)) != 0)
710 /* Finally, see if any of the insns that this insn links to
711 explicitly references CC0. If so, try this insn, that insn,
712 and its predecessor if it sets CC0. */
713 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
714 if (GET_CODE (XEXP (links, 0)) == INSN
715 && GET_CODE (PATTERN (XEXP (links, 0))) == SET
716 && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (XEXP (links, 0))))
717 && (prev = prev_nonnote_insn (XEXP (links, 0))) != 0
718 && GET_CODE (prev) == INSN
719 && sets_cc0_p (PATTERN (prev))
720 && (next = try_combine (insn, XEXP (links, 0),
721 prev, &new_direct_jump_p)) != 0)
725 /* Try combining an insn with two different insns whose results it
727 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
728 for (nextlinks = XEXP (links, 1); nextlinks;
729 nextlinks = XEXP (nextlinks, 1))
730 if ((next = try_combine (insn, XEXP (links, 0),
732 &new_direct_jump_p)) != 0)
735 if (GET_CODE (insn) != NOTE)
736 record_dead_and_set_regs (insn);
744 EXECUTE_IF_SET_IN_SBITMAP (refresh_blocks, 0, this_basic_block,
745 BASIC_BLOCK (this_basic_block)->flags |= BB_DIRTY);
746 new_direct_jump_p |= purge_all_dead_edges (0);
747 delete_noop_moves (f);
749 update_life_info_in_dirty_blocks (UPDATE_LIFE_GLOBAL_RM_NOTES,
750 PROP_DEATH_NOTES | PROP_SCAN_DEAD_CODE
751 | PROP_KILL_DEAD_CODE);
754 sbitmap_free (refresh_blocks);
755 free (reg_nonzero_bits);
756 free (reg_sign_bit_copies);
757 free (reg_last_death);
759 free (reg_last_set_value);
760 free (reg_last_set_table_tick);
761 free (reg_last_set_label);
762 free (reg_last_set_invalid);
763 free (reg_last_set_mode);
764 free (reg_last_set_nonzero_bits);
765 free (reg_last_set_sign_bit_copies);
769 struct undo *undo, *next;
770 for (undo = undobuf.frees; undo; undo = next)
778 total_attempts += combine_attempts;
779 total_merges += combine_merges;
780 total_extras += combine_extras;
781 total_successes += combine_successes;
783 nonzero_sign_valid = 0;
785 /* Make recognizer allow volatile MEMs again. */
788 return new_direct_jump_p;
791 /* Wipe the reg_last_xxx arrays in preparation for another pass. */
794 init_reg_last_arrays ()
796 unsigned int nregs = combine_max_regno;
798 memset ((char *) reg_last_death, 0, nregs * sizeof (rtx));
799 memset ((char *) reg_last_set, 0, nregs * sizeof (rtx));
800 memset ((char *) reg_last_set_value, 0, nregs * sizeof (rtx));
801 memset ((char *) reg_last_set_table_tick, 0, nregs * sizeof (int));
802 memset ((char *) reg_last_set_label, 0, nregs * sizeof (int));
803 memset (reg_last_set_invalid, 0, nregs * sizeof (char));
804 memset ((char *) reg_last_set_mode, 0, nregs * sizeof (enum machine_mode));
805 memset ((char *) reg_last_set_nonzero_bits, 0, nregs * sizeof (HOST_WIDE_INT));
806 memset (reg_last_set_sign_bit_copies, 0, nregs * sizeof (char));
809 /* Set up any promoted values for incoming argument registers. */
812 setup_incoming_promotions ()
814 #ifdef PROMOTE_FUNCTION_ARGS
817 enum machine_mode mode;
819 rtx first = get_insns ();
821 #ifndef OUTGOING_REGNO
822 #define OUTGOING_REGNO(N) N
824 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
825 /* Check whether this register can hold an incoming pointer
826 argument. FUNCTION_ARG_REGNO_P tests outgoing register
827 numbers, so translate if necessary due to register windows. */
828 if (FUNCTION_ARG_REGNO_P (OUTGOING_REGNO (regno))
829 && (reg = promoted_input_arg (regno, &mode, &unsignedp)) != 0)
832 (reg, first, gen_rtx_fmt_e ((unsignedp ? ZERO_EXTEND
835 gen_rtx_CLOBBER (mode, const0_rtx)));
840 /* Called via note_stores. If X is a pseudo that is narrower than
841 HOST_BITS_PER_WIDE_INT and is being set, record what bits are known zero.
843 If we are setting only a portion of X and we can't figure out what
844 portion, assume all bits will be used since we don't know what will
847 Similarly, set how many bits of X are known to be copies of the sign bit
848 at all locations in the function. This is the smallest number implied
852 set_nonzero_bits_and_sign_copies (x, set, data)
855 void *data ATTRIBUTE_UNUSED;
859 if (GET_CODE (x) == REG
860 && REGNO (x) >= FIRST_PSEUDO_REGISTER
861 /* If this register is undefined at the start of the file, we can't
862 say what its contents were. */
863 && ! REGNO_REG_SET_P (BASIC_BLOCK (0)->global_live_at_start, REGNO (x))
864 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT)
866 if (set == 0 || GET_CODE (set) == CLOBBER)
868 reg_nonzero_bits[REGNO (x)] = GET_MODE_MASK (GET_MODE (x));
869 reg_sign_bit_copies[REGNO (x)] = 1;
873 /* If this is a complex assignment, see if we can convert it into a
874 simple assignment. */
875 set = expand_field_assignment (set);
877 /* If this is a simple assignment, or we have a paradoxical SUBREG,
878 set what we know about X. */
880 if (SET_DEST (set) == x
881 || (GET_CODE (SET_DEST (set)) == SUBREG
882 && (GET_MODE_SIZE (GET_MODE (SET_DEST (set)))
883 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (set)))))
884 && SUBREG_REG (SET_DEST (set)) == x))
886 rtx src = SET_SRC (set);
888 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
889 /* If X is narrower than a word and SRC is a non-negative
890 constant that would appear negative in the mode of X,
891 sign-extend it for use in reg_nonzero_bits because some
892 machines (maybe most) will actually do the sign-extension
893 and this is the conservative approach.
895 ??? For 2.5, try to tighten up the MD files in this regard
896 instead of this kludge. */
898 if (GET_MODE_BITSIZE (GET_MODE (x)) < BITS_PER_WORD
899 && GET_CODE (src) == CONST_INT
901 && 0 != (INTVAL (src)
903 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
904 src = GEN_INT (INTVAL (src)
905 | ((HOST_WIDE_INT) (-1)
906 << GET_MODE_BITSIZE (GET_MODE (x))));
909 reg_nonzero_bits[REGNO (x)]
910 |= nonzero_bits (src, nonzero_bits_mode);
911 num = num_sign_bit_copies (SET_SRC (set), GET_MODE (x));
912 if (reg_sign_bit_copies[REGNO (x)] == 0
913 || reg_sign_bit_copies[REGNO (x)] > num)
914 reg_sign_bit_copies[REGNO (x)] = num;
918 reg_nonzero_bits[REGNO (x)] = GET_MODE_MASK (GET_MODE (x));
919 reg_sign_bit_copies[REGNO (x)] = 1;
924 /* See if INSN can be combined into I3. PRED and SUCC are optionally
925 insns that were previously combined into I3 or that will be combined
926 into the merger of INSN and I3.
928 Return 0 if the combination is not allowed for any reason.
930 If the combination is allowed, *PDEST will be set to the single
931 destination of INSN and *PSRC to the single source, and this function
935 can_combine_p (insn, i3, pred, succ, pdest, psrc)
938 rtx pred ATTRIBUTE_UNUSED;
943 rtx set = 0, src, dest;
948 int all_adjacent = (succ ? (next_active_insn (insn) == succ
949 && next_active_insn (succ) == i3)
950 : next_active_insn (insn) == i3);
952 /* Can combine only if previous insn is a SET of a REG, a SUBREG or CC0.
953 or a PARALLEL consisting of such a SET and CLOBBERs.
955 If INSN has CLOBBER parallel parts, ignore them for our processing.
956 By definition, these happen during the execution of the insn. When it
957 is merged with another insn, all bets are off. If they are, in fact,
958 needed and aren't also supplied in I3, they may be added by
959 recog_for_combine. Otherwise, it won't match.
961 We can also ignore a SET whose SET_DEST is mentioned in a REG_UNUSED
964 Get the source and destination of INSN. If more than one, can't
967 if (GET_CODE (PATTERN (insn)) == SET)
968 set = PATTERN (insn);
969 else if (GET_CODE (PATTERN (insn)) == PARALLEL
970 && GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == SET)
972 for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
974 rtx elt = XVECEXP (PATTERN (insn), 0, i);
976 switch (GET_CODE (elt))
978 /* This is important to combine floating point insns
981 /* Combining an isolated USE doesn't make sense.
982 We depend here on combinable_i3pat to reject them. */
983 /* The code below this loop only verifies that the inputs of
984 the SET in INSN do not change. We call reg_set_between_p
985 to verify that the REG in the USE does not change between
987 If the USE in INSN was for a pseudo register, the matching
988 insn pattern will likely match any register; combining this
989 with any other USE would only be safe if we knew that the
990 used registers have identical values, or if there was
991 something to tell them apart, e.g. different modes. For
992 now, we forgo such complicated tests and simply disallow
993 combining of USES of pseudo registers with any other USE. */
994 if (GET_CODE (XEXP (elt, 0)) == REG
995 && GET_CODE (PATTERN (i3)) == PARALLEL)
997 rtx i3pat = PATTERN (i3);
998 int i = XVECLEN (i3pat, 0) - 1;
999 unsigned int regno = REGNO (XEXP (elt, 0));
1003 rtx i3elt = XVECEXP (i3pat, 0, i);
1005 if (GET_CODE (i3elt) == USE
1006 && GET_CODE (XEXP (i3elt, 0)) == REG
1007 && (REGNO (XEXP (i3elt, 0)) == regno
1008 ? reg_set_between_p (XEXP (elt, 0),
1009 PREV_INSN (insn), i3)
1010 : regno >= FIRST_PSEUDO_REGISTER))
1017 /* We can ignore CLOBBERs. */
1022 /* Ignore SETs whose result isn't used but not those that
1023 have side-effects. */
1024 if (find_reg_note (insn, REG_UNUSED, SET_DEST (elt))
1025 && ! side_effects_p (elt))
1028 /* If we have already found a SET, this is a second one and
1029 so we cannot combine with this insn. */
1037 /* Anything else means we can't combine. */
1043 /* If SET_SRC is an ASM_OPERANDS we can't throw away these CLOBBERs,
1044 so don't do anything with it. */
1045 || GET_CODE (SET_SRC (set)) == ASM_OPERANDS)
1054 set = expand_field_assignment (set);
1055 src = SET_SRC (set), dest = SET_DEST (set);
1057 /* Don't eliminate a store in the stack pointer. */
1058 if (dest == stack_pointer_rtx
1059 /* If we couldn't eliminate a field assignment, we can't combine. */
1060 || GET_CODE (dest) == ZERO_EXTRACT || GET_CODE (dest) == STRICT_LOW_PART
1061 /* Don't combine with an insn that sets a register to itself if it has
1062 a REG_EQUAL note. This may be part of a REG_NO_CONFLICT sequence. */
1063 || (rtx_equal_p (src, dest) && find_reg_note (insn, REG_EQUAL, NULL_RTX))
1064 /* Can't merge an ASM_OPERANDS. */
1065 || GET_CODE (src) == ASM_OPERANDS
1066 /* Can't merge a function call. */
1067 || GET_CODE (src) == CALL
1068 /* Don't eliminate a function call argument. */
1069 || (GET_CODE (i3) == CALL_INSN
1070 && (find_reg_fusage (i3, USE, dest)
1071 || (GET_CODE (dest) == REG
1072 && REGNO (dest) < FIRST_PSEUDO_REGISTER
1073 && global_regs[REGNO (dest)])))
1074 /* Don't substitute into an incremented register. */
1075 || FIND_REG_INC_NOTE (i3, dest)
1076 || (succ && FIND_REG_INC_NOTE (succ, dest))
1078 /* Don't combine the end of a libcall into anything. */
1079 /* ??? This gives worse code, and appears to be unnecessary, since no
1080 pass after flow uses REG_LIBCALL/REG_RETVAL notes. Local-alloc does
1081 use REG_RETVAL notes for noconflict blocks, but other code here
1082 makes sure that those insns don't disappear. */
1083 || find_reg_note (insn, REG_RETVAL, NULL_RTX)
1085 /* Make sure that DEST is not used after SUCC but before I3. */
1086 || (succ && ! all_adjacent
1087 && reg_used_between_p (dest, succ, i3))
1088 /* Make sure that the value that is to be substituted for the register
1089 does not use any registers whose values alter in between. However,
1090 If the insns are adjacent, a use can't cross a set even though we
1091 think it might (this can happen for a sequence of insns each setting
1092 the same destination; reg_last_set of that register might point to
1093 a NOTE). If INSN has a REG_EQUIV note, the register is always
1094 equivalent to the memory so the substitution is valid even if there
1095 are intervening stores. Also, don't move a volatile asm or
1096 UNSPEC_VOLATILE across any other insns. */
1098 && (((GET_CODE (src) != MEM
1099 || ! find_reg_note (insn, REG_EQUIV, src))
1100 && use_crosses_set_p (src, INSN_CUID (insn)))
1101 || (GET_CODE (src) == ASM_OPERANDS && MEM_VOLATILE_P (src))
1102 || GET_CODE (src) == UNSPEC_VOLATILE))
1103 /* If there is a REG_NO_CONFLICT note for DEST in I3 or SUCC, we get
1104 better register allocation by not doing the combine. */
1105 || find_reg_note (i3, REG_NO_CONFLICT, dest)
1106 || (succ && find_reg_note (succ, REG_NO_CONFLICT, dest))
1107 /* Don't combine across a CALL_INSN, because that would possibly
1108 change whether the life span of some REGs crosses calls or not,
1109 and it is a pain to update that information.
1110 Exception: if source is a constant, moving it later can't hurt.
1111 Accept that special case, because it helps -fforce-addr a lot. */
1112 || (INSN_CUID (insn) < last_call_cuid && ! CONSTANT_P (src)))
1115 /* DEST must either be a REG or CC0. */
1116 if (GET_CODE (dest) == REG)
1118 /* If register alignment is being enforced for multi-word items in all
1119 cases except for parameters, it is possible to have a register copy
1120 insn referencing a hard register that is not allowed to contain the
1121 mode being copied and which would not be valid as an operand of most
1122 insns. Eliminate this problem by not combining with such an insn.
1124 Also, on some machines we don't want to extend the life of a hard
1127 if (GET_CODE (src) == REG
1128 && ((REGNO (dest) < FIRST_PSEUDO_REGISTER
1129 && ! HARD_REGNO_MODE_OK (REGNO (dest), GET_MODE (dest)))
1130 /* Don't extend the life of a hard register unless it is
1131 user variable (if we have few registers) or it can't
1132 fit into the desired register (meaning something special
1134 Also avoid substituting a return register into I3, because
1135 reload can't handle a conflict with constraints of other
1137 || (REGNO (src) < FIRST_PSEUDO_REGISTER
1138 && ! HARD_REGNO_MODE_OK (REGNO (src), GET_MODE (src)))))
1141 else if (GET_CODE (dest) != CC0)
1144 /* Don't substitute for a register intended as a clobberable operand.
1145 Similarly, don't substitute an expression containing a register that
1146 will be clobbered in I3. */
1147 if (GET_CODE (PATTERN (i3)) == PARALLEL)
1148 for (i = XVECLEN (PATTERN (i3), 0) - 1; i >= 0; i--)
1149 if (GET_CODE (XVECEXP (PATTERN (i3), 0, i)) == CLOBBER
1150 && (reg_overlap_mentioned_p (XEXP (XVECEXP (PATTERN (i3), 0, i), 0),
1152 || rtx_equal_p (XEXP (XVECEXP (PATTERN (i3), 0, i), 0), dest)))
1155 /* If INSN contains anything volatile, or is an `asm' (whether volatile
1156 or not), reject, unless nothing volatile comes between it and I3 */
1158 if (GET_CODE (src) == ASM_OPERANDS || volatile_refs_p (src))
1160 /* Make sure succ doesn't contain a volatile reference. */
1161 if (succ != 0 && volatile_refs_p (PATTERN (succ)))
1164 for (p = NEXT_INSN (insn); p != i3; p = NEXT_INSN (p))
1165 if (INSN_P (p) && p != succ && volatile_refs_p (PATTERN (p)))
1169 /* If INSN is an asm, and DEST is a hard register, reject, since it has
1170 to be an explicit register variable, and was chosen for a reason. */
1172 if (GET_CODE (src) == ASM_OPERANDS
1173 && GET_CODE (dest) == REG && REGNO (dest) < FIRST_PSEUDO_REGISTER)
1176 /* If there are any volatile insns between INSN and I3, reject, because
1177 they might affect machine state. */
1179 for (p = NEXT_INSN (insn); p != i3; p = NEXT_INSN (p))
1180 if (INSN_P (p) && p != succ && volatile_insn_p (PATTERN (p)))
1183 /* If INSN or I2 contains an autoincrement or autodecrement,
1184 make sure that register is not used between there and I3,
1185 and not already used in I3 either.
1186 Also insist that I3 not be a jump; if it were one
1187 and the incremented register were spilled, we would lose. */
1190 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
1191 if (REG_NOTE_KIND (link) == REG_INC
1192 && (GET_CODE (i3) == JUMP_INSN
1193 || reg_used_between_p (XEXP (link, 0), insn, i3)
1194 || reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i3))))
1199 /* Don't combine an insn that follows a CC0-setting insn.
1200 An insn that uses CC0 must not be separated from the one that sets it.
1201 We do, however, allow I2 to follow a CC0-setting insn if that insn
1202 is passed as I1; in that case it will be deleted also.
1203 We also allow combining in this case if all the insns are adjacent
1204 because that would leave the two CC0 insns adjacent as well.
1205 It would be more logical to test whether CC0 occurs inside I1 or I2,
1206 but that would be much slower, and this ought to be equivalent. */
1208 p = prev_nonnote_insn (insn);
1209 if (p && p != pred && GET_CODE (p) == INSN && sets_cc0_p (PATTERN (p))
1214 /* If we get here, we have passed all the tests and the combination is
1223 /* Check if PAT is an insn - or a part of it - used to set up an
1224 argument for a function in a hard register. */
1227 sets_function_arg_p (pat)
1233 switch (GET_CODE (pat))
1236 return sets_function_arg_p (PATTERN (pat));
1239 for (i = XVECLEN (pat, 0); --i >= 0;)
1240 if (sets_function_arg_p (XVECEXP (pat, 0, i)))
1246 inner_dest = SET_DEST (pat);
1247 while (GET_CODE (inner_dest) == STRICT_LOW_PART
1248 || GET_CODE (inner_dest) == SUBREG
1249 || GET_CODE (inner_dest) == ZERO_EXTRACT)
1250 inner_dest = XEXP (inner_dest, 0);
1252 return (GET_CODE (inner_dest) == REG
1253 && REGNO (inner_dest) < FIRST_PSEUDO_REGISTER
1254 && FUNCTION_ARG_REGNO_P (REGNO (inner_dest)));
1263 /* LOC is the location within I3 that contains its pattern or the component
1264 of a PARALLEL of the pattern. We validate that it is valid for combining.
1266 One problem is if I3 modifies its output, as opposed to replacing it
1267 entirely, we can't allow the output to contain I2DEST or I1DEST as doing
1268 so would produce an insn that is not equivalent to the original insns.
1272 (set (reg:DI 101) (reg:DI 100))
1273 (set (subreg:SI (reg:DI 101) 0) <foo>)
1275 This is NOT equivalent to:
1277 (parallel [(set (subreg:SI (reg:DI 100) 0) <foo>)
1278 (set (reg:DI 101) (reg:DI 100))])
1280 Not only does this modify 100 (in which case it might still be valid
1281 if 100 were dead in I2), it sets 101 to the ORIGINAL value of 100.
1283 We can also run into a problem if I2 sets a register that I1
1284 uses and I1 gets directly substituted into I3 (not via I2). In that
1285 case, we would be getting the wrong value of I2DEST into I3, so we
1286 must reject the combination. This case occurs when I2 and I1 both
1287 feed into I3, rather than when I1 feeds into I2, which feeds into I3.
1288 If I1_NOT_IN_SRC is non-zero, it means that finding I1 in the source
1289 of a SET must prevent combination from occurring.
1291 Before doing the above check, we first try to expand a field assignment
1292 into a set of logical operations.
1294 If PI3_DEST_KILLED is non-zero, it is a pointer to a location in which
1295 we place a register that is both set and used within I3. If more than one
1296 such register is detected, we fail.
1298 Return 1 if the combination is valid, zero otherwise. */
1301 combinable_i3pat (i3, loc, i2dest, i1dest, i1_not_in_src, pi3dest_killed)
1307 rtx *pi3dest_killed;
1311 if (GET_CODE (x) == SET)
1313 rtx set = expand_field_assignment (x);
1314 rtx dest = SET_DEST (set);
1315 rtx src = SET_SRC (set);
1316 rtx inner_dest = dest;
1319 rtx inner_src = src;
1324 while (GET_CODE (inner_dest) == STRICT_LOW_PART
1325 || GET_CODE (inner_dest) == SUBREG
1326 || GET_CODE (inner_dest) == ZERO_EXTRACT)
1327 inner_dest = XEXP (inner_dest, 0);
1329 /* We probably don't need this any more now that LIMIT_RELOAD_CLASS
1332 while (GET_CODE (inner_src) == STRICT_LOW_PART
1333 || GET_CODE (inner_src) == SUBREG
1334 || GET_CODE (inner_src) == ZERO_EXTRACT)
1335 inner_src = XEXP (inner_src, 0);
1337 /* If it is better that two different modes keep two different pseudos,
1338 avoid combining them. This avoids producing the following pattern
1340 (set (subreg:SI (reg/v:QI 21) 0)
1341 (lshiftrt:SI (reg/v:SI 20)
1343 If that were made, reload could not handle the pair of
1344 reg 20/21, since it would try to get any GENERAL_REGS
1345 but some of them don't handle QImode. */
1347 if (rtx_equal_p (inner_src, i2dest)
1348 && GET_CODE (inner_dest) == REG
1349 && ! MODES_TIEABLE_P (GET_MODE (i2dest), GET_MODE (inner_dest)))
1353 /* Check for the case where I3 modifies its output, as
1355 if ((inner_dest != dest
1356 && (reg_overlap_mentioned_p (i2dest, inner_dest)
1357 || (i1dest && reg_overlap_mentioned_p (i1dest, inner_dest))))
1359 /* This is the same test done in can_combine_p except we can't test
1360 all_adjacent; we don't have to, since this instruction will stay
1361 in place, thus we are not considering increasing the lifetime of
1364 Also, if this insn sets a function argument, combining it with
1365 something that might need a spill could clobber a previous
1366 function argument; the all_adjacent test in can_combine_p also
1367 checks this; here, we do a more specific test for this case. */
1369 || (GET_CODE (inner_dest) == REG
1370 && REGNO (inner_dest) < FIRST_PSEUDO_REGISTER
1371 && (! HARD_REGNO_MODE_OK (REGNO (inner_dest),
1372 GET_MODE (inner_dest))))
1373 || (i1_not_in_src && reg_overlap_mentioned_p (i1dest, src)))
1376 /* If DEST is used in I3, it is being killed in this insn,
1377 so record that for later.
1378 Never add REG_DEAD notes for the FRAME_POINTER_REGNUM or the
1379 STACK_POINTER_REGNUM, since these are always considered to be
1380 live. Similarly for ARG_POINTER_REGNUM if it is fixed. */
1381 if (pi3dest_killed && GET_CODE (dest) == REG
1382 && reg_referenced_p (dest, PATTERN (i3))
1383 && REGNO (dest) != FRAME_POINTER_REGNUM
1384 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
1385 && REGNO (dest) != HARD_FRAME_POINTER_REGNUM
1387 #if ARG_POINTER_REGNUM != FRAME_POINTER_REGNUM
1388 && (REGNO (dest) != ARG_POINTER_REGNUM
1389 || ! fixed_regs [REGNO (dest)])
1391 && REGNO (dest) != STACK_POINTER_REGNUM)
1393 if (*pi3dest_killed)
1396 *pi3dest_killed = dest;
1400 else if (GET_CODE (x) == PARALLEL)
1404 for (i = 0; i < XVECLEN (x, 0); i++)
1405 if (! combinable_i3pat (i3, &XVECEXP (x, 0, i), i2dest, i1dest,
1406 i1_not_in_src, pi3dest_killed))
1413 /* Return 1 if X is an arithmetic expression that contains a multiplication
1414 and division. We don't count multiplications by powers of two here. */
1420 switch (GET_CODE (x))
1422 case MOD: case DIV: case UMOD: case UDIV:
1426 return ! (GET_CODE (XEXP (x, 1)) == CONST_INT
1427 && exact_log2 (INTVAL (XEXP (x, 1))) >= 0);
1429 switch (GET_RTX_CLASS (GET_CODE (x)))
1431 case 'c': case '<': case '2':
1432 return contains_muldiv (XEXP (x, 0))
1433 || contains_muldiv (XEXP (x, 1));
1436 return contains_muldiv (XEXP (x, 0));
1444 /* Determine whether INSN can be used in a combination. Return nonzero if
1445 not. This is used in try_combine to detect early some cases where we
1446 can't perform combinations. */
1449 cant_combine_insn_p (insn)
1455 /* If this isn't really an insn, we can't do anything.
1456 This can occur when flow deletes an insn that it has merged into an
1457 auto-increment address. */
1458 if (! INSN_P (insn))
1461 /* Never combine loads and stores involving hard regs. The register
1462 allocator can usually handle such reg-reg moves by tying. If we allow
1463 the combiner to make substitutions of hard regs, we risk aborting in
1464 reload on machines that have SMALL_REGISTER_CLASSES.
1465 As an exception, we allow combinations involving fixed regs; these are
1466 not available to the register allocator so there's no risk involved. */
1468 set = single_set (insn);
1471 src = SET_SRC (set);
1472 dest = SET_DEST (set);
1473 if (GET_CODE (src) == SUBREG)
1474 src = SUBREG_REG (src);
1475 if (GET_CODE (dest) == SUBREG)
1476 dest = SUBREG_REG (dest);
1477 if (REG_P (src) && REG_P (dest)
1478 && ((REGNO (src) < FIRST_PSEUDO_REGISTER
1479 && ! fixed_regs[REGNO (src)])
1480 || (REGNO (dest) < FIRST_PSEUDO_REGISTER
1481 && ! fixed_regs[REGNO (dest)])))
1487 /* Try to combine the insns I1 and I2 into I3.
1488 Here I1 and I2 appear earlier than I3.
1489 I1 can be zero; then we combine just I2 into I3.
1491 If we are combining three insns and the resulting insn is not recognized,
1492 try splitting it into two insns. If that happens, I2 and I3 are retained
1493 and I1 is pseudo-deleted by turning it into a NOTE. Otherwise, I1 and I2
1496 Return 0 if the combination does not work. Then nothing is changed.
1497 If we did the combination, return the insn at which combine should
1500 Set NEW_DIRECT_JUMP_P to a non-zero value if try_combine creates a
1501 new direct jump instruction. */
1504 try_combine (i3, i2, i1, new_direct_jump_p)
1506 int *new_direct_jump_p;
1508 /* New patterns for I3 and I2, respectively. */
1509 rtx newpat, newi2pat = 0;
1510 int substed_i2 = 0, substed_i1 = 0;
1511 /* Indicates need to preserve SET in I1 or I2 in I3 if it is not dead. */
1512 int added_sets_1, added_sets_2;
1513 /* Total number of SETs to put into I3. */
1515 /* Nonzero is I2's body now appears in I3. */
1517 /* INSN_CODEs for new I3, new I2, and user of condition code. */
1518 int insn_code_number, i2_code_number = 0, other_code_number = 0;
1519 /* Contains I3 if the destination of I3 is used in its source, which means
1520 that the old life of I3 is being killed. If that usage is placed into
1521 I2 and not in I3, a REG_DEAD note must be made. */
1522 rtx i3dest_killed = 0;
1523 /* SET_DEST and SET_SRC of I2 and I1. */
1524 rtx i2dest, i2src, i1dest = 0, i1src = 0;
1525 /* PATTERN (I2), or a copy of it in certain cases. */
1527 /* Indicates if I2DEST or I1DEST is in I2SRC or I1_SRC. */
1528 int i2dest_in_i2src = 0, i1dest_in_i1src = 0, i2dest_in_i1src = 0;
1529 int i1_feeds_i3 = 0;
1530 /* Notes that must be added to REG_NOTES in I3 and I2. */
1531 rtx new_i3_notes, new_i2_notes;
1532 /* Notes that we substituted I3 into I2 instead of the normal case. */
1533 int i3_subst_into_i2 = 0;
1534 /* Notes that I1, I2 or I3 is a MULT operation. */
1542 /* Exit early if one of the insns involved can't be used for
1544 if (cant_combine_insn_p (i3)
1545 || cant_combine_insn_p (i2)
1546 || (i1 && cant_combine_insn_p (i1))
1547 /* We also can't do anything if I3 has a
1548 REG_LIBCALL note since we don't want to disrupt the contiguity of a
1551 /* ??? This gives worse code, and appears to be unnecessary, since no
1552 pass after flow uses REG_LIBCALL/REG_RETVAL notes. */
1553 || find_reg_note (i3, REG_LIBCALL, NULL_RTX)
1559 undobuf.other_insn = 0;
1561 /* Reset the hard register usage information. */
1562 CLEAR_HARD_REG_SET (newpat_used_regs);
1564 /* If I1 and I2 both feed I3, they can be in any order. To simplify the
1565 code below, set I1 to be the earlier of the two insns. */
1566 if (i1 && INSN_CUID (i1) > INSN_CUID (i2))
1567 temp = i1, i1 = i2, i2 = temp;
1569 added_links_insn = 0;
1571 /* First check for one important special-case that the code below will
1572 not handle. Namely, the case where I1 is zero, I2 is a PARALLEL
1573 and I3 is a SET whose SET_SRC is a SET_DEST in I2. In that case,
1574 we may be able to replace that destination with the destination of I3.
1575 This occurs in the common code where we compute both a quotient and
1576 remainder into a structure, in which case we want to do the computation
1577 directly into the structure to avoid register-register copies.
1579 Note that this case handles both multiple sets in I2 and also
1580 cases where I2 has a number of CLOBBER or PARALLELs.
1582 We make very conservative checks below and only try to handle the
1583 most common cases of this. For example, we only handle the case
1584 where I2 and I3 are adjacent to avoid making difficult register
1587 if (i1 == 0 && GET_CODE (i3) == INSN && GET_CODE (PATTERN (i3)) == SET
1588 && GET_CODE (SET_SRC (PATTERN (i3))) == REG
1589 && REGNO (SET_SRC (PATTERN (i3))) >= FIRST_PSEUDO_REGISTER
1590 && find_reg_note (i3, REG_DEAD, SET_SRC (PATTERN (i3)))
1591 && GET_CODE (PATTERN (i2)) == PARALLEL
1592 && ! side_effects_p (SET_DEST (PATTERN (i3)))
1593 /* If the dest of I3 is a ZERO_EXTRACT or STRICT_LOW_PART, the code
1594 below would need to check what is inside (and reg_overlap_mentioned_p
1595 doesn't support those codes anyway). Don't allow those destinations;
1596 the resulting insn isn't likely to be recognized anyway. */
1597 && GET_CODE (SET_DEST (PATTERN (i3))) != ZERO_EXTRACT
1598 && GET_CODE (SET_DEST (PATTERN (i3))) != STRICT_LOW_PART
1599 && ! reg_overlap_mentioned_p (SET_SRC (PATTERN (i3)),
1600 SET_DEST (PATTERN (i3)))
1601 && next_real_insn (i2) == i3)
1603 rtx p2 = PATTERN (i2);
1605 /* Make sure that the destination of I3,
1606 which we are going to substitute into one output of I2,
1607 is not used within another output of I2. We must avoid making this:
1608 (parallel [(set (mem (reg 69)) ...)
1609 (set (reg 69) ...)])
1610 which is not well-defined as to order of actions.
1611 (Besides, reload can't handle output reloads for this.)
1613 The problem can also happen if the dest of I3 is a memory ref,
1614 if another dest in I2 is an indirect memory ref. */
1615 for (i = 0; i < XVECLEN (p2, 0); i++)
1616 if ((GET_CODE (XVECEXP (p2, 0, i)) == SET
1617 || GET_CODE (XVECEXP (p2, 0, i)) == CLOBBER)
1618 && reg_overlap_mentioned_p (SET_DEST (PATTERN (i3)),
1619 SET_DEST (XVECEXP (p2, 0, i))))
1622 if (i == XVECLEN (p2, 0))
1623 for (i = 0; i < XVECLEN (p2, 0); i++)
1624 if ((GET_CODE (XVECEXP (p2, 0, i)) == SET
1625 || GET_CODE (XVECEXP (p2, 0, i)) == CLOBBER)
1626 && SET_DEST (XVECEXP (p2, 0, i)) == SET_SRC (PATTERN (i3)))
1631 subst_low_cuid = INSN_CUID (i2);
1633 added_sets_2 = added_sets_1 = 0;
1634 i2dest = SET_SRC (PATTERN (i3));
1636 /* Replace the dest in I2 with our dest and make the resulting
1637 insn the new pattern for I3. Then skip to where we
1638 validate the pattern. Everything was set up above. */
1639 SUBST (SET_DEST (XVECEXP (p2, 0, i)),
1640 SET_DEST (PATTERN (i3)));
1643 i3_subst_into_i2 = 1;
1644 goto validate_replacement;
1648 /* If I2 is setting a double-word pseudo to a constant and I3 is setting
1649 one of those words to another constant, merge them by making a new
1652 && (temp = single_set (i2)) != 0
1653 && (GET_CODE (SET_SRC (temp)) == CONST_INT
1654 || GET_CODE (SET_SRC (temp)) == CONST_DOUBLE)
1655 && GET_CODE (SET_DEST (temp)) == REG
1656 && GET_MODE_CLASS (GET_MODE (SET_DEST (temp))) == MODE_INT
1657 && GET_MODE_SIZE (GET_MODE (SET_DEST (temp))) == 2 * UNITS_PER_WORD
1658 && GET_CODE (PATTERN (i3)) == SET
1659 && GET_CODE (SET_DEST (PATTERN (i3))) == SUBREG
1660 && SUBREG_REG (SET_DEST (PATTERN (i3))) == SET_DEST (temp)
1661 && GET_MODE_CLASS (GET_MODE (SET_DEST (PATTERN (i3)))) == MODE_INT
1662 && GET_MODE_SIZE (GET_MODE (SET_DEST (PATTERN (i3)))) == UNITS_PER_WORD
1663 && GET_CODE (SET_SRC (PATTERN (i3))) == CONST_INT)
1665 HOST_WIDE_INT lo, hi;
1667 if (GET_CODE (SET_SRC (temp)) == CONST_INT)
1668 lo = INTVAL (SET_SRC (temp)), hi = lo < 0 ? -1 : 0;
1671 lo = CONST_DOUBLE_LOW (SET_SRC (temp));
1672 hi = CONST_DOUBLE_HIGH (SET_SRC (temp));
1675 if (subreg_lowpart_p (SET_DEST (PATTERN (i3))))
1677 /* We don't handle the case of the target word being wider
1678 than a host wide int. */
1679 if (HOST_BITS_PER_WIDE_INT < BITS_PER_WORD)
1682 lo &= ~(UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD (1) - 1);
1683 lo |= (INTVAL (SET_SRC (PATTERN (i3)))
1684 & (UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD (1) - 1));
1686 else if (HOST_BITS_PER_WIDE_INT == BITS_PER_WORD)
1687 hi = INTVAL (SET_SRC (PATTERN (i3)));
1688 else if (HOST_BITS_PER_WIDE_INT >= 2 * BITS_PER_WORD)
1690 int sign = -(int) ((unsigned HOST_WIDE_INT) lo
1691 >> (HOST_BITS_PER_WIDE_INT - 1));
1693 lo &= ~ (UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD
1694 (UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD (1) - 1));
1695 lo |= (UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD
1696 (INTVAL (SET_SRC (PATTERN (i3)))));
1698 hi = lo < 0 ? -1 : 0;
1701 /* We don't handle the case of the higher word not fitting
1702 entirely in either hi or lo. */
1707 subst_low_cuid = INSN_CUID (i2);
1708 added_sets_2 = added_sets_1 = 0;
1709 i2dest = SET_DEST (temp);
1711 SUBST (SET_SRC (temp),
1712 immed_double_const (lo, hi, GET_MODE (SET_DEST (temp))));
1714 newpat = PATTERN (i2);
1715 goto validate_replacement;
1719 /* If we have no I1 and I2 looks like:
1720 (parallel [(set (reg:CC X) (compare:CC OP (const_int 0)))
1722 make up a dummy I1 that is
1725 (set (reg:CC X) (compare:CC Y (const_int 0)))
1727 (We can ignore any trailing CLOBBERs.)
1729 This undoes a previous combination and allows us to match a branch-and-
1732 if (i1 == 0 && GET_CODE (PATTERN (i2)) == PARALLEL
1733 && XVECLEN (PATTERN (i2), 0) >= 2
1734 && GET_CODE (XVECEXP (PATTERN (i2), 0, 0)) == SET
1735 && (GET_MODE_CLASS (GET_MODE (SET_DEST (XVECEXP (PATTERN (i2), 0, 0))))
1737 && GET_CODE (SET_SRC (XVECEXP (PATTERN (i2), 0, 0))) == COMPARE
1738 && XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 1) == const0_rtx
1739 && GET_CODE (XVECEXP (PATTERN (i2), 0, 1)) == SET
1740 && GET_CODE (SET_DEST (XVECEXP (PATTERN (i2), 0, 1))) == REG
1741 && rtx_equal_p (XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 0),
1742 SET_SRC (XVECEXP (PATTERN (i2), 0, 1))))
1744 for (i = XVECLEN (PATTERN (i2), 0) - 1; i >= 2; i--)
1745 if (GET_CODE (XVECEXP (PATTERN (i2), 0, i)) != CLOBBER)
1750 /* We make I1 with the same INSN_UID as I2. This gives it
1751 the same INSN_CUID for value tracking. Our fake I1 will
1752 never appear in the insn stream so giving it the same INSN_UID
1753 as I2 will not cause a problem. */
1755 subst_prev_insn = i1
1756 = gen_rtx_INSN (VOIDmode, INSN_UID (i2), NULL_RTX, i2,
1757 XVECEXP (PATTERN (i2), 0, 1), -1, NULL_RTX,
1760 SUBST (PATTERN (i2), XVECEXP (PATTERN (i2), 0, 0));
1761 SUBST (XEXP (SET_SRC (PATTERN (i2)), 0),
1762 SET_DEST (PATTERN (i1)));
1767 /* Verify that I2 and I1 are valid for combining. */
1768 if (! can_combine_p (i2, i3, i1, NULL_RTX, &i2dest, &i2src)
1769 || (i1 && ! can_combine_p (i1, i3, NULL_RTX, i2, &i1dest, &i1src)))
1775 /* Record whether I2DEST is used in I2SRC and similarly for the other
1776 cases. Knowing this will help in register status updating below. */
1777 i2dest_in_i2src = reg_overlap_mentioned_p (i2dest, i2src);
1778 i1dest_in_i1src = i1 && reg_overlap_mentioned_p (i1dest, i1src);
1779 i2dest_in_i1src = i1 && reg_overlap_mentioned_p (i2dest, i1src);
1781 /* See if I1 directly feeds into I3. It does if I1DEST is not used
1783 i1_feeds_i3 = i1 && ! reg_overlap_mentioned_p (i1dest, i2src);
1785 /* Ensure that I3's pattern can be the destination of combines. */
1786 if (! combinable_i3pat (i3, &PATTERN (i3), i2dest, i1dest,
1787 i1 && i2dest_in_i1src && i1_feeds_i3,
1794 /* See if any of the insns is a MULT operation. Unless one is, we will
1795 reject a combination that is, since it must be slower. Be conservative
1797 if (GET_CODE (i2src) == MULT
1798 || (i1 != 0 && GET_CODE (i1src) == MULT)
1799 || (GET_CODE (PATTERN (i3)) == SET
1800 && GET_CODE (SET_SRC (PATTERN (i3))) == MULT))
1803 /* If I3 has an inc, then give up if I1 or I2 uses the reg that is inc'd.
1804 We used to do this EXCEPT in one case: I3 has a post-inc in an
1805 output operand. However, that exception can give rise to insns like
1807 which is a famous insn on the PDP-11 where the value of r3 used as the
1808 source was model-dependent. Avoid this sort of thing. */
1811 if (!(GET_CODE (PATTERN (i3)) == SET
1812 && GET_CODE (SET_SRC (PATTERN (i3))) == REG
1813 && GET_CODE (SET_DEST (PATTERN (i3))) == MEM
1814 && (GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_INC
1815 || GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_DEC)))
1816 /* It's not the exception. */
1819 for (link = REG_NOTES (i3); link; link = XEXP (link, 1))
1820 if (REG_NOTE_KIND (link) == REG_INC
1821 && (reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i2))
1823 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i1)))))
1830 /* See if the SETs in I1 or I2 need to be kept around in the merged
1831 instruction: whenever the value set there is still needed past I3.
1832 For the SETs in I2, this is easy: we see if I2DEST dies or is set in I3.
1834 For the SET in I1, we have two cases: If I1 and I2 independently
1835 feed into I3, the set in I1 needs to be kept around if I1DEST dies
1836 or is set in I3. Otherwise (if I1 feeds I2 which feeds I3), the set
1837 in I1 needs to be kept around unless I1DEST dies or is set in either
1838 I2 or I3. We can distinguish these cases by seeing if I2SRC mentions
1839 I1DEST. If so, we know I1 feeds into I2. */
1841 added_sets_2 = ! dead_or_set_p (i3, i2dest);
1844 = i1 && ! (i1_feeds_i3 ? dead_or_set_p (i3, i1dest)
1845 : (dead_or_set_p (i3, i1dest) || dead_or_set_p (i2, i1dest)));
1847 /* If the set in I2 needs to be kept around, we must make a copy of
1848 PATTERN (I2), so that when we substitute I1SRC for I1DEST in
1849 PATTERN (I2), we are only substituting for the original I1DEST, not into
1850 an already-substituted copy. This also prevents making self-referential
1851 rtx. If I2 is a PARALLEL, we just need the piece that assigns I2SRC to
1854 i2pat = (GET_CODE (PATTERN (i2)) == PARALLEL
1855 ? gen_rtx_SET (VOIDmode, i2dest, i2src)
1859 i2pat = copy_rtx (i2pat);
1863 /* Substitute in the latest insn for the regs set by the earlier ones. */
1865 maxreg = max_reg_num ();
1869 /* It is possible that the source of I2 or I1 may be performing an
1870 unneeded operation, such as a ZERO_EXTEND of something that is known
1871 to have the high part zero. Handle that case by letting subst look at
1872 the innermost one of them.
1874 Another way to do this would be to have a function that tries to
1875 simplify a single insn instead of merging two or more insns. We don't
1876 do this because of the potential of infinite loops and because
1877 of the potential extra memory required. However, doing it the way
1878 we are is a bit of a kludge and doesn't catch all cases.
1880 But only do this if -fexpensive-optimizations since it slows things down
1881 and doesn't usually win. */
1883 if (flag_expensive_optimizations)
1885 /* Pass pc_rtx so no substitutions are done, just simplifications.
1886 The cases that we are interested in here do not involve the few
1887 cases were is_replaced is checked. */
1890 subst_low_cuid = INSN_CUID (i1);
1891 i1src = subst (i1src, pc_rtx, pc_rtx, 0, 0);
1895 subst_low_cuid = INSN_CUID (i2);
1896 i2src = subst (i2src, pc_rtx, pc_rtx, 0, 0);
1901 /* Many machines that don't use CC0 have insns that can both perform an
1902 arithmetic operation and set the condition code. These operations will
1903 be represented as a PARALLEL with the first element of the vector
1904 being a COMPARE of an arithmetic operation with the constant zero.
1905 The second element of the vector will set some pseudo to the result
1906 of the same arithmetic operation. If we simplify the COMPARE, we won't
1907 match such a pattern and so will generate an extra insn. Here we test
1908 for this case, where both the comparison and the operation result are
1909 needed, and make the PARALLEL by just replacing I2DEST in I3SRC with
1910 I2SRC. Later we will make the PARALLEL that contains I2. */
1912 if (i1 == 0 && added_sets_2 && GET_CODE (PATTERN (i3)) == SET
1913 && GET_CODE (SET_SRC (PATTERN (i3))) == COMPARE
1914 && XEXP (SET_SRC (PATTERN (i3)), 1) == const0_rtx
1915 && rtx_equal_p (XEXP (SET_SRC (PATTERN (i3)), 0), i2dest))
1917 #ifdef EXTRA_CC_MODES
1919 enum machine_mode compare_mode;
1922 newpat = PATTERN (i3);
1923 SUBST (XEXP (SET_SRC (newpat), 0), i2src);
1927 #ifdef EXTRA_CC_MODES
1928 /* See if a COMPARE with the operand we substituted in should be done
1929 with the mode that is currently being used. If not, do the same
1930 processing we do in `subst' for a SET; namely, if the destination
1931 is used only once, try to replace it with a register of the proper
1932 mode and also replace the COMPARE. */
1933 if (undobuf.other_insn == 0
1934 && (cc_use = find_single_use (SET_DEST (newpat), i3,
1935 &undobuf.other_insn))
1936 && ((compare_mode = SELECT_CC_MODE (GET_CODE (*cc_use),
1938 != GET_MODE (SET_DEST (newpat))))
1940 unsigned int regno = REGNO (SET_DEST (newpat));
1941 rtx new_dest = gen_rtx_REG (compare_mode, regno);
1943 if (regno < FIRST_PSEUDO_REGISTER
1944 || (REG_N_SETS (regno) == 1 && ! added_sets_2
1945 && ! REG_USERVAR_P (SET_DEST (newpat))))
1947 if (regno >= FIRST_PSEUDO_REGISTER)
1948 SUBST (regno_reg_rtx[regno], new_dest);
1950 SUBST (SET_DEST (newpat), new_dest);
1951 SUBST (XEXP (*cc_use, 0), new_dest);
1952 SUBST (SET_SRC (newpat),
1953 gen_rtx_COMPARE (compare_mode, i2src, const0_rtx));
1956 undobuf.other_insn = 0;
1963 n_occurrences = 0; /* `subst' counts here */
1965 /* If I1 feeds into I2 (not into I3) and I1DEST is in I1SRC, we
1966 need to make a unique copy of I2SRC each time we substitute it
1967 to avoid self-referential rtl. */
1969 subst_low_cuid = INSN_CUID (i2);
1970 newpat = subst (PATTERN (i3), i2dest, i2src, 0,
1971 ! i1_feeds_i3 && i1dest_in_i1src);
1974 /* Record whether i2's body now appears within i3's body. */
1975 i2_is_used = n_occurrences;
1978 /* If we already got a failure, don't try to do more. Otherwise,
1979 try to substitute in I1 if we have it. */
1981 if (i1 && GET_CODE (newpat) != CLOBBER)
1983 /* Before we can do this substitution, we must redo the test done
1984 above (see detailed comments there) that ensures that I1DEST
1985 isn't mentioned in any SETs in NEWPAT that are field assignments. */
1987 if (! combinable_i3pat (NULL_RTX, &newpat, i1dest, NULL_RTX,
1995 subst_low_cuid = INSN_CUID (i1);
1996 newpat = subst (newpat, i1dest, i1src, 0, 0);
2000 /* Fail if an autoincrement side-effect has been duplicated. Be careful
2001 to count all the ways that I2SRC and I1SRC can be used. */
2002 if ((FIND_REG_INC_NOTE (i2, NULL_RTX) != 0
2003 && i2_is_used + added_sets_2 > 1)
2004 || (i1 != 0 && FIND_REG_INC_NOTE (i1, NULL_RTX) != 0
2005 && (n_occurrences + added_sets_1 + (added_sets_2 && ! i1_feeds_i3)
2007 /* Fail if we tried to make a new register (we used to abort, but there's
2008 really no reason to). */
2009 || max_reg_num () != maxreg
2010 /* Fail if we couldn't do something and have a CLOBBER. */
2011 || GET_CODE (newpat) == CLOBBER
2012 /* Fail if this new pattern is a MULT and we didn't have one before
2013 at the outer level. */
2014 || (GET_CODE (newpat) == SET && GET_CODE (SET_SRC (newpat)) == MULT
2021 /* If the actions of the earlier insns must be kept
2022 in addition to substituting them into the latest one,
2023 we must make a new PARALLEL for the latest insn
2024 to hold additional the SETs. */
2026 if (added_sets_1 || added_sets_2)
2030 if (GET_CODE (newpat) == PARALLEL)
2032 rtvec old = XVEC (newpat, 0);
2033 total_sets = XVECLEN (newpat, 0) + added_sets_1 + added_sets_2;
2034 newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (total_sets));
2035 memcpy (XVEC (newpat, 0)->elem, &old->elem[0],
2036 sizeof (old->elem[0]) * old->num_elem);
2041 total_sets = 1 + added_sets_1 + added_sets_2;
2042 newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (total_sets));
2043 XVECEXP (newpat, 0, 0) = old;
2047 XVECEXP (newpat, 0, --total_sets)
2048 = (GET_CODE (PATTERN (i1)) == PARALLEL
2049 ? gen_rtx_SET (VOIDmode, i1dest, i1src) : PATTERN (i1));
2053 /* If there is no I1, use I2's body as is. We used to also not do
2054 the subst call below if I2 was substituted into I3,
2055 but that could lose a simplification. */
2057 XVECEXP (newpat, 0, --total_sets) = i2pat;
2059 /* See comment where i2pat is assigned. */
2060 XVECEXP (newpat, 0, --total_sets)
2061 = subst (i2pat, i1dest, i1src, 0, 0);
2065 /* We come here when we are replacing a destination in I2 with the
2066 destination of I3. */
2067 validate_replacement:
2069 /* Note which hard regs this insn has as inputs. */
2070 mark_used_regs_combine (newpat);
2072 /* Is the result of combination a valid instruction? */
2073 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2075 /* If the result isn't valid, see if it is a PARALLEL of two SETs where
2076 the second SET's destination is a register that is unused. In that case,
2077 we just need the first SET. This can occur when simplifying a divmod
2078 insn. We *must* test for this case here because the code below that
2079 splits two independent SETs doesn't handle this case correctly when it
2080 updates the register status. Also check the case where the first
2081 SET's destination is unused. That would not cause incorrect code, but
2082 does cause an unneeded insn to remain. */
2084 if (insn_code_number < 0 && GET_CODE (newpat) == PARALLEL
2085 && XVECLEN (newpat, 0) == 2
2086 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
2087 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
2088 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) == REG
2089 && find_reg_note (i3, REG_UNUSED, SET_DEST (XVECEXP (newpat, 0, 1)))
2090 && ! side_effects_p (SET_SRC (XVECEXP (newpat, 0, 1)))
2091 && asm_noperands (newpat) < 0)
2093 newpat = XVECEXP (newpat, 0, 0);
2094 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2097 else if (insn_code_number < 0 && GET_CODE (newpat) == PARALLEL
2098 && XVECLEN (newpat, 0) == 2
2099 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
2100 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
2101 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) == REG
2102 && find_reg_note (i3, REG_UNUSED, SET_DEST (XVECEXP (newpat, 0, 0)))
2103 && ! side_effects_p (SET_SRC (XVECEXP (newpat, 0, 0)))
2104 && asm_noperands (newpat) < 0)
2106 newpat = XVECEXP (newpat, 0, 1);
2107 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2110 /* If we were combining three insns and the result is a simple SET
2111 with no ASM_OPERANDS that wasn't recognized, try to split it into two
2112 insns. There are two ways to do this. It can be split using a
2113 machine-specific method (like when you have an addition of a large
2114 constant) or by combine in the function find_split_point. */
2116 if (i1 && insn_code_number < 0 && GET_CODE (newpat) == SET
2117 && asm_noperands (newpat) < 0)
2119 rtx m_split, *split;
2120 rtx ni2dest = i2dest;
2122 /* See if the MD file can split NEWPAT. If it can't, see if letting it
2123 use I2DEST as a scratch register will help. In the latter case,
2124 convert I2DEST to the mode of the source of NEWPAT if we can. */
2126 m_split = split_insns (newpat, i3);
2128 /* We can only use I2DEST as a scratch reg if it doesn't overlap any
2129 inputs of NEWPAT. */
2131 /* ??? If I2DEST is not safe, and I1DEST exists, then it would be
2132 possible to try that as a scratch reg. This would require adding
2133 more code to make it work though. */
2135 if (m_split == 0 && ! reg_overlap_mentioned_p (ni2dest, newpat))
2137 /* If I2DEST is a hard register or the only use of a pseudo,
2138 we can change its mode. */
2139 if (GET_MODE (SET_DEST (newpat)) != GET_MODE (i2dest)
2140 && GET_MODE (SET_DEST (newpat)) != VOIDmode
2141 && GET_CODE (i2dest) == REG
2142 && (REGNO (i2dest) < FIRST_PSEUDO_REGISTER
2143 || (REG_N_SETS (REGNO (i2dest)) == 1 && ! added_sets_2
2144 && ! REG_USERVAR_P (i2dest))))
2145 ni2dest = gen_rtx_REG (GET_MODE (SET_DEST (newpat)),
2148 m_split = split_insns (gen_rtx_PARALLEL
2150 gen_rtvec (2, newpat,
2151 gen_rtx_CLOBBER (VOIDmode,
2154 /* If the split with the mode-changed register didn't work, try
2155 the original register. */
2156 if (! m_split && ni2dest != i2dest)
2159 m_split = split_insns (gen_rtx_PARALLEL
2161 gen_rtvec (2, newpat,
2162 gen_rtx_CLOBBER (VOIDmode,
2168 /* If we've split a jump pattern, we'll wind up with a sequence even
2169 with one instruction. We can handle that below, so extract it. */
2170 if (m_split && GET_CODE (m_split) == SEQUENCE
2171 && XVECLEN (m_split, 0) == 1)
2172 m_split = PATTERN (XVECEXP (m_split, 0, 0));
2174 if (m_split && GET_CODE (m_split) != SEQUENCE)
2176 insn_code_number = recog_for_combine (&m_split, i3, &new_i3_notes);
2177 if (insn_code_number >= 0)
2180 else if (m_split && GET_CODE (m_split) == SEQUENCE
2181 && XVECLEN (m_split, 0) == 2
2182 && (next_real_insn (i2) == i3
2183 || ! use_crosses_set_p (PATTERN (XVECEXP (m_split, 0, 0)),
2187 rtx newi3pat = PATTERN (XVECEXP (m_split, 0, 1));
2188 newi2pat = PATTERN (XVECEXP (m_split, 0, 0));
2190 i3set = single_set (XVECEXP (m_split, 0, 1));
2191 i2set = single_set (XVECEXP (m_split, 0, 0));
2193 /* In case we changed the mode of I2DEST, replace it in the
2194 pseudo-register table here. We can't do it above in case this
2195 code doesn't get executed and we do a split the other way. */
2197 if (REGNO (i2dest) >= FIRST_PSEUDO_REGISTER)
2198 SUBST (regno_reg_rtx[REGNO (i2dest)], ni2dest);
2200 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
2202 /* If I2 or I3 has multiple SETs, we won't know how to track
2203 register status, so don't use these insns. If I2's destination
2204 is used between I2 and I3, we also can't use these insns. */
2206 if (i2_code_number >= 0 && i2set && i3set
2207 && (next_real_insn (i2) == i3
2208 || ! reg_used_between_p (SET_DEST (i2set), i2, i3)))
2209 insn_code_number = recog_for_combine (&newi3pat, i3,
2211 if (insn_code_number >= 0)
2214 /* It is possible that both insns now set the destination of I3.
2215 If so, we must show an extra use of it. */
2217 if (insn_code_number >= 0)
2219 rtx new_i3_dest = SET_DEST (i3set);
2220 rtx new_i2_dest = SET_DEST (i2set);
2222 while (GET_CODE (new_i3_dest) == ZERO_EXTRACT
2223 || GET_CODE (new_i3_dest) == STRICT_LOW_PART
2224 || GET_CODE (new_i3_dest) == SUBREG)
2225 new_i3_dest = XEXP (new_i3_dest, 0);
2227 while (GET_CODE (new_i2_dest) == ZERO_EXTRACT
2228 || GET_CODE (new_i2_dest) == STRICT_LOW_PART
2229 || GET_CODE (new_i2_dest) == SUBREG)
2230 new_i2_dest = XEXP (new_i2_dest, 0);
2232 if (GET_CODE (new_i3_dest) == REG
2233 && GET_CODE (new_i2_dest) == REG
2234 && REGNO (new_i3_dest) == REGNO (new_i2_dest))
2235 REG_N_SETS (REGNO (new_i2_dest))++;
2239 /* If we can split it and use I2DEST, go ahead and see if that
2240 helps things be recognized. Verify that none of the registers
2241 are set between I2 and I3. */
2242 if (insn_code_number < 0 && (split = find_split_point (&newpat, i3)) != 0
2244 && GET_CODE (i2dest) == REG
2246 /* We need I2DEST in the proper mode. If it is a hard register
2247 or the only use of a pseudo, we can change its mode. */
2248 && (GET_MODE (*split) == GET_MODE (i2dest)
2249 || GET_MODE (*split) == VOIDmode
2250 || REGNO (i2dest) < FIRST_PSEUDO_REGISTER
2251 || (REG_N_SETS (REGNO (i2dest)) == 1 && ! added_sets_2
2252 && ! REG_USERVAR_P (i2dest)))
2253 && (next_real_insn (i2) == i3
2254 || ! use_crosses_set_p (*split, INSN_CUID (i2)))
2255 /* We can't overwrite I2DEST if its value is still used by
2257 && ! reg_referenced_p (i2dest, newpat))
2259 rtx newdest = i2dest;
2260 enum rtx_code split_code = GET_CODE (*split);
2261 enum machine_mode split_mode = GET_MODE (*split);
2263 /* Get NEWDEST as a register in the proper mode. We have already
2264 validated that we can do this. */
2265 if (GET_MODE (i2dest) != split_mode && split_mode != VOIDmode)
2267 newdest = gen_rtx_REG (split_mode, REGNO (i2dest));
2269 if (REGNO (i2dest) >= FIRST_PSEUDO_REGISTER)
2270 SUBST (regno_reg_rtx[REGNO (i2dest)], newdest);
2273 /* If *SPLIT is a (mult FOO (const_int pow2)), convert it to
2274 an ASHIFT. This can occur if it was inside a PLUS and hence
2275 appeared to be a memory address. This is a kludge. */
2276 if (split_code == MULT
2277 && GET_CODE (XEXP (*split, 1)) == CONST_INT
2278 && INTVAL (XEXP (*split, 1)) > 0
2279 && (i = exact_log2 (INTVAL (XEXP (*split, 1)))) >= 0)
2281 SUBST (*split, gen_rtx_ASHIFT (split_mode,
2282 XEXP (*split, 0), GEN_INT (i)));
2283 /* Update split_code because we may not have a multiply
2285 split_code = GET_CODE (*split);
2288 #ifdef INSN_SCHEDULING
2289 /* If *SPLIT is a paradoxical SUBREG, when we split it, it should
2290 be written as a ZERO_EXTEND. */
2291 if (split_code == SUBREG && GET_CODE (SUBREG_REG (*split)) == MEM)
2292 SUBST (*split, gen_rtx_ZERO_EXTEND (split_mode,
2293 SUBREG_REG (*split)));
2296 newi2pat = gen_rtx_SET (VOIDmode, newdest, *split);
2297 SUBST (*split, newdest);
2298 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
2300 /* If the split point was a MULT and we didn't have one before,
2301 don't use one now. */
2302 if (i2_code_number >= 0 && ! (split_code == MULT && ! have_mult))
2303 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2307 /* Check for a case where we loaded from memory in a narrow mode and
2308 then sign extended it, but we need both registers. In that case,
2309 we have a PARALLEL with both loads from the same memory location.
2310 We can split this into a load from memory followed by a register-register
2311 copy. This saves at least one insn, more if register allocation can
2314 We cannot do this if the destination of the second assignment is
2315 a register that we have already assumed is zero-extended. Similarly
2316 for a SUBREG of such a register. */
2318 else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0
2319 && GET_CODE (newpat) == PARALLEL
2320 && XVECLEN (newpat, 0) == 2
2321 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
2322 && GET_CODE (SET_SRC (XVECEXP (newpat, 0, 0))) == SIGN_EXTEND
2323 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
2324 && rtx_equal_p (SET_SRC (XVECEXP (newpat, 0, 1)),
2325 XEXP (SET_SRC (XVECEXP (newpat, 0, 0)), 0))
2326 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)),
2328 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
2329 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
2330 && ! (temp = SET_DEST (XVECEXP (newpat, 0, 1)),
2331 (GET_CODE (temp) == REG
2332 && reg_nonzero_bits[REGNO (temp)] != 0
2333 && GET_MODE_BITSIZE (GET_MODE (temp)) < BITS_PER_WORD
2334 && GET_MODE_BITSIZE (GET_MODE (temp)) < HOST_BITS_PER_INT
2335 && (reg_nonzero_bits[REGNO (temp)]
2336 != GET_MODE_MASK (word_mode))))
2337 && ! (GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) == SUBREG
2338 && (temp = SUBREG_REG (SET_DEST (XVECEXP (newpat, 0, 1))),
2339 (GET_CODE (temp) == REG
2340 && reg_nonzero_bits[REGNO (temp)] != 0
2341 && GET_MODE_BITSIZE (GET_MODE (temp)) < BITS_PER_WORD
2342 && GET_MODE_BITSIZE (GET_MODE (temp)) < HOST_BITS_PER_INT
2343 && (reg_nonzero_bits[REGNO (temp)]
2344 != GET_MODE_MASK (word_mode)))))
2345 && ! reg_overlap_mentioned_p (SET_DEST (XVECEXP (newpat, 0, 1)),
2346 SET_SRC (XVECEXP (newpat, 0, 1)))
2347 && ! find_reg_note (i3, REG_UNUSED,
2348 SET_DEST (XVECEXP (newpat, 0, 0))))
2352 newi2pat = XVECEXP (newpat, 0, 0);
2353 ni2dest = SET_DEST (XVECEXP (newpat, 0, 0));
2354 newpat = XVECEXP (newpat, 0, 1);
2355 SUBST (SET_SRC (newpat),
2356 gen_lowpart_for_combine (GET_MODE (SET_SRC (newpat)), ni2dest));
2357 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
2359 if (i2_code_number >= 0)
2360 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2362 if (insn_code_number >= 0)
2367 /* If we will be able to accept this, we have made a change to the
2368 destination of I3. This can invalidate a LOG_LINKS pointing
2369 to I3. No other part of combine.c makes such a transformation.
2371 The new I3 will have a destination that was previously the
2372 destination of I1 or I2 and which was used in i2 or I3. Call
2373 distribute_links to make a LOG_LINK from the next use of
2374 that destination. */
2376 PATTERN (i3) = newpat;
2377 distribute_links (gen_rtx_INSN_LIST (VOIDmode, i3, NULL_RTX));
2379 /* I3 now uses what used to be its destination and which is
2380 now I2's destination. That means we need a LOG_LINK from
2381 I3 to I2. But we used to have one, so we still will.
2383 However, some later insn might be using I2's dest and have
2384 a LOG_LINK pointing at I3. We must remove this link.
2385 The simplest way to remove the link is to point it at I1,
2386 which we know will be a NOTE. */
2388 for (insn = NEXT_INSN (i3);
2389 insn && (this_basic_block == n_basic_blocks - 1
2390 || insn != BLOCK_HEAD (this_basic_block + 1));
2391 insn = NEXT_INSN (insn))
2393 if (INSN_P (insn) && reg_referenced_p (ni2dest, PATTERN (insn)))
2395 for (link = LOG_LINKS (insn); link;
2396 link = XEXP (link, 1))
2397 if (XEXP (link, 0) == i3)
2398 XEXP (link, 0) = i1;
2406 /* Similarly, check for a case where we have a PARALLEL of two independent
2407 SETs but we started with three insns. In this case, we can do the sets
2408 as two separate insns. This case occurs when some SET allows two
2409 other insns to combine, but the destination of that SET is still live. */
2411 else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0
2412 && GET_CODE (newpat) == PARALLEL
2413 && XVECLEN (newpat, 0) == 2
2414 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
2415 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != ZERO_EXTRACT
2416 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != STRICT_LOW_PART
2417 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
2418 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
2419 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
2420 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)),
2422 /* Don't pass sets with (USE (MEM ...)) dests to the following. */
2423 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != USE
2424 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != USE
2425 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 1)),
2426 XVECEXP (newpat, 0, 0))
2427 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 0)),
2428 XVECEXP (newpat, 0, 1))
2429 && ! (contains_muldiv (SET_SRC (XVECEXP (newpat, 0, 0)))
2430 && contains_muldiv (SET_SRC (XVECEXP (newpat, 0, 1)))))
2432 /* Normally, it doesn't matter which of the two is done first,
2433 but it does if one references cc0. In that case, it has to
2436 if (reg_referenced_p (cc0_rtx, XVECEXP (newpat, 0, 0)))
2438 newi2pat = XVECEXP (newpat, 0, 0);
2439 newpat = XVECEXP (newpat, 0, 1);
2444 newi2pat = XVECEXP (newpat, 0, 1);
2445 newpat = XVECEXP (newpat, 0, 0);
2448 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
2450 if (i2_code_number >= 0)
2451 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2454 /* If it still isn't recognized, fail and change things back the way they
2456 if ((insn_code_number < 0
2457 /* Is the result a reasonable ASM_OPERANDS? */
2458 && (! check_asm_operands (newpat) || added_sets_1 || added_sets_2)))
2464 /* If we had to change another insn, make sure it is valid also. */
2465 if (undobuf.other_insn)
2467 rtx other_pat = PATTERN (undobuf.other_insn);
2468 rtx new_other_notes;
2471 CLEAR_HARD_REG_SET (newpat_used_regs);
2473 other_code_number = recog_for_combine (&other_pat, undobuf.other_insn,
2476 if (other_code_number < 0 && ! check_asm_operands (other_pat))
2482 PATTERN (undobuf.other_insn) = other_pat;
2484 /* If any of the notes in OTHER_INSN were REG_UNUSED, ensure that they
2485 are still valid. Then add any non-duplicate notes added by
2486 recog_for_combine. */
2487 for (note = REG_NOTES (undobuf.other_insn); note; note = next)
2489 next = XEXP (note, 1);
2491 if (REG_NOTE_KIND (note) == REG_UNUSED
2492 && ! reg_set_p (XEXP (note, 0), PATTERN (undobuf.other_insn)))
2494 if (GET_CODE (XEXP (note, 0)) == REG)
2495 REG_N_DEATHS (REGNO (XEXP (note, 0)))--;
2497 remove_note (undobuf.other_insn, note);
2501 for (note = new_other_notes; note; note = XEXP (note, 1))
2502 if (GET_CODE (XEXP (note, 0)) == REG)
2503 REG_N_DEATHS (REGNO (XEXP (note, 0)))++;
2505 distribute_notes (new_other_notes, undobuf.other_insn,
2506 undobuf.other_insn, NULL_RTX, NULL_RTX, NULL_RTX);
2509 /* If I2 is the setter CC0 and I3 is the user CC0 then check whether
2510 they are adjacent to each other or not. */
2512 rtx p = prev_nonnote_insn (i3);
2513 if (p && p != i2 && GET_CODE (p) == INSN && newi2pat
2514 && sets_cc0_p (newi2pat))
2522 /* We now know that we can do this combination. Merge the insns and
2523 update the status of registers and LOG_LINKS. */
2526 rtx i3notes, i2notes, i1notes = 0;
2527 rtx i3links, i2links, i1links = 0;
2530 /* Compute which registers we expect to eliminate. newi2pat may be setting
2531 either i3dest or i2dest, so we must check it. Also, i1dest may be the
2532 same as i3dest, in which case newi2pat may be setting i1dest. */
2533 rtx elim_i2 = ((newi2pat && reg_set_p (i2dest, newi2pat))
2534 || i2dest_in_i2src || i2dest_in_i1src
2536 rtx elim_i1 = (i1 == 0 || i1dest_in_i1src
2537 || (newi2pat && reg_set_p (i1dest, newi2pat))
2540 /* Get the old REG_NOTES and LOG_LINKS from all our insns and
2542 i3notes = REG_NOTES (i3), i3links = LOG_LINKS (i3);
2543 i2notes = REG_NOTES (i2), i2links = LOG_LINKS (i2);
2545 i1notes = REG_NOTES (i1), i1links = LOG_LINKS (i1);
2547 /* Ensure that we do not have something that should not be shared but
2548 occurs multiple times in the new insns. Check this by first
2549 resetting all the `used' flags and then copying anything is shared. */
2551 reset_used_flags (i3notes);
2552 reset_used_flags (i2notes);
2553 reset_used_flags (i1notes);
2554 reset_used_flags (newpat);
2555 reset_used_flags (newi2pat);
2556 if (undobuf.other_insn)
2557 reset_used_flags (PATTERN (undobuf.other_insn));
2559 i3notes = copy_rtx_if_shared (i3notes);
2560 i2notes = copy_rtx_if_shared (i2notes);
2561 i1notes = copy_rtx_if_shared (i1notes);
2562 newpat = copy_rtx_if_shared (newpat);
2563 newi2pat = copy_rtx_if_shared (newi2pat);
2564 if (undobuf.other_insn)
2565 reset_used_flags (PATTERN (undobuf.other_insn));
2567 INSN_CODE (i3) = insn_code_number;
2568 PATTERN (i3) = newpat;
2570 if (GET_CODE (i3) == CALL_INSN && CALL_INSN_FUNCTION_USAGE (i3))
2572 rtx call_usage = CALL_INSN_FUNCTION_USAGE (i3);
2574 reset_used_flags (call_usage);
2575 call_usage = copy_rtx (call_usage);
2578 replace_rtx (call_usage, i2dest, i2src);
2581 replace_rtx (call_usage, i1dest, i1src);
2583 CALL_INSN_FUNCTION_USAGE (i3) = call_usage;
2586 if (undobuf.other_insn)
2587 INSN_CODE (undobuf.other_insn) = other_code_number;
2589 /* We had one special case above where I2 had more than one set and
2590 we replaced a destination of one of those sets with the destination
2591 of I3. In that case, we have to update LOG_LINKS of insns later
2592 in this basic block. Note that this (expensive) case is rare.
2594 Also, in this case, we must pretend that all REG_NOTEs for I2
2595 actually came from I3, so that REG_UNUSED notes from I2 will be
2596 properly handled. */
2598 if (i3_subst_into_i2)
2600 for (i = 0; i < XVECLEN (PATTERN (i2), 0); i++)
2601 if (GET_CODE (XVECEXP (PATTERN (i2), 0, i)) != USE
2602 && GET_CODE (SET_DEST (XVECEXP (PATTERN (i2), 0, i))) == REG
2603 && SET_DEST (XVECEXP (PATTERN (i2), 0, i)) != i2dest
2604 && ! find_reg_note (i2, REG_UNUSED,
2605 SET_DEST (XVECEXP (PATTERN (i2), 0, i))))
2606 for (temp = NEXT_INSN (i2);
2607 temp && (this_basic_block == n_basic_blocks - 1
2608 || BLOCK_HEAD (this_basic_block) != temp);
2609 temp = NEXT_INSN (temp))
2610 if (temp != i3 && INSN_P (temp))
2611 for (link = LOG_LINKS (temp); link; link = XEXP (link, 1))
2612 if (XEXP (link, 0) == i2)
2613 XEXP (link, 0) = i3;
2618 while (XEXP (link, 1))
2619 link = XEXP (link, 1);
2620 XEXP (link, 1) = i2notes;
2634 INSN_CODE (i2) = i2_code_number;
2635 PATTERN (i2) = newi2pat;
2639 PUT_CODE (i2, NOTE);
2640 NOTE_LINE_NUMBER (i2) = NOTE_INSN_DELETED;
2641 NOTE_SOURCE_FILE (i2) = 0;
2648 PUT_CODE (i1, NOTE);
2649 NOTE_LINE_NUMBER (i1) = NOTE_INSN_DELETED;
2650 NOTE_SOURCE_FILE (i1) = 0;
2653 /* Get death notes for everything that is now used in either I3 or
2654 I2 and used to die in a previous insn. If we built two new
2655 patterns, move from I1 to I2 then I2 to I3 so that we get the
2656 proper movement on registers that I2 modifies. */
2660 move_deaths (newi2pat, NULL_RTX, INSN_CUID (i1), i2, &midnotes);
2661 move_deaths (newpat, newi2pat, INSN_CUID (i1), i3, &midnotes);
2664 move_deaths (newpat, NULL_RTX, i1 ? INSN_CUID (i1) : INSN_CUID (i2),
2667 /* Distribute all the LOG_LINKS and REG_NOTES from I1, I2, and I3. */
2669 distribute_notes (i3notes, i3, i3, newi2pat ? i2 : NULL_RTX,
2672 distribute_notes (i2notes, i2, i3, newi2pat ? i2 : NULL_RTX,
2675 distribute_notes (i1notes, i1, i3, newi2pat ? i2 : NULL_RTX,
2678 distribute_notes (midnotes, NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
2681 /* Distribute any notes added to I2 or I3 by recog_for_combine. We
2682 know these are REG_UNUSED and want them to go to the desired insn,
2683 so we always pass it as i3. We have not counted the notes in
2684 reg_n_deaths yet, so we need to do so now. */
2686 if (newi2pat && new_i2_notes)
2688 for (temp = new_i2_notes; temp; temp = XEXP (temp, 1))
2689 if (GET_CODE (XEXP (temp, 0)) == REG)
2690 REG_N_DEATHS (REGNO (XEXP (temp, 0)))++;
2692 distribute_notes (new_i2_notes, i2, i2, NULL_RTX, NULL_RTX, NULL_RTX);
2697 for (temp = new_i3_notes; temp; temp = XEXP (temp, 1))
2698 if (GET_CODE (XEXP (temp, 0)) == REG)
2699 REG_N_DEATHS (REGNO (XEXP (temp, 0)))++;
2701 distribute_notes (new_i3_notes, i3, i3, NULL_RTX, NULL_RTX, NULL_RTX);
2704 /* If I3DEST was used in I3SRC, it really died in I3. We may need to
2705 put a REG_DEAD note for it somewhere. If NEWI2PAT exists and sets
2706 I3DEST, the death must be somewhere before I2, not I3. If we passed I3
2707 in that case, it might delete I2. Similarly for I2 and I1.
2708 Show an additional death due to the REG_DEAD note we make here. If
2709 we discard it in distribute_notes, we will decrement it again. */
2713 if (GET_CODE (i3dest_killed) == REG)
2714 REG_N_DEATHS (REGNO (i3dest_killed))++;
2716 if (newi2pat && reg_set_p (i3dest_killed, newi2pat))
2717 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i3dest_killed,
2719 NULL_RTX, i2, NULL_RTX, elim_i2, elim_i1);
2721 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i3dest_killed,
2723 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
2727 if (i2dest_in_i2src)
2729 if (GET_CODE (i2dest) == REG)
2730 REG_N_DEATHS (REGNO (i2dest))++;
2732 if (newi2pat && reg_set_p (i2dest, newi2pat))
2733 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i2dest, NULL_RTX),
2734 NULL_RTX, i2, NULL_RTX, NULL_RTX, NULL_RTX);
2736 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i2dest, NULL_RTX),
2737 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
2738 NULL_RTX, NULL_RTX);
2741 if (i1dest_in_i1src)
2743 if (GET_CODE (i1dest) == REG)
2744 REG_N_DEATHS (REGNO (i1dest))++;
2746 if (newi2pat && reg_set_p (i1dest, newi2pat))
2747 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i1dest, NULL_RTX),
2748 NULL_RTX, i2, NULL_RTX, NULL_RTX, NULL_RTX);
2750 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i1dest, NULL_RTX),
2751 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
2752 NULL_RTX, NULL_RTX);
2755 distribute_links (i3links);
2756 distribute_links (i2links);
2757 distribute_links (i1links);
2759 if (GET_CODE (i2dest) == REG)
2762 rtx i2_insn = 0, i2_val = 0, set;
2764 /* The insn that used to set this register doesn't exist, and
2765 this life of the register may not exist either. See if one of
2766 I3's links points to an insn that sets I2DEST. If it does,
2767 that is now the last known value for I2DEST. If we don't update
2768 this and I2 set the register to a value that depended on its old
2769 contents, we will get confused. If this insn is used, thing
2770 will be set correctly in combine_instructions. */
2772 for (link = LOG_LINKS (i3); link; link = XEXP (link, 1))
2773 if ((set = single_set (XEXP (link, 0))) != 0
2774 && rtx_equal_p (i2dest, SET_DEST (set)))
2775 i2_insn = XEXP (link, 0), i2_val = SET_SRC (set);
2777 record_value_for_reg (i2dest, i2_insn, i2_val);
2779 /* If the reg formerly set in I2 died only once and that was in I3,
2780 zero its use count so it won't make `reload' do any work. */
2782 && (newi2pat == 0 || ! reg_mentioned_p (i2dest, newi2pat))
2783 && ! i2dest_in_i2src)
2785 regno = REGNO (i2dest);
2786 REG_N_SETS (regno)--;
2790 if (i1 && GET_CODE (i1dest) == REG)
2793 rtx i1_insn = 0, i1_val = 0, set;
2795 for (link = LOG_LINKS (i3); link; link = XEXP (link, 1))
2796 if ((set = single_set (XEXP (link, 0))) != 0
2797 && rtx_equal_p (i1dest, SET_DEST (set)))
2798 i1_insn = XEXP (link, 0), i1_val = SET_SRC (set);
2800 record_value_for_reg (i1dest, i1_insn, i1_val);
2802 regno = REGNO (i1dest);
2803 if (! added_sets_1 && ! i1dest_in_i1src)
2804 REG_N_SETS (regno)--;
2807 /* Update reg_nonzero_bits et al for any changes that may have been made
2808 to this insn. The order of set_nonzero_bits_and_sign_copies() is
2809 important. Because newi2pat can affect nonzero_bits of newpat */
2811 note_stores (newi2pat, set_nonzero_bits_and_sign_copies, NULL);
2812 note_stores (newpat, set_nonzero_bits_and_sign_copies, NULL);
2814 /* Set new_direct_jump_p if a new return or simple jump instruction
2817 If I3 is now an unconditional jump, ensure that it has a
2818 BARRIER following it since it may have initially been a
2819 conditional jump. It may also be the last nonnote insn. */
2821 if (GET_CODE (newpat) == RETURN || any_uncondjump_p (i3))
2823 *new_direct_jump_p = 1;
2825 if ((temp = next_nonnote_insn (i3)) == NULL_RTX
2826 || GET_CODE (temp) != BARRIER)
2827 emit_barrier_after (i3);
2829 /* An NOOP jump does not need barrier, but it does need cleaning up
2831 if (GET_CODE (newpat) == SET
2832 && SET_SRC (newpat) == pc_rtx
2833 && SET_DEST (newpat) == pc_rtx)
2834 *new_direct_jump_p = 1;
2837 combine_successes++;
2840 /* Clear this here, so that subsequent get_last_value calls are not
2842 subst_prev_insn = NULL_RTX;
2844 if (added_links_insn
2845 && (newi2pat == 0 || INSN_CUID (added_links_insn) < INSN_CUID (i2))
2846 && INSN_CUID (added_links_insn) < INSN_CUID (i3))
2847 return added_links_insn;
2849 return newi2pat ? i2 : i3;
2852 /* Undo all the modifications recorded in undobuf. */
2857 struct undo *undo, *next;
2859 for (undo = undobuf.undos; undo; undo = next)
2863 *undo->where.i = undo->old_contents.i;
2865 *undo->where.r = undo->old_contents.r;
2867 undo->next = undobuf.frees;
2868 undobuf.frees = undo;
2873 /* Clear this here, so that subsequent get_last_value calls are not
2875 subst_prev_insn = NULL_RTX;
2878 /* We've committed to accepting the changes we made. Move all
2879 of the undos to the free list. */
2884 struct undo *undo, *next;
2886 for (undo = undobuf.undos; undo; undo = next)
2889 undo->next = undobuf.frees;
2890 undobuf.frees = undo;
2896 /* Find the innermost point within the rtx at LOC, possibly LOC itself,
2897 where we have an arithmetic expression and return that point. LOC will
2900 try_combine will call this function to see if an insn can be split into
2904 find_split_point (loc, insn)
2909 enum rtx_code code = GET_CODE (x);
2911 unsigned HOST_WIDE_INT len = 0;
2912 HOST_WIDE_INT pos = 0;
2914 rtx inner = NULL_RTX;
2916 /* First special-case some codes. */
2920 #ifdef INSN_SCHEDULING
2921 /* If we are making a paradoxical SUBREG invalid, it becomes a split
2923 if (GET_CODE (SUBREG_REG (x)) == MEM)
2926 return find_split_point (&SUBREG_REG (x), insn);
2930 /* If we have (mem (const ..)) or (mem (symbol_ref ...)), split it
2931 using LO_SUM and HIGH. */
2932 if (GET_CODE (XEXP (x, 0)) == CONST
2933 || GET_CODE (XEXP (x, 0)) == SYMBOL_REF)
2936 gen_rtx_LO_SUM (Pmode,
2937 gen_rtx_HIGH (Pmode, XEXP (x, 0)),
2939 return &XEXP (XEXP (x, 0), 0);
2943 /* If we have a PLUS whose second operand is a constant and the
2944 address is not valid, perhaps will can split it up using
2945 the machine-specific way to split large constants. We use
2946 the first pseudo-reg (one of the virtual regs) as a placeholder;
2947 it will not remain in the result. */
2948 if (GET_CODE (XEXP (x, 0)) == PLUS
2949 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
2950 && ! memory_address_p (GET_MODE (x), XEXP (x, 0)))
2952 rtx reg = regno_reg_rtx[FIRST_PSEUDO_REGISTER];
2953 rtx seq = split_insns (gen_rtx_SET (VOIDmode, reg, XEXP (x, 0)),
2956 /* This should have produced two insns, each of which sets our
2957 placeholder. If the source of the second is a valid address,
2958 we can make put both sources together and make a split point
2961 if (seq && XVECLEN (seq, 0) == 2
2962 && GET_CODE (XVECEXP (seq, 0, 0)) == INSN
2963 && GET_CODE (PATTERN (XVECEXP (seq, 0, 0))) == SET
2964 && SET_DEST (PATTERN (XVECEXP (seq, 0, 0))) == reg
2965 && ! reg_mentioned_p (reg,
2966 SET_SRC (PATTERN (XVECEXP (seq, 0, 0))))
2967 && GET_CODE (XVECEXP (seq, 0, 1)) == INSN
2968 && GET_CODE (PATTERN (XVECEXP (seq, 0, 1))) == SET
2969 && SET_DEST (PATTERN (XVECEXP (seq, 0, 1))) == reg
2970 && memory_address_p (GET_MODE (x),
2971 SET_SRC (PATTERN (XVECEXP (seq, 0, 1)))))
2973 rtx src1 = SET_SRC (PATTERN (XVECEXP (seq, 0, 0)));
2974 rtx src2 = SET_SRC (PATTERN (XVECEXP (seq, 0, 1)));
2976 /* Replace the placeholder in SRC2 with SRC1. If we can
2977 find where in SRC2 it was placed, that can become our
2978 split point and we can replace this address with SRC2.
2979 Just try two obvious places. */
2981 src2 = replace_rtx (src2, reg, src1);
2983 if (XEXP (src2, 0) == src1)
2984 split = &XEXP (src2, 0);
2985 else if (GET_RTX_FORMAT (GET_CODE (XEXP (src2, 0)))[0] == 'e'
2986 && XEXP (XEXP (src2, 0), 0) == src1)
2987 split = &XEXP (XEXP (src2, 0), 0);
2991 SUBST (XEXP (x, 0), src2);
2996 /* If that didn't work, perhaps the first operand is complex and
2997 needs to be computed separately, so make a split point there.
2998 This will occur on machines that just support REG + CONST
2999 and have a constant moved through some previous computation. */
3001 else if (GET_RTX_CLASS (GET_CODE (XEXP (XEXP (x, 0), 0))) != 'o'
3002 && ! (GET_CODE (XEXP (XEXP (x, 0), 0)) == SUBREG
3003 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (XEXP (x, 0), 0))))
3005 return &XEXP (XEXP (x, 0), 0);
3011 /* If SET_DEST is CC0 and SET_SRC is not an operand, a COMPARE, or a
3012 ZERO_EXTRACT, the most likely reason why this doesn't match is that
3013 we need to put the operand into a register. So split at that
3016 if (SET_DEST (x) == cc0_rtx
3017 && GET_CODE (SET_SRC (x)) != COMPARE
3018 && GET_CODE (SET_SRC (x)) != ZERO_EXTRACT
3019 && GET_RTX_CLASS (GET_CODE (SET_SRC (x))) != 'o'
3020 && ! (GET_CODE (SET_SRC (x)) == SUBREG
3021 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (SET_SRC (x)))) == 'o'))
3022 return &SET_SRC (x);
3025 /* See if we can split SET_SRC as it stands. */
3026 split = find_split_point (&SET_SRC (x), insn);
3027 if (split && split != &SET_SRC (x))
3030 /* See if we can split SET_DEST as it stands. */
3031 split = find_split_point (&SET_DEST (x), insn);
3032 if (split && split != &SET_DEST (x))
3035 /* See if this is a bitfield assignment with everything constant. If
3036 so, this is an IOR of an AND, so split it into that. */
3037 if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
3038 && (GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0)))
3039 <= HOST_BITS_PER_WIDE_INT)
3040 && GET_CODE (XEXP (SET_DEST (x), 1)) == CONST_INT
3041 && GET_CODE (XEXP (SET_DEST (x), 2)) == CONST_INT
3042 && GET_CODE (SET_SRC (x)) == CONST_INT
3043 && ((INTVAL (XEXP (SET_DEST (x), 1))
3044 + INTVAL (XEXP (SET_DEST (x), 2)))
3045 <= GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0))))
3046 && ! side_effects_p (XEXP (SET_DEST (x), 0)))
3048 HOST_WIDE_INT pos = INTVAL (XEXP (SET_DEST (x), 2));
3049 unsigned HOST_WIDE_INT len = INTVAL (XEXP (SET_DEST (x), 1));
3050 unsigned HOST_WIDE_INT src = INTVAL (SET_SRC (x));
3051 rtx dest = XEXP (SET_DEST (x), 0);
3052 enum machine_mode mode = GET_MODE (dest);
3053 unsigned HOST_WIDE_INT mask = ((HOST_WIDE_INT) 1 << len) - 1;
3055 if (BITS_BIG_ENDIAN)
3056 pos = GET_MODE_BITSIZE (mode) - len - pos;
3060 gen_binary (IOR, mode, dest, GEN_INT (src << pos)));
3063 gen_binary (IOR, mode,
3064 gen_binary (AND, mode, dest,
3065 GEN_INT (~(mask << pos)
3066 & GET_MODE_MASK (mode))),
3067 GEN_INT (src << pos)));
3069 SUBST (SET_DEST (x), dest);
3071 split = find_split_point (&SET_SRC (x), insn);
3072 if (split && split != &SET_SRC (x))
3076 /* Otherwise, see if this is an operation that we can split into two.
3077 If so, try to split that. */
3078 code = GET_CODE (SET_SRC (x));
3083 /* If we are AND'ing with a large constant that is only a single
3084 bit and the result is only being used in a context where we
3085 need to know if it is zero or non-zero, replace it with a bit
3086 extraction. This will avoid the large constant, which might
3087 have taken more than one insn to make. If the constant were
3088 not a valid argument to the AND but took only one insn to make,
3089 this is no worse, but if it took more than one insn, it will
3092 if (GET_CODE (XEXP (SET_SRC (x), 1)) == CONST_INT
3093 && GET_CODE (XEXP (SET_SRC (x), 0)) == REG
3094 && (pos = exact_log2 (INTVAL (XEXP (SET_SRC (x), 1)))) >= 7
3095 && GET_CODE (SET_DEST (x)) == REG
3096 && (split = find_single_use (SET_DEST (x), insn, (rtx*) 0)) != 0
3097 && (GET_CODE (*split) == EQ || GET_CODE (*split) == NE)
3098 && XEXP (*split, 0) == SET_DEST (x)
3099 && XEXP (*split, 1) == const0_rtx)
3101 rtx extraction = make_extraction (GET_MODE (SET_DEST (x)),
3102 XEXP (SET_SRC (x), 0),
3103 pos, NULL_RTX, 1, 1, 0, 0);
3104 if (extraction != 0)
3106 SUBST (SET_SRC (x), extraction);
3107 return find_split_point (loc, insn);
3113 /* if STORE_FLAG_VALUE is -1, this is (NE X 0) and only one bit of X
3114 is known to be on, this can be converted into a NEG of a shift. */
3115 if (STORE_FLAG_VALUE == -1 && XEXP (SET_SRC (x), 1) == const0_rtx
3116 && GET_MODE (SET_SRC (x)) == GET_MODE (XEXP (SET_SRC (x), 0))
3117 && 1 <= (pos = exact_log2
3118 (nonzero_bits (XEXP (SET_SRC (x), 0),
3119 GET_MODE (XEXP (SET_SRC (x), 0))))))
3121 enum machine_mode mode = GET_MODE (XEXP (SET_SRC (x), 0));
3125 gen_rtx_LSHIFTRT (mode,
3126 XEXP (SET_SRC (x), 0),
3129 split = find_split_point (&SET_SRC (x), insn);
3130 if (split && split != &SET_SRC (x))
3136 inner = XEXP (SET_SRC (x), 0);
3138 /* We can't optimize if either mode is a partial integer
3139 mode as we don't know how many bits are significant
3141 if (GET_MODE_CLASS (GET_MODE (inner)) == MODE_PARTIAL_INT
3142 || GET_MODE_CLASS (GET_MODE (SET_SRC (x))) == MODE_PARTIAL_INT)
3146 len = GET_MODE_BITSIZE (GET_MODE (inner));
3152 if (GET_CODE (XEXP (SET_SRC (x), 1)) == CONST_INT
3153 && GET_CODE (XEXP (SET_SRC (x), 2)) == CONST_INT)
3155 inner = XEXP (SET_SRC (x), 0);
3156 len = INTVAL (XEXP (SET_SRC (x), 1));
3157 pos = INTVAL (XEXP (SET_SRC (x), 2));
3159 if (BITS_BIG_ENDIAN)
3160 pos = GET_MODE_BITSIZE (GET_MODE (inner)) - len - pos;
3161 unsignedp = (code == ZERO_EXTRACT);
3169 if (len && pos >= 0 && pos + len <= GET_MODE_BITSIZE (GET_MODE (inner)))
3171 enum machine_mode mode = GET_MODE (SET_SRC (x));
3173 /* For unsigned, we have a choice of a shift followed by an
3174 AND or two shifts. Use two shifts for field sizes where the
3175 constant might be too large. We assume here that we can
3176 always at least get 8-bit constants in an AND insn, which is
3177 true for every current RISC. */
3179 if (unsignedp && len <= 8)
3184 (mode, gen_lowpart_for_combine (mode, inner),
3186 GEN_INT (((HOST_WIDE_INT) 1 << len) - 1)));
3188 split = find_split_point (&SET_SRC (x), insn);
3189 if (split && split != &SET_SRC (x))
3196 (unsignedp ? LSHIFTRT : ASHIFTRT, mode,
3197 gen_rtx_ASHIFT (mode,
3198 gen_lowpart_for_combine (mode, inner),
3199 GEN_INT (GET_MODE_BITSIZE (mode)
3201 GEN_INT (GET_MODE_BITSIZE (mode) - len)));
3203 split = find_split_point (&SET_SRC (x), insn);
3204 if (split && split != &SET_SRC (x))
3209 /* See if this is a simple operation with a constant as the second
3210 operand. It might be that this constant is out of range and hence
3211 could be used as a split point. */
3212 if ((GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '2'
3213 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == 'c'
3214 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '<')
3215 && CONSTANT_P (XEXP (SET_SRC (x), 1))
3216 && (GET_RTX_CLASS (GET_CODE (XEXP (SET_SRC (x), 0))) == 'o'
3217 || (GET_CODE (XEXP (SET_SRC (x), 0)) == SUBREG
3218 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (SET_SRC (x), 0))))
3220 return &XEXP (SET_SRC (x), 1);
3222 /* Finally, see if this is a simple operation with its first operand
3223 not in a register. The operation might require this operand in a
3224 register, so return it as a split point. We can always do this
3225 because if the first operand were another operation, we would have
3226 already found it as a split point. */
3227 if ((GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '2'
3228 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == 'c'
3229 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '<'
3230 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '1')
3231 && ! register_operand (XEXP (SET_SRC (x), 0), VOIDmode))
3232 return &XEXP (SET_SRC (x), 0);
3238 /* We write NOR as (and (not A) (not B)), but if we don't have a NOR,
3239 it is better to write this as (not (ior A B)) so we can split it.
3240 Similarly for IOR. */
3241 if (GET_CODE (XEXP (x, 0)) == NOT && GET_CODE (XEXP (x, 1)) == NOT)
3244 gen_rtx_NOT (GET_MODE (x),
3245 gen_rtx_fmt_ee (code == IOR ? AND : IOR,
3247 XEXP (XEXP (x, 0), 0),
3248 XEXP (XEXP (x, 1), 0))));
3249 return find_split_point (loc, insn);
3252 /* Many RISC machines have a large set of logical insns. If the
3253 second operand is a NOT, put it first so we will try to split the
3254 other operand first. */
3255 if (GET_CODE (XEXP (x, 1)) == NOT)
3257 rtx tem = XEXP (x, 0);
3258 SUBST (XEXP (x, 0), XEXP (x, 1));
3259 SUBST (XEXP (x, 1), tem);
3267 /* Otherwise, select our actions depending on our rtx class. */
3268 switch (GET_RTX_CLASS (code))
3270 case 'b': /* This is ZERO_EXTRACT and SIGN_EXTRACT. */
3272 split = find_split_point (&XEXP (x, 2), insn);
3275 /* ... fall through ... */
3279 split = find_split_point (&XEXP (x, 1), insn);
3282 /* ... fall through ... */
3284 /* Some machines have (and (shift ...) ...) insns. If X is not
3285 an AND, but XEXP (X, 0) is, use it as our split point. */
3286 if (GET_CODE (x) != AND && GET_CODE (XEXP (x, 0)) == AND)
3287 return &XEXP (x, 0);
3289 split = find_split_point (&XEXP (x, 0), insn);
3295 /* Otherwise, we don't have a split point. */
3299 /* Throughout X, replace FROM with TO, and return the result.
3300 The result is TO if X is FROM;
3301 otherwise the result is X, but its contents may have been modified.
3302 If they were modified, a record was made in undobuf so that
3303 undo_all will (among other things) return X to its original state.
3305 If the number of changes necessary is too much to record to undo,
3306 the excess changes are not made, so the result is invalid.
3307 The changes already made can still be undone.
3308 undobuf.num_undo is incremented for such changes, so by testing that
3309 the caller can tell whether the result is valid.
3311 `n_occurrences' is incremented each time FROM is replaced.
3313 IN_DEST is non-zero if we are processing the SET_DEST of a SET.
3315 UNIQUE_COPY is non-zero if each substitution must be unique. We do this
3316 by copying if `n_occurrences' is non-zero. */
3319 subst (x, from, to, in_dest, unique_copy)
3324 enum rtx_code code = GET_CODE (x);
3325 enum machine_mode op0_mode = VOIDmode;
3330 /* Two expressions are equal if they are identical copies of a shared
3331 RTX or if they are both registers with the same register number
3334 #define COMBINE_RTX_EQUAL_P(X,Y) \
3336 || (GET_CODE (X) == REG && GET_CODE (Y) == REG \
3337 && REGNO (X) == REGNO (Y) && GET_MODE (X) == GET_MODE (Y)))
3339 if (! in_dest && COMBINE_RTX_EQUAL_P (x, from))
3342 return (unique_copy && n_occurrences > 1 ? copy_rtx (to) : to);
3345 /* If X and FROM are the same register but different modes, they will
3346 not have been seen as equal above. However, flow.c will make a
3347 LOG_LINKS entry for that case. If we do nothing, we will try to
3348 rerecognize our original insn and, when it succeeds, we will
3349 delete the feeding insn, which is incorrect.
3351 So force this insn not to match in this (rare) case. */
3352 if (! in_dest && code == REG && GET_CODE (from) == REG
3353 && REGNO (x) == REGNO (from))
3354 return gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
3356 /* If this is an object, we are done unless it is a MEM or LO_SUM, both
3357 of which may contain things that can be combined. */
3358 if (code != MEM && code != LO_SUM && GET_RTX_CLASS (code) == 'o')
3361 /* It is possible to have a subexpression appear twice in the insn.
3362 Suppose that FROM is a register that appears within TO.
3363 Then, after that subexpression has been scanned once by `subst',
3364 the second time it is scanned, TO may be found. If we were
3365 to scan TO here, we would find FROM within it and create a
3366 self-referent rtl structure which is completely wrong. */
3367 if (COMBINE_RTX_EQUAL_P (x, to))
3370 /* Parallel asm_operands need special attention because all of the
3371 inputs are shared across the arms. Furthermore, unsharing the
3372 rtl results in recognition failures. Failure to handle this case
3373 specially can result in circular rtl.
3375 Solve this by doing a normal pass across the first entry of the
3376 parallel, and only processing the SET_DESTs of the subsequent
3379 if (code == PARALLEL
3380 && GET_CODE (XVECEXP (x, 0, 0)) == SET
3381 && GET_CODE (SET_SRC (XVECEXP (x, 0, 0))) == ASM_OPERANDS)
3383 new = subst (XVECEXP (x, 0, 0), from, to, 0, unique_copy);
3385 /* If this substitution failed, this whole thing fails. */
3386 if (GET_CODE (new) == CLOBBER
3387 && XEXP (new, 0) == const0_rtx)
3390 SUBST (XVECEXP (x, 0, 0), new);
3392 for (i = XVECLEN (x, 0) - 1; i >= 1; i--)
3394 rtx dest = SET_DEST (XVECEXP (x, 0, i));
3396 if (GET_CODE (dest) != REG
3397 && GET_CODE (dest) != CC0
3398 && GET_CODE (dest) != PC)
3400 new = subst (dest, from, to, 0, unique_copy);
3402 /* If this substitution failed, this whole thing fails. */
3403 if (GET_CODE (new) == CLOBBER
3404 && XEXP (new, 0) == const0_rtx)
3407 SUBST (SET_DEST (XVECEXP (x, 0, i)), new);
3413 len = GET_RTX_LENGTH (code);
3414 fmt = GET_RTX_FORMAT (code);
3416 /* We don't need to process a SET_DEST that is a register, CC0,
3417 or PC, so set up to skip this common case. All other cases
3418 where we want to suppress replacing something inside a
3419 SET_SRC are handled via the IN_DEST operand. */
3421 && (GET_CODE (SET_DEST (x)) == REG
3422 || GET_CODE (SET_DEST (x)) == CC0
3423 || GET_CODE (SET_DEST (x)) == PC))
3426 /* Get the mode of operand 0 in case X is now a SIGN_EXTEND of a
3429 op0_mode = GET_MODE (XEXP (x, 0));
3431 for (i = 0; i < len; i++)
3436 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
3438 if (COMBINE_RTX_EQUAL_P (XVECEXP (x, i, j), from))
3440 new = (unique_copy && n_occurrences
3441 ? copy_rtx (to) : to);
3446 new = subst (XVECEXP (x, i, j), from, to, 0,
3449 /* If this substitution failed, this whole thing
3451 if (GET_CODE (new) == CLOBBER
3452 && XEXP (new, 0) == const0_rtx)
3456 SUBST (XVECEXP (x, i, j), new);
3459 else if (fmt[i] == 'e')
3461 /* If this is a register being set, ignore it. */
3464 && (code == SUBREG || code == STRICT_LOW_PART
3465 || code == ZERO_EXTRACT)
3467 && GET_CODE (new) == REG)
3470 else if (COMBINE_RTX_EQUAL_P (XEXP (x, i), from))
3472 /* In general, don't install a subreg involving two
3473 modes not tieable. It can worsen register
3474 allocation, and can even make invalid reload
3475 insns, since the reg inside may need to be copied
3476 from in the outside mode, and that may be invalid
3477 if it is an fp reg copied in integer mode.
3479 We allow two exceptions to this: It is valid if
3480 it is inside another SUBREG and the mode of that
3481 SUBREG and the mode of the inside of TO is
3482 tieable and it is valid if X is a SET that copies
3485 if (GET_CODE (to) == SUBREG
3486 && ! MODES_TIEABLE_P (GET_MODE (to),
3487 GET_MODE (SUBREG_REG (to)))
3488 && ! (code == SUBREG
3489 && MODES_TIEABLE_P (GET_MODE (x),
3490 GET_MODE (SUBREG_REG (to))))
3492 && ! (code == SET && i == 1 && XEXP (x, 0) == cc0_rtx)
3495 return gen_rtx_CLOBBER (VOIDmode, const0_rtx);
3497 #ifdef CLASS_CANNOT_CHANGE_MODE
3499 && GET_CODE (to) == REG
3500 && REGNO (to) < FIRST_PSEUDO_REGISTER
3501 && (TEST_HARD_REG_BIT
3502 (reg_class_contents[(int) CLASS_CANNOT_CHANGE_MODE],
3504 && CLASS_CANNOT_CHANGE_MODE_P (GET_MODE (to),
3506 return gen_rtx_CLOBBER (VOIDmode, const0_rtx);
3509 new = (unique_copy && n_occurrences ? copy_rtx (to) : to);
3513 /* If we are in a SET_DEST, suppress most cases unless we
3514 have gone inside a MEM, in which case we want to
3515 simplify the address. We assume here that things that
3516 are actually part of the destination have their inner
3517 parts in the first expression. This is true for SUBREG,
3518 STRICT_LOW_PART, and ZERO_EXTRACT, which are the only
3519 things aside from REG and MEM that should appear in a
3521 new = subst (XEXP (x, i), from, to,
3523 && (code == SUBREG || code == STRICT_LOW_PART
3524 || code == ZERO_EXTRACT))
3526 && i == 0), unique_copy);
3528 /* If we found that we will have to reject this combination,
3529 indicate that by returning the CLOBBER ourselves, rather than
3530 an expression containing it. This will speed things up as
3531 well as prevent accidents where two CLOBBERs are considered
3532 to be equal, thus producing an incorrect simplification. */
3534 if (GET_CODE (new) == CLOBBER && XEXP (new, 0) == const0_rtx)
3537 if (GET_CODE (new) == CONST_INT && GET_CODE (x) == SUBREG)
3539 x = simplify_subreg (GET_MODE (x), new,
3540 GET_MODE (SUBREG_REG (x)),
3545 else if (GET_CODE (new) == CONST_INT
3546 && GET_CODE (x) == ZERO_EXTEND)
3548 x = simplify_unary_operation (ZERO_EXTEND, GET_MODE (x),
3549 new, GET_MODE (XEXP (x, 0)));
3554 SUBST (XEXP (x, i), new);
3559 /* Try to simplify X. If the simplification changed the code, it is likely
3560 that further simplification will help, so loop, but limit the number
3561 of repetitions that will be performed. */
3563 for (i = 0; i < 4; i++)
3565 /* If X is sufficiently simple, don't bother trying to do anything
3567 if (code != CONST_INT && code != REG && code != CLOBBER)
3568 x = combine_simplify_rtx (x, op0_mode, i == 3, in_dest);
3570 if (GET_CODE (x) == code)
3573 code = GET_CODE (x);
3575 /* We no longer know the original mode of operand 0 since we
3576 have changed the form of X) */
3577 op0_mode = VOIDmode;
3583 /* Simplify X, a piece of RTL. We just operate on the expression at the
3584 outer level; call `subst' to simplify recursively. Return the new
3587 OP0_MODE is the original mode of XEXP (x, 0); LAST is nonzero if this
3588 will be the iteration even if an expression with a code different from
3589 X is returned; IN_DEST is nonzero if we are inside a SET_DEST. */
3592 combine_simplify_rtx (x, op0_mode, last, in_dest)
3594 enum machine_mode op0_mode;
3598 enum rtx_code code = GET_CODE (x);
3599 enum machine_mode mode = GET_MODE (x);
3604 /* If this is a commutative operation, put a constant last and a complex
3605 expression first. We don't need to do this for comparisons here. */
3606 if (GET_RTX_CLASS (code) == 'c'
3607 && swap_commutative_operands_p (XEXP (x, 0), XEXP (x, 1)))
3610 SUBST (XEXP (x, 0), XEXP (x, 1));
3611 SUBST (XEXP (x, 1), temp);
3614 /* If this is a PLUS, MINUS, or MULT, and the first operand is the
3615 sign extension of a PLUS with a constant, reverse the order of the sign
3616 extension and the addition. Note that this not the same as the original
3617 code, but overflow is undefined for signed values. Also note that the
3618 PLUS will have been partially moved "inside" the sign-extension, so that
3619 the first operand of X will really look like:
3620 (ashiftrt (plus (ashift A C4) C5) C4).
3622 (plus (ashiftrt (ashift A C4) C2) C4)
3623 and replace the first operand of X with that expression. Later parts
3624 of this function may simplify the expression further.
3626 For example, if we start with (mult (sign_extend (plus A C1)) C2),
3627 we swap the SIGN_EXTEND and PLUS. Later code will apply the
3628 distributive law to produce (plus (mult (sign_extend X) C1) C3).
3630 We do this to simplify address expressions. */
3632 if ((code == PLUS || code == MINUS || code == MULT)
3633 && GET_CODE (XEXP (x, 0)) == ASHIFTRT
3634 && GET_CODE (XEXP (XEXP (x, 0), 0)) == PLUS
3635 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == ASHIFT
3636 && GET_CODE (XEXP (XEXP (XEXP (XEXP (x, 0), 0), 0), 1)) == CONST_INT
3637 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3638 && XEXP (XEXP (XEXP (XEXP (x, 0), 0), 0), 1) == XEXP (XEXP (x, 0), 1)
3639 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == CONST_INT
3640 && (temp = simplify_binary_operation (ASHIFTRT, mode,
3641 XEXP (XEXP (XEXP (x, 0), 0), 1),
3642 XEXP (XEXP (x, 0), 1))) != 0)
3645 = simplify_shift_const (NULL_RTX, ASHIFT, mode,
3646 XEXP (XEXP (XEXP (XEXP (x, 0), 0), 0), 0),
3647 INTVAL (XEXP (XEXP (x, 0), 1)));
3649 new = simplify_shift_const (NULL_RTX, ASHIFTRT, mode, new,
3650 INTVAL (XEXP (XEXP (x, 0), 1)));
3652 SUBST (XEXP (x, 0), gen_binary (PLUS, mode, new, temp));
3655 /* If this is a simple operation applied to an IF_THEN_ELSE, try
3656 applying it to the arms of the IF_THEN_ELSE. This often simplifies
3657 things. Check for cases where both arms are testing the same
3660 Don't do anything if all operands are very simple. */
3662 if (((GET_RTX_CLASS (code) == '2' || GET_RTX_CLASS (code) == 'c'
3663 || GET_RTX_CLASS (code) == '<')
3664 && ((GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) != 'o'
3665 && ! (GET_CODE (XEXP (x, 0)) == SUBREG
3666 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 0))))
3668 || (GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) != 'o'
3669 && ! (GET_CODE (XEXP (x, 1)) == SUBREG
3670 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 1))))
3672 || (GET_RTX_CLASS (code) == '1'
3673 && ((GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) != 'o'
3674 && ! (GET_CODE (XEXP (x, 0)) == SUBREG
3675 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 0))))
3678 rtx cond, true_rtx, false_rtx;
3680 cond = if_then_else_cond (x, &true_rtx, &false_rtx);
3682 /* If everything is a comparison, what we have is highly unlikely
3683 to be simpler, so don't use it. */
3684 && ! (GET_RTX_CLASS (code) == '<'
3685 && (GET_RTX_CLASS (GET_CODE (true_rtx)) == '<'
3686 || GET_RTX_CLASS (GET_CODE (false_rtx)) == '<')))
3688 rtx cop1 = const0_rtx;
3689 enum rtx_code cond_code = simplify_comparison (NE, &cond, &cop1);
3691 if (cond_code == NE && GET_RTX_CLASS (GET_CODE (cond)) == '<')
3694 /* Simplify the alternative arms; this may collapse the true and
3695 false arms to store-flag values. */
3696 true_rtx = subst (true_rtx, pc_rtx, pc_rtx, 0, 0);
3697 false_rtx = subst (false_rtx, pc_rtx, pc_rtx, 0, 0);
3699 /* If true_rtx and false_rtx are not general_operands, an if_then_else
3700 is unlikely to be simpler. */
3701 if (general_operand (true_rtx, VOIDmode)
3702 && general_operand (false_rtx, VOIDmode))
3704 /* Restarting if we generate a store-flag expression will cause
3705 us to loop. Just drop through in this case. */
3707 /* If the result values are STORE_FLAG_VALUE and zero, we can
3708 just make the comparison operation. */
3709 if (true_rtx == const_true_rtx && false_rtx == const0_rtx)
3710 x = gen_binary (cond_code, mode, cond, cop1);
3711 else if (true_rtx == const0_rtx && false_rtx == const_true_rtx
3712 && reverse_condition (cond_code) != UNKNOWN)
3713 x = gen_binary (reverse_condition (cond_code),
3716 /* Likewise, we can make the negate of a comparison operation
3717 if the result values are - STORE_FLAG_VALUE and zero. */
3718 else if (GET_CODE (true_rtx) == CONST_INT
3719 && INTVAL (true_rtx) == - STORE_FLAG_VALUE
3720 && false_rtx == const0_rtx)
3721 x = simplify_gen_unary (NEG, mode,
3722 gen_binary (cond_code, mode, cond,
3725 else if (GET_CODE (false_rtx) == CONST_INT
3726 && INTVAL (false_rtx) == - STORE_FLAG_VALUE
3727 && true_rtx == const0_rtx)
3728 x = simplify_gen_unary (NEG, mode,
3729 gen_binary (reverse_condition
3734 return gen_rtx_IF_THEN_ELSE (mode,
3735 gen_binary (cond_code, VOIDmode,
3737 true_rtx, false_rtx);
3739 code = GET_CODE (x);
3740 op0_mode = VOIDmode;
3745 /* Try to fold this expression in case we have constants that weren't
3748 switch (GET_RTX_CLASS (code))
3751 temp = simplify_unary_operation (code, mode, XEXP (x, 0), op0_mode);
3755 enum machine_mode cmp_mode = GET_MODE (XEXP (x, 0));
3756 if (cmp_mode == VOIDmode)
3758 cmp_mode = GET_MODE (XEXP (x, 1));
3759 if (cmp_mode == VOIDmode)
3760 cmp_mode = op0_mode;
3762 temp = simplify_relational_operation (code, cmp_mode,
3763 XEXP (x, 0), XEXP (x, 1));
3765 #ifdef FLOAT_STORE_FLAG_VALUE
3766 if (temp != 0 && GET_MODE_CLASS (mode) == MODE_FLOAT)
3768 if (temp == const0_rtx)
3769 temp = CONST0_RTX (mode);
3771 temp = immed_real_const_1 (FLOAT_STORE_FLAG_VALUE (mode), mode);
3777 temp = simplify_binary_operation (code, mode, XEXP (x, 0), XEXP (x, 1));
3781 temp = simplify_ternary_operation (code, mode, op0_mode, XEXP (x, 0),
3782 XEXP (x, 1), XEXP (x, 2));
3789 code = GET_CODE (temp);
3790 op0_mode = VOIDmode;
3791 mode = GET_MODE (temp);
3794 /* First see if we can apply the inverse distributive law. */
3795 if (code == PLUS || code == MINUS
3796 || code == AND || code == IOR || code == XOR)
3798 x = apply_distributive_law (x);
3799 code = GET_CODE (x);
3800 op0_mode = VOIDmode;
3803 /* If CODE is an associative operation not otherwise handled, see if we
3804 can associate some operands. This can win if they are constants or
3805 if they are logically related (i.e. (a & b) & a). */
3806 if ((code == PLUS || code == MINUS || code == MULT || code == DIV
3807 || code == AND || code == IOR || code == XOR
3808 || code == SMAX || code == SMIN || code == UMAX || code == UMIN)
3809 && ((INTEGRAL_MODE_P (mode) && code != DIV)
3810 || (flag_unsafe_math_optimizations && FLOAT_MODE_P (mode))))
3812 if (GET_CODE (XEXP (x, 0)) == code)
3814 rtx other = XEXP (XEXP (x, 0), 0);
3815 rtx inner_op0 = XEXP (XEXP (x, 0), 1);
3816 rtx inner_op1 = XEXP (x, 1);
3819 /* Make sure we pass the constant operand if any as the second
3820 one if this is a commutative operation. */
3821 if (CONSTANT_P (inner_op0) && GET_RTX_CLASS (code) == 'c')
3823 rtx tem = inner_op0;
3824 inner_op0 = inner_op1;
3827 inner = simplify_binary_operation (code == MINUS ? PLUS
3828 : code == DIV ? MULT
3830 mode, inner_op0, inner_op1);
3832 /* For commutative operations, try the other pair if that one
3834 if (inner == 0 && GET_RTX_CLASS (code) == 'c')
3836 other = XEXP (XEXP (x, 0), 1);
3837 inner = simplify_binary_operation (code, mode,
3838 XEXP (XEXP (x, 0), 0),
3843 return gen_binary (code, mode, other, inner);
3847 /* A little bit of algebraic simplification here. */
3851 /* Ensure that our address has any ASHIFTs converted to MULT in case
3852 address-recognizing predicates are called later. */
3853 temp = make_compound_operation (XEXP (x, 0), MEM);
3854 SUBST (XEXP (x, 0), temp);
3858 if (op0_mode == VOIDmode)
3859 op0_mode = GET_MODE (SUBREG_REG (x));
3861 /* simplify_subreg can't use gen_lowpart_for_combine. */
3862 if (CONSTANT_P (SUBREG_REG (x))
3863 && subreg_lowpart_offset (mode, op0_mode) == SUBREG_BYTE (x))
3864 return gen_lowpart_for_combine (mode, SUBREG_REG (x));
3866 if (GET_MODE_CLASS (GET_MODE (SUBREG_REG (x))) == MODE_CC)
3870 temp = simplify_subreg (mode, SUBREG_REG (x), op0_mode,
3876 /* Note that we cannot do any narrowing for non-constants since
3877 we might have been counting on using the fact that some bits were
3878 zero. We now do this in the SET. */
3883 /* (not (plus X -1)) can become (neg X). */
3884 if (GET_CODE (XEXP (x, 0)) == PLUS
3885 && XEXP (XEXP (x, 0), 1) == constm1_rtx)
3886 return gen_rtx_NEG (mode, XEXP (XEXP (x, 0), 0));
3888 /* Similarly, (not (neg X)) is (plus X -1). */
3889 if (GET_CODE (XEXP (x, 0)) == NEG)
3890 return gen_rtx_PLUS (mode, XEXP (XEXP (x, 0), 0), constm1_rtx);
3892 /* (not (xor X C)) for C constant is (xor X D) with D = ~C. */
3893 if (GET_CODE (XEXP (x, 0)) == XOR
3894 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3895 && (temp = simplify_unary_operation (NOT, mode,
3896 XEXP (XEXP (x, 0), 1),
3898 return gen_binary (XOR, mode, XEXP (XEXP (x, 0), 0), temp);
3900 /* (not (ashift 1 X)) is (rotate ~1 X). We used to do this for operands
3901 other than 1, but that is not valid. We could do a similar
3902 simplification for (not (lshiftrt C X)) where C is just the sign bit,
3903 but this doesn't seem common enough to bother with. */
3904 if (GET_CODE (XEXP (x, 0)) == ASHIFT
3905 && XEXP (XEXP (x, 0), 0) == const1_rtx)
3906 return gen_rtx_ROTATE (mode, simplify_gen_unary (NOT, mode,
3908 XEXP (XEXP (x, 0), 1));
3910 if (GET_CODE (XEXP (x, 0)) == SUBREG
3911 && subreg_lowpart_p (XEXP (x, 0))
3912 && (GET_MODE_SIZE (GET_MODE (XEXP (x, 0)))
3913 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (x, 0)))))
3914 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == ASHIFT
3915 && XEXP (SUBREG_REG (XEXP (x, 0)), 0) == const1_rtx)
3917 enum machine_mode inner_mode = GET_MODE (SUBREG_REG (XEXP (x, 0)));
3919 x = gen_rtx_ROTATE (inner_mode,
3920 simplify_gen_unary (NOT, inner_mode, const1_rtx,
3922 XEXP (SUBREG_REG (XEXP (x, 0)), 1));
3923 return gen_lowpart_for_combine (mode, x);
3926 /* If STORE_FLAG_VALUE is -1, (not (comparison foo bar)) can be done by
3927 reversing the comparison code if valid. */
3928 if (STORE_FLAG_VALUE == -1
3929 && GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
3930 && (reversed = reversed_comparison (x, mode, XEXP (XEXP (x, 0), 0),
3931 XEXP (XEXP (x, 0), 1))))
3934 /* (not (ashiftrt foo C)) where C is the number of bits in FOO minus 1
3935 is (ge foo (const_int 0)) if STORE_FLAG_VALUE is -1, so we can
3936 perform the above simplification. */
3938 if (STORE_FLAG_VALUE == -1
3939 && GET_CODE (XEXP (x, 0)) == ASHIFTRT
3940 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3941 && INTVAL (XEXP (XEXP (x, 0), 1)) == GET_MODE_BITSIZE (mode) - 1)
3942 return gen_rtx_GE (mode, XEXP (XEXP (x, 0), 0), const0_rtx);
3944 /* Apply De Morgan's laws to reduce number of patterns for machines
3945 with negating logical insns (and-not, nand, etc.). If result has
3946 only one NOT, put it first, since that is how the patterns are
3949 if (GET_CODE (XEXP (x, 0)) == IOR || GET_CODE (XEXP (x, 0)) == AND)
3951 rtx in1 = XEXP (XEXP (x, 0), 0), in2 = XEXP (XEXP (x, 0), 1);
3952 enum machine_mode op_mode;
3954 op_mode = GET_MODE (in1);
3955 in1 = simplify_gen_unary (NOT, op_mode, in1, op_mode);
3957 op_mode = GET_MODE (in2);
3958 if (op_mode == VOIDmode)
3960 in2 = simplify_gen_unary (NOT, op_mode, in2, op_mode);
3962 if (GET_CODE (in2) == NOT && GET_CODE (in1) != NOT)
3965 in2 = in1; in1 = tem;
3968 return gen_rtx_fmt_ee (GET_CODE (XEXP (x, 0)) == IOR ? AND : IOR,
3974 /* (neg (plus X 1)) can become (not X). */
3975 if (GET_CODE (XEXP (x, 0)) == PLUS
3976 && XEXP (XEXP (x, 0), 1) == const1_rtx)
3977 return gen_rtx_NOT (mode, XEXP (XEXP (x, 0), 0));
3979 /* Similarly, (neg (not X)) is (plus X 1). */
3980 if (GET_CODE (XEXP (x, 0)) == NOT)
3981 return plus_constant (XEXP (XEXP (x, 0), 0), 1);
3983 /* (neg (minus X Y)) can become (minus Y X). This transformation
3984 isn't safe for modes with signed zeros, since if X and Y are
3985 both +0, (minus Y X) is the same as (minus X Y). If the rounding
3986 mode is towards +infinity (or -infinity) then the two expressions
3987 will be rounded differently. */
3988 if (GET_CODE (XEXP (x, 0)) == MINUS
3989 && !HONOR_SIGNED_ZEROS (mode)
3990 && !HONOR_SIGN_DEPENDENT_ROUNDING (mode))
3991 return gen_binary (MINUS, mode, XEXP (XEXP (x, 0), 1),
3992 XEXP (XEXP (x, 0), 0));
3994 /* (neg (xor A 1)) is (plus A -1) if A is known to be either 0 or 1. */
3995 if (GET_CODE (XEXP (x, 0)) == XOR && XEXP (XEXP (x, 0), 1) == const1_rtx
3996 && nonzero_bits (XEXP (XEXP (x, 0), 0), mode) == 1)
3997 return gen_binary (PLUS, mode, XEXP (XEXP (x, 0), 0), constm1_rtx);
3999 /* NEG commutes with ASHIFT since it is multiplication. Only do this
4000 if we can then eliminate the NEG (e.g.,
4001 if the operand is a constant). */
4003 if (GET_CODE (XEXP (x, 0)) == ASHIFT)
4005 temp = simplify_unary_operation (NEG, mode,
4006 XEXP (XEXP (x, 0), 0), mode);
4008 return gen_binary (ASHIFT, mode, temp, XEXP (XEXP (x, 0), 1));
4011 temp = expand_compound_operation (XEXP (x, 0));
4013 /* For C equal to the width of MODE minus 1, (neg (ashiftrt X C)) can be
4014 replaced by (lshiftrt X C). This will convert
4015 (neg (sign_extract X 1 Y)) to (zero_extract X 1 Y). */
4017 if (GET_CODE (temp) == ASHIFTRT
4018 && GET_CODE (XEXP (temp, 1)) == CONST_INT
4019 && INTVAL (XEXP (temp, 1)) == GET_MODE_BITSIZE (mode) - 1)
4020 return simplify_shift_const (temp, LSHIFTRT, mode, XEXP (temp, 0),
4021 INTVAL (XEXP (temp, 1)));
4023 /* If X has only a single bit that might be nonzero, say, bit I, convert
4024 (neg X) to (ashiftrt (ashift X C-I) C-I) where C is the bitsize of
4025 MODE minus 1. This will convert (neg (zero_extract X 1 Y)) to
4026 (sign_extract X 1 Y). But only do this if TEMP isn't a register
4027 or a SUBREG of one since we'd be making the expression more
4028 complex if it was just a register. */
4030 if (GET_CODE (temp) != REG
4031 && ! (GET_CODE (temp) == SUBREG
4032 && GET_CODE (SUBREG_REG (temp)) == REG)
4033 && (i = exact_log2 (nonzero_bits (temp, mode))) >= 0)
4035 rtx temp1 = simplify_shift_const
4036 (NULL_RTX, ASHIFTRT, mode,
4037 simplify_shift_const (NULL_RTX, ASHIFT, mode, temp,
4038 GET_MODE_BITSIZE (mode) - 1 - i),
4039 GET_MODE_BITSIZE (mode) - 1 - i);
4041 /* If all we did was surround TEMP with the two shifts, we
4042 haven't improved anything, so don't use it. Otherwise,
4043 we are better off with TEMP1. */
4044 if (GET_CODE (temp1) != ASHIFTRT
4045 || GET_CODE (XEXP (temp1, 0)) != ASHIFT
4046 || XEXP (XEXP (temp1, 0), 0) != temp)
4052 /* We can't handle truncation to a partial integer mode here
4053 because we don't know the real bitsize of the partial
4055 if (GET_MODE_CLASS (mode) == MODE_PARTIAL_INT)
4058 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4059 && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode),
4060 GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))))
4062 force_to_mode (XEXP (x, 0), GET_MODE (XEXP (x, 0)),
4063 GET_MODE_MASK (mode), NULL_RTX, 0));
4065 /* (truncate:SI ({sign,zero}_extend:DI foo:SI)) == foo:SI. */
4066 if ((GET_CODE (XEXP (x, 0)) == SIGN_EXTEND
4067 || GET_CODE (XEXP (x, 0)) == ZERO_EXTEND)
4068 && GET_MODE (XEXP (XEXP (x, 0), 0)) == mode)
4069 return XEXP (XEXP (x, 0), 0);
4071 /* (truncate:SI (OP:DI ({sign,zero}_extend:DI foo:SI))) is
4072 (OP:SI foo:SI) if OP is NEG or ABS. */
4073 if ((GET_CODE (XEXP (x, 0)) == ABS
4074 || GET_CODE (XEXP (x, 0)) == NEG)
4075 && (GET_CODE (XEXP (XEXP (x, 0), 0)) == SIGN_EXTEND
4076 || GET_CODE (XEXP (XEXP (x, 0), 0)) == ZERO_EXTEND)
4077 && GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == mode)
4078 return simplify_gen_unary (GET_CODE (XEXP (x, 0)), mode,
4079 XEXP (XEXP (XEXP (x, 0), 0), 0), mode);
4081 /* (truncate:SI (subreg:DI (truncate:SI X) 0)) is
4083 if (GET_CODE (XEXP (x, 0)) == SUBREG
4084 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == TRUNCATE
4085 && subreg_lowpart_p (XEXP (x, 0)))
4086 return SUBREG_REG (XEXP (x, 0));
4088 /* If we know that the value is already truncated, we can
4089 replace the TRUNCATE with a SUBREG if TRULY_NOOP_TRUNCATION
4090 is nonzero for the corresponding modes. But don't do this
4091 for an (LSHIFTRT (MULT ...)) since this will cause problems
4092 with the umulXi3_highpart patterns. */
4093 if (TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode),
4094 GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))))
4095 && num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
4096 >= GET_MODE_BITSIZE (mode) + 1
4097 && ! (GET_CODE (XEXP (x, 0)) == LSHIFTRT
4098 && GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT))
4099 return gen_lowpart_for_combine (mode, XEXP (x, 0));
4101 /* A truncate of a comparison can be replaced with a subreg if
4102 STORE_FLAG_VALUE permits. This is like the previous test,
4103 but it works even if the comparison is done in a mode larger
4104 than HOST_BITS_PER_WIDE_INT. */
4105 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4106 && GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
4107 && ((HOST_WIDE_INT) STORE_FLAG_VALUE & ~GET_MODE_MASK (mode)) == 0)
4108 return gen_lowpart_for_combine (mode, XEXP (x, 0));
4110 /* Similarly, a truncate of a register whose value is a
4111 comparison can be replaced with a subreg if STORE_FLAG_VALUE
4113 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4114 && ((HOST_WIDE_INT) STORE_FLAG_VALUE & ~GET_MODE_MASK (mode)) == 0
4115 && (temp = get_last_value (XEXP (x, 0)))
4116 && GET_RTX_CLASS (GET_CODE (temp)) == '<')
4117 return gen_lowpart_for_combine (mode, XEXP (x, 0));
4121 case FLOAT_TRUNCATE:
4122 /* (float_truncate:SF (float_extend:DF foo:SF)) = foo:SF. */
4123 if (GET_CODE (XEXP (x, 0)) == FLOAT_EXTEND
4124 && GET_MODE (XEXP (XEXP (x, 0), 0)) == mode)
4125 return XEXP (XEXP (x, 0), 0);
4127 /* (float_truncate:SF (OP:DF (float_extend:DF foo:sf))) is
4128 (OP:SF foo:SF) if OP is NEG or ABS. */
4129 if ((GET_CODE (XEXP (x, 0)) == ABS
4130 || GET_CODE (XEXP (x, 0)) == NEG)
4131 && GET_CODE (XEXP (XEXP (x, 0), 0)) == FLOAT_EXTEND
4132 && GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == mode)
4133 return simplify_gen_unary (GET_CODE (XEXP (x, 0)), mode,
4134 XEXP (XEXP (XEXP (x, 0), 0), 0), mode);
4136 /* (float_truncate:SF (subreg:DF (float_truncate:SF X) 0))
4137 is (float_truncate:SF x). */
4138 if (GET_CODE (XEXP (x, 0)) == SUBREG
4139 && subreg_lowpart_p (XEXP (x, 0))
4140 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == FLOAT_TRUNCATE)
4141 return SUBREG_REG (XEXP (x, 0));
4146 /* Convert (compare FOO (const_int 0)) to FOO unless we aren't
4147 using cc0, in which case we want to leave it as a COMPARE
4148 so we can distinguish it from a register-register-copy. */
4149 if (XEXP (x, 1) == const0_rtx)
4152 /* x - 0 is the same as x unless x's mode has signed zeros and
4153 allows rounding towards -infinity. Under those conditions,
4155 if (!(HONOR_SIGNED_ZEROS (GET_MODE (XEXP (x, 0)))
4156 && HONOR_SIGN_DEPENDENT_ROUNDING (GET_MODE (XEXP (x, 0))))
4157 && XEXP (x, 1) == CONST0_RTX (GET_MODE (XEXP (x, 0))))
4163 /* (const (const X)) can become (const X). Do it this way rather than
4164 returning the inner CONST since CONST can be shared with a
4166 if (GET_CODE (XEXP (x, 0)) == CONST)
4167 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4172 /* Convert (lo_sum (high FOO) FOO) to FOO. This is necessary so we
4173 can add in an offset. find_split_point will split this address up
4174 again if it doesn't match. */
4175 if (GET_CODE (XEXP (x, 0)) == HIGH
4176 && rtx_equal_p (XEXP (XEXP (x, 0), 0), XEXP (x, 1)))
4182 /* If we have (plus (plus (A const) B)), associate it so that CONST is
4183 outermost. That's because that's the way indexed addresses are
4184 supposed to appear. This code used to check many more cases, but
4185 they are now checked elsewhere. */
4186 if (GET_CODE (XEXP (x, 0)) == PLUS
4187 && CONSTANT_ADDRESS_P (XEXP (XEXP (x, 0), 1)))
4188 return gen_binary (PLUS, mode,
4189 gen_binary (PLUS, mode, XEXP (XEXP (x, 0), 0),
4191 XEXP (XEXP (x, 0), 1));
4193 /* (plus (xor (and <foo> (const_int pow2 - 1)) <c>) <-c>)
4194 when c is (const_int (pow2 + 1) / 2) is a sign extension of a
4195 bit-field and can be replaced by either a sign_extend or a
4196 sign_extract. The `and' may be a zero_extend and the two
4197 <c>, -<c> constants may be reversed. */
4198 if (GET_CODE (XEXP (x, 0)) == XOR
4199 && GET_CODE (XEXP (x, 1)) == CONST_INT
4200 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
4201 && INTVAL (XEXP (x, 1)) == -INTVAL (XEXP (XEXP (x, 0), 1))
4202 && ((i = exact_log2 (INTVAL (XEXP (XEXP (x, 0), 1)))) >= 0
4203 || (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0)
4204 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4205 && ((GET_CODE (XEXP (XEXP (x, 0), 0)) == AND
4206 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == CONST_INT
4207 && (INTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1))
4208 == ((HOST_WIDE_INT) 1 << (i + 1)) - 1))
4209 || (GET_CODE (XEXP (XEXP (x, 0), 0)) == ZERO_EXTEND
4210 && (GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)))
4211 == (unsigned int) i + 1))))
4212 return simplify_shift_const
4213 (NULL_RTX, ASHIFTRT, mode,
4214 simplify_shift_const (NULL_RTX, ASHIFT, mode,
4215 XEXP (XEXP (XEXP (x, 0), 0), 0),
4216 GET_MODE_BITSIZE (mode) - (i + 1)),
4217 GET_MODE_BITSIZE (mode) - (i + 1));
4219 /* (plus (comparison A B) C) can become (neg (rev-comp A B)) if
4220 C is 1 and STORE_FLAG_VALUE is -1 or if C is -1 and STORE_FLAG_VALUE
4221 is 1. This produces better code than the alternative immediately
4223 if (GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
4224 && ((STORE_FLAG_VALUE == -1 && XEXP (x, 1) == const1_rtx)
4225 || (STORE_FLAG_VALUE == 1 && XEXP (x, 1) == constm1_rtx))
4226 && (reversed = reversed_comparison (XEXP (x, 0), mode,
4227 XEXP (XEXP (x, 0), 0),
4228 XEXP (XEXP (x, 0), 1))))
4230 simplify_gen_unary (NEG, mode, reversed, mode);
4232 /* If only the low-order bit of X is possibly nonzero, (plus x -1)
4233 can become (ashiftrt (ashift (xor x 1) C) C) where C is
4234 the bitsize of the mode - 1. This allows simplification of
4235 "a = (b & 8) == 0;" */
4236 if (XEXP (x, 1) == constm1_rtx
4237 && GET_CODE (XEXP (x, 0)) != REG
4238 && ! (GET_CODE (XEXP (x,0)) == SUBREG
4239 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == REG)
4240 && nonzero_bits (XEXP (x, 0), mode) == 1)
4241 return simplify_shift_const (NULL_RTX, ASHIFTRT, mode,
4242 simplify_shift_const (NULL_RTX, ASHIFT, mode,
4243 gen_rtx_XOR (mode, XEXP (x, 0), const1_rtx),
4244 GET_MODE_BITSIZE (mode) - 1),
4245 GET_MODE_BITSIZE (mode) - 1);
4247 /* If we are adding two things that have no bits in common, convert
4248 the addition into an IOR. This will often be further simplified,
4249 for example in cases like ((a & 1) + (a & 2)), which can
4252 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4253 && (nonzero_bits (XEXP (x, 0), mode)
4254 & nonzero_bits (XEXP (x, 1), mode)) == 0)
4256 /* Try to simplify the expression further. */
4257 rtx tor = gen_binary (IOR, mode, XEXP (x, 0), XEXP (x, 1));
4258 temp = combine_simplify_rtx (tor, mode, last, in_dest);
4260 /* If we could, great. If not, do not go ahead with the IOR
4261 replacement, since PLUS appears in many special purpose
4262 address arithmetic instructions. */
4263 if (GET_CODE (temp) != CLOBBER && temp != tor)
4269 /* If STORE_FLAG_VALUE is 1, (minus 1 (comparison foo bar)) can be done
4270 by reversing the comparison code if valid. */
4271 if (STORE_FLAG_VALUE == 1
4272 && XEXP (x, 0) == const1_rtx
4273 && GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) == '<'
4274 && (reversed = reversed_comparison (XEXP (x, 1), mode,
4275 XEXP (XEXP (x, 1), 0),
4276 XEXP (XEXP (x, 1), 1))))
4279 /* (minus <foo> (and <foo> (const_int -pow2))) becomes
4280 (and <foo> (const_int pow2-1)) */
4281 if (GET_CODE (XEXP (x, 1)) == AND
4282 && GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT
4283 && exact_log2 (-INTVAL (XEXP (XEXP (x, 1), 1))) >= 0
4284 && rtx_equal_p (XEXP (XEXP (x, 1), 0), XEXP (x, 0)))
4285 return simplify_and_const_int (NULL_RTX, mode, XEXP (x, 0),
4286 -INTVAL (XEXP (XEXP (x, 1), 1)) - 1);
4288 /* Canonicalize (minus A (plus B C)) to (minus (minus A B) C) for
4290 if (GET_CODE (XEXP (x, 1)) == PLUS && INTEGRAL_MODE_P (mode))
4291 return gen_binary (MINUS, mode,
4292 gen_binary (MINUS, mode, XEXP (x, 0),
4293 XEXP (XEXP (x, 1), 0)),
4294 XEXP (XEXP (x, 1), 1));
4298 /* If we have (mult (plus A B) C), apply the distributive law and then
4299 the inverse distributive law to see if things simplify. This
4300 occurs mostly in addresses, often when unrolling loops. */
4302 if (GET_CODE (XEXP (x, 0)) == PLUS)
4304 x = apply_distributive_law
4305 (gen_binary (PLUS, mode,
4306 gen_binary (MULT, mode,
4307 XEXP (XEXP (x, 0), 0), XEXP (x, 1)),
4308 gen_binary (MULT, mode,
4309 XEXP (XEXP (x, 0), 1),
4310 copy_rtx (XEXP (x, 1)))));
4312 if (GET_CODE (x) != MULT)
4315 /* Try simplify a*(b/c) as (a*b)/c. */
4316 if (FLOAT_MODE_P (mode) && flag_unsafe_math_optimizations
4317 && GET_CODE (XEXP (x, 0)) == DIV)
4319 rtx tem = simplify_binary_operation (MULT, mode,
4320 XEXP (XEXP (x, 0), 0),
4323 return gen_binary (DIV, mode, tem, XEXP (XEXP (x, 0), 1));
4328 /* If this is a divide by a power of two, treat it as a shift if
4329 its first operand is a shift. */
4330 if (GET_CODE (XEXP (x, 1)) == CONST_INT
4331 && (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0
4332 && (GET_CODE (XEXP (x, 0)) == ASHIFT
4333 || GET_CODE (XEXP (x, 0)) == LSHIFTRT
4334 || GET_CODE (XEXP (x, 0)) == ASHIFTRT
4335 || GET_CODE (XEXP (x, 0)) == ROTATE
4336 || GET_CODE (XEXP (x, 0)) == ROTATERT))
4337 return simplify_shift_const (NULL_RTX, LSHIFTRT, mode, XEXP (x, 0), i);
4341 case GT: case GTU: case GE: case GEU:
4342 case LT: case LTU: case LE: case LEU:
4343 case UNEQ: case LTGT:
4344 case UNGT: case UNGE:
4345 case UNLT: case UNLE:
4346 case UNORDERED: case ORDERED:
4347 /* If the first operand is a condition code, we can't do anything
4349 if (GET_CODE (XEXP (x, 0)) == COMPARE
4350 || (GET_MODE_CLASS (GET_MODE (XEXP (x, 0))) != MODE_CC
4352 && XEXP (x, 0) != cc0_rtx
4356 rtx op0 = XEXP (x, 0);
4357 rtx op1 = XEXP (x, 1);
4358 enum rtx_code new_code;
4360 if (GET_CODE (op0) == COMPARE)
4361 op1 = XEXP (op0, 1), op0 = XEXP (op0, 0);
4363 /* Simplify our comparison, if possible. */
4364 new_code = simplify_comparison (code, &op0, &op1);
4366 /* If STORE_FLAG_VALUE is 1, we can convert (ne x 0) to simply X
4367 if only the low-order bit is possibly nonzero in X (such as when
4368 X is a ZERO_EXTRACT of one bit). Similarly, we can convert EQ to
4369 (xor X 1) or (minus 1 X); we use the former. Finally, if X is
4370 known to be either 0 or -1, NE becomes a NEG and EQ becomes
4373 Remove any ZERO_EXTRACT we made when thinking this was a
4374 comparison. It may now be simpler to use, e.g., an AND. If a
4375 ZERO_EXTRACT is indeed appropriate, it will be placed back by
4376 the call to make_compound_operation in the SET case. */
4378 if (STORE_FLAG_VALUE == 1
4379 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4380 && op1 == const0_rtx
4381 && mode == GET_MODE (op0)
4382 && nonzero_bits (op0, mode) == 1)
4383 return gen_lowpart_for_combine (mode,
4384 expand_compound_operation (op0));
4386 else if (STORE_FLAG_VALUE == 1
4387 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4388 && op1 == const0_rtx
4389 && mode == GET_MODE (op0)
4390 && (num_sign_bit_copies (op0, mode)
4391 == GET_MODE_BITSIZE (mode)))
4393 op0 = expand_compound_operation (op0);
4394 return simplify_gen_unary (NEG, mode,
4395 gen_lowpart_for_combine (mode, op0),
4399 else if (STORE_FLAG_VALUE == 1
4400 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
4401 && op1 == const0_rtx
4402 && mode == GET_MODE (op0)
4403 && nonzero_bits (op0, mode) == 1)
4405 op0 = expand_compound_operation (op0);
4406 return gen_binary (XOR, mode,
4407 gen_lowpart_for_combine (mode, op0),
4411 else if (STORE_FLAG_VALUE == 1
4412 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
4413 && op1 == const0_rtx
4414 && mode == GET_MODE (op0)
4415 && (num_sign_bit_copies (op0, mode)
4416 == GET_MODE_BITSIZE (mode)))
4418 op0 = expand_compound_operation (op0);
4419 return plus_constant (gen_lowpart_for_combine (mode, op0), 1);
4422 /* If STORE_FLAG_VALUE is -1, we have cases similar to
4424 if (STORE_FLAG_VALUE == -1
4425 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4426 && op1 == const0_rtx
4427 && (num_sign_bit_copies (op0, mode)
4428 == GET_MODE_BITSIZE (mode)))
4429 return gen_lowpart_for_combine (mode,
4430 expand_compound_operation (op0));
4432 else if (STORE_FLAG_VALUE == -1
4433 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4434 && op1 == const0_rtx
4435 && mode == GET_MODE (op0)
4436 && nonzero_bits (op0, mode) == 1)
4438 op0 = expand_compound_operation (op0);
4439 return simplify_gen_unary (NEG, mode,
4440 gen_lowpart_for_combine (mode, op0),
4444 else if (STORE_FLAG_VALUE == -1
4445 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
4446 && op1 == const0_rtx
4447 && mode == GET_MODE (op0)
4448 && (num_sign_bit_copies (op0, mode)
4449 == GET_MODE_BITSIZE (mode)))
4451 op0 = expand_compound_operation (op0);
4452 return simplify_gen_unary (NOT, mode,
4453 gen_lowpart_for_combine (mode, op0),
4457 /* If X is 0/1, (eq X 0) is X-1. */
4458 else if (STORE_FLAG_VALUE == -1
4459 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
4460 && op1 == const0_rtx
4461 && mode == GET_MODE (op0)
4462 && nonzero_bits (op0, mode) == 1)
4464 op0 = expand_compound_operation (op0);
4465 return plus_constant (gen_lowpart_for_combine (mode, op0), -1);
4468 /* If STORE_FLAG_VALUE says to just test the sign bit and X has just
4469 one bit that might be nonzero, we can convert (ne x 0) to
4470 (ashift x c) where C puts the bit in the sign bit. Remove any
4471 AND with STORE_FLAG_VALUE when we are done, since we are only
4472 going to test the sign bit. */
4473 if (new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4474 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4475 && ((STORE_FLAG_VALUE & GET_MODE_MASK (mode))
4476 == (unsigned HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE(mode)-1))
4477 && op1 == const0_rtx
4478 && mode == GET_MODE (op0)
4479 && (i = exact_log2 (nonzero_bits (op0, mode))) >= 0)
4481 x = simplify_shift_const (NULL_RTX, ASHIFT, mode,
4482 expand_compound_operation (op0),
4483 GET_MODE_BITSIZE (mode) - 1 - i);
4484 if (GET_CODE (x) == AND && XEXP (x, 1) == const_true_rtx)
4490 /* If the code changed, return a whole new comparison. */
4491 if (new_code != code)
4492 return gen_rtx_fmt_ee (new_code, mode, op0, op1);
4494 /* Otherwise, keep this operation, but maybe change its operands.
4495 This also converts (ne (compare FOO BAR) 0) to (ne FOO BAR). */
4496 SUBST (XEXP (x, 0), op0);
4497 SUBST (XEXP (x, 1), op1);
4502 return simplify_if_then_else (x);
4508 /* If we are processing SET_DEST, we are done. */
4512 return expand_compound_operation (x);
4515 return simplify_set (x);
4520 return simplify_logical (x, last);
4523 /* (abs (neg <foo>)) -> (abs <foo>) */
4524 if (GET_CODE (XEXP (x, 0)) == NEG)
4525 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4527 /* If the mode of the operand is VOIDmode (i.e. if it is ASM_OPERANDS),
4529 if (GET_MODE (XEXP (x, 0)) == VOIDmode)
4532 /* If operand is something known to be positive, ignore the ABS. */
4533 if (GET_CODE (XEXP (x, 0)) == FFS || GET_CODE (XEXP (x, 0)) == ABS
4534 || ((GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
4535 <= HOST_BITS_PER_WIDE_INT)
4536 && ((nonzero_bits (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
4537 & ((HOST_WIDE_INT) 1
4538 << (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - 1)))
4542 /* If operand is known to be only -1 or 0, convert ABS to NEG. */
4543 if (num_sign_bit_copies (XEXP (x, 0), mode) == GET_MODE_BITSIZE (mode))
4544 return gen_rtx_NEG (mode, XEXP (x, 0));
4549 /* (ffs (*_extend <X>)) = (ffs <X>) */
4550 if (GET_CODE (XEXP (x, 0)) == SIGN_EXTEND
4551 || GET_CODE (XEXP (x, 0)) == ZERO_EXTEND)
4552 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4556 /* (float (sign_extend <X>)) = (float <X>). */
4557 if (GET_CODE (XEXP (x, 0)) == SIGN_EXTEND)
4558 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4566 /* If this is a shift by a constant amount, simplify it. */
4567 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
4568 return simplify_shift_const (x, code, mode, XEXP (x, 0),
4569 INTVAL (XEXP (x, 1)));
4571 #ifdef SHIFT_COUNT_TRUNCATED
4572 else if (SHIFT_COUNT_TRUNCATED && GET_CODE (XEXP (x, 1)) != REG)
4574 force_to_mode (XEXP (x, 1), GET_MODE (x),
4576 << exact_log2 (GET_MODE_BITSIZE (GET_MODE (x))))
4585 rtx op0 = XEXP (x, 0);
4586 rtx op1 = XEXP (x, 1);
4589 if (GET_CODE (op1) != PARALLEL)
4591 len = XVECLEN (op1, 0);
4593 && GET_CODE (XVECEXP (op1, 0, 0)) == CONST_INT
4594 && GET_CODE (op0) == VEC_CONCAT)
4596 int offset = INTVAL (XVECEXP (op1, 0, 0)) * GET_MODE_SIZE (GET_MODE (x));
4598 /* Try to find the element in the VEC_CONCAT. */
4601 if (GET_MODE (op0) == GET_MODE (x))
4603 if (GET_CODE (op0) == VEC_CONCAT)
4605 HOST_WIDE_INT op0_size = GET_MODE_SIZE (GET_MODE (XEXP (op0, 0)));
4606 if (op0_size < offset)
4607 op0 = XEXP (op0, 0);
4611 op0 = XEXP (op0, 1);
4629 /* Simplify X, an IF_THEN_ELSE expression. Return the new expression. */
4632 simplify_if_then_else (x)
4635 enum machine_mode mode = GET_MODE (x);
4636 rtx cond = XEXP (x, 0);
4637 rtx true_rtx = XEXP (x, 1);
4638 rtx false_rtx = XEXP (x, 2);
4639 enum rtx_code true_code = GET_CODE (cond);
4640 int comparison_p = GET_RTX_CLASS (true_code) == '<';
4643 enum rtx_code false_code;
4646 /* Simplify storing of the truth value. */
4647 if (comparison_p && true_rtx == const_true_rtx && false_rtx == const0_rtx)
4648 return gen_binary (true_code, mode, XEXP (cond, 0), XEXP (cond, 1));
4650 /* Also when the truth value has to be reversed. */
4652 && true_rtx == const0_rtx && false_rtx == const_true_rtx
4653 && (reversed = reversed_comparison (cond, mode, XEXP (cond, 0),
4657 /* Sometimes we can simplify the arm of an IF_THEN_ELSE if a register used
4658 in it is being compared against certain values. Get the true and false
4659 comparisons and see if that says anything about the value of each arm. */
4662 && ((false_code = combine_reversed_comparison_code (cond))
4664 && GET_CODE (XEXP (cond, 0)) == REG)
4667 rtx from = XEXP (cond, 0);
4668 rtx true_val = XEXP (cond, 1);
4669 rtx false_val = true_val;
4672 /* If FALSE_CODE is EQ, swap the codes and arms. */
4674 if (false_code == EQ)
4676 swapped = 1, true_code = EQ, false_code = NE;
4677 temp = true_rtx, true_rtx = false_rtx, false_rtx = temp;
4680 /* If we are comparing against zero and the expression being tested has
4681 only a single bit that might be nonzero, that is its value when it is
4682 not equal to zero. Similarly if it is known to be -1 or 0. */
4684 if (true_code == EQ && true_val == const0_rtx
4685 && exact_log2 (nzb = nonzero_bits (from, GET_MODE (from))) >= 0)
4686 false_code = EQ, false_val = GEN_INT (nzb);
4687 else if (true_code == EQ && true_val == const0_rtx
4688 && (num_sign_bit_copies (from, GET_MODE (from))
4689 == GET_MODE_BITSIZE (GET_MODE (from))))
4690 false_code = EQ, false_val = constm1_rtx;
4692 /* Now simplify an arm if we know the value of the register in the
4693 branch and it is used in the arm. Be careful due to the potential
4694 of locally-shared RTL. */
4696 if (reg_mentioned_p (from, true_rtx))
4697 true_rtx = subst (known_cond (copy_rtx (true_rtx), true_code,
4699 pc_rtx, pc_rtx, 0, 0);
4700 if (reg_mentioned_p (from, false_rtx))
4701 false_rtx = subst (known_cond (copy_rtx (false_rtx), false_code,
4703 pc_rtx, pc_rtx, 0, 0);
4705 SUBST (XEXP (x, 1), swapped ? false_rtx : true_rtx);
4706 SUBST (XEXP (x, 2), swapped ? true_rtx : false_rtx);
4708 true_rtx = XEXP (x, 1);
4709 false_rtx = XEXP (x, 2);
4710 true_code = GET_CODE (cond);
4713 /* If we have (if_then_else FOO (pc) (label_ref BAR)) and FOO can be
4714 reversed, do so to avoid needing two sets of patterns for
4715 subtract-and-branch insns. Similarly if we have a constant in the true
4716 arm, the false arm is the same as the first operand of the comparison, or
4717 the false arm is more complicated than the true arm. */
4720 && combine_reversed_comparison_code (cond) != UNKNOWN
4721 && (true_rtx == pc_rtx
4722 || (CONSTANT_P (true_rtx)
4723 && GET_CODE (false_rtx) != CONST_INT && false_rtx != pc_rtx)
4724 || true_rtx == const0_rtx
4725 || (GET_RTX_CLASS (GET_CODE (true_rtx)) == 'o'
4726 && GET_RTX_CLASS (GET_CODE (false_rtx)) != 'o')
4727 || (GET_CODE (true_rtx) == SUBREG
4728 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (true_rtx))) == 'o'
4729 && GET_RTX_CLASS (GET_CODE (false_rtx)) != 'o')
4730 || reg_mentioned_p (true_rtx, false_rtx)
4731 || rtx_equal_p (false_rtx, XEXP (cond, 0))))
4733 true_code = reversed_comparison_code (cond, NULL);
4735 reversed_comparison (cond, GET_MODE (cond), XEXP (cond, 0),
4738 SUBST (XEXP (x, 1), false_rtx);
4739 SUBST (XEXP (x, 2), true_rtx);
4741 temp = true_rtx, true_rtx = false_rtx, false_rtx = temp;
4744 /* It is possible that the conditional has been simplified out. */
4745 true_code = GET_CODE (cond);
4746 comparison_p = GET_RTX_CLASS (true_code) == '<';
4749 /* If the two arms are identical, we don't need the comparison. */
4751 if (rtx_equal_p (true_rtx, false_rtx) && ! side_effects_p (cond))
4754 /* Convert a == b ? b : a to "a". */
4755 if (true_code == EQ && ! side_effects_p (cond)
4756 && (! FLOAT_MODE_P (mode) || flag_unsafe_math_optimizations)
4757 && rtx_equal_p (XEXP (cond, 0), false_rtx)
4758 && rtx_equal_p (XEXP (cond, 1), true_rtx))
4760 else if (true_code == NE && ! side_effects_p (cond)
4761 && (! FLOAT_MODE_P (mode) || flag_unsafe_math_optimizations)
4762 && rtx_equal_p (XEXP (cond, 0), true_rtx)
4763 && rtx_equal_p (XEXP (cond, 1), false_rtx))
4766 /* Look for cases where we have (abs x) or (neg (abs X)). */
4768 if (GET_MODE_CLASS (mode) == MODE_INT
4769 && GET_CODE (false_rtx) == NEG
4770 && rtx_equal_p (true_rtx, XEXP (false_rtx, 0))
4772 && rtx_equal_p (true_rtx, XEXP (cond, 0))
4773 && ! side_effects_p (true_rtx))
4778 return simplify_gen_unary (ABS, mode, true_rtx, mode);
4782 simplify_gen_unary (NEG, mode,
4783 simplify_gen_unary (ABS, mode, true_rtx, mode),
4789 /* Look for MIN or MAX. */
4791 if ((! FLOAT_MODE_P (mode) || flag_unsafe_math_optimizations)
4793 && rtx_equal_p (XEXP (cond, 0), true_rtx)
4794 && rtx_equal_p (XEXP (cond, 1), false_rtx)
4795 && ! side_effects_p (cond))
4800 return gen_binary (SMAX, mode, true_rtx, false_rtx);
4803 return gen_binary (SMIN, mode, true_rtx, false_rtx);
4806 return gen_binary (UMAX, mode, true_rtx, false_rtx);
4809 return gen_binary (UMIN, mode, true_rtx, false_rtx);
4814 /* If we have (if_then_else COND (OP Z C1) Z) and OP is an identity when its
4815 second operand is zero, this can be done as (OP Z (mult COND C2)) where
4816 C2 = C1 * STORE_FLAG_VALUE. Similarly if OP has an outer ZERO_EXTEND or
4817 SIGN_EXTEND as long as Z is already extended (so we don't destroy it).
4818 We can do this kind of thing in some cases when STORE_FLAG_VALUE is
4819 neither 1 or -1, but it isn't worth checking for. */
4821 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
4822 && comparison_p && mode != VOIDmode && ! side_effects_p (x))
4824 rtx t = make_compound_operation (true_rtx, SET);
4825 rtx f = make_compound_operation (false_rtx, SET);
4826 rtx cond_op0 = XEXP (cond, 0);
4827 rtx cond_op1 = XEXP (cond, 1);
4828 enum rtx_code op = NIL, extend_op = NIL;
4829 enum machine_mode m = mode;
4830 rtx z = 0, c1 = NULL_RTX;
4832 if ((GET_CODE (t) == PLUS || GET_CODE (t) == MINUS
4833 || GET_CODE (t) == IOR || GET_CODE (t) == XOR
4834 || GET_CODE (t) == ASHIFT
4835 || GET_CODE (t) == LSHIFTRT || GET_CODE (t) == ASHIFTRT)
4836 && rtx_equal_p (XEXP (t, 0), f))
4837 c1 = XEXP (t, 1), op = GET_CODE (t), z = f;
4839 /* If an identity-zero op is commutative, check whether there
4840 would be a match if we swapped the operands. */
4841 else if ((GET_CODE (t) == PLUS || GET_CODE (t) == IOR
4842 || GET_CODE (t) == XOR)
4843 && rtx_equal_p (XEXP (t, 1), f))
4844 c1 = XEXP (t, 0), op = GET_CODE (t), z = f;
4845 else if (GET_CODE (t) == SIGN_EXTEND
4846 && (GET_CODE (XEXP (t, 0)) == PLUS
4847 || GET_CODE (XEXP (t, 0)) == MINUS
4848 || GET_CODE (XEXP (t, 0)) == IOR
4849 || GET_CODE (XEXP (t, 0)) == XOR
4850 || GET_CODE (XEXP (t, 0)) == ASHIFT
4851 || GET_CODE (XEXP (t, 0)) == LSHIFTRT
4852 || GET_CODE (XEXP (t, 0)) == ASHIFTRT)
4853 && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG
4854 && subreg_lowpart_p (XEXP (XEXP (t, 0), 0))
4855 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f)
4856 && (num_sign_bit_copies (f, GET_MODE (f))
4857 > (GET_MODE_BITSIZE (mode)
4858 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t, 0), 0))))))
4860 c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0));
4861 extend_op = SIGN_EXTEND;
4862 m = GET_MODE (XEXP (t, 0));
4864 else if (GET_CODE (t) == SIGN_EXTEND
4865 && (GET_CODE (XEXP (t, 0)) == PLUS
4866 || GET_CODE (XEXP (t, 0)) == IOR
4867 || GET_CODE (XEXP (t, 0)) == XOR)
4868 && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG
4869 && subreg_lowpart_p (XEXP (XEXP (t, 0), 1))
4870 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f)
4871 && (num_sign_bit_copies (f, GET_MODE (f))
4872 > (GET_MODE_BITSIZE (mode)
4873 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t, 0), 1))))))
4875 c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0));
4876 extend_op = SIGN_EXTEND;
4877 m = GET_MODE (XEXP (t, 0));
4879 else if (GET_CODE (t) == ZERO_EXTEND
4880 && (GET_CODE (XEXP (t, 0)) == PLUS
4881 || GET_CODE (XEXP (t, 0)) == MINUS
4882 || GET_CODE (XEXP (t, 0)) == IOR
4883 || GET_CODE (XEXP (t, 0)) == XOR
4884 || GET_CODE (XEXP (t, 0)) == ASHIFT
4885 || GET_CODE (XEXP (t, 0)) == LSHIFTRT
4886 || GET_CODE (XEXP (t, 0)) == ASHIFTRT)
4887 && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG
4888 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4889 && subreg_lowpart_p (XEXP (XEXP (t, 0), 0))
4890 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f)
4891 && ((nonzero_bits (f, GET_MODE (f))
4892 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t, 0), 0))))
4895 c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0));
4896 extend_op = ZERO_EXTEND;
4897 m = GET_MODE (XEXP (t, 0));
4899 else if (GET_CODE (t) == ZERO_EXTEND
4900 && (GET_CODE (XEXP (t, 0)) == PLUS
4901 || GET_CODE (XEXP (t, 0)) == IOR
4902 || GET_CODE (XEXP (t, 0)) == XOR)
4903 && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG
4904 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4905 && subreg_lowpart_p (XEXP (XEXP (t, 0), 1))
4906 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f)
4907 && ((nonzero_bits (f, GET_MODE (f))
4908 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t, 0), 1))))
4911 c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0));
4912 extend_op = ZERO_EXTEND;
4913 m = GET_MODE (XEXP (t, 0));
4918 temp = subst (gen_binary (true_code, m, cond_op0, cond_op1),
4919 pc_rtx, pc_rtx, 0, 0);
4920 temp = gen_binary (MULT, m, temp,
4921 gen_binary (MULT, m, c1, const_true_rtx));
4922 temp = subst (temp, pc_rtx, pc_rtx, 0, 0);
4923 temp = gen_binary (op, m, gen_lowpart_for_combine (m, z), temp);
4925 if (extend_op != NIL)
4926 temp = simplify_gen_unary (extend_op, mode, temp, m);
4932 /* If we have (if_then_else (ne A 0) C1 0) and either A is known to be 0 or
4933 1 and C1 is a single bit or A is known to be 0 or -1 and C1 is the
4934 negation of a single bit, we can convert this operation to a shift. We
4935 can actually do this more generally, but it doesn't seem worth it. */
4937 if (true_code == NE && XEXP (cond, 1) == const0_rtx
4938 && false_rtx == const0_rtx && GET_CODE (true_rtx) == CONST_INT
4939 && ((1 == nonzero_bits (XEXP (cond, 0), mode)
4940 && (i = exact_log2 (INTVAL (true_rtx))) >= 0)
4941 || ((num_sign_bit_copies (XEXP (cond, 0), mode)
4942 == GET_MODE_BITSIZE (mode))
4943 && (i = exact_log2 (-INTVAL (true_rtx))) >= 0)))
4945 simplify_shift_const (NULL_RTX, ASHIFT, mode,
4946 gen_lowpart_for_combine (mode, XEXP (cond, 0)), i);
4951 /* Simplify X, a SET expression. Return the new expression. */
4957 rtx src = SET_SRC (x);
4958 rtx dest = SET_DEST (x);
4959 enum machine_mode mode
4960 = GET_MODE (src) != VOIDmode ? GET_MODE (src) : GET_MODE (dest);
4964 /* (set (pc) (return)) gets written as (return). */
4965 if (GET_CODE (dest) == PC && GET_CODE (src) == RETURN)
4968 /* Now that we know for sure which bits of SRC we are using, see if we can
4969 simplify the expression for the object knowing that we only need the
4972 if (GET_MODE_CLASS (mode) == MODE_INT)
4974 src = force_to_mode (src, mode, ~(HOST_WIDE_INT) 0, NULL_RTX, 0);
4975 SUBST (SET_SRC (x), src);
4978 /* If we are setting CC0 or if the source is a COMPARE, look for the use of
4979 the comparison result and try to simplify it unless we already have used
4980 undobuf.other_insn. */
4981 if ((GET_CODE (src) == COMPARE
4986 && (cc_use = find_single_use (dest, subst_insn, &other_insn)) != 0
4987 && (undobuf.other_insn == 0 || other_insn == undobuf.other_insn)
4988 && GET_RTX_CLASS (GET_CODE (*cc_use)) == '<'
4989 && rtx_equal_p (XEXP (*cc_use, 0), dest))
4991 enum rtx_code old_code = GET_CODE (*cc_use);
4992 enum rtx_code new_code;
4994 int other_changed = 0;
4995 enum machine_mode compare_mode = GET_MODE (dest);
4997 if (GET_CODE (src) == COMPARE)
4998 op0 = XEXP (src, 0), op1 = XEXP (src, 1);
5000 op0 = src, op1 = const0_rtx;
5002 /* Simplify our comparison, if possible. */
5003 new_code = simplify_comparison (old_code, &op0, &op1);
5005 #ifdef EXTRA_CC_MODES
5006 /* If this machine has CC modes other than CCmode, check to see if we
5007 need to use a different CC mode here. */
5008 compare_mode = SELECT_CC_MODE (new_code, op0, op1);
5009 #endif /* EXTRA_CC_MODES */
5011 #if !defined (HAVE_cc0) && defined (EXTRA_CC_MODES)
5012 /* If the mode changed, we have to change SET_DEST, the mode in the
5013 compare, and the mode in the place SET_DEST is used. If SET_DEST is
5014 a hard register, just build new versions with the proper mode. If it
5015 is a pseudo, we lose unless it is only time we set the pseudo, in
5016 which case we can safely change its mode. */
5017 if (compare_mode != GET_MODE (dest))
5019 unsigned int regno = REGNO (dest);
5020 rtx new_dest = gen_rtx_REG (compare_mode, regno);
5022 if (regno < FIRST_PSEUDO_REGISTER
5023 || (REG_N_SETS (regno) == 1 && ! REG_USERVAR_P (dest)))
5025 if (regno >= FIRST_PSEUDO_REGISTER)
5026 SUBST (regno_reg_rtx[regno], new_dest);
5028 SUBST (SET_DEST (x), new_dest);
5029 SUBST (XEXP (*cc_use, 0), new_dest);
5037 /* If the code changed, we have to build a new comparison in
5038 undobuf.other_insn. */
5039 if (new_code != old_code)
5041 unsigned HOST_WIDE_INT mask;
5043 SUBST (*cc_use, gen_rtx_fmt_ee (new_code, GET_MODE (*cc_use),
5046 /* If the only change we made was to change an EQ into an NE or
5047 vice versa, OP0 has only one bit that might be nonzero, and OP1
5048 is zero, check if changing the user of the condition code will
5049 produce a valid insn. If it won't, we can keep the original code
5050 in that insn by surrounding our operation with an XOR. */
5052 if (((old_code == NE && new_code == EQ)
5053 || (old_code == EQ && new_code == NE))
5054 && ! other_changed && op1 == const0_rtx
5055 && GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
5056 && exact_log2 (mask = nonzero_bits (op0, GET_MODE (op0))) >= 0)
5058 rtx pat = PATTERN (other_insn), note = 0;
5060 if ((recog_for_combine (&pat, other_insn, ¬e) < 0
5061 && ! check_asm_operands (pat)))
5063 PUT_CODE (*cc_use, old_code);
5066 op0 = gen_binary (XOR, GET_MODE (op0), op0, GEN_INT (mask));
5074 undobuf.other_insn = other_insn;
5077 /* If we are now comparing against zero, change our source if
5078 needed. If we do not use cc0, we always have a COMPARE. */
5079 if (op1 == const0_rtx && dest == cc0_rtx)
5081 SUBST (SET_SRC (x), op0);
5087 /* Otherwise, if we didn't previously have a COMPARE in the
5088 correct mode, we need one. */
5089 if (GET_CODE (src) != COMPARE || GET_MODE (src) != compare_mode)
5091 SUBST (SET_SRC (x), gen_rtx_COMPARE (compare_mode, op0, op1));
5096 /* Otherwise, update the COMPARE if needed. */
5097 SUBST (XEXP (src, 0), op0);
5098 SUBST (XEXP (src, 1), op1);
5103 /* Get SET_SRC in a form where we have placed back any
5104 compound expressions. Then do the checks below. */
5105 src = make_compound_operation (src, SET);
5106 SUBST (SET_SRC (x), src);
5109 /* If we have (set x (subreg:m1 (op:m2 ...) 0)) with OP being some operation,
5110 and X being a REG or (subreg (reg)), we may be able to convert this to
5111 (set (subreg:m2 x) (op)).
5113 We can always do this if M1 is narrower than M2 because that means that
5114 we only care about the low bits of the result.
5116 However, on machines without WORD_REGISTER_OPERATIONS defined, we cannot
5117 perform a narrower operation than requested since the high-order bits will
5118 be undefined. On machine where it is defined, this transformation is safe
5119 as long as M1 and M2 have the same number of words. */
5121 if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src)
5122 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (src))) != 'o'
5123 && (((GET_MODE_SIZE (GET_MODE (src)) + (UNITS_PER_WORD - 1))
5125 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (src)))
5126 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD))
5127 #ifndef WORD_REGISTER_OPERATIONS
5128 && (GET_MODE_SIZE (GET_MODE (src))
5129 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (src))))
5131 #ifdef CLASS_CANNOT_CHANGE_MODE
5132 && ! (GET_CODE (dest) == REG && REGNO (dest) < FIRST_PSEUDO_REGISTER
5133 && (TEST_HARD_REG_BIT
5134 (reg_class_contents[(int) CLASS_CANNOT_CHANGE_MODE],
5136 && CLASS_CANNOT_CHANGE_MODE_P (GET_MODE (src),
5137 GET_MODE (SUBREG_REG (src))))
5139 && (GET_CODE (dest) == REG
5140 || (GET_CODE (dest) == SUBREG
5141 && GET_CODE (SUBREG_REG (dest)) == REG)))
5143 SUBST (SET_DEST (x),
5144 gen_lowpart_for_combine (GET_MODE (SUBREG_REG (src)),
5146 SUBST (SET_SRC (x), SUBREG_REG (src));
5148 src = SET_SRC (x), dest = SET_DEST (x);
5151 #ifdef LOAD_EXTEND_OP
5152 /* If we have (set FOO (subreg:M (mem:N BAR) 0)) with M wider than N, this
5153 would require a paradoxical subreg. Replace the subreg with a
5154 zero_extend to avoid the reload that would otherwise be required. */
5156 if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src)
5157 && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src))) != NIL
5158 && SUBREG_BYTE (src) == 0
5159 && (GET_MODE_SIZE (GET_MODE (src))
5160 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (src))))
5161 && GET_CODE (SUBREG_REG (src)) == MEM)
5164 gen_rtx (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src))),
5165 GET_MODE (src), SUBREG_REG (src)));
5171 /* If we don't have a conditional move, SET_SRC is an IF_THEN_ELSE, and we
5172 are comparing an item known to be 0 or -1 against 0, use a logical
5173 operation instead. Check for one of the arms being an IOR of the other
5174 arm with some value. We compute three terms to be IOR'ed together. In
5175 practice, at most two will be nonzero. Then we do the IOR's. */
5177 if (GET_CODE (dest) != PC
5178 && GET_CODE (src) == IF_THEN_ELSE
5179 && GET_MODE_CLASS (GET_MODE (src)) == MODE_INT
5180 && (GET_CODE (XEXP (src, 0)) == EQ || GET_CODE (XEXP (src, 0)) == NE)
5181 && XEXP (XEXP (src, 0), 1) == const0_rtx
5182 && GET_MODE (src) == GET_MODE (XEXP (XEXP (src, 0), 0))
5183 #ifdef HAVE_conditional_move
5184 && ! can_conditionally_move_p (GET_MODE (src))
5186 && (num_sign_bit_copies (XEXP (XEXP (src, 0), 0),
5187 GET_MODE (XEXP (XEXP (src, 0), 0)))
5188 == GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (src, 0), 0))))
5189 && ! side_effects_p (src))
5191 rtx true_rtx = (GET_CODE (XEXP (src, 0)) == NE
5192 ? XEXP (src, 1) : XEXP (src, 2));
5193 rtx false_rtx = (GET_CODE (XEXP (src, 0)) == NE
5194 ? XEXP (src, 2) : XEXP (src, 1));
5195 rtx term1 = const0_rtx, term2, term3;
5197 if (GET_CODE (true_rtx) == IOR
5198 && rtx_equal_p (XEXP (true_rtx, 0), false_rtx))
5199 term1 = false_rtx, true_rtx = XEXP(true_rtx, 1), false_rtx = const0_rtx;
5200 else if (GET_CODE (true_rtx) == IOR
5201 && rtx_equal_p (XEXP (true_rtx, 1), false_rtx))
5202 term1 = false_rtx, true_rtx = XEXP(true_rtx, 0), false_rtx = const0_rtx;
5203 else if (GET_CODE (false_rtx) == IOR
5204 && rtx_equal_p (XEXP (false_rtx, 0), true_rtx))
5205 term1 = true_rtx, false_rtx = XEXP(false_rtx, 1), true_rtx = const0_rtx;
5206 else if (GET_CODE (false_rtx) == IOR
5207 && rtx_equal_p (XEXP (false_rtx, 1), true_rtx))
5208 term1 = true_rtx, false_rtx = XEXP(false_rtx, 0), true_rtx = const0_rtx;
5210 term2 = gen_binary (AND, GET_MODE (src),
5211 XEXP (XEXP (src, 0), 0), true_rtx);
5212 term3 = gen_binary (AND, GET_MODE (src),
5213 simplify_gen_unary (NOT, GET_MODE (src),
5214 XEXP (XEXP (src, 0), 0),
5219 gen_binary (IOR, GET_MODE (src),
5220 gen_binary (IOR, GET_MODE (src), term1, term2),
5226 /* If either SRC or DEST is a CLOBBER of (const_int 0), make this
5227 whole thing fail. */
5228 if (GET_CODE (src) == CLOBBER && XEXP (src, 0) == const0_rtx)
5230 else if (GET_CODE (dest) == CLOBBER && XEXP (dest, 0) == const0_rtx)
5233 /* Convert this into a field assignment operation, if possible. */
5234 return make_field_assignment (x);
5237 /* Simplify, X, and AND, IOR, or XOR operation, and return the simplified
5238 result. LAST is nonzero if this is the last retry. */
5241 simplify_logical (x, last)
5245 enum machine_mode mode = GET_MODE (x);
5246 rtx op0 = XEXP (x, 0);
5247 rtx op1 = XEXP (x, 1);
5250 switch (GET_CODE (x))
5253 /* Convert (A ^ B) & A to A & (~B) since the latter is often a single
5254 insn (and may simplify more). */
5255 if (GET_CODE (op0) == XOR
5256 && rtx_equal_p (XEXP (op0, 0), op1)
5257 && ! side_effects_p (op1))
5258 x = gen_binary (AND, mode,
5259 simplify_gen_unary (NOT, mode, XEXP (op0, 1), mode),
5262 if (GET_CODE (op0) == XOR
5263 && rtx_equal_p (XEXP (op0, 1), op1)
5264 && ! side_effects_p (op1))
5265 x = gen_binary (AND, mode,
5266 simplify_gen_unary (NOT, mode, XEXP (op0, 0), mode),
5269 /* Similarly for (~(A ^ B)) & A. */
5270 if (GET_CODE (op0) == NOT
5271 && GET_CODE (XEXP (op0, 0)) == XOR
5272 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), op1)
5273 && ! side_effects_p (op1))
5274 x = gen_binary (AND, mode, XEXP (XEXP (op0, 0), 1), op1);
5276 if (GET_CODE (op0) == NOT
5277 && GET_CODE (XEXP (op0, 0)) == XOR
5278 && rtx_equal_p (XEXP (XEXP (op0, 0), 1), op1)
5279 && ! side_effects_p (op1))
5280 x = gen_binary (AND, mode, XEXP (XEXP (op0, 0), 0), op1);
5282 /* We can call simplify_and_const_int only if we don't lose
5283 any (sign) bits when converting INTVAL (op1) to
5284 "unsigned HOST_WIDE_INT". */
5285 if (GET_CODE (op1) == CONST_INT
5286 && (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5287 || INTVAL (op1) > 0))
5289 x = simplify_and_const_int (x, mode, op0, INTVAL (op1));
5291 /* If we have (ior (and (X C1) C2)) and the next restart would be
5292 the last, simplify this by making C1 as small as possible
5295 && GET_CODE (x) == IOR && GET_CODE (op0) == AND
5296 && GET_CODE (XEXP (op0, 1)) == CONST_INT
5297 && GET_CODE (op1) == CONST_INT)
5298 return gen_binary (IOR, mode,
5299 gen_binary (AND, mode, XEXP (op0, 0),
5300 GEN_INT (INTVAL (XEXP (op0, 1))
5301 & ~INTVAL (op1))), op1);
5303 if (GET_CODE (x) != AND)
5306 if (GET_RTX_CLASS (GET_CODE (x)) == 'c'
5307 || GET_RTX_CLASS (GET_CODE (x)) == '2')
5308 op0 = XEXP (x, 0), op1 = XEXP (x, 1);
5311 /* Convert (A | B) & A to A. */
5312 if (GET_CODE (op0) == IOR
5313 && (rtx_equal_p (XEXP (op0, 0), op1)
5314 || rtx_equal_p (XEXP (op0, 1), op1))
5315 && ! side_effects_p (XEXP (op0, 0))
5316 && ! side_effects_p (XEXP (op0, 1)))
5319 /* In the following group of tests (and those in case IOR below),
5320 we start with some combination of logical operations and apply
5321 the distributive law followed by the inverse distributive law.
5322 Most of the time, this results in no change. However, if some of
5323 the operands are the same or inverses of each other, simplifications
5326 For example, (and (ior A B) (not B)) can occur as the result of
5327 expanding a bit field assignment. When we apply the distributive
5328 law to this, we get (ior (and (A (not B))) (and (B (not B)))),
5329 which then simplifies to (and (A (not B))).
5331 If we have (and (ior A B) C), apply the distributive law and then
5332 the inverse distributive law to see if things simplify. */
5334 if (GET_CODE (op0) == IOR || GET_CODE (op0) == XOR)
5336 x = apply_distributive_law
5337 (gen_binary (GET_CODE (op0), mode,
5338 gen_binary (AND, mode, XEXP (op0, 0), op1),
5339 gen_binary (AND, mode, XEXP (op0, 1),
5341 if (GET_CODE (x) != AND)
5345 if (GET_CODE (op1) == IOR || GET_CODE (op1) == XOR)
5346 return apply_distributive_law
5347 (gen_binary (GET_CODE (op1), mode,
5348 gen_binary (AND, mode, XEXP (op1, 0), op0),
5349 gen_binary (AND, mode, XEXP (op1, 1),
5352 /* Similarly, taking advantage of the fact that
5353 (and (not A) (xor B C)) == (xor (ior A B) (ior A C)) */
5355 if (GET_CODE (op0) == NOT && GET_CODE (op1) == XOR)
5356 return apply_distributive_law
5357 (gen_binary (XOR, mode,
5358 gen_binary (IOR, mode, XEXP (op0, 0), XEXP (op1, 0)),
5359 gen_binary (IOR, mode, copy_rtx (XEXP (op0, 0)),
5362 else if (GET_CODE (op1) == NOT && GET_CODE (op0) == XOR)
5363 return apply_distributive_law
5364 (gen_binary (XOR, mode,
5365 gen_binary (IOR, mode, XEXP (op1, 0), XEXP (op0, 0)),
5366 gen_binary (IOR, mode, copy_rtx (XEXP (op1, 0)), XEXP (op0, 1))));
5370 /* (ior A C) is C if all bits of A that might be nonzero are on in C. */
5371 if (GET_CODE (op1) == CONST_INT
5372 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5373 && (nonzero_bits (op0, mode) & ~INTVAL (op1)) == 0)
5376 /* Convert (A & B) | A to A. */
5377 if (GET_CODE (op0) == AND
5378 && (rtx_equal_p (XEXP (op0, 0), op1)
5379 || rtx_equal_p (XEXP (op0, 1), op1))
5380 && ! side_effects_p (XEXP (op0, 0))
5381 && ! side_effects_p (XEXP (op0, 1)))
5384 /* If we have (ior (and A B) C), apply the distributive law and then
5385 the inverse distributive law to see if things simplify. */
5387 if (GET_CODE (op0) == AND)
5389 x = apply_distributive_law
5390 (gen_binary (AND, mode,
5391 gen_binary (IOR, mode, XEXP (op0, 0), op1),
5392 gen_binary (IOR, mode, XEXP (op0, 1),
5395 if (GET_CODE (x) != IOR)
5399 if (GET_CODE (op1) == AND)
5401 x = apply_distributive_law
5402 (gen_binary (AND, mode,
5403 gen_binary (IOR, mode, XEXP (op1, 0), op0),
5404 gen_binary (IOR, mode, XEXP (op1, 1),
5407 if (GET_CODE (x) != IOR)
5411 /* Convert (ior (ashift A CX) (lshiftrt A CY)) where CX+CY equals the
5412 mode size to (rotate A CX). */
5414 if (((GET_CODE (op0) == ASHIFT && GET_CODE (op1) == LSHIFTRT)
5415 || (GET_CODE (op1) == ASHIFT && GET_CODE (op0) == LSHIFTRT))
5416 && rtx_equal_p (XEXP (op0, 0), XEXP (op1, 0))
5417 && GET_CODE (XEXP (op0, 1)) == CONST_INT
5418 && GET_CODE (XEXP (op1, 1)) == CONST_INT
5419 && (INTVAL (XEXP (op0, 1)) + INTVAL (XEXP (op1, 1))
5420 == GET_MODE_BITSIZE (mode)))
5421 return gen_rtx_ROTATE (mode, XEXP (op0, 0),
5422 (GET_CODE (op0) == ASHIFT
5423 ? XEXP (op0, 1) : XEXP (op1, 1)));
5425 /* If OP0 is (ashiftrt (plus ...) C), it might actually be
5426 a (sign_extend (plus ...)). If so, OP1 is a CONST_INT, and the PLUS
5427 does not affect any of the bits in OP1, it can really be done
5428 as a PLUS and we can associate. We do this by seeing if OP1
5429 can be safely shifted left C bits. */
5430 if (GET_CODE (op1) == CONST_INT && GET_CODE (op0) == ASHIFTRT
5431 && GET_CODE (XEXP (op0, 0)) == PLUS
5432 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
5433 && GET_CODE (XEXP (op0, 1)) == CONST_INT
5434 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT)
5436 int count = INTVAL (XEXP (op0, 1));
5437 HOST_WIDE_INT mask = INTVAL (op1) << count;
5439 if (mask >> count == INTVAL (op1)
5440 && (mask & nonzero_bits (XEXP (op0, 0), mode)) == 0)
5442 SUBST (XEXP (XEXP (op0, 0), 1),
5443 GEN_INT (INTVAL (XEXP (XEXP (op0, 0), 1)) | mask));
5450 /* If we are XORing two things that have no bits in common,
5451 convert them into an IOR. This helps to detect rotation encoded
5452 using those methods and possibly other simplifications. */
5454 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5455 && (nonzero_bits (op0, mode)
5456 & nonzero_bits (op1, mode)) == 0)
5457 return (gen_binary (IOR, mode, op0, op1));
5459 /* Convert (XOR (NOT x) (NOT y)) to (XOR x y).
5460 Also convert (XOR (NOT x) y) to (NOT (XOR x y)), similarly for
5463 int num_negated = 0;
5465 if (GET_CODE (op0) == NOT)
5466 num_negated++, op0 = XEXP (op0, 0);
5467 if (GET_CODE (op1) == NOT)
5468 num_negated++, op1 = XEXP (op1, 0);
5470 if (num_negated == 2)
5472 SUBST (XEXP (x, 0), op0);
5473 SUBST (XEXP (x, 1), op1);
5475 else if (num_negated == 1)
5477 simplify_gen_unary (NOT, mode, gen_binary (XOR, mode, op0, op1),
5481 /* Convert (xor (and A B) B) to (and (not A) B). The latter may
5482 correspond to a machine insn or result in further simplifications
5483 if B is a constant. */
5485 if (GET_CODE (op0) == AND
5486 && rtx_equal_p (XEXP (op0, 1), op1)
5487 && ! side_effects_p (op1))
5488 return gen_binary (AND, mode,
5489 simplify_gen_unary (NOT, mode, XEXP (op0, 0), mode),
5492 else if (GET_CODE (op0) == AND
5493 && rtx_equal_p (XEXP (op0, 0), op1)
5494 && ! side_effects_p (op1))
5495 return gen_binary (AND, mode,
5496 simplify_gen_unary (NOT, mode, XEXP (op0, 1), mode),
5499 /* (xor (comparison foo bar) (const_int 1)) can become the reversed
5500 comparison if STORE_FLAG_VALUE is 1. */
5501 if (STORE_FLAG_VALUE == 1
5502 && op1 == const1_rtx
5503 && GET_RTX_CLASS (GET_CODE (op0)) == '<'
5504 && (reversed = reversed_comparison (op0, mode, XEXP (op0, 0),
5508 /* (lshiftrt foo C) where C is the number of bits in FOO minus 1
5509 is (lt foo (const_int 0)), so we can perform the above
5510 simplification if STORE_FLAG_VALUE is 1. */
5512 if (STORE_FLAG_VALUE == 1
5513 && op1 == const1_rtx
5514 && GET_CODE (op0) == LSHIFTRT
5515 && GET_CODE (XEXP (op0, 1)) == CONST_INT
5516 && INTVAL (XEXP (op0, 1)) == GET_MODE_BITSIZE (mode) - 1)
5517 return gen_rtx_GE (mode, XEXP (op0, 0), const0_rtx);
5519 /* (xor (comparison foo bar) (const_int sign-bit))
5520 when STORE_FLAG_VALUE is the sign bit. */
5521 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5522 && ((STORE_FLAG_VALUE & GET_MODE_MASK (mode))
5523 == (unsigned HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (mode) - 1))
5524 && op1 == const_true_rtx
5525 && GET_RTX_CLASS (GET_CODE (op0)) == '<'
5526 && (reversed = reversed_comparison (op0, mode, XEXP (op0, 0),
5539 /* We consider ZERO_EXTRACT, SIGN_EXTRACT, and SIGN_EXTEND as "compound
5540 operations" because they can be replaced with two more basic operations.
5541 ZERO_EXTEND is also considered "compound" because it can be replaced with
5542 an AND operation, which is simpler, though only one operation.
5544 The function expand_compound_operation is called with an rtx expression
5545 and will convert it to the appropriate shifts and AND operations,
5546 simplifying at each stage.
5548 The function make_compound_operation is called to convert an expression
5549 consisting of shifts and ANDs into the equivalent compound expression.
5550 It is the inverse of this function, loosely speaking. */
5553 expand_compound_operation (x)
5556 unsigned HOST_WIDE_INT pos = 0, len;
5558 unsigned int modewidth;
5561 switch (GET_CODE (x))
5566 /* We can't necessarily use a const_int for a multiword mode;
5567 it depends on implicitly extending the value.
5568 Since we don't know the right way to extend it,
5569 we can't tell whether the implicit way is right.
5571 Even for a mode that is no wider than a const_int,
5572 we can't win, because we need to sign extend one of its bits through
5573 the rest of it, and we don't know which bit. */
5574 if (GET_CODE (XEXP (x, 0)) == CONST_INT)
5577 /* Return if (subreg:MODE FROM 0) is not a safe replacement for
5578 (zero_extend:MODE FROM) or (sign_extend:MODE FROM). It is for any MEM
5579 because (SUBREG (MEM...)) is guaranteed to cause the MEM to be
5580 reloaded. If not for that, MEM's would very rarely be safe.
5582 Reject MODEs bigger than a word, because we might not be able
5583 to reference a two-register group starting with an arbitrary register
5584 (and currently gen_lowpart might crash for a SUBREG). */
5586 if (GET_MODE_SIZE (GET_MODE (XEXP (x, 0))) > UNITS_PER_WORD)
5589 len = GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)));
5590 /* If the inner object has VOIDmode (the only way this can happen
5591 is if it is a ASM_OPERANDS), we can't do anything since we don't
5592 know how much masking to do. */
5601 /* If the operand is a CLOBBER, just return it. */
5602 if (GET_CODE (XEXP (x, 0)) == CLOBBER)
5605 if (GET_CODE (XEXP (x, 1)) != CONST_INT
5606 || GET_CODE (XEXP (x, 2)) != CONST_INT
5607 || GET_MODE (XEXP (x, 0)) == VOIDmode)
5610 len = INTVAL (XEXP (x, 1));
5611 pos = INTVAL (XEXP (x, 2));
5613 /* If this goes outside the object being extracted, replace the object
5614 with a (use (mem ...)) construct that only combine understands
5615 and is used only for this purpose. */
5616 if (len + pos > GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))))
5617 SUBST (XEXP (x, 0), gen_rtx_USE (GET_MODE (x), XEXP (x, 0)));
5619 if (BITS_BIG_ENDIAN)
5620 pos = GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - len - pos;
5627 /* Convert sign extension to zero extension, if we know that the high
5628 bit is not set, as this is easier to optimize. It will be converted
5629 back to cheaper alternative in make_extraction. */
5630 if (GET_CODE (x) == SIGN_EXTEND
5631 && (GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
5632 && ((nonzero_bits (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
5633 & ~(((unsigned HOST_WIDE_INT)
5634 GET_MODE_MASK (GET_MODE (XEXP (x, 0))))
5638 rtx temp = gen_rtx_ZERO_EXTEND (GET_MODE (x), XEXP (x, 0));
5639 return expand_compound_operation (temp);
5642 /* We can optimize some special cases of ZERO_EXTEND. */
5643 if (GET_CODE (x) == ZERO_EXTEND)
5645 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI if we
5646 know that the last value didn't have any inappropriate bits
5648 if (GET_CODE (XEXP (x, 0)) == TRUNCATE
5649 && GET_MODE (XEXP (XEXP (x, 0), 0)) == GET_MODE (x)
5650 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
5651 && (nonzero_bits (XEXP (XEXP (x, 0), 0), GET_MODE (x))
5652 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5653 return XEXP (XEXP (x, 0), 0);
5655 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
5656 if (GET_CODE (XEXP (x, 0)) == SUBREG
5657 && GET_MODE (SUBREG_REG (XEXP (x, 0))) == GET_MODE (x)
5658 && subreg_lowpart_p (XEXP (x, 0))
5659 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
5660 && (nonzero_bits (SUBREG_REG (XEXP (x, 0)), GET_MODE (x))
5661 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5662 return SUBREG_REG (XEXP (x, 0));
5664 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI when foo
5665 is a comparison and STORE_FLAG_VALUE permits. This is like
5666 the first case, but it works even when GET_MODE (x) is larger
5667 than HOST_WIDE_INT. */
5668 if (GET_CODE (XEXP (x, 0)) == TRUNCATE
5669 && GET_MODE (XEXP (XEXP (x, 0), 0)) == GET_MODE (x)
5670 && GET_RTX_CLASS (GET_CODE (XEXP (XEXP (x, 0), 0))) == '<'
5671 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
5672 <= HOST_BITS_PER_WIDE_INT)
5673 && ((HOST_WIDE_INT) STORE_FLAG_VALUE
5674 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5675 return XEXP (XEXP (x, 0), 0);
5677 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
5678 if (GET_CODE (XEXP (x, 0)) == SUBREG
5679 && GET_MODE (SUBREG_REG (XEXP (x, 0))) == GET_MODE (x)
5680 && subreg_lowpart_p (XEXP (x, 0))
5681 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 0)))) == '<'
5682 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
5683 <= HOST_BITS_PER_WIDE_INT)
5684 && ((HOST_WIDE_INT) STORE_FLAG_VALUE
5685 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5686 return SUBREG_REG (XEXP (x, 0));
5690 /* If we reach here, we want to return a pair of shifts. The inner
5691 shift is a left shift of BITSIZE - POS - LEN bits. The outer
5692 shift is a right shift of BITSIZE - LEN bits. It is arithmetic or
5693 logical depending on the value of UNSIGNEDP.
5695 If this was a ZERO_EXTEND or ZERO_EXTRACT, this pair of shifts will be
5696 converted into an AND of a shift.
5698 We must check for the case where the left shift would have a negative
5699 count. This can happen in a case like (x >> 31) & 255 on machines
5700 that can't shift by a constant. On those machines, we would first
5701 combine the shift with the AND to produce a variable-position
5702 extraction. Then the constant of 31 would be substituted in to produce
5703 a such a position. */
5705 modewidth = GET_MODE_BITSIZE (GET_MODE (x));
5706 if (modewidth + len >= pos)
5707 tem = simplify_shift_const (NULL_RTX, unsignedp ? LSHIFTRT : ASHIFTRT,
5709 simplify_shift_const (NULL_RTX, ASHIFT,
5712 modewidth - pos - len),
5715 else if (unsignedp && len < HOST_BITS_PER_WIDE_INT)
5716 tem = simplify_and_const_int (NULL_RTX, GET_MODE (x),
5717 simplify_shift_const (NULL_RTX, LSHIFTRT,
5720 ((HOST_WIDE_INT) 1 << len) - 1);
5722 /* Any other cases we can't handle. */
5725 /* If we couldn't do this for some reason, return the original
5727 if (GET_CODE (tem) == CLOBBER)
5733 /* X is a SET which contains an assignment of one object into
5734 a part of another (such as a bit-field assignment, STRICT_LOW_PART,
5735 or certain SUBREGS). If possible, convert it into a series of
5738 We half-heartedly support variable positions, but do not at all
5739 support variable lengths. */
5742 expand_field_assignment (x)
5746 rtx pos; /* Always counts from low bit. */
5749 enum machine_mode compute_mode;
5751 /* Loop until we find something we can't simplify. */
5754 if (GET_CODE (SET_DEST (x)) == STRICT_LOW_PART
5755 && GET_CODE (XEXP (SET_DEST (x), 0)) == SUBREG)
5757 inner = SUBREG_REG (XEXP (SET_DEST (x), 0));
5758 len = GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0)));
5759 pos = GEN_INT (subreg_lsb (XEXP (SET_DEST (x), 0)));
5761 else if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
5762 && GET_CODE (XEXP (SET_DEST (x), 1)) == CONST_INT)
5764 inner = XEXP (SET_DEST (x), 0);
5765 len = INTVAL (XEXP (SET_DEST (x), 1));
5766 pos = XEXP (SET_DEST (x), 2);
5768 /* If the position is constant and spans the width of INNER,
5769 surround INNER with a USE to indicate this. */
5770 if (GET_CODE (pos) == CONST_INT
5771 && INTVAL (pos) + len > GET_MODE_BITSIZE (GET_MODE (inner)))
5772 inner = gen_rtx_USE (GET_MODE (SET_DEST (x)), inner);
5774 if (BITS_BIG_ENDIAN)
5776 if (GET_CODE (pos) == CONST_INT)
5777 pos = GEN_INT (GET_MODE_BITSIZE (GET_MODE (inner)) - len
5779 else if (GET_CODE (pos) == MINUS
5780 && GET_CODE (XEXP (pos, 1)) == CONST_INT
5781 && (INTVAL (XEXP (pos, 1))
5782 == GET_MODE_BITSIZE (GET_MODE (inner)) - len))
5783 /* If position is ADJUST - X, new position is X. */
5784 pos = XEXP (pos, 0);
5786 pos = gen_binary (MINUS, GET_MODE (pos),
5787 GEN_INT (GET_MODE_BITSIZE (GET_MODE (inner))
5793 /* A SUBREG between two modes that occupy the same numbers of words
5794 can be done by moving the SUBREG to the source. */
5795 else if (GET_CODE (SET_DEST (x)) == SUBREG
5796 /* We need SUBREGs to compute nonzero_bits properly. */
5797 && nonzero_sign_valid
5798 && (((GET_MODE_SIZE (GET_MODE (SET_DEST (x)))
5799 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
5800 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x))))
5801 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)))
5803 x = gen_rtx_SET (VOIDmode, SUBREG_REG (SET_DEST (x)),
5804 gen_lowpart_for_combine
5805 (GET_MODE (SUBREG_REG (SET_DEST (x))),
5812 while (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
5813 inner = SUBREG_REG (inner);
5815 compute_mode = GET_MODE (inner);
5817 /* Don't attempt bitwise arithmetic on non-integral modes. */
5818 if (! INTEGRAL_MODE_P (compute_mode))
5820 enum machine_mode imode;
5822 /* Something is probably seriously wrong if this matches. */
5823 if (! FLOAT_MODE_P (compute_mode))
5826 /* Try to find an integral mode to pun with. */
5827 imode = mode_for_size (GET_MODE_BITSIZE (compute_mode), MODE_INT, 0);
5828 if (imode == BLKmode)
5831 compute_mode = imode;
5832 inner = gen_lowpart_for_combine (imode, inner);
5835 /* Compute a mask of LEN bits, if we can do this on the host machine. */
5836 if (len < HOST_BITS_PER_WIDE_INT)
5837 mask = GEN_INT (((HOST_WIDE_INT) 1 << len) - 1);
5841 /* Now compute the equivalent expression. Make a copy of INNER
5842 for the SET_DEST in case it is a MEM into which we will substitute;
5843 we don't want shared RTL in that case. */
5845 (VOIDmode, copy_rtx (inner),
5846 gen_binary (IOR, compute_mode,
5847 gen_binary (AND, compute_mode,
5848 simplify_gen_unary (NOT, compute_mode,
5854 gen_binary (ASHIFT, compute_mode,
5855 gen_binary (AND, compute_mode,
5856 gen_lowpart_for_combine
5857 (compute_mode, SET_SRC (x)),
5865 /* Return an RTX for a reference to LEN bits of INNER. If POS_RTX is nonzero,
5866 it is an RTX that represents a variable starting position; otherwise,
5867 POS is the (constant) starting bit position (counted from the LSB).
5869 INNER may be a USE. This will occur when we started with a bitfield
5870 that went outside the boundary of the object in memory, which is
5871 allowed on most machines. To isolate this case, we produce a USE
5872 whose mode is wide enough and surround the MEM with it. The only
5873 code that understands the USE is this routine. If it is not removed,
5874 it will cause the resulting insn not to match.
5876 UNSIGNEDP is non-zero for an unsigned reference and zero for a
5879 IN_DEST is non-zero if this is a reference in the destination of a
5880 SET. This is used when a ZERO_ or SIGN_EXTRACT isn't needed. If non-zero,
5881 a STRICT_LOW_PART will be used, if zero, ZERO_EXTEND or SIGN_EXTEND will
5884 IN_COMPARE is non-zero if we are in a COMPARE. This means that a
5885 ZERO_EXTRACT should be built even for bits starting at bit 0.
5887 MODE is the desired mode of the result (if IN_DEST == 0).
5889 The result is an RTX for the extraction or NULL_RTX if the target
5893 make_extraction (mode, inner, pos, pos_rtx, len,
5894 unsignedp, in_dest, in_compare)
5895 enum machine_mode mode;
5899 unsigned HOST_WIDE_INT len;
5901 int in_dest, in_compare;
5903 /* This mode describes the size of the storage area
5904 to fetch the overall value from. Within that, we
5905 ignore the POS lowest bits, etc. */
5906 enum machine_mode is_mode = GET_MODE (inner);
5907 enum machine_mode inner_mode;
5908 enum machine_mode wanted_inner_mode = byte_mode;
5909 enum machine_mode wanted_inner_reg_mode = word_mode;
5910 enum machine_mode pos_mode = word_mode;
5911 enum machine_mode extraction_mode = word_mode;
5912 enum machine_mode tmode = mode_for_size (len, MODE_INT, 1);
5915 rtx orig_pos_rtx = pos_rtx;
5916 HOST_WIDE_INT orig_pos;
5918 /* Get some information about INNER and get the innermost object. */
5919 if (GET_CODE (inner) == USE)
5920 /* (use:SI (mem:QI foo)) stands for (mem:SI foo). */
5921 /* We don't need to adjust the position because we set up the USE
5922 to pretend that it was a full-word object. */
5923 spans_byte = 1, inner = XEXP (inner, 0);
5924 else if (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
5926 /* If going from (subreg:SI (mem:QI ...)) to (mem:QI ...),
5927 consider just the QI as the memory to extract from.
5928 The subreg adds or removes high bits; its mode is
5929 irrelevant to the meaning of this extraction,
5930 since POS and LEN count from the lsb. */
5931 if (GET_CODE (SUBREG_REG (inner)) == MEM)
5932 is_mode = GET_MODE (SUBREG_REG (inner));
5933 inner = SUBREG_REG (inner);
5936 inner_mode = GET_MODE (inner);
5938 if (pos_rtx && GET_CODE (pos_rtx) == CONST_INT)
5939 pos = INTVAL (pos_rtx), pos_rtx = 0;
5941 /* See if this can be done without an extraction. We never can if the
5942 width of the field is not the same as that of some integer mode. For
5943 registers, we can only avoid the extraction if the position is at the
5944 low-order bit and this is either not in the destination or we have the
5945 appropriate STRICT_LOW_PART operation available.
5947 For MEM, we can avoid an extract if the field starts on an appropriate
5948 boundary and we can change the mode of the memory reference. However,
5949 we cannot directly access the MEM if we have a USE and the underlying
5950 MEM is not TMODE. This combination means that MEM was being used in a
5951 context where bits outside its mode were being referenced; that is only
5952 valid in bit-field insns. */
5954 if (tmode != BLKmode
5955 && ! (spans_byte && inner_mode != tmode)
5956 && ((pos_rtx == 0 && (pos % BITS_PER_WORD) == 0
5957 && GET_CODE (inner) != MEM
5959 || (GET_CODE (inner) == REG
5960 && have_insn_for (STRICT_LOW_PART, tmode))))
5961 || (GET_CODE (inner) == MEM && pos_rtx == 0
5963 % (STRICT_ALIGNMENT ? GET_MODE_ALIGNMENT (tmode)
5964 : BITS_PER_UNIT)) == 0
5965 /* We can't do this if we are widening INNER_MODE (it
5966 may not be aligned, for one thing). */
5967 && GET_MODE_BITSIZE (inner_mode) >= GET_MODE_BITSIZE (tmode)
5968 && (inner_mode == tmode
5969 || (! mode_dependent_address_p (XEXP (inner, 0))
5970 && ! MEM_VOLATILE_P (inner))))))
5972 /* If INNER is a MEM, make a new MEM that encompasses just the desired
5973 field. If the original and current mode are the same, we need not
5974 adjust the offset. Otherwise, we do if bytes big endian.
5976 If INNER is not a MEM, get a piece consisting of just the field
5977 of interest (in this case POS % BITS_PER_WORD must be 0). */
5979 if (GET_CODE (inner) == MEM)
5981 HOST_WIDE_INT offset;
5983 /* POS counts from lsb, but make OFFSET count in memory order. */
5984 if (BYTES_BIG_ENDIAN)
5985 offset = (GET_MODE_BITSIZE (is_mode) - len - pos) / BITS_PER_UNIT;
5987 offset = pos / BITS_PER_UNIT;
5989 new = adjust_address_nv (inner, tmode, offset);
5991 else if (GET_CODE (inner) == REG)
5993 /* We can't call gen_lowpart_for_combine here since we always want
5994 a SUBREG and it would sometimes return a new hard register. */
5995 if (tmode != inner_mode)
5997 HOST_WIDE_INT final_word = pos / BITS_PER_WORD;
5999 if (WORDS_BIG_ENDIAN
6000 && GET_MODE_SIZE (inner_mode) > UNITS_PER_WORD)
6001 final_word = ((GET_MODE_SIZE (inner_mode)
6002 - GET_MODE_SIZE (tmode))
6003 / UNITS_PER_WORD) - final_word;
6005 final_word *= UNITS_PER_WORD;
6006 if (BYTES_BIG_ENDIAN &&
6007 GET_MODE_SIZE (inner_mode) > GET_MODE_SIZE (tmode))
6008 final_word += (GET_MODE_SIZE (inner_mode)
6009 - GET_MODE_SIZE (tmode)) % UNITS_PER_WORD;
6011 new = gen_rtx_SUBREG (tmode, inner, final_word);
6017 new = force_to_mode (inner, tmode,
6018 len >= HOST_BITS_PER_WIDE_INT
6019 ? ~(unsigned HOST_WIDE_INT) 0
6020 : ((unsigned HOST_WIDE_INT) 1 << len) - 1,
6023 /* If this extraction is going into the destination of a SET,
6024 make a STRICT_LOW_PART unless we made a MEM. */
6027 return (GET_CODE (new) == MEM ? new
6028 : (GET_CODE (new) != SUBREG
6029 ? gen_rtx_CLOBBER (tmode, const0_rtx)
6030 : gen_rtx_STRICT_LOW_PART (VOIDmode, new)));
6035 if (GET_CODE (new) == CONST_INT)
6036 return gen_int_mode (INTVAL (new), mode);
6038 /* If we know that no extraneous bits are set, and that the high
6039 bit is not set, convert the extraction to the cheaper of
6040 sign and zero extension, that are equivalent in these cases. */
6041 if (flag_expensive_optimizations
6042 && (GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT
6043 && ((nonzero_bits (new, tmode)
6044 & ~(((unsigned HOST_WIDE_INT)
6045 GET_MODE_MASK (tmode))
6049 rtx temp = gen_rtx_ZERO_EXTEND (mode, new);
6050 rtx temp1 = gen_rtx_SIGN_EXTEND (mode, new);
6052 /* Prefer ZERO_EXTENSION, since it gives more information to
6054 if (rtx_cost (temp, SET) <= rtx_cost (temp1, SET))
6059 /* Otherwise, sign- or zero-extend unless we already are in the
6062 return (gen_rtx_fmt_e (unsignedp ? ZERO_EXTEND : SIGN_EXTEND,
6066 /* Unless this is a COMPARE or we have a funny memory reference,
6067 don't do anything with zero-extending field extracts starting at
6068 the low-order bit since they are simple AND operations. */
6069 if (pos_rtx == 0 && pos == 0 && ! in_dest
6070 && ! in_compare && ! spans_byte && unsignedp)
6073 /* Unless we are allowed to span bytes or INNER is not MEM, reject this if
6074 we would be spanning bytes or if the position is not a constant and the
6075 length is not 1. In all other cases, we would only be going outside
6076 our object in cases when an original shift would have been
6078 if (! spans_byte && GET_CODE (inner) == MEM
6079 && ((pos_rtx == 0 && pos + len > GET_MODE_BITSIZE (is_mode))
6080 || (pos_rtx != 0 && len != 1)))
6083 /* Get the mode to use should INNER not be a MEM, the mode for the position,
6084 and the mode for the result. */
6085 if (in_dest && mode_for_extraction (EP_insv, -1) != MAX_MACHINE_MODE)
6087 wanted_inner_reg_mode = mode_for_extraction (EP_insv, 0);
6088 pos_mode = mode_for_extraction (EP_insv, 2);
6089 extraction_mode = mode_for_extraction (EP_insv, 3);
6092 if (! in_dest && unsignedp
6093 && mode_for_extraction (EP_extzv, -1) != MAX_MACHINE_MODE)
6095 wanted_inner_reg_mode = mode_for_extraction (EP_extzv, 1);
6096 pos_mode = mode_for_extraction (EP_extzv, 3);
6097 extraction_mode = mode_for_extraction (EP_extzv, 0);
6100 if (! in_dest && ! unsignedp
6101 && mode_for_extraction (EP_extv, -1) != MAX_MACHINE_MODE)
6103 wanted_inner_reg_mode = mode_for_extraction (EP_extv, 1);
6104 pos_mode = mode_for_extraction (EP_extv, 3);
6105 extraction_mode = mode_for_extraction (EP_extv, 0);
6108 /* Never narrow an object, since that might not be safe. */
6110 if (mode != VOIDmode
6111 && GET_MODE_SIZE (extraction_mode) < GET_MODE_SIZE (mode))
6112 extraction_mode = mode;
6114 if (pos_rtx && GET_MODE (pos_rtx) != VOIDmode
6115 && GET_MODE_SIZE (pos_mode) < GET_MODE_SIZE (GET_MODE (pos_rtx)))
6116 pos_mode = GET_MODE (pos_rtx);
6118 /* If this is not from memory, the desired mode is wanted_inner_reg_mode;
6119 if we have to change the mode of memory and cannot, the desired mode is
6121 if (GET_CODE (inner) != MEM)
6122 wanted_inner_mode = wanted_inner_reg_mode;
6123 else if (inner_mode != wanted_inner_mode
6124 && (mode_dependent_address_p (XEXP (inner, 0))
6125 || MEM_VOLATILE_P (inner)))
6126 wanted_inner_mode = extraction_mode;
6130 if (BITS_BIG_ENDIAN)
6132 /* POS is passed as if BITS_BIG_ENDIAN == 0, so we need to convert it to
6133 BITS_BIG_ENDIAN style. If position is constant, compute new
6134 position. Otherwise, build subtraction.
6135 Note that POS is relative to the mode of the original argument.
6136 If it's a MEM we need to recompute POS relative to that.
6137 However, if we're extracting from (or inserting into) a register,
6138 we want to recompute POS relative to wanted_inner_mode. */
6139 int width = (GET_CODE (inner) == MEM
6140 ? GET_MODE_BITSIZE (is_mode)
6141 : GET_MODE_BITSIZE (wanted_inner_mode));
6144 pos = width - len - pos;
6147 = gen_rtx_MINUS (GET_MODE (pos_rtx), GEN_INT (width - len), pos_rtx);
6148 /* POS may be less than 0 now, but we check for that below.
6149 Note that it can only be less than 0 if GET_CODE (inner) != MEM. */
6152 /* If INNER has a wider mode, make it smaller. If this is a constant
6153 extract, try to adjust the byte to point to the byte containing
6155 if (wanted_inner_mode != VOIDmode
6156 && GET_MODE_SIZE (wanted_inner_mode) < GET_MODE_SIZE (is_mode)
6157 && ((GET_CODE (inner) == MEM
6158 && (inner_mode == wanted_inner_mode
6159 || (! mode_dependent_address_p (XEXP (inner, 0))
6160 && ! MEM_VOLATILE_P (inner))))))
6164 /* The computations below will be correct if the machine is big
6165 endian in both bits and bytes or little endian in bits and bytes.
6166 If it is mixed, we must adjust. */
6168 /* If bytes are big endian and we had a paradoxical SUBREG, we must
6169 adjust OFFSET to compensate. */
6170 if (BYTES_BIG_ENDIAN
6172 && GET_MODE_SIZE (inner_mode) < GET_MODE_SIZE (is_mode))
6173 offset -= GET_MODE_SIZE (is_mode) - GET_MODE_SIZE (inner_mode);
6175 /* If this is a constant position, we can move to the desired byte. */
6178 offset += pos / BITS_PER_UNIT;
6179 pos %= GET_MODE_BITSIZE (wanted_inner_mode);
6182 if (BYTES_BIG_ENDIAN != BITS_BIG_ENDIAN
6184 && is_mode != wanted_inner_mode)
6185 offset = (GET_MODE_SIZE (is_mode)
6186 - GET_MODE_SIZE (wanted_inner_mode) - offset);
6188 if (offset != 0 || inner_mode != wanted_inner_mode)
6189 inner = adjust_address_nv (inner, wanted_inner_mode, offset);
6192 /* If INNER is not memory, we can always get it into the proper mode. If we
6193 are changing its mode, POS must be a constant and smaller than the size
6195 else if (GET_CODE (inner) != MEM)
6197 if (GET_MODE (inner) != wanted_inner_mode
6199 || orig_pos + len > GET_MODE_BITSIZE (wanted_inner_mode)))
6202 inner = force_to_mode (inner, wanted_inner_mode,
6204 || len + orig_pos >= HOST_BITS_PER_WIDE_INT
6205 ? ~(unsigned HOST_WIDE_INT) 0
6206 : ((((unsigned HOST_WIDE_INT) 1 << len) - 1)
6211 /* Adjust mode of POS_RTX, if needed. If we want a wider mode, we
6212 have to zero extend. Otherwise, we can just use a SUBREG. */
6214 && GET_MODE_SIZE (pos_mode) > GET_MODE_SIZE (GET_MODE (pos_rtx)))
6216 rtx temp = gen_rtx_ZERO_EXTEND (pos_mode, pos_rtx);
6218 /* If we know that no extraneous bits are set, and that the high
6219 bit is not set, convert extraction to cheaper one - either
6220 SIGN_EXTENSION or ZERO_EXTENSION, that are equivalent in these
6222 if (flag_expensive_optimizations
6223 && (GET_MODE_BITSIZE (GET_MODE (pos_rtx)) <= HOST_BITS_PER_WIDE_INT
6224 && ((nonzero_bits (pos_rtx, GET_MODE (pos_rtx))
6225 & ~(((unsigned HOST_WIDE_INT)
6226 GET_MODE_MASK (GET_MODE (pos_rtx)))
6230 rtx temp1 = gen_rtx_SIGN_EXTEND (pos_mode, pos_rtx);
6232 /* Prefer ZERO_EXTENSION, since it gives more information to
6234 if (rtx_cost (temp1, SET) < rtx_cost (temp, SET))
6239 else if (pos_rtx != 0
6240 && GET_MODE_SIZE (pos_mode) < GET_MODE_SIZE (GET_MODE (pos_rtx)))
6241 pos_rtx = gen_lowpart_for_combine (pos_mode, pos_rtx);
6243 /* Make POS_RTX unless we already have it and it is correct. If we don't
6244 have a POS_RTX but we do have an ORIG_POS_RTX, the latter must
6246 if (pos_rtx == 0 && orig_pos_rtx != 0 && INTVAL (orig_pos_rtx) == pos)
6247 pos_rtx = orig_pos_rtx;
6249 else if (pos_rtx == 0)
6250 pos_rtx = GEN_INT (pos);
6252 /* Make the required operation. See if we can use existing rtx. */
6253 new = gen_rtx_fmt_eee (unsignedp ? ZERO_EXTRACT : SIGN_EXTRACT,
6254 extraction_mode, inner, GEN_INT (len), pos_rtx);
6256 new = gen_lowpart_for_combine (mode, new);
6261 /* See if X contains an ASHIFT of COUNT or more bits that can be commuted
6262 with any other operations in X. Return X without that shift if so. */
6265 extract_left_shift (x, count)
6269 enum rtx_code code = GET_CODE (x);
6270 enum machine_mode mode = GET_MODE (x);
6276 /* This is the shift itself. If it is wide enough, we will return
6277 either the value being shifted if the shift count is equal to
6278 COUNT or a shift for the difference. */
6279 if (GET_CODE (XEXP (x, 1)) == CONST_INT
6280 && INTVAL (XEXP (x, 1)) >= count)
6281 return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (x, 0),
6282 INTVAL (XEXP (x, 1)) - count);
6286 if ((tem = extract_left_shift (XEXP (x, 0), count)) != 0)
6287 return simplify_gen_unary (code, mode, tem, mode);
6291 case PLUS: case IOR: case XOR: case AND:
6292 /* If we can safely shift this constant and we find the inner shift,
6293 make a new operation. */
6294 if (GET_CODE (XEXP (x,1)) == CONST_INT
6295 && (INTVAL (XEXP (x, 1)) & ((((HOST_WIDE_INT) 1 << count)) - 1)) == 0
6296 && (tem = extract_left_shift (XEXP (x, 0), count)) != 0)
6297 return gen_binary (code, mode, tem,
6298 GEN_INT (INTVAL (XEXP (x, 1)) >> count));
6309 /* Look at the expression rooted at X. Look for expressions
6310 equivalent to ZERO_EXTRACT, SIGN_EXTRACT, ZERO_EXTEND, SIGN_EXTEND.
6311 Form these expressions.
6313 Return the new rtx, usually just X.
6315 Also, for machines like the VAX that don't have logical shift insns,
6316 try to convert logical to arithmetic shift operations in cases where
6317 they are equivalent. This undoes the canonicalizations to logical
6318 shifts done elsewhere.
6320 We try, as much as possible, to re-use rtl expressions to save memory.
6322 IN_CODE says what kind of expression we are processing. Normally, it is
6323 SET. In a memory address (inside a MEM, PLUS or minus, the latter two
6324 being kludges), it is MEM. When processing the arguments of a comparison
6325 or a COMPARE against zero, it is COMPARE. */
6328 make_compound_operation (x, in_code)
6330 enum rtx_code in_code;
6332 enum rtx_code code = GET_CODE (x);
6333 enum machine_mode mode = GET_MODE (x);
6334 int mode_width = GET_MODE_BITSIZE (mode);
6336 enum rtx_code next_code;
6342 /* Select the code to be used in recursive calls. Once we are inside an
6343 address, we stay there. If we have a comparison, set to COMPARE,
6344 but once inside, go back to our default of SET. */
6346 next_code = (code == MEM || code == PLUS || code == MINUS ? MEM
6347 : ((code == COMPARE || GET_RTX_CLASS (code) == '<')
6348 && XEXP (x, 1) == const0_rtx) ? COMPARE
6349 : in_code == COMPARE ? SET : in_code);
6351 /* Process depending on the code of this operation. If NEW is set
6352 non-zero, it will be returned. */
6357 /* Convert shifts by constants into multiplications if inside
6359 if (in_code == MEM && GET_CODE (XEXP (x, 1)) == CONST_INT
6360 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT
6361 && INTVAL (XEXP (x, 1)) >= 0)
6363 new = make_compound_operation (XEXP (x, 0), next_code);
6364 new = gen_rtx_MULT (mode, new,
6365 GEN_INT ((HOST_WIDE_INT) 1
6366 << INTVAL (XEXP (x, 1))));
6371 /* If the second operand is not a constant, we can't do anything
6373 if (GET_CODE (XEXP (x, 1)) != CONST_INT)
6376 /* If the constant is a power of two minus one and the first operand
6377 is a logical right shift, make an extraction. */
6378 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
6379 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6381 new = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code);
6382 new = make_extraction (mode, new, 0, XEXP (XEXP (x, 0), 1), i, 1,
6383 0, in_code == COMPARE);
6386 /* Same as previous, but for (subreg (lshiftrt ...)) in first op. */
6387 else if (GET_CODE (XEXP (x, 0)) == SUBREG
6388 && subreg_lowpart_p (XEXP (x, 0))
6389 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == LSHIFTRT
6390 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6392 new = make_compound_operation (XEXP (SUBREG_REG (XEXP (x, 0)), 0),
6394 new = make_extraction (GET_MODE (SUBREG_REG (XEXP (x, 0))), new, 0,
6395 XEXP (SUBREG_REG (XEXP (x, 0)), 1), i, 1,
6396 0, in_code == COMPARE);
6398 /* Same as previous, but for (xor/ior (lshiftrt...) (lshiftrt...)). */
6399 else if ((GET_CODE (XEXP (x, 0)) == XOR
6400 || GET_CODE (XEXP (x, 0)) == IOR)
6401 && GET_CODE (XEXP (XEXP (x, 0), 0)) == LSHIFTRT
6402 && GET_CODE (XEXP (XEXP (x, 0), 1)) == LSHIFTRT
6403 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6405 /* Apply the distributive law, and then try to make extractions. */
6406 new = gen_rtx_fmt_ee (GET_CODE (XEXP (x, 0)), mode,
6407 gen_rtx_AND (mode, XEXP (XEXP (x, 0), 0),
6409 gen_rtx_AND (mode, XEXP (XEXP (x, 0), 1),
6411 new = make_compound_operation (new, in_code);
6414 /* If we are have (and (rotate X C) M) and C is larger than the number
6415 of bits in M, this is an extraction. */
6417 else if (GET_CODE (XEXP (x, 0)) == ROTATE
6418 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
6419 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0
6420 && i <= INTVAL (XEXP (XEXP (x, 0), 1)))
6422 new = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code);
6423 new = make_extraction (mode, new,
6424 (GET_MODE_BITSIZE (mode)
6425 - INTVAL (XEXP (XEXP (x, 0), 1))),
6426 NULL_RTX, i, 1, 0, in_code == COMPARE);
6429 /* On machines without logical shifts, if the operand of the AND is
6430 a logical shift and our mask turns off all the propagated sign
6431 bits, we can replace the logical shift with an arithmetic shift. */
6432 else if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
6433 && !have_insn_for (LSHIFTRT, mode)
6434 && have_insn_for (ASHIFTRT, mode)
6435 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
6436 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
6437 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT
6438 && mode_width <= HOST_BITS_PER_WIDE_INT)
6440 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
6442 mask >>= INTVAL (XEXP (XEXP (x, 0), 1));
6443 if ((INTVAL (XEXP (x, 1)) & ~mask) == 0)
6445 gen_rtx_ASHIFTRT (mode,
6446 make_compound_operation
6447 (XEXP (XEXP (x, 0), 0), next_code),
6448 XEXP (XEXP (x, 0), 1)));
6451 /* If the constant is one less than a power of two, this might be
6452 representable by an extraction even if no shift is present.
6453 If it doesn't end up being a ZERO_EXTEND, we will ignore it unless
6454 we are in a COMPARE. */
6455 else if ((i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6456 new = make_extraction (mode,
6457 make_compound_operation (XEXP (x, 0),
6459 0, NULL_RTX, i, 1, 0, in_code == COMPARE);
6461 /* If we are in a comparison and this is an AND with a power of two,
6462 convert this into the appropriate bit extract. */
6463 else if (in_code == COMPARE
6464 && (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0)
6465 new = make_extraction (mode,
6466 make_compound_operation (XEXP (x, 0),
6468 i, NULL_RTX, 1, 1, 0, 1);
6473 /* If the sign bit is known to be zero, replace this with an
6474 arithmetic shift. */
6475 if (have_insn_for (ASHIFTRT, mode)
6476 && ! have_insn_for (LSHIFTRT, mode)
6477 && mode_width <= HOST_BITS_PER_WIDE_INT
6478 && (nonzero_bits (XEXP (x, 0), mode) & (1 << (mode_width - 1))) == 0)
6480 new = gen_rtx_ASHIFTRT (mode,
6481 make_compound_operation (XEXP (x, 0),
6487 /* ... fall through ... */
6493 /* If we have (ashiftrt (ashift foo C1) C2) with C2 >= C1,
6494 this is a SIGN_EXTRACT. */
6495 if (GET_CODE (rhs) == CONST_INT
6496 && GET_CODE (lhs) == ASHIFT
6497 && GET_CODE (XEXP (lhs, 1)) == CONST_INT
6498 && INTVAL (rhs) >= INTVAL (XEXP (lhs, 1)))
6500 new = make_compound_operation (XEXP (lhs, 0), next_code);
6501 new = make_extraction (mode, new,
6502 INTVAL (rhs) - INTVAL (XEXP (lhs, 1)),
6503 NULL_RTX, mode_width - INTVAL (rhs),
6504 code == LSHIFTRT, 0, in_code == COMPARE);
6508 /* See if we have operations between an ASHIFTRT and an ASHIFT.
6509 If so, try to merge the shifts into a SIGN_EXTEND. We could
6510 also do this for some cases of SIGN_EXTRACT, but it doesn't
6511 seem worth the effort; the case checked for occurs on Alpha. */
6513 if (GET_RTX_CLASS (GET_CODE (lhs)) != 'o'
6514 && ! (GET_CODE (lhs) == SUBREG
6515 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (lhs))) == 'o'))
6516 && GET_CODE (rhs) == CONST_INT
6517 && INTVAL (rhs) < HOST_BITS_PER_WIDE_INT
6518 && (new = extract_left_shift (lhs, INTVAL (rhs))) != 0)
6519 new = make_extraction (mode, make_compound_operation (new, next_code),
6520 0, NULL_RTX, mode_width - INTVAL (rhs),
6521 code == LSHIFTRT, 0, in_code == COMPARE);
6526 /* Call ourselves recursively on the inner expression. If we are
6527 narrowing the object and it has a different RTL code from
6528 what it originally did, do this SUBREG as a force_to_mode. */
6530 tem = make_compound_operation (SUBREG_REG (x), in_code);
6531 if (GET_CODE (tem) != GET_CODE (SUBREG_REG (x))
6532 && GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (tem))
6533 && subreg_lowpart_p (x))
6535 rtx newer = force_to_mode (tem, mode, ~(HOST_WIDE_INT) 0,
6538 /* If we have something other than a SUBREG, we might have
6539 done an expansion, so rerun ourselves. */
6540 if (GET_CODE (newer) != SUBREG)
6541 newer = make_compound_operation (newer, in_code);
6546 /* If this is a paradoxical subreg, and the new code is a sign or
6547 zero extension, omit the subreg and widen the extension. If it
6548 is a regular subreg, we can still get rid of the subreg by not
6549 widening so much, or in fact removing the extension entirely. */
6550 if ((GET_CODE (tem) == SIGN_EXTEND
6551 || GET_CODE (tem) == ZERO_EXTEND)
6552 && subreg_lowpart_p (x))
6554 if (GET_MODE_SIZE (mode) > GET_MODE_SIZE (GET_MODE (tem))
6555 || (GET_MODE_SIZE (mode) >
6556 GET_MODE_SIZE (GET_MODE (XEXP (tem, 0)))))
6557 tem = gen_rtx_fmt_e (GET_CODE (tem), mode, XEXP (tem, 0));
6559 tem = gen_lowpart_for_combine (mode, XEXP (tem, 0));
6570 x = gen_lowpart_for_combine (mode, new);
6571 code = GET_CODE (x);
6574 /* Now recursively process each operand of this operation. */
6575 fmt = GET_RTX_FORMAT (code);
6576 for (i = 0; i < GET_RTX_LENGTH (code); i++)
6579 new = make_compound_operation (XEXP (x, i), next_code);
6580 SUBST (XEXP (x, i), new);
6586 /* Given M see if it is a value that would select a field of bits
6587 within an item, but not the entire word. Return -1 if not.
6588 Otherwise, return the starting position of the field, where 0 is the
6591 *PLEN is set to the length of the field. */
6594 get_pos_from_mask (m, plen)
6595 unsigned HOST_WIDE_INT m;
6596 unsigned HOST_WIDE_INT *plen;
6598 /* Get the bit number of the first 1 bit from the right, -1 if none. */
6599 int pos = exact_log2 (m & -m);
6605 /* Now shift off the low-order zero bits and see if we have a power of
6607 len = exact_log2 ((m >> pos) + 1);
6616 /* See if X can be simplified knowing that we will only refer to it in
6617 MODE and will only refer to those bits that are nonzero in MASK.
6618 If other bits are being computed or if masking operations are done
6619 that select a superset of the bits in MASK, they can sometimes be
6622 Return a possibly simplified expression, but always convert X to
6623 MODE. If X is a CONST_INT, AND the CONST_INT with MASK.
6625 Also, if REG is non-zero and X is a register equal in value to REG,
6628 If JUST_SELECT is nonzero, don't optimize by noticing that bits in MASK
6629 are all off in X. This is used when X will be complemented, by either
6630 NOT, NEG, or XOR. */
6633 force_to_mode (x, mode, mask, reg, just_select)
6635 enum machine_mode mode;
6636 unsigned HOST_WIDE_INT mask;
6640 enum rtx_code code = GET_CODE (x);
6641 int next_select = just_select || code == XOR || code == NOT || code == NEG;
6642 enum machine_mode op_mode;
6643 unsigned HOST_WIDE_INT fuller_mask, nonzero;
6646 /* If this is a CALL or ASM_OPERANDS, don't do anything. Some of the
6647 code below will do the wrong thing since the mode of such an
6648 expression is VOIDmode.
6650 Also do nothing if X is a CLOBBER; this can happen if X was
6651 the return value from a call to gen_lowpart_for_combine. */
6652 if (code == CALL || code == ASM_OPERANDS || code == CLOBBER)
6655 /* We want to perform the operation is its present mode unless we know
6656 that the operation is valid in MODE, in which case we do the operation
6658 op_mode = ((GET_MODE_CLASS (mode) == GET_MODE_CLASS (GET_MODE (x))
6659 && have_insn_for (code, mode))
6660 ? mode : GET_MODE (x));
6662 /* It is not valid to do a right-shift in a narrower mode
6663 than the one it came in with. */
6664 if ((code == LSHIFTRT || code == ASHIFTRT)
6665 && GET_MODE_BITSIZE (mode) < GET_MODE_BITSIZE (GET_MODE (x)))
6666 op_mode = GET_MODE (x);
6668 /* Truncate MASK to fit OP_MODE. */
6670 mask &= GET_MODE_MASK (op_mode);
6672 /* When we have an arithmetic operation, or a shift whose count we
6673 do not know, we need to assume that all bit the up to the highest-order
6674 bit in MASK will be needed. This is how we form such a mask. */
6676 fuller_mask = (GET_MODE_BITSIZE (op_mode) >= HOST_BITS_PER_WIDE_INT
6677 ? GET_MODE_MASK (op_mode)
6678 : (((unsigned HOST_WIDE_INT) 1 << (floor_log2 (mask) + 1))
6681 fuller_mask = ~(HOST_WIDE_INT) 0;
6683 /* Determine what bits of X are guaranteed to be (non)zero. */
6684 nonzero = nonzero_bits (x, mode);
6686 /* If none of the bits in X are needed, return a zero. */
6687 if (! just_select && (nonzero & mask) == 0)
6690 /* If X is a CONST_INT, return a new one. Do this here since the
6691 test below will fail. */
6692 if (GET_CODE (x) == CONST_INT)
6694 HOST_WIDE_INT cval = INTVAL (x) & mask;
6695 int width = GET_MODE_BITSIZE (mode);
6697 /* If MODE is narrower that HOST_WIDE_INT and CVAL is a negative
6698 number, sign extend it. */
6699 if (width > 0 && width < HOST_BITS_PER_WIDE_INT
6700 && (cval & ((HOST_WIDE_INT) 1 << (width - 1))) != 0)
6701 cval |= (HOST_WIDE_INT) -1 << width;
6703 return GEN_INT (cval);
6706 /* If X is narrower than MODE and we want all the bits in X's mode, just
6707 get X in the proper mode. */
6708 if (GET_MODE_SIZE (GET_MODE (x)) < GET_MODE_SIZE (mode)
6709 && (GET_MODE_MASK (GET_MODE (x)) & ~mask) == 0)
6710 return gen_lowpart_for_combine (mode, x);
6712 /* If we aren't changing the mode, X is not a SUBREG, and all zero bits in
6713 MASK are already known to be zero in X, we need not do anything. */
6714 if (GET_MODE (x) == mode && code != SUBREG && (~mask & nonzero) == 0)
6720 /* If X is a (clobber (const_int)), return it since we know we are
6721 generating something that won't match. */
6725 /* X is a (use (mem ..)) that was made from a bit-field extraction that
6726 spanned the boundary of the MEM. If we are now masking so it is
6727 within that boundary, we don't need the USE any more. */
6728 if (! BITS_BIG_ENDIAN
6729 && (mask & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
6730 return force_to_mode (XEXP (x, 0), mode, mask, reg, next_select);
6737 x = expand_compound_operation (x);
6738 if (GET_CODE (x) != code)
6739 return force_to_mode (x, mode, mask, reg, next_select);
6743 if (reg != 0 && (rtx_equal_p (get_last_value (reg), x)
6744 || rtx_equal_p (reg, get_last_value (x))))
6749 if (subreg_lowpart_p (x)
6750 /* We can ignore the effect of this SUBREG if it narrows the mode or
6751 if the constant masks to zero all the bits the mode doesn't
6753 && ((GET_MODE_SIZE (GET_MODE (x))
6754 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
6756 & GET_MODE_MASK (GET_MODE (x))
6757 & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (x)))))))
6758 return force_to_mode (SUBREG_REG (x), mode, mask, reg, next_select);
6762 /* If this is an AND with a constant, convert it into an AND
6763 whose constant is the AND of that constant with MASK. If it
6764 remains an AND of MASK, delete it since it is redundant. */
6766 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
6768 x = simplify_and_const_int (x, op_mode, XEXP (x, 0),
6769 mask & INTVAL (XEXP (x, 1)));
6771 /* If X is still an AND, see if it is an AND with a mask that
6772 is just some low-order bits. If so, and it is MASK, we don't
6775 if (GET_CODE (x) == AND && GET_CODE (XEXP (x, 1)) == CONST_INT
6776 && ((INTVAL (XEXP (x, 1)) & GET_MODE_MASK (GET_MODE (x)))
6777 == (HOST_WIDE_INT) mask))
6780 /* If it remains an AND, try making another AND with the bits
6781 in the mode mask that aren't in MASK turned on. If the
6782 constant in the AND is wide enough, this might make a
6783 cheaper constant. */
6785 if (GET_CODE (x) == AND && GET_CODE (XEXP (x, 1)) == CONST_INT
6786 && GET_MODE_MASK (GET_MODE (x)) != mask
6787 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT)
6789 HOST_WIDE_INT cval = (INTVAL (XEXP (x, 1))
6790 | (GET_MODE_MASK (GET_MODE (x)) & ~mask));
6791 int width = GET_MODE_BITSIZE (GET_MODE (x));
6794 /* If MODE is narrower that HOST_WIDE_INT and CVAL is a negative
6795 number, sign extend it. */
6796 if (width > 0 && width < HOST_BITS_PER_WIDE_INT
6797 && (cval & ((HOST_WIDE_INT) 1 << (width - 1))) != 0)
6798 cval |= (HOST_WIDE_INT) -1 << width;
6800 y = gen_binary (AND, GET_MODE (x), XEXP (x, 0), GEN_INT (cval));
6801 if (rtx_cost (y, SET) < rtx_cost (x, SET))
6811 /* In (and (plus FOO C1) M), if M is a mask that just turns off
6812 low-order bits (as in an alignment operation) and FOO is already
6813 aligned to that boundary, mask C1 to that boundary as well.
6814 This may eliminate that PLUS and, later, the AND. */
6817 unsigned int width = GET_MODE_BITSIZE (mode);
6818 unsigned HOST_WIDE_INT smask = mask;
6820 /* If MODE is narrower than HOST_WIDE_INT and mask is a negative
6821 number, sign extend it. */
6823 if (width < HOST_BITS_PER_WIDE_INT
6824 && (smask & ((HOST_WIDE_INT) 1 << (width - 1))) != 0)
6825 smask |= (HOST_WIDE_INT) -1 << width;
6827 if (GET_CODE (XEXP (x, 1)) == CONST_INT
6828 && exact_log2 (- smask) >= 0
6829 && (nonzero_bits (XEXP (x, 0), mode) & ~smask) == 0
6830 && (INTVAL (XEXP (x, 1)) & ~smask) != 0)
6831 return force_to_mode (plus_constant (XEXP (x, 0),
6832 (INTVAL (XEXP (x, 1)) & smask)),
6833 mode, smask, reg, next_select);
6836 /* ... fall through ... */
6839 /* For PLUS, MINUS and MULT, we need any bits less significant than the
6840 most significant bit in MASK since carries from those bits will
6841 affect the bits we are interested in. */
6846 /* If X is (minus C Y) where C's least set bit is larger than any bit
6847 in the mask, then we may replace with (neg Y). */
6848 if (GET_CODE (XEXP (x, 0)) == CONST_INT
6849 && (((unsigned HOST_WIDE_INT) (INTVAL (XEXP (x, 0))
6850 & -INTVAL (XEXP (x, 0))))
6853 x = simplify_gen_unary (NEG, GET_MODE (x), XEXP (x, 1),
6855 return force_to_mode (x, mode, mask, reg, next_select);
6858 /* Similarly, if C contains every bit in the mask, then we may
6859 replace with (not Y). */
6860 if (GET_CODE (XEXP (x, 0)) == CONST_INT
6861 && ((INTVAL (XEXP (x, 0)) | (HOST_WIDE_INT) mask)
6862 == INTVAL (XEXP (x, 0))))
6864 x = simplify_gen_unary (NOT, GET_MODE (x),
6865 XEXP (x, 1), GET_MODE (x));
6866 return force_to_mode (x, mode, mask, reg, next_select);
6874 /* If X is (ior (lshiftrt FOO C1) C2), try to commute the IOR and
6875 LSHIFTRT so we end up with an (and (lshiftrt (ior ...) ...) ...)
6876 operation which may be a bitfield extraction. Ensure that the
6877 constant we form is not wider than the mode of X. */
6879 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
6880 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
6881 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
6882 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT
6883 && GET_CODE (XEXP (x, 1)) == CONST_INT
6884 && ((INTVAL (XEXP (XEXP (x, 0), 1))
6885 + floor_log2 (INTVAL (XEXP (x, 1))))
6886 < GET_MODE_BITSIZE (GET_MODE (x)))
6887 && (INTVAL (XEXP (x, 1))
6888 & ~nonzero_bits (XEXP (x, 0), GET_MODE (x))) == 0)
6890 temp = GEN_INT ((INTVAL (XEXP (x, 1)) & mask)
6891 << INTVAL (XEXP (XEXP (x, 0), 1)));
6892 temp = gen_binary (GET_CODE (x), GET_MODE (x),
6893 XEXP (XEXP (x, 0), 0), temp);
6894 x = gen_binary (LSHIFTRT, GET_MODE (x), temp,
6895 XEXP (XEXP (x, 0), 1));
6896 return force_to_mode (x, mode, mask, reg, next_select);
6900 /* For most binary operations, just propagate into the operation and
6901 change the mode if we have an operation of that mode. */
6903 op0 = gen_lowpart_for_combine (op_mode,
6904 force_to_mode (XEXP (x, 0), mode, mask,
6906 op1 = gen_lowpart_for_combine (op_mode,
6907 force_to_mode (XEXP (x, 1), mode, mask,
6910 /* If OP1 is a CONST_INT and X is an IOR or XOR, clear bits outside
6911 MASK since OP1 might have been sign-extended but we never want
6912 to turn on extra bits, since combine might have previously relied
6913 on them being off. */
6914 if (GET_CODE (op1) == CONST_INT && (code == IOR || code == XOR)
6915 && (INTVAL (op1) & mask) != 0)
6916 op1 = GEN_INT (INTVAL (op1) & mask);
6918 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
6919 x = gen_binary (code, op_mode, op0, op1);
6923 /* For left shifts, do the same, but just for the first operand.
6924 However, we cannot do anything with shifts where we cannot
6925 guarantee that the counts are smaller than the size of the mode
6926 because such a count will have a different meaning in a
6929 if (! (GET_CODE (XEXP (x, 1)) == CONST_INT
6930 && INTVAL (XEXP (x, 1)) >= 0
6931 && INTVAL (XEXP (x, 1)) < GET_MODE_BITSIZE (mode))
6932 && ! (GET_MODE (XEXP (x, 1)) != VOIDmode
6933 && (nonzero_bits (XEXP (x, 1), GET_MODE (XEXP (x, 1)))
6934 < (unsigned HOST_WIDE_INT) GET_MODE_BITSIZE (mode))))
6937 /* If the shift count is a constant and we can do arithmetic in
6938 the mode of the shift, refine which bits we need. Otherwise, use the
6939 conservative form of the mask. */
6940 if (GET_CODE (XEXP (x, 1)) == CONST_INT
6941 && INTVAL (XEXP (x, 1)) >= 0
6942 && INTVAL (XEXP (x, 1)) < GET_MODE_BITSIZE (op_mode)
6943 && GET_MODE_BITSIZE (op_mode) <= HOST_BITS_PER_WIDE_INT)
6944 mask >>= INTVAL (XEXP (x, 1));
6948 op0 = gen_lowpart_for_combine (op_mode,
6949 force_to_mode (XEXP (x, 0), op_mode,
6950 mask, reg, next_select));
6952 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0))
6953 x = gen_binary (code, op_mode, op0, XEXP (x, 1));
6957 /* Here we can only do something if the shift count is a constant,
6958 this shift constant is valid for the host, and we can do arithmetic
6961 if (GET_CODE (XEXP (x, 1)) == CONST_INT
6962 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT
6963 && GET_MODE_BITSIZE (op_mode) <= HOST_BITS_PER_WIDE_INT)
6965 rtx inner = XEXP (x, 0);
6966 unsigned HOST_WIDE_INT inner_mask;
6968 /* Select the mask of the bits we need for the shift operand. */
6969 inner_mask = mask << INTVAL (XEXP (x, 1));
6971 /* We can only change the mode of the shift if we can do arithmetic
6972 in the mode of the shift and INNER_MASK is no wider than the
6973 width of OP_MODE. */
6974 if (GET_MODE_BITSIZE (op_mode) > HOST_BITS_PER_WIDE_INT
6975 || (inner_mask & ~GET_MODE_MASK (op_mode)) != 0)
6976 op_mode = GET_MODE (x);
6978 inner = force_to_mode (inner, op_mode, inner_mask, reg, next_select);
6980 if (GET_MODE (x) != op_mode || inner != XEXP (x, 0))
6981 x = gen_binary (LSHIFTRT, op_mode, inner, XEXP (x, 1));
6984 /* If we have (and (lshiftrt FOO C1) C2) where the combination of the
6985 shift and AND produces only copies of the sign bit (C2 is one less
6986 than a power of two), we can do this with just a shift. */
6988 if (GET_CODE (x) == LSHIFTRT
6989 && GET_CODE (XEXP (x, 1)) == CONST_INT
6990 /* The shift puts one of the sign bit copies in the least significant
6992 && ((INTVAL (XEXP (x, 1))
6993 + num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0))))
6994 >= GET_MODE_BITSIZE (GET_MODE (x)))
6995 && exact_log2 (mask + 1) >= 0
6996 /* Number of bits left after the shift must be more than the mask
6998 && ((INTVAL (XEXP (x, 1)) + exact_log2 (mask + 1))
6999 <= GET_MODE_BITSIZE (GET_MODE (x)))
7000 /* Must be more sign bit copies than the mask needs. */
7001 && ((int) num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
7002 >= exact_log2 (mask + 1)))
7003 x = gen_binary (LSHIFTRT, GET_MODE (x), XEXP (x, 0),
7004 GEN_INT (GET_MODE_BITSIZE (GET_MODE (x))
7005 - exact_log2 (mask + 1)));
7010 /* If we are just looking for the sign bit, we don't need this shift at
7011 all, even if it has a variable count. */
7012 if (GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
7013 && (mask == ((unsigned HOST_WIDE_INT) 1
7014 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
7015 return force_to_mode (XEXP (x, 0), mode, mask, reg, next_select);
7017 /* If this is a shift by a constant, get a mask that contains those bits
7018 that are not copies of the sign bit. We then have two cases: If
7019 MASK only includes those bits, this can be a logical shift, which may
7020 allow simplifications. If MASK is a single-bit field not within
7021 those bits, we are requesting a copy of the sign bit and hence can
7022 shift the sign bit to the appropriate location. */
7024 if (GET_CODE (XEXP (x, 1)) == CONST_INT && INTVAL (XEXP (x, 1)) >= 0
7025 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT)
7029 /* If the considered data is wider than HOST_WIDE_INT, we can't
7030 represent a mask for all its bits in a single scalar.
7031 But we only care about the lower bits, so calculate these. */
7033 if (GET_MODE_BITSIZE (GET_MODE (x)) > HOST_BITS_PER_WIDE_INT)
7035 nonzero = ~(HOST_WIDE_INT) 0;
7037 /* GET_MODE_BITSIZE (GET_MODE (x)) - INTVAL (XEXP (x, 1))
7038 is the number of bits a full-width mask would have set.
7039 We need only shift if these are fewer than nonzero can
7040 hold. If not, we must keep all bits set in nonzero. */
7042 if (GET_MODE_BITSIZE (GET_MODE (x)) - INTVAL (XEXP (x, 1))
7043 < HOST_BITS_PER_WIDE_INT)
7044 nonzero >>= INTVAL (XEXP (x, 1))
7045 + HOST_BITS_PER_WIDE_INT
7046 - GET_MODE_BITSIZE (GET_MODE (x)) ;
7050 nonzero = GET_MODE_MASK (GET_MODE (x));
7051 nonzero >>= INTVAL (XEXP (x, 1));
7054 if ((mask & ~nonzero) == 0
7055 || (i = exact_log2 (mask)) >= 0)
7057 x = simplify_shift_const
7058 (x, LSHIFTRT, GET_MODE (x), XEXP (x, 0),
7059 i < 0 ? INTVAL (XEXP (x, 1))
7060 : GET_MODE_BITSIZE (GET_MODE (x)) - 1 - i);
7062 if (GET_CODE (x) != ASHIFTRT)
7063 return force_to_mode (x, mode, mask, reg, next_select);
7067 /* If MASK is 1, convert this to a LSHIFTRT. This can be done
7068 even if the shift count isn't a constant. */
7070 x = gen_binary (LSHIFTRT, GET_MODE (x), XEXP (x, 0), XEXP (x, 1));
7074 /* If this is a zero- or sign-extension operation that just affects bits
7075 we don't care about, remove it. Be sure the call above returned
7076 something that is still a shift. */
7078 if ((GET_CODE (x) == LSHIFTRT || GET_CODE (x) == ASHIFTRT)
7079 && GET_CODE (XEXP (x, 1)) == CONST_INT
7080 && INTVAL (XEXP (x, 1)) >= 0
7081 && (INTVAL (XEXP (x, 1))
7082 <= GET_MODE_BITSIZE (GET_MODE (x)) - (floor_log2 (mask) + 1))
7083 && GET_CODE (XEXP (x, 0)) == ASHIFT
7084 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
7085 && INTVAL (XEXP (XEXP (x, 0), 1)) == INTVAL (XEXP (x, 1)))
7086 return force_to_mode (XEXP (XEXP (x, 0), 0), mode, mask,
7093 /* If the shift count is constant and we can do computations
7094 in the mode of X, compute where the bits we care about are.
7095 Otherwise, we can't do anything. Don't change the mode of
7096 the shift or propagate MODE into the shift, though. */
7097 if (GET_CODE (XEXP (x, 1)) == CONST_INT
7098 && INTVAL (XEXP (x, 1)) >= 0)
7100 temp = simplify_binary_operation (code == ROTATE ? ROTATERT : ROTATE,
7101 GET_MODE (x), GEN_INT (mask),
7103 if (temp && GET_CODE(temp) == CONST_INT)
7105 force_to_mode (XEXP (x, 0), GET_MODE (x),
7106 INTVAL (temp), reg, next_select));
7111 /* If we just want the low-order bit, the NEG isn't needed since it
7112 won't change the low-order bit. */
7114 return force_to_mode (XEXP (x, 0), mode, mask, reg, just_select);
7116 /* We need any bits less significant than the most significant bit in
7117 MASK since carries from those bits will affect the bits we are
7123 /* (not FOO) is (xor FOO CONST), so if FOO is an LSHIFTRT, we can do the
7124 same as the XOR case above. Ensure that the constant we form is not
7125 wider than the mode of X. */
7127 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
7128 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
7129 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
7130 && (INTVAL (XEXP (XEXP (x, 0), 1)) + floor_log2 (mask)
7131 < GET_MODE_BITSIZE (GET_MODE (x)))
7132 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT)
7134 temp = GEN_INT (mask << INTVAL (XEXP (XEXP (x, 0), 1)));
7135 temp = gen_binary (XOR, GET_MODE (x), XEXP (XEXP (x, 0), 0), temp);
7136 x = gen_binary (LSHIFTRT, GET_MODE (x), temp, XEXP (XEXP (x, 0), 1));
7138 return force_to_mode (x, mode, mask, reg, next_select);
7141 /* (and (not FOO) CONST) is (not (or FOO (not CONST))), so we must
7142 use the full mask inside the NOT. */
7146 op0 = gen_lowpart_for_combine (op_mode,
7147 force_to_mode (XEXP (x, 0), mode, mask,
7149 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0))
7150 x = simplify_gen_unary (code, op_mode, op0, op_mode);
7154 /* (and (ne FOO 0) CONST) can be (and FOO CONST) if CONST is included
7155 in STORE_FLAG_VALUE and FOO has a single bit that might be nonzero,
7156 which is equal to STORE_FLAG_VALUE. */
7157 if ((mask & ~STORE_FLAG_VALUE) == 0 && XEXP (x, 1) == const0_rtx
7158 && exact_log2 (nonzero_bits (XEXP (x, 0), mode)) >= 0
7159 && nonzero_bits (XEXP (x, 0), mode) == STORE_FLAG_VALUE)
7160 return force_to_mode (XEXP (x, 0), mode, mask, reg, next_select);
7165 /* We have no way of knowing if the IF_THEN_ELSE can itself be
7166 written in a narrower mode. We play it safe and do not do so. */
7169 gen_lowpart_for_combine (GET_MODE (x),
7170 force_to_mode (XEXP (x, 1), mode,
7171 mask, reg, next_select)));
7173 gen_lowpart_for_combine (GET_MODE (x),
7174 force_to_mode (XEXP (x, 2), mode,
7175 mask, reg,next_select)));
7182 /* Ensure we return a value of the proper mode. */
7183 return gen_lowpart_for_combine (mode, x);
7186 /* Return nonzero if X is an expression that has one of two values depending on
7187 whether some other value is zero or nonzero. In that case, we return the
7188 value that is being tested, *PTRUE is set to the value if the rtx being
7189 returned has a nonzero value, and *PFALSE is set to the other alternative.
7191 If we return zero, we set *PTRUE and *PFALSE to X. */
7194 if_then_else_cond (x, ptrue, pfalse)
7196 rtx *ptrue, *pfalse;
7198 enum machine_mode mode = GET_MODE (x);
7199 enum rtx_code code = GET_CODE (x);
7200 rtx cond0, cond1, true0, true1, false0, false1;
7201 unsigned HOST_WIDE_INT nz;
7203 /* If we are comparing a value against zero, we are done. */
7204 if ((code == NE || code == EQ)
7205 && GET_CODE (XEXP (x, 1)) == CONST_INT && INTVAL (XEXP (x, 1)) == 0)
7207 *ptrue = (code == NE) ? const_true_rtx : const0_rtx;
7208 *pfalse = (code == NE) ? const0_rtx : const_true_rtx;
7212 /* If this is a unary operation whose operand has one of two values, apply
7213 our opcode to compute those values. */
7214 else if (GET_RTX_CLASS (code) == '1'
7215 && (cond0 = if_then_else_cond (XEXP (x, 0), &true0, &false0)) != 0)
7217 *ptrue = simplify_gen_unary (code, mode, true0, GET_MODE (XEXP (x, 0)));
7218 *pfalse = simplify_gen_unary (code, mode, false0,
7219 GET_MODE (XEXP (x, 0)));
7223 /* If this is a COMPARE, do nothing, since the IF_THEN_ELSE we would
7224 make can't possibly match and would suppress other optimizations. */
7225 else if (code == COMPARE)
7228 /* If this is a binary operation, see if either side has only one of two
7229 values. If either one does or if both do and they are conditional on
7230 the same value, compute the new true and false values. */
7231 else if (GET_RTX_CLASS (code) == 'c' || GET_RTX_CLASS (code) == '2'
7232 || GET_RTX_CLASS (code) == '<')
7234 cond0 = if_then_else_cond (XEXP (x, 0), &true0, &false0);
7235 cond1 = if_then_else_cond (XEXP (x, 1), &true1, &false1);
7237 if ((cond0 != 0 || cond1 != 0)
7238 && ! (cond0 != 0 && cond1 != 0 && ! rtx_equal_p (cond0, cond1)))
7240 /* If if_then_else_cond returned zero, then true/false are the
7241 same rtl. We must copy one of them to prevent invalid rtl
7244 true0 = copy_rtx (true0);
7245 else if (cond1 == 0)
7246 true1 = copy_rtx (true1);
7248 *ptrue = gen_binary (code, mode, true0, true1);
7249 *pfalse = gen_binary (code, mode, false0, false1);
7250 return cond0 ? cond0 : cond1;
7253 /* See if we have PLUS, IOR, XOR, MINUS or UMAX, where one of the
7254 operands is zero when the other is non-zero, and vice-versa,
7255 and STORE_FLAG_VALUE is 1 or -1. */
7257 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
7258 && (code == PLUS || code == IOR || code == XOR || code == MINUS
7260 && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT)
7262 rtx op0 = XEXP (XEXP (x, 0), 1);
7263 rtx op1 = XEXP (XEXP (x, 1), 1);
7265 cond0 = XEXP (XEXP (x, 0), 0);
7266 cond1 = XEXP (XEXP (x, 1), 0);
7268 if (GET_RTX_CLASS (GET_CODE (cond0)) == '<'
7269 && GET_RTX_CLASS (GET_CODE (cond1)) == '<'
7270 && ((GET_CODE (cond0) == combine_reversed_comparison_code (cond1)
7271 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0))
7272 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1)))
7273 || ((swap_condition (GET_CODE (cond0))
7274 == combine_reversed_comparison_code (cond1))
7275 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1))
7276 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0))))
7277 && ! side_effects_p (x))
7279 *ptrue = gen_binary (MULT, mode, op0, const_true_rtx);
7280 *pfalse = gen_binary (MULT, mode,
7282 ? simplify_gen_unary (NEG, mode, op1,
7290 /* Similarly for MULT, AND and UMIN, except that for these the result
7292 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
7293 && (code == MULT || code == AND || code == UMIN)
7294 && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT)
7296 cond0 = XEXP (XEXP (x, 0), 0);
7297 cond1 = XEXP (XEXP (x, 1), 0);
7299 if (GET_RTX_CLASS (GET_CODE (cond0)) == '<'
7300 && GET_RTX_CLASS (GET_CODE (cond1)) == '<'
7301 && ((GET_CODE (cond0) == combine_reversed_comparison_code (cond1)
7302 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0))
7303 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1)))
7304 || ((swap_condition (GET_CODE (cond0))
7305 == combine_reversed_comparison_code (cond1))
7306 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1))
7307 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0))))
7308 && ! side_effects_p (x))
7310 *ptrue = *pfalse = const0_rtx;
7316 else if (code == IF_THEN_ELSE)
7318 /* If we have IF_THEN_ELSE already, extract the condition and
7319 canonicalize it if it is NE or EQ. */
7320 cond0 = XEXP (x, 0);
7321 *ptrue = XEXP (x, 1), *pfalse = XEXP (x, 2);
7322 if (GET_CODE (cond0) == NE && XEXP (cond0, 1) == const0_rtx)
7323 return XEXP (cond0, 0);
7324 else if (GET_CODE (cond0) == EQ && XEXP (cond0, 1) == const0_rtx)
7326 *ptrue = XEXP (x, 2), *pfalse = XEXP (x, 1);
7327 return XEXP (cond0, 0);
7333 /* If X is a SUBREG, we can narrow both the true and false values
7334 if the inner expression, if there is a condition. */
7335 else if (code == SUBREG
7336 && 0 != (cond0 = if_then_else_cond (SUBREG_REG (x),
7339 *ptrue = simplify_gen_subreg (mode, true0,
7340 GET_MODE (SUBREG_REG (x)), SUBREG_BYTE (x));
7341 *pfalse = simplify_gen_subreg (mode, false0,
7342 GET_MODE (SUBREG_REG (x)), SUBREG_BYTE (x));
7347 /* If X is a constant, this isn't special and will cause confusions
7348 if we treat it as such. Likewise if it is equivalent to a constant. */
7349 else if (CONSTANT_P (x)
7350 || ((cond0 = get_last_value (x)) != 0 && CONSTANT_P (cond0)))
7353 /* If we're in BImode, canonicalize on 0 and STORE_FLAG_VALUE, as that
7354 will be least confusing to the rest of the compiler. */
7355 else if (mode == BImode)
7357 *ptrue = GEN_INT (STORE_FLAG_VALUE), *pfalse = const0_rtx;
7361 /* If X is known to be either 0 or -1, those are the true and
7362 false values when testing X. */
7363 else if (x == constm1_rtx || x == const0_rtx
7364 || (mode != VOIDmode
7365 && num_sign_bit_copies (x, mode) == GET_MODE_BITSIZE (mode)))
7367 *ptrue = constm1_rtx, *pfalse = const0_rtx;
7371 /* Likewise for 0 or a single bit. */
7372 else if (mode != VOIDmode
7373 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
7374 && exact_log2 (nz = nonzero_bits (x, mode)) >= 0)
7376 *ptrue = GEN_INT (nz), *pfalse = const0_rtx;
7380 /* Otherwise fail; show no condition with true and false values the same. */
7381 *ptrue = *pfalse = x;
7385 /* Return the value of expression X given the fact that condition COND
7386 is known to be true when applied to REG as its first operand and VAL
7387 as its second. X is known to not be shared and so can be modified in
7390 We only handle the simplest cases, and specifically those cases that
7391 arise with IF_THEN_ELSE expressions. */
7394 known_cond (x, cond, reg, val)
7399 enum rtx_code code = GET_CODE (x);
7404 if (side_effects_p (x))
7407 /* If either operand of the condition is a floating point value,
7408 then we have to avoid collapsing an EQ comparison. */
7410 && rtx_equal_p (x, reg)
7411 && ! FLOAT_MODE_P (GET_MODE (x))
7412 && ! FLOAT_MODE_P (GET_MODE (val)))
7415 if (cond == UNEQ && rtx_equal_p (x, reg))
7418 /* If X is (abs REG) and we know something about REG's relationship
7419 with zero, we may be able to simplify this. */
7421 if (code == ABS && rtx_equal_p (XEXP (x, 0), reg) && val == const0_rtx)
7424 case GE: case GT: case EQ:
7427 return simplify_gen_unary (NEG, GET_MODE (XEXP (x, 0)),
7429 GET_MODE (XEXP (x, 0)));
7434 /* The only other cases we handle are MIN, MAX, and comparisons if the
7435 operands are the same as REG and VAL. */
7437 else if (GET_RTX_CLASS (code) == '<' || GET_RTX_CLASS (code) == 'c')
7439 if (rtx_equal_p (XEXP (x, 0), val))
7440 cond = swap_condition (cond), temp = val, val = reg, reg = temp;
7442 if (rtx_equal_p (XEXP (x, 0), reg) && rtx_equal_p (XEXP (x, 1), val))
7444 if (GET_RTX_CLASS (code) == '<')
7446 if (comparison_dominates_p (cond, code))
7447 return const_true_rtx;
7449 code = combine_reversed_comparison_code (x);
7451 && comparison_dominates_p (cond, code))
7456 else if (code == SMAX || code == SMIN
7457 || code == UMIN || code == UMAX)
7459 int unsignedp = (code == UMIN || code == UMAX);
7461 /* Do not reverse the condition when it is NE or EQ.
7462 This is because we cannot conclude anything about
7463 the value of 'SMAX (x, y)' when x is not equal to y,
7464 but we can when x equals y. */
7465 if ((code == SMAX || code == UMAX)
7466 && ! (cond == EQ || cond == NE))
7467 cond = reverse_condition (cond);
7472 return unsignedp ? x : XEXP (x, 1);
7474 return unsignedp ? x : XEXP (x, 0);
7476 return unsignedp ? XEXP (x, 1) : x;
7478 return unsignedp ? XEXP (x, 0) : x;
7485 else if (code == SUBREG)
7487 enum machine_mode inner_mode = GET_MODE (SUBREG_REG (x));
7488 rtx new, r = known_cond (SUBREG_REG (x), cond, reg, val);
7490 if (SUBREG_REG (x) != r)
7492 /* We must simplify subreg here, before we lose track of the
7493 original inner_mode. */
7494 new = simplify_subreg (GET_MODE (x), r,
7495 inner_mode, SUBREG_BYTE (x));
7499 SUBST (SUBREG_REG (x), r);
7504 /* We don't have to handle SIGN_EXTEND here, because even in the
7505 case of replacing something with a modeless CONST_INT, a
7506 CONST_INT is already (supposed to be) a valid sign extension for
7507 its narrower mode, which implies it's already properly
7508 sign-extended for the wider mode. Now, for ZERO_EXTEND, the
7509 story is different. */
7510 else if (code == ZERO_EXTEND)
7512 enum machine_mode inner_mode = GET_MODE (XEXP (x, 0));
7513 rtx new, r = known_cond (XEXP (x, 0), cond, reg, val);
7515 if (XEXP (x, 0) != r)
7517 /* We must simplify the zero_extend here, before we lose
7518 track of the original inner_mode. */
7519 new = simplify_unary_operation (ZERO_EXTEND, GET_MODE (x),
7524 SUBST (XEXP (x, 0), r);
7530 fmt = GET_RTX_FORMAT (code);
7531 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
7534 SUBST (XEXP (x, i), known_cond (XEXP (x, i), cond, reg, val));
7535 else if (fmt[i] == 'E')
7536 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
7537 SUBST (XVECEXP (x, i, j), known_cond (XVECEXP (x, i, j),
7544 /* See if X and Y are equal for the purposes of seeing if we can rewrite an
7545 assignment as a field assignment. */
7548 rtx_equal_for_field_assignment_p (x, y)
7552 if (x == y || rtx_equal_p (x, y))
7555 if (x == 0 || y == 0 || GET_MODE (x) != GET_MODE (y))
7558 /* Check for a paradoxical SUBREG of a MEM compared with the MEM.
7559 Note that all SUBREGs of MEM are paradoxical; otherwise they
7560 would have been rewritten. */
7561 if (GET_CODE (x) == MEM && GET_CODE (y) == SUBREG
7562 && GET_CODE (SUBREG_REG (y)) == MEM
7563 && rtx_equal_p (SUBREG_REG (y),
7564 gen_lowpart_for_combine (GET_MODE (SUBREG_REG (y)), x)))
7567 if (GET_CODE (y) == MEM && GET_CODE (x) == SUBREG
7568 && GET_CODE (SUBREG_REG (x)) == MEM
7569 && rtx_equal_p (SUBREG_REG (x),
7570 gen_lowpart_for_combine (GET_MODE (SUBREG_REG (x)), y)))
7573 /* We used to see if get_last_value of X and Y were the same but that's
7574 not correct. In one direction, we'll cause the assignment to have
7575 the wrong destination and in the case, we'll import a register into this
7576 insn that might have already have been dead. So fail if none of the
7577 above cases are true. */
7581 /* See if X, a SET operation, can be rewritten as a bit-field assignment.
7582 Return that assignment if so.
7584 We only handle the most common cases. */
7587 make_field_assignment (x)
7590 rtx dest = SET_DEST (x);
7591 rtx src = SET_SRC (x);
7596 unsigned HOST_WIDE_INT len;
7598 enum machine_mode mode;
7600 /* If SRC was (and (not (ashift (const_int 1) POS)) DEST), this is
7601 a clear of a one-bit field. We will have changed it to
7602 (and (rotate (const_int -2) POS) DEST), so check for that. Also check
7605 if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == ROTATE
7606 && GET_CODE (XEXP (XEXP (src, 0), 0)) == CONST_INT
7607 && INTVAL (XEXP (XEXP (src, 0), 0)) == -2
7608 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
7610 assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1),
7613 return gen_rtx_SET (VOIDmode, assign, const0_rtx);
7617 else if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == SUBREG
7618 && subreg_lowpart_p (XEXP (src, 0))
7619 && (GET_MODE_SIZE (GET_MODE (XEXP (src, 0)))
7620 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (src, 0)))))
7621 && GET_CODE (SUBREG_REG (XEXP (src, 0))) == ROTATE
7622 && INTVAL (XEXP (SUBREG_REG (XEXP (src, 0)), 0)) == -2
7623 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
7625 assign = make_extraction (VOIDmode, dest, 0,
7626 XEXP (SUBREG_REG (XEXP (src, 0)), 1),
7629 return gen_rtx_SET (VOIDmode, assign, const0_rtx);
7633 /* If SRC is (ior (ashift (const_int 1) POS) DEST), this is a set of a
7635 else if (GET_CODE (src) == IOR && GET_CODE (XEXP (src, 0)) == ASHIFT
7636 && XEXP (XEXP (src, 0), 0) == const1_rtx
7637 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
7639 assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1),
7642 return gen_rtx_SET (VOIDmode, assign, const1_rtx);
7646 /* The other case we handle is assignments into a constant-position
7647 field. They look like (ior/xor (and DEST C1) OTHER). If C1 represents
7648 a mask that has all one bits except for a group of zero bits and
7649 OTHER is known to have zeros where C1 has ones, this is such an
7650 assignment. Compute the position and length from C1. Shift OTHER
7651 to the appropriate position, force it to the required mode, and
7652 make the extraction. Check for the AND in both operands. */
7654 if (GET_CODE (src) != IOR && GET_CODE (src) != XOR)
7657 rhs = expand_compound_operation (XEXP (src, 0));
7658 lhs = expand_compound_operation (XEXP (src, 1));
7660 if (GET_CODE (rhs) == AND
7661 && GET_CODE (XEXP (rhs, 1)) == CONST_INT
7662 && rtx_equal_for_field_assignment_p (XEXP (rhs, 0), dest))
7663 c1 = INTVAL (XEXP (rhs, 1)), other = lhs;
7664 else if (GET_CODE (lhs) == AND
7665 && GET_CODE (XEXP (lhs, 1)) == CONST_INT
7666 && rtx_equal_for_field_assignment_p (XEXP (lhs, 0), dest))
7667 c1 = INTVAL (XEXP (lhs, 1)), other = rhs;
7671 pos = get_pos_from_mask ((~c1) & GET_MODE_MASK (GET_MODE (dest)), &len);
7672 if (pos < 0 || pos + len > GET_MODE_BITSIZE (GET_MODE (dest))
7673 || GET_MODE_BITSIZE (GET_MODE (dest)) > HOST_BITS_PER_WIDE_INT
7674 || (c1 & nonzero_bits (other, GET_MODE (dest))) != 0)
7677 assign = make_extraction (VOIDmode, dest, pos, NULL_RTX, len, 1, 1, 0);
7681 /* The mode to use for the source is the mode of the assignment, or of
7682 what is inside a possible STRICT_LOW_PART. */
7683 mode = (GET_CODE (assign) == STRICT_LOW_PART
7684 ? GET_MODE (XEXP (assign, 0)) : GET_MODE (assign));
7686 /* Shift OTHER right POS places and make it the source, restricting it
7687 to the proper length and mode. */
7689 src = force_to_mode (simplify_shift_const (NULL_RTX, LSHIFTRT,
7690 GET_MODE (src), other, pos),
7692 GET_MODE_BITSIZE (mode) >= HOST_BITS_PER_WIDE_INT
7693 ? ~(unsigned HOST_WIDE_INT) 0
7694 : ((unsigned HOST_WIDE_INT) 1 << len) - 1,
7697 return gen_rtx_SET (VOIDmode, assign, src);
7700 /* See if X is of the form (+ (* a c) (* b c)) and convert to (* (+ a b) c)
7704 apply_distributive_law (x)
7707 enum rtx_code code = GET_CODE (x);
7708 rtx lhs, rhs, other;
7710 enum rtx_code inner_code;
7712 /* Distributivity is not true for floating point.
7713 It can change the value. So don't do it.
7714 -- rms and moshier@world.std.com. */
7715 if (FLOAT_MODE_P (GET_MODE (x)))
7718 /* The outer operation can only be one of the following: */
7719 if (code != IOR && code != AND && code != XOR
7720 && code != PLUS && code != MINUS)
7723 lhs = XEXP (x, 0), rhs = XEXP (x, 1);
7725 /* If either operand is a primitive we can't do anything, so get out
7727 if (GET_RTX_CLASS (GET_CODE (lhs)) == 'o'
7728 || GET_RTX_CLASS (GET_CODE (rhs)) == 'o')
7731 lhs = expand_compound_operation (lhs);
7732 rhs = expand_compound_operation (rhs);
7733 inner_code = GET_CODE (lhs);
7734 if (inner_code != GET_CODE (rhs))
7737 /* See if the inner and outer operations distribute. */
7744 /* These all distribute except over PLUS. */
7745 if (code == PLUS || code == MINUS)
7750 if (code != PLUS && code != MINUS)
7755 /* This is also a multiply, so it distributes over everything. */
7759 /* Non-paradoxical SUBREGs distributes over all operations, provided
7760 the inner modes and byte offsets are the same, this is an extraction
7761 of a low-order part, we don't convert an fp operation to int or
7762 vice versa, and we would not be converting a single-word
7763 operation into a multi-word operation. The latter test is not
7764 required, but it prevents generating unneeded multi-word operations.
7765 Some of the previous tests are redundant given the latter test, but
7766 are retained because they are required for correctness.
7768 We produce the result slightly differently in this case. */
7770 if (GET_MODE (SUBREG_REG (lhs)) != GET_MODE (SUBREG_REG (rhs))
7771 || SUBREG_BYTE (lhs) != SUBREG_BYTE (rhs)
7772 || ! subreg_lowpart_p (lhs)
7773 || (GET_MODE_CLASS (GET_MODE (lhs))
7774 != GET_MODE_CLASS (GET_MODE (SUBREG_REG (lhs))))
7775 || (GET_MODE_SIZE (GET_MODE (lhs))
7776 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs))))
7777 || GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs))) > UNITS_PER_WORD)
7780 tem = gen_binary (code, GET_MODE (SUBREG_REG (lhs)),
7781 SUBREG_REG (lhs), SUBREG_REG (rhs));
7782 return gen_lowpart_for_combine (GET_MODE (x), tem);
7788 /* Set LHS and RHS to the inner operands (A and B in the example
7789 above) and set OTHER to the common operand (C in the example).
7790 These is only one way to do this unless the inner operation is
7792 if (GET_RTX_CLASS (inner_code) == 'c'
7793 && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 0)))
7794 other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 1);
7795 else if (GET_RTX_CLASS (inner_code) == 'c'
7796 && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 1)))
7797 other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 0);
7798 else if (GET_RTX_CLASS (inner_code) == 'c'
7799 && rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 0)))
7800 other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 1);
7801 else if (rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 1)))
7802 other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 0);
7806 /* Form the new inner operation, seeing if it simplifies first. */
7807 tem = gen_binary (code, GET_MODE (x), lhs, rhs);
7809 /* There is one exception to the general way of distributing:
7810 (a ^ b) | (a ^ c) -> (~a) & (b ^ c) */
7811 if (code == XOR && inner_code == IOR)
7814 other = simplify_gen_unary (NOT, GET_MODE (x), other, GET_MODE (x));
7817 /* We may be able to continuing distributing the result, so call
7818 ourselves recursively on the inner operation before forming the
7819 outer operation, which we return. */
7820 return gen_binary (inner_code, GET_MODE (x),
7821 apply_distributive_law (tem), other);
7824 /* We have X, a logical `and' of VAROP with the constant CONSTOP, to be done
7827 Return an equivalent form, if different from X. Otherwise, return X. If
7828 X is zero, we are to always construct the equivalent form. */
7831 simplify_and_const_int (x, mode, varop, constop)
7833 enum machine_mode mode;
7835 unsigned HOST_WIDE_INT constop;
7837 unsigned HOST_WIDE_INT nonzero;
7840 /* Simplify VAROP knowing that we will be only looking at some of the
7842 varop = force_to_mode (varop, mode, constop, NULL_RTX, 0);
7844 /* If VAROP is a CLOBBER, we will fail so return it; if it is a
7845 CONST_INT, we are done. */
7846 if (GET_CODE (varop) == CLOBBER || GET_CODE (varop) == CONST_INT)
7849 /* See what bits may be nonzero in VAROP. Unlike the general case of
7850 a call to nonzero_bits, here we don't care about bits outside
7853 nonzero = nonzero_bits (varop, mode) & GET_MODE_MASK (mode);
7855 /* Turn off all bits in the constant that are known to already be zero.
7856 Thus, if the AND isn't needed at all, we will have CONSTOP == NONZERO_BITS
7857 which is tested below. */
7861 /* If we don't have any bits left, return zero. */
7865 /* If VAROP is a NEG of something known to be zero or 1 and CONSTOP is
7866 a power of two, we can replace this with a ASHIFT. */
7867 if (GET_CODE (varop) == NEG && nonzero_bits (XEXP (varop, 0), mode) == 1
7868 && (i = exact_log2 (constop)) >= 0)
7869 return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (varop, 0), i);
7871 /* If VAROP is an IOR or XOR, apply the AND to both branches of the IOR
7872 or XOR, then try to apply the distributive law. This may eliminate
7873 operations if either branch can be simplified because of the AND.
7874 It may also make some cases more complex, but those cases probably
7875 won't match a pattern either with or without this. */
7877 if (GET_CODE (varop) == IOR || GET_CODE (varop) == XOR)
7879 gen_lowpart_for_combine
7881 apply_distributive_law
7882 (gen_binary (GET_CODE (varop), GET_MODE (varop),
7883 simplify_and_const_int (NULL_RTX, GET_MODE (varop),
7884 XEXP (varop, 0), constop),
7885 simplify_and_const_int (NULL_RTX, GET_MODE (varop),
7886 XEXP (varop, 1), constop))));
7888 /* If VAROP is PLUS, and the constant is a mask of low bite, distribute
7889 the AND and see if one of the operands simplifies to zero. If so, we
7890 may eliminate it. */
7892 if (GET_CODE (varop) == PLUS
7893 && exact_log2 (constop + 1) >= 0)
7897 o0 = simplify_and_const_int (NULL_RTX, mode, XEXP (varop, 0), constop);
7898 o1 = simplify_and_const_int (NULL_RTX, mode, XEXP (varop, 1), constop);
7899 if (o0 == const0_rtx)
7901 if (o1 == const0_rtx)
7905 /* Get VAROP in MODE. Try to get a SUBREG if not. Don't make a new SUBREG
7906 if we already had one (just check for the simplest cases). */
7907 if (x && GET_CODE (XEXP (x, 0)) == SUBREG
7908 && GET_MODE (XEXP (x, 0)) == mode
7909 && SUBREG_REG (XEXP (x, 0)) == varop)
7910 varop = XEXP (x, 0);
7912 varop = gen_lowpart_for_combine (mode, varop);
7914 /* If we can't make the SUBREG, try to return what we were given. */
7915 if (GET_CODE (varop) == CLOBBER)
7916 return x ? x : varop;
7918 /* If we are only masking insignificant bits, return VAROP. */
7919 if (constop == nonzero)
7923 /* Otherwise, return an AND. */
7924 constop = trunc_int_for_mode (constop, mode);
7925 /* See how much, if any, of X we can use. */
7926 if (x == 0 || GET_CODE (x) != AND || GET_MODE (x) != mode)
7927 x = gen_binary (AND, mode, varop, GEN_INT (constop));
7931 if (GET_CODE (XEXP (x, 1)) != CONST_INT
7932 || (unsigned HOST_WIDE_INT) INTVAL (XEXP (x, 1)) != constop)
7933 SUBST (XEXP (x, 1), GEN_INT (constop));
7935 SUBST (XEXP (x, 0), varop);
7942 /* We let num_sign_bit_copies recur into nonzero_bits as that is useful.
7943 We don't let nonzero_bits recur into num_sign_bit_copies, because that
7944 is less useful. We can't allow both, because that results in exponential
7945 run time recursion. There is a nullstone testcase that triggered
7946 this. This macro avoids accidental uses of num_sign_bit_copies. */
7947 #define num_sign_bit_copies()
7949 /* Given an expression, X, compute which bits in X can be non-zero.
7950 We don't care about bits outside of those defined in MODE.
7952 For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is
7953 a shift, AND, or zero_extract, we can do better. */
7955 static unsigned HOST_WIDE_INT
7956 nonzero_bits (x, mode)
7958 enum machine_mode mode;
7960 unsigned HOST_WIDE_INT nonzero = GET_MODE_MASK (mode);
7961 unsigned HOST_WIDE_INT inner_nz;
7963 unsigned int mode_width = GET_MODE_BITSIZE (mode);
7966 /* For floating-point values, assume all bits are needed. */
7967 if (FLOAT_MODE_P (GET_MODE (x)) || FLOAT_MODE_P (mode))
7970 /* If X is wider than MODE, use its mode instead. */
7971 if (GET_MODE_BITSIZE (GET_MODE (x)) > mode_width)
7973 mode = GET_MODE (x);
7974 nonzero = GET_MODE_MASK (mode);
7975 mode_width = GET_MODE_BITSIZE (mode);
7978 if (mode_width > HOST_BITS_PER_WIDE_INT)
7979 /* Our only callers in this case look for single bit values. So
7980 just return the mode mask. Those tests will then be false. */
7983 #ifndef WORD_REGISTER_OPERATIONS
7984 /* If MODE is wider than X, but both are a single word for both the host
7985 and target machines, we can compute this from which bits of the
7986 object might be nonzero in its own mode, taking into account the fact
7987 that on many CISC machines, accessing an object in a wider mode
7988 causes the high-order bits to become undefined. So they are
7989 not known to be zero. */
7991 if (GET_MODE (x) != VOIDmode && GET_MODE (x) != mode
7992 && GET_MODE_BITSIZE (GET_MODE (x)) <= BITS_PER_WORD
7993 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
7994 && GET_MODE_BITSIZE (mode) > GET_MODE_BITSIZE (GET_MODE (x)))
7996 nonzero &= nonzero_bits (x, GET_MODE (x));
7997 nonzero |= GET_MODE_MASK (mode) & ~GET_MODE_MASK (GET_MODE (x));
8002 code = GET_CODE (x);
8006 #if defined(POINTERS_EXTEND_UNSIGNED) && !defined(HAVE_ptr_extend)
8007 /* If pointers extend unsigned and this is a pointer in Pmode, say that
8008 all the bits above ptr_mode are known to be zero. */
8009 if (POINTERS_EXTEND_UNSIGNED && GET_MODE (x) == Pmode
8011 nonzero &= GET_MODE_MASK (ptr_mode);
8014 /* Include declared information about alignment of pointers. */
8015 /* ??? We don't properly preserve REG_POINTER changes across
8016 pointer-to-integer casts, so we can't trust it except for
8017 things that we know must be pointers. See execute/960116-1.c. */
8018 if ((x == stack_pointer_rtx
8019 || x == frame_pointer_rtx
8020 || x == arg_pointer_rtx)
8021 && REGNO_POINTER_ALIGN (REGNO (x)))
8023 unsigned HOST_WIDE_INT alignment
8024 = REGNO_POINTER_ALIGN (REGNO (x)) / BITS_PER_UNIT;
8026 #ifdef PUSH_ROUNDING
8027 /* If PUSH_ROUNDING is defined, it is possible for the
8028 stack to be momentarily aligned only to that amount,
8029 so we pick the least alignment. */
8030 if (x == stack_pointer_rtx && PUSH_ARGS)
8031 alignment = MIN (PUSH_ROUNDING (1), alignment);
8034 nonzero &= ~(alignment - 1);
8037 /* If X is a register whose nonzero bits value is current, use it.
8038 Otherwise, if X is a register whose value we can find, use that
8039 value. Otherwise, use the previously-computed global nonzero bits
8040 for this register. */
8042 if (reg_last_set_value[REGNO (x)] != 0
8043 && reg_last_set_mode[REGNO (x)] == mode
8044 && (reg_last_set_label[REGNO (x)] == label_tick
8045 || (REGNO (x) >= FIRST_PSEUDO_REGISTER
8046 && REG_N_SETS (REGNO (x)) == 1
8047 && ! REGNO_REG_SET_P (BASIC_BLOCK (0)->global_live_at_start,
8049 && INSN_CUID (reg_last_set[REGNO (x)]) < subst_low_cuid)
8050 return reg_last_set_nonzero_bits[REGNO (x)] & nonzero;
8052 tem = get_last_value (x);
8056 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
8057 /* If X is narrower than MODE and TEM is a non-negative
8058 constant that would appear negative in the mode of X,
8059 sign-extend it for use in reg_nonzero_bits because some
8060 machines (maybe most) will actually do the sign-extension
8061 and this is the conservative approach.
8063 ??? For 2.5, try to tighten up the MD files in this regard
8064 instead of this kludge. */
8066 if (GET_MODE_BITSIZE (GET_MODE (x)) < mode_width
8067 && GET_CODE (tem) == CONST_INT
8069 && 0 != (INTVAL (tem)
8070 & ((HOST_WIDE_INT) 1
8071 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
8072 tem = GEN_INT (INTVAL (tem)
8073 | ((HOST_WIDE_INT) (-1)
8074 << GET_MODE_BITSIZE (GET_MODE (x))));
8076 return nonzero_bits (tem, mode) & nonzero;
8078 else if (nonzero_sign_valid && reg_nonzero_bits[REGNO (x)])
8080 unsigned HOST_WIDE_INT mask = reg_nonzero_bits[REGNO (x)];
8082 if (GET_MODE_BITSIZE (GET_MODE (x)) < mode_width)
8083 /* We don't know anything about the upper bits. */
8084 mask |= GET_MODE_MASK (mode) ^ GET_MODE_MASK (GET_MODE (x));
8085 return nonzero & mask;
8091 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
8092 /* If X is negative in MODE, sign-extend the value. */
8093 if (INTVAL (x) > 0 && mode_width < BITS_PER_WORD
8094 && 0 != (INTVAL (x) & ((HOST_WIDE_INT) 1 << (mode_width - 1))))
8095 return (INTVAL (x) | ((HOST_WIDE_INT) (-1) << mode_width));
8101 #ifdef LOAD_EXTEND_OP
8102 /* In many, if not most, RISC machines, reading a byte from memory
8103 zeros the rest of the register. Noticing that fact saves a lot
8104 of extra zero-extends. */
8105 if (LOAD_EXTEND_OP (GET_MODE (x)) == ZERO_EXTEND)
8106 nonzero &= GET_MODE_MASK (GET_MODE (x));
8111 case UNEQ: case LTGT:
8112 case GT: case GTU: case UNGT:
8113 case LT: case LTU: case UNLT:
8114 case GE: case GEU: case UNGE:
8115 case LE: case LEU: case UNLE:
8116 case UNORDERED: case ORDERED:
8118 /* If this produces an integer result, we know which bits are set.
8119 Code here used to clear bits outside the mode of X, but that is
8122 if (GET_MODE_CLASS (mode) == MODE_INT
8123 && mode_width <= HOST_BITS_PER_WIDE_INT)
8124 nonzero = STORE_FLAG_VALUE;
8129 /* Disabled to avoid exponential mutual recursion between nonzero_bits
8130 and num_sign_bit_copies. */
8131 if (num_sign_bit_copies (XEXP (x, 0), GET_MODE (x))
8132 == GET_MODE_BITSIZE (GET_MODE (x)))
8136 if (GET_MODE_SIZE (GET_MODE (x)) < mode_width)
8137 nonzero |= (GET_MODE_MASK (mode) & ~GET_MODE_MASK (GET_MODE (x)));
8142 /* Disabled to avoid exponential mutual recursion between nonzero_bits
8143 and num_sign_bit_copies. */
8144 if (num_sign_bit_copies (XEXP (x, 0), GET_MODE (x))
8145 == GET_MODE_BITSIZE (GET_MODE (x)))
8151 nonzero &= (nonzero_bits (XEXP (x, 0), mode) & GET_MODE_MASK (mode));
8155 nonzero &= nonzero_bits (XEXP (x, 0), mode);
8156 if (GET_MODE (XEXP (x, 0)) != VOIDmode)
8157 nonzero &= GET_MODE_MASK (GET_MODE (XEXP (x, 0)));
8161 /* If the sign bit is known clear, this is the same as ZERO_EXTEND.
8162 Otherwise, show all the bits in the outer mode but not the inner
8164 inner_nz = nonzero_bits (XEXP (x, 0), mode);
8165 if (GET_MODE (XEXP (x, 0)) != VOIDmode)
8167 inner_nz &= GET_MODE_MASK (GET_MODE (XEXP (x, 0)));
8169 & (((HOST_WIDE_INT) 1
8170 << (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - 1))))
8171 inner_nz |= (GET_MODE_MASK (mode)
8172 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0))));
8175 nonzero &= inner_nz;
8179 nonzero &= (nonzero_bits (XEXP (x, 0), mode)
8180 & nonzero_bits (XEXP (x, 1), mode));
8184 case UMIN: case UMAX: case SMIN: case SMAX:
8185 nonzero &= (nonzero_bits (XEXP (x, 0), mode)
8186 | nonzero_bits (XEXP (x, 1), mode));
8189 case PLUS: case MINUS:
8191 case DIV: case UDIV:
8192 case MOD: case UMOD:
8193 /* We can apply the rules of arithmetic to compute the number of
8194 high- and low-order zero bits of these operations. We start by
8195 computing the width (position of the highest-order non-zero bit)
8196 and the number of low-order zero bits for each value. */
8198 unsigned HOST_WIDE_INT nz0 = nonzero_bits (XEXP (x, 0), mode);
8199 unsigned HOST_WIDE_INT nz1 = nonzero_bits (XEXP (x, 1), mode);
8200 int width0 = floor_log2 (nz0) + 1;
8201 int width1 = floor_log2 (nz1) + 1;
8202 int low0 = floor_log2 (nz0 & -nz0);
8203 int low1 = floor_log2 (nz1 & -nz1);
8204 HOST_WIDE_INT op0_maybe_minusp
8205 = (nz0 & ((HOST_WIDE_INT) 1 << (mode_width - 1)));
8206 HOST_WIDE_INT op1_maybe_minusp
8207 = (nz1 & ((HOST_WIDE_INT) 1 << (mode_width - 1)));
8208 unsigned int result_width = mode_width;
8214 result_width = MAX (width0, width1) + 1;
8215 result_low = MIN (low0, low1);
8218 result_low = MIN (low0, low1);
8221 result_width = width0 + width1;
8222 result_low = low0 + low1;
8227 if (! op0_maybe_minusp && ! op1_maybe_minusp)
8228 result_width = width0;
8233 result_width = width0;
8238 if (! op0_maybe_minusp && ! op1_maybe_minusp)
8239 result_width = MIN (width0, width1);
8240 result_low = MIN (low0, low1);
8245 result_width = MIN (width0, width1);
8246 result_low = MIN (low0, low1);
8252 if (result_width < mode_width)
8253 nonzero &= ((HOST_WIDE_INT) 1 << result_width) - 1;
8256 nonzero &= ~(((HOST_WIDE_INT) 1 << result_low) - 1);
8258 #ifdef POINTERS_EXTEND_UNSIGNED
8259 /* If pointers extend unsigned and this is an addition or subtraction
8260 to a pointer in Pmode, all the bits above ptr_mode are known to be
8262 if (POINTERS_EXTEND_UNSIGNED > 0 && GET_MODE (x) == Pmode
8263 && (code == PLUS || code == MINUS)
8264 && GET_CODE (XEXP (x, 0)) == REG && REG_POINTER (XEXP (x, 0)))
8265 nonzero &= GET_MODE_MASK (ptr_mode);
8271 if (GET_CODE (XEXP (x, 1)) == CONST_INT
8272 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT)
8273 nonzero &= ((HOST_WIDE_INT) 1 << INTVAL (XEXP (x, 1))) - 1;
8277 /* If this is a SUBREG formed for a promoted variable that has
8278 been zero-extended, we know that at least the high-order bits
8279 are zero, though others might be too. */
8281 if (SUBREG_PROMOTED_VAR_P (x) && SUBREG_PROMOTED_UNSIGNED_P (x) > 0)
8282 nonzero = (GET_MODE_MASK (GET_MODE (x))
8283 & nonzero_bits (SUBREG_REG (x), GET_MODE (x)));
8285 /* If the inner mode is a single word for both the host and target
8286 machines, we can compute this from which bits of the inner
8287 object might be nonzero. */
8288 if (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x))) <= BITS_PER_WORD
8289 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x)))
8290 <= HOST_BITS_PER_WIDE_INT))
8292 nonzero &= nonzero_bits (SUBREG_REG (x), mode);
8294 #if defined (WORD_REGISTER_OPERATIONS) && defined (LOAD_EXTEND_OP)
8295 /* If this is a typical RISC machine, we only have to worry
8296 about the way loads are extended. */
8297 if (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (x))) == SIGN_EXTEND
8299 & (((unsigned HOST_WIDE_INT) 1
8300 << (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x))) - 1))))
8302 : LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (x))) != ZERO_EXTEND)
8305 /* On many CISC machines, accessing an object in a wider mode
8306 causes the high-order bits to become undefined. So they are
8307 not known to be zero. */
8308 if (GET_MODE_SIZE (GET_MODE (x))
8309 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
8310 nonzero |= (GET_MODE_MASK (GET_MODE (x))
8311 & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (x))));
8320 /* The nonzero bits are in two classes: any bits within MODE
8321 that aren't in GET_MODE (x) are always significant. The rest of the
8322 nonzero bits are those that are significant in the operand of
8323 the shift when shifted the appropriate number of bits. This
8324 shows that high-order bits are cleared by the right shift and
8325 low-order bits by left shifts. */
8326 if (GET_CODE (XEXP (x, 1)) == CONST_INT
8327 && INTVAL (XEXP (x, 1)) >= 0
8328 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT)
8330 enum machine_mode inner_mode = GET_MODE (x);
8331 unsigned int width = GET_MODE_BITSIZE (inner_mode);
8332 int count = INTVAL (XEXP (x, 1));
8333 unsigned HOST_WIDE_INT mode_mask = GET_MODE_MASK (inner_mode);
8334 unsigned HOST_WIDE_INT op_nonzero = nonzero_bits (XEXP (x, 0), mode);
8335 unsigned HOST_WIDE_INT inner = op_nonzero & mode_mask;
8336 unsigned HOST_WIDE_INT outer = 0;
8338 if (mode_width > width)
8339 outer = (op_nonzero & nonzero & ~mode_mask);
8341 if (code == LSHIFTRT)
8343 else if (code == ASHIFTRT)
8347 /* If the sign bit may have been nonzero before the shift, we
8348 need to mark all the places it could have been copied to
8349 by the shift as possibly nonzero. */
8350 if (inner & ((HOST_WIDE_INT) 1 << (width - 1 - count)))
8351 inner |= (((HOST_WIDE_INT) 1 << count) - 1) << (width - count);
8353 else if (code == ASHIFT)
8356 inner = ((inner << (count % width)
8357 | (inner >> (width - (count % width)))) & mode_mask);
8359 nonzero &= (outer | inner);
8364 /* This is at most the number of bits in the mode. */
8365 nonzero = ((HOST_WIDE_INT) 1 << (floor_log2 (mode_width) + 1)) - 1;
8369 nonzero &= (nonzero_bits (XEXP (x, 1), mode)
8370 | nonzero_bits (XEXP (x, 2), mode));
8380 /* See the macro definition above. */
8381 #undef num_sign_bit_copies
8383 /* Return the number of bits at the high-order end of X that are known to
8384 be equal to the sign bit. X will be used in mode MODE; if MODE is
8385 VOIDmode, X will be used in its own mode. The returned value will always
8386 be between 1 and the number of bits in MODE. */
8389 num_sign_bit_copies (x, mode)
8391 enum machine_mode mode;
8393 enum rtx_code code = GET_CODE (x);
8394 unsigned int bitwidth;
8395 int num0, num1, result;
8396 unsigned HOST_WIDE_INT nonzero;
8399 /* If we weren't given a mode, use the mode of X. If the mode is still
8400 VOIDmode, we don't know anything. Likewise if one of the modes is
8403 if (mode == VOIDmode)
8404 mode = GET_MODE (x);
8406 if (mode == VOIDmode || FLOAT_MODE_P (mode) || FLOAT_MODE_P (GET_MODE (x)))
8409 bitwidth = GET_MODE_BITSIZE (mode);
8411 /* For a smaller object, just ignore the high bits. */
8412 if (bitwidth < GET_MODE_BITSIZE (GET_MODE (x)))
8414 num0 = num_sign_bit_copies (x, GET_MODE (x));
8416 num0 - (int) (GET_MODE_BITSIZE (GET_MODE (x)) - bitwidth));
8419 if (GET_MODE (x) != VOIDmode && bitwidth > GET_MODE_BITSIZE (GET_MODE (x)))
8421 #ifndef WORD_REGISTER_OPERATIONS
8422 /* If this machine does not do all register operations on the entire
8423 register and MODE is wider than the mode of X, we can say nothing
8424 at all about the high-order bits. */
8427 /* Likewise on machines that do, if the mode of the object is smaller
8428 than a word and loads of that size don't sign extend, we can say
8429 nothing about the high order bits. */
8430 if (GET_MODE_BITSIZE (GET_MODE (x)) < BITS_PER_WORD
8431 #ifdef LOAD_EXTEND_OP
8432 && LOAD_EXTEND_OP (GET_MODE (x)) != SIGN_EXTEND
8443 #if defined(POINTERS_EXTEND_UNSIGNED) && !defined(HAVE_ptr_extend)
8444 /* If pointers extend signed and this is a pointer in Pmode, say that
8445 all the bits above ptr_mode are known to be sign bit copies. */
8446 if (! POINTERS_EXTEND_UNSIGNED && GET_MODE (x) == Pmode && mode == Pmode
8448 return GET_MODE_BITSIZE (Pmode) - GET_MODE_BITSIZE (ptr_mode) + 1;
8451 if (reg_last_set_value[REGNO (x)] != 0
8452 && reg_last_set_mode[REGNO (x)] == mode
8453 && (reg_last_set_label[REGNO (x)] == label_tick
8454 || (REGNO (x) >= FIRST_PSEUDO_REGISTER
8455 && REG_N_SETS (REGNO (x)) == 1
8456 && ! REGNO_REG_SET_P (BASIC_BLOCK (0)->global_live_at_start,
8458 && INSN_CUID (reg_last_set[REGNO (x)]) < subst_low_cuid)
8459 return reg_last_set_sign_bit_copies[REGNO (x)];
8461 tem = get_last_value (x);
8463 return num_sign_bit_copies (tem, mode);
8465 if (nonzero_sign_valid && reg_sign_bit_copies[REGNO (x)] != 0
8466 && GET_MODE_BITSIZE (GET_MODE (x)) == bitwidth)
8467 return reg_sign_bit_copies[REGNO (x)];
8471 #ifdef LOAD_EXTEND_OP
8472 /* Some RISC machines sign-extend all loads of smaller than a word. */
8473 if (LOAD_EXTEND_OP (GET_MODE (x)) == SIGN_EXTEND)
8474 return MAX (1, ((int) bitwidth
8475 - (int) GET_MODE_BITSIZE (GET_MODE (x)) + 1));
8480 /* If the constant is negative, take its 1's complement and remask.
8481 Then see how many zero bits we have. */
8482 nonzero = INTVAL (x) & GET_MODE_MASK (mode);
8483 if (bitwidth <= HOST_BITS_PER_WIDE_INT
8484 && (nonzero & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0)
8485 nonzero = (~nonzero) & GET_MODE_MASK (mode);
8487 return (nonzero == 0 ? bitwidth : bitwidth - floor_log2 (nonzero) - 1);
8490 /* If this is a SUBREG for a promoted object that is sign-extended
8491 and we are looking at it in a wider mode, we know that at least the
8492 high-order bits are known to be sign bit copies. */
8494 if (SUBREG_PROMOTED_VAR_P (x) && ! SUBREG_PROMOTED_UNSIGNED_P (x))
8496 num0 = num_sign_bit_copies (SUBREG_REG (x), mode);
8497 return MAX ((int) bitwidth
8498 - (int) GET_MODE_BITSIZE (GET_MODE (x)) + 1,
8502 /* For a smaller object, just ignore the high bits. */
8503 if (bitwidth <= GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x))))
8505 num0 = num_sign_bit_copies (SUBREG_REG (x), VOIDmode);
8506 return MAX (1, (num0
8507 - (int) (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x)))
8511 #ifdef WORD_REGISTER_OPERATIONS
8512 #ifdef LOAD_EXTEND_OP
8513 /* For paradoxical SUBREGs on machines where all register operations
8514 affect the entire register, just look inside. Note that we are
8515 passing MODE to the recursive call, so the number of sign bit copies
8516 will remain relative to that mode, not the inner mode. */
8518 /* This works only if loads sign extend. Otherwise, if we get a
8519 reload for the inner part, it may be loaded from the stack, and
8520 then we lose all sign bit copies that existed before the store
8523 if ((GET_MODE_SIZE (GET_MODE (x))
8524 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
8525 && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (x))) == SIGN_EXTEND)
8526 return num_sign_bit_copies (SUBREG_REG (x), mode);
8532 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
8533 return MAX (1, (int) bitwidth - INTVAL (XEXP (x, 1)));
8537 return (bitwidth - GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
8538 + num_sign_bit_copies (XEXP (x, 0), VOIDmode));
8541 /* For a smaller object, just ignore the high bits. */
8542 num0 = num_sign_bit_copies (XEXP (x, 0), VOIDmode);
8543 return MAX (1, (num0 - (int) (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
8547 return num_sign_bit_copies (XEXP (x, 0), mode);
8549 case ROTATE: case ROTATERT:
8550 /* If we are rotating left by a number of bits less than the number
8551 of sign bit copies, we can just subtract that amount from the
8553 if (GET_CODE (XEXP (x, 1)) == CONST_INT
8554 && INTVAL (XEXP (x, 1)) >= 0
8555 && INTVAL (XEXP (x, 1)) < (int) bitwidth)
8557 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
8558 return MAX (1, num0 - (code == ROTATE ? INTVAL (XEXP (x, 1))
8559 : (int) bitwidth - INTVAL (XEXP (x, 1))));
8564 /* In general, this subtracts one sign bit copy. But if the value
8565 is known to be positive, the number of sign bit copies is the
8566 same as that of the input. Finally, if the input has just one bit
8567 that might be nonzero, all the bits are copies of the sign bit. */
8568 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
8569 if (bitwidth > HOST_BITS_PER_WIDE_INT)
8570 return num0 > 1 ? num0 - 1 : 1;
8572 nonzero = nonzero_bits (XEXP (x, 0), mode);
8577 && (((HOST_WIDE_INT) 1 << (bitwidth - 1)) & nonzero))
8582 case IOR: case AND: case XOR:
8583 case SMIN: case SMAX: case UMIN: case UMAX:
8584 /* Logical operations will preserve the number of sign-bit copies.
8585 MIN and MAX operations always return one of the operands. */
8586 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
8587 num1 = num_sign_bit_copies (XEXP (x, 1), mode);
8588 return MIN (num0, num1);
8590 case PLUS: case MINUS:
8591 /* For addition and subtraction, we can have a 1-bit carry. However,
8592 if we are subtracting 1 from a positive number, there will not
8593 be such a carry. Furthermore, if the positive number is known to
8594 be 0 or 1, we know the result is either -1 or 0. */
8596 if (code == PLUS && XEXP (x, 1) == constm1_rtx
8597 && bitwidth <= HOST_BITS_PER_WIDE_INT)
8599 nonzero = nonzero_bits (XEXP (x, 0), mode);
8600 if ((((HOST_WIDE_INT) 1 << (bitwidth - 1)) & nonzero) == 0)
8601 return (nonzero == 1 || nonzero == 0 ? bitwidth
8602 : bitwidth - floor_log2 (nonzero) - 1);
8605 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
8606 num1 = num_sign_bit_copies (XEXP (x, 1), mode);
8607 result = MAX (1, MIN (num0, num1) - 1);
8609 #ifdef POINTERS_EXTEND_UNSIGNED
8610 /* If pointers extend signed and this is an addition or subtraction
8611 to a pointer in Pmode, all the bits above ptr_mode are known to be
8613 if (! POINTERS_EXTEND_UNSIGNED && GET_MODE (x) == Pmode
8614 && (code == PLUS || code == MINUS)
8615 && GET_CODE (XEXP (x, 0)) == REG && REG_POINTER (XEXP (x, 0)))
8616 result = MAX ((int) (GET_MODE_BITSIZE (Pmode)
8617 - GET_MODE_BITSIZE (ptr_mode) + 1),
8623 /* The number of bits of the product is the sum of the number of
8624 bits of both terms. However, unless one of the terms if known
8625 to be positive, we must allow for an additional bit since negating
8626 a negative number can remove one sign bit copy. */
8628 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
8629 num1 = num_sign_bit_copies (XEXP (x, 1), mode);
8631 result = bitwidth - (bitwidth - num0) - (bitwidth - num1);
8633 && (bitwidth > HOST_BITS_PER_WIDE_INT
8634 || (((nonzero_bits (XEXP (x, 0), mode)
8635 & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0)
8636 && ((nonzero_bits (XEXP (x, 1), mode)
8637 & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0))))
8640 return MAX (1, result);
8643 /* The result must be <= the first operand. If the first operand
8644 has the high bit set, we know nothing about the number of sign
8646 if (bitwidth > HOST_BITS_PER_WIDE_INT)
8648 else if ((nonzero_bits (XEXP (x, 0), mode)
8649 & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0)
8652 return num_sign_bit_copies (XEXP (x, 0), mode);
8655 /* The result must be <= the second operand. */
8656 return num_sign_bit_copies (XEXP (x, 1), mode);
8659 /* Similar to unsigned division, except that we have to worry about
8660 the case where the divisor is negative, in which case we have
8662 result = num_sign_bit_copies (XEXP (x, 0), mode);
8664 && (bitwidth > HOST_BITS_PER_WIDE_INT
8665 || (nonzero_bits (XEXP (x, 1), mode)
8666 & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0))
8672 result = num_sign_bit_copies (XEXP (x, 1), mode);
8674 && (bitwidth > HOST_BITS_PER_WIDE_INT
8675 || (nonzero_bits (XEXP (x, 1), mode)
8676 & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0))
8682 /* Shifts by a constant add to the number of bits equal to the
8684 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
8685 if (GET_CODE (XEXP (x, 1)) == CONST_INT
8686 && INTVAL (XEXP (x, 1)) > 0)
8687 num0 = MIN ((int) bitwidth, num0 + INTVAL (XEXP (x, 1)));
8692 /* Left shifts destroy copies. */
8693 if (GET_CODE (XEXP (x, 1)) != CONST_INT
8694 || INTVAL (XEXP (x, 1)) < 0
8695 || INTVAL (XEXP (x, 1)) >= (int) bitwidth)
8698 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
8699 return MAX (1, num0 - INTVAL (XEXP (x, 1)));
8702 num0 = num_sign_bit_copies (XEXP (x, 1), mode);
8703 num1 = num_sign_bit_copies (XEXP (x, 2), mode);
8704 return MIN (num0, num1);
8706 case EQ: case NE: case GE: case GT: case LE: case LT:
8707 case UNEQ: case LTGT: case UNGE: case UNGT: case UNLE: case UNLT:
8708 case GEU: case GTU: case LEU: case LTU:
8709 case UNORDERED: case ORDERED:
8710 /* If the constant is negative, take its 1's complement and remask.
8711 Then see how many zero bits we have. */
8712 nonzero = STORE_FLAG_VALUE;
8713 if (bitwidth <= HOST_BITS_PER_WIDE_INT
8714 && (nonzero & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0)
8715 nonzero = (~nonzero) & GET_MODE_MASK (mode);
8717 return (nonzero == 0 ? bitwidth : bitwidth - floor_log2 (nonzero) - 1);
8724 /* If we haven't been able to figure it out by one of the above rules,
8725 see if some of the high-order bits are known to be zero. If so,
8726 count those bits and return one less than that amount. If we can't
8727 safely compute the mask for this mode, always return BITWIDTH. */
8729 if (bitwidth > HOST_BITS_PER_WIDE_INT)
8732 nonzero = nonzero_bits (x, mode);
8733 return (nonzero & ((HOST_WIDE_INT) 1 << (bitwidth - 1))
8734 ? 1 : bitwidth - floor_log2 (nonzero) - 1);
8737 /* Return the number of "extended" bits there are in X, when interpreted
8738 as a quantity in MODE whose signedness is indicated by UNSIGNEDP. For
8739 unsigned quantities, this is the number of high-order zero bits.
8740 For signed quantities, this is the number of copies of the sign bit
8741 minus 1. In both case, this function returns the number of "spare"
8742 bits. For example, if two quantities for which this function returns
8743 at least 1 are added, the addition is known not to overflow.
8745 This function will always return 0 unless called during combine, which
8746 implies that it must be called from a define_split. */
8749 extended_count (x, mode, unsignedp)
8751 enum machine_mode mode;
8754 if (nonzero_sign_valid == 0)
8758 ? (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
8759 ? (GET_MODE_BITSIZE (mode) - 1
8760 - floor_log2 (nonzero_bits (x, mode)))
8762 : num_sign_bit_copies (x, mode) - 1);
8765 /* This function is called from `simplify_shift_const' to merge two
8766 outer operations. Specifically, we have already found that we need
8767 to perform operation *POP0 with constant *PCONST0 at the outermost
8768 position. We would now like to also perform OP1 with constant CONST1
8769 (with *POP0 being done last).
8771 Return 1 if we can do the operation and update *POP0 and *PCONST0 with
8772 the resulting operation. *PCOMP_P is set to 1 if we would need to
8773 complement the innermost operand, otherwise it is unchanged.
8775 MODE is the mode in which the operation will be done. No bits outside
8776 the width of this mode matter. It is assumed that the width of this mode
8777 is smaller than or equal to HOST_BITS_PER_WIDE_INT.
8779 If *POP0 or OP1 are NIL, it means no operation is required. Only NEG, PLUS,
8780 IOR, XOR, and AND are supported. We may set *POP0 to SET if the proper
8781 result is simply *PCONST0.
8783 If the resulting operation cannot be expressed as one operation, we
8784 return 0 and do not change *POP0, *PCONST0, and *PCOMP_P. */
8787 merge_outer_ops (pop0, pconst0, op1, const1, mode, pcomp_p)
8788 enum rtx_code *pop0;
8789 HOST_WIDE_INT *pconst0;
8791 HOST_WIDE_INT const1;
8792 enum machine_mode mode;
8795 enum rtx_code op0 = *pop0;
8796 HOST_WIDE_INT const0 = *pconst0;
8798 const0 &= GET_MODE_MASK (mode);
8799 const1 &= GET_MODE_MASK (mode);
8801 /* If OP0 is an AND, clear unimportant bits in CONST1. */
8805 /* If OP0 or OP1 is NIL, this is easy. Similarly if they are the same or
8808 if (op1 == NIL || op0 == SET)
8811 else if (op0 == NIL)
8812 op0 = op1, const0 = const1;
8814 else if (op0 == op1)
8838 /* Otherwise, if either is a PLUS or NEG, we can't do anything. */
8839 else if (op0 == PLUS || op1 == PLUS || op0 == NEG || op1 == NEG)
8842 /* If the two constants aren't the same, we can't do anything. The
8843 remaining six cases can all be done. */
8844 else if (const0 != const1)
8852 /* (a & b) | b == b */
8854 else /* op1 == XOR */
8855 /* (a ^ b) | b == a | b */
8861 /* (a & b) ^ b == (~a) & b */
8862 op0 = AND, *pcomp_p = 1;
8863 else /* op1 == IOR */
8864 /* (a | b) ^ b == a & ~b */
8865 op0 = AND, *pconst0 = ~const0;
8870 /* (a | b) & b == b */
8872 else /* op1 == XOR */
8873 /* (a ^ b) & b) == (~a) & b */
8880 /* Check for NO-OP cases. */
8881 const0 &= GET_MODE_MASK (mode);
8883 && (op0 == IOR || op0 == XOR || op0 == PLUS))
8885 else if (const0 == 0 && op0 == AND)
8887 else if ((unsigned HOST_WIDE_INT) const0 == GET_MODE_MASK (mode)
8891 /* ??? Slightly redundant with the above mask, but not entirely.
8892 Moving this above means we'd have to sign-extend the mode mask
8893 for the final test. */
8894 const0 = trunc_int_for_mode (const0, mode);
8902 /* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift.
8903 The result of the shift is RESULT_MODE. X, if non-zero, is an expression
8904 that we started with.
8906 The shift is normally computed in the widest mode we find in VAROP, as
8907 long as it isn't a different number of words than RESULT_MODE. Exceptions
8908 are ASHIFTRT and ROTATE, which are always done in their original mode, */
8911 simplify_shift_const (x, code, result_mode, varop, orig_count)
8914 enum machine_mode result_mode;
8918 enum rtx_code orig_code = code;
8921 enum machine_mode mode = result_mode;
8922 enum machine_mode shift_mode, tmode;
8923 unsigned int mode_words
8924 = (GET_MODE_SIZE (mode) + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD;
8925 /* We form (outer_op (code varop count) (outer_const)). */
8926 enum rtx_code outer_op = NIL;
8927 HOST_WIDE_INT outer_const = 0;
8929 int complement_p = 0;
8932 /* Make sure and truncate the "natural" shift on the way in. We don't
8933 want to do this inside the loop as it makes it more difficult to
8935 #ifdef SHIFT_COUNT_TRUNCATED
8936 if (SHIFT_COUNT_TRUNCATED)
8937 orig_count &= GET_MODE_BITSIZE (mode) - 1;
8940 /* If we were given an invalid count, don't do anything except exactly
8941 what was requested. */
8943 if (orig_count < 0 || orig_count >= (int) GET_MODE_BITSIZE (mode))
8948 return gen_rtx_fmt_ee (code, mode, varop, GEN_INT (orig_count));
8953 /* Unless one of the branches of the `if' in this loop does a `continue',
8954 we will `break' the loop after the `if'. */
8958 /* If we have an operand of (clobber (const_int 0)), just return that
8960 if (GET_CODE (varop) == CLOBBER)
8963 /* If we discovered we had to complement VAROP, leave. Making a NOT
8964 here would cause an infinite loop. */
8968 /* Convert ROTATERT to ROTATE. */
8969 if (code == ROTATERT)
8970 code = ROTATE, count = GET_MODE_BITSIZE (result_mode) - count;
8972 /* We need to determine what mode we will do the shift in. If the
8973 shift is a right shift or a ROTATE, we must always do it in the mode
8974 it was originally done in. Otherwise, we can do it in MODE, the
8975 widest mode encountered. */
8977 = (code == ASHIFTRT || code == LSHIFTRT || code == ROTATE
8978 ? result_mode : mode);
8980 /* Handle cases where the count is greater than the size of the mode
8981 minus 1. For ASHIFT, use the size minus one as the count (this can
8982 occur when simplifying (lshiftrt (ashiftrt ..))). For rotates,
8983 take the count modulo the size. For other shifts, the result is
8986 Since these shifts are being produced by the compiler by combining
8987 multiple operations, each of which are defined, we know what the
8988 result is supposed to be. */
8990 if (count > GET_MODE_BITSIZE (shift_mode) - 1)
8992 if (code == ASHIFTRT)
8993 count = GET_MODE_BITSIZE (shift_mode) - 1;
8994 else if (code == ROTATE || code == ROTATERT)
8995 count %= GET_MODE_BITSIZE (shift_mode);
8998 /* We can't simply return zero because there may be an
9006 /* An arithmetic right shift of a quantity known to be -1 or 0
9008 if (code == ASHIFTRT
9009 && (num_sign_bit_copies (varop, shift_mode)
9010 == GET_MODE_BITSIZE (shift_mode)))
9016 /* If we are doing an arithmetic right shift and discarding all but
9017 the sign bit copies, this is equivalent to doing a shift by the
9018 bitsize minus one. Convert it into that shift because it will often
9019 allow other simplifications. */
9021 if (code == ASHIFTRT
9022 && (count + num_sign_bit_copies (varop, shift_mode)
9023 >= GET_MODE_BITSIZE (shift_mode)))
9024 count = GET_MODE_BITSIZE (shift_mode) - 1;
9026 /* We simplify the tests below and elsewhere by converting
9027 ASHIFTRT to LSHIFTRT if we know the sign bit is clear.
9028 `make_compound_operation' will convert it to a ASHIFTRT for
9029 those machines (such as VAX) that don't have a LSHIFTRT. */
9030 if (GET_MODE_BITSIZE (shift_mode) <= HOST_BITS_PER_WIDE_INT
9032 && ((nonzero_bits (varop, shift_mode)
9033 & ((HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (shift_mode) - 1)))
9037 switch (GET_CODE (varop))
9043 new = expand_compound_operation (varop);
9052 /* If we have (xshiftrt (mem ...) C) and C is MODE_WIDTH
9053 minus the width of a smaller mode, we can do this with a
9054 SIGN_EXTEND or ZERO_EXTEND from the narrower memory location. */
9055 if ((code == ASHIFTRT || code == LSHIFTRT)
9056 && ! mode_dependent_address_p (XEXP (varop, 0))
9057 && ! MEM_VOLATILE_P (varop)
9058 && (tmode = mode_for_size (GET_MODE_BITSIZE (mode) - count,
9059 MODE_INT, 1)) != BLKmode)
9061 new = adjust_address_nv (varop, tmode,
9062 BYTES_BIG_ENDIAN ? 0
9063 : count / BITS_PER_UNIT);
9065 varop = gen_rtx_fmt_e (code == ASHIFTRT ? SIGN_EXTEND
9066 : ZERO_EXTEND, mode, new);
9073 /* Similar to the case above, except that we can only do this if
9074 the resulting mode is the same as that of the underlying
9075 MEM and adjust the address depending on the *bits* endianness
9076 because of the way that bit-field extract insns are defined. */
9077 if ((code == ASHIFTRT || code == LSHIFTRT)
9078 && (tmode = mode_for_size (GET_MODE_BITSIZE (mode) - count,
9079 MODE_INT, 1)) != BLKmode
9080 && tmode == GET_MODE (XEXP (varop, 0)))
9082 if (BITS_BIG_ENDIAN)
9083 new = XEXP (varop, 0);
9086 new = copy_rtx (XEXP (varop, 0));
9087 SUBST (XEXP (new, 0),
9088 plus_constant (XEXP (new, 0),
9089 count / BITS_PER_UNIT));
9092 varop = gen_rtx_fmt_e (code == ASHIFTRT ? SIGN_EXTEND
9093 : ZERO_EXTEND, mode, new);
9100 /* If VAROP is a SUBREG, strip it as long as the inner operand has
9101 the same number of words as what we've seen so far. Then store
9102 the widest mode in MODE. */
9103 if (subreg_lowpart_p (varop)
9104 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop)))
9105 > GET_MODE_SIZE (GET_MODE (varop)))
9106 && (((GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop)))
9107 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
9110 varop = SUBREG_REG (varop);
9111 if (GET_MODE_SIZE (GET_MODE (varop)) > GET_MODE_SIZE (mode))
9112 mode = GET_MODE (varop);
9118 /* Some machines use MULT instead of ASHIFT because MULT
9119 is cheaper. But it is still better on those machines to
9120 merge two shifts into one. */
9121 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
9122 && exact_log2 (INTVAL (XEXP (varop, 1))) >= 0)
9125 = gen_binary (ASHIFT, GET_MODE (varop), XEXP (varop, 0),
9126 GEN_INT (exact_log2 (INTVAL (XEXP (varop, 1)))));
9132 /* Similar, for when divides are cheaper. */
9133 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
9134 && exact_log2 (INTVAL (XEXP (varop, 1))) >= 0)
9137 = gen_binary (LSHIFTRT, GET_MODE (varop), XEXP (varop, 0),
9138 GEN_INT (exact_log2 (INTVAL (XEXP (varop, 1)))));
9144 /* If we are extracting just the sign bit of an arithmetic
9145 right shift, that shift is not needed. However, the sign
9146 bit of a wider mode may be different from what would be
9147 interpreted as the sign bit in a narrower mode, so, if
9148 the result is narrower, don't discard the shift. */
9149 if (code == LSHIFTRT && count == GET_MODE_BITSIZE (result_mode) - 1
9150 && (GET_MODE_BITSIZE (result_mode)
9151 >= GET_MODE_BITSIZE (GET_MODE (varop))))
9153 varop = XEXP (varop, 0);
9157 /* ... fall through ... */
9162 /* Here we have two nested shifts. The result is usually the
9163 AND of a new shift with a mask. We compute the result below. */
9164 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
9165 && INTVAL (XEXP (varop, 1)) >= 0
9166 && INTVAL (XEXP (varop, 1)) < GET_MODE_BITSIZE (GET_MODE (varop))
9167 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
9168 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
9170 enum rtx_code first_code = GET_CODE (varop);
9171 unsigned int first_count = INTVAL (XEXP (varop, 1));
9172 unsigned HOST_WIDE_INT mask;
9175 /* We have one common special case. We can't do any merging if
9176 the inner code is an ASHIFTRT of a smaller mode. However, if
9177 we have (ashift:M1 (subreg:M1 (ashiftrt:M2 FOO C1) 0) C2)
9178 with C2 == GET_MODE_BITSIZE (M1) - GET_MODE_BITSIZE (M2),
9179 we can convert it to
9180 (ashiftrt:M1 (ashift:M1 (and:M1 (subreg:M1 FOO 0 C2) C3) C1).
9181 This simplifies certain SIGN_EXTEND operations. */
9182 if (code == ASHIFT && first_code == ASHIFTRT
9183 && (GET_MODE_BITSIZE (result_mode)
9184 - GET_MODE_BITSIZE (GET_MODE (varop))) == count)
9186 /* C3 has the low-order C1 bits zero. */
9188 mask = (GET_MODE_MASK (mode)
9189 & ~(((HOST_WIDE_INT) 1 << first_count) - 1));
9191 varop = simplify_and_const_int (NULL_RTX, result_mode,
9192 XEXP (varop, 0), mask);
9193 varop = simplify_shift_const (NULL_RTX, ASHIFT, result_mode,
9195 count = first_count;
9200 /* If this was (ashiftrt (ashift foo C1) C2) and FOO has more
9201 than C1 high-order bits equal to the sign bit, we can convert
9202 this to either an ASHIFT or a ASHIFTRT depending on the
9205 We cannot do this if VAROP's mode is not SHIFT_MODE. */
9207 if (code == ASHIFTRT && first_code == ASHIFT
9208 && GET_MODE (varop) == shift_mode
9209 && (num_sign_bit_copies (XEXP (varop, 0), shift_mode)
9212 varop = XEXP (varop, 0);
9214 signed_count = count - first_count;
9215 if (signed_count < 0)
9216 count = -signed_count, code = ASHIFT;
9218 count = signed_count;
9223 /* There are some cases we can't do. If CODE is ASHIFTRT,
9224 we can only do this if FIRST_CODE is also ASHIFTRT.
9226 We can't do the case when CODE is ROTATE and FIRST_CODE is
9229 If the mode of this shift is not the mode of the outer shift,
9230 we can't do this if either shift is a right shift or ROTATE.
9232 Finally, we can't do any of these if the mode is too wide
9233 unless the codes are the same.
9235 Handle the case where the shift codes are the same
9238 if (code == first_code)
9240 if (GET_MODE (varop) != result_mode
9241 && (code == ASHIFTRT || code == LSHIFTRT
9245 count += first_count;
9246 varop = XEXP (varop, 0);
9250 if (code == ASHIFTRT
9251 || (code == ROTATE && first_code == ASHIFTRT)
9252 || GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT
9253 || (GET_MODE (varop) != result_mode
9254 && (first_code == ASHIFTRT || first_code == LSHIFTRT
9255 || first_code == ROTATE
9256 || code == ROTATE)))
9259 /* To compute the mask to apply after the shift, shift the
9260 nonzero bits of the inner shift the same way the
9261 outer shift will. */
9263 mask_rtx = GEN_INT (nonzero_bits (varop, GET_MODE (varop)));
9266 = simplify_binary_operation (code, result_mode, mask_rtx,
9269 /* Give up if we can't compute an outer operation to use. */
9271 || GET_CODE (mask_rtx) != CONST_INT
9272 || ! merge_outer_ops (&outer_op, &outer_const, AND,
9274 result_mode, &complement_p))
9277 /* If the shifts are in the same direction, we add the
9278 counts. Otherwise, we subtract them. */
9279 signed_count = count;
9280 if ((code == ASHIFTRT || code == LSHIFTRT)
9281 == (first_code == ASHIFTRT || first_code == LSHIFTRT))
9282 signed_count += first_count;
9284 signed_count -= first_count;
9286 /* If COUNT is positive, the new shift is usually CODE,
9287 except for the two exceptions below, in which case it is
9288 FIRST_CODE. If the count is negative, FIRST_CODE should
9290 if (signed_count > 0
9291 && ((first_code == ROTATE && code == ASHIFT)
9292 || (first_code == ASHIFTRT && code == LSHIFTRT)))
9293 code = first_code, count = signed_count;
9294 else if (signed_count < 0)
9295 code = first_code, count = -signed_count;
9297 count = signed_count;
9299 varop = XEXP (varop, 0);
9303 /* If we have (A << B << C) for any shift, we can convert this to
9304 (A << C << B). This wins if A is a constant. Only try this if
9305 B is not a constant. */
9307 else if (GET_CODE (varop) == code
9308 && GET_CODE (XEXP (varop, 1)) != CONST_INT
9310 = simplify_binary_operation (code, mode,
9314 varop = gen_rtx_fmt_ee (code, mode, new, XEXP (varop, 1));
9321 /* Make this fit the case below. */
9322 varop = gen_rtx_XOR (mode, XEXP (varop, 0),
9323 GEN_INT (GET_MODE_MASK (mode)));
9329 /* If we have (xshiftrt (ior (plus X (const_int -1)) X) C)
9330 with C the size of VAROP - 1 and the shift is logical if
9331 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
9332 we have an (le X 0) operation. If we have an arithmetic shift
9333 and STORE_FLAG_VALUE is 1 or we have a logical shift with
9334 STORE_FLAG_VALUE of -1, we have a (neg (le X 0)) operation. */
9336 if (GET_CODE (varop) == IOR && GET_CODE (XEXP (varop, 0)) == PLUS
9337 && XEXP (XEXP (varop, 0), 1) == constm1_rtx
9338 && (STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
9339 && (code == LSHIFTRT || code == ASHIFTRT)
9340 && count == GET_MODE_BITSIZE (GET_MODE (varop)) - 1
9341 && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
9344 varop = gen_rtx_LE (GET_MODE (varop), XEXP (varop, 1),
9347 if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
9348 varop = gen_rtx_NEG (GET_MODE (varop), varop);
9353 /* If we have (shift (logical)), move the logical to the outside
9354 to allow it to possibly combine with another logical and the
9355 shift to combine with another shift. This also canonicalizes to
9356 what a ZERO_EXTRACT looks like. Also, some machines have
9357 (and (shift)) insns. */
9359 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
9360 && (new = simplify_binary_operation (code, result_mode,
9362 GEN_INT (count))) != 0
9363 && GET_CODE (new) == CONST_INT
9364 && merge_outer_ops (&outer_op, &outer_const, GET_CODE (varop),
9365 INTVAL (new), result_mode, &complement_p))
9367 varop = XEXP (varop, 0);
9371 /* If we can't do that, try to simplify the shift in each arm of the
9372 logical expression, make a new logical expression, and apply
9373 the inverse distributive law. */
9375 rtx lhs = simplify_shift_const (NULL_RTX, code, shift_mode,
9376 XEXP (varop, 0), count);
9377 rtx rhs = simplify_shift_const (NULL_RTX, code, shift_mode,
9378 XEXP (varop, 1), count);
9380 varop = gen_binary (GET_CODE (varop), shift_mode, lhs, rhs);
9381 varop = apply_distributive_law (varop);
9388 /* convert (lshiftrt (eq FOO 0) C) to (xor FOO 1) if STORE_FLAG_VALUE
9389 says that the sign bit can be tested, FOO has mode MODE, C is
9390 GET_MODE_BITSIZE (MODE) - 1, and FOO has only its low-order bit
9391 that may be nonzero. */
9392 if (code == LSHIFTRT
9393 && XEXP (varop, 1) == const0_rtx
9394 && GET_MODE (XEXP (varop, 0)) == result_mode
9395 && count == GET_MODE_BITSIZE (result_mode) - 1
9396 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
9397 && ((STORE_FLAG_VALUE
9398 & ((HOST_WIDE_INT) 1
9399 < (GET_MODE_BITSIZE (result_mode) - 1))))
9400 && nonzero_bits (XEXP (varop, 0), result_mode) == 1
9401 && merge_outer_ops (&outer_op, &outer_const, XOR,
9402 (HOST_WIDE_INT) 1, result_mode,
9405 varop = XEXP (varop, 0);
9412 /* (lshiftrt (neg A) C) where A is either 0 or 1 and C is one less
9413 than the number of bits in the mode is equivalent to A. */
9414 if (code == LSHIFTRT && count == GET_MODE_BITSIZE (result_mode) - 1
9415 && nonzero_bits (XEXP (varop, 0), result_mode) == 1)
9417 varop = XEXP (varop, 0);
9422 /* NEG commutes with ASHIFT since it is multiplication. Move the
9423 NEG outside to allow shifts to combine. */
9425 && merge_outer_ops (&outer_op, &outer_const, NEG,
9426 (HOST_WIDE_INT) 0, result_mode,
9429 varop = XEXP (varop, 0);
9435 /* (lshiftrt (plus A -1) C) where A is either 0 or 1 and C
9436 is one less than the number of bits in the mode is
9437 equivalent to (xor A 1). */
9438 if (code == LSHIFTRT && count == GET_MODE_BITSIZE (result_mode) - 1
9439 && XEXP (varop, 1) == constm1_rtx
9440 && nonzero_bits (XEXP (varop, 0), result_mode) == 1
9441 && merge_outer_ops (&outer_op, &outer_const, XOR,
9442 (HOST_WIDE_INT) 1, result_mode,
9446 varop = XEXP (varop, 0);
9450 /* If we have (xshiftrt (plus FOO BAR) C), and the only bits
9451 that might be nonzero in BAR are those being shifted out and those
9452 bits are known zero in FOO, we can replace the PLUS with FOO.
9453 Similarly in the other operand order. This code occurs when
9454 we are computing the size of a variable-size array. */
9456 if ((code == ASHIFTRT || code == LSHIFTRT)
9457 && count < HOST_BITS_PER_WIDE_INT
9458 && nonzero_bits (XEXP (varop, 1), result_mode) >> count == 0
9459 && (nonzero_bits (XEXP (varop, 1), result_mode)
9460 & nonzero_bits (XEXP (varop, 0), result_mode)) == 0)
9462 varop = XEXP (varop, 0);
9465 else if ((code == ASHIFTRT || code == LSHIFTRT)
9466 && count < HOST_BITS_PER_WIDE_INT
9467 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
9468 && 0 == (nonzero_bits (XEXP (varop, 0), result_mode)
9470 && 0 == (nonzero_bits (XEXP (varop, 0), result_mode)
9471 & nonzero_bits (XEXP (varop, 1),
9474 varop = XEXP (varop, 1);
9478 /* (ashift (plus foo C) N) is (plus (ashift foo N) C'). */
9480 && GET_CODE (XEXP (varop, 1)) == CONST_INT
9481 && (new = simplify_binary_operation (ASHIFT, result_mode,
9483 GEN_INT (count))) != 0
9484 && GET_CODE (new) == CONST_INT
9485 && merge_outer_ops (&outer_op, &outer_const, PLUS,
9486 INTVAL (new), result_mode, &complement_p))
9488 varop = XEXP (varop, 0);
9494 /* If we have (xshiftrt (minus (ashiftrt X C)) X) C)
9495 with C the size of VAROP - 1 and the shift is logical if
9496 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
9497 we have a (gt X 0) operation. If the shift is arithmetic with
9498 STORE_FLAG_VALUE of 1 or logical with STORE_FLAG_VALUE == -1,
9499 we have a (neg (gt X 0)) operation. */
9501 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
9502 && GET_CODE (XEXP (varop, 0)) == ASHIFTRT
9503 && count == GET_MODE_BITSIZE (GET_MODE (varop)) - 1
9504 && (code == LSHIFTRT || code == ASHIFTRT)
9505 && GET_CODE (XEXP (XEXP (varop, 0), 1)) == CONST_INT
9506 && INTVAL (XEXP (XEXP (varop, 0), 1)) == count
9507 && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
9510 varop = gen_rtx_GT (GET_MODE (varop), XEXP (varop, 1),
9513 if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
9514 varop = gen_rtx_NEG (GET_MODE (varop), varop);
9521 /* Change (lshiftrt (truncate (lshiftrt))) to (truncate (lshiftrt))
9522 if the truncate does not affect the value. */
9523 if (code == LSHIFTRT
9524 && GET_CODE (XEXP (varop, 0)) == LSHIFTRT
9525 && GET_CODE (XEXP (XEXP (varop, 0), 1)) == CONST_INT
9526 && (INTVAL (XEXP (XEXP (varop, 0), 1))
9527 >= (GET_MODE_BITSIZE (GET_MODE (XEXP (varop, 0)))
9528 - GET_MODE_BITSIZE (GET_MODE (varop)))))
9530 rtx varop_inner = XEXP (varop, 0);
9533 = gen_rtx_LSHIFTRT (GET_MODE (varop_inner),
9534 XEXP (varop_inner, 0),
9536 (count + INTVAL (XEXP (varop_inner, 1))));
9537 varop = gen_rtx_TRUNCATE (GET_MODE (varop), varop_inner);
9550 /* We need to determine what mode to do the shift in. If the shift is
9551 a right shift or ROTATE, we must always do it in the mode it was
9552 originally done in. Otherwise, we can do it in MODE, the widest mode
9553 encountered. The code we care about is that of the shift that will
9554 actually be done, not the shift that was originally requested. */
9556 = (code == ASHIFTRT || code == LSHIFTRT || code == ROTATE
9557 ? result_mode : mode);
9559 /* We have now finished analyzing the shift. The result should be
9560 a shift of type CODE with SHIFT_MODE shifting VAROP COUNT places. If
9561 OUTER_OP is non-NIL, it is an operation that needs to be applied
9562 to the result of the shift. OUTER_CONST is the relevant constant,
9563 but we must turn off all bits turned off in the shift.
9565 If we were passed a value for X, see if we can use any pieces of
9566 it. If not, make new rtx. */
9568 if (x && GET_RTX_CLASS (GET_CODE (x)) == '2'
9569 && GET_CODE (XEXP (x, 1)) == CONST_INT
9570 && INTVAL (XEXP (x, 1)) == count)
9571 const_rtx = XEXP (x, 1);
9573 const_rtx = GEN_INT (count);
9575 if (x && GET_CODE (XEXP (x, 0)) == SUBREG
9576 && GET_MODE (XEXP (x, 0)) == shift_mode
9577 && SUBREG_REG (XEXP (x, 0)) == varop)
9578 varop = XEXP (x, 0);
9579 else if (GET_MODE (varop) != shift_mode)
9580 varop = gen_lowpart_for_combine (shift_mode, varop);
9582 /* If we can't make the SUBREG, try to return what we were given. */
9583 if (GET_CODE (varop) == CLOBBER)
9584 return x ? x : varop;
9586 new = simplify_binary_operation (code, shift_mode, varop, const_rtx);
9590 x = gen_rtx_fmt_ee (code, shift_mode, varop, const_rtx);
9592 /* If we have an outer operation and we just made a shift, it is
9593 possible that we could have simplified the shift were it not
9594 for the outer operation. So try to do the simplification
9597 if (outer_op != NIL && GET_CODE (x) == code
9598 && GET_CODE (XEXP (x, 1)) == CONST_INT)
9599 x = simplify_shift_const (x, code, shift_mode, XEXP (x, 0),
9600 INTVAL (XEXP (x, 1)));
9602 /* If we were doing a LSHIFTRT in a wider mode than it was originally,
9603 turn off all the bits that the shift would have turned off. */
9604 if (orig_code == LSHIFTRT && result_mode != shift_mode)
9605 x = simplify_and_const_int (NULL_RTX, shift_mode, x,
9606 GET_MODE_MASK (result_mode) >> orig_count);
9608 /* Do the remainder of the processing in RESULT_MODE. */
9609 x = gen_lowpart_for_combine (result_mode, x);
9611 /* If COMPLEMENT_P is set, we have to complement X before doing the outer
9614 x =simplify_gen_unary (NOT, result_mode, x, result_mode);
9616 if (outer_op != NIL)
9618 if (GET_MODE_BITSIZE (result_mode) < HOST_BITS_PER_WIDE_INT)
9619 outer_const = trunc_int_for_mode (outer_const, result_mode);
9621 if (outer_op == AND)
9622 x = simplify_and_const_int (NULL_RTX, result_mode, x, outer_const);
9623 else if (outer_op == SET)
9624 /* This means that we have determined that the result is
9625 equivalent to a constant. This should be rare. */
9626 x = GEN_INT (outer_const);
9627 else if (GET_RTX_CLASS (outer_op) == '1')
9628 x = simplify_gen_unary (outer_op, result_mode, x, result_mode);
9630 x = gen_binary (outer_op, result_mode, x, GEN_INT (outer_const));
9636 /* Like recog, but we receive the address of a pointer to a new pattern.
9637 We try to match the rtx that the pointer points to.
9638 If that fails, we may try to modify or replace the pattern,
9639 storing the replacement into the same pointer object.
9641 Modifications include deletion or addition of CLOBBERs.
9643 PNOTES is a pointer to a location where any REG_UNUSED notes added for
9644 the CLOBBERs are placed.
9646 The value is the final insn code from the pattern ultimately matched,
9650 recog_for_combine (pnewpat, insn, pnotes)
9656 int insn_code_number;
9657 int num_clobbers_to_add = 0;
9662 /* If PAT is a PARALLEL, check to see if it contains the CLOBBER
9663 we use to indicate that something didn't match. If we find such a
9664 thing, force rejection. */
9665 if (GET_CODE (pat) == PARALLEL)
9666 for (i = XVECLEN (pat, 0) - 1; i >= 0; i--)
9667 if (GET_CODE (XVECEXP (pat, 0, i)) == CLOBBER
9668 && XEXP (XVECEXP (pat, 0, i), 0) == const0_rtx)
9671 /* *pnewpat does not have to be actual PATTERN (insn), so make a dummy
9672 instruction for pattern recognition. */
9673 dummy_insn = shallow_copy_rtx (insn);
9674 PATTERN (dummy_insn) = pat;
9675 REG_NOTES (dummy_insn) = 0;
9677 insn_code_number = recog (pat, dummy_insn, &num_clobbers_to_add);
9679 /* If it isn't, there is the possibility that we previously had an insn
9680 that clobbered some register as a side effect, but the combined
9681 insn doesn't need to do that. So try once more without the clobbers
9682 unless this represents an ASM insn. */
9684 if (insn_code_number < 0 && ! check_asm_operands (pat)
9685 && GET_CODE (pat) == PARALLEL)
9689 for (pos = 0, i = 0; i < XVECLEN (pat, 0); i++)
9690 if (GET_CODE (XVECEXP (pat, 0, i)) != CLOBBER)
9693 SUBST (XVECEXP (pat, 0, pos), XVECEXP (pat, 0, i));
9697 SUBST_INT (XVECLEN (pat, 0), pos);
9700 pat = XVECEXP (pat, 0, 0);
9702 PATTERN (dummy_insn) = pat;
9703 insn_code_number = recog (pat, dummy_insn, &num_clobbers_to_add);
9706 /* Recognize all noop sets, these will be killed by followup pass. */
9707 if (insn_code_number < 0 && GET_CODE (pat) == SET && set_noop_p (pat))
9708 insn_code_number = NOOP_MOVE_INSN_CODE, num_clobbers_to_add = 0;
9710 /* If we had any clobbers to add, make a new pattern than contains
9711 them. Then check to make sure that all of them are dead. */
9712 if (num_clobbers_to_add)
9714 rtx newpat = gen_rtx_PARALLEL (VOIDmode,
9715 rtvec_alloc (GET_CODE (pat) == PARALLEL
9717 + num_clobbers_to_add)
9718 : num_clobbers_to_add + 1));
9720 if (GET_CODE (pat) == PARALLEL)
9721 for (i = 0; i < XVECLEN (pat, 0); i++)
9722 XVECEXP (newpat, 0, i) = XVECEXP (pat, 0, i);
9724 XVECEXP (newpat, 0, 0) = pat;
9726 add_clobbers (newpat, insn_code_number);
9728 for (i = XVECLEN (newpat, 0) - num_clobbers_to_add;
9729 i < XVECLEN (newpat, 0); i++)
9731 if (GET_CODE (XEXP (XVECEXP (newpat, 0, i), 0)) == REG
9732 && ! reg_dead_at_p (XEXP (XVECEXP (newpat, 0, i), 0), insn))
9734 notes = gen_rtx_EXPR_LIST (REG_UNUSED,
9735 XEXP (XVECEXP (newpat, 0, i), 0), notes);
9743 return insn_code_number;
9746 /* Like gen_lowpart but for use by combine. In combine it is not possible
9747 to create any new pseudoregs. However, it is safe to create
9748 invalid memory addresses, because combine will try to recognize
9749 them and all they will do is make the combine attempt fail.
9751 If for some reason this cannot do its job, an rtx
9752 (clobber (const_int 0)) is returned.
9753 An insn containing that will not be recognized. */
9758 gen_lowpart_for_combine (mode, x)
9759 enum machine_mode mode;
9764 if (GET_MODE (x) == mode)
9767 /* We can only support MODE being wider than a word if X is a
9768 constant integer or has a mode the same size. */
9770 if (GET_MODE_SIZE (mode) > UNITS_PER_WORD
9771 && ! ((GET_MODE (x) == VOIDmode
9772 && (GET_CODE (x) == CONST_INT
9773 || GET_CODE (x) == CONST_DOUBLE))
9774 || GET_MODE_SIZE (GET_MODE (x)) == GET_MODE_SIZE (mode)))
9775 return gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
9777 /* X might be a paradoxical (subreg (mem)). In that case, gen_lowpart
9778 won't know what to do. So we will strip off the SUBREG here and
9779 process normally. */
9780 if (GET_CODE (x) == SUBREG && GET_CODE (SUBREG_REG (x)) == MEM)
9783 if (GET_MODE (x) == mode)
9787 result = gen_lowpart_common (mode, x);
9788 #ifdef CLASS_CANNOT_CHANGE_MODE
9790 && GET_CODE (result) == SUBREG
9791 && GET_CODE (SUBREG_REG (result)) == REG
9792 && REGNO (SUBREG_REG (result)) >= FIRST_PSEUDO_REGISTER
9793 && CLASS_CANNOT_CHANGE_MODE_P (GET_MODE (result),
9794 GET_MODE (SUBREG_REG (result))))
9795 REG_CHANGES_MODE (REGNO (SUBREG_REG (result))) = 1;
9801 if (GET_CODE (x) == MEM)
9805 /* Refuse to work on a volatile memory ref or one with a mode-dependent
9807 if (MEM_VOLATILE_P (x) || mode_dependent_address_p (XEXP (x, 0)))
9808 return gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
9810 /* If we want to refer to something bigger than the original memref,
9811 generate a perverse subreg instead. That will force a reload
9812 of the original memref X. */
9813 if (GET_MODE_SIZE (GET_MODE (x)) < GET_MODE_SIZE (mode))
9814 return gen_rtx_SUBREG (mode, x, 0);
9816 if (WORDS_BIG_ENDIAN)
9817 offset = (MAX (GET_MODE_SIZE (GET_MODE (x)), UNITS_PER_WORD)
9818 - MAX (GET_MODE_SIZE (mode), UNITS_PER_WORD));
9820 if (BYTES_BIG_ENDIAN)
9822 /* Adjust the address so that the address-after-the-data is
9824 offset -= (MIN (UNITS_PER_WORD, GET_MODE_SIZE (mode))
9825 - MIN (UNITS_PER_WORD, GET_MODE_SIZE (GET_MODE (x))));
9828 return adjust_address_nv (x, mode, offset);
9831 /* If X is a comparison operator, rewrite it in a new mode. This
9832 probably won't match, but may allow further simplifications. */
9833 else if (GET_RTX_CLASS (GET_CODE (x)) == '<')
9834 return gen_rtx_fmt_ee (GET_CODE (x), mode, XEXP (x, 0), XEXP (x, 1));
9836 /* If we couldn't simplify X any other way, just enclose it in a
9837 SUBREG. Normally, this SUBREG won't match, but some patterns may
9838 include an explicit SUBREG or we may simplify it further in combine. */
9844 offset = subreg_lowpart_offset (mode, GET_MODE (x));
9845 res = simplify_gen_subreg (mode, x, GET_MODE (x), offset);
9848 return gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
9852 /* These routines make binary and unary operations by first seeing if they
9853 fold; if not, a new expression is allocated. */
9856 gen_binary (code, mode, op0, op1)
9858 enum machine_mode mode;
9864 if (GET_RTX_CLASS (code) == 'c'
9865 && swap_commutative_operands_p (op0, op1))
9866 tem = op0, op0 = op1, op1 = tem;
9868 if (GET_RTX_CLASS (code) == '<')
9870 enum machine_mode op_mode = GET_MODE (op0);
9872 /* Strip the COMPARE from (REL_OP (compare X Y) 0) to get
9873 just (REL_OP X Y). */
9874 if (GET_CODE (op0) == COMPARE && op1 == const0_rtx)
9876 op1 = XEXP (op0, 1);
9877 op0 = XEXP (op0, 0);
9878 op_mode = GET_MODE (op0);
9881 if (op_mode == VOIDmode)
9882 op_mode = GET_MODE (op1);
9883 result = simplify_relational_operation (code, op_mode, op0, op1);
9886 result = simplify_binary_operation (code, mode, op0, op1);
9891 /* Put complex operands first and constants second. */
9892 if (GET_RTX_CLASS (code) == 'c'
9893 && swap_commutative_operands_p (op0, op1))
9894 return gen_rtx_fmt_ee (code, mode, op1, op0);
9896 /* If we are turning off bits already known off in OP0, we need not do
9898 else if (code == AND && GET_CODE (op1) == CONST_INT
9899 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
9900 && (nonzero_bits (op0, mode) & ~INTVAL (op1)) == 0)
9903 return gen_rtx_fmt_ee (code, mode, op0, op1);
9906 /* Simplify a comparison between *POP0 and *POP1 where CODE is the
9907 comparison code that will be tested.
9909 The result is a possibly different comparison code to use. *POP0 and
9910 *POP1 may be updated.
9912 It is possible that we might detect that a comparison is either always
9913 true or always false. However, we do not perform general constant
9914 folding in combine, so this knowledge isn't useful. Such tautologies
9915 should have been detected earlier. Hence we ignore all such cases. */
9917 static enum rtx_code
9918 simplify_comparison (code, pop0, pop1)
9927 enum machine_mode mode, tmode;
9929 /* Try a few ways of applying the same transformation to both operands. */
9932 #ifndef WORD_REGISTER_OPERATIONS
9933 /* The test below this one won't handle SIGN_EXTENDs on these machines,
9934 so check specially. */
9935 if (code != GTU && code != GEU && code != LTU && code != LEU
9936 && GET_CODE (op0) == ASHIFTRT && GET_CODE (op1) == ASHIFTRT
9937 && GET_CODE (XEXP (op0, 0)) == ASHIFT
9938 && GET_CODE (XEXP (op1, 0)) == ASHIFT
9939 && GET_CODE (XEXP (XEXP (op0, 0), 0)) == SUBREG
9940 && GET_CODE (XEXP (XEXP (op1, 0), 0)) == SUBREG
9941 && (GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0)))
9942 == GET_MODE (SUBREG_REG (XEXP (XEXP (op1, 0), 0))))
9943 && GET_CODE (XEXP (op0, 1)) == CONST_INT
9944 && GET_CODE (XEXP (op1, 1)) == CONST_INT
9945 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
9946 && GET_CODE (XEXP (XEXP (op1, 0), 1)) == CONST_INT
9947 && INTVAL (XEXP (op0, 1)) == INTVAL (XEXP (op1, 1))
9948 && INTVAL (XEXP (op0, 1)) == INTVAL (XEXP (XEXP (op0, 0), 1))
9949 && INTVAL (XEXP (op0, 1)) == INTVAL (XEXP (XEXP (op1, 0), 1))
9950 && (INTVAL (XEXP (op0, 1))
9951 == (GET_MODE_BITSIZE (GET_MODE (op0))
9953 (GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0))))))))
9955 op0 = SUBREG_REG (XEXP (XEXP (op0, 0), 0));
9956 op1 = SUBREG_REG (XEXP (XEXP (op1, 0), 0));
9960 /* If both operands are the same constant shift, see if we can ignore the
9961 shift. We can if the shift is a rotate or if the bits shifted out of
9962 this shift are known to be zero for both inputs and if the type of
9963 comparison is compatible with the shift. */
9964 if (GET_CODE (op0) == GET_CODE (op1)
9965 && GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
9966 && ((GET_CODE (op0) == ROTATE && (code == NE || code == EQ))
9967 || ((GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFT)
9968 && (code != GT && code != LT && code != GE && code != LE))
9969 || (GET_CODE (op0) == ASHIFTRT
9970 && (code != GTU && code != LTU
9971 && code != GEU && code != LEU)))
9972 && GET_CODE (XEXP (op0, 1)) == CONST_INT
9973 && INTVAL (XEXP (op0, 1)) >= 0
9974 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT
9975 && XEXP (op0, 1) == XEXP (op1, 1))
9977 enum machine_mode mode = GET_MODE (op0);
9978 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
9979 int shift_count = INTVAL (XEXP (op0, 1));
9981 if (GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFTRT)
9982 mask &= (mask >> shift_count) << shift_count;
9983 else if (GET_CODE (op0) == ASHIFT)
9984 mask = (mask & (mask << shift_count)) >> shift_count;
9986 if ((nonzero_bits (XEXP (op0, 0), mode) & ~mask) == 0
9987 && (nonzero_bits (XEXP (op1, 0), mode) & ~mask) == 0)
9988 op0 = XEXP (op0, 0), op1 = XEXP (op1, 0);
9993 /* If both operands are AND's of a paradoxical SUBREG by constant, the
9994 SUBREGs are of the same mode, and, in both cases, the AND would
9995 be redundant if the comparison was done in the narrower mode,
9996 do the comparison in the narrower mode (e.g., we are AND'ing with 1
9997 and the operand's possibly nonzero bits are 0xffffff01; in that case
9998 if we only care about QImode, we don't need the AND). This case
9999 occurs if the output mode of an scc insn is not SImode and
10000 STORE_FLAG_VALUE == 1 (e.g., the 386).
10002 Similarly, check for a case where the AND's are ZERO_EXTEND
10003 operations from some narrower mode even though a SUBREG is not
10006 else if (GET_CODE (op0) == AND && GET_CODE (op1) == AND
10007 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10008 && GET_CODE (XEXP (op1, 1)) == CONST_INT)
10010 rtx inner_op0 = XEXP (op0, 0);
10011 rtx inner_op1 = XEXP (op1, 0);
10012 HOST_WIDE_INT c0 = INTVAL (XEXP (op0, 1));
10013 HOST_WIDE_INT c1 = INTVAL (XEXP (op1, 1));
10016 if (GET_CODE (inner_op0) == SUBREG && GET_CODE (inner_op1) == SUBREG
10017 && (GET_MODE_SIZE (GET_MODE (inner_op0))
10018 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (inner_op0))))
10019 && (GET_MODE (SUBREG_REG (inner_op0))
10020 == GET_MODE (SUBREG_REG (inner_op1)))
10021 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (inner_op0)))
10022 <= HOST_BITS_PER_WIDE_INT)
10023 && (0 == ((~c0) & nonzero_bits (SUBREG_REG (inner_op0),
10024 GET_MODE (SUBREG_REG (inner_op0)))))
10025 && (0 == ((~c1) & nonzero_bits (SUBREG_REG (inner_op1),
10026 GET_MODE (SUBREG_REG (inner_op1))))))
10028 op0 = SUBREG_REG (inner_op0);
10029 op1 = SUBREG_REG (inner_op1);
10031 /* The resulting comparison is always unsigned since we masked
10032 off the original sign bit. */
10033 code = unsigned_condition (code);
10039 for (tmode = GET_CLASS_NARROWEST_MODE
10040 (GET_MODE_CLASS (GET_MODE (op0)));
10041 tmode != GET_MODE (op0); tmode = GET_MODE_WIDER_MODE (tmode))
10042 if ((unsigned HOST_WIDE_INT) c0 == GET_MODE_MASK (tmode))
10044 op0 = gen_lowpart_for_combine (tmode, inner_op0);
10045 op1 = gen_lowpart_for_combine (tmode, inner_op1);
10046 code = unsigned_condition (code);
10055 /* If both operands are NOT, we can strip off the outer operation
10056 and adjust the comparison code for swapped operands; similarly for
10057 NEG, except that this must be an equality comparison. */
10058 else if ((GET_CODE (op0) == NOT && GET_CODE (op1) == NOT)
10059 || (GET_CODE (op0) == NEG && GET_CODE (op1) == NEG
10060 && (code == EQ || code == NE)))
10061 op0 = XEXP (op0, 0), op1 = XEXP (op1, 0), code = swap_condition (code);
10067 /* If the first operand is a constant, swap the operands and adjust the
10068 comparison code appropriately, but don't do this if the second operand
10069 is already a constant integer. */
10070 if (swap_commutative_operands_p (op0, op1))
10072 tem = op0, op0 = op1, op1 = tem;
10073 code = swap_condition (code);
10076 /* We now enter a loop during which we will try to simplify the comparison.
10077 For the most part, we only are concerned with comparisons with zero,
10078 but some things may really be comparisons with zero but not start
10079 out looking that way. */
10081 while (GET_CODE (op1) == CONST_INT)
10083 enum machine_mode mode = GET_MODE (op0);
10084 unsigned int mode_width = GET_MODE_BITSIZE (mode);
10085 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
10086 int equality_comparison_p;
10087 int sign_bit_comparison_p;
10088 int unsigned_comparison_p;
10089 HOST_WIDE_INT const_op;
10091 /* We only want to handle integral modes. This catches VOIDmode,
10092 CCmode, and the floating-point modes. An exception is that we
10093 can handle VOIDmode if OP0 is a COMPARE or a comparison
10096 if (GET_MODE_CLASS (mode) != MODE_INT
10097 && ! (mode == VOIDmode
10098 && (GET_CODE (op0) == COMPARE
10099 || GET_RTX_CLASS (GET_CODE (op0)) == '<')))
10102 /* Get the constant we are comparing against and turn off all bits
10103 not on in our mode. */
10104 const_op = trunc_int_for_mode (INTVAL (op1), mode);
10105 op1 = GEN_INT (const_op);
10107 /* If we are comparing against a constant power of two and the value
10108 being compared can only have that single bit nonzero (e.g., it was
10109 `and'ed with that bit), we can replace this with a comparison
10112 && (code == EQ || code == NE || code == GE || code == GEU
10113 || code == LT || code == LTU)
10114 && mode_width <= HOST_BITS_PER_WIDE_INT
10115 && exact_log2 (const_op) >= 0
10116 && nonzero_bits (op0, mode) == (unsigned HOST_WIDE_INT) const_op)
10118 code = (code == EQ || code == GE || code == GEU ? NE : EQ);
10119 op1 = const0_rtx, const_op = 0;
10122 /* Similarly, if we are comparing a value known to be either -1 or
10123 0 with -1, change it to the opposite comparison against zero. */
10126 && (code == EQ || code == NE || code == GT || code == LE
10127 || code == GEU || code == LTU)
10128 && num_sign_bit_copies (op0, mode) == mode_width)
10130 code = (code == EQ || code == LE || code == GEU ? NE : EQ);
10131 op1 = const0_rtx, const_op = 0;
10134 /* Do some canonicalizations based on the comparison code. We prefer
10135 comparisons against zero and then prefer equality comparisons.
10136 If we can reduce the size of a constant, we will do that too. */
10141 /* < C is equivalent to <= (C - 1) */
10145 op1 = GEN_INT (const_op);
10147 /* ... fall through to LE case below. */
10153 /* <= C is equivalent to < (C + 1); we do this for C < 0 */
10157 op1 = GEN_INT (const_op);
10161 /* If we are doing a <= 0 comparison on a value known to have
10162 a zero sign bit, we can replace this with == 0. */
10163 else if (const_op == 0
10164 && mode_width <= HOST_BITS_PER_WIDE_INT
10165 && (nonzero_bits (op0, mode)
10166 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)
10171 /* >= C is equivalent to > (C - 1). */
10175 op1 = GEN_INT (const_op);
10177 /* ... fall through to GT below. */
10183 /* > C is equivalent to >= (C + 1); we do this for C < 0. */
10187 op1 = GEN_INT (const_op);
10191 /* If we are doing a > 0 comparison on a value known to have
10192 a zero sign bit, we can replace this with != 0. */
10193 else if (const_op == 0
10194 && mode_width <= HOST_BITS_PER_WIDE_INT
10195 && (nonzero_bits (op0, mode)
10196 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)
10201 /* < C is equivalent to <= (C - 1). */
10205 op1 = GEN_INT (const_op);
10207 /* ... fall through ... */
10210 /* (unsigned) < 0x80000000 is equivalent to >= 0. */
10211 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
10212 && (const_op == (HOST_WIDE_INT) 1 << (mode_width - 1)))
10214 const_op = 0, op1 = const0_rtx;
10222 /* unsigned <= 0 is equivalent to == 0 */
10226 /* (unsigned) <= 0x7fffffff is equivalent to >= 0. */
10227 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
10228 && (const_op == ((HOST_WIDE_INT) 1 << (mode_width - 1)) - 1))
10230 const_op = 0, op1 = const0_rtx;
10236 /* >= C is equivalent to < (C - 1). */
10240 op1 = GEN_INT (const_op);
10242 /* ... fall through ... */
10245 /* (unsigned) >= 0x80000000 is equivalent to < 0. */
10246 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
10247 && (const_op == (HOST_WIDE_INT) 1 << (mode_width - 1)))
10249 const_op = 0, op1 = const0_rtx;
10257 /* unsigned > 0 is equivalent to != 0 */
10261 /* (unsigned) > 0x7fffffff is equivalent to < 0. */
10262 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
10263 && (const_op == ((HOST_WIDE_INT) 1 << (mode_width - 1)) - 1))
10265 const_op = 0, op1 = const0_rtx;
10274 /* Compute some predicates to simplify code below. */
10276 equality_comparison_p = (code == EQ || code == NE);
10277 sign_bit_comparison_p = ((code == LT || code == GE) && const_op == 0);
10278 unsigned_comparison_p = (code == LTU || code == LEU || code == GTU
10281 /* If this is a sign bit comparison and we can do arithmetic in
10282 MODE, say that we will only be needing the sign bit of OP0. */
10283 if (sign_bit_comparison_p
10284 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
10285 op0 = force_to_mode (op0, mode,
10287 << (GET_MODE_BITSIZE (mode) - 1)),
10290 /* Now try cases based on the opcode of OP0. If none of the cases
10291 does a "continue", we exit this loop immediately after the
10294 switch (GET_CODE (op0))
10297 /* If we are extracting a single bit from a variable position in
10298 a constant that has only a single bit set and are comparing it
10299 with zero, we can convert this into an equality comparison
10300 between the position and the location of the single bit. */
10302 if (GET_CODE (XEXP (op0, 0)) == CONST_INT
10303 && XEXP (op0, 1) == const1_rtx
10304 && equality_comparison_p && const_op == 0
10305 && (i = exact_log2 (INTVAL (XEXP (op0, 0)))) >= 0)
10307 if (BITS_BIG_ENDIAN)
10309 enum machine_mode new_mode
10310 = mode_for_extraction (EP_extzv, 1);
10311 if (new_mode == MAX_MACHINE_MODE)
10312 i = BITS_PER_WORD - 1 - i;
10316 i = (GET_MODE_BITSIZE (mode) - 1 - i);
10320 op0 = XEXP (op0, 2);
10324 /* Result is nonzero iff shift count is equal to I. */
10325 code = reverse_condition (code);
10329 /* ... fall through ... */
10332 tem = expand_compound_operation (op0);
10341 /* If testing for equality, we can take the NOT of the constant. */
10342 if (equality_comparison_p
10343 && (tem = simplify_unary_operation (NOT, mode, op1, mode)) != 0)
10345 op0 = XEXP (op0, 0);
10350 /* If just looking at the sign bit, reverse the sense of the
10352 if (sign_bit_comparison_p)
10354 op0 = XEXP (op0, 0);
10355 code = (code == GE ? LT : GE);
10361 /* If testing for equality, we can take the NEG of the constant. */
10362 if (equality_comparison_p
10363 && (tem = simplify_unary_operation (NEG, mode, op1, mode)) != 0)
10365 op0 = XEXP (op0, 0);
10370 /* The remaining cases only apply to comparisons with zero. */
10374 /* When X is ABS or is known positive,
10375 (neg X) is < 0 if and only if X != 0. */
10377 if (sign_bit_comparison_p
10378 && (GET_CODE (XEXP (op0, 0)) == ABS
10379 || (mode_width <= HOST_BITS_PER_WIDE_INT
10380 && (nonzero_bits (XEXP (op0, 0), mode)
10381 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)))
10383 op0 = XEXP (op0, 0);
10384 code = (code == LT ? NE : EQ);
10388 /* If we have NEG of something whose two high-order bits are the
10389 same, we know that "(-a) < 0" is equivalent to "a > 0". */
10390 if (num_sign_bit_copies (op0, mode) >= 2)
10392 op0 = XEXP (op0, 0);
10393 code = swap_condition (code);
10399 /* If we are testing equality and our count is a constant, we
10400 can perform the inverse operation on our RHS. */
10401 if (equality_comparison_p && GET_CODE (XEXP (op0, 1)) == CONST_INT
10402 && (tem = simplify_binary_operation (ROTATERT, mode,
10403 op1, XEXP (op0, 1))) != 0)
10405 op0 = XEXP (op0, 0);
10410 /* If we are doing a < 0 or >= 0 comparison, it means we are testing
10411 a particular bit. Convert it to an AND of a constant of that
10412 bit. This will be converted into a ZERO_EXTRACT. */
10413 if (const_op == 0 && sign_bit_comparison_p
10414 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10415 && mode_width <= HOST_BITS_PER_WIDE_INT)
10417 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
10420 - INTVAL (XEXP (op0, 1)))));
10421 code = (code == LT ? NE : EQ);
10425 /* Fall through. */
10428 /* ABS is ignorable inside an equality comparison with zero. */
10429 if (const_op == 0 && equality_comparison_p)
10431 op0 = XEXP (op0, 0);
10437 /* Can simplify (compare (zero/sign_extend FOO) CONST)
10438 to (compare FOO CONST) if CONST fits in FOO's mode and we
10439 are either testing inequality or have an unsigned comparison
10440 with ZERO_EXTEND or a signed comparison with SIGN_EXTEND. */
10441 if (! unsigned_comparison_p
10442 && (GET_MODE_BITSIZE (GET_MODE (XEXP (op0, 0)))
10443 <= HOST_BITS_PER_WIDE_INT)
10444 && ((unsigned HOST_WIDE_INT) const_op
10445 < (((unsigned HOST_WIDE_INT) 1
10446 << (GET_MODE_BITSIZE (GET_MODE (XEXP (op0, 0))) - 1)))))
10448 op0 = XEXP (op0, 0);
10454 /* Check for the case where we are comparing A - C1 with C2,
10455 both constants are smaller than 1/2 the maximum positive
10456 value in MODE, and the comparison is equality or unsigned.
10457 In that case, if A is either zero-extended to MODE or has
10458 sufficient sign bits so that the high-order bit in MODE
10459 is a copy of the sign in the inner mode, we can prove that it is
10460 safe to do the operation in the wider mode. This simplifies
10461 many range checks. */
10463 if (mode_width <= HOST_BITS_PER_WIDE_INT
10464 && subreg_lowpart_p (op0)
10465 && GET_CODE (SUBREG_REG (op0)) == PLUS
10466 && GET_CODE (XEXP (SUBREG_REG (op0), 1)) == CONST_INT
10467 && INTVAL (XEXP (SUBREG_REG (op0), 1)) < 0
10468 && (-INTVAL (XEXP (SUBREG_REG (op0), 1))
10469 < (HOST_WIDE_INT) (GET_MODE_MASK (mode) / 2))
10470 && (unsigned HOST_WIDE_INT) const_op < GET_MODE_MASK (mode) / 2
10471 && (0 == (nonzero_bits (XEXP (SUBREG_REG (op0), 0),
10472 GET_MODE (SUBREG_REG (op0)))
10473 & ~GET_MODE_MASK (mode))
10474 || (num_sign_bit_copies (XEXP (SUBREG_REG (op0), 0),
10475 GET_MODE (SUBREG_REG (op0)))
10476 > (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0)))
10477 - GET_MODE_BITSIZE (mode)))))
10479 op0 = SUBREG_REG (op0);
10483 /* If the inner mode is narrower and we are extracting the low part,
10484 we can treat the SUBREG as if it were a ZERO_EXTEND. */
10485 if (subreg_lowpart_p (op0)
10486 && GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0))) < mode_width)
10487 /* Fall through */ ;
10491 /* ... fall through ... */
10494 if ((unsigned_comparison_p || equality_comparison_p)
10495 && (GET_MODE_BITSIZE (GET_MODE (XEXP (op0, 0)))
10496 <= HOST_BITS_PER_WIDE_INT)
10497 && ((unsigned HOST_WIDE_INT) const_op
10498 < GET_MODE_MASK (GET_MODE (XEXP (op0, 0)))))
10500 op0 = XEXP (op0, 0);
10506 /* (eq (plus X A) B) -> (eq X (minus B A)). We can only do
10507 this for equality comparisons due to pathological cases involving
10509 if (equality_comparison_p
10510 && 0 != (tem = simplify_binary_operation (MINUS, mode,
10511 op1, XEXP (op0, 1))))
10513 op0 = XEXP (op0, 0);
10518 /* (plus (abs X) (const_int -1)) is < 0 if and only if X == 0. */
10519 if (const_op == 0 && XEXP (op0, 1) == constm1_rtx
10520 && GET_CODE (XEXP (op0, 0)) == ABS && sign_bit_comparison_p)
10522 op0 = XEXP (XEXP (op0, 0), 0);
10523 code = (code == LT ? EQ : NE);
10529 /* We used to optimize signed comparisons against zero, but that
10530 was incorrect. Unsigned comparisons against zero (GTU, LEU)
10531 arrive here as equality comparisons, or (GEU, LTU) are
10532 optimized away. No need to special-case them. */
10534 /* (eq (minus A B) C) -> (eq A (plus B C)) or
10535 (eq B (minus A C)), whichever simplifies. We can only do
10536 this for equality comparisons due to pathological cases involving
10538 if (equality_comparison_p
10539 && 0 != (tem = simplify_binary_operation (PLUS, mode,
10540 XEXP (op0, 1), op1)))
10542 op0 = XEXP (op0, 0);
10547 if (equality_comparison_p
10548 && 0 != (tem = simplify_binary_operation (MINUS, mode,
10549 XEXP (op0, 0), op1)))
10551 op0 = XEXP (op0, 1);
10556 /* The sign bit of (minus (ashiftrt X C) X), where C is the number
10557 of bits in X minus 1, is one iff X > 0. */
10558 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == ASHIFTRT
10559 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
10560 && INTVAL (XEXP (XEXP (op0, 0), 1)) == mode_width - 1
10561 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
10563 op0 = XEXP (op0, 1);
10564 code = (code == GE ? LE : GT);
10570 /* (eq (xor A B) C) -> (eq A (xor B C)). This is a simplification
10571 if C is zero or B is a constant. */
10572 if (equality_comparison_p
10573 && 0 != (tem = simplify_binary_operation (XOR, mode,
10574 XEXP (op0, 1), op1)))
10576 op0 = XEXP (op0, 0);
10583 case UNEQ: case LTGT:
10584 case LT: case LTU: case UNLT: case LE: case LEU: case UNLE:
10585 case GT: case GTU: case UNGT: case GE: case GEU: case UNGE:
10586 case UNORDERED: case ORDERED:
10587 /* We can't do anything if OP0 is a condition code value, rather
10588 than an actual data value. */
10591 || XEXP (op0, 0) == cc0_rtx
10593 || GET_MODE_CLASS (GET_MODE (XEXP (op0, 0))) == MODE_CC)
10596 /* Get the two operands being compared. */
10597 if (GET_CODE (XEXP (op0, 0)) == COMPARE)
10598 tem = XEXP (XEXP (op0, 0), 0), tem1 = XEXP (XEXP (op0, 0), 1);
10600 tem = XEXP (op0, 0), tem1 = XEXP (op0, 1);
10602 /* Check for the cases where we simply want the result of the
10603 earlier test or the opposite of that result. */
10604 if (code == NE || code == EQ
10605 || (GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
10606 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
10607 && (STORE_FLAG_VALUE
10608 & (((HOST_WIDE_INT) 1
10609 << (GET_MODE_BITSIZE (GET_MODE (op0)) - 1))))
10610 && (code == LT || code == GE)))
10612 enum rtx_code new_code;
10613 if (code == LT || code == NE)
10614 new_code = GET_CODE (op0);
10616 new_code = combine_reversed_comparison_code (op0);
10618 if (new_code != UNKNOWN)
10629 /* The sign bit of (ior (plus X (const_int -1)) X) is non-zero
10631 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == PLUS
10632 && XEXP (XEXP (op0, 0), 1) == constm1_rtx
10633 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
10635 op0 = XEXP (op0, 1);
10636 code = (code == GE ? GT : LE);
10642 /* Convert (and (xshift 1 X) Y) to (and (lshiftrt Y X) 1). This
10643 will be converted to a ZERO_EXTRACT later. */
10644 if (const_op == 0 && equality_comparison_p
10645 && GET_CODE (XEXP (op0, 0)) == ASHIFT
10646 && XEXP (XEXP (op0, 0), 0) == const1_rtx)
10648 op0 = simplify_and_const_int
10649 (op0, mode, gen_rtx_LSHIFTRT (mode,
10651 XEXP (XEXP (op0, 0), 1)),
10652 (HOST_WIDE_INT) 1);
10656 /* If we are comparing (and (lshiftrt X C1) C2) for equality with
10657 zero and X is a comparison and C1 and C2 describe only bits set
10658 in STORE_FLAG_VALUE, we can compare with X. */
10659 if (const_op == 0 && equality_comparison_p
10660 && mode_width <= HOST_BITS_PER_WIDE_INT
10661 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10662 && GET_CODE (XEXP (op0, 0)) == LSHIFTRT
10663 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
10664 && INTVAL (XEXP (XEXP (op0, 0), 1)) >= 0
10665 && INTVAL (XEXP (XEXP (op0, 0), 1)) < HOST_BITS_PER_WIDE_INT)
10667 mask = ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
10668 << INTVAL (XEXP (XEXP (op0, 0), 1)));
10669 if ((~STORE_FLAG_VALUE & mask) == 0
10670 && (GET_RTX_CLASS (GET_CODE (XEXP (XEXP (op0, 0), 0))) == '<'
10671 || ((tem = get_last_value (XEXP (XEXP (op0, 0), 0))) != 0
10672 && GET_RTX_CLASS (GET_CODE (tem)) == '<')))
10674 op0 = XEXP (XEXP (op0, 0), 0);
10679 /* If we are doing an equality comparison of an AND of a bit equal
10680 to the sign bit, replace this with a LT or GE comparison of
10681 the underlying value. */
10682 if (equality_comparison_p
10684 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10685 && mode_width <= HOST_BITS_PER_WIDE_INT
10686 && ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
10687 == (unsigned HOST_WIDE_INT) 1 << (mode_width - 1)))
10689 op0 = XEXP (op0, 0);
10690 code = (code == EQ ? GE : LT);
10694 /* If this AND operation is really a ZERO_EXTEND from a narrower
10695 mode, the constant fits within that mode, and this is either an
10696 equality or unsigned comparison, try to do this comparison in
10697 the narrower mode. */
10698 if ((equality_comparison_p || unsigned_comparison_p)
10699 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10700 && (i = exact_log2 ((INTVAL (XEXP (op0, 1))
10701 & GET_MODE_MASK (mode))
10703 && const_op >> i == 0
10704 && (tmode = mode_for_size (i, MODE_INT, 1)) != BLKmode)
10706 op0 = gen_lowpart_for_combine (tmode, XEXP (op0, 0));
10710 /* If this is (and:M1 (subreg:M2 X 0) (const_int C1)) where C1 fits
10711 in both M1 and M2 and the SUBREG is either paradoxical or
10712 represents the low part, permute the SUBREG and the AND and
10714 if (GET_CODE (XEXP (op0, 0)) == SUBREG
10716 #ifdef WORD_REGISTER_OPERATIONS
10718 > (GET_MODE_BITSIZE
10719 (GET_MODE (SUBREG_REG (XEXP (op0, 0))))))
10720 && mode_width <= BITS_PER_WORD)
10723 <= (GET_MODE_BITSIZE
10724 (GET_MODE (SUBREG_REG (XEXP (op0, 0))))))
10725 && subreg_lowpart_p (XEXP (op0, 0))))
10726 #ifndef WORD_REGISTER_OPERATIONS
10727 /* It is unsafe to commute the AND into the SUBREG if the SUBREG
10728 is paradoxical and WORD_REGISTER_OPERATIONS is not defined.
10729 As originally written the upper bits have a defined value
10730 due to the AND operation. However, if we commute the AND
10731 inside the SUBREG then they no longer have defined values
10732 and the meaning of the code has been changed. */
10733 && (GET_MODE_SIZE (GET_MODE (XEXP (op0, 0)))
10734 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (op0, 0)))))
10736 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10737 && mode_width <= HOST_BITS_PER_WIDE_INT
10738 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (XEXP (op0, 0))))
10739 <= HOST_BITS_PER_WIDE_INT)
10740 && (INTVAL (XEXP (op0, 1)) & ~mask) == 0
10741 && 0 == (~GET_MODE_MASK (GET_MODE (SUBREG_REG (XEXP (op0, 0))))
10742 & INTVAL (XEXP (op0, 1)))
10743 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (op0, 1)) != mask
10744 && ((unsigned HOST_WIDE_INT) INTVAL (XEXP (op0, 1))
10745 != GET_MODE_MASK (GET_MODE (SUBREG_REG (XEXP (op0, 0))))))
10749 = gen_lowpart_for_combine
10751 gen_binary (AND, GET_MODE (SUBREG_REG (XEXP (op0, 0))),
10752 SUBREG_REG (XEXP (op0, 0)), XEXP (op0, 1)));
10756 /* Convert (ne (and (lshiftrt (not X)) 1) 0) to
10757 (eq (and (lshiftrt X) 1) 0). */
10758 if (const_op == 0 && equality_comparison_p
10759 && XEXP (op0, 1) == const1_rtx
10760 && GET_CODE (XEXP (op0, 0)) == LSHIFTRT
10761 && GET_CODE (XEXP (XEXP (op0, 0), 0)) == NOT)
10763 op0 = simplify_and_const_int
10765 gen_rtx_LSHIFTRT (mode, XEXP (XEXP (XEXP (op0, 0), 0), 0),
10766 XEXP (XEXP (op0, 0), 1)),
10767 (HOST_WIDE_INT) 1);
10768 code = (code == NE ? EQ : NE);
10774 /* If we have (compare (ashift FOO N) (const_int C)) and
10775 the high order N bits of FOO (N+1 if an inequality comparison)
10776 are known to be zero, we can do this by comparing FOO with C
10777 shifted right N bits so long as the low-order N bits of C are
10779 if (GET_CODE (XEXP (op0, 1)) == CONST_INT
10780 && INTVAL (XEXP (op0, 1)) >= 0
10781 && ((INTVAL (XEXP (op0, 1)) + ! equality_comparison_p)
10782 < HOST_BITS_PER_WIDE_INT)
10784 & (((HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1))) - 1)) == 0)
10785 && mode_width <= HOST_BITS_PER_WIDE_INT
10786 && (nonzero_bits (XEXP (op0, 0), mode)
10787 & ~(mask >> (INTVAL (XEXP (op0, 1))
10788 + ! equality_comparison_p))) == 0)
10790 /* We must perform a logical shift, not an arithmetic one,
10791 as we want the top N bits of C to be zero. */
10792 unsigned HOST_WIDE_INT temp = const_op & GET_MODE_MASK (mode);
10794 temp >>= INTVAL (XEXP (op0, 1));
10795 op1 = gen_int_mode (temp, mode);
10796 op0 = XEXP (op0, 0);
10800 /* If we are doing a sign bit comparison, it means we are testing
10801 a particular bit. Convert it to the appropriate AND. */
10802 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 1)) == CONST_INT
10803 && mode_width <= HOST_BITS_PER_WIDE_INT)
10805 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
10808 - INTVAL (XEXP (op0, 1)))));
10809 code = (code == LT ? NE : EQ);
10813 /* If this an equality comparison with zero and we are shifting
10814 the low bit to the sign bit, we can convert this to an AND of the
10816 if (const_op == 0 && equality_comparison_p
10817 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10818 && INTVAL (XEXP (op0, 1)) == mode_width - 1)
10820 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
10821 (HOST_WIDE_INT) 1);
10827 /* If this is an equality comparison with zero, we can do this
10828 as a logical shift, which might be much simpler. */
10829 if (equality_comparison_p && const_op == 0
10830 && GET_CODE (XEXP (op0, 1)) == CONST_INT)
10832 op0 = simplify_shift_const (NULL_RTX, LSHIFTRT, mode,
10834 INTVAL (XEXP (op0, 1)));
10838 /* If OP0 is a sign extension and CODE is not an unsigned comparison,
10839 do the comparison in a narrower mode. */
10840 if (! unsigned_comparison_p
10841 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10842 && GET_CODE (XEXP (op0, 0)) == ASHIFT
10843 && XEXP (op0, 1) == XEXP (XEXP (op0, 0), 1)
10844 && (tmode = mode_for_size (mode_width - INTVAL (XEXP (op0, 1)),
10845 MODE_INT, 1)) != BLKmode
10846 && ((unsigned HOST_WIDE_INT) const_op <= GET_MODE_MASK (tmode)
10847 || ((unsigned HOST_WIDE_INT) -const_op
10848 <= GET_MODE_MASK (tmode))))
10850 op0 = gen_lowpart_for_combine (tmode, XEXP (XEXP (op0, 0), 0));
10854 /* Likewise if OP0 is a PLUS of a sign extension with a
10855 constant, which is usually represented with the PLUS
10856 between the shifts. */
10857 if (! unsigned_comparison_p
10858 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10859 && GET_CODE (XEXP (op0, 0)) == PLUS
10860 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
10861 && GET_CODE (XEXP (XEXP (op0, 0), 0)) == ASHIFT
10862 && XEXP (op0, 1) == XEXP (XEXP (XEXP (op0, 0), 0), 1)
10863 && (tmode = mode_for_size (mode_width - INTVAL (XEXP (op0, 1)),
10864 MODE_INT, 1)) != BLKmode
10865 && ((unsigned HOST_WIDE_INT) const_op <= GET_MODE_MASK (tmode)
10866 || ((unsigned HOST_WIDE_INT) -const_op
10867 <= GET_MODE_MASK (tmode))))
10869 rtx inner = XEXP (XEXP (XEXP (op0, 0), 0), 0);
10870 rtx add_const = XEXP (XEXP (op0, 0), 1);
10871 rtx new_const = gen_binary (ASHIFTRT, GET_MODE (op0), add_const,
10874 op0 = gen_binary (PLUS, tmode,
10875 gen_lowpart_for_combine (tmode, inner),
10880 /* ... fall through ... */
10882 /* If we have (compare (xshiftrt FOO N) (const_int C)) and
10883 the low order N bits of FOO are known to be zero, we can do this
10884 by comparing FOO with C shifted left N bits so long as no
10885 overflow occurs. */
10886 if (GET_CODE (XEXP (op0, 1)) == CONST_INT
10887 && INTVAL (XEXP (op0, 1)) >= 0
10888 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT
10889 && mode_width <= HOST_BITS_PER_WIDE_INT
10890 && (nonzero_bits (XEXP (op0, 0), mode)
10891 & (((HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1))) - 1)) == 0
10893 || (floor_log2 (const_op) + INTVAL (XEXP (op0, 1))
10896 /* If the shift was logical, then we must make the condition
10898 if (GET_CODE (op0) == LSHIFTRT)
10899 code = unsigned_condition (code);
10901 const_op <<= INTVAL (XEXP (op0, 1));
10902 op1 = GEN_INT (const_op);
10903 op0 = XEXP (op0, 0);
10907 /* If we are using this shift to extract just the sign bit, we
10908 can replace this with an LT or GE comparison. */
10910 && (equality_comparison_p || sign_bit_comparison_p)
10911 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10912 && INTVAL (XEXP (op0, 1)) == mode_width - 1)
10914 op0 = XEXP (op0, 0);
10915 code = (code == NE || code == GT ? LT : GE);
10927 /* Now make any compound operations involved in this comparison. Then,
10928 check for an outmost SUBREG on OP0 that is not doing anything or is
10929 paradoxical. The latter case can only occur when it is known that the
10930 "extra" bits will be zero. Therefore, it is safe to remove the SUBREG.
10931 We can never remove a SUBREG for a non-equality comparison because the
10932 sign bit is in a different place in the underlying object. */
10934 op0 = make_compound_operation (op0, op1 == const0_rtx ? COMPARE : SET);
10935 op1 = make_compound_operation (op1, SET);
10937 if (GET_CODE (op0) == SUBREG && subreg_lowpart_p (op0)
10938 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
10939 && GET_MODE_CLASS (GET_MODE (SUBREG_REG (op0))) == MODE_INT
10940 && (code == NE || code == EQ)
10941 && ((GET_MODE_SIZE (GET_MODE (op0))
10942 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (op0))))))
10944 op0 = SUBREG_REG (op0);
10945 op1 = gen_lowpart_for_combine (GET_MODE (op0), op1);
10948 else if (GET_CODE (op0) == SUBREG && subreg_lowpart_p (op0)
10949 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
10950 && GET_MODE_CLASS (GET_MODE (SUBREG_REG (op0))) == MODE_INT
10951 && (code == NE || code == EQ)
10952 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0)))
10953 <= HOST_BITS_PER_WIDE_INT)
10954 && (nonzero_bits (SUBREG_REG (op0), GET_MODE (SUBREG_REG (op0)))
10955 & ~GET_MODE_MASK (GET_MODE (op0))) == 0
10956 && (tem = gen_lowpart_for_combine (GET_MODE (SUBREG_REG (op0)),
10958 (nonzero_bits (tem, GET_MODE (SUBREG_REG (op0)))
10959 & ~GET_MODE_MASK (GET_MODE (op0))) == 0))
10960 op0 = SUBREG_REG (op0), op1 = tem;
10962 /* We now do the opposite procedure: Some machines don't have compare
10963 insns in all modes. If OP0's mode is an integer mode smaller than a
10964 word and we can't do a compare in that mode, see if there is a larger
10965 mode for which we can do the compare. There are a number of cases in
10966 which we can use the wider mode. */
10968 mode = GET_MODE (op0);
10969 if (mode != VOIDmode && GET_MODE_CLASS (mode) == MODE_INT
10970 && GET_MODE_SIZE (mode) < UNITS_PER_WORD
10971 && ! have_insn_for (COMPARE, mode))
10972 for (tmode = GET_MODE_WIDER_MODE (mode);
10974 && GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT);
10975 tmode = GET_MODE_WIDER_MODE (tmode))
10976 if (have_insn_for (COMPARE, tmode))
10980 /* If the only nonzero bits in OP0 and OP1 are those in the
10981 narrower mode and this is an equality or unsigned comparison,
10982 we can use the wider mode. Similarly for sign-extended
10983 values, in which case it is true for all comparisons. */
10984 zero_extended = ((code == EQ || code == NE
10985 || code == GEU || code == GTU
10986 || code == LEU || code == LTU)
10987 && (nonzero_bits (op0, tmode)
10988 & ~GET_MODE_MASK (mode)) == 0
10989 && ((GET_CODE (op1) == CONST_INT
10990 || (nonzero_bits (op1, tmode)
10991 & ~GET_MODE_MASK (mode)) == 0)));
10994 || ((num_sign_bit_copies (op0, tmode)
10995 > GET_MODE_BITSIZE (tmode) - GET_MODE_BITSIZE (mode))
10996 && (num_sign_bit_copies (op1, tmode)
10997 > GET_MODE_BITSIZE (tmode) - GET_MODE_BITSIZE (mode))))
10999 /* If OP0 is an AND and we don't have an AND in MODE either,
11000 make a new AND in the proper mode. */
11001 if (GET_CODE (op0) == AND
11002 && !have_insn_for (AND, mode))
11003 op0 = gen_binary (AND, tmode,
11004 gen_lowpart_for_combine (tmode,
11006 gen_lowpart_for_combine (tmode,
11009 op0 = gen_lowpart_for_combine (tmode, op0);
11010 if (zero_extended && GET_CODE (op1) == CONST_INT)
11011 op1 = GEN_INT (INTVAL (op1) & GET_MODE_MASK (mode));
11012 op1 = gen_lowpart_for_combine (tmode, op1);
11016 /* If this is a test for negative, we can make an explicit
11017 test of the sign bit. */
11019 if (op1 == const0_rtx && (code == LT || code == GE)
11020 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
11022 op0 = gen_binary (AND, tmode,
11023 gen_lowpart_for_combine (tmode, op0),
11024 GEN_INT ((HOST_WIDE_INT) 1
11025 << (GET_MODE_BITSIZE (mode) - 1)));
11026 code = (code == LT) ? NE : EQ;
11031 #ifdef CANONICALIZE_COMPARISON
11032 /* If this machine only supports a subset of valid comparisons, see if we
11033 can convert an unsupported one into a supported one. */
11034 CANONICALIZE_COMPARISON (code, op0, op1);
11043 /* Like jump.c' reversed_comparison_code, but use combine infrastructure for
11044 searching backward. */
11045 static enum rtx_code
11046 combine_reversed_comparison_code (exp)
11049 enum rtx_code code1 = reversed_comparison_code (exp, NULL);
11052 if (code1 != UNKNOWN
11053 || GET_MODE_CLASS (GET_MODE (XEXP (exp, 0))) != MODE_CC)
11055 /* Otherwise try and find where the condition codes were last set and
11057 x = get_last_value (XEXP (exp, 0));
11058 if (!x || GET_CODE (x) != COMPARE)
11060 return reversed_comparison_code_parts (GET_CODE (exp),
11061 XEXP (x, 0), XEXP (x, 1), NULL);
11063 /* Return comparison with reversed code of EXP and operands OP0 and OP1.
11064 Return NULL_RTX in case we fail to do the reversal. */
11066 reversed_comparison (exp, mode, op0, op1)
11068 enum machine_mode mode;
11070 enum rtx_code reversed_code = combine_reversed_comparison_code (exp);
11071 if (reversed_code == UNKNOWN)
11074 return gen_binary (reversed_code, mode, op0, op1);
11077 /* Utility function for following routine. Called when X is part of a value
11078 being stored into reg_last_set_value. Sets reg_last_set_table_tick
11079 for each register mentioned. Similar to mention_regs in cse.c */
11082 update_table_tick (x)
11085 enum rtx_code code = GET_CODE (x);
11086 const char *fmt = GET_RTX_FORMAT (code);
11091 unsigned int regno = REGNO (x);
11092 unsigned int endregno
11093 = regno + (regno < FIRST_PSEUDO_REGISTER
11094 ? HARD_REGNO_NREGS (regno, GET_MODE (x)) : 1);
11097 for (r = regno; r < endregno; r++)
11098 reg_last_set_table_tick[r] = label_tick;
11103 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
11104 /* Note that we can't have an "E" in values stored; see
11105 get_last_value_validate. */
11107 update_table_tick (XEXP (x, i));
11110 /* Record that REG is set to VALUE in insn INSN. If VALUE is zero, we
11111 are saying that the register is clobbered and we no longer know its
11112 value. If INSN is zero, don't update reg_last_set; this is only permitted
11113 with VALUE also zero and is used to invalidate the register. */
11116 record_value_for_reg (reg, insn, value)
11121 unsigned int regno = REGNO (reg);
11122 unsigned int endregno
11123 = regno + (regno < FIRST_PSEUDO_REGISTER
11124 ? HARD_REGNO_NREGS (regno, GET_MODE (reg)) : 1);
11127 /* If VALUE contains REG and we have a previous value for REG, substitute
11128 the previous value. */
11129 if (value && insn && reg_overlap_mentioned_p (reg, value))
11133 /* Set things up so get_last_value is allowed to see anything set up to
11135 subst_low_cuid = INSN_CUID (insn);
11136 tem = get_last_value (reg);
11138 /* If TEM is simply a binary operation with two CLOBBERs as operands,
11139 it isn't going to be useful and will take a lot of time to process,
11140 so just use the CLOBBER. */
11144 if ((GET_RTX_CLASS (GET_CODE (tem)) == '2'
11145 || GET_RTX_CLASS (GET_CODE (tem)) == 'c')
11146 && GET_CODE (XEXP (tem, 0)) == CLOBBER
11147 && GET_CODE (XEXP (tem, 1)) == CLOBBER)
11148 tem = XEXP (tem, 0);
11150 value = replace_rtx (copy_rtx (value), reg, tem);
11154 /* For each register modified, show we don't know its value, that
11155 we don't know about its bitwise content, that its value has been
11156 updated, and that we don't know the location of the death of the
11158 for (i = regno; i < endregno; i++)
11161 reg_last_set[i] = insn;
11163 reg_last_set_value[i] = 0;
11164 reg_last_set_mode[i] = 0;
11165 reg_last_set_nonzero_bits[i] = 0;
11166 reg_last_set_sign_bit_copies[i] = 0;
11167 reg_last_death[i] = 0;
11170 /* Mark registers that are being referenced in this value. */
11172 update_table_tick (value);
11174 /* Now update the status of each register being set.
11175 If someone is using this register in this block, set this register
11176 to invalid since we will get confused between the two lives in this
11177 basic block. This makes using this register always invalid. In cse, we
11178 scan the table to invalidate all entries using this register, but this
11179 is too much work for us. */
11181 for (i = regno; i < endregno; i++)
11183 reg_last_set_label[i] = label_tick;
11184 if (value && reg_last_set_table_tick[i] == label_tick)
11185 reg_last_set_invalid[i] = 1;
11187 reg_last_set_invalid[i] = 0;
11190 /* The value being assigned might refer to X (like in "x++;"). In that
11191 case, we must replace it with (clobber (const_int 0)) to prevent
11193 if (value && ! get_last_value_validate (&value, insn,
11194 reg_last_set_label[regno], 0))
11196 value = copy_rtx (value);
11197 if (! get_last_value_validate (&value, insn,
11198 reg_last_set_label[regno], 1))
11202 /* For the main register being modified, update the value, the mode, the
11203 nonzero bits, and the number of sign bit copies. */
11205 reg_last_set_value[regno] = value;
11209 subst_low_cuid = INSN_CUID (insn);
11210 reg_last_set_mode[regno] = GET_MODE (reg);
11211 reg_last_set_nonzero_bits[regno] = nonzero_bits (value, GET_MODE (reg));
11212 reg_last_set_sign_bit_copies[regno]
11213 = num_sign_bit_copies (value, GET_MODE (reg));
11217 /* Called via note_stores from record_dead_and_set_regs to handle one
11218 SET or CLOBBER in an insn. DATA is the instruction in which the
11219 set is occurring. */
11222 record_dead_and_set_regs_1 (dest, setter, data)
11226 rtx record_dead_insn = (rtx) data;
11228 if (GET_CODE (dest) == SUBREG)
11229 dest = SUBREG_REG (dest);
11231 if (GET_CODE (dest) == REG)
11233 /* If we are setting the whole register, we know its value. Otherwise
11234 show that we don't know the value. We can handle SUBREG in
11236 if (GET_CODE (setter) == SET && dest == SET_DEST (setter))
11237 record_value_for_reg (dest, record_dead_insn, SET_SRC (setter));
11238 else if (GET_CODE (setter) == SET
11239 && GET_CODE (SET_DEST (setter)) == SUBREG
11240 && SUBREG_REG (SET_DEST (setter)) == dest
11241 && GET_MODE_BITSIZE (GET_MODE (dest)) <= BITS_PER_WORD
11242 && subreg_lowpart_p (SET_DEST (setter)))
11243 record_value_for_reg (dest, record_dead_insn,
11244 gen_lowpart_for_combine (GET_MODE (dest),
11245 SET_SRC (setter)));
11247 record_value_for_reg (dest, record_dead_insn, NULL_RTX);
11249 else if (GET_CODE (dest) == MEM
11250 /* Ignore pushes, they clobber nothing. */
11251 && ! push_operand (dest, GET_MODE (dest)))
11252 mem_last_set = INSN_CUID (record_dead_insn);
11255 /* Update the records of when each REG was most recently set or killed
11256 for the things done by INSN. This is the last thing done in processing
11257 INSN in the combiner loop.
11259 We update reg_last_set, reg_last_set_value, reg_last_set_mode,
11260 reg_last_set_nonzero_bits, reg_last_set_sign_bit_copies, reg_last_death,
11261 and also the similar information mem_last_set (which insn most recently
11262 modified memory) and last_call_cuid (which insn was the most recent
11263 subroutine call). */
11266 record_dead_and_set_regs (insn)
11272 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
11274 if (REG_NOTE_KIND (link) == REG_DEAD
11275 && GET_CODE (XEXP (link, 0)) == REG)
11277 unsigned int regno = REGNO (XEXP (link, 0));
11278 unsigned int endregno
11279 = regno + (regno < FIRST_PSEUDO_REGISTER
11280 ? HARD_REGNO_NREGS (regno, GET_MODE (XEXP (link, 0)))
11283 for (i = regno; i < endregno; i++)
11284 reg_last_death[i] = insn;
11286 else if (REG_NOTE_KIND (link) == REG_INC)
11287 record_value_for_reg (XEXP (link, 0), insn, NULL_RTX);
11290 if (GET_CODE (insn) == CALL_INSN)
11292 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
11293 if (TEST_HARD_REG_BIT (regs_invalidated_by_call, i))
11295 reg_last_set_value[i] = 0;
11296 reg_last_set_mode[i] = 0;
11297 reg_last_set_nonzero_bits[i] = 0;
11298 reg_last_set_sign_bit_copies[i] = 0;
11299 reg_last_death[i] = 0;
11302 last_call_cuid = mem_last_set = INSN_CUID (insn);
11304 /* Don't bother recording what this insn does. It might set the
11305 return value register, but we can't combine into a call
11306 pattern anyway, so there's no point trying (and it may cause
11307 a crash, if e.g. we wind up asking for last_set_value of a
11308 SUBREG of the return value register). */
11312 note_stores (PATTERN (insn), record_dead_and_set_regs_1, insn);
11315 /* If a SUBREG has the promoted bit set, it is in fact a property of the
11316 register present in the SUBREG, so for each such SUBREG go back and
11317 adjust nonzero and sign bit information of the registers that are
11318 known to have some zero/sign bits set.
11320 This is needed because when combine blows the SUBREGs away, the
11321 information on zero/sign bits is lost and further combines can be
11322 missed because of that. */
11325 record_promoted_value (insn, subreg)
11330 unsigned int regno = REGNO (SUBREG_REG (subreg));
11331 enum machine_mode mode = GET_MODE (subreg);
11333 if (GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT)
11336 for (links = LOG_LINKS (insn); links;)
11338 insn = XEXP (links, 0);
11339 set = single_set (insn);
11341 if (! set || GET_CODE (SET_DEST (set)) != REG
11342 || REGNO (SET_DEST (set)) != regno
11343 || GET_MODE (SET_DEST (set)) != GET_MODE (SUBREG_REG (subreg)))
11345 links = XEXP (links, 1);
11349 if (reg_last_set[regno] == insn)
11351 if (SUBREG_PROMOTED_UNSIGNED_P (subreg) > 0)
11352 reg_last_set_nonzero_bits[regno] &= GET_MODE_MASK (mode);
11355 if (GET_CODE (SET_SRC (set)) == REG)
11357 regno = REGNO (SET_SRC (set));
11358 links = LOG_LINKS (insn);
11365 /* Scan X for promoted SUBREGs. For each one found,
11366 note what it implies to the registers used in it. */
11369 check_promoted_subreg (insn, x)
11373 if (GET_CODE (x) == SUBREG && SUBREG_PROMOTED_VAR_P (x)
11374 && GET_CODE (SUBREG_REG (x)) == REG)
11375 record_promoted_value (insn, x);
11378 const char *format = GET_RTX_FORMAT (GET_CODE (x));
11381 for (i = 0; i < GET_RTX_LENGTH (GET_CODE (x)); i++)
11385 check_promoted_subreg (insn, XEXP (x, i));
11389 if (XVEC (x, i) != 0)
11390 for (j = 0; j < XVECLEN (x, i); j++)
11391 check_promoted_subreg (insn, XVECEXP (x, i, j));
11397 /* Utility routine for the following function. Verify that all the registers
11398 mentioned in *LOC are valid when *LOC was part of a value set when
11399 label_tick == TICK. Return 0 if some are not.
11401 If REPLACE is non-zero, replace the invalid reference with
11402 (clobber (const_int 0)) and return 1. This replacement is useful because
11403 we often can get useful information about the form of a value (e.g., if
11404 it was produced by a shift that always produces -1 or 0) even though
11405 we don't know exactly what registers it was produced from. */
11408 get_last_value_validate (loc, insn, tick, replace)
11415 const char *fmt = GET_RTX_FORMAT (GET_CODE (x));
11416 int len = GET_RTX_LENGTH (GET_CODE (x));
11419 if (GET_CODE (x) == REG)
11421 unsigned int regno = REGNO (x);
11422 unsigned int endregno
11423 = regno + (regno < FIRST_PSEUDO_REGISTER
11424 ? HARD_REGNO_NREGS (regno, GET_MODE (x)) : 1);
11427 for (j = regno; j < endregno; j++)
11428 if (reg_last_set_invalid[j]
11429 /* If this is a pseudo-register that was only set once and not
11430 live at the beginning of the function, it is always valid. */
11431 || (! (regno >= FIRST_PSEUDO_REGISTER
11432 && REG_N_SETS (regno) == 1
11433 && (! REGNO_REG_SET_P
11434 (BASIC_BLOCK (0)->global_live_at_start, regno)))
11435 && reg_last_set_label[j] > tick))
11438 *loc = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
11444 /* If this is a memory reference, make sure that there were
11445 no stores after it that might have clobbered the value. We don't
11446 have alias info, so we assume any store invalidates it. */
11447 else if (GET_CODE (x) == MEM && ! RTX_UNCHANGING_P (x)
11448 && INSN_CUID (insn) <= mem_last_set)
11451 *loc = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
11455 for (i = 0; i < len; i++)
11457 && get_last_value_validate (&XEXP (x, i), insn, tick, replace) == 0)
11458 /* Don't bother with these. They shouldn't occur anyway. */
11462 /* If we haven't found a reason for it to be invalid, it is valid. */
11466 /* Get the last value assigned to X, if known. Some registers
11467 in the value may be replaced with (clobber (const_int 0)) if their value
11468 is known longer known reliably. */
11474 unsigned int regno;
11477 /* If this is a non-paradoxical SUBREG, get the value of its operand and
11478 then convert it to the desired mode. If this is a paradoxical SUBREG,
11479 we cannot predict what values the "extra" bits might have. */
11480 if (GET_CODE (x) == SUBREG
11481 && subreg_lowpart_p (x)
11482 && (GET_MODE_SIZE (GET_MODE (x))
11483 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
11484 && (value = get_last_value (SUBREG_REG (x))) != 0)
11485 return gen_lowpart_for_combine (GET_MODE (x), value);
11487 if (GET_CODE (x) != REG)
11491 value = reg_last_set_value[regno];
11493 /* If we don't have a value, or if it isn't for this basic block and
11494 it's either a hard register, set more than once, or it's a live
11495 at the beginning of the function, return 0.
11497 Because if it's not live at the beginning of the function then the reg
11498 is always set before being used (is never used without being set).
11499 And, if it's set only once, and it's always set before use, then all
11500 uses must have the same last value, even if it's not from this basic
11504 || (reg_last_set_label[regno] != label_tick
11505 && (regno < FIRST_PSEUDO_REGISTER
11506 || REG_N_SETS (regno) != 1
11507 || (REGNO_REG_SET_P
11508 (BASIC_BLOCK (0)->global_live_at_start, regno)))))
11511 /* If the value was set in a later insn than the ones we are processing,
11512 we can't use it even if the register was only set once. */
11513 if (INSN_CUID (reg_last_set[regno]) >= subst_low_cuid)
11516 /* If the value has all its registers valid, return it. */
11517 if (get_last_value_validate (&value, reg_last_set[regno],
11518 reg_last_set_label[regno], 0))
11521 /* Otherwise, make a copy and replace any invalid register with
11522 (clobber (const_int 0)). If that fails for some reason, return 0. */
11524 value = copy_rtx (value);
11525 if (get_last_value_validate (&value, reg_last_set[regno],
11526 reg_last_set_label[regno], 1))
11532 /* Return nonzero if expression X refers to a REG or to memory
11533 that is set in an instruction more recent than FROM_CUID. */
11536 use_crosses_set_p (x, from_cuid)
11542 enum rtx_code code = GET_CODE (x);
11546 unsigned int regno = REGNO (x);
11547 unsigned endreg = regno + (regno < FIRST_PSEUDO_REGISTER
11548 ? HARD_REGNO_NREGS (regno, GET_MODE (x)) : 1);
11550 #ifdef PUSH_ROUNDING
11551 /* Don't allow uses of the stack pointer to be moved,
11552 because we don't know whether the move crosses a push insn. */
11553 if (regno == STACK_POINTER_REGNUM && PUSH_ARGS)
11556 for (; regno < endreg; regno++)
11557 if (reg_last_set[regno]
11558 && INSN_CUID (reg_last_set[regno]) > from_cuid)
11563 if (code == MEM && mem_last_set > from_cuid)
11566 fmt = GET_RTX_FORMAT (code);
11568 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
11573 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
11574 if (use_crosses_set_p (XVECEXP (x, i, j), from_cuid))
11577 else if (fmt[i] == 'e'
11578 && use_crosses_set_p (XEXP (x, i), from_cuid))
11584 /* Define three variables used for communication between the following
11587 static unsigned int reg_dead_regno, reg_dead_endregno;
11588 static int reg_dead_flag;
11590 /* Function called via note_stores from reg_dead_at_p.
11592 If DEST is within [reg_dead_regno, reg_dead_endregno), set
11593 reg_dead_flag to 1 if X is a CLOBBER and to -1 it is a SET. */
11596 reg_dead_at_p_1 (dest, x, data)
11599 void *data ATTRIBUTE_UNUSED;
11601 unsigned int regno, endregno;
11603 if (GET_CODE (dest) != REG)
11606 regno = REGNO (dest);
11607 endregno = regno + (regno < FIRST_PSEUDO_REGISTER
11608 ? HARD_REGNO_NREGS (regno, GET_MODE (dest)) : 1);
11610 if (reg_dead_endregno > regno && reg_dead_regno < endregno)
11611 reg_dead_flag = (GET_CODE (x) == CLOBBER) ? 1 : -1;
11614 /* Return non-zero if REG is known to be dead at INSN.
11616 We scan backwards from INSN. If we hit a REG_DEAD note or a CLOBBER
11617 referencing REG, it is dead. If we hit a SET referencing REG, it is
11618 live. Otherwise, see if it is live or dead at the start of the basic
11619 block we are in. Hard regs marked as being live in NEWPAT_USED_REGS
11620 must be assumed to be always live. */
11623 reg_dead_at_p (reg, insn)
11630 /* Set variables for reg_dead_at_p_1. */
11631 reg_dead_regno = REGNO (reg);
11632 reg_dead_endregno = reg_dead_regno + (reg_dead_regno < FIRST_PSEUDO_REGISTER
11633 ? HARD_REGNO_NREGS (reg_dead_regno,
11639 /* Check that reg isn't mentioned in NEWPAT_USED_REGS. */
11640 if (reg_dead_regno < FIRST_PSEUDO_REGISTER)
11642 for (i = reg_dead_regno; i < reg_dead_endregno; i++)
11643 if (TEST_HARD_REG_BIT (newpat_used_regs, i))
11647 /* Scan backwards until we find a REG_DEAD note, SET, CLOBBER, label, or
11648 beginning of function. */
11649 for (; insn && GET_CODE (insn) != CODE_LABEL && GET_CODE (insn) != BARRIER;
11650 insn = prev_nonnote_insn (insn))
11652 note_stores (PATTERN (insn), reg_dead_at_p_1, NULL);
11654 return reg_dead_flag == 1 ? 1 : 0;
11656 if (find_regno_note (insn, REG_DEAD, reg_dead_regno))
11660 /* Get the basic block number that we were in. */
11665 for (block = 0; block < n_basic_blocks; block++)
11666 if (insn == BLOCK_HEAD (block))
11669 if (block == n_basic_blocks)
11673 for (i = reg_dead_regno; i < reg_dead_endregno; i++)
11674 if (REGNO_REG_SET_P (BASIC_BLOCK (block)->global_live_at_start, i))
11680 /* Note hard registers in X that are used. This code is similar to
11681 that in flow.c, but much simpler since we don't care about pseudos. */
11684 mark_used_regs_combine (x)
11687 RTX_CODE code = GET_CODE (x);
11688 unsigned int regno;
11701 case ADDR_DIFF_VEC:
11704 /* CC0 must die in the insn after it is set, so we don't need to take
11705 special note of it here. */
11711 /* If we are clobbering a MEM, mark any hard registers inside the
11712 address as used. */
11713 if (GET_CODE (XEXP (x, 0)) == MEM)
11714 mark_used_regs_combine (XEXP (XEXP (x, 0), 0));
11719 /* A hard reg in a wide mode may really be multiple registers.
11720 If so, mark all of them just like the first. */
11721 if (regno < FIRST_PSEUDO_REGISTER)
11723 unsigned int endregno, r;
11725 /* None of this applies to the stack, frame or arg pointers */
11726 if (regno == STACK_POINTER_REGNUM
11727 #if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM
11728 || regno == HARD_FRAME_POINTER_REGNUM
11730 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
11731 || (regno == ARG_POINTER_REGNUM && fixed_regs[regno])
11733 || regno == FRAME_POINTER_REGNUM)
11736 endregno = regno + HARD_REGNO_NREGS (regno, GET_MODE (x));
11737 for (r = regno; r < endregno; r++)
11738 SET_HARD_REG_BIT (newpat_used_regs, r);
11744 /* If setting a MEM, or a SUBREG of a MEM, then note any hard regs in
11746 rtx testreg = SET_DEST (x);
11748 while (GET_CODE (testreg) == SUBREG
11749 || GET_CODE (testreg) == ZERO_EXTRACT
11750 || GET_CODE (testreg) == SIGN_EXTRACT
11751 || GET_CODE (testreg) == STRICT_LOW_PART)
11752 testreg = XEXP (testreg, 0);
11754 if (GET_CODE (testreg) == MEM)
11755 mark_used_regs_combine (XEXP (testreg, 0));
11757 mark_used_regs_combine (SET_SRC (x));
11765 /* Recursively scan the operands of this expression. */
11768 const char *fmt = GET_RTX_FORMAT (code);
11770 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
11773 mark_used_regs_combine (XEXP (x, i));
11774 else if (fmt[i] == 'E')
11778 for (j = 0; j < XVECLEN (x, i); j++)
11779 mark_used_regs_combine (XVECEXP (x, i, j));
11785 /* Remove register number REGNO from the dead registers list of INSN.
11787 Return the note used to record the death, if there was one. */
11790 remove_death (regno, insn)
11791 unsigned int regno;
11794 rtx note = find_regno_note (insn, REG_DEAD, regno);
11798 REG_N_DEATHS (regno)--;
11799 remove_note (insn, note);
11805 /* For each register (hardware or pseudo) used within expression X, if its
11806 death is in an instruction with cuid between FROM_CUID (inclusive) and
11807 TO_INSN (exclusive), put a REG_DEAD note for that register in the
11808 list headed by PNOTES.
11810 That said, don't move registers killed by maybe_kill_insn.
11812 This is done when X is being merged by combination into TO_INSN. These
11813 notes will then be distributed as needed. */
11816 move_deaths (x, maybe_kill_insn, from_cuid, to_insn, pnotes)
11818 rtx maybe_kill_insn;
11825 enum rtx_code code = GET_CODE (x);
11829 unsigned int regno = REGNO (x);
11830 rtx where_dead = reg_last_death[regno];
11831 rtx before_dead, after_dead;
11833 /* Don't move the register if it gets killed in between from and to */
11834 if (maybe_kill_insn && reg_set_p (x, maybe_kill_insn)
11835 && ! reg_referenced_p (x, maybe_kill_insn))
11838 /* WHERE_DEAD could be a USE insn made by combine, so first we
11839 make sure that we have insns with valid INSN_CUID values. */
11840 before_dead = where_dead;
11841 while (before_dead && INSN_UID (before_dead) > max_uid_cuid)
11842 before_dead = PREV_INSN (before_dead);
11844 after_dead = where_dead;
11845 while (after_dead && INSN_UID (after_dead) > max_uid_cuid)
11846 after_dead = NEXT_INSN (after_dead);
11848 if (before_dead && after_dead
11849 && INSN_CUID (before_dead) >= from_cuid
11850 && (INSN_CUID (after_dead) < INSN_CUID (to_insn)
11851 || (where_dead != after_dead
11852 && INSN_CUID (after_dead) == INSN_CUID (to_insn))))
11854 rtx note = remove_death (regno, where_dead);
11856 /* It is possible for the call above to return 0. This can occur
11857 when reg_last_death points to I2 or I1 that we combined with.
11858 In that case make a new note.
11860 We must also check for the case where X is a hard register
11861 and NOTE is a death note for a range of hard registers
11862 including X. In that case, we must put REG_DEAD notes for
11863 the remaining registers in place of NOTE. */
11865 if (note != 0 && regno < FIRST_PSEUDO_REGISTER
11866 && (GET_MODE_SIZE (GET_MODE (XEXP (note, 0)))
11867 > GET_MODE_SIZE (GET_MODE (x))))
11869 unsigned int deadregno = REGNO (XEXP (note, 0));
11870 unsigned int deadend
11871 = (deadregno + HARD_REGNO_NREGS (deadregno,
11872 GET_MODE (XEXP (note, 0))));
11873 unsigned int ourend
11874 = regno + HARD_REGNO_NREGS (regno, GET_MODE (x));
11877 for (i = deadregno; i < deadend; i++)
11878 if (i < regno || i >= ourend)
11879 REG_NOTES (where_dead)
11880 = gen_rtx_EXPR_LIST (REG_DEAD,
11881 gen_rtx_REG (reg_raw_mode[i], i),
11882 REG_NOTES (where_dead));
11885 /* If we didn't find any note, or if we found a REG_DEAD note that
11886 covers only part of the given reg, and we have a multi-reg hard
11887 register, then to be safe we must check for REG_DEAD notes
11888 for each register other than the first. They could have
11889 their own REG_DEAD notes lying around. */
11890 else if ((note == 0
11892 && (GET_MODE_SIZE (GET_MODE (XEXP (note, 0)))
11893 < GET_MODE_SIZE (GET_MODE (x)))))
11894 && regno < FIRST_PSEUDO_REGISTER
11895 && HARD_REGNO_NREGS (regno, GET_MODE (x)) > 1)
11897 unsigned int ourend
11898 = regno + HARD_REGNO_NREGS (regno, GET_MODE (x));
11899 unsigned int i, offset;
11903 offset = HARD_REGNO_NREGS (regno, GET_MODE (XEXP (note, 0)));
11907 for (i = regno + offset; i < ourend; i++)
11908 move_deaths (gen_rtx_REG (reg_raw_mode[i], i),
11909 maybe_kill_insn, from_cuid, to_insn, &oldnotes);
11912 if (note != 0 && GET_MODE (XEXP (note, 0)) == GET_MODE (x))
11914 XEXP (note, 1) = *pnotes;
11918 *pnotes = gen_rtx_EXPR_LIST (REG_DEAD, x, *pnotes);
11920 REG_N_DEATHS (regno)++;
11926 else if (GET_CODE (x) == SET)
11928 rtx dest = SET_DEST (x);
11930 move_deaths (SET_SRC (x), maybe_kill_insn, from_cuid, to_insn, pnotes);
11932 /* In the case of a ZERO_EXTRACT, a STRICT_LOW_PART, or a SUBREG
11933 that accesses one word of a multi-word item, some
11934 piece of everything register in the expression is used by
11935 this insn, so remove any old death. */
11936 /* ??? So why do we test for equality of the sizes? */
11938 if (GET_CODE (dest) == ZERO_EXTRACT
11939 || GET_CODE (dest) == STRICT_LOW_PART
11940 || (GET_CODE (dest) == SUBREG
11941 && (((GET_MODE_SIZE (GET_MODE (dest))
11942 + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
11943 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (dest)))
11944 + UNITS_PER_WORD - 1) / UNITS_PER_WORD))))
11946 move_deaths (dest, maybe_kill_insn, from_cuid, to_insn, pnotes);
11950 /* If this is some other SUBREG, we know it replaces the entire
11951 value, so use that as the destination. */
11952 if (GET_CODE (dest) == SUBREG)
11953 dest = SUBREG_REG (dest);
11955 /* If this is a MEM, adjust deaths of anything used in the address.
11956 For a REG (the only other possibility), the entire value is
11957 being replaced so the old value is not used in this insn. */
11959 if (GET_CODE (dest) == MEM)
11960 move_deaths (XEXP (dest, 0), maybe_kill_insn, from_cuid,
11965 else if (GET_CODE (x) == CLOBBER)
11968 len = GET_RTX_LENGTH (code);
11969 fmt = GET_RTX_FORMAT (code);
11971 for (i = 0; i < len; i++)
11976 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
11977 move_deaths (XVECEXP (x, i, j), maybe_kill_insn, from_cuid,
11980 else if (fmt[i] == 'e')
11981 move_deaths (XEXP (x, i), maybe_kill_insn, from_cuid, to_insn, pnotes);
11985 /* Return 1 if X is the target of a bit-field assignment in BODY, the
11986 pattern of an insn. X must be a REG. */
11989 reg_bitfield_target_p (x, body)
11995 if (GET_CODE (body) == SET)
11997 rtx dest = SET_DEST (body);
11999 unsigned int regno, tregno, endregno, endtregno;
12001 if (GET_CODE (dest) == ZERO_EXTRACT)
12002 target = XEXP (dest, 0);
12003 else if (GET_CODE (dest) == STRICT_LOW_PART)
12004 target = SUBREG_REG (XEXP (dest, 0));
12008 if (GET_CODE (target) == SUBREG)
12009 target = SUBREG_REG (target);
12011 if (GET_CODE (target) != REG)
12014 tregno = REGNO (target), regno = REGNO (x);
12015 if (tregno >= FIRST_PSEUDO_REGISTER || regno >= FIRST_PSEUDO_REGISTER)
12016 return target == x;
12018 endtregno = tregno + HARD_REGNO_NREGS (tregno, GET_MODE (target));
12019 endregno = regno + HARD_REGNO_NREGS (regno, GET_MODE (x));
12021 return endregno > tregno && regno < endtregno;
12024 else if (GET_CODE (body) == PARALLEL)
12025 for (i = XVECLEN (body, 0) - 1; i >= 0; i--)
12026 if (reg_bitfield_target_p (x, XVECEXP (body, 0, i)))
12032 /* Given a chain of REG_NOTES originally from FROM_INSN, try to place them
12033 as appropriate. I3 and I2 are the insns resulting from the combination
12034 insns including FROM (I2 may be zero).
12036 ELIM_I2 and ELIM_I1 are either zero or registers that we know will
12037 not need REG_DEAD notes because they are being substituted for. This
12038 saves searching in the most common cases.
12040 Each note in the list is either ignored or placed on some insns, depending
12041 on the type of note. */
12044 distribute_notes (notes, from_insn, i3, i2, elim_i2, elim_i1)
12048 rtx elim_i2, elim_i1;
12050 rtx note, next_note;
12053 for (note = notes; note; note = next_note)
12055 rtx place = 0, place2 = 0;
12057 /* If this NOTE references a pseudo register, ensure it references
12058 the latest copy of that register. */
12059 if (XEXP (note, 0) && GET_CODE (XEXP (note, 0)) == REG
12060 && REGNO (XEXP (note, 0)) >= FIRST_PSEUDO_REGISTER)
12061 XEXP (note, 0) = regno_reg_rtx[REGNO (XEXP (note, 0))];
12063 next_note = XEXP (note, 1);
12064 switch (REG_NOTE_KIND (note))
12068 case REG_EXEC_COUNT:
12069 /* Doesn't matter much where we put this, as long as it's somewhere.
12070 It is preferable to keep these notes on branches, which is most
12071 likely to be i3. */
12075 case REG_VTABLE_REF:
12076 /* ??? Should remain with *a particular* memory load. Given the
12077 nature of vtable data, the last insn seems relatively safe. */
12081 case REG_NON_LOCAL_GOTO:
12082 if (GET_CODE (i3) == JUMP_INSN)
12084 else if (i2 && GET_CODE (i2) == JUMP_INSN)
12090 case REG_EH_REGION:
12091 /* These notes must remain with the call or trapping instruction. */
12092 if (GET_CODE (i3) == CALL_INSN)
12094 else if (i2 && GET_CODE (i2) == CALL_INSN)
12096 else if (flag_non_call_exceptions)
12098 if (may_trap_p (i3))
12100 else if (i2 && may_trap_p (i2))
12102 /* ??? Otherwise assume we've combined things such that we
12103 can now prove that the instructions can't trap. Drop the
12104 note in this case. */
12112 /* These notes must remain with the call. It should not be
12113 possible for both I2 and I3 to be a call. */
12114 if (GET_CODE (i3) == CALL_INSN)
12116 else if (i2 && GET_CODE (i2) == CALL_INSN)
12123 /* Any clobbers for i3 may still exist, and so we must process
12124 REG_UNUSED notes from that insn.
12126 Any clobbers from i2 or i1 can only exist if they were added by
12127 recog_for_combine. In that case, recog_for_combine created the
12128 necessary REG_UNUSED notes. Trying to keep any original
12129 REG_UNUSED notes from these insns can cause incorrect output
12130 if it is for the same register as the original i3 dest.
12131 In that case, we will notice that the register is set in i3,
12132 and then add a REG_UNUSED note for the destination of i3, which
12133 is wrong. However, it is possible to have REG_UNUSED notes from
12134 i2 or i1 for register which were both used and clobbered, so
12135 we keep notes from i2 or i1 if they will turn into REG_DEAD
12138 /* If this register is set or clobbered in I3, put the note there
12139 unless there is one already. */
12140 if (reg_set_p (XEXP (note, 0), PATTERN (i3)))
12142 if (from_insn != i3)
12145 if (! (GET_CODE (XEXP (note, 0)) == REG
12146 ? find_regno_note (i3, REG_UNUSED, REGNO (XEXP (note, 0)))
12147 : find_reg_note (i3, REG_UNUSED, XEXP (note, 0))))
12150 /* Otherwise, if this register is used by I3, then this register
12151 now dies here, so we must put a REG_DEAD note here unless there
12153 else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3))
12154 && ! (GET_CODE (XEXP (note, 0)) == REG
12155 ? find_regno_note (i3, REG_DEAD,
12156 REGNO (XEXP (note, 0)))
12157 : find_reg_note (i3, REG_DEAD, XEXP (note, 0))))
12159 PUT_REG_NOTE_KIND (note, REG_DEAD);
12167 /* These notes say something about results of an insn. We can
12168 only support them if they used to be on I3 in which case they
12169 remain on I3. Otherwise they are ignored.
12171 If the note refers to an expression that is not a constant, we
12172 must also ignore the note since we cannot tell whether the
12173 equivalence is still true. It might be possible to do
12174 slightly better than this (we only have a problem if I2DEST
12175 or I1DEST is present in the expression), but it doesn't
12176 seem worth the trouble. */
12178 if (from_insn == i3
12179 && (XEXP (note, 0) == 0 || CONSTANT_P (XEXP (note, 0))))
12184 case REG_NO_CONFLICT:
12185 /* These notes say something about how a register is used. They must
12186 be present on any use of the register in I2 or I3. */
12187 if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3)))
12190 if (i2 && reg_mentioned_p (XEXP (note, 0), PATTERN (i2)))
12200 /* This can show up in several ways -- either directly in the
12201 pattern, or hidden off in the constant pool with (or without?)
12202 a REG_EQUAL note. */
12203 /* ??? Ignore the without-reg_equal-note problem for now. */
12204 if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3))
12205 || ((tem = find_reg_note (i3, REG_EQUAL, NULL_RTX))
12206 && GET_CODE (XEXP (tem, 0)) == LABEL_REF
12207 && XEXP (XEXP (tem, 0), 0) == XEXP (note, 0)))
12211 && (reg_mentioned_p (XEXP (note, 0), PATTERN (i2))
12212 || ((tem = find_reg_note (i2, REG_EQUAL, NULL_RTX))
12213 && GET_CODE (XEXP (tem, 0)) == LABEL_REF
12214 && XEXP (XEXP (tem, 0), 0) == XEXP (note, 0))))
12222 /* Don't attach REG_LABEL note to a JUMP_INSN which has
12223 JUMP_LABEL already. Instead, decrement LABEL_NUSES. */
12224 if (place && GET_CODE (place) == JUMP_INSN && JUMP_LABEL (place))
12226 if (JUMP_LABEL (place) != XEXP (note, 0))
12228 if (GET_CODE (JUMP_LABEL (place)) == CODE_LABEL)
12229 LABEL_NUSES (JUMP_LABEL (place))--;
12232 if (place2 && GET_CODE (place2) == JUMP_INSN && JUMP_LABEL (place2))
12234 if (JUMP_LABEL (place2) != XEXP (note, 0))
12236 if (GET_CODE (JUMP_LABEL (place2)) == CODE_LABEL)
12237 LABEL_NUSES (JUMP_LABEL (place2))--;
12244 /* These notes say something about the value of a register prior
12245 to the execution of an insn. It is too much trouble to see
12246 if the note is still correct in all situations. It is better
12247 to simply delete it. */
12251 /* If the insn previously containing this note still exists,
12252 put it back where it was. Otherwise move it to the previous
12253 insn. Adjust the corresponding REG_LIBCALL note. */
12254 if (GET_CODE (from_insn) != NOTE)
12258 tem = find_reg_note (XEXP (note, 0), REG_LIBCALL, NULL_RTX);
12259 place = prev_real_insn (from_insn);
12261 XEXP (tem, 0) = place;
12262 /* If we're deleting the last remaining instruction of a
12263 libcall sequence, don't add the notes. */
12264 else if (XEXP (note, 0) == from_insn)
12270 /* This is handled similarly to REG_RETVAL. */
12271 if (GET_CODE (from_insn) != NOTE)
12275 tem = find_reg_note (XEXP (note, 0), REG_RETVAL, NULL_RTX);
12276 place = next_real_insn (from_insn);
12278 XEXP (tem, 0) = place;
12279 /* If we're deleting the last remaining instruction of a
12280 libcall sequence, don't add the notes. */
12281 else if (XEXP (note, 0) == from_insn)
12287 /* If the register is used as an input in I3, it dies there.
12288 Similarly for I2, if it is non-zero and adjacent to I3.
12290 If the register is not used as an input in either I3 or I2
12291 and it is not one of the registers we were supposed to eliminate,
12292 there are two possibilities. We might have a non-adjacent I2
12293 or we might have somehow eliminated an additional register
12294 from a computation. For example, we might have had A & B where
12295 we discover that B will always be zero. In this case we will
12296 eliminate the reference to A.
12298 In both cases, we must search to see if we can find a previous
12299 use of A and put the death note there. */
12302 && GET_CODE (from_insn) == CALL_INSN
12303 && find_reg_fusage (from_insn, USE, XEXP (note, 0)))
12305 else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3)))
12307 else if (i2 != 0 && next_nonnote_insn (i2) == i3
12308 && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
12311 if (rtx_equal_p (XEXP (note, 0), elim_i2)
12312 || rtx_equal_p (XEXP (note, 0), elim_i1))
12317 basic_block bb = BASIC_BLOCK (this_basic_block);
12319 for (tem = PREV_INSN (i3); place == 0; tem = PREV_INSN (tem))
12321 if (! INSN_P (tem))
12323 if (tem == bb->head)
12328 /* If the register is being set at TEM, see if that is all
12329 TEM is doing. If so, delete TEM. Otherwise, make this
12330 into a REG_UNUSED note instead. */
12331 if (reg_set_p (XEXP (note, 0), PATTERN (tem)))
12333 rtx set = single_set (tem);
12334 rtx inner_dest = 0;
12336 rtx cc0_setter = NULL_RTX;
12340 for (inner_dest = SET_DEST (set);
12341 (GET_CODE (inner_dest) == STRICT_LOW_PART
12342 || GET_CODE (inner_dest) == SUBREG
12343 || GET_CODE (inner_dest) == ZERO_EXTRACT);
12344 inner_dest = XEXP (inner_dest, 0))
12347 /* Verify that it was the set, and not a clobber that
12348 modified the register.
12350 CC0 targets must be careful to maintain setter/user
12351 pairs. If we cannot delete the setter due to side
12352 effects, mark the user with an UNUSED note instead
12355 if (set != 0 && ! side_effects_p (SET_SRC (set))
12356 && rtx_equal_p (XEXP (note, 0), inner_dest)
12358 && (! reg_mentioned_p (cc0_rtx, SET_SRC (set))
12359 || ((cc0_setter = prev_cc0_setter (tem)) != NULL
12360 && sets_cc0_p (PATTERN (cc0_setter)) > 0))
12364 /* Move the notes and links of TEM elsewhere.
12365 This might delete other dead insns recursively.
12366 First set the pattern to something that won't use
12369 PATTERN (tem) = pc_rtx;
12371 distribute_notes (REG_NOTES (tem), tem, tem,
12372 NULL_RTX, NULL_RTX, NULL_RTX);
12373 distribute_links (LOG_LINKS (tem));
12375 PUT_CODE (tem, NOTE);
12376 NOTE_LINE_NUMBER (tem) = NOTE_INSN_DELETED;
12377 NOTE_SOURCE_FILE (tem) = 0;
12380 /* Delete the setter too. */
12383 PATTERN (cc0_setter) = pc_rtx;
12385 distribute_notes (REG_NOTES (cc0_setter),
12386 cc0_setter, cc0_setter,
12387 NULL_RTX, NULL_RTX, NULL_RTX);
12388 distribute_links (LOG_LINKS (cc0_setter));
12390 PUT_CODE (cc0_setter, NOTE);
12391 NOTE_LINE_NUMBER (cc0_setter)
12392 = NOTE_INSN_DELETED;
12393 NOTE_SOURCE_FILE (cc0_setter) = 0;
12397 /* If the register is both set and used here, put the
12398 REG_DEAD note here, but place a REG_UNUSED note
12399 here too unless there already is one. */
12400 else if (reg_referenced_p (XEXP (note, 0),
12405 if (! find_regno_note (tem, REG_UNUSED,
12406 REGNO (XEXP (note, 0))))
12408 = gen_rtx_EXPR_LIST (REG_UNUSED, XEXP (note, 0),
12413 PUT_REG_NOTE_KIND (note, REG_UNUSED);
12415 /* If there isn't already a REG_UNUSED note, put one
12417 if (! find_regno_note (tem, REG_UNUSED,
12418 REGNO (XEXP (note, 0))))
12423 else if (reg_referenced_p (XEXP (note, 0), PATTERN (tem))
12424 || (GET_CODE (tem) == CALL_INSN
12425 && find_reg_fusage (tem, USE, XEXP (note, 0))))
12429 /* If we are doing a 3->2 combination, and we have a
12430 register which formerly died in i3 and was not used
12431 by i2, which now no longer dies in i3 and is used in
12432 i2 but does not die in i2, and place is between i2
12433 and i3, then we may need to move a link from place to
12435 if (i2 && INSN_UID (place) <= max_uid_cuid
12436 && INSN_CUID (place) > INSN_CUID (i2)
12438 && INSN_CUID (from_insn) > INSN_CUID (i2)
12439 && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
12441 rtx links = LOG_LINKS (place);
12442 LOG_LINKS (place) = 0;
12443 distribute_links (links);
12448 if (tem == bb->head)
12452 /* We haven't found an insn for the death note and it
12453 is still a REG_DEAD note, but we have hit the beginning
12454 of the block. If the existing life info says the reg
12455 was dead, there's nothing left to do. Otherwise, we'll
12456 need to do a global life update after combine. */
12457 if (REG_NOTE_KIND (note) == REG_DEAD && place == 0
12458 && REGNO_REG_SET_P (bb->global_live_at_start,
12459 REGNO (XEXP (note, 0))))
12461 SET_BIT (refresh_blocks, this_basic_block);
12466 /* If the register is set or already dead at PLACE, we needn't do
12467 anything with this note if it is still a REG_DEAD note.
12468 We can here if it is set at all, not if is it totally replace,
12469 which is what `dead_or_set_p' checks, so also check for it being
12472 if (place && REG_NOTE_KIND (note) == REG_DEAD)
12474 unsigned int regno = REGNO (XEXP (note, 0));
12476 /* Similarly, if the instruction on which we want to place
12477 the note is a noop, we'll need do a global live update
12478 after we remove them in delete_noop_moves. */
12479 if (noop_move_p (place))
12481 SET_BIT (refresh_blocks, this_basic_block);
12485 if (dead_or_set_p (place, XEXP (note, 0))
12486 || reg_bitfield_target_p (XEXP (note, 0), PATTERN (place)))
12488 /* Unless the register previously died in PLACE, clear
12489 reg_last_death. [I no longer understand why this is
12491 if (reg_last_death[regno] != place)
12492 reg_last_death[regno] = 0;
12496 reg_last_death[regno] = place;
12498 /* If this is a death note for a hard reg that is occupying
12499 multiple registers, ensure that we are still using all
12500 parts of the object. If we find a piece of the object
12501 that is unused, we must arrange for an appropriate REG_DEAD
12502 note to be added for it. However, we can't just emit a USE
12503 and tag the note to it, since the register might actually
12504 be dead; so we recourse, and the recursive call then finds
12505 the previous insn that used this register. */
12507 if (place && regno < FIRST_PSEUDO_REGISTER
12508 && HARD_REGNO_NREGS (regno, GET_MODE (XEXP (note, 0))) > 1)
12510 unsigned int endregno
12511 = regno + HARD_REGNO_NREGS (regno,
12512 GET_MODE (XEXP (note, 0)));
12516 for (i = regno; i < endregno; i++)
12517 if ((! refers_to_regno_p (i, i + 1, PATTERN (place), 0)
12518 && ! find_regno_fusage (place, USE, i))
12519 || dead_or_set_regno_p (place, i))
12524 /* Put only REG_DEAD notes for pieces that are
12525 not already dead or set. */
12527 for (i = regno; i < endregno;
12528 i += HARD_REGNO_NREGS (i, reg_raw_mode[i]))
12530 rtx piece = gen_rtx_REG (reg_raw_mode[i], i);
12531 basic_block bb = BASIC_BLOCK (this_basic_block);
12533 if (! dead_or_set_p (place, piece)
12534 && ! reg_bitfield_target_p (piece,
12538 = gen_rtx_EXPR_LIST (REG_DEAD, piece, NULL_RTX);
12540 distribute_notes (new_note, place, place,
12541 NULL_RTX, NULL_RTX, NULL_RTX);
12543 else if (! refers_to_regno_p (i, i + 1,
12544 PATTERN (place), 0)
12545 && ! find_regno_fusage (place, USE, i))
12546 for (tem = PREV_INSN (place); ;
12547 tem = PREV_INSN (tem))
12549 if (! INSN_P (tem))
12551 if (tem == bb->head)
12553 SET_BIT (refresh_blocks,
12560 if (dead_or_set_p (tem, piece)
12561 || reg_bitfield_target_p (piece,
12565 = gen_rtx_EXPR_LIST (REG_UNUSED, piece,
12580 /* Any other notes should not be present at this point in the
12587 XEXP (note, 1) = REG_NOTES (place);
12588 REG_NOTES (place) = note;
12590 else if ((REG_NOTE_KIND (note) == REG_DEAD
12591 || REG_NOTE_KIND (note) == REG_UNUSED)
12592 && GET_CODE (XEXP (note, 0)) == REG)
12593 REG_N_DEATHS (REGNO (XEXP (note, 0)))--;
12597 if ((REG_NOTE_KIND (note) == REG_DEAD
12598 || REG_NOTE_KIND (note) == REG_UNUSED)
12599 && GET_CODE (XEXP (note, 0)) == REG)
12600 REG_N_DEATHS (REGNO (XEXP (note, 0)))++;
12602 REG_NOTES (place2) = gen_rtx_fmt_ee (GET_CODE (note),
12603 REG_NOTE_KIND (note),
12605 REG_NOTES (place2));
12610 /* Similarly to above, distribute the LOG_LINKS that used to be present on
12611 I3, I2, and I1 to new locations. This is also called in one case to
12612 add a link pointing at I3 when I3's destination is changed. */
12615 distribute_links (links)
12618 rtx link, next_link;
12620 for (link = links; link; link = next_link)
12626 next_link = XEXP (link, 1);
12628 /* If the insn that this link points to is a NOTE or isn't a single
12629 set, ignore it. In the latter case, it isn't clear what we
12630 can do other than ignore the link, since we can't tell which
12631 register it was for. Such links wouldn't be used by combine
12634 It is not possible for the destination of the target of the link to
12635 have been changed by combine. The only potential of this is if we
12636 replace I3, I2, and I1 by I3 and I2. But in that case the
12637 destination of I2 also remains unchanged. */
12639 if (GET_CODE (XEXP (link, 0)) == NOTE
12640 || (set = single_set (XEXP (link, 0))) == 0)
12643 reg = SET_DEST (set);
12644 while (GET_CODE (reg) == SUBREG || GET_CODE (reg) == ZERO_EXTRACT
12645 || GET_CODE (reg) == SIGN_EXTRACT
12646 || GET_CODE (reg) == STRICT_LOW_PART)
12647 reg = XEXP (reg, 0);
12649 /* A LOG_LINK is defined as being placed on the first insn that uses
12650 a register and points to the insn that sets the register. Start
12651 searching at the next insn after the target of the link and stop
12652 when we reach a set of the register or the end of the basic block.
12654 Note that this correctly handles the link that used to point from
12655 I3 to I2. Also note that not much searching is typically done here
12656 since most links don't point very far away. */
12658 for (insn = NEXT_INSN (XEXP (link, 0));
12659 (insn && (this_basic_block == n_basic_blocks - 1
12660 || BLOCK_HEAD (this_basic_block + 1) != insn));
12661 insn = NEXT_INSN (insn))
12662 if (INSN_P (insn) && reg_overlap_mentioned_p (reg, PATTERN (insn)))
12664 if (reg_referenced_p (reg, PATTERN (insn)))
12668 else if (GET_CODE (insn) == CALL_INSN
12669 && find_reg_fusage (insn, USE, reg))
12675 /* If we found a place to put the link, place it there unless there
12676 is already a link to the same insn as LINK at that point. */
12682 for (link2 = LOG_LINKS (place); link2; link2 = XEXP (link2, 1))
12683 if (XEXP (link2, 0) == XEXP (link, 0))
12688 XEXP (link, 1) = LOG_LINKS (place);
12689 LOG_LINKS (place) = link;
12691 /* Set added_links_insn to the earliest insn we added a
12693 if (added_links_insn == 0
12694 || INSN_CUID (added_links_insn) > INSN_CUID (place))
12695 added_links_insn = place;
12701 /* Compute INSN_CUID for INSN, which is an insn made by combine. */
12707 while (insn != 0 && INSN_UID (insn) > max_uid_cuid
12708 && GET_CODE (insn) == INSN && GET_CODE (PATTERN (insn)) == USE)
12709 insn = NEXT_INSN (insn);
12711 if (INSN_UID (insn) > max_uid_cuid)
12714 return INSN_CUID (insn);
12718 dump_combine_stats (file)
12723 ";; Combiner statistics: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n\n",
12724 combine_attempts, combine_merges, combine_extras, combine_successes);
12728 dump_combine_total_stats (file)
12733 "\n;; Combiner totals: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n",
12734 total_attempts, total_merges, total_extras, total_successes);
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