1 /* Optimize by combining instructions for GNU compiler.
2 Copyright (C) 1987, 1988, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010,
4 2011 Free Software Foundation, Inc.
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify it under
9 the terms of the GNU General Public License as published by the Free
10 Software Foundation; either version 3, or (at your option) any later
13 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
14 WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
22 /* This module is essentially the "combiner" phase of the U. of Arizona
23 Portable Optimizer, but redone to work on our list-structured
24 representation for RTL instead of their string representation.
26 The LOG_LINKS of each insn identify the most recent assignment
27 to each REG used in the insn. It is a list of previous insns,
28 each of which contains a SET for a REG that is used in this insn
29 and not used or set in between. LOG_LINKs never cross basic blocks.
30 They were set up by the preceding pass (lifetime analysis).
32 We try to combine each pair of insns joined by a logical link.
33 We also try to combine triples of insns A, B and C when
34 C has a link back to B and B has a link back to A.
36 LOG_LINKS does not have links for use of the CC0. They don't
37 need to, because the insn that sets the CC0 is always immediately
38 before the insn that tests it. So we always regard a branch
39 insn as having a logical link to the preceding insn. The same is true
40 for an insn explicitly using CC0.
42 We check (with use_crosses_set_p) to avoid combining in such a way
43 as to move a computation to a place where its value would be different.
45 Combination is done by mathematically substituting the previous
46 insn(s) values for the regs they set into the expressions in
47 the later insns that refer to these regs. If the result is a valid insn
48 for our target machine, according to the machine description,
49 we install it, delete the earlier insns, and update the data flow
50 information (LOG_LINKS and REG_NOTES) for what we did.
52 There are a few exceptions where the dataflow information isn't
53 completely updated (however this is only a local issue since it is
54 regenerated before the next pass that uses it):
56 - reg_live_length is not updated
57 - reg_n_refs is not adjusted in the rare case when a register is
58 no longer required in a computation
59 - there are extremely rare cases (see distribute_notes) when a
61 - a LOG_LINKS entry that refers to an insn with multiple SETs may be
62 removed because there is no way to know which register it was
65 To simplify substitution, we combine only when the earlier insn(s)
66 consist of only a single assignment. To simplify updating afterward,
67 we never combine when a subroutine call appears in the middle.
69 Since we do not represent assignments to CC0 explicitly except when that
70 is all an insn does, there is no LOG_LINKS entry in an insn that uses
71 the condition code for the insn that set the condition code.
72 Fortunately, these two insns must be consecutive.
73 Therefore, every JUMP_INSN is taken to have an implicit logical link
74 to the preceding insn. This is not quite right, since non-jumps can
75 also use the condition code; but in practice such insns would not
80 #include "coretypes.h"
87 #include "hard-reg-set.h"
88 #include "basic-block.h"
89 #include "insn-config.h"
91 /* Include expr.h after insn-config.h so we get HAVE_conditional_move. */
93 #include "insn-attr.h"
95 #include "diagnostic-core.h"
98 #include "insn-codes.h"
99 #include "rtlhooks-def.h"
100 /* Include output.h for dump_file. */
104 #include "tree-pass.h"
109 /* Number of attempts to combine instructions in this function. */
111 static int combine_attempts;
113 /* Number of attempts that got as far as substitution in this function. */
115 static int combine_merges;
117 /* Number of instructions combined with added SETs in this function. */
119 static int combine_extras;
121 /* Number of instructions combined in this function. */
123 static int combine_successes;
125 /* Totals over entire compilation. */
127 static int total_attempts, total_merges, total_extras, total_successes;
129 /* combine_instructions may try to replace the right hand side of the
130 second instruction with the value of an associated REG_EQUAL note
131 before throwing it at try_combine. That is problematic when there
132 is a REG_DEAD note for a register used in the old right hand side
133 and can cause distribute_notes to do wrong things. This is the
134 second instruction if it has been so modified, null otherwise. */
138 /* When I2MOD is nonnull, this is a copy of the old right hand side. */
140 static rtx i2mod_old_rhs;
142 /* When I2MOD is nonnull, this is a copy of the new right hand side. */
144 static rtx i2mod_new_rhs;
146 typedef struct reg_stat_struct {
147 /* Record last point of death of (hard or pseudo) register n. */
150 /* Record last point of modification of (hard or pseudo) register n. */
153 /* The next group of fields allows the recording of the last value assigned
154 to (hard or pseudo) register n. We use this information to see if an
155 operation being processed is redundant given a prior operation performed
156 on the register. For example, an `and' with a constant is redundant if
157 all the zero bits are already known to be turned off.
159 We use an approach similar to that used by cse, but change it in the
162 (1) We do not want to reinitialize at each label.
163 (2) It is useful, but not critical, to know the actual value assigned
164 to a register. Often just its form is helpful.
166 Therefore, we maintain the following fields:
168 last_set_value the last value assigned
169 last_set_label records the value of label_tick when the
170 register was assigned
171 last_set_table_tick records the value of label_tick when a
172 value using the register is assigned
173 last_set_invalid set to nonzero when it is not valid
174 to use the value of this register in some
177 To understand the usage of these tables, it is important to understand
178 the distinction between the value in last_set_value being valid and
179 the register being validly contained in some other expression in the
182 (The next two parameters are out of date).
184 reg_stat[i].last_set_value is valid if it is nonzero, and either
185 reg_n_sets[i] is 1 or reg_stat[i].last_set_label == label_tick.
187 Register I may validly appear in any expression returned for the value
188 of another register if reg_n_sets[i] is 1. It may also appear in the
189 value for register J if reg_stat[j].last_set_invalid is zero, or
190 reg_stat[i].last_set_label < reg_stat[j].last_set_label.
192 If an expression is found in the table containing a register which may
193 not validly appear in an expression, the register is replaced by
194 something that won't match, (clobber (const_int 0)). */
196 /* Record last value assigned to (hard or pseudo) register n. */
200 /* Record the value of label_tick when an expression involving register n
201 is placed in last_set_value. */
203 int last_set_table_tick;
205 /* Record the value of label_tick when the value for register n is placed in
210 /* These fields are maintained in parallel with last_set_value and are
211 used to store the mode in which the register was last set, the bits
212 that were known to be zero when it was last set, and the number of
213 sign bits copies it was known to have when it was last set. */
215 unsigned HOST_WIDE_INT last_set_nonzero_bits;
216 char last_set_sign_bit_copies;
217 ENUM_BITFIELD(machine_mode) last_set_mode : 8;
219 /* Set nonzero if references to register n in expressions should not be
220 used. last_set_invalid is set nonzero when this register is being
221 assigned to and last_set_table_tick == label_tick. */
223 char last_set_invalid;
225 /* Some registers that are set more than once and used in more than one
226 basic block are nevertheless always set in similar ways. For example,
227 a QImode register may be loaded from memory in two places on a machine
228 where byte loads zero extend.
230 We record in the following fields if a register has some leading bits
231 that are always equal to the sign bit, and what we know about the
232 nonzero bits of a register, specifically which bits are known to be
235 If an entry is zero, it means that we don't know anything special. */
237 unsigned char sign_bit_copies;
239 unsigned HOST_WIDE_INT nonzero_bits;
241 /* Record the value of the label_tick when the last truncation
242 happened. The field truncated_to_mode is only valid if
243 truncation_label == label_tick. */
245 int truncation_label;
247 /* Record the last truncation seen for this register. If truncation
248 is not a nop to this mode we might be able to save an explicit
249 truncation if we know that value already contains a truncated
252 ENUM_BITFIELD(machine_mode) truncated_to_mode : 8;
255 DEF_VEC_O(reg_stat_type);
256 DEF_VEC_ALLOC_O(reg_stat_type,heap);
258 static VEC(reg_stat_type,heap) *reg_stat;
260 /* Record the luid of the last insn that invalidated memory
261 (anything that writes memory, and subroutine calls, but not pushes). */
263 static int mem_last_set;
265 /* Record the luid of the last CALL_INSN
266 so we can tell whether a potential combination crosses any calls. */
268 static int last_call_luid;
270 /* When `subst' is called, this is the insn that is being modified
271 (by combining in a previous insn). The PATTERN of this insn
272 is still the old pattern partially modified and it should not be
273 looked at, but this may be used to examine the successors of the insn
274 to judge whether a simplification is valid. */
276 static rtx subst_insn;
278 /* This is the lowest LUID that `subst' is currently dealing with.
279 get_last_value will not return a value if the register was set at or
280 after this LUID. If not for this mechanism, we could get confused if
281 I2 or I1 in try_combine were an insn that used the old value of a register
282 to obtain a new value. In that case, we might erroneously get the
283 new value of the register when we wanted the old one. */
285 static int subst_low_luid;
287 /* This contains any hard registers that are used in newpat; reg_dead_at_p
288 must consider all these registers to be always live. */
290 static HARD_REG_SET newpat_used_regs;
292 /* This is an insn to which a LOG_LINKS entry has been added. If this
293 insn is the earlier than I2 or I3, combine should rescan starting at
296 static rtx added_links_insn;
298 /* Basic block in which we are performing combines. */
299 static basic_block this_basic_block;
300 static bool optimize_this_for_speed_p;
303 /* Length of the currently allocated uid_insn_cost array. */
305 static int max_uid_known;
307 /* The following array records the insn_rtx_cost for every insn
308 in the instruction stream. */
310 static int *uid_insn_cost;
312 /* The following array records the LOG_LINKS for every insn in the
313 instruction stream as struct insn_link pointers. */
317 struct insn_link *next;
320 static struct insn_link **uid_log_links;
322 #define INSN_COST(INSN) (uid_insn_cost[INSN_UID (INSN)])
323 #define LOG_LINKS(INSN) (uid_log_links[INSN_UID (INSN)])
325 #define FOR_EACH_LOG_LINK(L, INSN) \
326 for ((L) = LOG_LINKS (INSN); (L); (L) = (L)->next)
328 /* Links for LOG_LINKS are allocated from this obstack. */
330 static struct obstack insn_link_obstack;
332 /* Allocate a link. */
334 static inline struct insn_link *
335 alloc_insn_link (rtx insn, struct insn_link *next)
338 = (struct insn_link *) obstack_alloc (&insn_link_obstack,
339 sizeof (struct insn_link));
345 /* Incremented for each basic block. */
347 static int label_tick;
349 /* Reset to label_tick for each extended basic block in scanning order. */
351 static int label_tick_ebb_start;
353 /* Mode used to compute significance in reg_stat[].nonzero_bits. It is the
354 largest integer mode that can fit in HOST_BITS_PER_WIDE_INT. */
356 static enum machine_mode nonzero_bits_mode;
358 /* Nonzero when reg_stat[].nonzero_bits and reg_stat[].sign_bit_copies can
359 be safely used. It is zero while computing them and after combine has
360 completed. This former test prevents propagating values based on
361 previously set values, which can be incorrect if a variable is modified
364 static int nonzero_sign_valid;
367 /* Record one modification to rtl structure
368 to be undone by storing old_contents into *where. */
370 enum undo_kind { UNDO_RTX, UNDO_INT, UNDO_MODE };
376 union { rtx r; int i; enum machine_mode m; } old_contents;
377 union { rtx *r; int *i; } where;
380 /* Record a bunch of changes to be undone, up to MAX_UNDO of them.
381 num_undo says how many are currently recorded.
383 other_insn is nonzero if we have modified some other insn in the process
384 of working on subst_insn. It must be verified too. */
393 static struct undobuf undobuf;
395 /* Number of times the pseudo being substituted for
396 was found and replaced. */
398 static int n_occurrences;
400 static rtx reg_nonzero_bits_for_combine (const_rtx, enum machine_mode, const_rtx,
402 unsigned HOST_WIDE_INT,
403 unsigned HOST_WIDE_INT *);
404 static rtx reg_num_sign_bit_copies_for_combine (const_rtx, enum machine_mode, const_rtx,
406 unsigned int, unsigned int *);
407 static void do_SUBST (rtx *, rtx);
408 static void do_SUBST_INT (int *, int);
409 static void init_reg_last (void);
410 static void setup_incoming_promotions (rtx);
411 static void set_nonzero_bits_and_sign_copies (rtx, const_rtx, void *);
412 static int cant_combine_insn_p (rtx);
413 static int can_combine_p (rtx, rtx, rtx, rtx, rtx, rtx, rtx *, rtx *);
414 static int combinable_i3pat (rtx, rtx *, rtx, rtx, rtx, int, int, rtx *);
415 static int contains_muldiv (rtx);
416 static rtx try_combine (rtx, rtx, rtx, rtx, int *, rtx);
417 static void undo_all (void);
418 static void undo_commit (void);
419 static rtx *find_split_point (rtx *, rtx, bool);
420 static rtx subst (rtx, rtx, rtx, int, int);
421 static rtx combine_simplify_rtx (rtx, enum machine_mode, int);
422 static rtx simplify_if_then_else (rtx);
423 static rtx simplify_set (rtx);
424 static rtx simplify_logical (rtx);
425 static rtx expand_compound_operation (rtx);
426 static const_rtx expand_field_assignment (const_rtx);
427 static rtx make_extraction (enum machine_mode, rtx, HOST_WIDE_INT,
428 rtx, unsigned HOST_WIDE_INT, int, int, int);
429 static rtx extract_left_shift (rtx, int);
430 static rtx make_compound_operation (rtx, enum rtx_code);
431 static int get_pos_from_mask (unsigned HOST_WIDE_INT,
432 unsigned HOST_WIDE_INT *);
433 static rtx canon_reg_for_combine (rtx, rtx);
434 static rtx force_to_mode (rtx, enum machine_mode,
435 unsigned HOST_WIDE_INT, int);
436 static rtx if_then_else_cond (rtx, rtx *, rtx *);
437 static rtx known_cond (rtx, enum rtx_code, rtx, rtx);
438 static int rtx_equal_for_field_assignment_p (rtx, rtx);
439 static rtx make_field_assignment (rtx);
440 static rtx apply_distributive_law (rtx);
441 static rtx distribute_and_simplify_rtx (rtx, int);
442 static rtx simplify_and_const_int_1 (enum machine_mode, rtx,
443 unsigned HOST_WIDE_INT);
444 static rtx simplify_and_const_int (rtx, enum machine_mode, rtx,
445 unsigned HOST_WIDE_INT);
446 static int merge_outer_ops (enum rtx_code *, HOST_WIDE_INT *, enum rtx_code,
447 HOST_WIDE_INT, enum machine_mode, int *);
448 static rtx simplify_shift_const_1 (enum rtx_code, enum machine_mode, rtx, int);
449 static rtx simplify_shift_const (rtx, enum rtx_code, enum machine_mode, rtx,
451 static int recog_for_combine (rtx *, rtx, rtx *);
452 static rtx gen_lowpart_for_combine (enum machine_mode, rtx);
453 static enum rtx_code simplify_comparison (enum rtx_code, rtx *, rtx *);
454 static void update_table_tick (rtx);
455 static void record_value_for_reg (rtx, rtx, rtx);
456 static void check_promoted_subreg (rtx, rtx);
457 static void record_dead_and_set_regs_1 (rtx, const_rtx, void *);
458 static void record_dead_and_set_regs (rtx);
459 static int get_last_value_validate (rtx *, rtx, int, int);
460 static rtx get_last_value (const_rtx);
461 static int use_crosses_set_p (const_rtx, int);
462 static void reg_dead_at_p_1 (rtx, const_rtx, void *);
463 static int reg_dead_at_p (rtx, rtx);
464 static void move_deaths (rtx, rtx, int, rtx, rtx *);
465 static int reg_bitfield_target_p (rtx, rtx);
466 static void distribute_notes (rtx, rtx, rtx, rtx, rtx, rtx, rtx);
467 static void distribute_links (struct insn_link *);
468 static void mark_used_regs_combine (rtx);
469 static void record_promoted_value (rtx, rtx);
470 static int unmentioned_reg_p_1 (rtx *, void *);
471 static bool unmentioned_reg_p (rtx, rtx);
472 static int record_truncated_value (rtx *, void *);
473 static void record_truncated_values (rtx *, void *);
474 static bool reg_truncated_to_mode (enum machine_mode, const_rtx);
475 static rtx gen_lowpart_or_truncate (enum machine_mode, rtx);
478 /* It is not safe to use ordinary gen_lowpart in combine.
479 See comments in gen_lowpart_for_combine. */
480 #undef RTL_HOOKS_GEN_LOWPART
481 #define RTL_HOOKS_GEN_LOWPART gen_lowpart_for_combine
483 /* Our implementation of gen_lowpart never emits a new pseudo. */
484 #undef RTL_HOOKS_GEN_LOWPART_NO_EMIT
485 #define RTL_HOOKS_GEN_LOWPART_NO_EMIT gen_lowpart_for_combine
487 #undef RTL_HOOKS_REG_NONZERO_REG_BITS
488 #define RTL_HOOKS_REG_NONZERO_REG_BITS reg_nonzero_bits_for_combine
490 #undef RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES
491 #define RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES reg_num_sign_bit_copies_for_combine
493 #undef RTL_HOOKS_REG_TRUNCATED_TO_MODE
494 #define RTL_HOOKS_REG_TRUNCATED_TO_MODE reg_truncated_to_mode
496 static const struct rtl_hooks combine_rtl_hooks = RTL_HOOKS_INITIALIZER;
499 /* Try to split PATTERN found in INSN. This returns NULL_RTX if
500 PATTERN can not be split. Otherwise, it returns an insn sequence.
501 This is a wrapper around split_insns which ensures that the
502 reg_stat vector is made larger if the splitter creates a new
506 combine_split_insns (rtx pattern, rtx insn)
511 ret = split_insns (pattern, insn);
512 nregs = max_reg_num ();
513 if (nregs > VEC_length (reg_stat_type, reg_stat))
514 VEC_safe_grow_cleared (reg_stat_type, heap, reg_stat, nregs);
518 /* This is used by find_single_use to locate an rtx in LOC that
519 contains exactly one use of DEST, which is typically either a REG
520 or CC0. It returns a pointer to the innermost rtx expression
521 containing DEST. Appearances of DEST that are being used to
522 totally replace it are not counted. */
525 find_single_use_1 (rtx dest, rtx *loc)
528 enum rtx_code code = GET_CODE (x);
546 /* If the destination is anything other than CC0, PC, a REG or a SUBREG
547 of a REG that occupies all of the REG, the insn uses DEST if
548 it is mentioned in the destination or the source. Otherwise, we
549 need just check the source. */
550 if (GET_CODE (SET_DEST (x)) != CC0
551 && GET_CODE (SET_DEST (x)) != PC
552 && !REG_P (SET_DEST (x))
553 && ! (GET_CODE (SET_DEST (x)) == SUBREG
554 && REG_P (SUBREG_REG (SET_DEST (x)))
555 && (((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x))))
556 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
557 == ((GET_MODE_SIZE (GET_MODE (SET_DEST (x)))
558 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD))))
561 return find_single_use_1 (dest, &SET_SRC (x));
565 return find_single_use_1 (dest, &XEXP (x, 0));
571 /* If it wasn't one of the common cases above, check each expression and
572 vector of this code. Look for a unique usage of DEST. */
574 fmt = GET_RTX_FORMAT (code);
575 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
579 if (dest == XEXP (x, i)
580 || (REG_P (dest) && REG_P (XEXP (x, i))
581 && REGNO (dest) == REGNO (XEXP (x, i))))
584 this_result = find_single_use_1 (dest, &XEXP (x, i));
587 result = this_result;
588 else if (this_result)
589 /* Duplicate usage. */
592 else if (fmt[i] == 'E')
596 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
598 if (XVECEXP (x, i, j) == dest
600 && REG_P (XVECEXP (x, i, j))
601 && REGNO (XVECEXP (x, i, j)) == REGNO (dest)))
604 this_result = find_single_use_1 (dest, &XVECEXP (x, i, j));
607 result = this_result;
608 else if (this_result)
618 /* See if DEST, produced in INSN, is used only a single time in the
619 sequel. If so, return a pointer to the innermost rtx expression in which
622 If PLOC is nonzero, *PLOC is set to the insn containing the single use.
624 If DEST is cc0_rtx, we look only at the next insn. In that case, we don't
625 care about REG_DEAD notes or LOG_LINKS.
627 Otherwise, we find the single use by finding an insn that has a
628 LOG_LINKS pointing at INSN and has a REG_DEAD note for DEST. If DEST is
629 only referenced once in that insn, we know that it must be the first
630 and last insn referencing DEST. */
633 find_single_use (rtx dest, rtx insn, rtx *ploc)
638 struct insn_link *link;
643 next = NEXT_INSN (insn);
645 || (!NONJUMP_INSN_P (next) && !JUMP_P (next)))
648 result = find_single_use_1 (dest, &PATTERN (next));
658 bb = BLOCK_FOR_INSN (insn);
659 for (next = NEXT_INSN (insn);
660 next && BLOCK_FOR_INSN (next) == bb;
661 next = NEXT_INSN (next))
662 if (INSN_P (next) && dead_or_set_p (next, dest))
664 FOR_EACH_LOG_LINK (link, next)
665 if (link->insn == insn)
670 result = find_single_use_1 (dest, &PATTERN (next));
680 /* Substitute NEWVAL, an rtx expression, into INTO, a place in some
681 insn. The substitution can be undone by undo_all. If INTO is already
682 set to NEWVAL, do not record this change. Because computing NEWVAL might
683 also call SUBST, we have to compute it before we put anything into
687 do_SUBST (rtx *into, rtx newval)
692 if (oldval == newval)
695 /* We'd like to catch as many invalid transformations here as
696 possible. Unfortunately, there are way too many mode changes
697 that are perfectly valid, so we'd waste too much effort for
698 little gain doing the checks here. Focus on catching invalid
699 transformations involving integer constants. */
700 if (GET_MODE_CLASS (GET_MODE (oldval)) == MODE_INT
701 && CONST_INT_P (newval))
703 /* Sanity check that we're replacing oldval with a CONST_INT
704 that is a valid sign-extension for the original mode. */
705 gcc_assert (INTVAL (newval)
706 == trunc_int_for_mode (INTVAL (newval), GET_MODE (oldval)));
708 /* Replacing the operand of a SUBREG or a ZERO_EXTEND with a
709 CONST_INT is not valid, because after the replacement, the
710 original mode would be gone. Unfortunately, we can't tell
711 when do_SUBST is called to replace the operand thereof, so we
712 perform this test on oldval instead, checking whether an
713 invalid replacement took place before we got here. */
714 gcc_assert (!(GET_CODE (oldval) == SUBREG
715 && CONST_INT_P (SUBREG_REG (oldval))));
716 gcc_assert (!(GET_CODE (oldval) == ZERO_EXTEND
717 && CONST_INT_P (XEXP (oldval, 0))));
721 buf = undobuf.frees, undobuf.frees = buf->next;
723 buf = XNEW (struct undo);
725 buf->kind = UNDO_RTX;
727 buf->old_contents.r = oldval;
730 buf->next = undobuf.undos, undobuf.undos = buf;
733 #define SUBST(INTO, NEWVAL) do_SUBST(&(INTO), (NEWVAL))
735 /* Similar to SUBST, but NEWVAL is an int expression. Note that substitution
736 for the value of a HOST_WIDE_INT value (including CONST_INT) is
740 do_SUBST_INT (int *into, int newval)
745 if (oldval == newval)
749 buf = undobuf.frees, undobuf.frees = buf->next;
751 buf = XNEW (struct undo);
753 buf->kind = UNDO_INT;
755 buf->old_contents.i = oldval;
758 buf->next = undobuf.undos, undobuf.undos = buf;
761 #define SUBST_INT(INTO, NEWVAL) do_SUBST_INT(&(INTO), (NEWVAL))
763 /* Similar to SUBST, but just substitute the mode. This is used when
764 changing the mode of a pseudo-register, so that any other
765 references to the entry in the regno_reg_rtx array will change as
769 do_SUBST_MODE (rtx *into, enum machine_mode newval)
772 enum machine_mode oldval = GET_MODE (*into);
774 if (oldval == newval)
778 buf = undobuf.frees, undobuf.frees = buf->next;
780 buf = XNEW (struct undo);
782 buf->kind = UNDO_MODE;
784 buf->old_contents.m = oldval;
785 adjust_reg_mode (*into, newval);
787 buf->next = undobuf.undos, undobuf.undos = buf;
790 #define SUBST_MODE(INTO, NEWVAL) do_SUBST_MODE(&(INTO), (NEWVAL))
792 /* Subroutine of try_combine. Determine whether the replacement patterns
793 NEWPAT, NEWI2PAT and NEWOTHERPAT are cheaper according to insn_rtx_cost
794 than the original sequence I0, I1, I2, I3 and undobuf.other_insn. Note
795 that I0, I1 and/or NEWI2PAT may be NULL_RTX. Similarly, NEWOTHERPAT and
796 undobuf.other_insn may also both be NULL_RTX. Return false if the cost
797 of all the instructions can be estimated and the replacements are more
798 expensive than the original sequence. */
801 combine_validate_cost (rtx i0, rtx i1, rtx i2, rtx i3, rtx newpat,
802 rtx newi2pat, rtx newotherpat)
804 int i0_cost, i1_cost, i2_cost, i3_cost;
805 int new_i2_cost, new_i3_cost;
806 int old_cost, new_cost;
808 /* Lookup the original insn_rtx_costs. */
809 i2_cost = INSN_COST (i2);
810 i3_cost = INSN_COST (i3);
814 i1_cost = INSN_COST (i1);
817 i0_cost = INSN_COST (i0);
818 old_cost = (i0_cost > 0 && i1_cost > 0 && i2_cost > 0 && i3_cost > 0
819 ? i0_cost + i1_cost + i2_cost + i3_cost : 0);
823 old_cost = (i1_cost > 0 && i2_cost > 0 && i3_cost > 0
824 ? i1_cost + i2_cost + i3_cost : 0);
830 old_cost = (i2_cost > 0 && i3_cost > 0) ? i2_cost + i3_cost : 0;
831 i1_cost = i0_cost = 0;
834 /* Calculate the replacement insn_rtx_costs. */
835 new_i3_cost = insn_rtx_cost (newpat, optimize_this_for_speed_p);
838 new_i2_cost = insn_rtx_cost (newi2pat, optimize_this_for_speed_p);
839 new_cost = (new_i2_cost > 0 && new_i3_cost > 0)
840 ? new_i2_cost + new_i3_cost : 0;
844 new_cost = new_i3_cost;
848 if (undobuf.other_insn)
850 int old_other_cost, new_other_cost;
852 old_other_cost = INSN_COST (undobuf.other_insn);
853 new_other_cost = insn_rtx_cost (newotherpat, optimize_this_for_speed_p);
854 if (old_other_cost > 0 && new_other_cost > 0)
856 old_cost += old_other_cost;
857 new_cost += new_other_cost;
863 /* Disallow this combination if both new_cost and old_cost are greater than
864 zero, and new_cost is greater than old cost. */
865 if (old_cost > 0 && new_cost > old_cost)
872 "rejecting combination of insns %d, %d, %d and %d\n",
873 INSN_UID (i0), INSN_UID (i1), INSN_UID (i2),
875 fprintf (dump_file, "original costs %d + %d + %d + %d = %d\n",
876 i0_cost, i1_cost, i2_cost, i3_cost, old_cost);
881 "rejecting combination of insns %d, %d and %d\n",
882 INSN_UID (i1), INSN_UID (i2), INSN_UID (i3));
883 fprintf (dump_file, "original costs %d + %d + %d = %d\n",
884 i1_cost, i2_cost, i3_cost, old_cost);
889 "rejecting combination of insns %d and %d\n",
890 INSN_UID (i2), INSN_UID (i3));
891 fprintf (dump_file, "original costs %d + %d = %d\n",
892 i2_cost, i3_cost, old_cost);
897 fprintf (dump_file, "replacement costs %d + %d = %d\n",
898 new_i2_cost, new_i3_cost, new_cost);
901 fprintf (dump_file, "replacement cost %d\n", new_cost);
907 /* Update the uid_insn_cost array with the replacement costs. */
908 INSN_COST (i2) = new_i2_cost;
909 INSN_COST (i3) = new_i3_cost;
921 /* Delete any insns that copy a register to itself. */
924 delete_noop_moves (void)
931 for (insn = BB_HEAD (bb); insn != NEXT_INSN (BB_END (bb)); insn = next)
933 next = NEXT_INSN (insn);
934 if (INSN_P (insn) && noop_move_p (insn))
937 fprintf (dump_file, "deleting noop move %d\n", INSN_UID (insn));
939 delete_insn_and_edges (insn);
946 /* Fill in log links field for all insns. */
949 create_log_links (void)
953 df_ref *def_vec, *use_vec;
955 next_use = XCNEWVEC (rtx, max_reg_num ());
957 /* Pass through each block from the end, recording the uses of each
958 register and establishing log links when def is encountered.
959 Note that we do not clear next_use array in order to save time,
960 so we have to test whether the use is in the same basic block as def.
962 There are a few cases below when we do not consider the definition or
963 usage -- these are taken from original flow.c did. Don't ask me why it is
964 done this way; I don't know and if it works, I don't want to know. */
968 FOR_BB_INSNS_REVERSE (bb, insn)
970 if (!NONDEBUG_INSN_P (insn))
973 /* Log links are created only once. */
974 gcc_assert (!LOG_LINKS (insn));
976 for (def_vec = DF_INSN_DEFS (insn); *def_vec; def_vec++)
978 df_ref def = *def_vec;
979 int regno = DF_REF_REGNO (def);
982 if (!next_use[regno])
985 /* Do not consider if it is pre/post modification in MEM. */
986 if (DF_REF_FLAGS (def) & DF_REF_PRE_POST_MODIFY)
989 /* Do not make the log link for frame pointer. */
990 if ((regno == FRAME_POINTER_REGNUM
991 && (! reload_completed || frame_pointer_needed))
992 #if !HARD_FRAME_POINTER_IS_FRAME_POINTER
993 || (regno == HARD_FRAME_POINTER_REGNUM
994 && (! reload_completed || frame_pointer_needed))
996 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
997 || (regno == ARG_POINTER_REGNUM && fixed_regs[regno])
1002 use_insn = next_use[regno];
1003 if (BLOCK_FOR_INSN (use_insn) == bb)
1007 We don't build a LOG_LINK for hard registers contained
1008 in ASM_OPERANDs. If these registers get replaced,
1009 we might wind up changing the semantics of the insn,
1010 even if reload can make what appear to be valid
1011 assignments later. */
1012 if (regno >= FIRST_PSEUDO_REGISTER
1013 || asm_noperands (PATTERN (use_insn)) < 0)
1015 /* Don't add duplicate links between instructions. */
1016 struct insn_link *links;
1017 FOR_EACH_LOG_LINK (links, use_insn)
1018 if (insn == links->insn)
1022 LOG_LINKS (use_insn)
1023 = alloc_insn_link (insn, LOG_LINKS (use_insn));
1026 next_use[regno] = NULL_RTX;
1029 for (use_vec = DF_INSN_USES (insn); *use_vec; use_vec++)
1031 df_ref use = *use_vec;
1032 int regno = DF_REF_REGNO (use);
1034 /* Do not consider the usage of the stack pointer
1035 by function call. */
1036 if (DF_REF_FLAGS (use) & DF_REF_CALL_STACK_USAGE)
1039 next_use[regno] = insn;
1047 /* Walk the LOG_LINKS of insn B to see if we find a reference to A. Return
1048 true if we found a LOG_LINK that proves that A feeds B. This only works
1049 if there are no instructions between A and B which could have a link
1050 depending on A, since in that case we would not record a link for B.
1051 We also check the implicit dependency created by a cc0 setter/user
1055 insn_a_feeds_b (rtx a, rtx b)
1057 struct insn_link *links;
1058 FOR_EACH_LOG_LINK (links, b)
1059 if (links->insn == a)
1068 /* Main entry point for combiner. F is the first insn of the function.
1069 NREGS is the first unused pseudo-reg number.
1071 Return nonzero if the combiner has turned an indirect jump
1072 instruction into a direct jump. */
1074 combine_instructions (rtx f, unsigned int nregs)
1080 struct insn_link *links, *nextlinks;
1082 basic_block last_bb;
1084 int new_direct_jump_p = 0;
1086 for (first = f; first && !INSN_P (first); )
1087 first = NEXT_INSN (first);
1091 combine_attempts = 0;
1094 combine_successes = 0;
1096 rtl_hooks = combine_rtl_hooks;
1098 VEC_safe_grow_cleared (reg_stat_type, heap, reg_stat, nregs);
1100 init_recog_no_volatile ();
1102 /* Allocate array for insn info. */
1103 max_uid_known = get_max_uid ();
1104 uid_log_links = XCNEWVEC (struct insn_link *, max_uid_known + 1);
1105 uid_insn_cost = XCNEWVEC (int, max_uid_known + 1);
1106 gcc_obstack_init (&insn_link_obstack);
1108 nonzero_bits_mode = mode_for_size (HOST_BITS_PER_WIDE_INT, MODE_INT, 0);
1110 /* Don't use reg_stat[].nonzero_bits when computing it. This can cause
1111 problems when, for example, we have j <<= 1 in a loop. */
1113 nonzero_sign_valid = 0;
1114 label_tick = label_tick_ebb_start = 1;
1116 /* Scan all SETs and see if we can deduce anything about what
1117 bits are known to be zero for some registers and how many copies
1118 of the sign bit are known to exist for those registers.
1120 Also set any known values so that we can use it while searching
1121 for what bits are known to be set. */
1123 setup_incoming_promotions (first);
1124 /* Allow the entry block and the first block to fall into the same EBB.
1125 Conceptually the incoming promotions are assigned to the entry block. */
1126 last_bb = ENTRY_BLOCK_PTR;
1128 create_log_links ();
1129 FOR_EACH_BB (this_basic_block)
1131 optimize_this_for_speed_p = optimize_bb_for_speed_p (this_basic_block);
1136 if (!single_pred_p (this_basic_block)
1137 || single_pred (this_basic_block) != last_bb)
1138 label_tick_ebb_start = label_tick;
1139 last_bb = this_basic_block;
1141 FOR_BB_INSNS (this_basic_block, insn)
1142 if (INSN_P (insn) && BLOCK_FOR_INSN (insn))
1148 subst_low_luid = DF_INSN_LUID (insn);
1151 note_stores (PATTERN (insn), set_nonzero_bits_and_sign_copies,
1153 record_dead_and_set_regs (insn);
1156 for (links = REG_NOTES (insn); links; links = XEXP (links, 1))
1157 if (REG_NOTE_KIND (links) == REG_INC)
1158 set_nonzero_bits_and_sign_copies (XEXP (links, 0), NULL_RTX,
1162 /* Record the current insn_rtx_cost of this instruction. */
1163 if (NONJUMP_INSN_P (insn))
1164 INSN_COST (insn) = insn_rtx_cost (PATTERN (insn),
1165 optimize_this_for_speed_p);
1167 fprintf(dump_file, "insn_cost %d: %d\n",
1168 INSN_UID (insn), INSN_COST (insn));
1172 nonzero_sign_valid = 1;
1174 /* Now scan all the insns in forward order. */
1175 label_tick = label_tick_ebb_start = 1;
1177 setup_incoming_promotions (first);
1178 last_bb = ENTRY_BLOCK_PTR;
1180 FOR_EACH_BB (this_basic_block)
1182 rtx last_combined_insn = NULL_RTX;
1183 optimize_this_for_speed_p = optimize_bb_for_speed_p (this_basic_block);
1188 if (!single_pred_p (this_basic_block)
1189 || single_pred (this_basic_block) != last_bb)
1190 label_tick_ebb_start = label_tick;
1191 last_bb = this_basic_block;
1193 rtl_profile_for_bb (this_basic_block);
1194 for (insn = BB_HEAD (this_basic_block);
1195 insn != NEXT_INSN (BB_END (this_basic_block));
1196 insn = next ? next : NEXT_INSN (insn))
1199 if (NONDEBUG_INSN_P (insn))
1201 while (last_combined_insn
1202 && INSN_DELETED_P (last_combined_insn))
1203 last_combined_insn = PREV_INSN (last_combined_insn);
1204 if (last_combined_insn == NULL_RTX
1205 || BARRIER_P (last_combined_insn)
1206 || BLOCK_FOR_INSN (last_combined_insn) != this_basic_block
1207 || DF_INSN_LUID (last_combined_insn) <= DF_INSN_LUID (insn))
1208 last_combined_insn = insn;
1210 /* See if we know about function return values before this
1211 insn based upon SUBREG flags. */
1212 check_promoted_subreg (insn, PATTERN (insn));
1214 /* See if we can find hardregs and subreg of pseudos in
1215 narrower modes. This could help turning TRUNCATEs
1217 note_uses (&PATTERN (insn), record_truncated_values, NULL);
1219 /* Try this insn with each insn it links back to. */
1221 FOR_EACH_LOG_LINK (links, insn)
1222 if ((next = try_combine (insn, links->insn, NULL_RTX,
1223 NULL_RTX, &new_direct_jump_p,
1224 last_combined_insn)) != 0)
1227 /* Try each sequence of three linked insns ending with this one. */
1229 FOR_EACH_LOG_LINK (links, insn)
1231 rtx link = links->insn;
1233 /* If the linked insn has been replaced by a note, then there
1234 is no point in pursuing this chain any further. */
1238 FOR_EACH_LOG_LINK (nextlinks, link)
1239 if ((next = try_combine (insn, link, nextlinks->insn,
1240 NULL_RTX, &new_direct_jump_p,
1241 last_combined_insn)) != 0)
1246 /* Try to combine a jump insn that uses CC0
1247 with a preceding insn that sets CC0, and maybe with its
1248 logical predecessor as well.
1249 This is how we make decrement-and-branch insns.
1250 We need this special code because data flow connections
1251 via CC0 do not get entered in LOG_LINKS. */
1254 && (prev = prev_nonnote_insn (insn)) != 0
1255 && NONJUMP_INSN_P (prev)
1256 && sets_cc0_p (PATTERN (prev)))
1258 if ((next = try_combine (insn, prev, NULL_RTX, NULL_RTX,
1260 last_combined_insn)) != 0)
1263 FOR_EACH_LOG_LINK (nextlinks, prev)
1264 if ((next = try_combine (insn, prev, nextlinks->insn,
1265 NULL_RTX, &new_direct_jump_p,
1266 last_combined_insn)) != 0)
1270 /* Do the same for an insn that explicitly references CC0. */
1271 if (NONJUMP_INSN_P (insn)
1272 && (prev = prev_nonnote_insn (insn)) != 0
1273 && NONJUMP_INSN_P (prev)
1274 && sets_cc0_p (PATTERN (prev))
1275 && GET_CODE (PATTERN (insn)) == SET
1276 && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (insn))))
1278 if ((next = try_combine (insn, prev, NULL_RTX, NULL_RTX,
1280 last_combined_insn)) != 0)
1283 FOR_EACH_LOG_LINK (nextlinks, prev)
1284 if ((next = try_combine (insn, prev, nextlinks->insn,
1285 NULL_RTX, &new_direct_jump_p,
1286 last_combined_insn)) != 0)
1290 /* Finally, see if any of the insns that this insn links to
1291 explicitly references CC0. If so, try this insn, that insn,
1292 and its predecessor if it sets CC0. */
1293 FOR_EACH_LOG_LINK (links, insn)
1294 if (NONJUMP_INSN_P (links->insn)
1295 && GET_CODE (PATTERN (links->insn)) == SET
1296 && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (links->insn)))
1297 && (prev = prev_nonnote_insn (links->insn)) != 0
1298 && NONJUMP_INSN_P (prev)
1299 && sets_cc0_p (PATTERN (prev))
1300 && (next = try_combine (insn, links->insn,
1301 prev, NULL_RTX, &new_direct_jump_p,
1302 last_combined_insn)) != 0)
1306 /* Try combining an insn with two different insns whose results it
1308 FOR_EACH_LOG_LINK (links, insn)
1309 for (nextlinks = links->next; nextlinks;
1310 nextlinks = nextlinks->next)
1311 if ((next = try_combine (insn, links->insn,
1312 nextlinks->insn, NULL_RTX,
1314 last_combined_insn)) != 0)
1317 /* Try four-instruction combinations. */
1318 FOR_EACH_LOG_LINK (links, insn)
1320 struct insn_link *next1;
1321 rtx link = links->insn;
1323 /* If the linked insn has been replaced by a note, then there
1324 is no point in pursuing this chain any further. */
1328 FOR_EACH_LOG_LINK (next1, link)
1330 rtx link1 = next1->insn;
1333 /* I0 -> I1 -> I2 -> I3. */
1334 FOR_EACH_LOG_LINK (nextlinks, link1)
1335 if ((next = try_combine (insn, link, link1,
1338 last_combined_insn)) != 0)
1340 /* I0, I1 -> I2, I2 -> I3. */
1341 for (nextlinks = next1->next; nextlinks;
1342 nextlinks = nextlinks->next)
1343 if ((next = try_combine (insn, link, link1,
1346 last_combined_insn)) != 0)
1350 for (next1 = links->next; next1; next1 = next1->next)
1352 rtx link1 = next1->insn;
1355 /* I0 -> I2; I1, I2 -> I3. */
1356 FOR_EACH_LOG_LINK (nextlinks, link)
1357 if ((next = try_combine (insn, link, link1,
1360 last_combined_insn)) != 0)
1362 /* I0 -> I1; I1, I2 -> I3. */
1363 FOR_EACH_LOG_LINK (nextlinks, link1)
1364 if ((next = try_combine (insn, link, link1,
1367 last_combined_insn)) != 0)
1372 /* Try this insn with each REG_EQUAL note it links back to. */
1373 FOR_EACH_LOG_LINK (links, insn)
1376 rtx temp = links->insn;
1377 if ((set = single_set (temp)) != 0
1378 && (note = find_reg_equal_equiv_note (temp)) != 0
1379 && (note = XEXP (note, 0), GET_CODE (note)) != EXPR_LIST
1380 /* Avoid using a register that may already been marked
1381 dead by an earlier instruction. */
1382 && ! unmentioned_reg_p (note, SET_SRC (set))
1383 && (GET_MODE (note) == VOIDmode
1384 ? SCALAR_INT_MODE_P (GET_MODE (SET_DEST (set)))
1385 : GET_MODE (SET_DEST (set)) == GET_MODE (note)))
1387 /* Temporarily replace the set's source with the
1388 contents of the REG_EQUAL note. The insn will
1389 be deleted or recognized by try_combine. */
1390 rtx orig = SET_SRC (set);
1391 SET_SRC (set) = note;
1393 i2mod_old_rhs = copy_rtx (orig);
1394 i2mod_new_rhs = copy_rtx (note);
1395 next = try_combine (insn, i2mod, NULL_RTX, NULL_RTX,
1397 last_combined_insn);
1401 SET_SRC (set) = orig;
1406 record_dead_and_set_regs (insn);
1414 default_rtl_profile ();
1416 new_direct_jump_p |= purge_all_dead_edges ();
1417 delete_noop_moves ();
1420 obstack_free (&insn_link_obstack, NULL);
1421 free (uid_log_links);
1422 free (uid_insn_cost);
1423 VEC_free (reg_stat_type, heap, reg_stat);
1426 struct undo *undo, *next;
1427 for (undo = undobuf.frees; undo; undo = next)
1435 total_attempts += combine_attempts;
1436 total_merges += combine_merges;
1437 total_extras += combine_extras;
1438 total_successes += combine_successes;
1440 nonzero_sign_valid = 0;
1441 rtl_hooks = general_rtl_hooks;
1443 /* Make recognizer allow volatile MEMs again. */
1446 return new_direct_jump_p;
1449 /* Wipe the last_xxx fields of reg_stat in preparation for another pass. */
1452 init_reg_last (void)
1457 FOR_EACH_VEC_ELT (reg_stat_type, reg_stat, i, p)
1458 memset (p, 0, offsetof (reg_stat_type, sign_bit_copies));
1461 /* Set up any promoted values for incoming argument registers. */
1464 setup_incoming_promotions (rtx first)
1467 bool strictly_local = false;
1469 for (arg = DECL_ARGUMENTS (current_function_decl); arg;
1470 arg = DECL_CHAIN (arg))
1472 rtx x, reg = DECL_INCOMING_RTL (arg);
1474 enum machine_mode mode1, mode2, mode3, mode4;
1476 /* Only continue if the incoming argument is in a register. */
1480 /* Determine, if possible, whether all call sites of the current
1481 function lie within the current compilation unit. (This does
1482 take into account the exporting of a function via taking its
1483 address, and so forth.) */
1484 strictly_local = cgraph_local_info (current_function_decl)->local;
1486 /* The mode and signedness of the argument before any promotions happen
1487 (equal to the mode of the pseudo holding it at that stage). */
1488 mode1 = TYPE_MODE (TREE_TYPE (arg));
1489 uns1 = TYPE_UNSIGNED (TREE_TYPE (arg));
1491 /* The mode and signedness of the argument after any source language and
1492 TARGET_PROMOTE_PROTOTYPES-driven promotions. */
1493 mode2 = TYPE_MODE (DECL_ARG_TYPE (arg));
1494 uns3 = TYPE_UNSIGNED (DECL_ARG_TYPE (arg));
1496 /* The mode and signedness of the argument as it is actually passed,
1497 after any TARGET_PROMOTE_FUNCTION_ARGS-driven ABI promotions. */
1498 mode3 = promote_function_mode (DECL_ARG_TYPE (arg), mode2, &uns3,
1499 TREE_TYPE (cfun->decl), 0);
1501 /* The mode of the register in which the argument is being passed. */
1502 mode4 = GET_MODE (reg);
1504 /* Eliminate sign extensions in the callee when:
1505 (a) A mode promotion has occurred; */
1508 /* (b) The mode of the register is the same as the mode of
1509 the argument as it is passed; */
1512 /* (c) There's no language level extension; */
1515 /* (c.1) All callers are from the current compilation unit. If that's
1516 the case we don't have to rely on an ABI, we only have to know
1517 what we're generating right now, and we know that we will do the
1518 mode1 to mode2 promotion with the given sign. */
1519 else if (!strictly_local)
1521 /* (c.2) The combination of the two promotions is useful. This is
1522 true when the signs match, or if the first promotion is unsigned.
1523 In the later case, (sign_extend (zero_extend x)) is the same as
1524 (zero_extend (zero_extend x)), so make sure to force UNS3 true. */
1530 /* Record that the value was promoted from mode1 to mode3,
1531 so that any sign extension at the head of the current
1532 function may be eliminated. */
1533 x = gen_rtx_CLOBBER (mode1, const0_rtx);
1534 x = gen_rtx_fmt_e ((uns3 ? ZERO_EXTEND : SIGN_EXTEND), mode3, x);
1535 record_value_for_reg (reg, first, x);
1539 /* Called via note_stores. If X is a pseudo that is narrower than
1540 HOST_BITS_PER_WIDE_INT and is being set, record what bits are known zero.
1542 If we are setting only a portion of X and we can't figure out what
1543 portion, assume all bits will be used since we don't know what will
1546 Similarly, set how many bits of X are known to be copies of the sign bit
1547 at all locations in the function. This is the smallest number implied
1551 set_nonzero_bits_and_sign_copies (rtx x, const_rtx set, void *data)
1553 rtx insn = (rtx) data;
1557 && REGNO (x) >= FIRST_PSEUDO_REGISTER
1558 /* If this register is undefined at the start of the file, we can't
1559 say what its contents were. */
1560 && ! REGNO_REG_SET_P
1561 (DF_LR_IN (ENTRY_BLOCK_PTR->next_bb), REGNO (x))
1562 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT)
1564 reg_stat_type *rsp = VEC_index (reg_stat_type, reg_stat, REGNO (x));
1566 if (set == 0 || GET_CODE (set) == CLOBBER)
1568 rsp->nonzero_bits = GET_MODE_MASK (GET_MODE (x));
1569 rsp->sign_bit_copies = 1;
1573 /* If this register is being initialized using itself, and the
1574 register is uninitialized in this basic block, and there are
1575 no LOG_LINKS which set the register, then part of the
1576 register is uninitialized. In that case we can't assume
1577 anything about the number of nonzero bits.
1579 ??? We could do better if we checked this in
1580 reg_{nonzero_bits,num_sign_bit_copies}_for_combine. Then we
1581 could avoid making assumptions about the insn which initially
1582 sets the register, while still using the information in other
1583 insns. We would have to be careful to check every insn
1584 involved in the combination. */
1587 && reg_referenced_p (x, PATTERN (insn))
1588 && !REGNO_REG_SET_P (DF_LR_IN (BLOCK_FOR_INSN (insn)),
1591 struct insn_link *link;
1593 FOR_EACH_LOG_LINK (link, insn)
1594 if (dead_or_set_p (link->insn, x))
1598 rsp->nonzero_bits = GET_MODE_MASK (GET_MODE (x));
1599 rsp->sign_bit_copies = 1;
1604 /* If this is a complex assignment, see if we can convert it into a
1605 simple assignment. */
1606 set = expand_field_assignment (set);
1608 /* If this is a simple assignment, or we have a paradoxical SUBREG,
1609 set what we know about X. */
1611 if (SET_DEST (set) == x
1612 || (GET_CODE (SET_DEST (set)) == SUBREG
1613 && (GET_MODE_SIZE (GET_MODE (SET_DEST (set)))
1614 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (set)))))
1615 && SUBREG_REG (SET_DEST (set)) == x))
1617 rtx src = SET_SRC (set);
1619 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
1620 /* If X is narrower than a word and SRC is a non-negative
1621 constant that would appear negative in the mode of X,
1622 sign-extend it for use in reg_stat[].nonzero_bits because some
1623 machines (maybe most) will actually do the sign-extension
1624 and this is the conservative approach.
1626 ??? For 2.5, try to tighten up the MD files in this regard
1627 instead of this kludge. */
1629 if (GET_MODE_BITSIZE (GET_MODE (x)) < BITS_PER_WORD
1630 && CONST_INT_P (src)
1632 && 0 != (UINTVAL (src)
1633 & ((unsigned HOST_WIDE_INT) 1
1634 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
1635 src = GEN_INT (UINTVAL (src)
1636 | ((unsigned HOST_WIDE_INT) (-1)
1637 << GET_MODE_BITSIZE (GET_MODE (x))));
1640 /* Don't call nonzero_bits if it cannot change anything. */
1641 if (rsp->nonzero_bits != ~(unsigned HOST_WIDE_INT) 0)
1642 rsp->nonzero_bits |= nonzero_bits (src, nonzero_bits_mode);
1643 num = num_sign_bit_copies (SET_SRC (set), GET_MODE (x));
1644 if (rsp->sign_bit_copies == 0
1645 || rsp->sign_bit_copies > num)
1646 rsp->sign_bit_copies = num;
1650 rsp->nonzero_bits = GET_MODE_MASK (GET_MODE (x));
1651 rsp->sign_bit_copies = 1;
1656 /* See if INSN can be combined into I3. PRED, PRED2, SUCC and SUCC2 are
1657 optionally insns that were previously combined into I3 or that will be
1658 combined into the merger of INSN and I3. The order is PRED, PRED2,
1659 INSN, SUCC, SUCC2, I3.
1661 Return 0 if the combination is not allowed for any reason.
1663 If the combination is allowed, *PDEST will be set to the single
1664 destination of INSN and *PSRC to the single source, and this function
1668 can_combine_p (rtx insn, rtx i3, rtx pred ATTRIBUTE_UNUSED,
1669 rtx pred2 ATTRIBUTE_UNUSED, rtx succ, rtx succ2,
1670 rtx *pdest, rtx *psrc)
1679 bool all_adjacent = true;
1685 if (next_active_insn (succ2) != i3)
1686 all_adjacent = false;
1687 if (next_active_insn (succ) != succ2)
1688 all_adjacent = false;
1690 else if (next_active_insn (succ) != i3)
1691 all_adjacent = false;
1692 if (next_active_insn (insn) != succ)
1693 all_adjacent = false;
1695 else if (next_active_insn (insn) != i3)
1696 all_adjacent = false;
1698 /* Can combine only if previous insn is a SET of a REG, a SUBREG or CC0.
1699 or a PARALLEL consisting of such a SET and CLOBBERs.
1701 If INSN has CLOBBER parallel parts, ignore them for our processing.
1702 By definition, these happen during the execution of the insn. When it
1703 is merged with another insn, all bets are off. If they are, in fact,
1704 needed and aren't also supplied in I3, they may be added by
1705 recog_for_combine. Otherwise, it won't match.
1707 We can also ignore a SET whose SET_DEST is mentioned in a REG_UNUSED
1710 Get the source and destination of INSN. If more than one, can't
1713 if (GET_CODE (PATTERN (insn)) == SET)
1714 set = PATTERN (insn);
1715 else if (GET_CODE (PATTERN (insn)) == PARALLEL
1716 && GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == SET)
1718 for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
1720 rtx elt = XVECEXP (PATTERN (insn), 0, i);
1722 switch (GET_CODE (elt))
1724 /* This is important to combine floating point insns
1725 for the SH4 port. */
1727 /* Combining an isolated USE doesn't make sense.
1728 We depend here on combinable_i3pat to reject them. */
1729 /* The code below this loop only verifies that the inputs of
1730 the SET in INSN do not change. We call reg_set_between_p
1731 to verify that the REG in the USE does not change between
1733 If the USE in INSN was for a pseudo register, the matching
1734 insn pattern will likely match any register; combining this
1735 with any other USE would only be safe if we knew that the
1736 used registers have identical values, or if there was
1737 something to tell them apart, e.g. different modes. For
1738 now, we forgo such complicated tests and simply disallow
1739 combining of USES of pseudo registers with any other USE. */
1740 if (REG_P (XEXP (elt, 0))
1741 && GET_CODE (PATTERN (i3)) == PARALLEL)
1743 rtx i3pat = PATTERN (i3);
1744 int i = XVECLEN (i3pat, 0) - 1;
1745 unsigned int regno = REGNO (XEXP (elt, 0));
1749 rtx i3elt = XVECEXP (i3pat, 0, i);
1751 if (GET_CODE (i3elt) == USE
1752 && REG_P (XEXP (i3elt, 0))
1753 && (REGNO (XEXP (i3elt, 0)) == regno
1754 ? reg_set_between_p (XEXP (elt, 0),
1755 PREV_INSN (insn), i3)
1756 : regno >= FIRST_PSEUDO_REGISTER))
1763 /* We can ignore CLOBBERs. */
1768 /* Ignore SETs whose result isn't used but not those that
1769 have side-effects. */
1770 if (find_reg_note (insn, REG_UNUSED, SET_DEST (elt))
1771 && insn_nothrow_p (insn)
1772 && !side_effects_p (elt))
1775 /* If we have already found a SET, this is a second one and
1776 so we cannot combine with this insn. */
1784 /* Anything else means we can't combine. */
1790 /* If SET_SRC is an ASM_OPERANDS we can't throw away these CLOBBERs,
1791 so don't do anything with it. */
1792 || GET_CODE (SET_SRC (set)) == ASM_OPERANDS)
1801 set = expand_field_assignment (set);
1802 src = SET_SRC (set), dest = SET_DEST (set);
1804 /* Don't eliminate a store in the stack pointer. */
1805 if (dest == stack_pointer_rtx
1806 /* Don't combine with an insn that sets a register to itself if it has
1807 a REG_EQUAL note. This may be part of a LIBCALL sequence. */
1808 || (rtx_equal_p (src, dest) && find_reg_note (insn, REG_EQUAL, NULL_RTX))
1809 /* Can't merge an ASM_OPERANDS. */
1810 || GET_CODE (src) == ASM_OPERANDS
1811 /* Can't merge a function call. */
1812 || GET_CODE (src) == CALL
1813 /* Don't eliminate a function call argument. */
1815 && (find_reg_fusage (i3, USE, dest)
1817 && REGNO (dest) < FIRST_PSEUDO_REGISTER
1818 && global_regs[REGNO (dest)])))
1819 /* Don't substitute into an incremented register. */
1820 || FIND_REG_INC_NOTE (i3, dest)
1821 || (succ && FIND_REG_INC_NOTE (succ, dest))
1822 || (succ2 && FIND_REG_INC_NOTE (succ2, dest))
1823 /* Don't substitute into a non-local goto, this confuses CFG. */
1824 || (JUMP_P (i3) && find_reg_note (i3, REG_NON_LOCAL_GOTO, NULL_RTX))
1825 /* Make sure that DEST is not used after SUCC but before I3. */
1828 && (reg_used_between_p (dest, succ2, i3)
1829 || reg_used_between_p (dest, succ, succ2)))
1830 || (!succ2 && succ && reg_used_between_p (dest, succ, i3))))
1831 /* Make sure that the value that is to be substituted for the register
1832 does not use any registers whose values alter in between. However,
1833 If the insns are adjacent, a use can't cross a set even though we
1834 think it might (this can happen for a sequence of insns each setting
1835 the same destination; last_set of that register might point to
1836 a NOTE). If INSN has a REG_EQUIV note, the register is always
1837 equivalent to the memory so the substitution is valid even if there
1838 are intervening stores. Also, don't move a volatile asm or
1839 UNSPEC_VOLATILE across any other insns. */
1842 || ! find_reg_note (insn, REG_EQUIV, src))
1843 && use_crosses_set_p (src, DF_INSN_LUID (insn)))
1844 || (GET_CODE (src) == ASM_OPERANDS && MEM_VOLATILE_P (src))
1845 || GET_CODE (src) == UNSPEC_VOLATILE))
1846 /* Don't combine across a CALL_INSN, because that would possibly
1847 change whether the life span of some REGs crosses calls or not,
1848 and it is a pain to update that information.
1849 Exception: if source is a constant, moving it later can't hurt.
1850 Accept that as a special case. */
1851 || (DF_INSN_LUID (insn) < last_call_luid && ! CONSTANT_P (src)))
1854 /* DEST must either be a REG or CC0. */
1857 /* If register alignment is being enforced for multi-word items in all
1858 cases except for parameters, it is possible to have a register copy
1859 insn referencing a hard register that is not allowed to contain the
1860 mode being copied and which would not be valid as an operand of most
1861 insns. Eliminate this problem by not combining with such an insn.
1863 Also, on some machines we don't want to extend the life of a hard
1867 && ((REGNO (dest) < FIRST_PSEUDO_REGISTER
1868 && ! HARD_REGNO_MODE_OK (REGNO (dest), GET_MODE (dest)))
1869 /* Don't extend the life of a hard register unless it is
1870 user variable (if we have few registers) or it can't
1871 fit into the desired register (meaning something special
1873 Also avoid substituting a return register into I3, because
1874 reload can't handle a conflict with constraints of other
1876 || (REGNO (src) < FIRST_PSEUDO_REGISTER
1877 && ! HARD_REGNO_MODE_OK (REGNO (src), GET_MODE (src)))))
1880 else if (GET_CODE (dest) != CC0)
1884 if (GET_CODE (PATTERN (i3)) == PARALLEL)
1885 for (i = XVECLEN (PATTERN (i3), 0) - 1; i >= 0; i--)
1886 if (GET_CODE (XVECEXP (PATTERN (i3), 0, i)) == CLOBBER)
1888 /* Don't substitute for a register intended as a clobberable
1890 rtx reg = XEXP (XVECEXP (PATTERN (i3), 0, i), 0);
1891 if (rtx_equal_p (reg, dest))
1894 /* If the clobber represents an earlyclobber operand, we must not
1895 substitute an expression containing the clobbered register.
1896 As we do not analyze the constraint strings here, we have to
1897 make the conservative assumption. However, if the register is
1898 a fixed hard reg, the clobber cannot represent any operand;
1899 we leave it up to the machine description to either accept or
1900 reject use-and-clobber patterns. */
1902 || REGNO (reg) >= FIRST_PSEUDO_REGISTER
1903 || !fixed_regs[REGNO (reg)])
1904 if (reg_overlap_mentioned_p (reg, src))
1908 /* If INSN contains anything volatile, or is an `asm' (whether volatile
1909 or not), reject, unless nothing volatile comes between it and I3 */
1911 if (GET_CODE (src) == ASM_OPERANDS || volatile_refs_p (src))
1913 /* Make sure neither succ nor succ2 contains a volatile reference. */
1914 if (succ2 != 0 && volatile_refs_p (PATTERN (succ2)))
1916 if (succ != 0 && volatile_refs_p (PATTERN (succ)))
1918 /* We'll check insns between INSN and I3 below. */
1921 /* If INSN is an asm, and DEST is a hard register, reject, since it has
1922 to be an explicit register variable, and was chosen for a reason. */
1924 if (GET_CODE (src) == ASM_OPERANDS
1925 && REG_P (dest) && REGNO (dest) < FIRST_PSEUDO_REGISTER)
1928 /* If there are any volatile insns between INSN and I3, reject, because
1929 they might affect machine state. */
1931 for (p = NEXT_INSN (insn); p != i3; p = NEXT_INSN (p))
1932 if (INSN_P (p) && p != succ && p != succ2 && volatile_insn_p (PATTERN (p)))
1935 /* If INSN contains an autoincrement or autodecrement, make sure that
1936 register is not used between there and I3, and not already used in
1937 I3 either. Neither must it be used in PRED or SUCC, if they exist.
1938 Also insist that I3 not be a jump; if it were one
1939 and the incremented register were spilled, we would lose. */
1942 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
1943 if (REG_NOTE_KIND (link) == REG_INC
1945 || reg_used_between_p (XEXP (link, 0), insn, i3)
1946 || (pred != NULL_RTX
1947 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (pred)))
1948 || (pred2 != NULL_RTX
1949 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (pred2)))
1950 || (succ != NULL_RTX
1951 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (succ)))
1952 || (succ2 != NULL_RTX
1953 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (succ2)))
1954 || reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i3))))
1959 /* Don't combine an insn that follows a CC0-setting insn.
1960 An insn that uses CC0 must not be separated from the one that sets it.
1961 We do, however, allow I2 to follow a CC0-setting insn if that insn
1962 is passed as I1; in that case it will be deleted also.
1963 We also allow combining in this case if all the insns are adjacent
1964 because that would leave the two CC0 insns adjacent as well.
1965 It would be more logical to test whether CC0 occurs inside I1 or I2,
1966 but that would be much slower, and this ought to be equivalent. */
1968 p = prev_nonnote_insn (insn);
1969 if (p && p != pred && NONJUMP_INSN_P (p) && sets_cc0_p (PATTERN (p))
1974 /* If we get here, we have passed all the tests and the combination is
1983 /* LOC is the location within I3 that contains its pattern or the component
1984 of a PARALLEL of the pattern. We validate that it is valid for combining.
1986 One problem is if I3 modifies its output, as opposed to replacing it
1987 entirely, we can't allow the output to contain I2DEST, I1DEST or I0DEST as
1988 doing so would produce an insn that is not equivalent to the original insns.
1992 (set (reg:DI 101) (reg:DI 100))
1993 (set (subreg:SI (reg:DI 101) 0) <foo>)
1995 This is NOT equivalent to:
1997 (parallel [(set (subreg:SI (reg:DI 100) 0) <foo>)
1998 (set (reg:DI 101) (reg:DI 100))])
2000 Not only does this modify 100 (in which case it might still be valid
2001 if 100 were dead in I2), it sets 101 to the ORIGINAL value of 100.
2003 We can also run into a problem if I2 sets a register that I1
2004 uses and I1 gets directly substituted into I3 (not via I2). In that
2005 case, we would be getting the wrong value of I2DEST into I3, so we
2006 must reject the combination. This case occurs when I2 and I1 both
2007 feed into I3, rather than when I1 feeds into I2, which feeds into I3.
2008 If I1_NOT_IN_SRC is nonzero, it means that finding I1 in the source
2009 of a SET must prevent combination from occurring. The same situation
2010 can occur for I0, in which case I0_NOT_IN_SRC is set.
2012 Before doing the above check, we first try to expand a field assignment
2013 into a set of logical operations.
2015 If PI3_DEST_KILLED is nonzero, it is a pointer to a location in which
2016 we place a register that is both set and used within I3. If more than one
2017 such register is detected, we fail.
2019 Return 1 if the combination is valid, zero otherwise. */
2022 combinable_i3pat (rtx i3, rtx *loc, rtx i2dest, rtx i1dest, rtx i0dest,
2023 int i1_not_in_src, int i0_not_in_src, rtx *pi3dest_killed)
2027 if (GET_CODE (x) == SET)
2030 rtx dest = SET_DEST (set);
2031 rtx src = SET_SRC (set);
2032 rtx inner_dest = dest;
2035 while (GET_CODE (inner_dest) == STRICT_LOW_PART
2036 || GET_CODE (inner_dest) == SUBREG
2037 || GET_CODE (inner_dest) == ZERO_EXTRACT)
2038 inner_dest = XEXP (inner_dest, 0);
2040 /* Check for the case where I3 modifies its output, as discussed
2041 above. We don't want to prevent pseudos from being combined
2042 into the address of a MEM, so only prevent the combination if
2043 i1 or i2 set the same MEM. */
2044 if ((inner_dest != dest &&
2045 (!MEM_P (inner_dest)
2046 || rtx_equal_p (i2dest, inner_dest)
2047 || (i1dest && rtx_equal_p (i1dest, inner_dest))
2048 || (i0dest && rtx_equal_p (i0dest, inner_dest)))
2049 && (reg_overlap_mentioned_p (i2dest, inner_dest)
2050 || (i1dest && reg_overlap_mentioned_p (i1dest, inner_dest))
2051 || (i0dest && reg_overlap_mentioned_p (i0dest, inner_dest))))
2053 /* This is the same test done in can_combine_p except we can't test
2054 all_adjacent; we don't have to, since this instruction will stay
2055 in place, thus we are not considering increasing the lifetime of
2058 Also, if this insn sets a function argument, combining it with
2059 something that might need a spill could clobber a previous
2060 function argument; the all_adjacent test in can_combine_p also
2061 checks this; here, we do a more specific test for this case. */
2063 || (REG_P (inner_dest)
2064 && REGNO (inner_dest) < FIRST_PSEUDO_REGISTER
2065 && (! HARD_REGNO_MODE_OK (REGNO (inner_dest),
2066 GET_MODE (inner_dest))))
2067 || (i1_not_in_src && reg_overlap_mentioned_p (i1dest, src))
2068 || (i0_not_in_src && reg_overlap_mentioned_p (i0dest, src)))
2071 /* If DEST is used in I3, it is being killed in this insn, so
2072 record that for later. We have to consider paradoxical
2073 subregs here, since they kill the whole register, but we
2074 ignore partial subregs, STRICT_LOW_PART, etc.
2075 Never add REG_DEAD notes for the FRAME_POINTER_REGNUM or the
2076 STACK_POINTER_REGNUM, since these are always considered to be
2077 live. Similarly for ARG_POINTER_REGNUM if it is fixed. */
2079 if (GET_CODE (subdest) == SUBREG
2080 && (GET_MODE_SIZE (GET_MODE (subdest))
2081 >= GET_MODE_SIZE (GET_MODE (SUBREG_REG (subdest)))))
2082 subdest = SUBREG_REG (subdest);
2085 && reg_referenced_p (subdest, PATTERN (i3))
2086 && REGNO (subdest) != FRAME_POINTER_REGNUM
2087 #if !HARD_FRAME_POINTER_IS_FRAME_POINTER
2088 && REGNO (subdest) != HARD_FRAME_POINTER_REGNUM
2090 #if ARG_POINTER_REGNUM != FRAME_POINTER_REGNUM
2091 && (REGNO (subdest) != ARG_POINTER_REGNUM
2092 || ! fixed_regs [REGNO (subdest)])
2094 && REGNO (subdest) != STACK_POINTER_REGNUM)
2096 if (*pi3dest_killed)
2099 *pi3dest_killed = subdest;
2103 else if (GET_CODE (x) == PARALLEL)
2107 for (i = 0; i < XVECLEN (x, 0); i++)
2108 if (! combinable_i3pat (i3, &XVECEXP (x, 0, i), i2dest, i1dest, i0dest,
2109 i1_not_in_src, i0_not_in_src, pi3dest_killed))
2116 /* Return 1 if X is an arithmetic expression that contains a multiplication
2117 and division. We don't count multiplications by powers of two here. */
2120 contains_muldiv (rtx x)
2122 switch (GET_CODE (x))
2124 case MOD: case DIV: case UMOD: case UDIV:
2128 return ! (CONST_INT_P (XEXP (x, 1))
2129 && exact_log2 (UINTVAL (XEXP (x, 1))) >= 0);
2132 return contains_muldiv (XEXP (x, 0))
2133 || contains_muldiv (XEXP (x, 1));
2136 return contains_muldiv (XEXP (x, 0));
2142 /* Determine whether INSN can be used in a combination. Return nonzero if
2143 not. This is used in try_combine to detect early some cases where we
2144 can't perform combinations. */
2147 cant_combine_insn_p (rtx insn)
2152 /* If this isn't really an insn, we can't do anything.
2153 This can occur when flow deletes an insn that it has merged into an
2154 auto-increment address. */
2155 if (! INSN_P (insn))
2158 /* Never combine loads and stores involving hard regs that are likely
2159 to be spilled. The register allocator can usually handle such
2160 reg-reg moves by tying. If we allow the combiner to make
2161 substitutions of likely-spilled regs, reload might die.
2162 As an exception, we allow combinations involving fixed regs; these are
2163 not available to the register allocator so there's no risk involved. */
2165 set = single_set (insn);
2168 src = SET_SRC (set);
2169 dest = SET_DEST (set);
2170 if (GET_CODE (src) == SUBREG)
2171 src = SUBREG_REG (src);
2172 if (GET_CODE (dest) == SUBREG)
2173 dest = SUBREG_REG (dest);
2174 if (REG_P (src) && REG_P (dest)
2175 && ((HARD_REGISTER_P (src)
2176 && ! TEST_HARD_REG_BIT (fixed_reg_set, REGNO (src))
2177 && targetm.class_likely_spilled_p (REGNO_REG_CLASS (REGNO (src))))
2178 || (HARD_REGISTER_P (dest)
2179 && ! TEST_HARD_REG_BIT (fixed_reg_set, REGNO (dest))
2180 && targetm.class_likely_spilled_p (REGNO_REG_CLASS (REGNO (dest))))))
2186 struct likely_spilled_retval_info
2188 unsigned regno, nregs;
2192 /* Called via note_stores by likely_spilled_retval_p. Remove from info->mask
2193 hard registers that are known to be written to / clobbered in full. */
2195 likely_spilled_retval_1 (rtx x, const_rtx set, void *data)
2197 struct likely_spilled_retval_info *const info =
2198 (struct likely_spilled_retval_info *) data;
2199 unsigned regno, nregs;
2202 if (!REG_P (XEXP (set, 0)))
2205 if (regno >= info->regno + info->nregs)
2207 nregs = hard_regno_nregs[regno][GET_MODE (x)];
2208 if (regno + nregs <= info->regno)
2210 new_mask = (2U << (nregs - 1)) - 1;
2211 if (regno < info->regno)
2212 new_mask >>= info->regno - regno;
2214 new_mask <<= regno - info->regno;
2215 info->mask &= ~new_mask;
2218 /* Return nonzero iff part of the return value is live during INSN, and
2219 it is likely spilled. This can happen when more than one insn is needed
2220 to copy the return value, e.g. when we consider to combine into the
2221 second copy insn for a complex value. */
2224 likely_spilled_retval_p (rtx insn)
2226 rtx use = BB_END (this_basic_block);
2228 unsigned regno, nregs;
2229 /* We assume here that no machine mode needs more than
2230 32 hard registers when the value overlaps with a register
2231 for which TARGET_FUNCTION_VALUE_REGNO_P is true. */
2233 struct likely_spilled_retval_info info;
2235 if (!NONJUMP_INSN_P (use) || GET_CODE (PATTERN (use)) != USE || insn == use)
2237 reg = XEXP (PATTERN (use), 0);
2238 if (!REG_P (reg) || !targetm.calls.function_value_regno_p (REGNO (reg)))
2240 regno = REGNO (reg);
2241 nregs = hard_regno_nregs[regno][GET_MODE (reg)];
2244 mask = (2U << (nregs - 1)) - 1;
2246 /* Disregard parts of the return value that are set later. */
2250 for (p = PREV_INSN (use); info.mask && p != insn; p = PREV_INSN (p))
2252 note_stores (PATTERN (p), likely_spilled_retval_1, &info);
2255 /* Check if any of the (probably) live return value registers is
2260 if ((mask & 1 << nregs)
2261 && targetm.class_likely_spilled_p (REGNO_REG_CLASS (regno + nregs)))
2267 /* Adjust INSN after we made a change to its destination.
2269 Changing the destination can invalidate notes that say something about
2270 the results of the insn and a LOG_LINK pointing to the insn. */
2273 adjust_for_new_dest (rtx insn)
2275 /* For notes, be conservative and simply remove them. */
2276 remove_reg_equal_equiv_notes (insn);
2278 /* The new insn will have a destination that was previously the destination
2279 of an insn just above it. Call distribute_links to make a LOG_LINK from
2280 the next use of that destination. */
2281 distribute_links (alloc_insn_link (insn, NULL));
2283 df_insn_rescan (insn);
2286 /* Return TRUE if combine can reuse reg X in mode MODE.
2287 ADDED_SETS is nonzero if the original set is still required. */
2289 can_change_dest_mode (rtx x, int added_sets, enum machine_mode mode)
2297 /* Allow hard registers if the new mode is legal, and occupies no more
2298 registers than the old mode. */
2299 if (regno < FIRST_PSEUDO_REGISTER)
2300 return (HARD_REGNO_MODE_OK (regno, mode)
2301 && (hard_regno_nregs[regno][GET_MODE (x)]
2302 >= hard_regno_nregs[regno][mode]));
2304 /* Or a pseudo that is only used once. */
2305 return (REG_N_SETS (regno) == 1 && !added_sets
2306 && !REG_USERVAR_P (x));
2310 /* Check whether X, the destination of a set, refers to part of
2311 the register specified by REG. */
2314 reg_subword_p (rtx x, rtx reg)
2316 /* Check that reg is an integer mode register. */
2317 if (!REG_P (reg) || GET_MODE_CLASS (GET_MODE (reg)) != MODE_INT)
2320 if (GET_CODE (x) == STRICT_LOW_PART
2321 || GET_CODE (x) == ZERO_EXTRACT)
2324 return GET_CODE (x) == SUBREG
2325 && SUBREG_REG (x) == reg
2326 && GET_MODE_CLASS (GET_MODE (x)) == MODE_INT;
2330 /* Replace auto-increment addressing modes with explicit operations to access
2331 the same addresses without modifying the corresponding registers. */
2334 cleanup_auto_inc_dec (rtx src, enum machine_mode mem_mode)
2337 const RTX_CODE code = GET_CODE (x);
2353 /* SCRATCH must be shared because they represent distinct values. */
2356 if (REG_P (XEXP (x, 0)) && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER)
2361 if (shared_const_p (x))
2366 mem_mode = GET_MODE (x);
2371 gcc_assert (mem_mode != VOIDmode && mem_mode != BLKmode);
2372 return gen_rtx_PLUS (GET_MODE (x),
2373 cleanup_auto_inc_dec (XEXP (x, 0), mem_mode),
2374 GEN_INT (code == PRE_INC
2375 ? GET_MODE_SIZE (mem_mode)
2376 : -GET_MODE_SIZE (mem_mode)));
2382 return cleanup_auto_inc_dec (code == PRE_MODIFY
2383 ? XEXP (x, 1) : XEXP (x, 0),
2390 /* Copy the various flags, fields, and other information. We assume
2391 that all fields need copying, and then clear the fields that should
2392 not be copied. That is the sensible default behavior, and forces
2393 us to explicitly document why we are *not* copying a flag. */
2394 x = shallow_copy_rtx (x);
2396 /* We do not copy the USED flag, which is used as a mark bit during
2397 walks over the RTL. */
2398 RTX_FLAG (x, used) = 0;
2400 /* We do not copy FRAME_RELATED for INSNs. */
2402 RTX_FLAG (x, frame_related) = 0;
2404 fmt = GET_RTX_FORMAT (code);
2405 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
2407 XEXP (x, i) = cleanup_auto_inc_dec (XEXP (x, i), mem_mode);
2408 else if (fmt[i] == 'E' || fmt[i] == 'V')
2411 XVEC (x, i) = rtvec_alloc (XVECLEN (x, i));
2412 for (j = 0; j < XVECLEN (x, i); j++)
2414 = cleanup_auto_inc_dec (XVECEXP (src, i, j), mem_mode);
2421 /* Auxiliary data structure for propagate_for_debug_stmt. */
2423 struct rtx_subst_pair
2429 /* DATA points to an rtx_subst_pair. Return the value that should be
2433 propagate_for_debug_subst (rtx from, const_rtx old_rtx, void *data)
2435 struct rtx_subst_pair *pair = (struct rtx_subst_pair *)data;
2437 if (!rtx_equal_p (from, old_rtx))
2439 if (!pair->adjusted)
2441 pair->adjusted = true;
2443 pair->to = cleanup_auto_inc_dec (pair->to, VOIDmode);
2445 pair->to = copy_rtx (pair->to);
2447 pair->to = make_compound_operation (pair->to, SET);
2450 return copy_rtx (pair->to);
2453 /* Replace all the occurrences of DEST with SRC in DEBUG_INSNs between INSN
2454 and LAST, not including INSN, but including LAST. Also stop at the end
2455 of THIS_BASIC_BLOCK. */
2458 propagate_for_debug (rtx insn, rtx last, rtx dest, rtx src)
2460 rtx next, loc, end = NEXT_INSN (BB_END (this_basic_block));
2462 struct rtx_subst_pair p;
2466 next = NEXT_INSN (insn);
2467 last = NEXT_INSN (last);
2468 while (next != last && next != end)
2471 next = NEXT_INSN (insn);
2472 if (DEBUG_INSN_P (insn))
2474 loc = simplify_replace_fn_rtx (INSN_VAR_LOCATION_LOC (insn),
2475 dest, propagate_for_debug_subst, &p);
2476 if (loc == INSN_VAR_LOCATION_LOC (insn))
2478 INSN_VAR_LOCATION_LOC (insn) = loc;
2479 df_insn_rescan (insn);
2484 /* Delete the unconditional jump INSN and adjust the CFG correspondingly.
2485 Note that the INSN should be deleted *after* removing dead edges, so
2486 that the kept edge is the fallthrough edge for a (set (pc) (pc))
2487 but not for a (set (pc) (label_ref FOO)). */
2490 update_cfg_for_uncondjump (rtx insn)
2492 basic_block bb = BLOCK_FOR_INSN (insn);
2493 bool at_end = (BB_END (bb) == insn);
2496 purge_dead_edges (bb);
2499 if (at_end && EDGE_COUNT (bb->succs) == 1)
2503 single_succ_edge (bb)->flags |= EDGE_FALLTHRU;
2505 /* Remove barriers from the footer if there are any. */
2506 for (insn = bb->il.rtl->footer; insn; insn = NEXT_INSN (insn))
2507 if (BARRIER_P (insn))
2509 if (PREV_INSN (insn))
2510 NEXT_INSN (PREV_INSN (insn)) = NEXT_INSN (insn);
2512 bb->il.rtl->footer = NEXT_INSN (insn);
2513 if (NEXT_INSN (insn))
2514 PREV_INSN (NEXT_INSN (insn)) = PREV_INSN (insn);
2516 else if (LABEL_P (insn))
2521 /* Try to combine the insns I0, I1 and I2 into I3.
2522 Here I0, I1 and I2 appear earlier than I3.
2523 I0 and I1 can be zero; then we combine just I2 into I3, or I1 and I2 into
2526 If we are combining more than two insns and the resulting insn is not
2527 recognized, try splitting it into two insns. If that happens, I2 and I3
2528 are retained and I1/I0 are pseudo-deleted by turning them into a NOTE.
2529 Otherwise, I0, I1 and I2 are pseudo-deleted.
2531 Return 0 if the combination does not work. Then nothing is changed.
2532 If we did the combination, return the insn at which combine should
2535 Set NEW_DIRECT_JUMP_P to a nonzero value if try_combine creates a
2536 new direct jump instruction.
2538 LAST_COMBINED_INSN is either I3, or some insn after I3 that has
2539 been I3 passed to an earlier try_combine within the same basic
2543 try_combine (rtx i3, rtx i2, rtx i1, rtx i0, int *new_direct_jump_p,
2544 rtx last_combined_insn)
2546 /* New patterns for I3 and I2, respectively. */
2547 rtx newpat, newi2pat = 0;
2548 rtvec newpat_vec_with_clobbers = 0;
2549 int substed_i2 = 0, substed_i1 = 0, substed_i0 = 0;
2550 /* Indicates need to preserve SET in I0, I1 or I2 in I3 if it is not
2552 int added_sets_0, added_sets_1, added_sets_2;
2553 /* Total number of SETs to put into I3. */
2555 /* Nonzero if I2's or I1's body now appears in I3. */
2556 int i2_is_used = 0, i1_is_used = 0;
2557 /* INSN_CODEs for new I3, new I2, and user of condition code. */
2558 int insn_code_number, i2_code_number = 0, other_code_number = 0;
2559 /* Contains I3 if the destination of I3 is used in its source, which means
2560 that the old life of I3 is being killed. If that usage is placed into
2561 I2 and not in I3, a REG_DEAD note must be made. */
2562 rtx i3dest_killed = 0;
2563 /* SET_DEST and SET_SRC of I2, I1 and I0. */
2564 rtx i2dest = 0, i2src = 0, i1dest = 0, i1src = 0, i0dest = 0, i0src = 0;
2565 /* Copy of SET_SRC of I1, if needed. */
2567 /* Set if I2DEST was reused as a scratch register. */
2568 bool i2scratch = false;
2569 /* The PATTERNs of I0, I1, and I2, or a copy of them in certain cases. */
2570 rtx i0pat = 0, i1pat = 0, i2pat = 0;
2571 /* Indicates if I2DEST or I1DEST is in I2SRC or I1_SRC. */
2572 int i2dest_in_i2src = 0, i1dest_in_i1src = 0, i2dest_in_i1src = 0;
2573 int i0dest_in_i0src = 0, i1dest_in_i0src = 0, i2dest_in_i0src = 0;
2574 int i2dest_killed = 0, i1dest_killed = 0, i0dest_killed = 0;
2575 int i1_feeds_i2_n = 0, i0_feeds_i2_n = 0, i0_feeds_i1_n = 0;
2576 /* Notes that must be added to REG_NOTES in I3 and I2. */
2577 rtx new_i3_notes, new_i2_notes;
2578 /* Notes that we substituted I3 into I2 instead of the normal case. */
2579 int i3_subst_into_i2 = 0;
2580 /* Notes that I1, I2 or I3 is a MULT operation. */
2583 int changed_i3_dest = 0;
2587 struct insn_link *link;
2589 rtx new_other_notes;
2592 /* Only try four-insn combinations when there's high likelihood of
2593 success. Look for simple insns, such as loads of constants or
2594 binary operations involving a constant. */
2601 if (!flag_expensive_optimizations)
2604 for (i = 0; i < 4; i++)
2606 rtx insn = i == 0 ? i0 : i == 1 ? i1 : i == 2 ? i2 : i3;
2607 rtx set = single_set (insn);
2611 src = SET_SRC (set);
2612 if (CONSTANT_P (src))
2617 else if (BINARY_P (src) && CONSTANT_P (XEXP (src, 1)))
2619 else if (GET_CODE (src) == ASHIFT || GET_CODE (src) == ASHIFTRT
2620 || GET_CODE (src) == LSHIFTRT)
2623 if (ngood < 2 && nshift < 2)
2627 /* Exit early if one of the insns involved can't be used for
2629 if (cant_combine_insn_p (i3)
2630 || cant_combine_insn_p (i2)
2631 || (i1 && cant_combine_insn_p (i1))
2632 || (i0 && cant_combine_insn_p (i0))
2633 || likely_spilled_retval_p (i3))
2637 undobuf.other_insn = 0;
2639 /* Reset the hard register usage information. */
2640 CLEAR_HARD_REG_SET (newpat_used_regs);
2642 if (dump_file && (dump_flags & TDF_DETAILS))
2645 fprintf (dump_file, "\nTrying %d, %d, %d -> %d:\n",
2646 INSN_UID (i0), INSN_UID (i1), INSN_UID (i2), INSN_UID (i3));
2648 fprintf (dump_file, "\nTrying %d, %d -> %d:\n",
2649 INSN_UID (i1), INSN_UID (i2), INSN_UID (i3));
2651 fprintf (dump_file, "\nTrying %d -> %d:\n",
2652 INSN_UID (i2), INSN_UID (i3));
2655 /* If multiple insns feed into one of I2 or I3, they can be in any
2656 order. To simplify the code below, reorder them in sequence. */
2657 if (i0 && DF_INSN_LUID (i0) > DF_INSN_LUID (i2))
2658 temp = i2, i2 = i0, i0 = temp;
2659 if (i0 && DF_INSN_LUID (i0) > DF_INSN_LUID (i1))
2660 temp = i1, i1 = i0, i0 = temp;
2661 if (i1 && DF_INSN_LUID (i1) > DF_INSN_LUID (i2))
2662 temp = i1, i1 = i2, i2 = temp;
2664 added_links_insn = 0;
2666 /* First check for one important special case that the code below will
2667 not handle. Namely, the case where I1 is zero, I2 is a PARALLEL
2668 and I3 is a SET whose SET_SRC is a SET_DEST in I2. In that case,
2669 we may be able to replace that destination with the destination of I3.
2670 This occurs in the common code where we compute both a quotient and
2671 remainder into a structure, in which case we want to do the computation
2672 directly into the structure to avoid register-register copies.
2674 Note that this case handles both multiple sets in I2 and also cases
2675 where I2 has a number of CLOBBERs inside the PARALLEL.
2677 We make very conservative checks below and only try to handle the
2678 most common cases of this. For example, we only handle the case
2679 where I2 and I3 are adjacent to avoid making difficult register
2682 if (i1 == 0 && NONJUMP_INSN_P (i3) && GET_CODE (PATTERN (i3)) == SET
2683 && REG_P (SET_SRC (PATTERN (i3)))
2684 && REGNO (SET_SRC (PATTERN (i3))) >= FIRST_PSEUDO_REGISTER
2685 && find_reg_note (i3, REG_DEAD, SET_SRC (PATTERN (i3)))
2686 && GET_CODE (PATTERN (i2)) == PARALLEL
2687 && ! side_effects_p (SET_DEST (PATTERN (i3)))
2688 /* If the dest of I3 is a ZERO_EXTRACT or STRICT_LOW_PART, the code
2689 below would need to check what is inside (and reg_overlap_mentioned_p
2690 doesn't support those codes anyway). Don't allow those destinations;
2691 the resulting insn isn't likely to be recognized anyway. */
2692 && GET_CODE (SET_DEST (PATTERN (i3))) != ZERO_EXTRACT
2693 && GET_CODE (SET_DEST (PATTERN (i3))) != STRICT_LOW_PART
2694 && ! reg_overlap_mentioned_p (SET_SRC (PATTERN (i3)),
2695 SET_DEST (PATTERN (i3)))
2696 && next_active_insn (i2) == i3)
2698 rtx p2 = PATTERN (i2);
2700 /* Make sure that the destination of I3,
2701 which we are going to substitute into one output of I2,
2702 is not used within another output of I2. We must avoid making this:
2703 (parallel [(set (mem (reg 69)) ...)
2704 (set (reg 69) ...)])
2705 which is not well-defined as to order of actions.
2706 (Besides, reload can't handle output reloads for this.)
2708 The problem can also happen if the dest of I3 is a memory ref,
2709 if another dest in I2 is an indirect memory ref. */
2710 for (i = 0; i < XVECLEN (p2, 0); i++)
2711 if ((GET_CODE (XVECEXP (p2, 0, i)) == SET
2712 || GET_CODE (XVECEXP (p2, 0, i)) == CLOBBER)
2713 && reg_overlap_mentioned_p (SET_DEST (PATTERN (i3)),
2714 SET_DEST (XVECEXP (p2, 0, i))))
2717 if (i == XVECLEN (p2, 0))
2718 for (i = 0; i < XVECLEN (p2, 0); i++)
2719 if (GET_CODE (XVECEXP (p2, 0, i)) == SET
2720 && SET_DEST (XVECEXP (p2, 0, i)) == SET_SRC (PATTERN (i3)))
2725 subst_low_luid = DF_INSN_LUID (i2);
2727 added_sets_2 = added_sets_1 = added_sets_0 = 0;
2728 i2src = SET_SRC (XVECEXP (p2, 0, i));
2729 i2dest = SET_DEST (XVECEXP (p2, 0, i));
2730 i2dest_killed = dead_or_set_p (i2, i2dest);
2732 /* Replace the dest in I2 with our dest and make the resulting
2733 insn the new pattern for I3. Then skip to where we validate
2734 the pattern. Everything was set up above. */
2735 SUBST (SET_DEST (XVECEXP (p2, 0, i)), SET_DEST (PATTERN (i3)));
2737 i3_subst_into_i2 = 1;
2738 goto validate_replacement;
2742 /* If I2 is setting a pseudo to a constant and I3 is setting some
2743 sub-part of it to another constant, merge them by making a new
2746 && (temp = single_set (i2)) != 0
2747 && (CONST_INT_P (SET_SRC (temp))
2748 || GET_CODE (SET_SRC (temp)) == CONST_DOUBLE)
2749 && GET_CODE (PATTERN (i3)) == SET
2750 && (CONST_INT_P (SET_SRC (PATTERN (i3)))
2751 || GET_CODE (SET_SRC (PATTERN (i3))) == CONST_DOUBLE)
2752 && reg_subword_p (SET_DEST (PATTERN (i3)), SET_DEST (temp)))
2754 rtx dest = SET_DEST (PATTERN (i3));
2758 if (GET_CODE (dest) == ZERO_EXTRACT)
2760 if (CONST_INT_P (XEXP (dest, 1))
2761 && CONST_INT_P (XEXP (dest, 2)))
2763 width = INTVAL (XEXP (dest, 1));
2764 offset = INTVAL (XEXP (dest, 2));
2765 dest = XEXP (dest, 0);
2766 if (BITS_BIG_ENDIAN)
2767 offset = GET_MODE_BITSIZE (GET_MODE (dest)) - width - offset;
2772 if (GET_CODE (dest) == STRICT_LOW_PART)
2773 dest = XEXP (dest, 0);
2774 width = GET_MODE_BITSIZE (GET_MODE (dest));
2780 /* If this is the low part, we're done. */
2781 if (subreg_lowpart_p (dest))
2783 /* Handle the case where inner is twice the size of outer. */
2784 else if (GET_MODE_BITSIZE (GET_MODE (SET_DEST (temp)))
2785 == 2 * GET_MODE_BITSIZE (GET_MODE (dest)))
2786 offset += GET_MODE_BITSIZE (GET_MODE (dest));
2787 /* Otherwise give up for now. */
2793 && (GET_MODE_BITSIZE (GET_MODE (SET_DEST (temp)))
2794 <= HOST_BITS_PER_DOUBLE_INT))
2797 rtx inner = SET_SRC (PATTERN (i3));
2798 rtx outer = SET_SRC (temp);
2800 o = rtx_to_double_int (outer);
2801 i = rtx_to_double_int (inner);
2803 m = double_int_mask (width);
2804 i = double_int_and (i, m);
2805 m = double_int_lshift (m, offset, HOST_BITS_PER_DOUBLE_INT, false);
2806 i = double_int_lshift (i, offset, HOST_BITS_PER_DOUBLE_INT, false);
2807 o = double_int_ior (double_int_and_not (o, m), i);
2811 subst_low_luid = DF_INSN_LUID (i2);
2812 added_sets_2 = added_sets_1 = added_sets_0 = 0;
2813 i2dest = SET_DEST (temp);
2814 i2dest_killed = dead_or_set_p (i2, i2dest);
2816 /* Replace the source in I2 with the new constant and make the
2817 resulting insn the new pattern for I3. Then skip to where we
2818 validate the pattern. Everything was set up above. */
2819 SUBST (SET_SRC (temp),
2820 immed_double_int_const (o, GET_MODE (SET_DEST (temp))));
2822 newpat = PATTERN (i2);
2824 /* The dest of I3 has been replaced with the dest of I2. */
2825 changed_i3_dest = 1;
2826 goto validate_replacement;
2831 /* If we have no I1 and I2 looks like:
2832 (parallel [(set (reg:CC X) (compare:CC OP (const_int 0)))
2834 make up a dummy I1 that is
2837 (set (reg:CC X) (compare:CC Y (const_int 0)))
2839 (We can ignore any trailing CLOBBERs.)
2841 This undoes a previous combination and allows us to match a branch-and-
2844 if (i1 == 0 && GET_CODE (PATTERN (i2)) == PARALLEL
2845 && XVECLEN (PATTERN (i2), 0) >= 2
2846 && GET_CODE (XVECEXP (PATTERN (i2), 0, 0)) == SET
2847 && (GET_MODE_CLASS (GET_MODE (SET_DEST (XVECEXP (PATTERN (i2), 0, 0))))
2849 && GET_CODE (SET_SRC (XVECEXP (PATTERN (i2), 0, 0))) == COMPARE
2850 && XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 1) == const0_rtx
2851 && GET_CODE (XVECEXP (PATTERN (i2), 0, 1)) == SET
2852 && REG_P (SET_DEST (XVECEXP (PATTERN (i2), 0, 1)))
2853 && rtx_equal_p (XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 0),
2854 SET_SRC (XVECEXP (PATTERN (i2), 0, 1))))
2856 for (i = XVECLEN (PATTERN (i2), 0) - 1; i >= 2; i--)
2857 if (GET_CODE (XVECEXP (PATTERN (i2), 0, i)) != CLOBBER)
2862 /* We make I1 with the same INSN_UID as I2. This gives it
2863 the same DF_INSN_LUID for value tracking. Our fake I1 will
2864 never appear in the insn stream so giving it the same INSN_UID
2865 as I2 will not cause a problem. */
2867 i1 = gen_rtx_INSN (VOIDmode, INSN_UID (i2), NULL_RTX, i2,
2868 BLOCK_FOR_INSN (i2), XVECEXP (PATTERN (i2), 0, 1),
2869 INSN_LOCATOR (i2), -1, NULL_RTX);
2871 SUBST (PATTERN (i2), XVECEXP (PATTERN (i2), 0, 0));
2872 SUBST (XEXP (SET_SRC (PATTERN (i2)), 0),
2873 SET_DEST (PATTERN (i1)));
2878 /* Verify that I2 and I1 are valid for combining. */
2879 if (! can_combine_p (i2, i3, i0, i1, NULL_RTX, NULL_RTX, &i2dest, &i2src)
2880 || (i1 && ! can_combine_p (i1, i3, i0, NULL_RTX, i2, NULL_RTX,
2882 || (i0 && ! can_combine_p (i0, i3, NULL_RTX, NULL_RTX, i1, i2,
2889 /* Record whether I2DEST is used in I2SRC and similarly for the other
2890 cases. Knowing this will help in register status updating below. */
2891 i2dest_in_i2src = reg_overlap_mentioned_p (i2dest, i2src);
2892 i1dest_in_i1src = i1 && reg_overlap_mentioned_p (i1dest, i1src);
2893 i2dest_in_i1src = i1 && reg_overlap_mentioned_p (i2dest, i1src);
2894 i0dest_in_i0src = i0 && reg_overlap_mentioned_p (i0dest, i0src);
2895 i1dest_in_i0src = i0 && reg_overlap_mentioned_p (i1dest, i0src);
2896 i2dest_in_i0src = i0 && reg_overlap_mentioned_p (i2dest, i0src);
2897 i2dest_killed = dead_or_set_p (i2, i2dest);
2898 i1dest_killed = i1 && dead_or_set_p (i1, i1dest);
2899 i0dest_killed = i0 && dead_or_set_p (i0, i0dest);
2901 /* For the earlier insns, determine which of the subsequent ones they
2903 i1_feeds_i2_n = i1 && insn_a_feeds_b (i1, i2);
2904 i0_feeds_i1_n = i0 && insn_a_feeds_b (i0, i1);
2905 i0_feeds_i2_n = (i0 && (!i0_feeds_i1_n ? insn_a_feeds_b (i0, i2)
2906 : (!reg_overlap_mentioned_p (i1dest, i0dest)
2907 && reg_overlap_mentioned_p (i0dest, i2src))));
2909 /* Ensure that I3's pattern can be the destination of combines. */
2910 if (! combinable_i3pat (i3, &PATTERN (i3), i2dest, i1dest, i0dest,
2911 i1 && i2dest_in_i1src && !i1_feeds_i2_n,
2912 i0 && ((i2dest_in_i0src && !i0_feeds_i2_n)
2913 || (i1dest_in_i0src && !i0_feeds_i1_n)),
2920 /* See if any of the insns is a MULT operation. Unless one is, we will
2921 reject a combination that is, since it must be slower. Be conservative
2923 if (GET_CODE (i2src) == MULT
2924 || (i1 != 0 && GET_CODE (i1src) == MULT)
2925 || (i0 != 0 && GET_CODE (i0src) == MULT)
2926 || (GET_CODE (PATTERN (i3)) == SET
2927 && GET_CODE (SET_SRC (PATTERN (i3))) == MULT))
2930 /* If I3 has an inc, then give up if I1 or I2 uses the reg that is inc'd.
2931 We used to do this EXCEPT in one case: I3 has a post-inc in an
2932 output operand. However, that exception can give rise to insns like
2934 which is a famous insn on the PDP-11 where the value of r3 used as the
2935 source was model-dependent. Avoid this sort of thing. */
2938 if (!(GET_CODE (PATTERN (i3)) == SET
2939 && REG_P (SET_SRC (PATTERN (i3)))
2940 && MEM_P (SET_DEST (PATTERN (i3)))
2941 && (GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_INC
2942 || GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_DEC)))
2943 /* It's not the exception. */
2948 for (link = REG_NOTES (i3); link; link = XEXP (link, 1))
2949 if (REG_NOTE_KIND (link) == REG_INC
2950 && (reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i2))
2952 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i1)))))
2960 /* See if the SETs in I1 or I2 need to be kept around in the merged
2961 instruction: whenever the value set there is still needed past I3.
2962 For the SETs in I2, this is easy: we see if I2DEST dies or is set in I3.
2964 For the SET in I1, we have two cases: If I1 and I2 independently
2965 feed into I3, the set in I1 needs to be kept around if I1DEST dies
2966 or is set in I3. Otherwise (if I1 feeds I2 which feeds I3), the set
2967 in I1 needs to be kept around unless I1DEST dies or is set in either
2968 I2 or I3. The same consideration applies to I0. */
2970 added_sets_2 = !dead_or_set_p (i3, i2dest);
2973 added_sets_1 = !(dead_or_set_p (i3, i1dest)
2974 || (i1_feeds_i2_n && dead_or_set_p (i2, i1dest)));
2979 added_sets_0 = !(dead_or_set_p (i3, i0dest)
2980 || (i0_feeds_i2_n && dead_or_set_p (i2, i0dest))
2981 || (i0_feeds_i1_n && dead_or_set_p (i1, i0dest)));
2985 /* We are about to copy insns for the case where they need to be kept
2986 around. Check that they can be copied in the merged instruction. */
2988 if (targetm.cannot_copy_insn_p
2989 && ((added_sets_2 && targetm.cannot_copy_insn_p (i2))
2990 || (i1 && added_sets_1 && targetm.cannot_copy_insn_p (i1))
2991 || (i0 && added_sets_0 && targetm.cannot_copy_insn_p (i0))))
2997 /* If the set in I2 needs to be kept around, we must make a copy of
2998 PATTERN (I2), so that when we substitute I1SRC for I1DEST in
2999 PATTERN (I2), we are only substituting for the original I1DEST, not into
3000 an already-substituted copy. This also prevents making self-referential
3001 rtx. If I2 is a PARALLEL, we just need the piece that assigns I2SRC to
3006 if (GET_CODE (PATTERN (i2)) == PARALLEL)
3007 i2pat = gen_rtx_SET (VOIDmode, i2dest, copy_rtx (i2src));
3009 i2pat = copy_rtx (PATTERN (i2));
3014 if (GET_CODE (PATTERN (i1)) == PARALLEL)
3015 i1pat = gen_rtx_SET (VOIDmode, i1dest, copy_rtx (i1src));
3017 i1pat = copy_rtx (PATTERN (i1));
3022 if (GET_CODE (PATTERN (i0)) == PARALLEL)
3023 i0pat = gen_rtx_SET (VOIDmode, i0dest, copy_rtx (i0src));
3025 i0pat = copy_rtx (PATTERN (i0));
3030 /* Substitute in the latest insn for the regs set by the earlier ones. */
3032 maxreg = max_reg_num ();
3037 /* Many machines that don't use CC0 have insns that can both perform an
3038 arithmetic operation and set the condition code. These operations will
3039 be represented as a PARALLEL with the first element of the vector
3040 being a COMPARE of an arithmetic operation with the constant zero.
3041 The second element of the vector will set some pseudo to the result
3042 of the same arithmetic operation. If we simplify the COMPARE, we won't
3043 match such a pattern and so will generate an extra insn. Here we test
3044 for this case, where both the comparison and the operation result are
3045 needed, and make the PARALLEL by just replacing I2DEST in I3SRC with
3046 I2SRC. Later we will make the PARALLEL that contains I2. */
3048 if (i1 == 0 && added_sets_2 && GET_CODE (PATTERN (i3)) == SET
3049 && GET_CODE (SET_SRC (PATTERN (i3))) == COMPARE
3050 && XEXP (SET_SRC (PATTERN (i3)), 1) == const0_rtx
3051 && rtx_equal_p (XEXP (SET_SRC (PATTERN (i3)), 0), i2dest))
3053 #ifdef SELECT_CC_MODE
3055 enum machine_mode compare_mode;
3058 newpat = PATTERN (i3);
3059 SUBST (XEXP (SET_SRC (newpat), 0), i2src);
3063 #ifdef SELECT_CC_MODE
3064 /* See if a COMPARE with the operand we substituted in should be done
3065 with the mode that is currently being used. If not, do the same
3066 processing we do in `subst' for a SET; namely, if the destination
3067 is used only once, try to replace it with a register of the proper
3068 mode and also replace the COMPARE. */
3069 if (undobuf.other_insn == 0
3070 && (cc_use = find_single_use (SET_DEST (newpat), i3,
3071 &undobuf.other_insn))
3072 && ((compare_mode = SELECT_CC_MODE (GET_CODE (*cc_use),
3074 != GET_MODE (SET_DEST (newpat))))
3076 if (can_change_dest_mode (SET_DEST (newpat), added_sets_2,
3079 unsigned int regno = REGNO (SET_DEST (newpat));
3082 if (regno < FIRST_PSEUDO_REGISTER)
3083 new_dest = gen_rtx_REG (compare_mode, regno);
3086 SUBST_MODE (regno_reg_rtx[regno], compare_mode);
3087 new_dest = regno_reg_rtx[regno];
3090 SUBST (SET_DEST (newpat), new_dest);
3091 SUBST (XEXP (*cc_use, 0), new_dest);
3092 SUBST (SET_SRC (newpat),
3093 gen_rtx_COMPARE (compare_mode, i2src, const0_rtx));
3096 undobuf.other_insn = 0;
3103 /* It is possible that the source of I2 or I1 may be performing
3104 an unneeded operation, such as a ZERO_EXTEND of something
3105 that is known to have the high part zero. Handle that case
3106 by letting subst look at the inner insns.
3108 Another way to do this would be to have a function that tries
3109 to simplify a single insn instead of merging two or more
3110 insns. We don't do this because of the potential of infinite
3111 loops and because of the potential extra memory required.
3112 However, doing it the way we are is a bit of a kludge and
3113 doesn't catch all cases.
3115 But only do this if -fexpensive-optimizations since it slows
3116 things down and doesn't usually win.
3118 This is not done in the COMPARE case above because the
3119 unmodified I2PAT is used in the PARALLEL and so a pattern
3120 with a modified I2SRC would not match. */
3122 if (flag_expensive_optimizations)
3124 /* Pass pc_rtx so no substitutions are done, just
3128 subst_low_luid = DF_INSN_LUID (i1);
3129 i1src = subst (i1src, pc_rtx, pc_rtx, 0, 0);
3132 subst_low_luid = DF_INSN_LUID (i2);
3133 i2src = subst (i2src, pc_rtx, pc_rtx, 0, 0);
3136 n_occurrences = 0; /* `subst' counts here */
3137 subst_low_luid = DF_INSN_LUID (i2);
3139 /* If I1 feeds into I2 and I1DEST is in I1SRC, we need to make a unique
3140 copy of I2SRC each time we substitute it, in order to avoid creating
3141 self-referential RTL when we will be substituting I1SRC for I1DEST
3142 later. Likewise if I0 feeds into I2, either directly or indirectly
3143 through I1, and I0DEST is in I0SRC. */
3144 newpat = subst (PATTERN (i3), i2dest, i2src, 0,
3145 (i1_feeds_i2_n && i1dest_in_i1src)
3146 || ((i0_feeds_i2_n || (i0_feeds_i1_n && i1_feeds_i2_n))
3147 && i0dest_in_i0src));
3150 /* Record whether I2's body now appears within I3's body. */
3151 i2_is_used = n_occurrences;
3154 /* If we already got a failure, don't try to do more. Otherwise, try to
3155 substitute I1 if we have it. */
3157 if (i1 && GET_CODE (newpat) != CLOBBER)
3159 /* Check that an autoincrement side-effect on I1 has not been lost.
3160 This happens if I1DEST is mentioned in I2 and dies there, and
3161 has disappeared from the new pattern. */
3162 if ((FIND_REG_INC_NOTE (i1, NULL_RTX) != 0
3164 && dead_or_set_p (i2, i1dest)
3165 && !reg_overlap_mentioned_p (i1dest, newpat))
3166 /* Before we can do this substitution, we must redo the test done
3167 above (see detailed comments there) that ensures I1DEST isn't
3168 mentioned in any SETs in NEWPAT that are field assignments. */
3169 || !combinable_i3pat (NULL_RTX, &newpat, i1dest, NULL_RTX, NULL_RTX,
3177 subst_low_luid = DF_INSN_LUID (i1);
3179 /* If I0 feeds into I1 and I0DEST is in I0SRC, we need to make a unique
3180 copy of I1SRC each time we substitute it, in order to avoid creating
3181 self-referential RTL when we will be substituting I0SRC for I0DEST
3183 newpat = subst (newpat, i1dest, i1src, 0,
3184 i0_feeds_i1_n && i0dest_in_i0src);
3187 /* Record whether I1's body now appears within I3's body. */
3188 i1_is_used = n_occurrences;
3191 /* Likewise for I0 if we have it. */
3193 if (i0 && GET_CODE (newpat) != CLOBBER)
3195 if ((FIND_REG_INC_NOTE (i0, NULL_RTX) != 0
3196 && ((i0_feeds_i2_n && dead_or_set_p (i2, i0dest))
3197 || (i0_feeds_i1_n && dead_or_set_p (i1, i0dest)))
3198 && !reg_overlap_mentioned_p (i0dest, newpat))
3199 || !combinable_i3pat (NULL_RTX, &newpat, i0dest, NULL_RTX, NULL_RTX,
3206 /* If the following substitution will modify I1SRC, make a copy of it
3207 for the case where it is substituted for I1DEST in I2PAT later. */
3208 if (i0_feeds_i1_n && added_sets_2 && i1_feeds_i2_n)
3209 i1src_copy = copy_rtx (i1src);
3212 subst_low_luid = DF_INSN_LUID (i0);
3213 newpat = subst (newpat, i0dest, i0src, 0, 0);
3217 /* Fail if an autoincrement side-effect has been duplicated. Be careful
3218 to count all the ways that I2SRC and I1SRC can be used. */
3219 if ((FIND_REG_INC_NOTE (i2, NULL_RTX) != 0
3220 && i2_is_used + added_sets_2 > 1)
3221 || (i1 != 0 && FIND_REG_INC_NOTE (i1, NULL_RTX) != 0
3222 && (i1_is_used + added_sets_1 + (added_sets_2 && i1_feeds_i2_n)
3224 || (i0 != 0 && FIND_REG_INC_NOTE (i0, NULL_RTX) != 0
3225 && (n_occurrences + added_sets_0
3226 + (added_sets_1 && i0_feeds_i1_n)
3227 + (added_sets_2 && i0_feeds_i2_n)
3229 /* Fail if we tried to make a new register. */
3230 || max_reg_num () != maxreg
3231 /* Fail if we couldn't do something and have a CLOBBER. */
3232 || GET_CODE (newpat) == CLOBBER
3233 /* Fail if this new pattern is a MULT and we didn't have one before
3234 at the outer level. */
3235 || (GET_CODE (newpat) == SET && GET_CODE (SET_SRC (newpat)) == MULT
3242 /* If the actions of the earlier insns must be kept
3243 in addition to substituting them into the latest one,
3244 we must make a new PARALLEL for the latest insn
3245 to hold additional the SETs. */
3247 if (added_sets_0 || added_sets_1 || added_sets_2)
3249 int extra_sets = added_sets_0 + added_sets_1 + added_sets_2;
3252 if (GET_CODE (newpat) == PARALLEL)
3254 rtvec old = XVEC (newpat, 0);
3255 total_sets = XVECLEN (newpat, 0) + extra_sets;
3256 newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (total_sets));
3257 memcpy (XVEC (newpat, 0)->elem, &old->elem[0],
3258 sizeof (old->elem[0]) * old->num_elem);
3263 total_sets = 1 + extra_sets;
3264 newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (total_sets));
3265 XVECEXP (newpat, 0, 0) = old;
3269 XVECEXP (newpat, 0, --total_sets) = i0pat;
3275 t = subst (t, i0dest, i0src, 0, 0);
3277 XVECEXP (newpat, 0, --total_sets) = t;
3283 t = subst (t, i1dest, i1src_copy ? i1src_copy : i1src, 0,
3284 i0_feeds_i1_n && i0dest_in_i0src);
3285 if ((i0_feeds_i1_n && i1_feeds_i2_n) || i0_feeds_i2_n)
3286 t = subst (t, i0dest, i0src, 0, 0);
3288 XVECEXP (newpat, 0, --total_sets) = t;
3292 validate_replacement:
3294 /* Note which hard regs this insn has as inputs. */
3295 mark_used_regs_combine (newpat);
3297 /* If recog_for_combine fails, it strips existing clobbers. If we'll
3298 consider splitting this pattern, we might need these clobbers. */
3299 if (i1 && GET_CODE (newpat) == PARALLEL
3300 && GET_CODE (XVECEXP (newpat, 0, XVECLEN (newpat, 0) - 1)) == CLOBBER)
3302 int len = XVECLEN (newpat, 0);
3304 newpat_vec_with_clobbers = rtvec_alloc (len);
3305 for (i = 0; i < len; i++)
3306 RTVEC_ELT (newpat_vec_with_clobbers, i) = XVECEXP (newpat, 0, i);
3309 /* Is the result of combination a valid instruction? */
3310 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
3312 /* If the result isn't valid, see if it is a PARALLEL of two SETs where
3313 the second SET's destination is a register that is unused and isn't
3314 marked as an instruction that might trap in an EH region. In that case,
3315 we just need the first SET. This can occur when simplifying a divmod
3316 insn. We *must* test for this case here because the code below that
3317 splits two independent SETs doesn't handle this case correctly when it
3318 updates the register status.
3320 It's pointless doing this if we originally had two sets, one from
3321 i3, and one from i2. Combining then splitting the parallel results
3322 in the original i2 again plus an invalid insn (which we delete).
3323 The net effect is only to move instructions around, which makes
3324 debug info less accurate.
3326 Also check the case where the first SET's destination is unused.
3327 That would not cause incorrect code, but does cause an unneeded
3330 if (insn_code_number < 0
3331 && !(added_sets_2 && i1 == 0)
3332 && GET_CODE (newpat) == PARALLEL
3333 && XVECLEN (newpat, 0) == 2
3334 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
3335 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
3336 && asm_noperands (newpat) < 0)
3338 rtx set0 = XVECEXP (newpat, 0, 0);
3339 rtx set1 = XVECEXP (newpat, 0, 1);
3341 if (((REG_P (SET_DEST (set1))
3342 && find_reg_note (i3, REG_UNUSED, SET_DEST (set1)))
3343 || (GET_CODE (SET_DEST (set1)) == SUBREG
3344 && find_reg_note (i3, REG_UNUSED, SUBREG_REG (SET_DEST (set1)))))
3345 && insn_nothrow_p (i3)
3346 && !side_effects_p (SET_SRC (set1)))
3349 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
3352 else if (((REG_P (SET_DEST (set0))
3353 && find_reg_note (i3, REG_UNUSED, SET_DEST (set0)))
3354 || (GET_CODE (SET_DEST (set0)) == SUBREG
3355 && find_reg_note (i3, REG_UNUSED,
3356 SUBREG_REG (SET_DEST (set0)))))
3357 && insn_nothrow_p (i3)
3358 && !side_effects_p (SET_SRC (set0)))
3361 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
3363 if (insn_code_number >= 0)
3364 changed_i3_dest = 1;
3368 /* If we were combining three insns and the result is a simple SET
3369 with no ASM_OPERANDS that wasn't recognized, try to split it into two
3370 insns. There are two ways to do this. It can be split using a
3371 machine-specific method (like when you have an addition of a large
3372 constant) or by combine in the function find_split_point. */
3374 if (i1 && insn_code_number < 0 && GET_CODE (newpat) == SET
3375 && asm_noperands (newpat) < 0)
3377 rtx parallel, m_split, *split;
3379 /* See if the MD file can split NEWPAT. If it can't, see if letting it
3380 use I2DEST as a scratch register will help. In the latter case,
3381 convert I2DEST to the mode of the source of NEWPAT if we can. */
3383 m_split = combine_split_insns (newpat, i3);
3385 /* We can only use I2DEST as a scratch reg if it doesn't overlap any
3386 inputs of NEWPAT. */
3388 /* ??? If I2DEST is not safe, and I1DEST exists, then it would be
3389 possible to try that as a scratch reg. This would require adding
3390 more code to make it work though. */
3392 if (m_split == 0 && ! reg_overlap_mentioned_p (i2dest, newpat))
3394 enum machine_mode new_mode = GET_MODE (SET_DEST (newpat));
3396 /* First try to split using the original register as a
3397 scratch register. */
3398 parallel = gen_rtx_PARALLEL (VOIDmode,
3399 gen_rtvec (2, newpat,
3400 gen_rtx_CLOBBER (VOIDmode,
3402 m_split = combine_split_insns (parallel, i3);
3404 /* If that didn't work, try changing the mode of I2DEST if
3407 && new_mode != GET_MODE (i2dest)
3408 && new_mode != VOIDmode
3409 && can_change_dest_mode (i2dest, added_sets_2, new_mode))
3411 enum machine_mode old_mode = GET_MODE (i2dest);
3414 if (REGNO (i2dest) < FIRST_PSEUDO_REGISTER)
3415 ni2dest = gen_rtx_REG (new_mode, REGNO (i2dest));
3418 SUBST_MODE (regno_reg_rtx[REGNO (i2dest)], new_mode);
3419 ni2dest = regno_reg_rtx[REGNO (i2dest)];
3422 parallel = (gen_rtx_PARALLEL
3424 gen_rtvec (2, newpat,
3425 gen_rtx_CLOBBER (VOIDmode,
3427 m_split = combine_split_insns (parallel, i3);
3430 && REGNO (i2dest) >= FIRST_PSEUDO_REGISTER)
3434 adjust_reg_mode (regno_reg_rtx[REGNO (i2dest)], old_mode);
3435 buf = undobuf.undos;
3436 undobuf.undos = buf->next;
3437 buf->next = undobuf.frees;
3438 undobuf.frees = buf;
3442 i2scratch = m_split != 0;
3445 /* If recog_for_combine has discarded clobbers, try to use them
3446 again for the split. */
3447 if (m_split == 0 && newpat_vec_with_clobbers)
3449 parallel = gen_rtx_PARALLEL (VOIDmode, newpat_vec_with_clobbers);
3450 m_split = combine_split_insns (parallel, i3);
3453 if (m_split && NEXT_INSN (m_split) == NULL_RTX)
3455 m_split = PATTERN (m_split);
3456 insn_code_number = recog_for_combine (&m_split, i3, &new_i3_notes);
3457 if (insn_code_number >= 0)
3460 else if (m_split && NEXT_INSN (NEXT_INSN (m_split)) == NULL_RTX
3461 && (next_real_insn (i2) == i3
3462 || ! use_crosses_set_p (PATTERN (m_split), DF_INSN_LUID (i2))))
3465 rtx newi3pat = PATTERN (NEXT_INSN (m_split));
3466 newi2pat = PATTERN (m_split);
3468 i3set = single_set (NEXT_INSN (m_split));
3469 i2set = single_set (m_split);
3471 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
3473 /* If I2 or I3 has multiple SETs, we won't know how to track
3474 register status, so don't use these insns. If I2's destination
3475 is used between I2 and I3, we also can't use these insns. */
3477 if (i2_code_number >= 0 && i2set && i3set
3478 && (next_real_insn (i2) == i3
3479 || ! reg_used_between_p (SET_DEST (i2set), i2, i3)))
3480 insn_code_number = recog_for_combine (&newi3pat, i3,
3482 if (insn_code_number >= 0)
3485 /* It is possible that both insns now set the destination of I3.
3486 If so, we must show an extra use of it. */
3488 if (insn_code_number >= 0)
3490 rtx new_i3_dest = SET_DEST (i3set);
3491 rtx new_i2_dest = SET_DEST (i2set);
3493 while (GET_CODE (new_i3_dest) == ZERO_EXTRACT
3494 || GET_CODE (new_i3_dest) == STRICT_LOW_PART
3495 || GET_CODE (new_i3_dest) == SUBREG)
3496 new_i3_dest = XEXP (new_i3_dest, 0);
3498 while (GET_CODE (new_i2_dest) == ZERO_EXTRACT
3499 || GET_CODE (new_i2_dest) == STRICT_LOW_PART
3500 || GET_CODE (new_i2_dest) == SUBREG)
3501 new_i2_dest = XEXP (new_i2_dest, 0);
3503 if (REG_P (new_i3_dest)
3504 && REG_P (new_i2_dest)
3505 && REGNO (new_i3_dest) == REGNO (new_i2_dest))
3506 INC_REG_N_SETS (REGNO (new_i2_dest), 1);
3510 /* If we can split it and use I2DEST, go ahead and see if that
3511 helps things be recognized. Verify that none of the registers
3512 are set between I2 and I3. */
3513 if (insn_code_number < 0
3514 && (split = find_split_point (&newpat, i3, false)) != 0
3518 /* We need I2DEST in the proper mode. If it is a hard register
3519 or the only use of a pseudo, we can change its mode.
3520 Make sure we don't change a hard register to have a mode that
3521 isn't valid for it, or change the number of registers. */
3522 && (GET_MODE (*split) == GET_MODE (i2dest)
3523 || GET_MODE (*split) == VOIDmode
3524 || can_change_dest_mode (i2dest, added_sets_2,
3526 && (next_real_insn (i2) == i3
3527 || ! use_crosses_set_p (*split, DF_INSN_LUID (i2)))
3528 /* We can't overwrite I2DEST if its value is still used by
3530 && ! reg_referenced_p (i2dest, newpat))
3532 rtx newdest = i2dest;
3533 enum rtx_code split_code = GET_CODE (*split);
3534 enum machine_mode split_mode = GET_MODE (*split);
3535 bool subst_done = false;
3536 newi2pat = NULL_RTX;
3540 /* *SPLIT may be part of I2SRC, so make sure we have the
3541 original expression around for later debug processing.
3542 We should not need I2SRC any more in other cases. */
3543 if (MAY_HAVE_DEBUG_INSNS)
3544 i2src = copy_rtx (i2src);
3548 /* Get NEWDEST as a register in the proper mode. We have already
3549 validated that we can do this. */
3550 if (GET_MODE (i2dest) != split_mode && split_mode != VOIDmode)
3552 if (REGNO (i2dest) < FIRST_PSEUDO_REGISTER)
3553 newdest = gen_rtx_REG (split_mode, REGNO (i2dest));
3556 SUBST_MODE (regno_reg_rtx[REGNO (i2dest)], split_mode);
3557 newdest = regno_reg_rtx[REGNO (i2dest)];
3561 /* If *SPLIT is a (mult FOO (const_int pow2)), convert it to
3562 an ASHIFT. This can occur if it was inside a PLUS and hence
3563 appeared to be a memory address. This is a kludge. */
3564 if (split_code == MULT
3565 && CONST_INT_P (XEXP (*split, 1))
3566 && INTVAL (XEXP (*split, 1)) > 0
3567 && (i = exact_log2 (UINTVAL (XEXP (*split, 1)))) >= 0)
3569 SUBST (*split, gen_rtx_ASHIFT (split_mode,
3570 XEXP (*split, 0), GEN_INT (i)));
3571 /* Update split_code because we may not have a multiply
3573 split_code = GET_CODE (*split);
3576 #ifdef INSN_SCHEDULING
3577 /* If *SPLIT is a paradoxical SUBREG, when we split it, it should
3578 be written as a ZERO_EXTEND. */
3579 if (split_code == SUBREG && MEM_P (SUBREG_REG (*split)))
3581 #ifdef LOAD_EXTEND_OP
3582 /* Or as a SIGN_EXTEND if LOAD_EXTEND_OP says that that's
3583 what it really is. */
3584 if (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (*split)))
3586 SUBST (*split, gen_rtx_SIGN_EXTEND (split_mode,
3587 SUBREG_REG (*split)));
3590 SUBST (*split, gen_rtx_ZERO_EXTEND (split_mode,
3591 SUBREG_REG (*split)));
3595 /* Attempt to split binary operators using arithmetic identities. */
3596 if (BINARY_P (SET_SRC (newpat))
3597 && split_mode == GET_MODE (SET_SRC (newpat))
3598 && ! side_effects_p (SET_SRC (newpat)))
3600 rtx setsrc = SET_SRC (newpat);
3601 enum machine_mode mode = GET_MODE (setsrc);
3602 enum rtx_code code = GET_CODE (setsrc);
3603 rtx src_op0 = XEXP (setsrc, 0);
3604 rtx src_op1 = XEXP (setsrc, 1);
3606 /* Split "X = Y op Y" as "Z = Y; X = Z op Z". */
3607 if (rtx_equal_p (src_op0, src_op1))
3609 newi2pat = gen_rtx_SET (VOIDmode, newdest, src_op0);
3610 SUBST (XEXP (setsrc, 0), newdest);
3611 SUBST (XEXP (setsrc, 1), newdest);
3614 /* Split "((P op Q) op R) op S" where op is PLUS or MULT. */
3615 else if ((code == PLUS || code == MULT)
3616 && GET_CODE (src_op0) == code
3617 && GET_CODE (XEXP (src_op0, 0)) == code
3618 && (INTEGRAL_MODE_P (mode)
3619 || (FLOAT_MODE_P (mode)
3620 && flag_unsafe_math_optimizations)))
3622 rtx p = XEXP (XEXP (src_op0, 0), 0);
3623 rtx q = XEXP (XEXP (src_op0, 0), 1);
3624 rtx r = XEXP (src_op0, 1);
3627 /* Split both "((X op Y) op X) op Y" and
3628 "((X op Y) op Y) op X" as "T op T" where T is
3630 if ((rtx_equal_p (p,r) && rtx_equal_p (q,s))
3631 || (rtx_equal_p (p,s) && rtx_equal_p (q,r)))
3633 newi2pat = gen_rtx_SET (VOIDmode, newdest,
3635 SUBST (XEXP (setsrc, 0), newdest);
3636 SUBST (XEXP (setsrc, 1), newdest);
3639 /* Split "((X op X) op Y) op Y)" as "T op T" where
3641 else if (rtx_equal_p (p,q) && rtx_equal_p (r,s))
3643 rtx tmp = simplify_gen_binary (code, mode, p, r);
3644 newi2pat = gen_rtx_SET (VOIDmode, newdest, tmp);
3645 SUBST (XEXP (setsrc, 0), newdest);
3646 SUBST (XEXP (setsrc, 1), newdest);
3654 newi2pat = gen_rtx_SET (VOIDmode, newdest, *split);
3655 SUBST (*split, newdest);
3658 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
3660 /* recog_for_combine might have added CLOBBERs to newi2pat.
3661 Make sure NEWPAT does not depend on the clobbered regs. */
3662 if (GET_CODE (newi2pat) == PARALLEL)
3663 for (i = XVECLEN (newi2pat, 0) - 1; i >= 0; i--)
3664 if (GET_CODE (XVECEXP (newi2pat, 0, i)) == CLOBBER)
3666 rtx reg = XEXP (XVECEXP (newi2pat, 0, i), 0);
3667 if (reg_overlap_mentioned_p (reg, newpat))
3674 /* If the split point was a MULT and we didn't have one before,
3675 don't use one now. */
3676 if (i2_code_number >= 0 && ! (split_code == MULT && ! have_mult))
3677 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
3681 /* Check for a case where we loaded from memory in a narrow mode and
3682 then sign extended it, but we need both registers. In that case,
3683 we have a PARALLEL with both loads from the same memory location.
3684 We can split this into a load from memory followed by a register-register
3685 copy. This saves at least one insn, more if register allocation can
3688 We cannot do this if the destination of the first assignment is a
3689 condition code register or cc0. We eliminate this case by making sure
3690 the SET_DEST and SET_SRC have the same mode.
3692 We cannot do this if the destination of the second assignment is
3693 a register that we have already assumed is zero-extended. Similarly
3694 for a SUBREG of such a register. */
3696 else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0
3697 && GET_CODE (newpat) == PARALLEL
3698 && XVECLEN (newpat, 0) == 2
3699 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
3700 && GET_CODE (SET_SRC (XVECEXP (newpat, 0, 0))) == SIGN_EXTEND
3701 && (GET_MODE (SET_DEST (XVECEXP (newpat, 0, 0)))
3702 == GET_MODE (SET_SRC (XVECEXP (newpat, 0, 0))))
3703 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
3704 && rtx_equal_p (SET_SRC (XVECEXP (newpat, 0, 1)),
3705 XEXP (SET_SRC (XVECEXP (newpat, 0, 0)), 0))
3706 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)),
3708 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
3709 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
3710 && ! (temp = SET_DEST (XVECEXP (newpat, 0, 1)),
3712 && VEC_index (reg_stat_type, reg_stat,
3713 REGNO (temp))->nonzero_bits != 0
3714 && GET_MODE_BITSIZE (GET_MODE (temp)) < BITS_PER_WORD
3715 && GET_MODE_BITSIZE (GET_MODE (temp)) < HOST_BITS_PER_INT
3716 && (VEC_index (reg_stat_type, reg_stat,
3717 REGNO (temp))->nonzero_bits
3718 != GET_MODE_MASK (word_mode))))
3719 && ! (GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) == SUBREG
3720 && (temp = SUBREG_REG (SET_DEST (XVECEXP (newpat, 0, 1))),
3722 && VEC_index (reg_stat_type, reg_stat,
3723 REGNO (temp))->nonzero_bits != 0
3724 && GET_MODE_BITSIZE (GET_MODE (temp)) < BITS_PER_WORD
3725 && GET_MODE_BITSIZE (GET_MODE (temp)) < HOST_BITS_PER_INT
3726 && (VEC_index (reg_stat_type, reg_stat,
3727 REGNO (temp))->nonzero_bits
3728 != GET_MODE_MASK (word_mode)))))
3729 && ! reg_overlap_mentioned_p (SET_DEST (XVECEXP (newpat, 0, 1)),
3730 SET_SRC (XVECEXP (newpat, 0, 1)))
3731 && ! find_reg_note (i3, REG_UNUSED,
3732 SET_DEST (XVECEXP (newpat, 0, 0))))
3736 newi2pat = XVECEXP (newpat, 0, 0);
3737 ni2dest = SET_DEST (XVECEXP (newpat, 0, 0));
3738 newpat = XVECEXP (newpat, 0, 1);
3739 SUBST (SET_SRC (newpat),
3740 gen_lowpart (GET_MODE (SET_SRC (newpat)), ni2dest));
3741 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
3743 if (i2_code_number >= 0)
3744 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
3746 if (insn_code_number >= 0)
3750 /* Similarly, check for a case where we have a PARALLEL of two independent
3751 SETs but we started with three insns. In this case, we can do the sets
3752 as two separate insns. This case occurs when some SET allows two
3753 other insns to combine, but the destination of that SET is still live. */
3755 else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0
3756 && GET_CODE (newpat) == PARALLEL
3757 && XVECLEN (newpat, 0) == 2
3758 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
3759 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != ZERO_EXTRACT
3760 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != STRICT_LOW_PART
3761 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
3762 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
3763 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
3764 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 1)),
3765 XVECEXP (newpat, 0, 0))
3766 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 0)),
3767 XVECEXP (newpat, 0, 1))
3768 && ! (contains_muldiv (SET_SRC (XVECEXP (newpat, 0, 0)))
3769 && contains_muldiv (SET_SRC (XVECEXP (newpat, 0, 1)))))
3771 /* Normally, it doesn't matter which of the two is done first,
3772 but the one that references cc0 can't be the second, and
3773 one which uses any regs/memory set in between i2 and i3 can't
3775 if (!use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)),
3778 && !reg_referenced_p (cc0_rtx, XVECEXP (newpat, 0, 0))
3782 newi2pat = XVECEXP (newpat, 0, 1);
3783 newpat = XVECEXP (newpat, 0, 0);
3785 else if (!use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 0)),
3788 && !reg_referenced_p (cc0_rtx, XVECEXP (newpat, 0, 1))
3792 newi2pat = XVECEXP (newpat, 0, 0);
3793 newpat = XVECEXP (newpat, 0, 1);
3801 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
3803 if (i2_code_number >= 0)
3805 /* recog_for_combine might have added CLOBBERs to newi2pat.
3806 Make sure NEWPAT does not depend on the clobbered regs. */
3807 if (GET_CODE (newi2pat) == PARALLEL)
3809 for (i = XVECLEN (newi2pat, 0) - 1; i >= 0; i--)
3810 if (GET_CODE (XVECEXP (newi2pat, 0, i)) == CLOBBER)
3812 rtx reg = XEXP (XVECEXP (newi2pat, 0, i), 0);
3813 if (reg_overlap_mentioned_p (reg, newpat))
3821 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
3825 /* If it still isn't recognized, fail and change things back the way they
3827 if ((insn_code_number < 0
3828 /* Is the result a reasonable ASM_OPERANDS? */
3829 && (! check_asm_operands (newpat) || added_sets_1 || added_sets_2)))
3835 /* If we had to change another insn, make sure it is valid also. */
3836 if (undobuf.other_insn)
3838 CLEAR_HARD_REG_SET (newpat_used_regs);
3840 other_pat = PATTERN (undobuf.other_insn);
3841 other_code_number = recog_for_combine (&other_pat, undobuf.other_insn,
3844 if (other_code_number < 0 && ! check_asm_operands (other_pat))
3852 /* If I2 is the CC0 setter and I3 is the CC0 user then check whether
3853 they are adjacent to each other or not. */
3855 rtx p = prev_nonnote_insn (i3);
3856 if (p && p != i2 && NONJUMP_INSN_P (p) && newi2pat
3857 && sets_cc0_p (newi2pat))
3865 /* Only allow this combination if insn_rtx_costs reports that the
3866 replacement instructions are cheaper than the originals. */
3867 if (!combine_validate_cost (i0, i1, i2, i3, newpat, newi2pat, other_pat))
3873 if (MAY_HAVE_DEBUG_INSNS)
3877 for (undo = undobuf.undos; undo; undo = undo->next)
3878 if (undo->kind == UNDO_MODE)
3880 rtx reg = *undo->where.r;
3881 enum machine_mode new_mode = GET_MODE (reg);
3882 enum machine_mode old_mode = undo->old_contents.m;
3884 /* Temporarily revert mode back. */
3885 adjust_reg_mode (reg, old_mode);
3887 if (reg == i2dest && i2scratch)
3889 /* If we used i2dest as a scratch register with a
3890 different mode, substitute it for the original
3891 i2src while its original mode is temporarily
3892 restored, and then clear i2scratch so that we don't
3893 do it again later. */
3894 propagate_for_debug (i2, last_combined_insn, reg, i2src);
3896 /* Put back the new mode. */
3897 adjust_reg_mode (reg, new_mode);
3901 rtx tempreg = gen_raw_REG (old_mode, REGNO (reg));
3907 last = last_combined_insn;
3912 last = undobuf.other_insn;
3914 if (DF_INSN_LUID (last)
3915 < DF_INSN_LUID (last_combined_insn))
3916 last = last_combined_insn;
3919 /* We're dealing with a reg that changed mode but not
3920 meaning, so we want to turn it into a subreg for
3921 the new mode. However, because of REG sharing and
3922 because its mode had already changed, we have to do
3923 it in two steps. First, replace any debug uses of
3924 reg, with its original mode temporarily restored,
3925 with this copy we have created; then, replace the
3926 copy with the SUBREG of the original shared reg,
3927 once again changed to the new mode. */
3928 propagate_for_debug (first, last, reg, tempreg);
3929 adjust_reg_mode (reg, new_mode);
3930 propagate_for_debug (first, last, tempreg,
3931 lowpart_subreg (old_mode, reg, new_mode));
3936 /* If we will be able to accept this, we have made a
3937 change to the destination of I3. This requires us to
3938 do a few adjustments. */
3940 if (changed_i3_dest)
3942 PATTERN (i3) = newpat;
3943 adjust_for_new_dest (i3);
3946 /* We now know that we can do this combination. Merge the insns and
3947 update the status of registers and LOG_LINKS. */
3949 if (undobuf.other_insn)
3953 PATTERN (undobuf.other_insn) = other_pat;
3955 /* If any of the notes in OTHER_INSN were REG_UNUSED, ensure that they
3956 are still valid. Then add any non-duplicate notes added by
3957 recog_for_combine. */
3958 for (note = REG_NOTES (undobuf.other_insn); note; note = next)
3960 next = XEXP (note, 1);
3962 if (REG_NOTE_KIND (note) == REG_UNUSED
3963 && ! reg_set_p (XEXP (note, 0), PATTERN (undobuf.other_insn)))
3964 remove_note (undobuf.other_insn, note);
3967 distribute_notes (new_other_notes, undobuf.other_insn,
3968 undobuf.other_insn, NULL_RTX, NULL_RTX, NULL_RTX,
3975 struct insn_link *link;
3978 /* I3 now uses what used to be its destination and which is now
3979 I2's destination. This requires us to do a few adjustments. */
3980 PATTERN (i3) = newpat;
3981 adjust_for_new_dest (i3);
3983 /* We need a LOG_LINK from I3 to I2. But we used to have one,
3986 However, some later insn might be using I2's dest and have
3987 a LOG_LINK pointing at I3. We must remove this link.
3988 The simplest way to remove the link is to point it at I1,
3989 which we know will be a NOTE. */
3991 /* newi2pat is usually a SET here; however, recog_for_combine might
3992 have added some clobbers. */
3993 if (GET_CODE (newi2pat) == PARALLEL)
3994 ni2dest = SET_DEST (XVECEXP (newi2pat, 0, 0));
3996 ni2dest = SET_DEST (newi2pat);
3998 for (insn = NEXT_INSN (i3);
3999 insn && (this_basic_block->next_bb == EXIT_BLOCK_PTR
4000 || insn != BB_HEAD (this_basic_block->next_bb));
4001 insn = NEXT_INSN (insn))
4003 if (INSN_P (insn) && reg_referenced_p (ni2dest, PATTERN (insn)))
4005 FOR_EACH_LOG_LINK (link, insn)
4006 if (link->insn == i3)
4015 rtx i3notes, i2notes, i1notes = 0, i0notes = 0;
4016 struct insn_link *i3links, *i2links, *i1links = 0, *i0links = 0;
4019 /* Compute which registers we expect to eliminate. newi2pat may be setting
4020 either i3dest or i2dest, so we must check it. Also, i1dest may be the
4021 same as i3dest, in which case newi2pat may be setting i1dest. */
4022 rtx elim_i2 = ((newi2pat && reg_set_p (i2dest, newi2pat))
4023 || i2dest_in_i2src || i2dest_in_i1src || i2dest_in_i0src
4026 rtx elim_i1 = (i1 == 0 || i1dest_in_i1src || i1dest_in_i0src
4027 || (newi2pat && reg_set_p (i1dest, newi2pat))
4030 rtx elim_i0 = (i0 == 0 || i0dest_in_i0src
4031 || (newi2pat && reg_set_p (i0dest, newi2pat))
4035 /* Get the old REG_NOTES and LOG_LINKS from all our insns and
4037 i3notes = REG_NOTES (i3), i3links = LOG_LINKS (i3);
4038 i2notes = REG_NOTES (i2), i2links = LOG_LINKS (i2);
4040 i1notes = REG_NOTES (i1), i1links = LOG_LINKS (i1);
4042 i0notes = REG_NOTES (i0), i0links = LOG_LINKS (i0);
4044 /* Ensure that we do not have something that should not be shared but
4045 occurs multiple times in the new insns. Check this by first
4046 resetting all the `used' flags and then copying anything is shared. */
4048 reset_used_flags (i3notes);
4049 reset_used_flags (i2notes);
4050 reset_used_flags (i1notes);
4051 reset_used_flags (i0notes);
4052 reset_used_flags (newpat);
4053 reset_used_flags (newi2pat);
4054 if (undobuf.other_insn)
4055 reset_used_flags (PATTERN (undobuf.other_insn));
4057 i3notes = copy_rtx_if_shared (i3notes);
4058 i2notes = copy_rtx_if_shared (i2notes);
4059 i1notes = copy_rtx_if_shared (i1notes);
4060 i0notes = copy_rtx_if_shared (i0notes);
4061 newpat = copy_rtx_if_shared (newpat);
4062 newi2pat = copy_rtx_if_shared (newi2pat);
4063 if (undobuf.other_insn)
4064 reset_used_flags (PATTERN (undobuf.other_insn));
4066 INSN_CODE (i3) = insn_code_number;
4067 PATTERN (i3) = newpat;
4069 if (CALL_P (i3) && CALL_INSN_FUNCTION_USAGE (i3))
4071 rtx call_usage = CALL_INSN_FUNCTION_USAGE (i3);
4073 reset_used_flags (call_usage);
4074 call_usage = copy_rtx (call_usage);
4078 /* I2SRC must still be meaningful at this point. Some splitting
4079 operations can invalidate I2SRC, but those operations do not
4082 replace_rtx (call_usage, i2dest, i2src);
4086 replace_rtx (call_usage, i1dest, i1src);
4088 replace_rtx (call_usage, i0dest, i0src);
4090 CALL_INSN_FUNCTION_USAGE (i3) = call_usage;
4093 if (undobuf.other_insn)
4094 INSN_CODE (undobuf.other_insn) = other_code_number;
4096 /* We had one special case above where I2 had more than one set and
4097 we replaced a destination of one of those sets with the destination
4098 of I3. In that case, we have to update LOG_LINKS of insns later
4099 in this basic block. Note that this (expensive) case is rare.
4101 Also, in this case, we must pretend that all REG_NOTEs for I2
4102 actually came from I3, so that REG_UNUSED notes from I2 will be
4103 properly handled. */
4105 if (i3_subst_into_i2)
4107 for (i = 0; i < XVECLEN (PATTERN (i2), 0); i++)
4108 if ((GET_CODE (XVECEXP (PATTERN (i2), 0, i)) == SET
4109 || GET_CODE (XVECEXP (PATTERN (i2), 0, i)) == CLOBBER)
4110 && REG_P (SET_DEST (XVECEXP (PATTERN (i2), 0, i)))
4111 && SET_DEST (XVECEXP (PATTERN (i2), 0, i)) != i2dest
4112 && ! find_reg_note (i2, REG_UNUSED,
4113 SET_DEST (XVECEXP (PATTERN (i2), 0, i))))
4114 for (temp = NEXT_INSN (i2);
4115 temp && (this_basic_block->next_bb == EXIT_BLOCK_PTR
4116 || BB_HEAD (this_basic_block) != temp);
4117 temp = NEXT_INSN (temp))
4118 if (temp != i3 && INSN_P (temp))
4119 FOR_EACH_LOG_LINK (link, temp)
4120 if (link->insn == i2)
4126 while (XEXP (link, 1))
4127 link = XEXP (link, 1);
4128 XEXP (link, 1) = i2notes;
4135 LOG_LINKS (i3) = NULL;
4137 LOG_LINKS (i2) = NULL;
4142 if (MAY_HAVE_DEBUG_INSNS && i2scratch)
4143 propagate_for_debug (i2, last_combined_insn, i2dest, i2src);
4144 INSN_CODE (i2) = i2_code_number;
4145 PATTERN (i2) = newi2pat;
4149 if (MAY_HAVE_DEBUG_INSNS && i2src)
4150 propagate_for_debug (i2, last_combined_insn, i2dest, i2src);
4151 SET_INSN_DELETED (i2);
4156 LOG_LINKS (i1) = NULL;
4158 if (MAY_HAVE_DEBUG_INSNS)
4159 propagate_for_debug (i1, last_combined_insn, i1dest, i1src);
4160 SET_INSN_DELETED (i1);
4165 LOG_LINKS (i0) = NULL;
4167 if (MAY_HAVE_DEBUG_INSNS)
4168 propagate_for_debug (i0, last_combined_insn, i0dest, i0src);
4169 SET_INSN_DELETED (i0);
4172 /* Get death notes for everything that is now used in either I3 or
4173 I2 and used to die in a previous insn. If we built two new
4174 patterns, move from I1 to I2 then I2 to I3 so that we get the
4175 proper movement on registers that I2 modifies. */
4178 from_luid = DF_INSN_LUID (i0);
4180 from_luid = DF_INSN_LUID (i1);
4182 from_luid = DF_INSN_LUID (i2);
4184 move_deaths (newi2pat, NULL_RTX, from_luid, i2, &midnotes);
4185 move_deaths (newpat, newi2pat, from_luid, i3, &midnotes);
4187 /* Distribute all the LOG_LINKS and REG_NOTES from I1, I2, and I3. */
4189 distribute_notes (i3notes, i3, i3, newi2pat ? i2 : NULL_RTX,
4190 elim_i2, elim_i1, elim_i0);
4192 distribute_notes (i2notes, i2, i3, newi2pat ? i2 : NULL_RTX,
4193 elim_i2, elim_i1, elim_i0);
4195 distribute_notes (i1notes, i1, i3, newi2pat ? i2 : NULL_RTX,
4196 elim_i2, elim_i1, elim_i0);
4198 distribute_notes (i0notes, i0, i3, newi2pat ? i2 : NULL_RTX,
4199 elim_i2, elim_i1, elim_i0);
4201 distribute_notes (midnotes, NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
4202 elim_i2, elim_i1, elim_i0);
4204 /* Distribute any notes added to I2 or I3 by recog_for_combine. We
4205 know these are REG_UNUSED and want them to go to the desired insn,
4206 so we always pass it as i3. */
4208 if (newi2pat && new_i2_notes)
4209 distribute_notes (new_i2_notes, i2, i2, NULL_RTX, NULL_RTX, NULL_RTX,
4213 distribute_notes (new_i3_notes, i3, i3, NULL_RTX, NULL_RTX, NULL_RTX,
4216 /* If I3DEST was used in I3SRC, it really died in I3. We may need to
4217 put a REG_DEAD note for it somewhere. If NEWI2PAT exists and sets
4218 I3DEST, the death must be somewhere before I2, not I3. If we passed I3
4219 in that case, it might delete I2. Similarly for I2 and I1.
4220 Show an additional death due to the REG_DEAD note we make here. If
4221 we discard it in distribute_notes, we will decrement it again. */
4225 if (newi2pat && reg_set_p (i3dest_killed, newi2pat))
4226 distribute_notes (alloc_reg_note (REG_DEAD, i3dest_killed,
4228 NULL_RTX, i2, NULL_RTX, elim_i2, elim_i1, elim_i0);
4230 distribute_notes (alloc_reg_note (REG_DEAD, i3dest_killed,
4232 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
4233 elim_i2, elim_i1, elim_i0);
4236 if (i2dest_in_i2src)
4238 rtx new_note = alloc_reg_note (REG_DEAD, i2dest, NULL_RTX);
4239 if (newi2pat && reg_set_p (i2dest, newi2pat))
4240 distribute_notes (new_note, NULL_RTX, i2, NULL_RTX, NULL_RTX,
4241 NULL_RTX, NULL_RTX);
4243 distribute_notes (new_note, NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
4244 NULL_RTX, NULL_RTX, NULL_RTX);
4247 if (i1dest_in_i1src)
4249 rtx new_note = alloc_reg_note (REG_DEAD, i1dest, NULL_RTX);
4250 if (newi2pat && reg_set_p (i1dest, newi2pat))
4251 distribute_notes (new_note, NULL_RTX, i2, NULL_RTX, NULL_RTX,
4252 NULL_RTX, NULL_RTX);
4254 distribute_notes (new_note, NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
4255 NULL_RTX, NULL_RTX, NULL_RTX);
4258 if (i0dest_in_i0src)
4260 rtx new_note = alloc_reg_note (REG_DEAD, i0dest, NULL_RTX);
4261 if (newi2pat && reg_set_p (i0dest, newi2pat))
4262 distribute_notes (new_note, NULL_RTX, i2, NULL_RTX, NULL_RTX,
4263 NULL_RTX, NULL_RTX);
4265 distribute_notes (new_note, NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
4266 NULL_RTX, NULL_RTX, NULL_RTX);
4269 distribute_links (i3links);
4270 distribute_links (i2links);
4271 distribute_links (i1links);
4272 distribute_links (i0links);
4276 struct insn_link *link;
4277 rtx i2_insn = 0, i2_val = 0, set;
4279 /* The insn that used to set this register doesn't exist, and
4280 this life of the register may not exist either. See if one of
4281 I3's links points to an insn that sets I2DEST. If it does,
4282 that is now the last known value for I2DEST. If we don't update
4283 this and I2 set the register to a value that depended on its old
4284 contents, we will get confused. If this insn is used, thing
4285 will be set correctly in combine_instructions. */
4286 FOR_EACH_LOG_LINK (link, i3)
4287 if ((set = single_set (link->insn)) != 0
4288 && rtx_equal_p (i2dest, SET_DEST (set)))
4289 i2_insn = link->insn, i2_val = SET_SRC (set);
4291 record_value_for_reg (i2dest, i2_insn, i2_val);
4293 /* If the reg formerly set in I2 died only once and that was in I3,
4294 zero its use count so it won't make `reload' do any work. */
4296 && (newi2pat == 0 || ! reg_mentioned_p (i2dest, newi2pat))
4297 && ! i2dest_in_i2src)
4298 INC_REG_N_SETS (REGNO (i2dest), -1);
4301 if (i1 && REG_P (i1dest))
4303 struct insn_link *link;
4304 rtx i1_insn = 0, i1_val = 0, set;
4306 FOR_EACH_LOG_LINK (link, i3)
4307 if ((set = single_set (link->insn)) != 0
4308 && rtx_equal_p (i1dest, SET_DEST (set)))
4309 i1_insn = link->insn, i1_val = SET_SRC (set);
4311 record_value_for_reg (i1dest, i1_insn, i1_val);
4313 if (! added_sets_1 && ! i1dest_in_i1src)
4314 INC_REG_N_SETS (REGNO (i1dest), -1);
4317 if (i0 && REG_P (i0dest))
4319 struct insn_link *link;
4320 rtx i0_insn = 0, i0_val = 0, set;
4322 FOR_EACH_LOG_LINK (link, i3)
4323 if ((set = single_set (link->insn)) != 0
4324 && rtx_equal_p (i0dest, SET_DEST (set)))
4325 i0_insn = link->insn, i0_val = SET_SRC (set);
4327 record_value_for_reg (i0dest, i0_insn, i0_val);
4329 if (! added_sets_0 && ! i0dest_in_i0src)
4330 INC_REG_N_SETS (REGNO (i0dest), -1);
4333 /* Update reg_stat[].nonzero_bits et al for any changes that may have
4334 been made to this insn. The order of
4335 set_nonzero_bits_and_sign_copies() is important. Because newi2pat
4336 can affect nonzero_bits of newpat */
4338 note_stores (newi2pat, set_nonzero_bits_and_sign_copies, NULL);
4339 note_stores (newpat, set_nonzero_bits_and_sign_copies, NULL);
4342 if (undobuf.other_insn != NULL_RTX)
4346 fprintf (dump_file, "modifying other_insn ");
4347 dump_insn_slim (dump_file, undobuf.other_insn);
4349 df_insn_rescan (undobuf.other_insn);
4352 if (i0 && !(NOTE_P(i0) && (NOTE_KIND (i0) == NOTE_INSN_DELETED)))
4356 fprintf (dump_file, "modifying insn i1 ");
4357 dump_insn_slim (dump_file, i0);
4359 df_insn_rescan (i0);
4362 if (i1 && !(NOTE_P(i1) && (NOTE_KIND (i1) == NOTE_INSN_DELETED)))
4366 fprintf (dump_file, "modifying insn i1 ");
4367 dump_insn_slim (dump_file, i1);
4369 df_insn_rescan (i1);
4372 if (i2 && !(NOTE_P(i2) && (NOTE_KIND (i2) == NOTE_INSN_DELETED)))
4376 fprintf (dump_file, "modifying insn i2 ");
4377 dump_insn_slim (dump_file, i2);
4379 df_insn_rescan (i2);
4382 if (i3 && !(NOTE_P(i3) && (NOTE_KIND (i3) == NOTE_INSN_DELETED)))
4386 fprintf (dump_file, "modifying insn i3 ");
4387 dump_insn_slim (dump_file, i3);
4389 df_insn_rescan (i3);
4392 /* Set new_direct_jump_p if a new return or simple jump instruction
4393 has been created. Adjust the CFG accordingly. */
4395 if (returnjump_p (i3) || any_uncondjump_p (i3))
4397 *new_direct_jump_p = 1;
4398 mark_jump_label (PATTERN (i3), i3, 0);
4399 update_cfg_for_uncondjump (i3);
4402 if (undobuf.other_insn != NULL_RTX
4403 && (returnjump_p (undobuf.other_insn)
4404 || any_uncondjump_p (undobuf.other_insn)))
4406 *new_direct_jump_p = 1;
4407 update_cfg_for_uncondjump (undobuf.other_insn);
4410 /* A noop might also need cleaning up of CFG, if it comes from the
4411 simplification of a jump. */
4412 if (GET_CODE (newpat) == SET
4413 && SET_SRC (newpat) == pc_rtx
4414 && SET_DEST (newpat) == pc_rtx)
4416 *new_direct_jump_p = 1;
4417 update_cfg_for_uncondjump (i3);
4420 if (undobuf.other_insn != NULL_RTX
4421 && GET_CODE (PATTERN (undobuf.other_insn)) == SET
4422 && SET_SRC (PATTERN (undobuf.other_insn)) == pc_rtx
4423 && SET_DEST (PATTERN (undobuf.other_insn)) == pc_rtx)
4425 *new_direct_jump_p = 1;
4426 update_cfg_for_uncondjump (undobuf.other_insn);
4429 combine_successes++;
4432 if (added_links_insn
4433 && (newi2pat == 0 || DF_INSN_LUID (added_links_insn) < DF_INSN_LUID (i2))
4434 && DF_INSN_LUID (added_links_insn) < DF_INSN_LUID (i3))
4435 return added_links_insn;
4437 return newi2pat ? i2 : i3;
4440 /* Undo all the modifications recorded in undobuf. */
4445 struct undo *undo, *next;
4447 for (undo = undobuf.undos; undo; undo = next)
4453 *undo->where.r = undo->old_contents.r;
4456 *undo->where.i = undo->old_contents.i;
4459 adjust_reg_mode (*undo->where.r, undo->old_contents.m);
4465 undo->next = undobuf.frees;
4466 undobuf.frees = undo;
4472 /* We've committed to accepting the changes we made. Move all
4473 of the undos to the free list. */
4478 struct undo *undo, *next;
4480 for (undo = undobuf.undos; undo; undo = next)
4483 undo->next = undobuf.frees;
4484 undobuf.frees = undo;
4489 /* Find the innermost point within the rtx at LOC, possibly LOC itself,
4490 where we have an arithmetic expression and return that point. LOC will
4493 try_combine will call this function to see if an insn can be split into
4497 find_split_point (rtx *loc, rtx insn, bool set_src)
4500 enum rtx_code code = GET_CODE (x);
4502 unsigned HOST_WIDE_INT len = 0;
4503 HOST_WIDE_INT pos = 0;
4505 rtx inner = NULL_RTX;
4507 /* First special-case some codes. */
4511 #ifdef INSN_SCHEDULING
4512 /* If we are making a paradoxical SUBREG invalid, it becomes a split
4514 if (MEM_P (SUBREG_REG (x)))
4517 return find_split_point (&SUBREG_REG (x), insn, false);
4521 /* If we have (mem (const ..)) or (mem (symbol_ref ...)), split it
4522 using LO_SUM and HIGH. */
4523 if (GET_CODE (XEXP (x, 0)) == CONST
4524 || GET_CODE (XEXP (x, 0)) == SYMBOL_REF)
4526 enum machine_mode address_mode
4527 = targetm.addr_space.address_mode (MEM_ADDR_SPACE (x));
4530 gen_rtx_LO_SUM (address_mode,
4531 gen_rtx_HIGH (address_mode, XEXP (x, 0)),
4533 return &XEXP (XEXP (x, 0), 0);
4537 /* If we have a PLUS whose second operand is a constant and the
4538 address is not valid, perhaps will can split it up using
4539 the machine-specific way to split large constants. We use
4540 the first pseudo-reg (one of the virtual regs) as a placeholder;
4541 it will not remain in the result. */
4542 if (GET_CODE (XEXP (x, 0)) == PLUS
4543 && CONST_INT_P (XEXP (XEXP (x, 0), 1))
4544 && ! memory_address_addr_space_p (GET_MODE (x), XEXP (x, 0),
4545 MEM_ADDR_SPACE (x)))
4547 rtx reg = regno_reg_rtx[FIRST_PSEUDO_REGISTER];
4548 rtx seq = combine_split_insns (gen_rtx_SET (VOIDmode, reg,
4552 /* This should have produced two insns, each of which sets our
4553 placeholder. If the source of the second is a valid address,
4554 we can make put both sources together and make a split point
4558 && NEXT_INSN (seq) != NULL_RTX
4559 && NEXT_INSN (NEXT_INSN (seq)) == NULL_RTX
4560 && NONJUMP_INSN_P (seq)
4561 && GET_CODE (PATTERN (seq)) == SET
4562 && SET_DEST (PATTERN (seq)) == reg
4563 && ! reg_mentioned_p (reg,
4564 SET_SRC (PATTERN (seq)))
4565 && NONJUMP_INSN_P (NEXT_INSN (seq))
4566 && GET_CODE (PATTERN (NEXT_INSN (seq))) == SET
4567 && SET_DEST (PATTERN (NEXT_INSN (seq))) == reg
4568 && memory_address_addr_space_p
4569 (GET_MODE (x), SET_SRC (PATTERN (NEXT_INSN (seq))),
4570 MEM_ADDR_SPACE (x)))
4572 rtx src1 = SET_SRC (PATTERN (seq));
4573 rtx src2 = SET_SRC (PATTERN (NEXT_INSN (seq)));
4575 /* Replace the placeholder in SRC2 with SRC1. If we can
4576 find where in SRC2 it was placed, that can become our
4577 split point and we can replace this address with SRC2.
4578 Just try two obvious places. */
4580 src2 = replace_rtx (src2, reg, src1);
4582 if (XEXP (src2, 0) == src1)
4583 split = &XEXP (src2, 0);
4584 else if (GET_RTX_FORMAT (GET_CODE (XEXP (src2, 0)))[0] == 'e'
4585 && XEXP (XEXP (src2, 0), 0) == src1)
4586 split = &XEXP (XEXP (src2, 0), 0);
4590 SUBST (XEXP (x, 0), src2);
4595 /* If that didn't work, perhaps the first operand is complex and
4596 needs to be computed separately, so make a split point there.
4597 This will occur on machines that just support REG + CONST
4598 and have a constant moved through some previous computation. */
4600 else if (!OBJECT_P (XEXP (XEXP (x, 0), 0))
4601 && ! (GET_CODE (XEXP (XEXP (x, 0), 0)) == SUBREG
4602 && OBJECT_P (SUBREG_REG (XEXP (XEXP (x, 0), 0)))))
4603 return &XEXP (XEXP (x, 0), 0);
4606 /* If we have a PLUS whose first operand is complex, try computing it
4607 separately by making a split there. */
4608 if (GET_CODE (XEXP (x, 0)) == PLUS
4609 && ! memory_address_addr_space_p (GET_MODE (x), XEXP (x, 0),
4611 && ! OBJECT_P (XEXP (XEXP (x, 0), 0))
4612 && ! (GET_CODE (XEXP (XEXP (x, 0), 0)) == SUBREG
4613 && OBJECT_P (SUBREG_REG (XEXP (XEXP (x, 0), 0)))))
4614 return &XEXP (XEXP (x, 0), 0);
4619 /* If SET_DEST is CC0 and SET_SRC is not an operand, a COMPARE, or a
4620 ZERO_EXTRACT, the most likely reason why this doesn't match is that
4621 we need to put the operand into a register. So split at that
4624 if (SET_DEST (x) == cc0_rtx
4625 && GET_CODE (SET_SRC (x)) != COMPARE
4626 && GET_CODE (SET_SRC (x)) != ZERO_EXTRACT
4627 && !OBJECT_P (SET_SRC (x))
4628 && ! (GET_CODE (SET_SRC (x)) == SUBREG
4629 && OBJECT_P (SUBREG_REG (SET_SRC (x)))))
4630 return &SET_SRC (x);
4633 /* See if we can split SET_SRC as it stands. */
4634 split = find_split_point (&SET_SRC (x), insn, true);
4635 if (split && split != &SET_SRC (x))
4638 /* See if we can split SET_DEST as it stands. */
4639 split = find_split_point (&SET_DEST (x), insn, false);
4640 if (split && split != &SET_DEST (x))
4643 /* See if this is a bitfield assignment with everything constant. If
4644 so, this is an IOR of an AND, so split it into that. */
4645 if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
4646 && (GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0)))
4647 <= HOST_BITS_PER_WIDE_INT)
4648 && CONST_INT_P (XEXP (SET_DEST (x), 1))
4649 && CONST_INT_P (XEXP (SET_DEST (x), 2))
4650 && CONST_INT_P (SET_SRC (x))
4651 && ((INTVAL (XEXP (SET_DEST (x), 1))
4652 + INTVAL (XEXP (SET_DEST (x), 2)))
4653 <= GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0))))
4654 && ! side_effects_p (XEXP (SET_DEST (x), 0)))
4656 HOST_WIDE_INT pos = INTVAL (XEXP (SET_DEST (x), 2));
4657 unsigned HOST_WIDE_INT len = INTVAL (XEXP (SET_DEST (x), 1));
4658 unsigned HOST_WIDE_INT src = INTVAL (SET_SRC (x));
4659 rtx dest = XEXP (SET_DEST (x), 0);
4660 enum machine_mode mode = GET_MODE (dest);
4661 unsigned HOST_WIDE_INT mask
4662 = ((unsigned HOST_WIDE_INT) 1 << len) - 1;
4665 if (BITS_BIG_ENDIAN)
4666 pos = GET_MODE_BITSIZE (mode) - len - pos;
4668 or_mask = gen_int_mode (src << pos, mode);
4671 simplify_gen_binary (IOR, mode, dest, or_mask));
4674 rtx negmask = gen_int_mode (~(mask << pos), mode);
4676 simplify_gen_binary (IOR, mode,
4677 simplify_gen_binary (AND, mode,
4682 SUBST (SET_DEST (x), dest);
4684 split = find_split_point (&SET_SRC (x), insn, true);
4685 if (split && split != &SET_SRC (x))
4689 /* Otherwise, see if this is an operation that we can split into two.
4690 If so, try to split that. */
4691 code = GET_CODE (SET_SRC (x));
4696 /* If we are AND'ing with a large constant that is only a single
4697 bit and the result is only being used in a context where we
4698 need to know if it is zero or nonzero, replace it with a bit
4699 extraction. This will avoid the large constant, which might
4700 have taken more than one insn to make. If the constant were
4701 not a valid argument to the AND but took only one insn to make,
4702 this is no worse, but if it took more than one insn, it will
4705 if (CONST_INT_P (XEXP (SET_SRC (x), 1))
4706 && REG_P (XEXP (SET_SRC (x), 0))
4707 && (pos = exact_log2 (UINTVAL (XEXP (SET_SRC (x), 1)))) >= 7
4708 && REG_P (SET_DEST (x))
4709 && (split = find_single_use (SET_DEST (x), insn, (rtx*) 0)) != 0
4710 && (GET_CODE (*split) == EQ || GET_CODE (*split) == NE)
4711 && XEXP (*split, 0) == SET_DEST (x)
4712 && XEXP (*split, 1) == const0_rtx)
4714 rtx extraction = make_extraction (GET_MODE (SET_DEST (x)),
4715 XEXP (SET_SRC (x), 0),
4716 pos, NULL_RTX, 1, 1, 0, 0);
4717 if (extraction != 0)
4719 SUBST (SET_SRC (x), extraction);
4720 return find_split_point (loc, insn, false);
4726 /* If STORE_FLAG_VALUE is -1, this is (NE X 0) and only one bit of X
4727 is known to be on, this can be converted into a NEG of a shift. */
4728 if (STORE_FLAG_VALUE == -1 && XEXP (SET_SRC (x), 1) == const0_rtx
4729 && GET_MODE (SET_SRC (x)) == GET_MODE (XEXP (SET_SRC (x), 0))
4730 && 1 <= (pos = exact_log2
4731 (nonzero_bits (XEXP (SET_SRC (x), 0),
4732 GET_MODE (XEXP (SET_SRC (x), 0))))))
4734 enum machine_mode mode = GET_MODE (XEXP (SET_SRC (x), 0));
4738 gen_rtx_LSHIFTRT (mode,
4739 XEXP (SET_SRC (x), 0),
4742 split = find_split_point (&SET_SRC (x), insn, true);
4743 if (split && split != &SET_SRC (x))
4749 inner = XEXP (SET_SRC (x), 0);
4751 /* We can't optimize if either mode is a partial integer
4752 mode as we don't know how many bits are significant
4754 if (GET_MODE_CLASS (GET_MODE (inner)) == MODE_PARTIAL_INT
4755 || GET_MODE_CLASS (GET_MODE (SET_SRC (x))) == MODE_PARTIAL_INT)
4759 len = GET_MODE_BITSIZE (GET_MODE (inner));
4765 if (CONST_INT_P (XEXP (SET_SRC (x), 1))
4766 && CONST_INT_P (XEXP (SET_SRC (x), 2)))
4768 inner = XEXP (SET_SRC (x), 0);
4769 len = INTVAL (XEXP (SET_SRC (x), 1));
4770 pos = INTVAL (XEXP (SET_SRC (x), 2));
4772 if (BITS_BIG_ENDIAN)
4773 pos = GET_MODE_BITSIZE (GET_MODE (inner)) - len - pos;
4774 unsignedp = (code == ZERO_EXTRACT);
4782 if (len && pos >= 0 && pos + len <= GET_MODE_BITSIZE (GET_MODE (inner)))
4784 enum machine_mode mode = GET_MODE (SET_SRC (x));
4786 /* For unsigned, we have a choice of a shift followed by an
4787 AND or two shifts. Use two shifts for field sizes where the
4788 constant might be too large. We assume here that we can
4789 always at least get 8-bit constants in an AND insn, which is
4790 true for every current RISC. */
4792 if (unsignedp && len <= 8)
4797 (mode, gen_lowpart (mode, inner),
4799 GEN_INT (((unsigned HOST_WIDE_INT) 1 << len)
4802 split = find_split_point (&SET_SRC (x), insn, true);
4803 if (split && split != &SET_SRC (x))
4810 (unsignedp ? LSHIFTRT : ASHIFTRT, mode,
4811 gen_rtx_ASHIFT (mode,
4812 gen_lowpart (mode, inner),
4813 GEN_INT (GET_MODE_BITSIZE (mode)
4815 GEN_INT (GET_MODE_BITSIZE (mode) - len)));
4817 split = find_split_point (&SET_SRC (x), insn, true);
4818 if (split && split != &SET_SRC (x))
4823 /* See if this is a simple operation with a constant as the second
4824 operand. It might be that this constant is out of range and hence
4825 could be used as a split point. */
4826 if (BINARY_P (SET_SRC (x))
4827 && CONSTANT_P (XEXP (SET_SRC (x), 1))
4828 && (OBJECT_P (XEXP (SET_SRC (x), 0))
4829 || (GET_CODE (XEXP (SET_SRC (x), 0)) == SUBREG
4830 && OBJECT_P (SUBREG_REG (XEXP (SET_SRC (x), 0))))))
4831 return &XEXP (SET_SRC (x), 1);
4833 /* Finally, see if this is a simple operation with its first operand
4834 not in a register. The operation might require this operand in a
4835 register, so return it as a split point. We can always do this
4836 because if the first operand were another operation, we would have
4837 already found it as a split point. */
4838 if ((BINARY_P (SET_SRC (x)) || UNARY_P (SET_SRC (x)))
4839 && ! register_operand (XEXP (SET_SRC (x), 0), VOIDmode))
4840 return &XEXP (SET_SRC (x), 0);
4846 /* We write NOR as (and (not A) (not B)), but if we don't have a NOR,
4847 it is better to write this as (not (ior A B)) so we can split it.
4848 Similarly for IOR. */
4849 if (GET_CODE (XEXP (x, 0)) == NOT && GET_CODE (XEXP (x, 1)) == NOT)
4852 gen_rtx_NOT (GET_MODE (x),
4853 gen_rtx_fmt_ee (code == IOR ? AND : IOR,
4855 XEXP (XEXP (x, 0), 0),
4856 XEXP (XEXP (x, 1), 0))));
4857 return find_split_point (loc, insn, set_src);
4860 /* Many RISC machines have a large set of logical insns. If the
4861 second operand is a NOT, put it first so we will try to split the
4862 other operand first. */
4863 if (GET_CODE (XEXP (x, 1)) == NOT)
4865 rtx tem = XEXP (x, 0);
4866 SUBST (XEXP (x, 0), XEXP (x, 1));
4867 SUBST (XEXP (x, 1), tem);
4873 /* Canonicalization can produce (minus A (mult B C)), where C is a
4874 constant. It may be better to try splitting (plus (mult B -C) A)
4875 instead if this isn't a multiply by a power of two. */
4876 if (set_src && code == MINUS && GET_CODE (XEXP (x, 1)) == MULT
4877 && GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT
4878 && exact_log2 (INTVAL (XEXP (XEXP (x, 1), 1))) < 0)
4880 enum machine_mode mode = GET_MODE (x);
4881 unsigned HOST_WIDE_INT this_int = INTVAL (XEXP (XEXP (x, 1), 1));
4882 HOST_WIDE_INT other_int = trunc_int_for_mode (-this_int, mode);
4883 SUBST (*loc, gen_rtx_PLUS (mode, gen_rtx_MULT (mode,
4884 XEXP (XEXP (x, 1), 0),
4885 GEN_INT (other_int)),
4887 return find_split_point (loc, insn, set_src);
4890 /* Split at a multiply-accumulate instruction. However if this is
4891 the SET_SRC, we likely do not have such an instruction and it's
4892 worthless to try this split. */
4893 if (!set_src && GET_CODE (XEXP (x, 0)) == MULT)
4900 /* Otherwise, select our actions depending on our rtx class. */
4901 switch (GET_RTX_CLASS (code))
4903 case RTX_BITFIELD_OPS: /* This is ZERO_EXTRACT and SIGN_EXTRACT. */
4905 split = find_split_point (&XEXP (x, 2), insn, false);
4908 /* ... fall through ... */
4910 case RTX_COMM_ARITH:
4912 case RTX_COMM_COMPARE:
4913 split = find_split_point (&XEXP (x, 1), insn, false);
4916 /* ... fall through ... */
4918 /* Some machines have (and (shift ...) ...) insns. If X is not
4919 an AND, but XEXP (X, 0) is, use it as our split point. */
4920 if (GET_CODE (x) != AND && GET_CODE (XEXP (x, 0)) == AND)
4921 return &XEXP (x, 0);
4923 split = find_split_point (&XEXP (x, 0), insn, false);
4929 /* Otherwise, we don't have a split point. */
4934 /* Throughout X, replace FROM with TO, and return the result.
4935 The result is TO if X is FROM;
4936 otherwise the result is X, but its contents may have been modified.
4937 If they were modified, a record was made in undobuf so that
4938 undo_all will (among other things) return X to its original state.
4940 If the number of changes necessary is too much to record to undo,
4941 the excess changes are not made, so the result is invalid.
4942 The changes already made can still be undone.
4943 undobuf.num_undo is incremented for such changes, so by testing that
4944 the caller can tell whether the result is valid.
4946 `n_occurrences' is incremented each time FROM is replaced.
4948 IN_DEST is nonzero if we are processing the SET_DEST of a SET.
4950 UNIQUE_COPY is nonzero if each substitution must be unique. We do this
4951 by copying if `n_occurrences' is nonzero. */
4954 subst (rtx x, rtx from, rtx to, int in_dest, int unique_copy)
4956 enum rtx_code code = GET_CODE (x);
4957 enum machine_mode op0_mode = VOIDmode;
4962 /* Two expressions are equal if they are identical copies of a shared
4963 RTX or if they are both registers with the same register number
4966 #define COMBINE_RTX_EQUAL_P(X,Y) \
4968 || (REG_P (X) && REG_P (Y) \
4969 && REGNO (X) == REGNO (Y) && GET_MODE (X) == GET_MODE (Y)))
4971 if (! in_dest && COMBINE_RTX_EQUAL_P (x, from))
4974 return (unique_copy && n_occurrences > 1 ? copy_rtx (to) : to);
4977 /* If X and FROM are the same register but different modes, they
4978 will not have been seen as equal above. However, the log links code
4979 will make a LOG_LINKS entry for that case. If we do nothing, we
4980 will try to rerecognize our original insn and, when it succeeds,
4981 we will delete the feeding insn, which is incorrect.
4983 So force this insn not to match in this (rare) case. */
4984 if (! in_dest && code == REG && REG_P (from)
4985 && reg_overlap_mentioned_p (x, from))
4986 return gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
4988 /* If this is an object, we are done unless it is a MEM or LO_SUM, both
4989 of which may contain things that can be combined. */
4990 if (code != MEM && code != LO_SUM && OBJECT_P (x))
4993 /* It is possible to have a subexpression appear twice in the insn.
4994 Suppose that FROM is a register that appears within TO.
4995 Then, after that subexpression has been scanned once by `subst',
4996 the second time it is scanned, TO may be found. If we were
4997 to scan TO here, we would find FROM within it and create a
4998 self-referent rtl structure which is completely wrong. */
4999 if (COMBINE_RTX_EQUAL_P (x, to))
5002 /* Parallel asm_operands need special attention because all of the
5003 inputs are shared across the arms. Furthermore, unsharing the
5004 rtl results in recognition failures. Failure to handle this case
5005 specially can result in circular rtl.
5007 Solve this by doing a normal pass across the first entry of the
5008 parallel, and only processing the SET_DESTs of the subsequent
5011 if (code == PARALLEL
5012 && GET_CODE (XVECEXP (x, 0, 0)) == SET
5013 && GET_CODE (SET_SRC (XVECEXP (x, 0, 0))) == ASM_OPERANDS)
5015 new_rtx = subst (XVECEXP (x, 0, 0), from, to, 0, unique_copy);
5017 /* If this substitution failed, this whole thing fails. */
5018 if (GET_CODE (new_rtx) == CLOBBER
5019 && XEXP (new_rtx, 0) == const0_rtx)
5022 SUBST (XVECEXP (x, 0, 0), new_rtx);
5024 for (i = XVECLEN (x, 0) - 1; i >= 1; i--)
5026 rtx dest = SET_DEST (XVECEXP (x, 0, i));
5029 && GET_CODE (dest) != CC0
5030 && GET_CODE (dest) != PC)
5032 new_rtx = subst (dest, from, to, 0, unique_copy);
5034 /* If this substitution failed, this whole thing fails. */
5035 if (GET_CODE (new_rtx) == CLOBBER
5036 && XEXP (new_rtx, 0) == const0_rtx)
5039 SUBST (SET_DEST (XVECEXP (x, 0, i)), new_rtx);
5045 len = GET_RTX_LENGTH (code);
5046 fmt = GET_RTX_FORMAT (code);
5048 /* We don't need to process a SET_DEST that is a register, CC0,
5049 or PC, so set up to skip this common case. All other cases
5050 where we want to suppress replacing something inside a
5051 SET_SRC are handled via the IN_DEST operand. */
5053 && (REG_P (SET_DEST (x))
5054 || GET_CODE (SET_DEST (x)) == CC0
5055 || GET_CODE (SET_DEST (x)) == PC))
5058 /* Get the mode of operand 0 in case X is now a SIGN_EXTEND of a
5061 op0_mode = GET_MODE (XEXP (x, 0));
5063 for (i = 0; i < len; i++)
5068 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
5070 if (COMBINE_RTX_EQUAL_P (XVECEXP (x, i, j), from))
5072 new_rtx = (unique_copy && n_occurrences
5073 ? copy_rtx (to) : to);
5078 new_rtx = subst (XVECEXP (x, i, j), from, to, 0,
5081 /* If this substitution failed, this whole thing
5083 if (GET_CODE (new_rtx) == CLOBBER
5084 && XEXP (new_rtx, 0) == const0_rtx)
5088 SUBST (XVECEXP (x, i, j), new_rtx);
5091 else if (fmt[i] == 'e')
5093 /* If this is a register being set, ignore it. */
5094 new_rtx = XEXP (x, i);
5097 && (((code == SUBREG || code == ZERO_EXTRACT)
5099 || code == STRICT_LOW_PART))
5102 else if (COMBINE_RTX_EQUAL_P (XEXP (x, i), from))
5104 /* In general, don't install a subreg involving two
5105 modes not tieable. It can worsen register
5106 allocation, and can even make invalid reload
5107 insns, since the reg inside may need to be copied
5108 from in the outside mode, and that may be invalid
5109 if it is an fp reg copied in integer mode.
5111 We allow two exceptions to this: It is valid if
5112 it is inside another SUBREG and the mode of that
5113 SUBREG and the mode of the inside of TO is
5114 tieable and it is valid if X is a SET that copies
5117 if (GET_CODE (to) == SUBREG
5118 && ! MODES_TIEABLE_P (GET_MODE (to),
5119 GET_MODE (SUBREG_REG (to)))
5120 && ! (code == SUBREG
5121 && MODES_TIEABLE_P (GET_MODE (x),
5122 GET_MODE (SUBREG_REG (to))))
5124 && ! (code == SET && i == 1 && XEXP (x, 0) == cc0_rtx)
5127 return gen_rtx_CLOBBER (VOIDmode, const0_rtx);
5129 #ifdef CANNOT_CHANGE_MODE_CLASS
5132 && REGNO (to) < FIRST_PSEUDO_REGISTER
5133 && REG_CANNOT_CHANGE_MODE_P (REGNO (to),
5136 return gen_rtx_CLOBBER (VOIDmode, const0_rtx);
5139 new_rtx = (unique_copy && n_occurrences ? copy_rtx (to) : to);
5143 /* If we are in a SET_DEST, suppress most cases unless we
5144 have gone inside a MEM, in which case we want to
5145 simplify the address. We assume here that things that
5146 are actually part of the destination have their inner
5147 parts in the first expression. This is true for SUBREG,
5148 STRICT_LOW_PART, and ZERO_EXTRACT, which are the only
5149 things aside from REG and MEM that should appear in a
5151 new_rtx = subst (XEXP (x, i), from, to,
5153 && (code == SUBREG || code == STRICT_LOW_PART
5154 || code == ZERO_EXTRACT))
5156 && i == 0), unique_copy);
5158 /* If we found that we will have to reject this combination,
5159 indicate that by returning the CLOBBER ourselves, rather than
5160 an expression containing it. This will speed things up as
5161 well as prevent accidents where two CLOBBERs are considered
5162 to be equal, thus producing an incorrect simplification. */
5164 if (GET_CODE (new_rtx) == CLOBBER && XEXP (new_rtx, 0) == const0_rtx)
5167 if (GET_CODE (x) == SUBREG
5168 && (CONST_INT_P (new_rtx)
5169 || GET_CODE (new_rtx) == CONST_DOUBLE))
5171 enum machine_mode mode = GET_MODE (x);
5173 x = simplify_subreg (GET_MODE (x), new_rtx,
5174 GET_MODE (SUBREG_REG (x)),
5177 x = gen_rtx_CLOBBER (mode, const0_rtx);
5179 else if (CONST_INT_P (new_rtx)
5180 && GET_CODE (x) == ZERO_EXTEND)
5182 x = simplify_unary_operation (ZERO_EXTEND, GET_MODE (x),
5183 new_rtx, GET_MODE (XEXP (x, 0)));
5187 SUBST (XEXP (x, i), new_rtx);
5192 /* Check if we are loading something from the constant pool via float
5193 extension; in this case we would undo compress_float_constant
5194 optimization and degenerate constant load to an immediate value. */
5195 if (GET_CODE (x) == FLOAT_EXTEND
5196 && MEM_P (XEXP (x, 0))
5197 && MEM_READONLY_P (XEXP (x, 0)))
5199 rtx tmp = avoid_constant_pool_reference (x);
5204 /* Try to simplify X. If the simplification changed the code, it is likely
5205 that further simplification will help, so loop, but limit the number
5206 of repetitions that will be performed. */
5208 for (i = 0; i < 4; i++)
5210 /* If X is sufficiently simple, don't bother trying to do anything
5212 if (code != CONST_INT && code != REG && code != CLOBBER)
5213 x = combine_simplify_rtx (x, op0_mode, in_dest);
5215 if (GET_CODE (x) == code)
5218 code = GET_CODE (x);
5220 /* We no longer know the original mode of operand 0 since we
5221 have changed the form of X) */
5222 op0_mode = VOIDmode;
5228 /* Simplify X, a piece of RTL. We just operate on the expression at the
5229 outer level; call `subst' to simplify recursively. Return the new
5232 OP0_MODE is the original mode of XEXP (x, 0). IN_DEST is nonzero
5233 if we are inside a SET_DEST. */
5236 combine_simplify_rtx (rtx x, enum machine_mode op0_mode, int in_dest)
5238 enum rtx_code code = GET_CODE (x);
5239 enum machine_mode mode = GET_MODE (x);
5243 /* If this is a commutative operation, put a constant last and a complex
5244 expression first. We don't need to do this for comparisons here. */
5245 if (COMMUTATIVE_ARITH_P (x)
5246 && swap_commutative_operands_p (XEXP (x, 0), XEXP (x, 1)))
5249 SUBST (XEXP (x, 0), XEXP (x, 1));
5250 SUBST (XEXP (x, 1), temp);
5253 /* If this is a simple operation applied to an IF_THEN_ELSE, try
5254 applying it to the arms of the IF_THEN_ELSE. This often simplifies
5255 things. Check for cases where both arms are testing the same
5258 Don't do anything if all operands are very simple. */
5261 && ((!OBJECT_P (XEXP (x, 0))
5262 && ! (GET_CODE (XEXP (x, 0)) == SUBREG
5263 && OBJECT_P (SUBREG_REG (XEXP (x, 0)))))
5264 || (!OBJECT_P (XEXP (x, 1))
5265 && ! (GET_CODE (XEXP (x, 1)) == SUBREG
5266 && OBJECT_P (SUBREG_REG (XEXP (x, 1)))))))
5268 && (!OBJECT_P (XEXP (x, 0))
5269 && ! (GET_CODE (XEXP (x, 0)) == SUBREG
5270 && OBJECT_P (SUBREG_REG (XEXP (x, 0)))))))
5272 rtx cond, true_rtx, false_rtx;
5274 cond = if_then_else_cond (x, &true_rtx, &false_rtx);
5276 /* If everything is a comparison, what we have is highly unlikely
5277 to be simpler, so don't use it. */
5278 && ! (COMPARISON_P (x)
5279 && (COMPARISON_P (true_rtx) || COMPARISON_P (false_rtx))))
5281 rtx cop1 = const0_rtx;
5282 enum rtx_code cond_code = simplify_comparison (NE, &cond, &cop1);
5284 if (cond_code == NE && COMPARISON_P (cond))
5287 /* Simplify the alternative arms; this may collapse the true and
5288 false arms to store-flag values. Be careful to use copy_rtx
5289 here since true_rtx or false_rtx might share RTL with x as a
5290 result of the if_then_else_cond call above. */
5291 true_rtx = subst (copy_rtx (true_rtx), pc_rtx, pc_rtx, 0, 0);
5292 false_rtx = subst (copy_rtx (false_rtx), pc_rtx, pc_rtx, 0, 0);
5294 /* If true_rtx and false_rtx are not general_operands, an if_then_else
5295 is unlikely to be simpler. */
5296 if (general_operand (true_rtx, VOIDmode)
5297 && general_operand (false_rtx, VOIDmode))
5299 enum rtx_code reversed;
5301 /* Restarting if we generate a store-flag expression will cause
5302 us to loop. Just drop through in this case. */
5304 /* If the result values are STORE_FLAG_VALUE and zero, we can
5305 just make the comparison operation. */
5306 if (true_rtx == const_true_rtx && false_rtx == const0_rtx)
5307 x = simplify_gen_relational (cond_code, mode, VOIDmode,
5309 else if (true_rtx == const0_rtx && false_rtx == const_true_rtx
5310 && ((reversed = reversed_comparison_code_parts
5311 (cond_code, cond, cop1, NULL))
5313 x = simplify_gen_relational (reversed, mode, VOIDmode,
5316 /* Likewise, we can make the negate of a comparison operation
5317 if the result values are - STORE_FLAG_VALUE and zero. */
5318 else if (CONST_INT_P (true_rtx)
5319 && INTVAL (true_rtx) == - STORE_FLAG_VALUE
5320 && false_rtx == const0_rtx)
5321 x = simplify_gen_unary (NEG, mode,
5322 simplify_gen_relational (cond_code,
5326 else if (CONST_INT_P (false_rtx)
5327 && INTVAL (false_rtx) == - STORE_FLAG_VALUE
5328 && true_rtx == const0_rtx
5329 && ((reversed = reversed_comparison_code_parts
5330 (cond_code, cond, cop1, NULL))
5332 x = simplify_gen_unary (NEG, mode,
5333 simplify_gen_relational (reversed,
5338 return gen_rtx_IF_THEN_ELSE (mode,
5339 simplify_gen_relational (cond_code,
5344 true_rtx, false_rtx);
5346 code = GET_CODE (x);
5347 op0_mode = VOIDmode;
5352 /* Try to fold this expression in case we have constants that weren't
5355 switch (GET_RTX_CLASS (code))
5358 if (op0_mode == VOIDmode)
5359 op0_mode = GET_MODE (XEXP (x, 0));
5360 temp = simplify_unary_operation (code, mode, XEXP (x, 0), op0_mode);
5363 case RTX_COMM_COMPARE:
5365 enum machine_mode cmp_mode = GET_MODE (XEXP (x, 0));
5366 if (cmp_mode == VOIDmode)
5368 cmp_mode = GET_MODE (XEXP (x, 1));
5369 if (cmp_mode == VOIDmode)
5370 cmp_mode = op0_mode;
5372 temp = simplify_relational_operation (code, mode, cmp_mode,
5373 XEXP (x, 0), XEXP (x, 1));
5376 case RTX_COMM_ARITH:
5378 temp = simplify_binary_operation (code, mode, XEXP (x, 0), XEXP (x, 1));
5380 case RTX_BITFIELD_OPS:
5382 temp = simplify_ternary_operation (code, mode, op0_mode, XEXP (x, 0),
5383 XEXP (x, 1), XEXP (x, 2));
5392 code = GET_CODE (temp);
5393 op0_mode = VOIDmode;
5394 mode = GET_MODE (temp);
5397 /* First see if we can apply the inverse distributive law. */
5398 if (code == PLUS || code == MINUS
5399 || code == AND || code == IOR || code == XOR)
5401 x = apply_distributive_law (x);
5402 code = GET_CODE (x);
5403 op0_mode = VOIDmode;
5406 /* If CODE is an associative operation not otherwise handled, see if we
5407 can associate some operands. This can win if they are constants or
5408 if they are logically related (i.e. (a & b) & a). */
5409 if ((code == PLUS || code == MINUS || code == MULT || code == DIV
5410 || code == AND || code == IOR || code == XOR
5411 || code == SMAX || code == SMIN || code == UMAX || code == UMIN)
5412 && ((INTEGRAL_MODE_P (mode) && code != DIV)
5413 || (flag_associative_math && FLOAT_MODE_P (mode))))
5415 if (GET_CODE (XEXP (x, 0)) == code)
5417 rtx other = XEXP (XEXP (x, 0), 0);
5418 rtx inner_op0 = XEXP (XEXP (x, 0), 1);
5419 rtx inner_op1 = XEXP (x, 1);
5422 /* Make sure we pass the constant operand if any as the second
5423 one if this is a commutative operation. */
5424 if (CONSTANT_P (inner_op0) && COMMUTATIVE_ARITH_P (x))
5426 rtx tem = inner_op0;
5427 inner_op0 = inner_op1;
5430 inner = simplify_binary_operation (code == MINUS ? PLUS
5431 : code == DIV ? MULT
5433 mode, inner_op0, inner_op1);
5435 /* For commutative operations, try the other pair if that one
5437 if (inner == 0 && COMMUTATIVE_ARITH_P (x))
5439 other = XEXP (XEXP (x, 0), 1);
5440 inner = simplify_binary_operation (code, mode,
5441 XEXP (XEXP (x, 0), 0),
5446 return simplify_gen_binary (code, mode, other, inner);
5450 /* A little bit of algebraic simplification here. */
5454 /* Ensure that our address has any ASHIFTs converted to MULT in case
5455 address-recognizing predicates are called later. */
5456 temp = make_compound_operation (XEXP (x, 0), MEM);
5457 SUBST (XEXP (x, 0), temp);
5461 if (op0_mode == VOIDmode)
5462 op0_mode = GET_MODE (SUBREG_REG (x));
5464 /* See if this can be moved to simplify_subreg. */
5465 if (CONSTANT_P (SUBREG_REG (x))
5466 && subreg_lowpart_offset (mode, op0_mode) == SUBREG_BYTE (x)
5467 /* Don't call gen_lowpart if the inner mode
5468 is VOIDmode and we cannot simplify it, as SUBREG without
5469 inner mode is invalid. */
5470 && (GET_MODE (SUBREG_REG (x)) != VOIDmode
5471 || gen_lowpart_common (mode, SUBREG_REG (x))))
5472 return gen_lowpart (mode, SUBREG_REG (x));
5474 if (GET_MODE_CLASS (GET_MODE (SUBREG_REG (x))) == MODE_CC)
5478 temp = simplify_subreg (mode, SUBREG_REG (x), op0_mode,
5484 /* Don't change the mode of the MEM if that would change the meaning
5486 if (MEM_P (SUBREG_REG (x))
5487 && (MEM_VOLATILE_P (SUBREG_REG (x))
5488 || mode_dependent_address_p (XEXP (SUBREG_REG (x), 0))))
5489 return gen_rtx_CLOBBER (mode, const0_rtx);
5491 /* Note that we cannot do any narrowing for non-constants since
5492 we might have been counting on using the fact that some bits were
5493 zero. We now do this in the SET. */
5498 temp = expand_compound_operation (XEXP (x, 0));
5500 /* For C equal to the width of MODE minus 1, (neg (ashiftrt X C)) can be
5501 replaced by (lshiftrt X C). This will convert
5502 (neg (sign_extract X 1 Y)) to (zero_extract X 1 Y). */
5504 if (GET_CODE (temp) == ASHIFTRT
5505 && CONST_INT_P (XEXP (temp, 1))
5506 && INTVAL (XEXP (temp, 1)) == GET_MODE_BITSIZE (mode) - 1)
5507 return simplify_shift_const (NULL_RTX, LSHIFTRT, mode, XEXP (temp, 0),
5508 INTVAL (XEXP (temp, 1)));
5510 /* If X has only a single bit that might be nonzero, say, bit I, convert
5511 (neg X) to (ashiftrt (ashift X C-I) C-I) where C is the bitsize of
5512 MODE minus 1. This will convert (neg (zero_extract X 1 Y)) to
5513 (sign_extract X 1 Y). But only do this if TEMP isn't a register
5514 or a SUBREG of one since we'd be making the expression more
5515 complex if it was just a register. */
5518 && ! (GET_CODE (temp) == SUBREG
5519 && REG_P (SUBREG_REG (temp)))
5520 && (i = exact_log2 (nonzero_bits (temp, mode))) >= 0)
5522 rtx temp1 = simplify_shift_const
5523 (NULL_RTX, ASHIFTRT, mode,
5524 simplify_shift_const (NULL_RTX, ASHIFT, mode, temp,
5525 GET_MODE_BITSIZE (mode) - 1 - i),
5526 GET_MODE_BITSIZE (mode) - 1 - i);
5528 /* If all we did was surround TEMP with the two shifts, we
5529 haven't improved anything, so don't use it. Otherwise,
5530 we are better off with TEMP1. */
5531 if (GET_CODE (temp1) != ASHIFTRT
5532 || GET_CODE (XEXP (temp1, 0)) != ASHIFT
5533 || XEXP (XEXP (temp1, 0), 0) != temp)
5539 /* We can't handle truncation to a partial integer mode here
5540 because we don't know the real bitsize of the partial
5542 if (GET_MODE_CLASS (mode) == MODE_PARTIAL_INT)
5545 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
5547 force_to_mode (XEXP (x, 0), GET_MODE (XEXP (x, 0)),
5548 GET_MODE_MASK (mode), 0));
5550 /* We can truncate a constant value and return it. */
5551 if (CONST_INT_P (XEXP (x, 0)))
5552 return gen_int_mode (INTVAL (XEXP (x, 0)), mode);
5554 /* Similarly to what we do in simplify-rtx.c, a truncate of a register
5555 whose value is a comparison can be replaced with a subreg if
5556 STORE_FLAG_VALUE permits. */
5557 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5558 && (STORE_FLAG_VALUE & ~GET_MODE_MASK (mode)) == 0
5559 && (temp = get_last_value (XEXP (x, 0)))
5560 && COMPARISON_P (temp))
5561 return gen_lowpart (mode, XEXP (x, 0));
5565 /* (const (const X)) can become (const X). Do it this way rather than
5566 returning the inner CONST since CONST can be shared with a
5568 if (GET_CODE (XEXP (x, 0)) == CONST)
5569 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
5574 /* Convert (lo_sum (high FOO) FOO) to FOO. This is necessary so we
5575 can add in an offset. find_split_point will split this address up
5576 again if it doesn't match. */
5577 if (GET_CODE (XEXP (x, 0)) == HIGH
5578 && rtx_equal_p (XEXP (XEXP (x, 0), 0), XEXP (x, 1)))
5584 /* (plus (xor (and <foo> (const_int pow2 - 1)) <c>) <-c>)
5585 when c is (const_int (pow2 + 1) / 2) is a sign extension of a
5586 bit-field and can be replaced by either a sign_extend or a
5587 sign_extract. The `and' may be a zero_extend and the two
5588 <c>, -<c> constants may be reversed. */
5589 if (GET_CODE (XEXP (x, 0)) == XOR
5590 && CONST_INT_P (XEXP (x, 1))
5591 && CONST_INT_P (XEXP (XEXP (x, 0), 1))
5592 && INTVAL (XEXP (x, 1)) == -INTVAL (XEXP (XEXP (x, 0), 1))
5593 && ((i = exact_log2 (UINTVAL (XEXP (XEXP (x, 0), 1)))) >= 0
5594 || (i = exact_log2 (UINTVAL (XEXP (x, 1)))) >= 0)
5595 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5596 && ((GET_CODE (XEXP (XEXP (x, 0), 0)) == AND
5597 && CONST_INT_P (XEXP (XEXP (XEXP (x, 0), 0), 1))
5598 && (UINTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1))
5599 == ((unsigned HOST_WIDE_INT) 1 << (i + 1)) - 1))
5600 || (GET_CODE (XEXP (XEXP (x, 0), 0)) == ZERO_EXTEND
5601 && (GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)))
5602 == (unsigned int) i + 1))))
5603 return simplify_shift_const
5604 (NULL_RTX, ASHIFTRT, mode,
5605 simplify_shift_const (NULL_RTX, ASHIFT, mode,
5606 XEXP (XEXP (XEXP (x, 0), 0), 0),
5607 GET_MODE_BITSIZE (mode) - (i + 1)),
5608 GET_MODE_BITSIZE (mode) - (i + 1));
5610 /* If only the low-order bit of X is possibly nonzero, (plus x -1)
5611 can become (ashiftrt (ashift (xor x 1) C) C) where C is
5612 the bitsize of the mode - 1. This allows simplification of
5613 "a = (b & 8) == 0;" */
5614 if (XEXP (x, 1) == constm1_rtx
5615 && !REG_P (XEXP (x, 0))
5616 && ! (GET_CODE (XEXP (x, 0)) == SUBREG
5617 && REG_P (SUBREG_REG (XEXP (x, 0))))
5618 && nonzero_bits (XEXP (x, 0), mode) == 1)
5619 return simplify_shift_const (NULL_RTX, ASHIFTRT, mode,
5620 simplify_shift_const (NULL_RTX, ASHIFT, mode,
5621 gen_rtx_XOR (mode, XEXP (x, 0), const1_rtx),
5622 GET_MODE_BITSIZE (mode) - 1),
5623 GET_MODE_BITSIZE (mode) - 1);
5625 /* If we are adding two things that have no bits in common, convert
5626 the addition into an IOR. This will often be further simplified,
5627 for example in cases like ((a & 1) + (a & 2)), which can
5630 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5631 && (nonzero_bits (XEXP (x, 0), mode)
5632 & nonzero_bits (XEXP (x, 1), mode)) == 0)
5634 /* Try to simplify the expression further. */
5635 rtx tor = simplify_gen_binary (IOR, mode, XEXP (x, 0), XEXP (x, 1));
5636 temp = combine_simplify_rtx (tor, mode, in_dest);
5638 /* If we could, great. If not, do not go ahead with the IOR
5639 replacement, since PLUS appears in many special purpose
5640 address arithmetic instructions. */
5641 if (GET_CODE (temp) != CLOBBER && temp != tor)
5647 /* (minus <foo> (and <foo> (const_int -pow2))) becomes
5648 (and <foo> (const_int pow2-1)) */
5649 if (GET_CODE (XEXP (x, 1)) == AND
5650 && CONST_INT_P (XEXP (XEXP (x, 1), 1))
5651 && exact_log2 (-UINTVAL (XEXP (XEXP (x, 1), 1))) >= 0
5652 && rtx_equal_p (XEXP (XEXP (x, 1), 0), XEXP (x, 0)))
5653 return simplify_and_const_int (NULL_RTX, mode, XEXP (x, 0),
5654 -INTVAL (XEXP (XEXP (x, 1), 1)) - 1);
5658 /* If we have (mult (plus A B) C), apply the distributive law and then
5659 the inverse distributive law to see if things simplify. This
5660 occurs mostly in addresses, often when unrolling loops. */
5662 if (GET_CODE (XEXP (x, 0)) == PLUS)
5664 rtx result = distribute_and_simplify_rtx (x, 0);
5669 /* Try simplify a*(b/c) as (a*b)/c. */
5670 if (FLOAT_MODE_P (mode) && flag_associative_math
5671 && GET_CODE (XEXP (x, 0)) == DIV)
5673 rtx tem = simplify_binary_operation (MULT, mode,
5674 XEXP (XEXP (x, 0), 0),
5677 return simplify_gen_binary (DIV, mode, tem, XEXP (XEXP (x, 0), 1));
5682 /* If this is a divide by a power of two, treat it as a shift if
5683 its first operand is a shift. */
5684 if (CONST_INT_P (XEXP (x, 1))
5685 && (i = exact_log2 (UINTVAL (XEXP (x, 1)))) >= 0
5686 && (GET_CODE (XEXP (x, 0)) == ASHIFT
5687 || GET_CODE (XEXP (x, 0)) == LSHIFTRT
5688 || GET_CODE (XEXP (x, 0)) == ASHIFTRT
5689 || GET_CODE (XEXP (x, 0)) == ROTATE
5690 || GET_CODE (XEXP (x, 0)) == ROTATERT))
5691 return simplify_shift_const (NULL_RTX, LSHIFTRT, mode, XEXP (x, 0), i);
5695 case GT: case GTU: case GE: case GEU:
5696 case LT: case LTU: case LE: case LEU:
5697 case UNEQ: case LTGT:
5698 case UNGT: case UNGE:
5699 case UNLT: case UNLE:
5700 case UNORDERED: case ORDERED:
5701 /* If the first operand is a condition code, we can't do anything
5703 if (GET_CODE (XEXP (x, 0)) == COMPARE
5704 || (GET_MODE_CLASS (GET_MODE (XEXP (x, 0))) != MODE_CC
5705 && ! CC0_P (XEXP (x, 0))))
5707 rtx op0 = XEXP (x, 0);
5708 rtx op1 = XEXP (x, 1);
5709 enum rtx_code new_code;
5711 if (GET_CODE (op0) == COMPARE)
5712 op1 = XEXP (op0, 1), op0 = XEXP (op0, 0);
5714 /* Simplify our comparison, if possible. */
5715 new_code = simplify_comparison (code, &op0, &op1);
5717 /* If STORE_FLAG_VALUE is 1, we can convert (ne x 0) to simply X
5718 if only the low-order bit is possibly nonzero in X (such as when
5719 X is a ZERO_EXTRACT of one bit). Similarly, we can convert EQ to
5720 (xor X 1) or (minus 1 X); we use the former. Finally, if X is
5721 known to be either 0 or -1, NE becomes a NEG and EQ becomes
5724 Remove any ZERO_EXTRACT we made when thinking this was a
5725 comparison. It may now be simpler to use, e.g., an AND. If a
5726 ZERO_EXTRACT is indeed appropriate, it will be placed back by
5727 the call to make_compound_operation in the SET case. */
5729 if (STORE_FLAG_VALUE == 1
5730 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
5731 && op1 == const0_rtx
5732 && mode == GET_MODE (op0)
5733 && nonzero_bits (op0, mode) == 1)
5734 return gen_lowpart (mode,
5735 expand_compound_operation (op0));
5737 else if (STORE_FLAG_VALUE == 1
5738 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
5739 && op1 == const0_rtx
5740 && mode == GET_MODE (op0)
5741 && (num_sign_bit_copies (op0, mode)
5742 == GET_MODE_BITSIZE (mode)))
5744 op0 = expand_compound_operation (op0);
5745 return simplify_gen_unary (NEG, mode,
5746 gen_lowpart (mode, op0),
5750 else if (STORE_FLAG_VALUE == 1
5751 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
5752 && op1 == const0_rtx
5753 && mode == GET_MODE (op0)
5754 && nonzero_bits (op0, mode) == 1)
5756 op0 = expand_compound_operation (op0);
5757 return simplify_gen_binary (XOR, mode,
5758 gen_lowpart (mode, op0),
5762 else if (STORE_FLAG_VALUE == 1
5763 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
5764 && op1 == const0_rtx
5765 && mode == GET_MODE (op0)
5766 && (num_sign_bit_copies (op0, mode)
5767 == GET_MODE_BITSIZE (mode)))
5769 op0 = expand_compound_operation (op0);
5770 return plus_constant (gen_lowpart (mode, op0), 1);
5773 /* If STORE_FLAG_VALUE is -1, we have cases similar to
5775 if (STORE_FLAG_VALUE == -1
5776 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
5777 && op1 == const0_rtx
5778 && (num_sign_bit_copies (op0, mode)
5779 == GET_MODE_BITSIZE (mode)))
5780 return gen_lowpart (mode,
5781 expand_compound_operation (op0));
5783 else if (STORE_FLAG_VALUE == -1
5784 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
5785 && op1 == const0_rtx
5786 && mode == GET_MODE (op0)
5787 && nonzero_bits (op0, mode) == 1)
5789 op0 = expand_compound_operation (op0);
5790 return simplify_gen_unary (NEG, mode,
5791 gen_lowpart (mode, op0),
5795 else if (STORE_FLAG_VALUE == -1
5796 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
5797 && op1 == const0_rtx
5798 && mode == GET_MODE (op0)
5799 && (num_sign_bit_copies (op0, mode)
5800 == GET_MODE_BITSIZE (mode)))
5802 op0 = expand_compound_operation (op0);
5803 return simplify_gen_unary (NOT, mode,
5804 gen_lowpart (mode, op0),
5808 /* If X is 0/1, (eq X 0) is X-1. */
5809 else if (STORE_FLAG_VALUE == -1
5810 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
5811 && op1 == const0_rtx
5812 && mode == GET_MODE (op0)
5813 && nonzero_bits (op0, mode) == 1)
5815 op0 = expand_compound_operation (op0);
5816 return plus_constant (gen_lowpart (mode, op0), -1);
5819 /* If STORE_FLAG_VALUE says to just test the sign bit and X has just
5820 one bit that might be nonzero, we can convert (ne x 0) to
5821 (ashift x c) where C puts the bit in the sign bit. Remove any
5822 AND with STORE_FLAG_VALUE when we are done, since we are only
5823 going to test the sign bit. */
5824 if (new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
5825 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5826 && ((STORE_FLAG_VALUE & GET_MODE_MASK (mode))
5827 == (unsigned HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (mode) - 1))
5828 && op1 == const0_rtx
5829 && mode == GET_MODE (op0)
5830 && (i = exact_log2 (nonzero_bits (op0, mode))) >= 0)
5832 x = simplify_shift_const (NULL_RTX, ASHIFT, mode,
5833 expand_compound_operation (op0),
5834 GET_MODE_BITSIZE (mode) - 1 - i);
5835 if (GET_CODE (x) == AND && XEXP (x, 1) == const_true_rtx)
5841 /* If the code changed, return a whole new comparison. */
5842 if (new_code != code)
5843 return gen_rtx_fmt_ee (new_code, mode, op0, op1);
5845 /* Otherwise, keep this operation, but maybe change its operands.
5846 This also converts (ne (compare FOO BAR) 0) to (ne FOO BAR). */
5847 SUBST (XEXP (x, 0), op0);
5848 SUBST (XEXP (x, 1), op1);
5853 return simplify_if_then_else (x);
5859 /* If we are processing SET_DEST, we are done. */
5863 return expand_compound_operation (x);
5866 return simplify_set (x);
5870 return simplify_logical (x);
5877 /* If this is a shift by a constant amount, simplify it. */
5878 if (CONST_INT_P (XEXP (x, 1)))
5879 return simplify_shift_const (x, code, mode, XEXP (x, 0),
5880 INTVAL (XEXP (x, 1)));
5882 else if (SHIFT_COUNT_TRUNCATED && !REG_P (XEXP (x, 1)))
5884 force_to_mode (XEXP (x, 1), GET_MODE (XEXP (x, 1)),
5885 ((unsigned HOST_WIDE_INT) 1
5886 << exact_log2 (GET_MODE_BITSIZE (GET_MODE (x))))
5898 /* Simplify X, an IF_THEN_ELSE expression. Return the new expression. */
5901 simplify_if_then_else (rtx x)
5903 enum machine_mode mode = GET_MODE (x);
5904 rtx cond = XEXP (x, 0);
5905 rtx true_rtx = XEXP (x, 1);
5906 rtx false_rtx = XEXP (x, 2);
5907 enum rtx_code true_code = GET_CODE (cond);
5908 int comparison_p = COMPARISON_P (cond);
5911 enum rtx_code false_code;
5914 /* Simplify storing of the truth value. */
5915 if (comparison_p && true_rtx == const_true_rtx && false_rtx == const0_rtx)
5916 return simplify_gen_relational (true_code, mode, VOIDmode,
5917 XEXP (cond, 0), XEXP (cond, 1));
5919 /* Also when the truth value has to be reversed. */
5921 && true_rtx == const0_rtx && false_rtx == const_true_rtx
5922 && (reversed = reversed_comparison (cond, mode)))
5925 /* Sometimes we can simplify the arm of an IF_THEN_ELSE if a register used
5926 in it is being compared against certain values. Get the true and false
5927 comparisons and see if that says anything about the value of each arm. */
5930 && ((false_code = reversed_comparison_code (cond, NULL))
5932 && REG_P (XEXP (cond, 0)))
5935 rtx from = XEXP (cond, 0);
5936 rtx true_val = XEXP (cond, 1);
5937 rtx false_val = true_val;
5940 /* If FALSE_CODE is EQ, swap the codes and arms. */
5942 if (false_code == EQ)
5944 swapped = 1, true_code = EQ, false_code = NE;
5945 temp = true_rtx, true_rtx = false_rtx, false_rtx = temp;
5948 /* If we are comparing against zero and the expression being tested has
5949 only a single bit that might be nonzero, that is its value when it is
5950 not equal to zero. Similarly if it is known to be -1 or 0. */
5952 if (true_code == EQ && true_val == const0_rtx
5953 && exact_log2 (nzb = nonzero_bits (from, GET_MODE (from))) >= 0)
5956 false_val = GEN_INT (trunc_int_for_mode (nzb, GET_MODE (from)));
5958 else if (true_code == EQ && true_val == const0_rtx
5959 && (num_sign_bit_copies (from, GET_MODE (from))
5960 == GET_MODE_BITSIZE (GET_MODE (from))))
5963 false_val = constm1_rtx;
5966 /* Now simplify an arm if we know the value of the register in the
5967 branch and it is used in the arm. Be careful due to the potential
5968 of locally-shared RTL. */
5970 if (reg_mentioned_p (from, true_rtx))
5971 true_rtx = subst (known_cond (copy_rtx (true_rtx), true_code,
5973 pc_rtx, pc_rtx, 0, 0);
5974 if (reg_mentioned_p (from, false_rtx))
5975 false_rtx = subst (known_cond (copy_rtx (false_rtx), false_code,
5977 pc_rtx, pc_rtx, 0, 0);
5979 SUBST (XEXP (x, 1), swapped ? false_rtx : true_rtx);
5980 SUBST (XEXP (x, 2), swapped ? true_rtx : false_rtx);
5982 true_rtx = XEXP (x, 1);
5983 false_rtx = XEXP (x, 2);
5984 true_code = GET_CODE (cond);
5987 /* If we have (if_then_else FOO (pc) (label_ref BAR)) and FOO can be
5988 reversed, do so to avoid needing two sets of patterns for
5989 subtract-and-branch insns. Similarly if we have a constant in the true
5990 arm, the false arm is the same as the first operand of the comparison, or
5991 the false arm is more complicated than the true arm. */
5994 && reversed_comparison_code (cond, NULL) != UNKNOWN
5995 && (true_rtx == pc_rtx
5996 || (CONSTANT_P (true_rtx)
5997 && !CONST_INT_P (false_rtx) && false_rtx != pc_rtx)
5998 || true_rtx == const0_rtx
5999 || (OBJECT_P (true_rtx) && !OBJECT_P (false_rtx))
6000 || (GET_CODE (true_rtx) == SUBREG && OBJECT_P (SUBREG_REG (true_rtx))
6001 && !OBJECT_P (false_rtx))
6002 || reg_mentioned_p (true_rtx, false_rtx)
6003 || rtx_equal_p (false_rtx, XEXP (cond, 0))))
6005 true_code = reversed_comparison_code (cond, NULL);
6006 SUBST (XEXP (x, 0), reversed_comparison (cond, GET_MODE (cond)));
6007 SUBST (XEXP (x, 1), false_rtx);
6008 SUBST (XEXP (x, 2), true_rtx);
6010 temp = true_rtx, true_rtx = false_rtx, false_rtx = temp;
6013 /* It is possible that the conditional has been simplified out. */
6014 true_code = GET_CODE (cond);
6015 comparison_p = COMPARISON_P (cond);
6018 /* If the two arms are identical, we don't need the comparison. */
6020 if (rtx_equal_p (true_rtx, false_rtx) && ! side_effects_p (cond))
6023 /* Convert a == b ? b : a to "a". */
6024 if (true_code == EQ && ! side_effects_p (cond)
6025 && !HONOR_NANS (mode)
6026 && rtx_equal_p (XEXP (cond, 0), false_rtx)
6027 && rtx_equal_p (XEXP (cond, 1), true_rtx))
6029 else if (true_code == NE && ! side_effects_p (cond)
6030 && !HONOR_NANS (mode)
6031 && rtx_equal_p (XEXP (cond, 0), true_rtx)
6032 && rtx_equal_p (XEXP (cond, 1), false_rtx))
6035 /* Look for cases where we have (abs x) or (neg (abs X)). */
6037 if (GET_MODE_CLASS (mode) == MODE_INT
6039 && XEXP (cond, 1) == const0_rtx
6040 && GET_CODE (false_rtx) == NEG
6041 && rtx_equal_p (true_rtx, XEXP (false_rtx, 0))
6042 && rtx_equal_p (true_rtx, XEXP (cond, 0))
6043 && ! side_effects_p (true_rtx))
6048 return simplify_gen_unary (ABS, mode, true_rtx, mode);
6052 simplify_gen_unary (NEG, mode,
6053 simplify_gen_unary (ABS, mode, true_rtx, mode),
6059 /* Look for MIN or MAX. */
6061 if ((! FLOAT_MODE_P (mode) || flag_unsafe_math_optimizations)
6063 && rtx_equal_p (XEXP (cond, 0), true_rtx)
6064 && rtx_equal_p (XEXP (cond, 1), false_rtx)
6065 && ! side_effects_p (cond))
6070 return simplify_gen_binary (SMAX, mode, true_rtx, false_rtx);
6073 return simplify_gen_binary (SMIN, mode, true_rtx, false_rtx);
6076 return simplify_gen_binary (UMAX, mode, true_rtx, false_rtx);
6079 return simplify_gen_binary (UMIN, mode, true_rtx, false_rtx);
6084 /* If we have (if_then_else COND (OP Z C1) Z) and OP is an identity when its
6085 second operand is zero, this can be done as (OP Z (mult COND C2)) where
6086 C2 = C1 * STORE_FLAG_VALUE. Similarly if OP has an outer ZERO_EXTEND or
6087 SIGN_EXTEND as long as Z is already extended (so we don't destroy it).
6088 We can do this kind of thing in some cases when STORE_FLAG_VALUE is
6089 neither 1 or -1, but it isn't worth checking for. */
6091 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
6093 && GET_MODE_CLASS (mode) == MODE_INT
6094 && ! side_effects_p (x))
6096 rtx t = make_compound_operation (true_rtx, SET);
6097 rtx f = make_compound_operation (false_rtx, SET);
6098 rtx cond_op0 = XEXP (cond, 0);
6099 rtx cond_op1 = XEXP (cond, 1);
6100 enum rtx_code op = UNKNOWN, extend_op = UNKNOWN;
6101 enum machine_mode m = mode;
6102 rtx z = 0, c1 = NULL_RTX;
6104 if ((GET_CODE (t) == PLUS || GET_CODE (t) == MINUS
6105 || GET_CODE (t) == IOR || GET_CODE (t) == XOR
6106 || GET_CODE (t) == ASHIFT
6107 || GET_CODE (t) == LSHIFTRT || GET_CODE (t) == ASHIFTRT)
6108 && rtx_equal_p (XEXP (t, 0), f))
6109 c1 = XEXP (t, 1), op = GET_CODE (t), z = f;
6111 /* If an identity-zero op is commutative, check whether there
6112 would be a match if we swapped the operands. */
6113 else if ((GET_CODE (t) == PLUS || GET_CODE (t) == IOR
6114 || GET_CODE (t) == XOR)
6115 && rtx_equal_p (XEXP (t, 1), f))
6116 c1 = XEXP (t, 0), op = GET_CODE (t), z = f;
6117 else if (GET_CODE (t) == SIGN_EXTEND
6118 && (GET_CODE (XEXP (t, 0)) == PLUS
6119 || GET_CODE (XEXP (t, 0)) == MINUS
6120 || GET_CODE (XEXP (t, 0)) == IOR
6121 || GET_CODE (XEXP (t, 0)) == XOR
6122 || GET_CODE (XEXP (t, 0)) == ASHIFT
6123 || GET_CODE (XEXP (t, 0)) == LSHIFTRT
6124 || GET_CODE (XEXP (t, 0)) == ASHIFTRT)
6125 && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG
6126 && subreg_lowpart_p (XEXP (XEXP (t, 0), 0))
6127 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f)
6128 && (num_sign_bit_copies (f, GET_MODE (f))
6130 (GET_MODE_BITSIZE (mode)
6131 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t, 0), 0))))))
6133 c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0));
6134 extend_op = SIGN_EXTEND;
6135 m = GET_MODE (XEXP (t, 0));
6137 else if (GET_CODE (t) == SIGN_EXTEND
6138 && (GET_CODE (XEXP (t, 0)) == PLUS
6139 || GET_CODE (XEXP (t, 0)) == IOR
6140 || GET_CODE (XEXP (t, 0)) == XOR)
6141 && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG
6142 && subreg_lowpart_p (XEXP (XEXP (t, 0), 1))
6143 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f)
6144 && (num_sign_bit_copies (f, GET_MODE (f))
6146 (GET_MODE_BITSIZE (mode)
6147 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t, 0), 1))))))
6149 c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0));
6150 extend_op = SIGN_EXTEND;
6151 m = GET_MODE (XEXP (t, 0));
6153 else if (GET_CODE (t) == ZERO_EXTEND
6154 && (GET_CODE (XEXP (t, 0)) == PLUS
6155 || GET_CODE (XEXP (t, 0)) == MINUS
6156 || GET_CODE (XEXP (t, 0)) == IOR
6157 || GET_CODE (XEXP (t, 0)) == XOR
6158 || GET_CODE (XEXP (t, 0)) == ASHIFT
6159 || GET_CODE (XEXP (t, 0)) == LSHIFTRT
6160 || GET_CODE (XEXP (t, 0)) == ASHIFTRT)
6161 && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG
6162 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
6163 && subreg_lowpart_p (XEXP (XEXP (t, 0), 0))
6164 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f)
6165 && ((nonzero_bits (f, GET_MODE (f))
6166 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t, 0), 0))))
6169 c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0));
6170 extend_op = ZERO_EXTEND;
6171 m = GET_MODE (XEXP (t, 0));
6173 else if (GET_CODE (t) == ZERO_EXTEND
6174 && (GET_CODE (XEXP (t, 0)) == PLUS
6175 || GET_CODE (XEXP (t, 0)) == IOR
6176 || GET_CODE (XEXP (t, 0)) == XOR)
6177 && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG
6178 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
6179 && subreg_lowpart_p (XEXP (XEXP (t, 0), 1))
6180 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f)
6181 && ((nonzero_bits (f, GET_MODE (f))
6182 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t, 0), 1))))
6185 c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0));
6186 extend_op = ZERO_EXTEND;
6187 m = GET_MODE (XEXP (t, 0));
6192 temp = subst (simplify_gen_relational (true_code, m, VOIDmode,
6193 cond_op0, cond_op1),
6194 pc_rtx, pc_rtx, 0, 0);
6195 temp = simplify_gen_binary (MULT, m, temp,
6196 simplify_gen_binary (MULT, m, c1,
6198 temp = subst (temp, pc_rtx, pc_rtx, 0, 0);
6199 temp = simplify_gen_binary (op, m, gen_lowpart (m, z), temp);
6201 if (extend_op != UNKNOWN)
6202 temp = simplify_gen_unary (extend_op, mode, temp, m);
6208 /* If we have (if_then_else (ne A 0) C1 0) and either A is known to be 0 or
6209 1 and C1 is a single bit or A is known to be 0 or -1 and C1 is the
6210 negation of a single bit, we can convert this operation to a shift. We
6211 can actually do this more generally, but it doesn't seem worth it. */
6213 if (true_code == NE && XEXP (cond, 1) == const0_rtx
6214 && false_rtx == const0_rtx && CONST_INT_P (true_rtx)
6215 && ((1 == nonzero_bits (XEXP (cond, 0), mode)
6216 && (i = exact_log2 (UINTVAL (true_rtx))) >= 0)
6217 || ((num_sign_bit_copies (XEXP (cond, 0), mode)
6218 == GET_MODE_BITSIZE (mode))
6219 && (i = exact_log2 (-UINTVAL (true_rtx))) >= 0)))
6221 simplify_shift_const (NULL_RTX, ASHIFT, mode,
6222 gen_lowpart (mode, XEXP (cond, 0)), i);
6224 /* (IF_THEN_ELSE (NE REG 0) (0) (8)) is REG for nonzero_bits (REG) == 8. */
6225 if (true_code == NE && XEXP (cond, 1) == const0_rtx
6226 && false_rtx == const0_rtx && CONST_INT_P (true_rtx)
6227 && GET_MODE (XEXP (cond, 0)) == mode
6228 && (UINTVAL (true_rtx) & GET_MODE_MASK (mode))
6229 == nonzero_bits (XEXP (cond, 0), mode)
6230 && (i = exact_log2 (UINTVAL (true_rtx) & GET_MODE_MASK (mode))) >= 0)
6231 return XEXP (cond, 0);
6236 /* Simplify X, a SET expression. Return the new expression. */
6239 simplify_set (rtx x)
6241 rtx src = SET_SRC (x);
6242 rtx dest = SET_DEST (x);
6243 enum machine_mode mode
6244 = GET_MODE (src) != VOIDmode ? GET_MODE (src) : GET_MODE (dest);
6248 /* (set (pc) (return)) gets written as (return). */
6249 if (GET_CODE (dest) == PC && GET_CODE (src) == RETURN)
6252 /* Now that we know for sure which bits of SRC we are using, see if we can
6253 simplify the expression for the object knowing that we only need the
6256 if (GET_MODE_CLASS (mode) == MODE_INT
6257 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
6259 src = force_to_mode (src, mode, ~(unsigned HOST_WIDE_INT) 0, 0);
6260 SUBST (SET_SRC (x), src);
6263 /* If we are setting CC0 or if the source is a COMPARE, look for the use of
6264 the comparison result and try to simplify it unless we already have used
6265 undobuf.other_insn. */
6266 if ((GET_MODE_CLASS (mode) == MODE_CC
6267 || GET_CODE (src) == COMPARE
6269 && (cc_use = find_single_use (dest, subst_insn, &other_insn)) != 0
6270 && (undobuf.other_insn == 0 || other_insn == undobuf.other_insn)
6271 && COMPARISON_P (*cc_use)
6272 && rtx_equal_p (XEXP (*cc_use, 0), dest))
6274 enum rtx_code old_code = GET_CODE (*cc_use);
6275 enum rtx_code new_code;
6277 int other_changed = 0;
6278 rtx inner_compare = NULL_RTX;
6279 enum machine_mode compare_mode = GET_MODE (dest);
6281 if (GET_CODE (src) == COMPARE)
6283 op0 = XEXP (src, 0), op1 = XEXP (src, 1);
6284 if (GET_CODE (op0) == COMPARE && op1 == const0_rtx)
6286 inner_compare = op0;
6287 op0 = XEXP (inner_compare, 0), op1 = XEXP (inner_compare, 1);
6291 op0 = src, op1 = CONST0_RTX (GET_MODE (src));
6293 tmp = simplify_relational_operation (old_code, compare_mode, VOIDmode,
6296 new_code = old_code;
6297 else if (!CONSTANT_P (tmp))
6299 new_code = GET_CODE (tmp);
6300 op0 = XEXP (tmp, 0);
6301 op1 = XEXP (tmp, 1);
6305 rtx pat = PATTERN (other_insn);
6306 undobuf.other_insn = other_insn;
6307 SUBST (*cc_use, tmp);
6309 /* Attempt to simplify CC user. */
6310 if (GET_CODE (pat) == SET)
6312 rtx new_rtx = simplify_rtx (SET_SRC (pat));
6313 if (new_rtx != NULL_RTX)
6314 SUBST (SET_SRC (pat), new_rtx);
6317 /* Convert X into a no-op move. */
6318 SUBST (SET_DEST (x), pc_rtx);
6319 SUBST (SET_SRC (x), pc_rtx);
6323 /* Simplify our comparison, if possible. */
6324 new_code = simplify_comparison (new_code, &op0, &op1);
6326 #ifdef SELECT_CC_MODE
6327 /* If this machine has CC modes other than CCmode, check to see if we
6328 need to use a different CC mode here. */
6329 if (GET_MODE_CLASS (GET_MODE (op0)) == MODE_CC)
6330 compare_mode = GET_MODE (op0);
6331 else if (inner_compare
6332 && GET_MODE_CLASS (GET_MODE (inner_compare)) == MODE_CC
6333 && new_code == old_code
6334 && op0 == XEXP (inner_compare, 0)
6335 && op1 == XEXP (inner_compare, 1))
6336 compare_mode = GET_MODE (inner_compare);
6338 compare_mode = SELECT_CC_MODE (new_code, op0, op1);
6341 /* If the mode changed, we have to change SET_DEST, the mode in the
6342 compare, and the mode in the place SET_DEST is used. If SET_DEST is
6343 a hard register, just build new versions with the proper mode. If it
6344 is a pseudo, we lose unless it is only time we set the pseudo, in
6345 which case we can safely change its mode. */
6346 if (compare_mode != GET_MODE (dest))
6348 if (can_change_dest_mode (dest, 0, compare_mode))
6350 unsigned int regno = REGNO (dest);
6353 if (regno < FIRST_PSEUDO_REGISTER)
6354 new_dest = gen_rtx_REG (compare_mode, regno);
6357 SUBST_MODE (regno_reg_rtx[regno], compare_mode);
6358 new_dest = regno_reg_rtx[regno];
6361 SUBST (SET_DEST (x), new_dest);
6362 SUBST (XEXP (*cc_use, 0), new_dest);
6369 #endif /* SELECT_CC_MODE */
6371 /* If the code changed, we have to build a new comparison in
6372 undobuf.other_insn. */
6373 if (new_code != old_code)
6375 int other_changed_previously = other_changed;
6376 unsigned HOST_WIDE_INT mask;
6377 rtx old_cc_use = *cc_use;
6379 SUBST (*cc_use, gen_rtx_fmt_ee (new_code, GET_MODE (*cc_use),
6383 /* If the only change we made was to change an EQ into an NE or
6384 vice versa, OP0 has only one bit that might be nonzero, and OP1
6385 is zero, check if changing the user of the condition code will
6386 produce a valid insn. If it won't, we can keep the original code
6387 in that insn by surrounding our operation with an XOR. */
6389 if (((old_code == NE && new_code == EQ)
6390 || (old_code == EQ && new_code == NE))
6391 && ! other_changed_previously && op1 == const0_rtx
6392 && GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
6393 && exact_log2 (mask = nonzero_bits (op0, GET_MODE (op0))) >= 0)
6395 rtx pat = PATTERN (other_insn), note = 0;
6397 if ((recog_for_combine (&pat, other_insn, ¬e) < 0
6398 && ! check_asm_operands (pat)))
6400 *cc_use = old_cc_use;
6403 op0 = simplify_gen_binary (XOR, GET_MODE (op0),
6404 op0, GEN_INT (mask));
6410 undobuf.other_insn = other_insn;
6412 /* Otherwise, if we didn't previously have a COMPARE in the
6413 correct mode, we need one. */
6414 if (GET_CODE (src) != COMPARE || GET_MODE (src) != compare_mode)
6416 SUBST (SET_SRC (x), gen_rtx_COMPARE (compare_mode, op0, op1));
6419 else if (GET_MODE (op0) == compare_mode && op1 == const0_rtx)
6421 SUBST (SET_SRC (x), op0);
6424 /* Otherwise, update the COMPARE if needed. */
6425 else if (XEXP (src, 0) != op0 || XEXP (src, 1) != op1)
6427 SUBST (SET_SRC (x), gen_rtx_COMPARE (compare_mode, op0, op1));
6433 /* Get SET_SRC in a form where we have placed back any
6434 compound expressions. Then do the checks below. */
6435 src = make_compound_operation (src, SET);
6436 SUBST (SET_SRC (x), src);
6439 /* If we have (set x (subreg:m1 (op:m2 ...) 0)) with OP being some operation,
6440 and X being a REG or (subreg (reg)), we may be able to convert this to
6441 (set (subreg:m2 x) (op)).
6443 We can always do this if M1 is narrower than M2 because that means that
6444 we only care about the low bits of the result.
6446 However, on machines without WORD_REGISTER_OPERATIONS defined, we cannot
6447 perform a narrower operation than requested since the high-order bits will
6448 be undefined. On machine where it is defined, this transformation is safe
6449 as long as M1 and M2 have the same number of words. */
6451 if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src)
6452 && !OBJECT_P (SUBREG_REG (src))
6453 && (((GET_MODE_SIZE (GET_MODE (src)) + (UNITS_PER_WORD - 1))
6455 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (src)))
6456 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD))
6457 #ifndef WORD_REGISTER_OPERATIONS
6458 && (GET_MODE_SIZE (GET_MODE (src))
6459 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (src))))
6461 #ifdef CANNOT_CHANGE_MODE_CLASS
6462 && ! (REG_P (dest) && REGNO (dest) < FIRST_PSEUDO_REGISTER
6463 && REG_CANNOT_CHANGE_MODE_P (REGNO (dest),
6464 GET_MODE (SUBREG_REG (src)),
6468 || (GET_CODE (dest) == SUBREG
6469 && REG_P (SUBREG_REG (dest)))))
6471 SUBST (SET_DEST (x),
6472 gen_lowpart (GET_MODE (SUBREG_REG (src)),
6474 SUBST (SET_SRC (x), SUBREG_REG (src));
6476 src = SET_SRC (x), dest = SET_DEST (x);
6480 /* If we have (set (cc0) (subreg ...)), we try to remove the subreg
6483 && GET_CODE (src) == SUBREG
6484 && subreg_lowpart_p (src)
6485 && (GET_MODE_BITSIZE (GET_MODE (src))
6486 < GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (src)))))
6488 rtx inner = SUBREG_REG (src);
6489 enum machine_mode inner_mode = GET_MODE (inner);
6491 /* Here we make sure that we don't have a sign bit on. */
6492 if (GET_MODE_BITSIZE (inner_mode) <= HOST_BITS_PER_WIDE_INT
6493 && (nonzero_bits (inner, inner_mode)
6494 < ((unsigned HOST_WIDE_INT) 1
6495 << (GET_MODE_BITSIZE (GET_MODE (src)) - 1))))
6497 SUBST (SET_SRC (x), inner);
6503 #ifdef LOAD_EXTEND_OP
6504 /* If we have (set FOO (subreg:M (mem:N BAR) 0)) with M wider than N, this
6505 would require a paradoxical subreg. Replace the subreg with a
6506 zero_extend to avoid the reload that would otherwise be required. */
6508 if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src)
6509 && INTEGRAL_MODE_P (GET_MODE (SUBREG_REG (src)))
6510 && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src))) != UNKNOWN
6511 && SUBREG_BYTE (src) == 0
6512 && (GET_MODE_SIZE (GET_MODE (src))
6513 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (src))))
6514 && MEM_P (SUBREG_REG (src)))
6517 gen_rtx_fmt_e (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src))),
6518 GET_MODE (src), SUBREG_REG (src)));
6524 /* If we don't have a conditional move, SET_SRC is an IF_THEN_ELSE, and we
6525 are comparing an item known to be 0 or -1 against 0, use a logical
6526 operation instead. Check for one of the arms being an IOR of the other
6527 arm with some value. We compute three terms to be IOR'ed together. In
6528 practice, at most two will be nonzero. Then we do the IOR's. */
6530 if (GET_CODE (dest) != PC
6531 && GET_CODE (src) == IF_THEN_ELSE
6532 && GET_MODE_CLASS (GET_MODE (src)) == MODE_INT
6533 && (GET_CODE (XEXP (src, 0)) == EQ || GET_CODE (XEXP (src, 0)) == NE)
6534 && XEXP (XEXP (src, 0), 1) == const0_rtx
6535 && GET_MODE (src) == GET_MODE (XEXP (XEXP (src, 0), 0))
6536 #ifdef HAVE_conditional_move
6537 && ! can_conditionally_move_p (GET_MODE (src))
6539 && (num_sign_bit_copies (XEXP (XEXP (src, 0), 0),
6540 GET_MODE (XEXP (XEXP (src, 0), 0)))
6541 == GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (src, 0), 0))))
6542 && ! side_effects_p (src))
6544 rtx true_rtx = (GET_CODE (XEXP (src, 0)) == NE
6545 ? XEXP (src, 1) : XEXP (src, 2));
6546 rtx false_rtx = (GET_CODE (XEXP (src, 0)) == NE
6547 ? XEXP (src, 2) : XEXP (src, 1));
6548 rtx term1 = const0_rtx, term2, term3;
6550 if (GET_CODE (true_rtx) == IOR
6551 && rtx_equal_p (XEXP (true_rtx, 0), false_rtx))
6552 term1 = false_rtx, true_rtx = XEXP (true_rtx, 1), false_rtx = const0_rtx;
6553 else if (GET_CODE (true_rtx) == IOR
6554 && rtx_equal_p (XEXP (true_rtx, 1), false_rtx))
6555 term1 = false_rtx, true_rtx = XEXP (true_rtx, 0), false_rtx = const0_rtx;
6556 else if (GET_CODE (false_rtx) == IOR
6557 && rtx_equal_p (XEXP (false_rtx, 0), true_rtx))
6558 term1 = true_rtx, false_rtx = XEXP (false_rtx, 1), true_rtx = const0_rtx;
6559 else if (GET_CODE (false_rtx) == IOR
6560 && rtx_equal_p (XEXP (false_rtx, 1), true_rtx))
6561 term1 = true_rtx, false_rtx = XEXP (false_rtx, 0), true_rtx = const0_rtx;
6563 term2 = simplify_gen_binary (AND, GET_MODE (src),
6564 XEXP (XEXP (src, 0), 0), true_rtx);
6565 term3 = simplify_gen_binary (AND, GET_MODE (src),
6566 simplify_gen_unary (NOT, GET_MODE (src),
6567 XEXP (XEXP (src, 0), 0),
6572 simplify_gen_binary (IOR, GET_MODE (src),
6573 simplify_gen_binary (IOR, GET_MODE (src),
6580 /* If either SRC or DEST is a CLOBBER of (const_int 0), make this
6581 whole thing fail. */
6582 if (GET_CODE (src) == CLOBBER && XEXP (src, 0) == const0_rtx)
6584 else if (GET_CODE (dest) == CLOBBER && XEXP (dest, 0) == const0_rtx)
6587 /* Convert this into a field assignment operation, if possible. */
6588 return make_field_assignment (x);
6591 /* Simplify, X, and AND, IOR, or XOR operation, and return the simplified
6595 simplify_logical (rtx x)
6597 enum machine_mode mode = GET_MODE (x);
6598 rtx op0 = XEXP (x, 0);
6599 rtx op1 = XEXP (x, 1);
6601 switch (GET_CODE (x))
6604 /* We can call simplify_and_const_int only if we don't lose
6605 any (sign) bits when converting INTVAL (op1) to
6606 "unsigned HOST_WIDE_INT". */
6607 if (CONST_INT_P (op1)
6608 && (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
6609 || INTVAL (op1) > 0))
6611 x = simplify_and_const_int (x, mode, op0, INTVAL (op1));
6612 if (GET_CODE (x) != AND)
6619 /* If we have any of (and (ior A B) C) or (and (xor A B) C),
6620 apply the distributive law and then the inverse distributive
6621 law to see if things simplify. */
6622 if (GET_CODE (op0) == IOR || GET_CODE (op0) == XOR)
6624 rtx result = distribute_and_simplify_rtx (x, 0);
6628 if (GET_CODE (op1) == IOR || GET_CODE (op1) == XOR)
6630 rtx result = distribute_and_simplify_rtx (x, 1);
6637 /* If we have (ior (and A B) C), apply the distributive law and then
6638 the inverse distributive law to see if things simplify. */
6640 if (GET_CODE (op0) == AND)
6642 rtx result = distribute_and_simplify_rtx (x, 0);
6647 if (GET_CODE (op1) == AND)
6649 rtx result = distribute_and_simplify_rtx (x, 1);
6662 /* We consider ZERO_EXTRACT, SIGN_EXTRACT, and SIGN_EXTEND as "compound
6663 operations" because they can be replaced with two more basic operations.
6664 ZERO_EXTEND is also considered "compound" because it can be replaced with
6665 an AND operation, which is simpler, though only one operation.
6667 The function expand_compound_operation is called with an rtx expression
6668 and will convert it to the appropriate shifts and AND operations,
6669 simplifying at each stage.
6671 The function make_compound_operation is called to convert an expression
6672 consisting of shifts and ANDs into the equivalent compound expression.
6673 It is the inverse of this function, loosely speaking. */
6676 expand_compound_operation (rtx x)
6678 unsigned HOST_WIDE_INT pos = 0, len;
6680 unsigned int modewidth;
6683 switch (GET_CODE (x))
6688 /* We can't necessarily use a const_int for a multiword mode;
6689 it depends on implicitly extending the value.
6690 Since we don't know the right way to extend it,
6691 we can't tell whether the implicit way is right.
6693 Even for a mode that is no wider than a const_int,
6694 we can't win, because we need to sign extend one of its bits through
6695 the rest of it, and we don't know which bit. */
6696 if (CONST_INT_P (XEXP (x, 0)))
6699 /* Return if (subreg:MODE FROM 0) is not a safe replacement for
6700 (zero_extend:MODE FROM) or (sign_extend:MODE FROM). It is for any MEM
6701 because (SUBREG (MEM...)) is guaranteed to cause the MEM to be
6702 reloaded. If not for that, MEM's would very rarely be safe.
6704 Reject MODEs bigger than a word, because we might not be able
6705 to reference a two-register group starting with an arbitrary register
6706 (and currently gen_lowpart might crash for a SUBREG). */
6708 if (GET_MODE_SIZE (GET_MODE (XEXP (x, 0))) > UNITS_PER_WORD)
6711 /* Reject MODEs that aren't scalar integers because turning vector
6712 or complex modes into shifts causes problems. */
6714 if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x, 0))))
6717 len = GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)));
6718 /* If the inner object has VOIDmode (the only way this can happen
6719 is if it is an ASM_OPERANDS), we can't do anything since we don't
6720 know how much masking to do. */
6729 /* ... fall through ... */
6732 /* If the operand is a CLOBBER, just return it. */
6733 if (GET_CODE (XEXP (x, 0)) == CLOBBER)
6736 if (!CONST_INT_P (XEXP (x, 1))
6737 || !CONST_INT_P (XEXP (x, 2))
6738 || GET_MODE (XEXP (x, 0)) == VOIDmode)
6741 /* Reject MODEs that aren't scalar integers because turning vector
6742 or complex modes into shifts causes problems. */
6744 if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x, 0))))
6747 len = INTVAL (XEXP (x, 1));
6748 pos = INTVAL (XEXP (x, 2));
6750 /* This should stay within the object being extracted, fail otherwise. */
6751 if (len + pos > GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))))
6754 if (BITS_BIG_ENDIAN)
6755 pos = GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - len - pos;
6762 /* Convert sign extension to zero extension, if we know that the high
6763 bit is not set, as this is easier to optimize. It will be converted
6764 back to cheaper alternative in make_extraction. */
6765 if (GET_CODE (x) == SIGN_EXTEND
6766 && (GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
6767 && ((nonzero_bits (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
6768 & ~(((unsigned HOST_WIDE_INT)
6769 GET_MODE_MASK (GET_MODE (XEXP (x, 0))))
6773 rtx temp = gen_rtx_ZERO_EXTEND (GET_MODE (x), XEXP (x, 0));
6774 rtx temp2 = expand_compound_operation (temp);
6776 /* Make sure this is a profitable operation. */
6777 if (rtx_cost (x, SET, optimize_this_for_speed_p)
6778 > rtx_cost (temp2, SET, optimize_this_for_speed_p))
6780 else if (rtx_cost (x, SET, optimize_this_for_speed_p)
6781 > rtx_cost (temp, SET, optimize_this_for_speed_p))
6787 /* We can optimize some special cases of ZERO_EXTEND. */
6788 if (GET_CODE (x) == ZERO_EXTEND)
6790 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI if we
6791 know that the last value didn't have any inappropriate bits
6793 if (GET_CODE (XEXP (x, 0)) == TRUNCATE
6794 && GET_MODE (XEXP (XEXP (x, 0), 0)) == GET_MODE (x)
6795 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
6796 && (nonzero_bits (XEXP (XEXP (x, 0), 0), GET_MODE (x))
6797 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
6798 return XEXP (XEXP (x, 0), 0);
6800 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
6801 if (GET_CODE (XEXP (x, 0)) == SUBREG
6802 && GET_MODE (SUBREG_REG (XEXP (x, 0))) == GET_MODE (x)
6803 && subreg_lowpart_p (XEXP (x, 0))
6804 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
6805 && (nonzero_bits (SUBREG_REG (XEXP (x, 0)), GET_MODE (x))
6806 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
6807 return SUBREG_REG (XEXP (x, 0));
6809 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI when foo
6810 is a comparison and STORE_FLAG_VALUE permits. This is like
6811 the first case, but it works even when GET_MODE (x) is larger
6812 than HOST_WIDE_INT. */
6813 if (GET_CODE (XEXP (x, 0)) == TRUNCATE
6814 && GET_MODE (XEXP (XEXP (x, 0), 0)) == GET_MODE (x)
6815 && COMPARISON_P (XEXP (XEXP (x, 0), 0))
6816 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
6817 <= HOST_BITS_PER_WIDE_INT)
6818 && (STORE_FLAG_VALUE & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
6819 return XEXP (XEXP (x, 0), 0);
6821 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
6822 if (GET_CODE (XEXP (x, 0)) == SUBREG
6823 && GET_MODE (SUBREG_REG (XEXP (x, 0))) == GET_MODE (x)
6824 && subreg_lowpart_p (XEXP (x, 0))
6825 && COMPARISON_P (SUBREG_REG (XEXP (x, 0)))
6826 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
6827 <= HOST_BITS_PER_WIDE_INT)
6828 && (STORE_FLAG_VALUE & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
6829 return SUBREG_REG (XEXP (x, 0));
6833 /* If we reach here, we want to return a pair of shifts. The inner
6834 shift is a left shift of BITSIZE - POS - LEN bits. The outer
6835 shift is a right shift of BITSIZE - LEN bits. It is arithmetic or
6836 logical depending on the value of UNSIGNEDP.
6838 If this was a ZERO_EXTEND or ZERO_EXTRACT, this pair of shifts will be
6839 converted into an AND of a shift.
6841 We must check for the case where the left shift would have a negative
6842 count. This can happen in a case like (x >> 31) & 255 on machines
6843 that can't shift by a constant. On those machines, we would first
6844 combine the shift with the AND to produce a variable-position
6845 extraction. Then the constant of 31 would be substituted in
6846 to produce such a position. */
6848 modewidth = GET_MODE_BITSIZE (GET_MODE (x));
6849 if (modewidth >= pos + len)
6851 enum machine_mode mode = GET_MODE (x);
6852 tem = gen_lowpart (mode, XEXP (x, 0));
6853 if (!tem || GET_CODE (tem) == CLOBBER)
6855 tem = simplify_shift_const (NULL_RTX, ASHIFT, mode,
6856 tem, modewidth - pos - len);
6857 tem = simplify_shift_const (NULL_RTX, unsignedp ? LSHIFTRT : ASHIFTRT,
6858 mode, tem, modewidth - len);
6860 else if (unsignedp && len < HOST_BITS_PER_WIDE_INT)
6861 tem = simplify_and_const_int (NULL_RTX, GET_MODE (x),
6862 simplify_shift_const (NULL_RTX, LSHIFTRT,
6865 ((unsigned HOST_WIDE_INT) 1 << len) - 1);
6867 /* Any other cases we can't handle. */
6870 /* If we couldn't do this for some reason, return the original
6872 if (GET_CODE (tem) == CLOBBER)
6878 /* X is a SET which contains an assignment of one object into
6879 a part of another (such as a bit-field assignment, STRICT_LOW_PART,
6880 or certain SUBREGS). If possible, convert it into a series of
6883 We half-heartedly support variable positions, but do not at all
6884 support variable lengths. */
6887 expand_field_assignment (const_rtx x)
6890 rtx pos; /* Always counts from low bit. */
6892 rtx mask, cleared, masked;
6893 enum machine_mode compute_mode;
6895 /* Loop until we find something we can't simplify. */
6898 if (GET_CODE (SET_DEST (x)) == STRICT_LOW_PART
6899 && GET_CODE (XEXP (SET_DEST (x), 0)) == SUBREG)
6901 inner = SUBREG_REG (XEXP (SET_DEST (x), 0));
6902 len = GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0)));
6903 pos = GEN_INT (subreg_lsb (XEXP (SET_DEST (x), 0)));
6905 else if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
6906 && CONST_INT_P (XEXP (SET_DEST (x), 1)))
6908 inner = XEXP (SET_DEST (x), 0);
6909 len = INTVAL (XEXP (SET_DEST (x), 1));
6910 pos = XEXP (SET_DEST (x), 2);
6912 /* A constant position should stay within the width of INNER. */
6913 if (CONST_INT_P (pos)
6914 && INTVAL (pos) + len > GET_MODE_BITSIZE (GET_MODE (inner)))
6917 if (BITS_BIG_ENDIAN)
6919 if (CONST_INT_P (pos))
6920 pos = GEN_INT (GET_MODE_BITSIZE (GET_MODE (inner)) - len
6922 else if (GET_CODE (pos) == MINUS
6923 && CONST_INT_P (XEXP (pos, 1))
6924 && (INTVAL (XEXP (pos, 1))
6925 == GET_MODE_BITSIZE (GET_MODE (inner)) - len))
6926 /* If position is ADJUST - X, new position is X. */
6927 pos = XEXP (pos, 0);
6929 pos = simplify_gen_binary (MINUS, GET_MODE (pos),
6930 GEN_INT (GET_MODE_BITSIZE (
6937 /* A SUBREG between two modes that occupy the same numbers of words
6938 can be done by moving the SUBREG to the source. */
6939 else if (GET_CODE (SET_DEST (x)) == SUBREG
6940 /* We need SUBREGs to compute nonzero_bits properly. */
6941 && nonzero_sign_valid
6942 && (((GET_MODE_SIZE (GET_MODE (SET_DEST (x)))
6943 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
6944 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x))))
6945 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)))
6947 x = gen_rtx_SET (VOIDmode, SUBREG_REG (SET_DEST (x)),
6949 (GET_MODE (SUBREG_REG (SET_DEST (x))),
6956 while (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
6957 inner = SUBREG_REG (inner);
6959 compute_mode = GET_MODE (inner);
6961 /* Don't attempt bitwise arithmetic on non scalar integer modes. */
6962 if (! SCALAR_INT_MODE_P (compute_mode))
6964 enum machine_mode imode;
6966 /* Don't do anything for vector or complex integral types. */
6967 if (! FLOAT_MODE_P (compute_mode))
6970 /* Try to find an integral mode to pun with. */
6971 imode = mode_for_size (GET_MODE_BITSIZE (compute_mode), MODE_INT, 0);
6972 if (imode == BLKmode)
6975 compute_mode = imode;
6976 inner = gen_lowpart (imode, inner);
6979 /* Compute a mask of LEN bits, if we can do this on the host machine. */
6980 if (len >= HOST_BITS_PER_WIDE_INT)
6983 /* Now compute the equivalent expression. Make a copy of INNER
6984 for the SET_DEST in case it is a MEM into which we will substitute;
6985 we don't want shared RTL in that case. */
6986 mask = GEN_INT (((unsigned HOST_WIDE_INT) 1 << len) - 1);
6987 cleared = simplify_gen_binary (AND, compute_mode,
6988 simplify_gen_unary (NOT, compute_mode,
6989 simplify_gen_binary (ASHIFT,
6994 masked = simplify_gen_binary (ASHIFT, compute_mode,
6995 simplify_gen_binary (
6997 gen_lowpart (compute_mode, SET_SRC (x)),
7001 x = gen_rtx_SET (VOIDmode, copy_rtx (inner),
7002 simplify_gen_binary (IOR, compute_mode,
7009 /* Return an RTX for a reference to LEN bits of INNER. If POS_RTX is nonzero,
7010 it is an RTX that represents a variable starting position; otherwise,
7011 POS is the (constant) starting bit position (counted from the LSB).
7013 UNSIGNEDP is nonzero for an unsigned reference and zero for a
7016 IN_DEST is nonzero if this is a reference in the destination of a
7017 SET. This is used when a ZERO_ or SIGN_EXTRACT isn't needed. If nonzero,
7018 a STRICT_LOW_PART will be used, if zero, ZERO_EXTEND or SIGN_EXTEND will
7021 IN_COMPARE is nonzero if we are in a COMPARE. This means that a
7022 ZERO_EXTRACT should be built even for bits starting at bit 0.
7024 MODE is the desired mode of the result (if IN_DEST == 0).
7026 The result is an RTX for the extraction or NULL_RTX if the target
7030 make_extraction (enum machine_mode mode, rtx inner, HOST_WIDE_INT pos,
7031 rtx pos_rtx, unsigned HOST_WIDE_INT len, int unsignedp,
7032 int in_dest, int in_compare)
7034 /* This mode describes the size of the storage area
7035 to fetch the overall value from. Within that, we
7036 ignore the POS lowest bits, etc. */
7037 enum machine_mode is_mode = GET_MODE (inner);
7038 enum machine_mode inner_mode;
7039 enum machine_mode wanted_inner_mode;
7040 enum machine_mode wanted_inner_reg_mode = word_mode;
7041 enum machine_mode pos_mode = word_mode;
7042 enum machine_mode extraction_mode = word_mode;
7043 enum machine_mode tmode = mode_for_size (len, MODE_INT, 1);
7045 rtx orig_pos_rtx = pos_rtx;
7046 HOST_WIDE_INT orig_pos;
7048 if (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
7050 /* If going from (subreg:SI (mem:QI ...)) to (mem:QI ...),
7051 consider just the QI as the memory to extract from.
7052 The subreg adds or removes high bits; its mode is
7053 irrelevant to the meaning of this extraction,
7054 since POS and LEN count from the lsb. */
7055 if (MEM_P (SUBREG_REG (inner)))
7056 is_mode = GET_MODE (SUBREG_REG (inner));
7057 inner = SUBREG_REG (inner);
7059 else if (GET_CODE (inner) == ASHIFT
7060 && CONST_INT_P (XEXP (inner, 1))
7061 && pos_rtx == 0 && pos == 0
7062 && len > UINTVAL (XEXP (inner, 1)))
7064 /* We're extracting the least significant bits of an rtx
7065 (ashift X (const_int C)), where LEN > C. Extract the
7066 least significant (LEN - C) bits of X, giving an rtx
7067 whose mode is MODE, then shift it left C times. */
7068 new_rtx = make_extraction (mode, XEXP (inner, 0),
7069 0, 0, len - INTVAL (XEXP (inner, 1)),
7070 unsignedp, in_dest, in_compare);
7072 return gen_rtx_ASHIFT (mode, new_rtx, XEXP (inner, 1));
7075 inner_mode = GET_MODE (inner);
7077 if (pos_rtx && CONST_INT_P (pos_rtx))
7078 pos = INTVAL (pos_rtx), pos_rtx = 0;
7080 /* See if this can be done without an extraction. We never can if the
7081 width of the field is not the same as that of some integer mode. For
7082 registers, we can only avoid the extraction if the position is at the
7083 low-order bit and this is either not in the destination or we have the
7084 appropriate STRICT_LOW_PART operation available.
7086 For MEM, we can avoid an extract if the field starts on an appropriate
7087 boundary and we can change the mode of the memory reference. */
7089 if (tmode != BLKmode
7090 && ((pos_rtx == 0 && (pos % BITS_PER_WORD) == 0
7092 && (inner_mode == tmode
7094 || TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (tmode),
7095 GET_MODE_BITSIZE (inner_mode))
7096 || reg_truncated_to_mode (tmode, inner))
7099 && have_insn_for (STRICT_LOW_PART, tmode))))
7100 || (MEM_P (inner) && pos_rtx == 0
7102 % (STRICT_ALIGNMENT ? GET_MODE_ALIGNMENT (tmode)
7103 : BITS_PER_UNIT)) == 0
7104 /* We can't do this if we are widening INNER_MODE (it
7105 may not be aligned, for one thing). */
7106 && GET_MODE_BITSIZE (inner_mode) >= GET_MODE_BITSIZE (tmode)
7107 && (inner_mode == tmode
7108 || (! mode_dependent_address_p (XEXP (inner, 0))
7109 && ! MEM_VOLATILE_P (inner))))))
7111 /* If INNER is a MEM, make a new MEM that encompasses just the desired
7112 field. If the original and current mode are the same, we need not
7113 adjust the offset. Otherwise, we do if bytes big endian.
7115 If INNER is not a MEM, get a piece consisting of just the field
7116 of interest (in this case POS % BITS_PER_WORD must be 0). */
7120 HOST_WIDE_INT offset;
7122 /* POS counts from lsb, but make OFFSET count in memory order. */
7123 if (BYTES_BIG_ENDIAN)
7124 offset = (GET_MODE_BITSIZE (is_mode) - len - pos) / BITS_PER_UNIT;
7126 offset = pos / BITS_PER_UNIT;
7128 new_rtx = adjust_address_nv (inner, tmode, offset);
7130 else if (REG_P (inner))
7132 if (tmode != inner_mode)
7134 /* We can't call gen_lowpart in a DEST since we
7135 always want a SUBREG (see below) and it would sometimes
7136 return a new hard register. */
7139 HOST_WIDE_INT final_word = pos / BITS_PER_WORD;
7141 if (WORDS_BIG_ENDIAN
7142 && GET_MODE_SIZE (inner_mode) > UNITS_PER_WORD)
7143 final_word = ((GET_MODE_SIZE (inner_mode)
7144 - GET_MODE_SIZE (tmode))
7145 / UNITS_PER_WORD) - final_word;
7147 final_word *= UNITS_PER_WORD;
7148 if (BYTES_BIG_ENDIAN &&
7149 GET_MODE_SIZE (inner_mode) > GET_MODE_SIZE (tmode))
7150 final_word += (GET_MODE_SIZE (inner_mode)
7151 - GET_MODE_SIZE (tmode)) % UNITS_PER_WORD;
7153 /* Avoid creating invalid subregs, for example when
7154 simplifying (x>>32)&255. */
7155 if (!validate_subreg (tmode, inner_mode, inner, final_word))
7158 new_rtx = gen_rtx_SUBREG (tmode, inner, final_word);
7161 new_rtx = gen_lowpart (tmode, inner);
7167 new_rtx = force_to_mode (inner, tmode,
7168 len >= HOST_BITS_PER_WIDE_INT
7169 ? ~(unsigned HOST_WIDE_INT) 0
7170 : ((unsigned HOST_WIDE_INT) 1 << len) - 1,
7173 /* If this extraction is going into the destination of a SET,
7174 make a STRICT_LOW_PART unless we made a MEM. */
7177 return (MEM_P (new_rtx) ? new_rtx
7178 : (GET_CODE (new_rtx) != SUBREG
7179 ? gen_rtx_CLOBBER (tmode, const0_rtx)
7180 : gen_rtx_STRICT_LOW_PART (VOIDmode, new_rtx)));
7185 if (CONST_INT_P (new_rtx)
7186 || GET_CODE (new_rtx) == CONST_DOUBLE)
7187 return simplify_unary_operation (unsignedp ? ZERO_EXTEND : SIGN_EXTEND,
7188 mode, new_rtx, tmode);
7190 /* If we know that no extraneous bits are set, and that the high
7191 bit is not set, convert the extraction to the cheaper of
7192 sign and zero extension, that are equivalent in these cases. */
7193 if (flag_expensive_optimizations
7194 && (GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT
7195 && ((nonzero_bits (new_rtx, tmode)
7196 & ~(((unsigned HOST_WIDE_INT)
7197 GET_MODE_MASK (tmode))
7201 rtx temp = gen_rtx_ZERO_EXTEND (mode, new_rtx);
7202 rtx temp1 = gen_rtx_SIGN_EXTEND (mode, new_rtx);
7204 /* Prefer ZERO_EXTENSION, since it gives more information to
7206 if (rtx_cost (temp, SET, optimize_this_for_speed_p)
7207 <= rtx_cost (temp1, SET, optimize_this_for_speed_p))
7212 /* Otherwise, sign- or zero-extend unless we already are in the
7215 return (gen_rtx_fmt_e (unsignedp ? ZERO_EXTEND : SIGN_EXTEND,
7219 /* Unless this is a COMPARE or we have a funny memory reference,
7220 don't do anything with zero-extending field extracts starting at
7221 the low-order bit since they are simple AND operations. */
7222 if (pos_rtx == 0 && pos == 0 && ! in_dest
7223 && ! in_compare && unsignedp)
7226 /* Unless INNER is not MEM, reject this if we would be spanning bytes or
7227 if the position is not a constant and the length is not 1. In all
7228 other cases, we would only be going outside our object in cases when
7229 an original shift would have been undefined. */
7231 && ((pos_rtx == 0 && pos + len > GET_MODE_BITSIZE (is_mode))
7232 || (pos_rtx != 0 && len != 1)))
7235 /* Get the mode to use should INNER not be a MEM, the mode for the position,
7236 and the mode for the result. */
7237 if (in_dest && mode_for_extraction (EP_insv, -1) != MAX_MACHINE_MODE)
7239 wanted_inner_reg_mode = mode_for_extraction (EP_insv, 0);
7240 pos_mode = mode_for_extraction (EP_insv, 2);
7241 extraction_mode = mode_for_extraction (EP_insv, 3);
7244 if (! in_dest && unsignedp
7245 && mode_for_extraction (EP_extzv, -1) != MAX_MACHINE_MODE)
7247 wanted_inner_reg_mode = mode_for_extraction (EP_extzv, 1);
7248 pos_mode = mode_for_extraction (EP_extzv, 3);
7249 extraction_mode = mode_for_extraction (EP_extzv, 0);
7252 if (! in_dest && ! unsignedp
7253 && mode_for_extraction (EP_extv, -1) != MAX_MACHINE_MODE)
7255 wanted_inner_reg_mode = mode_for_extraction (EP_extv, 1);
7256 pos_mode = mode_for_extraction (EP_extv, 3);
7257 extraction_mode = mode_for_extraction (EP_extv, 0);
7260 /* Never narrow an object, since that might not be safe. */
7262 if (mode != VOIDmode
7263 && GET_MODE_SIZE (extraction_mode) < GET_MODE_SIZE (mode))
7264 extraction_mode = mode;
7266 if (pos_rtx && GET_MODE (pos_rtx) != VOIDmode
7267 && GET_MODE_SIZE (pos_mode) < GET_MODE_SIZE (GET_MODE (pos_rtx)))
7268 pos_mode = GET_MODE (pos_rtx);
7270 /* If this is not from memory, the desired mode is the preferred mode
7271 for an extraction pattern's first input operand, or word_mode if there
7274 wanted_inner_mode = wanted_inner_reg_mode;
7277 /* Be careful not to go beyond the extracted object and maintain the
7278 natural alignment of the memory. */
7279 wanted_inner_mode = smallest_mode_for_size (len, MODE_INT);
7280 while (pos % GET_MODE_BITSIZE (wanted_inner_mode) + len
7281 > GET_MODE_BITSIZE (wanted_inner_mode))
7283 wanted_inner_mode = GET_MODE_WIDER_MODE (wanted_inner_mode);
7284 gcc_assert (wanted_inner_mode != VOIDmode);
7287 /* If we have to change the mode of memory and cannot, the desired mode
7288 is EXTRACTION_MODE. */
7289 if (inner_mode != wanted_inner_mode
7290 && (mode_dependent_address_p (XEXP (inner, 0))
7291 || MEM_VOLATILE_P (inner)
7293 wanted_inner_mode = extraction_mode;
7298 if (BITS_BIG_ENDIAN)
7300 /* POS is passed as if BITS_BIG_ENDIAN == 0, so we need to convert it to
7301 BITS_BIG_ENDIAN style. If position is constant, compute new
7302 position. Otherwise, build subtraction.
7303 Note that POS is relative to the mode of the original argument.
7304 If it's a MEM we need to recompute POS relative to that.
7305 However, if we're extracting from (or inserting into) a register,
7306 we want to recompute POS relative to wanted_inner_mode. */
7307 int width = (MEM_P (inner)
7308 ? GET_MODE_BITSIZE (is_mode)
7309 : GET_MODE_BITSIZE (wanted_inner_mode));
7312 pos = width - len - pos;
7315 = gen_rtx_MINUS (GET_MODE (pos_rtx), GEN_INT (width - len), pos_rtx);
7316 /* POS may be less than 0 now, but we check for that below.
7317 Note that it can only be less than 0 if !MEM_P (inner). */
7320 /* If INNER has a wider mode, and this is a constant extraction, try to
7321 make it smaller and adjust the byte to point to the byte containing
7323 if (wanted_inner_mode != VOIDmode
7324 && inner_mode != wanted_inner_mode
7326 && GET_MODE_SIZE (wanted_inner_mode) < GET_MODE_SIZE (is_mode)
7328 && ! mode_dependent_address_p (XEXP (inner, 0))
7329 && ! MEM_VOLATILE_P (inner))
7333 /* The computations below will be correct if the machine is big
7334 endian in both bits and bytes or little endian in bits and bytes.
7335 If it is mixed, we must adjust. */
7337 /* If bytes are big endian and we had a paradoxical SUBREG, we must
7338 adjust OFFSET to compensate. */
7339 if (BYTES_BIG_ENDIAN
7340 && GET_MODE_SIZE (inner_mode) < GET_MODE_SIZE (is_mode))
7341 offset -= GET_MODE_SIZE (is_mode) - GET_MODE_SIZE (inner_mode);
7343 /* We can now move to the desired byte. */
7344 offset += (pos / GET_MODE_BITSIZE (wanted_inner_mode))
7345 * GET_MODE_SIZE (wanted_inner_mode);
7346 pos %= GET_MODE_BITSIZE (wanted_inner_mode);
7348 if (BYTES_BIG_ENDIAN != BITS_BIG_ENDIAN
7349 && is_mode != wanted_inner_mode)
7350 offset = (GET_MODE_SIZE (is_mode)
7351 - GET_MODE_SIZE (wanted_inner_mode) - offset);
7353 inner = adjust_address_nv (inner, wanted_inner_mode, offset);
7356 /* If INNER is not memory, get it into the proper mode. If we are changing
7357 its mode, POS must be a constant and smaller than the size of the new
7359 else if (!MEM_P (inner))
7361 /* On the LHS, don't create paradoxical subregs implicitely truncating
7362 the register unless TRULY_NOOP_TRUNCATION. */
7364 && !TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (GET_MODE (inner)),
7365 GET_MODE_BITSIZE (wanted_inner_mode)))
7368 if (GET_MODE (inner) != wanted_inner_mode
7370 || orig_pos + len > GET_MODE_BITSIZE (wanted_inner_mode)))
7376 inner = force_to_mode (inner, wanted_inner_mode,
7378 || len + orig_pos >= HOST_BITS_PER_WIDE_INT
7379 ? ~(unsigned HOST_WIDE_INT) 0
7380 : ((((unsigned HOST_WIDE_INT) 1 << len) - 1)
7385 /* Adjust mode of POS_RTX, if needed. If we want a wider mode, we
7386 have to zero extend. Otherwise, we can just use a SUBREG. */
7388 && GET_MODE_SIZE (pos_mode) > GET_MODE_SIZE (GET_MODE (pos_rtx)))
7390 rtx temp = gen_rtx_ZERO_EXTEND (pos_mode, pos_rtx);
7392 /* If we know that no extraneous bits are set, and that the high
7393 bit is not set, convert extraction to cheaper one - either
7394 SIGN_EXTENSION or ZERO_EXTENSION, that are equivalent in these
7396 if (flag_expensive_optimizations
7397 && (GET_MODE_BITSIZE (GET_MODE (pos_rtx)) <= HOST_BITS_PER_WIDE_INT
7398 && ((nonzero_bits (pos_rtx, GET_MODE (pos_rtx))
7399 & ~(((unsigned HOST_WIDE_INT)
7400 GET_MODE_MASK (GET_MODE (pos_rtx)))
7404 rtx temp1 = gen_rtx_SIGN_EXTEND (pos_mode, pos_rtx);
7406 /* Prefer ZERO_EXTENSION, since it gives more information to
7408 if (rtx_cost (temp1, SET, optimize_this_for_speed_p)
7409 < rtx_cost (temp, SET, optimize_this_for_speed_p))
7414 else if (pos_rtx != 0
7415 && GET_MODE_SIZE (pos_mode) < GET_MODE_SIZE (GET_MODE (pos_rtx)))
7416 pos_rtx = gen_lowpart (pos_mode, pos_rtx);
7418 /* Make POS_RTX unless we already have it and it is correct. If we don't
7419 have a POS_RTX but we do have an ORIG_POS_RTX, the latter must
7421 if (pos_rtx == 0 && orig_pos_rtx != 0 && INTVAL (orig_pos_rtx) == pos)
7422 pos_rtx = orig_pos_rtx;
7424 else if (pos_rtx == 0)
7425 pos_rtx = GEN_INT (pos);
7427 /* Make the required operation. See if we can use existing rtx. */
7428 new_rtx = gen_rtx_fmt_eee (unsignedp ? ZERO_EXTRACT : SIGN_EXTRACT,
7429 extraction_mode, inner, GEN_INT (len), pos_rtx);
7431 new_rtx = gen_lowpart (mode, new_rtx);
7436 /* See if X contains an ASHIFT of COUNT or more bits that can be commuted
7437 with any other operations in X. Return X without that shift if so. */
7440 extract_left_shift (rtx x, int count)
7442 enum rtx_code code = GET_CODE (x);
7443 enum machine_mode mode = GET_MODE (x);
7449 /* This is the shift itself. If it is wide enough, we will return
7450 either the value being shifted if the shift count is equal to
7451 COUNT or a shift for the difference. */
7452 if (CONST_INT_P (XEXP (x, 1))
7453 && INTVAL (XEXP (x, 1)) >= count)
7454 return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (x, 0),
7455 INTVAL (XEXP (x, 1)) - count);
7459 if ((tem = extract_left_shift (XEXP (x, 0), count)) != 0)
7460 return simplify_gen_unary (code, mode, tem, mode);
7464 case PLUS: case IOR: case XOR: case AND:
7465 /* If we can safely shift this constant and we find the inner shift,
7466 make a new operation. */
7467 if (CONST_INT_P (XEXP (x, 1))
7468 && (UINTVAL (XEXP (x, 1))
7469 & ((((unsigned HOST_WIDE_INT) 1 << count)) - 1)) == 0
7470 && (tem = extract_left_shift (XEXP (x, 0), count)) != 0)
7471 return simplify_gen_binary (code, mode, tem,
7472 GEN_INT (INTVAL (XEXP (x, 1)) >> count));
7483 /* Look at the expression rooted at X. Look for expressions
7484 equivalent to ZERO_EXTRACT, SIGN_EXTRACT, ZERO_EXTEND, SIGN_EXTEND.
7485 Form these expressions.
7487 Return the new rtx, usually just X.
7489 Also, for machines like the VAX that don't have logical shift insns,
7490 try to convert logical to arithmetic shift operations in cases where
7491 they are equivalent. This undoes the canonicalizations to logical
7492 shifts done elsewhere.
7494 We try, as much as possible, to re-use rtl expressions to save memory.
7496 IN_CODE says what kind of expression we are processing. Normally, it is
7497 SET. In a memory address (inside a MEM, PLUS or minus, the latter two
7498 being kludges), it is MEM. When processing the arguments of a comparison
7499 or a COMPARE against zero, it is COMPARE. */
7502 make_compound_operation (rtx x, enum rtx_code in_code)
7504 enum rtx_code code = GET_CODE (x);
7505 enum machine_mode mode = GET_MODE (x);
7506 int mode_width = GET_MODE_BITSIZE (mode);
7508 enum rtx_code next_code;
7514 /* Select the code to be used in recursive calls. Once we are inside an
7515 address, we stay there. If we have a comparison, set to COMPARE,
7516 but once inside, go back to our default of SET. */
7518 next_code = (code == MEM ? MEM
7519 : ((code == PLUS || code == MINUS)
7520 && SCALAR_INT_MODE_P (mode)) ? MEM
7521 : ((code == COMPARE || COMPARISON_P (x))
7522 && XEXP (x, 1) == const0_rtx) ? COMPARE
7523 : in_code == COMPARE ? SET : in_code);
7525 /* Process depending on the code of this operation. If NEW is set
7526 nonzero, it will be returned. */
7531 /* Convert shifts by constants into multiplications if inside
7533 if (in_code == MEM && CONST_INT_P (XEXP (x, 1))
7534 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT
7535 && INTVAL (XEXP (x, 1)) >= 0
7536 && SCALAR_INT_MODE_P (mode))
7538 HOST_WIDE_INT count = INTVAL (XEXP (x, 1));
7539 HOST_WIDE_INT multval = (HOST_WIDE_INT) 1 << count;
7541 new_rtx = make_compound_operation (XEXP (x, 0), next_code);
7542 if (GET_CODE (new_rtx) == NEG)
7544 new_rtx = XEXP (new_rtx, 0);
7547 multval = trunc_int_for_mode (multval, mode);
7548 new_rtx = gen_rtx_MULT (mode, new_rtx, GEN_INT (multval));
7555 lhs = make_compound_operation (lhs, next_code);
7556 rhs = make_compound_operation (rhs, next_code);
7557 if (GET_CODE (lhs) == MULT && GET_CODE (XEXP (lhs, 0)) == NEG
7558 && SCALAR_INT_MODE_P (mode))
7560 tem = simplify_gen_binary (MULT, mode, XEXP (XEXP (lhs, 0), 0),
7562 new_rtx = simplify_gen_binary (MINUS, mode, rhs, tem);
7564 else if (GET_CODE (lhs) == MULT
7565 && (CONST_INT_P (XEXP (lhs, 1)) && INTVAL (XEXP (lhs, 1)) < 0))
7567 tem = simplify_gen_binary (MULT, mode, XEXP (lhs, 0),
7568 simplify_gen_unary (NEG, mode,
7571 new_rtx = simplify_gen_binary (MINUS, mode, rhs, tem);
7575 SUBST (XEXP (x, 0), lhs);
7576 SUBST (XEXP (x, 1), rhs);
7579 x = gen_lowpart (mode, new_rtx);
7585 lhs = make_compound_operation (lhs, next_code);
7586 rhs = make_compound_operation (rhs, next_code);
7587 if (GET_CODE (rhs) == MULT && GET_CODE (XEXP (rhs, 0)) == NEG
7588 && SCALAR_INT_MODE_P (mode))
7590 tem = simplify_gen_binary (MULT, mode, XEXP (XEXP (rhs, 0), 0),
7592 new_rtx = simplify_gen_binary (PLUS, mode, tem, lhs);
7594 else if (GET_CODE (rhs) == MULT
7595 && (CONST_INT_P (XEXP (rhs, 1)) && INTVAL (XEXP (rhs, 1)) < 0))
7597 tem = simplify_gen_binary (MULT, mode, XEXP (rhs, 0),
7598 simplify_gen_unary (NEG, mode,
7601 new_rtx = simplify_gen_binary (PLUS, mode, tem, lhs);
7605 SUBST (XEXP (x, 0), lhs);
7606 SUBST (XEXP (x, 1), rhs);
7609 return gen_lowpart (mode, new_rtx);
7612 /* If the second operand is not a constant, we can't do anything
7614 if (!CONST_INT_P (XEXP (x, 1)))
7617 /* If the constant is a power of two minus one and the first operand
7618 is a logical right shift, make an extraction. */
7619 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
7620 && (i = exact_log2 (UINTVAL (XEXP (x, 1)) + 1)) >= 0)
7622 new_rtx = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code);
7623 new_rtx = make_extraction (mode, new_rtx, 0, XEXP (XEXP (x, 0), 1), i, 1,
7624 0, in_code == COMPARE);
7627 /* Same as previous, but for (subreg (lshiftrt ...)) in first op. */
7628 else if (GET_CODE (XEXP (x, 0)) == SUBREG
7629 && subreg_lowpart_p (XEXP (x, 0))
7630 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == LSHIFTRT
7631 && (i = exact_log2 (UINTVAL (XEXP (x, 1)) + 1)) >= 0)
7633 new_rtx = make_compound_operation (XEXP (SUBREG_REG (XEXP (x, 0)), 0),
7635 new_rtx = make_extraction (GET_MODE (SUBREG_REG (XEXP (x, 0))), new_rtx, 0,
7636 XEXP (SUBREG_REG (XEXP (x, 0)), 1), i, 1,
7637 0, in_code == COMPARE);
7639 /* Same as previous, but for (xor/ior (lshiftrt...) (lshiftrt...)). */
7640 else if ((GET_CODE (XEXP (x, 0)) == XOR
7641 || GET_CODE (XEXP (x, 0)) == IOR)
7642 && GET_CODE (XEXP (XEXP (x, 0), 0)) == LSHIFTRT
7643 && GET_CODE (XEXP (XEXP (x, 0), 1)) == LSHIFTRT
7644 && (i = exact_log2 (UINTVAL (XEXP (x, 1)) + 1)) >= 0)
7646 /* Apply the distributive law, and then try to make extractions. */
7647 new_rtx = gen_rtx_fmt_ee (GET_CODE (XEXP (x, 0)), mode,
7648 gen_rtx_AND (mode, XEXP (XEXP (x, 0), 0),
7650 gen_rtx_AND (mode, XEXP (XEXP (x, 0), 1),
7652 new_rtx = make_compound_operation (new_rtx, in_code);
7655 /* If we are have (and (rotate X C) M) and C is larger than the number
7656 of bits in M, this is an extraction. */
7658 else if (GET_CODE (XEXP (x, 0)) == ROTATE
7659 && CONST_INT_P (XEXP (XEXP (x, 0), 1))
7660 && (i = exact_log2 (UINTVAL (XEXP (x, 1)) + 1)) >= 0
7661 && i <= INTVAL (XEXP (XEXP (x, 0), 1)))
7663 new_rtx = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code);
7664 new_rtx = make_extraction (mode, new_rtx,
7665 (GET_MODE_BITSIZE (mode)
7666 - INTVAL (XEXP (XEXP (x, 0), 1))),
7667 NULL_RTX, i, 1, 0, in_code == COMPARE);
7670 /* On machines without logical shifts, if the operand of the AND is
7671 a logical shift and our mask turns off all the propagated sign
7672 bits, we can replace the logical shift with an arithmetic shift. */
7673 else if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
7674 && !have_insn_for (LSHIFTRT, mode)
7675 && have_insn_for (ASHIFTRT, mode)
7676 && CONST_INT_P (XEXP (XEXP (x, 0), 1))
7677 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
7678 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT
7679 && mode_width <= HOST_BITS_PER_WIDE_INT)
7681 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
7683 mask >>= INTVAL (XEXP (XEXP (x, 0), 1));
7684 if ((INTVAL (XEXP (x, 1)) & ~mask) == 0)
7686 gen_rtx_ASHIFTRT (mode,
7687 make_compound_operation
7688 (XEXP (XEXP (x, 0), 0), next_code),
7689 XEXP (XEXP (x, 0), 1)));
7692 /* If the constant is one less than a power of two, this might be
7693 representable by an extraction even if no shift is present.
7694 If it doesn't end up being a ZERO_EXTEND, we will ignore it unless
7695 we are in a COMPARE. */
7696 else if ((i = exact_log2 (UINTVAL (XEXP (x, 1)) + 1)) >= 0)
7697 new_rtx = make_extraction (mode,
7698 make_compound_operation (XEXP (x, 0),
7700 0, NULL_RTX, i, 1, 0, in_code == COMPARE);
7702 /* If we are in a comparison and this is an AND with a power of two,
7703 convert this into the appropriate bit extract. */
7704 else if (in_code == COMPARE
7705 && (i = exact_log2 (UINTVAL (XEXP (x, 1)))) >= 0)
7706 new_rtx = make_extraction (mode,
7707 make_compound_operation (XEXP (x, 0),
7709 i, NULL_RTX, 1, 1, 0, 1);
7714 /* If the sign bit is known to be zero, replace this with an
7715 arithmetic shift. */
7716 if (have_insn_for (ASHIFTRT, mode)
7717 && ! have_insn_for (LSHIFTRT, mode)
7718 && mode_width <= HOST_BITS_PER_WIDE_INT
7719 && (nonzero_bits (XEXP (x, 0), mode) & (1 << (mode_width - 1))) == 0)
7721 new_rtx = gen_rtx_ASHIFTRT (mode,
7722 make_compound_operation (XEXP (x, 0),
7728 /* ... fall through ... */
7734 /* If we have (ashiftrt (ashift foo C1) C2) with C2 >= C1,
7735 this is a SIGN_EXTRACT. */
7736 if (CONST_INT_P (rhs)
7737 && GET_CODE (lhs) == ASHIFT
7738 && CONST_INT_P (XEXP (lhs, 1))
7739 && INTVAL (rhs) >= INTVAL (XEXP (lhs, 1))
7740 && INTVAL (rhs) < mode_width)
7742 new_rtx = make_compound_operation (XEXP (lhs, 0), next_code);
7743 new_rtx = make_extraction (mode, new_rtx,
7744 INTVAL (rhs) - INTVAL (XEXP (lhs, 1)),
7745 NULL_RTX, mode_width - INTVAL (rhs),
7746 code == LSHIFTRT, 0, in_code == COMPARE);
7750 /* See if we have operations between an ASHIFTRT and an ASHIFT.
7751 If so, try to merge the shifts into a SIGN_EXTEND. We could
7752 also do this for some cases of SIGN_EXTRACT, but it doesn't
7753 seem worth the effort; the case checked for occurs on Alpha. */
7756 && ! (GET_CODE (lhs) == SUBREG
7757 && (OBJECT_P (SUBREG_REG (lhs))))
7758 && CONST_INT_P (rhs)
7759 && INTVAL (rhs) < HOST_BITS_PER_WIDE_INT
7760 && INTVAL (rhs) < mode_width
7761 && (new_rtx = extract_left_shift (lhs, INTVAL (rhs))) != 0)
7762 new_rtx = make_extraction (mode, make_compound_operation (new_rtx, next_code),
7763 0, NULL_RTX, mode_width - INTVAL (rhs),
7764 code == LSHIFTRT, 0, in_code == COMPARE);
7769 /* Call ourselves recursively on the inner expression. If we are
7770 narrowing the object and it has a different RTL code from
7771 what it originally did, do this SUBREG as a force_to_mode. */
7773 rtx inner = SUBREG_REG (x), simplified;
7775 tem = make_compound_operation (inner, in_code);
7778 = simplify_subreg (mode, tem, GET_MODE (inner), SUBREG_BYTE (x));
7782 if (GET_CODE (tem) != GET_CODE (inner)
7783 && GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (inner))
7784 && subreg_lowpart_p (x))
7787 = force_to_mode (tem, mode, ~(unsigned HOST_WIDE_INT) 0, 0);
7789 /* If we have something other than a SUBREG, we might have
7790 done an expansion, so rerun ourselves. */
7791 if (GET_CODE (newer) != SUBREG)
7792 newer = make_compound_operation (newer, in_code);
7794 /* force_to_mode can expand compounds. If it just re-expanded the
7795 compound, use gen_lowpart to convert to the desired mode. */
7796 if (rtx_equal_p (newer, x)
7797 /* Likewise if it re-expanded the compound only partially.
7798 This happens for SUBREG of ZERO_EXTRACT if they extract
7799 the same number of bits. */
7800 || (GET_CODE (newer) == SUBREG
7801 && (GET_CODE (SUBREG_REG (newer)) == LSHIFTRT
7802 || GET_CODE (SUBREG_REG (newer)) == ASHIFTRT)
7803 && GET_CODE (inner) == AND
7804 && rtx_equal_p (SUBREG_REG (newer), XEXP (inner, 0))))
7805 return gen_lowpart (GET_MODE (x), tem);
7821 x = gen_lowpart (mode, new_rtx);
7822 code = GET_CODE (x);
7825 /* Now recursively process each operand of this operation. */
7826 fmt = GET_RTX_FORMAT (code);
7827 for (i = 0; i < GET_RTX_LENGTH (code); i++)
7830 new_rtx = make_compound_operation (XEXP (x, i), next_code);
7831 SUBST (XEXP (x, i), new_rtx);
7833 else if (fmt[i] == 'E')
7834 for (j = 0; j < XVECLEN (x, i); j++)
7836 new_rtx = make_compound_operation (XVECEXP (x, i, j), next_code);
7837 SUBST (XVECEXP (x, i, j), new_rtx);
7841 /* If this is a commutative operation, the changes to the operands
7842 may have made it noncanonical. */
7843 if (COMMUTATIVE_ARITH_P (x)
7844 && swap_commutative_operands_p (XEXP (x, 0), XEXP (x, 1)))
7847 SUBST (XEXP (x, 0), XEXP (x, 1));
7848 SUBST (XEXP (x, 1), tem);
7854 /* Given M see if it is a value that would select a field of bits
7855 within an item, but not the entire word. Return -1 if not.
7856 Otherwise, return the starting position of the field, where 0 is the
7859 *PLEN is set to the length of the field. */
7862 get_pos_from_mask (unsigned HOST_WIDE_INT m, unsigned HOST_WIDE_INT *plen)
7864 /* Get the bit number of the first 1 bit from the right, -1 if none. */
7865 int pos = m ? ctz_hwi (m) : -1;
7869 /* Now shift off the low-order zero bits and see if we have a
7870 power of two minus 1. */
7871 len = exact_log2 ((m >> pos) + 1);
7880 /* If X refers to a register that equals REG in value, replace these
7881 references with REG. */
7883 canon_reg_for_combine (rtx x, rtx reg)
7890 enum rtx_code code = GET_CODE (x);
7891 switch (GET_RTX_CLASS (code))
7894 op0 = canon_reg_for_combine (XEXP (x, 0), reg);
7895 if (op0 != XEXP (x, 0))
7896 return simplify_gen_unary (GET_CODE (x), GET_MODE (x), op0,
7901 case RTX_COMM_ARITH:
7902 op0 = canon_reg_for_combine (XEXP (x, 0), reg);
7903 op1 = canon_reg_for_combine (XEXP (x, 1), reg);
7904 if (op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
7905 return simplify_gen_binary (GET_CODE (x), GET_MODE (x), op0, op1);
7909 case RTX_COMM_COMPARE:
7910 op0 = canon_reg_for_combine (XEXP (x, 0), reg);
7911 op1 = canon_reg_for_combine (XEXP (x, 1), reg);
7912 if (op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
7913 return simplify_gen_relational (GET_CODE (x), GET_MODE (x),
7914 GET_MODE (op0), op0, op1);
7918 case RTX_BITFIELD_OPS:
7919 op0 = canon_reg_for_combine (XEXP (x, 0), reg);
7920 op1 = canon_reg_for_combine (XEXP (x, 1), reg);
7921 op2 = canon_reg_for_combine (XEXP (x, 2), reg);
7922 if (op0 != XEXP (x, 0) || op1 != XEXP (x, 1) || op2 != XEXP (x, 2))
7923 return simplify_gen_ternary (GET_CODE (x), GET_MODE (x),
7924 GET_MODE (op0), op0, op1, op2);
7929 if (rtx_equal_p (get_last_value (reg), x)
7930 || rtx_equal_p (reg, get_last_value (x)))
7939 fmt = GET_RTX_FORMAT (code);
7941 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
7944 rtx op = canon_reg_for_combine (XEXP (x, i), reg);
7945 if (op != XEXP (x, i))
7955 else if (fmt[i] == 'E')
7958 for (j = 0; j < XVECLEN (x, i); j++)
7960 rtx op = canon_reg_for_combine (XVECEXP (x, i, j), reg);
7961 if (op != XVECEXP (x, i, j))
7968 XVECEXP (x, i, j) = op;
7979 /* Return X converted to MODE. If the value is already truncated to
7980 MODE we can just return a subreg even though in the general case we
7981 would need an explicit truncation. */
7984 gen_lowpart_or_truncate (enum machine_mode mode, rtx x)
7986 if (!CONST_INT_P (x)
7987 && GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (x))
7988 && !TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode),
7989 GET_MODE_BITSIZE (GET_MODE (x)))
7990 && !(REG_P (x) && reg_truncated_to_mode (mode, x)))
7992 /* Bit-cast X into an integer mode. */
7993 if (!SCALAR_INT_MODE_P (GET_MODE (x)))
7994 x = gen_lowpart (int_mode_for_mode (GET_MODE (x)), x);
7995 x = simplify_gen_unary (TRUNCATE, int_mode_for_mode (mode),
7999 return gen_lowpart (mode, x);
8002 /* See if X can be simplified knowing that we will only refer to it in
8003 MODE and will only refer to those bits that are nonzero in MASK.
8004 If other bits are being computed or if masking operations are done
8005 that select a superset of the bits in MASK, they can sometimes be
8008 Return a possibly simplified expression, but always convert X to
8009 MODE. If X is a CONST_INT, AND the CONST_INT with MASK.
8011 If JUST_SELECT is nonzero, don't optimize by noticing that bits in MASK
8012 are all off in X. This is used when X will be complemented, by either
8013 NOT, NEG, or XOR. */
8016 force_to_mode (rtx x, enum machine_mode mode, unsigned HOST_WIDE_INT mask,
8019 enum rtx_code code = GET_CODE (x);
8020 int next_select = just_select || code == XOR || code == NOT || code == NEG;
8021 enum machine_mode op_mode;
8022 unsigned HOST_WIDE_INT fuller_mask, nonzero;
8025 /* If this is a CALL or ASM_OPERANDS, don't do anything. Some of the
8026 code below will do the wrong thing since the mode of such an
8027 expression is VOIDmode.
8029 Also do nothing if X is a CLOBBER; this can happen if X was
8030 the return value from a call to gen_lowpart. */
8031 if (code == CALL || code == ASM_OPERANDS || code == CLOBBER)
8034 /* We want to perform the operation is its present mode unless we know
8035 that the operation is valid in MODE, in which case we do the operation
8037 op_mode = ((GET_MODE_CLASS (mode) == GET_MODE_CLASS (GET_MODE (x))
8038 && have_insn_for (code, mode))
8039 ? mode : GET_MODE (x));
8041 /* It is not valid to do a right-shift in a narrower mode
8042 than the one it came in with. */
8043 if ((code == LSHIFTRT || code == ASHIFTRT)
8044 && GET_MODE_BITSIZE (mode) < GET_MODE_BITSIZE (GET_MODE (x)))
8045 op_mode = GET_MODE (x);
8047 /* Truncate MASK to fit OP_MODE. */
8049 mask &= GET_MODE_MASK (op_mode);
8051 /* When we have an arithmetic operation, or a shift whose count we
8052 do not know, we need to assume that all bits up to the highest-order
8053 bit in MASK will be needed. This is how we form such a mask. */
8054 if (mask & ((unsigned HOST_WIDE_INT) 1 << (HOST_BITS_PER_WIDE_INT - 1)))
8055 fuller_mask = ~(unsigned HOST_WIDE_INT) 0;
8057 fuller_mask = (((unsigned HOST_WIDE_INT) 1 << (floor_log2 (mask) + 1))
8060 /* Determine what bits of X are guaranteed to be (non)zero. */
8061 nonzero = nonzero_bits (x, mode);
8063 /* If none of the bits in X are needed, return a zero. */
8064 if (!just_select && (nonzero & mask) == 0 && !side_effects_p (x))
8067 /* If X is a CONST_INT, return a new one. Do this here since the
8068 test below will fail. */
8069 if (CONST_INT_P (x))
8071 if (SCALAR_INT_MODE_P (mode))
8072 return gen_int_mode (INTVAL (x) & mask, mode);
8075 x = GEN_INT (INTVAL (x) & mask);
8076 return gen_lowpart_common (mode, x);
8080 /* If X is narrower than MODE and we want all the bits in X's mode, just
8081 get X in the proper mode. */
8082 if (GET_MODE_SIZE (GET_MODE (x)) < GET_MODE_SIZE (mode)
8083 && (GET_MODE_MASK (GET_MODE (x)) & ~mask) == 0)
8084 return gen_lowpart (mode, x);
8086 /* We can ignore the effect of a SUBREG if it narrows the mode or
8087 if the constant masks to zero all the bits the mode doesn't have. */
8088 if (GET_CODE (x) == SUBREG
8089 && subreg_lowpart_p (x)
8090 && ((GET_MODE_SIZE (GET_MODE (x))
8091 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
8093 & GET_MODE_MASK (GET_MODE (x))
8094 & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (x)))))))
8095 return force_to_mode (SUBREG_REG (x), mode, mask, next_select);
8097 /* The arithmetic simplifications here only work for scalar integer modes. */
8098 if (!SCALAR_INT_MODE_P (mode) || !SCALAR_INT_MODE_P (GET_MODE (x)))
8099 return gen_lowpart_or_truncate (mode, x);
8104 /* If X is a (clobber (const_int)), return it since we know we are
8105 generating something that won't match. */
8112 x = expand_compound_operation (x);
8113 if (GET_CODE (x) != code)
8114 return force_to_mode (x, mode, mask, next_select);
8118 /* Similarly for a truncate. */
8119 return force_to_mode (XEXP (x, 0), mode, mask, next_select);
8122 /* If this is an AND with a constant, convert it into an AND
8123 whose constant is the AND of that constant with MASK. If it
8124 remains an AND of MASK, delete it since it is redundant. */
8126 if (CONST_INT_P (XEXP (x, 1)))
8128 x = simplify_and_const_int (x, op_mode, XEXP (x, 0),
8129 mask & INTVAL (XEXP (x, 1)));
8131 /* If X is still an AND, see if it is an AND with a mask that
8132 is just some low-order bits. If so, and it is MASK, we don't
8135 if (GET_CODE (x) == AND && CONST_INT_P (XEXP (x, 1))
8136 && ((INTVAL (XEXP (x, 1)) & GET_MODE_MASK (GET_MODE (x)))
8140 /* If it remains an AND, try making another AND with the bits
8141 in the mode mask that aren't in MASK turned on. If the
8142 constant in the AND is wide enough, this might make a
8143 cheaper constant. */
8145 if (GET_CODE (x) == AND && CONST_INT_P (XEXP (x, 1))
8146 && GET_MODE_MASK (GET_MODE (x)) != mask
8147 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT)
8149 unsigned HOST_WIDE_INT cval
8150 = UINTVAL (XEXP (x, 1))
8151 | (GET_MODE_MASK (GET_MODE (x)) & ~mask);
8152 int width = GET_MODE_BITSIZE (GET_MODE (x));
8155 /* If MODE is narrower than HOST_WIDE_INT and CVAL is a negative
8156 number, sign extend it. */
8157 if (width > 0 && width < HOST_BITS_PER_WIDE_INT
8158 && (cval & ((unsigned HOST_WIDE_INT) 1 << (width - 1))) != 0)
8159 cval |= (unsigned HOST_WIDE_INT) -1 << width;
8161 y = simplify_gen_binary (AND, GET_MODE (x),
8162 XEXP (x, 0), GEN_INT (cval));
8163 if (rtx_cost (y, SET, optimize_this_for_speed_p)
8164 < rtx_cost (x, SET, optimize_this_for_speed_p))
8174 /* In (and (plus FOO C1) M), if M is a mask that just turns off
8175 low-order bits (as in an alignment operation) and FOO is already
8176 aligned to that boundary, mask C1 to that boundary as well.
8177 This may eliminate that PLUS and, later, the AND. */
8180 unsigned int width = GET_MODE_BITSIZE (mode);
8181 unsigned HOST_WIDE_INT smask = mask;
8183 /* If MODE is narrower than HOST_WIDE_INT and mask is a negative
8184 number, sign extend it. */
8186 if (width < HOST_BITS_PER_WIDE_INT
8187 && (smask & ((unsigned HOST_WIDE_INT) 1 << (width - 1))) != 0)
8188 smask |= (unsigned HOST_WIDE_INT) (-1) << width;
8190 if (CONST_INT_P (XEXP (x, 1))
8191 && exact_log2 (- smask) >= 0
8192 && (nonzero_bits (XEXP (x, 0), mode) & ~smask) == 0
8193 && (INTVAL (XEXP (x, 1)) & ~smask) != 0)
8194 return force_to_mode (plus_constant (XEXP (x, 0),
8195 (INTVAL (XEXP (x, 1)) & smask)),
8196 mode, smask, next_select);
8199 /* ... fall through ... */
8202 /* For PLUS, MINUS and MULT, we need any bits less significant than the
8203 most significant bit in MASK since carries from those bits will
8204 affect the bits we are interested in. */
8209 /* If X is (minus C Y) where C's least set bit is larger than any bit
8210 in the mask, then we may replace with (neg Y). */
8211 if (CONST_INT_P (XEXP (x, 0))
8212 && (((unsigned HOST_WIDE_INT) (INTVAL (XEXP (x, 0))
8213 & -INTVAL (XEXP (x, 0))))
8216 x = simplify_gen_unary (NEG, GET_MODE (x), XEXP (x, 1),
8218 return force_to_mode (x, mode, mask, next_select);
8221 /* Similarly, if C contains every bit in the fuller_mask, then we may
8222 replace with (not Y). */
8223 if (CONST_INT_P (XEXP (x, 0))
8224 && ((UINTVAL (XEXP (x, 0)) | fuller_mask) == UINTVAL (XEXP (x, 0))))
8226 x = simplify_gen_unary (NOT, GET_MODE (x),
8227 XEXP (x, 1), GET_MODE (x));
8228 return force_to_mode (x, mode, mask, next_select);
8236 /* If X is (ior (lshiftrt FOO C1) C2), try to commute the IOR and
8237 LSHIFTRT so we end up with an (and (lshiftrt (ior ...) ...) ...)
8238 operation which may be a bitfield extraction. Ensure that the
8239 constant we form is not wider than the mode of X. */
8241 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
8242 && CONST_INT_P (XEXP (XEXP (x, 0), 1))
8243 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
8244 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT
8245 && CONST_INT_P (XEXP (x, 1))
8246 && ((INTVAL (XEXP (XEXP (x, 0), 1))
8247 + floor_log2 (INTVAL (XEXP (x, 1))))
8248 < GET_MODE_BITSIZE (GET_MODE (x)))
8249 && (UINTVAL (XEXP (x, 1))
8250 & ~nonzero_bits (XEXP (x, 0), GET_MODE (x))) == 0)
8252 temp = GEN_INT ((INTVAL (XEXP (x, 1)) & mask)
8253 << INTVAL (XEXP (XEXP (x, 0), 1)));
8254 temp = simplify_gen_binary (GET_CODE (x), GET_MODE (x),
8255 XEXP (XEXP (x, 0), 0), temp);
8256 x = simplify_gen_binary (LSHIFTRT, GET_MODE (x), temp,
8257 XEXP (XEXP (x, 0), 1));
8258 return force_to_mode (x, mode, mask, next_select);
8262 /* For most binary operations, just propagate into the operation and
8263 change the mode if we have an operation of that mode. */
8265 op0 = force_to_mode (XEXP (x, 0), mode, mask, next_select);
8266 op1 = force_to_mode (XEXP (x, 1), mode, mask, next_select);
8268 /* If we ended up truncating both operands, truncate the result of the
8269 operation instead. */
8270 if (GET_CODE (op0) == TRUNCATE
8271 && GET_CODE (op1) == TRUNCATE)
8273 op0 = XEXP (op0, 0);
8274 op1 = XEXP (op1, 0);
8277 op0 = gen_lowpart_or_truncate (op_mode, op0);
8278 op1 = gen_lowpart_or_truncate (op_mode, op1);
8280 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
8281 x = simplify_gen_binary (code, op_mode, op0, op1);
8285 /* For left shifts, do the same, but just for the first operand.
8286 However, we cannot do anything with shifts where we cannot
8287 guarantee that the counts are smaller than the size of the mode
8288 because such a count will have a different meaning in a
8291 if (! (CONST_INT_P (XEXP (x, 1))
8292 && INTVAL (XEXP (x, 1)) >= 0
8293 && INTVAL (XEXP (x, 1)) < GET_MODE_BITSIZE (mode))
8294 && ! (GET_MODE (XEXP (x, 1)) != VOIDmode
8295 && (nonzero_bits (XEXP (x, 1), GET_MODE (XEXP (x, 1)))
8296 < (unsigned HOST_WIDE_INT) GET_MODE_BITSIZE (mode))))
8299 /* If the shift count is a constant and we can do arithmetic in
8300 the mode of the shift, refine which bits we need. Otherwise, use the
8301 conservative form of the mask. */
8302 if (CONST_INT_P (XEXP (x, 1))
8303 && INTVAL (XEXP (x, 1)) >= 0
8304 && INTVAL (XEXP (x, 1)) < GET_MODE_BITSIZE (op_mode)
8305 && GET_MODE_BITSIZE (op_mode) <= HOST_BITS_PER_WIDE_INT)
8306 mask >>= INTVAL (XEXP (x, 1));
8310 op0 = gen_lowpart_or_truncate (op_mode,
8311 force_to_mode (XEXP (x, 0), op_mode,
8312 mask, next_select));
8314 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0))
8315 x = simplify_gen_binary (code, op_mode, op0, XEXP (x, 1));
8319 /* Here we can only do something if the shift count is a constant,
8320 this shift constant is valid for the host, and we can do arithmetic
8323 if (CONST_INT_P (XEXP (x, 1))
8324 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT
8325 && GET_MODE_BITSIZE (op_mode) <= HOST_BITS_PER_WIDE_INT)
8327 rtx inner = XEXP (x, 0);
8328 unsigned HOST_WIDE_INT inner_mask;
8330 /* Select the mask of the bits we need for the shift operand. */
8331 inner_mask = mask << INTVAL (XEXP (x, 1));
8333 /* We can only change the mode of the shift if we can do arithmetic
8334 in the mode of the shift and INNER_MASK is no wider than the
8335 width of X's mode. */
8336 if ((inner_mask & ~GET_MODE_MASK (GET_MODE (x))) != 0)
8337 op_mode = GET_MODE (x);
8339 inner = force_to_mode (inner, op_mode, inner_mask, next_select);
8341 if (GET_MODE (x) != op_mode || inner != XEXP (x, 0))
8342 x = simplify_gen_binary (LSHIFTRT, op_mode, inner, XEXP (x, 1));
8345 /* If we have (and (lshiftrt FOO C1) C2) where the combination of the
8346 shift and AND produces only copies of the sign bit (C2 is one less
8347 than a power of two), we can do this with just a shift. */
8349 if (GET_CODE (x) == LSHIFTRT
8350 && CONST_INT_P (XEXP (x, 1))
8351 /* The shift puts one of the sign bit copies in the least significant
8353 && ((INTVAL (XEXP (x, 1))
8354 + num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0))))
8355 >= GET_MODE_BITSIZE (GET_MODE (x)))
8356 && exact_log2 (mask + 1) >= 0
8357 /* Number of bits left after the shift must be more than the mask
8359 && ((INTVAL (XEXP (x, 1)) + exact_log2 (mask + 1))
8360 <= GET_MODE_BITSIZE (GET_MODE (x)))
8361 /* Must be more sign bit copies than the mask needs. */
8362 && ((int) num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
8363 >= exact_log2 (mask + 1)))
8364 x = simplify_gen_binary (LSHIFTRT, GET_MODE (x), XEXP (x, 0),
8365 GEN_INT (GET_MODE_BITSIZE (GET_MODE (x))
8366 - exact_log2 (mask + 1)));
8371 /* If we are just looking for the sign bit, we don't need this shift at
8372 all, even if it has a variable count. */
8373 if (GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
8374 && (mask == ((unsigned HOST_WIDE_INT) 1
8375 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
8376 return force_to_mode (XEXP (x, 0), mode, mask, next_select);
8378 /* If this is a shift by a constant, get a mask that contains those bits
8379 that are not copies of the sign bit. We then have two cases: If
8380 MASK only includes those bits, this can be a logical shift, which may
8381 allow simplifications. If MASK is a single-bit field not within
8382 those bits, we are requesting a copy of the sign bit and hence can
8383 shift the sign bit to the appropriate location. */
8385 if (CONST_INT_P (XEXP (x, 1)) && INTVAL (XEXP (x, 1)) >= 0
8386 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT)
8390 /* If the considered data is wider than HOST_WIDE_INT, we can't
8391 represent a mask for all its bits in a single scalar.
8392 But we only care about the lower bits, so calculate these. */
8394 if (GET_MODE_BITSIZE (GET_MODE (x)) > HOST_BITS_PER_WIDE_INT)
8396 nonzero = ~(unsigned HOST_WIDE_INT) 0;
8398 /* GET_MODE_BITSIZE (GET_MODE (x)) - INTVAL (XEXP (x, 1))
8399 is the number of bits a full-width mask would have set.
8400 We need only shift if these are fewer than nonzero can
8401 hold. If not, we must keep all bits set in nonzero. */
8403 if (GET_MODE_BITSIZE (GET_MODE (x)) - INTVAL (XEXP (x, 1))
8404 < HOST_BITS_PER_WIDE_INT)
8405 nonzero >>= INTVAL (XEXP (x, 1))
8406 + HOST_BITS_PER_WIDE_INT
8407 - GET_MODE_BITSIZE (GET_MODE (x)) ;
8411 nonzero = GET_MODE_MASK (GET_MODE (x));
8412 nonzero >>= INTVAL (XEXP (x, 1));
8415 if ((mask & ~nonzero) == 0)
8417 x = simplify_shift_const (NULL_RTX, LSHIFTRT, GET_MODE (x),
8418 XEXP (x, 0), INTVAL (XEXP (x, 1)));
8419 if (GET_CODE (x) != ASHIFTRT)
8420 return force_to_mode (x, mode, mask, next_select);
8423 else if ((i = exact_log2 (mask)) >= 0)
8425 x = simplify_shift_const
8426 (NULL_RTX, LSHIFTRT, GET_MODE (x), XEXP (x, 0),
8427 GET_MODE_BITSIZE (GET_MODE (x)) - 1 - i);
8429 if (GET_CODE (x) != ASHIFTRT)
8430 return force_to_mode (x, mode, mask, next_select);
8434 /* If MASK is 1, convert this to an LSHIFTRT. This can be done
8435 even if the shift count isn't a constant. */
8437 x = simplify_gen_binary (LSHIFTRT, GET_MODE (x),
8438 XEXP (x, 0), XEXP (x, 1));
8442 /* If this is a zero- or sign-extension operation that just affects bits
8443 we don't care about, remove it. Be sure the call above returned
8444 something that is still a shift. */
8446 if ((GET_CODE (x) == LSHIFTRT || GET_CODE (x) == ASHIFTRT)
8447 && CONST_INT_P (XEXP (x, 1))
8448 && INTVAL (XEXP (x, 1)) >= 0
8449 && (INTVAL (XEXP (x, 1))
8450 <= GET_MODE_BITSIZE (GET_MODE (x)) - (floor_log2 (mask) + 1))
8451 && GET_CODE (XEXP (x, 0)) == ASHIFT
8452 && XEXP (XEXP (x, 0), 1) == XEXP (x, 1))
8453 return force_to_mode (XEXP (XEXP (x, 0), 0), mode, mask,
8460 /* If the shift count is constant and we can do computations
8461 in the mode of X, compute where the bits we care about are.
8462 Otherwise, we can't do anything. Don't change the mode of
8463 the shift or propagate MODE into the shift, though. */
8464 if (CONST_INT_P (XEXP (x, 1))
8465 && INTVAL (XEXP (x, 1)) >= 0)
8467 temp = simplify_binary_operation (code == ROTATE ? ROTATERT : ROTATE,
8468 GET_MODE (x), GEN_INT (mask),
8470 if (temp && CONST_INT_P (temp))
8472 force_to_mode (XEXP (x, 0), GET_MODE (x),
8473 INTVAL (temp), next_select));
8478 /* If we just want the low-order bit, the NEG isn't needed since it
8479 won't change the low-order bit. */
8481 return force_to_mode (XEXP (x, 0), mode, mask, just_select);
8483 /* We need any bits less significant than the most significant bit in
8484 MASK since carries from those bits will affect the bits we are
8490 /* (not FOO) is (xor FOO CONST), so if FOO is an LSHIFTRT, we can do the
8491 same as the XOR case above. Ensure that the constant we form is not
8492 wider than the mode of X. */
8494 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
8495 && CONST_INT_P (XEXP (XEXP (x, 0), 1))
8496 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
8497 && (INTVAL (XEXP (XEXP (x, 0), 1)) + floor_log2 (mask)
8498 < GET_MODE_BITSIZE (GET_MODE (x)))
8499 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT)
8501 temp = gen_int_mode (mask << INTVAL (XEXP (XEXP (x, 0), 1)),
8503 temp = simplify_gen_binary (XOR, GET_MODE (x),
8504 XEXP (XEXP (x, 0), 0), temp);
8505 x = simplify_gen_binary (LSHIFTRT, GET_MODE (x),
8506 temp, XEXP (XEXP (x, 0), 1));
8508 return force_to_mode (x, mode, mask, next_select);
8511 /* (and (not FOO) CONST) is (not (or FOO (not CONST))), so we must
8512 use the full mask inside the NOT. */
8516 op0 = gen_lowpart_or_truncate (op_mode,
8517 force_to_mode (XEXP (x, 0), mode, mask,
8519 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0))
8520 x = simplify_gen_unary (code, op_mode, op0, op_mode);
8524 /* (and (ne FOO 0) CONST) can be (and FOO CONST) if CONST is included
8525 in STORE_FLAG_VALUE and FOO has a single bit that might be nonzero,
8526 which is equal to STORE_FLAG_VALUE. */
8527 if ((mask & ~STORE_FLAG_VALUE) == 0
8528 && XEXP (x, 1) == const0_rtx
8529 && GET_MODE (XEXP (x, 0)) == mode
8530 && exact_log2 (nonzero_bits (XEXP (x, 0), mode)) >= 0
8531 && (nonzero_bits (XEXP (x, 0), mode)
8532 == (unsigned HOST_WIDE_INT) STORE_FLAG_VALUE))
8533 return force_to_mode (XEXP (x, 0), mode, mask, next_select);
8538 /* We have no way of knowing if the IF_THEN_ELSE can itself be
8539 written in a narrower mode. We play it safe and do not do so. */
8542 gen_lowpart_or_truncate (GET_MODE (x),
8543 force_to_mode (XEXP (x, 1), mode,
8544 mask, next_select)));
8546 gen_lowpart_or_truncate (GET_MODE (x),
8547 force_to_mode (XEXP (x, 2), mode,
8548 mask, next_select)));
8555 /* Ensure we return a value of the proper mode. */
8556 return gen_lowpart_or_truncate (mode, x);
8559 /* Return nonzero if X is an expression that has one of two values depending on
8560 whether some other value is zero or nonzero. In that case, we return the
8561 value that is being tested, *PTRUE is set to the value if the rtx being
8562 returned has a nonzero value, and *PFALSE is set to the other alternative.
8564 If we return zero, we set *PTRUE and *PFALSE to X. */
8567 if_then_else_cond (rtx x, rtx *ptrue, rtx *pfalse)
8569 enum machine_mode mode = GET_MODE (x);
8570 enum rtx_code code = GET_CODE (x);
8571 rtx cond0, cond1, true0, true1, false0, false1;
8572 unsigned HOST_WIDE_INT nz;
8574 /* If we are comparing a value against zero, we are done. */
8575 if ((code == NE || code == EQ)
8576 && XEXP (x, 1) == const0_rtx)
8578 *ptrue = (code == NE) ? const_true_rtx : const0_rtx;
8579 *pfalse = (code == NE) ? const0_rtx : const_true_rtx;
8583 /* If this is a unary operation whose operand has one of two values, apply
8584 our opcode to compute those values. */
8585 else if (UNARY_P (x)
8586 && (cond0 = if_then_else_cond (XEXP (x, 0), &true0, &false0)) != 0)
8588 *ptrue = simplify_gen_unary (code, mode, true0, GET_MODE (XEXP (x, 0)));
8589 *pfalse = simplify_gen_unary (code, mode, false0,
8590 GET_MODE (XEXP (x, 0)));
8594 /* If this is a COMPARE, do nothing, since the IF_THEN_ELSE we would
8595 make can't possibly match and would suppress other optimizations. */
8596 else if (code == COMPARE)
8599 /* If this is a binary operation, see if either side has only one of two
8600 values. If either one does or if both do and they are conditional on
8601 the same value, compute the new true and false values. */
8602 else if (BINARY_P (x))
8604 cond0 = if_then_else_cond (XEXP (x, 0), &true0, &false0);
8605 cond1 = if_then_else_cond (XEXP (x, 1), &true1, &false1);
8607 if ((cond0 != 0 || cond1 != 0)
8608 && ! (cond0 != 0 && cond1 != 0 && ! rtx_equal_p (cond0, cond1)))
8610 /* If if_then_else_cond returned zero, then true/false are the
8611 same rtl. We must copy one of them to prevent invalid rtl
8614 true0 = copy_rtx (true0);
8615 else if (cond1 == 0)
8616 true1 = copy_rtx (true1);
8618 if (COMPARISON_P (x))
8620 *ptrue = simplify_gen_relational (code, mode, VOIDmode,
8622 *pfalse = simplify_gen_relational (code, mode, VOIDmode,
8627 *ptrue = simplify_gen_binary (code, mode, true0, true1);
8628 *pfalse = simplify_gen_binary (code, mode, false0, false1);
8631 return cond0 ? cond0 : cond1;
8634 /* See if we have PLUS, IOR, XOR, MINUS or UMAX, where one of the
8635 operands is zero when the other is nonzero, and vice-versa,
8636 and STORE_FLAG_VALUE is 1 or -1. */
8638 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
8639 && (code == PLUS || code == IOR || code == XOR || code == MINUS
8641 && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT)
8643 rtx op0 = XEXP (XEXP (x, 0), 1);
8644 rtx op1 = XEXP (XEXP (x, 1), 1);
8646 cond0 = XEXP (XEXP (x, 0), 0);
8647 cond1 = XEXP (XEXP (x, 1), 0);
8649 if (COMPARISON_P (cond0)
8650 && COMPARISON_P (cond1)
8651 && ((GET_CODE (cond0) == reversed_comparison_code (cond1, NULL)
8652 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0))
8653 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1)))
8654 || ((swap_condition (GET_CODE (cond0))
8655 == reversed_comparison_code (cond1, NULL))
8656 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1))
8657 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0))))
8658 && ! side_effects_p (x))
8660 *ptrue = simplify_gen_binary (MULT, mode, op0, const_true_rtx);
8661 *pfalse = simplify_gen_binary (MULT, mode,
8663 ? simplify_gen_unary (NEG, mode,
8671 /* Similarly for MULT, AND and UMIN, except that for these the result
8673 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
8674 && (code == MULT || code == AND || code == UMIN)
8675 && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT)
8677 cond0 = XEXP (XEXP (x, 0), 0);
8678 cond1 = XEXP (XEXP (x, 1), 0);
8680 if (COMPARISON_P (cond0)
8681 && COMPARISON_P (cond1)
8682 && ((GET_CODE (cond0) == reversed_comparison_code (cond1, NULL)
8683 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0))
8684 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1)))
8685 || ((swap_condition (GET_CODE (cond0))
8686 == reversed_comparison_code (cond1, NULL))
8687 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1))
8688 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0))))
8689 && ! side_effects_p (x))
8691 *ptrue = *pfalse = const0_rtx;
8697 else if (code == IF_THEN_ELSE)
8699 /* If we have IF_THEN_ELSE already, extract the condition and
8700 canonicalize it if it is NE or EQ. */
8701 cond0 = XEXP (x, 0);
8702 *ptrue = XEXP (x, 1), *pfalse = XEXP (x, 2);
8703 if (GET_CODE (cond0) == NE && XEXP (cond0, 1) == const0_rtx)
8704 return XEXP (cond0, 0);
8705 else if (GET_CODE (cond0) == EQ && XEXP (cond0, 1) == const0_rtx)
8707 *ptrue = XEXP (x, 2), *pfalse = XEXP (x, 1);
8708 return XEXP (cond0, 0);
8714 /* If X is a SUBREG, we can narrow both the true and false values
8715 if the inner expression, if there is a condition. */
8716 else if (code == SUBREG
8717 && 0 != (cond0 = if_then_else_cond (SUBREG_REG (x),
8720 true0 = simplify_gen_subreg (mode, true0,
8721 GET_MODE (SUBREG_REG (x)), SUBREG_BYTE (x));
8722 false0 = simplify_gen_subreg (mode, false0,
8723 GET_MODE (SUBREG_REG (x)), SUBREG_BYTE (x));
8724 if (true0 && false0)
8732 /* If X is a constant, this isn't special and will cause confusions
8733 if we treat it as such. Likewise if it is equivalent to a constant. */
8734 else if (CONSTANT_P (x)
8735 || ((cond0 = get_last_value (x)) != 0 && CONSTANT_P (cond0)))
8738 /* If we're in BImode, canonicalize on 0 and STORE_FLAG_VALUE, as that
8739 will be least confusing to the rest of the compiler. */
8740 else if (mode == BImode)
8742 *ptrue = GEN_INT (STORE_FLAG_VALUE), *pfalse = const0_rtx;
8746 /* If X is known to be either 0 or -1, those are the true and
8747 false values when testing X. */
8748 else if (x == constm1_rtx || x == const0_rtx
8749 || (mode != VOIDmode
8750 && num_sign_bit_copies (x, mode) == GET_MODE_BITSIZE (mode)))
8752 *ptrue = constm1_rtx, *pfalse = const0_rtx;
8756 /* Likewise for 0 or a single bit. */
8757 else if (SCALAR_INT_MODE_P (mode)
8758 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
8759 && exact_log2 (nz = nonzero_bits (x, mode)) >= 0)
8761 *ptrue = gen_int_mode (nz, mode), *pfalse = const0_rtx;
8765 /* Otherwise fail; show no condition with true and false values the same. */
8766 *ptrue = *pfalse = x;
8770 /* Return the value of expression X given the fact that condition COND
8771 is known to be true when applied to REG as its first operand and VAL
8772 as its second. X is known to not be shared and so can be modified in
8775 We only handle the simplest cases, and specifically those cases that
8776 arise with IF_THEN_ELSE expressions. */
8779 known_cond (rtx x, enum rtx_code cond, rtx reg, rtx val)
8781 enum rtx_code code = GET_CODE (x);
8786 if (side_effects_p (x))
8789 /* If either operand of the condition is a floating point value,
8790 then we have to avoid collapsing an EQ comparison. */
8792 && rtx_equal_p (x, reg)
8793 && ! FLOAT_MODE_P (GET_MODE (x))
8794 && ! FLOAT_MODE_P (GET_MODE (val)))
8797 if (cond == UNEQ && rtx_equal_p (x, reg))
8800 /* If X is (abs REG) and we know something about REG's relationship
8801 with zero, we may be able to simplify this. */
8803 if (code == ABS && rtx_equal_p (XEXP (x, 0), reg) && val == const0_rtx)
8806 case GE: case GT: case EQ:
8809 return simplify_gen_unary (NEG, GET_MODE (XEXP (x, 0)),
8811 GET_MODE (XEXP (x, 0)));
8816 /* The only other cases we handle are MIN, MAX, and comparisons if the
8817 operands are the same as REG and VAL. */
8819 else if (COMPARISON_P (x) || COMMUTATIVE_ARITH_P (x))
8821 if (rtx_equal_p (XEXP (x, 0), val))
8822 cond = swap_condition (cond), temp = val, val = reg, reg = temp;
8824 if (rtx_equal_p (XEXP (x, 0), reg) && rtx_equal_p (XEXP (x, 1), val))
8826 if (COMPARISON_P (x))
8828 if (comparison_dominates_p (cond, code))
8829 return const_true_rtx;
8831 code = reversed_comparison_code (x, NULL);
8833 && comparison_dominates_p (cond, code))
8838 else if (code == SMAX || code == SMIN
8839 || code == UMIN || code == UMAX)
8841 int unsignedp = (code == UMIN || code == UMAX);
8843 /* Do not reverse the condition when it is NE or EQ.
8844 This is because we cannot conclude anything about
8845 the value of 'SMAX (x, y)' when x is not equal to y,
8846 but we can when x equals y. */
8847 if ((code == SMAX || code == UMAX)
8848 && ! (cond == EQ || cond == NE))
8849 cond = reverse_condition (cond);
8854 return unsignedp ? x : XEXP (x, 1);
8856 return unsignedp ? x : XEXP (x, 0);
8858 return unsignedp ? XEXP (x, 1) : x;
8860 return unsignedp ? XEXP (x, 0) : x;
8867 else if (code == SUBREG)
8869 enum machine_mode inner_mode = GET_MODE (SUBREG_REG (x));
8870 rtx new_rtx, r = known_cond (SUBREG_REG (x), cond, reg, val);
8872 if (SUBREG_REG (x) != r)
8874 /* We must simplify subreg here, before we lose track of the
8875 original inner_mode. */
8876 new_rtx = simplify_subreg (GET_MODE (x), r,
8877 inner_mode, SUBREG_BYTE (x));
8881 SUBST (SUBREG_REG (x), r);
8886 /* We don't have to handle SIGN_EXTEND here, because even in the
8887 case of replacing something with a modeless CONST_INT, a
8888 CONST_INT is already (supposed to be) a valid sign extension for
8889 its narrower mode, which implies it's already properly
8890 sign-extended for the wider mode. Now, for ZERO_EXTEND, the
8891 story is different. */
8892 else if (code == ZERO_EXTEND)
8894 enum machine_mode inner_mode = GET_MODE (XEXP (x, 0));
8895 rtx new_rtx, r = known_cond (XEXP (x, 0), cond, reg, val);
8897 if (XEXP (x, 0) != r)
8899 /* We must simplify the zero_extend here, before we lose
8900 track of the original inner_mode. */
8901 new_rtx = simplify_unary_operation (ZERO_EXTEND, GET_MODE (x),
8906 SUBST (XEXP (x, 0), r);
8912 fmt = GET_RTX_FORMAT (code);
8913 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
8916 SUBST (XEXP (x, i), known_cond (XEXP (x, i), cond, reg, val));
8917 else if (fmt[i] == 'E')
8918 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
8919 SUBST (XVECEXP (x, i, j), known_cond (XVECEXP (x, i, j),
8926 /* See if X and Y are equal for the purposes of seeing if we can rewrite an
8927 assignment as a field assignment. */
8930 rtx_equal_for_field_assignment_p (rtx x, rtx y)
8932 if (x == y || rtx_equal_p (x, y))
8935 if (x == 0 || y == 0 || GET_MODE (x) != GET_MODE (y))
8938 /* Check for a paradoxical SUBREG of a MEM compared with the MEM.
8939 Note that all SUBREGs of MEM are paradoxical; otherwise they
8940 would have been rewritten. */
8941 if (MEM_P (x) && GET_CODE (y) == SUBREG
8942 && MEM_P (SUBREG_REG (y))
8943 && rtx_equal_p (SUBREG_REG (y),
8944 gen_lowpart (GET_MODE (SUBREG_REG (y)), x)))
8947 if (MEM_P (y) && GET_CODE (x) == SUBREG
8948 && MEM_P (SUBREG_REG (x))
8949 && rtx_equal_p (SUBREG_REG (x),
8950 gen_lowpart (GET_MODE (SUBREG_REG (x)), y)))
8953 /* We used to see if get_last_value of X and Y were the same but that's
8954 not correct. In one direction, we'll cause the assignment to have
8955 the wrong destination and in the case, we'll import a register into this
8956 insn that might have already have been dead. So fail if none of the
8957 above cases are true. */
8961 /* See if X, a SET operation, can be rewritten as a bit-field assignment.
8962 Return that assignment if so.
8964 We only handle the most common cases. */
8967 make_field_assignment (rtx x)
8969 rtx dest = SET_DEST (x);
8970 rtx src = SET_SRC (x);
8975 unsigned HOST_WIDE_INT len;
8977 enum machine_mode mode;
8979 /* If SRC was (and (not (ashift (const_int 1) POS)) DEST), this is
8980 a clear of a one-bit field. We will have changed it to
8981 (and (rotate (const_int -2) POS) DEST), so check for that. Also check
8984 if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == ROTATE
8985 && CONST_INT_P (XEXP (XEXP (src, 0), 0))
8986 && INTVAL (XEXP (XEXP (src, 0), 0)) == -2
8987 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
8989 assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1),
8992 return gen_rtx_SET (VOIDmode, assign, const0_rtx);
8996 if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == SUBREG
8997 && subreg_lowpart_p (XEXP (src, 0))
8998 && (GET_MODE_SIZE (GET_MODE (XEXP (src, 0)))
8999 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (src, 0)))))
9000 && GET_CODE (SUBREG_REG (XEXP (src, 0))) == ROTATE
9001 && CONST_INT_P (XEXP (SUBREG_REG (XEXP (src, 0)), 0))
9002 && INTVAL (XEXP (SUBREG_REG (XEXP (src, 0)), 0)) == -2
9003 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
9005 assign = make_extraction (VOIDmode, dest, 0,
9006 XEXP (SUBREG_REG (XEXP (src, 0)), 1),
9009 return gen_rtx_SET (VOIDmode, assign, const0_rtx);
9013 /* If SRC is (ior (ashift (const_int 1) POS) DEST), this is a set of a
9015 if (GET_CODE (src) == IOR && GET_CODE (XEXP (src, 0)) == ASHIFT
9016 && XEXP (XEXP (src, 0), 0) == const1_rtx
9017 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
9019 assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1),
9022 return gen_rtx_SET (VOIDmode, assign, const1_rtx);
9026 /* If DEST is already a field assignment, i.e. ZERO_EXTRACT, and the
9027 SRC is an AND with all bits of that field set, then we can discard
9029 if (GET_CODE (dest) == ZERO_EXTRACT
9030 && CONST_INT_P (XEXP (dest, 1))
9031 && GET_CODE (src) == AND
9032 && CONST_INT_P (XEXP (src, 1)))
9034 HOST_WIDE_INT width = INTVAL (XEXP (dest, 1));
9035 unsigned HOST_WIDE_INT and_mask = INTVAL (XEXP (src, 1));
9036 unsigned HOST_WIDE_INT ze_mask;
9038 if (width >= HOST_BITS_PER_WIDE_INT)
9041 ze_mask = ((unsigned HOST_WIDE_INT)1 << width) - 1;
9043 /* Complete overlap. We can remove the source AND. */
9044 if ((and_mask & ze_mask) == ze_mask)
9045 return gen_rtx_SET (VOIDmode, dest, XEXP (src, 0));
9047 /* Partial overlap. We can reduce the source AND. */
9048 if ((and_mask & ze_mask) != and_mask)
9050 mode = GET_MODE (src);
9051 src = gen_rtx_AND (mode, XEXP (src, 0),
9052 gen_int_mode (and_mask & ze_mask, mode));
9053 return gen_rtx_SET (VOIDmode, dest, src);
9057 /* The other case we handle is assignments into a constant-position
9058 field. They look like (ior/xor (and DEST C1) OTHER). If C1 represents
9059 a mask that has all one bits except for a group of zero bits and
9060 OTHER is known to have zeros where C1 has ones, this is such an
9061 assignment. Compute the position and length from C1. Shift OTHER
9062 to the appropriate position, force it to the required mode, and
9063 make the extraction. Check for the AND in both operands. */
9065 if (GET_CODE (src) != IOR && GET_CODE (src) != XOR)
9068 rhs = expand_compound_operation (XEXP (src, 0));
9069 lhs = expand_compound_operation (XEXP (src, 1));
9071 if (GET_CODE (rhs) == AND
9072 && CONST_INT_P (XEXP (rhs, 1))
9073 && rtx_equal_for_field_assignment_p (XEXP (rhs, 0), dest))
9074 c1 = INTVAL (XEXP (rhs, 1)), other = lhs;
9075 else if (GET_CODE (lhs) == AND
9076 && CONST_INT_P (XEXP (lhs, 1))
9077 && rtx_equal_for_field_assignment_p (XEXP (lhs, 0), dest))
9078 c1 = INTVAL (XEXP (lhs, 1)), other = rhs;
9082 pos = get_pos_from_mask ((~c1) & GET_MODE_MASK (GET_MODE (dest)), &len);
9083 if (pos < 0 || pos + len > GET_MODE_BITSIZE (GET_MODE (dest))
9084 || GET_MODE_BITSIZE (GET_MODE (dest)) > HOST_BITS_PER_WIDE_INT
9085 || (c1 & nonzero_bits (other, GET_MODE (dest))) != 0)
9088 assign = make_extraction (VOIDmode, dest, pos, NULL_RTX, len, 1, 1, 0);
9092 /* The mode to use for the source is the mode of the assignment, or of
9093 what is inside a possible STRICT_LOW_PART. */
9094 mode = (GET_CODE (assign) == STRICT_LOW_PART
9095 ? GET_MODE (XEXP (assign, 0)) : GET_MODE (assign));
9097 /* Shift OTHER right POS places and make it the source, restricting it
9098 to the proper length and mode. */
9100 src = canon_reg_for_combine (simplify_shift_const (NULL_RTX, LSHIFTRT,
9104 src = force_to_mode (src, mode,
9105 GET_MODE_BITSIZE (mode) >= HOST_BITS_PER_WIDE_INT
9106 ? ~(unsigned HOST_WIDE_INT) 0
9107 : ((unsigned HOST_WIDE_INT) 1 << len) - 1,
9110 /* If SRC is masked by an AND that does not make a difference in
9111 the value being stored, strip it. */
9112 if (GET_CODE (assign) == ZERO_EXTRACT
9113 && CONST_INT_P (XEXP (assign, 1))
9114 && INTVAL (XEXP (assign, 1)) < HOST_BITS_PER_WIDE_INT
9115 && GET_CODE (src) == AND
9116 && CONST_INT_P (XEXP (src, 1))
9117 && UINTVAL (XEXP (src, 1))
9118 == ((unsigned HOST_WIDE_INT) 1 << INTVAL (XEXP (assign, 1))) - 1)
9119 src = XEXP (src, 0);
9121 return gen_rtx_SET (VOIDmode, assign, src);
9124 /* See if X is of the form (+ (* a c) (* b c)) and convert to (* (+ a b) c)
9128 apply_distributive_law (rtx x)
9130 enum rtx_code code = GET_CODE (x);
9131 enum rtx_code inner_code;
9132 rtx lhs, rhs, other;
9135 /* Distributivity is not true for floating point as it can change the
9136 value. So we don't do it unless -funsafe-math-optimizations. */
9137 if (FLOAT_MODE_P (GET_MODE (x))
9138 && ! flag_unsafe_math_optimizations)
9141 /* The outer operation can only be one of the following: */
9142 if (code != IOR && code != AND && code != XOR
9143 && code != PLUS && code != MINUS)
9149 /* If either operand is a primitive we can't do anything, so get out
9151 if (OBJECT_P (lhs) || OBJECT_P (rhs))
9154 lhs = expand_compound_operation (lhs);
9155 rhs = expand_compound_operation (rhs);
9156 inner_code = GET_CODE (lhs);
9157 if (inner_code != GET_CODE (rhs))
9160 /* See if the inner and outer operations distribute. */
9167 /* These all distribute except over PLUS. */
9168 if (code == PLUS || code == MINUS)
9173 if (code != PLUS && code != MINUS)
9178 /* This is also a multiply, so it distributes over everything. */
9182 /* Non-paradoxical SUBREGs distributes over all operations,
9183 provided the inner modes and byte offsets are the same, this
9184 is an extraction of a low-order part, we don't convert an fp
9185 operation to int or vice versa, this is not a vector mode,
9186 and we would not be converting a single-word operation into a
9187 multi-word operation. The latter test is not required, but
9188 it prevents generating unneeded multi-word operations. Some
9189 of the previous tests are redundant given the latter test,
9190 but are retained because they are required for correctness.
9192 We produce the result slightly differently in this case. */
9194 if (GET_MODE (SUBREG_REG (lhs)) != GET_MODE (SUBREG_REG (rhs))
9195 || SUBREG_BYTE (lhs) != SUBREG_BYTE (rhs)
9196 || ! subreg_lowpart_p (lhs)
9197 || (GET_MODE_CLASS (GET_MODE (lhs))
9198 != GET_MODE_CLASS (GET_MODE (SUBREG_REG (lhs))))
9199 || (GET_MODE_SIZE (GET_MODE (lhs))
9200 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs))))
9201 || VECTOR_MODE_P (GET_MODE (lhs))
9202 || GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs))) > UNITS_PER_WORD
9203 /* Result might need to be truncated. Don't change mode if
9204 explicit truncation is needed. */
9205 || !TRULY_NOOP_TRUNCATION
9206 (GET_MODE_BITSIZE (GET_MODE (x)),
9207 GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (lhs)))))
9210 tem = simplify_gen_binary (code, GET_MODE (SUBREG_REG (lhs)),
9211 SUBREG_REG (lhs), SUBREG_REG (rhs));
9212 return gen_lowpart (GET_MODE (x), tem);
9218 /* Set LHS and RHS to the inner operands (A and B in the example
9219 above) and set OTHER to the common operand (C in the example).
9220 There is only one way to do this unless the inner operation is
9222 if (COMMUTATIVE_ARITH_P (lhs)
9223 && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 0)))
9224 other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 1);
9225 else if (COMMUTATIVE_ARITH_P (lhs)
9226 && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 1)))
9227 other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 0);
9228 else if (COMMUTATIVE_ARITH_P (lhs)
9229 && rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 0)))
9230 other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 1);
9231 else if (rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 1)))
9232 other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 0);
9236 /* Form the new inner operation, seeing if it simplifies first. */
9237 tem = simplify_gen_binary (code, GET_MODE (x), lhs, rhs);
9239 /* There is one exception to the general way of distributing:
9240 (a | c) ^ (b | c) -> (a ^ b) & ~c */
9241 if (code == XOR && inner_code == IOR)
9244 other = simplify_gen_unary (NOT, GET_MODE (x), other, GET_MODE (x));
9247 /* We may be able to continuing distributing the result, so call
9248 ourselves recursively on the inner operation before forming the
9249 outer operation, which we return. */
9250 return simplify_gen_binary (inner_code, GET_MODE (x),
9251 apply_distributive_law (tem), other);
9254 /* See if X is of the form (* (+ A B) C), and if so convert to
9255 (+ (* A C) (* B C)) and try to simplify.
9257 Most of the time, this results in no change. However, if some of
9258 the operands are the same or inverses of each other, simplifications
9261 For example, (and (ior A B) (not B)) can occur as the result of
9262 expanding a bit field assignment. When we apply the distributive
9263 law to this, we get (ior (and (A (not B))) (and (B (not B)))),
9264 which then simplifies to (and (A (not B))).
9266 Note that no checks happen on the validity of applying the inverse
9267 distributive law. This is pointless since we can do it in the
9268 few places where this routine is called.
9270 N is the index of the term that is decomposed (the arithmetic operation,
9271 i.e. (+ A B) in the first example above). !N is the index of the term that
9272 is distributed, i.e. of C in the first example above. */
9274 distribute_and_simplify_rtx (rtx x, int n)
9276 enum machine_mode mode;
9277 enum rtx_code outer_code, inner_code;
9278 rtx decomposed, distributed, inner_op0, inner_op1, new_op0, new_op1, tmp;
9280 /* Distributivity is not true for floating point as it can change the
9281 value. So we don't do it unless -funsafe-math-optimizations. */
9282 if (FLOAT_MODE_P (GET_MODE (x))
9283 && ! flag_unsafe_math_optimizations)
9286 decomposed = XEXP (x, n);
9287 if (!ARITHMETIC_P (decomposed))
9290 mode = GET_MODE (x);
9291 outer_code = GET_CODE (x);
9292 distributed = XEXP (x, !n);
9294 inner_code = GET_CODE (decomposed);
9295 inner_op0 = XEXP (decomposed, 0);
9296 inner_op1 = XEXP (decomposed, 1);
9298 /* Special case (and (xor B C) (not A)), which is equivalent to
9299 (xor (ior A B) (ior A C)) */
9300 if (outer_code == AND && inner_code == XOR && GET_CODE (distributed) == NOT)
9302 distributed = XEXP (distributed, 0);
9308 /* Distribute the second term. */
9309 new_op0 = simplify_gen_binary (outer_code, mode, inner_op0, distributed);
9310 new_op1 = simplify_gen_binary (outer_code, mode, inner_op1, distributed);
9314 /* Distribute the first term. */
9315 new_op0 = simplify_gen_binary (outer_code, mode, distributed, inner_op0);
9316 new_op1 = simplify_gen_binary (outer_code, mode, distributed, inner_op1);
9319 tmp = apply_distributive_law (simplify_gen_binary (inner_code, mode,
9321 if (GET_CODE (tmp) != outer_code
9322 && rtx_cost (tmp, SET, optimize_this_for_speed_p)
9323 < rtx_cost (x, SET, optimize_this_for_speed_p))
9329 /* Simplify a logical `and' of VAROP with the constant CONSTOP, to be done
9330 in MODE. Return an equivalent form, if different from (and VAROP
9331 (const_int CONSTOP)). Otherwise, return NULL_RTX. */
9334 simplify_and_const_int_1 (enum machine_mode mode, rtx varop,
9335 unsigned HOST_WIDE_INT constop)
9337 unsigned HOST_WIDE_INT nonzero;
9338 unsigned HOST_WIDE_INT orig_constop;
9343 orig_constop = constop;
9344 if (GET_CODE (varop) == CLOBBER)
9347 /* Simplify VAROP knowing that we will be only looking at some of the
9350 Note by passing in CONSTOP, we guarantee that the bits not set in
9351 CONSTOP are not significant and will never be examined. We must
9352 ensure that is the case by explicitly masking out those bits
9353 before returning. */
9354 varop = force_to_mode (varop, mode, constop, 0);
9356 /* If VAROP is a CLOBBER, we will fail so return it. */
9357 if (GET_CODE (varop) == CLOBBER)
9360 /* If VAROP is a CONST_INT, then we need to apply the mask in CONSTOP
9361 to VAROP and return the new constant. */
9362 if (CONST_INT_P (varop))
9363 return gen_int_mode (INTVAL (varop) & constop, mode);
9365 /* See what bits may be nonzero in VAROP. Unlike the general case of
9366 a call to nonzero_bits, here we don't care about bits outside
9369 nonzero = nonzero_bits (varop, mode) & GET_MODE_MASK (mode);
9371 /* Turn off all bits in the constant that are known to already be zero.
9372 Thus, if the AND isn't needed at all, we will have CONSTOP == NONZERO_BITS
9373 which is tested below. */
9377 /* If we don't have any bits left, return zero. */
9381 /* If VAROP is a NEG of something known to be zero or 1 and CONSTOP is
9382 a power of two, we can replace this with an ASHIFT. */
9383 if (GET_CODE (varop) == NEG && nonzero_bits (XEXP (varop, 0), mode) == 1
9384 && (i = exact_log2 (constop)) >= 0)
9385 return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (varop, 0), i);
9387 /* If VAROP is an IOR or XOR, apply the AND to both branches of the IOR
9388 or XOR, then try to apply the distributive law. This may eliminate
9389 operations if either branch can be simplified because of the AND.
9390 It may also make some cases more complex, but those cases probably
9391 won't match a pattern either with or without this. */
9393 if (GET_CODE (varop) == IOR || GET_CODE (varop) == XOR)
9397 apply_distributive_law
9398 (simplify_gen_binary (GET_CODE (varop), GET_MODE (varop),
9399 simplify_and_const_int (NULL_RTX,
9403 simplify_and_const_int (NULL_RTX,
9408 /* If VAROP is PLUS, and the constant is a mask of low bits, distribute
9409 the AND and see if one of the operands simplifies to zero. If so, we
9410 may eliminate it. */
9412 if (GET_CODE (varop) == PLUS
9413 && exact_log2 (constop + 1) >= 0)
9417 o0 = simplify_and_const_int (NULL_RTX, mode, XEXP (varop, 0), constop);
9418 o1 = simplify_and_const_int (NULL_RTX, mode, XEXP (varop, 1), constop);
9419 if (o0 == const0_rtx)
9421 if (o1 == const0_rtx)
9425 /* Make a SUBREG if necessary. If we can't make it, fail. */
9426 varop = gen_lowpart (mode, varop);
9427 if (varop == NULL_RTX || GET_CODE (varop) == CLOBBER)
9430 /* If we are only masking insignificant bits, return VAROP. */
9431 if (constop == nonzero)
9434 if (varop == orig_varop && constop == orig_constop)
9437 /* Otherwise, return an AND. */
9438 return simplify_gen_binary (AND, mode, varop, gen_int_mode (constop, mode));
9442 /* We have X, a logical `and' of VAROP with the constant CONSTOP, to be done
9445 Return an equivalent form, if different from X. Otherwise, return X. If
9446 X is zero, we are to always construct the equivalent form. */
9449 simplify_and_const_int (rtx x, enum machine_mode mode, rtx varop,
9450 unsigned HOST_WIDE_INT constop)
9452 rtx tem = simplify_and_const_int_1 (mode, varop, constop);
9457 x = simplify_gen_binary (AND, GET_MODE (varop), varop,
9458 gen_int_mode (constop, mode));
9459 if (GET_MODE (x) != mode)
9460 x = gen_lowpart (mode, x);
9464 /* Given a REG, X, compute which bits in X can be nonzero.
9465 We don't care about bits outside of those defined in MODE.
9467 For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is
9468 a shift, AND, or zero_extract, we can do better. */
9471 reg_nonzero_bits_for_combine (const_rtx x, enum machine_mode mode,
9472 const_rtx known_x ATTRIBUTE_UNUSED,
9473 enum machine_mode known_mode ATTRIBUTE_UNUSED,
9474 unsigned HOST_WIDE_INT known_ret ATTRIBUTE_UNUSED,
9475 unsigned HOST_WIDE_INT *nonzero)
9480 /* If X is a register whose nonzero bits value is current, use it.
9481 Otherwise, if X is a register whose value we can find, use that
9482 value. Otherwise, use the previously-computed global nonzero bits
9483 for this register. */
9485 rsp = VEC_index (reg_stat_type, reg_stat, REGNO (x));
9486 if (rsp->last_set_value != 0
9487 && (rsp->last_set_mode == mode
9488 || (GET_MODE_CLASS (rsp->last_set_mode) == MODE_INT
9489 && GET_MODE_CLASS (mode) == MODE_INT))
9490 && ((rsp->last_set_label >= label_tick_ebb_start
9491 && rsp->last_set_label < label_tick)
9492 || (rsp->last_set_label == label_tick
9493 && DF_INSN_LUID (rsp->last_set) < subst_low_luid)
9494 || (REGNO (x) >= FIRST_PSEUDO_REGISTER
9495 && REG_N_SETS (REGNO (x)) == 1
9497 (DF_LR_IN (ENTRY_BLOCK_PTR->next_bb), REGNO (x)))))
9499 *nonzero &= rsp->last_set_nonzero_bits;
9503 tem = get_last_value (x);
9507 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
9508 /* If X is narrower than MODE and TEM is a non-negative
9509 constant that would appear negative in the mode of X,
9510 sign-extend it for use in reg_nonzero_bits because some
9511 machines (maybe most) will actually do the sign-extension
9512 and this is the conservative approach.
9514 ??? For 2.5, try to tighten up the MD files in this regard
9515 instead of this kludge. */
9517 if (GET_MODE_BITSIZE (GET_MODE (x)) < GET_MODE_BITSIZE (mode)
9518 && CONST_INT_P (tem)
9520 && 0 != (UINTVAL (tem)
9521 & ((unsigned HOST_WIDE_INT) 1
9522 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
9523 tem = GEN_INT (UINTVAL (tem)
9524 | ((unsigned HOST_WIDE_INT) (-1)
9525 << GET_MODE_BITSIZE (GET_MODE (x))));
9529 else if (nonzero_sign_valid && rsp->nonzero_bits)
9531 unsigned HOST_WIDE_INT mask = rsp->nonzero_bits;
9533 if (GET_MODE_BITSIZE (GET_MODE (x)) < GET_MODE_BITSIZE (mode))
9534 /* We don't know anything about the upper bits. */
9535 mask |= GET_MODE_MASK (mode) ^ GET_MODE_MASK (GET_MODE (x));
9542 /* Return the number of bits at the high-order end of X that are known to
9543 be equal to the sign bit. X will be used in mode MODE; if MODE is
9544 VOIDmode, X will be used in its own mode. The returned value will always
9545 be between 1 and the number of bits in MODE. */
9548 reg_num_sign_bit_copies_for_combine (const_rtx x, enum machine_mode mode,
9549 const_rtx known_x ATTRIBUTE_UNUSED,
9550 enum machine_mode known_mode
9552 unsigned int known_ret ATTRIBUTE_UNUSED,
9553 unsigned int *result)
9558 rsp = VEC_index (reg_stat_type, reg_stat, REGNO (x));
9559 if (rsp->last_set_value != 0
9560 && rsp->last_set_mode == mode
9561 && ((rsp->last_set_label >= label_tick_ebb_start
9562 && rsp->last_set_label < label_tick)
9563 || (rsp->last_set_label == label_tick
9564 && DF_INSN_LUID (rsp->last_set) < subst_low_luid)
9565 || (REGNO (x) >= FIRST_PSEUDO_REGISTER
9566 && REG_N_SETS (REGNO (x)) == 1
9568 (DF_LR_IN (ENTRY_BLOCK_PTR->next_bb), REGNO (x)))))
9570 *result = rsp->last_set_sign_bit_copies;
9574 tem = get_last_value (x);
9578 if (nonzero_sign_valid && rsp->sign_bit_copies != 0
9579 && GET_MODE_BITSIZE (GET_MODE (x)) == GET_MODE_BITSIZE (mode))
9580 *result = rsp->sign_bit_copies;
9585 /* Return the number of "extended" bits there are in X, when interpreted
9586 as a quantity in MODE whose signedness is indicated by UNSIGNEDP. For
9587 unsigned quantities, this is the number of high-order zero bits.
9588 For signed quantities, this is the number of copies of the sign bit
9589 minus 1. In both case, this function returns the number of "spare"
9590 bits. For example, if two quantities for which this function returns
9591 at least 1 are added, the addition is known not to overflow.
9593 This function will always return 0 unless called during combine, which
9594 implies that it must be called from a define_split. */
9597 extended_count (const_rtx x, enum machine_mode mode, int unsignedp)
9599 if (nonzero_sign_valid == 0)
9603 ? (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
9604 ? (unsigned int) (GET_MODE_BITSIZE (mode) - 1
9605 - floor_log2 (nonzero_bits (x, mode)))
9607 : num_sign_bit_copies (x, mode) - 1);
9610 /* This function is called from `simplify_shift_const' to merge two
9611 outer operations. Specifically, we have already found that we need
9612 to perform operation *POP0 with constant *PCONST0 at the outermost
9613 position. We would now like to also perform OP1 with constant CONST1
9614 (with *POP0 being done last).
9616 Return 1 if we can do the operation and update *POP0 and *PCONST0 with
9617 the resulting operation. *PCOMP_P is set to 1 if we would need to
9618 complement the innermost operand, otherwise it is unchanged.
9620 MODE is the mode in which the operation will be done. No bits outside
9621 the width of this mode matter. It is assumed that the width of this mode
9622 is smaller than or equal to HOST_BITS_PER_WIDE_INT.
9624 If *POP0 or OP1 are UNKNOWN, it means no operation is required. Only NEG, PLUS,
9625 IOR, XOR, and AND are supported. We may set *POP0 to SET if the proper
9626 result is simply *PCONST0.
9628 If the resulting operation cannot be expressed as one operation, we
9629 return 0 and do not change *POP0, *PCONST0, and *PCOMP_P. */
9632 merge_outer_ops (enum rtx_code *pop0, HOST_WIDE_INT *pconst0, enum rtx_code op1, HOST_WIDE_INT const1, enum machine_mode mode, int *pcomp_p)
9634 enum rtx_code op0 = *pop0;
9635 HOST_WIDE_INT const0 = *pconst0;
9637 const0 &= GET_MODE_MASK (mode);
9638 const1 &= GET_MODE_MASK (mode);
9640 /* If OP0 is an AND, clear unimportant bits in CONST1. */
9644 /* If OP0 or OP1 is UNKNOWN, this is easy. Similarly if they are the same or
9647 if (op1 == UNKNOWN || op0 == SET)
9650 else if (op0 == UNKNOWN)
9651 op0 = op1, const0 = const1;
9653 else if (op0 == op1)
9677 /* Otherwise, if either is a PLUS or NEG, we can't do anything. */
9678 else if (op0 == PLUS || op1 == PLUS || op0 == NEG || op1 == NEG)
9681 /* If the two constants aren't the same, we can't do anything. The
9682 remaining six cases can all be done. */
9683 else if (const0 != const1)
9691 /* (a & b) | b == b */
9693 else /* op1 == XOR */
9694 /* (a ^ b) | b == a | b */
9700 /* (a & b) ^ b == (~a) & b */
9701 op0 = AND, *pcomp_p = 1;
9702 else /* op1 == IOR */
9703 /* (a | b) ^ b == a & ~b */
9704 op0 = AND, const0 = ~const0;
9709 /* (a | b) & b == b */
9711 else /* op1 == XOR */
9712 /* (a ^ b) & b) == (~a) & b */
9719 /* Check for NO-OP cases. */
9720 const0 &= GET_MODE_MASK (mode);
9722 && (op0 == IOR || op0 == XOR || op0 == PLUS))
9724 else if (const0 == 0 && op0 == AND)
9726 else if ((unsigned HOST_WIDE_INT) const0 == GET_MODE_MASK (mode)
9732 /* ??? Slightly redundant with the above mask, but not entirely.
9733 Moving this above means we'd have to sign-extend the mode mask
9734 for the final test. */
9735 if (op0 != UNKNOWN && op0 != NEG)
9736 *pconst0 = trunc_int_for_mode (const0, mode);
9741 /* A helper to simplify_shift_const_1 to determine the mode we can perform
9742 the shift in. The original shift operation CODE is performed on OP in
9743 ORIG_MODE. Return the wider mode MODE if we can perform the operation
9744 in that mode. Return ORIG_MODE otherwise. We can also assume that the
9745 result of the shift is subject to operation OUTER_CODE with operand
9748 static enum machine_mode
9749 try_widen_shift_mode (enum rtx_code code, rtx op, int count,
9750 enum machine_mode orig_mode, enum machine_mode mode,
9751 enum rtx_code outer_code, HOST_WIDE_INT outer_const)
9753 if (orig_mode == mode)
9755 gcc_assert (GET_MODE_BITSIZE (mode) > GET_MODE_BITSIZE (orig_mode));
9757 /* In general we can't perform in wider mode for right shift and rotate. */
9761 /* We can still widen if the bits brought in from the left are identical
9762 to the sign bit of ORIG_MODE. */
9763 if (num_sign_bit_copies (op, mode)
9764 > (unsigned) (GET_MODE_BITSIZE (mode)
9765 - GET_MODE_BITSIZE (orig_mode)))
9770 /* Similarly here but with zero bits. */
9771 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
9772 && (nonzero_bits (op, mode) & ~GET_MODE_MASK (orig_mode)) == 0)
9775 /* We can also widen if the bits brought in will be masked off. This
9776 operation is performed in ORIG_MODE. */
9777 if (outer_code == AND)
9779 int care_bits = low_bitmask_len (orig_mode, outer_const);
9782 && GET_MODE_BITSIZE (orig_mode) - care_bits >= count)
9798 /* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift.
9799 The result of the shift is RESULT_MODE. Return NULL_RTX if we cannot
9800 simplify it. Otherwise, return a simplified value.
9802 The shift is normally computed in the widest mode we find in VAROP, as
9803 long as it isn't a different number of words than RESULT_MODE. Exceptions
9804 are ASHIFTRT and ROTATE, which are always done in their original mode. */
9807 simplify_shift_const_1 (enum rtx_code code, enum machine_mode result_mode,
9808 rtx varop, int orig_count)
9810 enum rtx_code orig_code = code;
9811 rtx orig_varop = varop;
9813 enum machine_mode mode = result_mode;
9814 enum machine_mode shift_mode, tmode;
9815 unsigned int mode_words
9816 = (GET_MODE_SIZE (mode) + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD;
9817 /* We form (outer_op (code varop count) (outer_const)). */
9818 enum rtx_code outer_op = UNKNOWN;
9819 HOST_WIDE_INT outer_const = 0;
9820 int complement_p = 0;
9823 /* Make sure and truncate the "natural" shift on the way in. We don't
9824 want to do this inside the loop as it makes it more difficult to
9826 if (SHIFT_COUNT_TRUNCATED)
9827 orig_count &= GET_MODE_BITSIZE (mode) - 1;
9829 /* If we were given an invalid count, don't do anything except exactly
9830 what was requested. */
9832 if (orig_count < 0 || orig_count >= (int) GET_MODE_BITSIZE (mode))
9837 /* Unless one of the branches of the `if' in this loop does a `continue',
9838 we will `break' the loop after the `if'. */
9842 /* If we have an operand of (clobber (const_int 0)), fail. */
9843 if (GET_CODE (varop) == CLOBBER)
9846 /* Convert ROTATERT to ROTATE. */
9847 if (code == ROTATERT)
9849 unsigned int bitsize = GET_MODE_BITSIZE (result_mode);;
9851 if (VECTOR_MODE_P (result_mode))
9852 count = bitsize / GET_MODE_NUNITS (result_mode) - count;
9854 count = bitsize - count;
9857 shift_mode = try_widen_shift_mode (code, varop, count, result_mode,
9858 mode, outer_op, outer_const);
9860 /* Handle cases where the count is greater than the size of the mode
9861 minus 1. For ASHIFT, use the size minus one as the count (this can
9862 occur when simplifying (lshiftrt (ashiftrt ..))). For rotates,
9863 take the count modulo the size. For other shifts, the result is
9866 Since these shifts are being produced by the compiler by combining
9867 multiple operations, each of which are defined, we know what the
9868 result is supposed to be. */
9870 if (count > (GET_MODE_BITSIZE (shift_mode) - 1))
9872 if (code == ASHIFTRT)
9873 count = GET_MODE_BITSIZE (shift_mode) - 1;
9874 else if (code == ROTATE || code == ROTATERT)
9875 count %= GET_MODE_BITSIZE (shift_mode);
9878 /* We can't simply return zero because there may be an
9886 /* If we discovered we had to complement VAROP, leave. Making a NOT
9887 here would cause an infinite loop. */
9891 /* An arithmetic right shift of a quantity known to be -1 or 0
9893 if (code == ASHIFTRT
9894 && (num_sign_bit_copies (varop, shift_mode)
9895 == GET_MODE_BITSIZE (shift_mode)))
9901 /* If we are doing an arithmetic right shift and discarding all but
9902 the sign bit copies, this is equivalent to doing a shift by the
9903 bitsize minus one. Convert it into that shift because it will often
9904 allow other simplifications. */
9906 if (code == ASHIFTRT
9907 && (count + num_sign_bit_copies (varop, shift_mode)
9908 >= GET_MODE_BITSIZE (shift_mode)))
9909 count = GET_MODE_BITSIZE (shift_mode) - 1;
9911 /* We simplify the tests below and elsewhere by converting
9912 ASHIFTRT to LSHIFTRT if we know the sign bit is clear.
9913 `make_compound_operation' will convert it to an ASHIFTRT for
9914 those machines (such as VAX) that don't have an LSHIFTRT. */
9915 if (GET_MODE_BITSIZE (shift_mode) <= HOST_BITS_PER_WIDE_INT
9917 && ((nonzero_bits (varop, shift_mode)
9918 & ((unsigned HOST_WIDE_INT) 1
9919 << (GET_MODE_BITSIZE (shift_mode) - 1))) == 0))
9922 if (((code == LSHIFTRT
9923 && GET_MODE_BITSIZE (shift_mode) <= HOST_BITS_PER_WIDE_INT
9924 && !(nonzero_bits (varop, shift_mode) >> count))
9926 && GET_MODE_BITSIZE (shift_mode) <= HOST_BITS_PER_WIDE_INT
9927 && !((nonzero_bits (varop, shift_mode) << count)
9928 & GET_MODE_MASK (shift_mode))))
9929 && !side_effects_p (varop))
9932 switch (GET_CODE (varop))
9938 new_rtx = expand_compound_operation (varop);
9939 if (new_rtx != varop)
9947 /* If we have (xshiftrt (mem ...) C) and C is MODE_WIDTH
9948 minus the width of a smaller mode, we can do this with a
9949 SIGN_EXTEND or ZERO_EXTEND from the narrower memory location. */
9950 if ((code == ASHIFTRT || code == LSHIFTRT)
9951 && ! mode_dependent_address_p (XEXP (varop, 0))
9952 && ! MEM_VOLATILE_P (varop)
9953 && (tmode = mode_for_size (GET_MODE_BITSIZE (mode) - count,
9954 MODE_INT, 1)) != BLKmode)
9956 new_rtx = adjust_address_nv (varop, tmode,
9957 BYTES_BIG_ENDIAN ? 0
9958 : count / BITS_PER_UNIT);
9960 varop = gen_rtx_fmt_e (code == ASHIFTRT ? SIGN_EXTEND
9961 : ZERO_EXTEND, mode, new_rtx);
9968 /* If VAROP is a SUBREG, strip it as long as the inner operand has
9969 the same number of words as what we've seen so far. Then store
9970 the widest mode in MODE. */
9971 if (subreg_lowpart_p (varop)
9972 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop)))
9973 > GET_MODE_SIZE (GET_MODE (varop)))
9974 && (unsigned int) ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop)))
9975 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
9977 && GET_MODE_CLASS (GET_MODE (varop)) == MODE_INT
9978 && GET_MODE_CLASS (GET_MODE (SUBREG_REG (varop))) == MODE_INT)
9980 varop = SUBREG_REG (varop);
9981 if (GET_MODE_SIZE (GET_MODE (varop)) > GET_MODE_SIZE (mode))
9982 mode = GET_MODE (varop);
9988 /* Some machines use MULT instead of ASHIFT because MULT
9989 is cheaper. But it is still better on those machines to
9990 merge two shifts into one. */
9991 if (CONST_INT_P (XEXP (varop, 1))
9992 && exact_log2 (UINTVAL (XEXP (varop, 1))) >= 0)
9995 = simplify_gen_binary (ASHIFT, GET_MODE (varop),
9997 GEN_INT (exact_log2 (
9998 UINTVAL (XEXP (varop, 1)))));
10004 /* Similar, for when divides are cheaper. */
10005 if (CONST_INT_P (XEXP (varop, 1))
10006 && exact_log2 (UINTVAL (XEXP (varop, 1))) >= 0)
10009 = simplify_gen_binary (LSHIFTRT, GET_MODE (varop),
10011 GEN_INT (exact_log2 (
10012 UINTVAL (XEXP (varop, 1)))));
10018 /* If we are extracting just the sign bit of an arithmetic
10019 right shift, that shift is not needed. However, the sign
10020 bit of a wider mode may be different from what would be
10021 interpreted as the sign bit in a narrower mode, so, if
10022 the result is narrower, don't discard the shift. */
10023 if (code == LSHIFTRT
10024 && count == (GET_MODE_BITSIZE (result_mode) - 1)
10025 && (GET_MODE_BITSIZE (result_mode)
10026 >= GET_MODE_BITSIZE (GET_MODE (varop))))
10028 varop = XEXP (varop, 0);
10032 /* ... fall through ... */
10037 /* Here we have two nested shifts. The result is usually the
10038 AND of a new shift with a mask. We compute the result below. */
10039 if (CONST_INT_P (XEXP (varop, 1))
10040 && INTVAL (XEXP (varop, 1)) >= 0
10041 && INTVAL (XEXP (varop, 1)) < GET_MODE_BITSIZE (GET_MODE (varop))
10042 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
10043 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
10044 && !VECTOR_MODE_P (result_mode))
10046 enum rtx_code first_code = GET_CODE (varop);
10047 unsigned int first_count = INTVAL (XEXP (varop, 1));
10048 unsigned HOST_WIDE_INT mask;
10051 /* We have one common special case. We can't do any merging if
10052 the inner code is an ASHIFTRT of a smaller mode. However, if
10053 we have (ashift:M1 (subreg:M1 (ashiftrt:M2 FOO C1) 0) C2)
10054 with C2 == GET_MODE_BITSIZE (M1) - GET_MODE_BITSIZE (M2),
10055 we can convert it to
10056 (ashiftrt:M1 (ashift:M1 (and:M1 (subreg:M1 FOO 0 C2) C3) C1).
10057 This simplifies certain SIGN_EXTEND operations. */
10058 if (code == ASHIFT && first_code == ASHIFTRT
10059 && count == (GET_MODE_BITSIZE (result_mode)
10060 - GET_MODE_BITSIZE (GET_MODE (varop))))
10062 /* C3 has the low-order C1 bits zero. */
10064 mask = GET_MODE_MASK (mode)
10065 & ~(((unsigned HOST_WIDE_INT) 1 << first_count) - 1);
10067 varop = simplify_and_const_int (NULL_RTX, result_mode,
10068 XEXP (varop, 0), mask);
10069 varop = simplify_shift_const (NULL_RTX, ASHIFT, result_mode,
10071 count = first_count;
10076 /* If this was (ashiftrt (ashift foo C1) C2) and FOO has more
10077 than C1 high-order bits equal to the sign bit, we can convert
10078 this to either an ASHIFT or an ASHIFTRT depending on the
10081 We cannot do this if VAROP's mode is not SHIFT_MODE. */
10083 if (code == ASHIFTRT && first_code == ASHIFT
10084 && GET_MODE (varop) == shift_mode
10085 && (num_sign_bit_copies (XEXP (varop, 0), shift_mode)
10088 varop = XEXP (varop, 0);
10089 count -= first_count;
10099 /* There are some cases we can't do. If CODE is ASHIFTRT,
10100 we can only do this if FIRST_CODE is also ASHIFTRT.
10102 We can't do the case when CODE is ROTATE and FIRST_CODE is
10105 If the mode of this shift is not the mode of the outer shift,
10106 we can't do this if either shift is a right shift or ROTATE.
10108 Finally, we can't do any of these if the mode is too wide
10109 unless the codes are the same.
10111 Handle the case where the shift codes are the same
10114 if (code == first_code)
10116 if (GET_MODE (varop) != result_mode
10117 && (code == ASHIFTRT || code == LSHIFTRT
10118 || code == ROTATE))
10121 count += first_count;
10122 varop = XEXP (varop, 0);
10126 if (code == ASHIFTRT
10127 || (code == ROTATE && first_code == ASHIFTRT)
10128 || GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT
10129 || (GET_MODE (varop) != result_mode
10130 && (first_code == ASHIFTRT || first_code == LSHIFTRT
10131 || first_code == ROTATE
10132 || code == ROTATE)))
10135 /* To compute the mask to apply after the shift, shift the
10136 nonzero bits of the inner shift the same way the
10137 outer shift will. */
10139 mask_rtx = GEN_INT (nonzero_bits (varop, GET_MODE (varop)));
10142 = simplify_const_binary_operation (code, result_mode, mask_rtx,
10145 /* Give up if we can't compute an outer operation to use. */
10147 || !CONST_INT_P (mask_rtx)
10148 || ! merge_outer_ops (&outer_op, &outer_const, AND,
10150 result_mode, &complement_p))
10153 /* If the shifts are in the same direction, we add the
10154 counts. Otherwise, we subtract them. */
10155 if ((code == ASHIFTRT || code == LSHIFTRT)
10156 == (first_code == ASHIFTRT || first_code == LSHIFTRT))
10157 count += first_count;
10159 count -= first_count;
10161 /* If COUNT is positive, the new shift is usually CODE,
10162 except for the two exceptions below, in which case it is
10163 FIRST_CODE. If the count is negative, FIRST_CODE should
10166 && ((first_code == ROTATE && code == ASHIFT)
10167 || (first_code == ASHIFTRT && code == LSHIFTRT)))
10169 else if (count < 0)
10170 code = first_code, count = -count;
10172 varop = XEXP (varop, 0);
10176 /* If we have (A << B << C) for any shift, we can convert this to
10177 (A << C << B). This wins if A is a constant. Only try this if
10178 B is not a constant. */
10180 else if (GET_CODE (varop) == code
10181 && CONST_INT_P (XEXP (varop, 0))
10182 && !CONST_INT_P (XEXP (varop, 1)))
10184 rtx new_rtx = simplify_const_binary_operation (code, mode,
10187 varop = gen_rtx_fmt_ee (code, mode, new_rtx, XEXP (varop, 1));
10194 if (VECTOR_MODE_P (mode))
10197 /* Make this fit the case below. */
10198 varop = gen_rtx_XOR (mode, XEXP (varop, 0),
10199 GEN_INT (GET_MODE_MASK (mode)));
10205 /* If we have (xshiftrt (ior (plus X (const_int -1)) X) C)
10206 with C the size of VAROP - 1 and the shift is logical if
10207 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
10208 we have an (le X 0) operation. If we have an arithmetic shift
10209 and STORE_FLAG_VALUE is 1 or we have a logical shift with
10210 STORE_FLAG_VALUE of -1, we have a (neg (le X 0)) operation. */
10212 if (GET_CODE (varop) == IOR && GET_CODE (XEXP (varop, 0)) == PLUS
10213 && XEXP (XEXP (varop, 0), 1) == constm1_rtx
10214 && (STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
10215 && (code == LSHIFTRT || code == ASHIFTRT)
10216 && count == (GET_MODE_BITSIZE (GET_MODE (varop)) - 1)
10217 && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
10220 varop = gen_rtx_LE (GET_MODE (varop), XEXP (varop, 1),
10223 if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
10224 varop = gen_rtx_NEG (GET_MODE (varop), varop);
10229 /* If we have (shift (logical)), move the logical to the outside
10230 to allow it to possibly combine with another logical and the
10231 shift to combine with another shift. This also canonicalizes to
10232 what a ZERO_EXTRACT looks like. Also, some machines have
10233 (and (shift)) insns. */
10235 if (CONST_INT_P (XEXP (varop, 1))
10236 /* We can't do this if we have (ashiftrt (xor)) and the
10237 constant has its sign bit set in shift_mode. */
10238 && !(code == ASHIFTRT && GET_CODE (varop) == XOR
10239 && 0 > trunc_int_for_mode (INTVAL (XEXP (varop, 1)),
10241 && (new_rtx = simplify_const_binary_operation (code, result_mode,
10243 GEN_INT (count))) != 0
10244 && CONST_INT_P (new_rtx)
10245 && merge_outer_ops (&outer_op, &outer_const, GET_CODE (varop),
10246 INTVAL (new_rtx), result_mode, &complement_p))
10248 varop = XEXP (varop, 0);
10252 /* If we can't do that, try to simplify the shift in each arm of the
10253 logical expression, make a new logical expression, and apply
10254 the inverse distributive law. This also can't be done
10255 for some (ashiftrt (xor)). */
10256 if (CONST_INT_P (XEXP (varop, 1))
10257 && !(code == ASHIFTRT && GET_CODE (varop) == XOR
10258 && 0 > trunc_int_for_mode (INTVAL (XEXP (varop, 1)),
10261 rtx lhs = simplify_shift_const (NULL_RTX, code, shift_mode,
10262 XEXP (varop, 0), count);
10263 rtx rhs = simplify_shift_const (NULL_RTX, code, shift_mode,
10264 XEXP (varop, 1), count);
10266 varop = simplify_gen_binary (GET_CODE (varop), shift_mode,
10268 varop = apply_distributive_law (varop);
10276 /* Convert (lshiftrt (eq FOO 0) C) to (xor FOO 1) if STORE_FLAG_VALUE
10277 says that the sign bit can be tested, FOO has mode MODE, C is
10278 GET_MODE_BITSIZE (MODE) - 1, and FOO has only its low-order bit
10279 that may be nonzero. */
10280 if (code == LSHIFTRT
10281 && XEXP (varop, 1) == const0_rtx
10282 && GET_MODE (XEXP (varop, 0)) == result_mode
10283 && count == (GET_MODE_BITSIZE (result_mode) - 1)
10284 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
10285 && STORE_FLAG_VALUE == -1
10286 && nonzero_bits (XEXP (varop, 0), result_mode) == 1
10287 && merge_outer_ops (&outer_op, &outer_const, XOR, 1, result_mode,
10290 varop = XEXP (varop, 0);
10297 /* (lshiftrt (neg A) C) where A is either 0 or 1 and C is one less
10298 than the number of bits in the mode is equivalent to A. */
10299 if (code == LSHIFTRT
10300 && count == (GET_MODE_BITSIZE (result_mode) - 1)
10301 && nonzero_bits (XEXP (varop, 0), result_mode) == 1)
10303 varop = XEXP (varop, 0);
10308 /* NEG commutes with ASHIFT since it is multiplication. Move the
10309 NEG outside to allow shifts to combine. */
10311 && merge_outer_ops (&outer_op, &outer_const, NEG, 0, result_mode,
10314 varop = XEXP (varop, 0);
10320 /* (lshiftrt (plus A -1) C) where A is either 0 or 1 and C
10321 is one less than the number of bits in the mode is
10322 equivalent to (xor A 1). */
10323 if (code == LSHIFTRT
10324 && count == (GET_MODE_BITSIZE (result_mode) - 1)
10325 && XEXP (varop, 1) == constm1_rtx
10326 && nonzero_bits (XEXP (varop, 0), result_mode) == 1
10327 && merge_outer_ops (&outer_op, &outer_const, XOR, 1, result_mode,
10331 varop = XEXP (varop, 0);
10335 /* If we have (xshiftrt (plus FOO BAR) C), and the only bits
10336 that might be nonzero in BAR are those being shifted out and those
10337 bits are known zero in FOO, we can replace the PLUS with FOO.
10338 Similarly in the other operand order. This code occurs when
10339 we are computing the size of a variable-size array. */
10341 if ((code == ASHIFTRT || code == LSHIFTRT)
10342 && count < HOST_BITS_PER_WIDE_INT
10343 && nonzero_bits (XEXP (varop, 1), result_mode) >> count == 0
10344 && (nonzero_bits (XEXP (varop, 1), result_mode)
10345 & nonzero_bits (XEXP (varop, 0), result_mode)) == 0)
10347 varop = XEXP (varop, 0);
10350 else if ((code == ASHIFTRT || code == LSHIFTRT)
10351 && count < HOST_BITS_PER_WIDE_INT
10352 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
10353 && 0 == (nonzero_bits (XEXP (varop, 0), result_mode)
10355 && 0 == (nonzero_bits (XEXP (varop, 0), result_mode)
10356 & nonzero_bits (XEXP (varop, 1),
10359 varop = XEXP (varop, 1);
10363 /* (ashift (plus foo C) N) is (plus (ashift foo N) C'). */
10365 && CONST_INT_P (XEXP (varop, 1))
10366 && (new_rtx = simplify_const_binary_operation (ASHIFT, result_mode,
10368 GEN_INT (count))) != 0
10369 && CONST_INT_P (new_rtx)
10370 && merge_outer_ops (&outer_op, &outer_const, PLUS,
10371 INTVAL (new_rtx), result_mode, &complement_p))
10373 varop = XEXP (varop, 0);
10377 /* Check for 'PLUS signbit', which is the canonical form of 'XOR
10378 signbit', and attempt to change the PLUS to an XOR and move it to
10379 the outer operation as is done above in the AND/IOR/XOR case
10380 leg for shift(logical). See details in logical handling above
10381 for reasoning in doing so. */
10382 if (code == LSHIFTRT
10383 && CONST_INT_P (XEXP (varop, 1))
10384 && mode_signbit_p (result_mode, XEXP (varop, 1))
10385 && (new_rtx = simplify_const_binary_operation (code, result_mode,
10387 GEN_INT (count))) != 0
10388 && CONST_INT_P (new_rtx)
10389 && merge_outer_ops (&outer_op, &outer_const, XOR,
10390 INTVAL (new_rtx), result_mode, &complement_p))
10392 varop = XEXP (varop, 0);
10399 /* If we have (xshiftrt (minus (ashiftrt X C)) X) C)
10400 with C the size of VAROP - 1 and the shift is logical if
10401 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
10402 we have a (gt X 0) operation. If the shift is arithmetic with
10403 STORE_FLAG_VALUE of 1 or logical with STORE_FLAG_VALUE == -1,
10404 we have a (neg (gt X 0)) operation. */
10406 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
10407 && GET_CODE (XEXP (varop, 0)) == ASHIFTRT
10408 && count == (GET_MODE_BITSIZE (GET_MODE (varop)) - 1)
10409 && (code == LSHIFTRT || code == ASHIFTRT)
10410 && CONST_INT_P (XEXP (XEXP (varop, 0), 1))
10411 && INTVAL (XEXP (XEXP (varop, 0), 1)) == count
10412 && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
10415 varop = gen_rtx_GT (GET_MODE (varop), XEXP (varop, 1),
10418 if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
10419 varop = gen_rtx_NEG (GET_MODE (varop), varop);
10426 /* Change (lshiftrt (truncate (lshiftrt))) to (truncate (lshiftrt))
10427 if the truncate does not affect the value. */
10428 if (code == LSHIFTRT
10429 && GET_CODE (XEXP (varop, 0)) == LSHIFTRT
10430 && CONST_INT_P (XEXP (XEXP (varop, 0), 1))
10431 && (INTVAL (XEXP (XEXP (varop, 0), 1))
10432 >= (GET_MODE_BITSIZE (GET_MODE (XEXP (varop, 0)))
10433 - GET_MODE_BITSIZE (GET_MODE (varop)))))
10435 rtx varop_inner = XEXP (varop, 0);
10438 = gen_rtx_LSHIFTRT (GET_MODE (varop_inner),
10439 XEXP (varop_inner, 0),
10441 (count + INTVAL (XEXP (varop_inner, 1))));
10442 varop = gen_rtx_TRUNCATE (GET_MODE (varop), varop_inner);
10455 shift_mode = try_widen_shift_mode (code, varop, count, result_mode, mode,
10456 outer_op, outer_const);
10458 /* We have now finished analyzing the shift. The result should be
10459 a shift of type CODE with SHIFT_MODE shifting VAROP COUNT places. If
10460 OUTER_OP is non-UNKNOWN, it is an operation that needs to be applied
10461 to the result of the shift. OUTER_CONST is the relevant constant,
10462 but we must turn off all bits turned off in the shift. */
10464 if (outer_op == UNKNOWN
10465 && orig_code == code && orig_count == count
10466 && varop == orig_varop
10467 && shift_mode == GET_MODE (varop))
10470 /* Make a SUBREG if necessary. If we can't make it, fail. */
10471 varop = gen_lowpart (shift_mode, varop);
10472 if (varop == NULL_RTX || GET_CODE (varop) == CLOBBER)
10475 /* If we have an outer operation and we just made a shift, it is
10476 possible that we could have simplified the shift were it not
10477 for the outer operation. So try to do the simplification
10480 if (outer_op != UNKNOWN)
10481 x = simplify_shift_const_1 (code, shift_mode, varop, count);
10486 x = simplify_gen_binary (code, shift_mode, varop, GEN_INT (count));
10488 /* If we were doing an LSHIFTRT in a wider mode than it was originally,
10489 turn off all the bits that the shift would have turned off. */
10490 if (orig_code == LSHIFTRT && result_mode != shift_mode)
10491 x = simplify_and_const_int (NULL_RTX, shift_mode, x,
10492 GET_MODE_MASK (result_mode) >> orig_count);
10494 /* Do the remainder of the processing in RESULT_MODE. */
10495 x = gen_lowpart_or_truncate (result_mode, x);
10497 /* If COMPLEMENT_P is set, we have to complement X before doing the outer
10500 x = simplify_gen_unary (NOT, result_mode, x, result_mode);
10502 if (outer_op != UNKNOWN)
10504 if (GET_RTX_CLASS (outer_op) != RTX_UNARY
10505 && GET_MODE_BITSIZE (result_mode) < HOST_BITS_PER_WIDE_INT)
10506 outer_const = trunc_int_for_mode (outer_const, result_mode);
10508 if (outer_op == AND)
10509 x = simplify_and_const_int (NULL_RTX, result_mode, x, outer_const);
10510 else if (outer_op == SET)
10512 /* This means that we have determined that the result is
10513 equivalent to a constant. This should be rare. */
10514 if (!side_effects_p (x))
10515 x = GEN_INT (outer_const);
10517 else if (GET_RTX_CLASS (outer_op) == RTX_UNARY)
10518 x = simplify_gen_unary (outer_op, result_mode, x, result_mode);
10520 x = simplify_gen_binary (outer_op, result_mode, x,
10521 GEN_INT (outer_const));
10527 /* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift.
10528 The result of the shift is RESULT_MODE. If we cannot simplify it,
10529 return X or, if it is NULL, synthesize the expression with
10530 simplify_gen_binary. Otherwise, return a simplified value.
10532 The shift is normally computed in the widest mode we find in VAROP, as
10533 long as it isn't a different number of words than RESULT_MODE. Exceptions
10534 are ASHIFTRT and ROTATE, which are always done in their original mode. */
10537 simplify_shift_const (rtx x, enum rtx_code code, enum machine_mode result_mode,
10538 rtx varop, int count)
10540 rtx tem = simplify_shift_const_1 (code, result_mode, varop, count);
10545 x = simplify_gen_binary (code, GET_MODE (varop), varop, GEN_INT (count));
10546 if (GET_MODE (x) != result_mode)
10547 x = gen_lowpart (result_mode, x);
10552 /* Like recog, but we receive the address of a pointer to a new pattern.
10553 We try to match the rtx that the pointer points to.
10554 If that fails, we may try to modify or replace the pattern,
10555 storing the replacement into the same pointer object.
10557 Modifications include deletion or addition of CLOBBERs.
10559 PNOTES is a pointer to a location where any REG_UNUSED notes added for
10560 the CLOBBERs are placed.
10562 The value is the final insn code from the pattern ultimately matched,
10566 recog_for_combine (rtx *pnewpat, rtx insn, rtx *pnotes)
10568 rtx pat = *pnewpat;
10569 int insn_code_number;
10570 int num_clobbers_to_add = 0;
10573 rtx old_notes, old_pat;
10575 /* If PAT is a PARALLEL, check to see if it contains the CLOBBER
10576 we use to indicate that something didn't match. If we find such a
10577 thing, force rejection. */
10578 if (GET_CODE (pat) == PARALLEL)
10579 for (i = XVECLEN (pat, 0) - 1; i >= 0; i--)
10580 if (GET_CODE (XVECEXP (pat, 0, i)) == CLOBBER
10581 && XEXP (XVECEXP (pat, 0, i), 0) == const0_rtx)
10584 old_pat = PATTERN (insn);
10585 old_notes = REG_NOTES (insn);
10586 PATTERN (insn) = pat;
10587 REG_NOTES (insn) = 0;
10589 insn_code_number = recog (pat, insn, &num_clobbers_to_add);
10590 if (dump_file && (dump_flags & TDF_DETAILS))
10592 if (insn_code_number < 0)
10593 fputs ("Failed to match this instruction:\n", dump_file);
10595 fputs ("Successfully matched this instruction:\n", dump_file);
10596 print_rtl_single (dump_file, pat);
10599 /* If it isn't, there is the possibility that we previously had an insn
10600 that clobbered some register as a side effect, but the combined
10601 insn doesn't need to do that. So try once more without the clobbers
10602 unless this represents an ASM insn. */
10604 if (insn_code_number < 0 && ! check_asm_operands (pat)
10605 && GET_CODE (pat) == PARALLEL)
10609 for (pos = 0, i = 0; i < XVECLEN (pat, 0); i++)
10610 if (GET_CODE (XVECEXP (pat, 0, i)) != CLOBBER)
10613 SUBST (XVECEXP (pat, 0, pos), XVECEXP (pat, 0, i));
10617 SUBST_INT (XVECLEN (pat, 0), pos);
10620 pat = XVECEXP (pat, 0, 0);
10622 PATTERN (insn) = pat;
10623 insn_code_number = recog (pat, insn, &num_clobbers_to_add);
10624 if (dump_file && (dump_flags & TDF_DETAILS))
10626 if (insn_code_number < 0)
10627 fputs ("Failed to match this instruction:\n", dump_file);
10629 fputs ("Successfully matched this instruction:\n", dump_file);
10630 print_rtl_single (dump_file, pat);
10633 PATTERN (insn) = old_pat;
10634 REG_NOTES (insn) = old_notes;
10636 /* Recognize all noop sets, these will be killed by followup pass. */
10637 if (insn_code_number < 0 && GET_CODE (pat) == SET && set_noop_p (pat))
10638 insn_code_number = NOOP_MOVE_INSN_CODE, num_clobbers_to_add = 0;
10640 /* If we had any clobbers to add, make a new pattern than contains
10641 them. Then check to make sure that all of them are dead. */
10642 if (num_clobbers_to_add)
10644 rtx newpat = gen_rtx_PARALLEL (VOIDmode,
10645 rtvec_alloc (GET_CODE (pat) == PARALLEL
10646 ? (XVECLEN (pat, 0)
10647 + num_clobbers_to_add)
10648 : num_clobbers_to_add + 1));
10650 if (GET_CODE (pat) == PARALLEL)
10651 for (i = 0; i < XVECLEN (pat, 0); i++)
10652 XVECEXP (newpat, 0, i) = XVECEXP (pat, 0, i);
10654 XVECEXP (newpat, 0, 0) = pat;
10656 add_clobbers (newpat, insn_code_number);
10658 for (i = XVECLEN (newpat, 0) - num_clobbers_to_add;
10659 i < XVECLEN (newpat, 0); i++)
10661 if (REG_P (XEXP (XVECEXP (newpat, 0, i), 0))
10662 && ! reg_dead_at_p (XEXP (XVECEXP (newpat, 0, i), 0), insn))
10664 if (GET_CODE (XEXP (XVECEXP (newpat, 0, i), 0)) != SCRATCH)
10666 gcc_assert (REG_P (XEXP (XVECEXP (newpat, 0, i), 0)));
10667 notes = alloc_reg_note (REG_UNUSED,
10668 XEXP (XVECEXP (newpat, 0, i), 0), notes);
10677 return insn_code_number;
10680 /* Like gen_lowpart_general but for use by combine. In combine it
10681 is not possible to create any new pseudoregs. However, it is
10682 safe to create invalid memory addresses, because combine will
10683 try to recognize them and all they will do is make the combine
10686 If for some reason this cannot do its job, an rtx
10687 (clobber (const_int 0)) is returned.
10688 An insn containing that will not be recognized. */
10691 gen_lowpart_for_combine (enum machine_mode omode, rtx x)
10693 enum machine_mode imode = GET_MODE (x);
10694 unsigned int osize = GET_MODE_SIZE (omode);
10695 unsigned int isize = GET_MODE_SIZE (imode);
10698 if (omode == imode)
10701 /* Return identity if this is a CONST or symbolic reference. */
10703 && (GET_CODE (x) == CONST
10704 || GET_CODE (x) == SYMBOL_REF
10705 || GET_CODE (x) == LABEL_REF))
10708 /* We can only support MODE being wider than a word if X is a
10709 constant integer or has a mode the same size. */
10710 if (GET_MODE_SIZE (omode) > UNITS_PER_WORD
10711 && ! ((imode == VOIDmode
10712 && (CONST_INT_P (x)
10713 || GET_CODE (x) == CONST_DOUBLE))
10714 || isize == osize))
10717 /* X might be a paradoxical (subreg (mem)). In that case, gen_lowpart
10718 won't know what to do. So we will strip off the SUBREG here and
10719 process normally. */
10720 if (GET_CODE (x) == SUBREG && MEM_P (SUBREG_REG (x)))
10722 x = SUBREG_REG (x);
10724 /* For use in case we fall down into the address adjustments
10725 further below, we need to adjust the known mode and size of
10726 x; imode and isize, since we just adjusted x. */
10727 imode = GET_MODE (x);
10729 if (imode == omode)
10732 isize = GET_MODE_SIZE (imode);
10735 result = gen_lowpart_common (omode, x);
10744 /* Refuse to work on a volatile memory ref or one with a mode-dependent
10746 if (MEM_VOLATILE_P (x) || mode_dependent_address_p (XEXP (x, 0)))
10749 /* If we want to refer to something bigger than the original memref,
10750 generate a paradoxical subreg instead. That will force a reload
10751 of the original memref X. */
10753 return gen_rtx_SUBREG (omode, x, 0);
10755 if (WORDS_BIG_ENDIAN)
10756 offset = MAX (isize, UNITS_PER_WORD) - MAX (osize, UNITS_PER_WORD);
10758 /* Adjust the address so that the address-after-the-data is
10760 if (BYTES_BIG_ENDIAN)
10761 offset -= MIN (UNITS_PER_WORD, osize) - MIN (UNITS_PER_WORD, isize);
10763 return adjust_address_nv (x, omode, offset);
10766 /* If X is a comparison operator, rewrite it in a new mode. This
10767 probably won't match, but may allow further simplifications. */
10768 else if (COMPARISON_P (x))
10769 return gen_rtx_fmt_ee (GET_CODE (x), omode, XEXP (x, 0), XEXP (x, 1));
10771 /* If we couldn't simplify X any other way, just enclose it in a
10772 SUBREG. Normally, this SUBREG won't match, but some patterns may
10773 include an explicit SUBREG or we may simplify it further in combine. */
10779 offset = subreg_lowpart_offset (omode, imode);
10780 if (imode == VOIDmode)
10782 imode = int_mode_for_mode (omode);
10783 x = gen_lowpart_common (imode, x);
10787 res = simplify_gen_subreg (omode, x, imode, offset);
10793 return gen_rtx_CLOBBER (omode, const0_rtx);
10796 /* Simplify a comparison between *POP0 and *POP1 where CODE is the
10797 comparison code that will be tested.
10799 The result is a possibly different comparison code to use. *POP0 and
10800 *POP1 may be updated.
10802 It is possible that we might detect that a comparison is either always
10803 true or always false. However, we do not perform general constant
10804 folding in combine, so this knowledge isn't useful. Such tautologies
10805 should have been detected earlier. Hence we ignore all such cases. */
10807 static enum rtx_code
10808 simplify_comparison (enum rtx_code code, rtx *pop0, rtx *pop1)
10814 enum machine_mode mode, tmode;
10816 /* Try a few ways of applying the same transformation to both operands. */
10819 #ifndef WORD_REGISTER_OPERATIONS
10820 /* The test below this one won't handle SIGN_EXTENDs on these machines,
10821 so check specially. */
10822 if (code != GTU && code != GEU && code != LTU && code != LEU
10823 && GET_CODE (op0) == ASHIFTRT && GET_CODE (op1) == ASHIFTRT
10824 && GET_CODE (XEXP (op0, 0)) == ASHIFT
10825 && GET_CODE (XEXP (op1, 0)) == ASHIFT
10826 && GET_CODE (XEXP (XEXP (op0, 0), 0)) == SUBREG
10827 && GET_CODE (XEXP (XEXP (op1, 0), 0)) == SUBREG
10828 && (GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0)))
10829 == GET_MODE (SUBREG_REG (XEXP (XEXP (op1, 0), 0))))
10830 && CONST_INT_P (XEXP (op0, 1))
10831 && XEXP (op0, 1) == XEXP (op1, 1)
10832 && XEXP (op0, 1) == XEXP (XEXP (op0, 0), 1)
10833 && XEXP (op0, 1) == XEXP (XEXP (op1, 0), 1)
10834 && (INTVAL (XEXP (op0, 1))
10835 == (GET_MODE_BITSIZE (GET_MODE (op0))
10836 - (GET_MODE_BITSIZE
10837 (GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0))))))))
10839 op0 = SUBREG_REG (XEXP (XEXP (op0, 0), 0));
10840 op1 = SUBREG_REG (XEXP (XEXP (op1, 0), 0));
10844 /* If both operands are the same constant shift, see if we can ignore the
10845 shift. We can if the shift is a rotate or if the bits shifted out of
10846 this shift are known to be zero for both inputs and if the type of
10847 comparison is compatible with the shift. */
10848 if (GET_CODE (op0) == GET_CODE (op1)
10849 && GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
10850 && ((GET_CODE (op0) == ROTATE && (code == NE || code == EQ))
10851 || ((GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFT)
10852 && (code != GT && code != LT && code != GE && code != LE))
10853 || (GET_CODE (op0) == ASHIFTRT
10854 && (code != GTU && code != LTU
10855 && code != GEU && code != LEU)))
10856 && CONST_INT_P (XEXP (op0, 1))
10857 && INTVAL (XEXP (op0, 1)) >= 0
10858 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT
10859 && XEXP (op0, 1) == XEXP (op1, 1))
10861 enum machine_mode mode = GET_MODE (op0);
10862 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
10863 int shift_count = INTVAL (XEXP (op0, 1));
10865 if (GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFTRT)
10866 mask &= (mask >> shift_count) << shift_count;
10867 else if (GET_CODE (op0) == ASHIFT)
10868 mask = (mask & (mask << shift_count)) >> shift_count;
10870 if ((nonzero_bits (XEXP (op0, 0), mode) & ~mask) == 0
10871 && (nonzero_bits (XEXP (op1, 0), mode) & ~mask) == 0)
10872 op0 = XEXP (op0, 0), op1 = XEXP (op1, 0);
10877 /* If both operands are AND's of a paradoxical SUBREG by constant, the
10878 SUBREGs are of the same mode, and, in both cases, the AND would
10879 be redundant if the comparison was done in the narrower mode,
10880 do the comparison in the narrower mode (e.g., we are AND'ing with 1
10881 and the operand's possibly nonzero bits are 0xffffff01; in that case
10882 if we only care about QImode, we don't need the AND). This case
10883 occurs if the output mode of an scc insn is not SImode and
10884 STORE_FLAG_VALUE == 1 (e.g., the 386).
10886 Similarly, check for a case where the AND's are ZERO_EXTEND
10887 operations from some narrower mode even though a SUBREG is not
10890 else if (GET_CODE (op0) == AND && GET_CODE (op1) == AND
10891 && CONST_INT_P (XEXP (op0, 1))
10892 && CONST_INT_P (XEXP (op1, 1)))
10894 rtx inner_op0 = XEXP (op0, 0);
10895 rtx inner_op1 = XEXP (op1, 0);
10896 HOST_WIDE_INT c0 = INTVAL (XEXP (op0, 1));
10897 HOST_WIDE_INT c1 = INTVAL (XEXP (op1, 1));
10900 if (GET_CODE (inner_op0) == SUBREG && GET_CODE (inner_op1) == SUBREG
10901 && (GET_MODE_SIZE (GET_MODE (inner_op0))
10902 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (inner_op0))))
10903 && (GET_MODE (SUBREG_REG (inner_op0))
10904 == GET_MODE (SUBREG_REG (inner_op1)))
10905 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (inner_op0)))
10906 <= HOST_BITS_PER_WIDE_INT)
10907 && (0 == ((~c0) & nonzero_bits (SUBREG_REG (inner_op0),
10908 GET_MODE (SUBREG_REG (inner_op0)))))
10909 && (0 == ((~c1) & nonzero_bits (SUBREG_REG (inner_op1),
10910 GET_MODE (SUBREG_REG (inner_op1))))))
10912 op0 = SUBREG_REG (inner_op0);
10913 op1 = SUBREG_REG (inner_op1);
10915 /* The resulting comparison is always unsigned since we masked
10916 off the original sign bit. */
10917 code = unsigned_condition (code);
10923 for (tmode = GET_CLASS_NARROWEST_MODE
10924 (GET_MODE_CLASS (GET_MODE (op0)));
10925 tmode != GET_MODE (op0); tmode = GET_MODE_WIDER_MODE (tmode))
10926 if ((unsigned HOST_WIDE_INT) c0 == GET_MODE_MASK (tmode))
10928 op0 = gen_lowpart (tmode, inner_op0);
10929 op1 = gen_lowpart (tmode, inner_op1);
10930 code = unsigned_condition (code);
10939 /* If both operands are NOT, we can strip off the outer operation
10940 and adjust the comparison code for swapped operands; similarly for
10941 NEG, except that this must be an equality comparison. */
10942 else if ((GET_CODE (op0) == NOT && GET_CODE (op1) == NOT)
10943 || (GET_CODE (op0) == NEG && GET_CODE (op1) == NEG
10944 && (code == EQ || code == NE)))
10945 op0 = XEXP (op0, 0), op1 = XEXP (op1, 0), code = swap_condition (code);
10951 /* If the first operand is a constant, swap the operands and adjust the
10952 comparison code appropriately, but don't do this if the second operand
10953 is already a constant integer. */
10954 if (swap_commutative_operands_p (op0, op1))
10956 tem = op0, op0 = op1, op1 = tem;
10957 code = swap_condition (code);
10960 /* We now enter a loop during which we will try to simplify the comparison.
10961 For the most part, we only are concerned with comparisons with zero,
10962 but some things may really be comparisons with zero but not start
10963 out looking that way. */
10965 while (CONST_INT_P (op1))
10967 enum machine_mode mode = GET_MODE (op0);
10968 unsigned int mode_width = GET_MODE_BITSIZE (mode);
10969 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
10970 int equality_comparison_p;
10971 int sign_bit_comparison_p;
10972 int unsigned_comparison_p;
10973 HOST_WIDE_INT const_op;
10975 /* We only want to handle integral modes. This catches VOIDmode,
10976 CCmode, and the floating-point modes. An exception is that we
10977 can handle VOIDmode if OP0 is a COMPARE or a comparison
10980 if (GET_MODE_CLASS (mode) != MODE_INT
10981 && ! (mode == VOIDmode
10982 && (GET_CODE (op0) == COMPARE || COMPARISON_P (op0))))
10985 /* Get the constant we are comparing against and turn off all bits
10986 not on in our mode. */
10987 const_op = INTVAL (op1);
10988 if (mode != VOIDmode)
10989 const_op = trunc_int_for_mode (const_op, mode);
10990 op1 = GEN_INT (const_op);
10992 /* If we are comparing against a constant power of two and the value
10993 being compared can only have that single bit nonzero (e.g., it was
10994 `and'ed with that bit), we can replace this with a comparison
10997 && (code == EQ || code == NE || code == GE || code == GEU
10998 || code == LT || code == LTU)
10999 && mode_width <= HOST_BITS_PER_WIDE_INT
11000 && exact_log2 (const_op) >= 0
11001 && nonzero_bits (op0, mode) == (unsigned HOST_WIDE_INT) const_op)
11003 code = (code == EQ || code == GE || code == GEU ? NE : EQ);
11004 op1 = const0_rtx, const_op = 0;
11007 /* Similarly, if we are comparing a value known to be either -1 or
11008 0 with -1, change it to the opposite comparison against zero. */
11011 && (code == EQ || code == NE || code == GT || code == LE
11012 || code == GEU || code == LTU)
11013 && num_sign_bit_copies (op0, mode) == mode_width)
11015 code = (code == EQ || code == LE || code == GEU ? NE : EQ);
11016 op1 = const0_rtx, const_op = 0;
11019 /* Do some canonicalizations based on the comparison code. We prefer
11020 comparisons against zero and then prefer equality comparisons.
11021 If we can reduce the size of a constant, we will do that too. */
11026 /* < C is equivalent to <= (C - 1) */
11030 op1 = GEN_INT (const_op);
11032 /* ... fall through to LE case below. */
11038 /* <= C is equivalent to < (C + 1); we do this for C < 0 */
11042 op1 = GEN_INT (const_op);
11046 /* If we are doing a <= 0 comparison on a value known to have
11047 a zero sign bit, we can replace this with == 0. */
11048 else if (const_op == 0
11049 && mode_width <= HOST_BITS_PER_WIDE_INT
11050 && (nonzero_bits (op0, mode)
11051 & ((unsigned HOST_WIDE_INT) 1 << (mode_width - 1)))
11057 /* >= C is equivalent to > (C - 1). */
11061 op1 = GEN_INT (const_op);
11063 /* ... fall through to GT below. */
11069 /* > C is equivalent to >= (C + 1); we do this for C < 0. */
11073 op1 = GEN_INT (const_op);
11077 /* If we are doing a > 0 comparison on a value known to have
11078 a zero sign bit, we can replace this with != 0. */
11079 else if (const_op == 0
11080 && mode_width <= HOST_BITS_PER_WIDE_INT
11081 && (nonzero_bits (op0, mode)
11082 & ((unsigned HOST_WIDE_INT) 1 << (mode_width - 1)))
11088 /* < C is equivalent to <= (C - 1). */
11092 op1 = GEN_INT (const_op);
11094 /* ... fall through ... */
11097 /* (unsigned) < 0x80000000 is equivalent to >= 0. */
11098 else if (mode_width <= HOST_BITS_PER_WIDE_INT
11099 && (unsigned HOST_WIDE_INT) const_op
11100 == (unsigned HOST_WIDE_INT) 1 << (mode_width - 1))
11102 const_op = 0, op1 = const0_rtx;
11110 /* unsigned <= 0 is equivalent to == 0 */
11114 /* (unsigned) <= 0x7fffffff is equivalent to >= 0. */
11115 else if (mode_width <= HOST_BITS_PER_WIDE_INT
11116 && (unsigned HOST_WIDE_INT) const_op
11117 == ((unsigned HOST_WIDE_INT) 1 << (mode_width - 1)) - 1)
11119 const_op = 0, op1 = const0_rtx;
11125 /* >= C is equivalent to > (C - 1). */
11129 op1 = GEN_INT (const_op);
11131 /* ... fall through ... */
11134 /* (unsigned) >= 0x80000000 is equivalent to < 0. */
11135 else if (mode_width <= HOST_BITS_PER_WIDE_INT
11136 && (unsigned HOST_WIDE_INT) const_op
11137 == (unsigned HOST_WIDE_INT) 1 << (mode_width - 1))
11139 const_op = 0, op1 = const0_rtx;
11147 /* unsigned > 0 is equivalent to != 0 */
11151 /* (unsigned) > 0x7fffffff is equivalent to < 0. */
11152 else if (mode_width <= HOST_BITS_PER_WIDE_INT
11153 && (unsigned HOST_WIDE_INT) const_op
11154 == ((unsigned HOST_WIDE_INT) 1 << (mode_width - 1)) - 1)
11156 const_op = 0, op1 = const0_rtx;
11165 /* Compute some predicates to simplify code below. */
11167 equality_comparison_p = (code == EQ || code == NE);
11168 sign_bit_comparison_p = ((code == LT || code == GE) && const_op == 0);
11169 unsigned_comparison_p = (code == LTU || code == LEU || code == GTU
11172 /* If this is a sign bit comparison and we can do arithmetic in
11173 MODE, say that we will only be needing the sign bit of OP0. */
11174 if (sign_bit_comparison_p
11175 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
11176 op0 = force_to_mode (op0, mode,
11177 (unsigned HOST_WIDE_INT) 1
11178 << (GET_MODE_BITSIZE (mode) - 1),
11181 /* Now try cases based on the opcode of OP0. If none of the cases
11182 does a "continue", we exit this loop immediately after the
11185 switch (GET_CODE (op0))
11188 /* If we are extracting a single bit from a variable position in
11189 a constant that has only a single bit set and are comparing it
11190 with zero, we can convert this into an equality comparison
11191 between the position and the location of the single bit. */
11192 /* Except we can't if SHIFT_COUNT_TRUNCATED is set, since we might
11193 have already reduced the shift count modulo the word size. */
11194 if (!SHIFT_COUNT_TRUNCATED
11195 && CONST_INT_P (XEXP (op0, 0))
11196 && XEXP (op0, 1) == const1_rtx
11197 && equality_comparison_p && const_op == 0
11198 && (i = exact_log2 (UINTVAL (XEXP (op0, 0)))) >= 0)
11200 if (BITS_BIG_ENDIAN)
11202 enum machine_mode new_mode
11203 = mode_for_extraction (EP_extzv, 1);
11204 if (new_mode == MAX_MACHINE_MODE)
11205 i = BITS_PER_WORD - 1 - i;
11209 i = (GET_MODE_BITSIZE (mode) - 1 - i);
11213 op0 = XEXP (op0, 2);
11217 /* Result is nonzero iff shift count is equal to I. */
11218 code = reverse_condition (code);
11222 /* ... fall through ... */
11225 tem = expand_compound_operation (op0);
11234 /* If testing for equality, we can take the NOT of the constant. */
11235 if (equality_comparison_p
11236 && (tem = simplify_unary_operation (NOT, mode, op1, mode)) != 0)
11238 op0 = XEXP (op0, 0);
11243 /* If just looking at the sign bit, reverse the sense of the
11245 if (sign_bit_comparison_p)
11247 op0 = XEXP (op0, 0);
11248 code = (code == GE ? LT : GE);
11254 /* If testing for equality, we can take the NEG of the constant. */
11255 if (equality_comparison_p
11256 && (tem = simplify_unary_operation (NEG, mode, op1, mode)) != 0)
11258 op0 = XEXP (op0, 0);
11263 /* The remaining cases only apply to comparisons with zero. */
11267 /* When X is ABS or is known positive,
11268 (neg X) is < 0 if and only if X != 0. */
11270 if (sign_bit_comparison_p
11271 && (GET_CODE (XEXP (op0, 0)) == ABS
11272 || (mode_width <= HOST_BITS_PER_WIDE_INT
11273 && (nonzero_bits (XEXP (op0, 0), mode)
11274 & ((unsigned HOST_WIDE_INT) 1 << (mode_width - 1)))
11277 op0 = XEXP (op0, 0);
11278 code = (code == LT ? NE : EQ);
11282 /* If we have NEG of something whose two high-order bits are the
11283 same, we know that "(-a) < 0" is equivalent to "a > 0". */
11284 if (num_sign_bit_copies (op0, mode) >= 2)
11286 op0 = XEXP (op0, 0);
11287 code = swap_condition (code);
11293 /* If we are testing equality and our count is a constant, we
11294 can perform the inverse operation on our RHS. */
11295 if (equality_comparison_p && CONST_INT_P (XEXP (op0, 1))
11296 && (tem = simplify_binary_operation (ROTATERT, mode,
11297 op1, XEXP (op0, 1))) != 0)
11299 op0 = XEXP (op0, 0);
11304 /* If we are doing a < 0 or >= 0 comparison, it means we are testing
11305 a particular bit. Convert it to an AND of a constant of that
11306 bit. This will be converted into a ZERO_EXTRACT. */
11307 if (const_op == 0 && sign_bit_comparison_p
11308 && CONST_INT_P (XEXP (op0, 1))
11309 && mode_width <= HOST_BITS_PER_WIDE_INT)
11311 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
11312 ((unsigned HOST_WIDE_INT) 1
11314 - INTVAL (XEXP (op0, 1)))));
11315 code = (code == LT ? NE : EQ);
11319 /* Fall through. */
11322 /* ABS is ignorable inside an equality comparison with zero. */
11323 if (const_op == 0 && equality_comparison_p)
11325 op0 = XEXP (op0, 0);
11331 /* Can simplify (compare (zero/sign_extend FOO) CONST) to
11332 (compare FOO CONST) if CONST fits in FOO's mode and we
11333 are either testing inequality or have an unsigned
11334 comparison with ZERO_EXTEND or a signed comparison with
11335 SIGN_EXTEND. But don't do it if we don't have a compare
11336 insn of the given mode, since we'd have to revert it
11337 later on, and then we wouldn't know whether to sign- or
11339 mode = GET_MODE (XEXP (op0, 0));
11340 if (mode != VOIDmode && GET_MODE_CLASS (mode) == MODE_INT
11341 && ! unsigned_comparison_p
11342 && (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
11343 && ((unsigned HOST_WIDE_INT) const_op
11344 < (((unsigned HOST_WIDE_INT) 1
11345 << (GET_MODE_BITSIZE (mode) - 1))))
11346 && have_insn_for (COMPARE, mode))
11348 op0 = XEXP (op0, 0);
11354 /* Check for the case where we are comparing A - C1 with C2, that is
11356 (subreg:MODE (plus (A) (-C1))) op (C2)
11358 with C1 a constant, and try to lift the SUBREG, i.e. to do the
11359 comparison in the wider mode. One of the following two conditions
11360 must be true in order for this to be valid:
11362 1. The mode extension results in the same bit pattern being added
11363 on both sides and the comparison is equality or unsigned. As
11364 C2 has been truncated to fit in MODE, the pattern can only be
11367 2. The mode extension results in the sign bit being copied on
11370 The difficulty here is that we have predicates for A but not for
11371 (A - C1) so we need to check that C1 is within proper bounds so
11372 as to perturbate A as little as possible. */
11374 if (mode_width <= HOST_BITS_PER_WIDE_INT
11375 && subreg_lowpart_p (op0)
11376 && GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0))) > mode_width
11377 && GET_CODE (SUBREG_REG (op0)) == PLUS
11378 && CONST_INT_P (XEXP (SUBREG_REG (op0), 1)))
11380 enum machine_mode inner_mode = GET_MODE (SUBREG_REG (op0));
11381 rtx a = XEXP (SUBREG_REG (op0), 0);
11382 HOST_WIDE_INT c1 = -INTVAL (XEXP (SUBREG_REG (op0), 1));
11385 && (unsigned HOST_WIDE_INT) c1
11386 < (unsigned HOST_WIDE_INT) 1 << (mode_width - 1)
11387 && (equality_comparison_p || unsigned_comparison_p)
11388 /* (A - C1) zero-extends if it is positive and sign-extends
11389 if it is negative, C2 both zero- and sign-extends. */
11390 && ((0 == (nonzero_bits (a, inner_mode)
11391 & ~GET_MODE_MASK (mode))
11393 /* (A - C1) sign-extends if it is positive and 1-extends
11394 if it is negative, C2 both sign- and 1-extends. */
11395 || (num_sign_bit_copies (a, inner_mode)
11396 > (unsigned int) (GET_MODE_BITSIZE (inner_mode)
11399 || ((unsigned HOST_WIDE_INT) c1
11400 < (unsigned HOST_WIDE_INT) 1 << (mode_width - 2)
11401 /* (A - C1) always sign-extends, like C2. */
11402 && num_sign_bit_copies (a, inner_mode)
11403 > (unsigned int) (GET_MODE_BITSIZE (inner_mode)
11404 - (mode_width - 1))))
11406 op0 = SUBREG_REG (op0);
11411 /* If the inner mode is narrower and we are extracting the low part,
11412 we can treat the SUBREG as if it were a ZERO_EXTEND. */
11413 if (subreg_lowpart_p (op0)
11414 && GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0))) < mode_width)
11415 /* Fall through */ ;
11419 /* ... fall through ... */
11422 mode = GET_MODE (XEXP (op0, 0));
11423 if (mode != VOIDmode && GET_MODE_CLASS (mode) == MODE_INT
11424 && (unsigned_comparison_p || equality_comparison_p)
11425 && (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
11426 && ((unsigned HOST_WIDE_INT) const_op < GET_MODE_MASK (mode))
11427 && have_insn_for (COMPARE, mode))
11429 op0 = XEXP (op0, 0);
11435 /* (eq (plus X A) B) -> (eq X (minus B A)). We can only do
11436 this for equality comparisons due to pathological cases involving
11438 if (equality_comparison_p
11439 && 0 != (tem = simplify_binary_operation (MINUS, mode,
11440 op1, XEXP (op0, 1))))
11442 op0 = XEXP (op0, 0);
11447 /* (plus (abs X) (const_int -1)) is < 0 if and only if X == 0. */
11448 if (const_op == 0 && XEXP (op0, 1) == constm1_rtx
11449 && GET_CODE (XEXP (op0, 0)) == ABS && sign_bit_comparison_p)
11451 op0 = XEXP (XEXP (op0, 0), 0);
11452 code = (code == LT ? EQ : NE);
11458 /* We used to optimize signed comparisons against zero, but that
11459 was incorrect. Unsigned comparisons against zero (GTU, LEU)
11460 arrive here as equality comparisons, or (GEU, LTU) are
11461 optimized away. No need to special-case them. */
11463 /* (eq (minus A B) C) -> (eq A (plus B C)) or
11464 (eq B (minus A C)), whichever simplifies. We can only do
11465 this for equality comparisons due to pathological cases involving
11467 if (equality_comparison_p
11468 && 0 != (tem = simplify_binary_operation (PLUS, mode,
11469 XEXP (op0, 1), op1)))
11471 op0 = XEXP (op0, 0);
11476 if (equality_comparison_p
11477 && 0 != (tem = simplify_binary_operation (MINUS, mode,
11478 XEXP (op0, 0), op1)))
11480 op0 = XEXP (op0, 1);
11485 /* The sign bit of (minus (ashiftrt X C) X), where C is the number
11486 of bits in X minus 1, is one iff X > 0. */
11487 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == ASHIFTRT
11488 && CONST_INT_P (XEXP (XEXP (op0, 0), 1))
11489 && UINTVAL (XEXP (XEXP (op0, 0), 1)) == mode_width - 1
11490 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
11492 op0 = XEXP (op0, 1);
11493 code = (code == GE ? LE : GT);
11499 /* (eq (xor A B) C) -> (eq A (xor B C)). This is a simplification
11500 if C is zero or B is a constant. */
11501 if (equality_comparison_p
11502 && 0 != (tem = simplify_binary_operation (XOR, mode,
11503 XEXP (op0, 1), op1)))
11505 op0 = XEXP (op0, 0);
11512 case UNEQ: case LTGT:
11513 case LT: case LTU: case UNLT: case LE: case LEU: case UNLE:
11514 case GT: case GTU: case UNGT: case GE: case GEU: case UNGE:
11515 case UNORDERED: case ORDERED:
11516 /* We can't do anything if OP0 is a condition code value, rather
11517 than an actual data value. */
11519 || CC0_P (XEXP (op0, 0))
11520 || GET_MODE_CLASS (GET_MODE (XEXP (op0, 0))) == MODE_CC)
11523 /* Get the two operands being compared. */
11524 if (GET_CODE (XEXP (op0, 0)) == COMPARE)
11525 tem = XEXP (XEXP (op0, 0), 0), tem1 = XEXP (XEXP (op0, 0), 1);
11527 tem = XEXP (op0, 0), tem1 = XEXP (op0, 1);
11529 /* Check for the cases where we simply want the result of the
11530 earlier test or the opposite of that result. */
11531 if (code == NE || code == EQ
11532 || (GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
11533 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
11534 && (STORE_FLAG_VALUE
11535 & (((unsigned HOST_WIDE_INT) 1
11536 << (GET_MODE_BITSIZE (GET_MODE (op0)) - 1))))
11537 && (code == LT || code == GE)))
11539 enum rtx_code new_code;
11540 if (code == LT || code == NE)
11541 new_code = GET_CODE (op0);
11543 new_code = reversed_comparison_code (op0, NULL);
11545 if (new_code != UNKNOWN)
11556 /* The sign bit of (ior (plus X (const_int -1)) X) is nonzero
11558 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == PLUS
11559 && XEXP (XEXP (op0, 0), 1) == constm1_rtx
11560 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
11562 op0 = XEXP (op0, 1);
11563 code = (code == GE ? GT : LE);
11569 /* Convert (and (xshift 1 X) Y) to (and (lshiftrt Y X) 1). This
11570 will be converted to a ZERO_EXTRACT later. */
11571 if (const_op == 0 && equality_comparison_p
11572 && GET_CODE (XEXP (op0, 0)) == ASHIFT
11573 && XEXP (XEXP (op0, 0), 0) == const1_rtx)
11575 op0 = gen_rtx_LSHIFTRT (mode, XEXP (op0, 1),
11576 XEXP (XEXP (op0, 0), 1));
11577 op0 = simplify_and_const_int (NULL_RTX, mode, op0, 1);
11581 /* If we are comparing (and (lshiftrt X C1) C2) for equality with
11582 zero and X is a comparison and C1 and C2 describe only bits set
11583 in STORE_FLAG_VALUE, we can compare with X. */
11584 if (const_op == 0 && equality_comparison_p
11585 && mode_width <= HOST_BITS_PER_WIDE_INT
11586 && CONST_INT_P (XEXP (op0, 1))
11587 && GET_CODE (XEXP (op0, 0)) == LSHIFTRT
11588 && CONST_INT_P (XEXP (XEXP (op0, 0), 1))
11589 && INTVAL (XEXP (XEXP (op0, 0), 1)) >= 0
11590 && INTVAL (XEXP (XEXP (op0, 0), 1)) < HOST_BITS_PER_WIDE_INT)
11592 mask = ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
11593 << INTVAL (XEXP (XEXP (op0, 0), 1)));
11594 if ((~STORE_FLAG_VALUE & mask) == 0
11595 && (COMPARISON_P (XEXP (XEXP (op0, 0), 0))
11596 || ((tem = get_last_value (XEXP (XEXP (op0, 0), 0))) != 0
11597 && COMPARISON_P (tem))))
11599 op0 = XEXP (XEXP (op0, 0), 0);
11604 /* If we are doing an equality comparison of an AND of a bit equal
11605 to the sign bit, replace this with a LT or GE comparison of
11606 the underlying value. */
11607 if (equality_comparison_p
11609 && CONST_INT_P (XEXP (op0, 1))
11610 && mode_width <= HOST_BITS_PER_WIDE_INT
11611 && ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
11612 == (unsigned HOST_WIDE_INT) 1 << (mode_width - 1)))
11614 op0 = XEXP (op0, 0);
11615 code = (code == EQ ? GE : LT);
11619 /* If this AND operation is really a ZERO_EXTEND from a narrower
11620 mode, the constant fits within that mode, and this is either an
11621 equality or unsigned comparison, try to do this comparison in
11626 (ne:DI (and:DI (reg:DI 4) (const_int 0xffffffff)) (const_int 0))
11627 -> (ne:DI (reg:SI 4) (const_int 0))
11629 unless TRULY_NOOP_TRUNCATION allows it or the register is
11630 known to hold a value of the required mode the
11631 transformation is invalid. */
11632 if ((equality_comparison_p || unsigned_comparison_p)
11633 && CONST_INT_P (XEXP (op0, 1))
11634 && (i = exact_log2 ((UINTVAL (XEXP (op0, 1))
11635 & GET_MODE_MASK (mode))
11637 && const_op >> i == 0
11638 && (tmode = mode_for_size (i, MODE_INT, 1)) != BLKmode
11639 && (TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (tmode),
11640 GET_MODE_BITSIZE (GET_MODE (op0)))
11641 || (REG_P (XEXP (op0, 0))
11642 && reg_truncated_to_mode (tmode, XEXP (op0, 0)))))
11644 op0 = gen_lowpart (tmode, XEXP (op0, 0));
11648 /* If this is (and:M1 (subreg:M2 X 0) (const_int C1)) where C1
11649 fits in both M1 and M2 and the SUBREG is either paradoxical
11650 or represents the low part, permute the SUBREG and the AND
11652 if (GET_CODE (XEXP (op0, 0)) == SUBREG)
11654 unsigned HOST_WIDE_INT c1;
11655 tmode = GET_MODE (SUBREG_REG (XEXP (op0, 0)));
11656 /* Require an integral mode, to avoid creating something like
11658 if (SCALAR_INT_MODE_P (tmode)
11659 /* It is unsafe to commute the AND into the SUBREG if the
11660 SUBREG is paradoxical and WORD_REGISTER_OPERATIONS is
11661 not defined. As originally written the upper bits
11662 have a defined value due to the AND operation.
11663 However, if we commute the AND inside the SUBREG then
11664 they no longer have defined values and the meaning of
11665 the code has been changed. */
11667 #ifdef WORD_REGISTER_OPERATIONS
11668 || (mode_width > GET_MODE_BITSIZE (tmode)
11669 && mode_width <= BITS_PER_WORD)
11671 || (mode_width <= GET_MODE_BITSIZE (tmode)
11672 && subreg_lowpart_p (XEXP (op0, 0))))
11673 && CONST_INT_P (XEXP (op0, 1))
11674 && mode_width <= HOST_BITS_PER_WIDE_INT
11675 && GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT
11676 && ((c1 = INTVAL (XEXP (op0, 1))) & ~mask) == 0
11677 && (c1 & ~GET_MODE_MASK (tmode)) == 0
11679 && c1 != GET_MODE_MASK (tmode))
11681 op0 = simplify_gen_binary (AND, tmode,
11682 SUBREG_REG (XEXP (op0, 0)),
11683 gen_int_mode (c1, tmode));
11684 op0 = gen_lowpart (mode, op0);
11689 /* Convert (ne (and (not X) 1) 0) to (eq (and X 1) 0). */
11690 if (const_op == 0 && equality_comparison_p
11691 && XEXP (op0, 1) == const1_rtx
11692 && GET_CODE (XEXP (op0, 0)) == NOT)
11694 op0 = simplify_and_const_int (NULL_RTX, mode,
11695 XEXP (XEXP (op0, 0), 0), 1);
11696 code = (code == NE ? EQ : NE);
11700 /* Convert (ne (and (lshiftrt (not X)) 1) 0) to
11701 (eq (and (lshiftrt X) 1) 0).
11702 Also handle the case where (not X) is expressed using xor. */
11703 if (const_op == 0 && equality_comparison_p
11704 && XEXP (op0, 1) == const1_rtx
11705 && GET_CODE (XEXP (op0, 0)) == LSHIFTRT)
11707 rtx shift_op = XEXP (XEXP (op0, 0), 0);
11708 rtx shift_count = XEXP (XEXP (op0, 0), 1);
11710 if (GET_CODE (shift_op) == NOT
11711 || (GET_CODE (shift_op) == XOR
11712 && CONST_INT_P (XEXP (shift_op, 1))
11713 && CONST_INT_P (shift_count)
11714 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
11715 && (UINTVAL (XEXP (shift_op, 1))
11716 == (unsigned HOST_WIDE_INT) 1
11717 << INTVAL (shift_count))))
11720 = gen_rtx_LSHIFTRT (mode, XEXP (shift_op, 0), shift_count);
11721 op0 = simplify_and_const_int (NULL_RTX, mode, op0, 1);
11722 code = (code == NE ? EQ : NE);
11729 /* If we have (compare (ashift FOO N) (const_int C)) and
11730 the high order N bits of FOO (N+1 if an inequality comparison)
11731 are known to be zero, we can do this by comparing FOO with C
11732 shifted right N bits so long as the low-order N bits of C are
11734 if (CONST_INT_P (XEXP (op0, 1))
11735 && INTVAL (XEXP (op0, 1)) >= 0
11736 && ((INTVAL (XEXP (op0, 1)) + ! equality_comparison_p)
11737 < HOST_BITS_PER_WIDE_INT)
11738 && (((unsigned HOST_WIDE_INT) const_op
11739 & (((unsigned HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1)))
11741 && mode_width <= HOST_BITS_PER_WIDE_INT
11742 && (nonzero_bits (XEXP (op0, 0), mode)
11743 & ~(mask >> (INTVAL (XEXP (op0, 1))
11744 + ! equality_comparison_p))) == 0)
11746 /* We must perform a logical shift, not an arithmetic one,
11747 as we want the top N bits of C to be zero. */
11748 unsigned HOST_WIDE_INT temp = const_op & GET_MODE_MASK (mode);
11750 temp >>= INTVAL (XEXP (op0, 1));
11751 op1 = gen_int_mode (temp, mode);
11752 op0 = XEXP (op0, 0);
11756 /* If we are doing a sign bit comparison, it means we are testing
11757 a particular bit. Convert it to the appropriate AND. */
11758 if (sign_bit_comparison_p && CONST_INT_P (XEXP (op0, 1))
11759 && mode_width <= HOST_BITS_PER_WIDE_INT)
11761 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
11762 ((unsigned HOST_WIDE_INT) 1
11764 - INTVAL (XEXP (op0, 1)))));
11765 code = (code == LT ? NE : EQ);
11769 /* If this an equality comparison with zero and we are shifting
11770 the low bit to the sign bit, we can convert this to an AND of the
11772 if (const_op == 0 && equality_comparison_p
11773 && CONST_INT_P (XEXP (op0, 1))
11774 && UINTVAL (XEXP (op0, 1)) == mode_width - 1)
11776 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0), 1);
11782 /* If this is an equality comparison with zero, we can do this
11783 as a logical shift, which might be much simpler. */
11784 if (equality_comparison_p && const_op == 0
11785 && CONST_INT_P (XEXP (op0, 1)))
11787 op0 = simplify_shift_const (NULL_RTX, LSHIFTRT, mode,
11789 INTVAL (XEXP (op0, 1)));
11793 /* If OP0 is a sign extension and CODE is not an unsigned comparison,
11794 do the comparison in a narrower mode. */
11795 if (! unsigned_comparison_p
11796 && CONST_INT_P (XEXP (op0, 1))
11797 && GET_CODE (XEXP (op0, 0)) == ASHIFT
11798 && XEXP (op0, 1) == XEXP (XEXP (op0, 0), 1)
11799 && (tmode = mode_for_size (mode_width - INTVAL (XEXP (op0, 1)),
11800 MODE_INT, 1)) != BLKmode
11801 && (((unsigned HOST_WIDE_INT) const_op
11802 + (GET_MODE_MASK (tmode) >> 1) + 1)
11803 <= GET_MODE_MASK (tmode)))
11805 op0 = gen_lowpart (tmode, XEXP (XEXP (op0, 0), 0));
11809 /* Likewise if OP0 is a PLUS of a sign extension with a
11810 constant, which is usually represented with the PLUS
11811 between the shifts. */
11812 if (! unsigned_comparison_p
11813 && CONST_INT_P (XEXP (op0, 1))
11814 && GET_CODE (XEXP (op0, 0)) == PLUS
11815 && CONST_INT_P (XEXP (XEXP (op0, 0), 1))
11816 && GET_CODE (XEXP (XEXP (op0, 0), 0)) == ASHIFT
11817 && XEXP (op0, 1) == XEXP (XEXP (XEXP (op0, 0), 0), 1)
11818 && (tmode = mode_for_size (mode_width - INTVAL (XEXP (op0, 1)),
11819 MODE_INT, 1)) != BLKmode
11820 && (((unsigned HOST_WIDE_INT) const_op
11821 + (GET_MODE_MASK (tmode) >> 1) + 1)
11822 <= GET_MODE_MASK (tmode)))
11824 rtx inner = XEXP (XEXP (XEXP (op0, 0), 0), 0);
11825 rtx add_const = XEXP (XEXP (op0, 0), 1);
11826 rtx new_const = simplify_gen_binary (ASHIFTRT, GET_MODE (op0),
11827 add_const, XEXP (op0, 1));
11829 op0 = simplify_gen_binary (PLUS, tmode,
11830 gen_lowpart (tmode, inner),
11835 /* ... fall through ... */
11837 /* If we have (compare (xshiftrt FOO N) (const_int C)) and
11838 the low order N bits of FOO are known to be zero, we can do this
11839 by comparing FOO with C shifted left N bits so long as no
11840 overflow occurs. Even if the low order N bits of FOO aren't known
11841 to be zero, if the comparison is >= or < we can use the same
11842 optimization and for > or <= by setting all the low
11843 order N bits in the comparison constant. */
11844 if (CONST_INT_P (XEXP (op0, 1))
11845 && INTVAL (XEXP (op0, 1)) > 0
11846 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT
11847 && mode_width <= HOST_BITS_PER_WIDE_INT
11848 && (((unsigned HOST_WIDE_INT) const_op
11849 + (GET_CODE (op0) != LSHIFTRT
11850 ? ((GET_MODE_MASK (mode) >> INTVAL (XEXP (op0, 1)) >> 1)
11853 <= GET_MODE_MASK (mode) >> INTVAL (XEXP (op0, 1))))
11855 unsigned HOST_WIDE_INT low_bits
11856 = (nonzero_bits (XEXP (op0, 0), mode)
11857 & (((unsigned HOST_WIDE_INT) 1
11858 << INTVAL (XEXP (op0, 1))) - 1));
11859 if (low_bits == 0 || !equality_comparison_p)
11861 /* If the shift was logical, then we must make the condition
11863 if (GET_CODE (op0) == LSHIFTRT)
11864 code = unsigned_condition (code);
11866 const_op <<= INTVAL (XEXP (op0, 1));
11868 && (code == GT || code == GTU
11869 || code == LE || code == LEU))
11871 |= (((HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1))) - 1);
11872 op1 = GEN_INT (const_op);
11873 op0 = XEXP (op0, 0);
11878 /* If we are using this shift to extract just the sign bit, we
11879 can replace this with an LT or GE comparison. */
11881 && (equality_comparison_p || sign_bit_comparison_p)
11882 && CONST_INT_P (XEXP (op0, 1))
11883 && UINTVAL (XEXP (op0, 1)) == mode_width - 1)
11885 op0 = XEXP (op0, 0);
11886 code = (code == NE || code == GT ? LT : GE);
11898 /* Now make any compound operations involved in this comparison. Then,
11899 check for an outmost SUBREG on OP0 that is not doing anything or is
11900 paradoxical. The latter transformation must only be performed when
11901 it is known that the "extra" bits will be the same in op0 and op1 or
11902 that they don't matter. There are three cases to consider:
11904 1. SUBREG_REG (op0) is a register. In this case the bits are don't
11905 care bits and we can assume they have any convenient value. So
11906 making the transformation is safe.
11908 2. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is not defined.
11909 In this case the upper bits of op0 are undefined. We should not make
11910 the simplification in that case as we do not know the contents of
11913 3. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is defined and not
11914 UNKNOWN. In that case we know those bits are zeros or ones. We must
11915 also be sure that they are the same as the upper bits of op1.
11917 We can never remove a SUBREG for a non-equality comparison because
11918 the sign bit is in a different place in the underlying object. */
11920 op0 = make_compound_operation (op0, op1 == const0_rtx ? COMPARE : SET);
11921 op1 = make_compound_operation (op1, SET);
11923 if (GET_CODE (op0) == SUBREG && subreg_lowpart_p (op0)
11924 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
11925 && GET_MODE_CLASS (GET_MODE (SUBREG_REG (op0))) == MODE_INT
11926 && (code == NE || code == EQ))
11928 if (GET_MODE_SIZE (GET_MODE (op0))
11929 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (op0))))
11931 /* For paradoxical subregs, allow case 1 as above. Case 3 isn't
11933 if (REG_P (SUBREG_REG (op0)))
11935 op0 = SUBREG_REG (op0);
11936 op1 = gen_lowpart (GET_MODE (op0), op1);
11939 else if ((GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0)))
11940 <= HOST_BITS_PER_WIDE_INT)
11941 && (nonzero_bits (SUBREG_REG (op0),
11942 GET_MODE (SUBREG_REG (op0)))
11943 & ~GET_MODE_MASK (GET_MODE (op0))) == 0)
11945 tem = gen_lowpart (GET_MODE (SUBREG_REG (op0)), op1);
11947 if ((nonzero_bits (tem, GET_MODE (SUBREG_REG (op0)))
11948 & ~GET_MODE_MASK (GET_MODE (op0))) == 0)
11949 op0 = SUBREG_REG (op0), op1 = tem;
11953 /* We now do the opposite procedure: Some machines don't have compare
11954 insns in all modes. If OP0's mode is an integer mode smaller than a
11955 word and we can't do a compare in that mode, see if there is a larger
11956 mode for which we can do the compare. There are a number of cases in
11957 which we can use the wider mode. */
11959 mode = GET_MODE (op0);
11960 if (mode != VOIDmode && GET_MODE_CLASS (mode) == MODE_INT
11961 && GET_MODE_SIZE (mode) < UNITS_PER_WORD
11962 && ! have_insn_for (COMPARE, mode))
11963 for (tmode = GET_MODE_WIDER_MODE (mode);
11965 && GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT);
11966 tmode = GET_MODE_WIDER_MODE (tmode))
11967 if (have_insn_for (COMPARE, tmode))
11971 /* If this is a test for negative, we can make an explicit
11972 test of the sign bit. Test this first so we can use
11973 a paradoxical subreg to extend OP0. */
11975 if (op1 == const0_rtx && (code == LT || code == GE)
11976 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
11978 op0 = simplify_gen_binary (AND, tmode,
11979 gen_lowpart (tmode, op0),
11980 GEN_INT ((unsigned HOST_WIDE_INT) 1
11981 << (GET_MODE_BITSIZE (mode)
11983 code = (code == LT) ? NE : EQ;
11987 /* If the only nonzero bits in OP0 and OP1 are those in the
11988 narrower mode and this is an equality or unsigned comparison,
11989 we can use the wider mode. Similarly for sign-extended
11990 values, in which case it is true for all comparisons. */
11991 zero_extended = ((code == EQ || code == NE
11992 || code == GEU || code == GTU
11993 || code == LEU || code == LTU)
11994 && (nonzero_bits (op0, tmode)
11995 & ~GET_MODE_MASK (mode)) == 0
11996 && ((CONST_INT_P (op1)
11997 || (nonzero_bits (op1, tmode)
11998 & ~GET_MODE_MASK (mode)) == 0)));
12001 || ((num_sign_bit_copies (op0, tmode)
12002 > (unsigned int) (GET_MODE_BITSIZE (tmode)
12003 - GET_MODE_BITSIZE (mode)))
12004 && (num_sign_bit_copies (op1, tmode)
12005 > (unsigned int) (GET_MODE_BITSIZE (tmode)
12006 - GET_MODE_BITSIZE (mode)))))
12008 /* If OP0 is an AND and we don't have an AND in MODE either,
12009 make a new AND in the proper mode. */
12010 if (GET_CODE (op0) == AND
12011 && !have_insn_for (AND, mode))
12012 op0 = simplify_gen_binary (AND, tmode,
12013 gen_lowpart (tmode,
12015 gen_lowpart (tmode,
12021 op0 = simplify_gen_unary (ZERO_EXTEND, tmode, op0, mode);
12022 op1 = simplify_gen_unary (ZERO_EXTEND, tmode, op1, mode);
12026 op0 = simplify_gen_unary (SIGN_EXTEND, tmode, op0, mode);
12027 op1 = simplify_gen_unary (SIGN_EXTEND, tmode, op1, mode);
12034 #ifdef CANONICALIZE_COMPARISON
12035 /* If this machine only supports a subset of valid comparisons, see if we
12036 can convert an unsupported one into a supported one. */
12037 CANONICALIZE_COMPARISON (code, op0, op1);
12046 /* Utility function for record_value_for_reg. Count number of
12051 enum rtx_code code = GET_CODE (x);
12055 if (GET_RTX_CLASS (code) == '2'
12056 || GET_RTX_CLASS (code) == 'c')
12058 rtx x0 = XEXP (x, 0);
12059 rtx x1 = XEXP (x, 1);
12062 return 1 + 2 * count_rtxs (x0);
12064 if ((GET_RTX_CLASS (GET_CODE (x1)) == '2'
12065 || GET_RTX_CLASS (GET_CODE (x1)) == 'c')
12066 && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1)))
12067 return 2 + 2 * count_rtxs (x0)
12068 + count_rtxs (x == XEXP (x1, 0)
12069 ? XEXP (x1, 1) : XEXP (x1, 0));
12071 if ((GET_RTX_CLASS (GET_CODE (x0)) == '2'
12072 || GET_RTX_CLASS (GET_CODE (x0)) == 'c')
12073 && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1)))
12074 return 2 + 2 * count_rtxs (x1)
12075 + count_rtxs (x == XEXP (x0, 0)
12076 ? XEXP (x0, 1) : XEXP (x0, 0));
12079 fmt = GET_RTX_FORMAT (code);
12080 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
12082 ret += count_rtxs (XEXP (x, i));
12083 else if (fmt[i] == 'E')
12084 for (j = 0; j < XVECLEN (x, i); j++)
12085 ret += count_rtxs (XVECEXP (x, i, j));
12090 /* Utility function for following routine. Called when X is part of a value
12091 being stored into last_set_value. Sets last_set_table_tick
12092 for each register mentioned. Similar to mention_regs in cse.c */
12095 update_table_tick (rtx x)
12097 enum rtx_code code = GET_CODE (x);
12098 const char *fmt = GET_RTX_FORMAT (code);
12103 unsigned int regno = REGNO (x);
12104 unsigned int endregno = END_REGNO (x);
12107 for (r = regno; r < endregno; r++)
12109 reg_stat_type *rsp = VEC_index (reg_stat_type, reg_stat, r);
12110 rsp->last_set_table_tick = label_tick;
12116 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
12119 /* Check for identical subexpressions. If x contains
12120 identical subexpression we only have to traverse one of
12122 if (i == 0 && ARITHMETIC_P (x))
12124 /* Note that at this point x1 has already been
12126 rtx x0 = XEXP (x, 0);
12127 rtx x1 = XEXP (x, 1);
12129 /* If x0 and x1 are identical then there is no need to
12134 /* If x0 is identical to a subexpression of x1 then while
12135 processing x1, x0 has already been processed. Thus we
12136 are done with x. */
12137 if (ARITHMETIC_P (x1)
12138 && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1)))
12141 /* If x1 is identical to a subexpression of x0 then we
12142 still have to process the rest of x0. */
12143 if (ARITHMETIC_P (x0)
12144 && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1)))
12146 update_table_tick (XEXP (x0, x1 == XEXP (x0, 0) ? 1 : 0));
12151 update_table_tick (XEXP (x, i));
12153 else if (fmt[i] == 'E')
12154 for (j = 0; j < XVECLEN (x, i); j++)
12155 update_table_tick (XVECEXP (x, i, j));
12158 /* Record that REG is set to VALUE in insn INSN. If VALUE is zero, we
12159 are saying that the register is clobbered and we no longer know its
12160 value. If INSN is zero, don't update reg_stat[].last_set; this is
12161 only permitted with VALUE also zero and is used to invalidate the
12165 record_value_for_reg (rtx reg, rtx insn, rtx value)
12167 unsigned int regno = REGNO (reg);
12168 unsigned int endregno = END_REGNO (reg);
12170 reg_stat_type *rsp;
12172 /* If VALUE contains REG and we have a previous value for REG, substitute
12173 the previous value. */
12174 if (value && insn && reg_overlap_mentioned_p (reg, value))
12178 /* Set things up so get_last_value is allowed to see anything set up to
12180 subst_low_luid = DF_INSN_LUID (insn);
12181 tem = get_last_value (reg);
12183 /* If TEM is simply a binary operation with two CLOBBERs as operands,
12184 it isn't going to be useful and will take a lot of time to process,
12185 so just use the CLOBBER. */
12189 if (ARITHMETIC_P (tem)
12190 && GET_CODE (XEXP (tem, 0)) == CLOBBER
12191 && GET_CODE (XEXP (tem, 1)) == CLOBBER)
12192 tem = XEXP (tem, 0);
12193 else if (count_occurrences (value, reg, 1) >= 2)
12195 /* If there are two or more occurrences of REG in VALUE,
12196 prevent the value from growing too much. */
12197 if (count_rtxs (tem) > MAX_LAST_VALUE_RTL)
12198 tem = gen_rtx_CLOBBER (GET_MODE (tem), const0_rtx);
12201 value = replace_rtx (copy_rtx (value), reg, tem);
12205 /* For each register modified, show we don't know its value, that
12206 we don't know about its bitwise content, that its value has been
12207 updated, and that we don't know the location of the death of the
12209 for (i = regno; i < endregno; i++)
12211 rsp = VEC_index (reg_stat_type, reg_stat, i);
12214 rsp->last_set = insn;
12216 rsp->last_set_value = 0;
12217 rsp->last_set_mode = VOIDmode;
12218 rsp->last_set_nonzero_bits = 0;
12219 rsp->last_set_sign_bit_copies = 0;
12220 rsp->last_death = 0;
12221 rsp->truncated_to_mode = VOIDmode;
12224 /* Mark registers that are being referenced in this value. */
12226 update_table_tick (value);
12228 /* Now update the status of each register being set.
12229 If someone is using this register in this block, set this register
12230 to invalid since we will get confused between the two lives in this
12231 basic block. This makes using this register always invalid. In cse, we
12232 scan the table to invalidate all entries using this register, but this
12233 is too much work for us. */
12235 for (i = regno; i < endregno; i++)
12237 rsp = VEC_index (reg_stat_type, reg_stat, i);
12238 rsp->last_set_label = label_tick;
12240 || (value && rsp->last_set_table_tick >= label_tick_ebb_start))
12241 rsp->last_set_invalid = 1;
12243 rsp->last_set_invalid = 0;
12246 /* The value being assigned might refer to X (like in "x++;"). In that
12247 case, we must replace it with (clobber (const_int 0)) to prevent
12249 rsp = VEC_index (reg_stat_type, reg_stat, regno);
12250 if (value && !get_last_value_validate (&value, insn, label_tick, 0))
12252 value = copy_rtx (value);
12253 if (!get_last_value_validate (&value, insn, label_tick, 1))
12257 /* For the main register being modified, update the value, the mode, the
12258 nonzero bits, and the number of sign bit copies. */
12260 rsp->last_set_value = value;
12264 enum machine_mode mode = GET_MODE (reg);
12265 subst_low_luid = DF_INSN_LUID (insn);
12266 rsp->last_set_mode = mode;
12267 if (GET_MODE_CLASS (mode) == MODE_INT
12268 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
12269 mode = nonzero_bits_mode;
12270 rsp->last_set_nonzero_bits = nonzero_bits (value, mode);
12271 rsp->last_set_sign_bit_copies
12272 = num_sign_bit_copies (value, GET_MODE (reg));
12276 /* Called via note_stores from record_dead_and_set_regs to handle one
12277 SET or CLOBBER in an insn. DATA is the instruction in which the
12278 set is occurring. */
12281 record_dead_and_set_regs_1 (rtx dest, const_rtx setter, void *data)
12283 rtx record_dead_insn = (rtx) data;
12285 if (GET_CODE (dest) == SUBREG)
12286 dest = SUBREG_REG (dest);
12288 if (!record_dead_insn)
12291 record_value_for_reg (dest, NULL_RTX, NULL_RTX);
12297 /* If we are setting the whole register, we know its value. Otherwise
12298 show that we don't know the value. We can handle SUBREG in
12300 if (GET_CODE (setter) == SET && dest == SET_DEST (setter))
12301 record_value_for_reg (dest, record_dead_insn, SET_SRC (setter));
12302 else if (GET_CODE (setter) == SET
12303 && GET_CODE (SET_DEST (setter)) == SUBREG
12304 && SUBREG_REG (SET_DEST (setter)) == dest
12305 && GET_MODE_BITSIZE (GET_MODE (dest)) <= BITS_PER_WORD
12306 && subreg_lowpart_p (SET_DEST (setter)))
12307 record_value_for_reg (dest, record_dead_insn,
12308 gen_lowpart (GET_MODE (dest),
12309 SET_SRC (setter)));
12311 record_value_for_reg (dest, record_dead_insn, NULL_RTX);
12313 else if (MEM_P (dest)
12314 /* Ignore pushes, they clobber nothing. */
12315 && ! push_operand (dest, GET_MODE (dest)))
12316 mem_last_set = DF_INSN_LUID (record_dead_insn);
12319 /* Update the records of when each REG was most recently set or killed
12320 for the things done by INSN. This is the last thing done in processing
12321 INSN in the combiner loop.
12323 We update reg_stat[], in particular fields last_set, last_set_value,
12324 last_set_mode, last_set_nonzero_bits, last_set_sign_bit_copies,
12325 last_death, and also the similar information mem_last_set (which insn
12326 most recently modified memory) and last_call_luid (which insn was the
12327 most recent subroutine call). */
12330 record_dead_and_set_regs (rtx insn)
12335 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
12337 if (REG_NOTE_KIND (link) == REG_DEAD
12338 && REG_P (XEXP (link, 0)))
12340 unsigned int regno = REGNO (XEXP (link, 0));
12341 unsigned int endregno = END_REGNO (XEXP (link, 0));
12343 for (i = regno; i < endregno; i++)
12345 reg_stat_type *rsp;
12347 rsp = VEC_index (reg_stat_type, reg_stat, i);
12348 rsp->last_death = insn;
12351 else if (REG_NOTE_KIND (link) == REG_INC)
12352 record_value_for_reg (XEXP (link, 0), insn, NULL_RTX);
12357 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
12358 if (TEST_HARD_REG_BIT (regs_invalidated_by_call, i))
12360 reg_stat_type *rsp;
12362 rsp = VEC_index (reg_stat_type, reg_stat, i);
12363 rsp->last_set_invalid = 1;
12364 rsp->last_set = insn;
12365 rsp->last_set_value = 0;
12366 rsp->last_set_mode = VOIDmode;
12367 rsp->last_set_nonzero_bits = 0;
12368 rsp->last_set_sign_bit_copies = 0;
12369 rsp->last_death = 0;
12370 rsp->truncated_to_mode = VOIDmode;
12373 last_call_luid = mem_last_set = DF_INSN_LUID (insn);
12375 /* We can't combine into a call pattern. Remember, though, that
12376 the return value register is set at this LUID. We could
12377 still replace a register with the return value from the
12378 wrong subroutine call! */
12379 note_stores (PATTERN (insn), record_dead_and_set_regs_1, NULL_RTX);
12382 note_stores (PATTERN (insn), record_dead_and_set_regs_1, insn);
12385 /* If a SUBREG has the promoted bit set, it is in fact a property of the
12386 register present in the SUBREG, so for each such SUBREG go back and
12387 adjust nonzero and sign bit information of the registers that are
12388 known to have some zero/sign bits set.
12390 This is needed because when combine blows the SUBREGs away, the
12391 information on zero/sign bits is lost and further combines can be
12392 missed because of that. */
12395 record_promoted_value (rtx insn, rtx subreg)
12397 struct insn_link *links;
12399 unsigned int regno = REGNO (SUBREG_REG (subreg));
12400 enum machine_mode mode = GET_MODE (subreg);
12402 if (GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT)
12405 for (links = LOG_LINKS (insn); links;)
12407 reg_stat_type *rsp;
12409 insn = links->insn;
12410 set = single_set (insn);
12412 if (! set || !REG_P (SET_DEST (set))
12413 || REGNO (SET_DEST (set)) != regno
12414 || GET_MODE (SET_DEST (set)) != GET_MODE (SUBREG_REG (subreg)))
12416 links = links->next;
12420 rsp = VEC_index (reg_stat_type, reg_stat, regno);
12421 if (rsp->last_set == insn)
12423 if (SUBREG_PROMOTED_UNSIGNED_P (subreg) > 0)
12424 rsp->last_set_nonzero_bits &= GET_MODE_MASK (mode);
12427 if (REG_P (SET_SRC (set)))
12429 regno = REGNO (SET_SRC (set));
12430 links = LOG_LINKS (insn);
12437 /* Check if X, a register, is known to contain a value already
12438 truncated to MODE. In this case we can use a subreg to refer to
12439 the truncated value even though in the generic case we would need
12440 an explicit truncation. */
12443 reg_truncated_to_mode (enum machine_mode mode, const_rtx x)
12445 reg_stat_type *rsp = VEC_index (reg_stat_type, reg_stat, REGNO (x));
12446 enum machine_mode truncated = rsp->truncated_to_mode;
12449 || rsp->truncation_label < label_tick_ebb_start)
12451 if (GET_MODE_SIZE (truncated) <= GET_MODE_SIZE (mode))
12453 if (TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode),
12454 GET_MODE_BITSIZE (truncated)))
12459 /* Callback for for_each_rtx. If *P is a hard reg or a subreg record the mode
12460 that the register is accessed in. For non-TRULY_NOOP_TRUNCATION targets we
12461 might be able to turn a truncate into a subreg using this information.
12462 Return -1 if traversing *P is complete or 0 otherwise. */
12465 record_truncated_value (rtx *p, void *data ATTRIBUTE_UNUSED)
12468 enum machine_mode truncated_mode;
12469 reg_stat_type *rsp;
12471 if (GET_CODE (x) == SUBREG && REG_P (SUBREG_REG (x)))
12473 enum machine_mode original_mode = GET_MODE (SUBREG_REG (x));
12474 truncated_mode = GET_MODE (x);
12476 if (GET_MODE_SIZE (original_mode) <= GET_MODE_SIZE (truncated_mode))
12479 if (TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (truncated_mode),
12480 GET_MODE_BITSIZE (original_mode)))
12483 x = SUBREG_REG (x);
12485 /* ??? For hard-regs we now record everything. We might be able to
12486 optimize this using last_set_mode. */
12487 else if (REG_P (x) && REGNO (x) < FIRST_PSEUDO_REGISTER)
12488 truncated_mode = GET_MODE (x);
12492 rsp = VEC_index (reg_stat_type, reg_stat, REGNO (x));
12493 if (rsp->truncated_to_mode == 0
12494 || rsp->truncation_label < label_tick_ebb_start
12495 || (GET_MODE_SIZE (truncated_mode)
12496 < GET_MODE_SIZE (rsp->truncated_to_mode)))
12498 rsp->truncated_to_mode = truncated_mode;
12499 rsp->truncation_label = label_tick;
12505 /* Callback for note_uses. Find hardregs and subregs of pseudos and
12506 the modes they are used in. This can help truning TRUNCATEs into
12510 record_truncated_values (rtx *x, void *data ATTRIBUTE_UNUSED)
12512 for_each_rtx (x, record_truncated_value, NULL);
12515 /* Scan X for promoted SUBREGs. For each one found,
12516 note what it implies to the registers used in it. */
12519 check_promoted_subreg (rtx insn, rtx x)
12521 if (GET_CODE (x) == SUBREG
12522 && SUBREG_PROMOTED_VAR_P (x)
12523 && REG_P (SUBREG_REG (x)))
12524 record_promoted_value (insn, x);
12527 const char *format = GET_RTX_FORMAT (GET_CODE (x));
12530 for (i = 0; i < GET_RTX_LENGTH (GET_CODE (x)); i++)
12534 check_promoted_subreg (insn, XEXP (x, i));
12538 if (XVEC (x, i) != 0)
12539 for (j = 0; j < XVECLEN (x, i); j++)
12540 check_promoted_subreg (insn, XVECEXP (x, i, j));
12546 /* Verify that all the registers and memory references mentioned in *LOC are
12547 still valid. *LOC was part of a value set in INSN when label_tick was
12548 equal to TICK. Return 0 if some are not. If REPLACE is nonzero, replace
12549 the invalid references with (clobber (const_int 0)) and return 1. This
12550 replacement is useful because we often can get useful information about
12551 the form of a value (e.g., if it was produced by a shift that always
12552 produces -1 or 0) even though we don't know exactly what registers it
12553 was produced from. */
12556 get_last_value_validate (rtx *loc, rtx insn, int tick, int replace)
12559 const char *fmt = GET_RTX_FORMAT (GET_CODE (x));
12560 int len = GET_RTX_LENGTH (GET_CODE (x));
12565 unsigned int regno = REGNO (x);
12566 unsigned int endregno = END_REGNO (x);
12569 for (j = regno; j < endregno; j++)
12571 reg_stat_type *rsp = VEC_index (reg_stat_type, reg_stat, j);
12572 if (rsp->last_set_invalid
12573 /* If this is a pseudo-register that was only set once and not
12574 live at the beginning of the function, it is always valid. */
12575 || (! (regno >= FIRST_PSEUDO_REGISTER
12576 && REG_N_SETS (regno) == 1
12577 && (!REGNO_REG_SET_P
12578 (DF_LR_IN (ENTRY_BLOCK_PTR->next_bb), regno)))
12579 && rsp->last_set_label > tick))
12582 *loc = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
12589 /* If this is a memory reference, make sure that there were no stores after
12590 it that might have clobbered the value. We don't have alias info, so we
12591 assume any store invalidates it. Moreover, we only have local UIDs, so
12592 we also assume that there were stores in the intervening basic blocks. */
12593 else if (MEM_P (x) && !MEM_READONLY_P (x)
12594 && (tick != label_tick || DF_INSN_LUID (insn) <= mem_last_set))
12597 *loc = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
12601 for (i = 0; i < len; i++)
12605 /* Check for identical subexpressions. If x contains
12606 identical subexpression we only have to traverse one of
12608 if (i == 1 && ARITHMETIC_P (x))
12610 /* Note that at this point x0 has already been checked
12611 and found valid. */
12612 rtx x0 = XEXP (x, 0);
12613 rtx x1 = XEXP (x, 1);
12615 /* If x0 and x1 are identical then x is also valid. */
12619 /* If x1 is identical to a subexpression of x0 then
12620 while checking x0, x1 has already been checked. Thus
12621 it is valid and so as x. */
12622 if (ARITHMETIC_P (x0)
12623 && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1)))
12626 /* If x0 is identical to a subexpression of x1 then x is
12627 valid iff the rest of x1 is valid. */
12628 if (ARITHMETIC_P (x1)
12629 && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1)))
12631 get_last_value_validate (&XEXP (x1,
12632 x0 == XEXP (x1, 0) ? 1 : 0),
12633 insn, tick, replace);
12636 if (get_last_value_validate (&XEXP (x, i), insn, tick,
12640 else if (fmt[i] == 'E')
12641 for (j = 0; j < XVECLEN (x, i); j++)
12642 if (get_last_value_validate (&XVECEXP (x, i, j),
12643 insn, tick, replace) == 0)
12647 /* If we haven't found a reason for it to be invalid, it is valid. */
12651 /* Get the last value assigned to X, if known. Some registers
12652 in the value may be replaced with (clobber (const_int 0)) if their value
12653 is known longer known reliably. */
12656 get_last_value (const_rtx x)
12658 unsigned int regno;
12660 reg_stat_type *rsp;
12662 /* If this is a non-paradoxical SUBREG, get the value of its operand and
12663 then convert it to the desired mode. If this is a paradoxical SUBREG,
12664 we cannot predict what values the "extra" bits might have. */
12665 if (GET_CODE (x) == SUBREG
12666 && subreg_lowpart_p (x)
12667 && (GET_MODE_SIZE (GET_MODE (x))
12668 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
12669 && (value = get_last_value (SUBREG_REG (x))) != 0)
12670 return gen_lowpart (GET_MODE (x), value);
12676 rsp = VEC_index (reg_stat_type, reg_stat, regno);
12677 value = rsp->last_set_value;
12679 /* If we don't have a value, or if it isn't for this basic block and
12680 it's either a hard register, set more than once, or it's a live
12681 at the beginning of the function, return 0.
12683 Because if it's not live at the beginning of the function then the reg
12684 is always set before being used (is never used without being set).
12685 And, if it's set only once, and it's always set before use, then all
12686 uses must have the same last value, even if it's not from this basic
12690 || (rsp->last_set_label < label_tick_ebb_start
12691 && (regno < FIRST_PSEUDO_REGISTER
12692 || REG_N_SETS (regno) != 1
12694 (DF_LR_IN (ENTRY_BLOCK_PTR->next_bb), regno))))
12697 /* If the value was set in a later insn than the ones we are processing,
12698 we can't use it even if the register was only set once. */
12699 if (rsp->last_set_label == label_tick
12700 && DF_INSN_LUID (rsp->last_set) >= subst_low_luid)
12703 /* If the value has all its registers valid, return it. */
12704 if (get_last_value_validate (&value, rsp->last_set, rsp->last_set_label, 0))
12707 /* Otherwise, make a copy and replace any invalid register with
12708 (clobber (const_int 0)). If that fails for some reason, return 0. */
12710 value = copy_rtx (value);
12711 if (get_last_value_validate (&value, rsp->last_set, rsp->last_set_label, 1))
12717 /* Return nonzero if expression X refers to a REG or to memory
12718 that is set in an instruction more recent than FROM_LUID. */
12721 use_crosses_set_p (const_rtx x, int from_luid)
12725 enum rtx_code code = GET_CODE (x);
12729 unsigned int regno = REGNO (x);
12730 unsigned endreg = END_REGNO (x);
12732 #ifdef PUSH_ROUNDING
12733 /* Don't allow uses of the stack pointer to be moved,
12734 because we don't know whether the move crosses a push insn. */
12735 if (regno == STACK_POINTER_REGNUM && PUSH_ARGS)
12738 for (; regno < endreg; regno++)
12740 reg_stat_type *rsp = VEC_index (reg_stat_type, reg_stat, regno);
12742 && rsp->last_set_label == label_tick
12743 && DF_INSN_LUID (rsp->last_set) > from_luid)
12749 if (code == MEM && mem_last_set > from_luid)
12752 fmt = GET_RTX_FORMAT (code);
12754 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
12759 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
12760 if (use_crosses_set_p (XVECEXP (x, i, j), from_luid))
12763 else if (fmt[i] == 'e'
12764 && use_crosses_set_p (XEXP (x, i), from_luid))
12770 /* Define three variables used for communication between the following
12773 static unsigned int reg_dead_regno, reg_dead_endregno;
12774 static int reg_dead_flag;
12776 /* Function called via note_stores from reg_dead_at_p.
12778 If DEST is within [reg_dead_regno, reg_dead_endregno), set
12779 reg_dead_flag to 1 if X is a CLOBBER and to -1 it is a SET. */
12782 reg_dead_at_p_1 (rtx dest, const_rtx x, void *data ATTRIBUTE_UNUSED)
12784 unsigned int regno, endregno;
12789 regno = REGNO (dest);
12790 endregno = END_REGNO (dest);
12791 if (reg_dead_endregno > regno && reg_dead_regno < endregno)
12792 reg_dead_flag = (GET_CODE (x) == CLOBBER) ? 1 : -1;
12795 /* Return nonzero if REG is known to be dead at INSN.
12797 We scan backwards from INSN. If we hit a REG_DEAD note or a CLOBBER
12798 referencing REG, it is dead. If we hit a SET referencing REG, it is
12799 live. Otherwise, see if it is live or dead at the start of the basic
12800 block we are in. Hard regs marked as being live in NEWPAT_USED_REGS
12801 must be assumed to be always live. */
12804 reg_dead_at_p (rtx reg, rtx insn)
12809 /* Set variables for reg_dead_at_p_1. */
12810 reg_dead_regno = REGNO (reg);
12811 reg_dead_endregno = END_REGNO (reg);
12815 /* Check that reg isn't mentioned in NEWPAT_USED_REGS. For fixed registers
12816 we allow the machine description to decide whether use-and-clobber
12817 patterns are OK. */
12818 if (reg_dead_regno < FIRST_PSEUDO_REGISTER)
12820 for (i = reg_dead_regno; i < reg_dead_endregno; i++)
12821 if (!fixed_regs[i] && TEST_HARD_REG_BIT (newpat_used_regs, i))
12825 /* Scan backwards until we find a REG_DEAD note, SET, CLOBBER, or
12826 beginning of basic block. */
12827 block = BLOCK_FOR_INSN (insn);
12832 note_stores (PATTERN (insn), reg_dead_at_p_1, NULL);
12834 return reg_dead_flag == 1 ? 1 : 0;
12836 if (find_regno_note (insn, REG_DEAD, reg_dead_regno))
12840 if (insn == BB_HEAD (block))
12843 insn = PREV_INSN (insn);
12846 /* Look at live-in sets for the basic block that we were in. */
12847 for (i = reg_dead_regno; i < reg_dead_endregno; i++)
12848 if (REGNO_REG_SET_P (df_get_live_in (block), i))
12854 /* Note hard registers in X that are used. */
12857 mark_used_regs_combine (rtx x)
12859 RTX_CODE code = GET_CODE (x);
12860 unsigned int regno;
12873 case ADDR_DIFF_VEC:
12876 /* CC0 must die in the insn after it is set, so we don't need to take
12877 special note of it here. */
12883 /* If we are clobbering a MEM, mark any hard registers inside the
12884 address as used. */
12885 if (MEM_P (XEXP (x, 0)))
12886 mark_used_regs_combine (XEXP (XEXP (x, 0), 0));
12891 /* A hard reg in a wide mode may really be multiple registers.
12892 If so, mark all of them just like the first. */
12893 if (regno < FIRST_PSEUDO_REGISTER)
12895 /* None of this applies to the stack, frame or arg pointers. */
12896 if (regno == STACK_POINTER_REGNUM
12897 #if !HARD_FRAME_POINTER_IS_FRAME_POINTER
12898 || regno == HARD_FRAME_POINTER_REGNUM
12900 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
12901 || (regno == ARG_POINTER_REGNUM && fixed_regs[regno])
12903 || regno == FRAME_POINTER_REGNUM)
12906 add_to_hard_reg_set (&newpat_used_regs, GET_MODE (x), regno);
12912 /* If setting a MEM, or a SUBREG of a MEM, then note any hard regs in
12914 rtx testreg = SET_DEST (x);
12916 while (GET_CODE (testreg) == SUBREG
12917 || GET_CODE (testreg) == ZERO_EXTRACT
12918 || GET_CODE (testreg) == STRICT_LOW_PART)
12919 testreg = XEXP (testreg, 0);
12921 if (MEM_P (testreg))
12922 mark_used_regs_combine (XEXP (testreg, 0));
12924 mark_used_regs_combine (SET_SRC (x));
12932 /* Recursively scan the operands of this expression. */
12935 const char *fmt = GET_RTX_FORMAT (code);
12937 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
12940 mark_used_regs_combine (XEXP (x, i));
12941 else if (fmt[i] == 'E')
12945 for (j = 0; j < XVECLEN (x, i); j++)
12946 mark_used_regs_combine (XVECEXP (x, i, j));
12952 /* Remove register number REGNO from the dead registers list of INSN.
12954 Return the note used to record the death, if there was one. */
12957 remove_death (unsigned int regno, rtx insn)
12959 rtx note = find_regno_note (insn, REG_DEAD, regno);
12962 remove_note (insn, note);
12967 /* For each register (hardware or pseudo) used within expression X, if its
12968 death is in an instruction with luid between FROM_LUID (inclusive) and
12969 TO_INSN (exclusive), put a REG_DEAD note for that register in the
12970 list headed by PNOTES.
12972 That said, don't move registers killed by maybe_kill_insn.
12974 This is done when X is being merged by combination into TO_INSN. These
12975 notes will then be distributed as needed. */
12978 move_deaths (rtx x, rtx maybe_kill_insn, int from_luid, rtx to_insn,
12983 enum rtx_code code = GET_CODE (x);
12987 unsigned int regno = REGNO (x);
12988 rtx where_dead = VEC_index (reg_stat_type, reg_stat, regno)->last_death;
12990 /* Don't move the register if it gets killed in between from and to. */
12991 if (maybe_kill_insn && reg_set_p (x, maybe_kill_insn)
12992 && ! reg_referenced_p (x, maybe_kill_insn))
12996 && BLOCK_FOR_INSN (where_dead) == BLOCK_FOR_INSN (to_insn)
12997 && DF_INSN_LUID (where_dead) >= from_luid
12998 && DF_INSN_LUID (where_dead) < DF_INSN_LUID (to_insn))
13000 rtx note = remove_death (regno, where_dead);
13002 /* It is possible for the call above to return 0. This can occur
13003 when last_death points to I2 or I1 that we combined with.
13004 In that case make a new note.
13006 We must also check for the case where X is a hard register
13007 and NOTE is a death note for a range of hard registers
13008 including X. In that case, we must put REG_DEAD notes for
13009 the remaining registers in place of NOTE. */
13011 if (note != 0 && regno < FIRST_PSEUDO_REGISTER
13012 && (GET_MODE_SIZE (GET_MODE (XEXP (note, 0)))
13013 > GET_MODE_SIZE (GET_MODE (x))))
13015 unsigned int deadregno = REGNO (XEXP (note, 0));
13016 unsigned int deadend = END_HARD_REGNO (XEXP (note, 0));
13017 unsigned int ourend = END_HARD_REGNO (x);
13020 for (i = deadregno; i < deadend; i++)
13021 if (i < regno || i >= ourend)
13022 add_reg_note (where_dead, REG_DEAD, regno_reg_rtx[i]);
13025 /* If we didn't find any note, or if we found a REG_DEAD note that
13026 covers only part of the given reg, and we have a multi-reg hard
13027 register, then to be safe we must check for REG_DEAD notes
13028 for each register other than the first. They could have
13029 their own REG_DEAD notes lying around. */
13030 else if ((note == 0
13032 && (GET_MODE_SIZE (GET_MODE (XEXP (note, 0)))
13033 < GET_MODE_SIZE (GET_MODE (x)))))
13034 && regno < FIRST_PSEUDO_REGISTER
13035 && hard_regno_nregs[regno][GET_MODE (x)] > 1)
13037 unsigned int ourend = END_HARD_REGNO (x);
13038 unsigned int i, offset;
13042 offset = hard_regno_nregs[regno][GET_MODE (XEXP (note, 0))];
13046 for (i = regno + offset; i < ourend; i++)
13047 move_deaths (regno_reg_rtx[i],
13048 maybe_kill_insn, from_luid, to_insn, &oldnotes);
13051 if (note != 0 && GET_MODE (XEXP (note, 0)) == GET_MODE (x))
13053 XEXP (note, 1) = *pnotes;
13057 *pnotes = alloc_reg_note (REG_DEAD, x, *pnotes);
13063 else if (GET_CODE (x) == SET)
13065 rtx dest = SET_DEST (x);
13067 move_deaths (SET_SRC (x), maybe_kill_insn, from_luid, to_insn, pnotes);
13069 /* In the case of a ZERO_EXTRACT, a STRICT_LOW_PART, or a SUBREG
13070 that accesses one word of a multi-word item, some
13071 piece of everything register in the expression is used by
13072 this insn, so remove any old death. */
13073 /* ??? So why do we test for equality of the sizes? */
13075 if (GET_CODE (dest) == ZERO_EXTRACT
13076 || GET_CODE (dest) == STRICT_LOW_PART
13077 || (GET_CODE (dest) == SUBREG
13078 && (((GET_MODE_SIZE (GET_MODE (dest))
13079 + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
13080 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (dest)))
13081 + UNITS_PER_WORD - 1) / UNITS_PER_WORD))))
13083 move_deaths (dest, maybe_kill_insn, from_luid, to_insn, pnotes);
13087 /* If this is some other SUBREG, we know it replaces the entire
13088 value, so use that as the destination. */
13089 if (GET_CODE (dest) == SUBREG)
13090 dest = SUBREG_REG (dest);
13092 /* If this is a MEM, adjust deaths of anything used in the address.
13093 For a REG (the only other possibility), the entire value is
13094 being replaced so the old value is not used in this insn. */
13097 move_deaths (XEXP (dest, 0), maybe_kill_insn, from_luid,
13102 else if (GET_CODE (x) == CLOBBER)
13105 len = GET_RTX_LENGTH (code);
13106 fmt = GET_RTX_FORMAT (code);
13108 for (i = 0; i < len; i++)
13113 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
13114 move_deaths (XVECEXP (x, i, j), maybe_kill_insn, from_luid,
13117 else if (fmt[i] == 'e')
13118 move_deaths (XEXP (x, i), maybe_kill_insn, from_luid, to_insn, pnotes);
13122 /* Return 1 if X is the target of a bit-field assignment in BODY, the
13123 pattern of an insn. X must be a REG. */
13126 reg_bitfield_target_p (rtx x, rtx body)
13130 if (GET_CODE (body) == SET)
13132 rtx dest = SET_DEST (body);
13134 unsigned int regno, tregno, endregno, endtregno;
13136 if (GET_CODE (dest) == ZERO_EXTRACT)
13137 target = XEXP (dest, 0);
13138 else if (GET_CODE (dest) == STRICT_LOW_PART)
13139 target = SUBREG_REG (XEXP (dest, 0));
13143 if (GET_CODE (target) == SUBREG)
13144 target = SUBREG_REG (target);
13146 if (!REG_P (target))
13149 tregno = REGNO (target), regno = REGNO (x);
13150 if (tregno >= FIRST_PSEUDO_REGISTER || regno >= FIRST_PSEUDO_REGISTER)
13151 return target == x;
13153 endtregno = end_hard_regno (GET_MODE (target), tregno);
13154 endregno = end_hard_regno (GET_MODE (x), regno);
13156 return endregno > tregno && regno < endtregno;
13159 else if (GET_CODE (body) == PARALLEL)
13160 for (i = XVECLEN (body, 0) - 1; i >= 0; i--)
13161 if (reg_bitfield_target_p (x, XVECEXP (body, 0, i)))
13167 /* Given a chain of REG_NOTES originally from FROM_INSN, try to place them
13168 as appropriate. I3 and I2 are the insns resulting from the combination
13169 insns including FROM (I2 may be zero).
13171 ELIM_I2 and ELIM_I1 are either zero or registers that we know will
13172 not need REG_DEAD notes because they are being substituted for. This
13173 saves searching in the most common cases.
13175 Each note in the list is either ignored or placed on some insns, depending
13176 on the type of note. */
13179 distribute_notes (rtx notes, rtx from_insn, rtx i3, rtx i2, rtx elim_i2,
13180 rtx elim_i1, rtx elim_i0)
13182 rtx note, next_note;
13185 for (note = notes; note; note = next_note)
13187 rtx place = 0, place2 = 0;
13189 next_note = XEXP (note, 1);
13190 switch (REG_NOTE_KIND (note))
13194 /* Doesn't matter much where we put this, as long as it's somewhere.
13195 It is preferable to keep these notes on branches, which is most
13196 likely to be i3. */
13200 case REG_NON_LOCAL_GOTO:
13205 gcc_assert (i2 && JUMP_P (i2));
13210 case REG_EH_REGION:
13211 /* These notes must remain with the call or trapping instruction. */
13214 else if (i2 && CALL_P (i2))
13218 gcc_assert (cfun->can_throw_non_call_exceptions);
13219 if (may_trap_p (i3))
13221 else if (i2 && may_trap_p (i2))
13223 /* ??? Otherwise assume we've combined things such that we
13224 can now prove that the instructions can't trap. Drop the
13225 note in this case. */
13231 /* These notes must remain with the call. It should not be
13232 possible for both I2 and I3 to be a call. */
13237 gcc_assert (i2 && CALL_P (i2));
13243 /* Any clobbers for i3 may still exist, and so we must process
13244 REG_UNUSED notes from that insn.
13246 Any clobbers from i2 or i1 can only exist if they were added by
13247 recog_for_combine. In that case, recog_for_combine created the
13248 necessary REG_UNUSED notes. Trying to keep any original
13249 REG_UNUSED notes from these insns can cause incorrect output
13250 if it is for the same register as the original i3 dest.
13251 In that case, we will notice that the register is set in i3,
13252 and then add a REG_UNUSED note for the destination of i3, which
13253 is wrong. However, it is possible to have REG_UNUSED notes from
13254 i2 or i1 for register which were both used and clobbered, so
13255 we keep notes from i2 or i1 if they will turn into REG_DEAD
13258 /* If this register is set or clobbered in I3, put the note there
13259 unless there is one already. */
13260 if (reg_set_p (XEXP (note, 0), PATTERN (i3)))
13262 if (from_insn != i3)
13265 if (! (REG_P (XEXP (note, 0))
13266 ? find_regno_note (i3, REG_UNUSED, REGNO (XEXP (note, 0)))
13267 : find_reg_note (i3, REG_UNUSED, XEXP (note, 0))))
13270 /* Otherwise, if this register is used by I3, then this register
13271 now dies here, so we must put a REG_DEAD note here unless there
13273 else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3))
13274 && ! (REG_P (XEXP (note, 0))
13275 ? find_regno_note (i3, REG_DEAD,
13276 REGNO (XEXP (note, 0)))
13277 : find_reg_note (i3, REG_DEAD, XEXP (note, 0))))
13279 PUT_REG_NOTE_KIND (note, REG_DEAD);
13287 /* These notes say something about results of an insn. We can
13288 only support them if they used to be on I3 in which case they
13289 remain on I3. Otherwise they are ignored.
13291 If the note refers to an expression that is not a constant, we
13292 must also ignore the note since we cannot tell whether the
13293 equivalence is still true. It might be possible to do
13294 slightly better than this (we only have a problem if I2DEST
13295 or I1DEST is present in the expression), but it doesn't
13296 seem worth the trouble. */
13298 if (from_insn == i3
13299 && (XEXP (note, 0) == 0 || CONSTANT_P (XEXP (note, 0))))
13304 /* These notes say something about how a register is used. They must
13305 be present on any use of the register in I2 or I3. */
13306 if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3)))
13309 if (i2 && reg_mentioned_p (XEXP (note, 0), PATTERN (i2)))
13318 case REG_LABEL_TARGET:
13319 case REG_LABEL_OPERAND:
13320 /* This can show up in several ways -- either directly in the
13321 pattern, or hidden off in the constant pool with (or without?)
13322 a REG_EQUAL note. */
13323 /* ??? Ignore the without-reg_equal-note problem for now. */
13324 if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3))
13325 || ((tem = find_reg_note (i3, REG_EQUAL, NULL_RTX))
13326 && GET_CODE (XEXP (tem, 0)) == LABEL_REF
13327 && XEXP (XEXP (tem, 0), 0) == XEXP (note, 0)))
13331 && (reg_mentioned_p (XEXP (note, 0), PATTERN (i2))
13332 || ((tem = find_reg_note (i2, REG_EQUAL, NULL_RTX))
13333 && GET_CODE (XEXP (tem, 0)) == LABEL_REF
13334 && XEXP (XEXP (tem, 0), 0) == XEXP (note, 0))))
13342 /* For REG_LABEL_TARGET on a JUMP_P, we prefer to put the note
13343 as a JUMP_LABEL or decrement LABEL_NUSES if it's already
13345 if (place && JUMP_P (place)
13346 && REG_NOTE_KIND (note) == REG_LABEL_TARGET
13347 && (JUMP_LABEL (place) == NULL
13348 || JUMP_LABEL (place) == XEXP (note, 0)))
13350 rtx label = JUMP_LABEL (place);
13353 JUMP_LABEL (place) = XEXP (note, 0);
13354 else if (LABEL_P (label))
13355 LABEL_NUSES (label)--;
13358 if (place2 && JUMP_P (place2)
13359 && REG_NOTE_KIND (note) == REG_LABEL_TARGET
13360 && (JUMP_LABEL (place2) == NULL
13361 || JUMP_LABEL (place2) == XEXP (note, 0)))
13363 rtx label = JUMP_LABEL (place2);
13366 JUMP_LABEL (place2) = XEXP (note, 0);
13367 else if (LABEL_P (label))
13368 LABEL_NUSES (label)--;
13374 /* This note says something about the value of a register prior
13375 to the execution of an insn. It is too much trouble to see
13376 if the note is still correct in all situations. It is better
13377 to simply delete it. */
13381 /* If we replaced the right hand side of FROM_INSN with a
13382 REG_EQUAL note, the original use of the dying register
13383 will not have been combined into I3 and I2. In such cases,
13384 FROM_INSN is guaranteed to be the first of the combined
13385 instructions, so we simply need to search back before
13386 FROM_INSN for the previous use or set of this register,
13387 then alter the notes there appropriately.
13389 If the register is used as an input in I3, it dies there.
13390 Similarly for I2, if it is nonzero and adjacent to I3.
13392 If the register is not used as an input in either I3 or I2
13393 and it is not one of the registers we were supposed to eliminate,
13394 there are two possibilities. We might have a non-adjacent I2
13395 or we might have somehow eliminated an additional register
13396 from a computation. For example, we might have had A & B where
13397 we discover that B will always be zero. In this case we will
13398 eliminate the reference to A.
13400 In both cases, we must search to see if we can find a previous
13401 use of A and put the death note there. */
13404 && from_insn == i2mod
13405 && !reg_overlap_mentioned_p (XEXP (note, 0), i2mod_new_rhs))
13410 && CALL_P (from_insn)
13411 && find_reg_fusage (from_insn, USE, XEXP (note, 0)))
13413 else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3)))
13415 else if (i2 != 0 && next_nonnote_nondebug_insn (i2) == i3
13416 && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
13418 else if ((rtx_equal_p (XEXP (note, 0), elim_i2)
13420 && reg_overlap_mentioned_p (XEXP (note, 0),
13422 || rtx_equal_p (XEXP (note, 0), elim_i1)
13423 || rtx_equal_p (XEXP (note, 0), elim_i0))
13430 basic_block bb = this_basic_block;
13432 for (tem = PREV_INSN (tem); place == 0; tem = PREV_INSN (tem))
13434 if (!NONDEBUG_INSN_P (tem))
13436 if (tem == BB_HEAD (bb))
13441 /* If the register is being set at TEM, see if that is all
13442 TEM is doing. If so, delete TEM. Otherwise, make this
13443 into a REG_UNUSED note instead. Don't delete sets to
13444 global register vars. */
13445 if ((REGNO (XEXP (note, 0)) >= FIRST_PSEUDO_REGISTER
13446 || !global_regs[REGNO (XEXP (note, 0))])
13447 && reg_set_p (XEXP (note, 0), PATTERN (tem)))
13449 rtx set = single_set (tem);
13450 rtx inner_dest = 0;
13452 rtx cc0_setter = NULL_RTX;
13456 for (inner_dest = SET_DEST (set);
13457 (GET_CODE (inner_dest) == STRICT_LOW_PART
13458 || GET_CODE (inner_dest) == SUBREG
13459 || GET_CODE (inner_dest) == ZERO_EXTRACT);
13460 inner_dest = XEXP (inner_dest, 0))
13463 /* Verify that it was the set, and not a clobber that
13464 modified the register.
13466 CC0 targets must be careful to maintain setter/user
13467 pairs. If we cannot delete the setter due to side
13468 effects, mark the user with an UNUSED note instead
13471 if (set != 0 && ! side_effects_p (SET_SRC (set))
13472 && rtx_equal_p (XEXP (note, 0), inner_dest)
13474 && (! reg_mentioned_p (cc0_rtx, SET_SRC (set))
13475 || ((cc0_setter = prev_cc0_setter (tem)) != NULL
13476 && sets_cc0_p (PATTERN (cc0_setter)) > 0))
13480 /* Move the notes and links of TEM elsewhere.
13481 This might delete other dead insns recursively.
13482 First set the pattern to something that won't use
13484 rtx old_notes = REG_NOTES (tem);
13486 PATTERN (tem) = pc_rtx;
13487 REG_NOTES (tem) = NULL;
13489 distribute_notes (old_notes, tem, tem, NULL_RTX,
13490 NULL_RTX, NULL_RTX, NULL_RTX);
13491 distribute_links (LOG_LINKS (tem));
13493 SET_INSN_DELETED (tem);
13498 /* Delete the setter too. */
13501 PATTERN (cc0_setter) = pc_rtx;
13502 old_notes = REG_NOTES (cc0_setter);
13503 REG_NOTES (cc0_setter) = NULL;
13505 distribute_notes (old_notes, cc0_setter,
13506 cc0_setter, NULL_RTX,
13507 NULL_RTX, NULL_RTX, NULL_RTX);
13508 distribute_links (LOG_LINKS (cc0_setter));
13510 SET_INSN_DELETED (cc0_setter);
13511 if (cc0_setter == i2)
13518 PUT_REG_NOTE_KIND (note, REG_UNUSED);
13520 /* If there isn't already a REG_UNUSED note, put one
13521 here. Do not place a REG_DEAD note, even if
13522 the register is also used here; that would not
13523 match the algorithm used in lifetime analysis
13524 and can cause the consistency check in the
13525 scheduler to fail. */
13526 if (! find_regno_note (tem, REG_UNUSED,
13527 REGNO (XEXP (note, 0))))
13532 else if (reg_referenced_p (XEXP (note, 0), PATTERN (tem))
13534 && find_reg_fusage (tem, USE, XEXP (note, 0))))
13538 /* If we are doing a 3->2 combination, and we have a
13539 register which formerly died in i3 and was not used
13540 by i2, which now no longer dies in i3 and is used in
13541 i2 but does not die in i2, and place is between i2
13542 and i3, then we may need to move a link from place to
13544 if (i2 && DF_INSN_LUID (place) > DF_INSN_LUID (i2)
13546 && DF_INSN_LUID (from_insn) > DF_INSN_LUID (i2)
13547 && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
13549 struct insn_link *links = LOG_LINKS (place);
13550 LOG_LINKS (place) = NULL;
13551 distribute_links (links);
13556 if (tem == BB_HEAD (bb))
13562 /* If the register is set or already dead at PLACE, we needn't do
13563 anything with this note if it is still a REG_DEAD note.
13564 We check here if it is set at all, not if is it totally replaced,
13565 which is what `dead_or_set_p' checks, so also check for it being
13568 if (place && REG_NOTE_KIND (note) == REG_DEAD)
13570 unsigned int regno = REGNO (XEXP (note, 0));
13571 reg_stat_type *rsp = VEC_index (reg_stat_type, reg_stat, regno);
13573 if (dead_or_set_p (place, XEXP (note, 0))
13574 || reg_bitfield_target_p (XEXP (note, 0), PATTERN (place)))
13576 /* Unless the register previously died in PLACE, clear
13577 last_death. [I no longer understand why this is
13579 if (rsp->last_death != place)
13580 rsp->last_death = 0;
13584 rsp->last_death = place;
13586 /* If this is a death note for a hard reg that is occupying
13587 multiple registers, ensure that we are still using all
13588 parts of the object. If we find a piece of the object
13589 that is unused, we must arrange for an appropriate REG_DEAD
13590 note to be added for it. However, we can't just emit a USE
13591 and tag the note to it, since the register might actually
13592 be dead; so we recourse, and the recursive call then finds
13593 the previous insn that used this register. */
13595 if (place && regno < FIRST_PSEUDO_REGISTER
13596 && hard_regno_nregs[regno][GET_MODE (XEXP (note, 0))] > 1)
13598 unsigned int endregno = END_HARD_REGNO (XEXP (note, 0));
13602 for (i = regno; i < endregno; i++)
13603 if ((! refers_to_regno_p (i, i + 1, PATTERN (place), 0)
13604 && ! find_regno_fusage (place, USE, i))
13605 || dead_or_set_regno_p (place, i))
13610 /* Put only REG_DEAD notes for pieces that are
13611 not already dead or set. */
13613 for (i = regno; i < endregno;
13614 i += hard_regno_nregs[i][reg_raw_mode[i]])
13616 rtx piece = regno_reg_rtx[i];
13617 basic_block bb = this_basic_block;
13619 if (! dead_or_set_p (place, piece)
13620 && ! reg_bitfield_target_p (piece,
13623 rtx new_note = alloc_reg_note (REG_DEAD, piece,
13626 distribute_notes (new_note, place, place,
13627 NULL_RTX, NULL_RTX, NULL_RTX,
13630 else if (! refers_to_regno_p (i, i + 1,
13631 PATTERN (place), 0)
13632 && ! find_regno_fusage (place, USE, i))
13633 for (tem = PREV_INSN (place); ;
13634 tem = PREV_INSN (tem))
13636 if (!NONDEBUG_INSN_P (tem))
13638 if (tem == BB_HEAD (bb))
13642 if (dead_or_set_p (tem, piece)
13643 || reg_bitfield_target_p (piece,
13646 add_reg_note (tem, REG_UNUSED, piece);
13660 /* Any other notes should not be present at this point in the
13662 gcc_unreachable ();
13667 XEXP (note, 1) = REG_NOTES (place);
13668 REG_NOTES (place) = note;
13672 add_reg_note (place2, REG_NOTE_KIND (note), XEXP (note, 0));
13676 /* Similarly to above, distribute the LOG_LINKS that used to be present on
13677 I3, I2, and I1 to new locations. This is also called to add a link
13678 pointing at I3 when I3's destination is changed. */
13681 distribute_links (struct insn_link *links)
13683 struct insn_link *link, *next_link;
13685 for (link = links; link; link = next_link)
13691 next_link = link->next;
13693 /* If the insn that this link points to is a NOTE or isn't a single
13694 set, ignore it. In the latter case, it isn't clear what we
13695 can do other than ignore the link, since we can't tell which
13696 register it was for. Such links wouldn't be used by combine
13699 It is not possible for the destination of the target of the link to
13700 have been changed by combine. The only potential of this is if we
13701 replace I3, I2, and I1 by I3 and I2. But in that case the
13702 destination of I2 also remains unchanged. */
13704 if (NOTE_P (link->insn)
13705 || (set = single_set (link->insn)) == 0)
13708 reg = SET_DEST (set);
13709 while (GET_CODE (reg) == SUBREG || GET_CODE (reg) == ZERO_EXTRACT
13710 || GET_CODE (reg) == STRICT_LOW_PART)
13711 reg = XEXP (reg, 0);
13713 /* A LOG_LINK is defined as being placed on the first insn that uses
13714 a register and points to the insn that sets the register. Start
13715 searching at the next insn after the target of the link and stop
13716 when we reach a set of the register or the end of the basic block.
13718 Note that this correctly handles the link that used to point from
13719 I3 to I2. Also note that not much searching is typically done here
13720 since most links don't point very far away. */
13722 for (insn = NEXT_INSN (link->insn);
13723 (insn && (this_basic_block->next_bb == EXIT_BLOCK_PTR
13724 || BB_HEAD (this_basic_block->next_bb) != insn));
13725 insn = NEXT_INSN (insn))
13726 if (DEBUG_INSN_P (insn))
13728 else if (INSN_P (insn) && reg_overlap_mentioned_p (reg, PATTERN (insn)))
13730 if (reg_referenced_p (reg, PATTERN (insn)))
13734 else if (CALL_P (insn)
13735 && find_reg_fusage (insn, USE, reg))
13740 else if (INSN_P (insn) && reg_set_p (reg, insn))
13743 /* If we found a place to put the link, place it there unless there
13744 is already a link to the same insn as LINK at that point. */
13748 struct insn_link *link2;
13750 FOR_EACH_LOG_LINK (link2, place)
13751 if (link2->insn == link->insn)
13756 link->next = LOG_LINKS (place);
13757 LOG_LINKS (place) = link;
13759 /* Set added_links_insn to the earliest insn we added a
13761 if (added_links_insn == 0
13762 || DF_INSN_LUID (added_links_insn) > DF_INSN_LUID (place))
13763 added_links_insn = place;
13769 /* Subroutine of unmentioned_reg_p and callback from for_each_rtx.
13770 Check whether the expression pointer to by LOC is a register or
13771 memory, and if so return 1 if it isn't mentioned in the rtx EXPR.
13772 Otherwise return zero. */
13775 unmentioned_reg_p_1 (rtx *loc, void *expr)
13780 && (REG_P (x) || MEM_P (x))
13781 && ! reg_mentioned_p (x, (rtx) expr))
13786 /* Check for any register or memory mentioned in EQUIV that is not
13787 mentioned in EXPR. This is used to restrict EQUIV to "specializations"
13788 of EXPR where some registers may have been replaced by constants. */
13791 unmentioned_reg_p (rtx equiv, rtx expr)
13793 return for_each_rtx (&equiv, unmentioned_reg_p_1, expr);
13797 dump_combine_stats (FILE *file)
13801 ";; Combiner statistics: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n\n",
13802 combine_attempts, combine_merges, combine_extras, combine_successes);
13806 dump_combine_total_stats (FILE *file)
13810 "\n;; Combiner totals: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n",
13811 total_attempts, total_merges, total_extras, total_successes);
13815 gate_handle_combine (void)
13817 return (optimize > 0);
13820 /* Try combining insns through substitution. */
13821 static unsigned int
13822 rest_of_handle_combine (void)
13824 int rebuild_jump_labels_after_combine;
13826 df_set_flags (DF_LR_RUN_DCE + DF_DEFER_INSN_RESCAN);
13827 df_note_add_problem ();
13830 regstat_init_n_sets_and_refs ();
13832 rebuild_jump_labels_after_combine
13833 = combine_instructions (get_insns (), max_reg_num ());
13835 /* Combining insns may have turned an indirect jump into a
13836 direct jump. Rebuild the JUMP_LABEL fields of jumping
13838 if (rebuild_jump_labels_after_combine)
13840 timevar_push (TV_JUMP);
13841 rebuild_jump_labels (get_insns ());
13843 timevar_pop (TV_JUMP);
13846 regstat_free_n_sets_and_refs ();
13850 struct rtl_opt_pass pass_combine =
13854 "combine", /* name */
13855 gate_handle_combine, /* gate */
13856 rest_of_handle_combine, /* execute */
13859 0, /* static_pass_number */
13860 TV_COMBINE, /* tv_id */
13861 PROP_cfglayout, /* properties_required */
13862 0, /* properties_provided */
13863 0, /* properties_destroyed */
13864 0, /* todo_flags_start */
13866 TODO_df_finish | TODO_verify_rtl_sharing |
13867 TODO_ggc_collect, /* todo_flags_finish */