1 /* Optimize by combining instructions for GNU compiler.
2 Copyright (C) 1987, 1988, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010
4 Free Software Foundation, Inc.
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify it under
9 the terms of the GNU General Public License as published by the Free
10 Software Foundation; either version 3, or (at your option) any later
13 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
14 WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
22 /* This module is essentially the "combiner" phase of the U. of Arizona
23 Portable Optimizer, but redone to work on our list-structured
24 representation for RTL instead of their string representation.
26 The LOG_LINKS of each insn identify the most recent assignment
27 to each REG used in the insn. It is a list of previous insns,
28 each of which contains a SET for a REG that is used in this insn
29 and not used or set in between. LOG_LINKs never cross basic blocks.
30 They were set up by the preceding pass (lifetime analysis).
32 We try to combine each pair of insns joined by a logical link.
33 We also try to combine triples of insns A, B and C when
34 C has a link back to B and B has a link back to A.
36 LOG_LINKS does not have links for use of the CC0. They don't
37 need to, because the insn that sets the CC0 is always immediately
38 before the insn that tests it. So we always regard a branch
39 insn as having a logical link to the preceding insn. The same is true
40 for an insn explicitly using CC0.
42 We check (with use_crosses_set_p) to avoid combining in such a way
43 as to move a computation to a place where its value would be different.
45 Combination is done by mathematically substituting the previous
46 insn(s) values for the regs they set into the expressions in
47 the later insns that refer to these regs. If the result is a valid insn
48 for our target machine, according to the machine description,
49 we install it, delete the earlier insns, and update the data flow
50 information (LOG_LINKS and REG_NOTES) for what we did.
52 There are a few exceptions where the dataflow information isn't
53 completely updated (however this is only a local issue since it is
54 regenerated before the next pass that uses it):
56 - reg_live_length is not updated
57 - reg_n_refs is not adjusted in the rare case when a register is
58 no longer required in a computation
59 - there are extremely rare cases (see distribute_notes) when a
61 - a LOG_LINKS entry that refers to an insn with multiple SETs may be
62 removed because there is no way to know which register it was
65 To simplify substitution, we combine only when the earlier insn(s)
66 consist of only a single assignment. To simplify updating afterward,
67 we never combine when a subroutine call appears in the middle.
69 Since we do not represent assignments to CC0 explicitly except when that
70 is all an insn does, there is no LOG_LINKS entry in an insn that uses
71 the condition code for the insn that set the condition code.
72 Fortunately, these two insns must be consecutive.
73 Therefore, every JUMP_INSN is taken to have an implicit logical link
74 to the preceding insn. This is not quite right, since non-jumps can
75 also use the condition code; but in practice such insns would not
80 #include "coretypes.h"
87 #include "hard-reg-set.h"
88 #include "basic-block.h"
89 #include "insn-config.h"
91 /* Include expr.h after insn-config.h so we get HAVE_conditional_move. */
93 #include "insn-attr.h"
95 #include "diagnostic-core.h"
99 #include "insn-codes.h"
100 #include "rtlhooks-def.h"
101 /* Include output.h for dump_file. */
105 #include "tree-pass.h"
109 /* Number of attempts to combine instructions in this function. */
111 static int combine_attempts;
113 /* Number of attempts that got as far as substitution in this function. */
115 static int combine_merges;
117 /* Number of instructions combined with added SETs in this function. */
119 static int combine_extras;
121 /* Number of instructions combined in this function. */
123 static int combine_successes;
125 /* Totals over entire compilation. */
127 static int total_attempts, total_merges, total_extras, total_successes;
129 /* combine_instructions may try to replace the right hand side of the
130 second instruction with the value of an associated REG_EQUAL note
131 before throwing it at try_combine. That is problematic when there
132 is a REG_DEAD note for a register used in the old right hand side
133 and can cause distribute_notes to do wrong things. This is the
134 second instruction if it has been so modified, null otherwise. */
138 /* When I2MOD is nonnull, this is a copy of the old right hand side. */
140 static rtx i2mod_old_rhs;
142 /* When I2MOD is nonnull, this is a copy of the new right hand side. */
144 static rtx i2mod_new_rhs;
146 typedef struct reg_stat_struct {
147 /* Record last point of death of (hard or pseudo) register n. */
150 /* Record last point of modification of (hard or pseudo) register n. */
153 /* The next group of fields allows the recording of the last value assigned
154 to (hard or pseudo) register n. We use this information to see if an
155 operation being processed is redundant given a prior operation performed
156 on the register. For example, an `and' with a constant is redundant if
157 all the zero bits are already known to be turned off.
159 We use an approach similar to that used by cse, but change it in the
162 (1) We do not want to reinitialize at each label.
163 (2) It is useful, but not critical, to know the actual value assigned
164 to a register. Often just its form is helpful.
166 Therefore, we maintain the following fields:
168 last_set_value the last value assigned
169 last_set_label records the value of label_tick when the
170 register was assigned
171 last_set_table_tick records the value of label_tick when a
172 value using the register is assigned
173 last_set_invalid set to nonzero when it is not valid
174 to use the value of this register in some
177 To understand the usage of these tables, it is important to understand
178 the distinction between the value in last_set_value being valid and
179 the register being validly contained in some other expression in the
182 (The next two parameters are out of date).
184 reg_stat[i].last_set_value is valid if it is nonzero, and either
185 reg_n_sets[i] is 1 or reg_stat[i].last_set_label == label_tick.
187 Register I may validly appear in any expression returned for the value
188 of another register if reg_n_sets[i] is 1. It may also appear in the
189 value for register J if reg_stat[j].last_set_invalid is zero, or
190 reg_stat[i].last_set_label < reg_stat[j].last_set_label.
192 If an expression is found in the table containing a register which may
193 not validly appear in an expression, the register is replaced by
194 something that won't match, (clobber (const_int 0)). */
196 /* Record last value assigned to (hard or pseudo) register n. */
200 /* Record the value of label_tick when an expression involving register n
201 is placed in last_set_value. */
203 int last_set_table_tick;
205 /* Record the value of label_tick when the value for register n is placed in
210 /* These fields are maintained in parallel with last_set_value and are
211 used to store the mode in which the register was last set, the bits
212 that were known to be zero when it was last set, and the number of
213 sign bits copies it was known to have when it was last set. */
215 unsigned HOST_WIDE_INT last_set_nonzero_bits;
216 char last_set_sign_bit_copies;
217 ENUM_BITFIELD(machine_mode) last_set_mode : 8;
219 /* Set nonzero if references to register n in expressions should not be
220 used. last_set_invalid is set nonzero when this register is being
221 assigned to and last_set_table_tick == label_tick. */
223 char last_set_invalid;
225 /* Some registers that are set more than once and used in more than one
226 basic block are nevertheless always set in similar ways. For example,
227 a QImode register may be loaded from memory in two places on a machine
228 where byte loads zero extend.
230 We record in the following fields if a register has some leading bits
231 that are always equal to the sign bit, and what we know about the
232 nonzero bits of a register, specifically which bits are known to be
235 If an entry is zero, it means that we don't know anything special. */
237 unsigned char sign_bit_copies;
239 unsigned HOST_WIDE_INT nonzero_bits;
241 /* Record the value of the label_tick when the last truncation
242 happened. The field truncated_to_mode is only valid if
243 truncation_label == label_tick. */
245 int truncation_label;
247 /* Record the last truncation seen for this register. If truncation
248 is not a nop to this mode we might be able to save an explicit
249 truncation if we know that value already contains a truncated
252 ENUM_BITFIELD(machine_mode) truncated_to_mode : 8;
255 DEF_VEC_O(reg_stat_type);
256 DEF_VEC_ALLOC_O(reg_stat_type,heap);
258 static VEC(reg_stat_type,heap) *reg_stat;
260 /* Record the luid of the last insn that invalidated memory
261 (anything that writes memory, and subroutine calls, but not pushes). */
263 static int mem_last_set;
265 /* Record the luid of the last CALL_INSN
266 so we can tell whether a potential combination crosses any calls. */
268 static int last_call_luid;
270 /* When `subst' is called, this is the insn that is being modified
271 (by combining in a previous insn). The PATTERN of this insn
272 is still the old pattern partially modified and it should not be
273 looked at, but this may be used to examine the successors of the insn
274 to judge whether a simplification is valid. */
276 static rtx subst_insn;
278 /* This is the lowest LUID that `subst' is currently dealing with.
279 get_last_value will not return a value if the register was set at or
280 after this LUID. If not for this mechanism, we could get confused if
281 I2 or I1 in try_combine were an insn that used the old value of a register
282 to obtain a new value. In that case, we might erroneously get the
283 new value of the register when we wanted the old one. */
285 static int subst_low_luid;
287 /* This contains any hard registers that are used in newpat; reg_dead_at_p
288 must consider all these registers to be always live. */
290 static HARD_REG_SET newpat_used_regs;
292 /* This is an insn to which a LOG_LINKS entry has been added. If this
293 insn is the earlier than I2 or I3, combine should rescan starting at
296 static rtx added_links_insn;
298 /* Basic block in which we are performing combines. */
299 static basic_block this_basic_block;
300 static bool optimize_this_for_speed_p;
303 /* Length of the currently allocated uid_insn_cost array. */
305 static int max_uid_known;
307 /* The following array records the insn_rtx_cost for every insn
308 in the instruction stream. */
310 static int *uid_insn_cost;
312 /* The following array records the LOG_LINKS for every insn in the
313 instruction stream as an INSN_LIST rtx. */
315 static rtx *uid_log_links;
317 #define INSN_COST(INSN) (uid_insn_cost[INSN_UID (INSN)])
318 #define LOG_LINKS(INSN) (uid_log_links[INSN_UID (INSN)])
320 /* Incremented for each basic block. */
322 static int label_tick;
324 /* Reset to label_tick for each extended basic block in scanning order. */
326 static int label_tick_ebb_start;
328 /* Mode used to compute significance in reg_stat[].nonzero_bits. It is the
329 largest integer mode that can fit in HOST_BITS_PER_WIDE_INT. */
331 static enum machine_mode nonzero_bits_mode;
333 /* Nonzero when reg_stat[].nonzero_bits and reg_stat[].sign_bit_copies can
334 be safely used. It is zero while computing them and after combine has
335 completed. This former test prevents propagating values based on
336 previously set values, which can be incorrect if a variable is modified
339 static int nonzero_sign_valid;
342 /* Record one modification to rtl structure
343 to be undone by storing old_contents into *where. */
345 enum undo_kind { UNDO_RTX, UNDO_INT, UNDO_MODE };
351 union { rtx r; int i; enum machine_mode m; } old_contents;
352 union { rtx *r; int *i; } where;
355 /* Record a bunch of changes to be undone, up to MAX_UNDO of them.
356 num_undo says how many are currently recorded.
358 other_insn is nonzero if we have modified some other insn in the process
359 of working on subst_insn. It must be verified too. */
368 static struct undobuf undobuf;
370 /* Number of times the pseudo being substituted for
371 was found and replaced. */
373 static int n_occurrences;
375 static rtx reg_nonzero_bits_for_combine (const_rtx, enum machine_mode, const_rtx,
377 unsigned HOST_WIDE_INT,
378 unsigned HOST_WIDE_INT *);
379 static rtx reg_num_sign_bit_copies_for_combine (const_rtx, enum machine_mode, const_rtx,
381 unsigned int, unsigned int *);
382 static void do_SUBST (rtx *, rtx);
383 static void do_SUBST_INT (int *, int);
384 static void init_reg_last (void);
385 static void setup_incoming_promotions (rtx);
386 static void set_nonzero_bits_and_sign_copies (rtx, const_rtx, void *);
387 static int cant_combine_insn_p (rtx);
388 static int can_combine_p (rtx, rtx, rtx, rtx, rtx *, rtx *);
389 static int combinable_i3pat (rtx, rtx *, rtx, rtx, int, rtx *);
390 static int contains_muldiv (rtx);
391 static rtx try_combine (rtx, rtx, rtx, int *);
392 static void undo_all (void);
393 static void undo_commit (void);
394 static rtx *find_split_point (rtx *, rtx, bool);
395 static rtx subst (rtx, rtx, rtx, int, int);
396 static rtx combine_simplify_rtx (rtx, enum machine_mode, int);
397 static rtx simplify_if_then_else (rtx);
398 static rtx simplify_set (rtx);
399 static rtx simplify_logical (rtx);
400 static rtx expand_compound_operation (rtx);
401 static const_rtx expand_field_assignment (const_rtx);
402 static rtx make_extraction (enum machine_mode, rtx, HOST_WIDE_INT,
403 rtx, unsigned HOST_WIDE_INT, int, int, int);
404 static rtx extract_left_shift (rtx, int);
405 static rtx make_compound_operation (rtx, enum rtx_code);
406 static int get_pos_from_mask (unsigned HOST_WIDE_INT,
407 unsigned HOST_WIDE_INT *);
408 static rtx canon_reg_for_combine (rtx, rtx);
409 static rtx force_to_mode (rtx, enum machine_mode,
410 unsigned HOST_WIDE_INT, int);
411 static rtx if_then_else_cond (rtx, rtx *, rtx *);
412 static rtx known_cond (rtx, enum rtx_code, rtx, rtx);
413 static int rtx_equal_for_field_assignment_p (rtx, rtx);
414 static rtx make_field_assignment (rtx);
415 static rtx apply_distributive_law (rtx);
416 static rtx distribute_and_simplify_rtx (rtx, int);
417 static rtx simplify_and_const_int_1 (enum machine_mode, rtx,
418 unsigned HOST_WIDE_INT);
419 static rtx simplify_and_const_int (rtx, enum machine_mode, rtx,
420 unsigned HOST_WIDE_INT);
421 static int merge_outer_ops (enum rtx_code *, HOST_WIDE_INT *, enum rtx_code,
422 HOST_WIDE_INT, enum machine_mode, int *);
423 static rtx simplify_shift_const_1 (enum rtx_code, enum machine_mode, rtx, int);
424 static rtx simplify_shift_const (rtx, enum rtx_code, enum machine_mode, rtx,
426 static int recog_for_combine (rtx *, rtx, rtx *);
427 static rtx gen_lowpart_for_combine (enum machine_mode, rtx);
428 static enum rtx_code simplify_comparison (enum rtx_code, rtx *, rtx *);
429 static void update_table_tick (rtx);
430 static void record_value_for_reg (rtx, rtx, rtx);
431 static void check_promoted_subreg (rtx, rtx);
432 static void record_dead_and_set_regs_1 (rtx, const_rtx, void *);
433 static void record_dead_and_set_regs (rtx);
434 static int get_last_value_validate (rtx *, rtx, int, int);
435 static rtx get_last_value (const_rtx);
436 static int use_crosses_set_p (const_rtx, int);
437 static void reg_dead_at_p_1 (rtx, const_rtx, void *);
438 static int reg_dead_at_p (rtx, rtx);
439 static void move_deaths (rtx, rtx, int, rtx, rtx *);
440 static int reg_bitfield_target_p (rtx, rtx);
441 static void distribute_notes (rtx, rtx, rtx, rtx, rtx, rtx);
442 static void distribute_links (rtx);
443 static void mark_used_regs_combine (rtx);
444 static void record_promoted_value (rtx, rtx);
445 static int unmentioned_reg_p_1 (rtx *, void *);
446 static bool unmentioned_reg_p (rtx, rtx);
447 static int record_truncated_value (rtx *, void *);
448 static void record_truncated_values (rtx *, void *);
449 static bool reg_truncated_to_mode (enum machine_mode, const_rtx);
450 static rtx gen_lowpart_or_truncate (enum machine_mode, rtx);
453 /* It is not safe to use ordinary gen_lowpart in combine.
454 See comments in gen_lowpart_for_combine. */
455 #undef RTL_HOOKS_GEN_LOWPART
456 #define RTL_HOOKS_GEN_LOWPART gen_lowpart_for_combine
458 /* Our implementation of gen_lowpart never emits a new pseudo. */
459 #undef RTL_HOOKS_GEN_LOWPART_NO_EMIT
460 #define RTL_HOOKS_GEN_LOWPART_NO_EMIT gen_lowpart_for_combine
462 #undef RTL_HOOKS_REG_NONZERO_REG_BITS
463 #define RTL_HOOKS_REG_NONZERO_REG_BITS reg_nonzero_bits_for_combine
465 #undef RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES
466 #define RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES reg_num_sign_bit_copies_for_combine
468 #undef RTL_HOOKS_REG_TRUNCATED_TO_MODE
469 #define RTL_HOOKS_REG_TRUNCATED_TO_MODE reg_truncated_to_mode
471 static const struct rtl_hooks combine_rtl_hooks = RTL_HOOKS_INITIALIZER;
474 /* Try to split PATTERN found in INSN. This returns NULL_RTX if
475 PATTERN can not be split. Otherwise, it returns an insn sequence.
476 This is a wrapper around split_insns which ensures that the
477 reg_stat vector is made larger if the splitter creates a new
481 combine_split_insns (rtx pattern, rtx insn)
486 ret = split_insns (pattern, insn);
487 nregs = max_reg_num ();
488 if (nregs > VEC_length (reg_stat_type, reg_stat))
489 VEC_safe_grow_cleared (reg_stat_type, heap, reg_stat, nregs);
493 /* This is used by find_single_use to locate an rtx in LOC that
494 contains exactly one use of DEST, which is typically either a REG
495 or CC0. It returns a pointer to the innermost rtx expression
496 containing DEST. Appearances of DEST that are being used to
497 totally replace it are not counted. */
500 find_single_use_1 (rtx dest, rtx *loc)
503 enum rtx_code code = GET_CODE (x);
521 /* If the destination is anything other than CC0, PC, a REG or a SUBREG
522 of a REG that occupies all of the REG, the insn uses DEST if
523 it is mentioned in the destination or the source. Otherwise, we
524 need just check the source. */
525 if (GET_CODE (SET_DEST (x)) != CC0
526 && GET_CODE (SET_DEST (x)) != PC
527 && !REG_P (SET_DEST (x))
528 && ! (GET_CODE (SET_DEST (x)) == SUBREG
529 && REG_P (SUBREG_REG (SET_DEST (x)))
530 && (((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x))))
531 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
532 == ((GET_MODE_SIZE (GET_MODE (SET_DEST (x)))
533 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD))))
536 return find_single_use_1 (dest, &SET_SRC (x));
540 return find_single_use_1 (dest, &XEXP (x, 0));
546 /* If it wasn't one of the common cases above, check each expression and
547 vector of this code. Look for a unique usage of DEST. */
549 fmt = GET_RTX_FORMAT (code);
550 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
554 if (dest == XEXP (x, i)
555 || (REG_P (dest) && REG_P (XEXP (x, i))
556 && REGNO (dest) == REGNO (XEXP (x, i))))
559 this_result = find_single_use_1 (dest, &XEXP (x, i));
562 result = this_result;
563 else if (this_result)
564 /* Duplicate usage. */
567 else if (fmt[i] == 'E')
571 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
573 if (XVECEXP (x, i, j) == dest
575 && REG_P (XVECEXP (x, i, j))
576 && REGNO (XVECEXP (x, i, j)) == REGNO (dest)))
579 this_result = find_single_use_1 (dest, &XVECEXP (x, i, j));
582 result = this_result;
583 else if (this_result)
593 /* See if DEST, produced in INSN, is used only a single time in the
594 sequel. If so, return a pointer to the innermost rtx expression in which
597 If PLOC is nonzero, *PLOC is set to the insn containing the single use.
599 If DEST is cc0_rtx, we look only at the next insn. In that case, we don't
600 care about REG_DEAD notes or LOG_LINKS.
602 Otherwise, we find the single use by finding an insn that has a
603 LOG_LINKS pointing at INSN and has a REG_DEAD note for DEST. If DEST is
604 only referenced once in that insn, we know that it must be the first
605 and last insn referencing DEST. */
608 find_single_use (rtx dest, rtx insn, rtx *ploc)
618 next = NEXT_INSN (insn);
620 || (!NONJUMP_INSN_P (next) && !JUMP_P (next)))
623 result = find_single_use_1 (dest, &PATTERN (next));
633 bb = BLOCK_FOR_INSN (insn);
634 for (next = NEXT_INSN (insn);
635 next && BLOCK_FOR_INSN (next) == bb;
636 next = NEXT_INSN (next))
637 if (INSN_P (next) && dead_or_set_p (next, dest))
639 for (link = LOG_LINKS (next); link; link = XEXP (link, 1))
640 if (XEXP (link, 0) == insn)
645 result = find_single_use_1 (dest, &PATTERN (next));
655 /* Substitute NEWVAL, an rtx expression, into INTO, a place in some
656 insn. The substitution can be undone by undo_all. If INTO is already
657 set to NEWVAL, do not record this change. Because computing NEWVAL might
658 also call SUBST, we have to compute it before we put anything into
662 do_SUBST (rtx *into, rtx newval)
667 if (oldval == newval)
670 /* We'd like to catch as many invalid transformations here as
671 possible. Unfortunately, there are way too many mode changes
672 that are perfectly valid, so we'd waste too much effort for
673 little gain doing the checks here. Focus on catching invalid
674 transformations involving integer constants. */
675 if (GET_MODE_CLASS (GET_MODE (oldval)) == MODE_INT
676 && CONST_INT_P (newval))
678 /* Sanity check that we're replacing oldval with a CONST_INT
679 that is a valid sign-extension for the original mode. */
680 gcc_assert (INTVAL (newval)
681 == trunc_int_for_mode (INTVAL (newval), GET_MODE (oldval)));
683 /* Replacing the operand of a SUBREG or a ZERO_EXTEND with a
684 CONST_INT is not valid, because after the replacement, the
685 original mode would be gone. Unfortunately, we can't tell
686 when do_SUBST is called to replace the operand thereof, so we
687 perform this test on oldval instead, checking whether an
688 invalid replacement took place before we got here. */
689 gcc_assert (!(GET_CODE (oldval) == SUBREG
690 && CONST_INT_P (SUBREG_REG (oldval))));
691 gcc_assert (!(GET_CODE (oldval) == ZERO_EXTEND
692 && CONST_INT_P (XEXP (oldval, 0))));
696 buf = undobuf.frees, undobuf.frees = buf->next;
698 buf = XNEW (struct undo);
700 buf->kind = UNDO_RTX;
702 buf->old_contents.r = oldval;
705 buf->next = undobuf.undos, undobuf.undos = buf;
708 #define SUBST(INTO, NEWVAL) do_SUBST(&(INTO), (NEWVAL))
710 /* Similar to SUBST, but NEWVAL is an int expression. Note that substitution
711 for the value of a HOST_WIDE_INT value (including CONST_INT) is
715 do_SUBST_INT (int *into, int newval)
720 if (oldval == newval)
724 buf = undobuf.frees, undobuf.frees = buf->next;
726 buf = XNEW (struct undo);
728 buf->kind = UNDO_INT;
730 buf->old_contents.i = oldval;
733 buf->next = undobuf.undos, undobuf.undos = buf;
736 #define SUBST_INT(INTO, NEWVAL) do_SUBST_INT(&(INTO), (NEWVAL))
738 /* Similar to SUBST, but just substitute the mode. This is used when
739 changing the mode of a pseudo-register, so that any other
740 references to the entry in the regno_reg_rtx array will change as
744 do_SUBST_MODE (rtx *into, enum machine_mode newval)
747 enum machine_mode oldval = GET_MODE (*into);
749 if (oldval == newval)
753 buf = undobuf.frees, undobuf.frees = buf->next;
755 buf = XNEW (struct undo);
757 buf->kind = UNDO_MODE;
759 buf->old_contents.m = oldval;
760 adjust_reg_mode (*into, newval);
762 buf->next = undobuf.undos, undobuf.undos = buf;
765 #define SUBST_MODE(INTO, NEWVAL) do_SUBST_MODE(&(INTO), (NEWVAL))
767 /* Subroutine of try_combine. Determine whether the combine replacement
768 patterns NEWPAT, NEWI2PAT and NEWOTHERPAT are cheaper according to
769 insn_rtx_cost that the original instruction sequence I1, I2, I3 and
770 undobuf.other_insn. Note that I1 and/or NEWI2PAT may be NULL_RTX.
771 NEWOTHERPAT and undobuf.other_insn may also both be NULL_RTX. This
772 function returns false, if the costs of all instructions can be
773 estimated, and the replacements are more expensive than the original
777 combine_validate_cost (rtx i1, rtx i2, rtx i3, rtx newpat, rtx newi2pat,
780 int i1_cost, i2_cost, i3_cost;
781 int new_i2_cost, new_i3_cost;
782 int old_cost, new_cost;
784 /* Lookup the original insn_rtx_costs. */
785 i2_cost = INSN_COST (i2);
786 i3_cost = INSN_COST (i3);
790 i1_cost = INSN_COST (i1);
791 old_cost = (i1_cost > 0 && i2_cost > 0 && i3_cost > 0)
792 ? i1_cost + i2_cost + i3_cost : 0;
796 old_cost = (i2_cost > 0 && i3_cost > 0) ? i2_cost + i3_cost : 0;
800 /* Calculate the replacement insn_rtx_costs. */
801 new_i3_cost = insn_rtx_cost (newpat, optimize_this_for_speed_p);
804 new_i2_cost = insn_rtx_cost (newi2pat, optimize_this_for_speed_p);
805 new_cost = (new_i2_cost > 0 && new_i3_cost > 0)
806 ? new_i2_cost + new_i3_cost : 0;
810 new_cost = new_i3_cost;
814 if (undobuf.other_insn)
816 int old_other_cost, new_other_cost;
818 old_other_cost = INSN_COST (undobuf.other_insn);
819 new_other_cost = insn_rtx_cost (newotherpat, optimize_this_for_speed_p);
820 if (old_other_cost > 0 && new_other_cost > 0)
822 old_cost += old_other_cost;
823 new_cost += new_other_cost;
829 /* Disallow this recombination if both new_cost and old_cost are
830 greater than zero, and new_cost is greater than old cost. */
832 && new_cost > old_cost)
839 "rejecting combination of insns %d, %d and %d\n",
840 INSN_UID (i1), INSN_UID (i2), INSN_UID (i3));
841 fprintf (dump_file, "original costs %d + %d + %d = %d\n",
842 i1_cost, i2_cost, i3_cost, old_cost);
847 "rejecting combination of insns %d and %d\n",
848 INSN_UID (i2), INSN_UID (i3));
849 fprintf (dump_file, "original costs %d + %d = %d\n",
850 i2_cost, i3_cost, old_cost);
855 fprintf (dump_file, "replacement costs %d + %d = %d\n",
856 new_i2_cost, new_i3_cost, new_cost);
859 fprintf (dump_file, "replacement cost %d\n", new_cost);
865 /* Update the uid_insn_cost array with the replacement costs. */
866 INSN_COST (i2) = new_i2_cost;
867 INSN_COST (i3) = new_i3_cost;
875 /* Delete any insns that copy a register to itself. */
878 delete_noop_moves (void)
885 for (insn = BB_HEAD (bb); insn != NEXT_INSN (BB_END (bb)); insn = next)
887 next = NEXT_INSN (insn);
888 if (INSN_P (insn) && noop_move_p (insn))
891 fprintf (dump_file, "deleting noop move %d\n", INSN_UID (insn));
893 delete_insn_and_edges (insn);
900 /* Fill in log links field for all insns. */
903 create_log_links (void)
907 df_ref *def_vec, *use_vec;
909 next_use = XCNEWVEC (rtx, max_reg_num ());
911 /* Pass through each block from the end, recording the uses of each
912 register and establishing log links when def is encountered.
913 Note that we do not clear next_use array in order to save time,
914 so we have to test whether the use is in the same basic block as def.
916 There are a few cases below when we do not consider the definition or
917 usage -- these are taken from original flow.c did. Don't ask me why it is
918 done this way; I don't know and if it works, I don't want to know. */
922 FOR_BB_INSNS_REVERSE (bb, insn)
924 if (!NONDEBUG_INSN_P (insn))
927 /* Log links are created only once. */
928 gcc_assert (!LOG_LINKS (insn));
930 for (def_vec = DF_INSN_DEFS (insn); *def_vec; def_vec++)
932 df_ref def = *def_vec;
933 int regno = DF_REF_REGNO (def);
936 if (!next_use[regno])
939 /* Do not consider if it is pre/post modification in MEM. */
940 if (DF_REF_FLAGS (def) & DF_REF_PRE_POST_MODIFY)
943 /* Do not make the log link for frame pointer. */
944 if ((regno == FRAME_POINTER_REGNUM
945 && (! reload_completed || frame_pointer_needed))
946 #if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM
947 || (regno == HARD_FRAME_POINTER_REGNUM
948 && (! reload_completed || frame_pointer_needed))
950 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
951 || (regno == ARG_POINTER_REGNUM && fixed_regs[regno])
956 use_insn = next_use[regno];
957 if (BLOCK_FOR_INSN (use_insn) == bb)
961 We don't build a LOG_LINK for hard registers contained
962 in ASM_OPERANDs. If these registers get replaced,
963 we might wind up changing the semantics of the insn,
964 even if reload can make what appear to be valid
965 assignments later. */
966 if (regno >= FIRST_PSEUDO_REGISTER
967 || asm_noperands (PATTERN (use_insn)) < 0)
969 /* Don't add duplicate links between instructions. */
971 for (links = LOG_LINKS (use_insn); links;
972 links = XEXP (links, 1))
973 if (insn == XEXP (links, 0))
977 LOG_LINKS (use_insn) =
978 alloc_INSN_LIST (insn, LOG_LINKS (use_insn));
981 next_use[regno] = NULL_RTX;
984 for (use_vec = DF_INSN_USES (insn); *use_vec; use_vec++)
986 df_ref use = *use_vec;
987 int regno = DF_REF_REGNO (use);
989 /* Do not consider the usage of the stack pointer
991 if (DF_REF_FLAGS (use) & DF_REF_CALL_STACK_USAGE)
994 next_use[regno] = insn;
1002 /* Clear LOG_LINKS fields of insns. */
1005 clear_log_links (void)
1009 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
1011 free_INSN_LIST_list (&LOG_LINKS (insn));
1014 /* Main entry point for combiner. F is the first insn of the function.
1015 NREGS is the first unused pseudo-reg number.
1017 Return nonzero if the combiner has turned an indirect jump
1018 instruction into a direct jump. */
1020 combine_instructions (rtx f, unsigned int nregs)
1026 rtx links, nextlinks;
1028 basic_block last_bb;
1030 int new_direct_jump_p = 0;
1032 for (first = f; first && !INSN_P (first); )
1033 first = NEXT_INSN (first);
1037 combine_attempts = 0;
1040 combine_successes = 0;
1042 rtl_hooks = combine_rtl_hooks;
1044 VEC_safe_grow_cleared (reg_stat_type, heap, reg_stat, nregs);
1046 init_recog_no_volatile ();
1048 /* Allocate array for insn info. */
1049 max_uid_known = get_max_uid ();
1050 uid_log_links = XCNEWVEC (rtx, max_uid_known + 1);
1051 uid_insn_cost = XCNEWVEC (int, max_uid_known + 1);
1053 nonzero_bits_mode = mode_for_size (HOST_BITS_PER_WIDE_INT, MODE_INT, 0);
1055 /* Don't use reg_stat[].nonzero_bits when computing it. This can cause
1056 problems when, for example, we have j <<= 1 in a loop. */
1058 nonzero_sign_valid = 0;
1059 label_tick = label_tick_ebb_start = 1;
1061 /* Scan all SETs and see if we can deduce anything about what
1062 bits are known to be zero for some registers and how many copies
1063 of the sign bit are known to exist for those registers.
1065 Also set any known values so that we can use it while searching
1066 for what bits are known to be set. */
1068 setup_incoming_promotions (first);
1069 /* Allow the entry block and the first block to fall into the same EBB.
1070 Conceptually the incoming promotions are assigned to the entry block. */
1071 last_bb = ENTRY_BLOCK_PTR;
1073 create_log_links ();
1074 FOR_EACH_BB (this_basic_block)
1076 optimize_this_for_speed_p = optimize_bb_for_speed_p (this_basic_block);
1081 if (!single_pred_p (this_basic_block)
1082 || single_pred (this_basic_block) != last_bb)
1083 label_tick_ebb_start = label_tick;
1084 last_bb = this_basic_block;
1086 FOR_BB_INSNS (this_basic_block, insn)
1087 if (INSN_P (insn) && BLOCK_FOR_INSN (insn))
1089 subst_low_luid = DF_INSN_LUID (insn);
1092 note_stores (PATTERN (insn), set_nonzero_bits_and_sign_copies,
1094 record_dead_and_set_regs (insn);
1097 for (links = REG_NOTES (insn); links; links = XEXP (links, 1))
1098 if (REG_NOTE_KIND (links) == REG_INC)
1099 set_nonzero_bits_and_sign_copies (XEXP (links, 0), NULL_RTX,
1103 /* Record the current insn_rtx_cost of this instruction. */
1104 if (NONJUMP_INSN_P (insn))
1105 INSN_COST (insn) = insn_rtx_cost (PATTERN (insn),
1106 optimize_this_for_speed_p);
1108 fprintf(dump_file, "insn_cost %d: %d\n",
1109 INSN_UID (insn), INSN_COST (insn));
1113 nonzero_sign_valid = 1;
1115 /* Now scan all the insns in forward order. */
1116 label_tick = label_tick_ebb_start = 1;
1118 setup_incoming_promotions (first);
1119 last_bb = ENTRY_BLOCK_PTR;
1121 FOR_EACH_BB (this_basic_block)
1123 optimize_this_for_speed_p = optimize_bb_for_speed_p (this_basic_block);
1128 if (!single_pred_p (this_basic_block)
1129 || single_pred (this_basic_block) != last_bb)
1130 label_tick_ebb_start = label_tick;
1131 last_bb = this_basic_block;
1133 rtl_profile_for_bb (this_basic_block);
1134 for (insn = BB_HEAD (this_basic_block);
1135 insn != NEXT_INSN (BB_END (this_basic_block));
1136 insn = next ? next : NEXT_INSN (insn))
1139 if (NONDEBUG_INSN_P (insn))
1141 /* See if we know about function return values before this
1142 insn based upon SUBREG flags. */
1143 check_promoted_subreg (insn, PATTERN (insn));
1145 /* See if we can find hardregs and subreg of pseudos in
1146 narrower modes. This could help turning TRUNCATEs
1148 note_uses (&PATTERN (insn), record_truncated_values, NULL);
1150 /* Try this insn with each insn it links back to. */
1152 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
1153 if ((next = try_combine (insn, XEXP (links, 0),
1154 NULL_RTX, &new_direct_jump_p)) != 0)
1157 /* Try each sequence of three linked insns ending with this one. */
1159 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
1161 rtx link = XEXP (links, 0);
1163 /* If the linked insn has been replaced by a note, then there
1164 is no point in pursuing this chain any further. */
1168 for (nextlinks = LOG_LINKS (link);
1170 nextlinks = XEXP (nextlinks, 1))
1171 if ((next = try_combine (insn, link,
1172 XEXP (nextlinks, 0),
1173 &new_direct_jump_p)) != 0)
1178 /* Try to combine a jump insn that uses CC0
1179 with a preceding insn that sets CC0, and maybe with its
1180 logical predecessor as well.
1181 This is how we make decrement-and-branch insns.
1182 We need this special code because data flow connections
1183 via CC0 do not get entered in LOG_LINKS. */
1186 && (prev = prev_nonnote_insn (insn)) != 0
1187 && NONJUMP_INSN_P (prev)
1188 && sets_cc0_p (PATTERN (prev)))
1190 if ((next = try_combine (insn, prev,
1191 NULL_RTX, &new_direct_jump_p)) != 0)
1194 for (nextlinks = LOG_LINKS (prev); nextlinks;
1195 nextlinks = XEXP (nextlinks, 1))
1196 if ((next = try_combine (insn, prev,
1197 XEXP (nextlinks, 0),
1198 &new_direct_jump_p)) != 0)
1202 /* Do the same for an insn that explicitly references CC0. */
1203 if (NONJUMP_INSN_P (insn)
1204 && (prev = prev_nonnote_insn (insn)) != 0
1205 && NONJUMP_INSN_P (prev)
1206 && sets_cc0_p (PATTERN (prev))
1207 && GET_CODE (PATTERN (insn)) == SET
1208 && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (insn))))
1210 if ((next = try_combine (insn, prev,
1211 NULL_RTX, &new_direct_jump_p)) != 0)
1214 for (nextlinks = LOG_LINKS (prev); nextlinks;
1215 nextlinks = XEXP (nextlinks, 1))
1216 if ((next = try_combine (insn, prev,
1217 XEXP (nextlinks, 0),
1218 &new_direct_jump_p)) != 0)
1222 /* Finally, see if any of the insns that this insn links to
1223 explicitly references CC0. If so, try this insn, that insn,
1224 and its predecessor if it sets CC0. */
1225 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
1226 if (NONJUMP_INSN_P (XEXP (links, 0))
1227 && GET_CODE (PATTERN (XEXP (links, 0))) == SET
1228 && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (XEXP (links, 0))))
1229 && (prev = prev_nonnote_insn (XEXP (links, 0))) != 0
1230 && NONJUMP_INSN_P (prev)
1231 && sets_cc0_p (PATTERN (prev))
1232 && (next = try_combine (insn, XEXP (links, 0),
1233 prev, &new_direct_jump_p)) != 0)
1237 /* Try combining an insn with two different insns whose results it
1239 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
1240 for (nextlinks = XEXP (links, 1); nextlinks;
1241 nextlinks = XEXP (nextlinks, 1))
1242 if ((next = try_combine (insn, XEXP (links, 0),
1243 XEXP (nextlinks, 0),
1244 &new_direct_jump_p)) != 0)
1247 /* Try this insn with each REG_EQUAL note it links back to. */
1248 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
1251 rtx temp = XEXP (links, 0);
1252 if ((set = single_set (temp)) != 0
1253 && (note = find_reg_equal_equiv_note (temp)) != 0
1254 && (note = XEXP (note, 0), GET_CODE (note)) != EXPR_LIST
1255 /* Avoid using a register that may already been marked
1256 dead by an earlier instruction. */
1257 && ! unmentioned_reg_p (note, SET_SRC (set))
1258 && (GET_MODE (note) == VOIDmode
1259 ? SCALAR_INT_MODE_P (GET_MODE (SET_DEST (set)))
1260 : GET_MODE (SET_DEST (set)) == GET_MODE (note)))
1262 /* Temporarily replace the set's source with the
1263 contents of the REG_EQUAL note. The insn will
1264 be deleted or recognized by try_combine. */
1265 rtx orig = SET_SRC (set);
1266 SET_SRC (set) = note;
1268 i2mod_old_rhs = copy_rtx (orig);
1269 i2mod_new_rhs = copy_rtx (note);
1270 next = try_combine (insn, i2mod, NULL_RTX,
1271 &new_direct_jump_p);
1275 SET_SRC (set) = orig;
1280 record_dead_and_set_regs (insn);
1288 default_rtl_profile ();
1291 new_direct_jump_p |= purge_all_dead_edges ();
1292 delete_noop_moves ();
1295 free (uid_log_links);
1296 free (uid_insn_cost);
1297 VEC_free (reg_stat_type, heap, reg_stat);
1300 struct undo *undo, *next;
1301 for (undo = undobuf.frees; undo; undo = next)
1309 total_attempts += combine_attempts;
1310 total_merges += combine_merges;
1311 total_extras += combine_extras;
1312 total_successes += combine_successes;
1314 nonzero_sign_valid = 0;
1315 rtl_hooks = general_rtl_hooks;
1317 /* Make recognizer allow volatile MEMs again. */
1320 return new_direct_jump_p;
1323 /* Wipe the last_xxx fields of reg_stat in preparation for another pass. */
1326 init_reg_last (void)
1331 for (i = 0; VEC_iterate (reg_stat_type, reg_stat, i, p); ++i)
1332 memset (p, 0, offsetof (reg_stat_type, sign_bit_copies));
1335 /* Set up any promoted values for incoming argument registers. */
1338 setup_incoming_promotions (rtx first)
1341 bool strictly_local = false;
1343 for (arg = DECL_ARGUMENTS (current_function_decl); arg;
1344 arg = TREE_CHAIN (arg))
1346 rtx x, reg = DECL_INCOMING_RTL (arg);
1348 enum machine_mode mode1, mode2, mode3, mode4;
1350 /* Only continue if the incoming argument is in a register. */
1354 /* Determine, if possible, whether all call sites of the current
1355 function lie within the current compilation unit. (This does
1356 take into account the exporting of a function via taking its
1357 address, and so forth.) */
1358 strictly_local = cgraph_local_info (current_function_decl)->local;
1360 /* The mode and signedness of the argument before any promotions happen
1361 (equal to the mode of the pseudo holding it at that stage). */
1362 mode1 = TYPE_MODE (TREE_TYPE (arg));
1363 uns1 = TYPE_UNSIGNED (TREE_TYPE (arg));
1365 /* The mode and signedness of the argument after any source language and
1366 TARGET_PROMOTE_PROTOTYPES-driven promotions. */
1367 mode2 = TYPE_MODE (DECL_ARG_TYPE (arg));
1368 uns3 = TYPE_UNSIGNED (DECL_ARG_TYPE (arg));
1370 /* The mode and signedness of the argument as it is actually passed,
1371 after any TARGET_PROMOTE_FUNCTION_ARGS-driven ABI promotions. */
1372 mode3 = promote_function_mode (DECL_ARG_TYPE (arg), mode2, &uns3,
1373 TREE_TYPE (cfun->decl), 0);
1375 /* The mode of the register in which the argument is being passed. */
1376 mode4 = GET_MODE (reg);
1378 /* Eliminate sign extensions in the callee when:
1379 (a) A mode promotion has occurred; */
1382 /* (b) The mode of the register is the same as the mode of
1383 the argument as it is passed; */
1386 /* (c) There's no language level extension; */
1389 /* (c.1) All callers are from the current compilation unit. If that's
1390 the case we don't have to rely on an ABI, we only have to know
1391 what we're generating right now, and we know that we will do the
1392 mode1 to mode2 promotion with the given sign. */
1393 else if (!strictly_local)
1395 /* (c.2) The combination of the two promotions is useful. This is
1396 true when the signs match, or if the first promotion is unsigned.
1397 In the later case, (sign_extend (zero_extend x)) is the same as
1398 (zero_extend (zero_extend x)), so make sure to force UNS3 true. */
1404 /* Record that the value was promoted from mode1 to mode3,
1405 so that any sign extension at the head of the current
1406 function may be eliminated. */
1407 x = gen_rtx_CLOBBER (mode1, const0_rtx);
1408 x = gen_rtx_fmt_e ((uns3 ? ZERO_EXTEND : SIGN_EXTEND), mode3, x);
1409 record_value_for_reg (reg, first, x);
1413 /* Called via note_stores. If X is a pseudo that is narrower than
1414 HOST_BITS_PER_WIDE_INT and is being set, record what bits are known zero.
1416 If we are setting only a portion of X and we can't figure out what
1417 portion, assume all bits will be used since we don't know what will
1420 Similarly, set how many bits of X are known to be copies of the sign bit
1421 at all locations in the function. This is the smallest number implied
1425 set_nonzero_bits_and_sign_copies (rtx x, const_rtx set, void *data)
1427 rtx insn = (rtx) data;
1431 && REGNO (x) >= FIRST_PSEUDO_REGISTER
1432 /* If this register is undefined at the start of the file, we can't
1433 say what its contents were. */
1434 && ! REGNO_REG_SET_P
1435 (DF_LR_IN (ENTRY_BLOCK_PTR->next_bb), REGNO (x))
1436 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT)
1438 reg_stat_type *rsp = VEC_index (reg_stat_type, reg_stat, REGNO (x));
1440 if (set == 0 || GET_CODE (set) == CLOBBER)
1442 rsp->nonzero_bits = GET_MODE_MASK (GET_MODE (x));
1443 rsp->sign_bit_copies = 1;
1447 /* If this register is being initialized using itself, and the
1448 register is uninitialized in this basic block, and there are
1449 no LOG_LINKS which set the register, then part of the
1450 register is uninitialized. In that case we can't assume
1451 anything about the number of nonzero bits.
1453 ??? We could do better if we checked this in
1454 reg_{nonzero_bits,num_sign_bit_copies}_for_combine. Then we
1455 could avoid making assumptions about the insn which initially
1456 sets the register, while still using the information in other
1457 insns. We would have to be careful to check every insn
1458 involved in the combination. */
1461 && reg_referenced_p (x, PATTERN (insn))
1462 && !REGNO_REG_SET_P (DF_LR_IN (BLOCK_FOR_INSN (insn)),
1467 for (link = LOG_LINKS (insn); link; link = XEXP (link, 1))
1469 if (dead_or_set_p (XEXP (link, 0), x))
1474 rsp->nonzero_bits = GET_MODE_MASK (GET_MODE (x));
1475 rsp->sign_bit_copies = 1;
1480 /* If this is a complex assignment, see if we can convert it into a
1481 simple assignment. */
1482 set = expand_field_assignment (set);
1484 /* If this is a simple assignment, or we have a paradoxical SUBREG,
1485 set what we know about X. */
1487 if (SET_DEST (set) == x
1488 || (GET_CODE (SET_DEST (set)) == SUBREG
1489 && (GET_MODE_SIZE (GET_MODE (SET_DEST (set)))
1490 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (set)))))
1491 && SUBREG_REG (SET_DEST (set)) == x))
1493 rtx src = SET_SRC (set);
1495 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
1496 /* If X is narrower than a word and SRC is a non-negative
1497 constant that would appear negative in the mode of X,
1498 sign-extend it for use in reg_stat[].nonzero_bits because some
1499 machines (maybe most) will actually do the sign-extension
1500 and this is the conservative approach.
1502 ??? For 2.5, try to tighten up the MD files in this regard
1503 instead of this kludge. */
1505 if (GET_MODE_BITSIZE (GET_MODE (x)) < BITS_PER_WORD
1506 && CONST_INT_P (src)
1508 && 0 != (INTVAL (src)
1509 & ((HOST_WIDE_INT) 1
1510 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
1511 src = GEN_INT (INTVAL (src)
1512 | ((HOST_WIDE_INT) (-1)
1513 << GET_MODE_BITSIZE (GET_MODE (x))));
1516 /* Don't call nonzero_bits if it cannot change anything. */
1517 if (rsp->nonzero_bits != ~(unsigned HOST_WIDE_INT) 0)
1518 rsp->nonzero_bits |= nonzero_bits (src, nonzero_bits_mode);
1519 num = num_sign_bit_copies (SET_SRC (set), GET_MODE (x));
1520 if (rsp->sign_bit_copies == 0
1521 || rsp->sign_bit_copies > num)
1522 rsp->sign_bit_copies = num;
1526 rsp->nonzero_bits = GET_MODE_MASK (GET_MODE (x));
1527 rsp->sign_bit_copies = 1;
1532 /* See if INSN can be combined into I3. PRED and SUCC are optionally
1533 insns that were previously combined into I3 or that will be combined
1534 into the merger of INSN and I3.
1536 Return 0 if the combination is not allowed for any reason.
1538 If the combination is allowed, *PDEST will be set to the single
1539 destination of INSN and *PSRC to the single source, and this function
1543 can_combine_p (rtx insn, rtx i3, rtx pred ATTRIBUTE_UNUSED, rtx succ,
1544 rtx *pdest, rtx *psrc)
1553 int all_adjacent = (succ ? (next_active_insn (insn) == succ
1554 && next_active_insn (succ) == i3)
1555 : next_active_insn (insn) == i3);
1557 /* Can combine only if previous insn is a SET of a REG, a SUBREG or CC0.
1558 or a PARALLEL consisting of such a SET and CLOBBERs.
1560 If INSN has CLOBBER parallel parts, ignore them for our processing.
1561 By definition, these happen during the execution of the insn. When it
1562 is merged with another insn, all bets are off. If they are, in fact,
1563 needed and aren't also supplied in I3, they may be added by
1564 recog_for_combine. Otherwise, it won't match.
1566 We can also ignore a SET whose SET_DEST is mentioned in a REG_UNUSED
1569 Get the source and destination of INSN. If more than one, can't
1572 if (GET_CODE (PATTERN (insn)) == SET)
1573 set = PATTERN (insn);
1574 else if (GET_CODE (PATTERN (insn)) == PARALLEL
1575 && GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == SET)
1577 for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
1579 rtx elt = XVECEXP (PATTERN (insn), 0, i);
1581 switch (GET_CODE (elt))
1583 /* This is important to combine floating point insns
1584 for the SH4 port. */
1586 /* Combining an isolated USE doesn't make sense.
1587 We depend here on combinable_i3pat to reject them. */
1588 /* The code below this loop only verifies that the inputs of
1589 the SET in INSN do not change. We call reg_set_between_p
1590 to verify that the REG in the USE does not change between
1592 If the USE in INSN was for a pseudo register, the matching
1593 insn pattern will likely match any register; combining this
1594 with any other USE would only be safe if we knew that the
1595 used registers have identical values, or if there was
1596 something to tell them apart, e.g. different modes. For
1597 now, we forgo such complicated tests and simply disallow
1598 combining of USES of pseudo registers with any other USE. */
1599 if (REG_P (XEXP (elt, 0))
1600 && GET_CODE (PATTERN (i3)) == PARALLEL)
1602 rtx i3pat = PATTERN (i3);
1603 int i = XVECLEN (i3pat, 0) - 1;
1604 unsigned int regno = REGNO (XEXP (elt, 0));
1608 rtx i3elt = XVECEXP (i3pat, 0, i);
1610 if (GET_CODE (i3elt) == USE
1611 && REG_P (XEXP (i3elt, 0))
1612 && (REGNO (XEXP (i3elt, 0)) == regno
1613 ? reg_set_between_p (XEXP (elt, 0),
1614 PREV_INSN (insn), i3)
1615 : regno >= FIRST_PSEUDO_REGISTER))
1622 /* We can ignore CLOBBERs. */
1627 /* Ignore SETs whose result isn't used but not those that
1628 have side-effects. */
1629 if (find_reg_note (insn, REG_UNUSED, SET_DEST (elt))
1630 && insn_nothrow_p (insn)
1631 && !side_effects_p (elt))
1634 /* If we have already found a SET, this is a second one and
1635 so we cannot combine with this insn. */
1643 /* Anything else means we can't combine. */
1649 /* If SET_SRC is an ASM_OPERANDS we can't throw away these CLOBBERs,
1650 so don't do anything with it. */
1651 || GET_CODE (SET_SRC (set)) == ASM_OPERANDS)
1660 set = expand_field_assignment (set);
1661 src = SET_SRC (set), dest = SET_DEST (set);
1663 /* Don't eliminate a store in the stack pointer. */
1664 if (dest == stack_pointer_rtx
1665 /* Don't combine with an insn that sets a register to itself if it has
1666 a REG_EQUAL note. This may be part of a LIBCALL sequence. */
1667 || (rtx_equal_p (src, dest) && find_reg_note (insn, REG_EQUAL, NULL_RTX))
1668 /* Can't merge an ASM_OPERANDS. */
1669 || GET_CODE (src) == ASM_OPERANDS
1670 /* Can't merge a function call. */
1671 || GET_CODE (src) == CALL
1672 /* Don't eliminate a function call argument. */
1674 && (find_reg_fusage (i3, USE, dest)
1676 && REGNO (dest) < FIRST_PSEUDO_REGISTER
1677 && global_regs[REGNO (dest)])))
1678 /* Don't substitute into an incremented register. */
1679 || FIND_REG_INC_NOTE (i3, dest)
1680 || (succ && FIND_REG_INC_NOTE (succ, dest))
1681 /* Don't substitute into a non-local goto, this confuses CFG. */
1682 || (JUMP_P (i3) && find_reg_note (i3, REG_NON_LOCAL_GOTO, NULL_RTX))
1683 /* Make sure that DEST is not used after SUCC but before I3. */
1684 || (succ && ! all_adjacent
1685 && reg_used_between_p (dest, succ, i3))
1686 /* Make sure that the value that is to be substituted for the register
1687 does not use any registers whose values alter in between. However,
1688 If the insns are adjacent, a use can't cross a set even though we
1689 think it might (this can happen for a sequence of insns each setting
1690 the same destination; last_set of that register might point to
1691 a NOTE). If INSN has a REG_EQUIV note, the register is always
1692 equivalent to the memory so the substitution is valid even if there
1693 are intervening stores. Also, don't move a volatile asm or
1694 UNSPEC_VOLATILE across any other insns. */
1697 || ! find_reg_note (insn, REG_EQUIV, src))
1698 && use_crosses_set_p (src, DF_INSN_LUID (insn)))
1699 || (GET_CODE (src) == ASM_OPERANDS && MEM_VOLATILE_P (src))
1700 || GET_CODE (src) == UNSPEC_VOLATILE))
1701 /* Don't combine across a CALL_INSN, because that would possibly
1702 change whether the life span of some REGs crosses calls or not,
1703 and it is a pain to update that information.
1704 Exception: if source is a constant, moving it later can't hurt.
1705 Accept that as a special case. */
1706 || (DF_INSN_LUID (insn) < last_call_luid && ! CONSTANT_P (src)))
1709 /* DEST must either be a REG or CC0. */
1712 /* If register alignment is being enforced for multi-word items in all
1713 cases except for parameters, it is possible to have a register copy
1714 insn referencing a hard register that is not allowed to contain the
1715 mode being copied and which would not be valid as an operand of most
1716 insns. Eliminate this problem by not combining with such an insn.
1718 Also, on some machines we don't want to extend the life of a hard
1722 && ((REGNO (dest) < FIRST_PSEUDO_REGISTER
1723 && ! HARD_REGNO_MODE_OK (REGNO (dest), GET_MODE (dest)))
1724 /* Don't extend the life of a hard register unless it is
1725 user variable (if we have few registers) or it can't
1726 fit into the desired register (meaning something special
1728 Also avoid substituting a return register into I3, because
1729 reload can't handle a conflict with constraints of other
1731 || (REGNO (src) < FIRST_PSEUDO_REGISTER
1732 && ! HARD_REGNO_MODE_OK (REGNO (src), GET_MODE (src)))))
1735 else if (GET_CODE (dest) != CC0)
1739 if (GET_CODE (PATTERN (i3)) == PARALLEL)
1740 for (i = XVECLEN (PATTERN (i3), 0) - 1; i >= 0; i--)
1741 if (GET_CODE (XVECEXP (PATTERN (i3), 0, i)) == CLOBBER)
1743 /* Don't substitute for a register intended as a clobberable
1745 rtx reg = XEXP (XVECEXP (PATTERN (i3), 0, i), 0);
1746 if (rtx_equal_p (reg, dest))
1749 /* If the clobber represents an earlyclobber operand, we must not
1750 substitute an expression containing the clobbered register.
1751 As we do not analyze the constraint strings here, we have to
1752 make the conservative assumption. However, if the register is
1753 a fixed hard reg, the clobber cannot represent any operand;
1754 we leave it up to the machine description to either accept or
1755 reject use-and-clobber patterns. */
1757 || REGNO (reg) >= FIRST_PSEUDO_REGISTER
1758 || !fixed_regs[REGNO (reg)])
1759 if (reg_overlap_mentioned_p (reg, src))
1763 /* If INSN contains anything volatile, or is an `asm' (whether volatile
1764 or not), reject, unless nothing volatile comes between it and I3 */
1766 if (GET_CODE (src) == ASM_OPERANDS || volatile_refs_p (src))
1768 /* Make sure succ doesn't contain a volatile reference. */
1769 if (succ != 0 && volatile_refs_p (PATTERN (succ)))
1772 for (p = NEXT_INSN (insn); p != i3; p = NEXT_INSN (p))
1773 if (INSN_P (p) && p != succ && volatile_refs_p (PATTERN (p)))
1777 /* If INSN is an asm, and DEST is a hard register, reject, since it has
1778 to be an explicit register variable, and was chosen for a reason. */
1780 if (GET_CODE (src) == ASM_OPERANDS
1781 && REG_P (dest) && REGNO (dest) < FIRST_PSEUDO_REGISTER)
1784 /* If there are any volatile insns between INSN and I3, reject, because
1785 they might affect machine state. */
1787 for (p = NEXT_INSN (insn); p != i3; p = NEXT_INSN (p))
1788 if (INSN_P (p) && p != succ && volatile_insn_p (PATTERN (p)))
1791 /* If INSN contains an autoincrement or autodecrement, make sure that
1792 register is not used between there and I3, and not already used in
1793 I3 either. Neither must it be used in PRED or SUCC, if they exist.
1794 Also insist that I3 not be a jump; if it were one
1795 and the incremented register were spilled, we would lose. */
1798 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
1799 if (REG_NOTE_KIND (link) == REG_INC
1801 || reg_used_between_p (XEXP (link, 0), insn, i3)
1802 || (pred != NULL_RTX
1803 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (pred)))
1804 || (succ != NULL_RTX
1805 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (succ)))
1806 || reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i3))))
1811 /* Don't combine an insn that follows a CC0-setting insn.
1812 An insn that uses CC0 must not be separated from the one that sets it.
1813 We do, however, allow I2 to follow a CC0-setting insn if that insn
1814 is passed as I1; in that case it will be deleted also.
1815 We also allow combining in this case if all the insns are adjacent
1816 because that would leave the two CC0 insns adjacent as well.
1817 It would be more logical to test whether CC0 occurs inside I1 or I2,
1818 but that would be much slower, and this ought to be equivalent. */
1820 p = prev_nonnote_insn (insn);
1821 if (p && p != pred && NONJUMP_INSN_P (p) && sets_cc0_p (PATTERN (p))
1826 /* If we get here, we have passed all the tests and the combination is
1835 /* LOC is the location within I3 that contains its pattern or the component
1836 of a PARALLEL of the pattern. We validate that it is valid for combining.
1838 One problem is if I3 modifies its output, as opposed to replacing it
1839 entirely, we can't allow the output to contain I2DEST or I1DEST as doing
1840 so would produce an insn that is not equivalent to the original insns.
1844 (set (reg:DI 101) (reg:DI 100))
1845 (set (subreg:SI (reg:DI 101) 0) <foo>)
1847 This is NOT equivalent to:
1849 (parallel [(set (subreg:SI (reg:DI 100) 0) <foo>)
1850 (set (reg:DI 101) (reg:DI 100))])
1852 Not only does this modify 100 (in which case it might still be valid
1853 if 100 were dead in I2), it sets 101 to the ORIGINAL value of 100.
1855 We can also run into a problem if I2 sets a register that I1
1856 uses and I1 gets directly substituted into I3 (not via I2). In that
1857 case, we would be getting the wrong value of I2DEST into I3, so we
1858 must reject the combination. This case occurs when I2 and I1 both
1859 feed into I3, rather than when I1 feeds into I2, which feeds into I3.
1860 If I1_NOT_IN_SRC is nonzero, it means that finding I1 in the source
1861 of a SET must prevent combination from occurring.
1863 Before doing the above check, we first try to expand a field assignment
1864 into a set of logical operations.
1866 If PI3_DEST_KILLED is nonzero, it is a pointer to a location in which
1867 we place a register that is both set and used within I3. If more than one
1868 such register is detected, we fail.
1870 Return 1 if the combination is valid, zero otherwise. */
1873 combinable_i3pat (rtx i3, rtx *loc, rtx i2dest, rtx i1dest,
1874 int i1_not_in_src, rtx *pi3dest_killed)
1878 if (GET_CODE (x) == SET)
1881 rtx dest = SET_DEST (set);
1882 rtx src = SET_SRC (set);
1883 rtx inner_dest = dest;
1886 while (GET_CODE (inner_dest) == STRICT_LOW_PART
1887 || GET_CODE (inner_dest) == SUBREG
1888 || GET_CODE (inner_dest) == ZERO_EXTRACT)
1889 inner_dest = XEXP (inner_dest, 0);
1891 /* Check for the case where I3 modifies its output, as discussed
1892 above. We don't want to prevent pseudos from being combined
1893 into the address of a MEM, so only prevent the combination if
1894 i1 or i2 set the same MEM. */
1895 if ((inner_dest != dest &&
1896 (!MEM_P (inner_dest)
1897 || rtx_equal_p (i2dest, inner_dest)
1898 || (i1dest && rtx_equal_p (i1dest, inner_dest)))
1899 && (reg_overlap_mentioned_p (i2dest, inner_dest)
1900 || (i1dest && reg_overlap_mentioned_p (i1dest, inner_dest))))
1902 /* This is the same test done in can_combine_p except we can't test
1903 all_adjacent; we don't have to, since this instruction will stay
1904 in place, thus we are not considering increasing the lifetime of
1907 Also, if this insn sets a function argument, combining it with
1908 something that might need a spill could clobber a previous
1909 function argument; the all_adjacent test in can_combine_p also
1910 checks this; here, we do a more specific test for this case. */
1912 || (REG_P (inner_dest)
1913 && REGNO (inner_dest) < FIRST_PSEUDO_REGISTER
1914 && (! HARD_REGNO_MODE_OK (REGNO (inner_dest),
1915 GET_MODE (inner_dest))))
1916 || (i1_not_in_src && reg_overlap_mentioned_p (i1dest, src)))
1919 /* If DEST is used in I3, it is being killed in this insn, so
1920 record that for later. We have to consider paradoxical
1921 subregs here, since they kill the whole register, but we
1922 ignore partial subregs, STRICT_LOW_PART, etc.
1923 Never add REG_DEAD notes for the FRAME_POINTER_REGNUM or the
1924 STACK_POINTER_REGNUM, since these are always considered to be
1925 live. Similarly for ARG_POINTER_REGNUM if it is fixed. */
1927 if (GET_CODE (subdest) == SUBREG
1928 && (GET_MODE_SIZE (GET_MODE (subdest))
1929 >= GET_MODE_SIZE (GET_MODE (SUBREG_REG (subdest)))))
1930 subdest = SUBREG_REG (subdest);
1933 && reg_referenced_p (subdest, PATTERN (i3))
1934 && REGNO (subdest) != FRAME_POINTER_REGNUM
1935 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
1936 && REGNO (subdest) != HARD_FRAME_POINTER_REGNUM
1938 #if ARG_POINTER_REGNUM != FRAME_POINTER_REGNUM
1939 && (REGNO (subdest) != ARG_POINTER_REGNUM
1940 || ! fixed_regs [REGNO (subdest)])
1942 && REGNO (subdest) != STACK_POINTER_REGNUM)
1944 if (*pi3dest_killed)
1947 *pi3dest_killed = subdest;
1951 else if (GET_CODE (x) == PARALLEL)
1955 for (i = 0; i < XVECLEN (x, 0); i++)
1956 if (! combinable_i3pat (i3, &XVECEXP (x, 0, i), i2dest, i1dest,
1957 i1_not_in_src, pi3dest_killed))
1964 /* Return 1 if X is an arithmetic expression that contains a multiplication
1965 and division. We don't count multiplications by powers of two here. */
1968 contains_muldiv (rtx x)
1970 switch (GET_CODE (x))
1972 case MOD: case DIV: case UMOD: case UDIV:
1976 return ! (CONST_INT_P (XEXP (x, 1))
1977 && exact_log2 (INTVAL (XEXP (x, 1))) >= 0);
1980 return contains_muldiv (XEXP (x, 0))
1981 || contains_muldiv (XEXP (x, 1));
1984 return contains_muldiv (XEXP (x, 0));
1990 /* Determine whether INSN can be used in a combination. Return nonzero if
1991 not. This is used in try_combine to detect early some cases where we
1992 can't perform combinations. */
1995 cant_combine_insn_p (rtx insn)
2000 /* If this isn't really an insn, we can't do anything.
2001 This can occur when flow deletes an insn that it has merged into an
2002 auto-increment address. */
2003 if (! INSN_P (insn))
2006 /* Never combine loads and stores involving hard regs that are likely
2007 to be spilled. The register allocator can usually handle such
2008 reg-reg moves by tying. If we allow the combiner to make
2009 substitutions of likely-spilled regs, reload might die.
2010 As an exception, we allow combinations involving fixed regs; these are
2011 not available to the register allocator so there's no risk involved. */
2013 set = single_set (insn);
2016 src = SET_SRC (set);
2017 dest = SET_DEST (set);
2018 if (GET_CODE (src) == SUBREG)
2019 src = SUBREG_REG (src);
2020 if (GET_CODE (dest) == SUBREG)
2021 dest = SUBREG_REG (dest);
2022 if (REG_P (src) && REG_P (dest)
2023 && ((REGNO (src) < FIRST_PSEUDO_REGISTER
2024 && ! fixed_regs[REGNO (src)]
2025 && CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (REGNO (src))))
2026 || (REGNO (dest) < FIRST_PSEUDO_REGISTER
2027 && ! fixed_regs[REGNO (dest)]
2028 && CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (REGNO (dest))))))
2034 struct likely_spilled_retval_info
2036 unsigned regno, nregs;
2040 /* Called via note_stores by likely_spilled_retval_p. Remove from info->mask
2041 hard registers that are known to be written to / clobbered in full. */
2043 likely_spilled_retval_1 (rtx x, const_rtx set, void *data)
2045 struct likely_spilled_retval_info *const info =
2046 (struct likely_spilled_retval_info *) data;
2047 unsigned regno, nregs;
2050 if (!REG_P (XEXP (set, 0)))
2053 if (regno >= info->regno + info->nregs)
2055 nregs = hard_regno_nregs[regno][GET_MODE (x)];
2056 if (regno + nregs <= info->regno)
2058 new_mask = (2U << (nregs - 1)) - 1;
2059 if (regno < info->regno)
2060 new_mask >>= info->regno - regno;
2062 new_mask <<= regno - info->regno;
2063 info->mask &= ~new_mask;
2066 /* Return nonzero iff part of the return value is live during INSN, and
2067 it is likely spilled. This can happen when more than one insn is needed
2068 to copy the return value, e.g. when we consider to combine into the
2069 second copy insn for a complex value. */
2072 likely_spilled_retval_p (rtx insn)
2074 rtx use = BB_END (this_basic_block);
2076 unsigned regno, nregs;
2077 /* We assume here that no machine mode needs more than
2078 32 hard registers when the value overlaps with a register
2079 for which TARGET_FUNCTION_VALUE_REGNO_P is true. */
2081 struct likely_spilled_retval_info info;
2083 if (!NONJUMP_INSN_P (use) || GET_CODE (PATTERN (use)) != USE || insn == use)
2085 reg = XEXP (PATTERN (use), 0);
2086 if (!REG_P (reg) || !targetm.calls.function_value_regno_p (REGNO (reg)))
2088 regno = REGNO (reg);
2089 nregs = hard_regno_nregs[regno][GET_MODE (reg)];
2092 mask = (2U << (nregs - 1)) - 1;
2094 /* Disregard parts of the return value that are set later. */
2098 for (p = PREV_INSN (use); info.mask && p != insn; p = PREV_INSN (p))
2100 note_stores (PATTERN (p), likely_spilled_retval_1, &info);
2103 /* Check if any of the (probably) live return value registers is
2108 if ((mask & 1 << nregs)
2109 && CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (regno + nregs)))
2115 /* Adjust INSN after we made a change to its destination.
2117 Changing the destination can invalidate notes that say something about
2118 the results of the insn and a LOG_LINK pointing to the insn. */
2121 adjust_for_new_dest (rtx insn)
2123 /* For notes, be conservative and simply remove them. */
2124 remove_reg_equal_equiv_notes (insn);
2126 /* The new insn will have a destination that was previously the destination
2127 of an insn just above it. Call distribute_links to make a LOG_LINK from
2128 the next use of that destination. */
2129 distribute_links (gen_rtx_INSN_LIST (VOIDmode, insn, NULL_RTX));
2131 df_insn_rescan (insn);
2134 /* Return TRUE if combine can reuse reg X in mode MODE.
2135 ADDED_SETS is nonzero if the original set is still required. */
2137 can_change_dest_mode (rtx x, int added_sets, enum machine_mode mode)
2145 /* Allow hard registers if the new mode is legal, and occupies no more
2146 registers than the old mode. */
2147 if (regno < FIRST_PSEUDO_REGISTER)
2148 return (HARD_REGNO_MODE_OK (regno, mode)
2149 && (hard_regno_nregs[regno][GET_MODE (x)]
2150 >= hard_regno_nregs[regno][mode]));
2152 /* Or a pseudo that is only used once. */
2153 return (REG_N_SETS (regno) == 1 && !added_sets
2154 && !REG_USERVAR_P (x));
2158 /* Check whether X, the destination of a set, refers to part of
2159 the register specified by REG. */
2162 reg_subword_p (rtx x, rtx reg)
2164 /* Check that reg is an integer mode register. */
2165 if (!REG_P (reg) || GET_MODE_CLASS (GET_MODE (reg)) != MODE_INT)
2168 if (GET_CODE (x) == STRICT_LOW_PART
2169 || GET_CODE (x) == ZERO_EXTRACT)
2172 return GET_CODE (x) == SUBREG
2173 && SUBREG_REG (x) == reg
2174 && GET_MODE_CLASS (GET_MODE (x)) == MODE_INT;
2178 /* Replace auto-increment addressing modes with explicit operations to
2179 access the same addresses without modifying the corresponding
2180 registers. If AFTER holds, SRC is meant to be reused after the
2181 side effect, otherwise it is to be reused before that. */
2184 cleanup_auto_inc_dec (rtx src, bool after, enum machine_mode mem_mode)
2187 const RTX_CODE code = GET_CODE (x);
2203 /* SCRATCH must be shared because they represent distinct values. */
2206 if (REG_P (XEXP (x, 0)) && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER)
2211 if (shared_const_p (x))
2216 mem_mode = GET_MODE (x);
2223 gcc_assert (mem_mode != VOIDmode && mem_mode != BLKmode);
2224 if (after == (code == PRE_INC || code == PRE_DEC))
2225 x = cleanup_auto_inc_dec (XEXP (x, 0), after, mem_mode);
2227 x = gen_rtx_PLUS (GET_MODE (x),
2228 cleanup_auto_inc_dec (XEXP (x, 0), after, mem_mode),
2229 GEN_INT ((code == PRE_INC || code == POST_INC)
2230 ? GET_MODE_SIZE (mem_mode)
2231 : -GET_MODE_SIZE (mem_mode)));
2236 if (after == (code == PRE_MODIFY))
2240 return cleanup_auto_inc_dec (x, after, mem_mode);
2246 /* Copy the various flags, fields, and other information. We assume
2247 that all fields need copying, and then clear the fields that should
2248 not be copied. That is the sensible default behavior, and forces
2249 us to explicitly document why we are *not* copying a flag. */
2250 x = shallow_copy_rtx (x);
2252 /* We do not copy the USED flag, which is used as a mark bit during
2253 walks over the RTL. */
2254 RTX_FLAG (x, used) = 0;
2256 /* We do not copy FRAME_RELATED for INSNs. */
2258 RTX_FLAG (x, frame_related) = 0;
2260 fmt = GET_RTX_FORMAT (code);
2261 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
2263 XEXP (x, i) = cleanup_auto_inc_dec (XEXP (x, i), after, mem_mode);
2264 else if (fmt[i] == 'E' || fmt[i] == 'V')
2267 XVEC (x, i) = rtvec_alloc (XVECLEN (x, i));
2268 for (j = 0; j < XVECLEN (x, i); j++)
2270 = cleanup_auto_inc_dec (XVECEXP (src, i, j), after, mem_mode);
2277 /* Auxiliary data structure for propagate_for_debug_stmt. */
2279 struct rtx_subst_pair
2286 /* DATA points to an rtx_subst_pair. Return the value that should be
2290 propagate_for_debug_subst (rtx from, const_rtx old_rtx, void *data)
2292 struct rtx_subst_pair *pair = (struct rtx_subst_pair *)data;
2294 if (!rtx_equal_p (from, old_rtx))
2296 if (!pair->adjusted)
2298 pair->adjusted = true;
2300 pair->to = cleanup_auto_inc_dec (pair->to, pair->after, VOIDmode);
2302 pair->to = copy_rtx (pair->to);
2304 pair->to = make_compound_operation (pair->to, SET);
2307 return copy_rtx (pair->to);
2310 /* Replace occurrences of DEST with SRC in DEBUG_INSNs between INSN
2311 and LAST. If MOVE holds, debug insns must also be moved past
2315 propagate_for_debug (rtx insn, rtx last, rtx dest, rtx src, bool move)
2317 rtx next, move_pos = move ? last : NULL_RTX, loc;
2319 struct rtx_subst_pair p;
2324 next = NEXT_INSN (insn);
2325 while (next != last)
2328 next = NEXT_INSN (insn);
2329 if (DEBUG_INSN_P (insn))
2331 loc = simplify_replace_fn_rtx (INSN_VAR_LOCATION_LOC (insn),
2332 dest, propagate_for_debug_subst, &p);
2333 if (loc == INSN_VAR_LOCATION_LOC (insn))
2335 INSN_VAR_LOCATION_LOC (insn) = loc;
2339 PREV_INSN (insn) = NEXT_INSN (insn) = NULL_RTX;
2340 move_pos = emit_debug_insn_after (insn, move_pos);
2343 df_insn_rescan (insn);
2348 /* Delete the unconditional jump INSN and adjust the CFG correspondingly.
2349 Note that the INSN should be deleted *after* removing dead edges, so
2350 that the kept edge is the fallthrough edge for a (set (pc) (pc))
2351 but not for a (set (pc) (label_ref FOO)). */
2354 update_cfg_for_uncondjump (rtx insn)
2356 basic_block bb = BLOCK_FOR_INSN (insn);
2357 bool at_end = (BB_END (bb) == insn);
2360 purge_dead_edges (bb);
2363 if (at_end && EDGE_COUNT (bb->succs) == 1)
2364 single_succ_edge (bb)->flags |= EDGE_FALLTHRU;
2368 /* Try to combine the insns I1 and I2 into I3.
2369 Here I1 and I2 appear earlier than I3.
2370 I1 can be zero; then we combine just I2 into I3.
2372 If we are combining three insns and the resulting insn is not recognized,
2373 try splitting it into two insns. If that happens, I2 and I3 are retained
2374 and I1 is pseudo-deleted by turning it into a NOTE. Otherwise, I1 and I2
2377 Return 0 if the combination does not work. Then nothing is changed.
2378 If we did the combination, return the insn at which combine should
2381 Set NEW_DIRECT_JUMP_P to a nonzero value if try_combine creates a
2382 new direct jump instruction. */
2385 try_combine (rtx i3, rtx i2, rtx i1, int *new_direct_jump_p)
2387 /* New patterns for I3 and I2, respectively. */
2388 rtx newpat, newi2pat = 0;
2389 rtvec newpat_vec_with_clobbers = 0;
2390 int substed_i2 = 0, substed_i1 = 0;
2391 /* Indicates need to preserve SET in I1 or I2 in I3 if it is not dead. */
2392 int added_sets_1, added_sets_2;
2393 /* Total number of SETs to put into I3. */
2395 /* Nonzero if I2's body now appears in I3. */
2397 /* INSN_CODEs for new I3, new I2, and user of condition code. */
2398 int insn_code_number, i2_code_number = 0, other_code_number = 0;
2399 /* Contains I3 if the destination of I3 is used in its source, which means
2400 that the old life of I3 is being killed. If that usage is placed into
2401 I2 and not in I3, a REG_DEAD note must be made. */
2402 rtx i3dest_killed = 0;
2403 /* SET_DEST and SET_SRC of I2 and I1. */
2404 rtx i2dest = 0, i2src = 0, i1dest = 0, i1src = 0;
2405 /* Set if I2DEST was reused as a scratch register. */
2406 bool i2scratch = false;
2407 /* PATTERN (I1) and PATTERN (I2), or a copy of it in certain cases. */
2408 rtx i1pat = 0, i2pat = 0;
2409 /* Indicates if I2DEST or I1DEST is in I2SRC or I1_SRC. */
2410 int i2dest_in_i2src = 0, i1dest_in_i1src = 0, i2dest_in_i1src = 0;
2411 int i2dest_killed = 0, i1dest_killed = 0;
2412 int i1_feeds_i3 = 0;
2413 /* Notes that must be added to REG_NOTES in I3 and I2. */
2414 rtx new_i3_notes, new_i2_notes;
2415 /* Notes that we substituted I3 into I2 instead of the normal case. */
2416 int i3_subst_into_i2 = 0;
2417 /* Notes that I1, I2 or I3 is a MULT operation. */
2420 int changed_i3_dest = 0;
2426 rtx new_other_notes;
2429 /* Exit early if one of the insns involved can't be used for
2431 if (cant_combine_insn_p (i3)
2432 || cant_combine_insn_p (i2)
2433 || (i1 && cant_combine_insn_p (i1))
2434 || likely_spilled_retval_p (i3))
2438 undobuf.other_insn = 0;
2440 /* Reset the hard register usage information. */
2441 CLEAR_HARD_REG_SET (newpat_used_regs);
2443 if (dump_file && (dump_flags & TDF_DETAILS))
2446 fprintf (dump_file, "\nTrying %d, %d -> %d:\n",
2447 INSN_UID (i1), INSN_UID (i2), INSN_UID (i3));
2449 fprintf (dump_file, "\nTrying %d -> %d:\n",
2450 INSN_UID (i2), INSN_UID (i3));
2453 /* If I1 and I2 both feed I3, they can be in any order. To simplify the
2454 code below, set I1 to be the earlier of the two insns. */
2455 if (i1 && DF_INSN_LUID (i1) > DF_INSN_LUID (i2))
2456 temp = i1, i1 = i2, i2 = temp;
2458 added_links_insn = 0;
2460 /* First check for one important special-case that the code below will
2461 not handle. Namely, the case where I1 is zero, I2 is a PARALLEL
2462 and I3 is a SET whose SET_SRC is a SET_DEST in I2. In that case,
2463 we may be able to replace that destination with the destination of I3.
2464 This occurs in the common code where we compute both a quotient and
2465 remainder into a structure, in which case we want to do the computation
2466 directly into the structure to avoid register-register copies.
2468 Note that this case handles both multiple sets in I2 and also
2469 cases where I2 has a number of CLOBBER or PARALLELs.
2471 We make very conservative checks below and only try to handle the
2472 most common cases of this. For example, we only handle the case
2473 where I2 and I3 are adjacent to avoid making difficult register
2476 if (i1 == 0 && NONJUMP_INSN_P (i3) && GET_CODE (PATTERN (i3)) == SET
2477 && REG_P (SET_SRC (PATTERN (i3)))
2478 && REGNO (SET_SRC (PATTERN (i3))) >= FIRST_PSEUDO_REGISTER
2479 && find_reg_note (i3, REG_DEAD, SET_SRC (PATTERN (i3)))
2480 && GET_CODE (PATTERN (i2)) == PARALLEL
2481 && ! side_effects_p (SET_DEST (PATTERN (i3)))
2482 /* If the dest of I3 is a ZERO_EXTRACT or STRICT_LOW_PART, the code
2483 below would need to check what is inside (and reg_overlap_mentioned_p
2484 doesn't support those codes anyway). Don't allow those destinations;
2485 the resulting insn isn't likely to be recognized anyway. */
2486 && GET_CODE (SET_DEST (PATTERN (i3))) != ZERO_EXTRACT
2487 && GET_CODE (SET_DEST (PATTERN (i3))) != STRICT_LOW_PART
2488 && ! reg_overlap_mentioned_p (SET_SRC (PATTERN (i3)),
2489 SET_DEST (PATTERN (i3)))
2490 && next_active_insn (i2) == i3)
2492 rtx p2 = PATTERN (i2);
2494 /* Make sure that the destination of I3,
2495 which we are going to substitute into one output of I2,
2496 is not used within another output of I2. We must avoid making this:
2497 (parallel [(set (mem (reg 69)) ...)
2498 (set (reg 69) ...)])
2499 which is not well-defined as to order of actions.
2500 (Besides, reload can't handle output reloads for this.)
2502 The problem can also happen if the dest of I3 is a memory ref,
2503 if another dest in I2 is an indirect memory ref. */
2504 for (i = 0; i < XVECLEN (p2, 0); i++)
2505 if ((GET_CODE (XVECEXP (p2, 0, i)) == SET
2506 || GET_CODE (XVECEXP (p2, 0, i)) == CLOBBER)
2507 && reg_overlap_mentioned_p (SET_DEST (PATTERN (i3)),
2508 SET_DEST (XVECEXP (p2, 0, i))))
2511 if (i == XVECLEN (p2, 0))
2512 for (i = 0; i < XVECLEN (p2, 0); i++)
2513 if ((GET_CODE (XVECEXP (p2, 0, i)) == SET
2514 || GET_CODE (XVECEXP (p2, 0, i)) == CLOBBER)
2515 && SET_DEST (XVECEXP (p2, 0, i)) == SET_SRC (PATTERN (i3)))
2520 subst_low_luid = DF_INSN_LUID (i2);
2522 added_sets_2 = added_sets_1 = 0;
2523 i2src = SET_DEST (PATTERN (i3));
2524 i2dest = SET_SRC (PATTERN (i3));
2525 i2dest_killed = dead_or_set_p (i2, i2dest);
2527 /* Replace the dest in I2 with our dest and make the resulting
2528 insn the new pattern for I3. Then skip to where we
2529 validate the pattern. Everything was set up above. */
2530 SUBST (SET_DEST (XVECEXP (p2, 0, i)),
2531 SET_DEST (PATTERN (i3)));
2534 i3_subst_into_i2 = 1;
2535 goto validate_replacement;
2539 /* If I2 is setting a pseudo to a constant and I3 is setting some
2540 sub-part of it to another constant, merge them by making a new
2543 && (temp = single_set (i2)) != 0
2544 && (CONST_INT_P (SET_SRC (temp))
2545 || GET_CODE (SET_SRC (temp)) == CONST_DOUBLE)
2546 && GET_CODE (PATTERN (i3)) == SET
2547 && (CONST_INT_P (SET_SRC (PATTERN (i3)))
2548 || GET_CODE (SET_SRC (PATTERN (i3))) == CONST_DOUBLE)
2549 && reg_subword_p (SET_DEST (PATTERN (i3)), SET_DEST (temp)))
2551 rtx dest = SET_DEST (PATTERN (i3));
2555 if (GET_CODE (dest) == ZERO_EXTRACT)
2557 if (CONST_INT_P (XEXP (dest, 1))
2558 && CONST_INT_P (XEXP (dest, 2)))
2560 width = INTVAL (XEXP (dest, 1));
2561 offset = INTVAL (XEXP (dest, 2));
2562 dest = XEXP (dest, 0);
2563 if (BITS_BIG_ENDIAN)
2564 offset = GET_MODE_BITSIZE (GET_MODE (dest)) - width - offset;
2569 if (GET_CODE (dest) == STRICT_LOW_PART)
2570 dest = XEXP (dest, 0);
2571 width = GET_MODE_BITSIZE (GET_MODE (dest));
2577 /* If this is the low part, we're done. */
2578 if (subreg_lowpart_p (dest))
2580 /* Handle the case where inner is twice the size of outer. */
2581 else if (GET_MODE_BITSIZE (GET_MODE (SET_DEST (temp)))
2582 == 2 * GET_MODE_BITSIZE (GET_MODE (dest)))
2583 offset += GET_MODE_BITSIZE (GET_MODE (dest));
2584 /* Otherwise give up for now. */
2590 && (GET_MODE_BITSIZE (GET_MODE (SET_DEST (temp)))
2591 <= HOST_BITS_PER_DOUBLE_INT))
2594 rtx inner = SET_SRC (PATTERN (i3));
2595 rtx outer = SET_SRC (temp);
2597 o = rtx_to_double_int (outer);
2598 i = rtx_to_double_int (inner);
2600 m = double_int_mask (width);
2601 i = double_int_and (i, m);
2602 m = double_int_lshift (m, offset, HOST_BITS_PER_DOUBLE_INT, false);
2603 i = double_int_lshift (i, offset, HOST_BITS_PER_DOUBLE_INT, false);
2604 o = double_int_ior (double_int_and (o, double_int_not (m)), i);
2608 subst_low_luid = DF_INSN_LUID (i2);
2609 added_sets_2 = added_sets_1 = 0;
2610 i2dest = SET_DEST (temp);
2611 i2dest_killed = dead_or_set_p (i2, i2dest);
2613 /* Replace the source in I2 with the new constant and make the
2614 resulting insn the new pattern for I3. Then skip to where we
2615 validate the pattern. Everything was set up above. */
2616 SUBST (SET_SRC (temp),
2617 immed_double_int_const (o, GET_MODE (SET_DEST (temp))));
2619 newpat = PATTERN (i2);
2621 /* The dest of I3 has been replaced with the dest of I2. */
2622 changed_i3_dest = 1;
2623 goto validate_replacement;
2628 /* If we have no I1 and I2 looks like:
2629 (parallel [(set (reg:CC X) (compare:CC OP (const_int 0)))
2631 make up a dummy I1 that is
2634 (set (reg:CC X) (compare:CC Y (const_int 0)))
2636 (We can ignore any trailing CLOBBERs.)
2638 This undoes a previous combination and allows us to match a branch-and-
2641 if (i1 == 0 && GET_CODE (PATTERN (i2)) == PARALLEL
2642 && XVECLEN (PATTERN (i2), 0) >= 2
2643 && GET_CODE (XVECEXP (PATTERN (i2), 0, 0)) == SET
2644 && (GET_MODE_CLASS (GET_MODE (SET_DEST (XVECEXP (PATTERN (i2), 0, 0))))
2646 && GET_CODE (SET_SRC (XVECEXP (PATTERN (i2), 0, 0))) == COMPARE
2647 && XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 1) == const0_rtx
2648 && GET_CODE (XVECEXP (PATTERN (i2), 0, 1)) == SET
2649 && REG_P (SET_DEST (XVECEXP (PATTERN (i2), 0, 1)))
2650 && rtx_equal_p (XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 0),
2651 SET_SRC (XVECEXP (PATTERN (i2), 0, 1))))
2653 for (i = XVECLEN (PATTERN (i2), 0) - 1; i >= 2; i--)
2654 if (GET_CODE (XVECEXP (PATTERN (i2), 0, i)) != CLOBBER)
2659 /* We make I1 with the same INSN_UID as I2. This gives it
2660 the same DF_INSN_LUID for value tracking. Our fake I1 will
2661 never appear in the insn stream so giving it the same INSN_UID
2662 as I2 will not cause a problem. */
2664 i1 = gen_rtx_INSN (VOIDmode, INSN_UID (i2), NULL_RTX, i2,
2665 BLOCK_FOR_INSN (i2), INSN_LOCATOR (i2),
2666 XVECEXP (PATTERN (i2), 0, 1), -1, NULL_RTX);
2668 SUBST (PATTERN (i2), XVECEXP (PATTERN (i2), 0, 0));
2669 SUBST (XEXP (SET_SRC (PATTERN (i2)), 0),
2670 SET_DEST (PATTERN (i1)));
2675 /* Verify that I2 and I1 are valid for combining. */
2676 if (! can_combine_p (i2, i3, i1, NULL_RTX, &i2dest, &i2src)
2677 || (i1 && ! can_combine_p (i1, i3, NULL_RTX, i2, &i1dest, &i1src)))
2683 /* Record whether I2DEST is used in I2SRC and similarly for the other
2684 cases. Knowing this will help in register status updating below. */
2685 i2dest_in_i2src = reg_overlap_mentioned_p (i2dest, i2src);
2686 i1dest_in_i1src = i1 && reg_overlap_mentioned_p (i1dest, i1src);
2687 i2dest_in_i1src = i1 && reg_overlap_mentioned_p (i2dest, i1src);
2688 i2dest_killed = dead_or_set_p (i2, i2dest);
2689 i1dest_killed = i1 && dead_or_set_p (i1, i1dest);
2691 /* See if I1 directly feeds into I3. It does if I1DEST is not used
2693 i1_feeds_i3 = i1 && ! reg_overlap_mentioned_p (i1dest, i2src);
2695 /* Ensure that I3's pattern can be the destination of combines. */
2696 if (! combinable_i3pat (i3, &PATTERN (i3), i2dest, i1dest,
2697 i1 && i2dest_in_i1src && i1_feeds_i3,
2704 /* See if any of the insns is a MULT operation. Unless one is, we will
2705 reject a combination that is, since it must be slower. Be conservative
2707 if (GET_CODE (i2src) == MULT
2708 || (i1 != 0 && GET_CODE (i1src) == MULT)
2709 || (GET_CODE (PATTERN (i3)) == SET
2710 && GET_CODE (SET_SRC (PATTERN (i3))) == MULT))
2713 /* If I3 has an inc, then give up if I1 or I2 uses the reg that is inc'd.
2714 We used to do this EXCEPT in one case: I3 has a post-inc in an
2715 output operand. However, that exception can give rise to insns like
2717 which is a famous insn on the PDP-11 where the value of r3 used as the
2718 source was model-dependent. Avoid this sort of thing. */
2721 if (!(GET_CODE (PATTERN (i3)) == SET
2722 && REG_P (SET_SRC (PATTERN (i3)))
2723 && MEM_P (SET_DEST (PATTERN (i3)))
2724 && (GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_INC
2725 || GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_DEC)))
2726 /* It's not the exception. */
2729 for (link = REG_NOTES (i3); link; link = XEXP (link, 1))
2730 if (REG_NOTE_KIND (link) == REG_INC
2731 && (reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i2))
2733 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i1)))))
2740 /* See if the SETs in I1 or I2 need to be kept around in the merged
2741 instruction: whenever the value set there is still needed past I3.
2742 For the SETs in I2, this is easy: we see if I2DEST dies or is set in I3.
2744 For the SET in I1, we have two cases: If I1 and I2 independently
2745 feed into I3, the set in I1 needs to be kept around if I1DEST dies
2746 or is set in I3. Otherwise (if I1 feeds I2 which feeds I3), the set
2747 in I1 needs to be kept around unless I1DEST dies or is set in either
2748 I2 or I3. We can distinguish these cases by seeing if I2SRC mentions
2749 I1DEST. If so, we know I1 feeds into I2. */
2751 added_sets_2 = ! dead_or_set_p (i3, i2dest);
2754 = i1 && ! (i1_feeds_i3 ? dead_or_set_p (i3, i1dest)
2755 : (dead_or_set_p (i3, i1dest) || dead_or_set_p (i2, i1dest)));
2757 /* If the set in I2 needs to be kept around, we must make a copy of
2758 PATTERN (I2), so that when we substitute I1SRC for I1DEST in
2759 PATTERN (I2), we are only substituting for the original I1DEST, not into
2760 an already-substituted copy. This also prevents making self-referential
2761 rtx. If I2 is a PARALLEL, we just need the piece that assigns I2SRC to
2766 if (GET_CODE (PATTERN (i2)) == PARALLEL)
2767 i2pat = gen_rtx_SET (VOIDmode, i2dest, copy_rtx (i2src));
2769 i2pat = copy_rtx (PATTERN (i2));
2774 if (GET_CODE (PATTERN (i1)) == PARALLEL)
2775 i1pat = gen_rtx_SET (VOIDmode, i1dest, copy_rtx (i1src));
2777 i1pat = copy_rtx (PATTERN (i1));
2782 /* Substitute in the latest insn for the regs set by the earlier ones. */
2784 maxreg = max_reg_num ();
2789 /* Many machines that don't use CC0 have insns that can both perform an
2790 arithmetic operation and set the condition code. These operations will
2791 be represented as a PARALLEL with the first element of the vector
2792 being a COMPARE of an arithmetic operation with the constant zero.
2793 The second element of the vector will set some pseudo to the result
2794 of the same arithmetic operation. If we simplify the COMPARE, we won't
2795 match such a pattern and so will generate an extra insn. Here we test
2796 for this case, where both the comparison and the operation result are
2797 needed, and make the PARALLEL by just replacing I2DEST in I3SRC with
2798 I2SRC. Later we will make the PARALLEL that contains I2. */
2800 if (i1 == 0 && added_sets_2 && GET_CODE (PATTERN (i3)) == SET
2801 && GET_CODE (SET_SRC (PATTERN (i3))) == COMPARE
2802 && XEXP (SET_SRC (PATTERN (i3)), 1) == const0_rtx
2803 && rtx_equal_p (XEXP (SET_SRC (PATTERN (i3)), 0), i2dest))
2805 #ifdef SELECT_CC_MODE
2807 enum machine_mode compare_mode;
2810 newpat = PATTERN (i3);
2811 SUBST (XEXP (SET_SRC (newpat), 0), i2src);
2815 #ifdef SELECT_CC_MODE
2816 /* See if a COMPARE with the operand we substituted in should be done
2817 with the mode that is currently being used. If not, do the same
2818 processing we do in `subst' for a SET; namely, if the destination
2819 is used only once, try to replace it with a register of the proper
2820 mode and also replace the COMPARE. */
2821 if (undobuf.other_insn == 0
2822 && (cc_use = find_single_use (SET_DEST (newpat), i3,
2823 &undobuf.other_insn))
2824 && ((compare_mode = SELECT_CC_MODE (GET_CODE (*cc_use),
2826 != GET_MODE (SET_DEST (newpat))))
2828 if (can_change_dest_mode(SET_DEST (newpat), added_sets_2,
2831 unsigned int regno = REGNO (SET_DEST (newpat));
2834 if (regno < FIRST_PSEUDO_REGISTER)
2835 new_dest = gen_rtx_REG (compare_mode, regno);
2838 SUBST_MODE (regno_reg_rtx[regno], compare_mode);
2839 new_dest = regno_reg_rtx[regno];
2842 SUBST (SET_DEST (newpat), new_dest);
2843 SUBST (XEXP (*cc_use, 0), new_dest);
2844 SUBST (SET_SRC (newpat),
2845 gen_rtx_COMPARE (compare_mode, i2src, const0_rtx));
2848 undobuf.other_insn = 0;
2855 /* It is possible that the source of I2 or I1 may be performing
2856 an unneeded operation, such as a ZERO_EXTEND of something
2857 that is known to have the high part zero. Handle that case
2858 by letting subst look at the innermost one of them.
2860 Another way to do this would be to have a function that tries
2861 to simplify a single insn instead of merging two or more
2862 insns. We don't do this because of the potential of infinite
2863 loops and because of the potential extra memory required.
2864 However, doing it the way we are is a bit of a kludge and
2865 doesn't catch all cases.
2867 But only do this if -fexpensive-optimizations since it slows
2868 things down and doesn't usually win.
2870 This is not done in the COMPARE case above because the
2871 unmodified I2PAT is used in the PARALLEL and so a pattern
2872 with a modified I2SRC would not match. */
2874 if (flag_expensive_optimizations)
2876 /* Pass pc_rtx so no substitutions are done, just
2880 subst_low_luid = DF_INSN_LUID (i1);
2881 i1src = subst (i1src, pc_rtx, pc_rtx, 0, 0);
2885 subst_low_luid = DF_INSN_LUID (i2);
2886 i2src = subst (i2src, pc_rtx, pc_rtx, 0, 0);
2890 n_occurrences = 0; /* `subst' counts here */
2892 /* If I1 feeds into I2 (not into I3) and I1DEST is in I1SRC, we
2893 need to make a unique copy of I2SRC each time we substitute it
2894 to avoid self-referential rtl. */
2896 subst_low_luid = DF_INSN_LUID (i2);
2897 newpat = subst (PATTERN (i3), i2dest, i2src, 0,
2898 ! i1_feeds_i3 && i1dest_in_i1src);
2901 /* Record whether i2's body now appears within i3's body. */
2902 i2_is_used = n_occurrences;
2905 /* If we already got a failure, don't try to do more. Otherwise,
2906 try to substitute in I1 if we have it. */
2908 if (i1 && GET_CODE (newpat) != CLOBBER)
2910 /* Check that an autoincrement side-effect on I1 has not been lost.
2911 This happens if I1DEST is mentioned in I2 and dies there, and
2912 has disappeared from the new pattern. */
2913 if ((FIND_REG_INC_NOTE (i1, NULL_RTX) != 0
2915 && dead_or_set_p (i2, i1dest)
2916 && !reg_overlap_mentioned_p (i1dest, newpat))
2917 /* Before we can do this substitution, we must redo the test done
2918 above (see detailed comments there) that ensures that I1DEST
2919 isn't mentioned in any SETs in NEWPAT that are field assignments. */
2920 || !combinable_i3pat (NULL_RTX, &newpat, i1dest, NULL_RTX, 0, 0))
2927 subst_low_luid = DF_INSN_LUID (i1);
2928 newpat = subst (newpat, i1dest, i1src, 0, 0);
2932 /* Fail if an autoincrement side-effect has been duplicated. Be careful
2933 to count all the ways that I2SRC and I1SRC can be used. */
2934 if ((FIND_REG_INC_NOTE (i2, NULL_RTX) != 0
2935 && i2_is_used + added_sets_2 > 1)
2936 || (i1 != 0 && FIND_REG_INC_NOTE (i1, NULL_RTX) != 0
2937 && (n_occurrences + added_sets_1 + (added_sets_2 && ! i1_feeds_i3)
2939 /* Fail if we tried to make a new register. */
2940 || max_reg_num () != maxreg
2941 /* Fail if we couldn't do something and have a CLOBBER. */
2942 || GET_CODE (newpat) == CLOBBER
2943 /* Fail if this new pattern is a MULT and we didn't have one before
2944 at the outer level. */
2945 || (GET_CODE (newpat) == SET && GET_CODE (SET_SRC (newpat)) == MULT
2952 /* If the actions of the earlier insns must be kept
2953 in addition to substituting them into the latest one,
2954 we must make a new PARALLEL for the latest insn
2955 to hold additional the SETs. */
2957 if (added_sets_1 || added_sets_2)
2961 if (GET_CODE (newpat) == PARALLEL)
2963 rtvec old = XVEC (newpat, 0);
2964 total_sets = XVECLEN (newpat, 0) + added_sets_1 + added_sets_2;
2965 newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (total_sets));
2966 memcpy (XVEC (newpat, 0)->elem, &old->elem[0],
2967 sizeof (old->elem[0]) * old->num_elem);
2972 total_sets = 1 + added_sets_1 + added_sets_2;
2973 newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (total_sets));
2974 XVECEXP (newpat, 0, 0) = old;
2978 XVECEXP (newpat, 0, --total_sets) = i1pat;
2982 /* If there is no I1, use I2's body as is. We used to also not do
2983 the subst call below if I2 was substituted into I3,
2984 but that could lose a simplification. */
2986 XVECEXP (newpat, 0, --total_sets) = i2pat;
2988 /* See comment where i2pat is assigned. */
2989 XVECEXP (newpat, 0, --total_sets)
2990 = subst (i2pat, i1dest, i1src, 0, 0);
2994 validate_replacement:
2996 /* Note which hard regs this insn has as inputs. */
2997 mark_used_regs_combine (newpat);
2999 /* If recog_for_combine fails, it strips existing clobbers. If we'll
3000 consider splitting this pattern, we might need these clobbers. */
3001 if (i1 && GET_CODE (newpat) == PARALLEL
3002 && GET_CODE (XVECEXP (newpat, 0, XVECLEN (newpat, 0) - 1)) == CLOBBER)
3004 int len = XVECLEN (newpat, 0);
3006 newpat_vec_with_clobbers = rtvec_alloc (len);
3007 for (i = 0; i < len; i++)
3008 RTVEC_ELT (newpat_vec_with_clobbers, i) = XVECEXP (newpat, 0, i);
3011 /* Is the result of combination a valid instruction? */
3012 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
3014 /* If the result isn't valid, see if it is a PARALLEL of two SETs where
3015 the second SET's destination is a register that is unused and isn't
3016 marked as an instruction that might trap in an EH region. In that case,
3017 we just need the first SET. This can occur when simplifying a divmod
3018 insn. We *must* test for this case here because the code below that
3019 splits two independent SETs doesn't handle this case correctly when it
3020 updates the register status.
3022 It's pointless doing this if we originally had two sets, one from
3023 i3, and one from i2. Combining then splitting the parallel results
3024 in the original i2 again plus an invalid insn (which we delete).
3025 The net effect is only to move instructions around, which makes
3026 debug info less accurate.
3028 Also check the case where the first SET's destination is unused.
3029 That would not cause incorrect code, but does cause an unneeded
3032 if (insn_code_number < 0
3033 && !(added_sets_2 && i1 == 0)
3034 && GET_CODE (newpat) == PARALLEL
3035 && XVECLEN (newpat, 0) == 2
3036 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
3037 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
3038 && asm_noperands (newpat) < 0)
3040 rtx set0 = XVECEXP (newpat, 0, 0);
3041 rtx set1 = XVECEXP (newpat, 0, 1);
3043 if (((REG_P (SET_DEST (set1))
3044 && find_reg_note (i3, REG_UNUSED, SET_DEST (set1)))
3045 || (GET_CODE (SET_DEST (set1)) == SUBREG
3046 && find_reg_note (i3, REG_UNUSED, SUBREG_REG (SET_DEST (set1)))))
3047 && insn_nothrow_p (i3)
3048 && !side_effects_p (SET_SRC (set1)))
3051 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
3054 else if (((REG_P (SET_DEST (set0))
3055 && find_reg_note (i3, REG_UNUSED, SET_DEST (set0)))
3056 || (GET_CODE (SET_DEST (set0)) == SUBREG
3057 && find_reg_note (i3, REG_UNUSED,
3058 SUBREG_REG (SET_DEST (set0)))))
3059 && insn_nothrow_p (i3)
3060 && !side_effects_p (SET_SRC (set0)))
3063 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
3065 if (insn_code_number >= 0)
3066 changed_i3_dest = 1;
3070 /* If we were combining three insns and the result is a simple SET
3071 with no ASM_OPERANDS that wasn't recognized, try to split it into two
3072 insns. There are two ways to do this. It can be split using a
3073 machine-specific method (like when you have an addition of a large
3074 constant) or by combine in the function find_split_point. */
3076 if (i1 && insn_code_number < 0 && GET_CODE (newpat) == SET
3077 && asm_noperands (newpat) < 0)
3079 rtx parallel, m_split, *split;
3081 /* See if the MD file can split NEWPAT. If it can't, see if letting it
3082 use I2DEST as a scratch register will help. In the latter case,
3083 convert I2DEST to the mode of the source of NEWPAT if we can. */
3085 m_split = combine_split_insns (newpat, i3);
3087 /* We can only use I2DEST as a scratch reg if it doesn't overlap any
3088 inputs of NEWPAT. */
3090 /* ??? If I2DEST is not safe, and I1DEST exists, then it would be
3091 possible to try that as a scratch reg. This would require adding
3092 more code to make it work though. */
3094 if (m_split == 0 && ! reg_overlap_mentioned_p (i2dest, newpat))
3096 enum machine_mode new_mode = GET_MODE (SET_DEST (newpat));
3098 /* First try to split using the original register as a
3099 scratch register. */
3100 parallel = gen_rtx_PARALLEL (VOIDmode,
3101 gen_rtvec (2, newpat,
3102 gen_rtx_CLOBBER (VOIDmode,
3104 m_split = combine_split_insns (parallel, i3);
3106 /* If that didn't work, try changing the mode of I2DEST if
3109 && new_mode != GET_MODE (i2dest)
3110 && new_mode != VOIDmode
3111 && can_change_dest_mode (i2dest, added_sets_2, new_mode))
3113 enum machine_mode old_mode = GET_MODE (i2dest);
3116 if (REGNO (i2dest) < FIRST_PSEUDO_REGISTER)
3117 ni2dest = gen_rtx_REG (new_mode, REGNO (i2dest));
3120 SUBST_MODE (regno_reg_rtx[REGNO (i2dest)], new_mode);
3121 ni2dest = regno_reg_rtx[REGNO (i2dest)];
3124 parallel = (gen_rtx_PARALLEL
3126 gen_rtvec (2, newpat,
3127 gen_rtx_CLOBBER (VOIDmode,
3129 m_split = combine_split_insns (parallel, i3);
3132 && REGNO (i2dest) >= FIRST_PSEUDO_REGISTER)
3136 adjust_reg_mode (regno_reg_rtx[REGNO (i2dest)], old_mode);
3137 buf = undobuf.undos;
3138 undobuf.undos = buf->next;
3139 buf->next = undobuf.frees;
3140 undobuf.frees = buf;
3144 i2scratch = m_split != 0;
3147 /* If recog_for_combine has discarded clobbers, try to use them
3148 again for the split. */
3149 if (m_split == 0 && newpat_vec_with_clobbers)
3151 parallel = gen_rtx_PARALLEL (VOIDmode, newpat_vec_with_clobbers);
3152 m_split = combine_split_insns (parallel, i3);
3155 if (m_split && NEXT_INSN (m_split) == NULL_RTX)
3157 m_split = PATTERN (m_split);
3158 insn_code_number = recog_for_combine (&m_split, i3, &new_i3_notes);
3159 if (insn_code_number >= 0)
3162 else if (m_split && NEXT_INSN (NEXT_INSN (m_split)) == NULL_RTX
3163 && (next_real_insn (i2) == i3
3164 || ! use_crosses_set_p (PATTERN (m_split), DF_INSN_LUID (i2))))
3167 rtx newi3pat = PATTERN (NEXT_INSN (m_split));
3168 newi2pat = PATTERN (m_split);
3170 i3set = single_set (NEXT_INSN (m_split));
3171 i2set = single_set (m_split);
3173 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
3175 /* If I2 or I3 has multiple SETs, we won't know how to track
3176 register status, so don't use these insns. If I2's destination
3177 is used between I2 and I3, we also can't use these insns. */
3179 if (i2_code_number >= 0 && i2set && i3set
3180 && (next_real_insn (i2) == i3
3181 || ! reg_used_between_p (SET_DEST (i2set), i2, i3)))
3182 insn_code_number = recog_for_combine (&newi3pat, i3,
3184 if (insn_code_number >= 0)
3187 /* It is possible that both insns now set the destination of I3.
3188 If so, we must show an extra use of it. */
3190 if (insn_code_number >= 0)
3192 rtx new_i3_dest = SET_DEST (i3set);
3193 rtx new_i2_dest = SET_DEST (i2set);
3195 while (GET_CODE (new_i3_dest) == ZERO_EXTRACT
3196 || GET_CODE (new_i3_dest) == STRICT_LOW_PART
3197 || GET_CODE (new_i3_dest) == SUBREG)
3198 new_i3_dest = XEXP (new_i3_dest, 0);
3200 while (GET_CODE (new_i2_dest) == ZERO_EXTRACT
3201 || GET_CODE (new_i2_dest) == STRICT_LOW_PART
3202 || GET_CODE (new_i2_dest) == SUBREG)
3203 new_i2_dest = XEXP (new_i2_dest, 0);
3205 if (REG_P (new_i3_dest)
3206 && REG_P (new_i2_dest)
3207 && REGNO (new_i3_dest) == REGNO (new_i2_dest))
3208 INC_REG_N_SETS (REGNO (new_i2_dest), 1);
3212 /* If we can split it and use I2DEST, go ahead and see if that
3213 helps things be recognized. Verify that none of the registers
3214 are set between I2 and I3. */
3215 if (insn_code_number < 0
3216 && (split = find_split_point (&newpat, i3, false)) != 0
3220 /* We need I2DEST in the proper mode. If it is a hard register
3221 or the only use of a pseudo, we can change its mode.
3222 Make sure we don't change a hard register to have a mode that
3223 isn't valid for it, or change the number of registers. */
3224 && (GET_MODE (*split) == GET_MODE (i2dest)
3225 || GET_MODE (*split) == VOIDmode
3226 || can_change_dest_mode (i2dest, added_sets_2,
3228 && (next_real_insn (i2) == i3
3229 || ! use_crosses_set_p (*split, DF_INSN_LUID (i2)))
3230 /* We can't overwrite I2DEST if its value is still used by
3232 && ! reg_referenced_p (i2dest, newpat))
3234 rtx newdest = i2dest;
3235 enum rtx_code split_code = GET_CODE (*split);
3236 enum machine_mode split_mode = GET_MODE (*split);
3237 bool subst_done = false;
3238 newi2pat = NULL_RTX;
3242 /* *SPLIT may be part of I2SRC, so make sure we have the
3243 original expression around for later debug processing.
3244 We should not need I2SRC any more in other cases. */
3245 if (MAY_HAVE_DEBUG_INSNS)
3246 i2src = copy_rtx (i2src);
3250 /* Get NEWDEST as a register in the proper mode. We have already
3251 validated that we can do this. */
3252 if (GET_MODE (i2dest) != split_mode && split_mode != VOIDmode)
3254 if (REGNO (i2dest) < FIRST_PSEUDO_REGISTER)
3255 newdest = gen_rtx_REG (split_mode, REGNO (i2dest));
3258 SUBST_MODE (regno_reg_rtx[REGNO (i2dest)], split_mode);
3259 newdest = regno_reg_rtx[REGNO (i2dest)];
3263 /* If *SPLIT is a (mult FOO (const_int pow2)), convert it to
3264 an ASHIFT. This can occur if it was inside a PLUS and hence
3265 appeared to be a memory address. This is a kludge. */
3266 if (split_code == MULT
3267 && CONST_INT_P (XEXP (*split, 1))
3268 && INTVAL (XEXP (*split, 1)) > 0
3269 && (i = exact_log2 (INTVAL (XEXP (*split, 1)))) >= 0)
3271 SUBST (*split, gen_rtx_ASHIFT (split_mode,
3272 XEXP (*split, 0), GEN_INT (i)));
3273 /* Update split_code because we may not have a multiply
3275 split_code = GET_CODE (*split);
3278 #ifdef INSN_SCHEDULING
3279 /* If *SPLIT is a paradoxical SUBREG, when we split it, it should
3280 be written as a ZERO_EXTEND. */
3281 if (split_code == SUBREG && MEM_P (SUBREG_REG (*split)))
3283 #ifdef LOAD_EXTEND_OP
3284 /* Or as a SIGN_EXTEND if LOAD_EXTEND_OP says that that's
3285 what it really is. */
3286 if (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (*split)))
3288 SUBST (*split, gen_rtx_SIGN_EXTEND (split_mode,
3289 SUBREG_REG (*split)));
3292 SUBST (*split, gen_rtx_ZERO_EXTEND (split_mode,
3293 SUBREG_REG (*split)));
3297 /* Attempt to split binary operators using arithmetic identities. */
3298 if (BINARY_P (SET_SRC (newpat))
3299 && split_mode == GET_MODE (SET_SRC (newpat))
3300 && ! side_effects_p (SET_SRC (newpat)))
3302 rtx setsrc = SET_SRC (newpat);
3303 enum machine_mode mode = GET_MODE (setsrc);
3304 enum rtx_code code = GET_CODE (setsrc);
3305 rtx src_op0 = XEXP (setsrc, 0);
3306 rtx src_op1 = XEXP (setsrc, 1);
3308 /* Split "X = Y op Y" as "Z = Y; X = Z op Z". */
3309 if (rtx_equal_p (src_op0, src_op1))
3311 newi2pat = gen_rtx_SET (VOIDmode, newdest, src_op0);
3312 SUBST (XEXP (setsrc, 0), newdest);
3313 SUBST (XEXP (setsrc, 1), newdest);
3316 /* Split "((P op Q) op R) op S" where op is PLUS or MULT. */
3317 else if ((code == PLUS || code == MULT)
3318 && GET_CODE (src_op0) == code
3319 && GET_CODE (XEXP (src_op0, 0)) == code
3320 && (INTEGRAL_MODE_P (mode)
3321 || (FLOAT_MODE_P (mode)
3322 && flag_unsafe_math_optimizations)))
3324 rtx p = XEXP (XEXP (src_op0, 0), 0);
3325 rtx q = XEXP (XEXP (src_op0, 0), 1);
3326 rtx r = XEXP (src_op0, 1);
3329 /* Split both "((X op Y) op X) op Y" and
3330 "((X op Y) op Y) op X" as "T op T" where T is
3332 if ((rtx_equal_p (p,r) && rtx_equal_p (q,s))
3333 || (rtx_equal_p (p,s) && rtx_equal_p (q,r)))
3335 newi2pat = gen_rtx_SET (VOIDmode, newdest,
3337 SUBST (XEXP (setsrc, 0), newdest);
3338 SUBST (XEXP (setsrc, 1), newdest);
3341 /* Split "((X op X) op Y) op Y)" as "T op T" where
3343 else if (rtx_equal_p (p,q) && rtx_equal_p (r,s))
3345 rtx tmp = simplify_gen_binary (code, mode, p, r);
3346 newi2pat = gen_rtx_SET (VOIDmode, newdest, tmp);
3347 SUBST (XEXP (setsrc, 0), newdest);
3348 SUBST (XEXP (setsrc, 1), newdest);
3356 newi2pat = gen_rtx_SET (VOIDmode, newdest, *split);
3357 SUBST (*split, newdest);
3360 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
3362 /* recog_for_combine might have added CLOBBERs to newi2pat.
3363 Make sure NEWPAT does not depend on the clobbered regs. */
3364 if (GET_CODE (newi2pat) == PARALLEL)
3365 for (i = XVECLEN (newi2pat, 0) - 1; i >= 0; i--)
3366 if (GET_CODE (XVECEXP (newi2pat, 0, i)) == CLOBBER)
3368 rtx reg = XEXP (XVECEXP (newi2pat, 0, i), 0);
3369 if (reg_overlap_mentioned_p (reg, newpat))
3376 /* If the split point was a MULT and we didn't have one before,
3377 don't use one now. */
3378 if (i2_code_number >= 0 && ! (split_code == MULT && ! have_mult))
3379 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
3383 /* Check for a case where we loaded from memory in a narrow mode and
3384 then sign extended it, but we need both registers. In that case,
3385 we have a PARALLEL with both loads from the same memory location.
3386 We can split this into a load from memory followed by a register-register
3387 copy. This saves at least one insn, more if register allocation can
3390 We cannot do this if the destination of the first assignment is a
3391 condition code register or cc0. We eliminate this case by making sure
3392 the SET_DEST and SET_SRC have the same mode.
3394 We cannot do this if the destination of the second assignment is
3395 a register that we have already assumed is zero-extended. Similarly
3396 for a SUBREG of such a register. */
3398 else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0
3399 && GET_CODE (newpat) == PARALLEL
3400 && XVECLEN (newpat, 0) == 2
3401 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
3402 && GET_CODE (SET_SRC (XVECEXP (newpat, 0, 0))) == SIGN_EXTEND
3403 && (GET_MODE (SET_DEST (XVECEXP (newpat, 0, 0)))
3404 == GET_MODE (SET_SRC (XVECEXP (newpat, 0, 0))))
3405 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
3406 && rtx_equal_p (SET_SRC (XVECEXP (newpat, 0, 1)),
3407 XEXP (SET_SRC (XVECEXP (newpat, 0, 0)), 0))
3408 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)),
3410 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
3411 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
3412 && ! (temp = SET_DEST (XVECEXP (newpat, 0, 1)),
3414 && VEC_index (reg_stat_type, reg_stat,
3415 REGNO (temp))->nonzero_bits != 0
3416 && GET_MODE_BITSIZE (GET_MODE (temp)) < BITS_PER_WORD
3417 && GET_MODE_BITSIZE (GET_MODE (temp)) < HOST_BITS_PER_INT
3418 && (VEC_index (reg_stat_type, reg_stat,
3419 REGNO (temp))->nonzero_bits
3420 != GET_MODE_MASK (word_mode))))
3421 && ! (GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) == SUBREG
3422 && (temp = SUBREG_REG (SET_DEST (XVECEXP (newpat, 0, 1))),
3424 && VEC_index (reg_stat_type, reg_stat,
3425 REGNO (temp))->nonzero_bits != 0
3426 && GET_MODE_BITSIZE (GET_MODE (temp)) < BITS_PER_WORD
3427 && GET_MODE_BITSIZE (GET_MODE (temp)) < HOST_BITS_PER_INT
3428 && (VEC_index (reg_stat_type, reg_stat,
3429 REGNO (temp))->nonzero_bits
3430 != GET_MODE_MASK (word_mode)))))
3431 && ! reg_overlap_mentioned_p (SET_DEST (XVECEXP (newpat, 0, 1)),
3432 SET_SRC (XVECEXP (newpat, 0, 1)))
3433 && ! find_reg_note (i3, REG_UNUSED,
3434 SET_DEST (XVECEXP (newpat, 0, 0))))
3438 newi2pat = XVECEXP (newpat, 0, 0);
3439 ni2dest = SET_DEST (XVECEXP (newpat, 0, 0));
3440 newpat = XVECEXP (newpat, 0, 1);
3441 SUBST (SET_SRC (newpat),
3442 gen_lowpart (GET_MODE (SET_SRC (newpat)), ni2dest));
3443 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
3445 if (i2_code_number >= 0)
3446 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
3448 if (insn_code_number >= 0)
3452 /* Similarly, check for a case where we have a PARALLEL of two independent
3453 SETs but we started with three insns. In this case, we can do the sets
3454 as two separate insns. This case occurs when some SET allows two
3455 other insns to combine, but the destination of that SET is still live. */
3457 else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0
3458 && GET_CODE (newpat) == PARALLEL
3459 && XVECLEN (newpat, 0) == 2
3460 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
3461 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != ZERO_EXTRACT
3462 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != STRICT_LOW_PART
3463 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
3464 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
3465 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
3466 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)),
3468 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 1)),
3469 XVECEXP (newpat, 0, 0))
3470 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 0)),
3471 XVECEXP (newpat, 0, 1))
3472 && ! (contains_muldiv (SET_SRC (XVECEXP (newpat, 0, 0)))
3473 && contains_muldiv (SET_SRC (XVECEXP (newpat, 0, 1))))
3475 /* We cannot split the parallel into two sets if both sets
3477 && ! (reg_referenced_p (cc0_rtx, XVECEXP (newpat, 0, 0))
3478 && reg_referenced_p (cc0_rtx, XVECEXP (newpat, 0, 1)))
3482 /* Normally, it doesn't matter which of the two is done first,
3483 but it does if one references cc0. In that case, it has to
3486 if (reg_referenced_p (cc0_rtx, XVECEXP (newpat, 0, 0)))
3488 newi2pat = XVECEXP (newpat, 0, 0);
3489 newpat = XVECEXP (newpat, 0, 1);
3494 newi2pat = XVECEXP (newpat, 0, 1);
3495 newpat = XVECEXP (newpat, 0, 0);
3498 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
3500 if (i2_code_number >= 0)
3501 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
3504 /* If it still isn't recognized, fail and change things back the way they
3506 if ((insn_code_number < 0
3507 /* Is the result a reasonable ASM_OPERANDS? */
3508 && (! check_asm_operands (newpat) || added_sets_1 || added_sets_2)))
3514 /* If we had to change another insn, make sure it is valid also. */
3515 if (undobuf.other_insn)
3517 CLEAR_HARD_REG_SET (newpat_used_regs);
3519 other_pat = PATTERN (undobuf.other_insn);
3520 other_code_number = recog_for_combine (&other_pat, undobuf.other_insn,
3523 if (other_code_number < 0 && ! check_asm_operands (other_pat))
3531 /* If I2 is the CC0 setter and I3 is the CC0 user then check whether
3532 they are adjacent to each other or not. */
3534 rtx p = prev_nonnote_insn (i3);
3535 if (p && p != i2 && NONJUMP_INSN_P (p) && newi2pat
3536 && sets_cc0_p (newi2pat))
3544 /* Only allow this combination if insn_rtx_costs reports that the
3545 replacement instructions are cheaper than the originals. */
3546 if (!combine_validate_cost (i1, i2, i3, newpat, newi2pat, other_pat))
3552 if (MAY_HAVE_DEBUG_INSNS)
3556 for (undo = undobuf.undos; undo; undo = undo->next)
3557 if (undo->kind == UNDO_MODE)
3559 rtx reg = *undo->where.r;
3560 enum machine_mode new_mode = GET_MODE (reg);
3561 enum machine_mode old_mode = undo->old_contents.m;
3563 /* Temporarily revert mode back. */
3564 adjust_reg_mode (reg, old_mode);
3566 if (reg == i2dest && i2scratch)
3568 /* If we used i2dest as a scratch register with a
3569 different mode, substitute it for the original
3570 i2src while its original mode is temporarily
3571 restored, and then clear i2scratch so that we don't
3572 do it again later. */
3573 propagate_for_debug (i2, i3, reg, i2src, false);
3575 /* Put back the new mode. */
3576 adjust_reg_mode (reg, new_mode);
3580 rtx tempreg = gen_raw_REG (old_mode, REGNO (reg));
3591 last = undobuf.other_insn;
3595 /* We're dealing with a reg that changed mode but not
3596 meaning, so we want to turn it into a subreg for
3597 the new mode. However, because of REG sharing and
3598 because its mode had already changed, we have to do
3599 it in two steps. First, replace any debug uses of
3600 reg, with its original mode temporarily restored,
3601 with this copy we have created; then, replace the
3602 copy with the SUBREG of the original shared reg,
3603 once again changed to the new mode. */
3604 propagate_for_debug (first, last, reg, tempreg, false);
3605 adjust_reg_mode (reg, new_mode);
3606 propagate_for_debug (first, last, tempreg,
3607 lowpart_subreg (old_mode, reg, new_mode),
3613 /* If we will be able to accept this, we have made a
3614 change to the destination of I3. This requires us to
3615 do a few adjustments. */
3617 if (changed_i3_dest)
3619 PATTERN (i3) = newpat;
3620 adjust_for_new_dest (i3);
3623 /* We now know that we can do this combination. Merge the insns and
3624 update the status of registers and LOG_LINKS. */
3626 if (undobuf.other_insn)
3630 PATTERN (undobuf.other_insn) = other_pat;
3632 /* If any of the notes in OTHER_INSN were REG_UNUSED, ensure that they
3633 are still valid. Then add any non-duplicate notes added by
3634 recog_for_combine. */
3635 for (note = REG_NOTES (undobuf.other_insn); note; note = next)
3637 next = XEXP (note, 1);
3639 if (REG_NOTE_KIND (note) == REG_UNUSED
3640 && ! reg_set_p (XEXP (note, 0), PATTERN (undobuf.other_insn)))
3641 remove_note (undobuf.other_insn, note);
3644 distribute_notes (new_other_notes, undobuf.other_insn,
3645 undobuf.other_insn, NULL_RTX, NULL_RTX, NULL_RTX);
3654 /* I3 now uses what used to be its destination and which is now
3655 I2's destination. This requires us to do a few adjustments. */
3656 PATTERN (i3) = newpat;
3657 adjust_for_new_dest (i3);
3659 /* We need a LOG_LINK from I3 to I2. But we used to have one,
3662 However, some later insn might be using I2's dest and have
3663 a LOG_LINK pointing at I3. We must remove this link.
3664 The simplest way to remove the link is to point it at I1,
3665 which we know will be a NOTE. */
3667 /* newi2pat is usually a SET here; however, recog_for_combine might
3668 have added some clobbers. */
3669 if (GET_CODE (newi2pat) == PARALLEL)
3670 ni2dest = SET_DEST (XVECEXP (newi2pat, 0, 0));
3672 ni2dest = SET_DEST (newi2pat);
3674 for (insn = NEXT_INSN (i3);
3675 insn && (this_basic_block->next_bb == EXIT_BLOCK_PTR
3676 || insn != BB_HEAD (this_basic_block->next_bb));
3677 insn = NEXT_INSN (insn))
3679 if (INSN_P (insn) && reg_referenced_p (ni2dest, PATTERN (insn)))
3681 for (link = LOG_LINKS (insn); link;
3682 link = XEXP (link, 1))
3683 if (XEXP (link, 0) == i3)
3684 XEXP (link, 0) = i1;
3692 rtx i3notes, i2notes, i1notes = 0;
3693 rtx i3links, i2links, i1links = 0;
3696 /* Compute which registers we expect to eliminate. newi2pat may be setting
3697 either i3dest or i2dest, so we must check it. Also, i1dest may be the
3698 same as i3dest, in which case newi2pat may be setting i1dest. */
3699 rtx elim_i2 = ((newi2pat && reg_set_p (i2dest, newi2pat))
3700 || i2dest_in_i2src || i2dest_in_i1src
3703 rtx elim_i1 = (i1 == 0 || i1dest_in_i1src
3704 || (newi2pat && reg_set_p (i1dest, newi2pat))
3708 /* Get the old REG_NOTES and LOG_LINKS from all our insns and
3710 i3notes = REG_NOTES (i3), i3links = LOG_LINKS (i3);
3711 i2notes = REG_NOTES (i2), i2links = LOG_LINKS (i2);
3713 i1notes = REG_NOTES (i1), i1links = LOG_LINKS (i1);
3715 /* Ensure that we do not have something that should not be shared but
3716 occurs multiple times in the new insns. Check this by first
3717 resetting all the `used' flags and then copying anything is shared. */
3719 reset_used_flags (i3notes);
3720 reset_used_flags (i2notes);
3721 reset_used_flags (i1notes);
3722 reset_used_flags (newpat);
3723 reset_used_flags (newi2pat);
3724 if (undobuf.other_insn)
3725 reset_used_flags (PATTERN (undobuf.other_insn));
3727 i3notes = copy_rtx_if_shared (i3notes);
3728 i2notes = copy_rtx_if_shared (i2notes);
3729 i1notes = copy_rtx_if_shared (i1notes);
3730 newpat = copy_rtx_if_shared (newpat);
3731 newi2pat = copy_rtx_if_shared (newi2pat);
3732 if (undobuf.other_insn)
3733 reset_used_flags (PATTERN (undobuf.other_insn));
3735 INSN_CODE (i3) = insn_code_number;
3736 PATTERN (i3) = newpat;
3738 if (CALL_P (i3) && CALL_INSN_FUNCTION_USAGE (i3))
3740 rtx call_usage = CALL_INSN_FUNCTION_USAGE (i3);
3742 reset_used_flags (call_usage);
3743 call_usage = copy_rtx (call_usage);
3747 /* I2SRC must still be meaningful at this point. Some splitting
3748 operations can invalidate I2SRC, but those operations do not
3751 replace_rtx (call_usage, i2dest, i2src);
3755 replace_rtx (call_usage, i1dest, i1src);
3757 CALL_INSN_FUNCTION_USAGE (i3) = call_usage;
3760 if (undobuf.other_insn)
3761 INSN_CODE (undobuf.other_insn) = other_code_number;
3763 /* We had one special case above where I2 had more than one set and
3764 we replaced a destination of one of those sets with the destination
3765 of I3. In that case, we have to update LOG_LINKS of insns later
3766 in this basic block. Note that this (expensive) case is rare.
3768 Also, in this case, we must pretend that all REG_NOTEs for I2
3769 actually came from I3, so that REG_UNUSED notes from I2 will be
3770 properly handled. */
3772 if (i3_subst_into_i2)
3774 for (i = 0; i < XVECLEN (PATTERN (i2), 0); i++)
3775 if ((GET_CODE (XVECEXP (PATTERN (i2), 0, i)) == SET
3776 || GET_CODE (XVECEXP (PATTERN (i2), 0, i)) == CLOBBER)
3777 && REG_P (SET_DEST (XVECEXP (PATTERN (i2), 0, i)))
3778 && SET_DEST (XVECEXP (PATTERN (i2), 0, i)) != i2dest
3779 && ! find_reg_note (i2, REG_UNUSED,
3780 SET_DEST (XVECEXP (PATTERN (i2), 0, i))))
3781 for (temp = NEXT_INSN (i2);
3782 temp && (this_basic_block->next_bb == EXIT_BLOCK_PTR
3783 || BB_HEAD (this_basic_block) != temp);
3784 temp = NEXT_INSN (temp))
3785 if (temp != i3 && INSN_P (temp))
3786 for (link = LOG_LINKS (temp); link; link = XEXP (link, 1))
3787 if (XEXP (link, 0) == i2)
3788 XEXP (link, 0) = i3;
3793 while (XEXP (link, 1))
3794 link = XEXP (link, 1);
3795 XEXP (link, 1) = i2notes;
3809 if (MAY_HAVE_DEBUG_INSNS && i2scratch)
3810 propagate_for_debug (i2, i3, i2dest, i2src, false);
3811 INSN_CODE (i2) = i2_code_number;
3812 PATTERN (i2) = newi2pat;
3816 if (MAY_HAVE_DEBUG_INSNS && i2src)
3817 propagate_for_debug (i2, i3, i2dest, i2src, i3_subst_into_i2);
3818 SET_INSN_DELETED (i2);
3825 if (MAY_HAVE_DEBUG_INSNS)
3826 propagate_for_debug (i1, i3, i1dest, i1src, false);
3827 SET_INSN_DELETED (i1);
3830 /* Get death notes for everything that is now used in either I3 or
3831 I2 and used to die in a previous insn. If we built two new
3832 patterns, move from I1 to I2 then I2 to I3 so that we get the
3833 proper movement on registers that I2 modifies. */
3837 move_deaths (newi2pat, NULL_RTX, DF_INSN_LUID (i1), i2, &midnotes);
3838 move_deaths (newpat, newi2pat, DF_INSN_LUID (i1), i3, &midnotes);
3841 move_deaths (newpat, NULL_RTX, i1 ? DF_INSN_LUID (i1) : DF_INSN_LUID (i2),
3844 /* Distribute all the LOG_LINKS and REG_NOTES from I1, I2, and I3. */
3846 distribute_notes (i3notes, i3, i3, newi2pat ? i2 : NULL_RTX,
3849 distribute_notes (i2notes, i2, i3, newi2pat ? i2 : NULL_RTX,
3852 distribute_notes (i1notes, i1, i3, newi2pat ? i2 : NULL_RTX,
3855 distribute_notes (midnotes, NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
3858 /* Distribute any notes added to I2 or I3 by recog_for_combine. We
3859 know these are REG_UNUSED and want them to go to the desired insn,
3860 so we always pass it as i3. */
3862 if (newi2pat && new_i2_notes)
3863 distribute_notes (new_i2_notes, i2, i2, NULL_RTX, NULL_RTX, NULL_RTX);
3866 distribute_notes (new_i3_notes, i3, i3, NULL_RTX, NULL_RTX, NULL_RTX);
3868 /* If I3DEST was used in I3SRC, it really died in I3. We may need to
3869 put a REG_DEAD note for it somewhere. If NEWI2PAT exists and sets
3870 I3DEST, the death must be somewhere before I2, not I3. If we passed I3
3871 in that case, it might delete I2. Similarly for I2 and I1.
3872 Show an additional death due to the REG_DEAD note we make here. If
3873 we discard it in distribute_notes, we will decrement it again. */
3877 if (newi2pat && reg_set_p (i3dest_killed, newi2pat))
3878 distribute_notes (alloc_reg_note (REG_DEAD, i3dest_killed,
3880 NULL_RTX, i2, NULL_RTX, elim_i2, elim_i1);
3882 distribute_notes (alloc_reg_note (REG_DEAD, i3dest_killed,
3884 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
3888 if (i2dest_in_i2src)
3890 if (newi2pat && reg_set_p (i2dest, newi2pat))
3891 distribute_notes (alloc_reg_note (REG_DEAD, i2dest, NULL_RTX),
3892 NULL_RTX, i2, NULL_RTX, NULL_RTX, NULL_RTX);
3894 distribute_notes (alloc_reg_note (REG_DEAD, i2dest, NULL_RTX),
3895 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
3896 NULL_RTX, NULL_RTX);
3899 if (i1dest_in_i1src)
3901 if (newi2pat && reg_set_p (i1dest, newi2pat))
3902 distribute_notes (alloc_reg_note (REG_DEAD, i1dest, NULL_RTX),
3903 NULL_RTX, i2, NULL_RTX, NULL_RTX, NULL_RTX);
3905 distribute_notes (alloc_reg_note (REG_DEAD, i1dest, NULL_RTX),
3906 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
3907 NULL_RTX, NULL_RTX);
3910 distribute_links (i3links);
3911 distribute_links (i2links);
3912 distribute_links (i1links);
3917 rtx i2_insn = 0, i2_val = 0, set;
3919 /* The insn that used to set this register doesn't exist, and
3920 this life of the register may not exist either. See if one of
3921 I3's links points to an insn that sets I2DEST. If it does,
3922 that is now the last known value for I2DEST. If we don't update
3923 this and I2 set the register to a value that depended on its old
3924 contents, we will get confused. If this insn is used, thing
3925 will be set correctly in combine_instructions. */
3927 for (link = LOG_LINKS (i3); link; link = XEXP (link, 1))
3928 if ((set = single_set (XEXP (link, 0))) != 0
3929 && rtx_equal_p (i2dest, SET_DEST (set)))
3930 i2_insn = XEXP (link, 0), i2_val = SET_SRC (set);
3932 record_value_for_reg (i2dest, i2_insn, i2_val);
3934 /* If the reg formerly set in I2 died only once and that was in I3,
3935 zero its use count so it won't make `reload' do any work. */
3937 && (newi2pat == 0 || ! reg_mentioned_p (i2dest, newi2pat))
3938 && ! i2dest_in_i2src)
3940 regno = REGNO (i2dest);
3941 INC_REG_N_SETS (regno, -1);
3945 if (i1 && REG_P (i1dest))
3948 rtx i1_insn = 0, i1_val = 0, set;
3950 for (link = LOG_LINKS (i3); link; link = XEXP (link, 1))
3951 if ((set = single_set (XEXP (link, 0))) != 0
3952 && rtx_equal_p (i1dest, SET_DEST (set)))
3953 i1_insn = XEXP (link, 0), i1_val = SET_SRC (set);
3955 record_value_for_reg (i1dest, i1_insn, i1_val);
3957 regno = REGNO (i1dest);
3958 if (! added_sets_1 && ! i1dest_in_i1src)
3959 INC_REG_N_SETS (regno, -1);
3962 /* Update reg_stat[].nonzero_bits et al for any changes that may have
3963 been made to this insn. The order of
3964 set_nonzero_bits_and_sign_copies() is important. Because newi2pat
3965 can affect nonzero_bits of newpat */
3967 note_stores (newi2pat, set_nonzero_bits_and_sign_copies, NULL);
3968 note_stores (newpat, set_nonzero_bits_and_sign_copies, NULL);
3971 if (undobuf.other_insn != NULL_RTX)
3975 fprintf (dump_file, "modifying other_insn ");
3976 dump_insn_slim (dump_file, undobuf.other_insn);
3978 df_insn_rescan (undobuf.other_insn);
3981 if (i1 && !(NOTE_P(i1) && (NOTE_KIND (i1) == NOTE_INSN_DELETED)))
3985 fprintf (dump_file, "modifying insn i1 ");
3986 dump_insn_slim (dump_file, i1);
3988 df_insn_rescan (i1);
3991 if (i2 && !(NOTE_P(i2) && (NOTE_KIND (i2) == NOTE_INSN_DELETED)))
3995 fprintf (dump_file, "modifying insn i2 ");
3996 dump_insn_slim (dump_file, i2);
3998 df_insn_rescan (i2);
4001 if (i3 && !(NOTE_P(i3) && (NOTE_KIND (i3) == NOTE_INSN_DELETED)))
4005 fprintf (dump_file, "modifying insn i3 ");
4006 dump_insn_slim (dump_file, i3);
4008 df_insn_rescan (i3);
4011 /* Set new_direct_jump_p if a new return or simple jump instruction
4012 has been created. Adjust the CFG accordingly. */
4014 if (returnjump_p (i3) || any_uncondjump_p (i3))
4016 *new_direct_jump_p = 1;
4017 mark_jump_label (PATTERN (i3), i3, 0);
4018 update_cfg_for_uncondjump (i3);
4021 if (undobuf.other_insn != NULL_RTX
4022 && (returnjump_p (undobuf.other_insn)
4023 || any_uncondjump_p (undobuf.other_insn)))
4025 *new_direct_jump_p = 1;
4026 update_cfg_for_uncondjump (undobuf.other_insn);
4029 /* A noop might also need cleaning up of CFG, if it comes from the
4030 simplification of a jump. */
4031 if (GET_CODE (newpat) == SET
4032 && SET_SRC (newpat) == pc_rtx
4033 && SET_DEST (newpat) == pc_rtx)
4035 *new_direct_jump_p = 1;
4036 update_cfg_for_uncondjump (i3);
4039 combine_successes++;
4042 if (added_links_insn
4043 && (newi2pat == 0 || DF_INSN_LUID (added_links_insn) < DF_INSN_LUID (i2))
4044 && DF_INSN_LUID (added_links_insn) < DF_INSN_LUID (i3))
4045 return added_links_insn;
4047 return newi2pat ? i2 : i3;
4050 /* Undo all the modifications recorded in undobuf. */
4055 struct undo *undo, *next;
4057 for (undo = undobuf.undos; undo; undo = next)
4063 *undo->where.r = undo->old_contents.r;
4066 *undo->where.i = undo->old_contents.i;
4069 adjust_reg_mode (*undo->where.r, undo->old_contents.m);
4075 undo->next = undobuf.frees;
4076 undobuf.frees = undo;
4082 /* We've committed to accepting the changes we made. Move all
4083 of the undos to the free list. */
4088 struct undo *undo, *next;
4090 for (undo = undobuf.undos; undo; undo = next)
4093 undo->next = undobuf.frees;
4094 undobuf.frees = undo;
4099 /* Find the innermost point within the rtx at LOC, possibly LOC itself,
4100 where we have an arithmetic expression and return that point. LOC will
4103 try_combine will call this function to see if an insn can be split into
4107 find_split_point (rtx *loc, rtx insn, bool set_src)
4110 enum rtx_code code = GET_CODE (x);
4112 unsigned HOST_WIDE_INT len = 0;
4113 HOST_WIDE_INT pos = 0;
4115 rtx inner = NULL_RTX;
4117 /* First special-case some codes. */
4121 #ifdef INSN_SCHEDULING
4122 /* If we are making a paradoxical SUBREG invalid, it becomes a split
4124 if (MEM_P (SUBREG_REG (x)))
4127 return find_split_point (&SUBREG_REG (x), insn, false);
4131 /* If we have (mem (const ..)) or (mem (symbol_ref ...)), split it
4132 using LO_SUM and HIGH. */
4133 if (GET_CODE (XEXP (x, 0)) == CONST
4134 || GET_CODE (XEXP (x, 0)) == SYMBOL_REF)
4136 enum machine_mode address_mode
4137 = targetm.addr_space.address_mode (MEM_ADDR_SPACE (x));
4140 gen_rtx_LO_SUM (address_mode,
4141 gen_rtx_HIGH (address_mode, XEXP (x, 0)),
4143 return &XEXP (XEXP (x, 0), 0);
4147 /* If we have a PLUS whose second operand is a constant and the
4148 address is not valid, perhaps will can split it up using
4149 the machine-specific way to split large constants. We use
4150 the first pseudo-reg (one of the virtual regs) as a placeholder;
4151 it will not remain in the result. */
4152 if (GET_CODE (XEXP (x, 0)) == PLUS
4153 && CONST_INT_P (XEXP (XEXP (x, 0), 1))
4154 && ! memory_address_addr_space_p (GET_MODE (x), XEXP (x, 0),
4155 MEM_ADDR_SPACE (x)))
4157 rtx reg = regno_reg_rtx[FIRST_PSEUDO_REGISTER];
4158 rtx seq = combine_split_insns (gen_rtx_SET (VOIDmode, reg,
4162 /* This should have produced two insns, each of which sets our
4163 placeholder. If the source of the second is a valid address,
4164 we can make put both sources together and make a split point
4168 && NEXT_INSN (seq) != NULL_RTX
4169 && NEXT_INSN (NEXT_INSN (seq)) == NULL_RTX
4170 && NONJUMP_INSN_P (seq)
4171 && GET_CODE (PATTERN (seq)) == SET
4172 && SET_DEST (PATTERN (seq)) == reg
4173 && ! reg_mentioned_p (reg,
4174 SET_SRC (PATTERN (seq)))
4175 && NONJUMP_INSN_P (NEXT_INSN (seq))
4176 && GET_CODE (PATTERN (NEXT_INSN (seq))) == SET
4177 && SET_DEST (PATTERN (NEXT_INSN (seq))) == reg
4178 && memory_address_addr_space_p
4179 (GET_MODE (x), SET_SRC (PATTERN (NEXT_INSN (seq))),
4180 MEM_ADDR_SPACE (x)))
4182 rtx src1 = SET_SRC (PATTERN (seq));
4183 rtx src2 = SET_SRC (PATTERN (NEXT_INSN (seq)));
4185 /* Replace the placeholder in SRC2 with SRC1. If we can
4186 find where in SRC2 it was placed, that can become our
4187 split point and we can replace this address with SRC2.
4188 Just try two obvious places. */
4190 src2 = replace_rtx (src2, reg, src1);
4192 if (XEXP (src2, 0) == src1)
4193 split = &XEXP (src2, 0);
4194 else if (GET_RTX_FORMAT (GET_CODE (XEXP (src2, 0)))[0] == 'e'
4195 && XEXP (XEXP (src2, 0), 0) == src1)
4196 split = &XEXP (XEXP (src2, 0), 0);
4200 SUBST (XEXP (x, 0), src2);
4205 /* If that didn't work, perhaps the first operand is complex and
4206 needs to be computed separately, so make a split point there.
4207 This will occur on machines that just support REG + CONST
4208 and have a constant moved through some previous computation. */
4210 else if (!OBJECT_P (XEXP (XEXP (x, 0), 0))
4211 && ! (GET_CODE (XEXP (XEXP (x, 0), 0)) == SUBREG
4212 && OBJECT_P (SUBREG_REG (XEXP (XEXP (x, 0), 0)))))
4213 return &XEXP (XEXP (x, 0), 0);
4216 /* If we have a PLUS whose first operand is complex, try computing it
4217 separately by making a split there. */
4218 if (GET_CODE (XEXP (x, 0)) == PLUS
4219 && ! memory_address_addr_space_p (GET_MODE (x), XEXP (x, 0),
4221 && ! OBJECT_P (XEXP (XEXP (x, 0), 0))
4222 && ! (GET_CODE (XEXP (XEXP (x, 0), 0)) == SUBREG
4223 && OBJECT_P (SUBREG_REG (XEXP (XEXP (x, 0), 0)))))
4224 return &XEXP (XEXP (x, 0), 0);
4229 /* If SET_DEST is CC0 and SET_SRC is not an operand, a COMPARE, or a
4230 ZERO_EXTRACT, the most likely reason why this doesn't match is that
4231 we need to put the operand into a register. So split at that
4234 if (SET_DEST (x) == cc0_rtx
4235 && GET_CODE (SET_SRC (x)) != COMPARE
4236 && GET_CODE (SET_SRC (x)) != ZERO_EXTRACT
4237 && !OBJECT_P (SET_SRC (x))
4238 && ! (GET_CODE (SET_SRC (x)) == SUBREG
4239 && OBJECT_P (SUBREG_REG (SET_SRC (x)))))
4240 return &SET_SRC (x);
4243 /* See if we can split SET_SRC as it stands. */
4244 split = find_split_point (&SET_SRC (x), insn, true);
4245 if (split && split != &SET_SRC (x))
4248 /* See if we can split SET_DEST as it stands. */
4249 split = find_split_point (&SET_DEST (x), insn, false);
4250 if (split && split != &SET_DEST (x))
4253 /* See if this is a bitfield assignment with everything constant. If
4254 so, this is an IOR of an AND, so split it into that. */
4255 if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
4256 && (GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0)))
4257 <= HOST_BITS_PER_WIDE_INT)
4258 && CONST_INT_P (XEXP (SET_DEST (x), 1))
4259 && CONST_INT_P (XEXP (SET_DEST (x), 2))
4260 && CONST_INT_P (SET_SRC (x))
4261 && ((INTVAL (XEXP (SET_DEST (x), 1))
4262 + INTVAL (XEXP (SET_DEST (x), 2)))
4263 <= GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0))))
4264 && ! side_effects_p (XEXP (SET_DEST (x), 0)))
4266 HOST_WIDE_INT pos = INTVAL (XEXP (SET_DEST (x), 2));
4267 unsigned HOST_WIDE_INT len = INTVAL (XEXP (SET_DEST (x), 1));
4268 unsigned HOST_WIDE_INT src = INTVAL (SET_SRC (x));
4269 rtx dest = XEXP (SET_DEST (x), 0);
4270 enum machine_mode mode = GET_MODE (dest);
4271 unsigned HOST_WIDE_INT mask = ((HOST_WIDE_INT) 1 << len) - 1;
4274 if (BITS_BIG_ENDIAN)
4275 pos = GET_MODE_BITSIZE (mode) - len - pos;
4277 or_mask = gen_int_mode (src << pos, mode);
4280 simplify_gen_binary (IOR, mode, dest, or_mask));
4283 rtx negmask = gen_int_mode (~(mask << pos), mode);
4285 simplify_gen_binary (IOR, mode,
4286 simplify_gen_binary (AND, mode,
4291 SUBST (SET_DEST (x), dest);
4293 split = find_split_point (&SET_SRC (x), insn, true);
4294 if (split && split != &SET_SRC (x))
4298 /* Otherwise, see if this is an operation that we can split into two.
4299 If so, try to split that. */
4300 code = GET_CODE (SET_SRC (x));
4305 /* If we are AND'ing with a large constant that is only a single
4306 bit and the result is only being used in a context where we
4307 need to know if it is zero or nonzero, replace it with a bit
4308 extraction. This will avoid the large constant, which might
4309 have taken more than one insn to make. If the constant were
4310 not a valid argument to the AND but took only one insn to make,
4311 this is no worse, but if it took more than one insn, it will
4314 if (CONST_INT_P (XEXP (SET_SRC (x), 1))
4315 && REG_P (XEXP (SET_SRC (x), 0))
4316 && (pos = exact_log2 (INTVAL (XEXP (SET_SRC (x), 1)))) >= 7
4317 && REG_P (SET_DEST (x))
4318 && (split = find_single_use (SET_DEST (x), insn, (rtx*) 0)) != 0
4319 && (GET_CODE (*split) == EQ || GET_CODE (*split) == NE)
4320 && XEXP (*split, 0) == SET_DEST (x)
4321 && XEXP (*split, 1) == const0_rtx)
4323 rtx extraction = make_extraction (GET_MODE (SET_DEST (x)),
4324 XEXP (SET_SRC (x), 0),
4325 pos, NULL_RTX, 1, 1, 0, 0);
4326 if (extraction != 0)
4328 SUBST (SET_SRC (x), extraction);
4329 return find_split_point (loc, insn, false);
4335 /* If STORE_FLAG_VALUE is -1, this is (NE X 0) and only one bit of X
4336 is known to be on, this can be converted into a NEG of a shift. */
4337 if (STORE_FLAG_VALUE == -1 && XEXP (SET_SRC (x), 1) == const0_rtx
4338 && GET_MODE (SET_SRC (x)) == GET_MODE (XEXP (SET_SRC (x), 0))
4339 && 1 <= (pos = exact_log2
4340 (nonzero_bits (XEXP (SET_SRC (x), 0),
4341 GET_MODE (XEXP (SET_SRC (x), 0))))))
4343 enum machine_mode mode = GET_MODE (XEXP (SET_SRC (x), 0));
4347 gen_rtx_LSHIFTRT (mode,
4348 XEXP (SET_SRC (x), 0),
4351 split = find_split_point (&SET_SRC (x), insn, true);
4352 if (split && split != &SET_SRC (x))
4358 inner = XEXP (SET_SRC (x), 0);
4360 /* We can't optimize if either mode is a partial integer
4361 mode as we don't know how many bits are significant
4363 if (GET_MODE_CLASS (GET_MODE (inner)) == MODE_PARTIAL_INT
4364 || GET_MODE_CLASS (GET_MODE (SET_SRC (x))) == MODE_PARTIAL_INT)
4368 len = GET_MODE_BITSIZE (GET_MODE (inner));
4374 if (CONST_INT_P (XEXP (SET_SRC (x), 1))
4375 && CONST_INT_P (XEXP (SET_SRC (x), 2)))
4377 inner = XEXP (SET_SRC (x), 0);
4378 len = INTVAL (XEXP (SET_SRC (x), 1));
4379 pos = INTVAL (XEXP (SET_SRC (x), 2));
4381 if (BITS_BIG_ENDIAN)
4382 pos = GET_MODE_BITSIZE (GET_MODE (inner)) - len - pos;
4383 unsignedp = (code == ZERO_EXTRACT);
4391 if (len && pos >= 0 && pos + len <= GET_MODE_BITSIZE (GET_MODE (inner)))
4393 enum machine_mode mode = GET_MODE (SET_SRC (x));
4395 /* For unsigned, we have a choice of a shift followed by an
4396 AND or two shifts. Use two shifts for field sizes where the
4397 constant might be too large. We assume here that we can
4398 always at least get 8-bit constants in an AND insn, which is
4399 true for every current RISC. */
4401 if (unsignedp && len <= 8)
4406 (mode, gen_lowpart (mode, inner),
4408 GEN_INT (((HOST_WIDE_INT) 1 << len) - 1)));
4410 split = find_split_point (&SET_SRC (x), insn, true);
4411 if (split && split != &SET_SRC (x))
4418 (unsignedp ? LSHIFTRT : ASHIFTRT, mode,
4419 gen_rtx_ASHIFT (mode,
4420 gen_lowpart (mode, inner),
4421 GEN_INT (GET_MODE_BITSIZE (mode)
4423 GEN_INT (GET_MODE_BITSIZE (mode) - len)));
4425 split = find_split_point (&SET_SRC (x), insn, true);
4426 if (split && split != &SET_SRC (x))
4431 /* See if this is a simple operation with a constant as the second
4432 operand. It might be that this constant is out of range and hence
4433 could be used as a split point. */
4434 if (BINARY_P (SET_SRC (x))
4435 && CONSTANT_P (XEXP (SET_SRC (x), 1))
4436 && (OBJECT_P (XEXP (SET_SRC (x), 0))
4437 || (GET_CODE (XEXP (SET_SRC (x), 0)) == SUBREG
4438 && OBJECT_P (SUBREG_REG (XEXP (SET_SRC (x), 0))))))
4439 return &XEXP (SET_SRC (x), 1);
4441 /* Finally, see if this is a simple operation with its first operand
4442 not in a register. The operation might require this operand in a
4443 register, so return it as a split point. We can always do this
4444 because if the first operand were another operation, we would have
4445 already found it as a split point. */
4446 if ((BINARY_P (SET_SRC (x)) || UNARY_P (SET_SRC (x)))
4447 && ! register_operand (XEXP (SET_SRC (x), 0), VOIDmode))
4448 return &XEXP (SET_SRC (x), 0);
4454 /* We write NOR as (and (not A) (not B)), but if we don't have a NOR,
4455 it is better to write this as (not (ior A B)) so we can split it.
4456 Similarly for IOR. */
4457 if (GET_CODE (XEXP (x, 0)) == NOT && GET_CODE (XEXP (x, 1)) == NOT)
4460 gen_rtx_NOT (GET_MODE (x),
4461 gen_rtx_fmt_ee (code == IOR ? AND : IOR,
4463 XEXP (XEXP (x, 0), 0),
4464 XEXP (XEXP (x, 1), 0))));
4465 return find_split_point (loc, insn, set_src);
4468 /* Many RISC machines have a large set of logical insns. If the
4469 second operand is a NOT, put it first so we will try to split the
4470 other operand first. */
4471 if (GET_CODE (XEXP (x, 1)) == NOT)
4473 rtx tem = XEXP (x, 0);
4474 SUBST (XEXP (x, 0), XEXP (x, 1));
4475 SUBST (XEXP (x, 1), tem);
4481 /* Split at a multiply-accumulate instruction. However if this is
4482 the SET_SRC, we likely do not have such an instruction and it's
4483 worthless to try this split. */
4484 if (!set_src && GET_CODE (XEXP (x, 0)) == MULT)
4491 /* Otherwise, select our actions depending on our rtx class. */
4492 switch (GET_RTX_CLASS (code))
4494 case RTX_BITFIELD_OPS: /* This is ZERO_EXTRACT and SIGN_EXTRACT. */
4496 split = find_split_point (&XEXP (x, 2), insn, false);
4499 /* ... fall through ... */
4501 case RTX_COMM_ARITH:
4503 case RTX_COMM_COMPARE:
4504 split = find_split_point (&XEXP (x, 1), insn, false);
4507 /* ... fall through ... */
4509 /* Some machines have (and (shift ...) ...) insns. If X is not
4510 an AND, but XEXP (X, 0) is, use it as our split point. */
4511 if (GET_CODE (x) != AND && GET_CODE (XEXP (x, 0)) == AND)
4512 return &XEXP (x, 0);
4514 split = find_split_point (&XEXP (x, 0), insn, false);
4520 /* Otherwise, we don't have a split point. */
4525 /* Throughout X, replace FROM with TO, and return the result.
4526 The result is TO if X is FROM;
4527 otherwise the result is X, but its contents may have been modified.
4528 If they were modified, a record was made in undobuf so that
4529 undo_all will (among other things) return X to its original state.
4531 If the number of changes necessary is too much to record to undo,
4532 the excess changes are not made, so the result is invalid.
4533 The changes already made can still be undone.
4534 undobuf.num_undo is incremented for such changes, so by testing that
4535 the caller can tell whether the result is valid.
4537 `n_occurrences' is incremented each time FROM is replaced.
4539 IN_DEST is nonzero if we are processing the SET_DEST of a SET.
4541 UNIQUE_COPY is nonzero if each substitution must be unique. We do this
4542 by copying if `n_occurrences' is nonzero. */
4545 subst (rtx x, rtx from, rtx to, int in_dest, int unique_copy)
4547 enum rtx_code code = GET_CODE (x);
4548 enum machine_mode op0_mode = VOIDmode;
4553 /* Two expressions are equal if they are identical copies of a shared
4554 RTX or if they are both registers with the same register number
4557 #define COMBINE_RTX_EQUAL_P(X,Y) \
4559 || (REG_P (X) && REG_P (Y) \
4560 && REGNO (X) == REGNO (Y) && GET_MODE (X) == GET_MODE (Y)))
4562 if (! in_dest && COMBINE_RTX_EQUAL_P (x, from))
4565 return (unique_copy && n_occurrences > 1 ? copy_rtx (to) : to);
4568 /* If X and FROM are the same register but different modes, they
4569 will not have been seen as equal above. However, the log links code
4570 will make a LOG_LINKS entry for that case. If we do nothing, we
4571 will try to rerecognize our original insn and, when it succeeds,
4572 we will delete the feeding insn, which is incorrect.
4574 So force this insn not to match in this (rare) case. */
4575 if (! in_dest && code == REG && REG_P (from)
4576 && reg_overlap_mentioned_p (x, from))
4577 return gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
4579 /* If this is an object, we are done unless it is a MEM or LO_SUM, both
4580 of which may contain things that can be combined. */
4581 if (code != MEM && code != LO_SUM && OBJECT_P (x))
4584 /* It is possible to have a subexpression appear twice in the insn.
4585 Suppose that FROM is a register that appears within TO.
4586 Then, after that subexpression has been scanned once by `subst',
4587 the second time it is scanned, TO may be found. If we were
4588 to scan TO here, we would find FROM within it and create a
4589 self-referent rtl structure which is completely wrong. */
4590 if (COMBINE_RTX_EQUAL_P (x, to))
4593 /* Parallel asm_operands need special attention because all of the
4594 inputs are shared across the arms. Furthermore, unsharing the
4595 rtl results in recognition failures. Failure to handle this case
4596 specially can result in circular rtl.
4598 Solve this by doing a normal pass across the first entry of the
4599 parallel, and only processing the SET_DESTs of the subsequent
4602 if (code == PARALLEL
4603 && GET_CODE (XVECEXP (x, 0, 0)) == SET
4604 && GET_CODE (SET_SRC (XVECEXP (x, 0, 0))) == ASM_OPERANDS)
4606 new_rtx = subst (XVECEXP (x, 0, 0), from, to, 0, unique_copy);
4608 /* If this substitution failed, this whole thing fails. */
4609 if (GET_CODE (new_rtx) == CLOBBER
4610 && XEXP (new_rtx, 0) == const0_rtx)
4613 SUBST (XVECEXP (x, 0, 0), new_rtx);
4615 for (i = XVECLEN (x, 0) - 1; i >= 1; i--)
4617 rtx dest = SET_DEST (XVECEXP (x, 0, i));
4620 && GET_CODE (dest) != CC0
4621 && GET_CODE (dest) != PC)
4623 new_rtx = subst (dest, from, to, 0, unique_copy);
4625 /* If this substitution failed, this whole thing fails. */
4626 if (GET_CODE (new_rtx) == CLOBBER
4627 && XEXP (new_rtx, 0) == const0_rtx)
4630 SUBST (SET_DEST (XVECEXP (x, 0, i)), new_rtx);
4636 len = GET_RTX_LENGTH (code);
4637 fmt = GET_RTX_FORMAT (code);
4639 /* We don't need to process a SET_DEST that is a register, CC0,
4640 or PC, so set up to skip this common case. All other cases
4641 where we want to suppress replacing something inside a
4642 SET_SRC are handled via the IN_DEST operand. */
4644 && (REG_P (SET_DEST (x))
4645 || GET_CODE (SET_DEST (x)) == CC0
4646 || GET_CODE (SET_DEST (x)) == PC))
4649 /* Get the mode of operand 0 in case X is now a SIGN_EXTEND of a
4652 op0_mode = GET_MODE (XEXP (x, 0));
4654 for (i = 0; i < len; i++)
4659 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
4661 if (COMBINE_RTX_EQUAL_P (XVECEXP (x, i, j), from))
4663 new_rtx = (unique_copy && n_occurrences
4664 ? copy_rtx (to) : to);
4669 new_rtx = subst (XVECEXP (x, i, j), from, to, 0,
4672 /* If this substitution failed, this whole thing
4674 if (GET_CODE (new_rtx) == CLOBBER
4675 && XEXP (new_rtx, 0) == const0_rtx)
4679 SUBST (XVECEXP (x, i, j), new_rtx);
4682 else if (fmt[i] == 'e')
4684 /* If this is a register being set, ignore it. */
4685 new_rtx = XEXP (x, i);
4688 && (((code == SUBREG || code == ZERO_EXTRACT)
4690 || code == STRICT_LOW_PART))
4693 else if (COMBINE_RTX_EQUAL_P (XEXP (x, i), from))
4695 /* In general, don't install a subreg involving two
4696 modes not tieable. It can worsen register
4697 allocation, and can even make invalid reload
4698 insns, since the reg inside may need to be copied
4699 from in the outside mode, and that may be invalid
4700 if it is an fp reg copied in integer mode.
4702 We allow two exceptions to this: It is valid if
4703 it is inside another SUBREG and the mode of that
4704 SUBREG and the mode of the inside of TO is
4705 tieable and it is valid if X is a SET that copies
4708 if (GET_CODE (to) == SUBREG
4709 && ! MODES_TIEABLE_P (GET_MODE (to),
4710 GET_MODE (SUBREG_REG (to)))
4711 && ! (code == SUBREG
4712 && MODES_TIEABLE_P (GET_MODE (x),
4713 GET_MODE (SUBREG_REG (to))))
4715 && ! (code == SET && i == 1 && XEXP (x, 0) == cc0_rtx)
4718 return gen_rtx_CLOBBER (VOIDmode, const0_rtx);
4720 #ifdef CANNOT_CHANGE_MODE_CLASS
4723 && REGNO (to) < FIRST_PSEUDO_REGISTER
4724 && REG_CANNOT_CHANGE_MODE_P (REGNO (to),
4727 return gen_rtx_CLOBBER (VOIDmode, const0_rtx);
4730 new_rtx = (unique_copy && n_occurrences ? copy_rtx (to) : to);
4734 /* If we are in a SET_DEST, suppress most cases unless we
4735 have gone inside a MEM, in which case we want to
4736 simplify the address. We assume here that things that
4737 are actually part of the destination have their inner
4738 parts in the first expression. This is true for SUBREG,
4739 STRICT_LOW_PART, and ZERO_EXTRACT, which are the only
4740 things aside from REG and MEM that should appear in a
4742 new_rtx = subst (XEXP (x, i), from, to,
4744 && (code == SUBREG || code == STRICT_LOW_PART
4745 || code == ZERO_EXTRACT))
4747 && i == 0), unique_copy);
4749 /* If we found that we will have to reject this combination,
4750 indicate that by returning the CLOBBER ourselves, rather than
4751 an expression containing it. This will speed things up as
4752 well as prevent accidents where two CLOBBERs are considered
4753 to be equal, thus producing an incorrect simplification. */
4755 if (GET_CODE (new_rtx) == CLOBBER && XEXP (new_rtx, 0) == const0_rtx)
4758 if (GET_CODE (x) == SUBREG
4759 && (CONST_INT_P (new_rtx)
4760 || GET_CODE (new_rtx) == CONST_DOUBLE))
4762 enum machine_mode mode = GET_MODE (x);
4764 x = simplify_subreg (GET_MODE (x), new_rtx,
4765 GET_MODE (SUBREG_REG (x)),
4768 x = gen_rtx_CLOBBER (mode, const0_rtx);
4770 else if (CONST_INT_P (new_rtx)
4771 && GET_CODE (x) == ZERO_EXTEND)
4773 x = simplify_unary_operation (ZERO_EXTEND, GET_MODE (x),
4774 new_rtx, GET_MODE (XEXP (x, 0)));
4778 SUBST (XEXP (x, i), new_rtx);
4783 /* Check if we are loading something from the constant pool via float
4784 extension; in this case we would undo compress_float_constant
4785 optimization and degenerate constant load to an immediate value. */
4786 if (GET_CODE (x) == FLOAT_EXTEND
4787 && MEM_P (XEXP (x, 0))
4788 && MEM_READONLY_P (XEXP (x, 0)))
4790 rtx tmp = avoid_constant_pool_reference (x);
4795 /* Try to simplify X. If the simplification changed the code, it is likely
4796 that further simplification will help, so loop, but limit the number
4797 of repetitions that will be performed. */
4799 for (i = 0; i < 4; i++)
4801 /* If X is sufficiently simple, don't bother trying to do anything
4803 if (code != CONST_INT && code != REG && code != CLOBBER)
4804 x = combine_simplify_rtx (x, op0_mode, in_dest);
4806 if (GET_CODE (x) == code)
4809 code = GET_CODE (x);
4811 /* We no longer know the original mode of operand 0 since we
4812 have changed the form of X) */
4813 op0_mode = VOIDmode;
4819 /* Simplify X, a piece of RTL. We just operate on the expression at the
4820 outer level; call `subst' to simplify recursively. Return the new
4823 OP0_MODE is the original mode of XEXP (x, 0). IN_DEST is nonzero
4824 if we are inside a SET_DEST. */
4827 combine_simplify_rtx (rtx x, enum machine_mode op0_mode, int in_dest)
4829 enum rtx_code code = GET_CODE (x);
4830 enum machine_mode mode = GET_MODE (x);
4834 /* If this is a commutative operation, put a constant last and a complex
4835 expression first. We don't need to do this for comparisons here. */
4836 if (COMMUTATIVE_ARITH_P (x)
4837 && swap_commutative_operands_p (XEXP (x, 0), XEXP (x, 1)))
4840 SUBST (XEXP (x, 0), XEXP (x, 1));
4841 SUBST (XEXP (x, 1), temp);
4844 /* If this is a simple operation applied to an IF_THEN_ELSE, try
4845 applying it to the arms of the IF_THEN_ELSE. This often simplifies
4846 things. Check for cases where both arms are testing the same
4849 Don't do anything if all operands are very simple. */
4852 && ((!OBJECT_P (XEXP (x, 0))
4853 && ! (GET_CODE (XEXP (x, 0)) == SUBREG
4854 && OBJECT_P (SUBREG_REG (XEXP (x, 0)))))
4855 || (!OBJECT_P (XEXP (x, 1))
4856 && ! (GET_CODE (XEXP (x, 1)) == SUBREG
4857 && OBJECT_P (SUBREG_REG (XEXP (x, 1)))))))
4859 && (!OBJECT_P (XEXP (x, 0))
4860 && ! (GET_CODE (XEXP (x, 0)) == SUBREG
4861 && OBJECT_P (SUBREG_REG (XEXP (x, 0)))))))
4863 rtx cond, true_rtx, false_rtx;
4865 cond = if_then_else_cond (x, &true_rtx, &false_rtx);
4867 /* If everything is a comparison, what we have is highly unlikely
4868 to be simpler, so don't use it. */
4869 && ! (COMPARISON_P (x)
4870 && (COMPARISON_P (true_rtx) || COMPARISON_P (false_rtx))))
4872 rtx cop1 = const0_rtx;
4873 enum rtx_code cond_code = simplify_comparison (NE, &cond, &cop1);
4875 if (cond_code == NE && COMPARISON_P (cond))
4878 /* Simplify the alternative arms; this may collapse the true and
4879 false arms to store-flag values. Be careful to use copy_rtx
4880 here since true_rtx or false_rtx might share RTL with x as a
4881 result of the if_then_else_cond call above. */
4882 true_rtx = subst (copy_rtx (true_rtx), pc_rtx, pc_rtx, 0, 0);
4883 false_rtx = subst (copy_rtx (false_rtx), pc_rtx, pc_rtx, 0, 0);
4885 /* If true_rtx and false_rtx are not general_operands, an if_then_else
4886 is unlikely to be simpler. */
4887 if (general_operand (true_rtx, VOIDmode)
4888 && general_operand (false_rtx, VOIDmode))
4890 enum rtx_code reversed;
4892 /* Restarting if we generate a store-flag expression will cause
4893 us to loop. Just drop through in this case. */
4895 /* If the result values are STORE_FLAG_VALUE and zero, we can
4896 just make the comparison operation. */
4897 if (true_rtx == const_true_rtx && false_rtx == const0_rtx)
4898 x = simplify_gen_relational (cond_code, mode, VOIDmode,
4900 else if (true_rtx == const0_rtx && false_rtx == const_true_rtx
4901 && ((reversed = reversed_comparison_code_parts
4902 (cond_code, cond, cop1, NULL))
4904 x = simplify_gen_relational (reversed, mode, VOIDmode,
4907 /* Likewise, we can make the negate of a comparison operation
4908 if the result values are - STORE_FLAG_VALUE and zero. */
4909 else if (CONST_INT_P (true_rtx)
4910 && INTVAL (true_rtx) == - STORE_FLAG_VALUE
4911 && false_rtx == const0_rtx)
4912 x = simplify_gen_unary (NEG, mode,
4913 simplify_gen_relational (cond_code,
4917 else if (CONST_INT_P (false_rtx)
4918 && INTVAL (false_rtx) == - STORE_FLAG_VALUE
4919 && true_rtx == const0_rtx
4920 && ((reversed = reversed_comparison_code_parts
4921 (cond_code, cond, cop1, NULL))
4923 x = simplify_gen_unary (NEG, mode,
4924 simplify_gen_relational (reversed,
4929 return gen_rtx_IF_THEN_ELSE (mode,
4930 simplify_gen_relational (cond_code,
4935 true_rtx, false_rtx);
4937 code = GET_CODE (x);
4938 op0_mode = VOIDmode;
4943 /* Try to fold this expression in case we have constants that weren't
4946 switch (GET_RTX_CLASS (code))
4949 if (op0_mode == VOIDmode)
4950 op0_mode = GET_MODE (XEXP (x, 0));
4951 temp = simplify_unary_operation (code, mode, XEXP (x, 0), op0_mode);
4954 case RTX_COMM_COMPARE:
4956 enum machine_mode cmp_mode = GET_MODE (XEXP (x, 0));
4957 if (cmp_mode == VOIDmode)
4959 cmp_mode = GET_MODE (XEXP (x, 1));
4960 if (cmp_mode == VOIDmode)
4961 cmp_mode = op0_mode;
4963 temp = simplify_relational_operation (code, mode, cmp_mode,
4964 XEXP (x, 0), XEXP (x, 1));
4967 case RTX_COMM_ARITH:
4969 temp = simplify_binary_operation (code, mode, XEXP (x, 0), XEXP (x, 1));
4971 case RTX_BITFIELD_OPS:
4973 temp = simplify_ternary_operation (code, mode, op0_mode, XEXP (x, 0),
4974 XEXP (x, 1), XEXP (x, 2));
4983 code = GET_CODE (temp);
4984 op0_mode = VOIDmode;
4985 mode = GET_MODE (temp);
4988 /* First see if we can apply the inverse distributive law. */
4989 if (code == PLUS || code == MINUS
4990 || code == AND || code == IOR || code == XOR)
4992 x = apply_distributive_law (x);
4993 code = GET_CODE (x);
4994 op0_mode = VOIDmode;
4997 /* If CODE is an associative operation not otherwise handled, see if we
4998 can associate some operands. This can win if they are constants or
4999 if they are logically related (i.e. (a & b) & a). */
5000 if ((code == PLUS || code == MINUS || code == MULT || code == DIV
5001 || code == AND || code == IOR || code == XOR
5002 || code == SMAX || code == SMIN || code == UMAX || code == UMIN)
5003 && ((INTEGRAL_MODE_P (mode) && code != DIV)
5004 || (flag_associative_math && FLOAT_MODE_P (mode))))
5006 if (GET_CODE (XEXP (x, 0)) == code)
5008 rtx other = XEXP (XEXP (x, 0), 0);
5009 rtx inner_op0 = XEXP (XEXP (x, 0), 1);
5010 rtx inner_op1 = XEXP (x, 1);
5013 /* Make sure we pass the constant operand if any as the second
5014 one if this is a commutative operation. */
5015 if (CONSTANT_P (inner_op0) && COMMUTATIVE_ARITH_P (x))
5017 rtx tem = inner_op0;
5018 inner_op0 = inner_op1;
5021 inner = simplify_binary_operation (code == MINUS ? PLUS
5022 : code == DIV ? MULT
5024 mode, inner_op0, inner_op1);
5026 /* For commutative operations, try the other pair if that one
5028 if (inner == 0 && COMMUTATIVE_ARITH_P (x))
5030 other = XEXP (XEXP (x, 0), 1);
5031 inner = simplify_binary_operation (code, mode,
5032 XEXP (XEXP (x, 0), 0),
5037 return simplify_gen_binary (code, mode, other, inner);
5041 /* A little bit of algebraic simplification here. */
5045 /* Ensure that our address has any ASHIFTs converted to MULT in case
5046 address-recognizing predicates are called later. */
5047 temp = make_compound_operation (XEXP (x, 0), MEM);
5048 SUBST (XEXP (x, 0), temp);
5052 if (op0_mode == VOIDmode)
5053 op0_mode = GET_MODE (SUBREG_REG (x));
5055 /* See if this can be moved to simplify_subreg. */
5056 if (CONSTANT_P (SUBREG_REG (x))
5057 && subreg_lowpart_offset (mode, op0_mode) == SUBREG_BYTE (x)
5058 /* Don't call gen_lowpart if the inner mode
5059 is VOIDmode and we cannot simplify it, as SUBREG without
5060 inner mode is invalid. */
5061 && (GET_MODE (SUBREG_REG (x)) != VOIDmode
5062 || gen_lowpart_common (mode, SUBREG_REG (x))))
5063 return gen_lowpart (mode, SUBREG_REG (x));
5065 if (GET_MODE_CLASS (GET_MODE (SUBREG_REG (x))) == MODE_CC)
5069 temp = simplify_subreg (mode, SUBREG_REG (x), op0_mode,
5075 /* Don't change the mode of the MEM if that would change the meaning
5077 if (MEM_P (SUBREG_REG (x))
5078 && (MEM_VOLATILE_P (SUBREG_REG (x))
5079 || mode_dependent_address_p (XEXP (SUBREG_REG (x), 0))))
5080 return gen_rtx_CLOBBER (mode, const0_rtx);
5082 /* Note that we cannot do any narrowing for non-constants since
5083 we might have been counting on using the fact that some bits were
5084 zero. We now do this in the SET. */
5089 temp = expand_compound_operation (XEXP (x, 0));
5091 /* For C equal to the width of MODE minus 1, (neg (ashiftrt X C)) can be
5092 replaced by (lshiftrt X C). This will convert
5093 (neg (sign_extract X 1 Y)) to (zero_extract X 1 Y). */
5095 if (GET_CODE (temp) == ASHIFTRT
5096 && CONST_INT_P (XEXP (temp, 1))
5097 && INTVAL (XEXP (temp, 1)) == GET_MODE_BITSIZE (mode) - 1)
5098 return simplify_shift_const (NULL_RTX, LSHIFTRT, mode, XEXP (temp, 0),
5099 INTVAL (XEXP (temp, 1)));
5101 /* If X has only a single bit that might be nonzero, say, bit I, convert
5102 (neg X) to (ashiftrt (ashift X C-I) C-I) where C is the bitsize of
5103 MODE minus 1. This will convert (neg (zero_extract X 1 Y)) to
5104 (sign_extract X 1 Y). But only do this if TEMP isn't a register
5105 or a SUBREG of one since we'd be making the expression more
5106 complex if it was just a register. */
5109 && ! (GET_CODE (temp) == SUBREG
5110 && REG_P (SUBREG_REG (temp)))
5111 && (i = exact_log2 (nonzero_bits (temp, mode))) >= 0)
5113 rtx temp1 = simplify_shift_const
5114 (NULL_RTX, ASHIFTRT, mode,
5115 simplify_shift_const (NULL_RTX, ASHIFT, mode, temp,
5116 GET_MODE_BITSIZE (mode) - 1 - i),
5117 GET_MODE_BITSIZE (mode) - 1 - i);
5119 /* If all we did was surround TEMP with the two shifts, we
5120 haven't improved anything, so don't use it. Otherwise,
5121 we are better off with TEMP1. */
5122 if (GET_CODE (temp1) != ASHIFTRT
5123 || GET_CODE (XEXP (temp1, 0)) != ASHIFT
5124 || XEXP (XEXP (temp1, 0), 0) != temp)
5130 /* We can't handle truncation to a partial integer mode here
5131 because we don't know the real bitsize of the partial
5133 if (GET_MODE_CLASS (mode) == MODE_PARTIAL_INT)
5136 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
5138 force_to_mode (XEXP (x, 0), GET_MODE (XEXP (x, 0)),
5139 GET_MODE_MASK (mode), 0));
5141 /* We can truncate a constant value and return it. */
5142 if (CONST_INT_P (XEXP (x, 0)))
5143 return gen_int_mode (INTVAL (XEXP (x, 0)), mode);
5145 /* Similarly to what we do in simplify-rtx.c, a truncate of a register
5146 whose value is a comparison can be replaced with a subreg if
5147 STORE_FLAG_VALUE permits. */
5148 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5149 && ((HOST_WIDE_INT) STORE_FLAG_VALUE & ~GET_MODE_MASK (mode)) == 0
5150 && (temp = get_last_value (XEXP (x, 0)))
5151 && COMPARISON_P (temp))
5152 return gen_lowpart (mode, XEXP (x, 0));
5156 /* (const (const X)) can become (const X). Do it this way rather than
5157 returning the inner CONST since CONST can be shared with a
5159 if (GET_CODE (XEXP (x, 0)) == CONST)
5160 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
5165 /* Convert (lo_sum (high FOO) FOO) to FOO. This is necessary so we
5166 can add in an offset. find_split_point will split this address up
5167 again if it doesn't match. */
5168 if (GET_CODE (XEXP (x, 0)) == HIGH
5169 && rtx_equal_p (XEXP (XEXP (x, 0), 0), XEXP (x, 1)))
5175 /* (plus (xor (and <foo> (const_int pow2 - 1)) <c>) <-c>)
5176 when c is (const_int (pow2 + 1) / 2) is a sign extension of a
5177 bit-field and can be replaced by either a sign_extend or a
5178 sign_extract. The `and' may be a zero_extend and the two
5179 <c>, -<c> constants may be reversed. */
5180 if (GET_CODE (XEXP (x, 0)) == XOR
5181 && CONST_INT_P (XEXP (x, 1))
5182 && CONST_INT_P (XEXP (XEXP (x, 0), 1))
5183 && INTVAL (XEXP (x, 1)) == -INTVAL (XEXP (XEXP (x, 0), 1))
5184 && ((i = exact_log2 (INTVAL (XEXP (XEXP (x, 0), 1)))) >= 0
5185 || (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0)
5186 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5187 && ((GET_CODE (XEXP (XEXP (x, 0), 0)) == AND
5188 && CONST_INT_P (XEXP (XEXP (XEXP (x, 0), 0), 1))
5189 && (INTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1))
5190 == ((HOST_WIDE_INT) 1 << (i + 1)) - 1))
5191 || (GET_CODE (XEXP (XEXP (x, 0), 0)) == ZERO_EXTEND
5192 && (GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)))
5193 == (unsigned int) i + 1))))
5194 return simplify_shift_const
5195 (NULL_RTX, ASHIFTRT, mode,
5196 simplify_shift_const (NULL_RTX, ASHIFT, mode,
5197 XEXP (XEXP (XEXP (x, 0), 0), 0),
5198 GET_MODE_BITSIZE (mode) - (i + 1)),
5199 GET_MODE_BITSIZE (mode) - (i + 1));
5201 /* If only the low-order bit of X is possibly nonzero, (plus x -1)
5202 can become (ashiftrt (ashift (xor x 1) C) C) where C is
5203 the bitsize of the mode - 1. This allows simplification of
5204 "a = (b & 8) == 0;" */
5205 if (XEXP (x, 1) == constm1_rtx
5206 && !REG_P (XEXP (x, 0))
5207 && ! (GET_CODE (XEXP (x, 0)) == SUBREG
5208 && REG_P (SUBREG_REG (XEXP (x, 0))))
5209 && nonzero_bits (XEXP (x, 0), mode) == 1)
5210 return simplify_shift_const (NULL_RTX, ASHIFTRT, mode,
5211 simplify_shift_const (NULL_RTX, ASHIFT, mode,
5212 gen_rtx_XOR (mode, XEXP (x, 0), const1_rtx),
5213 GET_MODE_BITSIZE (mode) - 1),
5214 GET_MODE_BITSIZE (mode) - 1);
5216 /* If we are adding two things that have no bits in common, convert
5217 the addition into an IOR. This will often be further simplified,
5218 for example in cases like ((a & 1) + (a & 2)), which can
5221 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5222 && (nonzero_bits (XEXP (x, 0), mode)
5223 & nonzero_bits (XEXP (x, 1), mode)) == 0)
5225 /* Try to simplify the expression further. */
5226 rtx tor = simplify_gen_binary (IOR, mode, XEXP (x, 0), XEXP (x, 1));
5227 temp = combine_simplify_rtx (tor, mode, in_dest);
5229 /* If we could, great. If not, do not go ahead with the IOR
5230 replacement, since PLUS appears in many special purpose
5231 address arithmetic instructions. */
5232 if (GET_CODE (temp) != CLOBBER && temp != tor)
5238 /* (minus <foo> (and <foo> (const_int -pow2))) becomes
5239 (and <foo> (const_int pow2-1)) */
5240 if (GET_CODE (XEXP (x, 1)) == AND
5241 && CONST_INT_P (XEXP (XEXP (x, 1), 1))
5242 && exact_log2 (-INTVAL (XEXP (XEXP (x, 1), 1))) >= 0
5243 && rtx_equal_p (XEXP (XEXP (x, 1), 0), XEXP (x, 0)))
5244 return simplify_and_const_int (NULL_RTX, mode, XEXP (x, 0),
5245 -INTVAL (XEXP (XEXP (x, 1), 1)) - 1);
5249 /* If we have (mult (plus A B) C), apply the distributive law and then
5250 the inverse distributive law to see if things simplify. This
5251 occurs mostly in addresses, often when unrolling loops. */
5253 if (GET_CODE (XEXP (x, 0)) == PLUS)
5255 rtx result = distribute_and_simplify_rtx (x, 0);
5260 /* Try simplify a*(b/c) as (a*b)/c. */
5261 if (FLOAT_MODE_P (mode) && flag_associative_math
5262 && GET_CODE (XEXP (x, 0)) == DIV)
5264 rtx tem = simplify_binary_operation (MULT, mode,
5265 XEXP (XEXP (x, 0), 0),
5268 return simplify_gen_binary (DIV, mode, tem, XEXP (XEXP (x, 0), 1));
5273 /* If this is a divide by a power of two, treat it as a shift if
5274 its first operand is a shift. */
5275 if (CONST_INT_P (XEXP (x, 1))
5276 && (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0
5277 && (GET_CODE (XEXP (x, 0)) == ASHIFT
5278 || GET_CODE (XEXP (x, 0)) == LSHIFTRT
5279 || GET_CODE (XEXP (x, 0)) == ASHIFTRT
5280 || GET_CODE (XEXP (x, 0)) == ROTATE
5281 || GET_CODE (XEXP (x, 0)) == ROTATERT))
5282 return simplify_shift_const (NULL_RTX, LSHIFTRT, mode, XEXP (x, 0), i);
5286 case GT: case GTU: case GE: case GEU:
5287 case LT: case LTU: case LE: case LEU:
5288 case UNEQ: case LTGT:
5289 case UNGT: case UNGE:
5290 case UNLT: case UNLE:
5291 case UNORDERED: case ORDERED:
5292 /* If the first operand is a condition code, we can't do anything
5294 if (GET_CODE (XEXP (x, 0)) == COMPARE
5295 || (GET_MODE_CLASS (GET_MODE (XEXP (x, 0))) != MODE_CC
5296 && ! CC0_P (XEXP (x, 0))))
5298 rtx op0 = XEXP (x, 0);
5299 rtx op1 = XEXP (x, 1);
5300 enum rtx_code new_code;
5302 if (GET_CODE (op0) == COMPARE)
5303 op1 = XEXP (op0, 1), op0 = XEXP (op0, 0);
5305 /* Simplify our comparison, if possible. */
5306 new_code = simplify_comparison (code, &op0, &op1);
5308 /* If STORE_FLAG_VALUE is 1, we can convert (ne x 0) to simply X
5309 if only the low-order bit is possibly nonzero in X (such as when
5310 X is a ZERO_EXTRACT of one bit). Similarly, we can convert EQ to
5311 (xor X 1) or (minus 1 X); we use the former. Finally, if X is
5312 known to be either 0 or -1, NE becomes a NEG and EQ becomes
5315 Remove any ZERO_EXTRACT we made when thinking this was a
5316 comparison. It may now be simpler to use, e.g., an AND. If a
5317 ZERO_EXTRACT is indeed appropriate, it will be placed back by
5318 the call to make_compound_operation in the SET case. */
5320 if (STORE_FLAG_VALUE == 1
5321 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
5322 && op1 == const0_rtx
5323 && mode == GET_MODE (op0)
5324 && nonzero_bits (op0, mode) == 1)
5325 return gen_lowpart (mode,
5326 expand_compound_operation (op0));
5328 else if (STORE_FLAG_VALUE == 1
5329 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
5330 && op1 == const0_rtx
5331 && mode == GET_MODE (op0)
5332 && (num_sign_bit_copies (op0, mode)
5333 == GET_MODE_BITSIZE (mode)))
5335 op0 = expand_compound_operation (op0);
5336 return simplify_gen_unary (NEG, mode,
5337 gen_lowpart (mode, op0),
5341 else if (STORE_FLAG_VALUE == 1
5342 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
5343 && op1 == const0_rtx
5344 && mode == GET_MODE (op0)
5345 && nonzero_bits (op0, mode) == 1)
5347 op0 = expand_compound_operation (op0);
5348 return simplify_gen_binary (XOR, mode,
5349 gen_lowpart (mode, op0),
5353 else if (STORE_FLAG_VALUE == 1
5354 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
5355 && op1 == const0_rtx
5356 && mode == GET_MODE (op0)
5357 && (num_sign_bit_copies (op0, mode)
5358 == GET_MODE_BITSIZE (mode)))
5360 op0 = expand_compound_operation (op0);
5361 return plus_constant (gen_lowpart (mode, op0), 1);
5364 /* If STORE_FLAG_VALUE is -1, we have cases similar to
5366 if (STORE_FLAG_VALUE == -1
5367 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
5368 && op1 == const0_rtx
5369 && (num_sign_bit_copies (op0, mode)
5370 == GET_MODE_BITSIZE (mode)))
5371 return gen_lowpart (mode,
5372 expand_compound_operation (op0));
5374 else if (STORE_FLAG_VALUE == -1
5375 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
5376 && op1 == const0_rtx
5377 && mode == GET_MODE (op0)
5378 && nonzero_bits (op0, mode) == 1)
5380 op0 = expand_compound_operation (op0);
5381 return simplify_gen_unary (NEG, mode,
5382 gen_lowpart (mode, op0),
5386 else if (STORE_FLAG_VALUE == -1
5387 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
5388 && op1 == const0_rtx
5389 && mode == GET_MODE (op0)
5390 && (num_sign_bit_copies (op0, mode)
5391 == GET_MODE_BITSIZE (mode)))
5393 op0 = expand_compound_operation (op0);
5394 return simplify_gen_unary (NOT, mode,
5395 gen_lowpart (mode, op0),
5399 /* If X is 0/1, (eq X 0) is X-1. */
5400 else if (STORE_FLAG_VALUE == -1
5401 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
5402 && op1 == const0_rtx
5403 && mode == GET_MODE (op0)
5404 && nonzero_bits (op0, mode) == 1)
5406 op0 = expand_compound_operation (op0);
5407 return plus_constant (gen_lowpart (mode, op0), -1);
5410 /* If STORE_FLAG_VALUE says to just test the sign bit and X has just
5411 one bit that might be nonzero, we can convert (ne x 0) to
5412 (ashift x c) where C puts the bit in the sign bit. Remove any
5413 AND with STORE_FLAG_VALUE when we are done, since we are only
5414 going to test the sign bit. */
5415 if (new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
5416 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5417 && ((STORE_FLAG_VALUE & GET_MODE_MASK (mode))
5418 == (unsigned HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (mode) - 1))
5419 && op1 == const0_rtx
5420 && mode == GET_MODE (op0)
5421 && (i = exact_log2 (nonzero_bits (op0, mode))) >= 0)
5423 x = simplify_shift_const (NULL_RTX, ASHIFT, mode,
5424 expand_compound_operation (op0),
5425 GET_MODE_BITSIZE (mode) - 1 - i);
5426 if (GET_CODE (x) == AND && XEXP (x, 1) == const_true_rtx)
5432 /* If the code changed, return a whole new comparison. */
5433 if (new_code != code)
5434 return gen_rtx_fmt_ee (new_code, mode, op0, op1);
5436 /* Otherwise, keep this operation, but maybe change its operands.
5437 This also converts (ne (compare FOO BAR) 0) to (ne FOO BAR). */
5438 SUBST (XEXP (x, 0), op0);
5439 SUBST (XEXP (x, 1), op1);
5444 return simplify_if_then_else (x);
5450 /* If we are processing SET_DEST, we are done. */
5454 return expand_compound_operation (x);
5457 return simplify_set (x);
5461 return simplify_logical (x);
5468 /* If this is a shift by a constant amount, simplify it. */
5469 if (CONST_INT_P (XEXP (x, 1)))
5470 return simplify_shift_const (x, code, mode, XEXP (x, 0),
5471 INTVAL (XEXP (x, 1)));
5473 else if (SHIFT_COUNT_TRUNCATED && !REG_P (XEXP (x, 1)))
5475 force_to_mode (XEXP (x, 1), GET_MODE (XEXP (x, 1)),
5477 << exact_log2 (GET_MODE_BITSIZE (GET_MODE (x))))
5489 /* Simplify X, an IF_THEN_ELSE expression. Return the new expression. */
5492 simplify_if_then_else (rtx x)
5494 enum machine_mode mode = GET_MODE (x);
5495 rtx cond = XEXP (x, 0);
5496 rtx true_rtx = XEXP (x, 1);
5497 rtx false_rtx = XEXP (x, 2);
5498 enum rtx_code true_code = GET_CODE (cond);
5499 int comparison_p = COMPARISON_P (cond);
5502 enum rtx_code false_code;
5505 /* Simplify storing of the truth value. */
5506 if (comparison_p && true_rtx == const_true_rtx && false_rtx == const0_rtx)
5507 return simplify_gen_relational (true_code, mode, VOIDmode,
5508 XEXP (cond, 0), XEXP (cond, 1));
5510 /* Also when the truth value has to be reversed. */
5512 && true_rtx == const0_rtx && false_rtx == const_true_rtx
5513 && (reversed = reversed_comparison (cond, mode)))
5516 /* Sometimes we can simplify the arm of an IF_THEN_ELSE if a register used
5517 in it is being compared against certain values. Get the true and false
5518 comparisons and see if that says anything about the value of each arm. */
5521 && ((false_code = reversed_comparison_code (cond, NULL))
5523 && REG_P (XEXP (cond, 0)))
5526 rtx from = XEXP (cond, 0);
5527 rtx true_val = XEXP (cond, 1);
5528 rtx false_val = true_val;
5531 /* If FALSE_CODE is EQ, swap the codes and arms. */
5533 if (false_code == EQ)
5535 swapped = 1, true_code = EQ, false_code = NE;
5536 temp = true_rtx, true_rtx = false_rtx, false_rtx = temp;
5539 /* If we are comparing against zero and the expression being tested has
5540 only a single bit that might be nonzero, that is its value when it is
5541 not equal to zero. Similarly if it is known to be -1 or 0. */
5543 if (true_code == EQ && true_val == const0_rtx
5544 && exact_log2 (nzb = nonzero_bits (from, GET_MODE (from))) >= 0)
5547 false_val = GEN_INT (trunc_int_for_mode (nzb, GET_MODE (from)));
5549 else if (true_code == EQ && true_val == const0_rtx
5550 && (num_sign_bit_copies (from, GET_MODE (from))
5551 == GET_MODE_BITSIZE (GET_MODE (from))))
5554 false_val = constm1_rtx;
5557 /* Now simplify an arm if we know the value of the register in the
5558 branch and it is used in the arm. Be careful due to the potential
5559 of locally-shared RTL. */
5561 if (reg_mentioned_p (from, true_rtx))
5562 true_rtx = subst (known_cond (copy_rtx (true_rtx), true_code,
5564 pc_rtx, pc_rtx, 0, 0);
5565 if (reg_mentioned_p (from, false_rtx))
5566 false_rtx = subst (known_cond (copy_rtx (false_rtx), false_code,
5568 pc_rtx, pc_rtx, 0, 0);
5570 SUBST (XEXP (x, 1), swapped ? false_rtx : true_rtx);
5571 SUBST (XEXP (x, 2), swapped ? true_rtx : false_rtx);
5573 true_rtx = XEXP (x, 1);
5574 false_rtx = XEXP (x, 2);
5575 true_code = GET_CODE (cond);
5578 /* If we have (if_then_else FOO (pc) (label_ref BAR)) and FOO can be
5579 reversed, do so to avoid needing two sets of patterns for
5580 subtract-and-branch insns. Similarly if we have a constant in the true
5581 arm, the false arm is the same as the first operand of the comparison, or
5582 the false arm is more complicated than the true arm. */
5585 && reversed_comparison_code (cond, NULL) != UNKNOWN
5586 && (true_rtx == pc_rtx
5587 || (CONSTANT_P (true_rtx)
5588 && !CONST_INT_P (false_rtx) && false_rtx != pc_rtx)
5589 || true_rtx == const0_rtx
5590 || (OBJECT_P (true_rtx) && !OBJECT_P (false_rtx))
5591 || (GET_CODE (true_rtx) == SUBREG && OBJECT_P (SUBREG_REG (true_rtx))
5592 && !OBJECT_P (false_rtx))
5593 || reg_mentioned_p (true_rtx, false_rtx)
5594 || rtx_equal_p (false_rtx, XEXP (cond, 0))))
5596 true_code = reversed_comparison_code (cond, NULL);
5597 SUBST (XEXP (x, 0), reversed_comparison (cond, GET_MODE (cond)));
5598 SUBST (XEXP (x, 1), false_rtx);
5599 SUBST (XEXP (x, 2), true_rtx);
5601 temp = true_rtx, true_rtx = false_rtx, false_rtx = temp;
5604 /* It is possible that the conditional has been simplified out. */
5605 true_code = GET_CODE (cond);
5606 comparison_p = COMPARISON_P (cond);
5609 /* If the two arms are identical, we don't need the comparison. */
5611 if (rtx_equal_p (true_rtx, false_rtx) && ! side_effects_p (cond))
5614 /* Convert a == b ? b : a to "a". */
5615 if (true_code == EQ && ! side_effects_p (cond)
5616 && !HONOR_NANS (mode)
5617 && rtx_equal_p (XEXP (cond, 0), false_rtx)
5618 && rtx_equal_p (XEXP (cond, 1), true_rtx))
5620 else if (true_code == NE && ! side_effects_p (cond)
5621 && !HONOR_NANS (mode)
5622 && rtx_equal_p (XEXP (cond, 0), true_rtx)
5623 && rtx_equal_p (XEXP (cond, 1), false_rtx))
5626 /* Look for cases where we have (abs x) or (neg (abs X)). */
5628 if (GET_MODE_CLASS (mode) == MODE_INT
5630 && XEXP (cond, 1) == const0_rtx
5631 && GET_CODE (false_rtx) == NEG
5632 && rtx_equal_p (true_rtx, XEXP (false_rtx, 0))
5633 && rtx_equal_p (true_rtx, XEXP (cond, 0))
5634 && ! side_effects_p (true_rtx))
5639 return simplify_gen_unary (ABS, mode, true_rtx, mode);
5643 simplify_gen_unary (NEG, mode,
5644 simplify_gen_unary (ABS, mode, true_rtx, mode),
5650 /* Look for MIN or MAX. */
5652 if ((! FLOAT_MODE_P (mode) || flag_unsafe_math_optimizations)
5654 && rtx_equal_p (XEXP (cond, 0), true_rtx)
5655 && rtx_equal_p (XEXP (cond, 1), false_rtx)
5656 && ! side_effects_p (cond))
5661 return simplify_gen_binary (SMAX, mode, true_rtx, false_rtx);
5664 return simplify_gen_binary (SMIN, mode, true_rtx, false_rtx);
5667 return simplify_gen_binary (UMAX, mode, true_rtx, false_rtx);
5670 return simplify_gen_binary (UMIN, mode, true_rtx, false_rtx);
5675 /* If we have (if_then_else COND (OP Z C1) Z) and OP is an identity when its
5676 second operand is zero, this can be done as (OP Z (mult COND C2)) where
5677 C2 = C1 * STORE_FLAG_VALUE. Similarly if OP has an outer ZERO_EXTEND or
5678 SIGN_EXTEND as long as Z is already extended (so we don't destroy it).
5679 We can do this kind of thing in some cases when STORE_FLAG_VALUE is
5680 neither 1 or -1, but it isn't worth checking for. */
5682 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
5684 && GET_MODE_CLASS (mode) == MODE_INT
5685 && ! side_effects_p (x))
5687 rtx t = make_compound_operation (true_rtx, SET);
5688 rtx f = make_compound_operation (false_rtx, SET);
5689 rtx cond_op0 = XEXP (cond, 0);
5690 rtx cond_op1 = XEXP (cond, 1);
5691 enum rtx_code op = UNKNOWN, extend_op = UNKNOWN;
5692 enum machine_mode m = mode;
5693 rtx z = 0, c1 = NULL_RTX;
5695 if ((GET_CODE (t) == PLUS || GET_CODE (t) == MINUS
5696 || GET_CODE (t) == IOR || GET_CODE (t) == XOR
5697 || GET_CODE (t) == ASHIFT
5698 || GET_CODE (t) == LSHIFTRT || GET_CODE (t) == ASHIFTRT)
5699 && rtx_equal_p (XEXP (t, 0), f))
5700 c1 = XEXP (t, 1), op = GET_CODE (t), z = f;
5702 /* If an identity-zero op is commutative, check whether there
5703 would be a match if we swapped the operands. */
5704 else if ((GET_CODE (t) == PLUS || GET_CODE (t) == IOR
5705 || GET_CODE (t) == XOR)
5706 && rtx_equal_p (XEXP (t, 1), f))
5707 c1 = XEXP (t, 0), op = GET_CODE (t), z = f;
5708 else if (GET_CODE (t) == SIGN_EXTEND
5709 && (GET_CODE (XEXP (t, 0)) == PLUS
5710 || GET_CODE (XEXP (t, 0)) == MINUS
5711 || GET_CODE (XEXP (t, 0)) == IOR
5712 || GET_CODE (XEXP (t, 0)) == XOR
5713 || GET_CODE (XEXP (t, 0)) == ASHIFT
5714 || GET_CODE (XEXP (t, 0)) == LSHIFTRT
5715 || GET_CODE (XEXP (t, 0)) == ASHIFTRT)
5716 && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG
5717 && subreg_lowpart_p (XEXP (XEXP (t, 0), 0))
5718 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f)
5719 && (num_sign_bit_copies (f, GET_MODE (f))
5721 (GET_MODE_BITSIZE (mode)
5722 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t, 0), 0))))))
5724 c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0));
5725 extend_op = SIGN_EXTEND;
5726 m = GET_MODE (XEXP (t, 0));
5728 else if (GET_CODE (t) == SIGN_EXTEND
5729 && (GET_CODE (XEXP (t, 0)) == PLUS
5730 || GET_CODE (XEXP (t, 0)) == IOR
5731 || GET_CODE (XEXP (t, 0)) == XOR)
5732 && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG
5733 && subreg_lowpart_p (XEXP (XEXP (t, 0), 1))
5734 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f)
5735 && (num_sign_bit_copies (f, GET_MODE (f))
5737 (GET_MODE_BITSIZE (mode)
5738 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t, 0), 1))))))
5740 c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0));
5741 extend_op = SIGN_EXTEND;
5742 m = GET_MODE (XEXP (t, 0));
5744 else if (GET_CODE (t) == ZERO_EXTEND
5745 && (GET_CODE (XEXP (t, 0)) == PLUS
5746 || GET_CODE (XEXP (t, 0)) == MINUS
5747 || GET_CODE (XEXP (t, 0)) == IOR
5748 || GET_CODE (XEXP (t, 0)) == XOR
5749 || GET_CODE (XEXP (t, 0)) == ASHIFT
5750 || GET_CODE (XEXP (t, 0)) == LSHIFTRT
5751 || GET_CODE (XEXP (t, 0)) == ASHIFTRT)
5752 && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG
5753 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5754 && subreg_lowpart_p (XEXP (XEXP (t, 0), 0))
5755 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f)
5756 && ((nonzero_bits (f, GET_MODE (f))
5757 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t, 0), 0))))
5760 c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0));
5761 extend_op = ZERO_EXTEND;
5762 m = GET_MODE (XEXP (t, 0));
5764 else if (GET_CODE (t) == ZERO_EXTEND
5765 && (GET_CODE (XEXP (t, 0)) == PLUS
5766 || GET_CODE (XEXP (t, 0)) == IOR
5767 || GET_CODE (XEXP (t, 0)) == XOR)
5768 && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG
5769 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5770 && subreg_lowpart_p (XEXP (XEXP (t, 0), 1))
5771 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f)
5772 && ((nonzero_bits (f, GET_MODE (f))
5773 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t, 0), 1))))
5776 c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0));
5777 extend_op = ZERO_EXTEND;
5778 m = GET_MODE (XEXP (t, 0));
5783 temp = subst (simplify_gen_relational (true_code, m, VOIDmode,
5784 cond_op0, cond_op1),
5785 pc_rtx, pc_rtx, 0, 0);
5786 temp = simplify_gen_binary (MULT, m, temp,
5787 simplify_gen_binary (MULT, m, c1,
5789 temp = subst (temp, pc_rtx, pc_rtx, 0, 0);
5790 temp = simplify_gen_binary (op, m, gen_lowpart (m, z), temp);
5792 if (extend_op != UNKNOWN)
5793 temp = simplify_gen_unary (extend_op, mode, temp, m);
5799 /* If we have (if_then_else (ne A 0) C1 0) and either A is known to be 0 or
5800 1 and C1 is a single bit or A is known to be 0 or -1 and C1 is the
5801 negation of a single bit, we can convert this operation to a shift. We
5802 can actually do this more generally, but it doesn't seem worth it. */
5804 if (true_code == NE && XEXP (cond, 1) == const0_rtx
5805 && false_rtx == const0_rtx && CONST_INT_P (true_rtx)
5806 && ((1 == nonzero_bits (XEXP (cond, 0), mode)
5807 && (i = exact_log2 (INTVAL (true_rtx))) >= 0)
5808 || ((num_sign_bit_copies (XEXP (cond, 0), mode)
5809 == GET_MODE_BITSIZE (mode))
5810 && (i = exact_log2 (-INTVAL (true_rtx))) >= 0)))
5812 simplify_shift_const (NULL_RTX, ASHIFT, mode,
5813 gen_lowpart (mode, XEXP (cond, 0)), i);
5815 /* (IF_THEN_ELSE (NE REG 0) (0) (8)) is REG for nonzero_bits (REG) == 8. */
5816 if (true_code == NE && XEXP (cond, 1) == const0_rtx
5817 && false_rtx == const0_rtx && CONST_INT_P (true_rtx)
5818 && GET_MODE (XEXP (cond, 0)) == mode
5819 && (INTVAL (true_rtx) & GET_MODE_MASK (mode))
5820 == nonzero_bits (XEXP (cond, 0), mode)
5821 && (i = exact_log2 (INTVAL (true_rtx) & GET_MODE_MASK (mode))) >= 0)
5822 return XEXP (cond, 0);
5827 /* Simplify X, a SET expression. Return the new expression. */
5830 simplify_set (rtx x)
5832 rtx src = SET_SRC (x);
5833 rtx dest = SET_DEST (x);
5834 enum machine_mode mode
5835 = GET_MODE (src) != VOIDmode ? GET_MODE (src) : GET_MODE (dest);
5839 /* (set (pc) (return)) gets written as (return). */
5840 if (GET_CODE (dest) == PC && GET_CODE (src) == RETURN)
5843 /* Now that we know for sure which bits of SRC we are using, see if we can
5844 simplify the expression for the object knowing that we only need the
5847 if (GET_MODE_CLASS (mode) == MODE_INT
5848 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
5850 src = force_to_mode (src, mode, ~(HOST_WIDE_INT) 0, 0);
5851 SUBST (SET_SRC (x), src);
5854 /* If we are setting CC0 or if the source is a COMPARE, look for the use of
5855 the comparison result and try to simplify it unless we already have used
5856 undobuf.other_insn. */
5857 if ((GET_MODE_CLASS (mode) == MODE_CC
5858 || GET_CODE (src) == COMPARE
5860 && (cc_use = find_single_use (dest, subst_insn, &other_insn)) != 0
5861 && (undobuf.other_insn == 0 || other_insn == undobuf.other_insn)
5862 && COMPARISON_P (*cc_use)
5863 && rtx_equal_p (XEXP (*cc_use, 0), dest))
5865 enum rtx_code old_code = GET_CODE (*cc_use);
5866 enum rtx_code new_code;
5868 int other_changed = 0;
5869 enum machine_mode compare_mode = GET_MODE (dest);
5871 if (GET_CODE (src) == COMPARE)
5872 op0 = XEXP (src, 0), op1 = XEXP (src, 1);
5874 op0 = src, op1 = CONST0_RTX (GET_MODE (src));
5876 tmp = simplify_relational_operation (old_code, compare_mode, VOIDmode,
5879 new_code = old_code;
5880 else if (!CONSTANT_P (tmp))
5882 new_code = GET_CODE (tmp);
5883 op0 = XEXP (tmp, 0);
5884 op1 = XEXP (tmp, 1);
5888 rtx pat = PATTERN (other_insn);
5889 undobuf.other_insn = other_insn;
5890 SUBST (*cc_use, tmp);
5892 /* Attempt to simplify CC user. */
5893 if (GET_CODE (pat) == SET)
5895 rtx new_rtx = simplify_rtx (SET_SRC (pat));
5896 if (new_rtx != NULL_RTX)
5897 SUBST (SET_SRC (pat), new_rtx);
5900 /* Convert X into a no-op move. */
5901 SUBST (SET_DEST (x), pc_rtx);
5902 SUBST (SET_SRC (x), pc_rtx);
5906 /* Simplify our comparison, if possible. */
5907 new_code = simplify_comparison (new_code, &op0, &op1);
5909 #ifdef SELECT_CC_MODE
5910 /* If this machine has CC modes other than CCmode, check to see if we
5911 need to use a different CC mode here. */
5912 if (GET_MODE_CLASS (GET_MODE (op0)) == MODE_CC)
5913 compare_mode = GET_MODE (op0);
5915 compare_mode = SELECT_CC_MODE (new_code, op0, op1);
5918 /* If the mode changed, we have to change SET_DEST, the mode in the
5919 compare, and the mode in the place SET_DEST is used. If SET_DEST is
5920 a hard register, just build new versions with the proper mode. If it
5921 is a pseudo, we lose unless it is only time we set the pseudo, in
5922 which case we can safely change its mode. */
5923 if (compare_mode != GET_MODE (dest))
5925 if (can_change_dest_mode (dest, 0, compare_mode))
5927 unsigned int regno = REGNO (dest);
5930 if (regno < FIRST_PSEUDO_REGISTER)
5931 new_dest = gen_rtx_REG (compare_mode, regno);
5934 SUBST_MODE (regno_reg_rtx[regno], compare_mode);
5935 new_dest = regno_reg_rtx[regno];
5938 SUBST (SET_DEST (x), new_dest);
5939 SUBST (XEXP (*cc_use, 0), new_dest);
5946 #endif /* SELECT_CC_MODE */
5948 /* If the code changed, we have to build a new comparison in
5949 undobuf.other_insn. */
5950 if (new_code != old_code)
5952 int other_changed_previously = other_changed;
5953 unsigned HOST_WIDE_INT mask;
5954 rtx old_cc_use = *cc_use;
5956 SUBST (*cc_use, gen_rtx_fmt_ee (new_code, GET_MODE (*cc_use),
5960 /* If the only change we made was to change an EQ into an NE or
5961 vice versa, OP0 has only one bit that might be nonzero, and OP1
5962 is zero, check if changing the user of the condition code will
5963 produce a valid insn. If it won't, we can keep the original code
5964 in that insn by surrounding our operation with an XOR. */
5966 if (((old_code == NE && new_code == EQ)
5967 || (old_code == EQ && new_code == NE))
5968 && ! other_changed_previously && op1 == const0_rtx
5969 && GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
5970 && exact_log2 (mask = nonzero_bits (op0, GET_MODE (op0))) >= 0)
5972 rtx pat = PATTERN (other_insn), note = 0;
5974 if ((recog_for_combine (&pat, other_insn, ¬e) < 0
5975 && ! check_asm_operands (pat)))
5977 *cc_use = old_cc_use;
5980 op0 = simplify_gen_binary (XOR, GET_MODE (op0),
5981 op0, GEN_INT (mask));
5987 undobuf.other_insn = other_insn;
5989 /* Otherwise, if we didn't previously have a COMPARE in the
5990 correct mode, we need one. */
5991 if (GET_CODE (src) != COMPARE || GET_MODE (src) != compare_mode)
5993 SUBST (SET_SRC (x), gen_rtx_COMPARE (compare_mode, op0, op1));
5996 else if (GET_MODE (op0) == compare_mode && op1 == const0_rtx)
5998 SUBST (SET_SRC (x), op0);
6001 /* Otherwise, update the COMPARE if needed. */
6002 else if (XEXP (src, 0) != op0 || XEXP (src, 1) != op1)
6004 SUBST (SET_SRC (x), gen_rtx_COMPARE (compare_mode, op0, op1));
6010 /* Get SET_SRC in a form where we have placed back any
6011 compound expressions. Then do the checks below. */
6012 src = make_compound_operation (src, SET);
6013 SUBST (SET_SRC (x), src);
6016 /* If we have (set x (subreg:m1 (op:m2 ...) 0)) with OP being some operation,
6017 and X being a REG or (subreg (reg)), we may be able to convert this to
6018 (set (subreg:m2 x) (op)).
6020 We can always do this if M1 is narrower than M2 because that means that
6021 we only care about the low bits of the result.
6023 However, on machines without WORD_REGISTER_OPERATIONS defined, we cannot
6024 perform a narrower operation than requested since the high-order bits will
6025 be undefined. On machine where it is defined, this transformation is safe
6026 as long as M1 and M2 have the same number of words. */
6028 if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src)
6029 && !OBJECT_P (SUBREG_REG (src))
6030 && (((GET_MODE_SIZE (GET_MODE (src)) + (UNITS_PER_WORD - 1))
6032 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (src)))
6033 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD))
6034 #ifndef WORD_REGISTER_OPERATIONS
6035 && (GET_MODE_SIZE (GET_MODE (src))
6036 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (src))))
6038 #ifdef CANNOT_CHANGE_MODE_CLASS
6039 && ! (REG_P (dest) && REGNO (dest) < FIRST_PSEUDO_REGISTER
6040 && REG_CANNOT_CHANGE_MODE_P (REGNO (dest),
6041 GET_MODE (SUBREG_REG (src)),
6045 || (GET_CODE (dest) == SUBREG
6046 && REG_P (SUBREG_REG (dest)))))
6048 SUBST (SET_DEST (x),
6049 gen_lowpart (GET_MODE (SUBREG_REG (src)),
6051 SUBST (SET_SRC (x), SUBREG_REG (src));
6053 src = SET_SRC (x), dest = SET_DEST (x);
6057 /* If we have (set (cc0) (subreg ...)), we try to remove the subreg
6060 && GET_CODE (src) == SUBREG
6061 && subreg_lowpart_p (src)
6062 && (GET_MODE_BITSIZE (GET_MODE (src))
6063 < GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (src)))))
6065 rtx inner = SUBREG_REG (src);
6066 enum machine_mode inner_mode = GET_MODE (inner);
6068 /* Here we make sure that we don't have a sign bit on. */
6069 if (GET_MODE_BITSIZE (inner_mode) <= HOST_BITS_PER_WIDE_INT
6070 && (nonzero_bits (inner, inner_mode)
6071 < ((unsigned HOST_WIDE_INT) 1
6072 << (GET_MODE_BITSIZE (GET_MODE (src)) - 1))))
6074 SUBST (SET_SRC (x), inner);
6080 #ifdef LOAD_EXTEND_OP
6081 /* If we have (set FOO (subreg:M (mem:N BAR) 0)) with M wider than N, this
6082 would require a paradoxical subreg. Replace the subreg with a
6083 zero_extend to avoid the reload that would otherwise be required. */
6085 if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src)
6086 && INTEGRAL_MODE_P (GET_MODE (SUBREG_REG (src)))
6087 && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src))) != UNKNOWN
6088 && SUBREG_BYTE (src) == 0
6089 && (GET_MODE_SIZE (GET_MODE (src))
6090 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (src))))
6091 && MEM_P (SUBREG_REG (src)))
6094 gen_rtx_fmt_e (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src))),
6095 GET_MODE (src), SUBREG_REG (src)));
6101 /* If we don't have a conditional move, SET_SRC is an IF_THEN_ELSE, and we
6102 are comparing an item known to be 0 or -1 against 0, use a logical
6103 operation instead. Check for one of the arms being an IOR of the other
6104 arm with some value. We compute three terms to be IOR'ed together. In
6105 practice, at most two will be nonzero. Then we do the IOR's. */
6107 if (GET_CODE (dest) != PC
6108 && GET_CODE (src) == IF_THEN_ELSE
6109 && GET_MODE_CLASS (GET_MODE (src)) == MODE_INT
6110 && (GET_CODE (XEXP (src, 0)) == EQ || GET_CODE (XEXP (src, 0)) == NE)
6111 && XEXP (XEXP (src, 0), 1) == const0_rtx
6112 && GET_MODE (src) == GET_MODE (XEXP (XEXP (src, 0), 0))
6113 #ifdef HAVE_conditional_move
6114 && ! can_conditionally_move_p (GET_MODE (src))
6116 && (num_sign_bit_copies (XEXP (XEXP (src, 0), 0),
6117 GET_MODE (XEXP (XEXP (src, 0), 0)))
6118 == GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (src, 0), 0))))
6119 && ! side_effects_p (src))
6121 rtx true_rtx = (GET_CODE (XEXP (src, 0)) == NE
6122 ? XEXP (src, 1) : XEXP (src, 2));
6123 rtx false_rtx = (GET_CODE (XEXP (src, 0)) == NE
6124 ? XEXP (src, 2) : XEXP (src, 1));
6125 rtx term1 = const0_rtx, term2, term3;
6127 if (GET_CODE (true_rtx) == IOR
6128 && rtx_equal_p (XEXP (true_rtx, 0), false_rtx))
6129 term1 = false_rtx, true_rtx = XEXP (true_rtx, 1), false_rtx = const0_rtx;
6130 else if (GET_CODE (true_rtx) == IOR
6131 && rtx_equal_p (XEXP (true_rtx, 1), false_rtx))
6132 term1 = false_rtx, true_rtx = XEXP (true_rtx, 0), false_rtx = const0_rtx;
6133 else if (GET_CODE (false_rtx) == IOR
6134 && rtx_equal_p (XEXP (false_rtx, 0), true_rtx))
6135 term1 = true_rtx, false_rtx = XEXP (false_rtx, 1), true_rtx = const0_rtx;
6136 else if (GET_CODE (false_rtx) == IOR
6137 && rtx_equal_p (XEXP (false_rtx, 1), true_rtx))
6138 term1 = true_rtx, false_rtx = XEXP (false_rtx, 0), true_rtx = const0_rtx;
6140 term2 = simplify_gen_binary (AND, GET_MODE (src),
6141 XEXP (XEXP (src, 0), 0), true_rtx);
6142 term3 = simplify_gen_binary (AND, GET_MODE (src),
6143 simplify_gen_unary (NOT, GET_MODE (src),
6144 XEXP (XEXP (src, 0), 0),
6149 simplify_gen_binary (IOR, GET_MODE (src),
6150 simplify_gen_binary (IOR, GET_MODE (src),
6157 /* If either SRC or DEST is a CLOBBER of (const_int 0), make this
6158 whole thing fail. */
6159 if (GET_CODE (src) == CLOBBER && XEXP (src, 0) == const0_rtx)
6161 else if (GET_CODE (dest) == CLOBBER && XEXP (dest, 0) == const0_rtx)
6164 /* Convert this into a field assignment operation, if possible. */
6165 return make_field_assignment (x);
6168 /* Simplify, X, and AND, IOR, or XOR operation, and return the simplified
6172 simplify_logical (rtx x)
6174 enum machine_mode mode = GET_MODE (x);
6175 rtx op0 = XEXP (x, 0);
6176 rtx op1 = XEXP (x, 1);
6178 switch (GET_CODE (x))
6181 /* We can call simplify_and_const_int only if we don't lose
6182 any (sign) bits when converting INTVAL (op1) to
6183 "unsigned HOST_WIDE_INT". */
6184 if (CONST_INT_P (op1)
6185 && (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
6186 || INTVAL (op1) > 0))
6188 x = simplify_and_const_int (x, mode, op0, INTVAL (op1));
6189 if (GET_CODE (x) != AND)
6196 /* If we have any of (and (ior A B) C) or (and (xor A B) C),
6197 apply the distributive law and then the inverse distributive
6198 law to see if things simplify. */
6199 if (GET_CODE (op0) == IOR || GET_CODE (op0) == XOR)
6201 rtx result = distribute_and_simplify_rtx (x, 0);
6205 if (GET_CODE (op1) == IOR || GET_CODE (op1) == XOR)
6207 rtx result = distribute_and_simplify_rtx (x, 1);
6214 /* If we have (ior (and A B) C), apply the distributive law and then
6215 the inverse distributive law to see if things simplify. */
6217 if (GET_CODE (op0) == AND)
6219 rtx result = distribute_and_simplify_rtx (x, 0);
6224 if (GET_CODE (op1) == AND)
6226 rtx result = distribute_and_simplify_rtx (x, 1);
6239 /* We consider ZERO_EXTRACT, SIGN_EXTRACT, and SIGN_EXTEND as "compound
6240 operations" because they can be replaced with two more basic operations.
6241 ZERO_EXTEND is also considered "compound" because it can be replaced with
6242 an AND operation, which is simpler, though only one operation.
6244 The function expand_compound_operation is called with an rtx expression
6245 and will convert it to the appropriate shifts and AND operations,
6246 simplifying at each stage.
6248 The function make_compound_operation is called to convert an expression
6249 consisting of shifts and ANDs into the equivalent compound expression.
6250 It is the inverse of this function, loosely speaking. */
6253 expand_compound_operation (rtx x)
6255 unsigned HOST_WIDE_INT pos = 0, len;
6257 unsigned int modewidth;
6260 switch (GET_CODE (x))
6265 /* We can't necessarily use a const_int for a multiword mode;
6266 it depends on implicitly extending the value.
6267 Since we don't know the right way to extend it,
6268 we can't tell whether the implicit way is right.
6270 Even for a mode that is no wider than a const_int,
6271 we can't win, because we need to sign extend one of its bits through
6272 the rest of it, and we don't know which bit. */
6273 if (CONST_INT_P (XEXP (x, 0)))
6276 /* Return if (subreg:MODE FROM 0) is not a safe replacement for
6277 (zero_extend:MODE FROM) or (sign_extend:MODE FROM). It is for any MEM
6278 because (SUBREG (MEM...)) is guaranteed to cause the MEM to be
6279 reloaded. If not for that, MEM's would very rarely be safe.
6281 Reject MODEs bigger than a word, because we might not be able
6282 to reference a two-register group starting with an arbitrary register
6283 (and currently gen_lowpart might crash for a SUBREG). */
6285 if (GET_MODE_SIZE (GET_MODE (XEXP (x, 0))) > UNITS_PER_WORD)
6288 /* Reject MODEs that aren't scalar integers because turning vector
6289 or complex modes into shifts causes problems. */
6291 if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x, 0))))
6294 len = GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)));
6295 /* If the inner object has VOIDmode (the only way this can happen
6296 is if it is an ASM_OPERANDS), we can't do anything since we don't
6297 know how much masking to do. */
6306 /* ... fall through ... */
6309 /* If the operand is a CLOBBER, just return it. */
6310 if (GET_CODE (XEXP (x, 0)) == CLOBBER)
6313 if (!CONST_INT_P (XEXP (x, 1))
6314 || !CONST_INT_P (XEXP (x, 2))
6315 || GET_MODE (XEXP (x, 0)) == VOIDmode)
6318 /* Reject MODEs that aren't scalar integers because turning vector
6319 or complex modes into shifts causes problems. */
6321 if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x, 0))))
6324 len = INTVAL (XEXP (x, 1));
6325 pos = INTVAL (XEXP (x, 2));
6327 /* This should stay within the object being extracted, fail otherwise. */
6328 if (len + pos > GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))))
6331 if (BITS_BIG_ENDIAN)
6332 pos = GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - len - pos;
6339 /* Convert sign extension to zero extension, if we know that the high
6340 bit is not set, as this is easier to optimize. It will be converted
6341 back to cheaper alternative in make_extraction. */
6342 if (GET_CODE (x) == SIGN_EXTEND
6343 && (GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
6344 && ((nonzero_bits (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
6345 & ~(((unsigned HOST_WIDE_INT)
6346 GET_MODE_MASK (GET_MODE (XEXP (x, 0))))
6350 rtx temp = gen_rtx_ZERO_EXTEND (GET_MODE (x), XEXP (x, 0));
6351 rtx temp2 = expand_compound_operation (temp);
6353 /* Make sure this is a profitable operation. */
6354 if (rtx_cost (x, SET, optimize_this_for_speed_p)
6355 > rtx_cost (temp2, SET, optimize_this_for_speed_p))
6357 else if (rtx_cost (x, SET, optimize_this_for_speed_p)
6358 > rtx_cost (temp, SET, optimize_this_for_speed_p))
6364 /* We can optimize some special cases of ZERO_EXTEND. */
6365 if (GET_CODE (x) == ZERO_EXTEND)
6367 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI if we
6368 know that the last value didn't have any inappropriate bits
6370 if (GET_CODE (XEXP (x, 0)) == TRUNCATE
6371 && GET_MODE (XEXP (XEXP (x, 0), 0)) == GET_MODE (x)
6372 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
6373 && (nonzero_bits (XEXP (XEXP (x, 0), 0), GET_MODE (x))
6374 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
6375 return XEXP (XEXP (x, 0), 0);
6377 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
6378 if (GET_CODE (XEXP (x, 0)) == SUBREG
6379 && GET_MODE (SUBREG_REG (XEXP (x, 0))) == GET_MODE (x)
6380 && subreg_lowpart_p (XEXP (x, 0))
6381 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
6382 && (nonzero_bits (SUBREG_REG (XEXP (x, 0)), GET_MODE (x))
6383 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
6384 return SUBREG_REG (XEXP (x, 0));
6386 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI when foo
6387 is a comparison and STORE_FLAG_VALUE permits. This is like
6388 the first case, but it works even when GET_MODE (x) is larger
6389 than HOST_WIDE_INT. */
6390 if (GET_CODE (XEXP (x, 0)) == TRUNCATE
6391 && GET_MODE (XEXP (XEXP (x, 0), 0)) == GET_MODE (x)
6392 && COMPARISON_P (XEXP (XEXP (x, 0), 0))
6393 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
6394 <= HOST_BITS_PER_WIDE_INT)
6395 && ((HOST_WIDE_INT) STORE_FLAG_VALUE
6396 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
6397 return XEXP (XEXP (x, 0), 0);
6399 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
6400 if (GET_CODE (XEXP (x, 0)) == SUBREG
6401 && GET_MODE (SUBREG_REG (XEXP (x, 0))) == GET_MODE (x)
6402 && subreg_lowpart_p (XEXP (x, 0))
6403 && COMPARISON_P (SUBREG_REG (XEXP (x, 0)))
6404 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
6405 <= HOST_BITS_PER_WIDE_INT)
6406 && ((HOST_WIDE_INT) STORE_FLAG_VALUE
6407 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
6408 return SUBREG_REG (XEXP (x, 0));
6412 /* If we reach here, we want to return a pair of shifts. The inner
6413 shift is a left shift of BITSIZE - POS - LEN bits. The outer
6414 shift is a right shift of BITSIZE - LEN bits. It is arithmetic or
6415 logical depending on the value of UNSIGNEDP.
6417 If this was a ZERO_EXTEND or ZERO_EXTRACT, this pair of shifts will be
6418 converted into an AND of a shift.
6420 We must check for the case where the left shift would have a negative
6421 count. This can happen in a case like (x >> 31) & 255 on machines
6422 that can't shift by a constant. On those machines, we would first
6423 combine the shift with the AND to produce a variable-position
6424 extraction. Then the constant of 31 would be substituted in to produce
6425 a such a position. */
6427 modewidth = GET_MODE_BITSIZE (GET_MODE (x));
6428 if (modewidth + len >= pos)
6430 enum machine_mode mode = GET_MODE (x);
6431 tem = gen_lowpart (mode, XEXP (x, 0));
6432 if (!tem || GET_CODE (tem) == CLOBBER)
6434 tem = simplify_shift_const (NULL_RTX, ASHIFT, mode,
6435 tem, modewidth - pos - len);
6436 tem = simplify_shift_const (NULL_RTX, unsignedp ? LSHIFTRT : ASHIFTRT,
6437 mode, tem, modewidth - len);
6439 else if (unsignedp && len < HOST_BITS_PER_WIDE_INT)
6440 tem = simplify_and_const_int (NULL_RTX, GET_MODE (x),
6441 simplify_shift_const (NULL_RTX, LSHIFTRT,
6444 ((HOST_WIDE_INT) 1 << len) - 1);
6446 /* Any other cases we can't handle. */
6449 /* If we couldn't do this for some reason, return the original
6451 if (GET_CODE (tem) == CLOBBER)
6457 /* X is a SET which contains an assignment of one object into
6458 a part of another (such as a bit-field assignment, STRICT_LOW_PART,
6459 or certain SUBREGS). If possible, convert it into a series of
6462 We half-heartedly support variable positions, but do not at all
6463 support variable lengths. */
6466 expand_field_assignment (const_rtx x)
6469 rtx pos; /* Always counts from low bit. */
6471 rtx mask, cleared, masked;
6472 enum machine_mode compute_mode;
6474 /* Loop until we find something we can't simplify. */
6477 if (GET_CODE (SET_DEST (x)) == STRICT_LOW_PART
6478 && GET_CODE (XEXP (SET_DEST (x), 0)) == SUBREG)
6480 inner = SUBREG_REG (XEXP (SET_DEST (x), 0));
6481 len = GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0)));
6482 pos = GEN_INT (subreg_lsb (XEXP (SET_DEST (x), 0)));
6484 else if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
6485 && CONST_INT_P (XEXP (SET_DEST (x), 1)))
6487 inner = XEXP (SET_DEST (x), 0);
6488 len = INTVAL (XEXP (SET_DEST (x), 1));
6489 pos = XEXP (SET_DEST (x), 2);
6491 /* A constant position should stay within the width of INNER. */
6492 if (CONST_INT_P (pos)
6493 && INTVAL (pos) + len > GET_MODE_BITSIZE (GET_MODE (inner)))
6496 if (BITS_BIG_ENDIAN)
6498 if (CONST_INT_P (pos))
6499 pos = GEN_INT (GET_MODE_BITSIZE (GET_MODE (inner)) - len
6501 else if (GET_CODE (pos) == MINUS
6502 && CONST_INT_P (XEXP (pos, 1))
6503 && (INTVAL (XEXP (pos, 1))
6504 == GET_MODE_BITSIZE (GET_MODE (inner)) - len))
6505 /* If position is ADJUST - X, new position is X. */
6506 pos = XEXP (pos, 0);
6508 pos = simplify_gen_binary (MINUS, GET_MODE (pos),
6509 GEN_INT (GET_MODE_BITSIZE (
6516 /* A SUBREG between two modes that occupy the same numbers of words
6517 can be done by moving the SUBREG to the source. */
6518 else if (GET_CODE (SET_DEST (x)) == SUBREG
6519 /* We need SUBREGs to compute nonzero_bits properly. */
6520 && nonzero_sign_valid
6521 && (((GET_MODE_SIZE (GET_MODE (SET_DEST (x)))
6522 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
6523 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x))))
6524 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)))
6526 x = gen_rtx_SET (VOIDmode, SUBREG_REG (SET_DEST (x)),
6528 (GET_MODE (SUBREG_REG (SET_DEST (x))),
6535 while (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
6536 inner = SUBREG_REG (inner);
6538 compute_mode = GET_MODE (inner);
6540 /* Don't attempt bitwise arithmetic on non scalar integer modes. */
6541 if (! SCALAR_INT_MODE_P (compute_mode))
6543 enum machine_mode imode;
6545 /* Don't do anything for vector or complex integral types. */
6546 if (! FLOAT_MODE_P (compute_mode))
6549 /* Try to find an integral mode to pun with. */
6550 imode = mode_for_size (GET_MODE_BITSIZE (compute_mode), MODE_INT, 0);
6551 if (imode == BLKmode)
6554 compute_mode = imode;
6555 inner = gen_lowpart (imode, inner);
6558 /* Compute a mask of LEN bits, if we can do this on the host machine. */
6559 if (len >= HOST_BITS_PER_WIDE_INT)
6562 /* Now compute the equivalent expression. Make a copy of INNER
6563 for the SET_DEST in case it is a MEM into which we will substitute;
6564 we don't want shared RTL in that case. */
6565 mask = GEN_INT (((HOST_WIDE_INT) 1 << len) - 1);
6566 cleared = simplify_gen_binary (AND, compute_mode,
6567 simplify_gen_unary (NOT, compute_mode,
6568 simplify_gen_binary (ASHIFT,
6573 masked = simplify_gen_binary (ASHIFT, compute_mode,
6574 simplify_gen_binary (
6576 gen_lowpart (compute_mode, SET_SRC (x)),
6580 x = gen_rtx_SET (VOIDmode, copy_rtx (inner),
6581 simplify_gen_binary (IOR, compute_mode,
6588 /* Return an RTX for a reference to LEN bits of INNER. If POS_RTX is nonzero,
6589 it is an RTX that represents a variable starting position; otherwise,
6590 POS is the (constant) starting bit position (counted from the LSB).
6592 UNSIGNEDP is nonzero for an unsigned reference and zero for a
6595 IN_DEST is nonzero if this is a reference in the destination of a
6596 SET. This is used when a ZERO_ or SIGN_EXTRACT isn't needed. If nonzero,
6597 a STRICT_LOW_PART will be used, if zero, ZERO_EXTEND or SIGN_EXTEND will
6600 IN_COMPARE is nonzero if we are in a COMPARE. This means that a
6601 ZERO_EXTRACT should be built even for bits starting at bit 0.
6603 MODE is the desired mode of the result (if IN_DEST == 0).
6605 The result is an RTX for the extraction or NULL_RTX if the target
6609 make_extraction (enum machine_mode mode, rtx inner, HOST_WIDE_INT pos,
6610 rtx pos_rtx, unsigned HOST_WIDE_INT len, int unsignedp,
6611 int in_dest, int in_compare)
6613 /* This mode describes the size of the storage area
6614 to fetch the overall value from. Within that, we
6615 ignore the POS lowest bits, etc. */
6616 enum machine_mode is_mode = GET_MODE (inner);
6617 enum machine_mode inner_mode;
6618 enum machine_mode wanted_inner_mode;
6619 enum machine_mode wanted_inner_reg_mode = word_mode;
6620 enum machine_mode pos_mode = word_mode;
6621 enum machine_mode extraction_mode = word_mode;
6622 enum machine_mode tmode = mode_for_size (len, MODE_INT, 1);
6624 rtx orig_pos_rtx = pos_rtx;
6625 HOST_WIDE_INT orig_pos;
6627 if (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
6629 /* If going from (subreg:SI (mem:QI ...)) to (mem:QI ...),
6630 consider just the QI as the memory to extract from.
6631 The subreg adds or removes high bits; its mode is
6632 irrelevant to the meaning of this extraction,
6633 since POS and LEN count from the lsb. */
6634 if (MEM_P (SUBREG_REG (inner)))
6635 is_mode = GET_MODE (SUBREG_REG (inner));
6636 inner = SUBREG_REG (inner);
6638 else if (GET_CODE (inner) == ASHIFT
6639 && CONST_INT_P (XEXP (inner, 1))
6640 && pos_rtx == 0 && pos == 0
6641 && len > (unsigned HOST_WIDE_INT) INTVAL (XEXP (inner, 1)))
6643 /* We're extracting the least significant bits of an rtx
6644 (ashift X (const_int C)), where LEN > C. Extract the
6645 least significant (LEN - C) bits of X, giving an rtx
6646 whose mode is MODE, then shift it left C times. */
6647 new_rtx = make_extraction (mode, XEXP (inner, 0),
6648 0, 0, len - INTVAL (XEXP (inner, 1)),
6649 unsignedp, in_dest, in_compare);
6651 return gen_rtx_ASHIFT (mode, new_rtx, XEXP (inner, 1));
6654 inner_mode = GET_MODE (inner);
6656 if (pos_rtx && CONST_INT_P (pos_rtx))
6657 pos = INTVAL (pos_rtx), pos_rtx = 0;
6659 /* See if this can be done without an extraction. We never can if the
6660 width of the field is not the same as that of some integer mode. For
6661 registers, we can only avoid the extraction if the position is at the
6662 low-order bit and this is either not in the destination or we have the
6663 appropriate STRICT_LOW_PART operation available.
6665 For MEM, we can avoid an extract if the field starts on an appropriate
6666 boundary and we can change the mode of the memory reference. */
6668 if (tmode != BLKmode
6669 && ((pos_rtx == 0 && (pos % BITS_PER_WORD) == 0
6671 && (inner_mode == tmode
6673 || TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (tmode),
6674 GET_MODE_BITSIZE (inner_mode))
6675 || reg_truncated_to_mode (tmode, inner))
6678 && have_insn_for (STRICT_LOW_PART, tmode))))
6679 || (MEM_P (inner) && pos_rtx == 0
6681 % (STRICT_ALIGNMENT ? GET_MODE_ALIGNMENT (tmode)
6682 : BITS_PER_UNIT)) == 0
6683 /* We can't do this if we are widening INNER_MODE (it
6684 may not be aligned, for one thing). */
6685 && GET_MODE_BITSIZE (inner_mode) >= GET_MODE_BITSIZE (tmode)
6686 && (inner_mode == tmode
6687 || (! mode_dependent_address_p (XEXP (inner, 0))
6688 && ! MEM_VOLATILE_P (inner))))))
6690 /* If INNER is a MEM, make a new MEM that encompasses just the desired
6691 field. If the original and current mode are the same, we need not
6692 adjust the offset. Otherwise, we do if bytes big endian.
6694 If INNER is not a MEM, get a piece consisting of just the field
6695 of interest (in this case POS % BITS_PER_WORD must be 0). */
6699 HOST_WIDE_INT offset;
6701 /* POS counts from lsb, but make OFFSET count in memory order. */
6702 if (BYTES_BIG_ENDIAN)
6703 offset = (GET_MODE_BITSIZE (is_mode) - len - pos) / BITS_PER_UNIT;
6705 offset = pos / BITS_PER_UNIT;
6707 new_rtx = adjust_address_nv (inner, tmode, offset);
6709 else if (REG_P (inner))
6711 if (tmode != inner_mode)
6713 /* We can't call gen_lowpart in a DEST since we
6714 always want a SUBREG (see below) and it would sometimes
6715 return a new hard register. */
6718 HOST_WIDE_INT final_word = pos / BITS_PER_WORD;
6720 if (WORDS_BIG_ENDIAN
6721 && GET_MODE_SIZE (inner_mode) > UNITS_PER_WORD)
6722 final_word = ((GET_MODE_SIZE (inner_mode)
6723 - GET_MODE_SIZE (tmode))
6724 / UNITS_PER_WORD) - final_word;
6726 final_word *= UNITS_PER_WORD;
6727 if (BYTES_BIG_ENDIAN &&
6728 GET_MODE_SIZE (inner_mode) > GET_MODE_SIZE (tmode))
6729 final_word += (GET_MODE_SIZE (inner_mode)
6730 - GET_MODE_SIZE (tmode)) % UNITS_PER_WORD;
6732 /* Avoid creating invalid subregs, for example when
6733 simplifying (x>>32)&255. */
6734 if (!validate_subreg (tmode, inner_mode, inner, final_word))
6737 new_rtx = gen_rtx_SUBREG (tmode, inner, final_word);
6740 new_rtx = gen_lowpart (tmode, inner);
6746 new_rtx = force_to_mode (inner, tmode,
6747 len >= HOST_BITS_PER_WIDE_INT
6748 ? ~(unsigned HOST_WIDE_INT) 0
6749 : ((unsigned HOST_WIDE_INT) 1 << len) - 1,
6752 /* If this extraction is going into the destination of a SET,
6753 make a STRICT_LOW_PART unless we made a MEM. */
6756 return (MEM_P (new_rtx) ? new_rtx
6757 : (GET_CODE (new_rtx) != SUBREG
6758 ? gen_rtx_CLOBBER (tmode, const0_rtx)
6759 : gen_rtx_STRICT_LOW_PART (VOIDmode, new_rtx)));
6764 if (CONST_INT_P (new_rtx)
6765 || GET_CODE (new_rtx) == CONST_DOUBLE)
6766 return simplify_unary_operation (unsignedp ? ZERO_EXTEND : SIGN_EXTEND,
6767 mode, new_rtx, tmode);
6769 /* If we know that no extraneous bits are set, and that the high
6770 bit is not set, convert the extraction to the cheaper of
6771 sign and zero extension, that are equivalent in these cases. */
6772 if (flag_expensive_optimizations
6773 && (GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT
6774 && ((nonzero_bits (new_rtx, tmode)
6775 & ~(((unsigned HOST_WIDE_INT)
6776 GET_MODE_MASK (tmode))
6780 rtx temp = gen_rtx_ZERO_EXTEND (mode, new_rtx);
6781 rtx temp1 = gen_rtx_SIGN_EXTEND (mode, new_rtx);
6783 /* Prefer ZERO_EXTENSION, since it gives more information to
6785 if (rtx_cost (temp, SET, optimize_this_for_speed_p)
6786 <= rtx_cost (temp1, SET, optimize_this_for_speed_p))
6791 /* Otherwise, sign- or zero-extend unless we already are in the
6794 return (gen_rtx_fmt_e (unsignedp ? ZERO_EXTEND : SIGN_EXTEND,
6798 /* Unless this is a COMPARE or we have a funny memory reference,
6799 don't do anything with zero-extending field extracts starting at
6800 the low-order bit since they are simple AND operations. */
6801 if (pos_rtx == 0 && pos == 0 && ! in_dest
6802 && ! in_compare && unsignedp)
6805 /* Unless INNER is not MEM, reject this if we would be spanning bytes or
6806 if the position is not a constant and the length is not 1. In all
6807 other cases, we would only be going outside our object in cases when
6808 an original shift would have been undefined. */
6810 && ((pos_rtx == 0 && pos + len > GET_MODE_BITSIZE (is_mode))
6811 || (pos_rtx != 0 && len != 1)))
6814 /* Get the mode to use should INNER not be a MEM, the mode for the position,
6815 and the mode for the result. */
6816 if (in_dest && mode_for_extraction (EP_insv, -1) != MAX_MACHINE_MODE)
6818 wanted_inner_reg_mode = mode_for_extraction (EP_insv, 0);
6819 pos_mode = mode_for_extraction (EP_insv, 2);
6820 extraction_mode = mode_for_extraction (EP_insv, 3);
6823 if (! in_dest && unsignedp
6824 && mode_for_extraction (EP_extzv, -1) != MAX_MACHINE_MODE)
6826 wanted_inner_reg_mode = mode_for_extraction (EP_extzv, 1);
6827 pos_mode = mode_for_extraction (EP_extzv, 3);
6828 extraction_mode = mode_for_extraction (EP_extzv, 0);
6831 if (! in_dest && ! unsignedp
6832 && mode_for_extraction (EP_extv, -1) != MAX_MACHINE_MODE)
6834 wanted_inner_reg_mode = mode_for_extraction (EP_extv, 1);
6835 pos_mode = mode_for_extraction (EP_extv, 3);
6836 extraction_mode = mode_for_extraction (EP_extv, 0);
6839 /* Never narrow an object, since that might not be safe. */
6841 if (mode != VOIDmode
6842 && GET_MODE_SIZE (extraction_mode) < GET_MODE_SIZE (mode))
6843 extraction_mode = mode;
6845 if (pos_rtx && GET_MODE (pos_rtx) != VOIDmode
6846 && GET_MODE_SIZE (pos_mode) < GET_MODE_SIZE (GET_MODE (pos_rtx)))
6847 pos_mode = GET_MODE (pos_rtx);
6849 /* If this is not from memory, the desired mode is the preferred mode
6850 for an extraction pattern's first input operand, or word_mode if there
6853 wanted_inner_mode = wanted_inner_reg_mode;
6856 /* Be careful not to go beyond the extracted object and maintain the
6857 natural alignment of the memory. */
6858 wanted_inner_mode = smallest_mode_for_size (len, MODE_INT);
6859 while (pos % GET_MODE_BITSIZE (wanted_inner_mode) + len
6860 > GET_MODE_BITSIZE (wanted_inner_mode))
6862 wanted_inner_mode = GET_MODE_WIDER_MODE (wanted_inner_mode);
6863 gcc_assert (wanted_inner_mode != VOIDmode);
6866 /* If we have to change the mode of memory and cannot, the desired mode
6867 is EXTRACTION_MODE. */
6868 if (inner_mode != wanted_inner_mode
6869 && (mode_dependent_address_p (XEXP (inner, 0))
6870 || MEM_VOLATILE_P (inner)
6872 wanted_inner_mode = extraction_mode;
6877 if (BITS_BIG_ENDIAN)
6879 /* POS is passed as if BITS_BIG_ENDIAN == 0, so we need to convert it to
6880 BITS_BIG_ENDIAN style. If position is constant, compute new
6881 position. Otherwise, build subtraction.
6882 Note that POS is relative to the mode of the original argument.
6883 If it's a MEM we need to recompute POS relative to that.
6884 However, if we're extracting from (or inserting into) a register,
6885 we want to recompute POS relative to wanted_inner_mode. */
6886 int width = (MEM_P (inner)
6887 ? GET_MODE_BITSIZE (is_mode)
6888 : GET_MODE_BITSIZE (wanted_inner_mode));
6891 pos = width - len - pos;
6894 = gen_rtx_MINUS (GET_MODE (pos_rtx), GEN_INT (width - len), pos_rtx);
6895 /* POS may be less than 0 now, but we check for that below.
6896 Note that it can only be less than 0 if !MEM_P (inner). */
6899 /* If INNER has a wider mode, and this is a constant extraction, try to
6900 make it smaller and adjust the byte to point to the byte containing
6902 if (wanted_inner_mode != VOIDmode
6903 && inner_mode != wanted_inner_mode
6905 && GET_MODE_SIZE (wanted_inner_mode) < GET_MODE_SIZE (is_mode)
6907 && ! mode_dependent_address_p (XEXP (inner, 0))
6908 && ! MEM_VOLATILE_P (inner))
6912 /* The computations below will be correct if the machine is big
6913 endian in both bits and bytes or little endian in bits and bytes.
6914 If it is mixed, we must adjust. */
6916 /* If bytes are big endian and we had a paradoxical SUBREG, we must
6917 adjust OFFSET to compensate. */
6918 if (BYTES_BIG_ENDIAN
6919 && GET_MODE_SIZE (inner_mode) < GET_MODE_SIZE (is_mode))
6920 offset -= GET_MODE_SIZE (is_mode) - GET_MODE_SIZE (inner_mode);
6922 /* We can now move to the desired byte. */
6923 offset += (pos / GET_MODE_BITSIZE (wanted_inner_mode))
6924 * GET_MODE_SIZE (wanted_inner_mode);
6925 pos %= GET_MODE_BITSIZE (wanted_inner_mode);
6927 if (BYTES_BIG_ENDIAN != BITS_BIG_ENDIAN
6928 && is_mode != wanted_inner_mode)
6929 offset = (GET_MODE_SIZE (is_mode)
6930 - GET_MODE_SIZE (wanted_inner_mode) - offset);
6932 inner = adjust_address_nv (inner, wanted_inner_mode, offset);
6935 /* If INNER is not memory, get it into the proper mode. If we are changing
6936 its mode, POS must be a constant and smaller than the size of the new
6938 else if (!MEM_P (inner))
6940 /* On the LHS, don't create paradoxical subregs implicitely truncating
6941 the register unless TRULY_NOOP_TRUNCATION. */
6943 && !TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (GET_MODE (inner)),
6944 GET_MODE_BITSIZE (wanted_inner_mode)))
6947 if (GET_MODE (inner) != wanted_inner_mode
6949 || orig_pos + len > GET_MODE_BITSIZE (wanted_inner_mode)))
6955 inner = force_to_mode (inner, wanted_inner_mode,
6957 || len + orig_pos >= HOST_BITS_PER_WIDE_INT
6958 ? ~(unsigned HOST_WIDE_INT) 0
6959 : ((((unsigned HOST_WIDE_INT) 1 << len) - 1)
6964 /* Adjust mode of POS_RTX, if needed. If we want a wider mode, we
6965 have to zero extend. Otherwise, we can just use a SUBREG. */
6967 && GET_MODE_SIZE (pos_mode) > GET_MODE_SIZE (GET_MODE (pos_rtx)))
6969 rtx temp = gen_rtx_ZERO_EXTEND (pos_mode, pos_rtx);
6971 /* If we know that no extraneous bits are set, and that the high
6972 bit is not set, convert extraction to cheaper one - either
6973 SIGN_EXTENSION or ZERO_EXTENSION, that are equivalent in these
6975 if (flag_expensive_optimizations
6976 && (GET_MODE_BITSIZE (GET_MODE (pos_rtx)) <= HOST_BITS_PER_WIDE_INT
6977 && ((nonzero_bits (pos_rtx, GET_MODE (pos_rtx))
6978 & ~(((unsigned HOST_WIDE_INT)
6979 GET_MODE_MASK (GET_MODE (pos_rtx)))
6983 rtx temp1 = gen_rtx_SIGN_EXTEND (pos_mode, pos_rtx);
6985 /* Prefer ZERO_EXTENSION, since it gives more information to
6987 if (rtx_cost (temp1, SET, optimize_this_for_speed_p)
6988 < rtx_cost (temp, SET, optimize_this_for_speed_p))
6993 else if (pos_rtx != 0
6994 && GET_MODE_SIZE (pos_mode) < GET_MODE_SIZE (GET_MODE (pos_rtx)))
6995 pos_rtx = gen_lowpart (pos_mode, pos_rtx);
6997 /* Make POS_RTX unless we already have it and it is correct. If we don't
6998 have a POS_RTX but we do have an ORIG_POS_RTX, the latter must
7000 if (pos_rtx == 0 && orig_pos_rtx != 0 && INTVAL (orig_pos_rtx) == pos)
7001 pos_rtx = orig_pos_rtx;
7003 else if (pos_rtx == 0)
7004 pos_rtx = GEN_INT (pos);
7006 /* Make the required operation. See if we can use existing rtx. */
7007 new_rtx = gen_rtx_fmt_eee (unsignedp ? ZERO_EXTRACT : SIGN_EXTRACT,
7008 extraction_mode, inner, GEN_INT (len), pos_rtx);
7010 new_rtx = gen_lowpart (mode, new_rtx);
7015 /* See if X contains an ASHIFT of COUNT or more bits that can be commuted
7016 with any other operations in X. Return X without that shift if so. */
7019 extract_left_shift (rtx x, int count)
7021 enum rtx_code code = GET_CODE (x);
7022 enum machine_mode mode = GET_MODE (x);
7028 /* This is the shift itself. If it is wide enough, we will return
7029 either the value being shifted if the shift count is equal to
7030 COUNT or a shift for the difference. */
7031 if (CONST_INT_P (XEXP (x, 1))
7032 && INTVAL (XEXP (x, 1)) >= count)
7033 return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (x, 0),
7034 INTVAL (XEXP (x, 1)) - count);
7038 if ((tem = extract_left_shift (XEXP (x, 0), count)) != 0)
7039 return simplify_gen_unary (code, mode, tem, mode);
7043 case PLUS: case IOR: case XOR: case AND:
7044 /* If we can safely shift this constant and we find the inner shift,
7045 make a new operation. */
7046 if (CONST_INT_P (XEXP (x, 1))
7047 && (INTVAL (XEXP (x, 1)) & ((((HOST_WIDE_INT) 1 << count)) - 1)) == 0
7048 && (tem = extract_left_shift (XEXP (x, 0), count)) != 0)
7049 return simplify_gen_binary (code, mode, tem,
7050 GEN_INT (INTVAL (XEXP (x, 1)) >> count));
7061 /* Look at the expression rooted at X. Look for expressions
7062 equivalent to ZERO_EXTRACT, SIGN_EXTRACT, ZERO_EXTEND, SIGN_EXTEND.
7063 Form these expressions.
7065 Return the new rtx, usually just X.
7067 Also, for machines like the VAX that don't have logical shift insns,
7068 try to convert logical to arithmetic shift operations in cases where
7069 they are equivalent. This undoes the canonicalizations to logical
7070 shifts done elsewhere.
7072 We try, as much as possible, to re-use rtl expressions to save memory.
7074 IN_CODE says what kind of expression we are processing. Normally, it is
7075 SET. In a memory address (inside a MEM, PLUS or minus, the latter two
7076 being kludges), it is MEM. When processing the arguments of a comparison
7077 or a COMPARE against zero, it is COMPARE. */
7080 make_compound_operation (rtx x, enum rtx_code in_code)
7082 enum rtx_code code = GET_CODE (x);
7083 enum machine_mode mode = GET_MODE (x);
7084 int mode_width = GET_MODE_BITSIZE (mode);
7086 enum rtx_code next_code;
7092 /* Select the code to be used in recursive calls. Once we are inside an
7093 address, we stay there. If we have a comparison, set to COMPARE,
7094 but once inside, go back to our default of SET. */
7096 next_code = (code == MEM || code == PLUS || code == MINUS ? MEM
7097 : ((code == COMPARE || COMPARISON_P (x))
7098 && XEXP (x, 1) == const0_rtx) ? COMPARE
7099 : in_code == COMPARE ? SET : in_code);
7101 /* Process depending on the code of this operation. If NEW is set
7102 nonzero, it will be returned. */
7107 /* Convert shifts by constants into multiplications if inside
7109 if (in_code == MEM && CONST_INT_P (XEXP (x, 1))
7110 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT
7111 && INTVAL (XEXP (x, 1)) >= 0)
7113 new_rtx = make_compound_operation (XEXP (x, 0), next_code);
7114 new_rtx = gen_rtx_MULT (mode, new_rtx,
7115 GEN_INT ((HOST_WIDE_INT) 1
7116 << INTVAL (XEXP (x, 1))));
7121 /* If the second operand is not a constant, we can't do anything
7123 if (!CONST_INT_P (XEXP (x, 1)))
7126 /* If the constant is a power of two minus one and the first operand
7127 is a logical right shift, make an extraction. */
7128 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
7129 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
7131 new_rtx = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code);
7132 new_rtx = make_extraction (mode, new_rtx, 0, XEXP (XEXP (x, 0), 1), i, 1,
7133 0, in_code == COMPARE);
7136 /* Same as previous, but for (subreg (lshiftrt ...)) in first op. */
7137 else if (GET_CODE (XEXP (x, 0)) == SUBREG
7138 && subreg_lowpart_p (XEXP (x, 0))
7139 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == LSHIFTRT
7140 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
7142 new_rtx = make_compound_operation (XEXP (SUBREG_REG (XEXP (x, 0)), 0),
7144 new_rtx = make_extraction (GET_MODE (SUBREG_REG (XEXP (x, 0))), new_rtx, 0,
7145 XEXP (SUBREG_REG (XEXP (x, 0)), 1), i, 1,
7146 0, in_code == COMPARE);
7148 /* Same as previous, but for (xor/ior (lshiftrt...) (lshiftrt...)). */
7149 else if ((GET_CODE (XEXP (x, 0)) == XOR
7150 || GET_CODE (XEXP (x, 0)) == IOR)
7151 && GET_CODE (XEXP (XEXP (x, 0), 0)) == LSHIFTRT
7152 && GET_CODE (XEXP (XEXP (x, 0), 1)) == LSHIFTRT
7153 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
7155 /* Apply the distributive law, and then try to make extractions. */
7156 new_rtx = gen_rtx_fmt_ee (GET_CODE (XEXP (x, 0)), mode,
7157 gen_rtx_AND (mode, XEXP (XEXP (x, 0), 0),
7159 gen_rtx_AND (mode, XEXP (XEXP (x, 0), 1),
7161 new_rtx = make_compound_operation (new_rtx, in_code);
7164 /* If we are have (and (rotate X C) M) and C is larger than the number
7165 of bits in M, this is an extraction. */
7167 else if (GET_CODE (XEXP (x, 0)) == ROTATE
7168 && CONST_INT_P (XEXP (XEXP (x, 0), 1))
7169 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0
7170 && i <= INTVAL (XEXP (XEXP (x, 0), 1)))
7172 new_rtx = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code);
7173 new_rtx = make_extraction (mode, new_rtx,
7174 (GET_MODE_BITSIZE (mode)
7175 - INTVAL (XEXP (XEXP (x, 0), 1))),
7176 NULL_RTX, i, 1, 0, in_code == COMPARE);
7179 /* On machines without logical shifts, if the operand of the AND is
7180 a logical shift and our mask turns off all the propagated sign
7181 bits, we can replace the logical shift with an arithmetic shift. */
7182 else if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
7183 && !have_insn_for (LSHIFTRT, mode)
7184 && have_insn_for (ASHIFTRT, mode)
7185 && CONST_INT_P (XEXP (XEXP (x, 0), 1))
7186 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
7187 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT
7188 && mode_width <= HOST_BITS_PER_WIDE_INT)
7190 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
7192 mask >>= INTVAL (XEXP (XEXP (x, 0), 1));
7193 if ((INTVAL (XEXP (x, 1)) & ~mask) == 0)
7195 gen_rtx_ASHIFTRT (mode,
7196 make_compound_operation
7197 (XEXP (XEXP (x, 0), 0), next_code),
7198 XEXP (XEXP (x, 0), 1)));
7201 /* If the constant is one less than a power of two, this might be
7202 representable by an extraction even if no shift is present.
7203 If it doesn't end up being a ZERO_EXTEND, we will ignore it unless
7204 we are in a COMPARE. */
7205 else if ((i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
7206 new_rtx = make_extraction (mode,
7207 make_compound_operation (XEXP (x, 0),
7209 0, NULL_RTX, i, 1, 0, in_code == COMPARE);
7211 /* If we are in a comparison and this is an AND with a power of two,
7212 convert this into the appropriate bit extract. */
7213 else if (in_code == COMPARE
7214 && (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0)
7215 new_rtx = make_extraction (mode,
7216 make_compound_operation (XEXP (x, 0),
7218 i, NULL_RTX, 1, 1, 0, 1);
7223 /* If the sign bit is known to be zero, replace this with an
7224 arithmetic shift. */
7225 if (have_insn_for (ASHIFTRT, mode)
7226 && ! have_insn_for (LSHIFTRT, mode)
7227 && mode_width <= HOST_BITS_PER_WIDE_INT
7228 && (nonzero_bits (XEXP (x, 0), mode) & (1 << (mode_width - 1))) == 0)
7230 new_rtx = gen_rtx_ASHIFTRT (mode,
7231 make_compound_operation (XEXP (x, 0),
7237 /* ... fall through ... */
7243 /* If we have (ashiftrt (ashift foo C1) C2) with C2 >= C1,
7244 this is a SIGN_EXTRACT. */
7245 if (CONST_INT_P (rhs)
7246 && GET_CODE (lhs) == ASHIFT
7247 && CONST_INT_P (XEXP (lhs, 1))
7248 && INTVAL (rhs) >= INTVAL (XEXP (lhs, 1))
7249 && INTVAL (rhs) < mode_width)
7251 new_rtx = make_compound_operation (XEXP (lhs, 0), next_code);
7252 new_rtx = make_extraction (mode, new_rtx,
7253 INTVAL (rhs) - INTVAL (XEXP (lhs, 1)),
7254 NULL_RTX, mode_width - INTVAL (rhs),
7255 code == LSHIFTRT, 0, in_code == COMPARE);
7259 /* See if we have operations between an ASHIFTRT and an ASHIFT.
7260 If so, try to merge the shifts into a SIGN_EXTEND. We could
7261 also do this for some cases of SIGN_EXTRACT, but it doesn't
7262 seem worth the effort; the case checked for occurs on Alpha. */
7265 && ! (GET_CODE (lhs) == SUBREG
7266 && (OBJECT_P (SUBREG_REG (lhs))))
7267 && CONST_INT_P (rhs)
7268 && INTVAL (rhs) < HOST_BITS_PER_WIDE_INT
7269 && INTVAL (rhs) < mode_width
7270 && (new_rtx = extract_left_shift (lhs, INTVAL (rhs))) != 0)
7271 new_rtx = make_extraction (mode, make_compound_operation (new_rtx, next_code),
7272 0, NULL_RTX, mode_width - INTVAL (rhs),
7273 code == LSHIFTRT, 0, in_code == COMPARE);
7278 /* Call ourselves recursively on the inner expression. If we are
7279 narrowing the object and it has a different RTL code from
7280 what it originally did, do this SUBREG as a force_to_mode. */
7282 rtx inner = SUBREG_REG (x), simplified;
7284 tem = make_compound_operation (inner, in_code);
7287 = simplify_subreg (mode, tem, GET_MODE (inner), SUBREG_BYTE (x));
7291 if (GET_CODE (tem) != GET_CODE (inner)
7292 && GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (inner))
7293 && subreg_lowpart_p (x))
7295 rtx newer = force_to_mode (tem, mode, ~(HOST_WIDE_INT) 0, 0);
7297 /* If we have something other than a SUBREG, we might have
7298 done an expansion, so rerun ourselves. */
7299 if (GET_CODE (newer) != SUBREG)
7300 newer = make_compound_operation (newer, in_code);
7302 /* force_to_mode can expand compounds. If it just re-expanded the
7303 compound, use gen_lowpart to convert to the desired mode. */
7304 if (rtx_equal_p (newer, x)
7305 /* Likewise if it re-expanded the compound only partially.
7306 This happens for SUBREG of ZERO_EXTRACT if they extract
7307 the same number of bits. */
7308 || (GET_CODE (newer) == SUBREG
7309 && (GET_CODE (SUBREG_REG (newer)) == LSHIFTRT
7310 || GET_CODE (SUBREG_REG (newer)) == ASHIFTRT)
7311 && GET_CODE (inner) == AND
7312 && rtx_equal_p (SUBREG_REG (newer), XEXP (inner, 0))))
7313 return gen_lowpart (GET_MODE (x), tem);
7329 x = gen_lowpart (mode, new_rtx);
7330 code = GET_CODE (x);
7333 /* Now recursively process each operand of this operation. */
7334 fmt = GET_RTX_FORMAT (code);
7335 for (i = 0; i < GET_RTX_LENGTH (code); i++)
7338 new_rtx = make_compound_operation (XEXP (x, i), next_code);
7339 SUBST (XEXP (x, i), new_rtx);
7341 else if (fmt[i] == 'E')
7342 for (j = 0; j < XVECLEN (x, i); j++)
7344 new_rtx = make_compound_operation (XVECEXP (x, i, j), next_code);
7345 SUBST (XVECEXP (x, i, j), new_rtx);
7348 /* If this is a commutative operation, the changes to the operands
7349 may have made it noncanonical. */
7350 if (COMMUTATIVE_ARITH_P (x)
7351 && swap_commutative_operands_p (XEXP (x, 0), XEXP (x, 1)))
7354 SUBST (XEXP (x, 0), XEXP (x, 1));
7355 SUBST (XEXP (x, 1), tem);
7361 /* Given M see if it is a value that would select a field of bits
7362 within an item, but not the entire word. Return -1 if not.
7363 Otherwise, return the starting position of the field, where 0 is the
7366 *PLEN is set to the length of the field. */
7369 get_pos_from_mask (unsigned HOST_WIDE_INT m, unsigned HOST_WIDE_INT *plen)
7371 /* Get the bit number of the first 1 bit from the right, -1 if none. */
7372 int pos = exact_log2 (m & -m);
7376 /* Now shift off the low-order zero bits and see if we have a
7377 power of two minus 1. */
7378 len = exact_log2 ((m >> pos) + 1);
7387 /* If X refers to a register that equals REG in value, replace these
7388 references with REG. */
7390 canon_reg_for_combine (rtx x, rtx reg)
7397 enum rtx_code code = GET_CODE (x);
7398 switch (GET_RTX_CLASS (code))
7401 op0 = canon_reg_for_combine (XEXP (x, 0), reg);
7402 if (op0 != XEXP (x, 0))
7403 return simplify_gen_unary (GET_CODE (x), GET_MODE (x), op0,
7408 case RTX_COMM_ARITH:
7409 op0 = canon_reg_for_combine (XEXP (x, 0), reg);
7410 op1 = canon_reg_for_combine (XEXP (x, 1), reg);
7411 if (op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
7412 return simplify_gen_binary (GET_CODE (x), GET_MODE (x), op0, op1);
7416 case RTX_COMM_COMPARE:
7417 op0 = canon_reg_for_combine (XEXP (x, 0), reg);
7418 op1 = canon_reg_for_combine (XEXP (x, 1), reg);
7419 if (op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
7420 return simplify_gen_relational (GET_CODE (x), GET_MODE (x),
7421 GET_MODE (op0), op0, op1);
7425 case RTX_BITFIELD_OPS:
7426 op0 = canon_reg_for_combine (XEXP (x, 0), reg);
7427 op1 = canon_reg_for_combine (XEXP (x, 1), reg);
7428 op2 = canon_reg_for_combine (XEXP (x, 2), reg);
7429 if (op0 != XEXP (x, 0) || op1 != XEXP (x, 1) || op2 != XEXP (x, 2))
7430 return simplify_gen_ternary (GET_CODE (x), GET_MODE (x),
7431 GET_MODE (op0), op0, op1, op2);
7436 if (rtx_equal_p (get_last_value (reg), x)
7437 || rtx_equal_p (reg, get_last_value (x)))
7446 fmt = GET_RTX_FORMAT (code);
7448 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
7451 rtx op = canon_reg_for_combine (XEXP (x, i), reg);
7452 if (op != XEXP (x, i))
7462 else if (fmt[i] == 'E')
7465 for (j = 0; j < XVECLEN (x, i); j++)
7467 rtx op = canon_reg_for_combine (XVECEXP (x, i, j), reg);
7468 if (op != XVECEXP (x, i, j))
7475 XVECEXP (x, i, j) = op;
7486 /* Return X converted to MODE. If the value is already truncated to
7487 MODE we can just return a subreg even though in the general case we
7488 would need an explicit truncation. */
7491 gen_lowpart_or_truncate (enum machine_mode mode, rtx x)
7493 if (!CONST_INT_P (x)
7494 && GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (x))
7495 && !TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode),
7496 GET_MODE_BITSIZE (GET_MODE (x)))
7497 && !(REG_P (x) && reg_truncated_to_mode (mode, x)))
7499 /* Bit-cast X into an integer mode. */
7500 if (!SCALAR_INT_MODE_P (GET_MODE (x)))
7501 x = gen_lowpart (int_mode_for_mode (GET_MODE (x)), x);
7502 x = simplify_gen_unary (TRUNCATE, int_mode_for_mode (mode),
7506 return gen_lowpart (mode, x);
7509 /* See if X can be simplified knowing that we will only refer to it in
7510 MODE and will only refer to those bits that are nonzero in MASK.
7511 If other bits are being computed or if masking operations are done
7512 that select a superset of the bits in MASK, they can sometimes be
7515 Return a possibly simplified expression, but always convert X to
7516 MODE. If X is a CONST_INT, AND the CONST_INT with MASK.
7518 If JUST_SELECT is nonzero, don't optimize by noticing that bits in MASK
7519 are all off in X. This is used when X will be complemented, by either
7520 NOT, NEG, or XOR. */
7523 force_to_mode (rtx x, enum machine_mode mode, unsigned HOST_WIDE_INT mask,
7526 enum rtx_code code = GET_CODE (x);
7527 int next_select = just_select || code == XOR || code == NOT || code == NEG;
7528 enum machine_mode op_mode;
7529 unsigned HOST_WIDE_INT fuller_mask, nonzero;
7532 /* If this is a CALL or ASM_OPERANDS, don't do anything. Some of the
7533 code below will do the wrong thing since the mode of such an
7534 expression is VOIDmode.
7536 Also do nothing if X is a CLOBBER; this can happen if X was
7537 the return value from a call to gen_lowpart. */
7538 if (code == CALL || code == ASM_OPERANDS || code == CLOBBER)
7541 /* We want to perform the operation is its present mode unless we know
7542 that the operation is valid in MODE, in which case we do the operation
7544 op_mode = ((GET_MODE_CLASS (mode) == GET_MODE_CLASS (GET_MODE (x))
7545 && have_insn_for (code, mode))
7546 ? mode : GET_MODE (x));
7548 /* It is not valid to do a right-shift in a narrower mode
7549 than the one it came in with. */
7550 if ((code == LSHIFTRT || code == ASHIFTRT)
7551 && GET_MODE_BITSIZE (mode) < GET_MODE_BITSIZE (GET_MODE (x)))
7552 op_mode = GET_MODE (x);
7554 /* Truncate MASK to fit OP_MODE. */
7556 mask &= GET_MODE_MASK (op_mode);
7558 /* When we have an arithmetic operation, or a shift whose count we
7559 do not know, we need to assume that all bits up to the highest-order
7560 bit in MASK will be needed. This is how we form such a mask. */
7561 if (mask & ((unsigned HOST_WIDE_INT) 1 << (HOST_BITS_PER_WIDE_INT - 1)))
7562 fuller_mask = ~(unsigned HOST_WIDE_INT) 0;
7564 fuller_mask = (((unsigned HOST_WIDE_INT) 1 << (floor_log2 (mask) + 1))
7567 /* Determine what bits of X are guaranteed to be (non)zero. */
7568 nonzero = nonzero_bits (x, mode);
7570 /* If none of the bits in X are needed, return a zero. */
7571 if (!just_select && (nonzero & mask) == 0 && !side_effects_p (x))
7574 /* If X is a CONST_INT, return a new one. Do this here since the
7575 test below will fail. */
7576 if (CONST_INT_P (x))
7578 if (SCALAR_INT_MODE_P (mode))
7579 return gen_int_mode (INTVAL (x) & mask, mode);
7582 x = GEN_INT (INTVAL (x) & mask);
7583 return gen_lowpart_common (mode, x);
7587 /* If X is narrower than MODE and we want all the bits in X's mode, just
7588 get X in the proper mode. */
7589 if (GET_MODE_SIZE (GET_MODE (x)) < GET_MODE_SIZE (mode)
7590 && (GET_MODE_MASK (GET_MODE (x)) & ~mask) == 0)
7591 return gen_lowpart (mode, x);
7593 /* We can ignore the effect of a SUBREG if it narrows the mode or
7594 if the constant masks to zero all the bits the mode doesn't have. */
7595 if (GET_CODE (x) == SUBREG
7596 && subreg_lowpart_p (x)
7597 && ((GET_MODE_SIZE (GET_MODE (x))
7598 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
7600 & GET_MODE_MASK (GET_MODE (x))
7601 & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (x)))))))
7602 return force_to_mode (SUBREG_REG (x), mode, mask, next_select);
7604 /* The arithmetic simplifications here only work for scalar integer modes. */
7605 if (!SCALAR_INT_MODE_P (mode) || !SCALAR_INT_MODE_P (GET_MODE (x)))
7606 return gen_lowpart_or_truncate (mode, x);
7611 /* If X is a (clobber (const_int)), return it since we know we are
7612 generating something that won't match. */
7619 x = expand_compound_operation (x);
7620 if (GET_CODE (x) != code)
7621 return force_to_mode (x, mode, mask, next_select);
7625 /* Similarly for a truncate. */
7626 return force_to_mode (XEXP (x, 0), mode, mask, next_select);
7629 /* If this is an AND with a constant, convert it into an AND
7630 whose constant is the AND of that constant with MASK. If it
7631 remains an AND of MASK, delete it since it is redundant. */
7633 if (CONST_INT_P (XEXP (x, 1)))
7635 x = simplify_and_const_int (x, op_mode, XEXP (x, 0),
7636 mask & INTVAL (XEXP (x, 1)));
7638 /* If X is still an AND, see if it is an AND with a mask that
7639 is just some low-order bits. If so, and it is MASK, we don't
7642 if (GET_CODE (x) == AND && CONST_INT_P (XEXP (x, 1))
7643 && ((INTVAL (XEXP (x, 1)) & GET_MODE_MASK (GET_MODE (x)))
7647 /* If it remains an AND, try making another AND with the bits
7648 in the mode mask that aren't in MASK turned on. If the
7649 constant in the AND is wide enough, this might make a
7650 cheaper constant. */
7652 if (GET_CODE (x) == AND && CONST_INT_P (XEXP (x, 1))
7653 && GET_MODE_MASK (GET_MODE (x)) != mask
7654 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT)
7656 HOST_WIDE_INT cval = (INTVAL (XEXP (x, 1))
7657 | (GET_MODE_MASK (GET_MODE (x)) & ~mask));
7658 int width = GET_MODE_BITSIZE (GET_MODE (x));
7661 /* If MODE is narrower than HOST_WIDE_INT and CVAL is a negative
7662 number, sign extend it. */
7663 if (width > 0 && width < HOST_BITS_PER_WIDE_INT
7664 && (cval & ((HOST_WIDE_INT) 1 << (width - 1))) != 0)
7665 cval |= (HOST_WIDE_INT) -1 << width;
7667 y = simplify_gen_binary (AND, GET_MODE (x),
7668 XEXP (x, 0), GEN_INT (cval));
7669 if (rtx_cost (y, SET, optimize_this_for_speed_p)
7670 < rtx_cost (x, SET, optimize_this_for_speed_p))
7680 /* In (and (plus FOO C1) M), if M is a mask that just turns off
7681 low-order bits (as in an alignment operation) and FOO is already
7682 aligned to that boundary, mask C1 to that boundary as well.
7683 This may eliminate that PLUS and, later, the AND. */
7686 unsigned int width = GET_MODE_BITSIZE (mode);
7687 unsigned HOST_WIDE_INT smask = mask;
7689 /* If MODE is narrower than HOST_WIDE_INT and mask is a negative
7690 number, sign extend it. */
7692 if (width < HOST_BITS_PER_WIDE_INT
7693 && (smask & ((HOST_WIDE_INT) 1 << (width - 1))) != 0)
7694 smask |= (HOST_WIDE_INT) -1 << width;
7696 if (CONST_INT_P (XEXP (x, 1))
7697 && exact_log2 (- smask) >= 0
7698 && (nonzero_bits (XEXP (x, 0), mode) & ~smask) == 0
7699 && (INTVAL (XEXP (x, 1)) & ~smask) != 0)
7700 return force_to_mode (plus_constant (XEXP (x, 0),
7701 (INTVAL (XEXP (x, 1)) & smask)),
7702 mode, smask, next_select);
7705 /* ... fall through ... */
7708 /* For PLUS, MINUS and MULT, we need any bits less significant than the
7709 most significant bit in MASK since carries from those bits will
7710 affect the bits we are interested in. */
7715 /* If X is (minus C Y) where C's least set bit is larger than any bit
7716 in the mask, then we may replace with (neg Y). */
7717 if (CONST_INT_P (XEXP (x, 0))
7718 && (((unsigned HOST_WIDE_INT) (INTVAL (XEXP (x, 0))
7719 & -INTVAL (XEXP (x, 0))))
7722 x = simplify_gen_unary (NEG, GET_MODE (x), XEXP (x, 1),
7724 return force_to_mode (x, mode, mask, next_select);
7727 /* Similarly, if C contains every bit in the fuller_mask, then we may
7728 replace with (not Y). */
7729 if (CONST_INT_P (XEXP (x, 0))
7730 && ((INTVAL (XEXP (x, 0)) | (HOST_WIDE_INT) fuller_mask)
7731 == INTVAL (XEXP (x, 0))))
7733 x = simplify_gen_unary (NOT, GET_MODE (x),
7734 XEXP (x, 1), GET_MODE (x));
7735 return force_to_mode (x, mode, mask, next_select);
7743 /* If X is (ior (lshiftrt FOO C1) C2), try to commute the IOR and
7744 LSHIFTRT so we end up with an (and (lshiftrt (ior ...) ...) ...)
7745 operation which may be a bitfield extraction. Ensure that the
7746 constant we form is not wider than the mode of X. */
7748 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
7749 && CONST_INT_P (XEXP (XEXP (x, 0), 1))
7750 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
7751 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT
7752 && CONST_INT_P (XEXP (x, 1))
7753 && ((INTVAL (XEXP (XEXP (x, 0), 1))
7754 + floor_log2 (INTVAL (XEXP (x, 1))))
7755 < GET_MODE_BITSIZE (GET_MODE (x)))
7756 && (INTVAL (XEXP (x, 1))
7757 & ~nonzero_bits (XEXP (x, 0), GET_MODE (x))) == 0)
7759 temp = GEN_INT ((INTVAL (XEXP (x, 1)) & mask)
7760 << INTVAL (XEXP (XEXP (x, 0), 1)));
7761 temp = simplify_gen_binary (GET_CODE (x), GET_MODE (x),
7762 XEXP (XEXP (x, 0), 0), temp);
7763 x = simplify_gen_binary (LSHIFTRT, GET_MODE (x), temp,
7764 XEXP (XEXP (x, 0), 1));
7765 return force_to_mode (x, mode, mask, next_select);
7769 /* For most binary operations, just propagate into the operation and
7770 change the mode if we have an operation of that mode. */
7772 op0 = force_to_mode (XEXP (x, 0), mode, mask, next_select);
7773 op1 = force_to_mode (XEXP (x, 1), mode, mask, next_select);
7775 /* If we ended up truncating both operands, truncate the result of the
7776 operation instead. */
7777 if (GET_CODE (op0) == TRUNCATE
7778 && GET_CODE (op1) == TRUNCATE)
7780 op0 = XEXP (op0, 0);
7781 op1 = XEXP (op1, 0);
7784 op0 = gen_lowpart_or_truncate (op_mode, op0);
7785 op1 = gen_lowpart_or_truncate (op_mode, op1);
7787 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
7788 x = simplify_gen_binary (code, op_mode, op0, op1);
7792 /* For left shifts, do the same, but just for the first operand.
7793 However, we cannot do anything with shifts where we cannot
7794 guarantee that the counts are smaller than the size of the mode
7795 because such a count will have a different meaning in a
7798 if (! (CONST_INT_P (XEXP (x, 1))
7799 && INTVAL (XEXP (x, 1)) >= 0
7800 && INTVAL (XEXP (x, 1)) < GET_MODE_BITSIZE (mode))
7801 && ! (GET_MODE (XEXP (x, 1)) != VOIDmode
7802 && (nonzero_bits (XEXP (x, 1), GET_MODE (XEXP (x, 1)))
7803 < (unsigned HOST_WIDE_INT) GET_MODE_BITSIZE (mode))))
7806 /* If the shift count is a constant and we can do arithmetic in
7807 the mode of the shift, refine which bits we need. Otherwise, use the
7808 conservative form of the mask. */
7809 if (CONST_INT_P (XEXP (x, 1))
7810 && INTVAL (XEXP (x, 1)) >= 0
7811 && INTVAL (XEXP (x, 1)) < GET_MODE_BITSIZE (op_mode)
7812 && GET_MODE_BITSIZE (op_mode) <= HOST_BITS_PER_WIDE_INT)
7813 mask >>= INTVAL (XEXP (x, 1));
7817 op0 = gen_lowpart_or_truncate (op_mode,
7818 force_to_mode (XEXP (x, 0), op_mode,
7819 mask, next_select));
7821 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0))
7822 x = simplify_gen_binary (code, op_mode, op0, XEXP (x, 1));
7826 /* Here we can only do something if the shift count is a constant,
7827 this shift constant is valid for the host, and we can do arithmetic
7830 if (CONST_INT_P (XEXP (x, 1))
7831 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT
7832 && GET_MODE_BITSIZE (op_mode) <= HOST_BITS_PER_WIDE_INT)
7834 rtx inner = XEXP (x, 0);
7835 unsigned HOST_WIDE_INT inner_mask;
7837 /* Select the mask of the bits we need for the shift operand. */
7838 inner_mask = mask << INTVAL (XEXP (x, 1));
7840 /* We can only change the mode of the shift if we can do arithmetic
7841 in the mode of the shift and INNER_MASK is no wider than the
7842 width of X's mode. */
7843 if ((inner_mask & ~GET_MODE_MASK (GET_MODE (x))) != 0)
7844 op_mode = GET_MODE (x);
7846 inner = force_to_mode (inner, op_mode, inner_mask, next_select);
7848 if (GET_MODE (x) != op_mode || inner != XEXP (x, 0))
7849 x = simplify_gen_binary (LSHIFTRT, op_mode, inner, XEXP (x, 1));
7852 /* If we have (and (lshiftrt FOO C1) C2) where the combination of the
7853 shift and AND produces only copies of the sign bit (C2 is one less
7854 than a power of two), we can do this with just a shift. */
7856 if (GET_CODE (x) == LSHIFTRT
7857 && CONST_INT_P (XEXP (x, 1))
7858 /* The shift puts one of the sign bit copies in the least significant
7860 && ((INTVAL (XEXP (x, 1))
7861 + num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0))))
7862 >= GET_MODE_BITSIZE (GET_MODE (x)))
7863 && exact_log2 (mask + 1) >= 0
7864 /* Number of bits left after the shift must be more than the mask
7866 && ((INTVAL (XEXP (x, 1)) + exact_log2 (mask + 1))
7867 <= GET_MODE_BITSIZE (GET_MODE (x)))
7868 /* Must be more sign bit copies than the mask needs. */
7869 && ((int) num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
7870 >= exact_log2 (mask + 1)))
7871 x = simplify_gen_binary (LSHIFTRT, GET_MODE (x), XEXP (x, 0),
7872 GEN_INT (GET_MODE_BITSIZE (GET_MODE (x))
7873 - exact_log2 (mask + 1)));
7878 /* If we are just looking for the sign bit, we don't need this shift at
7879 all, even if it has a variable count. */
7880 if (GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
7881 && (mask == ((unsigned HOST_WIDE_INT) 1
7882 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
7883 return force_to_mode (XEXP (x, 0), mode, mask, next_select);
7885 /* If this is a shift by a constant, get a mask that contains those bits
7886 that are not copies of the sign bit. We then have two cases: If
7887 MASK only includes those bits, this can be a logical shift, which may
7888 allow simplifications. If MASK is a single-bit field not within
7889 those bits, we are requesting a copy of the sign bit and hence can
7890 shift the sign bit to the appropriate location. */
7892 if (CONST_INT_P (XEXP (x, 1)) && INTVAL (XEXP (x, 1)) >= 0
7893 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT)
7897 /* If the considered data is wider than HOST_WIDE_INT, we can't
7898 represent a mask for all its bits in a single scalar.
7899 But we only care about the lower bits, so calculate these. */
7901 if (GET_MODE_BITSIZE (GET_MODE (x)) > HOST_BITS_PER_WIDE_INT)
7903 nonzero = ~(HOST_WIDE_INT) 0;
7905 /* GET_MODE_BITSIZE (GET_MODE (x)) - INTVAL (XEXP (x, 1))
7906 is the number of bits a full-width mask would have set.
7907 We need only shift if these are fewer than nonzero can
7908 hold. If not, we must keep all bits set in nonzero. */
7910 if (GET_MODE_BITSIZE (GET_MODE (x)) - INTVAL (XEXP (x, 1))
7911 < HOST_BITS_PER_WIDE_INT)
7912 nonzero >>= INTVAL (XEXP (x, 1))
7913 + HOST_BITS_PER_WIDE_INT
7914 - GET_MODE_BITSIZE (GET_MODE (x)) ;
7918 nonzero = GET_MODE_MASK (GET_MODE (x));
7919 nonzero >>= INTVAL (XEXP (x, 1));
7922 if ((mask & ~nonzero) == 0)
7924 x = simplify_shift_const (NULL_RTX, LSHIFTRT, GET_MODE (x),
7925 XEXP (x, 0), INTVAL (XEXP (x, 1)));
7926 if (GET_CODE (x) != ASHIFTRT)
7927 return force_to_mode (x, mode, mask, next_select);
7930 else if ((i = exact_log2 (mask)) >= 0)
7932 x = simplify_shift_const
7933 (NULL_RTX, LSHIFTRT, GET_MODE (x), XEXP (x, 0),
7934 GET_MODE_BITSIZE (GET_MODE (x)) - 1 - i);
7936 if (GET_CODE (x) != ASHIFTRT)
7937 return force_to_mode (x, mode, mask, next_select);
7941 /* If MASK is 1, convert this to an LSHIFTRT. This can be done
7942 even if the shift count isn't a constant. */
7944 x = simplify_gen_binary (LSHIFTRT, GET_MODE (x),
7945 XEXP (x, 0), XEXP (x, 1));
7949 /* If this is a zero- or sign-extension operation that just affects bits
7950 we don't care about, remove it. Be sure the call above returned
7951 something that is still a shift. */
7953 if ((GET_CODE (x) == LSHIFTRT || GET_CODE (x) == ASHIFTRT)
7954 && CONST_INT_P (XEXP (x, 1))
7955 && INTVAL (XEXP (x, 1)) >= 0
7956 && (INTVAL (XEXP (x, 1))
7957 <= GET_MODE_BITSIZE (GET_MODE (x)) - (floor_log2 (mask) + 1))
7958 && GET_CODE (XEXP (x, 0)) == ASHIFT
7959 && XEXP (XEXP (x, 0), 1) == XEXP (x, 1))
7960 return force_to_mode (XEXP (XEXP (x, 0), 0), mode, mask,
7967 /* If the shift count is constant and we can do computations
7968 in the mode of X, compute where the bits we care about are.
7969 Otherwise, we can't do anything. Don't change the mode of
7970 the shift or propagate MODE into the shift, though. */
7971 if (CONST_INT_P (XEXP (x, 1))
7972 && INTVAL (XEXP (x, 1)) >= 0)
7974 temp = simplify_binary_operation (code == ROTATE ? ROTATERT : ROTATE,
7975 GET_MODE (x), GEN_INT (mask),
7977 if (temp && CONST_INT_P (temp))
7979 force_to_mode (XEXP (x, 0), GET_MODE (x),
7980 INTVAL (temp), next_select));
7985 /* If we just want the low-order bit, the NEG isn't needed since it
7986 won't change the low-order bit. */
7988 return force_to_mode (XEXP (x, 0), mode, mask, just_select);
7990 /* We need any bits less significant than the most significant bit in
7991 MASK since carries from those bits will affect the bits we are
7997 /* (not FOO) is (xor FOO CONST), so if FOO is an LSHIFTRT, we can do the
7998 same as the XOR case above. Ensure that the constant we form is not
7999 wider than the mode of X. */
8001 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
8002 && CONST_INT_P (XEXP (XEXP (x, 0), 1))
8003 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
8004 && (INTVAL (XEXP (XEXP (x, 0), 1)) + floor_log2 (mask)
8005 < GET_MODE_BITSIZE (GET_MODE (x)))
8006 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT)
8008 temp = gen_int_mode (mask << INTVAL (XEXP (XEXP (x, 0), 1)),
8010 temp = simplify_gen_binary (XOR, GET_MODE (x),
8011 XEXP (XEXP (x, 0), 0), temp);
8012 x = simplify_gen_binary (LSHIFTRT, GET_MODE (x),
8013 temp, XEXP (XEXP (x, 0), 1));
8015 return force_to_mode (x, mode, mask, next_select);
8018 /* (and (not FOO) CONST) is (not (or FOO (not CONST))), so we must
8019 use the full mask inside the NOT. */
8023 op0 = gen_lowpart_or_truncate (op_mode,
8024 force_to_mode (XEXP (x, 0), mode, mask,
8026 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0))
8027 x = simplify_gen_unary (code, op_mode, op0, op_mode);
8031 /* (and (ne FOO 0) CONST) can be (and FOO CONST) if CONST is included
8032 in STORE_FLAG_VALUE and FOO has a single bit that might be nonzero,
8033 which is equal to STORE_FLAG_VALUE. */
8034 if ((mask & ~STORE_FLAG_VALUE) == 0 && XEXP (x, 1) == const0_rtx
8035 && GET_MODE (XEXP (x, 0)) == mode
8036 && exact_log2 (nonzero_bits (XEXP (x, 0), mode)) >= 0
8037 && (nonzero_bits (XEXP (x, 0), mode)
8038 == (unsigned HOST_WIDE_INT) STORE_FLAG_VALUE))
8039 return force_to_mode (XEXP (x, 0), mode, mask, next_select);
8044 /* We have no way of knowing if the IF_THEN_ELSE can itself be
8045 written in a narrower mode. We play it safe and do not do so. */
8048 gen_lowpart_or_truncate (GET_MODE (x),
8049 force_to_mode (XEXP (x, 1), mode,
8050 mask, next_select)));
8052 gen_lowpart_or_truncate (GET_MODE (x),
8053 force_to_mode (XEXP (x, 2), mode,
8054 mask, next_select)));
8061 /* Ensure we return a value of the proper mode. */
8062 return gen_lowpart_or_truncate (mode, x);
8065 /* Return nonzero if X is an expression that has one of two values depending on
8066 whether some other value is zero or nonzero. In that case, we return the
8067 value that is being tested, *PTRUE is set to the value if the rtx being
8068 returned has a nonzero value, and *PFALSE is set to the other alternative.
8070 If we return zero, we set *PTRUE and *PFALSE to X. */
8073 if_then_else_cond (rtx x, rtx *ptrue, rtx *pfalse)
8075 enum machine_mode mode = GET_MODE (x);
8076 enum rtx_code code = GET_CODE (x);
8077 rtx cond0, cond1, true0, true1, false0, false1;
8078 unsigned HOST_WIDE_INT nz;
8080 /* If we are comparing a value against zero, we are done. */
8081 if ((code == NE || code == EQ)
8082 && XEXP (x, 1) == const0_rtx)
8084 *ptrue = (code == NE) ? const_true_rtx : const0_rtx;
8085 *pfalse = (code == NE) ? const0_rtx : const_true_rtx;
8089 /* If this is a unary operation whose operand has one of two values, apply
8090 our opcode to compute those values. */
8091 else if (UNARY_P (x)
8092 && (cond0 = if_then_else_cond (XEXP (x, 0), &true0, &false0)) != 0)
8094 *ptrue = simplify_gen_unary (code, mode, true0, GET_MODE (XEXP (x, 0)));
8095 *pfalse = simplify_gen_unary (code, mode, false0,
8096 GET_MODE (XEXP (x, 0)));
8100 /* If this is a COMPARE, do nothing, since the IF_THEN_ELSE we would
8101 make can't possibly match and would suppress other optimizations. */
8102 else if (code == COMPARE)
8105 /* If this is a binary operation, see if either side has only one of two
8106 values. If either one does or if both do and they are conditional on
8107 the same value, compute the new true and false values. */
8108 else if (BINARY_P (x))
8110 cond0 = if_then_else_cond (XEXP (x, 0), &true0, &false0);
8111 cond1 = if_then_else_cond (XEXP (x, 1), &true1, &false1);
8113 if ((cond0 != 0 || cond1 != 0)
8114 && ! (cond0 != 0 && cond1 != 0 && ! rtx_equal_p (cond0, cond1)))
8116 /* If if_then_else_cond returned zero, then true/false are the
8117 same rtl. We must copy one of them to prevent invalid rtl
8120 true0 = copy_rtx (true0);
8121 else if (cond1 == 0)
8122 true1 = copy_rtx (true1);
8124 if (COMPARISON_P (x))
8126 *ptrue = simplify_gen_relational (code, mode, VOIDmode,
8128 *pfalse = simplify_gen_relational (code, mode, VOIDmode,
8133 *ptrue = simplify_gen_binary (code, mode, true0, true1);
8134 *pfalse = simplify_gen_binary (code, mode, false0, false1);
8137 return cond0 ? cond0 : cond1;
8140 /* See if we have PLUS, IOR, XOR, MINUS or UMAX, where one of the
8141 operands is zero when the other is nonzero, and vice-versa,
8142 and STORE_FLAG_VALUE is 1 or -1. */
8144 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
8145 && (code == PLUS || code == IOR || code == XOR || code == MINUS
8147 && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT)
8149 rtx op0 = XEXP (XEXP (x, 0), 1);
8150 rtx op1 = XEXP (XEXP (x, 1), 1);
8152 cond0 = XEXP (XEXP (x, 0), 0);
8153 cond1 = XEXP (XEXP (x, 1), 0);
8155 if (COMPARISON_P (cond0)
8156 && COMPARISON_P (cond1)
8157 && ((GET_CODE (cond0) == reversed_comparison_code (cond1, NULL)
8158 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0))
8159 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1)))
8160 || ((swap_condition (GET_CODE (cond0))
8161 == reversed_comparison_code (cond1, NULL))
8162 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1))
8163 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0))))
8164 && ! side_effects_p (x))
8166 *ptrue = simplify_gen_binary (MULT, mode, op0, const_true_rtx);
8167 *pfalse = simplify_gen_binary (MULT, mode,
8169 ? simplify_gen_unary (NEG, mode,
8177 /* Similarly for MULT, AND and UMIN, except that for these the result
8179 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
8180 && (code == MULT || code == AND || code == UMIN)
8181 && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT)
8183 cond0 = XEXP (XEXP (x, 0), 0);
8184 cond1 = XEXP (XEXP (x, 1), 0);
8186 if (COMPARISON_P (cond0)
8187 && COMPARISON_P (cond1)
8188 && ((GET_CODE (cond0) == reversed_comparison_code (cond1, NULL)
8189 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0))
8190 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1)))
8191 || ((swap_condition (GET_CODE (cond0))
8192 == reversed_comparison_code (cond1, NULL))
8193 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1))
8194 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0))))
8195 && ! side_effects_p (x))
8197 *ptrue = *pfalse = const0_rtx;
8203 else if (code == IF_THEN_ELSE)
8205 /* If we have IF_THEN_ELSE already, extract the condition and
8206 canonicalize it if it is NE or EQ. */
8207 cond0 = XEXP (x, 0);
8208 *ptrue = XEXP (x, 1), *pfalse = XEXP (x, 2);
8209 if (GET_CODE (cond0) == NE && XEXP (cond0, 1) == const0_rtx)
8210 return XEXP (cond0, 0);
8211 else if (GET_CODE (cond0) == EQ && XEXP (cond0, 1) == const0_rtx)
8213 *ptrue = XEXP (x, 2), *pfalse = XEXP (x, 1);
8214 return XEXP (cond0, 0);
8220 /* If X is a SUBREG, we can narrow both the true and false values
8221 if the inner expression, if there is a condition. */
8222 else if (code == SUBREG
8223 && 0 != (cond0 = if_then_else_cond (SUBREG_REG (x),
8226 true0 = simplify_gen_subreg (mode, true0,
8227 GET_MODE (SUBREG_REG (x)), SUBREG_BYTE (x));
8228 false0 = simplify_gen_subreg (mode, false0,
8229 GET_MODE (SUBREG_REG (x)), SUBREG_BYTE (x));
8230 if (true0 && false0)
8238 /* If X is a constant, this isn't special and will cause confusions
8239 if we treat it as such. Likewise if it is equivalent to a constant. */
8240 else if (CONSTANT_P (x)
8241 || ((cond0 = get_last_value (x)) != 0 && CONSTANT_P (cond0)))
8244 /* If we're in BImode, canonicalize on 0 and STORE_FLAG_VALUE, as that
8245 will be least confusing to the rest of the compiler. */
8246 else if (mode == BImode)
8248 *ptrue = GEN_INT (STORE_FLAG_VALUE), *pfalse = const0_rtx;
8252 /* If X is known to be either 0 or -1, those are the true and
8253 false values when testing X. */
8254 else if (x == constm1_rtx || x == const0_rtx
8255 || (mode != VOIDmode
8256 && num_sign_bit_copies (x, mode) == GET_MODE_BITSIZE (mode)))
8258 *ptrue = constm1_rtx, *pfalse = const0_rtx;
8262 /* Likewise for 0 or a single bit. */
8263 else if (SCALAR_INT_MODE_P (mode)
8264 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
8265 && exact_log2 (nz = nonzero_bits (x, mode)) >= 0)
8267 *ptrue = gen_int_mode (nz, mode), *pfalse = const0_rtx;
8271 /* Otherwise fail; show no condition with true and false values the same. */
8272 *ptrue = *pfalse = x;
8276 /* Return the value of expression X given the fact that condition COND
8277 is known to be true when applied to REG as its first operand and VAL
8278 as its second. X is known to not be shared and so can be modified in
8281 We only handle the simplest cases, and specifically those cases that
8282 arise with IF_THEN_ELSE expressions. */
8285 known_cond (rtx x, enum rtx_code cond, rtx reg, rtx val)
8287 enum rtx_code code = GET_CODE (x);
8292 if (side_effects_p (x))
8295 /* If either operand of the condition is a floating point value,
8296 then we have to avoid collapsing an EQ comparison. */
8298 && rtx_equal_p (x, reg)
8299 && ! FLOAT_MODE_P (GET_MODE (x))
8300 && ! FLOAT_MODE_P (GET_MODE (val)))
8303 if (cond == UNEQ && rtx_equal_p (x, reg))
8306 /* If X is (abs REG) and we know something about REG's relationship
8307 with zero, we may be able to simplify this. */
8309 if (code == ABS && rtx_equal_p (XEXP (x, 0), reg) && val == const0_rtx)
8312 case GE: case GT: case EQ:
8315 return simplify_gen_unary (NEG, GET_MODE (XEXP (x, 0)),
8317 GET_MODE (XEXP (x, 0)));
8322 /* The only other cases we handle are MIN, MAX, and comparisons if the
8323 operands are the same as REG and VAL. */
8325 else if (COMPARISON_P (x) || COMMUTATIVE_ARITH_P (x))
8327 if (rtx_equal_p (XEXP (x, 0), val))
8328 cond = swap_condition (cond), temp = val, val = reg, reg = temp;
8330 if (rtx_equal_p (XEXP (x, 0), reg) && rtx_equal_p (XEXP (x, 1), val))
8332 if (COMPARISON_P (x))
8334 if (comparison_dominates_p (cond, code))
8335 return const_true_rtx;
8337 code = reversed_comparison_code (x, NULL);
8339 && comparison_dominates_p (cond, code))
8344 else if (code == SMAX || code == SMIN
8345 || code == UMIN || code == UMAX)
8347 int unsignedp = (code == UMIN || code == UMAX);
8349 /* Do not reverse the condition when it is NE or EQ.
8350 This is because we cannot conclude anything about
8351 the value of 'SMAX (x, y)' when x is not equal to y,
8352 but we can when x equals y. */
8353 if ((code == SMAX || code == UMAX)
8354 && ! (cond == EQ || cond == NE))
8355 cond = reverse_condition (cond);
8360 return unsignedp ? x : XEXP (x, 1);
8362 return unsignedp ? x : XEXP (x, 0);
8364 return unsignedp ? XEXP (x, 1) : x;
8366 return unsignedp ? XEXP (x, 0) : x;
8373 else if (code == SUBREG)
8375 enum machine_mode inner_mode = GET_MODE (SUBREG_REG (x));
8376 rtx new_rtx, r = known_cond (SUBREG_REG (x), cond, reg, val);
8378 if (SUBREG_REG (x) != r)
8380 /* We must simplify subreg here, before we lose track of the
8381 original inner_mode. */
8382 new_rtx = simplify_subreg (GET_MODE (x), r,
8383 inner_mode, SUBREG_BYTE (x));
8387 SUBST (SUBREG_REG (x), r);
8392 /* We don't have to handle SIGN_EXTEND here, because even in the
8393 case of replacing something with a modeless CONST_INT, a
8394 CONST_INT is already (supposed to be) a valid sign extension for
8395 its narrower mode, which implies it's already properly
8396 sign-extended for the wider mode. Now, for ZERO_EXTEND, the
8397 story is different. */
8398 else if (code == ZERO_EXTEND)
8400 enum machine_mode inner_mode = GET_MODE (XEXP (x, 0));
8401 rtx new_rtx, r = known_cond (XEXP (x, 0), cond, reg, val);
8403 if (XEXP (x, 0) != r)
8405 /* We must simplify the zero_extend here, before we lose
8406 track of the original inner_mode. */
8407 new_rtx = simplify_unary_operation (ZERO_EXTEND, GET_MODE (x),
8412 SUBST (XEXP (x, 0), r);
8418 fmt = GET_RTX_FORMAT (code);
8419 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
8422 SUBST (XEXP (x, i), known_cond (XEXP (x, i), cond, reg, val));
8423 else if (fmt[i] == 'E')
8424 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
8425 SUBST (XVECEXP (x, i, j), known_cond (XVECEXP (x, i, j),
8432 /* See if X and Y are equal for the purposes of seeing if we can rewrite an
8433 assignment as a field assignment. */
8436 rtx_equal_for_field_assignment_p (rtx x, rtx y)
8438 if (x == y || rtx_equal_p (x, y))
8441 if (x == 0 || y == 0 || GET_MODE (x) != GET_MODE (y))
8444 /* Check for a paradoxical SUBREG of a MEM compared with the MEM.
8445 Note that all SUBREGs of MEM are paradoxical; otherwise they
8446 would have been rewritten. */
8447 if (MEM_P (x) && GET_CODE (y) == SUBREG
8448 && MEM_P (SUBREG_REG (y))
8449 && rtx_equal_p (SUBREG_REG (y),
8450 gen_lowpart (GET_MODE (SUBREG_REG (y)), x)))
8453 if (MEM_P (y) && GET_CODE (x) == SUBREG
8454 && MEM_P (SUBREG_REG (x))
8455 && rtx_equal_p (SUBREG_REG (x),
8456 gen_lowpart (GET_MODE (SUBREG_REG (x)), y)))
8459 /* We used to see if get_last_value of X and Y were the same but that's
8460 not correct. In one direction, we'll cause the assignment to have
8461 the wrong destination and in the case, we'll import a register into this
8462 insn that might have already have been dead. So fail if none of the
8463 above cases are true. */
8467 /* See if X, a SET operation, can be rewritten as a bit-field assignment.
8468 Return that assignment if so.
8470 We only handle the most common cases. */
8473 make_field_assignment (rtx x)
8475 rtx dest = SET_DEST (x);
8476 rtx src = SET_SRC (x);
8481 unsigned HOST_WIDE_INT len;
8483 enum machine_mode mode;
8485 /* If SRC was (and (not (ashift (const_int 1) POS)) DEST), this is
8486 a clear of a one-bit field. We will have changed it to
8487 (and (rotate (const_int -2) POS) DEST), so check for that. Also check
8490 if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == ROTATE
8491 && CONST_INT_P (XEXP (XEXP (src, 0), 0))
8492 && INTVAL (XEXP (XEXP (src, 0), 0)) == -2
8493 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
8495 assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1),
8498 return gen_rtx_SET (VOIDmode, assign, const0_rtx);
8502 if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == SUBREG
8503 && subreg_lowpart_p (XEXP (src, 0))
8504 && (GET_MODE_SIZE (GET_MODE (XEXP (src, 0)))
8505 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (src, 0)))))
8506 && GET_CODE (SUBREG_REG (XEXP (src, 0))) == ROTATE
8507 && CONST_INT_P (XEXP (SUBREG_REG (XEXP (src, 0)), 0))
8508 && INTVAL (XEXP (SUBREG_REG (XEXP (src, 0)), 0)) == -2
8509 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
8511 assign = make_extraction (VOIDmode, dest, 0,
8512 XEXP (SUBREG_REG (XEXP (src, 0)), 1),
8515 return gen_rtx_SET (VOIDmode, assign, const0_rtx);
8519 /* If SRC is (ior (ashift (const_int 1) POS) DEST), this is a set of a
8521 if (GET_CODE (src) == IOR && GET_CODE (XEXP (src, 0)) == ASHIFT
8522 && XEXP (XEXP (src, 0), 0) == const1_rtx
8523 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
8525 assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1),
8528 return gen_rtx_SET (VOIDmode, assign, const1_rtx);
8532 /* If DEST is already a field assignment, i.e. ZERO_EXTRACT, and the
8533 SRC is an AND with all bits of that field set, then we can discard
8535 if (GET_CODE (dest) == ZERO_EXTRACT
8536 && CONST_INT_P (XEXP (dest, 1))
8537 && GET_CODE (src) == AND
8538 && CONST_INT_P (XEXP (src, 1)))
8540 HOST_WIDE_INT width = INTVAL (XEXP (dest, 1));
8541 unsigned HOST_WIDE_INT and_mask = INTVAL (XEXP (src, 1));
8542 unsigned HOST_WIDE_INT ze_mask;
8544 if (width >= HOST_BITS_PER_WIDE_INT)
8547 ze_mask = ((unsigned HOST_WIDE_INT)1 << width) - 1;
8549 /* Complete overlap. We can remove the source AND. */
8550 if ((and_mask & ze_mask) == ze_mask)
8551 return gen_rtx_SET (VOIDmode, dest, XEXP (src, 0));
8553 /* Partial overlap. We can reduce the source AND. */
8554 if ((and_mask & ze_mask) != and_mask)
8556 mode = GET_MODE (src);
8557 src = gen_rtx_AND (mode, XEXP (src, 0),
8558 gen_int_mode (and_mask & ze_mask, mode));
8559 return gen_rtx_SET (VOIDmode, dest, src);
8563 /* The other case we handle is assignments into a constant-position
8564 field. They look like (ior/xor (and DEST C1) OTHER). If C1 represents
8565 a mask that has all one bits except for a group of zero bits and
8566 OTHER is known to have zeros where C1 has ones, this is such an
8567 assignment. Compute the position and length from C1. Shift OTHER
8568 to the appropriate position, force it to the required mode, and
8569 make the extraction. Check for the AND in both operands. */
8571 if (GET_CODE (src) != IOR && GET_CODE (src) != XOR)
8574 rhs = expand_compound_operation (XEXP (src, 0));
8575 lhs = expand_compound_operation (XEXP (src, 1));
8577 if (GET_CODE (rhs) == AND
8578 && CONST_INT_P (XEXP (rhs, 1))
8579 && rtx_equal_for_field_assignment_p (XEXP (rhs, 0), dest))
8580 c1 = INTVAL (XEXP (rhs, 1)), other = lhs;
8581 else if (GET_CODE (lhs) == AND
8582 && CONST_INT_P (XEXP (lhs, 1))
8583 && rtx_equal_for_field_assignment_p (XEXP (lhs, 0), dest))
8584 c1 = INTVAL (XEXP (lhs, 1)), other = rhs;
8588 pos = get_pos_from_mask ((~c1) & GET_MODE_MASK (GET_MODE (dest)), &len);
8589 if (pos < 0 || pos + len > GET_MODE_BITSIZE (GET_MODE (dest))
8590 || GET_MODE_BITSIZE (GET_MODE (dest)) > HOST_BITS_PER_WIDE_INT
8591 || (c1 & nonzero_bits (other, GET_MODE (dest))) != 0)
8594 assign = make_extraction (VOIDmode, dest, pos, NULL_RTX, len, 1, 1, 0);
8598 /* The mode to use for the source is the mode of the assignment, or of
8599 what is inside a possible STRICT_LOW_PART. */
8600 mode = (GET_CODE (assign) == STRICT_LOW_PART
8601 ? GET_MODE (XEXP (assign, 0)) : GET_MODE (assign));
8603 /* Shift OTHER right POS places and make it the source, restricting it
8604 to the proper length and mode. */
8606 src = canon_reg_for_combine (simplify_shift_const (NULL_RTX, LSHIFTRT,
8610 src = force_to_mode (src, mode,
8611 GET_MODE_BITSIZE (mode) >= HOST_BITS_PER_WIDE_INT
8612 ? ~(unsigned HOST_WIDE_INT) 0
8613 : ((unsigned HOST_WIDE_INT) 1 << len) - 1,
8616 /* If SRC is masked by an AND that does not make a difference in
8617 the value being stored, strip it. */
8618 if (GET_CODE (assign) == ZERO_EXTRACT
8619 && CONST_INT_P (XEXP (assign, 1))
8620 && INTVAL (XEXP (assign, 1)) < HOST_BITS_PER_WIDE_INT
8621 && GET_CODE (src) == AND
8622 && CONST_INT_P (XEXP (src, 1))
8623 && ((unsigned HOST_WIDE_INT) INTVAL (XEXP (src, 1))
8624 == ((unsigned HOST_WIDE_INT) 1 << INTVAL (XEXP (assign, 1))) - 1))
8625 src = XEXP (src, 0);
8627 return gen_rtx_SET (VOIDmode, assign, src);
8630 /* See if X is of the form (+ (* a c) (* b c)) and convert to (* (+ a b) c)
8634 apply_distributive_law (rtx x)
8636 enum rtx_code code = GET_CODE (x);
8637 enum rtx_code inner_code;
8638 rtx lhs, rhs, other;
8641 /* Distributivity is not true for floating point as it can change the
8642 value. So we don't do it unless -funsafe-math-optimizations. */
8643 if (FLOAT_MODE_P (GET_MODE (x))
8644 && ! flag_unsafe_math_optimizations)
8647 /* The outer operation can only be one of the following: */
8648 if (code != IOR && code != AND && code != XOR
8649 && code != PLUS && code != MINUS)
8655 /* If either operand is a primitive we can't do anything, so get out
8657 if (OBJECT_P (lhs) || OBJECT_P (rhs))
8660 lhs = expand_compound_operation (lhs);
8661 rhs = expand_compound_operation (rhs);
8662 inner_code = GET_CODE (lhs);
8663 if (inner_code != GET_CODE (rhs))
8666 /* See if the inner and outer operations distribute. */
8673 /* These all distribute except over PLUS. */
8674 if (code == PLUS || code == MINUS)
8679 if (code != PLUS && code != MINUS)
8684 /* This is also a multiply, so it distributes over everything. */
8688 /* Non-paradoxical SUBREGs distributes over all operations,
8689 provided the inner modes and byte offsets are the same, this
8690 is an extraction of a low-order part, we don't convert an fp
8691 operation to int or vice versa, this is not a vector mode,
8692 and we would not be converting a single-word operation into a
8693 multi-word operation. The latter test is not required, but
8694 it prevents generating unneeded multi-word operations. Some
8695 of the previous tests are redundant given the latter test,
8696 but are retained because they are required for correctness.
8698 We produce the result slightly differently in this case. */
8700 if (GET_MODE (SUBREG_REG (lhs)) != GET_MODE (SUBREG_REG (rhs))
8701 || SUBREG_BYTE (lhs) != SUBREG_BYTE (rhs)
8702 || ! subreg_lowpart_p (lhs)
8703 || (GET_MODE_CLASS (GET_MODE (lhs))
8704 != GET_MODE_CLASS (GET_MODE (SUBREG_REG (lhs))))
8705 || (GET_MODE_SIZE (GET_MODE (lhs))
8706 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs))))
8707 || VECTOR_MODE_P (GET_MODE (lhs))
8708 || GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs))) > UNITS_PER_WORD
8709 /* Result might need to be truncated. Don't change mode if
8710 explicit truncation is needed. */
8711 || !TRULY_NOOP_TRUNCATION
8712 (GET_MODE_BITSIZE (GET_MODE (x)),
8713 GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (lhs)))))
8716 tem = simplify_gen_binary (code, GET_MODE (SUBREG_REG (lhs)),
8717 SUBREG_REG (lhs), SUBREG_REG (rhs));
8718 return gen_lowpart (GET_MODE (x), tem);
8724 /* Set LHS and RHS to the inner operands (A and B in the example
8725 above) and set OTHER to the common operand (C in the example).
8726 There is only one way to do this unless the inner operation is
8728 if (COMMUTATIVE_ARITH_P (lhs)
8729 && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 0)))
8730 other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 1);
8731 else if (COMMUTATIVE_ARITH_P (lhs)
8732 && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 1)))
8733 other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 0);
8734 else if (COMMUTATIVE_ARITH_P (lhs)
8735 && rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 0)))
8736 other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 1);
8737 else if (rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 1)))
8738 other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 0);
8742 /* Form the new inner operation, seeing if it simplifies first. */
8743 tem = simplify_gen_binary (code, GET_MODE (x), lhs, rhs);
8745 /* There is one exception to the general way of distributing:
8746 (a | c) ^ (b | c) -> (a ^ b) & ~c */
8747 if (code == XOR && inner_code == IOR)
8750 other = simplify_gen_unary (NOT, GET_MODE (x), other, GET_MODE (x));
8753 /* We may be able to continuing distributing the result, so call
8754 ourselves recursively on the inner operation before forming the
8755 outer operation, which we return. */
8756 return simplify_gen_binary (inner_code, GET_MODE (x),
8757 apply_distributive_law (tem), other);
8760 /* See if X is of the form (* (+ A B) C), and if so convert to
8761 (+ (* A C) (* B C)) and try to simplify.
8763 Most of the time, this results in no change. However, if some of
8764 the operands are the same or inverses of each other, simplifications
8767 For example, (and (ior A B) (not B)) can occur as the result of
8768 expanding a bit field assignment. When we apply the distributive
8769 law to this, we get (ior (and (A (not B))) (and (B (not B)))),
8770 which then simplifies to (and (A (not B))).
8772 Note that no checks happen on the validity of applying the inverse
8773 distributive law. This is pointless since we can do it in the
8774 few places where this routine is called.
8776 N is the index of the term that is decomposed (the arithmetic operation,
8777 i.e. (+ A B) in the first example above). !N is the index of the term that
8778 is distributed, i.e. of C in the first example above. */
8780 distribute_and_simplify_rtx (rtx x, int n)
8782 enum machine_mode mode;
8783 enum rtx_code outer_code, inner_code;
8784 rtx decomposed, distributed, inner_op0, inner_op1, new_op0, new_op1, tmp;
8786 /* Distributivity is not true for floating point as it can change the
8787 value. So we don't do it unless -funsafe-math-optimizations. */
8788 if (FLOAT_MODE_P (GET_MODE (x))
8789 && ! flag_unsafe_math_optimizations)
8792 decomposed = XEXP (x, n);
8793 if (!ARITHMETIC_P (decomposed))
8796 mode = GET_MODE (x);
8797 outer_code = GET_CODE (x);
8798 distributed = XEXP (x, !n);
8800 inner_code = GET_CODE (decomposed);
8801 inner_op0 = XEXP (decomposed, 0);
8802 inner_op1 = XEXP (decomposed, 1);
8804 /* Special case (and (xor B C) (not A)), which is equivalent to
8805 (xor (ior A B) (ior A C)) */
8806 if (outer_code == AND && inner_code == XOR && GET_CODE (distributed) == NOT)
8808 distributed = XEXP (distributed, 0);
8814 /* Distribute the second term. */
8815 new_op0 = simplify_gen_binary (outer_code, mode, inner_op0, distributed);
8816 new_op1 = simplify_gen_binary (outer_code, mode, inner_op1, distributed);
8820 /* Distribute the first term. */
8821 new_op0 = simplify_gen_binary (outer_code, mode, distributed, inner_op0);
8822 new_op1 = simplify_gen_binary (outer_code, mode, distributed, inner_op1);
8825 tmp = apply_distributive_law (simplify_gen_binary (inner_code, mode,
8827 if (GET_CODE (tmp) != outer_code
8828 && rtx_cost (tmp, SET, optimize_this_for_speed_p)
8829 < rtx_cost (x, SET, optimize_this_for_speed_p))
8835 /* Simplify a logical `and' of VAROP with the constant CONSTOP, to be done
8836 in MODE. Return an equivalent form, if different from (and VAROP
8837 (const_int CONSTOP)). Otherwise, return NULL_RTX. */
8840 simplify_and_const_int_1 (enum machine_mode mode, rtx varop,
8841 unsigned HOST_WIDE_INT constop)
8843 unsigned HOST_WIDE_INT nonzero;
8844 unsigned HOST_WIDE_INT orig_constop;
8849 orig_constop = constop;
8850 if (GET_CODE (varop) == CLOBBER)
8853 /* Simplify VAROP knowing that we will be only looking at some of the
8856 Note by passing in CONSTOP, we guarantee that the bits not set in
8857 CONSTOP are not significant and will never be examined. We must
8858 ensure that is the case by explicitly masking out those bits
8859 before returning. */
8860 varop = force_to_mode (varop, mode, constop, 0);
8862 /* If VAROP is a CLOBBER, we will fail so return it. */
8863 if (GET_CODE (varop) == CLOBBER)
8866 /* If VAROP is a CONST_INT, then we need to apply the mask in CONSTOP
8867 to VAROP and return the new constant. */
8868 if (CONST_INT_P (varop))
8869 return gen_int_mode (INTVAL (varop) & constop, mode);
8871 /* See what bits may be nonzero in VAROP. Unlike the general case of
8872 a call to nonzero_bits, here we don't care about bits outside
8875 nonzero = nonzero_bits (varop, mode) & GET_MODE_MASK (mode);
8877 /* Turn off all bits in the constant that are known to already be zero.
8878 Thus, if the AND isn't needed at all, we will have CONSTOP == NONZERO_BITS
8879 which is tested below. */
8883 /* If we don't have any bits left, return zero. */
8887 /* If VAROP is a NEG of something known to be zero or 1 and CONSTOP is
8888 a power of two, we can replace this with an ASHIFT. */
8889 if (GET_CODE (varop) == NEG && nonzero_bits (XEXP (varop, 0), mode) == 1
8890 && (i = exact_log2 (constop)) >= 0)
8891 return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (varop, 0), i);
8893 /* If VAROP is an IOR or XOR, apply the AND to both branches of the IOR
8894 or XOR, then try to apply the distributive law. This may eliminate
8895 operations if either branch can be simplified because of the AND.
8896 It may also make some cases more complex, but those cases probably
8897 won't match a pattern either with or without this. */
8899 if (GET_CODE (varop) == IOR || GET_CODE (varop) == XOR)
8903 apply_distributive_law
8904 (simplify_gen_binary (GET_CODE (varop), GET_MODE (varop),
8905 simplify_and_const_int (NULL_RTX,
8909 simplify_and_const_int (NULL_RTX,
8914 /* If VAROP is PLUS, and the constant is a mask of low bits, distribute
8915 the AND and see if one of the operands simplifies to zero. If so, we
8916 may eliminate it. */
8918 if (GET_CODE (varop) == PLUS
8919 && exact_log2 (constop + 1) >= 0)
8923 o0 = simplify_and_const_int (NULL_RTX, mode, XEXP (varop, 0), constop);
8924 o1 = simplify_and_const_int (NULL_RTX, mode, XEXP (varop, 1), constop);
8925 if (o0 == const0_rtx)
8927 if (o1 == const0_rtx)
8931 /* Make a SUBREG if necessary. If we can't make it, fail. */
8932 varop = gen_lowpart (mode, varop);
8933 if (varop == NULL_RTX || GET_CODE (varop) == CLOBBER)
8936 /* If we are only masking insignificant bits, return VAROP. */
8937 if (constop == nonzero)
8940 if (varop == orig_varop && constop == orig_constop)
8943 /* Otherwise, return an AND. */
8944 return simplify_gen_binary (AND, mode, varop, gen_int_mode (constop, mode));
8948 /* We have X, a logical `and' of VAROP with the constant CONSTOP, to be done
8951 Return an equivalent form, if different from X. Otherwise, return X. If
8952 X is zero, we are to always construct the equivalent form. */
8955 simplify_and_const_int (rtx x, enum machine_mode mode, rtx varop,
8956 unsigned HOST_WIDE_INT constop)
8958 rtx tem = simplify_and_const_int_1 (mode, varop, constop);
8963 x = simplify_gen_binary (AND, GET_MODE (varop), varop,
8964 gen_int_mode (constop, mode));
8965 if (GET_MODE (x) != mode)
8966 x = gen_lowpart (mode, x);
8970 /* Given a REG, X, compute which bits in X can be nonzero.
8971 We don't care about bits outside of those defined in MODE.
8973 For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is
8974 a shift, AND, or zero_extract, we can do better. */
8977 reg_nonzero_bits_for_combine (const_rtx x, enum machine_mode mode,
8978 const_rtx known_x ATTRIBUTE_UNUSED,
8979 enum machine_mode known_mode ATTRIBUTE_UNUSED,
8980 unsigned HOST_WIDE_INT known_ret ATTRIBUTE_UNUSED,
8981 unsigned HOST_WIDE_INT *nonzero)
8986 /* If X is a register whose nonzero bits value is current, use it.
8987 Otherwise, if X is a register whose value we can find, use that
8988 value. Otherwise, use the previously-computed global nonzero bits
8989 for this register. */
8991 rsp = VEC_index (reg_stat_type, reg_stat, REGNO (x));
8992 if (rsp->last_set_value != 0
8993 && (rsp->last_set_mode == mode
8994 || (GET_MODE_CLASS (rsp->last_set_mode) == MODE_INT
8995 && GET_MODE_CLASS (mode) == MODE_INT))
8996 && ((rsp->last_set_label >= label_tick_ebb_start
8997 && rsp->last_set_label < label_tick)
8998 || (rsp->last_set_label == label_tick
8999 && DF_INSN_LUID (rsp->last_set) < subst_low_luid)
9000 || (REGNO (x) >= FIRST_PSEUDO_REGISTER
9001 && REG_N_SETS (REGNO (x)) == 1
9003 (DF_LR_IN (ENTRY_BLOCK_PTR->next_bb), REGNO (x)))))
9005 *nonzero &= rsp->last_set_nonzero_bits;
9009 tem = get_last_value (x);
9013 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
9014 /* If X is narrower than MODE and TEM is a non-negative
9015 constant that would appear negative in the mode of X,
9016 sign-extend it for use in reg_nonzero_bits because some
9017 machines (maybe most) will actually do the sign-extension
9018 and this is the conservative approach.
9020 ??? For 2.5, try to tighten up the MD files in this regard
9021 instead of this kludge. */
9023 if (GET_MODE_BITSIZE (GET_MODE (x)) < GET_MODE_BITSIZE (mode)
9024 && CONST_INT_P (tem)
9026 && 0 != (INTVAL (tem)
9027 & ((HOST_WIDE_INT) 1
9028 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
9029 tem = GEN_INT (INTVAL (tem)
9030 | ((HOST_WIDE_INT) (-1)
9031 << GET_MODE_BITSIZE (GET_MODE (x))));
9035 else if (nonzero_sign_valid && rsp->nonzero_bits)
9037 unsigned HOST_WIDE_INT mask = rsp->nonzero_bits;
9039 if (GET_MODE_BITSIZE (GET_MODE (x)) < GET_MODE_BITSIZE (mode))
9040 /* We don't know anything about the upper bits. */
9041 mask |= GET_MODE_MASK (mode) ^ GET_MODE_MASK (GET_MODE (x));
9048 /* Return the number of bits at the high-order end of X that are known to
9049 be equal to the sign bit. X will be used in mode MODE; if MODE is
9050 VOIDmode, X will be used in its own mode. The returned value will always
9051 be between 1 and the number of bits in MODE. */
9054 reg_num_sign_bit_copies_for_combine (const_rtx x, enum machine_mode mode,
9055 const_rtx known_x ATTRIBUTE_UNUSED,
9056 enum machine_mode known_mode
9058 unsigned int known_ret ATTRIBUTE_UNUSED,
9059 unsigned int *result)
9064 rsp = VEC_index (reg_stat_type, reg_stat, REGNO (x));
9065 if (rsp->last_set_value != 0
9066 && rsp->last_set_mode == mode
9067 && ((rsp->last_set_label >= label_tick_ebb_start
9068 && rsp->last_set_label < label_tick)
9069 || (rsp->last_set_label == label_tick
9070 && DF_INSN_LUID (rsp->last_set) < subst_low_luid)
9071 || (REGNO (x) >= FIRST_PSEUDO_REGISTER
9072 && REG_N_SETS (REGNO (x)) == 1
9074 (DF_LR_IN (ENTRY_BLOCK_PTR->next_bb), REGNO (x)))))
9076 *result = rsp->last_set_sign_bit_copies;
9080 tem = get_last_value (x);
9084 if (nonzero_sign_valid && rsp->sign_bit_copies != 0
9085 && GET_MODE_BITSIZE (GET_MODE (x)) == GET_MODE_BITSIZE (mode))
9086 *result = rsp->sign_bit_copies;
9091 /* Return the number of "extended" bits there are in X, when interpreted
9092 as a quantity in MODE whose signedness is indicated by UNSIGNEDP. For
9093 unsigned quantities, this is the number of high-order zero bits.
9094 For signed quantities, this is the number of copies of the sign bit
9095 minus 1. In both case, this function returns the number of "spare"
9096 bits. For example, if two quantities for which this function returns
9097 at least 1 are added, the addition is known not to overflow.
9099 This function will always return 0 unless called during combine, which
9100 implies that it must be called from a define_split. */
9103 extended_count (const_rtx x, enum machine_mode mode, int unsignedp)
9105 if (nonzero_sign_valid == 0)
9109 ? (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
9110 ? (unsigned int) (GET_MODE_BITSIZE (mode) - 1
9111 - floor_log2 (nonzero_bits (x, mode)))
9113 : num_sign_bit_copies (x, mode) - 1);
9116 /* This function is called from `simplify_shift_const' to merge two
9117 outer operations. Specifically, we have already found that we need
9118 to perform operation *POP0 with constant *PCONST0 at the outermost
9119 position. We would now like to also perform OP1 with constant CONST1
9120 (with *POP0 being done last).
9122 Return 1 if we can do the operation and update *POP0 and *PCONST0 with
9123 the resulting operation. *PCOMP_P is set to 1 if we would need to
9124 complement the innermost operand, otherwise it is unchanged.
9126 MODE is the mode in which the operation will be done. No bits outside
9127 the width of this mode matter. It is assumed that the width of this mode
9128 is smaller than or equal to HOST_BITS_PER_WIDE_INT.
9130 If *POP0 or OP1 are UNKNOWN, it means no operation is required. Only NEG, PLUS,
9131 IOR, XOR, and AND are supported. We may set *POP0 to SET if the proper
9132 result is simply *PCONST0.
9134 If the resulting operation cannot be expressed as one operation, we
9135 return 0 and do not change *POP0, *PCONST0, and *PCOMP_P. */
9138 merge_outer_ops (enum rtx_code *pop0, HOST_WIDE_INT *pconst0, enum rtx_code op1, HOST_WIDE_INT const1, enum machine_mode mode, int *pcomp_p)
9140 enum rtx_code op0 = *pop0;
9141 HOST_WIDE_INT const0 = *pconst0;
9143 const0 &= GET_MODE_MASK (mode);
9144 const1 &= GET_MODE_MASK (mode);
9146 /* If OP0 is an AND, clear unimportant bits in CONST1. */
9150 /* If OP0 or OP1 is UNKNOWN, this is easy. Similarly if they are the same or
9153 if (op1 == UNKNOWN || op0 == SET)
9156 else if (op0 == UNKNOWN)
9157 op0 = op1, const0 = const1;
9159 else if (op0 == op1)
9183 /* Otherwise, if either is a PLUS or NEG, we can't do anything. */
9184 else if (op0 == PLUS || op1 == PLUS || op0 == NEG || op1 == NEG)
9187 /* If the two constants aren't the same, we can't do anything. The
9188 remaining six cases can all be done. */
9189 else if (const0 != const1)
9197 /* (a & b) | b == b */
9199 else /* op1 == XOR */
9200 /* (a ^ b) | b == a | b */
9206 /* (a & b) ^ b == (~a) & b */
9207 op0 = AND, *pcomp_p = 1;
9208 else /* op1 == IOR */
9209 /* (a | b) ^ b == a & ~b */
9210 op0 = AND, const0 = ~const0;
9215 /* (a | b) & b == b */
9217 else /* op1 == XOR */
9218 /* (a ^ b) & b) == (~a) & b */
9225 /* Check for NO-OP cases. */
9226 const0 &= GET_MODE_MASK (mode);
9228 && (op0 == IOR || op0 == XOR || op0 == PLUS))
9230 else if (const0 == 0 && op0 == AND)
9232 else if ((unsigned HOST_WIDE_INT) const0 == GET_MODE_MASK (mode)
9238 /* ??? Slightly redundant with the above mask, but not entirely.
9239 Moving this above means we'd have to sign-extend the mode mask
9240 for the final test. */
9241 if (op0 != UNKNOWN && op0 != NEG)
9242 *pconst0 = trunc_int_for_mode (const0, mode);
9247 /* A helper to simplify_shift_const_1 to determine the mode we can perform
9248 the shift in. The original shift operation CODE is performed on OP in
9249 ORIG_MODE. Return the wider mode MODE if we can perform the operation
9250 in that mode. Return ORIG_MODE otherwise. We can also assume that the
9251 result of the shift is subject to operation OUTER_CODE with operand
9254 static enum machine_mode
9255 try_widen_shift_mode (enum rtx_code code, rtx op, int count,
9256 enum machine_mode orig_mode, enum machine_mode mode,
9257 enum rtx_code outer_code, HOST_WIDE_INT outer_const)
9259 if (orig_mode == mode)
9261 gcc_assert (GET_MODE_BITSIZE (mode) > GET_MODE_BITSIZE (orig_mode));
9263 /* In general we can't perform in wider mode for right shift and rotate. */
9267 /* We can still widen if the bits brought in from the left are identical
9268 to the sign bit of ORIG_MODE. */
9269 if (num_sign_bit_copies (op, mode)
9270 > (unsigned) (GET_MODE_BITSIZE (mode)
9271 - GET_MODE_BITSIZE (orig_mode)))
9276 /* Similarly here but with zero bits. */
9277 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
9278 && (nonzero_bits (op, mode) & ~GET_MODE_MASK (orig_mode)) == 0)
9281 /* We can also widen if the bits brought in will be masked off. This
9282 operation is performed in ORIG_MODE. */
9283 if (outer_code == AND)
9285 int care_bits = low_bitmask_len (orig_mode, outer_const);
9288 && GET_MODE_BITSIZE (orig_mode) - care_bits >= count)
9304 /* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift.
9305 The result of the shift is RESULT_MODE. Return NULL_RTX if we cannot
9306 simplify it. Otherwise, return a simplified value.
9308 The shift is normally computed in the widest mode we find in VAROP, as
9309 long as it isn't a different number of words than RESULT_MODE. Exceptions
9310 are ASHIFTRT and ROTATE, which are always done in their original mode. */
9313 simplify_shift_const_1 (enum rtx_code code, enum machine_mode result_mode,
9314 rtx varop, int orig_count)
9316 enum rtx_code orig_code = code;
9317 rtx orig_varop = varop;
9319 enum machine_mode mode = result_mode;
9320 enum machine_mode shift_mode, tmode;
9321 unsigned int mode_words
9322 = (GET_MODE_SIZE (mode) + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD;
9323 /* We form (outer_op (code varop count) (outer_const)). */
9324 enum rtx_code outer_op = UNKNOWN;
9325 HOST_WIDE_INT outer_const = 0;
9326 int complement_p = 0;
9329 /* Make sure and truncate the "natural" shift on the way in. We don't
9330 want to do this inside the loop as it makes it more difficult to
9332 if (SHIFT_COUNT_TRUNCATED)
9333 orig_count &= GET_MODE_BITSIZE (mode) - 1;
9335 /* If we were given an invalid count, don't do anything except exactly
9336 what was requested. */
9338 if (orig_count < 0 || orig_count >= (int) GET_MODE_BITSIZE (mode))
9343 /* Unless one of the branches of the `if' in this loop does a `continue',
9344 we will `break' the loop after the `if'. */
9348 /* If we have an operand of (clobber (const_int 0)), fail. */
9349 if (GET_CODE (varop) == CLOBBER)
9352 /* Convert ROTATERT to ROTATE. */
9353 if (code == ROTATERT)
9355 unsigned int bitsize = GET_MODE_BITSIZE (result_mode);;
9357 if (VECTOR_MODE_P (result_mode))
9358 count = bitsize / GET_MODE_NUNITS (result_mode) - count;
9360 count = bitsize - count;
9363 shift_mode = try_widen_shift_mode (code, varop, count, result_mode,
9364 mode, outer_op, outer_const);
9366 /* Handle cases where the count is greater than the size of the mode
9367 minus 1. For ASHIFT, use the size minus one as the count (this can
9368 occur when simplifying (lshiftrt (ashiftrt ..))). For rotates,
9369 take the count modulo the size. For other shifts, the result is
9372 Since these shifts are being produced by the compiler by combining
9373 multiple operations, each of which are defined, we know what the
9374 result is supposed to be. */
9376 if (count > (GET_MODE_BITSIZE (shift_mode) - 1))
9378 if (code == ASHIFTRT)
9379 count = GET_MODE_BITSIZE (shift_mode) - 1;
9380 else if (code == ROTATE || code == ROTATERT)
9381 count %= GET_MODE_BITSIZE (shift_mode);
9384 /* We can't simply return zero because there may be an
9392 /* If we discovered we had to complement VAROP, leave. Making a NOT
9393 here would cause an infinite loop. */
9397 /* An arithmetic right shift of a quantity known to be -1 or 0
9399 if (code == ASHIFTRT
9400 && (num_sign_bit_copies (varop, shift_mode)
9401 == GET_MODE_BITSIZE (shift_mode)))
9407 /* If we are doing an arithmetic right shift and discarding all but
9408 the sign bit copies, this is equivalent to doing a shift by the
9409 bitsize minus one. Convert it into that shift because it will often
9410 allow other simplifications. */
9412 if (code == ASHIFTRT
9413 && (count + num_sign_bit_copies (varop, shift_mode)
9414 >= GET_MODE_BITSIZE (shift_mode)))
9415 count = GET_MODE_BITSIZE (shift_mode) - 1;
9417 /* We simplify the tests below and elsewhere by converting
9418 ASHIFTRT to LSHIFTRT if we know the sign bit is clear.
9419 `make_compound_operation' will convert it to an ASHIFTRT for
9420 those machines (such as VAX) that don't have an LSHIFTRT. */
9421 if (GET_MODE_BITSIZE (shift_mode) <= HOST_BITS_PER_WIDE_INT
9423 && ((nonzero_bits (varop, shift_mode)
9424 & ((HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (shift_mode) - 1)))
9428 if (((code == LSHIFTRT
9429 && GET_MODE_BITSIZE (shift_mode) <= HOST_BITS_PER_WIDE_INT
9430 && !(nonzero_bits (varop, shift_mode) >> count))
9432 && GET_MODE_BITSIZE (shift_mode) <= HOST_BITS_PER_WIDE_INT
9433 && !((nonzero_bits (varop, shift_mode) << count)
9434 & GET_MODE_MASK (shift_mode))))
9435 && !side_effects_p (varop))
9438 switch (GET_CODE (varop))
9444 new_rtx = expand_compound_operation (varop);
9445 if (new_rtx != varop)
9453 /* If we have (xshiftrt (mem ...) C) and C is MODE_WIDTH
9454 minus the width of a smaller mode, we can do this with a
9455 SIGN_EXTEND or ZERO_EXTEND from the narrower memory location. */
9456 if ((code == ASHIFTRT || code == LSHIFTRT)
9457 && ! mode_dependent_address_p (XEXP (varop, 0))
9458 && ! MEM_VOLATILE_P (varop)
9459 && (tmode = mode_for_size (GET_MODE_BITSIZE (mode) - count,
9460 MODE_INT, 1)) != BLKmode)
9462 new_rtx = adjust_address_nv (varop, tmode,
9463 BYTES_BIG_ENDIAN ? 0
9464 : count / BITS_PER_UNIT);
9466 varop = gen_rtx_fmt_e (code == ASHIFTRT ? SIGN_EXTEND
9467 : ZERO_EXTEND, mode, new_rtx);
9474 /* If VAROP is a SUBREG, strip it as long as the inner operand has
9475 the same number of words as what we've seen so far. Then store
9476 the widest mode in MODE. */
9477 if (subreg_lowpart_p (varop)
9478 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop)))
9479 > GET_MODE_SIZE (GET_MODE (varop)))
9480 && (unsigned int) ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop)))
9481 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
9484 varop = SUBREG_REG (varop);
9485 if (GET_MODE_SIZE (GET_MODE (varop)) > GET_MODE_SIZE (mode))
9486 mode = GET_MODE (varop);
9492 /* Some machines use MULT instead of ASHIFT because MULT
9493 is cheaper. But it is still better on those machines to
9494 merge two shifts into one. */
9495 if (CONST_INT_P (XEXP (varop, 1))
9496 && exact_log2 (INTVAL (XEXP (varop, 1))) >= 0)
9499 = simplify_gen_binary (ASHIFT, GET_MODE (varop),
9501 GEN_INT (exact_log2 (
9502 INTVAL (XEXP (varop, 1)))));
9508 /* Similar, for when divides are cheaper. */
9509 if (CONST_INT_P (XEXP (varop, 1))
9510 && exact_log2 (INTVAL (XEXP (varop, 1))) >= 0)
9513 = simplify_gen_binary (LSHIFTRT, GET_MODE (varop),
9515 GEN_INT (exact_log2 (
9516 INTVAL (XEXP (varop, 1)))));
9522 /* If we are extracting just the sign bit of an arithmetic
9523 right shift, that shift is not needed. However, the sign
9524 bit of a wider mode may be different from what would be
9525 interpreted as the sign bit in a narrower mode, so, if
9526 the result is narrower, don't discard the shift. */
9527 if (code == LSHIFTRT
9528 && count == (GET_MODE_BITSIZE (result_mode) - 1)
9529 && (GET_MODE_BITSIZE (result_mode)
9530 >= GET_MODE_BITSIZE (GET_MODE (varop))))
9532 varop = XEXP (varop, 0);
9536 /* ... fall through ... */
9541 /* Here we have two nested shifts. The result is usually the
9542 AND of a new shift with a mask. We compute the result below. */
9543 if (CONST_INT_P (XEXP (varop, 1))
9544 && INTVAL (XEXP (varop, 1)) >= 0
9545 && INTVAL (XEXP (varop, 1)) < GET_MODE_BITSIZE (GET_MODE (varop))
9546 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
9547 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
9548 && !VECTOR_MODE_P (result_mode))
9550 enum rtx_code first_code = GET_CODE (varop);
9551 unsigned int first_count = INTVAL (XEXP (varop, 1));
9552 unsigned HOST_WIDE_INT mask;
9555 /* We have one common special case. We can't do any merging if
9556 the inner code is an ASHIFTRT of a smaller mode. However, if
9557 we have (ashift:M1 (subreg:M1 (ashiftrt:M2 FOO C1) 0) C2)
9558 with C2 == GET_MODE_BITSIZE (M1) - GET_MODE_BITSIZE (M2),
9559 we can convert it to
9560 (ashiftrt:M1 (ashift:M1 (and:M1 (subreg:M1 FOO 0 C2) C3) C1).
9561 This simplifies certain SIGN_EXTEND operations. */
9562 if (code == ASHIFT && first_code == ASHIFTRT
9563 && count == (GET_MODE_BITSIZE (result_mode)
9564 - GET_MODE_BITSIZE (GET_MODE (varop))))
9566 /* C3 has the low-order C1 bits zero. */
9568 mask = (GET_MODE_MASK (mode)
9569 & ~(((HOST_WIDE_INT) 1 << first_count) - 1));
9571 varop = simplify_and_const_int (NULL_RTX, result_mode,
9572 XEXP (varop, 0), mask);
9573 varop = simplify_shift_const (NULL_RTX, ASHIFT, result_mode,
9575 count = first_count;
9580 /* If this was (ashiftrt (ashift foo C1) C2) and FOO has more
9581 than C1 high-order bits equal to the sign bit, we can convert
9582 this to either an ASHIFT or an ASHIFTRT depending on the
9585 We cannot do this if VAROP's mode is not SHIFT_MODE. */
9587 if (code == ASHIFTRT && first_code == ASHIFT
9588 && GET_MODE (varop) == shift_mode
9589 && (num_sign_bit_copies (XEXP (varop, 0), shift_mode)
9592 varop = XEXP (varop, 0);
9593 count -= first_count;
9603 /* There are some cases we can't do. If CODE is ASHIFTRT,
9604 we can only do this if FIRST_CODE is also ASHIFTRT.
9606 We can't do the case when CODE is ROTATE and FIRST_CODE is
9609 If the mode of this shift is not the mode of the outer shift,
9610 we can't do this if either shift is a right shift or ROTATE.
9612 Finally, we can't do any of these if the mode is too wide
9613 unless the codes are the same.
9615 Handle the case where the shift codes are the same
9618 if (code == first_code)
9620 if (GET_MODE (varop) != result_mode
9621 && (code == ASHIFTRT || code == LSHIFTRT
9625 count += first_count;
9626 varop = XEXP (varop, 0);
9630 if (code == ASHIFTRT
9631 || (code == ROTATE && first_code == ASHIFTRT)
9632 || GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT
9633 || (GET_MODE (varop) != result_mode
9634 && (first_code == ASHIFTRT || first_code == LSHIFTRT
9635 || first_code == ROTATE
9636 || code == ROTATE)))
9639 /* To compute the mask to apply after the shift, shift the
9640 nonzero bits of the inner shift the same way the
9641 outer shift will. */
9643 mask_rtx = GEN_INT (nonzero_bits (varop, GET_MODE (varop)));
9646 = simplify_const_binary_operation (code, result_mode, mask_rtx,
9649 /* Give up if we can't compute an outer operation to use. */
9651 || !CONST_INT_P (mask_rtx)
9652 || ! merge_outer_ops (&outer_op, &outer_const, AND,
9654 result_mode, &complement_p))
9657 /* If the shifts are in the same direction, we add the
9658 counts. Otherwise, we subtract them. */
9659 if ((code == ASHIFTRT || code == LSHIFTRT)
9660 == (first_code == ASHIFTRT || first_code == LSHIFTRT))
9661 count += first_count;
9663 count -= first_count;
9665 /* If COUNT is positive, the new shift is usually CODE,
9666 except for the two exceptions below, in which case it is
9667 FIRST_CODE. If the count is negative, FIRST_CODE should
9670 && ((first_code == ROTATE && code == ASHIFT)
9671 || (first_code == ASHIFTRT && code == LSHIFTRT)))
9674 code = first_code, count = -count;
9676 varop = XEXP (varop, 0);
9680 /* If we have (A << B << C) for any shift, we can convert this to
9681 (A << C << B). This wins if A is a constant. Only try this if
9682 B is not a constant. */
9684 else if (GET_CODE (varop) == code
9685 && CONST_INT_P (XEXP (varop, 0))
9686 && !CONST_INT_P (XEXP (varop, 1)))
9688 rtx new_rtx = simplify_const_binary_operation (code, mode,
9691 varop = gen_rtx_fmt_ee (code, mode, new_rtx, XEXP (varop, 1));
9698 if (VECTOR_MODE_P (mode))
9701 /* Make this fit the case below. */
9702 varop = gen_rtx_XOR (mode, XEXP (varop, 0),
9703 GEN_INT (GET_MODE_MASK (mode)));
9709 /* If we have (xshiftrt (ior (plus X (const_int -1)) X) C)
9710 with C the size of VAROP - 1 and the shift is logical if
9711 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
9712 we have an (le X 0) operation. If we have an arithmetic shift
9713 and STORE_FLAG_VALUE is 1 or we have a logical shift with
9714 STORE_FLAG_VALUE of -1, we have a (neg (le X 0)) operation. */
9716 if (GET_CODE (varop) == IOR && GET_CODE (XEXP (varop, 0)) == PLUS
9717 && XEXP (XEXP (varop, 0), 1) == constm1_rtx
9718 && (STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
9719 && (code == LSHIFTRT || code == ASHIFTRT)
9720 && count == (GET_MODE_BITSIZE (GET_MODE (varop)) - 1)
9721 && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
9724 varop = gen_rtx_LE (GET_MODE (varop), XEXP (varop, 1),
9727 if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
9728 varop = gen_rtx_NEG (GET_MODE (varop), varop);
9733 /* If we have (shift (logical)), move the logical to the outside
9734 to allow it to possibly combine with another logical and the
9735 shift to combine with another shift. This also canonicalizes to
9736 what a ZERO_EXTRACT looks like. Also, some machines have
9737 (and (shift)) insns. */
9739 if (CONST_INT_P (XEXP (varop, 1))
9740 /* We can't do this if we have (ashiftrt (xor)) and the
9741 constant has its sign bit set in shift_mode. */
9742 && !(code == ASHIFTRT && GET_CODE (varop) == XOR
9743 && 0 > trunc_int_for_mode (INTVAL (XEXP (varop, 1)),
9745 && (new_rtx = simplify_const_binary_operation (code, result_mode,
9747 GEN_INT (count))) != 0
9748 && CONST_INT_P (new_rtx)
9749 && merge_outer_ops (&outer_op, &outer_const, GET_CODE (varop),
9750 INTVAL (new_rtx), result_mode, &complement_p))
9752 varop = XEXP (varop, 0);
9756 /* If we can't do that, try to simplify the shift in each arm of the
9757 logical expression, make a new logical expression, and apply
9758 the inverse distributive law. This also can't be done
9759 for some (ashiftrt (xor)). */
9760 if (CONST_INT_P (XEXP (varop, 1))
9761 && !(code == ASHIFTRT && GET_CODE (varop) == XOR
9762 && 0 > trunc_int_for_mode (INTVAL (XEXP (varop, 1)),
9765 rtx lhs = simplify_shift_const (NULL_RTX, code, shift_mode,
9766 XEXP (varop, 0), count);
9767 rtx rhs = simplify_shift_const (NULL_RTX, code, shift_mode,
9768 XEXP (varop, 1), count);
9770 varop = simplify_gen_binary (GET_CODE (varop), shift_mode,
9772 varop = apply_distributive_law (varop);
9780 /* Convert (lshiftrt (eq FOO 0) C) to (xor FOO 1) if STORE_FLAG_VALUE
9781 says that the sign bit can be tested, FOO has mode MODE, C is
9782 GET_MODE_BITSIZE (MODE) - 1, and FOO has only its low-order bit
9783 that may be nonzero. */
9784 if (code == LSHIFTRT
9785 && XEXP (varop, 1) == const0_rtx
9786 && GET_MODE (XEXP (varop, 0)) == result_mode
9787 && count == (GET_MODE_BITSIZE (result_mode) - 1)
9788 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
9789 && STORE_FLAG_VALUE == -1
9790 && nonzero_bits (XEXP (varop, 0), result_mode) == 1
9791 && merge_outer_ops (&outer_op, &outer_const, XOR,
9792 (HOST_WIDE_INT) 1, result_mode,
9795 varop = XEXP (varop, 0);
9802 /* (lshiftrt (neg A) C) where A is either 0 or 1 and C is one less
9803 than the number of bits in the mode is equivalent to A. */
9804 if (code == LSHIFTRT
9805 && count == (GET_MODE_BITSIZE (result_mode) - 1)
9806 && nonzero_bits (XEXP (varop, 0), result_mode) == 1)
9808 varop = XEXP (varop, 0);
9813 /* NEG commutes with ASHIFT since it is multiplication. Move the
9814 NEG outside to allow shifts to combine. */
9816 && merge_outer_ops (&outer_op, &outer_const, NEG,
9817 (HOST_WIDE_INT) 0, result_mode,
9820 varop = XEXP (varop, 0);
9826 /* (lshiftrt (plus A -1) C) where A is either 0 or 1 and C
9827 is one less than the number of bits in the mode is
9828 equivalent to (xor A 1). */
9829 if (code == LSHIFTRT
9830 && count == (GET_MODE_BITSIZE (result_mode) - 1)
9831 && XEXP (varop, 1) == constm1_rtx
9832 && nonzero_bits (XEXP (varop, 0), result_mode) == 1
9833 && merge_outer_ops (&outer_op, &outer_const, XOR,
9834 (HOST_WIDE_INT) 1, result_mode,
9838 varop = XEXP (varop, 0);
9842 /* If we have (xshiftrt (plus FOO BAR) C), and the only bits
9843 that might be nonzero in BAR are those being shifted out and those
9844 bits are known zero in FOO, we can replace the PLUS with FOO.
9845 Similarly in the other operand order. This code occurs when
9846 we are computing the size of a variable-size array. */
9848 if ((code == ASHIFTRT || code == LSHIFTRT)
9849 && count < HOST_BITS_PER_WIDE_INT
9850 && nonzero_bits (XEXP (varop, 1), result_mode) >> count == 0
9851 && (nonzero_bits (XEXP (varop, 1), result_mode)
9852 & nonzero_bits (XEXP (varop, 0), result_mode)) == 0)
9854 varop = XEXP (varop, 0);
9857 else if ((code == ASHIFTRT || code == LSHIFTRT)
9858 && count < HOST_BITS_PER_WIDE_INT
9859 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
9860 && 0 == (nonzero_bits (XEXP (varop, 0), result_mode)
9862 && 0 == (nonzero_bits (XEXP (varop, 0), result_mode)
9863 & nonzero_bits (XEXP (varop, 1),
9866 varop = XEXP (varop, 1);
9870 /* (ashift (plus foo C) N) is (plus (ashift foo N) C'). */
9872 && CONST_INT_P (XEXP (varop, 1))
9873 && (new_rtx = simplify_const_binary_operation (ASHIFT, result_mode,
9875 GEN_INT (count))) != 0
9876 && CONST_INT_P (new_rtx)
9877 && merge_outer_ops (&outer_op, &outer_const, PLUS,
9878 INTVAL (new_rtx), result_mode, &complement_p))
9880 varop = XEXP (varop, 0);
9884 /* Check for 'PLUS signbit', which is the canonical form of 'XOR
9885 signbit', and attempt to change the PLUS to an XOR and move it to
9886 the outer operation as is done above in the AND/IOR/XOR case
9887 leg for shift(logical). See details in logical handling above
9888 for reasoning in doing so. */
9889 if (code == LSHIFTRT
9890 && CONST_INT_P (XEXP (varop, 1))
9891 && mode_signbit_p (result_mode, XEXP (varop, 1))
9892 && (new_rtx = simplify_const_binary_operation (code, result_mode,
9894 GEN_INT (count))) != 0
9895 && CONST_INT_P (new_rtx)
9896 && merge_outer_ops (&outer_op, &outer_const, XOR,
9897 INTVAL (new_rtx), result_mode, &complement_p))
9899 varop = XEXP (varop, 0);
9906 /* If we have (xshiftrt (minus (ashiftrt X C)) X) C)
9907 with C the size of VAROP - 1 and the shift is logical if
9908 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
9909 we have a (gt X 0) operation. If the shift is arithmetic with
9910 STORE_FLAG_VALUE of 1 or logical with STORE_FLAG_VALUE == -1,
9911 we have a (neg (gt X 0)) operation. */
9913 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
9914 && GET_CODE (XEXP (varop, 0)) == ASHIFTRT
9915 && count == (GET_MODE_BITSIZE (GET_MODE (varop)) - 1)
9916 && (code == LSHIFTRT || code == ASHIFTRT)
9917 && CONST_INT_P (XEXP (XEXP (varop, 0), 1))
9918 && INTVAL (XEXP (XEXP (varop, 0), 1)) == count
9919 && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
9922 varop = gen_rtx_GT (GET_MODE (varop), XEXP (varop, 1),
9925 if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
9926 varop = gen_rtx_NEG (GET_MODE (varop), varop);
9933 /* Change (lshiftrt (truncate (lshiftrt))) to (truncate (lshiftrt))
9934 if the truncate does not affect the value. */
9935 if (code == LSHIFTRT
9936 && GET_CODE (XEXP (varop, 0)) == LSHIFTRT
9937 && CONST_INT_P (XEXP (XEXP (varop, 0), 1))
9938 && (INTVAL (XEXP (XEXP (varop, 0), 1))
9939 >= (GET_MODE_BITSIZE (GET_MODE (XEXP (varop, 0)))
9940 - GET_MODE_BITSIZE (GET_MODE (varop)))))
9942 rtx varop_inner = XEXP (varop, 0);
9945 = gen_rtx_LSHIFTRT (GET_MODE (varop_inner),
9946 XEXP (varop_inner, 0),
9948 (count + INTVAL (XEXP (varop_inner, 1))));
9949 varop = gen_rtx_TRUNCATE (GET_MODE (varop), varop_inner);
9962 shift_mode = try_widen_shift_mode (code, varop, count, result_mode, mode,
9963 outer_op, outer_const);
9965 /* We have now finished analyzing the shift. The result should be
9966 a shift of type CODE with SHIFT_MODE shifting VAROP COUNT places. If
9967 OUTER_OP is non-UNKNOWN, it is an operation that needs to be applied
9968 to the result of the shift. OUTER_CONST is the relevant constant,
9969 but we must turn off all bits turned off in the shift. */
9971 if (outer_op == UNKNOWN
9972 && orig_code == code && orig_count == count
9973 && varop == orig_varop
9974 && shift_mode == GET_MODE (varop))
9977 /* Make a SUBREG if necessary. If we can't make it, fail. */
9978 varop = gen_lowpart (shift_mode, varop);
9979 if (varop == NULL_RTX || GET_CODE (varop) == CLOBBER)
9982 /* If we have an outer operation and we just made a shift, it is
9983 possible that we could have simplified the shift were it not
9984 for the outer operation. So try to do the simplification
9987 if (outer_op != UNKNOWN)
9988 x = simplify_shift_const_1 (code, shift_mode, varop, count);
9993 x = simplify_gen_binary (code, shift_mode, varop, GEN_INT (count));
9995 /* If we were doing an LSHIFTRT in a wider mode than it was originally,
9996 turn off all the bits that the shift would have turned off. */
9997 if (orig_code == LSHIFTRT && result_mode != shift_mode)
9998 x = simplify_and_const_int (NULL_RTX, shift_mode, x,
9999 GET_MODE_MASK (result_mode) >> orig_count);
10001 /* Do the remainder of the processing in RESULT_MODE. */
10002 x = gen_lowpart_or_truncate (result_mode, x);
10004 /* If COMPLEMENT_P is set, we have to complement X before doing the outer
10007 x = simplify_gen_unary (NOT, result_mode, x, result_mode);
10009 if (outer_op != UNKNOWN)
10011 if (GET_RTX_CLASS (outer_op) != RTX_UNARY
10012 && GET_MODE_BITSIZE (result_mode) < HOST_BITS_PER_WIDE_INT)
10013 outer_const = trunc_int_for_mode (outer_const, result_mode);
10015 if (outer_op == AND)
10016 x = simplify_and_const_int (NULL_RTX, result_mode, x, outer_const);
10017 else if (outer_op == SET)
10019 /* This means that we have determined that the result is
10020 equivalent to a constant. This should be rare. */
10021 if (!side_effects_p (x))
10022 x = GEN_INT (outer_const);
10024 else if (GET_RTX_CLASS (outer_op) == RTX_UNARY)
10025 x = simplify_gen_unary (outer_op, result_mode, x, result_mode);
10027 x = simplify_gen_binary (outer_op, result_mode, x,
10028 GEN_INT (outer_const));
10034 /* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift.
10035 The result of the shift is RESULT_MODE. If we cannot simplify it,
10036 return X or, if it is NULL, synthesize the expression with
10037 simplify_gen_binary. Otherwise, return a simplified value.
10039 The shift is normally computed in the widest mode we find in VAROP, as
10040 long as it isn't a different number of words than RESULT_MODE. Exceptions
10041 are ASHIFTRT and ROTATE, which are always done in their original mode. */
10044 simplify_shift_const (rtx x, enum rtx_code code, enum machine_mode result_mode,
10045 rtx varop, int count)
10047 rtx tem = simplify_shift_const_1 (code, result_mode, varop, count);
10052 x = simplify_gen_binary (code, GET_MODE (varop), varop, GEN_INT (count));
10053 if (GET_MODE (x) != result_mode)
10054 x = gen_lowpart (result_mode, x);
10059 /* Like recog, but we receive the address of a pointer to a new pattern.
10060 We try to match the rtx that the pointer points to.
10061 If that fails, we may try to modify or replace the pattern,
10062 storing the replacement into the same pointer object.
10064 Modifications include deletion or addition of CLOBBERs.
10066 PNOTES is a pointer to a location where any REG_UNUSED notes added for
10067 the CLOBBERs are placed.
10069 The value is the final insn code from the pattern ultimately matched,
10073 recog_for_combine (rtx *pnewpat, rtx insn, rtx *pnotes)
10075 rtx pat = *pnewpat;
10076 int insn_code_number;
10077 int num_clobbers_to_add = 0;
10080 rtx old_notes, old_pat;
10082 /* If PAT is a PARALLEL, check to see if it contains the CLOBBER
10083 we use to indicate that something didn't match. If we find such a
10084 thing, force rejection. */
10085 if (GET_CODE (pat) == PARALLEL)
10086 for (i = XVECLEN (pat, 0) - 1; i >= 0; i--)
10087 if (GET_CODE (XVECEXP (pat, 0, i)) == CLOBBER
10088 && XEXP (XVECEXP (pat, 0, i), 0) == const0_rtx)
10091 old_pat = PATTERN (insn);
10092 old_notes = REG_NOTES (insn);
10093 PATTERN (insn) = pat;
10094 REG_NOTES (insn) = 0;
10096 insn_code_number = recog (pat, insn, &num_clobbers_to_add);
10097 if (dump_file && (dump_flags & TDF_DETAILS))
10099 if (insn_code_number < 0)
10100 fputs ("Failed to match this instruction:\n", dump_file);
10102 fputs ("Successfully matched this instruction:\n", dump_file);
10103 print_rtl_single (dump_file, pat);
10106 /* If it isn't, there is the possibility that we previously had an insn
10107 that clobbered some register as a side effect, but the combined
10108 insn doesn't need to do that. So try once more without the clobbers
10109 unless this represents an ASM insn. */
10111 if (insn_code_number < 0 && ! check_asm_operands (pat)
10112 && GET_CODE (pat) == PARALLEL)
10116 for (pos = 0, i = 0; i < XVECLEN (pat, 0); i++)
10117 if (GET_CODE (XVECEXP (pat, 0, i)) != CLOBBER)
10120 SUBST (XVECEXP (pat, 0, pos), XVECEXP (pat, 0, i));
10124 SUBST_INT (XVECLEN (pat, 0), pos);
10127 pat = XVECEXP (pat, 0, 0);
10129 PATTERN (insn) = pat;
10130 insn_code_number = recog (pat, insn, &num_clobbers_to_add);
10131 if (dump_file && (dump_flags & TDF_DETAILS))
10133 if (insn_code_number < 0)
10134 fputs ("Failed to match this instruction:\n", dump_file);
10136 fputs ("Successfully matched this instruction:\n", dump_file);
10137 print_rtl_single (dump_file, pat);
10140 PATTERN (insn) = old_pat;
10141 REG_NOTES (insn) = old_notes;
10143 /* Recognize all noop sets, these will be killed by followup pass. */
10144 if (insn_code_number < 0 && GET_CODE (pat) == SET && set_noop_p (pat))
10145 insn_code_number = NOOP_MOVE_INSN_CODE, num_clobbers_to_add = 0;
10147 /* If we had any clobbers to add, make a new pattern than contains
10148 them. Then check to make sure that all of them are dead. */
10149 if (num_clobbers_to_add)
10151 rtx newpat = gen_rtx_PARALLEL (VOIDmode,
10152 rtvec_alloc (GET_CODE (pat) == PARALLEL
10153 ? (XVECLEN (pat, 0)
10154 + num_clobbers_to_add)
10155 : num_clobbers_to_add + 1));
10157 if (GET_CODE (pat) == PARALLEL)
10158 for (i = 0; i < XVECLEN (pat, 0); i++)
10159 XVECEXP (newpat, 0, i) = XVECEXP (pat, 0, i);
10161 XVECEXP (newpat, 0, 0) = pat;
10163 add_clobbers (newpat, insn_code_number);
10165 for (i = XVECLEN (newpat, 0) - num_clobbers_to_add;
10166 i < XVECLEN (newpat, 0); i++)
10168 if (REG_P (XEXP (XVECEXP (newpat, 0, i), 0))
10169 && ! reg_dead_at_p (XEXP (XVECEXP (newpat, 0, i), 0), insn))
10171 if (GET_CODE (XEXP (XVECEXP (newpat, 0, i), 0)) != SCRATCH)
10173 gcc_assert (REG_P (XEXP (XVECEXP (newpat, 0, i), 0)));
10174 notes = alloc_reg_note (REG_UNUSED,
10175 XEXP (XVECEXP (newpat, 0, i), 0), notes);
10184 return insn_code_number;
10187 /* Like gen_lowpart_general but for use by combine. In combine it
10188 is not possible to create any new pseudoregs. However, it is
10189 safe to create invalid memory addresses, because combine will
10190 try to recognize them and all they will do is make the combine
10193 If for some reason this cannot do its job, an rtx
10194 (clobber (const_int 0)) is returned.
10195 An insn containing that will not be recognized. */
10198 gen_lowpart_for_combine (enum machine_mode omode, rtx x)
10200 enum machine_mode imode = GET_MODE (x);
10201 unsigned int osize = GET_MODE_SIZE (omode);
10202 unsigned int isize = GET_MODE_SIZE (imode);
10205 if (omode == imode)
10208 /* Return identity if this is a CONST or symbolic reference. */
10210 && (GET_CODE (x) == CONST
10211 || GET_CODE (x) == SYMBOL_REF
10212 || GET_CODE (x) == LABEL_REF))
10215 /* We can only support MODE being wider than a word if X is a
10216 constant integer or has a mode the same size. */
10217 if (GET_MODE_SIZE (omode) > UNITS_PER_WORD
10218 && ! ((imode == VOIDmode
10219 && (CONST_INT_P (x)
10220 || GET_CODE (x) == CONST_DOUBLE))
10221 || isize == osize))
10224 /* X might be a paradoxical (subreg (mem)). In that case, gen_lowpart
10225 won't know what to do. So we will strip off the SUBREG here and
10226 process normally. */
10227 if (GET_CODE (x) == SUBREG && MEM_P (SUBREG_REG (x)))
10229 x = SUBREG_REG (x);
10231 /* For use in case we fall down into the address adjustments
10232 further below, we need to adjust the known mode and size of
10233 x; imode and isize, since we just adjusted x. */
10234 imode = GET_MODE (x);
10236 if (imode == omode)
10239 isize = GET_MODE_SIZE (imode);
10242 result = gen_lowpart_common (omode, x);
10251 /* Refuse to work on a volatile memory ref or one with a mode-dependent
10253 if (MEM_VOLATILE_P (x) || mode_dependent_address_p (XEXP (x, 0)))
10256 /* If we want to refer to something bigger than the original memref,
10257 generate a paradoxical subreg instead. That will force a reload
10258 of the original memref X. */
10260 return gen_rtx_SUBREG (omode, x, 0);
10262 if (WORDS_BIG_ENDIAN)
10263 offset = MAX (isize, UNITS_PER_WORD) - MAX (osize, UNITS_PER_WORD);
10265 /* Adjust the address so that the address-after-the-data is
10267 if (BYTES_BIG_ENDIAN)
10268 offset -= MIN (UNITS_PER_WORD, osize) - MIN (UNITS_PER_WORD, isize);
10270 return adjust_address_nv (x, omode, offset);
10273 /* If X is a comparison operator, rewrite it in a new mode. This
10274 probably won't match, but may allow further simplifications. */
10275 else if (COMPARISON_P (x))
10276 return gen_rtx_fmt_ee (GET_CODE (x), omode, XEXP (x, 0), XEXP (x, 1));
10278 /* If we couldn't simplify X any other way, just enclose it in a
10279 SUBREG. Normally, this SUBREG won't match, but some patterns may
10280 include an explicit SUBREG or we may simplify it further in combine. */
10286 offset = subreg_lowpart_offset (omode, imode);
10287 if (imode == VOIDmode)
10289 imode = int_mode_for_mode (omode);
10290 x = gen_lowpart_common (imode, x);
10294 res = simplify_gen_subreg (omode, x, imode, offset);
10300 return gen_rtx_CLOBBER (omode, const0_rtx);
10303 /* Simplify a comparison between *POP0 and *POP1 where CODE is the
10304 comparison code that will be tested.
10306 The result is a possibly different comparison code to use. *POP0 and
10307 *POP1 may be updated.
10309 It is possible that we might detect that a comparison is either always
10310 true or always false. However, we do not perform general constant
10311 folding in combine, so this knowledge isn't useful. Such tautologies
10312 should have been detected earlier. Hence we ignore all such cases. */
10314 static enum rtx_code
10315 simplify_comparison (enum rtx_code code, rtx *pop0, rtx *pop1)
10321 enum machine_mode mode, tmode;
10323 /* Try a few ways of applying the same transformation to both operands. */
10326 #ifndef WORD_REGISTER_OPERATIONS
10327 /* The test below this one won't handle SIGN_EXTENDs on these machines,
10328 so check specially. */
10329 if (code != GTU && code != GEU && code != LTU && code != LEU
10330 && GET_CODE (op0) == ASHIFTRT && GET_CODE (op1) == ASHIFTRT
10331 && GET_CODE (XEXP (op0, 0)) == ASHIFT
10332 && GET_CODE (XEXP (op1, 0)) == ASHIFT
10333 && GET_CODE (XEXP (XEXP (op0, 0), 0)) == SUBREG
10334 && GET_CODE (XEXP (XEXP (op1, 0), 0)) == SUBREG
10335 && (GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0)))
10336 == GET_MODE (SUBREG_REG (XEXP (XEXP (op1, 0), 0))))
10337 && CONST_INT_P (XEXP (op0, 1))
10338 && XEXP (op0, 1) == XEXP (op1, 1)
10339 && XEXP (op0, 1) == XEXP (XEXP (op0, 0), 1)
10340 && XEXP (op0, 1) == XEXP (XEXP (op1, 0), 1)
10341 && (INTVAL (XEXP (op0, 1))
10342 == (GET_MODE_BITSIZE (GET_MODE (op0))
10343 - (GET_MODE_BITSIZE
10344 (GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0))))))))
10346 op0 = SUBREG_REG (XEXP (XEXP (op0, 0), 0));
10347 op1 = SUBREG_REG (XEXP (XEXP (op1, 0), 0));
10351 /* If both operands are the same constant shift, see if we can ignore the
10352 shift. We can if the shift is a rotate or if the bits shifted out of
10353 this shift are known to be zero for both inputs and if the type of
10354 comparison is compatible with the shift. */
10355 if (GET_CODE (op0) == GET_CODE (op1)
10356 && GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
10357 && ((GET_CODE (op0) == ROTATE && (code == NE || code == EQ))
10358 || ((GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFT)
10359 && (code != GT && code != LT && code != GE && code != LE))
10360 || (GET_CODE (op0) == ASHIFTRT
10361 && (code != GTU && code != LTU
10362 && code != GEU && code != LEU)))
10363 && CONST_INT_P (XEXP (op0, 1))
10364 && INTVAL (XEXP (op0, 1)) >= 0
10365 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT
10366 && XEXP (op0, 1) == XEXP (op1, 1))
10368 enum machine_mode mode = GET_MODE (op0);
10369 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
10370 int shift_count = INTVAL (XEXP (op0, 1));
10372 if (GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFTRT)
10373 mask &= (mask >> shift_count) << shift_count;
10374 else if (GET_CODE (op0) == ASHIFT)
10375 mask = (mask & (mask << shift_count)) >> shift_count;
10377 if ((nonzero_bits (XEXP (op0, 0), mode) & ~mask) == 0
10378 && (nonzero_bits (XEXP (op1, 0), mode) & ~mask) == 0)
10379 op0 = XEXP (op0, 0), op1 = XEXP (op1, 0);
10384 /* If both operands are AND's of a paradoxical SUBREG by constant, the
10385 SUBREGs are of the same mode, and, in both cases, the AND would
10386 be redundant if the comparison was done in the narrower mode,
10387 do the comparison in the narrower mode (e.g., we are AND'ing with 1
10388 and the operand's possibly nonzero bits are 0xffffff01; in that case
10389 if we only care about QImode, we don't need the AND). This case
10390 occurs if the output mode of an scc insn is not SImode and
10391 STORE_FLAG_VALUE == 1 (e.g., the 386).
10393 Similarly, check for a case where the AND's are ZERO_EXTEND
10394 operations from some narrower mode even though a SUBREG is not
10397 else if (GET_CODE (op0) == AND && GET_CODE (op1) == AND
10398 && CONST_INT_P (XEXP (op0, 1))
10399 && CONST_INT_P (XEXP (op1, 1)))
10401 rtx inner_op0 = XEXP (op0, 0);
10402 rtx inner_op1 = XEXP (op1, 0);
10403 HOST_WIDE_INT c0 = INTVAL (XEXP (op0, 1));
10404 HOST_WIDE_INT c1 = INTVAL (XEXP (op1, 1));
10407 if (GET_CODE (inner_op0) == SUBREG && GET_CODE (inner_op1) == SUBREG
10408 && (GET_MODE_SIZE (GET_MODE (inner_op0))
10409 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (inner_op0))))
10410 && (GET_MODE (SUBREG_REG (inner_op0))
10411 == GET_MODE (SUBREG_REG (inner_op1)))
10412 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (inner_op0)))
10413 <= HOST_BITS_PER_WIDE_INT)
10414 && (0 == ((~c0) & nonzero_bits (SUBREG_REG (inner_op0),
10415 GET_MODE (SUBREG_REG (inner_op0)))))
10416 && (0 == ((~c1) & nonzero_bits (SUBREG_REG (inner_op1),
10417 GET_MODE (SUBREG_REG (inner_op1))))))
10419 op0 = SUBREG_REG (inner_op0);
10420 op1 = SUBREG_REG (inner_op1);
10422 /* The resulting comparison is always unsigned since we masked
10423 off the original sign bit. */
10424 code = unsigned_condition (code);
10430 for (tmode = GET_CLASS_NARROWEST_MODE
10431 (GET_MODE_CLASS (GET_MODE (op0)));
10432 tmode != GET_MODE (op0); tmode = GET_MODE_WIDER_MODE (tmode))
10433 if ((unsigned HOST_WIDE_INT) c0 == GET_MODE_MASK (tmode))
10435 op0 = gen_lowpart (tmode, inner_op0);
10436 op1 = gen_lowpart (tmode, inner_op1);
10437 code = unsigned_condition (code);
10446 /* If both operands are NOT, we can strip off the outer operation
10447 and adjust the comparison code for swapped operands; similarly for
10448 NEG, except that this must be an equality comparison. */
10449 else if ((GET_CODE (op0) == NOT && GET_CODE (op1) == NOT)
10450 || (GET_CODE (op0) == NEG && GET_CODE (op1) == NEG
10451 && (code == EQ || code == NE)))
10452 op0 = XEXP (op0, 0), op1 = XEXP (op1, 0), code = swap_condition (code);
10458 /* If the first operand is a constant, swap the operands and adjust the
10459 comparison code appropriately, but don't do this if the second operand
10460 is already a constant integer. */
10461 if (swap_commutative_operands_p (op0, op1))
10463 tem = op0, op0 = op1, op1 = tem;
10464 code = swap_condition (code);
10467 /* We now enter a loop during which we will try to simplify the comparison.
10468 For the most part, we only are concerned with comparisons with zero,
10469 but some things may really be comparisons with zero but not start
10470 out looking that way. */
10472 while (CONST_INT_P (op1))
10474 enum machine_mode mode = GET_MODE (op0);
10475 unsigned int mode_width = GET_MODE_BITSIZE (mode);
10476 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
10477 int equality_comparison_p;
10478 int sign_bit_comparison_p;
10479 int unsigned_comparison_p;
10480 HOST_WIDE_INT const_op;
10482 /* We only want to handle integral modes. This catches VOIDmode,
10483 CCmode, and the floating-point modes. An exception is that we
10484 can handle VOIDmode if OP0 is a COMPARE or a comparison
10487 if (GET_MODE_CLASS (mode) != MODE_INT
10488 && ! (mode == VOIDmode
10489 && (GET_CODE (op0) == COMPARE || COMPARISON_P (op0))))
10492 /* Get the constant we are comparing against and turn off all bits
10493 not on in our mode. */
10494 const_op = INTVAL (op1);
10495 if (mode != VOIDmode)
10496 const_op = trunc_int_for_mode (const_op, mode);
10497 op1 = GEN_INT (const_op);
10499 /* If we are comparing against a constant power of two and the value
10500 being compared can only have that single bit nonzero (e.g., it was
10501 `and'ed with that bit), we can replace this with a comparison
10504 && (code == EQ || code == NE || code == GE || code == GEU
10505 || code == LT || code == LTU)
10506 && mode_width <= HOST_BITS_PER_WIDE_INT
10507 && exact_log2 (const_op) >= 0
10508 && nonzero_bits (op0, mode) == (unsigned HOST_WIDE_INT) const_op)
10510 code = (code == EQ || code == GE || code == GEU ? NE : EQ);
10511 op1 = const0_rtx, const_op = 0;
10514 /* Similarly, if we are comparing a value known to be either -1 or
10515 0 with -1, change it to the opposite comparison against zero. */
10518 && (code == EQ || code == NE || code == GT || code == LE
10519 || code == GEU || code == LTU)
10520 && num_sign_bit_copies (op0, mode) == mode_width)
10522 code = (code == EQ || code == LE || code == GEU ? NE : EQ);
10523 op1 = const0_rtx, const_op = 0;
10526 /* Do some canonicalizations based on the comparison code. We prefer
10527 comparisons against zero and then prefer equality comparisons.
10528 If we can reduce the size of a constant, we will do that too. */
10533 /* < C is equivalent to <= (C - 1) */
10537 op1 = GEN_INT (const_op);
10539 /* ... fall through to LE case below. */
10545 /* <= C is equivalent to < (C + 1); we do this for C < 0 */
10549 op1 = GEN_INT (const_op);
10553 /* If we are doing a <= 0 comparison on a value known to have
10554 a zero sign bit, we can replace this with == 0. */
10555 else if (const_op == 0
10556 && mode_width <= HOST_BITS_PER_WIDE_INT
10557 && (nonzero_bits (op0, mode)
10558 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)
10563 /* >= C is equivalent to > (C - 1). */
10567 op1 = GEN_INT (const_op);
10569 /* ... fall through to GT below. */
10575 /* > C is equivalent to >= (C + 1); we do this for C < 0. */
10579 op1 = GEN_INT (const_op);
10583 /* If we are doing a > 0 comparison on a value known to have
10584 a zero sign bit, we can replace this with != 0. */
10585 else if (const_op == 0
10586 && mode_width <= HOST_BITS_PER_WIDE_INT
10587 && (nonzero_bits (op0, mode)
10588 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)
10593 /* < C is equivalent to <= (C - 1). */
10597 op1 = GEN_INT (const_op);
10599 /* ... fall through ... */
10602 /* (unsigned) < 0x80000000 is equivalent to >= 0. */
10603 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
10604 && (const_op == (HOST_WIDE_INT) 1 << (mode_width - 1)))
10606 const_op = 0, op1 = const0_rtx;
10614 /* unsigned <= 0 is equivalent to == 0 */
10618 /* (unsigned) <= 0x7fffffff is equivalent to >= 0. */
10619 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
10620 && (const_op == ((HOST_WIDE_INT) 1 << (mode_width - 1)) - 1))
10622 const_op = 0, op1 = const0_rtx;
10628 /* >= C is equivalent to > (C - 1). */
10632 op1 = GEN_INT (const_op);
10634 /* ... fall through ... */
10637 /* (unsigned) >= 0x80000000 is equivalent to < 0. */
10638 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
10639 && (const_op == (HOST_WIDE_INT) 1 << (mode_width - 1)))
10641 const_op = 0, op1 = const0_rtx;
10649 /* unsigned > 0 is equivalent to != 0 */
10653 /* (unsigned) > 0x7fffffff is equivalent to < 0. */
10654 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
10655 && (const_op == ((HOST_WIDE_INT) 1 << (mode_width - 1)) - 1))
10657 const_op = 0, op1 = const0_rtx;
10666 /* Compute some predicates to simplify code below. */
10668 equality_comparison_p = (code == EQ || code == NE);
10669 sign_bit_comparison_p = ((code == LT || code == GE) && const_op == 0);
10670 unsigned_comparison_p = (code == LTU || code == LEU || code == GTU
10673 /* If this is a sign bit comparison and we can do arithmetic in
10674 MODE, say that we will only be needing the sign bit of OP0. */
10675 if (sign_bit_comparison_p
10676 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
10677 op0 = force_to_mode (op0, mode,
10679 << (GET_MODE_BITSIZE (mode) - 1)),
10682 /* Now try cases based on the opcode of OP0. If none of the cases
10683 does a "continue", we exit this loop immediately after the
10686 switch (GET_CODE (op0))
10689 /* If we are extracting a single bit from a variable position in
10690 a constant that has only a single bit set and are comparing it
10691 with zero, we can convert this into an equality comparison
10692 between the position and the location of the single bit. */
10693 /* Except we can't if SHIFT_COUNT_TRUNCATED is set, since we might
10694 have already reduced the shift count modulo the word size. */
10695 if (!SHIFT_COUNT_TRUNCATED
10696 && CONST_INT_P (XEXP (op0, 0))
10697 && XEXP (op0, 1) == const1_rtx
10698 && equality_comparison_p && const_op == 0
10699 && (i = exact_log2 (INTVAL (XEXP (op0, 0)))) >= 0)
10701 if (BITS_BIG_ENDIAN)
10703 enum machine_mode new_mode
10704 = mode_for_extraction (EP_extzv, 1);
10705 if (new_mode == MAX_MACHINE_MODE)
10706 i = BITS_PER_WORD - 1 - i;
10710 i = (GET_MODE_BITSIZE (mode) - 1 - i);
10714 op0 = XEXP (op0, 2);
10718 /* Result is nonzero iff shift count is equal to I. */
10719 code = reverse_condition (code);
10723 /* ... fall through ... */
10726 tem = expand_compound_operation (op0);
10735 /* If testing for equality, we can take the NOT of the constant. */
10736 if (equality_comparison_p
10737 && (tem = simplify_unary_operation (NOT, mode, op1, mode)) != 0)
10739 op0 = XEXP (op0, 0);
10744 /* If just looking at the sign bit, reverse the sense of the
10746 if (sign_bit_comparison_p)
10748 op0 = XEXP (op0, 0);
10749 code = (code == GE ? LT : GE);
10755 /* If testing for equality, we can take the NEG of the constant. */
10756 if (equality_comparison_p
10757 && (tem = simplify_unary_operation (NEG, mode, op1, mode)) != 0)
10759 op0 = XEXP (op0, 0);
10764 /* The remaining cases only apply to comparisons with zero. */
10768 /* When X is ABS or is known positive,
10769 (neg X) is < 0 if and only if X != 0. */
10771 if (sign_bit_comparison_p
10772 && (GET_CODE (XEXP (op0, 0)) == ABS
10773 || (mode_width <= HOST_BITS_PER_WIDE_INT
10774 && (nonzero_bits (XEXP (op0, 0), mode)
10775 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)))
10777 op0 = XEXP (op0, 0);
10778 code = (code == LT ? NE : EQ);
10782 /* If we have NEG of something whose two high-order bits are the
10783 same, we know that "(-a) < 0" is equivalent to "a > 0". */
10784 if (num_sign_bit_copies (op0, mode) >= 2)
10786 op0 = XEXP (op0, 0);
10787 code = swap_condition (code);
10793 /* If we are testing equality and our count is a constant, we
10794 can perform the inverse operation on our RHS. */
10795 if (equality_comparison_p && CONST_INT_P (XEXP (op0, 1))
10796 && (tem = simplify_binary_operation (ROTATERT, mode,
10797 op1, XEXP (op0, 1))) != 0)
10799 op0 = XEXP (op0, 0);
10804 /* If we are doing a < 0 or >= 0 comparison, it means we are testing
10805 a particular bit. Convert it to an AND of a constant of that
10806 bit. This will be converted into a ZERO_EXTRACT. */
10807 if (const_op == 0 && sign_bit_comparison_p
10808 && CONST_INT_P (XEXP (op0, 1))
10809 && mode_width <= HOST_BITS_PER_WIDE_INT)
10811 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
10814 - INTVAL (XEXP (op0, 1)))));
10815 code = (code == LT ? NE : EQ);
10819 /* Fall through. */
10822 /* ABS is ignorable inside an equality comparison with zero. */
10823 if (const_op == 0 && equality_comparison_p)
10825 op0 = XEXP (op0, 0);
10831 /* Can simplify (compare (zero/sign_extend FOO) CONST) to
10832 (compare FOO CONST) if CONST fits in FOO's mode and we
10833 are either testing inequality or have an unsigned
10834 comparison with ZERO_EXTEND or a signed comparison with
10835 SIGN_EXTEND. But don't do it if we don't have a compare
10836 insn of the given mode, since we'd have to revert it
10837 later on, and then we wouldn't know whether to sign- or
10839 mode = GET_MODE (XEXP (op0, 0));
10840 if (mode != VOIDmode && GET_MODE_CLASS (mode) == MODE_INT
10841 && ! unsigned_comparison_p
10842 && (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
10843 && ((unsigned HOST_WIDE_INT) const_op
10844 < (((unsigned HOST_WIDE_INT) 1
10845 << (GET_MODE_BITSIZE (mode) - 1))))
10846 && have_insn_for (COMPARE, mode))
10848 op0 = XEXP (op0, 0);
10854 /* Check for the case where we are comparing A - C1 with C2, that is
10856 (subreg:MODE (plus (A) (-C1))) op (C2)
10858 with C1 a constant, and try to lift the SUBREG, i.e. to do the
10859 comparison in the wider mode. One of the following two conditions
10860 must be true in order for this to be valid:
10862 1. The mode extension results in the same bit pattern being added
10863 on both sides and the comparison is equality or unsigned. As
10864 C2 has been truncated to fit in MODE, the pattern can only be
10867 2. The mode extension results in the sign bit being copied on
10870 The difficulty here is that we have predicates for A but not for
10871 (A - C1) so we need to check that C1 is within proper bounds so
10872 as to perturbate A as little as possible. */
10874 if (mode_width <= HOST_BITS_PER_WIDE_INT
10875 && subreg_lowpart_p (op0)
10876 && GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0))) > mode_width
10877 && GET_CODE (SUBREG_REG (op0)) == PLUS
10878 && CONST_INT_P (XEXP (SUBREG_REG (op0), 1)))
10880 enum machine_mode inner_mode = GET_MODE (SUBREG_REG (op0));
10881 rtx a = XEXP (SUBREG_REG (op0), 0);
10882 HOST_WIDE_INT c1 = -INTVAL (XEXP (SUBREG_REG (op0), 1));
10885 && (unsigned HOST_WIDE_INT) c1
10886 < (unsigned HOST_WIDE_INT) 1 << (mode_width - 1)
10887 && (equality_comparison_p || unsigned_comparison_p)
10888 /* (A - C1) zero-extends if it is positive and sign-extends
10889 if it is negative, C2 both zero- and sign-extends. */
10890 && ((0 == (nonzero_bits (a, inner_mode)
10891 & ~GET_MODE_MASK (mode))
10893 /* (A - C1) sign-extends if it is positive and 1-extends
10894 if it is negative, C2 both sign- and 1-extends. */
10895 || (num_sign_bit_copies (a, inner_mode)
10896 > (unsigned int) (GET_MODE_BITSIZE (inner_mode)
10899 || ((unsigned HOST_WIDE_INT) c1
10900 < (unsigned HOST_WIDE_INT) 1 << (mode_width - 2)
10901 /* (A - C1) always sign-extends, like C2. */
10902 && num_sign_bit_copies (a, inner_mode)
10903 > (unsigned int) (GET_MODE_BITSIZE (inner_mode)
10904 - (mode_width - 1))))
10906 op0 = SUBREG_REG (op0);
10911 /* If the inner mode is narrower and we are extracting the low part,
10912 we can treat the SUBREG as if it were a ZERO_EXTEND. */
10913 if (subreg_lowpart_p (op0)
10914 && GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0))) < mode_width)
10915 /* Fall through */ ;
10919 /* ... fall through ... */
10922 mode = GET_MODE (XEXP (op0, 0));
10923 if (mode != VOIDmode && GET_MODE_CLASS (mode) == MODE_INT
10924 && (unsigned_comparison_p || equality_comparison_p)
10925 && (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
10926 && ((unsigned HOST_WIDE_INT) const_op < GET_MODE_MASK (mode))
10927 && have_insn_for (COMPARE, mode))
10929 op0 = XEXP (op0, 0);
10935 /* (eq (plus X A) B) -> (eq X (minus B A)). We can only do
10936 this for equality comparisons due to pathological cases involving
10938 if (equality_comparison_p
10939 && 0 != (tem = simplify_binary_operation (MINUS, mode,
10940 op1, XEXP (op0, 1))))
10942 op0 = XEXP (op0, 0);
10947 /* (plus (abs X) (const_int -1)) is < 0 if and only if X == 0. */
10948 if (const_op == 0 && XEXP (op0, 1) == constm1_rtx
10949 && GET_CODE (XEXP (op0, 0)) == ABS && sign_bit_comparison_p)
10951 op0 = XEXP (XEXP (op0, 0), 0);
10952 code = (code == LT ? EQ : NE);
10958 /* We used to optimize signed comparisons against zero, but that
10959 was incorrect. Unsigned comparisons against zero (GTU, LEU)
10960 arrive here as equality comparisons, or (GEU, LTU) are
10961 optimized away. No need to special-case them. */
10963 /* (eq (minus A B) C) -> (eq A (plus B C)) or
10964 (eq B (minus A C)), whichever simplifies. We can only do
10965 this for equality comparisons due to pathological cases involving
10967 if (equality_comparison_p
10968 && 0 != (tem = simplify_binary_operation (PLUS, mode,
10969 XEXP (op0, 1), op1)))
10971 op0 = XEXP (op0, 0);
10976 if (equality_comparison_p
10977 && 0 != (tem = simplify_binary_operation (MINUS, mode,
10978 XEXP (op0, 0), op1)))
10980 op0 = XEXP (op0, 1);
10985 /* The sign bit of (minus (ashiftrt X C) X), where C is the number
10986 of bits in X minus 1, is one iff X > 0. */
10987 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == ASHIFTRT
10988 && CONST_INT_P (XEXP (XEXP (op0, 0), 1))
10989 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (XEXP (op0, 0), 1))
10991 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
10993 op0 = XEXP (op0, 1);
10994 code = (code == GE ? LE : GT);
11000 /* (eq (xor A B) C) -> (eq A (xor B C)). This is a simplification
11001 if C is zero or B is a constant. */
11002 if (equality_comparison_p
11003 && 0 != (tem = simplify_binary_operation (XOR, mode,
11004 XEXP (op0, 1), op1)))
11006 op0 = XEXP (op0, 0);
11013 case UNEQ: case LTGT:
11014 case LT: case LTU: case UNLT: case LE: case LEU: case UNLE:
11015 case GT: case GTU: case UNGT: case GE: case GEU: case UNGE:
11016 case UNORDERED: case ORDERED:
11017 /* We can't do anything if OP0 is a condition code value, rather
11018 than an actual data value. */
11020 || CC0_P (XEXP (op0, 0))
11021 || GET_MODE_CLASS (GET_MODE (XEXP (op0, 0))) == MODE_CC)
11024 /* Get the two operands being compared. */
11025 if (GET_CODE (XEXP (op0, 0)) == COMPARE)
11026 tem = XEXP (XEXP (op0, 0), 0), tem1 = XEXP (XEXP (op0, 0), 1);
11028 tem = XEXP (op0, 0), tem1 = XEXP (op0, 1);
11030 /* Check for the cases where we simply want the result of the
11031 earlier test or the opposite of that result. */
11032 if (code == NE || code == EQ
11033 || (GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
11034 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
11035 && (STORE_FLAG_VALUE
11036 & (((HOST_WIDE_INT) 1
11037 << (GET_MODE_BITSIZE (GET_MODE (op0)) - 1))))
11038 && (code == LT || code == GE)))
11040 enum rtx_code new_code;
11041 if (code == LT || code == NE)
11042 new_code = GET_CODE (op0);
11044 new_code = reversed_comparison_code (op0, NULL);
11046 if (new_code != UNKNOWN)
11057 /* The sign bit of (ior (plus X (const_int -1)) X) is nonzero
11059 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == PLUS
11060 && XEXP (XEXP (op0, 0), 1) == constm1_rtx
11061 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
11063 op0 = XEXP (op0, 1);
11064 code = (code == GE ? GT : LE);
11070 /* Convert (and (xshift 1 X) Y) to (and (lshiftrt Y X) 1). This
11071 will be converted to a ZERO_EXTRACT later. */
11072 if (const_op == 0 && equality_comparison_p
11073 && GET_CODE (XEXP (op0, 0)) == ASHIFT
11074 && XEXP (XEXP (op0, 0), 0) == const1_rtx)
11076 op0 = simplify_and_const_int
11077 (NULL_RTX, mode, gen_rtx_LSHIFTRT (mode,
11079 XEXP (XEXP (op0, 0), 1)),
11080 (HOST_WIDE_INT) 1);
11084 /* If we are comparing (and (lshiftrt X C1) C2) for equality with
11085 zero and X is a comparison and C1 and C2 describe only bits set
11086 in STORE_FLAG_VALUE, we can compare with X. */
11087 if (const_op == 0 && equality_comparison_p
11088 && mode_width <= HOST_BITS_PER_WIDE_INT
11089 && CONST_INT_P (XEXP (op0, 1))
11090 && GET_CODE (XEXP (op0, 0)) == LSHIFTRT
11091 && CONST_INT_P (XEXP (XEXP (op0, 0), 1))
11092 && INTVAL (XEXP (XEXP (op0, 0), 1)) >= 0
11093 && INTVAL (XEXP (XEXP (op0, 0), 1)) < HOST_BITS_PER_WIDE_INT)
11095 mask = ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
11096 << INTVAL (XEXP (XEXP (op0, 0), 1)));
11097 if ((~STORE_FLAG_VALUE & mask) == 0
11098 && (COMPARISON_P (XEXP (XEXP (op0, 0), 0))
11099 || ((tem = get_last_value (XEXP (XEXP (op0, 0), 0))) != 0
11100 && COMPARISON_P (tem))))
11102 op0 = XEXP (XEXP (op0, 0), 0);
11107 /* If we are doing an equality comparison of an AND of a bit equal
11108 to the sign bit, replace this with a LT or GE comparison of
11109 the underlying value. */
11110 if (equality_comparison_p
11112 && CONST_INT_P (XEXP (op0, 1))
11113 && mode_width <= HOST_BITS_PER_WIDE_INT
11114 && ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
11115 == (unsigned HOST_WIDE_INT) 1 << (mode_width - 1)))
11117 op0 = XEXP (op0, 0);
11118 code = (code == EQ ? GE : LT);
11122 /* If this AND operation is really a ZERO_EXTEND from a narrower
11123 mode, the constant fits within that mode, and this is either an
11124 equality or unsigned comparison, try to do this comparison in
11129 (ne:DI (and:DI (reg:DI 4) (const_int 0xffffffff)) (const_int 0))
11130 -> (ne:DI (reg:SI 4) (const_int 0))
11132 unless TRULY_NOOP_TRUNCATION allows it or the register is
11133 known to hold a value of the required mode the
11134 transformation is invalid. */
11135 if ((equality_comparison_p || unsigned_comparison_p)
11136 && CONST_INT_P (XEXP (op0, 1))
11137 && (i = exact_log2 ((INTVAL (XEXP (op0, 1))
11138 & GET_MODE_MASK (mode))
11140 && const_op >> i == 0
11141 && (tmode = mode_for_size (i, MODE_INT, 1)) != BLKmode
11142 && (TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (tmode),
11143 GET_MODE_BITSIZE (GET_MODE (op0)))
11144 || (REG_P (XEXP (op0, 0))
11145 && reg_truncated_to_mode (tmode, XEXP (op0, 0)))))
11147 op0 = gen_lowpart (tmode, XEXP (op0, 0));
11151 /* If this is (and:M1 (subreg:M2 X 0) (const_int C1)) where C1
11152 fits in both M1 and M2 and the SUBREG is either paradoxical
11153 or represents the low part, permute the SUBREG and the AND
11155 if (GET_CODE (XEXP (op0, 0)) == SUBREG)
11157 unsigned HOST_WIDE_INT c1;
11158 tmode = GET_MODE (SUBREG_REG (XEXP (op0, 0)));
11159 /* Require an integral mode, to avoid creating something like
11161 if (SCALAR_INT_MODE_P (tmode)
11162 /* It is unsafe to commute the AND into the SUBREG if the
11163 SUBREG is paradoxical and WORD_REGISTER_OPERATIONS is
11164 not defined. As originally written the upper bits
11165 have a defined value due to the AND operation.
11166 However, if we commute the AND inside the SUBREG then
11167 they no longer have defined values and the meaning of
11168 the code has been changed. */
11170 #ifdef WORD_REGISTER_OPERATIONS
11171 || (mode_width > GET_MODE_BITSIZE (tmode)
11172 && mode_width <= BITS_PER_WORD)
11174 || (mode_width <= GET_MODE_BITSIZE (tmode)
11175 && subreg_lowpart_p (XEXP (op0, 0))))
11176 && CONST_INT_P (XEXP (op0, 1))
11177 && mode_width <= HOST_BITS_PER_WIDE_INT
11178 && GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT
11179 && ((c1 = INTVAL (XEXP (op0, 1))) & ~mask) == 0
11180 && (c1 & ~GET_MODE_MASK (tmode)) == 0
11182 && c1 != GET_MODE_MASK (tmode))
11184 op0 = simplify_gen_binary (AND, tmode,
11185 SUBREG_REG (XEXP (op0, 0)),
11186 gen_int_mode (c1, tmode));
11187 op0 = gen_lowpart (mode, op0);
11192 /* Convert (ne (and (not X) 1) 0) to (eq (and X 1) 0). */
11193 if (const_op == 0 && equality_comparison_p
11194 && XEXP (op0, 1) == const1_rtx
11195 && GET_CODE (XEXP (op0, 0)) == NOT)
11197 op0 = simplify_and_const_int
11198 (NULL_RTX, mode, XEXP (XEXP (op0, 0), 0), (HOST_WIDE_INT) 1);
11199 code = (code == NE ? EQ : NE);
11203 /* Convert (ne (and (lshiftrt (not X)) 1) 0) to
11204 (eq (and (lshiftrt X) 1) 0).
11205 Also handle the case where (not X) is expressed using xor. */
11206 if (const_op == 0 && equality_comparison_p
11207 && XEXP (op0, 1) == const1_rtx
11208 && GET_CODE (XEXP (op0, 0)) == LSHIFTRT)
11210 rtx shift_op = XEXP (XEXP (op0, 0), 0);
11211 rtx shift_count = XEXP (XEXP (op0, 0), 1);
11213 if (GET_CODE (shift_op) == NOT
11214 || (GET_CODE (shift_op) == XOR
11215 && CONST_INT_P (XEXP (shift_op, 1))
11216 && CONST_INT_P (shift_count)
11217 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
11218 && (INTVAL (XEXP (shift_op, 1))
11219 == (HOST_WIDE_INT) 1 << INTVAL (shift_count))))
11221 op0 = simplify_and_const_int
11223 gen_rtx_LSHIFTRT (mode, XEXP (shift_op, 0), shift_count),
11224 (HOST_WIDE_INT) 1);
11225 code = (code == NE ? EQ : NE);
11232 /* If we have (compare (ashift FOO N) (const_int C)) and
11233 the high order N bits of FOO (N+1 if an inequality comparison)
11234 are known to be zero, we can do this by comparing FOO with C
11235 shifted right N bits so long as the low-order N bits of C are
11237 if (CONST_INT_P (XEXP (op0, 1))
11238 && INTVAL (XEXP (op0, 1)) >= 0
11239 && ((INTVAL (XEXP (op0, 1)) + ! equality_comparison_p)
11240 < HOST_BITS_PER_WIDE_INT)
11242 & (((HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1))) - 1)) == 0)
11243 && mode_width <= HOST_BITS_PER_WIDE_INT
11244 && (nonzero_bits (XEXP (op0, 0), mode)
11245 & ~(mask >> (INTVAL (XEXP (op0, 1))
11246 + ! equality_comparison_p))) == 0)
11248 /* We must perform a logical shift, not an arithmetic one,
11249 as we want the top N bits of C to be zero. */
11250 unsigned HOST_WIDE_INT temp = const_op & GET_MODE_MASK (mode);
11252 temp >>= INTVAL (XEXP (op0, 1));
11253 op1 = gen_int_mode (temp, mode);
11254 op0 = XEXP (op0, 0);
11258 /* If we are doing a sign bit comparison, it means we are testing
11259 a particular bit. Convert it to the appropriate AND. */
11260 if (sign_bit_comparison_p && CONST_INT_P (XEXP (op0, 1))
11261 && mode_width <= HOST_BITS_PER_WIDE_INT)
11263 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
11266 - INTVAL (XEXP (op0, 1)))));
11267 code = (code == LT ? NE : EQ);
11271 /* If this an equality comparison with zero and we are shifting
11272 the low bit to the sign bit, we can convert this to an AND of the
11274 if (const_op == 0 && equality_comparison_p
11275 && CONST_INT_P (XEXP (op0, 1))
11276 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (op0, 1))
11279 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
11280 (HOST_WIDE_INT) 1);
11286 /* If this is an equality comparison with zero, we can do this
11287 as a logical shift, which might be much simpler. */
11288 if (equality_comparison_p && const_op == 0
11289 && CONST_INT_P (XEXP (op0, 1)))
11291 op0 = simplify_shift_const (NULL_RTX, LSHIFTRT, mode,
11293 INTVAL (XEXP (op0, 1)));
11297 /* If OP0 is a sign extension and CODE is not an unsigned comparison,
11298 do the comparison in a narrower mode. */
11299 if (! unsigned_comparison_p
11300 && CONST_INT_P (XEXP (op0, 1))
11301 && GET_CODE (XEXP (op0, 0)) == ASHIFT
11302 && XEXP (op0, 1) == XEXP (XEXP (op0, 0), 1)
11303 && (tmode = mode_for_size (mode_width - INTVAL (XEXP (op0, 1)),
11304 MODE_INT, 1)) != BLKmode
11305 && (((unsigned HOST_WIDE_INT) const_op
11306 + (GET_MODE_MASK (tmode) >> 1) + 1)
11307 <= GET_MODE_MASK (tmode)))
11309 op0 = gen_lowpart (tmode, XEXP (XEXP (op0, 0), 0));
11313 /* Likewise if OP0 is a PLUS of a sign extension with a
11314 constant, which is usually represented with the PLUS
11315 between the shifts. */
11316 if (! unsigned_comparison_p
11317 && CONST_INT_P (XEXP (op0, 1))
11318 && GET_CODE (XEXP (op0, 0)) == PLUS
11319 && CONST_INT_P (XEXP (XEXP (op0, 0), 1))
11320 && GET_CODE (XEXP (XEXP (op0, 0), 0)) == ASHIFT
11321 && XEXP (op0, 1) == XEXP (XEXP (XEXP (op0, 0), 0), 1)
11322 && (tmode = mode_for_size (mode_width - INTVAL (XEXP (op0, 1)),
11323 MODE_INT, 1)) != BLKmode
11324 && (((unsigned HOST_WIDE_INT) const_op
11325 + (GET_MODE_MASK (tmode) >> 1) + 1)
11326 <= GET_MODE_MASK (tmode)))
11328 rtx inner = XEXP (XEXP (XEXP (op0, 0), 0), 0);
11329 rtx add_const = XEXP (XEXP (op0, 0), 1);
11330 rtx new_const = simplify_gen_binary (ASHIFTRT, GET_MODE (op0),
11331 add_const, XEXP (op0, 1));
11333 op0 = simplify_gen_binary (PLUS, tmode,
11334 gen_lowpart (tmode, inner),
11339 /* ... fall through ... */
11341 /* If we have (compare (xshiftrt FOO N) (const_int C)) and
11342 the low order N bits of FOO are known to be zero, we can do this
11343 by comparing FOO with C shifted left N bits so long as no
11344 overflow occurs. */
11345 if (CONST_INT_P (XEXP (op0, 1))
11346 && INTVAL (XEXP (op0, 1)) >= 0
11347 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT
11348 && mode_width <= HOST_BITS_PER_WIDE_INT
11349 && (nonzero_bits (XEXP (op0, 0), mode)
11350 & (((HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1))) - 1)) == 0
11351 && (((unsigned HOST_WIDE_INT) const_op
11352 + (GET_CODE (op0) != LSHIFTRT
11353 ? ((GET_MODE_MASK (mode) >> INTVAL (XEXP (op0, 1)) >> 1)
11356 <= GET_MODE_MASK (mode) >> INTVAL (XEXP (op0, 1))))
11358 /* If the shift was logical, then we must make the condition
11360 if (GET_CODE (op0) == LSHIFTRT)
11361 code = unsigned_condition (code);
11363 const_op <<= INTVAL (XEXP (op0, 1));
11364 op1 = GEN_INT (const_op);
11365 op0 = XEXP (op0, 0);
11369 /* If we are using this shift to extract just the sign bit, we
11370 can replace this with an LT or GE comparison. */
11372 && (equality_comparison_p || sign_bit_comparison_p)
11373 && CONST_INT_P (XEXP (op0, 1))
11374 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (op0, 1))
11377 op0 = XEXP (op0, 0);
11378 code = (code == NE || code == GT ? LT : GE);
11390 /* Now make any compound operations involved in this comparison. Then,
11391 check for an outmost SUBREG on OP0 that is not doing anything or is
11392 paradoxical. The latter transformation must only be performed when
11393 it is known that the "extra" bits will be the same in op0 and op1 or
11394 that they don't matter. There are three cases to consider:
11396 1. SUBREG_REG (op0) is a register. In this case the bits are don't
11397 care bits and we can assume they have any convenient value. So
11398 making the transformation is safe.
11400 2. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is not defined.
11401 In this case the upper bits of op0 are undefined. We should not make
11402 the simplification in that case as we do not know the contents of
11405 3. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is defined and not
11406 UNKNOWN. In that case we know those bits are zeros or ones. We must
11407 also be sure that they are the same as the upper bits of op1.
11409 We can never remove a SUBREG for a non-equality comparison because
11410 the sign bit is in a different place in the underlying object. */
11412 op0 = make_compound_operation (op0, op1 == const0_rtx ? COMPARE : SET);
11413 op1 = make_compound_operation (op1, SET);
11415 if (GET_CODE (op0) == SUBREG && subreg_lowpart_p (op0)
11416 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
11417 && GET_MODE_CLASS (GET_MODE (SUBREG_REG (op0))) == MODE_INT
11418 && (code == NE || code == EQ))
11420 if (GET_MODE_SIZE (GET_MODE (op0))
11421 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (op0))))
11423 /* For paradoxical subregs, allow case 1 as above. Case 3 isn't
11425 if (REG_P (SUBREG_REG (op0)))
11427 op0 = SUBREG_REG (op0);
11428 op1 = gen_lowpart (GET_MODE (op0), op1);
11431 else if ((GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0)))
11432 <= HOST_BITS_PER_WIDE_INT)
11433 && (nonzero_bits (SUBREG_REG (op0),
11434 GET_MODE (SUBREG_REG (op0)))
11435 & ~GET_MODE_MASK (GET_MODE (op0))) == 0)
11437 tem = gen_lowpart (GET_MODE (SUBREG_REG (op0)), op1);
11439 if ((nonzero_bits (tem, GET_MODE (SUBREG_REG (op0)))
11440 & ~GET_MODE_MASK (GET_MODE (op0))) == 0)
11441 op0 = SUBREG_REG (op0), op1 = tem;
11445 /* We now do the opposite procedure: Some machines don't have compare
11446 insns in all modes. If OP0's mode is an integer mode smaller than a
11447 word and we can't do a compare in that mode, see if there is a larger
11448 mode for which we can do the compare. There are a number of cases in
11449 which we can use the wider mode. */
11451 mode = GET_MODE (op0);
11452 if (mode != VOIDmode && GET_MODE_CLASS (mode) == MODE_INT
11453 && GET_MODE_SIZE (mode) < UNITS_PER_WORD
11454 && ! have_insn_for (COMPARE, mode))
11455 for (tmode = GET_MODE_WIDER_MODE (mode);
11457 && GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT);
11458 tmode = GET_MODE_WIDER_MODE (tmode))
11459 if (have_insn_for (COMPARE, tmode))
11463 /* If this is a test for negative, we can make an explicit
11464 test of the sign bit. Test this first so we can use
11465 a paradoxical subreg to extend OP0. */
11467 if (op1 == const0_rtx && (code == LT || code == GE)
11468 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
11470 op0 = simplify_gen_binary (AND, tmode,
11471 gen_lowpart (tmode, op0),
11472 GEN_INT ((HOST_WIDE_INT) 1
11473 << (GET_MODE_BITSIZE (mode)
11475 code = (code == LT) ? NE : EQ;
11479 /* If the only nonzero bits in OP0 and OP1 are those in the
11480 narrower mode and this is an equality or unsigned comparison,
11481 we can use the wider mode. Similarly for sign-extended
11482 values, in which case it is true for all comparisons. */
11483 zero_extended = ((code == EQ || code == NE
11484 || code == GEU || code == GTU
11485 || code == LEU || code == LTU)
11486 && (nonzero_bits (op0, tmode)
11487 & ~GET_MODE_MASK (mode)) == 0
11488 && ((CONST_INT_P (op1)
11489 || (nonzero_bits (op1, tmode)
11490 & ~GET_MODE_MASK (mode)) == 0)));
11493 || ((num_sign_bit_copies (op0, tmode)
11494 > (unsigned int) (GET_MODE_BITSIZE (tmode)
11495 - GET_MODE_BITSIZE (mode)))
11496 && (num_sign_bit_copies (op1, tmode)
11497 > (unsigned int) (GET_MODE_BITSIZE (tmode)
11498 - GET_MODE_BITSIZE (mode)))))
11500 /* If OP0 is an AND and we don't have an AND in MODE either,
11501 make a new AND in the proper mode. */
11502 if (GET_CODE (op0) == AND
11503 && !have_insn_for (AND, mode))
11504 op0 = simplify_gen_binary (AND, tmode,
11505 gen_lowpart (tmode,
11507 gen_lowpart (tmode,
11513 op0 = simplify_gen_unary (ZERO_EXTEND, tmode, op0, mode);
11514 op1 = simplify_gen_unary (ZERO_EXTEND, tmode, op1, mode);
11518 op0 = simplify_gen_unary (SIGN_EXTEND, tmode, op0, mode);
11519 op1 = simplify_gen_unary (SIGN_EXTEND, tmode, op1, mode);
11526 #ifdef CANONICALIZE_COMPARISON
11527 /* If this machine only supports a subset of valid comparisons, see if we
11528 can convert an unsupported one into a supported one. */
11529 CANONICALIZE_COMPARISON (code, op0, op1);
11538 /* Utility function for record_value_for_reg. Count number of
11543 enum rtx_code code = GET_CODE (x);
11547 if (GET_RTX_CLASS (code) == '2'
11548 || GET_RTX_CLASS (code) == 'c')
11550 rtx x0 = XEXP (x, 0);
11551 rtx x1 = XEXP (x, 1);
11554 return 1 + 2 * count_rtxs (x0);
11556 if ((GET_RTX_CLASS (GET_CODE (x1)) == '2'
11557 || GET_RTX_CLASS (GET_CODE (x1)) == 'c')
11558 && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1)))
11559 return 2 + 2 * count_rtxs (x0)
11560 + count_rtxs (x == XEXP (x1, 0)
11561 ? XEXP (x1, 1) : XEXP (x1, 0));
11563 if ((GET_RTX_CLASS (GET_CODE (x0)) == '2'
11564 || GET_RTX_CLASS (GET_CODE (x0)) == 'c')
11565 && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1)))
11566 return 2 + 2 * count_rtxs (x1)
11567 + count_rtxs (x == XEXP (x0, 0)
11568 ? XEXP (x0, 1) : XEXP (x0, 0));
11571 fmt = GET_RTX_FORMAT (code);
11572 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
11574 ret += count_rtxs (XEXP (x, i));
11575 else if (fmt[i] == 'E')
11576 for (j = 0; j < XVECLEN (x, i); j++)
11577 ret += count_rtxs (XVECEXP (x, i, j));
11582 /* Utility function for following routine. Called when X is part of a value
11583 being stored into last_set_value. Sets last_set_table_tick
11584 for each register mentioned. Similar to mention_regs in cse.c */
11587 update_table_tick (rtx x)
11589 enum rtx_code code = GET_CODE (x);
11590 const char *fmt = GET_RTX_FORMAT (code);
11595 unsigned int regno = REGNO (x);
11596 unsigned int endregno = END_REGNO (x);
11599 for (r = regno; r < endregno; r++)
11601 reg_stat_type *rsp = VEC_index (reg_stat_type, reg_stat, r);
11602 rsp->last_set_table_tick = label_tick;
11608 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
11611 /* Check for identical subexpressions. If x contains
11612 identical subexpression we only have to traverse one of
11614 if (i == 0 && ARITHMETIC_P (x))
11616 /* Note that at this point x1 has already been
11618 rtx x0 = XEXP (x, 0);
11619 rtx x1 = XEXP (x, 1);
11621 /* If x0 and x1 are identical then there is no need to
11626 /* If x0 is identical to a subexpression of x1 then while
11627 processing x1, x0 has already been processed. Thus we
11628 are done with x. */
11629 if (ARITHMETIC_P (x1)
11630 && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1)))
11633 /* If x1 is identical to a subexpression of x0 then we
11634 still have to process the rest of x0. */
11635 if (ARITHMETIC_P (x0)
11636 && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1)))
11638 update_table_tick (XEXP (x0, x1 == XEXP (x0, 0) ? 1 : 0));
11643 update_table_tick (XEXP (x, i));
11645 else if (fmt[i] == 'E')
11646 for (j = 0; j < XVECLEN (x, i); j++)
11647 update_table_tick (XVECEXP (x, i, j));
11650 /* Record that REG is set to VALUE in insn INSN. If VALUE is zero, we
11651 are saying that the register is clobbered and we no longer know its
11652 value. If INSN is zero, don't update reg_stat[].last_set; this is
11653 only permitted with VALUE also zero and is used to invalidate the
11657 record_value_for_reg (rtx reg, rtx insn, rtx value)
11659 unsigned int regno = REGNO (reg);
11660 unsigned int endregno = END_REGNO (reg);
11662 reg_stat_type *rsp;
11664 /* If VALUE contains REG and we have a previous value for REG, substitute
11665 the previous value. */
11666 if (value && insn && reg_overlap_mentioned_p (reg, value))
11670 /* Set things up so get_last_value is allowed to see anything set up to
11672 subst_low_luid = DF_INSN_LUID (insn);
11673 tem = get_last_value (reg);
11675 /* If TEM is simply a binary operation with two CLOBBERs as operands,
11676 it isn't going to be useful and will take a lot of time to process,
11677 so just use the CLOBBER. */
11681 if (ARITHMETIC_P (tem)
11682 && GET_CODE (XEXP (tem, 0)) == CLOBBER
11683 && GET_CODE (XEXP (tem, 1)) == CLOBBER)
11684 tem = XEXP (tem, 0);
11685 else if (count_occurrences (value, reg, 1) >= 2)
11687 /* If there are two or more occurrences of REG in VALUE,
11688 prevent the value from growing too much. */
11689 if (count_rtxs (tem) > MAX_LAST_VALUE_RTL)
11690 tem = gen_rtx_CLOBBER (GET_MODE (tem), const0_rtx);
11693 value = replace_rtx (copy_rtx (value), reg, tem);
11697 /* For each register modified, show we don't know its value, that
11698 we don't know about its bitwise content, that its value has been
11699 updated, and that we don't know the location of the death of the
11701 for (i = regno; i < endregno; i++)
11703 rsp = VEC_index (reg_stat_type, reg_stat, i);
11706 rsp->last_set = insn;
11708 rsp->last_set_value = 0;
11709 rsp->last_set_mode = VOIDmode;
11710 rsp->last_set_nonzero_bits = 0;
11711 rsp->last_set_sign_bit_copies = 0;
11712 rsp->last_death = 0;
11713 rsp->truncated_to_mode = VOIDmode;
11716 /* Mark registers that are being referenced in this value. */
11718 update_table_tick (value);
11720 /* Now update the status of each register being set.
11721 If someone is using this register in this block, set this register
11722 to invalid since we will get confused between the two lives in this
11723 basic block. This makes using this register always invalid. In cse, we
11724 scan the table to invalidate all entries using this register, but this
11725 is too much work for us. */
11727 for (i = regno; i < endregno; i++)
11729 rsp = VEC_index (reg_stat_type, reg_stat, i);
11730 rsp->last_set_label = label_tick;
11732 || (value && rsp->last_set_table_tick >= label_tick_ebb_start))
11733 rsp->last_set_invalid = 1;
11735 rsp->last_set_invalid = 0;
11738 /* The value being assigned might refer to X (like in "x++;"). In that
11739 case, we must replace it with (clobber (const_int 0)) to prevent
11741 rsp = VEC_index (reg_stat_type, reg_stat, regno);
11742 if (value && !get_last_value_validate (&value, insn, label_tick, 0))
11744 value = copy_rtx (value);
11745 if (!get_last_value_validate (&value, insn, label_tick, 1))
11749 /* For the main register being modified, update the value, the mode, the
11750 nonzero bits, and the number of sign bit copies. */
11752 rsp->last_set_value = value;
11756 enum machine_mode mode = GET_MODE (reg);
11757 subst_low_luid = DF_INSN_LUID (insn);
11758 rsp->last_set_mode = mode;
11759 if (GET_MODE_CLASS (mode) == MODE_INT
11760 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
11761 mode = nonzero_bits_mode;
11762 rsp->last_set_nonzero_bits = nonzero_bits (value, mode);
11763 rsp->last_set_sign_bit_copies
11764 = num_sign_bit_copies (value, GET_MODE (reg));
11768 /* Called via note_stores from record_dead_and_set_regs to handle one
11769 SET or CLOBBER in an insn. DATA is the instruction in which the
11770 set is occurring. */
11773 record_dead_and_set_regs_1 (rtx dest, const_rtx setter, void *data)
11775 rtx record_dead_insn = (rtx) data;
11777 if (GET_CODE (dest) == SUBREG)
11778 dest = SUBREG_REG (dest);
11780 if (!record_dead_insn)
11783 record_value_for_reg (dest, NULL_RTX, NULL_RTX);
11789 /* If we are setting the whole register, we know its value. Otherwise
11790 show that we don't know the value. We can handle SUBREG in
11792 if (GET_CODE (setter) == SET && dest == SET_DEST (setter))
11793 record_value_for_reg (dest, record_dead_insn, SET_SRC (setter));
11794 else if (GET_CODE (setter) == SET
11795 && GET_CODE (SET_DEST (setter)) == SUBREG
11796 && SUBREG_REG (SET_DEST (setter)) == dest
11797 && GET_MODE_BITSIZE (GET_MODE (dest)) <= BITS_PER_WORD
11798 && subreg_lowpart_p (SET_DEST (setter)))
11799 record_value_for_reg (dest, record_dead_insn,
11800 gen_lowpart (GET_MODE (dest),
11801 SET_SRC (setter)));
11803 record_value_for_reg (dest, record_dead_insn, NULL_RTX);
11805 else if (MEM_P (dest)
11806 /* Ignore pushes, they clobber nothing. */
11807 && ! push_operand (dest, GET_MODE (dest)))
11808 mem_last_set = DF_INSN_LUID (record_dead_insn);
11811 /* Update the records of when each REG was most recently set or killed
11812 for the things done by INSN. This is the last thing done in processing
11813 INSN in the combiner loop.
11815 We update reg_stat[], in particular fields last_set, last_set_value,
11816 last_set_mode, last_set_nonzero_bits, last_set_sign_bit_copies,
11817 last_death, and also the similar information mem_last_set (which insn
11818 most recently modified memory) and last_call_luid (which insn was the
11819 most recent subroutine call). */
11822 record_dead_and_set_regs (rtx insn)
11827 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
11829 if (REG_NOTE_KIND (link) == REG_DEAD
11830 && REG_P (XEXP (link, 0)))
11832 unsigned int regno = REGNO (XEXP (link, 0));
11833 unsigned int endregno = END_REGNO (XEXP (link, 0));
11835 for (i = regno; i < endregno; i++)
11837 reg_stat_type *rsp;
11839 rsp = VEC_index (reg_stat_type, reg_stat, i);
11840 rsp->last_death = insn;
11843 else if (REG_NOTE_KIND (link) == REG_INC)
11844 record_value_for_reg (XEXP (link, 0), insn, NULL_RTX);
11849 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
11850 if (TEST_HARD_REG_BIT (regs_invalidated_by_call, i))
11852 reg_stat_type *rsp;
11854 rsp = VEC_index (reg_stat_type, reg_stat, i);
11855 rsp->last_set_invalid = 1;
11856 rsp->last_set = insn;
11857 rsp->last_set_value = 0;
11858 rsp->last_set_mode = VOIDmode;
11859 rsp->last_set_nonzero_bits = 0;
11860 rsp->last_set_sign_bit_copies = 0;
11861 rsp->last_death = 0;
11862 rsp->truncated_to_mode = VOIDmode;
11865 last_call_luid = mem_last_set = DF_INSN_LUID (insn);
11867 /* We can't combine into a call pattern. Remember, though, that
11868 the return value register is set at this LUID. We could
11869 still replace a register with the return value from the
11870 wrong subroutine call! */
11871 note_stores (PATTERN (insn), record_dead_and_set_regs_1, NULL_RTX);
11874 note_stores (PATTERN (insn), record_dead_and_set_regs_1, insn);
11877 /* If a SUBREG has the promoted bit set, it is in fact a property of the
11878 register present in the SUBREG, so for each such SUBREG go back and
11879 adjust nonzero and sign bit information of the registers that are
11880 known to have some zero/sign bits set.
11882 This is needed because when combine blows the SUBREGs away, the
11883 information on zero/sign bits is lost and further combines can be
11884 missed because of that. */
11887 record_promoted_value (rtx insn, rtx subreg)
11890 unsigned int regno = REGNO (SUBREG_REG (subreg));
11891 enum machine_mode mode = GET_MODE (subreg);
11893 if (GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT)
11896 for (links = LOG_LINKS (insn); links;)
11898 reg_stat_type *rsp;
11900 insn = XEXP (links, 0);
11901 set = single_set (insn);
11903 if (! set || !REG_P (SET_DEST (set))
11904 || REGNO (SET_DEST (set)) != regno
11905 || GET_MODE (SET_DEST (set)) != GET_MODE (SUBREG_REG (subreg)))
11907 links = XEXP (links, 1);
11911 rsp = VEC_index (reg_stat_type, reg_stat, regno);
11912 if (rsp->last_set == insn)
11914 if (SUBREG_PROMOTED_UNSIGNED_P (subreg) > 0)
11915 rsp->last_set_nonzero_bits &= GET_MODE_MASK (mode);
11918 if (REG_P (SET_SRC (set)))
11920 regno = REGNO (SET_SRC (set));
11921 links = LOG_LINKS (insn);
11928 /* Check if X, a register, is known to contain a value already
11929 truncated to MODE. In this case we can use a subreg to refer to
11930 the truncated value even though in the generic case we would need
11931 an explicit truncation. */
11934 reg_truncated_to_mode (enum machine_mode mode, const_rtx x)
11936 reg_stat_type *rsp = VEC_index (reg_stat_type, reg_stat, REGNO (x));
11937 enum machine_mode truncated = rsp->truncated_to_mode;
11940 || rsp->truncation_label < label_tick_ebb_start)
11942 if (GET_MODE_SIZE (truncated) <= GET_MODE_SIZE (mode))
11944 if (TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode),
11945 GET_MODE_BITSIZE (truncated)))
11950 /* Callback for for_each_rtx. If *P is a hard reg or a subreg record the mode
11951 that the register is accessed in. For non-TRULY_NOOP_TRUNCATION targets we
11952 might be able to turn a truncate into a subreg using this information.
11953 Return -1 if traversing *P is complete or 0 otherwise. */
11956 record_truncated_value (rtx *p, void *data ATTRIBUTE_UNUSED)
11959 enum machine_mode truncated_mode;
11960 reg_stat_type *rsp;
11962 if (GET_CODE (x) == SUBREG && REG_P (SUBREG_REG (x)))
11964 enum machine_mode original_mode = GET_MODE (SUBREG_REG (x));
11965 truncated_mode = GET_MODE (x);
11967 if (GET_MODE_SIZE (original_mode) <= GET_MODE_SIZE (truncated_mode))
11970 if (TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (truncated_mode),
11971 GET_MODE_BITSIZE (original_mode)))
11974 x = SUBREG_REG (x);
11976 /* ??? For hard-regs we now record everything. We might be able to
11977 optimize this using last_set_mode. */
11978 else if (REG_P (x) && REGNO (x) < FIRST_PSEUDO_REGISTER)
11979 truncated_mode = GET_MODE (x);
11983 rsp = VEC_index (reg_stat_type, reg_stat, REGNO (x));
11984 if (rsp->truncated_to_mode == 0
11985 || rsp->truncation_label < label_tick_ebb_start
11986 || (GET_MODE_SIZE (truncated_mode)
11987 < GET_MODE_SIZE (rsp->truncated_to_mode)))
11989 rsp->truncated_to_mode = truncated_mode;
11990 rsp->truncation_label = label_tick;
11996 /* Callback for note_uses. Find hardregs and subregs of pseudos and
11997 the modes they are used in. This can help truning TRUNCATEs into
12001 record_truncated_values (rtx *x, void *data ATTRIBUTE_UNUSED)
12003 for_each_rtx (x, record_truncated_value, NULL);
12006 /* Scan X for promoted SUBREGs. For each one found,
12007 note what it implies to the registers used in it. */
12010 check_promoted_subreg (rtx insn, rtx x)
12012 if (GET_CODE (x) == SUBREG
12013 && SUBREG_PROMOTED_VAR_P (x)
12014 && REG_P (SUBREG_REG (x)))
12015 record_promoted_value (insn, x);
12018 const char *format = GET_RTX_FORMAT (GET_CODE (x));
12021 for (i = 0; i < GET_RTX_LENGTH (GET_CODE (x)); i++)
12025 check_promoted_subreg (insn, XEXP (x, i));
12029 if (XVEC (x, i) != 0)
12030 for (j = 0; j < XVECLEN (x, i); j++)
12031 check_promoted_subreg (insn, XVECEXP (x, i, j));
12037 /* Verify that all the registers and memory references mentioned in *LOC are
12038 still valid. *LOC was part of a value set in INSN when label_tick was
12039 equal to TICK. Return 0 if some are not. If REPLACE is nonzero, replace
12040 the invalid references with (clobber (const_int 0)) and return 1. This
12041 replacement is useful because we often can get useful information about
12042 the form of a value (e.g., if it was produced by a shift that always
12043 produces -1 or 0) even though we don't know exactly what registers it
12044 was produced from. */
12047 get_last_value_validate (rtx *loc, rtx insn, int tick, int replace)
12050 const char *fmt = GET_RTX_FORMAT (GET_CODE (x));
12051 int len = GET_RTX_LENGTH (GET_CODE (x));
12056 unsigned int regno = REGNO (x);
12057 unsigned int endregno = END_REGNO (x);
12060 for (j = regno; j < endregno; j++)
12062 reg_stat_type *rsp = VEC_index (reg_stat_type, reg_stat, j);
12063 if (rsp->last_set_invalid
12064 /* If this is a pseudo-register that was only set once and not
12065 live at the beginning of the function, it is always valid. */
12066 || (! (regno >= FIRST_PSEUDO_REGISTER
12067 && REG_N_SETS (regno) == 1
12068 && (!REGNO_REG_SET_P
12069 (DF_LR_IN (ENTRY_BLOCK_PTR->next_bb), regno)))
12070 && rsp->last_set_label > tick))
12073 *loc = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
12080 /* If this is a memory reference, make sure that there were no stores after
12081 it that might have clobbered the value. We don't have alias info, so we
12082 assume any store invalidates it. Moreover, we only have local UIDs, so
12083 we also assume that there were stores in the intervening basic blocks. */
12084 else if (MEM_P (x) && !MEM_READONLY_P (x)
12085 && (tick != label_tick || DF_INSN_LUID (insn) <= mem_last_set))
12088 *loc = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
12092 for (i = 0; i < len; i++)
12096 /* Check for identical subexpressions. If x contains
12097 identical subexpression we only have to traverse one of
12099 if (i == 1 && ARITHMETIC_P (x))
12101 /* Note that at this point x0 has already been checked
12102 and found valid. */
12103 rtx x0 = XEXP (x, 0);
12104 rtx x1 = XEXP (x, 1);
12106 /* If x0 and x1 are identical then x is also valid. */
12110 /* If x1 is identical to a subexpression of x0 then
12111 while checking x0, x1 has already been checked. Thus
12112 it is valid and so as x. */
12113 if (ARITHMETIC_P (x0)
12114 && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1)))
12117 /* If x0 is identical to a subexpression of x1 then x is
12118 valid iff the rest of x1 is valid. */
12119 if (ARITHMETIC_P (x1)
12120 && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1)))
12122 get_last_value_validate (&XEXP (x1,
12123 x0 == XEXP (x1, 0) ? 1 : 0),
12124 insn, tick, replace);
12127 if (get_last_value_validate (&XEXP (x, i), insn, tick,
12131 else if (fmt[i] == 'E')
12132 for (j = 0; j < XVECLEN (x, i); j++)
12133 if (get_last_value_validate (&XVECEXP (x, i, j),
12134 insn, tick, replace) == 0)
12138 /* If we haven't found a reason for it to be invalid, it is valid. */
12142 /* Get the last value assigned to X, if known. Some registers
12143 in the value may be replaced with (clobber (const_int 0)) if their value
12144 is known longer known reliably. */
12147 get_last_value (const_rtx x)
12149 unsigned int regno;
12151 reg_stat_type *rsp;
12153 /* If this is a non-paradoxical SUBREG, get the value of its operand and
12154 then convert it to the desired mode. If this is a paradoxical SUBREG,
12155 we cannot predict what values the "extra" bits might have. */
12156 if (GET_CODE (x) == SUBREG
12157 && subreg_lowpart_p (x)
12158 && (GET_MODE_SIZE (GET_MODE (x))
12159 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
12160 && (value = get_last_value (SUBREG_REG (x))) != 0)
12161 return gen_lowpart (GET_MODE (x), value);
12167 rsp = VEC_index (reg_stat_type, reg_stat, regno);
12168 value = rsp->last_set_value;
12170 /* If we don't have a value, or if it isn't for this basic block and
12171 it's either a hard register, set more than once, or it's a live
12172 at the beginning of the function, return 0.
12174 Because if it's not live at the beginning of the function then the reg
12175 is always set before being used (is never used without being set).
12176 And, if it's set only once, and it's always set before use, then all
12177 uses must have the same last value, even if it's not from this basic
12181 || (rsp->last_set_label < label_tick_ebb_start
12182 && (regno < FIRST_PSEUDO_REGISTER
12183 || REG_N_SETS (regno) != 1
12185 (DF_LR_IN (ENTRY_BLOCK_PTR->next_bb), regno))))
12188 /* If the value was set in a later insn than the ones we are processing,
12189 we can't use it even if the register was only set once. */
12190 if (rsp->last_set_label == label_tick
12191 && DF_INSN_LUID (rsp->last_set) >= subst_low_luid)
12194 /* If the value has all its registers valid, return it. */
12195 if (get_last_value_validate (&value, rsp->last_set, rsp->last_set_label, 0))
12198 /* Otherwise, make a copy and replace any invalid register with
12199 (clobber (const_int 0)). If that fails for some reason, return 0. */
12201 value = copy_rtx (value);
12202 if (get_last_value_validate (&value, rsp->last_set, rsp->last_set_label, 1))
12208 /* Return nonzero if expression X refers to a REG or to memory
12209 that is set in an instruction more recent than FROM_LUID. */
12212 use_crosses_set_p (const_rtx x, int from_luid)
12216 enum rtx_code code = GET_CODE (x);
12220 unsigned int regno = REGNO (x);
12221 unsigned endreg = END_REGNO (x);
12223 #ifdef PUSH_ROUNDING
12224 /* Don't allow uses of the stack pointer to be moved,
12225 because we don't know whether the move crosses a push insn. */
12226 if (regno == STACK_POINTER_REGNUM && PUSH_ARGS)
12229 for (; regno < endreg; regno++)
12231 reg_stat_type *rsp = VEC_index (reg_stat_type, reg_stat, regno);
12233 && rsp->last_set_label == label_tick
12234 && DF_INSN_LUID (rsp->last_set) > from_luid)
12240 if (code == MEM && mem_last_set > from_luid)
12243 fmt = GET_RTX_FORMAT (code);
12245 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
12250 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
12251 if (use_crosses_set_p (XVECEXP (x, i, j), from_luid))
12254 else if (fmt[i] == 'e'
12255 && use_crosses_set_p (XEXP (x, i), from_luid))
12261 /* Define three variables used for communication between the following
12264 static unsigned int reg_dead_regno, reg_dead_endregno;
12265 static int reg_dead_flag;
12267 /* Function called via note_stores from reg_dead_at_p.
12269 If DEST is within [reg_dead_regno, reg_dead_endregno), set
12270 reg_dead_flag to 1 if X is a CLOBBER and to -1 it is a SET. */
12273 reg_dead_at_p_1 (rtx dest, const_rtx x, void *data ATTRIBUTE_UNUSED)
12275 unsigned int regno, endregno;
12280 regno = REGNO (dest);
12281 endregno = END_REGNO (dest);
12282 if (reg_dead_endregno > regno && reg_dead_regno < endregno)
12283 reg_dead_flag = (GET_CODE (x) == CLOBBER) ? 1 : -1;
12286 /* Return nonzero if REG is known to be dead at INSN.
12288 We scan backwards from INSN. If we hit a REG_DEAD note or a CLOBBER
12289 referencing REG, it is dead. If we hit a SET referencing REG, it is
12290 live. Otherwise, see if it is live or dead at the start of the basic
12291 block we are in. Hard regs marked as being live in NEWPAT_USED_REGS
12292 must be assumed to be always live. */
12295 reg_dead_at_p (rtx reg, rtx insn)
12300 /* Set variables for reg_dead_at_p_1. */
12301 reg_dead_regno = REGNO (reg);
12302 reg_dead_endregno = END_REGNO (reg);
12306 /* Check that reg isn't mentioned in NEWPAT_USED_REGS. For fixed registers
12307 we allow the machine description to decide whether use-and-clobber
12308 patterns are OK. */
12309 if (reg_dead_regno < FIRST_PSEUDO_REGISTER)
12311 for (i = reg_dead_regno; i < reg_dead_endregno; i++)
12312 if (!fixed_regs[i] && TEST_HARD_REG_BIT (newpat_used_regs, i))
12316 /* Scan backwards until we find a REG_DEAD note, SET, CLOBBER, or
12317 beginning of basic block. */
12318 block = BLOCK_FOR_INSN (insn);
12323 note_stores (PATTERN (insn), reg_dead_at_p_1, NULL);
12325 return reg_dead_flag == 1 ? 1 : 0;
12327 if (find_regno_note (insn, REG_DEAD, reg_dead_regno))
12331 if (insn == BB_HEAD (block))
12334 insn = PREV_INSN (insn);
12337 /* Look at live-in sets for the basic block that we were in. */
12338 for (i = reg_dead_regno; i < reg_dead_endregno; i++)
12339 if (REGNO_REG_SET_P (df_get_live_in (block), i))
12345 /* Note hard registers in X that are used. */
12348 mark_used_regs_combine (rtx x)
12350 RTX_CODE code = GET_CODE (x);
12351 unsigned int regno;
12364 case ADDR_DIFF_VEC:
12367 /* CC0 must die in the insn after it is set, so we don't need to take
12368 special note of it here. */
12374 /* If we are clobbering a MEM, mark any hard registers inside the
12375 address as used. */
12376 if (MEM_P (XEXP (x, 0)))
12377 mark_used_regs_combine (XEXP (XEXP (x, 0), 0));
12382 /* A hard reg in a wide mode may really be multiple registers.
12383 If so, mark all of them just like the first. */
12384 if (regno < FIRST_PSEUDO_REGISTER)
12386 /* None of this applies to the stack, frame or arg pointers. */
12387 if (regno == STACK_POINTER_REGNUM
12388 #if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM
12389 || regno == HARD_FRAME_POINTER_REGNUM
12391 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
12392 || (regno == ARG_POINTER_REGNUM && fixed_regs[regno])
12394 || regno == FRAME_POINTER_REGNUM)
12397 add_to_hard_reg_set (&newpat_used_regs, GET_MODE (x), regno);
12403 /* If setting a MEM, or a SUBREG of a MEM, then note any hard regs in
12405 rtx testreg = SET_DEST (x);
12407 while (GET_CODE (testreg) == SUBREG
12408 || GET_CODE (testreg) == ZERO_EXTRACT
12409 || GET_CODE (testreg) == STRICT_LOW_PART)
12410 testreg = XEXP (testreg, 0);
12412 if (MEM_P (testreg))
12413 mark_used_regs_combine (XEXP (testreg, 0));
12415 mark_used_regs_combine (SET_SRC (x));
12423 /* Recursively scan the operands of this expression. */
12426 const char *fmt = GET_RTX_FORMAT (code);
12428 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
12431 mark_used_regs_combine (XEXP (x, i));
12432 else if (fmt[i] == 'E')
12436 for (j = 0; j < XVECLEN (x, i); j++)
12437 mark_used_regs_combine (XVECEXP (x, i, j));
12443 /* Remove register number REGNO from the dead registers list of INSN.
12445 Return the note used to record the death, if there was one. */
12448 remove_death (unsigned int regno, rtx insn)
12450 rtx note = find_regno_note (insn, REG_DEAD, regno);
12453 remove_note (insn, note);
12458 /* For each register (hardware or pseudo) used within expression X, if its
12459 death is in an instruction with luid between FROM_LUID (inclusive) and
12460 TO_INSN (exclusive), put a REG_DEAD note for that register in the
12461 list headed by PNOTES.
12463 That said, don't move registers killed by maybe_kill_insn.
12465 This is done when X is being merged by combination into TO_INSN. These
12466 notes will then be distributed as needed. */
12469 move_deaths (rtx x, rtx maybe_kill_insn, int from_luid, rtx to_insn,
12474 enum rtx_code code = GET_CODE (x);
12478 unsigned int regno = REGNO (x);
12479 rtx where_dead = VEC_index (reg_stat_type, reg_stat, regno)->last_death;
12481 /* Don't move the register if it gets killed in between from and to. */
12482 if (maybe_kill_insn && reg_set_p (x, maybe_kill_insn)
12483 && ! reg_referenced_p (x, maybe_kill_insn))
12487 && BLOCK_FOR_INSN (where_dead) == BLOCK_FOR_INSN (to_insn)
12488 && DF_INSN_LUID (where_dead) >= from_luid
12489 && DF_INSN_LUID (where_dead) < DF_INSN_LUID (to_insn))
12491 rtx note = remove_death (regno, where_dead);
12493 /* It is possible for the call above to return 0. This can occur
12494 when last_death points to I2 or I1 that we combined with.
12495 In that case make a new note.
12497 We must also check for the case where X is a hard register
12498 and NOTE is a death note for a range of hard registers
12499 including X. In that case, we must put REG_DEAD notes for
12500 the remaining registers in place of NOTE. */
12502 if (note != 0 && regno < FIRST_PSEUDO_REGISTER
12503 && (GET_MODE_SIZE (GET_MODE (XEXP (note, 0)))
12504 > GET_MODE_SIZE (GET_MODE (x))))
12506 unsigned int deadregno = REGNO (XEXP (note, 0));
12507 unsigned int deadend = END_HARD_REGNO (XEXP (note, 0));
12508 unsigned int ourend = END_HARD_REGNO (x);
12511 for (i = deadregno; i < deadend; i++)
12512 if (i < regno || i >= ourend)
12513 add_reg_note (where_dead, REG_DEAD, regno_reg_rtx[i]);
12516 /* If we didn't find any note, or if we found a REG_DEAD note that
12517 covers only part of the given reg, and we have a multi-reg hard
12518 register, then to be safe we must check for REG_DEAD notes
12519 for each register other than the first. They could have
12520 their own REG_DEAD notes lying around. */
12521 else if ((note == 0
12523 && (GET_MODE_SIZE (GET_MODE (XEXP (note, 0)))
12524 < GET_MODE_SIZE (GET_MODE (x)))))
12525 && regno < FIRST_PSEUDO_REGISTER
12526 && hard_regno_nregs[regno][GET_MODE (x)] > 1)
12528 unsigned int ourend = END_HARD_REGNO (x);
12529 unsigned int i, offset;
12533 offset = hard_regno_nregs[regno][GET_MODE (XEXP (note, 0))];
12537 for (i = regno + offset; i < ourend; i++)
12538 move_deaths (regno_reg_rtx[i],
12539 maybe_kill_insn, from_luid, to_insn, &oldnotes);
12542 if (note != 0 && GET_MODE (XEXP (note, 0)) == GET_MODE (x))
12544 XEXP (note, 1) = *pnotes;
12548 *pnotes = alloc_reg_note (REG_DEAD, x, *pnotes);
12554 else if (GET_CODE (x) == SET)
12556 rtx dest = SET_DEST (x);
12558 move_deaths (SET_SRC (x), maybe_kill_insn, from_luid, to_insn, pnotes);
12560 /* In the case of a ZERO_EXTRACT, a STRICT_LOW_PART, or a SUBREG
12561 that accesses one word of a multi-word item, some
12562 piece of everything register in the expression is used by
12563 this insn, so remove any old death. */
12564 /* ??? So why do we test for equality of the sizes? */
12566 if (GET_CODE (dest) == ZERO_EXTRACT
12567 || GET_CODE (dest) == STRICT_LOW_PART
12568 || (GET_CODE (dest) == SUBREG
12569 && (((GET_MODE_SIZE (GET_MODE (dest))
12570 + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
12571 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (dest)))
12572 + UNITS_PER_WORD - 1) / UNITS_PER_WORD))))
12574 move_deaths (dest, maybe_kill_insn, from_luid, to_insn, pnotes);
12578 /* If this is some other SUBREG, we know it replaces the entire
12579 value, so use that as the destination. */
12580 if (GET_CODE (dest) == SUBREG)
12581 dest = SUBREG_REG (dest);
12583 /* If this is a MEM, adjust deaths of anything used in the address.
12584 For a REG (the only other possibility), the entire value is
12585 being replaced so the old value is not used in this insn. */
12588 move_deaths (XEXP (dest, 0), maybe_kill_insn, from_luid,
12593 else if (GET_CODE (x) == CLOBBER)
12596 len = GET_RTX_LENGTH (code);
12597 fmt = GET_RTX_FORMAT (code);
12599 for (i = 0; i < len; i++)
12604 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
12605 move_deaths (XVECEXP (x, i, j), maybe_kill_insn, from_luid,
12608 else if (fmt[i] == 'e')
12609 move_deaths (XEXP (x, i), maybe_kill_insn, from_luid, to_insn, pnotes);
12613 /* Return 1 if X is the target of a bit-field assignment in BODY, the
12614 pattern of an insn. X must be a REG. */
12617 reg_bitfield_target_p (rtx x, rtx body)
12621 if (GET_CODE (body) == SET)
12623 rtx dest = SET_DEST (body);
12625 unsigned int regno, tregno, endregno, endtregno;
12627 if (GET_CODE (dest) == ZERO_EXTRACT)
12628 target = XEXP (dest, 0);
12629 else if (GET_CODE (dest) == STRICT_LOW_PART)
12630 target = SUBREG_REG (XEXP (dest, 0));
12634 if (GET_CODE (target) == SUBREG)
12635 target = SUBREG_REG (target);
12637 if (!REG_P (target))
12640 tregno = REGNO (target), regno = REGNO (x);
12641 if (tregno >= FIRST_PSEUDO_REGISTER || regno >= FIRST_PSEUDO_REGISTER)
12642 return target == x;
12644 endtregno = end_hard_regno (GET_MODE (target), tregno);
12645 endregno = end_hard_regno (GET_MODE (x), regno);
12647 return endregno > tregno && regno < endtregno;
12650 else if (GET_CODE (body) == PARALLEL)
12651 for (i = XVECLEN (body, 0) - 1; i >= 0; i--)
12652 if (reg_bitfield_target_p (x, XVECEXP (body, 0, i)))
12658 /* Return the next insn after INSN that is neither a NOTE nor a
12659 DEBUG_INSN. This routine does not look inside SEQUENCEs. */
12662 next_nonnote_nondebug_insn (rtx insn)
12666 insn = NEXT_INSN (insn);
12671 if (DEBUG_INSN_P (insn))
12681 /* Given a chain of REG_NOTES originally from FROM_INSN, try to place them
12682 as appropriate. I3 and I2 are the insns resulting from the combination
12683 insns including FROM (I2 may be zero).
12685 ELIM_I2 and ELIM_I1 are either zero or registers that we know will
12686 not need REG_DEAD notes because they are being substituted for. This
12687 saves searching in the most common cases.
12689 Each note in the list is either ignored or placed on some insns, depending
12690 on the type of note. */
12693 distribute_notes (rtx notes, rtx from_insn, rtx i3, rtx i2, rtx elim_i2,
12696 rtx note, next_note;
12699 for (note = notes; note; note = next_note)
12701 rtx place = 0, place2 = 0;
12703 next_note = XEXP (note, 1);
12704 switch (REG_NOTE_KIND (note))
12708 /* Doesn't matter much where we put this, as long as it's somewhere.
12709 It is preferable to keep these notes on branches, which is most
12710 likely to be i3. */
12714 case REG_VALUE_PROFILE:
12715 /* Just get rid of this note, as it is unused later anyway. */
12718 case REG_NON_LOCAL_GOTO:
12723 gcc_assert (i2 && JUMP_P (i2));
12728 case REG_EH_REGION:
12729 /* These notes must remain with the call or trapping instruction. */
12732 else if (i2 && CALL_P (i2))
12736 gcc_assert (cfun->can_throw_non_call_exceptions);
12737 if (may_trap_p (i3))
12739 else if (i2 && may_trap_p (i2))
12741 /* ??? Otherwise assume we've combined things such that we
12742 can now prove that the instructions can't trap. Drop the
12743 note in this case. */
12749 /* These notes must remain with the call. It should not be
12750 possible for both I2 and I3 to be a call. */
12755 gcc_assert (i2 && CALL_P (i2));
12761 /* Any clobbers for i3 may still exist, and so we must process
12762 REG_UNUSED notes from that insn.
12764 Any clobbers from i2 or i1 can only exist if they were added by
12765 recog_for_combine. In that case, recog_for_combine created the
12766 necessary REG_UNUSED notes. Trying to keep any original
12767 REG_UNUSED notes from these insns can cause incorrect output
12768 if it is for the same register as the original i3 dest.
12769 In that case, we will notice that the register is set in i3,
12770 and then add a REG_UNUSED note for the destination of i3, which
12771 is wrong. However, it is possible to have REG_UNUSED notes from
12772 i2 or i1 for register which were both used and clobbered, so
12773 we keep notes from i2 or i1 if they will turn into REG_DEAD
12776 /* If this register is set or clobbered in I3, put the note there
12777 unless there is one already. */
12778 if (reg_set_p (XEXP (note, 0), PATTERN (i3)))
12780 if (from_insn != i3)
12783 if (! (REG_P (XEXP (note, 0))
12784 ? find_regno_note (i3, REG_UNUSED, REGNO (XEXP (note, 0)))
12785 : find_reg_note (i3, REG_UNUSED, XEXP (note, 0))))
12788 /* Otherwise, if this register is used by I3, then this register
12789 now dies here, so we must put a REG_DEAD note here unless there
12791 else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3))
12792 && ! (REG_P (XEXP (note, 0))
12793 ? find_regno_note (i3, REG_DEAD,
12794 REGNO (XEXP (note, 0)))
12795 : find_reg_note (i3, REG_DEAD, XEXP (note, 0))))
12797 PUT_REG_NOTE_KIND (note, REG_DEAD);
12805 /* These notes say something about results of an insn. We can
12806 only support them if they used to be on I3 in which case they
12807 remain on I3. Otherwise they are ignored.
12809 If the note refers to an expression that is not a constant, we
12810 must also ignore the note since we cannot tell whether the
12811 equivalence is still true. It might be possible to do
12812 slightly better than this (we only have a problem if I2DEST
12813 or I1DEST is present in the expression), but it doesn't
12814 seem worth the trouble. */
12816 if (from_insn == i3
12817 && (XEXP (note, 0) == 0 || CONSTANT_P (XEXP (note, 0))))
12822 /* These notes say something about how a register is used. They must
12823 be present on any use of the register in I2 or I3. */
12824 if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3)))
12827 if (i2 && reg_mentioned_p (XEXP (note, 0), PATTERN (i2)))
12836 case REG_LABEL_TARGET:
12837 case REG_LABEL_OPERAND:
12838 /* This can show up in several ways -- either directly in the
12839 pattern, or hidden off in the constant pool with (or without?)
12840 a REG_EQUAL note. */
12841 /* ??? Ignore the without-reg_equal-note problem for now. */
12842 if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3))
12843 || ((tem = find_reg_note (i3, REG_EQUAL, NULL_RTX))
12844 && GET_CODE (XEXP (tem, 0)) == LABEL_REF
12845 && XEXP (XEXP (tem, 0), 0) == XEXP (note, 0)))
12849 && (reg_mentioned_p (XEXP (note, 0), PATTERN (i2))
12850 || ((tem = find_reg_note (i2, REG_EQUAL, NULL_RTX))
12851 && GET_CODE (XEXP (tem, 0)) == LABEL_REF
12852 && XEXP (XEXP (tem, 0), 0) == XEXP (note, 0))))
12860 /* For REG_LABEL_TARGET on a JUMP_P, we prefer to put the note
12861 as a JUMP_LABEL or decrement LABEL_NUSES if it's already
12863 if (place && JUMP_P (place)
12864 && REG_NOTE_KIND (note) == REG_LABEL_TARGET
12865 && (JUMP_LABEL (place) == NULL
12866 || JUMP_LABEL (place) == XEXP (note, 0)))
12868 rtx label = JUMP_LABEL (place);
12871 JUMP_LABEL (place) = XEXP (note, 0);
12872 else if (LABEL_P (label))
12873 LABEL_NUSES (label)--;
12876 if (place2 && JUMP_P (place2)
12877 && REG_NOTE_KIND (note) == REG_LABEL_TARGET
12878 && (JUMP_LABEL (place2) == NULL
12879 || JUMP_LABEL (place2) == XEXP (note, 0)))
12881 rtx label = JUMP_LABEL (place2);
12884 JUMP_LABEL (place2) = XEXP (note, 0);
12885 else if (LABEL_P (label))
12886 LABEL_NUSES (label)--;
12892 /* This note says something about the value of a register prior
12893 to the execution of an insn. It is too much trouble to see
12894 if the note is still correct in all situations. It is better
12895 to simply delete it. */
12899 /* If we replaced the right hand side of FROM_INSN with a
12900 REG_EQUAL note, the original use of the dying register
12901 will not have been combined into I3 and I2. In such cases,
12902 FROM_INSN is guaranteed to be the first of the combined
12903 instructions, so we simply need to search back before
12904 FROM_INSN for the previous use or set of this register,
12905 then alter the notes there appropriately.
12907 If the register is used as an input in I3, it dies there.
12908 Similarly for I2, if it is nonzero and adjacent to I3.
12910 If the register is not used as an input in either I3 or I2
12911 and it is not one of the registers we were supposed to eliminate,
12912 there are two possibilities. We might have a non-adjacent I2
12913 or we might have somehow eliminated an additional register
12914 from a computation. For example, we might have had A & B where
12915 we discover that B will always be zero. In this case we will
12916 eliminate the reference to A.
12918 In both cases, we must search to see if we can find a previous
12919 use of A and put the death note there. */
12922 && from_insn == i2mod
12923 && !reg_overlap_mentioned_p (XEXP (note, 0), i2mod_new_rhs))
12928 && CALL_P (from_insn)
12929 && find_reg_fusage (from_insn, USE, XEXP (note, 0)))
12931 else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3)))
12933 else if (i2 != 0 && next_nonnote_nondebug_insn (i2) == i3
12934 && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
12936 else if ((rtx_equal_p (XEXP (note, 0), elim_i2)
12938 && reg_overlap_mentioned_p (XEXP (note, 0),
12940 || rtx_equal_p (XEXP (note, 0), elim_i1))
12947 basic_block bb = this_basic_block;
12949 for (tem = PREV_INSN (tem); place == 0; tem = PREV_INSN (tem))
12951 if (!NONDEBUG_INSN_P (tem))
12953 if (tem == BB_HEAD (bb))
12958 /* If the register is being set at TEM, see if that is all
12959 TEM is doing. If so, delete TEM. Otherwise, make this
12960 into a REG_UNUSED note instead. Don't delete sets to
12961 global register vars. */
12962 if ((REGNO (XEXP (note, 0)) >= FIRST_PSEUDO_REGISTER
12963 || !global_regs[REGNO (XEXP (note, 0))])
12964 && reg_set_p (XEXP (note, 0), PATTERN (tem)))
12966 rtx set = single_set (tem);
12967 rtx inner_dest = 0;
12969 rtx cc0_setter = NULL_RTX;
12973 for (inner_dest = SET_DEST (set);
12974 (GET_CODE (inner_dest) == STRICT_LOW_PART
12975 || GET_CODE (inner_dest) == SUBREG
12976 || GET_CODE (inner_dest) == ZERO_EXTRACT);
12977 inner_dest = XEXP (inner_dest, 0))
12980 /* Verify that it was the set, and not a clobber that
12981 modified the register.
12983 CC0 targets must be careful to maintain setter/user
12984 pairs. If we cannot delete the setter due to side
12985 effects, mark the user with an UNUSED note instead
12988 if (set != 0 && ! side_effects_p (SET_SRC (set))
12989 && rtx_equal_p (XEXP (note, 0), inner_dest)
12991 && (! reg_mentioned_p (cc0_rtx, SET_SRC (set))
12992 || ((cc0_setter = prev_cc0_setter (tem)) != NULL
12993 && sets_cc0_p (PATTERN (cc0_setter)) > 0))
12997 /* Move the notes and links of TEM elsewhere.
12998 This might delete other dead insns recursively.
12999 First set the pattern to something that won't use
13001 rtx old_notes = REG_NOTES (tem);
13003 PATTERN (tem) = pc_rtx;
13004 REG_NOTES (tem) = NULL;
13006 distribute_notes (old_notes, tem, tem, NULL_RTX,
13007 NULL_RTX, NULL_RTX);
13008 distribute_links (LOG_LINKS (tem));
13010 SET_INSN_DELETED (tem);
13015 /* Delete the setter too. */
13018 PATTERN (cc0_setter) = pc_rtx;
13019 old_notes = REG_NOTES (cc0_setter);
13020 REG_NOTES (cc0_setter) = NULL;
13022 distribute_notes (old_notes, cc0_setter,
13023 cc0_setter, NULL_RTX,
13024 NULL_RTX, NULL_RTX);
13025 distribute_links (LOG_LINKS (cc0_setter));
13027 SET_INSN_DELETED (cc0_setter);
13028 if (cc0_setter == i2)
13035 PUT_REG_NOTE_KIND (note, REG_UNUSED);
13037 /* If there isn't already a REG_UNUSED note, put one
13038 here. Do not place a REG_DEAD note, even if
13039 the register is also used here; that would not
13040 match the algorithm used in lifetime analysis
13041 and can cause the consistency check in the
13042 scheduler to fail. */
13043 if (! find_regno_note (tem, REG_UNUSED,
13044 REGNO (XEXP (note, 0))))
13049 else if (reg_referenced_p (XEXP (note, 0), PATTERN (tem))
13051 && find_reg_fusage (tem, USE, XEXP (note, 0))))
13055 /* If we are doing a 3->2 combination, and we have a
13056 register which formerly died in i3 and was not used
13057 by i2, which now no longer dies in i3 and is used in
13058 i2 but does not die in i2, and place is between i2
13059 and i3, then we may need to move a link from place to
13061 if (i2 && DF_INSN_LUID (place) > DF_INSN_LUID (i2)
13063 && DF_INSN_LUID (from_insn) > DF_INSN_LUID (i2)
13064 && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
13066 rtx links = LOG_LINKS (place);
13067 LOG_LINKS (place) = 0;
13068 distribute_links (links);
13073 if (tem == BB_HEAD (bb))
13079 /* If the register is set or already dead at PLACE, we needn't do
13080 anything with this note if it is still a REG_DEAD note.
13081 We check here if it is set at all, not if is it totally replaced,
13082 which is what `dead_or_set_p' checks, so also check for it being
13085 if (place && REG_NOTE_KIND (note) == REG_DEAD)
13087 unsigned int regno = REGNO (XEXP (note, 0));
13088 reg_stat_type *rsp = VEC_index (reg_stat_type, reg_stat, regno);
13090 if (dead_or_set_p (place, XEXP (note, 0))
13091 || reg_bitfield_target_p (XEXP (note, 0), PATTERN (place)))
13093 /* Unless the register previously died in PLACE, clear
13094 last_death. [I no longer understand why this is
13096 if (rsp->last_death != place)
13097 rsp->last_death = 0;
13101 rsp->last_death = place;
13103 /* If this is a death note for a hard reg that is occupying
13104 multiple registers, ensure that we are still using all
13105 parts of the object. If we find a piece of the object
13106 that is unused, we must arrange for an appropriate REG_DEAD
13107 note to be added for it. However, we can't just emit a USE
13108 and tag the note to it, since the register might actually
13109 be dead; so we recourse, and the recursive call then finds
13110 the previous insn that used this register. */
13112 if (place && regno < FIRST_PSEUDO_REGISTER
13113 && hard_regno_nregs[regno][GET_MODE (XEXP (note, 0))] > 1)
13115 unsigned int endregno = END_HARD_REGNO (XEXP (note, 0));
13119 for (i = regno; i < endregno; i++)
13120 if ((! refers_to_regno_p (i, i + 1, PATTERN (place), 0)
13121 && ! find_regno_fusage (place, USE, i))
13122 || dead_or_set_regno_p (place, i))
13127 /* Put only REG_DEAD notes for pieces that are
13128 not already dead or set. */
13130 for (i = regno; i < endregno;
13131 i += hard_regno_nregs[i][reg_raw_mode[i]])
13133 rtx piece = regno_reg_rtx[i];
13134 basic_block bb = this_basic_block;
13136 if (! dead_or_set_p (place, piece)
13137 && ! reg_bitfield_target_p (piece,
13140 rtx new_note = alloc_reg_note (REG_DEAD, piece,
13143 distribute_notes (new_note, place, place,
13144 NULL_RTX, NULL_RTX, NULL_RTX);
13146 else if (! refers_to_regno_p (i, i + 1,
13147 PATTERN (place), 0)
13148 && ! find_regno_fusage (place, USE, i))
13149 for (tem = PREV_INSN (place); ;
13150 tem = PREV_INSN (tem))
13152 if (!NONDEBUG_INSN_P (tem))
13154 if (tem == BB_HEAD (bb))
13158 if (dead_or_set_p (tem, piece)
13159 || reg_bitfield_target_p (piece,
13162 add_reg_note (tem, REG_UNUSED, piece);
13176 /* Any other notes should not be present at this point in the
13178 gcc_unreachable ();
13183 XEXP (note, 1) = REG_NOTES (place);
13184 REG_NOTES (place) = note;
13188 add_reg_note (place2, REG_NOTE_KIND (note), XEXP (note, 0));
13192 /* Similarly to above, distribute the LOG_LINKS that used to be present on
13193 I3, I2, and I1 to new locations. This is also called to add a link
13194 pointing at I3 when I3's destination is changed. */
13197 distribute_links (rtx links)
13199 rtx link, next_link;
13201 for (link = links; link; link = next_link)
13207 next_link = XEXP (link, 1);
13209 /* If the insn that this link points to is a NOTE or isn't a single
13210 set, ignore it. In the latter case, it isn't clear what we
13211 can do other than ignore the link, since we can't tell which
13212 register it was for. Such links wouldn't be used by combine
13215 It is not possible for the destination of the target of the link to
13216 have been changed by combine. The only potential of this is if we
13217 replace I3, I2, and I1 by I3 and I2. But in that case the
13218 destination of I2 also remains unchanged. */
13220 if (NOTE_P (XEXP (link, 0))
13221 || (set = single_set (XEXP (link, 0))) == 0)
13224 reg = SET_DEST (set);
13225 while (GET_CODE (reg) == SUBREG || GET_CODE (reg) == ZERO_EXTRACT
13226 || GET_CODE (reg) == STRICT_LOW_PART)
13227 reg = XEXP (reg, 0);
13229 /* A LOG_LINK is defined as being placed on the first insn that uses
13230 a register and points to the insn that sets the register. Start
13231 searching at the next insn after the target of the link and stop
13232 when we reach a set of the register or the end of the basic block.
13234 Note that this correctly handles the link that used to point from
13235 I3 to I2. Also note that not much searching is typically done here
13236 since most links don't point very far away. */
13238 for (insn = NEXT_INSN (XEXP (link, 0));
13239 (insn && (this_basic_block->next_bb == EXIT_BLOCK_PTR
13240 || BB_HEAD (this_basic_block->next_bb) != insn));
13241 insn = NEXT_INSN (insn))
13242 if (DEBUG_INSN_P (insn))
13244 else if (INSN_P (insn) && reg_overlap_mentioned_p (reg, PATTERN (insn)))
13246 if (reg_referenced_p (reg, PATTERN (insn)))
13250 else if (CALL_P (insn)
13251 && find_reg_fusage (insn, USE, reg))
13256 else if (INSN_P (insn) && reg_set_p (reg, insn))
13259 /* If we found a place to put the link, place it there unless there
13260 is already a link to the same insn as LINK at that point. */
13266 for (link2 = LOG_LINKS (place); link2; link2 = XEXP (link2, 1))
13267 if (XEXP (link2, 0) == XEXP (link, 0))
13272 XEXP (link, 1) = LOG_LINKS (place);
13273 LOG_LINKS (place) = link;
13275 /* Set added_links_insn to the earliest insn we added a
13277 if (added_links_insn == 0
13278 || DF_INSN_LUID (added_links_insn) > DF_INSN_LUID (place))
13279 added_links_insn = place;
13285 /* Subroutine of unmentioned_reg_p and callback from for_each_rtx.
13286 Check whether the expression pointer to by LOC is a register or
13287 memory, and if so return 1 if it isn't mentioned in the rtx EXPR.
13288 Otherwise return zero. */
13291 unmentioned_reg_p_1 (rtx *loc, void *expr)
13296 && (REG_P (x) || MEM_P (x))
13297 && ! reg_mentioned_p (x, (rtx) expr))
13302 /* Check for any register or memory mentioned in EQUIV that is not
13303 mentioned in EXPR. This is used to restrict EQUIV to "specializations"
13304 of EXPR where some registers may have been replaced by constants. */
13307 unmentioned_reg_p (rtx equiv, rtx expr)
13309 return for_each_rtx (&equiv, unmentioned_reg_p_1, expr);
13313 dump_combine_stats (FILE *file)
13317 ";; Combiner statistics: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n\n",
13318 combine_attempts, combine_merges, combine_extras, combine_successes);
13322 dump_combine_total_stats (FILE *file)
13326 "\n;; Combiner totals: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n",
13327 total_attempts, total_merges, total_extras, total_successes);
13331 gate_handle_combine (void)
13333 return (optimize > 0);
13336 /* Try combining insns through substitution. */
13337 static unsigned int
13338 rest_of_handle_combine (void)
13340 int rebuild_jump_labels_after_combine;
13342 df_set_flags (DF_LR_RUN_DCE + DF_DEFER_INSN_RESCAN);
13343 df_note_add_problem ();
13346 regstat_init_n_sets_and_refs ();
13348 rebuild_jump_labels_after_combine
13349 = combine_instructions (get_insns (), max_reg_num ());
13351 /* Combining insns may have turned an indirect jump into a
13352 direct jump. Rebuild the JUMP_LABEL fields of jumping
13354 if (rebuild_jump_labels_after_combine)
13356 timevar_push (TV_JUMP);
13357 rebuild_jump_labels (get_insns ());
13359 timevar_pop (TV_JUMP);
13362 regstat_free_n_sets_and_refs ();
13366 struct rtl_opt_pass pass_combine =
13370 "combine", /* name */
13371 gate_handle_combine, /* gate */
13372 rest_of_handle_combine, /* execute */
13375 0, /* static_pass_number */
13376 TV_COMBINE, /* tv_id */
13377 PROP_cfglayout, /* properties_required */
13378 0, /* properties_provided */
13379 0, /* properties_destroyed */
13380 0, /* todo_flags_start */
13382 TODO_df_finish | TODO_verify_rtl_sharing |
13383 TODO_ggc_collect, /* todo_flags_finish */
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