1 /* Optimize by combining instructions for GNU compiler.
2 Copyright (C) 1987, 1988, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003, 2004, 2005 Free Software Foundation, Inc.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it under
8 the terms of the GNU General Public License as published by the Free
9 Software Foundation; either version 2, or (at your option) any later
12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING. If not, write to the Free
19 Software Foundation, 51 Franklin Street, Fifth Floor, Boston, MA
22 /* This module is essentially the "combiner" phase of the U. of Arizona
23 Portable Optimizer, but redone to work on our list-structured
24 representation for RTL instead of their string representation.
26 The LOG_LINKS of each insn identify the most recent assignment
27 to each REG used in the insn. It is a list of previous insns,
28 each of which contains a SET for a REG that is used in this insn
29 and not used or set in between. LOG_LINKs never cross basic blocks.
30 They were set up by the preceding pass (lifetime analysis).
32 We try to combine each pair of insns joined by a logical link.
33 We also try to combine triples of insns A, B and C when
34 C has a link back to B and B has a link back to A.
36 LOG_LINKS does not have links for use of the CC0. They don't
37 need to, because the insn that sets the CC0 is always immediately
38 before the insn that tests it. So we always regard a branch
39 insn as having a logical link to the preceding insn. The same is true
40 for an insn explicitly using CC0.
42 We check (with use_crosses_set_p) to avoid combining in such a way
43 as to move a computation to a place where its value would be different.
45 Combination is done by mathematically substituting the previous
46 insn(s) values for the regs they set into the expressions in
47 the later insns that refer to these regs. If the result is a valid insn
48 for our target machine, according to the machine description,
49 we install it, delete the earlier insns, and update the data flow
50 information (LOG_LINKS and REG_NOTES) for what we did.
52 There are a few exceptions where the dataflow information created by
53 flow.c aren't completely updated:
55 - reg_live_length is not updated
56 - reg_n_refs is not adjusted in the rare case when a register is
57 no longer required in a computation
58 - there are extremely rare cases (see distribute_notes) when a
60 - a LOG_LINKS entry that refers to an insn with multiple SETs may be
61 removed because there is no way to know which register it was
64 To simplify substitution, we combine only when the earlier insn(s)
65 consist of only a single assignment. To simplify updating afterward,
66 we never combine when a subroutine call appears in the middle.
68 Since we do not represent assignments to CC0 explicitly except when that
69 is all an insn does, there is no LOG_LINKS entry in an insn that uses
70 the condition code for the insn that set the condition code.
71 Fortunately, these two insns must be consecutive.
72 Therefore, every JUMP_INSN is taken to have an implicit logical link
73 to the preceding insn. This is not quite right, since non-jumps can
74 also use the condition code; but in practice such insns would not
79 #include "coretypes.h"
86 #include "hard-reg-set.h"
87 #include "basic-block.h"
88 #include "insn-config.h"
90 /* Include expr.h after insn-config.h so we get HAVE_conditional_move. */
92 #include "insn-attr.h"
98 #include "insn-codes.h"
99 #include "rtlhooks-def.h"
100 /* Include output.h for dump_file. */
104 #include "tree-pass.h"
106 /* Number of attempts to combine instructions in this function. */
108 static int combine_attempts;
110 /* Number of attempts that got as far as substitution in this function. */
112 static int combine_merges;
114 /* Number of instructions combined with added SETs in this function. */
116 static int combine_extras;
118 /* Number of instructions combined in this function. */
120 static int combine_successes;
122 /* Totals over entire compilation. */
124 static int total_attempts, total_merges, total_extras, total_successes;
127 /* Vector mapping INSN_UIDs to cuids.
128 The cuids are like uids but increase monotonically always.
129 Combine always uses cuids so that it can compare them.
130 But actually renumbering the uids, which we used to do,
131 proves to be a bad idea because it makes it hard to compare
132 the dumps produced by earlier passes with those from later passes. */
134 static int *uid_cuid;
135 static int max_uid_cuid;
137 /* Get the cuid of an insn. */
139 #define INSN_CUID(INSN) \
140 (INSN_UID (INSN) > max_uid_cuid ? insn_cuid (INSN) : uid_cuid[INSN_UID (INSN)])
142 /* In case BITS_PER_WORD == HOST_BITS_PER_WIDE_INT, shifting by
143 BITS_PER_WORD would invoke undefined behavior. Work around it. */
145 #define UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD(val) \
146 (((unsigned HOST_WIDE_INT) (val) << (BITS_PER_WORD - 1)) << 1)
148 /* Maximum register number, which is the size of the tables below. */
150 static unsigned int combine_max_regno;
153 /* Record last point of death of (hard or pseudo) register n. */
156 /* Record last point of modification of (hard or pseudo) register n. */
159 /* The next group of fields allows the recording of the last value assigned
160 to (hard or pseudo) register n. We use this information to see if an
161 operation being processed is redundant given a prior operation performed
162 on the register. For example, an `and' with a constant is redundant if
163 all the zero bits are already known to be turned off.
165 We use an approach similar to that used by cse, but change it in the
168 (1) We do not want to reinitialize at each label.
169 (2) It is useful, but not critical, to know the actual value assigned
170 to a register. Often just its form is helpful.
172 Therefore, we maintain the following fields:
174 last_set_value the last value assigned
175 last_set_label records the value of label_tick when the
176 register was assigned
177 last_set_table_tick records the value of label_tick when a
178 value using the register is assigned
179 last_set_invalid set to nonzero when it is not valid
180 to use the value of this register in some
183 To understand the usage of these tables, it is important to understand
184 the distinction between the value in last_set_value being valid and
185 the register being validly contained in some other expression in the
188 (The next two parameters are out of date).
190 reg_stat[i].last_set_value is valid if it is nonzero, and either
191 reg_n_sets[i] is 1 or reg_stat[i].last_set_label == label_tick.
193 Register I may validly appear in any expression returned for the value
194 of another register if reg_n_sets[i] is 1. It may also appear in the
195 value for register J if reg_stat[j].last_set_invalid is zero, or
196 reg_stat[i].last_set_label < reg_stat[j].last_set_label.
198 If an expression is found in the table containing a register which may
199 not validly appear in an expression, the register is replaced by
200 something that won't match, (clobber (const_int 0)). */
202 /* Record last value assigned to (hard or pseudo) register n. */
206 /* Record the value of label_tick when an expression involving register n
207 is placed in last_set_value. */
209 int last_set_table_tick;
211 /* Record the value of label_tick when the value for register n is placed in
216 /* These fields are maintained in parallel with last_set_value and are
217 used to store the mode in which the register was last set, the bits
218 that were known to be zero when it was last set, and the number of
219 sign bits copies it was known to have when it was last set. */
221 unsigned HOST_WIDE_INT last_set_nonzero_bits;
222 char last_set_sign_bit_copies;
223 ENUM_BITFIELD(machine_mode) last_set_mode : 8;
225 /* Set nonzero if references to register n in expressions should not be
226 used. last_set_invalid is set nonzero when this register is being
227 assigned to and last_set_table_tick == label_tick. */
229 char last_set_invalid;
231 /* Some registers that are set more than once and used in more than one
232 basic block are nevertheless always set in similar ways. For example,
233 a QImode register may be loaded from memory in two places on a machine
234 where byte loads zero extend.
236 We record in the following fields if a register has some leading bits
237 that are always equal to the sign bit, and what we know about the
238 nonzero bits of a register, specifically which bits are known to be
241 If an entry is zero, it means that we don't know anything special. */
243 unsigned char sign_bit_copies;
245 unsigned HOST_WIDE_INT nonzero_bits;
248 static struct reg_stat *reg_stat;
250 /* Record the cuid of the last insn that invalidated memory
251 (anything that writes memory, and subroutine calls, but not pushes). */
253 static int mem_last_set;
255 /* Record the cuid of the last CALL_INSN
256 so we can tell whether a potential combination crosses any calls. */
258 static int last_call_cuid;
260 /* When `subst' is called, this is the insn that is being modified
261 (by combining in a previous insn). The PATTERN of this insn
262 is still the old pattern partially modified and it should not be
263 looked at, but this may be used to examine the successors of the insn
264 to judge whether a simplification is valid. */
266 static rtx subst_insn;
268 /* This is the lowest CUID that `subst' is currently dealing with.
269 get_last_value will not return a value if the register was set at or
270 after this CUID. If not for this mechanism, we could get confused if
271 I2 or I1 in try_combine were an insn that used the old value of a register
272 to obtain a new value. In that case, we might erroneously get the
273 new value of the register when we wanted the old one. */
275 static int subst_low_cuid;
277 /* This contains any hard registers that are used in newpat; reg_dead_at_p
278 must consider all these registers to be always live. */
280 static HARD_REG_SET newpat_used_regs;
282 /* This is an insn to which a LOG_LINKS entry has been added. If this
283 insn is the earlier than I2 or I3, combine should rescan starting at
286 static rtx added_links_insn;
288 /* Basic block in which we are performing combines. */
289 static basic_block this_basic_block;
291 /* A bitmap indicating which blocks had registers go dead at entry.
292 After combine, we'll need to re-do global life analysis with
293 those blocks as starting points. */
294 static sbitmap refresh_blocks;
296 /* The following array records the insn_rtx_cost for every insn
297 in the instruction stream. */
299 static int *uid_insn_cost;
301 /* Length of the currently allocated uid_insn_cost array. */
303 static int last_insn_cost;
305 /* Incremented for each label. */
307 static int label_tick;
309 /* Mode used to compute significance in reg_stat[].nonzero_bits. It is the
310 largest integer mode that can fit in HOST_BITS_PER_WIDE_INT. */
312 static enum machine_mode nonzero_bits_mode;
314 /* Nonzero when reg_stat[].nonzero_bits and reg_stat[].sign_bit_copies can
315 be safely used. It is zero while computing them and after combine has
316 completed. This former test prevents propagating values based on
317 previously set values, which can be incorrect if a variable is modified
320 static int nonzero_sign_valid;
323 /* Record one modification to rtl structure
324 to be undone by storing old_contents into *where.
325 is_int is 1 if the contents are an int. */
331 union {rtx r; int i;} old_contents;
332 union {rtx *r; int *i;} where;
335 /* Record a bunch of changes to be undone, up to MAX_UNDO of them.
336 num_undo says how many are currently recorded.
338 other_insn is nonzero if we have modified some other insn in the process
339 of working on subst_insn. It must be verified too. */
348 static struct undobuf undobuf;
350 /* Number of times the pseudo being substituted for
351 was found and replaced. */
353 static int n_occurrences;
355 static rtx reg_nonzero_bits_for_combine (rtx, enum machine_mode, rtx,
357 unsigned HOST_WIDE_INT,
358 unsigned HOST_WIDE_INT *);
359 static rtx reg_num_sign_bit_copies_for_combine (rtx, enum machine_mode, rtx,
361 unsigned int, unsigned int *);
362 static void do_SUBST (rtx *, rtx);
363 static void do_SUBST_INT (int *, int);
364 static void init_reg_last (void);
365 static void setup_incoming_promotions (void);
366 static void set_nonzero_bits_and_sign_copies (rtx, rtx, void *);
367 static int cant_combine_insn_p (rtx);
368 static int can_combine_p (rtx, rtx, rtx, rtx, rtx *, rtx *);
369 static int combinable_i3pat (rtx, rtx *, rtx, rtx, int, rtx *);
370 static int contains_muldiv (rtx);
371 static rtx try_combine (rtx, rtx, rtx, int *);
372 static void undo_all (void);
373 static void undo_commit (void);
374 static rtx *find_split_point (rtx *, rtx);
375 static rtx subst (rtx, rtx, rtx, int, int);
376 static rtx combine_simplify_rtx (rtx, enum machine_mode, int);
377 static rtx simplify_if_then_else (rtx);
378 static rtx simplify_set (rtx);
379 static rtx simplify_logical (rtx);
380 static rtx expand_compound_operation (rtx);
381 static rtx expand_field_assignment (rtx);
382 static rtx make_extraction (enum machine_mode, rtx, HOST_WIDE_INT,
383 rtx, unsigned HOST_WIDE_INT, int, int, int);
384 static rtx extract_left_shift (rtx, int);
385 static rtx make_compound_operation (rtx, enum rtx_code);
386 static int get_pos_from_mask (unsigned HOST_WIDE_INT,
387 unsigned HOST_WIDE_INT *);
388 static rtx canon_reg_for_combine (rtx, rtx);
389 static rtx force_to_mode (rtx, enum machine_mode,
390 unsigned HOST_WIDE_INT, int);
391 static rtx if_then_else_cond (rtx, rtx *, rtx *);
392 static rtx known_cond (rtx, enum rtx_code, rtx, rtx);
393 static int rtx_equal_for_field_assignment_p (rtx, rtx);
394 static rtx make_field_assignment (rtx);
395 static rtx apply_distributive_law (rtx);
396 static rtx distribute_and_simplify_rtx (rtx, int);
397 static rtx simplify_and_const_int (rtx, enum machine_mode, rtx,
398 unsigned HOST_WIDE_INT);
399 static int merge_outer_ops (enum rtx_code *, HOST_WIDE_INT *, enum rtx_code,
400 HOST_WIDE_INT, enum machine_mode, int *);
401 static rtx simplify_shift_const (rtx, enum rtx_code, enum machine_mode, rtx,
403 static int recog_for_combine (rtx *, rtx, rtx *);
404 static rtx gen_lowpart_for_combine (enum machine_mode, rtx);
405 static enum rtx_code simplify_comparison (enum rtx_code, rtx *, rtx *);
406 static void update_table_tick (rtx);
407 static void record_value_for_reg (rtx, rtx, rtx);
408 static void check_promoted_subreg (rtx, rtx);
409 static void record_dead_and_set_regs_1 (rtx, rtx, void *);
410 static void record_dead_and_set_regs (rtx);
411 static int get_last_value_validate (rtx *, rtx, int, int);
412 static rtx get_last_value (rtx);
413 static int use_crosses_set_p (rtx, int);
414 static void reg_dead_at_p_1 (rtx, rtx, void *);
415 static int reg_dead_at_p (rtx, rtx);
416 static void move_deaths (rtx, rtx, int, rtx, rtx *);
417 static int reg_bitfield_target_p (rtx, rtx);
418 static void distribute_notes (rtx, rtx, rtx, rtx, rtx, rtx);
419 static void distribute_links (rtx);
420 static void mark_used_regs_combine (rtx);
421 static int insn_cuid (rtx);
422 static void record_promoted_value (rtx, rtx);
423 static int unmentioned_reg_p_1 (rtx *, void *);
424 static bool unmentioned_reg_p (rtx, rtx);
427 /* It is not safe to use ordinary gen_lowpart in combine.
428 See comments in gen_lowpart_for_combine. */
429 #undef RTL_HOOKS_GEN_LOWPART
430 #define RTL_HOOKS_GEN_LOWPART gen_lowpart_for_combine
432 /* Our implementation of gen_lowpart never emits a new pseudo. */
433 #undef RTL_HOOKS_GEN_LOWPART_NO_EMIT
434 #define RTL_HOOKS_GEN_LOWPART_NO_EMIT gen_lowpart_for_combine
436 #undef RTL_HOOKS_REG_NONZERO_REG_BITS
437 #define RTL_HOOKS_REG_NONZERO_REG_BITS reg_nonzero_bits_for_combine
439 #undef RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES
440 #define RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES reg_num_sign_bit_copies_for_combine
442 static const struct rtl_hooks combine_rtl_hooks = RTL_HOOKS_INITIALIZER;
445 /* Substitute NEWVAL, an rtx expression, into INTO, a place in some
446 insn. The substitution can be undone by undo_all. If INTO is already
447 set to NEWVAL, do not record this change. Because computing NEWVAL might
448 also call SUBST, we have to compute it before we put anything into
452 do_SUBST (rtx *into, rtx newval)
457 if (oldval == newval)
460 /* We'd like to catch as many invalid transformations here as
461 possible. Unfortunately, there are way too many mode changes
462 that are perfectly valid, so we'd waste too much effort for
463 little gain doing the checks here. Focus on catching invalid
464 transformations involving integer constants. */
465 if (GET_MODE_CLASS (GET_MODE (oldval)) == MODE_INT
466 && GET_CODE (newval) == CONST_INT)
468 /* Sanity check that we're replacing oldval with a CONST_INT
469 that is a valid sign-extension for the original mode. */
470 gcc_assert (INTVAL (newval)
471 == trunc_int_for_mode (INTVAL (newval), GET_MODE (oldval)));
473 /* Replacing the operand of a SUBREG or a ZERO_EXTEND with a
474 CONST_INT is not valid, because after the replacement, the
475 original mode would be gone. Unfortunately, we can't tell
476 when do_SUBST is called to replace the operand thereof, so we
477 perform this test on oldval instead, checking whether an
478 invalid replacement took place before we got here. */
479 gcc_assert (!(GET_CODE (oldval) == SUBREG
480 && GET_CODE (SUBREG_REG (oldval)) == CONST_INT));
481 gcc_assert (!(GET_CODE (oldval) == ZERO_EXTEND
482 && GET_CODE (XEXP (oldval, 0)) == CONST_INT));
486 buf = undobuf.frees, undobuf.frees = buf->next;
488 buf = xmalloc (sizeof (struct undo));
492 buf->old_contents.r = oldval;
495 buf->next = undobuf.undos, undobuf.undos = buf;
498 #define SUBST(INTO, NEWVAL) do_SUBST(&(INTO), (NEWVAL))
500 /* Similar to SUBST, but NEWVAL is an int expression. Note that substitution
501 for the value of a HOST_WIDE_INT value (including CONST_INT) is
505 do_SUBST_INT (int *into, int newval)
510 if (oldval == newval)
514 buf = undobuf.frees, undobuf.frees = buf->next;
516 buf = xmalloc (sizeof (struct undo));
520 buf->old_contents.i = oldval;
523 buf->next = undobuf.undos, undobuf.undos = buf;
526 #define SUBST_INT(INTO, NEWVAL) do_SUBST_INT(&(INTO), (NEWVAL))
528 /* Subroutine of try_combine. Determine whether the combine replacement
529 patterns NEWPAT and NEWI2PAT are cheaper according to insn_rtx_cost
530 that the original instruction sequence I1, I2 and I3. Note that I1
531 and/or NEWI2PAT may be NULL_RTX. This function returns false, if the
532 costs of all instructions can be estimated, and the replacements are
533 more expensive than the original sequence. */
536 combine_validate_cost (rtx i1, rtx i2, rtx i3, rtx newpat, rtx newi2pat)
538 int i1_cost, i2_cost, i3_cost;
539 int new_i2_cost, new_i3_cost;
540 int old_cost, new_cost;
542 /* Lookup the original insn_rtx_costs. */
543 i2_cost = INSN_UID (i2) <= last_insn_cost
544 ? uid_insn_cost[INSN_UID (i2)] : 0;
545 i3_cost = INSN_UID (i3) <= last_insn_cost
546 ? uid_insn_cost[INSN_UID (i3)] : 0;
550 i1_cost = INSN_UID (i1) <= last_insn_cost
551 ? uid_insn_cost[INSN_UID (i1)] : 0;
552 old_cost = (i1_cost > 0 && i2_cost > 0 && i3_cost > 0)
553 ? i1_cost + i2_cost + i3_cost : 0;
557 old_cost = (i2_cost > 0 && i3_cost > 0) ? i2_cost + i3_cost : 0;
561 /* Calculate the replacement insn_rtx_costs. */
562 new_i3_cost = insn_rtx_cost (newpat);
565 new_i2_cost = insn_rtx_cost (newi2pat);
566 new_cost = (new_i2_cost > 0 && new_i3_cost > 0)
567 ? new_i2_cost + new_i3_cost : 0;
571 new_cost = new_i3_cost;
575 if (undobuf.other_insn)
577 int old_other_cost, new_other_cost;
579 old_other_cost = (INSN_UID (undobuf.other_insn) <= last_insn_cost
580 ? uid_insn_cost[INSN_UID (undobuf.other_insn)] : 0);
581 new_other_cost = insn_rtx_cost (PATTERN (undobuf.other_insn));
582 if (old_other_cost > 0 && new_other_cost > 0)
584 old_cost += old_other_cost;
585 new_cost += new_other_cost;
591 /* Disallow this recombination if both new_cost and old_cost are
592 greater than zero, and new_cost is greater than old cost. */
594 && new_cost > old_cost)
601 "rejecting combination of insns %d, %d and %d\n",
602 INSN_UID (i1), INSN_UID (i2), INSN_UID (i3));
603 fprintf (dump_file, "original costs %d + %d + %d = %d\n",
604 i1_cost, i2_cost, i3_cost, old_cost);
609 "rejecting combination of insns %d and %d\n",
610 INSN_UID (i2), INSN_UID (i3));
611 fprintf (dump_file, "original costs %d + %d = %d\n",
612 i2_cost, i3_cost, old_cost);
617 fprintf (dump_file, "replacement costs %d + %d = %d\n",
618 new_i2_cost, new_i3_cost, new_cost);
621 fprintf (dump_file, "replacement cost %d\n", new_cost);
627 /* Update the uid_insn_cost array with the replacement costs. */
628 uid_insn_cost[INSN_UID (i2)] = new_i2_cost;
629 uid_insn_cost[INSN_UID (i3)] = new_i3_cost;
631 uid_insn_cost[INSN_UID (i1)] = 0;
636 /* Main entry point for combiner. F is the first insn of the function.
637 NREGS is the first unused pseudo-reg number.
639 Return nonzero if the combiner has turned an indirect jump
640 instruction into a direct jump. */
642 combine_instructions (rtx f, unsigned int nregs)
650 rtx links, nextlinks;
651 sbitmap_iterator sbi;
653 int new_direct_jump_p = 0;
655 combine_attempts = 0;
658 combine_successes = 0;
660 combine_max_regno = nregs;
662 rtl_hooks = combine_rtl_hooks;
664 reg_stat = xcalloc (nregs, sizeof (struct reg_stat));
666 init_recog_no_volatile ();
668 /* Compute maximum uid value so uid_cuid can be allocated. */
670 for (insn = f, i = 0; insn; insn = NEXT_INSN (insn))
671 if (INSN_UID (insn) > i)
674 uid_cuid = xmalloc ((i + 1) * sizeof (int));
677 nonzero_bits_mode = mode_for_size (HOST_BITS_PER_WIDE_INT, MODE_INT, 0);
679 /* Don't use reg_stat[].nonzero_bits when computing it. This can cause
680 problems when, for example, we have j <<= 1 in a loop. */
682 nonzero_sign_valid = 0;
684 /* Compute the mapping from uids to cuids.
685 Cuids are numbers assigned to insns, like uids,
686 except that cuids increase monotonically through the code.
688 Scan all SETs and see if we can deduce anything about what
689 bits are known to be zero for some registers and how many copies
690 of the sign bit are known to exist for those registers.
692 Also set any known values so that we can use it while searching
693 for what bits are known to be set. */
697 setup_incoming_promotions ();
699 refresh_blocks = sbitmap_alloc (last_basic_block);
700 sbitmap_zero (refresh_blocks);
702 /* Allocate array of current insn_rtx_costs. */
703 uid_insn_cost = xcalloc (max_uid_cuid + 1, sizeof (int));
704 last_insn_cost = max_uid_cuid;
706 for (insn = f, i = 0; insn; insn = NEXT_INSN (insn))
708 uid_cuid[INSN_UID (insn)] = ++i;
714 note_stores (PATTERN (insn), set_nonzero_bits_and_sign_copies,
716 record_dead_and_set_regs (insn);
719 for (links = REG_NOTES (insn); links; links = XEXP (links, 1))
720 if (REG_NOTE_KIND (links) == REG_INC)
721 set_nonzero_bits_and_sign_copies (XEXP (links, 0), NULL_RTX,
725 /* Record the current insn_rtx_cost of this instruction. */
726 if (NONJUMP_INSN_P (insn))
727 uid_insn_cost[INSN_UID (insn)] = insn_rtx_cost (PATTERN (insn));
729 fprintf(dump_file, "insn_cost %d: %d\n",
730 INSN_UID (insn), uid_insn_cost[INSN_UID (insn)]);
737 nonzero_sign_valid = 1;
739 /* Now scan all the insns in forward order. */
745 setup_incoming_promotions ();
747 FOR_EACH_BB (this_basic_block)
749 for (insn = BB_HEAD (this_basic_block);
750 insn != NEXT_INSN (BB_END (this_basic_block));
751 insn = next ? next : NEXT_INSN (insn))
758 else if (INSN_P (insn))
760 /* See if we know about function return values before this
761 insn based upon SUBREG flags. */
762 check_promoted_subreg (insn, PATTERN (insn));
764 /* Try this insn with each insn it links back to. */
766 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
767 if ((next = try_combine (insn, XEXP (links, 0),
768 NULL_RTX, &new_direct_jump_p)) != 0)
771 /* Try each sequence of three linked insns ending with this one. */
773 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
775 rtx link = XEXP (links, 0);
777 /* If the linked insn has been replaced by a note, then there
778 is no point in pursuing this chain any further. */
782 for (nextlinks = LOG_LINKS (link);
784 nextlinks = XEXP (nextlinks, 1))
785 if ((next = try_combine (insn, link,
787 &new_direct_jump_p)) != 0)
792 /* Try to combine a jump insn that uses CC0
793 with a preceding insn that sets CC0, and maybe with its
794 logical predecessor as well.
795 This is how we make decrement-and-branch insns.
796 We need this special code because data flow connections
797 via CC0 do not get entered in LOG_LINKS. */
800 && (prev = prev_nonnote_insn (insn)) != 0
801 && NONJUMP_INSN_P (prev)
802 && sets_cc0_p (PATTERN (prev)))
804 if ((next = try_combine (insn, prev,
805 NULL_RTX, &new_direct_jump_p)) != 0)
808 for (nextlinks = LOG_LINKS (prev); nextlinks;
809 nextlinks = XEXP (nextlinks, 1))
810 if ((next = try_combine (insn, prev,
812 &new_direct_jump_p)) != 0)
816 /* Do the same for an insn that explicitly references CC0. */
817 if (NONJUMP_INSN_P (insn)
818 && (prev = prev_nonnote_insn (insn)) != 0
819 && NONJUMP_INSN_P (prev)
820 && sets_cc0_p (PATTERN (prev))
821 && GET_CODE (PATTERN (insn)) == SET
822 && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (insn))))
824 if ((next = try_combine (insn, prev,
825 NULL_RTX, &new_direct_jump_p)) != 0)
828 for (nextlinks = LOG_LINKS (prev); nextlinks;
829 nextlinks = XEXP (nextlinks, 1))
830 if ((next = try_combine (insn, prev,
832 &new_direct_jump_p)) != 0)
836 /* Finally, see if any of the insns that this insn links to
837 explicitly references CC0. If so, try this insn, that insn,
838 and its predecessor if it sets CC0. */
839 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
840 if (NONJUMP_INSN_P (XEXP (links, 0))
841 && GET_CODE (PATTERN (XEXP (links, 0))) == SET
842 && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (XEXP (links, 0))))
843 && (prev = prev_nonnote_insn (XEXP (links, 0))) != 0
844 && NONJUMP_INSN_P (prev)
845 && sets_cc0_p (PATTERN (prev))
846 && (next = try_combine (insn, XEXP (links, 0),
847 prev, &new_direct_jump_p)) != 0)
851 /* Try combining an insn with two different insns whose results it
853 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
854 for (nextlinks = XEXP (links, 1); nextlinks;
855 nextlinks = XEXP (nextlinks, 1))
856 if ((next = try_combine (insn, XEXP (links, 0),
858 &new_direct_jump_p)) != 0)
861 /* Try this insn with each REG_EQUAL note it links back to. */
862 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
865 rtx temp = XEXP (links, 0);
866 if ((set = single_set (temp)) != 0
867 && (note = find_reg_equal_equiv_note (temp)) != 0
868 && (note = XEXP (note, 0), GET_CODE (note)) != EXPR_LIST
869 /* Avoid using a register that may already been marked
870 dead by an earlier instruction. */
871 && ! unmentioned_reg_p (note, SET_SRC (set))
872 && (GET_MODE (note) == VOIDmode
873 ? SCALAR_INT_MODE_P (GET_MODE (SET_DEST (set)))
874 : GET_MODE (SET_DEST (set)) == GET_MODE (note)))
876 /* Temporarily replace the set's source with the
877 contents of the REG_EQUAL note. The insn will
878 be deleted or recognized by try_combine. */
879 rtx orig = SET_SRC (set);
880 SET_SRC (set) = note;
881 next = try_combine (insn, temp, NULL_RTX,
885 SET_SRC (set) = orig;
890 record_dead_and_set_regs (insn);
899 EXECUTE_IF_SET_IN_SBITMAP (refresh_blocks, 0, j, sbi)
900 BASIC_BLOCK (j)->flags |= BB_DIRTY;
901 new_direct_jump_p |= purge_all_dead_edges ();
902 delete_noop_moves ();
904 update_life_info_in_dirty_blocks (UPDATE_LIFE_GLOBAL_RM_NOTES,
905 PROP_DEATH_NOTES | PROP_SCAN_DEAD_CODE
906 | PROP_KILL_DEAD_CODE);
909 sbitmap_free (refresh_blocks);
910 free (uid_insn_cost);
915 struct undo *undo, *next;
916 for (undo = undobuf.frees; undo; undo = next)
924 total_attempts += combine_attempts;
925 total_merges += combine_merges;
926 total_extras += combine_extras;
927 total_successes += combine_successes;
929 nonzero_sign_valid = 0;
930 rtl_hooks = general_rtl_hooks;
932 /* Make recognizer allow volatile MEMs again. */
935 return new_direct_jump_p;
938 /* Wipe the last_xxx fields of reg_stat in preparation for another pass. */
944 for (i = 0; i < combine_max_regno; i++)
945 memset (reg_stat + i, 0, offsetof (struct reg_stat, sign_bit_copies));
948 /* Set up any promoted values for incoming argument registers. */
951 setup_incoming_promotions (void)
955 enum machine_mode mode;
957 rtx first = get_insns ();
959 if (targetm.calls.promote_function_args (TREE_TYPE (cfun->decl)))
961 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
962 /* Check whether this register can hold an incoming pointer
963 argument. FUNCTION_ARG_REGNO_P tests outgoing register
964 numbers, so translate if necessary due to register windows. */
965 if (FUNCTION_ARG_REGNO_P (OUTGOING_REGNO (regno))
966 && (reg = promoted_input_arg (regno, &mode, &unsignedp)) != 0)
969 (reg, first, gen_rtx_fmt_e ((unsignedp ? ZERO_EXTEND
972 gen_rtx_CLOBBER (mode, const0_rtx)));
977 /* Called via note_stores. If X is a pseudo that is narrower than
978 HOST_BITS_PER_WIDE_INT and is being set, record what bits are known zero.
980 If we are setting only a portion of X and we can't figure out what
981 portion, assume all bits will be used since we don't know what will
984 Similarly, set how many bits of X are known to be copies of the sign bit
985 at all locations in the function. This is the smallest number implied
989 set_nonzero_bits_and_sign_copies (rtx x, rtx set,
990 void *data ATTRIBUTE_UNUSED)
995 && REGNO (x) >= FIRST_PSEUDO_REGISTER
996 /* If this register is undefined at the start of the file, we can't
997 say what its contents were. */
999 (ENTRY_BLOCK_PTR->next_bb->il.rtl->global_live_at_start, REGNO (x))
1000 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT)
1002 if (set == 0 || GET_CODE (set) == CLOBBER)
1004 reg_stat[REGNO (x)].nonzero_bits = GET_MODE_MASK (GET_MODE (x));
1005 reg_stat[REGNO (x)].sign_bit_copies = 1;
1009 /* If this is a complex assignment, see if we can convert it into a
1010 simple assignment. */
1011 set = expand_field_assignment (set);
1013 /* If this is a simple assignment, or we have a paradoxical SUBREG,
1014 set what we know about X. */
1016 if (SET_DEST (set) == x
1017 || (GET_CODE (SET_DEST (set)) == SUBREG
1018 && (GET_MODE_SIZE (GET_MODE (SET_DEST (set)))
1019 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (set)))))
1020 && SUBREG_REG (SET_DEST (set)) == x))
1022 rtx src = SET_SRC (set);
1024 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
1025 /* If X is narrower than a word and SRC is a non-negative
1026 constant that would appear negative in the mode of X,
1027 sign-extend it for use in reg_stat[].nonzero_bits because some
1028 machines (maybe most) will actually do the sign-extension
1029 and this is the conservative approach.
1031 ??? For 2.5, try to tighten up the MD files in this regard
1032 instead of this kludge. */
1034 if (GET_MODE_BITSIZE (GET_MODE (x)) < BITS_PER_WORD
1035 && GET_CODE (src) == CONST_INT
1037 && 0 != (INTVAL (src)
1038 & ((HOST_WIDE_INT) 1
1039 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
1040 src = GEN_INT (INTVAL (src)
1041 | ((HOST_WIDE_INT) (-1)
1042 << GET_MODE_BITSIZE (GET_MODE (x))));
1045 /* Don't call nonzero_bits if it cannot change anything. */
1046 if (reg_stat[REGNO (x)].nonzero_bits != ~(unsigned HOST_WIDE_INT) 0)
1047 reg_stat[REGNO (x)].nonzero_bits
1048 |= nonzero_bits (src, nonzero_bits_mode);
1049 num = num_sign_bit_copies (SET_SRC (set), GET_MODE (x));
1050 if (reg_stat[REGNO (x)].sign_bit_copies == 0
1051 || reg_stat[REGNO (x)].sign_bit_copies > num)
1052 reg_stat[REGNO (x)].sign_bit_copies = num;
1056 reg_stat[REGNO (x)].nonzero_bits = GET_MODE_MASK (GET_MODE (x));
1057 reg_stat[REGNO (x)].sign_bit_copies = 1;
1062 /* See if INSN can be combined into I3. PRED and SUCC are optionally
1063 insns that were previously combined into I3 or that will be combined
1064 into the merger of INSN and I3.
1066 Return 0 if the combination is not allowed for any reason.
1068 If the combination is allowed, *PDEST will be set to the single
1069 destination of INSN and *PSRC to the single source, and this function
1073 can_combine_p (rtx insn, rtx i3, rtx pred ATTRIBUTE_UNUSED, rtx succ,
1074 rtx *pdest, rtx *psrc)
1077 rtx set = 0, src, dest;
1082 int all_adjacent = (succ ? (next_active_insn (insn) == succ
1083 && next_active_insn (succ) == i3)
1084 : next_active_insn (insn) == i3);
1086 /* Can combine only if previous insn is a SET of a REG, a SUBREG or CC0.
1087 or a PARALLEL consisting of such a SET and CLOBBERs.
1089 If INSN has CLOBBER parallel parts, ignore them for our processing.
1090 By definition, these happen during the execution of the insn. When it
1091 is merged with another insn, all bets are off. If they are, in fact,
1092 needed and aren't also supplied in I3, they may be added by
1093 recog_for_combine. Otherwise, it won't match.
1095 We can also ignore a SET whose SET_DEST is mentioned in a REG_UNUSED
1098 Get the source and destination of INSN. If more than one, can't
1101 if (GET_CODE (PATTERN (insn)) == SET)
1102 set = PATTERN (insn);
1103 else if (GET_CODE (PATTERN (insn)) == PARALLEL
1104 && GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == SET)
1106 for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
1108 rtx elt = XVECEXP (PATTERN (insn), 0, i);
1111 switch (GET_CODE (elt))
1113 /* This is important to combine floating point insns
1114 for the SH4 port. */
1116 /* Combining an isolated USE doesn't make sense.
1117 We depend here on combinable_i3pat to reject them. */
1118 /* The code below this loop only verifies that the inputs of
1119 the SET in INSN do not change. We call reg_set_between_p
1120 to verify that the REG in the USE does not change between
1122 If the USE in INSN was for a pseudo register, the matching
1123 insn pattern will likely match any register; combining this
1124 with any other USE would only be safe if we knew that the
1125 used registers have identical values, or if there was
1126 something to tell them apart, e.g. different modes. For
1127 now, we forgo such complicated tests and simply disallow
1128 combining of USES of pseudo registers with any other USE. */
1129 if (REG_P (XEXP (elt, 0))
1130 && GET_CODE (PATTERN (i3)) == PARALLEL)
1132 rtx i3pat = PATTERN (i3);
1133 int i = XVECLEN (i3pat, 0) - 1;
1134 unsigned int regno = REGNO (XEXP (elt, 0));
1138 rtx i3elt = XVECEXP (i3pat, 0, i);
1140 if (GET_CODE (i3elt) == USE
1141 && REG_P (XEXP (i3elt, 0))
1142 && (REGNO (XEXP (i3elt, 0)) == regno
1143 ? reg_set_between_p (XEXP (elt, 0),
1144 PREV_INSN (insn), i3)
1145 : regno >= FIRST_PSEUDO_REGISTER))
1152 /* We can ignore CLOBBERs. */
1157 /* Ignore SETs whose result isn't used but not those that
1158 have side-effects. */
1159 if (find_reg_note (insn, REG_UNUSED, SET_DEST (elt))
1160 && (!(note = find_reg_note (insn, REG_EH_REGION, NULL_RTX))
1161 || INTVAL (XEXP (note, 0)) <= 0)
1162 && ! side_effects_p (elt))
1165 /* If we have already found a SET, this is a second one and
1166 so we cannot combine with this insn. */
1174 /* Anything else means we can't combine. */
1180 /* If SET_SRC is an ASM_OPERANDS we can't throw away these CLOBBERs,
1181 so don't do anything with it. */
1182 || GET_CODE (SET_SRC (set)) == ASM_OPERANDS)
1191 set = expand_field_assignment (set);
1192 src = SET_SRC (set), dest = SET_DEST (set);
1194 /* Don't eliminate a store in the stack pointer. */
1195 if (dest == stack_pointer_rtx
1196 /* Don't combine with an insn that sets a register to itself if it has
1197 a REG_EQUAL note. This may be part of a REG_NO_CONFLICT sequence. */
1198 || (rtx_equal_p (src, dest) && find_reg_note (insn, REG_EQUAL, NULL_RTX))
1199 /* Can't merge an ASM_OPERANDS. */
1200 || GET_CODE (src) == ASM_OPERANDS
1201 /* Can't merge a function call. */
1202 || GET_CODE (src) == CALL
1203 /* Don't eliminate a function call argument. */
1205 && (find_reg_fusage (i3, USE, dest)
1207 && REGNO (dest) < FIRST_PSEUDO_REGISTER
1208 && global_regs[REGNO (dest)])))
1209 /* Don't substitute into an incremented register. */
1210 || FIND_REG_INC_NOTE (i3, dest)
1211 || (succ && FIND_REG_INC_NOTE (succ, dest))
1212 /* Don't substitute into a non-local goto, this confuses CFG. */
1213 || (JUMP_P (i3) && find_reg_note (i3, REG_NON_LOCAL_GOTO, NULL_RTX))
1215 /* Don't combine the end of a libcall into anything. */
1216 /* ??? This gives worse code, and appears to be unnecessary, since no
1217 pass after flow uses REG_LIBCALL/REG_RETVAL notes. Local-alloc does
1218 use REG_RETVAL notes for noconflict blocks, but other code here
1219 makes sure that those insns don't disappear. */
1220 || find_reg_note (insn, REG_RETVAL, NULL_RTX)
1222 /* Make sure that DEST is not used after SUCC but before I3. */
1223 || (succ && ! all_adjacent
1224 && reg_used_between_p (dest, succ, i3))
1225 /* Make sure that the value that is to be substituted for the register
1226 does not use any registers whose values alter in between. However,
1227 If the insns are adjacent, a use can't cross a set even though we
1228 think it might (this can happen for a sequence of insns each setting
1229 the same destination; last_set of that register might point to
1230 a NOTE). If INSN has a REG_EQUIV note, the register is always
1231 equivalent to the memory so the substitution is valid even if there
1232 are intervening stores. Also, don't move a volatile asm or
1233 UNSPEC_VOLATILE across any other insns. */
1236 || ! find_reg_note (insn, REG_EQUIV, src))
1237 && use_crosses_set_p (src, INSN_CUID (insn)))
1238 || (GET_CODE (src) == ASM_OPERANDS && MEM_VOLATILE_P (src))
1239 || GET_CODE (src) == UNSPEC_VOLATILE))
1240 /* If there is a REG_NO_CONFLICT note for DEST in I3 or SUCC, we get
1241 better register allocation by not doing the combine. */
1242 || find_reg_note (i3, REG_NO_CONFLICT, dest)
1243 || (succ && find_reg_note (succ, REG_NO_CONFLICT, dest))
1244 /* Don't combine across a CALL_INSN, because that would possibly
1245 change whether the life span of some REGs crosses calls or not,
1246 and it is a pain to update that information.
1247 Exception: if source is a constant, moving it later can't hurt.
1248 Accept that special case, because it helps -fforce-addr a lot. */
1249 || (INSN_CUID (insn) < last_call_cuid && ! CONSTANT_P (src)))
1252 /* DEST must either be a REG or CC0. */
1255 /* If register alignment is being enforced for multi-word items in all
1256 cases except for parameters, it is possible to have a register copy
1257 insn referencing a hard register that is not allowed to contain the
1258 mode being copied and which would not be valid as an operand of most
1259 insns. Eliminate this problem by not combining with such an insn.
1261 Also, on some machines we don't want to extend the life of a hard
1265 && ((REGNO (dest) < FIRST_PSEUDO_REGISTER
1266 && ! HARD_REGNO_MODE_OK (REGNO (dest), GET_MODE (dest)))
1267 /* Don't extend the life of a hard register unless it is
1268 user variable (if we have few registers) or it can't
1269 fit into the desired register (meaning something special
1271 Also avoid substituting a return register into I3, because
1272 reload can't handle a conflict with constraints of other
1274 || (REGNO (src) < FIRST_PSEUDO_REGISTER
1275 && ! HARD_REGNO_MODE_OK (REGNO (src), GET_MODE (src)))))
1278 else if (GET_CODE (dest) != CC0)
1282 if (GET_CODE (PATTERN (i3)) == PARALLEL)
1283 for (i = XVECLEN (PATTERN (i3), 0) - 1; i >= 0; i--)
1284 if (GET_CODE (XVECEXP (PATTERN (i3), 0, i)) == CLOBBER)
1286 /* Don't substitute for a register intended as a clobberable
1288 rtx reg = XEXP (XVECEXP (PATTERN (i3), 0, i), 0);
1289 if (rtx_equal_p (reg, dest))
1292 /* If the clobber represents an earlyclobber operand, we must not
1293 substitute an expression containing the clobbered register.
1294 As we do not analyze the constraint strings here, we have to
1295 make the conservative assumption. However, if the register is
1296 a fixed hard reg, the clobber cannot represent any operand;
1297 we leave it up to the machine description to either accept or
1298 reject use-and-clobber patterns. */
1300 || REGNO (reg) >= FIRST_PSEUDO_REGISTER
1301 || !fixed_regs[REGNO (reg)])
1302 if (reg_overlap_mentioned_p (reg, src))
1306 /* If INSN contains anything volatile, or is an `asm' (whether volatile
1307 or not), reject, unless nothing volatile comes between it and I3 */
1309 if (GET_CODE (src) == ASM_OPERANDS || volatile_refs_p (src))
1311 /* Make sure succ doesn't contain a volatile reference. */
1312 if (succ != 0 && volatile_refs_p (PATTERN (succ)))
1315 for (p = NEXT_INSN (insn); p != i3; p = NEXT_INSN (p))
1316 if (INSN_P (p) && p != succ && volatile_refs_p (PATTERN (p)))
1320 /* If INSN is an asm, and DEST is a hard register, reject, since it has
1321 to be an explicit register variable, and was chosen for a reason. */
1323 if (GET_CODE (src) == ASM_OPERANDS
1324 && REG_P (dest) && REGNO (dest) < FIRST_PSEUDO_REGISTER)
1327 /* If there are any volatile insns between INSN and I3, reject, because
1328 they might affect machine state. */
1330 for (p = NEXT_INSN (insn); p != i3; p = NEXT_INSN (p))
1331 if (INSN_P (p) && p != succ && volatile_insn_p (PATTERN (p)))
1334 /* If INSN contains an autoincrement or autodecrement, make sure that
1335 register is not used between there and I3, and not already used in
1336 I3 either. Neither must it be used in PRED or SUCC, if they exist.
1337 Also insist that I3 not be a jump; if it were one
1338 and the incremented register were spilled, we would lose. */
1341 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
1342 if (REG_NOTE_KIND (link) == REG_INC
1344 || reg_used_between_p (XEXP (link, 0), insn, i3)
1345 || (pred != NULL_RTX
1346 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (pred)))
1347 || (succ != NULL_RTX
1348 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (succ)))
1349 || reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i3))))
1354 /* Don't combine an insn that follows a CC0-setting insn.
1355 An insn that uses CC0 must not be separated from the one that sets it.
1356 We do, however, allow I2 to follow a CC0-setting insn if that insn
1357 is passed as I1; in that case it will be deleted also.
1358 We also allow combining in this case if all the insns are adjacent
1359 because that would leave the two CC0 insns adjacent as well.
1360 It would be more logical to test whether CC0 occurs inside I1 or I2,
1361 but that would be much slower, and this ought to be equivalent. */
1363 p = prev_nonnote_insn (insn);
1364 if (p && p != pred && NONJUMP_INSN_P (p) && sets_cc0_p (PATTERN (p))
1369 /* If we get here, we have passed all the tests and the combination is
1378 /* LOC is the location within I3 that contains its pattern or the component
1379 of a PARALLEL of the pattern. We validate that it is valid for combining.
1381 One problem is if I3 modifies its output, as opposed to replacing it
1382 entirely, we can't allow the output to contain I2DEST or I1DEST as doing
1383 so would produce an insn that is not equivalent to the original insns.
1387 (set (reg:DI 101) (reg:DI 100))
1388 (set (subreg:SI (reg:DI 101) 0) <foo>)
1390 This is NOT equivalent to:
1392 (parallel [(set (subreg:SI (reg:DI 100) 0) <foo>)
1393 (set (reg:DI 101) (reg:DI 100))])
1395 Not only does this modify 100 (in which case it might still be valid
1396 if 100 were dead in I2), it sets 101 to the ORIGINAL value of 100.
1398 We can also run into a problem if I2 sets a register that I1
1399 uses and I1 gets directly substituted into I3 (not via I2). In that
1400 case, we would be getting the wrong value of I2DEST into I3, so we
1401 must reject the combination. This case occurs when I2 and I1 both
1402 feed into I3, rather than when I1 feeds into I2, which feeds into I3.
1403 If I1_NOT_IN_SRC is nonzero, it means that finding I1 in the source
1404 of a SET must prevent combination from occurring.
1406 Before doing the above check, we first try to expand a field assignment
1407 into a set of logical operations.
1409 If PI3_DEST_KILLED is nonzero, it is a pointer to a location in which
1410 we place a register that is both set and used within I3. If more than one
1411 such register is detected, we fail.
1413 Return 1 if the combination is valid, zero otherwise. */
1416 combinable_i3pat (rtx i3, rtx *loc, rtx i2dest, rtx i1dest,
1417 int i1_not_in_src, rtx *pi3dest_killed)
1421 if (GET_CODE (x) == SET)
1424 rtx dest = SET_DEST (set);
1425 rtx src = SET_SRC (set);
1426 rtx inner_dest = dest;
1429 while (GET_CODE (inner_dest) == STRICT_LOW_PART
1430 || GET_CODE (inner_dest) == SUBREG
1431 || GET_CODE (inner_dest) == ZERO_EXTRACT)
1432 inner_dest = XEXP (inner_dest, 0);
1434 /* Check for the case where I3 modifies its output, as discussed
1435 above. We don't want to prevent pseudos from being combined
1436 into the address of a MEM, so only prevent the combination if
1437 i1 or i2 set the same MEM. */
1438 if ((inner_dest != dest &&
1439 (!MEM_P (inner_dest)
1440 || rtx_equal_p (i2dest, inner_dest)
1441 || (i1dest && rtx_equal_p (i1dest, inner_dest)))
1442 && (reg_overlap_mentioned_p (i2dest, inner_dest)
1443 || (i1dest && reg_overlap_mentioned_p (i1dest, inner_dest))))
1445 /* This is the same test done in can_combine_p except we can't test
1446 all_adjacent; we don't have to, since this instruction will stay
1447 in place, thus we are not considering increasing the lifetime of
1450 Also, if this insn sets a function argument, combining it with
1451 something that might need a spill could clobber a previous
1452 function argument; the all_adjacent test in can_combine_p also
1453 checks this; here, we do a more specific test for this case. */
1455 || (REG_P (inner_dest)
1456 && REGNO (inner_dest) < FIRST_PSEUDO_REGISTER
1457 && (! HARD_REGNO_MODE_OK (REGNO (inner_dest),
1458 GET_MODE (inner_dest))))
1459 || (i1_not_in_src && reg_overlap_mentioned_p (i1dest, src)))
1462 /* If DEST is used in I3, it is being killed in this insn, so
1463 record that for later. We have to consider paradoxical
1464 subregs here, since they kill the whole register, but we
1465 ignore partial subregs, STRICT_LOW_PART, etc.
1466 Never add REG_DEAD notes for the FRAME_POINTER_REGNUM or the
1467 STACK_POINTER_REGNUM, since these are always considered to be
1468 live. Similarly for ARG_POINTER_REGNUM if it is fixed. */
1470 if (GET_CODE (subdest) == SUBREG
1471 && (GET_MODE_SIZE (GET_MODE (subdest))
1472 >= GET_MODE_SIZE (GET_MODE (SUBREG_REG (subdest)))))
1473 subdest = SUBREG_REG (subdest);
1476 && reg_referenced_p (subdest, PATTERN (i3))
1477 && REGNO (subdest) != FRAME_POINTER_REGNUM
1478 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
1479 && REGNO (subdest) != HARD_FRAME_POINTER_REGNUM
1481 #if ARG_POINTER_REGNUM != FRAME_POINTER_REGNUM
1482 && (REGNO (subdest) != ARG_POINTER_REGNUM
1483 || ! fixed_regs [REGNO (subdest)])
1485 && REGNO (subdest) != STACK_POINTER_REGNUM)
1487 if (*pi3dest_killed)
1490 *pi3dest_killed = subdest;
1494 else if (GET_CODE (x) == PARALLEL)
1498 for (i = 0; i < XVECLEN (x, 0); i++)
1499 if (! combinable_i3pat (i3, &XVECEXP (x, 0, i), i2dest, i1dest,
1500 i1_not_in_src, pi3dest_killed))
1507 /* Return 1 if X is an arithmetic expression that contains a multiplication
1508 and division. We don't count multiplications by powers of two here. */
1511 contains_muldiv (rtx x)
1513 switch (GET_CODE (x))
1515 case MOD: case DIV: case UMOD: case UDIV:
1519 return ! (GET_CODE (XEXP (x, 1)) == CONST_INT
1520 && exact_log2 (INTVAL (XEXP (x, 1))) >= 0);
1523 return contains_muldiv (XEXP (x, 0))
1524 || contains_muldiv (XEXP (x, 1));
1527 return contains_muldiv (XEXP (x, 0));
1533 /* Determine whether INSN can be used in a combination. Return nonzero if
1534 not. This is used in try_combine to detect early some cases where we
1535 can't perform combinations. */
1538 cant_combine_insn_p (rtx insn)
1543 /* If this isn't really an insn, we can't do anything.
1544 This can occur when flow deletes an insn that it has merged into an
1545 auto-increment address. */
1546 if (! INSN_P (insn))
1549 /* Never combine loads and stores involving hard regs that are likely
1550 to be spilled. The register allocator can usually handle such
1551 reg-reg moves by tying. If we allow the combiner to make
1552 substitutions of likely-spilled regs, reload might die.
1553 As an exception, we allow combinations involving fixed regs; these are
1554 not available to the register allocator so there's no risk involved. */
1556 set = single_set (insn);
1559 src = SET_SRC (set);
1560 dest = SET_DEST (set);
1561 if (GET_CODE (src) == SUBREG)
1562 src = SUBREG_REG (src);
1563 if (GET_CODE (dest) == SUBREG)
1564 dest = SUBREG_REG (dest);
1565 if (REG_P (src) && REG_P (dest)
1566 && ((REGNO (src) < FIRST_PSEUDO_REGISTER
1567 && ! fixed_regs[REGNO (src)]
1568 && CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (REGNO (src))))
1569 || (REGNO (dest) < FIRST_PSEUDO_REGISTER
1570 && ! fixed_regs[REGNO (dest)]
1571 && CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (REGNO (dest))))))
1577 struct likely_spilled_retval_info
1579 unsigned regno, nregs;
1583 /* Called via note_stores by likely_spilled_retval_p. Remove from info->mask
1584 hard registers that are known to be written to / clobbered in full. */
1586 likely_spilled_retval_1 (rtx x, rtx set, void *data)
1588 struct likely_spilled_retval_info *info = data;
1589 unsigned regno, nregs;
1592 if (!REG_P (XEXP (set, 0)))
1595 if (regno >= info->regno + info->nregs)
1597 nregs = hard_regno_nregs[regno][GET_MODE (x)];
1598 if (regno + nregs <= info->regno)
1600 new_mask = (2U << (nregs - 1)) - 1;
1601 if (regno < info->regno)
1602 new_mask >>= info->regno - regno;
1604 new_mask <<= regno - info->regno;
1605 info->mask &= new_mask;
1608 /* Return nonzero iff part of the return value is live during INSN, and
1609 it is likely spilled. This can happen when more than one insn is needed
1610 to copy the return value, e.g. when we consider to combine into the
1611 second copy insn for a complex value. */
1614 likely_spilled_retval_p (rtx insn)
1616 rtx use = BB_END (this_basic_block);
1618 unsigned regno, nregs;
1619 /* We assume here that no machine mode needs more than
1620 32 hard registers when the value overlaps with a register
1621 for which FUNCTION_VALUE_REGNO_P is true. */
1623 struct likely_spilled_retval_info info;
1625 if (!NONJUMP_INSN_P (use) || GET_CODE (PATTERN (use)) != USE || insn == use)
1627 reg = XEXP (PATTERN (use), 0);
1628 if (!REG_P (reg) || !FUNCTION_VALUE_REGNO_P (REGNO (reg)))
1630 regno = REGNO (reg);
1631 nregs = hard_regno_nregs[regno][GET_MODE (reg)];
1634 mask = (2U << (nregs - 1)) - 1;
1636 /* Disregard parts of the return value that are set later. */
1640 for (p = PREV_INSN (use); info.mask && p != insn; p = PREV_INSN (p))
1641 note_stores (PATTERN (insn), likely_spilled_retval_1, &info);
1644 /* Check if any of the (probably) live return value registers is
1649 if ((mask & 1 << nregs)
1650 && CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (regno + nregs)))
1656 /* Adjust INSN after we made a change to its destination.
1658 Changing the destination can invalidate notes that say something about
1659 the results of the insn and a LOG_LINK pointing to the insn. */
1662 adjust_for_new_dest (rtx insn)
1666 /* For notes, be conservative and simply remove them. */
1667 loc = ®_NOTES (insn);
1670 enum reg_note kind = REG_NOTE_KIND (*loc);
1671 if (kind == REG_EQUAL || kind == REG_EQUIV)
1672 *loc = XEXP (*loc, 1);
1674 loc = &XEXP (*loc, 1);
1677 /* The new insn will have a destination that was previously the destination
1678 of an insn just above it. Call distribute_links to make a LOG_LINK from
1679 the next use of that destination. */
1680 distribute_links (gen_rtx_INSN_LIST (VOIDmode, insn, NULL_RTX));
1683 /* Return TRUE if combine can reuse reg X in mode MODE.
1684 ADDED_SETS is nonzero if the original set is still required. */
1686 can_change_dest_mode (rtx x, int added_sets, enum machine_mode mode)
1694 /* Allow hard registers if the new mode is legal, and occupies no more
1695 registers than the old mode. */
1696 if (regno < FIRST_PSEUDO_REGISTER)
1697 return (HARD_REGNO_MODE_OK (regno, mode)
1698 && (hard_regno_nregs[regno][GET_MODE (x)]
1699 >= hard_regno_nregs[regno][mode]));
1701 /* Or a pseudo that is only used once. */
1702 return (REG_N_SETS (regno) == 1 && !added_sets
1703 && !REG_USERVAR_P (x));
1706 /* Try to combine the insns I1 and I2 into I3.
1707 Here I1 and I2 appear earlier than I3.
1708 I1 can be zero; then we combine just I2 into I3.
1710 If we are combining three insns and the resulting insn is not recognized,
1711 try splitting it into two insns. If that happens, I2 and I3 are retained
1712 and I1 is pseudo-deleted by turning it into a NOTE. Otherwise, I1 and I2
1715 Return 0 if the combination does not work. Then nothing is changed.
1716 If we did the combination, return the insn at which combine should
1719 Set NEW_DIRECT_JUMP_P to a nonzero value if try_combine creates a
1720 new direct jump instruction. */
1723 try_combine (rtx i3, rtx i2, rtx i1, int *new_direct_jump_p)
1725 /* New patterns for I3 and I2, respectively. */
1726 rtx newpat, newi2pat = 0;
1727 rtvec newpat_vec_with_clobbers = 0;
1728 int substed_i2 = 0, substed_i1 = 0;
1729 /* Indicates need to preserve SET in I1 or I2 in I3 if it is not dead. */
1730 int added_sets_1, added_sets_2;
1731 /* Total number of SETs to put into I3. */
1733 /* Nonzero if I2's body now appears in I3. */
1735 /* INSN_CODEs for new I3, new I2, and user of condition code. */
1736 int insn_code_number, i2_code_number = 0, other_code_number = 0;
1737 /* Contains I3 if the destination of I3 is used in its source, which means
1738 that the old life of I3 is being killed. If that usage is placed into
1739 I2 and not in I3, a REG_DEAD note must be made. */
1740 rtx i3dest_killed = 0;
1741 /* SET_DEST and SET_SRC of I2 and I1. */
1742 rtx i2dest, i2src, i1dest = 0, i1src = 0;
1743 /* PATTERN (I2), or a copy of it in certain cases. */
1745 /* Indicates if I2DEST or I1DEST is in I2SRC or I1_SRC. */
1746 int i2dest_in_i2src = 0, i1dest_in_i1src = 0, i2dest_in_i1src = 0;
1747 int i2dest_killed = 0, i1dest_killed = 0;
1748 int i1_feeds_i3 = 0;
1749 /* Notes that must be added to REG_NOTES in I3 and I2. */
1750 rtx new_i3_notes, new_i2_notes;
1751 /* Notes that we substituted I3 into I2 instead of the normal case. */
1752 int i3_subst_into_i2 = 0;
1753 /* Notes that I1, I2 or I3 is a MULT operation. */
1762 /* Exit early if one of the insns involved can't be used for
1764 if (cant_combine_insn_p (i3)
1765 || cant_combine_insn_p (i2)
1766 || (i1 && cant_combine_insn_p (i1))
1767 || likely_spilled_retval_p (i3)
1768 /* We also can't do anything if I3 has a
1769 REG_LIBCALL note since we don't want to disrupt the contiguity of a
1772 /* ??? This gives worse code, and appears to be unnecessary, since no
1773 pass after flow uses REG_LIBCALL/REG_RETVAL notes. */
1774 || find_reg_note (i3, REG_LIBCALL, NULL_RTX)
1780 undobuf.other_insn = 0;
1782 /* Reset the hard register usage information. */
1783 CLEAR_HARD_REG_SET (newpat_used_regs);
1785 /* If I1 and I2 both feed I3, they can be in any order. To simplify the
1786 code below, set I1 to be the earlier of the two insns. */
1787 if (i1 && INSN_CUID (i1) > INSN_CUID (i2))
1788 temp = i1, i1 = i2, i2 = temp;
1790 added_links_insn = 0;
1792 /* First check for one important special-case that the code below will
1793 not handle. Namely, the case where I1 is zero, I2 is a PARALLEL
1794 and I3 is a SET whose SET_SRC is a SET_DEST in I2. In that case,
1795 we may be able to replace that destination with the destination of I3.
1796 This occurs in the common code where we compute both a quotient and
1797 remainder into a structure, in which case we want to do the computation
1798 directly into the structure to avoid register-register copies.
1800 Note that this case handles both multiple sets in I2 and also
1801 cases where I2 has a number of CLOBBER or PARALLELs.
1803 We make very conservative checks below and only try to handle the
1804 most common cases of this. For example, we only handle the case
1805 where I2 and I3 are adjacent to avoid making difficult register
1808 if (i1 == 0 && NONJUMP_INSN_P (i3) && GET_CODE (PATTERN (i3)) == SET
1809 && REG_P (SET_SRC (PATTERN (i3)))
1810 && REGNO (SET_SRC (PATTERN (i3))) >= FIRST_PSEUDO_REGISTER
1811 && find_reg_note (i3, REG_DEAD, SET_SRC (PATTERN (i3)))
1812 && GET_CODE (PATTERN (i2)) == PARALLEL
1813 && ! side_effects_p (SET_DEST (PATTERN (i3)))
1814 /* If the dest of I3 is a ZERO_EXTRACT or STRICT_LOW_PART, the code
1815 below would need to check what is inside (and reg_overlap_mentioned_p
1816 doesn't support those codes anyway). Don't allow those destinations;
1817 the resulting insn isn't likely to be recognized anyway. */
1818 && GET_CODE (SET_DEST (PATTERN (i3))) != ZERO_EXTRACT
1819 && GET_CODE (SET_DEST (PATTERN (i3))) != STRICT_LOW_PART
1820 && ! reg_overlap_mentioned_p (SET_SRC (PATTERN (i3)),
1821 SET_DEST (PATTERN (i3)))
1822 && next_real_insn (i2) == i3)
1824 rtx p2 = PATTERN (i2);
1826 /* Make sure that the destination of I3,
1827 which we are going to substitute into one output of I2,
1828 is not used within another output of I2. We must avoid making this:
1829 (parallel [(set (mem (reg 69)) ...)
1830 (set (reg 69) ...)])
1831 which is not well-defined as to order of actions.
1832 (Besides, reload can't handle output reloads for this.)
1834 The problem can also happen if the dest of I3 is a memory ref,
1835 if another dest in I2 is an indirect memory ref. */
1836 for (i = 0; i < XVECLEN (p2, 0); i++)
1837 if ((GET_CODE (XVECEXP (p2, 0, i)) == SET
1838 || GET_CODE (XVECEXP (p2, 0, i)) == CLOBBER)
1839 && reg_overlap_mentioned_p (SET_DEST (PATTERN (i3)),
1840 SET_DEST (XVECEXP (p2, 0, i))))
1843 if (i == XVECLEN (p2, 0))
1844 for (i = 0; i < XVECLEN (p2, 0); i++)
1845 if ((GET_CODE (XVECEXP (p2, 0, i)) == SET
1846 || GET_CODE (XVECEXP (p2, 0, i)) == CLOBBER)
1847 && SET_DEST (XVECEXP (p2, 0, i)) == SET_SRC (PATTERN (i3)))
1852 subst_low_cuid = INSN_CUID (i2);
1854 added_sets_2 = added_sets_1 = 0;
1855 i2dest = SET_SRC (PATTERN (i3));
1856 i2dest_killed = dead_or_set_p (i2, i2dest);
1858 /* Replace the dest in I2 with our dest and make the resulting
1859 insn the new pattern for I3. Then skip to where we
1860 validate the pattern. Everything was set up above. */
1861 SUBST (SET_DEST (XVECEXP (p2, 0, i)),
1862 SET_DEST (PATTERN (i3)));
1865 i3_subst_into_i2 = 1;
1866 goto validate_replacement;
1870 /* If I2 is setting a double-word pseudo to a constant and I3 is setting
1871 one of those words to another constant, merge them by making a new
1874 && (temp = single_set (i2)) != 0
1875 && (GET_CODE (SET_SRC (temp)) == CONST_INT
1876 || GET_CODE (SET_SRC (temp)) == CONST_DOUBLE)
1877 && REG_P (SET_DEST (temp))
1878 && GET_MODE_CLASS (GET_MODE (SET_DEST (temp))) == MODE_INT
1879 && GET_MODE_SIZE (GET_MODE (SET_DEST (temp))) == 2 * UNITS_PER_WORD
1880 && GET_CODE (PATTERN (i3)) == SET
1881 && GET_CODE (SET_DEST (PATTERN (i3))) == SUBREG
1882 && SUBREG_REG (SET_DEST (PATTERN (i3))) == SET_DEST (temp)
1883 && GET_MODE_CLASS (GET_MODE (SET_DEST (PATTERN (i3)))) == MODE_INT
1884 && GET_MODE_SIZE (GET_MODE (SET_DEST (PATTERN (i3)))) == UNITS_PER_WORD
1885 && GET_CODE (SET_SRC (PATTERN (i3))) == CONST_INT)
1887 HOST_WIDE_INT lo, hi;
1889 if (GET_CODE (SET_SRC (temp)) == CONST_INT)
1890 lo = INTVAL (SET_SRC (temp)), hi = lo < 0 ? -1 : 0;
1893 lo = CONST_DOUBLE_LOW (SET_SRC (temp));
1894 hi = CONST_DOUBLE_HIGH (SET_SRC (temp));
1897 if (subreg_lowpart_p (SET_DEST (PATTERN (i3))))
1899 /* We don't handle the case of the target word being wider
1900 than a host wide int. */
1901 gcc_assert (HOST_BITS_PER_WIDE_INT >= BITS_PER_WORD);
1903 lo &= ~(UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD (1) - 1);
1904 lo |= (INTVAL (SET_SRC (PATTERN (i3)))
1905 & (UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD (1) - 1));
1907 else if (HOST_BITS_PER_WIDE_INT == BITS_PER_WORD)
1908 hi = INTVAL (SET_SRC (PATTERN (i3)));
1909 else if (HOST_BITS_PER_WIDE_INT >= 2 * BITS_PER_WORD)
1911 int sign = -(int) ((unsigned HOST_WIDE_INT) lo
1912 >> (HOST_BITS_PER_WIDE_INT - 1));
1914 lo &= ~ (UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD
1915 (UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD (1) - 1));
1916 lo |= (UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD
1917 (INTVAL (SET_SRC (PATTERN (i3)))));
1919 hi = lo < 0 ? -1 : 0;
1922 /* We don't handle the case of the higher word not fitting
1923 entirely in either hi or lo. */
1928 subst_low_cuid = INSN_CUID (i2);
1929 added_sets_2 = added_sets_1 = 0;
1930 i2dest = SET_DEST (temp);
1931 i2dest_killed = dead_or_set_p (i2, i2dest);
1933 SUBST (SET_SRC (temp),
1934 immed_double_const (lo, hi, GET_MODE (SET_DEST (temp))));
1936 newpat = PATTERN (i2);
1937 goto validate_replacement;
1941 /* If we have no I1 and I2 looks like:
1942 (parallel [(set (reg:CC X) (compare:CC OP (const_int 0)))
1944 make up a dummy I1 that is
1947 (set (reg:CC X) (compare:CC Y (const_int 0)))
1949 (We can ignore any trailing CLOBBERs.)
1951 This undoes a previous combination and allows us to match a branch-and-
1954 if (i1 == 0 && GET_CODE (PATTERN (i2)) == PARALLEL
1955 && XVECLEN (PATTERN (i2), 0) >= 2
1956 && GET_CODE (XVECEXP (PATTERN (i2), 0, 0)) == SET
1957 && (GET_MODE_CLASS (GET_MODE (SET_DEST (XVECEXP (PATTERN (i2), 0, 0))))
1959 && GET_CODE (SET_SRC (XVECEXP (PATTERN (i2), 0, 0))) == COMPARE
1960 && XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 1) == const0_rtx
1961 && GET_CODE (XVECEXP (PATTERN (i2), 0, 1)) == SET
1962 && REG_P (SET_DEST (XVECEXP (PATTERN (i2), 0, 1)))
1963 && rtx_equal_p (XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 0),
1964 SET_SRC (XVECEXP (PATTERN (i2), 0, 1))))
1966 for (i = XVECLEN (PATTERN (i2), 0) - 1; i >= 2; i--)
1967 if (GET_CODE (XVECEXP (PATTERN (i2), 0, i)) != CLOBBER)
1972 /* We make I1 with the same INSN_UID as I2. This gives it
1973 the same INSN_CUID for value tracking. Our fake I1 will
1974 never appear in the insn stream so giving it the same INSN_UID
1975 as I2 will not cause a problem. */
1977 i1 = gen_rtx_INSN (VOIDmode, INSN_UID (i2), NULL_RTX, i2,
1978 BLOCK_FOR_INSN (i2), INSN_LOCATOR (i2),
1979 XVECEXP (PATTERN (i2), 0, 1), -1, NULL_RTX,
1982 SUBST (PATTERN (i2), XVECEXP (PATTERN (i2), 0, 0));
1983 SUBST (XEXP (SET_SRC (PATTERN (i2)), 0),
1984 SET_DEST (PATTERN (i1)));
1989 /* Verify that I2 and I1 are valid for combining. */
1990 if (! can_combine_p (i2, i3, i1, NULL_RTX, &i2dest, &i2src)
1991 || (i1 && ! can_combine_p (i1, i3, NULL_RTX, i2, &i1dest, &i1src)))
1997 /* Record whether I2DEST is used in I2SRC and similarly for the other
1998 cases. Knowing this will help in register status updating below. */
1999 i2dest_in_i2src = reg_overlap_mentioned_p (i2dest, i2src);
2000 i1dest_in_i1src = i1 && reg_overlap_mentioned_p (i1dest, i1src);
2001 i2dest_in_i1src = i1 && reg_overlap_mentioned_p (i2dest, i1src);
2002 i2dest_killed = dead_or_set_p (i2, i2dest);
2003 i1dest_killed = i1 && dead_or_set_p (i1, i1dest);
2005 /* See if I1 directly feeds into I3. It does if I1DEST is not used
2007 i1_feeds_i3 = i1 && ! reg_overlap_mentioned_p (i1dest, i2src);
2009 /* Ensure that I3's pattern can be the destination of combines. */
2010 if (! combinable_i3pat (i3, &PATTERN (i3), i2dest, i1dest,
2011 i1 && i2dest_in_i1src && i1_feeds_i3,
2018 /* See if any of the insns is a MULT operation. Unless one is, we will
2019 reject a combination that is, since it must be slower. Be conservative
2021 if (GET_CODE (i2src) == MULT
2022 || (i1 != 0 && GET_CODE (i1src) == MULT)
2023 || (GET_CODE (PATTERN (i3)) == SET
2024 && GET_CODE (SET_SRC (PATTERN (i3))) == MULT))
2027 /* If I3 has an inc, then give up if I1 or I2 uses the reg that is inc'd.
2028 We used to do this EXCEPT in one case: I3 has a post-inc in an
2029 output operand. However, that exception can give rise to insns like
2031 which is a famous insn on the PDP-11 where the value of r3 used as the
2032 source was model-dependent. Avoid this sort of thing. */
2035 if (!(GET_CODE (PATTERN (i3)) == SET
2036 && REG_P (SET_SRC (PATTERN (i3)))
2037 && MEM_P (SET_DEST (PATTERN (i3)))
2038 && (GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_INC
2039 || GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_DEC)))
2040 /* It's not the exception. */
2043 for (link = REG_NOTES (i3); link; link = XEXP (link, 1))
2044 if (REG_NOTE_KIND (link) == REG_INC
2045 && (reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i2))
2047 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i1)))))
2054 /* See if the SETs in I1 or I2 need to be kept around in the merged
2055 instruction: whenever the value set there is still needed past I3.
2056 For the SETs in I2, this is easy: we see if I2DEST dies or is set in I3.
2058 For the SET in I1, we have two cases: If I1 and I2 independently
2059 feed into I3, the set in I1 needs to be kept around if I1DEST dies
2060 or is set in I3. Otherwise (if I1 feeds I2 which feeds I3), the set
2061 in I1 needs to be kept around unless I1DEST dies or is set in either
2062 I2 or I3. We can distinguish these cases by seeing if I2SRC mentions
2063 I1DEST. If so, we know I1 feeds into I2. */
2065 added_sets_2 = ! dead_or_set_p (i3, i2dest);
2068 = i1 && ! (i1_feeds_i3 ? dead_or_set_p (i3, i1dest)
2069 : (dead_or_set_p (i3, i1dest) || dead_or_set_p (i2, i1dest)));
2071 /* If the set in I2 needs to be kept around, we must make a copy of
2072 PATTERN (I2), so that when we substitute I1SRC for I1DEST in
2073 PATTERN (I2), we are only substituting for the original I1DEST, not into
2074 an already-substituted copy. This also prevents making self-referential
2075 rtx. If I2 is a PARALLEL, we just need the piece that assigns I2SRC to
2078 i2pat = (GET_CODE (PATTERN (i2)) == PARALLEL
2079 ? gen_rtx_SET (VOIDmode, i2dest, i2src)
2083 i2pat = copy_rtx (i2pat);
2087 /* Substitute in the latest insn for the regs set by the earlier ones. */
2089 maxreg = max_reg_num ();
2094 /* Many machines that don't use CC0 have insns that can both perform an
2095 arithmetic operation and set the condition code. These operations will
2096 be represented as a PARALLEL with the first element of the vector
2097 being a COMPARE of an arithmetic operation with the constant zero.
2098 The second element of the vector will set some pseudo to the result
2099 of the same arithmetic operation. If we simplify the COMPARE, we won't
2100 match such a pattern and so will generate an extra insn. Here we test
2101 for this case, where both the comparison and the operation result are
2102 needed, and make the PARALLEL by just replacing I2DEST in I3SRC with
2103 I2SRC. Later we will make the PARALLEL that contains I2. */
2105 if (i1 == 0 && added_sets_2 && GET_CODE (PATTERN (i3)) == SET
2106 && GET_CODE (SET_SRC (PATTERN (i3))) == COMPARE
2107 && XEXP (SET_SRC (PATTERN (i3)), 1) == const0_rtx
2108 && rtx_equal_p (XEXP (SET_SRC (PATTERN (i3)), 0), i2dest))
2110 #ifdef SELECT_CC_MODE
2112 enum machine_mode compare_mode;
2115 newpat = PATTERN (i3);
2116 SUBST (XEXP (SET_SRC (newpat), 0), i2src);
2120 #ifdef SELECT_CC_MODE
2121 /* See if a COMPARE with the operand we substituted in should be done
2122 with the mode that is currently being used. If not, do the same
2123 processing we do in `subst' for a SET; namely, if the destination
2124 is used only once, try to replace it with a register of the proper
2125 mode and also replace the COMPARE. */
2126 if (undobuf.other_insn == 0
2127 && (cc_use = find_single_use (SET_DEST (newpat), i3,
2128 &undobuf.other_insn))
2129 && ((compare_mode = SELECT_CC_MODE (GET_CODE (*cc_use),
2131 != GET_MODE (SET_DEST (newpat))))
2133 if (can_change_dest_mode(SET_DEST (newpat), added_sets_2,
2136 unsigned int regno = REGNO (SET_DEST (newpat));
2137 rtx new_dest = gen_rtx_REG (compare_mode, regno);
2139 if (regno >= FIRST_PSEUDO_REGISTER)
2140 SUBST (regno_reg_rtx[regno], new_dest);
2142 SUBST (SET_DEST (newpat), new_dest);
2143 SUBST (XEXP (*cc_use, 0), new_dest);
2144 SUBST (SET_SRC (newpat),
2145 gen_rtx_COMPARE (compare_mode, i2src, const0_rtx));
2148 undobuf.other_insn = 0;
2155 /* It is possible that the source of I2 or I1 may be performing
2156 an unneeded operation, such as a ZERO_EXTEND of something
2157 that is known to have the high part zero. Handle that case
2158 by letting subst look at the innermost one of them.
2160 Another way to do this would be to have a function that tries
2161 to simplify a single insn instead of merging two or more
2162 insns. We don't do this because of the potential of infinite
2163 loops and because of the potential extra memory required.
2164 However, doing it the way we are is a bit of a kludge and
2165 doesn't catch all cases.
2167 But only do this if -fexpensive-optimizations since it slows
2168 things down and doesn't usually win.
2170 This is not done in the COMPARE case above because the
2171 unmodified I2PAT is used in the PARALLEL and so a pattern
2172 with a modified I2SRC would not match. */
2174 if (flag_expensive_optimizations)
2176 /* Pass pc_rtx so no substitutions are done, just
2180 subst_low_cuid = INSN_CUID (i1);
2181 i1src = subst (i1src, pc_rtx, pc_rtx, 0, 0);
2185 subst_low_cuid = INSN_CUID (i2);
2186 i2src = subst (i2src, pc_rtx, pc_rtx, 0, 0);
2190 n_occurrences = 0; /* `subst' counts here */
2192 /* If I1 feeds into I2 (not into I3) and I1DEST is in I1SRC, we
2193 need to make a unique copy of I2SRC each time we substitute it
2194 to avoid self-referential rtl. */
2196 subst_low_cuid = INSN_CUID (i2);
2197 newpat = subst (PATTERN (i3), i2dest, i2src, 0,
2198 ! i1_feeds_i3 && i1dest_in_i1src);
2201 /* Record whether i2's body now appears within i3's body. */
2202 i2_is_used = n_occurrences;
2205 /* If we already got a failure, don't try to do more. Otherwise,
2206 try to substitute in I1 if we have it. */
2208 if (i1 && GET_CODE (newpat) != CLOBBER)
2210 /* Before we can do this substitution, we must redo the test done
2211 above (see detailed comments there) that ensures that I1DEST
2212 isn't mentioned in any SETs in NEWPAT that are field assignments. */
2214 if (! combinable_i3pat (NULL_RTX, &newpat, i1dest, NULL_RTX,
2222 subst_low_cuid = INSN_CUID (i1);
2223 newpat = subst (newpat, i1dest, i1src, 0, 0);
2227 /* Fail if an autoincrement side-effect has been duplicated. Be careful
2228 to count all the ways that I2SRC and I1SRC can be used. */
2229 if ((FIND_REG_INC_NOTE (i2, NULL_RTX) != 0
2230 && i2_is_used + added_sets_2 > 1)
2231 || (i1 != 0 && FIND_REG_INC_NOTE (i1, NULL_RTX) != 0
2232 && (n_occurrences + added_sets_1 + (added_sets_2 && ! i1_feeds_i3)
2234 /* Fail if we tried to make a new register. */
2235 || max_reg_num () != maxreg
2236 /* Fail if we couldn't do something and have a CLOBBER. */
2237 || GET_CODE (newpat) == CLOBBER
2238 /* Fail if this new pattern is a MULT and we didn't have one before
2239 at the outer level. */
2240 || (GET_CODE (newpat) == SET && GET_CODE (SET_SRC (newpat)) == MULT
2247 /* If the actions of the earlier insns must be kept
2248 in addition to substituting them into the latest one,
2249 we must make a new PARALLEL for the latest insn
2250 to hold additional the SETs. */
2252 if (added_sets_1 || added_sets_2)
2256 if (GET_CODE (newpat) == PARALLEL)
2258 rtvec old = XVEC (newpat, 0);
2259 total_sets = XVECLEN (newpat, 0) + added_sets_1 + added_sets_2;
2260 newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (total_sets));
2261 memcpy (XVEC (newpat, 0)->elem, &old->elem[0],
2262 sizeof (old->elem[0]) * old->num_elem);
2267 total_sets = 1 + added_sets_1 + added_sets_2;
2268 newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (total_sets));
2269 XVECEXP (newpat, 0, 0) = old;
2273 XVECEXP (newpat, 0, --total_sets)
2274 = (GET_CODE (PATTERN (i1)) == PARALLEL
2275 ? gen_rtx_SET (VOIDmode, i1dest, i1src) : PATTERN (i1));
2279 /* If there is no I1, use I2's body as is. We used to also not do
2280 the subst call below if I2 was substituted into I3,
2281 but that could lose a simplification. */
2283 XVECEXP (newpat, 0, --total_sets) = i2pat;
2285 /* See comment where i2pat is assigned. */
2286 XVECEXP (newpat, 0, --total_sets)
2287 = subst (i2pat, i1dest, i1src, 0, 0);
2291 /* We come here when we are replacing a destination in I2 with the
2292 destination of I3. */
2293 validate_replacement:
2295 /* Note which hard regs this insn has as inputs. */
2296 mark_used_regs_combine (newpat);
2298 /* If recog_for_combine fails, it strips existing clobbers. If we'll
2299 consider splitting this pattern, we might need these clobbers. */
2300 if (i1 && GET_CODE (newpat) == PARALLEL
2301 && GET_CODE (XVECEXP (newpat, 0, XVECLEN (newpat, 0) - 1)) == CLOBBER)
2303 int len = XVECLEN (newpat, 0);
2305 newpat_vec_with_clobbers = rtvec_alloc (len);
2306 for (i = 0; i < len; i++)
2307 RTVEC_ELT (newpat_vec_with_clobbers, i) = XVECEXP (newpat, 0, i);
2310 /* Is the result of combination a valid instruction? */
2311 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2313 /* If the result isn't valid, see if it is a PARALLEL of two SETs where
2314 the second SET's destination is a register that is unused and isn't
2315 marked as an instruction that might trap in an EH region. In that case,
2316 we just need the first SET. This can occur when simplifying a divmod
2317 insn. We *must* test for this case here because the code below that
2318 splits two independent SETs doesn't handle this case correctly when it
2319 updates the register status.
2321 It's pointless doing this if we originally had two sets, one from
2322 i3, and one from i2. Combining then splitting the parallel results
2323 in the original i2 again plus an invalid insn (which we delete).
2324 The net effect is only to move instructions around, which makes
2325 debug info less accurate.
2327 Also check the case where the first SET's destination is unused.
2328 That would not cause incorrect code, but does cause an unneeded
2331 if (insn_code_number < 0
2332 && !(added_sets_2 && i1 == 0)
2333 && GET_CODE (newpat) == PARALLEL
2334 && XVECLEN (newpat, 0) == 2
2335 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
2336 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
2337 && asm_noperands (newpat) < 0)
2339 rtx set0 = XVECEXP (newpat, 0, 0);
2340 rtx set1 = XVECEXP (newpat, 0, 1);
2343 if (((REG_P (SET_DEST (set1))
2344 && find_reg_note (i3, REG_UNUSED, SET_DEST (set1)))
2345 || (GET_CODE (SET_DEST (set1)) == SUBREG
2346 && find_reg_note (i3, REG_UNUSED, SUBREG_REG (SET_DEST (set1)))))
2347 && (!(note = find_reg_note (i3, REG_EH_REGION, NULL_RTX))
2348 || INTVAL (XEXP (note, 0)) <= 0)
2349 && ! side_effects_p (SET_SRC (set1)))
2352 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2355 else if (((REG_P (SET_DEST (set0))
2356 && find_reg_note (i3, REG_UNUSED, SET_DEST (set0)))
2357 || (GET_CODE (SET_DEST (set0)) == SUBREG
2358 && find_reg_note (i3, REG_UNUSED,
2359 SUBREG_REG (SET_DEST (set0)))))
2360 && (!(note = find_reg_note (i3, REG_EH_REGION, NULL_RTX))
2361 || INTVAL (XEXP (note, 0)) <= 0)
2362 && ! side_effects_p (SET_SRC (set0)))
2365 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2367 if (insn_code_number >= 0)
2369 /* If we will be able to accept this, we have made a
2370 change to the destination of I3. This requires us to
2371 do a few adjustments. */
2373 PATTERN (i3) = newpat;
2374 adjust_for_new_dest (i3);
2379 /* If we were combining three insns and the result is a simple SET
2380 with no ASM_OPERANDS that wasn't recognized, try to split it into two
2381 insns. There are two ways to do this. It can be split using a
2382 machine-specific method (like when you have an addition of a large
2383 constant) or by combine in the function find_split_point. */
2385 if (i1 && insn_code_number < 0 && GET_CODE (newpat) == SET
2386 && asm_noperands (newpat) < 0)
2388 rtx m_split, *split;
2389 rtx ni2dest = i2dest;
2391 /* See if the MD file can split NEWPAT. If it can't, see if letting it
2392 use I2DEST as a scratch register will help. In the latter case,
2393 convert I2DEST to the mode of the source of NEWPAT if we can. */
2395 m_split = split_insns (newpat, i3);
2397 /* We can only use I2DEST as a scratch reg if it doesn't overlap any
2398 inputs of NEWPAT. */
2400 /* ??? If I2DEST is not safe, and I1DEST exists, then it would be
2401 possible to try that as a scratch reg. This would require adding
2402 more code to make it work though. */
2404 if (m_split == 0 && ! reg_overlap_mentioned_p (ni2dest, newpat))
2406 enum machine_mode new_mode = GET_MODE (SET_DEST (newpat));
2407 /* If I2DEST is a hard register or the only use of a pseudo,
2408 we can change its mode. */
2409 if (new_mode != GET_MODE (i2dest)
2410 && new_mode != VOIDmode
2411 && can_change_dest_mode (i2dest, added_sets_2, new_mode))
2412 ni2dest = gen_rtx_REG (GET_MODE (SET_DEST (newpat)),
2415 m_split = split_insns (gen_rtx_PARALLEL
2417 gen_rtvec (2, newpat,
2418 gen_rtx_CLOBBER (VOIDmode,
2421 /* If the split with the mode-changed register didn't work, try
2422 the original register. */
2423 if (! m_split && ni2dest != i2dest)
2426 m_split = split_insns (gen_rtx_PARALLEL
2428 gen_rtvec (2, newpat,
2429 gen_rtx_CLOBBER (VOIDmode,
2435 /* If recog_for_combine has discarded clobbers, try to use them
2436 again for the split. */
2437 if (m_split == 0 && newpat_vec_with_clobbers)
2439 = split_insns (gen_rtx_PARALLEL (VOIDmode,
2440 newpat_vec_with_clobbers), i3);
2442 if (m_split && NEXT_INSN (m_split) == NULL_RTX)
2444 m_split = PATTERN (m_split);
2445 insn_code_number = recog_for_combine (&m_split, i3, &new_i3_notes);
2446 if (insn_code_number >= 0)
2449 else if (m_split && NEXT_INSN (NEXT_INSN (m_split)) == NULL_RTX
2450 && (next_real_insn (i2) == i3
2451 || ! use_crosses_set_p (PATTERN (m_split), INSN_CUID (i2))))
2454 rtx newi3pat = PATTERN (NEXT_INSN (m_split));
2455 newi2pat = PATTERN (m_split);
2457 i3set = single_set (NEXT_INSN (m_split));
2458 i2set = single_set (m_split);
2460 /* In case we changed the mode of I2DEST, replace it in the
2461 pseudo-register table here. We can't do it above in case this
2462 code doesn't get executed and we do a split the other way. */
2464 if (REGNO (i2dest) >= FIRST_PSEUDO_REGISTER)
2465 SUBST (regno_reg_rtx[REGNO (i2dest)], ni2dest);
2467 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
2469 /* If I2 or I3 has multiple SETs, we won't know how to track
2470 register status, so don't use these insns. If I2's destination
2471 is used between I2 and I3, we also can't use these insns. */
2473 if (i2_code_number >= 0 && i2set && i3set
2474 && (next_real_insn (i2) == i3
2475 || ! reg_used_between_p (SET_DEST (i2set), i2, i3)))
2476 insn_code_number = recog_for_combine (&newi3pat, i3,
2478 if (insn_code_number >= 0)
2481 /* It is possible that both insns now set the destination of I3.
2482 If so, we must show an extra use of it. */
2484 if (insn_code_number >= 0)
2486 rtx new_i3_dest = SET_DEST (i3set);
2487 rtx new_i2_dest = SET_DEST (i2set);
2489 while (GET_CODE (new_i3_dest) == ZERO_EXTRACT
2490 || GET_CODE (new_i3_dest) == STRICT_LOW_PART
2491 || GET_CODE (new_i3_dest) == SUBREG)
2492 new_i3_dest = XEXP (new_i3_dest, 0);
2494 while (GET_CODE (new_i2_dest) == ZERO_EXTRACT
2495 || GET_CODE (new_i2_dest) == STRICT_LOW_PART
2496 || GET_CODE (new_i2_dest) == SUBREG)
2497 new_i2_dest = XEXP (new_i2_dest, 0);
2499 if (REG_P (new_i3_dest)
2500 && REG_P (new_i2_dest)
2501 && REGNO (new_i3_dest) == REGNO (new_i2_dest))
2502 REG_N_SETS (REGNO (new_i2_dest))++;
2506 /* If we can split it and use I2DEST, go ahead and see if that
2507 helps things be recognized. Verify that none of the registers
2508 are set between I2 and I3. */
2509 if (insn_code_number < 0 && (split = find_split_point (&newpat, i3)) != 0
2513 /* We need I2DEST in the proper mode. If it is a hard register
2514 or the only use of a pseudo, we can change its mode.
2515 Make sure we don't change a hard register to have a mode that
2516 isn't valid for it, or change the number of registers. */
2517 && (GET_MODE (*split) == GET_MODE (i2dest)
2518 || GET_MODE (*split) == VOIDmode
2519 || can_change_dest_mode (i2dest, added_sets_2,
2521 && (next_real_insn (i2) == i3
2522 || ! use_crosses_set_p (*split, INSN_CUID (i2)))
2523 /* We can't overwrite I2DEST if its value is still used by
2525 && ! reg_referenced_p (i2dest, newpat))
2527 rtx newdest = i2dest;
2528 enum rtx_code split_code = GET_CODE (*split);
2529 enum machine_mode split_mode = GET_MODE (*split);
2530 bool subst_done = false;
2531 newi2pat = NULL_RTX;
2533 /* Get NEWDEST as a register in the proper mode. We have already
2534 validated that we can do this. */
2535 if (GET_MODE (i2dest) != split_mode && split_mode != VOIDmode)
2537 newdest = gen_rtx_REG (split_mode, REGNO (i2dest));
2539 if (REGNO (i2dest) >= FIRST_PSEUDO_REGISTER)
2540 SUBST (regno_reg_rtx[REGNO (i2dest)], newdest);
2543 /* If *SPLIT is a (mult FOO (const_int pow2)), convert it to
2544 an ASHIFT. This can occur if it was inside a PLUS and hence
2545 appeared to be a memory address. This is a kludge. */
2546 if (split_code == MULT
2547 && GET_CODE (XEXP (*split, 1)) == CONST_INT
2548 && INTVAL (XEXP (*split, 1)) > 0
2549 && (i = exact_log2 (INTVAL (XEXP (*split, 1)))) >= 0)
2551 SUBST (*split, gen_rtx_ASHIFT (split_mode,
2552 XEXP (*split, 0), GEN_INT (i)));
2553 /* Update split_code because we may not have a multiply
2555 split_code = GET_CODE (*split);
2558 #ifdef INSN_SCHEDULING
2559 /* If *SPLIT is a paradoxical SUBREG, when we split it, it should
2560 be written as a ZERO_EXTEND. */
2561 if (split_code == SUBREG && MEM_P (SUBREG_REG (*split)))
2563 #ifdef LOAD_EXTEND_OP
2564 /* Or as a SIGN_EXTEND if LOAD_EXTEND_OP says that that's
2565 what it really is. */
2566 if (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (*split)))
2568 SUBST (*split, gen_rtx_SIGN_EXTEND (split_mode,
2569 SUBREG_REG (*split)));
2572 SUBST (*split, gen_rtx_ZERO_EXTEND (split_mode,
2573 SUBREG_REG (*split)));
2577 /* Attempt to split binary operators using arithmetic identities. */
2578 if (BINARY_P (SET_SRC (newpat))
2579 && split_mode == GET_MODE (SET_SRC (newpat))
2580 && ! side_effects_p (SET_SRC (newpat)))
2582 rtx setsrc = SET_SRC (newpat);
2583 enum machine_mode mode = GET_MODE (setsrc);
2584 enum rtx_code code = GET_CODE (setsrc);
2585 rtx src_op0 = XEXP (setsrc, 0);
2586 rtx src_op1 = XEXP (setsrc, 1);
2588 /* Split "X = Y op Y" as "Z = Y; X = Z op Z". */
2589 if (rtx_equal_p (src_op0, src_op1))
2591 newi2pat = gen_rtx_SET (VOIDmode, newdest, src_op0);
2592 SUBST (XEXP (setsrc, 0), newdest);
2593 SUBST (XEXP (setsrc, 1), newdest);
2596 /* Split "((P op Q) op R) op S" where op is PLUS or MULT. */
2597 else if ((code == PLUS || code == MULT)
2598 && GET_CODE (src_op0) == code
2599 && GET_CODE (XEXP (src_op0, 0)) == code
2600 && (INTEGRAL_MODE_P (mode)
2601 || (FLOAT_MODE_P (mode)
2602 && flag_unsafe_math_optimizations)))
2604 rtx p = XEXP (XEXP (src_op0, 0), 0);
2605 rtx q = XEXP (XEXP (src_op0, 0), 1);
2606 rtx r = XEXP (src_op0, 1);
2609 /* Split both "((X op Y) op X) op Y" and
2610 "((X op Y) op Y) op X" as "T op T" where T is
2612 if ((rtx_equal_p (p,r) && rtx_equal_p (q,s))
2613 || (rtx_equal_p (p,s) && rtx_equal_p (q,r)))
2615 newi2pat = gen_rtx_SET (VOIDmode, newdest,
2617 SUBST (XEXP (setsrc, 0), newdest);
2618 SUBST (XEXP (setsrc, 1), newdest);
2621 /* Split "((X op X) op Y) op Y)" as "T op T" where
2623 else if (rtx_equal_p (p,q) && rtx_equal_p (r,s))
2625 rtx tmp = simplify_gen_binary (code, mode, p, r);
2626 newi2pat = gen_rtx_SET (VOIDmode, newdest, tmp);
2627 SUBST (XEXP (setsrc, 0), newdest);
2628 SUBST (XEXP (setsrc, 1), newdest);
2636 newi2pat = gen_rtx_SET (VOIDmode, newdest, *split);
2637 SUBST (*split, newdest);
2640 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
2642 /* recog_for_combine might have added CLOBBERs to newi2pat.
2643 Make sure NEWPAT does not depend on the clobbered regs. */
2644 if (GET_CODE (newi2pat) == PARALLEL)
2645 for (i = XVECLEN (newi2pat, 0) - 1; i >= 0; i--)
2646 if (GET_CODE (XVECEXP (newi2pat, 0, i)) == CLOBBER)
2648 rtx reg = XEXP (XVECEXP (newi2pat, 0, i), 0);
2649 if (reg_overlap_mentioned_p (reg, newpat))
2656 /* If the split point was a MULT and we didn't have one before,
2657 don't use one now. */
2658 if (i2_code_number >= 0 && ! (split_code == MULT && ! have_mult))
2659 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2663 /* Check for a case where we loaded from memory in a narrow mode and
2664 then sign extended it, but we need both registers. In that case,
2665 we have a PARALLEL with both loads from the same memory location.
2666 We can split this into a load from memory followed by a register-register
2667 copy. This saves at least one insn, more if register allocation can
2670 We cannot do this if the destination of the first assignment is a
2671 condition code register or cc0. We eliminate this case by making sure
2672 the SET_DEST and SET_SRC have the same mode.
2674 We cannot do this if the destination of the second assignment is
2675 a register that we have already assumed is zero-extended. Similarly
2676 for a SUBREG of such a register. */
2678 else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0
2679 && GET_CODE (newpat) == PARALLEL
2680 && XVECLEN (newpat, 0) == 2
2681 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
2682 && GET_CODE (SET_SRC (XVECEXP (newpat, 0, 0))) == SIGN_EXTEND
2683 && (GET_MODE (SET_DEST (XVECEXP (newpat, 0, 0)))
2684 == GET_MODE (SET_SRC (XVECEXP (newpat, 0, 0))))
2685 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
2686 && rtx_equal_p (SET_SRC (XVECEXP (newpat, 0, 1)),
2687 XEXP (SET_SRC (XVECEXP (newpat, 0, 0)), 0))
2688 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)),
2690 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
2691 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
2692 && ! (temp = SET_DEST (XVECEXP (newpat, 0, 1)),
2694 && reg_stat[REGNO (temp)].nonzero_bits != 0
2695 && GET_MODE_BITSIZE (GET_MODE (temp)) < BITS_PER_WORD
2696 && GET_MODE_BITSIZE (GET_MODE (temp)) < HOST_BITS_PER_INT
2697 && (reg_stat[REGNO (temp)].nonzero_bits
2698 != GET_MODE_MASK (word_mode))))
2699 && ! (GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) == SUBREG
2700 && (temp = SUBREG_REG (SET_DEST (XVECEXP (newpat, 0, 1))),
2702 && reg_stat[REGNO (temp)].nonzero_bits != 0
2703 && GET_MODE_BITSIZE (GET_MODE (temp)) < BITS_PER_WORD
2704 && GET_MODE_BITSIZE (GET_MODE (temp)) < HOST_BITS_PER_INT
2705 && (reg_stat[REGNO (temp)].nonzero_bits
2706 != GET_MODE_MASK (word_mode)))))
2707 && ! reg_overlap_mentioned_p (SET_DEST (XVECEXP (newpat, 0, 1)),
2708 SET_SRC (XVECEXP (newpat, 0, 1)))
2709 && ! find_reg_note (i3, REG_UNUSED,
2710 SET_DEST (XVECEXP (newpat, 0, 0))))
2714 newi2pat = XVECEXP (newpat, 0, 0);
2715 ni2dest = SET_DEST (XVECEXP (newpat, 0, 0));
2716 newpat = XVECEXP (newpat, 0, 1);
2717 SUBST (SET_SRC (newpat),
2718 gen_lowpart (GET_MODE (SET_SRC (newpat)), ni2dest));
2719 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
2721 if (i2_code_number >= 0)
2722 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2724 if (insn_code_number >= 0)
2728 /* Similarly, check for a case where we have a PARALLEL of two independent
2729 SETs but we started with three insns. In this case, we can do the sets
2730 as two separate insns. This case occurs when some SET allows two
2731 other insns to combine, but the destination of that SET is still live. */
2733 else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0
2734 && GET_CODE (newpat) == PARALLEL
2735 && XVECLEN (newpat, 0) == 2
2736 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
2737 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != ZERO_EXTRACT
2738 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != STRICT_LOW_PART
2739 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
2740 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
2741 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
2742 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)),
2744 /* Don't pass sets with (USE (MEM ...)) dests to the following. */
2745 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != USE
2746 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != USE
2747 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 1)),
2748 XVECEXP (newpat, 0, 0))
2749 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 0)),
2750 XVECEXP (newpat, 0, 1))
2751 && ! (contains_muldiv (SET_SRC (XVECEXP (newpat, 0, 0)))
2752 && contains_muldiv (SET_SRC (XVECEXP (newpat, 0, 1)))))
2754 /* Normally, it doesn't matter which of the two is done first,
2755 but it does if one references cc0. In that case, it has to
2758 if (reg_referenced_p (cc0_rtx, XVECEXP (newpat, 0, 0)))
2760 newi2pat = XVECEXP (newpat, 0, 0);
2761 newpat = XVECEXP (newpat, 0, 1);
2766 newi2pat = XVECEXP (newpat, 0, 1);
2767 newpat = XVECEXP (newpat, 0, 0);
2770 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
2772 if (i2_code_number >= 0)
2773 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2776 /* If it still isn't recognized, fail and change things back the way they
2778 if ((insn_code_number < 0
2779 /* Is the result a reasonable ASM_OPERANDS? */
2780 && (! check_asm_operands (newpat) || added_sets_1 || added_sets_2)))
2786 /* If we had to change another insn, make sure it is valid also. */
2787 if (undobuf.other_insn)
2789 rtx other_pat = PATTERN (undobuf.other_insn);
2790 rtx new_other_notes;
2793 CLEAR_HARD_REG_SET (newpat_used_regs);
2795 other_code_number = recog_for_combine (&other_pat, undobuf.other_insn,
2798 if (other_code_number < 0 && ! check_asm_operands (other_pat))
2804 PATTERN (undobuf.other_insn) = other_pat;
2806 /* If any of the notes in OTHER_INSN were REG_UNUSED, ensure that they
2807 are still valid. Then add any non-duplicate notes added by
2808 recog_for_combine. */
2809 for (note = REG_NOTES (undobuf.other_insn); note; note = next)
2811 next = XEXP (note, 1);
2813 if (REG_NOTE_KIND (note) == REG_UNUSED
2814 && ! reg_set_p (XEXP (note, 0), PATTERN (undobuf.other_insn)))
2816 if (REG_P (XEXP (note, 0)))
2817 REG_N_DEATHS (REGNO (XEXP (note, 0)))--;
2819 remove_note (undobuf.other_insn, note);
2823 for (note = new_other_notes; note; note = XEXP (note, 1))
2824 if (REG_P (XEXP (note, 0)))
2825 REG_N_DEATHS (REGNO (XEXP (note, 0)))++;
2827 distribute_notes (new_other_notes, undobuf.other_insn,
2828 undobuf.other_insn, NULL_RTX, NULL_RTX, NULL_RTX);
2831 /* If I2 is the CC0 setter and I3 is the CC0 user then check whether
2832 they are adjacent to each other or not. */
2834 rtx p = prev_nonnote_insn (i3);
2835 if (p && p != i2 && NONJUMP_INSN_P (p) && newi2pat
2836 && sets_cc0_p (newi2pat))
2844 /* Only allow this combination if insn_rtx_costs reports that the
2845 replacement instructions are cheaper than the originals. */
2846 if (!combine_validate_cost (i1, i2, i3, newpat, newi2pat))
2852 /* We now know that we can do this combination. Merge the insns and
2853 update the status of registers and LOG_LINKS. */
2861 /* I3 now uses what used to be its destination and which is now
2862 I2's destination. This requires us to do a few adjustments. */
2863 PATTERN (i3) = newpat;
2864 adjust_for_new_dest (i3);
2866 /* We need a LOG_LINK from I3 to I2. But we used to have one,
2869 However, some later insn might be using I2's dest and have
2870 a LOG_LINK pointing at I3. We must remove this link.
2871 The simplest way to remove the link is to point it at I1,
2872 which we know will be a NOTE. */
2874 /* newi2pat is usually a SET here; however, recog_for_combine might
2875 have added some clobbers. */
2876 if (GET_CODE (newi2pat) == PARALLEL)
2877 ni2dest = SET_DEST (XVECEXP (newi2pat, 0, 0));
2879 ni2dest = SET_DEST (newi2pat);
2881 for (insn = NEXT_INSN (i3);
2882 insn && (this_basic_block->next_bb == EXIT_BLOCK_PTR
2883 || insn != BB_HEAD (this_basic_block->next_bb));
2884 insn = NEXT_INSN (insn))
2886 if (INSN_P (insn) && reg_referenced_p (ni2dest, PATTERN (insn)))
2888 for (link = LOG_LINKS (insn); link;
2889 link = XEXP (link, 1))
2890 if (XEXP (link, 0) == i3)
2891 XEXP (link, 0) = i1;
2899 rtx i3notes, i2notes, i1notes = 0;
2900 rtx i3links, i2links, i1links = 0;
2903 /* Compute which registers we expect to eliminate. newi2pat may be setting
2904 either i3dest or i2dest, so we must check it. Also, i1dest may be the
2905 same as i3dest, in which case newi2pat may be setting i1dest. */
2906 rtx elim_i2 = ((newi2pat && reg_set_p (i2dest, newi2pat))
2907 || i2dest_in_i2src || i2dest_in_i1src
2910 rtx elim_i1 = (i1 == 0 || i1dest_in_i1src
2911 || (newi2pat && reg_set_p (i1dest, newi2pat))
2915 /* Get the old REG_NOTES and LOG_LINKS from all our insns and
2917 i3notes = REG_NOTES (i3), i3links = LOG_LINKS (i3);
2918 i2notes = REG_NOTES (i2), i2links = LOG_LINKS (i2);
2920 i1notes = REG_NOTES (i1), i1links = LOG_LINKS (i1);
2922 /* Ensure that we do not have something that should not be shared but
2923 occurs multiple times in the new insns. Check this by first
2924 resetting all the `used' flags and then copying anything is shared. */
2926 reset_used_flags (i3notes);
2927 reset_used_flags (i2notes);
2928 reset_used_flags (i1notes);
2929 reset_used_flags (newpat);
2930 reset_used_flags (newi2pat);
2931 if (undobuf.other_insn)
2932 reset_used_flags (PATTERN (undobuf.other_insn));
2934 i3notes = copy_rtx_if_shared (i3notes);
2935 i2notes = copy_rtx_if_shared (i2notes);
2936 i1notes = copy_rtx_if_shared (i1notes);
2937 newpat = copy_rtx_if_shared (newpat);
2938 newi2pat = copy_rtx_if_shared (newi2pat);
2939 if (undobuf.other_insn)
2940 reset_used_flags (PATTERN (undobuf.other_insn));
2942 INSN_CODE (i3) = insn_code_number;
2943 PATTERN (i3) = newpat;
2945 if (CALL_P (i3) && CALL_INSN_FUNCTION_USAGE (i3))
2947 rtx call_usage = CALL_INSN_FUNCTION_USAGE (i3);
2949 reset_used_flags (call_usage);
2950 call_usage = copy_rtx (call_usage);
2953 replace_rtx (call_usage, i2dest, i2src);
2956 replace_rtx (call_usage, i1dest, i1src);
2958 CALL_INSN_FUNCTION_USAGE (i3) = call_usage;
2961 if (undobuf.other_insn)
2962 INSN_CODE (undobuf.other_insn) = other_code_number;
2964 /* We had one special case above where I2 had more than one set and
2965 we replaced a destination of one of those sets with the destination
2966 of I3. In that case, we have to update LOG_LINKS of insns later
2967 in this basic block. Note that this (expensive) case is rare.
2969 Also, in this case, we must pretend that all REG_NOTEs for I2
2970 actually came from I3, so that REG_UNUSED notes from I2 will be
2971 properly handled. */
2973 if (i3_subst_into_i2)
2975 for (i = 0; i < XVECLEN (PATTERN (i2), 0); i++)
2976 if (GET_CODE (XVECEXP (PATTERN (i2), 0, i)) != USE
2977 && REG_P (SET_DEST (XVECEXP (PATTERN (i2), 0, i)))
2978 && SET_DEST (XVECEXP (PATTERN (i2), 0, i)) != i2dest
2979 && ! find_reg_note (i2, REG_UNUSED,
2980 SET_DEST (XVECEXP (PATTERN (i2), 0, i))))
2981 for (temp = NEXT_INSN (i2);
2982 temp && (this_basic_block->next_bb == EXIT_BLOCK_PTR
2983 || BB_HEAD (this_basic_block) != temp);
2984 temp = NEXT_INSN (temp))
2985 if (temp != i3 && INSN_P (temp))
2986 for (link = LOG_LINKS (temp); link; link = XEXP (link, 1))
2987 if (XEXP (link, 0) == i2)
2988 XEXP (link, 0) = i3;
2993 while (XEXP (link, 1))
2994 link = XEXP (link, 1);
2995 XEXP (link, 1) = i2notes;
3009 INSN_CODE (i2) = i2_code_number;
3010 PATTERN (i2) = newi2pat;
3013 SET_INSN_DELETED (i2);
3019 SET_INSN_DELETED (i1);
3022 /* Get death notes for everything that is now used in either I3 or
3023 I2 and used to die in a previous insn. If we built two new
3024 patterns, move from I1 to I2 then I2 to I3 so that we get the
3025 proper movement on registers that I2 modifies. */
3029 move_deaths (newi2pat, NULL_RTX, INSN_CUID (i1), i2, &midnotes);
3030 move_deaths (newpat, newi2pat, INSN_CUID (i1), i3, &midnotes);
3033 move_deaths (newpat, NULL_RTX, i1 ? INSN_CUID (i1) : INSN_CUID (i2),
3036 /* Distribute all the LOG_LINKS and REG_NOTES from I1, I2, and I3. */
3038 distribute_notes (i3notes, i3, i3, newi2pat ? i2 : NULL_RTX,
3041 distribute_notes (i2notes, i2, i3, newi2pat ? i2 : NULL_RTX,
3044 distribute_notes (i1notes, i1, i3, newi2pat ? i2 : NULL_RTX,
3047 distribute_notes (midnotes, NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
3050 /* Distribute any notes added to I2 or I3 by recog_for_combine. We
3051 know these are REG_UNUSED and want them to go to the desired insn,
3052 so we always pass it as i3. We have not counted the notes in
3053 reg_n_deaths yet, so we need to do so now. */
3055 if (newi2pat && new_i2_notes)
3057 for (temp = new_i2_notes; temp; temp = XEXP (temp, 1))
3058 if (REG_P (XEXP (temp, 0)))
3059 REG_N_DEATHS (REGNO (XEXP (temp, 0)))++;
3061 distribute_notes (new_i2_notes, i2, i2, NULL_RTX, NULL_RTX, NULL_RTX);
3066 for (temp = new_i3_notes; temp; temp = XEXP (temp, 1))
3067 if (REG_P (XEXP (temp, 0)))
3068 REG_N_DEATHS (REGNO (XEXP (temp, 0)))++;
3070 distribute_notes (new_i3_notes, i3, i3, NULL_RTX, NULL_RTX, NULL_RTX);
3073 /* If I3DEST was used in I3SRC, it really died in I3. We may need to
3074 put a REG_DEAD note for it somewhere. If NEWI2PAT exists and sets
3075 I3DEST, the death must be somewhere before I2, not I3. If we passed I3
3076 in that case, it might delete I2. Similarly for I2 and I1.
3077 Show an additional death due to the REG_DEAD note we make here. If
3078 we discard it in distribute_notes, we will decrement it again. */
3082 if (REG_P (i3dest_killed))
3083 REG_N_DEATHS (REGNO (i3dest_killed))++;
3085 if (newi2pat && reg_set_p (i3dest_killed, newi2pat))
3086 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i3dest_killed,
3088 NULL_RTX, i2, NULL_RTX, elim_i2, elim_i1);
3090 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i3dest_killed,
3092 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
3096 if (i2dest_in_i2src)
3099 REG_N_DEATHS (REGNO (i2dest))++;
3101 if (newi2pat && reg_set_p (i2dest, newi2pat))
3102 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i2dest, NULL_RTX),
3103 NULL_RTX, i2, NULL_RTX, NULL_RTX, NULL_RTX);
3105 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i2dest, NULL_RTX),
3106 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
3107 NULL_RTX, NULL_RTX);
3110 if (i1dest_in_i1src)
3113 REG_N_DEATHS (REGNO (i1dest))++;
3115 if (newi2pat && reg_set_p (i1dest, newi2pat))
3116 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i1dest, NULL_RTX),
3117 NULL_RTX, i2, NULL_RTX, NULL_RTX, NULL_RTX);
3119 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i1dest, NULL_RTX),
3120 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
3121 NULL_RTX, NULL_RTX);
3124 distribute_links (i3links);
3125 distribute_links (i2links);
3126 distribute_links (i1links);
3131 rtx i2_insn = 0, i2_val = 0, set;
3133 /* The insn that used to set this register doesn't exist, and
3134 this life of the register may not exist either. See if one of
3135 I3's links points to an insn that sets I2DEST. If it does,
3136 that is now the last known value for I2DEST. If we don't update
3137 this and I2 set the register to a value that depended on its old
3138 contents, we will get confused. If this insn is used, thing
3139 will be set correctly in combine_instructions. */
3141 for (link = LOG_LINKS (i3); link; link = XEXP (link, 1))
3142 if ((set = single_set (XEXP (link, 0))) != 0
3143 && rtx_equal_p (i2dest, SET_DEST (set)))
3144 i2_insn = XEXP (link, 0), i2_val = SET_SRC (set);
3146 record_value_for_reg (i2dest, i2_insn, i2_val);
3148 /* If the reg formerly set in I2 died only once and that was in I3,
3149 zero its use count so it won't make `reload' do any work. */
3151 && (newi2pat == 0 || ! reg_mentioned_p (i2dest, newi2pat))
3152 && ! i2dest_in_i2src)
3154 regno = REGNO (i2dest);
3155 REG_N_SETS (regno)--;
3159 if (i1 && REG_P (i1dest))
3162 rtx i1_insn = 0, i1_val = 0, set;
3164 for (link = LOG_LINKS (i3); link; link = XEXP (link, 1))
3165 if ((set = single_set (XEXP (link, 0))) != 0
3166 && rtx_equal_p (i1dest, SET_DEST (set)))
3167 i1_insn = XEXP (link, 0), i1_val = SET_SRC (set);
3169 record_value_for_reg (i1dest, i1_insn, i1_val);
3171 regno = REGNO (i1dest);
3172 if (! added_sets_1 && ! i1dest_in_i1src)
3173 REG_N_SETS (regno)--;
3176 /* Update reg_stat[].nonzero_bits et al for any changes that may have
3177 been made to this insn. The order of
3178 set_nonzero_bits_and_sign_copies() is important. Because newi2pat
3179 can affect nonzero_bits of newpat */
3181 note_stores (newi2pat, set_nonzero_bits_and_sign_copies, NULL);
3182 note_stores (newpat, set_nonzero_bits_and_sign_copies, NULL);
3184 /* Set new_direct_jump_p if a new return or simple jump instruction
3187 If I3 is now an unconditional jump, ensure that it has a
3188 BARRIER following it since it may have initially been a
3189 conditional jump. It may also be the last nonnote insn. */
3191 if (returnjump_p (i3) || any_uncondjump_p (i3))
3193 *new_direct_jump_p = 1;
3194 mark_jump_label (PATTERN (i3), i3, 0);
3196 if ((temp = next_nonnote_insn (i3)) == NULL_RTX
3197 || !BARRIER_P (temp))
3198 emit_barrier_after (i3);
3201 if (undobuf.other_insn != NULL_RTX
3202 && (returnjump_p (undobuf.other_insn)
3203 || any_uncondjump_p (undobuf.other_insn)))
3205 *new_direct_jump_p = 1;
3207 if ((temp = next_nonnote_insn (undobuf.other_insn)) == NULL_RTX
3208 || !BARRIER_P (temp))
3209 emit_barrier_after (undobuf.other_insn);
3212 /* An NOOP jump does not need barrier, but it does need cleaning up
3214 if (GET_CODE (newpat) == SET
3215 && SET_SRC (newpat) == pc_rtx
3216 && SET_DEST (newpat) == pc_rtx)
3217 *new_direct_jump_p = 1;
3220 combine_successes++;
3223 if (added_links_insn
3224 && (newi2pat == 0 || INSN_CUID (added_links_insn) < INSN_CUID (i2))
3225 && INSN_CUID (added_links_insn) < INSN_CUID (i3))
3226 return added_links_insn;
3228 return newi2pat ? i2 : i3;
3231 /* Undo all the modifications recorded in undobuf. */
3236 struct undo *undo, *next;
3238 for (undo = undobuf.undos; undo; undo = next)
3242 *undo->where.i = undo->old_contents.i;
3244 *undo->where.r = undo->old_contents.r;
3246 undo->next = undobuf.frees;
3247 undobuf.frees = undo;
3253 /* We've committed to accepting the changes we made. Move all
3254 of the undos to the free list. */
3259 struct undo *undo, *next;
3261 for (undo = undobuf.undos; undo; undo = next)
3264 undo->next = undobuf.frees;
3265 undobuf.frees = undo;
3271 /* Find the innermost point within the rtx at LOC, possibly LOC itself,
3272 where we have an arithmetic expression and return that point. LOC will
3275 try_combine will call this function to see if an insn can be split into
3279 find_split_point (rtx *loc, rtx insn)
3282 enum rtx_code code = GET_CODE (x);
3284 unsigned HOST_WIDE_INT len = 0;
3285 HOST_WIDE_INT pos = 0;
3287 rtx inner = NULL_RTX;
3289 /* First special-case some codes. */
3293 #ifdef INSN_SCHEDULING
3294 /* If we are making a paradoxical SUBREG invalid, it becomes a split
3296 if (MEM_P (SUBREG_REG (x)))
3299 return find_split_point (&SUBREG_REG (x), insn);
3303 /* If we have (mem (const ..)) or (mem (symbol_ref ...)), split it
3304 using LO_SUM and HIGH. */
3305 if (GET_CODE (XEXP (x, 0)) == CONST
3306 || GET_CODE (XEXP (x, 0)) == SYMBOL_REF)
3309 gen_rtx_LO_SUM (Pmode,
3310 gen_rtx_HIGH (Pmode, XEXP (x, 0)),
3312 return &XEXP (XEXP (x, 0), 0);
3316 /* If we have a PLUS whose second operand is a constant and the
3317 address is not valid, perhaps will can split it up using
3318 the machine-specific way to split large constants. We use
3319 the first pseudo-reg (one of the virtual regs) as a placeholder;
3320 it will not remain in the result. */
3321 if (GET_CODE (XEXP (x, 0)) == PLUS
3322 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3323 && ! memory_address_p (GET_MODE (x), XEXP (x, 0)))
3325 rtx reg = regno_reg_rtx[FIRST_PSEUDO_REGISTER];
3326 rtx seq = split_insns (gen_rtx_SET (VOIDmode, reg, XEXP (x, 0)),
3329 /* This should have produced two insns, each of which sets our
3330 placeholder. If the source of the second is a valid address,
3331 we can make put both sources together and make a split point
3335 && NEXT_INSN (seq) != NULL_RTX
3336 && NEXT_INSN (NEXT_INSN (seq)) == NULL_RTX
3337 && NONJUMP_INSN_P (seq)
3338 && GET_CODE (PATTERN (seq)) == SET
3339 && SET_DEST (PATTERN (seq)) == reg
3340 && ! reg_mentioned_p (reg,
3341 SET_SRC (PATTERN (seq)))
3342 && NONJUMP_INSN_P (NEXT_INSN (seq))
3343 && GET_CODE (PATTERN (NEXT_INSN (seq))) == SET
3344 && SET_DEST (PATTERN (NEXT_INSN (seq))) == reg
3345 && memory_address_p (GET_MODE (x),
3346 SET_SRC (PATTERN (NEXT_INSN (seq)))))
3348 rtx src1 = SET_SRC (PATTERN (seq));
3349 rtx src2 = SET_SRC (PATTERN (NEXT_INSN (seq)));
3351 /* Replace the placeholder in SRC2 with SRC1. If we can
3352 find where in SRC2 it was placed, that can become our
3353 split point and we can replace this address with SRC2.
3354 Just try two obvious places. */
3356 src2 = replace_rtx (src2, reg, src1);
3358 if (XEXP (src2, 0) == src1)
3359 split = &XEXP (src2, 0);
3360 else if (GET_RTX_FORMAT (GET_CODE (XEXP (src2, 0)))[0] == 'e'
3361 && XEXP (XEXP (src2, 0), 0) == src1)
3362 split = &XEXP (XEXP (src2, 0), 0);
3366 SUBST (XEXP (x, 0), src2);
3371 /* If that didn't work, perhaps the first operand is complex and
3372 needs to be computed separately, so make a split point there.
3373 This will occur on machines that just support REG + CONST
3374 and have a constant moved through some previous computation. */
3376 else if (!OBJECT_P (XEXP (XEXP (x, 0), 0))
3377 && ! (GET_CODE (XEXP (XEXP (x, 0), 0)) == SUBREG
3378 && OBJECT_P (SUBREG_REG (XEXP (XEXP (x, 0), 0)))))
3379 return &XEXP (XEXP (x, 0), 0);
3385 /* If SET_DEST is CC0 and SET_SRC is not an operand, a COMPARE, or a
3386 ZERO_EXTRACT, the most likely reason why this doesn't match is that
3387 we need to put the operand into a register. So split at that
3390 if (SET_DEST (x) == cc0_rtx
3391 && GET_CODE (SET_SRC (x)) != COMPARE
3392 && GET_CODE (SET_SRC (x)) != ZERO_EXTRACT
3393 && !OBJECT_P (SET_SRC (x))
3394 && ! (GET_CODE (SET_SRC (x)) == SUBREG
3395 && OBJECT_P (SUBREG_REG (SET_SRC (x)))))
3396 return &SET_SRC (x);
3399 /* See if we can split SET_SRC as it stands. */
3400 split = find_split_point (&SET_SRC (x), insn);
3401 if (split && split != &SET_SRC (x))
3404 /* See if we can split SET_DEST as it stands. */
3405 split = find_split_point (&SET_DEST (x), insn);
3406 if (split && split != &SET_DEST (x))
3409 /* See if this is a bitfield assignment with everything constant. If
3410 so, this is an IOR of an AND, so split it into that. */
3411 if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
3412 && (GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0)))
3413 <= HOST_BITS_PER_WIDE_INT)
3414 && GET_CODE (XEXP (SET_DEST (x), 1)) == CONST_INT
3415 && GET_CODE (XEXP (SET_DEST (x), 2)) == CONST_INT
3416 && GET_CODE (SET_SRC (x)) == CONST_INT
3417 && ((INTVAL (XEXP (SET_DEST (x), 1))
3418 + INTVAL (XEXP (SET_DEST (x), 2)))
3419 <= GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0))))
3420 && ! side_effects_p (XEXP (SET_DEST (x), 0)))
3422 HOST_WIDE_INT pos = INTVAL (XEXP (SET_DEST (x), 2));
3423 unsigned HOST_WIDE_INT len = INTVAL (XEXP (SET_DEST (x), 1));
3424 unsigned HOST_WIDE_INT src = INTVAL (SET_SRC (x));
3425 rtx dest = XEXP (SET_DEST (x), 0);
3426 enum machine_mode mode = GET_MODE (dest);
3427 unsigned HOST_WIDE_INT mask = ((HOST_WIDE_INT) 1 << len) - 1;
3430 if (BITS_BIG_ENDIAN)
3431 pos = GET_MODE_BITSIZE (mode) - len - pos;
3433 or_mask = gen_int_mode (src << pos, mode);
3436 simplify_gen_binary (IOR, mode, dest, or_mask));
3439 rtx negmask = gen_int_mode (~(mask << pos), mode);
3441 simplify_gen_binary (IOR, mode,
3442 simplify_gen_binary (AND, mode,
3447 SUBST (SET_DEST (x), dest);
3449 split = find_split_point (&SET_SRC (x), insn);
3450 if (split && split != &SET_SRC (x))
3454 /* Otherwise, see if this is an operation that we can split into two.
3455 If so, try to split that. */
3456 code = GET_CODE (SET_SRC (x));
3461 /* If we are AND'ing with a large constant that is only a single
3462 bit and the result is only being used in a context where we
3463 need to know if it is zero or nonzero, replace it with a bit
3464 extraction. This will avoid the large constant, which might
3465 have taken more than one insn to make. If the constant were
3466 not a valid argument to the AND but took only one insn to make,
3467 this is no worse, but if it took more than one insn, it will
3470 if (GET_CODE (XEXP (SET_SRC (x), 1)) == CONST_INT
3471 && REG_P (XEXP (SET_SRC (x), 0))
3472 && (pos = exact_log2 (INTVAL (XEXP (SET_SRC (x), 1)))) >= 7
3473 && REG_P (SET_DEST (x))
3474 && (split = find_single_use (SET_DEST (x), insn, (rtx*) 0)) != 0
3475 && (GET_CODE (*split) == EQ || GET_CODE (*split) == NE)
3476 && XEXP (*split, 0) == SET_DEST (x)
3477 && XEXP (*split, 1) == const0_rtx)
3479 rtx extraction = make_extraction (GET_MODE (SET_DEST (x)),
3480 XEXP (SET_SRC (x), 0),
3481 pos, NULL_RTX, 1, 1, 0, 0);
3482 if (extraction != 0)
3484 SUBST (SET_SRC (x), extraction);
3485 return find_split_point (loc, insn);
3491 /* If STORE_FLAG_VALUE is -1, this is (NE X 0) and only one bit of X
3492 is known to be on, this can be converted into a NEG of a shift. */
3493 if (STORE_FLAG_VALUE == -1 && XEXP (SET_SRC (x), 1) == const0_rtx
3494 && GET_MODE (SET_SRC (x)) == GET_MODE (XEXP (SET_SRC (x), 0))
3495 && 1 <= (pos = exact_log2
3496 (nonzero_bits (XEXP (SET_SRC (x), 0),
3497 GET_MODE (XEXP (SET_SRC (x), 0))))))
3499 enum machine_mode mode = GET_MODE (XEXP (SET_SRC (x), 0));
3503 gen_rtx_LSHIFTRT (mode,
3504 XEXP (SET_SRC (x), 0),
3507 split = find_split_point (&SET_SRC (x), insn);
3508 if (split && split != &SET_SRC (x))
3514 inner = XEXP (SET_SRC (x), 0);
3516 /* We can't optimize if either mode is a partial integer
3517 mode as we don't know how many bits are significant
3519 if (GET_MODE_CLASS (GET_MODE (inner)) == MODE_PARTIAL_INT
3520 || GET_MODE_CLASS (GET_MODE (SET_SRC (x))) == MODE_PARTIAL_INT)
3524 len = GET_MODE_BITSIZE (GET_MODE (inner));
3530 if (GET_CODE (XEXP (SET_SRC (x), 1)) == CONST_INT
3531 && GET_CODE (XEXP (SET_SRC (x), 2)) == CONST_INT)
3533 inner = XEXP (SET_SRC (x), 0);
3534 len = INTVAL (XEXP (SET_SRC (x), 1));
3535 pos = INTVAL (XEXP (SET_SRC (x), 2));
3537 if (BITS_BIG_ENDIAN)
3538 pos = GET_MODE_BITSIZE (GET_MODE (inner)) - len - pos;
3539 unsignedp = (code == ZERO_EXTRACT);
3547 if (len && pos >= 0 && pos + len <= GET_MODE_BITSIZE (GET_MODE (inner)))
3549 enum machine_mode mode = GET_MODE (SET_SRC (x));
3551 /* For unsigned, we have a choice of a shift followed by an
3552 AND or two shifts. Use two shifts for field sizes where the
3553 constant might be too large. We assume here that we can
3554 always at least get 8-bit constants in an AND insn, which is
3555 true for every current RISC. */
3557 if (unsignedp && len <= 8)
3562 (mode, gen_lowpart (mode, inner),
3564 GEN_INT (((HOST_WIDE_INT) 1 << len) - 1)));
3566 split = find_split_point (&SET_SRC (x), insn);
3567 if (split && split != &SET_SRC (x))
3574 (unsignedp ? LSHIFTRT : ASHIFTRT, mode,
3575 gen_rtx_ASHIFT (mode,
3576 gen_lowpart (mode, inner),
3577 GEN_INT (GET_MODE_BITSIZE (mode)
3579 GEN_INT (GET_MODE_BITSIZE (mode) - len)));
3581 split = find_split_point (&SET_SRC (x), insn);
3582 if (split && split != &SET_SRC (x))
3587 /* See if this is a simple operation with a constant as the second
3588 operand. It might be that this constant is out of range and hence
3589 could be used as a split point. */
3590 if (BINARY_P (SET_SRC (x))
3591 && CONSTANT_P (XEXP (SET_SRC (x), 1))
3592 && (OBJECT_P (XEXP (SET_SRC (x), 0))
3593 || (GET_CODE (XEXP (SET_SRC (x), 0)) == SUBREG
3594 && OBJECT_P (SUBREG_REG (XEXP (SET_SRC (x), 0))))))
3595 return &XEXP (SET_SRC (x), 1);
3597 /* Finally, see if this is a simple operation with its first operand
3598 not in a register. The operation might require this operand in a
3599 register, so return it as a split point. We can always do this
3600 because if the first operand were another operation, we would have
3601 already found it as a split point. */
3602 if ((BINARY_P (SET_SRC (x)) || UNARY_P (SET_SRC (x)))
3603 && ! register_operand (XEXP (SET_SRC (x), 0), VOIDmode))
3604 return &XEXP (SET_SRC (x), 0);
3610 /* We write NOR as (and (not A) (not B)), but if we don't have a NOR,
3611 it is better to write this as (not (ior A B)) so we can split it.
3612 Similarly for IOR. */
3613 if (GET_CODE (XEXP (x, 0)) == NOT && GET_CODE (XEXP (x, 1)) == NOT)
3616 gen_rtx_NOT (GET_MODE (x),
3617 gen_rtx_fmt_ee (code == IOR ? AND : IOR,
3619 XEXP (XEXP (x, 0), 0),
3620 XEXP (XEXP (x, 1), 0))));
3621 return find_split_point (loc, insn);
3624 /* Many RISC machines have a large set of logical insns. If the
3625 second operand is a NOT, put it first so we will try to split the
3626 other operand first. */
3627 if (GET_CODE (XEXP (x, 1)) == NOT)
3629 rtx tem = XEXP (x, 0);
3630 SUBST (XEXP (x, 0), XEXP (x, 1));
3631 SUBST (XEXP (x, 1), tem);
3639 /* Otherwise, select our actions depending on our rtx class. */
3640 switch (GET_RTX_CLASS (code))
3642 case RTX_BITFIELD_OPS: /* This is ZERO_EXTRACT and SIGN_EXTRACT. */
3644 split = find_split_point (&XEXP (x, 2), insn);
3647 /* ... fall through ... */
3649 case RTX_COMM_ARITH:
3651 case RTX_COMM_COMPARE:
3652 split = find_split_point (&XEXP (x, 1), insn);
3655 /* ... fall through ... */
3657 /* Some machines have (and (shift ...) ...) insns. If X is not
3658 an AND, but XEXP (X, 0) is, use it as our split point. */
3659 if (GET_CODE (x) != AND && GET_CODE (XEXP (x, 0)) == AND)
3660 return &XEXP (x, 0);
3662 split = find_split_point (&XEXP (x, 0), insn);
3668 /* Otherwise, we don't have a split point. */
3673 /* Throughout X, replace FROM with TO, and return the result.
3674 The result is TO if X is FROM;
3675 otherwise the result is X, but its contents may have been modified.
3676 If they were modified, a record was made in undobuf so that
3677 undo_all will (among other things) return X to its original state.
3679 If the number of changes necessary is too much to record to undo,
3680 the excess changes are not made, so the result is invalid.
3681 The changes already made can still be undone.
3682 undobuf.num_undo is incremented for such changes, so by testing that
3683 the caller can tell whether the result is valid.
3685 `n_occurrences' is incremented each time FROM is replaced.
3687 IN_DEST is nonzero if we are processing the SET_DEST of a SET.
3689 UNIQUE_COPY is nonzero if each substitution must be unique. We do this
3690 by copying if `n_occurrences' is nonzero. */
3693 subst (rtx x, rtx from, rtx to, int in_dest, int unique_copy)
3695 enum rtx_code code = GET_CODE (x);
3696 enum machine_mode op0_mode = VOIDmode;
3701 /* Two expressions are equal if they are identical copies of a shared
3702 RTX or if they are both registers with the same register number
3705 #define COMBINE_RTX_EQUAL_P(X,Y) \
3707 || (REG_P (X) && REG_P (Y) \
3708 && REGNO (X) == REGNO (Y) && GET_MODE (X) == GET_MODE (Y)))
3710 if (! in_dest && COMBINE_RTX_EQUAL_P (x, from))
3713 return (unique_copy && n_occurrences > 1 ? copy_rtx (to) : to);
3716 /* If X and FROM are the same register but different modes, they will
3717 not have been seen as equal above. However, flow.c will make a
3718 LOG_LINKS entry for that case. If we do nothing, we will try to
3719 rerecognize our original insn and, when it succeeds, we will
3720 delete the feeding insn, which is incorrect.
3722 So force this insn not to match in this (rare) case. */
3723 if (! in_dest && code == REG && REG_P (from)
3724 && REGNO (x) == REGNO (from))
3725 return gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
3727 /* If this is an object, we are done unless it is a MEM or LO_SUM, both
3728 of which may contain things that can be combined. */
3729 if (code != MEM && code != LO_SUM && OBJECT_P (x))
3732 /* It is possible to have a subexpression appear twice in the insn.
3733 Suppose that FROM is a register that appears within TO.
3734 Then, after that subexpression has been scanned once by `subst',
3735 the second time it is scanned, TO may be found. If we were
3736 to scan TO here, we would find FROM within it and create a
3737 self-referent rtl structure which is completely wrong. */
3738 if (COMBINE_RTX_EQUAL_P (x, to))
3741 /* Parallel asm_operands need special attention because all of the
3742 inputs are shared across the arms. Furthermore, unsharing the
3743 rtl results in recognition failures. Failure to handle this case
3744 specially can result in circular rtl.
3746 Solve this by doing a normal pass across the first entry of the
3747 parallel, and only processing the SET_DESTs of the subsequent
3750 if (code == PARALLEL
3751 && GET_CODE (XVECEXP (x, 0, 0)) == SET
3752 && GET_CODE (SET_SRC (XVECEXP (x, 0, 0))) == ASM_OPERANDS)
3754 new = subst (XVECEXP (x, 0, 0), from, to, 0, unique_copy);
3756 /* If this substitution failed, this whole thing fails. */
3757 if (GET_CODE (new) == CLOBBER
3758 && XEXP (new, 0) == const0_rtx)
3761 SUBST (XVECEXP (x, 0, 0), new);
3763 for (i = XVECLEN (x, 0) - 1; i >= 1; i--)
3765 rtx dest = SET_DEST (XVECEXP (x, 0, i));
3768 && GET_CODE (dest) != CC0
3769 && GET_CODE (dest) != PC)
3771 new = subst (dest, from, to, 0, unique_copy);
3773 /* If this substitution failed, this whole thing fails. */
3774 if (GET_CODE (new) == CLOBBER
3775 && XEXP (new, 0) == const0_rtx)
3778 SUBST (SET_DEST (XVECEXP (x, 0, i)), new);
3784 len = GET_RTX_LENGTH (code);
3785 fmt = GET_RTX_FORMAT (code);
3787 /* We don't need to process a SET_DEST that is a register, CC0,
3788 or PC, so set up to skip this common case. All other cases
3789 where we want to suppress replacing something inside a
3790 SET_SRC are handled via the IN_DEST operand. */
3792 && (REG_P (SET_DEST (x))
3793 || GET_CODE (SET_DEST (x)) == CC0
3794 || GET_CODE (SET_DEST (x)) == PC))
3797 /* Get the mode of operand 0 in case X is now a SIGN_EXTEND of a
3800 op0_mode = GET_MODE (XEXP (x, 0));
3802 for (i = 0; i < len; i++)
3807 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
3809 if (COMBINE_RTX_EQUAL_P (XVECEXP (x, i, j), from))
3811 new = (unique_copy && n_occurrences
3812 ? copy_rtx (to) : to);
3817 new = subst (XVECEXP (x, i, j), from, to, 0,
3820 /* If this substitution failed, this whole thing
3822 if (GET_CODE (new) == CLOBBER
3823 && XEXP (new, 0) == const0_rtx)
3827 SUBST (XVECEXP (x, i, j), new);
3830 else if (fmt[i] == 'e')
3832 /* If this is a register being set, ignore it. */
3836 && (((code == SUBREG || code == ZERO_EXTRACT)
3838 || code == STRICT_LOW_PART))
3841 else if (COMBINE_RTX_EQUAL_P (XEXP (x, i), from))
3843 /* In general, don't install a subreg involving two
3844 modes not tieable. It can worsen register
3845 allocation, and can even make invalid reload
3846 insns, since the reg inside may need to be copied
3847 from in the outside mode, and that may be invalid
3848 if it is an fp reg copied in integer mode.
3850 We allow two exceptions to this: It is valid if
3851 it is inside another SUBREG and the mode of that
3852 SUBREG and the mode of the inside of TO is
3853 tieable and it is valid if X is a SET that copies
3856 if (GET_CODE (to) == SUBREG
3857 && ! MODES_TIEABLE_P (GET_MODE (to),
3858 GET_MODE (SUBREG_REG (to)))
3859 && ! (code == SUBREG
3860 && MODES_TIEABLE_P (GET_MODE (x),
3861 GET_MODE (SUBREG_REG (to))))
3863 && ! (code == SET && i == 1 && XEXP (x, 0) == cc0_rtx)
3866 return gen_rtx_CLOBBER (VOIDmode, const0_rtx);
3868 #ifdef CANNOT_CHANGE_MODE_CLASS
3871 && REGNO (to) < FIRST_PSEUDO_REGISTER
3872 && REG_CANNOT_CHANGE_MODE_P (REGNO (to),
3875 return gen_rtx_CLOBBER (VOIDmode, const0_rtx);
3878 new = (unique_copy && n_occurrences ? copy_rtx (to) : to);
3882 /* If we are in a SET_DEST, suppress most cases unless we
3883 have gone inside a MEM, in which case we want to
3884 simplify the address. We assume here that things that
3885 are actually part of the destination have their inner
3886 parts in the first expression. This is true for SUBREG,
3887 STRICT_LOW_PART, and ZERO_EXTRACT, which are the only
3888 things aside from REG and MEM that should appear in a
3890 new = subst (XEXP (x, i), from, to,
3892 && (code == SUBREG || code == STRICT_LOW_PART
3893 || code == ZERO_EXTRACT))
3895 && i == 0), unique_copy);
3897 /* If we found that we will have to reject this combination,
3898 indicate that by returning the CLOBBER ourselves, rather than
3899 an expression containing it. This will speed things up as
3900 well as prevent accidents where two CLOBBERs are considered
3901 to be equal, thus producing an incorrect simplification. */
3903 if (GET_CODE (new) == CLOBBER && XEXP (new, 0) == const0_rtx)
3906 if (GET_CODE (x) == SUBREG
3907 && (GET_CODE (new) == CONST_INT
3908 || GET_CODE (new) == CONST_DOUBLE))
3910 enum machine_mode mode = GET_MODE (x);
3912 x = simplify_subreg (GET_MODE (x), new,
3913 GET_MODE (SUBREG_REG (x)),
3916 x = gen_rtx_CLOBBER (mode, const0_rtx);
3918 else if (GET_CODE (new) == CONST_INT
3919 && GET_CODE (x) == ZERO_EXTEND)
3921 x = simplify_unary_operation (ZERO_EXTEND, GET_MODE (x),
3922 new, GET_MODE (XEXP (x, 0)));
3926 SUBST (XEXP (x, i), new);
3931 /* Try to simplify X. If the simplification changed the code, it is likely
3932 that further simplification will help, so loop, but limit the number
3933 of repetitions that will be performed. */
3935 for (i = 0; i < 4; i++)
3937 /* If X is sufficiently simple, don't bother trying to do anything
3939 if (code != CONST_INT && code != REG && code != CLOBBER)
3940 x = combine_simplify_rtx (x, op0_mode, in_dest);
3942 if (GET_CODE (x) == code)
3945 code = GET_CODE (x);
3947 /* We no longer know the original mode of operand 0 since we
3948 have changed the form of X) */
3949 op0_mode = VOIDmode;
3955 /* Simplify X, a piece of RTL. We just operate on the expression at the
3956 outer level; call `subst' to simplify recursively. Return the new
3959 OP0_MODE is the original mode of XEXP (x, 0). IN_DEST is nonzero
3960 if we are inside a SET_DEST. */
3963 combine_simplify_rtx (rtx x, enum machine_mode op0_mode, int in_dest)
3965 enum rtx_code code = GET_CODE (x);
3966 enum machine_mode mode = GET_MODE (x);
3970 /* If this is a commutative operation, put a constant last and a complex
3971 expression first. We don't need to do this for comparisons here. */
3972 if (COMMUTATIVE_ARITH_P (x)
3973 && swap_commutative_operands_p (XEXP (x, 0), XEXP (x, 1)))
3976 SUBST (XEXP (x, 0), XEXP (x, 1));
3977 SUBST (XEXP (x, 1), temp);
3980 /* If this is a simple operation applied to an IF_THEN_ELSE, try
3981 applying it to the arms of the IF_THEN_ELSE. This often simplifies
3982 things. Check for cases where both arms are testing the same
3985 Don't do anything if all operands are very simple. */
3988 && ((!OBJECT_P (XEXP (x, 0))
3989 && ! (GET_CODE (XEXP (x, 0)) == SUBREG
3990 && OBJECT_P (SUBREG_REG (XEXP (x, 0)))))
3991 || (!OBJECT_P (XEXP (x, 1))
3992 && ! (GET_CODE (XEXP (x, 1)) == SUBREG
3993 && OBJECT_P (SUBREG_REG (XEXP (x, 1)))))))
3995 && (!OBJECT_P (XEXP (x, 0))
3996 && ! (GET_CODE (XEXP (x, 0)) == SUBREG
3997 && OBJECT_P (SUBREG_REG (XEXP (x, 0)))))))
3999 rtx cond, true_rtx, false_rtx;
4001 cond = if_then_else_cond (x, &true_rtx, &false_rtx);
4003 /* If everything is a comparison, what we have is highly unlikely
4004 to be simpler, so don't use it. */
4005 && ! (COMPARISON_P (x)
4006 && (COMPARISON_P (true_rtx) || COMPARISON_P (false_rtx))))
4008 rtx cop1 = const0_rtx;
4009 enum rtx_code cond_code = simplify_comparison (NE, &cond, &cop1);
4011 if (cond_code == NE && COMPARISON_P (cond))
4014 /* Simplify the alternative arms; this may collapse the true and
4015 false arms to store-flag values. Be careful to use copy_rtx
4016 here since true_rtx or false_rtx might share RTL with x as a
4017 result of the if_then_else_cond call above. */
4018 true_rtx = subst (copy_rtx (true_rtx), pc_rtx, pc_rtx, 0, 0);
4019 false_rtx = subst (copy_rtx (false_rtx), pc_rtx, pc_rtx, 0, 0);
4021 /* If true_rtx and false_rtx are not general_operands, an if_then_else
4022 is unlikely to be simpler. */
4023 if (general_operand (true_rtx, VOIDmode)
4024 && general_operand (false_rtx, VOIDmode))
4026 enum rtx_code reversed;
4028 /* Restarting if we generate a store-flag expression will cause
4029 us to loop. Just drop through in this case. */
4031 /* If the result values are STORE_FLAG_VALUE and zero, we can
4032 just make the comparison operation. */
4033 if (true_rtx == const_true_rtx && false_rtx == const0_rtx)
4034 x = simplify_gen_relational (cond_code, mode, VOIDmode,
4036 else if (true_rtx == const0_rtx && false_rtx == const_true_rtx
4037 && ((reversed = reversed_comparison_code_parts
4038 (cond_code, cond, cop1, NULL))
4040 x = simplify_gen_relational (reversed, mode, VOIDmode,
4043 /* Likewise, we can make the negate of a comparison operation
4044 if the result values are - STORE_FLAG_VALUE and zero. */
4045 else if (GET_CODE (true_rtx) == CONST_INT
4046 && INTVAL (true_rtx) == - STORE_FLAG_VALUE
4047 && false_rtx == const0_rtx)
4048 x = simplify_gen_unary (NEG, mode,
4049 simplify_gen_relational (cond_code,
4053 else if (GET_CODE (false_rtx) == CONST_INT
4054 && INTVAL (false_rtx) == - STORE_FLAG_VALUE
4055 && true_rtx == const0_rtx
4056 && ((reversed = reversed_comparison_code_parts
4057 (cond_code, cond, cop1, NULL))
4059 x = simplify_gen_unary (NEG, mode,
4060 simplify_gen_relational (reversed,
4065 return gen_rtx_IF_THEN_ELSE (mode,
4066 simplify_gen_relational (cond_code,
4071 true_rtx, false_rtx);
4073 code = GET_CODE (x);
4074 op0_mode = VOIDmode;
4079 /* Try to fold this expression in case we have constants that weren't
4082 switch (GET_RTX_CLASS (code))
4085 if (op0_mode == VOIDmode)
4086 op0_mode = GET_MODE (XEXP (x, 0));
4087 temp = simplify_unary_operation (code, mode, XEXP (x, 0), op0_mode);
4090 case RTX_COMM_COMPARE:
4092 enum machine_mode cmp_mode = GET_MODE (XEXP (x, 0));
4093 if (cmp_mode == VOIDmode)
4095 cmp_mode = GET_MODE (XEXP (x, 1));
4096 if (cmp_mode == VOIDmode)
4097 cmp_mode = op0_mode;
4099 temp = simplify_relational_operation (code, mode, cmp_mode,
4100 XEXP (x, 0), XEXP (x, 1));
4103 case RTX_COMM_ARITH:
4105 temp = simplify_binary_operation (code, mode, XEXP (x, 0), XEXP (x, 1));
4107 case RTX_BITFIELD_OPS:
4109 temp = simplify_ternary_operation (code, mode, op0_mode, XEXP (x, 0),
4110 XEXP (x, 1), XEXP (x, 2));
4119 code = GET_CODE (temp);
4120 op0_mode = VOIDmode;
4121 mode = GET_MODE (temp);
4124 /* First see if we can apply the inverse distributive law. */
4125 if (code == PLUS || code == MINUS
4126 || code == AND || code == IOR || code == XOR)
4128 x = apply_distributive_law (x);
4129 code = GET_CODE (x);
4130 op0_mode = VOIDmode;
4133 /* If CODE is an associative operation not otherwise handled, see if we
4134 can associate some operands. This can win if they are constants or
4135 if they are logically related (i.e. (a & b) & a). */
4136 if ((code == PLUS || code == MINUS || code == MULT || code == DIV
4137 || code == AND || code == IOR || code == XOR
4138 || code == SMAX || code == SMIN || code == UMAX || code == UMIN)
4139 && ((INTEGRAL_MODE_P (mode) && code != DIV)
4140 || (flag_unsafe_math_optimizations && FLOAT_MODE_P (mode))))
4142 if (GET_CODE (XEXP (x, 0)) == code)
4144 rtx other = XEXP (XEXP (x, 0), 0);
4145 rtx inner_op0 = XEXP (XEXP (x, 0), 1);
4146 rtx inner_op1 = XEXP (x, 1);
4149 /* Make sure we pass the constant operand if any as the second
4150 one if this is a commutative operation. */
4151 if (CONSTANT_P (inner_op0) && COMMUTATIVE_ARITH_P (x))
4153 rtx tem = inner_op0;
4154 inner_op0 = inner_op1;
4157 inner = simplify_binary_operation (code == MINUS ? PLUS
4158 : code == DIV ? MULT
4160 mode, inner_op0, inner_op1);
4162 /* For commutative operations, try the other pair if that one
4164 if (inner == 0 && COMMUTATIVE_ARITH_P (x))
4166 other = XEXP (XEXP (x, 0), 1);
4167 inner = simplify_binary_operation (code, mode,
4168 XEXP (XEXP (x, 0), 0),
4173 return simplify_gen_binary (code, mode, other, inner);
4177 /* A little bit of algebraic simplification here. */
4181 /* Ensure that our address has any ASHIFTs converted to MULT in case
4182 address-recognizing predicates are called later. */
4183 temp = make_compound_operation (XEXP (x, 0), MEM);
4184 SUBST (XEXP (x, 0), temp);
4188 if (op0_mode == VOIDmode)
4189 op0_mode = GET_MODE (SUBREG_REG (x));
4191 /* See if this can be moved to simplify_subreg. */
4192 if (CONSTANT_P (SUBREG_REG (x))
4193 && subreg_lowpart_offset (mode, op0_mode) == SUBREG_BYTE (x)
4194 /* Don't call gen_lowpart if the inner mode
4195 is VOIDmode and we cannot simplify it, as SUBREG without
4196 inner mode is invalid. */
4197 && (GET_MODE (SUBREG_REG (x)) != VOIDmode
4198 || gen_lowpart_common (mode, SUBREG_REG (x))))
4199 return gen_lowpart (mode, SUBREG_REG (x));
4201 if (GET_MODE_CLASS (GET_MODE (SUBREG_REG (x))) == MODE_CC)
4205 temp = simplify_subreg (mode, SUBREG_REG (x), op0_mode,
4211 /* Don't change the mode of the MEM if that would change the meaning
4213 if (MEM_P (SUBREG_REG (x))
4214 && (MEM_VOLATILE_P (SUBREG_REG (x))
4215 || mode_dependent_address_p (XEXP (SUBREG_REG (x), 0))))
4216 return gen_rtx_CLOBBER (mode, const0_rtx);
4218 /* Note that we cannot do any narrowing for non-constants since
4219 we might have been counting on using the fact that some bits were
4220 zero. We now do this in the SET. */
4225 temp = expand_compound_operation (XEXP (x, 0));
4227 /* For C equal to the width of MODE minus 1, (neg (ashiftrt X C)) can be
4228 replaced by (lshiftrt X C). This will convert
4229 (neg (sign_extract X 1 Y)) to (zero_extract X 1 Y). */
4231 if (GET_CODE (temp) == ASHIFTRT
4232 && GET_CODE (XEXP (temp, 1)) == CONST_INT
4233 && INTVAL (XEXP (temp, 1)) == GET_MODE_BITSIZE (mode) - 1)
4234 return simplify_shift_const (temp, LSHIFTRT, mode, XEXP (temp, 0),
4235 INTVAL (XEXP (temp, 1)));
4237 /* If X has only a single bit that might be nonzero, say, bit I, convert
4238 (neg X) to (ashiftrt (ashift X C-I) C-I) where C is the bitsize of
4239 MODE minus 1. This will convert (neg (zero_extract X 1 Y)) to
4240 (sign_extract X 1 Y). But only do this if TEMP isn't a register
4241 or a SUBREG of one since we'd be making the expression more
4242 complex if it was just a register. */
4245 && ! (GET_CODE (temp) == SUBREG
4246 && REG_P (SUBREG_REG (temp)))
4247 && (i = exact_log2 (nonzero_bits (temp, mode))) >= 0)
4249 rtx temp1 = simplify_shift_const
4250 (NULL_RTX, ASHIFTRT, mode,
4251 simplify_shift_const (NULL_RTX, ASHIFT, mode, temp,
4252 GET_MODE_BITSIZE (mode) - 1 - i),
4253 GET_MODE_BITSIZE (mode) - 1 - i);
4255 /* If all we did was surround TEMP with the two shifts, we
4256 haven't improved anything, so don't use it. Otherwise,
4257 we are better off with TEMP1. */
4258 if (GET_CODE (temp1) != ASHIFTRT
4259 || GET_CODE (XEXP (temp1, 0)) != ASHIFT
4260 || XEXP (XEXP (temp1, 0), 0) != temp)
4266 /* We can't handle truncation to a partial integer mode here
4267 because we don't know the real bitsize of the partial
4269 if (GET_MODE_CLASS (mode) == MODE_PARTIAL_INT)
4272 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4273 && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode),
4274 GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))))
4276 force_to_mode (XEXP (x, 0), GET_MODE (XEXP (x, 0)),
4277 GET_MODE_MASK (mode), 0));
4279 /* Similarly to what we do in simplify-rtx.c, a truncate of a register
4280 whose value is a comparison can be replaced with a subreg if
4281 STORE_FLAG_VALUE permits. */
4282 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4283 && ((HOST_WIDE_INT) STORE_FLAG_VALUE & ~GET_MODE_MASK (mode)) == 0
4284 && (temp = get_last_value (XEXP (x, 0)))
4285 && COMPARISON_P (temp))
4286 return gen_lowpart (mode, XEXP (x, 0));
4291 /* Convert (compare FOO (const_int 0)) to FOO unless we aren't
4292 using cc0, in which case we want to leave it as a COMPARE
4293 so we can distinguish it from a register-register-copy. */
4294 if (XEXP (x, 1) == const0_rtx)
4297 /* x - 0 is the same as x unless x's mode has signed zeros and
4298 allows rounding towards -infinity. Under those conditions,
4300 if (!(HONOR_SIGNED_ZEROS (GET_MODE (XEXP (x, 0)))
4301 && HONOR_SIGN_DEPENDENT_ROUNDING (GET_MODE (XEXP (x, 0))))
4302 && XEXP (x, 1) == CONST0_RTX (GET_MODE (XEXP (x, 0))))
4308 /* (const (const X)) can become (const X). Do it this way rather than
4309 returning the inner CONST since CONST can be shared with a
4311 if (GET_CODE (XEXP (x, 0)) == CONST)
4312 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4317 /* Convert (lo_sum (high FOO) FOO) to FOO. This is necessary so we
4318 can add in an offset. find_split_point will split this address up
4319 again if it doesn't match. */
4320 if (GET_CODE (XEXP (x, 0)) == HIGH
4321 && rtx_equal_p (XEXP (XEXP (x, 0), 0), XEXP (x, 1)))
4327 /* (plus (xor (and <foo> (const_int pow2 - 1)) <c>) <-c>)
4328 when c is (const_int (pow2 + 1) / 2) is a sign extension of a
4329 bit-field and can be replaced by either a sign_extend or a
4330 sign_extract. The `and' may be a zero_extend and the two
4331 <c>, -<c> constants may be reversed. */
4332 if (GET_CODE (XEXP (x, 0)) == XOR
4333 && GET_CODE (XEXP (x, 1)) == CONST_INT
4334 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
4335 && INTVAL (XEXP (x, 1)) == -INTVAL (XEXP (XEXP (x, 0), 1))
4336 && ((i = exact_log2 (INTVAL (XEXP (XEXP (x, 0), 1)))) >= 0
4337 || (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0)
4338 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4339 && ((GET_CODE (XEXP (XEXP (x, 0), 0)) == AND
4340 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == CONST_INT
4341 && (INTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1))
4342 == ((HOST_WIDE_INT) 1 << (i + 1)) - 1))
4343 || (GET_CODE (XEXP (XEXP (x, 0), 0)) == ZERO_EXTEND
4344 && (GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)))
4345 == (unsigned int) i + 1))))
4346 return simplify_shift_const
4347 (NULL_RTX, ASHIFTRT, mode,
4348 simplify_shift_const (NULL_RTX, ASHIFT, mode,
4349 XEXP (XEXP (XEXP (x, 0), 0), 0),
4350 GET_MODE_BITSIZE (mode) - (i + 1)),
4351 GET_MODE_BITSIZE (mode) - (i + 1));
4353 /* If only the low-order bit of X is possibly nonzero, (plus x -1)
4354 can become (ashiftrt (ashift (xor x 1) C) C) where C is
4355 the bitsize of the mode - 1. This allows simplification of
4356 "a = (b & 8) == 0;" */
4357 if (XEXP (x, 1) == constm1_rtx
4358 && !REG_P (XEXP (x, 0))
4359 && ! (GET_CODE (XEXP (x, 0)) == SUBREG
4360 && REG_P (SUBREG_REG (XEXP (x, 0))))
4361 && nonzero_bits (XEXP (x, 0), mode) == 1)
4362 return simplify_shift_const (NULL_RTX, ASHIFTRT, mode,
4363 simplify_shift_const (NULL_RTX, ASHIFT, mode,
4364 gen_rtx_XOR (mode, XEXP (x, 0), const1_rtx),
4365 GET_MODE_BITSIZE (mode) - 1),
4366 GET_MODE_BITSIZE (mode) - 1);
4368 /* If we are adding two things that have no bits in common, convert
4369 the addition into an IOR. This will often be further simplified,
4370 for example in cases like ((a & 1) + (a & 2)), which can
4373 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4374 && (nonzero_bits (XEXP (x, 0), mode)
4375 & nonzero_bits (XEXP (x, 1), mode)) == 0)
4377 /* Try to simplify the expression further. */
4378 rtx tor = simplify_gen_binary (IOR, mode, XEXP (x, 0), XEXP (x, 1));
4379 temp = combine_simplify_rtx (tor, mode, in_dest);
4381 /* If we could, great. If not, do not go ahead with the IOR
4382 replacement, since PLUS appears in many special purpose
4383 address arithmetic instructions. */
4384 if (GET_CODE (temp) != CLOBBER && temp != tor)
4390 /* (minus <foo> (and <foo> (const_int -pow2))) becomes
4391 (and <foo> (const_int pow2-1)) */
4392 if (GET_CODE (XEXP (x, 1)) == AND
4393 && GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT
4394 && exact_log2 (-INTVAL (XEXP (XEXP (x, 1), 1))) >= 0
4395 && rtx_equal_p (XEXP (XEXP (x, 1), 0), XEXP (x, 0)))
4396 return simplify_and_const_int (NULL_RTX, mode, XEXP (x, 0),
4397 -INTVAL (XEXP (XEXP (x, 1), 1)) - 1);
4401 /* If we have (mult (plus A B) C), apply the distributive law and then
4402 the inverse distributive law to see if things simplify. This
4403 occurs mostly in addresses, often when unrolling loops. */
4405 if (GET_CODE (XEXP (x, 0)) == PLUS)
4407 rtx result = distribute_and_simplify_rtx (x, 0);
4412 /* Try simplify a*(b/c) as (a*b)/c. */
4413 if (FLOAT_MODE_P (mode) && flag_unsafe_math_optimizations
4414 && GET_CODE (XEXP (x, 0)) == DIV)
4416 rtx tem = simplify_binary_operation (MULT, mode,
4417 XEXP (XEXP (x, 0), 0),
4420 return simplify_gen_binary (DIV, mode, tem, XEXP (XEXP (x, 0), 1));
4425 /* If this is a divide by a power of two, treat it as a shift if
4426 its first operand is a shift. */
4427 if (GET_CODE (XEXP (x, 1)) == CONST_INT
4428 && (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0
4429 && (GET_CODE (XEXP (x, 0)) == ASHIFT
4430 || GET_CODE (XEXP (x, 0)) == LSHIFTRT
4431 || GET_CODE (XEXP (x, 0)) == ASHIFTRT
4432 || GET_CODE (XEXP (x, 0)) == ROTATE
4433 || GET_CODE (XEXP (x, 0)) == ROTATERT))
4434 return simplify_shift_const (NULL_RTX, LSHIFTRT, mode, XEXP (x, 0), i);
4438 case GT: case GTU: case GE: case GEU:
4439 case LT: case LTU: case LE: case LEU:
4440 case UNEQ: case LTGT:
4441 case UNGT: case UNGE:
4442 case UNLT: case UNLE:
4443 case UNORDERED: case ORDERED:
4444 /* If the first operand is a condition code, we can't do anything
4446 if (GET_CODE (XEXP (x, 0)) == COMPARE
4447 || (GET_MODE_CLASS (GET_MODE (XEXP (x, 0))) != MODE_CC
4448 && ! CC0_P (XEXP (x, 0))))
4450 rtx op0 = XEXP (x, 0);
4451 rtx op1 = XEXP (x, 1);
4452 enum rtx_code new_code;
4454 if (GET_CODE (op0) == COMPARE)
4455 op1 = XEXP (op0, 1), op0 = XEXP (op0, 0);
4457 /* Simplify our comparison, if possible. */
4458 new_code = simplify_comparison (code, &op0, &op1);
4460 /* If STORE_FLAG_VALUE is 1, we can convert (ne x 0) to simply X
4461 if only the low-order bit is possibly nonzero in X (such as when
4462 X is a ZERO_EXTRACT of one bit). Similarly, we can convert EQ to
4463 (xor X 1) or (minus 1 X); we use the former. Finally, if X is
4464 known to be either 0 or -1, NE becomes a NEG and EQ becomes
4467 Remove any ZERO_EXTRACT we made when thinking this was a
4468 comparison. It may now be simpler to use, e.g., an AND. If a
4469 ZERO_EXTRACT is indeed appropriate, it will be placed back by
4470 the call to make_compound_operation in the SET case. */
4472 if (STORE_FLAG_VALUE == 1
4473 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4474 && op1 == const0_rtx
4475 && mode == GET_MODE (op0)
4476 && nonzero_bits (op0, mode) == 1)
4477 return gen_lowpart (mode,
4478 expand_compound_operation (op0));
4480 else if (STORE_FLAG_VALUE == 1
4481 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4482 && op1 == const0_rtx
4483 && mode == GET_MODE (op0)
4484 && (num_sign_bit_copies (op0, mode)
4485 == GET_MODE_BITSIZE (mode)))
4487 op0 = expand_compound_operation (op0);
4488 return simplify_gen_unary (NEG, mode,
4489 gen_lowpart (mode, op0),
4493 else if (STORE_FLAG_VALUE == 1
4494 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
4495 && op1 == const0_rtx
4496 && mode == GET_MODE (op0)
4497 && nonzero_bits (op0, mode) == 1)
4499 op0 = expand_compound_operation (op0);
4500 return simplify_gen_binary (XOR, mode,
4501 gen_lowpart (mode, op0),
4505 else if (STORE_FLAG_VALUE == 1
4506 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
4507 && op1 == const0_rtx
4508 && mode == GET_MODE (op0)
4509 && (num_sign_bit_copies (op0, mode)
4510 == GET_MODE_BITSIZE (mode)))
4512 op0 = expand_compound_operation (op0);
4513 return plus_constant (gen_lowpart (mode, op0), 1);
4516 /* If STORE_FLAG_VALUE is -1, we have cases similar to
4518 if (STORE_FLAG_VALUE == -1
4519 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4520 && op1 == const0_rtx
4521 && (num_sign_bit_copies (op0, mode)
4522 == GET_MODE_BITSIZE (mode)))
4523 return gen_lowpart (mode,
4524 expand_compound_operation (op0));
4526 else if (STORE_FLAG_VALUE == -1
4527 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4528 && op1 == const0_rtx
4529 && mode == GET_MODE (op0)
4530 && nonzero_bits (op0, mode) == 1)
4532 op0 = expand_compound_operation (op0);
4533 return simplify_gen_unary (NEG, mode,
4534 gen_lowpart (mode, op0),
4538 else if (STORE_FLAG_VALUE == -1
4539 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
4540 && op1 == const0_rtx
4541 && mode == GET_MODE (op0)
4542 && (num_sign_bit_copies (op0, mode)
4543 == GET_MODE_BITSIZE (mode)))
4545 op0 = expand_compound_operation (op0);
4546 return simplify_gen_unary (NOT, mode,
4547 gen_lowpart (mode, op0),
4551 /* If X is 0/1, (eq X 0) is X-1. */
4552 else if (STORE_FLAG_VALUE == -1
4553 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
4554 && op1 == const0_rtx
4555 && mode == GET_MODE (op0)
4556 && nonzero_bits (op0, mode) == 1)
4558 op0 = expand_compound_operation (op0);
4559 return plus_constant (gen_lowpart (mode, op0), -1);
4562 /* If STORE_FLAG_VALUE says to just test the sign bit and X has just
4563 one bit that might be nonzero, we can convert (ne x 0) to
4564 (ashift x c) where C puts the bit in the sign bit. Remove any
4565 AND with STORE_FLAG_VALUE when we are done, since we are only
4566 going to test the sign bit. */
4567 if (new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4568 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4569 && ((STORE_FLAG_VALUE & GET_MODE_MASK (mode))
4570 == (unsigned HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (mode) - 1))
4571 && op1 == const0_rtx
4572 && mode == GET_MODE (op0)
4573 && (i = exact_log2 (nonzero_bits (op0, mode))) >= 0)
4575 x = simplify_shift_const (NULL_RTX, ASHIFT, mode,
4576 expand_compound_operation (op0),
4577 GET_MODE_BITSIZE (mode) - 1 - i);
4578 if (GET_CODE (x) == AND && XEXP (x, 1) == const_true_rtx)
4584 /* If the code changed, return a whole new comparison. */
4585 if (new_code != code)
4586 return gen_rtx_fmt_ee (new_code, mode, op0, op1);
4588 /* Otherwise, keep this operation, but maybe change its operands.
4589 This also converts (ne (compare FOO BAR) 0) to (ne FOO BAR). */
4590 SUBST (XEXP (x, 0), op0);
4591 SUBST (XEXP (x, 1), op1);
4596 return simplify_if_then_else (x);
4602 /* If we are processing SET_DEST, we are done. */
4606 return expand_compound_operation (x);
4609 return simplify_set (x);
4613 return simplify_logical (x);
4620 /* If this is a shift by a constant amount, simplify it. */
4621 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
4622 return simplify_shift_const (x, code, mode, XEXP (x, 0),
4623 INTVAL (XEXP (x, 1)));
4625 else if (SHIFT_COUNT_TRUNCATED && !REG_P (XEXP (x, 1)))
4627 force_to_mode (XEXP (x, 1), GET_MODE (XEXP (x, 1)),
4629 << exact_log2 (GET_MODE_BITSIZE (GET_MODE (x))))
4641 /* Simplify X, an IF_THEN_ELSE expression. Return the new expression. */
4644 simplify_if_then_else (rtx x)
4646 enum machine_mode mode = GET_MODE (x);
4647 rtx cond = XEXP (x, 0);
4648 rtx true_rtx = XEXP (x, 1);
4649 rtx false_rtx = XEXP (x, 2);
4650 enum rtx_code true_code = GET_CODE (cond);
4651 int comparison_p = COMPARISON_P (cond);
4654 enum rtx_code false_code;
4657 /* Simplify storing of the truth value. */
4658 if (comparison_p && true_rtx == const_true_rtx && false_rtx == const0_rtx)
4659 return simplify_gen_relational (true_code, mode, VOIDmode,
4660 XEXP (cond, 0), XEXP (cond, 1));
4662 /* Also when the truth value has to be reversed. */
4664 && true_rtx == const0_rtx && false_rtx == const_true_rtx
4665 && (reversed = reversed_comparison (cond, mode)))
4668 /* Sometimes we can simplify the arm of an IF_THEN_ELSE if a register used
4669 in it is being compared against certain values. Get the true and false
4670 comparisons and see if that says anything about the value of each arm. */
4673 && ((false_code = reversed_comparison_code (cond, NULL))
4675 && REG_P (XEXP (cond, 0)))
4678 rtx from = XEXP (cond, 0);
4679 rtx true_val = XEXP (cond, 1);
4680 rtx false_val = true_val;
4683 /* If FALSE_CODE is EQ, swap the codes and arms. */
4685 if (false_code == EQ)
4687 swapped = 1, true_code = EQ, false_code = NE;
4688 temp = true_rtx, true_rtx = false_rtx, false_rtx = temp;
4691 /* If we are comparing against zero and the expression being tested has
4692 only a single bit that might be nonzero, that is its value when it is
4693 not equal to zero. Similarly if it is known to be -1 or 0. */
4695 if (true_code == EQ && true_val == const0_rtx
4696 && exact_log2 (nzb = nonzero_bits (from, GET_MODE (from))) >= 0)
4697 false_code = EQ, false_val = GEN_INT (nzb);
4698 else if (true_code == EQ && true_val == const0_rtx
4699 && (num_sign_bit_copies (from, GET_MODE (from))
4700 == GET_MODE_BITSIZE (GET_MODE (from))))
4701 false_code = EQ, false_val = constm1_rtx;
4703 /* Now simplify an arm if we know the value of the register in the
4704 branch and it is used in the arm. Be careful due to the potential
4705 of locally-shared RTL. */
4707 if (reg_mentioned_p (from, true_rtx))
4708 true_rtx = subst (known_cond (copy_rtx (true_rtx), true_code,
4710 pc_rtx, pc_rtx, 0, 0);
4711 if (reg_mentioned_p (from, false_rtx))
4712 false_rtx = subst (known_cond (copy_rtx (false_rtx), false_code,
4714 pc_rtx, pc_rtx, 0, 0);
4716 SUBST (XEXP (x, 1), swapped ? false_rtx : true_rtx);
4717 SUBST (XEXP (x, 2), swapped ? true_rtx : false_rtx);
4719 true_rtx = XEXP (x, 1);
4720 false_rtx = XEXP (x, 2);
4721 true_code = GET_CODE (cond);
4724 /* If we have (if_then_else FOO (pc) (label_ref BAR)) and FOO can be
4725 reversed, do so to avoid needing two sets of patterns for
4726 subtract-and-branch insns. Similarly if we have a constant in the true
4727 arm, the false arm is the same as the first operand of the comparison, or
4728 the false arm is more complicated than the true arm. */
4731 && reversed_comparison_code (cond, NULL) != UNKNOWN
4732 && (true_rtx == pc_rtx
4733 || (CONSTANT_P (true_rtx)
4734 && GET_CODE (false_rtx) != CONST_INT && false_rtx != pc_rtx)
4735 || true_rtx == const0_rtx
4736 || (OBJECT_P (true_rtx) && !OBJECT_P (false_rtx))
4737 || (GET_CODE (true_rtx) == SUBREG && OBJECT_P (SUBREG_REG (true_rtx))
4738 && !OBJECT_P (false_rtx))
4739 || reg_mentioned_p (true_rtx, false_rtx)
4740 || rtx_equal_p (false_rtx, XEXP (cond, 0))))
4742 true_code = reversed_comparison_code (cond, NULL);
4743 SUBST (XEXP (x, 0), reversed_comparison (cond, GET_MODE (cond)));
4744 SUBST (XEXP (x, 1), false_rtx);
4745 SUBST (XEXP (x, 2), true_rtx);
4747 temp = true_rtx, true_rtx = false_rtx, false_rtx = temp;
4750 /* It is possible that the conditional has been simplified out. */
4751 true_code = GET_CODE (cond);
4752 comparison_p = COMPARISON_P (cond);
4755 /* If the two arms are identical, we don't need the comparison. */
4757 if (rtx_equal_p (true_rtx, false_rtx) && ! side_effects_p (cond))
4760 /* Convert a == b ? b : a to "a". */
4761 if (true_code == EQ && ! side_effects_p (cond)
4762 && !HONOR_NANS (mode)
4763 && rtx_equal_p (XEXP (cond, 0), false_rtx)
4764 && rtx_equal_p (XEXP (cond, 1), true_rtx))
4766 else if (true_code == NE && ! side_effects_p (cond)
4767 && !HONOR_NANS (mode)
4768 && rtx_equal_p (XEXP (cond, 0), true_rtx)
4769 && rtx_equal_p (XEXP (cond, 1), false_rtx))
4772 /* Look for cases where we have (abs x) or (neg (abs X)). */
4774 if (GET_MODE_CLASS (mode) == MODE_INT
4775 && GET_CODE (false_rtx) == NEG
4776 && rtx_equal_p (true_rtx, XEXP (false_rtx, 0))
4778 && rtx_equal_p (true_rtx, XEXP (cond, 0))
4779 && ! side_effects_p (true_rtx))
4784 return simplify_gen_unary (ABS, mode, true_rtx, mode);
4788 simplify_gen_unary (NEG, mode,
4789 simplify_gen_unary (ABS, mode, true_rtx, mode),
4795 /* Look for MIN or MAX. */
4797 if ((! FLOAT_MODE_P (mode) || flag_unsafe_math_optimizations)
4799 && rtx_equal_p (XEXP (cond, 0), true_rtx)
4800 && rtx_equal_p (XEXP (cond, 1), false_rtx)
4801 && ! side_effects_p (cond))
4806 return simplify_gen_binary (SMAX, mode, true_rtx, false_rtx);
4809 return simplify_gen_binary (SMIN, mode, true_rtx, false_rtx);
4812 return simplify_gen_binary (UMAX, mode, true_rtx, false_rtx);
4815 return simplify_gen_binary (UMIN, mode, true_rtx, false_rtx);
4820 /* If we have (if_then_else COND (OP Z C1) Z) and OP is an identity when its
4821 second operand is zero, this can be done as (OP Z (mult COND C2)) where
4822 C2 = C1 * STORE_FLAG_VALUE. Similarly if OP has an outer ZERO_EXTEND or
4823 SIGN_EXTEND as long as Z is already extended (so we don't destroy it).
4824 We can do this kind of thing in some cases when STORE_FLAG_VALUE is
4825 neither 1 or -1, but it isn't worth checking for. */
4827 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
4829 && GET_MODE_CLASS (mode) == MODE_INT
4830 && ! side_effects_p (x))
4832 rtx t = make_compound_operation (true_rtx, SET);
4833 rtx f = make_compound_operation (false_rtx, SET);
4834 rtx cond_op0 = XEXP (cond, 0);
4835 rtx cond_op1 = XEXP (cond, 1);
4836 enum rtx_code op = UNKNOWN, extend_op = UNKNOWN;
4837 enum machine_mode m = mode;
4838 rtx z = 0, c1 = NULL_RTX;
4840 if ((GET_CODE (t) == PLUS || GET_CODE (t) == MINUS
4841 || GET_CODE (t) == IOR || GET_CODE (t) == XOR
4842 || GET_CODE (t) == ASHIFT
4843 || GET_CODE (t) == LSHIFTRT || GET_CODE (t) == ASHIFTRT)
4844 && rtx_equal_p (XEXP (t, 0), f))
4845 c1 = XEXP (t, 1), op = GET_CODE (t), z = f;
4847 /* If an identity-zero op is commutative, check whether there
4848 would be a match if we swapped the operands. */
4849 else if ((GET_CODE (t) == PLUS || GET_CODE (t) == IOR
4850 || GET_CODE (t) == XOR)
4851 && rtx_equal_p (XEXP (t, 1), f))
4852 c1 = XEXP (t, 0), op = GET_CODE (t), z = f;
4853 else if (GET_CODE (t) == SIGN_EXTEND
4854 && (GET_CODE (XEXP (t, 0)) == PLUS
4855 || GET_CODE (XEXP (t, 0)) == MINUS
4856 || GET_CODE (XEXP (t, 0)) == IOR
4857 || GET_CODE (XEXP (t, 0)) == XOR
4858 || GET_CODE (XEXP (t, 0)) == ASHIFT
4859 || GET_CODE (XEXP (t, 0)) == LSHIFTRT
4860 || GET_CODE (XEXP (t, 0)) == ASHIFTRT)
4861 && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG
4862 && subreg_lowpart_p (XEXP (XEXP (t, 0), 0))
4863 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f)
4864 && (num_sign_bit_copies (f, GET_MODE (f))
4866 (GET_MODE_BITSIZE (mode)
4867 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t, 0), 0))))))
4869 c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0));
4870 extend_op = SIGN_EXTEND;
4871 m = GET_MODE (XEXP (t, 0));
4873 else if (GET_CODE (t) == SIGN_EXTEND
4874 && (GET_CODE (XEXP (t, 0)) == PLUS
4875 || GET_CODE (XEXP (t, 0)) == IOR
4876 || GET_CODE (XEXP (t, 0)) == XOR)
4877 && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG
4878 && subreg_lowpart_p (XEXP (XEXP (t, 0), 1))
4879 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f)
4880 && (num_sign_bit_copies (f, GET_MODE (f))
4882 (GET_MODE_BITSIZE (mode)
4883 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t, 0), 1))))))
4885 c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0));
4886 extend_op = SIGN_EXTEND;
4887 m = GET_MODE (XEXP (t, 0));
4889 else if (GET_CODE (t) == ZERO_EXTEND
4890 && (GET_CODE (XEXP (t, 0)) == PLUS
4891 || GET_CODE (XEXP (t, 0)) == MINUS
4892 || GET_CODE (XEXP (t, 0)) == IOR
4893 || GET_CODE (XEXP (t, 0)) == XOR
4894 || GET_CODE (XEXP (t, 0)) == ASHIFT
4895 || GET_CODE (XEXP (t, 0)) == LSHIFTRT
4896 || GET_CODE (XEXP (t, 0)) == ASHIFTRT)
4897 && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG
4898 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4899 && subreg_lowpart_p (XEXP (XEXP (t, 0), 0))
4900 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f)
4901 && ((nonzero_bits (f, GET_MODE (f))
4902 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t, 0), 0))))
4905 c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0));
4906 extend_op = ZERO_EXTEND;
4907 m = GET_MODE (XEXP (t, 0));
4909 else if (GET_CODE (t) == ZERO_EXTEND
4910 && (GET_CODE (XEXP (t, 0)) == PLUS
4911 || GET_CODE (XEXP (t, 0)) == IOR
4912 || GET_CODE (XEXP (t, 0)) == XOR)
4913 && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG
4914 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4915 && subreg_lowpart_p (XEXP (XEXP (t, 0), 1))
4916 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f)
4917 && ((nonzero_bits (f, GET_MODE (f))
4918 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t, 0), 1))))
4921 c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0));
4922 extend_op = ZERO_EXTEND;
4923 m = GET_MODE (XEXP (t, 0));
4928 temp = subst (simplify_gen_relational (true_code, m, VOIDmode,
4929 cond_op0, cond_op1),
4930 pc_rtx, pc_rtx, 0, 0);
4931 temp = simplify_gen_binary (MULT, m, temp,
4932 simplify_gen_binary (MULT, m, c1,
4934 temp = subst (temp, pc_rtx, pc_rtx, 0, 0);
4935 temp = simplify_gen_binary (op, m, gen_lowpart (m, z), temp);
4937 if (extend_op != UNKNOWN)
4938 temp = simplify_gen_unary (extend_op, mode, temp, m);
4944 /* If we have (if_then_else (ne A 0) C1 0) and either A is known to be 0 or
4945 1 and C1 is a single bit or A is known to be 0 or -1 and C1 is the
4946 negation of a single bit, we can convert this operation to a shift. We
4947 can actually do this more generally, but it doesn't seem worth it. */
4949 if (true_code == NE && XEXP (cond, 1) == const0_rtx
4950 && false_rtx == const0_rtx && GET_CODE (true_rtx) == CONST_INT
4951 && ((1 == nonzero_bits (XEXP (cond, 0), mode)
4952 && (i = exact_log2 (INTVAL (true_rtx))) >= 0)
4953 || ((num_sign_bit_copies (XEXP (cond, 0), mode)
4954 == GET_MODE_BITSIZE (mode))
4955 && (i = exact_log2 (-INTVAL (true_rtx))) >= 0)))
4957 simplify_shift_const (NULL_RTX, ASHIFT, mode,
4958 gen_lowpart (mode, XEXP (cond, 0)), i);
4960 /* (IF_THEN_ELSE (NE REG 0) (0) (8)) is REG for nonzero_bits (REG) == 8. */
4961 if (true_code == NE && XEXP (cond, 1) == const0_rtx
4962 && false_rtx == const0_rtx && GET_CODE (true_rtx) == CONST_INT
4963 && GET_MODE (XEXP (cond, 0)) == mode
4964 && (INTVAL (true_rtx) & GET_MODE_MASK (mode))
4965 == nonzero_bits (XEXP (cond, 0), mode)
4966 && (i = exact_log2 (INTVAL (true_rtx) & GET_MODE_MASK (mode))) >= 0)
4967 return XEXP (cond, 0);
4972 /* Simplify X, a SET expression. Return the new expression. */
4975 simplify_set (rtx x)
4977 rtx src = SET_SRC (x);
4978 rtx dest = SET_DEST (x);
4979 enum machine_mode mode
4980 = GET_MODE (src) != VOIDmode ? GET_MODE (src) : GET_MODE (dest);
4984 /* (set (pc) (return)) gets written as (return). */
4985 if (GET_CODE (dest) == PC && GET_CODE (src) == RETURN)
4988 /* Now that we know for sure which bits of SRC we are using, see if we can
4989 simplify the expression for the object knowing that we only need the
4992 if (GET_MODE_CLASS (mode) == MODE_INT
4993 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
4995 src = force_to_mode (src, mode, ~(HOST_WIDE_INT) 0, 0);
4996 SUBST (SET_SRC (x), src);
4999 /* If we are setting CC0 or if the source is a COMPARE, look for the use of
5000 the comparison result and try to simplify it unless we already have used
5001 undobuf.other_insn. */
5002 if ((GET_MODE_CLASS (mode) == MODE_CC
5003 || GET_CODE (src) == COMPARE
5005 && (cc_use = find_single_use (dest, subst_insn, &other_insn)) != 0
5006 && (undobuf.other_insn == 0 || other_insn == undobuf.other_insn)
5007 && COMPARISON_P (*cc_use)
5008 && rtx_equal_p (XEXP (*cc_use, 0), dest))
5010 enum rtx_code old_code = GET_CODE (*cc_use);
5011 enum rtx_code new_code;
5013 int other_changed = 0;
5014 enum machine_mode compare_mode = GET_MODE (dest);
5016 if (GET_CODE (src) == COMPARE)
5017 op0 = XEXP (src, 0), op1 = XEXP (src, 1);
5019 op0 = src, op1 = CONST0_RTX (GET_MODE (src));
5021 tmp = simplify_relational_operation (old_code, compare_mode, VOIDmode,
5024 new_code = old_code;
5025 else if (!CONSTANT_P (tmp))
5027 new_code = GET_CODE (tmp);
5028 op0 = XEXP (tmp, 0);
5029 op1 = XEXP (tmp, 1);
5033 rtx pat = PATTERN (other_insn);
5034 undobuf.other_insn = other_insn;
5035 SUBST (*cc_use, tmp);
5037 /* Attempt to simplify CC user. */
5038 if (GET_CODE (pat) == SET)
5040 rtx new = simplify_rtx (SET_SRC (pat));
5041 if (new != NULL_RTX)
5042 SUBST (SET_SRC (pat), new);
5045 /* Convert X into a no-op move. */
5046 SUBST (SET_DEST (x), pc_rtx);
5047 SUBST (SET_SRC (x), pc_rtx);
5051 /* Simplify our comparison, if possible. */
5052 new_code = simplify_comparison (new_code, &op0, &op1);
5054 #ifdef SELECT_CC_MODE
5055 /* If this machine has CC modes other than CCmode, check to see if we
5056 need to use a different CC mode here. */
5057 if (GET_MODE_CLASS (GET_MODE (op0)) == MODE_CC)
5058 compare_mode = GET_MODE (op0);
5060 compare_mode = SELECT_CC_MODE (new_code, op0, op1);
5063 /* If the mode changed, we have to change SET_DEST, the mode in the
5064 compare, and the mode in the place SET_DEST is used. If SET_DEST is
5065 a hard register, just build new versions with the proper mode. If it
5066 is a pseudo, we lose unless it is only time we set the pseudo, in
5067 which case we can safely change its mode. */
5068 if (compare_mode != GET_MODE (dest))
5070 if (can_change_dest_mode (dest, 0, compare_mode))
5072 unsigned int regno = REGNO (dest);
5073 rtx new_dest = gen_rtx_REG (compare_mode, regno);
5075 if (regno >= FIRST_PSEUDO_REGISTER)
5076 SUBST (regno_reg_rtx[regno], new_dest);
5078 SUBST (SET_DEST (x), new_dest);
5079 SUBST (XEXP (*cc_use, 0), new_dest);
5086 #endif /* SELECT_CC_MODE */
5088 /* If the code changed, we have to build a new comparison in
5089 undobuf.other_insn. */
5090 if (new_code != old_code)
5092 int other_changed_previously = other_changed;
5093 unsigned HOST_WIDE_INT mask;
5095 SUBST (*cc_use, gen_rtx_fmt_ee (new_code, GET_MODE (*cc_use),
5099 /* If the only change we made was to change an EQ into an NE or
5100 vice versa, OP0 has only one bit that might be nonzero, and OP1
5101 is zero, check if changing the user of the condition code will
5102 produce a valid insn. If it won't, we can keep the original code
5103 in that insn by surrounding our operation with an XOR. */
5105 if (((old_code == NE && new_code == EQ)
5106 || (old_code == EQ && new_code == NE))
5107 && ! other_changed_previously && op1 == const0_rtx
5108 && GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
5109 && exact_log2 (mask = nonzero_bits (op0, GET_MODE (op0))) >= 0)
5111 rtx pat = PATTERN (other_insn), note = 0;
5113 if ((recog_for_combine (&pat, other_insn, ¬e) < 0
5114 && ! check_asm_operands (pat)))
5116 PUT_CODE (*cc_use, old_code);
5119 op0 = simplify_gen_binary (XOR, GET_MODE (op0),
5120 op0, GEN_INT (mask));
5126 undobuf.other_insn = other_insn;
5129 /* If we are now comparing against zero, change our source if
5130 needed. If we do not use cc0, we always have a COMPARE. */
5131 if (op1 == const0_rtx && dest == cc0_rtx)
5133 SUBST (SET_SRC (x), op0);
5139 /* Otherwise, if we didn't previously have a COMPARE in the
5140 correct mode, we need one. */
5141 if (GET_CODE (src) != COMPARE || GET_MODE (src) != compare_mode)
5143 SUBST (SET_SRC (x), gen_rtx_COMPARE (compare_mode, op0, op1));
5146 else if (GET_MODE (op0) == compare_mode && op1 == const0_rtx)
5148 SUBST(SET_SRC (x), op0);
5153 /* Otherwise, update the COMPARE if needed. */
5154 SUBST (XEXP (src, 0), op0);
5155 SUBST (XEXP (src, 1), op1);
5160 /* Get SET_SRC in a form where we have placed back any
5161 compound expressions. Then do the checks below. */
5162 src = make_compound_operation (src, SET);
5163 SUBST (SET_SRC (x), src);
5166 /* If we have (set x (subreg:m1 (op:m2 ...) 0)) with OP being some operation,
5167 and X being a REG or (subreg (reg)), we may be able to convert this to
5168 (set (subreg:m2 x) (op)).
5170 We can always do this if M1 is narrower than M2 because that means that
5171 we only care about the low bits of the result.
5173 However, on machines without WORD_REGISTER_OPERATIONS defined, we cannot
5174 perform a narrower operation than requested since the high-order bits will
5175 be undefined. On machine where it is defined, this transformation is safe
5176 as long as M1 and M2 have the same number of words. */
5178 if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src)
5179 && !OBJECT_P (SUBREG_REG (src))
5180 && (((GET_MODE_SIZE (GET_MODE (src)) + (UNITS_PER_WORD - 1))
5182 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (src)))
5183 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD))
5184 #ifndef WORD_REGISTER_OPERATIONS
5185 && (GET_MODE_SIZE (GET_MODE (src))
5186 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (src))))
5188 #ifdef CANNOT_CHANGE_MODE_CLASS
5189 && ! (REG_P (dest) && REGNO (dest) < FIRST_PSEUDO_REGISTER
5190 && REG_CANNOT_CHANGE_MODE_P (REGNO (dest),
5191 GET_MODE (SUBREG_REG (src)),
5195 || (GET_CODE (dest) == SUBREG
5196 && REG_P (SUBREG_REG (dest)))))
5198 SUBST (SET_DEST (x),
5199 gen_lowpart (GET_MODE (SUBREG_REG (src)),
5201 SUBST (SET_SRC (x), SUBREG_REG (src));
5203 src = SET_SRC (x), dest = SET_DEST (x);
5207 /* If we have (set (cc0) (subreg ...)), we try to remove the subreg
5210 && GET_CODE (src) == SUBREG
5211 && subreg_lowpart_p (src)
5212 && (GET_MODE_BITSIZE (GET_MODE (src))
5213 < GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (src)))))
5215 rtx inner = SUBREG_REG (src);
5216 enum machine_mode inner_mode = GET_MODE (inner);
5218 /* Here we make sure that we don't have a sign bit on. */
5219 if (GET_MODE_BITSIZE (inner_mode) <= HOST_BITS_PER_WIDE_INT
5220 && (nonzero_bits (inner, inner_mode)
5221 < ((unsigned HOST_WIDE_INT) 1
5222 << (GET_MODE_BITSIZE (GET_MODE (src)) - 1))))
5224 SUBST (SET_SRC (x), inner);
5230 #ifdef LOAD_EXTEND_OP
5231 /* If we have (set FOO (subreg:M (mem:N BAR) 0)) with M wider than N, this
5232 would require a paradoxical subreg. Replace the subreg with a
5233 zero_extend to avoid the reload that would otherwise be required. */
5235 if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src)
5236 && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src))) != UNKNOWN
5237 && SUBREG_BYTE (src) == 0
5238 && (GET_MODE_SIZE (GET_MODE (src))
5239 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (src))))
5240 && MEM_P (SUBREG_REG (src)))
5243 gen_rtx_fmt_e (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src))),
5244 GET_MODE (src), SUBREG_REG (src)));
5250 /* If we don't have a conditional move, SET_SRC is an IF_THEN_ELSE, and we
5251 are comparing an item known to be 0 or -1 against 0, use a logical
5252 operation instead. Check for one of the arms being an IOR of the other
5253 arm with some value. We compute three terms to be IOR'ed together. In
5254 practice, at most two will be nonzero. Then we do the IOR's. */
5256 if (GET_CODE (dest) != PC
5257 && GET_CODE (src) == IF_THEN_ELSE
5258 && GET_MODE_CLASS (GET_MODE (src)) == MODE_INT
5259 && (GET_CODE (XEXP (src, 0)) == EQ || GET_CODE (XEXP (src, 0)) == NE)
5260 && XEXP (XEXP (src, 0), 1) == const0_rtx
5261 && GET_MODE (src) == GET_MODE (XEXP (XEXP (src, 0), 0))
5262 #ifdef HAVE_conditional_move
5263 && ! can_conditionally_move_p (GET_MODE (src))
5265 && (num_sign_bit_copies (XEXP (XEXP (src, 0), 0),
5266 GET_MODE (XEXP (XEXP (src, 0), 0)))
5267 == GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (src, 0), 0))))
5268 && ! side_effects_p (src))
5270 rtx true_rtx = (GET_CODE (XEXP (src, 0)) == NE
5271 ? XEXP (src, 1) : XEXP (src, 2));
5272 rtx false_rtx = (GET_CODE (XEXP (src, 0)) == NE
5273 ? XEXP (src, 2) : XEXP (src, 1));
5274 rtx term1 = const0_rtx, term2, term3;
5276 if (GET_CODE (true_rtx) == IOR
5277 && rtx_equal_p (XEXP (true_rtx, 0), false_rtx))
5278 term1 = false_rtx, true_rtx = XEXP (true_rtx, 1), false_rtx = const0_rtx;
5279 else if (GET_CODE (true_rtx) == IOR
5280 && rtx_equal_p (XEXP (true_rtx, 1), false_rtx))
5281 term1 = false_rtx, true_rtx = XEXP (true_rtx, 0), false_rtx = const0_rtx;
5282 else if (GET_CODE (false_rtx) == IOR
5283 && rtx_equal_p (XEXP (false_rtx, 0), true_rtx))
5284 term1 = true_rtx, false_rtx = XEXP (false_rtx, 1), true_rtx = const0_rtx;
5285 else if (GET_CODE (false_rtx) == IOR
5286 && rtx_equal_p (XEXP (false_rtx, 1), true_rtx))
5287 term1 = true_rtx, false_rtx = XEXP (false_rtx, 0), true_rtx = const0_rtx;
5289 term2 = simplify_gen_binary (AND, GET_MODE (src),
5290 XEXP (XEXP (src, 0), 0), true_rtx);
5291 term3 = simplify_gen_binary (AND, GET_MODE (src),
5292 simplify_gen_unary (NOT, GET_MODE (src),
5293 XEXP (XEXP (src, 0), 0),
5298 simplify_gen_binary (IOR, GET_MODE (src),
5299 simplify_gen_binary (IOR, GET_MODE (src),
5306 /* If either SRC or DEST is a CLOBBER of (const_int 0), make this
5307 whole thing fail. */
5308 if (GET_CODE (src) == CLOBBER && XEXP (src, 0) == const0_rtx)
5310 else if (GET_CODE (dest) == CLOBBER && XEXP (dest, 0) == const0_rtx)
5313 /* Convert this into a field assignment operation, if possible. */
5314 return make_field_assignment (x);
5317 /* Simplify, X, and AND, IOR, or XOR operation, and return the simplified
5321 simplify_logical (rtx x)
5323 enum machine_mode mode = GET_MODE (x);
5324 rtx op0 = XEXP (x, 0);
5325 rtx op1 = XEXP (x, 1);
5327 switch (GET_CODE (x))
5330 /* We can call simplify_and_const_int only if we don't lose
5331 any (sign) bits when converting INTVAL (op1) to
5332 "unsigned HOST_WIDE_INT". */
5333 if (GET_CODE (op1) == CONST_INT
5334 && (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5335 || INTVAL (op1) > 0))
5337 x = simplify_and_const_int (x, mode, op0, INTVAL (op1));
5338 if (GET_CODE (x) != AND)
5345 /* If we have any of (and (ior A B) C) or (and (xor A B) C),
5346 apply the distributive law and then the inverse distributive
5347 law to see if things simplify. */
5348 if (GET_CODE (op0) == IOR || GET_CODE (op0) == XOR)
5350 rtx result = distribute_and_simplify_rtx (x, 0);
5354 if (GET_CODE (op1) == IOR || GET_CODE (op1) == XOR)
5356 rtx result = distribute_and_simplify_rtx (x, 1);
5363 /* If we have (ior (and A B) C), apply the distributive law and then
5364 the inverse distributive law to see if things simplify. */
5366 if (GET_CODE (op0) == AND)
5368 rtx result = distribute_and_simplify_rtx (x, 0);
5373 if (GET_CODE (op1) == AND)
5375 rtx result = distribute_and_simplify_rtx (x, 1);
5388 /* We consider ZERO_EXTRACT, SIGN_EXTRACT, and SIGN_EXTEND as "compound
5389 operations" because they can be replaced with two more basic operations.
5390 ZERO_EXTEND is also considered "compound" because it can be replaced with
5391 an AND operation, which is simpler, though only one operation.
5393 The function expand_compound_operation is called with an rtx expression
5394 and will convert it to the appropriate shifts and AND operations,
5395 simplifying at each stage.
5397 The function make_compound_operation is called to convert an expression
5398 consisting of shifts and ANDs into the equivalent compound expression.
5399 It is the inverse of this function, loosely speaking. */
5402 expand_compound_operation (rtx x)
5404 unsigned HOST_WIDE_INT pos = 0, len;
5406 unsigned int modewidth;
5409 switch (GET_CODE (x))
5414 /* We can't necessarily use a const_int for a multiword mode;
5415 it depends on implicitly extending the value.
5416 Since we don't know the right way to extend it,
5417 we can't tell whether the implicit way is right.
5419 Even for a mode that is no wider than a const_int,
5420 we can't win, because we need to sign extend one of its bits through
5421 the rest of it, and we don't know which bit. */
5422 if (GET_CODE (XEXP (x, 0)) == CONST_INT)
5425 /* Return if (subreg:MODE FROM 0) is not a safe replacement for
5426 (zero_extend:MODE FROM) or (sign_extend:MODE FROM). It is for any MEM
5427 because (SUBREG (MEM...)) is guaranteed to cause the MEM to be
5428 reloaded. If not for that, MEM's would very rarely be safe.
5430 Reject MODEs bigger than a word, because we might not be able
5431 to reference a two-register group starting with an arbitrary register
5432 (and currently gen_lowpart might crash for a SUBREG). */
5434 if (GET_MODE_SIZE (GET_MODE (XEXP (x, 0))) > UNITS_PER_WORD)
5437 /* Reject MODEs that aren't scalar integers because turning vector
5438 or complex modes into shifts causes problems. */
5440 if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x, 0))))
5443 len = GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)));
5444 /* If the inner object has VOIDmode (the only way this can happen
5445 is if it is an ASM_OPERANDS), we can't do anything since we don't
5446 know how much masking to do. */
5455 /* ... fall through ... */
5458 /* If the operand is a CLOBBER, just return it. */
5459 if (GET_CODE (XEXP (x, 0)) == CLOBBER)
5462 if (GET_CODE (XEXP (x, 1)) != CONST_INT
5463 || GET_CODE (XEXP (x, 2)) != CONST_INT
5464 || GET_MODE (XEXP (x, 0)) == VOIDmode)
5467 /* Reject MODEs that aren't scalar integers because turning vector
5468 or complex modes into shifts causes problems. */
5470 if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x, 0))))
5473 len = INTVAL (XEXP (x, 1));
5474 pos = INTVAL (XEXP (x, 2));
5476 /* If this goes outside the object being extracted, replace the object
5477 with a (use (mem ...)) construct that only combine understands
5478 and is used only for this purpose. */
5479 if (len + pos > GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))))
5480 SUBST (XEXP (x, 0), gen_rtx_USE (GET_MODE (x), XEXP (x, 0)));
5482 if (BITS_BIG_ENDIAN)
5483 pos = GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - len - pos;
5490 /* Convert sign extension to zero extension, if we know that the high
5491 bit is not set, as this is easier to optimize. It will be converted
5492 back to cheaper alternative in make_extraction. */
5493 if (GET_CODE (x) == SIGN_EXTEND
5494 && (GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
5495 && ((nonzero_bits (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
5496 & ~(((unsigned HOST_WIDE_INT)
5497 GET_MODE_MASK (GET_MODE (XEXP (x, 0))))
5501 rtx temp = gen_rtx_ZERO_EXTEND (GET_MODE (x), XEXP (x, 0));
5502 rtx temp2 = expand_compound_operation (temp);
5504 /* Make sure this is a profitable operation. */
5505 if (rtx_cost (x, SET) > rtx_cost (temp2, SET))
5507 else if (rtx_cost (x, SET) > rtx_cost (temp, SET))
5513 /* We can optimize some special cases of ZERO_EXTEND. */
5514 if (GET_CODE (x) == ZERO_EXTEND)
5516 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI if we
5517 know that the last value didn't have any inappropriate bits
5519 if (GET_CODE (XEXP (x, 0)) == TRUNCATE
5520 && GET_MODE (XEXP (XEXP (x, 0), 0)) == GET_MODE (x)
5521 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
5522 && (nonzero_bits (XEXP (XEXP (x, 0), 0), GET_MODE (x))
5523 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5524 return XEXP (XEXP (x, 0), 0);
5526 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
5527 if (GET_CODE (XEXP (x, 0)) == SUBREG
5528 && GET_MODE (SUBREG_REG (XEXP (x, 0))) == GET_MODE (x)
5529 && subreg_lowpart_p (XEXP (x, 0))
5530 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
5531 && (nonzero_bits (SUBREG_REG (XEXP (x, 0)), GET_MODE (x))
5532 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5533 return SUBREG_REG (XEXP (x, 0));
5535 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI when foo
5536 is a comparison and STORE_FLAG_VALUE permits. This is like
5537 the first case, but it works even when GET_MODE (x) is larger
5538 than HOST_WIDE_INT. */
5539 if (GET_CODE (XEXP (x, 0)) == TRUNCATE
5540 && GET_MODE (XEXP (XEXP (x, 0), 0)) == GET_MODE (x)
5541 && COMPARISON_P (XEXP (XEXP (x, 0), 0))
5542 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
5543 <= HOST_BITS_PER_WIDE_INT)
5544 && ((HOST_WIDE_INT) STORE_FLAG_VALUE
5545 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5546 return XEXP (XEXP (x, 0), 0);
5548 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
5549 if (GET_CODE (XEXP (x, 0)) == SUBREG
5550 && GET_MODE (SUBREG_REG (XEXP (x, 0))) == GET_MODE (x)
5551 && subreg_lowpart_p (XEXP (x, 0))
5552 && COMPARISON_P (SUBREG_REG (XEXP (x, 0)))
5553 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
5554 <= HOST_BITS_PER_WIDE_INT)
5555 && ((HOST_WIDE_INT) STORE_FLAG_VALUE
5556 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5557 return SUBREG_REG (XEXP (x, 0));
5561 /* If we reach here, we want to return a pair of shifts. The inner
5562 shift is a left shift of BITSIZE - POS - LEN bits. The outer
5563 shift is a right shift of BITSIZE - LEN bits. It is arithmetic or
5564 logical depending on the value of UNSIGNEDP.
5566 If this was a ZERO_EXTEND or ZERO_EXTRACT, this pair of shifts will be
5567 converted into an AND of a shift.
5569 We must check for the case where the left shift would have a negative
5570 count. This can happen in a case like (x >> 31) & 255 on machines
5571 that can't shift by a constant. On those machines, we would first
5572 combine the shift with the AND to produce a variable-position
5573 extraction. Then the constant of 31 would be substituted in to produce
5574 a such a position. */
5576 modewidth = GET_MODE_BITSIZE (GET_MODE (x));
5577 if (modewidth + len >= pos)
5578 tem = simplify_shift_const (NULL_RTX, unsignedp ? LSHIFTRT : ASHIFTRT,
5580 simplify_shift_const (NULL_RTX, ASHIFT,
5583 modewidth - pos - len),
5586 else if (unsignedp && len < HOST_BITS_PER_WIDE_INT)
5587 tem = simplify_and_const_int (NULL_RTX, GET_MODE (x),
5588 simplify_shift_const (NULL_RTX, LSHIFTRT,
5591 ((HOST_WIDE_INT) 1 << len) - 1);
5593 /* Any other cases we can't handle. */
5596 /* If we couldn't do this for some reason, return the original
5598 if (GET_CODE (tem) == CLOBBER)
5604 /* X is a SET which contains an assignment of one object into
5605 a part of another (such as a bit-field assignment, STRICT_LOW_PART,
5606 or certain SUBREGS). If possible, convert it into a series of
5609 We half-heartedly support variable positions, but do not at all
5610 support variable lengths. */
5613 expand_field_assignment (rtx x)
5616 rtx pos; /* Always counts from low bit. */
5618 rtx mask, cleared, masked;
5619 enum machine_mode compute_mode;
5621 /* Loop until we find something we can't simplify. */
5624 if (GET_CODE (SET_DEST (x)) == STRICT_LOW_PART
5625 && GET_CODE (XEXP (SET_DEST (x), 0)) == SUBREG)
5627 inner = SUBREG_REG (XEXP (SET_DEST (x), 0));
5628 len = GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0)));
5629 pos = GEN_INT (subreg_lsb (XEXP (SET_DEST (x), 0)));
5631 else if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
5632 && GET_CODE (XEXP (SET_DEST (x), 1)) == CONST_INT)
5634 inner = XEXP (SET_DEST (x), 0);
5635 len = INTVAL (XEXP (SET_DEST (x), 1));
5636 pos = XEXP (SET_DEST (x), 2);
5638 /* If the position is constant and spans the width of INNER,
5639 surround INNER with a USE to indicate this. */
5640 if (GET_CODE (pos) == CONST_INT
5641 && INTVAL (pos) + len > GET_MODE_BITSIZE (GET_MODE (inner)))
5642 inner = gen_rtx_USE (GET_MODE (SET_DEST (x)), inner);
5644 if (BITS_BIG_ENDIAN)
5646 if (GET_CODE (pos) == CONST_INT)
5647 pos = GEN_INT (GET_MODE_BITSIZE (GET_MODE (inner)) - len
5649 else if (GET_CODE (pos) == MINUS
5650 && GET_CODE (XEXP (pos, 1)) == CONST_INT
5651 && (INTVAL (XEXP (pos, 1))
5652 == GET_MODE_BITSIZE (GET_MODE (inner)) - len))
5653 /* If position is ADJUST - X, new position is X. */
5654 pos = XEXP (pos, 0);
5656 pos = simplify_gen_binary (MINUS, GET_MODE (pos),
5657 GEN_INT (GET_MODE_BITSIZE (
5664 /* A SUBREG between two modes that occupy the same numbers of words
5665 can be done by moving the SUBREG to the source. */
5666 else if (GET_CODE (SET_DEST (x)) == SUBREG
5667 /* We need SUBREGs to compute nonzero_bits properly. */
5668 && nonzero_sign_valid
5669 && (((GET_MODE_SIZE (GET_MODE (SET_DEST (x)))
5670 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
5671 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x))))
5672 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)))
5674 x = gen_rtx_SET (VOIDmode, SUBREG_REG (SET_DEST (x)),
5676 (GET_MODE (SUBREG_REG (SET_DEST (x))),
5683 while (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
5684 inner = SUBREG_REG (inner);
5686 compute_mode = GET_MODE (inner);
5688 /* Don't attempt bitwise arithmetic on non scalar integer modes. */
5689 if (! SCALAR_INT_MODE_P (compute_mode))
5691 enum machine_mode imode;
5693 /* Don't do anything for vector or complex integral types. */
5694 if (! FLOAT_MODE_P (compute_mode))
5697 /* Try to find an integral mode to pun with. */
5698 imode = mode_for_size (GET_MODE_BITSIZE (compute_mode), MODE_INT, 0);
5699 if (imode == BLKmode)
5702 compute_mode = imode;
5703 inner = gen_lowpart (imode, inner);
5706 /* Compute a mask of LEN bits, if we can do this on the host machine. */
5707 if (len >= HOST_BITS_PER_WIDE_INT)
5710 /* Now compute the equivalent expression. Make a copy of INNER
5711 for the SET_DEST in case it is a MEM into which we will substitute;
5712 we don't want shared RTL in that case. */
5713 mask = GEN_INT (((HOST_WIDE_INT) 1 << len) - 1);
5714 cleared = simplify_gen_binary (AND, compute_mode,
5715 simplify_gen_unary (NOT, compute_mode,
5716 simplify_gen_binary (ASHIFT,
5721 masked = simplify_gen_binary (ASHIFT, compute_mode,
5722 simplify_gen_binary (
5724 gen_lowpart (compute_mode, SET_SRC (x)),
5728 x = gen_rtx_SET (VOIDmode, copy_rtx (inner),
5729 simplify_gen_binary (IOR, compute_mode,
5736 /* Return an RTX for a reference to LEN bits of INNER. If POS_RTX is nonzero,
5737 it is an RTX that represents a variable starting position; otherwise,
5738 POS is the (constant) starting bit position (counted from the LSB).
5740 INNER may be a USE. This will occur when we started with a bitfield
5741 that went outside the boundary of the object in memory, which is
5742 allowed on most machines. To isolate this case, we produce a USE
5743 whose mode is wide enough and surround the MEM with it. The only
5744 code that understands the USE is this routine. If it is not removed,
5745 it will cause the resulting insn not to match.
5747 UNSIGNEDP is nonzero for an unsigned reference and zero for a
5750 IN_DEST is nonzero if this is a reference in the destination of a
5751 SET. This is used when a ZERO_ or SIGN_EXTRACT isn't needed. If nonzero,
5752 a STRICT_LOW_PART will be used, if zero, ZERO_EXTEND or SIGN_EXTEND will
5755 IN_COMPARE is nonzero if we are in a COMPARE. This means that a
5756 ZERO_EXTRACT should be built even for bits starting at bit 0.
5758 MODE is the desired mode of the result (if IN_DEST == 0).
5760 The result is an RTX for the extraction or NULL_RTX if the target
5764 make_extraction (enum machine_mode mode, rtx inner, HOST_WIDE_INT pos,
5765 rtx pos_rtx, unsigned HOST_WIDE_INT len, int unsignedp,
5766 int in_dest, int in_compare)
5768 /* This mode describes the size of the storage area
5769 to fetch the overall value from. Within that, we
5770 ignore the POS lowest bits, etc. */
5771 enum machine_mode is_mode = GET_MODE (inner);
5772 enum machine_mode inner_mode;
5773 enum machine_mode wanted_inner_mode = byte_mode;
5774 enum machine_mode wanted_inner_reg_mode = word_mode;
5775 enum machine_mode pos_mode = word_mode;
5776 enum machine_mode extraction_mode = word_mode;
5777 enum machine_mode tmode = mode_for_size (len, MODE_INT, 1);
5780 rtx orig_pos_rtx = pos_rtx;
5781 HOST_WIDE_INT orig_pos;
5783 /* Get some information about INNER and get the innermost object. */
5784 if (GET_CODE (inner) == USE)
5785 /* (use:SI (mem:QI foo)) stands for (mem:SI foo). */
5786 /* We don't need to adjust the position because we set up the USE
5787 to pretend that it was a full-word object. */
5788 spans_byte = 1, inner = XEXP (inner, 0);
5789 else if (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
5791 /* If going from (subreg:SI (mem:QI ...)) to (mem:QI ...),
5792 consider just the QI as the memory to extract from.
5793 The subreg adds or removes high bits; its mode is
5794 irrelevant to the meaning of this extraction,
5795 since POS and LEN count from the lsb. */
5796 if (MEM_P (SUBREG_REG (inner)))
5797 is_mode = GET_MODE (SUBREG_REG (inner));
5798 inner = SUBREG_REG (inner);
5800 else if (GET_CODE (inner) == ASHIFT
5801 && GET_CODE (XEXP (inner, 1)) == CONST_INT
5802 && pos_rtx == 0 && pos == 0
5803 && len > (unsigned HOST_WIDE_INT) INTVAL (XEXP (inner, 1)))
5805 /* We're extracting the least significant bits of an rtx
5806 (ashift X (const_int C)), where LEN > C. Extract the
5807 least significant (LEN - C) bits of X, giving an rtx
5808 whose mode is MODE, then shift it left C times. */
5809 new = make_extraction (mode, XEXP (inner, 0),
5810 0, 0, len - INTVAL (XEXP (inner, 1)),
5811 unsignedp, in_dest, in_compare);
5813 return gen_rtx_ASHIFT (mode, new, XEXP (inner, 1));
5816 inner_mode = GET_MODE (inner);
5818 if (pos_rtx && GET_CODE (pos_rtx) == CONST_INT)
5819 pos = INTVAL (pos_rtx), pos_rtx = 0;
5821 /* See if this can be done without an extraction. We never can if the
5822 width of the field is not the same as that of some integer mode. For
5823 registers, we can only avoid the extraction if the position is at the
5824 low-order bit and this is either not in the destination or we have the
5825 appropriate STRICT_LOW_PART operation available.
5827 For MEM, we can avoid an extract if the field starts on an appropriate
5828 boundary and we can change the mode of the memory reference. However,
5829 we cannot directly access the MEM if we have a USE and the underlying
5830 MEM is not TMODE. This combination means that MEM was being used in a
5831 context where bits outside its mode were being referenced; that is only
5832 valid in bit-field insns. */
5834 if (tmode != BLKmode
5835 && ! (spans_byte && inner_mode != tmode)
5836 && ((pos_rtx == 0 && (pos % BITS_PER_WORD) == 0
5840 && have_insn_for (STRICT_LOW_PART, tmode))))
5841 || (MEM_P (inner) && pos_rtx == 0
5843 % (STRICT_ALIGNMENT ? GET_MODE_ALIGNMENT (tmode)
5844 : BITS_PER_UNIT)) == 0
5845 /* We can't do this if we are widening INNER_MODE (it
5846 may not be aligned, for one thing). */
5847 && GET_MODE_BITSIZE (inner_mode) >= GET_MODE_BITSIZE (tmode)
5848 && (inner_mode == tmode
5849 || (! mode_dependent_address_p (XEXP (inner, 0))
5850 && ! MEM_VOLATILE_P (inner))))))
5852 /* If INNER is a MEM, make a new MEM that encompasses just the desired
5853 field. If the original and current mode are the same, we need not
5854 adjust the offset. Otherwise, we do if bytes big endian.
5856 If INNER is not a MEM, get a piece consisting of just the field
5857 of interest (in this case POS % BITS_PER_WORD must be 0). */
5861 HOST_WIDE_INT offset;
5863 /* POS counts from lsb, but make OFFSET count in memory order. */
5864 if (BYTES_BIG_ENDIAN)
5865 offset = (GET_MODE_BITSIZE (is_mode) - len - pos) / BITS_PER_UNIT;
5867 offset = pos / BITS_PER_UNIT;
5869 new = adjust_address_nv (inner, tmode, offset);
5871 else if (REG_P (inner))
5873 if (tmode != inner_mode)
5875 /* We can't call gen_lowpart in a DEST since we
5876 always want a SUBREG (see below) and it would sometimes
5877 return a new hard register. */
5880 HOST_WIDE_INT final_word = pos / BITS_PER_WORD;
5882 if (WORDS_BIG_ENDIAN
5883 && GET_MODE_SIZE (inner_mode) > UNITS_PER_WORD)
5884 final_word = ((GET_MODE_SIZE (inner_mode)
5885 - GET_MODE_SIZE (tmode))
5886 / UNITS_PER_WORD) - final_word;
5888 final_word *= UNITS_PER_WORD;
5889 if (BYTES_BIG_ENDIAN &&
5890 GET_MODE_SIZE (inner_mode) > GET_MODE_SIZE (tmode))
5891 final_word += (GET_MODE_SIZE (inner_mode)
5892 - GET_MODE_SIZE (tmode)) % UNITS_PER_WORD;
5894 /* Avoid creating invalid subregs, for example when
5895 simplifying (x>>32)&255. */
5896 if (!validate_subreg (tmode, inner_mode, inner, final_word))
5899 new = gen_rtx_SUBREG (tmode, inner, final_word);
5902 new = gen_lowpart (tmode, inner);
5908 new = force_to_mode (inner, tmode,
5909 len >= HOST_BITS_PER_WIDE_INT
5910 ? ~(unsigned HOST_WIDE_INT) 0
5911 : ((unsigned HOST_WIDE_INT) 1 << len) - 1,
5914 /* If this extraction is going into the destination of a SET,
5915 make a STRICT_LOW_PART unless we made a MEM. */
5918 return (MEM_P (new) ? new
5919 : (GET_CODE (new) != SUBREG
5920 ? gen_rtx_CLOBBER (tmode, const0_rtx)
5921 : gen_rtx_STRICT_LOW_PART (VOIDmode, new)));
5926 if (GET_CODE (new) == CONST_INT)
5927 return gen_int_mode (INTVAL (new), mode);
5929 /* If we know that no extraneous bits are set, and that the high
5930 bit is not set, convert the extraction to the cheaper of
5931 sign and zero extension, that are equivalent in these cases. */
5932 if (flag_expensive_optimizations
5933 && (GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT
5934 && ((nonzero_bits (new, tmode)
5935 & ~(((unsigned HOST_WIDE_INT)
5936 GET_MODE_MASK (tmode))
5940 rtx temp = gen_rtx_ZERO_EXTEND (mode, new);
5941 rtx temp1 = gen_rtx_SIGN_EXTEND (mode, new);
5943 /* Prefer ZERO_EXTENSION, since it gives more information to
5945 if (rtx_cost (temp, SET) <= rtx_cost (temp1, SET))
5950 /* Otherwise, sign- or zero-extend unless we already are in the
5953 return (gen_rtx_fmt_e (unsignedp ? ZERO_EXTEND : SIGN_EXTEND,
5957 /* Unless this is a COMPARE or we have a funny memory reference,
5958 don't do anything with zero-extending field extracts starting at
5959 the low-order bit since they are simple AND operations. */
5960 if (pos_rtx == 0 && pos == 0 && ! in_dest
5961 && ! in_compare && ! spans_byte && unsignedp)
5964 /* Unless we are allowed to span bytes or INNER is not MEM, reject this if
5965 we would be spanning bytes or if the position is not a constant and the
5966 length is not 1. In all other cases, we would only be going outside
5967 our object in cases when an original shift would have been
5969 if (! spans_byte && MEM_P (inner)
5970 && ((pos_rtx == 0 && pos + len > GET_MODE_BITSIZE (is_mode))
5971 || (pos_rtx != 0 && len != 1)))
5974 /* Get the mode to use should INNER not be a MEM, the mode for the position,
5975 and the mode for the result. */
5976 if (in_dest && mode_for_extraction (EP_insv, -1) != MAX_MACHINE_MODE)
5978 wanted_inner_reg_mode = mode_for_extraction (EP_insv, 0);
5979 pos_mode = mode_for_extraction (EP_insv, 2);
5980 extraction_mode = mode_for_extraction (EP_insv, 3);
5983 if (! in_dest && unsignedp
5984 && mode_for_extraction (EP_extzv, -1) != MAX_MACHINE_MODE)
5986 wanted_inner_reg_mode = mode_for_extraction (EP_extzv, 1);
5987 pos_mode = mode_for_extraction (EP_extzv, 3);
5988 extraction_mode = mode_for_extraction (EP_extzv, 0);
5991 if (! in_dest && ! unsignedp
5992 && mode_for_extraction (EP_extv, -1) != MAX_MACHINE_MODE)
5994 wanted_inner_reg_mode = mode_for_extraction (EP_extv, 1);
5995 pos_mode = mode_for_extraction (EP_extv, 3);
5996 extraction_mode = mode_for_extraction (EP_extv, 0);
5999 /* Never narrow an object, since that might not be safe. */
6001 if (mode != VOIDmode
6002 && GET_MODE_SIZE (extraction_mode) < GET_MODE_SIZE (mode))
6003 extraction_mode = mode;
6005 if (pos_rtx && GET_MODE (pos_rtx) != VOIDmode
6006 && GET_MODE_SIZE (pos_mode) < GET_MODE_SIZE (GET_MODE (pos_rtx)))
6007 pos_mode = GET_MODE (pos_rtx);
6009 /* If this is not from memory, the desired mode is wanted_inner_reg_mode;
6010 if we have to change the mode of memory and cannot, the desired mode is
6013 wanted_inner_mode = wanted_inner_reg_mode;
6014 else if (inner_mode != wanted_inner_mode
6015 && (mode_dependent_address_p (XEXP (inner, 0))
6016 || MEM_VOLATILE_P (inner)))
6017 wanted_inner_mode = extraction_mode;
6021 if (BITS_BIG_ENDIAN)
6023 /* POS is passed as if BITS_BIG_ENDIAN == 0, so we need to convert it to
6024 BITS_BIG_ENDIAN style. If position is constant, compute new
6025 position. Otherwise, build subtraction.
6026 Note that POS is relative to the mode of the original argument.
6027 If it's a MEM we need to recompute POS relative to that.
6028 However, if we're extracting from (or inserting into) a register,
6029 we want to recompute POS relative to wanted_inner_mode. */
6030 int width = (MEM_P (inner)
6031 ? GET_MODE_BITSIZE (is_mode)
6032 : GET_MODE_BITSIZE (wanted_inner_mode));
6035 pos = width - len - pos;
6038 = gen_rtx_MINUS (GET_MODE (pos_rtx), GEN_INT (width - len), pos_rtx);
6039 /* POS may be less than 0 now, but we check for that below.
6040 Note that it can only be less than 0 if !MEM_P (inner). */
6043 /* If INNER has a wider mode, make it smaller. If this is a constant
6044 extract, try to adjust the byte to point to the byte containing
6046 if (wanted_inner_mode != VOIDmode
6047 && GET_MODE_SIZE (wanted_inner_mode) < GET_MODE_SIZE (is_mode)
6049 && (inner_mode == wanted_inner_mode
6050 || (! mode_dependent_address_p (XEXP (inner, 0))
6051 && ! MEM_VOLATILE_P (inner))))))
6055 /* The computations below will be correct if the machine is big
6056 endian in both bits and bytes or little endian in bits and bytes.
6057 If it is mixed, we must adjust. */
6059 /* If bytes are big endian and we had a paradoxical SUBREG, we must
6060 adjust OFFSET to compensate. */
6061 if (BYTES_BIG_ENDIAN
6063 && GET_MODE_SIZE (inner_mode) < GET_MODE_SIZE (is_mode))
6064 offset -= GET_MODE_SIZE (is_mode) - GET_MODE_SIZE (inner_mode);
6066 /* If this is a constant position, we can move to the desired byte.
6067 Be careful not to go beyond the original object and maintain the
6068 natural alignment of the memory. */
6071 enum machine_mode bfmode = smallest_mode_for_size (len, MODE_INT);
6072 offset += (pos / GET_MODE_BITSIZE (bfmode)) * GET_MODE_SIZE (bfmode);
6073 pos %= GET_MODE_BITSIZE (bfmode);
6076 if (BYTES_BIG_ENDIAN != BITS_BIG_ENDIAN
6078 && is_mode != wanted_inner_mode)
6079 offset = (GET_MODE_SIZE (is_mode)
6080 - GET_MODE_SIZE (wanted_inner_mode) - offset);
6082 if (offset != 0 || inner_mode != wanted_inner_mode)
6083 inner = adjust_address_nv (inner, wanted_inner_mode, offset);
6086 /* If INNER is not memory, we can always get it into the proper mode. If we
6087 are changing its mode, POS must be a constant and smaller than the size
6089 else if (!MEM_P (inner))
6091 if (GET_MODE (inner) != wanted_inner_mode
6093 || orig_pos + len > GET_MODE_BITSIZE (wanted_inner_mode)))
6096 inner = force_to_mode (inner, wanted_inner_mode,
6098 || len + orig_pos >= HOST_BITS_PER_WIDE_INT
6099 ? ~(unsigned HOST_WIDE_INT) 0
6100 : ((((unsigned HOST_WIDE_INT) 1 << len) - 1)
6105 /* Adjust mode of POS_RTX, if needed. If we want a wider mode, we
6106 have to zero extend. Otherwise, we can just use a SUBREG. */
6108 && GET_MODE_SIZE (pos_mode) > GET_MODE_SIZE (GET_MODE (pos_rtx)))
6110 rtx temp = gen_rtx_ZERO_EXTEND (pos_mode, pos_rtx);
6112 /* If we know that no extraneous bits are set, and that the high
6113 bit is not set, convert extraction to cheaper one - either
6114 SIGN_EXTENSION or ZERO_EXTENSION, that are equivalent in these
6116 if (flag_expensive_optimizations
6117 && (GET_MODE_BITSIZE (GET_MODE (pos_rtx)) <= HOST_BITS_PER_WIDE_INT
6118 && ((nonzero_bits (pos_rtx, GET_MODE (pos_rtx))
6119 & ~(((unsigned HOST_WIDE_INT)
6120 GET_MODE_MASK (GET_MODE (pos_rtx)))
6124 rtx temp1 = gen_rtx_SIGN_EXTEND (pos_mode, pos_rtx);
6126 /* Prefer ZERO_EXTENSION, since it gives more information to
6128 if (rtx_cost (temp1, SET) < rtx_cost (temp, SET))
6133 else if (pos_rtx != 0
6134 && GET_MODE_SIZE (pos_mode) < GET_MODE_SIZE (GET_MODE (pos_rtx)))
6135 pos_rtx = gen_lowpart (pos_mode, pos_rtx);
6137 /* Make POS_RTX unless we already have it and it is correct. If we don't
6138 have a POS_RTX but we do have an ORIG_POS_RTX, the latter must
6140 if (pos_rtx == 0 && orig_pos_rtx != 0 && INTVAL (orig_pos_rtx) == pos)
6141 pos_rtx = orig_pos_rtx;
6143 else if (pos_rtx == 0)
6144 pos_rtx = GEN_INT (pos);
6146 /* Make the required operation. See if we can use existing rtx. */
6147 new = gen_rtx_fmt_eee (unsignedp ? ZERO_EXTRACT : SIGN_EXTRACT,
6148 extraction_mode, inner, GEN_INT (len), pos_rtx);
6150 new = gen_lowpart (mode, new);
6155 /* See if X contains an ASHIFT of COUNT or more bits that can be commuted
6156 with any other operations in X. Return X without that shift if so. */
6159 extract_left_shift (rtx x, int count)
6161 enum rtx_code code = GET_CODE (x);
6162 enum machine_mode mode = GET_MODE (x);
6168 /* This is the shift itself. If it is wide enough, we will return
6169 either the value being shifted if the shift count is equal to
6170 COUNT or a shift for the difference. */
6171 if (GET_CODE (XEXP (x, 1)) == CONST_INT
6172 && INTVAL (XEXP (x, 1)) >= count)
6173 return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (x, 0),
6174 INTVAL (XEXP (x, 1)) - count);
6178 if ((tem = extract_left_shift (XEXP (x, 0), count)) != 0)
6179 return simplify_gen_unary (code, mode, tem, mode);
6183 case PLUS: case IOR: case XOR: case AND:
6184 /* If we can safely shift this constant and we find the inner shift,
6185 make a new operation. */
6186 if (GET_CODE (XEXP (x, 1)) == CONST_INT
6187 && (INTVAL (XEXP (x, 1)) & ((((HOST_WIDE_INT) 1 << count)) - 1)) == 0
6188 && (tem = extract_left_shift (XEXP (x, 0), count)) != 0)
6189 return simplify_gen_binary (code, mode, tem,
6190 GEN_INT (INTVAL (XEXP (x, 1)) >> count));
6201 /* Look at the expression rooted at X. Look for expressions
6202 equivalent to ZERO_EXTRACT, SIGN_EXTRACT, ZERO_EXTEND, SIGN_EXTEND.
6203 Form these expressions.
6205 Return the new rtx, usually just X.
6207 Also, for machines like the VAX that don't have logical shift insns,
6208 try to convert logical to arithmetic shift operations in cases where
6209 they are equivalent. This undoes the canonicalizations to logical
6210 shifts done elsewhere.
6212 We try, as much as possible, to re-use rtl expressions to save memory.
6214 IN_CODE says what kind of expression we are processing. Normally, it is
6215 SET. In a memory address (inside a MEM, PLUS or minus, the latter two
6216 being kludges), it is MEM. When processing the arguments of a comparison
6217 or a COMPARE against zero, it is COMPARE. */
6220 make_compound_operation (rtx x, enum rtx_code in_code)
6222 enum rtx_code code = GET_CODE (x);
6223 enum machine_mode mode = GET_MODE (x);
6224 int mode_width = GET_MODE_BITSIZE (mode);
6226 enum rtx_code next_code;
6232 /* Select the code to be used in recursive calls. Once we are inside an
6233 address, we stay there. If we have a comparison, set to COMPARE,
6234 but once inside, go back to our default of SET. */
6236 next_code = (code == MEM || code == PLUS || code == MINUS ? MEM
6237 : ((code == COMPARE || COMPARISON_P (x))
6238 && XEXP (x, 1) == const0_rtx) ? COMPARE
6239 : in_code == COMPARE ? SET : in_code);
6241 /* Process depending on the code of this operation. If NEW is set
6242 nonzero, it will be returned. */
6247 /* Convert shifts by constants into multiplications if inside
6249 if (in_code == MEM && GET_CODE (XEXP (x, 1)) == CONST_INT
6250 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT
6251 && INTVAL (XEXP (x, 1)) >= 0)
6253 new = make_compound_operation (XEXP (x, 0), next_code);
6254 new = gen_rtx_MULT (mode, new,
6255 GEN_INT ((HOST_WIDE_INT) 1
6256 << INTVAL (XEXP (x, 1))));
6261 /* If the second operand is not a constant, we can't do anything
6263 if (GET_CODE (XEXP (x, 1)) != CONST_INT)
6266 /* If the constant is a power of two minus one and the first operand
6267 is a logical right shift, make an extraction. */
6268 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
6269 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6271 new = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code);
6272 new = make_extraction (mode, new, 0, XEXP (XEXP (x, 0), 1), i, 1,
6273 0, in_code == COMPARE);
6276 /* Same as previous, but for (subreg (lshiftrt ...)) in first op. */
6277 else if (GET_CODE (XEXP (x, 0)) == SUBREG
6278 && subreg_lowpart_p (XEXP (x, 0))
6279 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == LSHIFTRT
6280 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6282 new = make_compound_operation (XEXP (SUBREG_REG (XEXP (x, 0)), 0),
6284 new = make_extraction (GET_MODE (SUBREG_REG (XEXP (x, 0))), new, 0,
6285 XEXP (SUBREG_REG (XEXP (x, 0)), 1), i, 1,
6286 0, in_code == COMPARE);
6288 /* Same as previous, but for (xor/ior (lshiftrt...) (lshiftrt...)). */
6289 else if ((GET_CODE (XEXP (x, 0)) == XOR
6290 || GET_CODE (XEXP (x, 0)) == IOR)
6291 && GET_CODE (XEXP (XEXP (x, 0), 0)) == LSHIFTRT
6292 && GET_CODE (XEXP (XEXP (x, 0), 1)) == LSHIFTRT
6293 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6295 /* Apply the distributive law, and then try to make extractions. */
6296 new = gen_rtx_fmt_ee (GET_CODE (XEXP (x, 0)), mode,
6297 gen_rtx_AND (mode, XEXP (XEXP (x, 0), 0),
6299 gen_rtx_AND (mode, XEXP (XEXP (x, 0), 1),
6301 new = make_compound_operation (new, in_code);
6304 /* If we are have (and (rotate X C) M) and C is larger than the number
6305 of bits in M, this is an extraction. */
6307 else if (GET_CODE (XEXP (x, 0)) == ROTATE
6308 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
6309 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0
6310 && i <= INTVAL (XEXP (XEXP (x, 0), 1)))
6312 new = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code);
6313 new = make_extraction (mode, new,
6314 (GET_MODE_BITSIZE (mode)
6315 - INTVAL (XEXP (XEXP (x, 0), 1))),
6316 NULL_RTX, i, 1, 0, in_code == COMPARE);
6319 /* On machines without logical shifts, if the operand of the AND is
6320 a logical shift and our mask turns off all the propagated sign
6321 bits, we can replace the logical shift with an arithmetic shift. */
6322 else if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
6323 && !have_insn_for (LSHIFTRT, mode)
6324 && have_insn_for (ASHIFTRT, mode)
6325 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
6326 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
6327 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT
6328 && mode_width <= HOST_BITS_PER_WIDE_INT)
6330 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
6332 mask >>= INTVAL (XEXP (XEXP (x, 0), 1));
6333 if ((INTVAL (XEXP (x, 1)) & ~mask) == 0)
6335 gen_rtx_ASHIFTRT (mode,
6336 make_compound_operation
6337 (XEXP (XEXP (x, 0), 0), next_code),
6338 XEXP (XEXP (x, 0), 1)));
6341 /* If the constant is one less than a power of two, this might be
6342 representable by an extraction even if no shift is present.
6343 If it doesn't end up being a ZERO_EXTEND, we will ignore it unless
6344 we are in a COMPARE. */
6345 else if ((i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6346 new = make_extraction (mode,
6347 make_compound_operation (XEXP (x, 0),
6349 0, NULL_RTX, i, 1, 0, in_code == COMPARE);
6351 /* If we are in a comparison and this is an AND with a power of two,
6352 convert this into the appropriate bit extract. */
6353 else if (in_code == COMPARE
6354 && (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0)
6355 new = make_extraction (mode,
6356 make_compound_operation (XEXP (x, 0),
6358 i, NULL_RTX, 1, 1, 0, 1);
6363 /* If the sign bit is known to be zero, replace this with an
6364 arithmetic shift. */
6365 if (have_insn_for (ASHIFTRT, mode)
6366 && ! have_insn_for (LSHIFTRT, mode)
6367 && mode_width <= HOST_BITS_PER_WIDE_INT
6368 && (nonzero_bits (XEXP (x, 0), mode) & (1 << (mode_width - 1))) == 0)
6370 new = gen_rtx_ASHIFTRT (mode,
6371 make_compound_operation (XEXP (x, 0),
6377 /* ... fall through ... */
6383 /* If we have (ashiftrt (ashift foo C1) C2) with C2 >= C1,
6384 this is a SIGN_EXTRACT. */
6385 if (GET_CODE (rhs) == CONST_INT
6386 && GET_CODE (lhs) == ASHIFT
6387 && GET_CODE (XEXP (lhs, 1)) == CONST_INT
6388 && INTVAL (rhs) >= INTVAL (XEXP (lhs, 1)))
6390 new = make_compound_operation (XEXP (lhs, 0), next_code);
6391 new = make_extraction (mode, new,
6392 INTVAL (rhs) - INTVAL (XEXP (lhs, 1)),
6393 NULL_RTX, mode_width - INTVAL (rhs),
6394 code == LSHIFTRT, 0, in_code == COMPARE);
6398 /* See if we have operations between an ASHIFTRT and an ASHIFT.
6399 If so, try to merge the shifts into a SIGN_EXTEND. We could
6400 also do this for some cases of SIGN_EXTRACT, but it doesn't
6401 seem worth the effort; the case checked for occurs on Alpha. */
6404 && ! (GET_CODE (lhs) == SUBREG
6405 && (OBJECT_P (SUBREG_REG (lhs))))
6406 && GET_CODE (rhs) == CONST_INT
6407 && INTVAL (rhs) < HOST_BITS_PER_WIDE_INT
6408 && (new = extract_left_shift (lhs, INTVAL (rhs))) != 0)
6409 new = make_extraction (mode, make_compound_operation (new, next_code),
6410 0, NULL_RTX, mode_width - INTVAL (rhs),
6411 code == LSHIFTRT, 0, in_code == COMPARE);
6416 /* Call ourselves recursively on the inner expression. If we are
6417 narrowing the object and it has a different RTL code from
6418 what it originally did, do this SUBREG as a force_to_mode. */
6420 tem = make_compound_operation (SUBREG_REG (x), in_code);
6424 simplified = simplify_subreg (GET_MODE (x), tem, GET_MODE (tem),
6430 if (GET_CODE (tem) != GET_CODE (SUBREG_REG (x))
6431 && GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (tem))
6432 && subreg_lowpart_p (x))
6434 rtx newer = force_to_mode (tem, mode, ~(HOST_WIDE_INT) 0,
6437 /* If we have something other than a SUBREG, we might have
6438 done an expansion, so rerun ourselves. */
6439 if (GET_CODE (newer) != SUBREG)
6440 newer = make_compound_operation (newer, in_code);
6456 x = gen_lowpart (mode, new);
6457 code = GET_CODE (x);
6460 /* Now recursively process each operand of this operation. */
6461 fmt = GET_RTX_FORMAT (code);
6462 for (i = 0; i < GET_RTX_LENGTH (code); i++)
6465 new = make_compound_operation (XEXP (x, i), next_code);
6466 SUBST (XEXP (x, i), new);
6469 /* If this is a commutative operation, the changes to the operands
6470 may have made it noncanonical. */
6471 if (COMMUTATIVE_ARITH_P (x)
6472 && swap_commutative_operands_p (XEXP (x, 0), XEXP (x, 1)))
6475 SUBST (XEXP (x, 0), XEXP (x, 1));
6476 SUBST (XEXP (x, 1), tem);
6482 /* Given M see if it is a value that would select a field of bits
6483 within an item, but not the entire word. Return -1 if not.
6484 Otherwise, return the starting position of the field, where 0 is the
6487 *PLEN is set to the length of the field. */
6490 get_pos_from_mask (unsigned HOST_WIDE_INT m, unsigned HOST_WIDE_INT *plen)
6492 /* Get the bit number of the first 1 bit from the right, -1 if none. */
6493 int pos = exact_log2 (m & -m);
6497 /* Now shift off the low-order zero bits and see if we have a
6498 power of two minus 1. */
6499 len = exact_log2 ((m >> pos) + 1);
6508 /* If X refers to a register that equals REG in value, replace these
6509 references with REG. */
6511 canon_reg_for_combine (rtx x, rtx reg)
6518 enum rtx_code code = GET_CODE (x);
6519 switch (GET_RTX_CLASS (code))
6522 op0 = canon_reg_for_combine (XEXP (x, 0), reg);
6523 if (op0 != XEXP (x, 0))
6524 return simplify_gen_unary (GET_CODE (x), GET_MODE (x), op0,
6529 case RTX_COMM_ARITH:
6530 op0 = canon_reg_for_combine (XEXP (x, 0), reg);
6531 op1 = canon_reg_for_combine (XEXP (x, 1), reg);
6532 if (op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
6533 return simplify_gen_binary (GET_CODE (x), GET_MODE (x), op0, op1);
6537 case RTX_COMM_COMPARE:
6538 op0 = canon_reg_for_combine (XEXP (x, 0), reg);
6539 op1 = canon_reg_for_combine (XEXP (x, 1), reg);
6540 if (op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
6541 return simplify_gen_relational (GET_CODE (x), GET_MODE (x),
6542 GET_MODE (op0), op0, op1);
6546 case RTX_BITFIELD_OPS:
6547 op0 = canon_reg_for_combine (XEXP (x, 0), reg);
6548 op1 = canon_reg_for_combine (XEXP (x, 1), reg);
6549 op2 = canon_reg_for_combine (XEXP (x, 2), reg);
6550 if (op0 != XEXP (x, 0) || op1 != XEXP (x, 1) || op2 != XEXP (x, 2))
6551 return simplify_gen_ternary (GET_CODE (x), GET_MODE (x),
6552 GET_MODE (op0), op0, op1, op2);
6557 if (rtx_equal_p (get_last_value (reg), x)
6558 || rtx_equal_p (reg, get_last_value (x)))
6567 fmt = GET_RTX_FORMAT (code);
6569 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
6572 rtx op = canon_reg_for_combine (XEXP (x, i), reg);
6573 if (op != XEXP (x, i))
6583 else if (fmt[i] == 'E')
6586 for (j = 0; j < XVECLEN (x, i); j++)
6588 rtx op = canon_reg_for_combine (XVECEXP (x, i, j), reg);
6589 if (op != XVECEXP (x, i, j))
6596 XVECEXP (x, i, j) = op;
6607 /* See if X can be simplified knowing that we will only refer to it in
6608 MODE and will only refer to those bits that are nonzero in MASK.
6609 If other bits are being computed or if masking operations are done
6610 that select a superset of the bits in MASK, they can sometimes be
6613 Return a possibly simplified expression, but always convert X to
6614 MODE. If X is a CONST_INT, AND the CONST_INT with MASK.
6616 If JUST_SELECT is nonzero, don't optimize by noticing that bits in MASK
6617 are all off in X. This is used when X will be complemented, by either
6618 NOT, NEG, or XOR. */
6621 force_to_mode (rtx x, enum machine_mode mode, unsigned HOST_WIDE_INT mask,
6624 enum rtx_code code = GET_CODE (x);
6625 int next_select = just_select || code == XOR || code == NOT || code == NEG;
6626 enum machine_mode op_mode;
6627 unsigned HOST_WIDE_INT fuller_mask, nonzero;
6630 /* If this is a CALL or ASM_OPERANDS, don't do anything. Some of the
6631 code below will do the wrong thing since the mode of such an
6632 expression is VOIDmode.
6634 Also do nothing if X is a CLOBBER; this can happen if X was
6635 the return value from a call to gen_lowpart. */
6636 if (code == CALL || code == ASM_OPERANDS || code == CLOBBER)
6639 /* We want to perform the operation is its present mode unless we know
6640 that the operation is valid in MODE, in which case we do the operation
6642 op_mode = ((GET_MODE_CLASS (mode) == GET_MODE_CLASS (GET_MODE (x))
6643 && have_insn_for (code, mode))
6644 ? mode : GET_MODE (x));
6646 /* It is not valid to do a right-shift in a narrower mode
6647 than the one it came in with. */
6648 if ((code == LSHIFTRT || code == ASHIFTRT)
6649 && GET_MODE_BITSIZE (mode) < GET_MODE_BITSIZE (GET_MODE (x)))
6650 op_mode = GET_MODE (x);
6652 /* Truncate MASK to fit OP_MODE. */
6654 mask &= GET_MODE_MASK (op_mode);
6656 /* When we have an arithmetic operation, or a shift whose count we
6657 do not know, we need to assume that all bits up to the highest-order
6658 bit in MASK will be needed. This is how we form such a mask. */
6659 if (mask & ((unsigned HOST_WIDE_INT) 1 << (HOST_BITS_PER_WIDE_INT - 1)))
6660 fuller_mask = ~(unsigned HOST_WIDE_INT) 0;
6662 fuller_mask = (((unsigned HOST_WIDE_INT) 1 << (floor_log2 (mask) + 1))
6665 /* Determine what bits of X are guaranteed to be (non)zero. */
6666 nonzero = nonzero_bits (x, mode);
6668 /* If none of the bits in X are needed, return a zero. */
6669 if (! just_select && (nonzero & mask) == 0)
6672 /* If X is a CONST_INT, return a new one. Do this here since the
6673 test below will fail. */
6674 if (GET_CODE (x) == CONST_INT)
6676 if (SCALAR_INT_MODE_P (mode))
6677 return gen_int_mode (INTVAL (x) & mask, mode);
6680 x = GEN_INT (INTVAL (x) & mask);
6681 return gen_lowpart_common (mode, x);
6685 /* If X is narrower than MODE and we want all the bits in X's mode, just
6686 get X in the proper mode. */
6687 if (GET_MODE_SIZE (GET_MODE (x)) < GET_MODE_SIZE (mode)
6688 && (GET_MODE_MASK (GET_MODE (x)) & ~mask) == 0)
6689 return gen_lowpart (mode, x);
6694 /* If X is a (clobber (const_int)), return it since we know we are
6695 generating something that won't match. */
6699 /* X is a (use (mem ..)) that was made from a bit-field extraction that
6700 spanned the boundary of the MEM. If we are now masking so it is
6701 within that boundary, we don't need the USE any more. */
6702 if (! BITS_BIG_ENDIAN
6703 && (mask & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
6704 return force_to_mode (XEXP (x, 0), mode, mask, next_select);
6711 x = expand_compound_operation (x);
6712 if (GET_CODE (x) != code)
6713 return force_to_mode (x, mode, mask, next_select);
6717 if (subreg_lowpart_p (x)
6718 /* We can ignore the effect of this SUBREG if it narrows the mode or
6719 if the constant masks to zero all the bits the mode doesn't
6721 && ((GET_MODE_SIZE (GET_MODE (x))
6722 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
6724 & GET_MODE_MASK (GET_MODE (x))
6725 & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (x)))))))
6726 return force_to_mode (SUBREG_REG (x), mode, mask, next_select);
6730 /* If this is an AND with a constant, convert it into an AND
6731 whose constant is the AND of that constant with MASK. If it
6732 remains an AND of MASK, delete it since it is redundant. */
6734 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
6736 x = simplify_and_const_int (x, op_mode, XEXP (x, 0),
6737 mask & INTVAL (XEXP (x, 1)));
6739 /* If X is still an AND, see if it is an AND with a mask that
6740 is just some low-order bits. If so, and it is MASK, we don't
6743 if (GET_CODE (x) == AND && GET_CODE (XEXP (x, 1)) == CONST_INT
6744 && ((INTVAL (XEXP (x, 1)) & GET_MODE_MASK (GET_MODE (x)))
6748 /* If it remains an AND, try making another AND with the bits
6749 in the mode mask that aren't in MASK turned on. If the
6750 constant in the AND is wide enough, this might make a
6751 cheaper constant. */
6753 if (GET_CODE (x) == AND && GET_CODE (XEXP (x, 1)) == CONST_INT
6754 && GET_MODE_MASK (GET_MODE (x)) != mask
6755 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT)
6757 HOST_WIDE_INT cval = (INTVAL (XEXP (x, 1))
6758 | (GET_MODE_MASK (GET_MODE (x)) & ~mask));
6759 int width = GET_MODE_BITSIZE (GET_MODE (x));
6762 /* If MODE is narrower than HOST_WIDE_INT and CVAL is a negative
6763 number, sign extend it. */
6764 if (width > 0 && width < HOST_BITS_PER_WIDE_INT
6765 && (cval & ((HOST_WIDE_INT) 1 << (width - 1))) != 0)
6766 cval |= (HOST_WIDE_INT) -1 << width;
6768 y = simplify_gen_binary (AND, GET_MODE (x),
6769 XEXP (x, 0), GEN_INT (cval));
6770 if (rtx_cost (y, SET) < rtx_cost (x, SET))
6780 /* In (and (plus FOO C1) M), if M is a mask that just turns off
6781 low-order bits (as in an alignment operation) and FOO is already
6782 aligned to that boundary, mask C1 to that boundary as well.
6783 This may eliminate that PLUS and, later, the AND. */
6786 unsigned int width = GET_MODE_BITSIZE (mode);
6787 unsigned HOST_WIDE_INT smask = mask;
6789 /* If MODE is narrower than HOST_WIDE_INT and mask is a negative
6790 number, sign extend it. */
6792 if (width < HOST_BITS_PER_WIDE_INT
6793 && (smask & ((HOST_WIDE_INT) 1 << (width - 1))) != 0)
6794 smask |= (HOST_WIDE_INT) -1 << width;
6796 if (GET_CODE (XEXP (x, 1)) == CONST_INT
6797 && exact_log2 (- smask) >= 0
6798 && (nonzero_bits (XEXP (x, 0), mode) & ~smask) == 0
6799 && (INTVAL (XEXP (x, 1)) & ~smask) != 0)
6800 return force_to_mode (plus_constant (XEXP (x, 0),
6801 (INTVAL (XEXP (x, 1)) & smask)),
6802 mode, smask, next_select);
6805 /* ... fall through ... */
6808 /* For PLUS, MINUS and MULT, we need any bits less significant than the
6809 most significant bit in MASK since carries from those bits will
6810 affect the bits we are interested in. */
6815 /* If X is (minus C Y) where C's least set bit is larger than any bit
6816 in the mask, then we may replace with (neg Y). */
6817 if (GET_CODE (XEXP (x, 0)) == CONST_INT
6818 && (((unsigned HOST_WIDE_INT) (INTVAL (XEXP (x, 0))
6819 & -INTVAL (XEXP (x, 0))))
6822 x = simplify_gen_unary (NEG, GET_MODE (x), XEXP (x, 1),
6824 return force_to_mode (x, mode, mask, next_select);
6827 /* Similarly, if C contains every bit in the fuller_mask, then we may
6828 replace with (not Y). */
6829 if (GET_CODE (XEXP (x, 0)) == CONST_INT
6830 && ((INTVAL (XEXP (x, 0)) | (HOST_WIDE_INT) fuller_mask)
6831 == INTVAL (XEXP (x, 0))))
6833 x = simplify_gen_unary (NOT, GET_MODE (x),
6834 XEXP (x, 1), GET_MODE (x));
6835 return force_to_mode (x, mode, mask, next_select);
6843 /* If X is (ior (lshiftrt FOO C1) C2), try to commute the IOR and
6844 LSHIFTRT so we end up with an (and (lshiftrt (ior ...) ...) ...)
6845 operation which may be a bitfield extraction. Ensure that the
6846 constant we form is not wider than the mode of X. */
6848 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
6849 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
6850 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
6851 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT
6852 && GET_CODE (XEXP (x, 1)) == CONST_INT
6853 && ((INTVAL (XEXP (XEXP (x, 0), 1))
6854 + floor_log2 (INTVAL (XEXP (x, 1))))
6855 < GET_MODE_BITSIZE (GET_MODE (x)))
6856 && (INTVAL (XEXP (x, 1))
6857 & ~nonzero_bits (XEXP (x, 0), GET_MODE (x))) == 0)
6859 temp = GEN_INT ((INTVAL (XEXP (x, 1)) & mask)
6860 << INTVAL (XEXP (XEXP (x, 0), 1)));
6861 temp = simplify_gen_binary (GET_CODE (x), GET_MODE (x),
6862 XEXP (XEXP (x, 0), 0), temp);
6863 x = simplify_gen_binary (LSHIFTRT, GET_MODE (x), temp,
6864 XEXP (XEXP (x, 0), 1));
6865 return force_to_mode (x, mode, mask, next_select);
6869 /* For most binary operations, just propagate into the operation and
6870 change the mode if we have an operation of that mode. */
6872 op0 = gen_lowpart (op_mode,
6873 force_to_mode (XEXP (x, 0), mode, mask,
6875 op1 = gen_lowpart (op_mode,
6876 force_to_mode (XEXP (x, 1), mode, mask,
6879 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
6880 x = simplify_gen_binary (code, op_mode, op0, op1);
6884 /* For left shifts, do the same, but just for the first operand.
6885 However, we cannot do anything with shifts where we cannot
6886 guarantee that the counts are smaller than the size of the mode
6887 because such a count will have a different meaning in a
6890 if (! (GET_CODE (XEXP (x, 1)) == CONST_INT
6891 && INTVAL (XEXP (x, 1)) >= 0
6892 && INTVAL (XEXP (x, 1)) < GET_MODE_BITSIZE (mode))
6893 && ! (GET_MODE (XEXP (x, 1)) != VOIDmode
6894 && (nonzero_bits (XEXP (x, 1), GET_MODE (XEXP (x, 1)))
6895 < (unsigned HOST_WIDE_INT) GET_MODE_BITSIZE (mode))))
6898 /* If the shift count is a constant and we can do arithmetic in
6899 the mode of the shift, refine which bits we need. Otherwise, use the
6900 conservative form of the mask. */
6901 if (GET_CODE (XEXP (x, 1)) == CONST_INT
6902 && INTVAL (XEXP (x, 1)) >= 0
6903 && INTVAL (XEXP (x, 1)) < GET_MODE_BITSIZE (op_mode)
6904 && GET_MODE_BITSIZE (op_mode) <= HOST_BITS_PER_WIDE_INT)
6905 mask >>= INTVAL (XEXP (x, 1));
6909 op0 = gen_lowpart (op_mode,
6910 force_to_mode (XEXP (x, 0), op_mode,
6911 mask, next_select));
6913 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0))
6914 x = simplify_gen_binary (code, op_mode, op0, XEXP (x, 1));
6918 /* Here we can only do something if the shift count is a constant,
6919 this shift constant is valid for the host, and we can do arithmetic
6922 if (GET_CODE (XEXP (x, 1)) == CONST_INT
6923 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT
6924 && GET_MODE_BITSIZE (op_mode) <= HOST_BITS_PER_WIDE_INT)
6926 rtx inner = XEXP (x, 0);
6927 unsigned HOST_WIDE_INT inner_mask;
6929 /* Select the mask of the bits we need for the shift operand. */
6930 inner_mask = mask << INTVAL (XEXP (x, 1));
6932 /* We can only change the mode of the shift if we can do arithmetic
6933 in the mode of the shift and INNER_MASK is no wider than the
6934 width of X's mode. */
6935 if ((inner_mask & ~GET_MODE_MASK (GET_MODE (x))) != 0)
6936 op_mode = GET_MODE (x);
6938 inner = force_to_mode (inner, op_mode, inner_mask, next_select);
6940 if (GET_MODE (x) != op_mode || inner != XEXP (x, 0))
6941 x = simplify_gen_binary (LSHIFTRT, op_mode, inner, XEXP (x, 1));
6944 /* If we have (and (lshiftrt FOO C1) C2) where the combination of the
6945 shift and AND produces only copies of the sign bit (C2 is one less
6946 than a power of two), we can do this with just a shift. */
6948 if (GET_CODE (x) == LSHIFTRT
6949 && GET_CODE (XEXP (x, 1)) == CONST_INT
6950 /* The shift puts one of the sign bit copies in the least significant
6952 && ((INTVAL (XEXP (x, 1))
6953 + num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0))))
6954 >= GET_MODE_BITSIZE (GET_MODE (x)))
6955 && exact_log2 (mask + 1) >= 0
6956 /* Number of bits left after the shift must be more than the mask
6958 && ((INTVAL (XEXP (x, 1)) + exact_log2 (mask + 1))
6959 <= GET_MODE_BITSIZE (GET_MODE (x)))
6960 /* Must be more sign bit copies than the mask needs. */
6961 && ((int) num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
6962 >= exact_log2 (mask + 1)))
6963 x = simplify_gen_binary (LSHIFTRT, GET_MODE (x), XEXP (x, 0),
6964 GEN_INT (GET_MODE_BITSIZE (GET_MODE (x))
6965 - exact_log2 (mask + 1)));
6970 /* If we are just looking for the sign bit, we don't need this shift at
6971 all, even if it has a variable count. */
6972 if (GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
6973 && (mask == ((unsigned HOST_WIDE_INT) 1
6974 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
6975 return force_to_mode (XEXP (x, 0), mode, mask, next_select);
6977 /* If this is a shift by a constant, get a mask that contains those bits
6978 that are not copies of the sign bit. We then have two cases: If
6979 MASK only includes those bits, this can be a logical shift, which may
6980 allow simplifications. If MASK is a single-bit field not within
6981 those bits, we are requesting a copy of the sign bit and hence can
6982 shift the sign bit to the appropriate location. */
6984 if (GET_CODE (XEXP (x, 1)) == CONST_INT && INTVAL (XEXP (x, 1)) >= 0
6985 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT)
6989 /* If the considered data is wider than HOST_WIDE_INT, we can't
6990 represent a mask for all its bits in a single scalar.
6991 But we only care about the lower bits, so calculate these. */
6993 if (GET_MODE_BITSIZE (GET_MODE (x)) > HOST_BITS_PER_WIDE_INT)
6995 nonzero = ~(HOST_WIDE_INT) 0;
6997 /* GET_MODE_BITSIZE (GET_MODE (x)) - INTVAL (XEXP (x, 1))
6998 is the number of bits a full-width mask would have set.
6999 We need only shift if these are fewer than nonzero can
7000 hold. If not, we must keep all bits set in nonzero. */
7002 if (GET_MODE_BITSIZE (GET_MODE (x)) - INTVAL (XEXP (x, 1))
7003 < HOST_BITS_PER_WIDE_INT)
7004 nonzero >>= INTVAL (XEXP (x, 1))
7005 + HOST_BITS_PER_WIDE_INT
7006 - GET_MODE_BITSIZE (GET_MODE (x)) ;
7010 nonzero = GET_MODE_MASK (GET_MODE (x));
7011 nonzero >>= INTVAL (XEXP (x, 1));
7014 if ((mask & ~nonzero) == 0
7015 || (i = exact_log2 (mask)) >= 0)
7017 x = simplify_shift_const
7018 (x, LSHIFTRT, GET_MODE (x), XEXP (x, 0),
7019 i < 0 ? INTVAL (XEXP (x, 1))
7020 : GET_MODE_BITSIZE (GET_MODE (x)) - 1 - i);
7022 if (GET_CODE (x) != ASHIFTRT)
7023 return force_to_mode (x, mode, mask, next_select);
7027 /* If MASK is 1, convert this to an LSHIFTRT. This can be done
7028 even if the shift count isn't a constant. */
7030 x = simplify_gen_binary (LSHIFTRT, GET_MODE (x),
7031 XEXP (x, 0), XEXP (x, 1));
7035 /* If this is a zero- or sign-extension operation that just affects bits
7036 we don't care about, remove it. Be sure the call above returned
7037 something that is still a shift. */
7039 if ((GET_CODE (x) == LSHIFTRT || GET_CODE (x) == ASHIFTRT)
7040 && GET_CODE (XEXP (x, 1)) == CONST_INT
7041 && INTVAL (XEXP (x, 1)) >= 0
7042 && (INTVAL (XEXP (x, 1))
7043 <= GET_MODE_BITSIZE (GET_MODE (x)) - (floor_log2 (mask) + 1))
7044 && GET_CODE (XEXP (x, 0)) == ASHIFT
7045 && XEXP (XEXP (x, 0), 1) == XEXP (x, 1))
7046 return force_to_mode (XEXP (XEXP (x, 0), 0), mode, mask,
7053 /* If the shift count is constant and we can do computations
7054 in the mode of X, compute where the bits we care about are.
7055 Otherwise, we can't do anything. Don't change the mode of
7056 the shift or propagate MODE into the shift, though. */
7057 if (GET_CODE (XEXP (x, 1)) == CONST_INT
7058 && INTVAL (XEXP (x, 1)) >= 0)
7060 temp = simplify_binary_operation (code == ROTATE ? ROTATERT : ROTATE,
7061 GET_MODE (x), GEN_INT (mask),
7063 if (temp && GET_CODE (temp) == CONST_INT)
7065 force_to_mode (XEXP (x, 0), GET_MODE (x),
7066 INTVAL (temp), next_select));
7071 /* If we just want the low-order bit, the NEG isn't needed since it
7072 won't change the low-order bit. */
7074 return force_to_mode (XEXP (x, 0), mode, mask, just_select);
7076 /* We need any bits less significant than the most significant bit in
7077 MASK since carries from those bits will affect the bits we are
7083 /* (not FOO) is (xor FOO CONST), so if FOO is an LSHIFTRT, we can do the
7084 same as the XOR case above. Ensure that the constant we form is not
7085 wider than the mode of X. */
7087 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
7088 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
7089 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
7090 && (INTVAL (XEXP (XEXP (x, 0), 1)) + floor_log2 (mask)
7091 < GET_MODE_BITSIZE (GET_MODE (x)))
7092 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT)
7094 temp = gen_int_mode (mask << INTVAL (XEXP (XEXP (x, 0), 1)),
7096 temp = simplify_gen_binary (XOR, GET_MODE (x),
7097 XEXP (XEXP (x, 0), 0), temp);
7098 x = simplify_gen_binary (LSHIFTRT, GET_MODE (x),
7099 temp, XEXP (XEXP (x, 0), 1));
7101 return force_to_mode (x, mode, mask, next_select);
7104 /* (and (not FOO) CONST) is (not (or FOO (not CONST))), so we must
7105 use the full mask inside the NOT. */
7109 op0 = gen_lowpart (op_mode,
7110 force_to_mode (XEXP (x, 0), mode, mask,
7112 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0))
7113 x = simplify_gen_unary (code, op_mode, op0, op_mode);
7117 /* (and (ne FOO 0) CONST) can be (and FOO CONST) if CONST is included
7118 in STORE_FLAG_VALUE and FOO has a single bit that might be nonzero,
7119 which is equal to STORE_FLAG_VALUE. */
7120 if ((mask & ~STORE_FLAG_VALUE) == 0 && XEXP (x, 1) == const0_rtx
7121 && GET_MODE (XEXP (x, 0)) == mode
7122 && exact_log2 (nonzero_bits (XEXP (x, 0), mode)) >= 0
7123 && (nonzero_bits (XEXP (x, 0), mode)
7124 == (unsigned HOST_WIDE_INT) STORE_FLAG_VALUE))
7125 return force_to_mode (XEXP (x, 0), mode, mask, next_select);
7130 /* We have no way of knowing if the IF_THEN_ELSE can itself be
7131 written in a narrower mode. We play it safe and do not do so. */
7134 gen_lowpart (GET_MODE (x), force_to_mode (XEXP (x, 1), mode,
7135 mask, next_select)));
7137 gen_lowpart (GET_MODE (x), force_to_mode (XEXP (x, 2), mode,
7138 mask, next_select)));
7145 /* Ensure we return a value of the proper mode. */
7146 return gen_lowpart (mode, x);
7149 /* Return nonzero if X is an expression that has one of two values depending on
7150 whether some other value is zero or nonzero. In that case, we return the
7151 value that is being tested, *PTRUE is set to the value if the rtx being
7152 returned has a nonzero value, and *PFALSE is set to the other alternative.
7154 If we return zero, we set *PTRUE and *PFALSE to X. */
7157 if_then_else_cond (rtx x, rtx *ptrue, rtx *pfalse)
7159 enum machine_mode mode = GET_MODE (x);
7160 enum rtx_code code = GET_CODE (x);
7161 rtx cond0, cond1, true0, true1, false0, false1;
7162 unsigned HOST_WIDE_INT nz;
7164 /* If we are comparing a value against zero, we are done. */
7165 if ((code == NE || code == EQ)
7166 && XEXP (x, 1) == const0_rtx)
7168 *ptrue = (code == NE) ? const_true_rtx : const0_rtx;
7169 *pfalse = (code == NE) ? const0_rtx : const_true_rtx;
7173 /* If this is a unary operation whose operand has one of two values, apply
7174 our opcode to compute those values. */
7175 else if (UNARY_P (x)
7176 && (cond0 = if_then_else_cond (XEXP (x, 0), &true0, &false0)) != 0)
7178 *ptrue = simplify_gen_unary (code, mode, true0, GET_MODE (XEXP (x, 0)));
7179 *pfalse = simplify_gen_unary (code, mode, false0,
7180 GET_MODE (XEXP (x, 0)));
7184 /* If this is a COMPARE, do nothing, since the IF_THEN_ELSE we would
7185 make can't possibly match and would suppress other optimizations. */
7186 else if (code == COMPARE)
7189 /* If this is a binary operation, see if either side has only one of two
7190 values. If either one does or if both do and they are conditional on
7191 the same value, compute the new true and false values. */
7192 else if (BINARY_P (x))
7194 cond0 = if_then_else_cond (XEXP (x, 0), &true0, &false0);
7195 cond1 = if_then_else_cond (XEXP (x, 1), &true1, &false1);
7197 if ((cond0 != 0 || cond1 != 0)
7198 && ! (cond0 != 0 && cond1 != 0 && ! rtx_equal_p (cond0, cond1)))
7200 /* If if_then_else_cond returned zero, then true/false are the
7201 same rtl. We must copy one of them to prevent invalid rtl
7204 true0 = copy_rtx (true0);
7205 else if (cond1 == 0)
7206 true1 = copy_rtx (true1);
7208 if (COMPARISON_P (x))
7210 *ptrue = simplify_gen_relational (code, mode, VOIDmode,
7212 *pfalse = simplify_gen_relational (code, mode, VOIDmode,
7217 *ptrue = simplify_gen_binary (code, mode, true0, true1);
7218 *pfalse = simplify_gen_binary (code, mode, false0, false1);
7221 return cond0 ? cond0 : cond1;
7224 /* See if we have PLUS, IOR, XOR, MINUS or UMAX, where one of the
7225 operands is zero when the other is nonzero, and vice-versa,
7226 and STORE_FLAG_VALUE is 1 or -1. */
7228 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
7229 && (code == PLUS || code == IOR || code == XOR || code == MINUS
7231 && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT)
7233 rtx op0 = XEXP (XEXP (x, 0), 1);
7234 rtx op1 = XEXP (XEXP (x, 1), 1);
7236 cond0 = XEXP (XEXP (x, 0), 0);
7237 cond1 = XEXP (XEXP (x, 1), 0);
7239 if (COMPARISON_P (cond0)
7240 && COMPARISON_P (cond1)
7241 && ((GET_CODE (cond0) == reversed_comparison_code (cond1, NULL)
7242 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0))
7243 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1)))
7244 || ((swap_condition (GET_CODE (cond0))
7245 == reversed_comparison_code (cond1, NULL))
7246 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1))
7247 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0))))
7248 && ! side_effects_p (x))
7250 *ptrue = simplify_gen_binary (MULT, mode, op0, const_true_rtx);
7251 *pfalse = simplify_gen_binary (MULT, mode,
7253 ? simplify_gen_unary (NEG, mode,
7261 /* Similarly for MULT, AND and UMIN, except that for these the result
7263 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
7264 && (code == MULT || code == AND || code == UMIN)
7265 && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT)
7267 cond0 = XEXP (XEXP (x, 0), 0);
7268 cond1 = XEXP (XEXP (x, 1), 0);
7270 if (COMPARISON_P (cond0)
7271 && COMPARISON_P (cond1)
7272 && ((GET_CODE (cond0) == reversed_comparison_code (cond1, NULL)
7273 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0))
7274 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1)))
7275 || ((swap_condition (GET_CODE (cond0))
7276 == reversed_comparison_code (cond1, NULL))
7277 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1))
7278 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0))))
7279 && ! side_effects_p (x))
7281 *ptrue = *pfalse = const0_rtx;
7287 else if (code == IF_THEN_ELSE)
7289 /* If we have IF_THEN_ELSE already, extract the condition and
7290 canonicalize it if it is NE or EQ. */
7291 cond0 = XEXP (x, 0);
7292 *ptrue = XEXP (x, 1), *pfalse = XEXP (x, 2);
7293 if (GET_CODE (cond0) == NE && XEXP (cond0, 1) == const0_rtx)
7294 return XEXP (cond0, 0);
7295 else if (GET_CODE (cond0) == EQ && XEXP (cond0, 1) == const0_rtx)
7297 *ptrue = XEXP (x, 2), *pfalse = XEXP (x, 1);
7298 return XEXP (cond0, 0);
7304 /* If X is a SUBREG, we can narrow both the true and false values
7305 if the inner expression, if there is a condition. */
7306 else if (code == SUBREG
7307 && 0 != (cond0 = if_then_else_cond (SUBREG_REG (x),
7310 true0 = simplify_gen_subreg (mode, true0,
7311 GET_MODE (SUBREG_REG (x)), SUBREG_BYTE (x));
7312 false0 = simplify_gen_subreg (mode, false0,
7313 GET_MODE (SUBREG_REG (x)), SUBREG_BYTE (x));
7314 if (true0 && false0)
7322 /* If X is a constant, this isn't special and will cause confusions
7323 if we treat it as such. Likewise if it is equivalent to a constant. */
7324 else if (CONSTANT_P (x)
7325 || ((cond0 = get_last_value (x)) != 0 && CONSTANT_P (cond0)))
7328 /* If we're in BImode, canonicalize on 0 and STORE_FLAG_VALUE, as that
7329 will be least confusing to the rest of the compiler. */
7330 else if (mode == BImode)
7332 *ptrue = GEN_INT (STORE_FLAG_VALUE), *pfalse = const0_rtx;
7336 /* If X is known to be either 0 or -1, those are the true and
7337 false values when testing X. */
7338 else if (x == constm1_rtx || x == const0_rtx
7339 || (mode != VOIDmode
7340 && num_sign_bit_copies (x, mode) == GET_MODE_BITSIZE (mode)))
7342 *ptrue = constm1_rtx, *pfalse = const0_rtx;
7346 /* Likewise for 0 or a single bit. */
7347 else if (SCALAR_INT_MODE_P (mode)
7348 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
7349 && exact_log2 (nz = nonzero_bits (x, mode)) >= 0)
7351 *ptrue = gen_int_mode (nz, mode), *pfalse = const0_rtx;
7355 /* Otherwise fail; show no condition with true and false values the same. */
7356 *ptrue = *pfalse = x;
7360 /* Return the value of expression X given the fact that condition COND
7361 is known to be true when applied to REG as its first operand and VAL
7362 as its second. X is known to not be shared and so can be modified in
7365 We only handle the simplest cases, and specifically those cases that
7366 arise with IF_THEN_ELSE expressions. */
7369 known_cond (rtx x, enum rtx_code cond, rtx reg, rtx val)
7371 enum rtx_code code = GET_CODE (x);
7376 if (side_effects_p (x))
7379 /* If either operand of the condition is a floating point value,
7380 then we have to avoid collapsing an EQ comparison. */
7382 && rtx_equal_p (x, reg)
7383 && ! FLOAT_MODE_P (GET_MODE (x))
7384 && ! FLOAT_MODE_P (GET_MODE (val)))
7387 if (cond == UNEQ && rtx_equal_p (x, reg))
7390 /* If X is (abs REG) and we know something about REG's relationship
7391 with zero, we may be able to simplify this. */
7393 if (code == ABS && rtx_equal_p (XEXP (x, 0), reg) && val == const0_rtx)
7396 case GE: case GT: case EQ:
7399 return simplify_gen_unary (NEG, GET_MODE (XEXP (x, 0)),
7401 GET_MODE (XEXP (x, 0)));
7406 /* The only other cases we handle are MIN, MAX, and comparisons if the
7407 operands are the same as REG and VAL. */
7409 else if (COMPARISON_P (x) || COMMUTATIVE_ARITH_P (x))
7411 if (rtx_equal_p (XEXP (x, 0), val))
7412 cond = swap_condition (cond), temp = val, val = reg, reg = temp;
7414 if (rtx_equal_p (XEXP (x, 0), reg) && rtx_equal_p (XEXP (x, 1), val))
7416 if (COMPARISON_P (x))
7418 if (comparison_dominates_p (cond, code))
7419 return const_true_rtx;
7421 code = reversed_comparison_code (x, NULL);
7423 && comparison_dominates_p (cond, code))
7428 else if (code == SMAX || code == SMIN
7429 || code == UMIN || code == UMAX)
7431 int unsignedp = (code == UMIN || code == UMAX);
7433 /* Do not reverse the condition when it is NE or EQ.
7434 This is because we cannot conclude anything about
7435 the value of 'SMAX (x, y)' when x is not equal to y,
7436 but we can when x equals y. */
7437 if ((code == SMAX || code == UMAX)
7438 && ! (cond == EQ || cond == NE))
7439 cond = reverse_condition (cond);
7444 return unsignedp ? x : XEXP (x, 1);
7446 return unsignedp ? x : XEXP (x, 0);
7448 return unsignedp ? XEXP (x, 1) : x;
7450 return unsignedp ? XEXP (x, 0) : x;
7457 else if (code == SUBREG)
7459 enum machine_mode inner_mode = GET_MODE (SUBREG_REG (x));
7460 rtx new, r = known_cond (SUBREG_REG (x), cond, reg, val);
7462 if (SUBREG_REG (x) != r)
7464 /* We must simplify subreg here, before we lose track of the
7465 original inner_mode. */
7466 new = simplify_subreg (GET_MODE (x), r,
7467 inner_mode, SUBREG_BYTE (x));
7471 SUBST (SUBREG_REG (x), r);
7476 /* We don't have to handle SIGN_EXTEND here, because even in the
7477 case of replacing something with a modeless CONST_INT, a
7478 CONST_INT is already (supposed to be) a valid sign extension for
7479 its narrower mode, which implies it's already properly
7480 sign-extended for the wider mode. Now, for ZERO_EXTEND, the
7481 story is different. */
7482 else if (code == ZERO_EXTEND)
7484 enum machine_mode inner_mode = GET_MODE (XEXP (x, 0));
7485 rtx new, r = known_cond (XEXP (x, 0), cond, reg, val);
7487 if (XEXP (x, 0) != r)
7489 /* We must simplify the zero_extend here, before we lose
7490 track of the original inner_mode. */
7491 new = simplify_unary_operation (ZERO_EXTEND, GET_MODE (x),
7496 SUBST (XEXP (x, 0), r);
7502 fmt = GET_RTX_FORMAT (code);
7503 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
7506 SUBST (XEXP (x, i), known_cond (XEXP (x, i), cond, reg, val));
7507 else if (fmt[i] == 'E')
7508 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
7509 SUBST (XVECEXP (x, i, j), known_cond (XVECEXP (x, i, j),
7516 /* See if X and Y are equal for the purposes of seeing if we can rewrite an
7517 assignment as a field assignment. */
7520 rtx_equal_for_field_assignment_p (rtx x, rtx y)
7522 if (x == y || rtx_equal_p (x, y))
7525 if (x == 0 || y == 0 || GET_MODE (x) != GET_MODE (y))
7528 /* Check for a paradoxical SUBREG of a MEM compared with the MEM.
7529 Note that all SUBREGs of MEM are paradoxical; otherwise they
7530 would have been rewritten. */
7531 if (MEM_P (x) && GET_CODE (y) == SUBREG
7532 && MEM_P (SUBREG_REG (y))
7533 && rtx_equal_p (SUBREG_REG (y),
7534 gen_lowpart (GET_MODE (SUBREG_REG (y)), x)))
7537 if (MEM_P (y) && GET_CODE (x) == SUBREG
7538 && MEM_P (SUBREG_REG (x))
7539 && rtx_equal_p (SUBREG_REG (x),
7540 gen_lowpart (GET_MODE (SUBREG_REG (x)), y)))
7543 /* We used to see if get_last_value of X and Y were the same but that's
7544 not correct. In one direction, we'll cause the assignment to have
7545 the wrong destination and in the case, we'll import a register into this
7546 insn that might have already have been dead. So fail if none of the
7547 above cases are true. */
7551 /* See if X, a SET operation, can be rewritten as a bit-field assignment.
7552 Return that assignment if so.
7554 We only handle the most common cases. */
7557 make_field_assignment (rtx x)
7559 rtx dest = SET_DEST (x);
7560 rtx src = SET_SRC (x);
7565 unsigned HOST_WIDE_INT len;
7567 enum machine_mode mode;
7569 /* If SRC was (and (not (ashift (const_int 1) POS)) DEST), this is
7570 a clear of a one-bit field. We will have changed it to
7571 (and (rotate (const_int -2) POS) DEST), so check for that. Also check
7574 if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == ROTATE
7575 && GET_CODE (XEXP (XEXP (src, 0), 0)) == CONST_INT
7576 && INTVAL (XEXP (XEXP (src, 0), 0)) == -2
7577 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
7579 assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1),
7582 return gen_rtx_SET (VOIDmode, assign, const0_rtx);
7586 if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == SUBREG
7587 && subreg_lowpart_p (XEXP (src, 0))
7588 && (GET_MODE_SIZE (GET_MODE (XEXP (src, 0)))
7589 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (src, 0)))))
7590 && GET_CODE (SUBREG_REG (XEXP (src, 0))) == ROTATE
7591 && GET_CODE (XEXP (SUBREG_REG (XEXP (src, 0)), 0)) == CONST_INT
7592 && INTVAL (XEXP (SUBREG_REG (XEXP (src, 0)), 0)) == -2
7593 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
7595 assign = make_extraction (VOIDmode, dest, 0,
7596 XEXP (SUBREG_REG (XEXP (src, 0)), 1),
7599 return gen_rtx_SET (VOIDmode, assign, const0_rtx);
7603 /* If SRC is (ior (ashift (const_int 1) POS) DEST), this is a set of a
7605 if (GET_CODE (src) == IOR && GET_CODE (XEXP (src, 0)) == ASHIFT
7606 && XEXP (XEXP (src, 0), 0) == const1_rtx
7607 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
7609 assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1),
7612 return gen_rtx_SET (VOIDmode, assign, const1_rtx);
7616 /* If DEST is already a field assignment, i.e. ZERO_EXTRACT, and the
7617 SRC is an AND with all bits of that field set, then we can discard
7619 if (GET_CODE (dest) == ZERO_EXTRACT
7620 && GET_CODE (XEXP (dest, 1)) == CONST_INT
7621 && GET_CODE (src) == AND
7622 && GET_CODE (XEXP (src, 1)) == CONST_INT)
7624 HOST_WIDE_INT width = INTVAL (XEXP (dest, 1));
7625 unsigned HOST_WIDE_INT and_mask = INTVAL (XEXP (src, 1));
7626 unsigned HOST_WIDE_INT ze_mask;
7628 if (width >= HOST_BITS_PER_WIDE_INT)
7631 ze_mask = ((unsigned HOST_WIDE_INT)1 << width) - 1;
7633 /* Complete overlap. We can remove the source AND. */
7634 if ((and_mask & ze_mask) == ze_mask)
7635 return gen_rtx_SET (VOIDmode, dest, XEXP (src, 0));
7637 /* Partial overlap. We can reduce the source AND. */
7638 if ((and_mask & ze_mask) != and_mask)
7640 mode = GET_MODE (src);
7641 src = gen_rtx_AND (mode, XEXP (src, 0),
7642 gen_int_mode (and_mask & ze_mask, mode));
7643 return gen_rtx_SET (VOIDmode, dest, src);
7647 /* The other case we handle is assignments into a constant-position
7648 field. They look like (ior/xor (and DEST C1) OTHER). If C1 represents
7649 a mask that has all one bits except for a group of zero bits and
7650 OTHER is known to have zeros where C1 has ones, this is such an
7651 assignment. Compute the position and length from C1. Shift OTHER
7652 to the appropriate position, force it to the required mode, and
7653 make the extraction. Check for the AND in both operands. */
7655 if (GET_CODE (src) != IOR && GET_CODE (src) != XOR)
7658 rhs = expand_compound_operation (XEXP (src, 0));
7659 lhs = expand_compound_operation (XEXP (src, 1));
7661 if (GET_CODE (rhs) == AND
7662 && GET_CODE (XEXP (rhs, 1)) == CONST_INT
7663 && rtx_equal_for_field_assignment_p (XEXP (rhs, 0), dest))
7664 c1 = INTVAL (XEXP (rhs, 1)), other = lhs;
7665 else if (GET_CODE (lhs) == AND
7666 && GET_CODE (XEXP (lhs, 1)) == CONST_INT
7667 && rtx_equal_for_field_assignment_p (XEXP (lhs, 0), dest))
7668 c1 = INTVAL (XEXP (lhs, 1)), other = rhs;
7672 pos = get_pos_from_mask ((~c1) & GET_MODE_MASK (GET_MODE (dest)), &len);
7673 if (pos < 0 || pos + len > GET_MODE_BITSIZE (GET_MODE (dest))
7674 || GET_MODE_BITSIZE (GET_MODE (dest)) > HOST_BITS_PER_WIDE_INT
7675 || (c1 & nonzero_bits (other, GET_MODE (dest))) != 0)
7678 assign = make_extraction (VOIDmode, dest, pos, NULL_RTX, len, 1, 1, 0);
7682 /* The mode to use for the source is the mode of the assignment, or of
7683 what is inside a possible STRICT_LOW_PART. */
7684 mode = (GET_CODE (assign) == STRICT_LOW_PART
7685 ? GET_MODE (XEXP (assign, 0)) : GET_MODE (assign));
7687 /* Shift OTHER right POS places and make it the source, restricting it
7688 to the proper length and mode. */
7690 src = canon_reg_for_combine (simplify_shift_const (NULL_RTX, LSHIFTRT,
7694 src = force_to_mode (src, mode,
7695 GET_MODE_BITSIZE (mode) >= HOST_BITS_PER_WIDE_INT
7696 ? ~(unsigned HOST_WIDE_INT) 0
7697 : ((unsigned HOST_WIDE_INT) 1 << len) - 1,
7700 /* If SRC is masked by an AND that does not make a difference in
7701 the value being stored, strip it. */
7702 if (GET_CODE (assign) == ZERO_EXTRACT
7703 && GET_CODE (XEXP (assign, 1)) == CONST_INT
7704 && INTVAL (XEXP (assign, 1)) < HOST_BITS_PER_WIDE_INT
7705 && GET_CODE (src) == AND
7706 && GET_CODE (XEXP (src, 1)) == CONST_INT
7707 && ((unsigned HOST_WIDE_INT) INTVAL (XEXP (src, 1))
7708 == ((unsigned HOST_WIDE_INT) 1 << INTVAL (XEXP (assign, 1))) - 1))
7709 src = XEXP (src, 0);
7711 return gen_rtx_SET (VOIDmode, assign, src);
7714 /* See if X is of the form (+ (* a c) (* b c)) and convert to (* (+ a b) c)
7718 apply_distributive_law (rtx x)
7720 enum rtx_code code = GET_CODE (x);
7721 enum rtx_code inner_code;
7722 rtx lhs, rhs, other;
7725 /* Distributivity is not true for floating point as it can change the
7726 value. So we don't do it unless -funsafe-math-optimizations. */
7727 if (FLOAT_MODE_P (GET_MODE (x))
7728 && ! flag_unsafe_math_optimizations)
7731 /* The outer operation can only be one of the following: */
7732 if (code != IOR && code != AND && code != XOR
7733 && code != PLUS && code != MINUS)
7739 /* If either operand is a primitive we can't do anything, so get out
7741 if (OBJECT_P (lhs) || OBJECT_P (rhs))
7744 lhs = expand_compound_operation (lhs);
7745 rhs = expand_compound_operation (rhs);
7746 inner_code = GET_CODE (lhs);
7747 if (inner_code != GET_CODE (rhs))
7750 /* See if the inner and outer operations distribute. */
7757 /* These all distribute except over PLUS. */
7758 if (code == PLUS || code == MINUS)
7763 if (code != PLUS && code != MINUS)
7768 /* This is also a multiply, so it distributes over everything. */
7772 /* Non-paradoxical SUBREGs distributes over all operations,
7773 provided the inner modes and byte offsets are the same, this
7774 is an extraction of a low-order part, we don't convert an fp
7775 operation to int or vice versa, this is not a vector mode,
7776 and we would not be converting a single-word operation into a
7777 multi-word operation. The latter test is not required, but
7778 it prevents generating unneeded multi-word operations. Some
7779 of the previous tests are redundant given the latter test,
7780 but are retained because they are required for correctness.
7782 We produce the result slightly differently in this case. */
7784 if (GET_MODE (SUBREG_REG (lhs)) != GET_MODE (SUBREG_REG (rhs))
7785 || SUBREG_BYTE (lhs) != SUBREG_BYTE (rhs)
7786 || ! subreg_lowpart_p (lhs)
7787 || (GET_MODE_CLASS (GET_MODE (lhs))
7788 != GET_MODE_CLASS (GET_MODE (SUBREG_REG (lhs))))
7789 || (GET_MODE_SIZE (GET_MODE (lhs))
7790 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs))))
7791 || VECTOR_MODE_P (GET_MODE (lhs))
7792 || GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs))) > UNITS_PER_WORD)
7795 tem = simplify_gen_binary (code, GET_MODE (SUBREG_REG (lhs)),
7796 SUBREG_REG (lhs), SUBREG_REG (rhs));
7797 return gen_lowpart (GET_MODE (x), tem);
7803 /* Set LHS and RHS to the inner operands (A and B in the example
7804 above) and set OTHER to the common operand (C in the example).
7805 There is only one way to do this unless the inner operation is
7807 if (COMMUTATIVE_ARITH_P (lhs)
7808 && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 0)))
7809 other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 1);
7810 else if (COMMUTATIVE_ARITH_P (lhs)
7811 && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 1)))
7812 other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 0);
7813 else if (COMMUTATIVE_ARITH_P (lhs)
7814 && rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 0)))
7815 other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 1);
7816 else if (rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 1)))
7817 other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 0);
7821 /* Form the new inner operation, seeing if it simplifies first. */
7822 tem = simplify_gen_binary (code, GET_MODE (x), lhs, rhs);
7824 /* There is one exception to the general way of distributing:
7825 (a | c) ^ (b | c) -> (a ^ b) & ~c */
7826 if (code == XOR && inner_code == IOR)
7829 other = simplify_gen_unary (NOT, GET_MODE (x), other, GET_MODE (x));
7832 /* We may be able to continuing distributing the result, so call
7833 ourselves recursively on the inner operation before forming the
7834 outer operation, which we return. */
7835 return simplify_gen_binary (inner_code, GET_MODE (x),
7836 apply_distributive_law (tem), other);
7839 /* See if X is of the form (* (+ A B) C), and if so convert to
7840 (+ (* A C) (* B C)) and try to simplify.
7842 Most of the time, this results in no change. However, if some of
7843 the operands are the same or inverses of each other, simplifications
7846 For example, (and (ior A B) (not B)) can occur as the result of
7847 expanding a bit field assignment. When we apply the distributive
7848 law to this, we get (ior (and (A (not B))) (and (B (not B)))),
7849 which then simplifies to (and (A (not B))).
7851 Note that no checks happen on the validity of applying the inverse
7852 distributive law. This is pointless since we can do it in the
7853 few places where this routine is called.
7855 N is the index of the term that is decomposed (the arithmetic operation,
7856 i.e. (+ A B) in the first example above). !N is the index of the term that
7857 is distributed, i.e. of C in the first example above. */
7859 distribute_and_simplify_rtx (rtx x, int n)
7861 enum machine_mode mode;
7862 enum rtx_code outer_code, inner_code;
7863 rtx decomposed, distributed, inner_op0, inner_op1, new_op0, new_op1, tmp;
7865 decomposed = XEXP (x, n);
7866 if (!ARITHMETIC_P (decomposed))
7869 mode = GET_MODE (x);
7870 outer_code = GET_CODE (x);
7871 distributed = XEXP (x, !n);
7873 inner_code = GET_CODE (decomposed);
7874 inner_op0 = XEXP (decomposed, 0);
7875 inner_op1 = XEXP (decomposed, 1);
7877 /* Special case (and (xor B C) (not A)), which is equivalent to
7878 (xor (ior A B) (ior A C)) */
7879 if (outer_code == AND && inner_code == XOR && GET_CODE (distributed) == NOT)
7881 distributed = XEXP (distributed, 0);
7887 /* Distribute the second term. */
7888 new_op0 = simplify_gen_binary (outer_code, mode, inner_op0, distributed);
7889 new_op1 = simplify_gen_binary (outer_code, mode, inner_op1, distributed);
7893 /* Distribute the first term. */
7894 new_op0 = simplify_gen_binary (outer_code, mode, distributed, inner_op0);
7895 new_op1 = simplify_gen_binary (outer_code, mode, distributed, inner_op1);
7898 tmp = apply_distributive_law (simplify_gen_binary (inner_code, mode,
7900 if (GET_CODE (tmp) != outer_code
7901 && rtx_cost (tmp, SET) < rtx_cost (x, SET))
7907 /* We have X, a logical `and' of VAROP with the constant CONSTOP, to be done
7910 Return an equivalent form, if different from X. Otherwise, return X. If
7911 X is zero, we are to always construct the equivalent form. */
7914 simplify_and_const_int (rtx x, enum machine_mode mode, rtx varop,
7915 unsigned HOST_WIDE_INT constop)
7917 unsigned HOST_WIDE_INT nonzero;
7920 /* Simplify VAROP knowing that we will be only looking at some of the
7923 Note by passing in CONSTOP, we guarantee that the bits not set in
7924 CONSTOP are not significant and will never be examined. We must
7925 ensure that is the case by explicitly masking out those bits
7926 before returning. */
7927 varop = force_to_mode (varop, mode, constop, 0);
7929 /* If VAROP is a CLOBBER, we will fail so return it. */
7930 if (GET_CODE (varop) == CLOBBER)
7933 /* If VAROP is a CONST_INT, then we need to apply the mask in CONSTOP
7934 to VAROP and return the new constant. */
7935 if (GET_CODE (varop) == CONST_INT)
7936 return gen_int_mode (INTVAL (varop) & constop, mode);
7938 /* See what bits may be nonzero in VAROP. Unlike the general case of
7939 a call to nonzero_bits, here we don't care about bits outside
7942 nonzero = nonzero_bits (varop, mode) & GET_MODE_MASK (mode);
7944 /* Turn off all bits in the constant that are known to already be zero.
7945 Thus, if the AND isn't needed at all, we will have CONSTOP == NONZERO_BITS
7946 which is tested below. */
7950 /* If we don't have any bits left, return zero. */
7954 /* If VAROP is a NEG of something known to be zero or 1 and CONSTOP is
7955 a power of two, we can replace this with an ASHIFT. */
7956 if (GET_CODE (varop) == NEG && nonzero_bits (XEXP (varop, 0), mode) == 1
7957 && (i = exact_log2 (constop)) >= 0)
7958 return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (varop, 0), i);
7960 /* If VAROP is an IOR or XOR, apply the AND to both branches of the IOR
7961 or XOR, then try to apply the distributive law. This may eliminate
7962 operations if either branch can be simplified because of the AND.
7963 It may also make some cases more complex, but those cases probably
7964 won't match a pattern either with or without this. */
7966 if (GET_CODE (varop) == IOR || GET_CODE (varop) == XOR)
7970 apply_distributive_law
7971 (simplify_gen_binary (GET_CODE (varop), GET_MODE (varop),
7972 simplify_and_const_int (NULL_RTX,
7976 simplify_and_const_int (NULL_RTX,
7981 /* If VAROP is PLUS, and the constant is a mask of low bits, distribute
7982 the AND and see if one of the operands simplifies to zero. If so, we
7983 may eliminate it. */
7985 if (GET_CODE (varop) == PLUS
7986 && exact_log2 (constop + 1) >= 0)
7990 o0 = simplify_and_const_int (NULL_RTX, mode, XEXP (varop, 0), constop);
7991 o1 = simplify_and_const_int (NULL_RTX, mode, XEXP (varop, 1), constop);
7992 if (o0 == const0_rtx)
7994 if (o1 == const0_rtx)
7998 /* Get VAROP in MODE. Try to get a SUBREG if not. Don't make a new SUBREG
7999 if we already had one (just check for the simplest cases). */
8000 if (x && GET_CODE (XEXP (x, 0)) == SUBREG
8001 && GET_MODE (XEXP (x, 0)) == mode
8002 && SUBREG_REG (XEXP (x, 0)) == varop)
8003 varop = XEXP (x, 0);
8005 varop = gen_lowpart (mode, varop);
8007 /* If we can't make the SUBREG, try to return what we were given. */
8008 if (GET_CODE (varop) == CLOBBER)
8009 return x ? x : varop;
8011 /* If we are only masking insignificant bits, return VAROP. */
8012 if (constop == nonzero)
8016 /* Otherwise, return an AND. */
8017 constop = trunc_int_for_mode (constop, mode);
8018 /* See how much, if any, of X we can use. */
8019 if (x == 0 || GET_CODE (x) != AND || GET_MODE (x) != mode)
8020 x = simplify_gen_binary (AND, mode, varop, GEN_INT (constop));
8024 if (GET_CODE (XEXP (x, 1)) != CONST_INT
8025 || (unsigned HOST_WIDE_INT) INTVAL (XEXP (x, 1)) != constop)
8026 SUBST (XEXP (x, 1), GEN_INT (constop));
8028 SUBST (XEXP (x, 0), varop);
8035 /* Given a REG, X, compute which bits in X can be nonzero.
8036 We don't care about bits outside of those defined in MODE.
8038 For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is
8039 a shift, AND, or zero_extract, we can do better. */
8042 reg_nonzero_bits_for_combine (rtx x, enum machine_mode mode,
8043 rtx known_x ATTRIBUTE_UNUSED,
8044 enum machine_mode known_mode ATTRIBUTE_UNUSED,
8045 unsigned HOST_WIDE_INT known_ret ATTRIBUTE_UNUSED,
8046 unsigned HOST_WIDE_INT *nonzero)
8050 /* If X is a register whose nonzero bits value is current, use it.
8051 Otherwise, if X is a register whose value we can find, use that
8052 value. Otherwise, use the previously-computed global nonzero bits
8053 for this register. */
8055 if (reg_stat[REGNO (x)].last_set_value != 0
8056 && (reg_stat[REGNO (x)].last_set_mode == mode
8057 || (GET_MODE_CLASS (reg_stat[REGNO (x)].last_set_mode) == MODE_INT
8058 && GET_MODE_CLASS (mode) == MODE_INT))
8059 && (reg_stat[REGNO (x)].last_set_label == label_tick
8060 || (REGNO (x) >= FIRST_PSEUDO_REGISTER
8061 && REG_N_SETS (REGNO (x)) == 1
8062 && ! REGNO_REG_SET_P
8063 (ENTRY_BLOCK_PTR->next_bb->il.rtl->global_live_at_start,
8065 && INSN_CUID (reg_stat[REGNO (x)].last_set) < subst_low_cuid)
8067 *nonzero &= reg_stat[REGNO (x)].last_set_nonzero_bits;
8071 tem = get_last_value (x);
8075 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
8076 /* If X is narrower than MODE and TEM is a non-negative
8077 constant that would appear negative in the mode of X,
8078 sign-extend it for use in reg_nonzero_bits because some
8079 machines (maybe most) will actually do the sign-extension
8080 and this is the conservative approach.
8082 ??? For 2.5, try to tighten up the MD files in this regard
8083 instead of this kludge. */
8085 if (GET_MODE_BITSIZE (GET_MODE (x)) < GET_MODE_BITSIZE (mode)
8086 && GET_CODE (tem) == CONST_INT
8088 && 0 != (INTVAL (tem)
8089 & ((HOST_WIDE_INT) 1
8090 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
8091 tem = GEN_INT (INTVAL (tem)
8092 | ((HOST_WIDE_INT) (-1)
8093 << GET_MODE_BITSIZE (GET_MODE (x))));
8097 else if (nonzero_sign_valid && reg_stat[REGNO (x)].nonzero_bits)
8099 unsigned HOST_WIDE_INT mask = reg_stat[REGNO (x)].nonzero_bits;
8101 if (GET_MODE_BITSIZE (GET_MODE (x)) < GET_MODE_BITSIZE (mode))
8102 /* We don't know anything about the upper bits. */
8103 mask |= GET_MODE_MASK (mode) ^ GET_MODE_MASK (GET_MODE (x));
8110 /* Return the number of bits at the high-order end of X that are known to
8111 be equal to the sign bit. X will be used in mode MODE; if MODE is
8112 VOIDmode, X will be used in its own mode. The returned value will always
8113 be between 1 and the number of bits in MODE. */
8116 reg_num_sign_bit_copies_for_combine (rtx x, enum machine_mode mode,
8117 rtx known_x ATTRIBUTE_UNUSED,
8118 enum machine_mode known_mode
8120 unsigned int known_ret ATTRIBUTE_UNUSED,
8121 unsigned int *result)
8125 if (reg_stat[REGNO (x)].last_set_value != 0
8126 && reg_stat[REGNO (x)].last_set_mode == mode
8127 && (reg_stat[REGNO (x)].last_set_label == label_tick
8128 || (REGNO (x) >= FIRST_PSEUDO_REGISTER
8129 && REG_N_SETS (REGNO (x)) == 1
8130 && ! REGNO_REG_SET_P
8131 (ENTRY_BLOCK_PTR->next_bb->il.rtl->global_live_at_start,
8133 && INSN_CUID (reg_stat[REGNO (x)].last_set) < subst_low_cuid)
8135 *result = reg_stat[REGNO (x)].last_set_sign_bit_copies;
8139 tem = get_last_value (x);
8143 if (nonzero_sign_valid && reg_stat[REGNO (x)].sign_bit_copies != 0
8144 && GET_MODE_BITSIZE (GET_MODE (x)) == GET_MODE_BITSIZE (mode))
8145 *result = reg_stat[REGNO (x)].sign_bit_copies;
8150 /* Return the number of "extended" bits there are in X, when interpreted
8151 as a quantity in MODE whose signedness is indicated by UNSIGNEDP. For
8152 unsigned quantities, this is the number of high-order zero bits.
8153 For signed quantities, this is the number of copies of the sign bit
8154 minus 1. In both case, this function returns the number of "spare"
8155 bits. For example, if two quantities for which this function returns
8156 at least 1 are added, the addition is known not to overflow.
8158 This function will always return 0 unless called during combine, which
8159 implies that it must be called from a define_split. */
8162 extended_count (rtx x, enum machine_mode mode, int unsignedp)
8164 if (nonzero_sign_valid == 0)
8168 ? (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
8169 ? (unsigned int) (GET_MODE_BITSIZE (mode) - 1
8170 - floor_log2 (nonzero_bits (x, mode)))
8172 : num_sign_bit_copies (x, mode) - 1);
8175 /* This function is called from `simplify_shift_const' to merge two
8176 outer operations. Specifically, we have already found that we need
8177 to perform operation *POP0 with constant *PCONST0 at the outermost
8178 position. We would now like to also perform OP1 with constant CONST1
8179 (with *POP0 being done last).
8181 Return 1 if we can do the operation and update *POP0 and *PCONST0 with
8182 the resulting operation. *PCOMP_P is set to 1 if we would need to
8183 complement the innermost operand, otherwise it is unchanged.
8185 MODE is the mode in which the operation will be done. No bits outside
8186 the width of this mode matter. It is assumed that the width of this mode
8187 is smaller than or equal to HOST_BITS_PER_WIDE_INT.
8189 If *POP0 or OP1 are UNKNOWN, it means no operation is required. Only NEG, PLUS,
8190 IOR, XOR, and AND are supported. We may set *POP0 to SET if the proper
8191 result is simply *PCONST0.
8193 If the resulting operation cannot be expressed as one operation, we
8194 return 0 and do not change *POP0, *PCONST0, and *PCOMP_P. */
8197 merge_outer_ops (enum rtx_code *pop0, HOST_WIDE_INT *pconst0, enum rtx_code op1, HOST_WIDE_INT const1, enum machine_mode mode, int *pcomp_p)
8199 enum rtx_code op0 = *pop0;
8200 HOST_WIDE_INT const0 = *pconst0;
8202 const0 &= GET_MODE_MASK (mode);
8203 const1 &= GET_MODE_MASK (mode);
8205 /* If OP0 is an AND, clear unimportant bits in CONST1. */
8209 /* If OP0 or OP1 is UNKNOWN, this is easy. Similarly if they are the same or
8212 if (op1 == UNKNOWN || op0 == SET)
8215 else if (op0 == UNKNOWN)
8216 op0 = op1, const0 = const1;
8218 else if (op0 == op1)
8242 /* Otherwise, if either is a PLUS or NEG, we can't do anything. */
8243 else if (op0 == PLUS || op1 == PLUS || op0 == NEG || op1 == NEG)
8246 /* If the two constants aren't the same, we can't do anything. The
8247 remaining six cases can all be done. */
8248 else if (const0 != const1)
8256 /* (a & b) | b == b */
8258 else /* op1 == XOR */
8259 /* (a ^ b) | b == a | b */
8265 /* (a & b) ^ b == (~a) & b */
8266 op0 = AND, *pcomp_p = 1;
8267 else /* op1 == IOR */
8268 /* (a | b) ^ b == a & ~b */
8269 op0 = AND, const0 = ~const0;
8274 /* (a | b) & b == b */
8276 else /* op1 == XOR */
8277 /* (a ^ b) & b) == (~a) & b */
8284 /* Check for NO-OP cases. */
8285 const0 &= GET_MODE_MASK (mode);
8287 && (op0 == IOR || op0 == XOR || op0 == PLUS))
8289 else if (const0 == 0 && op0 == AND)
8291 else if ((unsigned HOST_WIDE_INT) const0 == GET_MODE_MASK (mode)
8295 /* ??? Slightly redundant with the above mask, but not entirely.
8296 Moving this above means we'd have to sign-extend the mode mask
8297 for the final test. */
8298 const0 = trunc_int_for_mode (const0, mode);
8306 /* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift.
8307 The result of the shift is RESULT_MODE. X, if nonzero, is an expression
8308 that we started with.
8310 The shift is normally computed in the widest mode we find in VAROP, as
8311 long as it isn't a different number of words than RESULT_MODE. Exceptions
8312 are ASHIFTRT and ROTATE, which are always done in their original mode, */
8315 simplify_shift_const (rtx x, enum rtx_code code,
8316 enum machine_mode result_mode, rtx varop,
8319 enum rtx_code orig_code = code;
8322 enum machine_mode mode = result_mode;
8323 enum machine_mode shift_mode, tmode;
8324 unsigned int mode_words
8325 = (GET_MODE_SIZE (mode) + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD;
8326 /* We form (outer_op (code varop count) (outer_const)). */
8327 enum rtx_code outer_op = UNKNOWN;
8328 HOST_WIDE_INT outer_const = 0;
8330 int complement_p = 0;
8333 /* Make sure and truncate the "natural" shift on the way in. We don't
8334 want to do this inside the loop as it makes it more difficult to
8336 if (SHIFT_COUNT_TRUNCATED)
8337 orig_count &= GET_MODE_BITSIZE (mode) - 1;
8339 /* If we were given an invalid count, don't do anything except exactly
8340 what was requested. */
8342 if (orig_count < 0 || orig_count >= (int) GET_MODE_BITSIZE (mode))
8347 return gen_rtx_fmt_ee (code, mode, varop, GEN_INT (orig_count));
8352 /* Unless one of the branches of the `if' in this loop does a `continue',
8353 we will `break' the loop after the `if'. */
8357 /* If we have an operand of (clobber (const_int 0)), just return that
8359 if (GET_CODE (varop) == CLOBBER)
8362 /* If we discovered we had to complement VAROP, leave. Making a NOT
8363 here would cause an infinite loop. */
8367 /* Convert ROTATERT to ROTATE. */
8368 if (code == ROTATERT)
8370 unsigned int bitsize = GET_MODE_BITSIZE (result_mode);;
8372 if (VECTOR_MODE_P (result_mode))
8373 count = bitsize / GET_MODE_NUNITS (result_mode) - count;
8375 count = bitsize - count;
8378 /* We need to determine what mode we will do the shift in. If the
8379 shift is a right shift or a ROTATE, we must always do it in the mode
8380 it was originally done in. Otherwise, we can do it in MODE, the
8381 widest mode encountered. */
8383 = (code == ASHIFTRT || code == LSHIFTRT || code == ROTATE
8384 ? result_mode : mode);
8386 /* Handle cases where the count is greater than the size of the mode
8387 minus 1. For ASHIFT, use the size minus one as the count (this can
8388 occur when simplifying (lshiftrt (ashiftrt ..))). For rotates,
8389 take the count modulo the size. For other shifts, the result is
8392 Since these shifts are being produced by the compiler by combining
8393 multiple operations, each of which are defined, we know what the
8394 result is supposed to be. */
8396 if (count > (unsigned int) (GET_MODE_BITSIZE (shift_mode) - 1))
8398 if (code == ASHIFTRT)
8399 count = GET_MODE_BITSIZE (shift_mode) - 1;
8400 else if (code == ROTATE || code == ROTATERT)
8401 count %= GET_MODE_BITSIZE (shift_mode);
8404 /* We can't simply return zero because there may be an
8412 /* An arithmetic right shift of a quantity known to be -1 or 0
8414 if (code == ASHIFTRT
8415 && (num_sign_bit_copies (varop, shift_mode)
8416 == GET_MODE_BITSIZE (shift_mode)))
8422 /* If we are doing an arithmetic right shift and discarding all but
8423 the sign bit copies, this is equivalent to doing a shift by the
8424 bitsize minus one. Convert it into that shift because it will often
8425 allow other simplifications. */
8427 if (code == ASHIFTRT
8428 && (count + num_sign_bit_copies (varop, shift_mode)
8429 >= GET_MODE_BITSIZE (shift_mode)))
8430 count = GET_MODE_BITSIZE (shift_mode) - 1;
8432 /* We simplify the tests below and elsewhere by converting
8433 ASHIFTRT to LSHIFTRT if we know the sign bit is clear.
8434 `make_compound_operation' will convert it to an ASHIFTRT for
8435 those machines (such as VAX) that don't have an LSHIFTRT. */
8436 if (GET_MODE_BITSIZE (shift_mode) <= HOST_BITS_PER_WIDE_INT
8438 && ((nonzero_bits (varop, shift_mode)
8439 & ((HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (shift_mode) - 1)))
8443 if (code == LSHIFTRT
8444 && GET_MODE_BITSIZE (shift_mode) <= HOST_BITS_PER_WIDE_INT
8445 && !(nonzero_bits (varop, shift_mode) >> count))
8448 && GET_MODE_BITSIZE (shift_mode) <= HOST_BITS_PER_WIDE_INT
8449 && !((nonzero_bits (varop, shift_mode) << count)
8450 & GET_MODE_MASK (shift_mode)))
8453 switch (GET_CODE (varop))
8459 new = expand_compound_operation (varop);
8468 /* If we have (xshiftrt (mem ...) C) and C is MODE_WIDTH
8469 minus the width of a smaller mode, we can do this with a
8470 SIGN_EXTEND or ZERO_EXTEND from the narrower memory location. */
8471 if ((code == ASHIFTRT || code == LSHIFTRT)
8472 && ! mode_dependent_address_p (XEXP (varop, 0))
8473 && ! MEM_VOLATILE_P (varop)
8474 && (tmode = mode_for_size (GET_MODE_BITSIZE (mode) - count,
8475 MODE_INT, 1)) != BLKmode)
8477 new = adjust_address_nv (varop, tmode,
8478 BYTES_BIG_ENDIAN ? 0
8479 : count / BITS_PER_UNIT);
8481 varop = gen_rtx_fmt_e (code == ASHIFTRT ? SIGN_EXTEND
8482 : ZERO_EXTEND, mode, new);
8489 /* Similar to the case above, except that we can only do this if
8490 the resulting mode is the same as that of the underlying
8491 MEM and adjust the address depending on the *bits* endianness
8492 because of the way that bit-field extract insns are defined. */
8493 if ((code == ASHIFTRT || code == LSHIFTRT)
8494 && (tmode = mode_for_size (GET_MODE_BITSIZE (mode) - count,
8495 MODE_INT, 1)) != BLKmode
8496 && tmode == GET_MODE (XEXP (varop, 0)))
8498 if (BITS_BIG_ENDIAN)
8499 new = XEXP (varop, 0);
8502 new = copy_rtx (XEXP (varop, 0));
8503 SUBST (XEXP (new, 0),
8504 plus_constant (XEXP (new, 0),
8505 count / BITS_PER_UNIT));
8508 varop = gen_rtx_fmt_e (code == ASHIFTRT ? SIGN_EXTEND
8509 : ZERO_EXTEND, mode, new);
8516 /* If VAROP is a SUBREG, strip it as long as the inner operand has
8517 the same number of words as what we've seen so far. Then store
8518 the widest mode in MODE. */
8519 if (subreg_lowpart_p (varop)
8520 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop)))
8521 > GET_MODE_SIZE (GET_MODE (varop)))
8522 && (unsigned int) ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop)))
8523 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
8526 varop = SUBREG_REG (varop);
8527 if (GET_MODE_SIZE (GET_MODE (varop)) > GET_MODE_SIZE (mode))
8528 mode = GET_MODE (varop);
8534 /* Some machines use MULT instead of ASHIFT because MULT
8535 is cheaper. But it is still better on those machines to
8536 merge two shifts into one. */
8537 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
8538 && exact_log2 (INTVAL (XEXP (varop, 1))) >= 0)
8541 = simplify_gen_binary (ASHIFT, GET_MODE (varop),
8543 GEN_INT (exact_log2 (
8544 INTVAL (XEXP (varop, 1)))));
8550 /* Similar, for when divides are cheaper. */
8551 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
8552 && exact_log2 (INTVAL (XEXP (varop, 1))) >= 0)
8555 = simplify_gen_binary (LSHIFTRT, GET_MODE (varop),
8557 GEN_INT (exact_log2 (
8558 INTVAL (XEXP (varop, 1)))));
8564 /* If we are extracting just the sign bit of an arithmetic
8565 right shift, that shift is not needed. However, the sign
8566 bit of a wider mode may be different from what would be
8567 interpreted as the sign bit in a narrower mode, so, if
8568 the result is narrower, don't discard the shift. */
8569 if (code == LSHIFTRT
8570 && count == (unsigned int) (GET_MODE_BITSIZE (result_mode) - 1)
8571 && (GET_MODE_BITSIZE (result_mode)
8572 >= GET_MODE_BITSIZE (GET_MODE (varop))))
8574 varop = XEXP (varop, 0);
8578 /* ... fall through ... */
8583 /* Here we have two nested shifts. The result is usually the
8584 AND of a new shift with a mask. We compute the result below. */
8585 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
8586 && INTVAL (XEXP (varop, 1)) >= 0
8587 && INTVAL (XEXP (varop, 1)) < GET_MODE_BITSIZE (GET_MODE (varop))
8588 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
8589 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
8591 enum rtx_code first_code = GET_CODE (varop);
8592 unsigned int first_count = INTVAL (XEXP (varop, 1));
8593 unsigned HOST_WIDE_INT mask;
8596 /* We have one common special case. We can't do any merging if
8597 the inner code is an ASHIFTRT of a smaller mode. However, if
8598 we have (ashift:M1 (subreg:M1 (ashiftrt:M2 FOO C1) 0) C2)
8599 with C2 == GET_MODE_BITSIZE (M1) - GET_MODE_BITSIZE (M2),
8600 we can convert it to
8601 (ashiftrt:M1 (ashift:M1 (and:M1 (subreg:M1 FOO 0 C2) C3) C1).
8602 This simplifies certain SIGN_EXTEND operations. */
8603 if (code == ASHIFT && first_code == ASHIFTRT
8604 && count == (unsigned int)
8605 (GET_MODE_BITSIZE (result_mode)
8606 - GET_MODE_BITSIZE (GET_MODE (varop))))
8608 /* C3 has the low-order C1 bits zero. */
8610 mask = (GET_MODE_MASK (mode)
8611 & ~(((HOST_WIDE_INT) 1 << first_count) - 1));
8613 varop = simplify_and_const_int (NULL_RTX, result_mode,
8614 XEXP (varop, 0), mask);
8615 varop = simplify_shift_const (NULL_RTX, ASHIFT, result_mode,
8617 count = first_count;
8622 /* If this was (ashiftrt (ashift foo C1) C2) and FOO has more
8623 than C1 high-order bits equal to the sign bit, we can convert
8624 this to either an ASHIFT or an ASHIFTRT depending on the
8627 We cannot do this if VAROP's mode is not SHIFT_MODE. */
8629 if (code == ASHIFTRT && first_code == ASHIFT
8630 && GET_MODE (varop) == shift_mode
8631 && (num_sign_bit_copies (XEXP (varop, 0), shift_mode)
8634 varop = XEXP (varop, 0);
8636 signed_count = count - first_count;
8637 if (signed_count < 0)
8638 count = -signed_count, code = ASHIFT;
8640 count = signed_count;
8645 /* There are some cases we can't do. If CODE is ASHIFTRT,
8646 we can only do this if FIRST_CODE is also ASHIFTRT.
8648 We can't do the case when CODE is ROTATE and FIRST_CODE is
8651 If the mode of this shift is not the mode of the outer shift,
8652 we can't do this if either shift is a right shift or ROTATE.
8654 Finally, we can't do any of these if the mode is too wide
8655 unless the codes are the same.
8657 Handle the case where the shift codes are the same
8660 if (code == first_code)
8662 if (GET_MODE (varop) != result_mode
8663 && (code == ASHIFTRT || code == LSHIFTRT
8667 count += first_count;
8668 varop = XEXP (varop, 0);
8672 if (code == ASHIFTRT
8673 || (code == ROTATE && first_code == ASHIFTRT)
8674 || GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT
8675 || (GET_MODE (varop) != result_mode
8676 && (first_code == ASHIFTRT || first_code == LSHIFTRT
8677 || first_code == ROTATE
8678 || code == ROTATE)))
8681 /* To compute the mask to apply after the shift, shift the
8682 nonzero bits of the inner shift the same way the
8683 outer shift will. */
8685 mask_rtx = GEN_INT (nonzero_bits (varop, GET_MODE (varop)));
8688 = simplify_binary_operation (code, result_mode, mask_rtx,
8691 /* Give up if we can't compute an outer operation to use. */
8693 || GET_CODE (mask_rtx) != CONST_INT
8694 || ! merge_outer_ops (&outer_op, &outer_const, AND,
8696 result_mode, &complement_p))
8699 /* If the shifts are in the same direction, we add the
8700 counts. Otherwise, we subtract them. */
8701 signed_count = count;
8702 if ((code == ASHIFTRT || code == LSHIFTRT)
8703 == (first_code == ASHIFTRT || first_code == LSHIFTRT))
8704 signed_count += first_count;
8706 signed_count -= first_count;
8708 /* If COUNT is positive, the new shift is usually CODE,
8709 except for the two exceptions below, in which case it is
8710 FIRST_CODE. If the count is negative, FIRST_CODE should
8712 if (signed_count > 0
8713 && ((first_code == ROTATE && code == ASHIFT)
8714 || (first_code == ASHIFTRT && code == LSHIFTRT)))
8715 code = first_code, count = signed_count;
8716 else if (signed_count < 0)
8717 code = first_code, count = -signed_count;
8719 count = signed_count;
8721 varop = XEXP (varop, 0);
8725 /* If we have (A << B << C) for any shift, we can convert this to
8726 (A << C << B). This wins if A is a constant. Only try this if
8727 B is not a constant. */
8729 else if (GET_CODE (varop) == code
8730 && GET_CODE (XEXP (varop, 1)) != CONST_INT
8732 = simplify_binary_operation (code, mode,
8736 varop = gen_rtx_fmt_ee (code, mode, new, XEXP (varop, 1));
8743 /* Make this fit the case below. */
8744 varop = gen_rtx_XOR (mode, XEXP (varop, 0),
8745 GEN_INT (GET_MODE_MASK (mode)));
8751 /* If we have (xshiftrt (ior (plus X (const_int -1)) X) C)
8752 with C the size of VAROP - 1 and the shift is logical if
8753 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
8754 we have an (le X 0) operation. If we have an arithmetic shift
8755 and STORE_FLAG_VALUE is 1 or we have a logical shift with
8756 STORE_FLAG_VALUE of -1, we have a (neg (le X 0)) operation. */
8758 if (GET_CODE (varop) == IOR && GET_CODE (XEXP (varop, 0)) == PLUS
8759 && XEXP (XEXP (varop, 0), 1) == constm1_rtx
8760 && (STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
8761 && (code == LSHIFTRT || code == ASHIFTRT)
8762 && count == (unsigned int)
8763 (GET_MODE_BITSIZE (GET_MODE (varop)) - 1)
8764 && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
8767 varop = gen_rtx_LE (GET_MODE (varop), XEXP (varop, 1),
8770 if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
8771 varop = gen_rtx_NEG (GET_MODE (varop), varop);
8776 /* If we have (shift (logical)), move the logical to the outside
8777 to allow it to possibly combine with another logical and the
8778 shift to combine with another shift. This also canonicalizes to
8779 what a ZERO_EXTRACT looks like. Also, some machines have
8780 (and (shift)) insns. */
8782 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
8783 /* We can't do this if we have (ashiftrt (xor)) and the
8784 constant has its sign bit set in shift_mode. */
8785 && !(code == ASHIFTRT && GET_CODE (varop) == XOR
8786 && 0 > trunc_int_for_mode (INTVAL (XEXP (varop, 1)),
8788 && (new = simplify_binary_operation (code, result_mode,
8790 GEN_INT (count))) != 0
8791 && GET_CODE (new) == CONST_INT
8792 && merge_outer_ops (&outer_op, &outer_const, GET_CODE (varop),
8793 INTVAL (new), result_mode, &complement_p))
8795 varop = XEXP (varop, 0);
8799 /* If we can't do that, try to simplify the shift in each arm of the
8800 logical expression, make a new logical expression, and apply
8801 the inverse distributive law. This also can't be done
8802 for some (ashiftrt (xor)). */
8803 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
8804 && !(code == ASHIFTRT && GET_CODE (varop) == XOR
8805 && 0 > trunc_int_for_mode (INTVAL (XEXP (varop, 1)),
8808 rtx lhs = simplify_shift_const (NULL_RTX, code, shift_mode,
8809 XEXP (varop, 0), count);
8810 rtx rhs = simplify_shift_const (NULL_RTX, code, shift_mode,
8811 XEXP (varop, 1), count);
8813 varop = simplify_gen_binary (GET_CODE (varop), shift_mode,
8815 varop = apply_distributive_law (varop);
8823 /* Convert (lshiftrt (eq FOO 0) C) to (xor FOO 1) if STORE_FLAG_VALUE
8824 says that the sign bit can be tested, FOO has mode MODE, C is
8825 GET_MODE_BITSIZE (MODE) - 1, and FOO has only its low-order bit
8826 that may be nonzero. */
8827 if (code == LSHIFTRT
8828 && XEXP (varop, 1) == const0_rtx
8829 && GET_MODE (XEXP (varop, 0)) == result_mode
8830 && count == (unsigned int) (GET_MODE_BITSIZE (result_mode) - 1)
8831 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
8832 && ((STORE_FLAG_VALUE
8833 & ((HOST_WIDE_INT) 1
8834 < (GET_MODE_BITSIZE (result_mode) - 1))))
8835 && nonzero_bits (XEXP (varop, 0), result_mode) == 1
8836 && merge_outer_ops (&outer_op, &outer_const, XOR,
8837 (HOST_WIDE_INT) 1, result_mode,
8840 varop = XEXP (varop, 0);
8847 /* (lshiftrt (neg A) C) where A is either 0 or 1 and C is one less
8848 than the number of bits in the mode is equivalent to A. */
8849 if (code == LSHIFTRT
8850 && count == (unsigned int) (GET_MODE_BITSIZE (result_mode) - 1)
8851 && nonzero_bits (XEXP (varop, 0), result_mode) == 1)
8853 varop = XEXP (varop, 0);
8858 /* NEG commutes with ASHIFT since it is multiplication. Move the
8859 NEG outside to allow shifts to combine. */
8861 && merge_outer_ops (&outer_op, &outer_const, NEG,
8862 (HOST_WIDE_INT) 0, result_mode,
8865 varop = XEXP (varop, 0);
8871 /* (lshiftrt (plus A -1) C) where A is either 0 or 1 and C
8872 is one less than the number of bits in the mode is
8873 equivalent to (xor A 1). */
8874 if (code == LSHIFTRT
8875 && count == (unsigned int) (GET_MODE_BITSIZE (result_mode) - 1)
8876 && XEXP (varop, 1) == constm1_rtx
8877 && nonzero_bits (XEXP (varop, 0), result_mode) == 1
8878 && merge_outer_ops (&outer_op, &outer_const, XOR,
8879 (HOST_WIDE_INT) 1, result_mode,
8883 varop = XEXP (varop, 0);
8887 /* If we have (xshiftrt (plus FOO BAR) C), and the only bits
8888 that might be nonzero in BAR are those being shifted out and those
8889 bits are known zero in FOO, we can replace the PLUS with FOO.
8890 Similarly in the other operand order. This code occurs when
8891 we are computing the size of a variable-size array. */
8893 if ((code == ASHIFTRT || code == LSHIFTRT)
8894 && count < HOST_BITS_PER_WIDE_INT
8895 && nonzero_bits (XEXP (varop, 1), result_mode) >> count == 0
8896 && (nonzero_bits (XEXP (varop, 1), result_mode)
8897 & nonzero_bits (XEXP (varop, 0), result_mode)) == 0)
8899 varop = XEXP (varop, 0);
8902 else if ((code == ASHIFTRT || code == LSHIFTRT)
8903 && count < HOST_BITS_PER_WIDE_INT
8904 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
8905 && 0 == (nonzero_bits (XEXP (varop, 0), result_mode)
8907 && 0 == (nonzero_bits (XEXP (varop, 0), result_mode)
8908 & nonzero_bits (XEXP (varop, 1),
8911 varop = XEXP (varop, 1);
8915 /* (ashift (plus foo C) N) is (plus (ashift foo N) C'). */
8917 && GET_CODE (XEXP (varop, 1)) == CONST_INT
8918 && (new = simplify_binary_operation (ASHIFT, result_mode,
8920 GEN_INT (count))) != 0
8921 && GET_CODE (new) == CONST_INT
8922 && merge_outer_ops (&outer_op, &outer_const, PLUS,
8923 INTVAL (new), result_mode, &complement_p))
8925 varop = XEXP (varop, 0);
8929 /* Check for 'PLUS signbit', which is the canonical form of 'XOR
8930 signbit', and attempt to change the PLUS to an XOR and move it to
8931 the outer operation as is done above in the AND/IOR/XOR case
8932 leg for shift(logical). See details in logical handling above
8933 for reasoning in doing so. */
8934 if (code == LSHIFTRT
8935 && GET_CODE (XEXP (varop, 1)) == CONST_INT
8936 && mode_signbit_p (result_mode, XEXP (varop, 1))
8937 && (new = simplify_binary_operation (code, result_mode,
8939 GEN_INT (count))) != 0
8940 && GET_CODE (new) == CONST_INT
8941 && merge_outer_ops (&outer_op, &outer_const, XOR,
8942 INTVAL (new), result_mode, &complement_p))
8944 varop = XEXP (varop, 0);
8951 /* If we have (xshiftrt (minus (ashiftrt X C)) X) C)
8952 with C the size of VAROP - 1 and the shift is logical if
8953 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
8954 we have a (gt X 0) operation. If the shift is arithmetic with
8955 STORE_FLAG_VALUE of 1 or logical with STORE_FLAG_VALUE == -1,
8956 we have a (neg (gt X 0)) operation. */
8958 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
8959 && GET_CODE (XEXP (varop, 0)) == ASHIFTRT
8960 && count == (unsigned int)
8961 (GET_MODE_BITSIZE (GET_MODE (varop)) - 1)
8962 && (code == LSHIFTRT || code == ASHIFTRT)
8963 && GET_CODE (XEXP (XEXP (varop, 0), 1)) == CONST_INT
8964 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (XEXP (varop, 0), 1))
8966 && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
8969 varop = gen_rtx_GT (GET_MODE (varop), XEXP (varop, 1),
8972 if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
8973 varop = gen_rtx_NEG (GET_MODE (varop), varop);
8980 /* Change (lshiftrt (truncate (lshiftrt))) to (truncate (lshiftrt))
8981 if the truncate does not affect the value. */
8982 if (code == LSHIFTRT
8983 && GET_CODE (XEXP (varop, 0)) == LSHIFTRT
8984 && GET_CODE (XEXP (XEXP (varop, 0), 1)) == CONST_INT
8985 && (INTVAL (XEXP (XEXP (varop, 0), 1))
8986 >= (GET_MODE_BITSIZE (GET_MODE (XEXP (varop, 0)))
8987 - GET_MODE_BITSIZE (GET_MODE (varop)))))
8989 rtx varop_inner = XEXP (varop, 0);
8992 = gen_rtx_LSHIFTRT (GET_MODE (varop_inner),
8993 XEXP (varop_inner, 0),
8995 (count + INTVAL (XEXP (varop_inner, 1))));
8996 varop = gen_rtx_TRUNCATE (GET_MODE (varop), varop_inner);
9009 /* We need to determine what mode to do the shift in. If the shift is
9010 a right shift or ROTATE, we must always do it in the mode it was
9011 originally done in. Otherwise, we can do it in MODE, the widest mode
9012 encountered. The code we care about is that of the shift that will
9013 actually be done, not the shift that was originally requested. */
9015 = (code == ASHIFTRT || code == LSHIFTRT || code == ROTATE
9016 ? result_mode : mode);
9018 /* We have now finished analyzing the shift. The result should be
9019 a shift of type CODE with SHIFT_MODE shifting VAROP COUNT places. If
9020 OUTER_OP is non-UNKNOWN, it is an operation that needs to be applied
9021 to the result of the shift. OUTER_CONST is the relevant constant,
9022 but we must turn off all bits turned off in the shift.
9024 If we were passed a value for X, see if we can use any pieces of
9025 it. If not, make new rtx. */
9027 if (x && GET_RTX_CLASS (GET_CODE (x)) == RTX_BIN_ARITH
9028 && GET_CODE (XEXP (x, 1)) == CONST_INT
9029 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (x, 1)) == count)
9030 const_rtx = XEXP (x, 1);
9032 const_rtx = GEN_INT (count);
9034 if (x && GET_CODE (XEXP (x, 0)) == SUBREG
9035 && GET_MODE (XEXP (x, 0)) == shift_mode
9036 && SUBREG_REG (XEXP (x, 0)) == varop)
9037 varop = XEXP (x, 0);
9038 else if (GET_MODE (varop) != shift_mode)
9039 varop = gen_lowpart (shift_mode, varop);
9041 /* If we can't make the SUBREG, try to return what we were given. */
9042 if (GET_CODE (varop) == CLOBBER)
9043 return x ? x : varop;
9045 new = simplify_binary_operation (code, shift_mode, varop, const_rtx);
9049 x = gen_rtx_fmt_ee (code, shift_mode, varop, const_rtx);
9051 /* If we have an outer operation and we just made a shift, it is
9052 possible that we could have simplified the shift were it not
9053 for the outer operation. So try to do the simplification
9056 if (outer_op != UNKNOWN && GET_CODE (x) == code
9057 && GET_CODE (XEXP (x, 1)) == CONST_INT)
9058 x = simplify_shift_const (x, code, shift_mode, XEXP (x, 0),
9059 INTVAL (XEXP (x, 1)));
9061 /* If we were doing an LSHIFTRT in a wider mode than it was originally,
9062 turn off all the bits that the shift would have turned off. */
9063 if (orig_code == LSHIFTRT && result_mode != shift_mode)
9064 x = simplify_and_const_int (NULL_RTX, shift_mode, x,
9065 GET_MODE_MASK (result_mode) >> orig_count);
9067 /* Do the remainder of the processing in RESULT_MODE. */
9068 x = gen_lowpart (result_mode, x);
9070 /* If COMPLEMENT_P is set, we have to complement X before doing the outer
9073 x = simplify_gen_unary (NOT, result_mode, x, result_mode);
9075 if (outer_op != UNKNOWN)
9077 if (GET_MODE_BITSIZE (result_mode) < HOST_BITS_PER_WIDE_INT)
9078 outer_const = trunc_int_for_mode (outer_const, result_mode);
9080 if (outer_op == AND)
9081 x = simplify_and_const_int (NULL_RTX, result_mode, x, outer_const);
9082 else if (outer_op == SET)
9083 /* This means that we have determined that the result is
9084 equivalent to a constant. This should be rare. */
9085 x = GEN_INT (outer_const);
9086 else if (GET_RTX_CLASS (outer_op) == RTX_UNARY)
9087 x = simplify_gen_unary (outer_op, result_mode, x, result_mode);
9089 x = simplify_gen_binary (outer_op, result_mode, x,
9090 GEN_INT (outer_const));
9096 /* Like recog, but we receive the address of a pointer to a new pattern.
9097 We try to match the rtx that the pointer points to.
9098 If that fails, we may try to modify or replace the pattern,
9099 storing the replacement into the same pointer object.
9101 Modifications include deletion or addition of CLOBBERs.
9103 PNOTES is a pointer to a location where any REG_UNUSED notes added for
9104 the CLOBBERs are placed.
9106 The value is the final insn code from the pattern ultimately matched,
9110 recog_for_combine (rtx *pnewpat, rtx insn, rtx *pnotes)
9113 int insn_code_number;
9114 int num_clobbers_to_add = 0;
9117 rtx old_notes, old_pat;
9119 /* If PAT is a PARALLEL, check to see if it contains the CLOBBER
9120 we use to indicate that something didn't match. If we find such a
9121 thing, force rejection. */
9122 if (GET_CODE (pat) == PARALLEL)
9123 for (i = XVECLEN (pat, 0) - 1; i >= 0; i--)
9124 if (GET_CODE (XVECEXP (pat, 0, i)) == CLOBBER
9125 && XEXP (XVECEXP (pat, 0, i), 0) == const0_rtx)
9128 old_pat = PATTERN (insn);
9129 old_notes = REG_NOTES (insn);
9130 PATTERN (insn) = pat;
9131 REG_NOTES (insn) = 0;
9133 insn_code_number = recog (pat, insn, &num_clobbers_to_add);
9135 /* If it isn't, there is the possibility that we previously had an insn
9136 that clobbered some register as a side effect, but the combined
9137 insn doesn't need to do that. So try once more without the clobbers
9138 unless this represents an ASM insn. */
9140 if (insn_code_number < 0 && ! check_asm_operands (pat)
9141 && GET_CODE (pat) == PARALLEL)
9145 for (pos = 0, i = 0; i < XVECLEN (pat, 0); i++)
9146 if (GET_CODE (XVECEXP (pat, 0, i)) != CLOBBER)
9149 SUBST (XVECEXP (pat, 0, pos), XVECEXP (pat, 0, i));
9153 SUBST_INT (XVECLEN (pat, 0), pos);
9156 pat = XVECEXP (pat, 0, 0);
9158 PATTERN (insn) = pat;
9159 insn_code_number = recog (pat, insn, &num_clobbers_to_add);
9161 PATTERN (insn) = old_pat;
9162 REG_NOTES (insn) = old_notes;
9164 /* Recognize all noop sets, these will be killed by followup pass. */
9165 if (insn_code_number < 0 && GET_CODE (pat) == SET && set_noop_p (pat))
9166 insn_code_number = NOOP_MOVE_INSN_CODE, num_clobbers_to_add = 0;
9168 /* If we had any clobbers to add, make a new pattern than contains
9169 them. Then check to make sure that all of them are dead. */
9170 if (num_clobbers_to_add)
9172 rtx newpat = gen_rtx_PARALLEL (VOIDmode,
9173 rtvec_alloc (GET_CODE (pat) == PARALLEL
9175 + num_clobbers_to_add)
9176 : num_clobbers_to_add + 1));
9178 if (GET_CODE (pat) == PARALLEL)
9179 for (i = 0; i < XVECLEN (pat, 0); i++)
9180 XVECEXP (newpat, 0, i) = XVECEXP (pat, 0, i);
9182 XVECEXP (newpat, 0, 0) = pat;
9184 add_clobbers (newpat, insn_code_number);
9186 for (i = XVECLEN (newpat, 0) - num_clobbers_to_add;
9187 i < XVECLEN (newpat, 0); i++)
9189 if (REG_P (XEXP (XVECEXP (newpat, 0, i), 0))
9190 && ! reg_dead_at_p (XEXP (XVECEXP (newpat, 0, i), 0), insn))
9192 notes = gen_rtx_EXPR_LIST (REG_UNUSED,
9193 XEXP (XVECEXP (newpat, 0, i), 0), notes);
9201 return insn_code_number;
9204 /* Like gen_lowpart_general but for use by combine. In combine it
9205 is not possible to create any new pseudoregs. However, it is
9206 safe to create invalid memory addresses, because combine will
9207 try to recognize them and all they will do is make the combine
9210 If for some reason this cannot do its job, an rtx
9211 (clobber (const_int 0)) is returned.
9212 An insn containing that will not be recognized. */
9215 gen_lowpart_for_combine (enum machine_mode omode, rtx x)
9217 enum machine_mode imode = GET_MODE (x);
9218 unsigned int osize = GET_MODE_SIZE (omode);
9219 unsigned int isize = GET_MODE_SIZE (imode);
9225 /* Return identity if this is a CONST or symbolic reference. */
9227 && (GET_CODE (x) == CONST
9228 || GET_CODE (x) == SYMBOL_REF
9229 || GET_CODE (x) == LABEL_REF))
9232 /* We can only support MODE being wider than a word if X is a
9233 constant integer or has a mode the same size. */
9234 if (GET_MODE_SIZE (omode) > UNITS_PER_WORD
9235 && ! ((imode == VOIDmode
9236 && (GET_CODE (x) == CONST_INT
9237 || GET_CODE (x) == CONST_DOUBLE))
9241 /* X might be a paradoxical (subreg (mem)). In that case, gen_lowpart
9242 won't know what to do. So we will strip off the SUBREG here and
9243 process normally. */
9244 if (GET_CODE (x) == SUBREG && MEM_P (SUBREG_REG (x)))
9248 /* For use in case we fall down into the address adjustments
9249 further below, we need to adjust the known mode and size of
9250 x; imode and isize, since we just adjusted x. */
9251 imode = GET_MODE (x);
9256 isize = GET_MODE_SIZE (imode);
9259 result = gen_lowpart_common (omode, x);
9261 #ifdef CANNOT_CHANGE_MODE_CLASS
9262 if (result != 0 && GET_CODE (result) == SUBREG)
9263 record_subregs_of_mode (result);
9273 /* Refuse to work on a volatile memory ref or one with a mode-dependent
9275 if (MEM_VOLATILE_P (x) || mode_dependent_address_p (XEXP (x, 0)))
9278 /* If we want to refer to something bigger than the original memref,
9279 generate a paradoxical subreg instead. That will force a reload
9280 of the original memref X. */
9282 return gen_rtx_SUBREG (omode, x, 0);
9284 if (WORDS_BIG_ENDIAN)
9285 offset = MAX (isize, UNITS_PER_WORD) - MAX (osize, UNITS_PER_WORD);
9287 /* Adjust the address so that the address-after-the-data is
9289 if (BYTES_BIG_ENDIAN)
9290 offset -= MIN (UNITS_PER_WORD, osize) - MIN (UNITS_PER_WORD, isize);
9292 return adjust_address_nv (x, omode, offset);
9295 /* If X is a comparison operator, rewrite it in a new mode. This
9296 probably won't match, but may allow further simplifications. */
9297 else if (COMPARISON_P (x))
9298 return gen_rtx_fmt_ee (GET_CODE (x), omode, XEXP (x, 0), XEXP (x, 1));
9300 /* If we couldn't simplify X any other way, just enclose it in a
9301 SUBREG. Normally, this SUBREG won't match, but some patterns may
9302 include an explicit SUBREG or we may simplify it further in combine. */
9308 offset = subreg_lowpart_offset (omode, imode);
9309 if (imode == VOIDmode)
9311 imode = int_mode_for_mode (omode);
9312 x = gen_lowpart_common (imode, x);
9316 res = simplify_gen_subreg (omode, x, imode, offset);
9322 return gen_rtx_CLOBBER (imode, const0_rtx);
9325 /* Simplify a comparison between *POP0 and *POP1 where CODE is the
9326 comparison code that will be tested.
9328 The result is a possibly different comparison code to use. *POP0 and
9329 *POP1 may be updated.
9331 It is possible that we might detect that a comparison is either always
9332 true or always false. However, we do not perform general constant
9333 folding in combine, so this knowledge isn't useful. Such tautologies
9334 should have been detected earlier. Hence we ignore all such cases. */
9336 static enum rtx_code
9337 simplify_comparison (enum rtx_code code, rtx *pop0, rtx *pop1)
9343 enum machine_mode mode, tmode;
9345 /* Try a few ways of applying the same transformation to both operands. */
9348 #ifndef WORD_REGISTER_OPERATIONS
9349 /* The test below this one won't handle SIGN_EXTENDs on these machines,
9350 so check specially. */
9351 if (code != GTU && code != GEU && code != LTU && code != LEU
9352 && GET_CODE (op0) == ASHIFTRT && GET_CODE (op1) == ASHIFTRT
9353 && GET_CODE (XEXP (op0, 0)) == ASHIFT
9354 && GET_CODE (XEXP (op1, 0)) == ASHIFT
9355 && GET_CODE (XEXP (XEXP (op0, 0), 0)) == SUBREG
9356 && GET_CODE (XEXP (XEXP (op1, 0), 0)) == SUBREG
9357 && (GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0)))
9358 == GET_MODE (SUBREG_REG (XEXP (XEXP (op1, 0), 0))))
9359 && GET_CODE (XEXP (op0, 1)) == CONST_INT
9360 && XEXP (op0, 1) == XEXP (op1, 1)
9361 && XEXP (op0, 1) == XEXP (XEXP (op0, 0), 1)
9362 && XEXP (op0, 1) == XEXP (XEXP (op1, 0), 1)
9363 && (INTVAL (XEXP (op0, 1))
9364 == (GET_MODE_BITSIZE (GET_MODE (op0))
9366 (GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0))))))))
9368 op0 = SUBREG_REG (XEXP (XEXP (op0, 0), 0));
9369 op1 = SUBREG_REG (XEXP (XEXP (op1, 0), 0));
9373 /* If both operands are the same constant shift, see if we can ignore the
9374 shift. We can if the shift is a rotate or if the bits shifted out of
9375 this shift are known to be zero for both inputs and if the type of
9376 comparison is compatible with the shift. */
9377 if (GET_CODE (op0) == GET_CODE (op1)
9378 && GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
9379 && ((GET_CODE (op0) == ROTATE && (code == NE || code == EQ))
9380 || ((GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFT)
9381 && (code != GT && code != LT && code != GE && code != LE))
9382 || (GET_CODE (op0) == ASHIFTRT
9383 && (code != GTU && code != LTU
9384 && code != GEU && code != LEU)))
9385 && GET_CODE (XEXP (op0, 1)) == CONST_INT
9386 && INTVAL (XEXP (op0, 1)) >= 0
9387 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT
9388 && XEXP (op0, 1) == XEXP (op1, 1))
9390 enum machine_mode mode = GET_MODE (op0);
9391 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
9392 int shift_count = INTVAL (XEXP (op0, 1));
9394 if (GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFTRT)
9395 mask &= (mask >> shift_count) << shift_count;
9396 else if (GET_CODE (op0) == ASHIFT)
9397 mask = (mask & (mask << shift_count)) >> shift_count;
9399 if ((nonzero_bits (XEXP (op0, 0), mode) & ~mask) == 0
9400 && (nonzero_bits (XEXP (op1, 0), mode) & ~mask) == 0)
9401 op0 = XEXP (op0, 0), op1 = XEXP (op1, 0);
9406 /* If both operands are AND's of a paradoxical SUBREG by constant, the
9407 SUBREGs are of the same mode, and, in both cases, the AND would
9408 be redundant if the comparison was done in the narrower mode,
9409 do the comparison in the narrower mode (e.g., we are AND'ing with 1
9410 and the operand's possibly nonzero bits are 0xffffff01; in that case
9411 if we only care about QImode, we don't need the AND). This case
9412 occurs if the output mode of an scc insn is not SImode and
9413 STORE_FLAG_VALUE == 1 (e.g., the 386).
9415 Similarly, check for a case where the AND's are ZERO_EXTEND
9416 operations from some narrower mode even though a SUBREG is not
9419 else if (GET_CODE (op0) == AND && GET_CODE (op1) == AND
9420 && GET_CODE (XEXP (op0, 1)) == CONST_INT
9421 && GET_CODE (XEXP (op1, 1)) == CONST_INT)
9423 rtx inner_op0 = XEXP (op0, 0);
9424 rtx inner_op1 = XEXP (op1, 0);
9425 HOST_WIDE_INT c0 = INTVAL (XEXP (op0, 1));
9426 HOST_WIDE_INT c1 = INTVAL (XEXP (op1, 1));
9429 if (GET_CODE (inner_op0) == SUBREG && GET_CODE (inner_op1) == SUBREG
9430 && (GET_MODE_SIZE (GET_MODE (inner_op0))
9431 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (inner_op0))))
9432 && (GET_MODE (SUBREG_REG (inner_op0))
9433 == GET_MODE (SUBREG_REG (inner_op1)))
9434 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (inner_op0)))
9435 <= HOST_BITS_PER_WIDE_INT)
9436 && (0 == ((~c0) & nonzero_bits (SUBREG_REG (inner_op0),
9437 GET_MODE (SUBREG_REG (inner_op0)))))
9438 && (0 == ((~c1) & nonzero_bits (SUBREG_REG (inner_op1),
9439 GET_MODE (SUBREG_REG (inner_op1))))))
9441 op0 = SUBREG_REG (inner_op0);
9442 op1 = SUBREG_REG (inner_op1);
9444 /* The resulting comparison is always unsigned since we masked
9445 off the original sign bit. */
9446 code = unsigned_condition (code);
9452 for (tmode = GET_CLASS_NARROWEST_MODE
9453 (GET_MODE_CLASS (GET_MODE (op0)));
9454 tmode != GET_MODE (op0); tmode = GET_MODE_WIDER_MODE (tmode))
9455 if ((unsigned HOST_WIDE_INT) c0 == GET_MODE_MASK (tmode))
9457 op0 = gen_lowpart (tmode, inner_op0);
9458 op1 = gen_lowpart (tmode, inner_op1);
9459 code = unsigned_condition (code);
9468 /* If both operands are NOT, we can strip off the outer operation
9469 and adjust the comparison code for swapped operands; similarly for
9470 NEG, except that this must be an equality comparison. */
9471 else if ((GET_CODE (op0) == NOT && GET_CODE (op1) == NOT)
9472 || (GET_CODE (op0) == NEG && GET_CODE (op1) == NEG
9473 && (code == EQ || code == NE)))
9474 op0 = XEXP (op0, 0), op1 = XEXP (op1, 0), code = swap_condition (code);
9480 /* If the first operand is a constant, swap the operands and adjust the
9481 comparison code appropriately, but don't do this if the second operand
9482 is already a constant integer. */
9483 if (swap_commutative_operands_p (op0, op1))
9485 tem = op0, op0 = op1, op1 = tem;
9486 code = swap_condition (code);
9489 /* We now enter a loop during which we will try to simplify the comparison.
9490 For the most part, we only are concerned with comparisons with zero,
9491 but some things may really be comparisons with zero but not start
9492 out looking that way. */
9494 while (GET_CODE (op1) == CONST_INT)
9496 enum machine_mode mode = GET_MODE (op0);
9497 unsigned int mode_width = GET_MODE_BITSIZE (mode);
9498 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
9499 int equality_comparison_p;
9500 int sign_bit_comparison_p;
9501 int unsigned_comparison_p;
9502 HOST_WIDE_INT const_op;
9504 /* We only want to handle integral modes. This catches VOIDmode,
9505 CCmode, and the floating-point modes. An exception is that we
9506 can handle VOIDmode if OP0 is a COMPARE or a comparison
9509 if (GET_MODE_CLASS (mode) != MODE_INT
9510 && ! (mode == VOIDmode
9511 && (GET_CODE (op0) == COMPARE || COMPARISON_P (op0))))
9514 /* Get the constant we are comparing against and turn off all bits
9515 not on in our mode. */
9516 const_op = INTVAL (op1);
9517 if (mode != VOIDmode)
9518 const_op = trunc_int_for_mode (const_op, mode);
9519 op1 = GEN_INT (const_op);
9521 /* If we are comparing against a constant power of two and the value
9522 being compared can only have that single bit nonzero (e.g., it was
9523 `and'ed with that bit), we can replace this with a comparison
9526 && (code == EQ || code == NE || code == GE || code == GEU
9527 || code == LT || code == LTU)
9528 && mode_width <= HOST_BITS_PER_WIDE_INT
9529 && exact_log2 (const_op) >= 0
9530 && nonzero_bits (op0, mode) == (unsigned HOST_WIDE_INT) const_op)
9532 code = (code == EQ || code == GE || code == GEU ? NE : EQ);
9533 op1 = const0_rtx, const_op = 0;
9536 /* Similarly, if we are comparing a value known to be either -1 or
9537 0 with -1, change it to the opposite comparison against zero. */
9540 && (code == EQ || code == NE || code == GT || code == LE
9541 || code == GEU || code == LTU)
9542 && num_sign_bit_copies (op0, mode) == mode_width)
9544 code = (code == EQ || code == LE || code == GEU ? NE : EQ);
9545 op1 = const0_rtx, const_op = 0;
9548 /* Do some canonicalizations based on the comparison code. We prefer
9549 comparisons against zero and then prefer equality comparisons.
9550 If we can reduce the size of a constant, we will do that too. */
9555 /* < C is equivalent to <= (C - 1) */
9559 op1 = GEN_INT (const_op);
9561 /* ... fall through to LE case below. */
9567 /* <= C is equivalent to < (C + 1); we do this for C < 0 */
9571 op1 = GEN_INT (const_op);
9575 /* If we are doing a <= 0 comparison on a value known to have
9576 a zero sign bit, we can replace this with == 0. */
9577 else if (const_op == 0
9578 && mode_width <= HOST_BITS_PER_WIDE_INT
9579 && (nonzero_bits (op0, mode)
9580 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)
9585 /* >= C is equivalent to > (C - 1). */
9589 op1 = GEN_INT (const_op);
9591 /* ... fall through to GT below. */
9597 /* > C is equivalent to >= (C + 1); we do this for C < 0. */
9601 op1 = GEN_INT (const_op);
9605 /* If we are doing a > 0 comparison on a value known to have
9606 a zero sign bit, we can replace this with != 0. */
9607 else if (const_op == 0
9608 && mode_width <= HOST_BITS_PER_WIDE_INT
9609 && (nonzero_bits (op0, mode)
9610 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)
9615 /* < C is equivalent to <= (C - 1). */
9619 op1 = GEN_INT (const_op);
9621 /* ... fall through ... */
9624 /* (unsigned) < 0x80000000 is equivalent to >= 0. */
9625 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
9626 && (const_op == (HOST_WIDE_INT) 1 << (mode_width - 1)))
9628 const_op = 0, op1 = const0_rtx;
9636 /* unsigned <= 0 is equivalent to == 0 */
9640 /* (unsigned) <= 0x7fffffff is equivalent to >= 0. */
9641 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
9642 && (const_op == ((HOST_WIDE_INT) 1 << (mode_width - 1)) - 1))
9644 const_op = 0, op1 = const0_rtx;
9650 /* >= C is equivalent to > (C - 1). */
9654 op1 = GEN_INT (const_op);
9656 /* ... fall through ... */
9659 /* (unsigned) >= 0x80000000 is equivalent to < 0. */
9660 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
9661 && (const_op == (HOST_WIDE_INT) 1 << (mode_width - 1)))
9663 const_op = 0, op1 = const0_rtx;
9671 /* unsigned > 0 is equivalent to != 0 */
9675 /* (unsigned) > 0x7fffffff is equivalent to < 0. */
9676 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
9677 && (const_op == ((HOST_WIDE_INT) 1 << (mode_width - 1)) - 1))
9679 const_op = 0, op1 = const0_rtx;
9688 /* Compute some predicates to simplify code below. */
9690 equality_comparison_p = (code == EQ || code == NE);
9691 sign_bit_comparison_p = ((code == LT || code == GE) && const_op == 0);
9692 unsigned_comparison_p = (code == LTU || code == LEU || code == GTU
9695 /* If this is a sign bit comparison and we can do arithmetic in
9696 MODE, say that we will only be needing the sign bit of OP0. */
9697 if (sign_bit_comparison_p
9698 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
9699 op0 = force_to_mode (op0, mode,
9701 << (GET_MODE_BITSIZE (mode) - 1)),
9704 /* Now try cases based on the opcode of OP0. If none of the cases
9705 does a "continue", we exit this loop immediately after the
9708 switch (GET_CODE (op0))
9711 /* If we are extracting a single bit from a variable position in
9712 a constant that has only a single bit set and are comparing it
9713 with zero, we can convert this into an equality comparison
9714 between the position and the location of the single bit. */
9715 /* Except we can't if SHIFT_COUNT_TRUNCATED is set, since we might
9716 have already reduced the shift count modulo the word size. */
9717 if (!SHIFT_COUNT_TRUNCATED
9718 && GET_CODE (XEXP (op0, 0)) == CONST_INT
9719 && XEXP (op0, 1) == const1_rtx
9720 && equality_comparison_p && const_op == 0
9721 && (i = exact_log2 (INTVAL (XEXP (op0, 0)))) >= 0)
9723 if (BITS_BIG_ENDIAN)
9725 enum machine_mode new_mode
9726 = mode_for_extraction (EP_extzv, 1);
9727 if (new_mode == MAX_MACHINE_MODE)
9728 i = BITS_PER_WORD - 1 - i;
9732 i = (GET_MODE_BITSIZE (mode) - 1 - i);
9736 op0 = XEXP (op0, 2);
9740 /* Result is nonzero iff shift count is equal to I. */
9741 code = reverse_condition (code);
9745 /* ... fall through ... */
9748 tem = expand_compound_operation (op0);
9757 /* If testing for equality, we can take the NOT of the constant. */
9758 if (equality_comparison_p
9759 && (tem = simplify_unary_operation (NOT, mode, op1, mode)) != 0)
9761 op0 = XEXP (op0, 0);
9766 /* If just looking at the sign bit, reverse the sense of the
9768 if (sign_bit_comparison_p)
9770 op0 = XEXP (op0, 0);
9771 code = (code == GE ? LT : GE);
9777 /* If testing for equality, we can take the NEG of the constant. */
9778 if (equality_comparison_p
9779 && (tem = simplify_unary_operation (NEG, mode, op1, mode)) != 0)
9781 op0 = XEXP (op0, 0);
9786 /* The remaining cases only apply to comparisons with zero. */
9790 /* When X is ABS or is known positive,
9791 (neg X) is < 0 if and only if X != 0. */
9793 if (sign_bit_comparison_p
9794 && (GET_CODE (XEXP (op0, 0)) == ABS
9795 || (mode_width <= HOST_BITS_PER_WIDE_INT
9796 && (nonzero_bits (XEXP (op0, 0), mode)
9797 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)))
9799 op0 = XEXP (op0, 0);
9800 code = (code == LT ? NE : EQ);
9804 /* If we have NEG of something whose two high-order bits are the
9805 same, we know that "(-a) < 0" is equivalent to "a > 0". */
9806 if (num_sign_bit_copies (op0, mode) >= 2)
9808 op0 = XEXP (op0, 0);
9809 code = swap_condition (code);
9815 /* If we are testing equality and our count is a constant, we
9816 can perform the inverse operation on our RHS. */
9817 if (equality_comparison_p && GET_CODE (XEXP (op0, 1)) == CONST_INT
9818 && (tem = simplify_binary_operation (ROTATERT, mode,
9819 op1, XEXP (op0, 1))) != 0)
9821 op0 = XEXP (op0, 0);
9826 /* If we are doing a < 0 or >= 0 comparison, it means we are testing
9827 a particular bit. Convert it to an AND of a constant of that
9828 bit. This will be converted into a ZERO_EXTRACT. */
9829 if (const_op == 0 && sign_bit_comparison_p
9830 && GET_CODE (XEXP (op0, 1)) == CONST_INT
9831 && mode_width <= HOST_BITS_PER_WIDE_INT)
9833 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
9836 - INTVAL (XEXP (op0, 1)))));
9837 code = (code == LT ? NE : EQ);
9844 /* ABS is ignorable inside an equality comparison with zero. */
9845 if (const_op == 0 && equality_comparison_p)
9847 op0 = XEXP (op0, 0);
9853 /* Can simplify (compare (zero/sign_extend FOO) CONST) to
9854 (compare FOO CONST) if CONST fits in FOO's mode and we
9855 are either testing inequality or have an unsigned
9856 comparison with ZERO_EXTEND or a signed comparison with
9857 SIGN_EXTEND. But don't do it if we don't have a compare
9858 insn of the given mode, since we'd have to revert it
9859 later on, and then we wouldn't know whether to sign- or
9861 mode = GET_MODE (XEXP (op0, 0));
9862 if (mode != VOIDmode && GET_MODE_CLASS (mode) == MODE_INT
9863 && ! unsigned_comparison_p
9864 && (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
9865 && ((unsigned HOST_WIDE_INT) const_op
9866 < (((unsigned HOST_WIDE_INT) 1
9867 << (GET_MODE_BITSIZE (mode) - 1))))
9868 && cmp_optab->handlers[(int) mode].insn_code != CODE_FOR_nothing)
9870 op0 = XEXP (op0, 0);
9876 /* Check for the case where we are comparing A - C1 with C2, that is
9878 (subreg:MODE (plus (A) (-C1))) op (C2)
9880 with C1 a constant, and try to lift the SUBREG, i.e. to do the
9881 comparison in the wider mode. One of the following two conditions
9882 must be true in order for this to be valid:
9884 1. The mode extension results in the same bit pattern being added
9885 on both sides and the comparison is equality or unsigned. As
9886 C2 has been truncated to fit in MODE, the pattern can only be
9889 2. The mode extension results in the sign bit being copied on
9892 The difficulty here is that we have predicates for A but not for
9893 (A - C1) so we need to check that C1 is within proper bounds so
9894 as to perturbate A as little as possible. */
9896 if (mode_width <= HOST_BITS_PER_WIDE_INT
9897 && subreg_lowpart_p (op0)
9898 && GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0))) > mode_width
9899 && GET_CODE (SUBREG_REG (op0)) == PLUS
9900 && GET_CODE (XEXP (SUBREG_REG (op0), 1)) == CONST_INT)
9902 enum machine_mode inner_mode = GET_MODE (SUBREG_REG (op0));
9903 rtx a = XEXP (SUBREG_REG (op0), 0);
9904 HOST_WIDE_INT c1 = -INTVAL (XEXP (SUBREG_REG (op0), 1));
9907 && (unsigned HOST_WIDE_INT) c1
9908 < (unsigned HOST_WIDE_INT) 1 << (mode_width - 1)
9909 && (equality_comparison_p || unsigned_comparison_p)
9910 /* (A - C1) zero-extends if it is positive and sign-extends
9911 if it is negative, C2 both zero- and sign-extends. */
9912 && ((0 == (nonzero_bits (a, inner_mode)
9913 & ~GET_MODE_MASK (mode))
9915 /* (A - C1) sign-extends if it is positive and 1-extends
9916 if it is negative, C2 both sign- and 1-extends. */
9917 || (num_sign_bit_copies (a, inner_mode)
9918 > (unsigned int) (GET_MODE_BITSIZE (inner_mode)
9921 || ((unsigned HOST_WIDE_INT) c1
9922 < (unsigned HOST_WIDE_INT) 1 << (mode_width - 2)
9923 /* (A - C1) always sign-extends, like C2. */
9924 && num_sign_bit_copies (a, inner_mode)
9925 > (unsigned int) (GET_MODE_BITSIZE (inner_mode)
9926 - (mode_width - 1))))
9928 op0 = SUBREG_REG (op0);
9933 /* If the inner mode is narrower and we are extracting the low part,
9934 we can treat the SUBREG as if it were a ZERO_EXTEND. */
9935 if (subreg_lowpart_p (op0)
9936 && GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0))) < mode_width)
9937 /* Fall through */ ;
9941 /* ... fall through ... */
9944 mode = GET_MODE (XEXP (op0, 0));
9945 if (mode != VOIDmode && GET_MODE_CLASS (mode) == MODE_INT
9946 && (unsigned_comparison_p || equality_comparison_p)
9947 && (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
9948 && ((unsigned HOST_WIDE_INT) const_op < GET_MODE_MASK (mode))
9949 && cmp_optab->handlers[(int) mode].insn_code != CODE_FOR_nothing)
9951 op0 = XEXP (op0, 0);
9957 /* (eq (plus X A) B) -> (eq X (minus B A)). We can only do
9958 this for equality comparisons due to pathological cases involving
9960 if (equality_comparison_p
9961 && 0 != (tem = simplify_binary_operation (MINUS, mode,
9962 op1, XEXP (op0, 1))))
9964 op0 = XEXP (op0, 0);
9969 /* (plus (abs X) (const_int -1)) is < 0 if and only if X == 0. */
9970 if (const_op == 0 && XEXP (op0, 1) == constm1_rtx
9971 && GET_CODE (XEXP (op0, 0)) == ABS && sign_bit_comparison_p)
9973 op0 = XEXP (XEXP (op0, 0), 0);
9974 code = (code == LT ? EQ : NE);
9980 /* We used to optimize signed comparisons against zero, but that
9981 was incorrect. Unsigned comparisons against zero (GTU, LEU)
9982 arrive here as equality comparisons, or (GEU, LTU) are
9983 optimized away. No need to special-case them. */
9985 /* (eq (minus A B) C) -> (eq A (plus B C)) or
9986 (eq B (minus A C)), whichever simplifies. We can only do
9987 this for equality comparisons due to pathological cases involving
9989 if (equality_comparison_p
9990 && 0 != (tem = simplify_binary_operation (PLUS, mode,
9991 XEXP (op0, 1), op1)))
9993 op0 = XEXP (op0, 0);
9998 if (equality_comparison_p
9999 && 0 != (tem = simplify_binary_operation (MINUS, mode,
10000 XEXP (op0, 0), op1)))
10002 op0 = XEXP (op0, 1);
10007 /* The sign bit of (minus (ashiftrt X C) X), where C is the number
10008 of bits in X minus 1, is one iff X > 0. */
10009 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == ASHIFTRT
10010 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
10011 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (XEXP (op0, 0), 1))
10013 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
10015 op0 = XEXP (op0, 1);
10016 code = (code == GE ? LE : GT);
10022 /* (eq (xor A B) C) -> (eq A (xor B C)). This is a simplification
10023 if C is zero or B is a constant. */
10024 if (equality_comparison_p
10025 && 0 != (tem = simplify_binary_operation (XOR, mode,
10026 XEXP (op0, 1), op1)))
10028 op0 = XEXP (op0, 0);
10035 case UNEQ: case LTGT:
10036 case LT: case LTU: case UNLT: case LE: case LEU: case UNLE:
10037 case GT: case GTU: case UNGT: case GE: case GEU: case UNGE:
10038 case UNORDERED: case ORDERED:
10039 /* We can't do anything if OP0 is a condition code value, rather
10040 than an actual data value. */
10042 || CC0_P (XEXP (op0, 0))
10043 || GET_MODE_CLASS (GET_MODE (XEXP (op0, 0))) == MODE_CC)
10046 /* Get the two operands being compared. */
10047 if (GET_CODE (XEXP (op0, 0)) == COMPARE)
10048 tem = XEXP (XEXP (op0, 0), 0), tem1 = XEXP (XEXP (op0, 0), 1);
10050 tem = XEXP (op0, 0), tem1 = XEXP (op0, 1);
10052 /* Check for the cases where we simply want the result of the
10053 earlier test or the opposite of that result. */
10054 if (code == NE || code == EQ
10055 || (GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
10056 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
10057 && (STORE_FLAG_VALUE
10058 & (((HOST_WIDE_INT) 1
10059 << (GET_MODE_BITSIZE (GET_MODE (op0)) - 1))))
10060 && (code == LT || code == GE)))
10062 enum rtx_code new_code;
10063 if (code == LT || code == NE)
10064 new_code = GET_CODE (op0);
10066 new_code = reversed_comparison_code (op0, NULL);
10068 if (new_code != UNKNOWN)
10079 /* The sign bit of (ior (plus X (const_int -1)) X) is nonzero
10081 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == PLUS
10082 && XEXP (XEXP (op0, 0), 1) == constm1_rtx
10083 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
10085 op0 = XEXP (op0, 1);
10086 code = (code == GE ? GT : LE);
10092 /* Convert (and (xshift 1 X) Y) to (and (lshiftrt Y X) 1). This
10093 will be converted to a ZERO_EXTRACT later. */
10094 if (const_op == 0 && equality_comparison_p
10095 && GET_CODE (XEXP (op0, 0)) == ASHIFT
10096 && XEXP (XEXP (op0, 0), 0) == const1_rtx)
10098 op0 = simplify_and_const_int
10099 (op0, mode, gen_rtx_LSHIFTRT (mode,
10101 XEXP (XEXP (op0, 0), 1)),
10102 (HOST_WIDE_INT) 1);
10106 /* If we are comparing (and (lshiftrt X C1) C2) for equality with
10107 zero and X is a comparison and C1 and C2 describe only bits set
10108 in STORE_FLAG_VALUE, we can compare with X. */
10109 if (const_op == 0 && equality_comparison_p
10110 && mode_width <= HOST_BITS_PER_WIDE_INT
10111 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10112 && GET_CODE (XEXP (op0, 0)) == LSHIFTRT
10113 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
10114 && INTVAL (XEXP (XEXP (op0, 0), 1)) >= 0
10115 && INTVAL (XEXP (XEXP (op0, 0), 1)) < HOST_BITS_PER_WIDE_INT)
10117 mask = ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
10118 << INTVAL (XEXP (XEXP (op0, 0), 1)));
10119 if ((~STORE_FLAG_VALUE & mask) == 0
10120 && (COMPARISON_P (XEXP (XEXP (op0, 0), 0))
10121 || ((tem = get_last_value (XEXP (XEXP (op0, 0), 0))) != 0
10122 && COMPARISON_P (tem))))
10124 op0 = XEXP (XEXP (op0, 0), 0);
10129 /* If we are doing an equality comparison of an AND of a bit equal
10130 to the sign bit, replace this with a LT or GE comparison of
10131 the underlying value. */
10132 if (equality_comparison_p
10134 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10135 && mode_width <= HOST_BITS_PER_WIDE_INT
10136 && ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
10137 == (unsigned HOST_WIDE_INT) 1 << (mode_width - 1)))
10139 op0 = XEXP (op0, 0);
10140 code = (code == EQ ? GE : LT);
10144 /* If this AND operation is really a ZERO_EXTEND from a narrower
10145 mode, the constant fits within that mode, and this is either an
10146 equality or unsigned comparison, try to do this comparison in
10147 the narrower mode. */
10148 if ((equality_comparison_p || unsigned_comparison_p)
10149 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10150 && (i = exact_log2 ((INTVAL (XEXP (op0, 1))
10151 & GET_MODE_MASK (mode))
10153 && const_op >> i == 0
10154 && (tmode = mode_for_size (i, MODE_INT, 1)) != BLKmode)
10156 op0 = gen_lowpart (tmode, XEXP (op0, 0));
10160 /* If this is (and:M1 (subreg:M2 X 0) (const_int C1)) where C1
10161 fits in both M1 and M2 and the SUBREG is either paradoxical
10162 or represents the low part, permute the SUBREG and the AND
10164 if (GET_CODE (XEXP (op0, 0)) == SUBREG)
10166 unsigned HOST_WIDE_INT c1;
10167 tmode = GET_MODE (SUBREG_REG (XEXP (op0, 0)));
10168 /* Require an integral mode, to avoid creating something like
10170 if (SCALAR_INT_MODE_P (tmode)
10171 /* It is unsafe to commute the AND into the SUBREG if the
10172 SUBREG is paradoxical and WORD_REGISTER_OPERATIONS is
10173 not defined. As originally written the upper bits
10174 have a defined value due to the AND operation.
10175 However, if we commute the AND inside the SUBREG then
10176 they no longer have defined values and the meaning of
10177 the code has been changed. */
10179 #ifdef WORD_REGISTER_OPERATIONS
10180 || (mode_width > GET_MODE_BITSIZE (tmode)
10181 && mode_width <= BITS_PER_WORD)
10183 || (mode_width <= GET_MODE_BITSIZE (tmode)
10184 && subreg_lowpart_p (XEXP (op0, 0))))
10185 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10186 && mode_width <= HOST_BITS_PER_WIDE_INT
10187 && GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT
10188 && ((c1 = INTVAL (XEXP (op0, 1))) & ~mask) == 0
10189 && (c1 & ~GET_MODE_MASK (tmode)) == 0
10191 && c1 != GET_MODE_MASK (tmode))
10193 op0 = simplify_gen_binary (AND, tmode,
10194 SUBREG_REG (XEXP (op0, 0)),
10195 gen_int_mode (c1, tmode));
10196 op0 = gen_lowpart (mode, op0);
10201 /* Convert (ne (and (not X) 1) 0) to (eq (and X 1) 0). */
10202 if (const_op == 0 && equality_comparison_p
10203 && XEXP (op0, 1) == const1_rtx
10204 && GET_CODE (XEXP (op0, 0)) == NOT)
10206 op0 = simplify_and_const_int
10207 (NULL_RTX, mode, XEXP (XEXP (op0, 0), 0), (HOST_WIDE_INT) 1);
10208 code = (code == NE ? EQ : NE);
10212 /* Convert (ne (and (lshiftrt (not X)) 1) 0) to
10213 (eq (and (lshiftrt X) 1) 0).
10214 Also handle the case where (not X) is expressed using xor. */
10215 if (const_op == 0 && equality_comparison_p
10216 && XEXP (op0, 1) == const1_rtx
10217 && GET_CODE (XEXP (op0, 0)) == LSHIFTRT)
10219 rtx shift_op = XEXP (XEXP (op0, 0), 0);
10220 rtx shift_count = XEXP (XEXP (op0, 0), 1);
10222 if (GET_CODE (shift_op) == NOT
10223 || (GET_CODE (shift_op) == XOR
10224 && GET_CODE (XEXP (shift_op, 1)) == CONST_INT
10225 && GET_CODE (shift_count) == CONST_INT
10226 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
10227 && (INTVAL (XEXP (shift_op, 1))
10228 == (HOST_WIDE_INT) 1 << INTVAL (shift_count))))
10230 op0 = simplify_and_const_int
10232 gen_rtx_LSHIFTRT (mode, XEXP (shift_op, 0), shift_count),
10233 (HOST_WIDE_INT) 1);
10234 code = (code == NE ? EQ : NE);
10241 /* If we have (compare (ashift FOO N) (const_int C)) and
10242 the high order N bits of FOO (N+1 if an inequality comparison)
10243 are known to be zero, we can do this by comparing FOO with C
10244 shifted right N bits so long as the low-order N bits of C are
10246 if (GET_CODE (XEXP (op0, 1)) == CONST_INT
10247 && INTVAL (XEXP (op0, 1)) >= 0
10248 && ((INTVAL (XEXP (op0, 1)) + ! equality_comparison_p)
10249 < HOST_BITS_PER_WIDE_INT)
10251 & (((HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1))) - 1)) == 0)
10252 && mode_width <= HOST_BITS_PER_WIDE_INT
10253 && (nonzero_bits (XEXP (op0, 0), mode)
10254 & ~(mask >> (INTVAL (XEXP (op0, 1))
10255 + ! equality_comparison_p))) == 0)
10257 /* We must perform a logical shift, not an arithmetic one,
10258 as we want the top N bits of C to be zero. */
10259 unsigned HOST_WIDE_INT temp = const_op & GET_MODE_MASK (mode);
10261 temp >>= INTVAL (XEXP (op0, 1));
10262 op1 = gen_int_mode (temp, mode);
10263 op0 = XEXP (op0, 0);
10267 /* If we are doing a sign bit comparison, it means we are testing
10268 a particular bit. Convert it to the appropriate AND. */
10269 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 1)) == CONST_INT
10270 && mode_width <= HOST_BITS_PER_WIDE_INT)
10272 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
10275 - INTVAL (XEXP (op0, 1)))));
10276 code = (code == LT ? NE : EQ);
10280 /* If this an equality comparison with zero and we are shifting
10281 the low bit to the sign bit, we can convert this to an AND of the
10283 if (const_op == 0 && equality_comparison_p
10284 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10285 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (op0, 1))
10288 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
10289 (HOST_WIDE_INT) 1);
10295 /* If this is an equality comparison with zero, we can do this
10296 as a logical shift, which might be much simpler. */
10297 if (equality_comparison_p && const_op == 0
10298 && GET_CODE (XEXP (op0, 1)) == CONST_INT)
10300 op0 = simplify_shift_const (NULL_RTX, LSHIFTRT, mode,
10302 INTVAL (XEXP (op0, 1)));
10306 /* If OP0 is a sign extension and CODE is not an unsigned comparison,
10307 do the comparison in a narrower mode. */
10308 if (! unsigned_comparison_p
10309 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10310 && GET_CODE (XEXP (op0, 0)) == ASHIFT
10311 && XEXP (op0, 1) == XEXP (XEXP (op0, 0), 1)
10312 && (tmode = mode_for_size (mode_width - INTVAL (XEXP (op0, 1)),
10313 MODE_INT, 1)) != BLKmode
10314 && (((unsigned HOST_WIDE_INT) const_op
10315 + (GET_MODE_MASK (tmode) >> 1) + 1)
10316 <= GET_MODE_MASK (tmode)))
10318 op0 = gen_lowpart (tmode, XEXP (XEXP (op0, 0), 0));
10322 /* Likewise if OP0 is a PLUS of a sign extension with a
10323 constant, which is usually represented with the PLUS
10324 between the shifts. */
10325 if (! unsigned_comparison_p
10326 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10327 && GET_CODE (XEXP (op0, 0)) == PLUS
10328 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
10329 && GET_CODE (XEXP (XEXP (op0, 0), 0)) == ASHIFT
10330 && XEXP (op0, 1) == XEXP (XEXP (XEXP (op0, 0), 0), 1)
10331 && (tmode = mode_for_size (mode_width - INTVAL (XEXP (op0, 1)),
10332 MODE_INT, 1)) != BLKmode
10333 && (((unsigned HOST_WIDE_INT) const_op
10334 + (GET_MODE_MASK (tmode) >> 1) + 1)
10335 <= GET_MODE_MASK (tmode)))
10337 rtx inner = XEXP (XEXP (XEXP (op0, 0), 0), 0);
10338 rtx add_const = XEXP (XEXP (op0, 0), 1);
10339 rtx new_const = simplify_gen_binary (ASHIFTRT, GET_MODE (op0),
10340 add_const, XEXP (op0, 1));
10342 op0 = simplify_gen_binary (PLUS, tmode,
10343 gen_lowpart (tmode, inner),
10348 /* ... fall through ... */
10350 /* If we have (compare (xshiftrt FOO N) (const_int C)) and
10351 the low order N bits of FOO are known to be zero, we can do this
10352 by comparing FOO with C shifted left N bits so long as no
10353 overflow occurs. */
10354 if (GET_CODE (XEXP (op0, 1)) == CONST_INT
10355 && INTVAL (XEXP (op0, 1)) >= 0
10356 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT
10357 && mode_width <= HOST_BITS_PER_WIDE_INT
10358 && (nonzero_bits (XEXP (op0, 0), mode)
10359 & (((HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1))) - 1)) == 0
10360 && (((unsigned HOST_WIDE_INT) const_op
10361 + (GET_CODE (op0) != LSHIFTRT
10362 ? ((GET_MODE_MASK (mode) >> INTVAL (XEXP (op0, 1)) >> 1)
10365 <= GET_MODE_MASK (mode) >> INTVAL (XEXP (op0, 1))))
10367 /* If the shift was logical, then we must make the condition
10369 if (GET_CODE (op0) == LSHIFTRT)
10370 code = unsigned_condition (code);
10372 const_op <<= INTVAL (XEXP (op0, 1));
10373 op1 = GEN_INT (const_op);
10374 op0 = XEXP (op0, 0);
10378 /* If we are using this shift to extract just the sign bit, we
10379 can replace this with an LT or GE comparison. */
10381 && (equality_comparison_p || sign_bit_comparison_p)
10382 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10383 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (op0, 1))
10386 op0 = XEXP (op0, 0);
10387 code = (code == NE || code == GT ? LT : GE);
10399 /* Now make any compound operations involved in this comparison. Then,
10400 check for an outmost SUBREG on OP0 that is not doing anything or is
10401 paradoxical. The latter transformation must only be performed when
10402 it is known that the "extra" bits will be the same in op0 and op1 or
10403 that they don't matter. There are three cases to consider:
10405 1. SUBREG_REG (op0) is a register. In this case the bits are don't
10406 care bits and we can assume they have any convenient value. So
10407 making the transformation is safe.
10409 2. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is not defined.
10410 In this case the upper bits of op0 are undefined. We should not make
10411 the simplification in that case as we do not know the contents of
10414 3. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is defined and not
10415 UNKNOWN. In that case we know those bits are zeros or ones. We must
10416 also be sure that they are the same as the upper bits of op1.
10418 We can never remove a SUBREG for a non-equality comparison because
10419 the sign bit is in a different place in the underlying object. */
10421 op0 = make_compound_operation (op0, op1 == const0_rtx ? COMPARE : SET);
10422 op1 = make_compound_operation (op1, SET);
10424 if (GET_CODE (op0) == SUBREG && subreg_lowpart_p (op0)
10425 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
10426 && GET_MODE_CLASS (GET_MODE (SUBREG_REG (op0))) == MODE_INT
10427 && (code == NE || code == EQ))
10429 if (GET_MODE_SIZE (GET_MODE (op0))
10430 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (op0))))
10432 /* For paradoxical subregs, allow case 1 as above. Case 3 isn't
10434 if (REG_P (SUBREG_REG (op0)))
10436 op0 = SUBREG_REG (op0);
10437 op1 = gen_lowpart (GET_MODE (op0), op1);
10440 else if ((GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0)))
10441 <= HOST_BITS_PER_WIDE_INT)
10442 && (nonzero_bits (SUBREG_REG (op0),
10443 GET_MODE (SUBREG_REG (op0)))
10444 & ~GET_MODE_MASK (GET_MODE (op0))) == 0)
10446 tem = gen_lowpart (GET_MODE (SUBREG_REG (op0)), op1);
10448 if ((nonzero_bits (tem, GET_MODE (SUBREG_REG (op0)))
10449 & ~GET_MODE_MASK (GET_MODE (op0))) == 0)
10450 op0 = SUBREG_REG (op0), op1 = tem;
10454 /* We now do the opposite procedure: Some machines don't have compare
10455 insns in all modes. If OP0's mode is an integer mode smaller than a
10456 word and we can't do a compare in that mode, see if there is a larger
10457 mode for which we can do the compare. There are a number of cases in
10458 which we can use the wider mode. */
10460 mode = GET_MODE (op0);
10461 if (mode != VOIDmode && GET_MODE_CLASS (mode) == MODE_INT
10462 && GET_MODE_SIZE (mode) < UNITS_PER_WORD
10463 && ! have_insn_for (COMPARE, mode))
10464 for (tmode = GET_MODE_WIDER_MODE (mode);
10466 && GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT);
10467 tmode = GET_MODE_WIDER_MODE (tmode))
10468 if (have_insn_for (COMPARE, tmode))
10472 /* If the only nonzero bits in OP0 and OP1 are those in the
10473 narrower mode and this is an equality or unsigned comparison,
10474 we can use the wider mode. Similarly for sign-extended
10475 values, in which case it is true for all comparisons. */
10476 zero_extended = ((code == EQ || code == NE
10477 || code == GEU || code == GTU
10478 || code == LEU || code == LTU)
10479 && (nonzero_bits (op0, tmode)
10480 & ~GET_MODE_MASK (mode)) == 0
10481 && ((GET_CODE (op1) == CONST_INT
10482 || (nonzero_bits (op1, tmode)
10483 & ~GET_MODE_MASK (mode)) == 0)));
10486 || ((num_sign_bit_copies (op0, tmode)
10487 > (unsigned int) (GET_MODE_BITSIZE (tmode)
10488 - GET_MODE_BITSIZE (mode)))
10489 && (num_sign_bit_copies (op1, tmode)
10490 > (unsigned int) (GET_MODE_BITSIZE (tmode)
10491 - GET_MODE_BITSIZE (mode)))))
10493 /* If OP0 is an AND and we don't have an AND in MODE either,
10494 make a new AND in the proper mode. */
10495 if (GET_CODE (op0) == AND
10496 && !have_insn_for (AND, mode))
10497 op0 = simplify_gen_binary (AND, tmode,
10498 gen_lowpart (tmode,
10500 gen_lowpart (tmode,
10503 op0 = gen_lowpart (tmode, op0);
10504 if (zero_extended && GET_CODE (op1) == CONST_INT)
10505 op1 = GEN_INT (INTVAL (op1) & GET_MODE_MASK (mode));
10506 op1 = gen_lowpart (tmode, op1);
10510 /* If this is a test for negative, we can make an explicit
10511 test of the sign bit. */
10513 if (op1 == const0_rtx && (code == LT || code == GE)
10514 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
10516 op0 = simplify_gen_binary (AND, tmode,
10517 gen_lowpart (tmode, op0),
10518 GEN_INT ((HOST_WIDE_INT) 1
10519 << (GET_MODE_BITSIZE (mode)
10521 code = (code == LT) ? NE : EQ;
10526 #ifdef CANONICALIZE_COMPARISON
10527 /* If this machine only supports a subset of valid comparisons, see if we
10528 can convert an unsupported one into a supported one. */
10529 CANONICALIZE_COMPARISON (code, op0, op1);
10538 /* Utility function for record_value_for_reg. Count number of
10543 enum rtx_code code = GET_CODE (x);
10547 if (GET_RTX_CLASS (code) == '2'
10548 || GET_RTX_CLASS (code) == 'c')
10550 rtx x0 = XEXP (x, 0);
10551 rtx x1 = XEXP (x, 1);
10554 return 1 + 2 * count_rtxs (x0);
10556 if ((GET_RTX_CLASS (GET_CODE (x1)) == '2'
10557 || GET_RTX_CLASS (GET_CODE (x1)) == 'c')
10558 && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1)))
10559 return 2 + 2 * count_rtxs (x0)
10560 + count_rtxs (x == XEXP (x1, 0)
10561 ? XEXP (x1, 1) : XEXP (x1, 0));
10563 if ((GET_RTX_CLASS (GET_CODE (x0)) == '2'
10564 || GET_RTX_CLASS (GET_CODE (x0)) == 'c')
10565 && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1)))
10566 return 2 + 2 * count_rtxs (x1)
10567 + count_rtxs (x == XEXP (x0, 0)
10568 ? XEXP (x0, 1) : XEXP (x0, 0));
10571 fmt = GET_RTX_FORMAT (code);
10572 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
10574 ret += count_rtxs (XEXP (x, i));
10579 /* Utility function for following routine. Called when X is part of a value
10580 being stored into last_set_value. Sets last_set_table_tick
10581 for each register mentioned. Similar to mention_regs in cse.c */
10584 update_table_tick (rtx x)
10586 enum rtx_code code = GET_CODE (x);
10587 const char *fmt = GET_RTX_FORMAT (code);
10592 unsigned int regno = REGNO (x);
10593 unsigned int endregno
10594 = regno + (regno < FIRST_PSEUDO_REGISTER
10595 ? hard_regno_nregs[regno][GET_MODE (x)] : 1);
10598 for (r = regno; r < endregno; r++)
10599 reg_stat[r].last_set_table_tick = label_tick;
10604 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
10605 /* Note that we can't have an "E" in values stored; see
10606 get_last_value_validate. */
10609 /* Check for identical subexpressions. If x contains
10610 identical subexpression we only have to traverse one of
10612 if (i == 0 && ARITHMETIC_P (x))
10614 /* Note that at this point x1 has already been
10616 rtx x0 = XEXP (x, 0);
10617 rtx x1 = XEXP (x, 1);
10619 /* If x0 and x1 are identical then there is no need to
10624 /* If x0 is identical to a subexpression of x1 then while
10625 processing x1, x0 has already been processed. Thus we
10626 are done with x. */
10627 if (ARITHMETIC_P (x1)
10628 && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1)))
10631 /* If x1 is identical to a subexpression of x0 then we
10632 still have to process the rest of x0. */
10633 if (ARITHMETIC_P (x0)
10634 && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1)))
10636 update_table_tick (XEXP (x0, x1 == XEXP (x0, 0) ? 1 : 0));
10641 update_table_tick (XEXP (x, i));
10645 /* Record that REG is set to VALUE in insn INSN. If VALUE is zero, we
10646 are saying that the register is clobbered and we no longer know its
10647 value. If INSN is zero, don't update reg_stat[].last_set; this is
10648 only permitted with VALUE also zero and is used to invalidate the
10652 record_value_for_reg (rtx reg, rtx insn, rtx value)
10654 unsigned int regno = REGNO (reg);
10655 unsigned int endregno
10656 = regno + (regno < FIRST_PSEUDO_REGISTER
10657 ? hard_regno_nregs[regno][GET_MODE (reg)] : 1);
10660 /* If VALUE contains REG and we have a previous value for REG, substitute
10661 the previous value. */
10662 if (value && insn && reg_overlap_mentioned_p (reg, value))
10666 /* Set things up so get_last_value is allowed to see anything set up to
10668 subst_low_cuid = INSN_CUID (insn);
10669 tem = get_last_value (reg);
10671 /* If TEM is simply a binary operation with two CLOBBERs as operands,
10672 it isn't going to be useful and will take a lot of time to process,
10673 so just use the CLOBBER. */
10677 if (ARITHMETIC_P (tem)
10678 && GET_CODE (XEXP (tem, 0)) == CLOBBER
10679 && GET_CODE (XEXP (tem, 1)) == CLOBBER)
10680 tem = XEXP (tem, 0);
10681 else if (count_occurrences (value, reg, 1) >= 2)
10683 /* If there are two or more occurrences of REG in VALUE,
10684 prevent the value from growing too much. */
10685 if (count_rtxs (tem) > MAX_LAST_VALUE_RTL)
10686 tem = gen_rtx_CLOBBER (GET_MODE (tem), const0_rtx);
10689 value = replace_rtx (copy_rtx (value), reg, tem);
10693 /* For each register modified, show we don't know its value, that
10694 we don't know about its bitwise content, that its value has been
10695 updated, and that we don't know the location of the death of the
10697 for (i = regno; i < endregno; i++)
10700 reg_stat[i].last_set = insn;
10702 reg_stat[i].last_set_value = 0;
10703 reg_stat[i].last_set_mode = 0;
10704 reg_stat[i].last_set_nonzero_bits = 0;
10705 reg_stat[i].last_set_sign_bit_copies = 0;
10706 reg_stat[i].last_death = 0;
10709 /* Mark registers that are being referenced in this value. */
10711 update_table_tick (value);
10713 /* Now update the status of each register being set.
10714 If someone is using this register in this block, set this register
10715 to invalid since we will get confused between the two lives in this
10716 basic block. This makes using this register always invalid. In cse, we
10717 scan the table to invalidate all entries using this register, but this
10718 is too much work for us. */
10720 for (i = regno; i < endregno; i++)
10722 reg_stat[i].last_set_label = label_tick;
10723 if (value && reg_stat[i].last_set_table_tick == label_tick)
10724 reg_stat[i].last_set_invalid = 1;
10726 reg_stat[i].last_set_invalid = 0;
10729 /* The value being assigned might refer to X (like in "x++;"). In that
10730 case, we must replace it with (clobber (const_int 0)) to prevent
10732 if (value && ! get_last_value_validate (&value, insn,
10733 reg_stat[regno].last_set_label, 0))
10735 value = copy_rtx (value);
10736 if (! get_last_value_validate (&value, insn,
10737 reg_stat[regno].last_set_label, 1))
10741 /* For the main register being modified, update the value, the mode, the
10742 nonzero bits, and the number of sign bit copies. */
10744 reg_stat[regno].last_set_value = value;
10748 enum machine_mode mode = GET_MODE (reg);
10749 subst_low_cuid = INSN_CUID (insn);
10750 reg_stat[regno].last_set_mode = mode;
10751 if (GET_MODE_CLASS (mode) == MODE_INT
10752 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
10753 mode = nonzero_bits_mode;
10754 reg_stat[regno].last_set_nonzero_bits = nonzero_bits (value, mode);
10755 reg_stat[regno].last_set_sign_bit_copies
10756 = num_sign_bit_copies (value, GET_MODE (reg));
10760 /* Called via note_stores from record_dead_and_set_regs to handle one
10761 SET or CLOBBER in an insn. DATA is the instruction in which the
10762 set is occurring. */
10765 record_dead_and_set_regs_1 (rtx dest, rtx setter, void *data)
10767 rtx record_dead_insn = (rtx) data;
10769 if (GET_CODE (dest) == SUBREG)
10770 dest = SUBREG_REG (dest);
10774 /* If we are setting the whole register, we know its value. Otherwise
10775 show that we don't know the value. We can handle SUBREG in
10777 if (GET_CODE (setter) == SET && dest == SET_DEST (setter))
10778 record_value_for_reg (dest, record_dead_insn, SET_SRC (setter));
10779 else if (GET_CODE (setter) == SET
10780 && GET_CODE (SET_DEST (setter)) == SUBREG
10781 && SUBREG_REG (SET_DEST (setter)) == dest
10782 && GET_MODE_BITSIZE (GET_MODE (dest)) <= BITS_PER_WORD
10783 && subreg_lowpart_p (SET_DEST (setter)))
10784 record_value_for_reg (dest, record_dead_insn,
10785 gen_lowpart (GET_MODE (dest),
10786 SET_SRC (setter)));
10788 record_value_for_reg (dest, record_dead_insn, NULL_RTX);
10790 else if (MEM_P (dest)
10791 /* Ignore pushes, they clobber nothing. */
10792 && ! push_operand (dest, GET_MODE (dest)))
10793 mem_last_set = INSN_CUID (record_dead_insn);
10796 /* Update the records of when each REG was most recently set or killed
10797 for the things done by INSN. This is the last thing done in processing
10798 INSN in the combiner loop.
10800 We update reg_stat[], in particular fields last_set, last_set_value,
10801 last_set_mode, last_set_nonzero_bits, last_set_sign_bit_copies,
10802 last_death, and also the similar information mem_last_set (which insn
10803 most recently modified memory) and last_call_cuid (which insn was the
10804 most recent subroutine call). */
10807 record_dead_and_set_regs (rtx insn)
10812 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
10814 if (REG_NOTE_KIND (link) == REG_DEAD
10815 && REG_P (XEXP (link, 0)))
10817 unsigned int regno = REGNO (XEXP (link, 0));
10818 unsigned int endregno
10819 = regno + (regno < FIRST_PSEUDO_REGISTER
10820 ? hard_regno_nregs[regno][GET_MODE (XEXP (link, 0))]
10823 for (i = regno; i < endregno; i++)
10824 reg_stat[i].last_death = insn;
10826 else if (REG_NOTE_KIND (link) == REG_INC)
10827 record_value_for_reg (XEXP (link, 0), insn, NULL_RTX);
10832 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
10833 if (TEST_HARD_REG_BIT (regs_invalidated_by_call, i))
10835 reg_stat[i].last_set_value = 0;
10836 reg_stat[i].last_set_mode = 0;
10837 reg_stat[i].last_set_nonzero_bits = 0;
10838 reg_stat[i].last_set_sign_bit_copies = 0;
10839 reg_stat[i].last_death = 0;
10842 last_call_cuid = mem_last_set = INSN_CUID (insn);
10844 /* Don't bother recording what this insn does. It might set the
10845 return value register, but we can't combine into a call
10846 pattern anyway, so there's no point trying (and it may cause
10847 a crash, if e.g. we wind up asking for last_set_value of a
10848 SUBREG of the return value register). */
10852 note_stores (PATTERN (insn), record_dead_and_set_regs_1, insn);
10855 /* If a SUBREG has the promoted bit set, it is in fact a property of the
10856 register present in the SUBREG, so for each such SUBREG go back and
10857 adjust nonzero and sign bit information of the registers that are
10858 known to have some zero/sign bits set.
10860 This is needed because when combine blows the SUBREGs away, the
10861 information on zero/sign bits is lost and further combines can be
10862 missed because of that. */
10865 record_promoted_value (rtx insn, rtx subreg)
10868 unsigned int regno = REGNO (SUBREG_REG (subreg));
10869 enum machine_mode mode = GET_MODE (subreg);
10871 if (GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT)
10874 for (links = LOG_LINKS (insn); links;)
10876 insn = XEXP (links, 0);
10877 set = single_set (insn);
10879 if (! set || !REG_P (SET_DEST (set))
10880 || REGNO (SET_DEST (set)) != regno
10881 || GET_MODE (SET_DEST (set)) != GET_MODE (SUBREG_REG (subreg)))
10883 links = XEXP (links, 1);
10887 if (reg_stat[regno].last_set == insn)
10889 if (SUBREG_PROMOTED_UNSIGNED_P (subreg) > 0)
10890 reg_stat[regno].last_set_nonzero_bits &= GET_MODE_MASK (mode);
10893 if (REG_P (SET_SRC (set)))
10895 regno = REGNO (SET_SRC (set));
10896 links = LOG_LINKS (insn);
10903 /* Scan X for promoted SUBREGs. For each one found,
10904 note what it implies to the registers used in it. */
10907 check_promoted_subreg (rtx insn, rtx x)
10909 if (GET_CODE (x) == SUBREG && SUBREG_PROMOTED_VAR_P (x)
10910 && REG_P (SUBREG_REG (x)))
10911 record_promoted_value (insn, x);
10914 const char *format = GET_RTX_FORMAT (GET_CODE (x));
10917 for (i = 0; i < GET_RTX_LENGTH (GET_CODE (x)); i++)
10921 check_promoted_subreg (insn, XEXP (x, i));
10925 if (XVEC (x, i) != 0)
10926 for (j = 0; j < XVECLEN (x, i); j++)
10927 check_promoted_subreg (insn, XVECEXP (x, i, j));
10933 /* Utility routine for the following function. Verify that all the registers
10934 mentioned in *LOC are valid when *LOC was part of a value set when
10935 label_tick == TICK. Return 0 if some are not.
10937 If REPLACE is nonzero, replace the invalid reference with
10938 (clobber (const_int 0)) and return 1. This replacement is useful because
10939 we often can get useful information about the form of a value (e.g., if
10940 it was produced by a shift that always produces -1 or 0) even though
10941 we don't know exactly what registers it was produced from. */
10944 get_last_value_validate (rtx *loc, rtx insn, int tick, int replace)
10947 const char *fmt = GET_RTX_FORMAT (GET_CODE (x));
10948 int len = GET_RTX_LENGTH (GET_CODE (x));
10953 unsigned int regno = REGNO (x);
10954 unsigned int endregno
10955 = regno + (regno < FIRST_PSEUDO_REGISTER
10956 ? hard_regno_nregs[regno][GET_MODE (x)] : 1);
10959 for (j = regno; j < endregno; j++)
10960 if (reg_stat[j].last_set_invalid
10961 /* If this is a pseudo-register that was only set once and not
10962 live at the beginning of the function, it is always valid. */
10963 || (! (regno >= FIRST_PSEUDO_REGISTER
10964 && REG_N_SETS (regno) == 1
10965 && (! REGNO_REG_SET_P
10966 (ENTRY_BLOCK_PTR->next_bb->il.rtl->global_live_at_start,
10968 && reg_stat[j].last_set_label > tick))
10971 *loc = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
10977 /* If this is a memory reference, make sure that there were
10978 no stores after it that might have clobbered the value. We don't
10979 have alias info, so we assume any store invalidates it. */
10980 else if (MEM_P (x) && !MEM_READONLY_P (x)
10981 && INSN_CUID (insn) <= mem_last_set)
10984 *loc = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
10988 for (i = 0; i < len; i++)
10992 /* Check for identical subexpressions. If x contains
10993 identical subexpression we only have to traverse one of
10995 if (i == 1 && ARITHMETIC_P (x))
10997 /* Note that at this point x0 has already been checked
10998 and found valid. */
10999 rtx x0 = XEXP (x, 0);
11000 rtx x1 = XEXP (x, 1);
11002 /* If x0 and x1 are identical then x is also valid. */
11006 /* If x1 is identical to a subexpression of x0 then
11007 while checking x0, x1 has already been checked. Thus
11008 it is valid and so as x. */
11009 if (ARITHMETIC_P (x0)
11010 && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1)))
11013 /* If x0 is identical to a subexpression of x1 then x is
11014 valid iff the rest of x1 is valid. */
11015 if (ARITHMETIC_P (x1)
11016 && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1)))
11018 get_last_value_validate (&XEXP (x1,
11019 x0 == XEXP (x1, 0) ? 1 : 0),
11020 insn, tick, replace);
11023 if (get_last_value_validate (&XEXP (x, i), insn, tick,
11027 /* Don't bother with these. They shouldn't occur anyway. */
11028 else if (fmt[i] == 'E')
11032 /* If we haven't found a reason for it to be invalid, it is valid. */
11036 /* Get the last value assigned to X, if known. Some registers
11037 in the value may be replaced with (clobber (const_int 0)) if their value
11038 is known longer known reliably. */
11041 get_last_value (rtx x)
11043 unsigned int regno;
11046 /* If this is a non-paradoxical SUBREG, get the value of its operand and
11047 then convert it to the desired mode. If this is a paradoxical SUBREG,
11048 we cannot predict what values the "extra" bits might have. */
11049 if (GET_CODE (x) == SUBREG
11050 && subreg_lowpart_p (x)
11051 && (GET_MODE_SIZE (GET_MODE (x))
11052 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
11053 && (value = get_last_value (SUBREG_REG (x))) != 0)
11054 return gen_lowpart (GET_MODE (x), value);
11060 value = reg_stat[regno].last_set_value;
11062 /* If we don't have a value, or if it isn't for this basic block and
11063 it's either a hard register, set more than once, or it's a live
11064 at the beginning of the function, return 0.
11066 Because if it's not live at the beginning of the function then the reg
11067 is always set before being used (is never used without being set).
11068 And, if it's set only once, and it's always set before use, then all
11069 uses must have the same last value, even if it's not from this basic
11073 || (reg_stat[regno].last_set_label != label_tick
11074 && (regno < FIRST_PSEUDO_REGISTER
11075 || REG_N_SETS (regno) != 1
11076 || (REGNO_REG_SET_P
11077 (ENTRY_BLOCK_PTR->next_bb->il.rtl->global_live_at_start,
11081 /* If the value was set in a later insn than the ones we are processing,
11082 we can't use it even if the register was only set once. */
11083 if (INSN_CUID (reg_stat[regno].last_set) >= subst_low_cuid)
11086 /* If the value has all its registers valid, return it. */
11087 if (get_last_value_validate (&value, reg_stat[regno].last_set,
11088 reg_stat[regno].last_set_label, 0))
11091 /* Otherwise, make a copy and replace any invalid register with
11092 (clobber (const_int 0)). If that fails for some reason, return 0. */
11094 value = copy_rtx (value);
11095 if (get_last_value_validate (&value, reg_stat[regno].last_set,
11096 reg_stat[regno].last_set_label, 1))
11102 /* Return nonzero if expression X refers to a REG or to memory
11103 that is set in an instruction more recent than FROM_CUID. */
11106 use_crosses_set_p (rtx x, int from_cuid)
11110 enum rtx_code code = GET_CODE (x);
11114 unsigned int regno = REGNO (x);
11115 unsigned endreg = regno + (regno < FIRST_PSEUDO_REGISTER
11116 ? hard_regno_nregs[regno][GET_MODE (x)] : 1);
11118 #ifdef PUSH_ROUNDING
11119 /* Don't allow uses of the stack pointer to be moved,
11120 because we don't know whether the move crosses a push insn. */
11121 if (regno == STACK_POINTER_REGNUM && PUSH_ARGS)
11124 for (; regno < endreg; regno++)
11125 if (reg_stat[regno].last_set
11126 && INSN_CUID (reg_stat[regno].last_set) > from_cuid)
11131 if (code == MEM && mem_last_set > from_cuid)
11134 fmt = GET_RTX_FORMAT (code);
11136 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
11141 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
11142 if (use_crosses_set_p (XVECEXP (x, i, j), from_cuid))
11145 else if (fmt[i] == 'e'
11146 && use_crosses_set_p (XEXP (x, i), from_cuid))
11152 /* Define three variables used for communication between the following
11155 static unsigned int reg_dead_regno, reg_dead_endregno;
11156 static int reg_dead_flag;
11158 /* Function called via note_stores from reg_dead_at_p.
11160 If DEST is within [reg_dead_regno, reg_dead_endregno), set
11161 reg_dead_flag to 1 if X is a CLOBBER and to -1 it is a SET. */
11164 reg_dead_at_p_1 (rtx dest, rtx x, void *data ATTRIBUTE_UNUSED)
11166 unsigned int regno, endregno;
11171 regno = REGNO (dest);
11172 endregno = regno + (regno < FIRST_PSEUDO_REGISTER
11173 ? hard_regno_nregs[regno][GET_MODE (dest)] : 1);
11175 if (reg_dead_endregno > regno && reg_dead_regno < endregno)
11176 reg_dead_flag = (GET_CODE (x) == CLOBBER) ? 1 : -1;
11179 /* Return nonzero if REG is known to be dead at INSN.
11181 We scan backwards from INSN. If we hit a REG_DEAD note or a CLOBBER
11182 referencing REG, it is dead. If we hit a SET referencing REG, it is
11183 live. Otherwise, see if it is live or dead at the start of the basic
11184 block we are in. Hard regs marked as being live in NEWPAT_USED_REGS
11185 must be assumed to be always live. */
11188 reg_dead_at_p (rtx reg, rtx insn)
11193 /* Set variables for reg_dead_at_p_1. */
11194 reg_dead_regno = REGNO (reg);
11195 reg_dead_endregno = reg_dead_regno + (reg_dead_regno < FIRST_PSEUDO_REGISTER
11196 ? hard_regno_nregs[reg_dead_regno]
11202 /* Check that reg isn't mentioned in NEWPAT_USED_REGS. For fixed registers
11203 we allow the machine description to decide whether use-and-clobber
11204 patterns are OK. */
11205 if (reg_dead_regno < FIRST_PSEUDO_REGISTER)
11207 for (i = reg_dead_regno; i < reg_dead_endregno; i++)
11208 if (!fixed_regs[i] && TEST_HARD_REG_BIT (newpat_used_regs, i))
11212 /* Scan backwards until we find a REG_DEAD note, SET, CLOBBER, label, or
11213 beginning of function. */
11214 for (; insn && !LABEL_P (insn) && !BARRIER_P (insn);
11215 insn = prev_nonnote_insn (insn))
11217 note_stores (PATTERN (insn), reg_dead_at_p_1, NULL);
11219 return reg_dead_flag == 1 ? 1 : 0;
11221 if (find_regno_note (insn, REG_DEAD, reg_dead_regno))
11225 /* Get the basic block that we were in. */
11227 block = ENTRY_BLOCK_PTR->next_bb;
11230 FOR_EACH_BB (block)
11231 if (insn == BB_HEAD (block))
11234 if (block == EXIT_BLOCK_PTR)
11238 for (i = reg_dead_regno; i < reg_dead_endregno; i++)
11239 if (REGNO_REG_SET_P (block->il.rtl->global_live_at_start, i))
11245 /* Note hard registers in X that are used. This code is similar to
11246 that in flow.c, but much simpler since we don't care about pseudos. */
11249 mark_used_regs_combine (rtx x)
11251 RTX_CODE code = GET_CODE (x);
11252 unsigned int regno;
11265 case ADDR_DIFF_VEC:
11268 /* CC0 must die in the insn after it is set, so we don't need to take
11269 special note of it here. */
11275 /* If we are clobbering a MEM, mark any hard registers inside the
11276 address as used. */
11277 if (MEM_P (XEXP (x, 0)))
11278 mark_used_regs_combine (XEXP (XEXP (x, 0), 0));
11283 /* A hard reg in a wide mode may really be multiple registers.
11284 If so, mark all of them just like the first. */
11285 if (regno < FIRST_PSEUDO_REGISTER)
11287 unsigned int endregno, r;
11289 /* None of this applies to the stack, frame or arg pointers. */
11290 if (regno == STACK_POINTER_REGNUM
11291 #if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM
11292 || regno == HARD_FRAME_POINTER_REGNUM
11294 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
11295 || (regno == ARG_POINTER_REGNUM && fixed_regs[regno])
11297 || regno == FRAME_POINTER_REGNUM)
11300 endregno = regno + hard_regno_nregs[regno][GET_MODE (x)];
11301 for (r = regno; r < endregno; r++)
11302 SET_HARD_REG_BIT (newpat_used_regs, r);
11308 /* If setting a MEM, or a SUBREG of a MEM, then note any hard regs in
11310 rtx testreg = SET_DEST (x);
11312 while (GET_CODE (testreg) == SUBREG
11313 || GET_CODE (testreg) == ZERO_EXTRACT
11314 || GET_CODE (testreg) == STRICT_LOW_PART)
11315 testreg = XEXP (testreg, 0);
11317 if (MEM_P (testreg))
11318 mark_used_regs_combine (XEXP (testreg, 0));
11320 mark_used_regs_combine (SET_SRC (x));
11328 /* Recursively scan the operands of this expression. */
11331 const char *fmt = GET_RTX_FORMAT (code);
11333 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
11336 mark_used_regs_combine (XEXP (x, i));
11337 else if (fmt[i] == 'E')
11341 for (j = 0; j < XVECLEN (x, i); j++)
11342 mark_used_regs_combine (XVECEXP (x, i, j));
11348 /* Remove register number REGNO from the dead registers list of INSN.
11350 Return the note used to record the death, if there was one. */
11353 remove_death (unsigned int regno, rtx insn)
11355 rtx note = find_regno_note (insn, REG_DEAD, regno);
11359 REG_N_DEATHS (regno)--;
11360 remove_note (insn, note);
11366 /* For each register (hardware or pseudo) used within expression X, if its
11367 death is in an instruction with cuid between FROM_CUID (inclusive) and
11368 TO_INSN (exclusive), put a REG_DEAD note for that register in the
11369 list headed by PNOTES.
11371 That said, don't move registers killed by maybe_kill_insn.
11373 This is done when X is being merged by combination into TO_INSN. These
11374 notes will then be distributed as needed. */
11377 move_deaths (rtx x, rtx maybe_kill_insn, int from_cuid, rtx to_insn,
11382 enum rtx_code code = GET_CODE (x);
11386 unsigned int regno = REGNO (x);
11387 rtx where_dead = reg_stat[regno].last_death;
11388 rtx before_dead, after_dead;
11390 /* Don't move the register if it gets killed in between from and to. */
11391 if (maybe_kill_insn && reg_set_p (x, maybe_kill_insn)
11392 && ! reg_referenced_p (x, maybe_kill_insn))
11395 /* WHERE_DEAD could be a USE insn made by combine, so first we
11396 make sure that we have insns with valid INSN_CUID values. */
11397 before_dead = where_dead;
11398 while (before_dead && INSN_UID (before_dead) > max_uid_cuid)
11399 before_dead = PREV_INSN (before_dead);
11401 after_dead = where_dead;
11402 while (after_dead && INSN_UID (after_dead) > max_uid_cuid)
11403 after_dead = NEXT_INSN (after_dead);
11405 if (before_dead && after_dead
11406 && INSN_CUID (before_dead) >= from_cuid
11407 && (INSN_CUID (after_dead) < INSN_CUID (to_insn)
11408 || (where_dead != after_dead
11409 && INSN_CUID (after_dead) == INSN_CUID (to_insn))))
11411 rtx note = remove_death (regno, where_dead);
11413 /* It is possible for the call above to return 0. This can occur
11414 when last_death points to I2 or I1 that we combined with.
11415 In that case make a new note.
11417 We must also check for the case where X is a hard register
11418 and NOTE is a death note for a range of hard registers
11419 including X. In that case, we must put REG_DEAD notes for
11420 the remaining registers in place of NOTE. */
11422 if (note != 0 && regno < FIRST_PSEUDO_REGISTER
11423 && (GET_MODE_SIZE (GET_MODE (XEXP (note, 0)))
11424 > GET_MODE_SIZE (GET_MODE (x))))
11426 unsigned int deadregno = REGNO (XEXP (note, 0));
11427 unsigned int deadend
11428 = (deadregno + hard_regno_nregs[deadregno]
11429 [GET_MODE (XEXP (note, 0))]);
11430 unsigned int ourend
11431 = regno + hard_regno_nregs[regno][GET_MODE (x)];
11434 for (i = deadregno; i < deadend; i++)
11435 if (i < regno || i >= ourend)
11436 REG_NOTES (where_dead)
11437 = gen_rtx_EXPR_LIST (REG_DEAD,
11439 REG_NOTES (where_dead));
11442 /* If we didn't find any note, or if we found a REG_DEAD note that
11443 covers only part of the given reg, and we have a multi-reg hard
11444 register, then to be safe we must check for REG_DEAD notes
11445 for each register other than the first. They could have
11446 their own REG_DEAD notes lying around. */
11447 else if ((note == 0
11449 && (GET_MODE_SIZE (GET_MODE (XEXP (note, 0)))
11450 < GET_MODE_SIZE (GET_MODE (x)))))
11451 && regno < FIRST_PSEUDO_REGISTER
11452 && hard_regno_nregs[regno][GET_MODE (x)] > 1)
11454 unsigned int ourend
11455 = regno + hard_regno_nregs[regno][GET_MODE (x)];
11456 unsigned int i, offset;
11460 offset = hard_regno_nregs[regno][GET_MODE (XEXP (note, 0))];
11464 for (i = regno + offset; i < ourend; i++)
11465 move_deaths (regno_reg_rtx[i],
11466 maybe_kill_insn, from_cuid, to_insn, &oldnotes);
11469 if (note != 0 && GET_MODE (XEXP (note, 0)) == GET_MODE (x))
11471 XEXP (note, 1) = *pnotes;
11475 *pnotes = gen_rtx_EXPR_LIST (REG_DEAD, x, *pnotes);
11477 REG_N_DEATHS (regno)++;
11483 else if (GET_CODE (x) == SET)
11485 rtx dest = SET_DEST (x);
11487 move_deaths (SET_SRC (x), maybe_kill_insn, from_cuid, to_insn, pnotes);
11489 /* In the case of a ZERO_EXTRACT, a STRICT_LOW_PART, or a SUBREG
11490 that accesses one word of a multi-word item, some
11491 piece of everything register in the expression is used by
11492 this insn, so remove any old death. */
11493 /* ??? So why do we test for equality of the sizes? */
11495 if (GET_CODE (dest) == ZERO_EXTRACT
11496 || GET_CODE (dest) == STRICT_LOW_PART
11497 || (GET_CODE (dest) == SUBREG
11498 && (((GET_MODE_SIZE (GET_MODE (dest))
11499 + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
11500 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (dest)))
11501 + UNITS_PER_WORD - 1) / UNITS_PER_WORD))))
11503 move_deaths (dest, maybe_kill_insn, from_cuid, to_insn, pnotes);
11507 /* If this is some other SUBREG, we know it replaces the entire
11508 value, so use that as the destination. */
11509 if (GET_CODE (dest) == SUBREG)
11510 dest = SUBREG_REG (dest);
11512 /* If this is a MEM, adjust deaths of anything used in the address.
11513 For a REG (the only other possibility), the entire value is
11514 being replaced so the old value is not used in this insn. */
11517 move_deaths (XEXP (dest, 0), maybe_kill_insn, from_cuid,
11522 else if (GET_CODE (x) == CLOBBER)
11525 len = GET_RTX_LENGTH (code);
11526 fmt = GET_RTX_FORMAT (code);
11528 for (i = 0; i < len; i++)
11533 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
11534 move_deaths (XVECEXP (x, i, j), maybe_kill_insn, from_cuid,
11537 else if (fmt[i] == 'e')
11538 move_deaths (XEXP (x, i), maybe_kill_insn, from_cuid, to_insn, pnotes);
11542 /* Return 1 if X is the target of a bit-field assignment in BODY, the
11543 pattern of an insn. X must be a REG. */
11546 reg_bitfield_target_p (rtx x, rtx body)
11550 if (GET_CODE (body) == SET)
11552 rtx dest = SET_DEST (body);
11554 unsigned int regno, tregno, endregno, endtregno;
11556 if (GET_CODE (dest) == ZERO_EXTRACT)
11557 target = XEXP (dest, 0);
11558 else if (GET_CODE (dest) == STRICT_LOW_PART)
11559 target = SUBREG_REG (XEXP (dest, 0));
11563 if (GET_CODE (target) == SUBREG)
11564 target = SUBREG_REG (target);
11566 if (!REG_P (target))
11569 tregno = REGNO (target), regno = REGNO (x);
11570 if (tregno >= FIRST_PSEUDO_REGISTER || regno >= FIRST_PSEUDO_REGISTER)
11571 return target == x;
11573 endtregno = tregno + hard_regno_nregs[tregno][GET_MODE (target)];
11574 endregno = regno + hard_regno_nregs[regno][GET_MODE (x)];
11576 return endregno > tregno && regno < endtregno;
11579 else if (GET_CODE (body) == PARALLEL)
11580 for (i = XVECLEN (body, 0) - 1; i >= 0; i--)
11581 if (reg_bitfield_target_p (x, XVECEXP (body, 0, i)))
11587 /* Given a chain of REG_NOTES originally from FROM_INSN, try to place them
11588 as appropriate. I3 and I2 are the insns resulting from the combination
11589 insns including FROM (I2 may be zero).
11591 ELIM_I2 and ELIM_I1 are either zero or registers that we know will
11592 not need REG_DEAD notes because they are being substituted for. This
11593 saves searching in the most common cases.
11595 Each note in the list is either ignored or placed on some insns, depending
11596 on the type of note. */
11599 distribute_notes (rtx notes, rtx from_insn, rtx i3, rtx i2, rtx elim_i2,
11602 rtx note, next_note;
11605 for (note = notes; note; note = next_note)
11607 rtx place = 0, place2 = 0;
11609 /* If this NOTE references a pseudo register, ensure it references
11610 the latest copy of that register. */
11611 if (XEXP (note, 0) && REG_P (XEXP (note, 0))
11612 && REGNO (XEXP (note, 0)) >= FIRST_PSEUDO_REGISTER)
11613 XEXP (note, 0) = regno_reg_rtx[REGNO (XEXP (note, 0))];
11615 next_note = XEXP (note, 1);
11616 switch (REG_NOTE_KIND (note))
11620 /* Doesn't matter much where we put this, as long as it's somewhere.
11621 It is preferable to keep these notes on branches, which is most
11622 likely to be i3. */
11626 case REG_VALUE_PROFILE:
11627 /* Just get rid of this note, as it is unused later anyway. */
11630 case REG_NON_LOCAL_GOTO:
11635 gcc_assert (i2 && JUMP_P (i2));
11640 case REG_EH_REGION:
11641 /* These notes must remain with the call or trapping instruction. */
11644 else if (i2 && CALL_P (i2))
11648 gcc_assert (flag_non_call_exceptions);
11649 if (may_trap_p (i3))
11651 else if (i2 && may_trap_p (i2))
11653 /* ??? Otherwise assume we've combined things such that we
11654 can now prove that the instructions can't trap. Drop the
11655 note in this case. */
11661 /* These notes must remain with the call. It should not be
11662 possible for both I2 and I3 to be a call. */
11667 gcc_assert (i2 && CALL_P (i2));
11673 /* Any clobbers for i3 may still exist, and so we must process
11674 REG_UNUSED notes from that insn.
11676 Any clobbers from i2 or i1 can only exist if they were added by
11677 recog_for_combine. In that case, recog_for_combine created the
11678 necessary REG_UNUSED notes. Trying to keep any original
11679 REG_UNUSED notes from these insns can cause incorrect output
11680 if it is for the same register as the original i3 dest.
11681 In that case, we will notice that the register is set in i3,
11682 and then add a REG_UNUSED note for the destination of i3, which
11683 is wrong. However, it is possible to have REG_UNUSED notes from
11684 i2 or i1 for register which were both used and clobbered, so
11685 we keep notes from i2 or i1 if they will turn into REG_DEAD
11688 /* If this register is set or clobbered in I3, put the note there
11689 unless there is one already. */
11690 if (reg_set_p (XEXP (note, 0), PATTERN (i3)))
11692 if (from_insn != i3)
11695 if (! (REG_P (XEXP (note, 0))
11696 ? find_regno_note (i3, REG_UNUSED, REGNO (XEXP (note, 0)))
11697 : find_reg_note (i3, REG_UNUSED, XEXP (note, 0))))
11700 /* Otherwise, if this register is used by I3, then this register
11701 now dies here, so we must put a REG_DEAD note here unless there
11703 else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3))
11704 && ! (REG_P (XEXP (note, 0))
11705 ? find_regno_note (i3, REG_DEAD,
11706 REGNO (XEXP (note, 0)))
11707 : find_reg_note (i3, REG_DEAD, XEXP (note, 0))))
11709 PUT_REG_NOTE_KIND (note, REG_DEAD);
11717 /* These notes say something about results of an insn. We can
11718 only support them if they used to be on I3 in which case they
11719 remain on I3. Otherwise they are ignored.
11721 If the note refers to an expression that is not a constant, we
11722 must also ignore the note since we cannot tell whether the
11723 equivalence is still true. It might be possible to do
11724 slightly better than this (we only have a problem if I2DEST
11725 or I1DEST is present in the expression), but it doesn't
11726 seem worth the trouble. */
11728 if (from_insn == i3
11729 && (XEXP (note, 0) == 0 || CONSTANT_P (XEXP (note, 0))))
11734 case REG_NO_CONFLICT:
11735 /* These notes say something about how a register is used. They must
11736 be present on any use of the register in I2 or I3. */
11737 if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3)))
11740 if (i2 && reg_mentioned_p (XEXP (note, 0), PATTERN (i2)))
11750 /* This can show up in several ways -- either directly in the
11751 pattern, or hidden off in the constant pool with (or without?)
11752 a REG_EQUAL note. */
11753 /* ??? Ignore the without-reg_equal-note problem for now. */
11754 if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3))
11755 || ((tem = find_reg_note (i3, REG_EQUAL, NULL_RTX))
11756 && GET_CODE (XEXP (tem, 0)) == LABEL_REF
11757 && XEXP (XEXP (tem, 0), 0) == XEXP (note, 0)))
11761 && (reg_mentioned_p (XEXP (note, 0), PATTERN (i2))
11762 || ((tem = find_reg_note (i2, REG_EQUAL, NULL_RTX))
11763 && GET_CODE (XEXP (tem, 0)) == LABEL_REF
11764 && XEXP (XEXP (tem, 0), 0) == XEXP (note, 0))))
11772 /* Don't attach REG_LABEL note to a JUMP_INSN. Add
11773 a JUMP_LABEL instead or decrement LABEL_NUSES. */
11774 if (place && JUMP_P (place))
11776 rtx label = JUMP_LABEL (place);
11779 JUMP_LABEL (place) = XEXP (note, 0);
11782 gcc_assert (label == XEXP (note, 0));
11783 if (LABEL_P (label))
11784 LABEL_NUSES (label)--;
11788 if (place2 && JUMP_P (place2))
11790 rtx label = JUMP_LABEL (place2);
11793 JUMP_LABEL (place2) = XEXP (note, 0);
11796 gcc_assert (label == XEXP (note, 0));
11797 if (LABEL_P (label))
11798 LABEL_NUSES (label)--;
11805 /* This note says something about the value of a register prior
11806 to the execution of an insn. It is too much trouble to see
11807 if the note is still correct in all situations. It is better
11808 to simply delete it. */
11812 /* If the insn previously containing this note still exists,
11813 put it back where it was. Otherwise move it to the previous
11814 insn. Adjust the corresponding REG_LIBCALL note. */
11815 if (!NOTE_P (from_insn))
11819 tem = find_reg_note (XEXP (note, 0), REG_LIBCALL, NULL_RTX);
11820 place = prev_real_insn (from_insn);
11822 XEXP (tem, 0) = place;
11823 /* If we're deleting the last remaining instruction of a
11824 libcall sequence, don't add the notes. */
11825 else if (XEXP (note, 0) == from_insn)
11827 /* Don't add the dangling REG_RETVAL note. */
11834 /* This is handled similarly to REG_RETVAL. */
11835 if (!NOTE_P (from_insn))
11839 tem = find_reg_note (XEXP (note, 0), REG_RETVAL, NULL_RTX);
11840 place = next_real_insn (from_insn);
11842 XEXP (tem, 0) = place;
11843 /* If we're deleting the last remaining instruction of a
11844 libcall sequence, don't add the notes. */
11845 else if (XEXP (note, 0) == from_insn)
11847 /* Don't add the dangling REG_LIBCALL note. */
11854 /* If the register is used as an input in I3, it dies there.
11855 Similarly for I2, if it is nonzero and adjacent to I3.
11857 If the register is not used as an input in either I3 or I2
11858 and it is not one of the registers we were supposed to eliminate,
11859 there are two possibilities. We might have a non-adjacent I2
11860 or we might have somehow eliminated an additional register
11861 from a computation. For example, we might have had A & B where
11862 we discover that B will always be zero. In this case we will
11863 eliminate the reference to A.
11865 In both cases, we must search to see if we can find a previous
11866 use of A and put the death note there. */
11869 && CALL_P (from_insn)
11870 && find_reg_fusage (from_insn, USE, XEXP (note, 0)))
11872 else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3)))
11874 else if (i2 != 0 && next_nonnote_insn (i2) == i3
11875 && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
11879 && (rtx_equal_p (XEXP (note, 0), elim_i2)
11880 || rtx_equal_p (XEXP (note, 0), elim_i1)))
11885 basic_block bb = this_basic_block;
11887 /* You might think you could search back from FROM_INSN
11888 rather than from I3, but combine tries to split invalid
11889 combined instructions. This can result in the old I2
11890 or I1 moving later in the insn sequence. */
11891 for (tem = PREV_INSN (i3); place == 0; tem = PREV_INSN (tem))
11893 if (! INSN_P (tem))
11895 if (tem == BB_HEAD (bb))
11900 /* If the register is being set at TEM, see if that is all
11901 TEM is doing. If so, delete TEM. Otherwise, make this
11902 into a REG_UNUSED note instead. Don't delete sets to
11903 global register vars. */
11904 if ((REGNO (XEXP (note, 0)) >= FIRST_PSEUDO_REGISTER
11905 || !global_regs[REGNO (XEXP (note, 0))])
11906 && reg_set_p (XEXP (note, 0), PATTERN (tem)))
11908 rtx set = single_set (tem);
11909 rtx inner_dest = 0;
11911 rtx cc0_setter = NULL_RTX;
11915 for (inner_dest = SET_DEST (set);
11916 (GET_CODE (inner_dest) == STRICT_LOW_PART
11917 || GET_CODE (inner_dest) == SUBREG
11918 || GET_CODE (inner_dest) == ZERO_EXTRACT);
11919 inner_dest = XEXP (inner_dest, 0))
11922 /* Verify that it was the set, and not a clobber that
11923 modified the register.
11925 CC0 targets must be careful to maintain setter/user
11926 pairs. If we cannot delete the setter due to side
11927 effects, mark the user with an UNUSED note instead
11930 if (set != 0 && ! side_effects_p (SET_SRC (set))
11931 && rtx_equal_p (XEXP (note, 0), inner_dest)
11933 && (! reg_mentioned_p (cc0_rtx, SET_SRC (set))
11934 || ((cc0_setter = prev_cc0_setter (tem)) != NULL
11935 && sets_cc0_p (PATTERN (cc0_setter)) > 0))
11939 /* Move the notes and links of TEM elsewhere.
11940 This might delete other dead insns recursively.
11941 First set the pattern to something that won't use
11943 rtx old_notes = REG_NOTES (tem);
11945 PATTERN (tem) = pc_rtx;
11946 REG_NOTES (tem) = NULL;
11948 distribute_notes (old_notes, tem, tem, NULL_RTX,
11949 NULL_RTX, NULL_RTX);
11950 distribute_links (LOG_LINKS (tem));
11952 SET_INSN_DELETED (tem);
11955 /* Delete the setter too. */
11958 PATTERN (cc0_setter) = pc_rtx;
11959 old_notes = REG_NOTES (cc0_setter);
11960 REG_NOTES (cc0_setter) = NULL;
11962 distribute_notes (old_notes, cc0_setter,
11963 cc0_setter, NULL_RTX,
11964 NULL_RTX, NULL_RTX);
11965 distribute_links (LOG_LINKS (cc0_setter));
11967 SET_INSN_DELETED (cc0_setter);
11973 PUT_REG_NOTE_KIND (note, REG_UNUSED);
11975 /* If there isn't already a REG_UNUSED note, put one
11976 here. Do not place a REG_DEAD note, even if
11977 the register is also used here; that would not
11978 match the algorithm used in lifetime analysis
11979 and can cause the consistency check in the
11980 scheduler to fail. */
11981 if (! find_regno_note (tem, REG_UNUSED,
11982 REGNO (XEXP (note, 0))))
11987 else if (reg_referenced_p (XEXP (note, 0), PATTERN (tem))
11989 && find_reg_fusage (tem, USE, XEXP (note, 0))))
11991 /* This may not be the correct place for the death
11992 note if FROM_INSN is before TEM, and the reg is
11993 set between FROM_INSN and TEM. The reg might
11994 die two or more times. An existing death note
11995 means we are looking at the wrong live range. */
11997 && INSN_CUID (from_insn) < INSN_CUID (tem)
11998 && find_regno_note (tem, REG_DEAD,
11999 REGNO (XEXP (note, 0))))
12002 if (tem == BB_HEAD (bb))
12009 /* If we are doing a 3->2 combination, and we have a
12010 register which formerly died in i3 and was not used
12011 by i2, which now no longer dies in i3 and is used in
12012 i2 but does not die in i2, and place is between i2
12013 and i3, then we may need to move a link from place to
12015 if (i2 && INSN_UID (place) <= max_uid_cuid
12016 && INSN_CUID (place) > INSN_CUID (i2)
12018 && INSN_CUID (from_insn) > INSN_CUID (i2)
12019 && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
12021 rtx links = LOG_LINKS (place);
12022 LOG_LINKS (place) = 0;
12023 distribute_links (links);
12028 if (tem == BB_HEAD (bb))
12032 /* We haven't found an insn for the death note and it
12033 is still a REG_DEAD note, but we have hit the beginning
12034 of the block. If the existing life info says the reg
12035 was dead, there's nothing left to do. Otherwise, we'll
12036 need to do a global life update after combine. */
12037 if (REG_NOTE_KIND (note) == REG_DEAD && place == 0
12038 && REGNO_REG_SET_P (bb->il.rtl->global_live_at_start,
12039 REGNO (XEXP (note, 0))))
12040 SET_BIT (refresh_blocks, this_basic_block->index);
12043 /* If the register is set or already dead at PLACE, we needn't do
12044 anything with this note if it is still a REG_DEAD note.
12045 We check here if it is set at all, not if is it totally replaced,
12046 which is what `dead_or_set_p' checks, so also check for it being
12049 if (place && REG_NOTE_KIND (note) == REG_DEAD)
12051 unsigned int regno = REGNO (XEXP (note, 0));
12053 /* Similarly, if the instruction on which we want to place
12054 the note is a noop, we'll need do a global live update
12055 after we remove them in delete_noop_moves. */
12056 if (noop_move_p (place))
12057 SET_BIT (refresh_blocks, this_basic_block->index);
12059 if (dead_or_set_p (place, XEXP (note, 0))
12060 || reg_bitfield_target_p (XEXP (note, 0), PATTERN (place)))
12062 /* Unless the register previously died in PLACE, clear
12063 last_death. [I no longer understand why this is
12065 if (reg_stat[regno].last_death != place)
12066 reg_stat[regno].last_death = 0;
12070 reg_stat[regno].last_death = place;
12072 /* If this is a death note for a hard reg that is occupying
12073 multiple registers, ensure that we are still using all
12074 parts of the object. If we find a piece of the object
12075 that is unused, we must arrange for an appropriate REG_DEAD
12076 note to be added for it. However, we can't just emit a USE
12077 and tag the note to it, since the register might actually
12078 be dead; so we recourse, and the recursive call then finds
12079 the previous insn that used this register. */
12081 if (place && regno < FIRST_PSEUDO_REGISTER
12082 && hard_regno_nregs[regno][GET_MODE (XEXP (note, 0))] > 1)
12084 unsigned int endregno
12085 = regno + hard_regno_nregs[regno]
12086 [GET_MODE (XEXP (note, 0))];
12090 for (i = regno; i < endregno; i++)
12091 if ((! refers_to_regno_p (i, i + 1, PATTERN (place), 0)
12092 && ! find_regno_fusage (place, USE, i))
12093 || dead_or_set_regno_p (place, i))
12098 /* Put only REG_DEAD notes for pieces that are
12099 not already dead or set. */
12101 for (i = regno; i < endregno;
12102 i += hard_regno_nregs[i][reg_raw_mode[i]])
12104 rtx piece = regno_reg_rtx[i];
12105 basic_block bb = this_basic_block;
12107 if (! dead_or_set_p (place, piece)
12108 && ! reg_bitfield_target_p (piece,
12112 = gen_rtx_EXPR_LIST (REG_DEAD, piece, NULL_RTX);
12114 distribute_notes (new_note, place, place,
12115 NULL_RTX, NULL_RTX, NULL_RTX);
12117 else if (! refers_to_regno_p (i, i + 1,
12118 PATTERN (place), 0)
12119 && ! find_regno_fusage (place, USE, i))
12120 for (tem = PREV_INSN (place); ;
12121 tem = PREV_INSN (tem))
12123 if (! INSN_P (tem))
12125 if (tem == BB_HEAD (bb))
12127 SET_BIT (refresh_blocks,
12128 this_basic_block->index);
12133 if (dead_or_set_p (tem, piece)
12134 || reg_bitfield_target_p (piece,
12138 = gen_rtx_EXPR_LIST (REG_UNUSED, piece,
12153 /* Any other notes should not be present at this point in the
12155 gcc_unreachable ();
12160 XEXP (note, 1) = REG_NOTES (place);
12161 REG_NOTES (place) = note;
12163 else if ((REG_NOTE_KIND (note) == REG_DEAD
12164 || REG_NOTE_KIND (note) == REG_UNUSED)
12165 && REG_P (XEXP (note, 0)))
12166 REG_N_DEATHS (REGNO (XEXP (note, 0)))--;
12170 if ((REG_NOTE_KIND (note) == REG_DEAD
12171 || REG_NOTE_KIND (note) == REG_UNUSED)
12172 && REG_P (XEXP (note, 0)))
12173 REG_N_DEATHS (REGNO (XEXP (note, 0)))++;
12175 REG_NOTES (place2) = gen_rtx_fmt_ee (GET_CODE (note),
12176 REG_NOTE_KIND (note),
12178 REG_NOTES (place2));
12183 /* Similarly to above, distribute the LOG_LINKS that used to be present on
12184 I3, I2, and I1 to new locations. This is also called to add a link
12185 pointing at I3 when I3's destination is changed. */
12188 distribute_links (rtx links)
12190 rtx link, next_link;
12192 for (link = links; link; link = next_link)
12198 next_link = XEXP (link, 1);
12200 /* If the insn that this link points to is a NOTE or isn't a single
12201 set, ignore it. In the latter case, it isn't clear what we
12202 can do other than ignore the link, since we can't tell which
12203 register it was for. Such links wouldn't be used by combine
12206 It is not possible for the destination of the target of the link to
12207 have been changed by combine. The only potential of this is if we
12208 replace I3, I2, and I1 by I3 and I2. But in that case the
12209 destination of I2 also remains unchanged. */
12211 if (NOTE_P (XEXP (link, 0))
12212 || (set = single_set (XEXP (link, 0))) == 0)
12215 reg = SET_DEST (set);
12216 while (GET_CODE (reg) == SUBREG || GET_CODE (reg) == ZERO_EXTRACT
12217 || GET_CODE (reg) == STRICT_LOW_PART)
12218 reg = XEXP (reg, 0);
12220 /* A LOG_LINK is defined as being placed on the first insn that uses
12221 a register and points to the insn that sets the register. Start
12222 searching at the next insn after the target of the link and stop
12223 when we reach a set of the register or the end of the basic block.
12225 Note that this correctly handles the link that used to point from
12226 I3 to I2. Also note that not much searching is typically done here
12227 since most links don't point very far away. */
12229 for (insn = NEXT_INSN (XEXP (link, 0));
12230 (insn && (this_basic_block->next_bb == EXIT_BLOCK_PTR
12231 || BB_HEAD (this_basic_block->next_bb) != insn));
12232 insn = NEXT_INSN (insn))
12233 if (INSN_P (insn) && reg_overlap_mentioned_p (reg, PATTERN (insn)))
12235 if (reg_referenced_p (reg, PATTERN (insn)))
12239 else if (CALL_P (insn)
12240 && find_reg_fusage (insn, USE, reg))
12245 else if (INSN_P (insn) && reg_set_p (reg, insn))
12248 /* If we found a place to put the link, place it there unless there
12249 is already a link to the same insn as LINK at that point. */
12255 for (link2 = LOG_LINKS (place); link2; link2 = XEXP (link2, 1))
12256 if (XEXP (link2, 0) == XEXP (link, 0))
12261 XEXP (link, 1) = LOG_LINKS (place);
12262 LOG_LINKS (place) = link;
12264 /* Set added_links_insn to the earliest insn we added a
12266 if (added_links_insn == 0
12267 || INSN_CUID (added_links_insn) > INSN_CUID (place))
12268 added_links_insn = place;
12274 /* Subroutine of unmentioned_reg_p and callback from for_each_rtx.
12275 Check whether the expression pointer to by LOC is a register or
12276 memory, and if so return 1 if it isn't mentioned in the rtx EXPR.
12277 Otherwise return zero. */
12280 unmentioned_reg_p_1 (rtx *loc, void *expr)
12285 && (REG_P (x) || MEM_P (x))
12286 && ! reg_mentioned_p (x, (rtx) expr))
12291 /* Check for any register or memory mentioned in EQUIV that is not
12292 mentioned in EXPR. This is used to restrict EQUIV to "specializations"
12293 of EXPR where some registers may have been replaced by constants. */
12296 unmentioned_reg_p (rtx equiv, rtx expr)
12298 return for_each_rtx (&equiv, unmentioned_reg_p_1, expr);
12301 /* Compute INSN_CUID for INSN, which is an insn made by combine. */
12304 insn_cuid (rtx insn)
12306 while (insn != 0 && INSN_UID (insn) > max_uid_cuid
12307 && NONJUMP_INSN_P (insn) && GET_CODE (PATTERN (insn)) == USE)
12308 insn = NEXT_INSN (insn);
12310 gcc_assert (INSN_UID (insn) <= max_uid_cuid);
12312 return INSN_CUID (insn);
12316 dump_combine_stats (FILE *file)
12320 ";; Combiner statistics: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n\n",
12321 combine_attempts, combine_merges, combine_extras, combine_successes);
12325 dump_combine_total_stats (FILE *file)
12329 "\n;; Combiner totals: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n",
12330 total_attempts, total_merges, total_extras, total_successes);
12335 gate_handle_combine (void)
12337 return (optimize > 0);
12340 /* Try combining insns through substitution. */
12342 rest_of_handle_combine (void)
12344 int rebuild_jump_labels_after_combine
12345 = combine_instructions (get_insns (), max_reg_num ());
12347 /* Combining insns may have turned an indirect jump into a
12348 direct jump. Rebuild the JUMP_LABEL fields of jumping
12350 if (rebuild_jump_labels_after_combine)
12352 timevar_push (TV_JUMP);
12353 rebuild_jump_labels (get_insns ());
12354 timevar_pop (TV_JUMP);
12356 delete_dead_jumptables ();
12357 cleanup_cfg (CLEANUP_EXPENSIVE | CLEANUP_UPDATE_LIFE);
12361 struct tree_opt_pass pass_combine =
12363 "combine", /* name */
12364 gate_handle_combine, /* gate */
12365 rest_of_handle_combine, /* execute */
12368 0, /* static_pass_number */
12369 TV_COMBINE, /* tv_id */
12370 0, /* properties_required */
12371 0, /* properties_provided */
12372 0, /* properties_destroyed */
12373 0, /* todo_flags_start */
12375 TODO_ggc_collect, /* todo_flags_finish */
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