1 /* Optimize by combining instructions for GNU compiler.
2 Copyright (C) 1987, 1988, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003, 2004, 2005 Free Software Foundation, Inc.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it under
8 the terms of the GNU General Public License as published by the Free
9 Software Foundation; either version 2, or (at your option) any later
12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING. If not, write to the Free
19 Software Foundation, 51 Franklin Street, Fifth Floor, Boston, MA
22 /* This module is essentially the "combiner" phase of the U. of Arizona
23 Portable Optimizer, but redone to work on our list-structured
24 representation for RTL instead of their string representation.
26 The LOG_LINKS of each insn identify the most recent assignment
27 to each REG used in the insn. It is a list of previous insns,
28 each of which contains a SET for a REG that is used in this insn
29 and not used or set in between. LOG_LINKs never cross basic blocks.
30 They were set up by the preceding pass (lifetime analysis).
32 We try to combine each pair of insns joined by a logical link.
33 We also try to combine triples of insns A, B and C when
34 C has a link back to B and B has a link back to A.
36 LOG_LINKS does not have links for use of the CC0. They don't
37 need to, because the insn that sets the CC0 is always immediately
38 before the insn that tests it. So we always regard a branch
39 insn as having a logical link to the preceding insn. The same is true
40 for an insn explicitly using CC0.
42 We check (with use_crosses_set_p) to avoid combining in such a way
43 as to move a computation to a place where its value would be different.
45 Combination is done by mathematically substituting the previous
46 insn(s) values for the regs they set into the expressions in
47 the later insns that refer to these regs. If the result is a valid insn
48 for our target machine, according to the machine description,
49 we install it, delete the earlier insns, and update the data flow
50 information (LOG_LINKS and REG_NOTES) for what we did.
52 There are a few exceptions where the dataflow information created by
53 flow.c aren't completely updated:
55 - reg_live_length is not updated
56 - a LOG_LINKS entry that refers to an insn with multiple SETs may be
57 removed because there is no way to know which register it was
60 To simplify substitution, we combine only when the earlier insn(s)
61 consist of only a single assignment. To simplify updating afterward,
62 we never combine when a subroutine call appears in the middle.
64 Since we do not represent assignments to CC0 explicitly except when that
65 is all an insn does, there is no LOG_LINKS entry in an insn that uses
66 the condition code for the insn that set the condition code.
67 Fortunately, these two insns must be consecutive.
68 Therefore, every JUMP_INSN is taken to have an implicit logical link
69 to the preceding insn. This is not quite right, since non-jumps can
70 also use the condition code; but in practice such insns would not
75 #include "coretypes.h"
82 #include "hard-reg-set.h"
83 #include "basic-block.h"
84 #include "insn-config.h"
86 /* Include expr.h after insn-config.h so we get HAVE_conditional_move. */
88 #include "insn-attr.h"
94 #include "insn-codes.h"
95 #include "rtlhooks-def.h"
96 /* Include output.h for dump_file. */
100 #include "tree-pass.h"
102 /* Number of attempts to combine instructions in this function. */
104 static int combine_attempts;
106 /* Number of attempts that got as far as substitution in this function. */
108 static int combine_merges;
110 /* Number of instructions combined with added SETs in this function. */
112 static int combine_extras;
114 /* Number of instructions combined in this function. */
116 static int combine_successes;
118 /* Totals over entire compilation. */
120 static int total_attempts, total_merges, total_extras, total_successes;
123 /* Vector mapping INSN_UIDs to cuids.
124 The cuids are like uids but increase monotonically always.
125 Combine always uses cuids so that it can compare them.
126 But actually renumbering the uids, which we used to do,
127 proves to be a bad idea because it makes it hard to compare
128 the dumps produced by earlier passes with those from later passes. */
130 static int *uid_cuid;
131 static int max_uid_cuid;
133 /* Get the cuid of an insn. */
135 #define INSN_CUID(INSN) \
136 (INSN_UID (INSN) > max_uid_cuid ? insn_cuid (INSN) : uid_cuid[INSN_UID (INSN)])
138 /* In case BITS_PER_WORD == HOST_BITS_PER_WIDE_INT, shifting by
139 BITS_PER_WORD would invoke undefined behavior. Work around it. */
141 #define UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD(val) \
142 (((unsigned HOST_WIDE_INT) (val) << (BITS_PER_WORD - 1)) << 1)
144 /* Maximum register number, which is the size of the tables below. */
146 static unsigned int combine_max_regno;
149 /* Record last point of death of (hard or pseudo) register n. */
152 /* Record last point of modification of (hard or pseudo) register n. */
155 /* The next group of fields allows the recording of the last value assigned
156 to (hard or pseudo) register n. We use this information to see if an
157 operation being processed is redundant given a prior operation performed
158 on the register. For example, an `and' with a constant is redundant if
159 all the zero bits are already known to be turned off.
161 We use an approach similar to that used by cse, but change it in the
164 (1) We do not want to reinitialize at each label.
165 (2) It is useful, but not critical, to know the actual value assigned
166 to a register. Often just its form is helpful.
168 Therefore, we maintain the following fields:
170 last_set_value the last value assigned
171 last_set_label records the value of label_tick when the
172 register was assigned
173 last_set_table_tick records the value of label_tick when a
174 value using the register is assigned
175 last_set_invalid set to nonzero when it is not valid
176 to use the value of this register in some
179 To understand the usage of these tables, it is important to understand
180 the distinction between the value in last_set_value being valid and
181 the register being validly contained in some other expression in the
184 (The next two parameters are out of date).
186 reg_stat[i].last_set_value is valid if it is nonzero, and either
187 reg_n_sets[i] is 1 or reg_stat[i].last_set_label == label_tick.
189 Register I may validly appear in any expression returned for the value
190 of another register if reg_n_sets[i] is 1. It may also appear in the
191 value for register J if reg_stat[j].last_set_invalid is zero, or
192 reg_stat[i].last_set_label < reg_stat[j].last_set_label.
194 If an expression is found in the table containing a register which may
195 not validly appear in an expression, the register is replaced by
196 something that won't match, (clobber (const_int 0)). */
198 /* Record last value assigned to (hard or pseudo) register n. */
202 /* Record the value of label_tick when an expression involving register n
203 is placed in last_set_value. */
205 int last_set_table_tick;
207 /* Record the value of label_tick when the value for register n is placed in
212 /* These fields are maintained in parallel with last_set_value and are
213 used to store the mode in which the register was last set, the bits
214 that were known to be zero when it was last set, and the number of
215 sign bits copies it was known to have when it was last set. */
217 unsigned HOST_WIDE_INT last_set_nonzero_bits;
218 char last_set_sign_bit_copies;
219 ENUM_BITFIELD(machine_mode) last_set_mode : 8;
221 /* Set nonzero if references to register n in expressions should not be
222 used. last_set_invalid is set nonzero when this register is being
223 assigned to and last_set_table_tick == label_tick. */
225 char last_set_invalid;
227 /* Some registers that are set more than once and used in more than one
228 basic block are nevertheless always set in similar ways. For example,
229 a QImode register may be loaded from memory in two places on a machine
230 where byte loads zero extend.
232 We record in the following fields if a register has some leading bits
233 that are always equal to the sign bit, and what we know about the
234 nonzero bits of a register, specifically which bits are known to be
237 If an entry is zero, it means that we don't know anything special. */
239 unsigned char sign_bit_copies;
241 unsigned HOST_WIDE_INT nonzero_bits;
244 static struct reg_stat *reg_stat;
246 /* Record the cuid of the last insn that invalidated memory
247 (anything that writes memory, and subroutine calls, but not pushes). */
249 static int mem_last_set;
251 /* Record the cuid of the last CALL_INSN
252 so we can tell whether a potential combination crosses any calls. */
254 static int last_call_cuid;
256 /* When `subst' is called, this is the insn that is being modified
257 (by combining in a previous insn). The PATTERN of this insn
258 is still the old pattern partially modified and it should not be
259 looked at, but this may be used to examine the successors of the insn
260 to judge whether a simplification is valid. */
262 static rtx subst_insn;
264 /* This is the lowest CUID that `subst' is currently dealing with.
265 get_last_value will not return a value if the register was set at or
266 after this CUID. If not for this mechanism, we could get confused if
267 I2 or I1 in try_combine were an insn that used the old value of a register
268 to obtain a new value. In that case, we might erroneously get the
269 new value of the register when we wanted the old one. */
271 static int subst_low_cuid;
273 /* This contains any hard registers that are used in newpat; reg_dead_at_p
274 must consider all these registers to be always live. */
276 static HARD_REG_SET newpat_used_regs;
278 /* This is an insn to which a LOG_LINKS entry has been added. If this
279 insn is the earlier than I2 or I3, combine should rescan starting at
282 static rtx added_links_insn;
284 /* Basic block in which we are performing combines. */
285 static basic_block this_basic_block;
287 /* A bitmap indicating which blocks had registers go dead at entry.
288 After combine, we'll need to re-do global life analysis with
289 those blocks as starting points. */
290 static sbitmap refresh_blocks;
292 /* The following array records the insn_rtx_cost for every insn
293 in the instruction stream. */
295 static int *uid_insn_cost;
297 /* Length of the currently allocated uid_insn_cost array. */
299 static int last_insn_cost;
301 /* Incremented for each label. */
303 static int label_tick;
305 /* Mode used to compute significance in reg_stat[].nonzero_bits. It is the
306 largest integer mode that can fit in HOST_BITS_PER_WIDE_INT. */
308 static enum machine_mode nonzero_bits_mode;
310 /* Nonzero when reg_stat[].nonzero_bits and reg_stat[].sign_bit_copies can
311 be safely used. It is zero while computing them and after combine has
312 completed. This former test prevents propagating values based on
313 previously set values, which can be incorrect if a variable is modified
316 static int nonzero_sign_valid;
319 /* Record one modification to rtl structure
320 to be undone by storing old_contents into *where.
321 is_int is 1 if the contents are an int. */
327 union {rtx r; int i;} old_contents;
328 union {rtx *r; int *i;} where;
331 /* Record a bunch of changes to be undone, up to MAX_UNDO of them.
332 num_undo says how many are currently recorded.
334 other_insn is nonzero if we have modified some other insn in the process
335 of working on subst_insn. It must be verified too. */
344 static struct undobuf undobuf;
346 /* Number of times the pseudo being substituted for
347 was found and replaced. */
349 static int n_occurrences;
351 static rtx reg_nonzero_bits_for_combine (rtx, enum machine_mode, rtx,
353 unsigned HOST_WIDE_INT,
354 unsigned HOST_WIDE_INT *);
355 static rtx reg_num_sign_bit_copies_for_combine (rtx, enum machine_mode, rtx,
357 unsigned int, unsigned int *);
358 static void do_SUBST (rtx *, rtx);
359 static void do_SUBST_INT (int *, int);
360 static void init_reg_last (void);
361 static void setup_incoming_promotions (void);
362 static void set_nonzero_bits_and_sign_copies (rtx, rtx, void *);
363 static int cant_combine_insn_p (rtx);
364 static int can_combine_p (rtx, rtx, rtx, rtx, rtx *, rtx *);
365 static int combinable_i3pat (rtx, rtx *, rtx, rtx, int, rtx *);
366 static int contains_muldiv (rtx);
367 static rtx try_combine (rtx, rtx, rtx, int *);
368 static void undo_all (void);
369 static void undo_commit (void);
370 static rtx *find_split_point (rtx *, rtx);
371 static rtx subst (rtx, rtx, rtx, int, int);
372 static rtx combine_simplify_rtx (rtx, enum machine_mode, int);
373 static rtx simplify_if_then_else (rtx);
374 static rtx simplify_set (rtx);
375 static rtx simplify_logical (rtx);
376 static rtx expand_compound_operation (rtx);
377 static rtx expand_field_assignment (rtx);
378 static rtx make_extraction (enum machine_mode, rtx, HOST_WIDE_INT,
379 rtx, unsigned HOST_WIDE_INT, int, int, int);
380 static rtx extract_left_shift (rtx, int);
381 static rtx make_compound_operation (rtx, enum rtx_code);
382 static int get_pos_from_mask (unsigned HOST_WIDE_INT,
383 unsigned HOST_WIDE_INT *);
384 static rtx force_to_mode (rtx, enum machine_mode,
385 unsigned HOST_WIDE_INT, rtx, int);
386 static rtx if_then_else_cond (rtx, rtx *, rtx *);
387 static rtx known_cond (rtx, enum rtx_code, rtx, rtx);
388 static int rtx_equal_for_field_assignment_p (rtx, rtx);
389 static rtx make_field_assignment (rtx);
390 static rtx apply_distributive_law (rtx);
391 static rtx distribute_and_simplify_rtx (rtx, int);
392 static rtx simplify_and_const_int (rtx, enum machine_mode, rtx,
393 unsigned HOST_WIDE_INT);
394 static int merge_outer_ops (enum rtx_code *, HOST_WIDE_INT *, enum rtx_code,
395 HOST_WIDE_INT, enum machine_mode, int *);
396 static rtx simplify_shift_const (rtx, enum rtx_code, enum machine_mode, rtx,
398 static int recog_for_combine (rtx *, rtx, rtx *);
399 static rtx gen_lowpart_for_combine (enum machine_mode, rtx);
400 static enum rtx_code simplify_comparison (enum rtx_code, rtx *, rtx *);
401 static void update_table_tick (rtx);
402 static void record_value_for_reg (rtx, rtx, rtx);
403 static void check_promoted_subreg (rtx, rtx);
404 static void record_dead_and_set_regs_1 (rtx, rtx, void *);
405 static void record_dead_and_set_regs (rtx);
406 static int get_last_value_validate (rtx *, rtx, int, int);
407 static rtx get_last_value (rtx);
408 static int use_crosses_set_p (rtx, int);
409 static void reg_dead_at_p_1 (rtx, rtx, void *);
410 static int reg_dead_at_p (rtx, rtx);
411 static void move_deaths (rtx, rtx, int, rtx, rtx *);
412 static int reg_bitfield_target_p (rtx, rtx);
413 static void distribute_notes (rtx, rtx, rtx, rtx);
414 static void distribute_links (rtx);
415 static void mark_used_regs_combine (rtx);
416 static int insn_cuid (rtx);
417 static void record_promoted_value (rtx, rtx);
418 static int unmentioned_reg_p_1 (rtx *, void *);
419 static bool unmentioned_reg_p (rtx, rtx);
422 /* It is not safe to use ordinary gen_lowpart in combine.
423 See comments in gen_lowpart_for_combine. */
424 #undef RTL_HOOKS_GEN_LOWPART
425 #define RTL_HOOKS_GEN_LOWPART gen_lowpart_for_combine
427 /* Our implementation of gen_lowpart never emits a new pseudo. */
428 #undef RTL_HOOKS_GEN_LOWPART_NO_EMIT
429 #define RTL_HOOKS_GEN_LOWPART_NO_EMIT gen_lowpart_for_combine
431 #undef RTL_HOOKS_REG_NONZERO_REG_BITS
432 #define RTL_HOOKS_REG_NONZERO_REG_BITS reg_nonzero_bits_for_combine
434 #undef RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES
435 #define RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES reg_num_sign_bit_copies_for_combine
437 static const struct rtl_hooks combine_rtl_hooks = RTL_HOOKS_INITIALIZER;
440 /* Substitute NEWVAL, an rtx expression, into INTO, a place in some
441 insn. The substitution can be undone by undo_all. If INTO is already
442 set to NEWVAL, do not record this change. Because computing NEWVAL might
443 also call SUBST, we have to compute it before we put anything into
447 do_SUBST (rtx *into, rtx newval)
452 if (oldval == newval)
455 /* We'd like to catch as many invalid transformations here as
456 possible. Unfortunately, there are way too many mode changes
457 that are perfectly valid, so we'd waste too much effort for
458 little gain doing the checks here. Focus on catching invalid
459 transformations involving integer constants. */
460 if (GET_MODE_CLASS (GET_MODE (oldval)) == MODE_INT
461 && GET_CODE (newval) == CONST_INT)
463 /* Sanity check that we're replacing oldval with a CONST_INT
464 that is a valid sign-extension for the original mode. */
465 gcc_assert (INTVAL (newval)
466 == trunc_int_for_mode (INTVAL (newval), GET_MODE (oldval)));
468 /* Replacing the operand of a SUBREG or a ZERO_EXTEND with a
469 CONST_INT is not valid, because after the replacement, the
470 original mode would be gone. Unfortunately, we can't tell
471 when do_SUBST is called to replace the operand thereof, so we
472 perform this test on oldval instead, checking whether an
473 invalid replacement took place before we got here. */
474 gcc_assert (!(GET_CODE (oldval) == SUBREG
475 && GET_CODE (SUBREG_REG (oldval)) == CONST_INT));
476 gcc_assert (!(GET_CODE (oldval) == ZERO_EXTEND
477 && GET_CODE (XEXP (oldval, 0)) == CONST_INT));
481 buf = undobuf.frees, undobuf.frees = buf->next;
483 buf = xmalloc (sizeof (struct undo));
487 buf->old_contents.r = oldval;
490 buf->next = undobuf.undos, undobuf.undos = buf;
493 #define SUBST(INTO, NEWVAL) do_SUBST(&(INTO), (NEWVAL))
495 /* Similar to SUBST, but NEWVAL is an int expression. Note that substitution
496 for the value of a HOST_WIDE_INT value (including CONST_INT) is
500 do_SUBST_INT (int *into, int newval)
505 if (oldval == newval)
509 buf = undobuf.frees, undobuf.frees = buf->next;
511 buf = xmalloc (sizeof (struct undo));
515 buf->old_contents.i = oldval;
518 buf->next = undobuf.undos, undobuf.undos = buf;
521 #define SUBST_INT(INTO, NEWVAL) do_SUBST_INT(&(INTO), (NEWVAL))
523 /* Subroutine of try_combine. Determine whether the combine replacement
524 patterns NEWPAT and NEWI2PAT are cheaper according to insn_rtx_cost
525 that the original instruction sequence I1, I2 and I3. Note that I1
526 and/or NEWI2PAT may be NULL_RTX. This function returns false, if the
527 costs of all instructions can be estimated, and the replacements are
528 more expensive than the original sequence. */
531 combine_validate_cost (rtx i1, rtx i2, rtx i3, rtx newpat, rtx newi2pat)
533 int i1_cost, i2_cost, i3_cost;
534 int new_i2_cost, new_i3_cost;
535 int old_cost, new_cost;
537 /* Lookup the original insn_rtx_costs. */
538 i2_cost = INSN_UID (i2) <= last_insn_cost
539 ? uid_insn_cost[INSN_UID (i2)] : 0;
540 i3_cost = INSN_UID (i3) <= last_insn_cost
541 ? uid_insn_cost[INSN_UID (i3)] : 0;
545 i1_cost = INSN_UID (i1) <= last_insn_cost
546 ? uid_insn_cost[INSN_UID (i1)] : 0;
547 old_cost = (i1_cost > 0 && i2_cost > 0 && i3_cost > 0)
548 ? i1_cost + i2_cost + i3_cost : 0;
552 old_cost = (i2_cost > 0 && i3_cost > 0) ? i2_cost + i3_cost : 0;
556 /* Calculate the replacement insn_rtx_costs. */
557 new_i3_cost = insn_rtx_cost (newpat);
560 new_i2_cost = insn_rtx_cost (newi2pat);
561 new_cost = (new_i2_cost > 0 && new_i3_cost > 0)
562 ? new_i2_cost + new_i3_cost : 0;
566 new_cost = new_i3_cost;
570 if (undobuf.other_insn)
572 int old_other_cost, new_other_cost;
574 old_other_cost = (INSN_UID (undobuf.other_insn) <= last_insn_cost
575 ? uid_insn_cost[INSN_UID (undobuf.other_insn)] : 0);
576 new_other_cost = insn_rtx_cost (PATTERN (undobuf.other_insn));
577 if (old_other_cost > 0 && new_other_cost > 0)
579 old_cost += old_other_cost;
580 new_cost += new_other_cost;
586 /* Disallow this recombination if both new_cost and old_cost are
587 greater than zero, and new_cost is greater than old cost. */
589 && new_cost > old_cost)
596 "rejecting combination of insns %d, %d and %d\n",
597 INSN_UID (i1), INSN_UID (i2), INSN_UID (i3));
598 fprintf (dump_file, "original costs %d + %d + %d = %d\n",
599 i1_cost, i2_cost, i3_cost, old_cost);
604 "rejecting combination of insns %d and %d\n",
605 INSN_UID (i2), INSN_UID (i3));
606 fprintf (dump_file, "original costs %d + %d = %d\n",
607 i2_cost, i3_cost, old_cost);
612 fprintf (dump_file, "replacement costs %d + %d = %d\n",
613 new_i2_cost, new_i3_cost, new_cost);
616 fprintf (dump_file, "replacement cost %d\n", new_cost);
622 /* Update the uid_insn_cost array with the replacement costs. */
623 uid_insn_cost[INSN_UID (i2)] = new_i2_cost;
624 uid_insn_cost[INSN_UID (i3)] = new_i3_cost;
626 uid_insn_cost[INSN_UID (i1)] = 0;
631 /* Main entry point for combiner. F is the first insn of the function.
632 NREGS is the first unused pseudo-reg number.
634 Return nonzero if the combiner has turned an indirect jump
635 instruction into a direct jump. */
637 combine_instructions (rtx f, unsigned int nregs)
645 rtx links, nextlinks;
646 sbitmap_iterator sbi;
648 int new_direct_jump_p = 0;
650 combine_attempts = 0;
653 combine_successes = 0;
655 combine_max_regno = nregs;
657 rtl_hooks = combine_rtl_hooks;
659 reg_stat = xcalloc (nregs, sizeof (struct reg_stat));
661 init_recog_no_volatile ();
663 /* Compute maximum uid value so uid_cuid can be allocated. */
665 for (insn = f, i = 0; insn; insn = NEXT_INSN (insn))
666 if (INSN_UID (insn) > i)
669 uid_cuid = xmalloc ((i + 1) * sizeof (int));
672 nonzero_bits_mode = mode_for_size (HOST_BITS_PER_WIDE_INT, MODE_INT, 0);
674 /* Don't use reg_stat[].nonzero_bits when computing it. This can cause
675 problems when, for example, we have j <<= 1 in a loop. */
677 nonzero_sign_valid = 0;
679 /* Compute the mapping from uids to cuids.
680 Cuids are numbers assigned to insns, like uids,
681 except that cuids increase monotonically through the code.
683 Scan all SETs and see if we can deduce anything about what
684 bits are known to be zero for some registers and how many copies
685 of the sign bit are known to exist for those registers.
687 Also set any known values so that we can use it while searching
688 for what bits are known to be set. */
692 setup_incoming_promotions ();
694 refresh_blocks = sbitmap_alloc (last_basic_block);
695 sbitmap_zero (refresh_blocks);
697 /* Allocate array of current insn_rtx_costs. */
698 uid_insn_cost = xcalloc (max_uid_cuid + 1, sizeof (int));
699 last_insn_cost = max_uid_cuid;
701 for (insn = f, i = 0; insn; insn = NEXT_INSN (insn))
703 uid_cuid[INSN_UID (insn)] = ++i;
709 note_stores (PATTERN (insn), set_nonzero_bits_and_sign_copies,
711 record_dead_and_set_regs (insn);
714 for (links = REG_NOTES (insn); links; links = XEXP (links, 1))
715 if (REG_NOTE_KIND (links) == REG_INC)
716 set_nonzero_bits_and_sign_copies (XEXP (links, 0), NULL_RTX,
720 /* Record the current insn_rtx_cost of this instruction. */
721 if (NONJUMP_INSN_P (insn))
722 uid_insn_cost[INSN_UID (insn)] = insn_rtx_cost (PATTERN (insn));
724 fprintf(dump_file, "insn_cost %d: %d\n",
725 INSN_UID (insn), uid_insn_cost[INSN_UID (insn)]);
732 nonzero_sign_valid = 1;
734 /* Now scan all the insns in forward order. */
740 setup_incoming_promotions ();
742 FOR_EACH_BB (this_basic_block)
744 for (insn = BB_HEAD (this_basic_block);
745 insn != NEXT_INSN (BB_END (this_basic_block));
746 insn = next ? next : NEXT_INSN (insn))
753 else if (INSN_P (insn))
755 /* See if we know about function return values before this
756 insn based upon SUBREG flags. */
757 check_promoted_subreg (insn, PATTERN (insn));
759 /* Try this insn with each insn it links back to. */
761 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
762 if ((next = try_combine (insn, XEXP (links, 0),
763 NULL_RTX, &new_direct_jump_p)) != 0)
766 /* Try each sequence of three linked insns ending with this one. */
768 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
770 rtx link = XEXP (links, 0);
772 /* If the linked insn has been replaced by a note, then there
773 is no point in pursuing this chain any further. */
777 for (nextlinks = LOG_LINKS (link);
779 nextlinks = XEXP (nextlinks, 1))
780 if ((next = try_combine (insn, link,
782 &new_direct_jump_p)) != 0)
787 /* Try to combine a jump insn that uses CC0
788 with a preceding insn that sets CC0, and maybe with its
789 logical predecessor as well.
790 This is how we make decrement-and-branch insns.
791 We need this special code because data flow connections
792 via CC0 do not get entered in LOG_LINKS. */
795 && (prev = prev_nonnote_insn (insn)) != 0
796 && NONJUMP_INSN_P (prev)
797 && sets_cc0_p (PATTERN (prev)))
799 if ((next = try_combine (insn, prev,
800 NULL_RTX, &new_direct_jump_p)) != 0)
803 for (nextlinks = LOG_LINKS (prev); nextlinks;
804 nextlinks = XEXP (nextlinks, 1))
805 if ((next = try_combine (insn, prev,
807 &new_direct_jump_p)) != 0)
811 /* Do the same for an insn that explicitly references CC0. */
812 if (NONJUMP_INSN_P (insn)
813 && (prev = prev_nonnote_insn (insn)) != 0
814 && NONJUMP_INSN_P (prev)
815 && sets_cc0_p (PATTERN (prev))
816 && GET_CODE (PATTERN (insn)) == SET
817 && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (insn))))
819 if ((next = try_combine (insn, prev,
820 NULL_RTX, &new_direct_jump_p)) != 0)
823 for (nextlinks = LOG_LINKS (prev); nextlinks;
824 nextlinks = XEXP (nextlinks, 1))
825 if ((next = try_combine (insn, prev,
827 &new_direct_jump_p)) != 0)
831 /* Finally, see if any of the insns that this insn links to
832 explicitly references CC0. If so, try this insn, that insn,
833 and its predecessor if it sets CC0. */
834 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
835 if (NONJUMP_INSN_P (XEXP (links, 0))
836 && GET_CODE (PATTERN (XEXP (links, 0))) == SET
837 && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (XEXP (links, 0))))
838 && (prev = prev_nonnote_insn (XEXP (links, 0))) != 0
839 && NONJUMP_INSN_P (prev)
840 && sets_cc0_p (PATTERN (prev))
841 && (next = try_combine (insn, XEXP (links, 0),
842 prev, &new_direct_jump_p)) != 0)
846 /* Try combining an insn with two different insns whose results it
848 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
849 for (nextlinks = XEXP (links, 1); nextlinks;
850 nextlinks = XEXP (nextlinks, 1))
851 if ((next = try_combine (insn, XEXP (links, 0),
853 &new_direct_jump_p)) != 0)
856 /* Try this insn with each REG_EQUAL note it links back to. */
857 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
860 rtx temp = XEXP (links, 0);
861 if ((set = single_set (temp)) != 0
862 && (note = find_reg_equal_equiv_note (temp)) != 0
863 && GET_CODE (XEXP (note, 0)) != EXPR_LIST
864 /* Avoid using a register that may already been marked
865 dead by an earlier instruction. */
866 && ! unmentioned_reg_p (XEXP (note, 0), SET_SRC (set)))
868 /* Temporarily replace the set's source with the
869 contents of the REG_EQUAL note. The insn will
870 be deleted or recognized by try_combine. */
871 rtx orig = SET_SRC (set);
872 SET_SRC (set) = XEXP (note, 0);
873 next = try_combine (insn, temp, NULL_RTX,
877 SET_SRC (set) = orig;
882 record_dead_and_set_regs (insn);
891 EXECUTE_IF_SET_IN_SBITMAP (refresh_blocks, 0, j, sbi)
892 BASIC_BLOCK (j)->flags |= BB_DIRTY;
893 new_direct_jump_p |= purge_all_dead_edges ();
894 delete_noop_moves ();
896 update_life_info_in_dirty_blocks (UPDATE_LIFE_GLOBAL_RM_NOTES,
897 PROP_DEATH_NOTES | PROP_SCAN_DEAD_CODE
898 | PROP_KILL_DEAD_CODE);
901 sbitmap_free (refresh_blocks);
902 free (uid_insn_cost);
907 struct undo *undo, *next;
908 for (undo = undobuf.frees; undo; undo = next)
916 total_attempts += combine_attempts;
917 total_merges += combine_merges;
918 total_extras += combine_extras;
919 total_successes += combine_successes;
921 nonzero_sign_valid = 0;
922 rtl_hooks = general_rtl_hooks;
924 /* Make recognizer allow volatile MEMs again. */
927 return new_direct_jump_p;
930 /* Wipe the last_xxx fields of reg_stat in preparation for another pass. */
936 for (i = 0; i < combine_max_regno; i++)
937 memset (reg_stat + i, 0, offsetof (struct reg_stat, sign_bit_copies));
940 /* Set up any promoted values for incoming argument registers. */
943 setup_incoming_promotions (void)
947 enum machine_mode mode;
949 rtx first = get_insns ();
951 if (targetm.calls.promote_function_args (TREE_TYPE (cfun->decl)))
953 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
954 /* Check whether this register can hold an incoming pointer
955 argument. FUNCTION_ARG_REGNO_P tests outgoing register
956 numbers, so translate if necessary due to register windows. */
957 if (FUNCTION_ARG_REGNO_P (OUTGOING_REGNO (regno))
958 && (reg = promoted_input_arg (regno, &mode, &unsignedp)) != 0)
961 (reg, first, gen_rtx_fmt_e ((unsignedp ? ZERO_EXTEND
964 gen_rtx_CLOBBER (mode, const0_rtx)));
969 /* Called via note_stores. If X is a pseudo that is narrower than
970 HOST_BITS_PER_WIDE_INT and is being set, record what bits are known zero.
972 If we are setting only a portion of X and we can't figure out what
973 portion, assume all bits will be used since we don't know what will
976 Similarly, set how many bits of X are known to be copies of the sign bit
977 at all locations in the function. This is the smallest number implied
981 set_nonzero_bits_and_sign_copies (rtx x, rtx set,
982 void *data ATTRIBUTE_UNUSED)
987 && REGNO (x) >= FIRST_PSEUDO_REGISTER
988 /* If this register is undefined at the start of the file, we can't
989 say what its contents were. */
991 (ENTRY_BLOCK_PTR->next_bb->il.rtl->global_live_at_start, REGNO (x))
992 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT)
994 if (set == 0 || GET_CODE (set) == CLOBBER)
996 reg_stat[REGNO (x)].nonzero_bits = GET_MODE_MASK (GET_MODE (x));
997 reg_stat[REGNO (x)].sign_bit_copies = 1;
1001 /* If this is a complex assignment, see if we can convert it into a
1002 simple assignment. */
1003 set = expand_field_assignment (set);
1005 /* If this is a simple assignment, or we have a paradoxical SUBREG,
1006 set what we know about X. */
1008 if (SET_DEST (set) == x
1009 || (GET_CODE (SET_DEST (set)) == SUBREG
1010 && (GET_MODE_SIZE (GET_MODE (SET_DEST (set)))
1011 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (set)))))
1012 && SUBREG_REG (SET_DEST (set)) == x))
1014 rtx src = SET_SRC (set);
1016 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
1017 /* If X is narrower than a word and SRC is a non-negative
1018 constant that would appear negative in the mode of X,
1019 sign-extend it for use in reg_stat[].nonzero_bits because some
1020 machines (maybe most) will actually do the sign-extension
1021 and this is the conservative approach.
1023 ??? For 2.5, try to tighten up the MD files in this regard
1024 instead of this kludge. */
1026 if (GET_MODE_BITSIZE (GET_MODE (x)) < BITS_PER_WORD
1027 && GET_CODE (src) == CONST_INT
1029 && 0 != (INTVAL (src)
1030 & ((HOST_WIDE_INT) 1
1031 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
1032 src = GEN_INT (INTVAL (src)
1033 | ((HOST_WIDE_INT) (-1)
1034 << GET_MODE_BITSIZE (GET_MODE (x))));
1037 /* Don't call nonzero_bits if it cannot change anything. */
1038 if (reg_stat[REGNO (x)].nonzero_bits != ~(unsigned HOST_WIDE_INT) 0)
1039 reg_stat[REGNO (x)].nonzero_bits
1040 |= nonzero_bits (src, nonzero_bits_mode);
1041 num = num_sign_bit_copies (SET_SRC (set), GET_MODE (x));
1042 if (reg_stat[REGNO (x)].sign_bit_copies == 0
1043 || reg_stat[REGNO (x)].sign_bit_copies > num)
1044 reg_stat[REGNO (x)].sign_bit_copies = num;
1048 reg_stat[REGNO (x)].nonzero_bits = GET_MODE_MASK (GET_MODE (x));
1049 reg_stat[REGNO (x)].sign_bit_copies = 1;
1054 /* See if INSN can be combined into I3. PRED and SUCC are optionally
1055 insns that were previously combined into I3 or that will be combined
1056 into the merger of INSN and I3.
1058 Return 0 if the combination is not allowed for any reason.
1060 If the combination is allowed, *PDEST will be set to the single
1061 destination of INSN and *PSRC to the single source, and this function
1065 can_combine_p (rtx insn, rtx i3, rtx pred ATTRIBUTE_UNUSED, rtx succ,
1066 rtx *pdest, rtx *psrc)
1069 rtx set = 0, src, dest;
1074 int all_adjacent = (succ ? (next_active_insn (insn) == succ
1075 && next_active_insn (succ) == i3)
1076 : next_active_insn (insn) == i3);
1078 /* Can combine only if previous insn is a SET of a REG, a SUBREG or CC0.
1079 or a PARALLEL consisting of such a SET and CLOBBERs.
1081 If INSN has CLOBBER parallel parts, ignore them for our processing.
1082 By definition, these happen during the execution of the insn. When it
1083 is merged with another insn, all bets are off. If they are, in fact,
1084 needed and aren't also supplied in I3, they may be added by
1085 recog_for_combine. Otherwise, it won't match.
1087 We can also ignore a SET whose SET_DEST is mentioned in a REG_UNUSED
1090 Get the source and destination of INSN. If more than one, can't
1093 if (GET_CODE (PATTERN (insn)) == SET)
1094 set = PATTERN (insn);
1095 else if (GET_CODE (PATTERN (insn)) == PARALLEL
1096 && GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == SET)
1098 for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
1100 rtx elt = XVECEXP (PATTERN (insn), 0, i);
1103 switch (GET_CODE (elt))
1105 /* This is important to combine floating point insns
1106 for the SH4 port. */
1108 /* Combining an isolated USE doesn't make sense.
1109 We depend here on combinable_i3pat to reject them. */
1110 /* The code below this loop only verifies that the inputs of
1111 the SET in INSN do not change. We call reg_set_between_p
1112 to verify that the REG in the USE does not change between
1114 If the USE in INSN was for a pseudo register, the matching
1115 insn pattern will likely match any register; combining this
1116 with any other USE would only be safe if we knew that the
1117 used registers have identical values, or if there was
1118 something to tell them apart, e.g. different modes. For
1119 now, we forgo such complicated tests and simply disallow
1120 combining of USES of pseudo registers with any other USE. */
1121 if (REG_P (XEXP (elt, 0))
1122 && GET_CODE (PATTERN (i3)) == PARALLEL)
1124 rtx i3pat = PATTERN (i3);
1125 int i = XVECLEN (i3pat, 0) - 1;
1126 unsigned int regno = REGNO (XEXP (elt, 0));
1130 rtx i3elt = XVECEXP (i3pat, 0, i);
1132 if (GET_CODE (i3elt) == USE
1133 && REG_P (XEXP (i3elt, 0))
1134 && (REGNO (XEXP (i3elt, 0)) == regno
1135 ? reg_set_between_p (XEXP (elt, 0),
1136 PREV_INSN (insn), i3)
1137 : regno >= FIRST_PSEUDO_REGISTER))
1144 /* We can ignore CLOBBERs. */
1149 /* Ignore SETs whose result isn't used but not those that
1150 have side-effects. */
1151 if (find_reg_note (insn, REG_UNUSED, SET_DEST (elt))
1152 && (!(note = find_reg_note (insn, REG_EH_REGION, NULL_RTX))
1153 || INTVAL (XEXP (note, 0)) <= 0)
1154 && ! side_effects_p (elt))
1157 /* If we have already found a SET, this is a second one and
1158 so we cannot combine with this insn. */
1166 /* Anything else means we can't combine. */
1172 /* If SET_SRC is an ASM_OPERANDS we can't throw away these CLOBBERs,
1173 so don't do anything with it. */
1174 || GET_CODE (SET_SRC (set)) == ASM_OPERANDS)
1183 set = expand_field_assignment (set);
1184 src = SET_SRC (set), dest = SET_DEST (set);
1186 /* Don't eliminate a store in the stack pointer. */
1187 if (dest == stack_pointer_rtx
1188 /* Don't combine with an insn that sets a register to itself if it has
1189 a REG_EQUAL note. This may be part of a REG_NO_CONFLICT sequence. */
1190 || (rtx_equal_p (src, dest) && find_reg_note (insn, REG_EQUAL, NULL_RTX))
1191 /* Can't merge an ASM_OPERANDS. */
1192 || GET_CODE (src) == ASM_OPERANDS
1193 /* Can't merge a function call. */
1194 || GET_CODE (src) == CALL
1195 /* Don't eliminate a function call argument. */
1197 && (find_reg_fusage (i3, USE, dest)
1199 && REGNO (dest) < FIRST_PSEUDO_REGISTER
1200 && global_regs[REGNO (dest)])))
1201 /* Don't substitute into an incremented register. */
1202 || FIND_REG_INC_NOTE (i3, dest)
1203 || (succ && FIND_REG_INC_NOTE (succ, dest))
1204 /* Don't substitute into a non-local goto, this confuses CFG. */
1205 || (JUMP_P (i3) && find_reg_note (i3, REG_NON_LOCAL_GOTO, NULL_RTX))
1207 /* Don't combine the end of a libcall into anything. */
1208 /* ??? This gives worse code, and appears to be unnecessary, since no
1209 pass after flow uses REG_LIBCALL/REG_RETVAL notes. Local-alloc does
1210 use REG_RETVAL notes for noconflict blocks, but other code here
1211 makes sure that those insns don't disappear. */
1212 || find_reg_note (insn, REG_RETVAL, NULL_RTX)
1214 /* Make sure that DEST is not used after SUCC but before I3. */
1215 || (succ && ! all_adjacent
1216 && reg_used_between_p (dest, succ, i3))
1217 /* Make sure that the value that is to be substituted for the register
1218 does not use any registers whose values alter in between. However,
1219 If the insns are adjacent, a use can't cross a set even though we
1220 think it might (this can happen for a sequence of insns each setting
1221 the same destination; last_set of that register might point to
1222 a NOTE). If INSN has a REG_EQUIV note, the register is always
1223 equivalent to the memory so the substitution is valid even if there
1224 are intervening stores. Also, don't move a volatile asm or
1225 UNSPEC_VOLATILE across any other insns. */
1228 || ! find_reg_note (insn, REG_EQUIV, src))
1229 && use_crosses_set_p (src, INSN_CUID (insn)))
1230 || (GET_CODE (src) == ASM_OPERANDS && MEM_VOLATILE_P (src))
1231 || GET_CODE (src) == UNSPEC_VOLATILE))
1232 /* If there is a REG_NO_CONFLICT note for DEST in I3 or SUCC, we get
1233 better register allocation by not doing the combine. */
1234 || find_reg_note (i3, REG_NO_CONFLICT, dest)
1235 || (succ && find_reg_note (succ, REG_NO_CONFLICT, dest))
1236 /* Don't combine across a CALL_INSN, because that would possibly
1237 change whether the life span of some REGs crosses calls or not,
1238 and it is a pain to update that information.
1239 Exception: if source is a constant, moving it later can't hurt.
1240 Accept that special case, because it helps -fforce-addr a lot. */
1241 || (INSN_CUID (insn) < last_call_cuid && ! CONSTANT_P (src)))
1244 /* DEST must either be a REG or CC0. */
1247 /* If register alignment is being enforced for multi-word items in all
1248 cases except for parameters, it is possible to have a register copy
1249 insn referencing a hard register that is not allowed to contain the
1250 mode being copied and which would not be valid as an operand of most
1251 insns. Eliminate this problem by not combining with such an insn.
1253 Also, on some machines we don't want to extend the life of a hard
1257 && ((REGNO (dest) < FIRST_PSEUDO_REGISTER
1258 && ! HARD_REGNO_MODE_OK (REGNO (dest), GET_MODE (dest)))
1259 /* Don't extend the life of a hard register unless it is
1260 user variable (if we have few registers) or it can't
1261 fit into the desired register (meaning something special
1263 Also avoid substituting a return register into I3, because
1264 reload can't handle a conflict with constraints of other
1266 || (REGNO (src) < FIRST_PSEUDO_REGISTER
1267 && ! HARD_REGNO_MODE_OK (REGNO (src), GET_MODE (src)))))
1270 else if (GET_CODE (dest) != CC0)
1274 if (GET_CODE (PATTERN (i3)) == PARALLEL)
1275 for (i = XVECLEN (PATTERN (i3), 0) - 1; i >= 0; i--)
1276 if (GET_CODE (XVECEXP (PATTERN (i3), 0, i)) == CLOBBER)
1278 /* Don't substitute for a register intended as a clobberable
1280 rtx reg = XEXP (XVECEXP (PATTERN (i3), 0, i), 0);
1281 if (rtx_equal_p (reg, dest))
1284 /* If the clobber represents an earlyclobber operand, we must not
1285 substitute an expression containing the clobbered register.
1286 As we do not analyze the constraint strings here, we have to
1287 make the conservative assumption. However, if the register is
1288 a fixed hard reg, the clobber cannot represent any operand;
1289 we leave it up to the machine description to either accept or
1290 reject use-and-clobber patterns. */
1292 || REGNO (reg) >= FIRST_PSEUDO_REGISTER
1293 || !fixed_regs[REGNO (reg)])
1294 if (reg_overlap_mentioned_p (reg, src))
1298 /* If INSN contains anything volatile, or is an `asm' (whether volatile
1299 or not), reject, unless nothing volatile comes between it and I3 */
1301 if (GET_CODE (src) == ASM_OPERANDS || volatile_refs_p (src))
1303 /* Make sure succ doesn't contain a volatile reference. */
1304 if (succ != 0 && volatile_refs_p (PATTERN (succ)))
1307 for (p = NEXT_INSN (insn); p != i3; p = NEXT_INSN (p))
1308 if (INSN_P (p) && p != succ && volatile_refs_p (PATTERN (p)))
1312 /* If INSN is an asm, and DEST is a hard register, reject, since it has
1313 to be an explicit register variable, and was chosen for a reason. */
1315 if (GET_CODE (src) == ASM_OPERANDS
1316 && REG_P (dest) && REGNO (dest) < FIRST_PSEUDO_REGISTER)
1319 /* If there are any volatile insns between INSN and I3, reject, because
1320 they might affect machine state. */
1322 for (p = NEXT_INSN (insn); p != i3; p = NEXT_INSN (p))
1323 if (INSN_P (p) && p != succ && volatile_insn_p (PATTERN (p)))
1326 /* If INSN contains an autoincrement or autodecrement, make sure that
1327 register is not used between there and I3, and not already used in
1328 I3 either. Neither must it be used in PRED or SUCC, if they exist.
1329 Also insist that I3 not be a jump; if it were one
1330 and the incremented register were spilled, we would lose. */
1333 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
1334 if (REG_NOTE_KIND (link) == REG_INC
1336 || reg_used_between_p (XEXP (link, 0), insn, i3)
1337 || (pred != NULL_RTX
1338 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (pred)))
1339 || (succ != NULL_RTX
1340 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (succ)))
1341 || reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i3))))
1346 /* Don't combine an insn that follows a CC0-setting insn.
1347 An insn that uses CC0 must not be separated from the one that sets it.
1348 We do, however, allow I2 to follow a CC0-setting insn if that insn
1349 is passed as I1; in that case it will be deleted also.
1350 We also allow combining in this case if all the insns are adjacent
1351 because that would leave the two CC0 insns adjacent as well.
1352 It would be more logical to test whether CC0 occurs inside I1 or I2,
1353 but that would be much slower, and this ought to be equivalent. */
1355 p = prev_nonnote_insn (insn);
1356 if (p && p != pred && NONJUMP_INSN_P (p) && sets_cc0_p (PATTERN (p))
1361 /* If we get here, we have passed all the tests and the combination is
1370 /* LOC is the location within I3 that contains its pattern or the component
1371 of a PARALLEL of the pattern. We validate that it is valid for combining.
1373 One problem is if I3 modifies its output, as opposed to replacing it
1374 entirely, we can't allow the output to contain I2DEST or I1DEST as doing
1375 so would produce an insn that is not equivalent to the original insns.
1379 (set (reg:DI 101) (reg:DI 100))
1380 (set (subreg:SI (reg:DI 101) 0) <foo>)
1382 This is NOT equivalent to:
1384 (parallel [(set (subreg:SI (reg:DI 100) 0) <foo>)
1385 (set (reg:DI 101) (reg:DI 100))])
1387 Not only does this modify 100 (in which case it might still be valid
1388 if 100 were dead in I2), it sets 101 to the ORIGINAL value of 100.
1390 We can also run into a problem if I2 sets a register that I1
1391 uses and I1 gets directly substituted into I3 (not via I2). In that
1392 case, we would be getting the wrong value of I2DEST into I3, so we
1393 must reject the combination. This case occurs when I2 and I1 both
1394 feed into I3, rather than when I1 feeds into I2, which feeds into I3.
1395 If I1_NOT_IN_SRC is nonzero, it means that finding I1 in the source
1396 of a SET must prevent combination from occurring.
1398 Before doing the above check, we first try to expand a field assignment
1399 into a set of logical operations.
1401 If PI3_DEST_KILLED is nonzero, it is a pointer to a location in which
1402 we place a register that is both set and used within I3. If more than one
1403 such register is detected, we fail.
1405 Return 1 if the combination is valid, zero otherwise. */
1408 combinable_i3pat (rtx i3, rtx *loc, rtx i2dest, rtx i1dest,
1409 int i1_not_in_src, rtx *pi3dest_killed)
1413 if (GET_CODE (x) == SET)
1416 rtx dest = SET_DEST (set);
1417 rtx src = SET_SRC (set);
1418 rtx inner_dest = dest;
1420 while (GET_CODE (inner_dest) == STRICT_LOW_PART
1421 || GET_CODE (inner_dest) == SUBREG
1422 || GET_CODE (inner_dest) == ZERO_EXTRACT)
1423 inner_dest = XEXP (inner_dest, 0);
1425 /* Check for the case where I3 modifies its output, as discussed
1426 above. We don't want to prevent pseudos from being combined
1427 into the address of a MEM, so only prevent the combination if
1428 i1 or i2 set the same MEM. */
1429 if ((inner_dest != dest &&
1430 (!MEM_P (inner_dest)
1431 || rtx_equal_p (i2dest, inner_dest)
1432 || (i1dest && rtx_equal_p (i1dest, inner_dest)))
1433 && (reg_overlap_mentioned_p (i2dest, inner_dest)
1434 || (i1dest && reg_overlap_mentioned_p (i1dest, inner_dest))))
1436 /* This is the same test done in can_combine_p except we can't test
1437 all_adjacent; we don't have to, since this instruction will stay
1438 in place, thus we are not considering increasing the lifetime of
1441 Also, if this insn sets a function argument, combining it with
1442 something that might need a spill could clobber a previous
1443 function argument; the all_adjacent test in can_combine_p also
1444 checks this; here, we do a more specific test for this case. */
1446 || (REG_P (inner_dest)
1447 && REGNO (inner_dest) < FIRST_PSEUDO_REGISTER
1448 && (! HARD_REGNO_MODE_OK (REGNO (inner_dest),
1449 GET_MODE (inner_dest))))
1450 || (i1_not_in_src && reg_overlap_mentioned_p (i1dest, src)))
1453 /* If DEST is used in I3, it is being killed in this insn,
1454 so record that for later.
1455 Never add REG_DEAD notes for the FRAME_POINTER_REGNUM or the
1456 STACK_POINTER_REGNUM, since these are always considered to be
1457 live. Similarly for ARG_POINTER_REGNUM if it is fixed. */
1458 if (pi3dest_killed && REG_P (dest)
1459 && reg_referenced_p (dest, PATTERN (i3))
1460 && REGNO (dest) != FRAME_POINTER_REGNUM
1461 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
1462 && REGNO (dest) != HARD_FRAME_POINTER_REGNUM
1464 #if ARG_POINTER_REGNUM != FRAME_POINTER_REGNUM
1465 && (REGNO (dest) != ARG_POINTER_REGNUM
1466 || ! fixed_regs [REGNO (dest)])
1468 && REGNO (dest) != STACK_POINTER_REGNUM)
1470 if (*pi3dest_killed)
1473 *pi3dest_killed = dest;
1477 else if (GET_CODE (x) == PARALLEL)
1481 for (i = 0; i < XVECLEN (x, 0); i++)
1482 if (! combinable_i3pat (i3, &XVECEXP (x, 0, i), i2dest, i1dest,
1483 i1_not_in_src, pi3dest_killed))
1490 /* Return 1 if X is an arithmetic expression that contains a multiplication
1491 and division. We don't count multiplications by powers of two here. */
1494 contains_muldiv (rtx x)
1496 switch (GET_CODE (x))
1498 case MOD: case DIV: case UMOD: case UDIV:
1502 return ! (GET_CODE (XEXP (x, 1)) == CONST_INT
1503 && exact_log2 (INTVAL (XEXP (x, 1))) >= 0);
1506 return contains_muldiv (XEXP (x, 0))
1507 || contains_muldiv (XEXP (x, 1));
1510 return contains_muldiv (XEXP (x, 0));
1516 /* Determine whether INSN can be used in a combination. Return nonzero if
1517 not. This is used in try_combine to detect early some cases where we
1518 can't perform combinations. */
1521 cant_combine_insn_p (rtx insn)
1526 /* If this isn't really an insn, we can't do anything.
1527 This can occur when flow deletes an insn that it has merged into an
1528 auto-increment address. */
1529 if (! INSN_P (insn))
1532 /* Never combine loads and stores involving hard regs that are likely
1533 to be spilled. The register allocator can usually handle such
1534 reg-reg moves by tying. If we allow the combiner to make
1535 substitutions of likely-spilled regs, reload might die.
1536 As an exception, we allow combinations involving fixed regs; these are
1537 not available to the register allocator so there's no risk involved. */
1539 set = single_set (insn);
1542 src = SET_SRC (set);
1543 dest = SET_DEST (set);
1544 if (GET_CODE (src) == SUBREG)
1545 src = SUBREG_REG (src);
1546 if (GET_CODE (dest) == SUBREG)
1547 dest = SUBREG_REG (dest);
1548 if (REG_P (src) && REG_P (dest)
1549 && ((REGNO (src) < FIRST_PSEUDO_REGISTER
1550 && ! fixed_regs[REGNO (src)]
1551 && CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (REGNO (src))))
1552 || (REGNO (dest) < FIRST_PSEUDO_REGISTER
1553 && ! fixed_regs[REGNO (dest)]
1554 && CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (REGNO (dest))))))
1560 struct likely_spilled_retval_info
1562 unsigned regno, nregs;
1566 /* Called via note_stores by likely_spilled_retval_p. Remove from info->mask
1567 hard registers that are known to be written to / clobbered in full. */
1569 likely_spilled_retval_1 (rtx x, rtx set, void *data)
1571 struct likely_spilled_retval_info *info = data;
1572 unsigned regno, nregs;
1575 if (!REG_P (XEXP (set, 0)))
1578 if (regno >= info->regno + info->nregs)
1580 nregs = hard_regno_nregs[regno][GET_MODE (x)];
1581 if (regno + nregs <= info->regno)
1583 new_mask = (2U << (nregs - 1)) - 1;
1584 if (regno < info->regno)
1585 new_mask >>= info->regno - regno;
1587 new_mask <<= regno - info->regno;
1588 info->mask &= new_mask;
1591 /* Return nonzero iff part of the return value is live during INSN, and
1592 it is likely spilled. This can happen when more than one insn is needed
1593 to copy the return value, e.g. when we consider to combine into the
1594 second copy insn for a complex value. */
1597 likely_spilled_retval_p (rtx insn)
1599 rtx use = BB_END (this_basic_block);
1601 unsigned regno, nregs;
1602 /* We assume here that no machine mode needs more than
1603 32 hard registers when the value overlaps with a register
1604 for which FUNCTION_VALUE_REGNO_P is true. */
1606 struct likely_spilled_retval_info info;
1608 if (!NONJUMP_INSN_P (use) || GET_CODE (PATTERN (use)) != USE || insn == use)
1610 reg = XEXP (PATTERN (use), 0);
1611 if (!REG_P (reg) || !FUNCTION_VALUE_REGNO_P (REGNO (reg)))
1613 regno = REGNO (reg);
1614 nregs = hard_regno_nregs[regno][GET_MODE (reg)];
1617 mask = (2U << (nregs - 1)) - 1;
1619 /* Disregard parts of the return value that are set later. */
1623 for (p = PREV_INSN (use); info.mask && p != insn; p = PREV_INSN (p))
1624 note_stores (PATTERN (insn), likely_spilled_retval_1, &info);
1627 /* Check if any of the (probably) live return value registers is
1632 if ((mask & 1 << nregs)
1633 && CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (regno + nregs)))
1639 /* Adjust INSN after we made a change to its destination.
1641 Changing the destination can invalidate notes that say something about
1642 the results of the insn and a LOG_LINK pointing to the insn. */
1645 adjust_for_new_dest (rtx insn)
1649 /* For notes, be conservative and simply remove them. */
1650 loc = ®_NOTES (insn);
1653 enum reg_note kind = REG_NOTE_KIND (*loc);
1654 if (kind == REG_EQUAL || kind == REG_EQUIV)
1655 *loc = XEXP (*loc, 1);
1657 loc = &XEXP (*loc, 1);
1660 /* The new insn will have a destination that was previously the destination
1661 of an insn just above it. Call distribute_links to make a LOG_LINK from
1662 the next use of that destination. */
1663 distribute_links (gen_rtx_INSN_LIST (VOIDmode, insn, NULL_RTX));
1666 /* Try to combine the insns I1 and I2 into I3.
1667 Here I1 and I2 appear earlier than I3.
1668 I1 can be zero; then we combine just I2 into I3.
1670 If we are combining three insns and the resulting insn is not recognized,
1671 try splitting it into two insns. If that happens, I2 and I3 are retained
1672 and I1 is pseudo-deleted by turning it into a NOTE. Otherwise, I1 and I2
1675 Return 0 if the combination does not work. Then nothing is changed.
1676 If we did the combination, return the insn at which combine should
1679 Set NEW_DIRECT_JUMP_P to a nonzero value if try_combine creates a
1680 new direct jump instruction. */
1683 try_combine (rtx i3, rtx i2, rtx i1, int *new_direct_jump_p)
1685 /* New patterns for I3 and I2, respectively. */
1686 rtx newpat, newi2pat = 0;
1687 rtvec newpat_vec_with_clobbers = 0;
1688 int substed_i2 = 0, substed_i1 = 0;
1689 /* Indicates need to preserve SET in I1 or I2 in I3 if it is not dead. */
1690 int added_sets_1, added_sets_2;
1691 /* Total number of SETs to put into I3. */
1693 /* Nonzero if I2's body now appears in I3. */
1695 /* INSN_CODEs for new I3, new I2, and user of condition code. */
1696 int insn_code_number, i2_code_number = 0, other_code_number = 0;
1697 /* Contains I3 if the destination of I3 is used in its source, which means
1698 that the old life of I3 is being killed. If that usage is placed into
1699 I2 and not in I3, a REG_DEAD note must be made. */
1700 rtx i3dest_killed = 0;
1701 /* SET_DEST and SET_SRC of I2 and I1. */
1702 rtx i2dest, i2src, i1dest = 0, i1src = 0;
1703 /* PATTERN (I2), or a copy of it in certain cases. */
1705 /* Indicates if I2DEST or I1DEST is in I2SRC or I1_SRC. */
1706 int i2dest_in_i2src = 0, i1dest_in_i1src = 0, i2dest_in_i1src = 0;
1707 int i1_feeds_i3 = 0;
1708 /* Notes that must be added to REG_NOTES in I3 and I2. */
1709 rtx new_i3_notes, new_i2_notes;
1710 /* Notes that we substituted I3 into I2 instead of the normal case. */
1711 int i3_subst_into_i2 = 0;
1712 /* Notes that I1, I2 or I3 is a MULT operation. */
1721 /* Exit early if one of the insns involved can't be used for
1723 if (cant_combine_insn_p (i3)
1724 || cant_combine_insn_p (i2)
1725 || (i1 && cant_combine_insn_p (i1))
1726 || likely_spilled_retval_p (i3)
1727 /* We also can't do anything if I3 has a
1728 REG_LIBCALL note since we don't want to disrupt the contiguity of a
1731 /* ??? This gives worse code, and appears to be unnecessary, since no
1732 pass after flow uses REG_LIBCALL/REG_RETVAL notes. */
1733 || find_reg_note (i3, REG_LIBCALL, NULL_RTX)
1739 undobuf.other_insn = 0;
1741 /* Reset the hard register usage information. */
1742 CLEAR_HARD_REG_SET (newpat_used_regs);
1744 /* If I1 and I2 both feed I3, they can be in any order. To simplify the
1745 code below, set I1 to be the earlier of the two insns. */
1746 if (i1 && INSN_CUID (i1) > INSN_CUID (i2))
1747 temp = i1, i1 = i2, i2 = temp;
1749 added_links_insn = 0;
1751 /* First check for one important special-case that the code below will
1752 not handle. Namely, the case where I1 is zero, I2 is a PARALLEL
1753 and I3 is a SET whose SET_SRC is a SET_DEST in I2. In that case,
1754 we may be able to replace that destination with the destination of I3.
1755 This occurs in the common code where we compute both a quotient and
1756 remainder into a structure, in which case we want to do the computation
1757 directly into the structure to avoid register-register copies.
1759 Note that this case handles both multiple sets in I2 and also
1760 cases where I2 has a number of CLOBBER or PARALLELs.
1762 We make very conservative checks below and only try to handle the
1763 most common cases of this. For example, we only handle the case
1764 where I2 and I3 are adjacent to avoid making difficult register
1767 if (i1 == 0 && NONJUMP_INSN_P (i3) && GET_CODE (PATTERN (i3)) == SET
1768 && REG_P (SET_SRC (PATTERN (i3)))
1769 && REGNO (SET_SRC (PATTERN (i3))) >= FIRST_PSEUDO_REGISTER
1770 && find_reg_note (i3, REG_DEAD, SET_SRC (PATTERN (i3)))
1771 && GET_CODE (PATTERN (i2)) == PARALLEL
1772 && ! side_effects_p (SET_DEST (PATTERN (i3)))
1773 /* If the dest of I3 is a ZERO_EXTRACT or STRICT_LOW_PART, the code
1774 below would need to check what is inside (and reg_overlap_mentioned_p
1775 doesn't support those codes anyway). Don't allow those destinations;
1776 the resulting insn isn't likely to be recognized anyway. */
1777 && GET_CODE (SET_DEST (PATTERN (i3))) != ZERO_EXTRACT
1778 && GET_CODE (SET_DEST (PATTERN (i3))) != STRICT_LOW_PART
1779 && ! reg_overlap_mentioned_p (SET_SRC (PATTERN (i3)),
1780 SET_DEST (PATTERN (i3)))
1781 && next_real_insn (i2) == i3)
1783 rtx p2 = PATTERN (i2);
1785 /* Make sure that the destination of I3,
1786 which we are going to substitute into one output of I2,
1787 is not used within another output of I2. We must avoid making this:
1788 (parallel [(set (mem (reg 69)) ...)
1789 (set (reg 69) ...)])
1790 which is not well-defined as to order of actions.
1791 (Besides, reload can't handle output reloads for this.)
1793 The problem can also happen if the dest of I3 is a memory ref,
1794 if another dest in I2 is an indirect memory ref. */
1795 for (i = 0; i < XVECLEN (p2, 0); i++)
1796 if ((GET_CODE (XVECEXP (p2, 0, i)) == SET
1797 || GET_CODE (XVECEXP (p2, 0, i)) == CLOBBER)
1798 && reg_overlap_mentioned_p (SET_DEST (PATTERN (i3)),
1799 SET_DEST (XVECEXP (p2, 0, i))))
1802 if (i == XVECLEN (p2, 0))
1803 for (i = 0; i < XVECLEN (p2, 0); i++)
1804 if ((GET_CODE (XVECEXP (p2, 0, i)) == SET
1805 || GET_CODE (XVECEXP (p2, 0, i)) == CLOBBER)
1806 && SET_DEST (XVECEXP (p2, 0, i)) == SET_SRC (PATTERN (i3)))
1811 subst_low_cuid = INSN_CUID (i2);
1813 added_sets_2 = added_sets_1 = 0;
1814 i2dest = SET_SRC (PATTERN (i3));
1816 /* Replace the dest in I2 with our dest and make the resulting
1817 insn the new pattern for I3. Then skip to where we
1818 validate the pattern. Everything was set up above. */
1819 SUBST (SET_DEST (XVECEXP (p2, 0, i)),
1820 SET_DEST (PATTERN (i3)));
1823 i3_subst_into_i2 = 1;
1824 goto validate_replacement;
1828 /* If I2 is setting a double-word pseudo to a constant and I3 is setting
1829 one of those words to another constant, merge them by making a new
1832 && (temp = single_set (i2)) != 0
1833 && (GET_CODE (SET_SRC (temp)) == CONST_INT
1834 || GET_CODE (SET_SRC (temp)) == CONST_DOUBLE)
1835 && REG_P (SET_DEST (temp))
1836 && GET_MODE_CLASS (GET_MODE (SET_DEST (temp))) == MODE_INT
1837 && GET_MODE_SIZE (GET_MODE (SET_DEST (temp))) == 2 * UNITS_PER_WORD
1838 && GET_CODE (PATTERN (i3)) == SET
1839 && GET_CODE (SET_DEST (PATTERN (i3))) == SUBREG
1840 && SUBREG_REG (SET_DEST (PATTERN (i3))) == SET_DEST (temp)
1841 && GET_MODE_CLASS (GET_MODE (SET_DEST (PATTERN (i3)))) == MODE_INT
1842 && GET_MODE_SIZE (GET_MODE (SET_DEST (PATTERN (i3)))) == UNITS_PER_WORD
1843 && GET_CODE (SET_SRC (PATTERN (i3))) == CONST_INT)
1845 HOST_WIDE_INT lo, hi;
1847 if (GET_CODE (SET_SRC (temp)) == CONST_INT)
1848 lo = INTVAL (SET_SRC (temp)), hi = lo < 0 ? -1 : 0;
1851 lo = CONST_DOUBLE_LOW (SET_SRC (temp));
1852 hi = CONST_DOUBLE_HIGH (SET_SRC (temp));
1855 if (subreg_lowpart_p (SET_DEST (PATTERN (i3))))
1857 /* We don't handle the case of the target word being wider
1858 than a host wide int. */
1859 gcc_assert (HOST_BITS_PER_WIDE_INT >= BITS_PER_WORD);
1861 lo &= ~(UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD (1) - 1);
1862 lo |= (INTVAL (SET_SRC (PATTERN (i3)))
1863 & (UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD (1) - 1));
1865 else if (HOST_BITS_PER_WIDE_INT == BITS_PER_WORD)
1866 hi = INTVAL (SET_SRC (PATTERN (i3)));
1867 else if (HOST_BITS_PER_WIDE_INT >= 2 * BITS_PER_WORD)
1869 int sign = -(int) ((unsigned HOST_WIDE_INT) lo
1870 >> (HOST_BITS_PER_WIDE_INT - 1));
1872 lo &= ~ (UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD
1873 (UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD (1) - 1));
1874 lo |= (UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD
1875 (INTVAL (SET_SRC (PATTERN (i3)))));
1877 hi = lo < 0 ? -1 : 0;
1880 /* We don't handle the case of the higher word not fitting
1881 entirely in either hi or lo. */
1886 subst_low_cuid = INSN_CUID (i2);
1887 added_sets_2 = added_sets_1 = 0;
1888 i2dest = SET_DEST (temp);
1890 SUBST (SET_SRC (temp),
1891 immed_double_const (lo, hi, GET_MODE (SET_DEST (temp))));
1893 newpat = PATTERN (i2);
1894 goto validate_replacement;
1898 /* If we have no I1 and I2 looks like:
1899 (parallel [(set (reg:CC X) (compare:CC OP (const_int 0)))
1901 make up a dummy I1 that is
1904 (set (reg:CC X) (compare:CC Y (const_int 0)))
1906 (We can ignore any trailing CLOBBERs.)
1908 This undoes a previous combination and allows us to match a branch-and-
1911 if (i1 == 0 && GET_CODE (PATTERN (i2)) == PARALLEL
1912 && XVECLEN (PATTERN (i2), 0) >= 2
1913 && GET_CODE (XVECEXP (PATTERN (i2), 0, 0)) == SET
1914 && (GET_MODE_CLASS (GET_MODE (SET_DEST (XVECEXP (PATTERN (i2), 0, 0))))
1916 && GET_CODE (SET_SRC (XVECEXP (PATTERN (i2), 0, 0))) == COMPARE
1917 && XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 1) == const0_rtx
1918 && GET_CODE (XVECEXP (PATTERN (i2), 0, 1)) == SET
1919 && REG_P (SET_DEST (XVECEXP (PATTERN (i2), 0, 1)))
1920 && rtx_equal_p (XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 0),
1921 SET_SRC (XVECEXP (PATTERN (i2), 0, 1))))
1923 for (i = XVECLEN (PATTERN (i2), 0) - 1; i >= 2; i--)
1924 if (GET_CODE (XVECEXP (PATTERN (i2), 0, i)) != CLOBBER)
1929 /* We make I1 with the same INSN_UID as I2. This gives it
1930 the same INSN_CUID for value tracking. Our fake I1 will
1931 never appear in the insn stream so giving it the same INSN_UID
1932 as I2 will not cause a problem. */
1934 i1 = gen_rtx_INSN (VOIDmode, INSN_UID (i2), NULL_RTX, i2,
1935 BLOCK_FOR_INSN (i2), INSN_LOCATOR (i2),
1936 XVECEXP (PATTERN (i2), 0, 1), -1, NULL_RTX,
1939 SUBST (PATTERN (i2), XVECEXP (PATTERN (i2), 0, 0));
1940 SUBST (XEXP (SET_SRC (PATTERN (i2)), 0),
1941 SET_DEST (PATTERN (i1)));
1946 /* Verify that I2 and I1 are valid for combining. */
1947 if (! can_combine_p (i2, i3, i1, NULL_RTX, &i2dest, &i2src)
1948 || (i1 && ! can_combine_p (i1, i3, NULL_RTX, i2, &i1dest, &i1src)))
1954 /* Record whether I2DEST is used in I2SRC and similarly for the other
1955 cases. Knowing this will help in register status updating below. */
1956 i2dest_in_i2src = reg_overlap_mentioned_p (i2dest, i2src);
1957 i1dest_in_i1src = i1 && reg_overlap_mentioned_p (i1dest, i1src);
1958 i2dest_in_i1src = i1 && reg_overlap_mentioned_p (i2dest, i1src);
1960 /* See if I1 directly feeds into I3. It does if I1DEST is not used
1962 i1_feeds_i3 = i1 && ! reg_overlap_mentioned_p (i1dest, i2src);
1964 /* Ensure that I3's pattern can be the destination of combines. */
1965 if (! combinable_i3pat (i3, &PATTERN (i3), i2dest, i1dest,
1966 i1 && i2dest_in_i1src && i1_feeds_i3,
1973 /* See if any of the insns is a MULT operation. Unless one is, we will
1974 reject a combination that is, since it must be slower. Be conservative
1976 if (GET_CODE (i2src) == MULT
1977 || (i1 != 0 && GET_CODE (i1src) == MULT)
1978 || (GET_CODE (PATTERN (i3)) == SET
1979 && GET_CODE (SET_SRC (PATTERN (i3))) == MULT))
1982 /* If I3 has an inc, then give up if I1 or I2 uses the reg that is inc'd.
1983 We used to do this EXCEPT in one case: I3 has a post-inc in an
1984 output operand. However, that exception can give rise to insns like
1986 which is a famous insn on the PDP-11 where the value of r3 used as the
1987 source was model-dependent. Avoid this sort of thing. */
1990 if (!(GET_CODE (PATTERN (i3)) == SET
1991 && REG_P (SET_SRC (PATTERN (i3)))
1992 && MEM_P (SET_DEST (PATTERN (i3)))
1993 && (GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_INC
1994 || GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_DEC)))
1995 /* It's not the exception. */
1998 for (link = REG_NOTES (i3); link; link = XEXP (link, 1))
1999 if (REG_NOTE_KIND (link) == REG_INC
2000 && (reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i2))
2002 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i1)))))
2009 /* See if the SETs in I1 or I2 need to be kept around in the merged
2010 instruction: whenever the value set there is still needed past I3.
2011 For the SETs in I2, this is easy: we see if I2DEST dies or is set in I3.
2013 For the SET in I1, we have two cases: If I1 and I2 independently
2014 feed into I3, the set in I1 needs to be kept around if I1DEST dies
2015 or is set in I3. Otherwise (if I1 feeds I2 which feeds I3), the set
2016 in I1 needs to be kept around unless I1DEST dies or is set in either
2017 I2 or I3. We can distinguish these cases by seeing if I2SRC mentions
2018 I1DEST. If so, we know I1 feeds into I2. */
2020 added_sets_2 = ! dead_or_set_p (i3, i2dest);
2023 = i1 && ! (i1_feeds_i3 ? dead_or_set_p (i3, i1dest)
2024 : (dead_or_set_p (i3, i1dest) || dead_or_set_p (i2, i1dest)));
2026 /* If the set in I2 needs to be kept around, we must make a copy of
2027 PATTERN (I2), so that when we substitute I1SRC for I1DEST in
2028 PATTERN (I2), we are only substituting for the original I1DEST, not into
2029 an already-substituted copy. This also prevents making self-referential
2030 rtx. If I2 is a PARALLEL, we just need the piece that assigns I2SRC to
2033 i2pat = (GET_CODE (PATTERN (i2)) == PARALLEL
2034 ? gen_rtx_SET (VOIDmode, i2dest, i2src)
2038 i2pat = copy_rtx (i2pat);
2042 /* Substitute in the latest insn for the regs set by the earlier ones. */
2044 maxreg = max_reg_num ();
2048 /* It is possible that the source of I2 or I1 may be performing an
2049 unneeded operation, such as a ZERO_EXTEND of something that is known
2050 to have the high part zero. Handle that case by letting subst look at
2051 the innermost one of them.
2053 Another way to do this would be to have a function that tries to
2054 simplify a single insn instead of merging two or more insns. We don't
2055 do this because of the potential of infinite loops and because
2056 of the potential extra memory required. However, doing it the way
2057 we are is a bit of a kludge and doesn't catch all cases.
2059 But only do this if -fexpensive-optimizations since it slows things down
2060 and doesn't usually win. */
2062 if (flag_expensive_optimizations)
2064 /* Pass pc_rtx so no substitutions are done, just simplifications. */
2067 subst_low_cuid = INSN_CUID (i1);
2068 i1src = subst (i1src, pc_rtx, pc_rtx, 0, 0);
2072 subst_low_cuid = INSN_CUID (i2);
2073 i2src = subst (i2src, pc_rtx, pc_rtx, 0, 0);
2078 /* Many machines that don't use CC0 have insns that can both perform an
2079 arithmetic operation and set the condition code. These operations will
2080 be represented as a PARALLEL with the first element of the vector
2081 being a COMPARE of an arithmetic operation with the constant zero.
2082 The second element of the vector will set some pseudo to the result
2083 of the same arithmetic operation. If we simplify the COMPARE, we won't
2084 match such a pattern and so will generate an extra insn. Here we test
2085 for this case, where both the comparison and the operation result are
2086 needed, and make the PARALLEL by just replacing I2DEST in I3SRC with
2087 I2SRC. Later we will make the PARALLEL that contains I2. */
2089 if (i1 == 0 && added_sets_2 && GET_CODE (PATTERN (i3)) == SET
2090 && GET_CODE (SET_SRC (PATTERN (i3))) == COMPARE
2091 && XEXP (SET_SRC (PATTERN (i3)), 1) == const0_rtx
2092 && rtx_equal_p (XEXP (SET_SRC (PATTERN (i3)), 0), i2dest))
2094 #ifdef SELECT_CC_MODE
2096 enum machine_mode compare_mode;
2099 newpat = PATTERN (i3);
2100 SUBST (XEXP (SET_SRC (newpat), 0), i2src);
2104 #ifdef SELECT_CC_MODE
2105 /* See if a COMPARE with the operand we substituted in should be done
2106 with the mode that is currently being used. If not, do the same
2107 processing we do in `subst' for a SET; namely, if the destination
2108 is used only once, try to replace it with a register of the proper
2109 mode and also replace the COMPARE. */
2110 if (undobuf.other_insn == 0
2111 && (cc_use = find_single_use (SET_DEST (newpat), i3,
2112 &undobuf.other_insn))
2113 && ((compare_mode = SELECT_CC_MODE (GET_CODE (*cc_use),
2115 != GET_MODE (SET_DEST (newpat))))
2117 unsigned int regno = REGNO (SET_DEST (newpat));
2118 rtx new_dest = gen_rtx_REG (compare_mode, regno);
2120 if (regno < FIRST_PSEUDO_REGISTER
2121 || (REG_N_SETS (regno) == 1 && ! added_sets_2
2122 && ! REG_USERVAR_P (SET_DEST (newpat))))
2124 if (regno >= FIRST_PSEUDO_REGISTER)
2125 SUBST (regno_reg_rtx[regno], new_dest);
2127 SUBST (SET_DEST (newpat), new_dest);
2128 SUBST (XEXP (*cc_use, 0), new_dest);
2129 SUBST (SET_SRC (newpat),
2130 gen_rtx_COMPARE (compare_mode, i2src, const0_rtx));
2133 undobuf.other_insn = 0;
2140 n_occurrences = 0; /* `subst' counts here */
2142 /* If I1 feeds into I2 (not into I3) and I1DEST is in I1SRC, we
2143 need to make a unique copy of I2SRC each time we substitute it
2144 to avoid self-referential rtl. */
2146 subst_low_cuid = INSN_CUID (i2);
2147 newpat = subst (PATTERN (i3), i2dest, i2src, 0,
2148 ! i1_feeds_i3 && i1dest_in_i1src);
2151 /* Record whether i2's body now appears within i3's body. */
2152 i2_is_used = n_occurrences;
2155 /* If we already got a failure, don't try to do more. Otherwise,
2156 try to substitute in I1 if we have it. */
2158 if (i1 && GET_CODE (newpat) != CLOBBER)
2160 /* Before we can do this substitution, we must redo the test done
2161 above (see detailed comments there) that ensures that I1DEST
2162 isn't mentioned in any SETs in NEWPAT that are field assignments. */
2164 if (! combinable_i3pat (NULL_RTX, &newpat, i1dest, NULL_RTX,
2172 subst_low_cuid = INSN_CUID (i1);
2173 newpat = subst (newpat, i1dest, i1src, 0, 0);
2177 /* Fail if an autoincrement side-effect has been duplicated. Be careful
2178 to count all the ways that I2SRC and I1SRC can be used. */
2179 if ((FIND_REG_INC_NOTE (i2, NULL_RTX) != 0
2180 && i2_is_used + added_sets_2 > 1)
2181 || (i1 != 0 && FIND_REG_INC_NOTE (i1, NULL_RTX) != 0
2182 && (n_occurrences + added_sets_1 + (added_sets_2 && ! i1_feeds_i3)
2184 /* Fail if we tried to make a new register. */
2185 || max_reg_num () != maxreg
2186 /* Fail if we couldn't do something and have a CLOBBER. */
2187 || GET_CODE (newpat) == CLOBBER
2188 /* Fail if this new pattern is a MULT and we didn't have one before
2189 at the outer level. */
2190 || (GET_CODE (newpat) == SET && GET_CODE (SET_SRC (newpat)) == MULT
2197 /* If the actions of the earlier insns must be kept
2198 in addition to substituting them into the latest one,
2199 we must make a new PARALLEL for the latest insn
2200 to hold additional the SETs. */
2202 if (added_sets_1 || added_sets_2)
2206 if (GET_CODE (newpat) == PARALLEL)
2208 rtvec old = XVEC (newpat, 0);
2209 total_sets = XVECLEN (newpat, 0) + added_sets_1 + added_sets_2;
2210 newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (total_sets));
2211 memcpy (XVEC (newpat, 0)->elem, &old->elem[0],
2212 sizeof (old->elem[0]) * old->num_elem);
2217 total_sets = 1 + added_sets_1 + added_sets_2;
2218 newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (total_sets));
2219 XVECEXP (newpat, 0, 0) = old;
2223 XVECEXP (newpat, 0, --total_sets)
2224 = (GET_CODE (PATTERN (i1)) == PARALLEL
2225 ? gen_rtx_SET (VOIDmode, i1dest, i1src) : PATTERN (i1));
2229 /* If there is no I1, use I2's body as is. We used to also not do
2230 the subst call below if I2 was substituted into I3,
2231 but that could lose a simplification. */
2233 XVECEXP (newpat, 0, --total_sets) = i2pat;
2235 /* See comment where i2pat is assigned. */
2236 XVECEXP (newpat, 0, --total_sets)
2237 = subst (i2pat, i1dest, i1src, 0, 0);
2241 /* We come here when we are replacing a destination in I2 with the
2242 destination of I3. */
2243 validate_replacement:
2245 /* Note which hard regs this insn has as inputs. */
2246 mark_used_regs_combine (newpat);
2248 /* If recog_for_combine fails, it strips existing clobbers. If we'll
2249 consider splitting this pattern, we might need these clobbers. */
2250 if (i1 && GET_CODE (newpat) == PARALLEL
2251 && GET_CODE (XVECEXP (newpat, 0, XVECLEN (newpat, 0) - 1)) == CLOBBER)
2253 int len = XVECLEN (newpat, 0);
2255 newpat_vec_with_clobbers = rtvec_alloc (len);
2256 for (i = 0; i < len; i++)
2257 RTVEC_ELT (newpat_vec_with_clobbers, i) = XVECEXP (newpat, 0, i);
2260 /* Is the result of combination a valid instruction? */
2261 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2263 /* If the result isn't valid, see if it is a PARALLEL of two SETs where
2264 the second SET's destination is a register that is unused and isn't
2265 marked as an instruction that might trap in an EH region. In that case,
2266 we just need the first SET. This can occur when simplifying a divmod
2267 insn. We *must* test for this case here because the code below that
2268 splits two independent SETs doesn't handle this case correctly when it
2269 updates the register status.
2271 It's pointless doing this if we originally had two sets, one from
2272 i3, and one from i2. Combining then splitting the parallel results
2273 in the original i2 again plus an invalid insn (which we delete).
2274 The net effect is only to move instructions around, which makes
2275 debug info less accurate.
2277 Also check the case where the first SET's destination is unused.
2278 That would not cause incorrect code, but does cause an unneeded
2281 if (insn_code_number < 0
2282 && !(added_sets_2 && i1 == 0)
2283 && GET_CODE (newpat) == PARALLEL
2284 && XVECLEN (newpat, 0) == 2
2285 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
2286 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
2287 && asm_noperands (newpat) < 0)
2289 rtx set0 = XVECEXP (newpat, 0, 0);
2290 rtx set1 = XVECEXP (newpat, 0, 1);
2293 if (((REG_P (SET_DEST (set1))
2294 && find_reg_note (i3, REG_UNUSED, SET_DEST (set1)))
2295 || (GET_CODE (SET_DEST (set1)) == SUBREG
2296 && find_reg_note (i3, REG_UNUSED, SUBREG_REG (SET_DEST (set1)))))
2297 && (!(note = find_reg_note (i3, REG_EH_REGION, NULL_RTX))
2298 || INTVAL (XEXP (note, 0)) <= 0)
2299 && ! side_effects_p (SET_SRC (set1)))
2302 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2305 else if (((REG_P (SET_DEST (set0))
2306 && find_reg_note (i3, REG_UNUSED, SET_DEST (set0)))
2307 || (GET_CODE (SET_DEST (set0)) == SUBREG
2308 && find_reg_note (i3, REG_UNUSED,
2309 SUBREG_REG (SET_DEST (set0)))))
2310 && (!(note = find_reg_note (i3, REG_EH_REGION, NULL_RTX))
2311 || INTVAL (XEXP (note, 0)) <= 0)
2312 && ! side_effects_p (SET_SRC (set0)))
2315 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2317 if (insn_code_number >= 0)
2319 /* If we will be able to accept this, we have made a
2320 change to the destination of I3. This requires us to
2321 do a few adjustments. */
2323 PATTERN (i3) = newpat;
2324 adjust_for_new_dest (i3);
2329 /* If we were combining three insns and the result is a simple SET
2330 with no ASM_OPERANDS that wasn't recognized, try to split it into two
2331 insns. There are two ways to do this. It can be split using a
2332 machine-specific method (like when you have an addition of a large
2333 constant) or by combine in the function find_split_point. */
2335 if (i1 && insn_code_number < 0 && GET_CODE (newpat) == SET
2336 && asm_noperands (newpat) < 0)
2338 rtx m_split, *split;
2339 rtx ni2dest = i2dest;
2341 /* See if the MD file can split NEWPAT. If it can't, see if letting it
2342 use I2DEST as a scratch register will help. In the latter case,
2343 convert I2DEST to the mode of the source of NEWPAT if we can. */
2345 m_split = split_insns (newpat, i3);
2347 /* We can only use I2DEST as a scratch reg if it doesn't overlap any
2348 inputs of NEWPAT. */
2350 /* ??? If I2DEST is not safe, and I1DEST exists, then it would be
2351 possible to try that as a scratch reg. This would require adding
2352 more code to make it work though. */
2354 if (m_split == 0 && ! reg_overlap_mentioned_p (ni2dest, newpat))
2356 /* If I2DEST is a hard register or the only use of a pseudo,
2357 we can change its mode. */
2358 if (GET_MODE (SET_DEST (newpat)) != GET_MODE (i2dest)
2359 && GET_MODE (SET_DEST (newpat)) != VOIDmode
2361 && (REGNO (i2dest) < FIRST_PSEUDO_REGISTER
2362 || (REG_N_SETS (REGNO (i2dest)) == 1 && ! added_sets_2
2363 && ! REG_USERVAR_P (i2dest))))
2364 ni2dest = gen_rtx_REG (GET_MODE (SET_DEST (newpat)),
2367 m_split = split_insns (gen_rtx_PARALLEL
2369 gen_rtvec (2, newpat,
2370 gen_rtx_CLOBBER (VOIDmode,
2373 /* If the split with the mode-changed register didn't work, try
2374 the original register. */
2375 if (! m_split && ni2dest != i2dest)
2378 m_split = split_insns (gen_rtx_PARALLEL
2380 gen_rtvec (2, newpat,
2381 gen_rtx_CLOBBER (VOIDmode,
2387 /* If recog_for_combine has discarded clobbers, try to use them
2388 again for the split. */
2389 if (m_split == 0 && newpat_vec_with_clobbers)
2391 = split_insns (gen_rtx_PARALLEL (VOIDmode,
2392 newpat_vec_with_clobbers), i3);
2394 if (m_split && NEXT_INSN (m_split) == NULL_RTX)
2396 m_split = PATTERN (m_split);
2397 insn_code_number = recog_for_combine (&m_split, i3, &new_i3_notes);
2398 if (insn_code_number >= 0)
2401 else if (m_split && NEXT_INSN (NEXT_INSN (m_split)) == NULL_RTX
2402 && (next_real_insn (i2) == i3
2403 || ! use_crosses_set_p (PATTERN (m_split), INSN_CUID (i2))))
2406 rtx newi3pat = PATTERN (NEXT_INSN (m_split));
2407 newi2pat = PATTERN (m_split);
2409 i3set = single_set (NEXT_INSN (m_split));
2410 i2set = single_set (m_split);
2412 /* In case we changed the mode of I2DEST, replace it in the
2413 pseudo-register table here. We can't do it above in case this
2414 code doesn't get executed and we do a split the other way. */
2416 if (REGNO (i2dest) >= FIRST_PSEUDO_REGISTER)
2417 SUBST (regno_reg_rtx[REGNO (i2dest)], ni2dest);
2419 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
2421 /* If I2 or I3 has multiple SETs, we won't know how to track
2422 register status, so don't use these insns. If I2's destination
2423 is used between I2 and I3, we also can't use these insns. */
2425 if (i2_code_number >= 0 && i2set && i3set
2426 && (next_real_insn (i2) == i3
2427 || ! reg_used_between_p (SET_DEST (i2set), i2, i3)))
2428 insn_code_number = recog_for_combine (&newi3pat, i3,
2430 if (insn_code_number >= 0)
2433 /* It is possible that both insns now set the destination of I3.
2434 If so, we must show an extra use of it. */
2436 if (insn_code_number >= 0)
2438 rtx new_i3_dest = SET_DEST (i3set);
2439 rtx new_i2_dest = SET_DEST (i2set);
2441 while (GET_CODE (new_i3_dest) == ZERO_EXTRACT
2442 || GET_CODE (new_i3_dest) == STRICT_LOW_PART
2443 || GET_CODE (new_i3_dest) == SUBREG)
2444 new_i3_dest = XEXP (new_i3_dest, 0);
2446 while (GET_CODE (new_i2_dest) == ZERO_EXTRACT
2447 || GET_CODE (new_i2_dest) == STRICT_LOW_PART
2448 || GET_CODE (new_i2_dest) == SUBREG)
2449 new_i2_dest = XEXP (new_i2_dest, 0);
2451 if (REG_P (new_i3_dest)
2452 && REG_P (new_i2_dest)
2453 && REGNO (new_i3_dest) == REGNO (new_i2_dest))
2454 REG_N_SETS (REGNO (new_i2_dest))++;
2458 /* If we can split it and use I2DEST, go ahead and see if that
2459 helps things be recognized. Verify that none of the registers
2460 are set between I2 and I3. */
2461 if (insn_code_number < 0 && (split = find_split_point (&newpat, i3)) != 0
2465 /* We need I2DEST in the proper mode. If it is a hard register
2466 or the only use of a pseudo, we can change its mode.
2467 Make sure we don't change a hard register to have a mode that
2468 isn't valid for it, or change the number of registers. */
2469 && (GET_MODE (*split) == GET_MODE (i2dest)
2470 || GET_MODE (*split) == VOIDmode
2471 || (REGNO (i2dest) < FIRST_PSEUDO_REGISTER
2472 && HARD_REGNO_MODE_OK (REGNO (i2dest), GET_MODE (*split))
2473 && (hard_regno_nregs[REGNO (i2dest)][GET_MODE (i2dest)]
2474 == hard_regno_nregs[REGNO (i2dest)][GET_MODE (*split)]))
2475 || (REGNO (i2dest) >= FIRST_PSEUDO_REGISTER
2476 && REG_N_SETS (REGNO (i2dest)) == 1 && ! added_sets_2
2477 && ! REG_USERVAR_P (i2dest)))
2478 && (next_real_insn (i2) == i3
2479 || ! use_crosses_set_p (*split, INSN_CUID (i2)))
2480 /* We can't overwrite I2DEST if its value is still used by
2482 && ! reg_referenced_p (i2dest, newpat))
2484 rtx newdest = i2dest;
2485 enum rtx_code split_code = GET_CODE (*split);
2486 enum machine_mode split_mode = GET_MODE (*split);
2488 /* Get NEWDEST as a register in the proper mode. We have already
2489 validated that we can do this. */
2490 if (GET_MODE (i2dest) != split_mode && split_mode != VOIDmode)
2492 newdest = gen_rtx_REG (split_mode, REGNO (i2dest));
2494 if (REGNO (i2dest) >= FIRST_PSEUDO_REGISTER)
2495 SUBST (regno_reg_rtx[REGNO (i2dest)], newdest);
2498 /* If *SPLIT is a (mult FOO (const_int pow2)), convert it to
2499 an ASHIFT. This can occur if it was inside a PLUS and hence
2500 appeared to be a memory address. This is a kludge. */
2501 if (split_code == MULT
2502 && GET_CODE (XEXP (*split, 1)) == CONST_INT
2503 && INTVAL (XEXP (*split, 1)) > 0
2504 && (i = exact_log2 (INTVAL (XEXP (*split, 1)))) >= 0)
2506 SUBST (*split, gen_rtx_ASHIFT (split_mode,
2507 XEXP (*split, 0), GEN_INT (i)));
2508 /* Update split_code because we may not have a multiply
2510 split_code = GET_CODE (*split);
2513 #ifdef INSN_SCHEDULING
2514 /* If *SPLIT is a paradoxical SUBREG, when we split it, it should
2515 be written as a ZERO_EXTEND. */
2516 if (split_code == SUBREG && MEM_P (SUBREG_REG (*split)))
2518 #ifdef LOAD_EXTEND_OP
2519 /* Or as a SIGN_EXTEND if LOAD_EXTEND_OP says that that's
2520 what it really is. */
2521 if (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (*split)))
2523 SUBST (*split, gen_rtx_SIGN_EXTEND (split_mode,
2524 SUBREG_REG (*split)));
2527 SUBST (*split, gen_rtx_ZERO_EXTEND (split_mode,
2528 SUBREG_REG (*split)));
2532 newi2pat = gen_rtx_SET (VOIDmode, newdest, *split);
2533 SUBST (*split, newdest);
2534 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
2536 /* recog_for_combine might have added CLOBBERs to newi2pat.
2537 Make sure NEWPAT does not depend on the clobbered regs. */
2538 if (GET_CODE (newi2pat) == PARALLEL)
2539 for (i = XVECLEN (newi2pat, 0) - 1; i >= 0; i--)
2540 if (GET_CODE (XVECEXP (newi2pat, 0, i)) == CLOBBER)
2542 rtx reg = XEXP (XVECEXP (newi2pat, 0, i), 0);
2543 if (reg_overlap_mentioned_p (reg, newpat))
2550 /* If the split point was a MULT and we didn't have one before,
2551 don't use one now. */
2552 if (i2_code_number >= 0 && ! (split_code == MULT && ! have_mult))
2553 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2557 /* Check for a case where we loaded from memory in a narrow mode and
2558 then sign extended it, but we need both registers. In that case,
2559 we have a PARALLEL with both loads from the same memory location.
2560 We can split this into a load from memory followed by a register-register
2561 copy. This saves at least one insn, more if register allocation can
2564 We cannot do this if the destination of the first assignment is a
2565 condition code register or cc0. We eliminate this case by making sure
2566 the SET_DEST and SET_SRC have the same mode.
2568 We cannot do this if the destination of the second assignment is
2569 a register that we have already assumed is zero-extended. Similarly
2570 for a SUBREG of such a register. */
2572 else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0
2573 && GET_CODE (newpat) == PARALLEL
2574 && XVECLEN (newpat, 0) == 2
2575 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
2576 && GET_CODE (SET_SRC (XVECEXP (newpat, 0, 0))) == SIGN_EXTEND
2577 && (GET_MODE (SET_DEST (XVECEXP (newpat, 0, 0)))
2578 == GET_MODE (SET_SRC (XVECEXP (newpat, 0, 0))))
2579 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
2580 && rtx_equal_p (SET_SRC (XVECEXP (newpat, 0, 1)),
2581 XEXP (SET_SRC (XVECEXP (newpat, 0, 0)), 0))
2582 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)),
2584 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
2585 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
2586 && ! (temp = SET_DEST (XVECEXP (newpat, 0, 1)),
2588 && reg_stat[REGNO (temp)].nonzero_bits != 0
2589 && GET_MODE_BITSIZE (GET_MODE (temp)) < BITS_PER_WORD
2590 && GET_MODE_BITSIZE (GET_MODE (temp)) < HOST_BITS_PER_INT
2591 && (reg_stat[REGNO (temp)].nonzero_bits
2592 != GET_MODE_MASK (word_mode))))
2593 && ! (GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) == SUBREG
2594 && (temp = SUBREG_REG (SET_DEST (XVECEXP (newpat, 0, 1))),
2596 && reg_stat[REGNO (temp)].nonzero_bits != 0
2597 && GET_MODE_BITSIZE (GET_MODE (temp)) < BITS_PER_WORD
2598 && GET_MODE_BITSIZE (GET_MODE (temp)) < HOST_BITS_PER_INT
2599 && (reg_stat[REGNO (temp)].nonzero_bits
2600 != GET_MODE_MASK (word_mode)))))
2601 && ! reg_overlap_mentioned_p (SET_DEST (XVECEXP (newpat, 0, 1)),
2602 SET_SRC (XVECEXP (newpat, 0, 1)))
2603 && ! find_reg_note (i3, REG_UNUSED,
2604 SET_DEST (XVECEXP (newpat, 0, 0))))
2608 newi2pat = XVECEXP (newpat, 0, 0);
2609 ni2dest = SET_DEST (XVECEXP (newpat, 0, 0));
2610 newpat = XVECEXP (newpat, 0, 1);
2611 SUBST (SET_SRC (newpat),
2612 gen_lowpart (GET_MODE (SET_SRC (newpat)), ni2dest));
2613 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
2615 if (i2_code_number >= 0)
2616 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2618 if (insn_code_number >= 0)
2622 /* Similarly, check for a case where we have a PARALLEL of two independent
2623 SETs but we started with three insns. In this case, we can do the sets
2624 as two separate insns. This case occurs when some SET allows two
2625 other insns to combine, but the destination of that SET is still live. */
2627 else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0
2628 && GET_CODE (newpat) == PARALLEL
2629 && XVECLEN (newpat, 0) == 2
2630 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
2631 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != ZERO_EXTRACT
2632 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != STRICT_LOW_PART
2633 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
2634 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
2635 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
2636 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)),
2638 /* Don't pass sets with (USE (MEM ...)) dests to the following. */
2639 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != USE
2640 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != USE
2641 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 1)),
2642 XVECEXP (newpat, 0, 0))
2643 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 0)),
2644 XVECEXP (newpat, 0, 1))
2645 && ! (contains_muldiv (SET_SRC (XVECEXP (newpat, 0, 0)))
2646 && contains_muldiv (SET_SRC (XVECEXP (newpat, 0, 1)))))
2648 /* Normally, it doesn't matter which of the two is done first,
2649 but it does if one references cc0. In that case, it has to
2652 if (reg_referenced_p (cc0_rtx, XVECEXP (newpat, 0, 0)))
2654 newi2pat = XVECEXP (newpat, 0, 0);
2655 newpat = XVECEXP (newpat, 0, 1);
2660 newi2pat = XVECEXP (newpat, 0, 1);
2661 newpat = XVECEXP (newpat, 0, 0);
2664 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
2666 if (i2_code_number >= 0)
2667 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2670 /* If it still isn't recognized, fail and change things back the way they
2672 if ((insn_code_number < 0
2673 /* Is the result a reasonable ASM_OPERANDS? */
2674 && (! check_asm_operands (newpat) || added_sets_1 || added_sets_2)))
2680 /* If we had to change another insn, make sure it is valid also. */
2681 if (undobuf.other_insn)
2683 rtx other_pat = PATTERN (undobuf.other_insn);
2684 rtx new_other_notes;
2687 CLEAR_HARD_REG_SET (newpat_used_regs);
2689 other_code_number = recog_for_combine (&other_pat, undobuf.other_insn,
2692 if (other_code_number < 0 && ! check_asm_operands (other_pat))
2698 PATTERN (undobuf.other_insn) = other_pat;
2700 /* If any of the notes in OTHER_INSN were REG_UNUSED, ensure that they
2701 are still valid. Then add any non-duplicate notes added by
2702 recog_for_combine. */
2703 for (note = REG_NOTES (undobuf.other_insn); note; note = next)
2705 next = XEXP (note, 1);
2707 if (REG_NOTE_KIND (note) == REG_UNUSED
2708 && ! reg_set_p (XEXP (note, 0), PATTERN (undobuf.other_insn)))
2710 if (REG_P (XEXP (note, 0)))
2711 REG_N_DEATHS (REGNO (XEXP (note, 0)))--;
2713 remove_note (undobuf.other_insn, note);
2717 for (note = new_other_notes; note; note = XEXP (note, 1))
2718 if (REG_P (XEXP (note, 0)))
2719 REG_N_DEATHS (REGNO (XEXP (note, 0)))++;
2721 distribute_notes (new_other_notes, undobuf.other_insn,
2722 undobuf.other_insn, NULL_RTX);
2725 /* If I2 is the CC0 setter and I3 is the CC0 user then check whether
2726 they are adjacent to each other or not. */
2728 rtx p = prev_nonnote_insn (i3);
2729 if (p && p != i2 && NONJUMP_INSN_P (p) && newi2pat
2730 && sets_cc0_p (newi2pat))
2738 /* Only allow this combination if insn_rtx_costs reports that the
2739 replacement instructions are cheaper than the originals. */
2740 if (!combine_validate_cost (i1, i2, i3, newpat, newi2pat))
2746 /* We now know that we can do this combination. Merge the insns and
2747 update the status of registers and LOG_LINKS. */
2755 /* I3 now uses what used to be its destination and which is now
2756 I2's destination. This requires us to do a few adjustments. */
2757 PATTERN (i3) = newpat;
2758 adjust_for_new_dest (i3);
2760 /* We need a LOG_LINK from I3 to I2. But we used to have one,
2763 However, some later insn might be using I2's dest and have
2764 a LOG_LINK pointing at I3. We must remove this link.
2765 The simplest way to remove the link is to point it at I1,
2766 which we know will be a NOTE. */
2768 /* newi2pat is usually a SET here; however, recog_for_combine might
2769 have added some clobbers. */
2770 if (GET_CODE (newi2pat) == PARALLEL)
2771 ni2dest = SET_DEST (XVECEXP (newi2pat, 0, 0));
2773 ni2dest = SET_DEST (newi2pat);
2775 for (insn = NEXT_INSN (i3);
2776 insn && (this_basic_block->next_bb == EXIT_BLOCK_PTR
2777 || insn != BB_HEAD (this_basic_block->next_bb));
2778 insn = NEXT_INSN (insn))
2780 if (INSN_P (insn) && reg_referenced_p (ni2dest, PATTERN (insn)))
2782 for (link = LOG_LINKS (insn); link;
2783 link = XEXP (link, 1))
2784 if (XEXP (link, 0) == i3)
2785 XEXP (link, 0) = i1;
2793 rtx i3notes, i2notes, i1notes = 0;
2794 rtx i3links, i2links, i1links = 0;
2798 /* Get the old REG_NOTES and LOG_LINKS from all our insns and
2800 i3notes = REG_NOTES (i3), i3links = LOG_LINKS (i3);
2801 i2notes = REG_NOTES (i2), i2links = LOG_LINKS (i2);
2803 i1notes = REG_NOTES (i1), i1links = LOG_LINKS (i1);
2805 /* Ensure that we do not have something that should not be shared but
2806 occurs multiple times in the new insns. Check this by first
2807 resetting all the `used' flags and then copying anything is shared. */
2809 reset_used_flags (i3notes);
2810 reset_used_flags (i2notes);
2811 reset_used_flags (i1notes);
2812 reset_used_flags (newpat);
2813 reset_used_flags (newi2pat);
2814 if (undobuf.other_insn)
2815 reset_used_flags (PATTERN (undobuf.other_insn));
2817 i3notes = copy_rtx_if_shared (i3notes);
2818 i2notes = copy_rtx_if_shared (i2notes);
2819 i1notes = copy_rtx_if_shared (i1notes);
2820 newpat = copy_rtx_if_shared (newpat);
2821 newi2pat = copy_rtx_if_shared (newi2pat);
2822 if (undobuf.other_insn)
2823 reset_used_flags (PATTERN (undobuf.other_insn));
2825 INSN_CODE (i3) = insn_code_number;
2826 PATTERN (i3) = newpat;
2828 if (CALL_P (i3) && CALL_INSN_FUNCTION_USAGE (i3))
2830 rtx call_usage = CALL_INSN_FUNCTION_USAGE (i3);
2832 reset_used_flags (call_usage);
2833 call_usage = copy_rtx (call_usage);
2836 replace_rtx (call_usage, i2dest, i2src);
2839 replace_rtx (call_usage, i1dest, i1src);
2841 CALL_INSN_FUNCTION_USAGE (i3) = call_usage;
2844 if (undobuf.other_insn)
2845 INSN_CODE (undobuf.other_insn) = other_code_number;
2847 /* We had one special case above where I2 had more than one set and
2848 we replaced a destination of one of those sets with the destination
2849 of I3. In that case, we have to update LOG_LINKS of insns later
2850 in this basic block. Note that this (expensive) case is rare.
2852 Also, in this case, we must pretend that all REG_NOTEs for I2
2853 actually came from I3, so that REG_UNUSED notes from I2 will be
2854 properly handled. */
2856 if (i3_subst_into_i2)
2858 for (i = 0; i < XVECLEN (PATTERN (i2), 0); i++)
2859 if (GET_CODE (XVECEXP (PATTERN (i2), 0, i)) != USE
2860 && REG_P (SET_DEST (XVECEXP (PATTERN (i2), 0, i)))
2861 && SET_DEST (XVECEXP (PATTERN (i2), 0, i)) != i2dest
2862 && ! find_reg_note (i2, REG_UNUSED,
2863 SET_DEST (XVECEXP (PATTERN (i2), 0, i))))
2864 for (temp = NEXT_INSN (i2);
2865 temp && (this_basic_block->next_bb == EXIT_BLOCK_PTR
2866 || BB_HEAD (this_basic_block) != temp);
2867 temp = NEXT_INSN (temp))
2868 if (temp != i3 && INSN_P (temp))
2869 for (link = LOG_LINKS (temp); link; link = XEXP (link, 1))
2870 if (XEXP (link, 0) == i2)
2871 XEXP (link, 0) = i3;
2876 while (XEXP (link, 1))
2877 link = XEXP (link, 1);
2878 XEXP (link, 1) = i2notes;
2892 INSN_CODE (i2) = i2_code_number;
2893 PATTERN (i2) = newi2pat;
2896 SET_INSN_DELETED (i2);
2902 SET_INSN_DELETED (i1);
2905 /* Get death notes for everything that is now used in either I3 or
2906 I2 and used to die in a previous insn. If we built two new
2907 patterns, move from I1 to I2 then I2 to I3 so that we get the
2908 proper movement on registers that I2 modifies. */
2912 move_deaths (newi2pat, NULL_RTX, INSN_CUID (i1), i2, &midnotes);
2913 move_deaths (newpat, newi2pat, INSN_CUID (i1), i3, &midnotes);
2916 move_deaths (newpat, NULL_RTX, i1 ? INSN_CUID (i1) : INSN_CUID (i2),
2919 /* Distribute all the LOG_LINKS and REG_NOTES from I1, I2, and I3. */
2921 distribute_notes (i3notes, i3, i3, newi2pat ? i2 : NULL_RTX);
2923 distribute_notes (i2notes, i2, i3, newi2pat ? i2 : NULL_RTX);
2925 distribute_notes (i1notes, i1, i3, newi2pat ? i2 : NULL_RTX);
2927 distribute_notes (midnotes, NULL_RTX, i3, newi2pat ? i2 : NULL_RTX);
2929 /* Distribute any notes added to I2 or I3 by recog_for_combine. We
2930 know these are REG_UNUSED and want them to go to the desired insn,
2931 so we always pass it as i3. We have not counted the notes in
2932 reg_n_deaths yet, so we need to do so now. */
2934 if (newi2pat && new_i2_notes)
2936 for (temp = new_i2_notes; temp; temp = XEXP (temp, 1))
2937 if (REG_P (XEXP (temp, 0)))
2938 REG_N_DEATHS (REGNO (XEXP (temp, 0)))++;
2940 distribute_notes (new_i2_notes, i2, i2, NULL_RTX);
2945 for (temp = new_i3_notes; temp; temp = XEXP (temp, 1))
2946 if (REG_P (XEXP (temp, 0)))
2947 REG_N_DEATHS (REGNO (XEXP (temp, 0)))++;
2949 distribute_notes (new_i3_notes, i3, i3, NULL_RTX);
2952 /* If I3DEST was used in I3SRC, it really died in I3. We may need to
2953 put a REG_DEAD note for it somewhere. If NEWI2PAT exists and sets
2954 I3DEST, the death must be somewhere before I2, not I3. If we passed I3
2955 in that case, it might delete I2. Similarly for I2 and I1.
2956 Show an additional death due to the REG_DEAD note we make here. If
2957 we discard it in distribute_notes, we will decrement it again. */
2961 if (REG_P (i3dest_killed))
2962 REG_N_DEATHS (REGNO (i3dest_killed))++;
2964 if (newi2pat && reg_set_p (i3dest_killed, newi2pat))
2965 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i3dest_killed,
2967 NULL_RTX, i2, NULL_RTX);
2969 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i3dest_killed,
2971 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX);
2974 if (i2dest_in_i2src)
2977 REG_N_DEATHS (REGNO (i2dest))++;
2979 if (newi2pat && reg_set_p (i2dest, newi2pat))
2980 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i2dest, NULL_RTX),
2981 NULL_RTX, i2, NULL_RTX);
2983 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i2dest, NULL_RTX),
2984 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX);
2987 if (i1dest_in_i1src)
2990 REG_N_DEATHS (REGNO (i1dest))++;
2992 if (newi2pat && reg_set_p (i1dest, newi2pat))
2993 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i1dest, NULL_RTX),
2994 NULL_RTX, i2, NULL_RTX);
2996 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i1dest, NULL_RTX),
2997 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX);
3000 distribute_links (i3links);
3001 distribute_links (i2links);
3002 distribute_links (i1links);
3007 rtx i2_insn = 0, i2_val = 0, set;
3009 /* The insn that used to set this register doesn't exist, and
3010 this life of the register may not exist either. See if one of
3011 I3's links points to an insn that sets I2DEST. If it does,
3012 that is now the last known value for I2DEST. If we don't update
3013 this and I2 set the register to a value that depended on its old
3014 contents, we will get confused. If this insn is used, thing
3015 will be set correctly in combine_instructions. */
3017 for (link = LOG_LINKS (i3); link; link = XEXP (link, 1))
3018 if ((set = single_set (XEXP (link, 0))) != 0
3019 && rtx_equal_p (i2dest, SET_DEST (set)))
3020 i2_insn = XEXP (link, 0), i2_val = SET_SRC (set);
3022 record_value_for_reg (i2dest, i2_insn, i2_val);
3024 /* If the reg formerly set in I2 died only once and that was in I3,
3025 zero its use count so it won't make `reload' do any work. */
3027 && (newi2pat == 0 || ! reg_mentioned_p (i2dest, newi2pat))
3028 && ! i2dest_in_i2src)
3030 regno = REGNO (i2dest);
3031 REG_N_SETS (regno)--;
3035 if (i1 && REG_P (i1dest))
3038 rtx i1_insn = 0, i1_val = 0, set;
3040 for (link = LOG_LINKS (i3); link; link = XEXP (link, 1))
3041 if ((set = single_set (XEXP (link, 0))) != 0
3042 && rtx_equal_p (i1dest, SET_DEST (set)))
3043 i1_insn = XEXP (link, 0), i1_val = SET_SRC (set);
3045 record_value_for_reg (i1dest, i1_insn, i1_val);
3047 regno = REGNO (i1dest);
3048 if (! added_sets_1 && ! i1dest_in_i1src)
3049 REG_N_SETS (regno)--;
3052 /* Update reg_stat[].nonzero_bits et al for any changes that may have
3053 been made to this insn. The order of
3054 set_nonzero_bits_and_sign_copies() is important. Because newi2pat
3055 can affect nonzero_bits of newpat */
3057 note_stores (newi2pat, set_nonzero_bits_and_sign_copies, NULL);
3058 note_stores (newpat, set_nonzero_bits_and_sign_copies, NULL);
3060 /* Set new_direct_jump_p if a new return or simple jump instruction
3063 If I3 is now an unconditional jump, ensure that it has a
3064 BARRIER following it since it may have initially been a
3065 conditional jump. It may also be the last nonnote insn. */
3067 if (returnjump_p (i3) || any_uncondjump_p (i3))
3069 *new_direct_jump_p = 1;
3070 mark_jump_label (PATTERN (i3), i3, 0);
3072 if ((temp = next_nonnote_insn (i3)) == NULL_RTX
3073 || !BARRIER_P (temp))
3074 emit_barrier_after (i3);
3077 if (undobuf.other_insn != NULL_RTX
3078 && (returnjump_p (undobuf.other_insn)
3079 || any_uncondjump_p (undobuf.other_insn)))
3081 *new_direct_jump_p = 1;
3083 if ((temp = next_nonnote_insn (undobuf.other_insn)) == NULL_RTX
3084 || !BARRIER_P (temp))
3085 emit_barrier_after (undobuf.other_insn);
3088 /* An NOOP jump does not need barrier, but it does need cleaning up
3090 if (GET_CODE (newpat) == SET
3091 && SET_SRC (newpat) == pc_rtx
3092 && SET_DEST (newpat) == pc_rtx)
3093 *new_direct_jump_p = 1;
3096 combine_successes++;
3099 if (added_links_insn
3100 && (newi2pat == 0 || INSN_CUID (added_links_insn) < INSN_CUID (i2))
3101 && INSN_CUID (added_links_insn) < INSN_CUID (i3))
3102 return added_links_insn;
3104 return newi2pat ? i2 : i3;
3107 /* Undo all the modifications recorded in undobuf. */
3112 struct undo *undo, *next;
3114 for (undo = undobuf.undos; undo; undo = next)
3118 *undo->where.i = undo->old_contents.i;
3120 *undo->where.r = undo->old_contents.r;
3122 undo->next = undobuf.frees;
3123 undobuf.frees = undo;
3129 /* We've committed to accepting the changes we made. Move all
3130 of the undos to the free list. */
3135 struct undo *undo, *next;
3137 for (undo = undobuf.undos; undo; undo = next)
3140 undo->next = undobuf.frees;
3141 undobuf.frees = undo;
3147 /* Find the innermost point within the rtx at LOC, possibly LOC itself,
3148 where we have an arithmetic expression and return that point. LOC will
3151 try_combine will call this function to see if an insn can be split into
3155 find_split_point (rtx *loc, rtx insn)
3158 enum rtx_code code = GET_CODE (x);
3160 unsigned HOST_WIDE_INT len = 0;
3161 HOST_WIDE_INT pos = 0;
3163 rtx inner = NULL_RTX;
3165 /* First special-case some codes. */
3169 #ifdef INSN_SCHEDULING
3170 /* If we are making a paradoxical SUBREG invalid, it becomes a split
3172 if (MEM_P (SUBREG_REG (x)))
3175 return find_split_point (&SUBREG_REG (x), insn);
3179 /* If we have (mem (const ..)) or (mem (symbol_ref ...)), split it
3180 using LO_SUM and HIGH. */
3181 if (GET_CODE (XEXP (x, 0)) == CONST
3182 || GET_CODE (XEXP (x, 0)) == SYMBOL_REF)
3185 gen_rtx_LO_SUM (Pmode,
3186 gen_rtx_HIGH (Pmode, XEXP (x, 0)),
3188 return &XEXP (XEXP (x, 0), 0);
3192 /* If we have a PLUS whose second operand is a constant and the
3193 address is not valid, perhaps will can split it up using
3194 the machine-specific way to split large constants. We use
3195 the first pseudo-reg (one of the virtual regs) as a placeholder;
3196 it will not remain in the result. */
3197 if (GET_CODE (XEXP (x, 0)) == PLUS
3198 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3199 && ! memory_address_p (GET_MODE (x), XEXP (x, 0)))
3201 rtx reg = regno_reg_rtx[FIRST_PSEUDO_REGISTER];
3202 rtx seq = split_insns (gen_rtx_SET (VOIDmode, reg, XEXP (x, 0)),
3205 /* This should have produced two insns, each of which sets our
3206 placeholder. If the source of the second is a valid address,
3207 we can make put both sources together and make a split point
3211 && NEXT_INSN (seq) != NULL_RTX
3212 && NEXT_INSN (NEXT_INSN (seq)) == NULL_RTX
3213 && NONJUMP_INSN_P (seq)
3214 && GET_CODE (PATTERN (seq)) == SET
3215 && SET_DEST (PATTERN (seq)) == reg
3216 && ! reg_mentioned_p (reg,
3217 SET_SRC (PATTERN (seq)))
3218 && NONJUMP_INSN_P (NEXT_INSN (seq))
3219 && GET_CODE (PATTERN (NEXT_INSN (seq))) == SET
3220 && SET_DEST (PATTERN (NEXT_INSN (seq))) == reg
3221 && memory_address_p (GET_MODE (x),
3222 SET_SRC (PATTERN (NEXT_INSN (seq)))))
3224 rtx src1 = SET_SRC (PATTERN (seq));
3225 rtx src2 = SET_SRC (PATTERN (NEXT_INSN (seq)));
3227 /* Replace the placeholder in SRC2 with SRC1. If we can
3228 find where in SRC2 it was placed, that can become our
3229 split point and we can replace this address with SRC2.
3230 Just try two obvious places. */
3232 src2 = replace_rtx (src2, reg, src1);
3234 if (XEXP (src2, 0) == src1)
3235 split = &XEXP (src2, 0);
3236 else if (GET_RTX_FORMAT (GET_CODE (XEXP (src2, 0)))[0] == 'e'
3237 && XEXP (XEXP (src2, 0), 0) == src1)
3238 split = &XEXP (XEXP (src2, 0), 0);
3242 SUBST (XEXP (x, 0), src2);
3247 /* If that didn't work, perhaps the first operand is complex and
3248 needs to be computed separately, so make a split point there.
3249 This will occur on machines that just support REG + CONST
3250 and have a constant moved through some previous computation. */
3252 else if (!OBJECT_P (XEXP (XEXP (x, 0), 0))
3253 && ! (GET_CODE (XEXP (XEXP (x, 0), 0)) == SUBREG
3254 && OBJECT_P (SUBREG_REG (XEXP (XEXP (x, 0), 0)))))
3255 return &XEXP (XEXP (x, 0), 0);
3261 /* If SET_DEST is CC0 and SET_SRC is not an operand, a COMPARE, or a
3262 ZERO_EXTRACT, the most likely reason why this doesn't match is that
3263 we need to put the operand into a register. So split at that
3266 if (SET_DEST (x) == cc0_rtx
3267 && GET_CODE (SET_SRC (x)) != COMPARE
3268 && GET_CODE (SET_SRC (x)) != ZERO_EXTRACT
3269 && !OBJECT_P (SET_SRC (x))
3270 && ! (GET_CODE (SET_SRC (x)) == SUBREG
3271 && OBJECT_P (SUBREG_REG (SET_SRC (x)))))
3272 return &SET_SRC (x);
3275 /* See if we can split SET_SRC as it stands. */
3276 split = find_split_point (&SET_SRC (x), insn);
3277 if (split && split != &SET_SRC (x))
3280 /* See if we can split SET_DEST as it stands. */
3281 split = find_split_point (&SET_DEST (x), insn);
3282 if (split && split != &SET_DEST (x))
3285 /* See if this is a bitfield assignment with everything constant. If
3286 so, this is an IOR of an AND, so split it into that. */
3287 if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
3288 && (GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0)))
3289 <= HOST_BITS_PER_WIDE_INT)
3290 && GET_CODE (XEXP (SET_DEST (x), 1)) == CONST_INT
3291 && GET_CODE (XEXP (SET_DEST (x), 2)) == CONST_INT
3292 && GET_CODE (SET_SRC (x)) == CONST_INT
3293 && ((INTVAL (XEXP (SET_DEST (x), 1))
3294 + INTVAL (XEXP (SET_DEST (x), 2)))
3295 <= GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0))))
3296 && ! side_effects_p (XEXP (SET_DEST (x), 0)))
3298 HOST_WIDE_INT pos = INTVAL (XEXP (SET_DEST (x), 2));
3299 unsigned HOST_WIDE_INT len = INTVAL (XEXP (SET_DEST (x), 1));
3300 unsigned HOST_WIDE_INT src = INTVAL (SET_SRC (x));
3301 rtx dest = XEXP (SET_DEST (x), 0);
3302 enum machine_mode mode = GET_MODE (dest);
3303 unsigned HOST_WIDE_INT mask = ((HOST_WIDE_INT) 1 << len) - 1;
3305 if (BITS_BIG_ENDIAN)
3306 pos = GET_MODE_BITSIZE (mode) - len - pos;
3310 simplify_gen_binary (IOR, mode, dest, GEN_INT (src << pos)));
3313 rtx negmask = gen_int_mode (~(mask << pos), mode);
3315 simplify_gen_binary (IOR, mode,
3316 simplify_gen_binary (AND, mode,
3318 GEN_INT (src << pos)));
3321 SUBST (SET_DEST (x), dest);
3323 split = find_split_point (&SET_SRC (x), insn);
3324 if (split && split != &SET_SRC (x))
3328 /* Otherwise, see if this is an operation that we can split into two.
3329 If so, try to split that. */
3330 code = GET_CODE (SET_SRC (x));
3335 /* If we are AND'ing with a large constant that is only a single
3336 bit and the result is only being used in a context where we
3337 need to know if it is zero or nonzero, replace it with a bit
3338 extraction. This will avoid the large constant, which might
3339 have taken more than one insn to make. If the constant were
3340 not a valid argument to the AND but took only one insn to make,
3341 this is no worse, but if it took more than one insn, it will
3344 if (GET_CODE (XEXP (SET_SRC (x), 1)) == CONST_INT
3345 && REG_P (XEXP (SET_SRC (x), 0))
3346 && (pos = exact_log2 (INTVAL (XEXP (SET_SRC (x), 1)))) >= 7
3347 && REG_P (SET_DEST (x))
3348 && (split = find_single_use (SET_DEST (x), insn, (rtx*) 0)) != 0
3349 && (GET_CODE (*split) == EQ || GET_CODE (*split) == NE)
3350 && XEXP (*split, 0) == SET_DEST (x)
3351 && XEXP (*split, 1) == const0_rtx)
3353 rtx extraction = make_extraction (GET_MODE (SET_DEST (x)),
3354 XEXP (SET_SRC (x), 0),
3355 pos, NULL_RTX, 1, 1, 0, 0);
3356 if (extraction != 0)
3358 SUBST (SET_SRC (x), extraction);
3359 return find_split_point (loc, insn);
3365 /* If STORE_FLAG_VALUE is -1, this is (NE X 0) and only one bit of X
3366 is known to be on, this can be converted into a NEG of a shift. */
3367 if (STORE_FLAG_VALUE == -1 && XEXP (SET_SRC (x), 1) == const0_rtx
3368 && GET_MODE (SET_SRC (x)) == GET_MODE (XEXP (SET_SRC (x), 0))
3369 && 1 <= (pos = exact_log2
3370 (nonzero_bits (XEXP (SET_SRC (x), 0),
3371 GET_MODE (XEXP (SET_SRC (x), 0))))))
3373 enum machine_mode mode = GET_MODE (XEXP (SET_SRC (x), 0));
3377 gen_rtx_LSHIFTRT (mode,
3378 XEXP (SET_SRC (x), 0),
3381 split = find_split_point (&SET_SRC (x), insn);
3382 if (split && split != &SET_SRC (x))
3388 inner = XEXP (SET_SRC (x), 0);
3390 /* We can't optimize if either mode is a partial integer
3391 mode as we don't know how many bits are significant
3393 if (GET_MODE_CLASS (GET_MODE (inner)) == MODE_PARTIAL_INT
3394 || GET_MODE_CLASS (GET_MODE (SET_SRC (x))) == MODE_PARTIAL_INT)
3398 len = GET_MODE_BITSIZE (GET_MODE (inner));
3404 if (GET_CODE (XEXP (SET_SRC (x), 1)) == CONST_INT
3405 && GET_CODE (XEXP (SET_SRC (x), 2)) == CONST_INT)
3407 inner = XEXP (SET_SRC (x), 0);
3408 len = INTVAL (XEXP (SET_SRC (x), 1));
3409 pos = INTVAL (XEXP (SET_SRC (x), 2));
3411 if (BITS_BIG_ENDIAN)
3412 pos = GET_MODE_BITSIZE (GET_MODE (inner)) - len - pos;
3413 unsignedp = (code == ZERO_EXTRACT);
3421 if (len && pos >= 0 && pos + len <= GET_MODE_BITSIZE (GET_MODE (inner)))
3423 enum machine_mode mode = GET_MODE (SET_SRC (x));
3425 /* For unsigned, we have a choice of a shift followed by an
3426 AND or two shifts. Use two shifts for field sizes where the
3427 constant might be too large. We assume here that we can
3428 always at least get 8-bit constants in an AND insn, which is
3429 true for every current RISC. */
3431 if (unsignedp && len <= 8)
3436 (mode, gen_lowpart (mode, inner),
3438 GEN_INT (((HOST_WIDE_INT) 1 << len) - 1)));
3440 split = find_split_point (&SET_SRC (x), insn);
3441 if (split && split != &SET_SRC (x))
3448 (unsignedp ? LSHIFTRT : ASHIFTRT, mode,
3449 gen_rtx_ASHIFT (mode,
3450 gen_lowpart (mode, inner),
3451 GEN_INT (GET_MODE_BITSIZE (mode)
3453 GEN_INT (GET_MODE_BITSIZE (mode) - len)));
3455 split = find_split_point (&SET_SRC (x), insn);
3456 if (split && split != &SET_SRC (x))
3461 /* See if this is a simple operation with a constant as the second
3462 operand. It might be that this constant is out of range and hence
3463 could be used as a split point. */
3464 if (BINARY_P (SET_SRC (x))
3465 && CONSTANT_P (XEXP (SET_SRC (x), 1))
3466 && (OBJECT_P (XEXP (SET_SRC (x), 0))
3467 || (GET_CODE (XEXP (SET_SRC (x), 0)) == SUBREG
3468 && OBJECT_P (SUBREG_REG (XEXP (SET_SRC (x), 0))))))
3469 return &XEXP (SET_SRC (x), 1);
3471 /* Finally, see if this is a simple operation with its first operand
3472 not in a register. The operation might require this operand in a
3473 register, so return it as a split point. We can always do this
3474 because if the first operand were another operation, we would have
3475 already found it as a split point. */
3476 if ((BINARY_P (SET_SRC (x)) || UNARY_P (SET_SRC (x)))
3477 && ! register_operand (XEXP (SET_SRC (x), 0), VOIDmode))
3478 return &XEXP (SET_SRC (x), 0);
3484 /* We write NOR as (and (not A) (not B)), but if we don't have a NOR,
3485 it is better to write this as (not (ior A B)) so we can split it.
3486 Similarly for IOR. */
3487 if (GET_CODE (XEXP (x, 0)) == NOT && GET_CODE (XEXP (x, 1)) == NOT)
3490 gen_rtx_NOT (GET_MODE (x),
3491 gen_rtx_fmt_ee (code == IOR ? AND : IOR,
3493 XEXP (XEXP (x, 0), 0),
3494 XEXP (XEXP (x, 1), 0))));
3495 return find_split_point (loc, insn);
3498 /* Many RISC machines have a large set of logical insns. If the
3499 second operand is a NOT, put it first so we will try to split the
3500 other operand first. */
3501 if (GET_CODE (XEXP (x, 1)) == NOT)
3503 rtx tem = XEXP (x, 0);
3504 SUBST (XEXP (x, 0), XEXP (x, 1));
3505 SUBST (XEXP (x, 1), tem);
3513 /* Otherwise, select our actions depending on our rtx class. */
3514 switch (GET_RTX_CLASS (code))
3516 case RTX_BITFIELD_OPS: /* This is ZERO_EXTRACT and SIGN_EXTRACT. */
3518 split = find_split_point (&XEXP (x, 2), insn);
3521 /* ... fall through ... */
3523 case RTX_COMM_ARITH:
3525 case RTX_COMM_COMPARE:
3526 split = find_split_point (&XEXP (x, 1), insn);
3529 /* ... fall through ... */
3531 /* Some machines have (and (shift ...) ...) insns. If X is not
3532 an AND, but XEXP (X, 0) is, use it as our split point. */
3533 if (GET_CODE (x) != AND && GET_CODE (XEXP (x, 0)) == AND)
3534 return &XEXP (x, 0);
3536 split = find_split_point (&XEXP (x, 0), insn);
3542 /* Otherwise, we don't have a split point. */
3547 /* Throughout X, replace FROM with TO, and return the result.
3548 The result is TO if X is FROM;
3549 otherwise the result is X, but its contents may have been modified.
3550 If they were modified, a record was made in undobuf so that
3551 undo_all will (among other things) return X to its original state.
3553 If the number of changes necessary is too much to record to undo,
3554 the excess changes are not made, so the result is invalid.
3555 The changes already made can still be undone.
3556 undobuf.num_undo is incremented for such changes, so by testing that
3557 the caller can tell whether the result is valid.
3559 `n_occurrences' is incremented each time FROM is replaced.
3561 IN_DEST is nonzero if we are processing the SET_DEST of a SET.
3563 UNIQUE_COPY is nonzero if each substitution must be unique. We do this
3564 by copying if `n_occurrences' is nonzero. */
3567 subst (rtx x, rtx from, rtx to, int in_dest, int unique_copy)
3569 enum rtx_code code = GET_CODE (x);
3570 enum machine_mode op0_mode = VOIDmode;
3575 /* Two expressions are equal if they are identical copies of a shared
3576 RTX or if they are both registers with the same register number
3579 #define COMBINE_RTX_EQUAL_P(X,Y) \
3581 || (REG_P (X) && REG_P (Y) \
3582 && REGNO (X) == REGNO (Y) && GET_MODE (X) == GET_MODE (Y)))
3584 if (! in_dest && COMBINE_RTX_EQUAL_P (x, from))
3587 return (unique_copy && n_occurrences > 1 ? copy_rtx (to) : to);
3590 /* If X and FROM are the same register but different modes, they will
3591 not have been seen as equal above. However, flow.c will make a
3592 LOG_LINKS entry for that case. If we do nothing, we will try to
3593 rerecognize our original insn and, when it succeeds, we will
3594 delete the feeding insn, which is incorrect.
3596 So force this insn not to match in this (rare) case. */
3597 if (! in_dest && code == REG && REG_P (from)
3598 && REGNO (x) == REGNO (from))
3599 return gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
3601 /* If this is an object, we are done unless it is a MEM or LO_SUM, both
3602 of which may contain things that can be combined. */
3603 if (code != MEM && code != LO_SUM && OBJECT_P (x))
3606 /* It is possible to have a subexpression appear twice in the insn.
3607 Suppose that FROM is a register that appears within TO.
3608 Then, after that subexpression has been scanned once by `subst',
3609 the second time it is scanned, TO may be found. If we were
3610 to scan TO here, we would find FROM within it and create a
3611 self-referent rtl structure which is completely wrong. */
3612 if (COMBINE_RTX_EQUAL_P (x, to))
3615 /* Parallel asm_operands need special attention because all of the
3616 inputs are shared across the arms. Furthermore, unsharing the
3617 rtl results in recognition failures. Failure to handle this case
3618 specially can result in circular rtl.
3620 Solve this by doing a normal pass across the first entry of the
3621 parallel, and only processing the SET_DESTs of the subsequent
3624 if (code == PARALLEL
3625 && GET_CODE (XVECEXP (x, 0, 0)) == SET
3626 && GET_CODE (SET_SRC (XVECEXP (x, 0, 0))) == ASM_OPERANDS)
3628 new = subst (XVECEXP (x, 0, 0), from, to, 0, unique_copy);
3630 /* If this substitution failed, this whole thing fails. */
3631 if (GET_CODE (new) == CLOBBER
3632 && XEXP (new, 0) == const0_rtx)
3635 SUBST (XVECEXP (x, 0, 0), new);
3637 for (i = XVECLEN (x, 0) - 1; i >= 1; i--)
3639 rtx dest = SET_DEST (XVECEXP (x, 0, i));
3642 && GET_CODE (dest) != CC0
3643 && GET_CODE (dest) != PC)
3645 new = subst (dest, from, to, 0, unique_copy);
3647 /* If this substitution failed, this whole thing fails. */
3648 if (GET_CODE (new) == CLOBBER
3649 && XEXP (new, 0) == const0_rtx)
3652 SUBST (SET_DEST (XVECEXP (x, 0, i)), new);
3658 len = GET_RTX_LENGTH (code);
3659 fmt = GET_RTX_FORMAT (code);
3661 /* We don't need to process a SET_DEST that is a register, CC0,
3662 or PC, so set up to skip this common case. All other cases
3663 where we want to suppress replacing something inside a
3664 SET_SRC are handled via the IN_DEST operand. */
3666 && (REG_P (SET_DEST (x))
3667 || GET_CODE (SET_DEST (x)) == CC0
3668 || GET_CODE (SET_DEST (x)) == PC))
3671 /* Get the mode of operand 0 in case X is now a SIGN_EXTEND of a
3674 op0_mode = GET_MODE (XEXP (x, 0));
3676 for (i = 0; i < len; i++)
3681 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
3683 if (COMBINE_RTX_EQUAL_P (XVECEXP (x, i, j), from))
3685 new = (unique_copy && n_occurrences
3686 ? copy_rtx (to) : to);
3691 new = subst (XVECEXP (x, i, j), from, to, 0,
3694 /* If this substitution failed, this whole thing
3696 if (GET_CODE (new) == CLOBBER
3697 && XEXP (new, 0) == const0_rtx)
3701 SUBST (XVECEXP (x, i, j), new);
3704 else if (fmt[i] == 'e')
3706 /* If this is a register being set, ignore it. */
3710 && (((code == SUBREG || code == ZERO_EXTRACT)
3712 || code == STRICT_LOW_PART))
3715 else if (COMBINE_RTX_EQUAL_P (XEXP (x, i), from))
3717 /* In general, don't install a subreg involving two
3718 modes not tieable. It can worsen register
3719 allocation, and can even make invalid reload
3720 insns, since the reg inside may need to be copied
3721 from in the outside mode, and that may be invalid
3722 if it is an fp reg copied in integer mode.
3724 We allow two exceptions to this: It is valid if
3725 it is inside another SUBREG and the mode of that
3726 SUBREG and the mode of the inside of TO is
3727 tieable and it is valid if X is a SET that copies
3730 if (GET_CODE (to) == SUBREG
3731 && ! MODES_TIEABLE_P (GET_MODE (to),
3732 GET_MODE (SUBREG_REG (to)))
3733 && ! (code == SUBREG
3734 && MODES_TIEABLE_P (GET_MODE (x),
3735 GET_MODE (SUBREG_REG (to))))
3737 && ! (code == SET && i == 1 && XEXP (x, 0) == cc0_rtx)
3740 return gen_rtx_CLOBBER (VOIDmode, const0_rtx);
3742 #ifdef CANNOT_CHANGE_MODE_CLASS
3745 && REGNO (to) < FIRST_PSEUDO_REGISTER
3746 && REG_CANNOT_CHANGE_MODE_P (REGNO (to),
3749 return gen_rtx_CLOBBER (VOIDmode, const0_rtx);
3752 new = (unique_copy && n_occurrences ? copy_rtx (to) : to);
3756 /* If we are in a SET_DEST, suppress most cases unless we
3757 have gone inside a MEM, in which case we want to
3758 simplify the address. We assume here that things that
3759 are actually part of the destination have their inner
3760 parts in the first expression. This is true for SUBREG,
3761 STRICT_LOW_PART, and ZERO_EXTRACT, which are the only
3762 things aside from REG and MEM that should appear in a
3764 new = subst (XEXP (x, i), from, to,
3766 && (code == SUBREG || code == STRICT_LOW_PART
3767 || code == ZERO_EXTRACT))
3769 && i == 0), unique_copy);
3771 /* If we found that we will have to reject this combination,
3772 indicate that by returning the CLOBBER ourselves, rather than
3773 an expression containing it. This will speed things up as
3774 well as prevent accidents where two CLOBBERs are considered
3775 to be equal, thus producing an incorrect simplification. */
3777 if (GET_CODE (new) == CLOBBER && XEXP (new, 0) == const0_rtx)
3780 if (GET_CODE (x) == SUBREG
3781 && (GET_CODE (new) == CONST_INT
3782 || GET_CODE (new) == CONST_DOUBLE))
3784 enum machine_mode mode = GET_MODE (x);
3786 x = simplify_subreg (GET_MODE (x), new,
3787 GET_MODE (SUBREG_REG (x)),
3790 x = gen_rtx_CLOBBER (mode, const0_rtx);
3792 else if (GET_CODE (new) == CONST_INT
3793 && GET_CODE (x) == ZERO_EXTEND)
3795 x = simplify_unary_operation (ZERO_EXTEND, GET_MODE (x),
3796 new, GET_MODE (XEXP (x, 0)));
3800 SUBST (XEXP (x, i), new);
3805 /* Try to simplify X. If the simplification changed the code, it is likely
3806 that further simplification will help, so loop, but limit the number
3807 of repetitions that will be performed. */
3809 for (i = 0; i < 4; i++)
3811 /* If X is sufficiently simple, don't bother trying to do anything
3813 if (code != CONST_INT && code != REG && code != CLOBBER)
3814 x = combine_simplify_rtx (x, op0_mode, in_dest);
3816 if (GET_CODE (x) == code)
3819 code = GET_CODE (x);
3821 /* We no longer know the original mode of operand 0 since we
3822 have changed the form of X) */
3823 op0_mode = VOIDmode;
3829 /* Simplify X, a piece of RTL. We just operate on the expression at the
3830 outer level; call `subst' to simplify recursively. Return the new
3833 OP0_MODE is the original mode of XEXP (x, 0). IN_DEST is nonzero
3834 if we are inside a SET_DEST. */
3837 combine_simplify_rtx (rtx x, enum machine_mode op0_mode, int in_dest)
3839 enum rtx_code code = GET_CODE (x);
3840 enum machine_mode mode = GET_MODE (x);
3845 /* If this is a commutative operation, put a constant last and a complex
3846 expression first. We don't need to do this for comparisons here. */
3847 if (COMMUTATIVE_ARITH_P (x)
3848 && swap_commutative_operands_p (XEXP (x, 0), XEXP (x, 1)))
3851 SUBST (XEXP (x, 0), XEXP (x, 1));
3852 SUBST (XEXP (x, 1), temp);
3855 /* If this is a simple operation applied to an IF_THEN_ELSE, try
3856 applying it to the arms of the IF_THEN_ELSE. This often simplifies
3857 things. Check for cases where both arms are testing the same
3860 Don't do anything if all operands are very simple. */
3863 && ((!OBJECT_P (XEXP (x, 0))
3864 && ! (GET_CODE (XEXP (x, 0)) == SUBREG
3865 && OBJECT_P (SUBREG_REG (XEXP (x, 0)))))
3866 || (!OBJECT_P (XEXP (x, 1))
3867 && ! (GET_CODE (XEXP (x, 1)) == SUBREG
3868 && OBJECT_P (SUBREG_REG (XEXP (x, 1)))))))
3870 && (!OBJECT_P (XEXP (x, 0))
3871 && ! (GET_CODE (XEXP (x, 0)) == SUBREG
3872 && OBJECT_P (SUBREG_REG (XEXP (x, 0)))))))
3874 rtx cond, true_rtx, false_rtx;
3876 cond = if_then_else_cond (x, &true_rtx, &false_rtx);
3878 /* If everything is a comparison, what we have is highly unlikely
3879 to be simpler, so don't use it. */
3880 && ! (COMPARISON_P (x)
3881 && (COMPARISON_P (true_rtx) || COMPARISON_P (false_rtx))))
3883 rtx cop1 = const0_rtx;
3884 enum rtx_code cond_code = simplify_comparison (NE, &cond, &cop1);
3886 if (cond_code == NE && COMPARISON_P (cond))
3889 /* Simplify the alternative arms; this may collapse the true and
3890 false arms to store-flag values. Be careful to use copy_rtx
3891 here since true_rtx or false_rtx might share RTL with x as a
3892 result of the if_then_else_cond call above. */
3893 true_rtx = subst (copy_rtx (true_rtx), pc_rtx, pc_rtx, 0, 0);
3894 false_rtx = subst (copy_rtx (false_rtx), pc_rtx, pc_rtx, 0, 0);
3896 /* If true_rtx and false_rtx are not general_operands, an if_then_else
3897 is unlikely to be simpler. */
3898 if (general_operand (true_rtx, VOIDmode)
3899 && general_operand (false_rtx, VOIDmode))
3901 enum rtx_code reversed;
3903 /* Restarting if we generate a store-flag expression will cause
3904 us to loop. Just drop through in this case. */
3906 /* If the result values are STORE_FLAG_VALUE and zero, we can
3907 just make the comparison operation. */
3908 if (true_rtx == const_true_rtx && false_rtx == const0_rtx)
3909 x = simplify_gen_relational (cond_code, mode, VOIDmode,
3911 else if (true_rtx == const0_rtx && false_rtx == const_true_rtx
3912 && ((reversed = reversed_comparison_code_parts
3913 (cond_code, cond, cop1, NULL))
3915 x = simplify_gen_relational (reversed, mode, VOIDmode,
3918 /* Likewise, we can make the negate of a comparison operation
3919 if the result values are - STORE_FLAG_VALUE and zero. */
3920 else if (GET_CODE (true_rtx) == CONST_INT
3921 && INTVAL (true_rtx) == - STORE_FLAG_VALUE
3922 && false_rtx == const0_rtx)
3923 x = simplify_gen_unary (NEG, mode,
3924 simplify_gen_relational (cond_code,
3928 else if (GET_CODE (false_rtx) == CONST_INT
3929 && INTVAL (false_rtx) == - STORE_FLAG_VALUE
3930 && true_rtx == const0_rtx
3931 && ((reversed = reversed_comparison_code_parts
3932 (cond_code, cond, cop1, NULL))
3934 x = simplify_gen_unary (NEG, mode,
3935 simplify_gen_relational (reversed,
3940 return gen_rtx_IF_THEN_ELSE (mode,
3941 simplify_gen_relational (cond_code,
3946 true_rtx, false_rtx);
3948 code = GET_CODE (x);
3949 op0_mode = VOIDmode;
3954 /* Try to fold this expression in case we have constants that weren't
3957 switch (GET_RTX_CLASS (code))
3960 if (op0_mode == VOIDmode)
3961 op0_mode = GET_MODE (XEXP (x, 0));
3962 temp = simplify_unary_operation (code, mode, XEXP (x, 0), op0_mode);
3965 case RTX_COMM_COMPARE:
3967 enum machine_mode cmp_mode = GET_MODE (XEXP (x, 0));
3968 if (cmp_mode == VOIDmode)
3970 cmp_mode = GET_MODE (XEXP (x, 1));
3971 if (cmp_mode == VOIDmode)
3972 cmp_mode = op0_mode;
3974 temp = simplify_relational_operation (code, mode, cmp_mode,
3975 XEXP (x, 0), XEXP (x, 1));
3978 case RTX_COMM_ARITH:
3980 temp = simplify_binary_operation (code, mode, XEXP (x, 0), XEXP (x, 1));
3982 case RTX_BITFIELD_OPS:
3984 temp = simplify_ternary_operation (code, mode, op0_mode, XEXP (x, 0),
3985 XEXP (x, 1), XEXP (x, 2));
3994 code = GET_CODE (temp);
3995 op0_mode = VOIDmode;
3996 mode = GET_MODE (temp);
3999 /* First see if we can apply the inverse distributive law. */
4000 if (code == PLUS || code == MINUS
4001 || code == AND || code == IOR || code == XOR)
4003 x = apply_distributive_law (x);
4004 code = GET_CODE (x);
4005 op0_mode = VOIDmode;
4008 /* If CODE is an associative operation not otherwise handled, see if we
4009 can associate some operands. This can win if they are constants or
4010 if they are logically related (i.e. (a & b) & a). */
4011 if ((code == PLUS || code == MINUS || code == MULT || code == DIV
4012 || code == AND || code == IOR || code == XOR
4013 || code == SMAX || code == SMIN || code == UMAX || code == UMIN)
4014 && ((INTEGRAL_MODE_P (mode) && code != DIV)
4015 || (flag_unsafe_math_optimizations && FLOAT_MODE_P (mode))))
4017 if (GET_CODE (XEXP (x, 0)) == code)
4019 rtx other = XEXP (XEXP (x, 0), 0);
4020 rtx inner_op0 = XEXP (XEXP (x, 0), 1);
4021 rtx inner_op1 = XEXP (x, 1);
4024 /* Make sure we pass the constant operand if any as the second
4025 one if this is a commutative operation. */
4026 if (CONSTANT_P (inner_op0) && COMMUTATIVE_ARITH_P (x))
4028 rtx tem = inner_op0;
4029 inner_op0 = inner_op1;
4032 inner = simplify_binary_operation (code == MINUS ? PLUS
4033 : code == DIV ? MULT
4035 mode, inner_op0, inner_op1);
4037 /* For commutative operations, try the other pair if that one
4039 if (inner == 0 && COMMUTATIVE_ARITH_P (x))
4041 other = XEXP (XEXP (x, 0), 1);
4042 inner = simplify_binary_operation (code, mode,
4043 XEXP (XEXP (x, 0), 0),
4048 return simplify_gen_binary (code, mode, other, inner);
4052 /* A little bit of algebraic simplification here. */
4056 /* Ensure that our address has any ASHIFTs converted to MULT in case
4057 address-recognizing predicates are called later. */
4058 temp = make_compound_operation (XEXP (x, 0), MEM);
4059 SUBST (XEXP (x, 0), temp);
4063 if (op0_mode == VOIDmode)
4064 op0_mode = GET_MODE (SUBREG_REG (x));
4066 /* See if this can be moved to simplify_subreg. */
4067 if (CONSTANT_P (SUBREG_REG (x))
4068 && subreg_lowpart_offset (mode, op0_mode) == SUBREG_BYTE (x)
4069 /* Don't call gen_lowpart if the inner mode
4070 is VOIDmode and we cannot simplify it, as SUBREG without
4071 inner mode is invalid. */
4072 && (GET_MODE (SUBREG_REG (x)) != VOIDmode
4073 || gen_lowpart_common (mode, SUBREG_REG (x))))
4074 return gen_lowpart (mode, SUBREG_REG (x));
4076 if (GET_MODE_CLASS (GET_MODE (SUBREG_REG (x))) == MODE_CC)
4080 temp = simplify_subreg (mode, SUBREG_REG (x), op0_mode,
4086 /* Don't change the mode of the MEM if that would change the meaning
4088 if (MEM_P (SUBREG_REG (x))
4089 && (MEM_VOLATILE_P (SUBREG_REG (x))
4090 || mode_dependent_address_p (XEXP (SUBREG_REG (x), 0))))
4091 return gen_rtx_CLOBBER (mode, const0_rtx);
4093 /* Note that we cannot do any narrowing for non-constants since
4094 we might have been counting on using the fact that some bits were
4095 zero. We now do this in the SET. */
4100 if (GET_CODE (XEXP (x, 0)) == SUBREG
4101 && subreg_lowpart_p (XEXP (x, 0))
4102 && (GET_MODE_SIZE (GET_MODE (XEXP (x, 0)))
4103 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (x, 0)))))
4104 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == ASHIFT
4105 && XEXP (SUBREG_REG (XEXP (x, 0)), 0) == const1_rtx)
4107 enum machine_mode inner_mode = GET_MODE (SUBREG_REG (XEXP (x, 0)));
4109 x = gen_rtx_ROTATE (inner_mode,
4110 simplify_gen_unary (NOT, inner_mode, const1_rtx,
4112 XEXP (SUBREG_REG (XEXP (x, 0)), 1));
4113 return gen_lowpart (mode, x);
4116 /* Apply De Morgan's laws to reduce number of patterns for machines
4117 with negating logical insns (and-not, nand, etc.). If result has
4118 only one NOT, put it first, since that is how the patterns are
4121 if (GET_CODE (XEXP (x, 0)) == IOR || GET_CODE (XEXP (x, 0)) == AND)
4123 rtx in1 = XEXP (XEXP (x, 0), 0), in2 = XEXP (XEXP (x, 0), 1);
4124 enum machine_mode op_mode;
4126 op_mode = GET_MODE (in1);
4127 in1 = simplify_gen_unary (NOT, op_mode, in1, op_mode);
4129 op_mode = GET_MODE (in2);
4130 if (op_mode == VOIDmode)
4132 in2 = simplify_gen_unary (NOT, op_mode, in2, op_mode);
4134 if (GET_CODE (in2) == NOT && GET_CODE (in1) != NOT)
4137 in2 = in1; in1 = tem;
4140 return gen_rtx_fmt_ee (GET_CODE (XEXP (x, 0)) == IOR ? AND : IOR,
4146 /* (neg (xor A 1)) is (plus A -1) if A is known to be either 0 or 1. */
4147 if (GET_CODE (XEXP (x, 0)) == XOR
4148 && XEXP (XEXP (x, 0), 1) == const1_rtx
4149 && nonzero_bits (XEXP (XEXP (x, 0), 0), mode) == 1)
4150 return simplify_gen_binary (PLUS, mode, XEXP (XEXP (x, 0), 0),
4153 temp = expand_compound_operation (XEXP (x, 0));
4155 /* For C equal to the width of MODE minus 1, (neg (ashiftrt X C)) can be
4156 replaced by (lshiftrt X C). This will convert
4157 (neg (sign_extract X 1 Y)) to (zero_extract X 1 Y). */
4159 if (GET_CODE (temp) == ASHIFTRT
4160 && GET_CODE (XEXP (temp, 1)) == CONST_INT
4161 && INTVAL (XEXP (temp, 1)) == GET_MODE_BITSIZE (mode) - 1)
4162 return simplify_shift_const (temp, LSHIFTRT, mode, XEXP (temp, 0),
4163 INTVAL (XEXP (temp, 1)));
4165 /* If X has only a single bit that might be nonzero, say, bit I, convert
4166 (neg X) to (ashiftrt (ashift X C-I) C-I) where C is the bitsize of
4167 MODE minus 1. This will convert (neg (zero_extract X 1 Y)) to
4168 (sign_extract X 1 Y). But only do this if TEMP isn't a register
4169 or a SUBREG of one since we'd be making the expression more
4170 complex if it was just a register. */
4173 && ! (GET_CODE (temp) == SUBREG
4174 && REG_P (SUBREG_REG (temp)))
4175 && (i = exact_log2 (nonzero_bits (temp, mode))) >= 0)
4177 rtx temp1 = simplify_shift_const
4178 (NULL_RTX, ASHIFTRT, mode,
4179 simplify_shift_const (NULL_RTX, ASHIFT, mode, temp,
4180 GET_MODE_BITSIZE (mode) - 1 - i),
4181 GET_MODE_BITSIZE (mode) - 1 - i);
4183 /* If all we did was surround TEMP with the two shifts, we
4184 haven't improved anything, so don't use it. Otherwise,
4185 we are better off with TEMP1. */
4186 if (GET_CODE (temp1) != ASHIFTRT
4187 || GET_CODE (XEXP (temp1, 0)) != ASHIFT
4188 || XEXP (XEXP (temp1, 0), 0) != temp)
4194 /* We can't handle truncation to a partial integer mode here
4195 because we don't know the real bitsize of the partial
4197 if (GET_MODE_CLASS (mode) == MODE_PARTIAL_INT)
4200 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4201 && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode),
4202 GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))))
4204 force_to_mode (XEXP (x, 0), GET_MODE (XEXP (x, 0)),
4205 GET_MODE_MASK (mode), NULL_RTX, 0));
4207 /* (truncate:SI ({sign,zero}_extend:DI foo:SI)) == foo:SI. */
4208 if ((GET_CODE (XEXP (x, 0)) == SIGN_EXTEND
4209 || GET_CODE (XEXP (x, 0)) == ZERO_EXTEND)
4210 && GET_MODE (XEXP (XEXP (x, 0), 0)) == mode)
4211 return XEXP (XEXP (x, 0), 0);
4213 /* (truncate:SI (OP:DI ({sign,zero}_extend:DI foo:SI))) is
4214 (OP:SI foo:SI) if OP is NEG or ABS. */
4215 if ((GET_CODE (XEXP (x, 0)) == ABS
4216 || GET_CODE (XEXP (x, 0)) == NEG)
4217 && (GET_CODE (XEXP (XEXP (x, 0), 0)) == SIGN_EXTEND
4218 || GET_CODE (XEXP (XEXP (x, 0), 0)) == ZERO_EXTEND)
4219 && GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == mode)
4220 return simplify_gen_unary (GET_CODE (XEXP (x, 0)), mode,
4221 XEXP (XEXP (XEXP (x, 0), 0), 0), mode);
4223 /* (truncate:SI (subreg:DI (truncate:SI X) 0)) is
4225 if (GET_CODE (XEXP (x, 0)) == SUBREG
4226 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == TRUNCATE
4227 && subreg_lowpart_p (XEXP (x, 0)))
4228 return SUBREG_REG (XEXP (x, 0));
4230 /* If we know that the value is already truncated, we can
4231 replace the TRUNCATE with a SUBREG if TRULY_NOOP_TRUNCATION
4232 is nonzero for the corresponding modes. But don't do this
4233 for an (LSHIFTRT (MULT ...)) since this will cause problems
4234 with the umulXi3_highpart patterns. */
4235 if (TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode),
4236 GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))))
4237 && num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
4238 >= (unsigned int) (GET_MODE_BITSIZE (mode) + 1)
4239 && ! (GET_CODE (XEXP (x, 0)) == LSHIFTRT
4240 && GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT))
4241 return gen_lowpart (mode, XEXP (x, 0));
4243 /* A truncate of a comparison can be replaced with a subreg if
4244 STORE_FLAG_VALUE permits. This is like the previous test,
4245 but it works even if the comparison is done in a mode larger
4246 than HOST_BITS_PER_WIDE_INT. */
4247 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4248 && COMPARISON_P (XEXP (x, 0))
4249 && ((HOST_WIDE_INT) STORE_FLAG_VALUE & ~GET_MODE_MASK (mode)) == 0)
4250 return gen_lowpart (mode, XEXP (x, 0));
4252 /* Similarly, a truncate of a register whose value is a
4253 comparison can be replaced with a subreg if STORE_FLAG_VALUE
4255 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4256 && ((HOST_WIDE_INT) STORE_FLAG_VALUE & ~GET_MODE_MASK (mode)) == 0
4257 && (temp = get_last_value (XEXP (x, 0)))
4258 && COMPARISON_P (temp))
4259 return gen_lowpart (mode, XEXP (x, 0));
4263 case FLOAT_TRUNCATE:
4264 /* (float_truncate:SF (float_extend:DF foo:SF)) = foo:SF. */
4265 if (GET_CODE (XEXP (x, 0)) == FLOAT_EXTEND
4266 && GET_MODE (XEXP (XEXP (x, 0), 0)) == mode)
4267 return XEXP (XEXP (x, 0), 0);
4269 /* (float_truncate:SF (float_truncate:DF foo:XF))
4270 = (float_truncate:SF foo:XF).
4271 This may eliminate double rounding, so it is unsafe.
4273 (float_truncate:SF (float_extend:XF foo:DF))
4274 = (float_truncate:SF foo:DF).
4276 (float_truncate:DF (float_extend:XF foo:SF))
4277 = (float_extend:SF foo:DF). */
4278 if ((GET_CODE (XEXP (x, 0)) == FLOAT_TRUNCATE
4279 && flag_unsafe_math_optimizations)
4280 || GET_CODE (XEXP (x, 0)) == FLOAT_EXTEND)
4281 return simplify_gen_unary (GET_MODE_SIZE (GET_MODE (XEXP (XEXP (x, 0),
4283 > GET_MODE_SIZE (mode)
4284 ? FLOAT_TRUNCATE : FLOAT_EXTEND,
4286 XEXP (XEXP (x, 0), 0), mode);
4288 /* (float_truncate (float x)) is (float x) */
4289 if (GET_CODE (XEXP (x, 0)) == FLOAT
4290 && (flag_unsafe_math_optimizations
4291 || ((unsigned)significand_size (GET_MODE (XEXP (x, 0)))
4292 >= (GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (x, 0), 0)))
4293 - num_sign_bit_copies (XEXP (XEXP (x, 0), 0),
4294 GET_MODE (XEXP (XEXP (x, 0), 0)))))))
4295 return simplify_gen_unary (FLOAT, mode,
4296 XEXP (XEXP (x, 0), 0),
4297 GET_MODE (XEXP (XEXP (x, 0), 0)));
4299 /* (float_truncate:SF (OP:DF (float_extend:DF foo:sf))) is
4300 (OP:SF foo:SF) if OP is NEG or ABS. */
4301 if ((GET_CODE (XEXP (x, 0)) == ABS
4302 || GET_CODE (XEXP (x, 0)) == NEG)
4303 && GET_CODE (XEXP (XEXP (x, 0), 0)) == FLOAT_EXTEND
4304 && GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == mode)
4305 return simplify_gen_unary (GET_CODE (XEXP (x, 0)), mode,
4306 XEXP (XEXP (XEXP (x, 0), 0), 0), mode);
4308 /* (float_truncate:SF (subreg:DF (float_truncate:SF X) 0))
4309 is (float_truncate:SF x). */
4310 if (GET_CODE (XEXP (x, 0)) == SUBREG
4311 && subreg_lowpart_p (XEXP (x, 0))
4312 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == FLOAT_TRUNCATE)
4313 return SUBREG_REG (XEXP (x, 0));
4316 /* (float_extend (float_extend x)) is (float_extend x)
4318 (float_extend (float x)) is (float x) assuming that double
4319 rounding can't happen.
4321 if (GET_CODE (XEXP (x, 0)) == FLOAT_EXTEND
4322 || (GET_CODE (XEXP (x, 0)) == FLOAT
4323 && ((unsigned)significand_size (GET_MODE (XEXP (x, 0)))
4324 >= (GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (x, 0), 0)))
4325 - num_sign_bit_copies (XEXP (XEXP (x, 0), 0),
4326 GET_MODE (XEXP (XEXP (x, 0), 0)))))))
4327 return simplify_gen_unary (GET_CODE (XEXP (x, 0)), mode,
4328 XEXP (XEXP (x, 0), 0),
4329 GET_MODE (XEXP (XEXP (x, 0), 0)));
4334 /* Convert (compare FOO (const_int 0)) to FOO unless we aren't
4335 using cc0, in which case we want to leave it as a COMPARE
4336 so we can distinguish it from a register-register-copy. */
4337 if (XEXP (x, 1) == const0_rtx)
4340 /* x - 0 is the same as x unless x's mode has signed zeros and
4341 allows rounding towards -infinity. Under those conditions,
4343 if (!(HONOR_SIGNED_ZEROS (GET_MODE (XEXP (x, 0)))
4344 && HONOR_SIGN_DEPENDENT_ROUNDING (GET_MODE (XEXP (x, 0))))
4345 && XEXP (x, 1) == CONST0_RTX (GET_MODE (XEXP (x, 0))))
4351 /* (const (const X)) can become (const X). Do it this way rather than
4352 returning the inner CONST since CONST can be shared with a
4354 if (GET_CODE (XEXP (x, 0)) == CONST)
4355 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4360 /* Convert (lo_sum (high FOO) FOO) to FOO. This is necessary so we
4361 can add in an offset. find_split_point will split this address up
4362 again if it doesn't match. */
4363 if (GET_CODE (XEXP (x, 0)) == HIGH
4364 && rtx_equal_p (XEXP (XEXP (x, 0), 0), XEXP (x, 1)))
4370 /* Canonicalize (plus (mult (neg B) C) A) to (minus A (mult B C)).
4372 if (GET_CODE (XEXP (x, 0)) == MULT
4373 && GET_CODE (XEXP (XEXP (x, 0), 0)) == NEG)
4377 in1 = XEXP (XEXP (XEXP (x, 0), 0), 0);
4378 in2 = XEXP (XEXP (x, 0), 1);
4379 return simplify_gen_binary (MINUS, mode, XEXP (x, 1),
4380 simplify_gen_binary (MULT, mode,
4384 /* If we have (plus (plus (A const) B)), associate it so that CONST is
4385 outermost. That's because that's the way indexed addresses are
4386 supposed to appear. This code used to check many more cases, but
4387 they are now checked elsewhere. */
4388 if (GET_CODE (XEXP (x, 0)) == PLUS
4389 && CONSTANT_ADDRESS_P (XEXP (XEXP (x, 0), 1)))
4390 return simplify_gen_binary (PLUS, mode,
4391 simplify_gen_binary (PLUS, mode,
4392 XEXP (XEXP (x, 0), 0),
4394 XEXP (XEXP (x, 0), 1));
4396 /* (plus (xor (and <foo> (const_int pow2 - 1)) <c>) <-c>)
4397 when c is (const_int (pow2 + 1) / 2) is a sign extension of a
4398 bit-field and can be replaced by either a sign_extend or a
4399 sign_extract. The `and' may be a zero_extend and the two
4400 <c>, -<c> constants may be reversed. */
4401 if (GET_CODE (XEXP (x, 0)) == XOR
4402 && GET_CODE (XEXP (x, 1)) == CONST_INT
4403 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
4404 && INTVAL (XEXP (x, 1)) == -INTVAL (XEXP (XEXP (x, 0), 1))
4405 && ((i = exact_log2 (INTVAL (XEXP (XEXP (x, 0), 1)))) >= 0
4406 || (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0)
4407 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4408 && ((GET_CODE (XEXP (XEXP (x, 0), 0)) == AND
4409 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == CONST_INT
4410 && (INTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1))
4411 == ((HOST_WIDE_INT) 1 << (i + 1)) - 1))
4412 || (GET_CODE (XEXP (XEXP (x, 0), 0)) == ZERO_EXTEND
4413 && (GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)))
4414 == (unsigned int) i + 1))))
4415 return simplify_shift_const
4416 (NULL_RTX, ASHIFTRT, mode,
4417 simplify_shift_const (NULL_RTX, ASHIFT, mode,
4418 XEXP (XEXP (XEXP (x, 0), 0), 0),
4419 GET_MODE_BITSIZE (mode) - (i + 1)),
4420 GET_MODE_BITSIZE (mode) - (i + 1));
4422 /* (plus (comparison A B) C) can become (neg (rev-comp A B)) if
4423 C is 1 and STORE_FLAG_VALUE is -1 or if C is -1 and STORE_FLAG_VALUE
4424 is 1. This produces better code than the alternative immediately
4426 if (COMPARISON_P (XEXP (x, 0))
4427 && ((STORE_FLAG_VALUE == -1 && XEXP (x, 1) == const1_rtx)
4428 || (STORE_FLAG_VALUE == 1 && XEXP (x, 1) == constm1_rtx))
4429 && (reversed = reversed_comparison (XEXP (x, 0), mode)))
4431 simplify_gen_unary (NEG, mode, reversed, mode);
4433 /* If only the low-order bit of X is possibly nonzero, (plus x -1)
4434 can become (ashiftrt (ashift (xor x 1) C) C) where C is
4435 the bitsize of the mode - 1. This allows simplification of
4436 "a = (b & 8) == 0;" */
4437 if (XEXP (x, 1) == constm1_rtx
4438 && !REG_P (XEXP (x, 0))
4439 && ! (GET_CODE (XEXP (x, 0)) == SUBREG
4440 && REG_P (SUBREG_REG (XEXP (x, 0))))
4441 && nonzero_bits (XEXP (x, 0), mode) == 1)
4442 return simplify_shift_const (NULL_RTX, ASHIFTRT, mode,
4443 simplify_shift_const (NULL_RTX, ASHIFT, mode,
4444 gen_rtx_XOR (mode, XEXP (x, 0), const1_rtx),
4445 GET_MODE_BITSIZE (mode) - 1),
4446 GET_MODE_BITSIZE (mode) - 1);
4448 /* If we are adding two things that have no bits in common, convert
4449 the addition into an IOR. This will often be further simplified,
4450 for example in cases like ((a & 1) + (a & 2)), which can
4453 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4454 && (nonzero_bits (XEXP (x, 0), mode)
4455 & nonzero_bits (XEXP (x, 1), mode)) == 0)
4457 /* Try to simplify the expression further. */
4458 rtx tor = simplify_gen_binary (IOR, mode, XEXP (x, 0), XEXP (x, 1));
4459 temp = combine_simplify_rtx (tor, mode, in_dest);
4461 /* If we could, great. If not, do not go ahead with the IOR
4462 replacement, since PLUS appears in many special purpose
4463 address arithmetic instructions. */
4464 if (GET_CODE (temp) != CLOBBER && temp != tor)
4470 /* If STORE_FLAG_VALUE is 1, (minus 1 (comparison foo bar)) can be done
4471 by reversing the comparison code if valid. */
4472 if (STORE_FLAG_VALUE == 1
4473 && XEXP (x, 0) == const1_rtx
4474 && COMPARISON_P (XEXP (x, 1))
4475 && (reversed = reversed_comparison (XEXP (x, 1), mode)))
4478 /* (minus <foo> (and <foo> (const_int -pow2))) becomes
4479 (and <foo> (const_int pow2-1)) */
4480 if (GET_CODE (XEXP (x, 1)) == AND
4481 && GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT
4482 && exact_log2 (-INTVAL (XEXP (XEXP (x, 1), 1))) >= 0
4483 && rtx_equal_p (XEXP (XEXP (x, 1), 0), XEXP (x, 0)))
4484 return simplify_and_const_int (NULL_RTX, mode, XEXP (x, 0),
4485 -INTVAL (XEXP (XEXP (x, 1), 1)) - 1);
4487 /* Canonicalize (minus A (mult (neg B) C)) to (plus (mult B C) A).
4489 if (GET_CODE (XEXP (x, 1)) == MULT
4490 && GET_CODE (XEXP (XEXP (x, 1), 0)) == NEG)
4494 in1 = XEXP (XEXP (XEXP (x, 1), 0), 0);
4495 in2 = XEXP (XEXP (x, 1), 1);
4496 return simplify_gen_binary (PLUS, mode,
4497 simplify_gen_binary (MULT, mode,
4502 /* Canonicalize (minus (neg A) (mult B C)) to
4503 (minus (mult (neg B) C) A). */
4504 if (GET_CODE (XEXP (x, 1)) == MULT
4505 && GET_CODE (XEXP (x, 0)) == NEG)
4509 in1 = simplify_gen_unary (NEG, mode, XEXP (XEXP (x, 1), 0), mode);
4510 in2 = XEXP (XEXP (x, 1), 1);
4511 return simplify_gen_binary (MINUS, mode,
4512 simplify_gen_binary (MULT, mode,
4514 XEXP (XEXP (x, 0), 0));
4517 /* Canonicalize (minus A (plus B C)) to (minus (minus A B) C) for
4519 if (GET_CODE (XEXP (x, 1)) == PLUS && INTEGRAL_MODE_P (mode))
4520 return simplify_gen_binary (MINUS, mode,
4521 simplify_gen_binary (MINUS, mode,
4523 XEXP (XEXP (x, 1), 0)),
4524 XEXP (XEXP (x, 1), 1));
4528 /* If we have (mult (plus A B) C), apply the distributive law and then
4529 the inverse distributive law to see if things simplify. This
4530 occurs mostly in addresses, often when unrolling loops. */
4532 if (GET_CODE (XEXP (x, 0)) == PLUS)
4534 rtx result = distribute_and_simplify_rtx (x, 0);
4539 /* Try simplify a*(b/c) as (a*b)/c. */
4540 if (FLOAT_MODE_P (mode) && flag_unsafe_math_optimizations
4541 && GET_CODE (XEXP (x, 0)) == DIV)
4543 rtx tem = simplify_binary_operation (MULT, mode,
4544 XEXP (XEXP (x, 0), 0),
4547 return simplify_gen_binary (DIV, mode, tem, XEXP (XEXP (x, 0), 1));
4552 /* If this is a divide by a power of two, treat it as a shift if
4553 its first operand is a shift. */
4554 if (GET_CODE (XEXP (x, 1)) == CONST_INT
4555 && (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0
4556 && (GET_CODE (XEXP (x, 0)) == ASHIFT
4557 || GET_CODE (XEXP (x, 0)) == LSHIFTRT
4558 || GET_CODE (XEXP (x, 0)) == ASHIFTRT
4559 || GET_CODE (XEXP (x, 0)) == ROTATE
4560 || GET_CODE (XEXP (x, 0)) == ROTATERT))
4561 return simplify_shift_const (NULL_RTX, LSHIFTRT, mode, XEXP (x, 0), i);
4565 case GT: case GTU: case GE: case GEU:
4566 case LT: case LTU: case LE: case LEU:
4567 case UNEQ: case LTGT:
4568 case UNGT: case UNGE:
4569 case UNLT: case UNLE:
4570 case UNORDERED: case ORDERED:
4571 /* If the first operand is a condition code, we can't do anything
4573 if (GET_CODE (XEXP (x, 0)) == COMPARE
4574 || (GET_MODE_CLASS (GET_MODE (XEXP (x, 0))) != MODE_CC
4575 && ! CC0_P (XEXP (x, 0))))
4577 rtx op0 = XEXP (x, 0);
4578 rtx op1 = XEXP (x, 1);
4579 enum rtx_code new_code;
4581 if (GET_CODE (op0) == COMPARE)
4582 op1 = XEXP (op0, 1), op0 = XEXP (op0, 0);
4584 /* Simplify our comparison, if possible. */
4585 new_code = simplify_comparison (code, &op0, &op1);
4587 /* If STORE_FLAG_VALUE is 1, we can convert (ne x 0) to simply X
4588 if only the low-order bit is possibly nonzero in X (such as when
4589 X is a ZERO_EXTRACT of one bit). Similarly, we can convert EQ to
4590 (xor X 1) or (minus 1 X); we use the former. Finally, if X is
4591 known to be either 0 or -1, NE becomes a NEG and EQ becomes
4594 Remove any ZERO_EXTRACT we made when thinking this was a
4595 comparison. It may now be simpler to use, e.g., an AND. If a
4596 ZERO_EXTRACT is indeed appropriate, it will be placed back by
4597 the call to make_compound_operation in the SET case. */
4599 if (STORE_FLAG_VALUE == 1
4600 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4601 && op1 == const0_rtx
4602 && mode == GET_MODE (op0)
4603 && nonzero_bits (op0, mode) == 1)
4604 return gen_lowpart (mode,
4605 expand_compound_operation (op0));
4607 else if (STORE_FLAG_VALUE == 1
4608 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4609 && op1 == const0_rtx
4610 && mode == GET_MODE (op0)
4611 && (num_sign_bit_copies (op0, mode)
4612 == GET_MODE_BITSIZE (mode)))
4614 op0 = expand_compound_operation (op0);
4615 return simplify_gen_unary (NEG, mode,
4616 gen_lowpart (mode, op0),
4620 else if (STORE_FLAG_VALUE == 1
4621 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
4622 && op1 == const0_rtx
4623 && mode == GET_MODE (op0)
4624 && nonzero_bits (op0, mode) == 1)
4626 op0 = expand_compound_operation (op0);
4627 return simplify_gen_binary (XOR, mode,
4628 gen_lowpart (mode, op0),
4632 else if (STORE_FLAG_VALUE == 1
4633 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
4634 && op1 == const0_rtx
4635 && mode == GET_MODE (op0)
4636 && (num_sign_bit_copies (op0, mode)
4637 == GET_MODE_BITSIZE (mode)))
4639 op0 = expand_compound_operation (op0);
4640 return plus_constant (gen_lowpart (mode, op0), 1);
4643 /* If STORE_FLAG_VALUE is -1, we have cases similar to
4645 if (STORE_FLAG_VALUE == -1
4646 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4647 && op1 == const0_rtx
4648 && (num_sign_bit_copies (op0, mode)
4649 == GET_MODE_BITSIZE (mode)))
4650 return gen_lowpart (mode,
4651 expand_compound_operation (op0));
4653 else if (STORE_FLAG_VALUE == -1
4654 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4655 && op1 == const0_rtx
4656 && mode == GET_MODE (op0)
4657 && nonzero_bits (op0, mode) == 1)
4659 op0 = expand_compound_operation (op0);
4660 return simplify_gen_unary (NEG, mode,
4661 gen_lowpart (mode, op0),
4665 else if (STORE_FLAG_VALUE == -1
4666 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
4667 && op1 == const0_rtx
4668 && mode == GET_MODE (op0)
4669 && (num_sign_bit_copies (op0, mode)
4670 == GET_MODE_BITSIZE (mode)))
4672 op0 = expand_compound_operation (op0);
4673 return simplify_gen_unary (NOT, mode,
4674 gen_lowpart (mode, op0),
4678 /* If X is 0/1, (eq X 0) is X-1. */
4679 else if (STORE_FLAG_VALUE == -1
4680 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
4681 && op1 == const0_rtx
4682 && mode == GET_MODE (op0)
4683 && nonzero_bits (op0, mode) == 1)
4685 op0 = expand_compound_operation (op0);
4686 return plus_constant (gen_lowpart (mode, op0), -1);
4689 /* If STORE_FLAG_VALUE says to just test the sign bit and X has just
4690 one bit that might be nonzero, we can convert (ne x 0) to
4691 (ashift x c) where C puts the bit in the sign bit. Remove any
4692 AND with STORE_FLAG_VALUE when we are done, since we are only
4693 going to test the sign bit. */
4694 if (new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4695 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4696 && ((STORE_FLAG_VALUE & GET_MODE_MASK (mode))
4697 == (unsigned HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (mode) - 1))
4698 && op1 == const0_rtx
4699 && mode == GET_MODE (op0)
4700 && (i = exact_log2 (nonzero_bits (op0, mode))) >= 0)
4702 x = simplify_shift_const (NULL_RTX, ASHIFT, mode,
4703 expand_compound_operation (op0),
4704 GET_MODE_BITSIZE (mode) - 1 - i);
4705 if (GET_CODE (x) == AND && XEXP (x, 1) == const_true_rtx)
4711 /* If the code changed, return a whole new comparison. */
4712 if (new_code != code)
4713 return gen_rtx_fmt_ee (new_code, mode, op0, op1);
4715 /* Otherwise, keep this operation, but maybe change its operands.
4716 This also converts (ne (compare FOO BAR) 0) to (ne FOO BAR). */
4717 SUBST (XEXP (x, 0), op0);
4718 SUBST (XEXP (x, 1), op1);
4723 return simplify_if_then_else (x);
4729 /* If we are processing SET_DEST, we are done. */
4733 return expand_compound_operation (x);
4736 return simplify_set (x);
4741 return simplify_logical (x);
4744 /* (abs (neg <foo>)) -> (abs <foo>) */
4745 if (GET_CODE (XEXP (x, 0)) == NEG)
4746 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4748 /* If the mode of the operand is VOIDmode (i.e. if it is ASM_OPERANDS),
4750 if (GET_MODE (XEXP (x, 0)) == VOIDmode)
4753 /* If operand is something known to be positive, ignore the ABS. */
4754 if (GET_CODE (XEXP (x, 0)) == FFS || GET_CODE (XEXP (x, 0)) == ABS
4755 || ((GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
4756 <= HOST_BITS_PER_WIDE_INT)
4757 && ((nonzero_bits (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
4758 & ((HOST_WIDE_INT) 1
4759 << (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - 1)))
4763 /* If operand is known to be only -1 or 0, convert ABS to NEG. */
4764 if (num_sign_bit_copies (XEXP (x, 0), mode) == GET_MODE_BITSIZE (mode))
4765 return gen_rtx_NEG (mode, XEXP (x, 0));
4770 /* (ffs (*_extend <X>)) = (ffs <X>) */
4771 if (GET_CODE (XEXP (x, 0)) == SIGN_EXTEND
4772 || GET_CODE (XEXP (x, 0)) == ZERO_EXTEND)
4773 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4778 /* (pop* (zero_extend <X>)) = (pop* <X>) */
4779 if (GET_CODE (XEXP (x, 0)) == ZERO_EXTEND)
4780 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4784 /* (float (sign_extend <X>)) = (float <X>). */
4785 if (GET_CODE (XEXP (x, 0)) == SIGN_EXTEND)
4786 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4794 /* If this is a shift by a constant amount, simplify it. */
4795 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
4796 return simplify_shift_const (x, code, mode, XEXP (x, 0),
4797 INTVAL (XEXP (x, 1)));
4799 else if (SHIFT_COUNT_TRUNCATED && !REG_P (XEXP (x, 1)))
4801 force_to_mode (XEXP (x, 1), GET_MODE (XEXP (x, 1)),
4803 << exact_log2 (GET_MODE_BITSIZE (GET_MODE (x))))
4810 rtx op0 = XEXP (x, 0);
4811 rtx op1 = XEXP (x, 1);
4814 gcc_assert (GET_CODE (op1) == PARALLEL);
4815 len = XVECLEN (op1, 0);
4817 && GET_CODE (XVECEXP (op1, 0, 0)) == CONST_INT
4818 && GET_CODE (op0) == VEC_CONCAT)
4820 int offset = INTVAL (XVECEXP (op1, 0, 0)) * GET_MODE_SIZE (GET_MODE (x));
4822 /* Try to find the element in the VEC_CONCAT. */
4825 if (GET_MODE (op0) == GET_MODE (x))
4827 if (GET_CODE (op0) == VEC_CONCAT)
4829 HOST_WIDE_INT op0_size = GET_MODE_SIZE (GET_MODE (XEXP (op0, 0)));
4830 if (offset < op0_size)
4831 op0 = XEXP (op0, 0);
4835 op0 = XEXP (op0, 1);
4853 /* Simplify X, an IF_THEN_ELSE expression. Return the new expression. */
4856 simplify_if_then_else (rtx x)
4858 enum machine_mode mode = GET_MODE (x);
4859 rtx cond = XEXP (x, 0);
4860 rtx true_rtx = XEXP (x, 1);
4861 rtx false_rtx = XEXP (x, 2);
4862 enum rtx_code true_code = GET_CODE (cond);
4863 int comparison_p = COMPARISON_P (cond);
4866 enum rtx_code false_code;
4869 /* Simplify storing of the truth value. */
4870 if (comparison_p && true_rtx == const_true_rtx && false_rtx == const0_rtx)
4871 return simplify_gen_relational (true_code, mode, VOIDmode,
4872 XEXP (cond, 0), XEXP (cond, 1));
4874 /* Also when the truth value has to be reversed. */
4876 && true_rtx == const0_rtx && false_rtx == const_true_rtx
4877 && (reversed = reversed_comparison (cond, mode)))
4880 /* Sometimes we can simplify the arm of an IF_THEN_ELSE if a register used
4881 in it is being compared against certain values. Get the true and false
4882 comparisons and see if that says anything about the value of each arm. */
4885 && ((false_code = reversed_comparison_code (cond, NULL))
4887 && REG_P (XEXP (cond, 0)))
4890 rtx from = XEXP (cond, 0);
4891 rtx true_val = XEXP (cond, 1);
4892 rtx false_val = true_val;
4895 /* If FALSE_CODE is EQ, swap the codes and arms. */
4897 if (false_code == EQ)
4899 swapped = 1, true_code = EQ, false_code = NE;
4900 temp = true_rtx, true_rtx = false_rtx, false_rtx = temp;
4903 /* If we are comparing against zero and the expression being tested has
4904 only a single bit that might be nonzero, that is its value when it is
4905 not equal to zero. Similarly if it is known to be -1 or 0. */
4907 if (true_code == EQ && true_val == const0_rtx
4908 && exact_log2 (nzb = nonzero_bits (from, GET_MODE (from))) >= 0)
4909 false_code = EQ, false_val = GEN_INT (nzb);
4910 else if (true_code == EQ && true_val == const0_rtx
4911 && (num_sign_bit_copies (from, GET_MODE (from))
4912 == GET_MODE_BITSIZE (GET_MODE (from))))
4913 false_code = EQ, false_val = constm1_rtx;
4915 /* Now simplify an arm if we know the value of the register in the
4916 branch and it is used in the arm. Be careful due to the potential
4917 of locally-shared RTL. */
4919 if (reg_mentioned_p (from, true_rtx))
4920 true_rtx = subst (known_cond (copy_rtx (true_rtx), true_code,
4922 pc_rtx, pc_rtx, 0, 0);
4923 if (reg_mentioned_p (from, false_rtx))
4924 false_rtx = subst (known_cond (copy_rtx (false_rtx), false_code,
4926 pc_rtx, pc_rtx, 0, 0);
4928 SUBST (XEXP (x, 1), swapped ? false_rtx : true_rtx);
4929 SUBST (XEXP (x, 2), swapped ? true_rtx : false_rtx);
4931 true_rtx = XEXP (x, 1);
4932 false_rtx = XEXP (x, 2);
4933 true_code = GET_CODE (cond);
4936 /* If we have (if_then_else FOO (pc) (label_ref BAR)) and FOO can be
4937 reversed, do so to avoid needing two sets of patterns for
4938 subtract-and-branch insns. Similarly if we have a constant in the true
4939 arm, the false arm is the same as the first operand of the comparison, or
4940 the false arm is more complicated than the true arm. */
4943 && reversed_comparison_code (cond, NULL) != UNKNOWN
4944 && (true_rtx == pc_rtx
4945 || (CONSTANT_P (true_rtx)
4946 && GET_CODE (false_rtx) != CONST_INT && false_rtx != pc_rtx)
4947 || true_rtx == const0_rtx
4948 || (OBJECT_P (true_rtx) && !OBJECT_P (false_rtx))
4949 || (GET_CODE (true_rtx) == SUBREG && OBJECT_P (SUBREG_REG (true_rtx))
4950 && !OBJECT_P (false_rtx))
4951 || reg_mentioned_p (true_rtx, false_rtx)
4952 || rtx_equal_p (false_rtx, XEXP (cond, 0))))
4954 true_code = reversed_comparison_code (cond, NULL);
4955 SUBST (XEXP (x, 0), reversed_comparison (cond, GET_MODE (cond)));
4956 SUBST (XEXP (x, 1), false_rtx);
4957 SUBST (XEXP (x, 2), true_rtx);
4959 temp = true_rtx, true_rtx = false_rtx, false_rtx = temp;
4962 /* It is possible that the conditional has been simplified out. */
4963 true_code = GET_CODE (cond);
4964 comparison_p = COMPARISON_P (cond);
4967 /* If the two arms are identical, we don't need the comparison. */
4969 if (rtx_equal_p (true_rtx, false_rtx) && ! side_effects_p (cond))
4972 /* Convert a == b ? b : a to "a". */
4973 if (true_code == EQ && ! side_effects_p (cond)
4974 && !HONOR_NANS (mode)
4975 && rtx_equal_p (XEXP (cond, 0), false_rtx)
4976 && rtx_equal_p (XEXP (cond, 1), true_rtx))
4978 else if (true_code == NE && ! side_effects_p (cond)
4979 && !HONOR_NANS (mode)
4980 && rtx_equal_p (XEXP (cond, 0), true_rtx)
4981 && rtx_equal_p (XEXP (cond, 1), false_rtx))
4984 /* Look for cases where we have (abs x) or (neg (abs X)). */
4986 if (GET_MODE_CLASS (mode) == MODE_INT
4987 && GET_CODE (false_rtx) == NEG
4988 && rtx_equal_p (true_rtx, XEXP (false_rtx, 0))
4990 && rtx_equal_p (true_rtx, XEXP (cond, 0))
4991 && ! side_effects_p (true_rtx))
4996 return simplify_gen_unary (ABS, mode, true_rtx, mode);
5000 simplify_gen_unary (NEG, mode,
5001 simplify_gen_unary (ABS, mode, true_rtx, mode),
5007 /* Look for MIN or MAX. */
5009 if ((! FLOAT_MODE_P (mode) || flag_unsafe_math_optimizations)
5011 && rtx_equal_p (XEXP (cond, 0), true_rtx)
5012 && rtx_equal_p (XEXP (cond, 1), false_rtx)
5013 && ! side_effects_p (cond))
5018 return simplify_gen_binary (SMAX, mode, true_rtx, false_rtx);
5021 return simplify_gen_binary (SMIN, mode, true_rtx, false_rtx);
5024 return simplify_gen_binary (UMAX, mode, true_rtx, false_rtx);
5027 return simplify_gen_binary (UMIN, mode, true_rtx, false_rtx);
5032 /* If we have (if_then_else COND (OP Z C1) Z) and OP is an identity when its
5033 second operand is zero, this can be done as (OP Z (mult COND C2)) where
5034 C2 = C1 * STORE_FLAG_VALUE. Similarly if OP has an outer ZERO_EXTEND or
5035 SIGN_EXTEND as long as Z is already extended (so we don't destroy it).
5036 We can do this kind of thing in some cases when STORE_FLAG_VALUE is
5037 neither 1 or -1, but it isn't worth checking for. */
5039 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
5041 && GET_MODE_CLASS (mode) == MODE_INT
5042 && ! side_effects_p (x))
5044 rtx t = make_compound_operation (true_rtx, SET);
5045 rtx f = make_compound_operation (false_rtx, SET);
5046 rtx cond_op0 = XEXP (cond, 0);
5047 rtx cond_op1 = XEXP (cond, 1);
5048 enum rtx_code op = UNKNOWN, extend_op = UNKNOWN;
5049 enum machine_mode m = mode;
5050 rtx z = 0, c1 = NULL_RTX;
5052 if ((GET_CODE (t) == PLUS || GET_CODE (t) == MINUS
5053 || GET_CODE (t) == IOR || GET_CODE (t) == XOR
5054 || GET_CODE (t) == ASHIFT
5055 || GET_CODE (t) == LSHIFTRT || GET_CODE (t) == ASHIFTRT)
5056 && rtx_equal_p (XEXP (t, 0), f))
5057 c1 = XEXP (t, 1), op = GET_CODE (t), z = f;
5059 /* If an identity-zero op is commutative, check whether there
5060 would be a match if we swapped the operands. */
5061 else if ((GET_CODE (t) == PLUS || GET_CODE (t) == IOR
5062 || GET_CODE (t) == XOR)
5063 && rtx_equal_p (XEXP (t, 1), f))
5064 c1 = XEXP (t, 0), op = GET_CODE (t), z = f;
5065 else if (GET_CODE (t) == SIGN_EXTEND
5066 && (GET_CODE (XEXP (t, 0)) == PLUS
5067 || GET_CODE (XEXP (t, 0)) == MINUS
5068 || GET_CODE (XEXP (t, 0)) == IOR
5069 || GET_CODE (XEXP (t, 0)) == XOR
5070 || GET_CODE (XEXP (t, 0)) == ASHIFT
5071 || GET_CODE (XEXP (t, 0)) == LSHIFTRT
5072 || GET_CODE (XEXP (t, 0)) == ASHIFTRT)
5073 && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG
5074 && subreg_lowpart_p (XEXP (XEXP (t, 0), 0))
5075 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f)
5076 && (num_sign_bit_copies (f, GET_MODE (f))
5078 (GET_MODE_BITSIZE (mode)
5079 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t, 0), 0))))))
5081 c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0));
5082 extend_op = SIGN_EXTEND;
5083 m = GET_MODE (XEXP (t, 0));
5085 else if (GET_CODE (t) == SIGN_EXTEND
5086 && (GET_CODE (XEXP (t, 0)) == PLUS
5087 || GET_CODE (XEXP (t, 0)) == IOR
5088 || GET_CODE (XEXP (t, 0)) == XOR)
5089 && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG
5090 && subreg_lowpart_p (XEXP (XEXP (t, 0), 1))
5091 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f)
5092 && (num_sign_bit_copies (f, GET_MODE (f))
5094 (GET_MODE_BITSIZE (mode)
5095 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t, 0), 1))))))
5097 c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0));
5098 extend_op = SIGN_EXTEND;
5099 m = GET_MODE (XEXP (t, 0));
5101 else if (GET_CODE (t) == ZERO_EXTEND
5102 && (GET_CODE (XEXP (t, 0)) == PLUS
5103 || GET_CODE (XEXP (t, 0)) == MINUS
5104 || GET_CODE (XEXP (t, 0)) == IOR
5105 || GET_CODE (XEXP (t, 0)) == XOR
5106 || GET_CODE (XEXP (t, 0)) == ASHIFT
5107 || GET_CODE (XEXP (t, 0)) == LSHIFTRT
5108 || GET_CODE (XEXP (t, 0)) == ASHIFTRT)
5109 && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG
5110 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5111 && subreg_lowpart_p (XEXP (XEXP (t, 0), 0))
5112 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f)
5113 && ((nonzero_bits (f, GET_MODE (f))
5114 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t, 0), 0))))
5117 c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0));
5118 extend_op = ZERO_EXTEND;
5119 m = GET_MODE (XEXP (t, 0));
5121 else if (GET_CODE (t) == ZERO_EXTEND
5122 && (GET_CODE (XEXP (t, 0)) == PLUS
5123 || GET_CODE (XEXP (t, 0)) == IOR
5124 || GET_CODE (XEXP (t, 0)) == XOR)
5125 && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG
5126 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5127 && subreg_lowpart_p (XEXP (XEXP (t, 0), 1))
5128 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f)
5129 && ((nonzero_bits (f, GET_MODE (f))
5130 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t, 0), 1))))
5133 c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0));
5134 extend_op = ZERO_EXTEND;
5135 m = GET_MODE (XEXP (t, 0));
5140 temp = subst (simplify_gen_relational (true_code, m, VOIDmode,
5141 cond_op0, cond_op1),
5142 pc_rtx, pc_rtx, 0, 0);
5143 temp = simplify_gen_binary (MULT, m, temp,
5144 simplify_gen_binary (MULT, m, c1,
5146 temp = subst (temp, pc_rtx, pc_rtx, 0, 0);
5147 temp = simplify_gen_binary (op, m, gen_lowpart (m, z), temp);
5149 if (extend_op != UNKNOWN)
5150 temp = simplify_gen_unary (extend_op, mode, temp, m);
5156 /* If we have (if_then_else (ne A 0) C1 0) and either A is known to be 0 or
5157 1 and C1 is a single bit or A is known to be 0 or -1 and C1 is the
5158 negation of a single bit, we can convert this operation to a shift. We
5159 can actually do this more generally, but it doesn't seem worth it. */
5161 if (true_code == NE && XEXP (cond, 1) == const0_rtx
5162 && false_rtx == const0_rtx && GET_CODE (true_rtx) == CONST_INT
5163 && ((1 == nonzero_bits (XEXP (cond, 0), mode)
5164 && (i = exact_log2 (INTVAL (true_rtx))) >= 0)
5165 || ((num_sign_bit_copies (XEXP (cond, 0), mode)
5166 == GET_MODE_BITSIZE (mode))
5167 && (i = exact_log2 (-INTVAL (true_rtx))) >= 0)))
5169 simplify_shift_const (NULL_RTX, ASHIFT, mode,
5170 gen_lowpart (mode, XEXP (cond, 0)), i);
5172 /* (IF_THEN_ELSE (NE REG 0) (0) (8)) is REG for nonzero_bits (REG) == 8. */
5173 if (true_code == NE && XEXP (cond, 1) == const0_rtx
5174 && false_rtx == const0_rtx && GET_CODE (true_rtx) == CONST_INT
5175 && GET_MODE (XEXP (cond, 0)) == mode
5176 && (INTVAL (true_rtx) & GET_MODE_MASK (mode))
5177 == nonzero_bits (XEXP (cond, 0), mode)
5178 && (i = exact_log2 (INTVAL (true_rtx) & GET_MODE_MASK (mode))) >= 0)
5179 return XEXP (cond, 0);
5184 /* Simplify X, a SET expression. Return the new expression. */
5187 simplify_set (rtx x)
5189 rtx src = SET_SRC (x);
5190 rtx dest = SET_DEST (x);
5191 enum machine_mode mode
5192 = GET_MODE (src) != VOIDmode ? GET_MODE (src) : GET_MODE (dest);
5196 /* (set (pc) (return)) gets written as (return). */
5197 if (GET_CODE (dest) == PC && GET_CODE (src) == RETURN)
5200 /* Now that we know for sure which bits of SRC we are using, see if we can
5201 simplify the expression for the object knowing that we only need the
5204 if (GET_MODE_CLASS (mode) == MODE_INT
5205 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
5207 src = force_to_mode (src, mode, ~(HOST_WIDE_INT) 0, NULL_RTX, 0);
5208 SUBST (SET_SRC (x), src);
5211 /* If we are setting CC0 or if the source is a COMPARE, look for the use of
5212 the comparison result and try to simplify it unless we already have used
5213 undobuf.other_insn. */
5214 if ((GET_MODE_CLASS (mode) == MODE_CC
5215 || GET_CODE (src) == COMPARE
5217 && (cc_use = find_single_use (dest, subst_insn, &other_insn)) != 0
5218 && (undobuf.other_insn == 0 || other_insn == undobuf.other_insn)
5219 && COMPARISON_P (*cc_use)
5220 && rtx_equal_p (XEXP (*cc_use, 0), dest))
5222 enum rtx_code old_code = GET_CODE (*cc_use);
5223 enum rtx_code new_code;
5225 int other_changed = 0;
5226 enum machine_mode compare_mode = GET_MODE (dest);
5228 if (GET_CODE (src) == COMPARE)
5229 op0 = XEXP (src, 0), op1 = XEXP (src, 1);
5231 op0 = src, op1 = CONST0_RTX (GET_MODE (src));
5233 tmp = simplify_relational_operation (old_code, compare_mode, VOIDmode,
5236 new_code = old_code;
5237 else if (!CONSTANT_P (tmp))
5239 new_code = GET_CODE (tmp);
5240 op0 = XEXP (tmp, 0);
5241 op1 = XEXP (tmp, 1);
5245 rtx pat = PATTERN (other_insn);
5246 undobuf.other_insn = other_insn;
5247 SUBST (*cc_use, tmp);
5249 /* Attempt to simplify CC user. */
5250 if (GET_CODE (pat) == SET)
5252 rtx new = simplify_rtx (SET_SRC (pat));
5253 if (new != NULL_RTX)
5254 SUBST (SET_SRC (pat), new);
5257 /* Convert X into a no-op move. */
5258 SUBST (SET_DEST (x), pc_rtx);
5259 SUBST (SET_SRC (x), pc_rtx);
5263 /* Simplify our comparison, if possible. */
5264 new_code = simplify_comparison (new_code, &op0, &op1);
5266 #ifdef SELECT_CC_MODE
5267 /* If this machine has CC modes other than CCmode, check to see if we
5268 need to use a different CC mode here. */
5269 if (GET_MODE_CLASS (GET_MODE (op0)) == MODE_CC)
5270 compare_mode = GET_MODE (op0);
5272 compare_mode = SELECT_CC_MODE (new_code, op0, op1);
5275 /* If the mode changed, we have to change SET_DEST, the mode in the
5276 compare, and the mode in the place SET_DEST is used. If SET_DEST is
5277 a hard register, just build new versions with the proper mode. If it
5278 is a pseudo, we lose unless it is only time we set the pseudo, in
5279 which case we can safely change its mode. */
5280 if (compare_mode != GET_MODE (dest))
5282 unsigned int regno = REGNO (dest);
5283 rtx new_dest = gen_rtx_REG (compare_mode, regno);
5285 if (regno < FIRST_PSEUDO_REGISTER
5286 || (REG_N_SETS (regno) == 1 && ! REG_USERVAR_P (dest)))
5288 if (regno >= FIRST_PSEUDO_REGISTER)
5289 SUBST (regno_reg_rtx[regno], new_dest);
5291 SUBST (SET_DEST (x), new_dest);
5292 SUBST (XEXP (*cc_use, 0), new_dest);
5299 #endif /* SELECT_CC_MODE */
5301 /* If the code changed, we have to build a new comparison in
5302 undobuf.other_insn. */
5303 if (new_code != old_code)
5305 int other_changed_previously = other_changed;
5306 unsigned HOST_WIDE_INT mask;
5308 SUBST (*cc_use, gen_rtx_fmt_ee (new_code, GET_MODE (*cc_use),
5312 /* If the only change we made was to change an EQ into an NE or
5313 vice versa, OP0 has only one bit that might be nonzero, and OP1
5314 is zero, check if changing the user of the condition code will
5315 produce a valid insn. If it won't, we can keep the original code
5316 in that insn by surrounding our operation with an XOR. */
5318 if (((old_code == NE && new_code == EQ)
5319 || (old_code == EQ && new_code == NE))
5320 && ! other_changed_previously && op1 == const0_rtx
5321 && GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
5322 && exact_log2 (mask = nonzero_bits (op0, GET_MODE (op0))) >= 0)
5324 rtx pat = PATTERN (other_insn), note = 0;
5326 if ((recog_for_combine (&pat, other_insn, ¬e) < 0
5327 && ! check_asm_operands (pat)))
5329 PUT_CODE (*cc_use, old_code);
5332 op0 = simplify_gen_binary (XOR, GET_MODE (op0),
5333 op0, GEN_INT (mask));
5339 undobuf.other_insn = other_insn;
5342 /* If we are now comparing against zero, change our source if
5343 needed. If we do not use cc0, we always have a COMPARE. */
5344 if (op1 == const0_rtx && dest == cc0_rtx)
5346 SUBST (SET_SRC (x), op0);
5352 /* Otherwise, if we didn't previously have a COMPARE in the
5353 correct mode, we need one. */
5354 if (GET_CODE (src) != COMPARE || GET_MODE (src) != compare_mode)
5356 SUBST (SET_SRC (x), gen_rtx_COMPARE (compare_mode, op0, op1));
5359 else if (GET_MODE (op0) == compare_mode && op1 == const0_rtx)
5361 SUBST(SET_SRC (x), op0);
5366 /* Otherwise, update the COMPARE if needed. */
5367 SUBST (XEXP (src, 0), op0);
5368 SUBST (XEXP (src, 1), op1);
5373 /* Get SET_SRC in a form where we have placed back any
5374 compound expressions. Then do the checks below. */
5375 src = make_compound_operation (src, SET);
5376 SUBST (SET_SRC (x), src);
5379 /* If we have (set x (subreg:m1 (op:m2 ...) 0)) with OP being some operation,
5380 and X being a REG or (subreg (reg)), we may be able to convert this to
5381 (set (subreg:m2 x) (op)).
5383 We can always do this if M1 is narrower than M2 because that means that
5384 we only care about the low bits of the result.
5386 However, on machines without WORD_REGISTER_OPERATIONS defined, we cannot
5387 perform a narrower operation than requested since the high-order bits will
5388 be undefined. On machine where it is defined, this transformation is safe
5389 as long as M1 and M2 have the same number of words. */
5391 if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src)
5392 && !OBJECT_P (SUBREG_REG (src))
5393 && (((GET_MODE_SIZE (GET_MODE (src)) + (UNITS_PER_WORD - 1))
5395 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (src)))
5396 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD))
5397 #ifndef WORD_REGISTER_OPERATIONS
5398 && (GET_MODE_SIZE (GET_MODE (src))
5399 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (src))))
5401 #ifdef CANNOT_CHANGE_MODE_CLASS
5402 && ! (REG_P (dest) && REGNO (dest) < FIRST_PSEUDO_REGISTER
5403 && REG_CANNOT_CHANGE_MODE_P (REGNO (dest),
5404 GET_MODE (SUBREG_REG (src)),
5408 || (GET_CODE (dest) == SUBREG
5409 && REG_P (SUBREG_REG (dest)))))
5411 SUBST (SET_DEST (x),
5412 gen_lowpart (GET_MODE (SUBREG_REG (src)),
5414 SUBST (SET_SRC (x), SUBREG_REG (src));
5416 src = SET_SRC (x), dest = SET_DEST (x);
5420 /* If we have (set (cc0) (subreg ...)), we try to remove the subreg
5423 && GET_CODE (src) == SUBREG
5424 && subreg_lowpart_p (src)
5425 && (GET_MODE_BITSIZE (GET_MODE (src))
5426 < GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (src)))))
5428 rtx inner = SUBREG_REG (src);
5429 enum machine_mode inner_mode = GET_MODE (inner);
5431 /* Here we make sure that we don't have a sign bit on. */
5432 if (GET_MODE_BITSIZE (inner_mode) <= HOST_BITS_PER_WIDE_INT
5433 && (nonzero_bits (inner, inner_mode)
5434 < ((unsigned HOST_WIDE_INT) 1
5435 << (GET_MODE_BITSIZE (GET_MODE (src)) - 1))))
5437 SUBST (SET_SRC (x), inner);
5443 #ifdef LOAD_EXTEND_OP
5444 /* If we have (set FOO (subreg:M (mem:N BAR) 0)) with M wider than N, this
5445 would require a paradoxical subreg. Replace the subreg with a
5446 zero_extend to avoid the reload that would otherwise be required. */
5448 if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src)
5449 && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src))) != UNKNOWN
5450 && SUBREG_BYTE (src) == 0
5451 && (GET_MODE_SIZE (GET_MODE (src))
5452 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (src))))
5453 && MEM_P (SUBREG_REG (src)))
5456 gen_rtx_fmt_e (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src))),
5457 GET_MODE (src), SUBREG_REG (src)));
5463 /* If we don't have a conditional move, SET_SRC is an IF_THEN_ELSE, and we
5464 are comparing an item known to be 0 or -1 against 0, use a logical
5465 operation instead. Check for one of the arms being an IOR of the other
5466 arm with some value. We compute three terms to be IOR'ed together. In
5467 practice, at most two will be nonzero. Then we do the IOR's. */
5469 if (GET_CODE (dest) != PC
5470 && GET_CODE (src) == IF_THEN_ELSE
5471 && GET_MODE_CLASS (GET_MODE (src)) == MODE_INT
5472 && (GET_CODE (XEXP (src, 0)) == EQ || GET_CODE (XEXP (src, 0)) == NE)
5473 && XEXP (XEXP (src, 0), 1) == const0_rtx
5474 && GET_MODE (src) == GET_MODE (XEXP (XEXP (src, 0), 0))
5475 #ifdef HAVE_conditional_move
5476 && ! can_conditionally_move_p (GET_MODE (src))
5478 && (num_sign_bit_copies (XEXP (XEXP (src, 0), 0),
5479 GET_MODE (XEXP (XEXP (src, 0), 0)))
5480 == GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (src, 0), 0))))
5481 && ! side_effects_p (src))
5483 rtx true_rtx = (GET_CODE (XEXP (src, 0)) == NE
5484 ? XEXP (src, 1) : XEXP (src, 2));
5485 rtx false_rtx = (GET_CODE (XEXP (src, 0)) == NE
5486 ? XEXP (src, 2) : XEXP (src, 1));
5487 rtx term1 = const0_rtx, term2, term3;
5489 if (GET_CODE (true_rtx) == IOR
5490 && rtx_equal_p (XEXP (true_rtx, 0), false_rtx))
5491 term1 = false_rtx, true_rtx = XEXP (true_rtx, 1), false_rtx = const0_rtx;
5492 else if (GET_CODE (true_rtx) == IOR
5493 && rtx_equal_p (XEXP (true_rtx, 1), false_rtx))
5494 term1 = false_rtx, true_rtx = XEXP (true_rtx, 0), false_rtx = const0_rtx;
5495 else if (GET_CODE (false_rtx) == IOR
5496 && rtx_equal_p (XEXP (false_rtx, 0), true_rtx))
5497 term1 = true_rtx, false_rtx = XEXP (false_rtx, 1), true_rtx = const0_rtx;
5498 else if (GET_CODE (false_rtx) == IOR
5499 && rtx_equal_p (XEXP (false_rtx, 1), true_rtx))
5500 term1 = true_rtx, false_rtx = XEXP (false_rtx, 0), true_rtx = const0_rtx;
5502 term2 = simplify_gen_binary (AND, GET_MODE (src),
5503 XEXP (XEXP (src, 0), 0), true_rtx);
5504 term3 = simplify_gen_binary (AND, GET_MODE (src),
5505 simplify_gen_unary (NOT, GET_MODE (src),
5506 XEXP (XEXP (src, 0), 0),
5511 simplify_gen_binary (IOR, GET_MODE (src),
5512 simplify_gen_binary (IOR, GET_MODE (src),
5519 /* If either SRC or DEST is a CLOBBER of (const_int 0), make this
5520 whole thing fail. */
5521 if (GET_CODE (src) == CLOBBER && XEXP (src, 0) == const0_rtx)
5523 else if (GET_CODE (dest) == CLOBBER && XEXP (dest, 0) == const0_rtx)
5526 /* Convert this into a field assignment operation, if possible. */
5527 return make_field_assignment (x);
5530 /* Simplify, X, and AND, IOR, or XOR operation, and return the simplified
5534 simplify_logical (rtx x)
5536 enum machine_mode mode = GET_MODE (x);
5537 rtx op0 = XEXP (x, 0);
5538 rtx op1 = XEXP (x, 1);
5541 switch (GET_CODE (x))
5544 /* Convert (A ^ B) & A to A & (~B) since the latter is often a single
5545 insn (and may simplify more). */
5546 if (GET_CODE (op0) == XOR
5547 && rtx_equal_p (XEXP (op0, 0), op1)
5548 && ! side_effects_p (op1))
5549 x = simplify_gen_binary (AND, mode,
5550 simplify_gen_unary (NOT, mode,
5551 XEXP (op0, 1), mode),
5554 if (GET_CODE (op0) == XOR
5555 && rtx_equal_p (XEXP (op0, 1), op1)
5556 && ! side_effects_p (op1))
5557 x = simplify_gen_binary (AND, mode,
5558 simplify_gen_unary (NOT, mode,
5559 XEXP (op0, 0), mode),
5562 /* Similarly for (~(A ^ B)) & A. */
5563 if (GET_CODE (op0) == NOT
5564 && GET_CODE (XEXP (op0, 0)) == XOR
5565 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), op1)
5566 && ! side_effects_p (op1))
5567 x = simplify_gen_binary (AND, mode, XEXP (XEXP (op0, 0), 1), op1);
5569 if (GET_CODE (op0) == NOT
5570 && GET_CODE (XEXP (op0, 0)) == XOR
5571 && rtx_equal_p (XEXP (XEXP (op0, 0), 1), op1)
5572 && ! side_effects_p (op1))
5573 x = simplify_gen_binary (AND, mode, XEXP (XEXP (op0, 0), 0), op1);
5575 /* We can call simplify_and_const_int only if we don't lose
5576 any (sign) bits when converting INTVAL (op1) to
5577 "unsigned HOST_WIDE_INT". */
5578 if (GET_CODE (op1) == CONST_INT
5579 && (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5580 || INTVAL (op1) > 0))
5582 x = simplify_and_const_int (x, mode, op0, INTVAL (op1));
5584 /* If we have (ior (and (X C1) C2)) and the next restart would be
5585 the last, simplify this by making C1 as small as possible
5586 and then exit. Only do this if C1 actually changes: for now
5587 this only saves memory but, should this transformation be
5588 moved to simplify-rtx.c, we'd risk unbounded recursion there. */
5589 if (GET_CODE (x) == IOR && GET_CODE (op0) == AND
5590 && GET_CODE (XEXP (op0, 1)) == CONST_INT
5591 && GET_CODE (op1) == CONST_INT
5592 && (INTVAL (XEXP (op0, 1)) & INTVAL (op1)) != 0)
5593 return simplify_gen_binary (IOR, mode,
5595 (AND, mode, XEXP (op0, 0),
5596 GEN_INT (INTVAL (XEXP (op0, 1))
5597 & ~INTVAL (op1))), op1);
5599 if (GET_CODE (x) != AND)
5606 /* Convert (A | B) & A to A. */
5607 if (GET_CODE (op0) == IOR
5608 && (rtx_equal_p (XEXP (op0, 0), op1)
5609 || rtx_equal_p (XEXP (op0, 1), op1))
5610 && ! side_effects_p (XEXP (op0, 0))
5611 && ! side_effects_p (XEXP (op0, 1)))
5614 /* If we have any of (and (ior A B) C) or (and (xor A B) C),
5615 apply the distributive law and then the inverse distributive
5616 law to see if things simplify. */
5617 if (GET_CODE (op0) == IOR || GET_CODE (op0) == XOR)
5619 rtx result = distribute_and_simplify_rtx (x, 0);
5623 if (GET_CODE (op1) == IOR || GET_CODE (op1) == XOR)
5625 rtx result = distribute_and_simplify_rtx (x, 1);
5632 /* (ior A C) is C if all bits of A that might be nonzero are on in C. */
5633 if (GET_CODE (op1) == CONST_INT
5634 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5635 && (nonzero_bits (op0, mode) & ~INTVAL (op1)) == 0)
5638 /* Convert (A & B) | A to A. */
5639 if (GET_CODE (op0) == AND
5640 && (rtx_equal_p (XEXP (op0, 0), op1)
5641 || rtx_equal_p (XEXP (op0, 1), op1))
5642 && ! side_effects_p (XEXP (op0, 0))
5643 && ! side_effects_p (XEXP (op0, 1)))
5646 /* If we have (ior (and A B) C), apply the distributive law and then
5647 the inverse distributive law to see if things simplify. */
5649 if (GET_CODE (op0) == AND)
5651 rtx result = distribute_and_simplify_rtx (x, 0);
5656 if (GET_CODE (op1) == AND)
5658 rtx result = distribute_and_simplify_rtx (x, 1);
5663 /* Convert (ior (ashift A CX) (lshiftrt A CY)) where CX+CY equals the
5664 mode size to (rotate A CX). */
5666 if (((GET_CODE (op0) == ASHIFT && GET_CODE (op1) == LSHIFTRT)
5667 || (GET_CODE (op1) == ASHIFT && GET_CODE (op0) == LSHIFTRT))
5668 && rtx_equal_p (XEXP (op0, 0), XEXP (op1, 0))
5669 && GET_CODE (XEXP (op0, 1)) == CONST_INT
5670 && GET_CODE (XEXP (op1, 1)) == CONST_INT
5671 && (INTVAL (XEXP (op0, 1)) + INTVAL (XEXP (op1, 1))
5672 == GET_MODE_BITSIZE (mode)))
5673 return gen_rtx_ROTATE (mode, XEXP (op0, 0),
5674 (GET_CODE (op0) == ASHIFT
5675 ? XEXP (op0, 1) : XEXP (op1, 1)));
5677 /* If OP0 is (ashiftrt (plus ...) C), it might actually be
5678 a (sign_extend (plus ...)). If so, OP1 is a CONST_INT, and the PLUS
5679 does not affect any of the bits in OP1, it can really be done
5680 as a PLUS and we can associate. We do this by seeing if OP1
5681 can be safely shifted left C bits. */
5682 if (GET_CODE (op1) == CONST_INT && GET_CODE (op0) == ASHIFTRT
5683 && GET_CODE (XEXP (op0, 0)) == PLUS
5684 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
5685 && GET_CODE (XEXP (op0, 1)) == CONST_INT
5686 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT)
5688 int count = INTVAL (XEXP (op0, 1));
5689 HOST_WIDE_INT mask = INTVAL (op1) << count;
5691 if (mask >> count == INTVAL (op1)
5692 && (mask & nonzero_bits (XEXP (op0, 0), mode)) == 0)
5694 SUBST (XEXP (XEXP (op0, 0), 1),
5695 GEN_INT (INTVAL (XEXP (XEXP (op0, 0), 1)) | mask));
5702 /* If we are XORing two things that have no bits in common,
5703 convert them into an IOR. This helps to detect rotation encoded
5704 using those methods and possibly other simplifications. */
5706 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5707 && (nonzero_bits (op0, mode)
5708 & nonzero_bits (op1, mode)) == 0)
5709 return (simplify_gen_binary (IOR, mode, op0, op1));
5711 /* Convert (XOR (NOT x) (NOT y)) to (XOR x y).
5712 Also convert (XOR (NOT x) y) to (NOT (XOR x y)), similarly for
5715 int num_negated = 0;
5717 if (GET_CODE (op0) == NOT)
5718 num_negated++, op0 = XEXP (op0, 0);
5719 if (GET_CODE (op1) == NOT)
5720 num_negated++, op1 = XEXP (op1, 0);
5722 if (num_negated == 2)
5724 SUBST (XEXP (x, 0), op0);
5725 SUBST (XEXP (x, 1), op1);
5727 else if (num_negated == 1)
5729 simplify_gen_unary (NOT, mode,
5730 simplify_gen_binary (XOR, mode, op0, op1),
5734 /* Convert (xor (and A B) B) to (and (not A) B). The latter may
5735 correspond to a machine insn or result in further simplifications
5736 if B is a constant. */
5738 if (GET_CODE (op0) == AND
5739 && rtx_equal_p (XEXP (op0, 1), op1)
5740 && ! side_effects_p (op1))
5741 return simplify_gen_binary (AND, mode,
5742 simplify_gen_unary (NOT, mode,
5743 XEXP (op0, 0), mode),
5746 else if (GET_CODE (op0) == AND
5747 && rtx_equal_p (XEXP (op0, 0), op1)
5748 && ! side_effects_p (op1))
5749 return simplify_gen_binary (AND, mode,
5750 simplify_gen_unary (NOT, mode,
5751 XEXP (op0, 1), mode),
5754 /* (xor (comparison foo bar) (const_int 1)) can become the reversed
5755 comparison if STORE_FLAG_VALUE is 1. */
5756 if (STORE_FLAG_VALUE == 1
5757 && op1 == const1_rtx
5758 && COMPARISON_P (op0)
5759 && (reversed = reversed_comparison (op0, mode)))
5762 /* (lshiftrt foo C) where C is the number of bits in FOO minus 1
5763 is (lt foo (const_int 0)), so we can perform the above
5764 simplification if STORE_FLAG_VALUE is 1. */
5766 if (STORE_FLAG_VALUE == 1
5767 && op1 == const1_rtx
5768 && GET_CODE (op0) == LSHIFTRT
5769 && GET_CODE (XEXP (op0, 1)) == CONST_INT
5770 && INTVAL (XEXP (op0, 1)) == GET_MODE_BITSIZE (mode) - 1)
5771 return gen_rtx_GE (mode, XEXP (op0, 0), const0_rtx);
5773 /* (xor (comparison foo bar) (const_int sign-bit))
5774 when STORE_FLAG_VALUE is the sign bit. */
5775 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5776 && ((STORE_FLAG_VALUE & GET_MODE_MASK (mode))
5777 == (unsigned HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (mode) - 1))
5778 && op1 == const_true_rtx
5779 && COMPARISON_P (op0)
5780 && (reversed = reversed_comparison (op0, mode)))
5792 /* We consider ZERO_EXTRACT, SIGN_EXTRACT, and SIGN_EXTEND as "compound
5793 operations" because they can be replaced with two more basic operations.
5794 ZERO_EXTEND is also considered "compound" because it can be replaced with
5795 an AND operation, which is simpler, though only one operation.
5797 The function expand_compound_operation is called with an rtx expression
5798 and will convert it to the appropriate shifts and AND operations,
5799 simplifying at each stage.
5801 The function make_compound_operation is called to convert an expression
5802 consisting of shifts and ANDs into the equivalent compound expression.
5803 It is the inverse of this function, loosely speaking. */
5806 expand_compound_operation (rtx x)
5808 unsigned HOST_WIDE_INT pos = 0, len;
5810 unsigned int modewidth;
5813 switch (GET_CODE (x))
5818 /* We can't necessarily use a const_int for a multiword mode;
5819 it depends on implicitly extending the value.
5820 Since we don't know the right way to extend it,
5821 we can't tell whether the implicit way is right.
5823 Even for a mode that is no wider than a const_int,
5824 we can't win, because we need to sign extend one of its bits through
5825 the rest of it, and we don't know which bit. */
5826 if (GET_CODE (XEXP (x, 0)) == CONST_INT)
5829 /* Return if (subreg:MODE FROM 0) is not a safe replacement for
5830 (zero_extend:MODE FROM) or (sign_extend:MODE FROM). It is for any MEM
5831 because (SUBREG (MEM...)) is guaranteed to cause the MEM to be
5832 reloaded. If not for that, MEM's would very rarely be safe.
5834 Reject MODEs bigger than a word, because we might not be able
5835 to reference a two-register group starting with an arbitrary register
5836 (and currently gen_lowpart might crash for a SUBREG). */
5838 if (GET_MODE_SIZE (GET_MODE (XEXP (x, 0))) > UNITS_PER_WORD)
5841 /* Reject MODEs that aren't scalar integers because turning vector
5842 or complex modes into shifts causes problems. */
5844 if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x, 0))))
5847 len = GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)));
5848 /* If the inner object has VOIDmode (the only way this can happen
5849 is if it is an ASM_OPERANDS), we can't do anything since we don't
5850 know how much masking to do. */
5859 /* ... fall through ... */
5862 /* If the operand is a CLOBBER, just return it. */
5863 if (GET_CODE (XEXP (x, 0)) == CLOBBER)
5866 if (GET_CODE (XEXP (x, 1)) != CONST_INT
5867 || GET_CODE (XEXP (x, 2)) != CONST_INT
5868 || GET_MODE (XEXP (x, 0)) == VOIDmode)
5871 /* Reject MODEs that aren't scalar integers because turning vector
5872 or complex modes into shifts causes problems. */
5874 if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x, 0))))
5877 len = INTVAL (XEXP (x, 1));
5878 pos = INTVAL (XEXP (x, 2));
5880 /* If this goes outside the object being extracted, replace the object
5881 with a (use (mem ...)) construct that only combine understands
5882 and is used only for this purpose. */
5883 if (len + pos > GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))))
5884 SUBST (XEXP (x, 0), gen_rtx_USE (GET_MODE (x), XEXP (x, 0)));
5886 if (BITS_BIG_ENDIAN)
5887 pos = GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - len - pos;
5894 /* Convert sign extension to zero extension, if we know that the high
5895 bit is not set, as this is easier to optimize. It will be converted
5896 back to cheaper alternative in make_extraction. */
5897 if (GET_CODE (x) == SIGN_EXTEND
5898 && (GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
5899 && ((nonzero_bits (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
5900 & ~(((unsigned HOST_WIDE_INT)
5901 GET_MODE_MASK (GET_MODE (XEXP (x, 0))))
5905 rtx temp = gen_rtx_ZERO_EXTEND (GET_MODE (x), XEXP (x, 0));
5906 rtx temp2 = expand_compound_operation (temp);
5908 /* Make sure this is a profitable operation. */
5909 if (rtx_cost (x, SET) > rtx_cost (temp2, SET))
5911 else if (rtx_cost (x, SET) > rtx_cost (temp, SET))
5917 /* We can optimize some special cases of ZERO_EXTEND. */
5918 if (GET_CODE (x) == ZERO_EXTEND)
5920 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI if we
5921 know that the last value didn't have any inappropriate bits
5923 if (GET_CODE (XEXP (x, 0)) == TRUNCATE
5924 && GET_MODE (XEXP (XEXP (x, 0), 0)) == GET_MODE (x)
5925 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
5926 && (nonzero_bits (XEXP (XEXP (x, 0), 0), GET_MODE (x))
5927 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5928 return XEXP (XEXP (x, 0), 0);
5930 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
5931 if (GET_CODE (XEXP (x, 0)) == SUBREG
5932 && GET_MODE (SUBREG_REG (XEXP (x, 0))) == GET_MODE (x)
5933 && subreg_lowpart_p (XEXP (x, 0))
5934 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
5935 && (nonzero_bits (SUBREG_REG (XEXP (x, 0)), GET_MODE (x))
5936 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5937 return SUBREG_REG (XEXP (x, 0));
5939 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI when foo
5940 is a comparison and STORE_FLAG_VALUE permits. This is like
5941 the first case, but it works even when GET_MODE (x) is larger
5942 than HOST_WIDE_INT. */
5943 if (GET_CODE (XEXP (x, 0)) == TRUNCATE
5944 && GET_MODE (XEXP (XEXP (x, 0), 0)) == GET_MODE (x)
5945 && COMPARISON_P (XEXP (XEXP (x, 0), 0))
5946 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
5947 <= HOST_BITS_PER_WIDE_INT)
5948 && ((HOST_WIDE_INT) STORE_FLAG_VALUE
5949 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5950 return XEXP (XEXP (x, 0), 0);
5952 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
5953 if (GET_CODE (XEXP (x, 0)) == SUBREG
5954 && GET_MODE (SUBREG_REG (XEXP (x, 0))) == GET_MODE (x)
5955 && subreg_lowpart_p (XEXP (x, 0))
5956 && COMPARISON_P (SUBREG_REG (XEXP (x, 0)))
5957 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
5958 <= HOST_BITS_PER_WIDE_INT)
5959 && ((HOST_WIDE_INT) STORE_FLAG_VALUE
5960 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5961 return SUBREG_REG (XEXP (x, 0));
5965 /* If we reach here, we want to return a pair of shifts. The inner
5966 shift is a left shift of BITSIZE - POS - LEN bits. The outer
5967 shift is a right shift of BITSIZE - LEN bits. It is arithmetic or
5968 logical depending on the value of UNSIGNEDP.
5970 If this was a ZERO_EXTEND or ZERO_EXTRACT, this pair of shifts will be
5971 converted into an AND of a shift.
5973 We must check for the case where the left shift would have a negative
5974 count. This can happen in a case like (x >> 31) & 255 on machines
5975 that can't shift by a constant. On those machines, we would first
5976 combine the shift with the AND to produce a variable-position
5977 extraction. Then the constant of 31 would be substituted in to produce
5978 a such a position. */
5980 modewidth = GET_MODE_BITSIZE (GET_MODE (x));
5981 if (modewidth + len >= pos)
5982 tem = simplify_shift_const (NULL_RTX, unsignedp ? LSHIFTRT : ASHIFTRT,
5984 simplify_shift_const (NULL_RTX, ASHIFT,
5987 modewidth - pos - len),
5990 else if (unsignedp && len < HOST_BITS_PER_WIDE_INT)
5991 tem = simplify_and_const_int (NULL_RTX, GET_MODE (x),
5992 simplify_shift_const (NULL_RTX, LSHIFTRT,
5995 ((HOST_WIDE_INT) 1 << len) - 1);
5997 /* Any other cases we can't handle. */
6000 /* If we couldn't do this for some reason, return the original
6002 if (GET_CODE (tem) == CLOBBER)
6008 /* X is a SET which contains an assignment of one object into
6009 a part of another (such as a bit-field assignment, STRICT_LOW_PART,
6010 or certain SUBREGS). If possible, convert it into a series of
6013 We half-heartedly support variable positions, but do not at all
6014 support variable lengths. */
6017 expand_field_assignment (rtx x)
6020 rtx pos; /* Always counts from low bit. */
6022 rtx mask, cleared, masked;
6023 enum machine_mode compute_mode;
6025 /* Loop until we find something we can't simplify. */
6028 if (GET_CODE (SET_DEST (x)) == STRICT_LOW_PART
6029 && GET_CODE (XEXP (SET_DEST (x), 0)) == SUBREG)
6031 inner = SUBREG_REG (XEXP (SET_DEST (x), 0));
6032 len = GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0)));
6033 pos = GEN_INT (subreg_lsb (XEXP (SET_DEST (x), 0)));
6035 else if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
6036 && GET_CODE (XEXP (SET_DEST (x), 1)) == CONST_INT)
6038 inner = XEXP (SET_DEST (x), 0);
6039 len = INTVAL (XEXP (SET_DEST (x), 1));
6040 pos = XEXP (SET_DEST (x), 2);
6042 /* If the position is constant and spans the width of INNER,
6043 surround INNER with a USE to indicate this. */
6044 if (GET_CODE (pos) == CONST_INT
6045 && INTVAL (pos) + len > GET_MODE_BITSIZE (GET_MODE (inner)))
6046 inner = gen_rtx_USE (GET_MODE (SET_DEST (x)), inner);
6048 if (BITS_BIG_ENDIAN)
6050 if (GET_CODE (pos) == CONST_INT)
6051 pos = GEN_INT (GET_MODE_BITSIZE (GET_MODE (inner)) - len
6053 else if (GET_CODE (pos) == MINUS
6054 && GET_CODE (XEXP (pos, 1)) == CONST_INT
6055 && (INTVAL (XEXP (pos, 1))
6056 == GET_MODE_BITSIZE (GET_MODE (inner)) - len))
6057 /* If position is ADJUST - X, new position is X. */
6058 pos = XEXP (pos, 0);
6060 pos = simplify_gen_binary (MINUS, GET_MODE (pos),
6061 GEN_INT (GET_MODE_BITSIZE (
6068 /* A SUBREG between two modes that occupy the same numbers of words
6069 can be done by moving the SUBREG to the source. */
6070 else if (GET_CODE (SET_DEST (x)) == SUBREG
6071 /* We need SUBREGs to compute nonzero_bits properly. */
6072 && nonzero_sign_valid
6073 && (((GET_MODE_SIZE (GET_MODE (SET_DEST (x)))
6074 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
6075 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x))))
6076 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)))
6078 x = gen_rtx_SET (VOIDmode, SUBREG_REG (SET_DEST (x)),
6080 (GET_MODE (SUBREG_REG (SET_DEST (x))),
6087 while (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
6088 inner = SUBREG_REG (inner);
6090 compute_mode = GET_MODE (inner);
6092 /* Don't attempt bitwise arithmetic on non scalar integer modes. */
6093 if (! SCALAR_INT_MODE_P (compute_mode))
6095 enum machine_mode imode;
6097 /* Don't do anything for vector or complex integral types. */
6098 if (! FLOAT_MODE_P (compute_mode))
6101 /* Try to find an integral mode to pun with. */
6102 imode = mode_for_size (GET_MODE_BITSIZE (compute_mode), MODE_INT, 0);
6103 if (imode == BLKmode)
6106 compute_mode = imode;
6107 inner = gen_lowpart (imode, inner);
6110 /* Compute a mask of LEN bits, if we can do this on the host machine. */
6111 if (len >= HOST_BITS_PER_WIDE_INT)
6114 /* Now compute the equivalent expression. Make a copy of INNER
6115 for the SET_DEST in case it is a MEM into which we will substitute;
6116 we don't want shared RTL in that case. */
6117 mask = GEN_INT (((HOST_WIDE_INT) 1 << len) - 1);
6118 cleared = simplify_gen_binary (AND, compute_mode,
6119 simplify_gen_unary (NOT, compute_mode,
6120 simplify_gen_binary (ASHIFT,
6125 masked = simplify_gen_binary (ASHIFT, compute_mode,
6126 simplify_gen_binary (
6128 gen_lowpart (compute_mode, SET_SRC (x)),
6132 x = gen_rtx_SET (VOIDmode, copy_rtx (inner),
6133 simplify_gen_binary (IOR, compute_mode,
6140 /* Return an RTX for a reference to LEN bits of INNER. If POS_RTX is nonzero,
6141 it is an RTX that represents a variable starting position; otherwise,
6142 POS is the (constant) starting bit position (counted from the LSB).
6144 INNER may be a USE. This will occur when we started with a bitfield
6145 that went outside the boundary of the object in memory, which is
6146 allowed on most machines. To isolate this case, we produce a USE
6147 whose mode is wide enough and surround the MEM with it. The only
6148 code that understands the USE is this routine. If it is not removed,
6149 it will cause the resulting insn not to match.
6151 UNSIGNEDP is nonzero for an unsigned reference and zero for a
6154 IN_DEST is nonzero if this is a reference in the destination of a
6155 SET. This is used when a ZERO_ or SIGN_EXTRACT isn't needed. If nonzero,
6156 a STRICT_LOW_PART will be used, if zero, ZERO_EXTEND or SIGN_EXTEND will
6159 IN_COMPARE is nonzero if we are in a COMPARE. This means that a
6160 ZERO_EXTRACT should be built even for bits starting at bit 0.
6162 MODE is the desired mode of the result (if IN_DEST == 0).
6164 The result is an RTX for the extraction or NULL_RTX if the target
6168 make_extraction (enum machine_mode mode, rtx inner, HOST_WIDE_INT pos,
6169 rtx pos_rtx, unsigned HOST_WIDE_INT len, int unsignedp,
6170 int in_dest, int in_compare)
6172 /* This mode describes the size of the storage area
6173 to fetch the overall value from. Within that, we
6174 ignore the POS lowest bits, etc. */
6175 enum machine_mode is_mode = GET_MODE (inner);
6176 enum machine_mode inner_mode;
6177 enum machine_mode wanted_inner_mode = byte_mode;
6178 enum machine_mode wanted_inner_reg_mode = word_mode;
6179 enum machine_mode pos_mode = word_mode;
6180 enum machine_mode extraction_mode = word_mode;
6181 enum machine_mode tmode = mode_for_size (len, MODE_INT, 1);
6184 rtx orig_pos_rtx = pos_rtx;
6185 HOST_WIDE_INT orig_pos;
6187 /* Get some information about INNER and get the innermost object. */
6188 if (GET_CODE (inner) == USE)
6189 /* (use:SI (mem:QI foo)) stands for (mem:SI foo). */
6190 /* We don't need to adjust the position because we set up the USE
6191 to pretend that it was a full-word object. */
6192 spans_byte = 1, inner = XEXP (inner, 0);
6193 else if (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
6195 /* If going from (subreg:SI (mem:QI ...)) to (mem:QI ...),
6196 consider just the QI as the memory to extract from.
6197 The subreg adds or removes high bits; its mode is
6198 irrelevant to the meaning of this extraction,
6199 since POS and LEN count from the lsb. */
6200 if (MEM_P (SUBREG_REG (inner)))
6201 is_mode = GET_MODE (SUBREG_REG (inner));
6202 inner = SUBREG_REG (inner);
6204 else if (GET_CODE (inner) == ASHIFT
6205 && GET_CODE (XEXP (inner, 1)) == CONST_INT
6206 && pos_rtx == 0 && pos == 0
6207 && len > (unsigned HOST_WIDE_INT) INTVAL (XEXP (inner, 1)))
6209 /* We're extracting the least significant bits of an rtx
6210 (ashift X (const_int C)), where LEN > C. Extract the
6211 least significant (LEN - C) bits of X, giving an rtx
6212 whose mode is MODE, then shift it left C times. */
6213 new = make_extraction (mode, XEXP (inner, 0),
6214 0, 0, len - INTVAL (XEXP (inner, 1)),
6215 unsignedp, in_dest, in_compare);
6217 return gen_rtx_ASHIFT (mode, new, XEXP (inner, 1));
6220 inner_mode = GET_MODE (inner);
6222 if (pos_rtx && GET_CODE (pos_rtx) == CONST_INT)
6223 pos = INTVAL (pos_rtx), pos_rtx = 0;
6225 /* See if this can be done without an extraction. We never can if the
6226 width of the field is not the same as that of some integer mode. For
6227 registers, we can only avoid the extraction if the position is at the
6228 low-order bit and this is either not in the destination or we have the
6229 appropriate STRICT_LOW_PART operation available.
6231 For MEM, we can avoid an extract if the field starts on an appropriate
6232 boundary and we can change the mode of the memory reference. However,
6233 we cannot directly access the MEM if we have a USE and the underlying
6234 MEM is not TMODE. This combination means that MEM was being used in a
6235 context where bits outside its mode were being referenced; that is only
6236 valid in bit-field insns. */
6238 if (tmode != BLKmode
6239 && ! (spans_byte && inner_mode != tmode)
6240 && ((pos_rtx == 0 && (pos % BITS_PER_WORD) == 0
6244 && have_insn_for (STRICT_LOW_PART, tmode))))
6245 || (MEM_P (inner) && pos_rtx == 0
6247 % (STRICT_ALIGNMENT ? GET_MODE_ALIGNMENT (tmode)
6248 : BITS_PER_UNIT)) == 0
6249 /* We can't do this if we are widening INNER_MODE (it
6250 may not be aligned, for one thing). */
6251 && GET_MODE_BITSIZE (inner_mode) >= GET_MODE_BITSIZE (tmode)
6252 && (inner_mode == tmode
6253 || (! mode_dependent_address_p (XEXP (inner, 0))
6254 && ! MEM_VOLATILE_P (inner))))))
6256 /* If INNER is a MEM, make a new MEM that encompasses just the desired
6257 field. If the original and current mode are the same, we need not
6258 adjust the offset. Otherwise, we do if bytes big endian.
6260 If INNER is not a MEM, get a piece consisting of just the field
6261 of interest (in this case POS % BITS_PER_WORD must be 0). */
6265 HOST_WIDE_INT offset;
6267 /* POS counts from lsb, but make OFFSET count in memory order. */
6268 if (BYTES_BIG_ENDIAN)
6269 offset = (GET_MODE_BITSIZE (is_mode) - len - pos) / BITS_PER_UNIT;
6271 offset = pos / BITS_PER_UNIT;
6273 new = adjust_address_nv (inner, tmode, offset);
6275 else if (REG_P (inner))
6277 if (tmode != inner_mode)
6279 /* We can't call gen_lowpart in a DEST since we
6280 always want a SUBREG (see below) and it would sometimes
6281 return a new hard register. */
6284 HOST_WIDE_INT final_word = pos / BITS_PER_WORD;
6286 if (WORDS_BIG_ENDIAN
6287 && GET_MODE_SIZE (inner_mode) > UNITS_PER_WORD)
6288 final_word = ((GET_MODE_SIZE (inner_mode)
6289 - GET_MODE_SIZE (tmode))
6290 / UNITS_PER_WORD) - final_word;
6292 final_word *= UNITS_PER_WORD;
6293 if (BYTES_BIG_ENDIAN &&
6294 GET_MODE_SIZE (inner_mode) > GET_MODE_SIZE (tmode))
6295 final_word += (GET_MODE_SIZE (inner_mode)
6296 - GET_MODE_SIZE (tmode)) % UNITS_PER_WORD;
6298 /* Avoid creating invalid subregs, for example when
6299 simplifying (x>>32)&255. */
6300 if (final_word >= GET_MODE_SIZE (inner_mode))
6303 new = gen_rtx_SUBREG (tmode, inner, final_word);
6306 new = gen_lowpart (tmode, inner);
6312 new = force_to_mode (inner, tmode,
6313 len >= HOST_BITS_PER_WIDE_INT
6314 ? ~(unsigned HOST_WIDE_INT) 0
6315 : ((unsigned HOST_WIDE_INT) 1 << len) - 1,
6318 /* If this extraction is going into the destination of a SET,
6319 make a STRICT_LOW_PART unless we made a MEM. */
6322 return (MEM_P (new) ? new
6323 : (GET_CODE (new) != SUBREG
6324 ? gen_rtx_CLOBBER (tmode, const0_rtx)
6325 : gen_rtx_STRICT_LOW_PART (VOIDmode, new)));
6330 if (GET_CODE (new) == CONST_INT)
6331 return gen_int_mode (INTVAL (new), mode);
6333 /* If we know that no extraneous bits are set, and that the high
6334 bit is not set, convert the extraction to the cheaper of
6335 sign and zero extension, that are equivalent in these cases. */
6336 if (flag_expensive_optimizations
6337 && (GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT
6338 && ((nonzero_bits (new, tmode)
6339 & ~(((unsigned HOST_WIDE_INT)
6340 GET_MODE_MASK (tmode))
6344 rtx temp = gen_rtx_ZERO_EXTEND (mode, new);
6345 rtx temp1 = gen_rtx_SIGN_EXTEND (mode, new);
6347 /* Prefer ZERO_EXTENSION, since it gives more information to
6349 if (rtx_cost (temp, SET) <= rtx_cost (temp1, SET))
6354 /* Otherwise, sign- or zero-extend unless we already are in the
6357 return (gen_rtx_fmt_e (unsignedp ? ZERO_EXTEND : SIGN_EXTEND,
6361 /* Unless this is a COMPARE or we have a funny memory reference,
6362 don't do anything with zero-extending field extracts starting at
6363 the low-order bit since they are simple AND operations. */
6364 if (pos_rtx == 0 && pos == 0 && ! in_dest
6365 && ! in_compare && ! spans_byte && unsignedp)
6368 /* Unless we are allowed to span bytes or INNER is not MEM, reject this if
6369 we would be spanning bytes or if the position is not a constant and the
6370 length is not 1. In all other cases, we would only be going outside
6371 our object in cases when an original shift would have been
6373 if (! spans_byte && MEM_P (inner)
6374 && ((pos_rtx == 0 && pos + len > GET_MODE_BITSIZE (is_mode))
6375 || (pos_rtx != 0 && len != 1)))
6378 /* Get the mode to use should INNER not be a MEM, the mode for the position,
6379 and the mode for the result. */
6380 if (in_dest && mode_for_extraction (EP_insv, -1) != MAX_MACHINE_MODE)
6382 wanted_inner_reg_mode = mode_for_extraction (EP_insv, 0);
6383 pos_mode = mode_for_extraction (EP_insv, 2);
6384 extraction_mode = mode_for_extraction (EP_insv, 3);
6387 if (! in_dest && unsignedp
6388 && mode_for_extraction (EP_extzv, -1) != MAX_MACHINE_MODE)
6390 wanted_inner_reg_mode = mode_for_extraction (EP_extzv, 1);
6391 pos_mode = mode_for_extraction (EP_extzv, 3);
6392 extraction_mode = mode_for_extraction (EP_extzv, 0);
6395 if (! in_dest && ! unsignedp
6396 && mode_for_extraction (EP_extv, -1) != MAX_MACHINE_MODE)
6398 wanted_inner_reg_mode = mode_for_extraction (EP_extv, 1);
6399 pos_mode = mode_for_extraction (EP_extv, 3);
6400 extraction_mode = mode_for_extraction (EP_extv, 0);
6403 /* Never narrow an object, since that might not be safe. */
6405 if (mode != VOIDmode
6406 && GET_MODE_SIZE (extraction_mode) < GET_MODE_SIZE (mode))
6407 extraction_mode = mode;
6409 if (pos_rtx && GET_MODE (pos_rtx) != VOIDmode
6410 && GET_MODE_SIZE (pos_mode) < GET_MODE_SIZE (GET_MODE (pos_rtx)))
6411 pos_mode = GET_MODE (pos_rtx);
6413 /* If this is not from memory, the desired mode is wanted_inner_reg_mode;
6414 if we have to change the mode of memory and cannot, the desired mode is
6417 wanted_inner_mode = wanted_inner_reg_mode;
6418 else if (inner_mode != wanted_inner_mode
6419 && (mode_dependent_address_p (XEXP (inner, 0))
6420 || MEM_VOLATILE_P (inner)))
6421 wanted_inner_mode = extraction_mode;
6425 if (BITS_BIG_ENDIAN)
6427 /* POS is passed as if BITS_BIG_ENDIAN == 0, so we need to convert it to
6428 BITS_BIG_ENDIAN style. If position is constant, compute new
6429 position. Otherwise, build subtraction.
6430 Note that POS is relative to the mode of the original argument.
6431 If it's a MEM we need to recompute POS relative to that.
6432 However, if we're extracting from (or inserting into) a register,
6433 we want to recompute POS relative to wanted_inner_mode. */
6434 int width = (MEM_P (inner)
6435 ? GET_MODE_BITSIZE (is_mode)
6436 : GET_MODE_BITSIZE (wanted_inner_mode));
6439 pos = width - len - pos;
6442 = gen_rtx_MINUS (GET_MODE (pos_rtx), GEN_INT (width - len), pos_rtx);
6443 /* POS may be less than 0 now, but we check for that below.
6444 Note that it can only be less than 0 if !MEM_P (inner). */
6447 /* If INNER has a wider mode, make it smaller. If this is a constant
6448 extract, try to adjust the byte to point to the byte containing
6450 if (wanted_inner_mode != VOIDmode
6451 && GET_MODE_SIZE (wanted_inner_mode) < GET_MODE_SIZE (is_mode)
6453 && (inner_mode == wanted_inner_mode
6454 || (! mode_dependent_address_p (XEXP (inner, 0))
6455 && ! MEM_VOLATILE_P (inner))))))
6459 /* The computations below will be correct if the machine is big
6460 endian in both bits and bytes or little endian in bits and bytes.
6461 If it is mixed, we must adjust. */
6463 /* If bytes are big endian and we had a paradoxical SUBREG, we must
6464 adjust OFFSET to compensate. */
6465 if (BYTES_BIG_ENDIAN
6467 && GET_MODE_SIZE (inner_mode) < GET_MODE_SIZE (is_mode))
6468 offset -= GET_MODE_SIZE (is_mode) - GET_MODE_SIZE (inner_mode);
6470 /* If this is a constant position, we can move to the desired byte. */
6473 offset += pos / BITS_PER_UNIT;
6474 pos %= GET_MODE_BITSIZE (wanted_inner_mode);
6477 if (BYTES_BIG_ENDIAN != BITS_BIG_ENDIAN
6479 && is_mode != wanted_inner_mode)
6480 offset = (GET_MODE_SIZE (is_mode)
6481 - GET_MODE_SIZE (wanted_inner_mode) - offset);
6483 if (offset != 0 || inner_mode != wanted_inner_mode)
6484 inner = adjust_address_nv (inner, wanted_inner_mode, offset);
6487 /* If INNER is not memory, we can always get it into the proper mode. If we
6488 are changing its mode, POS must be a constant and smaller than the size
6490 else if (!MEM_P (inner))
6492 if (GET_MODE (inner) != wanted_inner_mode
6494 || orig_pos + len > GET_MODE_BITSIZE (wanted_inner_mode)))
6497 inner = force_to_mode (inner, wanted_inner_mode,
6499 || len + orig_pos >= HOST_BITS_PER_WIDE_INT
6500 ? ~(unsigned HOST_WIDE_INT) 0
6501 : ((((unsigned HOST_WIDE_INT) 1 << len) - 1)
6506 /* Adjust mode of POS_RTX, if needed. If we want a wider mode, we
6507 have to zero extend. Otherwise, we can just use a SUBREG. */
6509 && GET_MODE_SIZE (pos_mode) > GET_MODE_SIZE (GET_MODE (pos_rtx)))
6511 rtx temp = gen_rtx_ZERO_EXTEND (pos_mode, pos_rtx);
6513 /* If we know that no extraneous bits are set, and that the high
6514 bit is not set, convert extraction to cheaper one - either
6515 SIGN_EXTENSION or ZERO_EXTENSION, that are equivalent in these
6517 if (flag_expensive_optimizations
6518 && (GET_MODE_BITSIZE (GET_MODE (pos_rtx)) <= HOST_BITS_PER_WIDE_INT
6519 && ((nonzero_bits (pos_rtx, GET_MODE (pos_rtx))
6520 & ~(((unsigned HOST_WIDE_INT)
6521 GET_MODE_MASK (GET_MODE (pos_rtx)))
6525 rtx temp1 = gen_rtx_SIGN_EXTEND (pos_mode, pos_rtx);
6527 /* Prefer ZERO_EXTENSION, since it gives more information to
6529 if (rtx_cost (temp1, SET) < rtx_cost (temp, SET))
6534 else if (pos_rtx != 0
6535 && GET_MODE_SIZE (pos_mode) < GET_MODE_SIZE (GET_MODE (pos_rtx)))
6536 pos_rtx = gen_lowpart (pos_mode, pos_rtx);
6538 /* Make POS_RTX unless we already have it and it is correct. If we don't
6539 have a POS_RTX but we do have an ORIG_POS_RTX, the latter must
6541 if (pos_rtx == 0 && orig_pos_rtx != 0 && INTVAL (orig_pos_rtx) == pos)
6542 pos_rtx = orig_pos_rtx;
6544 else if (pos_rtx == 0)
6545 pos_rtx = GEN_INT (pos);
6547 /* Make the required operation. See if we can use existing rtx. */
6548 new = gen_rtx_fmt_eee (unsignedp ? ZERO_EXTRACT : SIGN_EXTRACT,
6549 extraction_mode, inner, GEN_INT (len), pos_rtx);
6551 new = gen_lowpart (mode, new);
6556 /* See if X contains an ASHIFT of COUNT or more bits that can be commuted
6557 with any other operations in X. Return X without that shift if so. */
6560 extract_left_shift (rtx x, int count)
6562 enum rtx_code code = GET_CODE (x);
6563 enum machine_mode mode = GET_MODE (x);
6569 /* This is the shift itself. If it is wide enough, we will return
6570 either the value being shifted if the shift count is equal to
6571 COUNT or a shift for the difference. */
6572 if (GET_CODE (XEXP (x, 1)) == CONST_INT
6573 && INTVAL (XEXP (x, 1)) >= count)
6574 return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (x, 0),
6575 INTVAL (XEXP (x, 1)) - count);
6579 if ((tem = extract_left_shift (XEXP (x, 0), count)) != 0)
6580 return simplify_gen_unary (code, mode, tem, mode);
6584 case PLUS: case IOR: case XOR: case AND:
6585 /* If we can safely shift this constant and we find the inner shift,
6586 make a new operation. */
6587 if (GET_CODE (XEXP (x, 1)) == CONST_INT
6588 && (INTVAL (XEXP (x, 1)) & ((((HOST_WIDE_INT) 1 << count)) - 1)) == 0
6589 && (tem = extract_left_shift (XEXP (x, 0), count)) != 0)
6590 return simplify_gen_binary (code, mode, tem,
6591 GEN_INT (INTVAL (XEXP (x, 1)) >> count));
6602 /* Look at the expression rooted at X. Look for expressions
6603 equivalent to ZERO_EXTRACT, SIGN_EXTRACT, ZERO_EXTEND, SIGN_EXTEND.
6604 Form these expressions.
6606 Return the new rtx, usually just X.
6608 Also, for machines like the VAX that don't have logical shift insns,
6609 try to convert logical to arithmetic shift operations in cases where
6610 they are equivalent. This undoes the canonicalizations to logical
6611 shifts done elsewhere.
6613 We try, as much as possible, to re-use rtl expressions to save memory.
6615 IN_CODE says what kind of expression we are processing. Normally, it is
6616 SET. In a memory address (inside a MEM, PLUS or minus, the latter two
6617 being kludges), it is MEM. When processing the arguments of a comparison
6618 or a COMPARE against zero, it is COMPARE. */
6621 make_compound_operation (rtx x, enum rtx_code in_code)
6623 enum rtx_code code = GET_CODE (x);
6624 enum machine_mode mode = GET_MODE (x);
6625 int mode_width = GET_MODE_BITSIZE (mode);
6627 enum rtx_code next_code;
6633 /* Select the code to be used in recursive calls. Once we are inside an
6634 address, we stay there. If we have a comparison, set to COMPARE,
6635 but once inside, go back to our default of SET. */
6637 next_code = (code == MEM || code == PLUS || code == MINUS ? MEM
6638 : ((code == COMPARE || COMPARISON_P (x))
6639 && XEXP (x, 1) == const0_rtx) ? COMPARE
6640 : in_code == COMPARE ? SET : in_code);
6642 /* Process depending on the code of this operation. If NEW is set
6643 nonzero, it will be returned. */
6648 /* Convert shifts by constants into multiplications if inside
6650 if (in_code == MEM && GET_CODE (XEXP (x, 1)) == CONST_INT
6651 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT
6652 && INTVAL (XEXP (x, 1)) >= 0)
6654 new = make_compound_operation (XEXP (x, 0), next_code);
6655 new = gen_rtx_MULT (mode, new,
6656 GEN_INT ((HOST_WIDE_INT) 1
6657 << INTVAL (XEXP (x, 1))));
6662 /* If the second operand is not a constant, we can't do anything
6664 if (GET_CODE (XEXP (x, 1)) != CONST_INT)
6667 /* If the constant is a power of two minus one and the first operand
6668 is a logical right shift, make an extraction. */
6669 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
6670 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6672 new = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code);
6673 new = make_extraction (mode, new, 0, XEXP (XEXP (x, 0), 1), i, 1,
6674 0, in_code == COMPARE);
6677 /* Same as previous, but for (subreg (lshiftrt ...)) in first op. */
6678 else if (GET_CODE (XEXP (x, 0)) == SUBREG
6679 && subreg_lowpart_p (XEXP (x, 0))
6680 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == LSHIFTRT
6681 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6683 new = make_compound_operation (XEXP (SUBREG_REG (XEXP (x, 0)), 0),
6685 new = make_extraction (GET_MODE (SUBREG_REG (XEXP (x, 0))), new, 0,
6686 XEXP (SUBREG_REG (XEXP (x, 0)), 1), i, 1,
6687 0, in_code == COMPARE);
6689 /* Same as previous, but for (xor/ior (lshiftrt...) (lshiftrt...)). */
6690 else if ((GET_CODE (XEXP (x, 0)) == XOR
6691 || GET_CODE (XEXP (x, 0)) == IOR)
6692 && GET_CODE (XEXP (XEXP (x, 0), 0)) == LSHIFTRT
6693 && GET_CODE (XEXP (XEXP (x, 0), 1)) == LSHIFTRT
6694 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6696 /* Apply the distributive law, and then try to make extractions. */
6697 new = gen_rtx_fmt_ee (GET_CODE (XEXP (x, 0)), mode,
6698 gen_rtx_AND (mode, XEXP (XEXP (x, 0), 0),
6700 gen_rtx_AND (mode, XEXP (XEXP (x, 0), 1),
6702 new = make_compound_operation (new, in_code);
6705 /* If we are have (and (rotate X C) M) and C is larger than the number
6706 of bits in M, this is an extraction. */
6708 else if (GET_CODE (XEXP (x, 0)) == ROTATE
6709 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
6710 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0
6711 && i <= INTVAL (XEXP (XEXP (x, 0), 1)))
6713 new = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code);
6714 new = make_extraction (mode, new,
6715 (GET_MODE_BITSIZE (mode)
6716 - INTVAL (XEXP (XEXP (x, 0), 1))),
6717 NULL_RTX, i, 1, 0, in_code == COMPARE);
6720 /* On machines without logical shifts, if the operand of the AND is
6721 a logical shift and our mask turns off all the propagated sign
6722 bits, we can replace the logical shift with an arithmetic shift. */
6723 else if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
6724 && !have_insn_for (LSHIFTRT, mode)
6725 && have_insn_for (ASHIFTRT, mode)
6726 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
6727 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
6728 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT
6729 && mode_width <= HOST_BITS_PER_WIDE_INT)
6731 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
6733 mask >>= INTVAL (XEXP (XEXP (x, 0), 1));
6734 if ((INTVAL (XEXP (x, 1)) & ~mask) == 0)
6736 gen_rtx_ASHIFTRT (mode,
6737 make_compound_operation
6738 (XEXP (XEXP (x, 0), 0), next_code),
6739 XEXP (XEXP (x, 0), 1)));
6742 /* If the constant is one less than a power of two, this might be
6743 representable by an extraction even if no shift is present.
6744 If it doesn't end up being a ZERO_EXTEND, we will ignore it unless
6745 we are in a COMPARE. */
6746 else if ((i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6747 new = make_extraction (mode,
6748 make_compound_operation (XEXP (x, 0),
6750 0, NULL_RTX, i, 1, 0, in_code == COMPARE);
6752 /* If we are in a comparison and this is an AND with a power of two,
6753 convert this into the appropriate bit extract. */
6754 else if (in_code == COMPARE
6755 && (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0)
6756 new = make_extraction (mode,
6757 make_compound_operation (XEXP (x, 0),
6759 i, NULL_RTX, 1, 1, 0, 1);
6764 /* If the sign bit is known to be zero, replace this with an
6765 arithmetic shift. */
6766 if (have_insn_for (ASHIFTRT, mode)
6767 && ! have_insn_for (LSHIFTRT, mode)
6768 && mode_width <= HOST_BITS_PER_WIDE_INT
6769 && (nonzero_bits (XEXP (x, 0), mode) & (1 << (mode_width - 1))) == 0)
6771 new = gen_rtx_ASHIFTRT (mode,
6772 make_compound_operation (XEXP (x, 0),
6778 /* ... fall through ... */
6784 /* If we have (ashiftrt (ashift foo C1) C2) with C2 >= C1,
6785 this is a SIGN_EXTRACT. */
6786 if (GET_CODE (rhs) == CONST_INT
6787 && GET_CODE (lhs) == ASHIFT
6788 && GET_CODE (XEXP (lhs, 1)) == CONST_INT
6789 && INTVAL (rhs) >= INTVAL (XEXP (lhs, 1)))
6791 new = make_compound_operation (XEXP (lhs, 0), next_code);
6792 new = make_extraction (mode, new,
6793 INTVAL (rhs) - INTVAL (XEXP (lhs, 1)),
6794 NULL_RTX, mode_width - INTVAL (rhs),
6795 code == LSHIFTRT, 0, in_code == COMPARE);
6799 /* See if we have operations between an ASHIFTRT and an ASHIFT.
6800 If so, try to merge the shifts into a SIGN_EXTEND. We could
6801 also do this for some cases of SIGN_EXTRACT, but it doesn't
6802 seem worth the effort; the case checked for occurs on Alpha. */
6805 && ! (GET_CODE (lhs) == SUBREG
6806 && (OBJECT_P (SUBREG_REG (lhs))))
6807 && GET_CODE (rhs) == CONST_INT
6808 && INTVAL (rhs) < HOST_BITS_PER_WIDE_INT
6809 && (new = extract_left_shift (lhs, INTVAL (rhs))) != 0)
6810 new = make_extraction (mode, make_compound_operation (new, next_code),
6811 0, NULL_RTX, mode_width - INTVAL (rhs),
6812 code == LSHIFTRT, 0, in_code == COMPARE);
6817 /* Call ourselves recursively on the inner expression. If we are
6818 narrowing the object and it has a different RTL code from
6819 what it originally did, do this SUBREG as a force_to_mode. */
6821 tem = make_compound_operation (SUBREG_REG (x), in_code);
6825 simplified = simplify_subreg (GET_MODE (x), tem, GET_MODE (tem),
6831 if (GET_CODE (tem) != GET_CODE (SUBREG_REG (x))
6832 && GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (tem))
6833 && subreg_lowpart_p (x))
6835 rtx newer = force_to_mode (tem, mode, ~(HOST_WIDE_INT) 0,
6838 /* If we have something other than a SUBREG, we might have
6839 done an expansion, so rerun ourselves. */
6840 if (GET_CODE (newer) != SUBREG)
6841 newer = make_compound_operation (newer, in_code);
6857 x = gen_lowpart (mode, new);
6858 code = GET_CODE (x);
6861 /* Now recursively process each operand of this operation. */
6862 fmt = GET_RTX_FORMAT (code);
6863 for (i = 0; i < GET_RTX_LENGTH (code); i++)
6866 new = make_compound_operation (XEXP (x, i), next_code);
6867 SUBST (XEXP (x, i), new);
6873 /* Given M see if it is a value that would select a field of bits
6874 within an item, but not the entire word. Return -1 if not.
6875 Otherwise, return the starting position of the field, where 0 is the
6878 *PLEN is set to the length of the field. */
6881 get_pos_from_mask (unsigned HOST_WIDE_INT m, unsigned HOST_WIDE_INT *plen)
6883 /* Get the bit number of the first 1 bit from the right, -1 if none. */
6884 int pos = exact_log2 (m & -m);
6888 /* Now shift off the low-order zero bits and see if we have a
6889 power of two minus 1. */
6890 len = exact_log2 ((m >> pos) + 1);
6899 /* See if X can be simplified knowing that we will only refer to it in
6900 MODE and will only refer to those bits that are nonzero in MASK.
6901 If other bits are being computed or if masking operations are done
6902 that select a superset of the bits in MASK, they can sometimes be
6905 Return a possibly simplified expression, but always convert X to
6906 MODE. If X is a CONST_INT, AND the CONST_INT with MASK.
6908 Also, if REG is nonzero and X is a register equal in value to REG,
6911 If JUST_SELECT is nonzero, don't optimize by noticing that bits in MASK
6912 are all off in X. This is used when X will be complemented, by either
6913 NOT, NEG, or XOR. */
6916 force_to_mode (rtx x, enum machine_mode mode, unsigned HOST_WIDE_INT mask,
6917 rtx reg, int just_select)
6919 enum rtx_code code = GET_CODE (x);
6920 int next_select = just_select || code == XOR || code == NOT || code == NEG;
6921 enum machine_mode op_mode;
6922 unsigned HOST_WIDE_INT fuller_mask, nonzero;
6925 /* If this is a CALL or ASM_OPERANDS, don't do anything. Some of the
6926 code below will do the wrong thing since the mode of such an
6927 expression is VOIDmode.
6929 Also do nothing if X is a CLOBBER; this can happen if X was
6930 the return value from a call to gen_lowpart. */
6931 if (code == CALL || code == ASM_OPERANDS || code == CLOBBER)
6934 /* We want to perform the operation is its present mode unless we know
6935 that the operation is valid in MODE, in which case we do the operation
6937 op_mode = ((GET_MODE_CLASS (mode) == GET_MODE_CLASS (GET_MODE (x))
6938 && have_insn_for (code, mode))
6939 ? mode : GET_MODE (x));
6941 /* It is not valid to do a right-shift in a narrower mode
6942 than the one it came in with. */
6943 if ((code == LSHIFTRT || code == ASHIFTRT)
6944 && GET_MODE_BITSIZE (mode) < GET_MODE_BITSIZE (GET_MODE (x)))
6945 op_mode = GET_MODE (x);
6947 /* Truncate MASK to fit OP_MODE. */
6949 mask &= GET_MODE_MASK (op_mode);
6951 /* When we have an arithmetic operation, or a shift whose count we
6952 do not know, we need to assume that all bits up to the highest-order
6953 bit in MASK will be needed. This is how we form such a mask. */
6954 if (mask & ((unsigned HOST_WIDE_INT) 1 << (HOST_BITS_PER_WIDE_INT - 1)))
6955 fuller_mask = ~(unsigned HOST_WIDE_INT) 0;
6957 fuller_mask = (((unsigned HOST_WIDE_INT) 1 << (floor_log2 (mask) + 1))
6960 /* Determine what bits of X are guaranteed to be (non)zero. */
6961 nonzero = nonzero_bits (x, mode);
6963 /* If none of the bits in X are needed, return a zero. */
6964 if (! just_select && (nonzero & mask) == 0)
6967 /* If X is a CONST_INT, return a new one. Do this here since the
6968 test below will fail. */
6969 if (GET_CODE (x) == CONST_INT)
6971 if (SCALAR_INT_MODE_P (mode))
6972 return gen_int_mode (INTVAL (x) & mask, mode);
6975 x = GEN_INT (INTVAL (x) & mask);
6976 return gen_lowpart_common (mode, x);
6980 /* If X is narrower than MODE and we want all the bits in X's mode, just
6981 get X in the proper mode. */
6982 if (GET_MODE_SIZE (GET_MODE (x)) < GET_MODE_SIZE (mode)
6983 && (GET_MODE_MASK (GET_MODE (x)) & ~mask) == 0)
6984 return gen_lowpart (mode, x);
6989 /* If X is a (clobber (const_int)), return it since we know we are
6990 generating something that won't match. */
6994 /* X is a (use (mem ..)) that was made from a bit-field extraction that
6995 spanned the boundary of the MEM. If we are now masking so it is
6996 within that boundary, we don't need the USE any more. */
6997 if (! BITS_BIG_ENDIAN
6998 && (mask & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
6999 return force_to_mode (XEXP (x, 0), mode, mask, reg, next_select);
7006 x = expand_compound_operation (x);
7007 if (GET_CODE (x) != code)
7008 return force_to_mode (x, mode, mask, reg, next_select);
7012 if (reg != 0 && (rtx_equal_p (get_last_value (reg), x)
7013 || rtx_equal_p (reg, get_last_value (x))))
7018 if (subreg_lowpart_p (x)
7019 /* We can ignore the effect of this SUBREG if it narrows the mode or
7020 if the constant masks to zero all the bits the mode doesn't
7022 && ((GET_MODE_SIZE (GET_MODE (x))
7023 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
7025 & GET_MODE_MASK (GET_MODE (x))
7026 & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (x)))))))
7027 return force_to_mode (SUBREG_REG (x), mode, mask, reg, next_select);
7031 /* If this is an AND with a constant, convert it into an AND
7032 whose constant is the AND of that constant with MASK. If it
7033 remains an AND of MASK, delete it since it is redundant. */
7035 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
7037 x = simplify_and_const_int (x, op_mode, XEXP (x, 0),
7038 mask & INTVAL (XEXP (x, 1)));
7040 /* If X is still an AND, see if it is an AND with a mask that
7041 is just some low-order bits. If so, and it is MASK, we don't
7044 if (GET_CODE (x) == AND && GET_CODE (XEXP (x, 1)) == CONST_INT
7045 && ((INTVAL (XEXP (x, 1)) & GET_MODE_MASK (GET_MODE (x)))
7049 /* If it remains an AND, try making another AND with the bits
7050 in the mode mask that aren't in MASK turned on. If the
7051 constant in the AND is wide enough, this might make a
7052 cheaper constant. */
7054 if (GET_CODE (x) == AND && GET_CODE (XEXP (x, 1)) == CONST_INT
7055 && GET_MODE_MASK (GET_MODE (x)) != mask
7056 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT)
7058 HOST_WIDE_INT cval = (INTVAL (XEXP (x, 1))
7059 | (GET_MODE_MASK (GET_MODE (x)) & ~mask));
7060 int width = GET_MODE_BITSIZE (GET_MODE (x));
7063 /* If MODE is narrower than HOST_WIDE_INT and CVAL is a negative
7064 number, sign extend it. */
7065 if (width > 0 && width < HOST_BITS_PER_WIDE_INT
7066 && (cval & ((HOST_WIDE_INT) 1 << (width - 1))) != 0)
7067 cval |= (HOST_WIDE_INT) -1 << width;
7069 y = simplify_gen_binary (AND, GET_MODE (x),
7070 XEXP (x, 0), GEN_INT (cval));
7071 if (rtx_cost (y, SET) < rtx_cost (x, SET))
7081 /* In (and (plus FOO C1) M), if M is a mask that just turns off
7082 low-order bits (as in an alignment operation) and FOO is already
7083 aligned to that boundary, mask C1 to that boundary as well.
7084 This may eliminate that PLUS and, later, the AND. */
7087 unsigned int width = GET_MODE_BITSIZE (mode);
7088 unsigned HOST_WIDE_INT smask = mask;
7090 /* If MODE is narrower than HOST_WIDE_INT and mask is a negative
7091 number, sign extend it. */
7093 if (width < HOST_BITS_PER_WIDE_INT
7094 && (smask & ((HOST_WIDE_INT) 1 << (width - 1))) != 0)
7095 smask |= (HOST_WIDE_INT) -1 << width;
7097 if (GET_CODE (XEXP (x, 1)) == CONST_INT
7098 && exact_log2 (- smask) >= 0
7099 && (nonzero_bits (XEXP (x, 0), mode) & ~smask) == 0
7100 && (INTVAL (XEXP (x, 1)) & ~smask) != 0)
7101 return force_to_mode (plus_constant (XEXP (x, 0),
7102 (INTVAL (XEXP (x, 1)) & smask)),
7103 mode, smask, reg, next_select);
7106 /* ... fall through ... */
7109 /* For PLUS, MINUS and MULT, we need any bits less significant than the
7110 most significant bit in MASK since carries from those bits will
7111 affect the bits we are interested in. */
7116 /* If X is (minus C Y) where C's least set bit is larger than any bit
7117 in the mask, then we may replace with (neg Y). */
7118 if (GET_CODE (XEXP (x, 0)) == CONST_INT
7119 && (((unsigned HOST_WIDE_INT) (INTVAL (XEXP (x, 0))
7120 & -INTVAL (XEXP (x, 0))))
7123 x = simplify_gen_unary (NEG, GET_MODE (x), XEXP (x, 1),
7125 return force_to_mode (x, mode, mask, reg, next_select);
7128 /* Similarly, if C contains every bit in the fuller_mask, then we may
7129 replace with (not Y). */
7130 if (GET_CODE (XEXP (x, 0)) == CONST_INT
7131 && ((INTVAL (XEXP (x, 0)) | (HOST_WIDE_INT) fuller_mask)
7132 == INTVAL (XEXP (x, 0))))
7134 x = simplify_gen_unary (NOT, GET_MODE (x),
7135 XEXP (x, 1), GET_MODE (x));
7136 return force_to_mode (x, mode, mask, reg, next_select);
7144 /* If X is (ior (lshiftrt FOO C1) C2), try to commute the IOR and
7145 LSHIFTRT so we end up with an (and (lshiftrt (ior ...) ...) ...)
7146 operation which may be a bitfield extraction. Ensure that the
7147 constant we form is not wider than the mode of X. */
7149 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
7150 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
7151 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
7152 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT
7153 && GET_CODE (XEXP (x, 1)) == CONST_INT
7154 && ((INTVAL (XEXP (XEXP (x, 0), 1))
7155 + floor_log2 (INTVAL (XEXP (x, 1))))
7156 < GET_MODE_BITSIZE (GET_MODE (x)))
7157 && (INTVAL (XEXP (x, 1))
7158 & ~nonzero_bits (XEXP (x, 0), GET_MODE (x))) == 0)
7160 temp = GEN_INT ((INTVAL (XEXP (x, 1)) & mask)
7161 << INTVAL (XEXP (XEXP (x, 0), 1)));
7162 temp = simplify_gen_binary (GET_CODE (x), GET_MODE (x),
7163 XEXP (XEXP (x, 0), 0), temp);
7164 x = simplify_gen_binary (LSHIFTRT, GET_MODE (x), temp,
7165 XEXP (XEXP (x, 0), 1));
7166 return force_to_mode (x, mode, mask, reg, next_select);
7170 /* For most binary operations, just propagate into the operation and
7171 change the mode if we have an operation of that mode. */
7173 op0 = gen_lowpart (op_mode,
7174 force_to_mode (XEXP (x, 0), mode, mask,
7176 op1 = gen_lowpart (op_mode,
7177 force_to_mode (XEXP (x, 1), mode, mask,
7180 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
7181 x = simplify_gen_binary (code, op_mode, op0, op1);
7185 /* For left shifts, do the same, but just for the first operand.
7186 However, we cannot do anything with shifts where we cannot
7187 guarantee that the counts are smaller than the size of the mode
7188 because such a count will have a different meaning in a
7191 if (! (GET_CODE (XEXP (x, 1)) == CONST_INT
7192 && INTVAL (XEXP (x, 1)) >= 0
7193 && INTVAL (XEXP (x, 1)) < GET_MODE_BITSIZE (mode))
7194 && ! (GET_MODE (XEXP (x, 1)) != VOIDmode
7195 && (nonzero_bits (XEXP (x, 1), GET_MODE (XEXP (x, 1)))
7196 < (unsigned HOST_WIDE_INT) GET_MODE_BITSIZE (mode))))
7199 /* If the shift count is a constant and we can do arithmetic in
7200 the mode of the shift, refine which bits we need. Otherwise, use the
7201 conservative form of the mask. */
7202 if (GET_CODE (XEXP (x, 1)) == CONST_INT
7203 && INTVAL (XEXP (x, 1)) >= 0
7204 && INTVAL (XEXP (x, 1)) < GET_MODE_BITSIZE (op_mode)
7205 && GET_MODE_BITSIZE (op_mode) <= HOST_BITS_PER_WIDE_INT)
7206 mask >>= INTVAL (XEXP (x, 1));
7210 op0 = gen_lowpart (op_mode,
7211 force_to_mode (XEXP (x, 0), op_mode,
7212 mask, reg, next_select));
7214 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0))
7215 x = simplify_gen_binary (code, op_mode, op0, XEXP (x, 1));
7219 /* Here we can only do something if the shift count is a constant,
7220 this shift constant is valid for the host, and we can do arithmetic
7223 if (GET_CODE (XEXP (x, 1)) == CONST_INT
7224 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT
7225 && GET_MODE_BITSIZE (op_mode) <= HOST_BITS_PER_WIDE_INT)
7227 rtx inner = XEXP (x, 0);
7228 unsigned HOST_WIDE_INT inner_mask;
7230 /* Select the mask of the bits we need for the shift operand. */
7231 inner_mask = mask << INTVAL (XEXP (x, 1));
7233 /* We can only change the mode of the shift if we can do arithmetic
7234 in the mode of the shift and INNER_MASK is no wider than the
7235 width of X's mode. */
7236 if ((inner_mask & ~GET_MODE_MASK (GET_MODE (x))) != 0)
7237 op_mode = GET_MODE (x);
7239 inner = force_to_mode (inner, op_mode, inner_mask, reg, next_select);
7241 if (GET_MODE (x) != op_mode || inner != XEXP (x, 0))
7242 x = simplify_gen_binary (LSHIFTRT, op_mode, inner, XEXP (x, 1));
7245 /* If we have (and (lshiftrt FOO C1) C2) where the combination of the
7246 shift and AND produces only copies of the sign bit (C2 is one less
7247 than a power of two), we can do this with just a shift. */
7249 if (GET_CODE (x) == LSHIFTRT
7250 && GET_CODE (XEXP (x, 1)) == CONST_INT
7251 /* The shift puts one of the sign bit copies in the least significant
7253 && ((INTVAL (XEXP (x, 1))
7254 + num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0))))
7255 >= GET_MODE_BITSIZE (GET_MODE (x)))
7256 && exact_log2 (mask + 1) >= 0
7257 /* Number of bits left after the shift must be more than the mask
7259 && ((INTVAL (XEXP (x, 1)) + exact_log2 (mask + 1))
7260 <= GET_MODE_BITSIZE (GET_MODE (x)))
7261 /* Must be more sign bit copies than the mask needs. */
7262 && ((int) num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
7263 >= exact_log2 (mask + 1)))
7264 x = simplify_gen_binary (LSHIFTRT, GET_MODE (x), XEXP (x, 0),
7265 GEN_INT (GET_MODE_BITSIZE (GET_MODE (x))
7266 - exact_log2 (mask + 1)));
7271 /* If we are just looking for the sign bit, we don't need this shift at
7272 all, even if it has a variable count. */
7273 if (GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
7274 && (mask == ((unsigned HOST_WIDE_INT) 1
7275 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
7276 return force_to_mode (XEXP (x, 0), mode, mask, reg, next_select);
7278 /* If this is a shift by a constant, get a mask that contains those bits
7279 that are not copies of the sign bit. We then have two cases: If
7280 MASK only includes those bits, this can be a logical shift, which may
7281 allow simplifications. If MASK is a single-bit field not within
7282 those bits, we are requesting a copy of the sign bit and hence can
7283 shift the sign bit to the appropriate location. */
7285 if (GET_CODE (XEXP (x, 1)) == CONST_INT && INTVAL (XEXP (x, 1)) >= 0
7286 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT)
7290 /* If the considered data is wider than HOST_WIDE_INT, we can't
7291 represent a mask for all its bits in a single scalar.
7292 But we only care about the lower bits, so calculate these. */
7294 if (GET_MODE_BITSIZE (GET_MODE (x)) > HOST_BITS_PER_WIDE_INT)
7296 nonzero = ~(HOST_WIDE_INT) 0;
7298 /* GET_MODE_BITSIZE (GET_MODE (x)) - INTVAL (XEXP (x, 1))
7299 is the number of bits a full-width mask would have set.
7300 We need only shift if these are fewer than nonzero can
7301 hold. If not, we must keep all bits set in nonzero. */
7303 if (GET_MODE_BITSIZE (GET_MODE (x)) - INTVAL (XEXP (x, 1))
7304 < HOST_BITS_PER_WIDE_INT)
7305 nonzero >>= INTVAL (XEXP (x, 1))
7306 + HOST_BITS_PER_WIDE_INT
7307 - GET_MODE_BITSIZE (GET_MODE (x)) ;
7311 nonzero = GET_MODE_MASK (GET_MODE (x));
7312 nonzero >>= INTVAL (XEXP (x, 1));
7315 if ((mask & ~nonzero) == 0
7316 || (i = exact_log2 (mask)) >= 0)
7318 x = simplify_shift_const
7319 (x, LSHIFTRT, GET_MODE (x), XEXP (x, 0),
7320 i < 0 ? INTVAL (XEXP (x, 1))
7321 : GET_MODE_BITSIZE (GET_MODE (x)) - 1 - i);
7323 if (GET_CODE (x) != ASHIFTRT)
7324 return force_to_mode (x, mode, mask, reg, next_select);
7328 /* If MASK is 1, convert this to an LSHIFTRT. This can be done
7329 even if the shift count isn't a constant. */
7331 x = simplify_gen_binary (LSHIFTRT, GET_MODE (x),
7332 XEXP (x, 0), XEXP (x, 1));
7336 /* If this is a zero- or sign-extension operation that just affects bits
7337 we don't care about, remove it. Be sure the call above returned
7338 something that is still a shift. */
7340 if ((GET_CODE (x) == LSHIFTRT || GET_CODE (x) == ASHIFTRT)
7341 && GET_CODE (XEXP (x, 1)) == CONST_INT
7342 && INTVAL (XEXP (x, 1)) >= 0
7343 && (INTVAL (XEXP (x, 1))
7344 <= GET_MODE_BITSIZE (GET_MODE (x)) - (floor_log2 (mask) + 1))
7345 && GET_CODE (XEXP (x, 0)) == ASHIFT
7346 && XEXP (XEXP (x, 0), 1) == XEXP (x, 1))
7347 return force_to_mode (XEXP (XEXP (x, 0), 0), mode, mask,
7354 /* If the shift count is constant and we can do computations
7355 in the mode of X, compute where the bits we care about are.
7356 Otherwise, we can't do anything. Don't change the mode of
7357 the shift or propagate MODE into the shift, though. */
7358 if (GET_CODE (XEXP (x, 1)) == CONST_INT
7359 && INTVAL (XEXP (x, 1)) >= 0)
7361 temp = simplify_binary_operation (code == ROTATE ? ROTATERT : ROTATE,
7362 GET_MODE (x), GEN_INT (mask),
7364 if (temp && GET_CODE (temp) == CONST_INT)
7366 force_to_mode (XEXP (x, 0), GET_MODE (x),
7367 INTVAL (temp), reg, next_select));
7372 /* If we just want the low-order bit, the NEG isn't needed since it
7373 won't change the low-order bit. */
7375 return force_to_mode (XEXP (x, 0), mode, mask, reg, just_select);
7377 /* We need any bits less significant than the most significant bit in
7378 MASK since carries from those bits will affect the bits we are
7384 /* (not FOO) is (xor FOO CONST), so if FOO is an LSHIFTRT, we can do the
7385 same as the XOR case above. Ensure that the constant we form is not
7386 wider than the mode of X. */
7388 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
7389 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
7390 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
7391 && (INTVAL (XEXP (XEXP (x, 0), 1)) + floor_log2 (mask)
7392 < GET_MODE_BITSIZE (GET_MODE (x)))
7393 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT)
7395 temp = gen_int_mode (mask << INTVAL (XEXP (XEXP (x, 0), 1)),
7397 temp = simplify_gen_binary (XOR, GET_MODE (x),
7398 XEXP (XEXP (x, 0), 0), temp);
7399 x = simplify_gen_binary (LSHIFTRT, GET_MODE (x),
7400 temp, XEXP (XEXP (x, 0), 1));
7402 return force_to_mode (x, mode, mask, reg, next_select);
7405 /* (and (not FOO) CONST) is (not (or FOO (not CONST))), so we must
7406 use the full mask inside the NOT. */
7410 op0 = gen_lowpart (op_mode,
7411 force_to_mode (XEXP (x, 0), mode, mask,
7413 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0))
7414 x = simplify_gen_unary (code, op_mode, op0, op_mode);
7418 /* (and (ne FOO 0) CONST) can be (and FOO CONST) if CONST is included
7419 in STORE_FLAG_VALUE and FOO has a single bit that might be nonzero,
7420 which is equal to STORE_FLAG_VALUE. */
7421 if ((mask & ~STORE_FLAG_VALUE) == 0 && XEXP (x, 1) == const0_rtx
7422 && GET_MODE (XEXP (x, 0)) == mode
7423 && exact_log2 (nonzero_bits (XEXP (x, 0), mode)) >= 0
7424 && (nonzero_bits (XEXP (x, 0), mode)
7425 == (unsigned HOST_WIDE_INT) STORE_FLAG_VALUE))
7426 return force_to_mode (XEXP (x, 0), mode, mask, reg, next_select);
7431 /* We have no way of knowing if the IF_THEN_ELSE can itself be
7432 written in a narrower mode. We play it safe and do not do so. */
7435 gen_lowpart (GET_MODE (x),
7436 force_to_mode (XEXP (x, 1), mode,
7437 mask, reg, next_select)));
7439 gen_lowpart (GET_MODE (x),
7440 force_to_mode (XEXP (x, 2), mode,
7441 mask, reg, next_select)));
7448 /* Ensure we return a value of the proper mode. */
7449 return gen_lowpart (mode, x);
7452 /* Return nonzero if X is an expression that has one of two values depending on
7453 whether some other value is zero or nonzero. In that case, we return the
7454 value that is being tested, *PTRUE is set to the value if the rtx being
7455 returned has a nonzero value, and *PFALSE is set to the other alternative.
7457 If we return zero, we set *PTRUE and *PFALSE to X. */
7460 if_then_else_cond (rtx x, rtx *ptrue, rtx *pfalse)
7462 enum machine_mode mode = GET_MODE (x);
7463 enum rtx_code code = GET_CODE (x);
7464 rtx cond0, cond1, true0, true1, false0, false1;
7465 unsigned HOST_WIDE_INT nz;
7467 /* If we are comparing a value against zero, we are done. */
7468 if ((code == NE || code == EQ)
7469 && XEXP (x, 1) == const0_rtx)
7471 *ptrue = (code == NE) ? const_true_rtx : const0_rtx;
7472 *pfalse = (code == NE) ? const0_rtx : const_true_rtx;
7476 /* If this is a unary operation whose operand has one of two values, apply
7477 our opcode to compute those values. */
7478 else if (UNARY_P (x)
7479 && (cond0 = if_then_else_cond (XEXP (x, 0), &true0, &false0)) != 0)
7481 *ptrue = simplify_gen_unary (code, mode, true0, GET_MODE (XEXP (x, 0)));
7482 *pfalse = simplify_gen_unary (code, mode, false0,
7483 GET_MODE (XEXP (x, 0)));
7487 /* If this is a COMPARE, do nothing, since the IF_THEN_ELSE we would
7488 make can't possibly match and would suppress other optimizations. */
7489 else if (code == COMPARE)
7492 /* If this is a binary operation, see if either side has only one of two
7493 values. If either one does or if both do and they are conditional on
7494 the same value, compute the new true and false values. */
7495 else if (BINARY_P (x))
7497 cond0 = if_then_else_cond (XEXP (x, 0), &true0, &false0);
7498 cond1 = if_then_else_cond (XEXP (x, 1), &true1, &false1);
7500 if ((cond0 != 0 || cond1 != 0)
7501 && ! (cond0 != 0 && cond1 != 0 && ! rtx_equal_p (cond0, cond1)))
7503 /* If if_then_else_cond returned zero, then true/false are the
7504 same rtl. We must copy one of them to prevent invalid rtl
7507 true0 = copy_rtx (true0);
7508 else if (cond1 == 0)
7509 true1 = copy_rtx (true1);
7511 if (COMPARISON_P (x))
7513 *ptrue = simplify_gen_relational (code, mode, VOIDmode,
7515 *pfalse = simplify_gen_relational (code, mode, VOIDmode,
7520 *ptrue = simplify_gen_binary (code, mode, true0, true1);
7521 *pfalse = simplify_gen_binary (code, mode, false0, false1);
7524 return cond0 ? cond0 : cond1;
7527 /* See if we have PLUS, IOR, XOR, MINUS or UMAX, where one of the
7528 operands is zero when the other is nonzero, and vice-versa,
7529 and STORE_FLAG_VALUE is 1 or -1. */
7531 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
7532 && (code == PLUS || code == IOR || code == XOR || code == MINUS
7534 && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT)
7536 rtx op0 = XEXP (XEXP (x, 0), 1);
7537 rtx op1 = XEXP (XEXP (x, 1), 1);
7539 cond0 = XEXP (XEXP (x, 0), 0);
7540 cond1 = XEXP (XEXP (x, 1), 0);
7542 if (COMPARISON_P (cond0)
7543 && COMPARISON_P (cond1)
7544 && ((GET_CODE (cond0) == reversed_comparison_code (cond1, NULL)
7545 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0))
7546 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1)))
7547 || ((swap_condition (GET_CODE (cond0))
7548 == reversed_comparison_code (cond1, NULL))
7549 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1))
7550 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0))))
7551 && ! side_effects_p (x))
7553 *ptrue = simplify_gen_binary (MULT, mode, op0, const_true_rtx);
7554 *pfalse = simplify_gen_binary (MULT, mode,
7556 ? simplify_gen_unary (NEG, mode,
7564 /* Similarly for MULT, AND and UMIN, except that for these the result
7566 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
7567 && (code == MULT || code == AND || code == UMIN)
7568 && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT)
7570 cond0 = XEXP (XEXP (x, 0), 0);
7571 cond1 = XEXP (XEXP (x, 1), 0);
7573 if (COMPARISON_P (cond0)
7574 && COMPARISON_P (cond1)
7575 && ((GET_CODE (cond0) == reversed_comparison_code (cond1, NULL)
7576 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0))
7577 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1)))
7578 || ((swap_condition (GET_CODE (cond0))
7579 == reversed_comparison_code (cond1, NULL))
7580 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1))
7581 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0))))
7582 && ! side_effects_p (x))
7584 *ptrue = *pfalse = const0_rtx;
7590 else if (code == IF_THEN_ELSE)
7592 /* If we have IF_THEN_ELSE already, extract the condition and
7593 canonicalize it if it is NE or EQ. */
7594 cond0 = XEXP (x, 0);
7595 *ptrue = XEXP (x, 1), *pfalse = XEXP (x, 2);
7596 if (GET_CODE (cond0) == NE && XEXP (cond0, 1) == const0_rtx)
7597 return XEXP (cond0, 0);
7598 else if (GET_CODE (cond0) == EQ && XEXP (cond0, 1) == const0_rtx)
7600 *ptrue = XEXP (x, 2), *pfalse = XEXP (x, 1);
7601 return XEXP (cond0, 0);
7607 /* If X is a SUBREG, we can narrow both the true and false values
7608 if the inner expression, if there is a condition. */
7609 else if (code == SUBREG
7610 && 0 != (cond0 = if_then_else_cond (SUBREG_REG (x),
7613 true0 = simplify_gen_subreg (mode, true0,
7614 GET_MODE (SUBREG_REG (x)), SUBREG_BYTE (x));
7615 false0 = simplify_gen_subreg (mode, false0,
7616 GET_MODE (SUBREG_REG (x)), SUBREG_BYTE (x));
7617 if (true0 && false0)
7625 /* If X is a constant, this isn't special and will cause confusions
7626 if we treat it as such. Likewise if it is equivalent to a constant. */
7627 else if (CONSTANT_P (x)
7628 || ((cond0 = get_last_value (x)) != 0 && CONSTANT_P (cond0)))
7631 /* If we're in BImode, canonicalize on 0 and STORE_FLAG_VALUE, as that
7632 will be least confusing to the rest of the compiler. */
7633 else if (mode == BImode)
7635 *ptrue = GEN_INT (STORE_FLAG_VALUE), *pfalse = const0_rtx;
7639 /* If X is known to be either 0 or -1, those are the true and
7640 false values when testing X. */
7641 else if (x == constm1_rtx || x == const0_rtx
7642 || (mode != VOIDmode
7643 && num_sign_bit_copies (x, mode) == GET_MODE_BITSIZE (mode)))
7645 *ptrue = constm1_rtx, *pfalse = const0_rtx;
7649 /* Likewise for 0 or a single bit. */
7650 else if (SCALAR_INT_MODE_P (mode)
7651 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
7652 && exact_log2 (nz = nonzero_bits (x, mode)) >= 0)
7654 *ptrue = gen_int_mode (nz, mode), *pfalse = const0_rtx;
7658 /* Otherwise fail; show no condition with true and false values the same. */
7659 *ptrue = *pfalse = x;
7663 /* Return the value of expression X given the fact that condition COND
7664 is known to be true when applied to REG as its first operand and VAL
7665 as its second. X is known to not be shared and so can be modified in
7668 We only handle the simplest cases, and specifically those cases that
7669 arise with IF_THEN_ELSE expressions. */
7672 known_cond (rtx x, enum rtx_code cond, rtx reg, rtx val)
7674 enum rtx_code code = GET_CODE (x);
7679 if (side_effects_p (x))
7682 /* If either operand of the condition is a floating point value,
7683 then we have to avoid collapsing an EQ comparison. */
7685 && rtx_equal_p (x, reg)
7686 && ! FLOAT_MODE_P (GET_MODE (x))
7687 && ! FLOAT_MODE_P (GET_MODE (val)))
7690 if (cond == UNEQ && rtx_equal_p (x, reg))
7693 /* If X is (abs REG) and we know something about REG's relationship
7694 with zero, we may be able to simplify this. */
7696 if (code == ABS && rtx_equal_p (XEXP (x, 0), reg) && val == const0_rtx)
7699 case GE: case GT: case EQ:
7702 return simplify_gen_unary (NEG, GET_MODE (XEXP (x, 0)),
7704 GET_MODE (XEXP (x, 0)));
7709 /* The only other cases we handle are MIN, MAX, and comparisons if the
7710 operands are the same as REG and VAL. */
7712 else if (COMPARISON_P (x) || COMMUTATIVE_ARITH_P (x))
7714 if (rtx_equal_p (XEXP (x, 0), val))
7715 cond = swap_condition (cond), temp = val, val = reg, reg = temp;
7717 if (rtx_equal_p (XEXP (x, 0), reg) && rtx_equal_p (XEXP (x, 1), val))
7719 if (COMPARISON_P (x))
7721 if (comparison_dominates_p (cond, code))
7722 return const_true_rtx;
7724 code = reversed_comparison_code (x, NULL);
7726 && comparison_dominates_p (cond, code))
7731 else if (code == SMAX || code == SMIN
7732 || code == UMIN || code == UMAX)
7734 int unsignedp = (code == UMIN || code == UMAX);
7736 /* Do not reverse the condition when it is NE or EQ.
7737 This is because we cannot conclude anything about
7738 the value of 'SMAX (x, y)' when x is not equal to y,
7739 but we can when x equals y. */
7740 if ((code == SMAX || code == UMAX)
7741 && ! (cond == EQ || cond == NE))
7742 cond = reverse_condition (cond);
7747 return unsignedp ? x : XEXP (x, 1);
7749 return unsignedp ? x : XEXP (x, 0);
7751 return unsignedp ? XEXP (x, 1) : x;
7753 return unsignedp ? XEXP (x, 0) : x;
7760 else if (code == SUBREG)
7762 enum machine_mode inner_mode = GET_MODE (SUBREG_REG (x));
7763 rtx new, r = known_cond (SUBREG_REG (x), cond, reg, val);
7765 if (SUBREG_REG (x) != r)
7767 /* We must simplify subreg here, before we lose track of the
7768 original inner_mode. */
7769 new = simplify_subreg (GET_MODE (x), r,
7770 inner_mode, SUBREG_BYTE (x));
7774 SUBST (SUBREG_REG (x), r);
7779 /* We don't have to handle SIGN_EXTEND here, because even in the
7780 case of replacing something with a modeless CONST_INT, a
7781 CONST_INT is already (supposed to be) a valid sign extension for
7782 its narrower mode, which implies it's already properly
7783 sign-extended for the wider mode. Now, for ZERO_EXTEND, the
7784 story is different. */
7785 else if (code == ZERO_EXTEND)
7787 enum machine_mode inner_mode = GET_MODE (XEXP (x, 0));
7788 rtx new, r = known_cond (XEXP (x, 0), cond, reg, val);
7790 if (XEXP (x, 0) != r)
7792 /* We must simplify the zero_extend here, before we lose
7793 track of the original inner_mode. */
7794 new = simplify_unary_operation (ZERO_EXTEND, GET_MODE (x),
7799 SUBST (XEXP (x, 0), r);
7805 fmt = GET_RTX_FORMAT (code);
7806 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
7809 SUBST (XEXP (x, i), known_cond (XEXP (x, i), cond, reg, val));
7810 else if (fmt[i] == 'E')
7811 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
7812 SUBST (XVECEXP (x, i, j), known_cond (XVECEXP (x, i, j),
7819 /* See if X and Y are equal for the purposes of seeing if we can rewrite an
7820 assignment as a field assignment. */
7823 rtx_equal_for_field_assignment_p (rtx x, rtx y)
7825 if (x == y || rtx_equal_p (x, y))
7828 if (x == 0 || y == 0 || GET_MODE (x) != GET_MODE (y))
7831 /* Check for a paradoxical SUBREG of a MEM compared with the MEM.
7832 Note that all SUBREGs of MEM are paradoxical; otherwise they
7833 would have been rewritten. */
7834 if (MEM_P (x) && GET_CODE (y) == SUBREG
7835 && MEM_P (SUBREG_REG (y))
7836 && rtx_equal_p (SUBREG_REG (y),
7837 gen_lowpart (GET_MODE (SUBREG_REG (y)), x)))
7840 if (MEM_P (y) && GET_CODE (x) == SUBREG
7841 && MEM_P (SUBREG_REG (x))
7842 && rtx_equal_p (SUBREG_REG (x),
7843 gen_lowpart (GET_MODE (SUBREG_REG (x)), y)))
7846 /* We used to see if get_last_value of X and Y were the same but that's
7847 not correct. In one direction, we'll cause the assignment to have
7848 the wrong destination and in the case, we'll import a register into this
7849 insn that might have already have been dead. So fail if none of the
7850 above cases are true. */
7854 /* See if X, a SET operation, can be rewritten as a bit-field assignment.
7855 Return that assignment if so.
7857 We only handle the most common cases. */
7860 make_field_assignment (rtx x)
7862 rtx dest = SET_DEST (x);
7863 rtx src = SET_SRC (x);
7868 unsigned HOST_WIDE_INT len;
7870 enum machine_mode mode;
7872 /* If SRC was (and (not (ashift (const_int 1) POS)) DEST), this is
7873 a clear of a one-bit field. We will have changed it to
7874 (and (rotate (const_int -2) POS) DEST), so check for that. Also check
7877 if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == ROTATE
7878 && GET_CODE (XEXP (XEXP (src, 0), 0)) == CONST_INT
7879 && INTVAL (XEXP (XEXP (src, 0), 0)) == -2
7880 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
7882 assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1),
7885 return gen_rtx_SET (VOIDmode, assign, const0_rtx);
7889 if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == SUBREG
7890 && subreg_lowpart_p (XEXP (src, 0))
7891 && (GET_MODE_SIZE (GET_MODE (XEXP (src, 0)))
7892 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (src, 0)))))
7893 && GET_CODE (SUBREG_REG (XEXP (src, 0))) == ROTATE
7894 && GET_CODE (XEXP (SUBREG_REG (XEXP (src, 0)), 0)) == CONST_INT
7895 && INTVAL (XEXP (SUBREG_REG (XEXP (src, 0)), 0)) == -2
7896 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
7898 assign = make_extraction (VOIDmode, dest, 0,
7899 XEXP (SUBREG_REG (XEXP (src, 0)), 1),
7902 return gen_rtx_SET (VOIDmode, assign, const0_rtx);
7906 /* If SRC is (ior (ashift (const_int 1) POS) DEST), this is a set of a
7908 if (GET_CODE (src) == IOR && GET_CODE (XEXP (src, 0)) == ASHIFT
7909 && XEXP (XEXP (src, 0), 0) == const1_rtx
7910 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
7912 assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1),
7915 return gen_rtx_SET (VOIDmode, assign, const1_rtx);
7919 /* If DEST is already a field assignment, i.e. ZERO_EXTRACT, and the
7920 SRC is an AND with all bits of that field set, then we can discard
7922 if (GET_CODE (dest) == ZERO_EXTRACT
7923 && GET_CODE (XEXP (dest, 1)) == CONST_INT
7924 && GET_CODE (src) == AND
7925 && GET_CODE (XEXP (src, 1)) == CONST_INT)
7927 HOST_WIDE_INT width = INTVAL (XEXP (dest, 1));
7928 unsigned HOST_WIDE_INT and_mask = INTVAL (XEXP (src, 1));
7929 unsigned HOST_WIDE_INT ze_mask;
7931 if (width >= HOST_BITS_PER_WIDE_INT)
7934 ze_mask = ((unsigned HOST_WIDE_INT)1 << width) - 1;
7936 /* Complete overlap. We can remove the source AND. */
7937 if ((and_mask & ze_mask) == ze_mask)
7938 return gen_rtx_SET (VOIDmode, dest, XEXP (src, 0));
7940 /* Partial overlap. We can reduce the source AND. */
7941 if ((and_mask & ze_mask) != and_mask)
7943 mode = GET_MODE (src);
7944 src = gen_rtx_AND (mode, XEXP (src, 0),
7945 gen_int_mode (and_mask & ze_mask, mode));
7946 return gen_rtx_SET (VOIDmode, dest, src);
7950 /* The other case we handle is assignments into a constant-position
7951 field. They look like (ior/xor (and DEST C1) OTHER). If C1 represents
7952 a mask that has all one bits except for a group of zero bits and
7953 OTHER is known to have zeros where C1 has ones, this is such an
7954 assignment. Compute the position and length from C1. Shift OTHER
7955 to the appropriate position, force it to the required mode, and
7956 make the extraction. Check for the AND in both operands. */
7958 if (GET_CODE (src) != IOR && GET_CODE (src) != XOR)
7961 rhs = expand_compound_operation (XEXP (src, 0));
7962 lhs = expand_compound_operation (XEXP (src, 1));
7964 if (GET_CODE (rhs) == AND
7965 && GET_CODE (XEXP (rhs, 1)) == CONST_INT
7966 && rtx_equal_for_field_assignment_p (XEXP (rhs, 0), dest))
7967 c1 = INTVAL (XEXP (rhs, 1)), other = lhs;
7968 else if (GET_CODE (lhs) == AND
7969 && GET_CODE (XEXP (lhs, 1)) == CONST_INT
7970 && rtx_equal_for_field_assignment_p (XEXP (lhs, 0), dest))
7971 c1 = INTVAL (XEXP (lhs, 1)), other = rhs;
7975 pos = get_pos_from_mask ((~c1) & GET_MODE_MASK (GET_MODE (dest)), &len);
7976 if (pos < 0 || pos + len > GET_MODE_BITSIZE (GET_MODE (dest))
7977 || GET_MODE_BITSIZE (GET_MODE (dest)) > HOST_BITS_PER_WIDE_INT
7978 || (c1 & nonzero_bits (other, GET_MODE (dest))) != 0)
7981 assign = make_extraction (VOIDmode, dest, pos, NULL_RTX, len, 1, 1, 0);
7985 /* The mode to use for the source is the mode of the assignment, or of
7986 what is inside a possible STRICT_LOW_PART. */
7987 mode = (GET_CODE (assign) == STRICT_LOW_PART
7988 ? GET_MODE (XEXP (assign, 0)) : GET_MODE (assign));
7990 /* Shift OTHER right POS places and make it the source, restricting it
7991 to the proper length and mode. */
7993 src = force_to_mode (simplify_shift_const (NULL_RTX, LSHIFTRT,
7994 GET_MODE (src), other, pos),
7996 GET_MODE_BITSIZE (mode) >= HOST_BITS_PER_WIDE_INT
7997 ? ~(unsigned HOST_WIDE_INT) 0
7998 : ((unsigned HOST_WIDE_INT) 1 << len) - 1,
8001 /* If SRC is masked by an AND that does not make a difference in
8002 the value being stored, strip it. */
8003 if (GET_CODE (assign) == ZERO_EXTRACT
8004 && GET_CODE (XEXP (assign, 1)) == CONST_INT
8005 && INTVAL (XEXP (assign, 1)) < HOST_BITS_PER_WIDE_INT
8006 && GET_CODE (src) == AND
8007 && GET_CODE (XEXP (src, 1)) == CONST_INT
8008 && ((unsigned HOST_WIDE_INT) INTVAL (XEXP (src, 1))
8009 == ((unsigned HOST_WIDE_INT) 1 << INTVAL (XEXP (assign, 1))) - 1))
8010 src = XEXP (src, 0);
8012 return gen_rtx_SET (VOIDmode, assign, src);
8015 /* See if X is of the form (+ (* a c) (* b c)) and convert to (* (+ a b) c)
8019 apply_distributive_law (rtx x)
8021 enum rtx_code code = GET_CODE (x);
8022 enum rtx_code inner_code;
8023 rtx lhs, rhs, other;
8026 /* Distributivity is not true for floating point as it can change the
8027 value. So we don't do it unless -funsafe-math-optimizations. */
8028 if (FLOAT_MODE_P (GET_MODE (x))
8029 && ! flag_unsafe_math_optimizations)
8032 /* The outer operation can only be one of the following: */
8033 if (code != IOR && code != AND && code != XOR
8034 && code != PLUS && code != MINUS)
8040 /* If either operand is a primitive we can't do anything, so get out
8042 if (OBJECT_P (lhs) || OBJECT_P (rhs))
8045 lhs = expand_compound_operation (lhs);
8046 rhs = expand_compound_operation (rhs);
8047 inner_code = GET_CODE (lhs);
8048 if (inner_code != GET_CODE (rhs))
8051 /* See if the inner and outer operations distribute. */
8058 /* These all distribute except over PLUS. */
8059 if (code == PLUS || code == MINUS)
8064 if (code != PLUS && code != MINUS)
8069 /* This is also a multiply, so it distributes over everything. */
8073 /* Non-paradoxical SUBREGs distributes over all operations, provided
8074 the inner modes and byte offsets are the same, this is an extraction
8075 of a low-order part, we don't convert an fp operation to int or
8076 vice versa, and we would not be converting a single-word
8077 operation into a multi-word operation. The latter test is not
8078 required, but it prevents generating unneeded multi-word operations.
8079 Some of the previous tests are redundant given the latter test, but
8080 are retained because they are required for correctness.
8082 We produce the result slightly differently in this case. */
8084 if (GET_MODE (SUBREG_REG (lhs)) != GET_MODE (SUBREG_REG (rhs))
8085 || SUBREG_BYTE (lhs) != SUBREG_BYTE (rhs)
8086 || ! subreg_lowpart_p (lhs)
8087 || (GET_MODE_CLASS (GET_MODE (lhs))
8088 != GET_MODE_CLASS (GET_MODE (SUBREG_REG (lhs))))
8089 || (GET_MODE_SIZE (GET_MODE (lhs))
8090 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs))))
8091 || GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs))) > UNITS_PER_WORD)
8094 tem = simplify_gen_binary (code, GET_MODE (SUBREG_REG (lhs)),
8095 SUBREG_REG (lhs), SUBREG_REG (rhs));
8096 return gen_lowpart (GET_MODE (x), tem);
8102 /* Set LHS and RHS to the inner operands (A and B in the example
8103 above) and set OTHER to the common operand (C in the example).
8104 There is only one way to do this unless the inner operation is
8106 if (COMMUTATIVE_ARITH_P (lhs)
8107 && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 0)))
8108 other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 1);
8109 else if (COMMUTATIVE_ARITH_P (lhs)
8110 && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 1)))
8111 other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 0);
8112 else if (COMMUTATIVE_ARITH_P (lhs)
8113 && rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 0)))
8114 other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 1);
8115 else if (rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 1)))
8116 other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 0);
8120 /* Form the new inner operation, seeing if it simplifies first. */
8121 tem = simplify_gen_binary (code, GET_MODE (x), lhs, rhs);
8123 /* There is one exception to the general way of distributing:
8124 (a | c) ^ (b | c) -> (a ^ b) & ~c */
8125 if (code == XOR && inner_code == IOR)
8128 other = simplify_gen_unary (NOT, GET_MODE (x), other, GET_MODE (x));
8131 /* We may be able to continuing distributing the result, so call
8132 ourselves recursively on the inner operation before forming the
8133 outer operation, which we return. */
8134 return simplify_gen_binary (inner_code, GET_MODE (x),
8135 apply_distributive_law (tem), other);
8138 /* See if X is of the form (* (+ A B) C), and if so convert to
8139 (+ (* A C) (* B C)) and try to simplify.
8141 Most of the time, this results in no change. However, if some of
8142 the operands are the same or inverses of each other, simplifications
8145 For example, (and (ior A B) (not B)) can occur as the result of
8146 expanding a bit field assignment. When we apply the distributive
8147 law to this, we get (ior (and (A (not B))) (and (B (not B)))),
8148 which then simplifies to (and (A (not B))).
8150 Note that no checks happen on the validity of applying the inverse
8151 distributive law. This is pointless since we can do it in the
8152 few places where this routine is called.
8154 N is the index of the term that is decomposed (the arithmetic operation,
8155 i.e. (+ A B) in the first example above). !N is the index of the term that
8156 is distributed, i.e. of C in the first example above. */
8158 distribute_and_simplify_rtx (rtx x, int n)
8160 enum machine_mode mode;
8161 enum rtx_code outer_code, inner_code;
8162 rtx decomposed, distributed, inner_op0, inner_op1, new_op0, new_op1, tmp;
8164 decomposed = XEXP (x, n);
8165 if (!ARITHMETIC_P (decomposed))
8168 mode = GET_MODE (x);
8169 outer_code = GET_CODE (x);
8170 distributed = XEXP (x, !n);
8172 inner_code = GET_CODE (decomposed);
8173 inner_op0 = XEXP (decomposed, 0);
8174 inner_op1 = XEXP (decomposed, 1);
8176 /* Special case (and (xor B C) (not A)), which is equivalent to
8177 (xor (ior A B) (ior A C)) */
8178 if (outer_code == AND && inner_code == XOR && GET_CODE (distributed) == NOT)
8180 distributed = XEXP (distributed, 0);
8186 /* Distribute the second term. */
8187 new_op0 = simplify_gen_binary (outer_code, mode, inner_op0, distributed);
8188 new_op1 = simplify_gen_binary (outer_code, mode, inner_op1, distributed);
8192 /* Distribute the first term. */
8193 new_op0 = simplify_gen_binary (outer_code, mode, distributed, inner_op0);
8194 new_op1 = simplify_gen_binary (outer_code, mode, distributed, inner_op1);
8197 tmp = apply_distributive_law (simplify_gen_binary (inner_code, mode,
8199 if (GET_CODE (tmp) != outer_code
8200 && rtx_cost (tmp, SET) < rtx_cost (x, SET))
8206 /* We have X, a logical `and' of VAROP with the constant CONSTOP, to be done
8209 Return an equivalent form, if different from X. Otherwise, return X. If
8210 X is zero, we are to always construct the equivalent form. */
8213 simplify_and_const_int (rtx x, enum machine_mode mode, rtx varop,
8214 unsigned HOST_WIDE_INT constop)
8216 unsigned HOST_WIDE_INT nonzero;
8219 /* Simplify VAROP knowing that we will be only looking at some of the
8222 Note by passing in CONSTOP, we guarantee that the bits not set in
8223 CONSTOP are not significant and will never be examined. We must
8224 ensure that is the case by explicitly masking out those bits
8225 before returning. */
8226 varop = force_to_mode (varop, mode, constop, NULL_RTX, 0);
8228 /* If VAROP is a CLOBBER, we will fail so return it. */
8229 if (GET_CODE (varop) == CLOBBER)
8232 /* If VAROP is a CONST_INT, then we need to apply the mask in CONSTOP
8233 to VAROP and return the new constant. */
8234 if (GET_CODE (varop) == CONST_INT)
8235 return gen_int_mode (INTVAL (varop) & constop, mode);
8237 /* See what bits may be nonzero in VAROP. Unlike the general case of
8238 a call to nonzero_bits, here we don't care about bits outside
8241 nonzero = nonzero_bits (varop, mode) & GET_MODE_MASK (mode);
8243 /* Turn off all bits in the constant that are known to already be zero.
8244 Thus, if the AND isn't needed at all, we will have CONSTOP == NONZERO_BITS
8245 which is tested below. */
8249 /* If we don't have any bits left, return zero. */
8253 /* If VAROP is a NEG of something known to be zero or 1 and CONSTOP is
8254 a power of two, we can replace this with an ASHIFT. */
8255 if (GET_CODE (varop) == NEG && nonzero_bits (XEXP (varop, 0), mode) == 1
8256 && (i = exact_log2 (constop)) >= 0)
8257 return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (varop, 0), i);
8259 /* If VAROP is an IOR or XOR, apply the AND to both branches of the IOR
8260 or XOR, then try to apply the distributive law. This may eliminate
8261 operations if either branch can be simplified because of the AND.
8262 It may also make some cases more complex, but those cases probably
8263 won't match a pattern either with or without this. */
8265 if (GET_CODE (varop) == IOR || GET_CODE (varop) == XOR)
8269 apply_distributive_law
8270 (simplify_gen_binary (GET_CODE (varop), GET_MODE (varop),
8271 simplify_and_const_int (NULL_RTX,
8275 simplify_and_const_int (NULL_RTX,
8280 /* If VAROP is PLUS, and the constant is a mask of low bite, distribute
8281 the AND and see if one of the operands simplifies to zero. If so, we
8282 may eliminate it. */
8284 if (GET_CODE (varop) == PLUS
8285 && exact_log2 (constop + 1) >= 0)
8289 o0 = simplify_and_const_int (NULL_RTX, mode, XEXP (varop, 0), constop);
8290 o1 = simplify_and_const_int (NULL_RTX, mode, XEXP (varop, 1), constop);
8291 if (o0 == const0_rtx)
8293 if (o1 == const0_rtx)
8297 /* Get VAROP in MODE. Try to get a SUBREG if not. Don't make a new SUBREG
8298 if we already had one (just check for the simplest cases). */
8299 if (x && GET_CODE (XEXP (x, 0)) == SUBREG
8300 && GET_MODE (XEXP (x, 0)) == mode
8301 && SUBREG_REG (XEXP (x, 0)) == varop)
8302 varop = XEXP (x, 0);
8304 varop = gen_lowpart (mode, varop);
8306 /* If we can't make the SUBREG, try to return what we were given. */
8307 if (GET_CODE (varop) == CLOBBER)
8308 return x ? x : varop;
8310 /* If we are only masking insignificant bits, return VAROP. */
8311 if (constop == nonzero)
8315 /* Otherwise, return an AND. */
8316 constop = trunc_int_for_mode (constop, mode);
8317 /* See how much, if any, of X we can use. */
8318 if (x == 0 || GET_CODE (x) != AND || GET_MODE (x) != mode)
8319 x = simplify_gen_binary (AND, mode, varop, GEN_INT (constop));
8323 if (GET_CODE (XEXP (x, 1)) != CONST_INT
8324 || (unsigned HOST_WIDE_INT) INTVAL (XEXP (x, 1)) != constop)
8325 SUBST (XEXP (x, 1), GEN_INT (constop));
8327 SUBST (XEXP (x, 0), varop);
8334 /* Given a REG, X, compute which bits in X can be nonzero.
8335 We don't care about bits outside of those defined in MODE.
8337 For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is
8338 a shift, AND, or zero_extract, we can do better. */
8341 reg_nonzero_bits_for_combine (rtx x, enum machine_mode mode,
8342 rtx known_x ATTRIBUTE_UNUSED,
8343 enum machine_mode known_mode ATTRIBUTE_UNUSED,
8344 unsigned HOST_WIDE_INT known_ret ATTRIBUTE_UNUSED,
8345 unsigned HOST_WIDE_INT *nonzero)
8349 /* If X is a register whose nonzero bits value is current, use it.
8350 Otherwise, if X is a register whose value we can find, use that
8351 value. Otherwise, use the previously-computed global nonzero bits
8352 for this register. */
8354 if (reg_stat[REGNO (x)].last_set_value != 0
8355 && (reg_stat[REGNO (x)].last_set_mode == mode
8356 || (GET_MODE_CLASS (reg_stat[REGNO (x)].last_set_mode) == MODE_INT
8357 && GET_MODE_CLASS (mode) == MODE_INT))
8358 && (reg_stat[REGNO (x)].last_set_label == label_tick
8359 || (REGNO (x) >= FIRST_PSEUDO_REGISTER
8360 && REG_N_SETS (REGNO (x)) == 1
8361 && ! REGNO_REG_SET_P
8362 (ENTRY_BLOCK_PTR->next_bb->il.rtl->global_live_at_start,
8364 && INSN_CUID (reg_stat[REGNO (x)].last_set) < subst_low_cuid)
8366 *nonzero &= reg_stat[REGNO (x)].last_set_nonzero_bits;
8370 tem = get_last_value (x);
8374 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
8375 /* If X is narrower than MODE and TEM is a non-negative
8376 constant that would appear negative in the mode of X,
8377 sign-extend it for use in reg_nonzero_bits because some
8378 machines (maybe most) will actually do the sign-extension
8379 and this is the conservative approach.
8381 ??? For 2.5, try to tighten up the MD files in this regard
8382 instead of this kludge. */
8384 if (GET_MODE_BITSIZE (GET_MODE (x)) < GET_MODE_BITSIZE (mode)
8385 && GET_CODE (tem) == CONST_INT
8387 && 0 != (INTVAL (tem)
8388 & ((HOST_WIDE_INT) 1
8389 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
8390 tem = GEN_INT (INTVAL (tem)
8391 | ((HOST_WIDE_INT) (-1)
8392 << GET_MODE_BITSIZE (GET_MODE (x))));
8396 else if (nonzero_sign_valid && reg_stat[REGNO (x)].nonzero_bits)
8398 unsigned HOST_WIDE_INT mask = reg_stat[REGNO (x)].nonzero_bits;
8400 if (GET_MODE_BITSIZE (GET_MODE (x)) < GET_MODE_BITSIZE (mode))
8401 /* We don't know anything about the upper bits. */
8402 mask |= GET_MODE_MASK (mode) ^ GET_MODE_MASK (GET_MODE (x));
8409 /* Return the number of bits at the high-order end of X that are known to
8410 be equal to the sign bit. X will be used in mode MODE; if MODE is
8411 VOIDmode, X will be used in its own mode. The returned value will always
8412 be between 1 and the number of bits in MODE. */
8415 reg_num_sign_bit_copies_for_combine (rtx x, enum machine_mode mode,
8416 rtx known_x ATTRIBUTE_UNUSED,
8417 enum machine_mode known_mode
8419 unsigned int known_ret ATTRIBUTE_UNUSED,
8420 unsigned int *result)
8424 if (reg_stat[REGNO (x)].last_set_value != 0
8425 && reg_stat[REGNO (x)].last_set_mode == mode
8426 && (reg_stat[REGNO (x)].last_set_label == label_tick
8427 || (REGNO (x) >= FIRST_PSEUDO_REGISTER
8428 && REG_N_SETS (REGNO (x)) == 1
8429 && ! REGNO_REG_SET_P
8430 (ENTRY_BLOCK_PTR->next_bb->il.rtl->global_live_at_start,
8432 && INSN_CUID (reg_stat[REGNO (x)].last_set) < subst_low_cuid)
8434 *result = reg_stat[REGNO (x)].last_set_sign_bit_copies;
8438 tem = get_last_value (x);
8442 if (nonzero_sign_valid && reg_stat[REGNO (x)].sign_bit_copies != 0
8443 && GET_MODE_BITSIZE (GET_MODE (x)) == GET_MODE_BITSIZE (mode))
8444 *result = reg_stat[REGNO (x)].sign_bit_copies;
8449 /* Return the number of "extended" bits there are in X, when interpreted
8450 as a quantity in MODE whose signedness is indicated by UNSIGNEDP. For
8451 unsigned quantities, this is the number of high-order zero bits.
8452 For signed quantities, this is the number of copies of the sign bit
8453 minus 1. In both case, this function returns the number of "spare"
8454 bits. For example, if two quantities for which this function returns
8455 at least 1 are added, the addition is known not to overflow.
8457 This function will always return 0 unless called during combine, which
8458 implies that it must be called from a define_split. */
8461 extended_count (rtx x, enum machine_mode mode, int unsignedp)
8463 if (nonzero_sign_valid == 0)
8467 ? (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
8468 ? (unsigned int) (GET_MODE_BITSIZE (mode) - 1
8469 - floor_log2 (nonzero_bits (x, mode)))
8471 : num_sign_bit_copies (x, mode) - 1);
8474 /* This function is called from `simplify_shift_const' to merge two
8475 outer operations. Specifically, we have already found that we need
8476 to perform operation *POP0 with constant *PCONST0 at the outermost
8477 position. We would now like to also perform OP1 with constant CONST1
8478 (with *POP0 being done last).
8480 Return 1 if we can do the operation and update *POP0 and *PCONST0 with
8481 the resulting operation. *PCOMP_P is set to 1 if we would need to
8482 complement the innermost operand, otherwise it is unchanged.
8484 MODE is the mode in which the operation will be done. No bits outside
8485 the width of this mode matter. It is assumed that the width of this mode
8486 is smaller than or equal to HOST_BITS_PER_WIDE_INT.
8488 If *POP0 or OP1 are UNKNOWN, it means no operation is required. Only NEG, PLUS,
8489 IOR, XOR, and AND are supported. We may set *POP0 to SET if the proper
8490 result is simply *PCONST0.
8492 If the resulting operation cannot be expressed as one operation, we
8493 return 0 and do not change *POP0, *PCONST0, and *PCOMP_P. */
8496 merge_outer_ops (enum rtx_code *pop0, HOST_WIDE_INT *pconst0, enum rtx_code op1, HOST_WIDE_INT const1, enum machine_mode mode, int *pcomp_p)
8498 enum rtx_code op0 = *pop0;
8499 HOST_WIDE_INT const0 = *pconst0;
8501 const0 &= GET_MODE_MASK (mode);
8502 const1 &= GET_MODE_MASK (mode);
8504 /* If OP0 is an AND, clear unimportant bits in CONST1. */
8508 /* If OP0 or OP1 is UNKNOWN, this is easy. Similarly if they are the same or
8511 if (op1 == UNKNOWN || op0 == SET)
8514 else if (op0 == UNKNOWN)
8515 op0 = op1, const0 = const1;
8517 else if (op0 == op1)
8541 /* Otherwise, if either is a PLUS or NEG, we can't do anything. */
8542 else if (op0 == PLUS || op1 == PLUS || op0 == NEG || op1 == NEG)
8545 /* If the two constants aren't the same, we can't do anything. The
8546 remaining six cases can all be done. */
8547 else if (const0 != const1)
8555 /* (a & b) | b == b */
8557 else /* op1 == XOR */
8558 /* (a ^ b) | b == a | b */
8564 /* (a & b) ^ b == (~a) & b */
8565 op0 = AND, *pcomp_p = 1;
8566 else /* op1 == IOR */
8567 /* (a | b) ^ b == a & ~b */
8568 op0 = AND, const0 = ~const0;
8573 /* (a | b) & b == b */
8575 else /* op1 == XOR */
8576 /* (a ^ b) & b) == (~a) & b */
8583 /* Check for NO-OP cases. */
8584 const0 &= GET_MODE_MASK (mode);
8586 && (op0 == IOR || op0 == XOR || op0 == PLUS))
8588 else if (const0 == 0 && op0 == AND)
8590 else if ((unsigned HOST_WIDE_INT) const0 == GET_MODE_MASK (mode)
8594 /* ??? Slightly redundant with the above mask, but not entirely.
8595 Moving this above means we'd have to sign-extend the mode mask
8596 for the final test. */
8597 const0 = trunc_int_for_mode (const0, mode);
8605 /* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift.
8606 The result of the shift is RESULT_MODE. X, if nonzero, is an expression
8607 that we started with.
8609 The shift is normally computed in the widest mode we find in VAROP, as
8610 long as it isn't a different number of words than RESULT_MODE. Exceptions
8611 are ASHIFTRT and ROTATE, which are always done in their original mode, */
8614 simplify_shift_const (rtx x, enum rtx_code code,
8615 enum machine_mode result_mode, rtx varop,
8618 enum rtx_code orig_code = code;
8621 enum machine_mode mode = result_mode;
8622 enum machine_mode shift_mode, tmode;
8623 unsigned int mode_words
8624 = (GET_MODE_SIZE (mode) + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD;
8625 /* We form (outer_op (code varop count) (outer_const)). */
8626 enum rtx_code outer_op = UNKNOWN;
8627 HOST_WIDE_INT outer_const = 0;
8629 int complement_p = 0;
8632 /* Make sure and truncate the "natural" shift on the way in. We don't
8633 want to do this inside the loop as it makes it more difficult to
8635 if (SHIFT_COUNT_TRUNCATED)
8636 orig_count &= GET_MODE_BITSIZE (mode) - 1;
8638 /* If we were given an invalid count, don't do anything except exactly
8639 what was requested. */
8641 if (orig_count < 0 || orig_count >= (int) GET_MODE_BITSIZE (mode))
8646 return gen_rtx_fmt_ee (code, mode, varop, GEN_INT (orig_count));
8651 /* Unless one of the branches of the `if' in this loop does a `continue',
8652 we will `break' the loop after the `if'. */
8656 /* If we have an operand of (clobber (const_int 0)), just return that
8658 if (GET_CODE (varop) == CLOBBER)
8661 /* If we discovered we had to complement VAROP, leave. Making a NOT
8662 here would cause an infinite loop. */
8666 /* Convert ROTATERT to ROTATE. */
8667 if (code == ROTATERT)
8669 unsigned int bitsize = GET_MODE_BITSIZE (result_mode);;
8671 if (VECTOR_MODE_P (result_mode))
8672 count = bitsize / GET_MODE_NUNITS (result_mode) - count;
8674 count = bitsize - count;
8677 /* We need to determine what mode we will do the shift in. If the
8678 shift is a right shift or a ROTATE, we must always do it in the mode
8679 it was originally done in. Otherwise, we can do it in MODE, the
8680 widest mode encountered. */
8682 = (code == ASHIFTRT || code == LSHIFTRT || code == ROTATE
8683 ? result_mode : mode);
8685 /* Handle cases where the count is greater than the size of the mode
8686 minus 1. For ASHIFT, use the size minus one as the count (this can
8687 occur when simplifying (lshiftrt (ashiftrt ..))). For rotates,
8688 take the count modulo the size. For other shifts, the result is
8691 Since these shifts are being produced by the compiler by combining
8692 multiple operations, each of which are defined, we know what the
8693 result is supposed to be. */
8695 if (count > (unsigned int) (GET_MODE_BITSIZE (shift_mode) - 1))
8697 if (code == ASHIFTRT)
8698 count = GET_MODE_BITSIZE (shift_mode) - 1;
8699 else if (code == ROTATE || code == ROTATERT)
8700 count %= GET_MODE_BITSIZE (shift_mode);
8703 /* We can't simply return zero because there may be an
8711 /* An arithmetic right shift of a quantity known to be -1 or 0
8713 if (code == ASHIFTRT
8714 && (num_sign_bit_copies (varop, shift_mode)
8715 == GET_MODE_BITSIZE (shift_mode)))
8721 /* If we are doing an arithmetic right shift and discarding all but
8722 the sign bit copies, this is equivalent to doing a shift by the
8723 bitsize minus one. Convert it into that shift because it will often
8724 allow other simplifications. */
8726 if (code == ASHIFTRT
8727 && (count + num_sign_bit_copies (varop, shift_mode)
8728 >= GET_MODE_BITSIZE (shift_mode)))
8729 count = GET_MODE_BITSIZE (shift_mode) - 1;
8731 /* We simplify the tests below and elsewhere by converting
8732 ASHIFTRT to LSHIFTRT if we know the sign bit is clear.
8733 `make_compound_operation' will convert it to an ASHIFTRT for
8734 those machines (such as VAX) that don't have an LSHIFTRT. */
8735 if (GET_MODE_BITSIZE (shift_mode) <= HOST_BITS_PER_WIDE_INT
8737 && ((nonzero_bits (varop, shift_mode)
8738 & ((HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (shift_mode) - 1)))
8742 if (code == LSHIFTRT
8743 && GET_MODE_BITSIZE (shift_mode) <= HOST_BITS_PER_WIDE_INT
8744 && !(nonzero_bits (varop, shift_mode) >> count))
8747 && GET_MODE_BITSIZE (shift_mode) <= HOST_BITS_PER_WIDE_INT
8748 && !((nonzero_bits (varop, shift_mode) << count)
8749 & GET_MODE_MASK (shift_mode)))
8752 switch (GET_CODE (varop))
8758 new = expand_compound_operation (varop);
8767 /* If we have (xshiftrt (mem ...) C) and C is MODE_WIDTH
8768 minus the width of a smaller mode, we can do this with a
8769 SIGN_EXTEND or ZERO_EXTEND from the narrower memory location. */
8770 if ((code == ASHIFTRT || code == LSHIFTRT)
8771 && ! mode_dependent_address_p (XEXP (varop, 0))
8772 && ! MEM_VOLATILE_P (varop)
8773 && (tmode = mode_for_size (GET_MODE_BITSIZE (mode) - count,
8774 MODE_INT, 1)) != BLKmode)
8776 new = adjust_address_nv (varop, tmode,
8777 BYTES_BIG_ENDIAN ? 0
8778 : count / BITS_PER_UNIT);
8780 varop = gen_rtx_fmt_e (code == ASHIFTRT ? SIGN_EXTEND
8781 : ZERO_EXTEND, mode, new);
8788 /* Similar to the case above, except that we can only do this if
8789 the resulting mode is the same as that of the underlying
8790 MEM and adjust the address depending on the *bits* endianness
8791 because of the way that bit-field extract insns are defined. */
8792 if ((code == ASHIFTRT || code == LSHIFTRT)
8793 && (tmode = mode_for_size (GET_MODE_BITSIZE (mode) - count,
8794 MODE_INT, 1)) != BLKmode
8795 && tmode == GET_MODE (XEXP (varop, 0)))
8797 if (BITS_BIG_ENDIAN)
8798 new = XEXP (varop, 0);
8801 new = copy_rtx (XEXP (varop, 0));
8802 SUBST (XEXP (new, 0),
8803 plus_constant (XEXP (new, 0),
8804 count / BITS_PER_UNIT));
8807 varop = gen_rtx_fmt_e (code == ASHIFTRT ? SIGN_EXTEND
8808 : ZERO_EXTEND, mode, new);
8815 /* If VAROP is a SUBREG, strip it as long as the inner operand has
8816 the same number of words as what we've seen so far. Then store
8817 the widest mode in MODE. */
8818 if (subreg_lowpart_p (varop)
8819 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop)))
8820 > GET_MODE_SIZE (GET_MODE (varop)))
8821 && (unsigned int) ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop)))
8822 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
8825 varop = SUBREG_REG (varop);
8826 if (GET_MODE_SIZE (GET_MODE (varop)) > GET_MODE_SIZE (mode))
8827 mode = GET_MODE (varop);
8833 /* Some machines use MULT instead of ASHIFT because MULT
8834 is cheaper. But it is still better on those machines to
8835 merge two shifts into one. */
8836 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
8837 && exact_log2 (INTVAL (XEXP (varop, 1))) >= 0)
8840 = simplify_gen_binary (ASHIFT, GET_MODE (varop),
8842 GEN_INT (exact_log2 (
8843 INTVAL (XEXP (varop, 1)))));
8849 /* Similar, for when divides are cheaper. */
8850 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
8851 && exact_log2 (INTVAL (XEXP (varop, 1))) >= 0)
8854 = simplify_gen_binary (LSHIFTRT, GET_MODE (varop),
8856 GEN_INT (exact_log2 (
8857 INTVAL (XEXP (varop, 1)))));
8863 /* If we are extracting just the sign bit of an arithmetic
8864 right shift, that shift is not needed. However, the sign
8865 bit of a wider mode may be different from what would be
8866 interpreted as the sign bit in a narrower mode, so, if
8867 the result is narrower, don't discard the shift. */
8868 if (code == LSHIFTRT
8869 && count == (unsigned int) (GET_MODE_BITSIZE (result_mode) - 1)
8870 && (GET_MODE_BITSIZE (result_mode)
8871 >= GET_MODE_BITSIZE (GET_MODE (varop))))
8873 varop = XEXP (varop, 0);
8877 /* ... fall through ... */
8882 /* Here we have two nested shifts. The result is usually the
8883 AND of a new shift with a mask. We compute the result below. */
8884 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
8885 && INTVAL (XEXP (varop, 1)) >= 0
8886 && INTVAL (XEXP (varop, 1)) < GET_MODE_BITSIZE (GET_MODE (varop))
8887 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
8888 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
8890 enum rtx_code first_code = GET_CODE (varop);
8891 unsigned int first_count = INTVAL (XEXP (varop, 1));
8892 unsigned HOST_WIDE_INT mask;
8895 /* We have one common special case. We can't do any merging if
8896 the inner code is an ASHIFTRT of a smaller mode. However, if
8897 we have (ashift:M1 (subreg:M1 (ashiftrt:M2 FOO C1) 0) C2)
8898 with C2 == GET_MODE_BITSIZE (M1) - GET_MODE_BITSIZE (M2),
8899 we can convert it to
8900 (ashiftrt:M1 (ashift:M1 (and:M1 (subreg:M1 FOO 0 C2) C3) C1).
8901 This simplifies certain SIGN_EXTEND operations. */
8902 if (code == ASHIFT && first_code == ASHIFTRT
8903 && count == (unsigned int)
8904 (GET_MODE_BITSIZE (result_mode)
8905 - GET_MODE_BITSIZE (GET_MODE (varop))))
8907 /* C3 has the low-order C1 bits zero. */
8909 mask = (GET_MODE_MASK (mode)
8910 & ~(((HOST_WIDE_INT) 1 << first_count) - 1));
8912 varop = simplify_and_const_int (NULL_RTX, result_mode,
8913 XEXP (varop, 0), mask);
8914 varop = simplify_shift_const (NULL_RTX, ASHIFT, result_mode,
8916 count = first_count;
8921 /* If this was (ashiftrt (ashift foo C1) C2) and FOO has more
8922 than C1 high-order bits equal to the sign bit, we can convert
8923 this to either an ASHIFT or an ASHIFTRT depending on the
8926 We cannot do this if VAROP's mode is not SHIFT_MODE. */
8928 if (code == ASHIFTRT && first_code == ASHIFT
8929 && GET_MODE (varop) == shift_mode
8930 && (num_sign_bit_copies (XEXP (varop, 0), shift_mode)
8933 varop = XEXP (varop, 0);
8935 signed_count = count - first_count;
8936 if (signed_count < 0)
8937 count = -signed_count, code = ASHIFT;
8939 count = signed_count;
8944 /* There are some cases we can't do. If CODE is ASHIFTRT,
8945 we can only do this if FIRST_CODE is also ASHIFTRT.
8947 We can't do the case when CODE is ROTATE and FIRST_CODE is
8950 If the mode of this shift is not the mode of the outer shift,
8951 we can't do this if either shift is a right shift or ROTATE.
8953 Finally, we can't do any of these if the mode is too wide
8954 unless the codes are the same.
8956 Handle the case where the shift codes are the same
8959 if (code == first_code)
8961 if (GET_MODE (varop) != result_mode
8962 && (code == ASHIFTRT || code == LSHIFTRT
8966 count += first_count;
8967 varop = XEXP (varop, 0);
8971 if (code == ASHIFTRT
8972 || (code == ROTATE && first_code == ASHIFTRT)
8973 || GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT
8974 || (GET_MODE (varop) != result_mode
8975 && (first_code == ASHIFTRT || first_code == LSHIFTRT
8976 || first_code == ROTATE
8977 || code == ROTATE)))
8980 /* To compute the mask to apply after the shift, shift the
8981 nonzero bits of the inner shift the same way the
8982 outer shift will. */
8984 mask_rtx = GEN_INT (nonzero_bits (varop, GET_MODE (varop)));
8987 = simplify_binary_operation (code, result_mode, mask_rtx,
8990 /* Give up if we can't compute an outer operation to use. */
8992 || GET_CODE (mask_rtx) != CONST_INT
8993 || ! merge_outer_ops (&outer_op, &outer_const, AND,
8995 result_mode, &complement_p))
8998 /* If the shifts are in the same direction, we add the
8999 counts. Otherwise, we subtract them. */
9000 signed_count = count;
9001 if ((code == ASHIFTRT || code == LSHIFTRT)
9002 == (first_code == ASHIFTRT || first_code == LSHIFTRT))
9003 signed_count += first_count;
9005 signed_count -= first_count;
9007 /* If COUNT is positive, the new shift is usually CODE,
9008 except for the two exceptions below, in which case it is
9009 FIRST_CODE. If the count is negative, FIRST_CODE should
9011 if (signed_count > 0
9012 && ((first_code == ROTATE && code == ASHIFT)
9013 || (first_code == ASHIFTRT && code == LSHIFTRT)))
9014 code = first_code, count = signed_count;
9015 else if (signed_count < 0)
9016 code = first_code, count = -signed_count;
9018 count = signed_count;
9020 varop = XEXP (varop, 0);
9024 /* If we have (A << B << C) for any shift, we can convert this to
9025 (A << C << B). This wins if A is a constant. Only try this if
9026 B is not a constant. */
9028 else if (GET_CODE (varop) == code
9029 && GET_CODE (XEXP (varop, 1)) != CONST_INT
9031 = simplify_binary_operation (code, mode,
9035 varop = gen_rtx_fmt_ee (code, mode, new, XEXP (varop, 1));
9042 /* Make this fit the case below. */
9043 varop = gen_rtx_XOR (mode, XEXP (varop, 0),
9044 GEN_INT (GET_MODE_MASK (mode)));
9050 /* If we have (xshiftrt (ior (plus X (const_int -1)) X) C)
9051 with C the size of VAROP - 1 and the shift is logical if
9052 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
9053 we have an (le X 0) operation. If we have an arithmetic shift
9054 and STORE_FLAG_VALUE is 1 or we have a logical shift with
9055 STORE_FLAG_VALUE of -1, we have a (neg (le X 0)) operation. */
9057 if (GET_CODE (varop) == IOR && GET_CODE (XEXP (varop, 0)) == PLUS
9058 && XEXP (XEXP (varop, 0), 1) == constm1_rtx
9059 && (STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
9060 && (code == LSHIFTRT || code == ASHIFTRT)
9061 && count == (unsigned int)
9062 (GET_MODE_BITSIZE (GET_MODE (varop)) - 1)
9063 && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
9066 varop = gen_rtx_LE (GET_MODE (varop), XEXP (varop, 1),
9069 if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
9070 varop = gen_rtx_NEG (GET_MODE (varop), varop);
9075 /* If we have (shift (logical)), move the logical to the outside
9076 to allow it to possibly combine with another logical and the
9077 shift to combine with another shift. This also canonicalizes to
9078 what a ZERO_EXTRACT looks like. Also, some machines have
9079 (and (shift)) insns. */
9081 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
9082 /* We can't do this if we have (ashiftrt (xor)) and the
9083 constant has its sign bit set in shift_mode. */
9084 && !(code == ASHIFTRT && GET_CODE (varop) == XOR
9085 && 0 > trunc_int_for_mode (INTVAL (XEXP (varop, 1)),
9087 && (new = simplify_binary_operation (code, result_mode,
9089 GEN_INT (count))) != 0
9090 && GET_CODE (new) == CONST_INT
9091 && merge_outer_ops (&outer_op, &outer_const, GET_CODE (varop),
9092 INTVAL (new), result_mode, &complement_p))
9094 varop = XEXP (varop, 0);
9098 /* If we can't do that, try to simplify the shift in each arm of the
9099 logical expression, make a new logical expression, and apply
9100 the inverse distributive law. This also can't be done
9101 for some (ashiftrt (xor)). */
9102 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
9103 && !(code == ASHIFTRT && GET_CODE (varop) == XOR
9104 && 0 > trunc_int_for_mode (INTVAL (XEXP (varop, 1)),
9107 rtx lhs = simplify_shift_const (NULL_RTX, code, shift_mode,
9108 XEXP (varop, 0), count);
9109 rtx rhs = simplify_shift_const (NULL_RTX, code, shift_mode,
9110 XEXP (varop, 1), count);
9112 varop = simplify_gen_binary (GET_CODE (varop), shift_mode,
9114 varop = apply_distributive_law (varop);
9122 /* Convert (lshiftrt (eq FOO 0) C) to (xor FOO 1) if STORE_FLAG_VALUE
9123 says that the sign bit can be tested, FOO has mode MODE, C is
9124 GET_MODE_BITSIZE (MODE) - 1, and FOO has only its low-order bit
9125 that may be nonzero. */
9126 if (code == LSHIFTRT
9127 && XEXP (varop, 1) == const0_rtx
9128 && GET_MODE (XEXP (varop, 0)) == result_mode
9129 && count == (unsigned int) (GET_MODE_BITSIZE (result_mode) - 1)
9130 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
9131 && ((STORE_FLAG_VALUE
9132 & ((HOST_WIDE_INT) 1
9133 < (GET_MODE_BITSIZE (result_mode) - 1))))
9134 && nonzero_bits (XEXP (varop, 0), result_mode) == 1
9135 && merge_outer_ops (&outer_op, &outer_const, XOR,
9136 (HOST_WIDE_INT) 1, result_mode,
9139 varop = XEXP (varop, 0);
9146 /* (lshiftrt (neg A) C) where A is either 0 or 1 and C is one less
9147 than the number of bits in the mode is equivalent to A. */
9148 if (code == LSHIFTRT
9149 && count == (unsigned int) (GET_MODE_BITSIZE (result_mode) - 1)
9150 && nonzero_bits (XEXP (varop, 0), result_mode) == 1)
9152 varop = XEXP (varop, 0);
9157 /* NEG commutes with ASHIFT since it is multiplication. Move the
9158 NEG outside to allow shifts to combine. */
9160 && merge_outer_ops (&outer_op, &outer_const, NEG,
9161 (HOST_WIDE_INT) 0, result_mode,
9164 varop = XEXP (varop, 0);
9170 /* (lshiftrt (plus A -1) C) where A is either 0 or 1 and C
9171 is one less than the number of bits in the mode is
9172 equivalent to (xor A 1). */
9173 if (code == LSHIFTRT
9174 && count == (unsigned int) (GET_MODE_BITSIZE (result_mode) - 1)
9175 && XEXP (varop, 1) == constm1_rtx
9176 && nonzero_bits (XEXP (varop, 0), result_mode) == 1
9177 && merge_outer_ops (&outer_op, &outer_const, XOR,
9178 (HOST_WIDE_INT) 1, result_mode,
9182 varop = XEXP (varop, 0);
9186 /* If we have (xshiftrt (plus FOO BAR) C), and the only bits
9187 that might be nonzero in BAR are those being shifted out and those
9188 bits are known zero in FOO, we can replace the PLUS with FOO.
9189 Similarly in the other operand order. This code occurs when
9190 we are computing the size of a variable-size array. */
9192 if ((code == ASHIFTRT || code == LSHIFTRT)
9193 && count < HOST_BITS_PER_WIDE_INT
9194 && nonzero_bits (XEXP (varop, 1), result_mode) >> count == 0
9195 && (nonzero_bits (XEXP (varop, 1), result_mode)
9196 & nonzero_bits (XEXP (varop, 0), result_mode)) == 0)
9198 varop = XEXP (varop, 0);
9201 else if ((code == ASHIFTRT || code == LSHIFTRT)
9202 && count < HOST_BITS_PER_WIDE_INT
9203 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
9204 && 0 == (nonzero_bits (XEXP (varop, 0), result_mode)
9206 && 0 == (nonzero_bits (XEXP (varop, 0), result_mode)
9207 & nonzero_bits (XEXP (varop, 1),
9210 varop = XEXP (varop, 1);
9214 /* (ashift (plus foo C) N) is (plus (ashift foo N) C'). */
9216 && GET_CODE (XEXP (varop, 1)) == CONST_INT
9217 && (new = simplify_binary_operation (ASHIFT, result_mode,
9219 GEN_INT (count))) != 0
9220 && GET_CODE (new) == CONST_INT
9221 && merge_outer_ops (&outer_op, &outer_const, PLUS,
9222 INTVAL (new), result_mode, &complement_p))
9224 varop = XEXP (varop, 0);
9228 /* Check for 'PLUS signbit', which is the canonical form of 'XOR
9229 signbit', and attempt to change the PLUS to an XOR and move it to
9230 the outer operation as is done above in the AND/IOR/XOR case
9231 leg for shift(logical). See details in logical handling above
9232 for reasoning in doing so. */
9233 if (code == LSHIFTRT
9234 && GET_CODE (XEXP (varop, 1)) == CONST_INT
9235 && mode_signbit_p (result_mode, XEXP (varop, 1))
9236 && (new = simplify_binary_operation (code, result_mode,
9238 GEN_INT (count))) != 0
9239 && GET_CODE (new) == CONST_INT
9240 && merge_outer_ops (&outer_op, &outer_const, XOR,
9241 INTVAL (new), result_mode, &complement_p))
9243 varop = XEXP (varop, 0);
9250 /* If we have (xshiftrt (minus (ashiftrt X C)) X) C)
9251 with C the size of VAROP - 1 and the shift is logical if
9252 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
9253 we have a (gt X 0) operation. If the shift is arithmetic with
9254 STORE_FLAG_VALUE of 1 or logical with STORE_FLAG_VALUE == -1,
9255 we have a (neg (gt X 0)) operation. */
9257 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
9258 && GET_CODE (XEXP (varop, 0)) == ASHIFTRT
9259 && count == (unsigned int)
9260 (GET_MODE_BITSIZE (GET_MODE (varop)) - 1)
9261 && (code == LSHIFTRT || code == ASHIFTRT)
9262 && GET_CODE (XEXP (XEXP (varop, 0), 1)) == CONST_INT
9263 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (XEXP (varop, 0), 1))
9265 && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
9268 varop = gen_rtx_GT (GET_MODE (varop), XEXP (varop, 1),
9271 if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
9272 varop = gen_rtx_NEG (GET_MODE (varop), varop);
9279 /* Change (lshiftrt (truncate (lshiftrt))) to (truncate (lshiftrt))
9280 if the truncate does not affect the value. */
9281 if (code == LSHIFTRT
9282 && GET_CODE (XEXP (varop, 0)) == LSHIFTRT
9283 && GET_CODE (XEXP (XEXP (varop, 0), 1)) == CONST_INT
9284 && (INTVAL (XEXP (XEXP (varop, 0), 1))
9285 >= (GET_MODE_BITSIZE (GET_MODE (XEXP (varop, 0)))
9286 - GET_MODE_BITSIZE (GET_MODE (varop)))))
9288 rtx varop_inner = XEXP (varop, 0);
9291 = gen_rtx_LSHIFTRT (GET_MODE (varop_inner),
9292 XEXP (varop_inner, 0),
9294 (count + INTVAL (XEXP (varop_inner, 1))));
9295 varop = gen_rtx_TRUNCATE (GET_MODE (varop), varop_inner);
9308 /* We need to determine what mode to do the shift in. If the shift is
9309 a right shift or ROTATE, we must always do it in the mode it was
9310 originally done in. Otherwise, we can do it in MODE, the widest mode
9311 encountered. The code we care about is that of the shift that will
9312 actually be done, not the shift that was originally requested. */
9314 = (code == ASHIFTRT || code == LSHIFTRT || code == ROTATE
9315 ? result_mode : mode);
9317 /* We have now finished analyzing the shift. The result should be
9318 a shift of type CODE with SHIFT_MODE shifting VAROP COUNT places. If
9319 OUTER_OP is non-UNKNOWN, it is an operation that needs to be applied
9320 to the result of the shift. OUTER_CONST is the relevant constant,
9321 but we must turn off all bits turned off in the shift.
9323 If we were passed a value for X, see if we can use any pieces of
9324 it. If not, make new rtx. */
9326 if (x && GET_RTX_CLASS (GET_CODE (x)) == RTX_BIN_ARITH
9327 && GET_CODE (XEXP (x, 1)) == CONST_INT
9328 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (x, 1)) == count)
9329 const_rtx = XEXP (x, 1);
9331 const_rtx = GEN_INT (count);
9333 if (x && GET_CODE (XEXP (x, 0)) == SUBREG
9334 && GET_MODE (XEXP (x, 0)) == shift_mode
9335 && SUBREG_REG (XEXP (x, 0)) == varop)
9336 varop = XEXP (x, 0);
9337 else if (GET_MODE (varop) != shift_mode)
9338 varop = gen_lowpart (shift_mode, varop);
9340 /* If we can't make the SUBREG, try to return what we were given. */
9341 if (GET_CODE (varop) == CLOBBER)
9342 return x ? x : varop;
9344 new = simplify_binary_operation (code, shift_mode, varop, const_rtx);
9348 x = gen_rtx_fmt_ee (code, shift_mode, varop, const_rtx);
9350 /* If we have an outer operation and we just made a shift, it is
9351 possible that we could have simplified the shift were it not
9352 for the outer operation. So try to do the simplification
9355 if (outer_op != UNKNOWN && GET_CODE (x) == code
9356 && GET_CODE (XEXP (x, 1)) == CONST_INT)
9357 x = simplify_shift_const (x, code, shift_mode, XEXP (x, 0),
9358 INTVAL (XEXP (x, 1)));
9360 /* If we were doing an LSHIFTRT in a wider mode than it was originally,
9361 turn off all the bits that the shift would have turned off. */
9362 if (orig_code == LSHIFTRT && result_mode != shift_mode)
9363 x = simplify_and_const_int (NULL_RTX, shift_mode, x,
9364 GET_MODE_MASK (result_mode) >> orig_count);
9366 /* Do the remainder of the processing in RESULT_MODE. */
9367 x = gen_lowpart (result_mode, x);
9369 /* If COMPLEMENT_P is set, we have to complement X before doing the outer
9372 x = simplify_gen_unary (NOT, result_mode, x, result_mode);
9374 if (outer_op != UNKNOWN)
9376 if (GET_MODE_BITSIZE (result_mode) < HOST_BITS_PER_WIDE_INT)
9377 outer_const = trunc_int_for_mode (outer_const, result_mode);
9379 if (outer_op == AND)
9380 x = simplify_and_const_int (NULL_RTX, result_mode, x, outer_const);
9381 else if (outer_op == SET)
9382 /* This means that we have determined that the result is
9383 equivalent to a constant. This should be rare. */
9384 x = GEN_INT (outer_const);
9385 else if (GET_RTX_CLASS (outer_op) == RTX_UNARY)
9386 x = simplify_gen_unary (outer_op, result_mode, x, result_mode);
9388 x = simplify_gen_binary (outer_op, result_mode, x,
9389 GEN_INT (outer_const));
9395 /* Like recog, but we receive the address of a pointer to a new pattern.
9396 We try to match the rtx that the pointer points to.
9397 If that fails, we may try to modify or replace the pattern,
9398 storing the replacement into the same pointer object.
9400 Modifications include deletion or addition of CLOBBERs.
9402 PNOTES is a pointer to a location where any REG_UNUSED notes added for
9403 the CLOBBERs are placed.
9405 The value is the final insn code from the pattern ultimately matched,
9409 recog_for_combine (rtx *pnewpat, rtx insn, rtx *pnotes)
9412 int insn_code_number;
9413 int num_clobbers_to_add = 0;
9416 rtx old_notes, old_pat;
9418 /* If PAT is a PARALLEL, check to see if it contains the CLOBBER
9419 we use to indicate that something didn't match. If we find such a
9420 thing, force rejection. */
9421 if (GET_CODE (pat) == PARALLEL)
9422 for (i = XVECLEN (pat, 0) - 1; i >= 0; i--)
9423 if (GET_CODE (XVECEXP (pat, 0, i)) == CLOBBER
9424 && XEXP (XVECEXP (pat, 0, i), 0) == const0_rtx)
9427 old_pat = PATTERN (insn);
9428 old_notes = REG_NOTES (insn);
9429 PATTERN (insn) = pat;
9430 REG_NOTES (insn) = 0;
9432 insn_code_number = recog (pat, insn, &num_clobbers_to_add);
9434 /* If it isn't, there is the possibility that we previously had an insn
9435 that clobbered some register as a side effect, but the combined
9436 insn doesn't need to do that. So try once more without the clobbers
9437 unless this represents an ASM insn. */
9439 if (insn_code_number < 0 && ! check_asm_operands (pat)
9440 && GET_CODE (pat) == PARALLEL)
9444 for (pos = 0, i = 0; i < XVECLEN (pat, 0); i++)
9445 if (GET_CODE (XVECEXP (pat, 0, i)) != CLOBBER)
9448 SUBST (XVECEXP (pat, 0, pos), XVECEXP (pat, 0, i));
9452 SUBST_INT (XVECLEN (pat, 0), pos);
9455 pat = XVECEXP (pat, 0, 0);
9457 PATTERN (insn) = pat;
9458 insn_code_number = recog (pat, insn, &num_clobbers_to_add);
9460 PATTERN (insn) = old_pat;
9461 REG_NOTES (insn) = old_notes;
9463 /* Recognize all noop sets, these will be killed by followup pass. */
9464 if (insn_code_number < 0 && GET_CODE (pat) == SET && set_noop_p (pat))
9465 insn_code_number = NOOP_MOVE_INSN_CODE, num_clobbers_to_add = 0;
9467 /* If we had any clobbers to add, make a new pattern than contains
9468 them. Then check to make sure that all of them are dead. */
9469 if (num_clobbers_to_add)
9471 rtx newpat = gen_rtx_PARALLEL (VOIDmode,
9472 rtvec_alloc (GET_CODE (pat) == PARALLEL
9474 + num_clobbers_to_add)
9475 : num_clobbers_to_add + 1));
9477 if (GET_CODE (pat) == PARALLEL)
9478 for (i = 0; i < XVECLEN (pat, 0); i++)
9479 XVECEXP (newpat, 0, i) = XVECEXP (pat, 0, i);
9481 XVECEXP (newpat, 0, 0) = pat;
9483 add_clobbers (newpat, insn_code_number);
9485 for (i = XVECLEN (newpat, 0) - num_clobbers_to_add;
9486 i < XVECLEN (newpat, 0); i++)
9488 if (REG_P (XEXP (XVECEXP (newpat, 0, i), 0))
9489 && ! reg_dead_at_p (XEXP (XVECEXP (newpat, 0, i), 0), insn))
9491 notes = gen_rtx_EXPR_LIST (REG_UNUSED,
9492 XEXP (XVECEXP (newpat, 0, i), 0), notes);
9500 return insn_code_number;
9503 /* Like gen_lowpart_general but for use by combine. In combine it
9504 is not possible to create any new pseudoregs. However, it is
9505 safe to create invalid memory addresses, because combine will
9506 try to recognize them and all they will do is make the combine
9509 If for some reason this cannot do its job, an rtx
9510 (clobber (const_int 0)) is returned.
9511 An insn containing that will not be recognized. */
9514 gen_lowpart_for_combine (enum machine_mode omode, rtx x)
9516 enum machine_mode imode = GET_MODE (x);
9517 unsigned int osize = GET_MODE_SIZE (omode);
9518 unsigned int isize = GET_MODE_SIZE (imode);
9524 /* Return identity if this is a CONST or symbolic reference. */
9526 && (GET_CODE (x) == CONST
9527 || GET_CODE (x) == SYMBOL_REF
9528 || GET_CODE (x) == LABEL_REF))
9531 /* We can only support MODE being wider than a word if X is a
9532 constant integer or has a mode the same size. */
9533 if (GET_MODE_SIZE (omode) > UNITS_PER_WORD
9534 && ! ((imode == VOIDmode
9535 && (GET_CODE (x) == CONST_INT
9536 || GET_CODE (x) == CONST_DOUBLE))
9540 /* X might be a paradoxical (subreg (mem)). In that case, gen_lowpart
9541 won't know what to do. So we will strip off the SUBREG here and
9542 process normally. */
9543 if (GET_CODE (x) == SUBREG && MEM_P (SUBREG_REG (x)))
9547 /* For use in case we fall down into the address adjustments
9548 further below, we need to adjust the known mode and size of
9549 x; imode and isize, since we just adjusted x. */
9550 imode = GET_MODE (x);
9555 isize = GET_MODE_SIZE (imode);
9558 result = gen_lowpart_common (omode, x);
9560 #ifdef CANNOT_CHANGE_MODE_CLASS
9561 if (result != 0 && GET_CODE (result) == SUBREG)
9562 record_subregs_of_mode (result);
9572 /* Refuse to work on a volatile memory ref or one with a mode-dependent
9574 if (MEM_VOLATILE_P (x) || mode_dependent_address_p (XEXP (x, 0)))
9577 /* If we want to refer to something bigger than the original memref,
9578 generate a paradoxical subreg instead. That will force a reload
9579 of the original memref X. */
9581 return gen_rtx_SUBREG (omode, x, 0);
9583 if (WORDS_BIG_ENDIAN)
9584 offset = MAX (isize, UNITS_PER_WORD) - MAX (osize, UNITS_PER_WORD);
9586 /* Adjust the address so that the address-after-the-data is
9588 if (BYTES_BIG_ENDIAN)
9589 offset -= MIN (UNITS_PER_WORD, osize) - MIN (UNITS_PER_WORD, isize);
9591 return adjust_address_nv (x, omode, offset);
9594 /* If X is a comparison operator, rewrite it in a new mode. This
9595 probably won't match, but may allow further simplifications. */
9596 else if (COMPARISON_P (x))
9597 return gen_rtx_fmt_ee (GET_CODE (x), omode, XEXP (x, 0), XEXP (x, 1));
9599 /* If we couldn't simplify X any other way, just enclose it in a
9600 SUBREG. Normally, this SUBREG won't match, but some patterns may
9601 include an explicit SUBREG or we may simplify it further in combine. */
9607 offset = subreg_lowpart_offset (omode, imode);
9608 if (imode == VOIDmode)
9610 imode = int_mode_for_mode (omode);
9611 x = gen_lowpart_common (imode, x);
9615 res = simplify_gen_subreg (omode, x, imode, offset);
9621 return gen_rtx_CLOBBER (imode, const0_rtx);
9624 /* Simplify a comparison between *POP0 and *POP1 where CODE is the
9625 comparison code that will be tested.
9627 The result is a possibly different comparison code to use. *POP0 and
9628 *POP1 may be updated.
9630 It is possible that we might detect that a comparison is either always
9631 true or always false. However, we do not perform general constant
9632 folding in combine, so this knowledge isn't useful. Such tautologies
9633 should have been detected earlier. Hence we ignore all such cases. */
9635 static enum rtx_code
9636 simplify_comparison (enum rtx_code code, rtx *pop0, rtx *pop1)
9642 enum machine_mode mode, tmode;
9644 /* Try a few ways of applying the same transformation to both operands. */
9647 #ifndef WORD_REGISTER_OPERATIONS
9648 /* The test below this one won't handle SIGN_EXTENDs on these machines,
9649 so check specially. */
9650 if (code != GTU && code != GEU && code != LTU && code != LEU
9651 && GET_CODE (op0) == ASHIFTRT && GET_CODE (op1) == ASHIFTRT
9652 && GET_CODE (XEXP (op0, 0)) == ASHIFT
9653 && GET_CODE (XEXP (op1, 0)) == ASHIFT
9654 && GET_CODE (XEXP (XEXP (op0, 0), 0)) == SUBREG
9655 && GET_CODE (XEXP (XEXP (op1, 0), 0)) == SUBREG
9656 && (GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0)))
9657 == GET_MODE (SUBREG_REG (XEXP (XEXP (op1, 0), 0))))
9658 && GET_CODE (XEXP (op0, 1)) == CONST_INT
9659 && XEXP (op0, 1) == XEXP (op1, 1)
9660 && XEXP (op0, 1) == XEXP (XEXP (op0, 0), 1)
9661 && XEXP (op0, 1) == XEXP (XEXP (op1, 0), 1)
9662 && (INTVAL (XEXP (op0, 1))
9663 == (GET_MODE_BITSIZE (GET_MODE (op0))
9665 (GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0))))))))
9667 op0 = SUBREG_REG (XEXP (XEXP (op0, 0), 0));
9668 op1 = SUBREG_REG (XEXP (XEXP (op1, 0), 0));
9672 /* If both operands are the same constant shift, see if we can ignore the
9673 shift. We can if the shift is a rotate or if the bits shifted out of
9674 this shift are known to be zero for both inputs and if the type of
9675 comparison is compatible with the shift. */
9676 if (GET_CODE (op0) == GET_CODE (op1)
9677 && GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
9678 && ((GET_CODE (op0) == ROTATE && (code == NE || code == EQ))
9679 || ((GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFT)
9680 && (code != GT && code != LT && code != GE && code != LE))
9681 || (GET_CODE (op0) == ASHIFTRT
9682 && (code != GTU && code != LTU
9683 && code != GEU && code != LEU)))
9684 && GET_CODE (XEXP (op0, 1)) == CONST_INT
9685 && INTVAL (XEXP (op0, 1)) >= 0
9686 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT
9687 && XEXP (op0, 1) == XEXP (op1, 1))
9689 enum machine_mode mode = GET_MODE (op0);
9690 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
9691 int shift_count = INTVAL (XEXP (op0, 1));
9693 if (GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFTRT)
9694 mask &= (mask >> shift_count) << shift_count;
9695 else if (GET_CODE (op0) == ASHIFT)
9696 mask = (mask & (mask << shift_count)) >> shift_count;
9698 if ((nonzero_bits (XEXP (op0, 0), mode) & ~mask) == 0
9699 && (nonzero_bits (XEXP (op1, 0), mode) & ~mask) == 0)
9700 op0 = XEXP (op0, 0), op1 = XEXP (op1, 0);
9705 /* If both operands are AND's of a paradoxical SUBREG by constant, the
9706 SUBREGs are of the same mode, and, in both cases, the AND would
9707 be redundant if the comparison was done in the narrower mode,
9708 do the comparison in the narrower mode (e.g., we are AND'ing with 1
9709 and the operand's possibly nonzero bits are 0xffffff01; in that case
9710 if we only care about QImode, we don't need the AND). This case
9711 occurs if the output mode of an scc insn is not SImode and
9712 STORE_FLAG_VALUE == 1 (e.g., the 386).
9714 Similarly, check for a case where the AND's are ZERO_EXTEND
9715 operations from some narrower mode even though a SUBREG is not
9718 else if (GET_CODE (op0) == AND && GET_CODE (op1) == AND
9719 && GET_CODE (XEXP (op0, 1)) == CONST_INT
9720 && GET_CODE (XEXP (op1, 1)) == CONST_INT)
9722 rtx inner_op0 = XEXP (op0, 0);
9723 rtx inner_op1 = XEXP (op1, 0);
9724 HOST_WIDE_INT c0 = INTVAL (XEXP (op0, 1));
9725 HOST_WIDE_INT c1 = INTVAL (XEXP (op1, 1));
9728 if (GET_CODE (inner_op0) == SUBREG && GET_CODE (inner_op1) == SUBREG
9729 && (GET_MODE_SIZE (GET_MODE (inner_op0))
9730 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (inner_op0))))
9731 && (GET_MODE (SUBREG_REG (inner_op0))
9732 == GET_MODE (SUBREG_REG (inner_op1)))
9733 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (inner_op0)))
9734 <= HOST_BITS_PER_WIDE_INT)
9735 && (0 == ((~c0) & nonzero_bits (SUBREG_REG (inner_op0),
9736 GET_MODE (SUBREG_REG (inner_op0)))))
9737 && (0 == ((~c1) & nonzero_bits (SUBREG_REG (inner_op1),
9738 GET_MODE (SUBREG_REG (inner_op1))))))
9740 op0 = SUBREG_REG (inner_op0);
9741 op1 = SUBREG_REG (inner_op1);
9743 /* The resulting comparison is always unsigned since we masked
9744 off the original sign bit. */
9745 code = unsigned_condition (code);
9751 for (tmode = GET_CLASS_NARROWEST_MODE
9752 (GET_MODE_CLASS (GET_MODE (op0)));
9753 tmode != GET_MODE (op0); tmode = GET_MODE_WIDER_MODE (tmode))
9754 if ((unsigned HOST_WIDE_INT) c0 == GET_MODE_MASK (tmode))
9756 op0 = gen_lowpart (tmode, inner_op0);
9757 op1 = gen_lowpart (tmode, inner_op1);
9758 code = unsigned_condition (code);
9767 /* If both operands are NOT, we can strip off the outer operation
9768 and adjust the comparison code for swapped operands; similarly for
9769 NEG, except that this must be an equality comparison. */
9770 else if ((GET_CODE (op0) == NOT && GET_CODE (op1) == NOT)
9771 || (GET_CODE (op0) == NEG && GET_CODE (op1) == NEG
9772 && (code == EQ || code == NE)))
9773 op0 = XEXP (op0, 0), op1 = XEXP (op1, 0), code = swap_condition (code);
9779 /* If the first operand is a constant, swap the operands and adjust the
9780 comparison code appropriately, but don't do this if the second operand
9781 is already a constant integer. */
9782 if (swap_commutative_operands_p (op0, op1))
9784 tem = op0, op0 = op1, op1 = tem;
9785 code = swap_condition (code);
9788 /* We now enter a loop during which we will try to simplify the comparison.
9789 For the most part, we only are concerned with comparisons with zero,
9790 but some things may really be comparisons with zero but not start
9791 out looking that way. */
9793 while (GET_CODE (op1) == CONST_INT)
9795 enum machine_mode mode = GET_MODE (op0);
9796 unsigned int mode_width = GET_MODE_BITSIZE (mode);
9797 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
9798 int equality_comparison_p;
9799 int sign_bit_comparison_p;
9800 int unsigned_comparison_p;
9801 HOST_WIDE_INT const_op;
9803 /* We only want to handle integral modes. This catches VOIDmode,
9804 CCmode, and the floating-point modes. An exception is that we
9805 can handle VOIDmode if OP0 is a COMPARE or a comparison
9808 if (GET_MODE_CLASS (mode) != MODE_INT
9809 && ! (mode == VOIDmode
9810 && (GET_CODE (op0) == COMPARE || COMPARISON_P (op0))))
9813 /* Get the constant we are comparing against and turn off all bits
9814 not on in our mode. */
9815 const_op = INTVAL (op1);
9816 if (mode != VOIDmode)
9817 const_op = trunc_int_for_mode (const_op, mode);
9818 op1 = GEN_INT (const_op);
9820 /* If we are comparing against a constant power of two and the value
9821 being compared can only have that single bit nonzero (e.g., it was
9822 `and'ed with that bit), we can replace this with a comparison
9825 && (code == EQ || code == NE || code == GE || code == GEU
9826 || code == LT || code == LTU)
9827 && mode_width <= HOST_BITS_PER_WIDE_INT
9828 && exact_log2 (const_op) >= 0
9829 && nonzero_bits (op0, mode) == (unsigned HOST_WIDE_INT) const_op)
9831 code = (code == EQ || code == GE || code == GEU ? NE : EQ);
9832 op1 = const0_rtx, const_op = 0;
9835 /* Similarly, if we are comparing a value known to be either -1 or
9836 0 with -1, change it to the opposite comparison against zero. */
9839 && (code == EQ || code == NE || code == GT || code == LE
9840 || code == GEU || code == LTU)
9841 && num_sign_bit_copies (op0, mode) == mode_width)
9843 code = (code == EQ || code == LE || code == GEU ? NE : EQ);
9844 op1 = const0_rtx, const_op = 0;
9847 /* Do some canonicalizations based on the comparison code. We prefer
9848 comparisons against zero and then prefer equality comparisons.
9849 If we can reduce the size of a constant, we will do that too. */
9854 /* < C is equivalent to <= (C - 1) */
9858 op1 = GEN_INT (const_op);
9860 /* ... fall through to LE case below. */
9866 /* <= C is equivalent to < (C + 1); we do this for C < 0 */
9870 op1 = GEN_INT (const_op);
9874 /* If we are doing a <= 0 comparison on a value known to have
9875 a zero sign bit, we can replace this with == 0. */
9876 else if (const_op == 0
9877 && mode_width <= HOST_BITS_PER_WIDE_INT
9878 && (nonzero_bits (op0, mode)
9879 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)
9884 /* >= C is equivalent to > (C - 1). */
9888 op1 = GEN_INT (const_op);
9890 /* ... fall through to GT below. */
9896 /* > C is equivalent to >= (C + 1); we do this for C < 0. */
9900 op1 = GEN_INT (const_op);
9904 /* If we are doing a > 0 comparison on a value known to have
9905 a zero sign bit, we can replace this with != 0. */
9906 else if (const_op == 0
9907 && mode_width <= HOST_BITS_PER_WIDE_INT
9908 && (nonzero_bits (op0, mode)
9909 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)
9914 /* < C is equivalent to <= (C - 1). */
9918 op1 = GEN_INT (const_op);
9920 /* ... fall through ... */
9923 /* (unsigned) < 0x80000000 is equivalent to >= 0. */
9924 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
9925 && (const_op == (HOST_WIDE_INT) 1 << (mode_width - 1)))
9927 const_op = 0, op1 = const0_rtx;
9935 /* unsigned <= 0 is equivalent to == 0 */
9939 /* (unsigned) <= 0x7fffffff is equivalent to >= 0. */
9940 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
9941 && (const_op == ((HOST_WIDE_INT) 1 << (mode_width - 1)) - 1))
9943 const_op = 0, op1 = const0_rtx;
9949 /* >= C is equivalent to > (C - 1). */
9953 op1 = GEN_INT (const_op);
9955 /* ... fall through ... */
9958 /* (unsigned) >= 0x80000000 is equivalent to < 0. */
9959 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
9960 && (const_op == (HOST_WIDE_INT) 1 << (mode_width - 1)))
9962 const_op = 0, op1 = const0_rtx;
9970 /* unsigned > 0 is equivalent to != 0 */
9974 /* (unsigned) > 0x7fffffff is equivalent to < 0. */
9975 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
9976 && (const_op == ((HOST_WIDE_INT) 1 << (mode_width - 1)) - 1))
9978 const_op = 0, op1 = const0_rtx;
9987 /* Compute some predicates to simplify code below. */
9989 equality_comparison_p = (code == EQ || code == NE);
9990 sign_bit_comparison_p = ((code == LT || code == GE) && const_op == 0);
9991 unsigned_comparison_p = (code == LTU || code == LEU || code == GTU
9994 /* If this is a sign bit comparison and we can do arithmetic in
9995 MODE, say that we will only be needing the sign bit of OP0. */
9996 if (sign_bit_comparison_p
9997 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
9998 op0 = force_to_mode (op0, mode,
10000 << (GET_MODE_BITSIZE (mode) - 1)),
10003 /* Now try cases based on the opcode of OP0. If none of the cases
10004 does a "continue", we exit this loop immediately after the
10007 switch (GET_CODE (op0))
10010 /* If we are extracting a single bit from a variable position in
10011 a constant that has only a single bit set and are comparing it
10012 with zero, we can convert this into an equality comparison
10013 between the position and the location of the single bit. */
10014 /* Except we can't if SHIFT_COUNT_TRUNCATED is set, since we might
10015 have already reduced the shift count modulo the word size. */
10016 if (!SHIFT_COUNT_TRUNCATED
10017 && GET_CODE (XEXP (op0, 0)) == CONST_INT
10018 && XEXP (op0, 1) == const1_rtx
10019 && equality_comparison_p && const_op == 0
10020 && (i = exact_log2 (INTVAL (XEXP (op0, 0)))) >= 0)
10022 if (BITS_BIG_ENDIAN)
10024 enum machine_mode new_mode
10025 = mode_for_extraction (EP_extzv, 1);
10026 if (new_mode == MAX_MACHINE_MODE)
10027 i = BITS_PER_WORD - 1 - i;
10031 i = (GET_MODE_BITSIZE (mode) - 1 - i);
10035 op0 = XEXP (op0, 2);
10039 /* Result is nonzero iff shift count is equal to I. */
10040 code = reverse_condition (code);
10044 /* ... fall through ... */
10047 tem = expand_compound_operation (op0);
10056 /* If testing for equality, we can take the NOT of the constant. */
10057 if (equality_comparison_p
10058 && (tem = simplify_unary_operation (NOT, mode, op1, mode)) != 0)
10060 op0 = XEXP (op0, 0);
10065 /* If just looking at the sign bit, reverse the sense of the
10067 if (sign_bit_comparison_p)
10069 op0 = XEXP (op0, 0);
10070 code = (code == GE ? LT : GE);
10076 /* If testing for equality, we can take the NEG of the constant. */
10077 if (equality_comparison_p
10078 && (tem = simplify_unary_operation (NEG, mode, op1, mode)) != 0)
10080 op0 = XEXP (op0, 0);
10085 /* The remaining cases only apply to comparisons with zero. */
10089 /* When X is ABS or is known positive,
10090 (neg X) is < 0 if and only if X != 0. */
10092 if (sign_bit_comparison_p
10093 && (GET_CODE (XEXP (op0, 0)) == ABS
10094 || (mode_width <= HOST_BITS_PER_WIDE_INT
10095 && (nonzero_bits (XEXP (op0, 0), mode)
10096 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)))
10098 op0 = XEXP (op0, 0);
10099 code = (code == LT ? NE : EQ);
10103 /* If we have NEG of something whose two high-order bits are the
10104 same, we know that "(-a) < 0" is equivalent to "a > 0". */
10105 if (num_sign_bit_copies (op0, mode) >= 2)
10107 op0 = XEXP (op0, 0);
10108 code = swap_condition (code);
10114 /* If we are testing equality and our count is a constant, we
10115 can perform the inverse operation on our RHS. */
10116 if (equality_comparison_p && GET_CODE (XEXP (op0, 1)) == CONST_INT
10117 && (tem = simplify_binary_operation (ROTATERT, mode,
10118 op1, XEXP (op0, 1))) != 0)
10120 op0 = XEXP (op0, 0);
10125 /* If we are doing a < 0 or >= 0 comparison, it means we are testing
10126 a particular bit. Convert it to an AND of a constant of that
10127 bit. This will be converted into a ZERO_EXTRACT. */
10128 if (const_op == 0 && sign_bit_comparison_p
10129 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10130 && mode_width <= HOST_BITS_PER_WIDE_INT)
10132 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
10135 - INTVAL (XEXP (op0, 1)))));
10136 code = (code == LT ? NE : EQ);
10140 /* Fall through. */
10143 /* ABS is ignorable inside an equality comparison with zero. */
10144 if (const_op == 0 && equality_comparison_p)
10146 op0 = XEXP (op0, 0);
10152 /* Can simplify (compare (zero/sign_extend FOO) CONST) to
10153 (compare FOO CONST) if CONST fits in FOO's mode and we
10154 are either testing inequality or have an unsigned
10155 comparison with ZERO_EXTEND or a signed comparison with
10156 SIGN_EXTEND. But don't do it if we don't have a compare
10157 insn of the given mode, since we'd have to revert it
10158 later on, and then we wouldn't know whether to sign- or
10160 mode = GET_MODE (XEXP (op0, 0));
10161 if (mode != VOIDmode && GET_MODE_CLASS (mode) == MODE_INT
10162 && ! unsigned_comparison_p
10163 && (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
10164 && ((unsigned HOST_WIDE_INT) const_op
10165 < (((unsigned HOST_WIDE_INT) 1
10166 << (GET_MODE_BITSIZE (mode) - 1))))
10167 && cmp_optab->handlers[(int) mode].insn_code != CODE_FOR_nothing)
10169 op0 = XEXP (op0, 0);
10175 /* Check for the case where we are comparing A - C1 with C2, that is
10177 (subreg:MODE (plus (A) (-C1))) op (C2)
10179 with C1 a constant, and try to lift the SUBREG, i.e. to do the
10180 comparison in the wider mode. One of the following two conditions
10181 must be true in order for this to be valid:
10183 1. The mode extension results in the same bit pattern being added
10184 on both sides and the comparison is equality or unsigned. As
10185 C2 has been truncated to fit in MODE, the pattern can only be
10188 2. The mode extension results in the sign bit being copied on
10191 The difficulty here is that we have predicates for A but not for
10192 (A - C1) so we need to check that C1 is within proper bounds so
10193 as to perturbate A as little as possible. */
10195 if (mode_width <= HOST_BITS_PER_WIDE_INT
10196 && subreg_lowpart_p (op0)
10197 && GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0))) > mode_width
10198 && GET_CODE (SUBREG_REG (op0)) == PLUS
10199 && GET_CODE (XEXP (SUBREG_REG (op0), 1)) == CONST_INT)
10201 enum machine_mode inner_mode = GET_MODE (SUBREG_REG (op0));
10202 rtx a = XEXP (SUBREG_REG (op0), 0);
10203 HOST_WIDE_INT c1 = -INTVAL (XEXP (SUBREG_REG (op0), 1));
10206 && (unsigned HOST_WIDE_INT) c1
10207 < (unsigned HOST_WIDE_INT) 1 << (mode_width - 1)
10208 && (equality_comparison_p || unsigned_comparison_p)
10209 /* (A - C1) zero-extends if it is positive and sign-extends
10210 if it is negative, C2 both zero- and sign-extends. */
10211 && ((0 == (nonzero_bits (a, inner_mode)
10212 & ~GET_MODE_MASK (mode))
10214 /* (A - C1) sign-extends if it is positive and 1-extends
10215 if it is negative, C2 both sign- and 1-extends. */
10216 || (num_sign_bit_copies (a, inner_mode)
10217 > (unsigned int) (GET_MODE_BITSIZE (inner_mode)
10220 || ((unsigned HOST_WIDE_INT) c1
10221 < (unsigned HOST_WIDE_INT) 1 << (mode_width - 2)
10222 /* (A - C1) always sign-extends, like C2. */
10223 && num_sign_bit_copies (a, inner_mode)
10224 > (unsigned int) (GET_MODE_BITSIZE (inner_mode)
10225 - mode_width - 1)))
10227 op0 = SUBREG_REG (op0);
10232 /* If the inner mode is narrower and we are extracting the low part,
10233 we can treat the SUBREG as if it were a ZERO_EXTEND. */
10234 if (subreg_lowpart_p (op0)
10235 && GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0))) < mode_width)
10236 /* Fall through */ ;
10240 /* ... fall through ... */
10243 mode = GET_MODE (XEXP (op0, 0));
10244 if (mode != VOIDmode && GET_MODE_CLASS (mode) == MODE_INT
10245 && (unsigned_comparison_p || equality_comparison_p)
10246 && (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
10247 && ((unsigned HOST_WIDE_INT) const_op < GET_MODE_MASK (mode))
10248 && cmp_optab->handlers[(int) mode].insn_code != CODE_FOR_nothing)
10250 op0 = XEXP (op0, 0);
10256 /* (eq (plus X A) B) -> (eq X (minus B A)). We can only do
10257 this for equality comparisons due to pathological cases involving
10259 if (equality_comparison_p
10260 && 0 != (tem = simplify_binary_operation (MINUS, mode,
10261 op1, XEXP (op0, 1))))
10263 op0 = XEXP (op0, 0);
10268 /* (plus (abs X) (const_int -1)) is < 0 if and only if X == 0. */
10269 if (const_op == 0 && XEXP (op0, 1) == constm1_rtx
10270 && GET_CODE (XEXP (op0, 0)) == ABS && sign_bit_comparison_p)
10272 op0 = XEXP (XEXP (op0, 0), 0);
10273 code = (code == LT ? EQ : NE);
10279 /* We used to optimize signed comparisons against zero, but that
10280 was incorrect. Unsigned comparisons against zero (GTU, LEU)
10281 arrive here as equality comparisons, or (GEU, LTU) are
10282 optimized away. No need to special-case them. */
10284 /* (eq (minus A B) C) -> (eq A (plus B C)) or
10285 (eq B (minus A C)), whichever simplifies. We can only do
10286 this for equality comparisons due to pathological cases involving
10288 if (equality_comparison_p
10289 && 0 != (tem = simplify_binary_operation (PLUS, mode,
10290 XEXP (op0, 1), op1)))
10292 op0 = XEXP (op0, 0);
10297 if (equality_comparison_p
10298 && 0 != (tem = simplify_binary_operation (MINUS, mode,
10299 XEXP (op0, 0), op1)))
10301 op0 = XEXP (op0, 1);
10306 /* The sign bit of (minus (ashiftrt X C) X), where C is the number
10307 of bits in X minus 1, is one iff X > 0. */
10308 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == ASHIFTRT
10309 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
10310 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (XEXP (op0, 0), 1))
10312 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
10314 op0 = XEXP (op0, 1);
10315 code = (code == GE ? LE : GT);
10321 /* (eq (xor A B) C) -> (eq A (xor B C)). This is a simplification
10322 if C is zero or B is a constant. */
10323 if (equality_comparison_p
10324 && 0 != (tem = simplify_binary_operation (XOR, mode,
10325 XEXP (op0, 1), op1)))
10327 op0 = XEXP (op0, 0);
10334 case UNEQ: case LTGT:
10335 case LT: case LTU: case UNLT: case LE: case LEU: case UNLE:
10336 case GT: case GTU: case UNGT: case GE: case GEU: case UNGE:
10337 case UNORDERED: case ORDERED:
10338 /* We can't do anything if OP0 is a condition code value, rather
10339 than an actual data value. */
10341 || CC0_P (XEXP (op0, 0))
10342 || GET_MODE_CLASS (GET_MODE (XEXP (op0, 0))) == MODE_CC)
10345 /* Get the two operands being compared. */
10346 if (GET_CODE (XEXP (op0, 0)) == COMPARE)
10347 tem = XEXP (XEXP (op0, 0), 0), tem1 = XEXP (XEXP (op0, 0), 1);
10349 tem = XEXP (op0, 0), tem1 = XEXP (op0, 1);
10351 /* Check for the cases where we simply want the result of the
10352 earlier test or the opposite of that result. */
10353 if (code == NE || code == EQ
10354 || (GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
10355 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
10356 && (STORE_FLAG_VALUE
10357 & (((HOST_WIDE_INT) 1
10358 << (GET_MODE_BITSIZE (GET_MODE (op0)) - 1))))
10359 && (code == LT || code == GE)))
10361 enum rtx_code new_code;
10362 if (code == LT || code == NE)
10363 new_code = GET_CODE (op0);
10365 new_code = reversed_comparison_code (op0, NULL);
10367 if (new_code != UNKNOWN)
10378 /* The sign bit of (ior (plus X (const_int -1)) X) is nonzero
10380 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == PLUS
10381 && XEXP (XEXP (op0, 0), 1) == constm1_rtx
10382 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
10384 op0 = XEXP (op0, 1);
10385 code = (code == GE ? GT : LE);
10391 /* Convert (and (xshift 1 X) Y) to (and (lshiftrt Y X) 1). This
10392 will be converted to a ZERO_EXTRACT later. */
10393 if (const_op == 0 && equality_comparison_p
10394 && GET_CODE (XEXP (op0, 0)) == ASHIFT
10395 && XEXP (XEXP (op0, 0), 0) == const1_rtx)
10397 op0 = simplify_and_const_int
10398 (op0, mode, gen_rtx_LSHIFTRT (mode,
10400 XEXP (XEXP (op0, 0), 1)),
10401 (HOST_WIDE_INT) 1);
10405 /* If we are comparing (and (lshiftrt X C1) C2) for equality with
10406 zero and X is a comparison and C1 and C2 describe only bits set
10407 in STORE_FLAG_VALUE, we can compare with X. */
10408 if (const_op == 0 && equality_comparison_p
10409 && mode_width <= HOST_BITS_PER_WIDE_INT
10410 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10411 && GET_CODE (XEXP (op0, 0)) == LSHIFTRT
10412 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
10413 && INTVAL (XEXP (XEXP (op0, 0), 1)) >= 0
10414 && INTVAL (XEXP (XEXP (op0, 0), 1)) < HOST_BITS_PER_WIDE_INT)
10416 mask = ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
10417 << INTVAL (XEXP (XEXP (op0, 0), 1)));
10418 if ((~STORE_FLAG_VALUE & mask) == 0
10419 && (COMPARISON_P (XEXP (XEXP (op0, 0), 0))
10420 || ((tem = get_last_value (XEXP (XEXP (op0, 0), 0))) != 0
10421 && COMPARISON_P (tem))))
10423 op0 = XEXP (XEXP (op0, 0), 0);
10428 /* If we are doing an equality comparison of an AND of a bit equal
10429 to the sign bit, replace this with a LT or GE comparison of
10430 the underlying value. */
10431 if (equality_comparison_p
10433 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10434 && mode_width <= HOST_BITS_PER_WIDE_INT
10435 && ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
10436 == (unsigned HOST_WIDE_INT) 1 << (mode_width - 1)))
10438 op0 = XEXP (op0, 0);
10439 code = (code == EQ ? GE : LT);
10443 /* If this AND operation is really a ZERO_EXTEND from a narrower
10444 mode, the constant fits within that mode, and this is either an
10445 equality or unsigned comparison, try to do this comparison in
10446 the narrower mode. */
10447 if ((equality_comparison_p || unsigned_comparison_p)
10448 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10449 && (i = exact_log2 ((INTVAL (XEXP (op0, 1))
10450 & GET_MODE_MASK (mode))
10452 && const_op >> i == 0
10453 && (tmode = mode_for_size (i, MODE_INT, 1)) != BLKmode)
10455 op0 = gen_lowpart (tmode, XEXP (op0, 0));
10459 /* If this is (and:M1 (subreg:M2 X 0) (const_int C1)) where C1
10460 fits in both M1 and M2 and the SUBREG is either paradoxical
10461 or represents the low part, permute the SUBREG and the AND
10463 if (GET_CODE (XEXP (op0, 0)) == SUBREG)
10465 unsigned HOST_WIDE_INT c1;
10466 tmode = GET_MODE (SUBREG_REG (XEXP (op0, 0)));
10467 /* Require an integral mode, to avoid creating something like
10469 if (SCALAR_INT_MODE_P (tmode)
10470 /* It is unsafe to commute the AND into the SUBREG if the
10471 SUBREG is paradoxical and WORD_REGISTER_OPERATIONS is
10472 not defined. As originally written the upper bits
10473 have a defined value due to the AND operation.
10474 However, if we commute the AND inside the SUBREG then
10475 they no longer have defined values and the meaning of
10476 the code has been changed. */
10478 #ifdef WORD_REGISTER_OPERATIONS
10479 || (mode_width > GET_MODE_BITSIZE (tmode)
10480 && mode_width <= BITS_PER_WORD)
10482 || (mode_width <= GET_MODE_BITSIZE (tmode)
10483 && subreg_lowpart_p (XEXP (op0, 0))))
10484 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10485 && mode_width <= HOST_BITS_PER_WIDE_INT
10486 && GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT
10487 && ((c1 = INTVAL (XEXP (op0, 1))) & ~mask) == 0
10488 && (c1 & ~GET_MODE_MASK (tmode)) == 0
10490 && c1 != GET_MODE_MASK (tmode))
10492 op0 = simplify_gen_binary (AND, tmode,
10493 SUBREG_REG (XEXP (op0, 0)),
10494 gen_int_mode (c1, tmode));
10495 op0 = gen_lowpart (mode, op0);
10500 /* Convert (ne (and (not X) 1) 0) to (eq (and X 1) 0). */
10501 if (const_op == 0 && equality_comparison_p
10502 && XEXP (op0, 1) == const1_rtx
10503 && GET_CODE (XEXP (op0, 0)) == NOT)
10505 op0 = simplify_and_const_int
10506 (NULL_RTX, mode, XEXP (XEXP (op0, 0), 0), (HOST_WIDE_INT) 1);
10507 code = (code == NE ? EQ : NE);
10511 /* Convert (ne (and (lshiftrt (not X)) 1) 0) to
10512 (eq (and (lshiftrt X) 1) 0).
10513 Also handle the case where (not X) is expressed using xor. */
10514 if (const_op == 0 && equality_comparison_p
10515 && XEXP (op0, 1) == const1_rtx
10516 && GET_CODE (XEXP (op0, 0)) == LSHIFTRT)
10518 rtx shift_op = XEXP (XEXP (op0, 0), 0);
10519 rtx shift_count = XEXP (XEXP (op0, 0), 1);
10521 if (GET_CODE (shift_op) == NOT
10522 || (GET_CODE (shift_op) == XOR
10523 && GET_CODE (XEXP (shift_op, 1)) == CONST_INT
10524 && GET_CODE (shift_count) == CONST_INT
10525 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
10526 && (INTVAL (XEXP (shift_op, 1))
10527 == (HOST_WIDE_INT) 1 << INTVAL (shift_count))))
10529 op0 = simplify_and_const_int
10531 gen_rtx_LSHIFTRT (mode, XEXP (shift_op, 0), shift_count),
10532 (HOST_WIDE_INT) 1);
10533 code = (code == NE ? EQ : NE);
10540 /* If we have (compare (ashift FOO N) (const_int C)) and
10541 the high order N bits of FOO (N+1 if an inequality comparison)
10542 are known to be zero, we can do this by comparing FOO with C
10543 shifted right N bits so long as the low-order N bits of C are
10545 if (GET_CODE (XEXP (op0, 1)) == CONST_INT
10546 && INTVAL (XEXP (op0, 1)) >= 0
10547 && ((INTVAL (XEXP (op0, 1)) + ! equality_comparison_p)
10548 < HOST_BITS_PER_WIDE_INT)
10550 & (((HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1))) - 1)) == 0)
10551 && mode_width <= HOST_BITS_PER_WIDE_INT
10552 && (nonzero_bits (XEXP (op0, 0), mode)
10553 & ~(mask >> (INTVAL (XEXP (op0, 1))
10554 + ! equality_comparison_p))) == 0)
10556 /* We must perform a logical shift, not an arithmetic one,
10557 as we want the top N bits of C to be zero. */
10558 unsigned HOST_WIDE_INT temp = const_op & GET_MODE_MASK (mode);
10560 temp >>= INTVAL (XEXP (op0, 1));
10561 op1 = gen_int_mode (temp, mode);
10562 op0 = XEXP (op0, 0);
10566 /* If we are doing a sign bit comparison, it means we are testing
10567 a particular bit. Convert it to the appropriate AND. */
10568 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 1)) == CONST_INT
10569 && mode_width <= HOST_BITS_PER_WIDE_INT)
10571 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
10574 - INTVAL (XEXP (op0, 1)))));
10575 code = (code == LT ? NE : EQ);
10579 /* If this an equality comparison with zero and we are shifting
10580 the low bit to the sign bit, we can convert this to an AND of the
10582 if (const_op == 0 && equality_comparison_p
10583 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10584 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (op0, 1))
10587 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
10588 (HOST_WIDE_INT) 1);
10594 /* If this is an equality comparison with zero, we can do this
10595 as a logical shift, which might be much simpler. */
10596 if (equality_comparison_p && const_op == 0
10597 && GET_CODE (XEXP (op0, 1)) == CONST_INT)
10599 op0 = simplify_shift_const (NULL_RTX, LSHIFTRT, mode,
10601 INTVAL (XEXP (op0, 1)));
10605 /* If OP0 is a sign extension and CODE is not an unsigned comparison,
10606 do the comparison in a narrower mode. */
10607 if (! unsigned_comparison_p
10608 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10609 && GET_CODE (XEXP (op0, 0)) == ASHIFT
10610 && XEXP (op0, 1) == XEXP (XEXP (op0, 0), 1)
10611 && (tmode = mode_for_size (mode_width - INTVAL (XEXP (op0, 1)),
10612 MODE_INT, 1)) != BLKmode
10613 && (((unsigned HOST_WIDE_INT) const_op
10614 + (GET_MODE_MASK (tmode) >> 1) + 1)
10615 <= GET_MODE_MASK (tmode)))
10617 op0 = gen_lowpart (tmode, XEXP (XEXP (op0, 0), 0));
10621 /* Likewise if OP0 is a PLUS of a sign extension with a
10622 constant, which is usually represented with the PLUS
10623 between the shifts. */
10624 if (! unsigned_comparison_p
10625 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10626 && GET_CODE (XEXP (op0, 0)) == PLUS
10627 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
10628 && GET_CODE (XEXP (XEXP (op0, 0), 0)) == ASHIFT
10629 && XEXP (op0, 1) == XEXP (XEXP (XEXP (op0, 0), 0), 1)
10630 && (tmode = mode_for_size (mode_width - INTVAL (XEXP (op0, 1)),
10631 MODE_INT, 1)) != BLKmode
10632 && (((unsigned HOST_WIDE_INT) const_op
10633 + (GET_MODE_MASK (tmode) >> 1) + 1)
10634 <= GET_MODE_MASK (tmode)))
10636 rtx inner = XEXP (XEXP (XEXP (op0, 0), 0), 0);
10637 rtx add_const = XEXP (XEXP (op0, 0), 1);
10638 rtx new_const = simplify_gen_binary (ASHIFTRT, GET_MODE (op0),
10639 add_const, XEXP (op0, 1));
10641 op0 = simplify_gen_binary (PLUS, tmode,
10642 gen_lowpart (tmode, inner),
10647 /* ... fall through ... */
10649 /* If we have (compare (xshiftrt FOO N) (const_int C)) and
10650 the low order N bits of FOO are known to be zero, we can do this
10651 by comparing FOO with C shifted left N bits so long as no
10652 overflow occurs. */
10653 if (GET_CODE (XEXP (op0, 1)) == CONST_INT
10654 && INTVAL (XEXP (op0, 1)) >= 0
10655 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT
10656 && mode_width <= HOST_BITS_PER_WIDE_INT
10657 && (nonzero_bits (XEXP (op0, 0), mode)
10658 & (((HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1))) - 1)) == 0
10659 && (((unsigned HOST_WIDE_INT) const_op
10660 + (GET_CODE (op0) != LSHIFTRT
10661 ? ((GET_MODE_MASK (mode) >> INTVAL (XEXP (op0, 1)) >> 1)
10664 <= GET_MODE_MASK (mode) >> INTVAL (XEXP (op0, 1))))
10666 /* If the shift was logical, then we must make the condition
10668 if (GET_CODE (op0) == LSHIFTRT)
10669 code = unsigned_condition (code);
10671 const_op <<= INTVAL (XEXP (op0, 1));
10672 op1 = GEN_INT (const_op);
10673 op0 = XEXP (op0, 0);
10677 /* If we are using this shift to extract just the sign bit, we
10678 can replace this with an LT or GE comparison. */
10680 && (equality_comparison_p || sign_bit_comparison_p)
10681 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10682 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (op0, 1))
10685 op0 = XEXP (op0, 0);
10686 code = (code == NE || code == GT ? LT : GE);
10698 /* Now make any compound operations involved in this comparison. Then,
10699 check for an outmost SUBREG on OP0 that is not doing anything or is
10700 paradoxical. The latter transformation must only be performed when
10701 it is known that the "extra" bits will be the same in op0 and op1 or
10702 that they don't matter. There are three cases to consider:
10704 1. SUBREG_REG (op0) is a register. In this case the bits are don't
10705 care bits and we can assume they have any convenient value. So
10706 making the transformation is safe.
10708 2. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is not defined.
10709 In this case the upper bits of op0 are undefined. We should not make
10710 the simplification in that case as we do not know the contents of
10713 3. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is defined and not
10714 UNKNOWN. In that case we know those bits are zeros or ones. We must
10715 also be sure that they are the same as the upper bits of op1.
10717 We can never remove a SUBREG for a non-equality comparison because
10718 the sign bit is in a different place in the underlying object. */
10720 op0 = make_compound_operation (op0, op1 == const0_rtx ? COMPARE : SET);
10721 op1 = make_compound_operation (op1, SET);
10723 if (GET_CODE (op0) == SUBREG && subreg_lowpart_p (op0)
10724 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
10725 && GET_MODE_CLASS (GET_MODE (SUBREG_REG (op0))) == MODE_INT
10726 && (code == NE || code == EQ))
10728 if (GET_MODE_SIZE (GET_MODE (op0))
10729 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (op0))))
10731 /* For paradoxical subregs, allow case 1 as above. Case 3 isn't
10733 if (REG_P (SUBREG_REG (op0)))
10735 op0 = SUBREG_REG (op0);
10736 op1 = gen_lowpart (GET_MODE (op0), op1);
10739 else if ((GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0)))
10740 <= HOST_BITS_PER_WIDE_INT)
10741 && (nonzero_bits (SUBREG_REG (op0),
10742 GET_MODE (SUBREG_REG (op0)))
10743 & ~GET_MODE_MASK (GET_MODE (op0))) == 0)
10745 tem = gen_lowpart (GET_MODE (SUBREG_REG (op0)), op1);
10747 if ((nonzero_bits (tem, GET_MODE (SUBREG_REG (op0)))
10748 & ~GET_MODE_MASK (GET_MODE (op0))) == 0)
10749 op0 = SUBREG_REG (op0), op1 = tem;
10753 /* We now do the opposite procedure: Some machines don't have compare
10754 insns in all modes. If OP0's mode is an integer mode smaller than a
10755 word and we can't do a compare in that mode, see if there is a larger
10756 mode for which we can do the compare. There are a number of cases in
10757 which we can use the wider mode. */
10759 mode = GET_MODE (op0);
10760 if (mode != VOIDmode && GET_MODE_CLASS (mode) == MODE_INT
10761 && GET_MODE_SIZE (mode) < UNITS_PER_WORD
10762 && ! have_insn_for (COMPARE, mode))
10763 for (tmode = GET_MODE_WIDER_MODE (mode);
10765 && GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT);
10766 tmode = GET_MODE_WIDER_MODE (tmode))
10767 if (have_insn_for (COMPARE, tmode))
10771 /* If the only nonzero bits in OP0 and OP1 are those in the
10772 narrower mode and this is an equality or unsigned comparison,
10773 we can use the wider mode. Similarly for sign-extended
10774 values, in which case it is true for all comparisons. */
10775 zero_extended = ((code == EQ || code == NE
10776 || code == GEU || code == GTU
10777 || code == LEU || code == LTU)
10778 && (nonzero_bits (op0, tmode)
10779 & ~GET_MODE_MASK (mode)) == 0
10780 && ((GET_CODE (op1) == CONST_INT
10781 || (nonzero_bits (op1, tmode)
10782 & ~GET_MODE_MASK (mode)) == 0)));
10785 || ((num_sign_bit_copies (op0, tmode)
10786 > (unsigned int) (GET_MODE_BITSIZE (tmode)
10787 - GET_MODE_BITSIZE (mode)))
10788 && (num_sign_bit_copies (op1, tmode)
10789 > (unsigned int) (GET_MODE_BITSIZE (tmode)
10790 - GET_MODE_BITSIZE (mode)))))
10792 /* If OP0 is an AND and we don't have an AND in MODE either,
10793 make a new AND in the proper mode. */
10794 if (GET_CODE (op0) == AND
10795 && !have_insn_for (AND, mode))
10796 op0 = simplify_gen_binary (AND, tmode,
10797 gen_lowpart (tmode,
10799 gen_lowpart (tmode,
10802 op0 = gen_lowpart (tmode, op0);
10803 if (zero_extended && GET_CODE (op1) == CONST_INT)
10804 op1 = GEN_INT (INTVAL (op1) & GET_MODE_MASK (mode));
10805 op1 = gen_lowpart (tmode, op1);
10809 /* If this is a test for negative, we can make an explicit
10810 test of the sign bit. */
10812 if (op1 == const0_rtx && (code == LT || code == GE)
10813 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
10815 op0 = simplify_gen_binary (AND, tmode,
10816 gen_lowpart (tmode, op0),
10817 GEN_INT ((HOST_WIDE_INT) 1
10818 << (GET_MODE_BITSIZE (mode)
10820 code = (code == LT) ? NE : EQ;
10825 #ifdef CANONICALIZE_COMPARISON
10826 /* If this machine only supports a subset of valid comparisons, see if we
10827 can convert an unsupported one into a supported one. */
10828 CANONICALIZE_COMPARISON (code, op0, op1);
10837 /* Utility function for record_value_for_reg. Count number of
10842 enum rtx_code code = GET_CODE (x);
10846 if (GET_RTX_CLASS (code) == '2'
10847 || GET_RTX_CLASS (code) == 'c')
10849 rtx x0 = XEXP (x, 0);
10850 rtx x1 = XEXP (x, 1);
10853 return 1 + 2 * count_rtxs (x0);
10855 if ((GET_RTX_CLASS (GET_CODE (x1)) == '2'
10856 || GET_RTX_CLASS (GET_CODE (x1)) == 'c')
10857 && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1)))
10858 return 2 + 2 * count_rtxs (x0)
10859 + count_rtxs (x == XEXP (x1, 0)
10860 ? XEXP (x1, 1) : XEXP (x1, 0));
10862 if ((GET_RTX_CLASS (GET_CODE (x0)) == '2'
10863 || GET_RTX_CLASS (GET_CODE (x0)) == 'c')
10864 && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1)))
10865 return 2 + 2 * count_rtxs (x1)
10866 + count_rtxs (x == XEXP (x0, 0)
10867 ? XEXP (x0, 1) : XEXP (x0, 0));
10870 fmt = GET_RTX_FORMAT (code);
10871 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
10873 ret += count_rtxs (XEXP (x, i));
10878 /* Utility function for following routine. Called when X is part of a value
10879 being stored into last_set_value. Sets last_set_table_tick
10880 for each register mentioned. Similar to mention_regs in cse.c */
10883 update_table_tick (rtx x)
10885 enum rtx_code code = GET_CODE (x);
10886 const char *fmt = GET_RTX_FORMAT (code);
10891 unsigned int regno = REGNO (x);
10892 unsigned int endregno
10893 = regno + (regno < FIRST_PSEUDO_REGISTER
10894 ? hard_regno_nregs[regno][GET_MODE (x)] : 1);
10897 for (r = regno; r < endregno; r++)
10898 reg_stat[r].last_set_table_tick = label_tick;
10903 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
10904 /* Note that we can't have an "E" in values stored; see
10905 get_last_value_validate. */
10908 /* Check for identical subexpressions. If x contains
10909 identical subexpression we only have to traverse one of
10911 if (i == 0 && ARITHMETIC_P (x))
10913 /* Note that at this point x1 has already been
10915 rtx x0 = XEXP (x, 0);
10916 rtx x1 = XEXP (x, 1);
10918 /* If x0 and x1 are identical then there is no need to
10923 /* If x0 is identical to a subexpression of x1 then while
10924 processing x1, x0 has already been processed. Thus we
10925 are done with x. */
10926 if (ARITHMETIC_P (x1)
10927 && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1)))
10930 /* If x1 is identical to a subexpression of x0 then we
10931 still have to process the rest of x0. */
10932 if (ARITHMETIC_P (x0)
10933 && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1)))
10935 update_table_tick (XEXP (x0, x1 == XEXP (x0, 0) ? 1 : 0));
10940 update_table_tick (XEXP (x, i));
10944 /* Record that REG is set to VALUE in insn INSN. If VALUE is zero, we
10945 are saying that the register is clobbered and we no longer know its
10946 value. If INSN is zero, don't update reg_stat[].last_set; this is
10947 only permitted with VALUE also zero and is used to invalidate the
10951 record_value_for_reg (rtx reg, rtx insn, rtx value)
10953 unsigned int regno = REGNO (reg);
10954 unsigned int endregno
10955 = regno + (regno < FIRST_PSEUDO_REGISTER
10956 ? hard_regno_nregs[regno][GET_MODE (reg)] : 1);
10959 /* If VALUE contains REG and we have a previous value for REG, substitute
10960 the previous value. */
10961 if (value && insn && reg_overlap_mentioned_p (reg, value))
10965 /* Set things up so get_last_value is allowed to see anything set up to
10967 subst_low_cuid = INSN_CUID (insn);
10968 tem = get_last_value (reg);
10970 /* If TEM is simply a binary operation with two CLOBBERs as operands,
10971 it isn't going to be useful and will take a lot of time to process,
10972 so just use the CLOBBER. */
10976 if (ARITHMETIC_P (tem)
10977 && GET_CODE (XEXP (tem, 0)) == CLOBBER
10978 && GET_CODE (XEXP (tem, 1)) == CLOBBER)
10979 tem = XEXP (tem, 0);
10980 else if (count_occurrences (value, reg, 1) >= 2)
10982 /* If there are two or more occurrences of REG in VALUE,
10983 prevent the value from growing too much. */
10984 if (count_rtxs (tem) > MAX_LAST_VALUE_RTL)
10985 tem = gen_rtx_CLOBBER (GET_MODE (tem), const0_rtx);
10988 value = replace_rtx (copy_rtx (value), reg, tem);
10992 /* For each register modified, show we don't know its value, that
10993 we don't know about its bitwise content, that its value has been
10994 updated, and that we don't know the location of the death of the
10996 for (i = regno; i < endregno; i++)
10999 reg_stat[i].last_set = insn;
11001 reg_stat[i].last_set_value = 0;
11002 reg_stat[i].last_set_mode = 0;
11003 reg_stat[i].last_set_nonzero_bits = 0;
11004 reg_stat[i].last_set_sign_bit_copies = 0;
11005 reg_stat[i].last_death = 0;
11008 /* Mark registers that are being referenced in this value. */
11010 update_table_tick (value);
11012 /* Now update the status of each register being set.
11013 If someone is using this register in this block, set this register
11014 to invalid since we will get confused between the two lives in this
11015 basic block. This makes using this register always invalid. In cse, we
11016 scan the table to invalidate all entries using this register, but this
11017 is too much work for us. */
11019 for (i = regno; i < endregno; i++)
11021 reg_stat[i].last_set_label = label_tick;
11022 if (value && reg_stat[i].last_set_table_tick == label_tick)
11023 reg_stat[i].last_set_invalid = 1;
11025 reg_stat[i].last_set_invalid = 0;
11028 /* The value being assigned might refer to X (like in "x++;"). In that
11029 case, we must replace it with (clobber (const_int 0)) to prevent
11031 if (value && ! get_last_value_validate (&value, insn,
11032 reg_stat[regno].last_set_label, 0))
11034 value = copy_rtx (value);
11035 if (! get_last_value_validate (&value, insn,
11036 reg_stat[regno].last_set_label, 1))
11040 /* For the main register being modified, update the value, the mode, the
11041 nonzero bits, and the number of sign bit copies. */
11043 reg_stat[regno].last_set_value = value;
11047 enum machine_mode mode = GET_MODE (reg);
11048 subst_low_cuid = INSN_CUID (insn);
11049 reg_stat[regno].last_set_mode = mode;
11050 if (GET_MODE_CLASS (mode) == MODE_INT
11051 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
11052 mode = nonzero_bits_mode;
11053 reg_stat[regno].last_set_nonzero_bits = nonzero_bits (value, mode);
11054 reg_stat[regno].last_set_sign_bit_copies
11055 = num_sign_bit_copies (value, GET_MODE (reg));
11059 /* Called via note_stores from record_dead_and_set_regs to handle one
11060 SET or CLOBBER in an insn. DATA is the instruction in which the
11061 set is occurring. */
11064 record_dead_and_set_regs_1 (rtx dest, rtx setter, void *data)
11066 rtx record_dead_insn = (rtx) data;
11068 if (GET_CODE (dest) == SUBREG)
11069 dest = SUBREG_REG (dest);
11073 /* If we are setting the whole register, we know its value. Otherwise
11074 show that we don't know the value. We can handle SUBREG in
11076 if (GET_CODE (setter) == SET && dest == SET_DEST (setter))
11077 record_value_for_reg (dest, record_dead_insn, SET_SRC (setter));
11078 else if (GET_CODE (setter) == SET
11079 && GET_CODE (SET_DEST (setter)) == SUBREG
11080 && SUBREG_REG (SET_DEST (setter)) == dest
11081 && GET_MODE_BITSIZE (GET_MODE (dest)) <= BITS_PER_WORD
11082 && subreg_lowpart_p (SET_DEST (setter)))
11083 record_value_for_reg (dest, record_dead_insn,
11084 gen_lowpart (GET_MODE (dest),
11085 SET_SRC (setter)));
11087 record_value_for_reg (dest, record_dead_insn, NULL_RTX);
11089 else if (MEM_P (dest)
11090 /* Ignore pushes, they clobber nothing. */
11091 && ! push_operand (dest, GET_MODE (dest)))
11092 mem_last_set = INSN_CUID (record_dead_insn);
11095 /* Update the records of when each REG was most recently set or killed
11096 for the things done by INSN. This is the last thing done in processing
11097 INSN in the combiner loop.
11099 We update reg_stat[], in particular fields last_set, last_set_value,
11100 last_set_mode, last_set_nonzero_bits, last_set_sign_bit_copies,
11101 last_death, and also the similar information mem_last_set (which insn
11102 most recently modified memory) and last_call_cuid (which insn was the
11103 most recent subroutine call). */
11106 record_dead_and_set_regs (rtx insn)
11111 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
11113 if (REG_NOTE_KIND (link) == REG_DEAD
11114 && REG_P (XEXP (link, 0)))
11116 unsigned int regno = REGNO (XEXP (link, 0));
11117 unsigned int endregno
11118 = regno + (regno < FIRST_PSEUDO_REGISTER
11119 ? hard_regno_nregs[regno][GET_MODE (XEXP (link, 0))]
11122 for (i = regno; i < endregno; i++)
11123 reg_stat[i].last_death = insn;
11125 else if (REG_NOTE_KIND (link) == REG_INC)
11126 record_value_for_reg (XEXP (link, 0), insn, NULL_RTX);
11131 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
11132 if (TEST_HARD_REG_BIT (regs_invalidated_by_call, i))
11134 reg_stat[i].last_set_value = 0;
11135 reg_stat[i].last_set_mode = 0;
11136 reg_stat[i].last_set_nonzero_bits = 0;
11137 reg_stat[i].last_set_sign_bit_copies = 0;
11138 reg_stat[i].last_death = 0;
11141 last_call_cuid = mem_last_set = INSN_CUID (insn);
11143 /* Don't bother recording what this insn does. It might set the
11144 return value register, but we can't combine into a call
11145 pattern anyway, so there's no point trying (and it may cause
11146 a crash, if e.g. we wind up asking for last_set_value of a
11147 SUBREG of the return value register). */
11151 note_stores (PATTERN (insn), record_dead_and_set_regs_1, insn);
11154 /* If a SUBREG has the promoted bit set, it is in fact a property of the
11155 register present in the SUBREG, so for each such SUBREG go back and
11156 adjust nonzero and sign bit information of the registers that are
11157 known to have some zero/sign bits set.
11159 This is needed because when combine blows the SUBREGs away, the
11160 information on zero/sign bits is lost and further combines can be
11161 missed because of that. */
11164 record_promoted_value (rtx insn, rtx subreg)
11167 unsigned int regno = REGNO (SUBREG_REG (subreg));
11168 enum machine_mode mode = GET_MODE (subreg);
11170 if (GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT)
11173 for (links = LOG_LINKS (insn); links;)
11175 insn = XEXP (links, 0);
11176 set = single_set (insn);
11178 if (! set || !REG_P (SET_DEST (set))
11179 || REGNO (SET_DEST (set)) != regno
11180 || GET_MODE (SET_DEST (set)) != GET_MODE (SUBREG_REG (subreg)))
11182 links = XEXP (links, 1);
11186 if (reg_stat[regno].last_set == insn)
11188 if (SUBREG_PROMOTED_UNSIGNED_P (subreg) > 0)
11189 reg_stat[regno].last_set_nonzero_bits &= GET_MODE_MASK (mode);
11192 if (REG_P (SET_SRC (set)))
11194 regno = REGNO (SET_SRC (set));
11195 links = LOG_LINKS (insn);
11202 /* Scan X for promoted SUBREGs. For each one found,
11203 note what it implies to the registers used in it. */
11206 check_promoted_subreg (rtx insn, rtx x)
11208 if (GET_CODE (x) == SUBREG && SUBREG_PROMOTED_VAR_P (x)
11209 && REG_P (SUBREG_REG (x)))
11210 record_promoted_value (insn, x);
11213 const char *format = GET_RTX_FORMAT (GET_CODE (x));
11216 for (i = 0; i < GET_RTX_LENGTH (GET_CODE (x)); i++)
11220 check_promoted_subreg (insn, XEXP (x, i));
11224 if (XVEC (x, i) != 0)
11225 for (j = 0; j < XVECLEN (x, i); j++)
11226 check_promoted_subreg (insn, XVECEXP (x, i, j));
11232 /* Utility routine for the following function. Verify that all the registers
11233 mentioned in *LOC are valid when *LOC was part of a value set when
11234 label_tick == TICK. Return 0 if some are not.
11236 If REPLACE is nonzero, replace the invalid reference with
11237 (clobber (const_int 0)) and return 1. This replacement is useful because
11238 we often can get useful information about the form of a value (e.g., if
11239 it was produced by a shift that always produces -1 or 0) even though
11240 we don't know exactly what registers it was produced from. */
11243 get_last_value_validate (rtx *loc, rtx insn, int tick, int replace)
11246 const char *fmt = GET_RTX_FORMAT (GET_CODE (x));
11247 int len = GET_RTX_LENGTH (GET_CODE (x));
11252 unsigned int regno = REGNO (x);
11253 unsigned int endregno
11254 = regno + (regno < FIRST_PSEUDO_REGISTER
11255 ? hard_regno_nregs[regno][GET_MODE (x)] : 1);
11258 for (j = regno; j < endregno; j++)
11259 if (reg_stat[j].last_set_invalid
11260 /* If this is a pseudo-register that was only set once and not
11261 live at the beginning of the function, it is always valid. */
11262 || (! (regno >= FIRST_PSEUDO_REGISTER
11263 && REG_N_SETS (regno) == 1
11264 && (! REGNO_REG_SET_P
11265 (ENTRY_BLOCK_PTR->next_bb->il.rtl->global_live_at_start,
11267 && reg_stat[j].last_set_label > tick))
11270 *loc = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
11276 /* If this is a memory reference, make sure that there were
11277 no stores after it that might have clobbered the value. We don't
11278 have alias info, so we assume any store invalidates it. */
11279 else if (MEM_P (x) && !MEM_READONLY_P (x)
11280 && INSN_CUID (insn) <= mem_last_set)
11283 *loc = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
11287 for (i = 0; i < len; i++)
11291 /* Check for identical subexpressions. If x contains
11292 identical subexpression we only have to traverse one of
11294 if (i == 1 && ARITHMETIC_P (x))
11296 /* Note that at this point x0 has already been checked
11297 and found valid. */
11298 rtx x0 = XEXP (x, 0);
11299 rtx x1 = XEXP (x, 1);
11301 /* If x0 and x1 are identical then x is also valid. */
11305 /* If x1 is identical to a subexpression of x0 then
11306 while checking x0, x1 has already been checked. Thus
11307 it is valid and so as x. */
11308 if (ARITHMETIC_P (x0)
11309 && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1)))
11312 /* If x0 is identical to a subexpression of x1 then x is
11313 valid iff the rest of x1 is valid. */
11314 if (ARITHMETIC_P (x1)
11315 && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1)))
11317 get_last_value_validate (&XEXP (x1,
11318 x0 == XEXP (x1, 0) ? 1 : 0),
11319 insn, tick, replace);
11322 if (get_last_value_validate (&XEXP (x, i), insn, tick,
11326 /* Don't bother with these. They shouldn't occur anyway. */
11327 else if (fmt[i] == 'E')
11331 /* If we haven't found a reason for it to be invalid, it is valid. */
11335 /* Get the last value assigned to X, if known. Some registers
11336 in the value may be replaced with (clobber (const_int 0)) if their value
11337 is known longer known reliably. */
11340 get_last_value (rtx x)
11342 unsigned int regno;
11345 /* If this is a non-paradoxical SUBREG, get the value of its operand and
11346 then convert it to the desired mode. If this is a paradoxical SUBREG,
11347 we cannot predict what values the "extra" bits might have. */
11348 if (GET_CODE (x) == SUBREG
11349 && subreg_lowpart_p (x)
11350 && (GET_MODE_SIZE (GET_MODE (x))
11351 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
11352 && (value = get_last_value (SUBREG_REG (x))) != 0)
11353 return gen_lowpart (GET_MODE (x), value);
11359 value = reg_stat[regno].last_set_value;
11361 /* If we don't have a value, or if it isn't for this basic block and
11362 it's either a hard register, set more than once, or it's a live
11363 at the beginning of the function, return 0.
11365 Because if it's not live at the beginning of the function then the reg
11366 is always set before being used (is never used without being set).
11367 And, if it's set only once, and it's always set before use, then all
11368 uses must have the same last value, even if it's not from this basic
11372 || (reg_stat[regno].last_set_label != label_tick
11373 && (regno < FIRST_PSEUDO_REGISTER
11374 || REG_N_SETS (regno) != 1
11375 || (REGNO_REG_SET_P
11376 (ENTRY_BLOCK_PTR->next_bb->il.rtl->global_live_at_start,
11380 /* If the value was set in a later insn than the ones we are processing,
11381 we can't use it even if the register was only set once. */
11382 if (INSN_CUID (reg_stat[regno].last_set) >= subst_low_cuid)
11385 /* If the value has all its registers valid, return it. */
11386 if (get_last_value_validate (&value, reg_stat[regno].last_set,
11387 reg_stat[regno].last_set_label, 0))
11390 /* Otherwise, make a copy and replace any invalid register with
11391 (clobber (const_int 0)). If that fails for some reason, return 0. */
11393 value = copy_rtx (value);
11394 if (get_last_value_validate (&value, reg_stat[regno].last_set,
11395 reg_stat[regno].last_set_label, 1))
11401 /* Return nonzero if expression X refers to a REG or to memory
11402 that is set in an instruction more recent than FROM_CUID. */
11405 use_crosses_set_p (rtx x, int from_cuid)
11409 enum rtx_code code = GET_CODE (x);
11413 unsigned int regno = REGNO (x);
11414 unsigned endreg = regno + (regno < FIRST_PSEUDO_REGISTER
11415 ? hard_regno_nregs[regno][GET_MODE (x)] : 1);
11417 #ifdef PUSH_ROUNDING
11418 /* Don't allow uses of the stack pointer to be moved,
11419 because we don't know whether the move crosses a push insn. */
11420 if (regno == STACK_POINTER_REGNUM && PUSH_ARGS)
11423 for (; regno < endreg; regno++)
11424 if (reg_stat[regno].last_set
11425 && INSN_CUID (reg_stat[regno].last_set) > from_cuid)
11430 if (code == MEM && mem_last_set > from_cuid)
11433 fmt = GET_RTX_FORMAT (code);
11435 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
11440 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
11441 if (use_crosses_set_p (XVECEXP (x, i, j), from_cuid))
11444 else if (fmt[i] == 'e'
11445 && use_crosses_set_p (XEXP (x, i), from_cuid))
11451 /* Define three variables used for communication between the following
11454 static unsigned int reg_dead_regno, reg_dead_endregno;
11455 static int reg_dead_flag;
11457 /* Function called via note_stores from reg_dead_at_p.
11459 If DEST is within [reg_dead_regno, reg_dead_endregno), set
11460 reg_dead_flag to 1 if X is a CLOBBER and to -1 it is a SET. */
11463 reg_dead_at_p_1 (rtx dest, rtx x, void *data ATTRIBUTE_UNUSED)
11465 unsigned int regno, endregno;
11470 regno = REGNO (dest);
11471 endregno = regno + (regno < FIRST_PSEUDO_REGISTER
11472 ? hard_regno_nregs[regno][GET_MODE (dest)] : 1);
11474 if (reg_dead_endregno > regno && reg_dead_regno < endregno)
11475 reg_dead_flag = (GET_CODE (x) == CLOBBER) ? 1 : -1;
11478 /* Return nonzero if REG is known to be dead at INSN.
11480 We scan backwards from INSN. If we hit a REG_DEAD note or a CLOBBER
11481 referencing REG, it is dead. If we hit a SET referencing REG, it is
11482 live. Otherwise, see if it is live or dead at the start of the basic
11483 block we are in. Hard regs marked as being live in NEWPAT_USED_REGS
11484 must be assumed to be always live. */
11487 reg_dead_at_p (rtx reg, rtx insn)
11492 /* Set variables for reg_dead_at_p_1. */
11493 reg_dead_regno = REGNO (reg);
11494 reg_dead_endregno = reg_dead_regno + (reg_dead_regno < FIRST_PSEUDO_REGISTER
11495 ? hard_regno_nregs[reg_dead_regno]
11501 /* Check that reg isn't mentioned in NEWPAT_USED_REGS. For fixed registers
11502 we allow the machine description to decide whether use-and-clobber
11503 patterns are OK. */
11504 if (reg_dead_regno < FIRST_PSEUDO_REGISTER)
11506 for (i = reg_dead_regno; i < reg_dead_endregno; i++)
11507 if (!fixed_regs[i] && TEST_HARD_REG_BIT (newpat_used_regs, i))
11511 /* Scan backwards until we find a REG_DEAD note, SET, CLOBBER, label, or
11512 beginning of function. */
11513 for (; insn && !LABEL_P (insn) && !BARRIER_P (insn);
11514 insn = prev_nonnote_insn (insn))
11516 note_stores (PATTERN (insn), reg_dead_at_p_1, NULL);
11518 return reg_dead_flag == 1 ? 1 : 0;
11520 if (find_regno_note (insn, REG_DEAD, reg_dead_regno))
11524 /* Get the basic block that we were in. */
11526 block = ENTRY_BLOCK_PTR->next_bb;
11529 FOR_EACH_BB (block)
11530 if (insn == BB_HEAD (block))
11533 if (block == EXIT_BLOCK_PTR)
11537 for (i = reg_dead_regno; i < reg_dead_endregno; i++)
11538 if (REGNO_REG_SET_P (block->il.rtl->global_live_at_start, i))
11544 /* Note hard registers in X that are used. This code is similar to
11545 that in flow.c, but much simpler since we don't care about pseudos. */
11548 mark_used_regs_combine (rtx x)
11550 RTX_CODE code = GET_CODE (x);
11551 unsigned int regno;
11564 case ADDR_DIFF_VEC:
11567 /* CC0 must die in the insn after it is set, so we don't need to take
11568 special note of it here. */
11574 /* If we are clobbering a MEM, mark any hard registers inside the
11575 address as used. */
11576 if (MEM_P (XEXP (x, 0)))
11577 mark_used_regs_combine (XEXP (XEXP (x, 0), 0));
11582 /* A hard reg in a wide mode may really be multiple registers.
11583 If so, mark all of them just like the first. */
11584 if (regno < FIRST_PSEUDO_REGISTER)
11586 unsigned int endregno, r;
11588 /* None of this applies to the stack, frame or arg pointers. */
11589 if (regno == STACK_POINTER_REGNUM
11590 #if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM
11591 || regno == HARD_FRAME_POINTER_REGNUM
11593 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
11594 || (regno == ARG_POINTER_REGNUM && fixed_regs[regno])
11596 || regno == FRAME_POINTER_REGNUM)
11599 endregno = regno + hard_regno_nregs[regno][GET_MODE (x)];
11600 for (r = regno; r < endregno; r++)
11601 SET_HARD_REG_BIT (newpat_used_regs, r);
11607 /* If setting a MEM, or a SUBREG of a MEM, then note any hard regs in
11609 rtx testreg = SET_DEST (x);
11611 while (GET_CODE (testreg) == SUBREG
11612 || GET_CODE (testreg) == ZERO_EXTRACT
11613 || GET_CODE (testreg) == STRICT_LOW_PART)
11614 testreg = XEXP (testreg, 0);
11616 if (MEM_P (testreg))
11617 mark_used_regs_combine (XEXP (testreg, 0));
11619 mark_used_regs_combine (SET_SRC (x));
11627 /* Recursively scan the operands of this expression. */
11630 const char *fmt = GET_RTX_FORMAT (code);
11632 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
11635 mark_used_regs_combine (XEXP (x, i));
11636 else if (fmt[i] == 'E')
11640 for (j = 0; j < XVECLEN (x, i); j++)
11641 mark_used_regs_combine (XVECEXP (x, i, j));
11647 /* Remove register number REGNO from the dead registers list of INSN.
11649 Return the note used to record the death, if there was one. */
11652 remove_death (unsigned int regno, rtx insn)
11654 rtx note = find_regno_note (insn, REG_DEAD, regno);
11658 REG_N_DEATHS (regno)--;
11659 remove_note (insn, note);
11665 /* For each register (hardware or pseudo) used within expression X, if its
11666 death is in an instruction with cuid between FROM_CUID (inclusive) and
11667 TO_INSN (exclusive), put a REG_DEAD note for that register in the
11668 list headed by PNOTES.
11670 That said, don't move registers killed by maybe_kill_insn.
11672 This is done when X is being merged by combination into TO_INSN. These
11673 notes will then be distributed as needed. */
11676 move_deaths (rtx x, rtx maybe_kill_insn, int from_cuid, rtx to_insn,
11681 enum rtx_code code = GET_CODE (x);
11685 unsigned int regno = REGNO (x);
11686 rtx where_dead = reg_stat[regno].last_death;
11687 rtx before_dead, after_dead;
11689 /* Don't move the register if it gets killed in between from and to. */
11690 if (maybe_kill_insn && reg_set_p (x, maybe_kill_insn)
11691 && ! reg_referenced_p (x, maybe_kill_insn))
11694 /* WHERE_DEAD could be a USE insn made by combine, so first we
11695 make sure that we have insns with valid INSN_CUID values. */
11696 before_dead = where_dead;
11697 while (before_dead && INSN_UID (before_dead) > max_uid_cuid)
11698 before_dead = PREV_INSN (before_dead);
11700 after_dead = where_dead;
11701 while (after_dead && INSN_UID (after_dead) > max_uid_cuid)
11702 after_dead = NEXT_INSN (after_dead);
11704 if (before_dead && after_dead
11705 && INSN_CUID (before_dead) >= from_cuid
11706 && (INSN_CUID (after_dead) < INSN_CUID (to_insn)
11707 || (where_dead != after_dead
11708 && INSN_CUID (after_dead) == INSN_CUID (to_insn))))
11710 rtx note = remove_death (regno, where_dead);
11712 /* It is possible for the call above to return 0. This can occur
11713 when last_death points to I2 or I1 that we combined with.
11714 In that case make a new note.
11716 We must also check for the case where X is a hard register
11717 and NOTE is a death note for a range of hard registers
11718 including X. In that case, we must put REG_DEAD notes for
11719 the remaining registers in place of NOTE. */
11721 if (note != 0 && regno < FIRST_PSEUDO_REGISTER
11722 && (GET_MODE_SIZE (GET_MODE (XEXP (note, 0)))
11723 > GET_MODE_SIZE (GET_MODE (x))))
11725 unsigned int deadregno = REGNO (XEXP (note, 0));
11726 unsigned int deadend
11727 = (deadregno + hard_regno_nregs[deadregno]
11728 [GET_MODE (XEXP (note, 0))]);
11729 unsigned int ourend
11730 = regno + hard_regno_nregs[regno][GET_MODE (x)];
11733 for (i = deadregno; i < deadend; i++)
11734 if (i < regno || i >= ourend)
11735 REG_NOTES (where_dead)
11736 = gen_rtx_EXPR_LIST (REG_DEAD,
11738 REG_NOTES (where_dead));
11741 /* If we didn't find any note, or if we found a REG_DEAD note that
11742 covers only part of the given reg, and we have a multi-reg hard
11743 register, then to be safe we must check for REG_DEAD notes
11744 for each register other than the first. They could have
11745 their own REG_DEAD notes lying around. */
11746 else if ((note == 0
11748 && (GET_MODE_SIZE (GET_MODE (XEXP (note, 0)))
11749 < GET_MODE_SIZE (GET_MODE (x)))))
11750 && regno < FIRST_PSEUDO_REGISTER
11751 && hard_regno_nregs[regno][GET_MODE (x)] > 1)
11753 unsigned int ourend
11754 = regno + hard_regno_nregs[regno][GET_MODE (x)];
11755 unsigned int i, offset;
11759 offset = hard_regno_nregs[regno][GET_MODE (XEXP (note, 0))];
11763 for (i = regno + offset; i < ourend; i++)
11764 move_deaths (regno_reg_rtx[i],
11765 maybe_kill_insn, from_cuid, to_insn, &oldnotes);
11768 if (note != 0 && GET_MODE (XEXP (note, 0)) == GET_MODE (x))
11770 XEXP (note, 1) = *pnotes;
11774 *pnotes = gen_rtx_EXPR_LIST (REG_DEAD, x, *pnotes);
11776 REG_N_DEATHS (regno)++;
11782 else if (GET_CODE (x) == SET)
11784 rtx dest = SET_DEST (x);
11786 move_deaths (SET_SRC (x), maybe_kill_insn, from_cuid, to_insn, pnotes);
11788 /* In the case of a ZERO_EXTRACT, a STRICT_LOW_PART, or a SUBREG
11789 that accesses one word of a multi-word item, some
11790 piece of everything register in the expression is used by
11791 this insn, so remove any old death. */
11792 /* ??? So why do we test for equality of the sizes? */
11794 if (GET_CODE (dest) == ZERO_EXTRACT
11795 || GET_CODE (dest) == STRICT_LOW_PART
11796 || (GET_CODE (dest) == SUBREG
11797 && (((GET_MODE_SIZE (GET_MODE (dest))
11798 + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
11799 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (dest)))
11800 + UNITS_PER_WORD - 1) / UNITS_PER_WORD))))
11802 move_deaths (dest, maybe_kill_insn, from_cuid, to_insn, pnotes);
11806 /* If this is some other SUBREG, we know it replaces the entire
11807 value, so use that as the destination. */
11808 if (GET_CODE (dest) == SUBREG)
11809 dest = SUBREG_REG (dest);
11811 /* If this is a MEM, adjust deaths of anything used in the address.
11812 For a REG (the only other possibility), the entire value is
11813 being replaced so the old value is not used in this insn. */
11816 move_deaths (XEXP (dest, 0), maybe_kill_insn, from_cuid,
11821 else if (GET_CODE (x) == CLOBBER)
11824 len = GET_RTX_LENGTH (code);
11825 fmt = GET_RTX_FORMAT (code);
11827 for (i = 0; i < len; i++)
11832 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
11833 move_deaths (XVECEXP (x, i, j), maybe_kill_insn, from_cuid,
11836 else if (fmt[i] == 'e')
11837 move_deaths (XEXP (x, i), maybe_kill_insn, from_cuid, to_insn, pnotes);
11841 /* Return 1 if X is the target of a bit-field assignment in BODY, the
11842 pattern of an insn. X must be a REG. */
11845 reg_bitfield_target_p (rtx x, rtx body)
11849 if (GET_CODE (body) == SET)
11851 rtx dest = SET_DEST (body);
11853 unsigned int regno, tregno, endregno, endtregno;
11855 if (GET_CODE (dest) == ZERO_EXTRACT)
11856 target = XEXP (dest, 0);
11857 else if (GET_CODE (dest) == STRICT_LOW_PART)
11858 target = SUBREG_REG (XEXP (dest, 0));
11862 if (GET_CODE (target) == SUBREG)
11863 target = SUBREG_REG (target);
11865 if (!REG_P (target))
11868 tregno = REGNO (target), regno = REGNO (x);
11869 if (tregno >= FIRST_PSEUDO_REGISTER || regno >= FIRST_PSEUDO_REGISTER)
11870 return target == x;
11872 endtregno = tregno + hard_regno_nregs[tregno][GET_MODE (target)];
11873 endregno = regno + hard_regno_nregs[regno][GET_MODE (x)];
11875 return endregno > tregno && regno < endtregno;
11878 else if (GET_CODE (body) == PARALLEL)
11879 for (i = XVECLEN (body, 0) - 1; i >= 0; i--)
11880 if (reg_bitfield_target_p (x, XVECEXP (body, 0, i)))
11886 /* Given a chain of REG_NOTES originally from FROM_INSN, try to place them
11887 as appropriate. I3 and I2 are the insns resulting from the combination
11888 insns including FROM (I2 may be zero).
11890 Each note in the list is either ignored or placed on some insns, depending
11891 on the type of note. */
11894 distribute_notes (rtx notes, rtx from_insn, rtx i3, rtx i2)
11896 rtx note, next_note;
11899 for (note = notes; note; note = next_note)
11901 rtx place = 0, place2 = 0;
11903 /* If this NOTE references a pseudo register, ensure it references
11904 the latest copy of that register. */
11905 if (XEXP (note, 0) && REG_P (XEXP (note, 0))
11906 && REGNO (XEXP (note, 0)) >= FIRST_PSEUDO_REGISTER)
11907 XEXP (note, 0) = regno_reg_rtx[REGNO (XEXP (note, 0))];
11909 next_note = XEXP (note, 1);
11910 switch (REG_NOTE_KIND (note))
11914 /* Doesn't matter much where we put this, as long as it's somewhere.
11915 It is preferable to keep these notes on branches, which is most
11916 likely to be i3. */
11920 case REG_VALUE_PROFILE:
11921 /* Just get rid of this note, as it is unused later anyway. */
11924 case REG_NON_LOCAL_GOTO:
11929 gcc_assert (i2 && JUMP_P (i2));
11934 case REG_EH_REGION:
11935 /* These notes must remain with the call or trapping instruction. */
11938 else if (i2 && CALL_P (i2))
11942 gcc_assert (flag_non_call_exceptions);
11943 if (may_trap_p (i3))
11945 else if (i2 && may_trap_p (i2))
11947 /* ??? Otherwise assume we've combined things such that we
11948 can now prove that the instructions can't trap. Drop the
11949 note in this case. */
11955 /* These notes must remain with the call. It should not be
11956 possible for both I2 and I3 to be a call. */
11961 gcc_assert (i2 && CALL_P (i2));
11967 /* Any clobbers for i3 may still exist, and so we must process
11968 REG_UNUSED notes from that insn.
11970 Any clobbers from i2 or i1 can only exist if they were added by
11971 recog_for_combine. In that case, recog_for_combine created the
11972 necessary REG_UNUSED notes. Trying to keep any original
11973 REG_UNUSED notes from these insns can cause incorrect output
11974 if it is for the same register as the original i3 dest.
11975 In that case, we will notice that the register is set in i3,
11976 and then add a REG_UNUSED note for the destination of i3, which
11977 is wrong. However, it is possible to have REG_UNUSED notes from
11978 i2 or i1 for register which were both used and clobbered, so
11979 we keep notes from i2 or i1 if they will turn into REG_DEAD
11982 /* If this register is set or clobbered in I3, put the note there
11983 unless there is one already. */
11984 if (reg_set_p (XEXP (note, 0), PATTERN (i3)))
11986 if (from_insn != i3)
11989 if (! (REG_P (XEXP (note, 0))
11990 ? find_regno_note (i3, REG_UNUSED, REGNO (XEXP (note, 0)))
11991 : find_reg_note (i3, REG_UNUSED, XEXP (note, 0))))
11994 /* Otherwise, if this register is used by I3, then this register
11995 now dies here, so we must put a REG_DEAD note here unless there
11997 else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3))
11998 && ! (REG_P (XEXP (note, 0))
11999 ? find_regno_note (i3, REG_DEAD,
12000 REGNO (XEXP (note, 0)))
12001 : find_reg_note (i3, REG_DEAD, XEXP (note, 0))))
12003 PUT_REG_NOTE_KIND (note, REG_DEAD);
12011 /* These notes say something about results of an insn. We can
12012 only support them if they used to be on I3 in which case they
12013 remain on I3. Otherwise they are ignored.
12015 If the note refers to an expression that is not a constant, we
12016 must also ignore the note since we cannot tell whether the
12017 equivalence is still true. It might be possible to do
12018 slightly better than this (we only have a problem if I2DEST
12019 or I1DEST is present in the expression), but it doesn't
12020 seem worth the trouble. */
12022 if (from_insn == i3
12023 && (XEXP (note, 0) == 0 || CONSTANT_P (XEXP (note, 0))))
12028 case REG_NO_CONFLICT:
12029 /* These notes say something about how a register is used. They must
12030 be present on any use of the register in I2 or I3. */
12031 if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3)))
12034 if (i2 && reg_mentioned_p (XEXP (note, 0), PATTERN (i2)))
12044 /* This can show up in several ways -- either directly in the
12045 pattern, or hidden off in the constant pool with (or without?)
12046 a REG_EQUAL note. */
12047 /* ??? Ignore the without-reg_equal-note problem for now. */
12048 if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3))
12049 || ((tem = find_reg_note (i3, REG_EQUAL, NULL_RTX))
12050 && GET_CODE (XEXP (tem, 0)) == LABEL_REF
12051 && XEXP (XEXP (tem, 0), 0) == XEXP (note, 0)))
12055 && (reg_mentioned_p (XEXP (note, 0), PATTERN (i2))
12056 || ((tem = find_reg_note (i2, REG_EQUAL, NULL_RTX))
12057 && GET_CODE (XEXP (tem, 0)) == LABEL_REF
12058 && XEXP (XEXP (tem, 0), 0) == XEXP (note, 0))))
12066 /* Don't attach REG_LABEL note to a JUMP_INSN. Add
12067 a JUMP_LABEL instead or decrement LABEL_NUSES. */
12068 if (place && JUMP_P (place))
12070 rtx label = JUMP_LABEL (place);
12073 JUMP_LABEL (place) = XEXP (note, 0);
12076 gcc_assert (label == XEXP (note, 0));
12077 if (LABEL_P (label))
12078 LABEL_NUSES (label)--;
12082 if (place2 && JUMP_P (place2))
12084 rtx label = JUMP_LABEL (place2);
12087 JUMP_LABEL (place2) = XEXP (note, 0);
12090 gcc_assert (label == XEXP (note, 0));
12091 if (LABEL_P (label))
12092 LABEL_NUSES (label)--;
12099 /* This note says something about the value of a register prior
12100 to the execution of an insn. It is too much trouble to see
12101 if the note is still correct in all situations. It is better
12102 to simply delete it. */
12106 /* If the insn previously containing this note still exists,
12107 put it back where it was. Otherwise move it to the previous
12108 insn. Adjust the corresponding REG_LIBCALL note. */
12109 if (!NOTE_P (from_insn))
12113 tem = find_reg_note (XEXP (note, 0), REG_LIBCALL, NULL_RTX);
12114 place = prev_real_insn (from_insn);
12116 XEXP (tem, 0) = place;
12117 /* If we're deleting the last remaining instruction of a
12118 libcall sequence, don't add the notes. */
12119 else if (XEXP (note, 0) == from_insn)
12121 /* Don't add the dangling REG_RETVAL note. */
12128 /* This is handled similarly to REG_RETVAL. */
12129 if (!NOTE_P (from_insn))
12133 tem = find_reg_note (XEXP (note, 0), REG_RETVAL, NULL_RTX);
12134 place = next_real_insn (from_insn);
12136 XEXP (tem, 0) = place;
12137 /* If we're deleting the last remaining instruction of a
12138 libcall sequence, don't add the notes. */
12139 else if (XEXP (note, 0) == from_insn)
12141 /* Don't add the dangling REG_LIBCALL note. */
12148 /* If the register is used as an input in I3, it dies there.
12149 Similarly for I2, if it is nonzero and adjacent to I3.
12151 If the register is not used as an input in either I3 or I2
12152 and it is not one of the registers we were supposed to eliminate,
12153 there are two possibilities. We might have a non-adjacent I2
12154 or we might have somehow eliminated an additional register
12155 from a computation. For example, we might have had A & B where
12156 we discover that B will always be zero. In this case we will
12157 eliminate the reference to A.
12159 In both cases, we must search to see if we can find a previous
12160 use of A and put the death note there. */
12163 && CALL_P (from_insn)
12164 && find_reg_fusage (from_insn, USE, XEXP (note, 0)))
12166 else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3)))
12168 else if (i2 != 0 && next_nonnote_insn (i2) == i3
12169 && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
12174 basic_block bb = this_basic_block;
12176 for (tem = PREV_INSN (i3); place == 0; tem = PREV_INSN (tem))
12178 if (! INSN_P (tem))
12180 if (tem == BB_HEAD (bb))
12185 /* If the register is being set at TEM, see if that is all
12186 TEM is doing. If so, delete TEM. Otherwise, make this
12187 into a REG_UNUSED note instead. Don't delete sets to
12188 global register vars. */
12189 if ((REGNO (XEXP (note, 0)) >= FIRST_PSEUDO_REGISTER
12190 || !global_regs[REGNO (XEXP (note, 0))])
12191 && reg_set_p (XEXP (note, 0), PATTERN (tem)))
12193 rtx set = single_set (tem);
12194 rtx inner_dest = 0;
12196 rtx cc0_setter = NULL_RTX;
12200 for (inner_dest = SET_DEST (set);
12201 (GET_CODE (inner_dest) == STRICT_LOW_PART
12202 || GET_CODE (inner_dest) == SUBREG
12203 || GET_CODE (inner_dest) == ZERO_EXTRACT);
12204 inner_dest = XEXP (inner_dest, 0))
12207 /* Verify that it was the set, and not a clobber that
12208 modified the register.
12210 CC0 targets must be careful to maintain setter/user
12211 pairs. If we cannot delete the setter due to side
12212 effects, mark the user with an UNUSED note instead
12215 if (set != 0 && ! side_effects_p (SET_SRC (set))
12216 && rtx_equal_p (XEXP (note, 0), inner_dest)
12218 && (! reg_mentioned_p (cc0_rtx, SET_SRC (set))
12219 || ((cc0_setter = prev_cc0_setter (tem)) != NULL
12220 && sets_cc0_p (PATTERN (cc0_setter)) > 0))
12224 /* Move the notes and links of TEM elsewhere.
12225 This might delete other dead insns recursively.
12226 First set the pattern to something that won't use
12228 rtx old_notes = REG_NOTES (tem);
12230 PATTERN (tem) = pc_rtx;
12231 REG_NOTES (tem) = NULL;
12233 distribute_notes (old_notes, tem, tem, NULL_RTX);
12234 distribute_links (LOG_LINKS (tem));
12236 SET_INSN_DELETED (tem);
12239 /* Delete the setter too. */
12242 PATTERN (cc0_setter) = pc_rtx;
12243 old_notes = REG_NOTES (cc0_setter);
12244 REG_NOTES (cc0_setter) = NULL;
12246 distribute_notes (old_notes, cc0_setter,
12247 cc0_setter, NULL_RTX);
12248 distribute_links (LOG_LINKS (cc0_setter));
12250 SET_INSN_DELETED (cc0_setter);
12256 PUT_REG_NOTE_KIND (note, REG_UNUSED);
12258 /* If there isn't already a REG_UNUSED note, put one
12259 here. Do not place a REG_DEAD note, even if
12260 the register is also used here; that would not
12261 match the algorithm used in lifetime analysis
12262 and can cause the consistency check in the
12263 scheduler to fail. */
12264 if (! find_regno_note (tem, REG_UNUSED,
12265 REGNO (XEXP (note, 0))))
12270 else if (reg_referenced_p (XEXP (note, 0), PATTERN (tem))
12272 && find_reg_fusage (tem, USE, XEXP (note, 0))))
12276 /* If we are doing a 3->2 combination, and we have a
12277 register which formerly died in i3 and was not used
12278 by i2, which now no longer dies in i3 and is used in
12279 i2 but does not die in i2, and place is between i2
12280 and i3, then we may need to move a link from place to
12282 if (i2 && INSN_UID (place) <= max_uid_cuid
12283 && INSN_CUID (place) > INSN_CUID (i2)
12285 && INSN_CUID (from_insn) > INSN_CUID (i2)
12286 && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
12288 rtx links = LOG_LINKS (place);
12289 LOG_LINKS (place) = 0;
12290 distribute_links (links);
12295 if (tem == BB_HEAD (bb))
12299 /* We haven't found an insn for the death note and it
12300 is still a REG_DEAD note, but we have hit the beginning
12301 of the block. If the existing life info says the reg
12302 was dead, there's nothing left to do. Otherwise, we'll
12303 need to do a global life update after combine. */
12304 if (REG_NOTE_KIND (note) == REG_DEAD && place == 0
12305 && REGNO_REG_SET_P (bb->il.rtl->global_live_at_start,
12306 REGNO (XEXP (note, 0))))
12307 SET_BIT (refresh_blocks, this_basic_block->index);
12310 /* If the register is set or already dead at PLACE, we needn't do
12311 anything with this note if it is still a REG_DEAD note.
12312 We check here if it is set at all, not if is it totally replaced,
12313 which is what `dead_or_set_p' checks, so also check for it being
12316 if (place && REG_NOTE_KIND (note) == REG_DEAD)
12318 unsigned int regno = REGNO (XEXP (note, 0));
12320 /* Similarly, if the instruction on which we want to place
12321 the note is a noop, we'll need do a global live update
12322 after we remove them in delete_noop_moves. */
12323 if (noop_move_p (place))
12324 SET_BIT (refresh_blocks, this_basic_block->index);
12326 if (dead_or_set_p (place, XEXP (note, 0))
12327 || reg_bitfield_target_p (XEXP (note, 0), PATTERN (place)))
12329 /* Unless the register previously died in PLACE, clear
12330 last_death. [I no longer understand why this is
12332 if (reg_stat[regno].last_death != place)
12333 reg_stat[regno].last_death = 0;
12337 reg_stat[regno].last_death = place;
12339 /* If this is a death note for a hard reg that is occupying
12340 multiple registers, ensure that we are still using all
12341 parts of the object. If we find a piece of the object
12342 that is unused, we must arrange for an appropriate REG_DEAD
12343 note to be added for it. However, we can't just emit a USE
12344 and tag the note to it, since the register might actually
12345 be dead; so we recourse, and the recursive call then finds
12346 the previous insn that used this register. */
12348 if (place && regno < FIRST_PSEUDO_REGISTER
12349 && hard_regno_nregs[regno][GET_MODE (XEXP (note, 0))] > 1)
12351 unsigned int endregno
12352 = regno + hard_regno_nregs[regno]
12353 [GET_MODE (XEXP (note, 0))];
12357 for (i = regno; i < endregno; i++)
12358 if ((! refers_to_regno_p (i, i + 1, PATTERN (place), 0)
12359 && ! find_regno_fusage (place, USE, i))
12360 || dead_or_set_regno_p (place, i))
12365 /* Put only REG_DEAD notes for pieces that are
12366 not already dead or set. */
12368 for (i = regno; i < endregno;
12369 i += hard_regno_nregs[i][reg_raw_mode[i]])
12371 rtx piece = regno_reg_rtx[i];
12372 basic_block bb = this_basic_block;
12374 if (! dead_or_set_p (place, piece)
12375 && ! reg_bitfield_target_p (piece,
12379 = gen_rtx_EXPR_LIST (REG_DEAD, piece, NULL_RTX);
12381 distribute_notes (new_note, place, place,
12384 else if (! refers_to_regno_p (i, i + 1,
12385 PATTERN (place), 0)
12386 && ! find_regno_fusage (place, USE, i))
12387 for (tem = PREV_INSN (place); ;
12388 tem = PREV_INSN (tem))
12390 if (! INSN_P (tem))
12392 if (tem == BB_HEAD (bb))
12394 SET_BIT (refresh_blocks,
12395 this_basic_block->index);
12400 if (dead_or_set_p (tem, piece)
12401 || reg_bitfield_target_p (piece,
12405 = gen_rtx_EXPR_LIST (REG_UNUSED, piece,
12420 /* Any other notes should not be present at this point in the
12422 gcc_unreachable ();
12427 XEXP (note, 1) = REG_NOTES (place);
12428 REG_NOTES (place) = note;
12430 else if ((REG_NOTE_KIND (note) == REG_DEAD
12431 || REG_NOTE_KIND (note) == REG_UNUSED)
12432 && REG_P (XEXP (note, 0)))
12433 REG_N_DEATHS (REGNO (XEXP (note, 0)))--;
12437 if ((REG_NOTE_KIND (note) == REG_DEAD
12438 || REG_NOTE_KIND (note) == REG_UNUSED)
12439 && REG_P (XEXP (note, 0)))
12440 REG_N_DEATHS (REGNO (XEXP (note, 0)))++;
12442 REG_NOTES (place2) = gen_rtx_fmt_ee (GET_CODE (note),
12443 REG_NOTE_KIND (note),
12445 REG_NOTES (place2));
12450 /* Similarly to above, distribute the LOG_LINKS that used to be present on
12451 I3, I2, and I1 to new locations. This is also called to add a link
12452 pointing at I3 when I3's destination is changed. */
12455 distribute_links (rtx links)
12457 rtx link, next_link;
12459 for (link = links; link; link = next_link)
12465 next_link = XEXP (link, 1);
12467 /* If the insn that this link points to is a NOTE or isn't a single
12468 set, ignore it. In the latter case, it isn't clear what we
12469 can do other than ignore the link, since we can't tell which
12470 register it was for. Such links wouldn't be used by combine
12473 It is not possible for the destination of the target of the link to
12474 have been changed by combine. The only potential of this is if we
12475 replace I3, I2, and I1 by I3 and I2. But in that case the
12476 destination of I2 also remains unchanged. */
12478 if (NOTE_P (XEXP (link, 0))
12479 || (set = single_set (XEXP (link, 0))) == 0)
12482 reg = SET_DEST (set);
12483 while (GET_CODE (reg) == SUBREG || GET_CODE (reg) == ZERO_EXTRACT
12484 || GET_CODE (reg) == STRICT_LOW_PART)
12485 reg = XEXP (reg, 0);
12487 /* A LOG_LINK is defined as being placed on the first insn that uses
12488 a register and points to the insn that sets the register. Start
12489 searching at the next insn after the target of the link and stop
12490 when we reach a set of the register or the end of the basic block.
12492 Note that this correctly handles the link that used to point from
12493 I3 to I2. Also note that not much searching is typically done here
12494 since most links don't point very far away. */
12496 for (insn = NEXT_INSN (XEXP (link, 0));
12497 (insn && (this_basic_block->next_bb == EXIT_BLOCK_PTR
12498 || BB_HEAD (this_basic_block->next_bb) != insn));
12499 insn = NEXT_INSN (insn))
12500 if (INSN_P (insn) && reg_overlap_mentioned_p (reg, PATTERN (insn)))
12502 if (reg_referenced_p (reg, PATTERN (insn)))
12506 else if (CALL_P (insn)
12507 && find_reg_fusage (insn, USE, reg))
12512 else if (INSN_P (insn) && reg_set_p (reg, insn))
12515 /* If we found a place to put the link, place it there unless there
12516 is already a link to the same insn as LINK at that point. */
12522 for (link2 = LOG_LINKS (place); link2; link2 = XEXP (link2, 1))
12523 if (XEXP (link2, 0) == XEXP (link, 0))
12528 XEXP (link, 1) = LOG_LINKS (place);
12529 LOG_LINKS (place) = link;
12531 /* Set added_links_insn to the earliest insn we added a
12533 if (added_links_insn == 0
12534 || INSN_CUID (added_links_insn) > INSN_CUID (place))
12535 added_links_insn = place;
12541 /* Subroutine of unmentioned_reg_p and callback from for_each_rtx.
12542 Check whether the expression pointer to by LOC is a register or
12543 memory, and if so return 1 if it isn't mentioned in the rtx EXPR.
12544 Otherwise return zero. */
12547 unmentioned_reg_p_1 (rtx *loc, void *expr)
12552 && (REG_P (x) || MEM_P (x))
12553 && ! reg_mentioned_p (x, (rtx) expr))
12558 /* Check for any register or memory mentioned in EQUIV that is not
12559 mentioned in EXPR. This is used to restrict EQUIV to "specializations"
12560 of EXPR where some registers may have been replaced by constants. */
12563 unmentioned_reg_p (rtx equiv, rtx expr)
12565 return for_each_rtx (&equiv, unmentioned_reg_p_1, expr);
12568 /* Compute INSN_CUID for INSN, which is an insn made by combine. */
12571 insn_cuid (rtx insn)
12573 while (insn != 0 && INSN_UID (insn) > max_uid_cuid
12574 && NONJUMP_INSN_P (insn) && GET_CODE (PATTERN (insn)) == USE)
12575 insn = NEXT_INSN (insn);
12577 gcc_assert (INSN_UID (insn) <= max_uid_cuid);
12579 return INSN_CUID (insn);
12583 dump_combine_stats (FILE *file)
12587 ";; Combiner statistics: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n\n",
12588 combine_attempts, combine_merges, combine_extras, combine_successes);
12592 dump_combine_total_stats (FILE *file)
12596 "\n;; Combiner totals: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n",
12597 total_attempts, total_merges, total_extras, total_successes);
12602 gate_handle_combine (void)
12604 return (optimize > 0);
12607 /* Try combining insns through substitution. */
12609 rest_of_handle_combine (void)
12611 int rebuild_jump_labels_after_combine
12612 = combine_instructions (get_insns (), max_reg_num ());
12614 /* Combining insns may have turned an indirect jump into a
12615 direct jump. Rebuild the JUMP_LABEL fields of jumping
12617 if (rebuild_jump_labels_after_combine)
12619 timevar_push (TV_JUMP);
12620 rebuild_jump_labels (get_insns ());
12621 timevar_pop (TV_JUMP);
12623 delete_dead_jumptables ();
12624 cleanup_cfg (CLEANUP_EXPENSIVE | CLEANUP_UPDATE_LIFE);
12628 struct tree_opt_pass pass_combine =
12630 "combine", /* name */
12631 gate_handle_combine, /* gate */
12632 rest_of_handle_combine, /* execute */
12635 0, /* static_pass_number */
12636 TV_COMBINE, /* tv_id */
12637 0, /* properties_required */
12638 0, /* properties_provided */
12639 0, /* properties_destroyed */
12640 0, /* todo_flags_start */
12642 TODO_ggc_collect, /* todo_flags_finish */