1 /* Optimize by combining instructions for GNU compiler.
2 Copyright (C) 1987, 1988, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008
4 Free Software Foundation, Inc.
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify it under
9 the terms of the GNU General Public License as published by the Free
10 Software Foundation; either version 3, or (at your option) any later
13 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
14 WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
22 /* This module is essentially the "combiner" phase of the U. of Arizona
23 Portable Optimizer, but redone to work on our list-structured
24 representation for RTL instead of their string representation.
26 The LOG_LINKS of each insn identify the most recent assignment
27 to each REG used in the insn. It is a list of previous insns,
28 each of which contains a SET for a REG that is used in this insn
29 and not used or set in between. LOG_LINKs never cross basic blocks.
30 They were set up by the preceding pass (lifetime analysis).
32 We try to combine each pair of insns joined by a logical link.
33 We also try to combine triples of insns A, B and C when
34 C has a link back to B and B has a link back to A.
36 LOG_LINKS does not have links for use of the CC0. They don't
37 need to, because the insn that sets the CC0 is always immediately
38 before the insn that tests it. So we always regard a branch
39 insn as having a logical link to the preceding insn. The same is true
40 for an insn explicitly using CC0.
42 We check (with use_crosses_set_p) to avoid combining in such a way
43 as to move a computation to a place where its value would be different.
45 Combination is done by mathematically substituting the previous
46 insn(s) values for the regs they set into the expressions in
47 the later insns that refer to these regs. If the result is a valid insn
48 for our target machine, according to the machine description,
49 we install it, delete the earlier insns, and update the data flow
50 information (LOG_LINKS and REG_NOTES) for what we did.
52 There are a few exceptions where the dataflow information isn't
53 completely updated (however this is only a local issue since it is
54 regenerated before the next pass that uses it):
56 - reg_live_length is not updated
57 - reg_n_refs is not adjusted in the rare case when a register is
58 no longer required in a computation
59 - there are extremely rare cases (see distribute_notes) when a
61 - a LOG_LINKS entry that refers to an insn with multiple SETs may be
62 removed because there is no way to know which register it was
65 To simplify substitution, we combine only when the earlier insn(s)
66 consist of only a single assignment. To simplify updating afterward,
67 we never combine when a subroutine call appears in the middle.
69 Since we do not represent assignments to CC0 explicitly except when that
70 is all an insn does, there is no LOG_LINKS entry in an insn that uses
71 the condition code for the insn that set the condition code.
72 Fortunately, these two insns must be consecutive.
73 Therefore, every JUMP_INSN is taken to have an implicit logical link
74 to the preceding insn. This is not quite right, since non-jumps can
75 also use the condition code; but in practice such insns would not
80 #include "coretypes.h"
87 #include "hard-reg-set.h"
88 #include "basic-block.h"
89 #include "insn-config.h"
91 /* Include expr.h after insn-config.h so we get HAVE_conditional_move. */
93 #include "insn-attr.h"
99 #include "insn-codes.h"
100 #include "rtlhooks-def.h"
101 /* Include output.h for dump_file. */
105 #include "tree-pass.h"
109 /* Number of attempts to combine instructions in this function. */
111 static int combine_attempts;
113 /* Number of attempts that got as far as substitution in this function. */
115 static int combine_merges;
117 /* Number of instructions combined with added SETs in this function. */
119 static int combine_extras;
121 /* Number of instructions combined in this function. */
123 static int combine_successes;
125 /* Totals over entire compilation. */
127 static int total_attempts, total_merges, total_extras, total_successes;
129 /* combine_instructions may try to replace the right hand side of the
130 second instruction with the value of an associated REG_EQUAL note
131 before throwing it at try_combine. That is problematic when there
132 is a REG_DEAD note for a register used in the old right hand side
133 and can cause distribute_notes to do wrong things. This is the
134 second instruction if it has been so modified, null otherwise. */
138 /* When I2MOD is nonnull, this is a copy of the old right hand side. */
140 static rtx i2mod_old_rhs;
142 /* When I2MOD is nonnull, this is a copy of the new right hand side. */
144 static rtx i2mod_new_rhs;
146 typedef struct reg_stat_struct {
147 /* Record last point of death of (hard or pseudo) register n. */
150 /* Record last point of modification of (hard or pseudo) register n. */
153 /* The next group of fields allows the recording of the last value assigned
154 to (hard or pseudo) register n. We use this information to see if an
155 operation being processed is redundant given a prior operation performed
156 on the register. For example, an `and' with a constant is redundant if
157 all the zero bits are already known to be turned off.
159 We use an approach similar to that used by cse, but change it in the
162 (1) We do not want to reinitialize at each label.
163 (2) It is useful, but not critical, to know the actual value assigned
164 to a register. Often just its form is helpful.
166 Therefore, we maintain the following fields:
168 last_set_value the last value assigned
169 last_set_label records the value of label_tick when the
170 register was assigned
171 last_set_table_tick records the value of label_tick when a
172 value using the register is assigned
173 last_set_invalid set to nonzero when it is not valid
174 to use the value of this register in some
177 To understand the usage of these tables, it is important to understand
178 the distinction between the value in last_set_value being valid and
179 the register being validly contained in some other expression in the
182 (The next two parameters are out of date).
184 reg_stat[i].last_set_value is valid if it is nonzero, and either
185 reg_n_sets[i] is 1 or reg_stat[i].last_set_label == label_tick.
187 Register I may validly appear in any expression returned for the value
188 of another register if reg_n_sets[i] is 1. It may also appear in the
189 value for register J if reg_stat[j].last_set_invalid is zero, or
190 reg_stat[i].last_set_label < reg_stat[j].last_set_label.
192 If an expression is found in the table containing a register which may
193 not validly appear in an expression, the register is replaced by
194 something that won't match, (clobber (const_int 0)). */
196 /* Record last value assigned to (hard or pseudo) register n. */
200 /* Record the value of label_tick when an expression involving register n
201 is placed in last_set_value. */
203 int last_set_table_tick;
205 /* Record the value of label_tick when the value for register n is placed in
210 /* These fields are maintained in parallel with last_set_value and are
211 used to store the mode in which the register was last set, the bits
212 that were known to be zero when it was last set, and the number of
213 sign bits copies it was known to have when it was last set. */
215 unsigned HOST_WIDE_INT last_set_nonzero_bits;
216 char last_set_sign_bit_copies;
217 ENUM_BITFIELD(machine_mode) last_set_mode : 8;
219 /* Set nonzero if references to register n in expressions should not be
220 used. last_set_invalid is set nonzero when this register is being
221 assigned to and last_set_table_tick == label_tick. */
223 char last_set_invalid;
225 /* Some registers that are set more than once and used in more than one
226 basic block are nevertheless always set in similar ways. For example,
227 a QImode register may be loaded from memory in two places on a machine
228 where byte loads zero extend.
230 We record in the following fields if a register has some leading bits
231 that are always equal to the sign bit, and what we know about the
232 nonzero bits of a register, specifically which bits are known to be
235 If an entry is zero, it means that we don't know anything special. */
237 unsigned char sign_bit_copies;
239 unsigned HOST_WIDE_INT nonzero_bits;
241 /* Record the value of the label_tick when the last truncation
242 happened. The field truncated_to_mode is only valid if
243 truncation_label == label_tick. */
245 int truncation_label;
247 /* Record the last truncation seen for this register. If truncation
248 is not a nop to this mode we might be able to save an explicit
249 truncation if we know that value already contains a truncated
252 ENUM_BITFIELD(machine_mode) truncated_to_mode : 8;
255 DEF_VEC_O(reg_stat_type);
256 DEF_VEC_ALLOC_O(reg_stat_type,heap);
258 static VEC(reg_stat_type,heap) *reg_stat;
260 /* Record the luid of the last insn that invalidated memory
261 (anything that writes memory, and subroutine calls, but not pushes). */
263 static int mem_last_set;
265 /* Record the luid of the last CALL_INSN
266 so we can tell whether a potential combination crosses any calls. */
268 static int last_call_luid;
270 /* When `subst' is called, this is the insn that is being modified
271 (by combining in a previous insn). The PATTERN of this insn
272 is still the old pattern partially modified and it should not be
273 looked at, but this may be used to examine the successors of the insn
274 to judge whether a simplification is valid. */
276 static rtx subst_insn;
278 /* This is the lowest LUID that `subst' is currently dealing with.
279 get_last_value will not return a value if the register was set at or
280 after this LUID. If not for this mechanism, we could get confused if
281 I2 or I1 in try_combine were an insn that used the old value of a register
282 to obtain a new value. In that case, we might erroneously get the
283 new value of the register when we wanted the old one. */
285 static int subst_low_luid;
287 /* This contains any hard registers that are used in newpat; reg_dead_at_p
288 must consider all these registers to be always live. */
290 static HARD_REG_SET newpat_used_regs;
292 /* This is an insn to which a LOG_LINKS entry has been added. If this
293 insn is the earlier than I2 or I3, combine should rescan starting at
296 static rtx added_links_insn;
298 /* Basic block in which we are performing combines. */
299 static basic_block this_basic_block;
302 /* Length of the currently allocated uid_insn_cost array. */
304 static int max_uid_known;
306 /* The following array records the insn_rtx_cost for every insn
307 in the instruction stream. */
309 static int *uid_insn_cost;
311 /* The following array records the LOG_LINKS for every insn in the
312 instruction stream as an INSN_LIST rtx. */
314 static rtx *uid_log_links;
316 #define INSN_COST(INSN) (uid_insn_cost[INSN_UID (INSN)])
317 #define LOG_LINKS(INSN) (uid_log_links[INSN_UID (INSN)])
319 /* Incremented for each basic block. */
321 static int label_tick;
323 /* Reset to label_tick for each label. */
325 static int label_tick_ebb_start;
327 /* Mode used to compute significance in reg_stat[].nonzero_bits. It is the
328 largest integer mode that can fit in HOST_BITS_PER_WIDE_INT. */
330 static enum machine_mode nonzero_bits_mode;
332 /* Nonzero when reg_stat[].nonzero_bits and reg_stat[].sign_bit_copies can
333 be safely used. It is zero while computing them and after combine has
334 completed. This former test prevents propagating values based on
335 previously set values, which can be incorrect if a variable is modified
338 static int nonzero_sign_valid;
341 /* Record one modification to rtl structure
342 to be undone by storing old_contents into *where. */
347 enum { UNDO_RTX, UNDO_INT, UNDO_MODE } kind;
348 union { rtx r; int i; enum machine_mode m; } old_contents;
349 union { rtx *r; int *i; } where;
352 /* Record a bunch of changes to be undone, up to MAX_UNDO of them.
353 num_undo says how many are currently recorded.
355 other_insn is nonzero if we have modified some other insn in the process
356 of working on subst_insn. It must be verified too. */
365 static struct undobuf undobuf;
367 /* Number of times the pseudo being substituted for
368 was found and replaced. */
370 static int n_occurrences;
372 static rtx reg_nonzero_bits_for_combine (const_rtx, enum machine_mode, const_rtx,
374 unsigned HOST_WIDE_INT,
375 unsigned HOST_WIDE_INT *);
376 static rtx reg_num_sign_bit_copies_for_combine (const_rtx, enum machine_mode, const_rtx,
378 unsigned int, unsigned int *);
379 static void do_SUBST (rtx *, rtx);
380 static void do_SUBST_INT (int *, int);
381 static void init_reg_last (void);
382 static void setup_incoming_promotions (rtx);
383 static void set_nonzero_bits_and_sign_copies (rtx, const_rtx, void *);
384 static int cant_combine_insn_p (rtx);
385 static int can_combine_p (rtx, rtx, rtx, rtx, rtx *, rtx *);
386 static int combinable_i3pat (rtx, rtx *, rtx, rtx, int, rtx *);
387 static int contains_muldiv (rtx);
388 static rtx try_combine (rtx, rtx, rtx, int *);
389 static void undo_all (void);
390 static void undo_commit (void);
391 static rtx *find_split_point (rtx *, rtx);
392 static rtx subst (rtx, rtx, rtx, int, int);
393 static rtx combine_simplify_rtx (rtx, enum machine_mode, int);
394 static rtx simplify_if_then_else (rtx);
395 static rtx simplify_set (rtx);
396 static rtx simplify_logical (rtx);
397 static rtx expand_compound_operation (rtx);
398 static const_rtx expand_field_assignment (const_rtx);
399 static rtx make_extraction (enum machine_mode, rtx, HOST_WIDE_INT,
400 rtx, unsigned HOST_WIDE_INT, int, int, int);
401 static rtx extract_left_shift (rtx, int);
402 static rtx make_compound_operation (rtx, enum rtx_code);
403 static int get_pos_from_mask (unsigned HOST_WIDE_INT,
404 unsigned HOST_WIDE_INT *);
405 static rtx canon_reg_for_combine (rtx, rtx);
406 static rtx force_to_mode (rtx, enum machine_mode,
407 unsigned HOST_WIDE_INT, int);
408 static rtx if_then_else_cond (rtx, rtx *, rtx *);
409 static rtx known_cond (rtx, enum rtx_code, rtx, rtx);
410 static int rtx_equal_for_field_assignment_p (rtx, rtx);
411 static rtx make_field_assignment (rtx);
412 static rtx apply_distributive_law (rtx);
413 static rtx distribute_and_simplify_rtx (rtx, int);
414 static rtx simplify_and_const_int_1 (enum machine_mode, rtx,
415 unsigned HOST_WIDE_INT);
416 static rtx simplify_and_const_int (rtx, enum machine_mode, rtx,
417 unsigned HOST_WIDE_INT);
418 static int merge_outer_ops (enum rtx_code *, HOST_WIDE_INT *, enum rtx_code,
419 HOST_WIDE_INT, enum machine_mode, int *);
420 static rtx simplify_shift_const_1 (enum rtx_code, enum machine_mode, rtx, int);
421 static rtx simplify_shift_const (rtx, enum rtx_code, enum machine_mode, rtx,
423 static int recog_for_combine (rtx *, rtx, rtx *);
424 static rtx gen_lowpart_for_combine (enum machine_mode, rtx);
425 static enum rtx_code simplify_comparison (enum rtx_code, rtx *, rtx *);
426 static void update_table_tick (rtx);
427 static void record_value_for_reg (rtx, rtx, rtx);
428 static void check_promoted_subreg (rtx, rtx);
429 static void record_dead_and_set_regs_1 (rtx, const_rtx, void *);
430 static void record_dead_and_set_regs (rtx);
431 static int get_last_value_validate (rtx *, rtx, int, int);
432 static rtx get_last_value (const_rtx);
433 static int use_crosses_set_p (const_rtx, int);
434 static void reg_dead_at_p_1 (rtx, const_rtx, void *);
435 static int reg_dead_at_p (rtx, rtx);
436 static void move_deaths (rtx, rtx, int, rtx, rtx *);
437 static int reg_bitfield_target_p (rtx, rtx);
438 static void distribute_notes (rtx, rtx, rtx, rtx, rtx, rtx);
439 static void distribute_links (rtx);
440 static void mark_used_regs_combine (rtx);
441 static void record_promoted_value (rtx, rtx);
442 static int unmentioned_reg_p_1 (rtx *, void *);
443 static bool unmentioned_reg_p (rtx, rtx);
444 static int record_truncated_value (rtx *, void *);
445 static void record_truncated_values (rtx *, void *);
446 static bool reg_truncated_to_mode (enum machine_mode, const_rtx);
447 static rtx gen_lowpart_or_truncate (enum machine_mode, rtx);
450 /* It is not safe to use ordinary gen_lowpart in combine.
451 See comments in gen_lowpart_for_combine. */
452 #undef RTL_HOOKS_GEN_LOWPART
453 #define RTL_HOOKS_GEN_LOWPART gen_lowpart_for_combine
455 /* Our implementation of gen_lowpart never emits a new pseudo. */
456 #undef RTL_HOOKS_GEN_LOWPART_NO_EMIT
457 #define RTL_HOOKS_GEN_LOWPART_NO_EMIT gen_lowpart_for_combine
459 #undef RTL_HOOKS_REG_NONZERO_REG_BITS
460 #define RTL_HOOKS_REG_NONZERO_REG_BITS reg_nonzero_bits_for_combine
462 #undef RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES
463 #define RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES reg_num_sign_bit_copies_for_combine
465 #undef RTL_HOOKS_REG_TRUNCATED_TO_MODE
466 #define RTL_HOOKS_REG_TRUNCATED_TO_MODE reg_truncated_to_mode
468 static const struct rtl_hooks combine_rtl_hooks = RTL_HOOKS_INITIALIZER;
471 /* Try to split PATTERN found in INSN. This returns NULL_RTX if
472 PATTERN can not be split. Otherwise, it returns an insn sequence.
473 This is a wrapper around split_insns which ensures that the
474 reg_stat vector is made larger if the splitter creates a new
478 combine_split_insns (rtx pattern, rtx insn)
483 ret = split_insns (pattern, insn);
484 nregs = max_reg_num ();
485 if (nregs > VEC_length (reg_stat_type, reg_stat))
486 VEC_safe_grow_cleared (reg_stat_type, heap, reg_stat, nregs);
490 /* This is used by find_single_use to locate an rtx in LOC that
491 contains exactly one use of DEST, which is typically either a REG
492 or CC0. It returns a pointer to the innermost rtx expression
493 containing DEST. Appearances of DEST that are being used to
494 totally replace it are not counted. */
497 find_single_use_1 (rtx dest, rtx *loc)
500 enum rtx_code code = GET_CODE (x);
518 /* If the destination is anything other than CC0, PC, a REG or a SUBREG
519 of a REG that occupies all of the REG, the insn uses DEST if
520 it is mentioned in the destination or the source. Otherwise, we
521 need just check the source. */
522 if (GET_CODE (SET_DEST (x)) != CC0
523 && GET_CODE (SET_DEST (x)) != PC
524 && !REG_P (SET_DEST (x))
525 && ! (GET_CODE (SET_DEST (x)) == SUBREG
526 && REG_P (SUBREG_REG (SET_DEST (x)))
527 && (((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x))))
528 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
529 == ((GET_MODE_SIZE (GET_MODE (SET_DEST (x)))
530 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD))))
533 return find_single_use_1 (dest, &SET_SRC (x));
537 return find_single_use_1 (dest, &XEXP (x, 0));
543 /* If it wasn't one of the common cases above, check each expression and
544 vector of this code. Look for a unique usage of DEST. */
546 fmt = GET_RTX_FORMAT (code);
547 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
551 if (dest == XEXP (x, i)
552 || (REG_P (dest) && REG_P (XEXP (x, i))
553 && REGNO (dest) == REGNO (XEXP (x, i))))
556 this_result = find_single_use_1 (dest, &XEXP (x, i));
559 result = this_result;
560 else if (this_result)
561 /* Duplicate usage. */
564 else if (fmt[i] == 'E')
568 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
570 if (XVECEXP (x, i, j) == dest
572 && REG_P (XVECEXP (x, i, j))
573 && REGNO (XVECEXP (x, i, j)) == REGNO (dest)))
576 this_result = find_single_use_1 (dest, &XVECEXP (x, i, j));
579 result = this_result;
580 else if (this_result)
590 /* See if DEST, produced in INSN, is used only a single time in the
591 sequel. If so, return a pointer to the innermost rtx expression in which
594 If PLOC is nonzero, *PLOC is set to the insn containing the single use.
596 If DEST is cc0_rtx, we look only at the next insn. In that case, we don't
597 care about REG_DEAD notes or LOG_LINKS.
599 Otherwise, we find the single use by finding an insn that has a
600 LOG_LINKS pointing at INSN and has a REG_DEAD note for DEST. If DEST is
601 only referenced once in that insn, we know that it must be the first
602 and last insn referencing DEST. */
605 find_single_use (rtx dest, rtx insn, rtx *ploc)
614 next = NEXT_INSN (insn);
616 || (!NONJUMP_INSN_P (next) && !JUMP_P (next)))
619 result = find_single_use_1 (dest, &PATTERN (next));
629 for (next = next_nonnote_insn (insn);
630 next != 0 && !LABEL_P (next);
631 next = next_nonnote_insn (next))
632 if (INSN_P (next) && dead_or_set_p (next, dest))
634 for (link = LOG_LINKS (next); link; link = XEXP (link, 1))
635 if (XEXP (link, 0) == insn)
640 result = find_single_use_1 (dest, &PATTERN (next));
650 /* Substitute NEWVAL, an rtx expression, into INTO, a place in some
651 insn. The substitution can be undone by undo_all. If INTO is already
652 set to NEWVAL, do not record this change. Because computing NEWVAL might
653 also call SUBST, we have to compute it before we put anything into
657 do_SUBST (rtx *into, rtx newval)
662 if (oldval == newval)
665 /* We'd like to catch as many invalid transformations here as
666 possible. Unfortunately, there are way too many mode changes
667 that are perfectly valid, so we'd waste too much effort for
668 little gain doing the checks here. Focus on catching invalid
669 transformations involving integer constants. */
670 if (GET_MODE_CLASS (GET_MODE (oldval)) == MODE_INT
671 && GET_CODE (newval) == CONST_INT)
673 /* Sanity check that we're replacing oldval with a CONST_INT
674 that is a valid sign-extension for the original mode. */
675 gcc_assert (INTVAL (newval)
676 == trunc_int_for_mode (INTVAL (newval), GET_MODE (oldval)));
678 /* Replacing the operand of a SUBREG or a ZERO_EXTEND with a
679 CONST_INT is not valid, because after the replacement, the
680 original mode would be gone. Unfortunately, we can't tell
681 when do_SUBST is called to replace the operand thereof, so we
682 perform this test on oldval instead, checking whether an
683 invalid replacement took place before we got here. */
684 gcc_assert (!(GET_CODE (oldval) == SUBREG
685 && GET_CODE (SUBREG_REG (oldval)) == CONST_INT));
686 gcc_assert (!(GET_CODE (oldval) == ZERO_EXTEND
687 && GET_CODE (XEXP (oldval, 0)) == CONST_INT));
691 buf = undobuf.frees, undobuf.frees = buf->next;
693 buf = XNEW (struct undo);
695 buf->kind = UNDO_RTX;
697 buf->old_contents.r = oldval;
700 buf->next = undobuf.undos, undobuf.undos = buf;
703 #define SUBST(INTO, NEWVAL) do_SUBST(&(INTO), (NEWVAL))
705 /* Similar to SUBST, but NEWVAL is an int expression. Note that substitution
706 for the value of a HOST_WIDE_INT value (including CONST_INT) is
710 do_SUBST_INT (int *into, int newval)
715 if (oldval == newval)
719 buf = undobuf.frees, undobuf.frees = buf->next;
721 buf = XNEW (struct undo);
723 buf->kind = UNDO_INT;
725 buf->old_contents.i = oldval;
728 buf->next = undobuf.undos, undobuf.undos = buf;
731 #define SUBST_INT(INTO, NEWVAL) do_SUBST_INT(&(INTO), (NEWVAL))
733 /* Similar to SUBST, but just substitute the mode. This is used when
734 changing the mode of a pseudo-register, so that any other
735 references to the entry in the regno_reg_rtx array will change as
739 do_SUBST_MODE (rtx *into, enum machine_mode newval)
742 enum machine_mode oldval = GET_MODE (*into);
744 if (oldval == newval)
748 buf = undobuf.frees, undobuf.frees = buf->next;
750 buf = XNEW (struct undo);
752 buf->kind = UNDO_MODE;
754 buf->old_contents.m = oldval;
755 adjust_reg_mode (*into, newval);
757 buf->next = undobuf.undos, undobuf.undos = buf;
760 #define SUBST_MODE(INTO, NEWVAL) do_SUBST_MODE(&(INTO), (NEWVAL))
762 /* Subroutine of try_combine. Determine whether the combine replacement
763 patterns NEWPAT, NEWI2PAT and NEWOTHERPAT are cheaper according to
764 insn_rtx_cost that the original instruction sequence I1, I2, I3 and
765 undobuf.other_insn. Note that I1 and/or NEWI2PAT may be NULL_RTX.
766 NEWOTHERPAT and undobuf.other_insn may also both be NULL_RTX. This
767 function returns false, if the costs of all instructions can be
768 estimated, and the replacements are more expensive than the original
772 combine_validate_cost (rtx i1, rtx i2, rtx i3, rtx newpat, rtx newi2pat,
775 int i1_cost, i2_cost, i3_cost;
776 int new_i2_cost, new_i3_cost;
777 int old_cost, new_cost;
779 /* Lookup the original insn_rtx_costs. */
780 i2_cost = INSN_COST (i2);
781 i3_cost = INSN_COST (i3);
785 i1_cost = INSN_COST (i1);
786 old_cost = (i1_cost > 0 && i2_cost > 0 && i3_cost > 0)
787 ? i1_cost + i2_cost + i3_cost : 0;
791 old_cost = (i2_cost > 0 && i3_cost > 0) ? i2_cost + i3_cost : 0;
795 /* Calculate the replacement insn_rtx_costs. */
796 new_i3_cost = insn_rtx_cost (newpat);
799 new_i2_cost = insn_rtx_cost (newi2pat);
800 new_cost = (new_i2_cost > 0 && new_i3_cost > 0)
801 ? new_i2_cost + new_i3_cost : 0;
805 new_cost = new_i3_cost;
809 if (undobuf.other_insn)
811 int old_other_cost, new_other_cost;
813 old_other_cost = INSN_COST (undobuf.other_insn);
814 new_other_cost = insn_rtx_cost (newotherpat);
815 if (old_other_cost > 0 && new_other_cost > 0)
817 old_cost += old_other_cost;
818 new_cost += new_other_cost;
824 /* Disallow this recombination if both new_cost and old_cost are
825 greater than zero, and new_cost is greater than old cost. */
827 && new_cost > old_cost)
834 "rejecting combination of insns %d, %d and %d\n",
835 INSN_UID (i1), INSN_UID (i2), INSN_UID (i3));
836 fprintf (dump_file, "original costs %d + %d + %d = %d\n",
837 i1_cost, i2_cost, i3_cost, old_cost);
842 "rejecting combination of insns %d and %d\n",
843 INSN_UID (i2), INSN_UID (i3));
844 fprintf (dump_file, "original costs %d + %d = %d\n",
845 i2_cost, i3_cost, old_cost);
850 fprintf (dump_file, "replacement costs %d + %d = %d\n",
851 new_i2_cost, new_i3_cost, new_cost);
854 fprintf (dump_file, "replacement cost %d\n", new_cost);
860 /* Update the uid_insn_cost array with the replacement costs. */
861 INSN_COST (i2) = new_i2_cost;
862 INSN_COST (i3) = new_i3_cost;
870 /* Delete any insns that copy a register to itself. */
873 delete_noop_moves (void)
880 for (insn = BB_HEAD (bb); insn != NEXT_INSN (BB_END (bb)); insn = next)
882 next = NEXT_INSN (insn);
883 if (INSN_P (insn) && noop_move_p (insn))
887 /* If we're about to remove the first insn of a libcall
888 then move the libcall note to the next real insn and
889 update the retval note. */
890 if ((note = find_reg_note (insn, REG_LIBCALL, NULL_RTX))
891 && XEXP (note, 0) != insn)
893 rtx new_libcall_insn = next_real_insn (insn);
894 rtx retval_note = find_reg_note (XEXP (note, 0),
895 REG_RETVAL, NULL_RTX);
896 REG_NOTES (new_libcall_insn)
897 = gen_rtx_INSN_LIST (REG_LIBCALL, XEXP (note, 0),
898 REG_NOTES (new_libcall_insn));
899 XEXP (retval_note, 0) = new_libcall_insn;
903 fprintf (dump_file, "deleting noop move %d\n", INSN_UID (insn));
905 delete_insn_and_edges (insn);
912 /* Fill in log links field for all insns. */
915 create_log_links (void)
919 struct df_ref **def_vec, **use_vec;
921 next_use = XCNEWVEC (rtx, max_reg_num ());
923 /* Pass through each block from the end, recording the uses of each
924 register and establishing log links when def is encountered.
925 Note that we do not clear next_use array in order to save time,
926 so we have to test whether the use is in the same basic block as def.
928 There are a few cases below when we do not consider the definition or
929 usage -- these are taken from original flow.c did. Don't ask me why it is
930 done this way; I don't know and if it works, I don't want to know. */
934 FOR_BB_INSNS_REVERSE (bb, insn)
939 /* Log links are created only once. */
940 gcc_assert (!LOG_LINKS (insn));
942 for (def_vec = DF_INSN_DEFS (insn); *def_vec; def_vec++)
944 struct df_ref *def = *def_vec;
945 int regno = DF_REF_REGNO (def);
948 if (!next_use[regno])
951 /* Do not consider if it is pre/post modification in MEM. */
952 if (DF_REF_FLAGS (def) & DF_REF_PRE_POST_MODIFY)
955 /* Do not make the log link for frame pointer. */
956 if ((regno == FRAME_POINTER_REGNUM
957 && (! reload_completed || frame_pointer_needed))
958 #if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM
959 || (regno == HARD_FRAME_POINTER_REGNUM
960 && (! reload_completed || frame_pointer_needed))
962 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
963 || (regno == ARG_POINTER_REGNUM && fixed_regs[regno])
968 use_insn = next_use[regno];
969 if (BLOCK_FOR_INSN (use_insn) == bb)
973 We don't build a LOG_LINK for hard registers contained
974 in ASM_OPERANDs. If these registers get replaced,
975 we might wind up changing the semantics of the insn,
976 even if reload can make what appear to be valid
977 assignments later. */
978 if (regno >= FIRST_PSEUDO_REGISTER
979 || asm_noperands (PATTERN (use_insn)) < 0)
981 /* Don't add duplicate links between instructions. */
983 for (links = LOG_LINKS (use_insn); links;
984 links = XEXP (links, 1))
985 if (insn == XEXP (links, 0))
989 LOG_LINKS (use_insn) =
990 alloc_INSN_LIST (insn, LOG_LINKS (use_insn));
993 next_use[regno] = NULL_RTX;
996 for (use_vec = DF_INSN_USES (insn); *use_vec; use_vec++)
998 struct df_ref *use = *use_vec;
999 int regno = DF_REF_REGNO (use);
1001 /* Do not consider the usage of the stack pointer
1002 by function call. */
1003 if (DF_REF_FLAGS (use) & DF_REF_CALL_STACK_USAGE)
1006 next_use[regno] = insn;
1014 /* Clear LOG_LINKS fields of insns. */
1017 clear_log_links (void)
1021 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
1023 free_INSN_LIST_list (&LOG_LINKS (insn));
1029 /* Main entry point for combiner. F is the first insn of the function.
1030 NREGS is the first unused pseudo-reg number.
1032 Return nonzero if the combiner has turned an indirect jump
1033 instruction into a direct jump. */
1035 combine_instructions (rtx f, unsigned int nregs)
1041 rtx links, nextlinks;
1044 int new_direct_jump_p = 0;
1046 for (first = f; first && !INSN_P (first); )
1047 first = NEXT_INSN (first);
1051 combine_attempts = 0;
1054 combine_successes = 0;
1056 rtl_hooks = combine_rtl_hooks;
1058 VEC_safe_grow_cleared (reg_stat_type, heap, reg_stat, nregs);
1060 init_recog_no_volatile ();
1062 /* Allocate array for insn info. */
1063 max_uid_known = get_max_uid ();
1064 uid_log_links = XCNEWVEC (rtx, max_uid_known + 1);
1065 uid_insn_cost = XCNEWVEC (int, max_uid_known + 1);
1067 nonzero_bits_mode = mode_for_size (HOST_BITS_PER_WIDE_INT, MODE_INT, 0);
1069 /* Don't use reg_stat[].nonzero_bits when computing it. This can cause
1070 problems when, for example, we have j <<= 1 in a loop. */
1072 nonzero_sign_valid = 0;
1074 /* Scan all SETs and see if we can deduce anything about what
1075 bits are known to be zero for some registers and how many copies
1076 of the sign bit are known to exist for those registers.
1078 Also set any known values so that we can use it while searching
1079 for what bits are known to be set. */
1081 label_tick = label_tick_ebb_start = 1;
1083 setup_incoming_promotions (first);
1085 create_log_links ();
1086 FOR_EACH_BB (this_basic_block)
1091 FOR_BB_INSNS (this_basic_block, insn)
1092 if (INSN_P (insn) && BLOCK_FOR_INSN (insn))
1094 subst_low_luid = DF_INSN_LUID (insn);
1097 note_stores (PATTERN (insn), set_nonzero_bits_and_sign_copies,
1099 record_dead_and_set_regs (insn);
1102 for (links = REG_NOTES (insn); links; links = XEXP (links, 1))
1103 if (REG_NOTE_KIND (links) == REG_INC)
1104 set_nonzero_bits_and_sign_copies (XEXP (links, 0), NULL_RTX,
1108 /* Record the current insn_rtx_cost of this instruction. */
1109 if (NONJUMP_INSN_P (insn))
1110 INSN_COST (insn) = insn_rtx_cost (PATTERN (insn));
1112 fprintf(dump_file, "insn_cost %d: %d\n",
1113 INSN_UID (insn), INSN_COST (insn));
1115 else if (LABEL_P (insn))
1116 label_tick_ebb_start = label_tick;
1119 nonzero_sign_valid = 1;
1121 /* Now scan all the insns in forward order. */
1123 label_tick = label_tick_ebb_start = 1;
1125 setup_incoming_promotions (first);
1127 FOR_EACH_BB (this_basic_block)
1132 for (insn = BB_HEAD (this_basic_block);
1133 insn != NEXT_INSN (BB_END (this_basic_block));
1134 insn = next ? next : NEXT_INSN (insn))
1139 /* See if we know about function return values before this
1140 insn based upon SUBREG flags. */
1141 check_promoted_subreg (insn, PATTERN (insn));
1143 /* See if we can find hardregs and subreg of pseudos in
1144 narrower modes. This could help turning TRUNCATEs
1146 note_uses (&PATTERN (insn), record_truncated_values, NULL);
1148 /* Try this insn with each insn it links back to. */
1150 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
1151 if ((next = try_combine (insn, XEXP (links, 0),
1152 NULL_RTX, &new_direct_jump_p)) != 0)
1155 /* Try each sequence of three linked insns ending with this one. */
1157 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
1159 rtx link = XEXP (links, 0);
1161 /* If the linked insn has been replaced by a note, then there
1162 is no point in pursuing this chain any further. */
1166 for (nextlinks = LOG_LINKS (link);
1168 nextlinks = XEXP (nextlinks, 1))
1169 if ((next = try_combine (insn, link,
1170 XEXP (nextlinks, 0),
1171 &new_direct_jump_p)) != 0)
1176 /* Try to combine a jump insn that uses CC0
1177 with a preceding insn that sets CC0, and maybe with its
1178 logical predecessor as well.
1179 This is how we make decrement-and-branch insns.
1180 We need this special code because data flow connections
1181 via CC0 do not get entered in LOG_LINKS. */
1184 && (prev = prev_nonnote_insn (insn)) != 0
1185 && NONJUMP_INSN_P (prev)
1186 && sets_cc0_p (PATTERN (prev)))
1188 if ((next = try_combine (insn, prev,
1189 NULL_RTX, &new_direct_jump_p)) != 0)
1192 for (nextlinks = LOG_LINKS (prev); nextlinks;
1193 nextlinks = XEXP (nextlinks, 1))
1194 if ((next = try_combine (insn, prev,
1195 XEXP (nextlinks, 0),
1196 &new_direct_jump_p)) != 0)
1200 /* Do the same for an insn that explicitly references CC0. */
1201 if (NONJUMP_INSN_P (insn)
1202 && (prev = prev_nonnote_insn (insn)) != 0
1203 && NONJUMP_INSN_P (prev)
1204 && sets_cc0_p (PATTERN (prev))
1205 && GET_CODE (PATTERN (insn)) == SET
1206 && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (insn))))
1208 if ((next = try_combine (insn, prev,
1209 NULL_RTX, &new_direct_jump_p)) != 0)
1212 for (nextlinks = LOG_LINKS (prev); nextlinks;
1213 nextlinks = XEXP (nextlinks, 1))
1214 if ((next = try_combine (insn, prev,
1215 XEXP (nextlinks, 0),
1216 &new_direct_jump_p)) != 0)
1220 /* Finally, see if any of the insns that this insn links to
1221 explicitly references CC0. If so, try this insn, that insn,
1222 and its predecessor if it sets CC0. */
1223 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
1224 if (NONJUMP_INSN_P (XEXP (links, 0))
1225 && GET_CODE (PATTERN (XEXP (links, 0))) == SET
1226 && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (XEXP (links, 0))))
1227 && (prev = prev_nonnote_insn (XEXP (links, 0))) != 0
1228 && NONJUMP_INSN_P (prev)
1229 && sets_cc0_p (PATTERN (prev))
1230 && (next = try_combine (insn, XEXP (links, 0),
1231 prev, &new_direct_jump_p)) != 0)
1235 /* Try combining an insn with two different insns whose results it
1237 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
1238 for (nextlinks = XEXP (links, 1); nextlinks;
1239 nextlinks = XEXP (nextlinks, 1))
1240 if ((next = try_combine (insn, XEXP (links, 0),
1241 XEXP (nextlinks, 0),
1242 &new_direct_jump_p)) != 0)
1245 /* Try this insn with each REG_EQUAL note it links back to. */
1246 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
1249 rtx temp = XEXP (links, 0);
1250 if ((set = single_set (temp)) != 0
1251 && (note = find_reg_equal_equiv_note (temp)) != 0
1252 && (note = XEXP (note, 0), GET_CODE (note)) != EXPR_LIST
1253 /* Avoid using a register that may already been marked
1254 dead by an earlier instruction. */
1255 && ! unmentioned_reg_p (note, SET_SRC (set))
1256 && (GET_MODE (note) == VOIDmode
1257 ? SCALAR_INT_MODE_P (GET_MODE (SET_DEST (set)))
1258 : GET_MODE (SET_DEST (set)) == GET_MODE (note)))
1260 /* Temporarily replace the set's source with the
1261 contents of the REG_EQUAL note. The insn will
1262 be deleted or recognized by try_combine. */
1263 rtx orig = SET_SRC (set);
1264 SET_SRC (set) = note;
1266 i2mod_old_rhs = copy_rtx (orig);
1267 i2mod_new_rhs = copy_rtx (note);
1268 next = try_combine (insn, i2mod, NULL_RTX,
1269 &new_direct_jump_p);
1273 SET_SRC (set) = orig;
1278 record_dead_and_set_regs (insn);
1283 else if (LABEL_P (insn))
1284 label_tick_ebb_start = label_tick;
1290 new_direct_jump_p |= purge_all_dead_edges ();
1291 delete_noop_moves ();
1294 free (uid_log_links);
1295 free (uid_insn_cost);
1296 VEC_free (reg_stat_type, heap, reg_stat);
1299 struct undo *undo, *next;
1300 for (undo = undobuf.frees; undo; undo = next)
1308 total_attempts += combine_attempts;
1309 total_merges += combine_merges;
1310 total_extras += combine_extras;
1311 total_successes += combine_successes;
1313 nonzero_sign_valid = 0;
1314 rtl_hooks = general_rtl_hooks;
1316 /* Make recognizer allow volatile MEMs again. */
1319 return new_direct_jump_p;
1322 /* Wipe the last_xxx fields of reg_stat in preparation for another pass. */
1325 init_reg_last (void)
1330 for (i = 0; VEC_iterate (reg_stat_type, reg_stat, i, p); ++i)
1331 memset (p, 0, offsetof (reg_stat_type, sign_bit_copies));
1334 /* Set up any promoted values for incoming argument registers. */
1337 setup_incoming_promotions (rtx first)
1340 bool strictly_local = false;
1342 if (!targetm.calls.promote_function_args (TREE_TYPE (cfun->decl)))
1345 for (arg = DECL_ARGUMENTS (current_function_decl); arg;
1346 arg = TREE_CHAIN (arg))
1348 rtx reg = DECL_INCOMING_RTL (arg);
1350 enum machine_mode mode1, mode2, mode3, mode4;
1352 /* Only continue if the incoming argument is in a register. */
1356 /* Determine, if possible, whether all call sites of the current
1357 function lie within the current compilation unit. (This does
1358 take into account the exporting of a function via taking its
1359 address, and so forth.) */
1360 if (flag_unit_at_a_time)
1361 strictly_local = cgraph_local_info (current_function_decl)->local;
1363 /* The mode and signedness of the argument before any promotions happen
1364 (equal to the mode of the pseudo holding it at that stage). */
1365 mode1 = TYPE_MODE (TREE_TYPE (arg));
1366 uns1 = TYPE_UNSIGNED (TREE_TYPE (arg));
1368 /* The mode and signedness of the argument after any source language and
1369 TARGET_PROMOTE_PROTOTYPES-driven promotions. */
1370 mode2 = TYPE_MODE (DECL_ARG_TYPE (arg));
1371 uns3 = TYPE_UNSIGNED (DECL_ARG_TYPE (arg));
1373 /* The mode and signedness of the argument as it is actually passed,
1374 after any TARGET_PROMOTE_FUNCTION_ARGS-driven ABI promotions. */
1375 mode3 = promote_mode (DECL_ARG_TYPE (arg), mode2, &uns3, 1);
1377 /* The mode of the register in which the argument is being passed. */
1378 mode4 = GET_MODE (reg);
1380 /* Eliminate sign extensions in the callee when possible. Only
1382 (a) a mode promotion has occurred;
1383 (b) the mode of the register is the same as the mode of
1384 the argument as it is passed; and
1385 (c) the signedness does not change across any of the promotions; and
1386 (d) when no language-level promotions (which we cannot guarantee
1387 will have been done by an external caller) are necessary,
1388 unless we know that this function is only ever called from
1389 the current compilation unit -- all of whose call sites will
1390 do the mode1 --> mode2 promotion. */
1394 && (mode1 == mode2 || strictly_local))
1396 /* Record that the value was promoted from mode1 to mode3,
1397 so that any sign extension at the head of the current
1398 function may be eliminated. */
1400 x = gen_rtx_CLOBBER (mode1, const0_rtx);
1401 x = gen_rtx_fmt_e ((uns3 ? ZERO_EXTEND : SIGN_EXTEND), mode3, x);
1402 record_value_for_reg (reg, first, x);
1407 /* Called via note_stores. If X is a pseudo that is narrower than
1408 HOST_BITS_PER_WIDE_INT and is being set, record what bits are known zero.
1410 If we are setting only a portion of X and we can't figure out what
1411 portion, assume all bits will be used since we don't know what will
1414 Similarly, set how many bits of X are known to be copies of the sign bit
1415 at all locations in the function. This is the smallest number implied
1419 set_nonzero_bits_and_sign_copies (rtx x, const_rtx set, void *data)
1421 rtx insn = (rtx) data;
1425 && REGNO (x) >= FIRST_PSEUDO_REGISTER
1426 /* If this register is undefined at the start of the file, we can't
1427 say what its contents were. */
1428 && ! REGNO_REG_SET_P
1429 (DF_LR_IN (ENTRY_BLOCK_PTR->next_bb), REGNO (x))
1430 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT)
1432 reg_stat_type *rsp = VEC_index (reg_stat_type, reg_stat, REGNO (x));
1434 if (set == 0 || GET_CODE (set) == CLOBBER)
1436 rsp->nonzero_bits = GET_MODE_MASK (GET_MODE (x));
1437 rsp->sign_bit_copies = 1;
1441 /* If this register is being initialized using itself, and the
1442 register is uninitialized in this basic block, and there are
1443 no LOG_LINKS which set the register, then part of the
1444 register is uninitialized. In that case we can't assume
1445 anything about the number of nonzero bits.
1447 ??? We could do better if we checked this in
1448 reg_{nonzero_bits,num_sign_bit_copies}_for_combine. Then we
1449 could avoid making assumptions about the insn which initially
1450 sets the register, while still using the information in other
1451 insns. We would have to be careful to check every insn
1452 involved in the combination. */
1455 && reg_referenced_p (x, PATTERN (insn))
1456 && !REGNO_REG_SET_P (DF_LR_IN (BLOCK_FOR_INSN (insn)),
1461 for (link = LOG_LINKS (insn); link; link = XEXP (link, 1))
1463 if (dead_or_set_p (XEXP (link, 0), x))
1468 rsp->nonzero_bits = GET_MODE_MASK (GET_MODE (x));
1469 rsp->sign_bit_copies = 1;
1474 /* If this is a complex assignment, see if we can convert it into a
1475 simple assignment. */
1476 set = expand_field_assignment (set);
1478 /* If this is a simple assignment, or we have a paradoxical SUBREG,
1479 set what we know about X. */
1481 if (SET_DEST (set) == x
1482 || (GET_CODE (SET_DEST (set)) == SUBREG
1483 && (GET_MODE_SIZE (GET_MODE (SET_DEST (set)))
1484 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (set)))))
1485 && SUBREG_REG (SET_DEST (set)) == x))
1487 rtx src = SET_SRC (set);
1489 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
1490 /* If X is narrower than a word and SRC is a non-negative
1491 constant that would appear negative in the mode of X,
1492 sign-extend it for use in reg_stat[].nonzero_bits because some
1493 machines (maybe most) will actually do the sign-extension
1494 and this is the conservative approach.
1496 ??? For 2.5, try to tighten up the MD files in this regard
1497 instead of this kludge. */
1499 if (GET_MODE_BITSIZE (GET_MODE (x)) < BITS_PER_WORD
1500 && GET_CODE (src) == CONST_INT
1502 && 0 != (INTVAL (src)
1503 & ((HOST_WIDE_INT) 1
1504 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
1505 src = GEN_INT (INTVAL (src)
1506 | ((HOST_WIDE_INT) (-1)
1507 << GET_MODE_BITSIZE (GET_MODE (x))));
1510 /* Don't call nonzero_bits if it cannot change anything. */
1511 if (rsp->nonzero_bits != ~(unsigned HOST_WIDE_INT) 0)
1512 rsp->nonzero_bits |= nonzero_bits (src, nonzero_bits_mode);
1513 num = num_sign_bit_copies (SET_SRC (set), GET_MODE (x));
1514 if (rsp->sign_bit_copies == 0
1515 || rsp->sign_bit_copies > num)
1516 rsp->sign_bit_copies = num;
1520 rsp->nonzero_bits = GET_MODE_MASK (GET_MODE (x));
1521 rsp->sign_bit_copies = 1;
1526 /* See if INSN can be combined into I3. PRED and SUCC are optionally
1527 insns that were previously combined into I3 or that will be combined
1528 into the merger of INSN and I3.
1530 Return 0 if the combination is not allowed for any reason.
1532 If the combination is allowed, *PDEST will be set to the single
1533 destination of INSN and *PSRC to the single source, and this function
1537 can_combine_p (rtx insn, rtx i3, rtx pred ATTRIBUTE_UNUSED, rtx succ,
1538 rtx *pdest, rtx *psrc)
1547 int all_adjacent = (succ ? (next_active_insn (insn) == succ
1548 && next_active_insn (succ) == i3)
1549 : next_active_insn (insn) == i3);
1551 /* Can combine only if previous insn is a SET of a REG, a SUBREG or CC0.
1552 or a PARALLEL consisting of such a SET and CLOBBERs.
1554 If INSN has CLOBBER parallel parts, ignore them for our processing.
1555 By definition, these happen during the execution of the insn. When it
1556 is merged with another insn, all bets are off. If they are, in fact,
1557 needed and aren't also supplied in I3, they may be added by
1558 recog_for_combine. Otherwise, it won't match.
1560 We can also ignore a SET whose SET_DEST is mentioned in a REG_UNUSED
1563 Get the source and destination of INSN. If more than one, can't
1566 if (GET_CODE (PATTERN (insn)) == SET)
1567 set = PATTERN (insn);
1568 else if (GET_CODE (PATTERN (insn)) == PARALLEL
1569 && GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == SET)
1571 for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
1573 rtx elt = XVECEXP (PATTERN (insn), 0, i);
1576 switch (GET_CODE (elt))
1578 /* This is important to combine floating point insns
1579 for the SH4 port. */
1581 /* Combining an isolated USE doesn't make sense.
1582 We depend here on combinable_i3pat to reject them. */
1583 /* The code below this loop only verifies that the inputs of
1584 the SET in INSN do not change. We call reg_set_between_p
1585 to verify that the REG in the USE does not change between
1587 If the USE in INSN was for a pseudo register, the matching
1588 insn pattern will likely match any register; combining this
1589 with any other USE would only be safe if we knew that the
1590 used registers have identical values, or if there was
1591 something to tell them apart, e.g. different modes. For
1592 now, we forgo such complicated tests and simply disallow
1593 combining of USES of pseudo registers with any other USE. */
1594 if (REG_P (XEXP (elt, 0))
1595 && GET_CODE (PATTERN (i3)) == PARALLEL)
1597 rtx i3pat = PATTERN (i3);
1598 int i = XVECLEN (i3pat, 0) - 1;
1599 unsigned int regno = REGNO (XEXP (elt, 0));
1603 rtx i3elt = XVECEXP (i3pat, 0, i);
1605 if (GET_CODE (i3elt) == USE
1606 && REG_P (XEXP (i3elt, 0))
1607 && (REGNO (XEXP (i3elt, 0)) == regno
1608 ? reg_set_between_p (XEXP (elt, 0),
1609 PREV_INSN (insn), i3)
1610 : regno >= FIRST_PSEUDO_REGISTER))
1617 /* We can ignore CLOBBERs. */
1622 /* Ignore SETs whose result isn't used but not those that
1623 have side-effects. */
1624 if (find_reg_note (insn, REG_UNUSED, SET_DEST (elt))
1625 && (!(note = find_reg_note (insn, REG_EH_REGION, NULL_RTX))
1626 || INTVAL (XEXP (note, 0)) <= 0)
1627 && ! side_effects_p (elt))
1630 /* If we have already found a SET, this is a second one and
1631 so we cannot combine with this insn. */
1639 /* Anything else means we can't combine. */
1645 /* If SET_SRC is an ASM_OPERANDS we can't throw away these CLOBBERs,
1646 so don't do anything with it. */
1647 || GET_CODE (SET_SRC (set)) == ASM_OPERANDS)
1656 set = expand_field_assignment (set);
1657 src = SET_SRC (set), dest = SET_DEST (set);
1659 /* Don't eliminate a store in the stack pointer. */
1660 if (dest == stack_pointer_rtx
1661 /* Don't combine with an insn that sets a register to itself if it has
1662 a REG_EQUAL note. This may be part of a LIBCALL sequence. */
1663 || (rtx_equal_p (src, dest) && find_reg_note (insn, REG_EQUAL, NULL_RTX))
1664 /* Can't merge an ASM_OPERANDS. */
1665 || GET_CODE (src) == ASM_OPERANDS
1666 /* Can't merge a function call. */
1667 || GET_CODE (src) == CALL
1668 /* Don't eliminate a function call argument. */
1670 && (find_reg_fusage (i3, USE, dest)
1672 && REGNO (dest) < FIRST_PSEUDO_REGISTER
1673 && global_regs[REGNO (dest)])))
1674 /* Don't substitute into an incremented register. */
1675 || FIND_REG_INC_NOTE (i3, dest)
1676 || (succ && FIND_REG_INC_NOTE (succ, dest))
1677 /* Don't substitute into a non-local goto, this confuses CFG. */
1678 || (JUMP_P (i3) && find_reg_note (i3, REG_NON_LOCAL_GOTO, NULL_RTX))
1680 /* Don't combine the end of a libcall into anything. */
1681 /* ??? This gives worse code, and appears to be unnecessary, since no
1682 pass after flow uses REG_LIBCALL/REG_RETVAL notes. Local-alloc does
1683 use REG_RETVAL notes for noconflict blocks, but other code here
1684 makes sure that those insns don't disappear. */
1685 || find_reg_note (insn, REG_RETVAL, NULL_RTX)
1687 /* Make sure that DEST is not used after SUCC but before I3. */
1688 || (succ && ! all_adjacent
1689 && reg_used_between_p (dest, succ, i3))
1690 /* Make sure that the value that is to be substituted for the register
1691 does not use any registers whose values alter in between. However,
1692 If the insns are adjacent, a use can't cross a set even though we
1693 think it might (this can happen for a sequence of insns each setting
1694 the same destination; last_set of that register might point to
1695 a NOTE). If INSN has a REG_EQUIV note, the register is always
1696 equivalent to the memory so the substitution is valid even if there
1697 are intervening stores. Also, don't move a volatile asm or
1698 UNSPEC_VOLATILE across any other insns. */
1701 || ! find_reg_note (insn, REG_EQUIV, src))
1702 && use_crosses_set_p (src, DF_INSN_LUID (insn)))
1703 || (GET_CODE (src) == ASM_OPERANDS && MEM_VOLATILE_P (src))
1704 || GET_CODE (src) == UNSPEC_VOLATILE))
1705 /* Don't combine across a CALL_INSN, because that would possibly
1706 change whether the life span of some REGs crosses calls or not,
1707 and it is a pain to update that information.
1708 Exception: if source is a constant, moving it later can't hurt.
1709 Accept that as a special case. */
1710 || (DF_INSN_LUID (insn) < last_call_luid && ! CONSTANT_P (src)))
1713 /* DEST must either be a REG or CC0. */
1716 /* If register alignment is being enforced for multi-word items in all
1717 cases except for parameters, it is possible to have a register copy
1718 insn referencing a hard register that is not allowed to contain the
1719 mode being copied and which would not be valid as an operand of most
1720 insns. Eliminate this problem by not combining with such an insn.
1722 Also, on some machines we don't want to extend the life of a hard
1726 && ((REGNO (dest) < FIRST_PSEUDO_REGISTER
1727 && ! HARD_REGNO_MODE_OK (REGNO (dest), GET_MODE (dest)))
1728 /* Don't extend the life of a hard register unless it is
1729 user variable (if we have few registers) or it can't
1730 fit into the desired register (meaning something special
1732 Also avoid substituting a return register into I3, because
1733 reload can't handle a conflict with constraints of other
1735 || (REGNO (src) < FIRST_PSEUDO_REGISTER
1736 && ! HARD_REGNO_MODE_OK (REGNO (src), GET_MODE (src)))))
1739 else if (GET_CODE (dest) != CC0)
1743 if (GET_CODE (PATTERN (i3)) == PARALLEL)
1744 for (i = XVECLEN (PATTERN (i3), 0) - 1; i >= 0; i--)
1745 if (GET_CODE (XVECEXP (PATTERN (i3), 0, i)) == CLOBBER)
1747 /* Don't substitute for a register intended as a clobberable
1749 rtx reg = XEXP (XVECEXP (PATTERN (i3), 0, i), 0);
1750 if (rtx_equal_p (reg, dest))
1753 /* If the clobber represents an earlyclobber operand, we must not
1754 substitute an expression containing the clobbered register.
1755 As we do not analyze the constraint strings here, we have to
1756 make the conservative assumption. However, if the register is
1757 a fixed hard reg, the clobber cannot represent any operand;
1758 we leave it up to the machine description to either accept or
1759 reject use-and-clobber patterns. */
1761 || REGNO (reg) >= FIRST_PSEUDO_REGISTER
1762 || !fixed_regs[REGNO (reg)])
1763 if (reg_overlap_mentioned_p (reg, src))
1767 /* If INSN contains anything volatile, or is an `asm' (whether volatile
1768 or not), reject, unless nothing volatile comes between it and I3 */
1770 if (GET_CODE (src) == ASM_OPERANDS || volatile_refs_p (src))
1772 /* Make sure succ doesn't contain a volatile reference. */
1773 if (succ != 0 && volatile_refs_p (PATTERN (succ)))
1776 for (p = NEXT_INSN (insn); p != i3; p = NEXT_INSN (p))
1777 if (INSN_P (p) && p != succ && volatile_refs_p (PATTERN (p)))
1781 /* If INSN is an asm, and DEST is a hard register, reject, since it has
1782 to be an explicit register variable, and was chosen for a reason. */
1784 if (GET_CODE (src) == ASM_OPERANDS
1785 && REG_P (dest) && REGNO (dest) < FIRST_PSEUDO_REGISTER)
1788 /* If there are any volatile insns between INSN and I3, reject, because
1789 they might affect machine state. */
1791 for (p = NEXT_INSN (insn); p != i3; p = NEXT_INSN (p))
1792 if (INSN_P (p) && p != succ && volatile_insn_p (PATTERN (p)))
1795 /* If INSN contains an autoincrement or autodecrement, make sure that
1796 register is not used between there and I3, and not already used in
1797 I3 either. Neither must it be used in PRED or SUCC, if they exist.
1798 Also insist that I3 not be a jump; if it were one
1799 and the incremented register were spilled, we would lose. */
1802 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
1803 if (REG_NOTE_KIND (link) == REG_INC
1805 || reg_used_between_p (XEXP (link, 0), insn, i3)
1806 || (pred != NULL_RTX
1807 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (pred)))
1808 || (succ != NULL_RTX
1809 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (succ)))
1810 || reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i3))))
1815 /* Don't combine an insn that follows a CC0-setting insn.
1816 An insn that uses CC0 must not be separated from the one that sets it.
1817 We do, however, allow I2 to follow a CC0-setting insn if that insn
1818 is passed as I1; in that case it will be deleted also.
1819 We also allow combining in this case if all the insns are adjacent
1820 because that would leave the two CC0 insns adjacent as well.
1821 It would be more logical to test whether CC0 occurs inside I1 or I2,
1822 but that would be much slower, and this ought to be equivalent. */
1824 p = prev_nonnote_insn (insn);
1825 if (p && p != pred && NONJUMP_INSN_P (p) && sets_cc0_p (PATTERN (p))
1830 /* If we get here, we have passed all the tests and the combination is
1839 /* LOC is the location within I3 that contains its pattern or the component
1840 of a PARALLEL of the pattern. We validate that it is valid for combining.
1842 One problem is if I3 modifies its output, as opposed to replacing it
1843 entirely, we can't allow the output to contain I2DEST or I1DEST as doing
1844 so would produce an insn that is not equivalent to the original insns.
1848 (set (reg:DI 101) (reg:DI 100))
1849 (set (subreg:SI (reg:DI 101) 0) <foo>)
1851 This is NOT equivalent to:
1853 (parallel [(set (subreg:SI (reg:DI 100) 0) <foo>)
1854 (set (reg:DI 101) (reg:DI 100))])
1856 Not only does this modify 100 (in which case it might still be valid
1857 if 100 were dead in I2), it sets 101 to the ORIGINAL value of 100.
1859 We can also run into a problem if I2 sets a register that I1
1860 uses and I1 gets directly substituted into I3 (not via I2). In that
1861 case, we would be getting the wrong value of I2DEST into I3, so we
1862 must reject the combination. This case occurs when I2 and I1 both
1863 feed into I3, rather than when I1 feeds into I2, which feeds into I3.
1864 If I1_NOT_IN_SRC is nonzero, it means that finding I1 in the source
1865 of a SET must prevent combination from occurring.
1867 Before doing the above check, we first try to expand a field assignment
1868 into a set of logical operations.
1870 If PI3_DEST_KILLED is nonzero, it is a pointer to a location in which
1871 we place a register that is both set and used within I3. If more than one
1872 such register is detected, we fail.
1874 Return 1 if the combination is valid, zero otherwise. */
1877 combinable_i3pat (rtx i3, rtx *loc, rtx i2dest, rtx i1dest,
1878 int i1_not_in_src, rtx *pi3dest_killed)
1882 if (GET_CODE (x) == SET)
1885 rtx dest = SET_DEST (set);
1886 rtx src = SET_SRC (set);
1887 rtx inner_dest = dest;
1890 while (GET_CODE (inner_dest) == STRICT_LOW_PART
1891 || GET_CODE (inner_dest) == SUBREG
1892 || GET_CODE (inner_dest) == ZERO_EXTRACT)
1893 inner_dest = XEXP (inner_dest, 0);
1895 /* Check for the case where I3 modifies its output, as discussed
1896 above. We don't want to prevent pseudos from being combined
1897 into the address of a MEM, so only prevent the combination if
1898 i1 or i2 set the same MEM. */
1899 if ((inner_dest != dest &&
1900 (!MEM_P (inner_dest)
1901 || rtx_equal_p (i2dest, inner_dest)
1902 || (i1dest && rtx_equal_p (i1dest, inner_dest)))
1903 && (reg_overlap_mentioned_p (i2dest, inner_dest)
1904 || (i1dest && reg_overlap_mentioned_p (i1dest, inner_dest))))
1906 /* This is the same test done in can_combine_p except we can't test
1907 all_adjacent; we don't have to, since this instruction will stay
1908 in place, thus we are not considering increasing the lifetime of
1911 Also, if this insn sets a function argument, combining it with
1912 something that might need a spill could clobber a previous
1913 function argument; the all_adjacent test in can_combine_p also
1914 checks this; here, we do a more specific test for this case. */
1916 || (REG_P (inner_dest)
1917 && REGNO (inner_dest) < FIRST_PSEUDO_REGISTER
1918 && (! HARD_REGNO_MODE_OK (REGNO (inner_dest),
1919 GET_MODE (inner_dest))))
1920 || (i1_not_in_src && reg_overlap_mentioned_p (i1dest, src)))
1923 /* If DEST is used in I3, it is being killed in this insn, so
1924 record that for later. We have to consider paradoxical
1925 subregs here, since they kill the whole register, but we
1926 ignore partial subregs, STRICT_LOW_PART, etc.
1927 Never add REG_DEAD notes for the FRAME_POINTER_REGNUM or the
1928 STACK_POINTER_REGNUM, since these are always considered to be
1929 live. Similarly for ARG_POINTER_REGNUM if it is fixed. */
1931 if (GET_CODE (subdest) == SUBREG
1932 && (GET_MODE_SIZE (GET_MODE (subdest))
1933 >= GET_MODE_SIZE (GET_MODE (SUBREG_REG (subdest)))))
1934 subdest = SUBREG_REG (subdest);
1937 && reg_referenced_p (subdest, PATTERN (i3))
1938 && REGNO (subdest) != FRAME_POINTER_REGNUM
1939 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
1940 && REGNO (subdest) != HARD_FRAME_POINTER_REGNUM
1942 #if ARG_POINTER_REGNUM != FRAME_POINTER_REGNUM
1943 && (REGNO (subdest) != ARG_POINTER_REGNUM
1944 || ! fixed_regs [REGNO (subdest)])
1946 && REGNO (subdest) != STACK_POINTER_REGNUM)
1948 if (*pi3dest_killed)
1951 *pi3dest_killed = subdest;
1955 else if (GET_CODE (x) == PARALLEL)
1959 for (i = 0; i < XVECLEN (x, 0); i++)
1960 if (! combinable_i3pat (i3, &XVECEXP (x, 0, i), i2dest, i1dest,
1961 i1_not_in_src, pi3dest_killed))
1968 /* Return 1 if X is an arithmetic expression that contains a multiplication
1969 and division. We don't count multiplications by powers of two here. */
1972 contains_muldiv (rtx x)
1974 switch (GET_CODE (x))
1976 case MOD: case DIV: case UMOD: case UDIV:
1980 return ! (GET_CODE (XEXP (x, 1)) == CONST_INT
1981 && exact_log2 (INTVAL (XEXP (x, 1))) >= 0);
1984 return contains_muldiv (XEXP (x, 0))
1985 || contains_muldiv (XEXP (x, 1));
1988 return contains_muldiv (XEXP (x, 0));
1994 /* Determine whether INSN can be used in a combination. Return nonzero if
1995 not. This is used in try_combine to detect early some cases where we
1996 can't perform combinations. */
1999 cant_combine_insn_p (rtx insn)
2004 /* If this isn't really an insn, we can't do anything.
2005 This can occur when flow deletes an insn that it has merged into an
2006 auto-increment address. */
2007 if (! INSN_P (insn))
2010 /* Never combine loads and stores involving hard regs that are likely
2011 to be spilled. The register allocator can usually handle such
2012 reg-reg moves by tying. If we allow the combiner to make
2013 substitutions of likely-spilled regs, reload might die.
2014 As an exception, we allow combinations involving fixed regs; these are
2015 not available to the register allocator so there's no risk involved. */
2017 set = single_set (insn);
2020 src = SET_SRC (set);
2021 dest = SET_DEST (set);
2022 if (GET_CODE (src) == SUBREG)
2023 src = SUBREG_REG (src);
2024 if (GET_CODE (dest) == SUBREG)
2025 dest = SUBREG_REG (dest);
2026 if (REG_P (src) && REG_P (dest)
2027 && ((REGNO (src) < FIRST_PSEUDO_REGISTER
2028 && ! fixed_regs[REGNO (src)]
2029 && CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (REGNO (src))))
2030 || (REGNO (dest) < FIRST_PSEUDO_REGISTER
2031 && ! fixed_regs[REGNO (dest)]
2032 && CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (REGNO (dest))))))
2038 struct likely_spilled_retval_info
2040 unsigned regno, nregs;
2044 /* Called via note_stores by likely_spilled_retval_p. Remove from info->mask
2045 hard registers that are known to be written to / clobbered in full. */
2047 likely_spilled_retval_1 (rtx x, const_rtx set, void *data)
2049 struct likely_spilled_retval_info *info = data;
2050 unsigned regno, nregs;
2053 if (!REG_P (XEXP (set, 0)))
2056 if (regno >= info->regno + info->nregs)
2058 nregs = hard_regno_nregs[regno][GET_MODE (x)];
2059 if (regno + nregs <= info->regno)
2061 new_mask = (2U << (nregs - 1)) - 1;
2062 if (regno < info->regno)
2063 new_mask >>= info->regno - regno;
2065 new_mask <<= regno - info->regno;
2066 info->mask &= ~new_mask;
2069 /* Return nonzero iff part of the return value is live during INSN, and
2070 it is likely spilled. This can happen when more than one insn is needed
2071 to copy the return value, e.g. when we consider to combine into the
2072 second copy insn for a complex value. */
2075 likely_spilled_retval_p (rtx insn)
2077 rtx use = BB_END (this_basic_block);
2079 unsigned regno, nregs;
2080 /* We assume here that no machine mode needs more than
2081 32 hard registers when the value overlaps with a register
2082 for which FUNCTION_VALUE_REGNO_P is true. */
2084 struct likely_spilled_retval_info info;
2086 if (!NONJUMP_INSN_P (use) || GET_CODE (PATTERN (use)) != USE || insn == use)
2088 reg = XEXP (PATTERN (use), 0);
2089 if (!REG_P (reg) || !FUNCTION_VALUE_REGNO_P (REGNO (reg)))
2091 regno = REGNO (reg);
2092 nregs = hard_regno_nregs[regno][GET_MODE (reg)];
2095 mask = (2U << (nregs - 1)) - 1;
2097 /* Disregard parts of the return value that are set later. */
2101 for (p = PREV_INSN (use); info.mask && p != insn; p = PREV_INSN (p))
2103 note_stores (PATTERN (p), likely_spilled_retval_1, &info);
2106 /* Check if any of the (probably) live return value registers is
2111 if ((mask & 1 << nregs)
2112 && CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (regno + nregs)))
2118 /* Adjust INSN after we made a change to its destination.
2120 Changing the destination can invalidate notes that say something about
2121 the results of the insn and a LOG_LINK pointing to the insn. */
2124 adjust_for_new_dest (rtx insn)
2126 /* For notes, be conservative and simply remove them. */
2127 remove_reg_equal_equiv_notes (insn);
2129 /* The new insn will have a destination that was previously the destination
2130 of an insn just above it. Call distribute_links to make a LOG_LINK from
2131 the next use of that destination. */
2132 distribute_links (gen_rtx_INSN_LIST (VOIDmode, insn, NULL_RTX));
2134 df_insn_rescan (insn);
2137 /* Return TRUE if combine can reuse reg X in mode MODE.
2138 ADDED_SETS is nonzero if the original set is still required. */
2140 can_change_dest_mode (rtx x, int added_sets, enum machine_mode mode)
2148 /* Allow hard registers if the new mode is legal, and occupies no more
2149 registers than the old mode. */
2150 if (regno < FIRST_PSEUDO_REGISTER)
2151 return (HARD_REGNO_MODE_OK (regno, mode)
2152 && (hard_regno_nregs[regno][GET_MODE (x)]
2153 >= hard_regno_nregs[regno][mode]));
2155 /* Or a pseudo that is only used once. */
2156 return (REG_N_SETS (regno) == 1 && !added_sets
2157 && !REG_USERVAR_P (x));
2161 /* Check whether X, the destination of a set, refers to part of
2162 the register specified by REG. */
2165 reg_subword_p (rtx x, rtx reg)
2167 /* Check that reg is an integer mode register. */
2168 if (!REG_P (reg) || GET_MODE_CLASS (GET_MODE (reg)) != MODE_INT)
2171 if (GET_CODE (x) == STRICT_LOW_PART
2172 || GET_CODE (x) == ZERO_EXTRACT)
2175 return GET_CODE (x) == SUBREG
2176 && SUBREG_REG (x) == reg
2177 && GET_MODE_CLASS (GET_MODE (x)) == MODE_INT;
2181 /* Try to combine the insns I1 and I2 into I3.
2182 Here I1 and I2 appear earlier than I3.
2183 I1 can be zero; then we combine just I2 into I3.
2185 If we are combining three insns and the resulting insn is not recognized,
2186 try splitting it into two insns. If that happens, I2 and I3 are retained
2187 and I1 is pseudo-deleted by turning it into a NOTE. Otherwise, I1 and I2
2190 Return 0 if the combination does not work. Then nothing is changed.
2191 If we did the combination, return the insn at which combine should
2194 Set NEW_DIRECT_JUMP_P to a nonzero value if try_combine creates a
2195 new direct jump instruction. */
2198 try_combine (rtx i3, rtx i2, rtx i1, int *new_direct_jump_p)
2200 /* New patterns for I3 and I2, respectively. */
2201 rtx newpat, newi2pat = 0;
2202 rtvec newpat_vec_with_clobbers = 0;
2203 int substed_i2 = 0, substed_i1 = 0;
2204 /* Indicates need to preserve SET in I1 or I2 in I3 if it is not dead. */
2205 int added_sets_1, added_sets_2;
2206 /* Total number of SETs to put into I3. */
2208 /* Nonzero if I2's body now appears in I3. */
2210 /* INSN_CODEs for new I3, new I2, and user of condition code. */
2211 int insn_code_number, i2_code_number = 0, other_code_number = 0;
2212 /* Contains I3 if the destination of I3 is used in its source, which means
2213 that the old life of I3 is being killed. If that usage is placed into
2214 I2 and not in I3, a REG_DEAD note must be made. */
2215 rtx i3dest_killed = 0;
2216 /* SET_DEST and SET_SRC of I2 and I1. */
2217 rtx i2dest, i2src, i1dest = 0, i1src = 0;
2218 /* PATTERN (I1) and PATTERN (I2), or a copy of it in certain cases. */
2219 rtx i1pat = 0, i2pat = 0;
2220 /* Indicates if I2DEST or I1DEST is in I2SRC or I1_SRC. */
2221 int i2dest_in_i2src = 0, i1dest_in_i1src = 0, i2dest_in_i1src = 0;
2222 int i2dest_killed = 0, i1dest_killed = 0;
2223 int i1_feeds_i3 = 0;
2224 /* Notes that must be added to REG_NOTES in I3 and I2. */
2225 rtx new_i3_notes, new_i2_notes;
2226 /* Notes that we substituted I3 into I2 instead of the normal case. */
2227 int i3_subst_into_i2 = 0;
2228 /* Notes that I1, I2 or I3 is a MULT operation. */
2236 rtx new_other_notes;
2239 /* Exit early if one of the insns involved can't be used for
2241 if (cant_combine_insn_p (i3)
2242 || cant_combine_insn_p (i2)
2243 || (i1 && cant_combine_insn_p (i1))
2244 || likely_spilled_retval_p (i3)
2245 /* We also can't do anything if I3 has a
2246 REG_LIBCALL note since we don't want to disrupt the contiguity of a
2249 /* ??? This gives worse code, and appears to be unnecessary, since no
2250 pass after flow uses REG_LIBCALL/REG_RETVAL notes. */
2251 || find_reg_note (i3, REG_LIBCALL, NULL_RTX)
2257 undobuf.other_insn = 0;
2259 /* Reset the hard register usage information. */
2260 CLEAR_HARD_REG_SET (newpat_used_regs);
2262 /* If I1 and I2 both feed I3, they can be in any order. To simplify the
2263 code below, set I1 to be the earlier of the two insns. */
2264 if (i1 && DF_INSN_LUID (i1) > DF_INSN_LUID (i2))
2265 temp = i1, i1 = i2, i2 = temp;
2267 added_links_insn = 0;
2269 /* First check for one important special-case that the code below will
2270 not handle. Namely, the case where I1 is zero, I2 is a PARALLEL
2271 and I3 is a SET whose SET_SRC is a SET_DEST in I2. In that case,
2272 we may be able to replace that destination with the destination of I3.
2273 This occurs in the common code where we compute both a quotient and
2274 remainder into a structure, in which case we want to do the computation
2275 directly into the structure to avoid register-register copies.
2277 Note that this case handles both multiple sets in I2 and also
2278 cases where I2 has a number of CLOBBER or PARALLELs.
2280 We make very conservative checks below and only try to handle the
2281 most common cases of this. For example, we only handle the case
2282 where I2 and I3 are adjacent to avoid making difficult register
2285 if (i1 == 0 && NONJUMP_INSN_P (i3) && GET_CODE (PATTERN (i3)) == SET
2286 && REG_P (SET_SRC (PATTERN (i3)))
2287 && REGNO (SET_SRC (PATTERN (i3))) >= FIRST_PSEUDO_REGISTER
2288 && find_reg_note (i3, REG_DEAD, SET_SRC (PATTERN (i3)))
2289 && GET_CODE (PATTERN (i2)) == PARALLEL
2290 && ! side_effects_p (SET_DEST (PATTERN (i3)))
2291 /* If the dest of I3 is a ZERO_EXTRACT or STRICT_LOW_PART, the code
2292 below would need to check what is inside (and reg_overlap_mentioned_p
2293 doesn't support those codes anyway). Don't allow those destinations;
2294 the resulting insn isn't likely to be recognized anyway. */
2295 && GET_CODE (SET_DEST (PATTERN (i3))) != ZERO_EXTRACT
2296 && GET_CODE (SET_DEST (PATTERN (i3))) != STRICT_LOW_PART
2297 && ! reg_overlap_mentioned_p (SET_SRC (PATTERN (i3)),
2298 SET_DEST (PATTERN (i3)))
2299 && next_real_insn (i2) == i3)
2301 rtx p2 = PATTERN (i2);
2303 /* Make sure that the destination of I3,
2304 which we are going to substitute into one output of I2,
2305 is not used within another output of I2. We must avoid making this:
2306 (parallel [(set (mem (reg 69)) ...)
2307 (set (reg 69) ...)])
2308 which is not well-defined as to order of actions.
2309 (Besides, reload can't handle output reloads for this.)
2311 The problem can also happen if the dest of I3 is a memory ref,
2312 if another dest in I2 is an indirect memory ref. */
2313 for (i = 0; i < XVECLEN (p2, 0); i++)
2314 if ((GET_CODE (XVECEXP (p2, 0, i)) == SET
2315 || GET_CODE (XVECEXP (p2, 0, i)) == CLOBBER)
2316 && reg_overlap_mentioned_p (SET_DEST (PATTERN (i3)),
2317 SET_DEST (XVECEXP (p2, 0, i))))
2320 if (i == XVECLEN (p2, 0))
2321 for (i = 0; i < XVECLEN (p2, 0); i++)
2322 if ((GET_CODE (XVECEXP (p2, 0, i)) == SET
2323 || GET_CODE (XVECEXP (p2, 0, i)) == CLOBBER)
2324 && SET_DEST (XVECEXP (p2, 0, i)) == SET_SRC (PATTERN (i3)))
2329 subst_low_luid = DF_INSN_LUID (i2);
2331 added_sets_2 = added_sets_1 = 0;
2332 i2dest = SET_SRC (PATTERN (i3));
2333 i2dest_killed = dead_or_set_p (i2, i2dest);
2335 /* Replace the dest in I2 with our dest and make the resulting
2336 insn the new pattern for I3. Then skip to where we
2337 validate the pattern. Everything was set up above. */
2338 SUBST (SET_DEST (XVECEXP (p2, 0, i)),
2339 SET_DEST (PATTERN (i3)));
2342 i3_subst_into_i2 = 1;
2343 goto validate_replacement;
2347 /* If I2 is setting a pseudo to a constant and I3 is setting some
2348 sub-part of it to another constant, merge them by making a new
2351 && (temp = single_set (i2)) != 0
2352 && (GET_CODE (SET_SRC (temp)) == CONST_INT
2353 || GET_CODE (SET_SRC (temp)) == CONST_DOUBLE)
2354 && GET_CODE (PATTERN (i3)) == SET
2355 && (GET_CODE (SET_SRC (PATTERN (i3))) == CONST_INT
2356 || GET_CODE (SET_SRC (PATTERN (i3))) == CONST_DOUBLE)
2357 && reg_subword_p (SET_DEST (PATTERN (i3)), SET_DEST (temp)))
2359 rtx dest = SET_DEST (PATTERN (i3));
2363 if (GET_CODE (dest) == ZERO_EXTRACT)
2365 if (GET_CODE (XEXP (dest, 1)) == CONST_INT
2366 && GET_CODE (XEXP (dest, 2)) == CONST_INT)
2368 width = INTVAL (XEXP (dest, 1));
2369 offset = INTVAL (XEXP (dest, 2));
2370 dest = XEXP (dest, 0);
2371 if (BITS_BIG_ENDIAN)
2372 offset = GET_MODE_BITSIZE (GET_MODE (dest)) - width - offset;
2377 if (GET_CODE (dest) == STRICT_LOW_PART)
2378 dest = XEXP (dest, 0);
2379 width = GET_MODE_BITSIZE (GET_MODE (dest));
2385 /* If this is the low part, we're done. */
2386 if (subreg_lowpart_p (dest))
2388 /* Handle the case where inner is twice the size of outer. */
2389 else if (GET_MODE_BITSIZE (GET_MODE (SET_DEST (temp)))
2390 == 2 * GET_MODE_BITSIZE (GET_MODE (dest)))
2391 offset += GET_MODE_BITSIZE (GET_MODE (dest));
2392 /* Otherwise give up for now. */
2398 && (GET_MODE_BITSIZE (GET_MODE (SET_DEST (temp)))
2399 <= HOST_BITS_PER_WIDE_INT * 2))
2401 HOST_WIDE_INT mhi, ohi, ihi;
2402 HOST_WIDE_INT mlo, olo, ilo;
2403 rtx inner = SET_SRC (PATTERN (i3));
2404 rtx outer = SET_SRC (temp);
2406 if (GET_CODE (outer) == CONST_INT)
2408 olo = INTVAL (outer);
2409 ohi = olo < 0 ? -1 : 0;
2413 olo = CONST_DOUBLE_LOW (outer);
2414 ohi = CONST_DOUBLE_HIGH (outer);
2417 if (GET_CODE (inner) == CONST_INT)
2419 ilo = INTVAL (inner);
2420 ihi = ilo < 0 ? -1 : 0;
2424 ilo = CONST_DOUBLE_LOW (inner);
2425 ihi = CONST_DOUBLE_HIGH (inner);
2428 if (width < HOST_BITS_PER_WIDE_INT)
2430 mlo = ((unsigned HOST_WIDE_INT) 1 << width) - 1;
2433 else if (width < HOST_BITS_PER_WIDE_INT * 2)
2435 mhi = ((unsigned HOST_WIDE_INT) 1
2436 << (width - HOST_BITS_PER_WIDE_INT)) - 1;
2448 if (offset >= HOST_BITS_PER_WIDE_INT)
2450 mhi = mlo << (offset - HOST_BITS_PER_WIDE_INT);
2452 ihi = ilo << (offset - HOST_BITS_PER_WIDE_INT);
2455 else if (offset > 0)
2457 mhi = (mhi << offset) | ((unsigned HOST_WIDE_INT) mlo
2458 >> (HOST_BITS_PER_WIDE_INT - offset));
2459 mlo = mlo << offset;
2460 ihi = (ihi << offset) | ((unsigned HOST_WIDE_INT) ilo
2461 >> (HOST_BITS_PER_WIDE_INT - offset));
2462 ilo = ilo << offset;
2465 olo = (olo & ~mlo) | ilo;
2466 ohi = (ohi & ~mhi) | ihi;
2470 subst_low_luid = DF_INSN_LUID (i2);
2471 added_sets_2 = added_sets_1 = 0;
2472 i2dest = SET_DEST (temp);
2473 i2dest_killed = dead_or_set_p (i2, i2dest);
2475 SUBST (SET_SRC (temp),
2476 immed_double_const (olo, ohi, GET_MODE (SET_DEST (temp))));
2478 newpat = PATTERN (i2);
2479 goto validate_replacement;
2484 /* If we have no I1 and I2 looks like:
2485 (parallel [(set (reg:CC X) (compare:CC OP (const_int 0)))
2487 make up a dummy I1 that is
2490 (set (reg:CC X) (compare:CC Y (const_int 0)))
2492 (We can ignore any trailing CLOBBERs.)
2494 This undoes a previous combination and allows us to match a branch-and-
2497 if (i1 == 0 && GET_CODE (PATTERN (i2)) == PARALLEL
2498 && XVECLEN (PATTERN (i2), 0) >= 2
2499 && GET_CODE (XVECEXP (PATTERN (i2), 0, 0)) == SET
2500 && (GET_MODE_CLASS (GET_MODE (SET_DEST (XVECEXP (PATTERN (i2), 0, 0))))
2502 && GET_CODE (SET_SRC (XVECEXP (PATTERN (i2), 0, 0))) == COMPARE
2503 && XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 1) == const0_rtx
2504 && GET_CODE (XVECEXP (PATTERN (i2), 0, 1)) == SET
2505 && REG_P (SET_DEST (XVECEXP (PATTERN (i2), 0, 1)))
2506 && rtx_equal_p (XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 0),
2507 SET_SRC (XVECEXP (PATTERN (i2), 0, 1))))
2509 for (i = XVECLEN (PATTERN (i2), 0) - 1; i >= 2; i--)
2510 if (GET_CODE (XVECEXP (PATTERN (i2), 0, i)) != CLOBBER)
2515 /* We make I1 with the same INSN_UID as I2. This gives it
2516 the same DF_INSN_LUID for value tracking. Our fake I1 will
2517 never appear in the insn stream so giving it the same INSN_UID
2518 as I2 will not cause a problem. */
2520 i1 = gen_rtx_INSN (VOIDmode, INSN_UID (i2), NULL_RTX, i2,
2521 BLOCK_FOR_INSN (i2), INSN_LOCATOR (i2),
2522 XVECEXP (PATTERN (i2), 0, 1), -1, NULL_RTX);
2524 SUBST (PATTERN (i2), XVECEXP (PATTERN (i2), 0, 0));
2525 SUBST (XEXP (SET_SRC (PATTERN (i2)), 0),
2526 SET_DEST (PATTERN (i1)));
2531 /* Verify that I2 and I1 are valid for combining. */
2532 if (! can_combine_p (i2, i3, i1, NULL_RTX, &i2dest, &i2src)
2533 || (i1 && ! can_combine_p (i1, i3, NULL_RTX, i2, &i1dest, &i1src)))
2539 /* Record whether I2DEST is used in I2SRC and similarly for the other
2540 cases. Knowing this will help in register status updating below. */
2541 i2dest_in_i2src = reg_overlap_mentioned_p (i2dest, i2src);
2542 i1dest_in_i1src = i1 && reg_overlap_mentioned_p (i1dest, i1src);
2543 i2dest_in_i1src = i1 && reg_overlap_mentioned_p (i2dest, i1src);
2544 i2dest_killed = dead_or_set_p (i2, i2dest);
2545 i1dest_killed = i1 && dead_or_set_p (i1, i1dest);
2547 /* See if I1 directly feeds into I3. It does if I1DEST is not used
2549 i1_feeds_i3 = i1 && ! reg_overlap_mentioned_p (i1dest, i2src);
2551 /* Ensure that I3's pattern can be the destination of combines. */
2552 if (! combinable_i3pat (i3, &PATTERN (i3), i2dest, i1dest,
2553 i1 && i2dest_in_i1src && i1_feeds_i3,
2560 /* See if any of the insns is a MULT operation. Unless one is, we will
2561 reject a combination that is, since it must be slower. Be conservative
2563 if (GET_CODE (i2src) == MULT
2564 || (i1 != 0 && GET_CODE (i1src) == MULT)
2565 || (GET_CODE (PATTERN (i3)) == SET
2566 && GET_CODE (SET_SRC (PATTERN (i3))) == MULT))
2569 /* If I3 has an inc, then give up if I1 or I2 uses the reg that is inc'd.
2570 We used to do this EXCEPT in one case: I3 has a post-inc in an
2571 output operand. However, that exception can give rise to insns like
2573 which is a famous insn on the PDP-11 where the value of r3 used as the
2574 source was model-dependent. Avoid this sort of thing. */
2577 if (!(GET_CODE (PATTERN (i3)) == SET
2578 && REG_P (SET_SRC (PATTERN (i3)))
2579 && MEM_P (SET_DEST (PATTERN (i3)))
2580 && (GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_INC
2581 || GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_DEC)))
2582 /* It's not the exception. */
2585 for (link = REG_NOTES (i3); link; link = XEXP (link, 1))
2586 if (REG_NOTE_KIND (link) == REG_INC
2587 && (reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i2))
2589 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i1)))))
2596 /* See if the SETs in I1 or I2 need to be kept around in the merged
2597 instruction: whenever the value set there is still needed past I3.
2598 For the SETs in I2, this is easy: we see if I2DEST dies or is set in I3.
2600 For the SET in I1, we have two cases: If I1 and I2 independently
2601 feed into I3, the set in I1 needs to be kept around if I1DEST dies
2602 or is set in I3. Otherwise (if I1 feeds I2 which feeds I3), the set
2603 in I1 needs to be kept around unless I1DEST dies or is set in either
2604 I2 or I3. We can distinguish these cases by seeing if I2SRC mentions
2605 I1DEST. If so, we know I1 feeds into I2. */
2607 added_sets_2 = ! dead_or_set_p (i3, i2dest);
2610 = i1 && ! (i1_feeds_i3 ? dead_or_set_p (i3, i1dest)
2611 : (dead_or_set_p (i3, i1dest) || dead_or_set_p (i2, i1dest)));
2613 /* If the set in I2 needs to be kept around, we must make a copy of
2614 PATTERN (I2), so that when we substitute I1SRC for I1DEST in
2615 PATTERN (I2), we are only substituting for the original I1DEST, not into
2616 an already-substituted copy. This also prevents making self-referential
2617 rtx. If I2 is a PARALLEL, we just need the piece that assigns I2SRC to
2622 if (GET_CODE (PATTERN (i2)) == PARALLEL)
2623 i2pat = gen_rtx_SET (VOIDmode, i2dest, copy_rtx (i2src));
2625 i2pat = copy_rtx (PATTERN (i2));
2630 if (GET_CODE (PATTERN (i1)) == PARALLEL)
2631 i1pat = gen_rtx_SET (VOIDmode, i1dest, copy_rtx (i1src));
2633 i1pat = copy_rtx (PATTERN (i1));
2638 /* Substitute in the latest insn for the regs set by the earlier ones. */
2640 maxreg = max_reg_num ();
2645 /* Many machines that don't use CC0 have insns that can both perform an
2646 arithmetic operation and set the condition code. These operations will
2647 be represented as a PARALLEL with the first element of the vector
2648 being a COMPARE of an arithmetic operation with the constant zero.
2649 The second element of the vector will set some pseudo to the result
2650 of the same arithmetic operation. If we simplify the COMPARE, we won't
2651 match such a pattern and so will generate an extra insn. Here we test
2652 for this case, where both the comparison and the operation result are
2653 needed, and make the PARALLEL by just replacing I2DEST in I3SRC with
2654 I2SRC. Later we will make the PARALLEL that contains I2. */
2656 if (i1 == 0 && added_sets_2 && GET_CODE (PATTERN (i3)) == SET
2657 && GET_CODE (SET_SRC (PATTERN (i3))) == COMPARE
2658 && XEXP (SET_SRC (PATTERN (i3)), 1) == const0_rtx
2659 && rtx_equal_p (XEXP (SET_SRC (PATTERN (i3)), 0), i2dest))
2661 #ifdef SELECT_CC_MODE
2663 enum machine_mode compare_mode;
2666 newpat = PATTERN (i3);
2667 SUBST (XEXP (SET_SRC (newpat), 0), i2src);
2671 #ifdef SELECT_CC_MODE
2672 /* See if a COMPARE with the operand we substituted in should be done
2673 with the mode that is currently being used. If not, do the same
2674 processing we do in `subst' for a SET; namely, if the destination
2675 is used only once, try to replace it with a register of the proper
2676 mode and also replace the COMPARE. */
2677 if (undobuf.other_insn == 0
2678 && (cc_use = find_single_use (SET_DEST (newpat), i3,
2679 &undobuf.other_insn))
2680 && ((compare_mode = SELECT_CC_MODE (GET_CODE (*cc_use),
2682 != GET_MODE (SET_DEST (newpat))))
2684 if (can_change_dest_mode(SET_DEST (newpat), added_sets_2,
2687 unsigned int regno = REGNO (SET_DEST (newpat));
2690 if (regno < FIRST_PSEUDO_REGISTER)
2691 new_dest = gen_rtx_REG (compare_mode, regno);
2694 SUBST_MODE (regno_reg_rtx[regno], compare_mode);
2695 new_dest = regno_reg_rtx[regno];
2698 SUBST (SET_DEST (newpat), new_dest);
2699 SUBST (XEXP (*cc_use, 0), new_dest);
2700 SUBST (SET_SRC (newpat),
2701 gen_rtx_COMPARE (compare_mode, i2src, const0_rtx));
2704 undobuf.other_insn = 0;
2711 /* It is possible that the source of I2 or I1 may be performing
2712 an unneeded operation, such as a ZERO_EXTEND of something
2713 that is known to have the high part zero. Handle that case
2714 by letting subst look at the innermost one of them.
2716 Another way to do this would be to have a function that tries
2717 to simplify a single insn instead of merging two or more
2718 insns. We don't do this because of the potential of infinite
2719 loops and because of the potential extra memory required.
2720 However, doing it the way we are is a bit of a kludge and
2721 doesn't catch all cases.
2723 But only do this if -fexpensive-optimizations since it slows
2724 things down and doesn't usually win.
2726 This is not done in the COMPARE case above because the
2727 unmodified I2PAT is used in the PARALLEL and so a pattern
2728 with a modified I2SRC would not match. */
2730 if (flag_expensive_optimizations)
2732 /* Pass pc_rtx so no substitutions are done, just
2736 subst_low_luid = DF_INSN_LUID (i1);
2737 i1src = subst (i1src, pc_rtx, pc_rtx, 0, 0);
2741 subst_low_luid = DF_INSN_LUID (i2);
2742 i2src = subst (i2src, pc_rtx, pc_rtx, 0, 0);
2746 n_occurrences = 0; /* `subst' counts here */
2748 /* If I1 feeds into I2 (not into I3) and I1DEST is in I1SRC, we
2749 need to make a unique copy of I2SRC each time we substitute it
2750 to avoid self-referential rtl. */
2752 subst_low_luid = DF_INSN_LUID (i2);
2753 newpat = subst (PATTERN (i3), i2dest, i2src, 0,
2754 ! i1_feeds_i3 && i1dest_in_i1src);
2757 /* Record whether i2's body now appears within i3's body. */
2758 i2_is_used = n_occurrences;
2761 /* If we already got a failure, don't try to do more. Otherwise,
2762 try to substitute in I1 if we have it. */
2764 if (i1 && GET_CODE (newpat) != CLOBBER)
2766 /* Check that an autoincrement side-effect on I1 has not been lost.
2767 This happens if I1DEST is mentioned in I2 and dies there, and
2768 has disappeared from the new pattern. */
2769 if ((FIND_REG_INC_NOTE (i1, NULL_RTX) != 0
2771 && dead_or_set_p (i2, i1dest)
2772 && !reg_overlap_mentioned_p (i1dest, newpat))
2773 /* Before we can do this substitution, we must redo the test done
2774 above (see detailed comments there) that ensures that I1DEST
2775 isn't mentioned in any SETs in NEWPAT that are field assignments. */
2776 || !combinable_i3pat (NULL_RTX, &newpat, i1dest, NULL_RTX, 0, 0))
2783 subst_low_luid = DF_INSN_LUID (i1);
2784 newpat = subst (newpat, i1dest, i1src, 0, 0);
2788 /* Fail if an autoincrement side-effect has been duplicated. Be careful
2789 to count all the ways that I2SRC and I1SRC can be used. */
2790 if ((FIND_REG_INC_NOTE (i2, NULL_RTX) != 0
2791 && i2_is_used + added_sets_2 > 1)
2792 || (i1 != 0 && FIND_REG_INC_NOTE (i1, NULL_RTX) != 0
2793 && (n_occurrences + added_sets_1 + (added_sets_2 && ! i1_feeds_i3)
2795 /* Fail if we tried to make a new register. */
2796 || max_reg_num () != maxreg
2797 /* Fail if we couldn't do something and have a CLOBBER. */
2798 || GET_CODE (newpat) == CLOBBER
2799 /* Fail if this new pattern is a MULT and we didn't have one before
2800 at the outer level. */
2801 || (GET_CODE (newpat) == SET && GET_CODE (SET_SRC (newpat)) == MULT
2808 /* If the actions of the earlier insns must be kept
2809 in addition to substituting them into the latest one,
2810 we must make a new PARALLEL for the latest insn
2811 to hold additional the SETs. */
2813 if (added_sets_1 || added_sets_2)
2817 if (GET_CODE (newpat) == PARALLEL)
2819 rtvec old = XVEC (newpat, 0);
2820 total_sets = XVECLEN (newpat, 0) + added_sets_1 + added_sets_2;
2821 newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (total_sets));
2822 memcpy (XVEC (newpat, 0)->elem, &old->elem[0],
2823 sizeof (old->elem[0]) * old->num_elem);
2828 total_sets = 1 + added_sets_1 + added_sets_2;
2829 newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (total_sets));
2830 XVECEXP (newpat, 0, 0) = old;
2834 XVECEXP (newpat, 0, --total_sets) = i1pat;
2838 /* If there is no I1, use I2's body as is. We used to also not do
2839 the subst call below if I2 was substituted into I3,
2840 but that could lose a simplification. */
2842 XVECEXP (newpat, 0, --total_sets) = i2pat;
2844 /* See comment where i2pat is assigned. */
2845 XVECEXP (newpat, 0, --total_sets)
2846 = subst (i2pat, i1dest, i1src, 0, 0);
2850 /* We come here when we are replacing a destination in I2 with the
2851 destination of I3. */
2852 validate_replacement:
2854 /* Note which hard regs this insn has as inputs. */
2855 mark_used_regs_combine (newpat);
2857 /* If recog_for_combine fails, it strips existing clobbers. If we'll
2858 consider splitting this pattern, we might need these clobbers. */
2859 if (i1 && GET_CODE (newpat) == PARALLEL
2860 && GET_CODE (XVECEXP (newpat, 0, XVECLEN (newpat, 0) - 1)) == CLOBBER)
2862 int len = XVECLEN (newpat, 0);
2864 newpat_vec_with_clobbers = rtvec_alloc (len);
2865 for (i = 0; i < len; i++)
2866 RTVEC_ELT (newpat_vec_with_clobbers, i) = XVECEXP (newpat, 0, i);
2869 /* Is the result of combination a valid instruction? */
2870 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2872 /* If the result isn't valid, see if it is a PARALLEL of two SETs where
2873 the second SET's destination is a register that is unused and isn't
2874 marked as an instruction that might trap in an EH region. In that case,
2875 we just need the first SET. This can occur when simplifying a divmod
2876 insn. We *must* test for this case here because the code below that
2877 splits two independent SETs doesn't handle this case correctly when it
2878 updates the register status.
2880 It's pointless doing this if we originally had two sets, one from
2881 i3, and one from i2. Combining then splitting the parallel results
2882 in the original i2 again plus an invalid insn (which we delete).
2883 The net effect is only to move instructions around, which makes
2884 debug info less accurate.
2886 Also check the case where the first SET's destination is unused.
2887 That would not cause incorrect code, but does cause an unneeded
2890 if (insn_code_number < 0
2891 && !(added_sets_2 && i1 == 0)
2892 && GET_CODE (newpat) == PARALLEL
2893 && XVECLEN (newpat, 0) == 2
2894 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
2895 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
2896 && asm_noperands (newpat) < 0)
2898 rtx set0 = XVECEXP (newpat, 0, 0);
2899 rtx set1 = XVECEXP (newpat, 0, 1);
2902 if (((REG_P (SET_DEST (set1))
2903 && find_reg_note (i3, REG_UNUSED, SET_DEST (set1)))
2904 || (GET_CODE (SET_DEST (set1)) == SUBREG
2905 && find_reg_note (i3, REG_UNUSED, SUBREG_REG (SET_DEST (set1)))))
2906 && (!(note = find_reg_note (i3, REG_EH_REGION, NULL_RTX))
2907 || INTVAL (XEXP (note, 0)) <= 0)
2908 && ! side_effects_p (SET_SRC (set1)))
2911 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2914 else if (((REG_P (SET_DEST (set0))
2915 && find_reg_note (i3, REG_UNUSED, SET_DEST (set0)))
2916 || (GET_CODE (SET_DEST (set0)) == SUBREG
2917 && find_reg_note (i3, REG_UNUSED,
2918 SUBREG_REG (SET_DEST (set0)))))
2919 && (!(note = find_reg_note (i3, REG_EH_REGION, NULL_RTX))
2920 || INTVAL (XEXP (note, 0)) <= 0)
2921 && ! side_effects_p (SET_SRC (set0)))
2924 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2926 if (insn_code_number >= 0)
2928 /* If we will be able to accept this, we have made a
2929 change to the destination of I3. This requires us to
2930 do a few adjustments. */
2932 PATTERN (i3) = newpat;
2933 adjust_for_new_dest (i3);
2938 /* If we were combining three insns and the result is a simple SET
2939 with no ASM_OPERANDS that wasn't recognized, try to split it into two
2940 insns. There are two ways to do this. It can be split using a
2941 machine-specific method (like when you have an addition of a large
2942 constant) or by combine in the function find_split_point. */
2944 if (i1 && insn_code_number < 0 && GET_CODE (newpat) == SET
2945 && asm_noperands (newpat) < 0)
2947 rtx parallel, m_split, *split;
2949 /* See if the MD file can split NEWPAT. If it can't, see if letting it
2950 use I2DEST as a scratch register will help. In the latter case,
2951 convert I2DEST to the mode of the source of NEWPAT if we can. */
2953 m_split = combine_split_insns (newpat, i3);
2955 /* We can only use I2DEST as a scratch reg if it doesn't overlap any
2956 inputs of NEWPAT. */
2958 /* ??? If I2DEST is not safe, and I1DEST exists, then it would be
2959 possible to try that as a scratch reg. This would require adding
2960 more code to make it work though. */
2962 if (m_split == 0 && ! reg_overlap_mentioned_p (i2dest, newpat))
2964 enum machine_mode new_mode = GET_MODE (SET_DEST (newpat));
2966 /* First try to split using the original register as a
2967 scratch register. */
2968 parallel = gen_rtx_PARALLEL (VOIDmode,
2969 gen_rtvec (2, newpat,
2970 gen_rtx_CLOBBER (VOIDmode,
2972 m_split = combine_split_insns (parallel, i3);
2974 /* If that didn't work, try changing the mode of I2DEST if
2977 && new_mode != GET_MODE (i2dest)
2978 && new_mode != VOIDmode
2979 && can_change_dest_mode (i2dest, added_sets_2, new_mode))
2981 enum machine_mode old_mode = GET_MODE (i2dest);
2984 if (REGNO (i2dest) < FIRST_PSEUDO_REGISTER)
2985 ni2dest = gen_rtx_REG (new_mode, REGNO (i2dest));
2988 SUBST_MODE (regno_reg_rtx[REGNO (i2dest)], new_mode);
2989 ni2dest = regno_reg_rtx[REGNO (i2dest)];
2992 parallel = (gen_rtx_PARALLEL
2994 gen_rtvec (2, newpat,
2995 gen_rtx_CLOBBER (VOIDmode,
2997 m_split = combine_split_insns (parallel, i3);
3000 && REGNO (i2dest) >= FIRST_PSEUDO_REGISTER)
3004 adjust_reg_mode (regno_reg_rtx[REGNO (i2dest)], old_mode);
3005 buf = undobuf.undos;
3006 undobuf.undos = buf->next;
3007 buf->next = undobuf.frees;
3008 undobuf.frees = buf;
3013 /* If recog_for_combine has discarded clobbers, try to use them
3014 again for the split. */
3015 if (m_split == 0 && newpat_vec_with_clobbers)
3017 parallel = gen_rtx_PARALLEL (VOIDmode, newpat_vec_with_clobbers);
3018 m_split = combine_split_insns (parallel, i3);
3021 if (m_split && NEXT_INSN (m_split) == NULL_RTX)
3023 m_split = PATTERN (m_split);
3024 insn_code_number = recog_for_combine (&m_split, i3, &new_i3_notes);
3025 if (insn_code_number >= 0)
3028 else if (m_split && NEXT_INSN (NEXT_INSN (m_split)) == NULL_RTX
3029 && (next_real_insn (i2) == i3
3030 || ! use_crosses_set_p (PATTERN (m_split), DF_INSN_LUID (i2))))
3033 rtx newi3pat = PATTERN (NEXT_INSN (m_split));
3034 newi2pat = PATTERN (m_split);
3036 i3set = single_set (NEXT_INSN (m_split));
3037 i2set = single_set (m_split);
3039 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
3041 /* If I2 or I3 has multiple SETs, we won't know how to track
3042 register status, so don't use these insns. If I2's destination
3043 is used between I2 and I3, we also can't use these insns. */
3045 if (i2_code_number >= 0 && i2set && i3set
3046 && (next_real_insn (i2) == i3
3047 || ! reg_used_between_p (SET_DEST (i2set), i2, i3)))
3048 insn_code_number = recog_for_combine (&newi3pat, i3,
3050 if (insn_code_number >= 0)
3053 /* It is possible that both insns now set the destination of I3.
3054 If so, we must show an extra use of it. */
3056 if (insn_code_number >= 0)
3058 rtx new_i3_dest = SET_DEST (i3set);
3059 rtx new_i2_dest = SET_DEST (i2set);
3061 while (GET_CODE (new_i3_dest) == ZERO_EXTRACT
3062 || GET_CODE (new_i3_dest) == STRICT_LOW_PART
3063 || GET_CODE (new_i3_dest) == SUBREG)
3064 new_i3_dest = XEXP (new_i3_dest, 0);
3066 while (GET_CODE (new_i2_dest) == ZERO_EXTRACT
3067 || GET_CODE (new_i2_dest) == STRICT_LOW_PART
3068 || GET_CODE (new_i2_dest) == SUBREG)
3069 new_i2_dest = XEXP (new_i2_dest, 0);
3071 if (REG_P (new_i3_dest)
3072 && REG_P (new_i2_dest)
3073 && REGNO (new_i3_dest) == REGNO (new_i2_dest))
3074 INC_REG_N_SETS (REGNO (new_i2_dest), 1);
3078 /* If we can split it and use I2DEST, go ahead and see if that
3079 helps things be recognized. Verify that none of the registers
3080 are set between I2 and I3. */
3081 if (insn_code_number < 0 && (split = find_split_point (&newpat, i3)) != 0
3085 /* We need I2DEST in the proper mode. If it is a hard register
3086 or the only use of a pseudo, we can change its mode.
3087 Make sure we don't change a hard register to have a mode that
3088 isn't valid for it, or change the number of registers. */
3089 && (GET_MODE (*split) == GET_MODE (i2dest)
3090 || GET_MODE (*split) == VOIDmode
3091 || can_change_dest_mode (i2dest, added_sets_2,
3093 && (next_real_insn (i2) == i3
3094 || ! use_crosses_set_p (*split, DF_INSN_LUID (i2)))
3095 /* We can't overwrite I2DEST if its value is still used by
3097 && ! reg_referenced_p (i2dest, newpat))
3099 rtx newdest = i2dest;
3100 enum rtx_code split_code = GET_CODE (*split);
3101 enum machine_mode split_mode = GET_MODE (*split);
3102 bool subst_done = false;
3103 newi2pat = NULL_RTX;
3105 /* Get NEWDEST as a register in the proper mode. We have already
3106 validated that we can do this. */
3107 if (GET_MODE (i2dest) != split_mode && split_mode != VOIDmode)
3109 if (REGNO (i2dest) < FIRST_PSEUDO_REGISTER)
3110 newdest = gen_rtx_REG (split_mode, REGNO (i2dest));
3113 SUBST_MODE (regno_reg_rtx[REGNO (i2dest)], split_mode);
3114 newdest = regno_reg_rtx[REGNO (i2dest)];
3118 /* If *SPLIT is a (mult FOO (const_int pow2)), convert it to
3119 an ASHIFT. This can occur if it was inside a PLUS and hence
3120 appeared to be a memory address. This is a kludge. */
3121 if (split_code == MULT
3122 && GET_CODE (XEXP (*split, 1)) == CONST_INT
3123 && INTVAL (XEXP (*split, 1)) > 0
3124 && (i = exact_log2 (INTVAL (XEXP (*split, 1)))) >= 0)
3126 SUBST (*split, gen_rtx_ASHIFT (split_mode,
3127 XEXP (*split, 0), GEN_INT (i)));
3128 /* Update split_code because we may not have a multiply
3130 split_code = GET_CODE (*split);
3133 #ifdef INSN_SCHEDULING
3134 /* If *SPLIT is a paradoxical SUBREG, when we split it, it should
3135 be written as a ZERO_EXTEND. */
3136 if (split_code == SUBREG && MEM_P (SUBREG_REG (*split)))
3138 #ifdef LOAD_EXTEND_OP
3139 /* Or as a SIGN_EXTEND if LOAD_EXTEND_OP says that that's
3140 what it really is. */
3141 if (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (*split)))
3143 SUBST (*split, gen_rtx_SIGN_EXTEND (split_mode,
3144 SUBREG_REG (*split)));
3147 SUBST (*split, gen_rtx_ZERO_EXTEND (split_mode,
3148 SUBREG_REG (*split)));
3152 /* Attempt to split binary operators using arithmetic identities. */
3153 if (BINARY_P (SET_SRC (newpat))
3154 && split_mode == GET_MODE (SET_SRC (newpat))
3155 && ! side_effects_p (SET_SRC (newpat)))
3157 rtx setsrc = SET_SRC (newpat);
3158 enum machine_mode mode = GET_MODE (setsrc);
3159 enum rtx_code code = GET_CODE (setsrc);
3160 rtx src_op0 = XEXP (setsrc, 0);
3161 rtx src_op1 = XEXP (setsrc, 1);
3163 /* Split "X = Y op Y" as "Z = Y; X = Z op Z". */
3164 if (rtx_equal_p (src_op0, src_op1))
3166 newi2pat = gen_rtx_SET (VOIDmode, newdest, src_op0);
3167 SUBST (XEXP (setsrc, 0), newdest);
3168 SUBST (XEXP (setsrc, 1), newdest);
3171 /* Split "((P op Q) op R) op S" where op is PLUS or MULT. */
3172 else if ((code == PLUS || code == MULT)
3173 && GET_CODE (src_op0) == code
3174 && GET_CODE (XEXP (src_op0, 0)) == code
3175 && (INTEGRAL_MODE_P (mode)
3176 || (FLOAT_MODE_P (mode)
3177 && flag_unsafe_math_optimizations)))
3179 rtx p = XEXP (XEXP (src_op0, 0), 0);
3180 rtx q = XEXP (XEXP (src_op0, 0), 1);
3181 rtx r = XEXP (src_op0, 1);
3184 /* Split both "((X op Y) op X) op Y" and
3185 "((X op Y) op Y) op X" as "T op T" where T is
3187 if ((rtx_equal_p (p,r) && rtx_equal_p (q,s))
3188 || (rtx_equal_p (p,s) && rtx_equal_p (q,r)))
3190 newi2pat = gen_rtx_SET (VOIDmode, newdest,
3192 SUBST (XEXP (setsrc, 0), newdest);
3193 SUBST (XEXP (setsrc, 1), newdest);
3196 /* Split "((X op X) op Y) op Y)" as "T op T" where
3198 else if (rtx_equal_p (p,q) && rtx_equal_p (r,s))
3200 rtx tmp = simplify_gen_binary (code, mode, p, r);
3201 newi2pat = gen_rtx_SET (VOIDmode, newdest, tmp);
3202 SUBST (XEXP (setsrc, 0), newdest);
3203 SUBST (XEXP (setsrc, 1), newdest);
3211 newi2pat = gen_rtx_SET (VOIDmode, newdest, *split);
3212 SUBST (*split, newdest);
3215 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
3217 /* recog_for_combine might have added CLOBBERs to newi2pat.
3218 Make sure NEWPAT does not depend on the clobbered regs. */
3219 if (GET_CODE (newi2pat) == PARALLEL)
3220 for (i = XVECLEN (newi2pat, 0) - 1; i >= 0; i--)
3221 if (GET_CODE (XVECEXP (newi2pat, 0, i)) == CLOBBER)
3223 rtx reg = XEXP (XVECEXP (newi2pat, 0, i), 0);
3224 if (reg_overlap_mentioned_p (reg, newpat))
3231 /* If the split point was a MULT and we didn't have one before,
3232 don't use one now. */
3233 if (i2_code_number >= 0 && ! (split_code == MULT && ! have_mult))
3234 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
3238 /* Check for a case where we loaded from memory in a narrow mode and
3239 then sign extended it, but we need both registers. In that case,
3240 we have a PARALLEL with both loads from the same memory location.
3241 We can split this into a load from memory followed by a register-register
3242 copy. This saves at least one insn, more if register allocation can
3245 We cannot do this if the destination of the first assignment is a
3246 condition code register or cc0. We eliminate this case by making sure
3247 the SET_DEST and SET_SRC have the same mode.
3249 We cannot do this if the destination of the second assignment is
3250 a register that we have already assumed is zero-extended. Similarly
3251 for a SUBREG of such a register. */
3253 else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0
3254 && GET_CODE (newpat) == PARALLEL
3255 && XVECLEN (newpat, 0) == 2
3256 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
3257 && GET_CODE (SET_SRC (XVECEXP (newpat, 0, 0))) == SIGN_EXTEND
3258 && (GET_MODE (SET_DEST (XVECEXP (newpat, 0, 0)))
3259 == GET_MODE (SET_SRC (XVECEXP (newpat, 0, 0))))
3260 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
3261 && rtx_equal_p (SET_SRC (XVECEXP (newpat, 0, 1)),
3262 XEXP (SET_SRC (XVECEXP (newpat, 0, 0)), 0))
3263 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)),
3265 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
3266 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
3267 && ! (temp = SET_DEST (XVECEXP (newpat, 0, 1)),
3269 && VEC_index (reg_stat_type, reg_stat,
3270 REGNO (temp))->nonzero_bits != 0
3271 && GET_MODE_BITSIZE (GET_MODE (temp)) < BITS_PER_WORD
3272 && GET_MODE_BITSIZE (GET_MODE (temp)) < HOST_BITS_PER_INT
3273 && (VEC_index (reg_stat_type, reg_stat,
3274 REGNO (temp))->nonzero_bits
3275 != GET_MODE_MASK (word_mode))))
3276 && ! (GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) == SUBREG
3277 && (temp = SUBREG_REG (SET_DEST (XVECEXP (newpat, 0, 1))),
3279 && VEC_index (reg_stat_type, reg_stat,
3280 REGNO (temp))->nonzero_bits != 0
3281 && GET_MODE_BITSIZE (GET_MODE (temp)) < BITS_PER_WORD
3282 && GET_MODE_BITSIZE (GET_MODE (temp)) < HOST_BITS_PER_INT
3283 && (VEC_index (reg_stat_type, reg_stat,
3284 REGNO (temp))->nonzero_bits
3285 != GET_MODE_MASK (word_mode)))))
3286 && ! reg_overlap_mentioned_p (SET_DEST (XVECEXP (newpat, 0, 1)),
3287 SET_SRC (XVECEXP (newpat, 0, 1)))
3288 && ! find_reg_note (i3, REG_UNUSED,
3289 SET_DEST (XVECEXP (newpat, 0, 0))))
3293 newi2pat = XVECEXP (newpat, 0, 0);
3294 ni2dest = SET_DEST (XVECEXP (newpat, 0, 0));
3295 newpat = XVECEXP (newpat, 0, 1);
3296 SUBST (SET_SRC (newpat),
3297 gen_lowpart (GET_MODE (SET_SRC (newpat)), ni2dest));
3298 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
3300 if (i2_code_number >= 0)
3301 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
3303 if (insn_code_number >= 0)
3307 /* Similarly, check for a case where we have a PARALLEL of two independent
3308 SETs but we started with three insns. In this case, we can do the sets
3309 as two separate insns. This case occurs when some SET allows two
3310 other insns to combine, but the destination of that SET is still live. */
3312 else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0
3313 && GET_CODE (newpat) == PARALLEL
3314 && XVECLEN (newpat, 0) == 2
3315 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
3316 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != ZERO_EXTRACT
3317 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != STRICT_LOW_PART
3318 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
3319 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
3320 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
3321 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)),
3323 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 1)),
3324 XVECEXP (newpat, 0, 0))
3325 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 0)),
3326 XVECEXP (newpat, 0, 1))
3327 && ! (contains_muldiv (SET_SRC (XVECEXP (newpat, 0, 0)))
3328 && contains_muldiv (SET_SRC (XVECEXP (newpat, 0, 1))))
3330 /* We cannot split the parallel into two sets if both sets
3332 && ! (reg_referenced_p (cc0_rtx, XVECEXP (newpat, 0, 0))
3333 && reg_referenced_p (cc0_rtx, XVECEXP (newpat, 0, 1)))
3337 /* Normally, it doesn't matter which of the two is done first,
3338 but it does if one references cc0. In that case, it has to
3341 if (reg_referenced_p (cc0_rtx, XVECEXP (newpat, 0, 0)))
3343 newi2pat = XVECEXP (newpat, 0, 0);
3344 newpat = XVECEXP (newpat, 0, 1);
3349 newi2pat = XVECEXP (newpat, 0, 1);
3350 newpat = XVECEXP (newpat, 0, 0);
3353 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
3355 if (i2_code_number >= 0)
3356 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
3359 /* If it still isn't recognized, fail and change things back the way they
3361 if ((insn_code_number < 0
3362 /* Is the result a reasonable ASM_OPERANDS? */
3363 && (! check_asm_operands (newpat) || added_sets_1 || added_sets_2)))
3369 /* If we had to change another insn, make sure it is valid also. */
3370 if (undobuf.other_insn)
3372 CLEAR_HARD_REG_SET (newpat_used_regs);
3374 other_pat = PATTERN (undobuf.other_insn);
3375 other_code_number = recog_for_combine (&other_pat, undobuf.other_insn,
3378 if (other_code_number < 0 && ! check_asm_operands (other_pat))
3386 /* If I2 is the CC0 setter and I3 is the CC0 user then check whether
3387 they are adjacent to each other or not. */
3389 rtx p = prev_nonnote_insn (i3);
3390 if (p && p != i2 && NONJUMP_INSN_P (p) && newi2pat
3391 && sets_cc0_p (newi2pat))
3399 /* Only allow this combination if insn_rtx_costs reports that the
3400 replacement instructions are cheaper than the originals. */
3401 if (!combine_validate_cost (i1, i2, i3, newpat, newi2pat, other_pat))
3407 /* We now know that we can do this combination. Merge the insns and
3408 update the status of registers and LOG_LINKS. */
3410 if (undobuf.other_insn)
3414 PATTERN (undobuf.other_insn) = other_pat;
3416 /* If any of the notes in OTHER_INSN were REG_UNUSED, ensure that they
3417 are still valid. Then add any non-duplicate notes added by
3418 recog_for_combine. */
3419 for (note = REG_NOTES (undobuf.other_insn); note; note = next)
3421 next = XEXP (note, 1);
3423 if (REG_NOTE_KIND (note) == REG_UNUSED
3424 && ! reg_set_p (XEXP (note, 0), PATTERN (undobuf.other_insn)))
3425 remove_note (undobuf.other_insn, note);
3428 distribute_notes (new_other_notes, undobuf.other_insn,
3429 undobuf.other_insn, NULL_RTX, NULL_RTX, NULL_RTX);
3438 /* I3 now uses what used to be its destination and which is now
3439 I2's destination. This requires us to do a few adjustments. */
3440 PATTERN (i3) = newpat;
3441 adjust_for_new_dest (i3);
3443 /* We need a LOG_LINK from I3 to I2. But we used to have one,
3446 However, some later insn might be using I2's dest and have
3447 a LOG_LINK pointing at I3. We must remove this link.
3448 The simplest way to remove the link is to point it at I1,
3449 which we know will be a NOTE. */
3451 /* newi2pat is usually a SET here; however, recog_for_combine might
3452 have added some clobbers. */
3453 if (GET_CODE (newi2pat) == PARALLEL)
3454 ni2dest = SET_DEST (XVECEXP (newi2pat, 0, 0));
3456 ni2dest = SET_DEST (newi2pat);
3458 for (insn = NEXT_INSN (i3);
3459 insn && (this_basic_block->next_bb == EXIT_BLOCK_PTR
3460 || insn != BB_HEAD (this_basic_block->next_bb));
3461 insn = NEXT_INSN (insn))
3463 if (INSN_P (insn) && reg_referenced_p (ni2dest, PATTERN (insn)))
3465 for (link = LOG_LINKS (insn); link;
3466 link = XEXP (link, 1))
3467 if (XEXP (link, 0) == i3)
3468 XEXP (link, 0) = i1;
3476 rtx i3notes, i2notes, i1notes = 0;
3477 rtx i3links, i2links, i1links = 0;
3480 /* Compute which registers we expect to eliminate. newi2pat may be setting
3481 either i3dest or i2dest, so we must check it. Also, i1dest may be the
3482 same as i3dest, in which case newi2pat may be setting i1dest. */
3483 rtx elim_i2 = ((newi2pat && reg_set_p (i2dest, newi2pat))
3484 || i2dest_in_i2src || i2dest_in_i1src
3487 rtx elim_i1 = (i1 == 0 || i1dest_in_i1src
3488 || (newi2pat && reg_set_p (i1dest, newi2pat))
3492 /* Get the old REG_NOTES and LOG_LINKS from all our insns and
3494 i3notes = REG_NOTES (i3), i3links = LOG_LINKS (i3);
3495 i2notes = REG_NOTES (i2), i2links = LOG_LINKS (i2);
3497 i1notes = REG_NOTES (i1), i1links = LOG_LINKS (i1);
3499 /* Ensure that we do not have something that should not be shared but
3500 occurs multiple times in the new insns. Check this by first
3501 resetting all the `used' flags and then copying anything is shared. */
3503 reset_used_flags (i3notes);
3504 reset_used_flags (i2notes);
3505 reset_used_flags (i1notes);
3506 reset_used_flags (newpat);
3507 reset_used_flags (newi2pat);
3508 if (undobuf.other_insn)
3509 reset_used_flags (PATTERN (undobuf.other_insn));
3511 i3notes = copy_rtx_if_shared (i3notes);
3512 i2notes = copy_rtx_if_shared (i2notes);
3513 i1notes = copy_rtx_if_shared (i1notes);
3514 newpat = copy_rtx_if_shared (newpat);
3515 newi2pat = copy_rtx_if_shared (newi2pat);
3516 if (undobuf.other_insn)
3517 reset_used_flags (PATTERN (undobuf.other_insn));
3519 INSN_CODE (i3) = insn_code_number;
3520 PATTERN (i3) = newpat;
3522 if (CALL_P (i3) && CALL_INSN_FUNCTION_USAGE (i3))
3524 rtx call_usage = CALL_INSN_FUNCTION_USAGE (i3);
3526 reset_used_flags (call_usage);
3527 call_usage = copy_rtx (call_usage);
3530 replace_rtx (call_usage, i2dest, i2src);
3533 replace_rtx (call_usage, i1dest, i1src);
3535 CALL_INSN_FUNCTION_USAGE (i3) = call_usage;
3538 if (undobuf.other_insn)
3539 INSN_CODE (undobuf.other_insn) = other_code_number;
3541 /* We had one special case above where I2 had more than one set and
3542 we replaced a destination of one of those sets with the destination
3543 of I3. In that case, we have to update LOG_LINKS of insns later
3544 in this basic block. Note that this (expensive) case is rare.
3546 Also, in this case, we must pretend that all REG_NOTEs for I2
3547 actually came from I3, so that REG_UNUSED notes from I2 will be
3548 properly handled. */
3550 if (i3_subst_into_i2)
3552 for (i = 0; i < XVECLEN (PATTERN (i2), 0); i++)
3553 if ((GET_CODE (XVECEXP (PATTERN (i2), 0, i)) == SET
3554 || GET_CODE (XVECEXP (PATTERN (i2), 0, i)) == CLOBBER)
3555 && REG_P (SET_DEST (XVECEXP (PATTERN (i2), 0, i)))
3556 && SET_DEST (XVECEXP (PATTERN (i2), 0, i)) != i2dest
3557 && ! find_reg_note (i2, REG_UNUSED,
3558 SET_DEST (XVECEXP (PATTERN (i2), 0, i))))
3559 for (temp = NEXT_INSN (i2);
3560 temp && (this_basic_block->next_bb == EXIT_BLOCK_PTR
3561 || BB_HEAD (this_basic_block) != temp);
3562 temp = NEXT_INSN (temp))
3563 if (temp != i3 && INSN_P (temp))
3564 for (link = LOG_LINKS (temp); link; link = XEXP (link, 1))
3565 if (XEXP (link, 0) == i2)
3566 XEXP (link, 0) = i3;
3571 while (XEXP (link, 1))
3572 link = XEXP (link, 1);
3573 XEXP (link, 1) = i2notes;
3587 INSN_CODE (i2) = i2_code_number;
3588 PATTERN (i2) = newi2pat;
3591 SET_INSN_DELETED (i2);
3597 SET_INSN_DELETED (i1);
3600 /* Get death notes for everything that is now used in either I3 or
3601 I2 and used to die in a previous insn. If we built two new
3602 patterns, move from I1 to I2 then I2 to I3 so that we get the
3603 proper movement on registers that I2 modifies. */
3607 move_deaths (newi2pat, NULL_RTX, DF_INSN_LUID (i1), i2, &midnotes);
3608 move_deaths (newpat, newi2pat, DF_INSN_LUID (i1), i3, &midnotes);
3611 move_deaths (newpat, NULL_RTX, i1 ? DF_INSN_LUID (i1) : DF_INSN_LUID (i2),
3614 /* Distribute all the LOG_LINKS and REG_NOTES from I1, I2, and I3. */
3616 distribute_notes (i3notes, i3, i3, newi2pat ? i2 : NULL_RTX,
3619 distribute_notes (i2notes, i2, i3, newi2pat ? i2 : NULL_RTX,
3622 distribute_notes (i1notes, i1, i3, newi2pat ? i2 : NULL_RTX,
3625 distribute_notes (midnotes, NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
3628 /* Distribute any notes added to I2 or I3 by recog_for_combine. We
3629 know these are REG_UNUSED and want them to go to the desired insn,
3630 so we always pass it as i3. */
3632 if (newi2pat && new_i2_notes)
3633 distribute_notes (new_i2_notes, i2, i2, NULL_RTX, NULL_RTX, NULL_RTX);
3636 distribute_notes (new_i3_notes, i3, i3, NULL_RTX, NULL_RTX, NULL_RTX);
3638 /* If I3DEST was used in I3SRC, it really died in I3. We may need to
3639 put a REG_DEAD note for it somewhere. If NEWI2PAT exists and sets
3640 I3DEST, the death must be somewhere before I2, not I3. If we passed I3
3641 in that case, it might delete I2. Similarly for I2 and I1.
3642 Show an additional death due to the REG_DEAD note we make here. If
3643 we discard it in distribute_notes, we will decrement it again. */
3647 if (newi2pat && reg_set_p (i3dest_killed, newi2pat))
3648 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i3dest_killed,
3650 NULL_RTX, i2, NULL_RTX, elim_i2, elim_i1);
3652 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i3dest_killed,
3654 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
3658 if (i2dest_in_i2src)
3660 if (newi2pat && reg_set_p (i2dest, newi2pat))
3661 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i2dest, NULL_RTX),
3662 NULL_RTX, i2, NULL_RTX, NULL_RTX, NULL_RTX);
3664 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i2dest, NULL_RTX),
3665 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
3666 NULL_RTX, NULL_RTX);
3669 if (i1dest_in_i1src)
3671 if (newi2pat && reg_set_p (i1dest, newi2pat))
3672 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i1dest, NULL_RTX),
3673 NULL_RTX, i2, NULL_RTX, NULL_RTX, NULL_RTX);
3675 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i1dest, NULL_RTX),
3676 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
3677 NULL_RTX, NULL_RTX);
3680 distribute_links (i3links);
3681 distribute_links (i2links);
3682 distribute_links (i1links);
3687 rtx i2_insn = 0, i2_val = 0, set;
3689 /* The insn that used to set this register doesn't exist, and
3690 this life of the register may not exist either. See if one of
3691 I3's links points to an insn that sets I2DEST. If it does,
3692 that is now the last known value for I2DEST. If we don't update
3693 this and I2 set the register to a value that depended on its old
3694 contents, we will get confused. If this insn is used, thing
3695 will be set correctly in combine_instructions. */
3697 for (link = LOG_LINKS (i3); link; link = XEXP (link, 1))
3698 if ((set = single_set (XEXP (link, 0))) != 0
3699 && rtx_equal_p (i2dest, SET_DEST (set)))
3700 i2_insn = XEXP (link, 0), i2_val = SET_SRC (set);
3702 record_value_for_reg (i2dest, i2_insn, i2_val);
3704 /* If the reg formerly set in I2 died only once and that was in I3,
3705 zero its use count so it won't make `reload' do any work. */
3707 && (newi2pat == 0 || ! reg_mentioned_p (i2dest, newi2pat))
3708 && ! i2dest_in_i2src)
3710 regno = REGNO (i2dest);
3711 INC_REG_N_SETS (regno, -1);
3715 if (i1 && REG_P (i1dest))
3718 rtx i1_insn = 0, i1_val = 0, set;
3720 for (link = LOG_LINKS (i3); link; link = XEXP (link, 1))
3721 if ((set = single_set (XEXP (link, 0))) != 0
3722 && rtx_equal_p (i1dest, SET_DEST (set)))
3723 i1_insn = XEXP (link, 0), i1_val = SET_SRC (set);
3725 record_value_for_reg (i1dest, i1_insn, i1_val);
3727 regno = REGNO (i1dest);
3728 if (! added_sets_1 && ! i1dest_in_i1src)
3729 INC_REG_N_SETS (regno, -1);
3732 /* Update reg_stat[].nonzero_bits et al for any changes that may have
3733 been made to this insn. The order of
3734 set_nonzero_bits_and_sign_copies() is important. Because newi2pat
3735 can affect nonzero_bits of newpat */
3737 note_stores (newi2pat, set_nonzero_bits_and_sign_copies, NULL);
3738 note_stores (newpat, set_nonzero_bits_and_sign_copies, NULL);
3740 /* Set new_direct_jump_p if a new return or simple jump instruction
3743 If I3 is now an unconditional jump, ensure that it has a
3744 BARRIER following it since it may have initially been a
3745 conditional jump. It may also be the last nonnote insn. */
3747 if (returnjump_p (i3) || any_uncondjump_p (i3))
3749 *new_direct_jump_p = 1;
3750 mark_jump_label (PATTERN (i3), i3, 0);
3752 if ((temp = next_nonnote_insn (i3)) == NULL_RTX
3753 || !BARRIER_P (temp))
3754 emit_barrier_after (i3);
3757 if (undobuf.other_insn != NULL_RTX
3758 && (returnjump_p (undobuf.other_insn)
3759 || any_uncondjump_p (undobuf.other_insn)))
3761 *new_direct_jump_p = 1;
3763 if ((temp = next_nonnote_insn (undobuf.other_insn)) == NULL_RTX
3764 || !BARRIER_P (temp))
3765 emit_barrier_after (undobuf.other_insn);
3768 /* An NOOP jump does not need barrier, but it does need cleaning up
3770 if (GET_CODE (newpat) == SET
3771 && SET_SRC (newpat) == pc_rtx
3772 && SET_DEST (newpat) == pc_rtx)
3773 *new_direct_jump_p = 1;
3776 if (undobuf.other_insn != NULL_RTX)
3780 fprintf (dump_file, "modifying other_insn ");
3781 dump_insn_slim (dump_file, undobuf.other_insn);
3783 df_insn_rescan (undobuf.other_insn);
3786 if (i1 && !(NOTE_P(i1) && (NOTE_KIND (i1) == NOTE_INSN_DELETED)))
3790 fprintf (dump_file, "modifying insn i1 ");
3791 dump_insn_slim (dump_file, i1);
3793 df_insn_rescan (i1);
3796 if (i2 && !(NOTE_P(i2) && (NOTE_KIND (i2) == NOTE_INSN_DELETED)))
3800 fprintf (dump_file, "modifying insn i2 ");
3801 dump_insn_slim (dump_file, i2);
3803 df_insn_rescan (i2);
3806 if (i3 && !(NOTE_P(i3) && (NOTE_KIND (i3) == NOTE_INSN_DELETED)))
3810 fprintf (dump_file, "modifying insn i3 ");
3811 dump_insn_slim (dump_file, i3);
3813 df_insn_rescan (i3);
3816 combine_successes++;
3819 if (added_links_insn
3820 && (newi2pat == 0 || DF_INSN_LUID (added_links_insn) < DF_INSN_LUID (i2))
3821 && DF_INSN_LUID (added_links_insn) < DF_INSN_LUID (i3))
3822 return added_links_insn;
3824 return newi2pat ? i2 : i3;
3827 /* Undo all the modifications recorded in undobuf. */
3832 struct undo *undo, *next;
3834 for (undo = undobuf.undos; undo; undo = next)
3840 *undo->where.r = undo->old_contents.r;
3843 *undo->where.i = undo->old_contents.i;
3846 adjust_reg_mode (*undo->where.r, undo->old_contents.m);
3852 undo->next = undobuf.frees;
3853 undobuf.frees = undo;
3859 /* We've committed to accepting the changes we made. Move all
3860 of the undos to the free list. */
3865 struct undo *undo, *next;
3867 for (undo = undobuf.undos; undo; undo = next)
3870 undo->next = undobuf.frees;
3871 undobuf.frees = undo;
3876 /* Find the innermost point within the rtx at LOC, possibly LOC itself,
3877 where we have an arithmetic expression and return that point. LOC will
3880 try_combine will call this function to see if an insn can be split into
3884 find_split_point (rtx *loc, rtx insn)
3887 enum rtx_code code = GET_CODE (x);
3889 unsigned HOST_WIDE_INT len = 0;
3890 HOST_WIDE_INT pos = 0;
3892 rtx inner = NULL_RTX;
3894 /* First special-case some codes. */
3898 #ifdef INSN_SCHEDULING
3899 /* If we are making a paradoxical SUBREG invalid, it becomes a split
3901 if (MEM_P (SUBREG_REG (x)))
3904 return find_split_point (&SUBREG_REG (x), insn);
3908 /* If we have (mem (const ..)) or (mem (symbol_ref ...)), split it
3909 using LO_SUM and HIGH. */
3910 if (GET_CODE (XEXP (x, 0)) == CONST
3911 || GET_CODE (XEXP (x, 0)) == SYMBOL_REF)
3914 gen_rtx_LO_SUM (Pmode,
3915 gen_rtx_HIGH (Pmode, XEXP (x, 0)),
3917 return &XEXP (XEXP (x, 0), 0);
3921 /* If we have a PLUS whose second operand is a constant and the
3922 address is not valid, perhaps will can split it up using
3923 the machine-specific way to split large constants. We use
3924 the first pseudo-reg (one of the virtual regs) as a placeholder;
3925 it will not remain in the result. */
3926 if (GET_CODE (XEXP (x, 0)) == PLUS
3927 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3928 && ! memory_address_p (GET_MODE (x), XEXP (x, 0)))
3930 rtx reg = regno_reg_rtx[FIRST_PSEUDO_REGISTER];
3931 rtx seq = combine_split_insns (gen_rtx_SET (VOIDmode, reg,
3935 /* This should have produced two insns, each of which sets our
3936 placeholder. If the source of the second is a valid address,
3937 we can make put both sources together and make a split point
3941 && NEXT_INSN (seq) != NULL_RTX
3942 && NEXT_INSN (NEXT_INSN (seq)) == NULL_RTX
3943 && NONJUMP_INSN_P (seq)
3944 && GET_CODE (PATTERN (seq)) == SET
3945 && SET_DEST (PATTERN (seq)) == reg
3946 && ! reg_mentioned_p (reg,
3947 SET_SRC (PATTERN (seq)))
3948 && NONJUMP_INSN_P (NEXT_INSN (seq))
3949 && GET_CODE (PATTERN (NEXT_INSN (seq))) == SET
3950 && SET_DEST (PATTERN (NEXT_INSN (seq))) == reg
3951 && memory_address_p (GET_MODE (x),
3952 SET_SRC (PATTERN (NEXT_INSN (seq)))))
3954 rtx src1 = SET_SRC (PATTERN (seq));
3955 rtx src2 = SET_SRC (PATTERN (NEXT_INSN (seq)));
3957 /* Replace the placeholder in SRC2 with SRC1. If we can
3958 find where in SRC2 it was placed, that can become our
3959 split point and we can replace this address with SRC2.
3960 Just try two obvious places. */
3962 src2 = replace_rtx (src2, reg, src1);
3964 if (XEXP (src2, 0) == src1)
3965 split = &XEXP (src2, 0);
3966 else if (GET_RTX_FORMAT (GET_CODE (XEXP (src2, 0)))[0] == 'e'
3967 && XEXP (XEXP (src2, 0), 0) == src1)
3968 split = &XEXP (XEXP (src2, 0), 0);
3972 SUBST (XEXP (x, 0), src2);
3977 /* If that didn't work, perhaps the first operand is complex and
3978 needs to be computed separately, so make a split point there.
3979 This will occur on machines that just support REG + CONST
3980 and have a constant moved through some previous computation. */
3982 else if (!OBJECT_P (XEXP (XEXP (x, 0), 0))
3983 && ! (GET_CODE (XEXP (XEXP (x, 0), 0)) == SUBREG
3984 && OBJECT_P (SUBREG_REG (XEXP (XEXP (x, 0), 0)))))
3985 return &XEXP (XEXP (x, 0), 0);
3988 /* If we have a PLUS whose first operand is complex, try computing it
3989 separately by making a split there. */
3990 if (GET_CODE (XEXP (x, 0)) == PLUS
3991 && ! memory_address_p (GET_MODE (x), XEXP (x, 0))
3992 && ! OBJECT_P (XEXP (XEXP (x, 0), 0))
3993 && ! (GET_CODE (XEXP (XEXP (x, 0), 0)) == SUBREG
3994 && OBJECT_P (SUBREG_REG (XEXP (XEXP (x, 0), 0)))))
3995 return &XEXP (XEXP (x, 0), 0);
4000 /* If SET_DEST is CC0 and SET_SRC is not an operand, a COMPARE, or a
4001 ZERO_EXTRACT, the most likely reason why this doesn't match is that
4002 we need to put the operand into a register. So split at that
4005 if (SET_DEST (x) == cc0_rtx
4006 && GET_CODE (SET_SRC (x)) != COMPARE
4007 && GET_CODE (SET_SRC (x)) != ZERO_EXTRACT
4008 && !OBJECT_P (SET_SRC (x))
4009 && ! (GET_CODE (SET_SRC (x)) == SUBREG
4010 && OBJECT_P (SUBREG_REG (SET_SRC (x)))))
4011 return &SET_SRC (x);
4014 /* See if we can split SET_SRC as it stands. */
4015 split = find_split_point (&SET_SRC (x), insn);
4016 if (split && split != &SET_SRC (x))
4019 /* See if we can split SET_DEST as it stands. */
4020 split = find_split_point (&SET_DEST (x), insn);
4021 if (split && split != &SET_DEST (x))
4024 /* See if this is a bitfield assignment with everything constant. If
4025 so, this is an IOR of an AND, so split it into that. */
4026 if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
4027 && (GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0)))
4028 <= HOST_BITS_PER_WIDE_INT)
4029 && GET_CODE (XEXP (SET_DEST (x), 1)) == CONST_INT
4030 && GET_CODE (XEXP (SET_DEST (x), 2)) == CONST_INT
4031 && GET_CODE (SET_SRC (x)) == CONST_INT
4032 && ((INTVAL (XEXP (SET_DEST (x), 1))
4033 + INTVAL (XEXP (SET_DEST (x), 2)))
4034 <= GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0))))
4035 && ! side_effects_p (XEXP (SET_DEST (x), 0)))
4037 HOST_WIDE_INT pos = INTVAL (XEXP (SET_DEST (x), 2));
4038 unsigned HOST_WIDE_INT len = INTVAL (XEXP (SET_DEST (x), 1));
4039 unsigned HOST_WIDE_INT src = INTVAL (SET_SRC (x));
4040 rtx dest = XEXP (SET_DEST (x), 0);
4041 enum machine_mode mode = GET_MODE (dest);
4042 unsigned HOST_WIDE_INT mask = ((HOST_WIDE_INT) 1 << len) - 1;
4045 if (BITS_BIG_ENDIAN)
4046 pos = GET_MODE_BITSIZE (mode) - len - pos;
4048 or_mask = gen_int_mode (src << pos, mode);
4051 simplify_gen_binary (IOR, mode, dest, or_mask));
4054 rtx negmask = gen_int_mode (~(mask << pos), mode);
4056 simplify_gen_binary (IOR, mode,
4057 simplify_gen_binary (AND, mode,
4062 SUBST (SET_DEST (x), dest);
4064 split = find_split_point (&SET_SRC (x), insn);
4065 if (split && split != &SET_SRC (x))
4069 /* Otherwise, see if this is an operation that we can split into two.
4070 If so, try to split that. */
4071 code = GET_CODE (SET_SRC (x));
4076 /* If we are AND'ing with a large constant that is only a single
4077 bit and the result is only being used in a context where we
4078 need to know if it is zero or nonzero, replace it with a bit
4079 extraction. This will avoid the large constant, which might
4080 have taken more than one insn to make. If the constant were
4081 not a valid argument to the AND but took only one insn to make,
4082 this is no worse, but if it took more than one insn, it will
4085 if (GET_CODE (XEXP (SET_SRC (x), 1)) == CONST_INT
4086 && REG_P (XEXP (SET_SRC (x), 0))
4087 && (pos = exact_log2 (INTVAL (XEXP (SET_SRC (x), 1)))) >= 7
4088 && REG_P (SET_DEST (x))
4089 && (split = find_single_use (SET_DEST (x), insn, (rtx*) 0)) != 0
4090 && (GET_CODE (*split) == EQ || GET_CODE (*split) == NE)
4091 && XEXP (*split, 0) == SET_DEST (x)
4092 && XEXP (*split, 1) == const0_rtx)
4094 rtx extraction = make_extraction (GET_MODE (SET_DEST (x)),
4095 XEXP (SET_SRC (x), 0),
4096 pos, NULL_RTX, 1, 1, 0, 0);
4097 if (extraction != 0)
4099 SUBST (SET_SRC (x), extraction);
4100 return find_split_point (loc, insn);
4106 /* If STORE_FLAG_VALUE is -1, this is (NE X 0) and only one bit of X
4107 is known to be on, this can be converted into a NEG of a shift. */
4108 if (STORE_FLAG_VALUE == -1 && XEXP (SET_SRC (x), 1) == const0_rtx
4109 && GET_MODE (SET_SRC (x)) == GET_MODE (XEXP (SET_SRC (x), 0))
4110 && 1 <= (pos = exact_log2
4111 (nonzero_bits (XEXP (SET_SRC (x), 0),
4112 GET_MODE (XEXP (SET_SRC (x), 0))))))
4114 enum machine_mode mode = GET_MODE (XEXP (SET_SRC (x), 0));
4118 gen_rtx_LSHIFTRT (mode,
4119 XEXP (SET_SRC (x), 0),
4122 split = find_split_point (&SET_SRC (x), insn);
4123 if (split && split != &SET_SRC (x))
4129 inner = XEXP (SET_SRC (x), 0);
4131 /* We can't optimize if either mode is a partial integer
4132 mode as we don't know how many bits are significant
4134 if (GET_MODE_CLASS (GET_MODE (inner)) == MODE_PARTIAL_INT
4135 || GET_MODE_CLASS (GET_MODE (SET_SRC (x))) == MODE_PARTIAL_INT)
4139 len = GET_MODE_BITSIZE (GET_MODE (inner));
4145 if (GET_CODE (XEXP (SET_SRC (x), 1)) == CONST_INT
4146 && GET_CODE (XEXP (SET_SRC (x), 2)) == CONST_INT)
4148 inner = XEXP (SET_SRC (x), 0);
4149 len = INTVAL (XEXP (SET_SRC (x), 1));
4150 pos = INTVAL (XEXP (SET_SRC (x), 2));
4152 if (BITS_BIG_ENDIAN)
4153 pos = GET_MODE_BITSIZE (GET_MODE (inner)) - len - pos;
4154 unsignedp = (code == ZERO_EXTRACT);
4162 if (len && pos >= 0 && pos + len <= GET_MODE_BITSIZE (GET_MODE (inner)))
4164 enum machine_mode mode = GET_MODE (SET_SRC (x));
4166 /* For unsigned, we have a choice of a shift followed by an
4167 AND or two shifts. Use two shifts for field sizes where the
4168 constant might be too large. We assume here that we can
4169 always at least get 8-bit constants in an AND insn, which is
4170 true for every current RISC. */
4172 if (unsignedp && len <= 8)
4177 (mode, gen_lowpart (mode, inner),
4179 GEN_INT (((HOST_WIDE_INT) 1 << len) - 1)));
4181 split = find_split_point (&SET_SRC (x), insn);
4182 if (split && split != &SET_SRC (x))
4189 (unsignedp ? LSHIFTRT : ASHIFTRT, mode,
4190 gen_rtx_ASHIFT (mode,
4191 gen_lowpart (mode, inner),
4192 GEN_INT (GET_MODE_BITSIZE (mode)
4194 GEN_INT (GET_MODE_BITSIZE (mode) - len)));
4196 split = find_split_point (&SET_SRC (x), insn);
4197 if (split && split != &SET_SRC (x))
4202 /* See if this is a simple operation with a constant as the second
4203 operand. It might be that this constant is out of range and hence
4204 could be used as a split point. */
4205 if (BINARY_P (SET_SRC (x))
4206 && CONSTANT_P (XEXP (SET_SRC (x), 1))
4207 && (OBJECT_P (XEXP (SET_SRC (x), 0))
4208 || (GET_CODE (XEXP (SET_SRC (x), 0)) == SUBREG
4209 && OBJECT_P (SUBREG_REG (XEXP (SET_SRC (x), 0))))))
4210 return &XEXP (SET_SRC (x), 1);
4212 /* Finally, see if this is a simple operation with its first operand
4213 not in a register. The operation might require this operand in a
4214 register, so return it as a split point. We can always do this
4215 because if the first operand were another operation, we would have
4216 already found it as a split point. */
4217 if ((BINARY_P (SET_SRC (x)) || UNARY_P (SET_SRC (x)))
4218 && ! register_operand (XEXP (SET_SRC (x), 0), VOIDmode))
4219 return &XEXP (SET_SRC (x), 0);
4225 /* We write NOR as (and (not A) (not B)), but if we don't have a NOR,
4226 it is better to write this as (not (ior A B)) so we can split it.
4227 Similarly for IOR. */
4228 if (GET_CODE (XEXP (x, 0)) == NOT && GET_CODE (XEXP (x, 1)) == NOT)
4231 gen_rtx_NOT (GET_MODE (x),
4232 gen_rtx_fmt_ee (code == IOR ? AND : IOR,
4234 XEXP (XEXP (x, 0), 0),
4235 XEXP (XEXP (x, 1), 0))));
4236 return find_split_point (loc, insn);
4239 /* Many RISC machines have a large set of logical insns. If the
4240 second operand is a NOT, put it first so we will try to split the
4241 other operand first. */
4242 if (GET_CODE (XEXP (x, 1)) == NOT)
4244 rtx tem = XEXP (x, 0);
4245 SUBST (XEXP (x, 0), XEXP (x, 1));
4246 SUBST (XEXP (x, 1), tem);
4254 /* Otherwise, select our actions depending on our rtx class. */
4255 switch (GET_RTX_CLASS (code))
4257 case RTX_BITFIELD_OPS: /* This is ZERO_EXTRACT and SIGN_EXTRACT. */
4259 split = find_split_point (&XEXP (x, 2), insn);
4262 /* ... fall through ... */
4264 case RTX_COMM_ARITH:
4266 case RTX_COMM_COMPARE:
4267 split = find_split_point (&XEXP (x, 1), insn);
4270 /* ... fall through ... */
4272 /* Some machines have (and (shift ...) ...) insns. If X is not
4273 an AND, but XEXP (X, 0) is, use it as our split point. */
4274 if (GET_CODE (x) != AND && GET_CODE (XEXP (x, 0)) == AND)
4275 return &XEXP (x, 0);
4277 split = find_split_point (&XEXP (x, 0), insn);
4283 /* Otherwise, we don't have a split point. */
4288 /* Throughout X, replace FROM with TO, and return the result.
4289 The result is TO if X is FROM;
4290 otherwise the result is X, but its contents may have been modified.
4291 If they were modified, a record was made in undobuf so that
4292 undo_all will (among other things) return X to its original state.
4294 If the number of changes necessary is too much to record to undo,
4295 the excess changes are not made, so the result is invalid.
4296 The changes already made can still be undone.
4297 undobuf.num_undo is incremented for such changes, so by testing that
4298 the caller can tell whether the result is valid.
4300 `n_occurrences' is incremented each time FROM is replaced.
4302 IN_DEST is nonzero if we are processing the SET_DEST of a SET.
4304 UNIQUE_COPY is nonzero if each substitution must be unique. We do this
4305 by copying if `n_occurrences' is nonzero. */
4308 subst (rtx x, rtx from, rtx to, int in_dest, int unique_copy)
4310 enum rtx_code code = GET_CODE (x);
4311 enum machine_mode op0_mode = VOIDmode;
4316 /* Two expressions are equal if they are identical copies of a shared
4317 RTX or if they are both registers with the same register number
4320 #define COMBINE_RTX_EQUAL_P(X,Y) \
4322 || (REG_P (X) && REG_P (Y) \
4323 && REGNO (X) == REGNO (Y) && GET_MODE (X) == GET_MODE (Y)))
4325 if (! in_dest && COMBINE_RTX_EQUAL_P (x, from))
4328 return (unique_copy && n_occurrences > 1 ? copy_rtx (to) : to);
4331 /* If X and FROM are the same register but different modes, they
4332 will not have been seen as equal above. However, the log links code
4333 will make a LOG_LINKS entry for that case. If we do nothing, we
4334 will try to rerecognize our original insn and, when it succeeds,
4335 we will delete the feeding insn, which is incorrect.
4337 So force this insn not to match in this (rare) case. */
4338 if (! in_dest && code == REG && REG_P (from)
4339 && reg_overlap_mentioned_p (x, from))
4340 return gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
4342 /* If this is an object, we are done unless it is a MEM or LO_SUM, both
4343 of which may contain things that can be combined. */
4344 if (code != MEM && code != LO_SUM && OBJECT_P (x))
4347 /* It is possible to have a subexpression appear twice in the insn.
4348 Suppose that FROM is a register that appears within TO.
4349 Then, after that subexpression has been scanned once by `subst',
4350 the second time it is scanned, TO may be found. If we were
4351 to scan TO here, we would find FROM within it and create a
4352 self-referent rtl structure which is completely wrong. */
4353 if (COMBINE_RTX_EQUAL_P (x, to))
4356 /* Parallel asm_operands need special attention because all of the
4357 inputs are shared across the arms. Furthermore, unsharing the
4358 rtl results in recognition failures. Failure to handle this case
4359 specially can result in circular rtl.
4361 Solve this by doing a normal pass across the first entry of the
4362 parallel, and only processing the SET_DESTs of the subsequent
4365 if (code == PARALLEL
4366 && GET_CODE (XVECEXP (x, 0, 0)) == SET
4367 && GET_CODE (SET_SRC (XVECEXP (x, 0, 0))) == ASM_OPERANDS)
4369 new = subst (XVECEXP (x, 0, 0), from, to, 0, unique_copy);
4371 /* If this substitution failed, this whole thing fails. */
4372 if (GET_CODE (new) == CLOBBER
4373 && XEXP (new, 0) == const0_rtx)
4376 SUBST (XVECEXP (x, 0, 0), new);
4378 for (i = XVECLEN (x, 0) - 1; i >= 1; i--)
4380 rtx dest = SET_DEST (XVECEXP (x, 0, i));
4383 && GET_CODE (dest) != CC0
4384 && GET_CODE (dest) != PC)
4386 new = subst (dest, from, to, 0, unique_copy);
4388 /* If this substitution failed, this whole thing fails. */
4389 if (GET_CODE (new) == CLOBBER
4390 && XEXP (new, 0) == const0_rtx)
4393 SUBST (SET_DEST (XVECEXP (x, 0, i)), new);
4399 len = GET_RTX_LENGTH (code);
4400 fmt = GET_RTX_FORMAT (code);
4402 /* We don't need to process a SET_DEST that is a register, CC0,
4403 or PC, so set up to skip this common case. All other cases
4404 where we want to suppress replacing something inside a
4405 SET_SRC are handled via the IN_DEST operand. */
4407 && (REG_P (SET_DEST (x))
4408 || GET_CODE (SET_DEST (x)) == CC0
4409 || GET_CODE (SET_DEST (x)) == PC))
4412 /* Get the mode of operand 0 in case X is now a SIGN_EXTEND of a
4415 op0_mode = GET_MODE (XEXP (x, 0));
4417 for (i = 0; i < len; i++)
4422 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
4424 if (COMBINE_RTX_EQUAL_P (XVECEXP (x, i, j), from))
4426 new = (unique_copy && n_occurrences
4427 ? copy_rtx (to) : to);
4432 new = subst (XVECEXP (x, i, j), from, to, 0,
4435 /* If this substitution failed, this whole thing
4437 if (GET_CODE (new) == CLOBBER
4438 && XEXP (new, 0) == const0_rtx)
4442 SUBST (XVECEXP (x, i, j), new);
4445 else if (fmt[i] == 'e')
4447 /* If this is a register being set, ignore it. */
4451 && (((code == SUBREG || code == ZERO_EXTRACT)
4453 || code == STRICT_LOW_PART))
4456 else if (COMBINE_RTX_EQUAL_P (XEXP (x, i), from))
4458 /* In general, don't install a subreg involving two
4459 modes not tieable. It can worsen register
4460 allocation, and can even make invalid reload
4461 insns, since the reg inside may need to be copied
4462 from in the outside mode, and that may be invalid
4463 if it is an fp reg copied in integer mode.
4465 We allow two exceptions to this: It is valid if
4466 it is inside another SUBREG and the mode of that
4467 SUBREG and the mode of the inside of TO is
4468 tieable and it is valid if X is a SET that copies
4471 if (GET_CODE (to) == SUBREG
4472 && ! MODES_TIEABLE_P (GET_MODE (to),
4473 GET_MODE (SUBREG_REG (to)))
4474 && ! (code == SUBREG
4475 && MODES_TIEABLE_P (GET_MODE (x),
4476 GET_MODE (SUBREG_REG (to))))
4478 && ! (code == SET && i == 1 && XEXP (x, 0) == cc0_rtx)
4481 return gen_rtx_CLOBBER (VOIDmode, const0_rtx);
4483 #ifdef CANNOT_CHANGE_MODE_CLASS
4486 && REGNO (to) < FIRST_PSEUDO_REGISTER
4487 && REG_CANNOT_CHANGE_MODE_P (REGNO (to),
4490 return gen_rtx_CLOBBER (VOIDmode, const0_rtx);
4493 new = (unique_copy && n_occurrences ? copy_rtx (to) : to);
4497 /* If we are in a SET_DEST, suppress most cases unless we
4498 have gone inside a MEM, in which case we want to
4499 simplify the address. We assume here that things that
4500 are actually part of the destination have their inner
4501 parts in the first expression. This is true for SUBREG,
4502 STRICT_LOW_PART, and ZERO_EXTRACT, which are the only
4503 things aside from REG and MEM that should appear in a
4505 new = subst (XEXP (x, i), from, to,
4507 && (code == SUBREG || code == STRICT_LOW_PART
4508 || code == ZERO_EXTRACT))
4510 && i == 0), unique_copy);
4512 /* If we found that we will have to reject this combination,
4513 indicate that by returning the CLOBBER ourselves, rather than
4514 an expression containing it. This will speed things up as
4515 well as prevent accidents where two CLOBBERs are considered
4516 to be equal, thus producing an incorrect simplification. */
4518 if (GET_CODE (new) == CLOBBER && XEXP (new, 0) == const0_rtx)
4521 if (GET_CODE (x) == SUBREG
4522 && (GET_CODE (new) == CONST_INT
4523 || GET_CODE (new) == CONST_DOUBLE))
4525 enum machine_mode mode = GET_MODE (x);
4527 x = simplify_subreg (GET_MODE (x), new,
4528 GET_MODE (SUBREG_REG (x)),
4531 x = gen_rtx_CLOBBER (mode, const0_rtx);
4533 else if (GET_CODE (new) == CONST_INT
4534 && GET_CODE (x) == ZERO_EXTEND)
4536 x = simplify_unary_operation (ZERO_EXTEND, GET_MODE (x),
4537 new, GET_MODE (XEXP (x, 0)));
4541 SUBST (XEXP (x, i), new);
4546 /* Check if we are loading something from the constant pool via float
4547 extension; in this case we would undo compress_float_constant
4548 optimization and degenerate constant load to an immediate value. */
4549 if (GET_CODE (x) == FLOAT_EXTEND
4550 && MEM_P (XEXP (x, 0))
4551 && MEM_READONLY_P (XEXP (x, 0)))
4553 rtx tmp = avoid_constant_pool_reference (x);
4558 /* Try to simplify X. If the simplification changed the code, it is likely
4559 that further simplification will help, so loop, but limit the number
4560 of repetitions that will be performed. */
4562 for (i = 0; i < 4; i++)
4564 /* If X is sufficiently simple, don't bother trying to do anything
4566 if (code != CONST_INT && code != REG && code != CLOBBER)
4567 x = combine_simplify_rtx (x, op0_mode, in_dest);
4569 if (GET_CODE (x) == code)
4572 code = GET_CODE (x);
4574 /* We no longer know the original mode of operand 0 since we
4575 have changed the form of X) */
4576 op0_mode = VOIDmode;
4582 /* Simplify X, a piece of RTL. We just operate on the expression at the
4583 outer level; call `subst' to simplify recursively. Return the new
4586 OP0_MODE is the original mode of XEXP (x, 0). IN_DEST is nonzero
4587 if we are inside a SET_DEST. */
4590 combine_simplify_rtx (rtx x, enum machine_mode op0_mode, int in_dest)
4592 enum rtx_code code = GET_CODE (x);
4593 enum machine_mode mode = GET_MODE (x);
4597 /* If this is a commutative operation, put a constant last and a complex
4598 expression first. We don't need to do this for comparisons here. */
4599 if (COMMUTATIVE_ARITH_P (x)
4600 && swap_commutative_operands_p (XEXP (x, 0), XEXP (x, 1)))
4603 SUBST (XEXP (x, 0), XEXP (x, 1));
4604 SUBST (XEXP (x, 1), temp);
4607 /* If this is a simple operation applied to an IF_THEN_ELSE, try
4608 applying it to the arms of the IF_THEN_ELSE. This often simplifies
4609 things. Check for cases where both arms are testing the same
4612 Don't do anything if all operands are very simple. */
4615 && ((!OBJECT_P (XEXP (x, 0))
4616 && ! (GET_CODE (XEXP (x, 0)) == SUBREG
4617 && OBJECT_P (SUBREG_REG (XEXP (x, 0)))))
4618 || (!OBJECT_P (XEXP (x, 1))
4619 && ! (GET_CODE (XEXP (x, 1)) == SUBREG
4620 && OBJECT_P (SUBREG_REG (XEXP (x, 1)))))))
4622 && (!OBJECT_P (XEXP (x, 0))
4623 && ! (GET_CODE (XEXP (x, 0)) == SUBREG
4624 && OBJECT_P (SUBREG_REG (XEXP (x, 0)))))))
4626 rtx cond, true_rtx, false_rtx;
4628 cond = if_then_else_cond (x, &true_rtx, &false_rtx);
4630 /* If everything is a comparison, what we have is highly unlikely
4631 to be simpler, so don't use it. */
4632 && ! (COMPARISON_P (x)
4633 && (COMPARISON_P (true_rtx) || COMPARISON_P (false_rtx))))
4635 rtx cop1 = const0_rtx;
4636 enum rtx_code cond_code = simplify_comparison (NE, &cond, &cop1);
4638 if (cond_code == NE && COMPARISON_P (cond))
4641 /* Simplify the alternative arms; this may collapse the true and
4642 false arms to store-flag values. Be careful to use copy_rtx
4643 here since true_rtx or false_rtx might share RTL with x as a
4644 result of the if_then_else_cond call above. */
4645 true_rtx = subst (copy_rtx (true_rtx), pc_rtx, pc_rtx, 0, 0);
4646 false_rtx = subst (copy_rtx (false_rtx), pc_rtx, pc_rtx, 0, 0);
4648 /* If true_rtx and false_rtx are not general_operands, an if_then_else
4649 is unlikely to be simpler. */
4650 if (general_operand (true_rtx, VOIDmode)
4651 && general_operand (false_rtx, VOIDmode))
4653 enum rtx_code reversed;
4655 /* Restarting if we generate a store-flag expression will cause
4656 us to loop. Just drop through in this case. */
4658 /* If the result values are STORE_FLAG_VALUE and zero, we can
4659 just make the comparison operation. */
4660 if (true_rtx == const_true_rtx && false_rtx == const0_rtx)
4661 x = simplify_gen_relational (cond_code, mode, VOIDmode,
4663 else if (true_rtx == const0_rtx && false_rtx == const_true_rtx
4664 && ((reversed = reversed_comparison_code_parts
4665 (cond_code, cond, cop1, NULL))
4667 x = simplify_gen_relational (reversed, mode, VOIDmode,
4670 /* Likewise, we can make the negate of a comparison operation
4671 if the result values are - STORE_FLAG_VALUE and zero. */
4672 else if (GET_CODE (true_rtx) == CONST_INT
4673 && INTVAL (true_rtx) == - STORE_FLAG_VALUE
4674 && false_rtx == const0_rtx)
4675 x = simplify_gen_unary (NEG, mode,
4676 simplify_gen_relational (cond_code,
4680 else if (GET_CODE (false_rtx) == CONST_INT
4681 && INTVAL (false_rtx) == - STORE_FLAG_VALUE
4682 && true_rtx == const0_rtx
4683 && ((reversed = reversed_comparison_code_parts
4684 (cond_code, cond, cop1, NULL))
4686 x = simplify_gen_unary (NEG, mode,
4687 simplify_gen_relational (reversed,
4692 return gen_rtx_IF_THEN_ELSE (mode,
4693 simplify_gen_relational (cond_code,
4698 true_rtx, false_rtx);
4700 code = GET_CODE (x);
4701 op0_mode = VOIDmode;
4706 /* Try to fold this expression in case we have constants that weren't
4709 switch (GET_RTX_CLASS (code))
4712 if (op0_mode == VOIDmode)
4713 op0_mode = GET_MODE (XEXP (x, 0));
4714 temp = simplify_unary_operation (code, mode, XEXP (x, 0), op0_mode);
4717 case RTX_COMM_COMPARE:
4719 enum machine_mode cmp_mode = GET_MODE (XEXP (x, 0));
4720 if (cmp_mode == VOIDmode)
4722 cmp_mode = GET_MODE (XEXP (x, 1));
4723 if (cmp_mode == VOIDmode)
4724 cmp_mode = op0_mode;
4726 temp = simplify_relational_operation (code, mode, cmp_mode,
4727 XEXP (x, 0), XEXP (x, 1));
4730 case RTX_COMM_ARITH:
4732 temp = simplify_binary_operation (code, mode, XEXP (x, 0), XEXP (x, 1));
4734 case RTX_BITFIELD_OPS:
4736 temp = simplify_ternary_operation (code, mode, op0_mode, XEXP (x, 0),
4737 XEXP (x, 1), XEXP (x, 2));
4746 code = GET_CODE (temp);
4747 op0_mode = VOIDmode;
4748 mode = GET_MODE (temp);
4751 /* First see if we can apply the inverse distributive law. */
4752 if (code == PLUS || code == MINUS
4753 || code == AND || code == IOR || code == XOR)
4755 x = apply_distributive_law (x);
4756 code = GET_CODE (x);
4757 op0_mode = VOIDmode;
4760 /* If CODE is an associative operation not otherwise handled, see if we
4761 can associate some operands. This can win if they are constants or
4762 if they are logically related (i.e. (a & b) & a). */
4763 if ((code == PLUS || code == MINUS || code == MULT || code == DIV
4764 || code == AND || code == IOR || code == XOR
4765 || code == SMAX || code == SMIN || code == UMAX || code == UMIN)
4766 && ((INTEGRAL_MODE_P (mode) && code != DIV)
4767 || (flag_associative_math && FLOAT_MODE_P (mode))))
4769 if (GET_CODE (XEXP (x, 0)) == code)
4771 rtx other = XEXP (XEXP (x, 0), 0);
4772 rtx inner_op0 = XEXP (XEXP (x, 0), 1);
4773 rtx inner_op1 = XEXP (x, 1);
4776 /* Make sure we pass the constant operand if any as the second
4777 one if this is a commutative operation. */
4778 if (CONSTANT_P (inner_op0) && COMMUTATIVE_ARITH_P (x))
4780 rtx tem = inner_op0;
4781 inner_op0 = inner_op1;
4784 inner = simplify_binary_operation (code == MINUS ? PLUS
4785 : code == DIV ? MULT
4787 mode, inner_op0, inner_op1);
4789 /* For commutative operations, try the other pair if that one
4791 if (inner == 0 && COMMUTATIVE_ARITH_P (x))
4793 other = XEXP (XEXP (x, 0), 1);
4794 inner = simplify_binary_operation (code, mode,
4795 XEXP (XEXP (x, 0), 0),
4800 return simplify_gen_binary (code, mode, other, inner);
4804 /* A little bit of algebraic simplification here. */
4808 /* Ensure that our address has any ASHIFTs converted to MULT in case
4809 address-recognizing predicates are called later. */
4810 temp = make_compound_operation (XEXP (x, 0), MEM);
4811 SUBST (XEXP (x, 0), temp);
4815 if (op0_mode == VOIDmode)
4816 op0_mode = GET_MODE (SUBREG_REG (x));
4818 /* See if this can be moved to simplify_subreg. */
4819 if (CONSTANT_P (SUBREG_REG (x))
4820 && subreg_lowpart_offset (mode, op0_mode) == SUBREG_BYTE (x)
4821 /* Don't call gen_lowpart if the inner mode
4822 is VOIDmode and we cannot simplify it, as SUBREG without
4823 inner mode is invalid. */
4824 && (GET_MODE (SUBREG_REG (x)) != VOIDmode
4825 || gen_lowpart_common (mode, SUBREG_REG (x))))
4826 return gen_lowpart (mode, SUBREG_REG (x));
4828 if (GET_MODE_CLASS (GET_MODE (SUBREG_REG (x))) == MODE_CC)
4832 temp = simplify_subreg (mode, SUBREG_REG (x), op0_mode,
4838 /* Don't change the mode of the MEM if that would change the meaning
4840 if (MEM_P (SUBREG_REG (x))
4841 && (MEM_VOLATILE_P (SUBREG_REG (x))
4842 || mode_dependent_address_p (XEXP (SUBREG_REG (x), 0))))
4843 return gen_rtx_CLOBBER (mode, const0_rtx);
4845 /* Note that we cannot do any narrowing for non-constants since
4846 we might have been counting on using the fact that some bits were
4847 zero. We now do this in the SET. */
4852 temp = expand_compound_operation (XEXP (x, 0));
4854 /* For C equal to the width of MODE minus 1, (neg (ashiftrt X C)) can be
4855 replaced by (lshiftrt X C). This will convert
4856 (neg (sign_extract X 1 Y)) to (zero_extract X 1 Y). */
4858 if (GET_CODE (temp) == ASHIFTRT
4859 && GET_CODE (XEXP (temp, 1)) == CONST_INT
4860 && INTVAL (XEXP (temp, 1)) == GET_MODE_BITSIZE (mode) - 1)
4861 return simplify_shift_const (NULL_RTX, LSHIFTRT, mode, XEXP (temp, 0),
4862 INTVAL (XEXP (temp, 1)));
4864 /* If X has only a single bit that might be nonzero, say, bit I, convert
4865 (neg X) to (ashiftrt (ashift X C-I) C-I) where C is the bitsize of
4866 MODE minus 1. This will convert (neg (zero_extract X 1 Y)) to
4867 (sign_extract X 1 Y). But only do this if TEMP isn't a register
4868 or a SUBREG of one since we'd be making the expression more
4869 complex if it was just a register. */
4872 && ! (GET_CODE (temp) == SUBREG
4873 && REG_P (SUBREG_REG (temp)))
4874 && (i = exact_log2 (nonzero_bits (temp, mode))) >= 0)
4876 rtx temp1 = simplify_shift_const
4877 (NULL_RTX, ASHIFTRT, mode,
4878 simplify_shift_const (NULL_RTX, ASHIFT, mode, temp,
4879 GET_MODE_BITSIZE (mode) - 1 - i),
4880 GET_MODE_BITSIZE (mode) - 1 - i);
4882 /* If all we did was surround TEMP with the two shifts, we
4883 haven't improved anything, so don't use it. Otherwise,
4884 we are better off with TEMP1. */
4885 if (GET_CODE (temp1) != ASHIFTRT
4886 || GET_CODE (XEXP (temp1, 0)) != ASHIFT
4887 || XEXP (XEXP (temp1, 0), 0) != temp)
4893 /* We can't handle truncation to a partial integer mode here
4894 because we don't know the real bitsize of the partial
4896 if (GET_MODE_CLASS (mode) == MODE_PARTIAL_INT)
4899 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4900 && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode),
4901 GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))))
4903 force_to_mode (XEXP (x, 0), GET_MODE (XEXP (x, 0)),
4904 GET_MODE_MASK (mode), 0));
4906 /* Similarly to what we do in simplify-rtx.c, a truncate of a register
4907 whose value is a comparison can be replaced with a subreg if
4908 STORE_FLAG_VALUE permits. */
4909 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4910 && ((HOST_WIDE_INT) STORE_FLAG_VALUE & ~GET_MODE_MASK (mode)) == 0
4911 && (temp = get_last_value (XEXP (x, 0)))
4912 && COMPARISON_P (temp))
4913 return gen_lowpart (mode, XEXP (x, 0));
4918 /* Convert (compare FOO (const_int 0)) to FOO unless we aren't
4919 using cc0, in which case we want to leave it as a COMPARE
4920 so we can distinguish it from a register-register-copy. */
4921 if (XEXP (x, 1) == const0_rtx)
4924 /* x - 0 is the same as x unless x's mode has signed zeros and
4925 allows rounding towards -infinity. Under those conditions,
4927 if (!(HONOR_SIGNED_ZEROS (GET_MODE (XEXP (x, 0)))
4928 && HONOR_SIGN_DEPENDENT_ROUNDING (GET_MODE (XEXP (x, 0))))
4929 && XEXP (x, 1) == CONST0_RTX (GET_MODE (XEXP (x, 0))))
4935 /* (const (const X)) can become (const X). Do it this way rather than
4936 returning the inner CONST since CONST can be shared with a
4938 if (GET_CODE (XEXP (x, 0)) == CONST)
4939 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4944 /* Convert (lo_sum (high FOO) FOO) to FOO. This is necessary so we
4945 can add in an offset. find_split_point will split this address up
4946 again if it doesn't match. */
4947 if (GET_CODE (XEXP (x, 0)) == HIGH
4948 && rtx_equal_p (XEXP (XEXP (x, 0), 0), XEXP (x, 1)))
4954 /* (plus (xor (and <foo> (const_int pow2 - 1)) <c>) <-c>)
4955 when c is (const_int (pow2 + 1) / 2) is a sign extension of a
4956 bit-field and can be replaced by either a sign_extend or a
4957 sign_extract. The `and' may be a zero_extend and the two
4958 <c>, -<c> constants may be reversed. */
4959 if (GET_CODE (XEXP (x, 0)) == XOR
4960 && GET_CODE (XEXP (x, 1)) == CONST_INT
4961 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
4962 && INTVAL (XEXP (x, 1)) == -INTVAL (XEXP (XEXP (x, 0), 1))
4963 && ((i = exact_log2 (INTVAL (XEXP (XEXP (x, 0), 1)))) >= 0
4964 || (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0)
4965 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4966 && ((GET_CODE (XEXP (XEXP (x, 0), 0)) == AND
4967 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == CONST_INT
4968 && (INTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1))
4969 == ((HOST_WIDE_INT) 1 << (i + 1)) - 1))
4970 || (GET_CODE (XEXP (XEXP (x, 0), 0)) == ZERO_EXTEND
4971 && (GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)))
4972 == (unsigned int) i + 1))))
4973 return simplify_shift_const
4974 (NULL_RTX, ASHIFTRT, mode,
4975 simplify_shift_const (NULL_RTX, ASHIFT, mode,
4976 XEXP (XEXP (XEXP (x, 0), 0), 0),
4977 GET_MODE_BITSIZE (mode) - (i + 1)),
4978 GET_MODE_BITSIZE (mode) - (i + 1));
4980 /* If only the low-order bit of X is possibly nonzero, (plus x -1)
4981 can become (ashiftrt (ashift (xor x 1) C) C) where C is
4982 the bitsize of the mode - 1. This allows simplification of
4983 "a = (b & 8) == 0;" */
4984 if (XEXP (x, 1) == constm1_rtx
4985 && !REG_P (XEXP (x, 0))
4986 && ! (GET_CODE (XEXP (x, 0)) == SUBREG
4987 && REG_P (SUBREG_REG (XEXP (x, 0))))
4988 && nonzero_bits (XEXP (x, 0), mode) == 1)
4989 return simplify_shift_const (NULL_RTX, ASHIFTRT, mode,
4990 simplify_shift_const (NULL_RTX, ASHIFT, mode,
4991 gen_rtx_XOR (mode, XEXP (x, 0), const1_rtx),
4992 GET_MODE_BITSIZE (mode) - 1),
4993 GET_MODE_BITSIZE (mode) - 1);
4995 /* If we are adding two things that have no bits in common, convert
4996 the addition into an IOR. This will often be further simplified,
4997 for example in cases like ((a & 1) + (a & 2)), which can
5000 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5001 && (nonzero_bits (XEXP (x, 0), mode)
5002 & nonzero_bits (XEXP (x, 1), mode)) == 0)
5004 /* Try to simplify the expression further. */
5005 rtx tor = simplify_gen_binary (IOR, mode, XEXP (x, 0), XEXP (x, 1));
5006 temp = combine_simplify_rtx (tor, mode, in_dest);
5008 /* If we could, great. If not, do not go ahead with the IOR
5009 replacement, since PLUS appears in many special purpose
5010 address arithmetic instructions. */
5011 if (GET_CODE (temp) != CLOBBER && temp != tor)
5017 /* (minus <foo> (and <foo> (const_int -pow2))) becomes
5018 (and <foo> (const_int pow2-1)) */
5019 if (GET_CODE (XEXP (x, 1)) == AND
5020 && GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT
5021 && exact_log2 (-INTVAL (XEXP (XEXP (x, 1), 1))) >= 0
5022 && rtx_equal_p (XEXP (XEXP (x, 1), 0), XEXP (x, 0)))
5023 return simplify_and_const_int (NULL_RTX, mode, XEXP (x, 0),
5024 -INTVAL (XEXP (XEXP (x, 1), 1)) - 1);
5028 /* If we have (mult (plus A B) C), apply the distributive law and then
5029 the inverse distributive law to see if things simplify. This
5030 occurs mostly in addresses, often when unrolling loops. */
5032 if (GET_CODE (XEXP (x, 0)) == PLUS)
5034 rtx result = distribute_and_simplify_rtx (x, 0);
5039 /* Try simplify a*(b/c) as (a*b)/c. */
5040 if (FLOAT_MODE_P (mode) && flag_associative_math
5041 && GET_CODE (XEXP (x, 0)) == DIV)
5043 rtx tem = simplify_binary_operation (MULT, mode,
5044 XEXP (XEXP (x, 0), 0),
5047 return simplify_gen_binary (DIV, mode, tem, XEXP (XEXP (x, 0), 1));
5052 /* If this is a divide by a power of two, treat it as a shift if
5053 its first operand is a shift. */
5054 if (GET_CODE (XEXP (x, 1)) == CONST_INT
5055 && (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0
5056 && (GET_CODE (XEXP (x, 0)) == ASHIFT
5057 || GET_CODE (XEXP (x, 0)) == LSHIFTRT
5058 || GET_CODE (XEXP (x, 0)) == ASHIFTRT
5059 || GET_CODE (XEXP (x, 0)) == ROTATE
5060 || GET_CODE (XEXP (x, 0)) == ROTATERT))
5061 return simplify_shift_const (NULL_RTX, LSHIFTRT, mode, XEXP (x, 0), i);
5065 case GT: case GTU: case GE: case GEU:
5066 case LT: case LTU: case LE: case LEU:
5067 case UNEQ: case LTGT:
5068 case UNGT: case UNGE:
5069 case UNLT: case UNLE:
5070 case UNORDERED: case ORDERED:
5071 /* If the first operand is a condition code, we can't do anything
5073 if (GET_CODE (XEXP (x, 0)) == COMPARE
5074 || (GET_MODE_CLASS (GET_MODE (XEXP (x, 0))) != MODE_CC
5075 && ! CC0_P (XEXP (x, 0))))
5077 rtx op0 = XEXP (x, 0);
5078 rtx op1 = XEXP (x, 1);
5079 enum rtx_code new_code;
5081 if (GET_CODE (op0) == COMPARE)
5082 op1 = XEXP (op0, 1), op0 = XEXP (op0, 0);
5084 /* Simplify our comparison, if possible. */
5085 new_code = simplify_comparison (code, &op0, &op1);
5087 /* If STORE_FLAG_VALUE is 1, we can convert (ne x 0) to simply X
5088 if only the low-order bit is possibly nonzero in X (such as when
5089 X is a ZERO_EXTRACT of one bit). Similarly, we can convert EQ to
5090 (xor X 1) or (minus 1 X); we use the former. Finally, if X is
5091 known to be either 0 or -1, NE becomes a NEG and EQ becomes
5094 Remove any ZERO_EXTRACT we made when thinking this was a
5095 comparison. It may now be simpler to use, e.g., an AND. If a
5096 ZERO_EXTRACT is indeed appropriate, it will be placed back by
5097 the call to make_compound_operation in the SET case. */
5099 if (STORE_FLAG_VALUE == 1
5100 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
5101 && op1 == const0_rtx
5102 && mode == GET_MODE (op0)
5103 && nonzero_bits (op0, mode) == 1)
5104 return gen_lowpart (mode,
5105 expand_compound_operation (op0));
5107 else if (STORE_FLAG_VALUE == 1
5108 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
5109 && op1 == const0_rtx
5110 && mode == GET_MODE (op0)
5111 && (num_sign_bit_copies (op0, mode)
5112 == GET_MODE_BITSIZE (mode)))
5114 op0 = expand_compound_operation (op0);
5115 return simplify_gen_unary (NEG, mode,
5116 gen_lowpart (mode, op0),
5120 else if (STORE_FLAG_VALUE == 1
5121 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
5122 && op1 == const0_rtx
5123 && mode == GET_MODE (op0)
5124 && nonzero_bits (op0, mode) == 1)
5126 op0 = expand_compound_operation (op0);
5127 return simplify_gen_binary (XOR, mode,
5128 gen_lowpart (mode, op0),
5132 else if (STORE_FLAG_VALUE == 1
5133 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
5134 && op1 == const0_rtx
5135 && mode == GET_MODE (op0)
5136 && (num_sign_bit_copies (op0, mode)
5137 == GET_MODE_BITSIZE (mode)))
5139 op0 = expand_compound_operation (op0);
5140 return plus_constant (gen_lowpart (mode, op0), 1);
5143 /* If STORE_FLAG_VALUE is -1, we have cases similar to
5145 if (STORE_FLAG_VALUE == -1
5146 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
5147 && op1 == const0_rtx
5148 && (num_sign_bit_copies (op0, mode)
5149 == GET_MODE_BITSIZE (mode)))
5150 return gen_lowpart (mode,
5151 expand_compound_operation (op0));
5153 else if (STORE_FLAG_VALUE == -1
5154 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
5155 && op1 == const0_rtx
5156 && mode == GET_MODE (op0)
5157 && nonzero_bits (op0, mode) == 1)
5159 op0 = expand_compound_operation (op0);
5160 return simplify_gen_unary (NEG, mode,
5161 gen_lowpart (mode, op0),
5165 else if (STORE_FLAG_VALUE == -1
5166 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
5167 && op1 == const0_rtx
5168 && mode == GET_MODE (op0)
5169 && (num_sign_bit_copies (op0, mode)
5170 == GET_MODE_BITSIZE (mode)))
5172 op0 = expand_compound_operation (op0);
5173 return simplify_gen_unary (NOT, mode,
5174 gen_lowpart (mode, op0),
5178 /* If X is 0/1, (eq X 0) is X-1. */
5179 else if (STORE_FLAG_VALUE == -1
5180 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
5181 && op1 == const0_rtx
5182 && mode == GET_MODE (op0)
5183 && nonzero_bits (op0, mode) == 1)
5185 op0 = expand_compound_operation (op0);
5186 return plus_constant (gen_lowpart (mode, op0), -1);
5189 /* If STORE_FLAG_VALUE says to just test the sign bit and X has just
5190 one bit that might be nonzero, we can convert (ne x 0) to
5191 (ashift x c) where C puts the bit in the sign bit. Remove any
5192 AND with STORE_FLAG_VALUE when we are done, since we are only
5193 going to test the sign bit. */
5194 if (new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
5195 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5196 && ((STORE_FLAG_VALUE & GET_MODE_MASK (mode))
5197 == (unsigned HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (mode) - 1))
5198 && op1 == const0_rtx
5199 && mode == GET_MODE (op0)
5200 && (i = exact_log2 (nonzero_bits (op0, mode))) >= 0)
5202 x = simplify_shift_const (NULL_RTX, ASHIFT, mode,
5203 expand_compound_operation (op0),
5204 GET_MODE_BITSIZE (mode) - 1 - i);
5205 if (GET_CODE (x) == AND && XEXP (x, 1) == const_true_rtx)
5211 /* If the code changed, return a whole new comparison. */
5212 if (new_code != code)
5213 return gen_rtx_fmt_ee (new_code, mode, op0, op1);
5215 /* Otherwise, keep this operation, but maybe change its operands.
5216 This also converts (ne (compare FOO BAR) 0) to (ne FOO BAR). */
5217 SUBST (XEXP (x, 0), op0);
5218 SUBST (XEXP (x, 1), op1);
5223 return simplify_if_then_else (x);
5229 /* If we are processing SET_DEST, we are done. */
5233 return expand_compound_operation (x);
5236 return simplify_set (x);
5240 return simplify_logical (x);
5247 /* If this is a shift by a constant amount, simplify it. */
5248 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
5249 return simplify_shift_const (x, code, mode, XEXP (x, 0),
5250 INTVAL (XEXP (x, 1)));
5252 else if (SHIFT_COUNT_TRUNCATED && !REG_P (XEXP (x, 1)))
5254 force_to_mode (XEXP (x, 1), GET_MODE (XEXP (x, 1)),
5256 << exact_log2 (GET_MODE_BITSIZE (GET_MODE (x))))
5268 /* Simplify X, an IF_THEN_ELSE expression. Return the new expression. */
5271 simplify_if_then_else (rtx x)
5273 enum machine_mode mode = GET_MODE (x);
5274 rtx cond = XEXP (x, 0);
5275 rtx true_rtx = XEXP (x, 1);
5276 rtx false_rtx = XEXP (x, 2);
5277 enum rtx_code true_code = GET_CODE (cond);
5278 int comparison_p = COMPARISON_P (cond);
5281 enum rtx_code false_code;
5284 /* Simplify storing of the truth value. */
5285 if (comparison_p && true_rtx == const_true_rtx && false_rtx == const0_rtx)
5286 return simplify_gen_relational (true_code, mode, VOIDmode,
5287 XEXP (cond, 0), XEXP (cond, 1));
5289 /* Also when the truth value has to be reversed. */
5291 && true_rtx == const0_rtx && false_rtx == const_true_rtx
5292 && (reversed = reversed_comparison (cond, mode)))
5295 /* Sometimes we can simplify the arm of an IF_THEN_ELSE if a register used
5296 in it is being compared against certain values. Get the true and false
5297 comparisons and see if that says anything about the value of each arm. */
5300 && ((false_code = reversed_comparison_code (cond, NULL))
5302 && REG_P (XEXP (cond, 0)))
5305 rtx from = XEXP (cond, 0);
5306 rtx true_val = XEXP (cond, 1);
5307 rtx false_val = true_val;
5310 /* If FALSE_CODE is EQ, swap the codes and arms. */
5312 if (false_code == EQ)
5314 swapped = 1, true_code = EQ, false_code = NE;
5315 temp = true_rtx, true_rtx = false_rtx, false_rtx = temp;
5318 /* If we are comparing against zero and the expression being tested has
5319 only a single bit that might be nonzero, that is its value when it is
5320 not equal to zero. Similarly if it is known to be -1 or 0. */
5322 if (true_code == EQ && true_val == const0_rtx
5323 && exact_log2 (nzb = nonzero_bits (from, GET_MODE (from))) >= 0)
5326 false_val = GEN_INT (trunc_int_for_mode (nzb, GET_MODE (from)));
5328 else if (true_code == EQ && true_val == const0_rtx
5329 && (num_sign_bit_copies (from, GET_MODE (from))
5330 == GET_MODE_BITSIZE (GET_MODE (from))))
5333 false_val = constm1_rtx;
5336 /* Now simplify an arm if we know the value of the register in the
5337 branch and it is used in the arm. Be careful due to the potential
5338 of locally-shared RTL. */
5340 if (reg_mentioned_p (from, true_rtx))
5341 true_rtx = subst (known_cond (copy_rtx (true_rtx), true_code,
5343 pc_rtx, pc_rtx, 0, 0);
5344 if (reg_mentioned_p (from, false_rtx))
5345 false_rtx = subst (known_cond (copy_rtx (false_rtx), false_code,
5347 pc_rtx, pc_rtx, 0, 0);
5349 SUBST (XEXP (x, 1), swapped ? false_rtx : true_rtx);
5350 SUBST (XEXP (x, 2), swapped ? true_rtx : false_rtx);
5352 true_rtx = XEXP (x, 1);
5353 false_rtx = XEXP (x, 2);
5354 true_code = GET_CODE (cond);
5357 /* If we have (if_then_else FOO (pc) (label_ref BAR)) and FOO can be
5358 reversed, do so to avoid needing two sets of patterns for
5359 subtract-and-branch insns. Similarly if we have a constant in the true
5360 arm, the false arm is the same as the first operand of the comparison, or
5361 the false arm is more complicated than the true arm. */
5364 && reversed_comparison_code (cond, NULL) != UNKNOWN
5365 && (true_rtx == pc_rtx
5366 || (CONSTANT_P (true_rtx)
5367 && GET_CODE (false_rtx) != CONST_INT && false_rtx != pc_rtx)
5368 || true_rtx == const0_rtx
5369 || (OBJECT_P (true_rtx) && !OBJECT_P (false_rtx))
5370 || (GET_CODE (true_rtx) == SUBREG && OBJECT_P (SUBREG_REG (true_rtx))
5371 && !OBJECT_P (false_rtx))
5372 || reg_mentioned_p (true_rtx, false_rtx)
5373 || rtx_equal_p (false_rtx, XEXP (cond, 0))))
5375 true_code = reversed_comparison_code (cond, NULL);
5376 SUBST (XEXP (x, 0), reversed_comparison (cond, GET_MODE (cond)));
5377 SUBST (XEXP (x, 1), false_rtx);
5378 SUBST (XEXP (x, 2), true_rtx);
5380 temp = true_rtx, true_rtx = false_rtx, false_rtx = temp;
5383 /* It is possible that the conditional has been simplified out. */
5384 true_code = GET_CODE (cond);
5385 comparison_p = COMPARISON_P (cond);
5388 /* If the two arms are identical, we don't need the comparison. */
5390 if (rtx_equal_p (true_rtx, false_rtx) && ! side_effects_p (cond))
5393 /* Convert a == b ? b : a to "a". */
5394 if (true_code == EQ && ! side_effects_p (cond)
5395 && !HONOR_NANS (mode)
5396 && rtx_equal_p (XEXP (cond, 0), false_rtx)
5397 && rtx_equal_p (XEXP (cond, 1), true_rtx))
5399 else if (true_code == NE && ! side_effects_p (cond)
5400 && !HONOR_NANS (mode)
5401 && rtx_equal_p (XEXP (cond, 0), true_rtx)
5402 && rtx_equal_p (XEXP (cond, 1), false_rtx))
5405 /* Look for cases where we have (abs x) or (neg (abs X)). */
5407 if (GET_MODE_CLASS (mode) == MODE_INT
5409 && XEXP (cond, 1) == const0_rtx
5410 && GET_CODE (false_rtx) == NEG
5411 && rtx_equal_p (true_rtx, XEXP (false_rtx, 0))
5412 && rtx_equal_p (true_rtx, XEXP (cond, 0))
5413 && ! side_effects_p (true_rtx))
5418 return simplify_gen_unary (ABS, mode, true_rtx, mode);
5422 simplify_gen_unary (NEG, mode,
5423 simplify_gen_unary (ABS, mode, true_rtx, mode),
5429 /* Look for MIN or MAX. */
5431 if ((! FLOAT_MODE_P (mode) || flag_unsafe_math_optimizations)
5433 && rtx_equal_p (XEXP (cond, 0), true_rtx)
5434 && rtx_equal_p (XEXP (cond, 1), false_rtx)
5435 && ! side_effects_p (cond))
5440 return simplify_gen_binary (SMAX, mode, true_rtx, false_rtx);
5443 return simplify_gen_binary (SMIN, mode, true_rtx, false_rtx);
5446 return simplify_gen_binary (UMAX, mode, true_rtx, false_rtx);
5449 return simplify_gen_binary (UMIN, mode, true_rtx, false_rtx);
5454 /* If we have (if_then_else COND (OP Z C1) Z) and OP is an identity when its
5455 second operand is zero, this can be done as (OP Z (mult COND C2)) where
5456 C2 = C1 * STORE_FLAG_VALUE. Similarly if OP has an outer ZERO_EXTEND or
5457 SIGN_EXTEND as long as Z is already extended (so we don't destroy it).
5458 We can do this kind of thing in some cases when STORE_FLAG_VALUE is
5459 neither 1 or -1, but it isn't worth checking for. */
5461 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
5463 && GET_MODE_CLASS (mode) == MODE_INT
5464 && ! side_effects_p (x))
5466 rtx t = make_compound_operation (true_rtx, SET);
5467 rtx f = make_compound_operation (false_rtx, SET);
5468 rtx cond_op0 = XEXP (cond, 0);
5469 rtx cond_op1 = XEXP (cond, 1);
5470 enum rtx_code op = UNKNOWN, extend_op = UNKNOWN;
5471 enum machine_mode m = mode;
5472 rtx z = 0, c1 = NULL_RTX;
5474 if ((GET_CODE (t) == PLUS || GET_CODE (t) == MINUS
5475 || GET_CODE (t) == IOR || GET_CODE (t) == XOR
5476 || GET_CODE (t) == ASHIFT
5477 || GET_CODE (t) == LSHIFTRT || GET_CODE (t) == ASHIFTRT)
5478 && rtx_equal_p (XEXP (t, 0), f))
5479 c1 = XEXP (t, 1), op = GET_CODE (t), z = f;
5481 /* If an identity-zero op is commutative, check whether there
5482 would be a match if we swapped the operands. */
5483 else if ((GET_CODE (t) == PLUS || GET_CODE (t) == IOR
5484 || GET_CODE (t) == XOR)
5485 && rtx_equal_p (XEXP (t, 1), f))
5486 c1 = XEXP (t, 0), op = GET_CODE (t), z = f;
5487 else if (GET_CODE (t) == SIGN_EXTEND
5488 && (GET_CODE (XEXP (t, 0)) == PLUS
5489 || GET_CODE (XEXP (t, 0)) == MINUS
5490 || GET_CODE (XEXP (t, 0)) == IOR
5491 || GET_CODE (XEXP (t, 0)) == XOR
5492 || GET_CODE (XEXP (t, 0)) == ASHIFT
5493 || GET_CODE (XEXP (t, 0)) == LSHIFTRT
5494 || GET_CODE (XEXP (t, 0)) == ASHIFTRT)
5495 && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG
5496 && subreg_lowpart_p (XEXP (XEXP (t, 0), 0))
5497 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f)
5498 && (num_sign_bit_copies (f, GET_MODE (f))
5500 (GET_MODE_BITSIZE (mode)
5501 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t, 0), 0))))))
5503 c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0));
5504 extend_op = SIGN_EXTEND;
5505 m = GET_MODE (XEXP (t, 0));
5507 else if (GET_CODE (t) == SIGN_EXTEND
5508 && (GET_CODE (XEXP (t, 0)) == PLUS
5509 || GET_CODE (XEXP (t, 0)) == IOR
5510 || GET_CODE (XEXP (t, 0)) == XOR)
5511 && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG
5512 && subreg_lowpart_p (XEXP (XEXP (t, 0), 1))
5513 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f)
5514 && (num_sign_bit_copies (f, GET_MODE (f))
5516 (GET_MODE_BITSIZE (mode)
5517 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t, 0), 1))))))
5519 c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0));
5520 extend_op = SIGN_EXTEND;
5521 m = GET_MODE (XEXP (t, 0));
5523 else if (GET_CODE (t) == ZERO_EXTEND
5524 && (GET_CODE (XEXP (t, 0)) == PLUS
5525 || GET_CODE (XEXP (t, 0)) == MINUS
5526 || GET_CODE (XEXP (t, 0)) == IOR
5527 || GET_CODE (XEXP (t, 0)) == XOR
5528 || GET_CODE (XEXP (t, 0)) == ASHIFT
5529 || GET_CODE (XEXP (t, 0)) == LSHIFTRT
5530 || GET_CODE (XEXP (t, 0)) == ASHIFTRT)
5531 && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG
5532 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5533 && subreg_lowpart_p (XEXP (XEXP (t, 0), 0))
5534 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f)
5535 && ((nonzero_bits (f, GET_MODE (f))
5536 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t, 0), 0))))
5539 c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0));
5540 extend_op = ZERO_EXTEND;
5541 m = GET_MODE (XEXP (t, 0));
5543 else if (GET_CODE (t) == ZERO_EXTEND
5544 && (GET_CODE (XEXP (t, 0)) == PLUS
5545 || GET_CODE (XEXP (t, 0)) == IOR
5546 || GET_CODE (XEXP (t, 0)) == XOR)
5547 && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG
5548 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5549 && subreg_lowpart_p (XEXP (XEXP (t, 0), 1))
5550 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f)
5551 && ((nonzero_bits (f, GET_MODE (f))
5552 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t, 0), 1))))
5555 c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0));
5556 extend_op = ZERO_EXTEND;
5557 m = GET_MODE (XEXP (t, 0));
5562 temp = subst (simplify_gen_relational (true_code, m, VOIDmode,
5563 cond_op0, cond_op1),
5564 pc_rtx, pc_rtx, 0, 0);
5565 temp = simplify_gen_binary (MULT, m, temp,
5566 simplify_gen_binary (MULT, m, c1,
5568 temp = subst (temp, pc_rtx, pc_rtx, 0, 0);
5569 temp = simplify_gen_binary (op, m, gen_lowpart (m, z), temp);
5571 if (extend_op != UNKNOWN)
5572 temp = simplify_gen_unary (extend_op, mode, temp, m);
5578 /* If we have (if_then_else (ne A 0) C1 0) and either A is known to be 0 or
5579 1 and C1 is a single bit or A is known to be 0 or -1 and C1 is the
5580 negation of a single bit, we can convert this operation to a shift. We
5581 can actually do this more generally, but it doesn't seem worth it. */
5583 if (true_code == NE && XEXP (cond, 1) == const0_rtx
5584 && false_rtx == const0_rtx && GET_CODE (true_rtx) == CONST_INT
5585 && ((1 == nonzero_bits (XEXP (cond, 0), mode)
5586 && (i = exact_log2 (INTVAL (true_rtx))) >= 0)
5587 || ((num_sign_bit_copies (XEXP (cond, 0), mode)
5588 == GET_MODE_BITSIZE (mode))
5589 && (i = exact_log2 (-INTVAL (true_rtx))) >= 0)))
5591 simplify_shift_const (NULL_RTX, ASHIFT, mode,
5592 gen_lowpart (mode, XEXP (cond, 0)), i);
5594 /* (IF_THEN_ELSE (NE REG 0) (0) (8)) is REG for nonzero_bits (REG) == 8. */
5595 if (true_code == NE && XEXP (cond, 1) == const0_rtx
5596 && false_rtx == const0_rtx && GET_CODE (true_rtx) == CONST_INT
5597 && GET_MODE (XEXP (cond, 0)) == mode
5598 && (INTVAL (true_rtx) & GET_MODE_MASK (mode))
5599 == nonzero_bits (XEXP (cond, 0), mode)
5600 && (i = exact_log2 (INTVAL (true_rtx) & GET_MODE_MASK (mode))) >= 0)
5601 return XEXP (cond, 0);
5606 /* Simplify X, a SET expression. Return the new expression. */
5609 simplify_set (rtx x)
5611 rtx src = SET_SRC (x);
5612 rtx dest = SET_DEST (x);
5613 enum machine_mode mode
5614 = GET_MODE (src) != VOIDmode ? GET_MODE (src) : GET_MODE (dest);
5618 /* (set (pc) (return)) gets written as (return). */
5619 if (GET_CODE (dest) == PC && GET_CODE (src) == RETURN)
5622 /* Now that we know for sure which bits of SRC we are using, see if we can
5623 simplify the expression for the object knowing that we only need the
5626 if (GET_MODE_CLASS (mode) == MODE_INT
5627 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
5629 src = force_to_mode (src, mode, ~(HOST_WIDE_INT) 0, 0);
5630 SUBST (SET_SRC (x), src);
5633 /* If we are setting CC0 or if the source is a COMPARE, look for the use of
5634 the comparison result and try to simplify it unless we already have used
5635 undobuf.other_insn. */
5636 if ((GET_MODE_CLASS (mode) == MODE_CC
5637 || GET_CODE (src) == COMPARE
5639 && (cc_use = find_single_use (dest, subst_insn, &other_insn)) != 0
5640 && (undobuf.other_insn == 0 || other_insn == undobuf.other_insn)
5641 && COMPARISON_P (*cc_use)
5642 && rtx_equal_p (XEXP (*cc_use, 0), dest))
5644 enum rtx_code old_code = GET_CODE (*cc_use);
5645 enum rtx_code new_code;
5647 int other_changed = 0;
5648 enum machine_mode compare_mode = GET_MODE (dest);
5650 if (GET_CODE (src) == COMPARE)
5651 op0 = XEXP (src, 0), op1 = XEXP (src, 1);
5653 op0 = src, op1 = CONST0_RTX (GET_MODE (src));
5655 tmp = simplify_relational_operation (old_code, compare_mode, VOIDmode,
5658 new_code = old_code;
5659 else if (!CONSTANT_P (tmp))
5661 new_code = GET_CODE (tmp);
5662 op0 = XEXP (tmp, 0);
5663 op1 = XEXP (tmp, 1);
5667 rtx pat = PATTERN (other_insn);
5668 undobuf.other_insn = other_insn;
5669 SUBST (*cc_use, tmp);
5671 /* Attempt to simplify CC user. */
5672 if (GET_CODE (pat) == SET)
5674 rtx new = simplify_rtx (SET_SRC (pat));
5675 if (new != NULL_RTX)
5676 SUBST (SET_SRC (pat), new);
5679 /* Convert X into a no-op move. */
5680 SUBST (SET_DEST (x), pc_rtx);
5681 SUBST (SET_SRC (x), pc_rtx);
5685 /* Simplify our comparison, if possible. */
5686 new_code = simplify_comparison (new_code, &op0, &op1);
5688 #ifdef SELECT_CC_MODE
5689 /* If this machine has CC modes other than CCmode, check to see if we
5690 need to use a different CC mode here. */
5691 if (GET_MODE_CLASS (GET_MODE (op0)) == MODE_CC)
5692 compare_mode = GET_MODE (op0);
5694 compare_mode = SELECT_CC_MODE (new_code, op0, op1);
5697 /* If the mode changed, we have to change SET_DEST, the mode in the
5698 compare, and the mode in the place SET_DEST is used. If SET_DEST is
5699 a hard register, just build new versions with the proper mode. If it
5700 is a pseudo, we lose unless it is only time we set the pseudo, in
5701 which case we can safely change its mode. */
5702 if (compare_mode != GET_MODE (dest))
5704 if (can_change_dest_mode (dest, 0, compare_mode))
5706 unsigned int regno = REGNO (dest);
5709 if (regno < FIRST_PSEUDO_REGISTER)
5710 new_dest = gen_rtx_REG (compare_mode, regno);
5713 SUBST_MODE (regno_reg_rtx[regno], compare_mode);
5714 new_dest = regno_reg_rtx[regno];
5717 SUBST (SET_DEST (x), new_dest);
5718 SUBST (XEXP (*cc_use, 0), new_dest);
5725 #endif /* SELECT_CC_MODE */
5727 /* If the code changed, we have to build a new comparison in
5728 undobuf.other_insn. */
5729 if (new_code != old_code)
5731 int other_changed_previously = other_changed;
5732 unsigned HOST_WIDE_INT mask;
5734 SUBST (*cc_use, gen_rtx_fmt_ee (new_code, GET_MODE (*cc_use),
5738 /* If the only change we made was to change an EQ into an NE or
5739 vice versa, OP0 has only one bit that might be nonzero, and OP1
5740 is zero, check if changing the user of the condition code will
5741 produce a valid insn. If it won't, we can keep the original code
5742 in that insn by surrounding our operation with an XOR. */
5744 if (((old_code == NE && new_code == EQ)
5745 || (old_code == EQ && new_code == NE))
5746 && ! other_changed_previously && op1 == const0_rtx
5747 && GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
5748 && exact_log2 (mask = nonzero_bits (op0, GET_MODE (op0))) >= 0)
5750 rtx pat = PATTERN (other_insn), note = 0;
5752 if ((recog_for_combine (&pat, other_insn, ¬e) < 0
5753 && ! check_asm_operands (pat)))
5755 PUT_CODE (*cc_use, old_code);
5758 op0 = simplify_gen_binary (XOR, GET_MODE (op0),
5759 op0, GEN_INT (mask));
5765 undobuf.other_insn = other_insn;
5768 /* If we are now comparing against zero, change our source if
5769 needed. If we do not use cc0, we always have a COMPARE. */
5770 if (op1 == const0_rtx && dest == cc0_rtx)
5772 SUBST (SET_SRC (x), op0);
5778 /* Otherwise, if we didn't previously have a COMPARE in the
5779 correct mode, we need one. */
5780 if (GET_CODE (src) != COMPARE || GET_MODE (src) != compare_mode)
5782 SUBST (SET_SRC (x), gen_rtx_COMPARE (compare_mode, op0, op1));
5785 else if (GET_MODE (op0) == compare_mode && op1 == const0_rtx)
5787 SUBST (SET_SRC (x), op0);
5790 /* Otherwise, update the COMPARE if needed. */
5791 else if (XEXP (src, 0) != op0 || XEXP (src, 1) != op1)
5793 SUBST (SET_SRC (x), gen_rtx_COMPARE (compare_mode, op0, op1));
5799 /* Get SET_SRC in a form where we have placed back any
5800 compound expressions. Then do the checks below. */
5801 src = make_compound_operation (src, SET);
5802 SUBST (SET_SRC (x), src);
5805 /* If we have (set x (subreg:m1 (op:m2 ...) 0)) with OP being some operation,
5806 and X being a REG or (subreg (reg)), we may be able to convert this to
5807 (set (subreg:m2 x) (op)).
5809 We can always do this if M1 is narrower than M2 because that means that
5810 we only care about the low bits of the result.
5812 However, on machines without WORD_REGISTER_OPERATIONS defined, we cannot
5813 perform a narrower operation than requested since the high-order bits will
5814 be undefined. On machine where it is defined, this transformation is safe
5815 as long as M1 and M2 have the same number of words. */
5817 if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src)
5818 && !OBJECT_P (SUBREG_REG (src))
5819 && (((GET_MODE_SIZE (GET_MODE (src)) + (UNITS_PER_WORD - 1))
5821 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (src)))
5822 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD))
5823 #ifndef WORD_REGISTER_OPERATIONS
5824 && (GET_MODE_SIZE (GET_MODE (src))
5825 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (src))))
5827 #ifdef CANNOT_CHANGE_MODE_CLASS
5828 && ! (REG_P (dest) && REGNO (dest) < FIRST_PSEUDO_REGISTER
5829 && REG_CANNOT_CHANGE_MODE_P (REGNO (dest),
5830 GET_MODE (SUBREG_REG (src)),
5834 || (GET_CODE (dest) == SUBREG
5835 && REG_P (SUBREG_REG (dest)))))
5837 SUBST (SET_DEST (x),
5838 gen_lowpart (GET_MODE (SUBREG_REG (src)),
5840 SUBST (SET_SRC (x), SUBREG_REG (src));
5842 src = SET_SRC (x), dest = SET_DEST (x);
5846 /* If we have (set (cc0) (subreg ...)), we try to remove the subreg
5849 && GET_CODE (src) == SUBREG
5850 && subreg_lowpart_p (src)
5851 && (GET_MODE_BITSIZE (GET_MODE (src))
5852 < GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (src)))))
5854 rtx inner = SUBREG_REG (src);
5855 enum machine_mode inner_mode = GET_MODE (inner);
5857 /* Here we make sure that we don't have a sign bit on. */
5858 if (GET_MODE_BITSIZE (inner_mode) <= HOST_BITS_PER_WIDE_INT
5859 && (nonzero_bits (inner, inner_mode)
5860 < ((unsigned HOST_WIDE_INT) 1
5861 << (GET_MODE_BITSIZE (GET_MODE (src)) - 1))))
5863 SUBST (SET_SRC (x), inner);
5869 #ifdef LOAD_EXTEND_OP
5870 /* If we have (set FOO (subreg:M (mem:N BAR) 0)) with M wider than N, this
5871 would require a paradoxical subreg. Replace the subreg with a
5872 zero_extend to avoid the reload that would otherwise be required. */
5874 if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src)
5875 && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src))) != UNKNOWN
5876 && SUBREG_BYTE (src) == 0
5877 && (GET_MODE_SIZE (GET_MODE (src))
5878 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (src))))
5879 && MEM_P (SUBREG_REG (src)))
5882 gen_rtx_fmt_e (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src))),
5883 GET_MODE (src), SUBREG_REG (src)));
5889 /* If we don't have a conditional move, SET_SRC is an IF_THEN_ELSE, and we
5890 are comparing an item known to be 0 or -1 against 0, use a logical
5891 operation instead. Check for one of the arms being an IOR of the other
5892 arm with some value. We compute three terms to be IOR'ed together. In
5893 practice, at most two will be nonzero. Then we do the IOR's. */
5895 if (GET_CODE (dest) != PC
5896 && GET_CODE (src) == IF_THEN_ELSE
5897 && GET_MODE_CLASS (GET_MODE (src)) == MODE_INT
5898 && (GET_CODE (XEXP (src, 0)) == EQ || GET_CODE (XEXP (src, 0)) == NE)
5899 && XEXP (XEXP (src, 0), 1) == const0_rtx
5900 && GET_MODE (src) == GET_MODE (XEXP (XEXP (src, 0), 0))
5901 #ifdef HAVE_conditional_move
5902 && ! can_conditionally_move_p (GET_MODE (src))
5904 && (num_sign_bit_copies (XEXP (XEXP (src, 0), 0),
5905 GET_MODE (XEXP (XEXP (src, 0), 0)))
5906 == GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (src, 0), 0))))
5907 && ! side_effects_p (src))
5909 rtx true_rtx = (GET_CODE (XEXP (src, 0)) == NE
5910 ? XEXP (src, 1) : XEXP (src, 2));
5911 rtx false_rtx = (GET_CODE (XEXP (src, 0)) == NE
5912 ? XEXP (src, 2) : XEXP (src, 1));
5913 rtx term1 = const0_rtx, term2, term3;
5915 if (GET_CODE (true_rtx) == IOR
5916 && rtx_equal_p (XEXP (true_rtx, 0), false_rtx))
5917 term1 = false_rtx, true_rtx = XEXP (true_rtx, 1), false_rtx = const0_rtx;
5918 else if (GET_CODE (true_rtx) == IOR
5919 && rtx_equal_p (XEXP (true_rtx, 1), false_rtx))
5920 term1 = false_rtx, true_rtx = XEXP (true_rtx, 0), false_rtx = const0_rtx;
5921 else if (GET_CODE (false_rtx) == IOR
5922 && rtx_equal_p (XEXP (false_rtx, 0), true_rtx))
5923 term1 = true_rtx, false_rtx = XEXP (false_rtx, 1), true_rtx = const0_rtx;
5924 else if (GET_CODE (false_rtx) == IOR
5925 && rtx_equal_p (XEXP (false_rtx, 1), true_rtx))
5926 term1 = true_rtx, false_rtx = XEXP (false_rtx, 0), true_rtx = const0_rtx;
5928 term2 = simplify_gen_binary (AND, GET_MODE (src),
5929 XEXP (XEXP (src, 0), 0), true_rtx);
5930 term3 = simplify_gen_binary (AND, GET_MODE (src),
5931 simplify_gen_unary (NOT, GET_MODE (src),
5932 XEXP (XEXP (src, 0), 0),
5937 simplify_gen_binary (IOR, GET_MODE (src),
5938 simplify_gen_binary (IOR, GET_MODE (src),
5945 /* If either SRC or DEST is a CLOBBER of (const_int 0), make this
5946 whole thing fail. */
5947 if (GET_CODE (src) == CLOBBER && XEXP (src, 0) == const0_rtx)
5949 else if (GET_CODE (dest) == CLOBBER && XEXP (dest, 0) == const0_rtx)
5952 /* Convert this into a field assignment operation, if possible. */
5953 return make_field_assignment (x);
5956 /* Simplify, X, and AND, IOR, or XOR operation, and return the simplified
5960 simplify_logical (rtx x)
5962 enum machine_mode mode = GET_MODE (x);
5963 rtx op0 = XEXP (x, 0);
5964 rtx op1 = XEXP (x, 1);
5966 switch (GET_CODE (x))
5969 /* We can call simplify_and_const_int only if we don't lose
5970 any (sign) bits when converting INTVAL (op1) to
5971 "unsigned HOST_WIDE_INT". */
5972 if (GET_CODE (op1) == CONST_INT
5973 && (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5974 || INTVAL (op1) > 0))
5976 x = simplify_and_const_int (x, mode, op0, INTVAL (op1));
5977 if (GET_CODE (x) != AND)
5984 /* If we have any of (and (ior A B) C) or (and (xor A B) C),
5985 apply the distributive law and then the inverse distributive
5986 law to see if things simplify. */
5987 if (GET_CODE (op0) == IOR || GET_CODE (op0) == XOR)
5989 rtx result = distribute_and_simplify_rtx (x, 0);
5993 if (GET_CODE (op1) == IOR || GET_CODE (op1) == XOR)
5995 rtx result = distribute_and_simplify_rtx (x, 1);
6002 /* If we have (ior (and A B) C), apply the distributive law and then
6003 the inverse distributive law to see if things simplify. */
6005 if (GET_CODE (op0) == AND)
6007 rtx result = distribute_and_simplify_rtx (x, 0);
6012 if (GET_CODE (op1) == AND)
6014 rtx result = distribute_and_simplify_rtx (x, 1);
6027 /* We consider ZERO_EXTRACT, SIGN_EXTRACT, and SIGN_EXTEND as "compound
6028 operations" because they can be replaced with two more basic operations.
6029 ZERO_EXTEND is also considered "compound" because it can be replaced with
6030 an AND operation, which is simpler, though only one operation.
6032 The function expand_compound_operation is called with an rtx expression
6033 and will convert it to the appropriate shifts and AND operations,
6034 simplifying at each stage.
6036 The function make_compound_operation is called to convert an expression
6037 consisting of shifts and ANDs into the equivalent compound expression.
6038 It is the inverse of this function, loosely speaking. */
6041 expand_compound_operation (rtx x)
6043 unsigned HOST_WIDE_INT pos = 0, len;
6045 unsigned int modewidth;
6048 switch (GET_CODE (x))
6053 /* We can't necessarily use a const_int for a multiword mode;
6054 it depends on implicitly extending the value.
6055 Since we don't know the right way to extend it,
6056 we can't tell whether the implicit way is right.
6058 Even for a mode that is no wider than a const_int,
6059 we can't win, because we need to sign extend one of its bits through
6060 the rest of it, and we don't know which bit. */
6061 if (GET_CODE (XEXP (x, 0)) == CONST_INT)
6064 /* Return if (subreg:MODE FROM 0) is not a safe replacement for
6065 (zero_extend:MODE FROM) or (sign_extend:MODE FROM). It is for any MEM
6066 because (SUBREG (MEM...)) is guaranteed to cause the MEM to be
6067 reloaded. If not for that, MEM's would very rarely be safe.
6069 Reject MODEs bigger than a word, because we might not be able
6070 to reference a two-register group starting with an arbitrary register
6071 (and currently gen_lowpart might crash for a SUBREG). */
6073 if (GET_MODE_SIZE (GET_MODE (XEXP (x, 0))) > UNITS_PER_WORD)
6076 /* Reject MODEs that aren't scalar integers because turning vector
6077 or complex modes into shifts causes problems. */
6079 if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x, 0))))
6082 len = GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)));
6083 /* If the inner object has VOIDmode (the only way this can happen
6084 is if it is an ASM_OPERANDS), we can't do anything since we don't
6085 know how much masking to do. */
6094 /* ... fall through ... */
6097 /* If the operand is a CLOBBER, just return it. */
6098 if (GET_CODE (XEXP (x, 0)) == CLOBBER)
6101 if (GET_CODE (XEXP (x, 1)) != CONST_INT
6102 || GET_CODE (XEXP (x, 2)) != CONST_INT
6103 || GET_MODE (XEXP (x, 0)) == VOIDmode)
6106 /* Reject MODEs that aren't scalar integers because turning vector
6107 or complex modes into shifts causes problems. */
6109 if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x, 0))))
6112 len = INTVAL (XEXP (x, 1));
6113 pos = INTVAL (XEXP (x, 2));
6115 /* This should stay within the object being extracted, fail otherwise. */
6116 if (len + pos > GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))))
6119 if (BITS_BIG_ENDIAN)
6120 pos = GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - len - pos;
6127 /* Convert sign extension to zero extension, if we know that the high
6128 bit is not set, as this is easier to optimize. It will be converted
6129 back to cheaper alternative in make_extraction. */
6130 if (GET_CODE (x) == SIGN_EXTEND
6131 && (GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
6132 && ((nonzero_bits (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
6133 & ~(((unsigned HOST_WIDE_INT)
6134 GET_MODE_MASK (GET_MODE (XEXP (x, 0))))
6138 rtx temp = gen_rtx_ZERO_EXTEND (GET_MODE (x), XEXP (x, 0));
6139 rtx temp2 = expand_compound_operation (temp);
6141 /* Make sure this is a profitable operation. */
6142 if (rtx_cost (x, SET) > rtx_cost (temp2, SET))
6144 else if (rtx_cost (x, SET) > rtx_cost (temp, SET))
6150 /* We can optimize some special cases of ZERO_EXTEND. */
6151 if (GET_CODE (x) == ZERO_EXTEND)
6153 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI if we
6154 know that the last value didn't have any inappropriate bits
6156 if (GET_CODE (XEXP (x, 0)) == TRUNCATE
6157 && GET_MODE (XEXP (XEXP (x, 0), 0)) == GET_MODE (x)
6158 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
6159 && (nonzero_bits (XEXP (XEXP (x, 0), 0), GET_MODE (x))
6160 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
6161 return XEXP (XEXP (x, 0), 0);
6163 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
6164 if (GET_CODE (XEXP (x, 0)) == SUBREG
6165 && GET_MODE (SUBREG_REG (XEXP (x, 0))) == GET_MODE (x)
6166 && subreg_lowpart_p (XEXP (x, 0))
6167 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
6168 && (nonzero_bits (SUBREG_REG (XEXP (x, 0)), GET_MODE (x))
6169 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
6170 return SUBREG_REG (XEXP (x, 0));
6172 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI when foo
6173 is a comparison and STORE_FLAG_VALUE permits. This is like
6174 the first case, but it works even when GET_MODE (x) is larger
6175 than HOST_WIDE_INT. */
6176 if (GET_CODE (XEXP (x, 0)) == TRUNCATE
6177 && GET_MODE (XEXP (XEXP (x, 0), 0)) == GET_MODE (x)
6178 && COMPARISON_P (XEXP (XEXP (x, 0), 0))
6179 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
6180 <= HOST_BITS_PER_WIDE_INT)
6181 && ((HOST_WIDE_INT) STORE_FLAG_VALUE
6182 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
6183 return XEXP (XEXP (x, 0), 0);
6185 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
6186 if (GET_CODE (XEXP (x, 0)) == SUBREG
6187 && GET_MODE (SUBREG_REG (XEXP (x, 0))) == GET_MODE (x)
6188 && subreg_lowpart_p (XEXP (x, 0))
6189 && COMPARISON_P (SUBREG_REG (XEXP (x, 0)))
6190 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
6191 <= HOST_BITS_PER_WIDE_INT)
6192 && ((HOST_WIDE_INT) STORE_FLAG_VALUE
6193 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
6194 return SUBREG_REG (XEXP (x, 0));
6198 /* If we reach here, we want to return a pair of shifts. The inner
6199 shift is a left shift of BITSIZE - POS - LEN bits. The outer
6200 shift is a right shift of BITSIZE - LEN bits. It is arithmetic or
6201 logical depending on the value of UNSIGNEDP.
6203 If this was a ZERO_EXTEND or ZERO_EXTRACT, this pair of shifts will be
6204 converted into an AND of a shift.
6206 We must check for the case where the left shift would have a negative
6207 count. This can happen in a case like (x >> 31) & 255 on machines
6208 that can't shift by a constant. On those machines, we would first
6209 combine the shift with the AND to produce a variable-position
6210 extraction. Then the constant of 31 would be substituted in to produce
6211 a such a position. */
6213 modewidth = GET_MODE_BITSIZE (GET_MODE (x));
6214 if (modewidth + len >= pos)
6216 enum machine_mode mode = GET_MODE (x);
6217 tem = gen_lowpart (mode, XEXP (x, 0));
6218 if (!tem || GET_CODE (tem) == CLOBBER)
6220 tem = simplify_shift_const (NULL_RTX, ASHIFT, mode,
6221 tem, modewidth - pos - len);
6222 tem = simplify_shift_const (NULL_RTX, unsignedp ? LSHIFTRT : ASHIFTRT,
6223 mode, tem, modewidth - len);
6225 else if (unsignedp && len < HOST_BITS_PER_WIDE_INT)
6226 tem = simplify_and_const_int (NULL_RTX, GET_MODE (x),
6227 simplify_shift_const (NULL_RTX, LSHIFTRT,
6230 ((HOST_WIDE_INT) 1 << len) - 1);
6232 /* Any other cases we can't handle. */
6235 /* If we couldn't do this for some reason, return the original
6237 if (GET_CODE (tem) == CLOBBER)
6243 /* X is a SET which contains an assignment of one object into
6244 a part of another (such as a bit-field assignment, STRICT_LOW_PART,
6245 or certain SUBREGS). If possible, convert it into a series of
6248 We half-heartedly support variable positions, but do not at all
6249 support variable lengths. */
6252 expand_field_assignment (const_rtx x)
6255 rtx pos; /* Always counts from low bit. */
6257 rtx mask, cleared, masked;
6258 enum machine_mode compute_mode;
6260 /* Loop until we find something we can't simplify. */
6263 if (GET_CODE (SET_DEST (x)) == STRICT_LOW_PART
6264 && GET_CODE (XEXP (SET_DEST (x), 0)) == SUBREG)
6266 inner = SUBREG_REG (XEXP (SET_DEST (x), 0));
6267 len = GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0)));
6268 pos = GEN_INT (subreg_lsb (XEXP (SET_DEST (x), 0)));
6270 else if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
6271 && GET_CODE (XEXP (SET_DEST (x), 1)) == CONST_INT)
6273 inner = XEXP (SET_DEST (x), 0);
6274 len = INTVAL (XEXP (SET_DEST (x), 1));
6275 pos = XEXP (SET_DEST (x), 2);
6277 /* A constant position should stay within the width of INNER. */
6278 if (GET_CODE (pos) == CONST_INT
6279 && INTVAL (pos) + len > GET_MODE_BITSIZE (GET_MODE (inner)))
6282 if (BITS_BIG_ENDIAN)
6284 if (GET_CODE (pos) == CONST_INT)
6285 pos = GEN_INT (GET_MODE_BITSIZE (GET_MODE (inner)) - len
6287 else if (GET_CODE (pos) == MINUS
6288 && GET_CODE (XEXP (pos, 1)) == CONST_INT
6289 && (INTVAL (XEXP (pos, 1))
6290 == GET_MODE_BITSIZE (GET_MODE (inner)) - len))
6291 /* If position is ADJUST - X, new position is X. */
6292 pos = XEXP (pos, 0);
6294 pos = simplify_gen_binary (MINUS, GET_MODE (pos),
6295 GEN_INT (GET_MODE_BITSIZE (
6302 /* A SUBREG between two modes that occupy the same numbers of words
6303 can be done by moving the SUBREG to the source. */
6304 else if (GET_CODE (SET_DEST (x)) == SUBREG
6305 /* We need SUBREGs to compute nonzero_bits properly. */
6306 && nonzero_sign_valid
6307 && (((GET_MODE_SIZE (GET_MODE (SET_DEST (x)))
6308 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
6309 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x))))
6310 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)))
6312 x = gen_rtx_SET (VOIDmode, SUBREG_REG (SET_DEST (x)),
6314 (GET_MODE (SUBREG_REG (SET_DEST (x))),
6321 while (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
6322 inner = SUBREG_REG (inner);
6324 compute_mode = GET_MODE (inner);
6326 /* Don't attempt bitwise arithmetic on non scalar integer modes. */
6327 if (! SCALAR_INT_MODE_P (compute_mode))
6329 enum machine_mode imode;
6331 /* Don't do anything for vector or complex integral types. */
6332 if (! FLOAT_MODE_P (compute_mode))
6335 /* Try to find an integral mode to pun with. */
6336 imode = mode_for_size (GET_MODE_BITSIZE (compute_mode), MODE_INT, 0);
6337 if (imode == BLKmode)
6340 compute_mode = imode;
6341 inner = gen_lowpart (imode, inner);
6344 /* Compute a mask of LEN bits, if we can do this on the host machine. */
6345 if (len >= HOST_BITS_PER_WIDE_INT)
6348 /* Now compute the equivalent expression. Make a copy of INNER
6349 for the SET_DEST in case it is a MEM into which we will substitute;
6350 we don't want shared RTL in that case. */
6351 mask = GEN_INT (((HOST_WIDE_INT) 1 << len) - 1);
6352 cleared = simplify_gen_binary (AND, compute_mode,
6353 simplify_gen_unary (NOT, compute_mode,
6354 simplify_gen_binary (ASHIFT,
6359 masked = simplify_gen_binary (ASHIFT, compute_mode,
6360 simplify_gen_binary (
6362 gen_lowpart (compute_mode, SET_SRC (x)),
6366 x = gen_rtx_SET (VOIDmode, copy_rtx (inner),
6367 simplify_gen_binary (IOR, compute_mode,
6374 /* Return an RTX for a reference to LEN bits of INNER. If POS_RTX is nonzero,
6375 it is an RTX that represents a variable starting position; otherwise,
6376 POS is the (constant) starting bit position (counted from the LSB).
6378 UNSIGNEDP is nonzero for an unsigned reference and zero for a
6381 IN_DEST is nonzero if this is a reference in the destination of a
6382 SET. This is used when a ZERO_ or SIGN_EXTRACT isn't needed. If nonzero,
6383 a STRICT_LOW_PART will be used, if zero, ZERO_EXTEND or SIGN_EXTEND will
6386 IN_COMPARE is nonzero if we are in a COMPARE. This means that a
6387 ZERO_EXTRACT should be built even for bits starting at bit 0.
6389 MODE is the desired mode of the result (if IN_DEST == 0).
6391 The result is an RTX for the extraction or NULL_RTX if the target
6395 make_extraction (enum machine_mode mode, rtx inner, HOST_WIDE_INT pos,
6396 rtx pos_rtx, unsigned HOST_WIDE_INT len, int unsignedp,
6397 int in_dest, int in_compare)
6399 /* This mode describes the size of the storage area
6400 to fetch the overall value from. Within that, we
6401 ignore the POS lowest bits, etc. */
6402 enum machine_mode is_mode = GET_MODE (inner);
6403 enum machine_mode inner_mode;
6404 enum machine_mode wanted_inner_mode;
6405 enum machine_mode wanted_inner_reg_mode = word_mode;
6406 enum machine_mode pos_mode = word_mode;
6407 enum machine_mode extraction_mode = word_mode;
6408 enum machine_mode tmode = mode_for_size (len, MODE_INT, 1);
6410 rtx orig_pos_rtx = pos_rtx;
6411 HOST_WIDE_INT orig_pos;
6413 if (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
6415 /* If going from (subreg:SI (mem:QI ...)) to (mem:QI ...),
6416 consider just the QI as the memory to extract from.
6417 The subreg adds or removes high bits; its mode is
6418 irrelevant to the meaning of this extraction,
6419 since POS and LEN count from the lsb. */
6420 if (MEM_P (SUBREG_REG (inner)))
6421 is_mode = GET_MODE (SUBREG_REG (inner));
6422 inner = SUBREG_REG (inner);
6424 else if (GET_CODE (inner) == ASHIFT
6425 && GET_CODE (XEXP (inner, 1)) == CONST_INT
6426 && pos_rtx == 0 && pos == 0
6427 && len > (unsigned HOST_WIDE_INT) INTVAL (XEXP (inner, 1)))
6429 /* We're extracting the least significant bits of an rtx
6430 (ashift X (const_int C)), where LEN > C. Extract the
6431 least significant (LEN - C) bits of X, giving an rtx
6432 whose mode is MODE, then shift it left C times. */
6433 new = make_extraction (mode, XEXP (inner, 0),
6434 0, 0, len - INTVAL (XEXP (inner, 1)),
6435 unsignedp, in_dest, in_compare);
6437 return gen_rtx_ASHIFT (mode, new, XEXP (inner, 1));
6440 inner_mode = GET_MODE (inner);
6442 if (pos_rtx && GET_CODE (pos_rtx) == CONST_INT)
6443 pos = INTVAL (pos_rtx), pos_rtx = 0;
6445 /* See if this can be done without an extraction. We never can if the
6446 width of the field is not the same as that of some integer mode. For
6447 registers, we can only avoid the extraction if the position is at the
6448 low-order bit and this is either not in the destination or we have the
6449 appropriate STRICT_LOW_PART operation available.
6451 For MEM, we can avoid an extract if the field starts on an appropriate
6452 boundary and we can change the mode of the memory reference. */
6454 if (tmode != BLKmode
6455 && ((pos_rtx == 0 && (pos % BITS_PER_WORD) == 0
6457 && (inner_mode == tmode
6459 || TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (tmode),
6460 GET_MODE_BITSIZE (inner_mode))
6461 || reg_truncated_to_mode (tmode, inner))
6464 && have_insn_for (STRICT_LOW_PART, tmode))))
6465 || (MEM_P (inner) && pos_rtx == 0
6467 % (STRICT_ALIGNMENT ? GET_MODE_ALIGNMENT (tmode)
6468 : BITS_PER_UNIT)) == 0
6469 /* We can't do this if we are widening INNER_MODE (it
6470 may not be aligned, for one thing). */
6471 && GET_MODE_BITSIZE (inner_mode) >= GET_MODE_BITSIZE (tmode)
6472 && (inner_mode == tmode
6473 || (! mode_dependent_address_p (XEXP (inner, 0))
6474 && ! MEM_VOLATILE_P (inner))))))
6476 /* If INNER is a MEM, make a new MEM that encompasses just the desired
6477 field. If the original and current mode are the same, we need not
6478 adjust the offset. Otherwise, we do if bytes big endian.
6480 If INNER is not a MEM, get a piece consisting of just the field
6481 of interest (in this case POS % BITS_PER_WORD must be 0). */
6485 HOST_WIDE_INT offset;
6487 /* POS counts from lsb, but make OFFSET count in memory order. */
6488 if (BYTES_BIG_ENDIAN)
6489 offset = (GET_MODE_BITSIZE (is_mode) - len - pos) / BITS_PER_UNIT;
6491 offset = pos / BITS_PER_UNIT;
6493 new = adjust_address_nv (inner, tmode, offset);
6495 else if (REG_P (inner))
6497 if (tmode != inner_mode)
6499 /* We can't call gen_lowpart in a DEST since we
6500 always want a SUBREG (see below) and it would sometimes
6501 return a new hard register. */
6504 HOST_WIDE_INT final_word = pos / BITS_PER_WORD;
6506 if (WORDS_BIG_ENDIAN
6507 && GET_MODE_SIZE (inner_mode) > UNITS_PER_WORD)
6508 final_word = ((GET_MODE_SIZE (inner_mode)
6509 - GET_MODE_SIZE (tmode))
6510 / UNITS_PER_WORD) - final_word;
6512 final_word *= UNITS_PER_WORD;
6513 if (BYTES_BIG_ENDIAN &&
6514 GET_MODE_SIZE (inner_mode) > GET_MODE_SIZE (tmode))
6515 final_word += (GET_MODE_SIZE (inner_mode)
6516 - GET_MODE_SIZE (tmode)) % UNITS_PER_WORD;
6518 /* Avoid creating invalid subregs, for example when
6519 simplifying (x>>32)&255. */
6520 if (!validate_subreg (tmode, inner_mode, inner, final_word))
6523 new = gen_rtx_SUBREG (tmode, inner, final_word);
6526 new = gen_lowpart (tmode, inner);
6532 new = force_to_mode (inner, tmode,
6533 len >= HOST_BITS_PER_WIDE_INT
6534 ? ~(unsigned HOST_WIDE_INT) 0
6535 : ((unsigned HOST_WIDE_INT) 1 << len) - 1,
6538 /* If this extraction is going into the destination of a SET,
6539 make a STRICT_LOW_PART unless we made a MEM. */
6542 return (MEM_P (new) ? new
6543 : (GET_CODE (new) != SUBREG
6544 ? gen_rtx_CLOBBER (tmode, const0_rtx)
6545 : gen_rtx_STRICT_LOW_PART (VOIDmode, new)));
6550 if (GET_CODE (new) == CONST_INT)
6551 return gen_int_mode (INTVAL (new), mode);
6553 /* If we know that no extraneous bits are set, and that the high
6554 bit is not set, convert the extraction to the cheaper of
6555 sign and zero extension, that are equivalent in these cases. */
6556 if (flag_expensive_optimizations
6557 && (GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT
6558 && ((nonzero_bits (new, tmode)
6559 & ~(((unsigned HOST_WIDE_INT)
6560 GET_MODE_MASK (tmode))
6564 rtx temp = gen_rtx_ZERO_EXTEND (mode, new);
6565 rtx temp1 = gen_rtx_SIGN_EXTEND (mode, new);
6567 /* Prefer ZERO_EXTENSION, since it gives more information to
6569 if (rtx_cost (temp, SET) <= rtx_cost (temp1, SET))
6574 /* Otherwise, sign- or zero-extend unless we already are in the
6577 return (gen_rtx_fmt_e (unsignedp ? ZERO_EXTEND : SIGN_EXTEND,
6581 /* Unless this is a COMPARE or we have a funny memory reference,
6582 don't do anything with zero-extending field extracts starting at
6583 the low-order bit since they are simple AND operations. */
6584 if (pos_rtx == 0 && pos == 0 && ! in_dest
6585 && ! in_compare && unsignedp)
6588 /* Unless INNER is not MEM, reject this if we would be spanning bytes or
6589 if the position is not a constant and the length is not 1. In all
6590 other cases, we would only be going outside our object in cases when
6591 an original shift would have been undefined. */
6593 && ((pos_rtx == 0 && pos + len > GET_MODE_BITSIZE (is_mode))
6594 || (pos_rtx != 0 && len != 1)))
6597 /* Get the mode to use should INNER not be a MEM, the mode for the position,
6598 and the mode for the result. */
6599 if (in_dest && mode_for_extraction (EP_insv, -1) != MAX_MACHINE_MODE)
6601 wanted_inner_reg_mode = mode_for_extraction (EP_insv, 0);
6602 pos_mode = mode_for_extraction (EP_insv, 2);
6603 extraction_mode = mode_for_extraction (EP_insv, 3);
6606 if (! in_dest && unsignedp
6607 && mode_for_extraction (EP_extzv, -1) != MAX_MACHINE_MODE)
6609 wanted_inner_reg_mode = mode_for_extraction (EP_extzv, 1);
6610 pos_mode = mode_for_extraction (EP_extzv, 3);
6611 extraction_mode = mode_for_extraction (EP_extzv, 0);
6614 if (! in_dest && ! unsignedp
6615 && mode_for_extraction (EP_extv, -1) != MAX_MACHINE_MODE)
6617 wanted_inner_reg_mode = mode_for_extraction (EP_extv, 1);
6618 pos_mode = mode_for_extraction (EP_extv, 3);
6619 extraction_mode = mode_for_extraction (EP_extv, 0);
6622 /* Never narrow an object, since that might not be safe. */
6624 if (mode != VOIDmode
6625 && GET_MODE_SIZE (extraction_mode) < GET_MODE_SIZE (mode))
6626 extraction_mode = mode;
6628 if (pos_rtx && GET_MODE (pos_rtx) != VOIDmode
6629 && GET_MODE_SIZE (pos_mode) < GET_MODE_SIZE (GET_MODE (pos_rtx)))
6630 pos_mode = GET_MODE (pos_rtx);
6632 /* If this is not from memory, the desired mode is the preferred mode
6633 for an extraction pattern's first input operand, or word_mode if there
6636 wanted_inner_mode = wanted_inner_reg_mode;
6639 /* Be careful not to go beyond the extracted object and maintain the
6640 natural alignment of the memory. */
6641 wanted_inner_mode = smallest_mode_for_size (len, MODE_INT);
6642 while (pos % GET_MODE_BITSIZE (wanted_inner_mode) + len
6643 > GET_MODE_BITSIZE (wanted_inner_mode))
6645 wanted_inner_mode = GET_MODE_WIDER_MODE (wanted_inner_mode);
6646 gcc_assert (wanted_inner_mode != VOIDmode);
6649 /* If we have to change the mode of memory and cannot, the desired mode
6650 is EXTRACTION_MODE. */
6651 if (inner_mode != wanted_inner_mode
6652 && (mode_dependent_address_p (XEXP (inner, 0))
6653 || MEM_VOLATILE_P (inner)
6655 wanted_inner_mode = extraction_mode;
6660 if (BITS_BIG_ENDIAN)
6662 /* POS is passed as if BITS_BIG_ENDIAN == 0, so we need to convert it to
6663 BITS_BIG_ENDIAN style. If position is constant, compute new
6664 position. Otherwise, build subtraction.
6665 Note that POS is relative to the mode of the original argument.
6666 If it's a MEM we need to recompute POS relative to that.
6667 However, if we're extracting from (or inserting into) a register,
6668 we want to recompute POS relative to wanted_inner_mode. */
6669 int width = (MEM_P (inner)
6670 ? GET_MODE_BITSIZE (is_mode)
6671 : GET_MODE_BITSIZE (wanted_inner_mode));
6674 pos = width - len - pos;
6677 = gen_rtx_MINUS (GET_MODE (pos_rtx), GEN_INT (width - len), pos_rtx);
6678 /* POS may be less than 0 now, but we check for that below.
6679 Note that it can only be less than 0 if !MEM_P (inner). */
6682 /* If INNER has a wider mode, and this is a constant extraction, try to
6683 make it smaller and adjust the byte to point to the byte containing
6685 if (wanted_inner_mode != VOIDmode
6686 && inner_mode != wanted_inner_mode
6688 && GET_MODE_SIZE (wanted_inner_mode) < GET_MODE_SIZE (is_mode)
6690 && ! mode_dependent_address_p (XEXP (inner, 0))
6691 && ! MEM_VOLATILE_P (inner))
6695 /* The computations below will be correct if the machine is big
6696 endian in both bits and bytes or little endian in bits and bytes.
6697 If it is mixed, we must adjust. */
6699 /* If bytes are big endian and we had a paradoxical SUBREG, we must
6700 adjust OFFSET to compensate. */
6701 if (BYTES_BIG_ENDIAN
6702 && GET_MODE_SIZE (inner_mode) < GET_MODE_SIZE (is_mode))
6703 offset -= GET_MODE_SIZE (is_mode) - GET_MODE_SIZE (inner_mode);
6705 /* We can now move to the desired byte. */
6706 offset += (pos / GET_MODE_BITSIZE (wanted_inner_mode))
6707 * GET_MODE_SIZE (wanted_inner_mode);
6708 pos %= GET_MODE_BITSIZE (wanted_inner_mode);
6710 if (BYTES_BIG_ENDIAN != BITS_BIG_ENDIAN
6711 && is_mode != wanted_inner_mode)
6712 offset = (GET_MODE_SIZE (is_mode)
6713 - GET_MODE_SIZE (wanted_inner_mode) - offset);
6715 inner = adjust_address_nv (inner, wanted_inner_mode, offset);
6718 /* If INNER is not memory, we can always get it into the proper mode. If we
6719 are changing its mode, POS must be a constant and smaller than the size
6721 else if (!MEM_P (inner))
6723 if (GET_MODE (inner) != wanted_inner_mode
6725 || orig_pos + len > GET_MODE_BITSIZE (wanted_inner_mode)))
6731 inner = force_to_mode (inner, wanted_inner_mode,
6733 || len + orig_pos >= HOST_BITS_PER_WIDE_INT
6734 ? ~(unsigned HOST_WIDE_INT) 0
6735 : ((((unsigned HOST_WIDE_INT) 1 << len) - 1)
6740 /* Adjust mode of POS_RTX, if needed. If we want a wider mode, we
6741 have to zero extend. Otherwise, we can just use a SUBREG. */
6743 && GET_MODE_SIZE (pos_mode) > GET_MODE_SIZE (GET_MODE (pos_rtx)))
6745 rtx temp = gen_rtx_ZERO_EXTEND (pos_mode, pos_rtx);
6747 /* If we know that no extraneous bits are set, and that the high
6748 bit is not set, convert extraction to cheaper one - either
6749 SIGN_EXTENSION or ZERO_EXTENSION, that are equivalent in these
6751 if (flag_expensive_optimizations
6752 && (GET_MODE_BITSIZE (GET_MODE (pos_rtx)) <= HOST_BITS_PER_WIDE_INT
6753 && ((nonzero_bits (pos_rtx, GET_MODE (pos_rtx))
6754 & ~(((unsigned HOST_WIDE_INT)
6755 GET_MODE_MASK (GET_MODE (pos_rtx)))
6759 rtx temp1 = gen_rtx_SIGN_EXTEND (pos_mode, pos_rtx);
6761 /* Prefer ZERO_EXTENSION, since it gives more information to
6763 if (rtx_cost (temp1, SET) < rtx_cost (temp, SET))
6768 else if (pos_rtx != 0
6769 && GET_MODE_SIZE (pos_mode) < GET_MODE_SIZE (GET_MODE (pos_rtx)))
6770 pos_rtx = gen_lowpart (pos_mode, pos_rtx);
6772 /* Make POS_RTX unless we already have it and it is correct. If we don't
6773 have a POS_RTX but we do have an ORIG_POS_RTX, the latter must
6775 if (pos_rtx == 0 && orig_pos_rtx != 0 && INTVAL (orig_pos_rtx) == pos)
6776 pos_rtx = orig_pos_rtx;
6778 else if (pos_rtx == 0)
6779 pos_rtx = GEN_INT (pos);
6781 /* Make the required operation. See if we can use existing rtx. */
6782 new = gen_rtx_fmt_eee (unsignedp ? ZERO_EXTRACT : SIGN_EXTRACT,
6783 extraction_mode, inner, GEN_INT (len), pos_rtx);
6785 new = gen_lowpart (mode, new);
6790 /* See if X contains an ASHIFT of COUNT or more bits that can be commuted
6791 with any other operations in X. Return X without that shift if so. */
6794 extract_left_shift (rtx x, int count)
6796 enum rtx_code code = GET_CODE (x);
6797 enum machine_mode mode = GET_MODE (x);
6803 /* This is the shift itself. If it is wide enough, we will return
6804 either the value being shifted if the shift count is equal to
6805 COUNT or a shift for the difference. */
6806 if (GET_CODE (XEXP (x, 1)) == CONST_INT
6807 && INTVAL (XEXP (x, 1)) >= count)
6808 return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (x, 0),
6809 INTVAL (XEXP (x, 1)) - count);
6813 if ((tem = extract_left_shift (XEXP (x, 0), count)) != 0)
6814 return simplify_gen_unary (code, mode, tem, mode);
6818 case PLUS: case IOR: case XOR: case AND:
6819 /* If we can safely shift this constant and we find the inner shift,
6820 make a new operation. */
6821 if (GET_CODE (XEXP (x, 1)) == CONST_INT
6822 && (INTVAL (XEXP (x, 1)) & ((((HOST_WIDE_INT) 1 << count)) - 1)) == 0
6823 && (tem = extract_left_shift (XEXP (x, 0), count)) != 0)
6824 return simplify_gen_binary (code, mode, tem,
6825 GEN_INT (INTVAL (XEXP (x, 1)) >> count));
6836 /* Look at the expression rooted at X. Look for expressions
6837 equivalent to ZERO_EXTRACT, SIGN_EXTRACT, ZERO_EXTEND, SIGN_EXTEND.
6838 Form these expressions.
6840 Return the new rtx, usually just X.
6842 Also, for machines like the VAX that don't have logical shift insns,
6843 try to convert logical to arithmetic shift operations in cases where
6844 they are equivalent. This undoes the canonicalizations to logical
6845 shifts done elsewhere.
6847 We try, as much as possible, to re-use rtl expressions to save memory.
6849 IN_CODE says what kind of expression we are processing. Normally, it is
6850 SET. In a memory address (inside a MEM, PLUS or minus, the latter two
6851 being kludges), it is MEM. When processing the arguments of a comparison
6852 or a COMPARE against zero, it is COMPARE. */
6855 make_compound_operation (rtx x, enum rtx_code in_code)
6857 enum rtx_code code = GET_CODE (x);
6858 enum machine_mode mode = GET_MODE (x);
6859 int mode_width = GET_MODE_BITSIZE (mode);
6861 enum rtx_code next_code;
6867 /* Select the code to be used in recursive calls. Once we are inside an
6868 address, we stay there. If we have a comparison, set to COMPARE,
6869 but once inside, go back to our default of SET. */
6871 next_code = (code == MEM || code == PLUS || code == MINUS ? MEM
6872 : ((code == COMPARE || COMPARISON_P (x))
6873 && XEXP (x, 1) == const0_rtx) ? COMPARE
6874 : in_code == COMPARE ? SET : in_code);
6876 /* Process depending on the code of this operation. If NEW is set
6877 nonzero, it will be returned. */
6882 /* Convert shifts by constants into multiplications if inside
6884 if (in_code == MEM && GET_CODE (XEXP (x, 1)) == CONST_INT
6885 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT
6886 && INTVAL (XEXP (x, 1)) >= 0)
6888 new = make_compound_operation (XEXP (x, 0), next_code);
6889 new = gen_rtx_MULT (mode, new,
6890 GEN_INT ((HOST_WIDE_INT) 1
6891 << INTVAL (XEXP (x, 1))));
6896 /* If the second operand is not a constant, we can't do anything
6898 if (GET_CODE (XEXP (x, 1)) != CONST_INT)
6901 /* If the constant is a power of two minus one and the first operand
6902 is a logical right shift, make an extraction. */
6903 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
6904 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6906 new = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code);
6907 new = make_extraction (mode, new, 0, XEXP (XEXP (x, 0), 1), i, 1,
6908 0, in_code == COMPARE);
6911 /* Same as previous, but for (subreg (lshiftrt ...)) in first op. */
6912 else if (GET_CODE (XEXP (x, 0)) == SUBREG
6913 && subreg_lowpart_p (XEXP (x, 0))
6914 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == LSHIFTRT
6915 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6917 new = make_compound_operation (XEXP (SUBREG_REG (XEXP (x, 0)), 0),
6919 new = make_extraction (GET_MODE (SUBREG_REG (XEXP (x, 0))), new, 0,
6920 XEXP (SUBREG_REG (XEXP (x, 0)), 1), i, 1,
6921 0, in_code == COMPARE);
6923 /* Same as previous, but for (xor/ior (lshiftrt...) (lshiftrt...)). */
6924 else if ((GET_CODE (XEXP (x, 0)) == XOR
6925 || GET_CODE (XEXP (x, 0)) == IOR)
6926 && GET_CODE (XEXP (XEXP (x, 0), 0)) == LSHIFTRT
6927 && GET_CODE (XEXP (XEXP (x, 0), 1)) == LSHIFTRT
6928 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6930 /* Apply the distributive law, and then try to make extractions. */
6931 new = gen_rtx_fmt_ee (GET_CODE (XEXP (x, 0)), mode,
6932 gen_rtx_AND (mode, XEXP (XEXP (x, 0), 0),
6934 gen_rtx_AND (mode, XEXP (XEXP (x, 0), 1),
6936 new = make_compound_operation (new, in_code);
6939 /* If we are have (and (rotate X C) M) and C is larger than the number
6940 of bits in M, this is an extraction. */
6942 else if (GET_CODE (XEXP (x, 0)) == ROTATE
6943 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
6944 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0
6945 && i <= INTVAL (XEXP (XEXP (x, 0), 1)))
6947 new = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code);
6948 new = make_extraction (mode, new,
6949 (GET_MODE_BITSIZE (mode)
6950 - INTVAL (XEXP (XEXP (x, 0), 1))),
6951 NULL_RTX, i, 1, 0, in_code == COMPARE);
6954 /* On machines without logical shifts, if the operand of the AND is
6955 a logical shift and our mask turns off all the propagated sign
6956 bits, we can replace the logical shift with an arithmetic shift. */
6957 else if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
6958 && !have_insn_for (LSHIFTRT, mode)
6959 && have_insn_for (ASHIFTRT, mode)
6960 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
6961 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
6962 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT
6963 && mode_width <= HOST_BITS_PER_WIDE_INT)
6965 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
6967 mask >>= INTVAL (XEXP (XEXP (x, 0), 1));
6968 if ((INTVAL (XEXP (x, 1)) & ~mask) == 0)
6970 gen_rtx_ASHIFTRT (mode,
6971 make_compound_operation
6972 (XEXP (XEXP (x, 0), 0), next_code),
6973 XEXP (XEXP (x, 0), 1)));
6976 /* If the constant is one less than a power of two, this might be
6977 representable by an extraction even if no shift is present.
6978 If it doesn't end up being a ZERO_EXTEND, we will ignore it unless
6979 we are in a COMPARE. */
6980 else if ((i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6981 new = make_extraction (mode,
6982 make_compound_operation (XEXP (x, 0),
6984 0, NULL_RTX, i, 1, 0, in_code == COMPARE);
6986 /* If we are in a comparison and this is an AND with a power of two,
6987 convert this into the appropriate bit extract. */
6988 else if (in_code == COMPARE
6989 && (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0)
6990 new = make_extraction (mode,
6991 make_compound_operation (XEXP (x, 0),
6993 i, NULL_RTX, 1, 1, 0, 1);
6998 /* If the sign bit is known to be zero, replace this with an
6999 arithmetic shift. */
7000 if (have_insn_for (ASHIFTRT, mode)
7001 && ! have_insn_for (LSHIFTRT, mode)
7002 && mode_width <= HOST_BITS_PER_WIDE_INT
7003 && (nonzero_bits (XEXP (x, 0), mode) & (1 << (mode_width - 1))) == 0)
7005 new = gen_rtx_ASHIFTRT (mode,
7006 make_compound_operation (XEXP (x, 0),
7012 /* ... fall through ... */
7018 /* If we have (ashiftrt (ashift foo C1) C2) with C2 >= C1,
7019 this is a SIGN_EXTRACT. */
7020 if (GET_CODE (rhs) == CONST_INT
7021 && GET_CODE (lhs) == ASHIFT
7022 && GET_CODE (XEXP (lhs, 1)) == CONST_INT
7023 && INTVAL (rhs) >= INTVAL (XEXP (lhs, 1)))
7025 new = make_compound_operation (XEXP (lhs, 0), next_code);
7026 new = make_extraction (mode, new,
7027 INTVAL (rhs) - INTVAL (XEXP (lhs, 1)),
7028 NULL_RTX, mode_width - INTVAL (rhs),
7029 code == LSHIFTRT, 0, in_code == COMPARE);
7033 /* See if we have operations between an ASHIFTRT and an ASHIFT.
7034 If so, try to merge the shifts into a SIGN_EXTEND. We could
7035 also do this for some cases of SIGN_EXTRACT, but it doesn't
7036 seem worth the effort; the case checked for occurs on Alpha. */
7039 && ! (GET_CODE (lhs) == SUBREG
7040 && (OBJECT_P (SUBREG_REG (lhs))))
7041 && GET_CODE (rhs) == CONST_INT
7042 && INTVAL (rhs) < HOST_BITS_PER_WIDE_INT
7043 && (new = extract_left_shift (lhs, INTVAL (rhs))) != 0)
7044 new = make_extraction (mode, make_compound_operation (new, next_code),
7045 0, NULL_RTX, mode_width - INTVAL (rhs),
7046 code == LSHIFTRT, 0, in_code == COMPARE);
7051 /* Call ourselves recursively on the inner expression. If we are
7052 narrowing the object and it has a different RTL code from
7053 what it originally did, do this SUBREG as a force_to_mode. */
7055 tem = make_compound_operation (SUBREG_REG (x), in_code);
7059 simplified = simplify_subreg (GET_MODE (x), tem, GET_MODE (tem),
7065 if (GET_CODE (tem) != GET_CODE (SUBREG_REG (x))
7066 && GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (tem))
7067 && subreg_lowpart_p (x))
7069 rtx newer = force_to_mode (tem, mode, ~(HOST_WIDE_INT) 0,
7072 /* If we have something other than a SUBREG, we might have
7073 done an expansion, so rerun ourselves. */
7074 if (GET_CODE (newer) != SUBREG)
7075 newer = make_compound_operation (newer, in_code);
7091 x = gen_lowpart (mode, new);
7092 code = GET_CODE (x);
7095 /* Now recursively process each operand of this operation. */
7096 fmt = GET_RTX_FORMAT (code);
7097 for (i = 0; i < GET_RTX_LENGTH (code); i++)
7100 new = make_compound_operation (XEXP (x, i), next_code);
7101 SUBST (XEXP (x, i), new);
7104 /* If this is a commutative operation, the changes to the operands
7105 may have made it noncanonical. */
7106 if (COMMUTATIVE_ARITH_P (x)
7107 && swap_commutative_operands_p (XEXP (x, 0), XEXP (x, 1)))
7110 SUBST (XEXP (x, 0), XEXP (x, 1));
7111 SUBST (XEXP (x, 1), tem);
7117 /* Given M see if it is a value that would select a field of bits
7118 within an item, but not the entire word. Return -1 if not.
7119 Otherwise, return the starting position of the field, where 0 is the
7122 *PLEN is set to the length of the field. */
7125 get_pos_from_mask (unsigned HOST_WIDE_INT m, unsigned HOST_WIDE_INT *plen)
7127 /* Get the bit number of the first 1 bit from the right, -1 if none. */
7128 int pos = exact_log2 (m & -m);
7132 /* Now shift off the low-order zero bits and see if we have a
7133 power of two minus 1. */
7134 len = exact_log2 ((m >> pos) + 1);
7143 /* If X refers to a register that equals REG in value, replace these
7144 references with REG. */
7146 canon_reg_for_combine (rtx x, rtx reg)
7153 enum rtx_code code = GET_CODE (x);
7154 switch (GET_RTX_CLASS (code))
7157 op0 = canon_reg_for_combine (XEXP (x, 0), reg);
7158 if (op0 != XEXP (x, 0))
7159 return simplify_gen_unary (GET_CODE (x), GET_MODE (x), op0,
7164 case RTX_COMM_ARITH:
7165 op0 = canon_reg_for_combine (XEXP (x, 0), reg);
7166 op1 = canon_reg_for_combine (XEXP (x, 1), reg);
7167 if (op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
7168 return simplify_gen_binary (GET_CODE (x), GET_MODE (x), op0, op1);
7172 case RTX_COMM_COMPARE:
7173 op0 = canon_reg_for_combine (XEXP (x, 0), reg);
7174 op1 = canon_reg_for_combine (XEXP (x, 1), reg);
7175 if (op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
7176 return simplify_gen_relational (GET_CODE (x), GET_MODE (x),
7177 GET_MODE (op0), op0, op1);
7181 case RTX_BITFIELD_OPS:
7182 op0 = canon_reg_for_combine (XEXP (x, 0), reg);
7183 op1 = canon_reg_for_combine (XEXP (x, 1), reg);
7184 op2 = canon_reg_for_combine (XEXP (x, 2), reg);
7185 if (op0 != XEXP (x, 0) || op1 != XEXP (x, 1) || op2 != XEXP (x, 2))
7186 return simplify_gen_ternary (GET_CODE (x), GET_MODE (x),
7187 GET_MODE (op0), op0, op1, op2);
7192 if (rtx_equal_p (get_last_value (reg), x)
7193 || rtx_equal_p (reg, get_last_value (x)))
7202 fmt = GET_RTX_FORMAT (code);
7204 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
7207 rtx op = canon_reg_for_combine (XEXP (x, i), reg);
7208 if (op != XEXP (x, i))
7218 else if (fmt[i] == 'E')
7221 for (j = 0; j < XVECLEN (x, i); j++)
7223 rtx op = canon_reg_for_combine (XVECEXP (x, i, j), reg);
7224 if (op != XVECEXP (x, i, j))
7231 XVECEXP (x, i, j) = op;
7242 /* Return X converted to MODE. If the value is already truncated to
7243 MODE we can just return a subreg even though in the general case we
7244 would need an explicit truncation. */
7247 gen_lowpart_or_truncate (enum machine_mode mode, rtx x)
7249 if (GET_MODE_SIZE (GET_MODE (x)) <= GET_MODE_SIZE (mode)
7250 || TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode),
7251 GET_MODE_BITSIZE (GET_MODE (x)))
7252 || (REG_P (x) && reg_truncated_to_mode (mode, x)))
7253 return gen_lowpart (mode, x);
7255 return simplify_gen_unary (TRUNCATE, mode, x, GET_MODE (x));
7258 /* See if X can be simplified knowing that we will only refer to it in
7259 MODE and will only refer to those bits that are nonzero in MASK.
7260 If other bits are being computed or if masking operations are done
7261 that select a superset of the bits in MASK, they can sometimes be
7264 Return a possibly simplified expression, but always convert X to
7265 MODE. If X is a CONST_INT, AND the CONST_INT with MASK.
7267 If JUST_SELECT is nonzero, don't optimize by noticing that bits in MASK
7268 are all off in X. This is used when X will be complemented, by either
7269 NOT, NEG, or XOR. */
7272 force_to_mode (rtx x, enum machine_mode mode, unsigned HOST_WIDE_INT mask,
7275 enum rtx_code code = GET_CODE (x);
7276 int next_select = just_select || code == XOR || code == NOT || code == NEG;
7277 enum machine_mode op_mode;
7278 unsigned HOST_WIDE_INT fuller_mask, nonzero;
7281 /* If this is a CALL or ASM_OPERANDS, don't do anything. Some of the
7282 code below will do the wrong thing since the mode of such an
7283 expression is VOIDmode.
7285 Also do nothing if X is a CLOBBER; this can happen if X was
7286 the return value from a call to gen_lowpart. */
7287 if (code == CALL || code == ASM_OPERANDS || code == CLOBBER)
7290 /* We want to perform the operation is its present mode unless we know
7291 that the operation is valid in MODE, in which case we do the operation
7293 op_mode = ((GET_MODE_CLASS (mode) == GET_MODE_CLASS (GET_MODE (x))
7294 && have_insn_for (code, mode))
7295 ? mode : GET_MODE (x));
7297 /* It is not valid to do a right-shift in a narrower mode
7298 than the one it came in with. */
7299 if ((code == LSHIFTRT || code == ASHIFTRT)
7300 && GET_MODE_BITSIZE (mode) < GET_MODE_BITSIZE (GET_MODE (x)))
7301 op_mode = GET_MODE (x);
7303 /* Truncate MASK to fit OP_MODE. */
7305 mask &= GET_MODE_MASK (op_mode);
7307 /* When we have an arithmetic operation, or a shift whose count we
7308 do not know, we need to assume that all bits up to the highest-order
7309 bit in MASK will be needed. This is how we form such a mask. */
7310 if (mask & ((unsigned HOST_WIDE_INT) 1 << (HOST_BITS_PER_WIDE_INT - 1)))
7311 fuller_mask = ~(unsigned HOST_WIDE_INT) 0;
7313 fuller_mask = (((unsigned HOST_WIDE_INT) 1 << (floor_log2 (mask) + 1))
7316 /* Determine what bits of X are guaranteed to be (non)zero. */
7317 nonzero = nonzero_bits (x, mode);
7319 /* If none of the bits in X are needed, return a zero. */
7320 if (!just_select && (nonzero & mask) == 0 && !side_effects_p (x))
7323 /* If X is a CONST_INT, return a new one. Do this here since the
7324 test below will fail. */
7325 if (GET_CODE (x) == CONST_INT)
7327 if (SCALAR_INT_MODE_P (mode))
7328 return gen_int_mode (INTVAL (x) & mask, mode);
7331 x = GEN_INT (INTVAL (x) & mask);
7332 return gen_lowpart_common (mode, x);
7336 /* If X is narrower than MODE and we want all the bits in X's mode, just
7337 get X in the proper mode. */
7338 if (GET_MODE_SIZE (GET_MODE (x)) < GET_MODE_SIZE (mode)
7339 && (GET_MODE_MASK (GET_MODE (x)) & ~mask) == 0)
7340 return gen_lowpart (mode, x);
7345 /* If X is a (clobber (const_int)), return it since we know we are
7346 generating something that won't match. */
7353 x = expand_compound_operation (x);
7354 if (GET_CODE (x) != code)
7355 return force_to_mode (x, mode, mask, next_select);
7359 if (subreg_lowpart_p (x)
7360 /* We can ignore the effect of this SUBREG if it narrows the mode or
7361 if the constant masks to zero all the bits the mode doesn't
7363 && ((GET_MODE_SIZE (GET_MODE (x))
7364 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
7366 & GET_MODE_MASK (GET_MODE (x))
7367 & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (x)))))))
7368 return force_to_mode (SUBREG_REG (x), mode, mask, next_select);
7372 /* If this is an AND with a constant, convert it into an AND
7373 whose constant is the AND of that constant with MASK. If it
7374 remains an AND of MASK, delete it since it is redundant. */
7376 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
7378 x = simplify_and_const_int (x, op_mode, XEXP (x, 0),
7379 mask & INTVAL (XEXP (x, 1)));
7381 /* If X is still an AND, see if it is an AND with a mask that
7382 is just some low-order bits. If so, and it is MASK, we don't
7385 if (GET_CODE (x) == AND && GET_CODE (XEXP (x, 1)) == CONST_INT
7386 && ((INTVAL (XEXP (x, 1)) & GET_MODE_MASK (GET_MODE (x)))
7390 /* If it remains an AND, try making another AND with the bits
7391 in the mode mask that aren't in MASK turned on. If the
7392 constant in the AND is wide enough, this might make a
7393 cheaper constant. */
7395 if (GET_CODE (x) == AND && GET_CODE (XEXP (x, 1)) == CONST_INT
7396 && GET_MODE_MASK (GET_MODE (x)) != mask
7397 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT)
7399 HOST_WIDE_INT cval = (INTVAL (XEXP (x, 1))
7400 | (GET_MODE_MASK (GET_MODE (x)) & ~mask));
7401 int width = GET_MODE_BITSIZE (GET_MODE (x));
7404 /* If MODE is narrower than HOST_WIDE_INT and CVAL is a negative
7405 number, sign extend it. */
7406 if (width > 0 && width < HOST_BITS_PER_WIDE_INT
7407 && (cval & ((HOST_WIDE_INT) 1 << (width - 1))) != 0)
7408 cval |= (HOST_WIDE_INT) -1 << width;
7410 y = simplify_gen_binary (AND, GET_MODE (x),
7411 XEXP (x, 0), GEN_INT (cval));
7412 if (rtx_cost (y, SET) < rtx_cost (x, SET))
7422 /* In (and (plus FOO C1) M), if M is a mask that just turns off
7423 low-order bits (as in an alignment operation) and FOO is already
7424 aligned to that boundary, mask C1 to that boundary as well.
7425 This may eliminate that PLUS and, later, the AND. */
7428 unsigned int width = GET_MODE_BITSIZE (mode);
7429 unsigned HOST_WIDE_INT smask = mask;
7431 /* If MODE is narrower than HOST_WIDE_INT and mask is a negative
7432 number, sign extend it. */
7434 if (width < HOST_BITS_PER_WIDE_INT
7435 && (smask & ((HOST_WIDE_INT) 1 << (width - 1))) != 0)
7436 smask |= (HOST_WIDE_INT) -1 << width;
7438 if (GET_CODE (XEXP (x, 1)) == CONST_INT
7439 && exact_log2 (- smask) >= 0
7440 && (nonzero_bits (XEXP (x, 0), mode) & ~smask) == 0
7441 && (INTVAL (XEXP (x, 1)) & ~smask) != 0)
7442 return force_to_mode (plus_constant (XEXP (x, 0),
7443 (INTVAL (XEXP (x, 1)) & smask)),
7444 mode, smask, next_select);
7447 /* ... fall through ... */
7450 /* For PLUS, MINUS and MULT, we need any bits less significant than the
7451 most significant bit in MASK since carries from those bits will
7452 affect the bits we are interested in. */
7457 /* If X is (minus C Y) where C's least set bit is larger than any bit
7458 in the mask, then we may replace with (neg Y). */
7459 if (GET_CODE (XEXP (x, 0)) == CONST_INT
7460 && (((unsigned HOST_WIDE_INT) (INTVAL (XEXP (x, 0))
7461 & -INTVAL (XEXP (x, 0))))
7464 x = simplify_gen_unary (NEG, GET_MODE (x), XEXP (x, 1),
7466 return force_to_mode (x, mode, mask, next_select);
7469 /* Similarly, if C contains every bit in the fuller_mask, then we may
7470 replace with (not Y). */
7471 if (GET_CODE (XEXP (x, 0)) == CONST_INT
7472 && ((INTVAL (XEXP (x, 0)) | (HOST_WIDE_INT) fuller_mask)
7473 == INTVAL (XEXP (x, 0))))
7475 x = simplify_gen_unary (NOT, GET_MODE (x),
7476 XEXP (x, 1), GET_MODE (x));
7477 return force_to_mode (x, mode, mask, next_select);
7485 /* If X is (ior (lshiftrt FOO C1) C2), try to commute the IOR and
7486 LSHIFTRT so we end up with an (and (lshiftrt (ior ...) ...) ...)
7487 operation which may be a bitfield extraction. Ensure that the
7488 constant we form is not wider than the mode of X. */
7490 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
7491 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
7492 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
7493 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT
7494 && GET_CODE (XEXP (x, 1)) == CONST_INT
7495 && ((INTVAL (XEXP (XEXP (x, 0), 1))
7496 + floor_log2 (INTVAL (XEXP (x, 1))))
7497 < GET_MODE_BITSIZE (GET_MODE (x)))
7498 && (INTVAL (XEXP (x, 1))
7499 & ~nonzero_bits (XEXP (x, 0), GET_MODE (x))) == 0)
7501 temp = GEN_INT ((INTVAL (XEXP (x, 1)) & mask)
7502 << INTVAL (XEXP (XEXP (x, 0), 1)));
7503 temp = simplify_gen_binary (GET_CODE (x), GET_MODE (x),
7504 XEXP (XEXP (x, 0), 0), temp);
7505 x = simplify_gen_binary (LSHIFTRT, GET_MODE (x), temp,
7506 XEXP (XEXP (x, 0), 1));
7507 return force_to_mode (x, mode, mask, next_select);
7511 /* For most binary operations, just propagate into the operation and
7512 change the mode if we have an operation of that mode. */
7514 op0 = gen_lowpart_or_truncate (op_mode,
7515 force_to_mode (XEXP (x, 0), mode, mask,
7517 op1 = gen_lowpart_or_truncate (op_mode,
7518 force_to_mode (XEXP (x, 1), mode, mask,
7521 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
7522 x = simplify_gen_binary (code, op_mode, op0, op1);
7526 /* For left shifts, do the same, but just for the first operand.
7527 However, we cannot do anything with shifts where we cannot
7528 guarantee that the counts are smaller than the size of the mode
7529 because such a count will have a different meaning in a
7532 if (! (GET_CODE (XEXP (x, 1)) == CONST_INT
7533 && INTVAL (XEXP (x, 1)) >= 0
7534 && INTVAL (XEXP (x, 1)) < GET_MODE_BITSIZE (mode))
7535 && ! (GET_MODE (XEXP (x, 1)) != VOIDmode
7536 && (nonzero_bits (XEXP (x, 1), GET_MODE (XEXP (x, 1)))
7537 < (unsigned HOST_WIDE_INT) GET_MODE_BITSIZE (mode))))
7540 /* If the shift count is a constant and we can do arithmetic in
7541 the mode of the shift, refine which bits we need. Otherwise, use the
7542 conservative form of the mask. */
7543 if (GET_CODE (XEXP (x, 1)) == CONST_INT
7544 && INTVAL (XEXP (x, 1)) >= 0
7545 && INTVAL (XEXP (x, 1)) < GET_MODE_BITSIZE (op_mode)
7546 && GET_MODE_BITSIZE (op_mode) <= HOST_BITS_PER_WIDE_INT)
7547 mask >>= INTVAL (XEXP (x, 1));
7551 op0 = gen_lowpart_or_truncate (op_mode,
7552 force_to_mode (XEXP (x, 0), op_mode,
7553 mask, next_select));
7555 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0))
7556 x = simplify_gen_binary (code, op_mode, op0, XEXP (x, 1));
7560 /* Here we can only do something if the shift count is a constant,
7561 this shift constant is valid for the host, and we can do arithmetic
7564 if (GET_CODE (XEXP (x, 1)) == CONST_INT
7565 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT
7566 && GET_MODE_BITSIZE (op_mode) <= HOST_BITS_PER_WIDE_INT)
7568 rtx inner = XEXP (x, 0);
7569 unsigned HOST_WIDE_INT inner_mask;
7571 /* Select the mask of the bits we need for the shift operand. */
7572 inner_mask = mask << INTVAL (XEXP (x, 1));
7574 /* We can only change the mode of the shift if we can do arithmetic
7575 in the mode of the shift and INNER_MASK is no wider than the
7576 width of X's mode. */
7577 if ((inner_mask & ~GET_MODE_MASK (GET_MODE (x))) != 0)
7578 op_mode = GET_MODE (x);
7580 inner = force_to_mode (inner, op_mode, inner_mask, next_select);
7582 if (GET_MODE (x) != op_mode || inner != XEXP (x, 0))
7583 x = simplify_gen_binary (LSHIFTRT, op_mode, inner, XEXP (x, 1));
7586 /* If we have (and (lshiftrt FOO C1) C2) where the combination of the
7587 shift and AND produces only copies of the sign bit (C2 is one less
7588 than a power of two), we can do this with just a shift. */
7590 if (GET_CODE (x) == LSHIFTRT
7591 && GET_CODE (XEXP (x, 1)) == CONST_INT
7592 /* The shift puts one of the sign bit copies in the least significant
7594 && ((INTVAL (XEXP (x, 1))
7595 + num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0))))
7596 >= GET_MODE_BITSIZE (GET_MODE (x)))
7597 && exact_log2 (mask + 1) >= 0
7598 /* Number of bits left after the shift must be more than the mask
7600 && ((INTVAL (XEXP (x, 1)) + exact_log2 (mask + 1))
7601 <= GET_MODE_BITSIZE (GET_MODE (x)))
7602 /* Must be more sign bit copies than the mask needs. */
7603 && ((int) num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
7604 >= exact_log2 (mask + 1)))
7605 x = simplify_gen_binary (LSHIFTRT, GET_MODE (x), XEXP (x, 0),
7606 GEN_INT (GET_MODE_BITSIZE (GET_MODE (x))
7607 - exact_log2 (mask + 1)));
7612 /* If we are just looking for the sign bit, we don't need this shift at
7613 all, even if it has a variable count. */
7614 if (GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
7615 && (mask == ((unsigned HOST_WIDE_INT) 1
7616 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
7617 return force_to_mode (XEXP (x, 0), mode, mask, next_select);
7619 /* If this is a shift by a constant, get a mask that contains those bits
7620 that are not copies of the sign bit. We then have two cases: If
7621 MASK only includes those bits, this can be a logical shift, which may
7622 allow simplifications. If MASK is a single-bit field not within
7623 those bits, we are requesting a copy of the sign bit and hence can
7624 shift the sign bit to the appropriate location. */
7626 if (GET_CODE (XEXP (x, 1)) == CONST_INT && INTVAL (XEXP (x, 1)) >= 0
7627 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT)
7631 /* If the considered data is wider than HOST_WIDE_INT, we can't
7632 represent a mask for all its bits in a single scalar.
7633 But we only care about the lower bits, so calculate these. */
7635 if (GET_MODE_BITSIZE (GET_MODE (x)) > HOST_BITS_PER_WIDE_INT)
7637 nonzero = ~(HOST_WIDE_INT) 0;
7639 /* GET_MODE_BITSIZE (GET_MODE (x)) - INTVAL (XEXP (x, 1))
7640 is the number of bits a full-width mask would have set.
7641 We need only shift if these are fewer than nonzero can
7642 hold. If not, we must keep all bits set in nonzero. */
7644 if (GET_MODE_BITSIZE (GET_MODE (x)) - INTVAL (XEXP (x, 1))
7645 < HOST_BITS_PER_WIDE_INT)
7646 nonzero >>= INTVAL (XEXP (x, 1))
7647 + HOST_BITS_PER_WIDE_INT
7648 - GET_MODE_BITSIZE (GET_MODE (x)) ;
7652 nonzero = GET_MODE_MASK (GET_MODE (x));
7653 nonzero >>= INTVAL (XEXP (x, 1));
7656 if ((mask & ~nonzero) == 0)
7658 x = simplify_shift_const (NULL_RTX, LSHIFTRT, GET_MODE (x),
7659 XEXP (x, 0), INTVAL (XEXP (x, 1)));
7660 if (GET_CODE (x) != ASHIFTRT)
7661 return force_to_mode (x, mode, mask, next_select);
7664 else if ((i = exact_log2 (mask)) >= 0)
7666 x = simplify_shift_const
7667 (NULL_RTX, LSHIFTRT, GET_MODE (x), XEXP (x, 0),
7668 GET_MODE_BITSIZE (GET_MODE (x)) - 1 - i);
7670 if (GET_CODE (x) != ASHIFTRT)
7671 return force_to_mode (x, mode, mask, next_select);
7675 /* If MASK is 1, convert this to an LSHIFTRT. This can be done
7676 even if the shift count isn't a constant. */
7678 x = simplify_gen_binary (LSHIFTRT, GET_MODE (x),
7679 XEXP (x, 0), XEXP (x, 1));
7683 /* If this is a zero- or sign-extension operation that just affects bits
7684 we don't care about, remove it. Be sure the call above returned
7685 something that is still a shift. */
7687 if ((GET_CODE (x) == LSHIFTRT || GET_CODE (x) == ASHIFTRT)
7688 && GET_CODE (XEXP (x, 1)) == CONST_INT
7689 && INTVAL (XEXP (x, 1)) >= 0
7690 && (INTVAL (XEXP (x, 1))
7691 <= GET_MODE_BITSIZE (GET_MODE (x)) - (floor_log2 (mask) + 1))
7692 && GET_CODE (XEXP (x, 0)) == ASHIFT
7693 && XEXP (XEXP (x, 0), 1) == XEXP (x, 1))
7694 return force_to_mode (XEXP (XEXP (x, 0), 0), mode, mask,
7701 /* If the shift count is constant and we can do computations
7702 in the mode of X, compute where the bits we care about are.
7703 Otherwise, we can't do anything. Don't change the mode of
7704 the shift or propagate MODE into the shift, though. */
7705 if (GET_CODE (XEXP (x, 1)) == CONST_INT
7706 && INTVAL (XEXP (x, 1)) >= 0)
7708 temp = simplify_binary_operation (code == ROTATE ? ROTATERT : ROTATE,
7709 GET_MODE (x), GEN_INT (mask),
7711 if (temp && GET_CODE (temp) == CONST_INT)
7713 force_to_mode (XEXP (x, 0), GET_MODE (x),
7714 INTVAL (temp), next_select));
7719 /* If we just want the low-order bit, the NEG isn't needed since it
7720 won't change the low-order bit. */
7722 return force_to_mode (XEXP (x, 0), mode, mask, just_select);
7724 /* We need any bits less significant than the most significant bit in
7725 MASK since carries from those bits will affect the bits we are
7731 /* (not FOO) is (xor FOO CONST), so if FOO is an LSHIFTRT, we can do the
7732 same as the XOR case above. Ensure that the constant we form is not
7733 wider than the mode of X. */
7735 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
7736 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
7737 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
7738 && (INTVAL (XEXP (XEXP (x, 0), 1)) + floor_log2 (mask)
7739 < GET_MODE_BITSIZE (GET_MODE (x)))
7740 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT)
7742 temp = gen_int_mode (mask << INTVAL (XEXP (XEXP (x, 0), 1)),
7744 temp = simplify_gen_binary (XOR, GET_MODE (x),
7745 XEXP (XEXP (x, 0), 0), temp);
7746 x = simplify_gen_binary (LSHIFTRT, GET_MODE (x),
7747 temp, XEXP (XEXP (x, 0), 1));
7749 return force_to_mode (x, mode, mask, next_select);
7752 /* (and (not FOO) CONST) is (not (or FOO (not CONST))), so we must
7753 use the full mask inside the NOT. */
7757 op0 = gen_lowpart_or_truncate (op_mode,
7758 force_to_mode (XEXP (x, 0), mode, mask,
7760 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0))
7761 x = simplify_gen_unary (code, op_mode, op0, op_mode);
7765 /* (and (ne FOO 0) CONST) can be (and FOO CONST) if CONST is included
7766 in STORE_FLAG_VALUE and FOO has a single bit that might be nonzero,
7767 which is equal to STORE_FLAG_VALUE. */
7768 if ((mask & ~STORE_FLAG_VALUE) == 0 && XEXP (x, 1) == const0_rtx
7769 && GET_MODE (XEXP (x, 0)) == mode
7770 && exact_log2 (nonzero_bits (XEXP (x, 0), mode)) >= 0
7771 && (nonzero_bits (XEXP (x, 0), mode)
7772 == (unsigned HOST_WIDE_INT) STORE_FLAG_VALUE))
7773 return force_to_mode (XEXP (x, 0), mode, mask, next_select);
7778 /* We have no way of knowing if the IF_THEN_ELSE can itself be
7779 written in a narrower mode. We play it safe and do not do so. */
7782 gen_lowpart_or_truncate (GET_MODE (x),
7783 force_to_mode (XEXP (x, 1), mode,
7784 mask, next_select)));
7786 gen_lowpart_or_truncate (GET_MODE (x),
7787 force_to_mode (XEXP (x, 2), mode,
7788 mask, next_select)));
7795 /* Ensure we return a value of the proper mode. */
7796 return gen_lowpart_or_truncate (mode, x);
7799 /* Return nonzero if X is an expression that has one of two values depending on
7800 whether some other value is zero or nonzero. In that case, we return the
7801 value that is being tested, *PTRUE is set to the value if the rtx being
7802 returned has a nonzero value, and *PFALSE is set to the other alternative.
7804 If we return zero, we set *PTRUE and *PFALSE to X. */
7807 if_then_else_cond (rtx x, rtx *ptrue, rtx *pfalse)
7809 enum machine_mode mode = GET_MODE (x);
7810 enum rtx_code code = GET_CODE (x);
7811 rtx cond0, cond1, true0, true1, false0, false1;
7812 unsigned HOST_WIDE_INT nz;
7814 /* If we are comparing a value against zero, we are done. */
7815 if ((code == NE || code == EQ)
7816 && XEXP (x, 1) == const0_rtx)
7818 *ptrue = (code == NE) ? const_true_rtx : const0_rtx;
7819 *pfalse = (code == NE) ? const0_rtx : const_true_rtx;
7823 /* If this is a unary operation whose operand has one of two values, apply
7824 our opcode to compute those values. */
7825 else if (UNARY_P (x)
7826 && (cond0 = if_then_else_cond (XEXP (x, 0), &true0, &false0)) != 0)
7828 *ptrue = simplify_gen_unary (code, mode, true0, GET_MODE (XEXP (x, 0)));
7829 *pfalse = simplify_gen_unary (code, mode, false0,
7830 GET_MODE (XEXP (x, 0)));
7834 /* If this is a COMPARE, do nothing, since the IF_THEN_ELSE we would
7835 make can't possibly match and would suppress other optimizations. */
7836 else if (code == COMPARE)
7839 /* If this is a binary operation, see if either side has only one of two
7840 values. If either one does or if both do and they are conditional on
7841 the same value, compute the new true and false values. */
7842 else if (BINARY_P (x))
7844 cond0 = if_then_else_cond (XEXP (x, 0), &true0, &false0);
7845 cond1 = if_then_else_cond (XEXP (x, 1), &true1, &false1);
7847 if ((cond0 != 0 || cond1 != 0)
7848 && ! (cond0 != 0 && cond1 != 0 && ! rtx_equal_p (cond0, cond1)))
7850 /* If if_then_else_cond returned zero, then true/false are the
7851 same rtl. We must copy one of them to prevent invalid rtl
7854 true0 = copy_rtx (true0);
7855 else if (cond1 == 0)
7856 true1 = copy_rtx (true1);
7858 if (COMPARISON_P (x))
7860 *ptrue = simplify_gen_relational (code, mode, VOIDmode,
7862 *pfalse = simplify_gen_relational (code, mode, VOIDmode,
7867 *ptrue = simplify_gen_binary (code, mode, true0, true1);
7868 *pfalse = simplify_gen_binary (code, mode, false0, false1);
7871 return cond0 ? cond0 : cond1;
7874 /* See if we have PLUS, IOR, XOR, MINUS or UMAX, where one of the
7875 operands is zero when the other is nonzero, and vice-versa,
7876 and STORE_FLAG_VALUE is 1 or -1. */
7878 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
7879 && (code == PLUS || code == IOR || code == XOR || code == MINUS
7881 && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT)
7883 rtx op0 = XEXP (XEXP (x, 0), 1);
7884 rtx op1 = XEXP (XEXP (x, 1), 1);
7886 cond0 = XEXP (XEXP (x, 0), 0);
7887 cond1 = XEXP (XEXP (x, 1), 0);
7889 if (COMPARISON_P (cond0)
7890 && COMPARISON_P (cond1)
7891 && ((GET_CODE (cond0) == reversed_comparison_code (cond1, NULL)
7892 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0))
7893 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1)))
7894 || ((swap_condition (GET_CODE (cond0))
7895 == reversed_comparison_code (cond1, NULL))
7896 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1))
7897 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0))))
7898 && ! side_effects_p (x))
7900 *ptrue = simplify_gen_binary (MULT, mode, op0, const_true_rtx);
7901 *pfalse = simplify_gen_binary (MULT, mode,
7903 ? simplify_gen_unary (NEG, mode,
7911 /* Similarly for MULT, AND and UMIN, except that for these the result
7913 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
7914 && (code == MULT || code == AND || code == UMIN)
7915 && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT)
7917 cond0 = XEXP (XEXP (x, 0), 0);
7918 cond1 = XEXP (XEXP (x, 1), 0);
7920 if (COMPARISON_P (cond0)
7921 && COMPARISON_P (cond1)
7922 && ((GET_CODE (cond0) == reversed_comparison_code (cond1, NULL)
7923 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0))
7924 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1)))
7925 || ((swap_condition (GET_CODE (cond0))
7926 == reversed_comparison_code (cond1, NULL))
7927 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1))
7928 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0))))
7929 && ! side_effects_p (x))
7931 *ptrue = *pfalse = const0_rtx;
7937 else if (code == IF_THEN_ELSE)
7939 /* If we have IF_THEN_ELSE already, extract the condition and
7940 canonicalize it if it is NE or EQ. */
7941 cond0 = XEXP (x, 0);
7942 *ptrue = XEXP (x, 1), *pfalse = XEXP (x, 2);
7943 if (GET_CODE (cond0) == NE && XEXP (cond0, 1) == const0_rtx)
7944 return XEXP (cond0, 0);
7945 else if (GET_CODE (cond0) == EQ && XEXP (cond0, 1) == const0_rtx)
7947 *ptrue = XEXP (x, 2), *pfalse = XEXP (x, 1);
7948 return XEXP (cond0, 0);
7954 /* If X is a SUBREG, we can narrow both the true and false values
7955 if the inner expression, if there is a condition. */
7956 else if (code == SUBREG
7957 && 0 != (cond0 = if_then_else_cond (SUBREG_REG (x),
7960 true0 = simplify_gen_subreg (mode, true0,
7961 GET_MODE (SUBREG_REG (x)), SUBREG_BYTE (x));
7962 false0 = simplify_gen_subreg (mode, false0,
7963 GET_MODE (SUBREG_REG (x)), SUBREG_BYTE (x));
7964 if (true0 && false0)
7972 /* If X is a constant, this isn't special and will cause confusions
7973 if we treat it as such. Likewise if it is equivalent to a constant. */
7974 else if (CONSTANT_P (x)
7975 || ((cond0 = get_last_value (x)) != 0 && CONSTANT_P (cond0)))
7978 /* If we're in BImode, canonicalize on 0 and STORE_FLAG_VALUE, as that
7979 will be least confusing to the rest of the compiler. */
7980 else if (mode == BImode)
7982 *ptrue = GEN_INT (STORE_FLAG_VALUE), *pfalse = const0_rtx;
7986 /* If X is known to be either 0 or -1, those are the true and
7987 false values when testing X. */
7988 else if (x == constm1_rtx || x == const0_rtx
7989 || (mode != VOIDmode
7990 && num_sign_bit_copies (x, mode) == GET_MODE_BITSIZE (mode)))
7992 *ptrue = constm1_rtx, *pfalse = const0_rtx;
7996 /* Likewise for 0 or a single bit. */
7997 else if (SCALAR_INT_MODE_P (mode)
7998 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
7999 && exact_log2 (nz = nonzero_bits (x, mode)) >= 0)
8001 *ptrue = gen_int_mode (nz, mode), *pfalse = const0_rtx;
8005 /* Otherwise fail; show no condition with true and false values the same. */
8006 *ptrue = *pfalse = x;
8010 /* Return the value of expression X given the fact that condition COND
8011 is known to be true when applied to REG as its first operand and VAL
8012 as its second. X is known to not be shared and so can be modified in
8015 We only handle the simplest cases, and specifically those cases that
8016 arise with IF_THEN_ELSE expressions. */
8019 known_cond (rtx x, enum rtx_code cond, rtx reg, rtx val)
8021 enum rtx_code code = GET_CODE (x);
8026 if (side_effects_p (x))
8029 /* If either operand of the condition is a floating point value,
8030 then we have to avoid collapsing an EQ comparison. */
8032 && rtx_equal_p (x, reg)
8033 && ! FLOAT_MODE_P (GET_MODE (x))
8034 && ! FLOAT_MODE_P (GET_MODE (val)))
8037 if (cond == UNEQ && rtx_equal_p (x, reg))
8040 /* If X is (abs REG) and we know something about REG's relationship
8041 with zero, we may be able to simplify this. */
8043 if (code == ABS && rtx_equal_p (XEXP (x, 0), reg) && val == const0_rtx)
8046 case GE: case GT: case EQ:
8049 return simplify_gen_unary (NEG, GET_MODE (XEXP (x, 0)),
8051 GET_MODE (XEXP (x, 0)));
8056 /* The only other cases we handle are MIN, MAX, and comparisons if the
8057 operands are the same as REG and VAL. */
8059 else if (COMPARISON_P (x) || COMMUTATIVE_ARITH_P (x))
8061 if (rtx_equal_p (XEXP (x, 0), val))
8062 cond = swap_condition (cond), temp = val, val = reg, reg = temp;
8064 if (rtx_equal_p (XEXP (x, 0), reg) && rtx_equal_p (XEXP (x, 1), val))
8066 if (COMPARISON_P (x))
8068 if (comparison_dominates_p (cond, code))
8069 return const_true_rtx;
8071 code = reversed_comparison_code (x, NULL);
8073 && comparison_dominates_p (cond, code))
8078 else if (code == SMAX || code == SMIN
8079 || code == UMIN || code == UMAX)
8081 int unsignedp = (code == UMIN || code == UMAX);
8083 /* Do not reverse the condition when it is NE or EQ.
8084 This is because we cannot conclude anything about
8085 the value of 'SMAX (x, y)' when x is not equal to y,
8086 but we can when x equals y. */
8087 if ((code == SMAX || code == UMAX)
8088 && ! (cond == EQ || cond == NE))
8089 cond = reverse_condition (cond);
8094 return unsignedp ? x : XEXP (x, 1);
8096 return unsignedp ? x : XEXP (x, 0);
8098 return unsignedp ? XEXP (x, 1) : x;
8100 return unsignedp ? XEXP (x, 0) : x;
8107 else if (code == SUBREG)
8109 enum machine_mode inner_mode = GET_MODE (SUBREG_REG (x));
8110 rtx new, r = known_cond (SUBREG_REG (x), cond, reg, val);
8112 if (SUBREG_REG (x) != r)
8114 /* We must simplify subreg here, before we lose track of the
8115 original inner_mode. */
8116 new = simplify_subreg (GET_MODE (x), r,
8117 inner_mode, SUBREG_BYTE (x));
8121 SUBST (SUBREG_REG (x), r);
8126 /* We don't have to handle SIGN_EXTEND here, because even in the
8127 case of replacing something with a modeless CONST_INT, a
8128 CONST_INT is already (supposed to be) a valid sign extension for
8129 its narrower mode, which implies it's already properly
8130 sign-extended for the wider mode. Now, for ZERO_EXTEND, the
8131 story is different. */
8132 else if (code == ZERO_EXTEND)
8134 enum machine_mode inner_mode = GET_MODE (XEXP (x, 0));
8135 rtx new, r = known_cond (XEXP (x, 0), cond, reg, val);
8137 if (XEXP (x, 0) != r)
8139 /* We must simplify the zero_extend here, before we lose
8140 track of the original inner_mode. */
8141 new = simplify_unary_operation (ZERO_EXTEND, GET_MODE (x),
8146 SUBST (XEXP (x, 0), r);
8152 fmt = GET_RTX_FORMAT (code);
8153 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
8156 SUBST (XEXP (x, i), known_cond (XEXP (x, i), cond, reg, val));
8157 else if (fmt[i] == 'E')
8158 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
8159 SUBST (XVECEXP (x, i, j), known_cond (XVECEXP (x, i, j),
8166 /* See if X and Y are equal for the purposes of seeing if we can rewrite an
8167 assignment as a field assignment. */
8170 rtx_equal_for_field_assignment_p (rtx x, rtx y)
8172 if (x == y || rtx_equal_p (x, y))
8175 if (x == 0 || y == 0 || GET_MODE (x) != GET_MODE (y))
8178 /* Check for a paradoxical SUBREG of a MEM compared with the MEM.
8179 Note that all SUBREGs of MEM are paradoxical; otherwise they
8180 would have been rewritten. */
8181 if (MEM_P (x) && GET_CODE (y) == SUBREG
8182 && MEM_P (SUBREG_REG (y))
8183 && rtx_equal_p (SUBREG_REG (y),
8184 gen_lowpart (GET_MODE (SUBREG_REG (y)), x)))
8187 if (MEM_P (y) && GET_CODE (x) == SUBREG
8188 && MEM_P (SUBREG_REG (x))
8189 && rtx_equal_p (SUBREG_REG (x),
8190 gen_lowpart (GET_MODE (SUBREG_REG (x)), y)))
8193 /* We used to see if get_last_value of X and Y were the same but that's
8194 not correct. In one direction, we'll cause the assignment to have
8195 the wrong destination and in the case, we'll import a register into this
8196 insn that might have already have been dead. So fail if none of the
8197 above cases are true. */
8201 /* See if X, a SET operation, can be rewritten as a bit-field assignment.
8202 Return that assignment if so.
8204 We only handle the most common cases. */
8207 make_field_assignment (rtx x)
8209 rtx dest = SET_DEST (x);
8210 rtx src = SET_SRC (x);
8215 unsigned HOST_WIDE_INT len;
8217 enum machine_mode mode;
8219 /* If SRC was (and (not (ashift (const_int 1) POS)) DEST), this is
8220 a clear of a one-bit field. We will have changed it to
8221 (and (rotate (const_int -2) POS) DEST), so check for that. Also check
8224 if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == ROTATE
8225 && GET_CODE (XEXP (XEXP (src, 0), 0)) == CONST_INT
8226 && INTVAL (XEXP (XEXP (src, 0), 0)) == -2
8227 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
8229 assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1),
8232 return gen_rtx_SET (VOIDmode, assign, const0_rtx);
8236 if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == SUBREG
8237 && subreg_lowpart_p (XEXP (src, 0))
8238 && (GET_MODE_SIZE (GET_MODE (XEXP (src, 0)))
8239 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (src, 0)))))
8240 && GET_CODE (SUBREG_REG (XEXP (src, 0))) == ROTATE
8241 && GET_CODE (XEXP (SUBREG_REG (XEXP (src, 0)), 0)) == CONST_INT
8242 && INTVAL (XEXP (SUBREG_REG (XEXP (src, 0)), 0)) == -2
8243 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
8245 assign = make_extraction (VOIDmode, dest, 0,
8246 XEXP (SUBREG_REG (XEXP (src, 0)), 1),
8249 return gen_rtx_SET (VOIDmode, assign, const0_rtx);
8253 /* If SRC is (ior (ashift (const_int 1) POS) DEST), this is a set of a
8255 if (GET_CODE (src) == IOR && GET_CODE (XEXP (src, 0)) == ASHIFT
8256 && XEXP (XEXP (src, 0), 0) == const1_rtx
8257 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
8259 assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1),
8262 return gen_rtx_SET (VOIDmode, assign, const1_rtx);
8266 /* If DEST is already a field assignment, i.e. ZERO_EXTRACT, and the
8267 SRC is an AND with all bits of that field set, then we can discard
8269 if (GET_CODE (dest) == ZERO_EXTRACT
8270 && GET_CODE (XEXP (dest, 1)) == CONST_INT
8271 && GET_CODE (src) == AND
8272 && GET_CODE (XEXP (src, 1)) == CONST_INT)
8274 HOST_WIDE_INT width = INTVAL (XEXP (dest, 1));
8275 unsigned HOST_WIDE_INT and_mask = INTVAL (XEXP (src, 1));
8276 unsigned HOST_WIDE_INT ze_mask;
8278 if (width >= HOST_BITS_PER_WIDE_INT)
8281 ze_mask = ((unsigned HOST_WIDE_INT)1 << width) - 1;
8283 /* Complete overlap. We can remove the source AND. */
8284 if ((and_mask & ze_mask) == ze_mask)
8285 return gen_rtx_SET (VOIDmode, dest, XEXP (src, 0));
8287 /* Partial overlap. We can reduce the source AND. */
8288 if ((and_mask & ze_mask) != and_mask)
8290 mode = GET_MODE (src);
8291 src = gen_rtx_AND (mode, XEXP (src, 0),
8292 gen_int_mode (and_mask & ze_mask, mode));
8293 return gen_rtx_SET (VOIDmode, dest, src);
8297 /* The other case we handle is assignments into a constant-position
8298 field. They look like (ior/xor (and DEST C1) OTHER). If C1 represents
8299 a mask that has all one bits except for a group of zero bits and
8300 OTHER is known to have zeros where C1 has ones, this is such an
8301 assignment. Compute the position and length from C1. Shift OTHER
8302 to the appropriate position, force it to the required mode, and
8303 make the extraction. Check for the AND in both operands. */
8305 if (GET_CODE (src) != IOR && GET_CODE (src) != XOR)
8308 rhs = expand_compound_operation (XEXP (src, 0));
8309 lhs = expand_compound_operation (XEXP (src, 1));
8311 if (GET_CODE (rhs) == AND
8312 && GET_CODE (XEXP (rhs, 1)) == CONST_INT
8313 && rtx_equal_for_field_assignment_p (XEXP (rhs, 0), dest))
8314 c1 = INTVAL (XEXP (rhs, 1)), other = lhs;
8315 else if (GET_CODE (lhs) == AND
8316 && GET_CODE (XEXP (lhs, 1)) == CONST_INT
8317 && rtx_equal_for_field_assignment_p (XEXP (lhs, 0), dest))
8318 c1 = INTVAL (XEXP (lhs, 1)), other = rhs;
8322 pos = get_pos_from_mask ((~c1) & GET_MODE_MASK (GET_MODE (dest)), &len);
8323 if (pos < 0 || pos + len > GET_MODE_BITSIZE (GET_MODE (dest))
8324 || GET_MODE_BITSIZE (GET_MODE (dest)) > HOST_BITS_PER_WIDE_INT
8325 || (c1 & nonzero_bits (other, GET_MODE (dest))) != 0)
8328 assign = make_extraction (VOIDmode, dest, pos, NULL_RTX, len, 1, 1, 0);
8332 /* The mode to use for the source is the mode of the assignment, or of
8333 what is inside a possible STRICT_LOW_PART. */
8334 mode = (GET_CODE (assign) == STRICT_LOW_PART
8335 ? GET_MODE (XEXP (assign, 0)) : GET_MODE (assign));
8337 /* Shift OTHER right POS places and make it the source, restricting it
8338 to the proper length and mode. */
8340 src = canon_reg_for_combine (simplify_shift_const (NULL_RTX, LSHIFTRT,
8344 src = force_to_mode (src, mode,
8345 GET_MODE_BITSIZE (mode) >= HOST_BITS_PER_WIDE_INT
8346 ? ~(unsigned HOST_WIDE_INT) 0
8347 : ((unsigned HOST_WIDE_INT) 1 << len) - 1,
8350 /* If SRC is masked by an AND that does not make a difference in
8351 the value being stored, strip it. */
8352 if (GET_CODE (assign) == ZERO_EXTRACT
8353 && GET_CODE (XEXP (assign, 1)) == CONST_INT
8354 && INTVAL (XEXP (assign, 1)) < HOST_BITS_PER_WIDE_INT
8355 && GET_CODE (src) == AND
8356 && GET_CODE (XEXP (src, 1)) == CONST_INT
8357 && ((unsigned HOST_WIDE_INT) INTVAL (XEXP (src, 1))
8358 == ((unsigned HOST_WIDE_INT) 1 << INTVAL (XEXP (assign, 1))) - 1))
8359 src = XEXP (src, 0);
8361 return gen_rtx_SET (VOIDmode, assign, src);
8364 /* See if X is of the form (+ (* a c) (* b c)) and convert to (* (+ a b) c)
8368 apply_distributive_law (rtx x)
8370 enum rtx_code code = GET_CODE (x);
8371 enum rtx_code inner_code;
8372 rtx lhs, rhs, other;
8375 /* Distributivity is not true for floating point as it can change the
8376 value. So we don't do it unless -funsafe-math-optimizations. */
8377 if (FLOAT_MODE_P (GET_MODE (x))
8378 && ! flag_unsafe_math_optimizations)
8381 /* The outer operation can only be one of the following: */
8382 if (code != IOR && code != AND && code != XOR
8383 && code != PLUS && code != MINUS)
8389 /* If either operand is a primitive we can't do anything, so get out
8391 if (OBJECT_P (lhs) || OBJECT_P (rhs))
8394 lhs = expand_compound_operation (lhs);
8395 rhs = expand_compound_operation (rhs);
8396 inner_code = GET_CODE (lhs);
8397 if (inner_code != GET_CODE (rhs))
8400 /* See if the inner and outer operations distribute. */
8407 /* These all distribute except over PLUS. */
8408 if (code == PLUS || code == MINUS)
8413 if (code != PLUS && code != MINUS)
8418 /* This is also a multiply, so it distributes over everything. */
8422 /* Non-paradoxical SUBREGs distributes over all operations,
8423 provided the inner modes and byte offsets are the same, this
8424 is an extraction of a low-order part, we don't convert an fp
8425 operation to int or vice versa, this is not a vector mode,
8426 and we would not be converting a single-word operation into a
8427 multi-word operation. The latter test is not required, but
8428 it prevents generating unneeded multi-word operations. Some
8429 of the previous tests are redundant given the latter test,
8430 but are retained because they are required for correctness.
8432 We produce the result slightly differently in this case. */
8434 if (GET_MODE (SUBREG_REG (lhs)) != GET_MODE (SUBREG_REG (rhs))
8435 || SUBREG_BYTE (lhs) != SUBREG_BYTE (rhs)
8436 || ! subreg_lowpart_p (lhs)
8437 || (GET_MODE_CLASS (GET_MODE (lhs))
8438 != GET_MODE_CLASS (GET_MODE (SUBREG_REG (lhs))))
8439 || (GET_MODE_SIZE (GET_MODE (lhs))
8440 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs))))
8441 || VECTOR_MODE_P (GET_MODE (lhs))
8442 || GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs))) > UNITS_PER_WORD
8443 /* Result might need to be truncated. Don't change mode if
8444 explicit truncation is needed. */
8445 || !TRULY_NOOP_TRUNCATION
8446 (GET_MODE_BITSIZE (GET_MODE (x)),
8447 GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (lhs)))))
8450 tem = simplify_gen_binary (code, GET_MODE (SUBREG_REG (lhs)),
8451 SUBREG_REG (lhs), SUBREG_REG (rhs));
8452 return gen_lowpart (GET_MODE (x), tem);
8458 /* Set LHS and RHS to the inner operands (A and B in the example
8459 above) and set OTHER to the common operand (C in the example).
8460 There is only one way to do this unless the inner operation is
8462 if (COMMUTATIVE_ARITH_P (lhs)
8463 && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 0)))
8464 other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 1);
8465 else if (COMMUTATIVE_ARITH_P (lhs)
8466 && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 1)))
8467 other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 0);
8468 else if (COMMUTATIVE_ARITH_P (lhs)
8469 && rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 0)))
8470 other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 1);
8471 else if (rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 1)))
8472 other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 0);
8476 /* Form the new inner operation, seeing if it simplifies first. */
8477 tem = simplify_gen_binary (code, GET_MODE (x), lhs, rhs);
8479 /* There is one exception to the general way of distributing:
8480 (a | c) ^ (b | c) -> (a ^ b) & ~c */
8481 if (code == XOR && inner_code == IOR)
8484 other = simplify_gen_unary (NOT, GET_MODE (x), other, GET_MODE (x));
8487 /* We may be able to continuing distributing the result, so call
8488 ourselves recursively on the inner operation before forming the
8489 outer operation, which we return. */
8490 return simplify_gen_binary (inner_code, GET_MODE (x),
8491 apply_distributive_law (tem), other);
8494 /* See if X is of the form (* (+ A B) C), and if so convert to
8495 (+ (* A C) (* B C)) and try to simplify.
8497 Most of the time, this results in no change. However, if some of
8498 the operands are the same or inverses of each other, simplifications
8501 For example, (and (ior A B) (not B)) can occur as the result of
8502 expanding a bit field assignment. When we apply the distributive
8503 law to this, we get (ior (and (A (not B))) (and (B (not B)))),
8504 which then simplifies to (and (A (not B))).
8506 Note that no checks happen on the validity of applying the inverse
8507 distributive law. This is pointless since we can do it in the
8508 few places where this routine is called.
8510 N is the index of the term that is decomposed (the arithmetic operation,
8511 i.e. (+ A B) in the first example above). !N is the index of the term that
8512 is distributed, i.e. of C in the first example above. */
8514 distribute_and_simplify_rtx (rtx x, int n)
8516 enum machine_mode mode;
8517 enum rtx_code outer_code, inner_code;
8518 rtx decomposed, distributed, inner_op0, inner_op1, new_op0, new_op1, tmp;
8520 decomposed = XEXP (x, n);
8521 if (!ARITHMETIC_P (decomposed))
8524 mode = GET_MODE (x);
8525 outer_code = GET_CODE (x);
8526 distributed = XEXP (x, !n);
8528 inner_code = GET_CODE (decomposed);
8529 inner_op0 = XEXP (decomposed, 0);
8530 inner_op1 = XEXP (decomposed, 1);
8532 /* Special case (and (xor B C) (not A)), which is equivalent to
8533 (xor (ior A B) (ior A C)) */
8534 if (outer_code == AND && inner_code == XOR && GET_CODE (distributed) == NOT)
8536 distributed = XEXP (distributed, 0);
8542 /* Distribute the second term. */
8543 new_op0 = simplify_gen_binary (outer_code, mode, inner_op0, distributed);
8544 new_op1 = simplify_gen_binary (outer_code, mode, inner_op1, distributed);
8548 /* Distribute the first term. */
8549 new_op0 = simplify_gen_binary (outer_code, mode, distributed, inner_op0);
8550 new_op1 = simplify_gen_binary (outer_code, mode, distributed, inner_op1);
8553 tmp = apply_distributive_law (simplify_gen_binary (inner_code, mode,
8555 if (GET_CODE (tmp) != outer_code
8556 && rtx_cost (tmp, SET) < rtx_cost (x, SET))
8562 /* Simplify a logical `and' of VAROP with the constant CONSTOP, to be done
8563 in MODE. Return an equivalent form, if different from (and VAROP
8564 (const_int CONSTOP)). Otherwise, return NULL_RTX. */
8567 simplify_and_const_int_1 (enum machine_mode mode, rtx varop,
8568 unsigned HOST_WIDE_INT constop)
8570 unsigned HOST_WIDE_INT nonzero;
8571 unsigned HOST_WIDE_INT orig_constop;
8576 orig_constop = constop;
8577 if (GET_CODE (varop) == CLOBBER)
8580 /* Simplify VAROP knowing that we will be only looking at some of the
8583 Note by passing in CONSTOP, we guarantee that the bits not set in
8584 CONSTOP are not significant and will never be examined. We must
8585 ensure that is the case by explicitly masking out those bits
8586 before returning. */
8587 varop = force_to_mode (varop, mode, constop, 0);
8589 /* If VAROP is a CLOBBER, we will fail so return it. */
8590 if (GET_CODE (varop) == CLOBBER)
8593 /* If VAROP is a CONST_INT, then we need to apply the mask in CONSTOP
8594 to VAROP and return the new constant. */
8595 if (GET_CODE (varop) == CONST_INT)
8596 return gen_int_mode (INTVAL (varop) & constop, mode);
8598 /* See what bits may be nonzero in VAROP. Unlike the general case of
8599 a call to nonzero_bits, here we don't care about bits outside
8602 nonzero = nonzero_bits (varop, mode) & GET_MODE_MASK (mode);
8604 /* Turn off all bits in the constant that are known to already be zero.
8605 Thus, if the AND isn't needed at all, we will have CONSTOP == NONZERO_BITS
8606 which is tested below. */
8610 /* If we don't have any bits left, return zero. */
8614 /* If VAROP is a NEG of something known to be zero or 1 and CONSTOP is
8615 a power of two, we can replace this with an ASHIFT. */
8616 if (GET_CODE (varop) == NEG && nonzero_bits (XEXP (varop, 0), mode) == 1
8617 && (i = exact_log2 (constop)) >= 0)
8618 return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (varop, 0), i);
8620 /* If VAROP is an IOR or XOR, apply the AND to both branches of the IOR
8621 or XOR, then try to apply the distributive law. This may eliminate
8622 operations if either branch can be simplified because of the AND.
8623 It may also make some cases more complex, but those cases probably
8624 won't match a pattern either with or without this. */
8626 if (GET_CODE (varop) == IOR || GET_CODE (varop) == XOR)
8630 apply_distributive_law
8631 (simplify_gen_binary (GET_CODE (varop), GET_MODE (varop),
8632 simplify_and_const_int (NULL_RTX,
8636 simplify_and_const_int (NULL_RTX,
8641 /* If VAROP is PLUS, and the constant is a mask of low bits, distribute
8642 the AND and see if one of the operands simplifies to zero. If so, we
8643 may eliminate it. */
8645 if (GET_CODE (varop) == PLUS
8646 && exact_log2 (constop + 1) >= 0)
8650 o0 = simplify_and_const_int (NULL_RTX, mode, XEXP (varop, 0), constop);
8651 o1 = simplify_and_const_int (NULL_RTX, mode, XEXP (varop, 1), constop);
8652 if (o0 == const0_rtx)
8654 if (o1 == const0_rtx)
8658 /* Make a SUBREG if necessary. If we can't make it, fail. */
8659 varop = gen_lowpart (mode, varop);
8660 if (varop == NULL_RTX || GET_CODE (varop) == CLOBBER)
8663 /* If we are only masking insignificant bits, return VAROP. */
8664 if (constop == nonzero)
8667 if (varop == orig_varop && constop == orig_constop)
8670 /* Otherwise, return an AND. */
8671 return simplify_gen_binary (AND, mode, varop, gen_int_mode (constop, mode));
8675 /* We have X, a logical `and' of VAROP with the constant CONSTOP, to be done
8678 Return an equivalent form, if different from X. Otherwise, return X. If
8679 X is zero, we are to always construct the equivalent form. */
8682 simplify_and_const_int (rtx x, enum machine_mode mode, rtx varop,
8683 unsigned HOST_WIDE_INT constop)
8685 rtx tem = simplify_and_const_int_1 (mode, varop, constop);
8690 x = simplify_gen_binary (AND, GET_MODE (varop), varop,
8691 gen_int_mode (constop, mode));
8692 if (GET_MODE (x) != mode)
8693 x = gen_lowpart (mode, x);
8697 /* Given a REG, X, compute which bits in X can be nonzero.
8698 We don't care about bits outside of those defined in MODE.
8700 For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is
8701 a shift, AND, or zero_extract, we can do better. */
8704 reg_nonzero_bits_for_combine (const_rtx x, enum machine_mode mode,
8705 const_rtx known_x ATTRIBUTE_UNUSED,
8706 enum machine_mode known_mode ATTRIBUTE_UNUSED,
8707 unsigned HOST_WIDE_INT known_ret ATTRIBUTE_UNUSED,
8708 unsigned HOST_WIDE_INT *nonzero)
8713 /* If X is a register whose nonzero bits value is current, use it.
8714 Otherwise, if X is a register whose value we can find, use that
8715 value. Otherwise, use the previously-computed global nonzero bits
8716 for this register. */
8718 rsp = VEC_index (reg_stat_type, reg_stat, REGNO (x));
8719 if (rsp->last_set_value != 0
8720 && (rsp->last_set_mode == mode
8721 || (GET_MODE_CLASS (rsp->last_set_mode) == MODE_INT
8722 && GET_MODE_CLASS (mode) == MODE_INT))
8723 && ((rsp->last_set_label >= label_tick_ebb_start
8724 && rsp->last_set_label < label_tick)
8725 || (rsp->last_set_label == label_tick
8726 && DF_INSN_LUID (rsp->last_set) < subst_low_luid)
8727 || (REGNO (x) >= FIRST_PSEUDO_REGISTER
8728 && REG_N_SETS (REGNO (x)) == 1
8730 (DF_LR_IN (ENTRY_BLOCK_PTR->next_bb), REGNO (x)))))
8732 *nonzero &= rsp->last_set_nonzero_bits;
8736 tem = get_last_value (x);
8740 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
8741 /* If X is narrower than MODE and TEM is a non-negative
8742 constant that would appear negative in the mode of X,
8743 sign-extend it for use in reg_nonzero_bits because some
8744 machines (maybe most) will actually do the sign-extension
8745 and this is the conservative approach.
8747 ??? For 2.5, try to tighten up the MD files in this regard
8748 instead of this kludge. */
8750 if (GET_MODE_BITSIZE (GET_MODE (x)) < GET_MODE_BITSIZE (mode)
8751 && GET_CODE (tem) == CONST_INT
8753 && 0 != (INTVAL (tem)
8754 & ((HOST_WIDE_INT) 1
8755 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
8756 tem = GEN_INT (INTVAL (tem)
8757 | ((HOST_WIDE_INT) (-1)
8758 << GET_MODE_BITSIZE (GET_MODE (x))));
8762 else if (nonzero_sign_valid && rsp->nonzero_bits)
8764 unsigned HOST_WIDE_INT mask = rsp->nonzero_bits;
8766 if (GET_MODE_BITSIZE (GET_MODE (x)) < GET_MODE_BITSIZE (mode))
8767 /* We don't know anything about the upper bits. */
8768 mask |= GET_MODE_MASK (mode) ^ GET_MODE_MASK (GET_MODE (x));
8775 /* Return the number of bits at the high-order end of X that are known to
8776 be equal to the sign bit. X will be used in mode MODE; if MODE is
8777 VOIDmode, X will be used in its own mode. The returned value will always
8778 be between 1 and the number of bits in MODE. */
8781 reg_num_sign_bit_copies_for_combine (const_rtx x, enum machine_mode mode,
8782 const_rtx known_x ATTRIBUTE_UNUSED,
8783 enum machine_mode known_mode
8785 unsigned int known_ret ATTRIBUTE_UNUSED,
8786 unsigned int *result)
8791 rsp = VEC_index (reg_stat_type, reg_stat, REGNO (x));
8792 if (rsp->last_set_value != 0
8793 && rsp->last_set_mode == mode
8794 && ((rsp->last_set_label >= label_tick_ebb_start
8795 && rsp->last_set_label < label_tick)
8796 || (rsp->last_set_label == label_tick
8797 && DF_INSN_LUID (rsp->last_set) < subst_low_luid)
8798 || (REGNO (x) >= FIRST_PSEUDO_REGISTER
8799 && REG_N_SETS (REGNO (x)) == 1
8801 (DF_LR_IN (ENTRY_BLOCK_PTR->next_bb), REGNO (x)))))
8803 *result = rsp->last_set_sign_bit_copies;
8807 tem = get_last_value (x);
8811 if (nonzero_sign_valid && rsp->sign_bit_copies != 0
8812 && GET_MODE_BITSIZE (GET_MODE (x)) == GET_MODE_BITSIZE (mode))
8813 *result = rsp->sign_bit_copies;
8818 /* Return the number of "extended" bits there are in X, when interpreted
8819 as a quantity in MODE whose signedness is indicated by UNSIGNEDP. For
8820 unsigned quantities, this is the number of high-order zero bits.
8821 For signed quantities, this is the number of copies of the sign bit
8822 minus 1. In both case, this function returns the number of "spare"
8823 bits. For example, if two quantities for which this function returns
8824 at least 1 are added, the addition is known not to overflow.
8826 This function will always return 0 unless called during combine, which
8827 implies that it must be called from a define_split. */
8830 extended_count (const_rtx x, enum machine_mode mode, int unsignedp)
8832 if (nonzero_sign_valid == 0)
8836 ? (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
8837 ? (unsigned int) (GET_MODE_BITSIZE (mode) - 1
8838 - floor_log2 (nonzero_bits (x, mode)))
8840 : num_sign_bit_copies (x, mode) - 1);
8843 /* This function is called from `simplify_shift_const' to merge two
8844 outer operations. Specifically, we have already found that we need
8845 to perform operation *POP0 with constant *PCONST0 at the outermost
8846 position. We would now like to also perform OP1 with constant CONST1
8847 (with *POP0 being done last).
8849 Return 1 if we can do the operation and update *POP0 and *PCONST0 with
8850 the resulting operation. *PCOMP_P is set to 1 if we would need to
8851 complement the innermost operand, otherwise it is unchanged.
8853 MODE is the mode in which the operation will be done. No bits outside
8854 the width of this mode matter. It is assumed that the width of this mode
8855 is smaller than or equal to HOST_BITS_PER_WIDE_INT.
8857 If *POP0 or OP1 are UNKNOWN, it means no operation is required. Only NEG, PLUS,
8858 IOR, XOR, and AND are supported. We may set *POP0 to SET if the proper
8859 result is simply *PCONST0.
8861 If the resulting operation cannot be expressed as one operation, we
8862 return 0 and do not change *POP0, *PCONST0, and *PCOMP_P. */
8865 merge_outer_ops (enum rtx_code *pop0, HOST_WIDE_INT *pconst0, enum rtx_code op1, HOST_WIDE_INT const1, enum machine_mode mode, int *pcomp_p)
8867 enum rtx_code op0 = *pop0;
8868 HOST_WIDE_INT const0 = *pconst0;
8870 const0 &= GET_MODE_MASK (mode);
8871 const1 &= GET_MODE_MASK (mode);
8873 /* If OP0 is an AND, clear unimportant bits in CONST1. */
8877 /* If OP0 or OP1 is UNKNOWN, this is easy. Similarly if they are the same or
8880 if (op1 == UNKNOWN || op0 == SET)
8883 else if (op0 == UNKNOWN)
8884 op0 = op1, const0 = const1;
8886 else if (op0 == op1)
8910 /* Otherwise, if either is a PLUS or NEG, we can't do anything. */
8911 else if (op0 == PLUS || op1 == PLUS || op0 == NEG || op1 == NEG)
8914 /* If the two constants aren't the same, we can't do anything. The
8915 remaining six cases can all be done. */
8916 else if (const0 != const1)
8924 /* (a & b) | b == b */
8926 else /* op1 == XOR */
8927 /* (a ^ b) | b == a | b */
8933 /* (a & b) ^ b == (~a) & b */
8934 op0 = AND, *pcomp_p = 1;
8935 else /* op1 == IOR */
8936 /* (a | b) ^ b == a & ~b */
8937 op0 = AND, const0 = ~const0;
8942 /* (a | b) & b == b */
8944 else /* op1 == XOR */
8945 /* (a ^ b) & b) == (~a) & b */
8952 /* Check for NO-OP cases. */
8953 const0 &= GET_MODE_MASK (mode);
8955 && (op0 == IOR || op0 == XOR || op0 == PLUS))
8957 else if (const0 == 0 && op0 == AND)
8959 else if ((unsigned HOST_WIDE_INT) const0 == GET_MODE_MASK (mode)
8963 /* ??? Slightly redundant with the above mask, but not entirely.
8964 Moving this above means we'd have to sign-extend the mode mask
8965 for the final test. */
8966 const0 = trunc_int_for_mode (const0, mode);
8974 /* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift.
8975 The result of the shift is RESULT_MODE. Return NULL_RTX if we cannot
8976 simplify it. Otherwise, return a simplified value.
8978 The shift is normally computed in the widest mode we find in VAROP, as
8979 long as it isn't a different number of words than RESULT_MODE. Exceptions
8980 are ASHIFTRT and ROTATE, which are always done in their original mode. */
8983 simplify_shift_const_1 (enum rtx_code code, enum machine_mode result_mode,
8984 rtx varop, int orig_count)
8986 enum rtx_code orig_code = code;
8987 rtx orig_varop = varop;
8989 enum machine_mode mode = result_mode;
8990 enum machine_mode shift_mode, tmode;
8991 unsigned int mode_words
8992 = (GET_MODE_SIZE (mode) + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD;
8993 /* We form (outer_op (code varop count) (outer_const)). */
8994 enum rtx_code outer_op = UNKNOWN;
8995 HOST_WIDE_INT outer_const = 0;
8996 int complement_p = 0;
8999 /* Make sure and truncate the "natural" shift on the way in. We don't
9000 want to do this inside the loop as it makes it more difficult to
9002 if (SHIFT_COUNT_TRUNCATED)
9003 orig_count &= GET_MODE_BITSIZE (mode) - 1;
9005 /* If we were given an invalid count, don't do anything except exactly
9006 what was requested. */
9008 if (orig_count < 0 || orig_count >= (int) GET_MODE_BITSIZE (mode))
9013 /* Unless one of the branches of the `if' in this loop does a `continue',
9014 we will `break' the loop after the `if'. */
9018 /* If we have an operand of (clobber (const_int 0)), fail. */
9019 if (GET_CODE (varop) == CLOBBER)
9022 /* If we discovered we had to complement VAROP, leave. Making a NOT
9023 here would cause an infinite loop. */
9027 /* Convert ROTATERT to ROTATE. */
9028 if (code == ROTATERT)
9030 unsigned int bitsize = GET_MODE_BITSIZE (result_mode);;
9032 if (VECTOR_MODE_P (result_mode))
9033 count = bitsize / GET_MODE_NUNITS (result_mode) - count;
9035 count = bitsize - count;
9038 /* We need to determine what mode we will do the shift in. If the
9039 shift is a right shift or a ROTATE, we must always do it in the mode
9040 it was originally done in. Otherwise, we can do it in MODE, the
9041 widest mode encountered. */
9043 = (code == ASHIFTRT || code == LSHIFTRT || code == ROTATE
9044 ? result_mode : mode);
9046 /* Handle cases where the count is greater than the size of the mode
9047 minus 1. For ASHIFT, use the size minus one as the count (this can
9048 occur when simplifying (lshiftrt (ashiftrt ..))). For rotates,
9049 take the count modulo the size. For other shifts, the result is
9052 Since these shifts are being produced by the compiler by combining
9053 multiple operations, each of which are defined, we know what the
9054 result is supposed to be. */
9056 if (count > (GET_MODE_BITSIZE (shift_mode) - 1))
9058 if (code == ASHIFTRT)
9059 count = GET_MODE_BITSIZE (shift_mode) - 1;
9060 else if (code == ROTATE || code == ROTATERT)
9061 count %= GET_MODE_BITSIZE (shift_mode);
9064 /* We can't simply return zero because there may be an
9072 /* An arithmetic right shift of a quantity known to be -1 or 0
9074 if (code == ASHIFTRT
9075 && (num_sign_bit_copies (varop, shift_mode)
9076 == GET_MODE_BITSIZE (shift_mode)))
9082 /* If we are doing an arithmetic right shift and discarding all but
9083 the sign bit copies, this is equivalent to doing a shift by the
9084 bitsize minus one. Convert it into that shift because it will often
9085 allow other simplifications. */
9087 if (code == ASHIFTRT
9088 && (count + num_sign_bit_copies (varop, shift_mode)
9089 >= GET_MODE_BITSIZE (shift_mode)))
9090 count = GET_MODE_BITSIZE (shift_mode) - 1;
9092 /* We simplify the tests below and elsewhere by converting
9093 ASHIFTRT to LSHIFTRT if we know the sign bit is clear.
9094 `make_compound_operation' will convert it to an ASHIFTRT for
9095 those machines (such as VAX) that don't have an LSHIFTRT. */
9096 if (GET_MODE_BITSIZE (shift_mode) <= HOST_BITS_PER_WIDE_INT
9098 && ((nonzero_bits (varop, shift_mode)
9099 & ((HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (shift_mode) - 1)))
9103 if (((code == LSHIFTRT
9104 && GET_MODE_BITSIZE (shift_mode) <= HOST_BITS_PER_WIDE_INT
9105 && !(nonzero_bits (varop, shift_mode) >> count))
9107 && GET_MODE_BITSIZE (shift_mode) <= HOST_BITS_PER_WIDE_INT
9108 && !((nonzero_bits (varop, shift_mode) << count)
9109 & GET_MODE_MASK (shift_mode))))
9110 && !side_effects_p (varop))
9113 switch (GET_CODE (varop))
9119 new = expand_compound_operation (varop);
9128 /* If we have (xshiftrt (mem ...) C) and C is MODE_WIDTH
9129 minus the width of a smaller mode, we can do this with a
9130 SIGN_EXTEND or ZERO_EXTEND from the narrower memory location. */
9131 if ((code == ASHIFTRT || code == LSHIFTRT)
9132 && ! mode_dependent_address_p (XEXP (varop, 0))
9133 && ! MEM_VOLATILE_P (varop)
9134 && (tmode = mode_for_size (GET_MODE_BITSIZE (mode) - count,
9135 MODE_INT, 1)) != BLKmode)
9137 new = adjust_address_nv (varop, tmode,
9138 BYTES_BIG_ENDIAN ? 0
9139 : count / BITS_PER_UNIT);
9141 varop = gen_rtx_fmt_e (code == ASHIFTRT ? SIGN_EXTEND
9142 : ZERO_EXTEND, mode, new);
9149 /* If VAROP is a SUBREG, strip it as long as the inner operand has
9150 the same number of words as what we've seen so far. Then store
9151 the widest mode in MODE. */
9152 if (subreg_lowpart_p (varop)
9153 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop)))
9154 > GET_MODE_SIZE (GET_MODE (varop)))
9155 && (unsigned int) ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop)))
9156 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
9159 varop = SUBREG_REG (varop);
9160 if (GET_MODE_SIZE (GET_MODE (varop)) > GET_MODE_SIZE (mode))
9161 mode = GET_MODE (varop);
9167 /* Some machines use MULT instead of ASHIFT because MULT
9168 is cheaper. But it is still better on those machines to
9169 merge two shifts into one. */
9170 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
9171 && exact_log2 (INTVAL (XEXP (varop, 1))) >= 0)
9174 = simplify_gen_binary (ASHIFT, GET_MODE (varop),
9176 GEN_INT (exact_log2 (
9177 INTVAL (XEXP (varop, 1)))));
9183 /* Similar, for when divides are cheaper. */
9184 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
9185 && exact_log2 (INTVAL (XEXP (varop, 1))) >= 0)
9188 = simplify_gen_binary (LSHIFTRT, GET_MODE (varop),
9190 GEN_INT (exact_log2 (
9191 INTVAL (XEXP (varop, 1)))));
9197 /* If we are extracting just the sign bit of an arithmetic
9198 right shift, that shift is not needed. However, the sign
9199 bit of a wider mode may be different from what would be
9200 interpreted as the sign bit in a narrower mode, so, if
9201 the result is narrower, don't discard the shift. */
9202 if (code == LSHIFTRT
9203 && count == (GET_MODE_BITSIZE (result_mode) - 1)
9204 && (GET_MODE_BITSIZE (result_mode)
9205 >= GET_MODE_BITSIZE (GET_MODE (varop))))
9207 varop = XEXP (varop, 0);
9211 /* ... fall through ... */
9216 /* Here we have two nested shifts. The result is usually the
9217 AND of a new shift with a mask. We compute the result below. */
9218 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
9219 && INTVAL (XEXP (varop, 1)) >= 0
9220 && INTVAL (XEXP (varop, 1)) < GET_MODE_BITSIZE (GET_MODE (varop))
9221 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
9222 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
9223 && !VECTOR_MODE_P (result_mode))
9225 enum rtx_code first_code = GET_CODE (varop);
9226 unsigned int first_count = INTVAL (XEXP (varop, 1));
9227 unsigned HOST_WIDE_INT mask;
9230 /* We have one common special case. We can't do any merging if
9231 the inner code is an ASHIFTRT of a smaller mode. However, if
9232 we have (ashift:M1 (subreg:M1 (ashiftrt:M2 FOO C1) 0) C2)
9233 with C2 == GET_MODE_BITSIZE (M1) - GET_MODE_BITSIZE (M2),
9234 we can convert it to
9235 (ashiftrt:M1 (ashift:M1 (and:M1 (subreg:M1 FOO 0 C2) C3) C1).
9236 This simplifies certain SIGN_EXTEND operations. */
9237 if (code == ASHIFT && first_code == ASHIFTRT
9238 && count == (GET_MODE_BITSIZE (result_mode)
9239 - GET_MODE_BITSIZE (GET_MODE (varop))))
9241 /* C3 has the low-order C1 bits zero. */
9243 mask = (GET_MODE_MASK (mode)
9244 & ~(((HOST_WIDE_INT) 1 << first_count) - 1));
9246 varop = simplify_and_const_int (NULL_RTX, result_mode,
9247 XEXP (varop, 0), mask);
9248 varop = simplify_shift_const (NULL_RTX, ASHIFT, result_mode,
9250 count = first_count;
9255 /* If this was (ashiftrt (ashift foo C1) C2) and FOO has more
9256 than C1 high-order bits equal to the sign bit, we can convert
9257 this to either an ASHIFT or an ASHIFTRT depending on the
9260 We cannot do this if VAROP's mode is not SHIFT_MODE. */
9262 if (code == ASHIFTRT && first_code == ASHIFT
9263 && GET_MODE (varop) == shift_mode
9264 && (num_sign_bit_copies (XEXP (varop, 0), shift_mode)
9267 varop = XEXP (varop, 0);
9268 count -= first_count;
9278 /* There are some cases we can't do. If CODE is ASHIFTRT,
9279 we can only do this if FIRST_CODE is also ASHIFTRT.
9281 We can't do the case when CODE is ROTATE and FIRST_CODE is
9284 If the mode of this shift is not the mode of the outer shift,
9285 we can't do this if either shift is a right shift or ROTATE.
9287 Finally, we can't do any of these if the mode is too wide
9288 unless the codes are the same.
9290 Handle the case where the shift codes are the same
9293 if (code == first_code)
9295 if (GET_MODE (varop) != result_mode
9296 && (code == ASHIFTRT || code == LSHIFTRT
9300 count += first_count;
9301 varop = XEXP (varop, 0);
9305 if (code == ASHIFTRT
9306 || (code == ROTATE && first_code == ASHIFTRT)
9307 || GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT
9308 || (GET_MODE (varop) != result_mode
9309 && (first_code == ASHIFTRT || first_code == LSHIFTRT
9310 || first_code == ROTATE
9311 || code == ROTATE)))
9314 /* To compute the mask to apply after the shift, shift the
9315 nonzero bits of the inner shift the same way the
9316 outer shift will. */
9318 mask_rtx = GEN_INT (nonzero_bits (varop, GET_MODE (varop)));
9321 = simplify_const_binary_operation (code, result_mode, mask_rtx,
9324 /* Give up if we can't compute an outer operation to use. */
9326 || GET_CODE (mask_rtx) != CONST_INT
9327 || ! merge_outer_ops (&outer_op, &outer_const, AND,
9329 result_mode, &complement_p))
9332 /* If the shifts are in the same direction, we add the
9333 counts. Otherwise, we subtract them. */
9334 if ((code == ASHIFTRT || code == LSHIFTRT)
9335 == (first_code == ASHIFTRT || first_code == LSHIFTRT))
9336 count += first_count;
9338 count -= first_count;
9340 /* If COUNT is positive, the new shift is usually CODE,
9341 except for the two exceptions below, in which case it is
9342 FIRST_CODE. If the count is negative, FIRST_CODE should
9345 && ((first_code == ROTATE && code == ASHIFT)
9346 || (first_code == ASHIFTRT && code == LSHIFTRT)))
9349 code = first_code, count = -count;
9351 varop = XEXP (varop, 0);
9355 /* If we have (A << B << C) for any shift, we can convert this to
9356 (A << C << B). This wins if A is a constant. Only try this if
9357 B is not a constant. */
9359 else if (GET_CODE (varop) == code
9360 && GET_CODE (XEXP (varop, 0)) == CONST_INT
9361 && GET_CODE (XEXP (varop, 1)) != CONST_INT)
9363 rtx new = simplify_const_binary_operation (code, mode,
9366 varop = gen_rtx_fmt_ee (code, mode, new, XEXP (varop, 1));
9373 if (VECTOR_MODE_P (mode))
9376 /* Make this fit the case below. */
9377 varop = gen_rtx_XOR (mode, XEXP (varop, 0),
9378 GEN_INT (GET_MODE_MASK (mode)));
9384 /* If we have (xshiftrt (ior (plus X (const_int -1)) X) C)
9385 with C the size of VAROP - 1 and the shift is logical if
9386 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
9387 we have an (le X 0) operation. If we have an arithmetic shift
9388 and STORE_FLAG_VALUE is 1 or we have a logical shift with
9389 STORE_FLAG_VALUE of -1, we have a (neg (le X 0)) operation. */
9391 if (GET_CODE (varop) == IOR && GET_CODE (XEXP (varop, 0)) == PLUS
9392 && XEXP (XEXP (varop, 0), 1) == constm1_rtx
9393 && (STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
9394 && (code == LSHIFTRT || code == ASHIFTRT)
9395 && count == (GET_MODE_BITSIZE (GET_MODE (varop)) - 1)
9396 && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
9399 varop = gen_rtx_LE (GET_MODE (varop), XEXP (varop, 1),
9402 if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
9403 varop = gen_rtx_NEG (GET_MODE (varop), varop);
9408 /* If we have (shift (logical)), move the logical to the outside
9409 to allow it to possibly combine with another logical and the
9410 shift to combine with another shift. This also canonicalizes to
9411 what a ZERO_EXTRACT looks like. Also, some machines have
9412 (and (shift)) insns. */
9414 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
9415 /* We can't do this if we have (ashiftrt (xor)) and the
9416 constant has its sign bit set in shift_mode. */
9417 && !(code == ASHIFTRT && GET_CODE (varop) == XOR
9418 && 0 > trunc_int_for_mode (INTVAL (XEXP (varop, 1)),
9420 && (new = simplify_const_binary_operation (code, result_mode,
9422 GEN_INT (count))) != 0
9423 && GET_CODE (new) == CONST_INT
9424 && merge_outer_ops (&outer_op, &outer_const, GET_CODE (varop),
9425 INTVAL (new), result_mode, &complement_p))
9427 varop = XEXP (varop, 0);
9431 /* If we can't do that, try to simplify the shift in each arm of the
9432 logical expression, make a new logical expression, and apply
9433 the inverse distributive law. This also can't be done
9434 for some (ashiftrt (xor)). */
9435 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
9436 && !(code == ASHIFTRT && GET_CODE (varop) == XOR
9437 && 0 > trunc_int_for_mode (INTVAL (XEXP (varop, 1)),
9440 rtx lhs = simplify_shift_const (NULL_RTX, code, shift_mode,
9441 XEXP (varop, 0), count);
9442 rtx rhs = simplify_shift_const (NULL_RTX, code, shift_mode,
9443 XEXP (varop, 1), count);
9445 varop = simplify_gen_binary (GET_CODE (varop), shift_mode,
9447 varop = apply_distributive_law (varop);
9455 /* Convert (lshiftrt (eq FOO 0) C) to (xor FOO 1) if STORE_FLAG_VALUE
9456 says that the sign bit can be tested, FOO has mode MODE, C is
9457 GET_MODE_BITSIZE (MODE) - 1, and FOO has only its low-order bit
9458 that may be nonzero. */
9459 if (code == LSHIFTRT
9460 && XEXP (varop, 1) == const0_rtx
9461 && GET_MODE (XEXP (varop, 0)) == result_mode
9462 && count == (GET_MODE_BITSIZE (result_mode) - 1)
9463 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
9464 && STORE_FLAG_VALUE == -1
9465 && nonzero_bits (XEXP (varop, 0), result_mode) == 1
9466 && merge_outer_ops (&outer_op, &outer_const, XOR,
9467 (HOST_WIDE_INT) 1, result_mode,
9470 varop = XEXP (varop, 0);
9477 /* (lshiftrt (neg A) C) where A is either 0 or 1 and C is one less
9478 than the number of bits in the mode is equivalent to A. */
9479 if (code == LSHIFTRT
9480 && count == (GET_MODE_BITSIZE (result_mode) - 1)
9481 && nonzero_bits (XEXP (varop, 0), result_mode) == 1)
9483 varop = XEXP (varop, 0);
9488 /* NEG commutes with ASHIFT since it is multiplication. Move the
9489 NEG outside to allow shifts to combine. */
9491 && merge_outer_ops (&outer_op, &outer_const, NEG,
9492 (HOST_WIDE_INT) 0, result_mode,
9495 varop = XEXP (varop, 0);
9501 /* (lshiftrt (plus A -1) C) where A is either 0 or 1 and C
9502 is one less than the number of bits in the mode is
9503 equivalent to (xor A 1). */
9504 if (code == LSHIFTRT
9505 && count == (GET_MODE_BITSIZE (result_mode) - 1)
9506 && XEXP (varop, 1) == constm1_rtx
9507 && nonzero_bits (XEXP (varop, 0), result_mode) == 1
9508 && merge_outer_ops (&outer_op, &outer_const, XOR,
9509 (HOST_WIDE_INT) 1, result_mode,
9513 varop = XEXP (varop, 0);
9517 /* If we have (xshiftrt (plus FOO BAR) C), and the only bits
9518 that might be nonzero in BAR are those being shifted out and those
9519 bits are known zero in FOO, we can replace the PLUS with FOO.
9520 Similarly in the other operand order. This code occurs when
9521 we are computing the size of a variable-size array. */
9523 if ((code == ASHIFTRT || code == LSHIFTRT)
9524 && count < HOST_BITS_PER_WIDE_INT
9525 && nonzero_bits (XEXP (varop, 1), result_mode) >> count == 0
9526 && (nonzero_bits (XEXP (varop, 1), result_mode)
9527 & nonzero_bits (XEXP (varop, 0), result_mode)) == 0)
9529 varop = XEXP (varop, 0);
9532 else if ((code == ASHIFTRT || code == LSHIFTRT)
9533 && count < HOST_BITS_PER_WIDE_INT
9534 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
9535 && 0 == (nonzero_bits (XEXP (varop, 0), result_mode)
9537 && 0 == (nonzero_bits (XEXP (varop, 0), result_mode)
9538 & nonzero_bits (XEXP (varop, 1),
9541 varop = XEXP (varop, 1);
9545 /* (ashift (plus foo C) N) is (plus (ashift foo N) C'). */
9547 && GET_CODE (XEXP (varop, 1)) == CONST_INT
9548 && (new = simplify_const_binary_operation (ASHIFT, result_mode,
9550 GEN_INT (count))) != 0
9551 && GET_CODE (new) == CONST_INT
9552 && merge_outer_ops (&outer_op, &outer_const, PLUS,
9553 INTVAL (new), result_mode, &complement_p))
9555 varop = XEXP (varop, 0);
9559 /* Check for 'PLUS signbit', which is the canonical form of 'XOR
9560 signbit', and attempt to change the PLUS to an XOR and move it to
9561 the outer operation as is done above in the AND/IOR/XOR case
9562 leg for shift(logical). See details in logical handling above
9563 for reasoning in doing so. */
9564 if (code == LSHIFTRT
9565 && GET_CODE (XEXP (varop, 1)) == CONST_INT
9566 && mode_signbit_p (result_mode, XEXP (varop, 1))
9567 && (new = simplify_const_binary_operation (code, result_mode,
9569 GEN_INT (count))) != 0
9570 && GET_CODE (new) == CONST_INT
9571 && merge_outer_ops (&outer_op, &outer_const, XOR,
9572 INTVAL (new), result_mode, &complement_p))
9574 varop = XEXP (varop, 0);
9581 /* If we have (xshiftrt (minus (ashiftrt X C)) X) C)
9582 with C the size of VAROP - 1 and the shift is logical if
9583 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
9584 we have a (gt X 0) operation. If the shift is arithmetic with
9585 STORE_FLAG_VALUE of 1 or logical with STORE_FLAG_VALUE == -1,
9586 we have a (neg (gt X 0)) operation. */
9588 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
9589 && GET_CODE (XEXP (varop, 0)) == ASHIFTRT
9590 && count == (GET_MODE_BITSIZE (GET_MODE (varop)) - 1)
9591 && (code == LSHIFTRT || code == ASHIFTRT)
9592 && GET_CODE (XEXP (XEXP (varop, 0), 1)) == CONST_INT
9593 && INTVAL (XEXP (XEXP (varop, 0), 1)) == count
9594 && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
9597 varop = gen_rtx_GT (GET_MODE (varop), XEXP (varop, 1),
9600 if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
9601 varop = gen_rtx_NEG (GET_MODE (varop), varop);
9608 /* Change (lshiftrt (truncate (lshiftrt))) to (truncate (lshiftrt))
9609 if the truncate does not affect the value. */
9610 if (code == LSHIFTRT
9611 && GET_CODE (XEXP (varop, 0)) == LSHIFTRT
9612 && GET_CODE (XEXP (XEXP (varop, 0), 1)) == CONST_INT
9613 && (INTVAL (XEXP (XEXP (varop, 0), 1))
9614 >= (GET_MODE_BITSIZE (GET_MODE (XEXP (varop, 0)))
9615 - GET_MODE_BITSIZE (GET_MODE (varop)))))
9617 rtx varop_inner = XEXP (varop, 0);
9620 = gen_rtx_LSHIFTRT (GET_MODE (varop_inner),
9621 XEXP (varop_inner, 0),
9623 (count + INTVAL (XEXP (varop_inner, 1))));
9624 varop = gen_rtx_TRUNCATE (GET_MODE (varop), varop_inner);
9637 /* We need to determine what mode to do the shift in. If the shift is
9638 a right shift or ROTATE, we must always do it in the mode it was
9639 originally done in. Otherwise, we can do it in MODE, the widest mode
9640 encountered. The code we care about is that of the shift that will
9641 actually be done, not the shift that was originally requested. */
9643 = (code == ASHIFTRT || code == LSHIFTRT || code == ROTATE
9644 ? result_mode : mode);
9646 /* We have now finished analyzing the shift. The result should be
9647 a shift of type CODE with SHIFT_MODE shifting VAROP COUNT places. If
9648 OUTER_OP is non-UNKNOWN, it is an operation that needs to be applied
9649 to the result of the shift. OUTER_CONST is the relevant constant,
9650 but we must turn off all bits turned off in the shift. */
9652 if (outer_op == UNKNOWN
9653 && orig_code == code && orig_count == count
9654 && varop == orig_varop
9655 && shift_mode == GET_MODE (varop))
9658 /* Make a SUBREG if necessary. If we can't make it, fail. */
9659 varop = gen_lowpart (shift_mode, varop);
9660 if (varop == NULL_RTX || GET_CODE (varop) == CLOBBER)
9663 /* If we have an outer operation and we just made a shift, it is
9664 possible that we could have simplified the shift were it not
9665 for the outer operation. So try to do the simplification
9668 if (outer_op != UNKNOWN)
9669 x = simplify_shift_const_1 (code, shift_mode, varop, count);
9674 x = simplify_gen_binary (code, shift_mode, varop, GEN_INT (count));
9676 /* If we were doing an LSHIFTRT in a wider mode than it was originally,
9677 turn off all the bits that the shift would have turned off. */
9678 if (orig_code == LSHIFTRT && result_mode != shift_mode)
9679 x = simplify_and_const_int (NULL_RTX, shift_mode, x,
9680 GET_MODE_MASK (result_mode) >> orig_count);
9682 /* Do the remainder of the processing in RESULT_MODE. */
9683 x = gen_lowpart_or_truncate (result_mode, x);
9685 /* If COMPLEMENT_P is set, we have to complement X before doing the outer
9688 x = simplify_gen_unary (NOT, result_mode, x, result_mode);
9690 if (outer_op != UNKNOWN)
9692 if (GET_MODE_BITSIZE (result_mode) < HOST_BITS_PER_WIDE_INT)
9693 outer_const = trunc_int_for_mode (outer_const, result_mode);
9695 if (outer_op == AND)
9696 x = simplify_and_const_int (NULL_RTX, result_mode, x, outer_const);
9697 else if (outer_op == SET)
9699 /* This means that we have determined that the result is
9700 equivalent to a constant. This should be rare. */
9701 if (!side_effects_p (x))
9702 x = GEN_INT (outer_const);
9704 else if (GET_RTX_CLASS (outer_op) == RTX_UNARY)
9705 x = simplify_gen_unary (outer_op, result_mode, x, result_mode);
9707 x = simplify_gen_binary (outer_op, result_mode, x,
9708 GEN_INT (outer_const));
9714 /* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift.
9715 The result of the shift is RESULT_MODE. If we cannot simplify it,
9716 return X or, if it is NULL, synthesize the expression with
9717 simplify_gen_binary. Otherwise, return a simplified value.
9719 The shift is normally computed in the widest mode we find in VAROP, as
9720 long as it isn't a different number of words than RESULT_MODE. Exceptions
9721 are ASHIFTRT and ROTATE, which are always done in their original mode. */
9724 simplify_shift_const (rtx x, enum rtx_code code, enum machine_mode result_mode,
9725 rtx varop, int count)
9727 rtx tem = simplify_shift_const_1 (code, result_mode, varop, count);
9732 x = simplify_gen_binary (code, GET_MODE (varop), varop, GEN_INT (count));
9733 if (GET_MODE (x) != result_mode)
9734 x = gen_lowpart (result_mode, x);
9739 /* Like recog, but we receive the address of a pointer to a new pattern.
9740 We try to match the rtx that the pointer points to.
9741 If that fails, we may try to modify or replace the pattern,
9742 storing the replacement into the same pointer object.
9744 Modifications include deletion or addition of CLOBBERs.
9746 PNOTES is a pointer to a location where any REG_UNUSED notes added for
9747 the CLOBBERs are placed.
9749 The value is the final insn code from the pattern ultimately matched,
9753 recog_for_combine (rtx *pnewpat, rtx insn, rtx *pnotes)
9756 int insn_code_number;
9757 int num_clobbers_to_add = 0;
9760 rtx old_notes, old_pat;
9762 /* If PAT is a PARALLEL, check to see if it contains the CLOBBER
9763 we use to indicate that something didn't match. If we find such a
9764 thing, force rejection. */
9765 if (GET_CODE (pat) == PARALLEL)
9766 for (i = XVECLEN (pat, 0) - 1; i >= 0; i--)
9767 if (GET_CODE (XVECEXP (pat, 0, i)) == CLOBBER
9768 && XEXP (XVECEXP (pat, 0, i), 0) == const0_rtx)
9771 old_pat = PATTERN (insn);
9772 old_notes = REG_NOTES (insn);
9773 PATTERN (insn) = pat;
9774 REG_NOTES (insn) = 0;
9776 insn_code_number = recog (pat, insn, &num_clobbers_to_add);
9777 if (dump_file && (dump_flags & TDF_DETAILS))
9779 if (insn_code_number < 0)
9780 fputs ("Failed to match this instruction:\n", dump_file);
9782 fputs ("Successfully matched this instruction:\n", dump_file);
9783 print_rtl_single (dump_file, pat);
9786 /* If it isn't, there is the possibility that we previously had an insn
9787 that clobbered some register as a side effect, but the combined
9788 insn doesn't need to do that. So try once more without the clobbers
9789 unless this represents an ASM insn. */
9791 if (insn_code_number < 0 && ! check_asm_operands (pat)
9792 && GET_CODE (pat) == PARALLEL)
9796 for (pos = 0, i = 0; i < XVECLEN (pat, 0); i++)
9797 if (GET_CODE (XVECEXP (pat, 0, i)) != CLOBBER)
9800 SUBST (XVECEXP (pat, 0, pos), XVECEXP (pat, 0, i));
9804 SUBST_INT (XVECLEN (pat, 0), pos);
9807 pat = XVECEXP (pat, 0, 0);
9809 PATTERN (insn) = pat;
9810 insn_code_number = recog (pat, insn, &num_clobbers_to_add);
9811 if (dump_file && (dump_flags & TDF_DETAILS))
9813 if (insn_code_number < 0)
9814 fputs ("Failed to match this instruction:\n", dump_file);
9816 fputs ("Successfully matched this instruction:\n", dump_file);
9817 print_rtl_single (dump_file, pat);
9820 PATTERN (insn) = old_pat;
9821 REG_NOTES (insn) = old_notes;
9823 /* Recognize all noop sets, these will be killed by followup pass. */
9824 if (insn_code_number < 0 && GET_CODE (pat) == SET && set_noop_p (pat))
9825 insn_code_number = NOOP_MOVE_INSN_CODE, num_clobbers_to_add = 0;
9827 /* If we had any clobbers to add, make a new pattern than contains
9828 them. Then check to make sure that all of them are dead. */
9829 if (num_clobbers_to_add)
9831 rtx newpat = gen_rtx_PARALLEL (VOIDmode,
9832 rtvec_alloc (GET_CODE (pat) == PARALLEL
9834 + num_clobbers_to_add)
9835 : num_clobbers_to_add + 1));
9837 if (GET_CODE (pat) == PARALLEL)
9838 for (i = 0; i < XVECLEN (pat, 0); i++)
9839 XVECEXP (newpat, 0, i) = XVECEXP (pat, 0, i);
9841 XVECEXP (newpat, 0, 0) = pat;
9843 add_clobbers (newpat, insn_code_number);
9845 for (i = XVECLEN (newpat, 0) - num_clobbers_to_add;
9846 i < XVECLEN (newpat, 0); i++)
9848 if (REG_P (XEXP (XVECEXP (newpat, 0, i), 0))
9849 && ! reg_dead_at_p (XEXP (XVECEXP (newpat, 0, i), 0), insn))
9851 if (GET_CODE (XEXP (XVECEXP (newpat, 0, i), 0)) != SCRATCH)
9853 gcc_assert (REG_P (XEXP (XVECEXP (newpat, 0, i), 0)));
9854 notes = gen_rtx_EXPR_LIST (REG_UNUSED,
9855 XEXP (XVECEXP (newpat, 0, i), 0), notes);
9864 return insn_code_number;
9867 /* Like gen_lowpart_general but for use by combine. In combine it
9868 is not possible to create any new pseudoregs. However, it is
9869 safe to create invalid memory addresses, because combine will
9870 try to recognize them and all they will do is make the combine
9873 If for some reason this cannot do its job, an rtx
9874 (clobber (const_int 0)) is returned.
9875 An insn containing that will not be recognized. */
9878 gen_lowpart_for_combine (enum machine_mode omode, rtx x)
9880 enum machine_mode imode = GET_MODE (x);
9881 unsigned int osize = GET_MODE_SIZE (omode);
9882 unsigned int isize = GET_MODE_SIZE (imode);
9888 /* Return identity if this is a CONST or symbolic reference. */
9890 && (GET_CODE (x) == CONST
9891 || GET_CODE (x) == SYMBOL_REF
9892 || GET_CODE (x) == LABEL_REF))
9895 /* We can only support MODE being wider than a word if X is a
9896 constant integer or has a mode the same size. */
9897 if (GET_MODE_SIZE (omode) > UNITS_PER_WORD
9898 && ! ((imode == VOIDmode
9899 && (GET_CODE (x) == CONST_INT
9900 || GET_CODE (x) == CONST_DOUBLE))
9904 /* X might be a paradoxical (subreg (mem)). In that case, gen_lowpart
9905 won't know what to do. So we will strip off the SUBREG here and
9906 process normally. */
9907 if (GET_CODE (x) == SUBREG && MEM_P (SUBREG_REG (x)))
9911 /* For use in case we fall down into the address adjustments
9912 further below, we need to adjust the known mode and size of
9913 x; imode and isize, since we just adjusted x. */
9914 imode = GET_MODE (x);
9919 isize = GET_MODE_SIZE (imode);
9922 result = gen_lowpart_common (omode, x);
9931 /* Refuse to work on a volatile memory ref or one with a mode-dependent
9933 if (MEM_VOLATILE_P (x) || mode_dependent_address_p (XEXP (x, 0)))
9936 /* If we want to refer to something bigger than the original memref,
9937 generate a paradoxical subreg instead. That will force a reload
9938 of the original memref X. */
9940 return gen_rtx_SUBREG (omode, x, 0);
9942 if (WORDS_BIG_ENDIAN)
9943 offset = MAX (isize, UNITS_PER_WORD) - MAX (osize, UNITS_PER_WORD);
9945 /* Adjust the address so that the address-after-the-data is
9947 if (BYTES_BIG_ENDIAN)
9948 offset -= MIN (UNITS_PER_WORD, osize) - MIN (UNITS_PER_WORD, isize);
9950 return adjust_address_nv (x, omode, offset);
9953 /* If X is a comparison operator, rewrite it in a new mode. This
9954 probably won't match, but may allow further simplifications. */
9955 else if (COMPARISON_P (x))
9956 return gen_rtx_fmt_ee (GET_CODE (x), omode, XEXP (x, 0), XEXP (x, 1));
9958 /* If we couldn't simplify X any other way, just enclose it in a
9959 SUBREG. Normally, this SUBREG won't match, but some patterns may
9960 include an explicit SUBREG or we may simplify it further in combine. */
9966 offset = subreg_lowpart_offset (omode, imode);
9967 if (imode == VOIDmode)
9969 imode = int_mode_for_mode (omode);
9970 x = gen_lowpart_common (imode, x);
9974 res = simplify_gen_subreg (omode, x, imode, offset);
9980 return gen_rtx_CLOBBER (imode, const0_rtx);
9983 /* Simplify a comparison between *POP0 and *POP1 where CODE is the
9984 comparison code that will be tested.
9986 The result is a possibly different comparison code to use. *POP0 and
9987 *POP1 may be updated.
9989 It is possible that we might detect that a comparison is either always
9990 true or always false. However, we do not perform general constant
9991 folding in combine, so this knowledge isn't useful. Such tautologies
9992 should have been detected earlier. Hence we ignore all such cases. */
9994 static enum rtx_code
9995 simplify_comparison (enum rtx_code code, rtx *pop0, rtx *pop1)
10001 enum machine_mode mode, tmode;
10003 /* Try a few ways of applying the same transformation to both operands. */
10006 #ifndef WORD_REGISTER_OPERATIONS
10007 /* The test below this one won't handle SIGN_EXTENDs on these machines,
10008 so check specially. */
10009 if (code != GTU && code != GEU && code != LTU && code != LEU
10010 && GET_CODE (op0) == ASHIFTRT && GET_CODE (op1) == ASHIFTRT
10011 && GET_CODE (XEXP (op0, 0)) == ASHIFT
10012 && GET_CODE (XEXP (op1, 0)) == ASHIFT
10013 && GET_CODE (XEXP (XEXP (op0, 0), 0)) == SUBREG
10014 && GET_CODE (XEXP (XEXP (op1, 0), 0)) == SUBREG
10015 && (GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0)))
10016 == GET_MODE (SUBREG_REG (XEXP (XEXP (op1, 0), 0))))
10017 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10018 && XEXP (op0, 1) == XEXP (op1, 1)
10019 && XEXP (op0, 1) == XEXP (XEXP (op0, 0), 1)
10020 && XEXP (op0, 1) == XEXP (XEXP (op1, 0), 1)
10021 && (INTVAL (XEXP (op0, 1))
10022 == (GET_MODE_BITSIZE (GET_MODE (op0))
10023 - (GET_MODE_BITSIZE
10024 (GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0))))))))
10026 op0 = SUBREG_REG (XEXP (XEXP (op0, 0), 0));
10027 op1 = SUBREG_REG (XEXP (XEXP (op1, 0), 0));
10031 /* If both operands are the same constant shift, see if we can ignore the
10032 shift. We can if the shift is a rotate or if the bits shifted out of
10033 this shift are known to be zero for both inputs and if the type of
10034 comparison is compatible with the shift. */
10035 if (GET_CODE (op0) == GET_CODE (op1)
10036 && GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
10037 && ((GET_CODE (op0) == ROTATE && (code == NE || code == EQ))
10038 || ((GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFT)
10039 && (code != GT && code != LT && code != GE && code != LE))
10040 || (GET_CODE (op0) == ASHIFTRT
10041 && (code != GTU && code != LTU
10042 && code != GEU && code != LEU)))
10043 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10044 && INTVAL (XEXP (op0, 1)) >= 0
10045 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT
10046 && XEXP (op0, 1) == XEXP (op1, 1))
10048 enum machine_mode mode = GET_MODE (op0);
10049 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
10050 int shift_count = INTVAL (XEXP (op0, 1));
10052 if (GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFTRT)
10053 mask &= (mask >> shift_count) << shift_count;
10054 else if (GET_CODE (op0) == ASHIFT)
10055 mask = (mask & (mask << shift_count)) >> shift_count;
10057 if ((nonzero_bits (XEXP (op0, 0), mode) & ~mask) == 0
10058 && (nonzero_bits (XEXP (op1, 0), mode) & ~mask) == 0)
10059 op0 = XEXP (op0, 0), op1 = XEXP (op1, 0);
10064 /* If both operands are AND's of a paradoxical SUBREG by constant, the
10065 SUBREGs are of the same mode, and, in both cases, the AND would
10066 be redundant if the comparison was done in the narrower mode,
10067 do the comparison in the narrower mode (e.g., we are AND'ing with 1
10068 and the operand's possibly nonzero bits are 0xffffff01; in that case
10069 if we only care about QImode, we don't need the AND). This case
10070 occurs if the output mode of an scc insn is not SImode and
10071 STORE_FLAG_VALUE == 1 (e.g., the 386).
10073 Similarly, check for a case where the AND's are ZERO_EXTEND
10074 operations from some narrower mode even though a SUBREG is not
10077 else if (GET_CODE (op0) == AND && GET_CODE (op1) == AND
10078 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10079 && GET_CODE (XEXP (op1, 1)) == CONST_INT)
10081 rtx inner_op0 = XEXP (op0, 0);
10082 rtx inner_op1 = XEXP (op1, 0);
10083 HOST_WIDE_INT c0 = INTVAL (XEXP (op0, 1));
10084 HOST_WIDE_INT c1 = INTVAL (XEXP (op1, 1));
10087 if (GET_CODE (inner_op0) == SUBREG && GET_CODE (inner_op1) == SUBREG
10088 && (GET_MODE_SIZE (GET_MODE (inner_op0))
10089 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (inner_op0))))
10090 && (GET_MODE (SUBREG_REG (inner_op0))
10091 == GET_MODE (SUBREG_REG (inner_op1)))
10092 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (inner_op0)))
10093 <= HOST_BITS_PER_WIDE_INT)
10094 && (0 == ((~c0) & nonzero_bits (SUBREG_REG (inner_op0),
10095 GET_MODE (SUBREG_REG (inner_op0)))))
10096 && (0 == ((~c1) & nonzero_bits (SUBREG_REG (inner_op1),
10097 GET_MODE (SUBREG_REG (inner_op1))))))
10099 op0 = SUBREG_REG (inner_op0);
10100 op1 = SUBREG_REG (inner_op1);
10102 /* The resulting comparison is always unsigned since we masked
10103 off the original sign bit. */
10104 code = unsigned_condition (code);
10110 for (tmode = GET_CLASS_NARROWEST_MODE
10111 (GET_MODE_CLASS (GET_MODE (op0)));
10112 tmode != GET_MODE (op0); tmode = GET_MODE_WIDER_MODE (tmode))
10113 if ((unsigned HOST_WIDE_INT) c0 == GET_MODE_MASK (tmode))
10115 op0 = gen_lowpart (tmode, inner_op0);
10116 op1 = gen_lowpart (tmode, inner_op1);
10117 code = unsigned_condition (code);
10126 /* If both operands are NOT, we can strip off the outer operation
10127 and adjust the comparison code for swapped operands; similarly for
10128 NEG, except that this must be an equality comparison. */
10129 else if ((GET_CODE (op0) == NOT && GET_CODE (op1) == NOT)
10130 || (GET_CODE (op0) == NEG && GET_CODE (op1) == NEG
10131 && (code == EQ || code == NE)))
10132 op0 = XEXP (op0, 0), op1 = XEXP (op1, 0), code = swap_condition (code);
10138 /* If the first operand is a constant, swap the operands and adjust the
10139 comparison code appropriately, but don't do this if the second operand
10140 is already a constant integer. */
10141 if (swap_commutative_operands_p (op0, op1))
10143 tem = op0, op0 = op1, op1 = tem;
10144 code = swap_condition (code);
10147 /* We now enter a loop during which we will try to simplify the comparison.
10148 For the most part, we only are concerned with comparisons with zero,
10149 but some things may really be comparisons with zero but not start
10150 out looking that way. */
10152 while (GET_CODE (op1) == CONST_INT)
10154 enum machine_mode mode = GET_MODE (op0);
10155 unsigned int mode_width = GET_MODE_BITSIZE (mode);
10156 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
10157 int equality_comparison_p;
10158 int sign_bit_comparison_p;
10159 int unsigned_comparison_p;
10160 HOST_WIDE_INT const_op;
10162 /* We only want to handle integral modes. This catches VOIDmode,
10163 CCmode, and the floating-point modes. An exception is that we
10164 can handle VOIDmode if OP0 is a COMPARE or a comparison
10167 if (GET_MODE_CLASS (mode) != MODE_INT
10168 && ! (mode == VOIDmode
10169 && (GET_CODE (op0) == COMPARE || COMPARISON_P (op0))))
10172 /* Get the constant we are comparing against and turn off all bits
10173 not on in our mode. */
10174 const_op = INTVAL (op1);
10175 if (mode != VOIDmode)
10176 const_op = trunc_int_for_mode (const_op, mode);
10177 op1 = GEN_INT (const_op);
10179 /* If we are comparing against a constant power of two and the value
10180 being compared can only have that single bit nonzero (e.g., it was
10181 `and'ed with that bit), we can replace this with a comparison
10184 && (code == EQ || code == NE || code == GE || code == GEU
10185 || code == LT || code == LTU)
10186 && mode_width <= HOST_BITS_PER_WIDE_INT
10187 && exact_log2 (const_op) >= 0
10188 && nonzero_bits (op0, mode) == (unsigned HOST_WIDE_INT) const_op)
10190 code = (code == EQ || code == GE || code == GEU ? NE : EQ);
10191 op1 = const0_rtx, const_op = 0;
10194 /* Similarly, if we are comparing a value known to be either -1 or
10195 0 with -1, change it to the opposite comparison against zero. */
10198 && (code == EQ || code == NE || code == GT || code == LE
10199 || code == GEU || code == LTU)
10200 && num_sign_bit_copies (op0, mode) == mode_width)
10202 code = (code == EQ || code == LE || code == GEU ? NE : EQ);
10203 op1 = const0_rtx, const_op = 0;
10206 /* Do some canonicalizations based on the comparison code. We prefer
10207 comparisons against zero and then prefer equality comparisons.
10208 If we can reduce the size of a constant, we will do that too. */
10213 /* < C is equivalent to <= (C - 1) */
10217 op1 = GEN_INT (const_op);
10219 /* ... fall through to LE case below. */
10225 /* <= C is equivalent to < (C + 1); we do this for C < 0 */
10229 op1 = GEN_INT (const_op);
10233 /* If we are doing a <= 0 comparison on a value known to have
10234 a zero sign bit, we can replace this with == 0. */
10235 else if (const_op == 0
10236 && mode_width <= HOST_BITS_PER_WIDE_INT
10237 && (nonzero_bits (op0, mode)
10238 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)
10243 /* >= C is equivalent to > (C - 1). */
10247 op1 = GEN_INT (const_op);
10249 /* ... fall through to GT below. */
10255 /* > C is equivalent to >= (C + 1); we do this for C < 0. */
10259 op1 = GEN_INT (const_op);
10263 /* If we are doing a > 0 comparison on a value known to have
10264 a zero sign bit, we can replace this with != 0. */
10265 else if (const_op == 0
10266 && mode_width <= HOST_BITS_PER_WIDE_INT
10267 && (nonzero_bits (op0, mode)
10268 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)
10273 /* < C is equivalent to <= (C - 1). */
10277 op1 = GEN_INT (const_op);
10279 /* ... fall through ... */
10282 /* (unsigned) < 0x80000000 is equivalent to >= 0. */
10283 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
10284 && (const_op == (HOST_WIDE_INT) 1 << (mode_width - 1)))
10286 const_op = 0, op1 = const0_rtx;
10294 /* unsigned <= 0 is equivalent to == 0 */
10298 /* (unsigned) <= 0x7fffffff is equivalent to >= 0. */
10299 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
10300 && (const_op == ((HOST_WIDE_INT) 1 << (mode_width - 1)) - 1))
10302 const_op = 0, op1 = const0_rtx;
10308 /* >= C is equivalent to > (C - 1). */
10312 op1 = GEN_INT (const_op);
10314 /* ... fall through ... */
10317 /* (unsigned) >= 0x80000000 is equivalent to < 0. */
10318 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
10319 && (const_op == (HOST_WIDE_INT) 1 << (mode_width - 1)))
10321 const_op = 0, op1 = const0_rtx;
10329 /* unsigned > 0 is equivalent to != 0 */
10333 /* (unsigned) > 0x7fffffff is equivalent to < 0. */
10334 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
10335 && (const_op == ((HOST_WIDE_INT) 1 << (mode_width - 1)) - 1))
10337 const_op = 0, op1 = const0_rtx;
10346 /* Compute some predicates to simplify code below. */
10348 equality_comparison_p = (code == EQ || code == NE);
10349 sign_bit_comparison_p = ((code == LT || code == GE) && const_op == 0);
10350 unsigned_comparison_p = (code == LTU || code == LEU || code == GTU
10353 /* If this is a sign bit comparison and we can do arithmetic in
10354 MODE, say that we will only be needing the sign bit of OP0. */
10355 if (sign_bit_comparison_p
10356 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
10357 op0 = force_to_mode (op0, mode,
10359 << (GET_MODE_BITSIZE (mode) - 1)),
10362 /* Now try cases based on the opcode of OP0. If none of the cases
10363 does a "continue", we exit this loop immediately after the
10366 switch (GET_CODE (op0))
10369 /* If we are extracting a single bit from a variable position in
10370 a constant that has only a single bit set and are comparing it
10371 with zero, we can convert this into an equality comparison
10372 between the position and the location of the single bit. */
10373 /* Except we can't if SHIFT_COUNT_TRUNCATED is set, since we might
10374 have already reduced the shift count modulo the word size. */
10375 if (!SHIFT_COUNT_TRUNCATED
10376 && GET_CODE (XEXP (op0, 0)) == CONST_INT
10377 && XEXP (op0, 1) == const1_rtx
10378 && equality_comparison_p && const_op == 0
10379 && (i = exact_log2 (INTVAL (XEXP (op0, 0)))) >= 0)
10381 if (BITS_BIG_ENDIAN)
10383 enum machine_mode new_mode
10384 = mode_for_extraction (EP_extzv, 1);
10385 if (new_mode == MAX_MACHINE_MODE)
10386 i = BITS_PER_WORD - 1 - i;
10390 i = (GET_MODE_BITSIZE (mode) - 1 - i);
10394 op0 = XEXP (op0, 2);
10398 /* Result is nonzero iff shift count is equal to I. */
10399 code = reverse_condition (code);
10403 /* ... fall through ... */
10406 tem = expand_compound_operation (op0);
10415 /* If testing for equality, we can take the NOT of the constant. */
10416 if (equality_comparison_p
10417 && (tem = simplify_unary_operation (NOT, mode, op1, mode)) != 0)
10419 op0 = XEXP (op0, 0);
10424 /* If just looking at the sign bit, reverse the sense of the
10426 if (sign_bit_comparison_p)
10428 op0 = XEXP (op0, 0);
10429 code = (code == GE ? LT : GE);
10435 /* If testing for equality, we can take the NEG of the constant. */
10436 if (equality_comparison_p
10437 && (tem = simplify_unary_operation (NEG, mode, op1, mode)) != 0)
10439 op0 = XEXP (op0, 0);
10444 /* The remaining cases only apply to comparisons with zero. */
10448 /* When X is ABS or is known positive,
10449 (neg X) is < 0 if and only if X != 0. */
10451 if (sign_bit_comparison_p
10452 && (GET_CODE (XEXP (op0, 0)) == ABS
10453 || (mode_width <= HOST_BITS_PER_WIDE_INT
10454 && (nonzero_bits (XEXP (op0, 0), mode)
10455 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)))
10457 op0 = XEXP (op0, 0);
10458 code = (code == LT ? NE : EQ);
10462 /* If we have NEG of something whose two high-order bits are the
10463 same, we know that "(-a) < 0" is equivalent to "a > 0". */
10464 if (num_sign_bit_copies (op0, mode) >= 2)
10466 op0 = XEXP (op0, 0);
10467 code = swap_condition (code);
10473 /* If we are testing equality and our count is a constant, we
10474 can perform the inverse operation on our RHS. */
10475 if (equality_comparison_p && GET_CODE (XEXP (op0, 1)) == CONST_INT
10476 && (tem = simplify_binary_operation (ROTATERT, mode,
10477 op1, XEXP (op0, 1))) != 0)
10479 op0 = XEXP (op0, 0);
10484 /* If we are doing a < 0 or >= 0 comparison, it means we are testing
10485 a particular bit. Convert it to an AND of a constant of that
10486 bit. This will be converted into a ZERO_EXTRACT. */
10487 if (const_op == 0 && sign_bit_comparison_p
10488 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10489 && mode_width <= HOST_BITS_PER_WIDE_INT)
10491 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
10494 - INTVAL (XEXP (op0, 1)))));
10495 code = (code == LT ? NE : EQ);
10499 /* Fall through. */
10502 /* ABS is ignorable inside an equality comparison with zero. */
10503 if (const_op == 0 && equality_comparison_p)
10505 op0 = XEXP (op0, 0);
10511 /* Can simplify (compare (zero/sign_extend FOO) CONST) to
10512 (compare FOO CONST) if CONST fits in FOO's mode and we
10513 are either testing inequality or have an unsigned
10514 comparison with ZERO_EXTEND or a signed comparison with
10515 SIGN_EXTEND. But don't do it if we don't have a compare
10516 insn of the given mode, since we'd have to revert it
10517 later on, and then we wouldn't know whether to sign- or
10519 mode = GET_MODE (XEXP (op0, 0));
10520 if (mode != VOIDmode && GET_MODE_CLASS (mode) == MODE_INT
10521 && ! unsigned_comparison_p
10522 && (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
10523 && ((unsigned HOST_WIDE_INT) const_op
10524 < (((unsigned HOST_WIDE_INT) 1
10525 << (GET_MODE_BITSIZE (mode) - 1))))
10526 && optab_handler (cmp_optab, mode)->insn_code != CODE_FOR_nothing)
10528 op0 = XEXP (op0, 0);
10534 /* Check for the case where we are comparing A - C1 with C2, that is
10536 (subreg:MODE (plus (A) (-C1))) op (C2)
10538 with C1 a constant, and try to lift the SUBREG, i.e. to do the
10539 comparison in the wider mode. One of the following two conditions
10540 must be true in order for this to be valid:
10542 1. The mode extension results in the same bit pattern being added
10543 on both sides and the comparison is equality or unsigned. As
10544 C2 has been truncated to fit in MODE, the pattern can only be
10547 2. The mode extension results in the sign bit being copied on
10550 The difficulty here is that we have predicates for A but not for
10551 (A - C1) so we need to check that C1 is within proper bounds so
10552 as to perturbate A as little as possible. */
10554 if (mode_width <= HOST_BITS_PER_WIDE_INT
10555 && subreg_lowpart_p (op0)
10556 && GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0))) > mode_width
10557 && GET_CODE (SUBREG_REG (op0)) == PLUS
10558 && GET_CODE (XEXP (SUBREG_REG (op0), 1)) == CONST_INT)
10560 enum machine_mode inner_mode = GET_MODE (SUBREG_REG (op0));
10561 rtx a = XEXP (SUBREG_REG (op0), 0);
10562 HOST_WIDE_INT c1 = -INTVAL (XEXP (SUBREG_REG (op0), 1));
10565 && (unsigned HOST_WIDE_INT) c1
10566 < (unsigned HOST_WIDE_INT) 1 << (mode_width - 1)
10567 && (equality_comparison_p || unsigned_comparison_p)
10568 /* (A - C1) zero-extends if it is positive and sign-extends
10569 if it is negative, C2 both zero- and sign-extends. */
10570 && ((0 == (nonzero_bits (a, inner_mode)
10571 & ~GET_MODE_MASK (mode))
10573 /* (A - C1) sign-extends if it is positive and 1-extends
10574 if it is negative, C2 both sign- and 1-extends. */
10575 || (num_sign_bit_copies (a, inner_mode)
10576 > (unsigned int) (GET_MODE_BITSIZE (inner_mode)
10579 || ((unsigned HOST_WIDE_INT) c1
10580 < (unsigned HOST_WIDE_INT) 1 << (mode_width - 2)
10581 /* (A - C1) always sign-extends, like C2. */
10582 && num_sign_bit_copies (a, inner_mode)
10583 > (unsigned int) (GET_MODE_BITSIZE (inner_mode)
10584 - (mode_width - 1))))
10586 op0 = SUBREG_REG (op0);
10591 /* If the inner mode is narrower and we are extracting the low part,
10592 we can treat the SUBREG as if it were a ZERO_EXTEND. */
10593 if (subreg_lowpart_p (op0)
10594 && GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0))) < mode_width)
10595 /* Fall through */ ;
10599 /* ... fall through ... */
10602 mode = GET_MODE (XEXP (op0, 0));
10603 if (mode != VOIDmode && GET_MODE_CLASS (mode) == MODE_INT
10604 && (unsigned_comparison_p || equality_comparison_p)
10605 && (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
10606 && ((unsigned HOST_WIDE_INT) const_op < GET_MODE_MASK (mode))
10607 && optab_handler (cmp_optab, mode)->insn_code != CODE_FOR_nothing)
10609 op0 = XEXP (op0, 0);
10615 /* (eq (plus X A) B) -> (eq X (minus B A)). We can only do
10616 this for equality comparisons due to pathological cases involving
10618 if (equality_comparison_p
10619 && 0 != (tem = simplify_binary_operation (MINUS, mode,
10620 op1, XEXP (op0, 1))))
10622 op0 = XEXP (op0, 0);
10627 /* (plus (abs X) (const_int -1)) is < 0 if and only if X == 0. */
10628 if (const_op == 0 && XEXP (op0, 1) == constm1_rtx
10629 && GET_CODE (XEXP (op0, 0)) == ABS && sign_bit_comparison_p)
10631 op0 = XEXP (XEXP (op0, 0), 0);
10632 code = (code == LT ? EQ : NE);
10638 /* We used to optimize signed comparisons against zero, but that
10639 was incorrect. Unsigned comparisons against zero (GTU, LEU)
10640 arrive here as equality comparisons, or (GEU, LTU) are
10641 optimized away. No need to special-case them. */
10643 /* (eq (minus A B) C) -> (eq A (plus B C)) or
10644 (eq B (minus A C)), whichever simplifies. We can only do
10645 this for equality comparisons due to pathological cases involving
10647 if (equality_comparison_p
10648 && 0 != (tem = simplify_binary_operation (PLUS, mode,
10649 XEXP (op0, 1), op1)))
10651 op0 = XEXP (op0, 0);
10656 if (equality_comparison_p
10657 && 0 != (tem = simplify_binary_operation (MINUS, mode,
10658 XEXP (op0, 0), op1)))
10660 op0 = XEXP (op0, 1);
10665 /* The sign bit of (minus (ashiftrt X C) X), where C is the number
10666 of bits in X minus 1, is one iff X > 0. */
10667 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == ASHIFTRT
10668 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
10669 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (XEXP (op0, 0), 1))
10671 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
10673 op0 = XEXP (op0, 1);
10674 code = (code == GE ? LE : GT);
10680 /* (eq (xor A B) C) -> (eq A (xor B C)). This is a simplification
10681 if C is zero or B is a constant. */
10682 if (equality_comparison_p
10683 && 0 != (tem = simplify_binary_operation (XOR, mode,
10684 XEXP (op0, 1), op1)))
10686 op0 = XEXP (op0, 0);
10693 case UNEQ: case LTGT:
10694 case LT: case LTU: case UNLT: case LE: case LEU: case UNLE:
10695 case GT: case GTU: case UNGT: case GE: case GEU: case UNGE:
10696 case UNORDERED: case ORDERED:
10697 /* We can't do anything if OP0 is a condition code value, rather
10698 than an actual data value. */
10700 || CC0_P (XEXP (op0, 0))
10701 || GET_MODE_CLASS (GET_MODE (XEXP (op0, 0))) == MODE_CC)
10704 /* Get the two operands being compared. */
10705 if (GET_CODE (XEXP (op0, 0)) == COMPARE)
10706 tem = XEXP (XEXP (op0, 0), 0), tem1 = XEXP (XEXP (op0, 0), 1);
10708 tem = XEXP (op0, 0), tem1 = XEXP (op0, 1);
10710 /* Check for the cases where we simply want the result of the
10711 earlier test or the opposite of that result. */
10712 if (code == NE || code == EQ
10713 || (GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
10714 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
10715 && (STORE_FLAG_VALUE
10716 & (((HOST_WIDE_INT) 1
10717 << (GET_MODE_BITSIZE (GET_MODE (op0)) - 1))))
10718 && (code == LT || code == GE)))
10720 enum rtx_code new_code;
10721 if (code == LT || code == NE)
10722 new_code = GET_CODE (op0);
10724 new_code = reversed_comparison_code (op0, NULL);
10726 if (new_code != UNKNOWN)
10737 /* The sign bit of (ior (plus X (const_int -1)) X) is nonzero
10739 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == PLUS
10740 && XEXP (XEXP (op0, 0), 1) == constm1_rtx
10741 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
10743 op0 = XEXP (op0, 1);
10744 code = (code == GE ? GT : LE);
10750 /* Convert (and (xshift 1 X) Y) to (and (lshiftrt Y X) 1). This
10751 will be converted to a ZERO_EXTRACT later. */
10752 if (const_op == 0 && equality_comparison_p
10753 && GET_CODE (XEXP (op0, 0)) == ASHIFT
10754 && XEXP (XEXP (op0, 0), 0) == const1_rtx)
10756 op0 = simplify_and_const_int
10757 (NULL_RTX, mode, gen_rtx_LSHIFTRT (mode,
10759 XEXP (XEXP (op0, 0), 1)),
10760 (HOST_WIDE_INT) 1);
10764 /* If we are comparing (and (lshiftrt X C1) C2) for equality with
10765 zero and X is a comparison and C1 and C2 describe only bits set
10766 in STORE_FLAG_VALUE, we can compare with X. */
10767 if (const_op == 0 && equality_comparison_p
10768 && mode_width <= HOST_BITS_PER_WIDE_INT
10769 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10770 && GET_CODE (XEXP (op0, 0)) == LSHIFTRT
10771 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
10772 && INTVAL (XEXP (XEXP (op0, 0), 1)) >= 0
10773 && INTVAL (XEXP (XEXP (op0, 0), 1)) < HOST_BITS_PER_WIDE_INT)
10775 mask = ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
10776 << INTVAL (XEXP (XEXP (op0, 0), 1)));
10777 if ((~STORE_FLAG_VALUE & mask) == 0
10778 && (COMPARISON_P (XEXP (XEXP (op0, 0), 0))
10779 || ((tem = get_last_value (XEXP (XEXP (op0, 0), 0))) != 0
10780 && COMPARISON_P (tem))))
10782 op0 = XEXP (XEXP (op0, 0), 0);
10787 /* If we are doing an equality comparison of an AND of a bit equal
10788 to the sign bit, replace this with a LT or GE comparison of
10789 the underlying value. */
10790 if (equality_comparison_p
10792 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10793 && mode_width <= HOST_BITS_PER_WIDE_INT
10794 && ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
10795 == (unsigned HOST_WIDE_INT) 1 << (mode_width - 1)))
10797 op0 = XEXP (op0, 0);
10798 code = (code == EQ ? GE : LT);
10802 /* If this AND operation is really a ZERO_EXTEND from a narrower
10803 mode, the constant fits within that mode, and this is either an
10804 equality or unsigned comparison, try to do this comparison in
10809 (ne:DI (and:DI (reg:DI 4) (const_int 0xffffffff)) (const_int 0))
10810 -> (ne:DI (reg:SI 4) (const_int 0))
10812 unless TRULY_NOOP_TRUNCATION allows it or the register is
10813 known to hold a value of the required mode the
10814 transformation is invalid. */
10815 if ((equality_comparison_p || unsigned_comparison_p)
10816 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10817 && (i = exact_log2 ((INTVAL (XEXP (op0, 1))
10818 & GET_MODE_MASK (mode))
10820 && const_op >> i == 0
10821 && (tmode = mode_for_size (i, MODE_INT, 1)) != BLKmode
10822 && (TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (tmode),
10823 GET_MODE_BITSIZE (GET_MODE (op0)))
10824 || (REG_P (XEXP (op0, 0))
10825 && reg_truncated_to_mode (tmode, XEXP (op0, 0)))))
10827 op0 = gen_lowpart (tmode, XEXP (op0, 0));
10831 /* If this is (and:M1 (subreg:M2 X 0) (const_int C1)) where C1
10832 fits in both M1 and M2 and the SUBREG is either paradoxical
10833 or represents the low part, permute the SUBREG and the AND
10835 if (GET_CODE (XEXP (op0, 0)) == SUBREG)
10837 unsigned HOST_WIDE_INT c1;
10838 tmode = GET_MODE (SUBREG_REG (XEXP (op0, 0)));
10839 /* Require an integral mode, to avoid creating something like
10841 if (SCALAR_INT_MODE_P (tmode)
10842 /* It is unsafe to commute the AND into the SUBREG if the
10843 SUBREG is paradoxical and WORD_REGISTER_OPERATIONS is
10844 not defined. As originally written the upper bits
10845 have a defined value due to the AND operation.
10846 However, if we commute the AND inside the SUBREG then
10847 they no longer have defined values and the meaning of
10848 the code has been changed. */
10850 #ifdef WORD_REGISTER_OPERATIONS
10851 || (mode_width > GET_MODE_BITSIZE (tmode)
10852 && mode_width <= BITS_PER_WORD)
10854 || (mode_width <= GET_MODE_BITSIZE (tmode)
10855 && subreg_lowpart_p (XEXP (op0, 0))))
10856 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10857 && mode_width <= HOST_BITS_PER_WIDE_INT
10858 && GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT
10859 && ((c1 = INTVAL (XEXP (op0, 1))) & ~mask) == 0
10860 && (c1 & ~GET_MODE_MASK (tmode)) == 0
10862 && c1 != GET_MODE_MASK (tmode))
10864 op0 = simplify_gen_binary (AND, tmode,
10865 SUBREG_REG (XEXP (op0, 0)),
10866 gen_int_mode (c1, tmode));
10867 op0 = gen_lowpart (mode, op0);
10872 /* Convert (ne (and (not X) 1) 0) to (eq (and X 1) 0). */
10873 if (const_op == 0 && equality_comparison_p
10874 && XEXP (op0, 1) == const1_rtx
10875 && GET_CODE (XEXP (op0, 0)) == NOT)
10877 op0 = simplify_and_const_int
10878 (NULL_RTX, mode, XEXP (XEXP (op0, 0), 0), (HOST_WIDE_INT) 1);
10879 code = (code == NE ? EQ : NE);
10883 /* Convert (ne (and (lshiftrt (not X)) 1) 0) to
10884 (eq (and (lshiftrt X) 1) 0).
10885 Also handle the case where (not X) is expressed using xor. */
10886 if (const_op == 0 && equality_comparison_p
10887 && XEXP (op0, 1) == const1_rtx
10888 && GET_CODE (XEXP (op0, 0)) == LSHIFTRT)
10890 rtx shift_op = XEXP (XEXP (op0, 0), 0);
10891 rtx shift_count = XEXP (XEXP (op0, 0), 1);
10893 if (GET_CODE (shift_op) == NOT
10894 || (GET_CODE (shift_op) == XOR
10895 && GET_CODE (XEXP (shift_op, 1)) == CONST_INT
10896 && GET_CODE (shift_count) == CONST_INT
10897 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
10898 && (INTVAL (XEXP (shift_op, 1))
10899 == (HOST_WIDE_INT) 1 << INTVAL (shift_count))))
10901 op0 = simplify_and_const_int
10903 gen_rtx_LSHIFTRT (mode, XEXP (shift_op, 0), shift_count),
10904 (HOST_WIDE_INT) 1);
10905 code = (code == NE ? EQ : NE);
10912 /* If we have (compare (ashift FOO N) (const_int C)) and
10913 the high order N bits of FOO (N+1 if an inequality comparison)
10914 are known to be zero, we can do this by comparing FOO with C
10915 shifted right N bits so long as the low-order N bits of C are
10917 if (GET_CODE (XEXP (op0, 1)) == CONST_INT
10918 && INTVAL (XEXP (op0, 1)) >= 0
10919 && ((INTVAL (XEXP (op0, 1)) + ! equality_comparison_p)
10920 < HOST_BITS_PER_WIDE_INT)
10922 & (((HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1))) - 1)) == 0)
10923 && mode_width <= HOST_BITS_PER_WIDE_INT
10924 && (nonzero_bits (XEXP (op0, 0), mode)
10925 & ~(mask >> (INTVAL (XEXP (op0, 1))
10926 + ! equality_comparison_p))) == 0)
10928 /* We must perform a logical shift, not an arithmetic one,
10929 as we want the top N bits of C to be zero. */
10930 unsigned HOST_WIDE_INT temp = const_op & GET_MODE_MASK (mode);
10932 temp >>= INTVAL (XEXP (op0, 1));
10933 op1 = gen_int_mode (temp, mode);
10934 op0 = XEXP (op0, 0);
10938 /* If we are doing a sign bit comparison, it means we are testing
10939 a particular bit. Convert it to the appropriate AND. */
10940 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 1)) == CONST_INT
10941 && mode_width <= HOST_BITS_PER_WIDE_INT)
10943 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
10946 - INTVAL (XEXP (op0, 1)))));
10947 code = (code == LT ? NE : EQ);
10951 /* If this an equality comparison with zero and we are shifting
10952 the low bit to the sign bit, we can convert this to an AND of the
10954 if (const_op == 0 && equality_comparison_p
10955 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10956 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (op0, 1))
10959 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
10960 (HOST_WIDE_INT) 1);
10966 /* If this is an equality comparison with zero, we can do this
10967 as a logical shift, which might be much simpler. */
10968 if (equality_comparison_p && const_op == 0
10969 && GET_CODE (XEXP (op0, 1)) == CONST_INT)
10971 op0 = simplify_shift_const (NULL_RTX, LSHIFTRT, mode,
10973 INTVAL (XEXP (op0, 1)));
10977 /* If OP0 is a sign extension and CODE is not an unsigned comparison,
10978 do the comparison in a narrower mode. */
10979 if (! unsigned_comparison_p
10980 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10981 && GET_CODE (XEXP (op0, 0)) == ASHIFT
10982 && XEXP (op0, 1) == XEXP (XEXP (op0, 0), 1)
10983 && (tmode = mode_for_size (mode_width - INTVAL (XEXP (op0, 1)),
10984 MODE_INT, 1)) != BLKmode
10985 && (((unsigned HOST_WIDE_INT) const_op
10986 + (GET_MODE_MASK (tmode) >> 1) + 1)
10987 <= GET_MODE_MASK (tmode)))
10989 op0 = gen_lowpart (tmode, XEXP (XEXP (op0, 0), 0));
10993 /* Likewise if OP0 is a PLUS of a sign extension with a
10994 constant, which is usually represented with the PLUS
10995 between the shifts. */
10996 if (! unsigned_comparison_p
10997 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10998 && GET_CODE (XEXP (op0, 0)) == PLUS
10999 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
11000 && GET_CODE (XEXP (XEXP (op0, 0), 0)) == ASHIFT
11001 && XEXP (op0, 1) == XEXP (XEXP (XEXP (op0, 0), 0), 1)
11002 && (tmode = mode_for_size (mode_width - INTVAL (XEXP (op0, 1)),
11003 MODE_INT, 1)) != BLKmode
11004 && (((unsigned HOST_WIDE_INT) const_op
11005 + (GET_MODE_MASK (tmode) >> 1) + 1)
11006 <= GET_MODE_MASK (tmode)))
11008 rtx inner = XEXP (XEXP (XEXP (op0, 0), 0), 0);
11009 rtx add_const = XEXP (XEXP (op0, 0), 1);
11010 rtx new_const = simplify_gen_binary (ASHIFTRT, GET_MODE (op0),
11011 add_const, XEXP (op0, 1));
11013 op0 = simplify_gen_binary (PLUS, tmode,
11014 gen_lowpart (tmode, inner),
11019 /* ... fall through ... */
11021 /* If we have (compare (xshiftrt FOO N) (const_int C)) and
11022 the low order N bits of FOO are known to be zero, we can do this
11023 by comparing FOO with C shifted left N bits so long as no
11024 overflow occurs. */
11025 if (GET_CODE (XEXP (op0, 1)) == CONST_INT
11026 && INTVAL (XEXP (op0, 1)) >= 0
11027 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT
11028 && mode_width <= HOST_BITS_PER_WIDE_INT
11029 && (nonzero_bits (XEXP (op0, 0), mode)
11030 & (((HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1))) - 1)) == 0
11031 && (((unsigned HOST_WIDE_INT) const_op
11032 + (GET_CODE (op0) != LSHIFTRT
11033 ? ((GET_MODE_MASK (mode) >> INTVAL (XEXP (op0, 1)) >> 1)
11036 <= GET_MODE_MASK (mode) >> INTVAL (XEXP (op0, 1))))
11038 /* If the shift was logical, then we must make the condition
11040 if (GET_CODE (op0) == LSHIFTRT)
11041 code = unsigned_condition (code);
11043 const_op <<= INTVAL (XEXP (op0, 1));
11044 op1 = GEN_INT (const_op);
11045 op0 = XEXP (op0, 0);
11049 /* If we are using this shift to extract just the sign bit, we
11050 can replace this with an LT or GE comparison. */
11052 && (equality_comparison_p || sign_bit_comparison_p)
11053 && GET_CODE (XEXP (op0, 1)) == CONST_INT
11054 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (op0, 1))
11057 op0 = XEXP (op0, 0);
11058 code = (code == NE || code == GT ? LT : GE);
11070 /* Now make any compound operations involved in this comparison. Then,
11071 check for an outmost SUBREG on OP0 that is not doing anything or is
11072 paradoxical. The latter transformation must only be performed when
11073 it is known that the "extra" bits will be the same in op0 and op1 or
11074 that they don't matter. There are three cases to consider:
11076 1. SUBREG_REG (op0) is a register. In this case the bits are don't
11077 care bits and we can assume they have any convenient value. So
11078 making the transformation is safe.
11080 2. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is not defined.
11081 In this case the upper bits of op0 are undefined. We should not make
11082 the simplification in that case as we do not know the contents of
11085 3. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is defined and not
11086 UNKNOWN. In that case we know those bits are zeros or ones. We must
11087 also be sure that they are the same as the upper bits of op1.
11089 We can never remove a SUBREG for a non-equality comparison because
11090 the sign bit is in a different place in the underlying object. */
11092 op0 = make_compound_operation (op0, op1 == const0_rtx ? COMPARE : SET);
11093 op1 = make_compound_operation (op1, SET);
11095 if (GET_CODE (op0) == SUBREG && subreg_lowpart_p (op0)
11096 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
11097 && GET_MODE_CLASS (GET_MODE (SUBREG_REG (op0))) == MODE_INT
11098 && (code == NE || code == EQ))
11100 if (GET_MODE_SIZE (GET_MODE (op0))
11101 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (op0))))
11103 /* For paradoxical subregs, allow case 1 as above. Case 3 isn't
11105 if (REG_P (SUBREG_REG (op0)))
11107 op0 = SUBREG_REG (op0);
11108 op1 = gen_lowpart (GET_MODE (op0), op1);
11111 else if ((GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0)))
11112 <= HOST_BITS_PER_WIDE_INT)
11113 && (nonzero_bits (SUBREG_REG (op0),
11114 GET_MODE (SUBREG_REG (op0)))
11115 & ~GET_MODE_MASK (GET_MODE (op0))) == 0)
11117 tem = gen_lowpart (GET_MODE (SUBREG_REG (op0)), op1);
11119 if ((nonzero_bits (tem, GET_MODE (SUBREG_REG (op0)))
11120 & ~GET_MODE_MASK (GET_MODE (op0))) == 0)
11121 op0 = SUBREG_REG (op0), op1 = tem;
11125 /* We now do the opposite procedure: Some machines don't have compare
11126 insns in all modes. If OP0's mode is an integer mode smaller than a
11127 word and we can't do a compare in that mode, see if there is a larger
11128 mode for which we can do the compare. There are a number of cases in
11129 which we can use the wider mode. */
11131 mode = GET_MODE (op0);
11132 if (mode != VOIDmode && GET_MODE_CLASS (mode) == MODE_INT
11133 && GET_MODE_SIZE (mode) < UNITS_PER_WORD
11134 && ! have_insn_for (COMPARE, mode))
11135 for (tmode = GET_MODE_WIDER_MODE (mode);
11137 && GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT);
11138 tmode = GET_MODE_WIDER_MODE (tmode))
11139 if (have_insn_for (COMPARE, tmode))
11143 /* If the only nonzero bits in OP0 and OP1 are those in the
11144 narrower mode and this is an equality or unsigned comparison,
11145 we can use the wider mode. Similarly for sign-extended
11146 values, in which case it is true for all comparisons. */
11147 zero_extended = ((code == EQ || code == NE
11148 || code == GEU || code == GTU
11149 || code == LEU || code == LTU)
11150 && (nonzero_bits (op0, tmode)
11151 & ~GET_MODE_MASK (mode)) == 0
11152 && ((GET_CODE (op1) == CONST_INT
11153 || (nonzero_bits (op1, tmode)
11154 & ~GET_MODE_MASK (mode)) == 0)));
11157 || ((num_sign_bit_copies (op0, tmode)
11158 > (unsigned int) (GET_MODE_BITSIZE (tmode)
11159 - GET_MODE_BITSIZE (mode)))
11160 && (num_sign_bit_copies (op1, tmode)
11161 > (unsigned int) (GET_MODE_BITSIZE (tmode)
11162 - GET_MODE_BITSIZE (mode)))))
11164 /* If OP0 is an AND and we don't have an AND in MODE either,
11165 make a new AND in the proper mode. */
11166 if (GET_CODE (op0) == AND
11167 && !have_insn_for (AND, mode))
11168 op0 = simplify_gen_binary (AND, tmode,
11169 gen_lowpart (tmode,
11171 gen_lowpart (tmode,
11174 op0 = gen_lowpart (tmode, op0);
11175 if (zero_extended && GET_CODE (op1) == CONST_INT)
11176 op1 = GEN_INT (INTVAL (op1) & GET_MODE_MASK (mode));
11177 op1 = gen_lowpart (tmode, op1);
11181 /* If this is a test for negative, we can make an explicit
11182 test of the sign bit. */
11184 if (op1 == const0_rtx && (code == LT || code == GE)
11185 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
11187 op0 = simplify_gen_binary (AND, tmode,
11188 gen_lowpart (tmode, op0),
11189 GEN_INT ((HOST_WIDE_INT) 1
11190 << (GET_MODE_BITSIZE (mode)
11192 code = (code == LT) ? NE : EQ;
11197 #ifdef CANONICALIZE_COMPARISON
11198 /* If this machine only supports a subset of valid comparisons, see if we
11199 can convert an unsupported one into a supported one. */
11200 CANONICALIZE_COMPARISON (code, op0, op1);
11209 /* Utility function for record_value_for_reg. Count number of
11214 enum rtx_code code = GET_CODE (x);
11218 if (GET_RTX_CLASS (code) == '2'
11219 || GET_RTX_CLASS (code) == 'c')
11221 rtx x0 = XEXP (x, 0);
11222 rtx x1 = XEXP (x, 1);
11225 return 1 + 2 * count_rtxs (x0);
11227 if ((GET_RTX_CLASS (GET_CODE (x1)) == '2'
11228 || GET_RTX_CLASS (GET_CODE (x1)) == 'c')
11229 && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1)))
11230 return 2 + 2 * count_rtxs (x0)
11231 + count_rtxs (x == XEXP (x1, 0)
11232 ? XEXP (x1, 1) : XEXP (x1, 0));
11234 if ((GET_RTX_CLASS (GET_CODE (x0)) == '2'
11235 || GET_RTX_CLASS (GET_CODE (x0)) == 'c')
11236 && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1)))
11237 return 2 + 2 * count_rtxs (x1)
11238 + count_rtxs (x == XEXP (x0, 0)
11239 ? XEXP (x0, 1) : XEXP (x0, 0));
11242 fmt = GET_RTX_FORMAT (code);
11243 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
11245 ret += count_rtxs (XEXP (x, i));
11250 /* Utility function for following routine. Called when X is part of a value
11251 being stored into last_set_value. Sets last_set_table_tick
11252 for each register mentioned. Similar to mention_regs in cse.c */
11255 update_table_tick (rtx x)
11257 enum rtx_code code = GET_CODE (x);
11258 const char *fmt = GET_RTX_FORMAT (code);
11263 unsigned int regno = REGNO (x);
11264 unsigned int endregno = END_REGNO (x);
11267 for (r = regno; r < endregno; r++)
11269 reg_stat_type *rsp = VEC_index (reg_stat_type, reg_stat, r);
11270 rsp->last_set_table_tick = label_tick;
11276 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
11277 /* Note that we can't have an "E" in values stored; see
11278 get_last_value_validate. */
11281 /* Check for identical subexpressions. If x contains
11282 identical subexpression we only have to traverse one of
11284 if (i == 0 && ARITHMETIC_P (x))
11286 /* Note that at this point x1 has already been
11288 rtx x0 = XEXP (x, 0);
11289 rtx x1 = XEXP (x, 1);
11291 /* If x0 and x1 are identical then there is no need to
11296 /* If x0 is identical to a subexpression of x1 then while
11297 processing x1, x0 has already been processed. Thus we
11298 are done with x. */
11299 if (ARITHMETIC_P (x1)
11300 && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1)))
11303 /* If x1 is identical to a subexpression of x0 then we
11304 still have to process the rest of x0. */
11305 if (ARITHMETIC_P (x0)
11306 && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1)))
11308 update_table_tick (XEXP (x0, x1 == XEXP (x0, 0) ? 1 : 0));
11313 update_table_tick (XEXP (x, i));
11317 /* Record that REG is set to VALUE in insn INSN. If VALUE is zero, we
11318 are saying that the register is clobbered and we no longer know its
11319 value. If INSN is zero, don't update reg_stat[].last_set; this is
11320 only permitted with VALUE also zero and is used to invalidate the
11324 record_value_for_reg (rtx reg, rtx insn, rtx value)
11326 unsigned int regno = REGNO (reg);
11327 unsigned int endregno = END_REGNO (reg);
11329 reg_stat_type *rsp;
11331 /* If VALUE contains REG and we have a previous value for REG, substitute
11332 the previous value. */
11333 if (value && insn && reg_overlap_mentioned_p (reg, value))
11337 /* Set things up so get_last_value is allowed to see anything set up to
11339 subst_low_luid = DF_INSN_LUID (insn);
11340 tem = get_last_value (reg);
11342 /* If TEM is simply a binary operation with two CLOBBERs as operands,
11343 it isn't going to be useful and will take a lot of time to process,
11344 so just use the CLOBBER. */
11348 if (ARITHMETIC_P (tem)
11349 && GET_CODE (XEXP (tem, 0)) == CLOBBER
11350 && GET_CODE (XEXP (tem, 1)) == CLOBBER)
11351 tem = XEXP (tem, 0);
11352 else if (count_occurrences (value, reg, 1) >= 2)
11354 /* If there are two or more occurrences of REG in VALUE,
11355 prevent the value from growing too much. */
11356 if (count_rtxs (tem) > MAX_LAST_VALUE_RTL)
11357 tem = gen_rtx_CLOBBER (GET_MODE (tem), const0_rtx);
11360 value = replace_rtx (copy_rtx (value), reg, tem);
11364 /* For each register modified, show we don't know its value, that
11365 we don't know about its bitwise content, that its value has been
11366 updated, and that we don't know the location of the death of the
11368 for (i = regno; i < endregno; i++)
11370 rsp = VEC_index (reg_stat_type, reg_stat, i);
11373 rsp->last_set = insn;
11375 rsp->last_set_value = 0;
11376 rsp->last_set_mode = 0;
11377 rsp->last_set_nonzero_bits = 0;
11378 rsp->last_set_sign_bit_copies = 0;
11379 rsp->last_death = 0;
11380 rsp->truncated_to_mode = 0;
11383 /* Mark registers that are being referenced in this value. */
11385 update_table_tick (value);
11387 /* Now update the status of each register being set.
11388 If someone is using this register in this block, set this register
11389 to invalid since we will get confused between the two lives in this
11390 basic block. This makes using this register always invalid. In cse, we
11391 scan the table to invalidate all entries using this register, but this
11392 is too much work for us. */
11394 for (i = regno; i < endregno; i++)
11396 rsp = VEC_index (reg_stat_type, reg_stat, i);
11397 rsp->last_set_label = label_tick;
11399 || (value && rsp->last_set_table_tick >= label_tick_ebb_start))
11400 rsp->last_set_invalid = 1;
11402 rsp->last_set_invalid = 0;
11405 /* The value being assigned might refer to X (like in "x++;"). In that
11406 case, we must replace it with (clobber (const_int 0)) to prevent
11408 rsp = VEC_index (reg_stat_type, reg_stat, regno);
11409 if (value && ! get_last_value_validate (&value, insn,
11410 rsp->last_set_label, 0))
11412 value = copy_rtx (value);
11413 if (! get_last_value_validate (&value, insn,
11414 rsp->last_set_label, 1))
11418 /* For the main register being modified, update the value, the mode, the
11419 nonzero bits, and the number of sign bit copies. */
11421 rsp->last_set_value = value;
11425 enum machine_mode mode = GET_MODE (reg);
11426 subst_low_luid = DF_INSN_LUID (insn);
11427 rsp->last_set_mode = mode;
11428 if (GET_MODE_CLASS (mode) == MODE_INT
11429 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
11430 mode = nonzero_bits_mode;
11431 rsp->last_set_nonzero_bits = nonzero_bits (value, mode);
11432 rsp->last_set_sign_bit_copies
11433 = num_sign_bit_copies (value, GET_MODE (reg));
11437 /* Called via note_stores from record_dead_and_set_regs to handle one
11438 SET or CLOBBER in an insn. DATA is the instruction in which the
11439 set is occurring. */
11442 record_dead_and_set_regs_1 (rtx dest, const_rtx setter, void *data)
11444 rtx record_dead_insn = (rtx) data;
11446 if (GET_CODE (dest) == SUBREG)
11447 dest = SUBREG_REG (dest);
11449 if (!record_dead_insn)
11452 record_value_for_reg (dest, NULL_RTX, NULL_RTX);
11458 /* If we are setting the whole register, we know its value. Otherwise
11459 show that we don't know the value. We can handle SUBREG in
11461 if (GET_CODE (setter) == SET && dest == SET_DEST (setter))
11462 record_value_for_reg (dest, record_dead_insn, SET_SRC (setter));
11463 else if (GET_CODE (setter) == SET
11464 && GET_CODE (SET_DEST (setter)) == SUBREG
11465 && SUBREG_REG (SET_DEST (setter)) == dest
11466 && GET_MODE_BITSIZE (GET_MODE (dest)) <= BITS_PER_WORD
11467 && subreg_lowpart_p (SET_DEST (setter)))
11468 record_value_for_reg (dest, record_dead_insn,
11469 gen_lowpart (GET_MODE (dest),
11470 SET_SRC (setter)));
11472 record_value_for_reg (dest, record_dead_insn, NULL_RTX);
11474 else if (MEM_P (dest)
11475 /* Ignore pushes, they clobber nothing. */
11476 && ! push_operand (dest, GET_MODE (dest)))
11477 mem_last_set = DF_INSN_LUID (record_dead_insn);
11480 /* Update the records of when each REG was most recently set or killed
11481 for the things done by INSN. This is the last thing done in processing
11482 INSN in the combiner loop.
11484 We update reg_stat[], in particular fields last_set, last_set_value,
11485 last_set_mode, last_set_nonzero_bits, last_set_sign_bit_copies,
11486 last_death, and also the similar information mem_last_set (which insn
11487 most recently modified memory) and last_call_luid (which insn was the
11488 most recent subroutine call). */
11491 record_dead_and_set_regs (rtx insn)
11496 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
11498 if (REG_NOTE_KIND (link) == REG_DEAD
11499 && REG_P (XEXP (link, 0)))
11501 unsigned int regno = REGNO (XEXP (link, 0));
11502 unsigned int endregno = END_REGNO (XEXP (link, 0));
11504 for (i = regno; i < endregno; i++)
11506 reg_stat_type *rsp;
11508 rsp = VEC_index (reg_stat_type, reg_stat, i);
11509 rsp->last_death = insn;
11512 else if (REG_NOTE_KIND (link) == REG_INC)
11513 record_value_for_reg (XEXP (link, 0), insn, NULL_RTX);
11518 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
11519 if (TEST_HARD_REG_BIT (regs_invalidated_by_call, i))
11521 reg_stat_type *rsp;
11523 rsp = VEC_index (reg_stat_type, reg_stat, i);
11524 rsp->last_set_invalid = 1;
11525 rsp->last_set = insn;
11526 rsp->last_set_value = 0;
11527 rsp->last_set_mode = 0;
11528 rsp->last_set_nonzero_bits = 0;
11529 rsp->last_set_sign_bit_copies = 0;
11530 rsp->last_death = 0;
11531 rsp->truncated_to_mode = 0;
11534 last_call_luid = mem_last_set = DF_INSN_LUID (insn);
11536 /* We can't combine into a call pattern. Remember, though, that
11537 the return value register is set at this LUID. We could
11538 still replace a register with the return value from the
11539 wrong subroutine call! */
11540 note_stores (PATTERN (insn), record_dead_and_set_regs_1, NULL_RTX);
11543 note_stores (PATTERN (insn), record_dead_and_set_regs_1, insn);
11546 /* If a SUBREG has the promoted bit set, it is in fact a property of the
11547 register present in the SUBREG, so for each such SUBREG go back and
11548 adjust nonzero and sign bit information of the registers that are
11549 known to have some zero/sign bits set.
11551 This is needed because when combine blows the SUBREGs away, the
11552 information on zero/sign bits is lost and further combines can be
11553 missed because of that. */
11556 record_promoted_value (rtx insn, rtx subreg)
11559 unsigned int regno = REGNO (SUBREG_REG (subreg));
11560 enum machine_mode mode = GET_MODE (subreg);
11562 if (GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT)
11565 for (links = LOG_LINKS (insn); links;)
11567 reg_stat_type *rsp;
11569 insn = XEXP (links, 0);
11570 set = single_set (insn);
11572 if (! set || !REG_P (SET_DEST (set))
11573 || REGNO (SET_DEST (set)) != regno
11574 || GET_MODE (SET_DEST (set)) != GET_MODE (SUBREG_REG (subreg)))
11576 links = XEXP (links, 1);
11580 rsp = VEC_index (reg_stat_type, reg_stat, regno);
11581 if (rsp->last_set == insn)
11583 if (SUBREG_PROMOTED_UNSIGNED_P (subreg) > 0)
11584 rsp->last_set_nonzero_bits &= GET_MODE_MASK (mode);
11587 if (REG_P (SET_SRC (set)))
11589 regno = REGNO (SET_SRC (set));
11590 links = LOG_LINKS (insn);
11597 /* Check if X, a register, is known to contain a value already
11598 truncated to MODE. In this case we can use a subreg to refer to
11599 the truncated value even though in the generic case we would need
11600 an explicit truncation. */
11603 reg_truncated_to_mode (enum machine_mode mode, const_rtx x)
11605 reg_stat_type *rsp = VEC_index (reg_stat_type, reg_stat, REGNO (x));
11606 enum machine_mode truncated = rsp->truncated_to_mode;
11609 || rsp->truncation_label < label_tick_ebb_start)
11611 if (GET_MODE_SIZE (truncated) <= GET_MODE_SIZE (mode))
11613 if (TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode),
11614 GET_MODE_BITSIZE (truncated)))
11619 /* Callback for for_each_rtx. If *P is a hard reg or a subreg record the mode
11620 that the register is accessed in. For non-TRULY_NOOP_TRUNCATION targets we
11621 might be able to turn a truncate into a subreg using this information.
11622 Return -1 if traversing *P is complete or 0 otherwise. */
11625 record_truncated_value (rtx *p, void *data ATTRIBUTE_UNUSED)
11628 enum machine_mode truncated_mode;
11629 reg_stat_type *rsp;
11631 if (GET_CODE (x) == SUBREG && REG_P (SUBREG_REG (x)))
11633 enum machine_mode original_mode = GET_MODE (SUBREG_REG (x));
11634 truncated_mode = GET_MODE (x);
11636 if (GET_MODE_SIZE (original_mode) <= GET_MODE_SIZE (truncated_mode))
11639 if (TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (truncated_mode),
11640 GET_MODE_BITSIZE (original_mode)))
11643 x = SUBREG_REG (x);
11645 /* ??? For hard-regs we now record everything. We might be able to
11646 optimize this using last_set_mode. */
11647 else if (REG_P (x) && REGNO (x) < FIRST_PSEUDO_REGISTER)
11648 truncated_mode = GET_MODE (x);
11652 rsp = VEC_index (reg_stat_type, reg_stat, REGNO (x));
11653 if (rsp->truncated_to_mode == 0
11654 || rsp->truncation_label < label_tick_ebb_start
11655 || (GET_MODE_SIZE (truncated_mode)
11656 < GET_MODE_SIZE (rsp->truncated_to_mode)))
11658 rsp->truncated_to_mode = truncated_mode;
11659 rsp->truncation_label = label_tick;
11665 /* Callback for note_uses. Find hardregs and subregs of pseudos and
11666 the modes they are used in. This can help truning TRUNCATEs into
11670 record_truncated_values (rtx *x, void *data ATTRIBUTE_UNUSED)
11672 for_each_rtx (x, record_truncated_value, NULL);
11675 /* Scan X for promoted SUBREGs. For each one found,
11676 note what it implies to the registers used in it. */
11679 check_promoted_subreg (rtx insn, rtx x)
11681 if (GET_CODE (x) == SUBREG
11682 && SUBREG_PROMOTED_VAR_P (x)
11683 && REG_P (SUBREG_REG (x)))
11684 record_promoted_value (insn, x);
11687 const char *format = GET_RTX_FORMAT (GET_CODE (x));
11690 for (i = 0; i < GET_RTX_LENGTH (GET_CODE (x)); i++)
11694 check_promoted_subreg (insn, XEXP (x, i));
11698 if (XVEC (x, i) != 0)
11699 for (j = 0; j < XVECLEN (x, i); j++)
11700 check_promoted_subreg (insn, XVECEXP (x, i, j));
11706 /* Utility routine for the following function. Verify that all the registers
11707 mentioned in *LOC are valid when *LOC was part of a value set when
11708 label_tick == TICK. Return 0 if some are not.
11710 If REPLACE is nonzero, replace the invalid reference with
11711 (clobber (const_int 0)) and return 1. This replacement is useful because
11712 we often can get useful information about the form of a value (e.g., if
11713 it was produced by a shift that always produces -1 or 0) even though
11714 we don't know exactly what registers it was produced from. */
11717 get_last_value_validate (rtx *loc, rtx insn, int tick, int replace)
11720 const char *fmt = GET_RTX_FORMAT (GET_CODE (x));
11721 int len = GET_RTX_LENGTH (GET_CODE (x));
11726 unsigned int regno = REGNO (x);
11727 unsigned int endregno = END_REGNO (x);
11730 for (j = regno; j < endregno; j++)
11732 reg_stat_type *rsp = VEC_index (reg_stat_type, reg_stat, j);
11733 if (rsp->last_set_invalid
11734 /* If this is a pseudo-register that was only set once and not
11735 live at the beginning of the function, it is always valid. */
11736 || (! (regno >= FIRST_PSEUDO_REGISTER
11737 && REG_N_SETS (regno) == 1
11738 && (!REGNO_REG_SET_P
11739 (DF_LR_IN (ENTRY_BLOCK_PTR->next_bb), regno)))
11740 && rsp->last_set_label > tick))
11743 *loc = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
11750 /* If this is a memory reference, make sure that there were
11751 no stores after it that might have clobbered the value. We don't
11752 have alias info, so we assume any store invalidates it. */
11753 else if (MEM_P (x) && !MEM_READONLY_P (x)
11754 && DF_INSN_LUID (insn) <= mem_last_set)
11757 *loc = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
11761 for (i = 0; i < len; i++)
11765 /* Check for identical subexpressions. If x contains
11766 identical subexpression we only have to traverse one of
11768 if (i == 1 && ARITHMETIC_P (x))
11770 /* Note that at this point x0 has already been checked
11771 and found valid. */
11772 rtx x0 = XEXP (x, 0);
11773 rtx x1 = XEXP (x, 1);
11775 /* If x0 and x1 are identical then x is also valid. */
11779 /* If x1 is identical to a subexpression of x0 then
11780 while checking x0, x1 has already been checked. Thus
11781 it is valid and so as x. */
11782 if (ARITHMETIC_P (x0)
11783 && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1)))
11786 /* If x0 is identical to a subexpression of x1 then x is
11787 valid iff the rest of x1 is valid. */
11788 if (ARITHMETIC_P (x1)
11789 && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1)))
11791 get_last_value_validate (&XEXP (x1,
11792 x0 == XEXP (x1, 0) ? 1 : 0),
11793 insn, tick, replace);
11796 if (get_last_value_validate (&XEXP (x, i), insn, tick,
11800 /* Don't bother with these. They shouldn't occur anyway. */
11801 else if (fmt[i] == 'E')
11805 /* If we haven't found a reason for it to be invalid, it is valid. */
11809 /* Get the last value assigned to X, if known. Some registers
11810 in the value may be replaced with (clobber (const_int 0)) if their value
11811 is known longer known reliably. */
11814 get_last_value (const_rtx x)
11816 unsigned int regno;
11818 reg_stat_type *rsp;
11820 /* If this is a non-paradoxical SUBREG, get the value of its operand and
11821 then convert it to the desired mode. If this is a paradoxical SUBREG,
11822 we cannot predict what values the "extra" bits might have. */
11823 if (GET_CODE (x) == SUBREG
11824 && subreg_lowpart_p (x)
11825 && (GET_MODE_SIZE (GET_MODE (x))
11826 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
11827 && (value = get_last_value (SUBREG_REG (x))) != 0)
11828 return gen_lowpart (GET_MODE (x), value);
11834 rsp = VEC_index (reg_stat_type, reg_stat, regno);
11835 value = rsp->last_set_value;
11837 /* If we don't have a value, or if it isn't for this basic block and
11838 it's either a hard register, set more than once, or it's a live
11839 at the beginning of the function, return 0.
11841 Because if it's not live at the beginning of the function then the reg
11842 is always set before being used (is never used without being set).
11843 And, if it's set only once, and it's always set before use, then all
11844 uses must have the same last value, even if it's not from this basic
11848 || (rsp->last_set_label < label_tick_ebb_start
11849 && (regno < FIRST_PSEUDO_REGISTER
11850 || REG_N_SETS (regno) != 1
11852 (DF_LR_IN (ENTRY_BLOCK_PTR->next_bb), regno))))
11855 /* If the value was set in a later insn than the ones we are processing,
11856 we can't use it even if the register was only set once. */
11857 if (rsp->last_set_label == label_tick
11858 && DF_INSN_LUID (rsp->last_set) >= subst_low_luid)
11861 /* If the value has all its registers valid, return it. */
11862 if (get_last_value_validate (&value, rsp->last_set,
11863 rsp->last_set_label, 0))
11866 /* Otherwise, make a copy and replace any invalid register with
11867 (clobber (const_int 0)). If that fails for some reason, return 0. */
11869 value = copy_rtx (value);
11870 if (get_last_value_validate (&value, rsp->last_set,
11871 rsp->last_set_label, 1))
11877 /* Return nonzero if expression X refers to a REG or to memory
11878 that is set in an instruction more recent than FROM_LUID. */
11881 use_crosses_set_p (const_rtx x, int from_luid)
11885 enum rtx_code code = GET_CODE (x);
11889 unsigned int regno = REGNO (x);
11890 unsigned endreg = END_REGNO (x);
11892 #ifdef PUSH_ROUNDING
11893 /* Don't allow uses of the stack pointer to be moved,
11894 because we don't know whether the move crosses a push insn. */
11895 if (regno == STACK_POINTER_REGNUM && PUSH_ARGS)
11898 for (; regno < endreg; regno++)
11900 reg_stat_type *rsp = VEC_index (reg_stat_type, reg_stat, regno);
11902 && rsp->last_set_label == label_tick
11903 && DF_INSN_LUID (rsp->last_set) > from_luid)
11909 if (code == MEM && mem_last_set > from_luid)
11912 fmt = GET_RTX_FORMAT (code);
11914 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
11919 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
11920 if (use_crosses_set_p (XVECEXP (x, i, j), from_luid))
11923 else if (fmt[i] == 'e'
11924 && use_crosses_set_p (XEXP (x, i), from_luid))
11930 /* Define three variables used for communication between the following
11933 static unsigned int reg_dead_regno, reg_dead_endregno;
11934 static int reg_dead_flag;
11936 /* Function called via note_stores from reg_dead_at_p.
11938 If DEST is within [reg_dead_regno, reg_dead_endregno), set
11939 reg_dead_flag to 1 if X is a CLOBBER and to -1 it is a SET. */
11942 reg_dead_at_p_1 (rtx dest, const_rtx x, void *data ATTRIBUTE_UNUSED)
11944 unsigned int regno, endregno;
11949 regno = REGNO (dest);
11950 endregno = END_REGNO (dest);
11951 if (reg_dead_endregno > regno && reg_dead_regno < endregno)
11952 reg_dead_flag = (GET_CODE (x) == CLOBBER) ? 1 : -1;
11955 /* Return nonzero if REG is known to be dead at INSN.
11957 We scan backwards from INSN. If we hit a REG_DEAD note or a CLOBBER
11958 referencing REG, it is dead. If we hit a SET referencing REG, it is
11959 live. Otherwise, see if it is live or dead at the start of the basic
11960 block we are in. Hard regs marked as being live in NEWPAT_USED_REGS
11961 must be assumed to be always live. */
11964 reg_dead_at_p (rtx reg, rtx insn)
11969 /* Set variables for reg_dead_at_p_1. */
11970 reg_dead_regno = REGNO (reg);
11971 reg_dead_endregno = END_REGNO (reg);
11975 /* Check that reg isn't mentioned in NEWPAT_USED_REGS. For fixed registers
11976 we allow the machine description to decide whether use-and-clobber
11977 patterns are OK. */
11978 if (reg_dead_regno < FIRST_PSEUDO_REGISTER)
11980 for (i = reg_dead_regno; i < reg_dead_endregno; i++)
11981 if (!fixed_regs[i] && TEST_HARD_REG_BIT (newpat_used_regs, i))
11985 /* Scan backwards until we find a REG_DEAD note, SET, CLOBBER, label, or
11986 beginning of function. */
11987 for (; insn && !LABEL_P (insn) && !BARRIER_P (insn);
11988 insn = prev_nonnote_insn (insn))
11990 note_stores (PATTERN (insn), reg_dead_at_p_1, NULL);
11992 return reg_dead_flag == 1 ? 1 : 0;
11994 if (find_regno_note (insn, REG_DEAD, reg_dead_regno))
11998 /* Get the basic block that we were in. */
12000 block = ENTRY_BLOCK_PTR->next_bb;
12003 FOR_EACH_BB (block)
12004 if (insn == BB_HEAD (block))
12007 if (block == EXIT_BLOCK_PTR)
12011 for (i = reg_dead_regno; i < reg_dead_endregno; i++)
12012 if (REGNO_REG_SET_P (df_get_live_in (block), i))
12018 /* Note hard registers in X that are used. */
12021 mark_used_regs_combine (rtx x)
12023 RTX_CODE code = GET_CODE (x);
12024 unsigned int regno;
12037 case ADDR_DIFF_VEC:
12040 /* CC0 must die in the insn after it is set, so we don't need to take
12041 special note of it here. */
12047 /* If we are clobbering a MEM, mark any hard registers inside the
12048 address as used. */
12049 if (MEM_P (XEXP (x, 0)))
12050 mark_used_regs_combine (XEXP (XEXP (x, 0), 0));
12055 /* A hard reg in a wide mode may really be multiple registers.
12056 If so, mark all of them just like the first. */
12057 if (regno < FIRST_PSEUDO_REGISTER)
12059 /* None of this applies to the stack, frame or arg pointers. */
12060 if (regno == STACK_POINTER_REGNUM
12061 #if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM
12062 || regno == HARD_FRAME_POINTER_REGNUM
12064 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
12065 || (regno == ARG_POINTER_REGNUM && fixed_regs[regno])
12067 || regno == FRAME_POINTER_REGNUM)
12070 add_to_hard_reg_set (&newpat_used_regs, GET_MODE (x), regno);
12076 /* If setting a MEM, or a SUBREG of a MEM, then note any hard regs in
12078 rtx testreg = SET_DEST (x);
12080 while (GET_CODE (testreg) == SUBREG
12081 || GET_CODE (testreg) == ZERO_EXTRACT
12082 || GET_CODE (testreg) == STRICT_LOW_PART)
12083 testreg = XEXP (testreg, 0);
12085 if (MEM_P (testreg))
12086 mark_used_regs_combine (XEXP (testreg, 0));
12088 mark_used_regs_combine (SET_SRC (x));
12096 /* Recursively scan the operands of this expression. */
12099 const char *fmt = GET_RTX_FORMAT (code);
12101 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
12104 mark_used_regs_combine (XEXP (x, i));
12105 else if (fmt[i] == 'E')
12109 for (j = 0; j < XVECLEN (x, i); j++)
12110 mark_used_regs_combine (XVECEXP (x, i, j));
12116 /* Remove register number REGNO from the dead registers list of INSN.
12118 Return the note used to record the death, if there was one. */
12121 remove_death (unsigned int regno, rtx insn)
12123 rtx note = find_regno_note (insn, REG_DEAD, regno);
12126 remove_note (insn, note);
12131 /* For each register (hardware or pseudo) used within expression X, if its
12132 death is in an instruction with luid between FROM_LUID (inclusive) and
12133 TO_INSN (exclusive), put a REG_DEAD note for that register in the
12134 list headed by PNOTES.
12136 That said, don't move registers killed by maybe_kill_insn.
12138 This is done when X is being merged by combination into TO_INSN. These
12139 notes will then be distributed as needed. */
12142 move_deaths (rtx x, rtx maybe_kill_insn, int from_luid, rtx to_insn,
12147 enum rtx_code code = GET_CODE (x);
12151 unsigned int regno = REGNO (x);
12152 rtx where_dead = VEC_index (reg_stat_type, reg_stat, regno)->last_death;
12154 /* Don't move the register if it gets killed in between from and to. */
12155 if (maybe_kill_insn && reg_set_p (x, maybe_kill_insn)
12156 && ! reg_referenced_p (x, maybe_kill_insn))
12160 && DF_INSN_LUID (where_dead) >= from_luid
12161 && DF_INSN_LUID (where_dead) < DF_INSN_LUID (to_insn))
12163 rtx note = remove_death (regno, where_dead);
12165 /* It is possible for the call above to return 0. This can occur
12166 when last_death points to I2 or I1 that we combined with.
12167 In that case make a new note.
12169 We must also check for the case where X is a hard register
12170 and NOTE is a death note for a range of hard registers
12171 including X. In that case, we must put REG_DEAD notes for
12172 the remaining registers in place of NOTE. */
12174 if (note != 0 && regno < FIRST_PSEUDO_REGISTER
12175 && (GET_MODE_SIZE (GET_MODE (XEXP (note, 0)))
12176 > GET_MODE_SIZE (GET_MODE (x))))
12178 unsigned int deadregno = REGNO (XEXP (note, 0));
12179 unsigned int deadend = END_HARD_REGNO (XEXP (note, 0));
12180 unsigned int ourend = END_HARD_REGNO (x);
12183 for (i = deadregno; i < deadend; i++)
12184 if (i < regno || i >= ourend)
12185 REG_NOTES (where_dead)
12186 = gen_rtx_EXPR_LIST (REG_DEAD,
12188 REG_NOTES (where_dead));
12191 /* If we didn't find any note, or if we found a REG_DEAD note that
12192 covers only part of the given reg, and we have a multi-reg hard
12193 register, then to be safe we must check for REG_DEAD notes
12194 for each register other than the first. They could have
12195 their own REG_DEAD notes lying around. */
12196 else if ((note == 0
12198 && (GET_MODE_SIZE (GET_MODE (XEXP (note, 0)))
12199 < GET_MODE_SIZE (GET_MODE (x)))))
12200 && regno < FIRST_PSEUDO_REGISTER
12201 && hard_regno_nregs[regno][GET_MODE (x)] > 1)
12203 unsigned int ourend = END_HARD_REGNO (x);
12204 unsigned int i, offset;
12208 offset = hard_regno_nregs[regno][GET_MODE (XEXP (note, 0))];
12212 for (i = regno + offset; i < ourend; i++)
12213 move_deaths (regno_reg_rtx[i],
12214 maybe_kill_insn, from_luid, to_insn, &oldnotes);
12217 if (note != 0 && GET_MODE (XEXP (note, 0)) == GET_MODE (x))
12219 XEXP (note, 1) = *pnotes;
12223 *pnotes = gen_rtx_EXPR_LIST (REG_DEAD, x, *pnotes);
12229 else if (GET_CODE (x) == SET)
12231 rtx dest = SET_DEST (x);
12233 move_deaths (SET_SRC (x), maybe_kill_insn, from_luid, to_insn, pnotes);
12235 /* In the case of a ZERO_EXTRACT, a STRICT_LOW_PART, or a SUBREG
12236 that accesses one word of a multi-word item, some
12237 piece of everything register in the expression is used by
12238 this insn, so remove any old death. */
12239 /* ??? So why do we test for equality of the sizes? */
12241 if (GET_CODE (dest) == ZERO_EXTRACT
12242 || GET_CODE (dest) == STRICT_LOW_PART
12243 || (GET_CODE (dest) == SUBREG
12244 && (((GET_MODE_SIZE (GET_MODE (dest))
12245 + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
12246 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (dest)))
12247 + UNITS_PER_WORD - 1) / UNITS_PER_WORD))))
12249 move_deaths (dest, maybe_kill_insn, from_luid, to_insn, pnotes);
12253 /* If this is some other SUBREG, we know it replaces the entire
12254 value, so use that as the destination. */
12255 if (GET_CODE (dest) == SUBREG)
12256 dest = SUBREG_REG (dest);
12258 /* If this is a MEM, adjust deaths of anything used in the address.
12259 For a REG (the only other possibility), the entire value is
12260 being replaced so the old value is not used in this insn. */
12263 move_deaths (XEXP (dest, 0), maybe_kill_insn, from_luid,
12268 else if (GET_CODE (x) == CLOBBER)
12271 len = GET_RTX_LENGTH (code);
12272 fmt = GET_RTX_FORMAT (code);
12274 for (i = 0; i < len; i++)
12279 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
12280 move_deaths (XVECEXP (x, i, j), maybe_kill_insn, from_luid,
12283 else if (fmt[i] == 'e')
12284 move_deaths (XEXP (x, i), maybe_kill_insn, from_luid, to_insn, pnotes);
12288 /* Return 1 if X is the target of a bit-field assignment in BODY, the
12289 pattern of an insn. X must be a REG. */
12292 reg_bitfield_target_p (rtx x, rtx body)
12296 if (GET_CODE (body) == SET)
12298 rtx dest = SET_DEST (body);
12300 unsigned int regno, tregno, endregno, endtregno;
12302 if (GET_CODE (dest) == ZERO_EXTRACT)
12303 target = XEXP (dest, 0);
12304 else if (GET_CODE (dest) == STRICT_LOW_PART)
12305 target = SUBREG_REG (XEXP (dest, 0));
12309 if (GET_CODE (target) == SUBREG)
12310 target = SUBREG_REG (target);
12312 if (!REG_P (target))
12315 tregno = REGNO (target), regno = REGNO (x);
12316 if (tregno >= FIRST_PSEUDO_REGISTER || regno >= FIRST_PSEUDO_REGISTER)
12317 return target == x;
12319 endtregno = end_hard_regno (GET_MODE (target), tregno);
12320 endregno = end_hard_regno (GET_MODE (x), regno);
12322 return endregno > tregno && regno < endtregno;
12325 else if (GET_CODE (body) == PARALLEL)
12326 for (i = XVECLEN (body, 0) - 1; i >= 0; i--)
12327 if (reg_bitfield_target_p (x, XVECEXP (body, 0, i)))
12333 /* Given a chain of REG_NOTES originally from FROM_INSN, try to place them
12334 as appropriate. I3 and I2 are the insns resulting from the combination
12335 insns including FROM (I2 may be zero).
12337 ELIM_I2 and ELIM_I1 are either zero or registers that we know will
12338 not need REG_DEAD notes because they are being substituted for. This
12339 saves searching in the most common cases.
12341 Each note in the list is either ignored or placed on some insns, depending
12342 on the type of note. */
12345 distribute_notes (rtx notes, rtx from_insn, rtx i3, rtx i2, rtx elim_i2,
12348 rtx note, next_note;
12351 for (note = notes; note; note = next_note)
12353 rtx place = 0, place2 = 0;
12355 next_note = XEXP (note, 1);
12356 switch (REG_NOTE_KIND (note))
12360 /* Doesn't matter much where we put this, as long as it's somewhere.
12361 It is preferable to keep these notes on branches, which is most
12362 likely to be i3. */
12366 case REG_VALUE_PROFILE:
12367 /* Just get rid of this note, as it is unused later anyway. */
12370 case REG_NON_LOCAL_GOTO:
12375 gcc_assert (i2 && JUMP_P (i2));
12380 case REG_EH_REGION:
12381 /* These notes must remain with the call or trapping instruction. */
12384 else if (i2 && CALL_P (i2))
12388 gcc_assert (flag_non_call_exceptions);
12389 if (may_trap_p (i3))
12391 else if (i2 && may_trap_p (i2))
12393 /* ??? Otherwise assume we've combined things such that we
12394 can now prove that the instructions can't trap. Drop the
12395 note in this case. */
12401 /* These notes must remain with the call. It should not be
12402 possible for both I2 and I3 to be a call. */
12407 gcc_assert (i2 && CALL_P (i2));
12413 /* Any clobbers for i3 may still exist, and so we must process
12414 REG_UNUSED notes from that insn.
12416 Any clobbers from i2 or i1 can only exist if they were added by
12417 recog_for_combine. In that case, recog_for_combine created the
12418 necessary REG_UNUSED notes. Trying to keep any original
12419 REG_UNUSED notes from these insns can cause incorrect output
12420 if it is for the same register as the original i3 dest.
12421 In that case, we will notice that the register is set in i3,
12422 and then add a REG_UNUSED note for the destination of i3, which
12423 is wrong. However, it is possible to have REG_UNUSED notes from
12424 i2 or i1 for register which were both used and clobbered, so
12425 we keep notes from i2 or i1 if they will turn into REG_DEAD
12428 /* If this register is set or clobbered in I3, put the note there
12429 unless there is one already. */
12430 if (reg_set_p (XEXP (note, 0), PATTERN (i3)))
12432 if (from_insn != i3)
12435 if (! (REG_P (XEXP (note, 0))
12436 ? find_regno_note (i3, REG_UNUSED, REGNO (XEXP (note, 0)))
12437 : find_reg_note (i3, REG_UNUSED, XEXP (note, 0))))
12440 /* Otherwise, if this register is used by I3, then this register
12441 now dies here, so we must put a REG_DEAD note here unless there
12443 else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3))
12444 && ! (REG_P (XEXP (note, 0))
12445 ? find_regno_note (i3, REG_DEAD,
12446 REGNO (XEXP (note, 0)))
12447 : find_reg_note (i3, REG_DEAD, XEXP (note, 0))))
12449 PUT_REG_NOTE_KIND (note, REG_DEAD);
12457 /* These notes say something about results of an insn. We can
12458 only support them if they used to be on I3 in which case they
12459 remain on I3. Otherwise they are ignored.
12461 If the note refers to an expression that is not a constant, we
12462 must also ignore the note since we cannot tell whether the
12463 equivalence is still true. It might be possible to do
12464 slightly better than this (we only have a problem if I2DEST
12465 or I1DEST is present in the expression), but it doesn't
12466 seem worth the trouble. */
12468 if (from_insn == i3
12469 && (XEXP (note, 0) == 0 || CONSTANT_P (XEXP (note, 0))))
12474 /* These notes say something about how a register is used. They must
12475 be present on any use of the register in I2 or I3. */
12476 if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3)))
12479 if (i2 && reg_mentioned_p (XEXP (note, 0), PATTERN (i2)))
12488 case REG_LABEL_TARGET:
12489 case REG_LABEL_OPERAND:
12490 /* This can show up in several ways -- either directly in the
12491 pattern, or hidden off in the constant pool with (or without?)
12492 a REG_EQUAL note. */
12493 /* ??? Ignore the without-reg_equal-note problem for now. */
12494 if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3))
12495 || ((tem = find_reg_note (i3, REG_EQUAL, NULL_RTX))
12496 && GET_CODE (XEXP (tem, 0)) == LABEL_REF
12497 && XEXP (XEXP (tem, 0), 0) == XEXP (note, 0)))
12501 && (reg_mentioned_p (XEXP (note, 0), PATTERN (i2))
12502 || ((tem = find_reg_note (i2, REG_EQUAL, NULL_RTX))
12503 && GET_CODE (XEXP (tem, 0)) == LABEL_REF
12504 && XEXP (XEXP (tem, 0), 0) == XEXP (note, 0))))
12512 /* For REG_LABEL_TARGET on a JUMP_P, we prefer to put the note
12513 as a JUMP_LABEL or decrement LABEL_NUSES if it's already
12515 if (place && JUMP_P (place)
12516 && REG_NOTE_KIND (note) == REG_LABEL_TARGET
12517 && (JUMP_LABEL (place) == NULL
12518 || JUMP_LABEL (place) == XEXP (note, 0)))
12520 rtx label = JUMP_LABEL (place);
12523 JUMP_LABEL (place) = XEXP (note, 0);
12524 else if (LABEL_P (label))
12525 LABEL_NUSES (label)--;
12528 if (place2 && JUMP_P (place2)
12529 && REG_NOTE_KIND (note) == REG_LABEL_TARGET
12530 && (JUMP_LABEL (place2) == NULL
12531 || JUMP_LABEL (place2) == XEXP (note, 0)))
12533 rtx label = JUMP_LABEL (place2);
12536 JUMP_LABEL (place2) = XEXP (note, 0);
12537 else if (LABEL_P (label))
12538 LABEL_NUSES (label)--;
12544 /* This note says something about the value of a register prior
12545 to the execution of an insn. It is too much trouble to see
12546 if the note is still correct in all situations. It is better
12547 to simply delete it. */
12551 /* If the insn previously containing this note still exists,
12552 put it back where it was. Otherwise move it to the previous
12553 insn. Adjust the corresponding REG_LIBCALL note. */
12554 if (!NOTE_P (from_insn))
12558 tem = find_reg_note (XEXP (note, 0), REG_LIBCALL, NULL_RTX);
12559 place = prev_real_insn (from_insn);
12561 XEXP (tem, 0) = place;
12562 /* If we're deleting the last remaining instruction of a
12563 libcall sequence, don't add the notes. */
12564 else if (XEXP (note, 0) == from_insn)
12566 /* Don't add the dangling REG_RETVAL note. */
12573 /* This is handled similarly to REG_RETVAL. */
12574 if (!NOTE_P (from_insn))
12578 tem = find_reg_note (XEXP (note, 0), REG_RETVAL, NULL_RTX);
12579 place = next_real_insn (from_insn);
12581 XEXP (tem, 0) = place;
12582 /* If we're deleting the last remaining instruction of a
12583 libcall sequence, don't add the notes. */
12584 else if (XEXP (note, 0) == from_insn)
12586 /* Don't add the dangling REG_LIBCALL note. */
12593 /* If we replaced the right hand side of FROM_INSN with a
12594 REG_EQUAL note, the original use of the dying register
12595 will not have been combined into I3 and I2. In such cases,
12596 FROM_INSN is guaranteed to be the first of the combined
12597 instructions, so we simply need to search back before
12598 FROM_INSN for the previous use or set of this register,
12599 then alter the notes there appropriately.
12601 If the register is used as an input in I3, it dies there.
12602 Similarly for I2, if it is nonzero and adjacent to I3.
12604 If the register is not used as an input in either I3 or I2
12605 and it is not one of the registers we were supposed to eliminate,
12606 there are two possibilities. We might have a non-adjacent I2
12607 or we might have somehow eliminated an additional register
12608 from a computation. For example, we might have had A & B where
12609 we discover that B will always be zero. In this case we will
12610 eliminate the reference to A.
12612 In both cases, we must search to see if we can find a previous
12613 use of A and put the death note there. */
12616 && from_insn == i2mod
12617 && !reg_overlap_mentioned_p (XEXP (note, 0), i2mod_new_rhs))
12622 && CALL_P (from_insn)
12623 && find_reg_fusage (from_insn, USE, XEXP (note, 0)))
12625 else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3)))
12627 else if (i2 != 0 && next_nonnote_insn (i2) == i3
12628 && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
12630 else if ((rtx_equal_p (XEXP (note, 0), elim_i2)
12632 && reg_overlap_mentioned_p (XEXP (note, 0),
12634 || rtx_equal_p (XEXP (note, 0), elim_i1))
12641 basic_block bb = this_basic_block;
12643 for (tem = PREV_INSN (tem); place == 0; tem = PREV_INSN (tem))
12645 if (! INSN_P (tem))
12647 if (tem == BB_HEAD (bb))
12652 /* If the register is being set at TEM, see if that is all
12653 TEM is doing. If so, delete TEM. Otherwise, make this
12654 into a REG_UNUSED note instead. Don't delete sets to
12655 global register vars. */
12656 if ((REGNO (XEXP (note, 0)) >= FIRST_PSEUDO_REGISTER
12657 || !global_regs[REGNO (XEXP (note, 0))])
12658 && reg_set_p (XEXP (note, 0), PATTERN (tem)))
12660 rtx set = single_set (tem);
12661 rtx inner_dest = 0;
12663 rtx cc0_setter = NULL_RTX;
12667 for (inner_dest = SET_DEST (set);
12668 (GET_CODE (inner_dest) == STRICT_LOW_PART
12669 || GET_CODE (inner_dest) == SUBREG
12670 || GET_CODE (inner_dest) == ZERO_EXTRACT);
12671 inner_dest = XEXP (inner_dest, 0))
12674 /* Verify that it was the set, and not a clobber that
12675 modified the register.
12677 CC0 targets must be careful to maintain setter/user
12678 pairs. If we cannot delete the setter due to side
12679 effects, mark the user with an UNUSED note instead
12682 if (set != 0 && ! side_effects_p (SET_SRC (set))
12683 && rtx_equal_p (XEXP (note, 0), inner_dest)
12685 && (! reg_mentioned_p (cc0_rtx, SET_SRC (set))
12686 || ((cc0_setter = prev_cc0_setter (tem)) != NULL
12687 && sets_cc0_p (PATTERN (cc0_setter)) > 0))
12691 /* Move the notes and links of TEM elsewhere.
12692 This might delete other dead insns recursively.
12693 First set the pattern to something that won't use
12695 rtx old_notes = REG_NOTES (tem);
12697 PATTERN (tem) = pc_rtx;
12698 REG_NOTES (tem) = NULL;
12700 distribute_notes (old_notes, tem, tem, NULL_RTX,
12701 NULL_RTX, NULL_RTX);
12702 distribute_links (LOG_LINKS (tem));
12704 SET_INSN_DELETED (tem);
12707 /* Delete the setter too. */
12710 PATTERN (cc0_setter) = pc_rtx;
12711 old_notes = REG_NOTES (cc0_setter);
12712 REG_NOTES (cc0_setter) = NULL;
12714 distribute_notes (old_notes, cc0_setter,
12715 cc0_setter, NULL_RTX,
12716 NULL_RTX, NULL_RTX);
12717 distribute_links (LOG_LINKS (cc0_setter));
12719 SET_INSN_DELETED (cc0_setter);
12725 PUT_REG_NOTE_KIND (note, REG_UNUSED);
12727 /* If there isn't already a REG_UNUSED note, put one
12728 here. Do not place a REG_DEAD note, even if
12729 the register is also used here; that would not
12730 match the algorithm used in lifetime analysis
12731 and can cause the consistency check in the
12732 scheduler to fail. */
12733 if (! find_regno_note (tem, REG_UNUSED,
12734 REGNO (XEXP (note, 0))))
12739 else if (reg_referenced_p (XEXP (note, 0), PATTERN (tem))
12741 && find_reg_fusage (tem, USE, XEXP (note, 0))))
12745 /* If we are doing a 3->2 combination, and we have a
12746 register which formerly died in i3 and was not used
12747 by i2, which now no longer dies in i3 and is used in
12748 i2 but does not die in i2, and place is between i2
12749 and i3, then we may need to move a link from place to
12751 if (i2 && DF_INSN_LUID (place) > DF_INSN_LUID (i2)
12753 && DF_INSN_LUID (from_insn) > DF_INSN_LUID (i2)
12754 && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
12756 rtx links = LOG_LINKS (place);
12757 LOG_LINKS (place) = 0;
12758 distribute_links (links);
12763 if (tem == BB_HEAD (bb))
12769 /* If the register is set or already dead at PLACE, we needn't do
12770 anything with this note if it is still a REG_DEAD note.
12771 We check here if it is set at all, not if is it totally replaced,
12772 which is what `dead_or_set_p' checks, so also check for it being
12775 if (place && REG_NOTE_KIND (note) == REG_DEAD)
12777 unsigned int regno = REGNO (XEXP (note, 0));
12778 reg_stat_type *rsp = VEC_index (reg_stat_type, reg_stat, regno);
12780 if (dead_or_set_p (place, XEXP (note, 0))
12781 || reg_bitfield_target_p (XEXP (note, 0), PATTERN (place)))
12783 /* Unless the register previously died in PLACE, clear
12784 last_death. [I no longer understand why this is
12786 if (rsp->last_death != place)
12787 rsp->last_death = 0;
12791 rsp->last_death = place;
12793 /* If this is a death note for a hard reg that is occupying
12794 multiple registers, ensure that we are still using all
12795 parts of the object. If we find a piece of the object
12796 that is unused, we must arrange for an appropriate REG_DEAD
12797 note to be added for it. However, we can't just emit a USE
12798 and tag the note to it, since the register might actually
12799 be dead; so we recourse, and the recursive call then finds
12800 the previous insn that used this register. */
12802 if (place && regno < FIRST_PSEUDO_REGISTER
12803 && hard_regno_nregs[regno][GET_MODE (XEXP (note, 0))] > 1)
12805 unsigned int endregno = END_HARD_REGNO (XEXP (note, 0));
12809 for (i = regno; i < endregno; i++)
12810 if ((! refers_to_regno_p (i, i + 1, PATTERN (place), 0)
12811 && ! find_regno_fusage (place, USE, i))
12812 || dead_or_set_regno_p (place, i))
12817 /* Put only REG_DEAD notes for pieces that are
12818 not already dead or set. */
12820 for (i = regno; i < endregno;
12821 i += hard_regno_nregs[i][reg_raw_mode[i]])
12823 rtx piece = regno_reg_rtx[i];
12824 basic_block bb = this_basic_block;
12826 if (! dead_or_set_p (place, piece)
12827 && ! reg_bitfield_target_p (piece,
12831 = gen_rtx_EXPR_LIST (REG_DEAD, piece, NULL_RTX);
12833 distribute_notes (new_note, place, place,
12834 NULL_RTX, NULL_RTX, NULL_RTX);
12836 else if (! refers_to_regno_p (i, i + 1,
12837 PATTERN (place), 0)
12838 && ! find_regno_fusage (place, USE, i))
12839 for (tem = PREV_INSN (place); ;
12840 tem = PREV_INSN (tem))
12842 if (! INSN_P (tem))
12844 if (tem == BB_HEAD (bb))
12848 if (dead_or_set_p (tem, piece)
12849 || reg_bitfield_target_p (piece,
12853 = gen_rtx_EXPR_LIST (REG_UNUSED, piece,
12868 /* Any other notes should not be present at this point in the
12870 gcc_unreachable ();
12875 XEXP (note, 1) = REG_NOTES (place);
12876 REG_NOTES (place) = note;
12881 = gen_rtx_fmt_ee (GET_CODE (note), REG_NOTE_KIND (note),
12882 XEXP (note, 0), REG_NOTES (place2));
12886 /* Similarly to above, distribute the LOG_LINKS that used to be present on
12887 I3, I2, and I1 to new locations. This is also called to add a link
12888 pointing at I3 when I3's destination is changed. */
12891 distribute_links (rtx links)
12893 rtx link, next_link;
12895 for (link = links; link; link = next_link)
12901 next_link = XEXP (link, 1);
12903 /* If the insn that this link points to is a NOTE or isn't a single
12904 set, ignore it. In the latter case, it isn't clear what we
12905 can do other than ignore the link, since we can't tell which
12906 register it was for. Such links wouldn't be used by combine
12909 It is not possible for the destination of the target of the link to
12910 have been changed by combine. The only potential of this is if we
12911 replace I3, I2, and I1 by I3 and I2. But in that case the
12912 destination of I2 also remains unchanged. */
12914 if (NOTE_P (XEXP (link, 0))
12915 || (set = single_set (XEXP (link, 0))) == 0)
12918 reg = SET_DEST (set);
12919 while (GET_CODE (reg) == SUBREG || GET_CODE (reg) == ZERO_EXTRACT
12920 || GET_CODE (reg) == STRICT_LOW_PART)
12921 reg = XEXP (reg, 0);
12923 /* A LOG_LINK is defined as being placed on the first insn that uses
12924 a register and points to the insn that sets the register. Start
12925 searching at the next insn after the target of the link and stop
12926 when we reach a set of the register or the end of the basic block.
12928 Note that this correctly handles the link that used to point from
12929 I3 to I2. Also note that not much searching is typically done here
12930 since most links don't point very far away. */
12932 for (insn = NEXT_INSN (XEXP (link, 0));
12933 (insn && (this_basic_block->next_bb == EXIT_BLOCK_PTR
12934 || BB_HEAD (this_basic_block->next_bb) != insn));
12935 insn = NEXT_INSN (insn))
12936 if (INSN_P (insn) && reg_overlap_mentioned_p (reg, PATTERN (insn)))
12938 if (reg_referenced_p (reg, PATTERN (insn)))
12942 else if (CALL_P (insn)
12943 && find_reg_fusage (insn, USE, reg))
12948 else if (INSN_P (insn) && reg_set_p (reg, insn))
12951 /* If we found a place to put the link, place it there unless there
12952 is already a link to the same insn as LINK at that point. */
12958 for (link2 = LOG_LINKS (place); link2; link2 = XEXP (link2, 1))
12959 if (XEXP (link2, 0) == XEXP (link, 0))
12964 XEXP (link, 1) = LOG_LINKS (place);
12965 LOG_LINKS (place) = link;
12967 /* Set added_links_insn to the earliest insn we added a
12969 if (added_links_insn == 0
12970 || DF_INSN_LUID (added_links_insn) > DF_INSN_LUID (place))
12971 added_links_insn = place;
12977 /* Subroutine of unmentioned_reg_p and callback from for_each_rtx.
12978 Check whether the expression pointer to by LOC is a register or
12979 memory, and if so return 1 if it isn't mentioned in the rtx EXPR.
12980 Otherwise return zero. */
12983 unmentioned_reg_p_1 (rtx *loc, void *expr)
12988 && (REG_P (x) || MEM_P (x))
12989 && ! reg_mentioned_p (x, (rtx) expr))
12994 /* Check for any register or memory mentioned in EQUIV that is not
12995 mentioned in EXPR. This is used to restrict EQUIV to "specializations"
12996 of EXPR where some registers may have been replaced by constants. */
12999 unmentioned_reg_p (rtx equiv, rtx expr)
13001 return for_each_rtx (&equiv, unmentioned_reg_p_1, expr);
13005 dump_combine_stats (FILE *file)
13009 ";; Combiner statistics: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n\n",
13010 combine_attempts, combine_merges, combine_extras, combine_successes);
13014 dump_combine_total_stats (FILE *file)
13018 "\n;; Combiner totals: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n",
13019 total_attempts, total_merges, total_extras, total_successes);
13023 gate_handle_combine (void)
13025 return (optimize > 0);
13028 /* Try combining insns through substitution. */
13029 static unsigned int
13030 rest_of_handle_combine (void)
13032 int rebuild_jump_labels_after_combine;
13034 df_set_flags (DF_LR_RUN_DCE + DF_DEFER_INSN_RESCAN);
13035 df_note_add_problem ();
13038 regstat_init_n_sets_and_refs ();
13040 rebuild_jump_labels_after_combine
13041 = combine_instructions (get_insns (), max_reg_num ());
13043 /* Combining insns may have turned an indirect jump into a
13044 direct jump. Rebuild the JUMP_LABEL fields of jumping
13046 if (rebuild_jump_labels_after_combine)
13048 timevar_push (TV_JUMP);
13049 rebuild_jump_labels (get_insns ());
13051 timevar_pop (TV_JUMP);
13054 regstat_free_n_sets_and_refs ();
13058 struct rtl_opt_pass pass_combine =
13062 "combine", /* name */
13063 gate_handle_combine, /* gate */
13064 rest_of_handle_combine, /* execute */
13067 0, /* static_pass_number */
13068 TV_COMBINE, /* tv_id */
13069 0, /* properties_required */
13070 0, /* properties_provided */
13071 0, /* properties_destroyed */
13072 0, /* todo_flags_start */
13074 TODO_df_finish | TODO_verify_rtl_sharing |
13075 TODO_ggc_collect, /* todo_flags_finish */
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