1 /* Optimize by combining instructions for GNU compiler.
2 Copyright (C) 1987, 1988, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it under
8 the terms of the GNU General Public License as published by the Free
9 Software Foundation; either version 2, or (at your option) any later
12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING. If not, write to the Free
19 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
22 /* This module is essentially the "combiner" phase of the U. of Arizona
23 Portable Optimizer, but redone to work on our list-structured
24 representation for RTL instead of their string representation.
26 The LOG_LINKS of each insn identify the most recent assignment
27 to each REG used in the insn. It is a list of previous insns,
28 each of which contains a SET for a REG that is used in this insn
29 and not used or set in between. LOG_LINKs never cross basic blocks.
30 They were set up by the preceding pass (lifetime analysis).
32 We try to combine each pair of insns joined by a logical link.
33 We also try to combine triples of insns A, B and C when
34 C has a link back to B and B has a link back to A.
36 LOG_LINKS does not have links for use of the CC0. They don't
37 need to, because the insn that sets the CC0 is always immediately
38 before the insn that tests it. So we always regard a branch
39 insn as having a logical link to the preceding insn. The same is true
40 for an insn explicitly using CC0.
42 We check (with use_crosses_set_p) to avoid combining in such a way
43 as to move a computation to a place where its value would be different.
45 Combination is done by mathematically substituting the previous
46 insn(s) values for the regs they set into the expressions in
47 the later insns that refer to these regs. If the result is a valid insn
48 for our target machine, according to the machine description,
49 we install it, delete the earlier insns, and update the data flow
50 information (LOG_LINKS and REG_NOTES) for what we did.
52 There are a few exceptions where the dataflow information created by
53 flow.c aren't completely updated:
55 - reg_live_length is not updated
56 - reg_n_refs is not adjusted in the rare case when a register is
57 no longer required in a computation
58 - there are extremely rare cases (see distribute_regnotes) when a
60 - a LOG_LINKS entry that refers to an insn with multiple SETs may be
61 removed because there is no way to know which register it was
64 To simplify substitution, we combine only when the earlier insn(s)
65 consist of only a single assignment. To simplify updating afterward,
66 we never combine when a subroutine call appears in the middle.
68 Since we do not represent assignments to CC0 explicitly except when that
69 is all an insn does, there is no LOG_LINKS entry in an insn that uses
70 the condition code for the insn that set the condition code.
71 Fortunately, these two insns must be consecutive.
72 Therefore, every JUMP_INSN is taken to have an implicit logical link
73 to the preceding insn. This is not quite right, since non-jumps can
74 also use the condition code; but in practice such insns would not
83 #include "hard-reg-set.h"
84 #include "basic-block.h"
85 #include "insn-config.h"
87 /* Include expr.h after insn-config.h so we get HAVE_conditional_move. */
89 #include "insn-attr.h"
94 /* It is not safe to use ordinary gen_lowpart in combine.
95 Use gen_lowpart_for_combine instead. See comments there. */
96 #define gen_lowpart dont_use_gen_lowpart_you_dummy
98 /* Number of attempts to combine instructions in this function. */
100 static int combine_attempts;
102 /* Number of attempts that got as far as substitution in this function. */
104 static int combine_merges;
106 /* Number of instructions combined with added SETs in this function. */
108 static int combine_extras;
110 /* Number of instructions combined in this function. */
112 static int combine_successes;
114 /* Totals over entire compilation. */
116 static int total_attempts, total_merges, total_extras, total_successes;
119 /* Vector mapping INSN_UIDs to cuids.
120 The cuids are like uids but increase monotonically always.
121 Combine always uses cuids so that it can compare them.
122 But actually renumbering the uids, which we used to do,
123 proves to be a bad idea because it makes it hard to compare
124 the dumps produced by earlier passes with those from later passes. */
126 static int *uid_cuid;
127 static int max_uid_cuid;
129 /* Get the cuid of an insn. */
131 #define INSN_CUID(INSN) \
132 (INSN_UID (INSN) > max_uid_cuid ? insn_cuid (INSN) : uid_cuid[INSN_UID (INSN)])
134 /* In case BITS_PER_WORD == HOST_BITS_PER_WIDE_INT, shifting by
135 BITS_PER_WORD would invoke undefined behavior. Work around it. */
137 #define UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD(val) \
138 (((unsigned HOST_WIDE_INT) (val) << (BITS_PER_WORD - 1)) << 1)
140 /* Maximum register number, which is the size of the tables below. */
142 static unsigned int combine_max_regno;
144 /* Record last point of death of (hard or pseudo) register n. */
146 static rtx *reg_last_death;
148 /* Record last point of modification of (hard or pseudo) register n. */
150 static rtx *reg_last_set;
152 /* Record the cuid of the last insn that invalidated memory
153 (anything that writes memory, and subroutine calls, but not pushes). */
155 static int mem_last_set;
157 /* Record the cuid of the last CALL_INSN
158 so we can tell whether a potential combination crosses any calls. */
160 static int last_call_cuid;
162 /* When `subst' is called, this is the insn that is being modified
163 (by combining in a previous insn). The PATTERN of this insn
164 is still the old pattern partially modified and it should not be
165 looked at, but this may be used to examine the successors of the insn
166 to judge whether a simplification is valid. */
168 static rtx subst_insn;
170 /* This is an insn that belongs before subst_insn, but is not currently
171 on the insn chain. */
173 static rtx subst_prev_insn;
175 /* This is the lowest CUID that `subst' is currently dealing with.
176 get_last_value will not return a value if the register was set at or
177 after this CUID. If not for this mechanism, we could get confused if
178 I2 or I1 in try_combine were an insn that used the old value of a register
179 to obtain a new value. In that case, we might erroneously get the
180 new value of the register when we wanted the old one. */
182 static int subst_low_cuid;
184 /* This contains any hard registers that are used in newpat; reg_dead_at_p
185 must consider all these registers to be always live. */
187 static HARD_REG_SET newpat_used_regs;
189 /* This is an insn to which a LOG_LINKS entry has been added. If this
190 insn is the earlier than I2 or I3, combine should rescan starting at
193 static rtx added_links_insn;
195 /* Basic block number of the block in which we are performing combines. */
196 static int this_basic_block;
198 /* A bitmap indicating which blocks had registers go dead at entry.
199 After combine, we'll need to re-do global life analysis with
200 those blocks as starting points. */
201 static sbitmap refresh_blocks;
202 static int need_refresh;
204 /* The next group of arrays allows the recording of the last value assigned
205 to (hard or pseudo) register n. We use this information to see if a
206 operation being processed is redundant given a prior operation performed
207 on the register. For example, an `and' with a constant is redundant if
208 all the zero bits are already known to be turned off.
210 We use an approach similar to that used by cse, but change it in the
213 (1) We do not want to reinitialize at each label.
214 (2) It is useful, but not critical, to know the actual value assigned
215 to a register. Often just its form is helpful.
217 Therefore, we maintain the following arrays:
219 reg_last_set_value the last value assigned
220 reg_last_set_label records the value of label_tick when the
221 register was assigned
222 reg_last_set_table_tick records the value of label_tick when a
223 value using the register is assigned
224 reg_last_set_invalid set to non-zero when it is not valid
225 to use the value of this register in some
228 To understand the usage of these tables, it is important to understand
229 the distinction between the value in reg_last_set_value being valid
230 and the register being validly contained in some other expression in the
233 Entry I in reg_last_set_value is valid if it is non-zero, and either
234 reg_n_sets[i] is 1 or reg_last_set_label[i] == label_tick.
236 Register I may validly appear in any expression returned for the value
237 of another register if reg_n_sets[i] is 1. It may also appear in the
238 value for register J if reg_last_set_label[i] < reg_last_set_label[j] or
239 reg_last_set_invalid[j] is zero.
241 If an expression is found in the table containing a register which may
242 not validly appear in an expression, the register is replaced by
243 something that won't match, (clobber (const_int 0)).
245 reg_last_set_invalid[i] is set non-zero when register I is being assigned
246 to and reg_last_set_table_tick[i] == label_tick. */
248 /* Record last value assigned to (hard or pseudo) register n. */
250 static rtx *reg_last_set_value;
252 /* Record the value of label_tick when the value for register n is placed in
253 reg_last_set_value[n]. */
255 static int *reg_last_set_label;
257 /* Record the value of label_tick when an expression involving register n
258 is placed in reg_last_set_value. */
260 static int *reg_last_set_table_tick;
262 /* Set non-zero if references to register n in expressions should not be
265 static char *reg_last_set_invalid;
267 /* Incremented for each label. */
269 static int label_tick;
271 /* Some registers that are set more than once and used in more than one
272 basic block are nevertheless always set in similar ways. For example,
273 a QImode register may be loaded from memory in two places on a machine
274 where byte loads zero extend.
276 We record in the following array what we know about the nonzero
277 bits of a register, specifically which bits are known to be zero.
279 If an entry is zero, it means that we don't know anything special. */
281 static unsigned HOST_WIDE_INT *reg_nonzero_bits;
283 /* Mode used to compute significance in reg_nonzero_bits. It is the largest
284 integer mode that can fit in HOST_BITS_PER_WIDE_INT. */
286 static enum machine_mode nonzero_bits_mode;
288 /* Nonzero if we know that a register has some leading bits that are always
289 equal to the sign bit. */
291 static unsigned char *reg_sign_bit_copies;
293 /* Nonzero when reg_nonzero_bits and reg_sign_bit_copies can be safely used.
294 It is zero while computing them and after combine has completed. This
295 former test prevents propagating values based on previously set values,
296 which can be incorrect if a variable is modified in a loop. */
298 static int nonzero_sign_valid;
300 /* These arrays are maintained in parallel with reg_last_set_value
301 and are used to store the mode in which the register was last set,
302 the bits that were known to be zero when it was last set, and the
303 number of sign bits copies it was known to have when it was last set. */
305 static enum machine_mode *reg_last_set_mode;
306 static unsigned HOST_WIDE_INT *reg_last_set_nonzero_bits;
307 static char *reg_last_set_sign_bit_copies;
309 /* Record one modification to rtl structure
310 to be undone by storing old_contents into *where.
311 is_int is 1 if the contents are an int. */
317 union {rtx r; unsigned int i;} old_contents;
318 union {rtx *r; unsigned int *i;} where;
321 /* Record a bunch of changes to be undone, up to MAX_UNDO of them.
322 num_undo says how many are currently recorded.
324 other_insn is nonzero if we have modified some other insn in the process
325 of working on subst_insn. It must be verified too. */
334 static struct undobuf undobuf;
336 /* Number of times the pseudo being substituted for
337 was found and replaced. */
339 static int n_occurrences;
341 static void do_SUBST PARAMS ((rtx *, rtx));
342 static void do_SUBST_INT PARAMS ((unsigned int *,
344 static void init_reg_last_arrays PARAMS ((void));
345 static void setup_incoming_promotions PARAMS ((void));
346 static void set_nonzero_bits_and_sign_copies PARAMS ((rtx, rtx, void *));
347 static int cant_combine_insn_p PARAMS ((rtx));
348 static int can_combine_p PARAMS ((rtx, rtx, rtx, rtx, rtx *, rtx *));
349 static int sets_function_arg_p PARAMS ((rtx));
350 static int combinable_i3pat PARAMS ((rtx, rtx *, rtx, rtx, int, rtx *));
351 static int contains_muldiv PARAMS ((rtx));
352 static rtx try_combine PARAMS ((rtx, rtx, rtx, int *));
353 static void undo_all PARAMS ((void));
354 static void undo_commit PARAMS ((void));
355 static rtx *find_split_point PARAMS ((rtx *, rtx));
356 static rtx subst PARAMS ((rtx, rtx, rtx, int, int));
357 static rtx combine_simplify_rtx PARAMS ((rtx, enum machine_mode, int, int));
358 static rtx simplify_if_then_else PARAMS ((rtx));
359 static rtx simplify_set PARAMS ((rtx));
360 static rtx simplify_logical PARAMS ((rtx, int));
361 static rtx expand_compound_operation PARAMS ((rtx));
362 static rtx expand_field_assignment PARAMS ((rtx));
363 static rtx make_extraction PARAMS ((enum machine_mode, rtx, HOST_WIDE_INT,
364 rtx, unsigned HOST_WIDE_INT, int,
366 static rtx extract_left_shift PARAMS ((rtx, int));
367 static rtx make_compound_operation PARAMS ((rtx, enum rtx_code));
368 static int get_pos_from_mask PARAMS ((unsigned HOST_WIDE_INT,
369 unsigned HOST_WIDE_INT *));
370 static rtx force_to_mode PARAMS ((rtx, enum machine_mode,
371 unsigned HOST_WIDE_INT, rtx, int));
372 static rtx if_then_else_cond PARAMS ((rtx, rtx *, rtx *));
373 static rtx known_cond PARAMS ((rtx, enum rtx_code, rtx, rtx));
374 static int rtx_equal_for_field_assignment_p PARAMS ((rtx, rtx));
375 static rtx make_field_assignment PARAMS ((rtx));
376 static rtx apply_distributive_law PARAMS ((rtx));
377 static rtx simplify_and_const_int PARAMS ((rtx, enum machine_mode, rtx,
378 unsigned HOST_WIDE_INT));
379 static unsigned HOST_WIDE_INT nonzero_bits PARAMS ((rtx, enum machine_mode));
380 static unsigned int num_sign_bit_copies PARAMS ((rtx, enum machine_mode));
381 static int merge_outer_ops PARAMS ((enum rtx_code *, HOST_WIDE_INT *,
382 enum rtx_code, HOST_WIDE_INT,
383 enum machine_mode, int *));
384 static rtx simplify_shift_const PARAMS ((rtx, enum rtx_code, enum machine_mode,
386 static int recog_for_combine PARAMS ((rtx *, rtx, rtx *));
387 static rtx gen_lowpart_for_combine PARAMS ((enum machine_mode, rtx));
388 static rtx gen_binary PARAMS ((enum rtx_code, enum machine_mode,
390 static enum rtx_code simplify_comparison PARAMS ((enum rtx_code, rtx *, rtx *));
391 static void update_table_tick PARAMS ((rtx));
392 static void record_value_for_reg PARAMS ((rtx, rtx, rtx));
393 static void check_promoted_subreg PARAMS ((rtx, rtx));
394 static void record_dead_and_set_regs_1 PARAMS ((rtx, rtx, void *));
395 static void record_dead_and_set_regs PARAMS ((rtx));
396 static int get_last_value_validate PARAMS ((rtx *, rtx, int, int));
397 static rtx get_last_value PARAMS ((rtx));
398 static int use_crosses_set_p PARAMS ((rtx, int));
399 static void reg_dead_at_p_1 PARAMS ((rtx, rtx, void *));
400 static int reg_dead_at_p PARAMS ((rtx, rtx));
401 static void move_deaths PARAMS ((rtx, rtx, int, rtx, rtx *));
402 static int reg_bitfield_target_p PARAMS ((rtx, rtx));
403 static void distribute_notes PARAMS ((rtx, rtx, rtx, rtx, rtx, rtx));
404 static void distribute_links PARAMS ((rtx));
405 static void mark_used_regs_combine PARAMS ((rtx));
406 static int insn_cuid PARAMS ((rtx));
407 static void record_promoted_value PARAMS ((rtx, rtx));
408 static rtx reversed_comparison PARAMS ((rtx, enum machine_mode, rtx, rtx));
409 static enum rtx_code combine_reversed_comparison_code PARAMS ((rtx));
411 /* Substitute NEWVAL, an rtx expression, into INTO, a place in some
412 insn. The substitution can be undone by undo_all. If INTO is already
413 set to NEWVAL, do not record this change. Because computing NEWVAL might
414 also call SUBST, we have to compute it before we put anything into
418 do_SUBST (into, newval)
424 if (oldval == newval)
427 /* We'd like to catch as many invalid transformations here as
428 possible. Unfortunately, there are way too many mode changes
429 that are perfectly valid, so we'd waste too much effort for
430 little gain doing the checks here. Focus on catching invalid
431 transformations involving integer constants. */
432 if (GET_MODE_CLASS (GET_MODE (oldval)) == MODE_INT
433 && GET_CODE (newval) == CONST_INT)
435 /* Sanity check that we're replacing oldval with a CONST_INT
436 that is a valid sign-extension for the original mode. */
437 if (INTVAL (newval) != trunc_int_for_mode (INTVAL (newval),
441 /* Replacing the operand of a SUBREG or a ZERO_EXTEND with a
442 CONST_INT is not valid, because after the replacement, the
443 original mode would be gone. Unfortunately, we can't tell
444 when do_SUBST is called to replace the operand thereof, so we
445 perform this test on oldval instead, checking whether an
446 invalid replacement took place before we got here. */
447 if ((GET_CODE (oldval) == SUBREG
448 && GET_CODE (SUBREG_REG (oldval)) == CONST_INT)
449 || (GET_CODE (oldval) == ZERO_EXTEND
450 && GET_CODE (XEXP (oldval, 0)) == CONST_INT))
455 buf = undobuf.frees, undobuf.frees = buf->next;
457 buf = (struct undo *) xmalloc (sizeof (struct undo));
461 buf->old_contents.r = oldval;
464 buf->next = undobuf.undos, undobuf.undos = buf;
467 #define SUBST(INTO, NEWVAL) do_SUBST(&(INTO), (NEWVAL))
469 /* Similar to SUBST, but NEWVAL is an int expression. Note that substitution
470 for the value of a HOST_WIDE_INT value (including CONST_INT) is
474 do_SUBST_INT (into, newval)
475 unsigned int *into, newval;
478 unsigned int oldval = *into;
480 if (oldval == newval)
484 buf = undobuf.frees, undobuf.frees = buf->next;
486 buf = (struct undo *) xmalloc (sizeof (struct undo));
490 buf->old_contents.i = oldval;
493 buf->next = undobuf.undos, undobuf.undos = buf;
496 #define SUBST_INT(INTO, NEWVAL) do_SUBST_INT(&(INTO), (NEWVAL))
498 /* Main entry point for combiner. F is the first insn of the function.
499 NREGS is the first unused pseudo-reg number.
501 Return non-zero if the combiner has turned an indirect jump
502 instruction into a direct jump. */
504 combine_instructions (f, nregs)
513 rtx links, nextlinks;
515 int new_direct_jump_p = 0;
517 combine_attempts = 0;
520 combine_successes = 0;
522 combine_max_regno = nregs;
524 reg_nonzero_bits = ((unsigned HOST_WIDE_INT *)
525 xcalloc (nregs, sizeof (unsigned HOST_WIDE_INT)));
527 = (unsigned char *) xcalloc (nregs, sizeof (unsigned char));
529 reg_last_death = (rtx *) xmalloc (nregs * sizeof (rtx));
530 reg_last_set = (rtx *) xmalloc (nregs * sizeof (rtx));
531 reg_last_set_value = (rtx *) xmalloc (nregs * sizeof (rtx));
532 reg_last_set_table_tick = (int *) xmalloc (nregs * sizeof (int));
533 reg_last_set_label = (int *) xmalloc (nregs * sizeof (int));
534 reg_last_set_invalid = (char *) xmalloc (nregs * sizeof (char));
536 = (enum machine_mode *) xmalloc (nregs * sizeof (enum machine_mode));
537 reg_last_set_nonzero_bits
538 = (unsigned HOST_WIDE_INT *) xmalloc (nregs * sizeof (HOST_WIDE_INT));
539 reg_last_set_sign_bit_copies
540 = (char *) xmalloc (nregs * sizeof (char));
542 init_reg_last_arrays ();
544 init_recog_no_volatile ();
546 /* Compute maximum uid value so uid_cuid can be allocated. */
548 for (insn = f, i = 0; insn; insn = NEXT_INSN (insn))
549 if (INSN_UID (insn) > i)
552 uid_cuid = (int *) xmalloc ((i + 1) * sizeof (int));
555 nonzero_bits_mode = mode_for_size (HOST_BITS_PER_WIDE_INT, MODE_INT, 0);
557 /* Don't use reg_nonzero_bits when computing it. This can cause problems
558 when, for example, we have j <<= 1 in a loop. */
560 nonzero_sign_valid = 0;
562 /* Compute the mapping from uids to cuids.
563 Cuids are numbers assigned to insns, like uids,
564 except that cuids increase monotonically through the code.
566 Scan all SETs and see if we can deduce anything about what
567 bits are known to be zero for some registers and how many copies
568 of the sign bit are known to exist for those registers.
570 Also set any known values so that we can use it while searching
571 for what bits are known to be set. */
575 /* We need to initialize it here, because record_dead_and_set_regs may call
577 subst_prev_insn = NULL_RTX;
579 setup_incoming_promotions ();
581 refresh_blocks = sbitmap_alloc (n_basic_blocks);
582 sbitmap_zero (refresh_blocks);
585 for (insn = f, i = 0; insn; insn = NEXT_INSN (insn))
587 uid_cuid[INSN_UID (insn)] = ++i;
593 note_stores (PATTERN (insn), set_nonzero_bits_and_sign_copies,
595 record_dead_and_set_regs (insn);
598 for (links = REG_NOTES (insn); links; links = XEXP (links, 1))
599 if (REG_NOTE_KIND (links) == REG_INC)
600 set_nonzero_bits_and_sign_copies (XEXP (links, 0), NULL_RTX,
605 if (GET_CODE (insn) == CODE_LABEL)
609 nonzero_sign_valid = 1;
611 /* Now scan all the insns in forward order. */
613 this_basic_block = -1;
617 init_reg_last_arrays ();
618 setup_incoming_promotions ();
620 for (insn = f; insn; insn = next ? next : NEXT_INSN (insn))
624 /* If INSN starts a new basic block, update our basic block number. */
625 if (this_basic_block + 1 < n_basic_blocks
626 && BLOCK_HEAD (this_basic_block + 1) == insn)
629 if (GET_CODE (insn) == CODE_LABEL)
632 else if (INSN_P (insn))
634 /* See if we know about function return values before this
635 insn based upon SUBREG flags. */
636 check_promoted_subreg (insn, PATTERN (insn));
638 /* Try this insn with each insn it links back to. */
640 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
641 if ((next = try_combine (insn, XEXP (links, 0),
642 NULL_RTX, &new_direct_jump_p)) != 0)
645 /* Try each sequence of three linked insns ending with this one. */
647 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
649 rtx link = XEXP (links, 0);
651 /* If the linked insn has been replaced by a note, then there
652 is no point in pursuing this chain any further. */
653 if (GET_CODE (link) == NOTE)
656 for (nextlinks = LOG_LINKS (link);
658 nextlinks = XEXP (nextlinks, 1))
659 if ((next = try_combine (insn, link,
661 &new_direct_jump_p)) != 0)
666 /* Try to combine a jump insn that uses CC0
667 with a preceding insn that sets CC0, and maybe with its
668 logical predecessor as well.
669 This is how we make decrement-and-branch insns.
670 We need this special code because data flow connections
671 via CC0 do not get entered in LOG_LINKS. */
673 if (GET_CODE (insn) == JUMP_INSN
674 && (prev = prev_nonnote_insn (insn)) != 0
675 && GET_CODE (prev) == INSN
676 && sets_cc0_p (PATTERN (prev)))
678 if ((next = try_combine (insn, prev,
679 NULL_RTX, &new_direct_jump_p)) != 0)
682 for (nextlinks = LOG_LINKS (prev); nextlinks;
683 nextlinks = XEXP (nextlinks, 1))
684 if ((next = try_combine (insn, prev,
686 &new_direct_jump_p)) != 0)
690 /* Do the same for an insn that explicitly references CC0. */
691 if (GET_CODE (insn) == INSN
692 && (prev = prev_nonnote_insn (insn)) != 0
693 && GET_CODE (prev) == INSN
694 && sets_cc0_p (PATTERN (prev))
695 && GET_CODE (PATTERN (insn)) == SET
696 && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (insn))))
698 if ((next = try_combine (insn, prev,
699 NULL_RTX, &new_direct_jump_p)) != 0)
702 for (nextlinks = LOG_LINKS (prev); nextlinks;
703 nextlinks = XEXP (nextlinks, 1))
704 if ((next = try_combine (insn, prev,
706 &new_direct_jump_p)) != 0)
710 /* Finally, see if any of the insns that this insn links to
711 explicitly references CC0. If so, try this insn, that insn,
712 and its predecessor if it sets CC0. */
713 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
714 if (GET_CODE (XEXP (links, 0)) == INSN
715 && GET_CODE (PATTERN (XEXP (links, 0))) == SET
716 && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (XEXP (links, 0))))
717 && (prev = prev_nonnote_insn (XEXP (links, 0))) != 0
718 && GET_CODE (prev) == INSN
719 && sets_cc0_p (PATTERN (prev))
720 && (next = try_combine (insn, XEXP (links, 0),
721 prev, &new_direct_jump_p)) != 0)
725 /* Try combining an insn with two different insns whose results it
727 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
728 for (nextlinks = XEXP (links, 1); nextlinks;
729 nextlinks = XEXP (nextlinks, 1))
730 if ((next = try_combine (insn, XEXP (links, 0),
732 &new_direct_jump_p)) != 0)
735 if (GET_CODE (insn) != NOTE)
736 record_dead_and_set_regs (insn);
743 delete_noop_moves (f);
747 update_life_info (refresh_blocks, UPDATE_LIFE_GLOBAL_RM_NOTES,
752 sbitmap_free (refresh_blocks);
753 free (reg_nonzero_bits);
754 free (reg_sign_bit_copies);
755 free (reg_last_death);
757 free (reg_last_set_value);
758 free (reg_last_set_table_tick);
759 free (reg_last_set_label);
760 free (reg_last_set_invalid);
761 free (reg_last_set_mode);
762 free (reg_last_set_nonzero_bits);
763 free (reg_last_set_sign_bit_copies);
767 struct undo *undo, *next;
768 for (undo = undobuf.frees; undo; undo = next)
776 total_attempts += combine_attempts;
777 total_merges += combine_merges;
778 total_extras += combine_extras;
779 total_successes += combine_successes;
781 nonzero_sign_valid = 0;
783 /* Make recognizer allow volatile MEMs again. */
786 return new_direct_jump_p;
789 /* Wipe the reg_last_xxx arrays in preparation for another pass. */
792 init_reg_last_arrays ()
794 unsigned int nregs = combine_max_regno;
796 memset ((char *) reg_last_death, 0, nregs * sizeof (rtx));
797 memset ((char *) reg_last_set, 0, nregs * sizeof (rtx));
798 memset ((char *) reg_last_set_value, 0, nregs * sizeof (rtx));
799 memset ((char *) reg_last_set_table_tick, 0, nregs * sizeof (int));
800 memset ((char *) reg_last_set_label, 0, nregs * sizeof (int));
801 memset (reg_last_set_invalid, 0, nregs * sizeof (char));
802 memset ((char *) reg_last_set_mode, 0, nregs * sizeof (enum machine_mode));
803 memset ((char *) reg_last_set_nonzero_bits, 0, nregs * sizeof (HOST_WIDE_INT));
804 memset (reg_last_set_sign_bit_copies, 0, nregs * sizeof (char));
807 /* Set up any promoted values for incoming argument registers. */
810 setup_incoming_promotions ()
812 #ifdef PROMOTE_FUNCTION_ARGS
815 enum machine_mode mode;
817 rtx first = get_insns ();
819 #ifndef OUTGOING_REGNO
820 #define OUTGOING_REGNO(N) N
822 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
823 /* Check whether this register can hold an incoming pointer
824 argument. FUNCTION_ARG_REGNO_P tests outgoing register
825 numbers, so translate if necessary due to register windows. */
826 if (FUNCTION_ARG_REGNO_P (OUTGOING_REGNO (regno))
827 && (reg = promoted_input_arg (regno, &mode, &unsignedp)) != 0)
830 (reg, first, gen_rtx_fmt_e ((unsignedp ? ZERO_EXTEND
833 gen_rtx_CLOBBER (mode, const0_rtx)));
838 /* Called via note_stores. If X is a pseudo that is narrower than
839 HOST_BITS_PER_WIDE_INT and is being set, record what bits are known zero.
841 If we are setting only a portion of X and we can't figure out what
842 portion, assume all bits will be used since we don't know what will
845 Similarly, set how many bits of X are known to be copies of the sign bit
846 at all locations in the function. This is the smallest number implied
850 set_nonzero_bits_and_sign_copies (x, set, data)
853 void *data ATTRIBUTE_UNUSED;
857 if (GET_CODE (x) == REG
858 && REGNO (x) >= FIRST_PSEUDO_REGISTER
859 /* If this register is undefined at the start of the file, we can't
860 say what its contents were. */
861 && ! REGNO_REG_SET_P (BASIC_BLOCK (0)->global_live_at_start, REGNO (x))
862 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT)
864 if (set == 0 || GET_CODE (set) == CLOBBER)
866 reg_nonzero_bits[REGNO (x)] = GET_MODE_MASK (GET_MODE (x));
867 reg_sign_bit_copies[REGNO (x)] = 1;
871 /* If this is a complex assignment, see if we can convert it into a
872 simple assignment. */
873 set = expand_field_assignment (set);
875 /* If this is a simple assignment, or we have a paradoxical SUBREG,
876 set what we know about X. */
878 if (SET_DEST (set) == x
879 || (GET_CODE (SET_DEST (set)) == SUBREG
880 && (GET_MODE_SIZE (GET_MODE (SET_DEST (set)))
881 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (set)))))
882 && SUBREG_REG (SET_DEST (set)) == x))
884 rtx src = SET_SRC (set);
886 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
887 /* If X is narrower than a word and SRC is a non-negative
888 constant that would appear negative in the mode of X,
889 sign-extend it for use in reg_nonzero_bits because some
890 machines (maybe most) will actually do the sign-extension
891 and this is the conservative approach.
893 ??? For 2.5, try to tighten up the MD files in this regard
894 instead of this kludge. */
896 if (GET_MODE_BITSIZE (GET_MODE (x)) < BITS_PER_WORD
897 && GET_CODE (src) == CONST_INT
899 && 0 != (INTVAL (src)
901 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
902 src = GEN_INT (INTVAL (src)
903 | ((HOST_WIDE_INT) (-1)
904 << GET_MODE_BITSIZE (GET_MODE (x))));
907 reg_nonzero_bits[REGNO (x)]
908 |= nonzero_bits (src, nonzero_bits_mode);
909 num = num_sign_bit_copies (SET_SRC (set), GET_MODE (x));
910 if (reg_sign_bit_copies[REGNO (x)] == 0
911 || reg_sign_bit_copies[REGNO (x)] > num)
912 reg_sign_bit_copies[REGNO (x)] = num;
916 reg_nonzero_bits[REGNO (x)] = GET_MODE_MASK (GET_MODE (x));
917 reg_sign_bit_copies[REGNO (x)] = 1;
922 /* See if INSN can be combined into I3. PRED and SUCC are optionally
923 insns that were previously combined into I3 or that will be combined
924 into the merger of INSN and I3.
926 Return 0 if the combination is not allowed for any reason.
928 If the combination is allowed, *PDEST will be set to the single
929 destination of INSN and *PSRC to the single source, and this function
933 can_combine_p (insn, i3, pred, succ, pdest, psrc)
936 rtx pred ATTRIBUTE_UNUSED;
941 rtx set = 0, src, dest;
946 int all_adjacent = (succ ? (next_active_insn (insn) == succ
947 && next_active_insn (succ) == i3)
948 : next_active_insn (insn) == i3);
950 /* Can combine only if previous insn is a SET of a REG, a SUBREG or CC0.
951 or a PARALLEL consisting of such a SET and CLOBBERs.
953 If INSN has CLOBBER parallel parts, ignore them for our processing.
954 By definition, these happen during the execution of the insn. When it
955 is merged with another insn, all bets are off. If they are, in fact,
956 needed and aren't also supplied in I3, they may be added by
957 recog_for_combine. Otherwise, it won't match.
959 We can also ignore a SET whose SET_DEST is mentioned in a REG_UNUSED
962 Get the source and destination of INSN. If more than one, can't
965 if (GET_CODE (PATTERN (insn)) == SET)
966 set = PATTERN (insn);
967 else if (GET_CODE (PATTERN (insn)) == PARALLEL
968 && GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == SET)
970 for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
972 rtx elt = XVECEXP (PATTERN (insn), 0, i);
974 switch (GET_CODE (elt))
976 /* This is important to combine floating point insns
979 /* Combining an isolated USE doesn't make sense.
980 We depend here on combinable_i3pat to reject them. */
981 /* The code below this loop only verifies that the inputs of
982 the SET in INSN do not change. We call reg_set_between_p
983 to verify that the REG in the USE does not change between
985 If the USE in INSN was for a pseudo register, the matching
986 insn pattern will likely match any register; combining this
987 with any other USE would only be safe if we knew that the
988 used registers have identical values, or if there was
989 something to tell them apart, e.g. different modes. For
990 now, we forgo such complicated tests and simply disallow
991 combining of USES of pseudo registers with any other USE. */
992 if (GET_CODE (XEXP (elt, 0)) == REG
993 && GET_CODE (PATTERN (i3)) == PARALLEL)
995 rtx i3pat = PATTERN (i3);
996 int i = XVECLEN (i3pat, 0) - 1;
997 unsigned int regno = REGNO (XEXP (elt, 0));
1001 rtx i3elt = XVECEXP (i3pat, 0, i);
1003 if (GET_CODE (i3elt) == USE
1004 && GET_CODE (XEXP (i3elt, 0)) == REG
1005 && (REGNO (XEXP (i3elt, 0)) == regno
1006 ? reg_set_between_p (XEXP (elt, 0),
1007 PREV_INSN (insn), i3)
1008 : regno >= FIRST_PSEUDO_REGISTER))
1015 /* We can ignore CLOBBERs. */
1020 /* Ignore SETs whose result isn't used but not those that
1021 have side-effects. */
1022 if (find_reg_note (insn, REG_UNUSED, SET_DEST (elt))
1023 && ! side_effects_p (elt))
1026 /* If we have already found a SET, this is a second one and
1027 so we cannot combine with this insn. */
1035 /* Anything else means we can't combine. */
1041 /* If SET_SRC is an ASM_OPERANDS we can't throw away these CLOBBERs,
1042 so don't do anything with it. */
1043 || GET_CODE (SET_SRC (set)) == ASM_OPERANDS)
1052 set = expand_field_assignment (set);
1053 src = SET_SRC (set), dest = SET_DEST (set);
1055 /* Don't eliminate a store in the stack pointer. */
1056 if (dest == stack_pointer_rtx
1057 /* If we couldn't eliminate a field assignment, we can't combine. */
1058 || GET_CODE (dest) == ZERO_EXTRACT || GET_CODE (dest) == STRICT_LOW_PART
1059 /* Don't combine with an insn that sets a register to itself if it has
1060 a REG_EQUAL note. This may be part of a REG_NO_CONFLICT sequence. */
1061 || (rtx_equal_p (src, dest) && find_reg_note (insn, REG_EQUAL, NULL_RTX))
1062 /* Can't merge an ASM_OPERANDS. */
1063 || GET_CODE (src) == ASM_OPERANDS
1064 /* Can't merge a function call. */
1065 || GET_CODE (src) == CALL
1066 /* Don't eliminate a function call argument. */
1067 || (GET_CODE (i3) == CALL_INSN
1068 && (find_reg_fusage (i3, USE, dest)
1069 || (GET_CODE (dest) == REG
1070 && REGNO (dest) < FIRST_PSEUDO_REGISTER
1071 && global_regs[REGNO (dest)])))
1072 /* Don't substitute into an incremented register. */
1073 || FIND_REG_INC_NOTE (i3, dest)
1074 || (succ && FIND_REG_INC_NOTE (succ, dest))
1076 /* Don't combine the end of a libcall into anything. */
1077 /* ??? This gives worse code, and appears to be unnecessary, since no
1078 pass after flow uses REG_LIBCALL/REG_RETVAL notes. Local-alloc does
1079 use REG_RETVAL notes for noconflict blocks, but other code here
1080 makes sure that those insns don't disappear. */
1081 || find_reg_note (insn, REG_RETVAL, NULL_RTX)
1083 /* Make sure that DEST is not used after SUCC but before I3. */
1084 || (succ && ! all_adjacent
1085 && reg_used_between_p (dest, succ, i3))
1086 /* Make sure that the value that is to be substituted for the register
1087 does not use any registers whose values alter in between. However,
1088 If the insns are adjacent, a use can't cross a set even though we
1089 think it might (this can happen for a sequence of insns each setting
1090 the same destination; reg_last_set of that register might point to
1091 a NOTE). If INSN has a REG_EQUIV note, the register is always
1092 equivalent to the memory so the substitution is valid even if there
1093 are intervening stores. Also, don't move a volatile asm or
1094 UNSPEC_VOLATILE across any other insns. */
1096 && (((GET_CODE (src) != MEM
1097 || ! find_reg_note (insn, REG_EQUIV, src))
1098 && use_crosses_set_p (src, INSN_CUID (insn)))
1099 || (GET_CODE (src) == ASM_OPERANDS && MEM_VOLATILE_P (src))
1100 || GET_CODE (src) == UNSPEC_VOLATILE))
1101 /* If there is a REG_NO_CONFLICT note for DEST in I3 or SUCC, we get
1102 better register allocation by not doing the combine. */
1103 || find_reg_note (i3, REG_NO_CONFLICT, dest)
1104 || (succ && find_reg_note (succ, REG_NO_CONFLICT, dest))
1105 /* Don't combine across a CALL_INSN, because that would possibly
1106 change whether the life span of some REGs crosses calls or not,
1107 and it is a pain to update that information.
1108 Exception: if source is a constant, moving it later can't hurt.
1109 Accept that special case, because it helps -fforce-addr a lot. */
1110 || (INSN_CUID (insn) < last_call_cuid && ! CONSTANT_P (src)))
1113 /* DEST must either be a REG or CC0. */
1114 if (GET_CODE (dest) == REG)
1116 /* If register alignment is being enforced for multi-word items in all
1117 cases except for parameters, it is possible to have a register copy
1118 insn referencing a hard register that is not allowed to contain the
1119 mode being copied and which would not be valid as an operand of most
1120 insns. Eliminate this problem by not combining with such an insn.
1122 Also, on some machines we don't want to extend the life of a hard
1125 if (GET_CODE (src) == REG
1126 && ((REGNO (dest) < FIRST_PSEUDO_REGISTER
1127 && ! HARD_REGNO_MODE_OK (REGNO (dest), GET_MODE (dest)))
1128 /* Don't extend the life of a hard register unless it is
1129 user variable (if we have few registers) or it can't
1130 fit into the desired register (meaning something special
1132 Also avoid substituting a return register into I3, because
1133 reload can't handle a conflict with constraints of other
1135 || (REGNO (src) < FIRST_PSEUDO_REGISTER
1136 && ! HARD_REGNO_MODE_OK (REGNO (src), GET_MODE (src)))))
1139 else if (GET_CODE (dest) != CC0)
1142 /* Don't substitute for a register intended as a clobberable operand.
1143 Similarly, don't substitute an expression containing a register that
1144 will be clobbered in I3. */
1145 if (GET_CODE (PATTERN (i3)) == PARALLEL)
1146 for (i = XVECLEN (PATTERN (i3), 0) - 1; i >= 0; i--)
1147 if (GET_CODE (XVECEXP (PATTERN (i3), 0, i)) == CLOBBER
1148 && (reg_overlap_mentioned_p (XEXP (XVECEXP (PATTERN (i3), 0, i), 0),
1150 || rtx_equal_p (XEXP (XVECEXP (PATTERN (i3), 0, i), 0), dest)))
1153 /* If INSN contains anything volatile, or is an `asm' (whether volatile
1154 or not), reject, unless nothing volatile comes between it and I3 */
1156 if (GET_CODE (src) == ASM_OPERANDS || volatile_refs_p (src))
1158 /* Make sure succ doesn't contain a volatile reference. */
1159 if (succ != 0 && volatile_refs_p (PATTERN (succ)))
1162 for (p = NEXT_INSN (insn); p != i3; p = NEXT_INSN (p))
1163 if (INSN_P (p) && p != succ && volatile_refs_p (PATTERN (p)))
1167 /* If INSN is an asm, and DEST is a hard register, reject, since it has
1168 to be an explicit register variable, and was chosen for a reason. */
1170 if (GET_CODE (src) == ASM_OPERANDS
1171 && GET_CODE (dest) == REG && REGNO (dest) < FIRST_PSEUDO_REGISTER)
1174 /* If there are any volatile insns between INSN and I3, reject, because
1175 they might affect machine state. */
1177 for (p = NEXT_INSN (insn); p != i3; p = NEXT_INSN (p))
1178 if (INSN_P (p) && p != succ && volatile_insn_p (PATTERN (p)))
1181 /* If INSN or I2 contains an autoincrement or autodecrement,
1182 make sure that register is not used between there and I3,
1183 and not already used in I3 either.
1184 Also insist that I3 not be a jump; if it were one
1185 and the incremented register were spilled, we would lose. */
1188 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
1189 if (REG_NOTE_KIND (link) == REG_INC
1190 && (GET_CODE (i3) == JUMP_INSN
1191 || reg_used_between_p (XEXP (link, 0), insn, i3)
1192 || reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i3))))
1197 /* Don't combine an insn that follows a CC0-setting insn.
1198 An insn that uses CC0 must not be separated from the one that sets it.
1199 We do, however, allow I2 to follow a CC0-setting insn if that insn
1200 is passed as I1; in that case it will be deleted also.
1201 We also allow combining in this case if all the insns are adjacent
1202 because that would leave the two CC0 insns adjacent as well.
1203 It would be more logical to test whether CC0 occurs inside I1 or I2,
1204 but that would be much slower, and this ought to be equivalent. */
1206 p = prev_nonnote_insn (insn);
1207 if (p && p != pred && GET_CODE (p) == INSN && sets_cc0_p (PATTERN (p))
1212 /* If we get here, we have passed all the tests and the combination is
1221 /* Check if PAT is an insn - or a part of it - used to set up an
1222 argument for a function in a hard register. */
1225 sets_function_arg_p (pat)
1231 switch (GET_CODE (pat))
1234 return sets_function_arg_p (PATTERN (pat));
1237 for (i = XVECLEN (pat, 0); --i >= 0;)
1238 if (sets_function_arg_p (XVECEXP (pat, 0, i)))
1244 inner_dest = SET_DEST (pat);
1245 while (GET_CODE (inner_dest) == STRICT_LOW_PART
1246 || GET_CODE (inner_dest) == SUBREG
1247 || GET_CODE (inner_dest) == ZERO_EXTRACT)
1248 inner_dest = XEXP (inner_dest, 0);
1250 return (GET_CODE (inner_dest) == REG
1251 && REGNO (inner_dest) < FIRST_PSEUDO_REGISTER
1252 && FUNCTION_ARG_REGNO_P (REGNO (inner_dest)));
1261 /* LOC is the location within I3 that contains its pattern or the component
1262 of a PARALLEL of the pattern. We validate that it is valid for combining.
1264 One problem is if I3 modifies its output, as opposed to replacing it
1265 entirely, we can't allow the output to contain I2DEST or I1DEST as doing
1266 so would produce an insn that is not equivalent to the original insns.
1270 (set (reg:DI 101) (reg:DI 100))
1271 (set (subreg:SI (reg:DI 101) 0) <foo>)
1273 This is NOT equivalent to:
1275 (parallel [(set (subreg:SI (reg:DI 100) 0) <foo>)
1276 (set (reg:DI 101) (reg:DI 100))])
1278 Not only does this modify 100 (in which case it might still be valid
1279 if 100 were dead in I2), it sets 101 to the ORIGINAL value of 100.
1281 We can also run into a problem if I2 sets a register that I1
1282 uses and I1 gets directly substituted into I3 (not via I2). In that
1283 case, we would be getting the wrong value of I2DEST into I3, so we
1284 must reject the combination. This case occurs when I2 and I1 both
1285 feed into I3, rather than when I1 feeds into I2, which feeds into I3.
1286 If I1_NOT_IN_SRC is non-zero, it means that finding I1 in the source
1287 of a SET must prevent combination from occurring.
1289 Before doing the above check, we first try to expand a field assignment
1290 into a set of logical operations.
1292 If PI3_DEST_KILLED is non-zero, it is a pointer to a location in which
1293 we place a register that is both set and used within I3. If more than one
1294 such register is detected, we fail.
1296 Return 1 if the combination is valid, zero otherwise. */
1299 combinable_i3pat (i3, loc, i2dest, i1dest, i1_not_in_src, pi3dest_killed)
1305 rtx *pi3dest_killed;
1309 if (GET_CODE (x) == SET)
1311 rtx set = expand_field_assignment (x);
1312 rtx dest = SET_DEST (set);
1313 rtx src = SET_SRC (set);
1314 rtx inner_dest = dest;
1317 rtx inner_src = src;
1322 while (GET_CODE (inner_dest) == STRICT_LOW_PART
1323 || GET_CODE (inner_dest) == SUBREG
1324 || GET_CODE (inner_dest) == ZERO_EXTRACT)
1325 inner_dest = XEXP (inner_dest, 0);
1327 /* We probably don't need this any more now that LIMIT_RELOAD_CLASS
1330 while (GET_CODE (inner_src) == STRICT_LOW_PART
1331 || GET_CODE (inner_src) == SUBREG
1332 || GET_CODE (inner_src) == ZERO_EXTRACT)
1333 inner_src = XEXP (inner_src, 0);
1335 /* If it is better that two different modes keep two different pseudos,
1336 avoid combining them. This avoids producing the following pattern
1338 (set (subreg:SI (reg/v:QI 21) 0)
1339 (lshiftrt:SI (reg/v:SI 20)
1341 If that were made, reload could not handle the pair of
1342 reg 20/21, since it would try to get any GENERAL_REGS
1343 but some of them don't handle QImode. */
1345 if (rtx_equal_p (inner_src, i2dest)
1346 && GET_CODE (inner_dest) == REG
1347 && ! MODES_TIEABLE_P (GET_MODE (i2dest), GET_MODE (inner_dest)))
1351 /* Check for the case where I3 modifies its output, as
1353 if ((inner_dest != dest
1354 && (reg_overlap_mentioned_p (i2dest, inner_dest)
1355 || (i1dest && reg_overlap_mentioned_p (i1dest, inner_dest))))
1357 /* This is the same test done in can_combine_p except we can't test
1358 all_adjacent; we don't have to, since this instruction will stay
1359 in place, thus we are not considering increasing the lifetime of
1362 Also, if this insn sets a function argument, combining it with
1363 something that might need a spill could clobber a previous
1364 function argument; the all_adjacent test in can_combine_p also
1365 checks this; here, we do a more specific test for this case. */
1367 || (GET_CODE (inner_dest) == REG
1368 && REGNO (inner_dest) < FIRST_PSEUDO_REGISTER
1369 && (! HARD_REGNO_MODE_OK (REGNO (inner_dest),
1370 GET_MODE (inner_dest))))
1371 || (i1_not_in_src && reg_overlap_mentioned_p (i1dest, src)))
1374 /* If DEST is used in I3, it is being killed in this insn,
1375 so record that for later.
1376 Never add REG_DEAD notes for the FRAME_POINTER_REGNUM or the
1377 STACK_POINTER_REGNUM, since these are always considered to be
1378 live. Similarly for ARG_POINTER_REGNUM if it is fixed. */
1379 if (pi3dest_killed && GET_CODE (dest) == REG
1380 && reg_referenced_p (dest, PATTERN (i3))
1381 && REGNO (dest) != FRAME_POINTER_REGNUM
1382 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
1383 && REGNO (dest) != HARD_FRAME_POINTER_REGNUM
1385 #if ARG_POINTER_REGNUM != FRAME_POINTER_REGNUM
1386 && (REGNO (dest) != ARG_POINTER_REGNUM
1387 || ! fixed_regs [REGNO (dest)])
1389 && REGNO (dest) != STACK_POINTER_REGNUM)
1391 if (*pi3dest_killed)
1394 *pi3dest_killed = dest;
1398 else if (GET_CODE (x) == PARALLEL)
1402 for (i = 0; i < XVECLEN (x, 0); i++)
1403 if (! combinable_i3pat (i3, &XVECEXP (x, 0, i), i2dest, i1dest,
1404 i1_not_in_src, pi3dest_killed))
1411 /* Return 1 if X is an arithmetic expression that contains a multiplication
1412 and division. We don't count multiplications by powers of two here. */
1418 switch (GET_CODE (x))
1420 case MOD: case DIV: case UMOD: case UDIV:
1424 return ! (GET_CODE (XEXP (x, 1)) == CONST_INT
1425 && exact_log2 (INTVAL (XEXP (x, 1))) >= 0);
1427 switch (GET_RTX_CLASS (GET_CODE (x)))
1429 case 'c': case '<': case '2':
1430 return contains_muldiv (XEXP (x, 0))
1431 || contains_muldiv (XEXP (x, 1));
1434 return contains_muldiv (XEXP (x, 0));
1442 /* Determine whether INSN can be used in a combination. Return nonzero if
1443 not. This is used in try_combine to detect early some cases where we
1444 can't perform combinations. */
1447 cant_combine_insn_p (insn)
1453 /* If this isn't really an insn, we can't do anything.
1454 This can occur when flow deletes an insn that it has merged into an
1455 auto-increment address. */
1456 if (! INSN_P (insn))
1459 /* Never combine loads and stores involving hard regs. The register
1460 allocator can usually handle such reg-reg moves by tying. If we allow
1461 the combiner to make substitutions of hard regs, we risk aborting in
1462 reload on machines that have SMALL_REGISTER_CLASSES.
1463 As an exception, we allow combinations involving fixed regs; these are
1464 not available to the register allocator so there's no risk involved. */
1466 set = single_set (insn);
1469 src = SET_SRC (set);
1470 dest = SET_DEST (set);
1471 if (GET_CODE (src) == SUBREG)
1472 src = SUBREG_REG (src);
1473 if (GET_CODE (dest) == SUBREG)
1474 dest = SUBREG_REG (dest);
1475 if (REG_P (src) && REG_P (dest)
1476 && ((REGNO (src) < FIRST_PSEUDO_REGISTER
1477 && ! fixed_regs[REGNO (src)])
1478 || (REGNO (dest) < FIRST_PSEUDO_REGISTER
1479 && ! fixed_regs[REGNO (dest)])))
1485 /* Try to combine the insns I1 and I2 into I3.
1486 Here I1 and I2 appear earlier than I3.
1487 I1 can be zero; then we combine just I2 into I3.
1489 If we are combining three insns and the resulting insn is not recognized,
1490 try splitting it into two insns. If that happens, I2 and I3 are retained
1491 and I1 is pseudo-deleted by turning it into a NOTE. Otherwise, I1 and I2
1494 Return 0 if the combination does not work. Then nothing is changed.
1495 If we did the combination, return the insn at which combine should
1498 Set NEW_DIRECT_JUMP_P to a non-zero value if try_combine creates a
1499 new direct jump instruction. */
1502 try_combine (i3, i2, i1, new_direct_jump_p)
1504 int *new_direct_jump_p;
1506 /* New patterns for I3 and I2, respectively. */
1507 rtx newpat, newi2pat = 0;
1508 int substed_i2 = 0, substed_i1 = 0;
1509 /* Indicates need to preserve SET in I1 or I2 in I3 if it is not dead. */
1510 int added_sets_1, added_sets_2;
1511 /* Total number of SETs to put into I3. */
1513 /* Nonzero is I2's body now appears in I3. */
1515 /* INSN_CODEs for new I3, new I2, and user of condition code. */
1516 int insn_code_number, i2_code_number = 0, other_code_number = 0;
1517 /* Contains I3 if the destination of I3 is used in its source, which means
1518 that the old life of I3 is being killed. If that usage is placed into
1519 I2 and not in I3, a REG_DEAD note must be made. */
1520 rtx i3dest_killed = 0;
1521 /* SET_DEST and SET_SRC of I2 and I1. */
1522 rtx i2dest, i2src, i1dest = 0, i1src = 0;
1523 /* PATTERN (I2), or a copy of it in certain cases. */
1525 /* Indicates if I2DEST or I1DEST is in I2SRC or I1_SRC. */
1526 int i2dest_in_i2src = 0, i1dest_in_i1src = 0, i2dest_in_i1src = 0;
1527 int i1_feeds_i3 = 0;
1528 /* Notes that must be added to REG_NOTES in I3 and I2. */
1529 rtx new_i3_notes, new_i2_notes;
1530 /* Notes that we substituted I3 into I2 instead of the normal case. */
1531 int i3_subst_into_i2 = 0;
1532 /* Notes that I1, I2 or I3 is a MULT operation. */
1540 /* Exit early if one of the insns involved can't be used for
1542 if (cant_combine_insn_p (i3)
1543 || cant_combine_insn_p (i2)
1544 || (i1 && cant_combine_insn_p (i1))
1545 /* We also can't do anything if I3 has a
1546 REG_LIBCALL note since we don't want to disrupt the contiguity of a
1549 /* ??? This gives worse code, and appears to be unnecessary, since no
1550 pass after flow uses REG_LIBCALL/REG_RETVAL notes. */
1551 || find_reg_note (i3, REG_LIBCALL, NULL_RTX)
1557 undobuf.other_insn = 0;
1559 /* Reset the hard register usage information. */
1560 CLEAR_HARD_REG_SET (newpat_used_regs);
1562 /* If I1 and I2 both feed I3, they can be in any order. To simplify the
1563 code below, set I1 to be the earlier of the two insns. */
1564 if (i1 && INSN_CUID (i1) > INSN_CUID (i2))
1565 temp = i1, i1 = i2, i2 = temp;
1567 added_links_insn = 0;
1569 /* First check for one important special-case that the code below will
1570 not handle. Namely, the case where I1 is zero, I2 is a PARALLEL
1571 and I3 is a SET whose SET_SRC is a SET_DEST in I2. In that case,
1572 we may be able to replace that destination with the destination of I3.
1573 This occurs in the common code where we compute both a quotient and
1574 remainder into a structure, in which case we want to do the computation
1575 directly into the structure to avoid register-register copies.
1577 Note that this case handles both multiple sets in I2 and also
1578 cases where I2 has a number of CLOBBER or PARALLELs.
1580 We make very conservative checks below and only try to handle the
1581 most common cases of this. For example, we only handle the case
1582 where I2 and I3 are adjacent to avoid making difficult register
1585 if (i1 == 0 && GET_CODE (i3) == INSN && GET_CODE (PATTERN (i3)) == SET
1586 && GET_CODE (SET_SRC (PATTERN (i3))) == REG
1587 && REGNO (SET_SRC (PATTERN (i3))) >= FIRST_PSEUDO_REGISTER
1588 && find_reg_note (i3, REG_DEAD, SET_SRC (PATTERN (i3)))
1589 && GET_CODE (PATTERN (i2)) == PARALLEL
1590 && ! side_effects_p (SET_DEST (PATTERN (i3)))
1591 /* If the dest of I3 is a ZERO_EXTRACT or STRICT_LOW_PART, the code
1592 below would need to check what is inside (and reg_overlap_mentioned_p
1593 doesn't support those codes anyway). Don't allow those destinations;
1594 the resulting insn isn't likely to be recognized anyway. */
1595 && GET_CODE (SET_DEST (PATTERN (i3))) != ZERO_EXTRACT
1596 && GET_CODE (SET_DEST (PATTERN (i3))) != STRICT_LOW_PART
1597 && ! reg_overlap_mentioned_p (SET_SRC (PATTERN (i3)),
1598 SET_DEST (PATTERN (i3)))
1599 && next_real_insn (i2) == i3)
1601 rtx p2 = PATTERN (i2);
1603 /* Make sure that the destination of I3,
1604 which we are going to substitute into one output of I2,
1605 is not used within another output of I2. We must avoid making this:
1606 (parallel [(set (mem (reg 69)) ...)
1607 (set (reg 69) ...)])
1608 which is not well-defined as to order of actions.
1609 (Besides, reload can't handle output reloads for this.)
1611 The problem can also happen if the dest of I3 is a memory ref,
1612 if another dest in I2 is an indirect memory ref. */
1613 for (i = 0; i < XVECLEN (p2, 0); i++)
1614 if ((GET_CODE (XVECEXP (p2, 0, i)) == SET
1615 || GET_CODE (XVECEXP (p2, 0, i)) == CLOBBER)
1616 && reg_overlap_mentioned_p (SET_DEST (PATTERN (i3)),
1617 SET_DEST (XVECEXP (p2, 0, i))))
1620 if (i == XVECLEN (p2, 0))
1621 for (i = 0; i < XVECLEN (p2, 0); i++)
1622 if ((GET_CODE (XVECEXP (p2, 0, i)) == SET
1623 || GET_CODE (XVECEXP (p2, 0, i)) == CLOBBER)
1624 && SET_DEST (XVECEXP (p2, 0, i)) == SET_SRC (PATTERN (i3)))
1629 subst_low_cuid = INSN_CUID (i2);
1631 added_sets_2 = added_sets_1 = 0;
1632 i2dest = SET_SRC (PATTERN (i3));
1634 /* Replace the dest in I2 with our dest and make the resulting
1635 insn the new pattern for I3. Then skip to where we
1636 validate the pattern. Everything was set up above. */
1637 SUBST (SET_DEST (XVECEXP (p2, 0, i)),
1638 SET_DEST (PATTERN (i3)));
1641 i3_subst_into_i2 = 1;
1642 goto validate_replacement;
1646 /* If I2 is setting a double-word pseudo to a constant and I3 is setting
1647 one of those words to another constant, merge them by making a new
1650 && (temp = single_set (i2)) != 0
1651 && (GET_CODE (SET_SRC (temp)) == CONST_INT
1652 || GET_CODE (SET_SRC (temp)) == CONST_DOUBLE)
1653 && GET_CODE (SET_DEST (temp)) == REG
1654 && GET_MODE_CLASS (GET_MODE (SET_DEST (temp))) == MODE_INT
1655 && GET_MODE_SIZE (GET_MODE (SET_DEST (temp))) == 2 * UNITS_PER_WORD
1656 && GET_CODE (PATTERN (i3)) == SET
1657 && GET_CODE (SET_DEST (PATTERN (i3))) == SUBREG
1658 && SUBREG_REG (SET_DEST (PATTERN (i3))) == SET_DEST (temp)
1659 && GET_MODE_CLASS (GET_MODE (SET_DEST (PATTERN (i3)))) == MODE_INT
1660 && GET_MODE_SIZE (GET_MODE (SET_DEST (PATTERN (i3)))) == UNITS_PER_WORD
1661 && GET_CODE (SET_SRC (PATTERN (i3))) == CONST_INT)
1663 HOST_WIDE_INT lo, hi;
1665 if (GET_CODE (SET_SRC (temp)) == CONST_INT)
1666 lo = INTVAL (SET_SRC (temp)), hi = lo < 0 ? -1 : 0;
1669 lo = CONST_DOUBLE_LOW (SET_SRC (temp));
1670 hi = CONST_DOUBLE_HIGH (SET_SRC (temp));
1673 if (subreg_lowpart_p (SET_DEST (PATTERN (i3))))
1675 /* We don't handle the case of the target word being wider
1676 than a host wide int. */
1677 if (HOST_BITS_PER_WIDE_INT < BITS_PER_WORD)
1680 lo &= ~(UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD (1) - 1);
1681 lo |= (INTVAL (SET_SRC (PATTERN (i3)))
1682 & (UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD (1) - 1));
1684 else if (HOST_BITS_PER_WIDE_INT == BITS_PER_WORD)
1685 hi = INTVAL (SET_SRC (PATTERN (i3)));
1686 else if (HOST_BITS_PER_WIDE_INT >= 2 * BITS_PER_WORD)
1688 int sign = -(int) ((unsigned HOST_WIDE_INT) lo
1689 >> (HOST_BITS_PER_WIDE_INT - 1));
1691 lo &= ~ (UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD
1692 (UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD (1) - 1));
1693 lo |= (UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD
1694 (INTVAL (SET_SRC (PATTERN (i3)))));
1696 hi = lo < 0 ? -1 : 0;
1699 /* We don't handle the case of the higher word not fitting
1700 entirely in either hi or lo. */
1705 subst_low_cuid = INSN_CUID (i2);
1706 added_sets_2 = added_sets_1 = 0;
1707 i2dest = SET_DEST (temp);
1709 SUBST (SET_SRC (temp),
1710 immed_double_const (lo, hi, GET_MODE (SET_DEST (temp))));
1712 newpat = PATTERN (i2);
1713 goto validate_replacement;
1717 /* If we have no I1 and I2 looks like:
1718 (parallel [(set (reg:CC X) (compare:CC OP (const_int 0)))
1720 make up a dummy I1 that is
1723 (set (reg:CC X) (compare:CC Y (const_int 0)))
1725 (We can ignore any trailing CLOBBERs.)
1727 This undoes a previous combination and allows us to match a branch-and-
1730 if (i1 == 0 && GET_CODE (PATTERN (i2)) == PARALLEL
1731 && XVECLEN (PATTERN (i2), 0) >= 2
1732 && GET_CODE (XVECEXP (PATTERN (i2), 0, 0)) == SET
1733 && (GET_MODE_CLASS (GET_MODE (SET_DEST (XVECEXP (PATTERN (i2), 0, 0))))
1735 && GET_CODE (SET_SRC (XVECEXP (PATTERN (i2), 0, 0))) == COMPARE
1736 && XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 1) == const0_rtx
1737 && GET_CODE (XVECEXP (PATTERN (i2), 0, 1)) == SET
1738 && GET_CODE (SET_DEST (XVECEXP (PATTERN (i2), 0, 1))) == REG
1739 && rtx_equal_p (XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 0),
1740 SET_SRC (XVECEXP (PATTERN (i2), 0, 1))))
1742 for (i = XVECLEN (PATTERN (i2), 0) - 1; i >= 2; i--)
1743 if (GET_CODE (XVECEXP (PATTERN (i2), 0, i)) != CLOBBER)
1748 /* We make I1 with the same INSN_UID as I2. This gives it
1749 the same INSN_CUID for value tracking. Our fake I1 will
1750 never appear in the insn stream so giving it the same INSN_UID
1751 as I2 will not cause a problem. */
1753 subst_prev_insn = i1
1754 = gen_rtx_INSN (VOIDmode, INSN_UID (i2), NULL_RTX, i2,
1755 XVECEXP (PATTERN (i2), 0, 1), -1, NULL_RTX,
1758 SUBST (PATTERN (i2), XVECEXP (PATTERN (i2), 0, 0));
1759 SUBST (XEXP (SET_SRC (PATTERN (i2)), 0),
1760 SET_DEST (PATTERN (i1)));
1765 /* Verify that I2 and I1 are valid for combining. */
1766 if (! can_combine_p (i2, i3, i1, NULL_RTX, &i2dest, &i2src)
1767 || (i1 && ! can_combine_p (i1, i3, NULL_RTX, i2, &i1dest, &i1src)))
1773 /* Record whether I2DEST is used in I2SRC and similarly for the other
1774 cases. Knowing this will help in register status updating below. */
1775 i2dest_in_i2src = reg_overlap_mentioned_p (i2dest, i2src);
1776 i1dest_in_i1src = i1 && reg_overlap_mentioned_p (i1dest, i1src);
1777 i2dest_in_i1src = i1 && reg_overlap_mentioned_p (i2dest, i1src);
1779 /* See if I1 directly feeds into I3. It does if I1DEST is not used
1781 i1_feeds_i3 = i1 && ! reg_overlap_mentioned_p (i1dest, i2src);
1783 /* Ensure that I3's pattern can be the destination of combines. */
1784 if (! combinable_i3pat (i3, &PATTERN (i3), i2dest, i1dest,
1785 i1 && i2dest_in_i1src && i1_feeds_i3,
1792 /* See if any of the insns is a MULT operation. Unless one is, we will
1793 reject a combination that is, since it must be slower. Be conservative
1795 if (GET_CODE (i2src) == MULT
1796 || (i1 != 0 && GET_CODE (i1src) == MULT)
1797 || (GET_CODE (PATTERN (i3)) == SET
1798 && GET_CODE (SET_SRC (PATTERN (i3))) == MULT))
1801 /* If I3 has an inc, then give up if I1 or I2 uses the reg that is inc'd.
1802 We used to do this EXCEPT in one case: I3 has a post-inc in an
1803 output operand. However, that exception can give rise to insns like
1805 which is a famous insn on the PDP-11 where the value of r3 used as the
1806 source was model-dependent. Avoid this sort of thing. */
1809 if (!(GET_CODE (PATTERN (i3)) == SET
1810 && GET_CODE (SET_SRC (PATTERN (i3))) == REG
1811 && GET_CODE (SET_DEST (PATTERN (i3))) == MEM
1812 && (GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_INC
1813 || GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_DEC)))
1814 /* It's not the exception. */
1817 for (link = REG_NOTES (i3); link; link = XEXP (link, 1))
1818 if (REG_NOTE_KIND (link) == REG_INC
1819 && (reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i2))
1821 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i1)))))
1828 /* See if the SETs in I1 or I2 need to be kept around in the merged
1829 instruction: whenever the value set there is still needed past I3.
1830 For the SETs in I2, this is easy: we see if I2DEST dies or is set in I3.
1832 For the SET in I1, we have two cases: If I1 and I2 independently
1833 feed into I3, the set in I1 needs to be kept around if I1DEST dies
1834 or is set in I3. Otherwise (if I1 feeds I2 which feeds I3), the set
1835 in I1 needs to be kept around unless I1DEST dies or is set in either
1836 I2 or I3. We can distinguish these cases by seeing if I2SRC mentions
1837 I1DEST. If so, we know I1 feeds into I2. */
1839 added_sets_2 = ! dead_or_set_p (i3, i2dest);
1842 = i1 && ! (i1_feeds_i3 ? dead_or_set_p (i3, i1dest)
1843 : (dead_or_set_p (i3, i1dest) || dead_or_set_p (i2, i1dest)));
1845 /* If the set in I2 needs to be kept around, we must make a copy of
1846 PATTERN (I2), so that when we substitute I1SRC for I1DEST in
1847 PATTERN (I2), we are only substituting for the original I1DEST, not into
1848 an already-substituted copy. This also prevents making self-referential
1849 rtx. If I2 is a PARALLEL, we just need the piece that assigns I2SRC to
1852 i2pat = (GET_CODE (PATTERN (i2)) == PARALLEL
1853 ? gen_rtx_SET (VOIDmode, i2dest, i2src)
1857 i2pat = copy_rtx (i2pat);
1861 /* Substitute in the latest insn for the regs set by the earlier ones. */
1863 maxreg = max_reg_num ();
1867 /* It is possible that the source of I2 or I1 may be performing an
1868 unneeded operation, such as a ZERO_EXTEND of something that is known
1869 to have the high part zero. Handle that case by letting subst look at
1870 the innermost one of them.
1872 Another way to do this would be to have a function that tries to
1873 simplify a single insn instead of merging two or more insns. We don't
1874 do this because of the potential of infinite loops and because
1875 of the potential extra memory required. However, doing it the way
1876 we are is a bit of a kludge and doesn't catch all cases.
1878 But only do this if -fexpensive-optimizations since it slows things down
1879 and doesn't usually win. */
1881 if (flag_expensive_optimizations)
1883 /* Pass pc_rtx so no substitutions are done, just simplifications.
1884 The cases that we are interested in here do not involve the few
1885 cases were is_replaced is checked. */
1888 subst_low_cuid = INSN_CUID (i1);
1889 i1src = subst (i1src, pc_rtx, pc_rtx, 0, 0);
1893 subst_low_cuid = INSN_CUID (i2);
1894 i2src = subst (i2src, pc_rtx, pc_rtx, 0, 0);
1899 /* Many machines that don't use CC0 have insns that can both perform an
1900 arithmetic operation and set the condition code. These operations will
1901 be represented as a PARALLEL with the first element of the vector
1902 being a COMPARE of an arithmetic operation with the constant zero.
1903 The second element of the vector will set some pseudo to the result
1904 of the same arithmetic operation. If we simplify the COMPARE, we won't
1905 match such a pattern and so will generate an extra insn. Here we test
1906 for this case, where both the comparison and the operation result are
1907 needed, and make the PARALLEL by just replacing I2DEST in I3SRC with
1908 I2SRC. Later we will make the PARALLEL that contains I2. */
1910 if (i1 == 0 && added_sets_2 && GET_CODE (PATTERN (i3)) == SET
1911 && GET_CODE (SET_SRC (PATTERN (i3))) == COMPARE
1912 && XEXP (SET_SRC (PATTERN (i3)), 1) == const0_rtx
1913 && rtx_equal_p (XEXP (SET_SRC (PATTERN (i3)), 0), i2dest))
1915 #ifdef EXTRA_CC_MODES
1917 enum machine_mode compare_mode;
1920 newpat = PATTERN (i3);
1921 SUBST (XEXP (SET_SRC (newpat), 0), i2src);
1925 #ifdef EXTRA_CC_MODES
1926 /* See if a COMPARE with the operand we substituted in should be done
1927 with the mode that is currently being used. If not, do the same
1928 processing we do in `subst' for a SET; namely, if the destination
1929 is used only once, try to replace it with a register of the proper
1930 mode and also replace the COMPARE. */
1931 if (undobuf.other_insn == 0
1932 && (cc_use = find_single_use (SET_DEST (newpat), i3,
1933 &undobuf.other_insn))
1934 && ((compare_mode = SELECT_CC_MODE (GET_CODE (*cc_use),
1936 != GET_MODE (SET_DEST (newpat))))
1938 unsigned int regno = REGNO (SET_DEST (newpat));
1939 rtx new_dest = gen_rtx_REG (compare_mode, regno);
1941 if (regno < FIRST_PSEUDO_REGISTER
1942 || (REG_N_SETS (regno) == 1 && ! added_sets_2
1943 && ! REG_USERVAR_P (SET_DEST (newpat))))
1945 if (regno >= FIRST_PSEUDO_REGISTER)
1946 SUBST (regno_reg_rtx[regno], new_dest);
1948 SUBST (SET_DEST (newpat), new_dest);
1949 SUBST (XEXP (*cc_use, 0), new_dest);
1950 SUBST (SET_SRC (newpat),
1951 gen_rtx_COMPARE (compare_mode, i2src, const0_rtx));
1954 undobuf.other_insn = 0;
1961 n_occurrences = 0; /* `subst' counts here */
1963 /* If I1 feeds into I2 (not into I3) and I1DEST is in I1SRC, we
1964 need to make a unique copy of I2SRC each time we substitute it
1965 to avoid self-referential rtl. */
1967 subst_low_cuid = INSN_CUID (i2);
1968 newpat = subst (PATTERN (i3), i2dest, i2src, 0,
1969 ! i1_feeds_i3 && i1dest_in_i1src);
1972 /* Record whether i2's body now appears within i3's body. */
1973 i2_is_used = n_occurrences;
1976 /* If we already got a failure, don't try to do more. Otherwise,
1977 try to substitute in I1 if we have it. */
1979 if (i1 && GET_CODE (newpat) != CLOBBER)
1981 /* Before we can do this substitution, we must redo the test done
1982 above (see detailed comments there) that ensures that I1DEST
1983 isn't mentioned in any SETs in NEWPAT that are field assignments. */
1985 if (! combinable_i3pat (NULL_RTX, &newpat, i1dest, NULL_RTX,
1993 subst_low_cuid = INSN_CUID (i1);
1994 newpat = subst (newpat, i1dest, i1src, 0, 0);
1998 /* Fail if an autoincrement side-effect has been duplicated. Be careful
1999 to count all the ways that I2SRC and I1SRC can be used. */
2000 if ((FIND_REG_INC_NOTE (i2, NULL_RTX) != 0
2001 && i2_is_used + added_sets_2 > 1)
2002 || (i1 != 0 && FIND_REG_INC_NOTE (i1, NULL_RTX) != 0
2003 && (n_occurrences + added_sets_1 + (added_sets_2 && ! i1_feeds_i3)
2005 /* Fail if we tried to make a new register (we used to abort, but there's
2006 really no reason to). */
2007 || max_reg_num () != maxreg
2008 /* Fail if we couldn't do something and have a CLOBBER. */
2009 || GET_CODE (newpat) == CLOBBER
2010 /* Fail if this new pattern is a MULT and we didn't have one before
2011 at the outer level. */
2012 || (GET_CODE (newpat) == SET && GET_CODE (SET_SRC (newpat)) == MULT
2019 /* If the actions of the earlier insns must be kept
2020 in addition to substituting them into the latest one,
2021 we must make a new PARALLEL for the latest insn
2022 to hold additional the SETs. */
2024 if (added_sets_1 || added_sets_2)
2028 if (GET_CODE (newpat) == PARALLEL)
2030 rtvec old = XVEC (newpat, 0);
2031 total_sets = XVECLEN (newpat, 0) + added_sets_1 + added_sets_2;
2032 newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (total_sets));
2033 memcpy (XVEC (newpat, 0)->elem, &old->elem[0],
2034 sizeof (old->elem[0]) * old->num_elem);
2039 total_sets = 1 + added_sets_1 + added_sets_2;
2040 newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (total_sets));
2041 XVECEXP (newpat, 0, 0) = old;
2045 XVECEXP (newpat, 0, --total_sets)
2046 = (GET_CODE (PATTERN (i1)) == PARALLEL
2047 ? gen_rtx_SET (VOIDmode, i1dest, i1src) : PATTERN (i1));
2051 /* If there is no I1, use I2's body as is. We used to also not do
2052 the subst call below if I2 was substituted into I3,
2053 but that could lose a simplification. */
2055 XVECEXP (newpat, 0, --total_sets) = i2pat;
2057 /* See comment where i2pat is assigned. */
2058 XVECEXP (newpat, 0, --total_sets)
2059 = subst (i2pat, i1dest, i1src, 0, 0);
2063 /* We come here when we are replacing a destination in I2 with the
2064 destination of I3. */
2065 validate_replacement:
2067 /* Note which hard regs this insn has as inputs. */
2068 mark_used_regs_combine (newpat);
2070 /* Is the result of combination a valid instruction? */
2071 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2073 /* If the result isn't valid, see if it is a PARALLEL of two SETs where
2074 the second SET's destination is a register that is unused. In that case,
2075 we just need the first SET. This can occur when simplifying a divmod
2076 insn. We *must* test for this case here because the code below that
2077 splits two independent SETs doesn't handle this case correctly when it
2078 updates the register status. Also check the case where the first
2079 SET's destination is unused. That would not cause incorrect code, but
2080 does cause an unneeded insn to remain. */
2082 if (insn_code_number < 0 && GET_CODE (newpat) == PARALLEL
2083 && XVECLEN (newpat, 0) == 2
2084 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
2085 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
2086 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) == REG
2087 && find_reg_note (i3, REG_UNUSED, SET_DEST (XVECEXP (newpat, 0, 1)))
2088 && ! side_effects_p (SET_SRC (XVECEXP (newpat, 0, 1)))
2089 && asm_noperands (newpat) < 0)
2091 newpat = XVECEXP (newpat, 0, 0);
2092 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2095 else if (insn_code_number < 0 && GET_CODE (newpat) == PARALLEL
2096 && XVECLEN (newpat, 0) == 2
2097 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
2098 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
2099 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) == REG
2100 && find_reg_note (i3, REG_UNUSED, SET_DEST (XVECEXP (newpat, 0, 0)))
2101 && ! side_effects_p (SET_SRC (XVECEXP (newpat, 0, 0)))
2102 && asm_noperands (newpat) < 0)
2104 newpat = XVECEXP (newpat, 0, 1);
2105 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2108 /* If we were combining three insns and the result is a simple SET
2109 with no ASM_OPERANDS that wasn't recognized, try to split it into two
2110 insns. There are two ways to do this. It can be split using a
2111 machine-specific method (like when you have an addition of a large
2112 constant) or by combine in the function find_split_point. */
2114 if (i1 && insn_code_number < 0 && GET_CODE (newpat) == SET
2115 && asm_noperands (newpat) < 0)
2117 rtx m_split, *split;
2118 rtx ni2dest = i2dest;
2120 /* See if the MD file can split NEWPAT. If it can't, see if letting it
2121 use I2DEST as a scratch register will help. In the latter case,
2122 convert I2DEST to the mode of the source of NEWPAT if we can. */
2124 m_split = split_insns (newpat, i3);
2126 /* We can only use I2DEST as a scratch reg if it doesn't overlap any
2127 inputs of NEWPAT. */
2129 /* ??? If I2DEST is not safe, and I1DEST exists, then it would be
2130 possible to try that as a scratch reg. This would require adding
2131 more code to make it work though. */
2133 if (m_split == 0 && ! reg_overlap_mentioned_p (ni2dest, newpat))
2135 /* If I2DEST is a hard register or the only use of a pseudo,
2136 we can change its mode. */
2137 if (GET_MODE (SET_DEST (newpat)) != GET_MODE (i2dest)
2138 && GET_MODE (SET_DEST (newpat)) != VOIDmode
2139 && GET_CODE (i2dest) == REG
2140 && (REGNO (i2dest) < FIRST_PSEUDO_REGISTER
2141 || (REG_N_SETS (REGNO (i2dest)) == 1 && ! added_sets_2
2142 && ! REG_USERVAR_P (i2dest))))
2143 ni2dest = gen_rtx_REG (GET_MODE (SET_DEST (newpat)),
2146 m_split = split_insns (gen_rtx_PARALLEL
2148 gen_rtvec (2, newpat,
2149 gen_rtx_CLOBBER (VOIDmode,
2152 /* If the split with the mode-changed register didn't work, try
2153 the original register. */
2154 if (! m_split && ni2dest != i2dest)
2157 m_split = split_insns (gen_rtx_PARALLEL
2159 gen_rtvec (2, newpat,
2160 gen_rtx_CLOBBER (VOIDmode,
2166 /* If we've split a jump pattern, we'll wind up with a sequence even
2167 with one instruction. We can handle that below, so extract it. */
2168 if (m_split && GET_CODE (m_split) == SEQUENCE
2169 && XVECLEN (m_split, 0) == 1)
2170 m_split = PATTERN (XVECEXP (m_split, 0, 0));
2172 if (m_split && GET_CODE (m_split) != SEQUENCE)
2174 insn_code_number = recog_for_combine (&m_split, i3, &new_i3_notes);
2175 if (insn_code_number >= 0)
2178 else if (m_split && GET_CODE (m_split) == SEQUENCE
2179 && XVECLEN (m_split, 0) == 2
2180 && (next_real_insn (i2) == i3
2181 || ! use_crosses_set_p (PATTERN (XVECEXP (m_split, 0, 0)),
2185 rtx newi3pat = PATTERN (XVECEXP (m_split, 0, 1));
2186 newi2pat = PATTERN (XVECEXP (m_split, 0, 0));
2188 i3set = single_set (XVECEXP (m_split, 0, 1));
2189 i2set = single_set (XVECEXP (m_split, 0, 0));
2191 /* In case we changed the mode of I2DEST, replace it in the
2192 pseudo-register table here. We can't do it above in case this
2193 code doesn't get executed and we do a split the other way. */
2195 if (REGNO (i2dest) >= FIRST_PSEUDO_REGISTER)
2196 SUBST (regno_reg_rtx[REGNO (i2dest)], ni2dest);
2198 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
2200 /* If I2 or I3 has multiple SETs, we won't know how to track
2201 register status, so don't use these insns. If I2's destination
2202 is used between I2 and I3, we also can't use these insns. */
2204 if (i2_code_number >= 0 && i2set && i3set
2205 && (next_real_insn (i2) == i3
2206 || ! reg_used_between_p (SET_DEST (i2set), i2, i3)))
2207 insn_code_number = recog_for_combine (&newi3pat, i3,
2209 if (insn_code_number >= 0)
2212 /* It is possible that both insns now set the destination of I3.
2213 If so, we must show an extra use of it. */
2215 if (insn_code_number >= 0)
2217 rtx new_i3_dest = SET_DEST (i3set);
2218 rtx new_i2_dest = SET_DEST (i2set);
2220 while (GET_CODE (new_i3_dest) == ZERO_EXTRACT
2221 || GET_CODE (new_i3_dest) == STRICT_LOW_PART
2222 || GET_CODE (new_i3_dest) == SUBREG)
2223 new_i3_dest = XEXP (new_i3_dest, 0);
2225 while (GET_CODE (new_i2_dest) == ZERO_EXTRACT
2226 || GET_CODE (new_i2_dest) == STRICT_LOW_PART
2227 || GET_CODE (new_i2_dest) == SUBREG)
2228 new_i2_dest = XEXP (new_i2_dest, 0);
2230 if (GET_CODE (new_i3_dest) == REG
2231 && GET_CODE (new_i2_dest) == REG
2232 && REGNO (new_i3_dest) == REGNO (new_i2_dest))
2233 REG_N_SETS (REGNO (new_i2_dest))++;
2237 /* If we can split it and use I2DEST, go ahead and see if that
2238 helps things be recognized. Verify that none of the registers
2239 are set between I2 and I3. */
2240 if (insn_code_number < 0 && (split = find_split_point (&newpat, i3)) != 0
2242 && GET_CODE (i2dest) == REG
2244 /* We need I2DEST in the proper mode. If it is a hard register
2245 or the only use of a pseudo, we can change its mode. */
2246 && (GET_MODE (*split) == GET_MODE (i2dest)
2247 || GET_MODE (*split) == VOIDmode
2248 || REGNO (i2dest) < FIRST_PSEUDO_REGISTER
2249 || (REG_N_SETS (REGNO (i2dest)) == 1 && ! added_sets_2
2250 && ! REG_USERVAR_P (i2dest)))
2251 && (next_real_insn (i2) == i3
2252 || ! use_crosses_set_p (*split, INSN_CUID (i2)))
2253 /* We can't overwrite I2DEST if its value is still used by
2255 && ! reg_referenced_p (i2dest, newpat))
2257 rtx newdest = i2dest;
2258 enum rtx_code split_code = GET_CODE (*split);
2259 enum machine_mode split_mode = GET_MODE (*split);
2261 /* Get NEWDEST as a register in the proper mode. We have already
2262 validated that we can do this. */
2263 if (GET_MODE (i2dest) != split_mode && split_mode != VOIDmode)
2265 newdest = gen_rtx_REG (split_mode, REGNO (i2dest));
2267 if (REGNO (i2dest) >= FIRST_PSEUDO_REGISTER)
2268 SUBST (regno_reg_rtx[REGNO (i2dest)], newdest);
2271 /* If *SPLIT is a (mult FOO (const_int pow2)), convert it to
2272 an ASHIFT. This can occur if it was inside a PLUS and hence
2273 appeared to be a memory address. This is a kludge. */
2274 if (split_code == MULT
2275 && GET_CODE (XEXP (*split, 1)) == CONST_INT
2276 && INTVAL (XEXP (*split, 1)) > 0
2277 && (i = exact_log2 (INTVAL (XEXP (*split, 1)))) >= 0)
2279 SUBST (*split, gen_rtx_ASHIFT (split_mode,
2280 XEXP (*split, 0), GEN_INT (i)));
2281 /* Update split_code because we may not have a multiply
2283 split_code = GET_CODE (*split);
2286 #ifdef INSN_SCHEDULING
2287 /* If *SPLIT is a paradoxical SUBREG, when we split it, it should
2288 be written as a ZERO_EXTEND. */
2289 if (split_code == SUBREG && GET_CODE (SUBREG_REG (*split)) == MEM)
2290 SUBST (*split, gen_rtx_ZERO_EXTEND (split_mode,
2291 SUBREG_REG (*split)));
2294 newi2pat = gen_rtx_SET (VOIDmode, newdest, *split);
2295 SUBST (*split, newdest);
2296 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
2298 /* If the split point was a MULT and we didn't have one before,
2299 don't use one now. */
2300 if (i2_code_number >= 0 && ! (split_code == MULT && ! have_mult))
2301 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2305 /* Check for a case where we loaded from memory in a narrow mode and
2306 then sign extended it, but we need both registers. In that case,
2307 we have a PARALLEL with both loads from the same memory location.
2308 We can split this into a load from memory followed by a register-register
2309 copy. This saves at least one insn, more if register allocation can
2312 We cannot do this if the destination of the second assignment is
2313 a register that we have already assumed is zero-extended. Similarly
2314 for a SUBREG of such a register. */
2316 else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0
2317 && GET_CODE (newpat) == PARALLEL
2318 && XVECLEN (newpat, 0) == 2
2319 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
2320 && GET_CODE (SET_SRC (XVECEXP (newpat, 0, 0))) == SIGN_EXTEND
2321 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
2322 && rtx_equal_p (SET_SRC (XVECEXP (newpat, 0, 1)),
2323 XEXP (SET_SRC (XVECEXP (newpat, 0, 0)), 0))
2324 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)),
2326 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
2327 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
2328 && ! (temp = SET_DEST (XVECEXP (newpat, 0, 1)),
2329 (GET_CODE (temp) == REG
2330 && reg_nonzero_bits[REGNO (temp)] != 0
2331 && GET_MODE_BITSIZE (GET_MODE (temp)) < BITS_PER_WORD
2332 && GET_MODE_BITSIZE (GET_MODE (temp)) < HOST_BITS_PER_INT
2333 && (reg_nonzero_bits[REGNO (temp)]
2334 != GET_MODE_MASK (word_mode))))
2335 && ! (GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) == SUBREG
2336 && (temp = SUBREG_REG (SET_DEST (XVECEXP (newpat, 0, 1))),
2337 (GET_CODE (temp) == REG
2338 && reg_nonzero_bits[REGNO (temp)] != 0
2339 && GET_MODE_BITSIZE (GET_MODE (temp)) < BITS_PER_WORD
2340 && GET_MODE_BITSIZE (GET_MODE (temp)) < HOST_BITS_PER_INT
2341 && (reg_nonzero_bits[REGNO (temp)]
2342 != GET_MODE_MASK (word_mode)))))
2343 && ! reg_overlap_mentioned_p (SET_DEST (XVECEXP (newpat, 0, 1)),
2344 SET_SRC (XVECEXP (newpat, 0, 1)))
2345 && ! find_reg_note (i3, REG_UNUSED,
2346 SET_DEST (XVECEXP (newpat, 0, 0))))
2350 newi2pat = XVECEXP (newpat, 0, 0);
2351 ni2dest = SET_DEST (XVECEXP (newpat, 0, 0));
2352 newpat = XVECEXP (newpat, 0, 1);
2353 SUBST (SET_SRC (newpat),
2354 gen_lowpart_for_combine (GET_MODE (SET_SRC (newpat)), ni2dest));
2355 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
2357 if (i2_code_number >= 0)
2358 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2360 if (insn_code_number >= 0)
2365 /* If we will be able to accept this, we have made a change to the
2366 destination of I3. This can invalidate a LOG_LINKS pointing
2367 to I3. No other part of combine.c makes such a transformation.
2369 The new I3 will have a destination that was previously the
2370 destination of I1 or I2 and which was used in i2 or I3. Call
2371 distribute_links to make a LOG_LINK from the next use of
2372 that destination. */
2374 PATTERN (i3) = newpat;
2375 distribute_links (gen_rtx_INSN_LIST (VOIDmode, i3, NULL_RTX));
2377 /* I3 now uses what used to be its destination and which is
2378 now I2's destination. That means we need a LOG_LINK from
2379 I3 to I2. But we used to have one, so we still will.
2381 However, some later insn might be using I2's dest and have
2382 a LOG_LINK pointing at I3. We must remove this link.
2383 The simplest way to remove the link is to point it at I1,
2384 which we know will be a NOTE. */
2386 for (insn = NEXT_INSN (i3);
2387 insn && (this_basic_block == n_basic_blocks - 1
2388 || insn != BLOCK_HEAD (this_basic_block + 1));
2389 insn = NEXT_INSN (insn))
2391 if (INSN_P (insn) && reg_referenced_p (ni2dest, PATTERN (insn)))
2393 for (link = LOG_LINKS (insn); link;
2394 link = XEXP (link, 1))
2395 if (XEXP (link, 0) == i3)
2396 XEXP (link, 0) = i1;
2404 /* Similarly, check for a case where we have a PARALLEL of two independent
2405 SETs but we started with three insns. In this case, we can do the sets
2406 as two separate insns. This case occurs when some SET allows two
2407 other insns to combine, but the destination of that SET is still live. */
2409 else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0
2410 && GET_CODE (newpat) == PARALLEL
2411 && XVECLEN (newpat, 0) == 2
2412 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
2413 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != ZERO_EXTRACT
2414 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != STRICT_LOW_PART
2415 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
2416 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
2417 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
2418 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)),
2420 /* Don't pass sets with (USE (MEM ...)) dests to the following. */
2421 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != USE
2422 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != USE
2423 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 1)),
2424 XVECEXP (newpat, 0, 0))
2425 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 0)),
2426 XVECEXP (newpat, 0, 1))
2427 && ! (contains_muldiv (SET_SRC (XVECEXP (newpat, 0, 0)))
2428 && contains_muldiv (SET_SRC (XVECEXP (newpat, 0, 1)))))
2430 /* Normally, it doesn't matter which of the two is done first,
2431 but it does if one references cc0. In that case, it has to
2434 if (reg_referenced_p (cc0_rtx, XVECEXP (newpat, 0, 0)))
2436 newi2pat = XVECEXP (newpat, 0, 0);
2437 newpat = XVECEXP (newpat, 0, 1);
2442 newi2pat = XVECEXP (newpat, 0, 1);
2443 newpat = XVECEXP (newpat, 0, 0);
2446 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
2448 if (i2_code_number >= 0)
2449 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2452 /* If it still isn't recognized, fail and change things back the way they
2454 if ((insn_code_number < 0
2455 /* Is the result a reasonable ASM_OPERANDS? */
2456 && (! check_asm_operands (newpat) || added_sets_1 || added_sets_2)))
2462 /* If we had to change another insn, make sure it is valid also. */
2463 if (undobuf.other_insn)
2465 rtx other_pat = PATTERN (undobuf.other_insn);
2466 rtx new_other_notes;
2469 CLEAR_HARD_REG_SET (newpat_used_regs);
2471 other_code_number = recog_for_combine (&other_pat, undobuf.other_insn,
2474 if (other_code_number < 0 && ! check_asm_operands (other_pat))
2480 PATTERN (undobuf.other_insn) = other_pat;
2482 /* If any of the notes in OTHER_INSN were REG_UNUSED, ensure that they
2483 are still valid. Then add any non-duplicate notes added by
2484 recog_for_combine. */
2485 for (note = REG_NOTES (undobuf.other_insn); note; note = next)
2487 next = XEXP (note, 1);
2489 if (REG_NOTE_KIND (note) == REG_UNUSED
2490 && ! reg_set_p (XEXP (note, 0), PATTERN (undobuf.other_insn)))
2492 if (GET_CODE (XEXP (note, 0)) == REG)
2493 REG_N_DEATHS (REGNO (XEXP (note, 0)))--;
2495 remove_note (undobuf.other_insn, note);
2499 for (note = new_other_notes; note; note = XEXP (note, 1))
2500 if (GET_CODE (XEXP (note, 0)) == REG)
2501 REG_N_DEATHS (REGNO (XEXP (note, 0)))++;
2503 distribute_notes (new_other_notes, undobuf.other_insn,
2504 undobuf.other_insn, NULL_RTX, NULL_RTX, NULL_RTX);
2507 /* If I2 is the setter CC0 and I3 is the user CC0 then check whether
2508 they are adjacent to each other or not. */
2510 rtx p = prev_nonnote_insn (i3);
2511 if (p && p != i2 && GET_CODE (p) == INSN && newi2pat
2512 && sets_cc0_p (newi2pat))
2520 /* We now know that we can do this combination. Merge the insns and
2521 update the status of registers and LOG_LINKS. */
2524 rtx i3notes, i2notes, i1notes = 0;
2525 rtx i3links, i2links, i1links = 0;
2528 /* Compute which registers we expect to eliminate. newi2pat may be setting
2529 either i3dest or i2dest, so we must check it. Also, i1dest may be the
2530 same as i3dest, in which case newi2pat may be setting i1dest. */
2531 rtx elim_i2 = ((newi2pat && reg_set_p (i2dest, newi2pat))
2532 || i2dest_in_i2src || i2dest_in_i1src
2534 rtx elim_i1 = (i1 == 0 || i1dest_in_i1src
2535 || (newi2pat && reg_set_p (i1dest, newi2pat))
2538 /* Get the old REG_NOTES and LOG_LINKS from all our insns and
2540 i3notes = REG_NOTES (i3), i3links = LOG_LINKS (i3);
2541 i2notes = REG_NOTES (i2), i2links = LOG_LINKS (i2);
2543 i1notes = REG_NOTES (i1), i1links = LOG_LINKS (i1);
2545 /* Ensure that we do not have something that should not be shared but
2546 occurs multiple times in the new insns. Check this by first
2547 resetting all the `used' flags and then copying anything is shared. */
2549 reset_used_flags (i3notes);
2550 reset_used_flags (i2notes);
2551 reset_used_flags (i1notes);
2552 reset_used_flags (newpat);
2553 reset_used_flags (newi2pat);
2554 if (undobuf.other_insn)
2555 reset_used_flags (PATTERN (undobuf.other_insn));
2557 i3notes = copy_rtx_if_shared (i3notes);
2558 i2notes = copy_rtx_if_shared (i2notes);
2559 i1notes = copy_rtx_if_shared (i1notes);
2560 newpat = copy_rtx_if_shared (newpat);
2561 newi2pat = copy_rtx_if_shared (newi2pat);
2562 if (undobuf.other_insn)
2563 reset_used_flags (PATTERN (undobuf.other_insn));
2565 INSN_CODE (i3) = insn_code_number;
2566 PATTERN (i3) = newpat;
2568 if (GET_CODE (i3) == CALL_INSN && CALL_INSN_FUNCTION_USAGE (i3))
2570 rtx call_usage = CALL_INSN_FUNCTION_USAGE (i3);
2572 reset_used_flags (call_usage);
2573 call_usage = copy_rtx (call_usage);
2576 replace_rtx (call_usage, i2dest, i2src);
2579 replace_rtx (call_usage, i1dest, i1src);
2581 CALL_INSN_FUNCTION_USAGE (i3) = call_usage;
2584 if (undobuf.other_insn)
2585 INSN_CODE (undobuf.other_insn) = other_code_number;
2587 /* We had one special case above where I2 had more than one set and
2588 we replaced a destination of one of those sets with the destination
2589 of I3. In that case, we have to update LOG_LINKS of insns later
2590 in this basic block. Note that this (expensive) case is rare.
2592 Also, in this case, we must pretend that all REG_NOTEs for I2
2593 actually came from I3, so that REG_UNUSED notes from I2 will be
2594 properly handled. */
2596 if (i3_subst_into_i2)
2598 for (i = 0; i < XVECLEN (PATTERN (i2), 0); i++)
2599 if (GET_CODE (XVECEXP (PATTERN (i2), 0, i)) != USE
2600 && GET_CODE (SET_DEST (XVECEXP (PATTERN (i2), 0, i))) == REG
2601 && SET_DEST (XVECEXP (PATTERN (i2), 0, i)) != i2dest
2602 && ! find_reg_note (i2, REG_UNUSED,
2603 SET_DEST (XVECEXP (PATTERN (i2), 0, i))))
2604 for (temp = NEXT_INSN (i2);
2605 temp && (this_basic_block == n_basic_blocks - 1
2606 || BLOCK_HEAD (this_basic_block) != temp);
2607 temp = NEXT_INSN (temp))
2608 if (temp != i3 && INSN_P (temp))
2609 for (link = LOG_LINKS (temp); link; link = XEXP (link, 1))
2610 if (XEXP (link, 0) == i2)
2611 XEXP (link, 0) = i3;
2616 while (XEXP (link, 1))
2617 link = XEXP (link, 1);
2618 XEXP (link, 1) = i2notes;
2632 INSN_CODE (i2) = i2_code_number;
2633 PATTERN (i2) = newi2pat;
2637 PUT_CODE (i2, NOTE);
2638 NOTE_LINE_NUMBER (i2) = NOTE_INSN_DELETED;
2639 NOTE_SOURCE_FILE (i2) = 0;
2646 PUT_CODE (i1, NOTE);
2647 NOTE_LINE_NUMBER (i1) = NOTE_INSN_DELETED;
2648 NOTE_SOURCE_FILE (i1) = 0;
2651 /* Get death notes for everything that is now used in either I3 or
2652 I2 and used to die in a previous insn. If we built two new
2653 patterns, move from I1 to I2 then I2 to I3 so that we get the
2654 proper movement on registers that I2 modifies. */
2658 move_deaths (newi2pat, NULL_RTX, INSN_CUID (i1), i2, &midnotes);
2659 move_deaths (newpat, newi2pat, INSN_CUID (i1), i3, &midnotes);
2662 move_deaths (newpat, NULL_RTX, i1 ? INSN_CUID (i1) : INSN_CUID (i2),
2665 /* Distribute all the LOG_LINKS and REG_NOTES from I1, I2, and I3. */
2667 distribute_notes (i3notes, i3, i3, newi2pat ? i2 : NULL_RTX,
2670 distribute_notes (i2notes, i2, i3, newi2pat ? i2 : NULL_RTX,
2673 distribute_notes (i1notes, i1, i3, newi2pat ? i2 : NULL_RTX,
2676 distribute_notes (midnotes, NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
2679 /* Distribute any notes added to I2 or I3 by recog_for_combine. We
2680 know these are REG_UNUSED and want them to go to the desired insn,
2681 so we always pass it as i3. We have not counted the notes in
2682 reg_n_deaths yet, so we need to do so now. */
2684 if (newi2pat && new_i2_notes)
2686 for (temp = new_i2_notes; temp; temp = XEXP (temp, 1))
2687 if (GET_CODE (XEXP (temp, 0)) == REG)
2688 REG_N_DEATHS (REGNO (XEXP (temp, 0)))++;
2690 distribute_notes (new_i2_notes, i2, i2, NULL_RTX, NULL_RTX, NULL_RTX);
2695 for (temp = new_i3_notes; temp; temp = XEXP (temp, 1))
2696 if (GET_CODE (XEXP (temp, 0)) == REG)
2697 REG_N_DEATHS (REGNO (XEXP (temp, 0)))++;
2699 distribute_notes (new_i3_notes, i3, i3, NULL_RTX, NULL_RTX, NULL_RTX);
2702 /* If I3DEST was used in I3SRC, it really died in I3. We may need to
2703 put a REG_DEAD note for it somewhere. If NEWI2PAT exists and sets
2704 I3DEST, the death must be somewhere before I2, not I3. If we passed I3
2705 in that case, it might delete I2. Similarly for I2 and I1.
2706 Show an additional death due to the REG_DEAD note we make here. If
2707 we discard it in distribute_notes, we will decrement it again. */
2711 if (GET_CODE (i3dest_killed) == REG)
2712 REG_N_DEATHS (REGNO (i3dest_killed))++;
2714 if (newi2pat && reg_set_p (i3dest_killed, newi2pat))
2715 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i3dest_killed,
2717 NULL_RTX, i2, NULL_RTX, elim_i2, elim_i1);
2719 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i3dest_killed,
2721 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
2725 if (i2dest_in_i2src)
2727 if (GET_CODE (i2dest) == REG)
2728 REG_N_DEATHS (REGNO (i2dest))++;
2730 if (newi2pat && reg_set_p (i2dest, newi2pat))
2731 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i2dest, NULL_RTX),
2732 NULL_RTX, i2, NULL_RTX, NULL_RTX, NULL_RTX);
2734 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i2dest, NULL_RTX),
2735 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
2736 NULL_RTX, NULL_RTX);
2739 if (i1dest_in_i1src)
2741 if (GET_CODE (i1dest) == REG)
2742 REG_N_DEATHS (REGNO (i1dest))++;
2744 if (newi2pat && reg_set_p (i1dest, newi2pat))
2745 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i1dest, NULL_RTX),
2746 NULL_RTX, i2, NULL_RTX, NULL_RTX, NULL_RTX);
2748 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i1dest, NULL_RTX),
2749 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
2750 NULL_RTX, NULL_RTX);
2753 distribute_links (i3links);
2754 distribute_links (i2links);
2755 distribute_links (i1links);
2757 if (GET_CODE (i2dest) == REG)
2760 rtx i2_insn = 0, i2_val = 0, set;
2762 /* The insn that used to set this register doesn't exist, and
2763 this life of the register may not exist either. See if one of
2764 I3's links points to an insn that sets I2DEST. If it does,
2765 that is now the last known value for I2DEST. If we don't update
2766 this and I2 set the register to a value that depended on its old
2767 contents, we will get confused. If this insn is used, thing
2768 will be set correctly in combine_instructions. */
2770 for (link = LOG_LINKS (i3); link; link = XEXP (link, 1))
2771 if ((set = single_set (XEXP (link, 0))) != 0
2772 && rtx_equal_p (i2dest, SET_DEST (set)))
2773 i2_insn = XEXP (link, 0), i2_val = SET_SRC (set);
2775 record_value_for_reg (i2dest, i2_insn, i2_val);
2777 /* If the reg formerly set in I2 died only once and that was in I3,
2778 zero its use count so it won't make `reload' do any work. */
2780 && (newi2pat == 0 || ! reg_mentioned_p (i2dest, newi2pat))
2781 && ! i2dest_in_i2src)
2783 regno = REGNO (i2dest);
2784 REG_N_SETS (regno)--;
2788 if (i1 && GET_CODE (i1dest) == REG)
2791 rtx i1_insn = 0, i1_val = 0, set;
2793 for (link = LOG_LINKS (i3); link; link = XEXP (link, 1))
2794 if ((set = single_set (XEXP (link, 0))) != 0
2795 && rtx_equal_p (i1dest, SET_DEST (set)))
2796 i1_insn = XEXP (link, 0), i1_val = SET_SRC (set);
2798 record_value_for_reg (i1dest, i1_insn, i1_val);
2800 regno = REGNO (i1dest);
2801 if (! added_sets_1 && ! i1dest_in_i1src)
2802 REG_N_SETS (regno)--;
2805 /* Update reg_nonzero_bits et al for any changes that may have been made
2806 to this insn. The order of set_nonzero_bits_and_sign_copies() is
2807 important. Because newi2pat can affect nonzero_bits of newpat */
2809 note_stores (newi2pat, set_nonzero_bits_and_sign_copies, NULL);
2810 note_stores (newpat, set_nonzero_bits_and_sign_copies, NULL);
2812 /* Set new_direct_jump_p if a new return or simple jump instruction
2815 If I3 is now an unconditional jump, ensure that it has a
2816 BARRIER following it since it may have initially been a
2817 conditional jump. It may also be the last nonnote insn. */
2819 if (GET_CODE (newpat) == RETURN || any_uncondjump_p (i3))
2821 *new_direct_jump_p = 1;
2823 if ((temp = next_nonnote_insn (i3)) == NULL_RTX
2824 || GET_CODE (temp) != BARRIER)
2825 emit_barrier_after (i3);
2827 /* An NOOP jump does not need barrier, but it does need cleaning up
2829 if (GET_CODE (newpat) == SET
2830 && SET_SRC (newpat) == pc_rtx
2831 && SET_DEST (newpat) == pc_rtx)
2832 *new_direct_jump_p = 1;
2835 combine_successes++;
2838 /* Clear this here, so that subsequent get_last_value calls are not
2840 subst_prev_insn = NULL_RTX;
2842 if (added_links_insn
2843 && (newi2pat == 0 || INSN_CUID (added_links_insn) < INSN_CUID (i2))
2844 && INSN_CUID (added_links_insn) < INSN_CUID (i3))
2845 return added_links_insn;
2847 return newi2pat ? i2 : i3;
2850 /* Undo all the modifications recorded in undobuf. */
2855 struct undo *undo, *next;
2857 for (undo = undobuf.undos; undo; undo = next)
2861 *undo->where.i = undo->old_contents.i;
2863 *undo->where.r = undo->old_contents.r;
2865 undo->next = undobuf.frees;
2866 undobuf.frees = undo;
2871 /* Clear this here, so that subsequent get_last_value calls are not
2873 subst_prev_insn = NULL_RTX;
2876 /* We've committed to accepting the changes we made. Move all
2877 of the undos to the free list. */
2882 struct undo *undo, *next;
2884 for (undo = undobuf.undos; undo; undo = next)
2887 undo->next = undobuf.frees;
2888 undobuf.frees = undo;
2894 /* Find the innermost point within the rtx at LOC, possibly LOC itself,
2895 where we have an arithmetic expression and return that point. LOC will
2898 try_combine will call this function to see if an insn can be split into
2902 find_split_point (loc, insn)
2907 enum rtx_code code = GET_CODE (x);
2909 unsigned HOST_WIDE_INT len = 0;
2910 HOST_WIDE_INT pos = 0;
2912 rtx inner = NULL_RTX;
2914 /* First special-case some codes. */
2918 #ifdef INSN_SCHEDULING
2919 /* If we are making a paradoxical SUBREG invalid, it becomes a split
2921 if (GET_CODE (SUBREG_REG (x)) == MEM)
2924 return find_split_point (&SUBREG_REG (x), insn);
2928 /* If we have (mem (const ..)) or (mem (symbol_ref ...)), split it
2929 using LO_SUM and HIGH. */
2930 if (GET_CODE (XEXP (x, 0)) == CONST
2931 || GET_CODE (XEXP (x, 0)) == SYMBOL_REF)
2934 gen_rtx_LO_SUM (Pmode,
2935 gen_rtx_HIGH (Pmode, XEXP (x, 0)),
2937 return &XEXP (XEXP (x, 0), 0);
2941 /* If we have a PLUS whose second operand is a constant and the
2942 address is not valid, perhaps will can split it up using
2943 the machine-specific way to split large constants. We use
2944 the first pseudo-reg (one of the virtual regs) as a placeholder;
2945 it will not remain in the result. */
2946 if (GET_CODE (XEXP (x, 0)) == PLUS
2947 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
2948 && ! memory_address_p (GET_MODE (x), XEXP (x, 0)))
2950 rtx reg = regno_reg_rtx[FIRST_PSEUDO_REGISTER];
2951 rtx seq = split_insns (gen_rtx_SET (VOIDmode, reg, XEXP (x, 0)),
2954 /* This should have produced two insns, each of which sets our
2955 placeholder. If the source of the second is a valid address,
2956 we can make put both sources together and make a split point
2959 if (seq && XVECLEN (seq, 0) == 2
2960 && GET_CODE (XVECEXP (seq, 0, 0)) == INSN
2961 && GET_CODE (PATTERN (XVECEXP (seq, 0, 0))) == SET
2962 && SET_DEST (PATTERN (XVECEXP (seq, 0, 0))) == reg
2963 && ! reg_mentioned_p (reg,
2964 SET_SRC (PATTERN (XVECEXP (seq, 0, 0))))
2965 && GET_CODE (XVECEXP (seq, 0, 1)) == INSN
2966 && GET_CODE (PATTERN (XVECEXP (seq, 0, 1))) == SET
2967 && SET_DEST (PATTERN (XVECEXP (seq, 0, 1))) == reg
2968 && memory_address_p (GET_MODE (x),
2969 SET_SRC (PATTERN (XVECEXP (seq, 0, 1)))))
2971 rtx src1 = SET_SRC (PATTERN (XVECEXP (seq, 0, 0)));
2972 rtx src2 = SET_SRC (PATTERN (XVECEXP (seq, 0, 1)));
2974 /* Replace the placeholder in SRC2 with SRC1. If we can
2975 find where in SRC2 it was placed, that can become our
2976 split point and we can replace this address with SRC2.
2977 Just try two obvious places. */
2979 src2 = replace_rtx (src2, reg, src1);
2981 if (XEXP (src2, 0) == src1)
2982 split = &XEXP (src2, 0);
2983 else if (GET_RTX_FORMAT (GET_CODE (XEXP (src2, 0)))[0] == 'e'
2984 && XEXP (XEXP (src2, 0), 0) == src1)
2985 split = &XEXP (XEXP (src2, 0), 0);
2989 SUBST (XEXP (x, 0), src2);
2994 /* If that didn't work, perhaps the first operand is complex and
2995 needs to be computed separately, so make a split point there.
2996 This will occur on machines that just support REG + CONST
2997 and have a constant moved through some previous computation. */
2999 else if (GET_RTX_CLASS (GET_CODE (XEXP (XEXP (x, 0), 0))) != 'o'
3000 && ! (GET_CODE (XEXP (XEXP (x, 0), 0)) == SUBREG
3001 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (XEXP (x, 0), 0))))
3003 return &XEXP (XEXP (x, 0), 0);
3009 /* If SET_DEST is CC0 and SET_SRC is not an operand, a COMPARE, or a
3010 ZERO_EXTRACT, the most likely reason why this doesn't match is that
3011 we need to put the operand into a register. So split at that
3014 if (SET_DEST (x) == cc0_rtx
3015 && GET_CODE (SET_SRC (x)) != COMPARE
3016 && GET_CODE (SET_SRC (x)) != ZERO_EXTRACT
3017 && GET_RTX_CLASS (GET_CODE (SET_SRC (x))) != 'o'
3018 && ! (GET_CODE (SET_SRC (x)) == SUBREG
3019 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (SET_SRC (x)))) == 'o'))
3020 return &SET_SRC (x);
3023 /* See if we can split SET_SRC as it stands. */
3024 split = find_split_point (&SET_SRC (x), insn);
3025 if (split && split != &SET_SRC (x))
3028 /* See if we can split SET_DEST as it stands. */
3029 split = find_split_point (&SET_DEST (x), insn);
3030 if (split && split != &SET_DEST (x))
3033 /* See if this is a bitfield assignment with everything constant. If
3034 so, this is an IOR of an AND, so split it into that. */
3035 if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
3036 && (GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0)))
3037 <= HOST_BITS_PER_WIDE_INT)
3038 && GET_CODE (XEXP (SET_DEST (x), 1)) == CONST_INT
3039 && GET_CODE (XEXP (SET_DEST (x), 2)) == CONST_INT
3040 && GET_CODE (SET_SRC (x)) == CONST_INT
3041 && ((INTVAL (XEXP (SET_DEST (x), 1))
3042 + INTVAL (XEXP (SET_DEST (x), 2)))
3043 <= GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0))))
3044 && ! side_effects_p (XEXP (SET_DEST (x), 0)))
3046 HOST_WIDE_INT pos = INTVAL (XEXP (SET_DEST (x), 2));
3047 unsigned HOST_WIDE_INT len = INTVAL (XEXP (SET_DEST (x), 1));
3048 unsigned HOST_WIDE_INT src = INTVAL (SET_SRC (x));
3049 rtx dest = XEXP (SET_DEST (x), 0);
3050 enum machine_mode mode = GET_MODE (dest);
3051 unsigned HOST_WIDE_INT mask = ((HOST_WIDE_INT) 1 << len) - 1;
3053 if (BITS_BIG_ENDIAN)
3054 pos = GET_MODE_BITSIZE (mode) - len - pos;
3058 gen_binary (IOR, mode, dest, GEN_INT (src << pos)));
3061 gen_binary (IOR, mode,
3062 gen_binary (AND, mode, dest,
3063 GEN_INT (~(mask << pos)
3064 & GET_MODE_MASK (mode))),
3065 GEN_INT (src << pos)));
3067 SUBST (SET_DEST (x), dest);
3069 split = find_split_point (&SET_SRC (x), insn);
3070 if (split && split != &SET_SRC (x))
3074 /* Otherwise, see if this is an operation that we can split into two.
3075 If so, try to split that. */
3076 code = GET_CODE (SET_SRC (x));
3081 /* If we are AND'ing with a large constant that is only a single
3082 bit and the result is only being used in a context where we
3083 need to know if it is zero or non-zero, replace it with a bit
3084 extraction. This will avoid the large constant, which might
3085 have taken more than one insn to make. If the constant were
3086 not a valid argument to the AND but took only one insn to make,
3087 this is no worse, but if it took more than one insn, it will
3090 if (GET_CODE (XEXP (SET_SRC (x), 1)) == CONST_INT
3091 && GET_CODE (XEXP (SET_SRC (x), 0)) == REG
3092 && (pos = exact_log2 (INTVAL (XEXP (SET_SRC (x), 1)))) >= 7
3093 && GET_CODE (SET_DEST (x)) == REG
3094 && (split = find_single_use (SET_DEST (x), insn, (rtx*) 0)) != 0
3095 && (GET_CODE (*split) == EQ || GET_CODE (*split) == NE)
3096 && XEXP (*split, 0) == SET_DEST (x)
3097 && XEXP (*split, 1) == const0_rtx)
3099 rtx extraction = make_extraction (GET_MODE (SET_DEST (x)),
3100 XEXP (SET_SRC (x), 0),
3101 pos, NULL_RTX, 1, 1, 0, 0);
3102 if (extraction != 0)
3104 SUBST (SET_SRC (x), extraction);
3105 return find_split_point (loc, insn);
3111 /* if STORE_FLAG_VALUE is -1, this is (NE X 0) and only one bit of X
3112 is known to be on, this can be converted into a NEG of a shift. */
3113 if (STORE_FLAG_VALUE == -1 && XEXP (SET_SRC (x), 1) == const0_rtx
3114 && GET_MODE (SET_SRC (x)) == GET_MODE (XEXP (SET_SRC (x), 0))
3115 && 1 <= (pos = exact_log2
3116 (nonzero_bits (XEXP (SET_SRC (x), 0),
3117 GET_MODE (XEXP (SET_SRC (x), 0))))))
3119 enum machine_mode mode = GET_MODE (XEXP (SET_SRC (x), 0));
3123 gen_rtx_LSHIFTRT (mode,
3124 XEXP (SET_SRC (x), 0),
3127 split = find_split_point (&SET_SRC (x), insn);
3128 if (split && split != &SET_SRC (x))
3134 inner = XEXP (SET_SRC (x), 0);
3136 /* We can't optimize if either mode is a partial integer
3137 mode as we don't know how many bits are significant
3139 if (GET_MODE_CLASS (GET_MODE (inner)) == MODE_PARTIAL_INT
3140 || GET_MODE_CLASS (GET_MODE (SET_SRC (x))) == MODE_PARTIAL_INT)
3144 len = GET_MODE_BITSIZE (GET_MODE (inner));
3150 if (GET_CODE (XEXP (SET_SRC (x), 1)) == CONST_INT
3151 && GET_CODE (XEXP (SET_SRC (x), 2)) == CONST_INT)
3153 inner = XEXP (SET_SRC (x), 0);
3154 len = INTVAL (XEXP (SET_SRC (x), 1));
3155 pos = INTVAL (XEXP (SET_SRC (x), 2));
3157 if (BITS_BIG_ENDIAN)
3158 pos = GET_MODE_BITSIZE (GET_MODE (inner)) - len - pos;
3159 unsignedp = (code == ZERO_EXTRACT);
3167 if (len && pos >= 0 && pos + len <= GET_MODE_BITSIZE (GET_MODE (inner)))
3169 enum machine_mode mode = GET_MODE (SET_SRC (x));
3171 /* For unsigned, we have a choice of a shift followed by an
3172 AND or two shifts. Use two shifts for field sizes where the
3173 constant might be too large. We assume here that we can
3174 always at least get 8-bit constants in an AND insn, which is
3175 true for every current RISC. */
3177 if (unsignedp && len <= 8)
3182 (mode, gen_lowpart_for_combine (mode, inner),
3184 GEN_INT (((HOST_WIDE_INT) 1 << len) - 1)));
3186 split = find_split_point (&SET_SRC (x), insn);
3187 if (split && split != &SET_SRC (x))
3194 (unsignedp ? LSHIFTRT : ASHIFTRT, mode,
3195 gen_rtx_ASHIFT (mode,
3196 gen_lowpart_for_combine (mode, inner),
3197 GEN_INT (GET_MODE_BITSIZE (mode)
3199 GEN_INT (GET_MODE_BITSIZE (mode) - len)));
3201 split = find_split_point (&SET_SRC (x), insn);
3202 if (split && split != &SET_SRC (x))
3207 /* See if this is a simple operation with a constant as the second
3208 operand. It might be that this constant is out of range and hence
3209 could be used as a split point. */
3210 if ((GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '2'
3211 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == 'c'
3212 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '<')
3213 && CONSTANT_P (XEXP (SET_SRC (x), 1))
3214 && (GET_RTX_CLASS (GET_CODE (XEXP (SET_SRC (x), 0))) == 'o'
3215 || (GET_CODE (XEXP (SET_SRC (x), 0)) == SUBREG
3216 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (SET_SRC (x), 0))))
3218 return &XEXP (SET_SRC (x), 1);
3220 /* Finally, see if this is a simple operation with its first operand
3221 not in a register. The operation might require this operand in a
3222 register, so return it as a split point. We can always do this
3223 because if the first operand were another operation, we would have
3224 already found it as a split point. */
3225 if ((GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '2'
3226 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == 'c'
3227 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '<'
3228 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '1')
3229 && ! register_operand (XEXP (SET_SRC (x), 0), VOIDmode))
3230 return &XEXP (SET_SRC (x), 0);
3236 /* We write NOR as (and (not A) (not B)), but if we don't have a NOR,
3237 it is better to write this as (not (ior A B)) so we can split it.
3238 Similarly for IOR. */
3239 if (GET_CODE (XEXP (x, 0)) == NOT && GET_CODE (XEXP (x, 1)) == NOT)
3242 gen_rtx_NOT (GET_MODE (x),
3243 gen_rtx_fmt_ee (code == IOR ? AND : IOR,
3245 XEXP (XEXP (x, 0), 0),
3246 XEXP (XEXP (x, 1), 0))));
3247 return find_split_point (loc, insn);
3250 /* Many RISC machines have a large set of logical insns. If the
3251 second operand is a NOT, put it first so we will try to split the
3252 other operand first. */
3253 if (GET_CODE (XEXP (x, 1)) == NOT)
3255 rtx tem = XEXP (x, 0);
3256 SUBST (XEXP (x, 0), XEXP (x, 1));
3257 SUBST (XEXP (x, 1), tem);
3265 /* Otherwise, select our actions depending on our rtx class. */
3266 switch (GET_RTX_CLASS (code))
3268 case 'b': /* This is ZERO_EXTRACT and SIGN_EXTRACT. */
3270 split = find_split_point (&XEXP (x, 2), insn);
3273 /* ... fall through ... */
3277 split = find_split_point (&XEXP (x, 1), insn);
3280 /* ... fall through ... */
3282 /* Some machines have (and (shift ...) ...) insns. If X is not
3283 an AND, but XEXP (X, 0) is, use it as our split point. */
3284 if (GET_CODE (x) != AND && GET_CODE (XEXP (x, 0)) == AND)
3285 return &XEXP (x, 0);
3287 split = find_split_point (&XEXP (x, 0), insn);
3293 /* Otherwise, we don't have a split point. */
3297 /* Throughout X, replace FROM with TO, and return the result.
3298 The result is TO if X is FROM;
3299 otherwise the result is X, but its contents may have been modified.
3300 If they were modified, a record was made in undobuf so that
3301 undo_all will (among other things) return X to its original state.
3303 If the number of changes necessary is too much to record to undo,
3304 the excess changes are not made, so the result is invalid.
3305 The changes already made can still be undone.
3306 undobuf.num_undo is incremented for such changes, so by testing that
3307 the caller can tell whether the result is valid.
3309 `n_occurrences' is incremented each time FROM is replaced.
3311 IN_DEST is non-zero if we are processing the SET_DEST of a SET.
3313 UNIQUE_COPY is non-zero if each substitution must be unique. We do this
3314 by copying if `n_occurrences' is non-zero. */
3317 subst (x, from, to, in_dest, unique_copy)
3322 enum rtx_code code = GET_CODE (x);
3323 enum machine_mode op0_mode = VOIDmode;
3328 /* Two expressions are equal if they are identical copies of a shared
3329 RTX or if they are both registers with the same register number
3332 #define COMBINE_RTX_EQUAL_P(X,Y) \
3334 || (GET_CODE (X) == REG && GET_CODE (Y) == REG \
3335 && REGNO (X) == REGNO (Y) && GET_MODE (X) == GET_MODE (Y)))
3337 if (! in_dest && COMBINE_RTX_EQUAL_P (x, from))
3340 return (unique_copy && n_occurrences > 1 ? copy_rtx (to) : to);
3343 /* If X and FROM are the same register but different modes, they will
3344 not have been seen as equal above. However, flow.c will make a
3345 LOG_LINKS entry for that case. If we do nothing, we will try to
3346 rerecognize our original insn and, when it succeeds, we will
3347 delete the feeding insn, which is incorrect.
3349 So force this insn not to match in this (rare) case. */
3350 if (! in_dest && code == REG && GET_CODE (from) == REG
3351 && REGNO (x) == REGNO (from))
3352 return gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
3354 /* If this is an object, we are done unless it is a MEM or LO_SUM, both
3355 of which may contain things that can be combined. */
3356 if (code != MEM && code != LO_SUM && GET_RTX_CLASS (code) == 'o')
3359 /* It is possible to have a subexpression appear twice in the insn.
3360 Suppose that FROM is a register that appears within TO.
3361 Then, after that subexpression has been scanned once by `subst',
3362 the second time it is scanned, TO may be found. If we were
3363 to scan TO here, we would find FROM within it and create a
3364 self-referent rtl structure which is completely wrong. */
3365 if (COMBINE_RTX_EQUAL_P (x, to))
3368 /* Parallel asm_operands need special attention because all of the
3369 inputs are shared across the arms. Furthermore, unsharing the
3370 rtl results in recognition failures. Failure to handle this case
3371 specially can result in circular rtl.
3373 Solve this by doing a normal pass across the first entry of the
3374 parallel, and only processing the SET_DESTs of the subsequent
3377 if (code == PARALLEL
3378 && GET_CODE (XVECEXP (x, 0, 0)) == SET
3379 && GET_CODE (SET_SRC (XVECEXP (x, 0, 0))) == ASM_OPERANDS)
3381 new = subst (XVECEXP (x, 0, 0), from, to, 0, unique_copy);
3383 /* If this substitution failed, this whole thing fails. */
3384 if (GET_CODE (new) == CLOBBER
3385 && XEXP (new, 0) == const0_rtx)
3388 SUBST (XVECEXP (x, 0, 0), new);
3390 for (i = XVECLEN (x, 0) - 1; i >= 1; i--)
3392 rtx dest = SET_DEST (XVECEXP (x, 0, i));
3394 if (GET_CODE (dest) != REG
3395 && GET_CODE (dest) != CC0
3396 && GET_CODE (dest) != PC)
3398 new = subst (dest, from, to, 0, unique_copy);
3400 /* If this substitution failed, this whole thing fails. */
3401 if (GET_CODE (new) == CLOBBER
3402 && XEXP (new, 0) == const0_rtx)
3405 SUBST (SET_DEST (XVECEXP (x, 0, i)), new);
3411 len = GET_RTX_LENGTH (code);
3412 fmt = GET_RTX_FORMAT (code);
3414 /* We don't need to process a SET_DEST that is a register, CC0,
3415 or PC, so set up to skip this common case. All other cases
3416 where we want to suppress replacing something inside a
3417 SET_SRC are handled via the IN_DEST operand. */
3419 && (GET_CODE (SET_DEST (x)) == REG
3420 || GET_CODE (SET_DEST (x)) == CC0
3421 || GET_CODE (SET_DEST (x)) == PC))
3424 /* Get the mode of operand 0 in case X is now a SIGN_EXTEND of a
3427 op0_mode = GET_MODE (XEXP (x, 0));
3429 for (i = 0; i < len; i++)
3434 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
3436 if (COMBINE_RTX_EQUAL_P (XVECEXP (x, i, j), from))
3438 new = (unique_copy && n_occurrences
3439 ? copy_rtx (to) : to);
3444 new = subst (XVECEXP (x, i, j), from, to, 0,
3447 /* If this substitution failed, this whole thing
3449 if (GET_CODE (new) == CLOBBER
3450 && XEXP (new, 0) == const0_rtx)
3454 SUBST (XVECEXP (x, i, j), new);
3457 else if (fmt[i] == 'e')
3459 /* If this is a register being set, ignore it. */
3462 && (code == SUBREG || code == STRICT_LOW_PART
3463 || code == ZERO_EXTRACT)
3465 && GET_CODE (new) == REG)
3468 else if (COMBINE_RTX_EQUAL_P (XEXP (x, i), from))
3470 /* In general, don't install a subreg involving two
3471 modes not tieable. It can worsen register
3472 allocation, and can even make invalid reload
3473 insns, since the reg inside may need to be copied
3474 from in the outside mode, and that may be invalid
3475 if it is an fp reg copied in integer mode.
3477 We allow two exceptions to this: It is valid if
3478 it is inside another SUBREG and the mode of that
3479 SUBREG and the mode of the inside of TO is
3480 tieable and it is valid if X is a SET that copies
3483 if (GET_CODE (to) == SUBREG
3484 && ! MODES_TIEABLE_P (GET_MODE (to),
3485 GET_MODE (SUBREG_REG (to)))
3486 && ! (code == SUBREG
3487 && MODES_TIEABLE_P (GET_MODE (x),
3488 GET_MODE (SUBREG_REG (to))))
3490 && ! (code == SET && i == 1 && XEXP (x, 0) == cc0_rtx)
3493 return gen_rtx_CLOBBER (VOIDmode, const0_rtx);
3495 #ifdef CLASS_CANNOT_CHANGE_MODE
3497 && GET_CODE (to) == REG
3498 && REGNO (to) < FIRST_PSEUDO_REGISTER
3499 && (TEST_HARD_REG_BIT
3500 (reg_class_contents[(int) CLASS_CANNOT_CHANGE_MODE],
3502 && CLASS_CANNOT_CHANGE_MODE_P (GET_MODE (to),
3504 return gen_rtx_CLOBBER (VOIDmode, const0_rtx);
3507 new = (unique_copy && n_occurrences ? copy_rtx (to) : to);
3511 /* If we are in a SET_DEST, suppress most cases unless we
3512 have gone inside a MEM, in which case we want to
3513 simplify the address. We assume here that things that
3514 are actually part of the destination have their inner
3515 parts in the first expression. This is true for SUBREG,
3516 STRICT_LOW_PART, and ZERO_EXTRACT, which are the only
3517 things aside from REG and MEM that should appear in a
3519 new = subst (XEXP (x, i), from, to,
3521 && (code == SUBREG || code == STRICT_LOW_PART
3522 || code == ZERO_EXTRACT))
3524 && i == 0), unique_copy);
3526 /* If we found that we will have to reject this combination,
3527 indicate that by returning the CLOBBER ourselves, rather than
3528 an expression containing it. This will speed things up as
3529 well as prevent accidents where two CLOBBERs are considered
3530 to be equal, thus producing an incorrect simplification. */
3532 if (GET_CODE (new) == CLOBBER && XEXP (new, 0) == const0_rtx)
3535 if (GET_CODE (new) == CONST_INT && GET_CODE (x) == SUBREG)
3537 x = simplify_subreg (GET_MODE (x), new,
3538 GET_MODE (SUBREG_REG (x)),
3543 else if (GET_CODE (new) == CONST_INT
3544 && GET_CODE (x) == ZERO_EXTEND)
3546 x = simplify_unary_operation (ZERO_EXTEND, GET_MODE (x),
3547 new, GET_MODE (XEXP (x, 0)));
3552 SUBST (XEXP (x, i), new);
3557 /* Try to simplify X. If the simplification changed the code, it is likely
3558 that further simplification will help, so loop, but limit the number
3559 of repetitions that will be performed. */
3561 for (i = 0; i < 4; i++)
3563 /* If X is sufficiently simple, don't bother trying to do anything
3565 if (code != CONST_INT && code != REG && code != CLOBBER)
3566 x = combine_simplify_rtx (x, op0_mode, i == 3, in_dest);
3568 if (GET_CODE (x) == code)
3571 code = GET_CODE (x);
3573 /* We no longer know the original mode of operand 0 since we
3574 have changed the form of X) */
3575 op0_mode = VOIDmode;
3581 /* Simplify X, a piece of RTL. We just operate on the expression at the
3582 outer level; call `subst' to simplify recursively. Return the new
3585 OP0_MODE is the original mode of XEXP (x, 0); LAST is nonzero if this
3586 will be the iteration even if an expression with a code different from
3587 X is returned; IN_DEST is nonzero if we are inside a SET_DEST. */
3590 combine_simplify_rtx (x, op0_mode, last, in_dest)
3592 enum machine_mode op0_mode;
3596 enum rtx_code code = GET_CODE (x);
3597 enum machine_mode mode = GET_MODE (x);
3602 /* If this is a commutative operation, put a constant last and a complex
3603 expression first. We don't need to do this for comparisons here. */
3604 if (GET_RTX_CLASS (code) == 'c'
3605 && swap_commutative_operands_p (XEXP (x, 0), XEXP (x, 1)))
3608 SUBST (XEXP (x, 0), XEXP (x, 1));
3609 SUBST (XEXP (x, 1), temp);
3612 /* If this is a PLUS, MINUS, or MULT, and the first operand is the
3613 sign extension of a PLUS with a constant, reverse the order of the sign
3614 extension and the addition. Note that this not the same as the original
3615 code, but overflow is undefined for signed values. Also note that the
3616 PLUS will have been partially moved "inside" the sign-extension, so that
3617 the first operand of X will really look like:
3618 (ashiftrt (plus (ashift A C4) C5) C4).
3620 (plus (ashiftrt (ashift A C4) C2) C4)
3621 and replace the first operand of X with that expression. Later parts
3622 of this function may simplify the expression further.
3624 For example, if we start with (mult (sign_extend (plus A C1)) C2),
3625 we swap the SIGN_EXTEND and PLUS. Later code will apply the
3626 distributive law to produce (plus (mult (sign_extend X) C1) C3).
3628 We do this to simplify address expressions. */
3630 if ((code == PLUS || code == MINUS || code == MULT)
3631 && GET_CODE (XEXP (x, 0)) == ASHIFTRT
3632 && GET_CODE (XEXP (XEXP (x, 0), 0)) == PLUS
3633 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == ASHIFT
3634 && GET_CODE (XEXP (XEXP (XEXP (XEXP (x, 0), 0), 0), 1)) == CONST_INT
3635 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3636 && XEXP (XEXP (XEXP (XEXP (x, 0), 0), 0), 1) == XEXP (XEXP (x, 0), 1)
3637 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == CONST_INT
3638 && (temp = simplify_binary_operation (ASHIFTRT, mode,
3639 XEXP (XEXP (XEXP (x, 0), 0), 1),
3640 XEXP (XEXP (x, 0), 1))) != 0)
3643 = simplify_shift_const (NULL_RTX, ASHIFT, mode,
3644 XEXP (XEXP (XEXP (XEXP (x, 0), 0), 0), 0),
3645 INTVAL (XEXP (XEXP (x, 0), 1)));
3647 new = simplify_shift_const (NULL_RTX, ASHIFTRT, mode, new,
3648 INTVAL (XEXP (XEXP (x, 0), 1)));
3650 SUBST (XEXP (x, 0), gen_binary (PLUS, mode, new, temp));
3653 /* If this is a simple operation applied to an IF_THEN_ELSE, try
3654 applying it to the arms of the IF_THEN_ELSE. This often simplifies
3655 things. Check for cases where both arms are testing the same
3658 Don't do anything if all operands are very simple. */
3660 if (((GET_RTX_CLASS (code) == '2' || GET_RTX_CLASS (code) == 'c'
3661 || GET_RTX_CLASS (code) == '<')
3662 && ((GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) != 'o'
3663 && ! (GET_CODE (XEXP (x, 0)) == SUBREG
3664 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 0))))
3666 || (GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) != 'o'
3667 && ! (GET_CODE (XEXP (x, 1)) == SUBREG
3668 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 1))))
3670 || (GET_RTX_CLASS (code) == '1'
3671 && ((GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) != 'o'
3672 && ! (GET_CODE (XEXP (x, 0)) == SUBREG
3673 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 0))))
3676 rtx cond, true_rtx, false_rtx;
3678 cond = if_then_else_cond (x, &true_rtx, &false_rtx);
3680 /* If everything is a comparison, what we have is highly unlikely
3681 to be simpler, so don't use it. */
3682 && ! (GET_RTX_CLASS (code) == '<'
3683 && (GET_RTX_CLASS (GET_CODE (true_rtx)) == '<'
3684 || GET_RTX_CLASS (GET_CODE (false_rtx)) == '<')))
3686 rtx cop1 = const0_rtx;
3687 enum rtx_code cond_code = simplify_comparison (NE, &cond, &cop1);
3689 if (cond_code == NE && GET_RTX_CLASS (GET_CODE (cond)) == '<')
3692 /* Simplify the alternative arms; this may collapse the true and
3693 false arms to store-flag values. */
3694 true_rtx = subst (true_rtx, pc_rtx, pc_rtx, 0, 0);
3695 false_rtx = subst (false_rtx, pc_rtx, pc_rtx, 0, 0);
3697 /* If true_rtx and false_rtx are not general_operands, an if_then_else
3698 is unlikely to be simpler. */
3699 if (general_operand (true_rtx, VOIDmode)
3700 && general_operand (false_rtx, VOIDmode))
3702 /* Restarting if we generate a store-flag expression will cause
3703 us to loop. Just drop through in this case. */
3705 /* If the result values are STORE_FLAG_VALUE and zero, we can
3706 just make the comparison operation. */
3707 if (true_rtx == const_true_rtx && false_rtx == const0_rtx)
3708 x = gen_binary (cond_code, mode, cond, cop1);
3709 else if (true_rtx == const0_rtx && false_rtx == const_true_rtx
3710 && reverse_condition (cond_code) != UNKNOWN)
3711 x = gen_binary (reverse_condition (cond_code),
3714 /* Likewise, we can make the negate of a comparison operation
3715 if the result values are - STORE_FLAG_VALUE and zero. */
3716 else if (GET_CODE (true_rtx) == CONST_INT
3717 && INTVAL (true_rtx) == - STORE_FLAG_VALUE
3718 && false_rtx == const0_rtx)
3719 x = simplify_gen_unary (NEG, mode,
3720 gen_binary (cond_code, mode, cond,
3723 else if (GET_CODE (false_rtx) == CONST_INT
3724 && INTVAL (false_rtx) == - STORE_FLAG_VALUE
3725 && true_rtx == const0_rtx)
3726 x = simplify_gen_unary (NEG, mode,
3727 gen_binary (reverse_condition
3732 return gen_rtx_IF_THEN_ELSE (mode,
3733 gen_binary (cond_code, VOIDmode,
3735 true_rtx, false_rtx);
3737 code = GET_CODE (x);
3738 op0_mode = VOIDmode;
3743 /* Try to fold this expression in case we have constants that weren't
3746 switch (GET_RTX_CLASS (code))
3749 temp = simplify_unary_operation (code, mode, XEXP (x, 0), op0_mode);
3753 enum machine_mode cmp_mode = GET_MODE (XEXP (x, 0));
3754 if (cmp_mode == VOIDmode)
3756 cmp_mode = GET_MODE (XEXP (x, 1));
3757 if (cmp_mode == VOIDmode)
3758 cmp_mode = op0_mode;
3760 temp = simplify_relational_operation (code, cmp_mode,
3761 XEXP (x, 0), XEXP (x, 1));
3763 #ifdef FLOAT_STORE_FLAG_VALUE
3764 if (temp != 0 && GET_MODE_CLASS (mode) == MODE_FLOAT)
3766 if (temp == const0_rtx)
3767 temp = CONST0_RTX (mode);
3769 temp = immed_real_const_1 (FLOAT_STORE_FLAG_VALUE (mode), mode);
3775 temp = simplify_binary_operation (code, mode, XEXP (x, 0), XEXP (x, 1));
3779 temp = simplify_ternary_operation (code, mode, op0_mode, XEXP (x, 0),
3780 XEXP (x, 1), XEXP (x, 2));
3787 code = GET_CODE (temp);
3788 op0_mode = VOIDmode;
3789 mode = GET_MODE (temp);
3792 /* First see if we can apply the inverse distributive law. */
3793 if (code == PLUS || code == MINUS
3794 || code == AND || code == IOR || code == XOR)
3796 x = apply_distributive_law (x);
3797 code = GET_CODE (x);
3798 op0_mode = VOIDmode;
3801 /* If CODE is an associative operation not otherwise handled, see if we
3802 can associate some operands. This can win if they are constants or
3803 if they are logically related (i.e. (a & b) & a). */
3804 if ((code == PLUS || code == MINUS || code == MULT || code == DIV
3805 || code == AND || code == IOR || code == XOR
3806 || code == SMAX || code == SMIN || code == UMAX || code == UMIN)
3807 && ((INTEGRAL_MODE_P (mode) && code != DIV)
3808 || (flag_unsafe_math_optimizations && FLOAT_MODE_P (mode))))
3810 if (GET_CODE (XEXP (x, 0)) == code)
3812 rtx other = XEXP (XEXP (x, 0), 0);
3813 rtx inner_op0 = XEXP (XEXP (x, 0), 1);
3814 rtx inner_op1 = XEXP (x, 1);
3817 /* Make sure we pass the constant operand if any as the second
3818 one if this is a commutative operation. */
3819 if (CONSTANT_P (inner_op0) && GET_RTX_CLASS (code) == 'c')
3821 rtx tem = inner_op0;
3822 inner_op0 = inner_op1;
3825 inner = simplify_binary_operation (code == MINUS ? PLUS
3826 : code == DIV ? MULT
3828 mode, inner_op0, inner_op1);
3830 /* For commutative operations, try the other pair if that one
3832 if (inner == 0 && GET_RTX_CLASS (code) == 'c')
3834 other = XEXP (XEXP (x, 0), 1);
3835 inner = simplify_binary_operation (code, mode,
3836 XEXP (XEXP (x, 0), 0),
3841 return gen_binary (code, mode, other, inner);
3845 /* A little bit of algebraic simplification here. */
3849 /* Ensure that our address has any ASHIFTs converted to MULT in case
3850 address-recognizing predicates are called later. */
3851 temp = make_compound_operation (XEXP (x, 0), MEM);
3852 SUBST (XEXP (x, 0), temp);
3856 if (op0_mode == VOIDmode)
3857 op0_mode = GET_MODE (SUBREG_REG (x));
3859 /* simplify_subreg can't use gen_lowpart_for_combine. */
3860 if (CONSTANT_P (SUBREG_REG (x))
3861 && subreg_lowpart_offset (mode, op0_mode) == SUBREG_BYTE (x))
3862 return gen_lowpart_for_combine (mode, SUBREG_REG (x));
3864 if (GET_MODE_CLASS (GET_MODE (SUBREG_REG (x))) == MODE_CC)
3868 temp = simplify_subreg (mode, SUBREG_REG (x), op0_mode,
3874 /* Note that we cannot do any narrowing for non-constants since
3875 we might have been counting on using the fact that some bits were
3876 zero. We now do this in the SET. */
3881 /* (not (plus X -1)) can become (neg X). */
3882 if (GET_CODE (XEXP (x, 0)) == PLUS
3883 && XEXP (XEXP (x, 0), 1) == constm1_rtx)
3884 return gen_rtx_NEG (mode, XEXP (XEXP (x, 0), 0));
3886 /* Similarly, (not (neg X)) is (plus X -1). */
3887 if (GET_CODE (XEXP (x, 0)) == NEG)
3888 return gen_rtx_PLUS (mode, XEXP (XEXP (x, 0), 0), constm1_rtx);
3890 /* (not (xor X C)) for C constant is (xor X D) with D = ~C. */
3891 if (GET_CODE (XEXP (x, 0)) == XOR
3892 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3893 && (temp = simplify_unary_operation (NOT, mode,
3894 XEXP (XEXP (x, 0), 1),
3896 return gen_binary (XOR, mode, XEXP (XEXP (x, 0), 0), temp);
3898 /* (not (ashift 1 X)) is (rotate ~1 X). We used to do this for operands
3899 other than 1, but that is not valid. We could do a similar
3900 simplification for (not (lshiftrt C X)) where C is just the sign bit,
3901 but this doesn't seem common enough to bother with. */
3902 if (GET_CODE (XEXP (x, 0)) == ASHIFT
3903 && XEXP (XEXP (x, 0), 0) == const1_rtx)
3904 return gen_rtx_ROTATE (mode, simplify_gen_unary (NOT, mode,
3906 XEXP (XEXP (x, 0), 1));
3908 if (GET_CODE (XEXP (x, 0)) == SUBREG
3909 && subreg_lowpart_p (XEXP (x, 0))
3910 && (GET_MODE_SIZE (GET_MODE (XEXP (x, 0)))
3911 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (x, 0)))))
3912 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == ASHIFT
3913 && XEXP (SUBREG_REG (XEXP (x, 0)), 0) == const1_rtx)
3915 enum machine_mode inner_mode = GET_MODE (SUBREG_REG (XEXP (x, 0)));
3917 x = gen_rtx_ROTATE (inner_mode,
3918 simplify_gen_unary (NOT, inner_mode, const1_rtx,
3920 XEXP (SUBREG_REG (XEXP (x, 0)), 1));
3921 return gen_lowpart_for_combine (mode, x);
3924 /* If STORE_FLAG_VALUE is -1, (not (comparison foo bar)) can be done by
3925 reversing the comparison code if valid. */
3926 if (STORE_FLAG_VALUE == -1
3927 && GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
3928 && (reversed = reversed_comparison (x, mode, XEXP (XEXP (x, 0), 0),
3929 XEXP (XEXP (x, 0), 1))))
3932 /* (not (ashiftrt foo C)) where C is the number of bits in FOO minus 1
3933 is (ge foo (const_int 0)) if STORE_FLAG_VALUE is -1, so we can
3934 perform the above simplification. */
3936 if (STORE_FLAG_VALUE == -1
3937 && GET_CODE (XEXP (x, 0)) == ASHIFTRT
3938 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3939 && INTVAL (XEXP (XEXP (x, 0), 1)) == GET_MODE_BITSIZE (mode) - 1)
3940 return gen_rtx_GE (mode, XEXP (XEXP (x, 0), 0), const0_rtx);
3942 /* Apply De Morgan's laws to reduce number of patterns for machines
3943 with negating logical insns (and-not, nand, etc.). If result has
3944 only one NOT, put it first, since that is how the patterns are
3947 if (GET_CODE (XEXP (x, 0)) == IOR || GET_CODE (XEXP (x, 0)) == AND)
3949 rtx in1 = XEXP (XEXP (x, 0), 0), in2 = XEXP (XEXP (x, 0), 1);
3950 enum machine_mode op_mode;
3952 op_mode = GET_MODE (in1);
3953 in1 = simplify_gen_unary (NOT, op_mode, in1, op_mode);
3955 op_mode = GET_MODE (in2);
3956 if (op_mode == VOIDmode)
3958 in2 = simplify_gen_unary (NOT, op_mode, in2, op_mode);
3960 if (GET_CODE (in2) == NOT && GET_CODE (in1) != NOT)
3963 in2 = in1; in1 = tem;
3966 return gen_rtx_fmt_ee (GET_CODE (XEXP (x, 0)) == IOR ? AND : IOR,
3972 /* (neg (plus X 1)) can become (not X). */
3973 if (GET_CODE (XEXP (x, 0)) == PLUS
3974 && XEXP (XEXP (x, 0), 1) == const1_rtx)
3975 return gen_rtx_NOT (mode, XEXP (XEXP (x, 0), 0));
3977 /* Similarly, (neg (not X)) is (plus X 1). */
3978 if (GET_CODE (XEXP (x, 0)) == NOT)
3979 return plus_constant (XEXP (XEXP (x, 0), 0), 1);
3981 /* (neg (minus X Y)) can become (minus Y X). */
3982 if (GET_CODE (XEXP (x, 0)) == MINUS
3983 && (! FLOAT_MODE_P (mode)
3984 /* x-y != -(y-x) with IEEE floating point. */
3985 || TARGET_FLOAT_FORMAT != IEEE_FLOAT_FORMAT
3986 || flag_unsafe_math_optimizations))
3987 return gen_binary (MINUS, mode, XEXP (XEXP (x, 0), 1),
3988 XEXP (XEXP (x, 0), 0));
3990 /* (neg (xor A 1)) is (plus A -1) if A is known to be either 0 or 1. */
3991 if (GET_CODE (XEXP (x, 0)) == XOR && XEXP (XEXP (x, 0), 1) == const1_rtx
3992 && nonzero_bits (XEXP (XEXP (x, 0), 0), mode) == 1)
3993 return gen_binary (PLUS, mode, XEXP (XEXP (x, 0), 0), constm1_rtx);
3995 /* NEG commutes with ASHIFT since it is multiplication. Only do this
3996 if we can then eliminate the NEG (e.g.,
3997 if the operand is a constant). */
3999 if (GET_CODE (XEXP (x, 0)) == ASHIFT)
4001 temp = simplify_unary_operation (NEG, mode,
4002 XEXP (XEXP (x, 0), 0), mode);
4004 return gen_binary (ASHIFT, mode, temp, XEXP (XEXP (x, 0), 1));
4007 temp = expand_compound_operation (XEXP (x, 0));
4009 /* For C equal to the width of MODE minus 1, (neg (ashiftrt X C)) can be
4010 replaced by (lshiftrt X C). This will convert
4011 (neg (sign_extract X 1 Y)) to (zero_extract X 1 Y). */
4013 if (GET_CODE (temp) == ASHIFTRT
4014 && GET_CODE (XEXP (temp, 1)) == CONST_INT
4015 && INTVAL (XEXP (temp, 1)) == GET_MODE_BITSIZE (mode) - 1)
4016 return simplify_shift_const (temp, LSHIFTRT, mode, XEXP (temp, 0),
4017 INTVAL (XEXP (temp, 1)));
4019 /* If X has only a single bit that might be nonzero, say, bit I, convert
4020 (neg X) to (ashiftrt (ashift X C-I) C-I) where C is the bitsize of
4021 MODE minus 1. This will convert (neg (zero_extract X 1 Y)) to
4022 (sign_extract X 1 Y). But only do this if TEMP isn't a register
4023 or a SUBREG of one since we'd be making the expression more
4024 complex if it was just a register. */
4026 if (GET_CODE (temp) != REG
4027 && ! (GET_CODE (temp) == SUBREG
4028 && GET_CODE (SUBREG_REG (temp)) == REG)
4029 && (i = exact_log2 (nonzero_bits (temp, mode))) >= 0)
4031 rtx temp1 = simplify_shift_const
4032 (NULL_RTX, ASHIFTRT, mode,
4033 simplify_shift_const (NULL_RTX, ASHIFT, mode, temp,
4034 GET_MODE_BITSIZE (mode) - 1 - i),
4035 GET_MODE_BITSIZE (mode) - 1 - i);
4037 /* If all we did was surround TEMP with the two shifts, we
4038 haven't improved anything, so don't use it. Otherwise,
4039 we are better off with TEMP1. */
4040 if (GET_CODE (temp1) != ASHIFTRT
4041 || GET_CODE (XEXP (temp1, 0)) != ASHIFT
4042 || XEXP (XEXP (temp1, 0), 0) != temp)
4048 /* We can't handle truncation to a partial integer mode here
4049 because we don't know the real bitsize of the partial
4051 if (GET_MODE_CLASS (mode) == MODE_PARTIAL_INT)
4054 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4055 && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode),
4056 GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))))
4058 force_to_mode (XEXP (x, 0), GET_MODE (XEXP (x, 0)),
4059 GET_MODE_MASK (mode), NULL_RTX, 0));
4061 /* (truncate:SI ({sign,zero}_extend:DI foo:SI)) == foo:SI. */
4062 if ((GET_CODE (XEXP (x, 0)) == SIGN_EXTEND
4063 || GET_CODE (XEXP (x, 0)) == ZERO_EXTEND)
4064 && GET_MODE (XEXP (XEXP (x, 0), 0)) == mode)
4065 return XEXP (XEXP (x, 0), 0);
4067 /* (truncate:SI (OP:DI ({sign,zero}_extend:DI foo:SI))) is
4068 (OP:SI foo:SI) if OP is NEG or ABS. */
4069 if ((GET_CODE (XEXP (x, 0)) == ABS
4070 || GET_CODE (XEXP (x, 0)) == NEG)
4071 && (GET_CODE (XEXP (XEXP (x, 0), 0)) == SIGN_EXTEND
4072 || GET_CODE (XEXP (XEXP (x, 0), 0)) == ZERO_EXTEND)
4073 && GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == mode)
4074 return simplify_gen_unary (GET_CODE (XEXP (x, 0)), mode,
4075 XEXP (XEXP (XEXP (x, 0), 0), 0), mode);
4077 /* (truncate:SI (subreg:DI (truncate:SI X) 0)) is
4079 if (GET_CODE (XEXP (x, 0)) == SUBREG
4080 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == TRUNCATE
4081 && subreg_lowpart_p (XEXP (x, 0)))
4082 return SUBREG_REG (XEXP (x, 0));
4084 /* If we know that the value is already truncated, we can
4085 replace the TRUNCATE with a SUBREG if TRULY_NOOP_TRUNCATION
4086 is nonzero for the corresponding modes. But don't do this
4087 for an (LSHIFTRT (MULT ...)) since this will cause problems
4088 with the umulXi3_highpart patterns. */
4089 if (TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode),
4090 GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))))
4091 && num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
4092 >= GET_MODE_BITSIZE (mode) + 1
4093 && ! (GET_CODE (XEXP (x, 0)) == LSHIFTRT
4094 && GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT))
4095 return gen_lowpart_for_combine (mode, XEXP (x, 0));
4097 /* A truncate of a comparison can be replaced with a subreg if
4098 STORE_FLAG_VALUE permits. This is like the previous test,
4099 but it works even if the comparison is done in a mode larger
4100 than HOST_BITS_PER_WIDE_INT. */
4101 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4102 && GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
4103 && ((HOST_WIDE_INT) STORE_FLAG_VALUE & ~GET_MODE_MASK (mode)) == 0)
4104 return gen_lowpart_for_combine (mode, XEXP (x, 0));
4106 /* Similarly, a truncate of a register whose value is a
4107 comparison can be replaced with a subreg if STORE_FLAG_VALUE
4109 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4110 && ((HOST_WIDE_INT) STORE_FLAG_VALUE & ~GET_MODE_MASK (mode)) == 0
4111 && (temp = get_last_value (XEXP (x, 0)))
4112 && GET_RTX_CLASS (GET_CODE (temp)) == '<')
4113 return gen_lowpart_for_combine (mode, XEXP (x, 0));
4117 case FLOAT_TRUNCATE:
4118 /* (float_truncate:SF (float_extend:DF foo:SF)) = foo:SF. */
4119 if (GET_CODE (XEXP (x, 0)) == FLOAT_EXTEND
4120 && GET_MODE (XEXP (XEXP (x, 0), 0)) == mode)
4121 return XEXP (XEXP (x, 0), 0);
4123 /* (float_truncate:SF (OP:DF (float_extend:DF foo:sf))) is
4124 (OP:SF foo:SF) if OP is NEG or ABS. */
4125 if ((GET_CODE (XEXP (x, 0)) == ABS
4126 || GET_CODE (XEXP (x, 0)) == NEG)
4127 && GET_CODE (XEXP (XEXP (x, 0), 0)) == FLOAT_EXTEND
4128 && GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == mode)
4129 return simplify_gen_unary (GET_CODE (XEXP (x, 0)), mode,
4130 XEXP (XEXP (XEXP (x, 0), 0), 0), mode);
4132 /* (float_truncate:SF (subreg:DF (float_truncate:SF X) 0))
4133 is (float_truncate:SF x). */
4134 if (GET_CODE (XEXP (x, 0)) == SUBREG
4135 && subreg_lowpart_p (XEXP (x, 0))
4136 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == FLOAT_TRUNCATE)
4137 return SUBREG_REG (XEXP (x, 0));
4142 /* Convert (compare FOO (const_int 0)) to FOO unless we aren't
4143 using cc0, in which case we want to leave it as a COMPARE
4144 so we can distinguish it from a register-register-copy. */
4145 if (XEXP (x, 1) == const0_rtx)
4148 /* In IEEE floating point, x-0 is not the same as x. */
4149 if ((TARGET_FLOAT_FORMAT != IEEE_FLOAT_FORMAT
4150 || ! FLOAT_MODE_P (GET_MODE (XEXP (x, 0)))
4151 || flag_unsafe_math_optimizations)
4152 && XEXP (x, 1) == CONST0_RTX (GET_MODE (XEXP (x, 0))))
4158 /* (const (const X)) can become (const X). Do it this way rather than
4159 returning the inner CONST since CONST can be shared with a
4161 if (GET_CODE (XEXP (x, 0)) == CONST)
4162 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4167 /* Convert (lo_sum (high FOO) FOO) to FOO. This is necessary so we
4168 can add in an offset. find_split_point will split this address up
4169 again if it doesn't match. */
4170 if (GET_CODE (XEXP (x, 0)) == HIGH
4171 && rtx_equal_p (XEXP (XEXP (x, 0), 0), XEXP (x, 1)))
4177 /* If we have (plus (plus (A const) B)), associate it so that CONST is
4178 outermost. That's because that's the way indexed addresses are
4179 supposed to appear. This code used to check many more cases, but
4180 they are now checked elsewhere. */
4181 if (GET_CODE (XEXP (x, 0)) == PLUS
4182 && CONSTANT_ADDRESS_P (XEXP (XEXP (x, 0), 1)))
4183 return gen_binary (PLUS, mode,
4184 gen_binary (PLUS, mode, XEXP (XEXP (x, 0), 0),
4186 XEXP (XEXP (x, 0), 1));
4188 /* (plus (xor (and <foo> (const_int pow2 - 1)) <c>) <-c>)
4189 when c is (const_int (pow2 + 1) / 2) is a sign extension of a
4190 bit-field and can be replaced by either a sign_extend or a
4191 sign_extract. The `and' may be a zero_extend and the two
4192 <c>, -<c> constants may be reversed. */
4193 if (GET_CODE (XEXP (x, 0)) == XOR
4194 && GET_CODE (XEXP (x, 1)) == CONST_INT
4195 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
4196 && INTVAL (XEXP (x, 1)) == -INTVAL (XEXP (XEXP (x, 0), 1))
4197 && ((i = exact_log2 (INTVAL (XEXP (XEXP (x, 0), 1)))) >= 0
4198 || (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0)
4199 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4200 && ((GET_CODE (XEXP (XEXP (x, 0), 0)) == AND
4201 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == CONST_INT
4202 && (INTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1))
4203 == ((HOST_WIDE_INT) 1 << (i + 1)) - 1))
4204 || (GET_CODE (XEXP (XEXP (x, 0), 0)) == ZERO_EXTEND
4205 && (GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)))
4206 == (unsigned int) i + 1))))
4207 return simplify_shift_const
4208 (NULL_RTX, ASHIFTRT, mode,
4209 simplify_shift_const (NULL_RTX, ASHIFT, mode,
4210 XEXP (XEXP (XEXP (x, 0), 0), 0),
4211 GET_MODE_BITSIZE (mode) - (i + 1)),
4212 GET_MODE_BITSIZE (mode) - (i + 1));
4214 /* (plus (comparison A B) C) can become (neg (rev-comp A B)) if
4215 C is 1 and STORE_FLAG_VALUE is -1 or if C is -1 and STORE_FLAG_VALUE
4216 is 1. This produces better code than the alternative immediately
4218 if (GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
4219 && ((STORE_FLAG_VALUE == -1 && XEXP (x, 1) == const1_rtx)
4220 || (STORE_FLAG_VALUE == 1 && XEXP (x, 1) == constm1_rtx))
4221 && (reversed = reversed_comparison (XEXP (x, 0), mode,
4222 XEXP (XEXP (x, 0), 0),
4223 XEXP (XEXP (x, 0), 1))))
4225 simplify_gen_unary (NEG, mode, reversed, mode);
4227 /* If only the low-order bit of X is possibly nonzero, (plus x -1)
4228 can become (ashiftrt (ashift (xor x 1) C) C) where C is
4229 the bitsize of the mode - 1. This allows simplification of
4230 "a = (b & 8) == 0;" */
4231 if (XEXP (x, 1) == constm1_rtx
4232 && GET_CODE (XEXP (x, 0)) != REG
4233 && ! (GET_CODE (XEXP (x,0)) == SUBREG
4234 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == REG)
4235 && nonzero_bits (XEXP (x, 0), mode) == 1)
4236 return simplify_shift_const (NULL_RTX, ASHIFTRT, mode,
4237 simplify_shift_const (NULL_RTX, ASHIFT, mode,
4238 gen_rtx_XOR (mode, XEXP (x, 0), const1_rtx),
4239 GET_MODE_BITSIZE (mode) - 1),
4240 GET_MODE_BITSIZE (mode) - 1);
4242 /* If we are adding two things that have no bits in common, convert
4243 the addition into an IOR. This will often be further simplified,
4244 for example in cases like ((a & 1) + (a & 2)), which can
4247 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4248 && (nonzero_bits (XEXP (x, 0), mode)
4249 & nonzero_bits (XEXP (x, 1), mode)) == 0)
4251 /* Try to simplify the expression further. */
4252 rtx tor = gen_binary (IOR, mode, XEXP (x, 0), XEXP (x, 1));
4253 temp = combine_simplify_rtx (tor, mode, last, in_dest);
4255 /* If we could, great. If not, do not go ahead with the IOR
4256 replacement, since PLUS appears in many special purpose
4257 address arithmetic instructions. */
4258 if (GET_CODE (temp) != CLOBBER && temp != tor)
4264 /* If STORE_FLAG_VALUE is 1, (minus 1 (comparison foo bar)) can be done
4265 by reversing the comparison code if valid. */
4266 if (STORE_FLAG_VALUE == 1
4267 && XEXP (x, 0) == const1_rtx
4268 && GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) == '<'
4269 && (reversed = reversed_comparison (XEXP (x, 1), mode,
4270 XEXP (XEXP (x, 1), 0),
4271 XEXP (XEXP (x, 1), 1))))
4274 /* (minus <foo> (and <foo> (const_int -pow2))) becomes
4275 (and <foo> (const_int pow2-1)) */
4276 if (GET_CODE (XEXP (x, 1)) == AND
4277 && GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT
4278 && exact_log2 (-INTVAL (XEXP (XEXP (x, 1), 1))) >= 0
4279 && rtx_equal_p (XEXP (XEXP (x, 1), 0), XEXP (x, 0)))
4280 return simplify_and_const_int (NULL_RTX, mode, XEXP (x, 0),
4281 -INTVAL (XEXP (XEXP (x, 1), 1)) - 1);
4283 /* Canonicalize (minus A (plus B C)) to (minus (minus A B) C) for
4285 if (GET_CODE (XEXP (x, 1)) == PLUS && INTEGRAL_MODE_P (mode))
4286 return gen_binary (MINUS, mode,
4287 gen_binary (MINUS, mode, XEXP (x, 0),
4288 XEXP (XEXP (x, 1), 0)),
4289 XEXP (XEXP (x, 1), 1));
4293 /* If we have (mult (plus A B) C), apply the distributive law and then
4294 the inverse distributive law to see if things simplify. This
4295 occurs mostly in addresses, often when unrolling loops. */
4297 if (GET_CODE (XEXP (x, 0)) == PLUS)
4299 x = apply_distributive_law
4300 (gen_binary (PLUS, mode,
4301 gen_binary (MULT, mode,
4302 XEXP (XEXP (x, 0), 0), XEXP (x, 1)),
4303 gen_binary (MULT, mode,
4304 XEXP (XEXP (x, 0), 1),
4305 copy_rtx (XEXP (x, 1)))));
4307 if (GET_CODE (x) != MULT)
4310 /* Try simplify a*(b/c) as (a*b)/c. */
4311 if (FLOAT_MODE_P (mode) && flag_unsafe_math_optimizations
4312 && GET_CODE (XEXP (x, 0)) == DIV)
4314 rtx tem = simplify_binary_operation (MULT, mode,
4315 XEXP (XEXP (x, 0), 0),
4318 return gen_binary (DIV, mode, tem, XEXP (XEXP (x, 0), 1));
4323 /* If this is a divide by a power of two, treat it as a shift if
4324 its first operand is a shift. */
4325 if (GET_CODE (XEXP (x, 1)) == CONST_INT
4326 && (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0
4327 && (GET_CODE (XEXP (x, 0)) == ASHIFT
4328 || GET_CODE (XEXP (x, 0)) == LSHIFTRT
4329 || GET_CODE (XEXP (x, 0)) == ASHIFTRT
4330 || GET_CODE (XEXP (x, 0)) == ROTATE
4331 || GET_CODE (XEXP (x, 0)) == ROTATERT))
4332 return simplify_shift_const (NULL_RTX, LSHIFTRT, mode, XEXP (x, 0), i);
4336 case GT: case GTU: case GE: case GEU:
4337 case LT: case LTU: case LE: case LEU:
4338 case UNEQ: case LTGT:
4339 case UNGT: case UNGE:
4340 case UNLT: case UNLE:
4341 case UNORDERED: case ORDERED:
4342 /* If the first operand is a condition code, we can't do anything
4344 if (GET_CODE (XEXP (x, 0)) == COMPARE
4345 || (GET_MODE_CLASS (GET_MODE (XEXP (x, 0))) != MODE_CC
4347 && XEXP (x, 0) != cc0_rtx
4351 rtx op0 = XEXP (x, 0);
4352 rtx op1 = XEXP (x, 1);
4353 enum rtx_code new_code;
4355 if (GET_CODE (op0) == COMPARE)
4356 op1 = XEXP (op0, 1), op0 = XEXP (op0, 0);
4358 /* Simplify our comparison, if possible. */
4359 new_code = simplify_comparison (code, &op0, &op1);
4361 /* If STORE_FLAG_VALUE is 1, we can convert (ne x 0) to simply X
4362 if only the low-order bit is possibly nonzero in X (such as when
4363 X is a ZERO_EXTRACT of one bit). Similarly, we can convert EQ to
4364 (xor X 1) or (minus 1 X); we use the former. Finally, if X is
4365 known to be either 0 or -1, NE becomes a NEG and EQ becomes
4368 Remove any ZERO_EXTRACT we made when thinking this was a
4369 comparison. It may now be simpler to use, e.g., an AND. If a
4370 ZERO_EXTRACT is indeed appropriate, it will be placed back by
4371 the call to make_compound_operation in the SET case. */
4373 if (STORE_FLAG_VALUE == 1
4374 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4375 && op1 == const0_rtx
4376 && mode == GET_MODE (op0)
4377 && nonzero_bits (op0, mode) == 1)
4378 return gen_lowpart_for_combine (mode,
4379 expand_compound_operation (op0));
4381 else if (STORE_FLAG_VALUE == 1
4382 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4383 && op1 == const0_rtx
4384 && mode == GET_MODE (op0)
4385 && (num_sign_bit_copies (op0, mode)
4386 == GET_MODE_BITSIZE (mode)))
4388 op0 = expand_compound_operation (op0);
4389 return simplify_gen_unary (NEG, mode,
4390 gen_lowpart_for_combine (mode, op0),
4394 else if (STORE_FLAG_VALUE == 1
4395 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
4396 && op1 == const0_rtx
4397 && mode == GET_MODE (op0)
4398 && nonzero_bits (op0, mode) == 1)
4400 op0 = expand_compound_operation (op0);
4401 return gen_binary (XOR, mode,
4402 gen_lowpart_for_combine (mode, op0),
4406 else if (STORE_FLAG_VALUE == 1
4407 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
4408 && op1 == const0_rtx
4409 && mode == GET_MODE (op0)
4410 && (num_sign_bit_copies (op0, mode)
4411 == GET_MODE_BITSIZE (mode)))
4413 op0 = expand_compound_operation (op0);
4414 return plus_constant (gen_lowpart_for_combine (mode, op0), 1);
4417 /* If STORE_FLAG_VALUE is -1, we have cases similar to
4419 if (STORE_FLAG_VALUE == -1
4420 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4421 && op1 == const0_rtx
4422 && (num_sign_bit_copies (op0, mode)
4423 == GET_MODE_BITSIZE (mode)))
4424 return gen_lowpart_for_combine (mode,
4425 expand_compound_operation (op0));
4427 else if (STORE_FLAG_VALUE == -1
4428 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4429 && op1 == const0_rtx
4430 && mode == GET_MODE (op0)
4431 && nonzero_bits (op0, mode) == 1)
4433 op0 = expand_compound_operation (op0);
4434 return simplify_gen_unary (NEG, mode,
4435 gen_lowpart_for_combine (mode, op0),
4439 else if (STORE_FLAG_VALUE == -1
4440 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
4441 && op1 == const0_rtx
4442 && mode == GET_MODE (op0)
4443 && (num_sign_bit_copies (op0, mode)
4444 == GET_MODE_BITSIZE (mode)))
4446 op0 = expand_compound_operation (op0);
4447 return simplify_gen_unary (NOT, mode,
4448 gen_lowpart_for_combine (mode, op0),
4452 /* If X is 0/1, (eq X 0) is X-1. */
4453 else if (STORE_FLAG_VALUE == -1
4454 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
4455 && op1 == const0_rtx
4456 && mode == GET_MODE (op0)
4457 && nonzero_bits (op0, mode) == 1)
4459 op0 = expand_compound_operation (op0);
4460 return plus_constant (gen_lowpart_for_combine (mode, op0), -1);
4463 /* If STORE_FLAG_VALUE says to just test the sign bit and X has just
4464 one bit that might be nonzero, we can convert (ne x 0) to
4465 (ashift x c) where C puts the bit in the sign bit. Remove any
4466 AND with STORE_FLAG_VALUE when we are done, since we are only
4467 going to test the sign bit. */
4468 if (new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4469 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4470 && ((STORE_FLAG_VALUE & GET_MODE_MASK (mode))
4471 == (unsigned HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE(mode)-1))
4472 && op1 == const0_rtx
4473 && mode == GET_MODE (op0)
4474 && (i = exact_log2 (nonzero_bits (op0, mode))) >= 0)
4476 x = simplify_shift_const (NULL_RTX, ASHIFT, mode,
4477 expand_compound_operation (op0),
4478 GET_MODE_BITSIZE (mode) - 1 - i);
4479 if (GET_CODE (x) == AND && XEXP (x, 1) == const_true_rtx)
4485 /* If the code changed, return a whole new comparison. */
4486 if (new_code != code)
4487 return gen_rtx_fmt_ee (new_code, mode, op0, op1);
4489 /* Otherwise, keep this operation, but maybe change its operands.
4490 This also converts (ne (compare FOO BAR) 0) to (ne FOO BAR). */
4491 SUBST (XEXP (x, 0), op0);
4492 SUBST (XEXP (x, 1), op1);
4497 return simplify_if_then_else (x);
4503 /* If we are processing SET_DEST, we are done. */
4507 return expand_compound_operation (x);
4510 return simplify_set (x);
4515 return simplify_logical (x, last);
4518 /* (abs (neg <foo>)) -> (abs <foo>) */
4519 if (GET_CODE (XEXP (x, 0)) == NEG)
4520 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4522 /* If the mode of the operand is VOIDmode (i.e. if it is ASM_OPERANDS),
4524 if (GET_MODE (XEXP (x, 0)) == VOIDmode)
4527 /* If operand is something known to be positive, ignore the ABS. */
4528 if (GET_CODE (XEXP (x, 0)) == FFS || GET_CODE (XEXP (x, 0)) == ABS
4529 || ((GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
4530 <= HOST_BITS_PER_WIDE_INT)
4531 && ((nonzero_bits (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
4532 & ((HOST_WIDE_INT) 1
4533 << (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - 1)))
4537 /* If operand is known to be only -1 or 0, convert ABS to NEG. */
4538 if (num_sign_bit_copies (XEXP (x, 0), mode) == GET_MODE_BITSIZE (mode))
4539 return gen_rtx_NEG (mode, XEXP (x, 0));
4544 /* (ffs (*_extend <X>)) = (ffs <X>) */
4545 if (GET_CODE (XEXP (x, 0)) == SIGN_EXTEND
4546 || GET_CODE (XEXP (x, 0)) == ZERO_EXTEND)
4547 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4551 /* (float (sign_extend <X>)) = (float <X>). */
4552 if (GET_CODE (XEXP (x, 0)) == SIGN_EXTEND)
4553 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4561 /* If this is a shift by a constant amount, simplify it. */
4562 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
4563 return simplify_shift_const (x, code, mode, XEXP (x, 0),
4564 INTVAL (XEXP (x, 1)));
4566 #ifdef SHIFT_COUNT_TRUNCATED
4567 else if (SHIFT_COUNT_TRUNCATED && GET_CODE (XEXP (x, 1)) != REG)
4569 force_to_mode (XEXP (x, 1), GET_MODE (x),
4571 << exact_log2 (GET_MODE_BITSIZE (GET_MODE (x))))
4580 rtx op0 = XEXP (x, 0);
4581 rtx op1 = XEXP (x, 1);
4584 if (GET_CODE (op1) != PARALLEL)
4586 len = XVECLEN (op1, 0);
4588 && GET_CODE (XVECEXP (op1, 0, 0)) == CONST_INT
4589 && GET_CODE (op0) == VEC_CONCAT)
4591 int offset = INTVAL (XVECEXP (op1, 0, 0)) * GET_MODE_SIZE (GET_MODE (x));
4593 /* Try to find the element in the VEC_CONCAT. */
4596 if (GET_MODE (op0) == GET_MODE (x))
4598 if (GET_CODE (op0) == VEC_CONCAT)
4600 HOST_WIDE_INT op0_size = GET_MODE_SIZE (GET_MODE (XEXP (op0, 0)));
4601 if (op0_size < offset)
4602 op0 = XEXP (op0, 0);
4606 op0 = XEXP (op0, 1);
4624 /* Simplify X, an IF_THEN_ELSE expression. Return the new expression. */
4627 simplify_if_then_else (x)
4630 enum machine_mode mode = GET_MODE (x);
4631 rtx cond = XEXP (x, 0);
4632 rtx true_rtx = XEXP (x, 1);
4633 rtx false_rtx = XEXP (x, 2);
4634 enum rtx_code true_code = GET_CODE (cond);
4635 int comparison_p = GET_RTX_CLASS (true_code) == '<';
4638 enum rtx_code false_code;
4641 /* Simplify storing of the truth value. */
4642 if (comparison_p && true_rtx == const_true_rtx && false_rtx == const0_rtx)
4643 return gen_binary (true_code, mode, XEXP (cond, 0), XEXP (cond, 1));
4645 /* Also when the truth value has to be reversed. */
4647 && true_rtx == const0_rtx && false_rtx == const_true_rtx
4648 && (reversed = reversed_comparison (cond, mode, XEXP (cond, 0),
4652 /* Sometimes we can simplify the arm of an IF_THEN_ELSE if a register used
4653 in it is being compared against certain values. Get the true and false
4654 comparisons and see if that says anything about the value of each arm. */
4657 && ((false_code = combine_reversed_comparison_code (cond))
4659 && GET_CODE (XEXP (cond, 0)) == REG)
4662 rtx from = XEXP (cond, 0);
4663 rtx true_val = XEXP (cond, 1);
4664 rtx false_val = true_val;
4667 /* If FALSE_CODE is EQ, swap the codes and arms. */
4669 if (false_code == EQ)
4671 swapped = 1, true_code = EQ, false_code = NE;
4672 temp = true_rtx, true_rtx = false_rtx, false_rtx = temp;
4675 /* If we are comparing against zero and the expression being tested has
4676 only a single bit that might be nonzero, that is its value when it is
4677 not equal to zero. Similarly if it is known to be -1 or 0. */
4679 if (true_code == EQ && true_val == const0_rtx
4680 && exact_log2 (nzb = nonzero_bits (from, GET_MODE (from))) >= 0)
4681 false_code = EQ, false_val = GEN_INT (nzb);
4682 else if (true_code == EQ && true_val == const0_rtx
4683 && (num_sign_bit_copies (from, GET_MODE (from))
4684 == GET_MODE_BITSIZE (GET_MODE (from))))
4685 false_code = EQ, false_val = constm1_rtx;
4687 /* Now simplify an arm if we know the value of the register in the
4688 branch and it is used in the arm. Be careful due to the potential
4689 of locally-shared RTL. */
4691 if (reg_mentioned_p (from, true_rtx))
4692 true_rtx = subst (known_cond (copy_rtx (true_rtx), true_code,
4694 pc_rtx, pc_rtx, 0, 0);
4695 if (reg_mentioned_p (from, false_rtx))
4696 false_rtx = subst (known_cond (copy_rtx (false_rtx), false_code,
4698 pc_rtx, pc_rtx, 0, 0);
4700 SUBST (XEXP (x, 1), swapped ? false_rtx : true_rtx);
4701 SUBST (XEXP (x, 2), swapped ? true_rtx : false_rtx);
4703 true_rtx = XEXP (x, 1);
4704 false_rtx = XEXP (x, 2);
4705 true_code = GET_CODE (cond);
4708 /* If we have (if_then_else FOO (pc) (label_ref BAR)) and FOO can be
4709 reversed, do so to avoid needing two sets of patterns for
4710 subtract-and-branch insns. Similarly if we have a constant in the true
4711 arm, the false arm is the same as the first operand of the comparison, or
4712 the false arm is more complicated than the true arm. */
4715 && combine_reversed_comparison_code (cond) != UNKNOWN
4716 && (true_rtx == pc_rtx
4717 || (CONSTANT_P (true_rtx)
4718 && GET_CODE (false_rtx) != CONST_INT && false_rtx != pc_rtx)
4719 || true_rtx == const0_rtx
4720 || (GET_RTX_CLASS (GET_CODE (true_rtx)) == 'o'
4721 && GET_RTX_CLASS (GET_CODE (false_rtx)) != 'o')
4722 || (GET_CODE (true_rtx) == SUBREG
4723 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (true_rtx))) == 'o'
4724 && GET_RTX_CLASS (GET_CODE (false_rtx)) != 'o')
4725 || reg_mentioned_p (true_rtx, false_rtx)
4726 || rtx_equal_p (false_rtx, XEXP (cond, 0))))
4728 true_code = reversed_comparison_code (cond, NULL);
4730 reversed_comparison (cond, GET_MODE (cond), XEXP (cond, 0),
4733 SUBST (XEXP (x, 1), false_rtx);
4734 SUBST (XEXP (x, 2), true_rtx);
4736 temp = true_rtx, true_rtx = false_rtx, false_rtx = temp;
4739 /* It is possible that the conditional has been simplified out. */
4740 true_code = GET_CODE (cond);
4741 comparison_p = GET_RTX_CLASS (true_code) == '<';
4744 /* If the two arms are identical, we don't need the comparison. */
4746 if (rtx_equal_p (true_rtx, false_rtx) && ! side_effects_p (cond))
4749 /* Convert a == b ? b : a to "a". */
4750 if (true_code == EQ && ! side_effects_p (cond)
4751 && (! FLOAT_MODE_P (mode) || flag_unsafe_math_optimizations)
4752 && rtx_equal_p (XEXP (cond, 0), false_rtx)
4753 && rtx_equal_p (XEXP (cond, 1), true_rtx))
4755 else if (true_code == NE && ! side_effects_p (cond)
4756 && (! FLOAT_MODE_P (mode) || flag_unsafe_math_optimizations)
4757 && rtx_equal_p (XEXP (cond, 0), true_rtx)
4758 && rtx_equal_p (XEXP (cond, 1), false_rtx))
4761 /* Look for cases where we have (abs x) or (neg (abs X)). */
4763 if (GET_MODE_CLASS (mode) == MODE_INT
4764 && GET_CODE (false_rtx) == NEG
4765 && rtx_equal_p (true_rtx, XEXP (false_rtx, 0))
4767 && rtx_equal_p (true_rtx, XEXP (cond, 0))
4768 && ! side_effects_p (true_rtx))
4773 return simplify_gen_unary (ABS, mode, true_rtx, mode);
4777 simplify_gen_unary (NEG, mode,
4778 simplify_gen_unary (ABS, mode, true_rtx, mode),
4784 /* Look for MIN or MAX. */
4786 if ((! FLOAT_MODE_P (mode) || flag_unsafe_math_optimizations)
4788 && rtx_equal_p (XEXP (cond, 0), true_rtx)
4789 && rtx_equal_p (XEXP (cond, 1), false_rtx)
4790 && ! side_effects_p (cond))
4795 return gen_binary (SMAX, mode, true_rtx, false_rtx);
4798 return gen_binary (SMIN, mode, true_rtx, false_rtx);
4801 return gen_binary (UMAX, mode, true_rtx, false_rtx);
4804 return gen_binary (UMIN, mode, true_rtx, false_rtx);
4809 /* If we have (if_then_else COND (OP Z C1) Z) and OP is an identity when its
4810 second operand is zero, this can be done as (OP Z (mult COND C2)) where
4811 C2 = C1 * STORE_FLAG_VALUE. Similarly if OP has an outer ZERO_EXTEND or
4812 SIGN_EXTEND as long as Z is already extended (so we don't destroy it).
4813 We can do this kind of thing in some cases when STORE_FLAG_VALUE is
4814 neither 1 or -1, but it isn't worth checking for. */
4816 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
4817 && comparison_p && mode != VOIDmode && ! side_effects_p (x))
4819 rtx t = make_compound_operation (true_rtx, SET);
4820 rtx f = make_compound_operation (false_rtx, SET);
4821 rtx cond_op0 = XEXP (cond, 0);
4822 rtx cond_op1 = XEXP (cond, 1);
4823 enum rtx_code op = NIL, extend_op = NIL;
4824 enum machine_mode m = mode;
4825 rtx z = 0, c1 = NULL_RTX;
4827 if ((GET_CODE (t) == PLUS || GET_CODE (t) == MINUS
4828 || GET_CODE (t) == IOR || GET_CODE (t) == XOR
4829 || GET_CODE (t) == ASHIFT
4830 || GET_CODE (t) == LSHIFTRT || GET_CODE (t) == ASHIFTRT)
4831 && rtx_equal_p (XEXP (t, 0), f))
4832 c1 = XEXP (t, 1), op = GET_CODE (t), z = f;
4834 /* If an identity-zero op is commutative, check whether there
4835 would be a match if we swapped the operands. */
4836 else if ((GET_CODE (t) == PLUS || GET_CODE (t) == IOR
4837 || GET_CODE (t) == XOR)
4838 && rtx_equal_p (XEXP (t, 1), f))
4839 c1 = XEXP (t, 0), op = GET_CODE (t), z = f;
4840 else if (GET_CODE (t) == SIGN_EXTEND
4841 && (GET_CODE (XEXP (t, 0)) == PLUS
4842 || GET_CODE (XEXP (t, 0)) == MINUS
4843 || GET_CODE (XEXP (t, 0)) == IOR
4844 || GET_CODE (XEXP (t, 0)) == XOR
4845 || GET_CODE (XEXP (t, 0)) == ASHIFT
4846 || GET_CODE (XEXP (t, 0)) == LSHIFTRT
4847 || GET_CODE (XEXP (t, 0)) == ASHIFTRT)
4848 && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG
4849 && subreg_lowpart_p (XEXP (XEXP (t, 0), 0))
4850 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f)
4851 && (num_sign_bit_copies (f, GET_MODE (f))
4852 > (GET_MODE_BITSIZE (mode)
4853 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t, 0), 0))))))
4855 c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0));
4856 extend_op = SIGN_EXTEND;
4857 m = GET_MODE (XEXP (t, 0));
4859 else if (GET_CODE (t) == SIGN_EXTEND
4860 && (GET_CODE (XEXP (t, 0)) == PLUS
4861 || GET_CODE (XEXP (t, 0)) == IOR
4862 || GET_CODE (XEXP (t, 0)) == XOR)
4863 && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG
4864 && subreg_lowpart_p (XEXP (XEXP (t, 0), 1))
4865 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f)
4866 && (num_sign_bit_copies (f, GET_MODE (f))
4867 > (GET_MODE_BITSIZE (mode)
4868 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t, 0), 1))))))
4870 c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0));
4871 extend_op = SIGN_EXTEND;
4872 m = GET_MODE (XEXP (t, 0));
4874 else if (GET_CODE (t) == ZERO_EXTEND
4875 && (GET_CODE (XEXP (t, 0)) == PLUS
4876 || GET_CODE (XEXP (t, 0)) == MINUS
4877 || GET_CODE (XEXP (t, 0)) == IOR
4878 || GET_CODE (XEXP (t, 0)) == XOR
4879 || GET_CODE (XEXP (t, 0)) == ASHIFT
4880 || GET_CODE (XEXP (t, 0)) == LSHIFTRT
4881 || GET_CODE (XEXP (t, 0)) == ASHIFTRT)
4882 && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG
4883 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4884 && subreg_lowpart_p (XEXP (XEXP (t, 0), 0))
4885 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f)
4886 && ((nonzero_bits (f, GET_MODE (f))
4887 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t, 0), 0))))
4890 c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0));
4891 extend_op = ZERO_EXTEND;
4892 m = GET_MODE (XEXP (t, 0));
4894 else if (GET_CODE (t) == ZERO_EXTEND
4895 && (GET_CODE (XEXP (t, 0)) == PLUS
4896 || GET_CODE (XEXP (t, 0)) == IOR
4897 || GET_CODE (XEXP (t, 0)) == XOR)
4898 && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG
4899 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4900 && subreg_lowpart_p (XEXP (XEXP (t, 0), 1))
4901 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f)
4902 && ((nonzero_bits (f, GET_MODE (f))
4903 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t, 0), 1))))
4906 c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0));
4907 extend_op = ZERO_EXTEND;
4908 m = GET_MODE (XEXP (t, 0));
4913 temp = subst (gen_binary (true_code, m, cond_op0, cond_op1),
4914 pc_rtx, pc_rtx, 0, 0);
4915 temp = gen_binary (MULT, m, temp,
4916 gen_binary (MULT, m, c1, const_true_rtx));
4917 temp = subst (temp, pc_rtx, pc_rtx, 0, 0);
4918 temp = gen_binary (op, m, gen_lowpart_for_combine (m, z), temp);
4920 if (extend_op != NIL)
4921 temp = simplify_gen_unary (extend_op, mode, temp, m);
4927 /* If we have (if_then_else (ne A 0) C1 0) and either A is known to be 0 or
4928 1 and C1 is a single bit or A is known to be 0 or -1 and C1 is the
4929 negation of a single bit, we can convert this operation to a shift. We
4930 can actually do this more generally, but it doesn't seem worth it. */
4932 if (true_code == NE && XEXP (cond, 1) == const0_rtx
4933 && false_rtx == const0_rtx && GET_CODE (true_rtx) == CONST_INT
4934 && ((1 == nonzero_bits (XEXP (cond, 0), mode)
4935 && (i = exact_log2 (INTVAL (true_rtx))) >= 0)
4936 || ((num_sign_bit_copies (XEXP (cond, 0), mode)
4937 == GET_MODE_BITSIZE (mode))
4938 && (i = exact_log2 (-INTVAL (true_rtx))) >= 0)))
4940 simplify_shift_const (NULL_RTX, ASHIFT, mode,
4941 gen_lowpart_for_combine (mode, XEXP (cond, 0)), i);
4946 /* Simplify X, a SET expression. Return the new expression. */
4952 rtx src = SET_SRC (x);
4953 rtx dest = SET_DEST (x);
4954 enum machine_mode mode
4955 = GET_MODE (src) != VOIDmode ? GET_MODE (src) : GET_MODE (dest);
4959 /* (set (pc) (return)) gets written as (return). */
4960 if (GET_CODE (dest) == PC && GET_CODE (src) == RETURN)
4963 /* Now that we know for sure which bits of SRC we are using, see if we can
4964 simplify the expression for the object knowing that we only need the
4967 if (GET_MODE_CLASS (mode) == MODE_INT)
4969 src = force_to_mode (src, mode, ~(HOST_WIDE_INT) 0, NULL_RTX, 0);
4970 SUBST (SET_SRC (x), src);
4973 /* If we are setting CC0 or if the source is a COMPARE, look for the use of
4974 the comparison result and try to simplify it unless we already have used
4975 undobuf.other_insn. */
4976 if ((GET_CODE (src) == COMPARE
4981 && (cc_use = find_single_use (dest, subst_insn, &other_insn)) != 0
4982 && (undobuf.other_insn == 0 || other_insn == undobuf.other_insn)
4983 && GET_RTX_CLASS (GET_CODE (*cc_use)) == '<'
4984 && rtx_equal_p (XEXP (*cc_use, 0), dest))
4986 enum rtx_code old_code = GET_CODE (*cc_use);
4987 enum rtx_code new_code;
4989 int other_changed = 0;
4990 enum machine_mode compare_mode = GET_MODE (dest);
4992 if (GET_CODE (src) == COMPARE)
4993 op0 = XEXP (src, 0), op1 = XEXP (src, 1);
4995 op0 = src, op1 = const0_rtx;
4997 /* Simplify our comparison, if possible. */
4998 new_code = simplify_comparison (old_code, &op0, &op1);
5000 #ifdef EXTRA_CC_MODES
5001 /* If this machine has CC modes other than CCmode, check to see if we
5002 need to use a different CC mode here. */
5003 compare_mode = SELECT_CC_MODE (new_code, op0, op1);
5004 #endif /* EXTRA_CC_MODES */
5006 #if !defined (HAVE_cc0) && defined (EXTRA_CC_MODES)
5007 /* If the mode changed, we have to change SET_DEST, the mode in the
5008 compare, and the mode in the place SET_DEST is used. If SET_DEST is
5009 a hard register, just build new versions with the proper mode. If it
5010 is a pseudo, we lose unless it is only time we set the pseudo, in
5011 which case we can safely change its mode. */
5012 if (compare_mode != GET_MODE (dest))
5014 unsigned int regno = REGNO (dest);
5015 rtx new_dest = gen_rtx_REG (compare_mode, regno);
5017 if (regno < FIRST_PSEUDO_REGISTER
5018 || (REG_N_SETS (regno) == 1 && ! REG_USERVAR_P (dest)))
5020 if (regno >= FIRST_PSEUDO_REGISTER)
5021 SUBST (regno_reg_rtx[regno], new_dest);
5023 SUBST (SET_DEST (x), new_dest);
5024 SUBST (XEXP (*cc_use, 0), new_dest);
5032 /* If the code changed, we have to build a new comparison in
5033 undobuf.other_insn. */
5034 if (new_code != old_code)
5036 unsigned HOST_WIDE_INT mask;
5038 SUBST (*cc_use, gen_rtx_fmt_ee (new_code, GET_MODE (*cc_use),
5041 /* If the only change we made was to change an EQ into an NE or
5042 vice versa, OP0 has only one bit that might be nonzero, and OP1
5043 is zero, check if changing the user of the condition code will
5044 produce a valid insn. If it won't, we can keep the original code
5045 in that insn by surrounding our operation with an XOR. */
5047 if (((old_code == NE && new_code == EQ)
5048 || (old_code == EQ && new_code == NE))
5049 && ! other_changed && op1 == const0_rtx
5050 && GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
5051 && exact_log2 (mask = nonzero_bits (op0, GET_MODE (op0))) >= 0)
5053 rtx pat = PATTERN (other_insn), note = 0;
5055 if ((recog_for_combine (&pat, other_insn, ¬e) < 0
5056 && ! check_asm_operands (pat)))
5058 PUT_CODE (*cc_use, old_code);
5061 op0 = gen_binary (XOR, GET_MODE (op0), op0, GEN_INT (mask));
5069 undobuf.other_insn = other_insn;
5072 /* If we are now comparing against zero, change our source if
5073 needed. If we do not use cc0, we always have a COMPARE. */
5074 if (op1 == const0_rtx && dest == cc0_rtx)
5076 SUBST (SET_SRC (x), op0);
5082 /* Otherwise, if we didn't previously have a COMPARE in the
5083 correct mode, we need one. */
5084 if (GET_CODE (src) != COMPARE || GET_MODE (src) != compare_mode)
5086 SUBST (SET_SRC (x), gen_rtx_COMPARE (compare_mode, op0, op1));
5091 /* Otherwise, update the COMPARE if needed. */
5092 SUBST (XEXP (src, 0), op0);
5093 SUBST (XEXP (src, 1), op1);
5098 /* Get SET_SRC in a form where we have placed back any
5099 compound expressions. Then do the checks below. */
5100 src = make_compound_operation (src, SET);
5101 SUBST (SET_SRC (x), src);
5104 /* If we have (set x (subreg:m1 (op:m2 ...) 0)) with OP being some operation,
5105 and X being a REG or (subreg (reg)), we may be able to convert this to
5106 (set (subreg:m2 x) (op)).
5108 We can always do this if M1 is narrower than M2 because that means that
5109 we only care about the low bits of the result.
5111 However, on machines without WORD_REGISTER_OPERATIONS defined, we cannot
5112 perform a narrower operation than requested since the high-order bits will
5113 be undefined. On machine where it is defined, this transformation is safe
5114 as long as M1 and M2 have the same number of words. */
5116 if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src)
5117 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (src))) != 'o'
5118 && (((GET_MODE_SIZE (GET_MODE (src)) + (UNITS_PER_WORD - 1))
5120 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (src)))
5121 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD))
5122 #ifndef WORD_REGISTER_OPERATIONS
5123 && (GET_MODE_SIZE (GET_MODE (src))
5124 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (src))))
5126 #ifdef CLASS_CANNOT_CHANGE_MODE
5127 && ! (GET_CODE (dest) == REG && REGNO (dest) < FIRST_PSEUDO_REGISTER
5128 && (TEST_HARD_REG_BIT
5129 (reg_class_contents[(int) CLASS_CANNOT_CHANGE_MODE],
5131 && CLASS_CANNOT_CHANGE_MODE_P (GET_MODE (src),
5132 GET_MODE (SUBREG_REG (src))))
5134 && (GET_CODE (dest) == REG
5135 || (GET_CODE (dest) == SUBREG
5136 && GET_CODE (SUBREG_REG (dest)) == REG)))
5138 SUBST (SET_DEST (x),
5139 gen_lowpart_for_combine (GET_MODE (SUBREG_REG (src)),
5141 SUBST (SET_SRC (x), SUBREG_REG (src));
5143 src = SET_SRC (x), dest = SET_DEST (x);
5146 #ifdef LOAD_EXTEND_OP
5147 /* If we have (set FOO (subreg:M (mem:N BAR) 0)) with M wider than N, this
5148 would require a paradoxical subreg. Replace the subreg with a
5149 zero_extend to avoid the reload that would otherwise be required. */
5151 if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src)
5152 && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src))) != NIL
5153 && SUBREG_BYTE (src) == 0
5154 && (GET_MODE_SIZE (GET_MODE (src))
5155 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (src))))
5156 && GET_CODE (SUBREG_REG (src)) == MEM)
5159 gen_rtx (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src))),
5160 GET_MODE (src), SUBREG_REG (src)));
5166 /* If we don't have a conditional move, SET_SRC is an IF_THEN_ELSE, and we
5167 are comparing an item known to be 0 or -1 against 0, use a logical
5168 operation instead. Check for one of the arms being an IOR of the other
5169 arm with some value. We compute three terms to be IOR'ed together. In
5170 practice, at most two will be nonzero. Then we do the IOR's. */
5172 if (GET_CODE (dest) != PC
5173 && GET_CODE (src) == IF_THEN_ELSE
5174 && GET_MODE_CLASS (GET_MODE (src)) == MODE_INT
5175 && (GET_CODE (XEXP (src, 0)) == EQ || GET_CODE (XEXP (src, 0)) == NE)
5176 && XEXP (XEXP (src, 0), 1) == const0_rtx
5177 && GET_MODE (src) == GET_MODE (XEXP (XEXP (src, 0), 0))
5178 #ifdef HAVE_conditional_move
5179 && ! can_conditionally_move_p (GET_MODE (src))
5181 && (num_sign_bit_copies (XEXP (XEXP (src, 0), 0),
5182 GET_MODE (XEXP (XEXP (src, 0), 0)))
5183 == GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (src, 0), 0))))
5184 && ! side_effects_p (src))
5186 rtx true_rtx = (GET_CODE (XEXP (src, 0)) == NE
5187 ? XEXP (src, 1) : XEXP (src, 2));
5188 rtx false_rtx = (GET_CODE (XEXP (src, 0)) == NE
5189 ? XEXP (src, 2) : XEXP (src, 1));
5190 rtx term1 = const0_rtx, term2, term3;
5192 if (GET_CODE (true_rtx) == IOR
5193 && rtx_equal_p (XEXP (true_rtx, 0), false_rtx))
5194 term1 = false_rtx, true_rtx = XEXP(true_rtx, 1), false_rtx = const0_rtx;
5195 else if (GET_CODE (true_rtx) == IOR
5196 && rtx_equal_p (XEXP (true_rtx, 1), false_rtx))
5197 term1 = false_rtx, true_rtx = XEXP(true_rtx, 0), false_rtx = const0_rtx;
5198 else if (GET_CODE (false_rtx) == IOR
5199 && rtx_equal_p (XEXP (false_rtx, 0), true_rtx))
5200 term1 = true_rtx, false_rtx = XEXP(false_rtx, 1), true_rtx = const0_rtx;
5201 else if (GET_CODE (false_rtx) == IOR
5202 && rtx_equal_p (XEXP (false_rtx, 1), true_rtx))
5203 term1 = true_rtx, false_rtx = XEXP(false_rtx, 0), true_rtx = const0_rtx;
5205 term2 = gen_binary (AND, GET_MODE (src),
5206 XEXP (XEXP (src, 0), 0), true_rtx);
5207 term3 = gen_binary (AND, GET_MODE (src),
5208 simplify_gen_unary (NOT, GET_MODE (src),
5209 XEXP (XEXP (src, 0), 0),
5214 gen_binary (IOR, GET_MODE (src),
5215 gen_binary (IOR, GET_MODE (src), term1, term2),
5221 /* If either SRC or DEST is a CLOBBER of (const_int 0), make this
5222 whole thing fail. */
5223 if (GET_CODE (src) == CLOBBER && XEXP (src, 0) == const0_rtx)
5225 else if (GET_CODE (dest) == CLOBBER && XEXP (dest, 0) == const0_rtx)
5228 /* Convert this into a field assignment operation, if possible. */
5229 return make_field_assignment (x);
5232 /* Simplify, X, and AND, IOR, or XOR operation, and return the simplified
5233 result. LAST is nonzero if this is the last retry. */
5236 simplify_logical (x, last)
5240 enum machine_mode mode = GET_MODE (x);
5241 rtx op0 = XEXP (x, 0);
5242 rtx op1 = XEXP (x, 1);
5245 switch (GET_CODE (x))
5248 /* Convert (A ^ B) & A to A & (~B) since the latter is often a single
5249 insn (and may simplify more). */
5250 if (GET_CODE (op0) == XOR
5251 && rtx_equal_p (XEXP (op0, 0), op1)
5252 && ! side_effects_p (op1))
5253 x = gen_binary (AND, mode,
5254 simplify_gen_unary (NOT, mode, XEXP (op0, 1), mode),
5257 if (GET_CODE (op0) == XOR
5258 && rtx_equal_p (XEXP (op0, 1), op1)
5259 && ! side_effects_p (op1))
5260 x = gen_binary (AND, mode,
5261 simplify_gen_unary (NOT, mode, XEXP (op0, 0), mode),
5264 /* Similarly for (~(A ^ B)) & A. */
5265 if (GET_CODE (op0) == NOT
5266 && GET_CODE (XEXP (op0, 0)) == XOR
5267 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), op1)
5268 && ! side_effects_p (op1))
5269 x = gen_binary (AND, mode, XEXP (XEXP (op0, 0), 1), op1);
5271 if (GET_CODE (op0) == NOT
5272 && GET_CODE (XEXP (op0, 0)) == XOR
5273 && rtx_equal_p (XEXP (XEXP (op0, 0), 1), op1)
5274 && ! side_effects_p (op1))
5275 x = gen_binary (AND, mode, XEXP (XEXP (op0, 0), 0), op1);
5277 /* We can call simplify_and_const_int only if we don't lose
5278 any (sign) bits when converting INTVAL (op1) to
5279 "unsigned HOST_WIDE_INT". */
5280 if (GET_CODE (op1) == CONST_INT
5281 && (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5282 || INTVAL (op1) > 0))
5284 x = simplify_and_const_int (x, mode, op0, INTVAL (op1));
5286 /* If we have (ior (and (X C1) C2)) and the next restart would be
5287 the last, simplify this by making C1 as small as possible
5290 && GET_CODE (x) == IOR && GET_CODE (op0) == AND
5291 && GET_CODE (XEXP (op0, 1)) == CONST_INT
5292 && GET_CODE (op1) == CONST_INT)
5293 return gen_binary (IOR, mode,
5294 gen_binary (AND, mode, XEXP (op0, 0),
5295 GEN_INT (INTVAL (XEXP (op0, 1))
5296 & ~INTVAL (op1))), op1);
5298 if (GET_CODE (x) != AND)
5301 if (GET_RTX_CLASS (GET_CODE (x)) == 'c'
5302 || GET_RTX_CLASS (GET_CODE (x)) == '2')
5303 op0 = XEXP (x, 0), op1 = XEXP (x, 1);
5306 /* Convert (A | B) & A to A. */
5307 if (GET_CODE (op0) == IOR
5308 && (rtx_equal_p (XEXP (op0, 0), op1)
5309 || rtx_equal_p (XEXP (op0, 1), op1))
5310 && ! side_effects_p (XEXP (op0, 0))
5311 && ! side_effects_p (XEXP (op0, 1)))
5314 /* In the following group of tests (and those in case IOR below),
5315 we start with some combination of logical operations and apply
5316 the distributive law followed by the inverse distributive law.
5317 Most of the time, this results in no change. However, if some of
5318 the operands are the same or inverses of each other, simplifications
5321 For example, (and (ior A B) (not B)) can occur as the result of
5322 expanding a bit field assignment. When we apply the distributive
5323 law to this, we get (ior (and (A (not B))) (and (B (not B)))),
5324 which then simplifies to (and (A (not B))).
5326 If we have (and (ior A B) C), apply the distributive law and then
5327 the inverse distributive law to see if things simplify. */
5329 if (GET_CODE (op0) == IOR || GET_CODE (op0) == XOR)
5331 x = apply_distributive_law
5332 (gen_binary (GET_CODE (op0), mode,
5333 gen_binary (AND, mode, XEXP (op0, 0), op1),
5334 gen_binary (AND, mode, XEXP (op0, 1),
5336 if (GET_CODE (x) != AND)
5340 if (GET_CODE (op1) == IOR || GET_CODE (op1) == XOR)
5341 return apply_distributive_law
5342 (gen_binary (GET_CODE (op1), mode,
5343 gen_binary (AND, mode, XEXP (op1, 0), op0),
5344 gen_binary (AND, mode, XEXP (op1, 1),
5347 /* Similarly, taking advantage of the fact that
5348 (and (not A) (xor B C)) == (xor (ior A B) (ior A C)) */
5350 if (GET_CODE (op0) == NOT && GET_CODE (op1) == XOR)
5351 return apply_distributive_law
5352 (gen_binary (XOR, mode,
5353 gen_binary (IOR, mode, XEXP (op0, 0), XEXP (op1, 0)),
5354 gen_binary (IOR, mode, copy_rtx (XEXP (op0, 0)),
5357 else if (GET_CODE (op1) == NOT && GET_CODE (op0) == XOR)
5358 return apply_distributive_law
5359 (gen_binary (XOR, mode,
5360 gen_binary (IOR, mode, XEXP (op1, 0), XEXP (op0, 0)),
5361 gen_binary (IOR, mode, copy_rtx (XEXP (op1, 0)), XEXP (op0, 1))));
5365 /* (ior A C) is C if all bits of A that might be nonzero are on in C. */
5366 if (GET_CODE (op1) == CONST_INT
5367 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5368 && (nonzero_bits (op0, mode) & ~INTVAL (op1)) == 0)
5371 /* Convert (A & B) | A to A. */
5372 if (GET_CODE (op0) == AND
5373 && (rtx_equal_p (XEXP (op0, 0), op1)
5374 || rtx_equal_p (XEXP (op0, 1), op1))
5375 && ! side_effects_p (XEXP (op0, 0))
5376 && ! side_effects_p (XEXP (op0, 1)))
5379 /* If we have (ior (and A B) C), apply the distributive law and then
5380 the inverse distributive law to see if things simplify. */
5382 if (GET_CODE (op0) == AND)
5384 x = apply_distributive_law
5385 (gen_binary (AND, mode,
5386 gen_binary (IOR, mode, XEXP (op0, 0), op1),
5387 gen_binary (IOR, mode, XEXP (op0, 1),
5390 if (GET_CODE (x) != IOR)
5394 if (GET_CODE (op1) == AND)
5396 x = apply_distributive_law
5397 (gen_binary (AND, mode,
5398 gen_binary (IOR, mode, XEXP (op1, 0), op0),
5399 gen_binary (IOR, mode, XEXP (op1, 1),
5402 if (GET_CODE (x) != IOR)
5406 /* Convert (ior (ashift A CX) (lshiftrt A CY)) where CX+CY equals the
5407 mode size to (rotate A CX). */
5409 if (((GET_CODE (op0) == ASHIFT && GET_CODE (op1) == LSHIFTRT)
5410 || (GET_CODE (op1) == ASHIFT && GET_CODE (op0) == LSHIFTRT))
5411 && rtx_equal_p (XEXP (op0, 0), XEXP (op1, 0))
5412 && GET_CODE (XEXP (op0, 1)) == CONST_INT
5413 && GET_CODE (XEXP (op1, 1)) == CONST_INT
5414 && (INTVAL (XEXP (op0, 1)) + INTVAL (XEXP (op1, 1))
5415 == GET_MODE_BITSIZE (mode)))
5416 return gen_rtx_ROTATE (mode, XEXP (op0, 0),
5417 (GET_CODE (op0) == ASHIFT
5418 ? XEXP (op0, 1) : XEXP (op1, 1)));
5420 /* If OP0 is (ashiftrt (plus ...) C), it might actually be
5421 a (sign_extend (plus ...)). If so, OP1 is a CONST_INT, and the PLUS
5422 does not affect any of the bits in OP1, it can really be done
5423 as a PLUS and we can associate. We do this by seeing if OP1
5424 can be safely shifted left C bits. */
5425 if (GET_CODE (op1) == CONST_INT && GET_CODE (op0) == ASHIFTRT
5426 && GET_CODE (XEXP (op0, 0)) == PLUS
5427 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
5428 && GET_CODE (XEXP (op0, 1)) == CONST_INT
5429 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT)
5431 int count = INTVAL (XEXP (op0, 1));
5432 HOST_WIDE_INT mask = INTVAL (op1) << count;
5434 if (mask >> count == INTVAL (op1)
5435 && (mask & nonzero_bits (XEXP (op0, 0), mode)) == 0)
5437 SUBST (XEXP (XEXP (op0, 0), 1),
5438 GEN_INT (INTVAL (XEXP (XEXP (op0, 0), 1)) | mask));
5445 /* If we are XORing two things that have no bits in common,
5446 convert them into an IOR. This helps to detect rotation encoded
5447 using those methods and possibly other simplifications. */
5449 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5450 && (nonzero_bits (op0, mode)
5451 & nonzero_bits (op1, mode)) == 0)
5452 return (gen_binary (IOR, mode, op0, op1));
5454 /* Convert (XOR (NOT x) (NOT y)) to (XOR x y).
5455 Also convert (XOR (NOT x) y) to (NOT (XOR x y)), similarly for
5458 int num_negated = 0;
5460 if (GET_CODE (op0) == NOT)
5461 num_negated++, op0 = XEXP (op0, 0);
5462 if (GET_CODE (op1) == NOT)
5463 num_negated++, op1 = XEXP (op1, 0);
5465 if (num_negated == 2)
5467 SUBST (XEXP (x, 0), op0);
5468 SUBST (XEXP (x, 1), op1);
5470 else if (num_negated == 1)
5472 simplify_gen_unary (NOT, mode, gen_binary (XOR, mode, op0, op1),
5476 /* Convert (xor (and A B) B) to (and (not A) B). The latter may
5477 correspond to a machine insn or result in further simplifications
5478 if B is a constant. */
5480 if (GET_CODE (op0) == AND
5481 && rtx_equal_p (XEXP (op0, 1), op1)
5482 && ! side_effects_p (op1))
5483 return gen_binary (AND, mode,
5484 simplify_gen_unary (NOT, mode, XEXP (op0, 0), mode),
5487 else if (GET_CODE (op0) == AND
5488 && rtx_equal_p (XEXP (op0, 0), op1)
5489 && ! side_effects_p (op1))
5490 return gen_binary (AND, mode,
5491 simplify_gen_unary (NOT, mode, XEXP (op0, 1), mode),
5494 /* (xor (comparison foo bar) (const_int 1)) can become the reversed
5495 comparison if STORE_FLAG_VALUE is 1. */
5496 if (STORE_FLAG_VALUE == 1
5497 && op1 == const1_rtx
5498 && GET_RTX_CLASS (GET_CODE (op0)) == '<'
5499 && (reversed = reversed_comparison (op0, mode, XEXP (op0, 0),
5503 /* (lshiftrt foo C) where C is the number of bits in FOO minus 1
5504 is (lt foo (const_int 0)), so we can perform the above
5505 simplification if STORE_FLAG_VALUE is 1. */
5507 if (STORE_FLAG_VALUE == 1
5508 && op1 == const1_rtx
5509 && GET_CODE (op0) == LSHIFTRT
5510 && GET_CODE (XEXP (op0, 1)) == CONST_INT
5511 && INTVAL (XEXP (op0, 1)) == GET_MODE_BITSIZE (mode) - 1)
5512 return gen_rtx_GE (mode, XEXP (op0, 0), const0_rtx);
5514 /* (xor (comparison foo bar) (const_int sign-bit))
5515 when STORE_FLAG_VALUE is the sign bit. */
5516 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5517 && ((STORE_FLAG_VALUE & GET_MODE_MASK (mode))
5518 == (unsigned HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (mode) - 1))
5519 && op1 == const_true_rtx
5520 && GET_RTX_CLASS (GET_CODE (op0)) == '<'
5521 && (reversed = reversed_comparison (op0, mode, XEXP (op0, 0),
5534 /* We consider ZERO_EXTRACT, SIGN_EXTRACT, and SIGN_EXTEND as "compound
5535 operations" because they can be replaced with two more basic operations.
5536 ZERO_EXTEND is also considered "compound" because it can be replaced with
5537 an AND operation, which is simpler, though only one operation.
5539 The function expand_compound_operation is called with an rtx expression
5540 and will convert it to the appropriate shifts and AND operations,
5541 simplifying at each stage.
5543 The function make_compound_operation is called to convert an expression
5544 consisting of shifts and ANDs into the equivalent compound expression.
5545 It is the inverse of this function, loosely speaking. */
5548 expand_compound_operation (x)
5551 unsigned HOST_WIDE_INT pos = 0, len;
5553 unsigned int modewidth;
5556 switch (GET_CODE (x))
5561 /* We can't necessarily use a const_int for a multiword mode;
5562 it depends on implicitly extending the value.
5563 Since we don't know the right way to extend it,
5564 we can't tell whether the implicit way is right.
5566 Even for a mode that is no wider than a const_int,
5567 we can't win, because we need to sign extend one of its bits through
5568 the rest of it, and we don't know which bit. */
5569 if (GET_CODE (XEXP (x, 0)) == CONST_INT)
5572 /* Return if (subreg:MODE FROM 0) is not a safe replacement for
5573 (zero_extend:MODE FROM) or (sign_extend:MODE FROM). It is for any MEM
5574 because (SUBREG (MEM...)) is guaranteed to cause the MEM to be
5575 reloaded. If not for that, MEM's would very rarely be safe.
5577 Reject MODEs bigger than a word, because we might not be able
5578 to reference a two-register group starting with an arbitrary register
5579 (and currently gen_lowpart might crash for a SUBREG). */
5581 if (GET_MODE_SIZE (GET_MODE (XEXP (x, 0))) > UNITS_PER_WORD)
5584 len = GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)));
5585 /* If the inner object has VOIDmode (the only way this can happen
5586 is if it is a ASM_OPERANDS), we can't do anything since we don't
5587 know how much masking to do. */
5596 /* If the operand is a CLOBBER, just return it. */
5597 if (GET_CODE (XEXP (x, 0)) == CLOBBER)
5600 if (GET_CODE (XEXP (x, 1)) != CONST_INT
5601 || GET_CODE (XEXP (x, 2)) != CONST_INT
5602 || GET_MODE (XEXP (x, 0)) == VOIDmode)
5605 len = INTVAL (XEXP (x, 1));
5606 pos = INTVAL (XEXP (x, 2));
5608 /* If this goes outside the object being extracted, replace the object
5609 with a (use (mem ...)) construct that only combine understands
5610 and is used only for this purpose. */
5611 if (len + pos > GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))))
5612 SUBST (XEXP (x, 0), gen_rtx_USE (GET_MODE (x), XEXP (x, 0)));
5614 if (BITS_BIG_ENDIAN)
5615 pos = GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - len - pos;
5622 /* Convert sign extension to zero extension, if we know that the high
5623 bit is not set, as this is easier to optimize. It will be converted
5624 back to cheaper alternative in make_extraction. */
5625 if (GET_CODE (x) == SIGN_EXTEND
5626 && (GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
5627 && ((nonzero_bits (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
5628 & ~(((unsigned HOST_WIDE_INT)
5629 GET_MODE_MASK (GET_MODE (XEXP (x, 0))))
5633 rtx temp = gen_rtx_ZERO_EXTEND (GET_MODE (x), XEXP (x, 0));
5634 return expand_compound_operation (temp);
5637 /* We can optimize some special cases of ZERO_EXTEND. */
5638 if (GET_CODE (x) == ZERO_EXTEND)
5640 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI if we
5641 know that the last value didn't have any inappropriate bits
5643 if (GET_CODE (XEXP (x, 0)) == TRUNCATE
5644 && GET_MODE (XEXP (XEXP (x, 0), 0)) == GET_MODE (x)
5645 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
5646 && (nonzero_bits (XEXP (XEXP (x, 0), 0), GET_MODE (x))
5647 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5648 return XEXP (XEXP (x, 0), 0);
5650 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
5651 if (GET_CODE (XEXP (x, 0)) == SUBREG
5652 && GET_MODE (SUBREG_REG (XEXP (x, 0))) == GET_MODE (x)
5653 && subreg_lowpart_p (XEXP (x, 0))
5654 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
5655 && (nonzero_bits (SUBREG_REG (XEXP (x, 0)), GET_MODE (x))
5656 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5657 return SUBREG_REG (XEXP (x, 0));
5659 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI when foo
5660 is a comparison and STORE_FLAG_VALUE permits. This is like
5661 the first case, but it works even when GET_MODE (x) is larger
5662 than HOST_WIDE_INT. */
5663 if (GET_CODE (XEXP (x, 0)) == TRUNCATE
5664 && GET_MODE (XEXP (XEXP (x, 0), 0)) == GET_MODE (x)
5665 && GET_RTX_CLASS (GET_CODE (XEXP (XEXP (x, 0), 0))) == '<'
5666 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
5667 <= HOST_BITS_PER_WIDE_INT)
5668 && ((HOST_WIDE_INT) STORE_FLAG_VALUE
5669 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5670 return XEXP (XEXP (x, 0), 0);
5672 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
5673 if (GET_CODE (XEXP (x, 0)) == SUBREG
5674 && GET_MODE (SUBREG_REG (XEXP (x, 0))) == GET_MODE (x)
5675 && subreg_lowpart_p (XEXP (x, 0))
5676 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 0)))) == '<'
5677 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
5678 <= HOST_BITS_PER_WIDE_INT)
5679 && ((HOST_WIDE_INT) STORE_FLAG_VALUE
5680 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5681 return SUBREG_REG (XEXP (x, 0));
5685 /* If we reach here, we want to return a pair of shifts. The inner
5686 shift is a left shift of BITSIZE - POS - LEN bits. The outer
5687 shift is a right shift of BITSIZE - LEN bits. It is arithmetic or
5688 logical depending on the value of UNSIGNEDP.
5690 If this was a ZERO_EXTEND or ZERO_EXTRACT, this pair of shifts will be
5691 converted into an AND of a shift.
5693 We must check for the case where the left shift would have a negative
5694 count. This can happen in a case like (x >> 31) & 255 on machines
5695 that can't shift by a constant. On those machines, we would first
5696 combine the shift with the AND to produce a variable-position
5697 extraction. Then the constant of 31 would be substituted in to produce
5698 a such a position. */
5700 modewidth = GET_MODE_BITSIZE (GET_MODE (x));
5701 if (modewidth + len >= pos)
5702 tem = simplify_shift_const (NULL_RTX, unsignedp ? LSHIFTRT : ASHIFTRT,
5704 simplify_shift_const (NULL_RTX, ASHIFT,
5707 modewidth - pos - len),
5710 else if (unsignedp && len < HOST_BITS_PER_WIDE_INT)
5711 tem = simplify_and_const_int (NULL_RTX, GET_MODE (x),
5712 simplify_shift_const (NULL_RTX, LSHIFTRT,
5715 ((HOST_WIDE_INT) 1 << len) - 1);
5717 /* Any other cases we can't handle. */
5720 /* If we couldn't do this for some reason, return the original
5722 if (GET_CODE (tem) == CLOBBER)
5728 /* X is a SET which contains an assignment of one object into
5729 a part of another (such as a bit-field assignment, STRICT_LOW_PART,
5730 or certain SUBREGS). If possible, convert it into a series of
5733 We half-heartedly support variable positions, but do not at all
5734 support variable lengths. */
5737 expand_field_assignment (x)
5741 rtx pos; /* Always counts from low bit. */
5744 enum machine_mode compute_mode;
5746 /* Loop until we find something we can't simplify. */
5749 if (GET_CODE (SET_DEST (x)) == STRICT_LOW_PART
5750 && GET_CODE (XEXP (SET_DEST (x), 0)) == SUBREG)
5752 inner = SUBREG_REG (XEXP (SET_DEST (x), 0));
5753 len = GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0)));
5754 pos = GEN_INT (subreg_lsb (XEXP (SET_DEST (x), 0)));
5756 else if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
5757 && GET_CODE (XEXP (SET_DEST (x), 1)) == CONST_INT)
5759 inner = XEXP (SET_DEST (x), 0);
5760 len = INTVAL (XEXP (SET_DEST (x), 1));
5761 pos = XEXP (SET_DEST (x), 2);
5763 /* If the position is constant and spans the width of INNER,
5764 surround INNER with a USE to indicate this. */
5765 if (GET_CODE (pos) == CONST_INT
5766 && INTVAL (pos) + len > GET_MODE_BITSIZE (GET_MODE (inner)))
5767 inner = gen_rtx_USE (GET_MODE (SET_DEST (x)), inner);
5769 if (BITS_BIG_ENDIAN)
5771 if (GET_CODE (pos) == CONST_INT)
5772 pos = GEN_INT (GET_MODE_BITSIZE (GET_MODE (inner)) - len
5774 else if (GET_CODE (pos) == MINUS
5775 && GET_CODE (XEXP (pos, 1)) == CONST_INT
5776 && (INTVAL (XEXP (pos, 1))
5777 == GET_MODE_BITSIZE (GET_MODE (inner)) - len))
5778 /* If position is ADJUST - X, new position is X. */
5779 pos = XEXP (pos, 0);
5781 pos = gen_binary (MINUS, GET_MODE (pos),
5782 GEN_INT (GET_MODE_BITSIZE (GET_MODE (inner))
5788 /* A SUBREG between two modes that occupy the same numbers of words
5789 can be done by moving the SUBREG to the source. */
5790 else if (GET_CODE (SET_DEST (x)) == SUBREG
5791 /* We need SUBREGs to compute nonzero_bits properly. */
5792 && nonzero_sign_valid
5793 && (((GET_MODE_SIZE (GET_MODE (SET_DEST (x)))
5794 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
5795 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x))))
5796 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)))
5798 x = gen_rtx_SET (VOIDmode, SUBREG_REG (SET_DEST (x)),
5799 gen_lowpart_for_combine
5800 (GET_MODE (SUBREG_REG (SET_DEST (x))),
5807 while (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
5808 inner = SUBREG_REG (inner);
5810 compute_mode = GET_MODE (inner);
5812 /* Don't attempt bitwise arithmetic on non-integral modes. */
5813 if (! INTEGRAL_MODE_P (compute_mode))
5815 enum machine_mode imode;
5817 /* Something is probably seriously wrong if this matches. */
5818 if (! FLOAT_MODE_P (compute_mode))
5821 /* Try to find an integral mode to pun with. */
5822 imode = mode_for_size (GET_MODE_BITSIZE (compute_mode), MODE_INT, 0);
5823 if (imode == BLKmode)
5826 compute_mode = imode;
5827 inner = gen_lowpart_for_combine (imode, inner);
5830 /* Compute a mask of LEN bits, if we can do this on the host machine. */
5831 if (len < HOST_BITS_PER_WIDE_INT)
5832 mask = GEN_INT (((HOST_WIDE_INT) 1 << len) - 1);
5836 /* Now compute the equivalent expression. Make a copy of INNER
5837 for the SET_DEST in case it is a MEM into which we will substitute;
5838 we don't want shared RTL in that case. */
5840 (VOIDmode, copy_rtx (inner),
5841 gen_binary (IOR, compute_mode,
5842 gen_binary (AND, compute_mode,
5843 simplify_gen_unary (NOT, compute_mode,
5849 gen_binary (ASHIFT, compute_mode,
5850 gen_binary (AND, compute_mode,
5851 gen_lowpart_for_combine
5852 (compute_mode, SET_SRC (x)),
5860 /* Return an RTX for a reference to LEN bits of INNER. If POS_RTX is nonzero,
5861 it is an RTX that represents a variable starting position; otherwise,
5862 POS is the (constant) starting bit position (counted from the LSB).
5864 INNER may be a USE. This will occur when we started with a bitfield
5865 that went outside the boundary of the object in memory, which is
5866 allowed on most machines. To isolate this case, we produce a USE
5867 whose mode is wide enough and surround the MEM with it. The only
5868 code that understands the USE is this routine. If it is not removed,
5869 it will cause the resulting insn not to match.
5871 UNSIGNEDP is non-zero for an unsigned reference and zero for a
5874 IN_DEST is non-zero if this is a reference in the destination of a
5875 SET. This is used when a ZERO_ or SIGN_EXTRACT isn't needed. If non-zero,
5876 a STRICT_LOW_PART will be used, if zero, ZERO_EXTEND or SIGN_EXTEND will
5879 IN_COMPARE is non-zero if we are in a COMPARE. This means that a
5880 ZERO_EXTRACT should be built even for bits starting at bit 0.
5882 MODE is the desired mode of the result (if IN_DEST == 0).
5884 The result is an RTX for the extraction or NULL_RTX if the target
5888 make_extraction (mode, inner, pos, pos_rtx, len,
5889 unsignedp, in_dest, in_compare)
5890 enum machine_mode mode;
5894 unsigned HOST_WIDE_INT len;
5896 int in_dest, in_compare;
5898 /* This mode describes the size of the storage area
5899 to fetch the overall value from. Within that, we
5900 ignore the POS lowest bits, etc. */
5901 enum machine_mode is_mode = GET_MODE (inner);
5902 enum machine_mode inner_mode;
5903 enum machine_mode wanted_inner_mode = byte_mode;
5904 enum machine_mode wanted_inner_reg_mode = word_mode;
5905 enum machine_mode pos_mode = word_mode;
5906 enum machine_mode extraction_mode = word_mode;
5907 enum machine_mode tmode = mode_for_size (len, MODE_INT, 1);
5910 rtx orig_pos_rtx = pos_rtx;
5911 HOST_WIDE_INT orig_pos;
5913 /* Get some information about INNER and get the innermost object. */
5914 if (GET_CODE (inner) == USE)
5915 /* (use:SI (mem:QI foo)) stands for (mem:SI foo). */
5916 /* We don't need to adjust the position because we set up the USE
5917 to pretend that it was a full-word object. */
5918 spans_byte = 1, inner = XEXP (inner, 0);
5919 else if (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
5921 /* If going from (subreg:SI (mem:QI ...)) to (mem:QI ...),
5922 consider just the QI as the memory to extract from.
5923 The subreg adds or removes high bits; its mode is
5924 irrelevant to the meaning of this extraction,
5925 since POS and LEN count from the lsb. */
5926 if (GET_CODE (SUBREG_REG (inner)) == MEM)
5927 is_mode = GET_MODE (SUBREG_REG (inner));
5928 inner = SUBREG_REG (inner);
5931 inner_mode = GET_MODE (inner);
5933 if (pos_rtx && GET_CODE (pos_rtx) == CONST_INT)
5934 pos = INTVAL (pos_rtx), pos_rtx = 0;
5936 /* See if this can be done without an extraction. We never can if the
5937 width of the field is not the same as that of some integer mode. For
5938 registers, we can only avoid the extraction if the position is at the
5939 low-order bit and this is either not in the destination or we have the
5940 appropriate STRICT_LOW_PART operation available.
5942 For MEM, we can avoid an extract if the field starts on an appropriate
5943 boundary and we can change the mode of the memory reference. However,
5944 we cannot directly access the MEM if we have a USE and the underlying
5945 MEM is not TMODE. This combination means that MEM was being used in a
5946 context where bits outside its mode were being referenced; that is only
5947 valid in bit-field insns. */
5949 if (tmode != BLKmode
5950 && ! (spans_byte && inner_mode != tmode)
5951 && ((pos_rtx == 0 && (pos % BITS_PER_WORD) == 0
5952 && GET_CODE (inner) != MEM
5954 || (GET_CODE (inner) == REG
5955 && have_insn_for (STRICT_LOW_PART, tmode))))
5956 || (GET_CODE (inner) == MEM && pos_rtx == 0
5958 % (STRICT_ALIGNMENT ? GET_MODE_ALIGNMENT (tmode)
5959 : BITS_PER_UNIT)) == 0
5960 /* We can't do this if we are widening INNER_MODE (it
5961 may not be aligned, for one thing). */
5962 && GET_MODE_BITSIZE (inner_mode) >= GET_MODE_BITSIZE (tmode)
5963 && (inner_mode == tmode
5964 || (! mode_dependent_address_p (XEXP (inner, 0))
5965 && ! MEM_VOLATILE_P (inner))))))
5967 /* If INNER is a MEM, make a new MEM that encompasses just the desired
5968 field. If the original and current mode are the same, we need not
5969 adjust the offset. Otherwise, we do if bytes big endian.
5971 If INNER is not a MEM, get a piece consisting of just the field
5972 of interest (in this case POS % BITS_PER_WORD must be 0). */
5974 if (GET_CODE (inner) == MEM)
5976 HOST_WIDE_INT offset;
5978 /* POS counts from lsb, but make OFFSET count in memory order. */
5979 if (BYTES_BIG_ENDIAN)
5980 offset = (GET_MODE_BITSIZE (is_mode) - len - pos) / BITS_PER_UNIT;
5982 offset = pos / BITS_PER_UNIT;
5984 new = adjust_address_nv (inner, tmode, offset);
5986 else if (GET_CODE (inner) == REG)
5988 /* We can't call gen_lowpart_for_combine here since we always want
5989 a SUBREG and it would sometimes return a new hard register. */
5990 if (tmode != inner_mode)
5992 HOST_WIDE_INT final_word = pos / BITS_PER_WORD;
5994 if (WORDS_BIG_ENDIAN
5995 && GET_MODE_SIZE (inner_mode) > UNITS_PER_WORD)
5996 final_word = ((GET_MODE_SIZE (inner_mode)
5997 - GET_MODE_SIZE (tmode))
5998 / UNITS_PER_WORD) - final_word;
6000 final_word *= UNITS_PER_WORD;
6001 if (BYTES_BIG_ENDIAN &&
6002 GET_MODE_SIZE (inner_mode) > GET_MODE_SIZE (tmode))
6003 final_word += (GET_MODE_SIZE (inner_mode)
6004 - GET_MODE_SIZE (tmode)) % UNITS_PER_WORD;
6006 new = gen_rtx_SUBREG (tmode, inner, final_word);
6012 new = force_to_mode (inner, tmode,
6013 len >= HOST_BITS_PER_WIDE_INT
6014 ? ~(unsigned HOST_WIDE_INT) 0
6015 : ((unsigned HOST_WIDE_INT) 1 << len) - 1,
6018 /* If this extraction is going into the destination of a SET,
6019 make a STRICT_LOW_PART unless we made a MEM. */
6022 return (GET_CODE (new) == MEM ? new
6023 : (GET_CODE (new) != SUBREG
6024 ? gen_rtx_CLOBBER (tmode, const0_rtx)
6025 : gen_rtx_STRICT_LOW_PART (VOIDmode, new)));
6030 /* If we know that no extraneous bits are set, and that the high
6031 bit is not set, convert the extraction to the cheaper of
6032 sign and zero extension, that are equivalent in these cases. */
6033 if (flag_expensive_optimizations
6034 && (GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT
6035 && ((nonzero_bits (new, tmode)
6036 & ~(((unsigned HOST_WIDE_INT)
6037 GET_MODE_MASK (tmode))
6041 rtx temp = gen_rtx_ZERO_EXTEND (mode, new);
6042 rtx temp1 = gen_rtx_SIGN_EXTEND (mode, new);
6044 /* Prefer ZERO_EXTENSION, since it gives more information to
6046 if (rtx_cost (temp, SET) <= rtx_cost (temp1, SET))
6051 /* Otherwise, sign- or zero-extend unless we already are in the
6054 return (gen_rtx_fmt_e (unsignedp ? ZERO_EXTEND : SIGN_EXTEND,
6058 /* Unless this is a COMPARE or we have a funny memory reference,
6059 don't do anything with zero-extending field extracts starting at
6060 the low-order bit since they are simple AND operations. */
6061 if (pos_rtx == 0 && pos == 0 && ! in_dest
6062 && ! in_compare && ! spans_byte && unsignedp)
6065 /* Unless we are allowed to span bytes or INNER is not MEM, reject this if
6066 we would be spanning bytes or if the position is not a constant and the
6067 length is not 1. In all other cases, we would only be going outside
6068 our object in cases when an original shift would have been
6070 if (! spans_byte && GET_CODE (inner) == MEM
6071 && ((pos_rtx == 0 && pos + len > GET_MODE_BITSIZE (is_mode))
6072 || (pos_rtx != 0 && len != 1)))
6075 /* Get the mode to use should INNER not be a MEM, the mode for the position,
6076 and the mode for the result. */
6077 if (in_dest && mode_for_extraction (EP_insv, -1) != MAX_MACHINE_MODE)
6079 wanted_inner_reg_mode = mode_for_extraction (EP_insv, 0);
6080 pos_mode = mode_for_extraction (EP_insv, 2);
6081 extraction_mode = mode_for_extraction (EP_insv, 3);
6084 if (! in_dest && unsignedp
6085 && mode_for_extraction (EP_extzv, -1) != MAX_MACHINE_MODE)
6087 wanted_inner_reg_mode = mode_for_extraction (EP_extzv, 1);
6088 pos_mode = mode_for_extraction (EP_extzv, 3);
6089 extraction_mode = mode_for_extraction (EP_extzv, 0);
6092 if (! in_dest && ! unsignedp
6093 && mode_for_extraction (EP_extv, -1) != MAX_MACHINE_MODE)
6095 wanted_inner_reg_mode = mode_for_extraction (EP_extv, 1);
6096 pos_mode = mode_for_extraction (EP_extv, 3);
6097 extraction_mode = mode_for_extraction (EP_extv, 0);
6100 /* Never narrow an object, since that might not be safe. */
6102 if (mode != VOIDmode
6103 && GET_MODE_SIZE (extraction_mode) < GET_MODE_SIZE (mode))
6104 extraction_mode = mode;
6106 if (pos_rtx && GET_MODE (pos_rtx) != VOIDmode
6107 && GET_MODE_SIZE (pos_mode) < GET_MODE_SIZE (GET_MODE (pos_rtx)))
6108 pos_mode = GET_MODE (pos_rtx);
6110 /* If this is not from memory, the desired mode is wanted_inner_reg_mode;
6111 if we have to change the mode of memory and cannot, the desired mode is
6113 if (GET_CODE (inner) != MEM)
6114 wanted_inner_mode = wanted_inner_reg_mode;
6115 else if (inner_mode != wanted_inner_mode
6116 && (mode_dependent_address_p (XEXP (inner, 0))
6117 || MEM_VOLATILE_P (inner)))
6118 wanted_inner_mode = extraction_mode;
6122 if (BITS_BIG_ENDIAN)
6124 /* POS is passed as if BITS_BIG_ENDIAN == 0, so we need to convert it to
6125 BITS_BIG_ENDIAN style. If position is constant, compute new
6126 position. Otherwise, build subtraction.
6127 Note that POS is relative to the mode of the original argument.
6128 If it's a MEM we need to recompute POS relative to that.
6129 However, if we're extracting from (or inserting into) a register,
6130 we want to recompute POS relative to wanted_inner_mode. */
6131 int width = (GET_CODE (inner) == MEM
6132 ? GET_MODE_BITSIZE (is_mode)
6133 : GET_MODE_BITSIZE (wanted_inner_mode));
6136 pos = width - len - pos;
6139 = gen_rtx_MINUS (GET_MODE (pos_rtx), GEN_INT (width - len), pos_rtx);
6140 /* POS may be less than 0 now, but we check for that below.
6141 Note that it can only be less than 0 if GET_CODE (inner) != MEM. */
6144 /* If INNER has a wider mode, make it smaller. If this is a constant
6145 extract, try to adjust the byte to point to the byte containing
6147 if (wanted_inner_mode != VOIDmode
6148 && GET_MODE_SIZE (wanted_inner_mode) < GET_MODE_SIZE (is_mode)
6149 && ((GET_CODE (inner) == MEM
6150 && (inner_mode == wanted_inner_mode
6151 || (! mode_dependent_address_p (XEXP (inner, 0))
6152 && ! MEM_VOLATILE_P (inner))))))
6156 /* The computations below will be correct if the machine is big
6157 endian in both bits and bytes or little endian in bits and bytes.
6158 If it is mixed, we must adjust. */
6160 /* If bytes are big endian and we had a paradoxical SUBREG, we must
6161 adjust OFFSET to compensate. */
6162 if (BYTES_BIG_ENDIAN
6164 && GET_MODE_SIZE (inner_mode) < GET_MODE_SIZE (is_mode))
6165 offset -= GET_MODE_SIZE (is_mode) - GET_MODE_SIZE (inner_mode);
6167 /* If this is a constant position, we can move to the desired byte. */
6170 offset += pos / BITS_PER_UNIT;
6171 pos %= GET_MODE_BITSIZE (wanted_inner_mode);
6174 if (BYTES_BIG_ENDIAN != BITS_BIG_ENDIAN
6176 && is_mode != wanted_inner_mode)
6177 offset = (GET_MODE_SIZE (is_mode)
6178 - GET_MODE_SIZE (wanted_inner_mode) - offset);
6180 if (offset != 0 || inner_mode != wanted_inner_mode)
6181 inner = adjust_address_nv (inner, wanted_inner_mode, offset);
6184 /* If INNER is not memory, we can always get it into the proper mode. If we
6185 are changing its mode, POS must be a constant and smaller than the size
6187 else if (GET_CODE (inner) != MEM)
6189 if (GET_MODE (inner) != wanted_inner_mode
6191 || orig_pos + len > GET_MODE_BITSIZE (wanted_inner_mode)))
6194 inner = force_to_mode (inner, wanted_inner_mode,
6196 || len + orig_pos >= HOST_BITS_PER_WIDE_INT
6197 ? ~(unsigned HOST_WIDE_INT) 0
6198 : ((((unsigned HOST_WIDE_INT) 1 << len) - 1)
6203 /* Adjust mode of POS_RTX, if needed. If we want a wider mode, we
6204 have to zero extend. Otherwise, we can just use a SUBREG. */
6206 && GET_MODE_SIZE (pos_mode) > GET_MODE_SIZE (GET_MODE (pos_rtx)))
6208 rtx temp = gen_rtx_ZERO_EXTEND (pos_mode, pos_rtx);
6210 /* If we know that no extraneous bits are set, and that the high
6211 bit is not set, convert extraction to cheaper one - either
6212 SIGN_EXTENSION or ZERO_EXTENSION, that are equivalent in these
6214 if (flag_expensive_optimizations
6215 && (GET_MODE_BITSIZE (GET_MODE (pos_rtx)) <= HOST_BITS_PER_WIDE_INT
6216 && ((nonzero_bits (pos_rtx, GET_MODE (pos_rtx))
6217 & ~(((unsigned HOST_WIDE_INT)
6218 GET_MODE_MASK (GET_MODE (pos_rtx)))
6222 rtx temp1 = gen_rtx_SIGN_EXTEND (pos_mode, pos_rtx);
6224 /* Prefer ZERO_EXTENSION, since it gives more information to
6226 if (rtx_cost (temp1, SET) < rtx_cost (temp, SET))
6231 else if (pos_rtx != 0
6232 && GET_MODE_SIZE (pos_mode) < GET_MODE_SIZE (GET_MODE (pos_rtx)))
6233 pos_rtx = gen_lowpart_for_combine (pos_mode, pos_rtx);
6235 /* Make POS_RTX unless we already have it and it is correct. If we don't
6236 have a POS_RTX but we do have an ORIG_POS_RTX, the latter must
6238 if (pos_rtx == 0 && orig_pos_rtx != 0 && INTVAL (orig_pos_rtx) == pos)
6239 pos_rtx = orig_pos_rtx;
6241 else if (pos_rtx == 0)
6242 pos_rtx = GEN_INT (pos);
6244 /* Make the required operation. See if we can use existing rtx. */
6245 new = gen_rtx_fmt_eee (unsignedp ? ZERO_EXTRACT : SIGN_EXTRACT,
6246 extraction_mode, inner, GEN_INT (len), pos_rtx);
6248 new = gen_lowpart_for_combine (mode, new);
6253 /* See if X contains an ASHIFT of COUNT or more bits that can be commuted
6254 with any other operations in X. Return X without that shift if so. */
6257 extract_left_shift (x, count)
6261 enum rtx_code code = GET_CODE (x);
6262 enum machine_mode mode = GET_MODE (x);
6268 /* This is the shift itself. If it is wide enough, we will return
6269 either the value being shifted if the shift count is equal to
6270 COUNT or a shift for the difference. */
6271 if (GET_CODE (XEXP (x, 1)) == CONST_INT
6272 && INTVAL (XEXP (x, 1)) >= count)
6273 return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (x, 0),
6274 INTVAL (XEXP (x, 1)) - count);
6278 if ((tem = extract_left_shift (XEXP (x, 0), count)) != 0)
6279 return simplify_gen_unary (code, mode, tem, mode);
6283 case PLUS: case IOR: case XOR: case AND:
6284 /* If we can safely shift this constant and we find the inner shift,
6285 make a new operation. */
6286 if (GET_CODE (XEXP (x,1)) == CONST_INT
6287 && (INTVAL (XEXP (x, 1)) & ((((HOST_WIDE_INT) 1 << count)) - 1)) == 0
6288 && (tem = extract_left_shift (XEXP (x, 0), count)) != 0)
6289 return gen_binary (code, mode, tem,
6290 GEN_INT (INTVAL (XEXP (x, 1)) >> count));
6301 /* Look at the expression rooted at X. Look for expressions
6302 equivalent to ZERO_EXTRACT, SIGN_EXTRACT, ZERO_EXTEND, SIGN_EXTEND.
6303 Form these expressions.
6305 Return the new rtx, usually just X.
6307 Also, for machines like the VAX that don't have logical shift insns,
6308 try to convert logical to arithmetic shift operations in cases where
6309 they are equivalent. This undoes the canonicalizations to logical
6310 shifts done elsewhere.
6312 We try, as much as possible, to re-use rtl expressions to save memory.
6314 IN_CODE says what kind of expression we are processing. Normally, it is
6315 SET. In a memory address (inside a MEM, PLUS or minus, the latter two
6316 being kludges), it is MEM. When processing the arguments of a comparison
6317 or a COMPARE against zero, it is COMPARE. */
6320 make_compound_operation (x, in_code)
6322 enum rtx_code in_code;
6324 enum rtx_code code = GET_CODE (x);
6325 enum machine_mode mode = GET_MODE (x);
6326 int mode_width = GET_MODE_BITSIZE (mode);
6328 enum rtx_code next_code;
6334 /* Select the code to be used in recursive calls. Once we are inside an
6335 address, we stay there. If we have a comparison, set to COMPARE,
6336 but once inside, go back to our default of SET. */
6338 next_code = (code == MEM || code == PLUS || code == MINUS ? MEM
6339 : ((code == COMPARE || GET_RTX_CLASS (code) == '<')
6340 && XEXP (x, 1) == const0_rtx) ? COMPARE
6341 : in_code == COMPARE ? SET : in_code);
6343 /* Process depending on the code of this operation. If NEW is set
6344 non-zero, it will be returned. */
6349 /* Convert shifts by constants into multiplications if inside
6351 if (in_code == MEM && GET_CODE (XEXP (x, 1)) == CONST_INT
6352 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT
6353 && INTVAL (XEXP (x, 1)) >= 0)
6355 new = make_compound_operation (XEXP (x, 0), next_code);
6356 new = gen_rtx_MULT (mode, new,
6357 GEN_INT ((HOST_WIDE_INT) 1
6358 << INTVAL (XEXP (x, 1))));
6363 /* If the second operand is not a constant, we can't do anything
6365 if (GET_CODE (XEXP (x, 1)) != CONST_INT)
6368 /* If the constant is a power of two minus one and the first operand
6369 is a logical right shift, make an extraction. */
6370 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
6371 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6373 new = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code);
6374 new = make_extraction (mode, new, 0, XEXP (XEXP (x, 0), 1), i, 1,
6375 0, in_code == COMPARE);
6378 /* Same as previous, but for (subreg (lshiftrt ...)) in first op. */
6379 else if (GET_CODE (XEXP (x, 0)) == SUBREG
6380 && subreg_lowpart_p (XEXP (x, 0))
6381 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == LSHIFTRT
6382 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6384 new = make_compound_operation (XEXP (SUBREG_REG (XEXP (x, 0)), 0),
6386 new = make_extraction (GET_MODE (SUBREG_REG (XEXP (x, 0))), new, 0,
6387 XEXP (SUBREG_REG (XEXP (x, 0)), 1), i, 1,
6388 0, in_code == COMPARE);
6390 /* Same as previous, but for (xor/ior (lshiftrt...) (lshiftrt...)). */
6391 else if ((GET_CODE (XEXP (x, 0)) == XOR
6392 || GET_CODE (XEXP (x, 0)) == IOR)
6393 && GET_CODE (XEXP (XEXP (x, 0), 0)) == LSHIFTRT
6394 && GET_CODE (XEXP (XEXP (x, 0), 1)) == LSHIFTRT
6395 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6397 /* Apply the distributive law, and then try to make extractions. */
6398 new = gen_rtx_fmt_ee (GET_CODE (XEXP (x, 0)), mode,
6399 gen_rtx_AND (mode, XEXP (XEXP (x, 0), 0),
6401 gen_rtx_AND (mode, XEXP (XEXP (x, 0), 1),
6403 new = make_compound_operation (new, in_code);
6406 /* If we are have (and (rotate X C) M) and C is larger than the number
6407 of bits in M, this is an extraction. */
6409 else if (GET_CODE (XEXP (x, 0)) == ROTATE
6410 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
6411 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0
6412 && i <= INTVAL (XEXP (XEXP (x, 0), 1)))
6414 new = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code);
6415 new = make_extraction (mode, new,
6416 (GET_MODE_BITSIZE (mode)
6417 - INTVAL (XEXP (XEXP (x, 0), 1))),
6418 NULL_RTX, i, 1, 0, in_code == COMPARE);
6421 /* On machines without logical shifts, if the operand of the AND is
6422 a logical shift and our mask turns off all the propagated sign
6423 bits, we can replace the logical shift with an arithmetic shift. */
6424 else if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
6425 && !have_insn_for (LSHIFTRT, mode)
6426 && have_insn_for (ASHIFTRT, mode)
6427 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
6428 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
6429 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT
6430 && mode_width <= HOST_BITS_PER_WIDE_INT)
6432 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
6434 mask >>= INTVAL (XEXP (XEXP (x, 0), 1));
6435 if ((INTVAL (XEXP (x, 1)) & ~mask) == 0)
6437 gen_rtx_ASHIFTRT (mode,
6438 make_compound_operation
6439 (XEXP (XEXP (x, 0), 0), next_code),
6440 XEXP (XEXP (x, 0), 1)));
6443 /* If the constant is one less than a power of two, this might be
6444 representable by an extraction even if no shift is present.
6445 If it doesn't end up being a ZERO_EXTEND, we will ignore it unless
6446 we are in a COMPARE. */
6447 else if ((i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6448 new = make_extraction (mode,
6449 make_compound_operation (XEXP (x, 0),
6451 0, NULL_RTX, i, 1, 0, in_code == COMPARE);
6453 /* If we are in a comparison and this is an AND with a power of two,
6454 convert this into the appropriate bit extract. */
6455 else if (in_code == COMPARE
6456 && (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0)
6457 new = make_extraction (mode,
6458 make_compound_operation (XEXP (x, 0),
6460 i, NULL_RTX, 1, 1, 0, 1);
6465 /* If the sign bit is known to be zero, replace this with an
6466 arithmetic shift. */
6467 if (have_insn_for (ASHIFTRT, mode)
6468 && ! have_insn_for (LSHIFTRT, mode)
6469 && mode_width <= HOST_BITS_PER_WIDE_INT
6470 && (nonzero_bits (XEXP (x, 0), mode) & (1 << (mode_width - 1))) == 0)
6472 new = gen_rtx_ASHIFTRT (mode,
6473 make_compound_operation (XEXP (x, 0),
6479 /* ... fall through ... */
6485 /* If we have (ashiftrt (ashift foo C1) C2) with C2 >= C1,
6486 this is a SIGN_EXTRACT. */
6487 if (GET_CODE (rhs) == CONST_INT
6488 && GET_CODE (lhs) == ASHIFT
6489 && GET_CODE (XEXP (lhs, 1)) == CONST_INT
6490 && INTVAL (rhs) >= INTVAL (XEXP (lhs, 1)))
6492 new = make_compound_operation (XEXP (lhs, 0), next_code);
6493 new = make_extraction (mode, new,
6494 INTVAL (rhs) - INTVAL (XEXP (lhs, 1)),
6495 NULL_RTX, mode_width - INTVAL (rhs),
6496 code == LSHIFTRT, 0, in_code == COMPARE);
6500 /* See if we have operations between an ASHIFTRT and an ASHIFT.
6501 If so, try to merge the shifts into a SIGN_EXTEND. We could
6502 also do this for some cases of SIGN_EXTRACT, but it doesn't
6503 seem worth the effort; the case checked for occurs on Alpha. */
6505 if (GET_RTX_CLASS (GET_CODE (lhs)) != 'o'
6506 && ! (GET_CODE (lhs) == SUBREG
6507 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (lhs))) == 'o'))
6508 && GET_CODE (rhs) == CONST_INT
6509 && INTVAL (rhs) < HOST_BITS_PER_WIDE_INT
6510 && (new = extract_left_shift (lhs, INTVAL (rhs))) != 0)
6511 new = make_extraction (mode, make_compound_operation (new, next_code),
6512 0, NULL_RTX, mode_width - INTVAL (rhs),
6513 code == LSHIFTRT, 0, in_code == COMPARE);
6518 /* Call ourselves recursively on the inner expression. If we are
6519 narrowing the object and it has a different RTL code from
6520 what it originally did, do this SUBREG as a force_to_mode. */
6522 tem = make_compound_operation (SUBREG_REG (x), in_code);
6523 if (GET_CODE (tem) != GET_CODE (SUBREG_REG (x))
6524 && GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (tem))
6525 && subreg_lowpart_p (x))
6527 rtx newer = force_to_mode (tem, mode, ~(HOST_WIDE_INT) 0,
6530 /* If we have something other than a SUBREG, we might have
6531 done an expansion, so rerun ourselves. */
6532 if (GET_CODE (newer) != SUBREG)
6533 newer = make_compound_operation (newer, in_code);
6538 /* If this is a paradoxical subreg, and the new code is a sign or
6539 zero extension, omit the subreg and widen the extension. If it
6540 is a regular subreg, we can still get rid of the subreg by not
6541 widening so much, or in fact removing the extension entirely. */
6542 if ((GET_CODE (tem) == SIGN_EXTEND
6543 || GET_CODE (tem) == ZERO_EXTEND)
6544 && subreg_lowpart_p (x))
6546 if (GET_MODE_SIZE (mode) > GET_MODE_SIZE (GET_MODE (tem))
6547 || (GET_MODE_SIZE (mode) >
6548 GET_MODE_SIZE (GET_MODE (XEXP (tem, 0)))))
6549 tem = gen_rtx_fmt_e (GET_CODE (tem), mode, XEXP (tem, 0));
6551 tem = gen_lowpart_for_combine (mode, XEXP (tem, 0));
6562 x = gen_lowpart_for_combine (mode, new);
6563 code = GET_CODE (x);
6566 /* Now recursively process each operand of this operation. */
6567 fmt = GET_RTX_FORMAT (code);
6568 for (i = 0; i < GET_RTX_LENGTH (code); i++)
6571 new = make_compound_operation (XEXP (x, i), next_code);
6572 SUBST (XEXP (x, i), new);
6578 /* Given M see if it is a value that would select a field of bits
6579 within an item, but not the entire word. Return -1 if not.
6580 Otherwise, return the starting position of the field, where 0 is the
6583 *PLEN is set to the length of the field. */
6586 get_pos_from_mask (m, plen)
6587 unsigned HOST_WIDE_INT m;
6588 unsigned HOST_WIDE_INT *plen;
6590 /* Get the bit number of the first 1 bit from the right, -1 if none. */
6591 int pos = exact_log2 (m & -m);
6597 /* Now shift off the low-order zero bits and see if we have a power of
6599 len = exact_log2 ((m >> pos) + 1);
6608 /* See if X can be simplified knowing that we will only refer to it in
6609 MODE and will only refer to those bits that are nonzero in MASK.
6610 If other bits are being computed or if masking operations are done
6611 that select a superset of the bits in MASK, they can sometimes be
6614 Return a possibly simplified expression, but always convert X to
6615 MODE. If X is a CONST_INT, AND the CONST_INT with MASK.
6617 Also, if REG is non-zero and X is a register equal in value to REG,
6620 If JUST_SELECT is nonzero, don't optimize by noticing that bits in MASK
6621 are all off in X. This is used when X will be complemented, by either
6622 NOT, NEG, or XOR. */
6625 force_to_mode (x, mode, mask, reg, just_select)
6627 enum machine_mode mode;
6628 unsigned HOST_WIDE_INT mask;
6632 enum rtx_code code = GET_CODE (x);
6633 int next_select = just_select || code == XOR || code == NOT || code == NEG;
6634 enum machine_mode op_mode;
6635 unsigned HOST_WIDE_INT fuller_mask, nonzero;
6638 /* If this is a CALL or ASM_OPERANDS, don't do anything. Some of the
6639 code below will do the wrong thing since the mode of such an
6640 expression is VOIDmode.
6642 Also do nothing if X is a CLOBBER; this can happen if X was
6643 the return value from a call to gen_lowpart_for_combine. */
6644 if (code == CALL || code == ASM_OPERANDS || code == CLOBBER)
6647 /* We want to perform the operation is its present mode unless we know
6648 that the operation is valid in MODE, in which case we do the operation
6650 op_mode = ((GET_MODE_CLASS (mode) == GET_MODE_CLASS (GET_MODE (x))
6651 && have_insn_for (code, mode))
6652 ? mode : GET_MODE (x));
6654 /* It is not valid to do a right-shift in a narrower mode
6655 than the one it came in with. */
6656 if ((code == LSHIFTRT || code == ASHIFTRT)
6657 && GET_MODE_BITSIZE (mode) < GET_MODE_BITSIZE (GET_MODE (x)))
6658 op_mode = GET_MODE (x);
6660 /* Truncate MASK to fit OP_MODE. */
6662 mask &= GET_MODE_MASK (op_mode);
6664 /* When we have an arithmetic operation, or a shift whose count we
6665 do not know, we need to assume that all bit the up to the highest-order
6666 bit in MASK will be needed. This is how we form such a mask. */
6668 fuller_mask = (GET_MODE_BITSIZE (op_mode) >= HOST_BITS_PER_WIDE_INT
6669 ? GET_MODE_MASK (op_mode)
6670 : (((unsigned HOST_WIDE_INT) 1 << (floor_log2 (mask) + 1))
6673 fuller_mask = ~(HOST_WIDE_INT) 0;
6675 /* Determine what bits of X are guaranteed to be (non)zero. */
6676 nonzero = nonzero_bits (x, mode);
6678 /* If none of the bits in X are needed, return a zero. */
6679 if (! just_select && (nonzero & mask) == 0)
6682 /* If X is a CONST_INT, return a new one. Do this here since the
6683 test below will fail. */
6684 if (GET_CODE (x) == CONST_INT)
6686 HOST_WIDE_INT cval = INTVAL (x) & mask;
6687 int width = GET_MODE_BITSIZE (mode);
6689 /* If MODE is narrower that HOST_WIDE_INT and CVAL is a negative
6690 number, sign extend it. */
6691 if (width > 0 && width < HOST_BITS_PER_WIDE_INT
6692 && (cval & ((HOST_WIDE_INT) 1 << (width - 1))) != 0)
6693 cval |= (HOST_WIDE_INT) -1 << width;
6695 return GEN_INT (cval);
6698 /* If X is narrower than MODE and we want all the bits in X's mode, just
6699 get X in the proper mode. */
6700 if (GET_MODE_SIZE (GET_MODE (x)) < GET_MODE_SIZE (mode)
6701 && (GET_MODE_MASK (GET_MODE (x)) & ~mask) == 0)
6702 return gen_lowpart_for_combine (mode, x);
6704 /* If we aren't changing the mode, X is not a SUBREG, and all zero bits in
6705 MASK are already known to be zero in X, we need not do anything. */
6706 if (GET_MODE (x) == mode && code != SUBREG && (~mask & nonzero) == 0)
6712 /* If X is a (clobber (const_int)), return it since we know we are
6713 generating something that won't match. */
6717 /* X is a (use (mem ..)) that was made from a bit-field extraction that
6718 spanned the boundary of the MEM. If we are now masking so it is
6719 within that boundary, we don't need the USE any more. */
6720 if (! BITS_BIG_ENDIAN
6721 && (mask & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
6722 return force_to_mode (XEXP (x, 0), mode, mask, reg, next_select);
6729 x = expand_compound_operation (x);
6730 if (GET_CODE (x) != code)
6731 return force_to_mode (x, mode, mask, reg, next_select);
6735 if (reg != 0 && (rtx_equal_p (get_last_value (reg), x)
6736 || rtx_equal_p (reg, get_last_value (x))))
6741 if (subreg_lowpart_p (x)
6742 /* We can ignore the effect of this SUBREG if it narrows the mode or
6743 if the constant masks to zero all the bits the mode doesn't
6745 && ((GET_MODE_SIZE (GET_MODE (x))
6746 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
6748 & GET_MODE_MASK (GET_MODE (x))
6749 & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (x)))))))
6750 return force_to_mode (SUBREG_REG (x), mode, mask, reg, next_select);
6754 /* If this is an AND with a constant, convert it into an AND
6755 whose constant is the AND of that constant with MASK. If it
6756 remains an AND of MASK, delete it since it is redundant. */
6758 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
6760 x = simplify_and_const_int (x, op_mode, XEXP (x, 0),
6761 mask & INTVAL (XEXP (x, 1)));
6763 /* If X is still an AND, see if it is an AND with a mask that
6764 is just some low-order bits. If so, and it is MASK, we don't
6767 if (GET_CODE (x) == AND && GET_CODE (XEXP (x, 1)) == CONST_INT
6768 && ((INTVAL (XEXP (x, 1)) & GET_MODE_MASK (GET_MODE (x)))
6769 == (HOST_WIDE_INT) mask))
6772 /* If it remains an AND, try making another AND with the bits
6773 in the mode mask that aren't in MASK turned on. If the
6774 constant in the AND is wide enough, this might make a
6775 cheaper constant. */
6777 if (GET_CODE (x) == AND && GET_CODE (XEXP (x, 1)) == CONST_INT
6778 && GET_MODE_MASK (GET_MODE (x)) != mask
6779 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT)
6781 HOST_WIDE_INT cval = (INTVAL (XEXP (x, 1))
6782 | (GET_MODE_MASK (GET_MODE (x)) & ~mask));
6783 int width = GET_MODE_BITSIZE (GET_MODE (x));
6786 /* If MODE is narrower that HOST_WIDE_INT and CVAL is a negative
6787 number, sign extend it. */
6788 if (width > 0 && width < HOST_BITS_PER_WIDE_INT
6789 && (cval & ((HOST_WIDE_INT) 1 << (width - 1))) != 0)
6790 cval |= (HOST_WIDE_INT) -1 << width;
6792 y = gen_binary (AND, GET_MODE (x), XEXP (x, 0), GEN_INT (cval));
6793 if (rtx_cost (y, SET) < rtx_cost (x, SET))
6803 /* In (and (plus FOO C1) M), if M is a mask that just turns off
6804 low-order bits (as in an alignment operation) and FOO is already
6805 aligned to that boundary, mask C1 to that boundary as well.
6806 This may eliminate that PLUS and, later, the AND. */
6809 unsigned int width = GET_MODE_BITSIZE (mode);
6810 unsigned HOST_WIDE_INT smask = mask;
6812 /* If MODE is narrower than HOST_WIDE_INT and mask is a negative
6813 number, sign extend it. */
6815 if (width < HOST_BITS_PER_WIDE_INT
6816 && (smask & ((HOST_WIDE_INT) 1 << (width - 1))) != 0)
6817 smask |= (HOST_WIDE_INT) -1 << width;
6819 if (GET_CODE (XEXP (x, 1)) == CONST_INT
6820 && exact_log2 (- smask) >= 0
6821 && (nonzero_bits (XEXP (x, 0), mode) & ~smask) == 0
6822 && (INTVAL (XEXP (x, 1)) & ~smask) != 0)
6823 return force_to_mode (plus_constant (XEXP (x, 0),
6824 (INTVAL (XEXP (x, 1)) & smask)),
6825 mode, smask, reg, next_select);
6828 /* ... fall through ... */
6831 /* For PLUS, MINUS and MULT, we need any bits less significant than the
6832 most significant bit in MASK since carries from those bits will
6833 affect the bits we are interested in. */
6838 /* If X is (minus C Y) where C's least set bit is larger than any bit
6839 in the mask, then we may replace with (neg Y). */
6840 if (GET_CODE (XEXP (x, 0)) == CONST_INT
6841 && (((unsigned HOST_WIDE_INT) (INTVAL (XEXP (x, 0))
6842 & -INTVAL (XEXP (x, 0))))
6845 x = simplify_gen_unary (NEG, GET_MODE (x), XEXP (x, 1),
6847 return force_to_mode (x, mode, mask, reg, next_select);
6850 /* Similarly, if C contains every bit in the mask, then we may
6851 replace with (not Y). */
6852 if (GET_CODE (XEXP (x, 0)) == CONST_INT
6853 && ((INTVAL (XEXP (x, 0)) | (HOST_WIDE_INT) mask)
6854 == INTVAL (XEXP (x, 0))))
6856 x = simplify_gen_unary (NOT, GET_MODE (x),
6857 XEXP (x, 1), GET_MODE (x));
6858 return force_to_mode (x, mode, mask, reg, next_select);
6866 /* If X is (ior (lshiftrt FOO C1) C2), try to commute the IOR and
6867 LSHIFTRT so we end up with an (and (lshiftrt (ior ...) ...) ...)
6868 operation which may be a bitfield extraction. Ensure that the
6869 constant we form is not wider than the mode of X. */
6871 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
6872 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
6873 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
6874 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT
6875 && GET_CODE (XEXP (x, 1)) == CONST_INT
6876 && ((INTVAL (XEXP (XEXP (x, 0), 1))
6877 + floor_log2 (INTVAL (XEXP (x, 1))))
6878 < GET_MODE_BITSIZE (GET_MODE (x)))
6879 && (INTVAL (XEXP (x, 1))
6880 & ~nonzero_bits (XEXP (x, 0), GET_MODE (x))) == 0)
6882 temp = GEN_INT ((INTVAL (XEXP (x, 1)) & mask)
6883 << INTVAL (XEXP (XEXP (x, 0), 1)));
6884 temp = gen_binary (GET_CODE (x), GET_MODE (x),
6885 XEXP (XEXP (x, 0), 0), temp);
6886 x = gen_binary (LSHIFTRT, GET_MODE (x), temp,
6887 XEXP (XEXP (x, 0), 1));
6888 return force_to_mode (x, mode, mask, reg, next_select);
6892 /* For most binary operations, just propagate into the operation and
6893 change the mode if we have an operation of that mode. */
6895 op0 = gen_lowpart_for_combine (op_mode,
6896 force_to_mode (XEXP (x, 0), mode, mask,
6898 op1 = gen_lowpart_for_combine (op_mode,
6899 force_to_mode (XEXP (x, 1), mode, mask,
6902 /* If OP1 is a CONST_INT and X is an IOR or XOR, clear bits outside
6903 MASK since OP1 might have been sign-extended but we never want
6904 to turn on extra bits, since combine might have previously relied
6905 on them being off. */
6906 if (GET_CODE (op1) == CONST_INT && (code == IOR || code == XOR)
6907 && (INTVAL (op1) & mask) != 0)
6908 op1 = GEN_INT (INTVAL (op1) & mask);
6910 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
6911 x = gen_binary (code, op_mode, op0, op1);
6915 /* For left shifts, do the same, but just for the first operand.
6916 However, we cannot do anything with shifts where we cannot
6917 guarantee that the counts are smaller than the size of the mode
6918 because such a count will have a different meaning in a
6921 if (! (GET_CODE (XEXP (x, 1)) == CONST_INT
6922 && INTVAL (XEXP (x, 1)) >= 0
6923 && INTVAL (XEXP (x, 1)) < GET_MODE_BITSIZE (mode))
6924 && ! (GET_MODE (XEXP (x, 1)) != VOIDmode
6925 && (nonzero_bits (XEXP (x, 1), GET_MODE (XEXP (x, 1)))
6926 < (unsigned HOST_WIDE_INT) GET_MODE_BITSIZE (mode))))
6929 /* If the shift count is a constant and we can do arithmetic in
6930 the mode of the shift, refine which bits we need. Otherwise, use the
6931 conservative form of the mask. */
6932 if (GET_CODE (XEXP (x, 1)) == CONST_INT
6933 && INTVAL (XEXP (x, 1)) >= 0
6934 && INTVAL (XEXP (x, 1)) < GET_MODE_BITSIZE (op_mode)
6935 && GET_MODE_BITSIZE (op_mode) <= HOST_BITS_PER_WIDE_INT)
6936 mask >>= INTVAL (XEXP (x, 1));
6940 op0 = gen_lowpart_for_combine (op_mode,
6941 force_to_mode (XEXP (x, 0), op_mode,
6942 mask, reg, next_select));
6944 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0))
6945 x = gen_binary (code, op_mode, op0, XEXP (x, 1));
6949 /* Here we can only do something if the shift count is a constant,
6950 this shift constant is valid for the host, and we can do arithmetic
6953 if (GET_CODE (XEXP (x, 1)) == CONST_INT
6954 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT
6955 && GET_MODE_BITSIZE (op_mode) <= HOST_BITS_PER_WIDE_INT)
6957 rtx inner = XEXP (x, 0);
6958 unsigned HOST_WIDE_INT inner_mask;
6960 /* Select the mask of the bits we need for the shift operand. */
6961 inner_mask = mask << INTVAL (XEXP (x, 1));
6963 /* We can only change the mode of the shift if we can do arithmetic
6964 in the mode of the shift and INNER_MASK is no wider than the
6965 width of OP_MODE. */
6966 if (GET_MODE_BITSIZE (op_mode) > HOST_BITS_PER_WIDE_INT
6967 || (inner_mask & ~GET_MODE_MASK (op_mode)) != 0)
6968 op_mode = GET_MODE (x);
6970 inner = force_to_mode (inner, op_mode, inner_mask, reg, next_select);
6972 if (GET_MODE (x) != op_mode || inner != XEXP (x, 0))
6973 x = gen_binary (LSHIFTRT, op_mode, inner, XEXP (x, 1));
6976 /* If we have (and (lshiftrt FOO C1) C2) where the combination of the
6977 shift and AND produces only copies of the sign bit (C2 is one less
6978 than a power of two), we can do this with just a shift. */
6980 if (GET_CODE (x) == LSHIFTRT
6981 && GET_CODE (XEXP (x, 1)) == CONST_INT
6982 /* The shift puts one of the sign bit copies in the least significant
6984 && ((INTVAL (XEXP (x, 1))
6985 + num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0))))
6986 >= GET_MODE_BITSIZE (GET_MODE (x)))
6987 && exact_log2 (mask + 1) >= 0
6988 /* Number of bits left after the shift must be more than the mask
6990 && ((INTVAL (XEXP (x, 1)) + exact_log2 (mask + 1))
6991 <= GET_MODE_BITSIZE (GET_MODE (x)))
6992 /* Must be more sign bit copies than the mask needs. */
6993 && ((int) num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
6994 >= exact_log2 (mask + 1)))
6995 x = gen_binary (LSHIFTRT, GET_MODE (x), XEXP (x, 0),
6996 GEN_INT (GET_MODE_BITSIZE (GET_MODE (x))
6997 - exact_log2 (mask + 1)));
7002 /* If we are just looking for the sign bit, we don't need this shift at
7003 all, even if it has a variable count. */
7004 if (GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
7005 && (mask == ((unsigned HOST_WIDE_INT) 1
7006 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
7007 return force_to_mode (XEXP (x, 0), mode, mask, reg, next_select);
7009 /* If this is a shift by a constant, get a mask that contains those bits
7010 that are not copies of the sign bit. We then have two cases: If
7011 MASK only includes those bits, this can be a logical shift, which may
7012 allow simplifications. If MASK is a single-bit field not within
7013 those bits, we are requesting a copy of the sign bit and hence can
7014 shift the sign bit to the appropriate location. */
7016 if (GET_CODE (XEXP (x, 1)) == CONST_INT && INTVAL (XEXP (x, 1)) >= 0
7017 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT)
7021 /* If the considered data is wider than HOST_WIDE_INT, we can't
7022 represent a mask for all its bits in a single scalar.
7023 But we only care about the lower bits, so calculate these. */
7025 if (GET_MODE_BITSIZE (GET_MODE (x)) > HOST_BITS_PER_WIDE_INT)
7027 nonzero = ~(HOST_WIDE_INT) 0;
7029 /* GET_MODE_BITSIZE (GET_MODE (x)) - INTVAL (XEXP (x, 1))
7030 is the number of bits a full-width mask would have set.
7031 We need only shift if these are fewer than nonzero can
7032 hold. If not, we must keep all bits set in nonzero. */
7034 if (GET_MODE_BITSIZE (GET_MODE (x)) - INTVAL (XEXP (x, 1))
7035 < HOST_BITS_PER_WIDE_INT)
7036 nonzero >>= INTVAL (XEXP (x, 1))
7037 + HOST_BITS_PER_WIDE_INT
7038 - GET_MODE_BITSIZE (GET_MODE (x)) ;
7042 nonzero = GET_MODE_MASK (GET_MODE (x));
7043 nonzero >>= INTVAL (XEXP (x, 1));
7046 if ((mask & ~nonzero) == 0
7047 || (i = exact_log2 (mask)) >= 0)
7049 x = simplify_shift_const
7050 (x, LSHIFTRT, GET_MODE (x), XEXP (x, 0),
7051 i < 0 ? INTVAL (XEXP (x, 1))
7052 : GET_MODE_BITSIZE (GET_MODE (x)) - 1 - i);
7054 if (GET_CODE (x) != ASHIFTRT)
7055 return force_to_mode (x, mode, mask, reg, next_select);
7059 /* If MASK is 1, convert this to a LSHIFTRT. This can be done
7060 even if the shift count isn't a constant. */
7062 x = gen_binary (LSHIFTRT, GET_MODE (x), XEXP (x, 0), XEXP (x, 1));
7066 /* If this is a zero- or sign-extension operation that just affects bits
7067 we don't care about, remove it. Be sure the call above returned
7068 something that is still a shift. */
7070 if ((GET_CODE (x) == LSHIFTRT || GET_CODE (x) == ASHIFTRT)
7071 && GET_CODE (XEXP (x, 1)) == CONST_INT
7072 && INTVAL (XEXP (x, 1)) >= 0
7073 && (INTVAL (XEXP (x, 1))
7074 <= GET_MODE_BITSIZE (GET_MODE (x)) - (floor_log2 (mask) + 1))
7075 && GET_CODE (XEXP (x, 0)) == ASHIFT
7076 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
7077 && INTVAL (XEXP (XEXP (x, 0), 1)) == INTVAL (XEXP (x, 1)))
7078 return force_to_mode (XEXP (XEXP (x, 0), 0), mode, mask,
7085 /* If the shift count is constant and we can do computations
7086 in the mode of X, compute where the bits we care about are.
7087 Otherwise, we can't do anything. Don't change the mode of
7088 the shift or propagate MODE into the shift, though. */
7089 if (GET_CODE (XEXP (x, 1)) == CONST_INT
7090 && INTVAL (XEXP (x, 1)) >= 0)
7092 temp = simplify_binary_operation (code == ROTATE ? ROTATERT : ROTATE,
7093 GET_MODE (x), GEN_INT (mask),
7095 if (temp && GET_CODE(temp) == CONST_INT)
7097 force_to_mode (XEXP (x, 0), GET_MODE (x),
7098 INTVAL (temp), reg, next_select));
7103 /* If we just want the low-order bit, the NEG isn't needed since it
7104 won't change the low-order bit. */
7106 return force_to_mode (XEXP (x, 0), mode, mask, reg, just_select);
7108 /* We need any bits less significant than the most significant bit in
7109 MASK since carries from those bits will affect the bits we are
7115 /* (not FOO) is (xor FOO CONST), so if FOO is an LSHIFTRT, we can do the
7116 same as the XOR case above. Ensure that the constant we form is not
7117 wider than the mode of X. */
7119 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
7120 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
7121 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
7122 && (INTVAL (XEXP (XEXP (x, 0), 1)) + floor_log2 (mask)
7123 < GET_MODE_BITSIZE (GET_MODE (x)))
7124 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT)
7126 temp = GEN_INT (mask << INTVAL (XEXP (XEXP (x, 0), 1)));
7127 temp = gen_binary (XOR, GET_MODE (x), XEXP (XEXP (x, 0), 0), temp);
7128 x = gen_binary (LSHIFTRT, GET_MODE (x), temp, XEXP (XEXP (x, 0), 1));
7130 return force_to_mode (x, mode, mask, reg, next_select);
7133 /* (and (not FOO) CONST) is (not (or FOO (not CONST))), so we must
7134 use the full mask inside the NOT. */
7138 op0 = gen_lowpart_for_combine (op_mode,
7139 force_to_mode (XEXP (x, 0), mode, mask,
7141 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0))
7142 x = simplify_gen_unary (code, op_mode, op0, op_mode);
7146 /* (and (ne FOO 0) CONST) can be (and FOO CONST) if CONST is included
7147 in STORE_FLAG_VALUE and FOO has a single bit that might be nonzero,
7148 which is equal to STORE_FLAG_VALUE. */
7149 if ((mask & ~STORE_FLAG_VALUE) == 0 && XEXP (x, 1) == const0_rtx
7150 && exact_log2 (nonzero_bits (XEXP (x, 0), mode)) >= 0
7151 && nonzero_bits (XEXP (x, 0), mode) == STORE_FLAG_VALUE)
7152 return force_to_mode (XEXP (x, 0), mode, mask, reg, next_select);
7157 /* We have no way of knowing if the IF_THEN_ELSE can itself be
7158 written in a narrower mode. We play it safe and do not do so. */
7161 gen_lowpart_for_combine (GET_MODE (x),
7162 force_to_mode (XEXP (x, 1), mode,
7163 mask, reg, next_select)));
7165 gen_lowpart_for_combine (GET_MODE (x),
7166 force_to_mode (XEXP (x, 2), mode,
7167 mask, reg,next_select)));
7174 /* Ensure we return a value of the proper mode. */
7175 return gen_lowpart_for_combine (mode, x);
7178 /* Return nonzero if X is an expression that has one of two values depending on
7179 whether some other value is zero or nonzero. In that case, we return the
7180 value that is being tested, *PTRUE is set to the value if the rtx being
7181 returned has a nonzero value, and *PFALSE is set to the other alternative.
7183 If we return zero, we set *PTRUE and *PFALSE to X. */
7186 if_then_else_cond (x, ptrue, pfalse)
7188 rtx *ptrue, *pfalse;
7190 enum machine_mode mode = GET_MODE (x);
7191 enum rtx_code code = GET_CODE (x);
7192 rtx cond0, cond1, true0, true1, false0, false1;
7193 unsigned HOST_WIDE_INT nz;
7195 /* If we are comparing a value against zero, we are done. */
7196 if ((code == NE || code == EQ)
7197 && GET_CODE (XEXP (x, 1)) == CONST_INT && INTVAL (XEXP (x, 1)) == 0)
7199 *ptrue = (code == NE) ? const_true_rtx : const0_rtx;
7200 *pfalse = (code == NE) ? const0_rtx : const_true_rtx;
7204 /* If this is a unary operation whose operand has one of two values, apply
7205 our opcode to compute those values. */
7206 else if (GET_RTX_CLASS (code) == '1'
7207 && (cond0 = if_then_else_cond (XEXP (x, 0), &true0, &false0)) != 0)
7209 *ptrue = simplify_gen_unary (code, mode, true0, GET_MODE (XEXP (x, 0)));
7210 *pfalse = simplify_gen_unary (code, mode, false0,
7211 GET_MODE (XEXP (x, 0)));
7215 /* If this is a COMPARE, do nothing, since the IF_THEN_ELSE we would
7216 make can't possibly match and would suppress other optimizations. */
7217 else if (code == COMPARE)
7220 /* If this is a binary operation, see if either side has only one of two
7221 values. If either one does or if both do and they are conditional on
7222 the same value, compute the new true and false values. */
7223 else if (GET_RTX_CLASS (code) == 'c' || GET_RTX_CLASS (code) == '2'
7224 || GET_RTX_CLASS (code) == '<')
7226 cond0 = if_then_else_cond (XEXP (x, 0), &true0, &false0);
7227 cond1 = if_then_else_cond (XEXP (x, 1), &true1, &false1);
7229 if ((cond0 != 0 || cond1 != 0)
7230 && ! (cond0 != 0 && cond1 != 0 && ! rtx_equal_p (cond0, cond1)))
7232 /* If if_then_else_cond returned zero, then true/false are the
7233 same rtl. We must copy one of them to prevent invalid rtl
7236 true0 = copy_rtx (true0);
7237 else if (cond1 == 0)
7238 true1 = copy_rtx (true1);
7240 *ptrue = gen_binary (code, mode, true0, true1);
7241 *pfalse = gen_binary (code, mode, false0, false1);
7242 return cond0 ? cond0 : cond1;
7245 /* See if we have PLUS, IOR, XOR, MINUS or UMAX, where one of the
7246 operands is zero when the other is non-zero, and vice-versa,
7247 and STORE_FLAG_VALUE is 1 or -1. */
7249 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
7250 && (code == PLUS || code == IOR || code == XOR || code == MINUS
7252 && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT)
7254 rtx op0 = XEXP (XEXP (x, 0), 1);
7255 rtx op1 = XEXP (XEXP (x, 1), 1);
7257 cond0 = XEXP (XEXP (x, 0), 0);
7258 cond1 = XEXP (XEXP (x, 1), 0);
7260 if (GET_RTX_CLASS (GET_CODE (cond0)) == '<'
7261 && GET_RTX_CLASS (GET_CODE (cond1)) == '<'
7262 && ((GET_CODE (cond0) == combine_reversed_comparison_code (cond1)
7263 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0))
7264 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1)))
7265 || ((swap_condition (GET_CODE (cond0))
7266 == combine_reversed_comparison_code (cond1))
7267 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1))
7268 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0))))
7269 && ! side_effects_p (x))
7271 *ptrue = gen_binary (MULT, mode, op0, const_true_rtx);
7272 *pfalse = gen_binary (MULT, mode,
7274 ? simplify_gen_unary (NEG, mode, op1,
7282 /* Similarly for MULT, AND and UMIN, except that for these the result
7284 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
7285 && (code == MULT || code == AND || code == UMIN)
7286 && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT)
7288 cond0 = XEXP (XEXP (x, 0), 0);
7289 cond1 = XEXP (XEXP (x, 1), 0);
7291 if (GET_RTX_CLASS (GET_CODE (cond0)) == '<'
7292 && GET_RTX_CLASS (GET_CODE (cond1)) == '<'
7293 && ((GET_CODE (cond0) == combine_reversed_comparison_code (cond1)
7294 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0))
7295 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1)))
7296 || ((swap_condition (GET_CODE (cond0))
7297 == combine_reversed_comparison_code (cond1))
7298 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1))
7299 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0))))
7300 && ! side_effects_p (x))
7302 *ptrue = *pfalse = const0_rtx;
7308 else if (code == IF_THEN_ELSE)
7310 /* If we have IF_THEN_ELSE already, extract the condition and
7311 canonicalize it if it is NE or EQ. */
7312 cond0 = XEXP (x, 0);
7313 *ptrue = XEXP (x, 1), *pfalse = XEXP (x, 2);
7314 if (GET_CODE (cond0) == NE && XEXP (cond0, 1) == const0_rtx)
7315 return XEXP (cond0, 0);
7316 else if (GET_CODE (cond0) == EQ && XEXP (cond0, 1) == const0_rtx)
7318 *ptrue = XEXP (x, 2), *pfalse = XEXP (x, 1);
7319 return XEXP (cond0, 0);
7325 /* If X is a SUBREG, we can narrow both the true and false values
7326 if the inner expression, if there is a condition. */
7327 else if (code == SUBREG
7328 && 0 != (cond0 = if_then_else_cond (SUBREG_REG (x),
7331 *ptrue = simplify_gen_subreg (mode, true0,
7332 GET_MODE (SUBREG_REG (x)), SUBREG_BYTE (x));
7333 *pfalse = simplify_gen_subreg (mode, false0,
7334 GET_MODE (SUBREG_REG (x)), SUBREG_BYTE (x));
7339 /* If X is a constant, this isn't special and will cause confusions
7340 if we treat it as such. Likewise if it is equivalent to a constant. */
7341 else if (CONSTANT_P (x)
7342 || ((cond0 = get_last_value (x)) != 0 && CONSTANT_P (cond0)))
7345 /* If we're in BImode, canonicalize on 0 and STORE_FLAG_VALUE, as that
7346 will be least confusing to the rest of the compiler. */
7347 else if (mode == BImode)
7349 *ptrue = GEN_INT (STORE_FLAG_VALUE), *pfalse = const0_rtx;
7353 /* If X is known to be either 0 or -1, those are the true and
7354 false values when testing X. */
7355 else if (x == constm1_rtx || x == const0_rtx
7356 || (mode != VOIDmode
7357 && num_sign_bit_copies (x, mode) == GET_MODE_BITSIZE (mode)))
7359 *ptrue = constm1_rtx, *pfalse = const0_rtx;
7363 /* Likewise for 0 or a single bit. */
7364 else if (mode != VOIDmode
7365 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
7366 && exact_log2 (nz = nonzero_bits (x, mode)) >= 0)
7368 *ptrue = GEN_INT (nz), *pfalse = const0_rtx;
7372 /* Otherwise fail; show no condition with true and false values the same. */
7373 *ptrue = *pfalse = x;
7377 /* Return the value of expression X given the fact that condition COND
7378 is known to be true when applied to REG as its first operand and VAL
7379 as its second. X is known to not be shared and so can be modified in
7382 We only handle the simplest cases, and specifically those cases that
7383 arise with IF_THEN_ELSE expressions. */
7386 known_cond (x, cond, reg, val)
7391 enum rtx_code code = GET_CODE (x);
7396 if (side_effects_p (x))
7399 /* If either operand of the condition is a floating point value,
7400 then we have to avoid collapsing an EQ comparison. */
7402 && rtx_equal_p (x, reg)
7403 && ! FLOAT_MODE_P (GET_MODE (x))
7404 && ! FLOAT_MODE_P (GET_MODE (val)))
7407 if (cond == UNEQ && rtx_equal_p (x, reg))
7410 /* If X is (abs REG) and we know something about REG's relationship
7411 with zero, we may be able to simplify this. */
7413 if (code == ABS && rtx_equal_p (XEXP (x, 0), reg) && val == const0_rtx)
7416 case GE: case GT: case EQ:
7419 return simplify_gen_unary (NEG, GET_MODE (XEXP (x, 0)),
7421 GET_MODE (XEXP (x, 0)));
7426 /* The only other cases we handle are MIN, MAX, and comparisons if the
7427 operands are the same as REG and VAL. */
7429 else if (GET_RTX_CLASS (code) == '<' || GET_RTX_CLASS (code) == 'c')
7431 if (rtx_equal_p (XEXP (x, 0), val))
7432 cond = swap_condition (cond), temp = val, val = reg, reg = temp;
7434 if (rtx_equal_p (XEXP (x, 0), reg) && rtx_equal_p (XEXP (x, 1), val))
7436 if (GET_RTX_CLASS (code) == '<')
7438 if (comparison_dominates_p (cond, code))
7439 return const_true_rtx;
7441 code = combine_reversed_comparison_code (x);
7443 && comparison_dominates_p (cond, code))
7448 else if (code == SMAX || code == SMIN
7449 || code == UMIN || code == UMAX)
7451 int unsignedp = (code == UMIN || code == UMAX);
7453 /* Do not reverse the condition when it is NE or EQ.
7454 This is because we cannot conclude anything about
7455 the value of 'SMAX (x, y)' when x is not equal to y,
7456 but we can when x equals y. */
7457 if ((code == SMAX || code == UMAX)
7458 && ! (cond == EQ || cond == NE))
7459 cond = reverse_condition (cond);
7464 return unsignedp ? x : XEXP (x, 1);
7466 return unsignedp ? x : XEXP (x, 0);
7468 return unsignedp ? XEXP (x, 1) : x;
7470 return unsignedp ? XEXP (x, 0) : x;
7477 else if (code == SUBREG)
7479 enum machine_mode inner_mode = GET_MODE (SUBREG_REG (x));
7480 rtx new, r = known_cond (SUBREG_REG (x), cond, reg, val);
7482 if (SUBREG_REG (x) != r)
7484 /* We must simplify subreg here, before we lose track of the
7485 original inner_mode. */
7486 new = simplify_subreg (GET_MODE (x), r,
7487 inner_mode, SUBREG_BYTE (x));
7491 SUBST (SUBREG_REG (x), r);
7496 /* We don't have to handle SIGN_EXTEND here, because even in the
7497 case of replacing something with a modeless CONST_INT, a
7498 CONST_INT is already (supposed to be) a valid sign extension for
7499 its narrower mode, which implies it's already properly
7500 sign-extended for the wider mode. Now, for ZERO_EXTEND, the
7501 story is different. */
7502 else if (code == ZERO_EXTEND)
7504 enum machine_mode inner_mode = GET_MODE (XEXP (x, 0));
7505 rtx new, r = known_cond (XEXP (x, 0), cond, reg, val);
7507 if (XEXP (x, 0) != r)
7509 /* We must simplify the zero_extend here, before we lose
7510 track of the original inner_mode. */
7511 new = simplify_unary_operation (ZERO_EXTEND, GET_MODE (x),
7516 SUBST (XEXP (x, 0), r);
7522 fmt = GET_RTX_FORMAT (code);
7523 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
7526 SUBST (XEXP (x, i), known_cond (XEXP (x, i), cond, reg, val));
7527 else if (fmt[i] == 'E')
7528 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
7529 SUBST (XVECEXP (x, i, j), known_cond (XVECEXP (x, i, j),
7536 /* See if X and Y are equal for the purposes of seeing if we can rewrite an
7537 assignment as a field assignment. */
7540 rtx_equal_for_field_assignment_p (x, y)
7544 if (x == y || rtx_equal_p (x, y))
7547 if (x == 0 || y == 0 || GET_MODE (x) != GET_MODE (y))
7550 /* Check for a paradoxical SUBREG of a MEM compared with the MEM.
7551 Note that all SUBREGs of MEM are paradoxical; otherwise they
7552 would have been rewritten. */
7553 if (GET_CODE (x) == MEM && GET_CODE (y) == SUBREG
7554 && GET_CODE (SUBREG_REG (y)) == MEM
7555 && rtx_equal_p (SUBREG_REG (y),
7556 gen_lowpart_for_combine (GET_MODE (SUBREG_REG (y)), x)))
7559 if (GET_CODE (y) == MEM && GET_CODE (x) == SUBREG
7560 && GET_CODE (SUBREG_REG (x)) == MEM
7561 && rtx_equal_p (SUBREG_REG (x),
7562 gen_lowpart_for_combine (GET_MODE (SUBREG_REG (x)), y)))
7565 /* We used to see if get_last_value of X and Y were the same but that's
7566 not correct. In one direction, we'll cause the assignment to have
7567 the wrong destination and in the case, we'll import a register into this
7568 insn that might have already have been dead. So fail if none of the
7569 above cases are true. */
7573 /* See if X, a SET operation, can be rewritten as a bit-field assignment.
7574 Return that assignment if so.
7576 We only handle the most common cases. */
7579 make_field_assignment (x)
7582 rtx dest = SET_DEST (x);
7583 rtx src = SET_SRC (x);
7588 unsigned HOST_WIDE_INT len;
7590 enum machine_mode mode;
7592 /* If SRC was (and (not (ashift (const_int 1) POS)) DEST), this is
7593 a clear of a one-bit field. We will have changed it to
7594 (and (rotate (const_int -2) POS) DEST), so check for that. Also check
7597 if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == ROTATE
7598 && GET_CODE (XEXP (XEXP (src, 0), 0)) == CONST_INT
7599 && INTVAL (XEXP (XEXP (src, 0), 0)) == -2
7600 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
7602 assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1),
7605 return gen_rtx_SET (VOIDmode, assign, const0_rtx);
7609 else if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == SUBREG
7610 && subreg_lowpart_p (XEXP (src, 0))
7611 && (GET_MODE_SIZE (GET_MODE (XEXP (src, 0)))
7612 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (src, 0)))))
7613 && GET_CODE (SUBREG_REG (XEXP (src, 0))) == ROTATE
7614 && INTVAL (XEXP (SUBREG_REG (XEXP (src, 0)), 0)) == -2
7615 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
7617 assign = make_extraction (VOIDmode, dest, 0,
7618 XEXP (SUBREG_REG (XEXP (src, 0)), 1),
7621 return gen_rtx_SET (VOIDmode, assign, const0_rtx);
7625 /* If SRC is (ior (ashift (const_int 1) POS) DEST), this is a set of a
7627 else if (GET_CODE (src) == IOR && GET_CODE (XEXP (src, 0)) == ASHIFT
7628 && XEXP (XEXP (src, 0), 0) == const1_rtx
7629 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
7631 assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1),
7634 return gen_rtx_SET (VOIDmode, assign, const1_rtx);
7638 /* The other case we handle is assignments into a constant-position
7639 field. They look like (ior/xor (and DEST C1) OTHER). If C1 represents
7640 a mask that has all one bits except for a group of zero bits and
7641 OTHER is known to have zeros where C1 has ones, this is such an
7642 assignment. Compute the position and length from C1. Shift OTHER
7643 to the appropriate position, force it to the required mode, and
7644 make the extraction. Check for the AND in both operands. */
7646 if (GET_CODE (src) != IOR && GET_CODE (src) != XOR)
7649 rhs = expand_compound_operation (XEXP (src, 0));
7650 lhs = expand_compound_operation (XEXP (src, 1));
7652 if (GET_CODE (rhs) == AND
7653 && GET_CODE (XEXP (rhs, 1)) == CONST_INT
7654 && rtx_equal_for_field_assignment_p (XEXP (rhs, 0), dest))
7655 c1 = INTVAL (XEXP (rhs, 1)), other = lhs;
7656 else if (GET_CODE (lhs) == AND
7657 && GET_CODE (XEXP (lhs, 1)) == CONST_INT
7658 && rtx_equal_for_field_assignment_p (XEXP (lhs, 0), dest))
7659 c1 = INTVAL (XEXP (lhs, 1)), other = rhs;
7663 pos = get_pos_from_mask ((~c1) & GET_MODE_MASK (GET_MODE (dest)), &len);
7664 if (pos < 0 || pos + len > GET_MODE_BITSIZE (GET_MODE (dest))
7665 || GET_MODE_BITSIZE (GET_MODE (dest)) > HOST_BITS_PER_WIDE_INT
7666 || (c1 & nonzero_bits (other, GET_MODE (dest))) != 0)
7669 assign = make_extraction (VOIDmode, dest, pos, NULL_RTX, len, 1, 1, 0);
7673 /* The mode to use for the source is the mode of the assignment, or of
7674 what is inside a possible STRICT_LOW_PART. */
7675 mode = (GET_CODE (assign) == STRICT_LOW_PART
7676 ? GET_MODE (XEXP (assign, 0)) : GET_MODE (assign));
7678 /* Shift OTHER right POS places and make it the source, restricting it
7679 to the proper length and mode. */
7681 src = force_to_mode (simplify_shift_const (NULL_RTX, LSHIFTRT,
7682 GET_MODE (src), other, pos),
7684 GET_MODE_BITSIZE (mode) >= HOST_BITS_PER_WIDE_INT
7685 ? ~(unsigned HOST_WIDE_INT) 0
7686 : ((unsigned HOST_WIDE_INT) 1 << len) - 1,
7689 return gen_rtx_SET (VOIDmode, assign, src);
7692 /* See if X is of the form (+ (* a c) (* b c)) and convert to (* (+ a b) c)
7696 apply_distributive_law (x)
7699 enum rtx_code code = GET_CODE (x);
7700 rtx lhs, rhs, other;
7702 enum rtx_code inner_code;
7704 /* Distributivity is not true for floating point.
7705 It can change the value. So don't do it.
7706 -- rms and moshier@world.std.com. */
7707 if (FLOAT_MODE_P (GET_MODE (x)))
7710 /* The outer operation can only be one of the following: */
7711 if (code != IOR && code != AND && code != XOR
7712 && code != PLUS && code != MINUS)
7715 lhs = XEXP (x, 0), rhs = XEXP (x, 1);
7717 /* If either operand is a primitive we can't do anything, so get out
7719 if (GET_RTX_CLASS (GET_CODE (lhs)) == 'o'
7720 || GET_RTX_CLASS (GET_CODE (rhs)) == 'o')
7723 lhs = expand_compound_operation (lhs);
7724 rhs = expand_compound_operation (rhs);
7725 inner_code = GET_CODE (lhs);
7726 if (inner_code != GET_CODE (rhs))
7729 /* See if the inner and outer operations distribute. */
7736 /* These all distribute except over PLUS. */
7737 if (code == PLUS || code == MINUS)
7742 if (code != PLUS && code != MINUS)
7747 /* This is also a multiply, so it distributes over everything. */
7751 /* Non-paradoxical SUBREGs distributes over all operations, provided
7752 the inner modes and byte offsets are the same, this is an extraction
7753 of a low-order part, we don't convert an fp operation to int or
7754 vice versa, and we would not be converting a single-word
7755 operation into a multi-word operation. The latter test is not
7756 required, but it prevents generating unneeded multi-word operations.
7757 Some of the previous tests are redundant given the latter test, but
7758 are retained because they are required for correctness.
7760 We produce the result slightly differently in this case. */
7762 if (GET_MODE (SUBREG_REG (lhs)) != GET_MODE (SUBREG_REG (rhs))
7763 || SUBREG_BYTE (lhs) != SUBREG_BYTE (rhs)
7764 || ! subreg_lowpart_p (lhs)
7765 || (GET_MODE_CLASS (GET_MODE (lhs))
7766 != GET_MODE_CLASS (GET_MODE (SUBREG_REG (lhs))))
7767 || (GET_MODE_SIZE (GET_MODE (lhs))
7768 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs))))
7769 || GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs))) > UNITS_PER_WORD)
7772 tem = gen_binary (code, GET_MODE (SUBREG_REG (lhs)),
7773 SUBREG_REG (lhs), SUBREG_REG (rhs));
7774 return gen_lowpart_for_combine (GET_MODE (x), tem);
7780 /* Set LHS and RHS to the inner operands (A and B in the example
7781 above) and set OTHER to the common operand (C in the example).
7782 These is only one way to do this unless the inner operation is
7784 if (GET_RTX_CLASS (inner_code) == 'c'
7785 && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 0)))
7786 other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 1);
7787 else if (GET_RTX_CLASS (inner_code) == 'c'
7788 && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 1)))
7789 other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 0);
7790 else if (GET_RTX_CLASS (inner_code) == 'c'
7791 && rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 0)))
7792 other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 1);
7793 else if (rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 1)))
7794 other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 0);
7798 /* Form the new inner operation, seeing if it simplifies first. */
7799 tem = gen_binary (code, GET_MODE (x), lhs, rhs);
7801 /* There is one exception to the general way of distributing:
7802 (a ^ b) | (a ^ c) -> (~a) & (b ^ c) */
7803 if (code == XOR && inner_code == IOR)
7806 other = simplify_gen_unary (NOT, GET_MODE (x), other, GET_MODE (x));
7809 /* We may be able to continuing distributing the result, so call
7810 ourselves recursively on the inner operation before forming the
7811 outer operation, which we return. */
7812 return gen_binary (inner_code, GET_MODE (x),
7813 apply_distributive_law (tem), other);
7816 /* We have X, a logical `and' of VAROP with the constant CONSTOP, to be done
7819 Return an equivalent form, if different from X. Otherwise, return X. If
7820 X is zero, we are to always construct the equivalent form. */
7823 simplify_and_const_int (x, mode, varop, constop)
7825 enum machine_mode mode;
7827 unsigned HOST_WIDE_INT constop;
7829 unsigned HOST_WIDE_INT nonzero;
7832 /* Simplify VAROP knowing that we will be only looking at some of the
7834 varop = force_to_mode (varop, mode, constop, NULL_RTX, 0);
7836 /* If VAROP is a CLOBBER, we will fail so return it; if it is a
7837 CONST_INT, we are done. */
7838 if (GET_CODE (varop) == CLOBBER || GET_CODE (varop) == CONST_INT)
7841 /* See what bits may be nonzero in VAROP. Unlike the general case of
7842 a call to nonzero_bits, here we don't care about bits outside
7845 nonzero = nonzero_bits (varop, mode) & GET_MODE_MASK (mode);
7847 /* Turn off all bits in the constant that are known to already be zero.
7848 Thus, if the AND isn't needed at all, we will have CONSTOP == NONZERO_BITS
7849 which is tested below. */
7853 /* If we don't have any bits left, return zero. */
7857 /* If VAROP is a NEG of something known to be zero or 1 and CONSTOP is
7858 a power of two, we can replace this with a ASHIFT. */
7859 if (GET_CODE (varop) == NEG && nonzero_bits (XEXP (varop, 0), mode) == 1
7860 && (i = exact_log2 (constop)) >= 0)
7861 return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (varop, 0), i);
7863 /* If VAROP is an IOR or XOR, apply the AND to both branches of the IOR
7864 or XOR, then try to apply the distributive law. This may eliminate
7865 operations if either branch can be simplified because of the AND.
7866 It may also make some cases more complex, but those cases probably
7867 won't match a pattern either with or without this. */
7869 if (GET_CODE (varop) == IOR || GET_CODE (varop) == XOR)
7871 gen_lowpart_for_combine
7873 apply_distributive_law
7874 (gen_binary (GET_CODE (varop), GET_MODE (varop),
7875 simplify_and_const_int (NULL_RTX, GET_MODE (varop),
7876 XEXP (varop, 0), constop),
7877 simplify_and_const_int (NULL_RTX, GET_MODE (varop),
7878 XEXP (varop, 1), constop))));
7880 /* If VAROP is PLUS, and the constant is a mask of low bite, distribute
7881 the AND and see if one of the operands simplifies to zero. If so, we
7882 may eliminate it. */
7884 if (GET_CODE (varop) == PLUS
7885 && exact_log2 (constop + 1) >= 0)
7889 o0 = simplify_and_const_int (NULL_RTX, mode, XEXP (varop, 0), constop);
7890 o1 = simplify_and_const_int (NULL_RTX, mode, XEXP (varop, 1), constop);
7891 if (o0 == const0_rtx)
7893 if (o1 == const0_rtx)
7897 /* Get VAROP in MODE. Try to get a SUBREG if not. Don't make a new SUBREG
7898 if we already had one (just check for the simplest cases). */
7899 if (x && GET_CODE (XEXP (x, 0)) == SUBREG
7900 && GET_MODE (XEXP (x, 0)) == mode
7901 && SUBREG_REG (XEXP (x, 0)) == varop)
7902 varop = XEXP (x, 0);
7904 varop = gen_lowpart_for_combine (mode, varop);
7906 /* If we can't make the SUBREG, try to return what we were given. */
7907 if (GET_CODE (varop) == CLOBBER)
7908 return x ? x : varop;
7910 /* If we are only masking insignificant bits, return VAROP. */
7911 if (constop == nonzero)
7915 /* Otherwise, return an AND. */
7916 constop = trunc_int_for_mode (constop, mode);
7917 /* See how much, if any, of X we can use. */
7918 if (x == 0 || GET_CODE (x) != AND || GET_MODE (x) != mode)
7919 x = gen_binary (AND, mode, varop, GEN_INT (constop));
7923 if (GET_CODE (XEXP (x, 1)) != CONST_INT
7924 || (unsigned HOST_WIDE_INT) INTVAL (XEXP (x, 1)) != constop)
7925 SUBST (XEXP (x, 1), GEN_INT (constop));
7927 SUBST (XEXP (x, 0), varop);
7934 /* We let num_sign_bit_copies recur into nonzero_bits as that is useful.
7935 We don't let nonzero_bits recur into num_sign_bit_copies, because that
7936 is less useful. We can't allow both, because that results in exponential
7937 run time recursion. There is a nullstone testcase that triggered
7938 this. This macro avoids accidental uses of num_sign_bit_copies. */
7939 #define num_sign_bit_copies()
7941 /* Given an expression, X, compute which bits in X can be non-zero.
7942 We don't care about bits outside of those defined in MODE.
7944 For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is
7945 a shift, AND, or zero_extract, we can do better. */
7947 static unsigned HOST_WIDE_INT
7948 nonzero_bits (x, mode)
7950 enum machine_mode mode;
7952 unsigned HOST_WIDE_INT nonzero = GET_MODE_MASK (mode);
7953 unsigned HOST_WIDE_INT inner_nz;
7955 unsigned int mode_width = GET_MODE_BITSIZE (mode);
7958 /* For floating-point values, assume all bits are needed. */
7959 if (FLOAT_MODE_P (GET_MODE (x)) || FLOAT_MODE_P (mode))
7962 /* If X is wider than MODE, use its mode instead. */
7963 if (GET_MODE_BITSIZE (GET_MODE (x)) > mode_width)
7965 mode = GET_MODE (x);
7966 nonzero = GET_MODE_MASK (mode);
7967 mode_width = GET_MODE_BITSIZE (mode);
7970 if (mode_width > HOST_BITS_PER_WIDE_INT)
7971 /* Our only callers in this case look for single bit values. So
7972 just return the mode mask. Those tests will then be false. */
7975 #ifndef WORD_REGISTER_OPERATIONS
7976 /* If MODE is wider than X, but both are a single word for both the host
7977 and target machines, we can compute this from which bits of the
7978 object might be nonzero in its own mode, taking into account the fact
7979 that on many CISC machines, accessing an object in a wider mode
7980 causes the high-order bits to become undefined. So they are
7981 not known to be zero. */
7983 if (GET_MODE (x) != VOIDmode && GET_MODE (x) != mode
7984 && GET_MODE_BITSIZE (GET_MODE (x)) <= BITS_PER_WORD
7985 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
7986 && GET_MODE_BITSIZE (mode) > GET_MODE_BITSIZE (GET_MODE (x)))
7988 nonzero &= nonzero_bits (x, GET_MODE (x));
7989 nonzero |= GET_MODE_MASK (mode) & ~GET_MODE_MASK (GET_MODE (x));
7994 code = GET_CODE (x);
7998 #if defined(POINTERS_EXTEND_UNSIGNED) && !defined(HAVE_ptr_extend)
7999 /* If pointers extend unsigned and this is a pointer in Pmode, say that
8000 all the bits above ptr_mode are known to be zero. */
8001 if (POINTERS_EXTEND_UNSIGNED && GET_MODE (x) == Pmode
8003 nonzero &= GET_MODE_MASK (ptr_mode);
8006 /* Include declared information about alignment of pointers. */
8007 /* ??? We don't properly preserve REG_POINTER changes across
8008 pointer-to-integer casts, so we can't trust it except for
8009 things that we know must be pointers. See execute/960116-1.c. */
8010 if ((x == stack_pointer_rtx
8011 || x == frame_pointer_rtx
8012 || x == arg_pointer_rtx)
8013 && REGNO_POINTER_ALIGN (REGNO (x)))
8015 unsigned HOST_WIDE_INT alignment
8016 = REGNO_POINTER_ALIGN (REGNO (x)) / BITS_PER_UNIT;
8018 #ifdef PUSH_ROUNDING
8019 /* If PUSH_ROUNDING is defined, it is possible for the
8020 stack to be momentarily aligned only to that amount,
8021 so we pick the least alignment. */
8022 if (x == stack_pointer_rtx && PUSH_ARGS)
8023 alignment = MIN (PUSH_ROUNDING (1), alignment);
8026 nonzero &= ~(alignment - 1);
8029 /* If X is a register whose nonzero bits value is current, use it.
8030 Otherwise, if X is a register whose value we can find, use that
8031 value. Otherwise, use the previously-computed global nonzero bits
8032 for this register. */
8034 if (reg_last_set_value[REGNO (x)] != 0
8035 && reg_last_set_mode[REGNO (x)] == mode
8036 && (reg_last_set_label[REGNO (x)] == label_tick
8037 || (REGNO (x) >= FIRST_PSEUDO_REGISTER
8038 && REG_N_SETS (REGNO (x)) == 1
8039 && ! REGNO_REG_SET_P (BASIC_BLOCK (0)->global_live_at_start,
8041 && INSN_CUID (reg_last_set[REGNO (x)]) < subst_low_cuid)
8042 return reg_last_set_nonzero_bits[REGNO (x)] & nonzero;
8044 tem = get_last_value (x);
8048 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
8049 /* If X is narrower than MODE and TEM is a non-negative
8050 constant that would appear negative in the mode of X,
8051 sign-extend it for use in reg_nonzero_bits because some
8052 machines (maybe most) will actually do the sign-extension
8053 and this is the conservative approach.
8055 ??? For 2.5, try to tighten up the MD files in this regard
8056 instead of this kludge. */
8058 if (GET_MODE_BITSIZE (GET_MODE (x)) < mode_width
8059 && GET_CODE (tem) == CONST_INT
8061 && 0 != (INTVAL (tem)
8062 & ((HOST_WIDE_INT) 1
8063 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
8064 tem = GEN_INT (INTVAL (tem)
8065 | ((HOST_WIDE_INT) (-1)
8066 << GET_MODE_BITSIZE (GET_MODE (x))));
8068 return nonzero_bits (tem, mode) & nonzero;
8070 else if (nonzero_sign_valid && reg_nonzero_bits[REGNO (x)])
8072 unsigned HOST_WIDE_INT mask = reg_nonzero_bits[REGNO (x)];
8074 if (GET_MODE_BITSIZE (GET_MODE (x)) < mode_width)
8075 /* We don't know anything about the upper bits. */
8076 mask |= GET_MODE_MASK (mode) ^ GET_MODE_MASK (GET_MODE (x));
8077 return nonzero & mask;
8083 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
8084 /* If X is negative in MODE, sign-extend the value. */
8085 if (INTVAL (x) > 0 && mode_width < BITS_PER_WORD
8086 && 0 != (INTVAL (x) & ((HOST_WIDE_INT) 1 << (mode_width - 1))))
8087 return (INTVAL (x) | ((HOST_WIDE_INT) (-1) << mode_width));
8093 #ifdef LOAD_EXTEND_OP
8094 /* In many, if not most, RISC machines, reading a byte from memory
8095 zeros the rest of the register. Noticing that fact saves a lot
8096 of extra zero-extends. */
8097 if (LOAD_EXTEND_OP (GET_MODE (x)) == ZERO_EXTEND)
8098 nonzero &= GET_MODE_MASK (GET_MODE (x));
8103 case UNEQ: case LTGT:
8104 case GT: case GTU: case UNGT:
8105 case LT: case LTU: case UNLT:
8106 case GE: case GEU: case UNGE:
8107 case LE: case LEU: case UNLE:
8108 case UNORDERED: case ORDERED:
8110 /* If this produces an integer result, we know which bits are set.
8111 Code here used to clear bits outside the mode of X, but that is
8114 if (GET_MODE_CLASS (mode) == MODE_INT
8115 && mode_width <= HOST_BITS_PER_WIDE_INT)
8116 nonzero = STORE_FLAG_VALUE;
8121 /* Disabled to avoid exponential mutual recursion between nonzero_bits
8122 and num_sign_bit_copies. */
8123 if (num_sign_bit_copies (XEXP (x, 0), GET_MODE (x))
8124 == GET_MODE_BITSIZE (GET_MODE (x)))
8128 if (GET_MODE_SIZE (GET_MODE (x)) < mode_width)
8129 nonzero |= (GET_MODE_MASK (mode) & ~GET_MODE_MASK (GET_MODE (x)));
8134 /* Disabled to avoid exponential mutual recursion between nonzero_bits
8135 and num_sign_bit_copies. */
8136 if (num_sign_bit_copies (XEXP (x, 0), GET_MODE (x))
8137 == GET_MODE_BITSIZE (GET_MODE (x)))
8143 nonzero &= (nonzero_bits (XEXP (x, 0), mode) & GET_MODE_MASK (mode));
8147 nonzero &= nonzero_bits (XEXP (x, 0), mode);
8148 if (GET_MODE (XEXP (x, 0)) != VOIDmode)
8149 nonzero &= GET_MODE_MASK (GET_MODE (XEXP (x, 0)));
8153 /* If the sign bit is known clear, this is the same as ZERO_EXTEND.
8154 Otherwise, show all the bits in the outer mode but not the inner
8156 inner_nz = nonzero_bits (XEXP (x, 0), mode);
8157 if (GET_MODE (XEXP (x, 0)) != VOIDmode)
8159 inner_nz &= GET_MODE_MASK (GET_MODE (XEXP (x, 0)));
8161 & (((HOST_WIDE_INT) 1
8162 << (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - 1))))
8163 inner_nz |= (GET_MODE_MASK (mode)
8164 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0))));
8167 nonzero &= inner_nz;
8171 nonzero &= (nonzero_bits (XEXP (x, 0), mode)
8172 & nonzero_bits (XEXP (x, 1), mode));
8176 case UMIN: case UMAX: case SMIN: case SMAX:
8177 nonzero &= (nonzero_bits (XEXP (x, 0), mode)
8178 | nonzero_bits (XEXP (x, 1), mode));
8181 case PLUS: case MINUS:
8183 case DIV: case UDIV:
8184 case MOD: case UMOD:
8185 /* We can apply the rules of arithmetic to compute the number of
8186 high- and low-order zero bits of these operations. We start by
8187 computing the width (position of the highest-order non-zero bit)
8188 and the number of low-order zero bits for each value. */
8190 unsigned HOST_WIDE_INT nz0 = nonzero_bits (XEXP (x, 0), mode);
8191 unsigned HOST_WIDE_INT nz1 = nonzero_bits (XEXP (x, 1), mode);
8192 int width0 = floor_log2 (nz0) + 1;
8193 int width1 = floor_log2 (nz1) + 1;
8194 int low0 = floor_log2 (nz0 & -nz0);
8195 int low1 = floor_log2 (nz1 & -nz1);
8196 HOST_WIDE_INT op0_maybe_minusp
8197 = (nz0 & ((HOST_WIDE_INT) 1 << (mode_width - 1)));
8198 HOST_WIDE_INT op1_maybe_minusp
8199 = (nz1 & ((HOST_WIDE_INT) 1 << (mode_width - 1)));
8200 unsigned int result_width = mode_width;
8206 result_width = MAX (width0, width1) + 1;
8207 result_low = MIN (low0, low1);
8210 result_low = MIN (low0, low1);
8213 result_width = width0 + width1;
8214 result_low = low0 + low1;
8219 if (! op0_maybe_minusp && ! op1_maybe_minusp)
8220 result_width = width0;
8225 result_width = width0;
8230 if (! op0_maybe_minusp && ! op1_maybe_minusp)
8231 result_width = MIN (width0, width1);
8232 result_low = MIN (low0, low1);
8237 result_width = MIN (width0, width1);
8238 result_low = MIN (low0, low1);
8244 if (result_width < mode_width)
8245 nonzero &= ((HOST_WIDE_INT) 1 << result_width) - 1;
8248 nonzero &= ~(((HOST_WIDE_INT) 1 << result_low) - 1);
8250 #ifdef POINTERS_EXTEND_UNSIGNED
8251 /* If pointers extend unsigned and this is an addition or subtraction
8252 to a pointer in Pmode, all the bits above ptr_mode are known to be
8254 if (POINTERS_EXTEND_UNSIGNED > 0 && GET_MODE (x) == Pmode
8255 && (code == PLUS || code == MINUS)
8256 && GET_CODE (XEXP (x, 0)) == REG && REG_POINTER (XEXP (x, 0)))
8257 nonzero &= GET_MODE_MASK (ptr_mode);
8263 if (GET_CODE (XEXP (x, 1)) == CONST_INT
8264 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT)
8265 nonzero &= ((HOST_WIDE_INT) 1 << INTVAL (XEXP (x, 1))) - 1;
8269 /* If this is a SUBREG formed for a promoted variable that has
8270 been zero-extended, we know that at least the high-order bits
8271 are zero, though others might be too. */
8273 if (SUBREG_PROMOTED_VAR_P (x) && SUBREG_PROMOTED_UNSIGNED_P (x) > 0)
8274 nonzero = (GET_MODE_MASK (GET_MODE (x))
8275 & nonzero_bits (SUBREG_REG (x), GET_MODE (x)));
8277 /* If the inner mode is a single word for both the host and target
8278 machines, we can compute this from which bits of the inner
8279 object might be nonzero. */
8280 if (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x))) <= BITS_PER_WORD
8281 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x)))
8282 <= HOST_BITS_PER_WIDE_INT))
8284 nonzero &= nonzero_bits (SUBREG_REG (x), mode);
8286 #if defined (WORD_REGISTER_OPERATIONS) && defined (LOAD_EXTEND_OP)
8287 /* If this is a typical RISC machine, we only have to worry
8288 about the way loads are extended. */
8289 if (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (x))) == SIGN_EXTEND
8291 & (((unsigned HOST_WIDE_INT) 1
8292 << (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x))) - 1))))
8294 : LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (x))) != ZERO_EXTEND)
8297 /* On many CISC machines, accessing an object in a wider mode
8298 causes the high-order bits to become undefined. So they are
8299 not known to be zero. */
8300 if (GET_MODE_SIZE (GET_MODE (x))
8301 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
8302 nonzero |= (GET_MODE_MASK (GET_MODE (x))
8303 & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (x))));
8312 /* The nonzero bits are in two classes: any bits within MODE
8313 that aren't in GET_MODE (x) are always significant. The rest of the
8314 nonzero bits are those that are significant in the operand of
8315 the shift when shifted the appropriate number of bits. This
8316 shows that high-order bits are cleared by the right shift and
8317 low-order bits by left shifts. */
8318 if (GET_CODE (XEXP (x, 1)) == CONST_INT
8319 && INTVAL (XEXP (x, 1)) >= 0
8320 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT)
8322 enum machine_mode inner_mode = GET_MODE (x);
8323 unsigned int width = GET_MODE_BITSIZE (inner_mode);
8324 int count = INTVAL (XEXP (x, 1));
8325 unsigned HOST_WIDE_INT mode_mask = GET_MODE_MASK (inner_mode);
8326 unsigned HOST_WIDE_INT op_nonzero = nonzero_bits (XEXP (x, 0), mode);
8327 unsigned HOST_WIDE_INT inner = op_nonzero & mode_mask;
8328 unsigned HOST_WIDE_INT outer = 0;
8330 if (mode_width > width)
8331 outer = (op_nonzero & nonzero & ~mode_mask);
8333 if (code == LSHIFTRT)
8335 else if (code == ASHIFTRT)
8339 /* If the sign bit may have been nonzero before the shift, we
8340 need to mark all the places it could have been copied to
8341 by the shift as possibly nonzero. */
8342 if (inner & ((HOST_WIDE_INT) 1 << (width - 1 - count)))
8343 inner |= (((HOST_WIDE_INT) 1 << count) - 1) << (width - count);
8345 else if (code == ASHIFT)
8348 inner = ((inner << (count % width)
8349 | (inner >> (width - (count % width)))) & mode_mask);
8351 nonzero &= (outer | inner);
8356 /* This is at most the number of bits in the mode. */
8357 nonzero = ((HOST_WIDE_INT) 1 << (floor_log2 (mode_width) + 1)) - 1;
8361 nonzero &= (nonzero_bits (XEXP (x, 1), mode)
8362 | nonzero_bits (XEXP (x, 2), mode));
8372 /* See the macro definition above. */
8373 #undef num_sign_bit_copies
8375 /* Return the number of bits at the high-order end of X that are known to
8376 be equal to the sign bit. X will be used in mode MODE; if MODE is
8377 VOIDmode, X will be used in its own mode. The returned value will always
8378 be between 1 and the number of bits in MODE. */
8381 num_sign_bit_copies (x, mode)
8383 enum machine_mode mode;
8385 enum rtx_code code = GET_CODE (x);
8386 unsigned int bitwidth;
8387 int num0, num1, result;
8388 unsigned HOST_WIDE_INT nonzero;
8391 /* If we weren't given a mode, use the mode of X. If the mode is still
8392 VOIDmode, we don't know anything. Likewise if one of the modes is
8395 if (mode == VOIDmode)
8396 mode = GET_MODE (x);
8398 if (mode == VOIDmode || FLOAT_MODE_P (mode) || FLOAT_MODE_P (GET_MODE (x)))
8401 bitwidth = GET_MODE_BITSIZE (mode);
8403 /* For a smaller object, just ignore the high bits. */
8404 if (bitwidth < GET_MODE_BITSIZE (GET_MODE (x)))
8406 num0 = num_sign_bit_copies (x, GET_MODE (x));
8408 num0 - (int) (GET_MODE_BITSIZE (GET_MODE (x)) - bitwidth));
8411 if (GET_MODE (x) != VOIDmode && bitwidth > GET_MODE_BITSIZE (GET_MODE (x)))
8413 #ifndef WORD_REGISTER_OPERATIONS
8414 /* If this machine does not do all register operations on the entire
8415 register and MODE is wider than the mode of X, we can say nothing
8416 at all about the high-order bits. */
8419 /* Likewise on machines that do, if the mode of the object is smaller
8420 than a word and loads of that size don't sign extend, we can say
8421 nothing about the high order bits. */
8422 if (GET_MODE_BITSIZE (GET_MODE (x)) < BITS_PER_WORD
8423 #ifdef LOAD_EXTEND_OP
8424 && LOAD_EXTEND_OP (GET_MODE (x)) != SIGN_EXTEND
8435 #if defined(POINTERS_EXTEND_UNSIGNED) && !defined(HAVE_ptr_extend)
8436 /* If pointers extend signed and this is a pointer in Pmode, say that
8437 all the bits above ptr_mode are known to be sign bit copies. */
8438 if (! POINTERS_EXTEND_UNSIGNED && GET_MODE (x) == Pmode && mode == Pmode
8440 return GET_MODE_BITSIZE (Pmode) - GET_MODE_BITSIZE (ptr_mode) + 1;
8443 if (reg_last_set_value[REGNO (x)] != 0
8444 && reg_last_set_mode[REGNO (x)] == mode
8445 && (reg_last_set_label[REGNO (x)] == label_tick
8446 || (REGNO (x) >= FIRST_PSEUDO_REGISTER
8447 && REG_N_SETS (REGNO (x)) == 1
8448 && ! REGNO_REG_SET_P (BASIC_BLOCK (0)->global_live_at_start,
8450 && INSN_CUID (reg_last_set[REGNO (x)]) < subst_low_cuid)
8451 return reg_last_set_sign_bit_copies[REGNO (x)];
8453 tem = get_last_value (x);
8455 return num_sign_bit_copies (tem, mode);
8457 if (nonzero_sign_valid && reg_sign_bit_copies[REGNO (x)] != 0
8458 && GET_MODE_BITSIZE (GET_MODE (x)) == bitwidth)
8459 return reg_sign_bit_copies[REGNO (x)];
8463 #ifdef LOAD_EXTEND_OP
8464 /* Some RISC machines sign-extend all loads of smaller than a word. */
8465 if (LOAD_EXTEND_OP (GET_MODE (x)) == SIGN_EXTEND)
8466 return MAX (1, ((int) bitwidth
8467 - (int) GET_MODE_BITSIZE (GET_MODE (x)) + 1));
8472 /* If the constant is negative, take its 1's complement and remask.
8473 Then see how many zero bits we have. */
8474 nonzero = INTVAL (x) & GET_MODE_MASK (mode);
8475 if (bitwidth <= HOST_BITS_PER_WIDE_INT
8476 && (nonzero & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0)
8477 nonzero = (~nonzero) & GET_MODE_MASK (mode);
8479 return (nonzero == 0 ? bitwidth : bitwidth - floor_log2 (nonzero) - 1);
8482 /* If this is a SUBREG for a promoted object that is sign-extended
8483 and we are looking at it in a wider mode, we know that at least the
8484 high-order bits are known to be sign bit copies. */
8486 if (SUBREG_PROMOTED_VAR_P (x) && ! SUBREG_PROMOTED_UNSIGNED_P (x))
8488 num0 = num_sign_bit_copies (SUBREG_REG (x), mode);
8489 return MAX ((int) bitwidth
8490 - (int) GET_MODE_BITSIZE (GET_MODE (x)) + 1,
8494 /* For a smaller object, just ignore the high bits. */
8495 if (bitwidth <= GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x))))
8497 num0 = num_sign_bit_copies (SUBREG_REG (x), VOIDmode);
8498 return MAX (1, (num0
8499 - (int) (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x)))
8503 #ifdef WORD_REGISTER_OPERATIONS
8504 #ifdef LOAD_EXTEND_OP
8505 /* For paradoxical SUBREGs on machines where all register operations
8506 affect the entire register, just look inside. Note that we are
8507 passing MODE to the recursive call, so the number of sign bit copies
8508 will remain relative to that mode, not the inner mode. */
8510 /* This works only if loads sign extend. Otherwise, if we get a
8511 reload for the inner part, it may be loaded from the stack, and
8512 then we lose all sign bit copies that existed before the store
8515 if ((GET_MODE_SIZE (GET_MODE (x))
8516 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
8517 && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (x))) == SIGN_EXTEND)
8518 return num_sign_bit_copies (SUBREG_REG (x), mode);
8524 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
8525 return MAX (1, (int) bitwidth - INTVAL (XEXP (x, 1)));
8529 return (bitwidth - GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
8530 + num_sign_bit_copies (XEXP (x, 0), VOIDmode));
8533 /* For a smaller object, just ignore the high bits. */
8534 num0 = num_sign_bit_copies (XEXP (x, 0), VOIDmode);
8535 return MAX (1, (num0 - (int) (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
8539 return num_sign_bit_copies (XEXP (x, 0), mode);
8541 case ROTATE: case ROTATERT:
8542 /* If we are rotating left by a number of bits less than the number
8543 of sign bit copies, we can just subtract that amount from the
8545 if (GET_CODE (XEXP (x, 1)) == CONST_INT
8546 && INTVAL (XEXP (x, 1)) >= 0
8547 && INTVAL (XEXP (x, 1)) < (int) bitwidth)
8549 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
8550 return MAX (1, num0 - (code == ROTATE ? INTVAL (XEXP (x, 1))
8551 : (int) bitwidth - INTVAL (XEXP (x, 1))));
8556 /* In general, this subtracts one sign bit copy. But if the value
8557 is known to be positive, the number of sign bit copies is the
8558 same as that of the input. Finally, if the input has just one bit
8559 that might be nonzero, all the bits are copies of the sign bit. */
8560 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
8561 if (bitwidth > HOST_BITS_PER_WIDE_INT)
8562 return num0 > 1 ? num0 - 1 : 1;
8564 nonzero = nonzero_bits (XEXP (x, 0), mode);
8569 && (((HOST_WIDE_INT) 1 << (bitwidth - 1)) & nonzero))
8574 case IOR: case AND: case XOR:
8575 case SMIN: case SMAX: case UMIN: case UMAX:
8576 /* Logical operations will preserve the number of sign-bit copies.
8577 MIN and MAX operations always return one of the operands. */
8578 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
8579 num1 = num_sign_bit_copies (XEXP (x, 1), mode);
8580 return MIN (num0, num1);
8582 case PLUS: case MINUS:
8583 /* For addition and subtraction, we can have a 1-bit carry. However,
8584 if we are subtracting 1 from a positive number, there will not
8585 be such a carry. Furthermore, if the positive number is known to
8586 be 0 or 1, we know the result is either -1 or 0. */
8588 if (code == PLUS && XEXP (x, 1) == constm1_rtx
8589 && bitwidth <= HOST_BITS_PER_WIDE_INT)
8591 nonzero = nonzero_bits (XEXP (x, 0), mode);
8592 if ((((HOST_WIDE_INT) 1 << (bitwidth - 1)) & nonzero) == 0)
8593 return (nonzero == 1 || nonzero == 0 ? bitwidth
8594 : bitwidth - floor_log2 (nonzero) - 1);
8597 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
8598 num1 = num_sign_bit_copies (XEXP (x, 1), mode);
8599 result = MAX (1, MIN (num0, num1) - 1);
8601 #ifdef POINTERS_EXTEND_UNSIGNED
8602 /* If pointers extend signed and this is an addition or subtraction
8603 to a pointer in Pmode, all the bits above ptr_mode are known to be
8605 if (! POINTERS_EXTEND_UNSIGNED && GET_MODE (x) == Pmode
8606 && (code == PLUS || code == MINUS)
8607 && GET_CODE (XEXP (x, 0)) == REG && REG_POINTER (XEXP (x, 0)))
8608 result = MAX ((int) (GET_MODE_BITSIZE (Pmode)
8609 - GET_MODE_BITSIZE (ptr_mode) + 1),
8615 /* The number of bits of the product is the sum of the number of
8616 bits of both terms. However, unless one of the terms if known
8617 to be positive, we must allow for an additional bit since negating
8618 a negative number can remove one sign bit copy. */
8620 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
8621 num1 = num_sign_bit_copies (XEXP (x, 1), mode);
8623 result = bitwidth - (bitwidth - num0) - (bitwidth - num1);
8625 && (bitwidth > HOST_BITS_PER_WIDE_INT
8626 || (((nonzero_bits (XEXP (x, 0), mode)
8627 & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0)
8628 && ((nonzero_bits (XEXP (x, 1), mode)
8629 & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0))))
8632 return MAX (1, result);
8635 /* The result must be <= the first operand. If the first operand
8636 has the high bit set, we know nothing about the number of sign
8638 if (bitwidth > HOST_BITS_PER_WIDE_INT)
8640 else if ((nonzero_bits (XEXP (x, 0), mode)
8641 & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0)
8644 return num_sign_bit_copies (XEXP (x, 0), mode);
8647 /* The result must be <= the second operand. */
8648 return num_sign_bit_copies (XEXP (x, 1), mode);
8651 /* Similar to unsigned division, except that we have to worry about
8652 the case where the divisor is negative, in which case we have
8654 result = num_sign_bit_copies (XEXP (x, 0), mode);
8656 && (bitwidth > HOST_BITS_PER_WIDE_INT
8657 || (nonzero_bits (XEXP (x, 1), mode)
8658 & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0))
8664 result = num_sign_bit_copies (XEXP (x, 1), mode);
8666 && (bitwidth > HOST_BITS_PER_WIDE_INT
8667 || (nonzero_bits (XEXP (x, 1), mode)
8668 & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0))
8674 /* Shifts by a constant add to the number of bits equal to the
8676 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
8677 if (GET_CODE (XEXP (x, 1)) == CONST_INT
8678 && INTVAL (XEXP (x, 1)) > 0)
8679 num0 = MIN ((int) bitwidth, num0 + INTVAL (XEXP (x, 1)));
8684 /* Left shifts destroy copies. */
8685 if (GET_CODE (XEXP (x, 1)) != CONST_INT
8686 || INTVAL (XEXP (x, 1)) < 0
8687 || INTVAL (XEXP (x, 1)) >= (int) bitwidth)
8690 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
8691 return MAX (1, num0 - INTVAL (XEXP (x, 1)));
8694 num0 = num_sign_bit_copies (XEXP (x, 1), mode);
8695 num1 = num_sign_bit_copies (XEXP (x, 2), mode);
8696 return MIN (num0, num1);
8698 case EQ: case NE: case GE: case GT: case LE: case LT:
8699 case UNEQ: case LTGT: case UNGE: case UNGT: case UNLE: case UNLT:
8700 case GEU: case GTU: case LEU: case LTU:
8701 case UNORDERED: case ORDERED:
8702 /* If the constant is negative, take its 1's complement and remask.
8703 Then see how many zero bits we have. */
8704 nonzero = STORE_FLAG_VALUE;
8705 if (bitwidth <= HOST_BITS_PER_WIDE_INT
8706 && (nonzero & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0)
8707 nonzero = (~nonzero) & GET_MODE_MASK (mode);
8709 return (nonzero == 0 ? bitwidth : bitwidth - floor_log2 (nonzero) - 1);
8716 /* If we haven't been able to figure it out by one of the above rules,
8717 see if some of the high-order bits are known to be zero. If so,
8718 count those bits and return one less than that amount. If we can't
8719 safely compute the mask for this mode, always return BITWIDTH. */
8721 if (bitwidth > HOST_BITS_PER_WIDE_INT)
8724 nonzero = nonzero_bits (x, mode);
8725 return (nonzero & ((HOST_WIDE_INT) 1 << (bitwidth - 1))
8726 ? 1 : bitwidth - floor_log2 (nonzero) - 1);
8729 /* Return the number of "extended" bits there are in X, when interpreted
8730 as a quantity in MODE whose signedness is indicated by UNSIGNEDP. For
8731 unsigned quantities, this is the number of high-order zero bits.
8732 For signed quantities, this is the number of copies of the sign bit
8733 minus 1. In both case, this function returns the number of "spare"
8734 bits. For example, if two quantities for which this function returns
8735 at least 1 are added, the addition is known not to overflow.
8737 This function will always return 0 unless called during combine, which
8738 implies that it must be called from a define_split. */
8741 extended_count (x, mode, unsignedp)
8743 enum machine_mode mode;
8746 if (nonzero_sign_valid == 0)
8750 ? (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
8751 ? (GET_MODE_BITSIZE (mode) - 1
8752 - floor_log2 (nonzero_bits (x, mode)))
8754 : num_sign_bit_copies (x, mode) - 1);
8757 /* This function is called from `simplify_shift_const' to merge two
8758 outer operations. Specifically, we have already found that we need
8759 to perform operation *POP0 with constant *PCONST0 at the outermost
8760 position. We would now like to also perform OP1 with constant CONST1
8761 (with *POP0 being done last).
8763 Return 1 if we can do the operation and update *POP0 and *PCONST0 with
8764 the resulting operation. *PCOMP_P is set to 1 if we would need to
8765 complement the innermost operand, otherwise it is unchanged.
8767 MODE is the mode in which the operation will be done. No bits outside
8768 the width of this mode matter. It is assumed that the width of this mode
8769 is smaller than or equal to HOST_BITS_PER_WIDE_INT.
8771 If *POP0 or OP1 are NIL, it means no operation is required. Only NEG, PLUS,
8772 IOR, XOR, and AND are supported. We may set *POP0 to SET if the proper
8773 result is simply *PCONST0.
8775 If the resulting operation cannot be expressed as one operation, we
8776 return 0 and do not change *POP0, *PCONST0, and *PCOMP_P. */
8779 merge_outer_ops (pop0, pconst0, op1, const1, mode, pcomp_p)
8780 enum rtx_code *pop0;
8781 HOST_WIDE_INT *pconst0;
8783 HOST_WIDE_INT const1;
8784 enum machine_mode mode;
8787 enum rtx_code op0 = *pop0;
8788 HOST_WIDE_INT const0 = *pconst0;
8790 const0 &= GET_MODE_MASK (mode);
8791 const1 &= GET_MODE_MASK (mode);
8793 /* If OP0 is an AND, clear unimportant bits in CONST1. */
8797 /* If OP0 or OP1 is NIL, this is easy. Similarly if they are the same or
8800 if (op1 == NIL || op0 == SET)
8803 else if (op0 == NIL)
8804 op0 = op1, const0 = const1;
8806 else if (op0 == op1)
8830 /* Otherwise, if either is a PLUS or NEG, we can't do anything. */
8831 else if (op0 == PLUS || op1 == PLUS || op0 == NEG || op1 == NEG)
8834 /* If the two constants aren't the same, we can't do anything. The
8835 remaining six cases can all be done. */
8836 else if (const0 != const1)
8844 /* (a & b) | b == b */
8846 else /* op1 == XOR */
8847 /* (a ^ b) | b == a | b */
8853 /* (a & b) ^ b == (~a) & b */
8854 op0 = AND, *pcomp_p = 1;
8855 else /* op1 == IOR */
8856 /* (a | b) ^ b == a & ~b */
8857 op0 = AND, *pconst0 = ~const0;
8862 /* (a | b) & b == b */
8864 else /* op1 == XOR */
8865 /* (a ^ b) & b) == (~a) & b */
8872 /* Check for NO-OP cases. */
8873 const0 &= GET_MODE_MASK (mode);
8875 && (op0 == IOR || op0 == XOR || op0 == PLUS))
8877 else if (const0 == 0 && op0 == AND)
8879 else if ((unsigned HOST_WIDE_INT) const0 == GET_MODE_MASK (mode)
8883 /* ??? Slightly redundant with the above mask, but not entirely.
8884 Moving this above means we'd have to sign-extend the mode mask
8885 for the final test. */
8886 const0 = trunc_int_for_mode (const0, mode);
8894 /* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift.
8895 The result of the shift is RESULT_MODE. X, if non-zero, is an expression
8896 that we started with.
8898 The shift is normally computed in the widest mode we find in VAROP, as
8899 long as it isn't a different number of words than RESULT_MODE. Exceptions
8900 are ASHIFTRT and ROTATE, which are always done in their original mode, */
8903 simplify_shift_const (x, code, result_mode, varop, orig_count)
8906 enum machine_mode result_mode;
8910 enum rtx_code orig_code = code;
8913 enum machine_mode mode = result_mode;
8914 enum machine_mode shift_mode, tmode;
8915 unsigned int mode_words
8916 = (GET_MODE_SIZE (mode) + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD;
8917 /* We form (outer_op (code varop count) (outer_const)). */
8918 enum rtx_code outer_op = NIL;
8919 HOST_WIDE_INT outer_const = 0;
8921 int complement_p = 0;
8924 /* Make sure and truncate the "natural" shift on the way in. We don't
8925 want to do this inside the loop as it makes it more difficult to
8927 #ifdef SHIFT_COUNT_TRUNCATED
8928 if (SHIFT_COUNT_TRUNCATED)
8929 orig_count &= GET_MODE_BITSIZE (mode) - 1;
8932 /* If we were given an invalid count, don't do anything except exactly
8933 what was requested. */
8935 if (orig_count < 0 || orig_count >= (int) GET_MODE_BITSIZE (mode))
8940 return gen_rtx_fmt_ee (code, mode, varop, GEN_INT (orig_count));
8945 /* Unless one of the branches of the `if' in this loop does a `continue',
8946 we will `break' the loop after the `if'. */
8950 /* If we have an operand of (clobber (const_int 0)), just return that
8952 if (GET_CODE (varop) == CLOBBER)
8955 /* If we discovered we had to complement VAROP, leave. Making a NOT
8956 here would cause an infinite loop. */
8960 /* Convert ROTATERT to ROTATE. */
8961 if (code == ROTATERT)
8962 code = ROTATE, count = GET_MODE_BITSIZE (result_mode) - count;
8964 /* We need to determine what mode we will do the shift in. If the
8965 shift is a right shift or a ROTATE, we must always do it in the mode
8966 it was originally done in. Otherwise, we can do it in MODE, the
8967 widest mode encountered. */
8969 = (code == ASHIFTRT || code == LSHIFTRT || code == ROTATE
8970 ? result_mode : mode);
8972 /* Handle cases where the count is greater than the size of the mode
8973 minus 1. For ASHIFT, use the size minus one as the count (this can
8974 occur when simplifying (lshiftrt (ashiftrt ..))). For rotates,
8975 take the count modulo the size. For other shifts, the result is
8978 Since these shifts are being produced by the compiler by combining
8979 multiple operations, each of which are defined, we know what the
8980 result is supposed to be. */
8982 if (count > GET_MODE_BITSIZE (shift_mode) - 1)
8984 if (code == ASHIFTRT)
8985 count = GET_MODE_BITSIZE (shift_mode) - 1;
8986 else if (code == ROTATE || code == ROTATERT)
8987 count %= GET_MODE_BITSIZE (shift_mode);
8990 /* We can't simply return zero because there may be an
8998 /* An arithmetic right shift of a quantity known to be -1 or 0
9000 if (code == ASHIFTRT
9001 && (num_sign_bit_copies (varop, shift_mode)
9002 == GET_MODE_BITSIZE (shift_mode)))
9008 /* If we are doing an arithmetic right shift and discarding all but
9009 the sign bit copies, this is equivalent to doing a shift by the
9010 bitsize minus one. Convert it into that shift because it will often
9011 allow other simplifications. */
9013 if (code == ASHIFTRT
9014 && (count + num_sign_bit_copies (varop, shift_mode)
9015 >= GET_MODE_BITSIZE (shift_mode)))
9016 count = GET_MODE_BITSIZE (shift_mode) - 1;
9018 /* We simplify the tests below and elsewhere by converting
9019 ASHIFTRT to LSHIFTRT if we know the sign bit is clear.
9020 `make_compound_operation' will convert it to a ASHIFTRT for
9021 those machines (such as VAX) that don't have a LSHIFTRT. */
9022 if (GET_MODE_BITSIZE (shift_mode) <= HOST_BITS_PER_WIDE_INT
9024 && ((nonzero_bits (varop, shift_mode)
9025 & ((HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (shift_mode) - 1)))
9029 switch (GET_CODE (varop))
9035 new = expand_compound_operation (varop);
9044 /* If we have (xshiftrt (mem ...) C) and C is MODE_WIDTH
9045 minus the width of a smaller mode, we can do this with a
9046 SIGN_EXTEND or ZERO_EXTEND from the narrower memory location. */
9047 if ((code == ASHIFTRT || code == LSHIFTRT)
9048 && ! mode_dependent_address_p (XEXP (varop, 0))
9049 && ! MEM_VOLATILE_P (varop)
9050 && (tmode = mode_for_size (GET_MODE_BITSIZE (mode) - count,
9051 MODE_INT, 1)) != BLKmode)
9053 new = adjust_address_nv (varop, tmode,
9054 BYTES_BIG_ENDIAN ? 0
9055 : count / BITS_PER_UNIT);
9057 varop = gen_rtx_fmt_e (code == ASHIFTRT ? SIGN_EXTEND
9058 : ZERO_EXTEND, mode, new);
9065 /* Similar to the case above, except that we can only do this if
9066 the resulting mode is the same as that of the underlying
9067 MEM and adjust the address depending on the *bits* endianness
9068 because of the way that bit-field extract insns are defined. */
9069 if ((code == ASHIFTRT || code == LSHIFTRT)
9070 && (tmode = mode_for_size (GET_MODE_BITSIZE (mode) - count,
9071 MODE_INT, 1)) != BLKmode
9072 && tmode == GET_MODE (XEXP (varop, 0)))
9074 if (BITS_BIG_ENDIAN)
9075 new = XEXP (varop, 0);
9078 new = copy_rtx (XEXP (varop, 0));
9079 SUBST (XEXP (new, 0),
9080 plus_constant (XEXP (new, 0),
9081 count / BITS_PER_UNIT));
9084 varop = gen_rtx_fmt_e (code == ASHIFTRT ? SIGN_EXTEND
9085 : ZERO_EXTEND, mode, new);
9092 /* If VAROP is a SUBREG, strip it as long as the inner operand has
9093 the same number of words as what we've seen so far. Then store
9094 the widest mode in MODE. */
9095 if (subreg_lowpart_p (varop)
9096 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop)))
9097 > GET_MODE_SIZE (GET_MODE (varop)))
9098 && (((GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop)))
9099 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
9102 varop = SUBREG_REG (varop);
9103 if (GET_MODE_SIZE (GET_MODE (varop)) > GET_MODE_SIZE (mode))
9104 mode = GET_MODE (varop);
9110 /* Some machines use MULT instead of ASHIFT because MULT
9111 is cheaper. But it is still better on those machines to
9112 merge two shifts into one. */
9113 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
9114 && exact_log2 (INTVAL (XEXP (varop, 1))) >= 0)
9117 = gen_binary (ASHIFT, GET_MODE (varop), XEXP (varop, 0),
9118 GEN_INT (exact_log2 (INTVAL (XEXP (varop, 1)))));
9124 /* Similar, for when divides are cheaper. */
9125 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
9126 && exact_log2 (INTVAL (XEXP (varop, 1))) >= 0)
9129 = gen_binary (LSHIFTRT, GET_MODE (varop), XEXP (varop, 0),
9130 GEN_INT (exact_log2 (INTVAL (XEXP (varop, 1)))));
9136 /* If we are extracting just the sign bit of an arithmetic
9137 right shift, that shift is not needed. However, the sign
9138 bit of a wider mode may be different from what would be
9139 interpreted as the sign bit in a narrower mode, so, if
9140 the result is narrower, don't discard the shift. */
9141 if (code == LSHIFTRT && count == GET_MODE_BITSIZE (result_mode) - 1
9142 && (GET_MODE_BITSIZE (result_mode)
9143 >= GET_MODE_BITSIZE (GET_MODE (varop))))
9145 varop = XEXP (varop, 0);
9149 /* ... fall through ... */
9154 /* Here we have two nested shifts. The result is usually the
9155 AND of a new shift with a mask. We compute the result below. */
9156 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
9157 && INTVAL (XEXP (varop, 1)) >= 0
9158 && INTVAL (XEXP (varop, 1)) < GET_MODE_BITSIZE (GET_MODE (varop))
9159 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
9160 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
9162 enum rtx_code first_code = GET_CODE (varop);
9163 unsigned int first_count = INTVAL (XEXP (varop, 1));
9164 unsigned HOST_WIDE_INT mask;
9167 /* We have one common special case. We can't do any merging if
9168 the inner code is an ASHIFTRT of a smaller mode. However, if
9169 we have (ashift:M1 (subreg:M1 (ashiftrt:M2 FOO C1) 0) C2)
9170 with C2 == GET_MODE_BITSIZE (M1) - GET_MODE_BITSIZE (M2),
9171 we can convert it to
9172 (ashiftrt:M1 (ashift:M1 (and:M1 (subreg:M1 FOO 0 C2) C3) C1).
9173 This simplifies certain SIGN_EXTEND operations. */
9174 if (code == ASHIFT && first_code == ASHIFTRT
9175 && (GET_MODE_BITSIZE (result_mode)
9176 - GET_MODE_BITSIZE (GET_MODE (varop))) == count)
9178 /* C3 has the low-order C1 bits zero. */
9180 mask = (GET_MODE_MASK (mode)
9181 & ~(((HOST_WIDE_INT) 1 << first_count) - 1));
9183 varop = simplify_and_const_int (NULL_RTX, result_mode,
9184 XEXP (varop, 0), mask);
9185 varop = simplify_shift_const (NULL_RTX, ASHIFT, result_mode,
9187 count = first_count;
9192 /* If this was (ashiftrt (ashift foo C1) C2) and FOO has more
9193 than C1 high-order bits equal to the sign bit, we can convert
9194 this to either an ASHIFT or a ASHIFTRT depending on the
9197 We cannot do this if VAROP's mode is not SHIFT_MODE. */
9199 if (code == ASHIFTRT && first_code == ASHIFT
9200 && GET_MODE (varop) == shift_mode
9201 && (num_sign_bit_copies (XEXP (varop, 0), shift_mode)
9204 varop = XEXP (varop, 0);
9206 signed_count = count - first_count;
9207 if (signed_count < 0)
9208 count = -signed_count, code = ASHIFT;
9210 count = signed_count;
9215 /* There are some cases we can't do. If CODE is ASHIFTRT,
9216 we can only do this if FIRST_CODE is also ASHIFTRT.
9218 We can't do the case when CODE is ROTATE and FIRST_CODE is
9221 If the mode of this shift is not the mode of the outer shift,
9222 we can't do this if either shift is a right shift or ROTATE.
9224 Finally, we can't do any of these if the mode is too wide
9225 unless the codes are the same.
9227 Handle the case where the shift codes are the same
9230 if (code == first_code)
9232 if (GET_MODE (varop) != result_mode
9233 && (code == ASHIFTRT || code == LSHIFTRT
9237 count += first_count;
9238 varop = XEXP (varop, 0);
9242 if (code == ASHIFTRT
9243 || (code == ROTATE && first_code == ASHIFTRT)
9244 || GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT
9245 || (GET_MODE (varop) != result_mode
9246 && (first_code == ASHIFTRT || first_code == LSHIFTRT
9247 || first_code == ROTATE
9248 || code == ROTATE)))
9251 /* To compute the mask to apply after the shift, shift the
9252 nonzero bits of the inner shift the same way the
9253 outer shift will. */
9255 mask_rtx = GEN_INT (nonzero_bits (varop, GET_MODE (varop)));
9258 = simplify_binary_operation (code, result_mode, mask_rtx,
9261 /* Give up if we can't compute an outer operation to use. */
9263 || GET_CODE (mask_rtx) != CONST_INT
9264 || ! merge_outer_ops (&outer_op, &outer_const, AND,
9266 result_mode, &complement_p))
9269 /* If the shifts are in the same direction, we add the
9270 counts. Otherwise, we subtract them. */
9271 signed_count = count;
9272 if ((code == ASHIFTRT || code == LSHIFTRT)
9273 == (first_code == ASHIFTRT || first_code == LSHIFTRT))
9274 signed_count += first_count;
9276 signed_count -= first_count;
9278 /* If COUNT is positive, the new shift is usually CODE,
9279 except for the two exceptions below, in which case it is
9280 FIRST_CODE. If the count is negative, FIRST_CODE should
9282 if (signed_count > 0
9283 && ((first_code == ROTATE && code == ASHIFT)
9284 || (first_code == ASHIFTRT && code == LSHIFTRT)))
9285 code = first_code, count = signed_count;
9286 else if (signed_count < 0)
9287 code = first_code, count = -signed_count;
9289 count = signed_count;
9291 varop = XEXP (varop, 0);
9295 /* If we have (A << B << C) for any shift, we can convert this to
9296 (A << C << B). This wins if A is a constant. Only try this if
9297 B is not a constant. */
9299 else if (GET_CODE (varop) == code
9300 && GET_CODE (XEXP (varop, 1)) != CONST_INT
9302 = simplify_binary_operation (code, mode,
9306 varop = gen_rtx_fmt_ee (code, mode, new, XEXP (varop, 1));
9313 /* Make this fit the case below. */
9314 varop = gen_rtx_XOR (mode, XEXP (varop, 0),
9315 GEN_INT (GET_MODE_MASK (mode)));
9321 /* If we have (xshiftrt (ior (plus X (const_int -1)) X) C)
9322 with C the size of VAROP - 1 and the shift is logical if
9323 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
9324 we have an (le X 0) operation. If we have an arithmetic shift
9325 and STORE_FLAG_VALUE is 1 or we have a logical shift with
9326 STORE_FLAG_VALUE of -1, we have a (neg (le X 0)) operation. */
9328 if (GET_CODE (varop) == IOR && GET_CODE (XEXP (varop, 0)) == PLUS
9329 && XEXP (XEXP (varop, 0), 1) == constm1_rtx
9330 && (STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
9331 && (code == LSHIFTRT || code == ASHIFTRT)
9332 && count == GET_MODE_BITSIZE (GET_MODE (varop)) - 1
9333 && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
9336 varop = gen_rtx_LE (GET_MODE (varop), XEXP (varop, 1),
9339 if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
9340 varop = gen_rtx_NEG (GET_MODE (varop), varop);
9345 /* If we have (shift (logical)), move the logical to the outside
9346 to allow it to possibly combine with another logical and the
9347 shift to combine with another shift. This also canonicalizes to
9348 what a ZERO_EXTRACT looks like. Also, some machines have
9349 (and (shift)) insns. */
9351 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
9352 && (new = simplify_binary_operation (code, result_mode,
9354 GEN_INT (count))) != 0
9355 && GET_CODE (new) == CONST_INT
9356 && merge_outer_ops (&outer_op, &outer_const, GET_CODE (varop),
9357 INTVAL (new), result_mode, &complement_p))
9359 varop = XEXP (varop, 0);
9363 /* If we can't do that, try to simplify the shift in each arm of the
9364 logical expression, make a new logical expression, and apply
9365 the inverse distributive law. */
9367 rtx lhs = simplify_shift_const (NULL_RTX, code, shift_mode,
9368 XEXP (varop, 0), count);
9369 rtx rhs = simplify_shift_const (NULL_RTX, code, shift_mode,
9370 XEXP (varop, 1), count);
9372 varop = gen_binary (GET_CODE (varop), shift_mode, lhs, rhs);
9373 varop = apply_distributive_law (varop);
9380 /* convert (lshiftrt (eq FOO 0) C) to (xor FOO 1) if STORE_FLAG_VALUE
9381 says that the sign bit can be tested, FOO has mode MODE, C is
9382 GET_MODE_BITSIZE (MODE) - 1, and FOO has only its low-order bit
9383 that may be nonzero. */
9384 if (code == LSHIFTRT
9385 && XEXP (varop, 1) == const0_rtx
9386 && GET_MODE (XEXP (varop, 0)) == result_mode
9387 && count == GET_MODE_BITSIZE (result_mode) - 1
9388 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
9389 && ((STORE_FLAG_VALUE
9390 & ((HOST_WIDE_INT) 1
9391 < (GET_MODE_BITSIZE (result_mode) - 1))))
9392 && nonzero_bits (XEXP (varop, 0), result_mode) == 1
9393 && merge_outer_ops (&outer_op, &outer_const, XOR,
9394 (HOST_WIDE_INT) 1, result_mode,
9397 varop = XEXP (varop, 0);
9404 /* (lshiftrt (neg A) C) where A is either 0 or 1 and C is one less
9405 than the number of bits in the mode is equivalent to A. */
9406 if (code == LSHIFTRT && count == GET_MODE_BITSIZE (result_mode) - 1
9407 && nonzero_bits (XEXP (varop, 0), result_mode) == 1)
9409 varop = XEXP (varop, 0);
9414 /* NEG commutes with ASHIFT since it is multiplication. Move the
9415 NEG outside to allow shifts to combine. */
9417 && merge_outer_ops (&outer_op, &outer_const, NEG,
9418 (HOST_WIDE_INT) 0, result_mode,
9421 varop = XEXP (varop, 0);
9427 /* (lshiftrt (plus A -1) C) where A is either 0 or 1 and C
9428 is one less than the number of bits in the mode is
9429 equivalent to (xor A 1). */
9430 if (code == LSHIFTRT && count == GET_MODE_BITSIZE (result_mode) - 1
9431 && XEXP (varop, 1) == constm1_rtx
9432 && nonzero_bits (XEXP (varop, 0), result_mode) == 1
9433 && merge_outer_ops (&outer_op, &outer_const, XOR,
9434 (HOST_WIDE_INT) 1, result_mode,
9438 varop = XEXP (varop, 0);
9442 /* If we have (xshiftrt (plus FOO BAR) C), and the only bits
9443 that might be nonzero in BAR are those being shifted out and those
9444 bits are known zero in FOO, we can replace the PLUS with FOO.
9445 Similarly in the other operand order. This code occurs when
9446 we are computing the size of a variable-size array. */
9448 if ((code == ASHIFTRT || code == LSHIFTRT)
9449 && count < HOST_BITS_PER_WIDE_INT
9450 && nonzero_bits (XEXP (varop, 1), result_mode) >> count == 0
9451 && (nonzero_bits (XEXP (varop, 1), result_mode)
9452 & nonzero_bits (XEXP (varop, 0), result_mode)) == 0)
9454 varop = XEXP (varop, 0);
9457 else if ((code == ASHIFTRT || code == LSHIFTRT)
9458 && count < HOST_BITS_PER_WIDE_INT
9459 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
9460 && 0 == (nonzero_bits (XEXP (varop, 0), result_mode)
9462 && 0 == (nonzero_bits (XEXP (varop, 0), result_mode)
9463 & nonzero_bits (XEXP (varop, 1),
9466 varop = XEXP (varop, 1);
9470 /* (ashift (plus foo C) N) is (plus (ashift foo N) C'). */
9472 && GET_CODE (XEXP (varop, 1)) == CONST_INT
9473 && (new = simplify_binary_operation (ASHIFT, result_mode,
9475 GEN_INT (count))) != 0
9476 && GET_CODE (new) == CONST_INT
9477 && merge_outer_ops (&outer_op, &outer_const, PLUS,
9478 INTVAL (new), result_mode, &complement_p))
9480 varop = XEXP (varop, 0);
9486 /* If we have (xshiftrt (minus (ashiftrt X C)) X) C)
9487 with C the size of VAROP - 1 and the shift is logical if
9488 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
9489 we have a (gt X 0) operation. If the shift is arithmetic with
9490 STORE_FLAG_VALUE of 1 or logical with STORE_FLAG_VALUE == -1,
9491 we have a (neg (gt X 0)) operation. */
9493 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
9494 && GET_CODE (XEXP (varop, 0)) == ASHIFTRT
9495 && count == GET_MODE_BITSIZE (GET_MODE (varop)) - 1
9496 && (code == LSHIFTRT || code == ASHIFTRT)
9497 && GET_CODE (XEXP (XEXP (varop, 0), 1)) == CONST_INT
9498 && INTVAL (XEXP (XEXP (varop, 0), 1)) == count
9499 && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
9502 varop = gen_rtx_GT (GET_MODE (varop), XEXP (varop, 1),
9505 if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
9506 varop = gen_rtx_NEG (GET_MODE (varop), varop);
9513 /* Change (lshiftrt (truncate (lshiftrt))) to (truncate (lshiftrt))
9514 if the truncate does not affect the value. */
9515 if (code == LSHIFTRT
9516 && GET_CODE (XEXP (varop, 0)) == LSHIFTRT
9517 && GET_CODE (XEXP (XEXP (varop, 0), 1)) == CONST_INT
9518 && (INTVAL (XEXP (XEXP (varop, 0), 1))
9519 >= (GET_MODE_BITSIZE (GET_MODE (XEXP (varop, 0)))
9520 - GET_MODE_BITSIZE (GET_MODE (varop)))))
9522 rtx varop_inner = XEXP (varop, 0);
9525 = gen_rtx_LSHIFTRT (GET_MODE (varop_inner),
9526 XEXP (varop_inner, 0),
9528 (count + INTVAL (XEXP (varop_inner, 1))));
9529 varop = gen_rtx_TRUNCATE (GET_MODE (varop), varop_inner);
9542 /* We need to determine what mode to do the shift in. If the shift is
9543 a right shift or ROTATE, we must always do it in the mode it was
9544 originally done in. Otherwise, we can do it in MODE, the widest mode
9545 encountered. The code we care about is that of the shift that will
9546 actually be done, not the shift that was originally requested. */
9548 = (code == ASHIFTRT || code == LSHIFTRT || code == ROTATE
9549 ? result_mode : mode);
9551 /* We have now finished analyzing the shift. The result should be
9552 a shift of type CODE with SHIFT_MODE shifting VAROP COUNT places. If
9553 OUTER_OP is non-NIL, it is an operation that needs to be applied
9554 to the result of the shift. OUTER_CONST is the relevant constant,
9555 but we must turn off all bits turned off in the shift.
9557 If we were passed a value for X, see if we can use any pieces of
9558 it. If not, make new rtx. */
9560 if (x && GET_RTX_CLASS (GET_CODE (x)) == '2'
9561 && GET_CODE (XEXP (x, 1)) == CONST_INT
9562 && INTVAL (XEXP (x, 1)) == count)
9563 const_rtx = XEXP (x, 1);
9565 const_rtx = GEN_INT (count);
9567 if (x && GET_CODE (XEXP (x, 0)) == SUBREG
9568 && GET_MODE (XEXP (x, 0)) == shift_mode
9569 && SUBREG_REG (XEXP (x, 0)) == varop)
9570 varop = XEXP (x, 0);
9571 else if (GET_MODE (varop) != shift_mode)
9572 varop = gen_lowpart_for_combine (shift_mode, varop);
9574 /* If we can't make the SUBREG, try to return what we were given. */
9575 if (GET_CODE (varop) == CLOBBER)
9576 return x ? x : varop;
9578 new = simplify_binary_operation (code, shift_mode, varop, const_rtx);
9582 x = gen_rtx_fmt_ee (code, shift_mode, varop, const_rtx);
9584 /* If we have an outer operation and we just made a shift, it is
9585 possible that we could have simplified the shift were it not
9586 for the outer operation. So try to do the simplification
9589 if (outer_op != NIL && GET_CODE (x) == code
9590 && GET_CODE (XEXP (x, 1)) == CONST_INT)
9591 x = simplify_shift_const (x, code, shift_mode, XEXP (x, 0),
9592 INTVAL (XEXP (x, 1)));
9594 /* If we were doing a LSHIFTRT in a wider mode than it was originally,
9595 turn off all the bits that the shift would have turned off. */
9596 if (orig_code == LSHIFTRT && result_mode != shift_mode)
9597 x = simplify_and_const_int (NULL_RTX, shift_mode, x,
9598 GET_MODE_MASK (result_mode) >> orig_count);
9600 /* Do the remainder of the processing in RESULT_MODE. */
9601 x = gen_lowpart_for_combine (result_mode, x);
9603 /* If COMPLEMENT_P is set, we have to complement X before doing the outer
9606 x =simplify_gen_unary (NOT, result_mode, x, result_mode);
9608 if (outer_op != NIL)
9610 if (GET_MODE_BITSIZE (result_mode) < HOST_BITS_PER_WIDE_INT)
9611 outer_const = trunc_int_for_mode (outer_const, result_mode);
9613 if (outer_op == AND)
9614 x = simplify_and_const_int (NULL_RTX, result_mode, x, outer_const);
9615 else if (outer_op == SET)
9616 /* This means that we have determined that the result is
9617 equivalent to a constant. This should be rare. */
9618 x = GEN_INT (outer_const);
9619 else if (GET_RTX_CLASS (outer_op) == '1')
9620 x = simplify_gen_unary (outer_op, result_mode, x, result_mode);
9622 x = gen_binary (outer_op, result_mode, x, GEN_INT (outer_const));
9628 /* Like recog, but we receive the address of a pointer to a new pattern.
9629 We try to match the rtx that the pointer points to.
9630 If that fails, we may try to modify or replace the pattern,
9631 storing the replacement into the same pointer object.
9633 Modifications include deletion or addition of CLOBBERs.
9635 PNOTES is a pointer to a location where any REG_UNUSED notes added for
9636 the CLOBBERs are placed.
9638 The value is the final insn code from the pattern ultimately matched,
9642 recog_for_combine (pnewpat, insn, pnotes)
9648 int insn_code_number;
9649 int num_clobbers_to_add = 0;
9654 /* If PAT is a PARALLEL, check to see if it contains the CLOBBER
9655 we use to indicate that something didn't match. If we find such a
9656 thing, force rejection. */
9657 if (GET_CODE (pat) == PARALLEL)
9658 for (i = XVECLEN (pat, 0) - 1; i >= 0; i--)
9659 if (GET_CODE (XVECEXP (pat, 0, i)) == CLOBBER
9660 && XEXP (XVECEXP (pat, 0, i), 0) == const0_rtx)
9663 /* *pnewpat does not have to be actual PATTERN (insn), so make a dummy
9664 instruction for pattern recognition. */
9665 dummy_insn = shallow_copy_rtx (insn);
9666 PATTERN (dummy_insn) = pat;
9667 REG_NOTES (dummy_insn) = 0;
9669 insn_code_number = recog (pat, dummy_insn, &num_clobbers_to_add);
9671 /* If it isn't, there is the possibility that we previously had an insn
9672 that clobbered some register as a side effect, but the combined
9673 insn doesn't need to do that. So try once more without the clobbers
9674 unless this represents an ASM insn. */
9676 if (insn_code_number < 0 && ! check_asm_operands (pat)
9677 && GET_CODE (pat) == PARALLEL)
9681 for (pos = 0, i = 0; i < XVECLEN (pat, 0); i++)
9682 if (GET_CODE (XVECEXP (pat, 0, i)) != CLOBBER)
9685 SUBST (XVECEXP (pat, 0, pos), XVECEXP (pat, 0, i));
9689 SUBST_INT (XVECLEN (pat, 0), pos);
9692 pat = XVECEXP (pat, 0, 0);
9694 PATTERN (dummy_insn) = pat;
9695 insn_code_number = recog (pat, dummy_insn, &num_clobbers_to_add);
9698 /* Recognize all noop sets, these will be killed by followup pass. */
9699 if (insn_code_number < 0 && GET_CODE (pat) == SET && set_noop_p (pat))
9700 insn_code_number = NOOP_MOVE_INSN_CODE, num_clobbers_to_add = 0;
9702 /* If we had any clobbers to add, make a new pattern than contains
9703 them. Then check to make sure that all of them are dead. */
9704 if (num_clobbers_to_add)
9706 rtx newpat = gen_rtx_PARALLEL (VOIDmode,
9707 rtvec_alloc (GET_CODE (pat) == PARALLEL
9709 + num_clobbers_to_add)
9710 : num_clobbers_to_add + 1));
9712 if (GET_CODE (pat) == PARALLEL)
9713 for (i = 0; i < XVECLEN (pat, 0); i++)
9714 XVECEXP (newpat, 0, i) = XVECEXP (pat, 0, i);
9716 XVECEXP (newpat, 0, 0) = pat;
9718 add_clobbers (newpat, insn_code_number);
9720 for (i = XVECLEN (newpat, 0) - num_clobbers_to_add;
9721 i < XVECLEN (newpat, 0); i++)
9723 if (GET_CODE (XEXP (XVECEXP (newpat, 0, i), 0)) == REG
9724 && ! reg_dead_at_p (XEXP (XVECEXP (newpat, 0, i), 0), insn))
9726 notes = gen_rtx_EXPR_LIST (REG_UNUSED,
9727 XEXP (XVECEXP (newpat, 0, i), 0), notes);
9735 return insn_code_number;
9738 /* Like gen_lowpart but for use by combine. In combine it is not possible
9739 to create any new pseudoregs. However, it is safe to create
9740 invalid memory addresses, because combine will try to recognize
9741 them and all they will do is make the combine attempt fail.
9743 If for some reason this cannot do its job, an rtx
9744 (clobber (const_int 0)) is returned.
9745 An insn containing that will not be recognized. */
9750 gen_lowpart_for_combine (mode, x)
9751 enum machine_mode mode;
9756 if (GET_MODE (x) == mode)
9759 /* We can only support MODE being wider than a word if X is a
9760 constant integer or has a mode the same size. */
9762 if (GET_MODE_SIZE (mode) > UNITS_PER_WORD
9763 && ! ((GET_MODE (x) == VOIDmode
9764 && (GET_CODE (x) == CONST_INT
9765 || GET_CODE (x) == CONST_DOUBLE))
9766 || GET_MODE_SIZE (GET_MODE (x)) == GET_MODE_SIZE (mode)))
9767 return gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
9769 /* X might be a paradoxical (subreg (mem)). In that case, gen_lowpart
9770 won't know what to do. So we will strip off the SUBREG here and
9771 process normally. */
9772 if (GET_CODE (x) == SUBREG && GET_CODE (SUBREG_REG (x)) == MEM)
9775 if (GET_MODE (x) == mode)
9779 result = gen_lowpart_common (mode, x);
9780 #ifdef CLASS_CANNOT_CHANGE_MODE
9782 && GET_CODE (result) == SUBREG
9783 && GET_CODE (SUBREG_REG (result)) == REG
9784 && REGNO (SUBREG_REG (result)) >= FIRST_PSEUDO_REGISTER
9785 && CLASS_CANNOT_CHANGE_MODE_P (GET_MODE (result),
9786 GET_MODE (SUBREG_REG (result))))
9787 REG_CHANGES_MODE (REGNO (SUBREG_REG (result))) = 1;
9793 if (GET_CODE (x) == MEM)
9797 /* Refuse to work on a volatile memory ref or one with a mode-dependent
9799 if (MEM_VOLATILE_P (x) || mode_dependent_address_p (XEXP (x, 0)))
9800 return gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
9802 /* If we want to refer to something bigger than the original memref,
9803 generate a perverse subreg instead. That will force a reload
9804 of the original memref X. */
9805 if (GET_MODE_SIZE (GET_MODE (x)) < GET_MODE_SIZE (mode))
9806 return gen_rtx_SUBREG (mode, x, 0);
9808 if (WORDS_BIG_ENDIAN)
9809 offset = (MAX (GET_MODE_SIZE (GET_MODE (x)), UNITS_PER_WORD)
9810 - MAX (GET_MODE_SIZE (mode), UNITS_PER_WORD));
9812 if (BYTES_BIG_ENDIAN)
9814 /* Adjust the address so that the address-after-the-data is
9816 offset -= (MIN (UNITS_PER_WORD, GET_MODE_SIZE (mode))
9817 - MIN (UNITS_PER_WORD, GET_MODE_SIZE (GET_MODE (x))));
9820 return adjust_address_nv (x, mode, offset);
9823 /* If X is a comparison operator, rewrite it in a new mode. This
9824 probably won't match, but may allow further simplifications. */
9825 else if (GET_RTX_CLASS (GET_CODE (x)) == '<')
9826 return gen_rtx_fmt_ee (GET_CODE (x), mode, XEXP (x, 0), XEXP (x, 1));
9828 /* If we couldn't simplify X any other way, just enclose it in a
9829 SUBREG. Normally, this SUBREG won't match, but some patterns may
9830 include an explicit SUBREG or we may simplify it further in combine. */
9836 offset = subreg_lowpart_offset (mode, GET_MODE (x));
9837 res = simplify_gen_subreg (mode, x, GET_MODE (x), offset);
9840 return gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
9844 /* These routines make binary and unary operations by first seeing if they
9845 fold; if not, a new expression is allocated. */
9848 gen_binary (code, mode, op0, op1)
9850 enum machine_mode mode;
9856 if (GET_RTX_CLASS (code) == 'c'
9857 && swap_commutative_operands_p (op0, op1))
9858 tem = op0, op0 = op1, op1 = tem;
9860 if (GET_RTX_CLASS (code) == '<')
9862 enum machine_mode op_mode = GET_MODE (op0);
9864 /* Strip the COMPARE from (REL_OP (compare X Y) 0) to get
9865 just (REL_OP X Y). */
9866 if (GET_CODE (op0) == COMPARE && op1 == const0_rtx)
9868 op1 = XEXP (op0, 1);
9869 op0 = XEXP (op0, 0);
9870 op_mode = GET_MODE (op0);
9873 if (op_mode == VOIDmode)
9874 op_mode = GET_MODE (op1);
9875 result = simplify_relational_operation (code, op_mode, op0, op1);
9878 result = simplify_binary_operation (code, mode, op0, op1);
9883 /* Put complex operands first and constants second. */
9884 if (GET_RTX_CLASS (code) == 'c'
9885 && swap_commutative_operands_p (op0, op1))
9886 return gen_rtx_fmt_ee (code, mode, op1, op0);
9888 /* If we are turning off bits already known off in OP0, we need not do
9890 else if (code == AND && GET_CODE (op1) == CONST_INT
9891 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
9892 && (nonzero_bits (op0, mode) & ~INTVAL (op1)) == 0)
9895 return gen_rtx_fmt_ee (code, mode, op0, op1);
9898 /* Simplify a comparison between *POP0 and *POP1 where CODE is the
9899 comparison code that will be tested.
9901 The result is a possibly different comparison code to use. *POP0 and
9902 *POP1 may be updated.
9904 It is possible that we might detect that a comparison is either always
9905 true or always false. However, we do not perform general constant
9906 folding in combine, so this knowledge isn't useful. Such tautologies
9907 should have been detected earlier. Hence we ignore all such cases. */
9909 static enum rtx_code
9910 simplify_comparison (code, pop0, pop1)
9919 enum machine_mode mode, tmode;
9921 /* Try a few ways of applying the same transformation to both operands. */
9924 #ifndef WORD_REGISTER_OPERATIONS
9925 /* The test below this one won't handle SIGN_EXTENDs on these machines,
9926 so check specially. */
9927 if (code != GTU && code != GEU && code != LTU && code != LEU
9928 && GET_CODE (op0) == ASHIFTRT && GET_CODE (op1) == ASHIFTRT
9929 && GET_CODE (XEXP (op0, 0)) == ASHIFT
9930 && GET_CODE (XEXP (op1, 0)) == ASHIFT
9931 && GET_CODE (XEXP (XEXP (op0, 0), 0)) == SUBREG
9932 && GET_CODE (XEXP (XEXP (op1, 0), 0)) == SUBREG
9933 && (GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0)))
9934 == GET_MODE (SUBREG_REG (XEXP (XEXP (op1, 0), 0))))
9935 && GET_CODE (XEXP (op0, 1)) == CONST_INT
9936 && GET_CODE (XEXP (op1, 1)) == CONST_INT
9937 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
9938 && GET_CODE (XEXP (XEXP (op1, 0), 1)) == CONST_INT
9939 && INTVAL (XEXP (op0, 1)) == INTVAL (XEXP (op1, 1))
9940 && INTVAL (XEXP (op0, 1)) == INTVAL (XEXP (XEXP (op0, 0), 1))
9941 && INTVAL (XEXP (op0, 1)) == INTVAL (XEXP (XEXP (op1, 0), 1))
9942 && (INTVAL (XEXP (op0, 1))
9943 == (GET_MODE_BITSIZE (GET_MODE (op0))
9945 (GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0))))))))
9947 op0 = SUBREG_REG (XEXP (XEXP (op0, 0), 0));
9948 op1 = SUBREG_REG (XEXP (XEXP (op1, 0), 0));
9952 /* If both operands are the same constant shift, see if we can ignore the
9953 shift. We can if the shift is a rotate or if the bits shifted out of
9954 this shift are known to be zero for both inputs and if the type of
9955 comparison is compatible with the shift. */
9956 if (GET_CODE (op0) == GET_CODE (op1)
9957 && GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
9958 && ((GET_CODE (op0) == ROTATE && (code == NE || code == EQ))
9959 || ((GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFT)
9960 && (code != GT && code != LT && code != GE && code != LE))
9961 || (GET_CODE (op0) == ASHIFTRT
9962 && (code != GTU && code != LTU
9963 && code != GEU && code != LEU)))
9964 && GET_CODE (XEXP (op0, 1)) == CONST_INT
9965 && INTVAL (XEXP (op0, 1)) >= 0
9966 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT
9967 && XEXP (op0, 1) == XEXP (op1, 1))
9969 enum machine_mode mode = GET_MODE (op0);
9970 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
9971 int shift_count = INTVAL (XEXP (op0, 1));
9973 if (GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFTRT)
9974 mask &= (mask >> shift_count) << shift_count;
9975 else if (GET_CODE (op0) == ASHIFT)
9976 mask = (mask & (mask << shift_count)) >> shift_count;
9978 if ((nonzero_bits (XEXP (op0, 0), mode) & ~mask) == 0
9979 && (nonzero_bits (XEXP (op1, 0), mode) & ~mask) == 0)
9980 op0 = XEXP (op0, 0), op1 = XEXP (op1, 0);
9985 /* If both operands are AND's of a paradoxical SUBREG by constant, the
9986 SUBREGs are of the same mode, and, in both cases, the AND would
9987 be redundant if the comparison was done in the narrower mode,
9988 do the comparison in the narrower mode (e.g., we are AND'ing with 1
9989 and the operand's possibly nonzero bits are 0xffffff01; in that case
9990 if we only care about QImode, we don't need the AND). This case
9991 occurs if the output mode of an scc insn is not SImode and
9992 STORE_FLAG_VALUE == 1 (e.g., the 386).
9994 Similarly, check for a case where the AND's are ZERO_EXTEND
9995 operations from some narrower mode even though a SUBREG is not
9998 else if (GET_CODE (op0) == AND && GET_CODE (op1) == AND
9999 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10000 && GET_CODE (XEXP (op1, 1)) == CONST_INT)
10002 rtx inner_op0 = XEXP (op0, 0);
10003 rtx inner_op1 = XEXP (op1, 0);
10004 HOST_WIDE_INT c0 = INTVAL (XEXP (op0, 1));
10005 HOST_WIDE_INT c1 = INTVAL (XEXP (op1, 1));
10008 if (GET_CODE (inner_op0) == SUBREG && GET_CODE (inner_op1) == SUBREG
10009 && (GET_MODE_SIZE (GET_MODE (inner_op0))
10010 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (inner_op0))))
10011 && (GET_MODE (SUBREG_REG (inner_op0))
10012 == GET_MODE (SUBREG_REG (inner_op1)))
10013 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (inner_op0)))
10014 <= HOST_BITS_PER_WIDE_INT)
10015 && (0 == ((~c0) & nonzero_bits (SUBREG_REG (inner_op0),
10016 GET_MODE (SUBREG_REG (inner_op0)))))
10017 && (0 == ((~c1) & nonzero_bits (SUBREG_REG (inner_op1),
10018 GET_MODE (SUBREG_REG (inner_op1))))))
10020 op0 = SUBREG_REG (inner_op0);
10021 op1 = SUBREG_REG (inner_op1);
10023 /* The resulting comparison is always unsigned since we masked
10024 off the original sign bit. */
10025 code = unsigned_condition (code);
10031 for (tmode = GET_CLASS_NARROWEST_MODE
10032 (GET_MODE_CLASS (GET_MODE (op0)));
10033 tmode != GET_MODE (op0); tmode = GET_MODE_WIDER_MODE (tmode))
10034 if ((unsigned HOST_WIDE_INT) c0 == GET_MODE_MASK (tmode))
10036 op0 = gen_lowpart_for_combine (tmode, inner_op0);
10037 op1 = gen_lowpart_for_combine (tmode, inner_op1);
10038 code = unsigned_condition (code);
10047 /* If both operands are NOT, we can strip off the outer operation
10048 and adjust the comparison code for swapped operands; similarly for
10049 NEG, except that this must be an equality comparison. */
10050 else if ((GET_CODE (op0) == NOT && GET_CODE (op1) == NOT)
10051 || (GET_CODE (op0) == NEG && GET_CODE (op1) == NEG
10052 && (code == EQ || code == NE)))
10053 op0 = XEXP (op0, 0), op1 = XEXP (op1, 0), code = swap_condition (code);
10059 /* If the first operand is a constant, swap the operands and adjust the
10060 comparison code appropriately, but don't do this if the second operand
10061 is already a constant integer. */
10062 if (swap_commutative_operands_p (op0, op1))
10064 tem = op0, op0 = op1, op1 = tem;
10065 code = swap_condition (code);
10068 /* We now enter a loop during which we will try to simplify the comparison.
10069 For the most part, we only are concerned with comparisons with zero,
10070 but some things may really be comparisons with zero but not start
10071 out looking that way. */
10073 while (GET_CODE (op1) == CONST_INT)
10075 enum machine_mode mode = GET_MODE (op0);
10076 unsigned int mode_width = GET_MODE_BITSIZE (mode);
10077 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
10078 int equality_comparison_p;
10079 int sign_bit_comparison_p;
10080 int unsigned_comparison_p;
10081 HOST_WIDE_INT const_op;
10083 /* We only want to handle integral modes. This catches VOIDmode,
10084 CCmode, and the floating-point modes. An exception is that we
10085 can handle VOIDmode if OP0 is a COMPARE or a comparison
10088 if (GET_MODE_CLASS (mode) != MODE_INT
10089 && ! (mode == VOIDmode
10090 && (GET_CODE (op0) == COMPARE
10091 || GET_RTX_CLASS (GET_CODE (op0)) == '<')))
10094 /* Get the constant we are comparing against and turn off all bits
10095 not on in our mode. */
10096 const_op = trunc_int_for_mode (INTVAL (op1), mode);
10097 op1 = GEN_INT (const_op);
10099 /* If we are comparing against a constant power of two and the value
10100 being compared can only have that single bit nonzero (e.g., it was
10101 `and'ed with that bit), we can replace this with a comparison
10104 && (code == EQ || code == NE || code == GE || code == GEU
10105 || code == LT || code == LTU)
10106 && mode_width <= HOST_BITS_PER_WIDE_INT
10107 && exact_log2 (const_op) >= 0
10108 && nonzero_bits (op0, mode) == (unsigned HOST_WIDE_INT) const_op)
10110 code = (code == EQ || code == GE || code == GEU ? NE : EQ);
10111 op1 = const0_rtx, const_op = 0;
10114 /* Similarly, if we are comparing a value known to be either -1 or
10115 0 with -1, change it to the opposite comparison against zero. */
10118 && (code == EQ || code == NE || code == GT || code == LE
10119 || code == GEU || code == LTU)
10120 && num_sign_bit_copies (op0, mode) == mode_width)
10122 code = (code == EQ || code == LE || code == GEU ? NE : EQ);
10123 op1 = const0_rtx, const_op = 0;
10126 /* Do some canonicalizations based on the comparison code. We prefer
10127 comparisons against zero and then prefer equality comparisons.
10128 If we can reduce the size of a constant, we will do that too. */
10133 /* < C is equivalent to <= (C - 1) */
10137 op1 = GEN_INT (const_op);
10139 /* ... fall through to LE case below. */
10145 /* <= C is equivalent to < (C + 1); we do this for C < 0 */
10149 op1 = GEN_INT (const_op);
10153 /* If we are doing a <= 0 comparison on a value known to have
10154 a zero sign bit, we can replace this with == 0. */
10155 else if (const_op == 0
10156 && mode_width <= HOST_BITS_PER_WIDE_INT
10157 && (nonzero_bits (op0, mode)
10158 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)
10163 /* >= C is equivalent to > (C - 1). */
10167 op1 = GEN_INT (const_op);
10169 /* ... fall through to GT below. */
10175 /* > C is equivalent to >= (C + 1); we do this for C < 0. */
10179 op1 = GEN_INT (const_op);
10183 /* If we are doing a > 0 comparison on a value known to have
10184 a zero sign bit, we can replace this with != 0. */
10185 else if (const_op == 0
10186 && mode_width <= HOST_BITS_PER_WIDE_INT
10187 && (nonzero_bits (op0, mode)
10188 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)
10193 /* < C is equivalent to <= (C - 1). */
10197 op1 = GEN_INT (const_op);
10199 /* ... fall through ... */
10202 /* (unsigned) < 0x80000000 is equivalent to >= 0. */
10203 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
10204 && (const_op == (HOST_WIDE_INT) 1 << (mode_width - 1)))
10206 const_op = 0, op1 = const0_rtx;
10214 /* unsigned <= 0 is equivalent to == 0 */
10218 /* (unsigned) <= 0x7fffffff is equivalent to >= 0. */
10219 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
10220 && (const_op == ((HOST_WIDE_INT) 1 << (mode_width - 1)) - 1))
10222 const_op = 0, op1 = const0_rtx;
10228 /* >= C is equivalent to < (C - 1). */
10232 op1 = GEN_INT (const_op);
10234 /* ... fall through ... */
10237 /* (unsigned) >= 0x80000000 is equivalent to < 0. */
10238 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
10239 && (const_op == (HOST_WIDE_INT) 1 << (mode_width - 1)))
10241 const_op = 0, op1 = const0_rtx;
10249 /* unsigned > 0 is equivalent to != 0 */
10253 /* (unsigned) > 0x7fffffff is equivalent to < 0. */
10254 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
10255 && (const_op == ((HOST_WIDE_INT) 1 << (mode_width - 1)) - 1))
10257 const_op = 0, op1 = const0_rtx;
10266 /* Compute some predicates to simplify code below. */
10268 equality_comparison_p = (code == EQ || code == NE);
10269 sign_bit_comparison_p = ((code == LT || code == GE) && const_op == 0);
10270 unsigned_comparison_p = (code == LTU || code == LEU || code == GTU
10273 /* If this is a sign bit comparison and we can do arithmetic in
10274 MODE, say that we will only be needing the sign bit of OP0. */
10275 if (sign_bit_comparison_p
10276 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
10277 op0 = force_to_mode (op0, mode,
10279 << (GET_MODE_BITSIZE (mode) - 1)),
10282 /* Now try cases based on the opcode of OP0. If none of the cases
10283 does a "continue", we exit this loop immediately after the
10286 switch (GET_CODE (op0))
10289 /* If we are extracting a single bit from a variable position in
10290 a constant that has only a single bit set and are comparing it
10291 with zero, we can convert this into an equality comparison
10292 between the position and the location of the single bit. */
10294 if (GET_CODE (XEXP (op0, 0)) == CONST_INT
10295 && XEXP (op0, 1) == const1_rtx
10296 && equality_comparison_p && const_op == 0
10297 && (i = exact_log2 (INTVAL (XEXP (op0, 0)))) >= 0)
10299 if (BITS_BIG_ENDIAN)
10301 enum machine_mode new_mode
10302 = mode_for_extraction (EP_extzv, 1);
10303 if (new_mode == MAX_MACHINE_MODE)
10304 i = BITS_PER_WORD - 1 - i;
10308 i = (GET_MODE_BITSIZE (mode) - 1 - i);
10312 op0 = XEXP (op0, 2);
10316 /* Result is nonzero iff shift count is equal to I. */
10317 code = reverse_condition (code);
10321 /* ... fall through ... */
10324 tem = expand_compound_operation (op0);
10333 /* If testing for equality, we can take the NOT of the constant. */
10334 if (equality_comparison_p
10335 && (tem = simplify_unary_operation (NOT, mode, op1, mode)) != 0)
10337 op0 = XEXP (op0, 0);
10342 /* If just looking at the sign bit, reverse the sense of the
10344 if (sign_bit_comparison_p)
10346 op0 = XEXP (op0, 0);
10347 code = (code == GE ? LT : GE);
10353 /* If testing for equality, we can take the NEG of the constant. */
10354 if (equality_comparison_p
10355 && (tem = simplify_unary_operation (NEG, mode, op1, mode)) != 0)
10357 op0 = XEXP (op0, 0);
10362 /* The remaining cases only apply to comparisons with zero. */
10366 /* When X is ABS or is known positive,
10367 (neg X) is < 0 if and only if X != 0. */
10369 if (sign_bit_comparison_p
10370 && (GET_CODE (XEXP (op0, 0)) == ABS
10371 || (mode_width <= HOST_BITS_PER_WIDE_INT
10372 && (nonzero_bits (XEXP (op0, 0), mode)
10373 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)))
10375 op0 = XEXP (op0, 0);
10376 code = (code == LT ? NE : EQ);
10380 /* If we have NEG of something whose two high-order bits are the
10381 same, we know that "(-a) < 0" is equivalent to "a > 0". */
10382 if (num_sign_bit_copies (op0, mode) >= 2)
10384 op0 = XEXP (op0, 0);
10385 code = swap_condition (code);
10391 /* If we are testing equality and our count is a constant, we
10392 can perform the inverse operation on our RHS. */
10393 if (equality_comparison_p && GET_CODE (XEXP (op0, 1)) == CONST_INT
10394 && (tem = simplify_binary_operation (ROTATERT, mode,
10395 op1, XEXP (op0, 1))) != 0)
10397 op0 = XEXP (op0, 0);
10402 /* If we are doing a < 0 or >= 0 comparison, it means we are testing
10403 a particular bit. Convert it to an AND of a constant of that
10404 bit. This will be converted into a ZERO_EXTRACT. */
10405 if (const_op == 0 && sign_bit_comparison_p
10406 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10407 && mode_width <= HOST_BITS_PER_WIDE_INT)
10409 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
10412 - INTVAL (XEXP (op0, 1)))));
10413 code = (code == LT ? NE : EQ);
10417 /* Fall through. */
10420 /* ABS is ignorable inside an equality comparison with zero. */
10421 if (const_op == 0 && equality_comparison_p)
10423 op0 = XEXP (op0, 0);
10429 /* Can simplify (compare (zero/sign_extend FOO) CONST)
10430 to (compare FOO CONST) if CONST fits in FOO's mode and we
10431 are either testing inequality or have an unsigned comparison
10432 with ZERO_EXTEND or a signed comparison with SIGN_EXTEND. */
10433 if (! unsigned_comparison_p
10434 && (GET_MODE_BITSIZE (GET_MODE (XEXP (op0, 0)))
10435 <= HOST_BITS_PER_WIDE_INT)
10436 && ((unsigned HOST_WIDE_INT) const_op
10437 < (((unsigned HOST_WIDE_INT) 1
10438 << (GET_MODE_BITSIZE (GET_MODE (XEXP (op0, 0))) - 1)))))
10440 op0 = XEXP (op0, 0);
10446 /* Check for the case where we are comparing A - C1 with C2,
10447 both constants are smaller than 1/2 the maximum positive
10448 value in MODE, and the comparison is equality or unsigned.
10449 In that case, if A is either zero-extended to MODE or has
10450 sufficient sign bits so that the high-order bit in MODE
10451 is a copy of the sign in the inner mode, we can prove that it is
10452 safe to do the operation in the wider mode. This simplifies
10453 many range checks. */
10455 if (mode_width <= HOST_BITS_PER_WIDE_INT
10456 && subreg_lowpart_p (op0)
10457 && GET_CODE (SUBREG_REG (op0)) == PLUS
10458 && GET_CODE (XEXP (SUBREG_REG (op0), 1)) == CONST_INT
10459 && INTVAL (XEXP (SUBREG_REG (op0), 1)) < 0
10460 && (-INTVAL (XEXP (SUBREG_REG (op0), 1))
10461 < (HOST_WIDE_INT) (GET_MODE_MASK (mode) / 2))
10462 && (unsigned HOST_WIDE_INT) const_op < GET_MODE_MASK (mode) / 2
10463 && (0 == (nonzero_bits (XEXP (SUBREG_REG (op0), 0),
10464 GET_MODE (SUBREG_REG (op0)))
10465 & ~GET_MODE_MASK (mode))
10466 || (num_sign_bit_copies (XEXP (SUBREG_REG (op0), 0),
10467 GET_MODE (SUBREG_REG (op0)))
10468 > (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0)))
10469 - GET_MODE_BITSIZE (mode)))))
10471 op0 = SUBREG_REG (op0);
10475 /* If the inner mode is narrower and we are extracting the low part,
10476 we can treat the SUBREG as if it were a ZERO_EXTEND. */
10477 if (subreg_lowpart_p (op0)
10478 && GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0))) < mode_width)
10479 /* Fall through */ ;
10483 /* ... fall through ... */
10486 if ((unsigned_comparison_p || equality_comparison_p)
10487 && (GET_MODE_BITSIZE (GET_MODE (XEXP (op0, 0)))
10488 <= HOST_BITS_PER_WIDE_INT)
10489 && ((unsigned HOST_WIDE_INT) const_op
10490 < GET_MODE_MASK (GET_MODE (XEXP (op0, 0)))))
10492 op0 = XEXP (op0, 0);
10498 /* (eq (plus X A) B) -> (eq X (minus B A)). We can only do
10499 this for equality comparisons due to pathological cases involving
10501 if (equality_comparison_p
10502 && 0 != (tem = simplify_binary_operation (MINUS, mode,
10503 op1, XEXP (op0, 1))))
10505 op0 = XEXP (op0, 0);
10510 /* (plus (abs X) (const_int -1)) is < 0 if and only if X == 0. */
10511 if (const_op == 0 && XEXP (op0, 1) == constm1_rtx
10512 && GET_CODE (XEXP (op0, 0)) == ABS && sign_bit_comparison_p)
10514 op0 = XEXP (XEXP (op0, 0), 0);
10515 code = (code == LT ? EQ : NE);
10521 /* We used to optimize signed comparisons against zero, but that
10522 was incorrect. Unsigned comparisons against zero (GTU, LEU)
10523 arrive here as equality comparisons, or (GEU, LTU) are
10524 optimized away. No need to special-case them. */
10526 /* (eq (minus A B) C) -> (eq A (plus B C)) or
10527 (eq B (minus A C)), whichever simplifies. We can only do
10528 this for equality comparisons due to pathological cases involving
10530 if (equality_comparison_p
10531 && 0 != (tem = simplify_binary_operation (PLUS, mode,
10532 XEXP (op0, 1), op1)))
10534 op0 = XEXP (op0, 0);
10539 if (equality_comparison_p
10540 && 0 != (tem = simplify_binary_operation (MINUS, mode,
10541 XEXP (op0, 0), op1)))
10543 op0 = XEXP (op0, 1);
10548 /* The sign bit of (minus (ashiftrt X C) X), where C is the number
10549 of bits in X minus 1, is one iff X > 0. */
10550 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == ASHIFTRT
10551 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
10552 && INTVAL (XEXP (XEXP (op0, 0), 1)) == mode_width - 1
10553 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
10555 op0 = XEXP (op0, 1);
10556 code = (code == GE ? LE : GT);
10562 /* (eq (xor A B) C) -> (eq A (xor B C)). This is a simplification
10563 if C is zero or B is a constant. */
10564 if (equality_comparison_p
10565 && 0 != (tem = simplify_binary_operation (XOR, mode,
10566 XEXP (op0, 1), op1)))
10568 op0 = XEXP (op0, 0);
10575 case UNEQ: case LTGT:
10576 case LT: case LTU: case UNLT: case LE: case LEU: case UNLE:
10577 case GT: case GTU: case UNGT: case GE: case GEU: case UNGE:
10578 case UNORDERED: case ORDERED:
10579 /* We can't do anything if OP0 is a condition code value, rather
10580 than an actual data value. */
10583 || XEXP (op0, 0) == cc0_rtx
10585 || GET_MODE_CLASS (GET_MODE (XEXP (op0, 0))) == MODE_CC)
10588 /* Get the two operands being compared. */
10589 if (GET_CODE (XEXP (op0, 0)) == COMPARE)
10590 tem = XEXP (XEXP (op0, 0), 0), tem1 = XEXP (XEXP (op0, 0), 1);
10592 tem = XEXP (op0, 0), tem1 = XEXP (op0, 1);
10594 /* Check for the cases where we simply want the result of the
10595 earlier test or the opposite of that result. */
10596 if (code == NE || code == EQ
10597 || (GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
10598 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
10599 && (STORE_FLAG_VALUE
10600 & (((HOST_WIDE_INT) 1
10601 << (GET_MODE_BITSIZE (GET_MODE (op0)) - 1))))
10602 && (code == LT || code == GE)))
10604 enum rtx_code new_code;
10605 if (code == LT || code == NE)
10606 new_code = GET_CODE (op0);
10608 new_code = combine_reversed_comparison_code (op0);
10610 if (new_code != UNKNOWN)
10621 /* The sign bit of (ior (plus X (const_int -1)) X) is non-zero
10623 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == PLUS
10624 && XEXP (XEXP (op0, 0), 1) == constm1_rtx
10625 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
10627 op0 = XEXP (op0, 1);
10628 code = (code == GE ? GT : LE);
10634 /* Convert (and (xshift 1 X) Y) to (and (lshiftrt Y X) 1). This
10635 will be converted to a ZERO_EXTRACT later. */
10636 if (const_op == 0 && equality_comparison_p
10637 && GET_CODE (XEXP (op0, 0)) == ASHIFT
10638 && XEXP (XEXP (op0, 0), 0) == const1_rtx)
10640 op0 = simplify_and_const_int
10641 (op0, mode, gen_rtx_LSHIFTRT (mode,
10643 XEXP (XEXP (op0, 0), 1)),
10644 (HOST_WIDE_INT) 1);
10648 /* If we are comparing (and (lshiftrt X C1) C2) for equality with
10649 zero and X is a comparison and C1 and C2 describe only bits set
10650 in STORE_FLAG_VALUE, we can compare with X. */
10651 if (const_op == 0 && equality_comparison_p
10652 && mode_width <= HOST_BITS_PER_WIDE_INT
10653 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10654 && GET_CODE (XEXP (op0, 0)) == LSHIFTRT
10655 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
10656 && INTVAL (XEXP (XEXP (op0, 0), 1)) >= 0
10657 && INTVAL (XEXP (XEXP (op0, 0), 1)) < HOST_BITS_PER_WIDE_INT)
10659 mask = ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
10660 << INTVAL (XEXP (XEXP (op0, 0), 1)));
10661 if ((~STORE_FLAG_VALUE & mask) == 0
10662 && (GET_RTX_CLASS (GET_CODE (XEXP (XEXP (op0, 0), 0))) == '<'
10663 || ((tem = get_last_value (XEXP (XEXP (op0, 0), 0))) != 0
10664 && GET_RTX_CLASS (GET_CODE (tem)) == '<')))
10666 op0 = XEXP (XEXP (op0, 0), 0);
10671 /* If we are doing an equality comparison of an AND of a bit equal
10672 to the sign bit, replace this with a LT or GE comparison of
10673 the underlying value. */
10674 if (equality_comparison_p
10676 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10677 && mode_width <= HOST_BITS_PER_WIDE_INT
10678 && ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
10679 == (unsigned HOST_WIDE_INT) 1 << (mode_width - 1)))
10681 op0 = XEXP (op0, 0);
10682 code = (code == EQ ? GE : LT);
10686 /* If this AND operation is really a ZERO_EXTEND from a narrower
10687 mode, the constant fits within that mode, and this is either an
10688 equality or unsigned comparison, try to do this comparison in
10689 the narrower mode. */
10690 if ((equality_comparison_p || unsigned_comparison_p)
10691 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10692 && (i = exact_log2 ((INTVAL (XEXP (op0, 1))
10693 & GET_MODE_MASK (mode))
10695 && const_op >> i == 0
10696 && (tmode = mode_for_size (i, MODE_INT, 1)) != BLKmode)
10698 op0 = gen_lowpart_for_combine (tmode, XEXP (op0, 0));
10702 /* If this is (and:M1 (subreg:M2 X 0) (const_int C1)) where C1 fits
10703 in both M1 and M2 and the SUBREG is either paradoxical or
10704 represents the low part, permute the SUBREG and the AND and
10706 if (GET_CODE (XEXP (op0, 0)) == SUBREG
10708 #ifdef WORD_REGISTER_OPERATIONS
10710 > (GET_MODE_BITSIZE
10711 (GET_MODE (SUBREG_REG (XEXP (op0, 0))))))
10712 && mode_width <= BITS_PER_WORD)
10715 <= (GET_MODE_BITSIZE
10716 (GET_MODE (SUBREG_REG (XEXP (op0, 0))))))
10717 && subreg_lowpart_p (XEXP (op0, 0))))
10718 #ifndef WORD_REGISTER_OPERATIONS
10719 /* It is unsafe to commute the AND into the SUBREG if the SUBREG
10720 is paradoxical and WORD_REGISTER_OPERATIONS is not defined.
10721 As originally written the upper bits have a defined value
10722 due to the AND operation. However, if we commute the AND
10723 inside the SUBREG then they no longer have defined values
10724 and the meaning of the code has been changed. */
10725 && (GET_MODE_SIZE (GET_MODE (XEXP (op0, 0)))
10726 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (op0, 0)))))
10728 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10729 && mode_width <= HOST_BITS_PER_WIDE_INT
10730 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (XEXP (op0, 0))))
10731 <= HOST_BITS_PER_WIDE_INT)
10732 && (INTVAL (XEXP (op0, 1)) & ~mask) == 0
10733 && 0 == (~GET_MODE_MASK (GET_MODE (SUBREG_REG (XEXP (op0, 0))))
10734 & INTVAL (XEXP (op0, 1)))
10735 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (op0, 1)) != mask
10736 && ((unsigned HOST_WIDE_INT) INTVAL (XEXP (op0, 1))
10737 != GET_MODE_MASK (GET_MODE (SUBREG_REG (XEXP (op0, 0))))))
10741 = gen_lowpart_for_combine
10743 gen_binary (AND, GET_MODE (SUBREG_REG (XEXP (op0, 0))),
10744 SUBREG_REG (XEXP (op0, 0)), XEXP (op0, 1)));
10748 /* Convert (ne (and (lshiftrt (not X)) 1) 0) to
10749 (eq (and (lshiftrt X) 1) 0). */
10750 if (const_op == 0 && equality_comparison_p
10751 && XEXP (op0, 1) == const1_rtx
10752 && GET_CODE (XEXP (op0, 0)) == LSHIFTRT
10753 && GET_CODE (XEXP (XEXP (op0, 0), 0)) == NOT)
10755 op0 = simplify_and_const_int
10757 gen_rtx_LSHIFTRT (mode, XEXP (XEXP (XEXP (op0, 0), 0), 0),
10758 XEXP (XEXP (op0, 0), 1)),
10759 (HOST_WIDE_INT) 1);
10760 code = (code == NE ? EQ : NE);
10766 /* If we have (compare (ashift FOO N) (const_int C)) and
10767 the high order N bits of FOO (N+1 if an inequality comparison)
10768 are known to be zero, we can do this by comparing FOO with C
10769 shifted right N bits so long as the low-order N bits of C are
10771 if (GET_CODE (XEXP (op0, 1)) == CONST_INT
10772 && INTVAL (XEXP (op0, 1)) >= 0
10773 && ((INTVAL (XEXP (op0, 1)) + ! equality_comparison_p)
10774 < HOST_BITS_PER_WIDE_INT)
10776 & (((HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1))) - 1)) == 0)
10777 && mode_width <= HOST_BITS_PER_WIDE_INT
10778 && (nonzero_bits (XEXP (op0, 0), mode)
10779 & ~(mask >> (INTVAL (XEXP (op0, 1))
10780 + ! equality_comparison_p))) == 0)
10782 /* We must perform a logical shift, not an arithmetic one,
10783 as we want the top N bits of C to be zero. */
10784 unsigned HOST_WIDE_INT temp = const_op & GET_MODE_MASK (mode);
10786 temp >>= INTVAL (XEXP (op0, 1));
10787 op1 = GEN_INT (trunc_int_for_mode (temp, mode));
10788 op0 = XEXP (op0, 0);
10792 /* If we are doing a sign bit comparison, it means we are testing
10793 a particular bit. Convert it to the appropriate AND. */
10794 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 1)) == CONST_INT
10795 && mode_width <= HOST_BITS_PER_WIDE_INT)
10797 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
10800 - INTVAL (XEXP (op0, 1)))));
10801 code = (code == LT ? NE : EQ);
10805 /* If this an equality comparison with zero and we are shifting
10806 the low bit to the sign bit, we can convert this to an AND of the
10808 if (const_op == 0 && equality_comparison_p
10809 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10810 && INTVAL (XEXP (op0, 1)) == mode_width - 1)
10812 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
10813 (HOST_WIDE_INT) 1);
10819 /* If this is an equality comparison with zero, we can do this
10820 as a logical shift, which might be much simpler. */
10821 if (equality_comparison_p && const_op == 0
10822 && GET_CODE (XEXP (op0, 1)) == CONST_INT)
10824 op0 = simplify_shift_const (NULL_RTX, LSHIFTRT, mode,
10826 INTVAL (XEXP (op0, 1)));
10830 /* If OP0 is a sign extension and CODE is not an unsigned comparison,
10831 do the comparison in a narrower mode. */
10832 if (! unsigned_comparison_p
10833 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10834 && GET_CODE (XEXP (op0, 0)) == ASHIFT
10835 && XEXP (op0, 1) == XEXP (XEXP (op0, 0), 1)
10836 && (tmode = mode_for_size (mode_width - INTVAL (XEXP (op0, 1)),
10837 MODE_INT, 1)) != BLKmode
10838 && ((unsigned HOST_WIDE_INT) const_op <= GET_MODE_MASK (tmode)
10839 || ((unsigned HOST_WIDE_INT) -const_op
10840 <= GET_MODE_MASK (tmode))))
10842 op0 = gen_lowpart_for_combine (tmode, XEXP (XEXP (op0, 0), 0));
10846 /* Likewise if OP0 is a PLUS of a sign extension with a
10847 constant, which is usually represented with the PLUS
10848 between the shifts. */
10849 if (! unsigned_comparison_p
10850 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10851 && GET_CODE (XEXP (op0, 0)) == PLUS
10852 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
10853 && GET_CODE (XEXP (XEXP (op0, 0), 0)) == ASHIFT
10854 && XEXP (op0, 1) == XEXP (XEXP (XEXP (op0, 0), 0), 1)
10855 && (tmode = mode_for_size (mode_width - INTVAL (XEXP (op0, 1)),
10856 MODE_INT, 1)) != BLKmode
10857 && ((unsigned HOST_WIDE_INT) const_op <= GET_MODE_MASK (tmode)
10858 || ((unsigned HOST_WIDE_INT) -const_op
10859 <= GET_MODE_MASK (tmode))))
10861 rtx inner = XEXP (XEXP (XEXP (op0, 0), 0), 0);
10862 rtx add_const = XEXP (XEXP (op0, 0), 1);
10863 rtx new_const = gen_binary (ASHIFTRT, GET_MODE (op0), add_const,
10866 op0 = gen_binary (PLUS, tmode,
10867 gen_lowpart_for_combine (tmode, inner),
10872 /* ... fall through ... */
10874 /* If we have (compare (xshiftrt FOO N) (const_int C)) and
10875 the low order N bits of FOO are known to be zero, we can do this
10876 by comparing FOO with C shifted left N bits so long as no
10877 overflow occurs. */
10878 if (GET_CODE (XEXP (op0, 1)) == CONST_INT
10879 && INTVAL (XEXP (op0, 1)) >= 0
10880 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT
10881 && mode_width <= HOST_BITS_PER_WIDE_INT
10882 && (nonzero_bits (XEXP (op0, 0), mode)
10883 & (((HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1))) - 1)) == 0
10885 || (floor_log2 (const_op) + INTVAL (XEXP (op0, 1))
10888 const_op <<= INTVAL (XEXP (op0, 1));
10889 op1 = GEN_INT (const_op);
10890 op0 = XEXP (op0, 0);
10894 /* If we are using this shift to extract just the sign bit, we
10895 can replace this with an LT or GE comparison. */
10897 && (equality_comparison_p || sign_bit_comparison_p)
10898 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10899 && INTVAL (XEXP (op0, 1)) == mode_width - 1)
10901 op0 = XEXP (op0, 0);
10902 code = (code == NE || code == GT ? LT : GE);
10914 /* Now make any compound operations involved in this comparison. Then,
10915 check for an outmost SUBREG on OP0 that is not doing anything or is
10916 paradoxical. The latter case can only occur when it is known that the
10917 "extra" bits will be zero. Therefore, it is safe to remove the SUBREG.
10918 We can never remove a SUBREG for a non-equality comparison because the
10919 sign bit is in a different place in the underlying object. */
10921 op0 = make_compound_operation (op0, op1 == const0_rtx ? COMPARE : SET);
10922 op1 = make_compound_operation (op1, SET);
10924 if (GET_CODE (op0) == SUBREG && subreg_lowpart_p (op0)
10925 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
10926 && GET_MODE_CLASS (GET_MODE (SUBREG_REG (op0))) == MODE_INT
10927 && (code == NE || code == EQ)
10928 && ((GET_MODE_SIZE (GET_MODE (op0))
10929 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (op0))))))
10931 op0 = SUBREG_REG (op0);
10932 op1 = gen_lowpart_for_combine (GET_MODE (op0), op1);
10935 else if (GET_CODE (op0) == SUBREG && subreg_lowpart_p (op0)
10936 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
10937 && GET_MODE_CLASS (GET_MODE (SUBREG_REG (op0))) == MODE_INT
10938 && (code == NE || code == EQ)
10939 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0)))
10940 <= HOST_BITS_PER_WIDE_INT)
10941 && (nonzero_bits (SUBREG_REG (op0), GET_MODE (SUBREG_REG (op0)))
10942 & ~GET_MODE_MASK (GET_MODE (op0))) == 0
10943 && (tem = gen_lowpart_for_combine (GET_MODE (SUBREG_REG (op0)),
10945 (nonzero_bits (tem, GET_MODE (SUBREG_REG (op0)))
10946 & ~GET_MODE_MASK (GET_MODE (op0))) == 0))
10947 op0 = SUBREG_REG (op0), op1 = tem;
10949 /* We now do the opposite procedure: Some machines don't have compare
10950 insns in all modes. If OP0's mode is an integer mode smaller than a
10951 word and we can't do a compare in that mode, see if there is a larger
10952 mode for which we can do the compare. There are a number of cases in
10953 which we can use the wider mode. */
10955 mode = GET_MODE (op0);
10956 if (mode != VOIDmode && GET_MODE_CLASS (mode) == MODE_INT
10957 && GET_MODE_SIZE (mode) < UNITS_PER_WORD
10958 && ! have_insn_for (COMPARE, mode))
10959 for (tmode = GET_MODE_WIDER_MODE (mode);
10961 && GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT);
10962 tmode = GET_MODE_WIDER_MODE (tmode))
10963 if (have_insn_for (COMPARE, tmode))
10965 /* If the only nonzero bits in OP0 and OP1 are those in the
10966 narrower mode and this is an equality or unsigned comparison,
10967 we can use the wider mode. Similarly for sign-extended
10968 values, in which case it is true for all comparisons. */
10969 if (((code == EQ || code == NE
10970 || code == GEU || code == GTU || code == LEU || code == LTU)
10971 && (nonzero_bits (op0, tmode) & ~GET_MODE_MASK (mode)) == 0
10972 && (nonzero_bits (op1, tmode) & ~GET_MODE_MASK (mode)) == 0)
10973 || ((num_sign_bit_copies (op0, tmode)
10974 > GET_MODE_BITSIZE (tmode) - GET_MODE_BITSIZE (mode))
10975 && (num_sign_bit_copies (op1, tmode)
10976 > GET_MODE_BITSIZE (tmode) - GET_MODE_BITSIZE (mode))))
10978 /* If OP0 is an AND and we don't have an AND in MODE either,
10979 make a new AND in the proper mode. */
10980 if (GET_CODE (op0) == AND
10981 && !have_insn_for (AND, mode))
10982 op0 = gen_binary (AND, tmode,
10983 gen_lowpart_for_combine (tmode,
10985 gen_lowpart_for_combine (tmode,
10988 op0 = gen_lowpart_for_combine (tmode, op0);
10989 op1 = gen_lowpart_for_combine (tmode, op1);
10993 /* If this is a test for negative, we can make an explicit
10994 test of the sign bit. */
10996 if (op1 == const0_rtx && (code == LT || code == GE)
10997 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
10999 op0 = gen_binary (AND, tmode,
11000 gen_lowpart_for_combine (tmode, op0),
11001 GEN_INT ((HOST_WIDE_INT) 1
11002 << (GET_MODE_BITSIZE (mode) - 1)));
11003 code = (code == LT) ? NE : EQ;
11008 #ifdef CANONICALIZE_COMPARISON
11009 /* If this machine only supports a subset of valid comparisons, see if we
11010 can convert an unsupported one into a supported one. */
11011 CANONICALIZE_COMPARISON (code, op0, op1);
11020 /* Like jump.c' reversed_comparison_code, but use combine infrastructure for
11021 searching backward. */
11022 static enum rtx_code
11023 combine_reversed_comparison_code (exp)
11026 enum rtx_code code1 = reversed_comparison_code (exp, NULL);
11029 if (code1 != UNKNOWN
11030 || GET_MODE_CLASS (GET_MODE (XEXP (exp, 0))) != MODE_CC)
11032 /* Otherwise try and find where the condition codes were last set and
11034 x = get_last_value (XEXP (exp, 0));
11035 if (!x || GET_CODE (x) != COMPARE)
11037 return reversed_comparison_code_parts (GET_CODE (exp),
11038 XEXP (x, 0), XEXP (x, 1), NULL);
11040 /* Return comparison with reversed code of EXP and operands OP0 and OP1.
11041 Return NULL_RTX in case we fail to do the reversal. */
11043 reversed_comparison (exp, mode, op0, op1)
11045 enum machine_mode mode;
11047 enum rtx_code reversed_code = combine_reversed_comparison_code (exp);
11048 if (reversed_code == UNKNOWN)
11051 return gen_binary (reversed_code, mode, op0, op1);
11054 /* Utility function for following routine. Called when X is part of a value
11055 being stored into reg_last_set_value. Sets reg_last_set_table_tick
11056 for each register mentioned. Similar to mention_regs in cse.c */
11059 update_table_tick (x)
11062 enum rtx_code code = GET_CODE (x);
11063 const char *fmt = GET_RTX_FORMAT (code);
11068 unsigned int regno = REGNO (x);
11069 unsigned int endregno
11070 = regno + (regno < FIRST_PSEUDO_REGISTER
11071 ? HARD_REGNO_NREGS (regno, GET_MODE (x)) : 1);
11074 for (r = regno; r < endregno; r++)
11075 reg_last_set_table_tick[r] = label_tick;
11080 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
11081 /* Note that we can't have an "E" in values stored; see
11082 get_last_value_validate. */
11084 update_table_tick (XEXP (x, i));
11087 /* Record that REG is set to VALUE in insn INSN. If VALUE is zero, we
11088 are saying that the register is clobbered and we no longer know its
11089 value. If INSN is zero, don't update reg_last_set; this is only permitted
11090 with VALUE also zero and is used to invalidate the register. */
11093 record_value_for_reg (reg, insn, value)
11098 unsigned int regno = REGNO (reg);
11099 unsigned int endregno
11100 = regno + (regno < FIRST_PSEUDO_REGISTER
11101 ? HARD_REGNO_NREGS (regno, GET_MODE (reg)) : 1);
11104 /* If VALUE contains REG and we have a previous value for REG, substitute
11105 the previous value. */
11106 if (value && insn && reg_overlap_mentioned_p (reg, value))
11110 /* Set things up so get_last_value is allowed to see anything set up to
11112 subst_low_cuid = INSN_CUID (insn);
11113 tem = get_last_value (reg);
11115 /* If TEM is simply a binary operation with two CLOBBERs as operands,
11116 it isn't going to be useful and will take a lot of time to process,
11117 so just use the CLOBBER. */
11121 if ((GET_RTX_CLASS (GET_CODE (tem)) == '2'
11122 || GET_RTX_CLASS (GET_CODE (tem)) == 'c')
11123 && GET_CODE (XEXP (tem, 0)) == CLOBBER
11124 && GET_CODE (XEXP (tem, 1)) == CLOBBER)
11125 tem = XEXP (tem, 0);
11127 value = replace_rtx (copy_rtx (value), reg, tem);
11131 /* For each register modified, show we don't know its value, that
11132 we don't know about its bitwise content, that its value has been
11133 updated, and that we don't know the location of the death of the
11135 for (i = regno; i < endregno; i++)
11138 reg_last_set[i] = insn;
11140 reg_last_set_value[i] = 0;
11141 reg_last_set_mode[i] = 0;
11142 reg_last_set_nonzero_bits[i] = 0;
11143 reg_last_set_sign_bit_copies[i] = 0;
11144 reg_last_death[i] = 0;
11147 /* Mark registers that are being referenced in this value. */
11149 update_table_tick (value);
11151 /* Now update the status of each register being set.
11152 If someone is using this register in this block, set this register
11153 to invalid since we will get confused between the two lives in this
11154 basic block. This makes using this register always invalid. In cse, we
11155 scan the table to invalidate all entries using this register, but this
11156 is too much work for us. */
11158 for (i = regno; i < endregno; i++)
11160 reg_last_set_label[i] = label_tick;
11161 if (value && reg_last_set_table_tick[i] == label_tick)
11162 reg_last_set_invalid[i] = 1;
11164 reg_last_set_invalid[i] = 0;
11167 /* The value being assigned might refer to X (like in "x++;"). In that
11168 case, we must replace it with (clobber (const_int 0)) to prevent
11170 if (value && ! get_last_value_validate (&value, insn,
11171 reg_last_set_label[regno], 0))
11173 value = copy_rtx (value);
11174 if (! get_last_value_validate (&value, insn,
11175 reg_last_set_label[regno], 1))
11179 /* For the main register being modified, update the value, the mode, the
11180 nonzero bits, and the number of sign bit copies. */
11182 reg_last_set_value[regno] = value;
11186 subst_low_cuid = INSN_CUID (insn);
11187 reg_last_set_mode[regno] = GET_MODE (reg);
11188 reg_last_set_nonzero_bits[regno] = nonzero_bits (value, GET_MODE (reg));
11189 reg_last_set_sign_bit_copies[regno]
11190 = num_sign_bit_copies (value, GET_MODE (reg));
11194 /* Called via note_stores from record_dead_and_set_regs to handle one
11195 SET or CLOBBER in an insn. DATA is the instruction in which the
11196 set is occurring. */
11199 record_dead_and_set_regs_1 (dest, setter, data)
11203 rtx record_dead_insn = (rtx) data;
11205 if (GET_CODE (dest) == SUBREG)
11206 dest = SUBREG_REG (dest);
11208 if (GET_CODE (dest) == REG)
11210 /* If we are setting the whole register, we know its value. Otherwise
11211 show that we don't know the value. We can handle SUBREG in
11213 if (GET_CODE (setter) == SET && dest == SET_DEST (setter))
11214 record_value_for_reg (dest, record_dead_insn, SET_SRC (setter));
11215 else if (GET_CODE (setter) == SET
11216 && GET_CODE (SET_DEST (setter)) == SUBREG
11217 && SUBREG_REG (SET_DEST (setter)) == dest
11218 && GET_MODE_BITSIZE (GET_MODE (dest)) <= BITS_PER_WORD
11219 && subreg_lowpart_p (SET_DEST (setter)))
11220 record_value_for_reg (dest, record_dead_insn,
11221 gen_lowpart_for_combine (GET_MODE (dest),
11222 SET_SRC (setter)));
11224 record_value_for_reg (dest, record_dead_insn, NULL_RTX);
11226 else if (GET_CODE (dest) == MEM
11227 /* Ignore pushes, they clobber nothing. */
11228 && ! push_operand (dest, GET_MODE (dest)))
11229 mem_last_set = INSN_CUID (record_dead_insn);
11232 /* Update the records of when each REG was most recently set or killed
11233 for the things done by INSN. This is the last thing done in processing
11234 INSN in the combiner loop.
11236 We update reg_last_set, reg_last_set_value, reg_last_set_mode,
11237 reg_last_set_nonzero_bits, reg_last_set_sign_bit_copies, reg_last_death,
11238 and also the similar information mem_last_set (which insn most recently
11239 modified memory) and last_call_cuid (which insn was the most recent
11240 subroutine call). */
11243 record_dead_and_set_regs (insn)
11249 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
11251 if (REG_NOTE_KIND (link) == REG_DEAD
11252 && GET_CODE (XEXP (link, 0)) == REG)
11254 unsigned int regno = REGNO (XEXP (link, 0));
11255 unsigned int endregno
11256 = regno + (regno < FIRST_PSEUDO_REGISTER
11257 ? HARD_REGNO_NREGS (regno, GET_MODE (XEXP (link, 0)))
11260 for (i = regno; i < endregno; i++)
11261 reg_last_death[i] = insn;
11263 else if (REG_NOTE_KIND (link) == REG_INC)
11264 record_value_for_reg (XEXP (link, 0), insn, NULL_RTX);
11267 if (GET_CODE (insn) == CALL_INSN)
11269 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
11270 if (TEST_HARD_REG_BIT (regs_invalidated_by_call, i))
11272 reg_last_set_value[i] = 0;
11273 reg_last_set_mode[i] = 0;
11274 reg_last_set_nonzero_bits[i] = 0;
11275 reg_last_set_sign_bit_copies[i] = 0;
11276 reg_last_death[i] = 0;
11279 last_call_cuid = mem_last_set = INSN_CUID (insn);
11281 /* Don't bother recording what this insn does. It might set the
11282 return value register, but we can't combine into a call
11283 pattern anyway, so there's no point trying (and it may cause
11284 a crash, if e.g. we wind up asking for last_set_value of a
11285 SUBREG of the return value register). */
11289 note_stores (PATTERN (insn), record_dead_and_set_regs_1, insn);
11292 /* If a SUBREG has the promoted bit set, it is in fact a property of the
11293 register present in the SUBREG, so for each such SUBREG go back and
11294 adjust nonzero and sign bit information of the registers that are
11295 known to have some zero/sign bits set.
11297 This is needed because when combine blows the SUBREGs away, the
11298 information on zero/sign bits is lost and further combines can be
11299 missed because of that. */
11302 record_promoted_value (insn, subreg)
11307 unsigned int regno = REGNO (SUBREG_REG (subreg));
11308 enum machine_mode mode = GET_MODE (subreg);
11310 if (GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT)
11313 for (links = LOG_LINKS (insn); links;)
11315 insn = XEXP (links, 0);
11316 set = single_set (insn);
11318 if (! set || GET_CODE (SET_DEST (set)) != REG
11319 || REGNO (SET_DEST (set)) != regno
11320 || GET_MODE (SET_DEST (set)) != GET_MODE (SUBREG_REG (subreg)))
11322 links = XEXP (links, 1);
11326 if (reg_last_set[regno] == insn)
11328 if (SUBREG_PROMOTED_UNSIGNED_P (subreg) > 0)
11329 reg_last_set_nonzero_bits[regno] &= GET_MODE_MASK (mode);
11332 if (GET_CODE (SET_SRC (set)) == REG)
11334 regno = REGNO (SET_SRC (set));
11335 links = LOG_LINKS (insn);
11342 /* Scan X for promoted SUBREGs. For each one found,
11343 note what it implies to the registers used in it. */
11346 check_promoted_subreg (insn, x)
11350 if (GET_CODE (x) == SUBREG && SUBREG_PROMOTED_VAR_P (x)
11351 && GET_CODE (SUBREG_REG (x)) == REG)
11352 record_promoted_value (insn, x);
11355 const char *format = GET_RTX_FORMAT (GET_CODE (x));
11358 for (i = 0; i < GET_RTX_LENGTH (GET_CODE (x)); i++)
11362 check_promoted_subreg (insn, XEXP (x, i));
11366 if (XVEC (x, i) != 0)
11367 for (j = 0; j < XVECLEN (x, i); j++)
11368 check_promoted_subreg (insn, XVECEXP (x, i, j));
11374 /* Utility routine for the following function. Verify that all the registers
11375 mentioned in *LOC are valid when *LOC was part of a value set when
11376 label_tick == TICK. Return 0 if some are not.
11378 If REPLACE is non-zero, replace the invalid reference with
11379 (clobber (const_int 0)) and return 1. This replacement is useful because
11380 we often can get useful information about the form of a value (e.g., if
11381 it was produced by a shift that always produces -1 or 0) even though
11382 we don't know exactly what registers it was produced from. */
11385 get_last_value_validate (loc, insn, tick, replace)
11392 const char *fmt = GET_RTX_FORMAT (GET_CODE (x));
11393 int len = GET_RTX_LENGTH (GET_CODE (x));
11396 if (GET_CODE (x) == REG)
11398 unsigned int regno = REGNO (x);
11399 unsigned int endregno
11400 = regno + (regno < FIRST_PSEUDO_REGISTER
11401 ? HARD_REGNO_NREGS (regno, GET_MODE (x)) : 1);
11404 for (j = regno; j < endregno; j++)
11405 if (reg_last_set_invalid[j]
11406 /* If this is a pseudo-register that was only set once and not
11407 live at the beginning of the function, it is always valid. */
11408 || (! (regno >= FIRST_PSEUDO_REGISTER
11409 && REG_N_SETS (regno) == 1
11410 && (! REGNO_REG_SET_P
11411 (BASIC_BLOCK (0)->global_live_at_start, regno)))
11412 && reg_last_set_label[j] > tick))
11415 *loc = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
11421 /* If this is a memory reference, make sure that there were
11422 no stores after it that might have clobbered the value. We don't
11423 have alias info, so we assume any store invalidates it. */
11424 else if (GET_CODE (x) == MEM && ! RTX_UNCHANGING_P (x)
11425 && INSN_CUID (insn) <= mem_last_set)
11428 *loc = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
11432 for (i = 0; i < len; i++)
11434 && get_last_value_validate (&XEXP (x, i), insn, tick, replace) == 0)
11435 /* Don't bother with these. They shouldn't occur anyway. */
11439 /* If we haven't found a reason for it to be invalid, it is valid. */
11443 /* Get the last value assigned to X, if known. Some registers
11444 in the value may be replaced with (clobber (const_int 0)) if their value
11445 is known longer known reliably. */
11451 unsigned int regno;
11454 /* If this is a non-paradoxical SUBREG, get the value of its operand and
11455 then convert it to the desired mode. If this is a paradoxical SUBREG,
11456 we cannot predict what values the "extra" bits might have. */
11457 if (GET_CODE (x) == SUBREG
11458 && subreg_lowpart_p (x)
11459 && (GET_MODE_SIZE (GET_MODE (x))
11460 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
11461 && (value = get_last_value (SUBREG_REG (x))) != 0)
11462 return gen_lowpart_for_combine (GET_MODE (x), value);
11464 if (GET_CODE (x) != REG)
11468 value = reg_last_set_value[regno];
11470 /* If we don't have a value, or if it isn't for this basic block and
11471 it's either a hard register, set more than once, or it's a live
11472 at the beginning of the function, return 0.
11474 Because if it's not live at the beginning of the function then the reg
11475 is always set before being used (is never used without being set).
11476 And, if it's set only once, and it's always set before use, then all
11477 uses must have the same last value, even if it's not from this basic
11481 || (reg_last_set_label[regno] != label_tick
11482 && (regno < FIRST_PSEUDO_REGISTER
11483 || REG_N_SETS (regno) != 1
11484 || (REGNO_REG_SET_P
11485 (BASIC_BLOCK (0)->global_live_at_start, regno)))))
11488 /* If the value was set in a later insn than the ones we are processing,
11489 we can't use it even if the register was only set once. */
11490 if (INSN_CUID (reg_last_set[regno]) >= subst_low_cuid)
11493 /* If the value has all its registers valid, return it. */
11494 if (get_last_value_validate (&value, reg_last_set[regno],
11495 reg_last_set_label[regno], 0))
11498 /* Otherwise, make a copy and replace any invalid register with
11499 (clobber (const_int 0)). If that fails for some reason, return 0. */
11501 value = copy_rtx (value);
11502 if (get_last_value_validate (&value, reg_last_set[regno],
11503 reg_last_set_label[regno], 1))
11509 /* Return nonzero if expression X refers to a REG or to memory
11510 that is set in an instruction more recent than FROM_CUID. */
11513 use_crosses_set_p (x, from_cuid)
11519 enum rtx_code code = GET_CODE (x);
11523 unsigned int regno = REGNO (x);
11524 unsigned endreg = regno + (regno < FIRST_PSEUDO_REGISTER
11525 ? HARD_REGNO_NREGS (regno, GET_MODE (x)) : 1);
11527 #ifdef PUSH_ROUNDING
11528 /* Don't allow uses of the stack pointer to be moved,
11529 because we don't know whether the move crosses a push insn. */
11530 if (regno == STACK_POINTER_REGNUM && PUSH_ARGS)
11533 for (; regno < endreg; regno++)
11534 if (reg_last_set[regno]
11535 && INSN_CUID (reg_last_set[regno]) > from_cuid)
11540 if (code == MEM && mem_last_set > from_cuid)
11543 fmt = GET_RTX_FORMAT (code);
11545 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
11550 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
11551 if (use_crosses_set_p (XVECEXP (x, i, j), from_cuid))
11554 else if (fmt[i] == 'e'
11555 && use_crosses_set_p (XEXP (x, i), from_cuid))
11561 /* Define three variables used for communication between the following
11564 static unsigned int reg_dead_regno, reg_dead_endregno;
11565 static int reg_dead_flag;
11567 /* Function called via note_stores from reg_dead_at_p.
11569 If DEST is within [reg_dead_regno, reg_dead_endregno), set
11570 reg_dead_flag to 1 if X is a CLOBBER and to -1 it is a SET. */
11573 reg_dead_at_p_1 (dest, x, data)
11576 void *data ATTRIBUTE_UNUSED;
11578 unsigned int regno, endregno;
11580 if (GET_CODE (dest) != REG)
11583 regno = REGNO (dest);
11584 endregno = regno + (regno < FIRST_PSEUDO_REGISTER
11585 ? HARD_REGNO_NREGS (regno, GET_MODE (dest)) : 1);
11587 if (reg_dead_endregno > regno && reg_dead_regno < endregno)
11588 reg_dead_flag = (GET_CODE (x) == CLOBBER) ? 1 : -1;
11591 /* Return non-zero if REG is known to be dead at INSN.
11593 We scan backwards from INSN. If we hit a REG_DEAD note or a CLOBBER
11594 referencing REG, it is dead. If we hit a SET referencing REG, it is
11595 live. Otherwise, see if it is live or dead at the start of the basic
11596 block we are in. Hard regs marked as being live in NEWPAT_USED_REGS
11597 must be assumed to be always live. */
11600 reg_dead_at_p (reg, insn)
11607 /* Set variables for reg_dead_at_p_1. */
11608 reg_dead_regno = REGNO (reg);
11609 reg_dead_endregno = reg_dead_regno + (reg_dead_regno < FIRST_PSEUDO_REGISTER
11610 ? HARD_REGNO_NREGS (reg_dead_regno,
11616 /* Check that reg isn't mentioned in NEWPAT_USED_REGS. */
11617 if (reg_dead_regno < FIRST_PSEUDO_REGISTER)
11619 for (i = reg_dead_regno; i < reg_dead_endregno; i++)
11620 if (TEST_HARD_REG_BIT (newpat_used_regs, i))
11624 /* Scan backwards until we find a REG_DEAD note, SET, CLOBBER, label, or
11625 beginning of function. */
11626 for (; insn && GET_CODE (insn) != CODE_LABEL && GET_CODE (insn) != BARRIER;
11627 insn = prev_nonnote_insn (insn))
11629 note_stores (PATTERN (insn), reg_dead_at_p_1, NULL);
11631 return reg_dead_flag == 1 ? 1 : 0;
11633 if (find_regno_note (insn, REG_DEAD, reg_dead_regno))
11637 /* Get the basic block number that we were in. */
11642 for (block = 0; block < n_basic_blocks; block++)
11643 if (insn == BLOCK_HEAD (block))
11646 if (block == n_basic_blocks)
11650 for (i = reg_dead_regno; i < reg_dead_endregno; i++)
11651 if (REGNO_REG_SET_P (BASIC_BLOCK (block)->global_live_at_start, i))
11657 /* Note hard registers in X that are used. This code is similar to
11658 that in flow.c, but much simpler since we don't care about pseudos. */
11661 mark_used_regs_combine (x)
11664 RTX_CODE code = GET_CODE (x);
11665 unsigned int regno;
11678 case ADDR_DIFF_VEC:
11681 /* CC0 must die in the insn after it is set, so we don't need to take
11682 special note of it here. */
11688 /* If we are clobbering a MEM, mark any hard registers inside the
11689 address as used. */
11690 if (GET_CODE (XEXP (x, 0)) == MEM)
11691 mark_used_regs_combine (XEXP (XEXP (x, 0), 0));
11696 /* A hard reg in a wide mode may really be multiple registers.
11697 If so, mark all of them just like the first. */
11698 if (regno < FIRST_PSEUDO_REGISTER)
11700 unsigned int endregno, r;
11702 /* None of this applies to the stack, frame or arg pointers */
11703 if (regno == STACK_POINTER_REGNUM
11704 #if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM
11705 || regno == HARD_FRAME_POINTER_REGNUM
11707 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
11708 || (regno == ARG_POINTER_REGNUM && fixed_regs[regno])
11710 || regno == FRAME_POINTER_REGNUM)
11713 endregno = regno + HARD_REGNO_NREGS (regno, GET_MODE (x));
11714 for (r = regno; r < endregno; r++)
11715 SET_HARD_REG_BIT (newpat_used_regs, r);
11721 /* If setting a MEM, or a SUBREG of a MEM, then note any hard regs in
11723 rtx testreg = SET_DEST (x);
11725 while (GET_CODE (testreg) == SUBREG
11726 || GET_CODE (testreg) == ZERO_EXTRACT
11727 || GET_CODE (testreg) == SIGN_EXTRACT
11728 || GET_CODE (testreg) == STRICT_LOW_PART)
11729 testreg = XEXP (testreg, 0);
11731 if (GET_CODE (testreg) == MEM)
11732 mark_used_regs_combine (XEXP (testreg, 0));
11734 mark_used_regs_combine (SET_SRC (x));
11742 /* Recursively scan the operands of this expression. */
11745 const char *fmt = GET_RTX_FORMAT (code);
11747 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
11750 mark_used_regs_combine (XEXP (x, i));
11751 else if (fmt[i] == 'E')
11755 for (j = 0; j < XVECLEN (x, i); j++)
11756 mark_used_regs_combine (XVECEXP (x, i, j));
11762 /* Remove register number REGNO from the dead registers list of INSN.
11764 Return the note used to record the death, if there was one. */
11767 remove_death (regno, insn)
11768 unsigned int regno;
11771 rtx note = find_regno_note (insn, REG_DEAD, regno);
11775 REG_N_DEATHS (regno)--;
11776 remove_note (insn, note);
11782 /* For each register (hardware or pseudo) used within expression X, if its
11783 death is in an instruction with cuid between FROM_CUID (inclusive) and
11784 TO_INSN (exclusive), put a REG_DEAD note for that register in the
11785 list headed by PNOTES.
11787 That said, don't move registers killed by maybe_kill_insn.
11789 This is done when X is being merged by combination into TO_INSN. These
11790 notes will then be distributed as needed. */
11793 move_deaths (x, maybe_kill_insn, from_cuid, to_insn, pnotes)
11795 rtx maybe_kill_insn;
11802 enum rtx_code code = GET_CODE (x);
11806 unsigned int regno = REGNO (x);
11807 rtx where_dead = reg_last_death[regno];
11808 rtx before_dead, after_dead;
11810 /* Don't move the register if it gets killed in between from and to */
11811 if (maybe_kill_insn && reg_set_p (x, maybe_kill_insn)
11812 && ! reg_referenced_p (x, maybe_kill_insn))
11815 /* WHERE_DEAD could be a USE insn made by combine, so first we
11816 make sure that we have insns with valid INSN_CUID values. */
11817 before_dead = where_dead;
11818 while (before_dead && INSN_UID (before_dead) > max_uid_cuid)
11819 before_dead = PREV_INSN (before_dead);
11821 after_dead = where_dead;
11822 while (after_dead && INSN_UID (after_dead) > max_uid_cuid)
11823 after_dead = NEXT_INSN (after_dead);
11825 if (before_dead && after_dead
11826 && INSN_CUID (before_dead) >= from_cuid
11827 && (INSN_CUID (after_dead) < INSN_CUID (to_insn)
11828 || (where_dead != after_dead
11829 && INSN_CUID (after_dead) == INSN_CUID (to_insn))))
11831 rtx note = remove_death (regno, where_dead);
11833 /* It is possible for the call above to return 0. This can occur
11834 when reg_last_death points to I2 or I1 that we combined with.
11835 In that case make a new note.
11837 We must also check for the case where X is a hard register
11838 and NOTE is a death note for a range of hard registers
11839 including X. In that case, we must put REG_DEAD notes for
11840 the remaining registers in place of NOTE. */
11842 if (note != 0 && regno < FIRST_PSEUDO_REGISTER
11843 && (GET_MODE_SIZE (GET_MODE (XEXP (note, 0)))
11844 > GET_MODE_SIZE (GET_MODE (x))))
11846 unsigned int deadregno = REGNO (XEXP (note, 0));
11847 unsigned int deadend
11848 = (deadregno + HARD_REGNO_NREGS (deadregno,
11849 GET_MODE (XEXP (note, 0))));
11850 unsigned int ourend
11851 = regno + HARD_REGNO_NREGS (regno, GET_MODE (x));
11854 for (i = deadregno; i < deadend; i++)
11855 if (i < regno || i >= ourend)
11856 REG_NOTES (where_dead)
11857 = gen_rtx_EXPR_LIST (REG_DEAD,
11858 gen_rtx_REG (reg_raw_mode[i], i),
11859 REG_NOTES (where_dead));
11862 /* If we didn't find any note, or if we found a REG_DEAD note that
11863 covers only part of the given reg, and we have a multi-reg hard
11864 register, then to be safe we must check for REG_DEAD notes
11865 for each register other than the first. They could have
11866 their own REG_DEAD notes lying around. */
11867 else if ((note == 0
11869 && (GET_MODE_SIZE (GET_MODE (XEXP (note, 0)))
11870 < GET_MODE_SIZE (GET_MODE (x)))))
11871 && regno < FIRST_PSEUDO_REGISTER
11872 && HARD_REGNO_NREGS (regno, GET_MODE (x)) > 1)
11874 unsigned int ourend
11875 = regno + HARD_REGNO_NREGS (regno, GET_MODE (x));
11876 unsigned int i, offset;
11880 offset = HARD_REGNO_NREGS (regno, GET_MODE (XEXP (note, 0)));
11884 for (i = regno + offset; i < ourend; i++)
11885 move_deaths (gen_rtx_REG (reg_raw_mode[i], i),
11886 maybe_kill_insn, from_cuid, to_insn, &oldnotes);
11889 if (note != 0 && GET_MODE (XEXP (note, 0)) == GET_MODE (x))
11891 XEXP (note, 1) = *pnotes;
11895 *pnotes = gen_rtx_EXPR_LIST (REG_DEAD, x, *pnotes);
11897 REG_N_DEATHS (regno)++;
11903 else if (GET_CODE (x) == SET)
11905 rtx dest = SET_DEST (x);
11907 move_deaths (SET_SRC (x), maybe_kill_insn, from_cuid, to_insn, pnotes);
11909 /* In the case of a ZERO_EXTRACT, a STRICT_LOW_PART, or a SUBREG
11910 that accesses one word of a multi-word item, some
11911 piece of everything register in the expression is used by
11912 this insn, so remove any old death. */
11913 /* ??? So why do we test for equality of the sizes? */
11915 if (GET_CODE (dest) == ZERO_EXTRACT
11916 || GET_CODE (dest) == STRICT_LOW_PART
11917 || (GET_CODE (dest) == SUBREG
11918 && (((GET_MODE_SIZE (GET_MODE (dest))
11919 + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
11920 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (dest)))
11921 + UNITS_PER_WORD - 1) / UNITS_PER_WORD))))
11923 move_deaths (dest, maybe_kill_insn, from_cuid, to_insn, pnotes);
11927 /* If this is some other SUBREG, we know it replaces the entire
11928 value, so use that as the destination. */
11929 if (GET_CODE (dest) == SUBREG)
11930 dest = SUBREG_REG (dest);
11932 /* If this is a MEM, adjust deaths of anything used in the address.
11933 For a REG (the only other possibility), the entire value is
11934 being replaced so the old value is not used in this insn. */
11936 if (GET_CODE (dest) == MEM)
11937 move_deaths (XEXP (dest, 0), maybe_kill_insn, from_cuid,
11942 else if (GET_CODE (x) == CLOBBER)
11945 len = GET_RTX_LENGTH (code);
11946 fmt = GET_RTX_FORMAT (code);
11948 for (i = 0; i < len; i++)
11953 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
11954 move_deaths (XVECEXP (x, i, j), maybe_kill_insn, from_cuid,
11957 else if (fmt[i] == 'e')
11958 move_deaths (XEXP (x, i), maybe_kill_insn, from_cuid, to_insn, pnotes);
11962 /* Return 1 if X is the target of a bit-field assignment in BODY, the
11963 pattern of an insn. X must be a REG. */
11966 reg_bitfield_target_p (x, body)
11972 if (GET_CODE (body) == SET)
11974 rtx dest = SET_DEST (body);
11976 unsigned int regno, tregno, endregno, endtregno;
11978 if (GET_CODE (dest) == ZERO_EXTRACT)
11979 target = XEXP (dest, 0);
11980 else if (GET_CODE (dest) == STRICT_LOW_PART)
11981 target = SUBREG_REG (XEXP (dest, 0));
11985 if (GET_CODE (target) == SUBREG)
11986 target = SUBREG_REG (target);
11988 if (GET_CODE (target) != REG)
11991 tregno = REGNO (target), regno = REGNO (x);
11992 if (tregno >= FIRST_PSEUDO_REGISTER || regno >= FIRST_PSEUDO_REGISTER)
11993 return target == x;
11995 endtregno = tregno + HARD_REGNO_NREGS (tregno, GET_MODE (target));
11996 endregno = regno + HARD_REGNO_NREGS (regno, GET_MODE (x));
11998 return endregno > tregno && regno < endtregno;
12001 else if (GET_CODE (body) == PARALLEL)
12002 for (i = XVECLEN (body, 0) - 1; i >= 0; i--)
12003 if (reg_bitfield_target_p (x, XVECEXP (body, 0, i)))
12009 /* Given a chain of REG_NOTES originally from FROM_INSN, try to place them
12010 as appropriate. I3 and I2 are the insns resulting from the combination
12011 insns including FROM (I2 may be zero).
12013 ELIM_I2 and ELIM_I1 are either zero or registers that we know will
12014 not need REG_DEAD notes because they are being substituted for. This
12015 saves searching in the most common cases.
12017 Each note in the list is either ignored or placed on some insns, depending
12018 on the type of note. */
12021 distribute_notes (notes, from_insn, i3, i2, elim_i2, elim_i1)
12025 rtx elim_i2, elim_i1;
12027 rtx note, next_note;
12030 for (note = notes; note; note = next_note)
12032 rtx place = 0, place2 = 0;
12034 /* If this NOTE references a pseudo register, ensure it references
12035 the latest copy of that register. */
12036 if (XEXP (note, 0) && GET_CODE (XEXP (note, 0)) == REG
12037 && REGNO (XEXP (note, 0)) >= FIRST_PSEUDO_REGISTER)
12038 XEXP (note, 0) = regno_reg_rtx[REGNO (XEXP (note, 0))];
12040 next_note = XEXP (note, 1);
12041 switch (REG_NOTE_KIND (note))
12045 case REG_EXEC_COUNT:
12046 /* Doesn't matter much where we put this, as long as it's somewhere.
12047 It is preferable to keep these notes on branches, which is most
12048 likely to be i3. */
12052 case REG_VTABLE_REF:
12053 /* ??? Should remain with *a particular* memory load. Given the
12054 nature of vtable data, the last insn seems relatively safe. */
12058 case REG_NON_LOCAL_GOTO:
12059 if (GET_CODE (i3) == JUMP_INSN)
12061 else if (i2 && GET_CODE (i2) == JUMP_INSN)
12067 case REG_EH_REGION:
12068 /* These notes must remain with the call or trapping instruction. */
12069 if (GET_CODE (i3) == CALL_INSN)
12071 else if (i2 && GET_CODE (i2) == CALL_INSN)
12073 else if (flag_non_call_exceptions)
12075 if (may_trap_p (i3))
12077 else if (i2 && may_trap_p (i2))
12079 /* ??? Otherwise assume we've combined things such that we
12080 can now prove that the instructions can't trap. Drop the
12081 note in this case. */
12089 /* These notes must remain with the call. It should not be
12090 possible for both I2 and I3 to be a call. */
12091 if (GET_CODE (i3) == CALL_INSN)
12093 else if (i2 && GET_CODE (i2) == CALL_INSN)
12100 /* Any clobbers for i3 may still exist, and so we must process
12101 REG_UNUSED notes from that insn.
12103 Any clobbers from i2 or i1 can only exist if they were added by
12104 recog_for_combine. In that case, recog_for_combine created the
12105 necessary REG_UNUSED notes. Trying to keep any original
12106 REG_UNUSED notes from these insns can cause incorrect output
12107 if it is for the same register as the original i3 dest.
12108 In that case, we will notice that the register is set in i3,
12109 and then add a REG_UNUSED note for the destination of i3, which
12110 is wrong. However, it is possible to have REG_UNUSED notes from
12111 i2 or i1 for register which were both used and clobbered, so
12112 we keep notes from i2 or i1 if they will turn into REG_DEAD
12115 /* If this register is set or clobbered in I3, put the note there
12116 unless there is one already. */
12117 if (reg_set_p (XEXP (note, 0), PATTERN (i3)))
12119 if (from_insn != i3)
12122 if (! (GET_CODE (XEXP (note, 0)) == REG
12123 ? find_regno_note (i3, REG_UNUSED, REGNO (XEXP (note, 0)))
12124 : find_reg_note (i3, REG_UNUSED, XEXP (note, 0))))
12127 /* Otherwise, if this register is used by I3, then this register
12128 now dies here, so we must put a REG_DEAD note here unless there
12130 else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3))
12131 && ! (GET_CODE (XEXP (note, 0)) == REG
12132 ? find_regno_note (i3, REG_DEAD,
12133 REGNO (XEXP (note, 0)))
12134 : find_reg_note (i3, REG_DEAD, XEXP (note, 0))))
12136 PUT_REG_NOTE_KIND (note, REG_DEAD);
12144 /* These notes say something about results of an insn. We can
12145 only support them if they used to be on I3 in which case they
12146 remain on I3. Otherwise they are ignored.
12148 If the note refers to an expression that is not a constant, we
12149 must also ignore the note since we cannot tell whether the
12150 equivalence is still true. It might be possible to do
12151 slightly better than this (we only have a problem if I2DEST
12152 or I1DEST is present in the expression), but it doesn't
12153 seem worth the trouble. */
12155 if (from_insn == i3
12156 && (XEXP (note, 0) == 0 || CONSTANT_P (XEXP (note, 0))))
12161 case REG_NO_CONFLICT:
12162 /* These notes say something about how a register is used. They must
12163 be present on any use of the register in I2 or I3. */
12164 if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3)))
12167 if (i2 && reg_mentioned_p (XEXP (note, 0), PATTERN (i2)))
12177 /* This can show up in several ways -- either directly in the
12178 pattern, or hidden off in the constant pool with (or without?)
12179 a REG_EQUAL note. */
12180 /* ??? Ignore the without-reg_equal-note problem for now. */
12181 if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3))
12182 || ((tem = find_reg_note (i3, REG_EQUAL, NULL_RTX))
12183 && GET_CODE (XEXP (tem, 0)) == LABEL_REF
12184 && XEXP (XEXP (tem, 0), 0) == XEXP (note, 0)))
12188 && (reg_mentioned_p (XEXP (note, 0), PATTERN (i2))
12189 || ((tem = find_reg_note (i2, REG_EQUAL, NULL_RTX))
12190 && GET_CODE (XEXP (tem, 0)) == LABEL_REF
12191 && XEXP (XEXP (tem, 0), 0) == XEXP (note, 0))))
12199 /* Don't attach REG_LABEL note to a JUMP_INSN which has
12200 JUMP_LABEL already. Instead, decrement LABEL_NUSES. */
12201 if (place && GET_CODE (place) == JUMP_INSN && JUMP_LABEL (place))
12203 if (JUMP_LABEL (place) != XEXP (note, 0))
12205 if (GET_CODE (JUMP_LABEL (place)) == CODE_LABEL)
12206 LABEL_NUSES (JUMP_LABEL (place))--;
12209 if (place2 && GET_CODE (place2) == JUMP_INSN && JUMP_LABEL (place2))
12211 if (JUMP_LABEL (place2) != XEXP (note, 0))
12213 if (GET_CODE (JUMP_LABEL (place2)) == CODE_LABEL)
12214 LABEL_NUSES (JUMP_LABEL (place2))--;
12221 /* These notes say something about the value of a register prior
12222 to the execution of an insn. It is too much trouble to see
12223 if the note is still correct in all situations. It is better
12224 to simply delete it. */
12228 /* If the insn previously containing this note still exists,
12229 put it back where it was. Otherwise move it to the previous
12230 insn. Adjust the corresponding REG_LIBCALL note. */
12231 if (GET_CODE (from_insn) != NOTE)
12235 tem = find_reg_note (XEXP (note, 0), REG_LIBCALL, NULL_RTX);
12236 place = prev_real_insn (from_insn);
12238 XEXP (tem, 0) = place;
12239 /* If we're deleting the last remaining instruction of a
12240 libcall sequence, don't add the notes. */
12241 else if (XEXP (note, 0) == from_insn)
12247 /* This is handled similarly to REG_RETVAL. */
12248 if (GET_CODE (from_insn) != NOTE)
12252 tem = find_reg_note (XEXP (note, 0), REG_RETVAL, NULL_RTX);
12253 place = next_real_insn (from_insn);
12255 XEXP (tem, 0) = place;
12256 /* If we're deleting the last remaining instruction of a
12257 libcall sequence, don't add the notes. */
12258 else if (XEXP (note, 0) == from_insn)
12264 /* If the register is used as an input in I3, it dies there.
12265 Similarly for I2, if it is non-zero and adjacent to I3.
12267 If the register is not used as an input in either I3 or I2
12268 and it is not one of the registers we were supposed to eliminate,
12269 there are two possibilities. We might have a non-adjacent I2
12270 or we might have somehow eliminated an additional register
12271 from a computation. For example, we might have had A & B where
12272 we discover that B will always be zero. In this case we will
12273 eliminate the reference to A.
12275 In both cases, we must search to see if we can find a previous
12276 use of A and put the death note there. */
12279 && GET_CODE (from_insn) == CALL_INSN
12280 && find_reg_fusage (from_insn, USE, XEXP (note, 0)))
12282 else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3)))
12284 else if (i2 != 0 && next_nonnote_insn (i2) == i3
12285 && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
12288 if (rtx_equal_p (XEXP (note, 0), elim_i2)
12289 || rtx_equal_p (XEXP (note, 0), elim_i1))
12294 basic_block bb = BASIC_BLOCK (this_basic_block);
12296 for (tem = PREV_INSN (i3); place == 0; tem = PREV_INSN (tem))
12298 if (! INSN_P (tem))
12300 if (tem == bb->head)
12305 /* If the register is being set at TEM, see if that is all
12306 TEM is doing. If so, delete TEM. Otherwise, make this
12307 into a REG_UNUSED note instead. */
12308 if (reg_set_p (XEXP (note, 0), PATTERN (tem)))
12310 rtx set = single_set (tem);
12311 rtx inner_dest = 0;
12313 rtx cc0_setter = NULL_RTX;
12317 for (inner_dest = SET_DEST (set);
12318 (GET_CODE (inner_dest) == STRICT_LOW_PART
12319 || GET_CODE (inner_dest) == SUBREG
12320 || GET_CODE (inner_dest) == ZERO_EXTRACT);
12321 inner_dest = XEXP (inner_dest, 0))
12324 /* Verify that it was the set, and not a clobber that
12325 modified the register.
12327 CC0 targets must be careful to maintain setter/user
12328 pairs. If we cannot delete the setter due to side
12329 effects, mark the user with an UNUSED note instead
12332 if (set != 0 && ! side_effects_p (SET_SRC (set))
12333 && rtx_equal_p (XEXP (note, 0), inner_dest)
12335 && (! reg_mentioned_p (cc0_rtx, SET_SRC (set))
12336 || ((cc0_setter = prev_cc0_setter (tem)) != NULL
12337 && sets_cc0_p (PATTERN (cc0_setter)) > 0))
12341 /* Move the notes and links of TEM elsewhere.
12342 This might delete other dead insns recursively.
12343 First set the pattern to something that won't use
12346 PATTERN (tem) = pc_rtx;
12348 distribute_notes (REG_NOTES (tem), tem, tem,
12349 NULL_RTX, NULL_RTX, NULL_RTX);
12350 distribute_links (LOG_LINKS (tem));
12352 PUT_CODE (tem, NOTE);
12353 NOTE_LINE_NUMBER (tem) = NOTE_INSN_DELETED;
12354 NOTE_SOURCE_FILE (tem) = 0;
12357 /* Delete the setter too. */
12360 PATTERN (cc0_setter) = pc_rtx;
12362 distribute_notes (REG_NOTES (cc0_setter),
12363 cc0_setter, cc0_setter,
12364 NULL_RTX, NULL_RTX, NULL_RTX);
12365 distribute_links (LOG_LINKS (cc0_setter));
12367 PUT_CODE (cc0_setter, NOTE);
12368 NOTE_LINE_NUMBER (cc0_setter)
12369 = NOTE_INSN_DELETED;
12370 NOTE_SOURCE_FILE (cc0_setter) = 0;
12374 /* If the register is both set and used here, put the
12375 REG_DEAD note here, but place a REG_UNUSED note
12376 here too unless there already is one. */
12377 else if (reg_referenced_p (XEXP (note, 0),
12382 if (! find_regno_note (tem, REG_UNUSED,
12383 REGNO (XEXP (note, 0))))
12385 = gen_rtx_EXPR_LIST (REG_UNUSED, XEXP (note, 0),
12390 PUT_REG_NOTE_KIND (note, REG_UNUSED);
12392 /* If there isn't already a REG_UNUSED note, put one
12394 if (! find_regno_note (tem, REG_UNUSED,
12395 REGNO (XEXP (note, 0))))
12400 else if (reg_referenced_p (XEXP (note, 0), PATTERN (tem))
12401 || (GET_CODE (tem) == CALL_INSN
12402 && find_reg_fusage (tem, USE, XEXP (note, 0))))
12406 /* If we are doing a 3->2 combination, and we have a
12407 register which formerly died in i3 and was not used
12408 by i2, which now no longer dies in i3 and is used in
12409 i2 but does not die in i2, and place is between i2
12410 and i3, then we may need to move a link from place to
12412 if (i2 && INSN_UID (place) <= max_uid_cuid
12413 && INSN_CUID (place) > INSN_CUID (i2)
12415 && INSN_CUID (from_insn) > INSN_CUID (i2)
12416 && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
12418 rtx links = LOG_LINKS (place);
12419 LOG_LINKS (place) = 0;
12420 distribute_links (links);
12425 if (tem == bb->head)
12429 /* We haven't found an insn for the death note and it
12430 is still a REG_DEAD note, but we have hit the beginning
12431 of the block. If the existing life info says the reg
12432 was dead, there's nothing left to do. Otherwise, we'll
12433 need to do a global life update after combine. */
12434 if (REG_NOTE_KIND (note) == REG_DEAD && place == 0
12435 && REGNO_REG_SET_P (bb->global_live_at_start,
12436 REGNO (XEXP (note, 0))))
12438 SET_BIT (refresh_blocks, this_basic_block);
12443 /* If the register is set or already dead at PLACE, we needn't do
12444 anything with this note if it is still a REG_DEAD note.
12445 We can here if it is set at all, not if is it totally replace,
12446 which is what `dead_or_set_p' checks, so also check for it being
12449 if (place && REG_NOTE_KIND (note) == REG_DEAD)
12451 unsigned int regno = REGNO (XEXP (note, 0));
12453 /* Similarly, if the instruction on which we want to place
12454 the note is a noop, we'll need do a global live update
12455 after we remove them in delete_noop_moves. */
12456 if (noop_move_p (place))
12458 SET_BIT (refresh_blocks, this_basic_block);
12462 if (dead_or_set_p (place, XEXP (note, 0))
12463 || reg_bitfield_target_p (XEXP (note, 0), PATTERN (place)))
12465 /* Unless the register previously died in PLACE, clear
12466 reg_last_death. [I no longer understand why this is
12468 if (reg_last_death[regno] != place)
12469 reg_last_death[regno] = 0;
12473 reg_last_death[regno] = place;
12475 /* If this is a death note for a hard reg that is occupying
12476 multiple registers, ensure that we are still using all
12477 parts of the object. If we find a piece of the object
12478 that is unused, we must arrange for an appropriate REG_DEAD
12479 note to be added for it. However, we can't just emit a USE
12480 and tag the note to it, since the register might actually
12481 be dead; so we recourse, and the recursive call then finds
12482 the previous insn that used this register. */
12484 if (place && regno < FIRST_PSEUDO_REGISTER
12485 && HARD_REGNO_NREGS (regno, GET_MODE (XEXP (note, 0))) > 1)
12487 unsigned int endregno
12488 = regno + HARD_REGNO_NREGS (regno,
12489 GET_MODE (XEXP (note, 0)));
12493 for (i = regno; i < endregno; i++)
12494 if ((! refers_to_regno_p (i, i + 1, PATTERN (place), 0)
12495 && ! find_regno_fusage (place, USE, i))
12496 || dead_or_set_regno_p (place, i))
12501 /* Put only REG_DEAD notes for pieces that are
12502 not already dead or set. */
12504 for (i = regno; i < endregno;
12505 i += HARD_REGNO_NREGS (i, reg_raw_mode[i]))
12507 rtx piece = gen_rtx_REG (reg_raw_mode[i], i);
12508 basic_block bb = BASIC_BLOCK (this_basic_block);
12510 if (! dead_or_set_p (place, piece)
12511 && ! reg_bitfield_target_p (piece,
12515 = gen_rtx_EXPR_LIST (REG_DEAD, piece, NULL_RTX);
12517 distribute_notes (new_note, place, place,
12518 NULL_RTX, NULL_RTX, NULL_RTX);
12520 else if (! refers_to_regno_p (i, i + 1,
12521 PATTERN (place), 0)
12522 && ! find_regno_fusage (place, USE, i))
12523 for (tem = PREV_INSN (place); ;
12524 tem = PREV_INSN (tem))
12526 if (! INSN_P (tem))
12528 if (tem == bb->head)
12530 SET_BIT (refresh_blocks,
12537 if (dead_or_set_p (tem, piece)
12538 || reg_bitfield_target_p (piece,
12542 = gen_rtx_EXPR_LIST (REG_UNUSED, piece,
12557 /* Any other notes should not be present at this point in the
12564 XEXP (note, 1) = REG_NOTES (place);
12565 REG_NOTES (place) = note;
12567 else if ((REG_NOTE_KIND (note) == REG_DEAD
12568 || REG_NOTE_KIND (note) == REG_UNUSED)
12569 && GET_CODE (XEXP (note, 0)) == REG)
12570 REG_N_DEATHS (REGNO (XEXP (note, 0)))--;
12574 if ((REG_NOTE_KIND (note) == REG_DEAD
12575 || REG_NOTE_KIND (note) == REG_UNUSED)
12576 && GET_CODE (XEXP (note, 0)) == REG)
12577 REG_N_DEATHS (REGNO (XEXP (note, 0)))++;
12579 REG_NOTES (place2) = gen_rtx_fmt_ee (GET_CODE (note),
12580 REG_NOTE_KIND (note),
12582 REG_NOTES (place2));
12587 /* Similarly to above, distribute the LOG_LINKS that used to be present on
12588 I3, I2, and I1 to new locations. This is also called in one case to
12589 add a link pointing at I3 when I3's destination is changed. */
12592 distribute_links (links)
12595 rtx link, next_link;
12597 for (link = links; link; link = next_link)
12603 next_link = XEXP (link, 1);
12605 /* If the insn that this link points to is a NOTE or isn't a single
12606 set, ignore it. In the latter case, it isn't clear what we
12607 can do other than ignore the link, since we can't tell which
12608 register it was for. Such links wouldn't be used by combine
12611 It is not possible for the destination of the target of the link to
12612 have been changed by combine. The only potential of this is if we
12613 replace I3, I2, and I1 by I3 and I2. But in that case the
12614 destination of I2 also remains unchanged. */
12616 if (GET_CODE (XEXP (link, 0)) == NOTE
12617 || (set = single_set (XEXP (link, 0))) == 0)
12620 reg = SET_DEST (set);
12621 while (GET_CODE (reg) == SUBREG || GET_CODE (reg) == ZERO_EXTRACT
12622 || GET_CODE (reg) == SIGN_EXTRACT
12623 || GET_CODE (reg) == STRICT_LOW_PART)
12624 reg = XEXP (reg, 0);
12626 /* A LOG_LINK is defined as being placed on the first insn that uses
12627 a register and points to the insn that sets the register. Start
12628 searching at the next insn after the target of the link and stop
12629 when we reach a set of the register or the end of the basic block.
12631 Note that this correctly handles the link that used to point from
12632 I3 to I2. Also note that not much searching is typically done here
12633 since most links don't point very far away. */
12635 for (insn = NEXT_INSN (XEXP (link, 0));
12636 (insn && (this_basic_block == n_basic_blocks - 1
12637 || BLOCK_HEAD (this_basic_block + 1) != insn));
12638 insn = NEXT_INSN (insn))
12639 if (INSN_P (insn) && reg_overlap_mentioned_p (reg, PATTERN (insn)))
12641 if (reg_referenced_p (reg, PATTERN (insn)))
12645 else if (GET_CODE (insn) == CALL_INSN
12646 && find_reg_fusage (insn, USE, reg))
12652 /* If we found a place to put the link, place it there unless there
12653 is already a link to the same insn as LINK at that point. */
12659 for (link2 = LOG_LINKS (place); link2; link2 = XEXP (link2, 1))
12660 if (XEXP (link2, 0) == XEXP (link, 0))
12665 XEXP (link, 1) = LOG_LINKS (place);
12666 LOG_LINKS (place) = link;
12668 /* Set added_links_insn to the earliest insn we added a
12670 if (added_links_insn == 0
12671 || INSN_CUID (added_links_insn) > INSN_CUID (place))
12672 added_links_insn = place;
12678 /* Compute INSN_CUID for INSN, which is an insn made by combine. */
12684 while (insn != 0 && INSN_UID (insn) > max_uid_cuid
12685 && GET_CODE (insn) == INSN && GET_CODE (PATTERN (insn)) == USE)
12686 insn = NEXT_INSN (insn);
12688 if (INSN_UID (insn) > max_uid_cuid)
12691 return INSN_CUID (insn);
12695 dump_combine_stats (file)
12700 ";; Combiner statistics: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n\n",
12701 combine_attempts, combine_merges, combine_extras, combine_successes);
12705 dump_combine_total_stats (file)
12710 "\n;; Combiner totals: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n",
12711 total_attempts, total_merges, total_extras, total_successes);