1 /* Optimize by combining instructions for GNU compiler.
2 Copyright (C) 1987, 88, 92, 93, 94, 95, 1996 Free Software Foundation, Inc.
4 This file is part of GNU CC.
6 GNU CC is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2, or (at your option)
11 GNU CC is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GNU CC; see the file COPYING. If not, write to
18 the Free Software Foundation, 59 Temple Place - Suite 330,
19 Boston, MA 02111-1307, USA. */
22 /* This module is essentially the "combiner" phase of the U. of Arizona
23 Portable Optimizer, but redone to work on our list-structured
24 representation for RTL instead of their string representation.
26 The LOG_LINKS of each insn identify the most recent assignment
27 to each REG used in the insn. It is a list of previous insns,
28 each of which contains a SET for a REG that is used in this insn
29 and not used or set in between. LOG_LINKs never cross basic blocks.
30 They were set up by the preceding pass (lifetime analysis).
32 We try to combine each pair of insns joined by a logical link.
33 We also try to combine triples of insns A, B and C when
34 C has a link back to B and B has a link back to A.
36 LOG_LINKS does not have links for use of the CC0. They don't
37 need to, because the insn that sets the CC0 is always immediately
38 before the insn that tests it. So we always regard a branch
39 insn as having a logical link to the preceding insn. The same is true
40 for an insn explicitly using CC0.
42 We check (with use_crosses_set_p) to avoid combining in such a way
43 as to move a computation to a place where its value would be different.
45 Combination is done by mathematically substituting the previous
46 insn(s) values for the regs they set into the expressions in
47 the later insns that refer to these regs. If the result is a valid insn
48 for our target machine, according to the machine description,
49 we install it, delete the earlier insns, and update the data flow
50 information (LOG_LINKS and REG_NOTES) for what we did.
52 There are a few exceptions where the dataflow information created by
53 flow.c aren't completely updated:
55 - reg_live_length is not updated
56 - reg_n_refs is not adjusted in the rare case when a register is
57 no longer required in a computation
58 - there are extremely rare cases (see distribute_regnotes) when a
60 - a LOG_LINKS entry that refers to an insn with multiple SETs may be
61 removed because there is no way to know which register it was
64 To simplify substitution, we combine only when the earlier insn(s)
65 consist of only a single assignment. To simplify updating afterward,
66 we never combine when a subroutine call appears in the middle.
68 Since we do not represent assignments to CC0 explicitly except when that
69 is all an insn does, there is no LOG_LINKS entry in an insn that uses
70 the condition code for the insn that set the condition code.
71 Fortunately, these two insns must be consecutive.
72 Therefore, every JUMP_INSN is taken to have an implicit logical link
73 to the preceding insn. This is not quite right, since non-jumps can
74 also use the condition code; but in practice such insns would not
84 /* Must precede rtl.h for FFS. */
90 #include "hard-reg-set.h"
92 #include "basic-block.h"
93 #include "insn-config.h"
94 #include "insn-flags.h"
95 #include "insn-codes.h"
96 #include "insn-attr.h"
100 /* It is not safe to use ordinary gen_lowpart in combine.
101 Use gen_lowpart_for_combine instead. See comments there. */
102 #define gen_lowpart dont_use_gen_lowpart_you_dummy
104 /* Number of attempts to combine instructions in this function. */
106 static int combine_attempts;
108 /* Number of attempts that got as far as substitution in this function. */
110 static int combine_merges;
112 /* Number of instructions combined with added SETs in this function. */
114 static int combine_extras;
116 /* Number of instructions combined in this function. */
118 static int combine_successes;
120 /* Totals over entire compilation. */
122 static int total_attempts, total_merges, total_extras, total_successes;
124 /* Define a default value for REVERSIBLE_CC_MODE.
125 We can never assume that a condition code mode is safe to reverse unless
126 the md tells us so. */
127 #ifndef REVERSIBLE_CC_MODE
128 #define REVERSIBLE_CC_MODE(MODE) 0
131 /* Vector mapping INSN_UIDs to cuids.
132 The cuids are like uids but increase monotonically always.
133 Combine always uses cuids so that it can compare them.
134 But actually renumbering the uids, which we used to do,
135 proves to be a bad idea because it makes it hard to compare
136 the dumps produced by earlier passes with those from later passes. */
138 static int *uid_cuid;
139 static int max_uid_cuid;
141 /* Get the cuid of an insn. */
143 #define INSN_CUID(INSN) \
144 (INSN_UID (INSN) > max_uid_cuid ? insn_cuid (INSN) : uid_cuid[INSN_UID (INSN)])
146 /* Maximum register number, which is the size of the tables below. */
148 static int combine_max_regno;
150 /* Record last point of death of (hard or pseudo) register n. */
152 static rtx *reg_last_death;
154 /* Record last point of modification of (hard or pseudo) register n. */
156 static rtx *reg_last_set;
158 /* Record the cuid of the last insn that invalidated memory
159 (anything that writes memory, and subroutine calls, but not pushes). */
161 static int mem_last_set;
163 /* Record the cuid of the last CALL_INSN
164 so we can tell whether a potential combination crosses any calls. */
166 static int last_call_cuid;
168 /* When `subst' is called, this is the insn that is being modified
169 (by combining in a previous insn). The PATTERN of this insn
170 is still the old pattern partially modified and it should not be
171 looked at, but this may be used to examine the successors of the insn
172 to judge whether a simplification is valid. */
174 static rtx subst_insn;
176 /* This is an insn that belongs before subst_insn, but is not currently
177 on the insn chain. */
179 static rtx subst_prev_insn;
181 /* This is the lowest CUID that `subst' is currently dealing with.
182 get_last_value will not return a value if the register was set at or
183 after this CUID. If not for this mechanism, we could get confused if
184 I2 or I1 in try_combine were an insn that used the old value of a register
185 to obtain a new value. In that case, we might erroneously get the
186 new value of the register when we wanted the old one. */
188 static int subst_low_cuid;
190 /* This contains any hard registers that are used in newpat; reg_dead_at_p
191 must consider all these registers to be always live. */
193 static HARD_REG_SET newpat_used_regs;
195 /* This is an insn to which a LOG_LINKS entry has been added. If this
196 insn is the earlier than I2 or I3, combine should rescan starting at
199 static rtx added_links_insn;
201 /* Basic block number of the block in which we are performing combines. */
202 static int this_basic_block;
204 /* The next group of arrays allows the recording of the last value assigned
205 to (hard or pseudo) register n. We use this information to see if a
206 operation being processed is redundant given a prior operation performed
207 on the register. For example, an `and' with a constant is redundant if
208 all the zero bits are already known to be turned off.
210 We use an approach similar to that used by cse, but change it in the
213 (1) We do not want to reinitialize at each label.
214 (2) It is useful, but not critical, to know the actual value assigned
215 to a register. Often just its form is helpful.
217 Therefore, we maintain the following arrays:
219 reg_last_set_value the last value assigned
220 reg_last_set_label records the value of label_tick when the
221 register was assigned
222 reg_last_set_table_tick records the value of label_tick when a
223 value using the register is assigned
224 reg_last_set_invalid set to non-zero when it is not valid
225 to use the value of this register in some
228 To understand the usage of these tables, it is important to understand
229 the distinction between the value in reg_last_set_value being valid
230 and the register being validly contained in some other expression in the
233 Entry I in reg_last_set_value is valid if it is non-zero, and either
234 reg_n_sets[i] is 1 or reg_last_set_label[i] == label_tick.
236 Register I may validly appear in any expression returned for the value
237 of another register if reg_n_sets[i] is 1. It may also appear in the
238 value for register J if reg_last_set_label[i] < reg_last_set_label[j] or
239 reg_last_set_invalid[j] is zero.
241 If an expression is found in the table containing a register which may
242 not validly appear in an expression, the register is replaced by
243 something that won't match, (clobber (const_int 0)).
245 reg_last_set_invalid[i] is set non-zero when register I is being assigned
246 to and reg_last_set_table_tick[i] == label_tick. */
248 /* Record last value assigned to (hard or pseudo) register n. */
250 static rtx *reg_last_set_value;
252 /* Record the value of label_tick when the value for register n is placed in
253 reg_last_set_value[n]. */
255 static int *reg_last_set_label;
257 /* Record the value of label_tick when an expression involving register n
258 is placed in reg_last_set_value. */
260 static int *reg_last_set_table_tick;
262 /* Set non-zero if references to register n in expressions should not be
265 static char *reg_last_set_invalid;
267 /* Incremented for each label. */
269 static int label_tick;
271 /* Some registers that are set more than once and used in more than one
272 basic block are nevertheless always set in similar ways. For example,
273 a QImode register may be loaded from memory in two places on a machine
274 where byte loads zero extend.
276 We record in the following array what we know about the nonzero
277 bits of a register, specifically which bits are known to be zero.
279 If an entry is zero, it means that we don't know anything special. */
281 static unsigned HOST_WIDE_INT *reg_nonzero_bits;
283 /* Mode used to compute significance in reg_nonzero_bits. It is the largest
284 integer mode that can fit in HOST_BITS_PER_WIDE_INT. */
286 static enum machine_mode nonzero_bits_mode;
288 /* Nonzero if we know that a register has some leading bits that are always
289 equal to the sign bit. */
291 static char *reg_sign_bit_copies;
293 /* Nonzero when reg_nonzero_bits and reg_sign_bit_copies can be safely used.
294 It is zero while computing them and after combine has completed. This
295 former test prevents propagating values based on previously set values,
296 which can be incorrect if a variable is modified in a loop. */
298 static int nonzero_sign_valid;
300 /* These arrays are maintained in parallel with reg_last_set_value
301 and are used to store the mode in which the register was last set,
302 the bits that were known to be zero when it was last set, and the
303 number of sign bits copies it was known to have when it was last set. */
305 static enum machine_mode *reg_last_set_mode;
306 static unsigned HOST_WIDE_INT *reg_last_set_nonzero_bits;
307 static char *reg_last_set_sign_bit_copies;
309 /* Record one modification to rtl structure
310 to be undone by storing old_contents into *where.
311 is_int is 1 if the contents are an int. */
317 union {rtx r; int i;} old_contents;
318 union {rtx *r; int *i;} where;
321 /* Record a bunch of changes to be undone, up to MAX_UNDO of them.
322 num_undo says how many are currently recorded.
324 storage is nonzero if we must undo the allocation of new storage.
325 The value of storage is what to pass to obfree.
327 other_insn is nonzero if we have modified some other insn in the process
328 of working on subst_insn. It must be verified too.
330 previous_undos is the value of undobuf.undos when we started processing
331 this substitution. This will prevent gen_rtx_combine from re-used a piece
332 from the previous expression. Doing so can produce circular rtl
340 struct undo *previous_undos;
344 static struct undobuf undobuf;
346 /* Substitute NEWVAL, an rtx expression, into INTO, a place in some
347 insn. The substitution can be undone by undo_all. If INTO is already
348 set to NEWVAL, do not record this change. Because computing NEWVAL might
349 also call SUBST, we have to compute it before we put anything into
352 #define SUBST(INTO, NEWVAL) \
353 do { rtx _new = (NEWVAL); \
357 _buf = undobuf.frees, undobuf.frees = _buf->next; \
359 _buf = (struct undo *) xmalloc (sizeof (struct undo)); \
362 _buf->where.r = &INTO; \
363 _buf->old_contents.r = INTO; \
365 if (_buf->old_contents.r == INTO) \
366 _buf->next = undobuf.frees, undobuf.frees = _buf; \
368 _buf->next = undobuf.undos, undobuf.undos = _buf; \
371 /* Similar to SUBST, but NEWVAL is an int expression. Note that substitution
372 for the value of a HOST_WIDE_INT value (including CONST_INT) is
375 #define SUBST_INT(INTO, NEWVAL) \
376 do { struct undo *_buf; \
379 _buf = undobuf.frees, undobuf.frees = _buf->next; \
381 _buf = (struct undo *) xmalloc (sizeof (struct undo)); \
384 _buf->where.i = (int *) &INTO; \
385 _buf->old_contents.i = INTO; \
387 if (_buf->old_contents.i == INTO) \
388 _buf->next = undobuf.frees, undobuf.frees = _buf; \
390 _buf->next = undobuf.undos, undobuf.undos = _buf; \
393 /* Number of times the pseudo being substituted for
394 was found and replaced. */
396 static int n_occurrences;
398 static void init_reg_last_arrays PROTO((void));
399 static void setup_incoming_promotions PROTO((void));
400 static void set_nonzero_bits_and_sign_copies PROTO((rtx, rtx));
401 static int can_combine_p PROTO((rtx, rtx, rtx, rtx, rtx *, rtx *));
402 static int combinable_i3pat PROTO((rtx, rtx *, rtx, rtx, int, rtx *));
403 static rtx try_combine PROTO((rtx, rtx, rtx));
404 static void undo_all PROTO((void));
405 static rtx *find_split_point PROTO((rtx *, rtx));
406 static rtx subst PROTO((rtx, rtx, rtx, int, int));
407 static rtx simplify_rtx PROTO((rtx, enum machine_mode, int, int));
408 static rtx simplify_if_then_else PROTO((rtx));
409 static rtx simplify_set PROTO((rtx));
410 static rtx simplify_logical PROTO((rtx, int));
411 static rtx expand_compound_operation PROTO((rtx));
412 static rtx expand_field_assignment PROTO((rtx));
413 static rtx make_extraction PROTO((enum machine_mode, rtx, int, rtx, int,
415 static rtx extract_left_shift PROTO((rtx, int));
416 static rtx make_compound_operation PROTO((rtx, enum rtx_code));
417 static int get_pos_from_mask PROTO((unsigned HOST_WIDE_INT, int *));
418 static rtx force_to_mode PROTO((rtx, enum machine_mode,
419 unsigned HOST_WIDE_INT, rtx, int));
420 static rtx if_then_else_cond PROTO((rtx, rtx *, rtx *));
421 static rtx known_cond PROTO((rtx, enum rtx_code, rtx, rtx));
422 static int rtx_equal_for_field_assignment_p PROTO((rtx, rtx));
423 static rtx make_field_assignment PROTO((rtx));
424 static rtx apply_distributive_law PROTO((rtx));
425 static rtx simplify_and_const_int PROTO((rtx, enum machine_mode, rtx,
426 unsigned HOST_WIDE_INT));
427 static unsigned HOST_WIDE_INT nonzero_bits PROTO((rtx, enum machine_mode));
428 static int num_sign_bit_copies PROTO((rtx, enum machine_mode));
429 static int merge_outer_ops PROTO((enum rtx_code *, HOST_WIDE_INT *,
430 enum rtx_code, HOST_WIDE_INT,
431 enum machine_mode, int *));
432 static rtx simplify_shift_const PROTO((rtx, enum rtx_code, enum machine_mode,
434 static int recog_for_combine PROTO((rtx *, rtx, rtx *, int *));
435 static rtx gen_lowpart_for_combine PROTO((enum machine_mode, rtx));
436 static rtx gen_rtx_combine PVPROTO((enum rtx_code code, enum machine_mode mode,
438 static rtx gen_binary PROTO((enum rtx_code, enum machine_mode,
440 static rtx gen_unary PROTO((enum rtx_code, enum machine_mode,
441 enum machine_mode, rtx));
442 static enum rtx_code simplify_comparison PROTO((enum rtx_code, rtx *, rtx *));
443 static int reversible_comparison_p PROTO((rtx));
444 static void update_table_tick PROTO((rtx));
445 static void record_value_for_reg PROTO((rtx, rtx, rtx));
446 static void record_dead_and_set_regs_1 PROTO((rtx, rtx));
447 static void record_dead_and_set_regs PROTO((rtx));
448 static int get_last_value_validate PROTO((rtx *, int, int));
449 static rtx get_last_value PROTO((rtx));
450 static int use_crosses_set_p PROTO((rtx, int));
451 static void reg_dead_at_p_1 PROTO((rtx, rtx));
452 static int reg_dead_at_p PROTO((rtx, rtx));
453 static void move_deaths PROTO((rtx, rtx, int, rtx, rtx *));
454 static int reg_bitfield_target_p PROTO((rtx, rtx));
455 static void distribute_notes PROTO((rtx, rtx, rtx, rtx, rtx, rtx));
456 static void distribute_links PROTO((rtx));
457 static void mark_used_regs_combine PROTO((rtx));
458 static int insn_cuid PROTO((rtx));
460 /* Main entry point for combiner. F is the first insn of the function.
461 NREGS is the first unused pseudo-reg number. */
464 combine_instructions (f, nregs)
468 register rtx insn, next, prev;
470 register rtx links, nextlinks;
472 combine_attempts = 0;
475 combine_successes = 0;
476 undobuf.undos = undobuf.previous_undos = 0;
478 combine_max_regno = nregs;
481 = (unsigned HOST_WIDE_INT *) alloca (nregs * sizeof (HOST_WIDE_INT));
482 reg_sign_bit_copies = (char *) alloca (nregs * sizeof (char));
484 bzero ((char *) reg_nonzero_bits, nregs * sizeof (HOST_WIDE_INT));
485 bzero (reg_sign_bit_copies, nregs * sizeof (char));
487 reg_last_death = (rtx *) alloca (nregs * sizeof (rtx));
488 reg_last_set = (rtx *) alloca (nregs * sizeof (rtx));
489 reg_last_set_value = (rtx *) alloca (nregs * sizeof (rtx));
490 reg_last_set_table_tick = (int *) alloca (nregs * sizeof (int));
491 reg_last_set_label = (int *) alloca (nregs * sizeof (int));
492 reg_last_set_invalid = (char *) alloca (nregs * sizeof (char));
494 = (enum machine_mode *) alloca (nregs * sizeof (enum machine_mode));
495 reg_last_set_nonzero_bits
496 = (unsigned HOST_WIDE_INT *) alloca (nregs * sizeof (HOST_WIDE_INT));
497 reg_last_set_sign_bit_copies
498 = (char *) alloca (nregs * sizeof (char));
500 init_reg_last_arrays ();
502 init_recog_no_volatile ();
504 /* Compute maximum uid value so uid_cuid can be allocated. */
506 for (insn = f, i = 0; insn; insn = NEXT_INSN (insn))
507 if (INSN_UID (insn) > i)
510 uid_cuid = (int *) alloca ((i + 1) * sizeof (int));
513 nonzero_bits_mode = mode_for_size (HOST_BITS_PER_WIDE_INT, MODE_INT, 0);
515 /* Don't use reg_nonzero_bits when computing it. This can cause problems
516 when, for example, we have j <<= 1 in a loop. */
518 nonzero_sign_valid = 0;
520 /* Compute the mapping from uids to cuids.
521 Cuids are numbers assigned to insns, like uids,
522 except that cuids increase monotonically through the code.
524 Scan all SETs and see if we can deduce anything about what
525 bits are known to be zero for some registers and how many copies
526 of the sign bit are known to exist for those registers.
528 Also set any known values so that we can use it while searching
529 for what bits are known to be set. */
533 /* We need to initialize it here, because record_dead_and_set_regs may call
535 subst_prev_insn = NULL_RTX;
537 setup_incoming_promotions ();
539 for (insn = f, i = 0; insn; insn = NEXT_INSN (insn))
541 uid_cuid[INSN_UID (insn)] = ++i;
545 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i')
547 note_stores (PATTERN (insn), set_nonzero_bits_and_sign_copies);
548 record_dead_and_set_regs (insn);
551 for (links = REG_NOTES (insn); links; links = XEXP (links, 1))
552 if (REG_NOTE_KIND (links) == REG_INC)
553 set_nonzero_bits_and_sign_copies (XEXP (links, 0), NULL_RTX);
557 if (GET_CODE (insn) == CODE_LABEL)
561 nonzero_sign_valid = 1;
563 /* Now scan all the insns in forward order. */
565 this_basic_block = -1;
569 init_reg_last_arrays ();
570 setup_incoming_promotions ();
572 for (insn = f; insn; insn = next ? next : NEXT_INSN (insn))
576 /* If INSN starts a new basic block, update our basic block number. */
577 if (this_basic_block + 1 < n_basic_blocks
578 && basic_block_head[this_basic_block + 1] == insn)
581 if (GET_CODE (insn) == CODE_LABEL)
584 else if (GET_RTX_CLASS (GET_CODE (insn)) == 'i')
586 /* Try this insn with each insn it links back to. */
588 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
589 if ((next = try_combine (insn, XEXP (links, 0), NULL_RTX)) != 0)
592 /* Try each sequence of three linked insns ending with this one. */
594 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
595 for (nextlinks = LOG_LINKS (XEXP (links, 0)); nextlinks;
596 nextlinks = XEXP (nextlinks, 1))
597 if ((next = try_combine (insn, XEXP (links, 0),
598 XEXP (nextlinks, 0))) != 0)
602 /* Try to combine a jump insn that uses CC0
603 with a preceding insn that sets CC0, and maybe with its
604 logical predecessor as well.
605 This is how we make decrement-and-branch insns.
606 We need this special code because data flow connections
607 via CC0 do not get entered in LOG_LINKS. */
609 if (GET_CODE (insn) == JUMP_INSN
610 && (prev = prev_nonnote_insn (insn)) != 0
611 && GET_CODE (prev) == INSN
612 && sets_cc0_p (PATTERN (prev)))
614 if ((next = try_combine (insn, prev, NULL_RTX)) != 0)
617 for (nextlinks = LOG_LINKS (prev); nextlinks;
618 nextlinks = XEXP (nextlinks, 1))
619 if ((next = try_combine (insn, prev,
620 XEXP (nextlinks, 0))) != 0)
624 /* Do the same for an insn that explicitly references CC0. */
625 if (GET_CODE (insn) == INSN
626 && (prev = prev_nonnote_insn (insn)) != 0
627 && GET_CODE (prev) == INSN
628 && sets_cc0_p (PATTERN (prev))
629 && GET_CODE (PATTERN (insn)) == SET
630 && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (insn))))
632 if ((next = try_combine (insn, prev, NULL_RTX)) != 0)
635 for (nextlinks = LOG_LINKS (prev); nextlinks;
636 nextlinks = XEXP (nextlinks, 1))
637 if ((next = try_combine (insn, prev,
638 XEXP (nextlinks, 0))) != 0)
642 /* Finally, see if any of the insns that this insn links to
643 explicitly references CC0. If so, try this insn, that insn,
644 and its predecessor if it sets CC0. */
645 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
646 if (GET_CODE (XEXP (links, 0)) == INSN
647 && GET_CODE (PATTERN (XEXP (links, 0))) == SET
648 && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (XEXP (links, 0))))
649 && (prev = prev_nonnote_insn (XEXP (links, 0))) != 0
650 && GET_CODE (prev) == INSN
651 && sets_cc0_p (PATTERN (prev))
652 && (next = try_combine (insn, XEXP (links, 0), prev)) != 0)
656 /* Try combining an insn with two different insns whose results it
658 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
659 for (nextlinks = XEXP (links, 1); nextlinks;
660 nextlinks = XEXP (nextlinks, 1))
661 if ((next = try_combine (insn, XEXP (links, 0),
662 XEXP (nextlinks, 0))) != 0)
665 if (GET_CODE (insn) != NOTE)
666 record_dead_and_set_regs (insn);
673 total_attempts += combine_attempts;
674 total_merges += combine_merges;
675 total_extras += combine_extras;
676 total_successes += combine_successes;
678 nonzero_sign_valid = 0;
681 /* Wipe the reg_last_xxx arrays in preparation for another pass. */
684 init_reg_last_arrays ()
686 int nregs = combine_max_regno;
688 bzero ((char *) reg_last_death, nregs * sizeof (rtx));
689 bzero ((char *) reg_last_set, nregs * sizeof (rtx));
690 bzero ((char *) reg_last_set_value, nregs * sizeof (rtx));
691 bzero ((char *) reg_last_set_table_tick, nregs * sizeof (int));
692 bzero ((char *) reg_last_set_label, nregs * sizeof (int));
693 bzero (reg_last_set_invalid, nregs * sizeof (char));
694 bzero ((char *) reg_last_set_mode, nregs * sizeof (enum machine_mode));
695 bzero ((char *) reg_last_set_nonzero_bits, nregs * sizeof (HOST_WIDE_INT));
696 bzero (reg_last_set_sign_bit_copies, nregs * sizeof (char));
699 /* Set up any promoted values for incoming argument registers. */
702 setup_incoming_promotions ()
704 #ifdef PROMOTE_FUNCTION_ARGS
707 enum machine_mode mode;
709 rtx first = get_insns ();
711 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
712 if (FUNCTION_ARG_REGNO_P (regno)
713 && (reg = promoted_input_arg (regno, &mode, &unsignedp)) != 0)
714 record_value_for_reg (reg, first,
715 gen_rtx (unsignedp ? ZERO_EXTEND : SIGN_EXTEND,
717 gen_rtx (CLOBBER, mode, const0_rtx)));
721 /* Called via note_stores. If X is a pseudo that is narrower than
722 HOST_BITS_PER_WIDE_INT and is being set, record what bits are known zero.
724 If we are setting only a portion of X and we can't figure out what
725 portion, assume all bits will be used since we don't know what will
728 Similarly, set how many bits of X are known to be copies of the sign bit
729 at all locations in the function. This is the smallest number implied
733 set_nonzero_bits_and_sign_copies (x, set)
739 if (GET_CODE (x) == REG
740 && REGNO (x) >= FIRST_PSEUDO_REGISTER
741 /* If this register is undefined at the start of the file, we can't
742 say what its contents were. */
743 && ! (basic_block_live_at_start[0][REGNO (x) / REGSET_ELT_BITS]
744 & ((REGSET_ELT_TYPE) 1 << (REGNO (x) % REGSET_ELT_BITS)))
745 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT)
747 if (set == 0 || GET_CODE (set) == CLOBBER)
749 reg_nonzero_bits[REGNO (x)] = GET_MODE_MASK (GET_MODE (x));
750 reg_sign_bit_copies[REGNO (x)] = 1;
754 /* If this is a complex assignment, see if we can convert it into a
755 simple assignment. */
756 set = expand_field_assignment (set);
758 /* If this is a simple assignment, or we have a paradoxical SUBREG,
759 set what we know about X. */
761 if (SET_DEST (set) == x
762 || (GET_CODE (SET_DEST (set)) == SUBREG
763 && (GET_MODE_SIZE (GET_MODE (SET_DEST (set)))
764 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (set)))))
765 && SUBREG_REG (SET_DEST (set)) == x))
767 rtx src = SET_SRC (set);
769 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
770 /* If X is narrower than a word and SRC is a non-negative
771 constant that would appear negative in the mode of X,
772 sign-extend it for use in reg_nonzero_bits because some
773 machines (maybe most) will actually do the sign-extension
774 and this is the conservative approach.
776 ??? For 2.5, try to tighten up the MD files in this regard
777 instead of this kludge. */
779 if (GET_MODE_BITSIZE (GET_MODE (x)) < BITS_PER_WORD
780 && GET_CODE (src) == CONST_INT
782 && 0 != (INTVAL (src)
784 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
785 src = GEN_INT (INTVAL (src)
786 | ((HOST_WIDE_INT) (-1)
787 << GET_MODE_BITSIZE (GET_MODE (x))));
790 reg_nonzero_bits[REGNO (x)]
791 |= nonzero_bits (src, nonzero_bits_mode);
792 num = num_sign_bit_copies (SET_SRC (set), GET_MODE (x));
793 if (reg_sign_bit_copies[REGNO (x)] == 0
794 || reg_sign_bit_copies[REGNO (x)] > num)
795 reg_sign_bit_copies[REGNO (x)] = num;
799 reg_nonzero_bits[REGNO (x)] = GET_MODE_MASK (GET_MODE (x));
800 reg_sign_bit_copies[REGNO (x)] = 1;
805 /* See if INSN can be combined into I3. PRED and SUCC are optionally
806 insns that were previously combined into I3 or that will be combined
807 into the merger of INSN and I3.
809 Return 0 if the combination is not allowed for any reason.
811 If the combination is allowed, *PDEST will be set to the single
812 destination of INSN and *PSRC to the single source, and this function
816 can_combine_p (insn, i3, pred, succ, pdest, psrc)
823 rtx set = 0, src, dest;
825 int all_adjacent = (succ ? (next_active_insn (insn) == succ
826 && next_active_insn (succ) == i3)
827 : next_active_insn (insn) == i3);
829 /* Can combine only if previous insn is a SET of a REG, a SUBREG or CC0.
830 or a PARALLEL consisting of such a SET and CLOBBERs.
832 If INSN has CLOBBER parallel parts, ignore them for our processing.
833 By definition, these happen during the execution of the insn. When it
834 is merged with another insn, all bets are off. If they are, in fact,
835 needed and aren't also supplied in I3, they may be added by
836 recog_for_combine. Otherwise, it won't match.
838 We can also ignore a SET whose SET_DEST is mentioned in a REG_UNUSED
841 Get the source and destination of INSN. If more than one, can't
844 if (GET_CODE (PATTERN (insn)) == SET)
845 set = PATTERN (insn);
846 else if (GET_CODE (PATTERN (insn)) == PARALLEL
847 && GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == SET)
849 for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
851 rtx elt = XVECEXP (PATTERN (insn), 0, i);
853 switch (GET_CODE (elt))
855 /* We can ignore CLOBBERs. */
860 /* Ignore SETs whose result isn't used but not those that
861 have side-effects. */
862 if (find_reg_note (insn, REG_UNUSED, SET_DEST (elt))
863 && ! side_effects_p (elt))
866 /* If we have already found a SET, this is a second one and
867 so we cannot combine with this insn. */
875 /* Anything else means we can't combine. */
881 /* If SET_SRC is an ASM_OPERANDS we can't throw away these CLOBBERs,
882 so don't do anything with it. */
883 || GET_CODE (SET_SRC (set)) == ASM_OPERANDS)
892 set = expand_field_assignment (set);
893 src = SET_SRC (set), dest = SET_DEST (set);
895 /* Don't eliminate a store in the stack pointer. */
896 if (dest == stack_pointer_rtx
897 /* If we couldn't eliminate a field assignment, we can't combine. */
898 || GET_CODE (dest) == ZERO_EXTRACT || GET_CODE (dest) == STRICT_LOW_PART
899 /* Don't combine with an insn that sets a register to itself if it has
900 a REG_EQUAL note. This may be part of a REG_NO_CONFLICT sequence. */
901 || (rtx_equal_p (src, dest) && find_reg_note (insn, REG_EQUAL, NULL_RTX))
902 /* Can't merge a function call. */
903 || GET_CODE (src) == CALL
904 /* Don't eliminate a function call argument. */
905 || (GET_CODE (i3) == CALL_INSN
906 && (find_reg_fusage (i3, USE, dest)
907 || (GET_CODE (dest) == REG
908 && REGNO (dest) < FIRST_PSEUDO_REGISTER
909 && global_regs[REGNO (dest)])))
910 /* Don't substitute into an incremented register. */
911 || FIND_REG_INC_NOTE (i3, dest)
912 || (succ && FIND_REG_INC_NOTE (succ, dest))
913 /* Don't combine the end of a libcall into anything. */
914 || find_reg_note (insn, REG_RETVAL, NULL_RTX)
915 /* Make sure that DEST is not used after SUCC but before I3. */
916 || (succ && ! all_adjacent
917 && reg_used_between_p (dest, succ, i3))
918 /* Make sure that the value that is to be substituted for the register
919 does not use any registers whose values alter in between. However,
920 If the insns are adjacent, a use can't cross a set even though we
921 think it might (this can happen for a sequence of insns each setting
922 the same destination; reg_last_set of that register might point to
923 a NOTE). If INSN has a REG_EQUIV note, the register is always
924 equivalent to the memory so the substitution is valid even if there
925 are intervening stores. Also, don't move a volatile asm or
926 UNSPEC_VOLATILE across any other insns. */
928 && (((GET_CODE (src) != MEM
929 || ! find_reg_note (insn, REG_EQUIV, src))
930 && use_crosses_set_p (src, INSN_CUID (insn)))
931 || (GET_CODE (src) == ASM_OPERANDS && MEM_VOLATILE_P (src))
932 || GET_CODE (src) == UNSPEC_VOLATILE))
933 /* If there is a REG_NO_CONFLICT note for DEST in I3 or SUCC, we get
934 better register allocation by not doing the combine. */
935 || find_reg_note (i3, REG_NO_CONFLICT, dest)
936 || (succ && find_reg_note (succ, REG_NO_CONFLICT, dest))
937 /* Don't combine across a CALL_INSN, because that would possibly
938 change whether the life span of some REGs crosses calls or not,
939 and it is a pain to update that information.
940 Exception: if source is a constant, moving it later can't hurt.
941 Accept that special case, because it helps -fforce-addr a lot. */
942 || (INSN_CUID (insn) < last_call_cuid && ! CONSTANT_P (src)))
945 /* DEST must either be a REG or CC0. */
946 if (GET_CODE (dest) == REG)
948 /* If register alignment is being enforced for multi-word items in all
949 cases except for parameters, it is possible to have a register copy
950 insn referencing a hard register that is not allowed to contain the
951 mode being copied and which would not be valid as an operand of most
952 insns. Eliminate this problem by not combining with such an insn.
954 Also, on some machines we don't want to extend the life of a hard
957 if (GET_CODE (src) == REG
958 && ((REGNO (dest) < FIRST_PSEUDO_REGISTER
959 && ! HARD_REGNO_MODE_OK (REGNO (dest), GET_MODE (dest)))
960 /* Don't extend the life of a hard register unless it is
961 user variable (if we have few registers) or it can't
962 fit into the desired register (meaning something special
964 Also avoid substituting a return register into I3, because
965 reload can't handle a conflict with constraints of other
967 || (REGNO (src) < FIRST_PSEUDO_REGISTER
968 && (! HARD_REGNO_MODE_OK (REGNO (src), GET_MODE (src))
969 #ifdef SMALL_REGISTER_CLASSES
970 || (! all_adjacent && ! REG_USERVAR_P (src))
971 || (FUNCTION_VALUE_REGNO_P (REGNO (src))
972 && ! REG_USERVAR_P (src))
977 else if (GET_CODE (dest) != CC0)
980 /* Don't substitute for a register intended as a clobberable operand.
981 Similarly, don't substitute an expression containing a register that
982 will be clobbered in I3. */
983 if (GET_CODE (PATTERN (i3)) == PARALLEL)
984 for (i = XVECLEN (PATTERN (i3), 0) - 1; i >= 0; i--)
985 if (GET_CODE (XVECEXP (PATTERN (i3), 0, i)) == CLOBBER
986 && (reg_overlap_mentioned_p (XEXP (XVECEXP (PATTERN (i3), 0, i), 0),
988 || rtx_equal_p (XEXP (XVECEXP (PATTERN (i3), 0, i), 0), dest)))
991 /* If INSN contains anything volatile, or is an `asm' (whether volatile
992 or not), reject, unless nothing volatile comes between it and I3,
993 with the exception of SUCC. */
995 if (GET_CODE (src) == ASM_OPERANDS || volatile_refs_p (src))
996 for (p = NEXT_INSN (insn); p != i3; p = NEXT_INSN (p))
997 if (GET_RTX_CLASS (GET_CODE (p)) == 'i'
998 && p != succ && volatile_refs_p (PATTERN (p)))
1001 /* If there are any volatile insns between INSN and I3, reject, because
1002 they might affect machine state. */
1004 for (p = NEXT_INSN (insn); p != i3; p = NEXT_INSN (p))
1005 if (GET_RTX_CLASS (GET_CODE (p)) == 'i'
1006 && p != succ && volatile_insn_p (PATTERN (p)))
1009 /* If INSN or I2 contains an autoincrement or autodecrement,
1010 make sure that register is not used between there and I3,
1011 and not already used in I3 either.
1012 Also insist that I3 not be a jump; if it were one
1013 and the incremented register were spilled, we would lose. */
1016 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
1017 if (REG_NOTE_KIND (link) == REG_INC
1018 && (GET_CODE (i3) == JUMP_INSN
1019 || reg_used_between_p (XEXP (link, 0), insn, i3)
1020 || reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i3))))
1025 /* Don't combine an insn that follows a CC0-setting insn.
1026 An insn that uses CC0 must not be separated from the one that sets it.
1027 We do, however, allow I2 to follow a CC0-setting insn if that insn
1028 is passed as I1; in that case it will be deleted also.
1029 We also allow combining in this case if all the insns are adjacent
1030 because that would leave the two CC0 insns adjacent as well.
1031 It would be more logical to test whether CC0 occurs inside I1 or I2,
1032 but that would be much slower, and this ought to be equivalent. */
1034 p = prev_nonnote_insn (insn);
1035 if (p && p != pred && GET_CODE (p) == INSN && sets_cc0_p (PATTERN (p))
1040 /* If we get here, we have passed all the tests and the combination is
1049 /* LOC is the location within I3 that contains its pattern or the component
1050 of a PARALLEL of the pattern. We validate that it is valid for combining.
1052 One problem is if I3 modifies its output, as opposed to replacing it
1053 entirely, we can't allow the output to contain I2DEST or I1DEST as doing
1054 so would produce an insn that is not equivalent to the original insns.
1058 (set (reg:DI 101) (reg:DI 100))
1059 (set (subreg:SI (reg:DI 101) 0) <foo>)
1061 This is NOT equivalent to:
1063 (parallel [(set (subreg:SI (reg:DI 100) 0) <foo>)
1064 (set (reg:DI 101) (reg:DI 100))])
1066 Not only does this modify 100 (in which case it might still be valid
1067 if 100 were dead in I2), it sets 101 to the ORIGINAL value of 100.
1069 We can also run into a problem if I2 sets a register that I1
1070 uses and I1 gets directly substituted into I3 (not via I2). In that
1071 case, we would be getting the wrong value of I2DEST into I3, so we
1072 must reject the combination. This case occurs when I2 and I1 both
1073 feed into I3, rather than when I1 feeds into I2, which feeds into I3.
1074 If I1_NOT_IN_SRC is non-zero, it means that finding I1 in the source
1075 of a SET must prevent combination from occurring.
1077 On machines where SMALL_REGISTER_CLASSES is defined, we don't combine
1078 if the destination of a SET is a hard register that isn't a user
1081 Before doing the above check, we first try to expand a field assignment
1082 into a set of logical operations.
1084 If PI3_DEST_KILLED is non-zero, it is a pointer to a location in which
1085 we place a register that is both set and used within I3. If more than one
1086 such register is detected, we fail.
1088 Return 1 if the combination is valid, zero otherwise. */
1091 combinable_i3pat (i3, loc, i2dest, i1dest, i1_not_in_src, pi3dest_killed)
1097 rtx *pi3dest_killed;
1101 if (GET_CODE (x) == SET)
1103 rtx set = expand_field_assignment (x);
1104 rtx dest = SET_DEST (set);
1105 rtx src = SET_SRC (set);
1106 rtx inner_dest = dest, inner_src = src;
1110 while (GET_CODE (inner_dest) == STRICT_LOW_PART
1111 || GET_CODE (inner_dest) == SUBREG
1112 || GET_CODE (inner_dest) == ZERO_EXTRACT)
1113 inner_dest = XEXP (inner_dest, 0);
1115 /* We probably don't need this any more now that LIMIT_RELOAD_CLASS
1118 while (GET_CODE (inner_src) == STRICT_LOW_PART
1119 || GET_CODE (inner_src) == SUBREG
1120 || GET_CODE (inner_src) == ZERO_EXTRACT)
1121 inner_src = XEXP (inner_src, 0);
1123 /* If it is better that two different modes keep two different pseudos,
1124 avoid combining them. This avoids producing the following pattern
1126 (set (subreg:SI (reg/v:QI 21) 0)
1127 (lshiftrt:SI (reg/v:SI 20)
1129 If that were made, reload could not handle the pair of
1130 reg 20/21, since it would try to get any GENERAL_REGS
1131 but some of them don't handle QImode. */
1133 if (rtx_equal_p (inner_src, i2dest)
1134 && GET_CODE (inner_dest) == REG
1135 && ! MODES_TIEABLE_P (GET_MODE (i2dest), GET_MODE (inner_dest)))
1139 /* Check for the case where I3 modifies its output, as
1141 if ((inner_dest != dest
1142 && (reg_overlap_mentioned_p (i2dest, inner_dest)
1143 || (i1dest && reg_overlap_mentioned_p (i1dest, inner_dest))))
1144 /* This is the same test done in can_combine_p except that we
1145 allow a hard register with SMALL_REGISTER_CLASSES if SRC is a
1147 Moreover, we can't test all_adjacent; we don't have to, since
1148 this instruction will stay in place, thus we are not considering
1149 to increase the lifetime of INNER_DEST. */
1150 || (GET_CODE (inner_dest) == REG
1151 && REGNO (inner_dest) < FIRST_PSEUDO_REGISTER
1152 && (! HARD_REGNO_MODE_OK (REGNO (inner_dest),
1153 GET_MODE (inner_dest))
1154 #ifdef SMALL_REGISTER_CLASSES
1155 || (GET_CODE (src) != CALL && ! REG_USERVAR_P (inner_dest)
1156 && FUNCTION_VALUE_REGNO_P (REGNO (inner_dest)))
1159 || (i1_not_in_src && reg_overlap_mentioned_p (i1dest, src)))
1162 /* If DEST is used in I3, it is being killed in this insn,
1163 so record that for later.
1164 Never add REG_DEAD notes for the FRAME_POINTER_REGNUM or the
1165 STACK_POINTER_REGNUM, since these are always considered to be
1166 live. Similarly for ARG_POINTER_REGNUM if it is fixed. */
1167 if (pi3dest_killed && GET_CODE (dest) == REG
1168 && reg_referenced_p (dest, PATTERN (i3))
1169 && REGNO (dest) != FRAME_POINTER_REGNUM
1170 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
1171 && REGNO (dest) != HARD_FRAME_POINTER_REGNUM
1173 #if ARG_POINTER_REGNUM != FRAME_POINTER_REGNUM
1174 && (REGNO (dest) != ARG_POINTER_REGNUM
1175 || ! fixed_regs [REGNO (dest)])
1177 && REGNO (dest) != STACK_POINTER_REGNUM)
1179 if (*pi3dest_killed)
1182 *pi3dest_killed = dest;
1186 else if (GET_CODE (x) == PARALLEL)
1190 for (i = 0; i < XVECLEN (x, 0); i++)
1191 if (! combinable_i3pat (i3, &XVECEXP (x, 0, i), i2dest, i1dest,
1192 i1_not_in_src, pi3dest_killed))
1199 /* Try to combine the insns I1 and I2 into I3.
1200 Here I1 and I2 appear earlier than I3.
1201 I1 can be zero; then we combine just I2 into I3.
1203 It we are combining three insns and the resulting insn is not recognized,
1204 try splitting it into two insns. If that happens, I2 and I3 are retained
1205 and I1 is pseudo-deleted by turning it into a NOTE. Otherwise, I1 and I2
1208 Return 0 if the combination does not work. Then nothing is changed.
1209 If we did the combination, return the insn at which combine should
1213 try_combine (i3, i2, i1)
1214 register rtx i3, i2, i1;
1216 /* New patterns for I3 and I3, respectively. */
1217 rtx newpat, newi2pat = 0;
1218 /* Indicates need to preserve SET in I1 or I2 in I3 if it is not dead. */
1219 int added_sets_1, added_sets_2;
1220 /* Total number of SETs to put into I3. */
1222 /* Nonzero is I2's body now appears in I3. */
1224 /* INSN_CODEs for new I3, new I2, and user of condition code. */
1225 int insn_code_number, i2_code_number, other_code_number;
1226 /* Contains I3 if the destination of I3 is used in its source, which means
1227 that the old life of I3 is being killed. If that usage is placed into
1228 I2 and not in I3, a REG_DEAD note must be made. */
1229 rtx i3dest_killed = 0;
1230 /* SET_DEST and SET_SRC of I2 and I1. */
1231 rtx i2dest, i2src, i1dest = 0, i1src = 0;
1232 /* PATTERN (I2), or a copy of it in certain cases. */
1234 /* Indicates if I2DEST or I1DEST is in I2SRC or I1_SRC. */
1235 int i2dest_in_i2src = 0, i1dest_in_i1src = 0, i2dest_in_i1src = 0;
1236 int i1_feeds_i3 = 0;
1237 /* Notes that must be added to REG_NOTES in I3 and I2. */
1238 rtx new_i3_notes, new_i2_notes;
1239 /* Notes that we substituted I3 into I2 instead of the normal case. */
1240 int i3_subst_into_i2 = 0;
1241 /* Notes that I1, I2 or I3 is a MULT operation. */
1243 /* Number of clobbers of SCRATCH we had to add. */
1244 int i3_scratches = 0, i2_scratches = 0, other_scratches = 0;
1251 /* If any of I1, I2, and I3 isn't really an insn, we can't do anything.
1252 This can occur when flow deletes an insn that it has merged into an
1253 auto-increment address. We also can't do anything if I3 has a
1254 REG_LIBCALL note since we don't want to disrupt the contiguity of a
1257 if (GET_RTX_CLASS (GET_CODE (i3)) != 'i'
1258 || GET_RTX_CLASS (GET_CODE (i2)) != 'i'
1259 || (i1 && GET_RTX_CLASS (GET_CODE (i1)) != 'i')
1260 || find_reg_note (i3, REG_LIBCALL, NULL_RTX))
1265 undobuf.undos = undobuf.previous_undos = 0;
1266 undobuf.other_insn = 0;
1268 /* Save the current high-water-mark so we can free storage if we didn't
1269 accept this combination. */
1270 undobuf.storage = (char *) oballoc (0);
1272 /* Reset the hard register usage information. */
1273 CLEAR_HARD_REG_SET (newpat_used_regs);
1275 /* If I1 and I2 both feed I3, they can be in any order. To simplify the
1276 code below, set I1 to be the earlier of the two insns. */
1277 if (i1 && INSN_CUID (i1) > INSN_CUID (i2))
1278 temp = i1, i1 = i2, i2 = temp;
1280 added_links_insn = 0;
1282 /* First check for one important special-case that the code below will
1283 not handle. Namely, the case where I1 is zero, I2 has multiple sets,
1284 and I3 is a SET whose SET_SRC is a SET_DEST in I2. In that case,
1285 we may be able to replace that destination with the destination of I3.
1286 This occurs in the common code where we compute both a quotient and
1287 remainder into a structure, in which case we want to do the computation
1288 directly into the structure to avoid register-register copies.
1290 We make very conservative checks below and only try to handle the
1291 most common cases of this. For example, we only handle the case
1292 where I2 and I3 are adjacent to avoid making difficult register
1295 if (i1 == 0 && GET_CODE (i3) == INSN && GET_CODE (PATTERN (i3)) == SET
1296 && GET_CODE (SET_SRC (PATTERN (i3))) == REG
1297 && REGNO (SET_SRC (PATTERN (i3))) >= FIRST_PSEUDO_REGISTER
1298 #ifdef SMALL_REGISTER_CLASSES
1299 && (GET_CODE (SET_DEST (PATTERN (i3))) != REG
1300 || REGNO (SET_DEST (PATTERN (i3))) >= FIRST_PSEUDO_REGISTER
1301 || REG_USERVAR_P (SET_DEST (PATTERN (i3))))
1303 && find_reg_note (i3, REG_DEAD, SET_SRC (PATTERN (i3)))
1304 && GET_CODE (PATTERN (i2)) == PARALLEL
1305 && ! side_effects_p (SET_DEST (PATTERN (i3)))
1306 /* If the dest of I3 is a ZERO_EXTRACT or STRICT_LOW_PART, the code
1307 below would need to check what is inside (and reg_overlap_mentioned_p
1308 doesn't support those codes anyway). Don't allow those destinations;
1309 the resulting insn isn't likely to be recognized anyway. */
1310 && GET_CODE (SET_DEST (PATTERN (i3))) != ZERO_EXTRACT
1311 && GET_CODE (SET_DEST (PATTERN (i3))) != STRICT_LOW_PART
1312 && ! reg_overlap_mentioned_p (SET_SRC (PATTERN (i3)),
1313 SET_DEST (PATTERN (i3)))
1314 && next_real_insn (i2) == i3)
1316 rtx p2 = PATTERN (i2);
1318 /* Make sure that the destination of I3,
1319 which we are going to substitute into one output of I2,
1320 is not used within another output of I2. We must avoid making this:
1321 (parallel [(set (mem (reg 69)) ...)
1322 (set (reg 69) ...)])
1323 which is not well-defined as to order of actions.
1324 (Besides, reload can't handle output reloads for this.)
1326 The problem can also happen if the dest of I3 is a memory ref,
1327 if another dest in I2 is an indirect memory ref. */
1328 for (i = 0; i < XVECLEN (p2, 0); i++)
1329 if ((GET_CODE (XVECEXP (p2, 0, i)) == SET
1330 || GET_CODE (XVECEXP (p2, 0, i)) == CLOBBER)
1331 && reg_overlap_mentioned_p (SET_DEST (PATTERN (i3)),
1332 SET_DEST (XVECEXP (p2, 0, i))))
1335 if (i == XVECLEN (p2, 0))
1336 for (i = 0; i < XVECLEN (p2, 0); i++)
1337 if (SET_DEST (XVECEXP (p2, 0, i)) == SET_SRC (PATTERN (i3)))
1342 subst_low_cuid = INSN_CUID (i2);
1344 added_sets_2 = added_sets_1 = 0;
1345 i2dest = SET_SRC (PATTERN (i3));
1347 /* Replace the dest in I2 with our dest and make the resulting
1348 insn the new pattern for I3. Then skip to where we
1349 validate the pattern. Everything was set up above. */
1350 SUBST (SET_DEST (XVECEXP (p2, 0, i)),
1351 SET_DEST (PATTERN (i3)));
1354 i3_subst_into_i2 = 1;
1355 goto validate_replacement;
1360 /* If we have no I1 and I2 looks like:
1361 (parallel [(set (reg:CC X) (compare:CC OP (const_int 0)))
1363 make up a dummy I1 that is
1366 (set (reg:CC X) (compare:CC Y (const_int 0)))
1368 (We can ignore any trailing CLOBBERs.)
1370 This undoes a previous combination and allows us to match a branch-and-
1373 if (i1 == 0 && GET_CODE (PATTERN (i2)) == PARALLEL
1374 && XVECLEN (PATTERN (i2), 0) >= 2
1375 && GET_CODE (XVECEXP (PATTERN (i2), 0, 0)) == SET
1376 && (GET_MODE_CLASS (GET_MODE (SET_DEST (XVECEXP (PATTERN (i2), 0, 0))))
1378 && GET_CODE (SET_SRC (XVECEXP (PATTERN (i2), 0, 0))) == COMPARE
1379 && XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 1) == const0_rtx
1380 && GET_CODE (XVECEXP (PATTERN (i2), 0, 1)) == SET
1381 && GET_CODE (SET_DEST (XVECEXP (PATTERN (i2), 0, 1))) == REG
1382 && rtx_equal_p (XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 0),
1383 SET_SRC (XVECEXP (PATTERN (i2), 0, 1))))
1385 for (i = XVECLEN (PATTERN (i2), 0) - 1; i >= 2; i--)
1386 if (GET_CODE (XVECEXP (PATTERN (i2), 0, i)) != CLOBBER)
1391 /* We make I1 with the same INSN_UID as I2. This gives it
1392 the same INSN_CUID for value tracking. Our fake I1 will
1393 never appear in the insn stream so giving it the same INSN_UID
1394 as I2 will not cause a problem. */
1396 subst_prev_insn = i1
1397 = gen_rtx (INSN, VOIDmode, INSN_UID (i2), 0, i2,
1398 XVECEXP (PATTERN (i2), 0, 1), -1, 0, 0);
1400 SUBST (PATTERN (i2), XVECEXP (PATTERN (i2), 0, 0));
1401 SUBST (XEXP (SET_SRC (PATTERN (i2)), 0),
1402 SET_DEST (PATTERN (i1)));
1407 /* Verify that I2 and I1 are valid for combining. */
1408 if (! can_combine_p (i2, i3, i1, NULL_RTX, &i2dest, &i2src)
1409 || (i1 && ! can_combine_p (i1, i3, NULL_RTX, i2, &i1dest, &i1src)))
1415 /* Record whether I2DEST is used in I2SRC and similarly for the other
1416 cases. Knowing this will help in register status updating below. */
1417 i2dest_in_i2src = reg_overlap_mentioned_p (i2dest, i2src);
1418 i1dest_in_i1src = i1 && reg_overlap_mentioned_p (i1dest, i1src);
1419 i2dest_in_i1src = i1 && reg_overlap_mentioned_p (i2dest, i1src);
1421 /* See if I1 directly feeds into I3. It does if I1DEST is not used
1423 i1_feeds_i3 = i1 && ! reg_overlap_mentioned_p (i1dest, i2src);
1425 /* Ensure that I3's pattern can be the destination of combines. */
1426 if (! combinable_i3pat (i3, &PATTERN (i3), i2dest, i1dest,
1427 i1 && i2dest_in_i1src && i1_feeds_i3,
1434 /* See if any of the insns is a MULT operation. Unless one is, we will
1435 reject a combination that is, since it must be slower. Be conservative
1437 if (GET_CODE (i2src) == MULT
1438 || (i1 != 0 && GET_CODE (i1src) == MULT)
1439 || (GET_CODE (PATTERN (i3)) == SET
1440 && GET_CODE (SET_SRC (PATTERN (i3))) == MULT))
1443 /* If I3 has an inc, then give up if I1 or I2 uses the reg that is inc'd.
1444 We used to do this EXCEPT in one case: I3 has a post-inc in an
1445 output operand. However, that exception can give rise to insns like
1447 which is a famous insn on the PDP-11 where the value of r3 used as the
1448 source was model-dependent. Avoid this sort of thing. */
1451 if (!(GET_CODE (PATTERN (i3)) == SET
1452 && GET_CODE (SET_SRC (PATTERN (i3))) == REG
1453 && GET_CODE (SET_DEST (PATTERN (i3))) == MEM
1454 && (GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_INC
1455 || GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_DEC)))
1456 /* It's not the exception. */
1459 for (link = REG_NOTES (i3); link; link = XEXP (link, 1))
1460 if (REG_NOTE_KIND (link) == REG_INC
1461 && (reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i2))
1463 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i1)))))
1470 /* See if the SETs in I1 or I2 need to be kept around in the merged
1471 instruction: whenever the value set there is still needed past I3.
1472 For the SETs in I2, this is easy: we see if I2DEST dies or is set in I3.
1474 For the SET in I1, we have two cases: If I1 and I2 independently
1475 feed into I3, the set in I1 needs to be kept around if I1DEST dies
1476 or is set in I3. Otherwise (if I1 feeds I2 which feeds I3), the set
1477 in I1 needs to be kept around unless I1DEST dies or is set in either
1478 I2 or I3. We can distinguish these cases by seeing if I2SRC mentions
1479 I1DEST. If so, we know I1 feeds into I2. */
1481 added_sets_2 = ! dead_or_set_p (i3, i2dest);
1484 = i1 && ! (i1_feeds_i3 ? dead_or_set_p (i3, i1dest)
1485 : (dead_or_set_p (i3, i1dest) || dead_or_set_p (i2, i1dest)));
1487 /* If the set in I2 needs to be kept around, we must make a copy of
1488 PATTERN (I2), so that when we substitute I1SRC for I1DEST in
1489 PATTERN (I2), we are only substituting for the original I1DEST, not into
1490 an already-substituted copy. This also prevents making self-referential
1491 rtx. If I2 is a PARALLEL, we just need the piece that assigns I2SRC to
1494 i2pat = (GET_CODE (PATTERN (i2)) == PARALLEL
1495 ? gen_rtx (SET, VOIDmode, i2dest, i2src)
1499 i2pat = copy_rtx (i2pat);
1503 /* Substitute in the latest insn for the regs set by the earlier ones. */
1505 maxreg = max_reg_num ();
1509 /* It is possible that the source of I2 or I1 may be performing an
1510 unneeded operation, such as a ZERO_EXTEND of something that is known
1511 to have the high part zero. Handle that case by letting subst look at
1512 the innermost one of them.
1514 Another way to do this would be to have a function that tries to
1515 simplify a single insn instead of merging two or more insns. We don't
1516 do this because of the potential of infinite loops and because
1517 of the potential extra memory required. However, doing it the way
1518 we are is a bit of a kludge and doesn't catch all cases.
1520 But only do this if -fexpensive-optimizations since it slows things down
1521 and doesn't usually win. */
1523 if (flag_expensive_optimizations)
1525 /* Pass pc_rtx so no substitutions are done, just simplifications.
1526 The cases that we are interested in here do not involve the few
1527 cases were is_replaced is checked. */
1530 subst_low_cuid = INSN_CUID (i1);
1531 i1src = subst (i1src, pc_rtx, pc_rtx, 0, 0);
1535 subst_low_cuid = INSN_CUID (i2);
1536 i2src = subst (i2src, pc_rtx, pc_rtx, 0, 0);
1539 undobuf.previous_undos = undobuf.undos;
1543 /* Many machines that don't use CC0 have insns that can both perform an
1544 arithmetic operation and set the condition code. These operations will
1545 be represented as a PARALLEL with the first element of the vector
1546 being a COMPARE of an arithmetic operation with the constant zero.
1547 The second element of the vector will set some pseudo to the result
1548 of the same arithmetic operation. If we simplify the COMPARE, we won't
1549 match such a pattern and so will generate an extra insn. Here we test
1550 for this case, where both the comparison and the operation result are
1551 needed, and make the PARALLEL by just replacing I2DEST in I3SRC with
1552 I2SRC. Later we will make the PARALLEL that contains I2. */
1554 if (i1 == 0 && added_sets_2 && GET_CODE (PATTERN (i3)) == SET
1555 && GET_CODE (SET_SRC (PATTERN (i3))) == COMPARE
1556 && XEXP (SET_SRC (PATTERN (i3)), 1) == const0_rtx
1557 && rtx_equal_p (XEXP (SET_SRC (PATTERN (i3)), 0), i2dest))
1560 enum machine_mode compare_mode;
1562 newpat = PATTERN (i3);
1563 SUBST (XEXP (SET_SRC (newpat), 0), i2src);
1567 #ifdef EXTRA_CC_MODES
1568 /* See if a COMPARE with the operand we substituted in should be done
1569 with the mode that is currently being used. If not, do the same
1570 processing we do in `subst' for a SET; namely, if the destination
1571 is used only once, try to replace it with a register of the proper
1572 mode and also replace the COMPARE. */
1573 if (undobuf.other_insn == 0
1574 && (cc_use = find_single_use (SET_DEST (newpat), i3,
1575 &undobuf.other_insn))
1576 && ((compare_mode = SELECT_CC_MODE (GET_CODE (*cc_use),
1578 != GET_MODE (SET_DEST (newpat))))
1580 int regno = REGNO (SET_DEST (newpat));
1581 rtx new_dest = gen_rtx (REG, compare_mode, regno);
1583 if (regno < FIRST_PSEUDO_REGISTER
1584 || (reg_n_sets[regno] == 1 && ! added_sets_2
1585 && ! REG_USERVAR_P (SET_DEST (newpat))))
1587 if (regno >= FIRST_PSEUDO_REGISTER)
1588 SUBST (regno_reg_rtx[regno], new_dest);
1590 SUBST (SET_DEST (newpat), new_dest);
1591 SUBST (XEXP (*cc_use, 0), new_dest);
1592 SUBST (SET_SRC (newpat),
1593 gen_rtx_combine (COMPARE, compare_mode,
1594 i2src, const0_rtx));
1597 undobuf.other_insn = 0;
1604 n_occurrences = 0; /* `subst' counts here */
1606 /* If I1 feeds into I2 (not into I3) and I1DEST is in I1SRC, we
1607 need to make a unique copy of I2SRC each time we substitute it
1608 to avoid self-referential rtl. */
1610 subst_low_cuid = INSN_CUID (i2);
1611 newpat = subst (PATTERN (i3), i2dest, i2src, 0,
1612 ! i1_feeds_i3 && i1dest_in_i1src);
1613 undobuf.previous_undos = undobuf.undos;
1615 /* Record whether i2's body now appears within i3's body. */
1616 i2_is_used = n_occurrences;
1619 /* If we already got a failure, don't try to do more. Otherwise,
1620 try to substitute in I1 if we have it. */
1622 if (i1 && GET_CODE (newpat) != CLOBBER)
1624 /* Before we can do this substitution, we must redo the test done
1625 above (see detailed comments there) that ensures that I1DEST
1626 isn't mentioned in any SETs in NEWPAT that are field assignments. */
1628 if (! combinable_i3pat (NULL_RTX, &newpat, i1dest, NULL_RTX,
1636 subst_low_cuid = INSN_CUID (i1);
1637 newpat = subst (newpat, i1dest, i1src, 0, 0);
1638 undobuf.previous_undos = undobuf.undos;
1641 /* Fail if an autoincrement side-effect has been duplicated. Be careful
1642 to count all the ways that I2SRC and I1SRC can be used. */
1643 if ((FIND_REG_INC_NOTE (i2, NULL_RTX) != 0
1644 && i2_is_used + added_sets_2 > 1)
1645 || (i1 != 0 && FIND_REG_INC_NOTE (i1, NULL_RTX) != 0
1646 && (n_occurrences + added_sets_1 + (added_sets_2 && ! i1_feeds_i3)
1648 /* Fail if we tried to make a new register (we used to abort, but there's
1649 really no reason to). */
1650 || max_reg_num () != maxreg
1651 /* Fail if we couldn't do something and have a CLOBBER. */
1652 || GET_CODE (newpat) == CLOBBER
1653 /* Fail if this new pattern is a MULT and we didn't have one before
1654 at the outer level. */
1655 || (GET_CODE (newpat) == SET && GET_CODE (SET_SRC (newpat)) == MULT
1662 /* If the actions of the earlier insns must be kept
1663 in addition to substituting them into the latest one,
1664 we must make a new PARALLEL for the latest insn
1665 to hold additional the SETs. */
1667 if (added_sets_1 || added_sets_2)
1671 if (GET_CODE (newpat) == PARALLEL)
1673 rtvec old = XVEC (newpat, 0);
1674 total_sets = XVECLEN (newpat, 0) + added_sets_1 + added_sets_2;
1675 newpat = gen_rtx (PARALLEL, VOIDmode, rtvec_alloc (total_sets));
1676 bcopy ((char *) &old->elem[0], (char *) XVEC (newpat, 0)->elem,
1677 sizeof (old->elem[0]) * old->num_elem);
1682 total_sets = 1 + added_sets_1 + added_sets_2;
1683 newpat = gen_rtx (PARALLEL, VOIDmode, rtvec_alloc (total_sets));
1684 XVECEXP (newpat, 0, 0) = old;
1688 XVECEXP (newpat, 0, --total_sets)
1689 = (GET_CODE (PATTERN (i1)) == PARALLEL
1690 ? gen_rtx (SET, VOIDmode, i1dest, i1src) : PATTERN (i1));
1694 /* If there is no I1, use I2's body as is. We used to also not do
1695 the subst call below if I2 was substituted into I3,
1696 but that could lose a simplification. */
1698 XVECEXP (newpat, 0, --total_sets) = i2pat;
1700 /* See comment where i2pat is assigned. */
1701 XVECEXP (newpat, 0, --total_sets)
1702 = subst (i2pat, i1dest, i1src, 0, 0);
1706 /* We come here when we are replacing a destination in I2 with the
1707 destination of I3. */
1708 validate_replacement:
1710 /* Note which hard regs this insn has as inputs. */
1711 mark_used_regs_combine (newpat);
1713 /* Is the result of combination a valid instruction? */
1715 = recog_for_combine (&newpat, i3, &new_i3_notes, &i3_scratches);
1717 /* If the result isn't valid, see if it is a PARALLEL of two SETs where
1718 the second SET's destination is a register that is unused. In that case,
1719 we just need the first SET. This can occur when simplifying a divmod
1720 insn. We *must* test for this case here because the code below that
1721 splits two independent SETs doesn't handle this case correctly when it
1722 updates the register status. Also check the case where the first
1723 SET's destination is unused. That would not cause incorrect code, but
1724 does cause an unneeded insn to remain. */
1726 if (insn_code_number < 0 && GET_CODE (newpat) == PARALLEL
1727 && XVECLEN (newpat, 0) == 2
1728 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
1729 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
1730 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) == REG
1731 && find_reg_note (i3, REG_UNUSED, SET_DEST (XVECEXP (newpat, 0, 1)))
1732 && ! side_effects_p (SET_SRC (XVECEXP (newpat, 0, 1)))
1733 && asm_noperands (newpat) < 0)
1735 newpat = XVECEXP (newpat, 0, 0);
1737 = recog_for_combine (&newpat, i3, &new_i3_notes, &i3_scratches);
1740 else if (insn_code_number < 0 && GET_CODE (newpat) == PARALLEL
1741 && XVECLEN (newpat, 0) == 2
1742 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
1743 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
1744 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) == REG
1745 && find_reg_note (i3, REG_UNUSED, SET_DEST (XVECEXP (newpat, 0, 0)))
1746 && ! side_effects_p (SET_SRC (XVECEXP (newpat, 0, 0)))
1747 && asm_noperands (newpat) < 0)
1749 newpat = XVECEXP (newpat, 0, 1);
1751 = recog_for_combine (&newpat, i3, &new_i3_notes, &i3_scratches);
1754 /* If we were combining three insns and the result is a simple SET
1755 with no ASM_OPERANDS that wasn't recognized, try to split it into two
1756 insns. There are two ways to do this. It can be split using a
1757 machine-specific method (like when you have an addition of a large
1758 constant) or by combine in the function find_split_point. */
1760 if (i1 && insn_code_number < 0 && GET_CODE (newpat) == SET
1761 && asm_noperands (newpat) < 0)
1763 rtx m_split, *split;
1764 rtx ni2dest = i2dest;
1766 /* See if the MD file can split NEWPAT. If it can't, see if letting it
1767 use I2DEST as a scratch register will help. In the latter case,
1768 convert I2DEST to the mode of the source of NEWPAT if we can. */
1770 m_split = split_insns (newpat, i3);
1772 /* We can only use I2DEST as a scratch reg if it doesn't overlap any
1773 inputs of NEWPAT. */
1775 /* ??? If I2DEST is not safe, and I1DEST exists, then it would be
1776 possible to try that as a scratch reg. This would require adding
1777 more code to make it work though. */
1779 if (m_split == 0 && ! reg_overlap_mentioned_p (ni2dest, newpat))
1781 /* If I2DEST is a hard register or the only use of a pseudo,
1782 we can change its mode. */
1783 if (GET_MODE (SET_DEST (newpat)) != GET_MODE (i2dest)
1784 && GET_MODE (SET_DEST (newpat)) != VOIDmode
1785 && GET_CODE (i2dest) == REG
1786 && (REGNO (i2dest) < FIRST_PSEUDO_REGISTER
1787 || (reg_n_sets[REGNO (i2dest)] == 1 && ! added_sets_2
1788 && ! REG_USERVAR_P (i2dest))))
1789 ni2dest = gen_rtx (REG, GET_MODE (SET_DEST (newpat)),
1792 m_split = split_insns (gen_rtx (PARALLEL, VOIDmode,
1793 gen_rtvec (2, newpat,
1800 if (m_split && GET_CODE (m_split) == SEQUENCE
1801 && XVECLEN (m_split, 0) == 2
1802 && (next_real_insn (i2) == i3
1803 || ! use_crosses_set_p (PATTERN (XVECEXP (m_split, 0, 0)),
1807 rtx newi3pat = PATTERN (XVECEXP (m_split, 0, 1));
1808 newi2pat = PATTERN (XVECEXP (m_split, 0, 0));
1810 i3set = single_set (XVECEXP (m_split, 0, 1));
1811 i2set = single_set (XVECEXP (m_split, 0, 0));
1813 /* In case we changed the mode of I2DEST, replace it in the
1814 pseudo-register table here. We can't do it above in case this
1815 code doesn't get executed and we do a split the other way. */
1817 if (REGNO (i2dest) >= FIRST_PSEUDO_REGISTER)
1818 SUBST (regno_reg_rtx[REGNO (i2dest)], ni2dest);
1820 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes,
1823 /* If I2 or I3 has multiple SETs, we won't know how to track
1824 register status, so don't use these insns. If I2's destination
1825 is used between I2 and I3, we also can't use these insns. */
1827 if (i2_code_number >= 0 && i2set && i3set
1828 && (next_real_insn (i2) == i3
1829 || ! reg_used_between_p (SET_DEST (i2set), i2, i3)))
1830 insn_code_number = recog_for_combine (&newi3pat, i3, &new_i3_notes,
1832 if (insn_code_number >= 0)
1835 /* It is possible that both insns now set the destination of I3.
1836 If so, we must show an extra use of it. */
1838 if (insn_code_number >= 0)
1840 rtx new_i3_dest = SET_DEST (i3set);
1841 rtx new_i2_dest = SET_DEST (i2set);
1843 while (GET_CODE (new_i3_dest) == ZERO_EXTRACT
1844 || GET_CODE (new_i3_dest) == STRICT_LOW_PART
1845 || GET_CODE (new_i3_dest) == SUBREG)
1846 new_i3_dest = XEXP (new_i3_dest, 0);
1848 while (GET_CODE (new_i2_dest) == ZERO_EXTRACT
1849 || GET_CODE (new_i2_dest) == STRICT_LOW_PART
1850 || GET_CODE (new_i2_dest) == SUBREG)
1851 new_i2_dest = XEXP (new_i2_dest, 0);
1853 if (GET_CODE (new_i3_dest) == REG
1854 && GET_CODE (new_i2_dest) == REG
1855 && REGNO (new_i3_dest) == REGNO (new_i2_dest))
1856 reg_n_sets[REGNO (new_i2_dest)]++;
1860 /* If we can split it and use I2DEST, go ahead and see if that
1861 helps things be recognized. Verify that none of the registers
1862 are set between I2 and I3. */
1863 if (insn_code_number < 0 && (split = find_split_point (&newpat, i3)) != 0
1865 && GET_CODE (i2dest) == REG
1867 /* We need I2DEST in the proper mode. If it is a hard register
1868 or the only use of a pseudo, we can change its mode. */
1869 && (GET_MODE (*split) == GET_MODE (i2dest)
1870 || GET_MODE (*split) == VOIDmode
1871 || REGNO (i2dest) < FIRST_PSEUDO_REGISTER
1872 || (reg_n_sets[REGNO (i2dest)] == 1 && ! added_sets_2
1873 && ! REG_USERVAR_P (i2dest)))
1874 && (next_real_insn (i2) == i3
1875 || ! use_crosses_set_p (*split, INSN_CUID (i2)))
1876 /* We can't overwrite I2DEST if its value is still used by
1878 && ! reg_referenced_p (i2dest, newpat))
1880 rtx newdest = i2dest;
1881 enum rtx_code split_code = GET_CODE (*split);
1882 enum machine_mode split_mode = GET_MODE (*split);
1884 /* Get NEWDEST as a register in the proper mode. We have already
1885 validated that we can do this. */
1886 if (GET_MODE (i2dest) != split_mode && split_mode != VOIDmode)
1888 newdest = gen_rtx (REG, split_mode, REGNO (i2dest));
1890 if (REGNO (i2dest) >= FIRST_PSEUDO_REGISTER)
1891 SUBST (regno_reg_rtx[REGNO (i2dest)], newdest);
1894 /* If *SPLIT is a (mult FOO (const_int pow2)), convert it to
1895 an ASHIFT. This can occur if it was inside a PLUS and hence
1896 appeared to be a memory address. This is a kludge. */
1897 if (split_code == MULT
1898 && GET_CODE (XEXP (*split, 1)) == CONST_INT
1899 && (i = exact_log2 (INTVAL (XEXP (*split, 1)))) >= 0)
1901 SUBST (*split, gen_rtx_combine (ASHIFT, split_mode,
1902 XEXP (*split, 0), GEN_INT (i)));
1903 /* Update split_code because we may not have a multiply
1905 split_code = GET_CODE (*split);
1908 #ifdef INSN_SCHEDULING
1909 /* If *SPLIT is a paradoxical SUBREG, when we split it, it should
1910 be written as a ZERO_EXTEND. */
1911 if (split_code == SUBREG && GET_CODE (SUBREG_REG (*split)) == MEM)
1912 SUBST (*split, gen_rtx_combine (ZERO_EXTEND, split_mode,
1916 newi2pat = gen_rtx_combine (SET, VOIDmode, newdest, *split);
1917 SUBST (*split, newdest);
1919 = recog_for_combine (&newi2pat, i2, &new_i2_notes, &i2_scratches);
1921 /* If the split point was a MULT and we didn't have one before,
1922 don't use one now. */
1923 if (i2_code_number >= 0 && ! (split_code == MULT && ! have_mult))
1925 = recog_for_combine (&newpat, i3, &new_i3_notes, &i3_scratches);
1929 /* Check for a case where we loaded from memory in a narrow mode and
1930 then sign extended it, but we need both registers. In that case,
1931 we have a PARALLEL with both loads from the same memory location.
1932 We can split this into a load from memory followed by a register-register
1933 copy. This saves at least one insn, more if register allocation can
1936 We cannot do this if the destination of the second assignment is
1937 a register that we have already assumed is zero-extended. Similarly
1938 for a SUBREG of such a register. */
1940 else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0
1941 && GET_CODE (newpat) == PARALLEL
1942 && XVECLEN (newpat, 0) == 2
1943 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
1944 && GET_CODE (SET_SRC (XVECEXP (newpat, 0, 0))) == SIGN_EXTEND
1945 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
1946 && rtx_equal_p (SET_SRC (XVECEXP (newpat, 0, 1)),
1947 XEXP (SET_SRC (XVECEXP (newpat, 0, 0)), 0))
1948 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)),
1950 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
1951 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
1952 && ! (temp = SET_DEST (XVECEXP (newpat, 0, 1)),
1953 (GET_CODE (temp) == REG
1954 && reg_nonzero_bits[REGNO (temp)] != 0
1955 && GET_MODE_BITSIZE (GET_MODE (temp)) < BITS_PER_WORD
1956 && GET_MODE_BITSIZE (GET_MODE (temp)) < HOST_BITS_PER_INT
1957 && (reg_nonzero_bits[REGNO (temp)]
1958 != GET_MODE_MASK (word_mode))))
1959 && ! (GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) == SUBREG
1960 && (temp = SUBREG_REG (SET_DEST (XVECEXP (newpat, 0, 1))),
1961 (GET_CODE (temp) == REG
1962 && reg_nonzero_bits[REGNO (temp)] != 0
1963 && GET_MODE_BITSIZE (GET_MODE (temp)) < BITS_PER_WORD
1964 && GET_MODE_BITSIZE (GET_MODE (temp)) < HOST_BITS_PER_INT
1965 && (reg_nonzero_bits[REGNO (temp)]
1966 != GET_MODE_MASK (word_mode)))))
1967 && ! reg_overlap_mentioned_p (SET_DEST (XVECEXP (newpat, 0, 1)),
1968 SET_SRC (XVECEXP (newpat, 0, 1)))
1969 && ! find_reg_note (i3, REG_UNUSED,
1970 SET_DEST (XVECEXP (newpat, 0, 0))))
1974 newi2pat = XVECEXP (newpat, 0, 0);
1975 ni2dest = SET_DEST (XVECEXP (newpat, 0, 0));
1976 newpat = XVECEXP (newpat, 0, 1);
1977 SUBST (SET_SRC (newpat),
1978 gen_lowpart_for_combine (GET_MODE (SET_SRC (newpat)), ni2dest));
1980 = recog_for_combine (&newi2pat, i2, &new_i2_notes, &i2_scratches);
1982 if (i2_code_number >= 0)
1984 = recog_for_combine (&newpat, i3, &new_i3_notes, &i3_scratches);
1986 if (insn_code_number >= 0)
1991 /* If we will be able to accept this, we have made a change to the
1992 destination of I3. This can invalidate a LOG_LINKS pointing
1993 to I3. No other part of combine.c makes such a transformation.
1995 The new I3 will have a destination that was previously the
1996 destination of I1 or I2 and which was used in i2 or I3. Call
1997 distribute_links to make a LOG_LINK from the next use of
1998 that destination. */
2000 PATTERN (i3) = newpat;
2001 distribute_links (gen_rtx (INSN_LIST, VOIDmode, i3, NULL_RTX));
2003 /* I3 now uses what used to be its destination and which is
2004 now I2's destination. That means we need a LOG_LINK from
2005 I3 to I2. But we used to have one, so we still will.
2007 However, some later insn might be using I2's dest and have
2008 a LOG_LINK pointing at I3. We must remove this link.
2009 The simplest way to remove the link is to point it at I1,
2010 which we know will be a NOTE. */
2012 for (insn = NEXT_INSN (i3);
2013 insn && (this_basic_block == n_basic_blocks - 1
2014 || insn != basic_block_head[this_basic_block + 1]);
2015 insn = NEXT_INSN (insn))
2017 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i'
2018 && reg_referenced_p (ni2dest, PATTERN (insn)))
2020 for (link = LOG_LINKS (insn); link;
2021 link = XEXP (link, 1))
2022 if (XEXP (link, 0) == i3)
2023 XEXP (link, 0) = i1;
2031 /* Similarly, check for a case where we have a PARALLEL of two independent
2032 SETs but we started with three insns. In this case, we can do the sets
2033 as two separate insns. This case occurs when some SET allows two
2034 other insns to combine, but the destination of that SET is still live. */
2036 else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0
2037 && GET_CODE (newpat) == PARALLEL
2038 && XVECLEN (newpat, 0) == 2
2039 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
2040 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != ZERO_EXTRACT
2041 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != STRICT_LOW_PART
2042 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
2043 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
2044 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
2045 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)),
2047 /* Don't pass sets with (USE (MEM ...)) dests to the following. */
2048 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != USE
2049 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != USE
2050 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 1)),
2051 XVECEXP (newpat, 0, 0))
2052 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 0)),
2053 XVECEXP (newpat, 0, 1)))
2055 newi2pat = XVECEXP (newpat, 0, 1);
2056 newpat = XVECEXP (newpat, 0, 0);
2059 = recog_for_combine (&newi2pat, i2, &new_i2_notes, &i2_scratches);
2061 if (i2_code_number >= 0)
2063 = recog_for_combine (&newpat, i3, &new_i3_notes, &i3_scratches);
2066 /* If it still isn't recognized, fail and change things back the way they
2068 if ((insn_code_number < 0
2069 /* Is the result a reasonable ASM_OPERANDS? */
2070 && (! check_asm_operands (newpat) || added_sets_1 || added_sets_2)))
2076 /* If we had to change another insn, make sure it is valid also. */
2077 if (undobuf.other_insn)
2079 rtx other_pat = PATTERN (undobuf.other_insn);
2080 rtx new_other_notes;
2083 CLEAR_HARD_REG_SET (newpat_used_regs);
2086 = recog_for_combine (&other_pat, undobuf.other_insn,
2087 &new_other_notes, &other_scratches);
2089 if (other_code_number < 0 && ! check_asm_operands (other_pat))
2095 PATTERN (undobuf.other_insn) = other_pat;
2097 /* If any of the notes in OTHER_INSN were REG_UNUSED, ensure that they
2098 are still valid. Then add any non-duplicate notes added by
2099 recog_for_combine. */
2100 for (note = REG_NOTES (undobuf.other_insn); note; note = next)
2102 next = XEXP (note, 1);
2104 if (REG_NOTE_KIND (note) == REG_UNUSED
2105 && ! reg_set_p (XEXP (note, 0), PATTERN (undobuf.other_insn)))
2107 if (GET_CODE (XEXP (note, 0)) == REG)
2108 reg_n_deaths[REGNO (XEXP (note, 0))]--;
2110 remove_note (undobuf.other_insn, note);
2114 for (note = new_other_notes; note; note = XEXP (note, 1))
2115 if (GET_CODE (XEXP (note, 0)) == REG)
2116 reg_n_deaths[REGNO (XEXP (note, 0))]++;
2118 distribute_notes (new_other_notes, undobuf.other_insn,
2119 undobuf.other_insn, NULL_RTX, NULL_RTX, NULL_RTX);
2122 /* We now know that we can do this combination. Merge the insns and
2123 update the status of registers and LOG_LINKS. */
2126 rtx i3notes, i2notes, i1notes = 0;
2127 rtx i3links, i2links, i1links = 0;
2130 /* Compute which registers we expect to eliminate. */
2131 rtx elim_i2 = (newi2pat || i2dest_in_i2src || i2dest_in_i1src
2133 rtx elim_i1 = i1 == 0 || i1dest_in_i1src ? 0 : i1dest;
2135 /* Get the old REG_NOTES and LOG_LINKS from all our insns and
2137 i3notes = REG_NOTES (i3), i3links = LOG_LINKS (i3);
2138 i2notes = REG_NOTES (i2), i2links = LOG_LINKS (i2);
2140 i1notes = REG_NOTES (i1), i1links = LOG_LINKS (i1);
2142 /* Ensure that we do not have something that should not be shared but
2143 occurs multiple times in the new insns. Check this by first
2144 resetting all the `used' flags and then copying anything is shared. */
2146 reset_used_flags (i3notes);
2147 reset_used_flags (i2notes);
2148 reset_used_flags (i1notes);
2149 reset_used_flags (newpat);
2150 reset_used_flags (newi2pat);
2151 if (undobuf.other_insn)
2152 reset_used_flags (PATTERN (undobuf.other_insn));
2154 i3notes = copy_rtx_if_shared (i3notes);
2155 i2notes = copy_rtx_if_shared (i2notes);
2156 i1notes = copy_rtx_if_shared (i1notes);
2157 newpat = copy_rtx_if_shared (newpat);
2158 newi2pat = copy_rtx_if_shared (newi2pat);
2159 if (undobuf.other_insn)
2160 reset_used_flags (PATTERN (undobuf.other_insn));
2162 INSN_CODE (i3) = insn_code_number;
2163 PATTERN (i3) = newpat;
2164 if (undobuf.other_insn)
2165 INSN_CODE (undobuf.other_insn) = other_code_number;
2167 /* We had one special case above where I2 had more than one set and
2168 we replaced a destination of one of those sets with the destination
2169 of I3. In that case, we have to update LOG_LINKS of insns later
2170 in this basic block. Note that this (expensive) case is rare.
2172 Also, in this case, we must pretend that all REG_NOTEs for I2
2173 actually came from I3, so that REG_UNUSED notes from I2 will be
2174 properly handled. */
2176 if (i3_subst_into_i2)
2178 for (i = 0; i < XVECLEN (PATTERN (i2), 0); i++)
2179 if (GET_CODE (SET_DEST (XVECEXP (PATTERN (i2), 0, i))) == REG
2180 && SET_DEST (XVECEXP (PATTERN (i2), 0, i)) != i2dest
2181 && ! find_reg_note (i2, REG_UNUSED,
2182 SET_DEST (XVECEXP (PATTERN (i2), 0, i))))
2183 for (temp = NEXT_INSN (i2);
2184 temp && (this_basic_block == n_basic_blocks - 1
2185 || basic_block_head[this_basic_block] != temp);
2186 temp = NEXT_INSN (temp))
2187 if (temp != i3 && GET_RTX_CLASS (GET_CODE (temp)) == 'i')
2188 for (link = LOG_LINKS (temp); link; link = XEXP (link, 1))
2189 if (XEXP (link, 0) == i2)
2190 XEXP (link, 0) = i3;
2195 while (XEXP (link, 1))
2196 link = XEXP (link, 1);
2197 XEXP (link, 1) = i2notes;
2211 INSN_CODE (i2) = i2_code_number;
2212 PATTERN (i2) = newi2pat;
2216 PUT_CODE (i2, NOTE);
2217 NOTE_LINE_NUMBER (i2) = NOTE_INSN_DELETED;
2218 NOTE_SOURCE_FILE (i2) = 0;
2225 PUT_CODE (i1, NOTE);
2226 NOTE_LINE_NUMBER (i1) = NOTE_INSN_DELETED;
2227 NOTE_SOURCE_FILE (i1) = 0;
2230 /* Get death notes for everything that is now used in either I3 or
2231 I2 and used to die in a previous insn. If we built two new
2232 patterns, move from I1 to I2 then I2 to I3 so that we get the
2233 proper movement on registers that I2 modifies. */
2237 move_deaths (newi2pat, NULL_RTX, INSN_CUID (i1), i2, &midnotes);
2238 move_deaths (newpat, newi2pat, INSN_CUID (i1), i3, &midnotes);
2241 move_deaths (newpat, NULL_RTX, i1 ? INSN_CUID (i1) : INSN_CUID (i2),
2244 /* Distribute all the LOG_LINKS and REG_NOTES from I1, I2, and I3. */
2246 distribute_notes (i3notes, i3, i3, newi2pat ? i2 : NULL_RTX,
2249 distribute_notes (i2notes, i2, i3, newi2pat ? i2 : NULL_RTX,
2252 distribute_notes (i1notes, i1, i3, newi2pat ? i2 : NULL_RTX,
2255 distribute_notes (midnotes, NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
2258 /* Distribute any notes added to I2 or I3 by recog_for_combine. We
2259 know these are REG_UNUSED and want them to go to the desired insn,
2260 so we always pass it as i3. We have not counted the notes in
2261 reg_n_deaths yet, so we need to do so now. */
2263 if (newi2pat && new_i2_notes)
2265 for (temp = new_i2_notes; temp; temp = XEXP (temp, 1))
2266 if (GET_CODE (XEXP (temp, 0)) == REG)
2267 reg_n_deaths[REGNO (XEXP (temp, 0))]++;
2269 distribute_notes (new_i2_notes, i2, i2, NULL_RTX, NULL_RTX, NULL_RTX);
2274 for (temp = new_i3_notes; temp; temp = XEXP (temp, 1))
2275 if (GET_CODE (XEXP (temp, 0)) == REG)
2276 reg_n_deaths[REGNO (XEXP (temp, 0))]++;
2278 distribute_notes (new_i3_notes, i3, i3, NULL_RTX, NULL_RTX, NULL_RTX);
2281 /* If I3DEST was used in I3SRC, it really died in I3. We may need to
2282 put a REG_DEAD note for it somewhere. Similarly for I2 and I1.
2283 Show an additional death due to the REG_DEAD note we make here. If
2284 we discard it in distribute_notes, we will decrement it again. */
2288 if (GET_CODE (i3dest_killed) == REG)
2289 reg_n_deaths[REGNO (i3dest_killed)]++;
2291 distribute_notes (gen_rtx (EXPR_LIST, REG_DEAD, i3dest_killed,
2293 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
2294 NULL_RTX, NULL_RTX);
2297 /* For I2 and I1, we have to be careful. If NEWI2PAT exists and sets
2298 I2DEST or I1DEST, the death must be somewhere before I2, not I3. If
2299 we passed I3 in that case, it might delete I2. */
2301 if (i2dest_in_i2src)
2303 if (GET_CODE (i2dest) == REG)
2304 reg_n_deaths[REGNO (i2dest)]++;
2306 if (newi2pat && reg_set_p (i2dest, newi2pat))
2307 distribute_notes (gen_rtx (EXPR_LIST, REG_DEAD, i2dest, NULL_RTX),
2308 NULL_RTX, i2, NULL_RTX, NULL_RTX, NULL_RTX);
2310 distribute_notes (gen_rtx (EXPR_LIST, REG_DEAD, i2dest, NULL_RTX),
2311 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
2312 NULL_RTX, NULL_RTX);
2315 if (i1dest_in_i1src)
2317 if (GET_CODE (i1dest) == REG)
2318 reg_n_deaths[REGNO (i1dest)]++;
2320 if (newi2pat && reg_set_p (i1dest, newi2pat))
2321 distribute_notes (gen_rtx (EXPR_LIST, REG_DEAD, i1dest, NULL_RTX),
2322 NULL_RTX, i2, NULL_RTX, NULL_RTX, NULL_RTX);
2324 distribute_notes (gen_rtx (EXPR_LIST, REG_DEAD, i1dest, NULL_RTX),
2325 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
2326 NULL_RTX, NULL_RTX);
2329 distribute_links (i3links);
2330 distribute_links (i2links);
2331 distribute_links (i1links);
2333 if (GET_CODE (i2dest) == REG)
2336 rtx i2_insn = 0, i2_val = 0, set;
2338 /* The insn that used to set this register doesn't exist, and
2339 this life of the register may not exist either. See if one of
2340 I3's links points to an insn that sets I2DEST. If it does,
2341 that is now the last known value for I2DEST. If we don't update
2342 this and I2 set the register to a value that depended on its old
2343 contents, we will get confused. If this insn is used, thing
2344 will be set correctly in combine_instructions. */
2346 for (link = LOG_LINKS (i3); link; link = XEXP (link, 1))
2347 if ((set = single_set (XEXP (link, 0))) != 0
2348 && rtx_equal_p (i2dest, SET_DEST (set)))
2349 i2_insn = XEXP (link, 0), i2_val = SET_SRC (set);
2351 record_value_for_reg (i2dest, i2_insn, i2_val);
2353 /* If the reg formerly set in I2 died only once and that was in I3,
2354 zero its use count so it won't make `reload' do any work. */
2355 if (! added_sets_2 && newi2pat == 0 && ! i2dest_in_i2src)
2357 regno = REGNO (i2dest);
2358 reg_n_sets[regno]--;
2359 if (reg_n_sets[regno] == 0
2360 && ! (basic_block_live_at_start[0][regno / REGSET_ELT_BITS]
2361 & ((REGSET_ELT_TYPE) 1 << (regno % REGSET_ELT_BITS))))
2362 reg_n_refs[regno] = 0;
2366 if (i1 && GET_CODE (i1dest) == REG)
2369 rtx i1_insn = 0, i1_val = 0, set;
2371 for (link = LOG_LINKS (i3); link; link = XEXP (link, 1))
2372 if ((set = single_set (XEXP (link, 0))) != 0
2373 && rtx_equal_p (i1dest, SET_DEST (set)))
2374 i1_insn = XEXP (link, 0), i1_val = SET_SRC (set);
2376 record_value_for_reg (i1dest, i1_insn, i1_val);
2378 regno = REGNO (i1dest);
2379 if (! added_sets_1 && ! i1dest_in_i1src)
2381 reg_n_sets[regno]--;
2382 if (reg_n_sets[regno] == 0
2383 && ! (basic_block_live_at_start[0][regno / REGSET_ELT_BITS]
2384 & ((REGSET_ELT_TYPE) 1 << (regno % REGSET_ELT_BITS))))
2385 reg_n_refs[regno] = 0;
2389 /* Update reg_nonzero_bits et al for any changes that may have been made
2392 note_stores (newpat, set_nonzero_bits_and_sign_copies);
2394 note_stores (newi2pat, set_nonzero_bits_and_sign_copies);
2396 /* If we added any (clobber (scratch)), add them to the max for a
2397 block. This is a very pessimistic calculation, since we might
2398 have had them already and this might not be the worst block, but
2399 it's not worth doing any better. */
2400 max_scratch += i3_scratches + i2_scratches + other_scratches;
2402 /* If I3 is now an unconditional jump, ensure that it has a
2403 BARRIER following it since it may have initially been a
2404 conditional jump. It may also be the last nonnote insn. */
2406 if ((GET_CODE (newpat) == RETURN || simplejump_p (i3))
2407 && ((temp = next_nonnote_insn (i3)) == NULL_RTX
2408 || GET_CODE (temp) != BARRIER))
2409 emit_barrier_after (i3);
2412 combine_successes++;
2414 /* Clear this here, so that subsequent get_last_value calls are not
2416 subst_prev_insn = NULL_RTX;
2418 if (added_links_insn
2419 && (newi2pat == 0 || INSN_CUID (added_links_insn) < INSN_CUID (i2))
2420 && INSN_CUID (added_links_insn) < INSN_CUID (i3))
2421 return added_links_insn;
2423 return newi2pat ? i2 : i3;
2426 /* Undo all the modifications recorded in undobuf. */
2431 struct undo *undo, *next;
2433 for (undo = undobuf.undos; undo; undo = next)
2437 *undo->where.i = undo->old_contents.i;
2439 *undo->where.r = undo->old_contents.r;
2441 undo->next = undobuf.frees;
2442 undobuf.frees = undo;
2445 obfree (undobuf.storage);
2446 undobuf.undos = undobuf.previous_undos = 0;
2448 /* Clear this here, so that subsequent get_last_value calls are not
2450 subst_prev_insn = NULL_RTX;
2453 /* Find the innermost point within the rtx at LOC, possibly LOC itself,
2454 where we have an arithmetic expression and return that point. LOC will
2457 try_combine will call this function to see if an insn can be split into
2461 find_split_point (loc, insn)
2466 enum rtx_code code = GET_CODE (x);
2468 int len = 0, pos, unsignedp;
2471 /* First special-case some codes. */
2475 #ifdef INSN_SCHEDULING
2476 /* If we are making a paradoxical SUBREG invalid, it becomes a split
2478 if (GET_CODE (SUBREG_REG (x)) == MEM)
2481 return find_split_point (&SUBREG_REG (x), insn);
2485 /* If we have (mem (const ..)) or (mem (symbol_ref ...)), split it
2486 using LO_SUM and HIGH. */
2487 if (GET_CODE (XEXP (x, 0)) == CONST
2488 || GET_CODE (XEXP (x, 0)) == SYMBOL_REF)
2491 gen_rtx_combine (LO_SUM, Pmode,
2492 gen_rtx_combine (HIGH, Pmode, XEXP (x, 0)),
2494 return &XEXP (XEXP (x, 0), 0);
2498 /* If we have a PLUS whose second operand is a constant and the
2499 address is not valid, perhaps will can split it up using
2500 the machine-specific way to split large constants. We use
2501 the first pseudo-reg (one of the virtual regs) as a placeholder;
2502 it will not remain in the result. */
2503 if (GET_CODE (XEXP (x, 0)) == PLUS
2504 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
2505 && ! memory_address_p (GET_MODE (x), XEXP (x, 0)))
2507 rtx reg = regno_reg_rtx[FIRST_PSEUDO_REGISTER];
2508 rtx seq = split_insns (gen_rtx (SET, VOIDmode, reg, XEXP (x, 0)),
2511 /* This should have produced two insns, each of which sets our
2512 placeholder. If the source of the second is a valid address,
2513 we can make put both sources together and make a split point
2516 if (seq && XVECLEN (seq, 0) == 2
2517 && GET_CODE (XVECEXP (seq, 0, 0)) == INSN
2518 && GET_CODE (PATTERN (XVECEXP (seq, 0, 0))) == SET
2519 && SET_DEST (PATTERN (XVECEXP (seq, 0, 0))) == reg
2520 && ! reg_mentioned_p (reg,
2521 SET_SRC (PATTERN (XVECEXP (seq, 0, 0))))
2522 && GET_CODE (XVECEXP (seq, 0, 1)) == INSN
2523 && GET_CODE (PATTERN (XVECEXP (seq, 0, 1))) == SET
2524 && SET_DEST (PATTERN (XVECEXP (seq, 0, 1))) == reg
2525 && memory_address_p (GET_MODE (x),
2526 SET_SRC (PATTERN (XVECEXP (seq, 0, 1)))))
2528 rtx src1 = SET_SRC (PATTERN (XVECEXP (seq, 0, 0)));
2529 rtx src2 = SET_SRC (PATTERN (XVECEXP (seq, 0, 1)));
2531 /* Replace the placeholder in SRC2 with SRC1. If we can
2532 find where in SRC2 it was placed, that can become our
2533 split point and we can replace this address with SRC2.
2534 Just try two obvious places. */
2536 src2 = replace_rtx (src2, reg, src1);
2538 if (XEXP (src2, 0) == src1)
2539 split = &XEXP (src2, 0);
2540 else if (GET_RTX_FORMAT (GET_CODE (XEXP (src2, 0)))[0] == 'e'
2541 && XEXP (XEXP (src2, 0), 0) == src1)
2542 split = &XEXP (XEXP (src2, 0), 0);
2546 SUBST (XEXP (x, 0), src2);
2551 /* If that didn't work, perhaps the first operand is complex and
2552 needs to be computed separately, so make a split point there.
2553 This will occur on machines that just support REG + CONST
2554 and have a constant moved through some previous computation. */
2556 else if (GET_RTX_CLASS (GET_CODE (XEXP (XEXP (x, 0), 0))) != 'o'
2557 && ! (GET_CODE (XEXP (XEXP (x, 0), 0)) == SUBREG
2558 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (XEXP (x, 0), 0))))
2560 return &XEXP (XEXP (x, 0), 0);
2566 /* If SET_DEST is CC0 and SET_SRC is not an operand, a COMPARE, or a
2567 ZERO_EXTRACT, the most likely reason why this doesn't match is that
2568 we need to put the operand into a register. So split at that
2571 if (SET_DEST (x) == cc0_rtx
2572 && GET_CODE (SET_SRC (x)) != COMPARE
2573 && GET_CODE (SET_SRC (x)) != ZERO_EXTRACT
2574 && GET_RTX_CLASS (GET_CODE (SET_SRC (x))) != 'o'
2575 && ! (GET_CODE (SET_SRC (x)) == SUBREG
2576 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (SET_SRC (x)))) == 'o'))
2577 return &SET_SRC (x);
2580 /* See if we can split SET_SRC as it stands. */
2581 split = find_split_point (&SET_SRC (x), insn);
2582 if (split && split != &SET_SRC (x))
2585 /* See if we can split SET_DEST as it stands. */
2586 split = find_split_point (&SET_DEST (x), insn);
2587 if (split && split != &SET_DEST (x))
2590 /* See if this is a bitfield assignment with everything constant. If
2591 so, this is an IOR of an AND, so split it into that. */
2592 if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
2593 && (GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0)))
2594 <= HOST_BITS_PER_WIDE_INT)
2595 && GET_CODE (XEXP (SET_DEST (x), 1)) == CONST_INT
2596 && GET_CODE (XEXP (SET_DEST (x), 2)) == CONST_INT
2597 && GET_CODE (SET_SRC (x)) == CONST_INT
2598 && ((INTVAL (XEXP (SET_DEST (x), 1))
2599 + INTVAL (XEXP (SET_DEST (x), 2)))
2600 <= GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0))))
2601 && ! side_effects_p (XEXP (SET_DEST (x), 0)))
2603 int pos = INTVAL (XEXP (SET_DEST (x), 2));
2604 int len = INTVAL (XEXP (SET_DEST (x), 1));
2605 int src = INTVAL (SET_SRC (x));
2606 rtx dest = XEXP (SET_DEST (x), 0);
2607 enum machine_mode mode = GET_MODE (dest);
2608 unsigned HOST_WIDE_INT mask = ((HOST_WIDE_INT) 1 << len) - 1;
2610 if (BITS_BIG_ENDIAN)
2611 pos = GET_MODE_BITSIZE (mode) - len - pos;
2615 gen_binary (IOR, mode, dest, GEN_INT (src << pos)));
2618 gen_binary (IOR, mode,
2619 gen_binary (AND, mode, dest,
2620 GEN_INT (~ (mask << pos)
2621 & GET_MODE_MASK (mode))),
2622 GEN_INT (src << pos)));
2624 SUBST (SET_DEST (x), dest);
2626 split = find_split_point (&SET_SRC (x), insn);
2627 if (split && split != &SET_SRC (x))
2631 /* Otherwise, see if this is an operation that we can split into two.
2632 If so, try to split that. */
2633 code = GET_CODE (SET_SRC (x));
2638 /* If we are AND'ing with a large constant that is only a single
2639 bit and the result is only being used in a context where we
2640 need to know if it is zero or non-zero, replace it with a bit
2641 extraction. This will avoid the large constant, which might
2642 have taken more than one insn to make. If the constant were
2643 not a valid argument to the AND but took only one insn to make,
2644 this is no worse, but if it took more than one insn, it will
2647 if (GET_CODE (XEXP (SET_SRC (x), 1)) == CONST_INT
2648 && GET_CODE (XEXP (SET_SRC (x), 0)) == REG
2649 && (pos = exact_log2 (INTVAL (XEXP (SET_SRC (x), 1)))) >= 7
2650 && GET_CODE (SET_DEST (x)) == REG
2651 && (split = find_single_use (SET_DEST (x), insn, NULL_PTR)) != 0
2652 && (GET_CODE (*split) == EQ || GET_CODE (*split) == NE)
2653 && XEXP (*split, 0) == SET_DEST (x)
2654 && XEXP (*split, 1) == const0_rtx)
2656 rtx extraction = make_extraction (GET_MODE (SET_DEST (x)),
2657 XEXP (SET_SRC (x), 0),
2658 pos, NULL_RTX, 1, 1, 0, 0);
2659 if (extraction != 0)
2661 SUBST (SET_SRC (x), extraction);
2662 return find_split_point (loc, insn);
2668 inner = XEXP (SET_SRC (x), 0);
2670 len = GET_MODE_BITSIZE (GET_MODE (inner));
2676 if (GET_CODE (XEXP (SET_SRC (x), 1)) == CONST_INT
2677 && GET_CODE (XEXP (SET_SRC (x), 2)) == CONST_INT)
2679 inner = XEXP (SET_SRC (x), 0);
2680 len = INTVAL (XEXP (SET_SRC (x), 1));
2681 pos = INTVAL (XEXP (SET_SRC (x), 2));
2683 if (BITS_BIG_ENDIAN)
2684 pos = GET_MODE_BITSIZE (GET_MODE (inner)) - len - pos;
2685 unsignedp = (code == ZERO_EXTRACT);
2690 if (len && pos >= 0 && pos + len <= GET_MODE_BITSIZE (GET_MODE (inner)))
2692 enum machine_mode mode = GET_MODE (SET_SRC (x));
2694 /* For unsigned, we have a choice of a shift followed by an
2695 AND or two shifts. Use two shifts for field sizes where the
2696 constant might be too large. We assume here that we can
2697 always at least get 8-bit constants in an AND insn, which is
2698 true for every current RISC. */
2700 if (unsignedp && len <= 8)
2705 gen_rtx_combine (LSHIFTRT, mode,
2706 gen_lowpart_for_combine (mode, inner),
2708 GEN_INT (((HOST_WIDE_INT) 1 << len) - 1)));
2710 split = find_split_point (&SET_SRC (x), insn);
2711 if (split && split != &SET_SRC (x))
2718 (unsignedp ? LSHIFTRT : ASHIFTRT, mode,
2719 gen_rtx_combine (ASHIFT, mode,
2720 gen_lowpart_for_combine (mode, inner),
2721 GEN_INT (GET_MODE_BITSIZE (mode)
2723 GEN_INT (GET_MODE_BITSIZE (mode) - len)));
2725 split = find_split_point (&SET_SRC (x), insn);
2726 if (split && split != &SET_SRC (x))
2731 /* See if this is a simple operation with a constant as the second
2732 operand. It might be that this constant is out of range and hence
2733 could be used as a split point. */
2734 if ((GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '2'
2735 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == 'c'
2736 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '<')
2737 && CONSTANT_P (XEXP (SET_SRC (x), 1))
2738 && (GET_RTX_CLASS (GET_CODE (XEXP (SET_SRC (x), 0))) == 'o'
2739 || (GET_CODE (XEXP (SET_SRC (x), 0)) == SUBREG
2740 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (SET_SRC (x), 0))))
2742 return &XEXP (SET_SRC (x), 1);
2744 /* Finally, see if this is a simple operation with its first operand
2745 not in a register. The operation might require this operand in a
2746 register, so return it as a split point. We can always do this
2747 because if the first operand were another operation, we would have
2748 already found it as a split point. */
2749 if ((GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '2'
2750 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == 'c'
2751 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '<'
2752 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '1')
2753 && ! register_operand (XEXP (SET_SRC (x), 0), VOIDmode))
2754 return &XEXP (SET_SRC (x), 0);
2760 /* We write NOR as (and (not A) (not B)), but if we don't have a NOR,
2761 it is better to write this as (not (ior A B)) so we can split it.
2762 Similarly for IOR. */
2763 if (GET_CODE (XEXP (x, 0)) == NOT && GET_CODE (XEXP (x, 1)) == NOT)
2766 gen_rtx_combine (NOT, GET_MODE (x),
2767 gen_rtx_combine (code == IOR ? AND : IOR,
2769 XEXP (XEXP (x, 0), 0),
2770 XEXP (XEXP (x, 1), 0))));
2771 return find_split_point (loc, insn);
2774 /* Many RISC machines have a large set of logical insns. If the
2775 second operand is a NOT, put it first so we will try to split the
2776 other operand first. */
2777 if (GET_CODE (XEXP (x, 1)) == NOT)
2779 rtx tem = XEXP (x, 0);
2780 SUBST (XEXP (x, 0), XEXP (x, 1));
2781 SUBST (XEXP (x, 1), tem);
2786 /* Otherwise, select our actions depending on our rtx class. */
2787 switch (GET_RTX_CLASS (code))
2789 case 'b': /* This is ZERO_EXTRACT and SIGN_EXTRACT. */
2791 split = find_split_point (&XEXP (x, 2), insn);
2794 /* ... fall through ... */
2798 split = find_split_point (&XEXP (x, 1), insn);
2801 /* ... fall through ... */
2803 /* Some machines have (and (shift ...) ...) insns. If X is not
2804 an AND, but XEXP (X, 0) is, use it as our split point. */
2805 if (GET_CODE (x) != AND && GET_CODE (XEXP (x, 0)) == AND)
2806 return &XEXP (x, 0);
2808 split = find_split_point (&XEXP (x, 0), insn);
2814 /* Otherwise, we don't have a split point. */
2818 /* Throughout X, replace FROM with TO, and return the result.
2819 The result is TO if X is FROM;
2820 otherwise the result is X, but its contents may have been modified.
2821 If they were modified, a record was made in undobuf so that
2822 undo_all will (among other things) return X to its original state.
2824 If the number of changes necessary is too much to record to undo,
2825 the excess changes are not made, so the result is invalid.
2826 The changes already made can still be undone.
2827 undobuf.num_undo is incremented for such changes, so by testing that
2828 the caller can tell whether the result is valid.
2830 `n_occurrences' is incremented each time FROM is replaced.
2832 IN_DEST is non-zero if we are processing the SET_DEST of a SET.
2834 UNIQUE_COPY is non-zero if each substitution must be unique. We do this
2835 by copying if `n_occurrences' is non-zero. */
2838 subst (x, from, to, in_dest, unique_copy)
2839 register rtx x, from, to;
2843 register enum rtx_code code = GET_CODE (x);
2844 enum machine_mode op0_mode = VOIDmode;
2846 register int len, i;
2849 /* Two expressions are equal if they are identical copies of a shared
2850 RTX or if they are both registers with the same register number
2853 #define COMBINE_RTX_EQUAL_P(X,Y) \
2855 || (GET_CODE (X) == REG && GET_CODE (Y) == REG \
2856 && REGNO (X) == REGNO (Y) && GET_MODE (X) == GET_MODE (Y)))
2858 if (! in_dest && COMBINE_RTX_EQUAL_P (x, from))
2861 return (unique_copy && n_occurrences > 1 ? copy_rtx (to) : to);
2864 /* If X and FROM are the same register but different modes, they will
2865 not have been seen as equal above. However, flow.c will make a
2866 LOG_LINKS entry for that case. If we do nothing, we will try to
2867 rerecognize our original insn and, when it succeeds, we will
2868 delete the feeding insn, which is incorrect.
2870 So force this insn not to match in this (rare) case. */
2871 if (! in_dest && code == REG && GET_CODE (from) == REG
2872 && REGNO (x) == REGNO (from))
2873 return gen_rtx (CLOBBER, GET_MODE (x), const0_rtx);
2875 /* If this is an object, we are done unless it is a MEM or LO_SUM, both
2876 of which may contain things that can be combined. */
2877 if (code != MEM && code != LO_SUM && GET_RTX_CLASS (code) == 'o')
2880 /* It is possible to have a subexpression appear twice in the insn.
2881 Suppose that FROM is a register that appears within TO.
2882 Then, after that subexpression has been scanned once by `subst',
2883 the second time it is scanned, TO may be found. If we were
2884 to scan TO here, we would find FROM within it and create a
2885 self-referent rtl structure which is completely wrong. */
2886 if (COMBINE_RTX_EQUAL_P (x, to))
2889 len = GET_RTX_LENGTH (code);
2890 fmt = GET_RTX_FORMAT (code);
2892 /* We don't need to process a SET_DEST that is a register, CC0, or PC, so
2893 set up to skip this common case. All other cases where we want to
2894 suppress replacing something inside a SET_SRC are handled via the
2897 && (GET_CODE (SET_DEST (x)) == REG
2898 || GET_CODE (SET_DEST (x)) == CC0
2899 || GET_CODE (SET_DEST (x)) == PC))
2902 /* Get the mode of operand 0 in case X is now a SIGN_EXTEND of a
2905 op0_mode = GET_MODE (XEXP (x, 0));
2907 for (i = 0; i < len; i++)
2912 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
2914 if (COMBINE_RTX_EQUAL_P (XVECEXP (x, i, j), from))
2916 new = (unique_copy && n_occurrences ? copy_rtx (to) : to);
2921 new = subst (XVECEXP (x, i, j), from, to, 0, unique_copy);
2923 /* If this substitution failed, this whole thing fails. */
2924 if (GET_CODE (new) == CLOBBER && XEXP (new, 0) == const0_rtx)
2928 SUBST (XVECEXP (x, i, j), new);
2931 else if (fmt[i] == 'e')
2933 if (COMBINE_RTX_EQUAL_P (XEXP (x, i), from))
2935 /* In general, don't install a subreg involving two modes not
2936 tieable. It can worsen register allocation, and can even
2937 make invalid reload insns, since the reg inside may need to
2938 be copied from in the outside mode, and that may be invalid
2939 if it is an fp reg copied in integer mode.
2941 We allow two exceptions to this: It is valid if it is inside
2942 another SUBREG and the mode of that SUBREG and the mode of
2943 the inside of TO is tieable and it is valid if X is a SET
2944 that copies FROM to CC0. */
2945 if (GET_CODE (to) == SUBREG
2946 && ! MODES_TIEABLE_P (GET_MODE (to),
2947 GET_MODE (SUBREG_REG (to)))
2948 && ! (code == SUBREG
2949 && MODES_TIEABLE_P (GET_MODE (x),
2950 GET_MODE (SUBREG_REG (to))))
2952 && ! (code == SET && i == 1 && XEXP (x, 0) == cc0_rtx)
2955 return gen_rtx (CLOBBER, VOIDmode, const0_rtx);
2957 new = (unique_copy && n_occurrences ? copy_rtx (to) : to);
2961 /* If we are in a SET_DEST, suppress most cases unless we
2962 have gone inside a MEM, in which case we want to
2963 simplify the address. We assume here that things that
2964 are actually part of the destination have their inner
2965 parts in the first expression. This is true for SUBREG,
2966 STRICT_LOW_PART, and ZERO_EXTRACT, which are the only
2967 things aside from REG and MEM that should appear in a
2969 new = subst (XEXP (x, i), from, to,
2971 && (code == SUBREG || code == STRICT_LOW_PART
2972 || code == ZERO_EXTRACT))
2974 && i == 0), unique_copy);
2976 /* If we found that we will have to reject this combination,
2977 indicate that by returning the CLOBBER ourselves, rather than
2978 an expression containing it. This will speed things up as
2979 well as prevent accidents where two CLOBBERs are considered
2980 to be equal, thus producing an incorrect simplification. */
2982 if (GET_CODE (new) == CLOBBER && XEXP (new, 0) == const0_rtx)
2985 SUBST (XEXP (x, i), new);
2989 /* Try to simplify X. If the simplification changed the code, it is likely
2990 that further simplification will help, so loop, but limit the number
2991 of repetitions that will be performed. */
2993 for (i = 0; i < 4; i++)
2995 /* If X is sufficiently simple, don't bother trying to do anything
2997 if (code != CONST_INT && code != REG && code != CLOBBER)
2998 x = simplify_rtx (x, op0_mode, i == 3, in_dest);
3000 if (GET_CODE (x) == code)
3003 code = GET_CODE (x);
3005 /* We no longer know the original mode of operand 0 since we
3006 have changed the form of X) */
3007 op0_mode = VOIDmode;
3013 /* Simplify X, a piece of RTL. We just operate on the expression at the
3014 outer level; call `subst' to simplify recursively. Return the new
3017 OP0_MODE is the original mode of XEXP (x, 0); LAST is nonzero if this
3018 will be the iteration even if an expression with a code different from
3019 X is returned; IN_DEST is nonzero if we are inside a SET_DEST. */
3022 simplify_rtx (x, op0_mode, last, in_dest)
3024 enum machine_mode op0_mode;
3028 enum rtx_code code = GET_CODE (x);
3029 enum machine_mode mode = GET_MODE (x);
3033 /* If this is a commutative operation, put a constant last and a complex
3034 expression first. We don't need to do this for comparisons here. */
3035 if (GET_RTX_CLASS (code) == 'c'
3036 && ((CONSTANT_P (XEXP (x, 0)) && GET_CODE (XEXP (x, 1)) != CONST_INT)
3037 || (GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == 'o'
3038 && GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) != 'o')
3039 || (GET_CODE (XEXP (x, 0)) == SUBREG
3040 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 0)))) == 'o'
3041 && GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) != 'o')))
3044 SUBST (XEXP (x, 0), XEXP (x, 1));
3045 SUBST (XEXP (x, 1), temp);
3048 /* If this is a PLUS, MINUS, or MULT, and the first operand is the
3049 sign extension of a PLUS with a constant, reverse the order of the sign
3050 extension and the addition. Note that this not the same as the original
3051 code, but overflow is undefined for signed values. Also note that the
3052 PLUS will have been partially moved "inside" the sign-extension, so that
3053 the first operand of X will really look like:
3054 (ashiftrt (plus (ashift A C4) C5) C4).
3056 (plus (ashiftrt (ashift A C4) C2) C4)
3057 and replace the first operand of X with that expression. Later parts
3058 of this function may simplify the expression further.
3060 For example, if we start with (mult (sign_extend (plus A C1)) C2),
3061 we swap the SIGN_EXTEND and PLUS. Later code will apply the
3062 distributive law to produce (plus (mult (sign_extend X) C1) C3).
3064 We do this to simplify address expressions. */
3066 if ((code == PLUS || code == MINUS || code == MULT)
3067 && GET_CODE (XEXP (x, 0)) == ASHIFTRT
3068 && GET_CODE (XEXP (XEXP (x, 0), 0)) == PLUS
3069 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == ASHIFT
3070 && GET_CODE (XEXP (XEXP (XEXP (XEXP (x, 0), 0), 0), 1)) == CONST_INT
3071 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3072 && XEXP (XEXP (XEXP (XEXP (x, 0), 0), 0), 1) == XEXP (XEXP (x, 0), 1)
3073 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == CONST_INT
3074 && (temp = simplify_binary_operation (ASHIFTRT, mode,
3075 XEXP (XEXP (XEXP (x, 0), 0), 1),
3076 XEXP (XEXP (x, 0), 1))) != 0)
3079 = simplify_shift_const (NULL_RTX, ASHIFT, mode,
3080 XEXP (XEXP (XEXP (XEXP (x, 0), 0), 0), 0),
3081 INTVAL (XEXP (XEXP (x, 0), 1)));
3083 new = simplify_shift_const (NULL_RTX, ASHIFTRT, mode, new,
3084 INTVAL (XEXP (XEXP (x, 0), 1)));
3086 SUBST (XEXP (x, 0), gen_binary (PLUS, mode, new, temp));
3089 /* If this is a simple operation applied to an IF_THEN_ELSE, try
3090 applying it to the arms of the IF_THEN_ELSE. This often simplifies
3091 things. Check for cases where both arms are testing the same
3094 Don't do anything if all operands are very simple. */
3096 if (((GET_RTX_CLASS (code) == '2' || GET_RTX_CLASS (code) == 'c'
3097 || GET_RTX_CLASS (code) == '<')
3098 && ((GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) != 'o'
3099 && ! (GET_CODE (XEXP (x, 0)) == SUBREG
3100 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 0))))
3102 || (GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) != 'o'
3103 && ! (GET_CODE (XEXP (x, 1)) == SUBREG
3104 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 1))))
3106 || (GET_RTX_CLASS (code) == '1'
3107 && ((GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) != 'o'
3108 && ! (GET_CODE (XEXP (x, 0)) == SUBREG
3109 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 0))))
3112 rtx cond, true, false;
3114 cond = if_then_else_cond (x, &true, &false);
3117 rtx cop1 = const0_rtx;
3118 enum rtx_code cond_code = simplify_comparison (NE, &cond, &cop1);
3120 if (cond_code == NE && GET_RTX_CLASS (GET_CODE (cond)) == '<')
3123 /* Simplify the alternative arms; this may collapse the true and
3124 false arms to store-flag values. */
3125 true = subst (true, pc_rtx, pc_rtx, 0, 0);
3126 false = subst (false, pc_rtx, pc_rtx, 0, 0);
3128 /* Restarting if we generate a store-flag expression will cause
3129 us to loop. Just drop through in this case. */
3131 /* If the result values are STORE_FLAG_VALUE and zero, we can
3132 just make the comparison operation. */
3133 if (true == const_true_rtx && false == const0_rtx)
3134 x = gen_binary (cond_code, mode, cond, cop1);
3135 else if (true == const0_rtx && false == const_true_rtx)
3136 x = gen_binary (reverse_condition (cond_code), mode, cond, cop1);
3138 /* Likewise, we can make the negate of a comparison operation
3139 if the result values are - STORE_FLAG_VALUE and zero. */
3140 else if (GET_CODE (true) == CONST_INT
3141 && INTVAL (true) == - STORE_FLAG_VALUE
3142 && false == const0_rtx)
3143 x = gen_unary (NEG, mode, mode,
3144 gen_binary (cond_code, mode, cond, cop1));
3145 else if (GET_CODE (false) == CONST_INT
3146 && INTVAL (false) == - STORE_FLAG_VALUE
3147 && true == const0_rtx)
3148 x = gen_unary (NEG, mode, mode,
3149 gen_binary (reverse_condition (cond_code),
3152 return gen_rtx (IF_THEN_ELSE, mode,
3153 gen_binary (cond_code, VOIDmode, cond, cop1),
3156 code = GET_CODE (x);
3157 op0_mode = VOIDmode;
3161 /* Try to fold this expression in case we have constants that weren't
3164 switch (GET_RTX_CLASS (code))
3167 temp = simplify_unary_operation (code, mode, XEXP (x, 0), op0_mode);
3170 temp = simplify_relational_operation (code, op0_mode,
3171 XEXP (x, 0), XEXP (x, 1));
3172 #ifdef FLOAT_STORE_FLAG_VALUE
3173 if (temp != 0 && GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
3174 temp = ((temp == const0_rtx) ? CONST0_RTX (GET_MODE (x))
3175 : immed_real_const_1 (FLOAT_STORE_FLAG_VALUE, GET_MODE (x)));
3180 temp = simplify_binary_operation (code, mode, XEXP (x, 0), XEXP (x, 1));
3184 temp = simplify_ternary_operation (code, mode, op0_mode, XEXP (x, 0),
3185 XEXP (x, 1), XEXP (x, 2));
3190 x = temp, code = GET_CODE (temp);
3192 /* First see if we can apply the inverse distributive law. */
3193 if (code == PLUS || code == MINUS
3194 || code == AND || code == IOR || code == XOR)
3196 x = apply_distributive_law (x);
3197 code = GET_CODE (x);
3200 /* If CODE is an associative operation not otherwise handled, see if we
3201 can associate some operands. This can win if they are constants or
3202 if they are logically related (i.e. (a & b) & a. */
3203 if ((code == PLUS || code == MINUS
3204 || code == MULT || code == AND || code == IOR || code == XOR
3205 || code == DIV || code == UDIV
3206 || code == SMAX || code == SMIN || code == UMAX || code == UMIN)
3207 && INTEGRAL_MODE_P (mode))
3209 if (GET_CODE (XEXP (x, 0)) == code)
3211 rtx other = XEXP (XEXP (x, 0), 0);
3212 rtx inner_op0 = XEXP (XEXP (x, 0), 1);
3213 rtx inner_op1 = XEXP (x, 1);
3216 /* Make sure we pass the constant operand if any as the second
3217 one if this is a commutative operation. */
3218 if (CONSTANT_P (inner_op0) && GET_RTX_CLASS (code) == 'c')
3220 rtx tem = inner_op0;
3221 inner_op0 = inner_op1;
3224 inner = simplify_binary_operation (code == MINUS ? PLUS
3225 : code == DIV ? MULT
3226 : code == UDIV ? MULT
3228 mode, inner_op0, inner_op1);
3230 /* For commutative operations, try the other pair if that one
3232 if (inner == 0 && GET_RTX_CLASS (code) == 'c')
3234 other = XEXP (XEXP (x, 0), 1);
3235 inner = simplify_binary_operation (code, mode,
3236 XEXP (XEXP (x, 0), 0),
3241 return gen_binary (code, mode, other, inner);
3245 /* A little bit of algebraic simplification here. */
3249 /* Ensure that our address has any ASHIFTs converted to MULT in case
3250 address-recognizing predicates are called later. */
3251 temp = make_compound_operation (XEXP (x, 0), MEM);
3252 SUBST (XEXP (x, 0), temp);
3256 /* (subreg:A (mem:B X) N) becomes a modified MEM unless the SUBREG
3257 is paradoxical. If we can't do that safely, then it becomes
3258 something nonsensical so that this combination won't take place. */
3260 if (GET_CODE (SUBREG_REG (x)) == MEM
3261 && (GET_MODE_SIZE (mode)
3262 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x)))))
3264 rtx inner = SUBREG_REG (x);
3265 int endian_offset = 0;
3266 /* Don't change the mode of the MEM
3267 if that would change the meaning of the address. */
3268 if (MEM_VOLATILE_P (SUBREG_REG (x))
3269 || mode_dependent_address_p (XEXP (inner, 0)))
3270 return gen_rtx (CLOBBER, mode, const0_rtx);
3272 if (BYTES_BIG_ENDIAN)
3274 if (GET_MODE_SIZE (mode) < UNITS_PER_WORD)
3275 endian_offset += UNITS_PER_WORD - GET_MODE_SIZE (mode);
3276 if (GET_MODE_SIZE (GET_MODE (inner)) < UNITS_PER_WORD)
3277 endian_offset -= (UNITS_PER_WORD
3278 - GET_MODE_SIZE (GET_MODE (inner)));
3280 /* Note if the plus_constant doesn't make a valid address
3281 then this combination won't be accepted. */
3282 x = gen_rtx (MEM, mode,
3283 plus_constant (XEXP (inner, 0),
3284 (SUBREG_WORD (x) * UNITS_PER_WORD
3286 MEM_VOLATILE_P (x) = MEM_VOLATILE_P (inner);
3287 RTX_UNCHANGING_P (x) = RTX_UNCHANGING_P (inner);
3288 MEM_IN_STRUCT_P (x) = MEM_IN_STRUCT_P (inner);
3292 /* If we are in a SET_DEST, these other cases can't apply. */
3296 /* Changing mode twice with SUBREG => just change it once,
3297 or not at all if changing back to starting mode. */
3298 if (GET_CODE (SUBREG_REG (x)) == SUBREG)
3300 if (mode == GET_MODE (SUBREG_REG (SUBREG_REG (x)))
3301 && SUBREG_WORD (x) == 0 && SUBREG_WORD (SUBREG_REG (x)) == 0)
3302 return SUBREG_REG (SUBREG_REG (x));
3304 SUBST_INT (SUBREG_WORD (x),
3305 SUBREG_WORD (x) + SUBREG_WORD (SUBREG_REG (x)));
3306 SUBST (SUBREG_REG (x), SUBREG_REG (SUBREG_REG (x)));
3309 /* SUBREG of a hard register => just change the register number
3310 and/or mode. If the hard register is not valid in that mode,
3311 suppress this combination. If the hard register is the stack,
3312 frame, or argument pointer, leave this as a SUBREG. */
3314 if (GET_CODE (SUBREG_REG (x)) == REG
3315 && REGNO (SUBREG_REG (x)) < FIRST_PSEUDO_REGISTER
3316 && REGNO (SUBREG_REG (x)) != FRAME_POINTER_REGNUM
3317 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
3318 && REGNO (SUBREG_REG (x)) != HARD_FRAME_POINTER_REGNUM
3320 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
3321 && REGNO (SUBREG_REG (x)) != ARG_POINTER_REGNUM
3323 && REGNO (SUBREG_REG (x)) != STACK_POINTER_REGNUM)
3325 if (HARD_REGNO_MODE_OK (REGNO (SUBREG_REG (x)) + SUBREG_WORD (x),
3327 return gen_rtx (REG, mode,
3328 REGNO (SUBREG_REG (x)) + SUBREG_WORD (x));
3330 return gen_rtx (CLOBBER, mode, const0_rtx);
3333 /* For a constant, try to pick up the part we want. Handle a full
3334 word and low-order part. Only do this if we are narrowing
3335 the constant; if it is being widened, we have no idea what
3336 the extra bits will have been set to. */
3338 if (CONSTANT_P (SUBREG_REG (x)) && op0_mode != VOIDmode
3339 && GET_MODE_SIZE (mode) == UNITS_PER_WORD
3340 && GET_MODE_SIZE (op0_mode) < UNITS_PER_WORD
3341 && GET_MODE_CLASS (mode) == MODE_INT)
3343 temp = operand_subword (SUBREG_REG (x), SUBREG_WORD (x),
3349 /* If we want a subreg of a constant, at offset 0,
3350 take the low bits. On a little-endian machine, that's
3351 always valid. On a big-endian machine, it's valid
3352 only if the constant's mode fits in one word. */
3353 if (CONSTANT_P (SUBREG_REG (x)) && subreg_lowpart_p (x)
3354 && GET_MODE_SIZE (mode) <= GET_MODE_SIZE (op0_mode)
3355 && (! WORDS_BIG_ENDIAN
3356 || GET_MODE_BITSIZE (op0_mode) <= BITS_PER_WORD))
3357 return gen_lowpart_for_combine (mode, SUBREG_REG (x));
3359 /* A paradoxical SUBREG of a VOIDmode constant is the same constant,
3360 since we are saying that the high bits don't matter. */
3361 if (CONSTANT_P (SUBREG_REG (x)) && GET_MODE (SUBREG_REG (x)) == VOIDmode
3362 && GET_MODE_SIZE (mode) > GET_MODE_SIZE (op0_mode))
3363 return SUBREG_REG (x);
3365 /* Note that we cannot do any narrowing for non-constants since
3366 we might have been counting on using the fact that some bits were
3367 zero. We now do this in the SET. */
3372 /* (not (plus X -1)) can become (neg X). */
3373 if (GET_CODE (XEXP (x, 0)) == PLUS
3374 && XEXP (XEXP (x, 0), 1) == constm1_rtx)
3375 return gen_rtx_combine (NEG, mode, XEXP (XEXP (x, 0), 0));
3377 /* Similarly, (not (neg X)) is (plus X -1). */
3378 if (GET_CODE (XEXP (x, 0)) == NEG)
3379 return gen_rtx_combine (PLUS, mode, XEXP (XEXP (x, 0), 0),
3382 /* (not (xor X C)) for C constant is (xor X D) with D = ~ C. */
3383 if (GET_CODE (XEXP (x, 0)) == XOR
3384 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3385 && (temp = simplify_unary_operation (NOT, mode,
3386 XEXP (XEXP (x, 0), 1),
3388 return gen_binary (XOR, mode, XEXP (XEXP (x, 0), 0), temp);
3390 /* (not (ashift 1 X)) is (rotate ~1 X). We used to do this for operands
3391 other than 1, but that is not valid. We could do a similar
3392 simplification for (not (lshiftrt C X)) where C is just the sign bit,
3393 but this doesn't seem common enough to bother with. */
3394 if (GET_CODE (XEXP (x, 0)) == ASHIFT
3395 && XEXP (XEXP (x, 0), 0) == const1_rtx)
3396 return gen_rtx (ROTATE, mode, gen_unary (NOT, mode, mode, const1_rtx),
3397 XEXP (XEXP (x, 0), 1));
3399 if (GET_CODE (XEXP (x, 0)) == SUBREG
3400 && subreg_lowpart_p (XEXP (x, 0))
3401 && (GET_MODE_SIZE (GET_MODE (XEXP (x, 0)))
3402 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (x, 0)))))
3403 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == ASHIFT
3404 && XEXP (SUBREG_REG (XEXP (x, 0)), 0) == const1_rtx)
3406 enum machine_mode inner_mode = GET_MODE (SUBREG_REG (XEXP (x, 0)));
3408 x = gen_rtx (ROTATE, inner_mode,
3409 gen_unary (NOT, inner_mode, inner_mode, const1_rtx),
3410 XEXP (SUBREG_REG (XEXP (x, 0)), 1));
3411 return gen_lowpart_for_combine (mode, x);
3414 #if STORE_FLAG_VALUE == -1
3415 /* (not (comparison foo bar)) can be done by reversing the comparison
3417 if (GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
3418 && reversible_comparison_p (XEXP (x, 0)))
3419 return gen_rtx_combine (reverse_condition (GET_CODE (XEXP (x, 0))),
3420 mode, XEXP (XEXP (x, 0), 0),
3421 XEXP (XEXP (x, 0), 1));
3423 /* (ashiftrt foo C) where C is the number of bits in FOO minus 1
3424 is (lt foo (const_int 0)), so we can perform the above
3427 if (XEXP (x, 1) == const1_rtx
3428 && GET_CODE (XEXP (x, 0)) == ASHIFTRT
3429 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3430 && INTVAL (XEXP (XEXP (x, 0), 1)) == GET_MODE_BITSIZE (mode) - 1)
3431 return gen_rtx_combine (GE, mode, XEXP (XEXP (x, 0), 0), const0_rtx);
3434 /* Apply De Morgan's laws to reduce number of patterns for machines
3435 with negating logical insns (and-not, nand, etc.). If result has
3436 only one NOT, put it first, since that is how the patterns are
3439 if (GET_CODE (XEXP (x, 0)) == IOR || GET_CODE (XEXP (x, 0)) == AND)
3441 rtx in1 = XEXP (XEXP (x, 0), 0), in2 = XEXP (XEXP (x, 0), 1);
3443 if (GET_CODE (in1) == NOT)
3444 in1 = XEXP (in1, 0);
3446 in1 = gen_rtx_combine (NOT, GET_MODE (in1), in1);
3448 if (GET_CODE (in2) == NOT)
3449 in2 = XEXP (in2, 0);
3450 else if (GET_CODE (in2) == CONST_INT
3451 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
3452 in2 = GEN_INT (GET_MODE_MASK (mode) & ~ INTVAL (in2));
3454 in2 = gen_rtx_combine (NOT, GET_MODE (in2), in2);
3456 if (GET_CODE (in2) == NOT)
3459 in2 = in1; in1 = tem;
3462 return gen_rtx_combine (GET_CODE (XEXP (x, 0)) == IOR ? AND : IOR,
3468 /* (neg (plus X 1)) can become (not X). */
3469 if (GET_CODE (XEXP (x, 0)) == PLUS
3470 && XEXP (XEXP (x, 0), 1) == const1_rtx)
3471 return gen_rtx_combine (NOT, mode, XEXP (XEXP (x, 0), 0));
3473 /* Similarly, (neg (not X)) is (plus X 1). */
3474 if (GET_CODE (XEXP (x, 0)) == NOT)
3475 return plus_constant (XEXP (XEXP (x, 0), 0), 1);
3477 /* (neg (minus X Y)) can become (minus Y X). */
3478 if (GET_CODE (XEXP (x, 0)) == MINUS
3479 && (! FLOAT_MODE_P (mode)
3480 /* x-y != -(y-x) with IEEE floating point. */
3481 || TARGET_FLOAT_FORMAT != IEEE_FLOAT_FORMAT
3483 return gen_binary (MINUS, mode, XEXP (XEXP (x, 0), 1),
3484 XEXP (XEXP (x, 0), 0));
3486 /* (neg (xor A 1)) is (plus A -1) if A is known to be either 0 or 1. */
3487 if (GET_CODE (XEXP (x, 0)) == XOR && XEXP (XEXP (x, 0), 1) == const1_rtx
3488 && nonzero_bits (XEXP (XEXP (x, 0), 0), mode) == 1)
3489 return gen_binary (PLUS, mode, XEXP (XEXP (x, 0), 0), constm1_rtx);
3491 /* NEG commutes with ASHIFT since it is multiplication. Only do this
3492 if we can then eliminate the NEG (e.g.,
3493 if the operand is a constant). */
3495 if (GET_CODE (XEXP (x, 0)) == ASHIFT)
3497 temp = simplify_unary_operation (NEG, mode,
3498 XEXP (XEXP (x, 0), 0), mode);
3501 SUBST (XEXP (XEXP (x, 0), 0), temp);
3506 temp = expand_compound_operation (XEXP (x, 0));
3508 /* For C equal to the width of MODE minus 1, (neg (ashiftrt X C)) can be
3509 replaced by (lshiftrt X C). This will convert
3510 (neg (sign_extract X 1 Y)) to (zero_extract X 1 Y). */
3512 if (GET_CODE (temp) == ASHIFTRT
3513 && GET_CODE (XEXP (temp, 1)) == CONST_INT
3514 && INTVAL (XEXP (temp, 1)) == GET_MODE_BITSIZE (mode) - 1)
3515 return simplify_shift_const (temp, LSHIFTRT, mode, XEXP (temp, 0),
3516 INTVAL (XEXP (temp, 1)));
3518 /* If X has only a single bit that might be nonzero, say, bit I, convert
3519 (neg X) to (ashiftrt (ashift X C-I) C-I) where C is the bitsize of
3520 MODE minus 1. This will convert (neg (zero_extract X 1 Y)) to
3521 (sign_extract X 1 Y). But only do this if TEMP isn't a register
3522 or a SUBREG of one since we'd be making the expression more
3523 complex if it was just a register. */
3525 if (GET_CODE (temp) != REG
3526 && ! (GET_CODE (temp) == SUBREG
3527 && GET_CODE (SUBREG_REG (temp)) == REG)
3528 && (i = exact_log2 (nonzero_bits (temp, mode))) >= 0)
3530 rtx temp1 = simplify_shift_const
3531 (NULL_RTX, ASHIFTRT, mode,
3532 simplify_shift_const (NULL_RTX, ASHIFT, mode, temp,
3533 GET_MODE_BITSIZE (mode) - 1 - i),
3534 GET_MODE_BITSIZE (mode) - 1 - i);
3536 /* If all we did was surround TEMP with the two shifts, we
3537 haven't improved anything, so don't use it. Otherwise,
3538 we are better off with TEMP1. */
3539 if (GET_CODE (temp1) != ASHIFTRT
3540 || GET_CODE (XEXP (temp1, 0)) != ASHIFT
3541 || XEXP (XEXP (temp1, 0), 0) != temp)
3547 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
3549 force_to_mode (XEXP (x, 0), GET_MODE (XEXP (x, 0)),
3550 GET_MODE_MASK (mode), NULL_RTX, 0));
3552 /* (truncate:SI ({sign,zero}_extend:DI foo:SI)) == foo:SI. */
3553 if ((GET_CODE (XEXP (x, 0)) == SIGN_EXTEND
3554 || GET_CODE (XEXP (x, 0)) == ZERO_EXTEND)
3555 && GET_MODE (XEXP (XEXP (x, 0), 0)) == mode)
3556 return XEXP (XEXP (x, 0), 0);
3558 /* (truncate:SI (OP:DI ({sign,zero}_extend:DI foo:SI))) is
3559 (OP:SI foo:SI) if OP is NEG or ABS. */
3560 if ((GET_CODE (XEXP (x, 0)) == ABS
3561 || GET_CODE (XEXP (x, 0)) == NEG)
3562 && (GET_CODE (XEXP (XEXP (x, 0), 0)) == SIGN_EXTEND
3563 || GET_CODE (XEXP (XEXP (x, 0), 0)) == ZERO_EXTEND)
3564 && GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == mode)
3565 return gen_unary (GET_CODE (XEXP (x, 0)), mode, mode,
3566 XEXP (XEXP (XEXP (x, 0), 0), 0));
3568 /* (truncate:SI (subreg:DI (truncate:SI X) 0)) is
3570 if (GET_CODE (XEXP (x, 0)) == SUBREG
3571 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == TRUNCATE
3572 && subreg_lowpart_p (XEXP (x, 0)))
3573 return SUBREG_REG (XEXP (x, 0));
3575 /* If we know that the value is already truncated, we can
3576 replace the TRUNCATE with a SUBREG. */
3577 if (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) <= HOST_BITS_PER_WIDE_INT
3578 && (nonzero_bits (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
3579 &~ GET_MODE_MASK (mode)) == 0)
3580 return gen_lowpart_for_combine (mode, XEXP (x, 0));
3582 /* A truncate of a comparison can be replaced with a subreg if
3583 STORE_FLAG_VALUE permits. This is like the previous test,
3584 but it works even if the comparison is done in a mode larger
3585 than HOST_BITS_PER_WIDE_INT. */
3586 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
3587 && GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
3588 && ((HOST_WIDE_INT) STORE_FLAG_VALUE &~ GET_MODE_MASK (mode)) == 0)
3589 return gen_lowpart_for_combine (mode, XEXP (x, 0));
3591 /* Similarly, a truncate of a register whose value is a
3592 comparison can be replaced with a subreg if STORE_FLAG_VALUE
3594 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
3595 && ((HOST_WIDE_INT) STORE_FLAG_VALUE &~ GET_MODE_MASK (mode)) == 0
3596 && (temp = get_last_value (XEXP (x, 0)))
3597 && GET_RTX_CLASS (GET_CODE (temp)) == '<')
3598 return gen_lowpart_for_combine (mode, XEXP (x, 0));
3602 case FLOAT_TRUNCATE:
3603 /* (float_truncate:SF (float_extend:DF foo:SF)) = foo:SF. */
3604 if (GET_CODE (XEXP (x, 0)) == FLOAT_EXTEND
3605 && GET_MODE (XEXP (XEXP (x, 0), 0)) == mode)
3606 return XEXP (XEXP (x, 0), 0);
3608 /* (float_truncate:SF (OP:DF (float_extend:DF foo:sf))) is
3609 (OP:SF foo:SF) if OP is NEG or ABS. */
3610 if ((GET_CODE (XEXP (x, 0)) == ABS
3611 || GET_CODE (XEXP (x, 0)) == NEG)
3612 && GET_CODE (XEXP (XEXP (x, 0), 0)) == FLOAT_EXTEND
3613 && GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == mode)
3614 return gen_unary (GET_CODE (XEXP (x, 0)), mode, mode,
3615 XEXP (XEXP (XEXP (x, 0), 0), 0));
3617 /* (float_truncate:SF (subreg:DF (float_truncate:SF X) 0))
3618 is (float_truncate:SF x). */
3619 if (GET_CODE (XEXP (x, 0)) == SUBREG
3620 && subreg_lowpart_p (XEXP (x, 0))
3621 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == FLOAT_TRUNCATE)
3622 return SUBREG_REG (XEXP (x, 0));
3627 /* Convert (compare FOO (const_int 0)) to FOO unless we aren't
3628 using cc0, in which case we want to leave it as a COMPARE
3629 so we can distinguish it from a register-register-copy. */
3630 if (XEXP (x, 1) == const0_rtx)
3633 /* In IEEE floating point, x-0 is not the same as x. */
3634 if ((TARGET_FLOAT_FORMAT != IEEE_FLOAT_FORMAT
3635 || ! FLOAT_MODE_P (GET_MODE (XEXP (x, 0)))
3637 && XEXP (x, 1) == CONST0_RTX (GET_MODE (XEXP (x, 0))))
3643 /* (const (const X)) can become (const X). Do it this way rather than
3644 returning the inner CONST since CONST can be shared with a
3646 if (GET_CODE (XEXP (x, 0)) == CONST)
3647 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
3652 /* Convert (lo_sum (high FOO) FOO) to FOO. This is necessary so we
3653 can add in an offset. find_split_point will split this address up
3654 again if it doesn't match. */
3655 if (GET_CODE (XEXP (x, 0)) == HIGH
3656 && rtx_equal_p (XEXP (XEXP (x, 0), 0), XEXP (x, 1)))
3662 /* If we have (plus (plus (A const) B)), associate it so that CONST is
3663 outermost. That's because that's the way indexed addresses are
3664 supposed to appear. This code used to check many more cases, but
3665 they are now checked elsewhere. */
3666 if (GET_CODE (XEXP (x, 0)) == PLUS
3667 && CONSTANT_ADDRESS_P (XEXP (XEXP (x, 0), 1)))
3668 return gen_binary (PLUS, mode,
3669 gen_binary (PLUS, mode, XEXP (XEXP (x, 0), 0),
3671 XEXP (XEXP (x, 0), 1));
3673 /* (plus (xor (and <foo> (const_int pow2 - 1)) <c>) <-c>)
3674 when c is (const_int (pow2 + 1) / 2) is a sign extension of a
3675 bit-field and can be replaced by either a sign_extend or a
3676 sign_extract. The `and' may be a zero_extend. */
3677 if (GET_CODE (XEXP (x, 0)) == XOR
3678 && GET_CODE (XEXP (x, 1)) == CONST_INT
3679 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3680 && INTVAL (XEXP (x, 1)) == - INTVAL (XEXP (XEXP (x, 0), 1))
3681 && (i = exact_log2 (INTVAL (XEXP (XEXP (x, 0), 1)))) >= 0
3682 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
3683 && ((GET_CODE (XEXP (XEXP (x, 0), 0)) == AND
3684 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == CONST_INT
3685 && (INTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1))
3686 == ((HOST_WIDE_INT) 1 << (i + 1)) - 1))
3687 || (GET_CODE (XEXP (XEXP (x, 0), 0)) == ZERO_EXTEND
3688 && (GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)))
3690 return simplify_shift_const
3691 (NULL_RTX, ASHIFTRT, mode,
3692 simplify_shift_const (NULL_RTX, ASHIFT, mode,
3693 XEXP (XEXP (XEXP (x, 0), 0), 0),
3694 GET_MODE_BITSIZE (mode) - (i + 1)),
3695 GET_MODE_BITSIZE (mode) - (i + 1));
3697 /* (plus (comparison A B) C) can become (neg (rev-comp A B)) if
3698 C is 1 and STORE_FLAG_VALUE is -1 or if C is -1 and STORE_FLAG_VALUE
3699 is 1. This produces better code than the alternative immediately
3701 if (GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
3702 && reversible_comparison_p (XEXP (x, 0))
3703 && ((STORE_FLAG_VALUE == -1 && XEXP (x, 1) == const1_rtx)
3704 || (STORE_FLAG_VALUE == 1 && XEXP (x, 1) == constm1_rtx)))
3706 gen_unary (NEG, mode, mode,
3707 gen_binary (reverse_condition (GET_CODE (XEXP (x, 0))),
3708 mode, XEXP (XEXP (x, 0), 0),
3709 XEXP (XEXP (x, 0), 1)));
3711 /* If only the low-order bit of X is possibly nonzero, (plus x -1)
3712 can become (ashiftrt (ashift (xor x 1) C) C) where C is
3713 the bitsize of the mode - 1. This allows simplification of
3714 "a = (b & 8) == 0;" */
3715 if (XEXP (x, 1) == constm1_rtx
3716 && GET_CODE (XEXP (x, 0)) != REG
3717 && ! (GET_CODE (XEXP (x,0)) == SUBREG
3718 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == REG)
3719 && nonzero_bits (XEXP (x, 0), mode) == 1)
3720 return simplify_shift_const (NULL_RTX, ASHIFTRT, mode,
3721 simplify_shift_const (NULL_RTX, ASHIFT, mode,
3722 gen_rtx_combine (XOR, mode,
3723 XEXP (x, 0), const1_rtx),
3724 GET_MODE_BITSIZE (mode) - 1),
3725 GET_MODE_BITSIZE (mode) - 1);
3727 /* If we are adding two things that have no bits in common, convert
3728 the addition into an IOR. This will often be further simplified,
3729 for example in cases like ((a & 1) + (a & 2)), which can
3732 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
3733 && (nonzero_bits (XEXP (x, 0), mode)
3734 & nonzero_bits (XEXP (x, 1), mode)) == 0)
3735 return gen_binary (IOR, mode, XEXP (x, 0), XEXP (x, 1));
3739 #if STORE_FLAG_VALUE == 1
3740 /* (minus 1 (comparison foo bar)) can be done by reversing the comparison
3742 if (XEXP (x, 0) == const1_rtx
3743 && GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) == '<'
3744 && reversible_comparison_p (XEXP (x, 1)))
3745 return gen_binary (reverse_condition (GET_CODE (XEXP (x, 1))),
3746 mode, XEXP (XEXP (x, 1), 0),
3747 XEXP (XEXP (x, 1), 1));
3750 /* (minus <foo> (and <foo> (const_int -pow2))) becomes
3751 (and <foo> (const_int pow2-1)) */
3752 if (GET_CODE (XEXP (x, 1)) == AND
3753 && GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT
3754 && exact_log2 (- INTVAL (XEXP (XEXP (x, 1), 1))) >= 0
3755 && rtx_equal_p (XEXP (XEXP (x, 1), 0), XEXP (x, 0)))
3756 return simplify_and_const_int (NULL_RTX, mode, XEXP (x, 0),
3757 - INTVAL (XEXP (XEXP (x, 1), 1)) - 1);
3759 /* Canonicalize (minus A (plus B C)) to (minus (minus A B) C) for
3761 if (GET_CODE (XEXP (x, 1)) == PLUS && INTEGRAL_MODE_P (mode))
3762 return gen_binary (MINUS, mode,
3763 gen_binary (MINUS, mode, XEXP (x, 0),
3764 XEXP (XEXP (x, 1), 0)),
3765 XEXP (XEXP (x, 1), 1));
3769 /* If we have (mult (plus A B) C), apply the distributive law and then
3770 the inverse distributive law to see if things simplify. This
3771 occurs mostly in addresses, often when unrolling loops. */
3773 if (GET_CODE (XEXP (x, 0)) == PLUS)
3775 x = apply_distributive_law
3776 (gen_binary (PLUS, mode,
3777 gen_binary (MULT, mode,
3778 XEXP (XEXP (x, 0), 0), XEXP (x, 1)),
3779 gen_binary (MULT, mode,
3780 XEXP (XEXP (x, 0), 1), XEXP (x, 1))));
3782 if (GET_CODE (x) != MULT)
3788 /* If this is a divide by a power of two, treat it as a shift if
3789 its first operand is a shift. */
3790 if (GET_CODE (XEXP (x, 1)) == CONST_INT
3791 && (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0
3792 && (GET_CODE (XEXP (x, 0)) == ASHIFT
3793 || GET_CODE (XEXP (x, 0)) == LSHIFTRT
3794 || GET_CODE (XEXP (x, 0)) == ASHIFTRT
3795 || GET_CODE (XEXP (x, 0)) == ROTATE
3796 || GET_CODE (XEXP (x, 0)) == ROTATERT))
3797 return simplify_shift_const (NULL_RTX, LSHIFTRT, mode, XEXP (x, 0), i);
3801 case GT: case GTU: case GE: case GEU:
3802 case LT: case LTU: case LE: case LEU:
3803 /* If the first operand is a condition code, we can't do anything
3805 if (GET_CODE (XEXP (x, 0)) == COMPARE
3806 || (GET_MODE_CLASS (GET_MODE (XEXP (x, 0))) != MODE_CC
3808 && XEXP (x, 0) != cc0_rtx
3812 rtx op0 = XEXP (x, 0);
3813 rtx op1 = XEXP (x, 1);
3814 enum rtx_code new_code;
3816 if (GET_CODE (op0) == COMPARE)
3817 op1 = XEXP (op0, 1), op0 = XEXP (op0, 0);
3819 /* Simplify our comparison, if possible. */
3820 new_code = simplify_comparison (code, &op0, &op1);
3822 #if STORE_FLAG_VALUE == 1
3823 /* If STORE_FLAG_VALUE is 1, we can convert (ne x 0) to simply X
3824 if only the low-order bit is possibly nonzero in X (such as when
3825 X is a ZERO_EXTRACT of one bit). Similarly, we can convert EQ to
3826 (xor X 1) or (minus 1 X); we use the former. Finally, if X is
3827 known to be either 0 or -1, NE becomes a NEG and EQ becomes
3830 Remove any ZERO_EXTRACT we made when thinking this was a
3831 comparison. It may now be simpler to use, e.g., an AND. If a
3832 ZERO_EXTRACT is indeed appropriate, it will be placed back by
3833 the call to make_compound_operation in the SET case. */
3835 if (new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
3836 && op1 == const0_rtx
3837 && nonzero_bits (op0, mode) == 1)
3838 return gen_lowpart_for_combine (mode,
3839 expand_compound_operation (op0));
3841 else if (new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
3842 && op1 == const0_rtx
3843 && (num_sign_bit_copies (op0, mode)
3844 == GET_MODE_BITSIZE (mode)))
3846 op0 = expand_compound_operation (op0);
3847 return gen_unary (NEG, mode, mode,
3848 gen_lowpart_for_combine (mode, op0));
3851 else if (new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
3852 && op1 == const0_rtx
3853 && nonzero_bits (op0, mode) == 1)
3855 op0 = expand_compound_operation (op0);
3856 return gen_binary (XOR, mode,
3857 gen_lowpart_for_combine (mode, op0),
3861 else if (new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
3862 && op1 == const0_rtx
3863 && (num_sign_bit_copies (op0, mode)
3864 == GET_MODE_BITSIZE (mode)))
3866 op0 = expand_compound_operation (op0);
3867 return plus_constant (gen_lowpart_for_combine (mode, op0), 1);
3871 #if STORE_FLAG_VALUE == -1
3872 /* If STORE_FLAG_VALUE is -1, we have cases similar to
3874 if (new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
3875 && op1 == const0_rtx
3876 && (num_sign_bit_copies (op0, mode)
3877 == GET_MODE_BITSIZE (mode)))
3878 return gen_lowpart_for_combine (mode,
3879 expand_compound_operation (op0));
3881 else if (new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
3882 && op1 == const0_rtx
3883 && nonzero_bits (op0, mode) == 1)
3885 op0 = expand_compound_operation (op0);
3886 return gen_unary (NEG, mode, mode,
3887 gen_lowpart_for_combine (mode, op0));
3890 else if (new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
3891 && op1 == const0_rtx
3892 && (num_sign_bit_copies (op0, mode)
3893 == GET_MODE_BITSIZE (mode)))
3895 op0 = expand_compound_operation (op0);
3896 return gen_unary (NOT, mode, mode,
3897 gen_lowpart_for_combine (mode, op0));
3900 /* If X is 0/1, (eq X 0) is X-1. */
3901 else if (new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
3902 && op1 == const0_rtx
3903 && nonzero_bits (op0, mode) == 1)
3905 op0 = expand_compound_operation (op0);
3906 return plus_constant (gen_lowpart_for_combine (mode, op0), -1);
3910 /* If STORE_FLAG_VALUE says to just test the sign bit and X has just
3911 one bit that might be nonzero, we can convert (ne x 0) to
3912 (ashift x c) where C puts the bit in the sign bit. Remove any
3913 AND with STORE_FLAG_VALUE when we are done, since we are only
3914 going to test the sign bit. */
3915 if (new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
3916 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
3917 && (STORE_FLAG_VALUE
3918 == (HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (mode) - 1))
3919 && op1 == const0_rtx
3920 && mode == GET_MODE (op0)
3921 && (i = exact_log2 (nonzero_bits (op0, mode))) >= 0)
3923 x = simplify_shift_const (NULL_RTX, ASHIFT, mode,
3924 expand_compound_operation (op0),
3925 GET_MODE_BITSIZE (mode) - 1 - i);
3926 if (GET_CODE (x) == AND && XEXP (x, 1) == const_true_rtx)
3932 /* If the code changed, return a whole new comparison. */
3933 if (new_code != code)
3934 return gen_rtx_combine (new_code, mode, op0, op1);
3936 /* Otherwise, keep this operation, but maybe change its operands.
3937 This also converts (ne (compare FOO BAR) 0) to (ne FOO BAR). */
3938 SUBST (XEXP (x, 0), op0);
3939 SUBST (XEXP (x, 1), op1);
3944 return simplify_if_then_else (x);
3950 /* If we are processing SET_DEST, we are done. */
3954 return expand_compound_operation (x);
3957 return simplify_set (x);
3962 return simplify_logical (x, last);
3965 /* (abs (neg <foo>)) -> (abs <foo>) */
3966 if (GET_CODE (XEXP (x, 0)) == NEG)
3967 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
3969 /* If operand is something known to be positive, ignore the ABS. */
3970 if (GET_CODE (XEXP (x, 0)) == FFS || GET_CODE (XEXP (x, 0)) == ABS
3971 || ((GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
3972 <= HOST_BITS_PER_WIDE_INT)
3973 && ((nonzero_bits (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
3974 & ((HOST_WIDE_INT) 1
3975 << (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - 1)))
3980 /* If operand is known to be only -1 or 0, convert ABS to NEG. */
3981 if (num_sign_bit_copies (XEXP (x, 0), mode) == GET_MODE_BITSIZE (mode))
3982 return gen_rtx_combine (NEG, mode, XEXP (x, 0));
3987 /* (ffs (*_extend <X>)) = (ffs <X>) */
3988 if (GET_CODE (XEXP (x, 0)) == SIGN_EXTEND
3989 || GET_CODE (XEXP (x, 0)) == ZERO_EXTEND)
3990 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
3994 /* (float (sign_extend <X>)) = (float <X>). */
3995 if (GET_CODE (XEXP (x, 0)) == SIGN_EXTEND)
3996 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4004 /* If this is a shift by a constant amount, simplify it. */
4005 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
4006 return simplify_shift_const (x, code, mode, XEXP (x, 0),
4007 INTVAL (XEXP (x, 1)));
4009 #ifdef SHIFT_COUNT_TRUNCATED
4010 else if (SHIFT_COUNT_TRUNCATED && GET_CODE (XEXP (x, 1)) != REG)
4012 force_to_mode (XEXP (x, 1), GET_MODE (x),
4014 << exact_log2 (GET_MODE_BITSIZE (GET_MODE (x))))
4025 /* Simplify X, an IF_THEN_ELSE expression. Return the new expression. */
4028 simplify_if_then_else (x)
4031 enum machine_mode mode = GET_MODE (x);
4032 rtx cond = XEXP (x, 0);
4033 rtx true = XEXP (x, 1);
4034 rtx false = XEXP (x, 2);
4035 enum rtx_code true_code = GET_CODE (cond);
4036 int comparison_p = GET_RTX_CLASS (true_code) == '<';
4040 /* Simplify storing of the truth value. */
4041 if (comparison_p && true == const_true_rtx && false == const0_rtx)
4042 return gen_binary (true_code, mode, XEXP (cond, 0), XEXP (cond, 1));
4044 /* Also when the truth value has to be reversed. */
4045 if (comparison_p && reversible_comparison_p (cond)
4046 && true == const0_rtx && false == const_true_rtx)
4047 return gen_binary (reverse_condition (true_code),
4048 mode, XEXP (cond, 0), XEXP (cond, 1));
4050 /* Sometimes we can simplify the arm of an IF_THEN_ELSE if a register used
4051 in it is being compared against certain values. Get the true and false
4052 comparisons and see if that says anything about the value of each arm. */
4054 if (comparison_p && reversible_comparison_p (cond)
4055 && GET_CODE (XEXP (cond, 0)) == REG)
4058 rtx from = XEXP (cond, 0);
4059 enum rtx_code false_code = reverse_condition (true_code);
4060 rtx true_val = XEXP (cond, 1);
4061 rtx false_val = true_val;
4064 /* If FALSE_CODE is EQ, swap the codes and arms. */
4066 if (false_code == EQ)
4068 swapped = 1, true_code = EQ, false_code = NE;
4069 temp = true, true = false, false = temp;
4072 /* If we are comparing against zero and the expression being tested has
4073 only a single bit that might be nonzero, that is its value when it is
4074 not equal to zero. Similarly if it is known to be -1 or 0. */
4076 if (true_code == EQ && true_val == const0_rtx
4077 && exact_log2 (nzb = nonzero_bits (from, GET_MODE (from))) >= 0)
4078 false_code = EQ, false_val = GEN_INT (nzb);
4079 else if (true_code == EQ && true_val == const0_rtx
4080 && (num_sign_bit_copies (from, GET_MODE (from))
4081 == GET_MODE_BITSIZE (GET_MODE (from))))
4082 false_code = EQ, false_val = constm1_rtx;
4084 /* Now simplify an arm if we know the value of the register in the
4085 branch and it is used in the arm. Be careful due to the potential
4086 of locally-shared RTL. */
4088 if (reg_mentioned_p (from, true))
4089 true = subst (known_cond (copy_rtx (true), true_code, from, true_val),
4090 pc_rtx, pc_rtx, 0, 0);
4091 if (reg_mentioned_p (from, false))
4092 false = subst (known_cond (copy_rtx (false), false_code,
4094 pc_rtx, pc_rtx, 0, 0);
4096 SUBST (XEXP (x, 1), swapped ? false : true);
4097 SUBST (XEXP (x, 2), swapped ? true : false);
4099 true = XEXP (x, 1), false = XEXP (x, 2), true_code = GET_CODE (cond);
4102 /* If we have (if_then_else FOO (pc) (label_ref BAR)) and FOO can be
4103 reversed, do so to avoid needing two sets of patterns for
4104 subtract-and-branch insns. Similarly if we have a constant in the true
4105 arm, the false arm is the same as the first operand of the comparison, or
4106 the false arm is more complicated than the true arm. */
4108 if (comparison_p && reversible_comparison_p (cond)
4110 || (CONSTANT_P (true)
4111 && GET_CODE (false) != CONST_INT && false != pc_rtx)
4112 || true == const0_rtx
4113 || (GET_RTX_CLASS (GET_CODE (true)) == 'o'
4114 && GET_RTX_CLASS (GET_CODE (false)) != 'o')
4115 || (GET_CODE (true) == SUBREG
4116 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (true))) == 'o'
4117 && GET_RTX_CLASS (GET_CODE (false)) != 'o')
4118 || reg_mentioned_p (true, false)
4119 || rtx_equal_p (false, XEXP (cond, 0))))
4121 true_code = reverse_condition (true_code);
4123 gen_binary (true_code, GET_MODE (cond), XEXP (cond, 0),
4126 SUBST (XEXP (x, 1), false);
4127 SUBST (XEXP (x, 2), true);
4129 temp = true, true = false, false = temp, cond = XEXP (x, 0);
4131 /* It is possible that the conditional has been simplified out. */
4132 true_code = GET_CODE (cond);
4133 comparison_p = GET_RTX_CLASS (true_code) == '<';
4136 /* If the two arms are identical, we don't need the comparison. */
4138 if (rtx_equal_p (true, false) && ! side_effects_p (cond))
4141 /* Convert a == b ? b : a to "a". */
4142 if (true_code == EQ && ! side_effects_p (cond)
4143 && rtx_equal_p (XEXP (cond, 0), false)
4144 && rtx_equal_p (XEXP (cond, 1), true))
4146 else if (true_code == NE && ! side_effects_p (cond)
4147 && rtx_equal_p (XEXP (cond, 0), true)
4148 && rtx_equal_p (XEXP (cond, 1), false))
4151 /* Look for cases where we have (abs x) or (neg (abs X)). */
4153 if (GET_MODE_CLASS (mode) == MODE_INT
4154 && GET_CODE (false) == NEG
4155 && rtx_equal_p (true, XEXP (false, 0))
4157 && rtx_equal_p (true, XEXP (cond, 0))
4158 && ! side_effects_p (true))
4163 return gen_unary (ABS, mode, mode, true);
4166 return gen_unary (NEG, mode, mode, gen_unary (ABS, mode, mode, true));
4169 /* Look for MIN or MAX. */
4171 if ((! FLOAT_MODE_P (mode) || flag_fast_math)
4173 && rtx_equal_p (XEXP (cond, 0), true)
4174 && rtx_equal_p (XEXP (cond, 1), false)
4175 && ! side_effects_p (cond))
4180 return gen_binary (SMAX, mode, true, false);
4183 return gen_binary (SMIN, mode, true, false);
4186 return gen_binary (UMAX, mode, true, false);
4189 return gen_binary (UMIN, mode, true, false);
4192 #if STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1
4194 /* If we have (if_then_else COND (OP Z C1) Z) and OP is an identity when its
4195 second operand is zero, this can be done as (OP Z (mult COND C2)) where
4196 C2 = C1 * STORE_FLAG_VALUE. Similarly if OP has an outer ZERO_EXTEND or
4197 SIGN_EXTEND as long as Z is already extended (so we don't destroy it).
4198 We can do this kind of thing in some cases when STORE_FLAG_VALUE is
4199 neither of the above, but it isn't worth checking for. */
4201 if (comparison_p && mode != VOIDmode && ! side_effects_p (x))
4203 rtx t = make_compound_operation (true, SET);
4204 rtx f = make_compound_operation (false, SET);
4205 rtx cond_op0 = XEXP (cond, 0);
4206 rtx cond_op1 = XEXP (cond, 1);
4207 enum rtx_code op, extend_op = NIL;
4208 enum machine_mode m = mode;
4211 if ((GET_CODE (t) == PLUS || GET_CODE (t) == MINUS
4212 || GET_CODE (t) == IOR || GET_CODE (t) == XOR
4213 || GET_CODE (t) == ASHIFT
4214 || GET_CODE (t) == LSHIFTRT || GET_CODE (t) == ASHIFTRT)
4215 && rtx_equal_p (XEXP (t, 0), f))
4216 c1 = XEXP (t, 1), op = GET_CODE (t), z = f;
4218 /* If an identity-zero op is commutative, check whether there
4219 would be a match if we swapped the operands. */
4220 else if ((GET_CODE (t) == PLUS || GET_CODE (t) == IOR
4221 || GET_CODE (t) == XOR)
4222 && rtx_equal_p (XEXP (t, 1), f))
4223 c1 = XEXP (t, 0), op = GET_CODE (t), z = f;
4224 else if (GET_CODE (t) == SIGN_EXTEND
4225 && (GET_CODE (XEXP (t, 0)) == PLUS
4226 || GET_CODE (XEXP (t, 0)) == MINUS
4227 || GET_CODE (XEXP (t, 0)) == IOR
4228 || GET_CODE (XEXP (t, 0)) == XOR
4229 || GET_CODE (XEXP (t, 0)) == ASHIFT
4230 || GET_CODE (XEXP (t, 0)) == LSHIFTRT
4231 || GET_CODE (XEXP (t, 0)) == ASHIFTRT)
4232 && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG
4233 && subreg_lowpart_p (XEXP (XEXP (t, 0), 0))
4234 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f)
4235 && (num_sign_bit_copies (f, GET_MODE (f))
4236 > (GET_MODE_BITSIZE (mode)
4237 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t, 0), 0))))))
4239 c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0));
4240 extend_op = SIGN_EXTEND;
4241 m = GET_MODE (XEXP (t, 0));
4243 else if (GET_CODE (t) == SIGN_EXTEND
4244 && (GET_CODE (XEXP (t, 0)) == PLUS
4245 || GET_CODE (XEXP (t, 0)) == IOR
4246 || GET_CODE (XEXP (t, 0)) == XOR)
4247 && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG
4248 && subreg_lowpart_p (XEXP (XEXP (t, 0), 1))
4249 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f)
4250 && (num_sign_bit_copies (f, GET_MODE (f))
4251 > (GET_MODE_BITSIZE (mode)
4252 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t, 0), 1))))))
4254 c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0));
4255 extend_op = SIGN_EXTEND;
4256 m = GET_MODE (XEXP (t, 0));
4258 else if (GET_CODE (t) == ZERO_EXTEND
4259 && (GET_CODE (XEXP (t, 0)) == PLUS
4260 || GET_CODE (XEXP (t, 0)) == MINUS
4261 || GET_CODE (XEXP (t, 0)) == IOR
4262 || GET_CODE (XEXP (t, 0)) == XOR
4263 || GET_CODE (XEXP (t, 0)) == ASHIFT
4264 || GET_CODE (XEXP (t, 0)) == LSHIFTRT
4265 || GET_CODE (XEXP (t, 0)) == ASHIFTRT)
4266 && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG
4267 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4268 && subreg_lowpart_p (XEXP (XEXP (t, 0), 0))
4269 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f)
4270 && ((nonzero_bits (f, GET_MODE (f))
4271 & ~ GET_MODE_MASK (GET_MODE (XEXP (XEXP (t, 0), 0))))
4274 c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0));
4275 extend_op = ZERO_EXTEND;
4276 m = GET_MODE (XEXP (t, 0));
4278 else if (GET_CODE (t) == ZERO_EXTEND
4279 && (GET_CODE (XEXP (t, 0)) == PLUS
4280 || GET_CODE (XEXP (t, 0)) == IOR
4281 || GET_CODE (XEXP (t, 0)) == XOR)
4282 && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG
4283 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4284 && subreg_lowpart_p (XEXP (XEXP (t, 0), 1))
4285 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f)
4286 && ((nonzero_bits (f, GET_MODE (f))
4287 & ~ GET_MODE_MASK (GET_MODE (XEXP (XEXP (t, 0), 1))))
4290 c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0));
4291 extend_op = ZERO_EXTEND;
4292 m = GET_MODE (XEXP (t, 0));
4297 temp = subst (gen_binary (true_code, m, cond_op0, cond_op1),
4298 pc_rtx, pc_rtx, 0, 0);
4299 temp = gen_binary (MULT, m, temp,
4300 gen_binary (MULT, m, c1, const_true_rtx));
4301 temp = subst (temp, pc_rtx, pc_rtx, 0, 0);
4302 temp = gen_binary (op, m, gen_lowpart_for_combine (m, z), temp);
4304 if (extend_op != NIL)
4305 temp = gen_unary (extend_op, mode, m, temp);
4312 /* If we have (if_then_else (ne A 0) C1 0) and either A is known to be 0 or
4313 1 and C1 is a single bit or A is known to be 0 or -1 and C1 is the
4314 negation of a single bit, we can convert this operation to a shift. We
4315 can actually do this more generally, but it doesn't seem worth it. */
4317 if (true_code == NE && XEXP (cond, 1) == const0_rtx
4318 && false == const0_rtx && GET_CODE (true) == CONST_INT
4319 && ((1 == nonzero_bits (XEXP (cond, 0), mode)
4320 && (i = exact_log2 (INTVAL (true))) >= 0)
4321 || ((num_sign_bit_copies (XEXP (cond, 0), mode)
4322 == GET_MODE_BITSIZE (mode))
4323 && (i = exact_log2 (- INTVAL (true))) >= 0)))
4325 simplify_shift_const (NULL_RTX, ASHIFT, mode,
4326 gen_lowpart_for_combine (mode, XEXP (cond, 0)), i);
4331 /* Simplify X, a SET expression. Return the new expression. */
4337 rtx src = SET_SRC (x);
4338 rtx dest = SET_DEST (x);
4339 enum machine_mode mode
4340 = GET_MODE (src) != VOIDmode ? GET_MODE (src) : GET_MODE (dest);
4344 /* (set (pc) (return)) gets written as (return). */
4345 if (GET_CODE (dest) == PC && GET_CODE (src) == RETURN)
4348 /* Now that we know for sure which bits of SRC we are using, see if we can
4349 simplify the expression for the object knowing that we only need the
4352 if (GET_MODE_CLASS (mode) == MODE_INT)
4353 src = force_to_mode (src, mode, GET_MODE_MASK (mode), NULL_RTX, 0);
4355 /* If we are setting CC0 or if the source is a COMPARE, look for the use of
4356 the comparison result and try to simplify it unless we already have used
4357 undobuf.other_insn. */
4358 if ((GET_CODE (src) == COMPARE
4363 && (cc_use = find_single_use (dest, subst_insn, &other_insn)) != 0
4364 && (undobuf.other_insn == 0 || other_insn == undobuf.other_insn)
4365 && GET_RTX_CLASS (GET_CODE (*cc_use)) == '<'
4366 && rtx_equal_p (XEXP (*cc_use, 0), dest))
4368 enum rtx_code old_code = GET_CODE (*cc_use);
4369 enum rtx_code new_code;
4371 int other_changed = 0;
4372 enum machine_mode compare_mode = GET_MODE (dest);
4374 if (GET_CODE (src) == COMPARE)
4375 op0 = XEXP (src, 0), op1 = XEXP (src, 1);
4377 op0 = src, op1 = const0_rtx;
4379 /* Simplify our comparison, if possible. */
4380 new_code = simplify_comparison (old_code, &op0, &op1);
4382 #ifdef EXTRA_CC_MODES
4383 /* If this machine has CC modes other than CCmode, check to see if we
4384 need to use a different CC mode here. */
4385 compare_mode = SELECT_CC_MODE (new_code, op0, op1);
4386 #endif /* EXTRA_CC_MODES */
4388 #if !defined (HAVE_cc0) && defined (EXTRA_CC_MODES)
4389 /* If the mode changed, we have to change SET_DEST, the mode in the
4390 compare, and the mode in the place SET_DEST is used. If SET_DEST is
4391 a hard register, just build new versions with the proper mode. If it
4392 is a pseudo, we lose unless it is only time we set the pseudo, in
4393 which case we can safely change its mode. */
4394 if (compare_mode != GET_MODE (dest))
4396 int regno = REGNO (dest);
4397 rtx new_dest = gen_rtx (REG, compare_mode, regno);
4399 if (regno < FIRST_PSEUDO_REGISTER
4400 || (reg_n_sets[regno] == 1 && ! REG_USERVAR_P (dest)))
4402 if (regno >= FIRST_PSEUDO_REGISTER)
4403 SUBST (regno_reg_rtx[regno], new_dest);
4405 SUBST (SET_DEST (x), new_dest);
4406 SUBST (XEXP (*cc_use, 0), new_dest);
4414 /* If the code changed, we have to build a new comparison in
4415 undobuf.other_insn. */
4416 if (new_code != old_code)
4418 unsigned HOST_WIDE_INT mask;
4420 SUBST (*cc_use, gen_rtx_combine (new_code, GET_MODE (*cc_use),
4423 /* If the only change we made was to change an EQ into an NE or
4424 vice versa, OP0 has only one bit that might be nonzero, and OP1
4425 is zero, check if changing the user of the condition code will
4426 produce a valid insn. If it won't, we can keep the original code
4427 in that insn by surrounding our operation with an XOR. */
4429 if (((old_code == NE && new_code == EQ)
4430 || (old_code == EQ && new_code == NE))
4431 && ! other_changed && op1 == const0_rtx
4432 && GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
4433 && exact_log2 (mask = nonzero_bits (op0, GET_MODE (op0))) >= 0)
4435 rtx pat = PATTERN (other_insn), note = 0;
4438 if ((recog_for_combine (&pat, other_insn, ¬e, &scratches) < 0
4439 && ! check_asm_operands (pat)))
4441 PUT_CODE (*cc_use, old_code);
4444 op0 = gen_binary (XOR, GET_MODE (op0), op0, GEN_INT (mask));
4452 undobuf.other_insn = other_insn;
4455 /* If we are now comparing against zero, change our source if
4456 needed. If we do not use cc0, we always have a COMPARE. */
4457 if (op1 == const0_rtx && dest == cc0_rtx)
4459 SUBST (SET_SRC (x), op0);
4465 /* Otherwise, if we didn't previously have a COMPARE in the
4466 correct mode, we need one. */
4467 if (GET_CODE (src) != COMPARE || GET_MODE (src) != compare_mode)
4470 gen_rtx_combine (COMPARE, compare_mode, op0, op1));
4475 /* Otherwise, update the COMPARE if needed. */
4476 SUBST (XEXP (src, 0), op0);
4477 SUBST (XEXP (src, 1), op1);
4482 /* Get SET_SRC in a form where we have placed back any
4483 compound expressions. Then do the checks below. */
4484 src = make_compound_operation (src, SET);
4485 SUBST (SET_SRC (x), src);
4488 /* If we have (set x (subreg:m1 (op:m2 ...) 0)) with OP being some operation,
4489 and X being a REG or (subreg (reg)), we may be able to convert this to
4490 (set (subreg:m2 x) (op)).
4492 We can always do this if M1 is narrower than M2 because that means that
4493 we only care about the low bits of the result.
4495 However, on machines without WORD_REGISTER_OPERATIONS defined, we cannot
4496 perform a narrower operation that requested since the high-order bits will
4497 be undefined. On machine where it is defined, this transformation is safe
4498 as long as M1 and M2 have the same number of words. */
4500 if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src)
4501 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (src))) != 'o'
4502 && (((GET_MODE_SIZE (GET_MODE (src)) + (UNITS_PER_WORD - 1))
4504 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (src)))
4505 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD))
4506 #ifndef WORD_REGISTER_OPERATIONS
4507 && (GET_MODE_SIZE (GET_MODE (src))
4508 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (src))))
4510 #ifdef CLASS_CANNOT_CHANGE_SIZE
4511 && ! (GET_CODE (dest) == REG && REGNO (dest) < FIRST_PSEUDO_REGISTER
4512 && (TEST_HARD_REG_BIT
4513 (reg_class_contents[(int) CLASS_CANNOT_CHANGE_SIZE],
4515 && (GET_MODE_SIZE (GET_MODE (src))
4516 != GET_MODE_SIZE (GET_MODE (SUBREG_REG (src)))))
4518 && (GET_CODE (dest) == REG
4519 || (GET_CODE (dest) == SUBREG
4520 && GET_CODE (SUBREG_REG (dest)) == REG)))
4522 SUBST (SET_DEST (x),
4523 gen_lowpart_for_combine (GET_MODE (SUBREG_REG (src)),
4525 SUBST (SET_SRC (x), SUBREG_REG (src));
4527 src = SET_SRC (x), dest = SET_DEST (x);
4530 #ifdef LOAD_EXTEND_OP
4531 /* If we have (set FOO (subreg:M (mem:N BAR) 0)) with M wider than N, this
4532 would require a paradoxical subreg. Replace the subreg with a
4533 zero_extend to avoid the reload that would otherwise be required. */
4535 if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src)
4536 && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src))) != NIL
4537 && SUBREG_WORD (src) == 0
4538 && (GET_MODE_SIZE (GET_MODE (src))
4539 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (src))))
4540 && GET_CODE (SUBREG_REG (src)) == MEM)
4543 gen_rtx_combine (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src))),
4544 GET_MODE (src), XEXP (src, 0)));
4550 /* If we don't have a conditional move, SET_SRC is an IF_THEN_ELSE, and we
4551 are comparing an item known to be 0 or -1 against 0, use a logical
4552 operation instead. Check for one of the arms being an IOR of the other
4553 arm with some value. We compute three terms to be IOR'ed together. In
4554 practice, at most two will be nonzero. Then we do the IOR's. */
4556 if (GET_CODE (dest) != PC
4557 && GET_CODE (src) == IF_THEN_ELSE
4558 && GET_MODE_CLASS (GET_MODE (src)) == MODE_INT
4559 && (GET_CODE (XEXP (src, 0)) == EQ || GET_CODE (XEXP (src, 0)) == NE)
4560 && XEXP (XEXP (src, 0), 1) == const0_rtx
4561 && GET_MODE (src) == GET_MODE (XEXP (XEXP (src, 0), 0))
4562 #ifdef HAVE_conditional_move
4563 && ! can_conditionally_move_p (GET_MODE (src))
4565 && (num_sign_bit_copies (XEXP (XEXP (src, 0), 0),
4566 GET_MODE (XEXP (XEXP (src, 0), 0)))
4567 == GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (src, 0), 0))))
4568 && ! side_effects_p (src))
4570 rtx true = (GET_CODE (XEXP (src, 0)) == NE
4571 ? XEXP (src, 1) : XEXP (src, 2));
4572 rtx false = (GET_CODE (XEXP (src, 0)) == NE
4573 ? XEXP (src, 2) : XEXP (src, 1));
4574 rtx term1 = const0_rtx, term2, term3;
4576 if (GET_CODE (true) == IOR && rtx_equal_p (XEXP (true, 0), false))
4577 term1 = false, true = XEXP (true, 1), false = const0_rtx;
4578 else if (GET_CODE (true) == IOR
4579 && rtx_equal_p (XEXP (true, 1), false))
4580 term1 = false, true = XEXP (true, 0), false = const0_rtx;
4581 else if (GET_CODE (false) == IOR
4582 && rtx_equal_p (XEXP (false, 0), true))
4583 term1 = true, false = XEXP (false, 1), true = const0_rtx;
4584 else if (GET_CODE (false) == IOR
4585 && rtx_equal_p (XEXP (false, 1), true))
4586 term1 = true, false = XEXP (false, 0), true = const0_rtx;
4588 term2 = gen_binary (AND, GET_MODE (src), XEXP (XEXP (src, 0), 0), true);
4589 term3 = gen_binary (AND, GET_MODE (src),
4590 gen_unary (NOT, GET_MODE (src), GET_MODE (src),
4591 XEXP (XEXP (src, 0), 0)),
4595 gen_binary (IOR, GET_MODE (src),
4596 gen_binary (IOR, GET_MODE (src), term1, term2),
4602 /* If either SRC or DEST is a CLOBBER of (const_int 0), make this
4603 whole thing fail. */
4604 if (GET_CODE (src) == CLOBBER && XEXP (src, 0) == const0_rtx)
4606 else if (GET_CODE (dest) == CLOBBER && XEXP (dest, 0) == const0_rtx)
4609 /* Convert this into a field assignment operation, if possible. */
4610 return make_field_assignment (x);
4613 /* Simplify, X, and AND, IOR, or XOR operation, and return the simplified
4614 result. LAST is nonzero if this is the last retry. */
4617 simplify_logical (x, last)
4621 enum machine_mode mode = GET_MODE (x);
4622 rtx op0 = XEXP (x, 0);
4623 rtx op1 = XEXP (x, 1);
4625 switch (GET_CODE (x))
4628 /* Convert (A ^ B) & A to A & (~ B) since the latter is often a single
4629 insn (and may simplify more). */
4630 if (GET_CODE (op0) == XOR
4631 && rtx_equal_p (XEXP (op0, 0), op1)
4632 && ! side_effects_p (op1))
4633 x = gen_binary (AND, mode,
4634 gen_unary (NOT, mode, mode, XEXP (op0, 1)), op1);
4636 if (GET_CODE (op0) == XOR
4637 && rtx_equal_p (XEXP (op0, 1), op1)
4638 && ! side_effects_p (op1))
4639 x = gen_binary (AND, mode,
4640 gen_unary (NOT, mode, mode, XEXP (op0, 0)), op1);
4642 /* Similarly for (~ (A ^ B)) & A. */
4643 if (GET_CODE (op0) == NOT
4644 && GET_CODE (XEXP (op0, 0)) == XOR
4645 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), op1)
4646 && ! side_effects_p (op1))
4647 x = gen_binary (AND, mode, XEXP (XEXP (op0, 0), 1), op1);
4649 if (GET_CODE (op0) == NOT
4650 && GET_CODE (XEXP (op0, 0)) == XOR
4651 && rtx_equal_p (XEXP (XEXP (op0, 0), 1), op1)
4652 && ! side_effects_p (op1))
4653 x = gen_binary (AND, mode, XEXP (XEXP (op0, 0), 0), op1);
4655 if (GET_CODE (op1) == CONST_INT)
4657 x = simplify_and_const_int (x, mode, op0, INTVAL (op1));
4659 /* If we have (ior (and (X C1) C2)) and the next restart would be
4660 the last, simplify this by making C1 as small as possible
4663 && GET_CODE (x) == IOR && GET_CODE (op0) == AND
4664 && GET_CODE (XEXP (op0, 1)) == CONST_INT
4665 && GET_CODE (op1) == CONST_INT)
4666 return gen_binary (IOR, mode,
4667 gen_binary (AND, mode, XEXP (op0, 0),
4668 GEN_INT (INTVAL (XEXP (op0, 1))
4669 & ~ INTVAL (op1))), op1);
4671 if (GET_CODE (x) != AND)
4674 if (GET_RTX_CLASS (GET_CODE (x)) == 'c'
4675 || GET_RTX_CLASS (GET_CODE (x)) == '2')
4676 op0 = XEXP (x, 0), op1 = XEXP (x, 1);
4679 /* Convert (A | B) & A to A. */
4680 if (GET_CODE (op0) == IOR
4681 && (rtx_equal_p (XEXP (op0, 0), op1)
4682 || rtx_equal_p (XEXP (op0, 1), op1))
4683 && ! side_effects_p (XEXP (op0, 0))
4684 && ! side_effects_p (XEXP (op0, 1)))
4687 /* In the following group of tests (and those in case IOR below),
4688 we start with some combination of logical operations and apply
4689 the distributive law followed by the inverse distributive law.
4690 Most of the time, this results in no change. However, if some of
4691 the operands are the same or inverses of each other, simplifications
4694 For example, (and (ior A B) (not B)) can occur as the result of
4695 expanding a bit field assignment. When we apply the distributive
4696 law to this, we get (ior (and (A (not B))) (and (B (not B)))),
4697 which then simplifies to (and (A (not B))).
4699 If we have (and (ior A B) C), apply the distributive law and then
4700 the inverse distributive law to see if things simplify. */
4702 if (GET_CODE (op0) == IOR || GET_CODE (op0) == XOR)
4704 x = apply_distributive_law
4705 (gen_binary (GET_CODE (op0), mode,
4706 gen_binary (AND, mode, XEXP (op0, 0), op1),
4707 gen_binary (AND, mode, XEXP (op0, 1), op1)));
4708 if (GET_CODE (x) != AND)
4712 if (GET_CODE (op1) == IOR || GET_CODE (op1) == XOR)
4713 return apply_distributive_law
4714 (gen_binary (GET_CODE (op1), mode,
4715 gen_binary (AND, mode, XEXP (op1, 0), op0),
4716 gen_binary (AND, mode, XEXP (op1, 1), op0)));
4718 /* Similarly, taking advantage of the fact that
4719 (and (not A) (xor B C)) == (xor (ior A B) (ior A C)) */
4721 if (GET_CODE (op0) == NOT && GET_CODE (op1) == XOR)
4722 return apply_distributive_law
4723 (gen_binary (XOR, mode,
4724 gen_binary (IOR, mode, XEXP (op0, 0), XEXP (op1, 0)),
4725 gen_binary (IOR, mode, XEXP (op0, 0), XEXP (op1, 1))));
4727 else if (GET_CODE (op1) == NOT && GET_CODE (op0) == XOR)
4728 return apply_distributive_law
4729 (gen_binary (XOR, mode,
4730 gen_binary (IOR, mode, XEXP (op1, 0), XEXP (op0, 0)),
4731 gen_binary (IOR, mode, XEXP (op1, 0), XEXP (op0, 1))));
4735 /* (ior A C) is C if all bits of A that might be nonzero are on in C. */
4736 if (GET_CODE (op1) == CONST_INT
4737 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4738 && (nonzero_bits (op0, mode) & ~ INTVAL (op1)) == 0)
4741 /* Convert (A & B) | A to A. */
4742 if (GET_CODE (op0) == AND
4743 && (rtx_equal_p (XEXP (op0, 0), op1)
4744 || rtx_equal_p (XEXP (op0, 1), op1))
4745 && ! side_effects_p (XEXP (op0, 0))
4746 && ! side_effects_p (XEXP (op0, 1)))
4749 /* If we have (ior (and A B) C), apply the distributive law and then
4750 the inverse distributive law to see if things simplify. */
4752 if (GET_CODE (op0) == AND)
4754 x = apply_distributive_law
4755 (gen_binary (AND, mode,
4756 gen_binary (IOR, mode, XEXP (op0, 0), op1),
4757 gen_binary (IOR, mode, XEXP (op0, 1), op1)));
4759 if (GET_CODE (x) != IOR)
4763 if (GET_CODE (op1) == AND)
4765 x = apply_distributive_law
4766 (gen_binary (AND, mode,
4767 gen_binary (IOR, mode, XEXP (op1, 0), op0),
4768 gen_binary (IOR, mode, XEXP (op1, 1), op0)));
4770 if (GET_CODE (x) != IOR)
4774 /* Convert (ior (ashift A CX) (lshiftrt A CY)) where CX+CY equals the
4775 mode size to (rotate A CX). */
4777 if (((GET_CODE (op0) == ASHIFT && GET_CODE (op1) == LSHIFTRT)
4778 || (GET_CODE (op1) == ASHIFT && GET_CODE (op0) == LSHIFTRT))
4779 && rtx_equal_p (XEXP (op0, 0), XEXP (op1, 0))
4780 && GET_CODE (XEXP (op0, 1)) == CONST_INT
4781 && GET_CODE (XEXP (op1, 1)) == CONST_INT
4782 && (INTVAL (XEXP (op0, 1)) + INTVAL (XEXP (op1, 1))
4783 == GET_MODE_BITSIZE (mode)))
4784 return gen_rtx (ROTATE, mode, XEXP (op0, 0),
4785 (GET_CODE (op0) == ASHIFT
4786 ? XEXP (op0, 1) : XEXP (op1, 1)));
4788 /* If OP0 is (ashiftrt (plus ...) C), it might actually be
4789 a (sign_extend (plus ...)). If so, OP1 is a CONST_INT, and the PLUS
4790 does not affect any of the bits in OP1, it can really be done
4791 as a PLUS and we can associate. We do this by seeing if OP1
4792 can be safely shifted left C bits. */
4793 if (GET_CODE (op1) == CONST_INT && GET_CODE (op0) == ASHIFTRT
4794 && GET_CODE (XEXP (op0, 0)) == PLUS
4795 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
4796 && GET_CODE (XEXP (op0, 1)) == CONST_INT
4797 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT)
4799 int count = INTVAL (XEXP (op0, 1));
4800 HOST_WIDE_INT mask = INTVAL (op1) << count;
4802 if (mask >> count == INTVAL (op1)
4803 && (mask & nonzero_bits (XEXP (op0, 0), mode)) == 0)
4805 SUBST (XEXP (XEXP (op0, 0), 1),
4806 GEN_INT (INTVAL (XEXP (XEXP (op0, 0), 1)) | mask));
4813 /* Convert (XOR (NOT x) (NOT y)) to (XOR x y).
4814 Also convert (XOR (NOT x) y) to (NOT (XOR x y)), similarly for
4817 int num_negated = 0;
4819 if (GET_CODE (op0) == NOT)
4820 num_negated++, op0 = XEXP (op0, 0);
4821 if (GET_CODE (op1) == NOT)
4822 num_negated++, op1 = XEXP (op1, 0);
4824 if (num_negated == 2)
4826 SUBST (XEXP (x, 0), op0);
4827 SUBST (XEXP (x, 1), op1);
4829 else if (num_negated == 1)
4830 return gen_unary (NOT, mode, mode, gen_binary (XOR, mode, op0, op1));
4833 /* Convert (xor (and A B) B) to (and (not A) B). The latter may
4834 correspond to a machine insn or result in further simplifications
4835 if B is a constant. */
4837 if (GET_CODE (op0) == AND
4838 && rtx_equal_p (XEXP (op0, 1), op1)
4839 && ! side_effects_p (op1))
4840 return gen_binary (AND, mode,
4841 gen_unary (NOT, mode, mode, XEXP (op0, 0)),
4844 else if (GET_CODE (op0) == AND
4845 && rtx_equal_p (XEXP (op0, 0), op1)
4846 && ! side_effects_p (op1))
4847 return gen_binary (AND, mode,
4848 gen_unary (NOT, mode, mode, XEXP (op0, 1)),
4851 #if STORE_FLAG_VALUE == 1
4852 /* (xor (comparison foo bar) (const_int 1)) can become the reversed
4854 if (op1 == const1_rtx
4855 && GET_RTX_CLASS (GET_CODE (op0)) == '<'
4856 && reversible_comparison_p (op0))
4857 return gen_rtx_combine (reverse_condition (GET_CODE (op0)),
4858 mode, XEXP (op0, 0), XEXP (op0, 1));
4860 /* (lshiftrt foo C) where C is the number of bits in FOO minus 1
4861 is (lt foo (const_int 0)), so we can perform the above
4864 if (op1 == const1_rtx
4865 && GET_CODE (op0) == LSHIFTRT
4866 && GET_CODE (XEXP (op0, 1)) == CONST_INT
4867 && INTVAL (XEXP (op0, 1)) == GET_MODE_BITSIZE (mode) - 1)
4868 return gen_rtx_combine (GE, mode, XEXP (op0, 0), const0_rtx);
4871 /* (xor (comparison foo bar) (const_int sign-bit))
4872 when STORE_FLAG_VALUE is the sign bit. */
4873 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4874 && (STORE_FLAG_VALUE
4875 == (HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (mode) - 1))
4876 && op1 == const_true_rtx
4877 && GET_RTX_CLASS (GET_CODE (op0)) == '<'
4878 && reversible_comparison_p (op0))
4879 return gen_rtx_combine (reverse_condition (GET_CODE (op0)),
4880 mode, XEXP (op0, 0), XEXP (op0, 1));
4887 /* We consider ZERO_EXTRACT, SIGN_EXTRACT, and SIGN_EXTEND as "compound
4888 operations" because they can be replaced with two more basic operations.
4889 ZERO_EXTEND is also considered "compound" because it can be replaced with
4890 an AND operation, which is simpler, though only one operation.
4892 The function expand_compound_operation is called with an rtx expression
4893 and will convert it to the appropriate shifts and AND operations,
4894 simplifying at each stage.
4896 The function make_compound_operation is called to convert an expression
4897 consisting of shifts and ANDs into the equivalent compound expression.
4898 It is the inverse of this function, loosely speaking. */
4901 expand_compound_operation (x)
4909 switch (GET_CODE (x))
4914 /* We can't necessarily use a const_int for a multiword mode;
4915 it depends on implicitly extending the value.
4916 Since we don't know the right way to extend it,
4917 we can't tell whether the implicit way is right.
4919 Even for a mode that is no wider than a const_int,
4920 we can't win, because we need to sign extend one of its bits through
4921 the rest of it, and we don't know which bit. */
4922 if (GET_CODE (XEXP (x, 0)) == CONST_INT)
4925 /* Return if (subreg:MODE FROM 0) is not a safe replacement for
4926 (zero_extend:MODE FROM) or (sign_extend:MODE FROM). It is for any MEM
4927 because (SUBREG (MEM...)) is guaranteed to cause the MEM to be
4928 reloaded. If not for that, MEM's would very rarely be safe.
4930 Reject MODEs bigger than a word, because we might not be able
4931 to reference a two-register group starting with an arbitrary register
4932 (and currently gen_lowpart might crash for a SUBREG). */
4934 if (GET_MODE_SIZE (GET_MODE (XEXP (x, 0))) > UNITS_PER_WORD)
4937 len = GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)));
4938 /* If the inner object has VOIDmode (the only way this can happen
4939 is if it is a ASM_OPERANDS), we can't do anything since we don't
4940 know how much masking to do. */
4949 /* If the operand is a CLOBBER, just return it. */
4950 if (GET_CODE (XEXP (x, 0)) == CLOBBER)
4953 if (GET_CODE (XEXP (x, 1)) != CONST_INT
4954 || GET_CODE (XEXP (x, 2)) != CONST_INT
4955 || GET_MODE (XEXP (x, 0)) == VOIDmode)
4958 len = INTVAL (XEXP (x, 1));
4959 pos = INTVAL (XEXP (x, 2));
4961 /* If this goes outside the object being extracted, replace the object
4962 with a (use (mem ...)) construct that only combine understands
4963 and is used only for this purpose. */
4964 if (len + pos > GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))))
4965 SUBST (XEXP (x, 0), gen_rtx (USE, GET_MODE (x), XEXP (x, 0)));
4967 if (BITS_BIG_ENDIAN)
4968 pos = GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - len - pos;
4976 /* We can optimize some special cases of ZERO_EXTEND. */
4977 if (GET_CODE (x) == ZERO_EXTEND)
4979 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI if we
4980 know that the last value didn't have any inappropriate bits
4982 if (GET_CODE (XEXP (x, 0)) == TRUNCATE
4983 && GET_MODE (XEXP (XEXP (x, 0), 0)) == GET_MODE (x)
4984 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
4985 && (nonzero_bits (XEXP (XEXP (x, 0), 0), GET_MODE (x))
4986 & ~ GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
4987 return XEXP (XEXP (x, 0), 0);
4989 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
4990 if (GET_CODE (XEXP (x, 0)) == SUBREG
4991 && GET_MODE (SUBREG_REG (XEXP (x, 0))) == GET_MODE (x)
4992 && subreg_lowpart_p (XEXP (x, 0))
4993 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
4994 && (nonzero_bits (SUBREG_REG (XEXP (x, 0)), GET_MODE (x))
4995 & ~ GET_MODE_MASK (GET_MODE (SUBREG_REG (x)))) == 0)
4996 return SUBREG_REG (XEXP (x, 0));
4998 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI when foo
4999 is a comparison and STORE_FLAG_VALUE permits. This is like
5000 the first case, but it works even when GET_MODE (x) is larger
5001 than HOST_WIDE_INT. */
5002 if (GET_CODE (XEXP (x, 0)) == TRUNCATE
5003 && GET_MODE (XEXP (XEXP (x, 0), 0)) == GET_MODE (x)
5004 && GET_RTX_CLASS (GET_CODE (XEXP (XEXP (x, 0), 0))) == '<'
5005 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
5006 <= HOST_BITS_PER_WIDE_INT)
5007 && ((HOST_WIDE_INT) STORE_FLAG_VALUE
5008 & ~ GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5009 return XEXP (XEXP (x, 0), 0);
5011 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
5012 if (GET_CODE (XEXP (x, 0)) == SUBREG
5013 && GET_MODE (SUBREG_REG (XEXP (x, 0))) == GET_MODE (x)
5014 && subreg_lowpart_p (XEXP (x, 0))
5015 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 0)))) == '<'
5016 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
5017 <= HOST_BITS_PER_WIDE_INT)
5018 && ((HOST_WIDE_INT) STORE_FLAG_VALUE
5019 & ~ GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5020 return SUBREG_REG (XEXP (x, 0));
5022 /* If sign extension is cheaper than zero extension, then use it
5023 if we know that no extraneous bits are set, and that the high
5025 if (flag_expensive_optimizations
5026 && ((GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
5027 && ((nonzero_bits (XEXP (x, 0), GET_MODE (x))
5028 & ~ (((unsigned HOST_WIDE_INT)
5029 GET_MODE_MASK (GET_MODE (XEXP (x, 0))))
5032 || (GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
5033 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
5034 <= HOST_BITS_PER_WIDE_INT)
5035 && (((HOST_WIDE_INT) STORE_FLAG_VALUE
5036 & ~ (((unsigned HOST_WIDE_INT)
5037 GET_MODE_MASK (GET_MODE (XEXP (x, 0))))
5041 rtx temp = gen_rtx (SIGN_EXTEND, GET_MODE (x), XEXP (x, 0));
5043 if (rtx_cost (temp, SET) < rtx_cost (x, SET))
5044 return expand_compound_operation (temp);
5048 /* If we reach here, we want to return a pair of shifts. The inner
5049 shift is a left shift of BITSIZE - POS - LEN bits. The outer
5050 shift is a right shift of BITSIZE - LEN bits. It is arithmetic or
5051 logical depending on the value of UNSIGNEDP.
5053 If this was a ZERO_EXTEND or ZERO_EXTRACT, this pair of shifts will be
5054 converted into an AND of a shift.
5056 We must check for the case where the left shift would have a negative
5057 count. This can happen in a case like (x >> 31) & 255 on machines
5058 that can't shift by a constant. On those machines, we would first
5059 combine the shift with the AND to produce a variable-position
5060 extraction. Then the constant of 31 would be substituted in to produce
5061 a such a position. */
5063 modewidth = GET_MODE_BITSIZE (GET_MODE (x));
5064 if (modewidth >= pos - len)
5065 tem = simplify_shift_const (NULL_RTX, unsignedp ? LSHIFTRT : ASHIFTRT,
5067 simplify_shift_const (NULL_RTX, ASHIFT,
5070 modewidth - pos - len),
5073 else if (unsignedp && len < HOST_BITS_PER_WIDE_INT)
5074 tem = simplify_and_const_int (NULL_RTX, GET_MODE (x),
5075 simplify_shift_const (NULL_RTX, LSHIFTRT,
5078 ((HOST_WIDE_INT) 1 << len) - 1);
5080 /* Any other cases we can't handle. */
5084 /* If we couldn't do this for some reason, return the original
5086 if (GET_CODE (tem) == CLOBBER)
5092 /* X is a SET which contains an assignment of one object into
5093 a part of another (such as a bit-field assignment, STRICT_LOW_PART,
5094 or certain SUBREGS). If possible, convert it into a series of
5097 We half-heartedly support variable positions, but do not at all
5098 support variable lengths. */
5101 expand_field_assignment (x)
5105 rtx pos; /* Always counts from low bit. */
5108 enum machine_mode compute_mode;
5110 /* Loop until we find something we can't simplify. */
5113 if (GET_CODE (SET_DEST (x)) == STRICT_LOW_PART
5114 && GET_CODE (XEXP (SET_DEST (x), 0)) == SUBREG)
5116 inner = SUBREG_REG (XEXP (SET_DEST (x), 0));
5117 len = GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0)));
5118 pos = GEN_INT (BITS_PER_WORD * SUBREG_WORD (XEXP (SET_DEST (x), 0)));
5120 else if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
5121 && GET_CODE (XEXP (SET_DEST (x), 1)) == CONST_INT)
5123 inner = XEXP (SET_DEST (x), 0);
5124 len = INTVAL (XEXP (SET_DEST (x), 1));
5125 pos = XEXP (SET_DEST (x), 2);
5127 /* If the position is constant and spans the width of INNER,
5128 surround INNER with a USE to indicate this. */
5129 if (GET_CODE (pos) == CONST_INT
5130 && INTVAL (pos) + len > GET_MODE_BITSIZE (GET_MODE (inner)))
5131 inner = gen_rtx (USE, GET_MODE (SET_DEST (x)), inner);
5133 if (BITS_BIG_ENDIAN)
5135 if (GET_CODE (pos) == CONST_INT)
5136 pos = GEN_INT (GET_MODE_BITSIZE (GET_MODE (inner)) - len
5138 else if (GET_CODE (pos) == MINUS
5139 && GET_CODE (XEXP (pos, 1)) == CONST_INT
5140 && (INTVAL (XEXP (pos, 1))
5141 == GET_MODE_BITSIZE (GET_MODE (inner)) - len))
5142 /* If position is ADJUST - X, new position is X. */
5143 pos = XEXP (pos, 0);
5145 pos = gen_binary (MINUS, GET_MODE (pos),
5146 GEN_INT (GET_MODE_BITSIZE (GET_MODE (inner))
5152 /* A SUBREG between two modes that occupy the same numbers of words
5153 can be done by moving the SUBREG to the source. */
5154 else if (GET_CODE (SET_DEST (x)) == SUBREG
5155 && (((GET_MODE_SIZE (GET_MODE (SET_DEST (x)))
5156 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
5157 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x))))
5158 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)))
5160 x = gen_rtx (SET, VOIDmode, SUBREG_REG (SET_DEST (x)),
5161 gen_lowpart_for_combine (GET_MODE (SUBREG_REG (SET_DEST (x))),
5168 while (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
5169 inner = SUBREG_REG (inner);
5171 compute_mode = GET_MODE (inner);
5173 /* Compute a mask of LEN bits, if we can do this on the host machine. */
5174 if (len < HOST_BITS_PER_WIDE_INT)
5175 mask = GEN_INT (((HOST_WIDE_INT) 1 << len) - 1);
5179 /* Now compute the equivalent expression. Make a copy of INNER
5180 for the SET_DEST in case it is a MEM into which we will substitute;
5181 we don't want shared RTL in that case. */
5182 x = gen_rtx (SET, VOIDmode, copy_rtx (inner),
5183 gen_binary (IOR, compute_mode,
5184 gen_binary (AND, compute_mode,
5185 gen_unary (NOT, compute_mode,
5191 gen_binary (ASHIFT, compute_mode,
5192 gen_binary (AND, compute_mode,
5193 gen_lowpart_for_combine
5203 /* Return an RTX for a reference to LEN bits of INNER. If POS_RTX is nonzero,
5204 it is an RTX that represents a variable starting position; otherwise,
5205 POS is the (constant) starting bit position (counted from the LSB).
5207 INNER may be a USE. This will occur when we started with a bitfield
5208 that went outside the boundary of the object in memory, which is
5209 allowed on most machines. To isolate this case, we produce a USE
5210 whose mode is wide enough and surround the MEM with it. The only
5211 code that understands the USE is this routine. If it is not removed,
5212 it will cause the resulting insn not to match.
5214 UNSIGNEDP is non-zero for an unsigned reference and zero for a
5217 IN_DEST is non-zero if this is a reference in the destination of a
5218 SET. This is used when a ZERO_ or SIGN_EXTRACT isn't needed. If non-zero,
5219 a STRICT_LOW_PART will be used, if zero, ZERO_EXTEND or SIGN_EXTEND will
5222 IN_COMPARE is non-zero if we are in a COMPARE. This means that a
5223 ZERO_EXTRACT should be built even for bits starting at bit 0.
5225 MODE is the desired mode of the result (if IN_DEST == 0).
5227 The result is an RTX for the extraction or NULL_RTX if the target
5231 make_extraction (mode, inner, pos, pos_rtx, len,
5232 unsignedp, in_dest, in_compare)
5233 enum machine_mode mode;
5239 int in_dest, in_compare;
5241 /* This mode describes the size of the storage area
5242 to fetch the overall value from. Within that, we
5243 ignore the POS lowest bits, etc. */
5244 enum machine_mode is_mode = GET_MODE (inner);
5245 enum machine_mode inner_mode;
5246 enum machine_mode wanted_inner_mode = byte_mode;
5247 enum machine_mode wanted_inner_reg_mode = word_mode;
5248 enum machine_mode pos_mode = word_mode;
5249 enum machine_mode extraction_mode = word_mode;
5250 enum machine_mode tmode = mode_for_size (len, MODE_INT, 1);
5253 rtx orig_pos_rtx = pos_rtx;
5256 /* Get some information about INNER and get the innermost object. */
5257 if (GET_CODE (inner) == USE)
5258 /* (use:SI (mem:QI foo)) stands for (mem:SI foo). */
5259 /* We don't need to adjust the position because we set up the USE
5260 to pretend that it was a full-word object. */
5261 spans_byte = 1, inner = XEXP (inner, 0);
5262 else if (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
5264 /* If going from (subreg:SI (mem:QI ...)) to (mem:QI ...),
5265 consider just the QI as the memory to extract from.
5266 The subreg adds or removes high bits; its mode is
5267 irrelevant to the meaning of this extraction,
5268 since POS and LEN count from the lsb. */
5269 if (GET_CODE (SUBREG_REG (inner)) == MEM)
5270 is_mode = GET_MODE (SUBREG_REG (inner));
5271 inner = SUBREG_REG (inner);
5274 inner_mode = GET_MODE (inner);
5276 if (pos_rtx && GET_CODE (pos_rtx) == CONST_INT)
5277 pos = INTVAL (pos_rtx), pos_rtx = 0;
5279 /* See if this can be done without an extraction. We never can if the
5280 width of the field is not the same as that of some integer mode. For
5281 registers, we can only avoid the extraction if the position is at the
5282 low-order bit and this is either not in the destination or we have the
5283 appropriate STRICT_LOW_PART operation available.
5285 For MEM, we can avoid an extract if the field starts on an appropriate
5286 boundary and we can change the mode of the memory reference. However,
5287 we cannot directly access the MEM if we have a USE and the underlying
5288 MEM is not TMODE. This combination means that MEM was being used in a
5289 context where bits outside its mode were being referenced; that is only
5290 valid in bit-field insns. */
5292 if (tmode != BLKmode
5293 && ! (spans_byte && inner_mode != tmode)
5294 && ((pos_rtx == 0 && (pos % BITS_PER_WORD) == 0
5295 && GET_CODE (inner) != MEM
5297 || (GET_CODE (inner) == REG
5298 && (movstrict_optab->handlers[(int) tmode].insn_code
5299 != CODE_FOR_nothing))))
5300 || (GET_CODE (inner) == MEM && pos_rtx == 0
5302 % (STRICT_ALIGNMENT ? GET_MODE_ALIGNMENT (tmode)
5303 : BITS_PER_UNIT)) == 0
5304 /* We can't do this if we are widening INNER_MODE (it
5305 may not be aligned, for one thing). */
5306 && GET_MODE_BITSIZE (inner_mode) >= GET_MODE_BITSIZE (tmode)
5307 && (inner_mode == tmode
5308 || (! mode_dependent_address_p (XEXP (inner, 0))
5309 && ! MEM_VOLATILE_P (inner))))))
5311 /* If INNER is a MEM, make a new MEM that encompasses just the desired
5312 field. If the original and current mode are the same, we need not
5313 adjust the offset. Otherwise, we do if bytes big endian.
5315 If INNER is not a MEM, get a piece consisting of just the field
5316 of interest (in this case POS % BITS_PER_WORD must be 0). */
5318 if (GET_CODE (inner) == MEM)
5321 /* POS counts from lsb, but make OFFSET count in memory order. */
5322 if (BYTES_BIG_ENDIAN)
5323 offset = (GET_MODE_BITSIZE (is_mode) - len - pos) / BITS_PER_UNIT;
5325 offset = pos / BITS_PER_UNIT;
5327 new = gen_rtx (MEM, tmode, plus_constant (XEXP (inner, 0), offset));
5328 RTX_UNCHANGING_P (new) = RTX_UNCHANGING_P (inner);
5329 MEM_VOLATILE_P (new) = MEM_VOLATILE_P (inner);
5330 MEM_IN_STRUCT_P (new) = MEM_IN_STRUCT_P (inner);
5332 else if (GET_CODE (inner) == REG)
5334 /* We can't call gen_lowpart_for_combine here since we always want
5335 a SUBREG and it would sometimes return a new hard register. */
5336 if (tmode != inner_mode)
5337 new = gen_rtx (SUBREG, tmode, inner,
5339 && GET_MODE_SIZE (inner_mode) > UNITS_PER_WORD
5340 ? (((GET_MODE_SIZE (inner_mode)
5341 - GET_MODE_SIZE (tmode))
5343 - pos / BITS_PER_WORD)
5344 : pos / BITS_PER_WORD));
5349 new = force_to_mode (inner, tmode,
5350 len >= HOST_BITS_PER_WIDE_INT
5351 ? GET_MODE_MASK (tmode)
5352 : ((HOST_WIDE_INT) 1 << len) - 1,
5355 /* If this extraction is going into the destination of a SET,
5356 make a STRICT_LOW_PART unless we made a MEM. */
5359 return (GET_CODE (new) == MEM ? new
5360 : (GET_CODE (new) != SUBREG
5361 ? gen_rtx (CLOBBER, tmode, const0_rtx)
5362 : gen_rtx_combine (STRICT_LOW_PART, VOIDmode, new)));
5364 /* Otherwise, sign- or zero-extend unless we already are in the
5367 return (mode == tmode ? new
5368 : gen_rtx_combine (unsignedp ? ZERO_EXTEND : SIGN_EXTEND,
5372 /* Unless this is a COMPARE or we have a funny memory reference,
5373 don't do anything with zero-extending field extracts starting at
5374 the low-order bit since they are simple AND operations. */
5375 if (pos_rtx == 0 && pos == 0 && ! in_dest
5376 && ! in_compare && ! spans_byte && unsignedp)
5379 /* Unless we are allowed to span bytes, reject this if we would be
5380 spanning bytes or if the position is not a constant and the length
5381 is not 1. In all other cases, we would only be going outside
5382 out object in cases when an original shift would have been
5385 && ((pos_rtx == 0 && pos + len > GET_MODE_BITSIZE (is_mode))
5386 || (pos_rtx != 0 && len != 1)))
5389 /* Get the mode to use should INNER not be a MEM, the mode for the position,
5390 and the mode for the result. */
5394 wanted_inner_reg_mode = insn_operand_mode[(int) CODE_FOR_insv][0];
5395 pos_mode = insn_operand_mode[(int) CODE_FOR_insv][2];
5396 extraction_mode = insn_operand_mode[(int) CODE_FOR_insv][3];
5401 if (! in_dest && unsignedp)
5403 wanted_inner_reg_mode = insn_operand_mode[(int) CODE_FOR_extzv][1];
5404 pos_mode = insn_operand_mode[(int) CODE_FOR_extzv][3];
5405 extraction_mode = insn_operand_mode[(int) CODE_FOR_extzv][0];
5410 if (! in_dest && ! unsignedp)
5412 wanted_inner_reg_mode = insn_operand_mode[(int) CODE_FOR_extv][1];
5413 pos_mode = insn_operand_mode[(int) CODE_FOR_extv][3];
5414 extraction_mode = insn_operand_mode[(int) CODE_FOR_extv][0];
5418 /* Never narrow an object, since that might not be safe. */
5420 if (mode != VOIDmode
5421 && GET_MODE_SIZE (extraction_mode) < GET_MODE_SIZE (mode))
5422 extraction_mode = mode;
5424 if (pos_rtx && GET_MODE (pos_rtx) != VOIDmode
5425 && GET_MODE_SIZE (pos_mode) < GET_MODE_SIZE (GET_MODE (pos_rtx)))
5426 pos_mode = GET_MODE (pos_rtx);
5428 /* If this is not from memory, the desired mode is wanted_inner_reg_mode;
5429 if we have to change the mode of memory and cannot, the desired mode is
5431 if (GET_CODE (inner) != MEM)
5432 wanted_inner_mode = wanted_inner_reg_mode;
5433 else if (inner_mode != wanted_inner_mode
5434 && (mode_dependent_address_p (XEXP (inner, 0))
5435 || MEM_VOLATILE_P (inner)))
5436 wanted_inner_mode = extraction_mode;
5440 if (BITS_BIG_ENDIAN)
5442 /* POS is passed as if BITS_BIG_ENDIAN == 0, so we need to convert it to
5443 BITS_BIG_ENDIAN style. If position is constant, compute new
5444 position. Otherwise, build subtraction.
5445 Note that POS is relative to the mode of the original argument.
5446 If it's a MEM we need to recompute POS relative to that.
5447 However, if we're extracting from (or inserting into) a register,
5448 we want to recompute POS relative to wanted_inner_mode. */
5449 int width = (GET_CODE (inner) == MEM
5450 ? GET_MODE_BITSIZE (is_mode)
5451 : GET_MODE_BITSIZE (wanted_inner_mode));
5454 pos = width - len - pos;
5457 = gen_rtx_combine (MINUS, GET_MODE (pos_rtx),
5458 GEN_INT (width - len), pos_rtx);
5459 /* POS may be less than 0 now, but we check for that below.
5460 Note that it can only be less than 0 if GET_CODE (inner) != MEM. */
5463 /* If INNER has a wider mode, make it smaller. If this is a constant
5464 extract, try to adjust the byte to point to the byte containing
5466 if (wanted_inner_mode != VOIDmode
5467 && GET_MODE_SIZE (wanted_inner_mode) < GET_MODE_SIZE (is_mode)
5468 && ((GET_CODE (inner) == MEM
5469 && (inner_mode == wanted_inner_mode
5470 || (! mode_dependent_address_p (XEXP (inner, 0))
5471 && ! MEM_VOLATILE_P (inner))))))
5475 /* The computations below will be correct if the machine is big
5476 endian in both bits and bytes or little endian in bits and bytes.
5477 If it is mixed, we must adjust. */
5479 /* If bytes are big endian and we had a paradoxical SUBREG, we must
5480 adjust OFFSET to compensate. */
5481 if (BYTES_BIG_ENDIAN
5483 && GET_MODE_SIZE (inner_mode) < GET_MODE_SIZE (is_mode))
5484 offset -= GET_MODE_SIZE (is_mode) - GET_MODE_SIZE (inner_mode);
5486 /* If this is a constant position, we can move to the desired byte. */
5489 offset += pos / BITS_PER_UNIT;
5490 pos %= GET_MODE_BITSIZE (wanted_inner_mode);
5493 if (BYTES_BIG_ENDIAN != BITS_BIG_ENDIAN
5495 && is_mode != wanted_inner_mode)
5496 offset = (GET_MODE_SIZE (is_mode)
5497 - GET_MODE_SIZE (wanted_inner_mode) - offset);
5499 if (offset != 0 || inner_mode != wanted_inner_mode)
5501 rtx newmem = gen_rtx (MEM, wanted_inner_mode,
5502 plus_constant (XEXP (inner, 0), offset));
5503 RTX_UNCHANGING_P (newmem) = RTX_UNCHANGING_P (inner);
5504 MEM_VOLATILE_P (newmem) = MEM_VOLATILE_P (inner);
5505 MEM_IN_STRUCT_P (newmem) = MEM_IN_STRUCT_P (inner);
5510 /* If INNER is not memory, we can always get it into the proper mode. If we
5511 are changing its mode, POS must be a constant and smaller than the size
5513 else if (GET_CODE (inner) != MEM)
5515 if (GET_MODE (inner) != wanted_inner_mode
5517 || orig_pos + len > GET_MODE_BITSIZE (wanted_inner_mode)))
5520 inner = force_to_mode (inner, wanted_inner_mode,
5522 || len + orig_pos >= HOST_BITS_PER_WIDE_INT
5523 ? GET_MODE_MASK (wanted_inner_mode)
5524 : (((HOST_WIDE_INT) 1 << len) - 1) << orig_pos,
5528 /* Adjust mode of POS_RTX, if needed. If we want a wider mode, we
5529 have to zero extend. Otherwise, we can just use a SUBREG. */
5531 && GET_MODE_SIZE (pos_mode) > GET_MODE_SIZE (GET_MODE (pos_rtx)))
5532 pos_rtx = gen_rtx_combine (ZERO_EXTEND, pos_mode, pos_rtx);
5533 else if (pos_rtx != 0
5534 && GET_MODE_SIZE (pos_mode) < GET_MODE_SIZE (GET_MODE (pos_rtx)))
5535 pos_rtx = gen_lowpart_for_combine (pos_mode, pos_rtx);
5537 /* Make POS_RTX unless we already have it and it is correct. If we don't
5538 have a POS_RTX but we do have an ORIG_POS_RTX, the latter must
5540 if (pos_rtx == 0 && orig_pos_rtx != 0 && INTVAL (orig_pos_rtx) == pos)
5541 pos_rtx = orig_pos_rtx;
5543 else if (pos_rtx == 0)
5544 pos_rtx = GEN_INT (pos);
5546 /* Make the required operation. See if we can use existing rtx. */
5547 new = gen_rtx_combine (unsignedp ? ZERO_EXTRACT : SIGN_EXTRACT,
5548 extraction_mode, inner, GEN_INT (len), pos_rtx);
5550 new = gen_lowpart_for_combine (mode, new);
5555 /* See if X contains an ASHIFT of COUNT or more bits that can be commuted
5556 with any other operations in X. Return X without that shift if so. */
5559 extract_left_shift (x, count)
5563 enum rtx_code code = GET_CODE (x);
5564 enum machine_mode mode = GET_MODE (x);
5570 /* This is the shift itself. If it is wide enough, we will return
5571 either the value being shifted if the shift count is equal to
5572 COUNT or a shift for the difference. */
5573 if (GET_CODE (XEXP (x, 1)) == CONST_INT
5574 && INTVAL (XEXP (x, 1)) >= count)
5575 return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (x, 0),
5576 INTVAL (XEXP (x, 1)) - count);
5580 if ((tem = extract_left_shift (XEXP (x, 0), count)) != 0)
5581 return gen_unary (code, mode, mode, tem);
5585 case PLUS: case IOR: case XOR: case AND:
5586 /* If we can safely shift this constant and we find the inner shift,
5587 make a new operation. */
5588 if (GET_CODE (XEXP (x,1)) == CONST_INT
5589 && (INTVAL (XEXP (x, 1)) & (((HOST_WIDE_INT) 1 << count)) - 1) == 0
5590 && (tem = extract_left_shift (XEXP (x, 0), count)) != 0)
5591 return gen_binary (code, mode, tem,
5592 GEN_INT (INTVAL (XEXP (x, 1)) >> count));
5600 /* Look at the expression rooted at X. Look for expressions
5601 equivalent to ZERO_EXTRACT, SIGN_EXTRACT, ZERO_EXTEND, SIGN_EXTEND.
5602 Form these expressions.
5604 Return the new rtx, usually just X.
5606 Also, for machines like the Vax that don't have logical shift insns,
5607 try to convert logical to arithmetic shift operations in cases where
5608 they are equivalent. This undoes the canonicalizations to logical
5609 shifts done elsewhere.
5611 We try, as much as possible, to re-use rtl expressions to save memory.
5613 IN_CODE says what kind of expression we are processing. Normally, it is
5614 SET. In a memory address (inside a MEM, PLUS or minus, the latter two
5615 being kludges), it is MEM. When processing the arguments of a comparison
5616 or a COMPARE against zero, it is COMPARE. */
5619 make_compound_operation (x, in_code)
5621 enum rtx_code in_code;
5623 enum rtx_code code = GET_CODE (x);
5624 enum machine_mode mode = GET_MODE (x);
5625 int mode_width = GET_MODE_BITSIZE (mode);
5627 enum rtx_code next_code;
5633 /* Select the code to be used in recursive calls. Once we are inside an
5634 address, we stay there. If we have a comparison, set to COMPARE,
5635 but once inside, go back to our default of SET. */
5637 next_code = (code == MEM || code == PLUS || code == MINUS ? MEM
5638 : ((code == COMPARE || GET_RTX_CLASS (code) == '<')
5639 && XEXP (x, 1) == const0_rtx) ? COMPARE
5640 : in_code == COMPARE ? SET : in_code);
5642 /* Process depending on the code of this operation. If NEW is set
5643 non-zero, it will be returned. */
5648 /* Convert shifts by constants into multiplications if inside
5650 if (in_code == MEM && GET_CODE (XEXP (x, 1)) == CONST_INT
5651 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT
5652 && INTVAL (XEXP (x, 1)) >= 0)
5654 new = make_compound_operation (XEXP (x, 0), next_code);
5655 new = gen_rtx_combine (MULT, mode, new,
5656 GEN_INT ((HOST_WIDE_INT) 1
5657 << INTVAL (XEXP (x, 1))));
5662 /* If the second operand is not a constant, we can't do anything
5664 if (GET_CODE (XEXP (x, 1)) != CONST_INT)
5667 /* If the constant is a power of two minus one and the first operand
5668 is a logical right shift, make an extraction. */
5669 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
5670 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
5672 new = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code);
5673 new = make_extraction (mode, new, 0, XEXP (XEXP (x, 0), 1), i, 1,
5674 0, in_code == COMPARE);
5677 /* Same as previous, but for (subreg (lshiftrt ...)) in first op. */
5678 else if (GET_CODE (XEXP (x, 0)) == SUBREG
5679 && subreg_lowpart_p (XEXP (x, 0))
5680 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == LSHIFTRT
5681 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
5683 new = make_compound_operation (XEXP (SUBREG_REG (XEXP (x, 0)), 0),
5685 new = make_extraction (GET_MODE (SUBREG_REG (XEXP (x, 0))), new, 0,
5686 XEXP (SUBREG_REG (XEXP (x, 0)), 1), i, 1,
5687 0, in_code == COMPARE);
5689 /* Same as previous, but for (xor/ior (lshiftrt...) (lshiftrt...)). */
5690 else if ((GET_CODE (XEXP (x, 0)) == XOR
5691 || GET_CODE (XEXP (x, 0)) == IOR)
5692 && GET_CODE (XEXP (XEXP (x, 0), 0)) == LSHIFTRT
5693 && GET_CODE (XEXP (XEXP (x, 0), 1)) == LSHIFTRT
5694 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
5696 /* Apply the distributive law, and then try to make extractions. */
5697 new = gen_rtx_combine (GET_CODE (XEXP (x, 0)), mode,
5698 gen_rtx (AND, mode, XEXP (XEXP (x, 0), 0),
5700 gen_rtx (AND, mode, XEXP (XEXP (x, 0), 1),
5702 new = make_compound_operation (new, in_code);
5705 /* If we are have (and (rotate X C) M) and C is larger than the number
5706 of bits in M, this is an extraction. */
5708 else if (GET_CODE (XEXP (x, 0)) == ROTATE
5709 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
5710 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0
5711 && i <= INTVAL (XEXP (XEXP (x, 0), 1)))
5713 new = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code);
5714 new = make_extraction (mode, new,
5715 (GET_MODE_BITSIZE (mode)
5716 - INTVAL (XEXP (XEXP (x, 0), 1))),
5717 NULL_RTX, i, 1, 0, in_code == COMPARE);
5720 /* On machines without logical shifts, if the operand of the AND is
5721 a logical shift and our mask turns off all the propagated sign
5722 bits, we can replace the logical shift with an arithmetic shift. */
5723 else if (ashr_optab->handlers[(int) mode].insn_code != CODE_FOR_nothing
5724 && (lshr_optab->handlers[(int) mode].insn_code
5725 == CODE_FOR_nothing)
5726 && GET_CODE (XEXP (x, 0)) == LSHIFTRT
5727 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
5728 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
5729 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT
5730 && mode_width <= HOST_BITS_PER_WIDE_INT)
5732 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
5734 mask >>= INTVAL (XEXP (XEXP (x, 0), 1));
5735 if ((INTVAL (XEXP (x, 1)) & ~mask) == 0)
5737 gen_rtx_combine (ASHIFTRT, mode,
5738 make_compound_operation (XEXP (XEXP (x, 0), 0),
5740 XEXP (XEXP (x, 0), 1)));
5743 /* If the constant is one less than a power of two, this might be
5744 representable by an extraction even if no shift is present.
5745 If it doesn't end up being a ZERO_EXTEND, we will ignore it unless
5746 we are in a COMPARE. */
5747 else if ((i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
5748 new = make_extraction (mode,
5749 make_compound_operation (XEXP (x, 0),
5751 0, NULL_RTX, i, 1, 0, in_code == COMPARE);
5753 /* If we are in a comparison and this is an AND with a power of two,
5754 convert this into the appropriate bit extract. */
5755 else if (in_code == COMPARE
5756 && (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0)
5757 new = make_extraction (mode,
5758 make_compound_operation (XEXP (x, 0),
5760 i, NULL_RTX, 1, 1, 0, 1);
5765 /* If the sign bit is known to be zero, replace this with an
5766 arithmetic shift. */
5767 if (ashr_optab->handlers[(int) mode].insn_code == CODE_FOR_nothing
5768 && lshr_optab->handlers[(int) mode].insn_code != CODE_FOR_nothing
5769 && mode_width <= HOST_BITS_PER_WIDE_INT
5770 && (nonzero_bits (XEXP (x, 0), mode) & (1 << (mode_width - 1))) == 0)
5772 new = gen_rtx_combine (ASHIFTRT, mode,
5773 make_compound_operation (XEXP (x, 0),
5779 /* ... fall through ... */
5785 /* If we have (ashiftrt (ashift foo C1) C2) with C2 >= C1,
5786 this is a SIGN_EXTRACT. */
5787 if (GET_CODE (rhs) == CONST_INT
5788 && GET_CODE (lhs) == ASHIFT
5789 && GET_CODE (XEXP (lhs, 1)) == CONST_INT
5790 && INTVAL (rhs) >= INTVAL (XEXP (lhs, 1)))
5792 new = make_compound_operation (XEXP (lhs, 0), next_code);
5793 new = make_extraction (mode, new,
5794 INTVAL (rhs) - INTVAL (XEXP (lhs, 1)),
5795 NULL_RTX, mode_width - INTVAL (rhs),
5796 code == LSHIFTRT, 0, in_code == COMPARE);
5799 /* See if we have operations between an ASHIFTRT and an ASHIFT.
5800 If so, try to merge the shifts into a SIGN_EXTEND. We could
5801 also do this for some cases of SIGN_EXTRACT, but it doesn't
5802 seem worth the effort; the case checked for occurs on Alpha. */
5804 if (GET_RTX_CLASS (GET_CODE (lhs)) != 'o'
5805 && ! (GET_CODE (lhs) == SUBREG
5806 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (lhs))) == 'o'))
5807 && GET_CODE (rhs) == CONST_INT
5808 && INTVAL (rhs) < HOST_BITS_PER_WIDE_INT
5809 && (new = extract_left_shift (lhs, INTVAL (rhs))) != 0)
5810 new = make_extraction (mode, make_compound_operation (new, next_code),
5811 0, NULL_RTX, mode_width - INTVAL (rhs),
5812 code == LSHIFTRT, 0, in_code == COMPARE);
5817 /* Call ourselves recursively on the inner expression. If we are
5818 narrowing the object and it has a different RTL code from
5819 what it originally did, do this SUBREG as a force_to_mode. */
5821 tem = make_compound_operation (SUBREG_REG (x), in_code);
5822 if (GET_CODE (tem) != GET_CODE (SUBREG_REG (x))
5823 && GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (tem))
5824 && subreg_lowpart_p (x))
5826 rtx newer = force_to_mode (tem, mode,
5827 GET_MODE_MASK (mode), NULL_RTX, 0);
5829 /* If we have something other than a SUBREG, we might have
5830 done an expansion, so rerun outselves. */
5831 if (GET_CODE (newer) != SUBREG)
5832 newer = make_compound_operation (newer, in_code);
5840 x = gen_lowpart_for_combine (mode, new);
5841 code = GET_CODE (x);
5844 /* Now recursively process each operand of this operation. */
5845 fmt = GET_RTX_FORMAT (code);
5846 for (i = 0; i < GET_RTX_LENGTH (code); i++)
5849 new = make_compound_operation (XEXP (x, i), next_code);
5850 SUBST (XEXP (x, i), new);
5856 /* Given M see if it is a value that would select a field of bits
5857 within an item, but not the entire word. Return -1 if not.
5858 Otherwise, return the starting position of the field, where 0 is the
5861 *PLEN is set to the length of the field. */
5864 get_pos_from_mask (m, plen)
5865 unsigned HOST_WIDE_INT m;
5868 /* Get the bit number of the first 1 bit from the right, -1 if none. */
5869 int pos = exact_log2 (m & - m);
5874 /* Now shift off the low-order zero bits and see if we have a power of
5876 *plen = exact_log2 ((m >> pos) + 1);
5884 /* See if X can be simplified knowing that we will only refer to it in
5885 MODE and will only refer to those bits that are nonzero in MASK.
5886 If other bits are being computed or if masking operations are done
5887 that select a superset of the bits in MASK, they can sometimes be
5890 Return a possibly simplified expression, but always convert X to
5891 MODE. If X is a CONST_INT, AND the CONST_INT with MASK.
5893 Also, if REG is non-zero and X is a register equal in value to REG,
5896 If JUST_SELECT is nonzero, don't optimize by noticing that bits in MASK
5897 are all off in X. This is used when X will be complemented, by either
5898 NOT, NEG, or XOR. */
5901 force_to_mode (x, mode, mask, reg, just_select)
5903 enum machine_mode mode;
5904 unsigned HOST_WIDE_INT mask;
5908 enum rtx_code code = GET_CODE (x);
5909 int next_select = just_select || code == XOR || code == NOT || code == NEG;
5910 enum machine_mode op_mode;
5911 unsigned HOST_WIDE_INT fuller_mask, nonzero;
5914 /* If this is a CALL, don't do anything. Some of the code below
5915 will do the wrong thing since the mode of a CALL is VOIDmode. */
5919 /* We want to perform the operation is its present mode unless we know
5920 that the operation is valid in MODE, in which case we do the operation
5922 op_mode = ((GET_MODE_CLASS (mode) == GET_MODE_CLASS (GET_MODE (x))
5923 && code_to_optab[(int) code] != 0
5924 && (code_to_optab[(int) code]->handlers[(int) mode].insn_code
5925 != CODE_FOR_nothing))
5926 ? mode : GET_MODE (x));
5928 /* It is not valid to do a right-shift in a narrower mode
5929 than the one it came in with. */
5930 if ((code == LSHIFTRT || code == ASHIFTRT)
5931 && GET_MODE_BITSIZE (mode) < GET_MODE_BITSIZE (GET_MODE (x)))
5932 op_mode = GET_MODE (x);
5934 /* Truncate MASK to fit OP_MODE. */
5936 mask &= GET_MODE_MASK (op_mode);
5938 /* When we have an arithmetic operation, or a shift whose count we
5939 do not know, we need to assume that all bit the up to the highest-order
5940 bit in MASK will be needed. This is how we form such a mask. */
5942 fuller_mask = (GET_MODE_BITSIZE (op_mode) >= HOST_BITS_PER_WIDE_INT
5943 ? GET_MODE_MASK (op_mode)
5944 : ((HOST_WIDE_INT) 1 << (floor_log2 (mask) + 1)) - 1);
5946 fuller_mask = ~ (HOST_WIDE_INT) 0;
5948 /* Determine what bits of X are guaranteed to be (non)zero. */
5949 nonzero = nonzero_bits (x, mode);
5951 /* If none of the bits in X are needed, return a zero. */
5952 if (! just_select && (nonzero & mask) == 0)
5955 /* If X is a CONST_INT, return a new one. Do this here since the
5956 test below will fail. */
5957 if (GET_CODE (x) == CONST_INT)
5959 HOST_WIDE_INT cval = INTVAL (x) & mask;
5960 int width = GET_MODE_BITSIZE (mode);
5962 /* If MODE is narrower that HOST_WIDE_INT and CVAL is a negative
5963 number, sign extend it. */
5964 if (width > 0 && width < HOST_BITS_PER_WIDE_INT
5965 && (cval & ((HOST_WIDE_INT) 1 << (width - 1))) != 0)
5966 cval |= (HOST_WIDE_INT) -1 << width;
5968 return GEN_INT (cval);
5971 /* If X is narrower than MODE and we want all the bits in X's mode, just
5972 get X in the proper mode. */
5973 if (GET_MODE_SIZE (GET_MODE (x)) < GET_MODE_SIZE (mode)
5974 && (GET_MODE_MASK (GET_MODE (x)) & ~ mask) == 0)
5975 return gen_lowpart_for_combine (mode, x);
5977 /* If we aren't changing the mode, X is not a SUBREG, and all zero bits in
5978 MASK are already known to be zero in X, we need not do anything. */
5979 if (GET_MODE (x) == mode && code != SUBREG && (~ mask & nonzero) == 0)
5985 /* If X is a (clobber (const_int)), return it since we know we are
5986 generating something that won't match. */
5990 /* X is a (use (mem ..)) that was made from a bit-field extraction that
5991 spanned the boundary of the MEM. If we are now masking so it is
5992 within that boundary, we don't need the USE any more. */
5993 if (! BITS_BIG_ENDIAN
5994 && (mask & ~ GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5995 return force_to_mode (XEXP (x, 0), mode, mask, reg, next_select);
6002 x = expand_compound_operation (x);
6003 if (GET_CODE (x) != code)
6004 return force_to_mode (x, mode, mask, reg, next_select);
6008 if (reg != 0 && (rtx_equal_p (get_last_value (reg), x)
6009 || rtx_equal_p (reg, get_last_value (x))))
6014 if (subreg_lowpart_p (x)
6015 /* We can ignore the effect of this SUBREG if it narrows the mode or
6016 if the constant masks to zero all the bits the mode doesn't
6018 && ((GET_MODE_SIZE (GET_MODE (x))
6019 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
6021 & GET_MODE_MASK (GET_MODE (x))
6022 & ~ GET_MODE_MASK (GET_MODE (SUBREG_REG (x)))))))
6023 return force_to_mode (SUBREG_REG (x), mode, mask, reg, next_select);
6027 /* If this is an AND with a constant, convert it into an AND
6028 whose constant is the AND of that constant with MASK. If it
6029 remains an AND of MASK, delete it since it is redundant. */
6031 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
6033 x = simplify_and_const_int (x, op_mode, XEXP (x, 0),
6034 mask & INTVAL (XEXP (x, 1)));
6036 /* If X is still an AND, see if it is an AND with a mask that
6037 is just some low-order bits. If so, and it is MASK, we don't
6040 if (GET_CODE (x) == AND && GET_CODE (XEXP (x, 1)) == CONST_INT
6041 && INTVAL (XEXP (x, 1)) == mask)
6044 /* If it remains an AND, try making another AND with the bits
6045 in the mode mask that aren't in MASK turned on. If the
6046 constant in the AND is wide enough, this might make a
6047 cheaper constant. */
6049 if (GET_CODE (x) == AND && GET_CODE (XEXP (x, 1)) == CONST_INT
6050 && GET_MODE_MASK (GET_MODE (x)) != mask
6051 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT)
6053 HOST_WIDE_INT cval = (INTVAL (XEXP (x, 1))
6054 | (GET_MODE_MASK (GET_MODE (x)) & ~ mask));
6055 int width = GET_MODE_BITSIZE (GET_MODE (x));
6058 /* If MODE is narrower that HOST_WIDE_INT and CVAL is a negative
6059 number, sign extend it. */
6060 if (width > 0 && width < HOST_BITS_PER_WIDE_INT
6061 && (cval & ((HOST_WIDE_INT) 1 << (width - 1))) != 0)
6062 cval |= (HOST_WIDE_INT) -1 << width;
6064 y = gen_binary (AND, GET_MODE (x), XEXP (x, 0), GEN_INT (cval));
6065 if (rtx_cost (y, SET) < rtx_cost (x, SET))
6075 /* In (and (plus FOO C1) M), if M is a mask that just turns off
6076 low-order bits (as in an alignment operation) and FOO is already
6077 aligned to that boundary, mask C1 to that boundary as well.
6078 This may eliminate that PLUS and, later, the AND. */
6081 int width = GET_MODE_BITSIZE (mode);
6082 unsigned HOST_WIDE_INT smask = mask;
6084 /* If MODE is narrower than HOST_WIDE_INT and mask is a negative
6085 number, sign extend it. */
6087 if (width < HOST_BITS_PER_WIDE_INT
6088 && (smask & ((HOST_WIDE_INT) 1 << (width - 1))) != 0)
6089 smask |= (HOST_WIDE_INT) -1 << width;
6091 if (GET_CODE (XEXP (x, 1)) == CONST_INT
6092 && exact_log2 (- smask) >= 0
6093 && (nonzero_bits (XEXP (x, 0), mode) & ~ mask) == 0
6094 && (INTVAL (XEXP (x, 1)) & ~ mask) != 0)
6095 return force_to_mode (plus_constant (XEXP (x, 0),
6096 INTVAL (XEXP (x, 1)) & mask),
6097 mode, mask, reg, next_select);
6100 /* ... fall through ... */
6104 /* For PLUS, MINUS and MULT, we need any bits less significant than the
6105 most significant bit in MASK since carries from those bits will
6106 affect the bits we are interested in. */
6112 /* If X is (ior (lshiftrt FOO C1) C2), try to commute the IOR and
6113 LSHIFTRT so we end up with an (and (lshiftrt (ior ...) ...) ...)
6114 operation which may be a bitfield extraction. Ensure that the
6115 constant we form is not wider than the mode of X. */
6117 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
6118 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
6119 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
6120 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT
6121 && GET_CODE (XEXP (x, 1)) == CONST_INT
6122 && ((INTVAL (XEXP (XEXP (x, 0), 1))
6123 + floor_log2 (INTVAL (XEXP (x, 1))))
6124 < GET_MODE_BITSIZE (GET_MODE (x)))
6125 && (INTVAL (XEXP (x, 1))
6126 & ~ nonzero_bits (XEXP (x, 0), GET_MODE (x))) == 0)
6128 temp = GEN_INT ((INTVAL (XEXP (x, 1)) & mask)
6129 << INTVAL (XEXP (XEXP (x, 0), 1)));
6130 temp = gen_binary (GET_CODE (x), GET_MODE (x),
6131 XEXP (XEXP (x, 0), 0), temp);
6132 x = gen_binary (LSHIFTRT, GET_MODE (x), temp,
6133 XEXP (XEXP (x, 0), 1));
6134 return force_to_mode (x, mode, mask, reg, next_select);
6138 /* For most binary operations, just propagate into the operation and
6139 change the mode if we have an operation of that mode. */
6141 op0 = gen_lowpart_for_combine (op_mode,
6142 force_to_mode (XEXP (x, 0), mode, mask,
6144 op1 = gen_lowpart_for_combine (op_mode,
6145 force_to_mode (XEXP (x, 1), mode, mask,
6148 /* If OP1 is a CONST_INT and X is an IOR or XOR, clear bits outside
6149 MASK since OP1 might have been sign-extended but we never want
6150 to turn on extra bits, since combine might have previously relied
6151 on them being off. */
6152 if (GET_CODE (op1) == CONST_INT && (code == IOR || code == XOR)
6153 && (INTVAL (op1) & mask) != 0)
6154 op1 = GEN_INT (INTVAL (op1) & mask);
6156 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
6157 x = gen_binary (code, op_mode, op0, op1);
6161 /* For left shifts, do the same, but just for the first operand.
6162 However, we cannot do anything with shifts where we cannot
6163 guarantee that the counts are smaller than the size of the mode
6164 because such a count will have a different meaning in a
6167 if (! (GET_CODE (XEXP (x, 1)) == CONST_INT
6168 && INTVAL (XEXP (x, 1)) >= 0
6169 && INTVAL (XEXP (x, 1)) < GET_MODE_BITSIZE (mode))
6170 && ! (GET_MODE (XEXP (x, 1)) != VOIDmode
6171 && (nonzero_bits (XEXP (x, 1), GET_MODE (XEXP (x, 1)))
6172 < (unsigned HOST_WIDE_INT) GET_MODE_BITSIZE (mode))))
6175 /* If the shift count is a constant and we can do arithmetic in
6176 the mode of the shift, refine which bits we need. Otherwise, use the
6177 conservative form of the mask. */
6178 if (GET_CODE (XEXP (x, 1)) == CONST_INT
6179 && INTVAL (XEXP (x, 1)) >= 0
6180 && INTVAL (XEXP (x, 1)) < GET_MODE_BITSIZE (op_mode)
6181 && GET_MODE_BITSIZE (op_mode) <= HOST_BITS_PER_WIDE_INT)
6182 mask >>= INTVAL (XEXP (x, 1));
6186 op0 = gen_lowpart_for_combine (op_mode,
6187 force_to_mode (XEXP (x, 0), op_mode,
6188 mask, reg, next_select));
6190 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0))
6191 x = gen_binary (code, op_mode, op0, XEXP (x, 1));
6195 /* Here we can only do something if the shift count is a constant,
6196 this shift constant is valid for the host, and we can do arithmetic
6199 if (GET_CODE (XEXP (x, 1)) == CONST_INT
6200 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT
6201 && GET_MODE_BITSIZE (op_mode) <= HOST_BITS_PER_WIDE_INT)
6203 rtx inner = XEXP (x, 0);
6205 /* Select the mask of the bits we need for the shift operand. */
6206 mask <<= INTVAL (XEXP (x, 1));
6208 /* We can only change the mode of the shift if we can do arithmetic
6209 in the mode of the shift and MASK is no wider than the width of
6211 if (GET_MODE_BITSIZE (op_mode) > HOST_BITS_PER_WIDE_INT
6212 || (mask & ~ GET_MODE_MASK (op_mode)) != 0)
6213 op_mode = GET_MODE (x);
6215 inner = force_to_mode (inner, op_mode, mask, reg, next_select);
6217 if (GET_MODE (x) != op_mode || inner != XEXP (x, 0))
6218 x = gen_binary (LSHIFTRT, op_mode, inner, XEXP (x, 1));
6221 /* If we have (and (lshiftrt FOO C1) C2) where the combination of the
6222 shift and AND produces only copies of the sign bit (C2 is one less
6223 than a power of two), we can do this with just a shift. */
6225 if (GET_CODE (x) == LSHIFTRT
6226 && GET_CODE (XEXP (x, 1)) == CONST_INT
6227 && ((INTVAL (XEXP (x, 1))
6228 + num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0))))
6229 >= GET_MODE_BITSIZE (GET_MODE (x)))
6230 && exact_log2 (mask + 1) >= 0
6231 && (num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
6232 >= exact_log2 (mask + 1)))
6233 x = gen_binary (LSHIFTRT, GET_MODE (x), XEXP (x, 0),
6234 GEN_INT (GET_MODE_BITSIZE (GET_MODE (x))
6235 - exact_log2 (mask + 1)));
6239 /* If we are just looking for the sign bit, we don't need this shift at
6240 all, even if it has a variable count. */
6241 if (GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
6242 && (mask == ((HOST_WIDE_INT) 1
6243 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
6244 return force_to_mode (XEXP (x, 0), mode, mask, reg, next_select);
6246 /* If this is a shift by a constant, get a mask that contains those bits
6247 that are not copies of the sign bit. We then have two cases: If
6248 MASK only includes those bits, this can be a logical shift, which may
6249 allow simplifications. If MASK is a single-bit field not within
6250 those bits, we are requesting a copy of the sign bit and hence can
6251 shift the sign bit to the appropriate location. */
6253 if (GET_CODE (XEXP (x, 1)) == CONST_INT && INTVAL (XEXP (x, 1)) >= 0
6254 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT)
6258 /* If the considered data is wider then HOST_WIDE_INT, we can't
6259 represent a mask for all its bits in a single scalar.
6260 But we only care about the lower bits, so calculate these. */
6262 if (GET_MODE_BITSIZE (GET_MODE (x)) > HOST_BITS_PER_WIDE_INT)
6264 nonzero = ~ (HOST_WIDE_INT) 0;
6266 /* GET_MODE_BITSIZE (GET_MODE (x)) - INTVAL (XEXP (x, 1))
6267 is the number of bits a full-width mask would have set.
6268 We need only shift if these are fewer than nonzero can
6269 hold. If not, we must keep all bits set in nonzero. */
6271 if (GET_MODE_BITSIZE (GET_MODE (x)) - INTVAL (XEXP (x, 1))
6272 < HOST_BITS_PER_WIDE_INT)
6273 nonzero >>= INTVAL (XEXP (x, 1))
6274 + HOST_BITS_PER_WIDE_INT
6275 - GET_MODE_BITSIZE (GET_MODE (x)) ;
6279 nonzero = GET_MODE_MASK (GET_MODE (x));
6280 nonzero >>= INTVAL (XEXP (x, 1));
6283 if ((mask & ~ nonzero) == 0
6284 || (i = exact_log2 (mask)) >= 0)
6286 x = simplify_shift_const
6287 (x, LSHIFTRT, GET_MODE (x), XEXP (x, 0),
6288 i < 0 ? INTVAL (XEXP (x, 1))
6289 : GET_MODE_BITSIZE (GET_MODE (x)) - 1 - i);
6291 if (GET_CODE (x) != ASHIFTRT)
6292 return force_to_mode (x, mode, mask, reg, next_select);
6296 /* If MASK is 1, convert this to a LSHIFTRT. This can be done
6297 even if the shift count isn't a constant. */
6299 x = gen_binary (LSHIFTRT, GET_MODE (x), XEXP (x, 0), XEXP (x, 1));
6301 /* If this is a sign-extension operation that just affects bits
6302 we don't care about, remove it. Be sure the call above returned
6303 something that is still a shift. */
6305 if ((GET_CODE (x) == LSHIFTRT || GET_CODE (x) == ASHIFTRT)
6306 && GET_CODE (XEXP (x, 1)) == CONST_INT
6307 && INTVAL (XEXP (x, 1)) >= 0
6308 && (INTVAL (XEXP (x, 1))
6309 <= GET_MODE_BITSIZE (GET_MODE (x)) - (floor_log2 (mask) + 1))
6310 && GET_CODE (XEXP (x, 0)) == ASHIFT
6311 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
6312 && INTVAL (XEXP (XEXP (x, 0), 1)) == INTVAL (XEXP (x, 1)))
6313 return force_to_mode (XEXP (XEXP (x, 0), 0), mode, mask,
6320 /* If the shift count is constant and we can do computations
6321 in the mode of X, compute where the bits we care about are.
6322 Otherwise, we can't do anything. Don't change the mode of
6323 the shift or propagate MODE into the shift, though. */
6324 if (GET_CODE (XEXP (x, 1)) == CONST_INT
6325 && INTVAL (XEXP (x, 1)) >= 0)
6327 temp = simplify_binary_operation (code == ROTATE ? ROTATERT : ROTATE,
6328 GET_MODE (x), GEN_INT (mask),
6330 if (temp && GET_CODE(temp) == CONST_INT)
6332 force_to_mode (XEXP (x, 0), GET_MODE (x),
6333 INTVAL (temp), reg, next_select));
6338 /* If we just want the low-order bit, the NEG isn't needed since it
6339 won't change the low-order bit. */
6341 return force_to_mode (XEXP (x, 0), mode, mask, reg, just_select);
6343 /* We need any bits less significant than the most significant bit in
6344 MASK since carries from those bits will affect the bits we are
6350 /* (not FOO) is (xor FOO CONST), so if FOO is an LSHIFTRT, we can do the
6351 same as the XOR case above. Ensure that the constant we form is not
6352 wider than the mode of X. */
6354 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
6355 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
6356 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
6357 && (INTVAL (XEXP (XEXP (x, 0), 1)) + floor_log2 (mask)
6358 < GET_MODE_BITSIZE (GET_MODE (x)))
6359 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT)
6361 temp = GEN_INT (mask << INTVAL (XEXP (XEXP (x, 0), 1)));
6362 temp = gen_binary (XOR, GET_MODE (x), XEXP (XEXP (x, 0), 0), temp);
6363 x = gen_binary (LSHIFTRT, GET_MODE (x), temp, XEXP (XEXP (x, 0), 1));
6365 return force_to_mode (x, mode, mask, reg, next_select);
6368 /* (and (not FOO) CONST) is (not (or FOO (not CONST))), so we must
6369 use the full mask inside the NOT. */
6373 op0 = gen_lowpart_for_combine (op_mode,
6374 force_to_mode (XEXP (x, 0), mode, mask,
6376 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0))
6377 x = gen_unary (code, op_mode, op_mode, op0);
6381 /* (and (ne FOO 0) CONST) can be (and FOO CONST) if CONST is included
6382 in STORE_FLAG_VALUE and FOO has a single bit that might be nonzero,
6383 which is in CONST. */
6384 if ((mask & ~ STORE_FLAG_VALUE) == 0 && XEXP (x, 1) == const0_rtx
6385 && exact_log2 (nonzero_bits (XEXP (x, 0), mode)) >= 0
6386 && (nonzero_bits (XEXP (x, 0), mode) & ~ mask) == 0)
6387 return force_to_mode (XEXP (x, 0), mode, mask, reg, next_select);
6392 /* We have no way of knowing if the IF_THEN_ELSE can itself be
6393 written in a narrower mode. We play it safe and do not do so. */
6396 gen_lowpart_for_combine (GET_MODE (x),
6397 force_to_mode (XEXP (x, 1), mode,
6398 mask, reg, next_select)));
6400 gen_lowpart_for_combine (GET_MODE (x),
6401 force_to_mode (XEXP (x, 2), mode,
6402 mask, reg,next_select)));
6406 /* Ensure we return a value of the proper mode. */
6407 return gen_lowpart_for_combine (mode, x);
6410 /* Return nonzero if X is an expression that has one of two values depending on
6411 whether some other value is zero or nonzero. In that case, we return the
6412 value that is being tested, *PTRUE is set to the value if the rtx being
6413 returned has a nonzero value, and *PFALSE is set to the other alternative.
6415 If we return zero, we set *PTRUE and *PFALSE to X. */
6418 if_then_else_cond (x, ptrue, pfalse)
6420 rtx *ptrue, *pfalse;
6422 enum machine_mode mode = GET_MODE (x);
6423 enum rtx_code code = GET_CODE (x);
6424 int size = GET_MODE_BITSIZE (mode);
6425 rtx cond0, cond1, true0, true1, false0, false1;
6426 unsigned HOST_WIDE_INT nz;
6428 /* If this is a unary operation whose operand has one of two values, apply
6429 our opcode to compute those values. */
6430 if (GET_RTX_CLASS (code) == '1'
6431 && (cond0 = if_then_else_cond (XEXP (x, 0), &true0, &false0)) != 0)
6433 *ptrue = gen_unary (code, mode, GET_MODE (XEXP (x, 0)), true0);
6434 *pfalse = gen_unary (code, mode, GET_MODE (XEXP (x, 0)), false0);
6438 /* If this is a COMPARE, do nothing, since the IF_THEN_ELSE we would
6439 make can't possibly match and would suppress other optimizations. */
6440 else if (code == COMPARE)
6443 /* If this is a binary operation, see if either side has only one of two
6444 values. If either one does or if both do and they are conditional on
6445 the same value, compute the new true and false values. */
6446 else if (GET_RTX_CLASS (code) == 'c' || GET_RTX_CLASS (code) == '2'
6447 || GET_RTX_CLASS (code) == '<')
6449 cond0 = if_then_else_cond (XEXP (x, 0), &true0, &false0);
6450 cond1 = if_then_else_cond (XEXP (x, 1), &true1, &false1);
6452 if ((cond0 != 0 || cond1 != 0)
6453 && ! (cond0 != 0 && cond1 != 0 && ! rtx_equal_p (cond0, cond1)))
6455 *ptrue = gen_binary (code, mode, true0, true1);
6456 *pfalse = gen_binary (code, mode, false0, false1);
6457 return cond0 ? cond0 : cond1;
6460 #if STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1
6462 /* See if we have PLUS, IOR, XOR, MINUS or UMAX, where one of the
6463 operands is zero when the other is non-zero, and vice-versa. */
6465 if ((code == PLUS || code == IOR || code == XOR || code == MINUS
6467 && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT)
6469 rtx op0 = XEXP (XEXP (x, 0), 1);
6470 rtx op1 = XEXP (XEXP (x, 1), 1);
6472 cond0 = XEXP (XEXP (x, 0), 0);
6473 cond1 = XEXP (XEXP (x, 1), 0);
6475 if (GET_RTX_CLASS (GET_CODE (cond0)) == '<'
6476 && GET_RTX_CLASS (GET_CODE (cond1)) == '<'
6477 && reversible_comparison_p (cond1)
6478 && ((GET_CODE (cond0) == reverse_condition (GET_CODE (cond1))
6479 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0))
6480 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1)))
6481 || ((swap_condition (GET_CODE (cond0))
6482 == reverse_condition (GET_CODE (cond1)))
6483 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1))
6484 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0))))
6485 && ! side_effects_p (x))
6487 *ptrue = gen_binary (MULT, mode, op0, const_true_rtx);
6488 *pfalse = gen_binary (MULT, mode,
6490 ? gen_unary (NEG, mode, mode, op1) : op1),
6496 /* Similarly for MULT, AND and UMIN, execpt that for these the result
6498 if ((code == MULT || code == AND || code == UMIN)
6499 && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT)
6501 cond0 = XEXP (XEXP (x, 0), 0);
6502 cond1 = XEXP (XEXP (x, 1), 0);
6504 if (GET_RTX_CLASS (GET_CODE (cond0)) == '<'
6505 && GET_RTX_CLASS (GET_CODE (cond1)) == '<'
6506 && reversible_comparison_p (cond1)
6507 && ((GET_CODE (cond0) == reverse_condition (GET_CODE (cond1))
6508 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0))
6509 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1)))
6510 || ((swap_condition (GET_CODE (cond0))
6511 == reverse_condition (GET_CODE (cond1)))
6512 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1))
6513 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0))))
6514 && ! side_effects_p (x))
6516 *ptrue = *pfalse = const0_rtx;
6523 else if (code == IF_THEN_ELSE)
6525 /* If we have IF_THEN_ELSE already, extract the condition and
6526 canonicalize it if it is NE or EQ. */
6527 cond0 = XEXP (x, 0);
6528 *ptrue = XEXP (x, 1), *pfalse = XEXP (x, 2);
6529 if (GET_CODE (cond0) == NE && XEXP (cond0, 1) == const0_rtx)
6530 return XEXP (cond0, 0);
6531 else if (GET_CODE (cond0) == EQ && XEXP (cond0, 1) == const0_rtx)
6533 *ptrue = XEXP (x, 2), *pfalse = XEXP (x, 1);
6534 return XEXP (cond0, 0);
6540 /* If X is a normal SUBREG with both inner and outer modes integral,
6541 we can narrow both the true and false values of the inner expression,
6542 if there is a condition. */
6543 else if (code == SUBREG && GET_MODE_CLASS (mode) == MODE_INT
6544 && GET_MODE_CLASS (GET_MODE (SUBREG_REG (x))) == MODE_INT
6545 && GET_MODE_SIZE (mode) <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x)))
6546 && 0 != (cond0 = if_then_else_cond (SUBREG_REG (x),
6549 *ptrue = force_to_mode (true0, mode, GET_MODE_MASK (mode), NULL_RTX, 0);
6551 = force_to_mode (false0, mode, GET_MODE_MASK (mode), NULL_RTX, 0);
6556 /* If X is a constant, this isn't special and will cause confusions
6557 if we treat it as such. Likewise if it is equivalent to a constant. */
6558 else if (CONSTANT_P (x)
6559 || ((cond0 = get_last_value (x)) != 0 && CONSTANT_P (cond0)))
6562 /* If X is known to be either 0 or -1, those are the true and
6563 false values when testing X. */
6564 else if (num_sign_bit_copies (x, mode) == size)
6566 *ptrue = constm1_rtx, *pfalse = const0_rtx;
6570 /* Likewise for 0 or a single bit. */
6571 else if (exact_log2 (nz = nonzero_bits (x, mode)) >= 0)
6573 *ptrue = GEN_INT (nz), *pfalse = const0_rtx;
6577 /* Otherwise fail; show no condition with true and false values the same. */
6578 *ptrue = *pfalse = x;
6582 /* Return the value of expression X given the fact that condition COND
6583 is known to be true when applied to REG as its first operand and VAL
6584 as its second. X is known to not be shared and so can be modified in
6587 We only handle the simplest cases, and specifically those cases that
6588 arise with IF_THEN_ELSE expressions. */
6591 known_cond (x, cond, reg, val)
6596 enum rtx_code code = GET_CODE (x);
6601 if (side_effects_p (x))
6604 if (cond == EQ && rtx_equal_p (x, reg))
6607 /* If X is (abs REG) and we know something about REG's relationship
6608 with zero, we may be able to simplify this. */
6610 if (code == ABS && rtx_equal_p (XEXP (x, 0), reg) && val == const0_rtx)
6613 case GE: case GT: case EQ:
6616 return gen_unary (NEG, GET_MODE (XEXP (x, 0)), GET_MODE (XEXP (x, 0)),
6620 /* The only other cases we handle are MIN, MAX, and comparisons if the
6621 operands are the same as REG and VAL. */
6623 else if (GET_RTX_CLASS (code) == '<' || GET_RTX_CLASS (code) == 'c')
6625 if (rtx_equal_p (XEXP (x, 0), val))
6626 cond = swap_condition (cond), temp = val, val = reg, reg = temp;
6628 if (rtx_equal_p (XEXP (x, 0), reg) && rtx_equal_p (XEXP (x, 1), val))
6630 if (GET_RTX_CLASS (code) == '<')
6631 return (comparison_dominates_p (cond, code) ? const_true_rtx
6632 : (comparison_dominates_p (cond,
6633 reverse_condition (code))
6636 else if (code == SMAX || code == SMIN
6637 || code == UMIN || code == UMAX)
6639 int unsignedp = (code == UMIN || code == UMAX);
6641 if (code == SMAX || code == UMAX)
6642 cond = reverse_condition (cond);
6647 return unsignedp ? x : XEXP (x, 1);
6649 return unsignedp ? x : XEXP (x, 0);
6651 return unsignedp ? XEXP (x, 1) : x;
6653 return unsignedp ? XEXP (x, 0) : x;
6659 fmt = GET_RTX_FORMAT (code);
6660 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
6663 SUBST (XEXP (x, i), known_cond (XEXP (x, i), cond, reg, val));
6664 else if (fmt[i] == 'E')
6665 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
6666 SUBST (XVECEXP (x, i, j), known_cond (XVECEXP (x, i, j),
6673 /* See if X and Y are equal for the purposes of seeing if we can rewrite an
6674 assignment as a field assignment. */
6677 rtx_equal_for_field_assignment_p (x, y)
6683 if (x == y || rtx_equal_p (x, y))
6686 if (x == 0 || y == 0 || GET_MODE (x) != GET_MODE (y))
6689 /* Check for a paradoxical SUBREG of a MEM compared with the MEM.
6690 Note that all SUBREGs of MEM are paradoxical; otherwise they
6691 would have been rewritten. */
6692 if (GET_CODE (x) == MEM && GET_CODE (y) == SUBREG
6693 && GET_CODE (SUBREG_REG (y)) == MEM
6694 && rtx_equal_p (SUBREG_REG (y),
6695 gen_lowpart_for_combine (GET_MODE (SUBREG_REG (y)), x)))
6698 if (GET_CODE (y) == MEM && GET_CODE (x) == SUBREG
6699 && GET_CODE (SUBREG_REG (x)) == MEM
6700 && rtx_equal_p (SUBREG_REG (x),
6701 gen_lowpart_for_combine (GET_MODE (SUBREG_REG (x)), y)))
6704 last_x = get_last_value (x);
6705 last_y = get_last_value (y);
6707 return ((last_x != 0
6708 && GET_CODE (last_x) != CLOBBER
6709 && rtx_equal_for_field_assignment_p (last_x, y))
6711 && GET_CODE (last_y) != CLOBBER
6712 && rtx_equal_for_field_assignment_p (x, last_y))
6713 || (last_x != 0 && last_y != 0
6714 && GET_CODE (last_x) != CLOBBER
6715 && GET_CODE (last_y) != CLOBBER
6716 && rtx_equal_for_field_assignment_p (last_x, last_y)));
6719 /* See if X, a SET operation, can be rewritten as a bit-field assignment.
6720 Return that assignment if so.
6722 We only handle the most common cases. */
6725 make_field_assignment (x)
6728 rtx dest = SET_DEST (x);
6729 rtx src = SET_SRC (x);
6735 enum machine_mode mode;
6737 /* If SRC was (and (not (ashift (const_int 1) POS)) DEST), this is
6738 a clear of a one-bit field. We will have changed it to
6739 (and (rotate (const_int -2) POS) DEST), so check for that. Also check
6742 if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == ROTATE
6743 && GET_CODE (XEXP (XEXP (src, 0), 0)) == CONST_INT
6744 && INTVAL (XEXP (XEXP (src, 0), 0)) == -2
6745 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
6747 assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1),
6750 return gen_rtx (SET, VOIDmode, assign, const0_rtx);
6754 else if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == SUBREG
6755 && subreg_lowpart_p (XEXP (src, 0))
6756 && (GET_MODE_SIZE (GET_MODE (XEXP (src, 0)))
6757 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (src, 0)))))
6758 && GET_CODE (SUBREG_REG (XEXP (src, 0))) == ROTATE
6759 && INTVAL (XEXP (SUBREG_REG (XEXP (src, 0)), 0)) == -2
6760 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
6762 assign = make_extraction (VOIDmode, dest, 0,
6763 XEXP (SUBREG_REG (XEXP (src, 0)), 1),
6766 return gen_rtx (SET, VOIDmode, assign, const0_rtx);
6770 /* If SRC is (ior (ashift (const_int 1) POS) DEST), this is a set of a
6772 else if (GET_CODE (src) == IOR && GET_CODE (XEXP (src, 0)) == ASHIFT
6773 && XEXP (XEXP (src, 0), 0) == const1_rtx
6774 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
6776 assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1),
6779 return gen_rtx (SET, VOIDmode, assign, const1_rtx);
6783 /* The other case we handle is assignments into a constant-position
6784 field. They look like (ior/xor (and DEST C1) OTHER). If C1 represents
6785 a mask that has all one bits except for a group of zero bits and
6786 OTHER is known to have zeros where C1 has ones, this is such an
6787 assignment. Compute the position and length from C1. Shift OTHER
6788 to the appropriate position, force it to the required mode, and
6789 make the extraction. Check for the AND in both operands. */
6791 if (GET_CODE (src) != IOR && GET_CODE (src) != XOR)
6794 rhs = expand_compound_operation (XEXP (src, 0));
6795 lhs = expand_compound_operation (XEXP (src, 1));
6797 if (GET_CODE (rhs) == AND
6798 && GET_CODE (XEXP (rhs, 1)) == CONST_INT
6799 && rtx_equal_for_field_assignment_p (XEXP (rhs, 0), dest))
6800 c1 = INTVAL (XEXP (rhs, 1)), other = lhs;
6801 else if (GET_CODE (lhs) == AND
6802 && GET_CODE (XEXP (lhs, 1)) == CONST_INT
6803 && rtx_equal_for_field_assignment_p (XEXP (lhs, 0), dest))
6804 c1 = INTVAL (XEXP (lhs, 1)), other = rhs;
6808 pos = get_pos_from_mask ((~ c1) & GET_MODE_MASK (GET_MODE (dest)), &len);
6809 if (pos < 0 || pos + len > GET_MODE_BITSIZE (GET_MODE (dest))
6810 || (GET_MODE_BITSIZE (GET_MODE (other)) <= HOST_BITS_PER_WIDE_INT
6811 && (c1 & nonzero_bits (other, GET_MODE (other))) != 0))
6814 assign = make_extraction (VOIDmode, dest, pos, NULL_RTX, len, 1, 1, 0);
6818 /* The mode to use for the source is the mode of the assignment, or of
6819 what is inside a possible STRICT_LOW_PART. */
6820 mode = (GET_CODE (assign) == STRICT_LOW_PART
6821 ? GET_MODE (XEXP (assign, 0)) : GET_MODE (assign));
6823 /* Shift OTHER right POS places and make it the source, restricting it
6824 to the proper length and mode. */
6826 src = force_to_mode (simplify_shift_const (NULL_RTX, LSHIFTRT,
6827 GET_MODE (src), other, pos),
6829 GET_MODE_BITSIZE (mode) >= HOST_BITS_PER_WIDE_INT
6830 ? GET_MODE_MASK (mode)
6831 : ((HOST_WIDE_INT) 1 << len) - 1,
6834 return gen_rtx_combine (SET, VOIDmode, assign, src);
6837 /* See if X is of the form (+ (* a c) (* b c)) and convert to (* (+ a b) c)
6841 apply_distributive_law (x)
6844 enum rtx_code code = GET_CODE (x);
6845 rtx lhs, rhs, other;
6847 enum rtx_code inner_code;
6849 /* Distributivity is not true for floating point.
6850 It can change the value. So don't do it.
6851 -- rms and moshier@world.std.com. */
6852 if (FLOAT_MODE_P (GET_MODE (x)))
6855 /* The outer operation can only be one of the following: */
6856 if (code != IOR && code != AND && code != XOR
6857 && code != PLUS && code != MINUS)
6860 lhs = XEXP (x, 0), rhs = XEXP (x, 1);
6862 /* If either operand is a primitive we can't do anything, so get out
6864 if (GET_RTX_CLASS (GET_CODE (lhs)) == 'o'
6865 || GET_RTX_CLASS (GET_CODE (rhs)) == 'o')
6868 lhs = expand_compound_operation (lhs);
6869 rhs = expand_compound_operation (rhs);
6870 inner_code = GET_CODE (lhs);
6871 if (inner_code != GET_CODE (rhs))
6874 /* See if the inner and outer operations distribute. */
6881 /* These all distribute except over PLUS. */
6882 if (code == PLUS || code == MINUS)
6887 if (code != PLUS && code != MINUS)
6892 /* This is also a multiply, so it distributes over everything. */
6896 /* Non-paradoxical SUBREGs distributes over all operations, provided
6897 the inner modes and word numbers are the same, this is an extraction
6898 of a low-order part, we don't convert an fp operation to int or
6899 vice versa, and we would not be converting a single-word
6900 operation into a multi-word operation. The latter test is not
6901 required, but it prevents generating unneeded multi-word operations.
6902 Some of the previous tests are redundant given the latter test, but
6903 are retained because they are required for correctness.
6905 We produce the result slightly differently in this case. */
6907 if (GET_MODE (SUBREG_REG (lhs)) != GET_MODE (SUBREG_REG (rhs))
6908 || SUBREG_WORD (lhs) != SUBREG_WORD (rhs)
6909 || ! subreg_lowpart_p (lhs)
6910 || (GET_MODE_CLASS (GET_MODE (lhs))
6911 != GET_MODE_CLASS (GET_MODE (SUBREG_REG (lhs))))
6912 || (GET_MODE_SIZE (GET_MODE (lhs))
6913 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs))))
6914 || GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs))) > UNITS_PER_WORD)
6917 tem = gen_binary (code, GET_MODE (SUBREG_REG (lhs)),
6918 SUBREG_REG (lhs), SUBREG_REG (rhs));
6919 return gen_lowpart_for_combine (GET_MODE (x), tem);
6925 /* Set LHS and RHS to the inner operands (A and B in the example
6926 above) and set OTHER to the common operand (C in the example).
6927 These is only one way to do this unless the inner operation is
6929 if (GET_RTX_CLASS (inner_code) == 'c'
6930 && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 0)))
6931 other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 1);
6932 else if (GET_RTX_CLASS (inner_code) == 'c'
6933 && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 1)))
6934 other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 0);
6935 else if (GET_RTX_CLASS (inner_code) == 'c'
6936 && rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 0)))
6937 other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 1);
6938 else if (rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 1)))
6939 other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 0);
6943 /* Form the new inner operation, seeing if it simplifies first. */
6944 tem = gen_binary (code, GET_MODE (x), lhs, rhs);
6946 /* There is one exception to the general way of distributing:
6947 (a ^ b) | (a ^ c) -> (~a) & (b ^ c) */
6948 if (code == XOR && inner_code == IOR)
6951 other = gen_unary (NOT, GET_MODE (x), GET_MODE (x), other);
6954 /* We may be able to continuing distributing the result, so call
6955 ourselves recursively on the inner operation before forming the
6956 outer operation, which we return. */
6957 return gen_binary (inner_code, GET_MODE (x),
6958 apply_distributive_law (tem), other);
6961 /* We have X, a logical `and' of VAROP with the constant CONSTOP, to be done
6964 Return an equivalent form, if different from X. Otherwise, return X. If
6965 X is zero, we are to always construct the equivalent form. */
6968 simplify_and_const_int (x, mode, varop, constop)
6970 enum machine_mode mode;
6972 unsigned HOST_WIDE_INT constop;
6974 unsigned HOST_WIDE_INT nonzero;
6975 int width = GET_MODE_BITSIZE (mode);
6978 /* Simplify VAROP knowing that we will be only looking at some of the
6980 varop = force_to_mode (varop, mode, constop, NULL_RTX, 0);
6982 /* If VAROP is a CLOBBER, we will fail so return it; if it is a
6983 CONST_INT, we are done. */
6984 if (GET_CODE (varop) == CLOBBER || GET_CODE (varop) == CONST_INT)
6987 /* See what bits may be nonzero in VAROP. Unlike the general case of
6988 a call to nonzero_bits, here we don't care about bits outside
6991 nonzero = nonzero_bits (varop, mode) & GET_MODE_MASK (mode);
6993 /* If this would be an entire word for the target, but is not for
6994 the host, then sign-extend on the host so that the number will look
6995 the same way on the host that it would on the target.
6997 For example, when building a 64 bit alpha hosted 32 bit sparc
6998 targeted compiler, then we want the 32 bit unsigned value -1 to be
6999 represented as a 64 bit value -1, and not as 0x00000000ffffffff.
7000 The later confuses the sparc backend. */
7002 if (BITS_PER_WORD < HOST_BITS_PER_WIDE_INT && BITS_PER_WORD == width
7003 && (nonzero & ((HOST_WIDE_INT) 1 << (width - 1))))
7004 nonzero |= ((HOST_WIDE_INT) (-1) << width);
7006 /* Turn off all bits in the constant that are known to already be zero.
7007 Thus, if the AND isn't needed at all, we will have CONSTOP == NONZERO_BITS
7008 which is tested below. */
7012 /* If we don't have any bits left, return zero. */
7016 /* If VAROP is a NEG of something known to be zero or 1 and CONSTOP is
7017 a power of two, we can replace this with a ASHIFT. */
7018 if (GET_CODE (varop) == NEG && nonzero_bits (XEXP (varop, 0), mode) == 1
7019 && (i = exact_log2 (constop)) >= 0)
7020 return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (varop, 0), i);
7022 /* If VAROP is an IOR or XOR, apply the AND to both branches of the IOR
7023 or XOR, then try to apply the distributive law. This may eliminate
7024 operations if either branch can be simplified because of the AND.
7025 It may also make some cases more complex, but those cases probably
7026 won't match a pattern either with or without this. */
7028 if (GET_CODE (varop) == IOR || GET_CODE (varop) == XOR)
7030 gen_lowpart_for_combine
7032 apply_distributive_law
7033 (gen_binary (GET_CODE (varop), GET_MODE (varop),
7034 simplify_and_const_int (NULL_RTX, GET_MODE (varop),
7035 XEXP (varop, 0), constop),
7036 simplify_and_const_int (NULL_RTX, GET_MODE (varop),
7037 XEXP (varop, 1), constop))));
7039 /* Get VAROP in MODE. Try to get a SUBREG if not. Don't make a new SUBREG
7040 if we already had one (just check for the simplest cases). */
7041 if (x && GET_CODE (XEXP (x, 0)) == SUBREG
7042 && GET_MODE (XEXP (x, 0)) == mode
7043 && SUBREG_REG (XEXP (x, 0)) == varop)
7044 varop = XEXP (x, 0);
7046 varop = gen_lowpart_for_combine (mode, varop);
7048 /* If we can't make the SUBREG, try to return what we were given. */
7049 if (GET_CODE (varop) == CLOBBER)
7050 return x ? x : varop;
7052 /* If we are only masking insignificant bits, return VAROP. */
7053 if (constop == nonzero)
7056 /* Otherwise, return an AND. See how much, if any, of X we can use. */
7057 else if (x == 0 || GET_CODE (x) != AND || GET_MODE (x) != mode)
7058 x = gen_binary (AND, mode, varop, GEN_INT (constop));
7062 if (GET_CODE (XEXP (x, 1)) != CONST_INT
7063 || INTVAL (XEXP (x, 1)) != constop)
7064 SUBST (XEXP (x, 1), GEN_INT (constop));
7066 SUBST (XEXP (x, 0), varop);
7072 /* Given an expression, X, compute which bits in X can be non-zero.
7073 We don't care about bits outside of those defined in MODE.
7075 For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is
7076 a shift, AND, or zero_extract, we can do better. */
7078 static unsigned HOST_WIDE_INT
7079 nonzero_bits (x, mode)
7081 enum machine_mode mode;
7083 unsigned HOST_WIDE_INT nonzero = GET_MODE_MASK (mode);
7084 unsigned HOST_WIDE_INT inner_nz;
7086 int mode_width = GET_MODE_BITSIZE (mode);
7089 /* For floating-point values, assume all bits are needed. */
7090 if (FLOAT_MODE_P (GET_MODE (x)) || FLOAT_MODE_P (mode))
7093 /* If X is wider than MODE, use its mode instead. */
7094 if (GET_MODE_BITSIZE (GET_MODE (x)) > mode_width)
7096 mode = GET_MODE (x);
7097 nonzero = GET_MODE_MASK (mode);
7098 mode_width = GET_MODE_BITSIZE (mode);
7101 if (mode_width > HOST_BITS_PER_WIDE_INT)
7102 /* Our only callers in this case look for single bit values. So
7103 just return the mode mask. Those tests will then be false. */
7106 #ifndef WORD_REGISTER_OPERATIONS
7107 /* If MODE is wider than X, but both are a single word for both the host
7108 and target machines, we can compute this from which bits of the
7109 object might be nonzero in its own mode, taking into account the fact
7110 that on many CISC machines, accessing an object in a wider mode
7111 causes the high-order bits to become undefined. So they are
7112 not known to be zero. */
7114 if (GET_MODE (x) != VOIDmode && GET_MODE (x) != mode
7115 && GET_MODE_BITSIZE (GET_MODE (x)) <= BITS_PER_WORD
7116 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
7117 && GET_MODE_BITSIZE (mode) > GET_MODE_BITSIZE (GET_MODE (x)))
7119 nonzero &= nonzero_bits (x, GET_MODE (x));
7120 nonzero |= GET_MODE_MASK (mode) & ~ GET_MODE_MASK (GET_MODE (x));
7125 code = GET_CODE (x);
7129 #ifdef POINTERS_EXTEND_UNSIGNED
7130 /* If pointers extend unsigned and this is a pointer in Pmode, say that
7131 all the bits above ptr_mode are known to be zero. */
7132 if (POINTERS_EXTEND_UNSIGNED && GET_MODE (x) == Pmode
7133 && REGNO_POINTER_FLAG (REGNO (x)))
7134 nonzero &= GET_MODE_MASK (ptr_mode);
7137 #ifdef STACK_BOUNDARY
7138 /* If this is the stack pointer, we may know something about its
7139 alignment. If PUSH_ROUNDING is defined, it is possible for the
7140 stack to be momentarily aligned only to that amount, so we pick
7141 the least alignment. */
7143 /* We can't check for arg_pointer_rtx here, because it is not
7144 guaranteed to have as much alignment as the stack pointer.
7145 In particular, in the Irix6 n64 ABI, the stack has 128 bit
7146 alignment but the argument pointer has only 64 bit alignment. */
7148 if (x == stack_pointer_rtx || x == frame_pointer_rtx
7149 || x == hard_frame_pointer_rtx
7150 || (REGNO (x) >= FIRST_VIRTUAL_REGISTER
7151 && REGNO (x) <= LAST_VIRTUAL_REGISTER))
7153 int sp_alignment = STACK_BOUNDARY / BITS_PER_UNIT;
7155 #ifdef PUSH_ROUNDING
7156 if (REGNO (x) == STACK_POINTER_REGNUM)
7157 sp_alignment = MIN (PUSH_ROUNDING (1), sp_alignment);
7160 /* We must return here, otherwise we may get a worse result from
7161 one of the choices below. There is nothing useful below as
7162 far as the stack pointer is concerned. */
7163 return nonzero &= ~ (sp_alignment - 1);
7167 /* If X is a register whose nonzero bits value is current, use it.
7168 Otherwise, if X is a register whose value we can find, use that
7169 value. Otherwise, use the previously-computed global nonzero bits
7170 for this register. */
7172 if (reg_last_set_value[REGNO (x)] != 0
7173 && reg_last_set_mode[REGNO (x)] == mode
7174 && (reg_n_sets[REGNO (x)] == 1
7175 || reg_last_set_label[REGNO (x)] == label_tick)
7176 && INSN_CUID (reg_last_set[REGNO (x)]) < subst_low_cuid)
7177 return reg_last_set_nonzero_bits[REGNO (x)];
7179 tem = get_last_value (x);
7183 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
7184 /* If X is narrower than MODE and TEM is a non-negative
7185 constant that would appear negative in the mode of X,
7186 sign-extend it for use in reg_nonzero_bits because some
7187 machines (maybe most) will actually do the sign-extension
7188 and this is the conservative approach.
7190 ??? For 2.5, try to tighten up the MD files in this regard
7191 instead of this kludge. */
7193 if (GET_MODE_BITSIZE (GET_MODE (x)) < mode_width
7194 && GET_CODE (tem) == CONST_INT
7196 && 0 != (INTVAL (tem)
7197 & ((HOST_WIDE_INT) 1
7198 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
7199 tem = GEN_INT (INTVAL (tem)
7200 | ((HOST_WIDE_INT) (-1)
7201 << GET_MODE_BITSIZE (GET_MODE (x))));
7203 return nonzero_bits (tem, mode);
7205 else if (nonzero_sign_valid && reg_nonzero_bits[REGNO (x)])
7206 return reg_nonzero_bits[REGNO (x)] & nonzero;
7211 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
7212 /* If X is negative in MODE, sign-extend the value. */
7213 if (INTVAL (x) > 0 && mode_width < BITS_PER_WORD
7214 && 0 != (INTVAL (x) & ((HOST_WIDE_INT) 1 << (mode_width - 1))))
7215 return (INTVAL (x) | ((HOST_WIDE_INT) (-1) << mode_width));
7221 #ifdef LOAD_EXTEND_OP
7222 /* In many, if not most, RISC machines, reading a byte from memory
7223 zeros the rest of the register. Noticing that fact saves a lot
7224 of extra zero-extends. */
7225 if (LOAD_EXTEND_OP (GET_MODE (x)) == ZERO_EXTEND)
7226 nonzero &= GET_MODE_MASK (GET_MODE (x));
7236 /* If this produces an integer result, we know which bits are set.
7237 Code here used to clear bits outside the mode of X, but that is
7240 if (GET_MODE_CLASS (mode) == MODE_INT
7241 && mode_width <= HOST_BITS_PER_WIDE_INT)
7242 nonzero = STORE_FLAG_VALUE;
7246 if (num_sign_bit_copies (XEXP (x, 0), GET_MODE (x))
7247 == GET_MODE_BITSIZE (GET_MODE (x)))
7250 if (GET_MODE_SIZE (GET_MODE (x)) < mode_width)
7251 nonzero |= (GET_MODE_MASK (mode) & ~ GET_MODE_MASK (GET_MODE (x)));
7255 if (num_sign_bit_copies (XEXP (x, 0), GET_MODE (x))
7256 == GET_MODE_BITSIZE (GET_MODE (x)))
7261 nonzero &= (nonzero_bits (XEXP (x, 0), mode) & GET_MODE_MASK (mode));
7265 nonzero &= nonzero_bits (XEXP (x, 0), mode);
7266 if (GET_MODE (XEXP (x, 0)) != VOIDmode)
7267 nonzero &= GET_MODE_MASK (GET_MODE (XEXP (x, 0)));
7271 /* If the sign bit is known clear, this is the same as ZERO_EXTEND.
7272 Otherwise, show all the bits in the outer mode but not the inner
7274 inner_nz = nonzero_bits (XEXP (x, 0), mode);
7275 if (GET_MODE (XEXP (x, 0)) != VOIDmode)
7277 inner_nz &= GET_MODE_MASK (GET_MODE (XEXP (x, 0)));
7280 << (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - 1))))
7281 inner_nz |= (GET_MODE_MASK (mode)
7282 & ~ GET_MODE_MASK (GET_MODE (XEXP (x, 0))));
7285 nonzero &= inner_nz;
7289 nonzero &= (nonzero_bits (XEXP (x, 0), mode)
7290 & nonzero_bits (XEXP (x, 1), mode));
7294 case UMIN: case UMAX: case SMIN: case SMAX:
7295 nonzero &= (nonzero_bits (XEXP (x, 0), mode)
7296 | nonzero_bits (XEXP (x, 1), mode));
7299 case PLUS: case MINUS:
7301 case DIV: case UDIV:
7302 case MOD: case UMOD:
7303 /* We can apply the rules of arithmetic to compute the number of
7304 high- and low-order zero bits of these operations. We start by
7305 computing the width (position of the highest-order non-zero bit)
7306 and the number of low-order zero bits for each value. */
7308 unsigned HOST_WIDE_INT nz0 = nonzero_bits (XEXP (x, 0), mode);
7309 unsigned HOST_WIDE_INT nz1 = nonzero_bits (XEXP (x, 1), mode);
7310 int width0 = floor_log2 (nz0) + 1;
7311 int width1 = floor_log2 (nz1) + 1;
7312 int low0 = floor_log2 (nz0 & -nz0);
7313 int low1 = floor_log2 (nz1 & -nz1);
7314 HOST_WIDE_INT op0_maybe_minusp
7315 = (nz0 & ((HOST_WIDE_INT) 1 << (mode_width - 1)));
7316 HOST_WIDE_INT op1_maybe_minusp
7317 = (nz1 & ((HOST_WIDE_INT) 1 << (mode_width - 1)));
7318 int result_width = mode_width;
7324 result_width = MAX (width0, width1) + 1;
7325 result_low = MIN (low0, low1);
7328 result_low = MIN (low0, low1);
7331 result_width = width0 + width1;
7332 result_low = low0 + low1;
7335 if (! op0_maybe_minusp && ! op1_maybe_minusp)
7336 result_width = width0;
7339 result_width = width0;
7342 if (! op0_maybe_minusp && ! op1_maybe_minusp)
7343 result_width = MIN (width0, width1);
7344 result_low = MIN (low0, low1);
7347 result_width = MIN (width0, width1);
7348 result_low = MIN (low0, low1);
7352 if (result_width < mode_width)
7353 nonzero &= ((HOST_WIDE_INT) 1 << result_width) - 1;
7356 nonzero &= ~ (((HOST_WIDE_INT) 1 << result_low) - 1);
7361 if (GET_CODE (XEXP (x, 1)) == CONST_INT
7362 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT)
7363 nonzero &= ((HOST_WIDE_INT) 1 << INTVAL (XEXP (x, 1))) - 1;
7367 /* If this is a SUBREG formed for a promoted variable that has
7368 been zero-extended, we know that at least the high-order bits
7369 are zero, though others might be too. */
7371 if (SUBREG_PROMOTED_VAR_P (x) && SUBREG_PROMOTED_UNSIGNED_P (x))
7372 nonzero = (GET_MODE_MASK (GET_MODE (x))
7373 & nonzero_bits (SUBREG_REG (x), GET_MODE (x)));
7375 /* If the inner mode is a single word for both the host and target
7376 machines, we can compute this from which bits of the inner
7377 object might be nonzero. */
7378 if (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x))) <= BITS_PER_WORD
7379 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x)))
7380 <= HOST_BITS_PER_WIDE_INT))
7382 nonzero &= nonzero_bits (SUBREG_REG (x), mode);
7384 #ifndef WORD_REGISTER_OPERATIONS
7385 /* On many CISC machines, accessing an object in a wider mode
7386 causes the high-order bits to become undefined. So they are
7387 not known to be zero. */
7388 if (GET_MODE_SIZE (GET_MODE (x))
7389 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
7390 nonzero |= (GET_MODE_MASK (GET_MODE (x))
7391 & ~ GET_MODE_MASK (GET_MODE (SUBREG_REG (x))));
7400 /* The nonzero bits are in two classes: any bits within MODE
7401 that aren't in GET_MODE (x) are always significant. The rest of the
7402 nonzero bits are those that are significant in the operand of
7403 the shift when shifted the appropriate number of bits. This
7404 shows that high-order bits are cleared by the right shift and
7405 low-order bits by left shifts. */
7406 if (GET_CODE (XEXP (x, 1)) == CONST_INT
7407 && INTVAL (XEXP (x, 1)) >= 0
7408 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT)
7410 enum machine_mode inner_mode = GET_MODE (x);
7411 int width = GET_MODE_BITSIZE (inner_mode);
7412 int count = INTVAL (XEXP (x, 1));
7413 unsigned HOST_WIDE_INT mode_mask = GET_MODE_MASK (inner_mode);
7414 unsigned HOST_WIDE_INT op_nonzero = nonzero_bits (XEXP (x, 0), mode);
7415 unsigned HOST_WIDE_INT inner = op_nonzero & mode_mask;
7416 unsigned HOST_WIDE_INT outer = 0;
7418 if (mode_width > width)
7419 outer = (op_nonzero & nonzero & ~ mode_mask);
7421 if (code == LSHIFTRT)
7423 else if (code == ASHIFTRT)
7427 /* If the sign bit may have been nonzero before the shift, we
7428 need to mark all the places it could have been copied to
7429 by the shift as possibly nonzero. */
7430 if (inner & ((HOST_WIDE_INT) 1 << (width - 1 - count)))
7431 inner |= (((HOST_WIDE_INT) 1 << count) - 1) << (width - count);
7433 else if (code == ASHIFT)
7436 inner = ((inner << (count % width)
7437 | (inner >> (width - (count % width)))) & mode_mask);
7439 nonzero &= (outer | inner);
7444 /* This is at most the number of bits in the mode. */
7445 nonzero = ((HOST_WIDE_INT) 1 << (floor_log2 (mode_width) + 1)) - 1;
7449 nonzero &= (nonzero_bits (XEXP (x, 1), mode)
7450 | nonzero_bits (XEXP (x, 2), mode));
7457 /* Return the number of bits at the high-order end of X that are known to
7458 be equal to the sign bit. X will be used in mode MODE; if MODE is
7459 VOIDmode, X will be used in its own mode. The returned value will always
7460 be between 1 and the number of bits in MODE. */
7463 num_sign_bit_copies (x, mode)
7465 enum machine_mode mode;
7467 enum rtx_code code = GET_CODE (x);
7469 int num0, num1, result;
7470 unsigned HOST_WIDE_INT nonzero;
7473 /* If we weren't given a mode, use the mode of X. If the mode is still
7474 VOIDmode, we don't know anything. Likewise if one of the modes is
7477 if (mode == VOIDmode)
7478 mode = GET_MODE (x);
7480 if (mode == VOIDmode || FLOAT_MODE_P (mode) || FLOAT_MODE_P (GET_MODE (x)))
7483 bitwidth = GET_MODE_BITSIZE (mode);
7485 /* For a smaller object, just ignore the high bits. */
7486 if (bitwidth < GET_MODE_BITSIZE (GET_MODE (x)))
7487 return MAX (1, (num_sign_bit_copies (x, GET_MODE (x))
7488 - (GET_MODE_BITSIZE (GET_MODE (x)) - bitwidth)));
7490 #ifndef WORD_REGISTER_OPERATIONS
7491 /* If this machine does not do all register operations on the entire
7492 register and MODE is wider than the mode of X, we can say nothing
7493 at all about the high-order bits. */
7494 if (GET_MODE (x) != VOIDmode && bitwidth > GET_MODE_BITSIZE (GET_MODE (x)))
7502 #ifdef POINTERS_EXTEND_UNSIGNED
7503 /* If pointers extend signed and this is a pointer in Pmode, say that
7504 all the bits above ptr_mode are known to be sign bit copies. */
7505 if (! POINTERS_EXTEND_UNSIGNED && GET_MODE (x) == Pmode && mode == Pmode
7506 && REGNO_POINTER_FLAG (REGNO (x)))
7507 return GET_MODE_BITSIZE (Pmode) - GET_MODE_BITSIZE (ptr_mode) + 1;
7510 if (reg_last_set_value[REGNO (x)] != 0
7511 && reg_last_set_mode[REGNO (x)] == mode
7512 && (reg_n_sets[REGNO (x)] == 1
7513 || reg_last_set_label[REGNO (x)] == label_tick)
7514 && INSN_CUID (reg_last_set[REGNO (x)]) < subst_low_cuid)
7515 return reg_last_set_sign_bit_copies[REGNO (x)];
7517 tem = get_last_value (x);
7519 return num_sign_bit_copies (tem, mode);
7521 if (nonzero_sign_valid && reg_sign_bit_copies[REGNO (x)] != 0)
7522 return reg_sign_bit_copies[REGNO (x)];
7526 #ifdef LOAD_EXTEND_OP
7527 /* Some RISC machines sign-extend all loads of smaller than a word. */
7528 if (LOAD_EXTEND_OP (GET_MODE (x)) == SIGN_EXTEND)
7529 return MAX (1, bitwidth - GET_MODE_BITSIZE (GET_MODE (x)) + 1);
7534 /* If the constant is negative, take its 1's complement and remask.
7535 Then see how many zero bits we have. */
7536 nonzero = INTVAL (x) & GET_MODE_MASK (mode);
7537 if (bitwidth <= HOST_BITS_PER_WIDE_INT
7538 && (nonzero & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0)
7539 nonzero = (~ nonzero) & GET_MODE_MASK (mode);
7541 return (nonzero == 0 ? bitwidth : bitwidth - floor_log2 (nonzero) - 1);
7544 /* If this is a SUBREG for a promoted object that is sign-extended
7545 and we are looking at it in a wider mode, we know that at least the
7546 high-order bits are known to be sign bit copies. */
7548 if (SUBREG_PROMOTED_VAR_P (x) && ! SUBREG_PROMOTED_UNSIGNED_P (x))
7549 return MAX (bitwidth - GET_MODE_BITSIZE (GET_MODE (x)) + 1,
7550 num_sign_bit_copies (SUBREG_REG (x), mode));
7552 /* For a smaller object, just ignore the high bits. */
7553 if (bitwidth <= GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x))))
7555 num0 = num_sign_bit_copies (SUBREG_REG (x), VOIDmode);
7556 return MAX (1, (num0
7557 - (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x)))
7561 #ifdef WORD_REGISTER_OPERATIONS
7562 #ifdef LOAD_EXTEND_OP
7563 /* For paradoxical SUBREGs on machines where all register operations
7564 affect the entire register, just look inside. Note that we are
7565 passing MODE to the recursive call, so the number of sign bit copies
7566 will remain relative to that mode, not the inner mode. */
7568 /* This works only if loads sign extend. Otherwise, if we get a
7569 reload for the inner part, it may be loaded from the stack, and
7570 then we lose all sign bit copies that existed before the store
7573 if ((GET_MODE_SIZE (GET_MODE (x))
7574 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
7575 && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (x))) == SIGN_EXTEND)
7576 return num_sign_bit_copies (SUBREG_REG (x), mode);
7582 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
7583 return MAX (1, bitwidth - INTVAL (XEXP (x, 1)));
7587 return (bitwidth - GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
7588 + num_sign_bit_copies (XEXP (x, 0), VOIDmode));
7591 /* For a smaller object, just ignore the high bits. */
7592 num0 = num_sign_bit_copies (XEXP (x, 0), VOIDmode);
7593 return MAX (1, (num0 - (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
7597 return num_sign_bit_copies (XEXP (x, 0), mode);
7599 case ROTATE: case ROTATERT:
7600 /* If we are rotating left by a number of bits less than the number
7601 of sign bit copies, we can just subtract that amount from the
7603 if (GET_CODE (XEXP (x, 1)) == CONST_INT
7604 && INTVAL (XEXP (x, 1)) >= 0 && INTVAL (XEXP (x, 1)) < bitwidth)
7606 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
7607 return MAX (1, num0 - (code == ROTATE ? INTVAL (XEXP (x, 1))
7608 : bitwidth - INTVAL (XEXP (x, 1))));
7613 /* In general, this subtracts one sign bit copy. But if the value
7614 is known to be positive, the number of sign bit copies is the
7615 same as that of the input. Finally, if the input has just one bit
7616 that might be nonzero, all the bits are copies of the sign bit. */
7617 nonzero = nonzero_bits (XEXP (x, 0), mode);
7621 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
7623 && bitwidth <= HOST_BITS_PER_WIDE_INT
7624 && (((HOST_WIDE_INT) 1 << (bitwidth - 1)) & nonzero))
7629 case IOR: case AND: case XOR:
7630 case SMIN: case SMAX: case UMIN: case UMAX:
7631 /* Logical operations will preserve the number of sign-bit copies.
7632 MIN and MAX operations always return one of the operands. */
7633 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
7634 num1 = num_sign_bit_copies (XEXP (x, 1), mode);
7635 return MIN (num0, num1);
7637 case PLUS: case MINUS:
7638 /* For addition and subtraction, we can have a 1-bit carry. However,
7639 if we are subtracting 1 from a positive number, there will not
7640 be such a carry. Furthermore, if the positive number is known to
7641 be 0 or 1, we know the result is either -1 or 0. */
7643 if (code == PLUS && XEXP (x, 1) == constm1_rtx
7644 && bitwidth <= HOST_BITS_PER_WIDE_INT)
7646 nonzero = nonzero_bits (XEXP (x, 0), mode);
7647 if ((((HOST_WIDE_INT) 1 << (bitwidth - 1)) & nonzero) == 0)
7648 return (nonzero == 1 || nonzero == 0 ? bitwidth
7649 : bitwidth - floor_log2 (nonzero) - 1);
7652 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
7653 num1 = num_sign_bit_copies (XEXP (x, 1), mode);
7654 return MAX (1, MIN (num0, num1) - 1);
7657 /* The number of bits of the product is the sum of the number of
7658 bits of both terms. However, unless one of the terms if known
7659 to be positive, we must allow for an additional bit since negating
7660 a negative number can remove one sign bit copy. */
7662 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
7663 num1 = num_sign_bit_copies (XEXP (x, 1), mode);
7665 result = bitwidth - (bitwidth - num0) - (bitwidth - num1);
7667 && bitwidth <= HOST_BITS_PER_WIDE_INT
7668 && ((nonzero_bits (XEXP (x, 0), mode)
7669 & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0)
7670 && ((nonzero_bits (XEXP (x, 1), mode)
7671 & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0))
7674 return MAX (1, result);
7677 /* The result must be <= the first operand. */
7678 return num_sign_bit_copies (XEXP (x, 0), mode);
7681 /* The result must be <= the scond operand. */
7682 return num_sign_bit_copies (XEXP (x, 1), mode);
7685 /* Similar to unsigned division, except that we have to worry about
7686 the case where the divisor is negative, in which case we have
7688 result = num_sign_bit_copies (XEXP (x, 0), mode);
7690 && bitwidth <= HOST_BITS_PER_WIDE_INT
7691 && (nonzero_bits (XEXP (x, 1), mode)
7692 & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0)
7698 result = num_sign_bit_copies (XEXP (x, 1), mode);
7700 && bitwidth <= HOST_BITS_PER_WIDE_INT
7701 && (nonzero_bits (XEXP (x, 1), mode)
7702 & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0)
7708 /* Shifts by a constant add to the number of bits equal to the
7710 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
7711 if (GET_CODE (XEXP (x, 1)) == CONST_INT
7712 && INTVAL (XEXP (x, 1)) > 0)
7713 num0 = MIN (bitwidth, num0 + INTVAL (XEXP (x, 1)));
7718 /* Left shifts destroy copies. */
7719 if (GET_CODE (XEXP (x, 1)) != CONST_INT
7720 || INTVAL (XEXP (x, 1)) < 0
7721 || INTVAL (XEXP (x, 1)) >= bitwidth)
7724 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
7725 return MAX (1, num0 - INTVAL (XEXP (x, 1)));
7728 num0 = num_sign_bit_copies (XEXP (x, 1), mode);
7729 num1 = num_sign_bit_copies (XEXP (x, 2), mode);
7730 return MIN (num0, num1);
7732 #if STORE_FLAG_VALUE == -1
7733 case EQ: case NE: case GE: case GT: case LE: case LT:
7734 case GEU: case GTU: case LEU: case LTU:
7739 /* If we haven't been able to figure it out by one of the above rules,
7740 see if some of the high-order bits are known to be zero. If so,
7741 count those bits and return one less than that amount. If we can't
7742 safely compute the mask for this mode, always return BITWIDTH. */
7744 if (bitwidth > HOST_BITS_PER_WIDE_INT)
7747 nonzero = nonzero_bits (x, mode);
7748 return (nonzero & ((HOST_WIDE_INT) 1 << (bitwidth - 1))
7749 ? 1 : bitwidth - floor_log2 (nonzero) - 1);
7752 /* Return the number of "extended" bits there are in X, when interpreted
7753 as a quantity in MODE whose signedness is indicated by UNSIGNEDP. For
7754 unsigned quantities, this is the number of high-order zero bits.
7755 For signed quantities, this is the number of copies of the sign bit
7756 minus 1. In both case, this function returns the number of "spare"
7757 bits. For example, if two quantities for which this function returns
7758 at least 1 are added, the addition is known not to overflow.
7760 This function will always return 0 unless called during combine, which
7761 implies that it must be called from a define_split. */
7764 extended_count (x, mode, unsignedp)
7766 enum machine_mode mode;
7769 if (nonzero_sign_valid == 0)
7773 ? (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
7774 && (GET_MODE_BITSIZE (mode) - 1
7775 - floor_log2 (nonzero_bits (x, mode))))
7776 : num_sign_bit_copies (x, mode) - 1);
7779 /* This function is called from `simplify_shift_const' to merge two
7780 outer operations. Specifically, we have already found that we need
7781 to perform operation *POP0 with constant *PCONST0 at the outermost
7782 position. We would now like to also perform OP1 with constant CONST1
7783 (with *POP0 being done last).
7785 Return 1 if we can do the operation and update *POP0 and *PCONST0 with
7786 the resulting operation. *PCOMP_P is set to 1 if we would need to
7787 complement the innermost operand, otherwise it is unchanged.
7789 MODE is the mode in which the operation will be done. No bits outside
7790 the width of this mode matter. It is assumed that the width of this mode
7791 is smaller than or equal to HOST_BITS_PER_WIDE_INT.
7793 If *POP0 or OP1 are NIL, it means no operation is required. Only NEG, PLUS,
7794 IOR, XOR, and AND are supported. We may set *POP0 to SET if the proper
7795 result is simply *PCONST0.
7797 If the resulting operation cannot be expressed as one operation, we
7798 return 0 and do not change *POP0, *PCONST0, and *PCOMP_P. */
7801 merge_outer_ops (pop0, pconst0, op1, const1, mode, pcomp_p)
7802 enum rtx_code *pop0;
7803 HOST_WIDE_INT *pconst0;
7805 HOST_WIDE_INT const1;
7806 enum machine_mode mode;
7809 enum rtx_code op0 = *pop0;
7810 HOST_WIDE_INT const0 = *pconst0;
7811 int width = GET_MODE_BITSIZE (mode);
7813 const0 &= GET_MODE_MASK (mode);
7814 const1 &= GET_MODE_MASK (mode);
7816 /* If OP0 is an AND, clear unimportant bits in CONST1. */
7820 /* If OP0 or OP1 is NIL, this is easy. Similarly if they are the same or
7823 if (op1 == NIL || op0 == SET)
7826 else if (op0 == NIL)
7827 op0 = op1, const0 = const1;
7829 else if (op0 == op1)
7851 /* Otherwise, if either is a PLUS or NEG, we can't do anything. */
7852 else if (op0 == PLUS || op1 == PLUS || op0 == NEG || op1 == NEG)
7855 /* If the two constants aren't the same, we can't do anything. The
7856 remaining six cases can all be done. */
7857 else if (const0 != const1)
7865 /* (a & b) | b == b */
7867 else /* op1 == XOR */
7868 /* (a ^ b) | b == a | b */
7874 /* (a & b) ^ b == (~a) & b */
7875 op0 = AND, *pcomp_p = 1;
7876 else /* op1 == IOR */
7877 /* (a | b) ^ b == a & ~b */
7878 op0 = AND, *pconst0 = ~ const0;
7883 /* (a | b) & b == b */
7885 else /* op1 == XOR */
7886 /* (a ^ b) & b) == (~a) & b */
7891 /* Check for NO-OP cases. */
7892 const0 &= GET_MODE_MASK (mode);
7894 && (op0 == IOR || op0 == XOR || op0 == PLUS))
7896 else if (const0 == 0 && op0 == AND)
7898 else if (const0 == GET_MODE_MASK (mode) && op0 == AND)
7901 /* If this would be an entire word for the target, but is not for
7902 the host, then sign-extend on the host so that the number will look
7903 the same way on the host that it would on the target.
7905 For example, when building a 64 bit alpha hosted 32 bit sparc
7906 targeted compiler, then we want the 32 bit unsigned value -1 to be
7907 represented as a 64 bit value -1, and not as 0x00000000ffffffff.
7908 The later confuses the sparc backend. */
7910 if (BITS_PER_WORD < HOST_BITS_PER_WIDE_INT && BITS_PER_WORD == width
7911 && (const0 & ((HOST_WIDE_INT) 1 << (width - 1))))
7912 const0 |= ((HOST_WIDE_INT) (-1) << width);
7920 /* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift.
7921 The result of the shift is RESULT_MODE. X, if non-zero, is an expression
7922 that we started with.
7924 The shift is normally computed in the widest mode we find in VAROP, as
7925 long as it isn't a different number of words than RESULT_MODE. Exceptions
7926 are ASHIFTRT and ROTATE, which are always done in their original mode, */
7929 simplify_shift_const (x, code, result_mode, varop, count)
7932 enum machine_mode result_mode;
7936 enum rtx_code orig_code = code;
7937 int orig_count = count;
7938 enum machine_mode mode = result_mode;
7939 enum machine_mode shift_mode, tmode;
7941 = (GET_MODE_SIZE (mode) + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD;
7942 /* We form (outer_op (code varop count) (outer_const)). */
7943 enum rtx_code outer_op = NIL;
7944 HOST_WIDE_INT outer_const = 0;
7946 int complement_p = 0;
7949 /* If we were given an invalid count, don't do anything except exactly
7950 what was requested. */
7952 if (count < 0 || count > GET_MODE_BITSIZE (mode))
7957 return gen_rtx (code, mode, varop, GEN_INT (count));
7960 /* Unless one of the branches of the `if' in this loop does a `continue',
7961 we will `break' the loop after the `if'. */
7965 /* If we have an operand of (clobber (const_int 0)), just return that
7967 if (GET_CODE (varop) == CLOBBER)
7970 /* If we discovered we had to complement VAROP, leave. Making a NOT
7971 here would cause an infinite loop. */
7975 /* Convert ROTATERT to ROTATE. */
7976 if (code == ROTATERT)
7977 code = ROTATE, count = GET_MODE_BITSIZE (result_mode) - count;
7979 /* We need to determine what mode we will do the shift in. If the
7980 shift is a right shift or a ROTATE, we must always do it in the mode
7981 it was originally done in. Otherwise, we can do it in MODE, the
7982 widest mode encountered. */
7984 = (code == ASHIFTRT || code == LSHIFTRT || code == ROTATE
7985 ? result_mode : mode);
7987 /* Handle cases where the count is greater than the size of the mode
7988 minus 1. For ASHIFT, use the size minus one as the count (this can
7989 occur when simplifying (lshiftrt (ashiftrt ..))). For rotates,
7990 take the count modulo the size. For other shifts, the result is
7993 Since these shifts are being produced by the compiler by combining
7994 multiple operations, each of which are defined, we know what the
7995 result is supposed to be. */
7997 if (count > GET_MODE_BITSIZE (shift_mode) - 1)
7999 if (code == ASHIFTRT)
8000 count = GET_MODE_BITSIZE (shift_mode) - 1;
8001 else if (code == ROTATE || code == ROTATERT)
8002 count %= GET_MODE_BITSIZE (shift_mode);
8005 /* We can't simply return zero because there may be an
8013 /* Negative counts are invalid and should not have been made (a
8014 programmer-specified negative count should have been handled
8019 /* An arithmetic right shift of a quantity known to be -1 or 0
8021 if (code == ASHIFTRT
8022 && (num_sign_bit_copies (varop, shift_mode)
8023 == GET_MODE_BITSIZE (shift_mode)))
8029 /* If we are doing an arithmetic right shift and discarding all but
8030 the sign bit copies, this is equivalent to doing a shift by the
8031 bitsize minus one. Convert it into that shift because it will often
8032 allow other simplifications. */
8034 if (code == ASHIFTRT
8035 && (count + num_sign_bit_copies (varop, shift_mode)
8036 >= GET_MODE_BITSIZE (shift_mode)))
8037 count = GET_MODE_BITSIZE (shift_mode) - 1;
8039 /* We simplify the tests below and elsewhere by converting
8040 ASHIFTRT to LSHIFTRT if we know the sign bit is clear.
8041 `make_compound_operation' will convert it to a ASHIFTRT for
8042 those machines (such as Vax) that don't have a LSHIFTRT. */
8043 if (GET_MODE_BITSIZE (shift_mode) <= HOST_BITS_PER_WIDE_INT
8045 && ((nonzero_bits (varop, shift_mode)
8046 & ((HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (shift_mode) - 1)))
8050 switch (GET_CODE (varop))
8056 new = expand_compound_operation (varop);
8065 /* If we have (xshiftrt (mem ...) C) and C is MODE_WIDTH
8066 minus the width of a smaller mode, we can do this with a
8067 SIGN_EXTEND or ZERO_EXTEND from the narrower memory location. */
8068 if ((code == ASHIFTRT || code == LSHIFTRT)
8069 && ! mode_dependent_address_p (XEXP (varop, 0))
8070 && ! MEM_VOLATILE_P (varop)
8071 && (tmode = mode_for_size (GET_MODE_BITSIZE (mode) - count,
8072 MODE_INT, 1)) != BLKmode)
8074 if (BYTES_BIG_ENDIAN)
8075 new = gen_rtx (MEM, tmode, XEXP (varop, 0));
8077 new = gen_rtx (MEM, tmode,
8078 plus_constant (XEXP (varop, 0),
8079 count / BITS_PER_UNIT));
8080 RTX_UNCHANGING_P (new) = RTX_UNCHANGING_P (varop);
8081 MEM_VOLATILE_P (new) = MEM_VOLATILE_P (varop);
8082 MEM_IN_STRUCT_P (new) = MEM_IN_STRUCT_P (varop);
8083 varop = gen_rtx_combine (code == ASHIFTRT ? SIGN_EXTEND
8084 : ZERO_EXTEND, mode, new);
8091 /* Similar to the case above, except that we can only do this if
8092 the resulting mode is the same as that of the underlying
8093 MEM and adjust the address depending on the *bits* endianness
8094 because of the way that bit-field extract insns are defined. */
8095 if ((code == ASHIFTRT || code == LSHIFTRT)
8096 && (tmode = mode_for_size (GET_MODE_BITSIZE (mode) - count,
8097 MODE_INT, 1)) != BLKmode
8098 && tmode == GET_MODE (XEXP (varop, 0)))
8100 if (BITS_BIG_ENDIAN)
8101 new = XEXP (varop, 0);
8104 new = copy_rtx (XEXP (varop, 0));
8105 SUBST (XEXP (new, 0),
8106 plus_constant (XEXP (new, 0),
8107 count / BITS_PER_UNIT));
8110 varop = gen_rtx_combine (code == ASHIFTRT ? SIGN_EXTEND
8111 : ZERO_EXTEND, mode, new);
8118 /* If VAROP is a SUBREG, strip it as long as the inner operand has
8119 the same number of words as what we've seen so far. Then store
8120 the widest mode in MODE. */
8121 if (subreg_lowpart_p (varop)
8122 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop)))
8123 > GET_MODE_SIZE (GET_MODE (varop)))
8124 && (((GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop)))
8125 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
8128 varop = SUBREG_REG (varop);
8129 if (GET_MODE_SIZE (GET_MODE (varop)) > GET_MODE_SIZE (mode))
8130 mode = GET_MODE (varop);
8136 /* Some machines use MULT instead of ASHIFT because MULT
8137 is cheaper. But it is still better on those machines to
8138 merge two shifts into one. */
8139 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
8140 && exact_log2 (INTVAL (XEXP (varop, 1))) >= 0)
8142 varop = gen_binary (ASHIFT, GET_MODE (varop), XEXP (varop, 0),
8143 GEN_INT (exact_log2 (INTVAL (XEXP (varop, 1)))));;
8149 /* Similar, for when divides are cheaper. */
8150 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
8151 && exact_log2 (INTVAL (XEXP (varop, 1))) >= 0)
8153 varop = gen_binary (LSHIFTRT, GET_MODE (varop), XEXP (varop, 0),
8154 GEN_INT (exact_log2 (INTVAL (XEXP (varop, 1)))));
8160 /* If we are extracting just the sign bit of an arithmetic right
8161 shift, that shift is not needed. */
8162 if (code == LSHIFTRT && count == GET_MODE_BITSIZE (result_mode) - 1)
8164 varop = XEXP (varop, 0);
8168 /* ... fall through ... */
8173 /* Here we have two nested shifts. The result is usually the
8174 AND of a new shift with a mask. We compute the result below. */
8175 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
8176 && INTVAL (XEXP (varop, 1)) >= 0
8177 && INTVAL (XEXP (varop, 1)) < GET_MODE_BITSIZE (GET_MODE (varop))
8178 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
8179 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
8181 enum rtx_code first_code = GET_CODE (varop);
8182 int first_count = INTVAL (XEXP (varop, 1));
8183 unsigned HOST_WIDE_INT mask;
8186 /* We have one common special case. We can't do any merging if
8187 the inner code is an ASHIFTRT of a smaller mode. However, if
8188 we have (ashift:M1 (subreg:M1 (ashiftrt:M2 FOO C1) 0) C2)
8189 with C2 == GET_MODE_BITSIZE (M1) - GET_MODE_BITSIZE (M2),
8190 we can convert it to
8191 (ashiftrt:M1 (ashift:M1 (and:M1 (subreg:M1 FOO 0 C2) C3) C1).
8192 This simplifies certain SIGN_EXTEND operations. */
8193 if (code == ASHIFT && first_code == ASHIFTRT
8194 && (GET_MODE_BITSIZE (result_mode)
8195 - GET_MODE_BITSIZE (GET_MODE (varop))) == count)
8197 /* C3 has the low-order C1 bits zero. */
8199 mask = (GET_MODE_MASK (mode)
8200 & ~ (((HOST_WIDE_INT) 1 << first_count) - 1));
8202 varop = simplify_and_const_int (NULL_RTX, result_mode,
8203 XEXP (varop, 0), mask);
8204 varop = simplify_shift_const (NULL_RTX, ASHIFT, result_mode,
8206 count = first_count;
8211 /* If this was (ashiftrt (ashift foo C1) C2) and FOO has more
8212 than C1 high-order bits equal to the sign bit, we can convert
8213 this to either an ASHIFT or a ASHIFTRT depending on the
8216 We cannot do this if VAROP's mode is not SHIFT_MODE. */
8218 if (code == ASHIFTRT && first_code == ASHIFT
8219 && GET_MODE (varop) == shift_mode
8220 && (num_sign_bit_copies (XEXP (varop, 0), shift_mode)
8223 count -= first_count;
8225 count = - count, code = ASHIFT;
8226 varop = XEXP (varop, 0);
8230 /* There are some cases we can't do. If CODE is ASHIFTRT,
8231 we can only do this if FIRST_CODE is also ASHIFTRT.
8233 We can't do the case when CODE is ROTATE and FIRST_CODE is
8236 If the mode of this shift is not the mode of the outer shift,
8237 we can't do this if either shift is a right shift or ROTATE.
8239 Finally, we can't do any of these if the mode is too wide
8240 unless the codes are the same.
8242 Handle the case where the shift codes are the same
8245 if (code == first_code)
8247 if (GET_MODE (varop) != result_mode
8248 && (code == ASHIFTRT || code == LSHIFTRT
8252 count += first_count;
8253 varop = XEXP (varop, 0);
8257 if (code == ASHIFTRT
8258 || (code == ROTATE && first_code == ASHIFTRT)
8259 || GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT
8260 || (GET_MODE (varop) != result_mode
8261 && (first_code == ASHIFTRT || first_code == LSHIFTRT
8262 || first_code == ROTATE
8263 || code == ROTATE)))
8266 /* To compute the mask to apply after the shift, shift the
8267 nonzero bits of the inner shift the same way the
8268 outer shift will. */
8270 mask_rtx = GEN_INT (nonzero_bits (varop, GET_MODE (varop)));
8273 = simplify_binary_operation (code, result_mode, mask_rtx,
8276 /* Give up if we can't compute an outer operation to use. */
8278 || GET_CODE (mask_rtx) != CONST_INT
8279 || ! merge_outer_ops (&outer_op, &outer_const, AND,
8281 result_mode, &complement_p))
8284 /* If the shifts are in the same direction, we add the
8285 counts. Otherwise, we subtract them. */
8286 if ((code == ASHIFTRT || code == LSHIFTRT)
8287 == (first_code == ASHIFTRT || first_code == LSHIFTRT))
8288 count += first_count;
8290 count -= first_count;
8292 /* If COUNT is positive, the new shift is usually CODE,
8293 except for the two exceptions below, in which case it is
8294 FIRST_CODE. If the count is negative, FIRST_CODE should
8297 && ((first_code == ROTATE && code == ASHIFT)
8298 || (first_code == ASHIFTRT && code == LSHIFTRT)))
8301 code = first_code, count = - count;
8303 varop = XEXP (varop, 0);
8307 /* If we have (A << B << C) for any shift, we can convert this to
8308 (A << C << B). This wins if A is a constant. Only try this if
8309 B is not a constant. */
8311 else if (GET_CODE (varop) == code
8312 && GET_CODE (XEXP (varop, 1)) != CONST_INT
8314 = simplify_binary_operation (code, mode,
8318 varop = gen_rtx_combine (code, mode, new, XEXP (varop, 1));
8325 /* Make this fit the case below. */
8326 varop = gen_rtx_combine (XOR, mode, XEXP (varop, 0),
8327 GEN_INT (GET_MODE_MASK (mode)));
8333 /* If we have (xshiftrt (ior (plus X (const_int -1)) X) C)
8334 with C the size of VAROP - 1 and the shift is logical if
8335 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
8336 we have an (le X 0) operation. If we have an arithmetic shift
8337 and STORE_FLAG_VALUE is 1 or we have a logical shift with
8338 STORE_FLAG_VALUE of -1, we have a (neg (le X 0)) operation. */
8340 if (GET_CODE (varop) == IOR && GET_CODE (XEXP (varop, 0)) == PLUS
8341 && XEXP (XEXP (varop, 0), 1) == constm1_rtx
8342 && (STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
8343 && (code == LSHIFTRT || code == ASHIFTRT)
8344 && count == GET_MODE_BITSIZE (GET_MODE (varop)) - 1
8345 && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
8348 varop = gen_rtx_combine (LE, GET_MODE (varop), XEXP (varop, 1),
8351 if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
8352 varop = gen_rtx_combine (NEG, GET_MODE (varop), varop);
8357 /* If we have (shift (logical)), move the logical to the outside
8358 to allow it to possibly combine with another logical and the
8359 shift to combine with another shift. This also canonicalizes to
8360 what a ZERO_EXTRACT looks like. Also, some machines have
8361 (and (shift)) insns. */
8363 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
8364 && (new = simplify_binary_operation (code, result_mode,
8366 GEN_INT (count))) != 0
8367 && GET_CODE(new) == CONST_INT
8368 && merge_outer_ops (&outer_op, &outer_const, GET_CODE (varop),
8369 INTVAL (new), result_mode, &complement_p))
8371 varop = XEXP (varop, 0);
8375 /* If we can't do that, try to simplify the shift in each arm of the
8376 logical expression, make a new logical expression, and apply
8377 the inverse distributive law. */
8379 rtx lhs = simplify_shift_const (NULL_RTX, code, shift_mode,
8380 XEXP (varop, 0), count);
8381 rtx rhs = simplify_shift_const (NULL_RTX, code, shift_mode,
8382 XEXP (varop, 1), count);
8384 varop = gen_binary (GET_CODE (varop), shift_mode, lhs, rhs);
8385 varop = apply_distributive_law (varop);
8392 /* convert (lshiftrt (eq FOO 0) C) to (xor FOO 1) if STORE_FLAG_VALUE
8393 says that the sign bit can be tested, FOO has mode MODE, C is
8394 GET_MODE_BITSIZE (MODE) - 1, and FOO has only its low-order bit
8395 that may be nonzero. */
8396 if (code == LSHIFTRT
8397 && XEXP (varop, 1) == const0_rtx
8398 && GET_MODE (XEXP (varop, 0)) == result_mode
8399 && count == GET_MODE_BITSIZE (result_mode) - 1
8400 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
8401 && ((STORE_FLAG_VALUE
8402 & ((HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (result_mode) - 1))))
8403 && nonzero_bits (XEXP (varop, 0), result_mode) == 1
8404 && merge_outer_ops (&outer_op, &outer_const, XOR,
8405 (HOST_WIDE_INT) 1, result_mode,
8408 varop = XEXP (varop, 0);
8415 /* (lshiftrt (neg A) C) where A is either 0 or 1 and C is one less
8416 than the number of bits in the mode is equivalent to A. */
8417 if (code == LSHIFTRT && count == GET_MODE_BITSIZE (result_mode) - 1
8418 && nonzero_bits (XEXP (varop, 0), result_mode) == 1)
8420 varop = XEXP (varop, 0);
8425 /* NEG commutes with ASHIFT since it is multiplication. Move the
8426 NEG outside to allow shifts to combine. */
8428 && merge_outer_ops (&outer_op, &outer_const, NEG,
8429 (HOST_WIDE_INT) 0, result_mode,
8432 varop = XEXP (varop, 0);
8438 /* (lshiftrt (plus A -1) C) where A is either 0 or 1 and C
8439 is one less than the number of bits in the mode is
8440 equivalent to (xor A 1). */
8441 if (code == LSHIFTRT && count == GET_MODE_BITSIZE (result_mode) - 1
8442 && XEXP (varop, 1) == constm1_rtx
8443 && nonzero_bits (XEXP (varop, 0), result_mode) == 1
8444 && merge_outer_ops (&outer_op, &outer_const, XOR,
8445 (HOST_WIDE_INT) 1, result_mode,
8449 varop = XEXP (varop, 0);
8453 /* If we have (xshiftrt (plus FOO BAR) C), and the only bits
8454 that might be nonzero in BAR are those being shifted out and those
8455 bits are known zero in FOO, we can replace the PLUS with FOO.
8456 Similarly in the other operand order. This code occurs when
8457 we are computing the size of a variable-size array. */
8459 if ((code == ASHIFTRT || code == LSHIFTRT)
8460 && count < HOST_BITS_PER_WIDE_INT
8461 && nonzero_bits (XEXP (varop, 1), result_mode) >> count == 0
8462 && (nonzero_bits (XEXP (varop, 1), result_mode)
8463 & nonzero_bits (XEXP (varop, 0), result_mode)) == 0)
8465 varop = XEXP (varop, 0);
8468 else if ((code == ASHIFTRT || code == LSHIFTRT)
8469 && count < HOST_BITS_PER_WIDE_INT
8470 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
8471 && 0 == (nonzero_bits (XEXP (varop, 0), result_mode)
8473 && 0 == (nonzero_bits (XEXP (varop, 0), result_mode)
8474 & nonzero_bits (XEXP (varop, 1),
8477 varop = XEXP (varop, 1);
8481 /* (ashift (plus foo C) N) is (plus (ashift foo N) C'). */
8483 && GET_CODE (XEXP (varop, 1)) == CONST_INT
8484 && (new = simplify_binary_operation (ASHIFT, result_mode,
8486 GEN_INT (count))) != 0
8487 && GET_CODE(new) == CONST_INT
8488 && merge_outer_ops (&outer_op, &outer_const, PLUS,
8489 INTVAL (new), result_mode, &complement_p))
8491 varop = XEXP (varop, 0);
8497 /* If we have (xshiftrt (minus (ashiftrt X C)) X) C)
8498 with C the size of VAROP - 1 and the shift is logical if
8499 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
8500 we have a (gt X 0) operation. If the shift is arithmetic with
8501 STORE_FLAG_VALUE of 1 or logical with STORE_FLAG_VALUE == -1,
8502 we have a (neg (gt X 0)) operation. */
8504 if (GET_CODE (XEXP (varop, 0)) == ASHIFTRT
8505 && count == GET_MODE_BITSIZE (GET_MODE (varop)) - 1
8506 && (STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
8507 && (code == LSHIFTRT || code == ASHIFTRT)
8508 && GET_CODE (XEXP (XEXP (varop, 0), 1)) == CONST_INT
8509 && INTVAL (XEXP (XEXP (varop, 0), 1)) == count
8510 && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
8513 varop = gen_rtx_combine (GT, GET_MODE (varop), XEXP (varop, 1),
8516 if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
8517 varop = gen_rtx_combine (NEG, GET_MODE (varop), varop);
8527 /* We need to determine what mode to do the shift in. If the shift is
8528 a right shift or ROTATE, we must always do it in the mode it was
8529 originally done in. Otherwise, we can do it in MODE, the widest mode
8530 encountered. The code we care about is that of the shift that will
8531 actually be done, not the shift that was originally requested. */
8533 = (code == ASHIFTRT || code == LSHIFTRT || code == ROTATE
8534 ? result_mode : mode);
8536 /* We have now finished analyzing the shift. The result should be
8537 a shift of type CODE with SHIFT_MODE shifting VAROP COUNT places. If
8538 OUTER_OP is non-NIL, it is an operation that needs to be applied
8539 to the result of the shift. OUTER_CONST is the relevant constant,
8540 but we must turn off all bits turned off in the shift.
8542 If we were passed a value for X, see if we can use any pieces of
8543 it. If not, make new rtx. */
8545 if (x && GET_RTX_CLASS (GET_CODE (x)) == '2'
8546 && GET_CODE (XEXP (x, 1)) == CONST_INT
8547 && INTVAL (XEXP (x, 1)) == count)
8548 const_rtx = XEXP (x, 1);
8550 const_rtx = GEN_INT (count);
8552 if (x && GET_CODE (XEXP (x, 0)) == SUBREG
8553 && GET_MODE (XEXP (x, 0)) == shift_mode
8554 && SUBREG_REG (XEXP (x, 0)) == varop)
8555 varop = XEXP (x, 0);
8556 else if (GET_MODE (varop) != shift_mode)
8557 varop = gen_lowpart_for_combine (shift_mode, varop);
8559 /* If we can't make the SUBREG, try to return what we were given. */
8560 if (GET_CODE (varop) == CLOBBER)
8561 return x ? x : varop;
8563 new = simplify_binary_operation (code, shift_mode, varop, const_rtx);
8568 if (x == 0 || GET_CODE (x) != code || GET_MODE (x) != shift_mode)
8569 x = gen_rtx_combine (code, shift_mode, varop, const_rtx);
8571 SUBST (XEXP (x, 0), varop);
8572 SUBST (XEXP (x, 1), const_rtx);
8575 /* If we have an outer operation and we just made a shift, it is
8576 possible that we could have simplified the shift were it not
8577 for the outer operation. So try to do the simplification
8580 if (outer_op != NIL && GET_CODE (x) == code
8581 && GET_CODE (XEXP (x, 1)) == CONST_INT)
8582 x = simplify_shift_const (x, code, shift_mode, XEXP (x, 0),
8583 INTVAL (XEXP (x, 1)));
8585 /* If we were doing a LSHIFTRT in a wider mode than it was originally,
8586 turn off all the bits that the shift would have turned off. */
8587 if (orig_code == LSHIFTRT && result_mode != shift_mode)
8588 x = simplify_and_const_int (NULL_RTX, shift_mode, x,
8589 GET_MODE_MASK (result_mode) >> orig_count);
8591 /* Do the remainder of the processing in RESULT_MODE. */
8592 x = gen_lowpart_for_combine (result_mode, x);
8594 /* If COMPLEMENT_P is set, we have to complement X before doing the outer
8597 x = gen_unary (NOT, result_mode, result_mode, x);
8599 if (outer_op != NIL)
8601 if (GET_MODE_BITSIZE (result_mode) < HOST_BITS_PER_WIDE_INT)
8603 int width = GET_MODE_BITSIZE (result_mode);
8605 outer_const &= GET_MODE_MASK (result_mode);
8607 /* If this would be an entire word for the target, but is not for
8608 the host, then sign-extend on the host so that the number will
8609 look the same way on the host that it would on the target.
8611 For example, when building a 64 bit alpha hosted 32 bit sparc
8612 targeted compiler, then we want the 32 bit unsigned value -1 to be
8613 represented as a 64 bit value -1, and not as 0x00000000ffffffff.
8614 The later confuses the sparc backend. */
8616 if (BITS_PER_WORD < HOST_BITS_PER_WIDE_INT && BITS_PER_WORD == width
8617 && (outer_const & ((HOST_WIDE_INT) 1 << (width - 1))))
8618 outer_const |= ((HOST_WIDE_INT) (-1) << width);
8621 if (outer_op == AND)
8622 x = simplify_and_const_int (NULL_RTX, result_mode, x, outer_const);
8623 else if (outer_op == SET)
8624 /* This means that we have determined that the result is
8625 equivalent to a constant. This should be rare. */
8626 x = GEN_INT (outer_const);
8627 else if (GET_RTX_CLASS (outer_op) == '1')
8628 x = gen_unary (outer_op, result_mode, result_mode, x);
8630 x = gen_binary (outer_op, result_mode, x, GEN_INT (outer_const));
8636 /* Like recog, but we receive the address of a pointer to a new pattern.
8637 We try to match the rtx that the pointer points to.
8638 If that fails, we may try to modify or replace the pattern,
8639 storing the replacement into the same pointer object.
8641 Modifications include deletion or addition of CLOBBERs.
8643 PNOTES is a pointer to a location where any REG_UNUSED notes added for
8644 the CLOBBERs are placed.
8646 PADDED_SCRATCHES is set to the number of (clobber (scratch)) patterns
8649 The value is the final insn code from the pattern ultimately matched,
8653 recog_for_combine (pnewpat, insn, pnotes, padded_scratches)
8657 int *padded_scratches;
8659 register rtx pat = *pnewpat;
8660 int insn_code_number;
8661 int num_clobbers_to_add = 0;
8665 *padded_scratches = 0;
8667 /* If PAT is a PARALLEL, check to see if it contains the CLOBBER
8668 we use to indicate that something didn't match. If we find such a
8669 thing, force rejection. */
8670 if (GET_CODE (pat) == PARALLEL)
8671 for (i = XVECLEN (pat, 0) - 1; i >= 0; i--)
8672 if (GET_CODE (XVECEXP (pat, 0, i)) == CLOBBER
8673 && XEXP (XVECEXP (pat, 0, i), 0) == const0_rtx)
8676 /* Is the result of combination a valid instruction? */
8677 insn_code_number = recog (pat, insn, &num_clobbers_to_add);
8679 /* If it isn't, there is the possibility that we previously had an insn
8680 that clobbered some register as a side effect, but the combined
8681 insn doesn't need to do that. So try once more without the clobbers
8682 unless this represents an ASM insn. */
8684 if (insn_code_number < 0 && ! check_asm_operands (pat)
8685 && GET_CODE (pat) == PARALLEL)
8689 for (pos = 0, i = 0; i < XVECLEN (pat, 0); i++)
8690 if (GET_CODE (XVECEXP (pat, 0, i)) != CLOBBER)
8693 SUBST (XVECEXP (pat, 0, pos), XVECEXP (pat, 0, i));
8697 SUBST_INT (XVECLEN (pat, 0), pos);
8700 pat = XVECEXP (pat, 0, 0);
8702 insn_code_number = recog (pat, insn, &num_clobbers_to_add);
8705 /* If we had any clobbers to add, make a new pattern than contains
8706 them. Then check to make sure that all of them are dead. */
8707 if (num_clobbers_to_add)
8709 rtx newpat = gen_rtx (PARALLEL, VOIDmode,
8710 gen_rtvec (GET_CODE (pat) == PARALLEL
8711 ? XVECLEN (pat, 0) + num_clobbers_to_add
8712 : num_clobbers_to_add + 1));
8714 if (GET_CODE (pat) == PARALLEL)
8715 for (i = 0; i < XVECLEN (pat, 0); i++)
8716 XVECEXP (newpat, 0, i) = XVECEXP (pat, 0, i);
8718 XVECEXP (newpat, 0, 0) = pat;
8720 add_clobbers (newpat, insn_code_number);
8722 for (i = XVECLEN (newpat, 0) - num_clobbers_to_add;
8723 i < XVECLEN (newpat, 0); i++)
8725 if (GET_CODE (XEXP (XVECEXP (newpat, 0, i), 0)) == REG
8726 && ! reg_dead_at_p (XEXP (XVECEXP (newpat, 0, i), 0), insn))
8728 else if (GET_CODE (XEXP (XVECEXP (newpat, 0, i), 0)) == SCRATCH)
8729 (*padded_scratches)++;
8730 notes = gen_rtx (EXPR_LIST, REG_UNUSED,
8731 XEXP (XVECEXP (newpat, 0, i), 0), notes);
8739 return insn_code_number;
8742 /* Like gen_lowpart but for use by combine. In combine it is not possible
8743 to create any new pseudoregs. However, it is safe to create
8744 invalid memory addresses, because combine will try to recognize
8745 them and all they will do is make the combine attempt fail.
8747 If for some reason this cannot do its job, an rtx
8748 (clobber (const_int 0)) is returned.
8749 An insn containing that will not be recognized. */
8754 gen_lowpart_for_combine (mode, x)
8755 enum machine_mode mode;
8760 if (GET_MODE (x) == mode)
8763 /* We can only support MODE being wider than a word if X is a
8764 constant integer or has a mode the same size. */
8766 if (GET_MODE_SIZE (mode) > UNITS_PER_WORD
8767 && ! ((GET_MODE (x) == VOIDmode
8768 && (GET_CODE (x) == CONST_INT
8769 || GET_CODE (x) == CONST_DOUBLE))
8770 || GET_MODE_SIZE (GET_MODE (x)) == GET_MODE_SIZE (mode)))
8771 return gen_rtx (CLOBBER, GET_MODE (x), const0_rtx);
8773 /* X might be a paradoxical (subreg (mem)). In that case, gen_lowpart
8774 won't know what to do. So we will strip off the SUBREG here and
8775 process normally. */
8776 if (GET_CODE (x) == SUBREG && GET_CODE (SUBREG_REG (x)) == MEM)
8779 if (GET_MODE (x) == mode)
8783 result = gen_lowpart_common (mode, x);
8785 && GET_CODE (result) == SUBREG
8786 && GET_CODE (SUBREG_REG (result)) == REG
8787 && REGNO (SUBREG_REG (result)) >= FIRST_PSEUDO_REGISTER
8788 && (GET_MODE_SIZE (GET_MODE (result))
8789 != GET_MODE_SIZE (GET_MODE (SUBREG_REG (result)))))
8790 reg_changes_size[REGNO (SUBREG_REG (result))] = 1;
8795 if (GET_CODE (x) == MEM)
8797 register int offset = 0;
8800 /* Refuse to work on a volatile memory ref or one with a mode-dependent
8802 if (MEM_VOLATILE_P (x) || mode_dependent_address_p (XEXP (x, 0)))
8803 return gen_rtx (CLOBBER, GET_MODE (x), const0_rtx);
8805 /* If we want to refer to something bigger than the original memref,
8806 generate a perverse subreg instead. That will force a reload
8807 of the original memref X. */
8808 if (GET_MODE_SIZE (GET_MODE (x)) < GET_MODE_SIZE (mode))
8809 return gen_rtx (SUBREG, mode, x, 0);
8811 if (WORDS_BIG_ENDIAN)
8812 offset = (MAX (GET_MODE_SIZE (GET_MODE (x)), UNITS_PER_WORD)
8813 - MAX (GET_MODE_SIZE (mode), UNITS_PER_WORD));
8814 if (BYTES_BIG_ENDIAN)
8816 /* Adjust the address so that the address-after-the-data is
8818 offset -= (MIN (UNITS_PER_WORD, GET_MODE_SIZE (mode))
8819 - MIN (UNITS_PER_WORD, GET_MODE_SIZE (GET_MODE (x))));
8821 new = gen_rtx (MEM, mode, plus_constant (XEXP (x, 0), offset));
8822 RTX_UNCHANGING_P (new) = RTX_UNCHANGING_P (x);
8823 MEM_VOLATILE_P (new) = MEM_VOLATILE_P (x);
8824 MEM_IN_STRUCT_P (new) = MEM_IN_STRUCT_P (x);
8828 /* If X is a comparison operator, rewrite it in a new mode. This
8829 probably won't match, but may allow further simplifications. */
8830 else if (GET_RTX_CLASS (GET_CODE (x)) == '<')
8831 return gen_rtx_combine (GET_CODE (x), mode, XEXP (x, 0), XEXP (x, 1));
8833 /* If we couldn't simplify X any other way, just enclose it in a
8834 SUBREG. Normally, this SUBREG won't match, but some patterns may
8835 include an explicit SUBREG or we may simplify it further in combine. */
8840 if (WORDS_BIG_ENDIAN && GET_MODE_SIZE (GET_MODE (x)) > UNITS_PER_WORD)
8841 word = ((GET_MODE_SIZE (GET_MODE (x))
8842 - MAX (GET_MODE_SIZE (mode), UNITS_PER_WORD))
8844 return gen_rtx (SUBREG, mode, x, word);
8848 /* Make an rtx expression. This is a subset of gen_rtx and only supports
8849 expressions of 1, 2, or 3 operands, each of which are rtx expressions.
8851 If the identical expression was previously in the insn (in the undobuf),
8852 it will be returned. Only if it is not found will a new expression
8857 gen_rtx_combine VPROTO((enum rtx_code code, enum machine_mode mode, ...))
8861 enum machine_mode mode;
8874 code = va_arg (p, enum rtx_code);
8875 mode = va_arg (p, enum machine_mode);
8878 n_args = GET_RTX_LENGTH (code);
8879 fmt = GET_RTX_FORMAT (code);
8881 if (n_args == 0 || n_args > 3)
8884 /* Get each arg and verify that it is supposed to be an expression. */
8885 for (j = 0; j < n_args; j++)
8890 args[j] = va_arg (p, rtx);
8893 /* See if this is in undobuf. Be sure we don't use objects that came
8894 from another insn; this could produce circular rtl structures. */
8896 for (undo = undobuf.undos; undo != undobuf.previous_undos; undo = undo->next)
8898 && GET_CODE (undo->old_contents.r) == code
8899 && GET_MODE (undo->old_contents.r) == mode)
8901 for (j = 0; j < n_args; j++)
8902 if (XEXP (undo->old_contents.r, j) != args[j])
8906 return undo->old_contents.r;
8909 /* Otherwise make a new rtx. We know we have 1, 2, or 3 args.
8910 Use rtx_alloc instead of gen_rtx because it's faster on RISC. */
8911 rt = rtx_alloc (code);
8912 PUT_MODE (rt, mode);
8913 XEXP (rt, 0) = args[0];
8916 XEXP (rt, 1) = args[1];
8918 XEXP (rt, 2) = args[2];
8923 /* These routines make binary and unary operations by first seeing if they
8924 fold; if not, a new expression is allocated. */
8927 gen_binary (code, mode, op0, op1)
8929 enum machine_mode mode;
8935 if (GET_RTX_CLASS (code) == 'c'
8936 && (GET_CODE (op0) == CONST_INT
8937 || (CONSTANT_P (op0) && GET_CODE (op1) != CONST_INT)))
8938 tem = op0, op0 = op1, op1 = tem;
8940 if (GET_RTX_CLASS (code) == '<')
8942 enum machine_mode op_mode = GET_MODE (op0);
8944 /* Strip the COMPARE from (REL_OP (compare X Y) 0) to get
8945 just (REL_OP X Y). */
8946 if (GET_CODE (op0) == COMPARE && op1 == const0_rtx)
8948 op1 = XEXP (op0, 1);
8949 op0 = XEXP (op0, 0);
8950 op_mode = GET_MODE (op0);
8953 if (op_mode == VOIDmode)
8954 op_mode = GET_MODE (op1);
8955 result = simplify_relational_operation (code, op_mode, op0, op1);
8958 result = simplify_binary_operation (code, mode, op0, op1);
8963 /* Put complex operands first and constants second. */
8964 if (GET_RTX_CLASS (code) == 'c'
8965 && ((CONSTANT_P (op0) && GET_CODE (op1) != CONST_INT)
8966 || (GET_RTX_CLASS (GET_CODE (op0)) == 'o'
8967 && GET_RTX_CLASS (GET_CODE (op1)) != 'o')
8968 || (GET_CODE (op0) == SUBREG
8969 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (op0))) == 'o'
8970 && GET_RTX_CLASS (GET_CODE (op1)) != 'o')))
8971 return gen_rtx_combine (code, mode, op1, op0);
8973 return gen_rtx_combine (code, mode, op0, op1);
8977 gen_unary (code, mode, op0_mode, op0)
8979 enum machine_mode mode, op0_mode;
8982 rtx result = simplify_unary_operation (code, mode, op0, op0_mode);
8987 return gen_rtx_combine (code, mode, op0);
8990 /* Simplify a comparison between *POP0 and *POP1 where CODE is the
8991 comparison code that will be tested.
8993 The result is a possibly different comparison code to use. *POP0 and
8994 *POP1 may be updated.
8996 It is possible that we might detect that a comparison is either always
8997 true or always false. However, we do not perform general constant
8998 folding in combine, so this knowledge isn't useful. Such tautologies
8999 should have been detected earlier. Hence we ignore all such cases. */
9001 static enum rtx_code
9002 simplify_comparison (code, pop0, pop1)
9011 enum machine_mode mode, tmode;
9013 /* Try a few ways of applying the same transformation to both operands. */
9016 #ifndef WORD_REGISTER_OPERATIONS
9017 /* The test below this one won't handle SIGN_EXTENDs on these machines,
9018 so check specially. */
9019 if (code != GTU && code != GEU && code != LTU && code != LEU
9020 && GET_CODE (op0) == ASHIFTRT && GET_CODE (op1) == ASHIFTRT
9021 && GET_CODE (XEXP (op0, 0)) == ASHIFT
9022 && GET_CODE (XEXP (op1, 0)) == ASHIFT
9023 && GET_CODE (XEXP (XEXP (op0, 0), 0)) == SUBREG
9024 && GET_CODE (XEXP (XEXP (op1, 0), 0)) == SUBREG
9025 && (GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0)))
9026 == GET_MODE (SUBREG_REG (XEXP (XEXP (op1, 0), 0))))
9027 && GET_CODE (XEXP (op0, 1)) == CONST_INT
9028 && GET_CODE (XEXP (op1, 1)) == CONST_INT
9029 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
9030 && GET_CODE (XEXP (XEXP (op1, 0), 1)) == CONST_INT
9031 && INTVAL (XEXP (op0, 1)) == INTVAL (XEXP (op1, 1))
9032 && INTVAL (XEXP (op0, 1)) == INTVAL (XEXP (XEXP (op0, 0), 1))
9033 && INTVAL (XEXP (op0, 1)) == INTVAL (XEXP (XEXP (op1, 0), 1))
9034 && (INTVAL (XEXP (op0, 1))
9035 == (GET_MODE_BITSIZE (GET_MODE (op0))
9037 (GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0))))))))
9039 op0 = SUBREG_REG (XEXP (XEXP (op0, 0), 0));
9040 op1 = SUBREG_REG (XEXP (XEXP (op1, 0), 0));
9044 /* If both operands are the same constant shift, see if we can ignore the
9045 shift. We can if the shift is a rotate or if the bits shifted out of
9046 this shift are known to be zero for both inputs and if the type of
9047 comparison is compatible with the shift. */
9048 if (GET_CODE (op0) == GET_CODE (op1)
9049 && GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
9050 && ((GET_CODE (op0) == ROTATE && (code == NE || code == EQ))
9051 || ((GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFT)
9052 && (code != GT && code != LT && code != GE && code != LE))
9053 || (GET_CODE (op0) == ASHIFTRT
9054 && (code != GTU && code != LTU
9055 && code != GEU && code != GEU)))
9056 && GET_CODE (XEXP (op0, 1)) == CONST_INT
9057 && INTVAL (XEXP (op0, 1)) >= 0
9058 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT
9059 && XEXP (op0, 1) == XEXP (op1, 1))
9061 enum machine_mode mode = GET_MODE (op0);
9062 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
9063 int shift_count = INTVAL (XEXP (op0, 1));
9065 if (GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFTRT)
9066 mask &= (mask >> shift_count) << shift_count;
9067 else if (GET_CODE (op0) == ASHIFT)
9068 mask = (mask & (mask << shift_count)) >> shift_count;
9070 if ((nonzero_bits (XEXP (op0, 0), mode) & ~ mask) == 0
9071 && (nonzero_bits (XEXP (op1, 0), mode) & ~ mask) == 0)
9072 op0 = XEXP (op0, 0), op1 = XEXP (op1, 0);
9077 /* If both operands are AND's of a paradoxical SUBREG by constant, the
9078 SUBREGs are of the same mode, and, in both cases, the AND would
9079 be redundant if the comparison was done in the narrower mode,
9080 do the comparison in the narrower mode (e.g., we are AND'ing with 1
9081 and the operand's possibly nonzero bits are 0xffffff01; in that case
9082 if we only care about QImode, we don't need the AND). This case
9083 occurs if the output mode of an scc insn is not SImode and
9084 STORE_FLAG_VALUE == 1 (e.g., the 386).
9086 Similarly, check for a case where the AND's are ZERO_EXTEND
9087 operations from some narrower mode even though a SUBREG is not
9090 else if (GET_CODE (op0) == AND && GET_CODE (op1) == AND
9091 && GET_CODE (XEXP (op0, 1)) == CONST_INT
9092 && GET_CODE (XEXP (op1, 1)) == CONST_INT)
9094 rtx inner_op0 = XEXP (op0, 0);
9095 rtx inner_op1 = XEXP (op1, 0);
9096 HOST_WIDE_INT c0 = INTVAL (XEXP (op0, 1));
9097 HOST_WIDE_INT c1 = INTVAL (XEXP (op1, 1));
9100 if (GET_CODE (inner_op0) == SUBREG && GET_CODE (inner_op1) == SUBREG
9101 && (GET_MODE_SIZE (GET_MODE (inner_op0))
9102 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (inner_op0))))
9103 && (GET_MODE (SUBREG_REG (inner_op0))
9104 == GET_MODE (SUBREG_REG (inner_op1)))
9105 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0)))
9106 <= HOST_BITS_PER_WIDE_INT)
9107 && (0 == ((~c0) & nonzero_bits (SUBREG_REG (inner_op0),
9108 GET_MODE (SUBREG_REG (op0)))))
9109 && (0 == ((~c1) & nonzero_bits (SUBREG_REG (inner_op1),
9110 GET_MODE (SUBREG_REG (inner_op1))))))
9112 op0 = SUBREG_REG (inner_op0);
9113 op1 = SUBREG_REG (inner_op1);
9115 /* The resulting comparison is always unsigned since we masked
9116 off the original sign bit. */
9117 code = unsigned_condition (code);
9123 for (tmode = GET_CLASS_NARROWEST_MODE
9124 (GET_MODE_CLASS (GET_MODE (op0)));
9125 tmode != GET_MODE (op0); tmode = GET_MODE_WIDER_MODE (tmode))
9126 if (c0 == GET_MODE_MASK (tmode))
9128 op0 = gen_lowpart_for_combine (tmode, inner_op0);
9129 op1 = gen_lowpart_for_combine (tmode, inner_op1);
9130 code = unsigned_condition (code);
9139 /* If both operands are NOT, we can strip off the outer operation
9140 and adjust the comparison code for swapped operands; similarly for
9141 NEG, except that this must be an equality comparison. */
9142 else if ((GET_CODE (op0) == NOT && GET_CODE (op1) == NOT)
9143 || (GET_CODE (op0) == NEG && GET_CODE (op1) == NEG
9144 && (code == EQ || code == NE)))
9145 op0 = XEXP (op0, 0), op1 = XEXP (op1, 0), code = swap_condition (code);
9151 /* If the first operand is a constant, swap the operands and adjust the
9152 comparison code appropriately, but don't do this if the second operand
9153 is already a constant integer. */
9154 if (CONSTANT_P (op0) && GET_CODE (op1) != CONST_INT)
9156 tem = op0, op0 = op1, op1 = tem;
9157 code = swap_condition (code);
9160 /* We now enter a loop during which we will try to simplify the comparison.
9161 For the most part, we only are concerned with comparisons with zero,
9162 but some things may really be comparisons with zero but not start
9163 out looking that way. */
9165 while (GET_CODE (op1) == CONST_INT)
9167 enum machine_mode mode = GET_MODE (op0);
9168 int mode_width = GET_MODE_BITSIZE (mode);
9169 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
9170 int equality_comparison_p;
9171 int sign_bit_comparison_p;
9172 int unsigned_comparison_p;
9173 HOST_WIDE_INT const_op;
9175 /* We only want to handle integral modes. This catches VOIDmode,
9176 CCmode, and the floating-point modes. An exception is that we
9177 can handle VOIDmode if OP0 is a COMPARE or a comparison
9180 if (GET_MODE_CLASS (mode) != MODE_INT
9181 && ! (mode == VOIDmode
9182 && (GET_CODE (op0) == COMPARE
9183 || GET_RTX_CLASS (GET_CODE (op0)) == '<')))
9186 /* Get the constant we are comparing against and turn off all bits
9187 not on in our mode. */
9188 const_op = INTVAL (op1);
9189 if (mode_width <= HOST_BITS_PER_WIDE_INT)
9192 /* If we are comparing against a constant power of two and the value
9193 being compared can only have that single bit nonzero (e.g., it was
9194 `and'ed with that bit), we can replace this with a comparison
9197 && (code == EQ || code == NE || code == GE || code == GEU
9198 || code == LT || code == LTU)
9199 && mode_width <= HOST_BITS_PER_WIDE_INT
9200 && exact_log2 (const_op) >= 0
9201 && nonzero_bits (op0, mode) == const_op)
9203 code = (code == EQ || code == GE || code == GEU ? NE : EQ);
9204 op1 = const0_rtx, const_op = 0;
9207 /* Similarly, if we are comparing a value known to be either -1 or
9208 0 with -1, change it to the opposite comparison against zero. */
9211 && (code == EQ || code == NE || code == GT || code == LE
9212 || code == GEU || code == LTU)
9213 && num_sign_bit_copies (op0, mode) == mode_width)
9215 code = (code == EQ || code == LE || code == GEU ? NE : EQ);
9216 op1 = const0_rtx, const_op = 0;
9219 /* Do some canonicalizations based on the comparison code. We prefer
9220 comparisons against zero and then prefer equality comparisons.
9221 If we can reduce the size of a constant, we will do that too. */
9226 /* < C is equivalent to <= (C - 1) */
9230 op1 = GEN_INT (const_op);
9232 /* ... fall through to LE case below. */
9238 /* <= C is equivalent to < (C + 1); we do this for C < 0 */
9242 op1 = GEN_INT (const_op);
9246 /* If we are doing a <= 0 comparison on a value known to have
9247 a zero sign bit, we can replace this with == 0. */
9248 else if (const_op == 0
9249 && mode_width <= HOST_BITS_PER_WIDE_INT
9250 && (nonzero_bits (op0, mode)
9251 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)
9256 /* >= C is equivalent to > (C - 1). */
9260 op1 = GEN_INT (const_op);
9262 /* ... fall through to GT below. */
9268 /* > C is equivalent to >= (C + 1); we do this for C < 0*/
9272 op1 = GEN_INT (const_op);
9276 /* If we are doing a > 0 comparison on a value known to have
9277 a zero sign bit, we can replace this with != 0. */
9278 else if (const_op == 0
9279 && mode_width <= HOST_BITS_PER_WIDE_INT
9280 && (nonzero_bits (op0, mode)
9281 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)
9286 /* < C is equivalent to <= (C - 1). */
9290 op1 = GEN_INT (const_op);
9292 /* ... fall through ... */
9295 /* (unsigned) < 0x80000000 is equivalent to >= 0. */
9296 else if (const_op == (HOST_WIDE_INT) 1 << (mode_width - 1))
9298 const_op = 0, op1 = const0_rtx;
9306 /* unsigned <= 0 is equivalent to == 0 */
9310 /* (unsigned) <= 0x7fffffff is equivalent to >= 0. */
9311 else if (const_op == ((HOST_WIDE_INT) 1 << (mode_width - 1)) - 1)
9313 const_op = 0, op1 = const0_rtx;
9319 /* >= C is equivalent to < (C - 1). */
9323 op1 = GEN_INT (const_op);
9325 /* ... fall through ... */
9328 /* (unsigned) >= 0x80000000 is equivalent to < 0. */
9329 else if (const_op == (HOST_WIDE_INT) 1 << (mode_width - 1))
9331 const_op = 0, op1 = const0_rtx;
9339 /* unsigned > 0 is equivalent to != 0 */
9343 /* (unsigned) > 0x7fffffff is equivalent to < 0. */
9344 else if (const_op == ((HOST_WIDE_INT) 1 << (mode_width - 1)) - 1)
9346 const_op = 0, op1 = const0_rtx;
9352 /* Compute some predicates to simplify code below. */
9354 equality_comparison_p = (code == EQ || code == NE);
9355 sign_bit_comparison_p = ((code == LT || code == GE) && const_op == 0);
9356 unsigned_comparison_p = (code == LTU || code == LEU || code == GTU
9359 /* If this is a sign bit comparison and we can do arithmetic in
9360 MODE, say that we will only be needing the sign bit of OP0. */
9361 if (sign_bit_comparison_p
9362 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
9363 op0 = force_to_mode (op0, mode,
9365 << (GET_MODE_BITSIZE (mode) - 1)),
9368 /* Now try cases based on the opcode of OP0. If none of the cases
9369 does a "continue", we exit this loop immediately after the
9372 switch (GET_CODE (op0))
9375 /* If we are extracting a single bit from a variable position in
9376 a constant that has only a single bit set and are comparing it
9377 with zero, we can convert this into an equality comparison
9378 between the position and the location of the single bit. */
9380 if (GET_CODE (XEXP (op0, 0)) == CONST_INT
9381 && XEXP (op0, 1) == const1_rtx
9382 && equality_comparison_p && const_op == 0
9383 && (i = exact_log2 (INTVAL (XEXP (op0, 0)))) >= 0)
9385 if (BITS_BIG_ENDIAN)
9387 i = (GET_MODE_BITSIZE
9388 (insn_operand_mode[(int) CODE_FOR_extzv][1]) - 1 - i);
9390 i = BITS_PER_WORD - 1 - i;
9393 op0 = XEXP (op0, 2);
9397 /* Result is nonzero iff shift count is equal to I. */
9398 code = reverse_condition (code);
9402 /* ... fall through ... */
9405 tem = expand_compound_operation (op0);
9414 /* If testing for equality, we can take the NOT of the constant. */
9415 if (equality_comparison_p
9416 && (tem = simplify_unary_operation (NOT, mode, op1, mode)) != 0)
9418 op0 = XEXP (op0, 0);
9423 /* If just looking at the sign bit, reverse the sense of the
9425 if (sign_bit_comparison_p)
9427 op0 = XEXP (op0, 0);
9428 code = (code == GE ? LT : GE);
9434 /* If testing for equality, we can take the NEG of the constant. */
9435 if (equality_comparison_p
9436 && (tem = simplify_unary_operation (NEG, mode, op1, mode)) != 0)
9438 op0 = XEXP (op0, 0);
9443 /* The remaining cases only apply to comparisons with zero. */
9447 /* When X is ABS or is known positive,
9448 (neg X) is < 0 if and only if X != 0. */
9450 if (sign_bit_comparison_p
9451 && (GET_CODE (XEXP (op0, 0)) == ABS
9452 || (mode_width <= HOST_BITS_PER_WIDE_INT
9453 && (nonzero_bits (XEXP (op0, 0), mode)
9454 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)))
9456 op0 = XEXP (op0, 0);
9457 code = (code == LT ? NE : EQ);
9461 /* If we have NEG of something whose two high-order bits are the
9462 same, we know that "(-a) < 0" is equivalent to "a > 0". */
9463 if (num_sign_bit_copies (op0, mode) >= 2)
9465 op0 = XEXP (op0, 0);
9466 code = swap_condition (code);
9472 /* If we are testing equality and our count is a constant, we
9473 can perform the inverse operation on our RHS. */
9474 if (equality_comparison_p && GET_CODE (XEXP (op0, 1)) == CONST_INT
9475 && (tem = simplify_binary_operation (ROTATERT, mode,
9476 op1, XEXP (op0, 1))) != 0)
9478 op0 = XEXP (op0, 0);
9483 /* If we are doing a < 0 or >= 0 comparison, it means we are testing
9484 a particular bit. Convert it to an AND of a constant of that
9485 bit. This will be converted into a ZERO_EXTRACT. */
9486 if (const_op == 0 && sign_bit_comparison_p
9487 && GET_CODE (XEXP (op0, 1)) == CONST_INT
9488 && mode_width <= HOST_BITS_PER_WIDE_INT)
9490 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
9493 - INTVAL (XEXP (op0, 1)))));
9494 code = (code == LT ? NE : EQ);
9498 /* ... fall through ... */
9501 /* ABS is ignorable inside an equality comparison with zero. */
9502 if (const_op == 0 && equality_comparison_p)
9504 op0 = XEXP (op0, 0);
9511 /* Can simplify (compare (zero/sign_extend FOO) CONST)
9512 to (compare FOO CONST) if CONST fits in FOO's mode and we
9513 are either testing inequality or have an unsigned comparison
9514 with ZERO_EXTEND or a signed comparison with SIGN_EXTEND. */
9515 if (! unsigned_comparison_p
9516 && (GET_MODE_BITSIZE (GET_MODE (XEXP (op0, 0)))
9517 <= HOST_BITS_PER_WIDE_INT)
9518 && ((unsigned HOST_WIDE_INT) const_op
9519 < (((HOST_WIDE_INT) 1
9520 << (GET_MODE_BITSIZE (GET_MODE (XEXP (op0, 0))) - 1)))))
9522 op0 = XEXP (op0, 0);
9528 /* Check for the case where we are comparing A - C1 with C2,
9529 both constants are smaller than 1/2 the maximum positive
9530 value in MODE, and the comparison is equality or unsigned.
9531 In that case, if A is either zero-extended to MODE or has
9532 sufficient sign bits so that the high-order bit in MODE
9533 is a copy of the sign in the inner mode, we can prove that it is
9534 safe to do the operation in the wider mode. This simplifies
9535 many range checks. */
9537 if (mode_width <= HOST_BITS_PER_WIDE_INT
9538 && subreg_lowpart_p (op0)
9539 && GET_CODE (SUBREG_REG (op0)) == PLUS
9540 && GET_CODE (XEXP (SUBREG_REG (op0), 1)) == CONST_INT
9541 && INTVAL (XEXP (SUBREG_REG (op0), 1)) < 0
9542 && (- INTVAL (XEXP (SUBREG_REG (op0), 1))
9543 < GET_MODE_MASK (mode) / 2)
9544 && (unsigned HOST_WIDE_INT) const_op < GET_MODE_MASK (mode) / 2
9545 && (0 == (nonzero_bits (XEXP (SUBREG_REG (op0), 0),
9546 GET_MODE (SUBREG_REG (op0)))
9547 & ~ GET_MODE_MASK (mode))
9548 || (num_sign_bit_copies (XEXP (SUBREG_REG (op0), 0),
9549 GET_MODE (SUBREG_REG (op0)))
9550 > (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0)))
9551 - GET_MODE_BITSIZE (mode)))))
9553 op0 = SUBREG_REG (op0);
9557 /* If the inner mode is narrower and we are extracting the low part,
9558 we can treat the SUBREG as if it were a ZERO_EXTEND. */
9559 if (subreg_lowpart_p (op0)
9560 && GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0))) < mode_width)
9561 /* Fall through */ ;
9565 /* ... fall through ... */
9568 if ((unsigned_comparison_p || equality_comparison_p)
9569 && (GET_MODE_BITSIZE (GET_MODE (XEXP (op0, 0)))
9570 <= HOST_BITS_PER_WIDE_INT)
9571 && ((unsigned HOST_WIDE_INT) const_op
9572 < GET_MODE_MASK (GET_MODE (XEXP (op0, 0)))))
9574 op0 = XEXP (op0, 0);
9580 /* (eq (plus X A) B) -> (eq X (minus B A)). We can only do
9581 this for equality comparisons due to pathological cases involving
9583 if (equality_comparison_p
9584 && 0 != (tem = simplify_binary_operation (MINUS, mode,
9585 op1, XEXP (op0, 1))))
9587 op0 = XEXP (op0, 0);
9592 /* (plus (abs X) (const_int -1)) is < 0 if and only if X == 0. */
9593 if (const_op == 0 && XEXP (op0, 1) == constm1_rtx
9594 && GET_CODE (XEXP (op0, 0)) == ABS && sign_bit_comparison_p)
9596 op0 = XEXP (XEXP (op0, 0), 0);
9597 code = (code == LT ? EQ : NE);
9603 /* (eq (minus A B) C) -> (eq A (plus B C)) or
9604 (eq B (minus A C)), whichever simplifies. We can only do
9605 this for equality comparisons due to pathological cases involving
9607 if (equality_comparison_p
9608 && 0 != (tem = simplify_binary_operation (PLUS, mode,
9609 XEXP (op0, 1), op1)))
9611 op0 = XEXP (op0, 0);
9616 if (equality_comparison_p
9617 && 0 != (tem = simplify_binary_operation (MINUS, mode,
9618 XEXP (op0, 0), op1)))
9620 op0 = XEXP (op0, 1);
9625 /* The sign bit of (minus (ashiftrt X C) X), where C is the number
9626 of bits in X minus 1, is one iff X > 0. */
9627 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == ASHIFTRT
9628 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
9629 && INTVAL (XEXP (XEXP (op0, 0), 1)) == mode_width - 1
9630 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
9632 op0 = XEXP (op0, 1);
9633 code = (code == GE ? LE : GT);
9639 /* (eq (xor A B) C) -> (eq A (xor B C)). This is a simplification
9640 if C is zero or B is a constant. */
9641 if (equality_comparison_p
9642 && 0 != (tem = simplify_binary_operation (XOR, mode,
9643 XEXP (op0, 1), op1)))
9645 op0 = XEXP (op0, 0);
9652 case LT: case LTU: case LE: case LEU:
9653 case GT: case GTU: case GE: case GEU:
9654 /* We can't do anything if OP0 is a condition code value, rather
9655 than an actual data value. */
9658 || XEXP (op0, 0) == cc0_rtx
9660 || GET_MODE_CLASS (GET_MODE (XEXP (op0, 0))) == MODE_CC)
9663 /* Get the two operands being compared. */
9664 if (GET_CODE (XEXP (op0, 0)) == COMPARE)
9665 tem = XEXP (XEXP (op0, 0), 0), tem1 = XEXP (XEXP (op0, 0), 1);
9667 tem = XEXP (op0, 0), tem1 = XEXP (op0, 1);
9669 /* Check for the cases where we simply want the result of the
9670 earlier test or the opposite of that result. */
9672 || (code == EQ && reversible_comparison_p (op0))
9673 || (GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
9674 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
9675 && (STORE_FLAG_VALUE
9676 & (((HOST_WIDE_INT) 1
9677 << (GET_MODE_BITSIZE (GET_MODE (op0)) - 1))))
9679 || (code == GE && reversible_comparison_p (op0)))))
9681 code = (code == LT || code == NE
9682 ? GET_CODE (op0) : reverse_condition (GET_CODE (op0)));
9683 op0 = tem, op1 = tem1;
9689 /* The sign bit of (ior (plus X (const_int -1)) X) is non-zero
9691 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == PLUS
9692 && XEXP (XEXP (op0, 0), 1) == constm1_rtx
9693 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
9695 op0 = XEXP (op0, 1);
9696 code = (code == GE ? GT : LE);
9702 /* Convert (and (xshift 1 X) Y) to (and (lshiftrt Y X) 1). This
9703 will be converted to a ZERO_EXTRACT later. */
9704 if (const_op == 0 && equality_comparison_p
9705 && GET_CODE (XEXP (op0, 0)) == ASHIFT
9706 && XEXP (XEXP (op0, 0), 0) == const1_rtx)
9708 op0 = simplify_and_const_int
9709 (op0, mode, gen_rtx_combine (LSHIFTRT, mode,
9711 XEXP (XEXP (op0, 0), 1)),
9716 /* If we are comparing (and (lshiftrt X C1) C2) for equality with
9717 zero and X is a comparison and C1 and C2 describe only bits set
9718 in STORE_FLAG_VALUE, we can compare with X. */
9719 if (const_op == 0 && equality_comparison_p
9720 && mode_width <= HOST_BITS_PER_WIDE_INT
9721 && GET_CODE (XEXP (op0, 1)) == CONST_INT
9722 && GET_CODE (XEXP (op0, 0)) == LSHIFTRT
9723 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
9724 && INTVAL (XEXP (XEXP (op0, 0), 1)) >= 0
9725 && INTVAL (XEXP (XEXP (op0, 0), 1)) < HOST_BITS_PER_WIDE_INT)
9727 mask = ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
9728 << INTVAL (XEXP (XEXP (op0, 0), 1)));
9729 if ((~ STORE_FLAG_VALUE & mask) == 0
9730 && (GET_RTX_CLASS (GET_CODE (XEXP (XEXP (op0, 0), 0))) == '<'
9731 || ((tem = get_last_value (XEXP (XEXP (op0, 0), 0))) != 0
9732 && GET_RTX_CLASS (GET_CODE (tem)) == '<')))
9734 op0 = XEXP (XEXP (op0, 0), 0);
9739 /* If we are doing an equality comparison of an AND of a bit equal
9740 to the sign bit, replace this with a LT or GE comparison of
9741 the underlying value. */
9742 if (equality_comparison_p
9744 && GET_CODE (XEXP (op0, 1)) == CONST_INT
9745 && mode_width <= HOST_BITS_PER_WIDE_INT
9746 && ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
9747 == (HOST_WIDE_INT) 1 << (mode_width - 1)))
9749 op0 = XEXP (op0, 0);
9750 code = (code == EQ ? GE : LT);
9754 /* If this AND operation is really a ZERO_EXTEND from a narrower
9755 mode, the constant fits within that mode, and this is either an
9756 equality or unsigned comparison, try to do this comparison in
9757 the narrower mode. */
9758 if ((equality_comparison_p || unsigned_comparison_p)
9759 && GET_CODE (XEXP (op0, 1)) == CONST_INT
9760 && (i = exact_log2 ((INTVAL (XEXP (op0, 1))
9761 & GET_MODE_MASK (mode))
9763 && const_op >> i == 0
9764 && (tmode = mode_for_size (i, MODE_INT, 1)) != BLKmode)
9766 op0 = gen_lowpart_for_combine (tmode, XEXP (op0, 0));
9772 /* If we have (compare (ashift FOO N) (const_int C)) and
9773 the high order N bits of FOO (N+1 if an inequality comparison)
9774 are known to be zero, we can do this by comparing FOO with C
9775 shifted right N bits so long as the low-order N bits of C are
9777 if (GET_CODE (XEXP (op0, 1)) == CONST_INT
9778 && INTVAL (XEXP (op0, 1)) >= 0
9779 && ((INTVAL (XEXP (op0, 1)) + ! equality_comparison_p)
9780 < HOST_BITS_PER_WIDE_INT)
9782 & (((HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1))) - 1)) == 0)
9783 && mode_width <= HOST_BITS_PER_WIDE_INT
9784 && (nonzero_bits (XEXP (op0, 0), mode)
9785 & ~ (mask >> (INTVAL (XEXP (op0, 1))
9786 + ! equality_comparison_p))) == 0)
9788 const_op >>= INTVAL (XEXP (op0, 1));
9789 op1 = GEN_INT (const_op);
9790 op0 = XEXP (op0, 0);
9794 /* If we are doing a sign bit comparison, it means we are testing
9795 a particular bit. Convert it to the appropriate AND. */
9796 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 1)) == CONST_INT
9797 && mode_width <= HOST_BITS_PER_WIDE_INT)
9799 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
9802 - INTVAL (XEXP (op0, 1)))));
9803 code = (code == LT ? NE : EQ);
9807 /* If this an equality comparison with zero and we are shifting
9808 the low bit to the sign bit, we can convert this to an AND of the
9810 if (const_op == 0 && equality_comparison_p
9811 && GET_CODE (XEXP (op0, 1)) == CONST_INT
9812 && INTVAL (XEXP (op0, 1)) == mode_width - 1)
9814 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
9821 /* If this is an equality comparison with zero, we can do this
9822 as a logical shift, which might be much simpler. */
9823 if (equality_comparison_p && const_op == 0
9824 && GET_CODE (XEXP (op0, 1)) == CONST_INT)
9826 op0 = simplify_shift_const (NULL_RTX, LSHIFTRT, mode,
9828 INTVAL (XEXP (op0, 1)));
9832 /* If OP0 is a sign extension and CODE is not an unsigned comparison,
9833 do the comparison in a narrower mode. */
9834 if (! unsigned_comparison_p
9835 && GET_CODE (XEXP (op0, 1)) == CONST_INT
9836 && GET_CODE (XEXP (op0, 0)) == ASHIFT
9837 && XEXP (op0, 1) == XEXP (XEXP (op0, 0), 1)
9838 && (tmode = mode_for_size (mode_width - INTVAL (XEXP (op0, 1)),
9839 MODE_INT, 1)) != BLKmode
9840 && ((unsigned HOST_WIDE_INT) const_op <= GET_MODE_MASK (tmode)
9841 || ((unsigned HOST_WIDE_INT) - const_op
9842 <= GET_MODE_MASK (tmode))))
9844 op0 = gen_lowpart_for_combine (tmode, XEXP (XEXP (op0, 0), 0));
9848 /* ... fall through ... */
9850 /* If we have (compare (xshiftrt FOO N) (const_int C)) and
9851 the low order N bits of FOO are known to be zero, we can do this
9852 by comparing FOO with C shifted left N bits so long as no
9854 if (GET_CODE (XEXP (op0, 1)) == CONST_INT
9855 && INTVAL (XEXP (op0, 1)) >= 0
9856 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT
9857 && mode_width <= HOST_BITS_PER_WIDE_INT
9858 && (nonzero_bits (XEXP (op0, 0), mode)
9859 & (((HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1))) - 1)) == 0
9861 || (floor_log2 (const_op) + INTVAL (XEXP (op0, 1))
9864 const_op <<= INTVAL (XEXP (op0, 1));
9865 op1 = GEN_INT (const_op);
9866 op0 = XEXP (op0, 0);
9870 /* If we are using this shift to extract just the sign bit, we
9871 can replace this with an LT or GE comparison. */
9873 && (equality_comparison_p || sign_bit_comparison_p)
9874 && GET_CODE (XEXP (op0, 1)) == CONST_INT
9875 && INTVAL (XEXP (op0, 1)) == mode_width - 1)
9877 op0 = XEXP (op0, 0);
9878 code = (code == NE || code == GT ? LT : GE);
9887 /* Now make any compound operations involved in this comparison. Then,
9888 check for an outmost SUBREG on OP0 that isn't doing anything or is
9889 paradoxical. The latter case can only occur when it is known that the
9890 "extra" bits will be zero. Therefore, it is safe to remove the SUBREG.
9891 We can never remove a SUBREG for a non-equality comparison because the
9892 sign bit is in a different place in the underlying object. */
9894 op0 = make_compound_operation (op0, op1 == const0_rtx ? COMPARE : SET);
9895 op1 = make_compound_operation (op1, SET);
9897 if (GET_CODE (op0) == SUBREG && subreg_lowpart_p (op0)
9898 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
9899 && (code == NE || code == EQ)
9900 && ((GET_MODE_SIZE (GET_MODE (op0))
9901 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (op0))))))
9903 op0 = SUBREG_REG (op0);
9904 op1 = gen_lowpart_for_combine (GET_MODE (op0), op1);
9907 else if (GET_CODE (op0) == SUBREG && subreg_lowpart_p (op0)
9908 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
9909 && (code == NE || code == EQ)
9910 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0)))
9911 <= HOST_BITS_PER_WIDE_INT)
9912 && (nonzero_bits (SUBREG_REG (op0), GET_MODE (SUBREG_REG (op0)))
9913 & ~ GET_MODE_MASK (GET_MODE (op0))) == 0
9914 && (tem = gen_lowpart_for_combine (GET_MODE (SUBREG_REG (op0)),
9916 (nonzero_bits (tem, GET_MODE (SUBREG_REG (op0)))
9917 & ~ GET_MODE_MASK (GET_MODE (op0))) == 0))
9918 op0 = SUBREG_REG (op0), op1 = tem;
9920 /* We now do the opposite procedure: Some machines don't have compare
9921 insns in all modes. If OP0's mode is an integer mode smaller than a
9922 word and we can't do a compare in that mode, see if there is a larger
9923 mode for which we can do the compare. There are a number of cases in
9924 which we can use the wider mode. */
9926 mode = GET_MODE (op0);
9927 if (mode != VOIDmode && GET_MODE_CLASS (mode) == MODE_INT
9928 && GET_MODE_SIZE (mode) < UNITS_PER_WORD
9929 && cmp_optab->handlers[(int) mode].insn_code == CODE_FOR_nothing)
9930 for (tmode = GET_MODE_WIDER_MODE (mode);
9932 && GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT);
9933 tmode = GET_MODE_WIDER_MODE (tmode))
9934 if (cmp_optab->handlers[(int) tmode].insn_code != CODE_FOR_nothing)
9936 /* If the only nonzero bits in OP0 and OP1 are those in the
9937 narrower mode and this is an equality or unsigned comparison,
9938 we can use the wider mode. Similarly for sign-extended
9939 values, in which case it is true for all comparisons. */
9940 if (((code == EQ || code == NE
9941 || code == GEU || code == GTU || code == LEU || code == LTU)
9942 && (nonzero_bits (op0, tmode) & ~ GET_MODE_MASK (mode)) == 0
9943 && (nonzero_bits (op1, tmode) & ~ GET_MODE_MASK (mode)) == 0)
9944 || ((num_sign_bit_copies (op0, tmode)
9945 > GET_MODE_BITSIZE (tmode) - GET_MODE_BITSIZE (mode))
9946 && (num_sign_bit_copies (op1, tmode)
9947 > GET_MODE_BITSIZE (tmode) - GET_MODE_BITSIZE (mode))))
9949 op0 = gen_lowpart_for_combine (tmode, op0);
9950 op1 = gen_lowpart_for_combine (tmode, op1);
9954 /* If this is a test for negative, we can make an explicit
9955 test of the sign bit. */
9957 if (op1 == const0_rtx && (code == LT || code == GE)
9958 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
9960 op0 = gen_binary (AND, tmode,
9961 gen_lowpart_for_combine (tmode, op0),
9962 GEN_INT ((HOST_WIDE_INT) 1
9963 << (GET_MODE_BITSIZE (mode) - 1)));
9964 code = (code == LT) ? NE : EQ;
9969 #ifdef CANONICALIZE_COMPARISON
9970 /* If this machine only supports a subset of valid comparisons, see if we
9971 can convert an unsupported one into a supported one. */
9972 CANONICALIZE_COMPARISON (code, op0, op1);
9981 /* Return 1 if we know that X, a comparison operation, is not operating
9982 on a floating-point value or is EQ or NE, meaning that we can safely
9986 reversible_comparison_p (x)
9989 if (TARGET_FLOAT_FORMAT != IEEE_FLOAT_FORMAT
9991 || GET_CODE (x) == NE || GET_CODE (x) == EQ)
9994 switch (GET_MODE_CLASS (GET_MODE (XEXP (x, 0))))
9997 case MODE_PARTIAL_INT:
9998 case MODE_COMPLEX_INT:
10002 /* If the mode of the condition codes tells us that this is safe,
10003 we need look no further. */
10004 if (REVERSIBLE_CC_MODE (GET_MODE (XEXP (x, 0))))
10007 /* Otherwise try and find where the condition codes were last set and
10009 x = get_last_value (XEXP (x, 0));
10010 return (x && GET_CODE (x) == COMPARE
10011 && ! FLOAT_MODE_P (GET_MODE (XEXP (x, 0))));
10017 /* Utility function for following routine. Called when X is part of a value
10018 being stored into reg_last_set_value. Sets reg_last_set_table_tick
10019 for each register mentioned. Similar to mention_regs in cse.c */
10022 update_table_tick (x)
10025 register enum rtx_code code = GET_CODE (x);
10026 register char *fmt = GET_RTX_FORMAT (code);
10031 int regno = REGNO (x);
10032 int endregno = regno + (regno < FIRST_PSEUDO_REGISTER
10033 ? HARD_REGNO_NREGS (regno, GET_MODE (x)) : 1);
10035 for (i = regno; i < endregno; i++)
10036 reg_last_set_table_tick[i] = label_tick;
10041 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
10042 /* Note that we can't have an "E" in values stored; see
10043 get_last_value_validate. */
10045 update_table_tick (XEXP (x, i));
10048 /* Record that REG is set to VALUE in insn INSN. If VALUE is zero, we
10049 are saying that the register is clobbered and we no longer know its
10050 value. If INSN is zero, don't update reg_last_set; this is only permitted
10051 with VALUE also zero and is used to invalidate the register. */
10054 record_value_for_reg (reg, insn, value)
10059 int regno = REGNO (reg);
10060 int endregno = regno + (regno < FIRST_PSEUDO_REGISTER
10061 ? HARD_REGNO_NREGS (regno, GET_MODE (reg)) : 1);
10064 /* If VALUE contains REG and we have a previous value for REG, substitute
10065 the previous value. */
10066 if (value && insn && reg_overlap_mentioned_p (reg, value))
10070 /* Set things up so get_last_value is allowed to see anything set up to
10072 subst_low_cuid = INSN_CUID (insn);
10073 tem = get_last_value (reg);
10076 value = replace_rtx (copy_rtx (value), reg, tem);
10079 /* For each register modified, show we don't know its value, that
10080 we don't know about its bitwise content, that its value has been
10081 updated, and that we don't know the location of the death of the
10083 for (i = regno; i < endregno; i ++)
10086 reg_last_set[i] = insn;
10087 reg_last_set_value[i] = 0;
10088 reg_last_set_mode[i] = 0;
10089 reg_last_set_nonzero_bits[i] = 0;
10090 reg_last_set_sign_bit_copies[i] = 0;
10091 reg_last_death[i] = 0;
10094 /* Mark registers that are being referenced in this value. */
10096 update_table_tick (value);
10098 /* Now update the status of each register being set.
10099 If someone is using this register in this block, set this register
10100 to invalid since we will get confused between the two lives in this
10101 basic block. This makes using this register always invalid. In cse, we
10102 scan the table to invalidate all entries using this register, but this
10103 is too much work for us. */
10105 for (i = regno; i < endregno; i++)
10107 reg_last_set_label[i] = label_tick;
10108 if (value && reg_last_set_table_tick[i] == label_tick)
10109 reg_last_set_invalid[i] = 1;
10111 reg_last_set_invalid[i] = 0;
10114 /* The value being assigned might refer to X (like in "x++;"). In that
10115 case, we must replace it with (clobber (const_int 0)) to prevent
10117 if (value && ! get_last_value_validate (&value,
10118 reg_last_set_label[regno], 0))
10120 value = copy_rtx (value);
10121 if (! get_last_value_validate (&value, reg_last_set_label[regno], 1))
10125 /* For the main register being modified, update the value, the mode, the
10126 nonzero bits, and the number of sign bit copies. */
10128 reg_last_set_value[regno] = value;
10132 subst_low_cuid = INSN_CUID (insn);
10133 reg_last_set_mode[regno] = GET_MODE (reg);
10134 reg_last_set_nonzero_bits[regno] = nonzero_bits (value, GET_MODE (reg));
10135 reg_last_set_sign_bit_copies[regno]
10136 = num_sign_bit_copies (value, GET_MODE (reg));
10140 /* Used for communication between the following two routines. */
10141 static rtx record_dead_insn;
10143 /* Called via note_stores from record_dead_and_set_regs to handle one
10144 SET or CLOBBER in an insn. */
10147 record_dead_and_set_regs_1 (dest, setter)
10150 if (GET_CODE (dest) == SUBREG)
10151 dest = SUBREG_REG (dest);
10153 if (GET_CODE (dest) == REG)
10155 /* If we are setting the whole register, we know its value. Otherwise
10156 show that we don't know the value. We can handle SUBREG in
10158 if (GET_CODE (setter) == SET && dest == SET_DEST (setter))
10159 record_value_for_reg (dest, record_dead_insn, SET_SRC (setter));
10160 else if (GET_CODE (setter) == SET
10161 && GET_CODE (SET_DEST (setter)) == SUBREG
10162 && SUBREG_REG (SET_DEST (setter)) == dest
10163 && GET_MODE_BITSIZE (GET_MODE (dest)) <= BITS_PER_WORD
10164 && subreg_lowpart_p (SET_DEST (setter)))
10165 record_value_for_reg (dest, record_dead_insn,
10166 gen_lowpart_for_combine (GET_MODE (dest),
10167 SET_SRC (setter)));
10169 record_value_for_reg (dest, record_dead_insn, NULL_RTX);
10171 else if (GET_CODE (dest) == MEM
10172 /* Ignore pushes, they clobber nothing. */
10173 && ! push_operand (dest, GET_MODE (dest)))
10174 mem_last_set = INSN_CUID (record_dead_insn);
10177 /* Update the records of when each REG was most recently set or killed
10178 for the things done by INSN. This is the last thing done in processing
10179 INSN in the combiner loop.
10181 We update reg_last_set, reg_last_set_value, reg_last_set_mode,
10182 reg_last_set_nonzero_bits, reg_last_set_sign_bit_copies, reg_last_death,
10183 and also the similar information mem_last_set (which insn most recently
10184 modified memory) and last_call_cuid (which insn was the most recent
10185 subroutine call). */
10188 record_dead_and_set_regs (insn)
10194 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
10196 if (REG_NOTE_KIND (link) == REG_DEAD
10197 && GET_CODE (XEXP (link, 0)) == REG)
10199 int regno = REGNO (XEXP (link, 0));
10201 = regno + (regno < FIRST_PSEUDO_REGISTER
10202 ? HARD_REGNO_NREGS (regno, GET_MODE (XEXP (link, 0)))
10205 for (i = regno; i < endregno; i++)
10206 reg_last_death[i] = insn;
10208 else if (REG_NOTE_KIND (link) == REG_INC)
10209 record_value_for_reg (XEXP (link, 0), insn, NULL_RTX);
10212 if (GET_CODE (insn) == CALL_INSN)
10214 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
10215 if (call_used_regs[i])
10217 reg_last_set_value[i] = 0;
10218 reg_last_set_mode[i] = 0;
10219 reg_last_set_nonzero_bits[i] = 0;
10220 reg_last_set_sign_bit_copies[i] = 0;
10221 reg_last_death[i] = 0;
10224 last_call_cuid = mem_last_set = INSN_CUID (insn);
10227 record_dead_insn = insn;
10228 note_stores (PATTERN (insn), record_dead_and_set_regs_1);
10231 /* Utility routine for the following function. Verify that all the registers
10232 mentioned in *LOC are valid when *LOC was part of a value set when
10233 label_tick == TICK. Return 0 if some are not.
10235 If REPLACE is non-zero, replace the invalid reference with
10236 (clobber (const_int 0)) and return 1. This replacement is useful because
10237 we often can get useful information about the form of a value (e.g., if
10238 it was produced by a shift that always produces -1 or 0) even though
10239 we don't know exactly what registers it was produced from. */
10242 get_last_value_validate (loc, tick, replace)
10248 char *fmt = GET_RTX_FORMAT (GET_CODE (x));
10249 int len = GET_RTX_LENGTH (GET_CODE (x));
10252 if (GET_CODE (x) == REG)
10254 int regno = REGNO (x);
10255 int endregno = regno + (regno < FIRST_PSEUDO_REGISTER
10256 ? HARD_REGNO_NREGS (regno, GET_MODE (x)) : 1);
10259 for (j = regno; j < endregno; j++)
10260 if (reg_last_set_invalid[j]
10261 /* If this is a pseudo-register that was only set once, it is
10263 || (! (regno >= FIRST_PSEUDO_REGISTER && reg_n_sets[regno] == 1)
10264 && reg_last_set_label[j] > tick))
10267 *loc = gen_rtx (CLOBBER, GET_MODE (x), const0_rtx);
10274 for (i = 0; i < len; i++)
10276 && get_last_value_validate (&XEXP (x, i), tick, replace) == 0)
10277 /* Don't bother with these. They shouldn't occur anyway. */
10281 /* If we haven't found a reason for it to be invalid, it is valid. */
10285 /* Get the last value assigned to X, if known. Some registers
10286 in the value may be replaced with (clobber (const_int 0)) if their value
10287 is known longer known reliably. */
10296 /* If this is a non-paradoxical SUBREG, get the value of its operand and
10297 then convert it to the desired mode. If this is a paradoxical SUBREG,
10298 we cannot predict what values the "extra" bits might have. */
10299 if (GET_CODE (x) == SUBREG
10300 && subreg_lowpart_p (x)
10301 && (GET_MODE_SIZE (GET_MODE (x))
10302 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
10303 && (value = get_last_value (SUBREG_REG (x))) != 0)
10304 return gen_lowpart_for_combine (GET_MODE (x), value);
10306 if (GET_CODE (x) != REG)
10310 value = reg_last_set_value[regno];
10312 /* If we don't have a value or if it isn't for this basic block,
10316 || (reg_n_sets[regno] != 1
10317 && reg_last_set_label[regno] != label_tick))
10320 /* If the value was set in a later insn than the ones we are processing,
10321 we can't use it even if the register was only set once, but make a quick
10322 check to see if the previous insn set it to something. This is commonly
10323 the case when the same pseudo is used by repeated insns.
10325 This does not work if there exists an instruction which is temporarily
10326 not on the insn chain. */
10328 if (INSN_CUID (reg_last_set[regno]) >= subst_low_cuid)
10332 /* We can not do anything useful in this case, because there is
10333 an instruction which is not on the insn chain. */
10334 if (subst_prev_insn)
10337 /* Skip over USE insns. They are not useful here, and they may have
10338 been made by combine, in which case they do not have a INSN_CUID
10339 value. We can't use prev_real_insn, because that would incorrectly
10340 take us backwards across labels. Skip over BARRIERs also, since
10341 they could have been made by combine. If we see one, we must be
10342 optimizing dead code, so it doesn't matter what we do. */
10343 for (insn = prev_nonnote_insn (subst_insn);
10344 insn && ((GET_CODE (insn) == INSN
10345 && GET_CODE (PATTERN (insn)) == USE)
10346 || GET_CODE (insn) == BARRIER
10347 || INSN_CUID (insn) >= subst_low_cuid);
10348 insn = prev_nonnote_insn (insn))
10352 && (set = single_set (insn)) != 0
10353 && rtx_equal_p (SET_DEST (set), x))
10355 value = SET_SRC (set);
10357 /* Make sure that VALUE doesn't reference X. Replace any
10358 explicit references with a CLOBBER. If there are any remaining
10359 references (rare), don't use the value. */
10361 if (reg_mentioned_p (x, value))
10362 value = replace_rtx (copy_rtx (value), x,
10363 gen_rtx (CLOBBER, GET_MODE (x), const0_rtx));
10365 if (reg_overlap_mentioned_p (x, value))
10372 /* If the value has all its registers valid, return it. */
10373 if (get_last_value_validate (&value, reg_last_set_label[regno], 0))
10376 /* Otherwise, make a copy and replace any invalid register with
10377 (clobber (const_int 0)). If that fails for some reason, return 0. */
10379 value = copy_rtx (value);
10380 if (get_last_value_validate (&value, reg_last_set_label[regno], 1))
10386 /* Return nonzero if expression X refers to a REG or to memory
10387 that is set in an instruction more recent than FROM_CUID. */
10390 use_crosses_set_p (x, from_cuid)
10394 register char *fmt;
10396 register enum rtx_code code = GET_CODE (x);
10400 register int regno = REGNO (x);
10401 int endreg = regno + (regno < FIRST_PSEUDO_REGISTER
10402 ? HARD_REGNO_NREGS (regno, GET_MODE (x)) : 1);
10404 #ifdef PUSH_ROUNDING
10405 /* Don't allow uses of the stack pointer to be moved,
10406 because we don't know whether the move crosses a push insn. */
10407 if (regno == STACK_POINTER_REGNUM)
10410 for (;regno < endreg; regno++)
10411 if (reg_last_set[regno]
10412 && INSN_CUID (reg_last_set[regno]) > from_cuid)
10417 if (code == MEM && mem_last_set > from_cuid)
10420 fmt = GET_RTX_FORMAT (code);
10422 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
10427 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
10428 if (use_crosses_set_p (XVECEXP (x, i, j), from_cuid))
10431 else if (fmt[i] == 'e'
10432 && use_crosses_set_p (XEXP (x, i), from_cuid))
10438 /* Define three variables used for communication between the following
10441 static int reg_dead_regno, reg_dead_endregno;
10442 static int reg_dead_flag;
10444 /* Function called via note_stores from reg_dead_at_p.
10446 If DEST is within [reg_dead_regno, reg_dead_endregno), set
10447 reg_dead_flag to 1 if X is a CLOBBER and to -1 it is a SET. */
10450 reg_dead_at_p_1 (dest, x)
10454 int regno, endregno;
10456 if (GET_CODE (dest) != REG)
10459 regno = REGNO (dest);
10460 endregno = regno + (regno < FIRST_PSEUDO_REGISTER
10461 ? HARD_REGNO_NREGS (regno, GET_MODE (dest)) : 1);
10463 if (reg_dead_endregno > regno && reg_dead_regno < endregno)
10464 reg_dead_flag = (GET_CODE (x) == CLOBBER) ? 1 : -1;
10467 /* Return non-zero if REG is known to be dead at INSN.
10469 We scan backwards from INSN. If we hit a REG_DEAD note or a CLOBBER
10470 referencing REG, it is dead. If we hit a SET referencing REG, it is
10471 live. Otherwise, see if it is live or dead at the start of the basic
10472 block we are in. Hard regs marked as being live in NEWPAT_USED_REGS
10473 must be assumed to be always live. */
10476 reg_dead_at_p (reg, insn)
10482 /* Set variables for reg_dead_at_p_1. */
10483 reg_dead_regno = REGNO (reg);
10484 reg_dead_endregno = reg_dead_regno + (reg_dead_regno < FIRST_PSEUDO_REGISTER
10485 ? HARD_REGNO_NREGS (reg_dead_regno,
10491 /* Check that reg isn't mentioned in NEWPAT_USED_REGS. */
10492 if (reg_dead_regno < FIRST_PSEUDO_REGISTER)
10494 for (i = reg_dead_regno; i < reg_dead_endregno; i++)
10495 if (TEST_HARD_REG_BIT (newpat_used_regs, i))
10499 /* Scan backwards until we find a REG_DEAD note, SET, CLOBBER, label, or
10500 beginning of function. */
10501 for (; insn && GET_CODE (insn) != CODE_LABEL && GET_CODE (insn) != BARRIER;
10502 insn = prev_nonnote_insn (insn))
10504 note_stores (PATTERN (insn), reg_dead_at_p_1);
10506 return reg_dead_flag == 1 ? 1 : 0;
10508 if (find_regno_note (insn, REG_DEAD, reg_dead_regno))
10512 /* Get the basic block number that we were in. */
10517 for (block = 0; block < n_basic_blocks; block++)
10518 if (insn == basic_block_head[block])
10521 if (block == n_basic_blocks)
10525 for (i = reg_dead_regno; i < reg_dead_endregno; i++)
10526 if (basic_block_live_at_start[block][i / REGSET_ELT_BITS]
10527 & ((REGSET_ELT_TYPE) 1 << (i % REGSET_ELT_BITS)))
10533 /* Note hard registers in X that are used. This code is similar to
10534 that in flow.c, but much simpler since we don't care about pseudos. */
10537 mark_used_regs_combine (x)
10540 register RTX_CODE code = GET_CODE (x);
10541 register int regno;
10553 case ADDR_DIFF_VEC:
10556 /* CC0 must die in the insn after it is set, so we don't need to take
10557 special note of it here. */
10563 /* If we are clobbering a MEM, mark any hard registers inside the
10564 address as used. */
10565 if (GET_CODE (XEXP (x, 0)) == MEM)
10566 mark_used_regs_combine (XEXP (XEXP (x, 0), 0));
10571 /* A hard reg in a wide mode may really be multiple registers.
10572 If so, mark all of them just like the first. */
10573 if (regno < FIRST_PSEUDO_REGISTER)
10575 /* None of this applies to the stack, frame or arg pointers */
10576 if (regno == STACK_POINTER_REGNUM
10577 #if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM
10578 || regno == HARD_FRAME_POINTER_REGNUM
10580 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
10581 || (regno == ARG_POINTER_REGNUM && fixed_regs[regno])
10583 || regno == FRAME_POINTER_REGNUM)
10586 i = HARD_REGNO_NREGS (regno, GET_MODE (x));
10588 SET_HARD_REG_BIT (newpat_used_regs, regno + i);
10594 /* If setting a MEM, or a SUBREG of a MEM, then note any hard regs in
10596 register rtx testreg = SET_DEST (x);
10598 while (GET_CODE (testreg) == SUBREG
10599 || GET_CODE (testreg) == ZERO_EXTRACT
10600 || GET_CODE (testreg) == SIGN_EXTRACT
10601 || GET_CODE (testreg) == STRICT_LOW_PART)
10602 testreg = XEXP (testreg, 0);
10604 if (GET_CODE (testreg) == MEM)
10605 mark_used_regs_combine (XEXP (testreg, 0));
10607 mark_used_regs_combine (SET_SRC (x));
10612 /* Recursively scan the operands of this expression. */
10615 register char *fmt = GET_RTX_FORMAT (code);
10617 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
10620 mark_used_regs_combine (XEXP (x, i));
10621 else if (fmt[i] == 'E')
10625 for (j = 0; j < XVECLEN (x, i); j++)
10626 mark_used_regs_combine (XVECEXP (x, i, j));
10633 /* Remove register number REGNO from the dead registers list of INSN.
10635 Return the note used to record the death, if there was one. */
10638 remove_death (regno, insn)
10642 register rtx note = find_regno_note (insn, REG_DEAD, regno);
10646 reg_n_deaths[regno]--;
10647 remove_note (insn, note);
10653 /* For each register (hardware or pseudo) used within expression X, if its
10654 death is in an instruction with cuid between FROM_CUID (inclusive) and
10655 TO_INSN (exclusive), put a REG_DEAD note for that register in the
10656 list headed by PNOTES.
10658 That said, don't move registers killed by maybe_kill_insn.
10660 This is done when X is being merged by combination into TO_INSN. These
10661 notes will then be distributed as needed. */
10664 move_deaths (x, maybe_kill_insn, from_cuid, to_insn, pnotes)
10666 rtx maybe_kill_insn;
10671 register char *fmt;
10672 register int len, i;
10673 register enum rtx_code code = GET_CODE (x);
10677 register int regno = REGNO (x);
10678 register rtx where_dead = reg_last_death[regno];
10679 register rtx before_dead, after_dead;
10681 /* Don't move the register if it gets killed in between from and to */
10682 if (maybe_kill_insn && reg_set_p (x, maybe_kill_insn)
10683 && !reg_referenced_p (x, maybe_kill_insn))
10686 /* WHERE_DEAD could be a USE insn made by combine, so first we
10687 make sure that we have insns with valid INSN_CUID values. */
10688 before_dead = where_dead;
10689 while (before_dead && INSN_UID (before_dead) > max_uid_cuid)
10690 before_dead = PREV_INSN (before_dead);
10691 after_dead = where_dead;
10692 while (after_dead && INSN_UID (after_dead) > max_uid_cuid)
10693 after_dead = NEXT_INSN (after_dead);
10695 if (before_dead && after_dead
10696 && INSN_CUID (before_dead) >= from_cuid
10697 && (INSN_CUID (after_dead) < INSN_CUID (to_insn)
10698 || (where_dead != after_dead
10699 && INSN_CUID (after_dead) == INSN_CUID (to_insn))))
10701 rtx note = remove_death (regno, where_dead);
10703 /* It is possible for the call above to return 0. This can occur
10704 when reg_last_death points to I2 or I1 that we combined with.
10705 In that case make a new note.
10707 We must also check for the case where X is a hard register
10708 and NOTE is a death note for a range of hard registers
10709 including X. In that case, we must put REG_DEAD notes for
10710 the remaining registers in place of NOTE. */
10712 if (note != 0 && regno < FIRST_PSEUDO_REGISTER
10713 && (GET_MODE_SIZE (GET_MODE (XEXP (note, 0)))
10714 != GET_MODE_SIZE (GET_MODE (x))))
10716 int deadregno = REGNO (XEXP (note, 0));
10718 = (deadregno + HARD_REGNO_NREGS (deadregno,
10719 GET_MODE (XEXP (note, 0))));
10720 int ourend = regno + HARD_REGNO_NREGS (regno, GET_MODE (x));
10723 for (i = deadregno; i < deadend; i++)
10724 if (i < regno || i >= ourend)
10725 REG_NOTES (where_dead)
10726 = gen_rtx (EXPR_LIST, REG_DEAD,
10727 gen_rtx (REG, reg_raw_mode[i], i),
10728 REG_NOTES (where_dead));
10730 /* If we didn't find any note, and we have a multi-reg hard
10731 register, then to be safe we must check for REG_DEAD notes
10732 for each register other than the first. They could have
10733 their own REG_DEAD notes lying around. */
10734 else if (note == 0 && regno < FIRST_PSEUDO_REGISTER
10735 && HARD_REGNO_NREGS (regno, GET_MODE (x)) > 1)
10737 int ourend = regno + HARD_REGNO_NREGS (regno, GET_MODE (x));
10741 for (i = regno + 1; i < ourend; i++)
10742 move_deaths (gen_rtx (REG, reg_raw_mode[i], i),
10743 maybe_kill_insn, from_cuid, to_insn, &oldnotes);
10746 if (note != 0 && GET_MODE (XEXP (note, 0)) == GET_MODE (x))
10748 XEXP (note, 1) = *pnotes;
10752 *pnotes = gen_rtx (EXPR_LIST, REG_DEAD, x, *pnotes);
10754 reg_n_deaths[regno]++;
10760 else if (GET_CODE (x) == SET)
10762 rtx dest = SET_DEST (x);
10764 move_deaths (SET_SRC (x), maybe_kill_insn, from_cuid, to_insn, pnotes);
10766 /* In the case of a ZERO_EXTRACT, a STRICT_LOW_PART, or a SUBREG
10767 that accesses one word of a multi-word item, some
10768 piece of everything register in the expression is used by
10769 this insn, so remove any old death. */
10771 if (GET_CODE (dest) == ZERO_EXTRACT
10772 || GET_CODE (dest) == STRICT_LOW_PART
10773 || (GET_CODE (dest) == SUBREG
10774 && (((GET_MODE_SIZE (GET_MODE (dest))
10775 + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
10776 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (dest)))
10777 + UNITS_PER_WORD - 1) / UNITS_PER_WORD))))
10779 move_deaths (dest, maybe_kill_insn, from_cuid, to_insn, pnotes);
10783 /* If this is some other SUBREG, we know it replaces the entire
10784 value, so use that as the destination. */
10785 if (GET_CODE (dest) == SUBREG)
10786 dest = SUBREG_REG (dest);
10788 /* If this is a MEM, adjust deaths of anything used in the address.
10789 For a REG (the only other possibility), the entire value is
10790 being replaced so the old value is not used in this insn. */
10792 if (GET_CODE (dest) == MEM)
10793 move_deaths (XEXP (dest, 0), maybe_kill_insn, from_cuid,
10798 else if (GET_CODE (x) == CLOBBER)
10801 len = GET_RTX_LENGTH (code);
10802 fmt = GET_RTX_FORMAT (code);
10804 for (i = 0; i < len; i++)
10809 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
10810 move_deaths (XVECEXP (x, i, j), maybe_kill_insn, from_cuid,
10813 else if (fmt[i] == 'e')
10814 move_deaths (XEXP (x, i), maybe_kill_insn, from_cuid, to_insn, pnotes);
10818 /* Return 1 if X is the target of a bit-field assignment in BODY, the
10819 pattern of an insn. X must be a REG. */
10822 reg_bitfield_target_p (x, body)
10828 if (GET_CODE (body) == SET)
10830 rtx dest = SET_DEST (body);
10832 int regno, tregno, endregno, endtregno;
10834 if (GET_CODE (dest) == ZERO_EXTRACT)
10835 target = XEXP (dest, 0);
10836 else if (GET_CODE (dest) == STRICT_LOW_PART)
10837 target = SUBREG_REG (XEXP (dest, 0));
10841 if (GET_CODE (target) == SUBREG)
10842 target = SUBREG_REG (target);
10844 if (GET_CODE (target) != REG)
10847 tregno = REGNO (target), regno = REGNO (x);
10848 if (tregno >= FIRST_PSEUDO_REGISTER || regno >= FIRST_PSEUDO_REGISTER)
10849 return target == x;
10851 endtregno = tregno + HARD_REGNO_NREGS (tregno, GET_MODE (target));
10852 endregno = regno + HARD_REGNO_NREGS (regno, GET_MODE (x));
10854 return endregno > tregno && regno < endtregno;
10857 else if (GET_CODE (body) == PARALLEL)
10858 for (i = XVECLEN (body, 0) - 1; i >= 0; i--)
10859 if (reg_bitfield_target_p (x, XVECEXP (body, 0, i)))
10865 /* Given a chain of REG_NOTES originally from FROM_INSN, try to place them
10866 as appropriate. I3 and I2 are the insns resulting from the combination
10867 insns including FROM (I2 may be zero).
10869 ELIM_I2 and ELIM_I1 are either zero or registers that we know will
10870 not need REG_DEAD notes because they are being substituted for. This
10871 saves searching in the most common cases.
10873 Each note in the list is either ignored or placed on some insns, depending
10874 on the type of note. */
10877 distribute_notes (notes, from_insn, i3, i2, elim_i2, elim_i1)
10881 rtx elim_i2, elim_i1;
10883 rtx note, next_note;
10886 for (note = notes; note; note = next_note)
10888 rtx place = 0, place2 = 0;
10890 /* If this NOTE references a pseudo register, ensure it references
10891 the latest copy of that register. */
10892 if (XEXP (note, 0) && GET_CODE (XEXP (note, 0)) == REG
10893 && REGNO (XEXP (note, 0)) >= FIRST_PSEUDO_REGISTER)
10894 XEXP (note, 0) = regno_reg_rtx[REGNO (XEXP (note, 0))];
10896 next_note = XEXP (note, 1);
10897 switch (REG_NOTE_KIND (note))
10900 /* Any clobbers for i3 may still exist, and so we must process
10901 REG_UNUSED notes from that insn.
10903 Any clobbers from i2 or i1 can only exist if they were added by
10904 recog_for_combine. In that case, recog_for_combine created the
10905 necessary REG_UNUSED notes. Trying to keep any original
10906 REG_UNUSED notes from these insns can cause incorrect output
10907 if it is for the same register as the original i3 dest.
10908 In that case, we will notice that the register is set in i3,
10909 and then add a REG_UNUSED note for the destination of i3, which
10910 is wrong. However, it is possible to have REG_UNUSED notes from
10911 i2 or i1 for register which were both used and clobbered, so
10912 we keep notes from i2 or i1 if they will turn into REG_DEAD
10915 /* If this register is set or clobbered in I3, put the note there
10916 unless there is one already. */
10917 if (reg_set_p (XEXP (note, 0), PATTERN (i3)))
10919 if (from_insn != i3)
10922 if (! (GET_CODE (XEXP (note, 0)) == REG
10923 ? find_regno_note (i3, REG_UNUSED, REGNO (XEXP (note, 0)))
10924 : find_reg_note (i3, REG_UNUSED, XEXP (note, 0))))
10927 /* Otherwise, if this register is used by I3, then this register
10928 now dies here, so we must put a REG_DEAD note here unless there
10930 else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3))
10931 && ! (GET_CODE (XEXP (note, 0)) == REG
10932 ? find_regno_note (i3, REG_DEAD, REGNO (XEXP (note, 0)))
10933 : find_reg_note (i3, REG_DEAD, XEXP (note, 0))))
10935 PUT_REG_NOTE_KIND (note, REG_DEAD);
10943 /* These notes say something about results of an insn. We can
10944 only support them if they used to be on I3 in which case they
10945 remain on I3. Otherwise they are ignored.
10947 If the note refers to an expression that is not a constant, we
10948 must also ignore the note since we cannot tell whether the
10949 equivalence is still true. It might be possible to do
10950 slightly better than this (we only have a problem if I2DEST
10951 or I1DEST is present in the expression), but it doesn't
10952 seem worth the trouble. */
10954 if (from_insn == i3
10955 && (XEXP (note, 0) == 0 || CONSTANT_P (XEXP (note, 0))))
10960 case REG_NO_CONFLICT:
10962 /* These notes say something about how a register is used. They must
10963 be present on any use of the register in I2 or I3. */
10964 if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3)))
10967 if (i2 && reg_mentioned_p (XEXP (note, 0), PATTERN (i2)))
10977 /* It is too much trouble to try to see if this note is still
10978 correct in all situations. It is better to simply delete it. */
10982 /* If the insn previously containing this note still exists,
10983 put it back where it was. Otherwise move it to the previous
10984 insn. Adjust the corresponding REG_LIBCALL note. */
10985 if (GET_CODE (from_insn) != NOTE)
10989 tem = find_reg_note (XEXP (note, 0), REG_LIBCALL, NULL_RTX);
10990 place = prev_real_insn (from_insn);
10992 XEXP (tem, 0) = place;
10997 /* This is handled similarly to REG_RETVAL. */
10998 if (GET_CODE (from_insn) != NOTE)
11002 tem = find_reg_note (XEXP (note, 0), REG_RETVAL, NULL_RTX);
11003 place = next_real_insn (from_insn);
11005 XEXP (tem, 0) = place;
11010 /* If the register is used as an input in I3, it dies there.
11011 Similarly for I2, if it is non-zero and adjacent to I3.
11013 If the register is not used as an input in either I3 or I2
11014 and it is not one of the registers we were supposed to eliminate,
11015 there are two possibilities. We might have a non-adjacent I2
11016 or we might have somehow eliminated an additional register
11017 from a computation. For example, we might have had A & B where
11018 we discover that B will always be zero. In this case we will
11019 eliminate the reference to A.
11021 In both cases, we must search to see if we can find a previous
11022 use of A and put the death note there. */
11025 && GET_CODE (from_insn) == CALL_INSN
11026 && find_reg_fusage (from_insn, USE, XEXP (note, 0)))
11028 else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3)))
11030 else if (i2 != 0 && next_nonnote_insn (i2) == i3
11031 && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
11034 if (XEXP (note, 0) == elim_i2 || XEXP (note, 0) == elim_i1)
11037 /* If the register is used in both I2 and I3 and it dies in I3,
11038 we might have added another reference to it. If reg_n_refs
11039 was 2, bump it to 3. This has to be correct since the
11040 register must have been set somewhere. The reason this is
11041 done is because local-alloc.c treats 2 references as a
11044 if (place == i3 && i2 != 0 && GET_CODE (XEXP (note, 0)) == REG
11045 && reg_n_refs[REGNO (XEXP (note, 0))]== 2
11046 && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
11047 reg_n_refs[REGNO (XEXP (note, 0))] = 3;
11051 for (tem = prev_nonnote_insn (i3);
11053 && (GET_CODE (tem) == INSN || GET_CODE (tem) == CALL_INSN);
11054 tem = prev_nonnote_insn (tem))
11056 /* If the register is being set at TEM, see if that is all
11057 TEM is doing. If so, delete TEM. Otherwise, make this
11058 into a REG_UNUSED note instead. */
11059 if (reg_set_p (XEXP (note, 0), PATTERN (tem)))
11061 rtx set = single_set (tem);
11063 /* Verify that it was the set, and not a clobber that
11064 modified the register. */
11066 if (set != 0 && ! side_effects_p (SET_SRC (set))
11067 && (rtx_equal_p (XEXP (note, 0), SET_DEST (set))
11068 || (GET_CODE (SET_DEST (set)) == SUBREG
11069 && rtx_equal_p (XEXP (note, 0),
11070 XEXP (SET_DEST (set), 0)))))
11072 /* Move the notes and links of TEM elsewhere.
11073 This might delete other dead insns recursively.
11074 First set the pattern to something that won't use
11077 PATTERN (tem) = pc_rtx;
11079 distribute_notes (REG_NOTES (tem), tem, tem,
11080 NULL_RTX, NULL_RTX, NULL_RTX);
11081 distribute_links (LOG_LINKS (tem));
11083 PUT_CODE (tem, NOTE);
11084 NOTE_LINE_NUMBER (tem) = NOTE_INSN_DELETED;
11085 NOTE_SOURCE_FILE (tem) = 0;
11089 PUT_REG_NOTE_KIND (note, REG_UNUSED);
11091 /* If there isn't already a REG_UNUSED note, put one
11093 if (! find_regno_note (tem, REG_UNUSED,
11094 REGNO (XEXP (note, 0))))
11099 else if (reg_referenced_p (XEXP (note, 0), PATTERN (tem))
11100 || (GET_CODE (tem) == CALL_INSN
11101 && find_reg_fusage (tem, USE, XEXP (note, 0))))
11105 /* If we are doing a 3->2 combination, and we have a
11106 register which formerly died in i3 and was not used
11107 by i2, which now no longer dies in i3 and is used in
11108 i2 but does not die in i2, and place is between i2
11109 and i3, then we may need to move a link from place to
11111 if (i2 && INSN_UID (place) <= max_uid_cuid
11112 && INSN_CUID (place) > INSN_CUID (i2)
11113 && from_insn && INSN_CUID (from_insn) > INSN_CUID (i2)
11114 && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
11116 rtx links = LOG_LINKS (place);
11117 LOG_LINKS (place) = 0;
11118 distribute_links (links);
11124 /* If we haven't found an insn for the death note and it
11125 is still a REG_DEAD note, but we have hit a CODE_LABEL,
11126 insert a USE insn for the register at that label and
11127 put the death node there. This prevents problems with
11128 call-state tracking in caller-save.c. */
11129 if (REG_NOTE_KIND (note) == REG_DEAD && place == 0 && tem != 0)
11132 = emit_insn_after (gen_rtx (USE, VOIDmode, XEXP (note, 0)),
11135 /* If this insn was emitted between blocks, then update
11136 basic_block_head of the current block to include it. */
11137 if (basic_block_end[this_basic_block - 1] == tem)
11138 basic_block_head[this_basic_block] = place;
11142 /* If the register is set or already dead at PLACE, we needn't do
11143 anything with this note if it is still a REG_DEAD note.
11145 Note that we cannot use just `dead_or_set_p' here since we can
11146 convert an assignment to a register into a bit-field assignment.
11147 Therefore, we must also omit the note if the register is the
11148 target of a bitfield assignment. */
11150 if (place && REG_NOTE_KIND (note) == REG_DEAD)
11152 int regno = REGNO (XEXP (note, 0));
11154 if (dead_or_set_p (place, XEXP (note, 0))
11155 || reg_bitfield_target_p (XEXP (note, 0), PATTERN (place)))
11157 /* Unless the register previously died in PLACE, clear
11158 reg_last_death. [I no longer understand why this is
11160 if (reg_last_death[regno] != place)
11161 reg_last_death[regno] = 0;
11165 reg_last_death[regno] = place;
11167 /* If this is a death note for a hard reg that is occupying
11168 multiple registers, ensure that we are still using all
11169 parts of the object. If we find a piece of the object
11170 that is unused, we must add a USE for that piece before
11171 PLACE and put the appropriate REG_DEAD note on it.
11173 An alternative would be to put a REG_UNUSED for the pieces
11174 on the insn that set the register, but that can't be done if
11175 it is not in the same block. It is simpler, though less
11176 efficient, to add the USE insns. */
11178 if (place && regno < FIRST_PSEUDO_REGISTER
11179 && HARD_REGNO_NREGS (regno, GET_MODE (XEXP (note, 0))) > 1)
11182 = regno + HARD_REGNO_NREGS (regno,
11183 GET_MODE (XEXP (note, 0)));
11187 for (i = regno; i < endregno; i++)
11188 if (! refers_to_regno_p (i, i + 1, PATTERN (place), 0)
11189 && ! find_regno_fusage (place, USE, i))
11191 rtx piece = gen_rtx (REG, reg_raw_mode[i], i);
11194 /* See if we already placed a USE note for this
11195 register in front of PLACE. */
11197 GET_CODE (PREV_INSN (p)) == INSN
11198 && GET_CODE (PATTERN (PREV_INSN (p))) == USE;
11200 if (rtx_equal_p (piece,
11201 XEXP (PATTERN (PREV_INSN (p)), 0)))
11210 = emit_insn_before (gen_rtx (USE, VOIDmode,
11213 REG_NOTES (use_insn)
11214 = gen_rtx (EXPR_LIST, REG_DEAD, piece,
11215 REG_NOTES (use_insn));
11221 /* Check for the case where the register dying partially
11222 overlaps the register set by this insn. */
11224 for (i = regno; i < endregno; i++)
11225 if (dead_or_set_regno_p (place, i))
11233 /* Put only REG_DEAD notes for pieces that are
11234 still used and that are not already dead or set. */
11236 for (i = regno; i < endregno; i++)
11238 rtx piece = gen_rtx (REG, reg_raw_mode[i], i);
11240 if ((reg_referenced_p (piece, PATTERN (place))
11241 || (GET_CODE (place) == CALL_INSN
11242 && find_reg_fusage (place, USE, piece)))
11243 && ! dead_or_set_p (place, piece)
11244 && ! reg_bitfield_target_p (piece,
11246 REG_NOTES (place) = gen_rtx (EXPR_LIST, REG_DEAD,
11248 REG_NOTES (place));
11258 /* Any other notes should not be present at this point in the
11265 XEXP (note, 1) = REG_NOTES (place);
11266 REG_NOTES (place) = note;
11268 else if ((REG_NOTE_KIND (note) == REG_DEAD
11269 || REG_NOTE_KIND (note) == REG_UNUSED)
11270 && GET_CODE (XEXP (note, 0)) == REG)
11271 reg_n_deaths[REGNO (XEXP (note, 0))]--;
11275 if ((REG_NOTE_KIND (note) == REG_DEAD
11276 || REG_NOTE_KIND (note) == REG_UNUSED)
11277 && GET_CODE (XEXP (note, 0)) == REG)
11278 reg_n_deaths[REGNO (XEXP (note, 0))]++;
11280 REG_NOTES (place2) = gen_rtx (GET_CODE (note), REG_NOTE_KIND (note),
11281 XEXP (note, 0), REG_NOTES (place2));
11286 /* Similarly to above, distribute the LOG_LINKS that used to be present on
11287 I3, I2, and I1 to new locations. This is also called in one case to
11288 add a link pointing at I3 when I3's destination is changed. */
11291 distribute_links (links)
11294 rtx link, next_link;
11296 for (link = links; link; link = next_link)
11302 next_link = XEXP (link, 1);
11304 /* If the insn that this link points to is a NOTE or isn't a single
11305 set, ignore it. In the latter case, it isn't clear what we
11306 can do other than ignore the link, since we can't tell which
11307 register it was for. Such links wouldn't be used by combine
11310 It is not possible for the destination of the target of the link to
11311 have been changed by combine. The only potential of this is if we
11312 replace I3, I2, and I1 by I3 and I2. But in that case the
11313 destination of I2 also remains unchanged. */
11315 if (GET_CODE (XEXP (link, 0)) == NOTE
11316 || (set = single_set (XEXP (link, 0))) == 0)
11319 reg = SET_DEST (set);
11320 while (GET_CODE (reg) == SUBREG || GET_CODE (reg) == ZERO_EXTRACT
11321 || GET_CODE (reg) == SIGN_EXTRACT
11322 || GET_CODE (reg) == STRICT_LOW_PART)
11323 reg = XEXP (reg, 0);
11325 /* A LOG_LINK is defined as being placed on the first insn that uses
11326 a register and points to the insn that sets the register. Start
11327 searching at the next insn after the target of the link and stop
11328 when we reach a set of the register or the end of the basic block.
11330 Note that this correctly handles the link that used to point from
11331 I3 to I2. Also note that not much searching is typically done here
11332 since most links don't point very far away. */
11334 for (insn = NEXT_INSN (XEXP (link, 0));
11335 (insn && (this_basic_block == n_basic_blocks - 1
11336 || basic_block_head[this_basic_block + 1] != insn));
11337 insn = NEXT_INSN (insn))
11338 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i'
11339 && reg_overlap_mentioned_p (reg, PATTERN (insn)))
11341 if (reg_referenced_p (reg, PATTERN (insn)))
11345 else if (GET_CODE (insn) == CALL_INSN
11346 && find_reg_fusage (insn, USE, reg))
11352 /* If we found a place to put the link, place it there unless there
11353 is already a link to the same insn as LINK at that point. */
11359 for (link2 = LOG_LINKS (place); link2; link2 = XEXP (link2, 1))
11360 if (XEXP (link2, 0) == XEXP (link, 0))
11365 XEXP (link, 1) = LOG_LINKS (place);
11366 LOG_LINKS (place) = link;
11368 /* Set added_links_insn to the earliest insn we added a
11370 if (added_links_insn == 0
11371 || INSN_CUID (added_links_insn) > INSN_CUID (place))
11372 added_links_insn = place;
11378 /* Compute INSN_CUID for INSN, which is an insn made by combine. */
11384 while (insn != 0 && INSN_UID (insn) > max_uid_cuid
11385 && GET_CODE (insn) == INSN && GET_CODE (PATTERN (insn)) == USE)
11386 insn = NEXT_INSN (insn);
11388 if (INSN_UID (insn) > max_uid_cuid)
11391 return INSN_CUID (insn);
11395 dump_combine_stats (file)
11400 ";; Combiner statistics: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n\n",
11401 combine_attempts, combine_merges, combine_extras, combine_successes);
11405 dump_combine_total_stats (file)
11410 "\n;; Combiner totals: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n",
11411 total_attempts, total_merges, total_extras, total_successes);
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