1 /* Optimize by combining instructions for GNU compiler.
2 Copyright (C) 1987, 1988, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003, 2004 Free Software Foundation, Inc.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it under
8 the terms of the GNU General Public License as published by the Free
9 Software Foundation; either version 2, or (at your option) any later
12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING. If not, write to the Free
19 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
22 /* This module is essentially the "combiner" phase of the U. of Arizona
23 Portable Optimizer, but redone to work on our list-structured
24 representation for RTL instead of their string representation.
26 The LOG_LINKS of each insn identify the most recent assignment
27 to each REG used in the insn. It is a list of previous insns,
28 each of which contains a SET for a REG that is used in this insn
29 and not used or set in between. LOG_LINKs never cross basic blocks.
30 They were set up by the preceding pass (lifetime analysis).
32 We try to combine each pair of insns joined by a logical link.
33 We also try to combine triples of insns A, B and C when
34 C has a link back to B and B has a link back to A.
36 LOG_LINKS does not have links for use of the CC0. They don't
37 need to, because the insn that sets the CC0 is always immediately
38 before the insn that tests it. So we always regard a branch
39 insn as having a logical link to the preceding insn. The same is true
40 for an insn explicitly using CC0.
42 We check (with use_crosses_set_p) to avoid combining in such a way
43 as to move a computation to a place where its value would be different.
45 Combination is done by mathematically substituting the previous
46 insn(s) values for the regs they set into the expressions in
47 the later insns that refer to these regs. If the result is a valid insn
48 for our target machine, according to the machine description,
49 we install it, delete the earlier insns, and update the data flow
50 information (LOG_LINKS and REG_NOTES) for what we did.
52 There are a few exceptions where the dataflow information created by
53 flow.c aren't completely updated:
55 - reg_live_length is not updated
56 - a LOG_LINKS entry that refers to an insn with multiple SETs may be
57 removed because there is no way to know which register it was
60 To simplify substitution, we combine only when the earlier insn(s)
61 consist of only a single assignment. To simplify updating afterward,
62 we never combine when a subroutine call appears in the middle.
64 Since we do not represent assignments to CC0 explicitly except when that
65 is all an insn does, there is no LOG_LINKS entry in an insn that uses
66 the condition code for the insn that set the condition code.
67 Fortunately, these two insns must be consecutive.
68 Therefore, every JUMP_INSN is taken to have an implicit logical link
69 to the preceding insn. This is not quite right, since non-jumps can
70 also use the condition code; but in practice such insns would not
75 #include "coretypes.h"
82 #include "hard-reg-set.h"
83 #include "basic-block.h"
84 #include "insn-config.h"
86 /* Include expr.h after insn-config.h so we get HAVE_conditional_move. */
88 #include "insn-attr.h"
93 #include "rtlhooks-def.h"
94 /* Include output.h for dump_file. */
97 /* Number of attempts to combine instructions in this function. */
99 static int combine_attempts;
101 /* Number of attempts that got as far as substitution in this function. */
103 static int combine_merges;
105 /* Number of instructions combined with added SETs in this function. */
107 static int combine_extras;
109 /* Number of instructions combined in this function. */
111 static int combine_successes;
113 /* Totals over entire compilation. */
115 static int total_attempts, total_merges, total_extras, total_successes;
118 /* Vector mapping INSN_UIDs to cuids.
119 The cuids are like uids but increase monotonically always.
120 Combine always uses cuids so that it can compare them.
121 But actually renumbering the uids, which we used to do,
122 proves to be a bad idea because it makes it hard to compare
123 the dumps produced by earlier passes with those from later passes. */
125 static int *uid_cuid;
126 static int max_uid_cuid;
128 /* Get the cuid of an insn. */
130 #define INSN_CUID(INSN) \
131 (INSN_UID (INSN) > max_uid_cuid ? insn_cuid (INSN) : uid_cuid[INSN_UID (INSN)])
133 /* In case BITS_PER_WORD == HOST_BITS_PER_WIDE_INT, shifting by
134 BITS_PER_WORD would invoke undefined behavior. Work around it. */
136 #define UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD(val) \
137 (((unsigned HOST_WIDE_INT) (val) << (BITS_PER_WORD - 1)) << 1)
139 /* Maximum register number, which is the size of the tables below. */
141 static unsigned int combine_max_regno;
144 /* Record last point of death of (hard or pseudo) register n. */
147 /* Record last point of modification of (hard or pseudo) register n. */
150 /* The next group of fields allows the recording of the last value assigned
151 to (hard or pseudo) register n. We use this information to see if an
152 operation being processed is redundant given a prior operation performed
153 on the register. For example, an `and' with a constant is redundant if
154 all the zero bits are already known to be turned off.
156 We use an approach similar to that used by cse, but change it in the
159 (1) We do not want to reinitialize at each label.
160 (2) It is useful, but not critical, to know the actual value assigned
161 to a register. Often just its form is helpful.
163 Therefore, we maintain the following fields:
165 last_set_value the last value assigned
166 last_set_label records the value of label_tick when the
167 register was assigned
168 last_set_table_tick records the value of label_tick when a
169 value using the register is assigned
170 last_set_invalid set to nonzero when it is not valid
171 to use the value of this register in some
174 To understand the usage of these tables, it is important to understand
175 the distinction between the value in last_set_value being valid and
176 the register being validly contained in some other expression in the
179 (The next two parameters are out of date).
181 reg_stat[i].last_set_value is valid if it is nonzero, and either
182 reg_n_sets[i] is 1 or reg_stat[i].last_set_label == label_tick.
184 Register I may validly appear in any expression returned for the value
185 of another register if reg_n_sets[i] is 1. It may also appear in the
186 value for register J if reg_stat[j].last_set_invalid is zero, or
187 reg_stat[i].last_set_label < reg_stat[j].last_set_label.
189 If an expression is found in the table containing a register which may
190 not validly appear in an expression, the register is replaced by
191 something that won't match, (clobber (const_int 0)). */
193 /* Record last value assigned to (hard or pseudo) register n. */
197 /* Record the value of label_tick when an expression involving register n
198 is placed in last_set_value. */
200 int last_set_table_tick;
202 /* Record the value of label_tick when the value for register n is placed in
207 /* These fields are maintained in parallel with last_set_value and are
208 used to store the mode in which the register was last set, the bits
209 that were known to be zero when it was last set, and the number of
210 sign bits copies it was known to have when it was last set. */
212 unsigned HOST_WIDE_INT last_set_nonzero_bits;
213 char last_set_sign_bit_copies;
214 ENUM_BITFIELD(machine_mode) last_set_mode : 8;
216 /* Set nonzero if references to register n in expressions should not be
217 used. last_set_invalid is set nonzero when this register is being
218 assigned to and last_set_table_tick == label_tick. */
220 char last_set_invalid;
222 /* Some registers that are set more than once and used in more than one
223 basic block are nevertheless always set in similar ways. For example,
224 a QImode register may be loaded from memory in two places on a machine
225 where byte loads zero extend.
227 We record in the following fields if a register has some leading bits
228 that are always equal to the sign bit, and what we know about the
229 nonzero bits of a register, specifically which bits are known to be
232 If an entry is zero, it means that we don't know anything special. */
234 unsigned char sign_bit_copies;
236 unsigned HOST_WIDE_INT nonzero_bits;
239 static struct reg_stat *reg_stat;
241 /* Record the cuid of the last insn that invalidated memory
242 (anything that writes memory, and subroutine calls, but not pushes). */
244 static int mem_last_set;
246 /* Record the cuid of the last CALL_INSN
247 so we can tell whether a potential combination crosses any calls. */
249 static int last_call_cuid;
251 /* When `subst' is called, this is the insn that is being modified
252 (by combining in a previous insn). The PATTERN of this insn
253 is still the old pattern partially modified and it should not be
254 looked at, but this may be used to examine the successors of the insn
255 to judge whether a simplification is valid. */
257 static rtx subst_insn;
259 /* This is the lowest CUID that `subst' is currently dealing with.
260 get_last_value will not return a value if the register was set at or
261 after this CUID. If not for this mechanism, we could get confused if
262 I2 or I1 in try_combine were an insn that used the old value of a register
263 to obtain a new value. In that case, we might erroneously get the
264 new value of the register when we wanted the old one. */
266 static int subst_low_cuid;
268 /* This contains any hard registers that are used in newpat; reg_dead_at_p
269 must consider all these registers to be always live. */
271 static HARD_REG_SET newpat_used_regs;
273 /* This is an insn to which a LOG_LINKS entry has been added. If this
274 insn is the earlier than I2 or I3, combine should rescan starting at
277 static rtx added_links_insn;
279 /* Basic block in which we are performing combines. */
280 static basic_block this_basic_block;
282 /* A bitmap indicating which blocks had registers go dead at entry.
283 After combine, we'll need to re-do global life analysis with
284 those blocks as starting points. */
285 static sbitmap refresh_blocks;
287 /* The following array records the insn_rtx_cost for every insn
288 in the instruction stream. */
290 static int *uid_insn_cost;
292 /* Length of the currently allocated uid_insn_cost array. */
294 static int last_insn_cost;
296 /* Incremented for each label. */
298 static int label_tick;
300 /* Mode used to compute significance in reg_stat[].nonzero_bits. It is the
301 largest integer mode that can fit in HOST_BITS_PER_WIDE_INT. */
303 static enum machine_mode nonzero_bits_mode;
305 /* Nonzero when reg_stat[].nonzero_bits and reg_stat[].sign_bit_copies can
306 be safely used. It is zero while computing them and after combine has
307 completed. This former test prevents propagating values based on
308 previously set values, which can be incorrect if a variable is modified
311 static int nonzero_sign_valid;
314 /* Record one modification to rtl structure
315 to be undone by storing old_contents into *where.
316 is_int is 1 if the contents are an int. */
322 union {rtx r; int i;} old_contents;
323 union {rtx *r; int *i;} where;
326 /* Record a bunch of changes to be undone, up to MAX_UNDO of them.
327 num_undo says how many are currently recorded.
329 other_insn is nonzero if we have modified some other insn in the process
330 of working on subst_insn. It must be verified too. */
339 static struct undobuf undobuf;
341 /* Number of times the pseudo being substituted for
342 was found and replaced. */
344 static int n_occurrences;
346 static rtx reg_nonzero_bits_for_combine (rtx, enum machine_mode, rtx,
348 unsigned HOST_WIDE_INT,
349 unsigned HOST_WIDE_INT *);
350 static rtx reg_num_sign_bit_copies_for_combine (rtx, enum machine_mode, rtx,
352 unsigned int, unsigned int *);
353 static void do_SUBST (rtx *, rtx);
354 static void do_SUBST_INT (int *, int);
355 static void init_reg_last (void);
356 static void setup_incoming_promotions (void);
357 static void set_nonzero_bits_and_sign_copies (rtx, rtx, void *);
358 static int cant_combine_insn_p (rtx);
359 static int can_combine_p (rtx, rtx, rtx, rtx, rtx *, rtx *);
360 static int combinable_i3pat (rtx, rtx *, rtx, rtx, int, rtx *);
361 static int contains_muldiv (rtx);
362 static rtx try_combine (rtx, rtx, rtx, int *);
363 static void undo_all (void);
364 static void undo_commit (void);
365 static rtx *find_split_point (rtx *, rtx);
366 static rtx subst (rtx, rtx, rtx, int, int);
367 static rtx combine_simplify_rtx (rtx, enum machine_mode, int);
368 static rtx simplify_if_then_else (rtx);
369 static rtx simplify_set (rtx);
370 static rtx simplify_logical (rtx);
371 static rtx expand_compound_operation (rtx);
372 static rtx expand_field_assignment (rtx);
373 static rtx make_extraction (enum machine_mode, rtx, HOST_WIDE_INT,
374 rtx, unsigned HOST_WIDE_INT, int, int, int);
375 static rtx extract_left_shift (rtx, int);
376 static rtx make_compound_operation (rtx, enum rtx_code);
377 static int get_pos_from_mask (unsigned HOST_WIDE_INT,
378 unsigned HOST_WIDE_INT *);
379 static rtx force_to_mode (rtx, enum machine_mode,
380 unsigned HOST_WIDE_INT, rtx, int);
381 static rtx if_then_else_cond (rtx, rtx *, rtx *);
382 static rtx known_cond (rtx, enum rtx_code, rtx, rtx);
383 static int rtx_equal_for_field_assignment_p (rtx, rtx);
384 static rtx make_field_assignment (rtx);
385 static rtx apply_distributive_law (rtx);
386 static rtx simplify_and_const_int (rtx, enum machine_mode, rtx,
387 unsigned HOST_WIDE_INT);
388 static int merge_outer_ops (enum rtx_code *, HOST_WIDE_INT *, enum rtx_code,
389 HOST_WIDE_INT, enum machine_mode, int *);
390 static rtx simplify_shift_const (rtx, enum rtx_code, enum machine_mode, rtx,
392 static int recog_for_combine (rtx *, rtx, rtx *);
393 static rtx gen_lowpart_for_combine (enum machine_mode, rtx);
394 static rtx gen_binary (enum rtx_code, enum machine_mode, rtx, rtx);
395 static enum rtx_code simplify_comparison (enum rtx_code, rtx *, rtx *);
396 static void update_table_tick (rtx);
397 static void record_value_for_reg (rtx, rtx, rtx);
398 static void check_promoted_subreg (rtx, rtx);
399 static void record_dead_and_set_regs_1 (rtx, rtx, void *);
400 static void record_dead_and_set_regs (rtx);
401 static int get_last_value_validate (rtx *, rtx, int, int);
402 static rtx get_last_value (rtx);
403 static int use_crosses_set_p (rtx, int);
404 static void reg_dead_at_p_1 (rtx, rtx, void *);
405 static int reg_dead_at_p (rtx, rtx);
406 static void move_deaths (rtx, rtx, int, rtx, rtx *);
407 static int reg_bitfield_target_p (rtx, rtx);
408 static void distribute_notes (rtx, rtx, rtx, rtx);
409 static void distribute_links (rtx);
410 static void mark_used_regs_combine (rtx);
411 static int insn_cuid (rtx);
412 static void record_promoted_value (rtx, rtx);
413 static rtx reversed_comparison (rtx, enum machine_mode, rtx, rtx);
414 static enum rtx_code combine_reversed_comparison_code (rtx);
415 static int unmentioned_reg_p_1 (rtx *, void *);
416 static bool unmentioned_reg_p (rtx, rtx);
419 /* It is not safe to use ordinary gen_lowpart in combine.
420 See comments in gen_lowpart_for_combine. */
421 #undef RTL_HOOKS_GEN_LOWPART
422 #define RTL_HOOKS_GEN_LOWPART gen_lowpart_for_combine
424 #undef RTL_HOOKS_REG_NONZERO_REG_BITS
425 #define RTL_HOOKS_REG_NONZERO_REG_BITS reg_nonzero_bits_for_combine
427 #undef RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES
428 #define RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES reg_num_sign_bit_copies_for_combine
430 static const struct rtl_hooks combine_rtl_hooks = RTL_HOOKS_INITIALIZER;
433 /* Substitute NEWVAL, an rtx expression, into INTO, a place in some
434 insn. The substitution can be undone by undo_all. If INTO is already
435 set to NEWVAL, do not record this change. Because computing NEWVAL might
436 also call SUBST, we have to compute it before we put anything into
440 do_SUBST (rtx *into, rtx newval)
445 if (oldval == newval)
448 /* We'd like to catch as many invalid transformations here as
449 possible. Unfortunately, there are way too many mode changes
450 that are perfectly valid, so we'd waste too much effort for
451 little gain doing the checks here. Focus on catching invalid
452 transformations involving integer constants. */
453 if (GET_MODE_CLASS (GET_MODE (oldval)) == MODE_INT
454 && GET_CODE (newval) == CONST_INT)
456 /* Sanity check that we're replacing oldval with a CONST_INT
457 that is a valid sign-extension for the original mode. */
458 if (INTVAL (newval) != trunc_int_for_mode (INTVAL (newval),
462 /* Replacing the operand of a SUBREG or a ZERO_EXTEND with a
463 CONST_INT is not valid, because after the replacement, the
464 original mode would be gone. Unfortunately, we can't tell
465 when do_SUBST is called to replace the operand thereof, so we
466 perform this test on oldval instead, checking whether an
467 invalid replacement took place before we got here. */
468 if ((GET_CODE (oldval) == SUBREG
469 && GET_CODE (SUBREG_REG (oldval)) == CONST_INT)
470 || (GET_CODE (oldval) == ZERO_EXTEND
471 && GET_CODE (XEXP (oldval, 0)) == CONST_INT))
476 buf = undobuf.frees, undobuf.frees = buf->next;
478 buf = xmalloc (sizeof (struct undo));
482 buf->old_contents.r = oldval;
485 buf->next = undobuf.undos, undobuf.undos = buf;
488 #define SUBST(INTO, NEWVAL) do_SUBST(&(INTO), (NEWVAL))
490 /* Similar to SUBST, but NEWVAL is an int expression. Note that substitution
491 for the value of a HOST_WIDE_INT value (including CONST_INT) is
495 do_SUBST_INT (int *into, int newval)
500 if (oldval == newval)
504 buf = undobuf.frees, undobuf.frees = buf->next;
506 buf = xmalloc (sizeof (struct undo));
510 buf->old_contents.i = oldval;
513 buf->next = undobuf.undos, undobuf.undos = buf;
516 #define SUBST_INT(INTO, NEWVAL) do_SUBST_INT(&(INTO), (NEWVAL))
518 /* Subroutine of try_combine. Determine whether the combine replacement
519 patterns NEWPAT and NEWI2PAT are cheaper according to insn_rtx_cost
520 that the original instruction sequence I1, I2 and I3. Note that I1
521 and/or NEWI2PAT may be NULL_RTX. This function returns false, if the
522 costs of all instructions can be estimated, and the replacements are
523 more expensive than the original sequence. */
526 combine_validate_cost (rtx i1, rtx i2, rtx i3, rtx newpat, rtx newi2pat)
528 int i1_cost, i2_cost, i3_cost;
529 int new_i2_cost, new_i3_cost;
530 int old_cost, new_cost;
532 /* Lookup the original insn_rtx_costs. */
533 i2_cost = INSN_UID (i2) <= last_insn_cost
534 ? uid_insn_cost[INSN_UID (i2)] : 0;
535 i3_cost = INSN_UID (i3) <= last_insn_cost
536 ? uid_insn_cost[INSN_UID (i3)] : 0;
540 i1_cost = INSN_UID (i1) <= last_insn_cost
541 ? uid_insn_cost[INSN_UID (i1)] : 0;
542 old_cost = (i1_cost > 0 && i2_cost > 0 && i3_cost > 0)
543 ? i1_cost + i2_cost + i3_cost : 0;
547 old_cost = (i2_cost > 0 && i3_cost > 0) ? i2_cost + i3_cost : 0;
551 /* Calculate the replacement insn_rtx_costs. */
552 new_i3_cost = insn_rtx_cost (newpat);
555 new_i2_cost = insn_rtx_cost (newi2pat);
556 new_cost = (new_i2_cost > 0 && new_i3_cost > 0)
557 ? new_i2_cost + new_i3_cost : 0;
561 new_cost = new_i3_cost;
565 /* Disallow this recombination if both new_cost and old_cost are
566 greater than zero, and new_cost is greater than old cost. */
567 if (!undobuf.other_insn
569 && new_cost > old_cost)
576 "rejecting combination of insns %d, %d and %d\n",
577 INSN_UID (i1), INSN_UID (i2), INSN_UID (i3));
578 fprintf (dump_file, "original costs %d + %d + %d = %d\n",
579 i1_cost, i2_cost, i3_cost, old_cost);
584 "rejecting combination of insns %d and %d\n",
585 INSN_UID (i2), INSN_UID (i3));
586 fprintf (dump_file, "original costs %d + %d = %d\n",
587 i2_cost, i3_cost, old_cost);
592 fprintf (dump_file, "replacement costs %d + %d = %d\n",
593 new_i2_cost, new_i3_cost, new_cost);
596 fprintf (dump_file, "replacement cost %d\n", new_cost);
602 /* Update the uid_insn_cost array with the replacement costs. */
603 uid_insn_cost[INSN_UID (i2)] = new_i2_cost;
604 uid_insn_cost[INSN_UID (i3)] = new_i3_cost;
606 uid_insn_cost[INSN_UID (i1)] = 0;
611 /* Main entry point for combiner. F is the first insn of the function.
612 NREGS is the first unused pseudo-reg number.
614 Return nonzero if the combiner has turned an indirect jump
615 instruction into a direct jump. */
617 combine_instructions (rtx f, unsigned int nregs)
624 rtx links, nextlinks;
626 int new_direct_jump_p = 0;
628 combine_attempts = 0;
631 combine_successes = 0;
633 combine_max_regno = nregs;
635 rtl_hooks = combine_rtl_hooks;
637 reg_stat = xcalloc (nregs, sizeof (struct reg_stat));
639 init_recog_no_volatile ();
641 /* Compute maximum uid value so uid_cuid can be allocated. */
643 for (insn = f, i = 0; insn; insn = NEXT_INSN (insn))
644 if (INSN_UID (insn) > i)
647 uid_cuid = xmalloc ((i + 1) * sizeof (int));
650 nonzero_bits_mode = mode_for_size (HOST_BITS_PER_WIDE_INT, MODE_INT, 0);
652 /* Don't use reg_stat[].nonzero_bits when computing it. This can cause
653 problems when, for example, we have j <<= 1 in a loop. */
655 nonzero_sign_valid = 0;
657 /* Compute the mapping from uids to cuids.
658 Cuids are numbers assigned to insns, like uids,
659 except that cuids increase monotonically through the code.
661 Scan all SETs and see if we can deduce anything about what
662 bits are known to be zero for some registers and how many copies
663 of the sign bit are known to exist for those registers.
665 Also set any known values so that we can use it while searching
666 for what bits are known to be set. */
670 setup_incoming_promotions ();
672 refresh_blocks = sbitmap_alloc (last_basic_block);
673 sbitmap_zero (refresh_blocks);
675 /* Allocate array of current insn_rtx_costs. */
676 uid_insn_cost = xcalloc (max_uid_cuid + 1, sizeof (int));
677 last_insn_cost = max_uid_cuid;
679 for (insn = f, i = 0; insn; insn = NEXT_INSN (insn))
681 uid_cuid[INSN_UID (insn)] = ++i;
687 note_stores (PATTERN (insn), set_nonzero_bits_and_sign_copies,
689 record_dead_and_set_regs (insn);
692 for (links = REG_NOTES (insn); links; links = XEXP (links, 1))
693 if (REG_NOTE_KIND (links) == REG_INC)
694 set_nonzero_bits_and_sign_copies (XEXP (links, 0), NULL_RTX,
698 /* Record the current insn_rtx_cost of this instruction. */
699 if (NONJUMP_INSN_P (insn))
700 uid_insn_cost[INSN_UID (insn)] = insn_rtx_cost (PATTERN (insn));
702 fprintf(dump_file, "insn_cost %d: %d\n",
703 INSN_UID (insn), uid_insn_cost[INSN_UID (insn)]);
710 nonzero_sign_valid = 1;
712 /* Now scan all the insns in forward order. */
718 setup_incoming_promotions ();
720 FOR_EACH_BB (this_basic_block)
722 for (insn = BB_HEAD (this_basic_block);
723 insn != NEXT_INSN (BB_END (this_basic_block));
724 insn = next ? next : NEXT_INSN (insn))
731 else if (INSN_P (insn))
733 /* See if we know about function return values before this
734 insn based upon SUBREG flags. */
735 check_promoted_subreg (insn, PATTERN (insn));
737 /* Try this insn with each insn it links back to. */
739 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
740 if ((next = try_combine (insn, XEXP (links, 0),
741 NULL_RTX, &new_direct_jump_p)) != 0)
744 /* Try each sequence of three linked insns ending with this one. */
746 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
748 rtx link = XEXP (links, 0);
750 /* If the linked insn has been replaced by a note, then there
751 is no point in pursuing this chain any further. */
755 for (nextlinks = LOG_LINKS (link);
757 nextlinks = XEXP (nextlinks, 1))
758 if ((next = try_combine (insn, link,
760 &new_direct_jump_p)) != 0)
765 /* Try to combine a jump insn that uses CC0
766 with a preceding insn that sets CC0, and maybe with its
767 logical predecessor as well.
768 This is how we make decrement-and-branch insns.
769 We need this special code because data flow connections
770 via CC0 do not get entered in LOG_LINKS. */
773 && (prev = prev_nonnote_insn (insn)) != 0
774 && NONJUMP_INSN_P (prev)
775 && sets_cc0_p (PATTERN (prev)))
777 if ((next = try_combine (insn, prev,
778 NULL_RTX, &new_direct_jump_p)) != 0)
781 for (nextlinks = LOG_LINKS (prev); nextlinks;
782 nextlinks = XEXP (nextlinks, 1))
783 if ((next = try_combine (insn, prev,
785 &new_direct_jump_p)) != 0)
789 /* Do the same for an insn that explicitly references CC0. */
790 if (NONJUMP_INSN_P (insn)
791 && (prev = prev_nonnote_insn (insn)) != 0
792 && NONJUMP_INSN_P (prev)
793 && sets_cc0_p (PATTERN (prev))
794 && GET_CODE (PATTERN (insn)) == SET
795 && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (insn))))
797 if ((next = try_combine (insn, prev,
798 NULL_RTX, &new_direct_jump_p)) != 0)
801 for (nextlinks = LOG_LINKS (prev); nextlinks;
802 nextlinks = XEXP (nextlinks, 1))
803 if ((next = try_combine (insn, prev,
805 &new_direct_jump_p)) != 0)
809 /* Finally, see if any of the insns that this insn links to
810 explicitly references CC0. If so, try this insn, that insn,
811 and its predecessor if it sets CC0. */
812 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
813 if (NONJUMP_INSN_P (XEXP (links, 0))
814 && GET_CODE (PATTERN (XEXP (links, 0))) == SET
815 && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (XEXP (links, 0))))
816 && (prev = prev_nonnote_insn (XEXP (links, 0))) != 0
817 && NONJUMP_INSN_P (prev)
818 && sets_cc0_p (PATTERN (prev))
819 && (next = try_combine (insn, XEXP (links, 0),
820 prev, &new_direct_jump_p)) != 0)
824 /* Try combining an insn with two different insns whose results it
826 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
827 for (nextlinks = XEXP (links, 1); nextlinks;
828 nextlinks = XEXP (nextlinks, 1))
829 if ((next = try_combine (insn, XEXP (links, 0),
831 &new_direct_jump_p)) != 0)
834 /* Try this insn with each REG_EQUAL note it links back to. */
835 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
838 rtx temp = XEXP (links, 0);
839 if ((set = single_set (temp)) != 0
840 && (note = find_reg_equal_equiv_note (temp)) != 0
841 && GET_CODE (XEXP (note, 0)) != EXPR_LIST
842 /* Avoid using a register that may already been marked
843 dead by an earlier instruction. */
844 && ! unmentioned_reg_p (XEXP (note, 0), SET_SRC (set)))
846 /* Temporarily replace the set's source with the
847 contents of the REG_EQUAL note. The insn will
848 be deleted or recognized by try_combine. */
849 rtx orig = SET_SRC (set);
850 SET_SRC (set) = XEXP (note, 0);
851 next = try_combine (insn, temp, NULL_RTX,
855 SET_SRC (set) = orig;
860 record_dead_and_set_regs (insn);
869 EXECUTE_IF_SET_IN_SBITMAP (refresh_blocks, 0, i,
870 BASIC_BLOCK (i)->flags |= BB_DIRTY);
871 new_direct_jump_p |= purge_all_dead_edges (0);
872 delete_noop_moves ();
874 update_life_info_in_dirty_blocks (UPDATE_LIFE_GLOBAL_RM_NOTES,
875 PROP_DEATH_NOTES | PROP_SCAN_DEAD_CODE
876 | PROP_KILL_DEAD_CODE);
879 sbitmap_free (refresh_blocks);
880 free (uid_insn_cost);
885 struct undo *undo, *next;
886 for (undo = undobuf.frees; undo; undo = next)
894 total_attempts += combine_attempts;
895 total_merges += combine_merges;
896 total_extras += combine_extras;
897 total_successes += combine_successes;
899 nonzero_sign_valid = 0;
900 rtl_hooks = general_rtl_hooks;
902 /* Make recognizer allow volatile MEMs again. */
905 return new_direct_jump_p;
908 /* Wipe the last_xxx fields of reg_stat in preparation for another pass. */
914 for (i = 0; i < combine_max_regno; i++)
915 memset (reg_stat + i, 0, offsetof (struct reg_stat, sign_bit_copies));
918 /* Set up any promoted values for incoming argument registers. */
921 setup_incoming_promotions (void)
925 enum machine_mode mode;
927 rtx first = get_insns ();
929 if (targetm.calls.promote_function_args (TREE_TYPE (cfun->decl)))
931 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
932 /* Check whether this register can hold an incoming pointer
933 argument. FUNCTION_ARG_REGNO_P tests outgoing register
934 numbers, so translate if necessary due to register windows. */
935 if (FUNCTION_ARG_REGNO_P (OUTGOING_REGNO (regno))
936 && (reg = promoted_input_arg (regno, &mode, &unsignedp)) != 0)
939 (reg, first, gen_rtx_fmt_e ((unsignedp ? ZERO_EXTEND
942 gen_rtx_CLOBBER (mode, const0_rtx)));
947 /* Called via note_stores. If X is a pseudo that is narrower than
948 HOST_BITS_PER_WIDE_INT and is being set, record what bits are known zero.
950 If we are setting only a portion of X and we can't figure out what
951 portion, assume all bits will be used since we don't know what will
954 Similarly, set how many bits of X are known to be copies of the sign bit
955 at all locations in the function. This is the smallest number implied
959 set_nonzero_bits_and_sign_copies (rtx x, rtx set,
960 void *data ATTRIBUTE_UNUSED)
965 && REGNO (x) >= FIRST_PSEUDO_REGISTER
966 /* If this register is undefined at the start of the file, we can't
967 say what its contents were. */
968 && ! REGNO_REG_SET_P (ENTRY_BLOCK_PTR->next_bb->global_live_at_start, REGNO (x))
969 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT)
971 if (set == 0 || GET_CODE (set) == CLOBBER)
973 reg_stat[REGNO (x)].nonzero_bits = GET_MODE_MASK (GET_MODE (x));
974 reg_stat[REGNO (x)].sign_bit_copies = 1;
978 /* If this is a complex assignment, see if we can convert it into a
979 simple assignment. */
980 set = expand_field_assignment (set);
982 /* If this is a simple assignment, or we have a paradoxical SUBREG,
983 set what we know about X. */
985 if (SET_DEST (set) == x
986 || (GET_CODE (SET_DEST (set)) == SUBREG
987 && (GET_MODE_SIZE (GET_MODE (SET_DEST (set)))
988 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (set)))))
989 && SUBREG_REG (SET_DEST (set)) == x))
991 rtx src = SET_SRC (set);
993 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
994 /* If X is narrower than a word and SRC is a non-negative
995 constant that would appear negative in the mode of X,
996 sign-extend it for use in reg_stat[].nonzero_bits because some
997 machines (maybe most) will actually do the sign-extension
998 and this is the conservative approach.
1000 ??? For 2.5, try to tighten up the MD files in this regard
1001 instead of this kludge. */
1003 if (GET_MODE_BITSIZE (GET_MODE (x)) < BITS_PER_WORD
1004 && GET_CODE (src) == CONST_INT
1006 && 0 != (INTVAL (src)
1007 & ((HOST_WIDE_INT) 1
1008 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
1009 src = GEN_INT (INTVAL (src)
1010 | ((HOST_WIDE_INT) (-1)
1011 << GET_MODE_BITSIZE (GET_MODE (x))));
1014 /* Don't call nonzero_bits if it cannot change anything. */
1015 if (reg_stat[REGNO (x)].nonzero_bits != ~(unsigned HOST_WIDE_INT) 0)
1016 reg_stat[REGNO (x)].nonzero_bits
1017 |= nonzero_bits (src, nonzero_bits_mode);
1018 num = num_sign_bit_copies (SET_SRC (set), GET_MODE (x));
1019 if (reg_stat[REGNO (x)].sign_bit_copies == 0
1020 || reg_stat[REGNO (x)].sign_bit_copies > num)
1021 reg_stat[REGNO (x)].sign_bit_copies = num;
1025 reg_stat[REGNO (x)].nonzero_bits = GET_MODE_MASK (GET_MODE (x));
1026 reg_stat[REGNO (x)].sign_bit_copies = 1;
1031 /* See if INSN can be combined into I3. PRED and SUCC are optionally
1032 insns that were previously combined into I3 or that will be combined
1033 into the merger of INSN and I3.
1035 Return 0 if the combination is not allowed for any reason.
1037 If the combination is allowed, *PDEST will be set to the single
1038 destination of INSN and *PSRC to the single source, and this function
1042 can_combine_p (rtx insn, rtx i3, rtx pred ATTRIBUTE_UNUSED, rtx succ,
1043 rtx *pdest, rtx *psrc)
1046 rtx set = 0, src, dest;
1051 int all_adjacent = (succ ? (next_active_insn (insn) == succ
1052 && next_active_insn (succ) == i3)
1053 : next_active_insn (insn) == i3);
1055 /* Can combine only if previous insn is a SET of a REG, a SUBREG or CC0.
1056 or a PARALLEL consisting of such a SET and CLOBBERs.
1058 If INSN has CLOBBER parallel parts, ignore them for our processing.
1059 By definition, these happen during the execution of the insn. When it
1060 is merged with another insn, all bets are off. If they are, in fact,
1061 needed and aren't also supplied in I3, they may be added by
1062 recog_for_combine. Otherwise, it won't match.
1064 We can also ignore a SET whose SET_DEST is mentioned in a REG_UNUSED
1067 Get the source and destination of INSN. If more than one, can't
1070 if (GET_CODE (PATTERN (insn)) == SET)
1071 set = PATTERN (insn);
1072 else if (GET_CODE (PATTERN (insn)) == PARALLEL
1073 && GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == SET)
1075 for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
1077 rtx elt = XVECEXP (PATTERN (insn), 0, i);
1080 switch (GET_CODE (elt))
1082 /* This is important to combine floating point insns
1083 for the SH4 port. */
1085 /* Combining an isolated USE doesn't make sense.
1086 We depend here on combinable_i3pat to reject them. */
1087 /* The code below this loop only verifies that the inputs of
1088 the SET in INSN do not change. We call reg_set_between_p
1089 to verify that the REG in the USE does not change between
1091 If the USE in INSN was for a pseudo register, the matching
1092 insn pattern will likely match any register; combining this
1093 with any other USE would only be safe if we knew that the
1094 used registers have identical values, or if there was
1095 something to tell them apart, e.g. different modes. For
1096 now, we forgo such complicated tests and simply disallow
1097 combining of USES of pseudo registers with any other USE. */
1098 if (REG_P (XEXP (elt, 0))
1099 && GET_CODE (PATTERN (i3)) == PARALLEL)
1101 rtx i3pat = PATTERN (i3);
1102 int i = XVECLEN (i3pat, 0) - 1;
1103 unsigned int regno = REGNO (XEXP (elt, 0));
1107 rtx i3elt = XVECEXP (i3pat, 0, i);
1109 if (GET_CODE (i3elt) == USE
1110 && REG_P (XEXP (i3elt, 0))
1111 && (REGNO (XEXP (i3elt, 0)) == regno
1112 ? reg_set_between_p (XEXP (elt, 0),
1113 PREV_INSN (insn), i3)
1114 : regno >= FIRST_PSEUDO_REGISTER))
1121 /* We can ignore CLOBBERs. */
1126 /* Ignore SETs whose result isn't used but not those that
1127 have side-effects. */
1128 if (find_reg_note (insn, REG_UNUSED, SET_DEST (elt))
1129 && (!(note = find_reg_note (insn, REG_EH_REGION, NULL_RTX))
1130 || INTVAL (XEXP (note, 0)) <= 0)
1131 && ! side_effects_p (elt))
1134 /* If we have already found a SET, this is a second one and
1135 so we cannot combine with this insn. */
1143 /* Anything else means we can't combine. */
1149 /* If SET_SRC is an ASM_OPERANDS we can't throw away these CLOBBERs,
1150 so don't do anything with it. */
1151 || GET_CODE (SET_SRC (set)) == ASM_OPERANDS)
1160 set = expand_field_assignment (set);
1161 src = SET_SRC (set), dest = SET_DEST (set);
1163 /* Don't eliminate a store in the stack pointer. */
1164 if (dest == stack_pointer_rtx
1165 /* Don't combine with an insn that sets a register to itself if it has
1166 a REG_EQUAL note. This may be part of a REG_NO_CONFLICT sequence. */
1167 || (rtx_equal_p (src, dest) && find_reg_note (insn, REG_EQUAL, NULL_RTX))
1168 /* Can't merge an ASM_OPERANDS. */
1169 || GET_CODE (src) == ASM_OPERANDS
1170 /* Can't merge a function call. */
1171 || GET_CODE (src) == CALL
1172 /* Don't eliminate a function call argument. */
1174 && (find_reg_fusage (i3, USE, dest)
1176 && REGNO (dest) < FIRST_PSEUDO_REGISTER
1177 && global_regs[REGNO (dest)])))
1178 /* Don't substitute into an incremented register. */
1179 || FIND_REG_INC_NOTE (i3, dest)
1180 || (succ && FIND_REG_INC_NOTE (succ, dest))
1182 /* Don't combine the end of a libcall into anything. */
1183 /* ??? This gives worse code, and appears to be unnecessary, since no
1184 pass after flow uses REG_LIBCALL/REG_RETVAL notes. Local-alloc does
1185 use REG_RETVAL notes for noconflict blocks, but other code here
1186 makes sure that those insns don't disappear. */
1187 || find_reg_note (insn, REG_RETVAL, NULL_RTX)
1189 /* Make sure that DEST is not used after SUCC but before I3. */
1190 || (succ && ! all_adjacent
1191 && reg_used_between_p (dest, succ, i3))
1192 /* Make sure that the value that is to be substituted for the register
1193 does not use any registers whose values alter in between. However,
1194 If the insns are adjacent, a use can't cross a set even though we
1195 think it might (this can happen for a sequence of insns each setting
1196 the same destination; last_set of that register might point to
1197 a NOTE). If INSN has a REG_EQUIV note, the register is always
1198 equivalent to the memory so the substitution is valid even if there
1199 are intervening stores. Also, don't move a volatile asm or
1200 UNSPEC_VOLATILE across any other insns. */
1203 || ! find_reg_note (insn, REG_EQUIV, src))
1204 && use_crosses_set_p (src, INSN_CUID (insn)))
1205 || (GET_CODE (src) == ASM_OPERANDS && MEM_VOLATILE_P (src))
1206 || GET_CODE (src) == UNSPEC_VOLATILE))
1207 /* If there is a REG_NO_CONFLICT note for DEST in I3 or SUCC, we get
1208 better register allocation by not doing the combine. */
1209 || find_reg_note (i3, REG_NO_CONFLICT, dest)
1210 || (succ && find_reg_note (succ, REG_NO_CONFLICT, dest))
1211 /* Don't combine across a CALL_INSN, because that would possibly
1212 change whether the life span of some REGs crosses calls or not,
1213 and it is a pain to update that information.
1214 Exception: if source is a constant, moving it later can't hurt.
1215 Accept that special case, because it helps -fforce-addr a lot. */
1216 || (INSN_CUID (insn) < last_call_cuid && ! CONSTANT_P (src)))
1219 /* DEST must either be a REG or CC0. */
1222 /* If register alignment is being enforced for multi-word items in all
1223 cases except for parameters, it is possible to have a register copy
1224 insn referencing a hard register that is not allowed to contain the
1225 mode being copied and which would not be valid as an operand of most
1226 insns. Eliminate this problem by not combining with such an insn.
1228 Also, on some machines we don't want to extend the life of a hard
1232 && ((REGNO (dest) < FIRST_PSEUDO_REGISTER
1233 && ! HARD_REGNO_MODE_OK (REGNO (dest), GET_MODE (dest)))
1234 /* Don't extend the life of a hard register unless it is
1235 user variable (if we have few registers) or it can't
1236 fit into the desired register (meaning something special
1238 Also avoid substituting a return register into I3, because
1239 reload can't handle a conflict with constraints of other
1241 || (REGNO (src) < FIRST_PSEUDO_REGISTER
1242 && ! HARD_REGNO_MODE_OK (REGNO (src), GET_MODE (src)))))
1245 else if (GET_CODE (dest) != CC0)
1249 if (GET_CODE (PATTERN (i3)) == PARALLEL)
1250 for (i = XVECLEN (PATTERN (i3), 0) - 1; i >= 0; i--)
1251 if (GET_CODE (XVECEXP (PATTERN (i3), 0, i)) == CLOBBER)
1253 /* Don't substitute for a register intended as a clobberable
1255 rtx reg = XEXP (XVECEXP (PATTERN (i3), 0, i), 0);
1256 if (rtx_equal_p (reg, dest))
1259 /* If the clobber represents an earlyclobber operand, we must not
1260 substitute an expression containing the clobbered register.
1261 As we do not analyse the constraint strings here, we have to
1262 make the conservative assumption. However, if the register is
1263 a fixed hard reg, the clobber cannot represent any operand;
1264 we leave it up to the machine description to either accept or
1265 reject use-and-clobber patterns. */
1267 || REGNO (reg) >= FIRST_PSEUDO_REGISTER
1268 || !fixed_regs[REGNO (reg)])
1269 if (reg_overlap_mentioned_p (reg, src))
1273 /* If INSN contains anything volatile, or is an `asm' (whether volatile
1274 or not), reject, unless nothing volatile comes between it and I3 */
1276 if (GET_CODE (src) == ASM_OPERANDS || volatile_refs_p (src))
1278 /* Make sure succ doesn't contain a volatile reference. */
1279 if (succ != 0 && volatile_refs_p (PATTERN (succ)))
1282 for (p = NEXT_INSN (insn); p != i3; p = NEXT_INSN (p))
1283 if (INSN_P (p) && p != succ && volatile_refs_p (PATTERN (p)))
1287 /* If INSN is an asm, and DEST is a hard register, reject, since it has
1288 to be an explicit register variable, and was chosen for a reason. */
1290 if (GET_CODE (src) == ASM_OPERANDS
1291 && REG_P (dest) && REGNO (dest) < FIRST_PSEUDO_REGISTER)
1294 /* If there are any volatile insns between INSN and I3, reject, because
1295 they might affect machine state. */
1297 for (p = NEXT_INSN (insn); p != i3; p = NEXT_INSN (p))
1298 if (INSN_P (p) && p != succ && volatile_insn_p (PATTERN (p)))
1301 /* If INSN or I2 contains an autoincrement or autodecrement,
1302 make sure that register is not used between there and I3,
1303 and not already used in I3 either.
1304 Also insist that I3 not be a jump; if it were one
1305 and the incremented register were spilled, we would lose. */
1308 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
1309 if (REG_NOTE_KIND (link) == REG_INC
1311 || reg_used_between_p (XEXP (link, 0), insn, i3)
1312 || reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i3))))
1317 /* Don't combine an insn that follows a CC0-setting insn.
1318 An insn that uses CC0 must not be separated from the one that sets it.
1319 We do, however, allow I2 to follow a CC0-setting insn if that insn
1320 is passed as I1; in that case it will be deleted also.
1321 We also allow combining in this case if all the insns are adjacent
1322 because that would leave the two CC0 insns adjacent as well.
1323 It would be more logical to test whether CC0 occurs inside I1 or I2,
1324 but that would be much slower, and this ought to be equivalent. */
1326 p = prev_nonnote_insn (insn);
1327 if (p && p != pred && NONJUMP_INSN_P (p) && sets_cc0_p (PATTERN (p))
1332 /* If we get here, we have passed all the tests and the combination is
1341 /* LOC is the location within I3 that contains its pattern or the component
1342 of a PARALLEL of the pattern. We validate that it is valid for combining.
1344 One problem is if I3 modifies its output, as opposed to replacing it
1345 entirely, we can't allow the output to contain I2DEST or I1DEST as doing
1346 so would produce an insn that is not equivalent to the original insns.
1350 (set (reg:DI 101) (reg:DI 100))
1351 (set (subreg:SI (reg:DI 101) 0) <foo>)
1353 This is NOT equivalent to:
1355 (parallel [(set (subreg:SI (reg:DI 100) 0) <foo>)
1356 (set (reg:DI 101) (reg:DI 100))])
1358 Not only does this modify 100 (in which case it might still be valid
1359 if 100 were dead in I2), it sets 101 to the ORIGINAL value of 100.
1361 We can also run into a problem if I2 sets a register that I1
1362 uses and I1 gets directly substituted into I3 (not via I2). In that
1363 case, we would be getting the wrong value of I2DEST into I3, so we
1364 must reject the combination. This case occurs when I2 and I1 both
1365 feed into I3, rather than when I1 feeds into I2, which feeds into I3.
1366 If I1_NOT_IN_SRC is nonzero, it means that finding I1 in the source
1367 of a SET must prevent combination from occurring.
1369 Before doing the above check, we first try to expand a field assignment
1370 into a set of logical operations.
1372 If PI3_DEST_KILLED is nonzero, it is a pointer to a location in which
1373 we place a register that is both set and used within I3. If more than one
1374 such register is detected, we fail.
1376 Return 1 if the combination is valid, zero otherwise. */
1379 combinable_i3pat (rtx i3, rtx *loc, rtx i2dest, rtx i1dest,
1380 int i1_not_in_src, rtx *pi3dest_killed)
1384 if (GET_CODE (x) == SET)
1387 rtx dest = SET_DEST (set);
1388 rtx src = SET_SRC (set);
1389 rtx inner_dest = dest;
1391 while (GET_CODE (inner_dest) == STRICT_LOW_PART
1392 || GET_CODE (inner_dest) == SUBREG
1393 || GET_CODE (inner_dest) == ZERO_EXTRACT)
1394 inner_dest = XEXP (inner_dest, 0);
1396 /* Check for the case where I3 modifies its output, as discussed
1397 above. We don't want to prevent pseudos from being combined
1398 into the address of a MEM, so only prevent the combination if
1399 i1 or i2 set the same MEM. */
1400 if ((inner_dest != dest &&
1401 (!MEM_P (inner_dest)
1402 || rtx_equal_p (i2dest, inner_dest)
1403 || (i1dest && rtx_equal_p (i1dest, inner_dest)))
1404 && (reg_overlap_mentioned_p (i2dest, inner_dest)
1405 || (i1dest && reg_overlap_mentioned_p (i1dest, inner_dest))))
1407 /* This is the same test done in can_combine_p except we can't test
1408 all_adjacent; we don't have to, since this instruction will stay
1409 in place, thus we are not considering increasing the lifetime of
1412 Also, if this insn sets a function argument, combining it with
1413 something that might need a spill could clobber a previous
1414 function argument; the all_adjacent test in can_combine_p also
1415 checks this; here, we do a more specific test for this case. */
1417 || (REG_P (inner_dest)
1418 && REGNO (inner_dest) < FIRST_PSEUDO_REGISTER
1419 && (! HARD_REGNO_MODE_OK (REGNO (inner_dest),
1420 GET_MODE (inner_dest))))
1421 || (i1_not_in_src && reg_overlap_mentioned_p (i1dest, src)))
1424 /* If DEST is used in I3, it is being killed in this insn,
1425 so record that for later.
1426 Never add REG_DEAD notes for the FRAME_POINTER_REGNUM or the
1427 STACK_POINTER_REGNUM, since these are always considered to be
1428 live. Similarly for ARG_POINTER_REGNUM if it is fixed. */
1429 if (pi3dest_killed && REG_P (dest)
1430 && reg_referenced_p (dest, PATTERN (i3))
1431 && REGNO (dest) != FRAME_POINTER_REGNUM
1432 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
1433 && REGNO (dest) != HARD_FRAME_POINTER_REGNUM
1435 #if ARG_POINTER_REGNUM != FRAME_POINTER_REGNUM
1436 && (REGNO (dest) != ARG_POINTER_REGNUM
1437 || ! fixed_regs [REGNO (dest)])
1439 && REGNO (dest) != STACK_POINTER_REGNUM)
1441 if (*pi3dest_killed)
1444 *pi3dest_killed = dest;
1448 else if (GET_CODE (x) == PARALLEL)
1452 for (i = 0; i < XVECLEN (x, 0); i++)
1453 if (! combinable_i3pat (i3, &XVECEXP (x, 0, i), i2dest, i1dest,
1454 i1_not_in_src, pi3dest_killed))
1461 /* Return 1 if X is an arithmetic expression that contains a multiplication
1462 and division. We don't count multiplications by powers of two here. */
1465 contains_muldiv (rtx x)
1467 switch (GET_CODE (x))
1469 case MOD: case DIV: case UMOD: case UDIV:
1473 return ! (GET_CODE (XEXP (x, 1)) == CONST_INT
1474 && exact_log2 (INTVAL (XEXP (x, 1))) >= 0);
1477 return contains_muldiv (XEXP (x, 0))
1478 || contains_muldiv (XEXP (x, 1));
1481 return contains_muldiv (XEXP (x, 0));
1487 /* Determine whether INSN can be used in a combination. Return nonzero if
1488 not. This is used in try_combine to detect early some cases where we
1489 can't perform combinations. */
1492 cant_combine_insn_p (rtx insn)
1497 /* If this isn't really an insn, we can't do anything.
1498 This can occur when flow deletes an insn that it has merged into an
1499 auto-increment address. */
1500 if (! INSN_P (insn))
1503 /* Never combine loads and stores involving hard regs that are likely
1504 to be spilled. The register allocator can usually handle such
1505 reg-reg moves by tying. If we allow the combiner to make
1506 substitutions of likely-spilled regs, we may abort in reload.
1507 As an exception, we allow combinations involving fixed regs; these are
1508 not available to the register allocator so there's no risk involved. */
1510 set = single_set (insn);
1513 src = SET_SRC (set);
1514 dest = SET_DEST (set);
1515 if (GET_CODE (src) == SUBREG)
1516 src = SUBREG_REG (src);
1517 if (GET_CODE (dest) == SUBREG)
1518 dest = SUBREG_REG (dest);
1519 if (REG_P (src) && REG_P (dest)
1520 && ((REGNO (src) < FIRST_PSEUDO_REGISTER
1521 && ! fixed_regs[REGNO (src)]
1522 && CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (REGNO (src))))
1523 || (REGNO (dest) < FIRST_PSEUDO_REGISTER
1524 && ! fixed_regs[REGNO (dest)]
1525 && CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (REGNO (dest))))))
1531 /* Adjust INSN after we made a change to its destination.
1533 Changing the destination can invalidate notes that say something about
1534 the results of the insn and a LOG_LINK pointing to the insn. */
1537 adjust_for_new_dest (rtx insn)
1541 /* For notes, be conservative and simply remove them. */
1542 loc = ®_NOTES (insn);
1545 enum reg_note kind = REG_NOTE_KIND (*loc);
1546 if (kind == REG_EQUAL || kind == REG_EQUIV)
1547 *loc = XEXP (*loc, 1);
1549 loc = &XEXP (*loc, 1);
1552 /* The new insn will have a destination that was previously the destination
1553 of an insn just above it. Call distribute_links to make a LOG_LINK from
1554 the next use of that destination. */
1555 distribute_links (gen_rtx_INSN_LIST (VOIDmode, insn, NULL_RTX));
1558 /* Try to combine the insns I1 and I2 into I3.
1559 Here I1 and I2 appear earlier than I3.
1560 I1 can be zero; then we combine just I2 into I3.
1562 If we are combining three insns and the resulting insn is not recognized,
1563 try splitting it into two insns. If that happens, I2 and I3 are retained
1564 and I1 is pseudo-deleted by turning it into a NOTE. Otherwise, I1 and I2
1567 Return 0 if the combination does not work. Then nothing is changed.
1568 If we did the combination, return the insn at which combine should
1571 Set NEW_DIRECT_JUMP_P to a nonzero value if try_combine creates a
1572 new direct jump instruction. */
1575 try_combine (rtx i3, rtx i2, rtx i1, int *new_direct_jump_p)
1577 /* New patterns for I3 and I2, respectively. */
1578 rtx newpat, newi2pat = 0;
1579 int substed_i2 = 0, substed_i1 = 0;
1580 /* Indicates need to preserve SET in I1 or I2 in I3 if it is not dead. */
1581 int added_sets_1, added_sets_2;
1582 /* Total number of SETs to put into I3. */
1584 /* Nonzero if I2's body now appears in I3. */
1586 /* INSN_CODEs for new I3, new I2, and user of condition code. */
1587 int insn_code_number, i2_code_number = 0, other_code_number = 0;
1588 /* Contains I3 if the destination of I3 is used in its source, which means
1589 that the old life of I3 is being killed. If that usage is placed into
1590 I2 and not in I3, a REG_DEAD note must be made. */
1591 rtx i3dest_killed = 0;
1592 /* SET_DEST and SET_SRC of I2 and I1. */
1593 rtx i2dest, i2src, i1dest = 0, i1src = 0;
1594 /* PATTERN (I2), or a copy of it in certain cases. */
1596 /* Indicates if I2DEST or I1DEST is in I2SRC or I1_SRC. */
1597 int i2dest_in_i2src = 0, i1dest_in_i1src = 0, i2dest_in_i1src = 0;
1598 int i1_feeds_i3 = 0;
1599 /* Notes that must be added to REG_NOTES in I3 and I2. */
1600 rtx new_i3_notes, new_i2_notes;
1601 /* Notes that we substituted I3 into I2 instead of the normal case. */
1602 int i3_subst_into_i2 = 0;
1603 /* Notes that I1, I2 or I3 is a MULT operation. */
1612 /* Exit early if one of the insns involved can't be used for
1614 if (cant_combine_insn_p (i3)
1615 || cant_combine_insn_p (i2)
1616 || (i1 && cant_combine_insn_p (i1))
1617 /* We also can't do anything if I3 has a
1618 REG_LIBCALL note since we don't want to disrupt the contiguity of a
1621 /* ??? This gives worse code, and appears to be unnecessary, since no
1622 pass after flow uses REG_LIBCALL/REG_RETVAL notes. */
1623 || find_reg_note (i3, REG_LIBCALL, NULL_RTX)
1629 undobuf.other_insn = 0;
1631 /* Reset the hard register usage information. */
1632 CLEAR_HARD_REG_SET (newpat_used_regs);
1634 /* If I1 and I2 both feed I3, they can be in any order. To simplify the
1635 code below, set I1 to be the earlier of the two insns. */
1636 if (i1 && INSN_CUID (i1) > INSN_CUID (i2))
1637 temp = i1, i1 = i2, i2 = temp;
1639 added_links_insn = 0;
1641 /* First check for one important special-case that the code below will
1642 not handle. Namely, the case where I1 is zero, I2 is a PARALLEL
1643 and I3 is a SET whose SET_SRC is a SET_DEST in I2. In that case,
1644 we may be able to replace that destination with the destination of I3.
1645 This occurs in the common code where we compute both a quotient and
1646 remainder into a structure, in which case we want to do the computation
1647 directly into the structure to avoid register-register copies.
1649 Note that this case handles both multiple sets in I2 and also
1650 cases where I2 has a number of CLOBBER or PARALLELs.
1652 We make very conservative checks below and only try to handle the
1653 most common cases of this. For example, we only handle the case
1654 where I2 and I3 are adjacent to avoid making difficult register
1657 if (i1 == 0 && NONJUMP_INSN_P (i3) && GET_CODE (PATTERN (i3)) == SET
1658 && REG_P (SET_SRC (PATTERN (i3)))
1659 && REGNO (SET_SRC (PATTERN (i3))) >= FIRST_PSEUDO_REGISTER
1660 && find_reg_note (i3, REG_DEAD, SET_SRC (PATTERN (i3)))
1661 && GET_CODE (PATTERN (i2)) == PARALLEL
1662 && ! side_effects_p (SET_DEST (PATTERN (i3)))
1663 /* If the dest of I3 is a ZERO_EXTRACT or STRICT_LOW_PART, the code
1664 below would need to check what is inside (and reg_overlap_mentioned_p
1665 doesn't support those codes anyway). Don't allow those destinations;
1666 the resulting insn isn't likely to be recognized anyway. */
1667 && GET_CODE (SET_DEST (PATTERN (i3))) != ZERO_EXTRACT
1668 && GET_CODE (SET_DEST (PATTERN (i3))) != STRICT_LOW_PART
1669 && ! reg_overlap_mentioned_p (SET_SRC (PATTERN (i3)),
1670 SET_DEST (PATTERN (i3)))
1671 && next_real_insn (i2) == i3)
1673 rtx p2 = PATTERN (i2);
1675 /* Make sure that the destination of I3,
1676 which we are going to substitute into one output of I2,
1677 is not used within another output of I2. We must avoid making this:
1678 (parallel [(set (mem (reg 69)) ...)
1679 (set (reg 69) ...)])
1680 which is not well-defined as to order of actions.
1681 (Besides, reload can't handle output reloads for this.)
1683 The problem can also happen if the dest of I3 is a memory ref,
1684 if another dest in I2 is an indirect memory ref. */
1685 for (i = 0; i < XVECLEN (p2, 0); i++)
1686 if ((GET_CODE (XVECEXP (p2, 0, i)) == SET
1687 || GET_CODE (XVECEXP (p2, 0, i)) == CLOBBER)
1688 && reg_overlap_mentioned_p (SET_DEST (PATTERN (i3)),
1689 SET_DEST (XVECEXP (p2, 0, i))))
1692 if (i == XVECLEN (p2, 0))
1693 for (i = 0; i < XVECLEN (p2, 0); i++)
1694 if ((GET_CODE (XVECEXP (p2, 0, i)) == SET
1695 || GET_CODE (XVECEXP (p2, 0, i)) == CLOBBER)
1696 && SET_DEST (XVECEXP (p2, 0, i)) == SET_SRC (PATTERN (i3)))
1701 subst_low_cuid = INSN_CUID (i2);
1703 added_sets_2 = added_sets_1 = 0;
1704 i2dest = SET_SRC (PATTERN (i3));
1706 /* Replace the dest in I2 with our dest and make the resulting
1707 insn the new pattern for I3. Then skip to where we
1708 validate the pattern. Everything was set up above. */
1709 SUBST (SET_DEST (XVECEXP (p2, 0, i)),
1710 SET_DEST (PATTERN (i3)));
1713 i3_subst_into_i2 = 1;
1714 goto validate_replacement;
1718 /* If I2 is setting a double-word pseudo to a constant and I3 is setting
1719 one of those words to another constant, merge them by making a new
1722 && (temp = single_set (i2)) != 0
1723 && (GET_CODE (SET_SRC (temp)) == CONST_INT
1724 || GET_CODE (SET_SRC (temp)) == CONST_DOUBLE)
1725 && REG_P (SET_DEST (temp))
1726 && GET_MODE_CLASS (GET_MODE (SET_DEST (temp))) == MODE_INT
1727 && GET_MODE_SIZE (GET_MODE (SET_DEST (temp))) == 2 * UNITS_PER_WORD
1728 && GET_CODE (PATTERN (i3)) == SET
1729 && GET_CODE (SET_DEST (PATTERN (i3))) == SUBREG
1730 && SUBREG_REG (SET_DEST (PATTERN (i3))) == SET_DEST (temp)
1731 && GET_MODE_CLASS (GET_MODE (SET_DEST (PATTERN (i3)))) == MODE_INT
1732 && GET_MODE_SIZE (GET_MODE (SET_DEST (PATTERN (i3)))) == UNITS_PER_WORD
1733 && GET_CODE (SET_SRC (PATTERN (i3))) == CONST_INT)
1735 HOST_WIDE_INT lo, hi;
1737 if (GET_CODE (SET_SRC (temp)) == CONST_INT)
1738 lo = INTVAL (SET_SRC (temp)), hi = lo < 0 ? -1 : 0;
1741 lo = CONST_DOUBLE_LOW (SET_SRC (temp));
1742 hi = CONST_DOUBLE_HIGH (SET_SRC (temp));
1745 if (subreg_lowpart_p (SET_DEST (PATTERN (i3))))
1747 /* We don't handle the case of the target word being wider
1748 than a host wide int. */
1749 if (HOST_BITS_PER_WIDE_INT < BITS_PER_WORD)
1752 lo &= ~(UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD (1) - 1);
1753 lo |= (INTVAL (SET_SRC (PATTERN (i3)))
1754 & (UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD (1) - 1));
1756 else if (HOST_BITS_PER_WIDE_INT == BITS_PER_WORD)
1757 hi = INTVAL (SET_SRC (PATTERN (i3)));
1758 else if (HOST_BITS_PER_WIDE_INT >= 2 * BITS_PER_WORD)
1760 int sign = -(int) ((unsigned HOST_WIDE_INT) lo
1761 >> (HOST_BITS_PER_WIDE_INT - 1));
1763 lo &= ~ (UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD
1764 (UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD (1) - 1));
1765 lo |= (UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD
1766 (INTVAL (SET_SRC (PATTERN (i3)))));
1768 hi = lo < 0 ? -1 : 0;
1771 /* We don't handle the case of the higher word not fitting
1772 entirely in either hi or lo. */
1777 subst_low_cuid = INSN_CUID (i2);
1778 added_sets_2 = added_sets_1 = 0;
1779 i2dest = SET_DEST (temp);
1781 SUBST (SET_SRC (temp),
1782 immed_double_const (lo, hi, GET_MODE (SET_DEST (temp))));
1784 newpat = PATTERN (i2);
1785 goto validate_replacement;
1789 /* If we have no I1 and I2 looks like:
1790 (parallel [(set (reg:CC X) (compare:CC OP (const_int 0)))
1792 make up a dummy I1 that is
1795 (set (reg:CC X) (compare:CC Y (const_int 0)))
1797 (We can ignore any trailing CLOBBERs.)
1799 This undoes a previous combination and allows us to match a branch-and-
1802 if (i1 == 0 && GET_CODE (PATTERN (i2)) == PARALLEL
1803 && XVECLEN (PATTERN (i2), 0) >= 2
1804 && GET_CODE (XVECEXP (PATTERN (i2), 0, 0)) == SET
1805 && (GET_MODE_CLASS (GET_MODE (SET_DEST (XVECEXP (PATTERN (i2), 0, 0))))
1807 && GET_CODE (SET_SRC (XVECEXP (PATTERN (i2), 0, 0))) == COMPARE
1808 && XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 1) == const0_rtx
1809 && GET_CODE (XVECEXP (PATTERN (i2), 0, 1)) == SET
1810 && REG_P (SET_DEST (XVECEXP (PATTERN (i2), 0, 1)))
1811 && rtx_equal_p (XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 0),
1812 SET_SRC (XVECEXP (PATTERN (i2), 0, 1))))
1814 for (i = XVECLEN (PATTERN (i2), 0) - 1; i >= 2; i--)
1815 if (GET_CODE (XVECEXP (PATTERN (i2), 0, i)) != CLOBBER)
1820 /* We make I1 with the same INSN_UID as I2. This gives it
1821 the same INSN_CUID for value tracking. Our fake I1 will
1822 never appear in the insn stream so giving it the same INSN_UID
1823 as I2 will not cause a problem. */
1825 i1 = gen_rtx_INSN (VOIDmode, INSN_UID (i2), NULL_RTX, i2,
1826 BLOCK_FOR_INSN (i2), INSN_LOCATOR (i2),
1827 XVECEXP (PATTERN (i2), 0, 1), -1, NULL_RTX,
1830 SUBST (PATTERN (i2), XVECEXP (PATTERN (i2), 0, 0));
1831 SUBST (XEXP (SET_SRC (PATTERN (i2)), 0),
1832 SET_DEST (PATTERN (i1)));
1837 /* Verify that I2 and I1 are valid for combining. */
1838 if (! can_combine_p (i2, i3, i1, NULL_RTX, &i2dest, &i2src)
1839 || (i1 && ! can_combine_p (i1, i3, NULL_RTX, i2, &i1dest, &i1src)))
1845 /* Record whether I2DEST is used in I2SRC and similarly for the other
1846 cases. Knowing this will help in register status updating below. */
1847 i2dest_in_i2src = reg_overlap_mentioned_p (i2dest, i2src);
1848 i1dest_in_i1src = i1 && reg_overlap_mentioned_p (i1dest, i1src);
1849 i2dest_in_i1src = i1 && reg_overlap_mentioned_p (i2dest, i1src);
1851 /* See if I1 directly feeds into I3. It does if I1DEST is not used
1853 i1_feeds_i3 = i1 && ! reg_overlap_mentioned_p (i1dest, i2src);
1855 /* Ensure that I3's pattern can be the destination of combines. */
1856 if (! combinable_i3pat (i3, &PATTERN (i3), i2dest, i1dest,
1857 i1 && i2dest_in_i1src && i1_feeds_i3,
1864 /* See if any of the insns is a MULT operation. Unless one is, we will
1865 reject a combination that is, since it must be slower. Be conservative
1867 if (GET_CODE (i2src) == MULT
1868 || (i1 != 0 && GET_CODE (i1src) == MULT)
1869 || (GET_CODE (PATTERN (i3)) == SET
1870 && GET_CODE (SET_SRC (PATTERN (i3))) == MULT))
1873 /* If I3 has an inc, then give up if I1 or I2 uses the reg that is inc'd.
1874 We used to do this EXCEPT in one case: I3 has a post-inc in an
1875 output operand. However, that exception can give rise to insns like
1877 which is a famous insn on the PDP-11 where the value of r3 used as the
1878 source was model-dependent. Avoid this sort of thing. */
1881 if (!(GET_CODE (PATTERN (i3)) == SET
1882 && REG_P (SET_SRC (PATTERN (i3)))
1883 && MEM_P (SET_DEST (PATTERN (i3)))
1884 && (GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_INC
1885 || GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_DEC)))
1886 /* It's not the exception. */
1889 for (link = REG_NOTES (i3); link; link = XEXP (link, 1))
1890 if (REG_NOTE_KIND (link) == REG_INC
1891 && (reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i2))
1893 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i1)))))
1900 /* See if the SETs in I1 or I2 need to be kept around in the merged
1901 instruction: whenever the value set there is still needed past I3.
1902 For the SETs in I2, this is easy: we see if I2DEST dies or is set in I3.
1904 For the SET in I1, we have two cases: If I1 and I2 independently
1905 feed into I3, the set in I1 needs to be kept around if I1DEST dies
1906 or is set in I3. Otherwise (if I1 feeds I2 which feeds I3), the set
1907 in I1 needs to be kept around unless I1DEST dies or is set in either
1908 I2 or I3. We can distinguish these cases by seeing if I2SRC mentions
1909 I1DEST. If so, we know I1 feeds into I2. */
1911 added_sets_2 = ! dead_or_set_p (i3, i2dest);
1914 = i1 && ! (i1_feeds_i3 ? dead_or_set_p (i3, i1dest)
1915 : (dead_or_set_p (i3, i1dest) || dead_or_set_p (i2, i1dest)));
1917 /* If the set in I2 needs to be kept around, we must make a copy of
1918 PATTERN (I2), so that when we substitute I1SRC for I1DEST in
1919 PATTERN (I2), we are only substituting for the original I1DEST, not into
1920 an already-substituted copy. This also prevents making self-referential
1921 rtx. If I2 is a PARALLEL, we just need the piece that assigns I2SRC to
1924 i2pat = (GET_CODE (PATTERN (i2)) == PARALLEL
1925 ? gen_rtx_SET (VOIDmode, i2dest, i2src)
1929 i2pat = copy_rtx (i2pat);
1933 /* Substitute in the latest insn for the regs set by the earlier ones. */
1935 maxreg = max_reg_num ();
1939 /* It is possible that the source of I2 or I1 may be performing an
1940 unneeded operation, such as a ZERO_EXTEND of something that is known
1941 to have the high part zero. Handle that case by letting subst look at
1942 the innermost one of them.
1944 Another way to do this would be to have a function that tries to
1945 simplify a single insn instead of merging two or more insns. We don't
1946 do this because of the potential of infinite loops and because
1947 of the potential extra memory required. However, doing it the way
1948 we are is a bit of a kludge and doesn't catch all cases.
1950 But only do this if -fexpensive-optimizations since it slows things down
1951 and doesn't usually win. */
1953 if (flag_expensive_optimizations)
1955 /* Pass pc_rtx so no substitutions are done, just simplifications. */
1958 subst_low_cuid = INSN_CUID (i1);
1959 i1src = subst (i1src, pc_rtx, pc_rtx, 0, 0);
1963 subst_low_cuid = INSN_CUID (i2);
1964 i2src = subst (i2src, pc_rtx, pc_rtx, 0, 0);
1969 /* Many machines that don't use CC0 have insns that can both perform an
1970 arithmetic operation and set the condition code. These operations will
1971 be represented as a PARALLEL with the first element of the vector
1972 being a COMPARE of an arithmetic operation with the constant zero.
1973 The second element of the vector will set some pseudo to the result
1974 of the same arithmetic operation. If we simplify the COMPARE, we won't
1975 match such a pattern and so will generate an extra insn. Here we test
1976 for this case, where both the comparison and the operation result are
1977 needed, and make the PARALLEL by just replacing I2DEST in I3SRC with
1978 I2SRC. Later we will make the PARALLEL that contains I2. */
1980 if (i1 == 0 && added_sets_2 && GET_CODE (PATTERN (i3)) == SET
1981 && GET_CODE (SET_SRC (PATTERN (i3))) == COMPARE
1982 && XEXP (SET_SRC (PATTERN (i3)), 1) == const0_rtx
1983 && rtx_equal_p (XEXP (SET_SRC (PATTERN (i3)), 0), i2dest))
1985 #ifdef SELECT_CC_MODE
1987 enum machine_mode compare_mode;
1990 newpat = PATTERN (i3);
1991 SUBST (XEXP (SET_SRC (newpat), 0), i2src);
1995 #ifdef SELECT_CC_MODE
1996 /* See if a COMPARE with the operand we substituted in should be done
1997 with the mode that is currently being used. If not, do the same
1998 processing we do in `subst' for a SET; namely, if the destination
1999 is used only once, try to replace it with a register of the proper
2000 mode and also replace the COMPARE. */
2001 if (undobuf.other_insn == 0
2002 && (cc_use = find_single_use (SET_DEST (newpat), i3,
2003 &undobuf.other_insn))
2004 && ((compare_mode = SELECT_CC_MODE (GET_CODE (*cc_use),
2006 != GET_MODE (SET_DEST (newpat))))
2008 unsigned int regno = REGNO (SET_DEST (newpat));
2009 rtx new_dest = gen_rtx_REG (compare_mode, regno);
2011 if (regno < FIRST_PSEUDO_REGISTER
2012 || (REG_N_SETS (regno) == 1 && ! added_sets_2
2013 && ! REG_USERVAR_P (SET_DEST (newpat))))
2015 if (regno >= FIRST_PSEUDO_REGISTER)
2016 SUBST (regno_reg_rtx[regno], new_dest);
2018 SUBST (SET_DEST (newpat), new_dest);
2019 SUBST (XEXP (*cc_use, 0), new_dest);
2020 SUBST (SET_SRC (newpat),
2021 gen_rtx_COMPARE (compare_mode, i2src, const0_rtx));
2024 undobuf.other_insn = 0;
2031 n_occurrences = 0; /* `subst' counts here */
2033 /* If I1 feeds into I2 (not into I3) and I1DEST is in I1SRC, we
2034 need to make a unique copy of I2SRC each time we substitute it
2035 to avoid self-referential rtl. */
2037 subst_low_cuid = INSN_CUID (i2);
2038 newpat = subst (PATTERN (i3), i2dest, i2src, 0,
2039 ! i1_feeds_i3 && i1dest_in_i1src);
2042 /* Record whether i2's body now appears within i3's body. */
2043 i2_is_used = n_occurrences;
2046 /* If we already got a failure, don't try to do more. Otherwise,
2047 try to substitute in I1 if we have it. */
2049 if (i1 && GET_CODE (newpat) != CLOBBER)
2051 /* Before we can do this substitution, we must redo the test done
2052 above (see detailed comments there) that ensures that I1DEST
2053 isn't mentioned in any SETs in NEWPAT that are field assignments. */
2055 if (! combinable_i3pat (NULL_RTX, &newpat, i1dest, NULL_RTX,
2063 subst_low_cuid = INSN_CUID (i1);
2064 newpat = subst (newpat, i1dest, i1src, 0, 0);
2068 /* Fail if an autoincrement side-effect has been duplicated. Be careful
2069 to count all the ways that I2SRC and I1SRC can be used. */
2070 if ((FIND_REG_INC_NOTE (i2, NULL_RTX) != 0
2071 && i2_is_used + added_sets_2 > 1)
2072 || (i1 != 0 && FIND_REG_INC_NOTE (i1, NULL_RTX) != 0
2073 && (n_occurrences + added_sets_1 + (added_sets_2 && ! i1_feeds_i3)
2075 /* Fail if we tried to make a new register (we used to abort, but there's
2076 really no reason to). */
2077 || max_reg_num () != maxreg
2078 /* Fail if we couldn't do something and have a CLOBBER. */
2079 || GET_CODE (newpat) == CLOBBER
2080 /* Fail if this new pattern is a MULT and we didn't have one before
2081 at the outer level. */
2082 || (GET_CODE (newpat) == SET && GET_CODE (SET_SRC (newpat)) == MULT
2089 /* If the actions of the earlier insns must be kept
2090 in addition to substituting them into the latest one,
2091 we must make a new PARALLEL for the latest insn
2092 to hold additional the SETs. */
2094 if (added_sets_1 || added_sets_2)
2098 if (GET_CODE (newpat) == PARALLEL)
2100 rtvec old = XVEC (newpat, 0);
2101 total_sets = XVECLEN (newpat, 0) + added_sets_1 + added_sets_2;
2102 newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (total_sets));
2103 memcpy (XVEC (newpat, 0)->elem, &old->elem[0],
2104 sizeof (old->elem[0]) * old->num_elem);
2109 total_sets = 1 + added_sets_1 + added_sets_2;
2110 newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (total_sets));
2111 XVECEXP (newpat, 0, 0) = old;
2115 XVECEXP (newpat, 0, --total_sets)
2116 = (GET_CODE (PATTERN (i1)) == PARALLEL
2117 ? gen_rtx_SET (VOIDmode, i1dest, i1src) : PATTERN (i1));
2121 /* If there is no I1, use I2's body as is. We used to also not do
2122 the subst call below if I2 was substituted into I3,
2123 but that could lose a simplification. */
2125 XVECEXP (newpat, 0, --total_sets) = i2pat;
2127 /* See comment where i2pat is assigned. */
2128 XVECEXP (newpat, 0, --total_sets)
2129 = subst (i2pat, i1dest, i1src, 0, 0);
2133 /* We come here when we are replacing a destination in I2 with the
2134 destination of I3. */
2135 validate_replacement:
2137 /* Note which hard regs this insn has as inputs. */
2138 mark_used_regs_combine (newpat);
2140 /* Is the result of combination a valid instruction? */
2141 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2143 /* If the result isn't valid, see if it is a PARALLEL of two SETs where
2144 the second SET's destination is a register that is unused and isn't
2145 marked as an instruction that might trap in an EH region. In that case,
2146 we just need the first SET. This can occur when simplifying a divmod
2147 insn. We *must* test for this case here because the code below that
2148 splits two independent SETs doesn't handle this case correctly when it
2149 updates the register status.
2151 It's pointless doing this if we originally had two sets, one from
2152 i3, and one from i2. Combining then splitting the parallel results
2153 in the original i2 again plus an invalid insn (which we delete).
2154 The net effect is only to move instructions around, which makes
2155 debug info less accurate.
2157 Also check the case where the first SET's destination is unused.
2158 That would not cause incorrect code, but does cause an unneeded
2161 if (insn_code_number < 0
2162 && !(added_sets_2 && i1 == 0)
2163 && GET_CODE (newpat) == PARALLEL
2164 && XVECLEN (newpat, 0) == 2
2165 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
2166 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
2167 && asm_noperands (newpat) < 0)
2169 rtx set0 = XVECEXP (newpat, 0, 0);
2170 rtx set1 = XVECEXP (newpat, 0, 1);
2173 if (((REG_P (SET_DEST (set1))
2174 && find_reg_note (i3, REG_UNUSED, SET_DEST (set1)))
2175 || (GET_CODE (SET_DEST (set1)) == SUBREG
2176 && find_reg_note (i3, REG_UNUSED, SUBREG_REG (SET_DEST (set1)))))
2177 && (!(note = find_reg_note (i3, REG_EH_REGION, NULL_RTX))
2178 || INTVAL (XEXP (note, 0)) <= 0)
2179 && ! side_effects_p (SET_SRC (set1)))
2182 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2185 else if (((REG_P (SET_DEST (set0))
2186 && find_reg_note (i3, REG_UNUSED, SET_DEST (set0)))
2187 || (GET_CODE (SET_DEST (set0)) == SUBREG
2188 && find_reg_note (i3, REG_UNUSED,
2189 SUBREG_REG (SET_DEST (set0)))))
2190 && (!(note = find_reg_note (i3, REG_EH_REGION, NULL_RTX))
2191 || INTVAL (XEXP (note, 0)) <= 0)
2192 && ! side_effects_p (SET_SRC (set0)))
2195 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2197 if (insn_code_number >= 0)
2199 /* If we will be able to accept this, we have made a
2200 change to the destination of I3. This requires us to
2201 do a few adjustments. */
2203 PATTERN (i3) = newpat;
2204 adjust_for_new_dest (i3);
2209 /* If we were combining three insns and the result is a simple SET
2210 with no ASM_OPERANDS that wasn't recognized, try to split it into two
2211 insns. There are two ways to do this. It can be split using a
2212 machine-specific method (like when you have an addition of a large
2213 constant) or by combine in the function find_split_point. */
2215 if (i1 && insn_code_number < 0 && GET_CODE (newpat) == SET
2216 && asm_noperands (newpat) < 0)
2218 rtx m_split, *split;
2219 rtx ni2dest = i2dest;
2221 /* See if the MD file can split NEWPAT. If it can't, see if letting it
2222 use I2DEST as a scratch register will help. In the latter case,
2223 convert I2DEST to the mode of the source of NEWPAT if we can. */
2225 m_split = split_insns (newpat, i3);
2227 /* We can only use I2DEST as a scratch reg if it doesn't overlap any
2228 inputs of NEWPAT. */
2230 /* ??? If I2DEST is not safe, and I1DEST exists, then it would be
2231 possible to try that as a scratch reg. This would require adding
2232 more code to make it work though. */
2234 if (m_split == 0 && ! reg_overlap_mentioned_p (ni2dest, newpat))
2236 /* If I2DEST is a hard register or the only use of a pseudo,
2237 we can change its mode. */
2238 if (GET_MODE (SET_DEST (newpat)) != GET_MODE (i2dest)
2239 && GET_MODE (SET_DEST (newpat)) != VOIDmode
2241 && (REGNO (i2dest) < FIRST_PSEUDO_REGISTER
2242 || (REG_N_SETS (REGNO (i2dest)) == 1 && ! added_sets_2
2243 && ! REG_USERVAR_P (i2dest))))
2244 ni2dest = gen_rtx_REG (GET_MODE (SET_DEST (newpat)),
2247 m_split = split_insns (gen_rtx_PARALLEL
2249 gen_rtvec (2, newpat,
2250 gen_rtx_CLOBBER (VOIDmode,
2253 /* If the split with the mode-changed register didn't work, try
2254 the original register. */
2255 if (! m_split && ni2dest != i2dest)
2258 m_split = split_insns (gen_rtx_PARALLEL
2260 gen_rtvec (2, newpat,
2261 gen_rtx_CLOBBER (VOIDmode,
2267 if (m_split && NEXT_INSN (m_split) == NULL_RTX)
2269 m_split = PATTERN (m_split);
2270 insn_code_number = recog_for_combine (&m_split, i3, &new_i3_notes);
2271 if (insn_code_number >= 0)
2274 else if (m_split && NEXT_INSN (NEXT_INSN (m_split)) == NULL_RTX
2275 && (next_real_insn (i2) == i3
2276 || ! use_crosses_set_p (PATTERN (m_split), INSN_CUID (i2))))
2279 rtx newi3pat = PATTERN (NEXT_INSN (m_split));
2280 newi2pat = PATTERN (m_split);
2282 i3set = single_set (NEXT_INSN (m_split));
2283 i2set = single_set (m_split);
2285 /* In case we changed the mode of I2DEST, replace it in the
2286 pseudo-register table here. We can't do it above in case this
2287 code doesn't get executed and we do a split the other way. */
2289 if (REGNO (i2dest) >= FIRST_PSEUDO_REGISTER)
2290 SUBST (regno_reg_rtx[REGNO (i2dest)], ni2dest);
2292 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
2294 /* If I2 or I3 has multiple SETs, we won't know how to track
2295 register status, so don't use these insns. If I2's destination
2296 is used between I2 and I3, we also can't use these insns. */
2298 if (i2_code_number >= 0 && i2set && i3set
2299 && (next_real_insn (i2) == i3
2300 || ! reg_used_between_p (SET_DEST (i2set), i2, i3)))
2301 insn_code_number = recog_for_combine (&newi3pat, i3,
2303 if (insn_code_number >= 0)
2306 /* It is possible that both insns now set the destination of I3.
2307 If so, we must show an extra use of it. */
2309 if (insn_code_number >= 0)
2311 rtx new_i3_dest = SET_DEST (i3set);
2312 rtx new_i2_dest = SET_DEST (i2set);
2314 while (GET_CODE (new_i3_dest) == ZERO_EXTRACT
2315 || GET_CODE (new_i3_dest) == STRICT_LOW_PART
2316 || GET_CODE (new_i3_dest) == SUBREG)
2317 new_i3_dest = XEXP (new_i3_dest, 0);
2319 while (GET_CODE (new_i2_dest) == ZERO_EXTRACT
2320 || GET_CODE (new_i2_dest) == STRICT_LOW_PART
2321 || GET_CODE (new_i2_dest) == SUBREG)
2322 new_i2_dest = XEXP (new_i2_dest, 0);
2324 if (REG_P (new_i3_dest)
2325 && REG_P (new_i2_dest)
2326 && REGNO (new_i3_dest) == REGNO (new_i2_dest))
2327 REG_N_SETS (REGNO (new_i2_dest))++;
2331 /* If we can split it and use I2DEST, go ahead and see if that
2332 helps things be recognized. Verify that none of the registers
2333 are set between I2 and I3. */
2334 if (insn_code_number < 0 && (split = find_split_point (&newpat, i3)) != 0
2338 /* We need I2DEST in the proper mode. If it is a hard register
2339 or the only use of a pseudo, we can change its mode. */
2340 && (GET_MODE (*split) == GET_MODE (i2dest)
2341 || GET_MODE (*split) == VOIDmode
2342 || REGNO (i2dest) < FIRST_PSEUDO_REGISTER
2343 || (REG_N_SETS (REGNO (i2dest)) == 1 && ! added_sets_2
2344 && ! REG_USERVAR_P (i2dest)))
2345 && (next_real_insn (i2) == i3
2346 || ! use_crosses_set_p (*split, INSN_CUID (i2)))
2347 /* We can't overwrite I2DEST if its value is still used by
2349 && ! reg_referenced_p (i2dest, newpat))
2351 rtx newdest = i2dest;
2352 enum rtx_code split_code = GET_CODE (*split);
2353 enum machine_mode split_mode = GET_MODE (*split);
2355 /* Get NEWDEST as a register in the proper mode. We have already
2356 validated that we can do this. */
2357 if (GET_MODE (i2dest) != split_mode && split_mode != VOIDmode)
2359 newdest = gen_rtx_REG (split_mode, REGNO (i2dest));
2361 if (REGNO (i2dest) >= FIRST_PSEUDO_REGISTER)
2362 SUBST (regno_reg_rtx[REGNO (i2dest)], newdest);
2365 /* If *SPLIT is a (mult FOO (const_int pow2)), convert it to
2366 an ASHIFT. This can occur if it was inside a PLUS and hence
2367 appeared to be a memory address. This is a kludge. */
2368 if (split_code == MULT
2369 && GET_CODE (XEXP (*split, 1)) == CONST_INT
2370 && INTVAL (XEXP (*split, 1)) > 0
2371 && (i = exact_log2 (INTVAL (XEXP (*split, 1)))) >= 0)
2373 SUBST (*split, gen_rtx_ASHIFT (split_mode,
2374 XEXP (*split, 0), GEN_INT (i)));
2375 /* Update split_code because we may not have a multiply
2377 split_code = GET_CODE (*split);
2380 #ifdef INSN_SCHEDULING
2381 /* If *SPLIT is a paradoxical SUBREG, when we split it, it should
2382 be written as a ZERO_EXTEND. */
2383 if (split_code == SUBREG && MEM_P (SUBREG_REG (*split)))
2385 #ifdef LOAD_EXTEND_OP
2386 /* Or as a SIGN_EXTEND if LOAD_EXTEND_OP says that that's
2387 what it really is. */
2388 if (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (*split)))
2390 SUBST (*split, gen_rtx_SIGN_EXTEND (split_mode,
2391 SUBREG_REG (*split)));
2394 SUBST (*split, gen_rtx_ZERO_EXTEND (split_mode,
2395 SUBREG_REG (*split)));
2399 newi2pat = gen_rtx_SET (VOIDmode, newdest, *split);
2400 SUBST (*split, newdest);
2401 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
2403 /* If the split point was a MULT and we didn't have one before,
2404 don't use one now. */
2405 if (i2_code_number >= 0 && ! (split_code == MULT && ! have_mult))
2406 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2410 /* Check for a case where we loaded from memory in a narrow mode and
2411 then sign extended it, but we need both registers. In that case,
2412 we have a PARALLEL with both loads from the same memory location.
2413 We can split this into a load from memory followed by a register-register
2414 copy. This saves at least one insn, more if register allocation can
2417 We cannot do this if the destination of the first assignment is a
2418 condition code register or cc0. We eliminate this case by making sure
2419 the SET_DEST and SET_SRC have the same mode.
2421 We cannot do this if the destination of the second assignment is
2422 a register that we have already assumed is zero-extended. Similarly
2423 for a SUBREG of such a register. */
2425 else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0
2426 && GET_CODE (newpat) == PARALLEL
2427 && XVECLEN (newpat, 0) == 2
2428 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
2429 && GET_CODE (SET_SRC (XVECEXP (newpat, 0, 0))) == SIGN_EXTEND
2430 && (GET_MODE (SET_DEST (XVECEXP (newpat, 0, 0)))
2431 == GET_MODE (SET_SRC (XVECEXP (newpat, 0, 0))))
2432 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
2433 && rtx_equal_p (SET_SRC (XVECEXP (newpat, 0, 1)),
2434 XEXP (SET_SRC (XVECEXP (newpat, 0, 0)), 0))
2435 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)),
2437 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
2438 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
2439 && ! (temp = SET_DEST (XVECEXP (newpat, 0, 1)),
2441 && reg_stat[REGNO (temp)].nonzero_bits != 0
2442 && GET_MODE_BITSIZE (GET_MODE (temp)) < BITS_PER_WORD
2443 && GET_MODE_BITSIZE (GET_MODE (temp)) < HOST_BITS_PER_INT
2444 && (reg_stat[REGNO (temp)].nonzero_bits
2445 != GET_MODE_MASK (word_mode))))
2446 && ! (GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) == SUBREG
2447 && (temp = SUBREG_REG (SET_DEST (XVECEXP (newpat, 0, 1))),
2449 && reg_stat[REGNO (temp)].nonzero_bits != 0
2450 && GET_MODE_BITSIZE (GET_MODE (temp)) < BITS_PER_WORD
2451 && GET_MODE_BITSIZE (GET_MODE (temp)) < HOST_BITS_PER_INT
2452 && (reg_stat[REGNO (temp)].nonzero_bits
2453 != GET_MODE_MASK (word_mode)))))
2454 && ! reg_overlap_mentioned_p (SET_DEST (XVECEXP (newpat, 0, 1)),
2455 SET_SRC (XVECEXP (newpat, 0, 1)))
2456 && ! find_reg_note (i3, REG_UNUSED,
2457 SET_DEST (XVECEXP (newpat, 0, 0))))
2461 newi2pat = XVECEXP (newpat, 0, 0);
2462 ni2dest = SET_DEST (XVECEXP (newpat, 0, 0));
2463 newpat = XVECEXP (newpat, 0, 1);
2464 SUBST (SET_SRC (newpat),
2465 gen_lowpart (GET_MODE (SET_SRC (newpat)), ni2dest));
2466 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
2468 if (i2_code_number >= 0)
2469 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2471 if (insn_code_number >= 0)
2475 /* Similarly, check for a case where we have a PARALLEL of two independent
2476 SETs but we started with three insns. In this case, we can do the sets
2477 as two separate insns. This case occurs when some SET allows two
2478 other insns to combine, but the destination of that SET is still live. */
2480 else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0
2481 && GET_CODE (newpat) == PARALLEL
2482 && XVECLEN (newpat, 0) == 2
2483 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
2484 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != ZERO_EXTRACT
2485 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != STRICT_LOW_PART
2486 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
2487 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
2488 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
2489 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)),
2491 /* Don't pass sets with (USE (MEM ...)) dests to the following. */
2492 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != USE
2493 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != USE
2494 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 1)),
2495 XVECEXP (newpat, 0, 0))
2496 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 0)),
2497 XVECEXP (newpat, 0, 1))
2498 && ! (contains_muldiv (SET_SRC (XVECEXP (newpat, 0, 0)))
2499 && contains_muldiv (SET_SRC (XVECEXP (newpat, 0, 1)))))
2501 /* Normally, it doesn't matter which of the two is done first,
2502 but it does if one references cc0. In that case, it has to
2505 if (reg_referenced_p (cc0_rtx, XVECEXP (newpat, 0, 0)))
2507 newi2pat = XVECEXP (newpat, 0, 0);
2508 newpat = XVECEXP (newpat, 0, 1);
2513 newi2pat = XVECEXP (newpat, 0, 1);
2514 newpat = XVECEXP (newpat, 0, 0);
2517 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
2519 if (i2_code_number >= 0)
2520 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2523 /* If it still isn't recognized, fail and change things back the way they
2525 if ((insn_code_number < 0
2526 /* Is the result a reasonable ASM_OPERANDS? */
2527 && (! check_asm_operands (newpat) || added_sets_1 || added_sets_2)))
2533 /* If we had to change another insn, make sure it is valid also. */
2534 if (undobuf.other_insn)
2536 rtx other_pat = PATTERN (undobuf.other_insn);
2537 rtx new_other_notes;
2540 CLEAR_HARD_REG_SET (newpat_used_regs);
2542 other_code_number = recog_for_combine (&other_pat, undobuf.other_insn,
2545 if (other_code_number < 0 && ! check_asm_operands (other_pat))
2551 PATTERN (undobuf.other_insn) = other_pat;
2553 /* If any of the notes in OTHER_INSN were REG_UNUSED, ensure that they
2554 are still valid. Then add any non-duplicate notes added by
2555 recog_for_combine. */
2556 for (note = REG_NOTES (undobuf.other_insn); note; note = next)
2558 next = XEXP (note, 1);
2560 if (REG_NOTE_KIND (note) == REG_UNUSED
2561 && ! reg_set_p (XEXP (note, 0), PATTERN (undobuf.other_insn)))
2563 if (REG_P (XEXP (note, 0)))
2564 REG_N_DEATHS (REGNO (XEXP (note, 0)))--;
2566 remove_note (undobuf.other_insn, note);
2570 for (note = new_other_notes; note; note = XEXP (note, 1))
2571 if (REG_P (XEXP (note, 0)))
2572 REG_N_DEATHS (REGNO (XEXP (note, 0)))++;
2574 distribute_notes (new_other_notes, undobuf.other_insn,
2575 undobuf.other_insn, NULL_RTX);
2578 /* If I2 is the CC0 setter and I3 is the CC0 user then check whether
2579 they are adjacent to each other or not. */
2581 rtx p = prev_nonnote_insn (i3);
2582 if (p && p != i2 && NONJUMP_INSN_P (p) && newi2pat
2583 && sets_cc0_p (newi2pat))
2591 /* Only allow this combination if insn_rtx_costs reports that the
2592 replacement instructions are cheaper than the originals. */
2593 if (!combine_validate_cost (i1, i2, i3, newpat, newi2pat))
2599 /* We now know that we can do this combination. Merge the insns and
2600 update the status of registers and LOG_LINKS. */
2608 /* I3 now uses what used to be its destination and which is now
2609 I2's destination. This requires us to do a few adjustments. */
2610 PATTERN (i3) = newpat;
2611 adjust_for_new_dest (i3);
2613 /* We need a LOG_LINK from I3 to I2. But we used to have one,
2616 However, some later insn might be using I2's dest and have
2617 a LOG_LINK pointing at I3. We must remove this link.
2618 The simplest way to remove the link is to point it at I1,
2619 which we know will be a NOTE. */
2621 ni2dest = SET_DEST (newi2pat);
2622 for (insn = NEXT_INSN (i3);
2623 insn && (this_basic_block->next_bb == EXIT_BLOCK_PTR
2624 || insn != BB_HEAD (this_basic_block->next_bb));
2625 insn = NEXT_INSN (insn))
2627 if (INSN_P (insn) && reg_referenced_p (ni2dest, PATTERN (insn)))
2629 for (link = LOG_LINKS (insn); link;
2630 link = XEXP (link, 1))
2631 if (XEXP (link, 0) == i3)
2632 XEXP (link, 0) = i1;
2640 rtx i3notes, i2notes, i1notes = 0;
2641 rtx i3links, i2links, i1links = 0;
2645 /* Get the old REG_NOTES and LOG_LINKS from all our insns and
2647 i3notes = REG_NOTES (i3), i3links = LOG_LINKS (i3);
2648 i2notes = REG_NOTES (i2), i2links = LOG_LINKS (i2);
2650 i1notes = REG_NOTES (i1), i1links = LOG_LINKS (i1);
2652 /* Ensure that we do not have something that should not be shared but
2653 occurs multiple times in the new insns. Check this by first
2654 resetting all the `used' flags and then copying anything is shared. */
2656 reset_used_flags (i3notes);
2657 reset_used_flags (i2notes);
2658 reset_used_flags (i1notes);
2659 reset_used_flags (newpat);
2660 reset_used_flags (newi2pat);
2661 if (undobuf.other_insn)
2662 reset_used_flags (PATTERN (undobuf.other_insn));
2664 i3notes = copy_rtx_if_shared (i3notes);
2665 i2notes = copy_rtx_if_shared (i2notes);
2666 i1notes = copy_rtx_if_shared (i1notes);
2667 newpat = copy_rtx_if_shared (newpat);
2668 newi2pat = copy_rtx_if_shared (newi2pat);
2669 if (undobuf.other_insn)
2670 reset_used_flags (PATTERN (undobuf.other_insn));
2672 INSN_CODE (i3) = insn_code_number;
2673 PATTERN (i3) = newpat;
2675 if (CALL_P (i3) && CALL_INSN_FUNCTION_USAGE (i3))
2677 rtx call_usage = CALL_INSN_FUNCTION_USAGE (i3);
2679 reset_used_flags (call_usage);
2680 call_usage = copy_rtx (call_usage);
2683 replace_rtx (call_usage, i2dest, i2src);
2686 replace_rtx (call_usage, i1dest, i1src);
2688 CALL_INSN_FUNCTION_USAGE (i3) = call_usage;
2691 if (undobuf.other_insn)
2692 INSN_CODE (undobuf.other_insn) = other_code_number;
2694 /* We had one special case above where I2 had more than one set and
2695 we replaced a destination of one of those sets with the destination
2696 of I3. In that case, we have to update LOG_LINKS of insns later
2697 in this basic block. Note that this (expensive) case is rare.
2699 Also, in this case, we must pretend that all REG_NOTEs for I2
2700 actually came from I3, so that REG_UNUSED notes from I2 will be
2701 properly handled. */
2703 if (i3_subst_into_i2)
2705 for (i = 0; i < XVECLEN (PATTERN (i2), 0); i++)
2706 if (GET_CODE (XVECEXP (PATTERN (i2), 0, i)) != USE
2707 && REG_P (SET_DEST (XVECEXP (PATTERN (i2), 0, i)))
2708 && SET_DEST (XVECEXP (PATTERN (i2), 0, i)) != i2dest
2709 && ! find_reg_note (i2, REG_UNUSED,
2710 SET_DEST (XVECEXP (PATTERN (i2), 0, i))))
2711 for (temp = NEXT_INSN (i2);
2712 temp && (this_basic_block->next_bb == EXIT_BLOCK_PTR
2713 || BB_HEAD (this_basic_block) != temp);
2714 temp = NEXT_INSN (temp))
2715 if (temp != i3 && INSN_P (temp))
2716 for (link = LOG_LINKS (temp); link; link = XEXP (link, 1))
2717 if (XEXP (link, 0) == i2)
2718 XEXP (link, 0) = i3;
2723 while (XEXP (link, 1))
2724 link = XEXP (link, 1);
2725 XEXP (link, 1) = i2notes;
2739 INSN_CODE (i2) = i2_code_number;
2740 PATTERN (i2) = newi2pat;
2743 SET_INSN_DELETED (i2);
2749 SET_INSN_DELETED (i1);
2752 /* Get death notes for everything that is now used in either I3 or
2753 I2 and used to die in a previous insn. If we built two new
2754 patterns, move from I1 to I2 then I2 to I3 so that we get the
2755 proper movement on registers that I2 modifies. */
2759 move_deaths (newi2pat, NULL_RTX, INSN_CUID (i1), i2, &midnotes);
2760 move_deaths (newpat, newi2pat, INSN_CUID (i1), i3, &midnotes);
2763 move_deaths (newpat, NULL_RTX, i1 ? INSN_CUID (i1) : INSN_CUID (i2),
2766 /* Distribute all the LOG_LINKS and REG_NOTES from I1, I2, and I3. */
2768 distribute_notes (i3notes, i3, i3, newi2pat ? i2 : NULL_RTX);
2770 distribute_notes (i2notes, i2, i3, newi2pat ? i2 : NULL_RTX);
2772 distribute_notes (i1notes, i1, i3, newi2pat ? i2 : NULL_RTX);
2774 distribute_notes (midnotes, NULL_RTX, i3, newi2pat ? i2 : NULL_RTX);
2776 /* Distribute any notes added to I2 or I3 by recog_for_combine. We
2777 know these are REG_UNUSED and want them to go to the desired insn,
2778 so we always pass it as i3. We have not counted the notes in
2779 reg_n_deaths yet, so we need to do so now. */
2781 if (newi2pat && new_i2_notes)
2783 for (temp = new_i2_notes; temp; temp = XEXP (temp, 1))
2784 if (REG_P (XEXP (temp, 0)))
2785 REG_N_DEATHS (REGNO (XEXP (temp, 0)))++;
2787 distribute_notes (new_i2_notes, i2, i2, NULL_RTX);
2792 for (temp = new_i3_notes; temp; temp = XEXP (temp, 1))
2793 if (REG_P (XEXP (temp, 0)))
2794 REG_N_DEATHS (REGNO (XEXP (temp, 0)))++;
2796 distribute_notes (new_i3_notes, i3, i3, NULL_RTX);
2799 /* If I3DEST was used in I3SRC, it really died in I3. We may need to
2800 put a REG_DEAD note for it somewhere. If NEWI2PAT exists and sets
2801 I3DEST, the death must be somewhere before I2, not I3. If we passed I3
2802 in that case, it might delete I2. Similarly for I2 and I1.
2803 Show an additional death due to the REG_DEAD note we make here. If
2804 we discard it in distribute_notes, we will decrement it again. */
2808 if (REG_P (i3dest_killed))
2809 REG_N_DEATHS (REGNO (i3dest_killed))++;
2811 if (newi2pat && reg_set_p (i3dest_killed, newi2pat))
2812 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i3dest_killed,
2814 NULL_RTX, i2, NULL_RTX);
2816 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i3dest_killed,
2818 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX);
2821 if (i2dest_in_i2src)
2824 REG_N_DEATHS (REGNO (i2dest))++;
2826 if (newi2pat && reg_set_p (i2dest, newi2pat))
2827 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i2dest, NULL_RTX),
2828 NULL_RTX, i2, NULL_RTX);
2830 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i2dest, NULL_RTX),
2831 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX);
2834 if (i1dest_in_i1src)
2837 REG_N_DEATHS (REGNO (i1dest))++;
2839 if (newi2pat && reg_set_p (i1dest, newi2pat))
2840 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i1dest, NULL_RTX),
2841 NULL_RTX, i2, NULL_RTX);
2843 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i1dest, NULL_RTX),
2844 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX);
2847 distribute_links (i3links);
2848 distribute_links (i2links);
2849 distribute_links (i1links);
2854 rtx i2_insn = 0, i2_val = 0, set;
2856 /* The insn that used to set this register doesn't exist, and
2857 this life of the register may not exist either. See if one of
2858 I3's links points to an insn that sets I2DEST. If it does,
2859 that is now the last known value for I2DEST. If we don't update
2860 this and I2 set the register to a value that depended on its old
2861 contents, we will get confused. If this insn is used, thing
2862 will be set correctly in combine_instructions. */
2864 for (link = LOG_LINKS (i3); link; link = XEXP (link, 1))
2865 if ((set = single_set (XEXP (link, 0))) != 0
2866 && rtx_equal_p (i2dest, SET_DEST (set)))
2867 i2_insn = XEXP (link, 0), i2_val = SET_SRC (set);
2869 record_value_for_reg (i2dest, i2_insn, i2_val);
2871 /* If the reg formerly set in I2 died only once and that was in I3,
2872 zero its use count so it won't make `reload' do any work. */
2874 && (newi2pat == 0 || ! reg_mentioned_p (i2dest, newi2pat))
2875 && ! i2dest_in_i2src)
2877 regno = REGNO (i2dest);
2878 REG_N_SETS (regno)--;
2882 if (i1 && REG_P (i1dest))
2885 rtx i1_insn = 0, i1_val = 0, set;
2887 for (link = LOG_LINKS (i3); link; link = XEXP (link, 1))
2888 if ((set = single_set (XEXP (link, 0))) != 0
2889 && rtx_equal_p (i1dest, SET_DEST (set)))
2890 i1_insn = XEXP (link, 0), i1_val = SET_SRC (set);
2892 record_value_for_reg (i1dest, i1_insn, i1_val);
2894 regno = REGNO (i1dest);
2895 if (! added_sets_1 && ! i1dest_in_i1src)
2896 REG_N_SETS (regno)--;
2899 /* Update reg_stat[].nonzero_bits et al for any changes that may have
2900 been made to this insn. The order of
2901 set_nonzero_bits_and_sign_copies() is important. Because newi2pat
2902 can affect nonzero_bits of newpat */
2904 note_stores (newi2pat, set_nonzero_bits_and_sign_copies, NULL);
2905 note_stores (newpat, set_nonzero_bits_and_sign_copies, NULL);
2907 /* Set new_direct_jump_p if a new return or simple jump instruction
2910 If I3 is now an unconditional jump, ensure that it has a
2911 BARRIER following it since it may have initially been a
2912 conditional jump. It may also be the last nonnote insn. */
2914 if (returnjump_p (i3) || any_uncondjump_p (i3))
2916 *new_direct_jump_p = 1;
2917 mark_jump_label (PATTERN (i3), i3, 0);
2919 if ((temp = next_nonnote_insn (i3)) == NULL_RTX
2920 || !BARRIER_P (temp))
2921 emit_barrier_after (i3);
2924 if (undobuf.other_insn != NULL_RTX
2925 && (returnjump_p (undobuf.other_insn)
2926 || any_uncondjump_p (undobuf.other_insn)))
2928 *new_direct_jump_p = 1;
2930 if ((temp = next_nonnote_insn (undobuf.other_insn)) == NULL_RTX
2931 || !BARRIER_P (temp))
2932 emit_barrier_after (undobuf.other_insn);
2935 /* An NOOP jump does not need barrier, but it does need cleaning up
2937 if (GET_CODE (newpat) == SET
2938 && SET_SRC (newpat) == pc_rtx
2939 && SET_DEST (newpat) == pc_rtx)
2940 *new_direct_jump_p = 1;
2943 combine_successes++;
2946 if (added_links_insn
2947 && (newi2pat == 0 || INSN_CUID (added_links_insn) < INSN_CUID (i2))
2948 && INSN_CUID (added_links_insn) < INSN_CUID (i3))
2949 return added_links_insn;
2951 return newi2pat ? i2 : i3;
2954 /* Undo all the modifications recorded in undobuf. */
2959 struct undo *undo, *next;
2961 for (undo = undobuf.undos; undo; undo = next)
2965 *undo->where.i = undo->old_contents.i;
2967 *undo->where.r = undo->old_contents.r;
2969 undo->next = undobuf.frees;
2970 undobuf.frees = undo;
2976 /* We've committed to accepting the changes we made. Move all
2977 of the undos to the free list. */
2982 struct undo *undo, *next;
2984 for (undo = undobuf.undos; undo; undo = next)
2987 undo->next = undobuf.frees;
2988 undobuf.frees = undo;
2994 /* Find the innermost point within the rtx at LOC, possibly LOC itself,
2995 where we have an arithmetic expression and return that point. LOC will
2998 try_combine will call this function to see if an insn can be split into
3002 find_split_point (rtx *loc, rtx insn)
3005 enum rtx_code code = GET_CODE (x);
3007 unsigned HOST_WIDE_INT len = 0;
3008 HOST_WIDE_INT pos = 0;
3010 rtx inner = NULL_RTX;
3012 /* First special-case some codes. */
3016 #ifdef INSN_SCHEDULING
3017 /* If we are making a paradoxical SUBREG invalid, it becomes a split
3019 if (MEM_P (SUBREG_REG (x)))
3022 return find_split_point (&SUBREG_REG (x), insn);
3026 /* If we have (mem (const ..)) or (mem (symbol_ref ...)), split it
3027 using LO_SUM and HIGH. */
3028 if (GET_CODE (XEXP (x, 0)) == CONST
3029 || GET_CODE (XEXP (x, 0)) == SYMBOL_REF)
3032 gen_rtx_LO_SUM (Pmode,
3033 gen_rtx_HIGH (Pmode, XEXP (x, 0)),
3035 return &XEXP (XEXP (x, 0), 0);
3039 /* If we have a PLUS whose second operand is a constant and the
3040 address is not valid, perhaps will can split it up using
3041 the machine-specific way to split large constants. We use
3042 the first pseudo-reg (one of the virtual regs) as a placeholder;
3043 it will not remain in the result. */
3044 if (GET_CODE (XEXP (x, 0)) == PLUS
3045 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3046 && ! memory_address_p (GET_MODE (x), XEXP (x, 0)))
3048 rtx reg = regno_reg_rtx[FIRST_PSEUDO_REGISTER];
3049 rtx seq = split_insns (gen_rtx_SET (VOIDmode, reg, XEXP (x, 0)),
3052 /* This should have produced two insns, each of which sets our
3053 placeholder. If the source of the second is a valid address,
3054 we can make put both sources together and make a split point
3058 && NEXT_INSN (seq) != NULL_RTX
3059 && NEXT_INSN (NEXT_INSN (seq)) == NULL_RTX
3060 && NONJUMP_INSN_P (seq)
3061 && GET_CODE (PATTERN (seq)) == SET
3062 && SET_DEST (PATTERN (seq)) == reg
3063 && ! reg_mentioned_p (reg,
3064 SET_SRC (PATTERN (seq)))
3065 && NONJUMP_INSN_P (NEXT_INSN (seq))
3066 && GET_CODE (PATTERN (NEXT_INSN (seq))) == SET
3067 && SET_DEST (PATTERN (NEXT_INSN (seq))) == reg
3068 && memory_address_p (GET_MODE (x),
3069 SET_SRC (PATTERN (NEXT_INSN (seq)))))
3071 rtx src1 = SET_SRC (PATTERN (seq));
3072 rtx src2 = SET_SRC (PATTERN (NEXT_INSN (seq)));
3074 /* Replace the placeholder in SRC2 with SRC1. If we can
3075 find where in SRC2 it was placed, that can become our
3076 split point and we can replace this address with SRC2.
3077 Just try two obvious places. */
3079 src2 = replace_rtx (src2, reg, src1);
3081 if (XEXP (src2, 0) == src1)
3082 split = &XEXP (src2, 0);
3083 else if (GET_RTX_FORMAT (GET_CODE (XEXP (src2, 0)))[0] == 'e'
3084 && XEXP (XEXP (src2, 0), 0) == src1)
3085 split = &XEXP (XEXP (src2, 0), 0);
3089 SUBST (XEXP (x, 0), src2);
3094 /* If that didn't work, perhaps the first operand is complex and
3095 needs to be computed separately, so make a split point there.
3096 This will occur on machines that just support REG + CONST
3097 and have a constant moved through some previous computation. */
3099 else if (!OBJECT_P (XEXP (XEXP (x, 0), 0))
3100 && ! (GET_CODE (XEXP (XEXP (x, 0), 0)) == SUBREG
3101 && OBJECT_P (SUBREG_REG (XEXP (XEXP (x, 0), 0)))))
3102 return &XEXP (XEXP (x, 0), 0);
3108 /* If SET_DEST is CC0 and SET_SRC is not an operand, a COMPARE, or a
3109 ZERO_EXTRACT, the most likely reason why this doesn't match is that
3110 we need to put the operand into a register. So split at that
3113 if (SET_DEST (x) == cc0_rtx
3114 && GET_CODE (SET_SRC (x)) != COMPARE
3115 && GET_CODE (SET_SRC (x)) != ZERO_EXTRACT
3116 && !OBJECT_P (SET_SRC (x))
3117 && ! (GET_CODE (SET_SRC (x)) == SUBREG
3118 && OBJECT_P (SUBREG_REG (SET_SRC (x)))))
3119 return &SET_SRC (x);
3122 /* See if we can split SET_SRC as it stands. */
3123 split = find_split_point (&SET_SRC (x), insn);
3124 if (split && split != &SET_SRC (x))
3127 /* See if we can split SET_DEST as it stands. */
3128 split = find_split_point (&SET_DEST (x), insn);
3129 if (split && split != &SET_DEST (x))
3132 /* See if this is a bitfield assignment with everything constant. If
3133 so, this is an IOR of an AND, so split it into that. */
3134 if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
3135 && (GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0)))
3136 <= HOST_BITS_PER_WIDE_INT)
3137 && GET_CODE (XEXP (SET_DEST (x), 1)) == CONST_INT
3138 && GET_CODE (XEXP (SET_DEST (x), 2)) == CONST_INT
3139 && GET_CODE (SET_SRC (x)) == CONST_INT
3140 && ((INTVAL (XEXP (SET_DEST (x), 1))
3141 + INTVAL (XEXP (SET_DEST (x), 2)))
3142 <= GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0))))
3143 && ! side_effects_p (XEXP (SET_DEST (x), 0)))
3145 HOST_WIDE_INT pos = INTVAL (XEXP (SET_DEST (x), 2));
3146 unsigned HOST_WIDE_INT len = INTVAL (XEXP (SET_DEST (x), 1));
3147 unsigned HOST_WIDE_INT src = INTVAL (SET_SRC (x));
3148 rtx dest = XEXP (SET_DEST (x), 0);
3149 enum machine_mode mode = GET_MODE (dest);
3150 unsigned HOST_WIDE_INT mask = ((HOST_WIDE_INT) 1 << len) - 1;
3152 if (BITS_BIG_ENDIAN)
3153 pos = GET_MODE_BITSIZE (mode) - len - pos;
3157 gen_binary (IOR, mode, dest, GEN_INT (src << pos)));
3160 gen_binary (IOR, mode,
3161 gen_binary (AND, mode, dest,
3162 gen_int_mode (~(mask << pos),
3164 GEN_INT (src << pos)));
3166 SUBST (SET_DEST (x), dest);
3168 split = find_split_point (&SET_SRC (x), insn);
3169 if (split && split != &SET_SRC (x))
3173 /* Otherwise, see if this is an operation that we can split into two.
3174 If so, try to split that. */
3175 code = GET_CODE (SET_SRC (x));
3180 /* If we are AND'ing with a large constant that is only a single
3181 bit and the result is only being used in a context where we
3182 need to know if it is zero or nonzero, replace it with a bit
3183 extraction. This will avoid the large constant, which might
3184 have taken more than one insn to make. If the constant were
3185 not a valid argument to the AND but took only one insn to make,
3186 this is no worse, but if it took more than one insn, it will
3189 if (GET_CODE (XEXP (SET_SRC (x), 1)) == CONST_INT
3190 && REG_P (XEXP (SET_SRC (x), 0))
3191 && (pos = exact_log2 (INTVAL (XEXP (SET_SRC (x), 1)))) >= 7
3192 && REG_P (SET_DEST (x))
3193 && (split = find_single_use (SET_DEST (x), insn, (rtx*) 0)) != 0
3194 && (GET_CODE (*split) == EQ || GET_CODE (*split) == NE)
3195 && XEXP (*split, 0) == SET_DEST (x)
3196 && XEXP (*split, 1) == const0_rtx)
3198 rtx extraction = make_extraction (GET_MODE (SET_DEST (x)),
3199 XEXP (SET_SRC (x), 0),
3200 pos, NULL_RTX, 1, 1, 0, 0);
3201 if (extraction != 0)
3203 SUBST (SET_SRC (x), extraction);
3204 return find_split_point (loc, insn);
3210 /* If STORE_FLAG_VALUE is -1, this is (NE X 0) and only one bit of X
3211 is known to be on, this can be converted into a NEG of a shift. */
3212 if (STORE_FLAG_VALUE == -1 && XEXP (SET_SRC (x), 1) == const0_rtx
3213 && GET_MODE (SET_SRC (x)) == GET_MODE (XEXP (SET_SRC (x), 0))
3214 && 1 <= (pos = exact_log2
3215 (nonzero_bits (XEXP (SET_SRC (x), 0),
3216 GET_MODE (XEXP (SET_SRC (x), 0))))))
3218 enum machine_mode mode = GET_MODE (XEXP (SET_SRC (x), 0));
3222 gen_rtx_LSHIFTRT (mode,
3223 XEXP (SET_SRC (x), 0),
3226 split = find_split_point (&SET_SRC (x), insn);
3227 if (split && split != &SET_SRC (x))
3233 inner = XEXP (SET_SRC (x), 0);
3235 /* We can't optimize if either mode is a partial integer
3236 mode as we don't know how many bits are significant
3238 if (GET_MODE_CLASS (GET_MODE (inner)) == MODE_PARTIAL_INT
3239 || GET_MODE_CLASS (GET_MODE (SET_SRC (x))) == MODE_PARTIAL_INT)
3243 len = GET_MODE_BITSIZE (GET_MODE (inner));
3249 if (GET_CODE (XEXP (SET_SRC (x), 1)) == CONST_INT
3250 && GET_CODE (XEXP (SET_SRC (x), 2)) == CONST_INT)
3252 inner = XEXP (SET_SRC (x), 0);
3253 len = INTVAL (XEXP (SET_SRC (x), 1));
3254 pos = INTVAL (XEXP (SET_SRC (x), 2));
3256 if (BITS_BIG_ENDIAN)
3257 pos = GET_MODE_BITSIZE (GET_MODE (inner)) - len - pos;
3258 unsignedp = (code == ZERO_EXTRACT);
3266 if (len && pos >= 0 && pos + len <= GET_MODE_BITSIZE (GET_MODE (inner)))
3268 enum machine_mode mode = GET_MODE (SET_SRC (x));
3270 /* For unsigned, we have a choice of a shift followed by an
3271 AND or two shifts. Use two shifts for field sizes where the
3272 constant might be too large. We assume here that we can
3273 always at least get 8-bit constants in an AND insn, which is
3274 true for every current RISC. */
3276 if (unsignedp && len <= 8)
3281 (mode, gen_lowpart (mode, inner),
3283 GEN_INT (((HOST_WIDE_INT) 1 << len) - 1)));
3285 split = find_split_point (&SET_SRC (x), insn);
3286 if (split && split != &SET_SRC (x))
3293 (unsignedp ? LSHIFTRT : ASHIFTRT, mode,
3294 gen_rtx_ASHIFT (mode,
3295 gen_lowpart (mode, inner),
3296 GEN_INT (GET_MODE_BITSIZE (mode)
3298 GEN_INT (GET_MODE_BITSIZE (mode) - len)));
3300 split = find_split_point (&SET_SRC (x), insn);
3301 if (split && split != &SET_SRC (x))
3306 /* See if this is a simple operation with a constant as the second
3307 operand. It might be that this constant is out of range and hence
3308 could be used as a split point. */
3309 if (BINARY_P (SET_SRC (x))
3310 && CONSTANT_P (XEXP (SET_SRC (x), 1))
3311 && (OBJECT_P (XEXP (SET_SRC (x), 0))
3312 || (GET_CODE (XEXP (SET_SRC (x), 0)) == SUBREG
3313 && OBJECT_P (SUBREG_REG (XEXP (SET_SRC (x), 0))))))
3314 return &XEXP (SET_SRC (x), 1);
3316 /* Finally, see if this is a simple operation with its first operand
3317 not in a register. The operation might require this operand in a
3318 register, so return it as a split point. We can always do this
3319 because if the first operand were another operation, we would have
3320 already found it as a split point. */
3321 if ((BINARY_P (SET_SRC (x)) || UNARY_P (SET_SRC (x)))
3322 && ! register_operand (XEXP (SET_SRC (x), 0), VOIDmode))
3323 return &XEXP (SET_SRC (x), 0);
3329 /* We write NOR as (and (not A) (not B)), but if we don't have a NOR,
3330 it is better to write this as (not (ior A B)) so we can split it.
3331 Similarly for IOR. */
3332 if (GET_CODE (XEXP (x, 0)) == NOT && GET_CODE (XEXP (x, 1)) == NOT)
3335 gen_rtx_NOT (GET_MODE (x),
3336 gen_rtx_fmt_ee (code == IOR ? AND : IOR,
3338 XEXP (XEXP (x, 0), 0),
3339 XEXP (XEXP (x, 1), 0))));
3340 return find_split_point (loc, insn);
3343 /* Many RISC machines have a large set of logical insns. If the
3344 second operand is a NOT, put it first so we will try to split the
3345 other operand first. */
3346 if (GET_CODE (XEXP (x, 1)) == NOT)
3348 rtx tem = XEXP (x, 0);
3349 SUBST (XEXP (x, 0), XEXP (x, 1));
3350 SUBST (XEXP (x, 1), tem);
3358 /* Otherwise, select our actions depending on our rtx class. */
3359 switch (GET_RTX_CLASS (code))
3361 case RTX_BITFIELD_OPS: /* This is ZERO_EXTRACT and SIGN_EXTRACT. */
3363 split = find_split_point (&XEXP (x, 2), insn);
3366 /* ... fall through ... */
3368 case RTX_COMM_ARITH:
3370 case RTX_COMM_COMPARE:
3371 split = find_split_point (&XEXP (x, 1), insn);
3374 /* ... fall through ... */
3376 /* Some machines have (and (shift ...) ...) insns. If X is not
3377 an AND, but XEXP (X, 0) is, use it as our split point. */
3378 if (GET_CODE (x) != AND && GET_CODE (XEXP (x, 0)) == AND)
3379 return &XEXP (x, 0);
3381 split = find_split_point (&XEXP (x, 0), insn);
3387 /* Otherwise, we don't have a split point. */
3392 /* Throughout X, replace FROM with TO, and return the result.
3393 The result is TO if X is FROM;
3394 otherwise the result is X, but its contents may have been modified.
3395 If they were modified, a record was made in undobuf so that
3396 undo_all will (among other things) return X to its original state.
3398 If the number of changes necessary is too much to record to undo,
3399 the excess changes are not made, so the result is invalid.
3400 The changes already made can still be undone.
3401 undobuf.num_undo is incremented for such changes, so by testing that
3402 the caller can tell whether the result is valid.
3404 `n_occurrences' is incremented each time FROM is replaced.
3406 IN_DEST is nonzero if we are processing the SET_DEST of a SET.
3408 UNIQUE_COPY is nonzero if each substitution must be unique. We do this
3409 by copying if `n_occurrences' is nonzero. */
3412 subst (rtx x, rtx from, rtx to, int in_dest, int unique_copy)
3414 enum rtx_code code = GET_CODE (x);
3415 enum machine_mode op0_mode = VOIDmode;
3420 /* Two expressions are equal if they are identical copies of a shared
3421 RTX or if they are both registers with the same register number
3424 #define COMBINE_RTX_EQUAL_P(X,Y) \
3426 || (REG_P (X) && REG_P (Y) \
3427 && REGNO (X) == REGNO (Y) && GET_MODE (X) == GET_MODE (Y)))
3429 if (! in_dest && COMBINE_RTX_EQUAL_P (x, from))
3432 return (unique_copy && n_occurrences > 1 ? copy_rtx (to) : to);
3435 /* If X and FROM are the same register but different modes, they will
3436 not have been seen as equal above. However, flow.c will make a
3437 LOG_LINKS entry for that case. If we do nothing, we will try to
3438 rerecognize our original insn and, when it succeeds, we will
3439 delete the feeding insn, which is incorrect.
3441 So force this insn not to match in this (rare) case. */
3442 if (! in_dest && code == REG && REG_P (from)
3443 && REGNO (x) == REGNO (from))
3444 return gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
3446 /* If this is an object, we are done unless it is a MEM or LO_SUM, both
3447 of which may contain things that can be combined. */
3448 if (code != MEM && code != LO_SUM && OBJECT_P (x))
3451 /* It is possible to have a subexpression appear twice in the insn.
3452 Suppose that FROM is a register that appears within TO.
3453 Then, after that subexpression has been scanned once by `subst',
3454 the second time it is scanned, TO may be found. If we were
3455 to scan TO here, we would find FROM within it and create a
3456 self-referent rtl structure which is completely wrong. */
3457 if (COMBINE_RTX_EQUAL_P (x, to))
3460 /* Parallel asm_operands need special attention because all of the
3461 inputs are shared across the arms. Furthermore, unsharing the
3462 rtl results in recognition failures. Failure to handle this case
3463 specially can result in circular rtl.
3465 Solve this by doing a normal pass across the first entry of the
3466 parallel, and only processing the SET_DESTs of the subsequent
3469 if (code == PARALLEL
3470 && GET_CODE (XVECEXP (x, 0, 0)) == SET
3471 && GET_CODE (SET_SRC (XVECEXP (x, 0, 0))) == ASM_OPERANDS)
3473 new = subst (XVECEXP (x, 0, 0), from, to, 0, unique_copy);
3475 /* If this substitution failed, this whole thing fails. */
3476 if (GET_CODE (new) == CLOBBER
3477 && XEXP (new, 0) == const0_rtx)
3480 SUBST (XVECEXP (x, 0, 0), new);
3482 for (i = XVECLEN (x, 0) - 1; i >= 1; i--)
3484 rtx dest = SET_DEST (XVECEXP (x, 0, i));
3487 && GET_CODE (dest) != CC0
3488 && GET_CODE (dest) != PC)
3490 new = subst (dest, from, to, 0, unique_copy);
3492 /* If this substitution failed, this whole thing fails. */
3493 if (GET_CODE (new) == CLOBBER
3494 && XEXP (new, 0) == const0_rtx)
3497 SUBST (SET_DEST (XVECEXP (x, 0, i)), new);
3503 len = GET_RTX_LENGTH (code);
3504 fmt = GET_RTX_FORMAT (code);
3506 /* We don't need to process a SET_DEST that is a register, CC0,
3507 or PC, so set up to skip this common case. All other cases
3508 where we want to suppress replacing something inside a
3509 SET_SRC are handled via the IN_DEST operand. */
3511 && (REG_P (SET_DEST (x))
3512 || GET_CODE (SET_DEST (x)) == CC0
3513 || GET_CODE (SET_DEST (x)) == PC))
3516 /* Get the mode of operand 0 in case X is now a SIGN_EXTEND of a
3519 op0_mode = GET_MODE (XEXP (x, 0));
3521 for (i = 0; i < len; i++)
3526 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
3528 if (COMBINE_RTX_EQUAL_P (XVECEXP (x, i, j), from))
3530 new = (unique_copy && n_occurrences
3531 ? copy_rtx (to) : to);
3536 new = subst (XVECEXP (x, i, j), from, to, 0,
3539 /* If this substitution failed, this whole thing
3541 if (GET_CODE (new) == CLOBBER
3542 && XEXP (new, 0) == const0_rtx)
3546 SUBST (XVECEXP (x, i, j), new);
3549 else if (fmt[i] == 'e')
3551 /* If this is a register being set, ignore it. */
3554 && (code == SUBREG || code == STRICT_LOW_PART
3555 || code == ZERO_EXTRACT)
3560 else if (COMBINE_RTX_EQUAL_P (XEXP (x, i), from))
3562 /* In general, don't install a subreg involving two
3563 modes not tieable. It can worsen register
3564 allocation, and can even make invalid reload
3565 insns, since the reg inside may need to be copied
3566 from in the outside mode, and that may be invalid
3567 if it is an fp reg copied in integer mode.
3569 We allow two exceptions to this: It is valid if
3570 it is inside another SUBREG and the mode of that
3571 SUBREG and the mode of the inside of TO is
3572 tieable and it is valid if X is a SET that copies
3575 if (GET_CODE (to) == SUBREG
3576 && ! MODES_TIEABLE_P (GET_MODE (to),
3577 GET_MODE (SUBREG_REG (to)))
3578 && ! (code == SUBREG
3579 && MODES_TIEABLE_P (GET_MODE (x),
3580 GET_MODE (SUBREG_REG (to))))
3582 && ! (code == SET && i == 1 && XEXP (x, 0) == cc0_rtx)
3585 return gen_rtx_CLOBBER (VOIDmode, const0_rtx);
3587 #ifdef CANNOT_CHANGE_MODE_CLASS
3590 && REGNO (to) < FIRST_PSEUDO_REGISTER
3591 && REG_CANNOT_CHANGE_MODE_P (REGNO (to),
3594 return gen_rtx_CLOBBER (VOIDmode, const0_rtx);
3597 new = (unique_copy && n_occurrences ? copy_rtx (to) : to);
3601 /* If we are in a SET_DEST, suppress most cases unless we
3602 have gone inside a MEM, in which case we want to
3603 simplify the address. We assume here that things that
3604 are actually part of the destination have their inner
3605 parts in the first expression. This is true for SUBREG,
3606 STRICT_LOW_PART, and ZERO_EXTRACT, which are the only
3607 things aside from REG and MEM that should appear in a
3609 new = subst (XEXP (x, i), from, to,
3611 && (code == SUBREG || code == STRICT_LOW_PART
3612 || code == ZERO_EXTRACT))
3614 && i == 0), unique_copy);
3616 /* If we found that we will have to reject this combination,
3617 indicate that by returning the CLOBBER ourselves, rather than
3618 an expression containing it. This will speed things up as
3619 well as prevent accidents where two CLOBBERs are considered
3620 to be equal, thus producing an incorrect simplification. */
3622 if (GET_CODE (new) == CLOBBER && XEXP (new, 0) == const0_rtx)
3625 if (GET_CODE (x) == SUBREG
3626 && (GET_CODE (new) == CONST_INT
3627 || GET_CODE (new) == CONST_DOUBLE))
3629 enum machine_mode mode = GET_MODE (x);
3631 x = simplify_subreg (GET_MODE (x), new,
3632 GET_MODE (SUBREG_REG (x)),
3635 x = gen_rtx_CLOBBER (mode, const0_rtx);
3637 else if (GET_CODE (new) == CONST_INT
3638 && GET_CODE (x) == ZERO_EXTEND)
3640 x = simplify_unary_operation (ZERO_EXTEND, GET_MODE (x),
3641 new, GET_MODE (XEXP (x, 0)));
3646 SUBST (XEXP (x, i), new);
3651 /* Try to simplify X. If the simplification changed the code, it is likely
3652 that further simplification will help, so loop, but limit the number
3653 of repetitions that will be performed. */
3655 for (i = 0; i < 4; i++)
3657 /* If X is sufficiently simple, don't bother trying to do anything
3659 if (code != CONST_INT && code != REG && code != CLOBBER)
3660 x = combine_simplify_rtx (x, op0_mode, in_dest);
3662 if (GET_CODE (x) == code)
3665 code = GET_CODE (x);
3667 /* We no longer know the original mode of operand 0 since we
3668 have changed the form of X) */
3669 op0_mode = VOIDmode;
3675 /* Simplify X, a piece of RTL. We just operate on the expression at the
3676 outer level; call `subst' to simplify recursively. Return the new
3679 OP0_MODE is the original mode of XEXP (x, 0). IN_DEST is nonzero
3680 if we are inside a SET_DEST. */
3683 combine_simplify_rtx (rtx x, enum machine_mode op0_mode, int in_dest)
3685 enum rtx_code code = GET_CODE (x);
3686 enum machine_mode mode = GET_MODE (x);
3691 /* If this is a commutative operation, put a constant last and a complex
3692 expression first. We don't need to do this for comparisons here. */
3693 if (COMMUTATIVE_ARITH_P (x)
3694 && swap_commutative_operands_p (XEXP (x, 0), XEXP (x, 1)))
3697 SUBST (XEXP (x, 0), XEXP (x, 1));
3698 SUBST (XEXP (x, 1), temp);
3701 /* If this is a PLUS, MINUS, or MULT, and the first operand is the
3702 sign extension of a PLUS with a constant, reverse the order of the sign
3703 extension and the addition. Note that this not the same as the original
3704 code, but overflow is undefined for signed values. Also note that the
3705 PLUS will have been partially moved "inside" the sign-extension, so that
3706 the first operand of X will really look like:
3707 (ashiftrt (plus (ashift A C4) C5) C4).
3709 (plus (ashiftrt (ashift A C4) C2) C4)
3710 and replace the first operand of X with that expression. Later parts
3711 of this function may simplify the expression further.
3713 For example, if we start with (mult (sign_extend (plus A C1)) C2),
3714 we swap the SIGN_EXTEND and PLUS. Later code will apply the
3715 distributive law to produce (plus (mult (sign_extend X) C1) C3).
3717 We do this to simplify address expressions. */
3719 if ((code == PLUS || code == MINUS || code == MULT)
3720 && GET_CODE (XEXP (x, 0)) == ASHIFTRT
3721 && GET_CODE (XEXP (XEXP (x, 0), 0)) == PLUS
3722 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == ASHIFT
3723 && GET_CODE (XEXP (XEXP (XEXP (XEXP (x, 0), 0), 0), 1)) == CONST_INT
3724 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3725 && XEXP (XEXP (XEXP (XEXP (x, 0), 0), 0), 1) == XEXP (XEXP (x, 0), 1)
3726 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == CONST_INT
3727 && (temp = simplify_binary_operation (ASHIFTRT, mode,
3728 XEXP (XEXP (XEXP (x, 0), 0), 1),
3729 XEXP (XEXP (x, 0), 1))) != 0)
3732 = simplify_shift_const (NULL_RTX, ASHIFT, mode,
3733 XEXP (XEXP (XEXP (XEXP (x, 0), 0), 0), 0),
3734 INTVAL (XEXP (XEXP (x, 0), 1)));
3736 new = simplify_shift_const (NULL_RTX, ASHIFTRT, mode, new,
3737 INTVAL (XEXP (XEXP (x, 0), 1)));
3739 SUBST (XEXP (x, 0), gen_binary (PLUS, mode, new, temp));
3742 /* If this is a simple operation applied to an IF_THEN_ELSE, try
3743 applying it to the arms of the IF_THEN_ELSE. This often simplifies
3744 things. Check for cases where both arms are testing the same
3747 Don't do anything if all operands are very simple. */
3750 && ((!OBJECT_P (XEXP (x, 0))
3751 && ! (GET_CODE (XEXP (x, 0)) == SUBREG
3752 && OBJECT_P (SUBREG_REG (XEXP (x, 0)))))
3753 || (!OBJECT_P (XEXP (x, 1))
3754 && ! (GET_CODE (XEXP (x, 1)) == SUBREG
3755 && OBJECT_P (SUBREG_REG (XEXP (x, 1)))))))
3757 && (!OBJECT_P (XEXP (x, 0))
3758 && ! (GET_CODE (XEXP (x, 0)) == SUBREG
3759 && OBJECT_P (SUBREG_REG (XEXP (x, 0)))))))
3761 rtx cond, true_rtx, false_rtx;
3763 cond = if_then_else_cond (x, &true_rtx, &false_rtx);
3765 /* If everything is a comparison, what we have is highly unlikely
3766 to be simpler, so don't use it. */
3767 && ! (COMPARISON_P (x)
3768 && (COMPARISON_P (true_rtx) || COMPARISON_P (false_rtx))))
3770 rtx cop1 = const0_rtx;
3771 enum rtx_code cond_code = simplify_comparison (NE, &cond, &cop1);
3773 if (cond_code == NE && COMPARISON_P (cond))
3776 /* Simplify the alternative arms; this may collapse the true and
3777 false arms to store-flag values. Be careful to use copy_rtx
3778 here since true_rtx or false_rtx might share RTL with x as a
3779 result of the if_then_else_cond call above. */
3780 true_rtx = subst (copy_rtx (true_rtx), pc_rtx, pc_rtx, 0, 0);
3781 false_rtx = subst (copy_rtx (false_rtx), pc_rtx, pc_rtx, 0, 0);
3783 /* If true_rtx and false_rtx are not general_operands, an if_then_else
3784 is unlikely to be simpler. */
3785 if (general_operand (true_rtx, VOIDmode)
3786 && general_operand (false_rtx, VOIDmode))
3788 enum rtx_code reversed;
3790 /* Restarting if we generate a store-flag expression will cause
3791 us to loop. Just drop through in this case. */
3793 /* If the result values are STORE_FLAG_VALUE and zero, we can
3794 just make the comparison operation. */
3795 if (true_rtx == const_true_rtx && false_rtx == const0_rtx)
3796 x = gen_binary (cond_code, mode, cond, cop1);
3797 else if (true_rtx == const0_rtx && false_rtx == const_true_rtx
3798 && ((reversed = reversed_comparison_code_parts
3799 (cond_code, cond, cop1, NULL))
3801 x = gen_binary (reversed, mode, cond, cop1);
3803 /* Likewise, we can make the negate of a comparison operation
3804 if the result values are - STORE_FLAG_VALUE and zero. */
3805 else if (GET_CODE (true_rtx) == CONST_INT
3806 && INTVAL (true_rtx) == - STORE_FLAG_VALUE
3807 && false_rtx == const0_rtx)
3808 x = simplify_gen_unary (NEG, mode,
3809 gen_binary (cond_code, mode, cond,
3812 else if (GET_CODE (false_rtx) == CONST_INT
3813 && INTVAL (false_rtx) == - STORE_FLAG_VALUE
3814 && true_rtx == const0_rtx
3815 && ((reversed = reversed_comparison_code_parts
3816 (cond_code, cond, cop1, NULL))
3818 x = simplify_gen_unary (NEG, mode,
3819 gen_binary (reversed, mode,
3823 return gen_rtx_IF_THEN_ELSE (mode,
3824 gen_binary (cond_code, VOIDmode,
3826 true_rtx, false_rtx);
3828 code = GET_CODE (x);
3829 op0_mode = VOIDmode;
3834 /* Try to fold this expression in case we have constants that weren't
3837 switch (GET_RTX_CLASS (code))
3840 if (op0_mode == VOIDmode)
3841 op0_mode = GET_MODE (XEXP (x, 0));
3842 temp = simplify_unary_operation (code, mode, XEXP (x, 0), op0_mode);
3845 case RTX_COMM_COMPARE:
3847 enum machine_mode cmp_mode = GET_MODE (XEXP (x, 0));
3848 if (cmp_mode == VOIDmode)
3850 cmp_mode = GET_MODE (XEXP (x, 1));
3851 if (cmp_mode == VOIDmode)
3852 cmp_mode = op0_mode;
3854 temp = simplify_relational_operation (code, mode, cmp_mode,
3855 XEXP (x, 0), XEXP (x, 1));
3858 case RTX_COMM_ARITH:
3860 temp = simplify_binary_operation (code, mode, XEXP (x, 0), XEXP (x, 1));
3862 case RTX_BITFIELD_OPS:
3864 temp = simplify_ternary_operation (code, mode, op0_mode, XEXP (x, 0),
3865 XEXP (x, 1), XEXP (x, 2));
3874 code = GET_CODE (temp);
3875 op0_mode = VOIDmode;
3876 mode = GET_MODE (temp);
3879 /* First see if we can apply the inverse distributive law. */
3880 if (code == PLUS || code == MINUS
3881 || code == AND || code == IOR || code == XOR)
3883 x = apply_distributive_law (x);
3884 code = GET_CODE (x);
3885 op0_mode = VOIDmode;
3888 /* If CODE is an associative operation not otherwise handled, see if we
3889 can associate some operands. This can win if they are constants or
3890 if they are logically related (i.e. (a & b) & a). */
3891 if ((code == PLUS || code == MINUS || code == MULT || code == DIV
3892 || code == AND || code == IOR || code == XOR
3893 || code == SMAX || code == SMIN || code == UMAX || code == UMIN)
3894 && ((INTEGRAL_MODE_P (mode) && code != DIV)
3895 || (flag_unsafe_math_optimizations && FLOAT_MODE_P (mode))))
3897 if (GET_CODE (XEXP (x, 0)) == code)
3899 rtx other = XEXP (XEXP (x, 0), 0);
3900 rtx inner_op0 = XEXP (XEXP (x, 0), 1);
3901 rtx inner_op1 = XEXP (x, 1);
3904 /* Make sure we pass the constant operand if any as the second
3905 one if this is a commutative operation. */
3906 if (CONSTANT_P (inner_op0) && COMMUTATIVE_ARITH_P (x))
3908 rtx tem = inner_op0;
3909 inner_op0 = inner_op1;
3912 inner = simplify_binary_operation (code == MINUS ? PLUS
3913 : code == DIV ? MULT
3915 mode, inner_op0, inner_op1);
3917 /* For commutative operations, try the other pair if that one
3919 if (inner == 0 && COMMUTATIVE_ARITH_P (x))
3921 other = XEXP (XEXP (x, 0), 1);
3922 inner = simplify_binary_operation (code, mode,
3923 XEXP (XEXP (x, 0), 0),
3928 return gen_binary (code, mode, other, inner);
3932 /* A little bit of algebraic simplification here. */
3936 /* Ensure that our address has any ASHIFTs converted to MULT in case
3937 address-recognizing predicates are called later. */
3938 temp = make_compound_operation (XEXP (x, 0), MEM);
3939 SUBST (XEXP (x, 0), temp);
3943 if (op0_mode == VOIDmode)
3944 op0_mode = GET_MODE (SUBREG_REG (x));
3946 /* See if this can be moved to simplify_subreg. */
3947 if (CONSTANT_P (SUBREG_REG (x))
3948 && subreg_lowpart_offset (mode, op0_mode) == SUBREG_BYTE (x)
3949 /* Don't call gen_lowpart if the inner mode
3950 is VOIDmode and we cannot simplify it, as SUBREG without
3951 inner mode is invalid. */
3952 && (GET_MODE (SUBREG_REG (x)) != VOIDmode
3953 || gen_lowpart_common (mode, SUBREG_REG (x))))
3954 return gen_lowpart (mode, SUBREG_REG (x));
3956 if (GET_MODE_CLASS (GET_MODE (SUBREG_REG (x))) == MODE_CC)
3960 temp = simplify_subreg (mode, SUBREG_REG (x), op0_mode,
3966 /* Don't change the mode of the MEM if that would change the meaning
3968 if (MEM_P (SUBREG_REG (x))
3969 && (MEM_VOLATILE_P (SUBREG_REG (x))
3970 || mode_dependent_address_p (XEXP (SUBREG_REG (x), 0))))
3971 return gen_rtx_CLOBBER (mode, const0_rtx);
3973 /* Note that we cannot do any narrowing for non-constants since
3974 we might have been counting on using the fact that some bits were
3975 zero. We now do this in the SET. */
3980 if (GET_CODE (XEXP (x, 0)) == SUBREG
3981 && subreg_lowpart_p (XEXP (x, 0))
3982 && (GET_MODE_SIZE (GET_MODE (XEXP (x, 0)))
3983 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (x, 0)))))
3984 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == ASHIFT
3985 && XEXP (SUBREG_REG (XEXP (x, 0)), 0) == const1_rtx)
3987 enum machine_mode inner_mode = GET_MODE (SUBREG_REG (XEXP (x, 0)));
3989 x = gen_rtx_ROTATE (inner_mode,
3990 simplify_gen_unary (NOT, inner_mode, const1_rtx,
3992 XEXP (SUBREG_REG (XEXP (x, 0)), 1));
3993 return gen_lowpart (mode, x);
3996 /* Apply De Morgan's laws to reduce number of patterns for machines
3997 with negating logical insns (and-not, nand, etc.). If result has
3998 only one NOT, put it first, since that is how the patterns are
4001 if (GET_CODE (XEXP (x, 0)) == IOR || GET_CODE (XEXP (x, 0)) == AND)
4003 rtx in1 = XEXP (XEXP (x, 0), 0), in2 = XEXP (XEXP (x, 0), 1);
4004 enum machine_mode op_mode;
4006 op_mode = GET_MODE (in1);
4007 in1 = simplify_gen_unary (NOT, op_mode, in1, op_mode);
4009 op_mode = GET_MODE (in2);
4010 if (op_mode == VOIDmode)
4012 in2 = simplify_gen_unary (NOT, op_mode, in2, op_mode);
4014 if (GET_CODE (in2) == NOT && GET_CODE (in1) != NOT)
4017 in2 = in1; in1 = tem;
4020 return gen_rtx_fmt_ee (GET_CODE (XEXP (x, 0)) == IOR ? AND : IOR,
4026 /* (neg (xor A 1)) is (plus A -1) if A is known to be either 0 or 1. */
4027 if (GET_CODE (XEXP (x, 0)) == XOR
4028 && XEXP (XEXP (x, 0), 1) == const1_rtx
4029 && nonzero_bits (XEXP (XEXP (x, 0), 0), mode) == 1)
4030 return gen_binary (PLUS, mode, XEXP (XEXP (x, 0), 0), constm1_rtx);
4032 temp = expand_compound_operation (XEXP (x, 0));
4034 /* For C equal to the width of MODE minus 1, (neg (ashiftrt X C)) can be
4035 replaced by (lshiftrt X C). This will convert
4036 (neg (sign_extract X 1 Y)) to (zero_extract X 1 Y). */
4038 if (GET_CODE (temp) == ASHIFTRT
4039 && GET_CODE (XEXP (temp, 1)) == CONST_INT
4040 && INTVAL (XEXP (temp, 1)) == GET_MODE_BITSIZE (mode) - 1)
4041 return simplify_shift_const (temp, LSHIFTRT, mode, XEXP (temp, 0),
4042 INTVAL (XEXP (temp, 1)));
4044 /* If X has only a single bit that might be nonzero, say, bit I, convert
4045 (neg X) to (ashiftrt (ashift X C-I) C-I) where C is the bitsize of
4046 MODE minus 1. This will convert (neg (zero_extract X 1 Y)) to
4047 (sign_extract X 1 Y). But only do this if TEMP isn't a register
4048 or a SUBREG of one since we'd be making the expression more
4049 complex if it was just a register. */
4052 && ! (GET_CODE (temp) == SUBREG
4053 && REG_P (SUBREG_REG (temp)))
4054 && (i = exact_log2 (nonzero_bits (temp, mode))) >= 0)
4056 rtx temp1 = simplify_shift_const
4057 (NULL_RTX, ASHIFTRT, mode,
4058 simplify_shift_const (NULL_RTX, ASHIFT, mode, temp,
4059 GET_MODE_BITSIZE (mode) - 1 - i),
4060 GET_MODE_BITSIZE (mode) - 1 - i);
4062 /* If all we did was surround TEMP with the two shifts, we
4063 haven't improved anything, so don't use it. Otherwise,
4064 we are better off with TEMP1. */
4065 if (GET_CODE (temp1) != ASHIFTRT
4066 || GET_CODE (XEXP (temp1, 0)) != ASHIFT
4067 || XEXP (XEXP (temp1, 0), 0) != temp)
4073 /* We can't handle truncation to a partial integer mode here
4074 because we don't know the real bitsize of the partial
4076 if (GET_MODE_CLASS (mode) == MODE_PARTIAL_INT)
4079 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4080 && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode),
4081 GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))))
4083 force_to_mode (XEXP (x, 0), GET_MODE (XEXP (x, 0)),
4084 GET_MODE_MASK (mode), NULL_RTX, 0));
4086 /* (truncate:SI ({sign,zero}_extend:DI foo:SI)) == foo:SI. */
4087 if ((GET_CODE (XEXP (x, 0)) == SIGN_EXTEND
4088 || GET_CODE (XEXP (x, 0)) == ZERO_EXTEND)
4089 && GET_MODE (XEXP (XEXP (x, 0), 0)) == mode)
4090 return XEXP (XEXP (x, 0), 0);
4092 /* (truncate:SI (OP:DI ({sign,zero}_extend:DI foo:SI))) is
4093 (OP:SI foo:SI) if OP is NEG or ABS. */
4094 if ((GET_CODE (XEXP (x, 0)) == ABS
4095 || GET_CODE (XEXP (x, 0)) == NEG)
4096 && (GET_CODE (XEXP (XEXP (x, 0), 0)) == SIGN_EXTEND
4097 || GET_CODE (XEXP (XEXP (x, 0), 0)) == ZERO_EXTEND)
4098 && GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == mode)
4099 return simplify_gen_unary (GET_CODE (XEXP (x, 0)), mode,
4100 XEXP (XEXP (XEXP (x, 0), 0), 0), mode);
4102 /* (truncate:SI (subreg:DI (truncate:SI X) 0)) is
4104 if (GET_CODE (XEXP (x, 0)) == SUBREG
4105 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == TRUNCATE
4106 && subreg_lowpart_p (XEXP (x, 0)))
4107 return SUBREG_REG (XEXP (x, 0));
4109 /* If we know that the value is already truncated, we can
4110 replace the TRUNCATE with a SUBREG if TRULY_NOOP_TRUNCATION
4111 is nonzero for the corresponding modes. But don't do this
4112 for an (LSHIFTRT (MULT ...)) since this will cause problems
4113 with the umulXi3_highpart patterns. */
4114 if (TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode),
4115 GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))))
4116 && num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
4117 >= (unsigned int) (GET_MODE_BITSIZE (mode) + 1)
4118 && ! (GET_CODE (XEXP (x, 0)) == LSHIFTRT
4119 && GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT))
4120 return gen_lowpart (mode, XEXP (x, 0));
4122 /* A truncate of a comparison can be replaced with a subreg if
4123 STORE_FLAG_VALUE permits. This is like the previous test,
4124 but it works even if the comparison is done in a mode larger
4125 than HOST_BITS_PER_WIDE_INT. */
4126 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4127 && COMPARISON_P (XEXP (x, 0))
4128 && ((HOST_WIDE_INT) STORE_FLAG_VALUE & ~GET_MODE_MASK (mode)) == 0)
4129 return gen_lowpart (mode, XEXP (x, 0));
4131 /* Similarly, a truncate of a register whose value is a
4132 comparison can be replaced with a subreg if STORE_FLAG_VALUE
4134 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4135 && ((HOST_WIDE_INT) STORE_FLAG_VALUE & ~GET_MODE_MASK (mode)) == 0
4136 && (temp = get_last_value (XEXP (x, 0)))
4137 && COMPARISON_P (temp))
4138 return gen_lowpart (mode, XEXP (x, 0));
4142 case FLOAT_TRUNCATE:
4143 /* (float_truncate:SF (float_extend:DF foo:SF)) = foo:SF. */
4144 if (GET_CODE (XEXP (x, 0)) == FLOAT_EXTEND
4145 && GET_MODE (XEXP (XEXP (x, 0), 0)) == mode)
4146 return XEXP (XEXP (x, 0), 0);
4148 /* (float_truncate:SF (float_truncate:DF foo:XF))
4149 = (float_truncate:SF foo:XF).
4150 This may eliminate double rounding, so it is unsafe.
4152 (float_truncate:SF (float_extend:XF foo:DF))
4153 = (float_truncate:SF foo:DF).
4155 (float_truncate:DF (float_extend:XF foo:SF))
4156 = (float_extend:SF foo:DF). */
4157 if ((GET_CODE (XEXP (x, 0)) == FLOAT_TRUNCATE
4158 && flag_unsafe_math_optimizations)
4159 || GET_CODE (XEXP (x, 0)) == FLOAT_EXTEND)
4160 return simplify_gen_unary (GET_MODE_SIZE (GET_MODE (XEXP (XEXP (x, 0),
4162 > GET_MODE_SIZE (mode)
4163 ? FLOAT_TRUNCATE : FLOAT_EXTEND,
4165 XEXP (XEXP (x, 0), 0), mode);
4167 /* (float_truncate (float x)) is (float x) */
4168 if (GET_CODE (XEXP (x, 0)) == FLOAT
4169 && (flag_unsafe_math_optimizations
4170 || ((unsigned)significand_size (GET_MODE (XEXP (x, 0)))
4171 >= (GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (x, 0), 0)))
4172 - num_sign_bit_copies (XEXP (XEXP (x, 0), 0),
4173 GET_MODE (XEXP (XEXP (x, 0), 0)))))))
4174 return simplify_gen_unary (FLOAT, mode,
4175 XEXP (XEXP (x, 0), 0),
4176 GET_MODE (XEXP (XEXP (x, 0), 0)));
4178 /* (float_truncate:SF (OP:DF (float_extend:DF foo:sf))) is
4179 (OP:SF foo:SF) if OP is NEG or ABS. */
4180 if ((GET_CODE (XEXP (x, 0)) == ABS
4181 || GET_CODE (XEXP (x, 0)) == NEG)
4182 && GET_CODE (XEXP (XEXP (x, 0), 0)) == FLOAT_EXTEND
4183 && GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == mode)
4184 return simplify_gen_unary (GET_CODE (XEXP (x, 0)), mode,
4185 XEXP (XEXP (XEXP (x, 0), 0), 0), mode);
4187 /* (float_truncate:SF (subreg:DF (float_truncate:SF X) 0))
4188 is (float_truncate:SF x). */
4189 if (GET_CODE (XEXP (x, 0)) == SUBREG
4190 && subreg_lowpart_p (XEXP (x, 0))
4191 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == FLOAT_TRUNCATE)
4192 return SUBREG_REG (XEXP (x, 0));
4195 /* (float_extend (float_extend x)) is (float_extend x)
4197 (float_extend (float x)) is (float x) assuming that double
4198 rounding can't happen.
4200 if (GET_CODE (XEXP (x, 0)) == FLOAT_EXTEND
4201 || (GET_CODE (XEXP (x, 0)) == FLOAT
4202 && ((unsigned)significand_size (GET_MODE (XEXP (x, 0)))
4203 >= (GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (x, 0), 0)))
4204 - num_sign_bit_copies (XEXP (XEXP (x, 0), 0),
4205 GET_MODE (XEXP (XEXP (x, 0), 0)))))))
4206 return simplify_gen_unary (GET_CODE (XEXP (x, 0)), mode,
4207 XEXP (XEXP (x, 0), 0),
4208 GET_MODE (XEXP (XEXP (x, 0), 0)));
4213 /* Convert (compare FOO (const_int 0)) to FOO unless we aren't
4214 using cc0, in which case we want to leave it as a COMPARE
4215 so we can distinguish it from a register-register-copy. */
4216 if (XEXP (x, 1) == const0_rtx)
4219 /* x - 0 is the same as x unless x's mode has signed zeros and
4220 allows rounding towards -infinity. Under those conditions,
4222 if (!(HONOR_SIGNED_ZEROS (GET_MODE (XEXP (x, 0)))
4223 && HONOR_SIGN_DEPENDENT_ROUNDING (GET_MODE (XEXP (x, 0))))
4224 && XEXP (x, 1) == CONST0_RTX (GET_MODE (XEXP (x, 0))))
4230 /* (const (const X)) can become (const X). Do it this way rather than
4231 returning the inner CONST since CONST can be shared with a
4233 if (GET_CODE (XEXP (x, 0)) == CONST)
4234 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4239 /* Convert (lo_sum (high FOO) FOO) to FOO. This is necessary so we
4240 can add in an offset. find_split_point will split this address up
4241 again if it doesn't match. */
4242 if (GET_CODE (XEXP (x, 0)) == HIGH
4243 && rtx_equal_p (XEXP (XEXP (x, 0), 0), XEXP (x, 1)))
4249 /* Canonicalize (plus (mult (neg B) C) A) to (minus A (mult B C)).
4251 if (GET_CODE (XEXP (x, 0)) == MULT
4252 && GET_CODE (XEXP (XEXP (x, 0), 0)) == NEG)
4256 in1 = XEXP (XEXP (XEXP (x, 0), 0), 0);
4257 in2 = XEXP (XEXP (x, 0), 1);
4258 return gen_binary (MINUS, mode, XEXP (x, 1),
4259 gen_binary (MULT, mode, in1, in2));
4262 /* If we have (plus (plus (A const) B)), associate it so that CONST is
4263 outermost. That's because that's the way indexed addresses are
4264 supposed to appear. This code used to check many more cases, but
4265 they are now checked elsewhere. */
4266 if (GET_CODE (XEXP (x, 0)) == PLUS
4267 && CONSTANT_ADDRESS_P (XEXP (XEXP (x, 0), 1)))
4268 return gen_binary (PLUS, mode,
4269 gen_binary (PLUS, mode, XEXP (XEXP (x, 0), 0),
4271 XEXP (XEXP (x, 0), 1));
4273 /* (plus (xor (and <foo> (const_int pow2 - 1)) <c>) <-c>)
4274 when c is (const_int (pow2 + 1) / 2) is a sign extension of a
4275 bit-field and can be replaced by either a sign_extend or a
4276 sign_extract. The `and' may be a zero_extend and the two
4277 <c>, -<c> constants may be reversed. */
4278 if (GET_CODE (XEXP (x, 0)) == XOR
4279 && GET_CODE (XEXP (x, 1)) == CONST_INT
4280 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
4281 && INTVAL (XEXP (x, 1)) == -INTVAL (XEXP (XEXP (x, 0), 1))
4282 && ((i = exact_log2 (INTVAL (XEXP (XEXP (x, 0), 1)))) >= 0
4283 || (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0)
4284 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4285 && ((GET_CODE (XEXP (XEXP (x, 0), 0)) == AND
4286 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == CONST_INT
4287 && (INTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1))
4288 == ((HOST_WIDE_INT) 1 << (i + 1)) - 1))
4289 || (GET_CODE (XEXP (XEXP (x, 0), 0)) == ZERO_EXTEND
4290 && (GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)))
4291 == (unsigned int) i + 1))))
4292 return simplify_shift_const
4293 (NULL_RTX, ASHIFTRT, mode,
4294 simplify_shift_const (NULL_RTX, ASHIFT, mode,
4295 XEXP (XEXP (XEXP (x, 0), 0), 0),
4296 GET_MODE_BITSIZE (mode) - (i + 1)),
4297 GET_MODE_BITSIZE (mode) - (i + 1));
4299 /* (plus (comparison A B) C) can become (neg (rev-comp A B)) if
4300 C is 1 and STORE_FLAG_VALUE is -1 or if C is -1 and STORE_FLAG_VALUE
4301 is 1. This produces better code than the alternative immediately
4303 if (COMPARISON_P (XEXP (x, 0))
4304 && ((STORE_FLAG_VALUE == -1 && XEXP (x, 1) == const1_rtx)
4305 || (STORE_FLAG_VALUE == 1 && XEXP (x, 1) == constm1_rtx))
4306 && (reversed = reversed_comparison (XEXP (x, 0), mode,
4307 XEXP (XEXP (x, 0), 0),
4308 XEXP (XEXP (x, 0), 1))))
4310 simplify_gen_unary (NEG, mode, reversed, mode);
4312 /* If only the low-order bit of X is possibly nonzero, (plus x -1)
4313 can become (ashiftrt (ashift (xor x 1) C) C) where C is
4314 the bitsize of the mode - 1. This allows simplification of
4315 "a = (b & 8) == 0;" */
4316 if (XEXP (x, 1) == constm1_rtx
4317 && !REG_P (XEXP (x, 0))
4318 && ! (GET_CODE (XEXP (x, 0)) == SUBREG
4319 && REG_P (SUBREG_REG (XEXP (x, 0))))
4320 && nonzero_bits (XEXP (x, 0), mode) == 1)
4321 return simplify_shift_const (NULL_RTX, ASHIFTRT, mode,
4322 simplify_shift_const (NULL_RTX, ASHIFT, mode,
4323 gen_rtx_XOR (mode, XEXP (x, 0), const1_rtx),
4324 GET_MODE_BITSIZE (mode) - 1),
4325 GET_MODE_BITSIZE (mode) - 1);
4327 /* If we are adding two things that have no bits in common, convert
4328 the addition into an IOR. This will often be further simplified,
4329 for example in cases like ((a & 1) + (a & 2)), which can
4332 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4333 && (nonzero_bits (XEXP (x, 0), mode)
4334 & nonzero_bits (XEXP (x, 1), mode)) == 0)
4336 /* Try to simplify the expression further. */
4337 rtx tor = gen_binary (IOR, mode, XEXP (x, 0), XEXP (x, 1));
4338 temp = combine_simplify_rtx (tor, mode, in_dest);
4340 /* If we could, great. If not, do not go ahead with the IOR
4341 replacement, since PLUS appears in many special purpose
4342 address arithmetic instructions. */
4343 if (GET_CODE (temp) != CLOBBER && temp != tor)
4349 /* If STORE_FLAG_VALUE is 1, (minus 1 (comparison foo bar)) can be done
4350 by reversing the comparison code if valid. */
4351 if (STORE_FLAG_VALUE == 1
4352 && XEXP (x, 0) == const1_rtx
4353 && COMPARISON_P (XEXP (x, 1))
4354 && (reversed = reversed_comparison (XEXP (x, 1), mode,
4355 XEXP (XEXP (x, 1), 0),
4356 XEXP (XEXP (x, 1), 1))))
4359 /* (minus <foo> (and <foo> (const_int -pow2))) becomes
4360 (and <foo> (const_int pow2-1)) */
4361 if (GET_CODE (XEXP (x, 1)) == AND
4362 && GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT
4363 && exact_log2 (-INTVAL (XEXP (XEXP (x, 1), 1))) >= 0
4364 && rtx_equal_p (XEXP (XEXP (x, 1), 0), XEXP (x, 0)))
4365 return simplify_and_const_int (NULL_RTX, mode, XEXP (x, 0),
4366 -INTVAL (XEXP (XEXP (x, 1), 1)) - 1);
4368 /* Canonicalize (minus A (mult (neg B) C)) to (plus (mult B C) A).
4370 if (GET_CODE (XEXP (x, 1)) == MULT
4371 && GET_CODE (XEXP (XEXP (x, 1), 0)) == NEG)
4375 in1 = XEXP (XEXP (XEXP (x, 1), 0), 0);
4376 in2 = XEXP (XEXP (x, 1), 1);
4377 return gen_binary (PLUS, mode, gen_binary (MULT, mode, in1, in2),
4381 /* Canonicalize (minus (neg A) (mult B C)) to
4382 (minus (mult (neg B) C) A). */
4383 if (GET_CODE (XEXP (x, 1)) == MULT
4384 && GET_CODE (XEXP (x, 0)) == NEG)
4388 in1 = simplify_gen_unary (NEG, mode, XEXP (XEXP (x, 1), 0), mode);
4389 in2 = XEXP (XEXP (x, 1), 1);
4390 return gen_binary (MINUS, mode, gen_binary (MULT, mode, in1, in2),
4391 XEXP (XEXP (x, 0), 0));
4394 /* Canonicalize (minus A (plus B C)) to (minus (minus A B) C) for
4396 if (GET_CODE (XEXP (x, 1)) == PLUS && INTEGRAL_MODE_P (mode))
4397 return gen_binary (MINUS, mode,
4398 gen_binary (MINUS, mode, XEXP (x, 0),
4399 XEXP (XEXP (x, 1), 0)),
4400 XEXP (XEXP (x, 1), 1));
4404 /* If we have (mult (plus A B) C), apply the distributive law and then
4405 the inverse distributive law to see if things simplify. This
4406 occurs mostly in addresses, often when unrolling loops. */
4408 if (GET_CODE (XEXP (x, 0)) == PLUS)
4410 x = apply_distributive_law
4411 (gen_binary (PLUS, mode,
4412 gen_binary (MULT, mode,
4413 XEXP (XEXP (x, 0), 0), XEXP (x, 1)),
4414 gen_binary (MULT, mode,
4415 XEXP (XEXP (x, 0), 1),
4416 copy_rtx (XEXP (x, 1)))));
4418 if (GET_CODE (x) != MULT)
4421 /* Try simplify a*(b/c) as (a*b)/c. */
4422 if (FLOAT_MODE_P (mode) && flag_unsafe_math_optimizations
4423 && GET_CODE (XEXP (x, 0)) == DIV)
4425 rtx tem = simplify_binary_operation (MULT, mode,
4426 XEXP (XEXP (x, 0), 0),
4429 return gen_binary (DIV, mode, tem, XEXP (XEXP (x, 0), 1));
4434 /* If this is a divide by a power of two, treat it as a shift if
4435 its first operand is a shift. */
4436 if (GET_CODE (XEXP (x, 1)) == CONST_INT
4437 && (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0
4438 && (GET_CODE (XEXP (x, 0)) == ASHIFT
4439 || GET_CODE (XEXP (x, 0)) == LSHIFTRT
4440 || GET_CODE (XEXP (x, 0)) == ASHIFTRT
4441 || GET_CODE (XEXP (x, 0)) == ROTATE
4442 || GET_CODE (XEXP (x, 0)) == ROTATERT))
4443 return simplify_shift_const (NULL_RTX, LSHIFTRT, mode, XEXP (x, 0), i);
4447 case GT: case GTU: case GE: case GEU:
4448 case LT: case LTU: case LE: case LEU:
4449 case UNEQ: case LTGT:
4450 case UNGT: case UNGE:
4451 case UNLT: case UNLE:
4452 case UNORDERED: case ORDERED:
4453 /* If the first operand is a condition code, we can't do anything
4455 if (GET_CODE (XEXP (x, 0)) == COMPARE
4456 || (GET_MODE_CLASS (GET_MODE (XEXP (x, 0))) != MODE_CC
4457 && ! CC0_P (XEXP (x, 0))))
4459 rtx op0 = XEXP (x, 0);
4460 rtx op1 = XEXP (x, 1);
4461 enum rtx_code new_code;
4463 if (GET_CODE (op0) == COMPARE)
4464 op1 = XEXP (op0, 1), op0 = XEXP (op0, 0);
4466 /* Simplify our comparison, if possible. */
4467 new_code = simplify_comparison (code, &op0, &op1);
4469 /* If STORE_FLAG_VALUE is 1, we can convert (ne x 0) to simply X
4470 if only the low-order bit is possibly nonzero in X (such as when
4471 X is a ZERO_EXTRACT of one bit). Similarly, we can convert EQ to
4472 (xor X 1) or (minus 1 X); we use the former. Finally, if X is
4473 known to be either 0 or -1, NE becomes a NEG and EQ becomes
4476 Remove any ZERO_EXTRACT we made when thinking this was a
4477 comparison. It may now be simpler to use, e.g., an AND. If a
4478 ZERO_EXTRACT is indeed appropriate, it will be placed back by
4479 the call to make_compound_operation in the SET case. */
4481 if (STORE_FLAG_VALUE == 1
4482 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4483 && op1 == const0_rtx
4484 && mode == GET_MODE (op0)
4485 && nonzero_bits (op0, mode) == 1)
4486 return gen_lowpart (mode,
4487 expand_compound_operation (op0));
4489 else if (STORE_FLAG_VALUE == 1
4490 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4491 && op1 == const0_rtx
4492 && mode == GET_MODE (op0)
4493 && (num_sign_bit_copies (op0, mode)
4494 == GET_MODE_BITSIZE (mode)))
4496 op0 = expand_compound_operation (op0);
4497 return simplify_gen_unary (NEG, mode,
4498 gen_lowpart (mode, op0),
4502 else if (STORE_FLAG_VALUE == 1
4503 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
4504 && op1 == const0_rtx
4505 && mode == GET_MODE (op0)
4506 && nonzero_bits (op0, mode) == 1)
4508 op0 = expand_compound_operation (op0);
4509 return gen_binary (XOR, mode,
4510 gen_lowpart (mode, op0),
4514 else if (STORE_FLAG_VALUE == 1
4515 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
4516 && op1 == const0_rtx
4517 && mode == GET_MODE (op0)
4518 && (num_sign_bit_copies (op0, mode)
4519 == GET_MODE_BITSIZE (mode)))
4521 op0 = expand_compound_operation (op0);
4522 return plus_constant (gen_lowpart (mode, op0), 1);
4525 /* If STORE_FLAG_VALUE is -1, we have cases similar to
4527 if (STORE_FLAG_VALUE == -1
4528 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4529 && op1 == const0_rtx
4530 && (num_sign_bit_copies (op0, mode)
4531 == GET_MODE_BITSIZE (mode)))
4532 return gen_lowpart (mode,
4533 expand_compound_operation (op0));
4535 else if (STORE_FLAG_VALUE == -1
4536 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4537 && op1 == const0_rtx
4538 && mode == GET_MODE (op0)
4539 && nonzero_bits (op0, mode) == 1)
4541 op0 = expand_compound_operation (op0);
4542 return simplify_gen_unary (NEG, mode,
4543 gen_lowpart (mode, op0),
4547 else if (STORE_FLAG_VALUE == -1
4548 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
4549 && op1 == const0_rtx
4550 && mode == GET_MODE (op0)
4551 && (num_sign_bit_copies (op0, mode)
4552 == GET_MODE_BITSIZE (mode)))
4554 op0 = expand_compound_operation (op0);
4555 return simplify_gen_unary (NOT, mode,
4556 gen_lowpart (mode, op0),
4560 /* If X is 0/1, (eq X 0) is X-1. */
4561 else if (STORE_FLAG_VALUE == -1
4562 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
4563 && op1 == const0_rtx
4564 && mode == GET_MODE (op0)
4565 && nonzero_bits (op0, mode) == 1)
4567 op0 = expand_compound_operation (op0);
4568 return plus_constant (gen_lowpart (mode, op0), -1);
4571 /* If STORE_FLAG_VALUE says to just test the sign bit and X has just
4572 one bit that might be nonzero, we can convert (ne x 0) to
4573 (ashift x c) where C puts the bit in the sign bit. Remove any
4574 AND with STORE_FLAG_VALUE when we are done, since we are only
4575 going to test the sign bit. */
4576 if (new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4577 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4578 && ((STORE_FLAG_VALUE & GET_MODE_MASK (mode))
4579 == (unsigned HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (mode) - 1))
4580 && op1 == const0_rtx
4581 && mode == GET_MODE (op0)
4582 && (i = exact_log2 (nonzero_bits (op0, mode))) >= 0)
4584 x = simplify_shift_const (NULL_RTX, ASHIFT, mode,
4585 expand_compound_operation (op0),
4586 GET_MODE_BITSIZE (mode) - 1 - i);
4587 if (GET_CODE (x) == AND && XEXP (x, 1) == const_true_rtx)
4593 /* If the code changed, return a whole new comparison. */
4594 if (new_code != code)
4595 return gen_rtx_fmt_ee (new_code, mode, op0, op1);
4597 /* Otherwise, keep this operation, but maybe change its operands.
4598 This also converts (ne (compare FOO BAR) 0) to (ne FOO BAR). */
4599 SUBST (XEXP (x, 0), op0);
4600 SUBST (XEXP (x, 1), op1);
4605 return simplify_if_then_else (x);
4611 /* If we are processing SET_DEST, we are done. */
4615 return expand_compound_operation (x);
4618 return simplify_set (x);
4623 return simplify_logical (x);
4626 /* (abs (neg <foo>)) -> (abs <foo>) */
4627 if (GET_CODE (XEXP (x, 0)) == NEG)
4628 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4630 /* If the mode of the operand is VOIDmode (i.e. if it is ASM_OPERANDS),
4632 if (GET_MODE (XEXP (x, 0)) == VOIDmode)
4635 /* If operand is something known to be positive, ignore the ABS. */
4636 if (GET_CODE (XEXP (x, 0)) == FFS || GET_CODE (XEXP (x, 0)) == ABS
4637 || ((GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
4638 <= HOST_BITS_PER_WIDE_INT)
4639 && ((nonzero_bits (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
4640 & ((HOST_WIDE_INT) 1
4641 << (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - 1)))
4645 /* If operand is known to be only -1 or 0, convert ABS to NEG. */
4646 if (num_sign_bit_copies (XEXP (x, 0), mode) == GET_MODE_BITSIZE (mode))
4647 return gen_rtx_NEG (mode, XEXP (x, 0));
4652 /* (ffs (*_extend <X>)) = (ffs <X>) */
4653 if (GET_CODE (XEXP (x, 0)) == SIGN_EXTEND
4654 || GET_CODE (XEXP (x, 0)) == ZERO_EXTEND)
4655 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4660 /* (pop* (zero_extend <X>)) = (pop* <X>) */
4661 if (GET_CODE (XEXP (x, 0)) == ZERO_EXTEND)
4662 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4666 /* (float (sign_extend <X>)) = (float <X>). */
4667 if (GET_CODE (XEXP (x, 0)) == SIGN_EXTEND)
4668 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4676 /* If this is a shift by a constant amount, simplify it. */
4677 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
4678 return simplify_shift_const (x, code, mode, XEXP (x, 0),
4679 INTVAL (XEXP (x, 1)));
4681 else if (SHIFT_COUNT_TRUNCATED && !REG_P (XEXP (x, 1)))
4683 force_to_mode (XEXP (x, 1), GET_MODE (XEXP (x, 1)),
4685 << exact_log2 (GET_MODE_BITSIZE (GET_MODE (x))))
4692 rtx op0 = XEXP (x, 0);
4693 rtx op1 = XEXP (x, 1);
4696 if (GET_CODE (op1) != PARALLEL)
4698 len = XVECLEN (op1, 0);
4700 && GET_CODE (XVECEXP (op1, 0, 0)) == CONST_INT
4701 && GET_CODE (op0) == VEC_CONCAT)
4703 int offset = INTVAL (XVECEXP (op1, 0, 0)) * GET_MODE_SIZE (GET_MODE (x));
4705 /* Try to find the element in the VEC_CONCAT. */
4708 if (GET_MODE (op0) == GET_MODE (x))
4710 if (GET_CODE (op0) == VEC_CONCAT)
4712 HOST_WIDE_INT op0_size = GET_MODE_SIZE (GET_MODE (XEXP (op0, 0)));
4713 if (op0_size < offset)
4714 op0 = XEXP (op0, 0);
4718 op0 = XEXP (op0, 1);
4736 /* Simplify X, an IF_THEN_ELSE expression. Return the new expression. */
4739 simplify_if_then_else (rtx x)
4741 enum machine_mode mode = GET_MODE (x);
4742 rtx cond = XEXP (x, 0);
4743 rtx true_rtx = XEXP (x, 1);
4744 rtx false_rtx = XEXP (x, 2);
4745 enum rtx_code true_code = GET_CODE (cond);
4746 int comparison_p = COMPARISON_P (cond);
4749 enum rtx_code false_code;
4752 /* Simplify storing of the truth value. */
4753 if (comparison_p && true_rtx == const_true_rtx && false_rtx == const0_rtx)
4754 return gen_binary (true_code, mode, XEXP (cond, 0), XEXP (cond, 1));
4756 /* Also when the truth value has to be reversed. */
4758 && true_rtx == const0_rtx && false_rtx == const_true_rtx
4759 && (reversed = reversed_comparison (cond, mode, XEXP (cond, 0),
4763 /* Sometimes we can simplify the arm of an IF_THEN_ELSE if a register used
4764 in it is being compared against certain values. Get the true and false
4765 comparisons and see if that says anything about the value of each arm. */
4768 && ((false_code = combine_reversed_comparison_code (cond))
4770 && REG_P (XEXP (cond, 0)))
4773 rtx from = XEXP (cond, 0);
4774 rtx true_val = XEXP (cond, 1);
4775 rtx false_val = true_val;
4778 /* If FALSE_CODE is EQ, swap the codes and arms. */
4780 if (false_code == EQ)
4782 swapped = 1, true_code = EQ, false_code = NE;
4783 temp = true_rtx, true_rtx = false_rtx, false_rtx = temp;
4786 /* If we are comparing against zero and the expression being tested has
4787 only a single bit that might be nonzero, that is its value when it is
4788 not equal to zero. Similarly if it is known to be -1 or 0. */
4790 if (true_code == EQ && true_val == const0_rtx
4791 && exact_log2 (nzb = nonzero_bits (from, GET_MODE (from))) >= 0)
4792 false_code = EQ, false_val = GEN_INT (nzb);
4793 else if (true_code == EQ && true_val == const0_rtx
4794 && (num_sign_bit_copies (from, GET_MODE (from))
4795 == GET_MODE_BITSIZE (GET_MODE (from))))
4796 false_code = EQ, false_val = constm1_rtx;
4798 /* Now simplify an arm if we know the value of the register in the
4799 branch and it is used in the arm. Be careful due to the potential
4800 of locally-shared RTL. */
4802 if (reg_mentioned_p (from, true_rtx))
4803 true_rtx = subst (known_cond (copy_rtx (true_rtx), true_code,
4805 pc_rtx, pc_rtx, 0, 0);
4806 if (reg_mentioned_p (from, false_rtx))
4807 false_rtx = subst (known_cond (copy_rtx (false_rtx), false_code,
4809 pc_rtx, pc_rtx, 0, 0);
4811 SUBST (XEXP (x, 1), swapped ? false_rtx : true_rtx);
4812 SUBST (XEXP (x, 2), swapped ? true_rtx : false_rtx);
4814 true_rtx = XEXP (x, 1);
4815 false_rtx = XEXP (x, 2);
4816 true_code = GET_CODE (cond);
4819 /* If we have (if_then_else FOO (pc) (label_ref BAR)) and FOO can be
4820 reversed, do so to avoid needing two sets of patterns for
4821 subtract-and-branch insns. Similarly if we have a constant in the true
4822 arm, the false arm is the same as the first operand of the comparison, or
4823 the false arm is more complicated than the true arm. */
4826 && combine_reversed_comparison_code (cond) != UNKNOWN
4827 && (true_rtx == pc_rtx
4828 || (CONSTANT_P (true_rtx)
4829 && GET_CODE (false_rtx) != CONST_INT && false_rtx != pc_rtx)
4830 || true_rtx == const0_rtx
4831 || (OBJECT_P (true_rtx) && !OBJECT_P (false_rtx))
4832 || (GET_CODE (true_rtx) == SUBREG && OBJECT_P (SUBREG_REG (true_rtx))
4833 && !OBJECT_P (false_rtx))
4834 || reg_mentioned_p (true_rtx, false_rtx)
4835 || rtx_equal_p (false_rtx, XEXP (cond, 0))))
4837 true_code = reversed_comparison_code (cond, NULL);
4839 reversed_comparison (cond, GET_MODE (cond), XEXP (cond, 0),
4842 SUBST (XEXP (x, 1), false_rtx);
4843 SUBST (XEXP (x, 2), true_rtx);
4845 temp = true_rtx, true_rtx = false_rtx, false_rtx = temp;
4848 /* It is possible that the conditional has been simplified out. */
4849 true_code = GET_CODE (cond);
4850 comparison_p = COMPARISON_P (cond);
4853 /* If the two arms are identical, we don't need the comparison. */
4855 if (rtx_equal_p (true_rtx, false_rtx) && ! side_effects_p (cond))
4858 /* Convert a == b ? b : a to "a". */
4859 if (true_code == EQ && ! side_effects_p (cond)
4860 && !HONOR_NANS (mode)
4861 && rtx_equal_p (XEXP (cond, 0), false_rtx)
4862 && rtx_equal_p (XEXP (cond, 1), true_rtx))
4864 else if (true_code == NE && ! side_effects_p (cond)
4865 && !HONOR_NANS (mode)
4866 && rtx_equal_p (XEXP (cond, 0), true_rtx)
4867 && rtx_equal_p (XEXP (cond, 1), false_rtx))
4870 /* Look for cases where we have (abs x) or (neg (abs X)). */
4872 if (GET_MODE_CLASS (mode) == MODE_INT
4873 && GET_CODE (false_rtx) == NEG
4874 && rtx_equal_p (true_rtx, XEXP (false_rtx, 0))
4876 && rtx_equal_p (true_rtx, XEXP (cond, 0))
4877 && ! side_effects_p (true_rtx))
4882 return simplify_gen_unary (ABS, mode, true_rtx, mode);
4886 simplify_gen_unary (NEG, mode,
4887 simplify_gen_unary (ABS, mode, true_rtx, mode),
4893 /* Look for MIN or MAX. */
4895 if ((! FLOAT_MODE_P (mode) || flag_unsafe_math_optimizations)
4897 && rtx_equal_p (XEXP (cond, 0), true_rtx)
4898 && rtx_equal_p (XEXP (cond, 1), false_rtx)
4899 && ! side_effects_p (cond))
4904 return gen_binary (SMAX, mode, true_rtx, false_rtx);
4907 return gen_binary (SMIN, mode, true_rtx, false_rtx);
4910 return gen_binary (UMAX, mode, true_rtx, false_rtx);
4913 return gen_binary (UMIN, mode, true_rtx, false_rtx);
4918 /* If we have (if_then_else COND (OP Z C1) Z) and OP is an identity when its
4919 second operand is zero, this can be done as (OP Z (mult COND C2)) where
4920 C2 = C1 * STORE_FLAG_VALUE. Similarly if OP has an outer ZERO_EXTEND or
4921 SIGN_EXTEND as long as Z is already extended (so we don't destroy it).
4922 We can do this kind of thing in some cases when STORE_FLAG_VALUE is
4923 neither 1 or -1, but it isn't worth checking for. */
4925 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
4927 && GET_MODE_CLASS (mode) == MODE_INT
4928 && ! side_effects_p (x))
4930 rtx t = make_compound_operation (true_rtx, SET);
4931 rtx f = make_compound_operation (false_rtx, SET);
4932 rtx cond_op0 = XEXP (cond, 0);
4933 rtx cond_op1 = XEXP (cond, 1);
4934 enum rtx_code op = UNKNOWN, extend_op = UNKNOWN;
4935 enum machine_mode m = mode;
4936 rtx z = 0, c1 = NULL_RTX;
4938 if ((GET_CODE (t) == PLUS || GET_CODE (t) == MINUS
4939 || GET_CODE (t) == IOR || GET_CODE (t) == XOR
4940 || GET_CODE (t) == ASHIFT
4941 || GET_CODE (t) == LSHIFTRT || GET_CODE (t) == ASHIFTRT)
4942 && rtx_equal_p (XEXP (t, 0), f))
4943 c1 = XEXP (t, 1), op = GET_CODE (t), z = f;
4945 /* If an identity-zero op is commutative, check whether there
4946 would be a match if we swapped the operands. */
4947 else if ((GET_CODE (t) == PLUS || GET_CODE (t) == IOR
4948 || GET_CODE (t) == XOR)
4949 && rtx_equal_p (XEXP (t, 1), f))
4950 c1 = XEXP (t, 0), op = GET_CODE (t), z = f;
4951 else if (GET_CODE (t) == SIGN_EXTEND
4952 && (GET_CODE (XEXP (t, 0)) == PLUS
4953 || GET_CODE (XEXP (t, 0)) == MINUS
4954 || GET_CODE (XEXP (t, 0)) == IOR
4955 || GET_CODE (XEXP (t, 0)) == XOR
4956 || GET_CODE (XEXP (t, 0)) == ASHIFT
4957 || GET_CODE (XEXP (t, 0)) == LSHIFTRT
4958 || GET_CODE (XEXP (t, 0)) == ASHIFTRT)
4959 && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG
4960 && subreg_lowpart_p (XEXP (XEXP (t, 0), 0))
4961 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f)
4962 && (num_sign_bit_copies (f, GET_MODE (f))
4964 (GET_MODE_BITSIZE (mode)
4965 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t, 0), 0))))))
4967 c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0));
4968 extend_op = SIGN_EXTEND;
4969 m = GET_MODE (XEXP (t, 0));
4971 else if (GET_CODE (t) == SIGN_EXTEND
4972 && (GET_CODE (XEXP (t, 0)) == PLUS
4973 || GET_CODE (XEXP (t, 0)) == IOR
4974 || GET_CODE (XEXP (t, 0)) == XOR)
4975 && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG
4976 && subreg_lowpart_p (XEXP (XEXP (t, 0), 1))
4977 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f)
4978 && (num_sign_bit_copies (f, GET_MODE (f))
4980 (GET_MODE_BITSIZE (mode)
4981 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t, 0), 1))))))
4983 c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0));
4984 extend_op = SIGN_EXTEND;
4985 m = GET_MODE (XEXP (t, 0));
4987 else if (GET_CODE (t) == ZERO_EXTEND
4988 && (GET_CODE (XEXP (t, 0)) == PLUS
4989 || GET_CODE (XEXP (t, 0)) == MINUS
4990 || GET_CODE (XEXP (t, 0)) == IOR
4991 || GET_CODE (XEXP (t, 0)) == XOR
4992 || GET_CODE (XEXP (t, 0)) == ASHIFT
4993 || GET_CODE (XEXP (t, 0)) == LSHIFTRT
4994 || GET_CODE (XEXP (t, 0)) == ASHIFTRT)
4995 && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG
4996 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4997 && subreg_lowpart_p (XEXP (XEXP (t, 0), 0))
4998 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f)
4999 && ((nonzero_bits (f, GET_MODE (f))
5000 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t, 0), 0))))
5003 c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0));
5004 extend_op = ZERO_EXTEND;
5005 m = GET_MODE (XEXP (t, 0));
5007 else if (GET_CODE (t) == ZERO_EXTEND
5008 && (GET_CODE (XEXP (t, 0)) == PLUS
5009 || GET_CODE (XEXP (t, 0)) == IOR
5010 || GET_CODE (XEXP (t, 0)) == XOR)
5011 && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG
5012 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5013 && subreg_lowpart_p (XEXP (XEXP (t, 0), 1))
5014 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f)
5015 && ((nonzero_bits (f, GET_MODE (f))
5016 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t, 0), 1))))
5019 c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0));
5020 extend_op = ZERO_EXTEND;
5021 m = GET_MODE (XEXP (t, 0));
5026 temp = subst (gen_binary (true_code, m, cond_op0, cond_op1),
5027 pc_rtx, pc_rtx, 0, 0);
5028 temp = gen_binary (MULT, m, temp,
5029 gen_binary (MULT, m, c1, const_true_rtx));
5030 temp = subst (temp, pc_rtx, pc_rtx, 0, 0);
5031 temp = gen_binary (op, m, gen_lowpart (m, z), temp);
5033 if (extend_op != UNKNOWN)
5034 temp = simplify_gen_unary (extend_op, mode, temp, m);
5040 /* If we have (if_then_else (ne A 0) C1 0) and either A is known to be 0 or
5041 1 and C1 is a single bit or A is known to be 0 or -1 and C1 is the
5042 negation of a single bit, we can convert this operation to a shift. We
5043 can actually do this more generally, but it doesn't seem worth it. */
5045 if (true_code == NE && XEXP (cond, 1) == const0_rtx
5046 && false_rtx == const0_rtx && GET_CODE (true_rtx) == CONST_INT
5047 && ((1 == nonzero_bits (XEXP (cond, 0), mode)
5048 && (i = exact_log2 (INTVAL (true_rtx))) >= 0)
5049 || ((num_sign_bit_copies (XEXP (cond, 0), mode)
5050 == GET_MODE_BITSIZE (mode))
5051 && (i = exact_log2 (-INTVAL (true_rtx))) >= 0)))
5053 simplify_shift_const (NULL_RTX, ASHIFT, mode,
5054 gen_lowpart (mode, XEXP (cond, 0)), i);
5056 /* (IF_THEN_ELSE (NE REG 0) (0) (8)) is REG for nonzero_bits (REG) == 8. */
5057 if (true_code == NE && XEXP (cond, 1) == const0_rtx
5058 && false_rtx == const0_rtx && GET_CODE (true_rtx) == CONST_INT
5059 && GET_MODE (XEXP (cond, 0)) == mode
5060 && (INTVAL (true_rtx) & GET_MODE_MASK (mode))
5061 == nonzero_bits (XEXP (cond, 0), mode)
5062 && (i = exact_log2 (INTVAL (true_rtx) & GET_MODE_MASK (mode))) >= 0)
5063 return XEXP (cond, 0);
5068 /* Simplify X, a SET expression. Return the new expression. */
5071 simplify_set (rtx x)
5073 rtx src = SET_SRC (x);
5074 rtx dest = SET_DEST (x);
5075 enum machine_mode mode
5076 = GET_MODE (src) != VOIDmode ? GET_MODE (src) : GET_MODE (dest);
5080 /* (set (pc) (return)) gets written as (return). */
5081 if (GET_CODE (dest) == PC && GET_CODE (src) == RETURN)
5084 /* Now that we know for sure which bits of SRC we are using, see if we can
5085 simplify the expression for the object knowing that we only need the
5088 if (GET_MODE_CLASS (mode) == MODE_INT
5089 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
5091 src = force_to_mode (src, mode, ~(HOST_WIDE_INT) 0, NULL_RTX, 0);
5092 SUBST (SET_SRC (x), src);
5095 /* If we are setting CC0 or if the source is a COMPARE, look for the use of
5096 the comparison result and try to simplify it unless we already have used
5097 undobuf.other_insn. */
5098 if ((GET_MODE_CLASS (mode) == MODE_CC
5099 || GET_CODE (src) == COMPARE
5101 && (cc_use = find_single_use (dest, subst_insn, &other_insn)) != 0
5102 && (undobuf.other_insn == 0 || other_insn == undobuf.other_insn)
5103 && COMPARISON_P (*cc_use)
5104 && rtx_equal_p (XEXP (*cc_use, 0), dest))
5106 enum rtx_code old_code = GET_CODE (*cc_use);
5107 enum rtx_code new_code;
5109 int other_changed = 0;
5110 enum machine_mode compare_mode = GET_MODE (dest);
5112 if (GET_CODE (src) == COMPARE)
5113 op0 = XEXP (src, 0), op1 = XEXP (src, 1);
5115 op0 = src, op1 = CONST0_RTX (GET_MODE (src));
5117 tmp = simplify_relational_operation (old_code, compare_mode, VOIDmode,
5120 new_code = old_code;
5121 else if (!CONSTANT_P (tmp))
5123 new_code = GET_CODE (tmp);
5124 op0 = XEXP (tmp, 0);
5125 op1 = XEXP (tmp, 1);
5129 rtx pat = PATTERN (other_insn);
5130 undobuf.other_insn = other_insn;
5131 SUBST (*cc_use, tmp);
5133 /* Attempt to simplify CC user. */
5134 if (GET_CODE (pat) == SET)
5136 rtx new = simplify_rtx (SET_SRC (pat));
5137 if (new != NULL_RTX)
5138 SUBST (SET_SRC (pat), new);
5141 /* Convert X into a no-op move. */
5142 SUBST (SET_DEST (x), pc_rtx);
5143 SUBST (SET_SRC (x), pc_rtx);
5147 /* Simplify our comparison, if possible. */
5148 new_code = simplify_comparison (new_code, &op0, &op1);
5150 #ifdef SELECT_CC_MODE
5151 /* If this machine has CC modes other than CCmode, check to see if we
5152 need to use a different CC mode here. */
5153 if (GET_MODE_CLASS (GET_MODE (op0)) == MODE_CC)
5154 compare_mode = GET_MODE (op0);
5156 compare_mode = SELECT_CC_MODE (new_code, op0, op1);
5159 /* If the mode changed, we have to change SET_DEST, the mode in the
5160 compare, and the mode in the place SET_DEST is used. If SET_DEST is
5161 a hard register, just build new versions with the proper mode. If it
5162 is a pseudo, we lose unless it is only time we set the pseudo, in
5163 which case we can safely change its mode. */
5164 if (compare_mode != GET_MODE (dest))
5166 unsigned int regno = REGNO (dest);
5167 rtx new_dest = gen_rtx_REG (compare_mode, regno);
5169 if (regno < FIRST_PSEUDO_REGISTER
5170 || (REG_N_SETS (regno) == 1 && ! REG_USERVAR_P (dest)))
5172 if (regno >= FIRST_PSEUDO_REGISTER)
5173 SUBST (regno_reg_rtx[regno], new_dest);
5175 SUBST (SET_DEST (x), new_dest);
5176 SUBST (XEXP (*cc_use, 0), new_dest);
5183 #endif /* SELECT_CC_MODE */
5185 /* If the code changed, we have to build a new comparison in
5186 undobuf.other_insn. */
5187 if (new_code != old_code)
5189 int other_changed_previously = other_changed;
5190 unsigned HOST_WIDE_INT mask;
5192 SUBST (*cc_use, gen_rtx_fmt_ee (new_code, GET_MODE (*cc_use),
5196 /* If the only change we made was to change an EQ into an NE or
5197 vice versa, OP0 has only one bit that might be nonzero, and OP1
5198 is zero, check if changing the user of the condition code will
5199 produce a valid insn. If it won't, we can keep the original code
5200 in that insn by surrounding our operation with an XOR. */
5202 if (((old_code == NE && new_code == EQ)
5203 || (old_code == EQ && new_code == NE))
5204 && ! other_changed_previously && op1 == const0_rtx
5205 && GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
5206 && exact_log2 (mask = nonzero_bits (op0, GET_MODE (op0))) >= 0)
5208 rtx pat = PATTERN (other_insn), note = 0;
5210 if ((recog_for_combine (&pat, other_insn, ¬e) < 0
5211 && ! check_asm_operands (pat)))
5213 PUT_CODE (*cc_use, old_code);
5216 op0 = gen_binary (XOR, GET_MODE (op0), op0, GEN_INT (mask));
5222 undobuf.other_insn = other_insn;
5225 /* If we are now comparing against zero, change our source if
5226 needed. If we do not use cc0, we always have a COMPARE. */
5227 if (op1 == const0_rtx && dest == cc0_rtx)
5229 SUBST (SET_SRC (x), op0);
5235 /* Otherwise, if we didn't previously have a COMPARE in the
5236 correct mode, we need one. */
5237 if (GET_CODE (src) != COMPARE || GET_MODE (src) != compare_mode)
5239 SUBST (SET_SRC (x), gen_rtx_COMPARE (compare_mode, op0, op1));
5244 /* Otherwise, update the COMPARE if needed. */
5245 SUBST (XEXP (src, 0), op0);
5246 SUBST (XEXP (src, 1), op1);
5251 /* Get SET_SRC in a form where we have placed back any
5252 compound expressions. Then do the checks below. */
5253 src = make_compound_operation (src, SET);
5254 SUBST (SET_SRC (x), src);
5257 /* If we have (set x (subreg:m1 (op:m2 ...) 0)) with OP being some operation,
5258 and X being a REG or (subreg (reg)), we may be able to convert this to
5259 (set (subreg:m2 x) (op)).
5261 We can always do this if M1 is narrower than M2 because that means that
5262 we only care about the low bits of the result.
5264 However, on machines without WORD_REGISTER_OPERATIONS defined, we cannot
5265 perform a narrower operation than requested since the high-order bits will
5266 be undefined. On machine where it is defined, this transformation is safe
5267 as long as M1 and M2 have the same number of words. */
5269 if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src)
5270 && !OBJECT_P (SUBREG_REG (src))
5271 && (((GET_MODE_SIZE (GET_MODE (src)) + (UNITS_PER_WORD - 1))
5273 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (src)))
5274 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD))
5275 #ifndef WORD_REGISTER_OPERATIONS
5276 && (GET_MODE_SIZE (GET_MODE (src))
5277 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (src))))
5279 #ifdef CANNOT_CHANGE_MODE_CLASS
5280 && ! (REG_P (dest) && REGNO (dest) < FIRST_PSEUDO_REGISTER
5281 && REG_CANNOT_CHANGE_MODE_P (REGNO (dest),
5282 GET_MODE (SUBREG_REG (src)),
5286 || (GET_CODE (dest) == SUBREG
5287 && REG_P (SUBREG_REG (dest)))))
5289 SUBST (SET_DEST (x),
5290 gen_lowpart (GET_MODE (SUBREG_REG (src)),
5292 SUBST (SET_SRC (x), SUBREG_REG (src));
5294 src = SET_SRC (x), dest = SET_DEST (x);
5298 /* If we have (set (cc0) (subreg ...)), we try to remove the subreg
5301 && GET_CODE (src) == SUBREG
5302 && subreg_lowpart_p (src)
5303 && (GET_MODE_BITSIZE (GET_MODE (src))
5304 < GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (src)))))
5306 rtx inner = SUBREG_REG (src);
5307 enum machine_mode inner_mode = GET_MODE (inner);
5309 /* Here we make sure that we don't have a sign bit on. */
5310 if (GET_MODE_BITSIZE (inner_mode) <= HOST_BITS_PER_WIDE_INT
5311 && (nonzero_bits (inner, inner_mode)
5312 < ((unsigned HOST_WIDE_INT) 1
5313 << (GET_MODE_BITSIZE (GET_MODE (src)) - 1))))
5315 SUBST (SET_SRC (x), inner);
5321 #ifdef LOAD_EXTEND_OP
5322 /* If we have (set FOO (subreg:M (mem:N BAR) 0)) with M wider than N, this
5323 would require a paradoxical subreg. Replace the subreg with a
5324 zero_extend to avoid the reload that would otherwise be required. */
5326 if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src)
5327 && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src))) != UNKNOWN
5328 && SUBREG_BYTE (src) == 0
5329 && (GET_MODE_SIZE (GET_MODE (src))
5330 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (src))))
5331 && MEM_P (SUBREG_REG (src)))
5334 gen_rtx_fmt_e (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src))),
5335 GET_MODE (src), SUBREG_REG (src)));
5341 /* If we don't have a conditional move, SET_SRC is an IF_THEN_ELSE, and we
5342 are comparing an item known to be 0 or -1 against 0, use a logical
5343 operation instead. Check for one of the arms being an IOR of the other
5344 arm with some value. We compute three terms to be IOR'ed together. In
5345 practice, at most two will be nonzero. Then we do the IOR's. */
5347 if (GET_CODE (dest) != PC
5348 && GET_CODE (src) == IF_THEN_ELSE
5349 && GET_MODE_CLASS (GET_MODE (src)) == MODE_INT
5350 && (GET_CODE (XEXP (src, 0)) == EQ || GET_CODE (XEXP (src, 0)) == NE)
5351 && XEXP (XEXP (src, 0), 1) == const0_rtx
5352 && GET_MODE (src) == GET_MODE (XEXP (XEXP (src, 0), 0))
5353 #ifdef HAVE_conditional_move
5354 && ! can_conditionally_move_p (GET_MODE (src))
5356 && (num_sign_bit_copies (XEXP (XEXP (src, 0), 0),
5357 GET_MODE (XEXP (XEXP (src, 0), 0)))
5358 == GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (src, 0), 0))))
5359 && ! side_effects_p (src))
5361 rtx true_rtx = (GET_CODE (XEXP (src, 0)) == NE
5362 ? XEXP (src, 1) : XEXP (src, 2));
5363 rtx false_rtx = (GET_CODE (XEXP (src, 0)) == NE
5364 ? XEXP (src, 2) : XEXP (src, 1));
5365 rtx term1 = const0_rtx, term2, term3;
5367 if (GET_CODE (true_rtx) == IOR
5368 && rtx_equal_p (XEXP (true_rtx, 0), false_rtx))
5369 term1 = false_rtx, true_rtx = XEXP (true_rtx, 1), false_rtx = const0_rtx;
5370 else if (GET_CODE (true_rtx) == IOR
5371 && rtx_equal_p (XEXP (true_rtx, 1), false_rtx))
5372 term1 = false_rtx, true_rtx = XEXP (true_rtx, 0), false_rtx = const0_rtx;
5373 else if (GET_CODE (false_rtx) == IOR
5374 && rtx_equal_p (XEXP (false_rtx, 0), true_rtx))
5375 term1 = true_rtx, false_rtx = XEXP (false_rtx, 1), true_rtx = const0_rtx;
5376 else if (GET_CODE (false_rtx) == IOR
5377 && rtx_equal_p (XEXP (false_rtx, 1), true_rtx))
5378 term1 = true_rtx, false_rtx = XEXP (false_rtx, 0), true_rtx = const0_rtx;
5380 term2 = gen_binary (AND, GET_MODE (src),
5381 XEXP (XEXP (src, 0), 0), true_rtx);
5382 term3 = gen_binary (AND, GET_MODE (src),
5383 simplify_gen_unary (NOT, GET_MODE (src),
5384 XEXP (XEXP (src, 0), 0),
5389 gen_binary (IOR, GET_MODE (src),
5390 gen_binary (IOR, GET_MODE (src), term1, term2),
5396 /* If either SRC or DEST is a CLOBBER of (const_int 0), make this
5397 whole thing fail. */
5398 if (GET_CODE (src) == CLOBBER && XEXP (src, 0) == const0_rtx)
5400 else if (GET_CODE (dest) == CLOBBER && XEXP (dest, 0) == const0_rtx)
5403 /* Convert this into a field assignment operation, if possible. */
5404 return make_field_assignment (x);
5407 /* Simplify, X, and AND, IOR, or XOR operation, and return the simplified
5411 simplify_logical (rtx x)
5413 enum machine_mode mode = GET_MODE (x);
5414 rtx op0 = XEXP (x, 0);
5415 rtx op1 = XEXP (x, 1);
5418 switch (GET_CODE (x))
5421 /* Convert (A ^ B) & A to A & (~B) since the latter is often a single
5422 insn (and may simplify more). */
5423 if (GET_CODE (op0) == XOR
5424 && rtx_equal_p (XEXP (op0, 0), op1)
5425 && ! side_effects_p (op1))
5426 x = gen_binary (AND, mode,
5427 simplify_gen_unary (NOT, mode, XEXP (op0, 1), mode),
5430 if (GET_CODE (op0) == XOR
5431 && rtx_equal_p (XEXP (op0, 1), op1)
5432 && ! side_effects_p (op1))
5433 x = gen_binary (AND, mode,
5434 simplify_gen_unary (NOT, mode, XEXP (op0, 0), mode),
5437 /* Similarly for (~(A ^ B)) & A. */
5438 if (GET_CODE (op0) == NOT
5439 && GET_CODE (XEXP (op0, 0)) == XOR
5440 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), op1)
5441 && ! side_effects_p (op1))
5442 x = gen_binary (AND, mode, XEXP (XEXP (op0, 0), 1), op1);
5444 if (GET_CODE (op0) == NOT
5445 && GET_CODE (XEXP (op0, 0)) == XOR
5446 && rtx_equal_p (XEXP (XEXP (op0, 0), 1), op1)
5447 && ! side_effects_p (op1))
5448 x = gen_binary (AND, mode, XEXP (XEXP (op0, 0), 0), op1);
5450 /* We can call simplify_and_const_int only if we don't lose
5451 any (sign) bits when converting INTVAL (op1) to
5452 "unsigned HOST_WIDE_INT". */
5453 if (GET_CODE (op1) == CONST_INT
5454 && (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5455 || INTVAL (op1) > 0))
5457 x = simplify_and_const_int (x, mode, op0, INTVAL (op1));
5459 /* If we have (ior (and (X C1) C2)) and the next restart would be
5460 the last, simplify this by making C1 as small as possible
5461 and then exit. Only do this if C1 actually changes: for now
5462 this only saves memory but, should this transformation be
5463 moved to simplify-rtx.c, we'd risk unbounded recursion there. */
5464 if (GET_CODE (x) == IOR && GET_CODE (op0) == AND
5465 && GET_CODE (XEXP (op0, 1)) == CONST_INT
5466 && GET_CODE (op1) == CONST_INT
5467 && (INTVAL (XEXP (op0, 1)) & INTVAL (op1)) != 0)
5468 return gen_binary (IOR, mode,
5469 gen_binary (AND, mode, XEXP (op0, 0),
5470 GEN_INT (INTVAL (XEXP (op0, 1))
5471 & ~INTVAL (op1))), op1);
5473 if (GET_CODE (x) != AND)
5480 /* Convert (A | B) & A to A. */
5481 if (GET_CODE (op0) == IOR
5482 && (rtx_equal_p (XEXP (op0, 0), op1)
5483 || rtx_equal_p (XEXP (op0, 1), op1))
5484 && ! side_effects_p (XEXP (op0, 0))
5485 && ! side_effects_p (XEXP (op0, 1)))
5488 /* In the following group of tests (and those in case IOR below),
5489 we start with some combination of logical operations and apply
5490 the distributive law followed by the inverse distributive law.
5491 Most of the time, this results in no change. However, if some of
5492 the operands are the same or inverses of each other, simplifications
5495 For example, (and (ior A B) (not B)) can occur as the result of
5496 expanding a bit field assignment. When we apply the distributive
5497 law to this, we get (ior (and (A (not B))) (and (B (not B)))),
5498 which then simplifies to (and (A (not B))).
5500 If we have (and (ior A B) C), apply the distributive law and then
5501 the inverse distributive law to see if things simplify. */
5503 if (GET_CODE (op0) == IOR || GET_CODE (op0) == XOR)
5505 x = apply_distributive_law
5506 (gen_binary (GET_CODE (op0), mode,
5507 gen_binary (AND, mode, XEXP (op0, 0), op1),
5508 gen_binary (AND, mode, XEXP (op0, 1),
5510 if (GET_CODE (x) != AND)
5514 if (GET_CODE (op1) == IOR || GET_CODE (op1) == XOR)
5515 return apply_distributive_law
5516 (gen_binary (GET_CODE (op1), mode,
5517 gen_binary (AND, mode, XEXP (op1, 0), op0),
5518 gen_binary (AND, mode, XEXP (op1, 1),
5521 /* Similarly, taking advantage of the fact that
5522 (and (not A) (xor B C)) == (xor (ior A B) (ior A C)) */
5524 if (GET_CODE (op0) == NOT && GET_CODE (op1) == XOR)
5525 return apply_distributive_law
5526 (gen_binary (XOR, mode,
5527 gen_binary (IOR, mode, XEXP (op0, 0), XEXP (op1, 0)),
5528 gen_binary (IOR, mode, copy_rtx (XEXP (op0, 0)),
5531 else if (GET_CODE (op1) == NOT && GET_CODE (op0) == XOR)
5532 return apply_distributive_law
5533 (gen_binary (XOR, mode,
5534 gen_binary (IOR, mode, XEXP (op1, 0), XEXP (op0, 0)),
5535 gen_binary (IOR, mode, copy_rtx (XEXP (op1, 0)), XEXP (op0, 1))));
5539 /* (ior A C) is C if all bits of A that might be nonzero are on in C. */
5540 if (GET_CODE (op1) == CONST_INT
5541 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5542 && (nonzero_bits (op0, mode) & ~INTVAL (op1)) == 0)
5545 /* Convert (A & B) | A to A. */
5546 if (GET_CODE (op0) == AND
5547 && (rtx_equal_p (XEXP (op0, 0), op1)
5548 || rtx_equal_p (XEXP (op0, 1), op1))
5549 && ! side_effects_p (XEXP (op0, 0))
5550 && ! side_effects_p (XEXP (op0, 1)))
5553 /* If we have (ior (and A B) C), apply the distributive law and then
5554 the inverse distributive law to see if things simplify. */
5556 if (GET_CODE (op0) == AND)
5558 x = apply_distributive_law
5559 (gen_binary (AND, mode,
5560 gen_binary (IOR, mode, XEXP (op0, 0), op1),
5561 gen_binary (IOR, mode, XEXP (op0, 1),
5564 if (GET_CODE (x) != IOR)
5568 if (GET_CODE (op1) == AND)
5570 x = apply_distributive_law
5571 (gen_binary (AND, mode,
5572 gen_binary (IOR, mode, XEXP (op1, 0), op0),
5573 gen_binary (IOR, mode, XEXP (op1, 1),
5576 if (GET_CODE (x) != IOR)
5580 /* Convert (ior (ashift A CX) (lshiftrt A CY)) where CX+CY equals the
5581 mode size to (rotate A CX). */
5583 if (((GET_CODE (op0) == ASHIFT && GET_CODE (op1) == LSHIFTRT)
5584 || (GET_CODE (op1) == ASHIFT && GET_CODE (op0) == LSHIFTRT))
5585 && rtx_equal_p (XEXP (op0, 0), XEXP (op1, 0))
5586 && GET_CODE (XEXP (op0, 1)) == CONST_INT
5587 && GET_CODE (XEXP (op1, 1)) == CONST_INT
5588 && (INTVAL (XEXP (op0, 1)) + INTVAL (XEXP (op1, 1))
5589 == GET_MODE_BITSIZE (mode)))
5590 return gen_rtx_ROTATE (mode, XEXP (op0, 0),
5591 (GET_CODE (op0) == ASHIFT
5592 ? XEXP (op0, 1) : XEXP (op1, 1)));
5594 /* If OP0 is (ashiftrt (plus ...) C), it might actually be
5595 a (sign_extend (plus ...)). If so, OP1 is a CONST_INT, and the PLUS
5596 does not affect any of the bits in OP1, it can really be done
5597 as a PLUS and we can associate. We do this by seeing if OP1
5598 can be safely shifted left C bits. */
5599 if (GET_CODE (op1) == CONST_INT && GET_CODE (op0) == ASHIFTRT
5600 && GET_CODE (XEXP (op0, 0)) == PLUS
5601 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
5602 && GET_CODE (XEXP (op0, 1)) == CONST_INT
5603 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT)
5605 int count = INTVAL (XEXP (op0, 1));
5606 HOST_WIDE_INT mask = INTVAL (op1) << count;
5608 if (mask >> count == INTVAL (op1)
5609 && (mask & nonzero_bits (XEXP (op0, 0), mode)) == 0)
5611 SUBST (XEXP (XEXP (op0, 0), 1),
5612 GEN_INT (INTVAL (XEXP (XEXP (op0, 0), 1)) | mask));
5619 /* If we are XORing two things that have no bits in common,
5620 convert them into an IOR. This helps to detect rotation encoded
5621 using those methods and possibly other simplifications. */
5623 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5624 && (nonzero_bits (op0, mode)
5625 & nonzero_bits (op1, mode)) == 0)
5626 return (gen_binary (IOR, mode, op0, op1));
5628 /* Convert (XOR (NOT x) (NOT y)) to (XOR x y).
5629 Also convert (XOR (NOT x) y) to (NOT (XOR x y)), similarly for
5632 int num_negated = 0;
5634 if (GET_CODE (op0) == NOT)
5635 num_negated++, op0 = XEXP (op0, 0);
5636 if (GET_CODE (op1) == NOT)
5637 num_negated++, op1 = XEXP (op1, 0);
5639 if (num_negated == 2)
5641 SUBST (XEXP (x, 0), op0);
5642 SUBST (XEXP (x, 1), op1);
5644 else if (num_negated == 1)
5646 simplify_gen_unary (NOT, mode, gen_binary (XOR, mode, op0, op1),
5650 /* Convert (xor (and A B) B) to (and (not A) B). The latter may
5651 correspond to a machine insn or result in further simplifications
5652 if B is a constant. */
5654 if (GET_CODE (op0) == AND
5655 && rtx_equal_p (XEXP (op0, 1), op1)
5656 && ! side_effects_p (op1))
5657 return gen_binary (AND, mode,
5658 simplify_gen_unary (NOT, mode, XEXP (op0, 0), mode),
5661 else if (GET_CODE (op0) == AND
5662 && rtx_equal_p (XEXP (op0, 0), op1)
5663 && ! side_effects_p (op1))
5664 return gen_binary (AND, mode,
5665 simplify_gen_unary (NOT, mode, XEXP (op0, 1), mode),
5668 /* (xor (comparison foo bar) (const_int 1)) can become the reversed
5669 comparison if STORE_FLAG_VALUE is 1. */
5670 if (STORE_FLAG_VALUE == 1
5671 && op1 == const1_rtx
5672 && COMPARISON_P (op0)
5673 && (reversed = reversed_comparison (op0, mode, XEXP (op0, 0),
5677 /* (lshiftrt foo C) where C is the number of bits in FOO minus 1
5678 is (lt foo (const_int 0)), so we can perform the above
5679 simplification if STORE_FLAG_VALUE is 1. */
5681 if (STORE_FLAG_VALUE == 1
5682 && op1 == const1_rtx
5683 && GET_CODE (op0) == LSHIFTRT
5684 && GET_CODE (XEXP (op0, 1)) == CONST_INT
5685 && INTVAL (XEXP (op0, 1)) == GET_MODE_BITSIZE (mode) - 1)
5686 return gen_rtx_GE (mode, XEXP (op0, 0), const0_rtx);
5688 /* (xor (comparison foo bar) (const_int sign-bit))
5689 when STORE_FLAG_VALUE is the sign bit. */
5690 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5691 && ((STORE_FLAG_VALUE & GET_MODE_MASK (mode))
5692 == (unsigned HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (mode) - 1))
5693 && op1 == const_true_rtx
5694 && COMPARISON_P (op0)
5695 && (reversed = reversed_comparison (op0, mode, XEXP (op0, 0),
5708 /* We consider ZERO_EXTRACT, SIGN_EXTRACT, and SIGN_EXTEND as "compound
5709 operations" because they can be replaced with two more basic operations.
5710 ZERO_EXTEND is also considered "compound" because it can be replaced with
5711 an AND operation, which is simpler, though only one operation.
5713 The function expand_compound_operation is called with an rtx expression
5714 and will convert it to the appropriate shifts and AND operations,
5715 simplifying at each stage.
5717 The function make_compound_operation is called to convert an expression
5718 consisting of shifts and ANDs into the equivalent compound expression.
5719 It is the inverse of this function, loosely speaking. */
5722 expand_compound_operation (rtx x)
5724 unsigned HOST_WIDE_INT pos = 0, len;
5726 unsigned int modewidth;
5729 switch (GET_CODE (x))
5734 /* We can't necessarily use a const_int for a multiword mode;
5735 it depends on implicitly extending the value.
5736 Since we don't know the right way to extend it,
5737 we can't tell whether the implicit way is right.
5739 Even for a mode that is no wider than a const_int,
5740 we can't win, because we need to sign extend one of its bits through
5741 the rest of it, and we don't know which bit. */
5742 if (GET_CODE (XEXP (x, 0)) == CONST_INT)
5745 /* Return if (subreg:MODE FROM 0) is not a safe replacement for
5746 (zero_extend:MODE FROM) or (sign_extend:MODE FROM). It is for any MEM
5747 because (SUBREG (MEM...)) is guaranteed to cause the MEM to be
5748 reloaded. If not for that, MEM's would very rarely be safe.
5750 Reject MODEs bigger than a word, because we might not be able
5751 to reference a two-register group starting with an arbitrary register
5752 (and currently gen_lowpart might crash for a SUBREG). */
5754 if (GET_MODE_SIZE (GET_MODE (XEXP (x, 0))) > UNITS_PER_WORD)
5757 /* Reject MODEs that aren't scalar integers because turning vector
5758 or complex modes into shifts causes problems. */
5760 if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x, 0))))
5763 len = GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)));
5764 /* If the inner object has VOIDmode (the only way this can happen
5765 is if it is an ASM_OPERANDS), we can't do anything since we don't
5766 know how much masking to do. */
5775 /* If the operand is a CLOBBER, just return it. */
5776 if (GET_CODE (XEXP (x, 0)) == CLOBBER)
5779 if (GET_CODE (XEXP (x, 1)) != CONST_INT
5780 || GET_CODE (XEXP (x, 2)) != CONST_INT
5781 || GET_MODE (XEXP (x, 0)) == VOIDmode)
5784 /* Reject MODEs that aren't scalar integers because turning vector
5785 or complex modes into shifts causes problems. */
5787 if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x, 0))))
5790 len = INTVAL (XEXP (x, 1));
5791 pos = INTVAL (XEXP (x, 2));
5793 /* If this goes outside the object being extracted, replace the object
5794 with a (use (mem ...)) construct that only combine understands
5795 and is used only for this purpose. */
5796 if (len + pos > GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))))
5797 SUBST (XEXP (x, 0), gen_rtx_USE (GET_MODE (x), XEXP (x, 0)));
5799 if (BITS_BIG_ENDIAN)
5800 pos = GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - len - pos;
5807 /* Convert sign extension to zero extension, if we know that the high
5808 bit is not set, as this is easier to optimize. It will be converted
5809 back to cheaper alternative in make_extraction. */
5810 if (GET_CODE (x) == SIGN_EXTEND
5811 && (GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
5812 && ((nonzero_bits (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
5813 & ~(((unsigned HOST_WIDE_INT)
5814 GET_MODE_MASK (GET_MODE (XEXP (x, 0))))
5818 rtx temp = gen_rtx_ZERO_EXTEND (GET_MODE (x), XEXP (x, 0));
5819 rtx temp2 = expand_compound_operation (temp);
5821 /* Make sure this is a profitable operation. */
5822 if (rtx_cost (x, SET) > rtx_cost (temp2, SET))
5824 else if (rtx_cost (x, SET) > rtx_cost (temp, SET))
5830 /* We can optimize some special cases of ZERO_EXTEND. */
5831 if (GET_CODE (x) == ZERO_EXTEND)
5833 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI if we
5834 know that the last value didn't have any inappropriate bits
5836 if (GET_CODE (XEXP (x, 0)) == TRUNCATE
5837 && GET_MODE (XEXP (XEXP (x, 0), 0)) == GET_MODE (x)
5838 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
5839 && (nonzero_bits (XEXP (XEXP (x, 0), 0), GET_MODE (x))
5840 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5841 return XEXP (XEXP (x, 0), 0);
5843 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
5844 if (GET_CODE (XEXP (x, 0)) == SUBREG
5845 && GET_MODE (SUBREG_REG (XEXP (x, 0))) == GET_MODE (x)
5846 && subreg_lowpart_p (XEXP (x, 0))
5847 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
5848 && (nonzero_bits (SUBREG_REG (XEXP (x, 0)), GET_MODE (x))
5849 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5850 return SUBREG_REG (XEXP (x, 0));
5852 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI when foo
5853 is a comparison and STORE_FLAG_VALUE permits. This is like
5854 the first case, but it works even when GET_MODE (x) is larger
5855 than HOST_WIDE_INT. */
5856 if (GET_CODE (XEXP (x, 0)) == TRUNCATE
5857 && GET_MODE (XEXP (XEXP (x, 0), 0)) == GET_MODE (x)
5858 && COMPARISON_P (XEXP (XEXP (x, 0), 0))
5859 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
5860 <= HOST_BITS_PER_WIDE_INT)
5861 && ((HOST_WIDE_INT) STORE_FLAG_VALUE
5862 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5863 return XEXP (XEXP (x, 0), 0);
5865 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
5866 if (GET_CODE (XEXP (x, 0)) == SUBREG
5867 && GET_MODE (SUBREG_REG (XEXP (x, 0))) == GET_MODE (x)
5868 && subreg_lowpart_p (XEXP (x, 0))
5869 && COMPARISON_P (SUBREG_REG (XEXP (x, 0)))
5870 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
5871 <= HOST_BITS_PER_WIDE_INT)
5872 && ((HOST_WIDE_INT) STORE_FLAG_VALUE
5873 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5874 return SUBREG_REG (XEXP (x, 0));
5878 /* If we reach here, we want to return a pair of shifts. The inner
5879 shift is a left shift of BITSIZE - POS - LEN bits. The outer
5880 shift is a right shift of BITSIZE - LEN bits. It is arithmetic or
5881 logical depending on the value of UNSIGNEDP.
5883 If this was a ZERO_EXTEND or ZERO_EXTRACT, this pair of shifts will be
5884 converted into an AND of a shift.
5886 We must check for the case where the left shift would have a negative
5887 count. This can happen in a case like (x >> 31) & 255 on machines
5888 that can't shift by a constant. On those machines, we would first
5889 combine the shift with the AND to produce a variable-position
5890 extraction. Then the constant of 31 would be substituted in to produce
5891 a such a position. */
5893 modewidth = GET_MODE_BITSIZE (GET_MODE (x));
5894 if (modewidth + len >= pos)
5895 tem = simplify_shift_const (NULL_RTX, unsignedp ? LSHIFTRT : ASHIFTRT,
5897 simplify_shift_const (NULL_RTX, ASHIFT,
5900 modewidth - pos - len),
5903 else if (unsignedp && len < HOST_BITS_PER_WIDE_INT)
5904 tem = simplify_and_const_int (NULL_RTX, GET_MODE (x),
5905 simplify_shift_const (NULL_RTX, LSHIFTRT,
5908 ((HOST_WIDE_INT) 1 << len) - 1);
5910 /* Any other cases we can't handle. */
5913 /* If we couldn't do this for some reason, return the original
5915 if (GET_CODE (tem) == CLOBBER)
5921 /* X is a SET which contains an assignment of one object into
5922 a part of another (such as a bit-field assignment, STRICT_LOW_PART,
5923 or certain SUBREGS). If possible, convert it into a series of
5926 We half-heartedly support variable positions, but do not at all
5927 support variable lengths. */
5930 expand_field_assignment (rtx x)
5933 rtx pos; /* Always counts from low bit. */
5936 enum machine_mode compute_mode;
5938 /* Loop until we find something we can't simplify. */
5941 if (GET_CODE (SET_DEST (x)) == STRICT_LOW_PART
5942 && GET_CODE (XEXP (SET_DEST (x), 0)) == SUBREG)
5944 inner = SUBREG_REG (XEXP (SET_DEST (x), 0));
5945 len = GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0)));
5946 pos = GEN_INT (subreg_lsb (XEXP (SET_DEST (x), 0)));
5948 else if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
5949 && GET_CODE (XEXP (SET_DEST (x), 1)) == CONST_INT)
5951 inner = XEXP (SET_DEST (x), 0);
5952 len = INTVAL (XEXP (SET_DEST (x), 1));
5953 pos = XEXP (SET_DEST (x), 2);
5955 /* If the position is constant and spans the width of INNER,
5956 surround INNER with a USE to indicate this. */
5957 if (GET_CODE (pos) == CONST_INT
5958 && INTVAL (pos) + len > GET_MODE_BITSIZE (GET_MODE (inner)))
5959 inner = gen_rtx_USE (GET_MODE (SET_DEST (x)), inner);
5961 if (BITS_BIG_ENDIAN)
5963 if (GET_CODE (pos) == CONST_INT)
5964 pos = GEN_INT (GET_MODE_BITSIZE (GET_MODE (inner)) - len
5966 else if (GET_CODE (pos) == MINUS
5967 && GET_CODE (XEXP (pos, 1)) == CONST_INT
5968 && (INTVAL (XEXP (pos, 1))
5969 == GET_MODE_BITSIZE (GET_MODE (inner)) - len))
5970 /* If position is ADJUST - X, new position is X. */
5971 pos = XEXP (pos, 0);
5973 pos = gen_binary (MINUS, GET_MODE (pos),
5974 GEN_INT (GET_MODE_BITSIZE (GET_MODE (inner))
5980 /* A SUBREG between two modes that occupy the same numbers of words
5981 can be done by moving the SUBREG to the source. */
5982 else if (GET_CODE (SET_DEST (x)) == SUBREG
5983 /* We need SUBREGs to compute nonzero_bits properly. */
5984 && nonzero_sign_valid
5985 && (((GET_MODE_SIZE (GET_MODE (SET_DEST (x)))
5986 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
5987 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x))))
5988 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)))
5990 x = gen_rtx_SET (VOIDmode, SUBREG_REG (SET_DEST (x)),
5992 (GET_MODE (SUBREG_REG (SET_DEST (x))),
5999 while (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
6000 inner = SUBREG_REG (inner);
6002 compute_mode = GET_MODE (inner);
6004 /* Don't attempt bitwise arithmetic on non scalar integer modes. */
6005 if (! SCALAR_INT_MODE_P (compute_mode))
6007 enum machine_mode imode;
6009 /* Don't do anything for vector or complex integral types. */
6010 if (! FLOAT_MODE_P (compute_mode))
6013 /* Try to find an integral mode to pun with. */
6014 imode = mode_for_size (GET_MODE_BITSIZE (compute_mode), MODE_INT, 0);
6015 if (imode == BLKmode)
6018 compute_mode = imode;
6019 inner = gen_lowpart (imode, inner);
6022 /* Compute a mask of LEN bits, if we can do this on the host machine. */
6023 if (len < HOST_BITS_PER_WIDE_INT)
6024 mask = GEN_INT (((HOST_WIDE_INT) 1 << len) - 1);
6028 /* Now compute the equivalent expression. Make a copy of INNER
6029 for the SET_DEST in case it is a MEM into which we will substitute;
6030 we don't want shared RTL in that case. */
6032 (VOIDmode, copy_rtx (inner),
6033 gen_binary (IOR, compute_mode,
6034 gen_binary (AND, compute_mode,
6035 simplify_gen_unary (NOT, compute_mode,
6041 gen_binary (ASHIFT, compute_mode,
6042 gen_binary (AND, compute_mode,
6044 (compute_mode, SET_SRC (x)),
6052 /* Return an RTX for a reference to LEN bits of INNER. If POS_RTX is nonzero,
6053 it is an RTX that represents a variable starting position; otherwise,
6054 POS is the (constant) starting bit position (counted from the LSB).
6056 INNER may be a USE. This will occur when we started with a bitfield
6057 that went outside the boundary of the object in memory, which is
6058 allowed on most machines. To isolate this case, we produce a USE
6059 whose mode is wide enough and surround the MEM with it. The only
6060 code that understands the USE is this routine. If it is not removed,
6061 it will cause the resulting insn not to match.
6063 UNSIGNEDP is nonzero for an unsigned reference and zero for a
6066 IN_DEST is nonzero if this is a reference in the destination of a
6067 SET. This is used when a ZERO_ or SIGN_EXTRACT isn't needed. If nonzero,
6068 a STRICT_LOW_PART will be used, if zero, ZERO_EXTEND or SIGN_EXTEND will
6071 IN_COMPARE is nonzero if we are in a COMPARE. This means that a
6072 ZERO_EXTRACT should be built even for bits starting at bit 0.
6074 MODE is the desired mode of the result (if IN_DEST == 0).
6076 The result is an RTX for the extraction or NULL_RTX if the target
6080 make_extraction (enum machine_mode mode, rtx inner, HOST_WIDE_INT pos,
6081 rtx pos_rtx, unsigned HOST_WIDE_INT len, int unsignedp,
6082 int in_dest, int in_compare)
6084 /* This mode describes the size of the storage area
6085 to fetch the overall value from. Within that, we
6086 ignore the POS lowest bits, etc. */
6087 enum machine_mode is_mode = GET_MODE (inner);
6088 enum machine_mode inner_mode;
6089 enum machine_mode wanted_inner_mode = byte_mode;
6090 enum machine_mode wanted_inner_reg_mode = word_mode;
6091 enum machine_mode pos_mode = word_mode;
6092 enum machine_mode extraction_mode = word_mode;
6093 enum machine_mode tmode = mode_for_size (len, MODE_INT, 1);
6096 rtx orig_pos_rtx = pos_rtx;
6097 HOST_WIDE_INT orig_pos;
6099 /* Get some information about INNER and get the innermost object. */
6100 if (GET_CODE (inner) == USE)
6101 /* (use:SI (mem:QI foo)) stands for (mem:SI foo). */
6102 /* We don't need to adjust the position because we set up the USE
6103 to pretend that it was a full-word object. */
6104 spans_byte = 1, inner = XEXP (inner, 0);
6105 else if (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
6107 /* If going from (subreg:SI (mem:QI ...)) to (mem:QI ...),
6108 consider just the QI as the memory to extract from.
6109 The subreg adds or removes high bits; its mode is
6110 irrelevant to the meaning of this extraction,
6111 since POS and LEN count from the lsb. */
6112 if (MEM_P (SUBREG_REG (inner)))
6113 is_mode = GET_MODE (SUBREG_REG (inner));
6114 inner = SUBREG_REG (inner);
6116 else if (GET_CODE (inner) == ASHIFT
6117 && GET_CODE (XEXP (inner, 1)) == CONST_INT
6118 && pos_rtx == 0 && pos == 0
6119 && len > (unsigned HOST_WIDE_INT) INTVAL (XEXP (inner, 1)))
6121 /* We're extracting the least significant bits of an rtx
6122 (ashift X (const_int C)), where LEN > C. Extract the
6123 least significant (LEN - C) bits of X, giving an rtx
6124 whose mode is MODE, then shift it left C times. */
6125 new = make_extraction (mode, XEXP (inner, 0),
6126 0, 0, len - INTVAL (XEXP (inner, 1)),
6127 unsignedp, in_dest, in_compare);
6129 return gen_rtx_ASHIFT (mode, new, XEXP (inner, 1));
6132 inner_mode = GET_MODE (inner);
6134 if (pos_rtx && GET_CODE (pos_rtx) == CONST_INT)
6135 pos = INTVAL (pos_rtx), pos_rtx = 0;
6137 /* See if this can be done without an extraction. We never can if the
6138 width of the field is not the same as that of some integer mode. For
6139 registers, we can only avoid the extraction if the position is at the
6140 low-order bit and this is either not in the destination or we have the
6141 appropriate STRICT_LOW_PART operation available.
6143 For MEM, we can avoid an extract if the field starts on an appropriate
6144 boundary and we can change the mode of the memory reference. However,
6145 we cannot directly access the MEM if we have a USE and the underlying
6146 MEM is not TMODE. This combination means that MEM was being used in a
6147 context where bits outside its mode were being referenced; that is only
6148 valid in bit-field insns. */
6150 if (tmode != BLKmode
6151 && ! (spans_byte && inner_mode != tmode)
6152 && ((pos_rtx == 0 && (pos % BITS_PER_WORD) == 0
6156 && have_insn_for (STRICT_LOW_PART, tmode))))
6157 || (MEM_P (inner) && pos_rtx == 0
6159 % (STRICT_ALIGNMENT ? GET_MODE_ALIGNMENT (tmode)
6160 : BITS_PER_UNIT)) == 0
6161 /* We can't do this if we are widening INNER_MODE (it
6162 may not be aligned, for one thing). */
6163 && GET_MODE_BITSIZE (inner_mode) >= GET_MODE_BITSIZE (tmode)
6164 && (inner_mode == tmode
6165 || (! mode_dependent_address_p (XEXP (inner, 0))
6166 && ! MEM_VOLATILE_P (inner))))))
6168 /* If INNER is a MEM, make a new MEM that encompasses just the desired
6169 field. If the original and current mode are the same, we need not
6170 adjust the offset. Otherwise, we do if bytes big endian.
6172 If INNER is not a MEM, get a piece consisting of just the field
6173 of interest (in this case POS % BITS_PER_WORD must be 0). */
6177 HOST_WIDE_INT offset;
6179 /* POS counts from lsb, but make OFFSET count in memory order. */
6180 if (BYTES_BIG_ENDIAN)
6181 offset = (GET_MODE_BITSIZE (is_mode) - len - pos) / BITS_PER_UNIT;
6183 offset = pos / BITS_PER_UNIT;
6185 new = adjust_address_nv (inner, tmode, offset);
6187 else if (REG_P (inner))
6189 if (tmode != inner_mode)
6191 /* We can't call gen_lowpart in a DEST since we
6192 always want a SUBREG (see below) and it would sometimes
6193 return a new hard register. */
6196 HOST_WIDE_INT final_word = pos / BITS_PER_WORD;
6198 if (WORDS_BIG_ENDIAN
6199 && GET_MODE_SIZE (inner_mode) > UNITS_PER_WORD)
6200 final_word = ((GET_MODE_SIZE (inner_mode)
6201 - GET_MODE_SIZE (tmode))
6202 / UNITS_PER_WORD) - final_word;
6204 final_word *= UNITS_PER_WORD;
6205 if (BYTES_BIG_ENDIAN &&
6206 GET_MODE_SIZE (inner_mode) > GET_MODE_SIZE (tmode))
6207 final_word += (GET_MODE_SIZE (inner_mode)
6208 - GET_MODE_SIZE (tmode)) % UNITS_PER_WORD;
6210 /* Avoid creating invalid subregs, for example when
6211 simplifying (x>>32)&255. */
6212 if (final_word >= GET_MODE_SIZE (inner_mode))
6215 new = gen_rtx_SUBREG (tmode, inner, final_word);
6218 new = gen_lowpart (tmode, inner);
6224 new = force_to_mode (inner, tmode,
6225 len >= HOST_BITS_PER_WIDE_INT
6226 ? ~(unsigned HOST_WIDE_INT) 0
6227 : ((unsigned HOST_WIDE_INT) 1 << len) - 1,
6230 /* If this extraction is going into the destination of a SET,
6231 make a STRICT_LOW_PART unless we made a MEM. */
6234 return (MEM_P (new) ? new
6235 : (GET_CODE (new) != SUBREG
6236 ? gen_rtx_CLOBBER (tmode, const0_rtx)
6237 : gen_rtx_STRICT_LOW_PART (VOIDmode, new)));
6242 if (GET_CODE (new) == CONST_INT)
6243 return gen_int_mode (INTVAL (new), mode);
6245 /* If we know that no extraneous bits are set, and that the high
6246 bit is not set, convert the extraction to the cheaper of
6247 sign and zero extension, that are equivalent in these cases. */
6248 if (flag_expensive_optimizations
6249 && (GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT
6250 && ((nonzero_bits (new, tmode)
6251 & ~(((unsigned HOST_WIDE_INT)
6252 GET_MODE_MASK (tmode))
6256 rtx temp = gen_rtx_ZERO_EXTEND (mode, new);
6257 rtx temp1 = gen_rtx_SIGN_EXTEND (mode, new);
6259 /* Prefer ZERO_EXTENSION, since it gives more information to
6261 if (rtx_cost (temp, SET) <= rtx_cost (temp1, SET))
6266 /* Otherwise, sign- or zero-extend unless we already are in the
6269 return (gen_rtx_fmt_e (unsignedp ? ZERO_EXTEND : SIGN_EXTEND,
6273 /* Unless this is a COMPARE or we have a funny memory reference,
6274 don't do anything with zero-extending field extracts starting at
6275 the low-order bit since they are simple AND operations. */
6276 if (pos_rtx == 0 && pos == 0 && ! in_dest
6277 && ! in_compare && ! spans_byte && unsignedp)
6280 /* Unless we are allowed to span bytes or INNER is not MEM, reject this if
6281 we would be spanning bytes or if the position is not a constant and the
6282 length is not 1. In all other cases, we would only be going outside
6283 our object in cases when an original shift would have been
6285 if (! spans_byte && MEM_P (inner)
6286 && ((pos_rtx == 0 && pos + len > GET_MODE_BITSIZE (is_mode))
6287 || (pos_rtx != 0 && len != 1)))
6290 /* Get the mode to use should INNER not be a MEM, the mode for the position,
6291 and the mode for the result. */
6292 if (in_dest && mode_for_extraction (EP_insv, -1) != MAX_MACHINE_MODE)
6294 wanted_inner_reg_mode = mode_for_extraction (EP_insv, 0);
6295 pos_mode = mode_for_extraction (EP_insv, 2);
6296 extraction_mode = mode_for_extraction (EP_insv, 3);
6299 if (! in_dest && unsignedp
6300 && mode_for_extraction (EP_extzv, -1) != MAX_MACHINE_MODE)
6302 wanted_inner_reg_mode = mode_for_extraction (EP_extzv, 1);
6303 pos_mode = mode_for_extraction (EP_extzv, 3);
6304 extraction_mode = mode_for_extraction (EP_extzv, 0);
6307 if (! in_dest && ! unsignedp
6308 && mode_for_extraction (EP_extv, -1) != MAX_MACHINE_MODE)
6310 wanted_inner_reg_mode = mode_for_extraction (EP_extv, 1);
6311 pos_mode = mode_for_extraction (EP_extv, 3);
6312 extraction_mode = mode_for_extraction (EP_extv, 0);
6315 /* Never narrow an object, since that might not be safe. */
6317 if (mode != VOIDmode
6318 && GET_MODE_SIZE (extraction_mode) < GET_MODE_SIZE (mode))
6319 extraction_mode = mode;
6321 if (pos_rtx && GET_MODE (pos_rtx) != VOIDmode
6322 && GET_MODE_SIZE (pos_mode) < GET_MODE_SIZE (GET_MODE (pos_rtx)))
6323 pos_mode = GET_MODE (pos_rtx);
6325 /* If this is not from memory, the desired mode is wanted_inner_reg_mode;
6326 if we have to change the mode of memory and cannot, the desired mode is
6329 wanted_inner_mode = wanted_inner_reg_mode;
6330 else if (inner_mode != wanted_inner_mode
6331 && (mode_dependent_address_p (XEXP (inner, 0))
6332 || MEM_VOLATILE_P (inner)))
6333 wanted_inner_mode = extraction_mode;
6337 if (BITS_BIG_ENDIAN)
6339 /* POS is passed as if BITS_BIG_ENDIAN == 0, so we need to convert it to
6340 BITS_BIG_ENDIAN style. If position is constant, compute new
6341 position. Otherwise, build subtraction.
6342 Note that POS is relative to the mode of the original argument.
6343 If it's a MEM we need to recompute POS relative to that.
6344 However, if we're extracting from (or inserting into) a register,
6345 we want to recompute POS relative to wanted_inner_mode. */
6346 int width = (MEM_P (inner)
6347 ? GET_MODE_BITSIZE (is_mode)
6348 : GET_MODE_BITSIZE (wanted_inner_mode));
6351 pos = width - len - pos;
6354 = gen_rtx_MINUS (GET_MODE (pos_rtx), GEN_INT (width - len), pos_rtx);
6355 /* POS may be less than 0 now, but we check for that below.
6356 Note that it can only be less than 0 if !MEM_P (inner). */
6359 /* If INNER has a wider mode, make it smaller. If this is a constant
6360 extract, try to adjust the byte to point to the byte containing
6362 if (wanted_inner_mode != VOIDmode
6363 && GET_MODE_SIZE (wanted_inner_mode) < GET_MODE_SIZE (is_mode)
6365 && (inner_mode == wanted_inner_mode
6366 || (! mode_dependent_address_p (XEXP (inner, 0))
6367 && ! MEM_VOLATILE_P (inner))))))
6371 /* The computations below will be correct if the machine is big
6372 endian in both bits and bytes or little endian in bits and bytes.
6373 If it is mixed, we must adjust. */
6375 /* If bytes are big endian and we had a paradoxical SUBREG, we must
6376 adjust OFFSET to compensate. */
6377 if (BYTES_BIG_ENDIAN
6379 && GET_MODE_SIZE (inner_mode) < GET_MODE_SIZE (is_mode))
6380 offset -= GET_MODE_SIZE (is_mode) - GET_MODE_SIZE (inner_mode);
6382 /* If this is a constant position, we can move to the desired byte. */
6385 offset += pos / BITS_PER_UNIT;
6386 pos %= GET_MODE_BITSIZE (wanted_inner_mode);
6389 if (BYTES_BIG_ENDIAN != BITS_BIG_ENDIAN
6391 && is_mode != wanted_inner_mode)
6392 offset = (GET_MODE_SIZE (is_mode)
6393 - GET_MODE_SIZE (wanted_inner_mode) - offset);
6395 if (offset != 0 || inner_mode != wanted_inner_mode)
6396 inner = adjust_address_nv (inner, wanted_inner_mode, offset);
6399 /* If INNER is not memory, we can always get it into the proper mode. If we
6400 are changing its mode, POS must be a constant and smaller than the size
6402 else if (!MEM_P (inner))
6404 if (GET_MODE (inner) != wanted_inner_mode
6406 || orig_pos + len > GET_MODE_BITSIZE (wanted_inner_mode)))
6409 inner = force_to_mode (inner, wanted_inner_mode,
6411 || len + orig_pos >= HOST_BITS_PER_WIDE_INT
6412 ? ~(unsigned HOST_WIDE_INT) 0
6413 : ((((unsigned HOST_WIDE_INT) 1 << len) - 1)
6418 /* Adjust mode of POS_RTX, if needed. If we want a wider mode, we
6419 have to zero extend. Otherwise, we can just use a SUBREG. */
6421 && GET_MODE_SIZE (pos_mode) > GET_MODE_SIZE (GET_MODE (pos_rtx)))
6423 rtx temp = gen_rtx_ZERO_EXTEND (pos_mode, pos_rtx);
6425 /* If we know that no extraneous bits are set, and that the high
6426 bit is not set, convert extraction to cheaper one - either
6427 SIGN_EXTENSION or ZERO_EXTENSION, that are equivalent in these
6429 if (flag_expensive_optimizations
6430 && (GET_MODE_BITSIZE (GET_MODE (pos_rtx)) <= HOST_BITS_PER_WIDE_INT
6431 && ((nonzero_bits (pos_rtx, GET_MODE (pos_rtx))
6432 & ~(((unsigned HOST_WIDE_INT)
6433 GET_MODE_MASK (GET_MODE (pos_rtx)))
6437 rtx temp1 = gen_rtx_SIGN_EXTEND (pos_mode, pos_rtx);
6439 /* Prefer ZERO_EXTENSION, since it gives more information to
6441 if (rtx_cost (temp1, SET) < rtx_cost (temp, SET))
6446 else if (pos_rtx != 0
6447 && GET_MODE_SIZE (pos_mode) < GET_MODE_SIZE (GET_MODE (pos_rtx)))
6448 pos_rtx = gen_lowpart (pos_mode, pos_rtx);
6450 /* Make POS_RTX unless we already have it and it is correct. If we don't
6451 have a POS_RTX but we do have an ORIG_POS_RTX, the latter must
6453 if (pos_rtx == 0 && orig_pos_rtx != 0 && INTVAL (orig_pos_rtx) == pos)
6454 pos_rtx = orig_pos_rtx;
6456 else if (pos_rtx == 0)
6457 pos_rtx = GEN_INT (pos);
6459 /* Make the required operation. See if we can use existing rtx. */
6460 new = gen_rtx_fmt_eee (unsignedp ? ZERO_EXTRACT : SIGN_EXTRACT,
6461 extraction_mode, inner, GEN_INT (len), pos_rtx);
6463 new = gen_lowpart (mode, new);
6468 /* See if X contains an ASHIFT of COUNT or more bits that can be commuted
6469 with any other operations in X. Return X without that shift if so. */
6472 extract_left_shift (rtx x, int count)
6474 enum rtx_code code = GET_CODE (x);
6475 enum machine_mode mode = GET_MODE (x);
6481 /* This is the shift itself. If it is wide enough, we will return
6482 either the value being shifted if the shift count is equal to
6483 COUNT or a shift for the difference. */
6484 if (GET_CODE (XEXP (x, 1)) == CONST_INT
6485 && INTVAL (XEXP (x, 1)) >= count)
6486 return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (x, 0),
6487 INTVAL (XEXP (x, 1)) - count);
6491 if ((tem = extract_left_shift (XEXP (x, 0), count)) != 0)
6492 return simplify_gen_unary (code, mode, tem, mode);
6496 case PLUS: case IOR: case XOR: case AND:
6497 /* If we can safely shift this constant and we find the inner shift,
6498 make a new operation. */
6499 if (GET_CODE (XEXP (x, 1)) == CONST_INT
6500 && (INTVAL (XEXP (x, 1)) & ((((HOST_WIDE_INT) 1 << count)) - 1)) == 0
6501 && (tem = extract_left_shift (XEXP (x, 0), count)) != 0)
6502 return gen_binary (code, mode, tem,
6503 GEN_INT (INTVAL (XEXP (x, 1)) >> count));
6514 /* Look at the expression rooted at X. Look for expressions
6515 equivalent to ZERO_EXTRACT, SIGN_EXTRACT, ZERO_EXTEND, SIGN_EXTEND.
6516 Form these expressions.
6518 Return the new rtx, usually just X.
6520 Also, for machines like the VAX that don't have logical shift insns,
6521 try to convert logical to arithmetic shift operations in cases where
6522 they are equivalent. This undoes the canonicalizations to logical
6523 shifts done elsewhere.
6525 We try, as much as possible, to re-use rtl expressions to save memory.
6527 IN_CODE says what kind of expression we are processing. Normally, it is
6528 SET. In a memory address (inside a MEM, PLUS or minus, the latter two
6529 being kludges), it is MEM. When processing the arguments of a comparison
6530 or a COMPARE against zero, it is COMPARE. */
6533 make_compound_operation (rtx x, enum rtx_code in_code)
6535 enum rtx_code code = GET_CODE (x);
6536 enum machine_mode mode = GET_MODE (x);
6537 int mode_width = GET_MODE_BITSIZE (mode);
6539 enum rtx_code next_code;
6545 /* Select the code to be used in recursive calls. Once we are inside an
6546 address, we stay there. If we have a comparison, set to COMPARE,
6547 but once inside, go back to our default of SET. */
6549 next_code = (code == MEM || code == PLUS || code == MINUS ? MEM
6550 : ((code == COMPARE || COMPARISON_P (x))
6551 && XEXP (x, 1) == const0_rtx) ? COMPARE
6552 : in_code == COMPARE ? SET : in_code);
6554 /* Process depending on the code of this operation. If NEW is set
6555 nonzero, it will be returned. */
6560 /* Convert shifts by constants into multiplications if inside
6562 if (in_code == MEM && GET_CODE (XEXP (x, 1)) == CONST_INT
6563 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT
6564 && INTVAL (XEXP (x, 1)) >= 0)
6566 new = make_compound_operation (XEXP (x, 0), next_code);
6567 new = gen_rtx_MULT (mode, new,
6568 GEN_INT ((HOST_WIDE_INT) 1
6569 << INTVAL (XEXP (x, 1))));
6574 /* If the second operand is not a constant, we can't do anything
6576 if (GET_CODE (XEXP (x, 1)) != CONST_INT)
6579 /* If the constant is a power of two minus one and the first operand
6580 is a logical right shift, make an extraction. */
6581 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
6582 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6584 new = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code);
6585 new = make_extraction (mode, new, 0, XEXP (XEXP (x, 0), 1), i, 1,
6586 0, in_code == COMPARE);
6589 /* Same as previous, but for (subreg (lshiftrt ...)) in first op. */
6590 else if (GET_CODE (XEXP (x, 0)) == SUBREG
6591 && subreg_lowpart_p (XEXP (x, 0))
6592 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == LSHIFTRT
6593 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6595 new = make_compound_operation (XEXP (SUBREG_REG (XEXP (x, 0)), 0),
6597 new = make_extraction (GET_MODE (SUBREG_REG (XEXP (x, 0))), new, 0,
6598 XEXP (SUBREG_REG (XEXP (x, 0)), 1), i, 1,
6599 0, in_code == COMPARE);
6601 /* Same as previous, but for (xor/ior (lshiftrt...) (lshiftrt...)). */
6602 else if ((GET_CODE (XEXP (x, 0)) == XOR
6603 || GET_CODE (XEXP (x, 0)) == IOR)
6604 && GET_CODE (XEXP (XEXP (x, 0), 0)) == LSHIFTRT
6605 && GET_CODE (XEXP (XEXP (x, 0), 1)) == LSHIFTRT
6606 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6608 /* Apply the distributive law, and then try to make extractions. */
6609 new = gen_rtx_fmt_ee (GET_CODE (XEXP (x, 0)), mode,
6610 gen_rtx_AND (mode, XEXP (XEXP (x, 0), 0),
6612 gen_rtx_AND (mode, XEXP (XEXP (x, 0), 1),
6614 new = make_compound_operation (new, in_code);
6617 /* If we are have (and (rotate X C) M) and C is larger than the number
6618 of bits in M, this is an extraction. */
6620 else if (GET_CODE (XEXP (x, 0)) == ROTATE
6621 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
6622 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0
6623 && i <= INTVAL (XEXP (XEXP (x, 0), 1)))
6625 new = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code);
6626 new = make_extraction (mode, new,
6627 (GET_MODE_BITSIZE (mode)
6628 - INTVAL (XEXP (XEXP (x, 0), 1))),
6629 NULL_RTX, i, 1, 0, in_code == COMPARE);
6632 /* On machines without logical shifts, if the operand of the AND is
6633 a logical shift and our mask turns off all the propagated sign
6634 bits, we can replace the logical shift with an arithmetic shift. */
6635 else if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
6636 && !have_insn_for (LSHIFTRT, mode)
6637 && have_insn_for (ASHIFTRT, mode)
6638 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
6639 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
6640 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT
6641 && mode_width <= HOST_BITS_PER_WIDE_INT)
6643 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
6645 mask >>= INTVAL (XEXP (XEXP (x, 0), 1));
6646 if ((INTVAL (XEXP (x, 1)) & ~mask) == 0)
6648 gen_rtx_ASHIFTRT (mode,
6649 make_compound_operation
6650 (XEXP (XEXP (x, 0), 0), next_code),
6651 XEXP (XEXP (x, 0), 1)));
6654 /* If the constant is one less than a power of two, this might be
6655 representable by an extraction even if no shift is present.
6656 If it doesn't end up being a ZERO_EXTEND, we will ignore it unless
6657 we are in a COMPARE. */
6658 else if ((i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6659 new = make_extraction (mode,
6660 make_compound_operation (XEXP (x, 0),
6662 0, NULL_RTX, i, 1, 0, in_code == COMPARE);
6664 /* If we are in a comparison and this is an AND with a power of two,
6665 convert this into the appropriate bit extract. */
6666 else if (in_code == COMPARE
6667 && (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0)
6668 new = make_extraction (mode,
6669 make_compound_operation (XEXP (x, 0),
6671 i, NULL_RTX, 1, 1, 0, 1);
6676 /* If the sign bit is known to be zero, replace this with an
6677 arithmetic shift. */
6678 if (have_insn_for (ASHIFTRT, mode)
6679 && ! have_insn_for (LSHIFTRT, mode)
6680 && mode_width <= HOST_BITS_PER_WIDE_INT
6681 && (nonzero_bits (XEXP (x, 0), mode) & (1 << (mode_width - 1))) == 0)
6683 new = gen_rtx_ASHIFTRT (mode,
6684 make_compound_operation (XEXP (x, 0),
6690 /* ... fall through ... */
6696 /* If we have (ashiftrt (ashift foo C1) C2) with C2 >= C1,
6697 this is a SIGN_EXTRACT. */
6698 if (GET_CODE (rhs) == CONST_INT
6699 && GET_CODE (lhs) == ASHIFT
6700 && GET_CODE (XEXP (lhs, 1)) == CONST_INT
6701 && INTVAL (rhs) >= INTVAL (XEXP (lhs, 1)))
6703 new = make_compound_operation (XEXP (lhs, 0), next_code);
6704 new = make_extraction (mode, new,
6705 INTVAL (rhs) - INTVAL (XEXP (lhs, 1)),
6706 NULL_RTX, mode_width - INTVAL (rhs),
6707 code == LSHIFTRT, 0, in_code == COMPARE);
6711 /* See if we have operations between an ASHIFTRT and an ASHIFT.
6712 If so, try to merge the shifts into a SIGN_EXTEND. We could
6713 also do this for some cases of SIGN_EXTRACT, but it doesn't
6714 seem worth the effort; the case checked for occurs on Alpha. */
6717 && ! (GET_CODE (lhs) == SUBREG
6718 && (OBJECT_P (SUBREG_REG (lhs))))
6719 && GET_CODE (rhs) == CONST_INT
6720 && INTVAL (rhs) < HOST_BITS_PER_WIDE_INT
6721 && (new = extract_left_shift (lhs, INTVAL (rhs))) != 0)
6722 new = make_extraction (mode, make_compound_operation (new, next_code),
6723 0, NULL_RTX, mode_width - INTVAL (rhs),
6724 code == LSHIFTRT, 0, in_code == COMPARE);
6729 /* Call ourselves recursively on the inner expression. If we are
6730 narrowing the object and it has a different RTL code from
6731 what it originally did, do this SUBREG as a force_to_mode. */
6733 tem = make_compound_operation (SUBREG_REG (x), in_code);
6734 if (GET_CODE (tem) != GET_CODE (SUBREG_REG (x))
6735 && GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (tem))
6736 && subreg_lowpart_p (x))
6738 rtx newer = force_to_mode (tem, mode, ~(HOST_WIDE_INT) 0,
6741 /* If we have something other than a SUBREG, we might have
6742 done an expansion, so rerun ourselves. */
6743 if (GET_CODE (newer) != SUBREG)
6744 newer = make_compound_operation (newer, in_code);
6749 /* If this is a paradoxical subreg, and the new code is a sign or
6750 zero extension, omit the subreg and widen the extension. If it
6751 is a regular subreg, we can still get rid of the subreg by not
6752 widening so much, or in fact removing the extension entirely. */
6753 if ((GET_CODE (tem) == SIGN_EXTEND
6754 || GET_CODE (tem) == ZERO_EXTEND)
6755 && subreg_lowpart_p (x))
6757 if (GET_MODE_SIZE (mode) > GET_MODE_SIZE (GET_MODE (tem))
6758 || (GET_MODE_SIZE (mode) >
6759 GET_MODE_SIZE (GET_MODE (XEXP (tem, 0)))))
6761 if (! SCALAR_INT_MODE_P (mode))
6763 tem = gen_rtx_fmt_e (GET_CODE (tem), mode, XEXP (tem, 0));
6766 tem = gen_lowpart (mode, XEXP (tem, 0));
6777 x = gen_lowpart (mode, new);
6778 code = GET_CODE (x);
6781 /* Now recursively process each operand of this operation. */
6782 fmt = GET_RTX_FORMAT (code);
6783 for (i = 0; i < GET_RTX_LENGTH (code); i++)
6786 new = make_compound_operation (XEXP (x, i), next_code);
6787 SUBST (XEXP (x, i), new);
6793 /* Given M see if it is a value that would select a field of bits
6794 within an item, but not the entire word. Return -1 if not.
6795 Otherwise, return the starting position of the field, where 0 is the
6798 *PLEN is set to the length of the field. */
6801 get_pos_from_mask (unsigned HOST_WIDE_INT m, unsigned HOST_WIDE_INT *plen)
6803 /* Get the bit number of the first 1 bit from the right, -1 if none. */
6804 int pos = exact_log2 (m & -m);
6808 /* Now shift off the low-order zero bits and see if we have a
6809 power of two minus 1. */
6810 len = exact_log2 ((m >> pos) + 1);
6819 /* See if X can be simplified knowing that we will only refer to it in
6820 MODE and will only refer to those bits that are nonzero in MASK.
6821 If other bits are being computed or if masking operations are done
6822 that select a superset of the bits in MASK, they can sometimes be
6825 Return a possibly simplified expression, but always convert X to
6826 MODE. If X is a CONST_INT, AND the CONST_INT with MASK.
6828 Also, if REG is nonzero and X is a register equal in value to REG,
6831 If JUST_SELECT is nonzero, don't optimize by noticing that bits in MASK
6832 are all off in X. This is used when X will be complemented, by either
6833 NOT, NEG, or XOR. */
6836 force_to_mode (rtx x, enum machine_mode mode, unsigned HOST_WIDE_INT mask,
6837 rtx reg, int just_select)
6839 enum rtx_code code = GET_CODE (x);
6840 int next_select = just_select || code == XOR || code == NOT || code == NEG;
6841 enum machine_mode op_mode;
6842 unsigned HOST_WIDE_INT fuller_mask, nonzero;
6845 /* If this is a CALL or ASM_OPERANDS, don't do anything. Some of the
6846 code below will do the wrong thing since the mode of such an
6847 expression is VOIDmode.
6849 Also do nothing if X is a CLOBBER; this can happen if X was
6850 the return value from a call to gen_lowpart. */
6851 if (code == CALL || code == ASM_OPERANDS || code == CLOBBER)
6854 /* We want to perform the operation is its present mode unless we know
6855 that the operation is valid in MODE, in which case we do the operation
6857 op_mode = ((GET_MODE_CLASS (mode) == GET_MODE_CLASS (GET_MODE (x))
6858 && have_insn_for (code, mode))
6859 ? mode : GET_MODE (x));
6861 /* It is not valid to do a right-shift in a narrower mode
6862 than the one it came in with. */
6863 if ((code == LSHIFTRT || code == ASHIFTRT)
6864 && GET_MODE_BITSIZE (mode) < GET_MODE_BITSIZE (GET_MODE (x)))
6865 op_mode = GET_MODE (x);
6867 /* Truncate MASK to fit OP_MODE. */
6869 mask &= GET_MODE_MASK (op_mode);
6871 /* When we have an arithmetic operation, or a shift whose count we
6872 do not know, we need to assume that all bits up to the highest-order
6873 bit in MASK will be needed. This is how we form such a mask. */
6874 if (mask & ((unsigned HOST_WIDE_INT) 1 << (HOST_BITS_PER_WIDE_INT - 1)))
6875 fuller_mask = ~(unsigned HOST_WIDE_INT) 0;
6877 fuller_mask = (((unsigned HOST_WIDE_INT) 1 << (floor_log2 (mask) + 1))
6880 /* Determine what bits of X are guaranteed to be (non)zero. */
6881 nonzero = nonzero_bits (x, mode);
6883 /* If none of the bits in X are needed, return a zero. */
6884 if (! just_select && (nonzero & mask) == 0)
6887 /* If X is a CONST_INT, return a new one. Do this here since the
6888 test below will fail. */
6889 if (GET_CODE (x) == CONST_INT)
6891 if (SCALAR_INT_MODE_P (mode))
6892 return gen_int_mode (INTVAL (x) & mask, mode);
6895 x = GEN_INT (INTVAL (x) & mask);
6896 return gen_lowpart_common (mode, x);
6900 /* If X is narrower than MODE and we want all the bits in X's mode, just
6901 get X in the proper mode. */
6902 if (GET_MODE_SIZE (GET_MODE (x)) < GET_MODE_SIZE (mode)
6903 && (GET_MODE_MASK (GET_MODE (x)) & ~mask) == 0)
6904 return gen_lowpart (mode, x);
6906 /* If we aren't changing the mode, X is not a SUBREG, and all zero bits in
6907 MASK are already known to be zero in X, we need not do anything. */
6908 if (GET_MODE (x) == mode && code != SUBREG && (~mask & nonzero) == 0)
6914 /* If X is a (clobber (const_int)), return it since we know we are
6915 generating something that won't match. */
6919 /* X is a (use (mem ..)) that was made from a bit-field extraction that
6920 spanned the boundary of the MEM. If we are now masking so it is
6921 within that boundary, we don't need the USE any more. */
6922 if (! BITS_BIG_ENDIAN
6923 && (mask & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
6924 return force_to_mode (XEXP (x, 0), mode, mask, reg, next_select);
6931 x = expand_compound_operation (x);
6932 if (GET_CODE (x) != code)
6933 return force_to_mode (x, mode, mask, reg, next_select);
6937 if (reg != 0 && (rtx_equal_p (get_last_value (reg), x)
6938 || rtx_equal_p (reg, get_last_value (x))))
6943 if (subreg_lowpart_p (x)
6944 /* We can ignore the effect of this SUBREG if it narrows the mode or
6945 if the constant masks to zero all the bits the mode doesn't
6947 && ((GET_MODE_SIZE (GET_MODE (x))
6948 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
6950 & GET_MODE_MASK (GET_MODE (x))
6951 & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (x)))))))
6952 return force_to_mode (SUBREG_REG (x), mode, mask, reg, next_select);
6956 /* If this is an AND with a constant, convert it into an AND
6957 whose constant is the AND of that constant with MASK. If it
6958 remains an AND of MASK, delete it since it is redundant. */
6960 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
6962 x = simplify_and_const_int (x, op_mode, XEXP (x, 0),
6963 mask & INTVAL (XEXP (x, 1)));
6965 /* If X is still an AND, see if it is an AND with a mask that
6966 is just some low-order bits. If so, and it is MASK, we don't
6969 if (GET_CODE (x) == AND && GET_CODE (XEXP (x, 1)) == CONST_INT
6970 && ((INTVAL (XEXP (x, 1)) & GET_MODE_MASK (GET_MODE (x)))
6974 /* If it remains an AND, try making another AND with the bits
6975 in the mode mask that aren't in MASK turned on. If the
6976 constant in the AND is wide enough, this might make a
6977 cheaper constant. */
6979 if (GET_CODE (x) == AND && GET_CODE (XEXP (x, 1)) == CONST_INT
6980 && GET_MODE_MASK (GET_MODE (x)) != mask
6981 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT)
6983 HOST_WIDE_INT cval = (INTVAL (XEXP (x, 1))
6984 | (GET_MODE_MASK (GET_MODE (x)) & ~mask));
6985 int width = GET_MODE_BITSIZE (GET_MODE (x));
6988 /* If MODE is narrower than HOST_WIDE_INT and CVAL is a negative
6989 number, sign extend it. */
6990 if (width > 0 && width < HOST_BITS_PER_WIDE_INT
6991 && (cval & ((HOST_WIDE_INT) 1 << (width - 1))) != 0)
6992 cval |= (HOST_WIDE_INT) -1 << width;
6994 y = gen_binary (AND, GET_MODE (x), XEXP (x, 0), GEN_INT (cval));
6995 if (rtx_cost (y, SET) < rtx_cost (x, SET))
7005 /* In (and (plus FOO C1) M), if M is a mask that just turns off
7006 low-order bits (as in an alignment operation) and FOO is already
7007 aligned to that boundary, mask C1 to that boundary as well.
7008 This may eliminate that PLUS and, later, the AND. */
7011 unsigned int width = GET_MODE_BITSIZE (mode);
7012 unsigned HOST_WIDE_INT smask = mask;
7014 /* If MODE is narrower than HOST_WIDE_INT and mask is a negative
7015 number, sign extend it. */
7017 if (width < HOST_BITS_PER_WIDE_INT
7018 && (smask & ((HOST_WIDE_INT) 1 << (width - 1))) != 0)
7019 smask |= (HOST_WIDE_INT) -1 << width;
7021 if (GET_CODE (XEXP (x, 1)) == CONST_INT
7022 && exact_log2 (- smask) >= 0
7023 && (nonzero_bits (XEXP (x, 0), mode) & ~smask) == 0
7024 && (INTVAL (XEXP (x, 1)) & ~smask) != 0)
7025 return force_to_mode (plus_constant (XEXP (x, 0),
7026 (INTVAL (XEXP (x, 1)) & smask)),
7027 mode, smask, reg, next_select);
7030 /* ... fall through ... */
7033 /* For PLUS, MINUS and MULT, we need any bits less significant than the
7034 most significant bit in MASK since carries from those bits will
7035 affect the bits we are interested in. */
7040 /* If X is (minus C Y) where C's least set bit is larger than any bit
7041 in the mask, then we may replace with (neg Y). */
7042 if (GET_CODE (XEXP (x, 0)) == CONST_INT
7043 && (((unsigned HOST_WIDE_INT) (INTVAL (XEXP (x, 0))
7044 & -INTVAL (XEXP (x, 0))))
7047 x = simplify_gen_unary (NEG, GET_MODE (x), XEXP (x, 1),
7049 return force_to_mode (x, mode, mask, reg, next_select);
7052 /* Similarly, if C contains every bit in the fuller_mask, then we may
7053 replace with (not Y). */
7054 if (GET_CODE (XEXP (x, 0)) == CONST_INT
7055 && ((INTVAL (XEXP (x, 0)) | (HOST_WIDE_INT) fuller_mask)
7056 == INTVAL (XEXP (x, 0))))
7058 x = simplify_gen_unary (NOT, GET_MODE (x),
7059 XEXP (x, 1), GET_MODE (x));
7060 return force_to_mode (x, mode, mask, reg, next_select);
7068 /* If X is (ior (lshiftrt FOO C1) C2), try to commute the IOR and
7069 LSHIFTRT so we end up with an (and (lshiftrt (ior ...) ...) ...)
7070 operation which may be a bitfield extraction. Ensure that the
7071 constant we form is not wider than the mode of X. */
7073 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
7074 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
7075 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
7076 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT
7077 && GET_CODE (XEXP (x, 1)) == CONST_INT
7078 && ((INTVAL (XEXP (XEXP (x, 0), 1))
7079 + floor_log2 (INTVAL (XEXP (x, 1))))
7080 < GET_MODE_BITSIZE (GET_MODE (x)))
7081 && (INTVAL (XEXP (x, 1))
7082 & ~nonzero_bits (XEXP (x, 0), GET_MODE (x))) == 0)
7084 temp = GEN_INT ((INTVAL (XEXP (x, 1)) & mask)
7085 << INTVAL (XEXP (XEXP (x, 0), 1)));
7086 temp = gen_binary (GET_CODE (x), GET_MODE (x),
7087 XEXP (XEXP (x, 0), 0), temp);
7088 x = gen_binary (LSHIFTRT, GET_MODE (x), temp,
7089 XEXP (XEXP (x, 0), 1));
7090 return force_to_mode (x, mode, mask, reg, next_select);
7094 /* For most binary operations, just propagate into the operation and
7095 change the mode if we have an operation of that mode. */
7097 op0 = gen_lowpart (op_mode,
7098 force_to_mode (XEXP (x, 0), mode, mask,
7100 op1 = gen_lowpart (op_mode,
7101 force_to_mode (XEXP (x, 1), mode, mask,
7104 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
7105 x = gen_binary (code, op_mode, op0, op1);
7109 /* For left shifts, do the same, but just for the first operand.
7110 However, we cannot do anything with shifts where we cannot
7111 guarantee that the counts are smaller than the size of the mode
7112 because such a count will have a different meaning in a
7115 if (! (GET_CODE (XEXP (x, 1)) == CONST_INT
7116 && INTVAL (XEXP (x, 1)) >= 0
7117 && INTVAL (XEXP (x, 1)) < GET_MODE_BITSIZE (mode))
7118 && ! (GET_MODE (XEXP (x, 1)) != VOIDmode
7119 && (nonzero_bits (XEXP (x, 1), GET_MODE (XEXP (x, 1)))
7120 < (unsigned HOST_WIDE_INT) GET_MODE_BITSIZE (mode))))
7123 /* If the shift count is a constant and we can do arithmetic in
7124 the mode of the shift, refine which bits we need. Otherwise, use the
7125 conservative form of the mask. */
7126 if (GET_CODE (XEXP (x, 1)) == CONST_INT
7127 && INTVAL (XEXP (x, 1)) >= 0
7128 && INTVAL (XEXP (x, 1)) < GET_MODE_BITSIZE (op_mode)
7129 && GET_MODE_BITSIZE (op_mode) <= HOST_BITS_PER_WIDE_INT)
7130 mask >>= INTVAL (XEXP (x, 1));
7134 op0 = gen_lowpart (op_mode,
7135 force_to_mode (XEXP (x, 0), op_mode,
7136 mask, reg, next_select));
7138 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0))
7139 x = gen_binary (code, op_mode, op0, XEXP (x, 1));
7143 /* Here we can only do something if the shift count is a constant,
7144 this shift constant is valid for the host, and we can do arithmetic
7147 if (GET_CODE (XEXP (x, 1)) == CONST_INT
7148 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT
7149 && GET_MODE_BITSIZE (op_mode) <= HOST_BITS_PER_WIDE_INT)
7151 rtx inner = XEXP (x, 0);
7152 unsigned HOST_WIDE_INT inner_mask;
7154 /* Select the mask of the bits we need for the shift operand. */
7155 inner_mask = mask << INTVAL (XEXP (x, 1));
7157 /* We can only change the mode of the shift if we can do arithmetic
7158 in the mode of the shift and INNER_MASK is no wider than the
7159 width of X's mode. */
7160 if ((inner_mask & ~GET_MODE_MASK (GET_MODE (x))) != 0)
7161 op_mode = GET_MODE (x);
7163 inner = force_to_mode (inner, op_mode, inner_mask, reg, next_select);
7165 if (GET_MODE (x) != op_mode || inner != XEXP (x, 0))
7166 x = gen_binary (LSHIFTRT, op_mode, inner, XEXP (x, 1));
7169 /* If we have (and (lshiftrt FOO C1) C2) where the combination of the
7170 shift and AND produces only copies of the sign bit (C2 is one less
7171 than a power of two), we can do this with just a shift. */
7173 if (GET_CODE (x) == LSHIFTRT
7174 && GET_CODE (XEXP (x, 1)) == CONST_INT
7175 /* The shift puts one of the sign bit copies in the least significant
7177 && ((INTVAL (XEXP (x, 1))
7178 + num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0))))
7179 >= GET_MODE_BITSIZE (GET_MODE (x)))
7180 && exact_log2 (mask + 1) >= 0
7181 /* Number of bits left after the shift must be more than the mask
7183 && ((INTVAL (XEXP (x, 1)) + exact_log2 (mask + 1))
7184 <= GET_MODE_BITSIZE (GET_MODE (x)))
7185 /* Must be more sign bit copies than the mask needs. */
7186 && ((int) num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
7187 >= exact_log2 (mask + 1)))
7188 x = gen_binary (LSHIFTRT, GET_MODE (x), XEXP (x, 0),
7189 GEN_INT (GET_MODE_BITSIZE (GET_MODE (x))
7190 - exact_log2 (mask + 1)));
7195 /* If we are just looking for the sign bit, we don't need this shift at
7196 all, even if it has a variable count. */
7197 if (GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
7198 && (mask == ((unsigned HOST_WIDE_INT) 1
7199 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
7200 return force_to_mode (XEXP (x, 0), mode, mask, reg, next_select);
7202 /* If this is a shift by a constant, get a mask that contains those bits
7203 that are not copies of the sign bit. We then have two cases: If
7204 MASK only includes those bits, this can be a logical shift, which may
7205 allow simplifications. If MASK is a single-bit field not within
7206 those bits, we are requesting a copy of the sign bit and hence can
7207 shift the sign bit to the appropriate location. */
7209 if (GET_CODE (XEXP (x, 1)) == CONST_INT && INTVAL (XEXP (x, 1)) >= 0
7210 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT)
7214 /* If the considered data is wider than HOST_WIDE_INT, we can't
7215 represent a mask for all its bits in a single scalar.
7216 But we only care about the lower bits, so calculate these. */
7218 if (GET_MODE_BITSIZE (GET_MODE (x)) > HOST_BITS_PER_WIDE_INT)
7220 nonzero = ~(HOST_WIDE_INT) 0;
7222 /* GET_MODE_BITSIZE (GET_MODE (x)) - INTVAL (XEXP (x, 1))
7223 is the number of bits a full-width mask would have set.
7224 We need only shift if these are fewer than nonzero can
7225 hold. If not, we must keep all bits set in nonzero. */
7227 if (GET_MODE_BITSIZE (GET_MODE (x)) - INTVAL (XEXP (x, 1))
7228 < HOST_BITS_PER_WIDE_INT)
7229 nonzero >>= INTVAL (XEXP (x, 1))
7230 + HOST_BITS_PER_WIDE_INT
7231 - GET_MODE_BITSIZE (GET_MODE (x)) ;
7235 nonzero = GET_MODE_MASK (GET_MODE (x));
7236 nonzero >>= INTVAL (XEXP (x, 1));
7239 if ((mask & ~nonzero) == 0
7240 || (i = exact_log2 (mask)) >= 0)
7242 x = simplify_shift_const
7243 (x, LSHIFTRT, GET_MODE (x), XEXP (x, 0),
7244 i < 0 ? INTVAL (XEXP (x, 1))
7245 : GET_MODE_BITSIZE (GET_MODE (x)) - 1 - i);
7247 if (GET_CODE (x) != ASHIFTRT)
7248 return force_to_mode (x, mode, mask, reg, next_select);
7252 /* If MASK is 1, convert this to an LSHIFTRT. This can be done
7253 even if the shift count isn't a constant. */
7255 x = gen_binary (LSHIFTRT, GET_MODE (x), XEXP (x, 0), XEXP (x, 1));
7259 /* If this is a zero- or sign-extension operation that just affects bits
7260 we don't care about, remove it. Be sure the call above returned
7261 something that is still a shift. */
7263 if ((GET_CODE (x) == LSHIFTRT || GET_CODE (x) == ASHIFTRT)
7264 && GET_CODE (XEXP (x, 1)) == CONST_INT
7265 && INTVAL (XEXP (x, 1)) >= 0
7266 && (INTVAL (XEXP (x, 1))
7267 <= GET_MODE_BITSIZE (GET_MODE (x)) - (floor_log2 (mask) + 1))
7268 && GET_CODE (XEXP (x, 0)) == ASHIFT
7269 && XEXP (XEXP (x, 0), 1) == XEXP (x, 1))
7270 return force_to_mode (XEXP (XEXP (x, 0), 0), mode, mask,
7277 /* If the shift count is constant and we can do computations
7278 in the mode of X, compute where the bits we care about are.
7279 Otherwise, we can't do anything. Don't change the mode of
7280 the shift or propagate MODE into the shift, though. */
7281 if (GET_CODE (XEXP (x, 1)) == CONST_INT
7282 && INTVAL (XEXP (x, 1)) >= 0)
7284 temp = simplify_binary_operation (code == ROTATE ? ROTATERT : ROTATE,
7285 GET_MODE (x), GEN_INT (mask),
7287 if (temp && GET_CODE (temp) == CONST_INT)
7289 force_to_mode (XEXP (x, 0), GET_MODE (x),
7290 INTVAL (temp), reg, next_select));
7295 /* If we just want the low-order bit, the NEG isn't needed since it
7296 won't change the low-order bit. */
7298 return force_to_mode (XEXP (x, 0), mode, mask, reg, just_select);
7300 /* We need any bits less significant than the most significant bit in
7301 MASK since carries from those bits will affect the bits we are
7307 /* (not FOO) is (xor FOO CONST), so if FOO is an LSHIFTRT, we can do the
7308 same as the XOR case above. Ensure that the constant we form is not
7309 wider than the mode of X. */
7311 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
7312 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
7313 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
7314 && (INTVAL (XEXP (XEXP (x, 0), 1)) + floor_log2 (mask)
7315 < GET_MODE_BITSIZE (GET_MODE (x)))
7316 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT)
7318 temp = gen_int_mode (mask << INTVAL (XEXP (XEXP (x, 0), 1)),
7320 temp = gen_binary (XOR, GET_MODE (x), XEXP (XEXP (x, 0), 0), temp);
7321 x = gen_binary (LSHIFTRT, GET_MODE (x), temp, XEXP (XEXP (x, 0), 1));
7323 return force_to_mode (x, mode, mask, reg, next_select);
7326 /* (and (not FOO) CONST) is (not (or FOO (not CONST))), so we must
7327 use the full mask inside the NOT. */
7331 op0 = gen_lowpart (op_mode,
7332 force_to_mode (XEXP (x, 0), mode, mask,
7334 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0))
7335 x = simplify_gen_unary (code, op_mode, op0, op_mode);
7339 /* (and (ne FOO 0) CONST) can be (and FOO CONST) if CONST is included
7340 in STORE_FLAG_VALUE and FOO has a single bit that might be nonzero,
7341 which is equal to STORE_FLAG_VALUE. */
7342 if ((mask & ~STORE_FLAG_VALUE) == 0 && XEXP (x, 1) == const0_rtx
7343 && exact_log2 (nonzero_bits (XEXP (x, 0), mode)) >= 0
7344 && (nonzero_bits (XEXP (x, 0), mode)
7345 == (unsigned HOST_WIDE_INT) STORE_FLAG_VALUE))
7346 return force_to_mode (XEXP (x, 0), mode, mask, reg, next_select);
7351 /* We have no way of knowing if the IF_THEN_ELSE can itself be
7352 written in a narrower mode. We play it safe and do not do so. */
7355 gen_lowpart (GET_MODE (x),
7356 force_to_mode (XEXP (x, 1), mode,
7357 mask, reg, next_select)));
7359 gen_lowpart (GET_MODE (x),
7360 force_to_mode (XEXP (x, 2), mode,
7361 mask, reg, next_select)));
7368 /* Ensure we return a value of the proper mode. */
7369 return gen_lowpart (mode, x);
7372 /* Return nonzero if X is an expression that has one of two values depending on
7373 whether some other value is zero or nonzero. In that case, we return the
7374 value that is being tested, *PTRUE is set to the value if the rtx being
7375 returned has a nonzero value, and *PFALSE is set to the other alternative.
7377 If we return zero, we set *PTRUE and *PFALSE to X. */
7380 if_then_else_cond (rtx x, rtx *ptrue, rtx *pfalse)
7382 enum machine_mode mode = GET_MODE (x);
7383 enum rtx_code code = GET_CODE (x);
7384 rtx cond0, cond1, true0, true1, false0, false1;
7385 unsigned HOST_WIDE_INT nz;
7387 /* If we are comparing a value against zero, we are done. */
7388 if ((code == NE || code == EQ)
7389 && XEXP (x, 1) == const0_rtx)
7391 *ptrue = (code == NE) ? const_true_rtx : const0_rtx;
7392 *pfalse = (code == NE) ? const0_rtx : const_true_rtx;
7396 /* If this is a unary operation whose operand has one of two values, apply
7397 our opcode to compute those values. */
7398 else if (UNARY_P (x)
7399 && (cond0 = if_then_else_cond (XEXP (x, 0), &true0, &false0)) != 0)
7401 *ptrue = simplify_gen_unary (code, mode, true0, GET_MODE (XEXP (x, 0)));
7402 *pfalse = simplify_gen_unary (code, mode, false0,
7403 GET_MODE (XEXP (x, 0)));
7407 /* If this is a COMPARE, do nothing, since the IF_THEN_ELSE we would
7408 make can't possibly match and would suppress other optimizations. */
7409 else if (code == COMPARE)
7412 /* If this is a binary operation, see if either side has only one of two
7413 values. If either one does or if both do and they are conditional on
7414 the same value, compute the new true and false values. */
7415 else if (BINARY_P (x))
7417 cond0 = if_then_else_cond (XEXP (x, 0), &true0, &false0);
7418 cond1 = if_then_else_cond (XEXP (x, 1), &true1, &false1);
7420 if ((cond0 != 0 || cond1 != 0)
7421 && ! (cond0 != 0 && cond1 != 0 && ! rtx_equal_p (cond0, cond1)))
7423 /* If if_then_else_cond returned zero, then true/false are the
7424 same rtl. We must copy one of them to prevent invalid rtl
7427 true0 = copy_rtx (true0);
7428 else if (cond1 == 0)
7429 true1 = copy_rtx (true1);
7431 *ptrue = gen_binary (code, mode, true0, true1);
7432 *pfalse = gen_binary (code, mode, false0, false1);
7433 return cond0 ? cond0 : cond1;
7436 /* See if we have PLUS, IOR, XOR, MINUS or UMAX, where one of the
7437 operands is zero when the other is nonzero, and vice-versa,
7438 and STORE_FLAG_VALUE is 1 or -1. */
7440 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
7441 && (code == PLUS || code == IOR || code == XOR || code == MINUS
7443 && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT)
7445 rtx op0 = XEXP (XEXP (x, 0), 1);
7446 rtx op1 = XEXP (XEXP (x, 1), 1);
7448 cond0 = XEXP (XEXP (x, 0), 0);
7449 cond1 = XEXP (XEXP (x, 1), 0);
7451 if (COMPARISON_P (cond0)
7452 && COMPARISON_P (cond1)
7453 && ((GET_CODE (cond0) == combine_reversed_comparison_code (cond1)
7454 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0))
7455 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1)))
7456 || ((swap_condition (GET_CODE (cond0))
7457 == combine_reversed_comparison_code (cond1))
7458 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1))
7459 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0))))
7460 && ! side_effects_p (x))
7462 *ptrue = gen_binary (MULT, mode, op0, const_true_rtx);
7463 *pfalse = gen_binary (MULT, mode,
7465 ? simplify_gen_unary (NEG, mode, op1,
7473 /* Similarly for MULT, AND and UMIN, except that for these the result
7475 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
7476 && (code == MULT || code == AND || code == UMIN)
7477 && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT)
7479 cond0 = XEXP (XEXP (x, 0), 0);
7480 cond1 = XEXP (XEXP (x, 1), 0);
7482 if (COMPARISON_P (cond0)
7483 && COMPARISON_P (cond1)
7484 && ((GET_CODE (cond0) == combine_reversed_comparison_code (cond1)
7485 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0))
7486 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1)))
7487 || ((swap_condition (GET_CODE (cond0))
7488 == combine_reversed_comparison_code (cond1))
7489 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1))
7490 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0))))
7491 && ! side_effects_p (x))
7493 *ptrue = *pfalse = const0_rtx;
7499 else if (code == IF_THEN_ELSE)
7501 /* If we have IF_THEN_ELSE already, extract the condition and
7502 canonicalize it if it is NE or EQ. */
7503 cond0 = XEXP (x, 0);
7504 *ptrue = XEXP (x, 1), *pfalse = XEXP (x, 2);
7505 if (GET_CODE (cond0) == NE && XEXP (cond0, 1) == const0_rtx)
7506 return XEXP (cond0, 0);
7507 else if (GET_CODE (cond0) == EQ && XEXP (cond0, 1) == const0_rtx)
7509 *ptrue = XEXP (x, 2), *pfalse = XEXP (x, 1);
7510 return XEXP (cond0, 0);
7516 /* If X is a SUBREG, we can narrow both the true and false values
7517 if the inner expression, if there is a condition. */
7518 else if (code == SUBREG
7519 && 0 != (cond0 = if_then_else_cond (SUBREG_REG (x),
7522 true0 = simplify_gen_subreg (mode, true0,
7523 GET_MODE (SUBREG_REG (x)), SUBREG_BYTE (x));
7524 false0 = simplify_gen_subreg (mode, false0,
7525 GET_MODE (SUBREG_REG (x)), SUBREG_BYTE (x));
7526 if (true0 && false0)
7534 /* If X is a constant, this isn't special and will cause confusions
7535 if we treat it as such. Likewise if it is equivalent to a constant. */
7536 else if (CONSTANT_P (x)
7537 || ((cond0 = get_last_value (x)) != 0 && CONSTANT_P (cond0)))
7540 /* If we're in BImode, canonicalize on 0 and STORE_FLAG_VALUE, as that
7541 will be least confusing to the rest of the compiler. */
7542 else if (mode == BImode)
7544 *ptrue = GEN_INT (STORE_FLAG_VALUE), *pfalse = const0_rtx;
7548 /* If X is known to be either 0 or -1, those are the true and
7549 false values when testing X. */
7550 else if (x == constm1_rtx || x == const0_rtx
7551 || (mode != VOIDmode
7552 && num_sign_bit_copies (x, mode) == GET_MODE_BITSIZE (mode)))
7554 *ptrue = constm1_rtx, *pfalse = const0_rtx;
7558 /* Likewise for 0 or a single bit. */
7559 else if (SCALAR_INT_MODE_P (mode)
7560 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
7561 && exact_log2 (nz = nonzero_bits (x, mode)) >= 0)
7563 *ptrue = gen_int_mode (nz, mode), *pfalse = const0_rtx;
7567 /* Otherwise fail; show no condition with true and false values the same. */
7568 *ptrue = *pfalse = x;
7572 /* Return the value of expression X given the fact that condition COND
7573 is known to be true when applied to REG as its first operand and VAL
7574 as its second. X is known to not be shared and so can be modified in
7577 We only handle the simplest cases, and specifically those cases that
7578 arise with IF_THEN_ELSE expressions. */
7581 known_cond (rtx x, enum rtx_code cond, rtx reg, rtx val)
7583 enum rtx_code code = GET_CODE (x);
7588 if (side_effects_p (x))
7591 /* If either operand of the condition is a floating point value,
7592 then we have to avoid collapsing an EQ comparison. */
7594 && rtx_equal_p (x, reg)
7595 && ! FLOAT_MODE_P (GET_MODE (x))
7596 && ! FLOAT_MODE_P (GET_MODE (val)))
7599 if (cond == UNEQ && rtx_equal_p (x, reg))
7602 /* If X is (abs REG) and we know something about REG's relationship
7603 with zero, we may be able to simplify this. */
7605 if (code == ABS && rtx_equal_p (XEXP (x, 0), reg) && val == const0_rtx)
7608 case GE: case GT: case EQ:
7611 return simplify_gen_unary (NEG, GET_MODE (XEXP (x, 0)),
7613 GET_MODE (XEXP (x, 0)));
7618 /* The only other cases we handle are MIN, MAX, and comparisons if the
7619 operands are the same as REG and VAL. */
7621 else if (COMPARISON_P (x) || COMMUTATIVE_ARITH_P (x))
7623 if (rtx_equal_p (XEXP (x, 0), val))
7624 cond = swap_condition (cond), temp = val, val = reg, reg = temp;
7626 if (rtx_equal_p (XEXP (x, 0), reg) && rtx_equal_p (XEXP (x, 1), val))
7628 if (COMPARISON_P (x))
7630 if (comparison_dominates_p (cond, code))
7631 return const_true_rtx;
7633 code = combine_reversed_comparison_code (x);
7635 && comparison_dominates_p (cond, code))
7640 else if (code == SMAX || code == SMIN
7641 || code == UMIN || code == UMAX)
7643 int unsignedp = (code == UMIN || code == UMAX);
7645 /* Do not reverse the condition when it is NE or EQ.
7646 This is because we cannot conclude anything about
7647 the value of 'SMAX (x, y)' when x is not equal to y,
7648 but we can when x equals y. */
7649 if ((code == SMAX || code == UMAX)
7650 && ! (cond == EQ || cond == NE))
7651 cond = reverse_condition (cond);
7656 return unsignedp ? x : XEXP (x, 1);
7658 return unsignedp ? x : XEXP (x, 0);
7660 return unsignedp ? XEXP (x, 1) : x;
7662 return unsignedp ? XEXP (x, 0) : x;
7669 else if (code == SUBREG)
7671 enum machine_mode inner_mode = GET_MODE (SUBREG_REG (x));
7672 rtx new, r = known_cond (SUBREG_REG (x), cond, reg, val);
7674 if (SUBREG_REG (x) != r)
7676 /* We must simplify subreg here, before we lose track of the
7677 original inner_mode. */
7678 new = simplify_subreg (GET_MODE (x), r,
7679 inner_mode, SUBREG_BYTE (x));
7683 SUBST (SUBREG_REG (x), r);
7688 /* We don't have to handle SIGN_EXTEND here, because even in the
7689 case of replacing something with a modeless CONST_INT, a
7690 CONST_INT is already (supposed to be) a valid sign extension for
7691 its narrower mode, which implies it's already properly
7692 sign-extended for the wider mode. Now, for ZERO_EXTEND, the
7693 story is different. */
7694 else if (code == ZERO_EXTEND)
7696 enum machine_mode inner_mode = GET_MODE (XEXP (x, 0));
7697 rtx new, r = known_cond (XEXP (x, 0), cond, reg, val);
7699 if (XEXP (x, 0) != r)
7701 /* We must simplify the zero_extend here, before we lose
7702 track of the original inner_mode. */
7703 new = simplify_unary_operation (ZERO_EXTEND, GET_MODE (x),
7708 SUBST (XEXP (x, 0), r);
7714 fmt = GET_RTX_FORMAT (code);
7715 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
7718 SUBST (XEXP (x, i), known_cond (XEXP (x, i), cond, reg, val));
7719 else if (fmt[i] == 'E')
7720 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
7721 SUBST (XVECEXP (x, i, j), known_cond (XVECEXP (x, i, j),
7728 /* See if X and Y are equal for the purposes of seeing if we can rewrite an
7729 assignment as a field assignment. */
7732 rtx_equal_for_field_assignment_p (rtx x, rtx y)
7734 if (x == y || rtx_equal_p (x, y))
7737 if (x == 0 || y == 0 || GET_MODE (x) != GET_MODE (y))
7740 /* Check for a paradoxical SUBREG of a MEM compared with the MEM.
7741 Note that all SUBREGs of MEM are paradoxical; otherwise they
7742 would have been rewritten. */
7743 if (MEM_P (x) && GET_CODE (y) == SUBREG
7744 && MEM_P (SUBREG_REG (y))
7745 && rtx_equal_p (SUBREG_REG (y),
7746 gen_lowpart (GET_MODE (SUBREG_REG (y)), x)))
7749 if (MEM_P (y) && GET_CODE (x) == SUBREG
7750 && MEM_P (SUBREG_REG (x))
7751 && rtx_equal_p (SUBREG_REG (x),
7752 gen_lowpart (GET_MODE (SUBREG_REG (x)), y)))
7755 /* We used to see if get_last_value of X and Y were the same but that's
7756 not correct. In one direction, we'll cause the assignment to have
7757 the wrong destination and in the case, we'll import a register into this
7758 insn that might have already have been dead. So fail if none of the
7759 above cases are true. */
7763 /* See if X, a SET operation, can be rewritten as a bit-field assignment.
7764 Return that assignment if so.
7766 We only handle the most common cases. */
7769 make_field_assignment (rtx x)
7771 rtx dest = SET_DEST (x);
7772 rtx src = SET_SRC (x);
7777 unsigned HOST_WIDE_INT len;
7779 enum machine_mode mode;
7781 /* If SRC was (and (not (ashift (const_int 1) POS)) DEST), this is
7782 a clear of a one-bit field. We will have changed it to
7783 (and (rotate (const_int -2) POS) DEST), so check for that. Also check
7786 if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == ROTATE
7787 && GET_CODE (XEXP (XEXP (src, 0), 0)) == CONST_INT
7788 && INTVAL (XEXP (XEXP (src, 0), 0)) == -2
7789 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
7791 assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1),
7794 return gen_rtx_SET (VOIDmode, assign, const0_rtx);
7798 else if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == SUBREG
7799 && subreg_lowpart_p (XEXP (src, 0))
7800 && (GET_MODE_SIZE (GET_MODE (XEXP (src, 0)))
7801 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (src, 0)))))
7802 && GET_CODE (SUBREG_REG (XEXP (src, 0))) == ROTATE
7803 && GET_CODE (XEXP (SUBREG_REG (XEXP (src, 0)), 0)) == CONST_INT
7804 && INTVAL (XEXP (SUBREG_REG (XEXP (src, 0)), 0)) == -2
7805 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
7807 assign = make_extraction (VOIDmode, dest, 0,
7808 XEXP (SUBREG_REG (XEXP (src, 0)), 1),
7811 return gen_rtx_SET (VOIDmode, assign, const0_rtx);
7815 /* If SRC is (ior (ashift (const_int 1) POS) DEST), this is a set of a
7817 else if (GET_CODE (src) == IOR && GET_CODE (XEXP (src, 0)) == ASHIFT
7818 && XEXP (XEXP (src, 0), 0) == const1_rtx
7819 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
7821 assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1),
7824 return gen_rtx_SET (VOIDmode, assign, const1_rtx);
7828 /* The other case we handle is assignments into a constant-position
7829 field. They look like (ior/xor (and DEST C1) OTHER). If C1 represents
7830 a mask that has all one bits except for a group of zero bits and
7831 OTHER is known to have zeros where C1 has ones, this is such an
7832 assignment. Compute the position and length from C1. Shift OTHER
7833 to the appropriate position, force it to the required mode, and
7834 make the extraction. Check for the AND in both operands. */
7836 if (GET_CODE (src) != IOR && GET_CODE (src) != XOR)
7839 rhs = expand_compound_operation (XEXP (src, 0));
7840 lhs = expand_compound_operation (XEXP (src, 1));
7842 if (GET_CODE (rhs) == AND
7843 && GET_CODE (XEXP (rhs, 1)) == CONST_INT
7844 && rtx_equal_for_field_assignment_p (XEXP (rhs, 0), dest))
7845 c1 = INTVAL (XEXP (rhs, 1)), other = lhs;
7846 else if (GET_CODE (lhs) == AND
7847 && GET_CODE (XEXP (lhs, 1)) == CONST_INT
7848 && rtx_equal_for_field_assignment_p (XEXP (lhs, 0), dest))
7849 c1 = INTVAL (XEXP (lhs, 1)), other = rhs;
7853 pos = get_pos_from_mask ((~c1) & GET_MODE_MASK (GET_MODE (dest)), &len);
7854 if (pos < 0 || pos + len > GET_MODE_BITSIZE (GET_MODE (dest))
7855 || GET_MODE_BITSIZE (GET_MODE (dest)) > HOST_BITS_PER_WIDE_INT
7856 || (c1 & nonzero_bits (other, GET_MODE (dest))) != 0)
7859 assign = make_extraction (VOIDmode, dest, pos, NULL_RTX, len, 1, 1, 0);
7863 /* The mode to use for the source is the mode of the assignment, or of
7864 what is inside a possible STRICT_LOW_PART. */
7865 mode = (GET_CODE (assign) == STRICT_LOW_PART
7866 ? GET_MODE (XEXP (assign, 0)) : GET_MODE (assign));
7868 /* Shift OTHER right POS places and make it the source, restricting it
7869 to the proper length and mode. */
7871 src = force_to_mode (simplify_shift_const (NULL_RTX, LSHIFTRT,
7872 GET_MODE (src), other, pos),
7874 GET_MODE_BITSIZE (mode) >= HOST_BITS_PER_WIDE_INT
7875 ? ~(unsigned HOST_WIDE_INT) 0
7876 : ((unsigned HOST_WIDE_INT) 1 << len) - 1,
7879 /* If SRC is masked by an AND that does not make a difference in
7880 the value being stored, strip it. */
7881 if (GET_CODE (assign) == ZERO_EXTRACT
7882 && GET_CODE (XEXP (assign, 1)) == CONST_INT
7883 && INTVAL (XEXP (assign, 1)) < HOST_BITS_PER_WIDE_INT
7884 && GET_CODE (src) == AND
7885 && GET_CODE (XEXP (src, 1)) == CONST_INT
7886 && ((unsigned HOST_WIDE_INT) INTVAL (XEXP (src, 1))
7887 == ((unsigned HOST_WIDE_INT) 1 << INTVAL (XEXP (assign, 1))) - 1))
7888 src = XEXP (src, 0);
7890 return gen_rtx_SET (VOIDmode, assign, src);
7893 /* See if X is of the form (+ (* a c) (* b c)) and convert to (* (+ a b) c)
7897 apply_distributive_law (rtx x)
7899 enum rtx_code code = GET_CODE (x);
7900 enum rtx_code inner_code;
7901 rtx lhs, rhs, other;
7904 /* Distributivity is not true for floating point as it can change the
7905 value. So we don't do it unless -funsafe-math-optimizations. */
7906 if (FLOAT_MODE_P (GET_MODE (x))
7907 && ! flag_unsafe_math_optimizations)
7910 /* The outer operation can only be one of the following: */
7911 if (code != IOR && code != AND && code != XOR
7912 && code != PLUS && code != MINUS)
7918 /* If either operand is a primitive we can't do anything, so get out
7920 if (OBJECT_P (lhs) || OBJECT_P (rhs))
7923 lhs = expand_compound_operation (lhs);
7924 rhs = expand_compound_operation (rhs);
7925 inner_code = GET_CODE (lhs);
7926 if (inner_code != GET_CODE (rhs))
7929 /* See if the inner and outer operations distribute. */
7936 /* These all distribute except over PLUS. */
7937 if (code == PLUS || code == MINUS)
7942 if (code != PLUS && code != MINUS)
7947 /* This is also a multiply, so it distributes over everything. */
7951 /* Non-paradoxical SUBREGs distributes over all operations, provided
7952 the inner modes and byte offsets are the same, this is an extraction
7953 of a low-order part, we don't convert an fp operation to int or
7954 vice versa, and we would not be converting a single-word
7955 operation into a multi-word operation. The latter test is not
7956 required, but it prevents generating unneeded multi-word operations.
7957 Some of the previous tests are redundant given the latter test, but
7958 are retained because they are required for correctness.
7960 We produce the result slightly differently in this case. */
7962 if (GET_MODE (SUBREG_REG (lhs)) != GET_MODE (SUBREG_REG (rhs))
7963 || SUBREG_BYTE (lhs) != SUBREG_BYTE (rhs)
7964 || ! subreg_lowpart_p (lhs)
7965 || (GET_MODE_CLASS (GET_MODE (lhs))
7966 != GET_MODE_CLASS (GET_MODE (SUBREG_REG (lhs))))
7967 || (GET_MODE_SIZE (GET_MODE (lhs))
7968 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs))))
7969 || GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs))) > UNITS_PER_WORD)
7972 tem = gen_binary (code, GET_MODE (SUBREG_REG (lhs)),
7973 SUBREG_REG (lhs), SUBREG_REG (rhs));
7974 return gen_lowpart (GET_MODE (x), tem);
7980 /* Set LHS and RHS to the inner operands (A and B in the example
7981 above) and set OTHER to the common operand (C in the example).
7982 There is only one way to do this unless the inner operation is
7984 if (COMMUTATIVE_ARITH_P (lhs)
7985 && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 0)))
7986 other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 1);
7987 else if (COMMUTATIVE_ARITH_P (lhs)
7988 && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 1)))
7989 other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 0);
7990 else if (COMMUTATIVE_ARITH_P (lhs)
7991 && rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 0)))
7992 other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 1);
7993 else if (rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 1)))
7994 other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 0);
7998 /* Form the new inner operation, seeing if it simplifies first. */
7999 tem = gen_binary (code, GET_MODE (x), lhs, rhs);
8001 /* There is one exception to the general way of distributing:
8002 (a | c) ^ (b | c) -> (a ^ b) & ~c */
8003 if (code == XOR && inner_code == IOR)
8006 other = simplify_gen_unary (NOT, GET_MODE (x), other, GET_MODE (x));
8009 /* We may be able to continuing distributing the result, so call
8010 ourselves recursively on the inner operation before forming the
8011 outer operation, which we return. */
8012 return gen_binary (inner_code, GET_MODE (x),
8013 apply_distributive_law (tem), other);
8016 /* We have X, a logical `and' of VAROP with the constant CONSTOP, to be done
8019 Return an equivalent form, if different from X. Otherwise, return X. If
8020 X is zero, we are to always construct the equivalent form. */
8023 simplify_and_const_int (rtx x, enum machine_mode mode, rtx varop,
8024 unsigned HOST_WIDE_INT constop)
8026 unsigned HOST_WIDE_INT nonzero;
8029 /* Simplify VAROP knowing that we will be only looking at some of the
8032 Note by passing in CONSTOP, we guarantee that the bits not set in
8033 CONSTOP are not significant and will never be examined. We must
8034 ensure that is the case by explicitly masking out those bits
8035 before returning. */
8036 varop = force_to_mode (varop, mode, constop, NULL_RTX, 0);
8038 /* If VAROP is a CLOBBER, we will fail so return it. */
8039 if (GET_CODE (varop) == CLOBBER)
8042 /* If VAROP is a CONST_INT, then we need to apply the mask in CONSTOP
8043 to VAROP and return the new constant. */
8044 if (GET_CODE (varop) == CONST_INT)
8045 return GEN_INT (trunc_int_for_mode (INTVAL (varop) & constop, mode));
8047 /* See what bits may be nonzero in VAROP. Unlike the general case of
8048 a call to nonzero_bits, here we don't care about bits outside
8051 nonzero = nonzero_bits (varop, mode) & GET_MODE_MASK (mode);
8053 /* Turn off all bits in the constant that are known to already be zero.
8054 Thus, if the AND isn't needed at all, we will have CONSTOP == NONZERO_BITS
8055 which is tested below. */
8059 /* If we don't have any bits left, return zero. */
8063 /* If VAROP is a NEG of something known to be zero or 1 and CONSTOP is
8064 a power of two, we can replace this with an ASHIFT. */
8065 if (GET_CODE (varop) == NEG && nonzero_bits (XEXP (varop, 0), mode) == 1
8066 && (i = exact_log2 (constop)) >= 0)
8067 return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (varop, 0), i);
8069 /* If VAROP is an IOR or XOR, apply the AND to both branches of the IOR
8070 or XOR, then try to apply the distributive law. This may eliminate
8071 operations if either branch can be simplified because of the AND.
8072 It may also make some cases more complex, but those cases probably
8073 won't match a pattern either with or without this. */
8075 if (GET_CODE (varop) == IOR || GET_CODE (varop) == XOR)
8079 apply_distributive_law
8080 (gen_binary (GET_CODE (varop), GET_MODE (varop),
8081 simplify_and_const_int (NULL_RTX, GET_MODE (varop),
8082 XEXP (varop, 0), constop),
8083 simplify_and_const_int (NULL_RTX, GET_MODE (varop),
8084 XEXP (varop, 1), constop))));
8086 /* If VAROP is PLUS, and the constant is a mask of low bite, distribute
8087 the AND and see if one of the operands simplifies to zero. If so, we
8088 may eliminate it. */
8090 if (GET_CODE (varop) == PLUS
8091 && exact_log2 (constop + 1) >= 0)
8095 o0 = simplify_and_const_int (NULL_RTX, mode, XEXP (varop, 0), constop);
8096 o1 = simplify_and_const_int (NULL_RTX, mode, XEXP (varop, 1), constop);
8097 if (o0 == const0_rtx)
8099 if (o1 == const0_rtx)
8103 /* Get VAROP in MODE. Try to get a SUBREG if not. Don't make a new SUBREG
8104 if we already had one (just check for the simplest cases). */
8105 if (x && GET_CODE (XEXP (x, 0)) == SUBREG
8106 && GET_MODE (XEXP (x, 0)) == mode
8107 && SUBREG_REG (XEXP (x, 0)) == varop)
8108 varop = XEXP (x, 0);
8110 varop = gen_lowpart (mode, varop);
8112 /* If we can't make the SUBREG, try to return what we were given. */
8113 if (GET_CODE (varop) == CLOBBER)
8114 return x ? x : varop;
8116 /* If we are only masking insignificant bits, return VAROP. */
8117 if (constop == nonzero)
8121 /* Otherwise, return an AND. */
8122 constop = trunc_int_for_mode (constop, mode);
8123 /* See how much, if any, of X we can use. */
8124 if (x == 0 || GET_CODE (x) != AND || GET_MODE (x) != mode)
8125 x = gen_binary (AND, mode, varop, GEN_INT (constop));
8129 if (GET_CODE (XEXP (x, 1)) != CONST_INT
8130 || (unsigned HOST_WIDE_INT) INTVAL (XEXP (x, 1)) != constop)
8131 SUBST (XEXP (x, 1), GEN_INT (constop));
8133 SUBST (XEXP (x, 0), varop);
8140 /* Given a REG, X, compute which bits in X can be nonzero.
8141 We don't care about bits outside of those defined in MODE.
8143 For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is
8144 a shift, AND, or zero_extract, we can do better. */
8147 reg_nonzero_bits_for_combine (rtx x, enum machine_mode mode,
8148 rtx known_x ATTRIBUTE_UNUSED,
8149 enum machine_mode known_mode ATTRIBUTE_UNUSED,
8150 unsigned HOST_WIDE_INT known_ret ATTRIBUTE_UNUSED,
8151 unsigned HOST_WIDE_INT *nonzero)
8155 /* If X is a register whose nonzero bits value is current, use it.
8156 Otherwise, if X is a register whose value we can find, use that
8157 value. Otherwise, use the previously-computed global nonzero bits
8158 for this register. */
8160 if (reg_stat[REGNO (x)].last_set_value != 0
8161 && (reg_stat[REGNO (x)].last_set_mode == mode
8162 || (GET_MODE_CLASS (reg_stat[REGNO (x)].last_set_mode) == MODE_INT
8163 && GET_MODE_CLASS (mode) == MODE_INT))
8164 && (reg_stat[REGNO (x)].last_set_label == label_tick
8165 || (REGNO (x) >= FIRST_PSEUDO_REGISTER
8166 && REG_N_SETS (REGNO (x)) == 1
8167 && ! REGNO_REG_SET_P (ENTRY_BLOCK_PTR->next_bb->global_live_at_start,
8169 && INSN_CUID (reg_stat[REGNO (x)].last_set) < subst_low_cuid)
8171 *nonzero &= reg_stat[REGNO (x)].last_set_nonzero_bits;
8175 tem = get_last_value (x);
8179 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
8180 /* If X is narrower than MODE and TEM is a non-negative
8181 constant that would appear negative in the mode of X,
8182 sign-extend it for use in reg_nonzero_bits because some
8183 machines (maybe most) will actually do the sign-extension
8184 and this is the conservative approach.
8186 ??? For 2.5, try to tighten up the MD files in this regard
8187 instead of this kludge. */
8189 if (GET_MODE_BITSIZE (GET_MODE (x)) < GET_MODE_BITSIZE (mode)
8190 && GET_CODE (tem) == CONST_INT
8192 && 0 != (INTVAL (tem)
8193 & ((HOST_WIDE_INT) 1
8194 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
8195 tem = GEN_INT (INTVAL (tem)
8196 | ((HOST_WIDE_INT) (-1)
8197 << GET_MODE_BITSIZE (GET_MODE (x))));
8201 else if (nonzero_sign_valid && reg_stat[REGNO (x)].nonzero_bits)
8203 unsigned HOST_WIDE_INT mask = reg_stat[REGNO (x)].nonzero_bits;
8205 if (GET_MODE_BITSIZE (GET_MODE (x)) < GET_MODE_BITSIZE (mode))
8206 /* We don't know anything about the upper bits. */
8207 mask |= GET_MODE_MASK (mode) ^ GET_MODE_MASK (GET_MODE (x));
8214 /* Return the number of bits at the high-order end of X that are known to
8215 be equal to the sign bit. X will be used in mode MODE; if MODE is
8216 VOIDmode, X will be used in its own mode. The returned value will always
8217 be between 1 and the number of bits in MODE. */
8220 reg_num_sign_bit_copies_for_combine (rtx x, enum machine_mode mode,
8221 rtx known_x ATTRIBUTE_UNUSED,
8222 enum machine_mode known_mode
8224 unsigned int known_ret ATTRIBUTE_UNUSED,
8225 unsigned int *result)
8229 if (reg_stat[REGNO (x)].last_set_value != 0
8230 && reg_stat[REGNO (x)].last_set_mode == mode
8231 && (reg_stat[REGNO (x)].last_set_label == label_tick
8232 || (REGNO (x) >= FIRST_PSEUDO_REGISTER
8233 && REG_N_SETS (REGNO (x)) == 1
8234 && ! REGNO_REG_SET_P (ENTRY_BLOCK_PTR->next_bb->global_live_at_start,
8236 && INSN_CUID (reg_stat[REGNO (x)].last_set) < subst_low_cuid)
8238 *result = reg_stat[REGNO (x)].last_set_sign_bit_copies;
8242 tem = get_last_value (x);
8246 if (nonzero_sign_valid && reg_stat[REGNO (x)].sign_bit_copies != 0
8247 && GET_MODE_BITSIZE (GET_MODE (x)) == GET_MODE_BITSIZE (mode))
8248 *result = reg_stat[REGNO (x)].sign_bit_copies;
8253 /* Return the number of "extended" bits there are in X, when interpreted
8254 as a quantity in MODE whose signedness is indicated by UNSIGNEDP. For
8255 unsigned quantities, this is the number of high-order zero bits.
8256 For signed quantities, this is the number of copies of the sign bit
8257 minus 1. In both case, this function returns the number of "spare"
8258 bits. For example, if two quantities for which this function returns
8259 at least 1 are added, the addition is known not to overflow.
8261 This function will always return 0 unless called during combine, which
8262 implies that it must be called from a define_split. */
8265 extended_count (rtx x, enum machine_mode mode, int unsignedp)
8267 if (nonzero_sign_valid == 0)
8271 ? (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
8272 ? (unsigned int) (GET_MODE_BITSIZE (mode) - 1
8273 - floor_log2 (nonzero_bits (x, mode)))
8275 : num_sign_bit_copies (x, mode) - 1);
8278 /* This function is called from `simplify_shift_const' to merge two
8279 outer operations. Specifically, we have already found that we need
8280 to perform operation *POP0 with constant *PCONST0 at the outermost
8281 position. We would now like to also perform OP1 with constant CONST1
8282 (with *POP0 being done last).
8284 Return 1 if we can do the operation and update *POP0 and *PCONST0 with
8285 the resulting operation. *PCOMP_P is set to 1 if we would need to
8286 complement the innermost operand, otherwise it is unchanged.
8288 MODE is the mode in which the operation will be done. No bits outside
8289 the width of this mode matter. It is assumed that the width of this mode
8290 is smaller than or equal to HOST_BITS_PER_WIDE_INT.
8292 If *POP0 or OP1 are UNKNOWN, it means no operation is required. Only NEG, PLUS,
8293 IOR, XOR, and AND are supported. We may set *POP0 to SET if the proper
8294 result is simply *PCONST0.
8296 If the resulting operation cannot be expressed as one operation, we
8297 return 0 and do not change *POP0, *PCONST0, and *PCOMP_P. */
8300 merge_outer_ops (enum rtx_code *pop0, HOST_WIDE_INT *pconst0, enum rtx_code op1, HOST_WIDE_INT const1, enum machine_mode mode, int *pcomp_p)
8302 enum rtx_code op0 = *pop0;
8303 HOST_WIDE_INT const0 = *pconst0;
8305 const0 &= GET_MODE_MASK (mode);
8306 const1 &= GET_MODE_MASK (mode);
8308 /* If OP0 is an AND, clear unimportant bits in CONST1. */
8312 /* If OP0 or OP1 is UNKNOWN, this is easy. Similarly if they are the same or
8315 if (op1 == UNKNOWN || op0 == SET)
8318 else if (op0 == UNKNOWN)
8319 op0 = op1, const0 = const1;
8321 else if (op0 == op1)
8345 /* Otherwise, if either is a PLUS or NEG, we can't do anything. */
8346 else if (op0 == PLUS || op1 == PLUS || op0 == NEG || op1 == NEG)
8349 /* If the two constants aren't the same, we can't do anything. The
8350 remaining six cases can all be done. */
8351 else if (const0 != const1)
8359 /* (a & b) | b == b */
8361 else /* op1 == XOR */
8362 /* (a ^ b) | b == a | b */
8368 /* (a & b) ^ b == (~a) & b */
8369 op0 = AND, *pcomp_p = 1;
8370 else /* op1 == IOR */
8371 /* (a | b) ^ b == a & ~b */
8372 op0 = AND, const0 = ~const0;
8377 /* (a | b) & b == b */
8379 else /* op1 == XOR */
8380 /* (a ^ b) & b) == (~a) & b */
8387 /* Check for NO-OP cases. */
8388 const0 &= GET_MODE_MASK (mode);
8390 && (op0 == IOR || op0 == XOR || op0 == PLUS))
8392 else if (const0 == 0 && op0 == AND)
8394 else if ((unsigned HOST_WIDE_INT) const0 == GET_MODE_MASK (mode)
8398 /* ??? Slightly redundant with the above mask, but not entirely.
8399 Moving this above means we'd have to sign-extend the mode mask
8400 for the final test. */
8401 const0 = trunc_int_for_mode (const0, mode);
8409 /* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift.
8410 The result of the shift is RESULT_MODE. X, if nonzero, is an expression
8411 that we started with.
8413 The shift is normally computed in the widest mode we find in VAROP, as
8414 long as it isn't a different number of words than RESULT_MODE. Exceptions
8415 are ASHIFTRT and ROTATE, which are always done in their original mode, */
8418 simplify_shift_const (rtx x, enum rtx_code code,
8419 enum machine_mode result_mode, rtx varop,
8422 enum rtx_code orig_code = code;
8425 enum machine_mode mode = result_mode;
8426 enum machine_mode shift_mode, tmode;
8427 unsigned int mode_words
8428 = (GET_MODE_SIZE (mode) + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD;
8429 /* We form (outer_op (code varop count) (outer_const)). */
8430 enum rtx_code outer_op = UNKNOWN;
8431 HOST_WIDE_INT outer_const = 0;
8433 int complement_p = 0;
8436 /* Make sure and truncate the "natural" shift on the way in. We don't
8437 want to do this inside the loop as it makes it more difficult to
8439 if (SHIFT_COUNT_TRUNCATED)
8440 orig_count &= GET_MODE_BITSIZE (mode) - 1;
8442 /* If we were given an invalid count, don't do anything except exactly
8443 what was requested. */
8445 if (orig_count < 0 || orig_count >= (int) GET_MODE_BITSIZE (mode))
8450 return gen_rtx_fmt_ee (code, mode, varop, GEN_INT (orig_count));
8455 /* Unless one of the branches of the `if' in this loop does a `continue',
8456 we will `break' the loop after the `if'. */
8460 /* If we have an operand of (clobber (const_int 0)), just return that
8462 if (GET_CODE (varop) == CLOBBER)
8465 /* If we discovered we had to complement VAROP, leave. Making a NOT
8466 here would cause an infinite loop. */
8470 /* Convert ROTATERT to ROTATE. */
8471 if (code == ROTATERT)
8473 unsigned int bitsize = GET_MODE_BITSIZE (result_mode);;
8475 if (VECTOR_MODE_P (result_mode))
8476 count = bitsize / GET_MODE_NUNITS (result_mode) - count;
8478 count = bitsize - count;
8481 /* We need to determine what mode we will do the shift in. If the
8482 shift is a right shift or a ROTATE, we must always do it in the mode
8483 it was originally done in. Otherwise, we can do it in MODE, the
8484 widest mode encountered. */
8486 = (code == ASHIFTRT || code == LSHIFTRT || code == ROTATE
8487 ? result_mode : mode);
8489 /* Handle cases where the count is greater than the size of the mode
8490 minus 1. For ASHIFT, use the size minus one as the count (this can
8491 occur when simplifying (lshiftrt (ashiftrt ..))). For rotates,
8492 take the count modulo the size. For other shifts, the result is
8495 Since these shifts are being produced by the compiler by combining
8496 multiple operations, each of which are defined, we know what the
8497 result is supposed to be. */
8499 if (count > (unsigned int) (GET_MODE_BITSIZE (shift_mode) - 1))
8501 if (code == ASHIFTRT)
8502 count = GET_MODE_BITSIZE (shift_mode) - 1;
8503 else if (code == ROTATE || code == ROTATERT)
8504 count %= GET_MODE_BITSIZE (shift_mode);
8507 /* We can't simply return zero because there may be an
8515 /* An arithmetic right shift of a quantity known to be -1 or 0
8517 if (code == ASHIFTRT
8518 && (num_sign_bit_copies (varop, shift_mode)
8519 == GET_MODE_BITSIZE (shift_mode)))
8525 /* If we are doing an arithmetic right shift and discarding all but
8526 the sign bit copies, this is equivalent to doing a shift by the
8527 bitsize minus one. Convert it into that shift because it will often
8528 allow other simplifications. */
8530 if (code == ASHIFTRT
8531 && (count + num_sign_bit_copies (varop, shift_mode)
8532 >= GET_MODE_BITSIZE (shift_mode)))
8533 count = GET_MODE_BITSIZE (shift_mode) - 1;
8535 /* We simplify the tests below and elsewhere by converting
8536 ASHIFTRT to LSHIFTRT if we know the sign bit is clear.
8537 `make_compound_operation' will convert it to an ASHIFTRT for
8538 those machines (such as VAX) that don't have an LSHIFTRT. */
8539 if (GET_MODE_BITSIZE (shift_mode) <= HOST_BITS_PER_WIDE_INT
8541 && ((nonzero_bits (varop, shift_mode)
8542 & ((HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (shift_mode) - 1)))
8546 if (code == LSHIFTRT
8547 && GET_MODE_BITSIZE (shift_mode) <= HOST_BITS_PER_WIDE_INT
8548 && !(nonzero_bits (varop, shift_mode) >> count))
8551 && GET_MODE_BITSIZE (shift_mode) <= HOST_BITS_PER_WIDE_INT
8552 && !((nonzero_bits (varop, shift_mode) << count)
8553 & GET_MODE_MASK (shift_mode)))
8556 switch (GET_CODE (varop))
8562 new = expand_compound_operation (varop);
8571 /* If we have (xshiftrt (mem ...) C) and C is MODE_WIDTH
8572 minus the width of a smaller mode, we can do this with a
8573 SIGN_EXTEND or ZERO_EXTEND from the narrower memory location. */
8574 if ((code == ASHIFTRT || code == LSHIFTRT)
8575 && ! mode_dependent_address_p (XEXP (varop, 0))
8576 && ! MEM_VOLATILE_P (varop)
8577 && (tmode = mode_for_size (GET_MODE_BITSIZE (mode) - count,
8578 MODE_INT, 1)) != BLKmode)
8580 new = adjust_address_nv (varop, tmode,
8581 BYTES_BIG_ENDIAN ? 0
8582 : count / BITS_PER_UNIT);
8584 varop = gen_rtx_fmt_e (code == ASHIFTRT ? SIGN_EXTEND
8585 : ZERO_EXTEND, mode, new);
8592 /* Similar to the case above, except that we can only do this if
8593 the resulting mode is the same as that of the underlying
8594 MEM and adjust the address depending on the *bits* endianness
8595 because of the way that bit-field extract insns are defined. */
8596 if ((code == ASHIFTRT || code == LSHIFTRT)
8597 && (tmode = mode_for_size (GET_MODE_BITSIZE (mode) - count,
8598 MODE_INT, 1)) != BLKmode
8599 && tmode == GET_MODE (XEXP (varop, 0)))
8601 if (BITS_BIG_ENDIAN)
8602 new = XEXP (varop, 0);
8605 new = copy_rtx (XEXP (varop, 0));
8606 SUBST (XEXP (new, 0),
8607 plus_constant (XEXP (new, 0),
8608 count / BITS_PER_UNIT));
8611 varop = gen_rtx_fmt_e (code == ASHIFTRT ? SIGN_EXTEND
8612 : ZERO_EXTEND, mode, new);
8619 /* If VAROP is a SUBREG, strip it as long as the inner operand has
8620 the same number of words as what we've seen so far. Then store
8621 the widest mode in MODE. */
8622 if (subreg_lowpart_p (varop)
8623 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop)))
8624 > GET_MODE_SIZE (GET_MODE (varop)))
8625 && (unsigned int) ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop)))
8626 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
8629 varop = SUBREG_REG (varop);
8630 if (GET_MODE_SIZE (GET_MODE (varop)) > GET_MODE_SIZE (mode))
8631 mode = GET_MODE (varop);
8637 /* Some machines use MULT instead of ASHIFT because MULT
8638 is cheaper. But it is still better on those machines to
8639 merge two shifts into one. */
8640 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
8641 && exact_log2 (INTVAL (XEXP (varop, 1))) >= 0)
8644 = gen_binary (ASHIFT, GET_MODE (varop), XEXP (varop, 0),
8645 GEN_INT (exact_log2 (INTVAL (XEXP (varop, 1)))));
8651 /* Similar, for when divides are cheaper. */
8652 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
8653 && exact_log2 (INTVAL (XEXP (varop, 1))) >= 0)
8656 = gen_binary (LSHIFTRT, GET_MODE (varop), XEXP (varop, 0),
8657 GEN_INT (exact_log2 (INTVAL (XEXP (varop, 1)))));
8663 /* If we are extracting just the sign bit of an arithmetic
8664 right shift, that shift is not needed. However, the sign
8665 bit of a wider mode may be different from what would be
8666 interpreted as the sign bit in a narrower mode, so, if
8667 the result is narrower, don't discard the shift. */
8668 if (code == LSHIFTRT
8669 && count == (unsigned int) (GET_MODE_BITSIZE (result_mode) - 1)
8670 && (GET_MODE_BITSIZE (result_mode)
8671 >= GET_MODE_BITSIZE (GET_MODE (varop))))
8673 varop = XEXP (varop, 0);
8677 /* ... fall through ... */
8682 /* Here we have two nested shifts. The result is usually the
8683 AND of a new shift with a mask. We compute the result below. */
8684 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
8685 && INTVAL (XEXP (varop, 1)) >= 0
8686 && INTVAL (XEXP (varop, 1)) < GET_MODE_BITSIZE (GET_MODE (varop))
8687 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
8688 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
8690 enum rtx_code first_code = GET_CODE (varop);
8691 unsigned int first_count = INTVAL (XEXP (varop, 1));
8692 unsigned HOST_WIDE_INT mask;
8695 /* We have one common special case. We can't do any merging if
8696 the inner code is an ASHIFTRT of a smaller mode. However, if
8697 we have (ashift:M1 (subreg:M1 (ashiftrt:M2 FOO C1) 0) C2)
8698 with C2 == GET_MODE_BITSIZE (M1) - GET_MODE_BITSIZE (M2),
8699 we can convert it to
8700 (ashiftrt:M1 (ashift:M1 (and:M1 (subreg:M1 FOO 0 C2) C3) C1).
8701 This simplifies certain SIGN_EXTEND operations. */
8702 if (code == ASHIFT && first_code == ASHIFTRT
8703 && count == (unsigned int)
8704 (GET_MODE_BITSIZE (result_mode)
8705 - GET_MODE_BITSIZE (GET_MODE (varop))))
8707 /* C3 has the low-order C1 bits zero. */
8709 mask = (GET_MODE_MASK (mode)
8710 & ~(((HOST_WIDE_INT) 1 << first_count) - 1));
8712 varop = simplify_and_const_int (NULL_RTX, result_mode,
8713 XEXP (varop, 0), mask);
8714 varop = simplify_shift_const (NULL_RTX, ASHIFT, result_mode,
8716 count = first_count;
8721 /* If this was (ashiftrt (ashift foo C1) C2) and FOO has more
8722 than C1 high-order bits equal to the sign bit, we can convert
8723 this to either an ASHIFT or an ASHIFTRT depending on the
8726 We cannot do this if VAROP's mode is not SHIFT_MODE. */
8728 if (code == ASHIFTRT && first_code == ASHIFT
8729 && GET_MODE (varop) == shift_mode
8730 && (num_sign_bit_copies (XEXP (varop, 0), shift_mode)
8733 varop = XEXP (varop, 0);
8735 signed_count = count - first_count;
8736 if (signed_count < 0)
8737 count = -signed_count, code = ASHIFT;
8739 count = signed_count;
8744 /* There are some cases we can't do. If CODE is ASHIFTRT,
8745 we can only do this if FIRST_CODE is also ASHIFTRT.
8747 We can't do the case when CODE is ROTATE and FIRST_CODE is
8750 If the mode of this shift is not the mode of the outer shift,
8751 we can't do this if either shift is a right shift or ROTATE.
8753 Finally, we can't do any of these if the mode is too wide
8754 unless the codes are the same.
8756 Handle the case where the shift codes are the same
8759 if (code == first_code)
8761 if (GET_MODE (varop) != result_mode
8762 && (code == ASHIFTRT || code == LSHIFTRT
8766 count += first_count;
8767 varop = XEXP (varop, 0);
8771 if (code == ASHIFTRT
8772 || (code == ROTATE && first_code == ASHIFTRT)
8773 || GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT
8774 || (GET_MODE (varop) != result_mode
8775 && (first_code == ASHIFTRT || first_code == LSHIFTRT
8776 || first_code == ROTATE
8777 || code == ROTATE)))
8780 /* To compute the mask to apply after the shift, shift the
8781 nonzero bits of the inner shift the same way the
8782 outer shift will. */
8784 mask_rtx = GEN_INT (nonzero_bits (varop, GET_MODE (varop)));
8787 = simplify_binary_operation (code, result_mode, mask_rtx,
8790 /* Give up if we can't compute an outer operation to use. */
8792 || GET_CODE (mask_rtx) != CONST_INT
8793 || ! merge_outer_ops (&outer_op, &outer_const, AND,
8795 result_mode, &complement_p))
8798 /* If the shifts are in the same direction, we add the
8799 counts. Otherwise, we subtract them. */
8800 signed_count = count;
8801 if ((code == ASHIFTRT || code == LSHIFTRT)
8802 == (first_code == ASHIFTRT || first_code == LSHIFTRT))
8803 signed_count += first_count;
8805 signed_count -= first_count;
8807 /* If COUNT is positive, the new shift is usually CODE,
8808 except for the two exceptions below, in which case it is
8809 FIRST_CODE. If the count is negative, FIRST_CODE should
8811 if (signed_count > 0
8812 && ((first_code == ROTATE && code == ASHIFT)
8813 || (first_code == ASHIFTRT && code == LSHIFTRT)))
8814 code = first_code, count = signed_count;
8815 else if (signed_count < 0)
8816 code = first_code, count = -signed_count;
8818 count = signed_count;
8820 varop = XEXP (varop, 0);
8824 /* If we have (A << B << C) for any shift, we can convert this to
8825 (A << C << B). This wins if A is a constant. Only try this if
8826 B is not a constant. */
8828 else if (GET_CODE (varop) == code
8829 && GET_CODE (XEXP (varop, 1)) != CONST_INT
8831 = simplify_binary_operation (code, mode,
8835 varop = gen_rtx_fmt_ee (code, mode, new, XEXP (varop, 1));
8842 /* Make this fit the case below. */
8843 varop = gen_rtx_XOR (mode, XEXP (varop, 0),
8844 GEN_INT (GET_MODE_MASK (mode)));
8850 /* If we have (xshiftrt (ior (plus X (const_int -1)) X) C)
8851 with C the size of VAROP - 1 and the shift is logical if
8852 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
8853 we have an (le X 0) operation. If we have an arithmetic shift
8854 and STORE_FLAG_VALUE is 1 or we have a logical shift with
8855 STORE_FLAG_VALUE of -1, we have a (neg (le X 0)) operation. */
8857 if (GET_CODE (varop) == IOR && GET_CODE (XEXP (varop, 0)) == PLUS
8858 && XEXP (XEXP (varop, 0), 1) == constm1_rtx
8859 && (STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
8860 && (code == LSHIFTRT || code == ASHIFTRT)
8861 && count == (unsigned int)
8862 (GET_MODE_BITSIZE (GET_MODE (varop)) - 1)
8863 && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
8866 varop = gen_rtx_LE (GET_MODE (varop), XEXP (varop, 1),
8869 if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
8870 varop = gen_rtx_NEG (GET_MODE (varop), varop);
8875 /* If we have (shift (logical)), move the logical to the outside
8876 to allow it to possibly combine with another logical and the
8877 shift to combine with another shift. This also canonicalizes to
8878 what a ZERO_EXTRACT looks like. Also, some machines have
8879 (and (shift)) insns. */
8881 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
8882 /* We can't do this if we have (ashiftrt (xor)) and the
8883 constant has its sign bit set in shift_mode. */
8884 && !(code == ASHIFTRT && GET_CODE (varop) == XOR
8885 && 0 > trunc_int_for_mode (INTVAL (XEXP (varop, 1)),
8887 && (new = simplify_binary_operation (code, result_mode,
8889 GEN_INT (count))) != 0
8890 && GET_CODE (new) == CONST_INT
8891 && merge_outer_ops (&outer_op, &outer_const, GET_CODE (varop),
8892 INTVAL (new), result_mode, &complement_p))
8894 varop = XEXP (varop, 0);
8898 /* If we can't do that, try to simplify the shift in each arm of the
8899 logical expression, make a new logical expression, and apply
8900 the inverse distributive law. This also can't be done
8901 for some (ashiftrt (xor)). */
8902 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
8903 && !(code == ASHIFTRT && GET_CODE (varop) == XOR
8904 && 0 > trunc_int_for_mode (INTVAL (XEXP (varop, 1)),
8907 rtx lhs = simplify_shift_const (NULL_RTX, code, shift_mode,
8908 XEXP (varop, 0), count);
8909 rtx rhs = simplify_shift_const (NULL_RTX, code, shift_mode,
8910 XEXP (varop, 1), count);
8912 varop = gen_binary (GET_CODE (varop), shift_mode, lhs, rhs);
8913 varop = apply_distributive_law (varop);
8921 /* Convert (lshiftrt (eq FOO 0) C) to (xor FOO 1) if STORE_FLAG_VALUE
8922 says that the sign bit can be tested, FOO has mode MODE, C is
8923 GET_MODE_BITSIZE (MODE) - 1, and FOO has only its low-order bit
8924 that may be nonzero. */
8925 if (code == LSHIFTRT
8926 && XEXP (varop, 1) == const0_rtx
8927 && GET_MODE (XEXP (varop, 0)) == result_mode
8928 && count == (unsigned int) (GET_MODE_BITSIZE (result_mode) - 1)
8929 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
8930 && ((STORE_FLAG_VALUE
8931 & ((HOST_WIDE_INT) 1
8932 < (GET_MODE_BITSIZE (result_mode) - 1))))
8933 && nonzero_bits (XEXP (varop, 0), result_mode) == 1
8934 && merge_outer_ops (&outer_op, &outer_const, XOR,
8935 (HOST_WIDE_INT) 1, result_mode,
8938 varop = XEXP (varop, 0);
8945 /* (lshiftrt (neg A) C) where A is either 0 or 1 and C is one less
8946 than the number of bits in the mode is equivalent to A. */
8947 if (code == LSHIFTRT
8948 && count == (unsigned int) (GET_MODE_BITSIZE (result_mode) - 1)
8949 && nonzero_bits (XEXP (varop, 0), result_mode) == 1)
8951 varop = XEXP (varop, 0);
8956 /* NEG commutes with ASHIFT since it is multiplication. Move the
8957 NEG outside to allow shifts to combine. */
8959 && merge_outer_ops (&outer_op, &outer_const, NEG,
8960 (HOST_WIDE_INT) 0, result_mode,
8963 varop = XEXP (varop, 0);
8969 /* (lshiftrt (plus A -1) C) where A is either 0 or 1 and C
8970 is one less than the number of bits in the mode is
8971 equivalent to (xor A 1). */
8972 if (code == LSHIFTRT
8973 && count == (unsigned int) (GET_MODE_BITSIZE (result_mode) - 1)
8974 && XEXP (varop, 1) == constm1_rtx
8975 && nonzero_bits (XEXP (varop, 0), result_mode) == 1
8976 && merge_outer_ops (&outer_op, &outer_const, XOR,
8977 (HOST_WIDE_INT) 1, result_mode,
8981 varop = XEXP (varop, 0);
8985 /* If we have (xshiftrt (plus FOO BAR) C), and the only bits
8986 that might be nonzero in BAR are those being shifted out and those
8987 bits are known zero in FOO, we can replace the PLUS with FOO.
8988 Similarly in the other operand order. This code occurs when
8989 we are computing the size of a variable-size array. */
8991 if ((code == ASHIFTRT || code == LSHIFTRT)
8992 && count < HOST_BITS_PER_WIDE_INT
8993 && nonzero_bits (XEXP (varop, 1), result_mode) >> count == 0
8994 && (nonzero_bits (XEXP (varop, 1), result_mode)
8995 & nonzero_bits (XEXP (varop, 0), result_mode)) == 0)
8997 varop = XEXP (varop, 0);
9000 else if ((code == ASHIFTRT || code == LSHIFTRT)
9001 && count < HOST_BITS_PER_WIDE_INT
9002 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
9003 && 0 == (nonzero_bits (XEXP (varop, 0), result_mode)
9005 && 0 == (nonzero_bits (XEXP (varop, 0), result_mode)
9006 & nonzero_bits (XEXP (varop, 1),
9009 varop = XEXP (varop, 1);
9013 /* (ashift (plus foo C) N) is (plus (ashift foo N) C'). */
9015 && GET_CODE (XEXP (varop, 1)) == CONST_INT
9016 && (new = simplify_binary_operation (ASHIFT, result_mode,
9018 GEN_INT (count))) != 0
9019 && GET_CODE (new) == CONST_INT
9020 && merge_outer_ops (&outer_op, &outer_const, PLUS,
9021 INTVAL (new), result_mode, &complement_p))
9023 varop = XEXP (varop, 0);
9029 /* If we have (xshiftrt (minus (ashiftrt X C)) X) C)
9030 with C the size of VAROP - 1 and the shift is logical if
9031 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
9032 we have a (gt X 0) operation. If the shift is arithmetic with
9033 STORE_FLAG_VALUE of 1 or logical with STORE_FLAG_VALUE == -1,
9034 we have a (neg (gt X 0)) operation. */
9036 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
9037 && GET_CODE (XEXP (varop, 0)) == ASHIFTRT
9038 && count == (unsigned int)
9039 (GET_MODE_BITSIZE (GET_MODE (varop)) - 1)
9040 && (code == LSHIFTRT || code == ASHIFTRT)
9041 && GET_CODE (XEXP (XEXP (varop, 0), 1)) == CONST_INT
9042 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (XEXP (varop, 0), 1))
9044 && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
9047 varop = gen_rtx_GT (GET_MODE (varop), XEXP (varop, 1),
9050 if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
9051 varop = gen_rtx_NEG (GET_MODE (varop), varop);
9058 /* Change (lshiftrt (truncate (lshiftrt))) to (truncate (lshiftrt))
9059 if the truncate does not affect the value. */
9060 if (code == LSHIFTRT
9061 && GET_CODE (XEXP (varop, 0)) == LSHIFTRT
9062 && GET_CODE (XEXP (XEXP (varop, 0), 1)) == CONST_INT
9063 && (INTVAL (XEXP (XEXP (varop, 0), 1))
9064 >= (GET_MODE_BITSIZE (GET_MODE (XEXP (varop, 0)))
9065 - GET_MODE_BITSIZE (GET_MODE (varop)))))
9067 rtx varop_inner = XEXP (varop, 0);
9070 = gen_rtx_LSHIFTRT (GET_MODE (varop_inner),
9071 XEXP (varop_inner, 0),
9073 (count + INTVAL (XEXP (varop_inner, 1))));
9074 varop = gen_rtx_TRUNCATE (GET_MODE (varop), varop_inner);
9087 /* We need to determine what mode to do the shift in. If the shift is
9088 a right shift or ROTATE, we must always do it in the mode it was
9089 originally done in. Otherwise, we can do it in MODE, the widest mode
9090 encountered. The code we care about is that of the shift that will
9091 actually be done, not the shift that was originally requested. */
9093 = (code == ASHIFTRT || code == LSHIFTRT || code == ROTATE
9094 ? result_mode : mode);
9096 /* We have now finished analyzing the shift. The result should be
9097 a shift of type CODE with SHIFT_MODE shifting VAROP COUNT places. If
9098 OUTER_OP is non-UNKNOWN, it is an operation that needs to be applied
9099 to the result of the shift. OUTER_CONST is the relevant constant,
9100 but we must turn off all bits turned off in the shift.
9102 If we were passed a value for X, see if we can use any pieces of
9103 it. If not, make new rtx. */
9105 if (x && GET_RTX_CLASS (GET_CODE (x)) == RTX_BIN_ARITH
9106 && GET_CODE (XEXP (x, 1)) == CONST_INT
9107 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (x, 1)) == count)
9108 const_rtx = XEXP (x, 1);
9110 const_rtx = GEN_INT (count);
9112 if (x && GET_CODE (XEXP (x, 0)) == SUBREG
9113 && GET_MODE (XEXP (x, 0)) == shift_mode
9114 && SUBREG_REG (XEXP (x, 0)) == varop)
9115 varop = XEXP (x, 0);
9116 else if (GET_MODE (varop) != shift_mode)
9117 varop = gen_lowpart (shift_mode, varop);
9119 /* If we can't make the SUBREG, try to return what we were given. */
9120 if (GET_CODE (varop) == CLOBBER)
9121 return x ? x : varop;
9123 new = simplify_binary_operation (code, shift_mode, varop, const_rtx);
9127 x = gen_rtx_fmt_ee (code, shift_mode, varop, const_rtx);
9129 /* If we have an outer operation and we just made a shift, it is
9130 possible that we could have simplified the shift were it not
9131 for the outer operation. So try to do the simplification
9134 if (outer_op != UNKNOWN && GET_CODE (x) == code
9135 && GET_CODE (XEXP (x, 1)) == CONST_INT)
9136 x = simplify_shift_const (x, code, shift_mode, XEXP (x, 0),
9137 INTVAL (XEXP (x, 1)));
9139 /* If we were doing an LSHIFTRT in a wider mode than it was originally,
9140 turn off all the bits that the shift would have turned off. */
9141 if (orig_code == LSHIFTRT && result_mode != shift_mode)
9142 x = simplify_and_const_int (NULL_RTX, shift_mode, x,
9143 GET_MODE_MASK (result_mode) >> orig_count);
9145 /* Do the remainder of the processing in RESULT_MODE. */
9146 x = gen_lowpart (result_mode, x);
9148 /* If COMPLEMENT_P is set, we have to complement X before doing the outer
9151 x = simplify_gen_unary (NOT, result_mode, x, result_mode);
9153 if (outer_op != UNKNOWN)
9155 if (GET_MODE_BITSIZE (result_mode) < HOST_BITS_PER_WIDE_INT)
9156 outer_const = trunc_int_for_mode (outer_const, result_mode);
9158 if (outer_op == AND)
9159 x = simplify_and_const_int (NULL_RTX, result_mode, x, outer_const);
9160 else if (outer_op == SET)
9161 /* This means that we have determined that the result is
9162 equivalent to a constant. This should be rare. */
9163 x = GEN_INT (outer_const);
9164 else if (GET_RTX_CLASS (outer_op) == RTX_UNARY)
9165 x = simplify_gen_unary (outer_op, result_mode, x, result_mode);
9167 x = gen_binary (outer_op, result_mode, x, GEN_INT (outer_const));
9173 /* Like recog, but we receive the address of a pointer to a new pattern.
9174 We try to match the rtx that the pointer points to.
9175 If that fails, we may try to modify or replace the pattern,
9176 storing the replacement into the same pointer object.
9178 Modifications include deletion or addition of CLOBBERs.
9180 PNOTES is a pointer to a location where any REG_UNUSED notes added for
9181 the CLOBBERs are placed.
9183 The value is the final insn code from the pattern ultimately matched,
9187 recog_for_combine (rtx *pnewpat, rtx insn, rtx *pnotes)
9190 int insn_code_number;
9191 int num_clobbers_to_add = 0;
9194 rtx old_notes, old_pat;
9196 /* If PAT is a PARALLEL, check to see if it contains the CLOBBER
9197 we use to indicate that something didn't match. If we find such a
9198 thing, force rejection. */
9199 if (GET_CODE (pat) == PARALLEL)
9200 for (i = XVECLEN (pat, 0) - 1; i >= 0; i--)
9201 if (GET_CODE (XVECEXP (pat, 0, i)) == CLOBBER
9202 && XEXP (XVECEXP (pat, 0, i), 0) == const0_rtx)
9205 old_pat = PATTERN (insn);
9206 old_notes = REG_NOTES (insn);
9207 PATTERN (insn) = pat;
9208 REG_NOTES (insn) = 0;
9210 insn_code_number = recog (pat, insn, &num_clobbers_to_add);
9212 /* If it isn't, there is the possibility that we previously had an insn
9213 that clobbered some register as a side effect, but the combined
9214 insn doesn't need to do that. So try once more without the clobbers
9215 unless this represents an ASM insn. */
9217 if (insn_code_number < 0 && ! check_asm_operands (pat)
9218 && GET_CODE (pat) == PARALLEL)
9222 for (pos = 0, i = 0; i < XVECLEN (pat, 0); i++)
9223 if (GET_CODE (XVECEXP (pat, 0, i)) != CLOBBER)
9226 SUBST (XVECEXP (pat, 0, pos), XVECEXP (pat, 0, i));
9230 SUBST_INT (XVECLEN (pat, 0), pos);
9233 pat = XVECEXP (pat, 0, 0);
9235 PATTERN (insn) = pat;
9236 insn_code_number = recog (pat, insn, &num_clobbers_to_add);
9238 PATTERN (insn) = old_pat;
9239 REG_NOTES (insn) = old_notes;
9241 /* Recognize all noop sets, these will be killed by followup pass. */
9242 if (insn_code_number < 0 && GET_CODE (pat) == SET && set_noop_p (pat))
9243 insn_code_number = NOOP_MOVE_INSN_CODE, num_clobbers_to_add = 0;
9245 /* If we had any clobbers to add, make a new pattern than contains
9246 them. Then check to make sure that all of them are dead. */
9247 if (num_clobbers_to_add)
9249 rtx newpat = gen_rtx_PARALLEL (VOIDmode,
9250 rtvec_alloc (GET_CODE (pat) == PARALLEL
9252 + num_clobbers_to_add)
9253 : num_clobbers_to_add + 1));
9255 if (GET_CODE (pat) == PARALLEL)
9256 for (i = 0; i < XVECLEN (pat, 0); i++)
9257 XVECEXP (newpat, 0, i) = XVECEXP (pat, 0, i);
9259 XVECEXP (newpat, 0, 0) = pat;
9261 add_clobbers (newpat, insn_code_number);
9263 for (i = XVECLEN (newpat, 0) - num_clobbers_to_add;
9264 i < XVECLEN (newpat, 0); i++)
9266 if (REG_P (XEXP (XVECEXP (newpat, 0, i), 0))
9267 && ! reg_dead_at_p (XEXP (XVECEXP (newpat, 0, i), 0), insn))
9269 notes = gen_rtx_EXPR_LIST (REG_UNUSED,
9270 XEXP (XVECEXP (newpat, 0, i), 0), notes);
9278 return insn_code_number;
9281 /* Like gen_lowpart_general but for use by combine. In combine it
9282 is not possible to create any new pseudoregs. However, it is
9283 safe to create invalid memory addresses, because combine will
9284 try to recognize them and all they will do is make the combine
9287 If for some reason this cannot do its job, an rtx
9288 (clobber (const_int 0)) is returned.
9289 An insn containing that will not be recognized. */
9292 gen_lowpart_for_combine (enum machine_mode mode, rtx x)
9296 if (GET_MODE (x) == mode)
9299 /* Return identity if this is a CONST or symbolic
9302 && (GET_CODE (x) == CONST
9303 || GET_CODE (x) == SYMBOL_REF
9304 || GET_CODE (x) == LABEL_REF))
9307 /* We can only support MODE being wider than a word if X is a
9308 constant integer or has a mode the same size. */
9310 if (GET_MODE_SIZE (mode) > UNITS_PER_WORD
9311 && ! ((GET_MODE (x) == VOIDmode
9312 && (GET_CODE (x) == CONST_INT
9313 || GET_CODE (x) == CONST_DOUBLE))
9314 || GET_MODE_SIZE (GET_MODE (x)) == GET_MODE_SIZE (mode)))
9315 return gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
9317 /* X might be a paradoxical (subreg (mem)). In that case, gen_lowpart
9318 won't know what to do. So we will strip off the SUBREG here and
9319 process normally. */
9320 if (GET_CODE (x) == SUBREG && MEM_P (SUBREG_REG (x)))
9323 if (GET_MODE (x) == mode)
9327 result = gen_lowpart_common (mode, x);
9328 #ifdef CANNOT_CHANGE_MODE_CLASS
9330 && GET_CODE (result) == SUBREG
9331 && REG_P (SUBREG_REG (result))
9332 && REGNO (SUBREG_REG (result)) >= FIRST_PSEUDO_REGISTER)
9333 bitmap_set_bit (&subregs_of_mode, REGNO (SUBREG_REG (result))
9335 + GET_MODE (result));
9345 /* Refuse to work on a volatile memory ref or one with a mode-dependent
9347 if (MEM_VOLATILE_P (x) || mode_dependent_address_p (XEXP (x, 0)))
9348 return gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
9350 /* If we want to refer to something bigger than the original memref,
9351 generate a paradoxical subreg instead. That will force a reload
9352 of the original memref X. */
9353 if (GET_MODE_SIZE (GET_MODE (x)) < GET_MODE_SIZE (mode))
9354 return gen_rtx_SUBREG (mode, x, 0);
9356 if (WORDS_BIG_ENDIAN)
9357 offset = (MAX (GET_MODE_SIZE (GET_MODE (x)), UNITS_PER_WORD)
9358 - MAX (GET_MODE_SIZE (mode), UNITS_PER_WORD));
9360 if (BYTES_BIG_ENDIAN)
9362 /* Adjust the address so that the address-after-the-data is
9364 offset -= (MIN (UNITS_PER_WORD, GET_MODE_SIZE (mode))
9365 - MIN (UNITS_PER_WORD, GET_MODE_SIZE (GET_MODE (x))));
9368 return adjust_address_nv (x, mode, offset);
9371 /* If X is a comparison operator, rewrite it in a new mode. This
9372 probably won't match, but may allow further simplifications. */
9373 else if (COMPARISON_P (x))
9374 return gen_rtx_fmt_ee (GET_CODE (x), mode, XEXP (x, 0), XEXP (x, 1));
9376 /* If we couldn't simplify X any other way, just enclose it in a
9377 SUBREG. Normally, this SUBREG won't match, but some patterns may
9378 include an explicit SUBREG or we may simplify it further in combine. */
9383 enum machine_mode sub_mode = GET_MODE (x);
9385 offset = subreg_lowpart_offset (mode, sub_mode);
9386 if (sub_mode == VOIDmode)
9388 sub_mode = int_mode_for_mode (mode);
9389 x = gen_lowpart_common (sub_mode, x);
9391 return gen_rtx_CLOBBER (VOIDmode, const0_rtx);
9393 res = simplify_gen_subreg (mode, x, sub_mode, offset);
9396 return gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
9400 /* These routines make binary and unary operations by first seeing if they
9401 fold; if not, a new expression is allocated. */
9404 gen_binary (enum rtx_code code, enum machine_mode mode, rtx op0, rtx op1)
9409 if (GET_CODE (op0) == CLOBBER)
9411 else if (GET_CODE (op1) == CLOBBER)
9414 if (GET_RTX_CLASS (code) == RTX_COMM_ARITH
9415 && swap_commutative_operands_p (op0, op1))
9416 tem = op0, op0 = op1, op1 = tem;
9418 if (GET_RTX_CLASS (code) == RTX_COMPARE
9419 || GET_RTX_CLASS (code) == RTX_COMM_COMPARE)
9421 enum machine_mode op_mode = GET_MODE (op0);
9423 /* Strip the COMPARE from (REL_OP (compare X Y) 0) to get
9424 just (REL_OP X Y). */
9425 if (GET_CODE (op0) == COMPARE && op1 == const0_rtx)
9427 op1 = XEXP (op0, 1);
9428 op0 = XEXP (op0, 0);
9429 op_mode = GET_MODE (op0);
9432 if (op_mode == VOIDmode)
9433 op_mode = GET_MODE (op1);
9434 result = simplify_relational_operation (code, mode, op_mode, op0, op1);
9437 result = simplify_binary_operation (code, mode, op0, op1);
9442 /* Put complex operands first and constants second. */
9443 if (GET_RTX_CLASS (code) == RTX_COMM_ARITH
9444 && swap_commutative_operands_p (op0, op1))
9445 return gen_rtx_fmt_ee (code, mode, op1, op0);
9447 /* If we are turning off bits already known off in OP0, we need not do
9449 else if (code == AND && GET_CODE (op1) == CONST_INT
9450 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
9451 && (nonzero_bits (op0, mode) & ~INTVAL (op1)) == 0)
9454 return gen_rtx_fmt_ee (code, mode, op0, op1);
9457 /* Simplify a comparison between *POP0 and *POP1 where CODE is the
9458 comparison code that will be tested.
9460 The result is a possibly different comparison code to use. *POP0 and
9461 *POP1 may be updated.
9463 It is possible that we might detect that a comparison is either always
9464 true or always false. However, we do not perform general constant
9465 folding in combine, so this knowledge isn't useful. Such tautologies
9466 should have been detected earlier. Hence we ignore all such cases. */
9468 static enum rtx_code
9469 simplify_comparison (enum rtx_code code, rtx *pop0, rtx *pop1)
9475 enum machine_mode mode, tmode;
9477 /* Try a few ways of applying the same transformation to both operands. */
9480 #ifndef WORD_REGISTER_OPERATIONS
9481 /* The test below this one won't handle SIGN_EXTENDs on these machines,
9482 so check specially. */
9483 if (code != GTU && code != GEU && code != LTU && code != LEU
9484 && GET_CODE (op0) == ASHIFTRT && GET_CODE (op1) == ASHIFTRT
9485 && GET_CODE (XEXP (op0, 0)) == ASHIFT
9486 && GET_CODE (XEXP (op1, 0)) == ASHIFT
9487 && GET_CODE (XEXP (XEXP (op0, 0), 0)) == SUBREG
9488 && GET_CODE (XEXP (XEXP (op1, 0), 0)) == SUBREG
9489 && (GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0)))
9490 == GET_MODE (SUBREG_REG (XEXP (XEXP (op1, 0), 0))))
9491 && GET_CODE (XEXP (op0, 1)) == CONST_INT
9492 && XEXP (op0, 1) == XEXP (op1, 1)
9493 && XEXP (op0, 1) == XEXP (XEXP (op0, 0), 1)
9494 && XEXP (op0, 1) == XEXP (XEXP (op1, 0), 1)
9495 && (INTVAL (XEXP (op0, 1))
9496 == (GET_MODE_BITSIZE (GET_MODE (op0))
9498 (GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0))))))))
9500 op0 = SUBREG_REG (XEXP (XEXP (op0, 0), 0));
9501 op1 = SUBREG_REG (XEXP (XEXP (op1, 0), 0));
9505 /* If both operands are the same constant shift, see if we can ignore the
9506 shift. We can if the shift is a rotate or if the bits shifted out of
9507 this shift are known to be zero for both inputs and if the type of
9508 comparison is compatible with the shift. */
9509 if (GET_CODE (op0) == GET_CODE (op1)
9510 && GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
9511 && ((GET_CODE (op0) == ROTATE && (code == NE || code == EQ))
9512 || ((GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFT)
9513 && (code != GT && code != LT && code != GE && code != LE))
9514 || (GET_CODE (op0) == ASHIFTRT
9515 && (code != GTU && code != LTU
9516 && code != GEU && code != LEU)))
9517 && GET_CODE (XEXP (op0, 1)) == CONST_INT
9518 && INTVAL (XEXP (op0, 1)) >= 0
9519 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT
9520 && XEXP (op0, 1) == XEXP (op1, 1))
9522 enum machine_mode mode = GET_MODE (op0);
9523 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
9524 int shift_count = INTVAL (XEXP (op0, 1));
9526 if (GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFTRT)
9527 mask &= (mask >> shift_count) << shift_count;
9528 else if (GET_CODE (op0) == ASHIFT)
9529 mask = (mask & (mask << shift_count)) >> shift_count;
9531 if ((nonzero_bits (XEXP (op0, 0), mode) & ~mask) == 0
9532 && (nonzero_bits (XEXP (op1, 0), mode) & ~mask) == 0)
9533 op0 = XEXP (op0, 0), op1 = XEXP (op1, 0);
9538 /* If both operands are AND's of a paradoxical SUBREG by constant, the
9539 SUBREGs are of the same mode, and, in both cases, the AND would
9540 be redundant if the comparison was done in the narrower mode,
9541 do the comparison in the narrower mode (e.g., we are AND'ing with 1
9542 and the operand's possibly nonzero bits are 0xffffff01; in that case
9543 if we only care about QImode, we don't need the AND). This case
9544 occurs if the output mode of an scc insn is not SImode and
9545 STORE_FLAG_VALUE == 1 (e.g., the 386).
9547 Similarly, check for a case where the AND's are ZERO_EXTEND
9548 operations from some narrower mode even though a SUBREG is not
9551 else if (GET_CODE (op0) == AND && GET_CODE (op1) == AND
9552 && GET_CODE (XEXP (op0, 1)) == CONST_INT
9553 && GET_CODE (XEXP (op1, 1)) == CONST_INT)
9555 rtx inner_op0 = XEXP (op0, 0);
9556 rtx inner_op1 = XEXP (op1, 0);
9557 HOST_WIDE_INT c0 = INTVAL (XEXP (op0, 1));
9558 HOST_WIDE_INT c1 = INTVAL (XEXP (op1, 1));
9561 if (GET_CODE (inner_op0) == SUBREG && GET_CODE (inner_op1) == SUBREG
9562 && (GET_MODE_SIZE (GET_MODE (inner_op0))
9563 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (inner_op0))))
9564 && (GET_MODE (SUBREG_REG (inner_op0))
9565 == GET_MODE (SUBREG_REG (inner_op1)))
9566 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (inner_op0)))
9567 <= HOST_BITS_PER_WIDE_INT)
9568 && (0 == ((~c0) & nonzero_bits (SUBREG_REG (inner_op0),
9569 GET_MODE (SUBREG_REG (inner_op0)))))
9570 && (0 == ((~c1) & nonzero_bits (SUBREG_REG (inner_op1),
9571 GET_MODE (SUBREG_REG (inner_op1))))))
9573 op0 = SUBREG_REG (inner_op0);
9574 op1 = SUBREG_REG (inner_op1);
9576 /* The resulting comparison is always unsigned since we masked
9577 off the original sign bit. */
9578 code = unsigned_condition (code);
9584 for (tmode = GET_CLASS_NARROWEST_MODE
9585 (GET_MODE_CLASS (GET_MODE (op0)));
9586 tmode != GET_MODE (op0); tmode = GET_MODE_WIDER_MODE (tmode))
9587 if ((unsigned HOST_WIDE_INT) c0 == GET_MODE_MASK (tmode))
9589 op0 = gen_lowpart (tmode, inner_op0);
9590 op1 = gen_lowpart (tmode, inner_op1);
9591 code = unsigned_condition (code);
9600 /* If both operands are NOT, we can strip off the outer operation
9601 and adjust the comparison code for swapped operands; similarly for
9602 NEG, except that this must be an equality comparison. */
9603 else if ((GET_CODE (op0) == NOT && GET_CODE (op1) == NOT)
9604 || (GET_CODE (op0) == NEG && GET_CODE (op1) == NEG
9605 && (code == EQ || code == NE)))
9606 op0 = XEXP (op0, 0), op1 = XEXP (op1, 0), code = swap_condition (code);
9612 /* If the first operand is a constant, swap the operands and adjust the
9613 comparison code appropriately, but don't do this if the second operand
9614 is already a constant integer. */
9615 if (swap_commutative_operands_p (op0, op1))
9617 tem = op0, op0 = op1, op1 = tem;
9618 code = swap_condition (code);
9621 /* We now enter a loop during which we will try to simplify the comparison.
9622 For the most part, we only are concerned with comparisons with zero,
9623 but some things may really be comparisons with zero but not start
9624 out looking that way. */
9626 while (GET_CODE (op1) == CONST_INT)
9628 enum machine_mode mode = GET_MODE (op0);
9629 unsigned int mode_width = GET_MODE_BITSIZE (mode);
9630 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
9631 int equality_comparison_p;
9632 int sign_bit_comparison_p;
9633 int unsigned_comparison_p;
9634 HOST_WIDE_INT const_op;
9636 /* We only want to handle integral modes. This catches VOIDmode,
9637 CCmode, and the floating-point modes. An exception is that we
9638 can handle VOIDmode if OP0 is a COMPARE or a comparison
9641 if (GET_MODE_CLASS (mode) != MODE_INT
9642 && ! (mode == VOIDmode
9643 && (GET_CODE (op0) == COMPARE || COMPARISON_P (op0))))
9646 /* Get the constant we are comparing against and turn off all bits
9647 not on in our mode. */
9648 const_op = INTVAL (op1);
9649 if (mode != VOIDmode)
9650 const_op = trunc_int_for_mode (const_op, mode);
9651 op1 = GEN_INT (const_op);
9653 /* If we are comparing against a constant power of two and the value
9654 being compared can only have that single bit nonzero (e.g., it was
9655 `and'ed with that bit), we can replace this with a comparison
9658 && (code == EQ || code == NE || code == GE || code == GEU
9659 || code == LT || code == LTU)
9660 && mode_width <= HOST_BITS_PER_WIDE_INT
9661 && exact_log2 (const_op) >= 0
9662 && nonzero_bits (op0, mode) == (unsigned HOST_WIDE_INT) const_op)
9664 code = (code == EQ || code == GE || code == GEU ? NE : EQ);
9665 op1 = const0_rtx, const_op = 0;
9668 /* Similarly, if we are comparing a value known to be either -1 or
9669 0 with -1, change it to the opposite comparison against zero. */
9672 && (code == EQ || code == NE || code == GT || code == LE
9673 || code == GEU || code == LTU)
9674 && num_sign_bit_copies (op0, mode) == mode_width)
9676 code = (code == EQ || code == LE || code == GEU ? NE : EQ);
9677 op1 = const0_rtx, const_op = 0;
9680 /* Do some canonicalizations based on the comparison code. We prefer
9681 comparisons against zero and then prefer equality comparisons.
9682 If we can reduce the size of a constant, we will do that too. */
9687 /* < C is equivalent to <= (C - 1) */
9691 op1 = GEN_INT (const_op);
9693 /* ... fall through to LE case below. */
9699 /* <= C is equivalent to < (C + 1); we do this for C < 0 */
9703 op1 = GEN_INT (const_op);
9707 /* If we are doing a <= 0 comparison on a value known to have
9708 a zero sign bit, we can replace this with == 0. */
9709 else if (const_op == 0
9710 && mode_width <= HOST_BITS_PER_WIDE_INT
9711 && (nonzero_bits (op0, mode)
9712 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)
9717 /* >= C is equivalent to > (C - 1). */
9721 op1 = GEN_INT (const_op);
9723 /* ... fall through to GT below. */
9729 /* > C is equivalent to >= (C + 1); we do this for C < 0. */
9733 op1 = GEN_INT (const_op);
9737 /* If we are doing a > 0 comparison on a value known to have
9738 a zero sign bit, we can replace this with != 0. */
9739 else if (const_op == 0
9740 && mode_width <= HOST_BITS_PER_WIDE_INT
9741 && (nonzero_bits (op0, mode)
9742 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)
9747 /* < C is equivalent to <= (C - 1). */
9751 op1 = GEN_INT (const_op);
9753 /* ... fall through ... */
9756 /* (unsigned) < 0x80000000 is equivalent to >= 0. */
9757 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
9758 && (const_op == (HOST_WIDE_INT) 1 << (mode_width - 1)))
9760 const_op = 0, op1 = const0_rtx;
9768 /* unsigned <= 0 is equivalent to == 0 */
9772 /* (unsigned) <= 0x7fffffff is equivalent to >= 0. */
9773 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
9774 && (const_op == ((HOST_WIDE_INT) 1 << (mode_width - 1)) - 1))
9776 const_op = 0, op1 = const0_rtx;
9782 /* >= C is equivalent to > (C - 1). */
9786 op1 = GEN_INT (const_op);
9788 /* ... fall through ... */
9791 /* (unsigned) >= 0x80000000 is equivalent to < 0. */
9792 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
9793 && (const_op == (HOST_WIDE_INT) 1 << (mode_width - 1)))
9795 const_op = 0, op1 = const0_rtx;
9803 /* unsigned > 0 is equivalent to != 0 */
9807 /* (unsigned) > 0x7fffffff is equivalent to < 0. */
9808 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
9809 && (const_op == ((HOST_WIDE_INT) 1 << (mode_width - 1)) - 1))
9811 const_op = 0, op1 = const0_rtx;
9820 /* Compute some predicates to simplify code below. */
9822 equality_comparison_p = (code == EQ || code == NE);
9823 sign_bit_comparison_p = ((code == LT || code == GE) && const_op == 0);
9824 unsigned_comparison_p = (code == LTU || code == LEU || code == GTU
9827 /* If this is a sign bit comparison and we can do arithmetic in
9828 MODE, say that we will only be needing the sign bit of OP0. */
9829 if (sign_bit_comparison_p
9830 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
9831 op0 = force_to_mode (op0, mode,
9833 << (GET_MODE_BITSIZE (mode) - 1)),
9836 /* Now try cases based on the opcode of OP0. If none of the cases
9837 does a "continue", we exit this loop immediately after the
9840 switch (GET_CODE (op0))
9843 /* If we are extracting a single bit from a variable position in
9844 a constant that has only a single bit set and are comparing it
9845 with zero, we can convert this into an equality comparison
9846 between the position and the location of the single bit. */
9847 /* Except we can't if SHIFT_COUNT_TRUNCATED is set, since we might
9848 have already reduced the shift count modulo the word size. */
9849 if (!SHIFT_COUNT_TRUNCATED
9850 && GET_CODE (XEXP (op0, 0)) == CONST_INT
9851 && XEXP (op0, 1) == const1_rtx
9852 && equality_comparison_p && const_op == 0
9853 && (i = exact_log2 (INTVAL (XEXP (op0, 0)))) >= 0)
9855 if (BITS_BIG_ENDIAN)
9857 enum machine_mode new_mode
9858 = mode_for_extraction (EP_extzv, 1);
9859 if (new_mode == MAX_MACHINE_MODE)
9860 i = BITS_PER_WORD - 1 - i;
9864 i = (GET_MODE_BITSIZE (mode) - 1 - i);
9868 op0 = XEXP (op0, 2);
9872 /* Result is nonzero iff shift count is equal to I. */
9873 code = reverse_condition (code);
9877 /* ... fall through ... */
9880 tem = expand_compound_operation (op0);
9889 /* If testing for equality, we can take the NOT of the constant. */
9890 if (equality_comparison_p
9891 && (tem = simplify_unary_operation (NOT, mode, op1, mode)) != 0)
9893 op0 = XEXP (op0, 0);
9898 /* If just looking at the sign bit, reverse the sense of the
9900 if (sign_bit_comparison_p)
9902 op0 = XEXP (op0, 0);
9903 code = (code == GE ? LT : GE);
9909 /* If testing for equality, we can take the NEG of the constant. */
9910 if (equality_comparison_p
9911 && (tem = simplify_unary_operation (NEG, mode, op1, mode)) != 0)
9913 op0 = XEXP (op0, 0);
9918 /* The remaining cases only apply to comparisons with zero. */
9922 /* When X is ABS or is known positive,
9923 (neg X) is < 0 if and only if X != 0. */
9925 if (sign_bit_comparison_p
9926 && (GET_CODE (XEXP (op0, 0)) == ABS
9927 || (mode_width <= HOST_BITS_PER_WIDE_INT
9928 && (nonzero_bits (XEXP (op0, 0), mode)
9929 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)))
9931 op0 = XEXP (op0, 0);
9932 code = (code == LT ? NE : EQ);
9936 /* If we have NEG of something whose two high-order bits are the
9937 same, we know that "(-a) < 0" is equivalent to "a > 0". */
9938 if (num_sign_bit_copies (op0, mode) >= 2)
9940 op0 = XEXP (op0, 0);
9941 code = swap_condition (code);
9947 /* If we are testing equality and our count is a constant, we
9948 can perform the inverse operation on our RHS. */
9949 if (equality_comparison_p && GET_CODE (XEXP (op0, 1)) == CONST_INT
9950 && (tem = simplify_binary_operation (ROTATERT, mode,
9951 op1, XEXP (op0, 1))) != 0)
9953 op0 = XEXP (op0, 0);
9958 /* If we are doing a < 0 or >= 0 comparison, it means we are testing
9959 a particular bit. Convert it to an AND of a constant of that
9960 bit. This will be converted into a ZERO_EXTRACT. */
9961 if (const_op == 0 && sign_bit_comparison_p
9962 && GET_CODE (XEXP (op0, 1)) == CONST_INT
9963 && mode_width <= HOST_BITS_PER_WIDE_INT)
9965 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
9968 - INTVAL (XEXP (op0, 1)))));
9969 code = (code == LT ? NE : EQ);
9976 /* ABS is ignorable inside an equality comparison with zero. */
9977 if (const_op == 0 && equality_comparison_p)
9979 op0 = XEXP (op0, 0);
9985 /* Can simplify (compare (zero/sign_extend FOO) CONST)
9986 to (compare FOO CONST) if CONST fits in FOO's mode and we
9987 are either testing inequality or have an unsigned comparison
9988 with ZERO_EXTEND or a signed comparison with SIGN_EXTEND. */
9989 if (! unsigned_comparison_p
9990 && (GET_MODE_BITSIZE (GET_MODE (XEXP (op0, 0)))
9991 <= HOST_BITS_PER_WIDE_INT)
9992 && ((unsigned HOST_WIDE_INT) const_op
9993 < (((unsigned HOST_WIDE_INT) 1
9994 << (GET_MODE_BITSIZE (GET_MODE (XEXP (op0, 0))) - 1)))))
9996 op0 = XEXP (op0, 0);
10002 /* Check for the case where we are comparing A - C1 with C2,
10003 both constants are smaller than 1/2 the maximum positive
10004 value in MODE, and the comparison is equality or unsigned.
10005 In that case, if A is either zero-extended to MODE or has
10006 sufficient sign bits so that the high-order bit in MODE
10007 is a copy of the sign in the inner mode, we can prove that it is
10008 safe to do the operation in the wider mode. This simplifies
10009 many range checks. */
10011 if (mode_width <= HOST_BITS_PER_WIDE_INT
10012 && subreg_lowpart_p (op0)
10013 && GET_CODE (SUBREG_REG (op0)) == PLUS
10014 && GET_CODE (XEXP (SUBREG_REG (op0), 1)) == CONST_INT
10015 && INTVAL (XEXP (SUBREG_REG (op0), 1)) < 0
10016 && (-INTVAL (XEXP (SUBREG_REG (op0), 1))
10017 < (HOST_WIDE_INT) (GET_MODE_MASK (mode) / 2))
10018 && (unsigned HOST_WIDE_INT) const_op < GET_MODE_MASK (mode) / 2
10019 && (0 == (nonzero_bits (XEXP (SUBREG_REG (op0), 0),
10020 GET_MODE (SUBREG_REG (op0)))
10021 & ~GET_MODE_MASK (mode))
10022 || (num_sign_bit_copies (XEXP (SUBREG_REG (op0), 0),
10023 GET_MODE (SUBREG_REG (op0)))
10025 (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0)))
10026 - GET_MODE_BITSIZE (mode)))))
10028 op0 = SUBREG_REG (op0);
10032 /* If the inner mode is narrower and we are extracting the low part,
10033 we can treat the SUBREG as if it were a ZERO_EXTEND. */
10034 if (subreg_lowpart_p (op0)
10035 && GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0))) < mode_width)
10036 /* Fall through */ ;
10040 /* ... fall through ... */
10043 if ((unsigned_comparison_p || equality_comparison_p)
10044 && (GET_MODE_BITSIZE (GET_MODE (XEXP (op0, 0)))
10045 <= HOST_BITS_PER_WIDE_INT)
10046 && ((unsigned HOST_WIDE_INT) const_op
10047 < GET_MODE_MASK (GET_MODE (XEXP (op0, 0)))))
10049 op0 = XEXP (op0, 0);
10055 /* (eq (plus X A) B) -> (eq X (minus B A)). We can only do
10056 this for equality comparisons due to pathological cases involving
10058 if (equality_comparison_p
10059 && 0 != (tem = simplify_binary_operation (MINUS, mode,
10060 op1, XEXP (op0, 1))))
10062 op0 = XEXP (op0, 0);
10067 /* (plus (abs X) (const_int -1)) is < 0 if and only if X == 0. */
10068 if (const_op == 0 && XEXP (op0, 1) == constm1_rtx
10069 && GET_CODE (XEXP (op0, 0)) == ABS && sign_bit_comparison_p)
10071 op0 = XEXP (XEXP (op0, 0), 0);
10072 code = (code == LT ? EQ : NE);
10078 /* We used to optimize signed comparisons against zero, but that
10079 was incorrect. Unsigned comparisons against zero (GTU, LEU)
10080 arrive here as equality comparisons, or (GEU, LTU) are
10081 optimized away. No need to special-case them. */
10083 /* (eq (minus A B) C) -> (eq A (plus B C)) or
10084 (eq B (minus A C)), whichever simplifies. We can only do
10085 this for equality comparisons due to pathological cases involving
10087 if (equality_comparison_p
10088 && 0 != (tem = simplify_binary_operation (PLUS, mode,
10089 XEXP (op0, 1), op1)))
10091 op0 = XEXP (op0, 0);
10096 if (equality_comparison_p
10097 && 0 != (tem = simplify_binary_operation (MINUS, mode,
10098 XEXP (op0, 0), op1)))
10100 op0 = XEXP (op0, 1);
10105 /* The sign bit of (minus (ashiftrt X C) X), where C is the number
10106 of bits in X minus 1, is one iff X > 0. */
10107 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == ASHIFTRT
10108 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
10109 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (XEXP (op0, 0), 1))
10111 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
10113 op0 = XEXP (op0, 1);
10114 code = (code == GE ? LE : GT);
10120 /* (eq (xor A B) C) -> (eq A (xor B C)). This is a simplification
10121 if C is zero or B is a constant. */
10122 if (equality_comparison_p
10123 && 0 != (tem = simplify_binary_operation (XOR, mode,
10124 XEXP (op0, 1), op1)))
10126 op0 = XEXP (op0, 0);
10133 case UNEQ: case LTGT:
10134 case LT: case LTU: case UNLT: case LE: case LEU: case UNLE:
10135 case GT: case GTU: case UNGT: case GE: case GEU: case UNGE:
10136 case UNORDERED: case ORDERED:
10137 /* We can't do anything if OP0 is a condition code value, rather
10138 than an actual data value. */
10140 || CC0_P (XEXP (op0, 0))
10141 || GET_MODE_CLASS (GET_MODE (XEXP (op0, 0))) == MODE_CC)
10144 /* Get the two operands being compared. */
10145 if (GET_CODE (XEXP (op0, 0)) == COMPARE)
10146 tem = XEXP (XEXP (op0, 0), 0), tem1 = XEXP (XEXP (op0, 0), 1);
10148 tem = XEXP (op0, 0), tem1 = XEXP (op0, 1);
10150 /* Check for the cases where we simply want the result of the
10151 earlier test or the opposite of that result. */
10152 if (code == NE || code == EQ
10153 || (GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
10154 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
10155 && (STORE_FLAG_VALUE
10156 & (((HOST_WIDE_INT) 1
10157 << (GET_MODE_BITSIZE (GET_MODE (op0)) - 1))))
10158 && (code == LT || code == GE)))
10160 enum rtx_code new_code;
10161 if (code == LT || code == NE)
10162 new_code = GET_CODE (op0);
10164 new_code = combine_reversed_comparison_code (op0);
10166 if (new_code != UNKNOWN)
10177 /* The sign bit of (ior (plus X (const_int -1)) X) is nonzero
10179 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == PLUS
10180 && XEXP (XEXP (op0, 0), 1) == constm1_rtx
10181 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
10183 op0 = XEXP (op0, 1);
10184 code = (code == GE ? GT : LE);
10190 /* Convert (and (xshift 1 X) Y) to (and (lshiftrt Y X) 1). This
10191 will be converted to a ZERO_EXTRACT later. */
10192 if (const_op == 0 && equality_comparison_p
10193 && GET_CODE (XEXP (op0, 0)) == ASHIFT
10194 && XEXP (XEXP (op0, 0), 0) == const1_rtx)
10196 op0 = simplify_and_const_int
10197 (op0, mode, gen_rtx_LSHIFTRT (mode,
10199 XEXP (XEXP (op0, 0), 1)),
10200 (HOST_WIDE_INT) 1);
10204 /* If we are comparing (and (lshiftrt X C1) C2) for equality with
10205 zero and X is a comparison and C1 and C2 describe only bits set
10206 in STORE_FLAG_VALUE, we can compare with X. */
10207 if (const_op == 0 && equality_comparison_p
10208 && mode_width <= HOST_BITS_PER_WIDE_INT
10209 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10210 && GET_CODE (XEXP (op0, 0)) == LSHIFTRT
10211 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
10212 && INTVAL (XEXP (XEXP (op0, 0), 1)) >= 0
10213 && INTVAL (XEXP (XEXP (op0, 0), 1)) < HOST_BITS_PER_WIDE_INT)
10215 mask = ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
10216 << INTVAL (XEXP (XEXP (op0, 0), 1)));
10217 if ((~STORE_FLAG_VALUE & mask) == 0
10218 && (COMPARISON_P (XEXP (XEXP (op0, 0), 0))
10219 || ((tem = get_last_value (XEXP (XEXP (op0, 0), 0))) != 0
10220 && COMPARISON_P (tem))))
10222 op0 = XEXP (XEXP (op0, 0), 0);
10227 /* If we are doing an equality comparison of an AND of a bit equal
10228 to the sign bit, replace this with a LT or GE comparison of
10229 the underlying value. */
10230 if (equality_comparison_p
10232 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10233 && mode_width <= HOST_BITS_PER_WIDE_INT
10234 && ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
10235 == (unsigned HOST_WIDE_INT) 1 << (mode_width - 1)))
10237 op0 = XEXP (op0, 0);
10238 code = (code == EQ ? GE : LT);
10242 /* If this AND operation is really a ZERO_EXTEND from a narrower
10243 mode, the constant fits within that mode, and this is either an
10244 equality or unsigned comparison, try to do this comparison in
10245 the narrower mode. */
10246 if ((equality_comparison_p || unsigned_comparison_p)
10247 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10248 && (i = exact_log2 ((INTVAL (XEXP (op0, 1))
10249 & GET_MODE_MASK (mode))
10251 && const_op >> i == 0
10252 && (tmode = mode_for_size (i, MODE_INT, 1)) != BLKmode)
10254 op0 = gen_lowpart (tmode, XEXP (op0, 0));
10258 /* If this is (and:M1 (subreg:M2 X 0) (const_int C1)) where C1
10259 fits in both M1 and M2 and the SUBREG is either paradoxical
10260 or represents the low part, permute the SUBREG and the AND
10262 if (GET_CODE (XEXP (op0, 0)) == SUBREG)
10264 unsigned HOST_WIDE_INT c1;
10265 tmode = GET_MODE (SUBREG_REG (XEXP (op0, 0)));
10266 /* Require an integral mode, to avoid creating something like
10268 if (SCALAR_INT_MODE_P (tmode)
10269 /* It is unsafe to commute the AND into the SUBREG if the
10270 SUBREG is paradoxical and WORD_REGISTER_OPERATIONS is
10271 not defined. As originally written the upper bits
10272 have a defined value due to the AND operation.
10273 However, if we commute the AND inside the SUBREG then
10274 they no longer have defined values and the meaning of
10275 the code has been changed. */
10277 #ifdef WORD_REGISTER_OPERATIONS
10278 || (mode_width > GET_MODE_BITSIZE (tmode)
10279 && mode_width <= BITS_PER_WORD)
10281 || (mode_width <= GET_MODE_BITSIZE (tmode)
10282 && subreg_lowpart_p (XEXP (op0, 0))))
10283 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10284 && mode_width <= HOST_BITS_PER_WIDE_INT
10285 && GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT
10286 && ((c1 = INTVAL (XEXP (op0, 1))) & ~mask) == 0
10287 && (c1 & ~GET_MODE_MASK (tmode)) == 0
10289 && c1 != GET_MODE_MASK (tmode))
10291 op0 = gen_binary (AND, tmode,
10292 SUBREG_REG (XEXP (op0, 0)),
10293 gen_int_mode (c1, tmode));
10294 op0 = gen_lowpart (mode, op0);
10299 /* Convert (ne (and (not X) 1) 0) to (eq (and X 1) 0). */
10300 if (const_op == 0 && equality_comparison_p
10301 && XEXP (op0, 1) == const1_rtx
10302 && GET_CODE (XEXP (op0, 0)) == NOT)
10304 op0 = simplify_and_const_int
10305 (NULL_RTX, mode, XEXP (XEXP (op0, 0), 0), (HOST_WIDE_INT) 1);
10306 code = (code == NE ? EQ : NE);
10310 /* Convert (ne (and (lshiftrt (not X)) 1) 0) to
10311 (eq (and (lshiftrt X) 1) 0).
10312 Also handle the case where (not X) is expressed using xor. */
10313 if (const_op == 0 && equality_comparison_p
10314 && XEXP (op0, 1) == const1_rtx
10315 && GET_CODE (XEXP (op0, 0)) == LSHIFTRT)
10317 rtx shift_op = XEXP (XEXP (op0, 0), 0);
10318 rtx shift_count = XEXP (XEXP (op0, 0), 1);
10320 if (GET_CODE (shift_op) == NOT
10321 || (GET_CODE (shift_op) == XOR
10322 && GET_CODE (XEXP (shift_op, 1)) == CONST_INT
10323 && GET_CODE (shift_count) == CONST_INT
10324 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
10325 && (INTVAL (XEXP (shift_op, 1))
10326 == (HOST_WIDE_INT) 1 << INTVAL (shift_count))))
10328 op0 = simplify_and_const_int
10330 gen_rtx_LSHIFTRT (mode, XEXP (shift_op, 0), shift_count),
10331 (HOST_WIDE_INT) 1);
10332 code = (code == NE ? EQ : NE);
10339 /* If we have (compare (ashift FOO N) (const_int C)) and
10340 the high order N bits of FOO (N+1 if an inequality comparison)
10341 are known to be zero, we can do this by comparing FOO with C
10342 shifted right N bits so long as the low-order N bits of C are
10344 if (GET_CODE (XEXP (op0, 1)) == CONST_INT
10345 && INTVAL (XEXP (op0, 1)) >= 0
10346 && ((INTVAL (XEXP (op0, 1)) + ! equality_comparison_p)
10347 < HOST_BITS_PER_WIDE_INT)
10349 & (((HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1))) - 1)) == 0)
10350 && mode_width <= HOST_BITS_PER_WIDE_INT
10351 && (nonzero_bits (XEXP (op0, 0), mode)
10352 & ~(mask >> (INTVAL (XEXP (op0, 1))
10353 + ! equality_comparison_p))) == 0)
10355 /* We must perform a logical shift, not an arithmetic one,
10356 as we want the top N bits of C to be zero. */
10357 unsigned HOST_WIDE_INT temp = const_op & GET_MODE_MASK (mode);
10359 temp >>= INTVAL (XEXP (op0, 1));
10360 op1 = gen_int_mode (temp, mode);
10361 op0 = XEXP (op0, 0);
10365 /* If we are doing a sign bit comparison, it means we are testing
10366 a particular bit. Convert it to the appropriate AND. */
10367 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 1)) == CONST_INT
10368 && mode_width <= HOST_BITS_PER_WIDE_INT)
10370 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
10373 - INTVAL (XEXP (op0, 1)))));
10374 code = (code == LT ? NE : EQ);
10378 /* If this an equality comparison with zero and we are shifting
10379 the low bit to the sign bit, we can convert this to an AND of the
10381 if (const_op == 0 && equality_comparison_p
10382 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10383 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (op0, 1))
10386 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
10387 (HOST_WIDE_INT) 1);
10393 /* If this is an equality comparison with zero, we can do this
10394 as a logical shift, which might be much simpler. */
10395 if (equality_comparison_p && const_op == 0
10396 && GET_CODE (XEXP (op0, 1)) == CONST_INT)
10398 op0 = simplify_shift_const (NULL_RTX, LSHIFTRT, mode,
10400 INTVAL (XEXP (op0, 1)));
10404 /* If OP0 is a sign extension and CODE is not an unsigned comparison,
10405 do the comparison in a narrower mode. */
10406 if (! unsigned_comparison_p
10407 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10408 && GET_CODE (XEXP (op0, 0)) == ASHIFT
10409 && XEXP (op0, 1) == XEXP (XEXP (op0, 0), 1)
10410 && (tmode = mode_for_size (mode_width - INTVAL (XEXP (op0, 1)),
10411 MODE_INT, 1)) != BLKmode
10412 && (((unsigned HOST_WIDE_INT) const_op
10413 + (GET_MODE_MASK (tmode) >> 1) + 1)
10414 <= GET_MODE_MASK (tmode)))
10416 op0 = gen_lowpart (tmode, XEXP (XEXP (op0, 0), 0));
10420 /* Likewise if OP0 is a PLUS of a sign extension with a
10421 constant, which is usually represented with the PLUS
10422 between the shifts. */
10423 if (! unsigned_comparison_p
10424 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10425 && GET_CODE (XEXP (op0, 0)) == PLUS
10426 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
10427 && GET_CODE (XEXP (XEXP (op0, 0), 0)) == ASHIFT
10428 && XEXP (op0, 1) == XEXP (XEXP (XEXP (op0, 0), 0), 1)
10429 && (tmode = mode_for_size (mode_width - INTVAL (XEXP (op0, 1)),
10430 MODE_INT, 1)) != BLKmode
10431 && (((unsigned HOST_WIDE_INT) const_op
10432 + (GET_MODE_MASK (tmode) >> 1) + 1)
10433 <= GET_MODE_MASK (tmode)))
10435 rtx inner = XEXP (XEXP (XEXP (op0, 0), 0), 0);
10436 rtx add_const = XEXP (XEXP (op0, 0), 1);
10437 rtx new_const = gen_binary (ASHIFTRT, GET_MODE (op0), add_const,
10440 op0 = gen_binary (PLUS, tmode,
10441 gen_lowpart (tmode, inner),
10446 /* ... fall through ... */
10448 /* If we have (compare (xshiftrt FOO N) (const_int C)) and
10449 the low order N bits of FOO are known to be zero, we can do this
10450 by comparing FOO with C shifted left N bits so long as no
10451 overflow occurs. */
10452 if (GET_CODE (XEXP (op0, 1)) == CONST_INT
10453 && INTVAL (XEXP (op0, 1)) >= 0
10454 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT
10455 && mode_width <= HOST_BITS_PER_WIDE_INT
10456 && (nonzero_bits (XEXP (op0, 0), mode)
10457 & (((HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1))) - 1)) == 0
10458 && (((unsigned HOST_WIDE_INT) const_op
10459 + (GET_CODE (op0) != LSHIFTRT
10460 ? ((GET_MODE_MASK (mode) >> INTVAL (XEXP (op0, 1)) >> 1)
10463 <= GET_MODE_MASK (mode) >> INTVAL (XEXP (op0, 1))))
10465 /* If the shift was logical, then we must make the condition
10467 if (GET_CODE (op0) == LSHIFTRT)
10468 code = unsigned_condition (code);
10470 const_op <<= INTVAL (XEXP (op0, 1));
10471 op1 = GEN_INT (const_op);
10472 op0 = XEXP (op0, 0);
10476 /* If we are using this shift to extract just the sign bit, we
10477 can replace this with an LT or GE comparison. */
10479 && (equality_comparison_p || sign_bit_comparison_p)
10480 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10481 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (op0, 1))
10484 op0 = XEXP (op0, 0);
10485 code = (code == NE || code == GT ? LT : GE);
10497 /* Now make any compound operations involved in this comparison. Then,
10498 check for an outmost SUBREG on OP0 that is not doing anything or is
10499 paradoxical. The latter transformation must only be performed when
10500 it is known that the "extra" bits will be the same in op0 and op1 or
10501 that they don't matter. There are three cases to consider:
10503 1. SUBREG_REG (op0) is a register. In this case the bits are don't
10504 care bits and we can assume they have any convenient value. So
10505 making the transformation is safe.
10507 2. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is not defined.
10508 In this case the upper bits of op0 are undefined. We should not make
10509 the simplification in that case as we do not know the contents of
10512 3. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is defined and not
10513 UNKNOWN. In that case we know those bits are zeros or ones. We must
10514 also be sure that they are the same as the upper bits of op1.
10516 We can never remove a SUBREG for a non-equality comparison because
10517 the sign bit is in a different place in the underlying object. */
10519 op0 = make_compound_operation (op0, op1 == const0_rtx ? COMPARE : SET);
10520 op1 = make_compound_operation (op1, SET);
10522 if (GET_CODE (op0) == SUBREG && subreg_lowpart_p (op0)
10523 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
10524 && GET_MODE_CLASS (GET_MODE (SUBREG_REG (op0))) == MODE_INT
10525 && (code == NE || code == EQ))
10527 if (GET_MODE_SIZE (GET_MODE (op0))
10528 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (op0))))
10530 /* For paradoxical subregs, allow case 1 as above. Case 3 isn't
10532 if (REG_P (SUBREG_REG (op0)))
10534 op0 = SUBREG_REG (op0);
10535 op1 = gen_lowpart (GET_MODE (op0), op1);
10538 else if ((GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0)))
10539 <= HOST_BITS_PER_WIDE_INT)
10540 && (nonzero_bits (SUBREG_REG (op0),
10541 GET_MODE (SUBREG_REG (op0)))
10542 & ~GET_MODE_MASK (GET_MODE (op0))) == 0)
10544 tem = gen_lowpart (GET_MODE (SUBREG_REG (op0)), op1);
10546 if ((nonzero_bits (tem, GET_MODE (SUBREG_REG (op0)))
10547 & ~GET_MODE_MASK (GET_MODE (op0))) == 0)
10548 op0 = SUBREG_REG (op0), op1 = tem;
10552 /* We now do the opposite procedure: Some machines don't have compare
10553 insns in all modes. If OP0's mode is an integer mode smaller than a
10554 word and we can't do a compare in that mode, see if there is a larger
10555 mode for which we can do the compare. There are a number of cases in
10556 which we can use the wider mode. */
10558 mode = GET_MODE (op0);
10559 if (mode != VOIDmode && GET_MODE_CLASS (mode) == MODE_INT
10560 && GET_MODE_SIZE (mode) < UNITS_PER_WORD
10561 && ! have_insn_for (COMPARE, mode))
10562 for (tmode = GET_MODE_WIDER_MODE (mode);
10564 && GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT);
10565 tmode = GET_MODE_WIDER_MODE (tmode))
10566 if (have_insn_for (COMPARE, tmode))
10570 /* If the only nonzero bits in OP0 and OP1 are those in the
10571 narrower mode and this is an equality or unsigned comparison,
10572 we can use the wider mode. Similarly for sign-extended
10573 values, in which case it is true for all comparisons. */
10574 zero_extended = ((code == EQ || code == NE
10575 || code == GEU || code == GTU
10576 || code == LEU || code == LTU)
10577 && (nonzero_bits (op0, tmode)
10578 & ~GET_MODE_MASK (mode)) == 0
10579 && ((GET_CODE (op1) == CONST_INT
10580 || (nonzero_bits (op1, tmode)
10581 & ~GET_MODE_MASK (mode)) == 0)));
10584 || ((num_sign_bit_copies (op0, tmode)
10585 > (unsigned int) (GET_MODE_BITSIZE (tmode)
10586 - GET_MODE_BITSIZE (mode)))
10587 && (num_sign_bit_copies (op1, tmode)
10588 > (unsigned int) (GET_MODE_BITSIZE (tmode)
10589 - GET_MODE_BITSIZE (mode)))))
10591 /* If OP0 is an AND and we don't have an AND in MODE either,
10592 make a new AND in the proper mode. */
10593 if (GET_CODE (op0) == AND
10594 && !have_insn_for (AND, mode))
10595 op0 = gen_binary (AND, tmode,
10596 gen_lowpart (tmode,
10598 gen_lowpart (tmode,
10601 op0 = gen_lowpart (tmode, op0);
10602 if (zero_extended && GET_CODE (op1) == CONST_INT)
10603 op1 = GEN_INT (INTVAL (op1) & GET_MODE_MASK (mode));
10604 op1 = gen_lowpart (tmode, op1);
10608 /* If this is a test for negative, we can make an explicit
10609 test of the sign bit. */
10611 if (op1 == const0_rtx && (code == LT || code == GE)
10612 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
10614 op0 = gen_binary (AND, tmode,
10615 gen_lowpart (tmode, op0),
10616 GEN_INT ((HOST_WIDE_INT) 1
10617 << (GET_MODE_BITSIZE (mode) - 1)));
10618 code = (code == LT) ? NE : EQ;
10623 #ifdef CANONICALIZE_COMPARISON
10624 /* If this machine only supports a subset of valid comparisons, see if we
10625 can convert an unsupported one into a supported one. */
10626 CANONICALIZE_COMPARISON (code, op0, op1);
10635 /* Like jump.c' reversed_comparison_code, but use combine infrastructure for
10636 searching backward. */
10637 static enum rtx_code
10638 combine_reversed_comparison_code (rtx exp)
10640 enum rtx_code code1 = reversed_comparison_code (exp, NULL);
10643 if (code1 != UNKNOWN
10644 || GET_MODE_CLASS (GET_MODE (XEXP (exp, 0))) != MODE_CC)
10646 /* Otherwise try and find where the condition codes were last set and
10648 x = get_last_value (XEXP (exp, 0));
10649 if (!x || GET_CODE (x) != COMPARE)
10651 return reversed_comparison_code_parts (GET_CODE (exp),
10652 XEXP (x, 0), XEXP (x, 1), NULL);
10655 /* Return comparison with reversed code of EXP and operands OP0 and OP1.
10656 Return NULL_RTX in case we fail to do the reversal. */
10658 reversed_comparison (rtx exp, enum machine_mode mode, rtx op0, rtx op1)
10660 enum rtx_code reversed_code = combine_reversed_comparison_code (exp);
10661 if (reversed_code == UNKNOWN)
10664 return gen_binary (reversed_code, mode, op0, op1);
10667 /* Utility function for following routine. Called when X is part of a value
10668 being stored into last_set_value. Sets last_set_table_tick
10669 for each register mentioned. Similar to mention_regs in cse.c */
10672 update_table_tick (rtx x)
10674 enum rtx_code code = GET_CODE (x);
10675 const char *fmt = GET_RTX_FORMAT (code);
10680 unsigned int regno = REGNO (x);
10681 unsigned int endregno
10682 = regno + (regno < FIRST_PSEUDO_REGISTER
10683 ? hard_regno_nregs[regno][GET_MODE (x)] : 1);
10686 for (r = regno; r < endregno; r++)
10687 reg_stat[r].last_set_table_tick = label_tick;
10692 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
10693 /* Note that we can't have an "E" in values stored; see
10694 get_last_value_validate. */
10697 /* Check for identical subexpressions. If x contains
10698 identical subexpression we only have to traverse one of
10700 if (i == 0 && ARITHMETIC_P (x))
10702 /* Note that at this point x1 has already been
10704 rtx x0 = XEXP (x, 0);
10705 rtx x1 = XEXP (x, 1);
10707 /* If x0 and x1 are identical then there is no need to
10712 /* If x0 is identical to a subexpression of x1 then while
10713 processing x1, x0 has already been processed. Thus we
10714 are done with x. */
10715 if (ARITHMETIC_P (x1)
10716 && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1)))
10719 /* If x1 is identical to a subexpression of x0 then we
10720 still have to process the rest of x0. */
10721 if (ARITHMETIC_P (x0)
10722 && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1)))
10724 update_table_tick (XEXP (x0, x1 == XEXP (x0, 0) ? 1 : 0));
10729 update_table_tick (XEXP (x, i));
10733 /* Record that REG is set to VALUE in insn INSN. If VALUE is zero, we
10734 are saying that the register is clobbered and we no longer know its
10735 value. If INSN is zero, don't update reg_stat[].last_set; this is
10736 only permitted with VALUE also zero and is used to invalidate the
10740 record_value_for_reg (rtx reg, rtx insn, rtx value)
10742 unsigned int regno = REGNO (reg);
10743 unsigned int endregno
10744 = regno + (regno < FIRST_PSEUDO_REGISTER
10745 ? hard_regno_nregs[regno][GET_MODE (reg)] : 1);
10748 /* If VALUE contains REG and we have a previous value for REG, substitute
10749 the previous value. */
10750 if (value && insn && reg_overlap_mentioned_p (reg, value))
10754 /* Set things up so get_last_value is allowed to see anything set up to
10756 subst_low_cuid = INSN_CUID (insn);
10757 tem = get_last_value (reg);
10759 /* If TEM is simply a binary operation with two CLOBBERs as operands,
10760 it isn't going to be useful and will take a lot of time to process,
10761 so just use the CLOBBER. */
10765 if (ARITHMETIC_P (tem)
10766 && GET_CODE (XEXP (tem, 0)) == CLOBBER
10767 && GET_CODE (XEXP (tem, 1)) == CLOBBER)
10768 tem = XEXP (tem, 0);
10770 value = replace_rtx (copy_rtx (value), reg, tem);
10774 /* For each register modified, show we don't know its value, that
10775 we don't know about its bitwise content, that its value has been
10776 updated, and that we don't know the location of the death of the
10778 for (i = regno; i < endregno; i++)
10781 reg_stat[i].last_set = insn;
10783 reg_stat[i].last_set_value = 0;
10784 reg_stat[i].last_set_mode = 0;
10785 reg_stat[i].last_set_nonzero_bits = 0;
10786 reg_stat[i].last_set_sign_bit_copies = 0;
10787 reg_stat[i].last_death = 0;
10790 /* Mark registers that are being referenced in this value. */
10792 update_table_tick (value);
10794 /* Now update the status of each register being set.
10795 If someone is using this register in this block, set this register
10796 to invalid since we will get confused between the two lives in this
10797 basic block. This makes using this register always invalid. In cse, we
10798 scan the table to invalidate all entries using this register, but this
10799 is too much work for us. */
10801 for (i = regno; i < endregno; i++)
10803 reg_stat[i].last_set_label = label_tick;
10804 if (value && reg_stat[i].last_set_table_tick == label_tick)
10805 reg_stat[i].last_set_invalid = 1;
10807 reg_stat[i].last_set_invalid = 0;
10810 /* The value being assigned might refer to X (like in "x++;"). In that
10811 case, we must replace it with (clobber (const_int 0)) to prevent
10813 if (value && ! get_last_value_validate (&value, insn,
10814 reg_stat[regno].last_set_label, 0))
10816 value = copy_rtx (value);
10817 if (! get_last_value_validate (&value, insn,
10818 reg_stat[regno].last_set_label, 1))
10822 /* For the main register being modified, update the value, the mode, the
10823 nonzero bits, and the number of sign bit copies. */
10825 reg_stat[regno].last_set_value = value;
10829 enum machine_mode mode = GET_MODE (reg);
10830 subst_low_cuid = INSN_CUID (insn);
10831 reg_stat[regno].last_set_mode = mode;
10832 if (GET_MODE_CLASS (mode) == MODE_INT
10833 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
10834 mode = nonzero_bits_mode;
10835 reg_stat[regno].last_set_nonzero_bits = nonzero_bits (value, mode);
10836 reg_stat[regno].last_set_sign_bit_copies
10837 = num_sign_bit_copies (value, GET_MODE (reg));
10841 /* Called via note_stores from record_dead_and_set_regs to handle one
10842 SET or CLOBBER in an insn. DATA is the instruction in which the
10843 set is occurring. */
10846 record_dead_and_set_regs_1 (rtx dest, rtx setter, void *data)
10848 rtx record_dead_insn = (rtx) data;
10850 if (GET_CODE (dest) == SUBREG)
10851 dest = SUBREG_REG (dest);
10855 /* If we are setting the whole register, we know its value. Otherwise
10856 show that we don't know the value. We can handle SUBREG in
10858 if (GET_CODE (setter) == SET && dest == SET_DEST (setter))
10859 record_value_for_reg (dest, record_dead_insn, SET_SRC (setter));
10860 else if (GET_CODE (setter) == SET
10861 && GET_CODE (SET_DEST (setter)) == SUBREG
10862 && SUBREG_REG (SET_DEST (setter)) == dest
10863 && GET_MODE_BITSIZE (GET_MODE (dest)) <= BITS_PER_WORD
10864 && subreg_lowpart_p (SET_DEST (setter)))
10865 record_value_for_reg (dest, record_dead_insn,
10866 gen_lowpart (GET_MODE (dest),
10867 SET_SRC (setter)));
10869 record_value_for_reg (dest, record_dead_insn, NULL_RTX);
10871 else if (MEM_P (dest)
10872 /* Ignore pushes, they clobber nothing. */
10873 && ! push_operand (dest, GET_MODE (dest)))
10874 mem_last_set = INSN_CUID (record_dead_insn);
10877 /* Update the records of when each REG was most recently set or killed
10878 for the things done by INSN. This is the last thing done in processing
10879 INSN in the combiner loop.
10881 We update reg_stat[], in particular fields last_set, last_set_value,
10882 last_set_mode, last_set_nonzero_bits, last_set_sign_bit_copies,
10883 last_death, and also the similar information mem_last_set (which insn
10884 most recently modified memory) and last_call_cuid (which insn was the
10885 most recent subroutine call). */
10888 record_dead_and_set_regs (rtx insn)
10893 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
10895 if (REG_NOTE_KIND (link) == REG_DEAD
10896 && REG_P (XEXP (link, 0)))
10898 unsigned int regno = REGNO (XEXP (link, 0));
10899 unsigned int endregno
10900 = regno + (regno < FIRST_PSEUDO_REGISTER
10901 ? hard_regno_nregs[regno][GET_MODE (XEXP (link, 0))]
10904 for (i = regno; i < endregno; i++)
10905 reg_stat[i].last_death = insn;
10907 else if (REG_NOTE_KIND (link) == REG_INC)
10908 record_value_for_reg (XEXP (link, 0), insn, NULL_RTX);
10913 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
10914 if (TEST_HARD_REG_BIT (regs_invalidated_by_call, i))
10916 reg_stat[i].last_set_value = 0;
10917 reg_stat[i].last_set_mode = 0;
10918 reg_stat[i].last_set_nonzero_bits = 0;
10919 reg_stat[i].last_set_sign_bit_copies = 0;
10920 reg_stat[i].last_death = 0;
10923 last_call_cuid = mem_last_set = INSN_CUID (insn);
10925 /* Don't bother recording what this insn does. It might set the
10926 return value register, but we can't combine into a call
10927 pattern anyway, so there's no point trying (and it may cause
10928 a crash, if e.g. we wind up asking for last_set_value of a
10929 SUBREG of the return value register). */
10933 note_stores (PATTERN (insn), record_dead_and_set_regs_1, insn);
10936 /* If a SUBREG has the promoted bit set, it is in fact a property of the
10937 register present in the SUBREG, so for each such SUBREG go back and
10938 adjust nonzero and sign bit information of the registers that are
10939 known to have some zero/sign bits set.
10941 This is needed because when combine blows the SUBREGs away, the
10942 information on zero/sign bits is lost and further combines can be
10943 missed because of that. */
10946 record_promoted_value (rtx insn, rtx subreg)
10949 unsigned int regno = REGNO (SUBREG_REG (subreg));
10950 enum machine_mode mode = GET_MODE (subreg);
10952 if (GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT)
10955 for (links = LOG_LINKS (insn); links;)
10957 insn = XEXP (links, 0);
10958 set = single_set (insn);
10960 if (! set || !REG_P (SET_DEST (set))
10961 || REGNO (SET_DEST (set)) != regno
10962 || GET_MODE (SET_DEST (set)) != GET_MODE (SUBREG_REG (subreg)))
10964 links = XEXP (links, 1);
10968 if (reg_stat[regno].last_set == insn)
10970 if (SUBREG_PROMOTED_UNSIGNED_P (subreg) > 0)
10971 reg_stat[regno].last_set_nonzero_bits &= GET_MODE_MASK (mode);
10974 if (REG_P (SET_SRC (set)))
10976 regno = REGNO (SET_SRC (set));
10977 links = LOG_LINKS (insn);
10984 /* Scan X for promoted SUBREGs. For each one found,
10985 note what it implies to the registers used in it. */
10988 check_promoted_subreg (rtx insn, rtx x)
10990 if (GET_CODE (x) == SUBREG && SUBREG_PROMOTED_VAR_P (x)
10991 && REG_P (SUBREG_REG (x)))
10992 record_promoted_value (insn, x);
10995 const char *format = GET_RTX_FORMAT (GET_CODE (x));
10998 for (i = 0; i < GET_RTX_LENGTH (GET_CODE (x)); i++)
11002 check_promoted_subreg (insn, XEXP (x, i));
11006 if (XVEC (x, i) != 0)
11007 for (j = 0; j < XVECLEN (x, i); j++)
11008 check_promoted_subreg (insn, XVECEXP (x, i, j));
11014 /* Utility routine for the following function. Verify that all the registers
11015 mentioned in *LOC are valid when *LOC was part of a value set when
11016 label_tick == TICK. Return 0 if some are not.
11018 If REPLACE is nonzero, replace the invalid reference with
11019 (clobber (const_int 0)) and return 1. This replacement is useful because
11020 we often can get useful information about the form of a value (e.g., if
11021 it was produced by a shift that always produces -1 or 0) even though
11022 we don't know exactly what registers it was produced from. */
11025 get_last_value_validate (rtx *loc, rtx insn, int tick, int replace)
11028 const char *fmt = GET_RTX_FORMAT (GET_CODE (x));
11029 int len = GET_RTX_LENGTH (GET_CODE (x));
11034 unsigned int regno = REGNO (x);
11035 unsigned int endregno
11036 = regno + (regno < FIRST_PSEUDO_REGISTER
11037 ? hard_regno_nregs[regno][GET_MODE (x)] : 1);
11040 for (j = regno; j < endregno; j++)
11041 if (reg_stat[j].last_set_invalid
11042 /* If this is a pseudo-register that was only set once and not
11043 live at the beginning of the function, it is always valid. */
11044 || (! (regno >= FIRST_PSEUDO_REGISTER
11045 && REG_N_SETS (regno) == 1
11046 && (! REGNO_REG_SET_P
11047 (ENTRY_BLOCK_PTR->next_bb->global_live_at_start, regno)))
11048 && reg_stat[j].last_set_label > tick))
11051 *loc = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
11057 /* If this is a memory reference, make sure that there were
11058 no stores after it that might have clobbered the value. We don't
11059 have alias info, so we assume any store invalidates it. */
11060 else if (MEM_P (x) && !MEM_READONLY_P (x)
11061 && INSN_CUID (insn) <= mem_last_set)
11064 *loc = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
11068 for (i = 0; i < len; i++)
11072 /* Check for identical subexpressions. If x contains
11073 identical subexpression we only have to traverse one of
11075 if (i == 1 && ARITHMETIC_P (x))
11077 /* Note that at this point x0 has already been checked
11078 and found valid. */
11079 rtx x0 = XEXP (x, 0);
11080 rtx x1 = XEXP (x, 1);
11082 /* If x0 and x1 are identical then x is also valid. */
11086 /* If x1 is identical to a subexpression of x0 then
11087 while checking x0, x1 has already been checked. Thus
11088 it is valid and so as x. */
11089 if (ARITHMETIC_P (x0)
11090 && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1)))
11093 /* If x0 is identical to a subexpression of x1 then x is
11094 valid iff the rest of x1 is valid. */
11095 if (ARITHMETIC_P (x1)
11096 && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1)))
11098 get_last_value_validate (&XEXP (x1,
11099 x0 == XEXP (x1, 0) ? 1 : 0),
11100 insn, tick, replace);
11103 if (get_last_value_validate (&XEXP (x, i), insn, tick,
11107 /* Don't bother with these. They shouldn't occur anyway. */
11108 else if (fmt[i] == 'E')
11112 /* If we haven't found a reason for it to be invalid, it is valid. */
11116 /* Get the last value assigned to X, if known. Some registers
11117 in the value may be replaced with (clobber (const_int 0)) if their value
11118 is known longer known reliably. */
11121 get_last_value (rtx x)
11123 unsigned int regno;
11126 /* If this is a non-paradoxical SUBREG, get the value of its operand and
11127 then convert it to the desired mode. If this is a paradoxical SUBREG,
11128 we cannot predict what values the "extra" bits might have. */
11129 if (GET_CODE (x) == SUBREG
11130 && subreg_lowpart_p (x)
11131 && (GET_MODE_SIZE (GET_MODE (x))
11132 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
11133 && (value = get_last_value (SUBREG_REG (x))) != 0)
11134 return gen_lowpart (GET_MODE (x), value);
11140 value = reg_stat[regno].last_set_value;
11142 /* If we don't have a value, or if it isn't for this basic block and
11143 it's either a hard register, set more than once, or it's a live
11144 at the beginning of the function, return 0.
11146 Because if it's not live at the beginning of the function then the reg
11147 is always set before being used (is never used without being set).
11148 And, if it's set only once, and it's always set before use, then all
11149 uses must have the same last value, even if it's not from this basic
11153 || (reg_stat[regno].last_set_label != label_tick
11154 && (regno < FIRST_PSEUDO_REGISTER
11155 || REG_N_SETS (regno) != 1
11156 || (REGNO_REG_SET_P
11157 (ENTRY_BLOCK_PTR->next_bb->global_live_at_start, regno)))))
11160 /* If the value was set in a later insn than the ones we are processing,
11161 we can't use it even if the register was only set once. */
11162 if (INSN_CUID (reg_stat[regno].last_set) >= subst_low_cuid)
11165 /* If the value has all its registers valid, return it. */
11166 if (get_last_value_validate (&value, reg_stat[regno].last_set,
11167 reg_stat[regno].last_set_label, 0))
11170 /* Otherwise, make a copy and replace any invalid register with
11171 (clobber (const_int 0)). If that fails for some reason, return 0. */
11173 value = copy_rtx (value);
11174 if (get_last_value_validate (&value, reg_stat[regno].last_set,
11175 reg_stat[regno].last_set_label, 1))
11181 /* Return nonzero if expression X refers to a REG or to memory
11182 that is set in an instruction more recent than FROM_CUID. */
11185 use_crosses_set_p (rtx x, int from_cuid)
11189 enum rtx_code code = GET_CODE (x);
11193 unsigned int regno = REGNO (x);
11194 unsigned endreg = regno + (regno < FIRST_PSEUDO_REGISTER
11195 ? hard_regno_nregs[regno][GET_MODE (x)] : 1);
11197 #ifdef PUSH_ROUNDING
11198 /* Don't allow uses of the stack pointer to be moved,
11199 because we don't know whether the move crosses a push insn. */
11200 if (regno == STACK_POINTER_REGNUM && PUSH_ARGS)
11203 for (; regno < endreg; regno++)
11204 if (reg_stat[regno].last_set
11205 && INSN_CUID (reg_stat[regno].last_set) > from_cuid)
11210 if (code == MEM && mem_last_set > from_cuid)
11213 fmt = GET_RTX_FORMAT (code);
11215 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
11220 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
11221 if (use_crosses_set_p (XVECEXP (x, i, j), from_cuid))
11224 else if (fmt[i] == 'e'
11225 && use_crosses_set_p (XEXP (x, i), from_cuid))
11231 /* Define three variables used for communication between the following
11234 static unsigned int reg_dead_regno, reg_dead_endregno;
11235 static int reg_dead_flag;
11237 /* Function called via note_stores from reg_dead_at_p.
11239 If DEST is within [reg_dead_regno, reg_dead_endregno), set
11240 reg_dead_flag to 1 if X is a CLOBBER and to -1 it is a SET. */
11243 reg_dead_at_p_1 (rtx dest, rtx x, void *data ATTRIBUTE_UNUSED)
11245 unsigned int regno, endregno;
11250 regno = REGNO (dest);
11251 endregno = regno + (regno < FIRST_PSEUDO_REGISTER
11252 ? hard_regno_nregs[regno][GET_MODE (dest)] : 1);
11254 if (reg_dead_endregno > regno && reg_dead_regno < endregno)
11255 reg_dead_flag = (GET_CODE (x) == CLOBBER) ? 1 : -1;
11258 /* Return nonzero if REG is known to be dead at INSN.
11260 We scan backwards from INSN. If we hit a REG_DEAD note or a CLOBBER
11261 referencing REG, it is dead. If we hit a SET referencing REG, it is
11262 live. Otherwise, see if it is live or dead at the start of the basic
11263 block we are in. Hard regs marked as being live in NEWPAT_USED_REGS
11264 must be assumed to be always live. */
11267 reg_dead_at_p (rtx reg, rtx insn)
11272 /* Set variables for reg_dead_at_p_1. */
11273 reg_dead_regno = REGNO (reg);
11274 reg_dead_endregno = reg_dead_regno + (reg_dead_regno < FIRST_PSEUDO_REGISTER
11275 ? hard_regno_nregs[reg_dead_regno]
11281 /* Check that reg isn't mentioned in NEWPAT_USED_REGS. For fixed registers
11282 we allow the machine description to decide whether use-and-clobber
11283 patterns are OK. */
11284 if (reg_dead_regno < FIRST_PSEUDO_REGISTER)
11286 for (i = reg_dead_regno; i < reg_dead_endregno; i++)
11287 if (!fixed_regs[i] && TEST_HARD_REG_BIT (newpat_used_regs, i))
11291 /* Scan backwards until we find a REG_DEAD note, SET, CLOBBER, label, or
11292 beginning of function. */
11293 for (; insn && !LABEL_P (insn) && !BARRIER_P (insn);
11294 insn = prev_nonnote_insn (insn))
11296 note_stores (PATTERN (insn), reg_dead_at_p_1, NULL);
11298 return reg_dead_flag == 1 ? 1 : 0;
11300 if (find_regno_note (insn, REG_DEAD, reg_dead_regno))
11304 /* Get the basic block that we were in. */
11306 block = ENTRY_BLOCK_PTR->next_bb;
11309 FOR_EACH_BB (block)
11310 if (insn == BB_HEAD (block))
11313 if (block == EXIT_BLOCK_PTR)
11317 for (i = reg_dead_regno; i < reg_dead_endregno; i++)
11318 if (REGNO_REG_SET_P (block->global_live_at_start, i))
11324 /* Note hard registers in X that are used. This code is similar to
11325 that in flow.c, but much simpler since we don't care about pseudos. */
11328 mark_used_regs_combine (rtx x)
11330 RTX_CODE code = GET_CODE (x);
11331 unsigned int regno;
11344 case ADDR_DIFF_VEC:
11347 /* CC0 must die in the insn after it is set, so we don't need to take
11348 special note of it here. */
11354 /* If we are clobbering a MEM, mark any hard registers inside the
11355 address as used. */
11356 if (MEM_P (XEXP (x, 0)))
11357 mark_used_regs_combine (XEXP (XEXP (x, 0), 0));
11362 /* A hard reg in a wide mode may really be multiple registers.
11363 If so, mark all of them just like the first. */
11364 if (regno < FIRST_PSEUDO_REGISTER)
11366 unsigned int endregno, r;
11368 /* None of this applies to the stack, frame or arg pointers. */
11369 if (regno == STACK_POINTER_REGNUM
11370 #if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM
11371 || regno == HARD_FRAME_POINTER_REGNUM
11373 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
11374 || (regno == ARG_POINTER_REGNUM && fixed_regs[regno])
11376 || regno == FRAME_POINTER_REGNUM)
11379 endregno = regno + hard_regno_nregs[regno][GET_MODE (x)];
11380 for (r = regno; r < endregno; r++)
11381 SET_HARD_REG_BIT (newpat_used_regs, r);
11387 /* If setting a MEM, or a SUBREG of a MEM, then note any hard regs in
11389 rtx testreg = SET_DEST (x);
11391 while (GET_CODE (testreg) == SUBREG
11392 || GET_CODE (testreg) == ZERO_EXTRACT
11393 || GET_CODE (testreg) == SIGN_EXTRACT
11394 || GET_CODE (testreg) == STRICT_LOW_PART)
11395 testreg = XEXP (testreg, 0);
11397 if (MEM_P (testreg))
11398 mark_used_regs_combine (XEXP (testreg, 0));
11400 mark_used_regs_combine (SET_SRC (x));
11408 /* Recursively scan the operands of this expression. */
11411 const char *fmt = GET_RTX_FORMAT (code);
11413 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
11416 mark_used_regs_combine (XEXP (x, i));
11417 else if (fmt[i] == 'E')
11421 for (j = 0; j < XVECLEN (x, i); j++)
11422 mark_used_regs_combine (XVECEXP (x, i, j));
11428 /* Remove register number REGNO from the dead registers list of INSN.
11430 Return the note used to record the death, if there was one. */
11433 remove_death (unsigned int regno, rtx insn)
11435 rtx note = find_regno_note (insn, REG_DEAD, regno);
11439 REG_N_DEATHS (regno)--;
11440 remove_note (insn, note);
11446 /* For each register (hardware or pseudo) used within expression X, if its
11447 death is in an instruction with cuid between FROM_CUID (inclusive) and
11448 TO_INSN (exclusive), put a REG_DEAD note for that register in the
11449 list headed by PNOTES.
11451 That said, don't move registers killed by maybe_kill_insn.
11453 This is done when X is being merged by combination into TO_INSN. These
11454 notes will then be distributed as needed. */
11457 move_deaths (rtx x, rtx maybe_kill_insn, int from_cuid, rtx to_insn,
11462 enum rtx_code code = GET_CODE (x);
11466 unsigned int regno = REGNO (x);
11467 rtx where_dead = reg_stat[regno].last_death;
11468 rtx before_dead, after_dead;
11470 /* Don't move the register if it gets killed in between from and to. */
11471 if (maybe_kill_insn && reg_set_p (x, maybe_kill_insn)
11472 && ! reg_referenced_p (x, maybe_kill_insn))
11475 /* WHERE_DEAD could be a USE insn made by combine, so first we
11476 make sure that we have insns with valid INSN_CUID values. */
11477 before_dead = where_dead;
11478 while (before_dead && INSN_UID (before_dead) > max_uid_cuid)
11479 before_dead = PREV_INSN (before_dead);
11481 after_dead = where_dead;
11482 while (after_dead && INSN_UID (after_dead) > max_uid_cuid)
11483 after_dead = NEXT_INSN (after_dead);
11485 if (before_dead && after_dead
11486 && INSN_CUID (before_dead) >= from_cuid
11487 && (INSN_CUID (after_dead) < INSN_CUID (to_insn)
11488 || (where_dead != after_dead
11489 && INSN_CUID (after_dead) == INSN_CUID (to_insn))))
11491 rtx note = remove_death (regno, where_dead);
11493 /* It is possible for the call above to return 0. This can occur
11494 when last_death points to I2 or I1 that we combined with.
11495 In that case make a new note.
11497 We must also check for the case where X is a hard register
11498 and NOTE is a death note for a range of hard registers
11499 including X. In that case, we must put REG_DEAD notes for
11500 the remaining registers in place of NOTE. */
11502 if (note != 0 && regno < FIRST_PSEUDO_REGISTER
11503 && (GET_MODE_SIZE (GET_MODE (XEXP (note, 0)))
11504 > GET_MODE_SIZE (GET_MODE (x))))
11506 unsigned int deadregno = REGNO (XEXP (note, 0));
11507 unsigned int deadend
11508 = (deadregno + hard_regno_nregs[deadregno]
11509 [GET_MODE (XEXP (note, 0))]);
11510 unsigned int ourend
11511 = regno + hard_regno_nregs[regno][GET_MODE (x)];
11514 for (i = deadregno; i < deadend; i++)
11515 if (i < regno || i >= ourend)
11516 REG_NOTES (where_dead)
11517 = gen_rtx_EXPR_LIST (REG_DEAD,
11519 REG_NOTES (where_dead));
11522 /* If we didn't find any note, or if we found a REG_DEAD note that
11523 covers only part of the given reg, and we have a multi-reg hard
11524 register, then to be safe we must check for REG_DEAD notes
11525 for each register other than the first. They could have
11526 their own REG_DEAD notes lying around. */
11527 else if ((note == 0
11529 && (GET_MODE_SIZE (GET_MODE (XEXP (note, 0)))
11530 < GET_MODE_SIZE (GET_MODE (x)))))
11531 && regno < FIRST_PSEUDO_REGISTER
11532 && hard_regno_nregs[regno][GET_MODE (x)] > 1)
11534 unsigned int ourend
11535 = regno + hard_regno_nregs[regno][GET_MODE (x)];
11536 unsigned int i, offset;
11540 offset = hard_regno_nregs[regno][GET_MODE (XEXP (note, 0))];
11544 for (i = regno + offset; i < ourend; i++)
11545 move_deaths (regno_reg_rtx[i],
11546 maybe_kill_insn, from_cuid, to_insn, &oldnotes);
11549 if (note != 0 && GET_MODE (XEXP (note, 0)) == GET_MODE (x))
11551 XEXP (note, 1) = *pnotes;
11555 *pnotes = gen_rtx_EXPR_LIST (REG_DEAD, x, *pnotes);
11557 REG_N_DEATHS (regno)++;
11563 else if (GET_CODE (x) == SET)
11565 rtx dest = SET_DEST (x);
11567 move_deaths (SET_SRC (x), maybe_kill_insn, from_cuid, to_insn, pnotes);
11569 /* In the case of a ZERO_EXTRACT, a STRICT_LOW_PART, or a SUBREG
11570 that accesses one word of a multi-word item, some
11571 piece of everything register in the expression is used by
11572 this insn, so remove any old death. */
11573 /* ??? So why do we test for equality of the sizes? */
11575 if (GET_CODE (dest) == ZERO_EXTRACT
11576 || GET_CODE (dest) == STRICT_LOW_PART
11577 || (GET_CODE (dest) == SUBREG
11578 && (((GET_MODE_SIZE (GET_MODE (dest))
11579 + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
11580 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (dest)))
11581 + UNITS_PER_WORD - 1) / UNITS_PER_WORD))))
11583 move_deaths (dest, maybe_kill_insn, from_cuid, to_insn, pnotes);
11587 /* If this is some other SUBREG, we know it replaces the entire
11588 value, so use that as the destination. */
11589 if (GET_CODE (dest) == SUBREG)
11590 dest = SUBREG_REG (dest);
11592 /* If this is a MEM, adjust deaths of anything used in the address.
11593 For a REG (the only other possibility), the entire value is
11594 being replaced so the old value is not used in this insn. */
11597 move_deaths (XEXP (dest, 0), maybe_kill_insn, from_cuid,
11602 else if (GET_CODE (x) == CLOBBER)
11605 len = GET_RTX_LENGTH (code);
11606 fmt = GET_RTX_FORMAT (code);
11608 for (i = 0; i < len; i++)
11613 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
11614 move_deaths (XVECEXP (x, i, j), maybe_kill_insn, from_cuid,
11617 else if (fmt[i] == 'e')
11618 move_deaths (XEXP (x, i), maybe_kill_insn, from_cuid, to_insn, pnotes);
11622 /* Return 1 if X is the target of a bit-field assignment in BODY, the
11623 pattern of an insn. X must be a REG. */
11626 reg_bitfield_target_p (rtx x, rtx body)
11630 if (GET_CODE (body) == SET)
11632 rtx dest = SET_DEST (body);
11634 unsigned int regno, tregno, endregno, endtregno;
11636 if (GET_CODE (dest) == ZERO_EXTRACT)
11637 target = XEXP (dest, 0);
11638 else if (GET_CODE (dest) == STRICT_LOW_PART)
11639 target = SUBREG_REG (XEXP (dest, 0));
11643 if (GET_CODE (target) == SUBREG)
11644 target = SUBREG_REG (target);
11646 if (!REG_P (target))
11649 tregno = REGNO (target), regno = REGNO (x);
11650 if (tregno >= FIRST_PSEUDO_REGISTER || regno >= FIRST_PSEUDO_REGISTER)
11651 return target == x;
11653 endtregno = tregno + hard_regno_nregs[tregno][GET_MODE (target)];
11654 endregno = regno + hard_regno_nregs[regno][GET_MODE (x)];
11656 return endregno > tregno && regno < endtregno;
11659 else if (GET_CODE (body) == PARALLEL)
11660 for (i = XVECLEN (body, 0) - 1; i >= 0; i--)
11661 if (reg_bitfield_target_p (x, XVECEXP (body, 0, i)))
11667 /* Given a chain of REG_NOTES originally from FROM_INSN, try to place them
11668 as appropriate. I3 and I2 are the insns resulting from the combination
11669 insns including FROM (I2 may be zero).
11671 Each note in the list is either ignored or placed on some insns, depending
11672 on the type of note. */
11675 distribute_notes (rtx notes, rtx from_insn, rtx i3, rtx i2)
11677 rtx note, next_note;
11680 for (note = notes; note; note = next_note)
11682 rtx place = 0, place2 = 0;
11684 /* If this NOTE references a pseudo register, ensure it references
11685 the latest copy of that register. */
11686 if (XEXP (note, 0) && REG_P (XEXP (note, 0))
11687 && REGNO (XEXP (note, 0)) >= FIRST_PSEUDO_REGISTER)
11688 XEXP (note, 0) = regno_reg_rtx[REGNO (XEXP (note, 0))];
11690 next_note = XEXP (note, 1);
11691 switch (REG_NOTE_KIND (note))
11695 /* Doesn't matter much where we put this, as long as it's somewhere.
11696 It is preferable to keep these notes on branches, which is most
11697 likely to be i3. */
11701 case REG_VALUE_PROFILE:
11702 /* Just get rid of this note, as it is unused later anyway. */
11705 case REG_NON_LOCAL_GOTO:
11708 else if (i2 && JUMP_P (i2))
11714 case REG_EH_REGION:
11715 /* These notes must remain with the call or trapping instruction. */
11718 else if (i2 && CALL_P (i2))
11720 else if (flag_non_call_exceptions)
11722 if (may_trap_p (i3))
11724 else if (i2 && may_trap_p (i2))
11726 /* ??? Otherwise assume we've combined things such that we
11727 can now prove that the instructions can't trap. Drop the
11728 note in this case. */
11734 case REG_ALWAYS_RETURN:
11737 /* These notes must remain with the call. It should not be
11738 possible for both I2 and I3 to be a call. */
11741 else if (i2 && CALL_P (i2))
11748 /* Any clobbers for i3 may still exist, and so we must process
11749 REG_UNUSED notes from that insn.
11751 Any clobbers from i2 or i1 can only exist if they were added by
11752 recog_for_combine. In that case, recog_for_combine created the
11753 necessary REG_UNUSED notes. Trying to keep any original
11754 REG_UNUSED notes from these insns can cause incorrect output
11755 if it is for the same register as the original i3 dest.
11756 In that case, we will notice that the register is set in i3,
11757 and then add a REG_UNUSED note for the destination of i3, which
11758 is wrong. However, it is possible to have REG_UNUSED notes from
11759 i2 or i1 for register which were both used and clobbered, so
11760 we keep notes from i2 or i1 if they will turn into REG_DEAD
11763 /* If this register is set or clobbered in I3, put the note there
11764 unless there is one already. */
11765 if (reg_set_p (XEXP (note, 0), PATTERN (i3)))
11767 if (from_insn != i3)
11770 if (! (REG_P (XEXP (note, 0))
11771 ? find_regno_note (i3, REG_UNUSED, REGNO (XEXP (note, 0)))
11772 : find_reg_note (i3, REG_UNUSED, XEXP (note, 0))))
11775 /* Otherwise, if this register is used by I3, then this register
11776 now dies here, so we must put a REG_DEAD note here unless there
11778 else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3))
11779 && ! (REG_P (XEXP (note, 0))
11780 ? find_regno_note (i3, REG_DEAD,
11781 REGNO (XEXP (note, 0)))
11782 : find_reg_note (i3, REG_DEAD, XEXP (note, 0))))
11784 PUT_REG_NOTE_KIND (note, REG_DEAD);
11792 /* These notes say something about results of an insn. We can
11793 only support them if they used to be on I3 in which case they
11794 remain on I3. Otherwise they are ignored.
11796 If the note refers to an expression that is not a constant, we
11797 must also ignore the note since we cannot tell whether the
11798 equivalence is still true. It might be possible to do
11799 slightly better than this (we only have a problem if I2DEST
11800 or I1DEST is present in the expression), but it doesn't
11801 seem worth the trouble. */
11803 if (from_insn == i3
11804 && (XEXP (note, 0) == 0 || CONSTANT_P (XEXP (note, 0))))
11809 case REG_NO_CONFLICT:
11810 /* These notes say something about how a register is used. They must
11811 be present on any use of the register in I2 or I3. */
11812 if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3)))
11815 if (i2 && reg_mentioned_p (XEXP (note, 0), PATTERN (i2)))
11825 /* This can show up in several ways -- either directly in the
11826 pattern, or hidden off in the constant pool with (or without?)
11827 a REG_EQUAL note. */
11828 /* ??? Ignore the without-reg_equal-note problem for now. */
11829 if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3))
11830 || ((tem = find_reg_note (i3, REG_EQUAL, NULL_RTX))
11831 && GET_CODE (XEXP (tem, 0)) == LABEL_REF
11832 && XEXP (XEXP (tem, 0), 0) == XEXP (note, 0)))
11836 && (reg_mentioned_p (XEXP (note, 0), PATTERN (i2))
11837 || ((tem = find_reg_note (i2, REG_EQUAL, NULL_RTX))
11838 && GET_CODE (XEXP (tem, 0)) == LABEL_REF
11839 && XEXP (XEXP (tem, 0), 0) == XEXP (note, 0))))
11847 /* Don't attach REG_LABEL note to a JUMP_INSN. Add
11848 a JUMP_LABEL instead or decrement LABEL_NUSES. */
11849 if (place && JUMP_P (place))
11851 if (!JUMP_LABEL (place))
11852 JUMP_LABEL (place) = XEXP (note, 0);
11853 else if (JUMP_LABEL (place) != XEXP (note, 0))
11855 else if (LABEL_P (JUMP_LABEL (place)))
11856 LABEL_NUSES (JUMP_LABEL (place))--;
11859 if (place2 && JUMP_P (place2))
11861 if (!JUMP_LABEL (place2))
11862 JUMP_LABEL (place2) = XEXP (note, 0);
11863 else if (JUMP_LABEL (place2) != XEXP (note, 0))
11865 else if (LABEL_P (JUMP_LABEL (place2)))
11866 LABEL_NUSES (JUMP_LABEL (place2))--;
11872 /* This note says something about the value of a register prior
11873 to the execution of an insn. It is too much trouble to see
11874 if the note is still correct in all situations. It is better
11875 to simply delete it. */
11879 /* If the insn previously containing this note still exists,
11880 put it back where it was. Otherwise move it to the previous
11881 insn. Adjust the corresponding REG_LIBCALL note. */
11882 if (!NOTE_P (from_insn))
11886 tem = find_reg_note (XEXP (note, 0), REG_LIBCALL, NULL_RTX);
11887 place = prev_real_insn (from_insn);
11889 XEXP (tem, 0) = place;
11890 /* If we're deleting the last remaining instruction of a
11891 libcall sequence, don't add the notes. */
11892 else if (XEXP (note, 0) == from_insn)
11894 /* Don't add the dangling REG_RETVAL note. */
11901 /* This is handled similarly to REG_RETVAL. */
11902 if (!NOTE_P (from_insn))
11906 tem = find_reg_note (XEXP (note, 0), REG_RETVAL, NULL_RTX);
11907 place = next_real_insn (from_insn);
11909 XEXP (tem, 0) = place;
11910 /* If we're deleting the last remaining instruction of a
11911 libcall sequence, don't add the notes. */
11912 else if (XEXP (note, 0) == from_insn)
11914 /* Don't add the dangling REG_LIBCALL note. */
11921 /* If the register is used as an input in I3, it dies there.
11922 Similarly for I2, if it is nonzero and adjacent to I3.
11924 If the register is not used as an input in either I3 or I2
11925 and it is not one of the registers we were supposed to eliminate,
11926 there are two possibilities. We might have a non-adjacent I2
11927 or we might have somehow eliminated an additional register
11928 from a computation. For example, we might have had A & B where
11929 we discover that B will always be zero. In this case we will
11930 eliminate the reference to A.
11932 In both cases, we must search to see if we can find a previous
11933 use of A and put the death note there. */
11936 && CALL_P (from_insn)
11937 && find_reg_fusage (from_insn, USE, XEXP (note, 0)))
11939 else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3)))
11941 else if (i2 != 0 && next_nonnote_insn (i2) == i3
11942 && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
11947 basic_block bb = this_basic_block;
11949 for (tem = PREV_INSN (i3); place == 0; tem = PREV_INSN (tem))
11951 if (! INSN_P (tem))
11953 if (tem == BB_HEAD (bb))
11958 /* If the register is being set at TEM, see if that is all
11959 TEM is doing. If so, delete TEM. Otherwise, make this
11960 into a REG_UNUSED note instead. Don't delete sets to
11961 global register vars. */
11962 if ((REGNO (XEXP (note, 0)) >= FIRST_PSEUDO_REGISTER
11963 || !global_regs[REGNO (XEXP (note, 0))])
11964 && reg_set_p (XEXP (note, 0), PATTERN (tem)))
11966 rtx set = single_set (tem);
11967 rtx inner_dest = 0;
11969 rtx cc0_setter = NULL_RTX;
11973 for (inner_dest = SET_DEST (set);
11974 (GET_CODE (inner_dest) == STRICT_LOW_PART
11975 || GET_CODE (inner_dest) == SUBREG
11976 || GET_CODE (inner_dest) == ZERO_EXTRACT);
11977 inner_dest = XEXP (inner_dest, 0))
11980 /* Verify that it was the set, and not a clobber that
11981 modified the register.
11983 CC0 targets must be careful to maintain setter/user
11984 pairs. If we cannot delete the setter due to side
11985 effects, mark the user with an UNUSED note instead
11988 if (set != 0 && ! side_effects_p (SET_SRC (set))
11989 && rtx_equal_p (XEXP (note, 0), inner_dest)
11991 && (! reg_mentioned_p (cc0_rtx, SET_SRC (set))
11992 || ((cc0_setter = prev_cc0_setter (tem)) != NULL
11993 && sets_cc0_p (PATTERN (cc0_setter)) > 0))
11997 /* Move the notes and links of TEM elsewhere.
11998 This might delete other dead insns recursively.
11999 First set the pattern to something that won't use
12001 rtx old_notes = REG_NOTES (tem);
12003 PATTERN (tem) = pc_rtx;
12004 REG_NOTES (tem) = NULL;
12006 distribute_notes (old_notes, tem, tem, NULL_RTX);
12007 distribute_links (LOG_LINKS (tem));
12009 SET_INSN_DELETED (tem);
12012 /* Delete the setter too. */
12015 PATTERN (cc0_setter) = pc_rtx;
12016 old_notes = REG_NOTES (cc0_setter);
12017 REG_NOTES (cc0_setter) = NULL;
12019 distribute_notes (old_notes, cc0_setter,
12020 cc0_setter, NULL_RTX);
12021 distribute_links (LOG_LINKS (cc0_setter));
12023 SET_INSN_DELETED (cc0_setter);
12029 PUT_REG_NOTE_KIND (note, REG_UNUSED);
12031 /* If there isn't already a REG_UNUSED note, put one
12032 here. Do not place a REG_DEAD note, even if
12033 the register is also used here; that would not
12034 match the algorithm used in lifetime analysis
12035 and can cause the consistency check in the
12036 scheduler to fail. */
12037 if (! find_regno_note (tem, REG_UNUSED,
12038 REGNO (XEXP (note, 0))))
12043 else if (reg_referenced_p (XEXP (note, 0), PATTERN (tem))
12045 && find_reg_fusage (tem, USE, XEXP (note, 0))))
12049 /* If we are doing a 3->2 combination, and we have a
12050 register which formerly died in i3 and was not used
12051 by i2, which now no longer dies in i3 and is used in
12052 i2 but does not die in i2, and place is between i2
12053 and i3, then we may need to move a link from place to
12055 if (i2 && INSN_UID (place) <= max_uid_cuid
12056 && INSN_CUID (place) > INSN_CUID (i2)
12058 && INSN_CUID (from_insn) > INSN_CUID (i2)
12059 && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
12061 rtx links = LOG_LINKS (place);
12062 LOG_LINKS (place) = 0;
12063 distribute_links (links);
12068 if (tem == BB_HEAD (bb))
12072 /* We haven't found an insn for the death note and it
12073 is still a REG_DEAD note, but we have hit the beginning
12074 of the block. If the existing life info says the reg
12075 was dead, there's nothing left to do. Otherwise, we'll
12076 need to do a global life update after combine. */
12077 if (REG_NOTE_KIND (note) == REG_DEAD && place == 0
12078 && REGNO_REG_SET_P (bb->global_live_at_start,
12079 REGNO (XEXP (note, 0))))
12080 SET_BIT (refresh_blocks, this_basic_block->index);
12083 /* If the register is set or already dead at PLACE, we needn't do
12084 anything with this note if it is still a REG_DEAD note.
12085 We check here if it is set at all, not if is it totally replaced,
12086 which is what `dead_or_set_p' checks, so also check for it being
12089 if (place && REG_NOTE_KIND (note) == REG_DEAD)
12091 unsigned int regno = REGNO (XEXP (note, 0));
12093 /* Similarly, if the instruction on which we want to place
12094 the note is a noop, we'll need do a global live update
12095 after we remove them in delete_noop_moves. */
12096 if (noop_move_p (place))
12097 SET_BIT (refresh_blocks, this_basic_block->index);
12099 if (dead_or_set_p (place, XEXP (note, 0))
12100 || reg_bitfield_target_p (XEXP (note, 0), PATTERN (place)))
12102 /* Unless the register previously died in PLACE, clear
12103 last_death. [I no longer understand why this is
12105 if (reg_stat[regno].last_death != place)
12106 reg_stat[regno].last_death = 0;
12110 reg_stat[regno].last_death = place;
12112 /* If this is a death note for a hard reg that is occupying
12113 multiple registers, ensure that we are still using all
12114 parts of the object. If we find a piece of the object
12115 that is unused, we must arrange for an appropriate REG_DEAD
12116 note to be added for it. However, we can't just emit a USE
12117 and tag the note to it, since the register might actually
12118 be dead; so we recourse, and the recursive call then finds
12119 the previous insn that used this register. */
12121 if (place && regno < FIRST_PSEUDO_REGISTER
12122 && hard_regno_nregs[regno][GET_MODE (XEXP (note, 0))] > 1)
12124 unsigned int endregno
12125 = regno + hard_regno_nregs[regno]
12126 [GET_MODE (XEXP (note, 0))];
12130 for (i = regno; i < endregno; i++)
12131 if ((! refers_to_regno_p (i, i + 1, PATTERN (place), 0)
12132 && ! find_regno_fusage (place, USE, i))
12133 || dead_or_set_regno_p (place, i))
12138 /* Put only REG_DEAD notes for pieces that are
12139 not already dead or set. */
12141 for (i = regno; i < endregno;
12142 i += hard_regno_nregs[i][reg_raw_mode[i]])
12144 rtx piece = regno_reg_rtx[i];
12145 basic_block bb = this_basic_block;
12147 if (! dead_or_set_p (place, piece)
12148 && ! reg_bitfield_target_p (piece,
12152 = gen_rtx_EXPR_LIST (REG_DEAD, piece, NULL_RTX);
12154 distribute_notes (new_note, place, place,
12157 else if (! refers_to_regno_p (i, i + 1,
12158 PATTERN (place), 0)
12159 && ! find_regno_fusage (place, USE, i))
12160 for (tem = PREV_INSN (place); ;
12161 tem = PREV_INSN (tem))
12163 if (! INSN_P (tem))
12165 if (tem == BB_HEAD (bb))
12167 SET_BIT (refresh_blocks,
12168 this_basic_block->index);
12173 if (dead_or_set_p (tem, piece)
12174 || reg_bitfield_target_p (piece,
12178 = gen_rtx_EXPR_LIST (REG_UNUSED, piece,
12193 /* Any other notes should not be present at this point in the
12200 XEXP (note, 1) = REG_NOTES (place);
12201 REG_NOTES (place) = note;
12203 else if ((REG_NOTE_KIND (note) == REG_DEAD
12204 || REG_NOTE_KIND (note) == REG_UNUSED)
12205 && REG_P (XEXP (note, 0)))
12206 REG_N_DEATHS (REGNO (XEXP (note, 0)))--;
12210 if ((REG_NOTE_KIND (note) == REG_DEAD
12211 || REG_NOTE_KIND (note) == REG_UNUSED)
12212 && REG_P (XEXP (note, 0)))
12213 REG_N_DEATHS (REGNO (XEXP (note, 0)))++;
12215 REG_NOTES (place2) = gen_rtx_fmt_ee (GET_CODE (note),
12216 REG_NOTE_KIND (note),
12218 REG_NOTES (place2));
12223 /* Similarly to above, distribute the LOG_LINKS that used to be present on
12224 I3, I2, and I1 to new locations. This is also called to add a link
12225 pointing at I3 when I3's destination is changed. */
12228 distribute_links (rtx links)
12230 rtx link, next_link;
12232 for (link = links; link; link = next_link)
12238 next_link = XEXP (link, 1);
12240 /* If the insn that this link points to is a NOTE or isn't a single
12241 set, ignore it. In the latter case, it isn't clear what we
12242 can do other than ignore the link, since we can't tell which
12243 register it was for. Such links wouldn't be used by combine
12246 It is not possible for the destination of the target of the link to
12247 have been changed by combine. The only potential of this is if we
12248 replace I3, I2, and I1 by I3 and I2. But in that case the
12249 destination of I2 also remains unchanged. */
12251 if (NOTE_P (XEXP (link, 0))
12252 || (set = single_set (XEXP (link, 0))) == 0)
12255 reg = SET_DEST (set);
12256 while (GET_CODE (reg) == SUBREG || GET_CODE (reg) == ZERO_EXTRACT
12257 || GET_CODE (reg) == SIGN_EXTRACT
12258 || GET_CODE (reg) == STRICT_LOW_PART)
12259 reg = XEXP (reg, 0);
12261 /* A LOG_LINK is defined as being placed on the first insn that uses
12262 a register and points to the insn that sets the register. Start
12263 searching at the next insn after the target of the link and stop
12264 when we reach a set of the register or the end of the basic block.
12266 Note that this correctly handles the link that used to point from
12267 I3 to I2. Also note that not much searching is typically done here
12268 since most links don't point very far away. */
12270 for (insn = NEXT_INSN (XEXP (link, 0));
12271 (insn && (this_basic_block->next_bb == EXIT_BLOCK_PTR
12272 || BB_HEAD (this_basic_block->next_bb) != insn));
12273 insn = NEXT_INSN (insn))
12274 if (INSN_P (insn) && reg_overlap_mentioned_p (reg, PATTERN (insn)))
12276 if (reg_referenced_p (reg, PATTERN (insn)))
12280 else if (CALL_P (insn)
12281 && find_reg_fusage (insn, USE, reg))
12286 else if (INSN_P (insn) && reg_set_p (reg, insn))
12289 /* If we found a place to put the link, place it there unless there
12290 is already a link to the same insn as LINK at that point. */
12296 for (link2 = LOG_LINKS (place); link2; link2 = XEXP (link2, 1))
12297 if (XEXP (link2, 0) == XEXP (link, 0))
12302 XEXP (link, 1) = LOG_LINKS (place);
12303 LOG_LINKS (place) = link;
12305 /* Set added_links_insn to the earliest insn we added a
12307 if (added_links_insn == 0
12308 || INSN_CUID (added_links_insn) > INSN_CUID (place))
12309 added_links_insn = place;
12315 /* Subroutine of unmentioned_reg_p and callback from for_each_rtx.
12316 Check whether the expression pointer to by LOC is a register or
12317 memory, and if so return 1 if it isn't mentioned in the rtx EXPR.
12318 Otherwise return zero. */
12321 unmentioned_reg_p_1 (rtx *loc, void *expr)
12326 && (REG_P (x) || MEM_P (x))
12327 && ! reg_mentioned_p (x, (rtx) expr))
12332 /* Check for any register or memory mentioned in EQUIV that is not
12333 mentioned in EXPR. This is used to restrict EQUIV to "specializations"
12334 of EXPR where some registers may have been replaced by constants. */
12337 unmentioned_reg_p (rtx equiv, rtx expr)
12339 return for_each_rtx (&equiv, unmentioned_reg_p_1, expr);
12342 /* Compute INSN_CUID for INSN, which is an insn made by combine. */
12345 insn_cuid (rtx insn)
12347 while (insn != 0 && INSN_UID (insn) > max_uid_cuid
12348 && NONJUMP_INSN_P (insn) && GET_CODE (PATTERN (insn)) == USE)
12349 insn = NEXT_INSN (insn);
12351 if (INSN_UID (insn) > max_uid_cuid)
12354 return INSN_CUID (insn);
12358 dump_combine_stats (FILE *file)
12362 ";; Combiner statistics: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n\n",
12363 combine_attempts, combine_merges, combine_extras, combine_successes);
12367 dump_combine_total_stats (FILE *file)
12371 "\n;; Combiner totals: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n",
12372 total_attempts, total_merges, total_extras, total_successes);