1 /* Optimize by combining instructions for GNU compiler.
2 Copyright (C) 1987, 88, 92-96, 1997 Free Software Foundation, Inc.
4 This file is part of GNU CC.
6 GNU CC is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2, or (at your option)
11 GNU CC is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GNU CC; see the file COPYING. If not, write to
18 the Free Software Foundation, 59 Temple Place - Suite 330,
19 Boston, MA 02111-1307, USA. */
22 /* This module is essentially the "combiner" phase of the U. of Arizona
23 Portable Optimizer, but redone to work on our list-structured
24 representation for RTL instead of their string representation.
26 The LOG_LINKS of each insn identify the most recent assignment
27 to each REG used in the insn. It is a list of previous insns,
28 each of which contains a SET for a REG that is used in this insn
29 and not used or set in between. LOG_LINKs never cross basic blocks.
30 They were set up by the preceding pass (lifetime analysis).
32 We try to combine each pair of insns joined by a logical link.
33 We also try to combine triples of insns A, B and C when
34 C has a link back to B and B has a link back to A.
36 LOG_LINKS does not have links for use of the CC0. They don't
37 need to, because the insn that sets the CC0 is always immediately
38 before the insn that tests it. So we always regard a branch
39 insn as having a logical link to the preceding insn. The same is true
40 for an insn explicitly using CC0.
42 We check (with use_crosses_set_p) to avoid combining in such a way
43 as to move a computation to a place where its value would be different.
45 Combination is done by mathematically substituting the previous
46 insn(s) values for the regs they set into the expressions in
47 the later insns that refer to these regs. If the result is a valid insn
48 for our target machine, according to the machine description,
49 we install it, delete the earlier insns, and update the data flow
50 information (LOG_LINKS and REG_NOTES) for what we did.
52 There are a few exceptions where the dataflow information created by
53 flow.c aren't completely updated:
55 - reg_live_length is not updated
56 - reg_n_refs is not adjusted in the rare case when a register is
57 no longer required in a computation
58 - there are extremely rare cases (see distribute_regnotes) when a
60 - a LOG_LINKS entry that refers to an insn with multiple SETs may be
61 removed because there is no way to know which register it was
64 To simplify substitution, we combine only when the earlier insn(s)
65 consist of only a single assignment. To simplify updating afterward,
66 we never combine when a subroutine call appears in the middle.
68 Since we do not represent assignments to CC0 explicitly except when that
69 is all an insn does, there is no LOG_LINKS entry in an insn that uses
70 the condition code for the insn that set the condition code.
71 Fortunately, these two insns must be consecutive.
72 Therefore, every JUMP_INSN is taken to have an implicit logical link
73 to the preceding insn. This is not quite right, since non-jumps can
74 also use the condition code; but in practice such insns would not
84 /* Must precede rtl.h for FFS. */
90 #include "hard-reg-set.h"
92 #include "basic-block.h"
93 #include "insn-config.h"
94 #include "insn-flags.h"
95 #include "insn-codes.h"
96 #include "insn-attr.h"
100 /* It is not safe to use ordinary gen_lowpart in combine.
101 Use gen_lowpart_for_combine instead. See comments there. */
102 #define gen_lowpart dont_use_gen_lowpart_you_dummy
104 /* Number of attempts to combine instructions in this function. */
106 static int combine_attempts;
108 /* Number of attempts that got as far as substitution in this function. */
110 static int combine_merges;
112 /* Number of instructions combined with added SETs in this function. */
114 static int combine_extras;
116 /* Number of instructions combined in this function. */
118 static int combine_successes;
120 /* Totals over entire compilation. */
122 static int total_attempts, total_merges, total_extras, total_successes;
124 /* Define a default value for REVERSIBLE_CC_MODE.
125 We can never assume that a condition code mode is safe to reverse unless
126 the md tells us so. */
127 #ifndef REVERSIBLE_CC_MODE
128 #define REVERSIBLE_CC_MODE(MODE) 0
131 /* Vector mapping INSN_UIDs to cuids.
132 The cuids are like uids but increase monotonically always.
133 Combine always uses cuids so that it can compare them.
134 But actually renumbering the uids, which we used to do,
135 proves to be a bad idea because it makes it hard to compare
136 the dumps produced by earlier passes with those from later passes. */
138 static int *uid_cuid;
139 static int max_uid_cuid;
141 /* Get the cuid of an insn. */
143 #define INSN_CUID(INSN) \
144 (INSN_UID (INSN) > max_uid_cuid ? insn_cuid (INSN) : uid_cuid[INSN_UID (INSN)])
146 /* Maximum register number, which is the size of the tables below. */
148 static int combine_max_regno;
150 /* Record last point of death of (hard or pseudo) register n. */
152 static rtx *reg_last_death;
154 /* Record last point of modification of (hard or pseudo) register n. */
156 static rtx *reg_last_set;
158 /* Record the cuid of the last insn that invalidated memory
159 (anything that writes memory, and subroutine calls, but not pushes). */
161 static int mem_last_set;
163 /* Record the cuid of the last CALL_INSN
164 so we can tell whether a potential combination crosses any calls. */
166 static int last_call_cuid;
168 /* When `subst' is called, this is the insn that is being modified
169 (by combining in a previous insn). The PATTERN of this insn
170 is still the old pattern partially modified and it should not be
171 looked at, but this may be used to examine the successors of the insn
172 to judge whether a simplification is valid. */
174 static rtx subst_insn;
176 /* This is an insn that belongs before subst_insn, but is not currently
177 on the insn chain. */
179 static rtx subst_prev_insn;
181 /* This is the lowest CUID that `subst' is currently dealing with.
182 get_last_value will not return a value if the register was set at or
183 after this CUID. If not for this mechanism, we could get confused if
184 I2 or I1 in try_combine were an insn that used the old value of a register
185 to obtain a new value. In that case, we might erroneously get the
186 new value of the register when we wanted the old one. */
188 static int subst_low_cuid;
190 /* This contains any hard registers that are used in newpat; reg_dead_at_p
191 must consider all these registers to be always live. */
193 static HARD_REG_SET newpat_used_regs;
195 /* This is an insn to which a LOG_LINKS entry has been added. If this
196 insn is the earlier than I2 or I3, combine should rescan starting at
199 static rtx added_links_insn;
201 /* Basic block number of the block in which we are performing combines. */
202 static int this_basic_block;
204 /* The next group of arrays allows the recording of the last value assigned
205 to (hard or pseudo) register n. We use this information to see if a
206 operation being processed is redundant given a prior operation performed
207 on the register. For example, an `and' with a constant is redundant if
208 all the zero bits are already known to be turned off.
210 We use an approach similar to that used by cse, but change it in the
213 (1) We do not want to reinitialize at each label.
214 (2) It is useful, but not critical, to know the actual value assigned
215 to a register. Often just its form is helpful.
217 Therefore, we maintain the following arrays:
219 reg_last_set_value the last value assigned
220 reg_last_set_label records the value of label_tick when the
221 register was assigned
222 reg_last_set_table_tick records the value of label_tick when a
223 value using the register is assigned
224 reg_last_set_invalid set to non-zero when it is not valid
225 to use the value of this register in some
228 To understand the usage of these tables, it is important to understand
229 the distinction between the value in reg_last_set_value being valid
230 and the register being validly contained in some other expression in the
233 Entry I in reg_last_set_value is valid if it is non-zero, and either
234 reg_n_sets[i] is 1 or reg_last_set_label[i] == label_tick.
236 Register I may validly appear in any expression returned for the value
237 of another register if reg_n_sets[i] is 1. It may also appear in the
238 value for register J if reg_last_set_label[i] < reg_last_set_label[j] or
239 reg_last_set_invalid[j] is zero.
241 If an expression is found in the table containing a register which may
242 not validly appear in an expression, the register is replaced by
243 something that won't match, (clobber (const_int 0)).
245 reg_last_set_invalid[i] is set non-zero when register I is being assigned
246 to and reg_last_set_table_tick[i] == label_tick. */
248 /* Record last value assigned to (hard or pseudo) register n. */
250 static rtx *reg_last_set_value;
252 /* Record the value of label_tick when the value for register n is placed in
253 reg_last_set_value[n]. */
255 static int *reg_last_set_label;
257 /* Record the value of label_tick when an expression involving register n
258 is placed in reg_last_set_value. */
260 static int *reg_last_set_table_tick;
262 /* Set non-zero if references to register n in expressions should not be
265 static char *reg_last_set_invalid;
267 /* Incremented for each label. */
269 static int label_tick;
271 /* Some registers that are set more than once and used in more than one
272 basic block are nevertheless always set in similar ways. For example,
273 a QImode register may be loaded from memory in two places on a machine
274 where byte loads zero extend.
276 We record in the following array what we know about the nonzero
277 bits of a register, specifically which bits are known to be zero.
279 If an entry is zero, it means that we don't know anything special. */
281 static unsigned HOST_WIDE_INT *reg_nonzero_bits;
283 /* Mode used to compute significance in reg_nonzero_bits. It is the largest
284 integer mode that can fit in HOST_BITS_PER_WIDE_INT. */
286 static enum machine_mode nonzero_bits_mode;
288 /* Nonzero if we know that a register has some leading bits that are always
289 equal to the sign bit. */
291 static char *reg_sign_bit_copies;
293 /* Nonzero when reg_nonzero_bits and reg_sign_bit_copies can be safely used.
294 It is zero while computing them and after combine has completed. This
295 former test prevents propagating values based on previously set values,
296 which can be incorrect if a variable is modified in a loop. */
298 static int nonzero_sign_valid;
300 /* These arrays are maintained in parallel with reg_last_set_value
301 and are used to store the mode in which the register was last set,
302 the bits that were known to be zero when it was last set, and the
303 number of sign bits copies it was known to have when it was last set. */
305 static enum machine_mode *reg_last_set_mode;
306 static unsigned HOST_WIDE_INT *reg_last_set_nonzero_bits;
307 static char *reg_last_set_sign_bit_copies;
309 /* Record one modification to rtl structure
310 to be undone by storing old_contents into *where.
311 is_int is 1 if the contents are an int. */
317 union {rtx r; int i;} old_contents;
318 union {rtx *r; int *i;} where;
321 /* Record a bunch of changes to be undone, up to MAX_UNDO of them.
322 num_undo says how many are currently recorded.
324 storage is nonzero if we must undo the allocation of new storage.
325 The value of storage is what to pass to obfree.
327 other_insn is nonzero if we have modified some other insn in the process
328 of working on subst_insn. It must be verified too.
330 previous_undos is the value of undobuf.undos when we started processing
331 this substitution. This will prevent gen_rtx_combine from re-used a piece
332 from the previous expression. Doing so can produce circular rtl
340 struct undo *previous_undos;
344 static struct undobuf undobuf;
346 /* Substitute NEWVAL, an rtx expression, into INTO, a place in some
347 insn. The substitution can be undone by undo_all. If INTO is already
348 set to NEWVAL, do not record this change. Because computing NEWVAL might
349 also call SUBST, we have to compute it before we put anything into
352 #define SUBST(INTO, NEWVAL) \
353 do { rtx _new = (NEWVAL); \
357 _buf = undobuf.frees, undobuf.frees = _buf->next; \
359 _buf = (struct undo *) xmalloc (sizeof (struct undo)); \
362 _buf->where.r = &INTO; \
363 _buf->old_contents.r = INTO; \
365 if (_buf->old_contents.r == INTO) \
366 _buf->next = undobuf.frees, undobuf.frees = _buf; \
368 _buf->next = undobuf.undos, undobuf.undos = _buf; \
371 /* Similar to SUBST, but NEWVAL is an int expression. Note that substitution
372 for the value of a HOST_WIDE_INT value (including CONST_INT) is
375 #define SUBST_INT(INTO, NEWVAL) \
376 do { struct undo *_buf; \
379 _buf = undobuf.frees, undobuf.frees = _buf->next; \
381 _buf = (struct undo *) xmalloc (sizeof (struct undo)); \
384 _buf->where.i = (int *) &INTO; \
385 _buf->old_contents.i = INTO; \
387 if (_buf->old_contents.i == INTO) \
388 _buf->next = undobuf.frees, undobuf.frees = _buf; \
390 _buf->next = undobuf.undos, undobuf.undos = _buf; \
393 /* Number of times the pseudo being substituted for
394 was found and replaced. */
396 static int n_occurrences;
398 static void init_reg_last_arrays PROTO((void));
399 static void setup_incoming_promotions PROTO((void));
400 static void set_nonzero_bits_and_sign_copies PROTO((rtx, rtx));
401 static int can_combine_p PROTO((rtx, rtx, rtx, rtx, rtx *, rtx *));
402 static int combinable_i3pat PROTO((rtx, rtx *, rtx, rtx, int, rtx *));
403 static rtx try_combine PROTO((rtx, rtx, rtx));
404 static void undo_all PROTO((void));
405 static rtx *find_split_point PROTO((rtx *, rtx));
406 static rtx subst PROTO((rtx, rtx, rtx, int, int));
407 static rtx simplify_rtx PROTO((rtx, enum machine_mode, int, int));
408 static rtx simplify_if_then_else PROTO((rtx));
409 static rtx simplify_set PROTO((rtx));
410 static rtx simplify_logical PROTO((rtx, int));
411 static rtx expand_compound_operation PROTO((rtx));
412 static rtx expand_field_assignment PROTO((rtx));
413 static rtx make_extraction PROTO((enum machine_mode, rtx, int, rtx, int,
415 static rtx extract_left_shift PROTO((rtx, int));
416 static rtx make_compound_operation PROTO((rtx, enum rtx_code));
417 static int get_pos_from_mask PROTO((unsigned HOST_WIDE_INT, int *));
418 static rtx force_to_mode PROTO((rtx, enum machine_mode,
419 unsigned HOST_WIDE_INT, rtx, int));
420 static rtx if_then_else_cond PROTO((rtx, rtx *, rtx *));
421 static rtx known_cond PROTO((rtx, enum rtx_code, rtx, rtx));
422 static int rtx_equal_for_field_assignment_p PROTO((rtx, rtx));
423 static rtx make_field_assignment PROTO((rtx));
424 static rtx apply_distributive_law PROTO((rtx));
425 static rtx simplify_and_const_int PROTO((rtx, enum machine_mode, rtx,
426 unsigned HOST_WIDE_INT));
427 static unsigned HOST_WIDE_INT nonzero_bits PROTO((rtx, enum machine_mode));
428 static int num_sign_bit_copies PROTO((rtx, enum machine_mode));
429 static int merge_outer_ops PROTO((enum rtx_code *, HOST_WIDE_INT *,
430 enum rtx_code, HOST_WIDE_INT,
431 enum machine_mode, int *));
432 static rtx simplify_shift_const PROTO((rtx, enum rtx_code, enum machine_mode,
434 static int recog_for_combine PROTO((rtx *, rtx, rtx *, int *));
435 static rtx gen_lowpart_for_combine PROTO((enum machine_mode, rtx));
436 static rtx gen_rtx_combine PVPROTO((enum rtx_code code, enum machine_mode mode,
438 static rtx gen_binary PROTO((enum rtx_code, enum machine_mode,
440 static rtx gen_unary PROTO((enum rtx_code, enum machine_mode,
441 enum machine_mode, rtx));
442 static enum rtx_code simplify_comparison PROTO((enum rtx_code, rtx *, rtx *));
443 static int reversible_comparison_p PROTO((rtx));
444 static void update_table_tick PROTO((rtx));
445 static void record_value_for_reg PROTO((rtx, rtx, rtx));
446 static void record_dead_and_set_regs_1 PROTO((rtx, rtx));
447 static void record_dead_and_set_regs PROTO((rtx));
448 static int get_last_value_validate PROTO((rtx *, rtx, int, int));
449 static rtx get_last_value PROTO((rtx));
450 static int use_crosses_set_p PROTO((rtx, int));
451 static void reg_dead_at_p_1 PROTO((rtx, rtx));
452 static int reg_dead_at_p PROTO((rtx, rtx));
453 static void move_deaths PROTO((rtx, rtx, int, rtx, rtx *));
454 static int reg_bitfield_target_p PROTO((rtx, rtx));
455 static void distribute_notes PROTO((rtx, rtx, rtx, rtx, rtx, rtx));
456 static void distribute_links PROTO((rtx));
457 static void mark_used_regs_combine PROTO((rtx));
458 static int insn_cuid PROTO((rtx));
460 /* Main entry point for combiner. F is the first insn of the function.
461 NREGS is the first unused pseudo-reg number. */
464 combine_instructions (f, nregs)
468 register rtx insn, next, prev;
470 register rtx links, nextlinks;
472 combine_attempts = 0;
475 combine_successes = 0;
476 undobuf.undos = undobuf.previous_undos = 0;
478 combine_max_regno = nregs;
481 = (unsigned HOST_WIDE_INT *) alloca (nregs * sizeof (HOST_WIDE_INT));
482 reg_sign_bit_copies = (char *) alloca (nregs * sizeof (char));
484 bzero ((char *) reg_nonzero_bits, nregs * sizeof (HOST_WIDE_INT));
485 bzero (reg_sign_bit_copies, nregs * sizeof (char));
487 reg_last_death = (rtx *) alloca (nregs * sizeof (rtx));
488 reg_last_set = (rtx *) alloca (nregs * sizeof (rtx));
489 reg_last_set_value = (rtx *) alloca (nregs * sizeof (rtx));
490 reg_last_set_table_tick = (int *) alloca (nregs * sizeof (int));
491 reg_last_set_label = (int *) alloca (nregs * sizeof (int));
492 reg_last_set_invalid = (char *) alloca (nregs * sizeof (char));
494 = (enum machine_mode *) alloca (nregs * sizeof (enum machine_mode));
495 reg_last_set_nonzero_bits
496 = (unsigned HOST_WIDE_INT *) alloca (nregs * sizeof (HOST_WIDE_INT));
497 reg_last_set_sign_bit_copies
498 = (char *) alloca (nregs * sizeof (char));
500 init_reg_last_arrays ();
502 init_recog_no_volatile ();
504 /* Compute maximum uid value so uid_cuid can be allocated. */
506 for (insn = f, i = 0; insn; insn = NEXT_INSN (insn))
507 if (INSN_UID (insn) > i)
510 uid_cuid = (int *) alloca ((i + 1) * sizeof (int));
513 nonzero_bits_mode = mode_for_size (HOST_BITS_PER_WIDE_INT, MODE_INT, 0);
515 /* Don't use reg_nonzero_bits when computing it. This can cause problems
516 when, for example, we have j <<= 1 in a loop. */
518 nonzero_sign_valid = 0;
520 /* Compute the mapping from uids to cuids.
521 Cuids are numbers assigned to insns, like uids,
522 except that cuids increase monotonically through the code.
524 Scan all SETs and see if we can deduce anything about what
525 bits are known to be zero for some registers and how many copies
526 of the sign bit are known to exist for those registers.
528 Also set any known values so that we can use it while searching
529 for what bits are known to be set. */
533 /* We need to initialize it here, because record_dead_and_set_regs may call
535 subst_prev_insn = NULL_RTX;
537 setup_incoming_promotions ();
539 for (insn = f, i = 0; insn; insn = NEXT_INSN (insn))
541 uid_cuid[INSN_UID (insn)] = ++i;
545 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i')
547 note_stores (PATTERN (insn), set_nonzero_bits_and_sign_copies);
548 record_dead_and_set_regs (insn);
551 for (links = REG_NOTES (insn); links; links = XEXP (links, 1))
552 if (REG_NOTE_KIND (links) == REG_INC)
553 set_nonzero_bits_and_sign_copies (XEXP (links, 0), NULL_RTX);
557 if (GET_CODE (insn) == CODE_LABEL)
561 nonzero_sign_valid = 1;
563 /* Now scan all the insns in forward order. */
565 this_basic_block = -1;
569 init_reg_last_arrays ();
570 setup_incoming_promotions ();
572 for (insn = f; insn; insn = next ? next : NEXT_INSN (insn))
576 /* If INSN starts a new basic block, update our basic block number. */
577 if (this_basic_block + 1 < n_basic_blocks
578 && basic_block_head[this_basic_block + 1] == insn)
581 if (GET_CODE (insn) == CODE_LABEL)
584 else if (GET_RTX_CLASS (GET_CODE (insn)) == 'i')
586 /* Try this insn with each insn it links back to. */
588 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
589 if ((next = try_combine (insn, XEXP (links, 0), NULL_RTX)) != 0)
592 /* Try each sequence of three linked insns ending with this one. */
594 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
595 for (nextlinks = LOG_LINKS (XEXP (links, 0)); nextlinks;
596 nextlinks = XEXP (nextlinks, 1))
597 if ((next = try_combine (insn, XEXP (links, 0),
598 XEXP (nextlinks, 0))) != 0)
602 /* Try to combine a jump insn that uses CC0
603 with a preceding insn that sets CC0, and maybe with its
604 logical predecessor as well.
605 This is how we make decrement-and-branch insns.
606 We need this special code because data flow connections
607 via CC0 do not get entered in LOG_LINKS. */
609 if (GET_CODE (insn) == JUMP_INSN
610 && (prev = prev_nonnote_insn (insn)) != 0
611 && GET_CODE (prev) == INSN
612 && sets_cc0_p (PATTERN (prev)))
614 if ((next = try_combine (insn, prev, NULL_RTX)) != 0)
617 for (nextlinks = LOG_LINKS (prev); nextlinks;
618 nextlinks = XEXP (nextlinks, 1))
619 if ((next = try_combine (insn, prev,
620 XEXP (nextlinks, 0))) != 0)
624 /* Do the same for an insn that explicitly references CC0. */
625 if (GET_CODE (insn) == INSN
626 && (prev = prev_nonnote_insn (insn)) != 0
627 && GET_CODE (prev) == INSN
628 && sets_cc0_p (PATTERN (prev))
629 && GET_CODE (PATTERN (insn)) == SET
630 && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (insn))))
632 if ((next = try_combine (insn, prev, NULL_RTX)) != 0)
635 for (nextlinks = LOG_LINKS (prev); nextlinks;
636 nextlinks = XEXP (nextlinks, 1))
637 if ((next = try_combine (insn, prev,
638 XEXP (nextlinks, 0))) != 0)
642 /* Finally, see if any of the insns that this insn links to
643 explicitly references CC0. If so, try this insn, that insn,
644 and its predecessor if it sets CC0. */
645 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
646 if (GET_CODE (XEXP (links, 0)) == INSN
647 && GET_CODE (PATTERN (XEXP (links, 0))) == SET
648 && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (XEXP (links, 0))))
649 && (prev = prev_nonnote_insn (XEXP (links, 0))) != 0
650 && GET_CODE (prev) == INSN
651 && sets_cc0_p (PATTERN (prev))
652 && (next = try_combine (insn, XEXP (links, 0), prev)) != 0)
656 /* Try combining an insn with two different insns whose results it
658 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
659 for (nextlinks = XEXP (links, 1); nextlinks;
660 nextlinks = XEXP (nextlinks, 1))
661 if ((next = try_combine (insn, XEXP (links, 0),
662 XEXP (nextlinks, 0))) != 0)
665 if (GET_CODE (insn) != NOTE)
666 record_dead_and_set_regs (insn);
673 total_attempts += combine_attempts;
674 total_merges += combine_merges;
675 total_extras += combine_extras;
676 total_successes += combine_successes;
678 nonzero_sign_valid = 0;
681 /* Wipe the reg_last_xxx arrays in preparation for another pass. */
684 init_reg_last_arrays ()
686 int nregs = combine_max_regno;
688 bzero ((char *) reg_last_death, nregs * sizeof (rtx));
689 bzero ((char *) reg_last_set, nregs * sizeof (rtx));
690 bzero ((char *) reg_last_set_value, nregs * sizeof (rtx));
691 bzero ((char *) reg_last_set_table_tick, nregs * sizeof (int));
692 bzero ((char *) reg_last_set_label, nregs * sizeof (int));
693 bzero (reg_last_set_invalid, nregs * sizeof (char));
694 bzero ((char *) reg_last_set_mode, nregs * sizeof (enum machine_mode));
695 bzero ((char *) reg_last_set_nonzero_bits, nregs * sizeof (HOST_WIDE_INT));
696 bzero (reg_last_set_sign_bit_copies, nregs * sizeof (char));
699 /* Set up any promoted values for incoming argument registers. */
702 setup_incoming_promotions ()
704 #ifdef PROMOTE_FUNCTION_ARGS
707 enum machine_mode mode;
709 rtx first = get_insns ();
711 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
712 if (FUNCTION_ARG_REGNO_P (regno)
713 && (reg = promoted_input_arg (regno, &mode, &unsignedp)) != 0)
714 record_value_for_reg (reg, first,
715 gen_rtx (unsignedp ? ZERO_EXTEND : SIGN_EXTEND,
717 gen_rtx (CLOBBER, mode, const0_rtx)));
721 /* Called via note_stores. If X is a pseudo that is narrower than
722 HOST_BITS_PER_WIDE_INT and is being set, record what bits are known zero.
724 If we are setting only a portion of X and we can't figure out what
725 portion, assume all bits will be used since we don't know what will
728 Similarly, set how many bits of X are known to be copies of the sign bit
729 at all locations in the function. This is the smallest number implied
733 set_nonzero_bits_and_sign_copies (x, set)
739 if (GET_CODE (x) == REG
740 && REGNO (x) >= FIRST_PSEUDO_REGISTER
741 /* If this register is undefined at the start of the file, we can't
742 say what its contents were. */
743 && ! REGNO_REG_SET_P (basic_block_live_at_start[0], REGNO (x))
744 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT)
746 if (set == 0 || GET_CODE (set) == CLOBBER)
748 reg_nonzero_bits[REGNO (x)] = GET_MODE_MASK (GET_MODE (x));
749 reg_sign_bit_copies[REGNO (x)] = 1;
753 /* If this is a complex assignment, see if we can convert it into a
754 simple assignment. */
755 set = expand_field_assignment (set);
757 /* If this is a simple assignment, or we have a paradoxical SUBREG,
758 set what we know about X. */
760 if (SET_DEST (set) == x
761 || (GET_CODE (SET_DEST (set)) == SUBREG
762 && (GET_MODE_SIZE (GET_MODE (SET_DEST (set)))
763 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (set)))))
764 && SUBREG_REG (SET_DEST (set)) == x))
766 rtx src = SET_SRC (set);
768 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
769 /* If X is narrower than a word and SRC is a non-negative
770 constant that would appear negative in the mode of X,
771 sign-extend it for use in reg_nonzero_bits because some
772 machines (maybe most) will actually do the sign-extension
773 and this is the conservative approach.
775 ??? For 2.5, try to tighten up the MD files in this regard
776 instead of this kludge. */
778 if (GET_MODE_BITSIZE (GET_MODE (x)) < BITS_PER_WORD
779 && GET_CODE (src) == CONST_INT
781 && 0 != (INTVAL (src)
783 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
784 src = GEN_INT (INTVAL (src)
785 | ((HOST_WIDE_INT) (-1)
786 << GET_MODE_BITSIZE (GET_MODE (x))));
789 reg_nonzero_bits[REGNO (x)]
790 |= nonzero_bits (src, nonzero_bits_mode);
791 num = num_sign_bit_copies (SET_SRC (set), GET_MODE (x));
792 if (reg_sign_bit_copies[REGNO (x)] == 0
793 || reg_sign_bit_copies[REGNO (x)] > num)
794 reg_sign_bit_copies[REGNO (x)] = num;
798 reg_nonzero_bits[REGNO (x)] = GET_MODE_MASK (GET_MODE (x));
799 reg_sign_bit_copies[REGNO (x)] = 1;
804 /* See if INSN can be combined into I3. PRED and SUCC are optionally
805 insns that were previously combined into I3 or that will be combined
806 into the merger of INSN and I3.
808 Return 0 if the combination is not allowed for any reason.
810 If the combination is allowed, *PDEST will be set to the single
811 destination of INSN and *PSRC to the single source, and this function
815 can_combine_p (insn, i3, pred, succ, pdest, psrc)
822 rtx set = 0, src, dest;
824 int all_adjacent = (succ ? (next_active_insn (insn) == succ
825 && next_active_insn (succ) == i3)
826 : next_active_insn (insn) == i3);
828 /* Can combine only if previous insn is a SET of a REG, a SUBREG or CC0.
829 or a PARALLEL consisting of such a SET and CLOBBERs.
831 If INSN has CLOBBER parallel parts, ignore them for our processing.
832 By definition, these happen during the execution of the insn. When it
833 is merged with another insn, all bets are off. If they are, in fact,
834 needed and aren't also supplied in I3, they may be added by
835 recog_for_combine. Otherwise, it won't match.
837 We can also ignore a SET whose SET_DEST is mentioned in a REG_UNUSED
840 Get the source and destination of INSN. If more than one, can't
843 if (GET_CODE (PATTERN (insn)) == SET)
844 set = PATTERN (insn);
845 else if (GET_CODE (PATTERN (insn)) == PARALLEL
846 && GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == SET)
848 for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
850 rtx elt = XVECEXP (PATTERN (insn), 0, i);
852 switch (GET_CODE (elt))
854 /* We can ignore CLOBBERs. */
859 /* Ignore SETs whose result isn't used but not those that
860 have side-effects. */
861 if (find_reg_note (insn, REG_UNUSED, SET_DEST (elt))
862 && ! side_effects_p (elt))
865 /* If we have already found a SET, this is a second one and
866 so we cannot combine with this insn. */
874 /* Anything else means we can't combine. */
880 /* If SET_SRC is an ASM_OPERANDS we can't throw away these CLOBBERs,
881 so don't do anything with it. */
882 || GET_CODE (SET_SRC (set)) == ASM_OPERANDS)
891 set = expand_field_assignment (set);
892 src = SET_SRC (set), dest = SET_DEST (set);
894 /* Don't eliminate a store in the stack pointer. */
895 if (dest == stack_pointer_rtx
896 /* If we couldn't eliminate a field assignment, we can't combine. */
897 || GET_CODE (dest) == ZERO_EXTRACT || GET_CODE (dest) == STRICT_LOW_PART
898 /* Don't combine with an insn that sets a register to itself if it has
899 a REG_EQUAL note. This may be part of a REG_NO_CONFLICT sequence. */
900 || (rtx_equal_p (src, dest) && find_reg_note (insn, REG_EQUAL, NULL_RTX))
901 /* Can't merge a function call. */
902 || GET_CODE (src) == CALL
903 /* Don't eliminate a function call argument. */
904 || (GET_CODE (i3) == CALL_INSN
905 && (find_reg_fusage (i3, USE, dest)
906 || (GET_CODE (dest) == REG
907 && REGNO (dest) < FIRST_PSEUDO_REGISTER
908 && global_regs[REGNO (dest)])))
909 /* Don't substitute into an incremented register. */
910 || FIND_REG_INC_NOTE (i3, dest)
911 || (succ && FIND_REG_INC_NOTE (succ, dest))
912 /* Don't combine the end of a libcall into anything. */
913 || find_reg_note (insn, REG_RETVAL, NULL_RTX)
914 /* Make sure that DEST is not used after SUCC but before I3. */
915 || (succ && ! all_adjacent
916 && reg_used_between_p (dest, succ, i3))
917 /* Make sure that the value that is to be substituted for the register
918 does not use any registers whose values alter in between. However,
919 If the insns are adjacent, a use can't cross a set even though we
920 think it might (this can happen for a sequence of insns each setting
921 the same destination; reg_last_set of that register might point to
922 a NOTE). If INSN has a REG_EQUIV note, the register is always
923 equivalent to the memory so the substitution is valid even if there
924 are intervening stores. Also, don't move a volatile asm or
925 UNSPEC_VOLATILE across any other insns. */
927 && (((GET_CODE (src) != MEM
928 || ! find_reg_note (insn, REG_EQUIV, src))
929 && use_crosses_set_p (src, INSN_CUID (insn)))
930 || (GET_CODE (src) == ASM_OPERANDS && MEM_VOLATILE_P (src))
931 || GET_CODE (src) == UNSPEC_VOLATILE))
932 /* If there is a REG_NO_CONFLICT note for DEST in I3 or SUCC, we get
933 better register allocation by not doing the combine. */
934 || find_reg_note (i3, REG_NO_CONFLICT, dest)
935 || (succ && find_reg_note (succ, REG_NO_CONFLICT, dest))
936 /* Don't combine across a CALL_INSN, because that would possibly
937 change whether the life span of some REGs crosses calls or not,
938 and it is a pain to update that information.
939 Exception: if source is a constant, moving it later can't hurt.
940 Accept that special case, because it helps -fforce-addr a lot. */
941 || (INSN_CUID (insn) < last_call_cuid && ! CONSTANT_P (src)))
944 /* DEST must either be a REG or CC0. */
945 if (GET_CODE (dest) == REG)
947 /* If register alignment is being enforced for multi-word items in all
948 cases except for parameters, it is possible to have a register copy
949 insn referencing a hard register that is not allowed to contain the
950 mode being copied and which would not be valid as an operand of most
951 insns. Eliminate this problem by not combining with such an insn.
953 Also, on some machines we don't want to extend the life of a hard
956 This is the same test done in can_combine except that we don't test
957 if SRC is a CALL operation to permit a hard register with
958 SMALL_REGISTER_CLASSES, and that we have to take all_adjacent
961 if (GET_CODE (src) == REG
962 && ((REGNO (dest) < FIRST_PSEUDO_REGISTER
963 && ! HARD_REGNO_MODE_OK (REGNO (dest), GET_MODE (dest)))
964 /* Don't extend the life of a hard register unless it is
965 user variable (if we have few registers) or it can't
966 fit into the desired register (meaning something special
968 Also avoid substituting a return register into I3, because
969 reload can't handle a conflict with constraints of other
971 || (REGNO (src) < FIRST_PSEUDO_REGISTER
972 && (! HARD_REGNO_MODE_OK (REGNO (src), GET_MODE (src))
973 #ifdef SMALL_REGISTER_CLASSES
974 || (SMALL_REGISTER_CLASSES
975 && ((! all_adjacent && ! REG_USERVAR_P (src))
976 || (FUNCTION_VALUE_REGNO_P (REGNO (src))
977 && ! REG_USERVAR_P (src))))
982 else if (GET_CODE (dest) != CC0)
985 /* Don't substitute for a register intended as a clobberable operand.
986 Similarly, don't substitute an expression containing a register that
987 will be clobbered in I3. */
988 if (GET_CODE (PATTERN (i3)) == PARALLEL)
989 for (i = XVECLEN (PATTERN (i3), 0) - 1; i >= 0; i--)
990 if (GET_CODE (XVECEXP (PATTERN (i3), 0, i)) == CLOBBER
991 && (reg_overlap_mentioned_p (XEXP (XVECEXP (PATTERN (i3), 0, i), 0),
993 || rtx_equal_p (XEXP (XVECEXP (PATTERN (i3), 0, i), 0), dest)))
996 /* If INSN contains anything volatile, or is an `asm' (whether volatile
997 or not), reject, unless nothing volatile comes between it and I3,
998 with the exception of SUCC. */
1000 if (GET_CODE (src) == ASM_OPERANDS || volatile_refs_p (src))
1001 for (p = NEXT_INSN (insn); p != i3; p = NEXT_INSN (p))
1002 if (GET_RTX_CLASS (GET_CODE (p)) == 'i'
1003 && p != succ && volatile_refs_p (PATTERN (p)))
1006 /* If there are any volatile insns between INSN and I3, reject, because
1007 they might affect machine state. */
1009 for (p = NEXT_INSN (insn); p != i3; p = NEXT_INSN (p))
1010 if (GET_RTX_CLASS (GET_CODE (p)) == 'i'
1011 && p != succ && volatile_insn_p (PATTERN (p)))
1014 /* If INSN or I2 contains an autoincrement or autodecrement,
1015 make sure that register is not used between there and I3,
1016 and not already used in I3 either.
1017 Also insist that I3 not be a jump; if it were one
1018 and the incremented register were spilled, we would lose. */
1021 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
1022 if (REG_NOTE_KIND (link) == REG_INC
1023 && (GET_CODE (i3) == JUMP_INSN
1024 || reg_used_between_p (XEXP (link, 0), insn, i3)
1025 || reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i3))))
1030 /* Don't combine an insn that follows a CC0-setting insn.
1031 An insn that uses CC0 must not be separated from the one that sets it.
1032 We do, however, allow I2 to follow a CC0-setting insn if that insn
1033 is passed as I1; in that case it will be deleted also.
1034 We also allow combining in this case if all the insns are adjacent
1035 because that would leave the two CC0 insns adjacent as well.
1036 It would be more logical to test whether CC0 occurs inside I1 or I2,
1037 but that would be much slower, and this ought to be equivalent. */
1039 p = prev_nonnote_insn (insn);
1040 if (p && p != pred && GET_CODE (p) == INSN && sets_cc0_p (PATTERN (p))
1045 /* If we get here, we have passed all the tests and the combination is
1054 /* LOC is the location within I3 that contains its pattern or the component
1055 of a PARALLEL of the pattern. We validate that it is valid for combining.
1057 One problem is if I3 modifies its output, as opposed to replacing it
1058 entirely, we can't allow the output to contain I2DEST or I1DEST as doing
1059 so would produce an insn that is not equivalent to the original insns.
1063 (set (reg:DI 101) (reg:DI 100))
1064 (set (subreg:SI (reg:DI 101) 0) <foo>)
1066 This is NOT equivalent to:
1068 (parallel [(set (subreg:SI (reg:DI 100) 0) <foo>)
1069 (set (reg:DI 101) (reg:DI 100))])
1071 Not only does this modify 100 (in which case it might still be valid
1072 if 100 were dead in I2), it sets 101 to the ORIGINAL value of 100.
1074 We can also run into a problem if I2 sets a register that I1
1075 uses and I1 gets directly substituted into I3 (not via I2). In that
1076 case, we would be getting the wrong value of I2DEST into I3, so we
1077 must reject the combination. This case occurs when I2 and I1 both
1078 feed into I3, rather than when I1 feeds into I2, which feeds into I3.
1079 If I1_NOT_IN_SRC is non-zero, it means that finding I1 in the source
1080 of a SET must prevent combination from occurring.
1082 On machines where SMALL_REGISTER_CLASSES is defined, we don't combine
1083 if the destination of a SET is a hard register that isn't a user
1086 Before doing the above check, we first try to expand a field assignment
1087 into a set of logical operations.
1089 If PI3_DEST_KILLED is non-zero, it is a pointer to a location in which
1090 we place a register that is both set and used within I3. If more than one
1091 such register is detected, we fail.
1093 Return 1 if the combination is valid, zero otherwise. */
1096 combinable_i3pat (i3, loc, i2dest, i1dest, i1_not_in_src, pi3dest_killed)
1102 rtx *pi3dest_killed;
1106 if (GET_CODE (x) == SET)
1108 rtx set = expand_field_assignment (x);
1109 rtx dest = SET_DEST (set);
1110 rtx src = SET_SRC (set);
1111 rtx inner_dest = dest, inner_src = src;
1115 while (GET_CODE (inner_dest) == STRICT_LOW_PART
1116 || GET_CODE (inner_dest) == SUBREG
1117 || GET_CODE (inner_dest) == ZERO_EXTRACT)
1118 inner_dest = XEXP (inner_dest, 0);
1120 /* We probably don't need this any more now that LIMIT_RELOAD_CLASS
1123 while (GET_CODE (inner_src) == STRICT_LOW_PART
1124 || GET_CODE (inner_src) == SUBREG
1125 || GET_CODE (inner_src) == ZERO_EXTRACT)
1126 inner_src = XEXP (inner_src, 0);
1128 /* If it is better that two different modes keep two different pseudos,
1129 avoid combining them. This avoids producing the following pattern
1131 (set (subreg:SI (reg/v:QI 21) 0)
1132 (lshiftrt:SI (reg/v:SI 20)
1134 If that were made, reload could not handle the pair of
1135 reg 20/21, since it would try to get any GENERAL_REGS
1136 but some of them don't handle QImode. */
1138 if (rtx_equal_p (inner_src, i2dest)
1139 && GET_CODE (inner_dest) == REG
1140 && ! MODES_TIEABLE_P (GET_MODE (i2dest), GET_MODE (inner_dest)))
1144 /* Check for the case where I3 modifies its output, as
1146 if ((inner_dest != dest
1147 && (reg_overlap_mentioned_p (i2dest, inner_dest)
1148 || (i1dest && reg_overlap_mentioned_p (i1dest, inner_dest))))
1149 /* This is the same test done in can_combine_p except that we
1150 allow a hard register with SMALL_REGISTER_CLASSES if SRC is a
1152 Moreover, we can't test all_adjacent; we don't have to, since
1153 this instruction will stay in place, thus we are not considering
1154 to increase the lifetime of INNER_DEST. */
1155 || (GET_CODE (inner_dest) == REG
1156 && REGNO (inner_dest) < FIRST_PSEUDO_REGISTER
1157 && (! HARD_REGNO_MODE_OK (REGNO (inner_dest),
1158 GET_MODE (inner_dest))
1159 #ifdef SMALL_REGISTER_CLASSES
1160 || (SMALL_REGISTER_CLASSES
1161 && GET_CODE (src) != CALL && ! REG_USERVAR_P (inner_dest)
1162 && FUNCTION_VALUE_REGNO_P (REGNO (inner_dest)))
1165 || (i1_not_in_src && reg_overlap_mentioned_p (i1dest, src)))
1168 /* If DEST is used in I3, it is being killed in this insn,
1169 so record that for later.
1170 Never add REG_DEAD notes for the FRAME_POINTER_REGNUM or the
1171 STACK_POINTER_REGNUM, since these are always considered to be
1172 live. Similarly for ARG_POINTER_REGNUM if it is fixed. */
1173 if (pi3dest_killed && GET_CODE (dest) == REG
1174 && reg_referenced_p (dest, PATTERN (i3))
1175 && REGNO (dest) != FRAME_POINTER_REGNUM
1176 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
1177 && REGNO (dest) != HARD_FRAME_POINTER_REGNUM
1179 #if ARG_POINTER_REGNUM != FRAME_POINTER_REGNUM
1180 && (REGNO (dest) != ARG_POINTER_REGNUM
1181 || ! fixed_regs [REGNO (dest)])
1183 && REGNO (dest) != STACK_POINTER_REGNUM)
1185 if (*pi3dest_killed)
1188 *pi3dest_killed = dest;
1192 else if (GET_CODE (x) == PARALLEL)
1196 for (i = 0; i < XVECLEN (x, 0); i++)
1197 if (! combinable_i3pat (i3, &XVECEXP (x, 0, i), i2dest, i1dest,
1198 i1_not_in_src, pi3dest_killed))
1205 /* Try to combine the insns I1 and I2 into I3.
1206 Here I1 and I2 appear earlier than I3.
1207 I1 can be zero; then we combine just I2 into I3.
1209 It we are combining three insns and the resulting insn is not recognized,
1210 try splitting it into two insns. If that happens, I2 and I3 are retained
1211 and I1 is pseudo-deleted by turning it into a NOTE. Otherwise, I1 and I2
1214 Return 0 if the combination does not work. Then nothing is changed.
1215 If we did the combination, return the insn at which combine should
1219 try_combine (i3, i2, i1)
1220 register rtx i3, i2, i1;
1222 /* New patterns for I3 and I3, respectively. */
1223 rtx newpat, newi2pat = 0;
1224 /* Indicates need to preserve SET in I1 or I2 in I3 if it is not dead. */
1225 int added_sets_1, added_sets_2;
1226 /* Total number of SETs to put into I3. */
1228 /* Nonzero is I2's body now appears in I3. */
1230 /* INSN_CODEs for new I3, new I2, and user of condition code. */
1231 int insn_code_number, i2_code_number, other_code_number;
1232 /* Contains I3 if the destination of I3 is used in its source, which means
1233 that the old life of I3 is being killed. If that usage is placed into
1234 I2 and not in I3, a REG_DEAD note must be made. */
1235 rtx i3dest_killed = 0;
1236 /* SET_DEST and SET_SRC of I2 and I1. */
1237 rtx i2dest, i2src, i1dest = 0, i1src = 0;
1238 /* PATTERN (I2), or a copy of it in certain cases. */
1240 /* Indicates if I2DEST or I1DEST is in I2SRC or I1_SRC. */
1241 int i2dest_in_i2src = 0, i1dest_in_i1src = 0, i2dest_in_i1src = 0;
1242 int i1_feeds_i3 = 0;
1243 /* Notes that must be added to REG_NOTES in I3 and I2. */
1244 rtx new_i3_notes, new_i2_notes;
1245 /* Notes that we substituted I3 into I2 instead of the normal case. */
1246 int i3_subst_into_i2 = 0;
1247 /* Notes that I1, I2 or I3 is a MULT operation. */
1249 /* Number of clobbers of SCRATCH we had to add. */
1250 int i3_scratches = 0, i2_scratches = 0, other_scratches = 0;
1257 /* If any of I1, I2, and I3 isn't really an insn, we can't do anything.
1258 This can occur when flow deletes an insn that it has merged into an
1259 auto-increment address. We also can't do anything if I3 has a
1260 REG_LIBCALL note since we don't want to disrupt the contiguity of a
1263 if (GET_RTX_CLASS (GET_CODE (i3)) != 'i'
1264 || GET_RTX_CLASS (GET_CODE (i2)) != 'i'
1265 || (i1 && GET_RTX_CLASS (GET_CODE (i1)) != 'i')
1266 || find_reg_note (i3, REG_LIBCALL, NULL_RTX))
1271 undobuf.undos = undobuf.previous_undos = 0;
1272 undobuf.other_insn = 0;
1274 /* Save the current high-water-mark so we can free storage if we didn't
1275 accept this combination. */
1276 undobuf.storage = (char *) oballoc (0);
1278 /* Reset the hard register usage information. */
1279 CLEAR_HARD_REG_SET (newpat_used_regs);
1281 /* If I1 and I2 both feed I3, they can be in any order. To simplify the
1282 code below, set I1 to be the earlier of the two insns. */
1283 if (i1 && INSN_CUID (i1) > INSN_CUID (i2))
1284 temp = i1, i1 = i2, i2 = temp;
1286 added_links_insn = 0;
1288 /* First check for one important special-case that the code below will
1289 not handle. Namely, the case where I1 is zero, I2 has multiple sets,
1290 and I3 is a SET whose SET_SRC is a SET_DEST in I2. In that case,
1291 we may be able to replace that destination with the destination of I3.
1292 This occurs in the common code where we compute both a quotient and
1293 remainder into a structure, in which case we want to do the computation
1294 directly into the structure to avoid register-register copies.
1296 We make very conservative checks below and only try to handle the
1297 most common cases of this. For example, we only handle the case
1298 where I2 and I3 are adjacent to avoid making difficult register
1301 if (i1 == 0 && GET_CODE (i3) == INSN && GET_CODE (PATTERN (i3)) == SET
1302 && GET_CODE (SET_SRC (PATTERN (i3))) == REG
1303 && REGNO (SET_SRC (PATTERN (i3))) >= FIRST_PSEUDO_REGISTER
1304 #ifdef SMALL_REGISTER_CLASSES
1305 && (! SMALL_REGISTER_CLASSES
1306 || GET_CODE (SET_DEST (PATTERN (i3))) != REG
1307 || REGNO (SET_DEST (PATTERN (i3))) >= FIRST_PSEUDO_REGISTER
1308 || REG_USERVAR_P (SET_DEST (PATTERN (i3))))
1310 && find_reg_note (i3, REG_DEAD, SET_SRC (PATTERN (i3)))
1311 && GET_CODE (PATTERN (i2)) == PARALLEL
1312 && ! side_effects_p (SET_DEST (PATTERN (i3)))
1313 /* If the dest of I3 is a ZERO_EXTRACT or STRICT_LOW_PART, the code
1314 below would need to check what is inside (and reg_overlap_mentioned_p
1315 doesn't support those codes anyway). Don't allow those destinations;
1316 the resulting insn isn't likely to be recognized anyway. */
1317 && GET_CODE (SET_DEST (PATTERN (i3))) != ZERO_EXTRACT
1318 && GET_CODE (SET_DEST (PATTERN (i3))) != STRICT_LOW_PART
1319 && ! reg_overlap_mentioned_p (SET_SRC (PATTERN (i3)),
1320 SET_DEST (PATTERN (i3)))
1321 && next_real_insn (i2) == i3)
1323 rtx p2 = PATTERN (i2);
1325 /* Make sure that the destination of I3,
1326 which we are going to substitute into one output of I2,
1327 is not used within another output of I2. We must avoid making this:
1328 (parallel [(set (mem (reg 69)) ...)
1329 (set (reg 69) ...)])
1330 which is not well-defined as to order of actions.
1331 (Besides, reload can't handle output reloads for this.)
1333 The problem can also happen if the dest of I3 is a memory ref,
1334 if another dest in I2 is an indirect memory ref. */
1335 for (i = 0; i < XVECLEN (p2, 0); i++)
1336 if ((GET_CODE (XVECEXP (p2, 0, i)) == SET
1337 || GET_CODE (XVECEXP (p2, 0, i)) == CLOBBER)
1338 && reg_overlap_mentioned_p (SET_DEST (PATTERN (i3)),
1339 SET_DEST (XVECEXP (p2, 0, i))))
1342 if (i == XVECLEN (p2, 0))
1343 for (i = 0; i < XVECLEN (p2, 0); i++)
1344 if (SET_DEST (XVECEXP (p2, 0, i)) == SET_SRC (PATTERN (i3)))
1349 subst_low_cuid = INSN_CUID (i2);
1351 added_sets_2 = added_sets_1 = 0;
1352 i2dest = SET_SRC (PATTERN (i3));
1354 /* Replace the dest in I2 with our dest and make the resulting
1355 insn the new pattern for I3. Then skip to where we
1356 validate the pattern. Everything was set up above. */
1357 SUBST (SET_DEST (XVECEXP (p2, 0, i)),
1358 SET_DEST (PATTERN (i3)));
1361 i3_subst_into_i2 = 1;
1362 goto validate_replacement;
1367 /* If we have no I1 and I2 looks like:
1368 (parallel [(set (reg:CC X) (compare:CC OP (const_int 0)))
1370 make up a dummy I1 that is
1373 (set (reg:CC X) (compare:CC Y (const_int 0)))
1375 (We can ignore any trailing CLOBBERs.)
1377 This undoes a previous combination and allows us to match a branch-and-
1380 if (i1 == 0 && GET_CODE (PATTERN (i2)) == PARALLEL
1381 && XVECLEN (PATTERN (i2), 0) >= 2
1382 && GET_CODE (XVECEXP (PATTERN (i2), 0, 0)) == SET
1383 && (GET_MODE_CLASS (GET_MODE (SET_DEST (XVECEXP (PATTERN (i2), 0, 0))))
1385 && GET_CODE (SET_SRC (XVECEXP (PATTERN (i2), 0, 0))) == COMPARE
1386 && XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 1) == const0_rtx
1387 && GET_CODE (XVECEXP (PATTERN (i2), 0, 1)) == SET
1388 && GET_CODE (SET_DEST (XVECEXP (PATTERN (i2), 0, 1))) == REG
1389 && rtx_equal_p (XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 0),
1390 SET_SRC (XVECEXP (PATTERN (i2), 0, 1))))
1392 for (i = XVECLEN (PATTERN (i2), 0) - 1; i >= 2; i--)
1393 if (GET_CODE (XVECEXP (PATTERN (i2), 0, i)) != CLOBBER)
1398 /* We make I1 with the same INSN_UID as I2. This gives it
1399 the same INSN_CUID for value tracking. Our fake I1 will
1400 never appear in the insn stream so giving it the same INSN_UID
1401 as I2 will not cause a problem. */
1403 subst_prev_insn = i1
1404 = gen_rtx (INSN, VOIDmode, INSN_UID (i2), 0, i2,
1405 XVECEXP (PATTERN (i2), 0, 1), -1, 0, 0);
1407 SUBST (PATTERN (i2), XVECEXP (PATTERN (i2), 0, 0));
1408 SUBST (XEXP (SET_SRC (PATTERN (i2)), 0),
1409 SET_DEST (PATTERN (i1)));
1414 /* Verify that I2 and I1 are valid for combining. */
1415 if (! can_combine_p (i2, i3, i1, NULL_RTX, &i2dest, &i2src)
1416 || (i1 && ! can_combine_p (i1, i3, NULL_RTX, i2, &i1dest, &i1src)))
1422 /* Record whether I2DEST is used in I2SRC and similarly for the other
1423 cases. Knowing this will help in register status updating below. */
1424 i2dest_in_i2src = reg_overlap_mentioned_p (i2dest, i2src);
1425 i1dest_in_i1src = i1 && reg_overlap_mentioned_p (i1dest, i1src);
1426 i2dest_in_i1src = i1 && reg_overlap_mentioned_p (i2dest, i1src);
1428 /* See if I1 directly feeds into I3. It does if I1DEST is not used
1430 i1_feeds_i3 = i1 && ! reg_overlap_mentioned_p (i1dest, i2src);
1432 /* Ensure that I3's pattern can be the destination of combines. */
1433 if (! combinable_i3pat (i3, &PATTERN (i3), i2dest, i1dest,
1434 i1 && i2dest_in_i1src && i1_feeds_i3,
1441 /* See if any of the insns is a MULT operation. Unless one is, we will
1442 reject a combination that is, since it must be slower. Be conservative
1444 if (GET_CODE (i2src) == MULT
1445 || (i1 != 0 && GET_CODE (i1src) == MULT)
1446 || (GET_CODE (PATTERN (i3)) == SET
1447 && GET_CODE (SET_SRC (PATTERN (i3))) == MULT))
1450 /* If I3 has an inc, then give up if I1 or I2 uses the reg that is inc'd.
1451 We used to do this EXCEPT in one case: I3 has a post-inc in an
1452 output operand. However, that exception can give rise to insns like
1454 which is a famous insn on the PDP-11 where the value of r3 used as the
1455 source was model-dependent. Avoid this sort of thing. */
1458 if (!(GET_CODE (PATTERN (i3)) == SET
1459 && GET_CODE (SET_SRC (PATTERN (i3))) == REG
1460 && GET_CODE (SET_DEST (PATTERN (i3))) == MEM
1461 && (GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_INC
1462 || GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_DEC)))
1463 /* It's not the exception. */
1466 for (link = REG_NOTES (i3); link; link = XEXP (link, 1))
1467 if (REG_NOTE_KIND (link) == REG_INC
1468 && (reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i2))
1470 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i1)))))
1477 /* See if the SETs in I1 or I2 need to be kept around in the merged
1478 instruction: whenever the value set there is still needed past I3.
1479 For the SETs in I2, this is easy: we see if I2DEST dies or is set in I3.
1481 For the SET in I1, we have two cases: If I1 and I2 independently
1482 feed into I3, the set in I1 needs to be kept around if I1DEST dies
1483 or is set in I3. Otherwise (if I1 feeds I2 which feeds I3), the set
1484 in I1 needs to be kept around unless I1DEST dies or is set in either
1485 I2 or I3. We can distinguish these cases by seeing if I2SRC mentions
1486 I1DEST. If so, we know I1 feeds into I2. */
1488 added_sets_2 = ! dead_or_set_p (i3, i2dest);
1491 = i1 && ! (i1_feeds_i3 ? dead_or_set_p (i3, i1dest)
1492 : (dead_or_set_p (i3, i1dest) || dead_or_set_p (i2, i1dest)));
1494 /* If the set in I2 needs to be kept around, we must make a copy of
1495 PATTERN (I2), so that when we substitute I1SRC for I1DEST in
1496 PATTERN (I2), we are only substituting for the original I1DEST, not into
1497 an already-substituted copy. This also prevents making self-referential
1498 rtx. If I2 is a PARALLEL, we just need the piece that assigns I2SRC to
1501 i2pat = (GET_CODE (PATTERN (i2)) == PARALLEL
1502 ? gen_rtx (SET, VOIDmode, i2dest, i2src)
1506 i2pat = copy_rtx (i2pat);
1510 /* Substitute in the latest insn for the regs set by the earlier ones. */
1512 maxreg = max_reg_num ();
1516 /* It is possible that the source of I2 or I1 may be performing an
1517 unneeded operation, such as a ZERO_EXTEND of something that is known
1518 to have the high part zero. Handle that case by letting subst look at
1519 the innermost one of them.
1521 Another way to do this would be to have a function that tries to
1522 simplify a single insn instead of merging two or more insns. We don't
1523 do this because of the potential of infinite loops and because
1524 of the potential extra memory required. However, doing it the way
1525 we are is a bit of a kludge and doesn't catch all cases.
1527 But only do this if -fexpensive-optimizations since it slows things down
1528 and doesn't usually win. */
1530 if (flag_expensive_optimizations)
1532 /* Pass pc_rtx so no substitutions are done, just simplifications.
1533 The cases that we are interested in here do not involve the few
1534 cases were is_replaced is checked. */
1537 subst_low_cuid = INSN_CUID (i1);
1538 i1src = subst (i1src, pc_rtx, pc_rtx, 0, 0);
1542 subst_low_cuid = INSN_CUID (i2);
1543 i2src = subst (i2src, pc_rtx, pc_rtx, 0, 0);
1546 undobuf.previous_undos = undobuf.undos;
1550 /* Many machines that don't use CC0 have insns that can both perform an
1551 arithmetic operation and set the condition code. These operations will
1552 be represented as a PARALLEL with the first element of the vector
1553 being a COMPARE of an arithmetic operation with the constant zero.
1554 The second element of the vector will set some pseudo to the result
1555 of the same arithmetic operation. If we simplify the COMPARE, we won't
1556 match such a pattern and so will generate an extra insn. Here we test
1557 for this case, where both the comparison and the operation result are
1558 needed, and make the PARALLEL by just replacing I2DEST in I3SRC with
1559 I2SRC. Later we will make the PARALLEL that contains I2. */
1561 if (i1 == 0 && added_sets_2 && GET_CODE (PATTERN (i3)) == SET
1562 && GET_CODE (SET_SRC (PATTERN (i3))) == COMPARE
1563 && XEXP (SET_SRC (PATTERN (i3)), 1) == const0_rtx
1564 && rtx_equal_p (XEXP (SET_SRC (PATTERN (i3)), 0), i2dest))
1567 enum machine_mode compare_mode;
1569 newpat = PATTERN (i3);
1570 SUBST (XEXP (SET_SRC (newpat), 0), i2src);
1574 #ifdef EXTRA_CC_MODES
1575 /* See if a COMPARE with the operand we substituted in should be done
1576 with the mode that is currently being used. If not, do the same
1577 processing we do in `subst' for a SET; namely, if the destination
1578 is used only once, try to replace it with a register of the proper
1579 mode and also replace the COMPARE. */
1580 if (undobuf.other_insn == 0
1581 && (cc_use = find_single_use (SET_DEST (newpat), i3,
1582 &undobuf.other_insn))
1583 && ((compare_mode = SELECT_CC_MODE (GET_CODE (*cc_use),
1585 != GET_MODE (SET_DEST (newpat))))
1587 int regno = REGNO (SET_DEST (newpat));
1588 rtx new_dest = gen_rtx (REG, compare_mode, regno);
1590 if (regno < FIRST_PSEUDO_REGISTER
1591 || (REG_N_SETS (regno) == 1 && ! added_sets_2
1592 && ! REG_USERVAR_P (SET_DEST (newpat))))
1594 if (regno >= FIRST_PSEUDO_REGISTER)
1595 SUBST (regno_reg_rtx[regno], new_dest);
1597 SUBST (SET_DEST (newpat), new_dest);
1598 SUBST (XEXP (*cc_use, 0), new_dest);
1599 SUBST (SET_SRC (newpat),
1600 gen_rtx_combine (COMPARE, compare_mode,
1601 i2src, const0_rtx));
1604 undobuf.other_insn = 0;
1611 n_occurrences = 0; /* `subst' counts here */
1613 /* If I1 feeds into I2 (not into I3) and I1DEST is in I1SRC, we
1614 need to make a unique copy of I2SRC each time we substitute it
1615 to avoid self-referential rtl. */
1617 subst_low_cuid = INSN_CUID (i2);
1618 newpat = subst (PATTERN (i3), i2dest, i2src, 0,
1619 ! i1_feeds_i3 && i1dest_in_i1src);
1620 undobuf.previous_undos = undobuf.undos;
1622 /* Record whether i2's body now appears within i3's body. */
1623 i2_is_used = n_occurrences;
1626 /* If we already got a failure, don't try to do more. Otherwise,
1627 try to substitute in I1 if we have it. */
1629 if (i1 && GET_CODE (newpat) != CLOBBER)
1631 /* Before we can do this substitution, we must redo the test done
1632 above (see detailed comments there) that ensures that I1DEST
1633 isn't mentioned in any SETs in NEWPAT that are field assignments. */
1635 if (! combinable_i3pat (NULL_RTX, &newpat, i1dest, NULL_RTX,
1643 subst_low_cuid = INSN_CUID (i1);
1644 newpat = subst (newpat, i1dest, i1src, 0, 0);
1645 undobuf.previous_undos = undobuf.undos;
1648 /* Fail if an autoincrement side-effect has been duplicated. Be careful
1649 to count all the ways that I2SRC and I1SRC can be used. */
1650 if ((FIND_REG_INC_NOTE (i2, NULL_RTX) != 0
1651 && i2_is_used + added_sets_2 > 1)
1652 || (i1 != 0 && FIND_REG_INC_NOTE (i1, NULL_RTX) != 0
1653 && (n_occurrences + added_sets_1 + (added_sets_2 && ! i1_feeds_i3)
1655 /* Fail if we tried to make a new register (we used to abort, but there's
1656 really no reason to). */
1657 || max_reg_num () != maxreg
1658 /* Fail if we couldn't do something and have a CLOBBER. */
1659 || GET_CODE (newpat) == CLOBBER
1660 /* Fail if this new pattern is a MULT and we didn't have one before
1661 at the outer level. */
1662 || (GET_CODE (newpat) == SET && GET_CODE (SET_SRC (newpat)) == MULT
1669 /* If the actions of the earlier insns must be kept
1670 in addition to substituting them into the latest one,
1671 we must make a new PARALLEL for the latest insn
1672 to hold additional the SETs. */
1674 if (added_sets_1 || added_sets_2)
1678 if (GET_CODE (newpat) == PARALLEL)
1680 rtvec old = XVEC (newpat, 0);
1681 total_sets = XVECLEN (newpat, 0) + added_sets_1 + added_sets_2;
1682 newpat = gen_rtx (PARALLEL, VOIDmode, rtvec_alloc (total_sets));
1683 bcopy ((char *) &old->elem[0], (char *) XVEC (newpat, 0)->elem,
1684 sizeof (old->elem[0]) * old->num_elem);
1689 total_sets = 1 + added_sets_1 + added_sets_2;
1690 newpat = gen_rtx (PARALLEL, VOIDmode, rtvec_alloc (total_sets));
1691 XVECEXP (newpat, 0, 0) = old;
1695 XVECEXP (newpat, 0, --total_sets)
1696 = (GET_CODE (PATTERN (i1)) == PARALLEL
1697 ? gen_rtx (SET, VOIDmode, i1dest, i1src) : PATTERN (i1));
1701 /* If there is no I1, use I2's body as is. We used to also not do
1702 the subst call below if I2 was substituted into I3,
1703 but that could lose a simplification. */
1705 XVECEXP (newpat, 0, --total_sets) = i2pat;
1707 /* See comment where i2pat is assigned. */
1708 XVECEXP (newpat, 0, --total_sets)
1709 = subst (i2pat, i1dest, i1src, 0, 0);
1713 /* We come here when we are replacing a destination in I2 with the
1714 destination of I3. */
1715 validate_replacement:
1717 /* Note which hard regs this insn has as inputs. */
1718 mark_used_regs_combine (newpat);
1720 /* Is the result of combination a valid instruction? */
1722 = recog_for_combine (&newpat, i3, &new_i3_notes, &i3_scratches);
1724 /* If the result isn't valid, see if it is a PARALLEL of two SETs where
1725 the second SET's destination is a register that is unused. In that case,
1726 we just need the first SET. This can occur when simplifying a divmod
1727 insn. We *must* test for this case here because the code below that
1728 splits two independent SETs doesn't handle this case correctly when it
1729 updates the register status. Also check the case where the first
1730 SET's destination is unused. That would not cause incorrect code, but
1731 does cause an unneeded insn to remain. */
1733 if (insn_code_number < 0 && GET_CODE (newpat) == PARALLEL
1734 && XVECLEN (newpat, 0) == 2
1735 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
1736 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
1737 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) == REG
1738 && find_reg_note (i3, REG_UNUSED, SET_DEST (XVECEXP (newpat, 0, 1)))
1739 && ! side_effects_p (SET_SRC (XVECEXP (newpat, 0, 1)))
1740 && asm_noperands (newpat) < 0)
1742 newpat = XVECEXP (newpat, 0, 0);
1744 = recog_for_combine (&newpat, i3, &new_i3_notes, &i3_scratches);
1747 else if (insn_code_number < 0 && GET_CODE (newpat) == PARALLEL
1748 && XVECLEN (newpat, 0) == 2
1749 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
1750 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
1751 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) == REG
1752 && find_reg_note (i3, REG_UNUSED, SET_DEST (XVECEXP (newpat, 0, 0)))
1753 && ! side_effects_p (SET_SRC (XVECEXP (newpat, 0, 0)))
1754 && asm_noperands (newpat) < 0)
1756 newpat = XVECEXP (newpat, 0, 1);
1758 = recog_for_combine (&newpat, i3, &new_i3_notes, &i3_scratches);
1761 /* If we were combining three insns and the result is a simple SET
1762 with no ASM_OPERANDS that wasn't recognized, try to split it into two
1763 insns. There are two ways to do this. It can be split using a
1764 machine-specific method (like when you have an addition of a large
1765 constant) or by combine in the function find_split_point. */
1767 if (i1 && insn_code_number < 0 && GET_CODE (newpat) == SET
1768 && asm_noperands (newpat) < 0)
1770 rtx m_split, *split;
1771 rtx ni2dest = i2dest;
1773 /* See if the MD file can split NEWPAT. If it can't, see if letting it
1774 use I2DEST as a scratch register will help. In the latter case,
1775 convert I2DEST to the mode of the source of NEWPAT if we can. */
1777 m_split = split_insns (newpat, i3);
1779 /* We can only use I2DEST as a scratch reg if it doesn't overlap any
1780 inputs of NEWPAT. */
1782 /* ??? If I2DEST is not safe, and I1DEST exists, then it would be
1783 possible to try that as a scratch reg. This would require adding
1784 more code to make it work though. */
1786 if (m_split == 0 && ! reg_overlap_mentioned_p (ni2dest, newpat))
1788 /* If I2DEST is a hard register or the only use of a pseudo,
1789 we can change its mode. */
1790 if (GET_MODE (SET_DEST (newpat)) != GET_MODE (i2dest)
1791 && GET_MODE (SET_DEST (newpat)) != VOIDmode
1792 && GET_CODE (i2dest) == REG
1793 && (REGNO (i2dest) < FIRST_PSEUDO_REGISTER
1794 || (REG_N_SETS (REGNO (i2dest)) == 1 && ! added_sets_2
1795 && ! REG_USERVAR_P (i2dest))))
1796 ni2dest = gen_rtx (REG, GET_MODE (SET_DEST (newpat)),
1799 m_split = split_insns (gen_rtx (PARALLEL, VOIDmode,
1800 gen_rtvec (2, newpat,
1807 if (m_split && GET_CODE (m_split) == SEQUENCE
1808 && XVECLEN (m_split, 0) == 2
1809 && (next_real_insn (i2) == i3
1810 || ! use_crosses_set_p (PATTERN (XVECEXP (m_split, 0, 0)),
1814 rtx newi3pat = PATTERN (XVECEXP (m_split, 0, 1));
1815 newi2pat = PATTERN (XVECEXP (m_split, 0, 0));
1817 i3set = single_set (XVECEXP (m_split, 0, 1));
1818 i2set = single_set (XVECEXP (m_split, 0, 0));
1820 /* In case we changed the mode of I2DEST, replace it in the
1821 pseudo-register table here. We can't do it above in case this
1822 code doesn't get executed and we do a split the other way. */
1824 if (REGNO (i2dest) >= FIRST_PSEUDO_REGISTER)
1825 SUBST (regno_reg_rtx[REGNO (i2dest)], ni2dest);
1827 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes,
1830 /* If I2 or I3 has multiple SETs, we won't know how to track
1831 register status, so don't use these insns. If I2's destination
1832 is used between I2 and I3, we also can't use these insns. */
1834 if (i2_code_number >= 0 && i2set && i3set
1835 && (next_real_insn (i2) == i3
1836 || ! reg_used_between_p (SET_DEST (i2set), i2, i3)))
1837 insn_code_number = recog_for_combine (&newi3pat, i3, &new_i3_notes,
1839 if (insn_code_number >= 0)
1842 /* It is possible that both insns now set the destination of I3.
1843 If so, we must show an extra use of it. */
1845 if (insn_code_number >= 0)
1847 rtx new_i3_dest = SET_DEST (i3set);
1848 rtx new_i2_dest = SET_DEST (i2set);
1850 while (GET_CODE (new_i3_dest) == ZERO_EXTRACT
1851 || GET_CODE (new_i3_dest) == STRICT_LOW_PART
1852 || GET_CODE (new_i3_dest) == SUBREG)
1853 new_i3_dest = XEXP (new_i3_dest, 0);
1855 while (GET_CODE (new_i2_dest) == ZERO_EXTRACT
1856 || GET_CODE (new_i2_dest) == STRICT_LOW_PART
1857 || GET_CODE (new_i2_dest) == SUBREG)
1858 new_i2_dest = XEXP (new_i2_dest, 0);
1860 if (GET_CODE (new_i3_dest) == REG
1861 && GET_CODE (new_i2_dest) == REG
1862 && REGNO (new_i3_dest) == REGNO (new_i2_dest))
1863 REG_N_SETS (REGNO (new_i2_dest))++;
1867 /* If we can split it and use I2DEST, go ahead and see if that
1868 helps things be recognized. Verify that none of the registers
1869 are set between I2 and I3. */
1870 if (insn_code_number < 0 && (split = find_split_point (&newpat, i3)) != 0
1872 && GET_CODE (i2dest) == REG
1874 /* We need I2DEST in the proper mode. If it is a hard register
1875 or the only use of a pseudo, we can change its mode. */
1876 && (GET_MODE (*split) == GET_MODE (i2dest)
1877 || GET_MODE (*split) == VOIDmode
1878 || REGNO (i2dest) < FIRST_PSEUDO_REGISTER
1879 || (REG_N_SETS (REGNO (i2dest)) == 1 && ! added_sets_2
1880 && ! REG_USERVAR_P (i2dest)))
1881 && (next_real_insn (i2) == i3
1882 || ! use_crosses_set_p (*split, INSN_CUID (i2)))
1883 /* We can't overwrite I2DEST if its value is still used by
1885 && ! reg_referenced_p (i2dest, newpat))
1887 rtx newdest = i2dest;
1888 enum rtx_code split_code = GET_CODE (*split);
1889 enum machine_mode split_mode = GET_MODE (*split);
1891 /* Get NEWDEST as a register in the proper mode. We have already
1892 validated that we can do this. */
1893 if (GET_MODE (i2dest) != split_mode && split_mode != VOIDmode)
1895 newdest = gen_rtx (REG, split_mode, REGNO (i2dest));
1897 if (REGNO (i2dest) >= FIRST_PSEUDO_REGISTER)
1898 SUBST (regno_reg_rtx[REGNO (i2dest)], newdest);
1901 /* If *SPLIT is a (mult FOO (const_int pow2)), convert it to
1902 an ASHIFT. This can occur if it was inside a PLUS and hence
1903 appeared to be a memory address. This is a kludge. */
1904 if (split_code == MULT
1905 && GET_CODE (XEXP (*split, 1)) == CONST_INT
1906 && (i = exact_log2 (INTVAL (XEXP (*split, 1)))) >= 0)
1908 SUBST (*split, gen_rtx_combine (ASHIFT, split_mode,
1909 XEXP (*split, 0), GEN_INT (i)));
1910 /* Update split_code because we may not have a multiply
1912 split_code = GET_CODE (*split);
1915 #ifdef INSN_SCHEDULING
1916 /* If *SPLIT is a paradoxical SUBREG, when we split it, it should
1917 be written as a ZERO_EXTEND. */
1918 if (split_code == SUBREG && GET_CODE (SUBREG_REG (*split)) == MEM)
1919 SUBST (*split, gen_rtx_combine (ZERO_EXTEND, split_mode,
1923 newi2pat = gen_rtx_combine (SET, VOIDmode, newdest, *split);
1924 SUBST (*split, newdest);
1926 = recog_for_combine (&newi2pat, i2, &new_i2_notes, &i2_scratches);
1928 /* If the split point was a MULT and we didn't have one before,
1929 don't use one now. */
1930 if (i2_code_number >= 0 && ! (split_code == MULT && ! have_mult))
1932 = recog_for_combine (&newpat, i3, &new_i3_notes, &i3_scratches);
1936 /* Check for a case where we loaded from memory in a narrow mode and
1937 then sign extended it, but we need both registers. In that case,
1938 we have a PARALLEL with both loads from the same memory location.
1939 We can split this into a load from memory followed by a register-register
1940 copy. This saves at least one insn, more if register allocation can
1943 We cannot do this if the destination of the second assignment is
1944 a register that we have already assumed is zero-extended. Similarly
1945 for a SUBREG of such a register. */
1947 else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0
1948 && GET_CODE (newpat) == PARALLEL
1949 && XVECLEN (newpat, 0) == 2
1950 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
1951 && GET_CODE (SET_SRC (XVECEXP (newpat, 0, 0))) == SIGN_EXTEND
1952 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
1953 && rtx_equal_p (SET_SRC (XVECEXP (newpat, 0, 1)),
1954 XEXP (SET_SRC (XVECEXP (newpat, 0, 0)), 0))
1955 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)),
1957 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
1958 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
1959 && ! (temp = SET_DEST (XVECEXP (newpat, 0, 1)),
1960 (GET_CODE (temp) == REG
1961 && reg_nonzero_bits[REGNO (temp)] != 0
1962 && GET_MODE_BITSIZE (GET_MODE (temp)) < BITS_PER_WORD
1963 && GET_MODE_BITSIZE (GET_MODE (temp)) < HOST_BITS_PER_INT
1964 && (reg_nonzero_bits[REGNO (temp)]
1965 != GET_MODE_MASK (word_mode))))
1966 && ! (GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) == SUBREG
1967 && (temp = SUBREG_REG (SET_DEST (XVECEXP (newpat, 0, 1))),
1968 (GET_CODE (temp) == REG
1969 && reg_nonzero_bits[REGNO (temp)] != 0
1970 && GET_MODE_BITSIZE (GET_MODE (temp)) < BITS_PER_WORD
1971 && GET_MODE_BITSIZE (GET_MODE (temp)) < HOST_BITS_PER_INT
1972 && (reg_nonzero_bits[REGNO (temp)]
1973 != GET_MODE_MASK (word_mode)))))
1974 && ! reg_overlap_mentioned_p (SET_DEST (XVECEXP (newpat, 0, 1)),
1975 SET_SRC (XVECEXP (newpat, 0, 1)))
1976 && ! find_reg_note (i3, REG_UNUSED,
1977 SET_DEST (XVECEXP (newpat, 0, 0))))
1981 newi2pat = XVECEXP (newpat, 0, 0);
1982 ni2dest = SET_DEST (XVECEXP (newpat, 0, 0));
1983 newpat = XVECEXP (newpat, 0, 1);
1984 SUBST (SET_SRC (newpat),
1985 gen_lowpart_for_combine (GET_MODE (SET_SRC (newpat)), ni2dest));
1987 = recog_for_combine (&newi2pat, i2, &new_i2_notes, &i2_scratches);
1989 if (i2_code_number >= 0)
1991 = recog_for_combine (&newpat, i3, &new_i3_notes, &i3_scratches);
1993 if (insn_code_number >= 0)
1998 /* If we will be able to accept this, we have made a change to the
1999 destination of I3. This can invalidate a LOG_LINKS pointing
2000 to I3. No other part of combine.c makes such a transformation.
2002 The new I3 will have a destination that was previously the
2003 destination of I1 or I2 and which was used in i2 or I3. Call
2004 distribute_links to make a LOG_LINK from the next use of
2005 that destination. */
2007 PATTERN (i3) = newpat;
2008 distribute_links (gen_rtx (INSN_LIST, VOIDmode, i3, NULL_RTX));
2010 /* I3 now uses what used to be its destination and which is
2011 now I2's destination. That means we need a LOG_LINK from
2012 I3 to I2. But we used to have one, so we still will.
2014 However, some later insn might be using I2's dest and have
2015 a LOG_LINK pointing at I3. We must remove this link.
2016 The simplest way to remove the link is to point it at I1,
2017 which we know will be a NOTE. */
2019 for (insn = NEXT_INSN (i3);
2020 insn && (this_basic_block == n_basic_blocks - 1
2021 || insn != basic_block_head[this_basic_block + 1]);
2022 insn = NEXT_INSN (insn))
2024 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i'
2025 && reg_referenced_p (ni2dest, PATTERN (insn)))
2027 for (link = LOG_LINKS (insn); link;
2028 link = XEXP (link, 1))
2029 if (XEXP (link, 0) == i3)
2030 XEXP (link, 0) = i1;
2038 /* Similarly, check for a case where we have a PARALLEL of two independent
2039 SETs but we started with three insns. In this case, we can do the sets
2040 as two separate insns. This case occurs when some SET allows two
2041 other insns to combine, but the destination of that SET is still live. */
2043 else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0
2044 && GET_CODE (newpat) == PARALLEL
2045 && XVECLEN (newpat, 0) == 2
2046 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
2047 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != ZERO_EXTRACT
2048 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != STRICT_LOW_PART
2049 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
2050 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
2051 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
2052 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)),
2054 /* Don't pass sets with (USE (MEM ...)) dests to the following. */
2055 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != USE
2056 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != USE
2057 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 1)),
2058 XVECEXP (newpat, 0, 0))
2059 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 0)),
2060 XVECEXP (newpat, 0, 1)))
2062 newi2pat = XVECEXP (newpat, 0, 1);
2063 newpat = XVECEXP (newpat, 0, 0);
2066 = recog_for_combine (&newi2pat, i2, &new_i2_notes, &i2_scratches);
2068 if (i2_code_number >= 0)
2070 = recog_for_combine (&newpat, i3, &new_i3_notes, &i3_scratches);
2073 /* If it still isn't recognized, fail and change things back the way they
2075 if ((insn_code_number < 0
2076 /* Is the result a reasonable ASM_OPERANDS? */
2077 && (! check_asm_operands (newpat) || added_sets_1 || added_sets_2)))
2083 /* If we had to change another insn, make sure it is valid also. */
2084 if (undobuf.other_insn)
2086 rtx other_pat = PATTERN (undobuf.other_insn);
2087 rtx new_other_notes;
2090 CLEAR_HARD_REG_SET (newpat_used_regs);
2093 = recog_for_combine (&other_pat, undobuf.other_insn,
2094 &new_other_notes, &other_scratches);
2096 if (other_code_number < 0 && ! check_asm_operands (other_pat))
2102 PATTERN (undobuf.other_insn) = other_pat;
2104 /* If any of the notes in OTHER_INSN were REG_UNUSED, ensure that they
2105 are still valid. Then add any non-duplicate notes added by
2106 recog_for_combine. */
2107 for (note = REG_NOTES (undobuf.other_insn); note; note = next)
2109 next = XEXP (note, 1);
2111 if (REG_NOTE_KIND (note) == REG_UNUSED
2112 && ! reg_set_p (XEXP (note, 0), PATTERN (undobuf.other_insn)))
2114 if (GET_CODE (XEXP (note, 0)) == REG)
2115 REG_N_DEATHS (REGNO (XEXP (note, 0)))--;
2117 remove_note (undobuf.other_insn, note);
2121 for (note = new_other_notes; note; note = XEXP (note, 1))
2122 if (GET_CODE (XEXP (note, 0)) == REG)
2123 REG_N_DEATHS (REGNO (XEXP (note, 0)))++;
2125 distribute_notes (new_other_notes, undobuf.other_insn,
2126 undobuf.other_insn, NULL_RTX, NULL_RTX, NULL_RTX);
2129 /* We now know that we can do this combination. Merge the insns and
2130 update the status of registers and LOG_LINKS. */
2133 rtx i3notes, i2notes, i1notes = 0;
2134 rtx i3links, i2links, i1links = 0;
2137 /* Compute which registers we expect to eliminate. */
2138 rtx elim_i2 = (newi2pat || i2dest_in_i2src || i2dest_in_i1src
2140 rtx elim_i1 = i1 == 0 || i1dest_in_i1src ? 0 : i1dest;
2142 /* Get the old REG_NOTES and LOG_LINKS from all our insns and
2144 i3notes = REG_NOTES (i3), i3links = LOG_LINKS (i3);
2145 i2notes = REG_NOTES (i2), i2links = LOG_LINKS (i2);
2147 i1notes = REG_NOTES (i1), i1links = LOG_LINKS (i1);
2149 /* Ensure that we do not have something that should not be shared but
2150 occurs multiple times in the new insns. Check this by first
2151 resetting all the `used' flags and then copying anything is shared. */
2153 reset_used_flags (i3notes);
2154 reset_used_flags (i2notes);
2155 reset_used_flags (i1notes);
2156 reset_used_flags (newpat);
2157 reset_used_flags (newi2pat);
2158 if (undobuf.other_insn)
2159 reset_used_flags (PATTERN (undobuf.other_insn));
2161 i3notes = copy_rtx_if_shared (i3notes);
2162 i2notes = copy_rtx_if_shared (i2notes);
2163 i1notes = copy_rtx_if_shared (i1notes);
2164 newpat = copy_rtx_if_shared (newpat);
2165 newi2pat = copy_rtx_if_shared (newi2pat);
2166 if (undobuf.other_insn)
2167 reset_used_flags (PATTERN (undobuf.other_insn));
2169 INSN_CODE (i3) = insn_code_number;
2170 PATTERN (i3) = newpat;
2171 if (undobuf.other_insn)
2172 INSN_CODE (undobuf.other_insn) = other_code_number;
2174 /* We had one special case above where I2 had more than one set and
2175 we replaced a destination of one of those sets with the destination
2176 of I3. In that case, we have to update LOG_LINKS of insns later
2177 in this basic block. Note that this (expensive) case is rare.
2179 Also, in this case, we must pretend that all REG_NOTEs for I2
2180 actually came from I3, so that REG_UNUSED notes from I2 will be
2181 properly handled. */
2183 if (i3_subst_into_i2)
2185 for (i = 0; i < XVECLEN (PATTERN (i2), 0); i++)
2186 if (GET_CODE (SET_DEST (XVECEXP (PATTERN (i2), 0, i))) == REG
2187 && SET_DEST (XVECEXP (PATTERN (i2), 0, i)) != i2dest
2188 && ! find_reg_note (i2, REG_UNUSED,
2189 SET_DEST (XVECEXP (PATTERN (i2), 0, i))))
2190 for (temp = NEXT_INSN (i2);
2191 temp && (this_basic_block == n_basic_blocks - 1
2192 || basic_block_head[this_basic_block] != temp);
2193 temp = NEXT_INSN (temp))
2194 if (temp != i3 && GET_RTX_CLASS (GET_CODE (temp)) == 'i')
2195 for (link = LOG_LINKS (temp); link; link = XEXP (link, 1))
2196 if (XEXP (link, 0) == i2)
2197 XEXP (link, 0) = i3;
2202 while (XEXP (link, 1))
2203 link = XEXP (link, 1);
2204 XEXP (link, 1) = i2notes;
2218 INSN_CODE (i2) = i2_code_number;
2219 PATTERN (i2) = newi2pat;
2223 PUT_CODE (i2, NOTE);
2224 NOTE_LINE_NUMBER (i2) = NOTE_INSN_DELETED;
2225 NOTE_SOURCE_FILE (i2) = 0;
2232 PUT_CODE (i1, NOTE);
2233 NOTE_LINE_NUMBER (i1) = NOTE_INSN_DELETED;
2234 NOTE_SOURCE_FILE (i1) = 0;
2237 /* Get death notes for everything that is now used in either I3 or
2238 I2 and used to die in a previous insn. If we built two new
2239 patterns, move from I1 to I2 then I2 to I3 so that we get the
2240 proper movement on registers that I2 modifies. */
2244 move_deaths (newi2pat, NULL_RTX, INSN_CUID (i1), i2, &midnotes);
2245 move_deaths (newpat, newi2pat, INSN_CUID (i1), i3, &midnotes);
2248 move_deaths (newpat, NULL_RTX, i1 ? INSN_CUID (i1) : INSN_CUID (i2),
2251 /* Distribute all the LOG_LINKS and REG_NOTES from I1, I2, and I3. */
2253 distribute_notes (i3notes, i3, i3, newi2pat ? i2 : NULL_RTX,
2256 distribute_notes (i2notes, i2, i3, newi2pat ? i2 : NULL_RTX,
2259 distribute_notes (i1notes, i1, i3, newi2pat ? i2 : NULL_RTX,
2262 distribute_notes (midnotes, NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
2265 /* Distribute any notes added to I2 or I3 by recog_for_combine. We
2266 know these are REG_UNUSED and want them to go to the desired insn,
2267 so we always pass it as i3. We have not counted the notes in
2268 reg_n_deaths yet, so we need to do so now. */
2270 if (newi2pat && new_i2_notes)
2272 for (temp = new_i2_notes; temp; temp = XEXP (temp, 1))
2273 if (GET_CODE (XEXP (temp, 0)) == REG)
2274 REG_N_DEATHS (REGNO (XEXP (temp, 0)))++;
2276 distribute_notes (new_i2_notes, i2, i2, NULL_RTX, NULL_RTX, NULL_RTX);
2281 for (temp = new_i3_notes; temp; temp = XEXP (temp, 1))
2282 if (GET_CODE (XEXP (temp, 0)) == REG)
2283 REG_N_DEATHS (REGNO (XEXP (temp, 0)))++;
2285 distribute_notes (new_i3_notes, i3, i3, NULL_RTX, NULL_RTX, NULL_RTX);
2288 /* If I3DEST was used in I3SRC, it really died in I3. We may need to
2289 put a REG_DEAD note for it somewhere. Similarly for I2 and I1.
2290 Show an additional death due to the REG_DEAD note we make here. If
2291 we discard it in distribute_notes, we will decrement it again. */
2295 if (GET_CODE (i3dest_killed) == REG)
2296 REG_N_DEATHS (REGNO (i3dest_killed))++;
2298 distribute_notes (gen_rtx (EXPR_LIST, REG_DEAD, i3dest_killed,
2300 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
2301 NULL_RTX, NULL_RTX);
2304 /* For I2 and I1, we have to be careful. If NEWI2PAT exists and sets
2305 I2DEST or I1DEST, the death must be somewhere before I2, not I3. If
2306 we passed I3 in that case, it might delete I2. */
2308 if (i2dest_in_i2src)
2310 if (GET_CODE (i2dest) == REG)
2311 REG_N_DEATHS (REGNO (i2dest))++;
2313 if (newi2pat && reg_set_p (i2dest, newi2pat))
2314 distribute_notes (gen_rtx (EXPR_LIST, REG_DEAD, i2dest, NULL_RTX),
2315 NULL_RTX, i2, NULL_RTX, NULL_RTX, NULL_RTX);
2317 distribute_notes (gen_rtx (EXPR_LIST, REG_DEAD, i2dest, NULL_RTX),
2318 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
2319 NULL_RTX, NULL_RTX);
2322 if (i1dest_in_i1src)
2324 if (GET_CODE (i1dest) == REG)
2325 REG_N_DEATHS (REGNO (i1dest))++;
2327 if (newi2pat && reg_set_p (i1dest, newi2pat))
2328 distribute_notes (gen_rtx (EXPR_LIST, REG_DEAD, i1dest, NULL_RTX),
2329 NULL_RTX, i2, NULL_RTX, NULL_RTX, NULL_RTX);
2331 distribute_notes (gen_rtx (EXPR_LIST, REG_DEAD, i1dest, NULL_RTX),
2332 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
2333 NULL_RTX, NULL_RTX);
2336 distribute_links (i3links);
2337 distribute_links (i2links);
2338 distribute_links (i1links);
2340 if (GET_CODE (i2dest) == REG)
2343 rtx i2_insn = 0, i2_val = 0, set;
2345 /* The insn that used to set this register doesn't exist, and
2346 this life of the register may not exist either. See if one of
2347 I3's links points to an insn that sets I2DEST. If it does,
2348 that is now the last known value for I2DEST. If we don't update
2349 this and I2 set the register to a value that depended on its old
2350 contents, we will get confused. If this insn is used, thing
2351 will be set correctly in combine_instructions. */
2353 for (link = LOG_LINKS (i3); link; link = XEXP (link, 1))
2354 if ((set = single_set (XEXP (link, 0))) != 0
2355 && rtx_equal_p (i2dest, SET_DEST (set)))
2356 i2_insn = XEXP (link, 0), i2_val = SET_SRC (set);
2358 record_value_for_reg (i2dest, i2_insn, i2_val);
2360 /* If the reg formerly set in I2 died only once and that was in I3,
2361 zero its use count so it won't make `reload' do any work. */
2363 && (newi2pat == 0 || ! reg_mentioned_p (i2dest, newi2pat))
2364 && ! i2dest_in_i2src)
2366 regno = REGNO (i2dest);
2367 REG_N_SETS (regno)--;
2368 if (REG_N_SETS (regno) == 0
2369 && ! REGNO_REG_SET_P (basic_block_live_at_start[0], regno))
2370 REG_N_REFS (regno) = 0;
2374 if (i1 && GET_CODE (i1dest) == REG)
2377 rtx i1_insn = 0, i1_val = 0, set;
2379 for (link = LOG_LINKS (i3); link; link = XEXP (link, 1))
2380 if ((set = single_set (XEXP (link, 0))) != 0
2381 && rtx_equal_p (i1dest, SET_DEST (set)))
2382 i1_insn = XEXP (link, 0), i1_val = SET_SRC (set);
2384 record_value_for_reg (i1dest, i1_insn, i1_val);
2386 regno = REGNO (i1dest);
2387 if (! added_sets_1 && ! i1dest_in_i1src)
2389 REG_N_SETS (regno)--;
2390 if (REG_N_SETS (regno) == 0
2391 && ! REGNO_REG_SET_P (basic_block_live_at_start[0], regno))
2392 REG_N_REFS (regno) = 0;
2396 /* Update reg_nonzero_bits et al for any changes that may have been made
2399 note_stores (newpat, set_nonzero_bits_and_sign_copies);
2401 note_stores (newi2pat, set_nonzero_bits_and_sign_copies);
2403 /* If we added any (clobber (scratch)), add them to the max for a
2404 block. This is a very pessimistic calculation, since we might
2405 have had them already and this might not be the worst block, but
2406 it's not worth doing any better. */
2407 max_scratch += i3_scratches + i2_scratches + other_scratches;
2409 /* If I3 is now an unconditional jump, ensure that it has a
2410 BARRIER following it since it may have initially been a
2411 conditional jump. It may also be the last nonnote insn. */
2413 if ((GET_CODE (newpat) == RETURN || simplejump_p (i3))
2414 && ((temp = next_nonnote_insn (i3)) == NULL_RTX
2415 || GET_CODE (temp) != BARRIER))
2416 emit_barrier_after (i3);
2419 combine_successes++;
2421 /* Clear this here, so that subsequent get_last_value calls are not
2423 subst_prev_insn = NULL_RTX;
2425 if (added_links_insn
2426 && (newi2pat == 0 || INSN_CUID (added_links_insn) < INSN_CUID (i2))
2427 && INSN_CUID (added_links_insn) < INSN_CUID (i3))
2428 return added_links_insn;
2430 return newi2pat ? i2 : i3;
2433 /* Undo all the modifications recorded in undobuf. */
2438 struct undo *undo, *next;
2440 for (undo = undobuf.undos; undo; undo = next)
2444 *undo->where.i = undo->old_contents.i;
2446 *undo->where.r = undo->old_contents.r;
2448 undo->next = undobuf.frees;
2449 undobuf.frees = undo;
2452 obfree (undobuf.storage);
2453 undobuf.undos = undobuf.previous_undos = 0;
2455 /* Clear this here, so that subsequent get_last_value calls are not
2457 subst_prev_insn = NULL_RTX;
2460 /* Find the innermost point within the rtx at LOC, possibly LOC itself,
2461 where we have an arithmetic expression and return that point. LOC will
2464 try_combine will call this function to see if an insn can be split into
2468 find_split_point (loc, insn)
2473 enum rtx_code code = GET_CODE (x);
2475 int len = 0, pos, unsignedp;
2478 /* First special-case some codes. */
2482 #ifdef INSN_SCHEDULING
2483 /* If we are making a paradoxical SUBREG invalid, it becomes a split
2485 if (GET_CODE (SUBREG_REG (x)) == MEM)
2488 return find_split_point (&SUBREG_REG (x), insn);
2492 /* If we have (mem (const ..)) or (mem (symbol_ref ...)), split it
2493 using LO_SUM and HIGH. */
2494 if (GET_CODE (XEXP (x, 0)) == CONST
2495 || GET_CODE (XEXP (x, 0)) == SYMBOL_REF)
2498 gen_rtx_combine (LO_SUM, Pmode,
2499 gen_rtx_combine (HIGH, Pmode, XEXP (x, 0)),
2501 return &XEXP (XEXP (x, 0), 0);
2505 /* If we have a PLUS whose second operand is a constant and the
2506 address is not valid, perhaps will can split it up using
2507 the machine-specific way to split large constants. We use
2508 the first pseudo-reg (one of the virtual regs) as a placeholder;
2509 it will not remain in the result. */
2510 if (GET_CODE (XEXP (x, 0)) == PLUS
2511 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
2512 && ! memory_address_p (GET_MODE (x), XEXP (x, 0)))
2514 rtx reg = regno_reg_rtx[FIRST_PSEUDO_REGISTER];
2515 rtx seq = split_insns (gen_rtx (SET, VOIDmode, reg, XEXP (x, 0)),
2518 /* This should have produced two insns, each of which sets our
2519 placeholder. If the source of the second is a valid address,
2520 we can make put both sources together and make a split point
2523 if (seq && XVECLEN (seq, 0) == 2
2524 && GET_CODE (XVECEXP (seq, 0, 0)) == INSN
2525 && GET_CODE (PATTERN (XVECEXP (seq, 0, 0))) == SET
2526 && SET_DEST (PATTERN (XVECEXP (seq, 0, 0))) == reg
2527 && ! reg_mentioned_p (reg,
2528 SET_SRC (PATTERN (XVECEXP (seq, 0, 0))))
2529 && GET_CODE (XVECEXP (seq, 0, 1)) == INSN
2530 && GET_CODE (PATTERN (XVECEXP (seq, 0, 1))) == SET
2531 && SET_DEST (PATTERN (XVECEXP (seq, 0, 1))) == reg
2532 && memory_address_p (GET_MODE (x),
2533 SET_SRC (PATTERN (XVECEXP (seq, 0, 1)))))
2535 rtx src1 = SET_SRC (PATTERN (XVECEXP (seq, 0, 0)));
2536 rtx src2 = SET_SRC (PATTERN (XVECEXP (seq, 0, 1)));
2538 /* Replace the placeholder in SRC2 with SRC1. If we can
2539 find where in SRC2 it was placed, that can become our
2540 split point and we can replace this address with SRC2.
2541 Just try two obvious places. */
2543 src2 = replace_rtx (src2, reg, src1);
2545 if (XEXP (src2, 0) == src1)
2546 split = &XEXP (src2, 0);
2547 else if (GET_RTX_FORMAT (GET_CODE (XEXP (src2, 0)))[0] == 'e'
2548 && XEXP (XEXP (src2, 0), 0) == src1)
2549 split = &XEXP (XEXP (src2, 0), 0);
2553 SUBST (XEXP (x, 0), src2);
2558 /* If that didn't work, perhaps the first operand is complex and
2559 needs to be computed separately, so make a split point there.
2560 This will occur on machines that just support REG + CONST
2561 and have a constant moved through some previous computation. */
2563 else if (GET_RTX_CLASS (GET_CODE (XEXP (XEXP (x, 0), 0))) != 'o'
2564 && ! (GET_CODE (XEXP (XEXP (x, 0), 0)) == SUBREG
2565 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (XEXP (x, 0), 0))))
2567 return &XEXP (XEXP (x, 0), 0);
2573 /* If SET_DEST is CC0 and SET_SRC is not an operand, a COMPARE, or a
2574 ZERO_EXTRACT, the most likely reason why this doesn't match is that
2575 we need to put the operand into a register. So split at that
2578 if (SET_DEST (x) == cc0_rtx
2579 && GET_CODE (SET_SRC (x)) != COMPARE
2580 && GET_CODE (SET_SRC (x)) != ZERO_EXTRACT
2581 && GET_RTX_CLASS (GET_CODE (SET_SRC (x))) != 'o'
2582 && ! (GET_CODE (SET_SRC (x)) == SUBREG
2583 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (SET_SRC (x)))) == 'o'))
2584 return &SET_SRC (x);
2587 /* See if we can split SET_SRC as it stands. */
2588 split = find_split_point (&SET_SRC (x), insn);
2589 if (split && split != &SET_SRC (x))
2592 /* See if we can split SET_DEST as it stands. */
2593 split = find_split_point (&SET_DEST (x), insn);
2594 if (split && split != &SET_DEST (x))
2597 /* See if this is a bitfield assignment with everything constant. If
2598 so, this is an IOR of an AND, so split it into that. */
2599 if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
2600 && (GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0)))
2601 <= HOST_BITS_PER_WIDE_INT)
2602 && GET_CODE (XEXP (SET_DEST (x), 1)) == CONST_INT
2603 && GET_CODE (XEXP (SET_DEST (x), 2)) == CONST_INT
2604 && GET_CODE (SET_SRC (x)) == CONST_INT
2605 && ((INTVAL (XEXP (SET_DEST (x), 1))
2606 + INTVAL (XEXP (SET_DEST (x), 2)))
2607 <= GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0))))
2608 && ! side_effects_p (XEXP (SET_DEST (x), 0)))
2610 int pos = INTVAL (XEXP (SET_DEST (x), 2));
2611 int len = INTVAL (XEXP (SET_DEST (x), 1));
2612 int src = INTVAL (SET_SRC (x));
2613 rtx dest = XEXP (SET_DEST (x), 0);
2614 enum machine_mode mode = GET_MODE (dest);
2615 unsigned HOST_WIDE_INT mask = ((HOST_WIDE_INT) 1 << len) - 1;
2617 if (BITS_BIG_ENDIAN)
2618 pos = GET_MODE_BITSIZE (mode) - len - pos;
2622 gen_binary (IOR, mode, dest, GEN_INT (src << pos)));
2625 gen_binary (IOR, mode,
2626 gen_binary (AND, mode, dest,
2627 GEN_INT (~ (mask << pos)
2628 & GET_MODE_MASK (mode))),
2629 GEN_INT (src << pos)));
2631 SUBST (SET_DEST (x), dest);
2633 split = find_split_point (&SET_SRC (x), insn);
2634 if (split && split != &SET_SRC (x))
2638 /* Otherwise, see if this is an operation that we can split into two.
2639 If so, try to split that. */
2640 code = GET_CODE (SET_SRC (x));
2645 /* If we are AND'ing with a large constant that is only a single
2646 bit and the result is only being used in a context where we
2647 need to know if it is zero or non-zero, replace it with a bit
2648 extraction. This will avoid the large constant, which might
2649 have taken more than one insn to make. If the constant were
2650 not a valid argument to the AND but took only one insn to make,
2651 this is no worse, but if it took more than one insn, it will
2654 if (GET_CODE (XEXP (SET_SRC (x), 1)) == CONST_INT
2655 && GET_CODE (XEXP (SET_SRC (x), 0)) == REG
2656 && (pos = exact_log2 (INTVAL (XEXP (SET_SRC (x), 1)))) >= 7
2657 && GET_CODE (SET_DEST (x)) == REG
2658 && (split = find_single_use (SET_DEST (x), insn, NULL_PTR)) != 0
2659 && (GET_CODE (*split) == EQ || GET_CODE (*split) == NE)
2660 && XEXP (*split, 0) == SET_DEST (x)
2661 && XEXP (*split, 1) == const0_rtx)
2663 rtx extraction = make_extraction (GET_MODE (SET_DEST (x)),
2664 XEXP (SET_SRC (x), 0),
2665 pos, NULL_RTX, 1, 1, 0, 0);
2666 if (extraction != 0)
2668 SUBST (SET_SRC (x), extraction);
2669 return find_split_point (loc, insn);
2675 /* if STORE_FLAG_VALUE is -1, this is (NE X 0) and only one bit of X
2676 is known to be on, this can be converted into a NEG of a shift. */
2677 if (STORE_FLAG_VALUE == -1 && XEXP (SET_SRC (x), 1) == const0_rtx
2678 && GET_MODE (SET_SRC (x)) == GET_MODE (XEXP (SET_SRC (x), 0))
2679 && 1 <= (pos = exact_log2
2680 (nonzero_bits (XEXP (SET_SRC (x), 0),
2681 GET_MODE (XEXP (SET_SRC (x), 0))))))
2683 enum machine_mode mode = GET_MODE (XEXP (SET_SRC (x), 0));
2686 gen_rtx_combine (NEG, mode,
2687 gen_rtx_combine (LSHIFTRT, mode,
2688 XEXP (SET_SRC (x), 0),
2691 split = find_split_point (&SET_SRC (x), insn);
2692 if (split && split != &SET_SRC (x))
2698 inner = XEXP (SET_SRC (x), 0);
2700 /* We can't optimize if either mode is a partial integer
2701 mode as we don't know how many bits are significant
2703 if (GET_MODE_CLASS (GET_MODE (inner)) == MODE_PARTIAL_INT
2704 || GET_MODE_CLASS (GET_MODE (SET_SRC (x))) == MODE_PARTIAL_INT)
2708 len = GET_MODE_BITSIZE (GET_MODE (inner));
2714 if (GET_CODE (XEXP (SET_SRC (x), 1)) == CONST_INT
2715 && GET_CODE (XEXP (SET_SRC (x), 2)) == CONST_INT)
2717 inner = XEXP (SET_SRC (x), 0);
2718 len = INTVAL (XEXP (SET_SRC (x), 1));
2719 pos = INTVAL (XEXP (SET_SRC (x), 2));
2721 if (BITS_BIG_ENDIAN)
2722 pos = GET_MODE_BITSIZE (GET_MODE (inner)) - len - pos;
2723 unsignedp = (code == ZERO_EXTRACT);
2728 if (len && pos >= 0 && pos + len <= GET_MODE_BITSIZE (GET_MODE (inner)))
2730 enum machine_mode mode = GET_MODE (SET_SRC (x));
2732 /* For unsigned, we have a choice of a shift followed by an
2733 AND or two shifts. Use two shifts for field sizes where the
2734 constant might be too large. We assume here that we can
2735 always at least get 8-bit constants in an AND insn, which is
2736 true for every current RISC. */
2738 if (unsignedp && len <= 8)
2743 gen_rtx_combine (LSHIFTRT, mode,
2744 gen_lowpart_for_combine (mode, inner),
2746 GEN_INT (((HOST_WIDE_INT) 1 << len) - 1)));
2748 split = find_split_point (&SET_SRC (x), insn);
2749 if (split && split != &SET_SRC (x))
2756 (unsignedp ? LSHIFTRT : ASHIFTRT, mode,
2757 gen_rtx_combine (ASHIFT, mode,
2758 gen_lowpart_for_combine (mode, inner),
2759 GEN_INT (GET_MODE_BITSIZE (mode)
2761 GEN_INT (GET_MODE_BITSIZE (mode) - len)));
2763 split = find_split_point (&SET_SRC (x), insn);
2764 if (split && split != &SET_SRC (x))
2769 /* See if this is a simple operation with a constant as the second
2770 operand. It might be that this constant is out of range and hence
2771 could be used as a split point. */
2772 if ((GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '2'
2773 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == 'c'
2774 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '<')
2775 && CONSTANT_P (XEXP (SET_SRC (x), 1))
2776 && (GET_RTX_CLASS (GET_CODE (XEXP (SET_SRC (x), 0))) == 'o'
2777 || (GET_CODE (XEXP (SET_SRC (x), 0)) == SUBREG
2778 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (SET_SRC (x), 0))))
2780 return &XEXP (SET_SRC (x), 1);
2782 /* Finally, see if this is a simple operation with its first operand
2783 not in a register. The operation might require this operand in a
2784 register, so return it as a split point. We can always do this
2785 because if the first operand were another operation, we would have
2786 already found it as a split point. */
2787 if ((GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '2'
2788 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == 'c'
2789 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '<'
2790 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '1')
2791 && ! register_operand (XEXP (SET_SRC (x), 0), VOIDmode))
2792 return &XEXP (SET_SRC (x), 0);
2798 /* We write NOR as (and (not A) (not B)), but if we don't have a NOR,
2799 it is better to write this as (not (ior A B)) so we can split it.
2800 Similarly for IOR. */
2801 if (GET_CODE (XEXP (x, 0)) == NOT && GET_CODE (XEXP (x, 1)) == NOT)
2804 gen_rtx_combine (NOT, GET_MODE (x),
2805 gen_rtx_combine (code == IOR ? AND : IOR,
2807 XEXP (XEXP (x, 0), 0),
2808 XEXP (XEXP (x, 1), 0))));
2809 return find_split_point (loc, insn);
2812 /* Many RISC machines have a large set of logical insns. If the
2813 second operand is a NOT, put it first so we will try to split the
2814 other operand first. */
2815 if (GET_CODE (XEXP (x, 1)) == NOT)
2817 rtx tem = XEXP (x, 0);
2818 SUBST (XEXP (x, 0), XEXP (x, 1));
2819 SUBST (XEXP (x, 1), tem);
2824 /* Otherwise, select our actions depending on our rtx class. */
2825 switch (GET_RTX_CLASS (code))
2827 case 'b': /* This is ZERO_EXTRACT and SIGN_EXTRACT. */
2829 split = find_split_point (&XEXP (x, 2), insn);
2832 /* ... fall through ... */
2836 split = find_split_point (&XEXP (x, 1), insn);
2839 /* ... fall through ... */
2841 /* Some machines have (and (shift ...) ...) insns. If X is not
2842 an AND, but XEXP (X, 0) is, use it as our split point. */
2843 if (GET_CODE (x) != AND && GET_CODE (XEXP (x, 0)) == AND)
2844 return &XEXP (x, 0);
2846 split = find_split_point (&XEXP (x, 0), insn);
2852 /* Otherwise, we don't have a split point. */
2856 /* Throughout X, replace FROM with TO, and return the result.
2857 The result is TO if X is FROM;
2858 otherwise the result is X, but its contents may have been modified.
2859 If they were modified, a record was made in undobuf so that
2860 undo_all will (among other things) return X to its original state.
2862 If the number of changes necessary is too much to record to undo,
2863 the excess changes are not made, so the result is invalid.
2864 The changes already made can still be undone.
2865 undobuf.num_undo is incremented for such changes, so by testing that
2866 the caller can tell whether the result is valid.
2868 `n_occurrences' is incremented each time FROM is replaced.
2870 IN_DEST is non-zero if we are processing the SET_DEST of a SET.
2872 UNIQUE_COPY is non-zero if each substitution must be unique. We do this
2873 by copying if `n_occurrences' is non-zero. */
2876 subst (x, from, to, in_dest, unique_copy)
2877 register rtx x, from, to;
2881 register enum rtx_code code = GET_CODE (x);
2882 enum machine_mode op0_mode = VOIDmode;
2884 register int len, i;
2887 /* Two expressions are equal if they are identical copies of a shared
2888 RTX or if they are both registers with the same register number
2891 #define COMBINE_RTX_EQUAL_P(X,Y) \
2893 || (GET_CODE (X) == REG && GET_CODE (Y) == REG \
2894 && REGNO (X) == REGNO (Y) && GET_MODE (X) == GET_MODE (Y)))
2896 if (! in_dest && COMBINE_RTX_EQUAL_P (x, from))
2899 return (unique_copy && n_occurrences > 1 ? copy_rtx (to) : to);
2902 /* If X and FROM are the same register but different modes, they will
2903 not have been seen as equal above. However, flow.c will make a
2904 LOG_LINKS entry for that case. If we do nothing, we will try to
2905 rerecognize our original insn and, when it succeeds, we will
2906 delete the feeding insn, which is incorrect.
2908 So force this insn not to match in this (rare) case. */
2909 if (! in_dest && code == REG && GET_CODE (from) == REG
2910 && REGNO (x) == REGNO (from))
2911 return gen_rtx (CLOBBER, GET_MODE (x), const0_rtx);
2913 /* If this is an object, we are done unless it is a MEM or LO_SUM, both
2914 of which may contain things that can be combined. */
2915 if (code != MEM && code != LO_SUM && GET_RTX_CLASS (code) == 'o')
2918 /* It is possible to have a subexpression appear twice in the insn.
2919 Suppose that FROM is a register that appears within TO.
2920 Then, after that subexpression has been scanned once by `subst',
2921 the second time it is scanned, TO may be found. If we were
2922 to scan TO here, we would find FROM within it and create a
2923 self-referent rtl structure which is completely wrong. */
2924 if (COMBINE_RTX_EQUAL_P (x, to))
2927 len = GET_RTX_LENGTH (code);
2928 fmt = GET_RTX_FORMAT (code);
2930 /* We don't need to process a SET_DEST that is a register, CC0, or PC, so
2931 set up to skip this common case. All other cases where we want to
2932 suppress replacing something inside a SET_SRC are handled via the
2935 && (GET_CODE (SET_DEST (x)) == REG
2936 || GET_CODE (SET_DEST (x)) == CC0
2937 || GET_CODE (SET_DEST (x)) == PC))
2940 /* Get the mode of operand 0 in case X is now a SIGN_EXTEND of a
2943 op0_mode = GET_MODE (XEXP (x, 0));
2945 for (i = 0; i < len; i++)
2950 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
2952 if (COMBINE_RTX_EQUAL_P (XVECEXP (x, i, j), from))
2954 new = (unique_copy && n_occurrences ? copy_rtx (to) : to);
2959 new = subst (XVECEXP (x, i, j), from, to, 0, unique_copy);
2961 /* If this substitution failed, this whole thing fails. */
2962 if (GET_CODE (new) == CLOBBER && XEXP (new, 0) == const0_rtx)
2966 SUBST (XVECEXP (x, i, j), new);
2969 else if (fmt[i] == 'e')
2971 if (COMBINE_RTX_EQUAL_P (XEXP (x, i), from))
2973 /* In general, don't install a subreg involving two modes not
2974 tieable. It can worsen register allocation, and can even
2975 make invalid reload insns, since the reg inside may need to
2976 be copied from in the outside mode, and that may be invalid
2977 if it is an fp reg copied in integer mode.
2979 We allow two exceptions to this: It is valid if it is inside
2980 another SUBREG and the mode of that SUBREG and the mode of
2981 the inside of TO is tieable and it is valid if X is a SET
2982 that copies FROM to CC0. */
2983 if (GET_CODE (to) == SUBREG
2984 && ! MODES_TIEABLE_P (GET_MODE (to),
2985 GET_MODE (SUBREG_REG (to)))
2986 && ! (code == SUBREG
2987 && MODES_TIEABLE_P (GET_MODE (x),
2988 GET_MODE (SUBREG_REG (to))))
2990 && ! (code == SET && i == 1 && XEXP (x, 0) == cc0_rtx)
2993 return gen_rtx (CLOBBER, VOIDmode, const0_rtx);
2995 new = (unique_copy && n_occurrences ? copy_rtx (to) : to);
2999 /* If we are in a SET_DEST, suppress most cases unless we
3000 have gone inside a MEM, in which case we want to
3001 simplify the address. We assume here that things that
3002 are actually part of the destination have their inner
3003 parts in the first expression. This is true for SUBREG,
3004 STRICT_LOW_PART, and ZERO_EXTRACT, which are the only
3005 things aside from REG and MEM that should appear in a
3007 new = subst (XEXP (x, i), from, to,
3009 && (code == SUBREG || code == STRICT_LOW_PART
3010 || code == ZERO_EXTRACT))
3012 && i == 0), unique_copy);
3014 /* If we found that we will have to reject this combination,
3015 indicate that by returning the CLOBBER ourselves, rather than
3016 an expression containing it. This will speed things up as
3017 well as prevent accidents where two CLOBBERs are considered
3018 to be equal, thus producing an incorrect simplification. */
3020 if (GET_CODE (new) == CLOBBER && XEXP (new, 0) == const0_rtx)
3023 SUBST (XEXP (x, i), new);
3027 /* Try to simplify X. If the simplification changed the code, it is likely
3028 that further simplification will help, so loop, but limit the number
3029 of repetitions that will be performed. */
3031 for (i = 0; i < 4; i++)
3033 /* If X is sufficiently simple, don't bother trying to do anything
3035 if (code != CONST_INT && code != REG && code != CLOBBER)
3036 x = simplify_rtx (x, op0_mode, i == 3, in_dest);
3038 if (GET_CODE (x) == code)
3041 code = GET_CODE (x);
3043 /* We no longer know the original mode of operand 0 since we
3044 have changed the form of X) */
3045 op0_mode = VOIDmode;
3051 /* Simplify X, a piece of RTL. We just operate on the expression at the
3052 outer level; call `subst' to simplify recursively. Return the new
3055 OP0_MODE is the original mode of XEXP (x, 0); LAST is nonzero if this
3056 will be the iteration even if an expression with a code different from
3057 X is returned; IN_DEST is nonzero if we are inside a SET_DEST. */
3060 simplify_rtx (x, op0_mode, last, in_dest)
3062 enum machine_mode op0_mode;
3066 enum rtx_code code = GET_CODE (x);
3067 enum machine_mode mode = GET_MODE (x);
3071 /* If this is a commutative operation, put a constant last and a complex
3072 expression first. We don't need to do this for comparisons here. */
3073 if (GET_RTX_CLASS (code) == 'c'
3074 && ((CONSTANT_P (XEXP (x, 0)) && GET_CODE (XEXP (x, 1)) != CONST_INT)
3075 || (GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == 'o'
3076 && GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) != 'o')
3077 || (GET_CODE (XEXP (x, 0)) == SUBREG
3078 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 0)))) == 'o'
3079 && GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) != 'o')))
3082 SUBST (XEXP (x, 0), XEXP (x, 1));
3083 SUBST (XEXP (x, 1), temp);
3086 /* If this is a PLUS, MINUS, or MULT, and the first operand is the
3087 sign extension of a PLUS with a constant, reverse the order of the sign
3088 extension and the addition. Note that this not the same as the original
3089 code, but overflow is undefined for signed values. Also note that the
3090 PLUS will have been partially moved "inside" the sign-extension, so that
3091 the first operand of X will really look like:
3092 (ashiftrt (plus (ashift A C4) C5) C4).
3094 (plus (ashiftrt (ashift A C4) C2) C4)
3095 and replace the first operand of X with that expression. Later parts
3096 of this function may simplify the expression further.
3098 For example, if we start with (mult (sign_extend (plus A C1)) C2),
3099 we swap the SIGN_EXTEND and PLUS. Later code will apply the
3100 distributive law to produce (plus (mult (sign_extend X) C1) C3).
3102 We do this to simplify address expressions. */
3104 if ((code == PLUS || code == MINUS || code == MULT)
3105 && GET_CODE (XEXP (x, 0)) == ASHIFTRT
3106 && GET_CODE (XEXP (XEXP (x, 0), 0)) == PLUS
3107 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == ASHIFT
3108 && GET_CODE (XEXP (XEXP (XEXP (XEXP (x, 0), 0), 0), 1)) == CONST_INT
3109 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3110 && XEXP (XEXP (XEXP (XEXP (x, 0), 0), 0), 1) == XEXP (XEXP (x, 0), 1)
3111 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == CONST_INT
3112 && (temp = simplify_binary_operation (ASHIFTRT, mode,
3113 XEXP (XEXP (XEXP (x, 0), 0), 1),
3114 XEXP (XEXP (x, 0), 1))) != 0)
3117 = simplify_shift_const (NULL_RTX, ASHIFT, mode,
3118 XEXP (XEXP (XEXP (XEXP (x, 0), 0), 0), 0),
3119 INTVAL (XEXP (XEXP (x, 0), 1)));
3121 new = simplify_shift_const (NULL_RTX, ASHIFTRT, mode, new,
3122 INTVAL (XEXP (XEXP (x, 0), 1)));
3124 SUBST (XEXP (x, 0), gen_binary (PLUS, mode, new, temp));
3127 /* If this is a simple operation applied to an IF_THEN_ELSE, try
3128 applying it to the arms of the IF_THEN_ELSE. This often simplifies
3129 things. Check for cases where both arms are testing the same
3132 Don't do anything if all operands are very simple. */
3134 if (((GET_RTX_CLASS (code) == '2' || GET_RTX_CLASS (code) == 'c'
3135 || GET_RTX_CLASS (code) == '<')
3136 && ((GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) != 'o'
3137 && ! (GET_CODE (XEXP (x, 0)) == SUBREG
3138 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 0))))
3140 || (GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) != 'o'
3141 && ! (GET_CODE (XEXP (x, 1)) == SUBREG
3142 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 1))))
3144 || (GET_RTX_CLASS (code) == '1'
3145 && ((GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) != 'o'
3146 && ! (GET_CODE (XEXP (x, 0)) == SUBREG
3147 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 0))))
3150 rtx cond, true, false;
3152 cond = if_then_else_cond (x, &true, &false);
3154 /* If everything is a comparison, what we have is highly unlikely
3155 to be simpler, so don't use it. */
3156 && ! (GET_RTX_CLASS (code) == '<'
3157 && (GET_RTX_CLASS (GET_CODE (true)) == '<'
3158 || GET_RTX_CLASS (GET_CODE (false)) == '<')))
3160 rtx cop1 = const0_rtx;
3161 enum rtx_code cond_code = simplify_comparison (NE, &cond, &cop1);
3163 if (cond_code == NE && GET_RTX_CLASS (GET_CODE (cond)) == '<')
3166 /* Simplify the alternative arms; this may collapse the true and
3167 false arms to store-flag values. */
3168 true = subst (true, pc_rtx, pc_rtx, 0, 0);
3169 false = subst (false, pc_rtx, pc_rtx, 0, 0);
3171 /* Restarting if we generate a store-flag expression will cause
3172 us to loop. Just drop through in this case. */
3174 /* If the result values are STORE_FLAG_VALUE and zero, we can
3175 just make the comparison operation. */
3176 if (true == const_true_rtx && false == const0_rtx)
3177 x = gen_binary (cond_code, mode, cond, cop1);
3178 else if (true == const0_rtx && false == const_true_rtx)
3179 x = gen_binary (reverse_condition (cond_code), mode, cond, cop1);
3181 /* Likewise, we can make the negate of a comparison operation
3182 if the result values are - STORE_FLAG_VALUE and zero. */
3183 else if (GET_CODE (true) == CONST_INT
3184 && INTVAL (true) == - STORE_FLAG_VALUE
3185 && false == const0_rtx)
3186 x = gen_unary (NEG, mode, mode,
3187 gen_binary (cond_code, mode, cond, cop1));
3188 else if (GET_CODE (false) == CONST_INT
3189 && INTVAL (false) == - STORE_FLAG_VALUE
3190 && true == const0_rtx)
3191 x = gen_unary (NEG, mode, mode,
3192 gen_binary (reverse_condition (cond_code),
3195 return gen_rtx (IF_THEN_ELSE, mode,
3196 gen_binary (cond_code, VOIDmode, cond, cop1),
3199 code = GET_CODE (x);
3200 op0_mode = VOIDmode;
3204 /* Try to fold this expression in case we have constants that weren't
3207 switch (GET_RTX_CLASS (code))
3210 temp = simplify_unary_operation (code, mode, XEXP (x, 0), op0_mode);
3213 temp = simplify_relational_operation (code, op0_mode,
3214 XEXP (x, 0), XEXP (x, 1));
3215 #ifdef FLOAT_STORE_FLAG_VALUE
3216 if (temp != 0 && GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
3217 temp = ((temp == const0_rtx) ? CONST0_RTX (GET_MODE (x))
3218 : immed_real_const_1 (FLOAT_STORE_FLAG_VALUE, GET_MODE (x)));
3223 temp = simplify_binary_operation (code, mode, XEXP (x, 0), XEXP (x, 1));
3227 temp = simplify_ternary_operation (code, mode, op0_mode, XEXP (x, 0),
3228 XEXP (x, 1), XEXP (x, 2));
3233 x = temp, code = GET_CODE (temp);
3235 /* First see if we can apply the inverse distributive law. */
3236 if (code == PLUS || code == MINUS
3237 || code == AND || code == IOR || code == XOR)
3239 x = apply_distributive_law (x);
3240 code = GET_CODE (x);
3243 /* If CODE is an associative operation not otherwise handled, see if we
3244 can associate some operands. This can win if they are constants or
3245 if they are logically related (i.e. (a & b) & a. */
3246 if ((code == PLUS || code == MINUS
3247 || code == MULT || code == AND || code == IOR || code == XOR
3248 || code == DIV || code == UDIV
3249 || code == SMAX || code == SMIN || code == UMAX || code == UMIN)
3250 && INTEGRAL_MODE_P (mode))
3252 if (GET_CODE (XEXP (x, 0)) == code)
3254 rtx other = XEXP (XEXP (x, 0), 0);
3255 rtx inner_op0 = XEXP (XEXP (x, 0), 1);
3256 rtx inner_op1 = XEXP (x, 1);
3259 /* Make sure we pass the constant operand if any as the second
3260 one if this is a commutative operation. */
3261 if (CONSTANT_P (inner_op0) && GET_RTX_CLASS (code) == 'c')
3263 rtx tem = inner_op0;
3264 inner_op0 = inner_op1;
3267 inner = simplify_binary_operation (code == MINUS ? PLUS
3268 : code == DIV ? MULT
3269 : code == UDIV ? MULT
3271 mode, inner_op0, inner_op1);
3273 /* For commutative operations, try the other pair if that one
3275 if (inner == 0 && GET_RTX_CLASS (code) == 'c')
3277 other = XEXP (XEXP (x, 0), 1);
3278 inner = simplify_binary_operation (code, mode,
3279 XEXP (XEXP (x, 0), 0),
3284 return gen_binary (code, mode, other, inner);
3288 /* A little bit of algebraic simplification here. */
3292 /* Ensure that our address has any ASHIFTs converted to MULT in case
3293 address-recognizing predicates are called later. */
3294 temp = make_compound_operation (XEXP (x, 0), MEM);
3295 SUBST (XEXP (x, 0), temp);
3299 /* (subreg:A (mem:B X) N) becomes a modified MEM unless the SUBREG
3300 is paradoxical. If we can't do that safely, then it becomes
3301 something nonsensical so that this combination won't take place. */
3303 if (GET_CODE (SUBREG_REG (x)) == MEM
3304 && (GET_MODE_SIZE (mode)
3305 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x)))))
3307 rtx inner = SUBREG_REG (x);
3308 int endian_offset = 0;
3309 /* Don't change the mode of the MEM
3310 if that would change the meaning of the address. */
3311 if (MEM_VOLATILE_P (SUBREG_REG (x))
3312 || mode_dependent_address_p (XEXP (inner, 0)))
3313 return gen_rtx (CLOBBER, mode, const0_rtx);
3315 if (BYTES_BIG_ENDIAN)
3317 if (GET_MODE_SIZE (mode) < UNITS_PER_WORD)
3318 endian_offset += UNITS_PER_WORD - GET_MODE_SIZE (mode);
3319 if (GET_MODE_SIZE (GET_MODE (inner)) < UNITS_PER_WORD)
3320 endian_offset -= (UNITS_PER_WORD
3321 - GET_MODE_SIZE (GET_MODE (inner)));
3323 /* Note if the plus_constant doesn't make a valid address
3324 then this combination won't be accepted. */
3325 x = gen_rtx (MEM, mode,
3326 plus_constant (XEXP (inner, 0),
3327 (SUBREG_WORD (x) * UNITS_PER_WORD
3329 MEM_VOLATILE_P (x) = MEM_VOLATILE_P (inner);
3330 RTX_UNCHANGING_P (x) = RTX_UNCHANGING_P (inner);
3331 MEM_IN_STRUCT_P (x) = MEM_IN_STRUCT_P (inner);
3335 /* If we are in a SET_DEST, these other cases can't apply. */
3339 /* Changing mode twice with SUBREG => just change it once,
3340 or not at all if changing back to starting mode. */
3341 if (GET_CODE (SUBREG_REG (x)) == SUBREG)
3343 if (mode == GET_MODE (SUBREG_REG (SUBREG_REG (x)))
3344 && SUBREG_WORD (x) == 0 && SUBREG_WORD (SUBREG_REG (x)) == 0)
3345 return SUBREG_REG (SUBREG_REG (x));
3347 SUBST_INT (SUBREG_WORD (x),
3348 SUBREG_WORD (x) + SUBREG_WORD (SUBREG_REG (x)));
3349 SUBST (SUBREG_REG (x), SUBREG_REG (SUBREG_REG (x)));
3352 /* SUBREG of a hard register => just change the register number
3353 and/or mode. If the hard register is not valid in that mode,
3354 suppress this combination. If the hard register is the stack,
3355 frame, or argument pointer, leave this as a SUBREG. */
3357 if (GET_CODE (SUBREG_REG (x)) == REG
3358 && REGNO (SUBREG_REG (x)) < FIRST_PSEUDO_REGISTER
3359 && REGNO (SUBREG_REG (x)) != FRAME_POINTER_REGNUM
3360 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
3361 && REGNO (SUBREG_REG (x)) != HARD_FRAME_POINTER_REGNUM
3363 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
3364 && REGNO (SUBREG_REG (x)) != ARG_POINTER_REGNUM
3366 && REGNO (SUBREG_REG (x)) != STACK_POINTER_REGNUM)
3368 if (HARD_REGNO_MODE_OK (REGNO (SUBREG_REG (x)) + SUBREG_WORD (x),
3370 return gen_rtx (REG, mode,
3371 REGNO (SUBREG_REG (x)) + SUBREG_WORD (x));
3373 return gen_rtx (CLOBBER, mode, const0_rtx);
3376 /* For a constant, try to pick up the part we want. Handle a full
3377 word and low-order part. Only do this if we are narrowing
3378 the constant; if it is being widened, we have no idea what
3379 the extra bits will have been set to. */
3381 if (CONSTANT_P (SUBREG_REG (x)) && op0_mode != VOIDmode
3382 && GET_MODE_SIZE (mode) == UNITS_PER_WORD
3383 && GET_MODE_SIZE (op0_mode) > UNITS_PER_WORD
3384 && GET_MODE_CLASS (mode) == MODE_INT)
3386 temp = operand_subword (SUBREG_REG (x), SUBREG_WORD (x),
3392 /* If we want a subreg of a constant, at offset 0,
3393 take the low bits. On a little-endian machine, that's
3394 always valid. On a big-endian machine, it's valid
3395 only if the constant's mode fits in one word. Note that we
3396 cannot use subreg_lowpart_p since SUBREG_REG may be VOIDmode. */
3397 if (CONSTANT_P (SUBREG_REG (x))
3398 && ((GET_MODE_SIZE (op0_mode) <= UNITS_PER_WORD
3399 || ! WORDS_BIG_ENDIAN)
3400 ? SUBREG_WORD (x) == 0
3402 == ((GET_MODE_SIZE (op0_mode)
3403 - MAX (GET_MODE_SIZE (mode), UNITS_PER_WORD))
3405 && GET_MODE_SIZE (mode) <= GET_MODE_SIZE (op0_mode)
3406 && (! WORDS_BIG_ENDIAN
3407 || GET_MODE_BITSIZE (op0_mode) <= BITS_PER_WORD))
3408 return gen_lowpart_for_combine (mode, SUBREG_REG (x));
3410 /* A paradoxical SUBREG of a VOIDmode constant is the same constant,
3411 since we are saying that the high bits don't matter. */
3412 if (CONSTANT_P (SUBREG_REG (x)) && GET_MODE (SUBREG_REG (x)) == VOIDmode
3413 && GET_MODE_SIZE (mode) > GET_MODE_SIZE (op0_mode))
3414 return SUBREG_REG (x);
3416 /* Note that we cannot do any narrowing for non-constants since
3417 we might have been counting on using the fact that some bits were
3418 zero. We now do this in the SET. */
3423 /* (not (plus X -1)) can become (neg X). */
3424 if (GET_CODE (XEXP (x, 0)) == PLUS
3425 && XEXP (XEXP (x, 0), 1) == constm1_rtx)
3426 return gen_rtx_combine (NEG, mode, XEXP (XEXP (x, 0), 0));
3428 /* Similarly, (not (neg X)) is (plus X -1). */
3429 if (GET_CODE (XEXP (x, 0)) == NEG)
3430 return gen_rtx_combine (PLUS, mode, XEXP (XEXP (x, 0), 0),
3433 /* (not (xor X C)) for C constant is (xor X D) with D = ~ C. */
3434 if (GET_CODE (XEXP (x, 0)) == XOR
3435 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3436 && (temp = simplify_unary_operation (NOT, mode,
3437 XEXP (XEXP (x, 0), 1),
3439 return gen_binary (XOR, mode, XEXP (XEXP (x, 0), 0), temp);
3441 /* (not (ashift 1 X)) is (rotate ~1 X). We used to do this for operands
3442 other than 1, but that is not valid. We could do a similar
3443 simplification for (not (lshiftrt C X)) where C is just the sign bit,
3444 but this doesn't seem common enough to bother with. */
3445 if (GET_CODE (XEXP (x, 0)) == ASHIFT
3446 && XEXP (XEXP (x, 0), 0) == const1_rtx)
3447 return gen_rtx (ROTATE, mode, gen_unary (NOT, mode, mode, const1_rtx),
3448 XEXP (XEXP (x, 0), 1));
3450 if (GET_CODE (XEXP (x, 0)) == SUBREG
3451 && subreg_lowpart_p (XEXP (x, 0))
3452 && (GET_MODE_SIZE (GET_MODE (XEXP (x, 0)))
3453 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (x, 0)))))
3454 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == ASHIFT
3455 && XEXP (SUBREG_REG (XEXP (x, 0)), 0) == const1_rtx)
3457 enum machine_mode inner_mode = GET_MODE (SUBREG_REG (XEXP (x, 0)));
3459 x = gen_rtx (ROTATE, inner_mode,
3460 gen_unary (NOT, inner_mode, inner_mode, const1_rtx),
3461 XEXP (SUBREG_REG (XEXP (x, 0)), 1));
3462 return gen_lowpart_for_combine (mode, x);
3465 /* If STORE_FLAG_VALUE is -1, (not (comparison foo bar)) can be done by
3466 reversing the comparison code if valid. */
3467 if (STORE_FLAG_VALUE == -1
3468 && GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
3469 && reversible_comparison_p (XEXP (x, 0)))
3470 return gen_rtx_combine (reverse_condition (GET_CODE (XEXP (x, 0))),
3471 mode, XEXP (XEXP (x, 0), 0),
3472 XEXP (XEXP (x, 0), 1));
3474 /* (ashiftrt foo C) where C is the number of bits in FOO minus 1
3475 is (lt foo (const_int 0)) if STORE_FLAG_VALUE is -1, so we can
3476 perform the above simplification. */
3478 if (STORE_FLAG_VALUE == -1
3479 && XEXP (x, 1) == const1_rtx
3480 && GET_CODE (XEXP (x, 0)) == ASHIFTRT
3481 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3482 && INTVAL (XEXP (XEXP (x, 0), 1)) == GET_MODE_BITSIZE (mode) - 1)
3483 return gen_rtx_combine (GE, mode, XEXP (XEXP (x, 0), 0), const0_rtx);
3485 /* Apply De Morgan's laws to reduce number of patterns for machines
3486 with negating logical insns (and-not, nand, etc.). If result has
3487 only one NOT, put it first, since that is how the patterns are
3490 if (GET_CODE (XEXP (x, 0)) == IOR || GET_CODE (XEXP (x, 0)) == AND)
3492 rtx in1 = XEXP (XEXP (x, 0), 0), in2 = XEXP (XEXP (x, 0), 1);
3494 if (GET_CODE (in1) == NOT)
3495 in1 = XEXP (in1, 0);
3497 in1 = gen_rtx_combine (NOT, GET_MODE (in1), in1);
3499 if (GET_CODE (in2) == NOT)
3500 in2 = XEXP (in2, 0);
3501 else if (GET_CODE (in2) == CONST_INT
3502 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
3503 in2 = GEN_INT (GET_MODE_MASK (mode) & ~ INTVAL (in2));
3505 in2 = gen_rtx_combine (NOT, GET_MODE (in2), in2);
3507 if (GET_CODE (in2) == NOT)
3510 in2 = in1; in1 = tem;
3513 return gen_rtx_combine (GET_CODE (XEXP (x, 0)) == IOR ? AND : IOR,
3519 /* (neg (plus X 1)) can become (not X). */
3520 if (GET_CODE (XEXP (x, 0)) == PLUS
3521 && XEXP (XEXP (x, 0), 1) == const1_rtx)
3522 return gen_rtx_combine (NOT, mode, XEXP (XEXP (x, 0), 0));
3524 /* Similarly, (neg (not X)) is (plus X 1). */
3525 if (GET_CODE (XEXP (x, 0)) == NOT)
3526 return plus_constant (XEXP (XEXP (x, 0), 0), 1);
3528 /* (neg (minus X Y)) can become (minus Y X). */
3529 if (GET_CODE (XEXP (x, 0)) == MINUS
3530 && (! FLOAT_MODE_P (mode)
3531 /* x-y != -(y-x) with IEEE floating point. */
3532 || TARGET_FLOAT_FORMAT != IEEE_FLOAT_FORMAT
3534 return gen_binary (MINUS, mode, XEXP (XEXP (x, 0), 1),
3535 XEXP (XEXP (x, 0), 0));
3537 /* (neg (xor A 1)) is (plus A -1) if A is known to be either 0 or 1. */
3538 if (GET_CODE (XEXP (x, 0)) == XOR && XEXP (XEXP (x, 0), 1) == const1_rtx
3539 && nonzero_bits (XEXP (XEXP (x, 0), 0), mode) == 1)
3540 return gen_binary (PLUS, mode, XEXP (XEXP (x, 0), 0), constm1_rtx);
3542 /* NEG commutes with ASHIFT since it is multiplication. Only do this
3543 if we can then eliminate the NEG (e.g.,
3544 if the operand is a constant). */
3546 if (GET_CODE (XEXP (x, 0)) == ASHIFT)
3548 temp = simplify_unary_operation (NEG, mode,
3549 XEXP (XEXP (x, 0), 0), mode);
3552 SUBST (XEXP (XEXP (x, 0), 0), temp);
3557 temp = expand_compound_operation (XEXP (x, 0));
3559 /* For C equal to the width of MODE minus 1, (neg (ashiftrt X C)) can be
3560 replaced by (lshiftrt X C). This will convert
3561 (neg (sign_extract X 1 Y)) to (zero_extract X 1 Y). */
3563 if (GET_CODE (temp) == ASHIFTRT
3564 && GET_CODE (XEXP (temp, 1)) == CONST_INT
3565 && INTVAL (XEXP (temp, 1)) == GET_MODE_BITSIZE (mode) - 1)
3566 return simplify_shift_const (temp, LSHIFTRT, mode, XEXP (temp, 0),
3567 INTVAL (XEXP (temp, 1)));
3569 /* If X has only a single bit that might be nonzero, say, bit I, convert
3570 (neg X) to (ashiftrt (ashift X C-I) C-I) where C is the bitsize of
3571 MODE minus 1. This will convert (neg (zero_extract X 1 Y)) to
3572 (sign_extract X 1 Y). But only do this if TEMP isn't a register
3573 or a SUBREG of one since we'd be making the expression more
3574 complex if it was just a register. */
3576 if (GET_CODE (temp) != REG
3577 && ! (GET_CODE (temp) == SUBREG
3578 && GET_CODE (SUBREG_REG (temp)) == REG)
3579 && (i = exact_log2 (nonzero_bits (temp, mode))) >= 0)
3581 rtx temp1 = simplify_shift_const
3582 (NULL_RTX, ASHIFTRT, mode,
3583 simplify_shift_const (NULL_RTX, ASHIFT, mode, temp,
3584 GET_MODE_BITSIZE (mode) - 1 - i),
3585 GET_MODE_BITSIZE (mode) - 1 - i);
3587 /* If all we did was surround TEMP with the two shifts, we
3588 haven't improved anything, so don't use it. Otherwise,
3589 we are better off with TEMP1. */
3590 if (GET_CODE (temp1) != ASHIFTRT
3591 || GET_CODE (XEXP (temp1, 0)) != ASHIFT
3592 || XEXP (XEXP (temp1, 0), 0) != temp)
3598 /* We can't handle truncation to a partial integer mode here
3599 because we don't know the real bitsize of the partial
3601 if (GET_MODE_CLASS (mode) == MODE_PARTIAL_INT)
3604 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
3606 force_to_mode (XEXP (x, 0), GET_MODE (XEXP (x, 0)),
3607 GET_MODE_MASK (mode), NULL_RTX, 0));
3609 /* (truncate:SI ({sign,zero}_extend:DI foo:SI)) == foo:SI. */
3610 if ((GET_CODE (XEXP (x, 0)) == SIGN_EXTEND
3611 || GET_CODE (XEXP (x, 0)) == ZERO_EXTEND)
3612 && GET_MODE (XEXP (XEXP (x, 0), 0)) == mode)
3613 return XEXP (XEXP (x, 0), 0);
3615 /* (truncate:SI (OP:DI ({sign,zero}_extend:DI foo:SI))) is
3616 (OP:SI foo:SI) if OP is NEG or ABS. */
3617 if ((GET_CODE (XEXP (x, 0)) == ABS
3618 || GET_CODE (XEXP (x, 0)) == NEG)
3619 && (GET_CODE (XEXP (XEXP (x, 0), 0)) == SIGN_EXTEND
3620 || GET_CODE (XEXP (XEXP (x, 0), 0)) == ZERO_EXTEND)
3621 && GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == mode)
3622 return gen_unary (GET_CODE (XEXP (x, 0)), mode, mode,
3623 XEXP (XEXP (XEXP (x, 0), 0), 0));
3625 /* (truncate:SI (subreg:DI (truncate:SI X) 0)) is
3627 if (GET_CODE (XEXP (x, 0)) == SUBREG
3628 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == TRUNCATE
3629 && subreg_lowpart_p (XEXP (x, 0)))
3630 return SUBREG_REG (XEXP (x, 0));
3632 /* If we know that the value is already truncated, we can
3633 replace the TRUNCATE with a SUBREG. */
3634 if (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) <= HOST_BITS_PER_WIDE_INT
3635 && (nonzero_bits (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
3636 &~ GET_MODE_MASK (mode)) == 0)
3637 return gen_lowpart_for_combine (mode, XEXP (x, 0));
3639 /* A truncate of a comparison can be replaced with a subreg if
3640 STORE_FLAG_VALUE permits. This is like the previous test,
3641 but it works even if the comparison is done in a mode larger
3642 than HOST_BITS_PER_WIDE_INT. */
3643 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
3644 && GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
3645 && ((HOST_WIDE_INT) STORE_FLAG_VALUE &~ GET_MODE_MASK (mode)) == 0)
3646 return gen_lowpart_for_combine (mode, XEXP (x, 0));
3648 /* Similarly, a truncate of a register whose value is a
3649 comparison can be replaced with a subreg if STORE_FLAG_VALUE
3651 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
3652 && ((HOST_WIDE_INT) STORE_FLAG_VALUE &~ GET_MODE_MASK (mode)) == 0
3653 && (temp = get_last_value (XEXP (x, 0)))
3654 && GET_RTX_CLASS (GET_CODE (temp)) == '<')
3655 return gen_lowpart_for_combine (mode, XEXP (x, 0));
3659 case FLOAT_TRUNCATE:
3660 /* (float_truncate:SF (float_extend:DF foo:SF)) = foo:SF. */
3661 if (GET_CODE (XEXP (x, 0)) == FLOAT_EXTEND
3662 && GET_MODE (XEXP (XEXP (x, 0), 0)) == mode)
3663 return XEXP (XEXP (x, 0), 0);
3665 /* (float_truncate:SF (OP:DF (float_extend:DF foo:sf))) is
3666 (OP:SF foo:SF) if OP is NEG or ABS. */
3667 if ((GET_CODE (XEXP (x, 0)) == ABS
3668 || GET_CODE (XEXP (x, 0)) == NEG)
3669 && GET_CODE (XEXP (XEXP (x, 0), 0)) == FLOAT_EXTEND
3670 && GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == mode)
3671 return gen_unary (GET_CODE (XEXP (x, 0)), mode, mode,
3672 XEXP (XEXP (XEXP (x, 0), 0), 0));
3674 /* (float_truncate:SF (subreg:DF (float_truncate:SF X) 0))
3675 is (float_truncate:SF x). */
3676 if (GET_CODE (XEXP (x, 0)) == SUBREG
3677 && subreg_lowpart_p (XEXP (x, 0))
3678 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == FLOAT_TRUNCATE)
3679 return SUBREG_REG (XEXP (x, 0));
3684 /* Convert (compare FOO (const_int 0)) to FOO unless we aren't
3685 using cc0, in which case we want to leave it as a COMPARE
3686 so we can distinguish it from a register-register-copy. */
3687 if (XEXP (x, 1) == const0_rtx)
3690 /* In IEEE floating point, x-0 is not the same as x. */
3691 if ((TARGET_FLOAT_FORMAT != IEEE_FLOAT_FORMAT
3692 || ! FLOAT_MODE_P (GET_MODE (XEXP (x, 0)))
3694 && XEXP (x, 1) == CONST0_RTX (GET_MODE (XEXP (x, 0))))
3700 /* (const (const X)) can become (const X). Do it this way rather than
3701 returning the inner CONST since CONST can be shared with a
3703 if (GET_CODE (XEXP (x, 0)) == CONST)
3704 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
3709 /* Convert (lo_sum (high FOO) FOO) to FOO. This is necessary so we
3710 can add in an offset. find_split_point will split this address up
3711 again if it doesn't match. */
3712 if (GET_CODE (XEXP (x, 0)) == HIGH
3713 && rtx_equal_p (XEXP (XEXP (x, 0), 0), XEXP (x, 1)))
3719 /* If we have (plus (plus (A const) B)), associate it so that CONST is
3720 outermost. That's because that's the way indexed addresses are
3721 supposed to appear. This code used to check many more cases, but
3722 they are now checked elsewhere. */
3723 if (GET_CODE (XEXP (x, 0)) == PLUS
3724 && CONSTANT_ADDRESS_P (XEXP (XEXP (x, 0), 1)))
3725 return gen_binary (PLUS, mode,
3726 gen_binary (PLUS, mode, XEXP (XEXP (x, 0), 0),
3728 XEXP (XEXP (x, 0), 1));
3730 /* (plus (xor (and <foo> (const_int pow2 - 1)) <c>) <-c>)
3731 when c is (const_int (pow2 + 1) / 2) is a sign extension of a
3732 bit-field and can be replaced by either a sign_extend or a
3733 sign_extract. The `and' may be a zero_extend. */
3734 if (GET_CODE (XEXP (x, 0)) == XOR
3735 && GET_CODE (XEXP (x, 1)) == CONST_INT
3736 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3737 && INTVAL (XEXP (x, 1)) == - INTVAL (XEXP (XEXP (x, 0), 1))
3738 && (i = exact_log2 (INTVAL (XEXP (XEXP (x, 0), 1)))) >= 0
3739 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
3740 && ((GET_CODE (XEXP (XEXP (x, 0), 0)) == AND
3741 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == CONST_INT
3742 && (INTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1))
3743 == ((HOST_WIDE_INT) 1 << (i + 1)) - 1))
3744 || (GET_CODE (XEXP (XEXP (x, 0), 0)) == ZERO_EXTEND
3745 && (GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)))
3747 return simplify_shift_const
3748 (NULL_RTX, ASHIFTRT, mode,
3749 simplify_shift_const (NULL_RTX, ASHIFT, mode,
3750 XEXP (XEXP (XEXP (x, 0), 0), 0),
3751 GET_MODE_BITSIZE (mode) - (i + 1)),
3752 GET_MODE_BITSIZE (mode) - (i + 1));
3754 /* (plus (comparison A B) C) can become (neg (rev-comp A B)) if
3755 C is 1 and STORE_FLAG_VALUE is -1 or if C is -1 and STORE_FLAG_VALUE
3756 is 1. This produces better code than the alternative immediately
3758 if (GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
3759 && reversible_comparison_p (XEXP (x, 0))
3760 && ((STORE_FLAG_VALUE == -1 && XEXP (x, 1) == const1_rtx)
3761 || (STORE_FLAG_VALUE == 1 && XEXP (x, 1) == constm1_rtx)))
3763 gen_unary (NEG, mode, mode,
3764 gen_binary (reverse_condition (GET_CODE (XEXP (x, 0))),
3765 mode, XEXP (XEXP (x, 0), 0),
3766 XEXP (XEXP (x, 0), 1)));
3768 /* If only the low-order bit of X is possibly nonzero, (plus x -1)
3769 can become (ashiftrt (ashift (xor x 1) C) C) where C is
3770 the bitsize of the mode - 1. This allows simplification of
3771 "a = (b & 8) == 0;" */
3772 if (XEXP (x, 1) == constm1_rtx
3773 && GET_CODE (XEXP (x, 0)) != REG
3774 && ! (GET_CODE (XEXP (x,0)) == SUBREG
3775 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == REG)
3776 && nonzero_bits (XEXP (x, 0), mode) == 1)
3777 return simplify_shift_const (NULL_RTX, ASHIFTRT, mode,
3778 simplify_shift_const (NULL_RTX, ASHIFT, mode,
3779 gen_rtx_combine (XOR, mode,
3780 XEXP (x, 0), const1_rtx),
3781 GET_MODE_BITSIZE (mode) - 1),
3782 GET_MODE_BITSIZE (mode) - 1);
3784 /* If we are adding two things that have no bits in common, convert
3785 the addition into an IOR. This will often be further simplified,
3786 for example in cases like ((a & 1) + (a & 2)), which can
3789 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
3790 && (nonzero_bits (XEXP (x, 0), mode)
3791 & nonzero_bits (XEXP (x, 1), mode)) == 0)
3792 return gen_binary (IOR, mode, XEXP (x, 0), XEXP (x, 1));
3796 /* If STORE_FLAG_VALUE is 1, (minus 1 (comparison foo bar)) can be done
3797 by reversing the comparison code if valid. */
3798 if (STORE_FLAG_VALUE == 1
3799 && XEXP (x, 0) == const1_rtx
3800 && GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) == '<'
3801 && reversible_comparison_p (XEXP (x, 1)))
3802 return gen_binary (reverse_condition (GET_CODE (XEXP (x, 1))),
3803 mode, XEXP (XEXP (x, 1), 0),
3804 XEXP (XEXP (x, 1), 1));
3806 /* (minus <foo> (and <foo> (const_int -pow2))) becomes
3807 (and <foo> (const_int pow2-1)) */
3808 if (GET_CODE (XEXP (x, 1)) == AND
3809 && GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT
3810 && exact_log2 (- INTVAL (XEXP (XEXP (x, 1), 1))) >= 0
3811 && rtx_equal_p (XEXP (XEXP (x, 1), 0), XEXP (x, 0)))
3812 return simplify_and_const_int (NULL_RTX, mode, XEXP (x, 0),
3813 - INTVAL (XEXP (XEXP (x, 1), 1)) - 1);
3815 /* Canonicalize (minus A (plus B C)) to (minus (minus A B) C) for
3817 if (GET_CODE (XEXP (x, 1)) == PLUS && INTEGRAL_MODE_P (mode))
3818 return gen_binary (MINUS, mode,
3819 gen_binary (MINUS, mode, XEXP (x, 0),
3820 XEXP (XEXP (x, 1), 0)),
3821 XEXP (XEXP (x, 1), 1));
3825 /* If we have (mult (plus A B) C), apply the distributive law and then
3826 the inverse distributive law to see if things simplify. This
3827 occurs mostly in addresses, often when unrolling loops. */
3829 if (GET_CODE (XEXP (x, 0)) == PLUS)
3831 x = apply_distributive_law
3832 (gen_binary (PLUS, mode,
3833 gen_binary (MULT, mode,
3834 XEXP (XEXP (x, 0), 0), XEXP (x, 1)),
3835 gen_binary (MULT, mode,
3836 XEXP (XEXP (x, 0), 1), XEXP (x, 1))));
3838 if (GET_CODE (x) != MULT)
3844 /* If this is a divide by a power of two, treat it as a shift if
3845 its first operand is a shift. */
3846 if (GET_CODE (XEXP (x, 1)) == CONST_INT
3847 && (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0
3848 && (GET_CODE (XEXP (x, 0)) == ASHIFT
3849 || GET_CODE (XEXP (x, 0)) == LSHIFTRT
3850 || GET_CODE (XEXP (x, 0)) == ASHIFTRT
3851 || GET_CODE (XEXP (x, 0)) == ROTATE
3852 || GET_CODE (XEXP (x, 0)) == ROTATERT))
3853 return simplify_shift_const (NULL_RTX, LSHIFTRT, mode, XEXP (x, 0), i);
3857 case GT: case GTU: case GE: case GEU:
3858 case LT: case LTU: case LE: case LEU:
3859 /* If the first operand is a condition code, we can't do anything
3861 if (GET_CODE (XEXP (x, 0)) == COMPARE
3862 || (GET_MODE_CLASS (GET_MODE (XEXP (x, 0))) != MODE_CC
3864 && XEXP (x, 0) != cc0_rtx
3868 rtx op0 = XEXP (x, 0);
3869 rtx op1 = XEXP (x, 1);
3870 enum rtx_code new_code;
3872 if (GET_CODE (op0) == COMPARE)
3873 op1 = XEXP (op0, 1), op0 = XEXP (op0, 0);
3875 /* Simplify our comparison, if possible. */
3876 new_code = simplify_comparison (code, &op0, &op1);
3878 /* If STORE_FLAG_VALUE is 1, we can convert (ne x 0) to simply X
3879 if only the low-order bit is possibly nonzero in X (such as when
3880 X is a ZERO_EXTRACT of one bit). Similarly, we can convert EQ to
3881 (xor X 1) or (minus 1 X); we use the former. Finally, if X is
3882 known to be either 0 or -1, NE becomes a NEG and EQ becomes
3885 Remove any ZERO_EXTRACT we made when thinking this was a
3886 comparison. It may now be simpler to use, e.g., an AND. If a
3887 ZERO_EXTRACT is indeed appropriate, it will be placed back by
3888 the call to make_compound_operation in the SET case. */
3890 if (STORE_FLAG_VALUE == 1
3891 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
3892 && op1 == const0_rtx && nonzero_bits (op0, mode) == 1)
3893 return gen_lowpart_for_combine (mode,
3894 expand_compound_operation (op0));
3896 else if (STORE_FLAG_VALUE == 1
3897 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
3898 && op1 == const0_rtx
3899 && (num_sign_bit_copies (op0, mode)
3900 == GET_MODE_BITSIZE (mode)))
3902 op0 = expand_compound_operation (op0);
3903 return gen_unary (NEG, mode, mode,
3904 gen_lowpart_for_combine (mode, op0));
3907 else if (STORE_FLAG_VALUE == 1
3908 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
3909 && op1 == const0_rtx
3910 && nonzero_bits (op0, mode) == 1)
3912 op0 = expand_compound_operation (op0);
3913 return gen_binary (XOR, mode,
3914 gen_lowpart_for_combine (mode, op0),
3918 else if (STORE_FLAG_VALUE == 1
3919 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
3920 && op1 == const0_rtx
3921 && (num_sign_bit_copies (op0, mode)
3922 == GET_MODE_BITSIZE (mode)))
3924 op0 = expand_compound_operation (op0);
3925 return plus_constant (gen_lowpart_for_combine (mode, op0), 1);
3928 /* If STORE_FLAG_VALUE is -1, we have cases similar to
3930 if (STORE_FLAG_VALUE == -1
3931 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
3932 && op1 == const0_rtx
3933 && (num_sign_bit_copies (op0, mode)
3934 == GET_MODE_BITSIZE (mode)))
3935 return gen_lowpart_for_combine (mode,
3936 expand_compound_operation (op0));
3938 else if (STORE_FLAG_VALUE == -1
3939 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
3940 && op1 == const0_rtx
3941 && nonzero_bits (op0, mode) == 1)
3943 op0 = expand_compound_operation (op0);
3944 return gen_unary (NEG, mode, mode,
3945 gen_lowpart_for_combine (mode, op0));
3948 else if (STORE_FLAG_VALUE == -1
3949 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
3950 && op1 == const0_rtx
3951 && (num_sign_bit_copies (op0, mode)
3952 == GET_MODE_BITSIZE (mode)))
3954 op0 = expand_compound_operation (op0);
3955 return gen_unary (NOT, mode, mode,
3956 gen_lowpart_for_combine (mode, op0));
3959 /* If X is 0/1, (eq X 0) is X-1. */
3960 else if (STORE_FLAG_VALUE == -1
3961 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
3962 && op1 == const0_rtx
3963 && nonzero_bits (op0, mode) == 1)
3965 op0 = expand_compound_operation (op0);
3966 return plus_constant (gen_lowpart_for_combine (mode, op0), -1);
3969 /* If STORE_FLAG_VALUE says to just test the sign bit and X has just
3970 one bit that might be nonzero, we can convert (ne x 0) to
3971 (ashift x c) where C puts the bit in the sign bit. Remove any
3972 AND with STORE_FLAG_VALUE when we are done, since we are only
3973 going to test the sign bit. */
3974 if (new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
3975 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
3976 && ((STORE_FLAG_VALUE & GET_MODE_MASK (mode))
3977 == (HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (mode) - 1))
3978 && op1 == const0_rtx
3979 && mode == GET_MODE (op0)
3980 && (i = exact_log2 (nonzero_bits (op0, mode))) >= 0)
3982 x = simplify_shift_const (NULL_RTX, ASHIFT, mode,
3983 expand_compound_operation (op0),
3984 GET_MODE_BITSIZE (mode) - 1 - i);
3985 if (GET_CODE (x) == AND && XEXP (x, 1) == const_true_rtx)
3991 /* If the code changed, return a whole new comparison. */
3992 if (new_code != code)
3993 return gen_rtx_combine (new_code, mode, op0, op1);
3995 /* Otherwise, keep this operation, but maybe change its operands.
3996 This also converts (ne (compare FOO BAR) 0) to (ne FOO BAR). */
3997 SUBST (XEXP (x, 0), op0);
3998 SUBST (XEXP (x, 1), op1);
4003 return simplify_if_then_else (x);
4009 /* If we are processing SET_DEST, we are done. */
4013 return expand_compound_operation (x);
4016 return simplify_set (x);
4021 return simplify_logical (x, last);
4024 /* (abs (neg <foo>)) -> (abs <foo>) */
4025 if (GET_CODE (XEXP (x, 0)) == NEG)
4026 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4028 /* If operand is something known to be positive, ignore the ABS. */
4029 if (GET_CODE (XEXP (x, 0)) == FFS || GET_CODE (XEXP (x, 0)) == ABS
4030 || ((GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
4031 <= HOST_BITS_PER_WIDE_INT)
4032 && ((nonzero_bits (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
4033 & ((HOST_WIDE_INT) 1
4034 << (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - 1)))
4039 /* If operand is known to be only -1 or 0, convert ABS to NEG. */
4040 if (num_sign_bit_copies (XEXP (x, 0), mode) == GET_MODE_BITSIZE (mode))
4041 return gen_rtx_combine (NEG, mode, XEXP (x, 0));
4046 /* (ffs (*_extend <X>)) = (ffs <X>) */
4047 if (GET_CODE (XEXP (x, 0)) == SIGN_EXTEND
4048 || GET_CODE (XEXP (x, 0)) == ZERO_EXTEND)
4049 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4053 /* (float (sign_extend <X>)) = (float <X>). */
4054 if (GET_CODE (XEXP (x, 0)) == SIGN_EXTEND)
4055 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4063 /* If this is a shift by a constant amount, simplify it. */
4064 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
4065 return simplify_shift_const (x, code, mode, XEXP (x, 0),
4066 INTVAL (XEXP (x, 1)));
4068 #ifdef SHIFT_COUNT_TRUNCATED
4069 else if (SHIFT_COUNT_TRUNCATED && GET_CODE (XEXP (x, 1)) != REG)
4071 force_to_mode (XEXP (x, 1), GET_MODE (x),
4073 << exact_log2 (GET_MODE_BITSIZE (GET_MODE (x))))
4084 /* Simplify X, an IF_THEN_ELSE expression. Return the new expression. */
4087 simplify_if_then_else (x)
4090 enum machine_mode mode = GET_MODE (x);
4091 rtx cond = XEXP (x, 0);
4092 rtx true = XEXP (x, 1);
4093 rtx false = XEXP (x, 2);
4094 enum rtx_code true_code = GET_CODE (cond);
4095 int comparison_p = GET_RTX_CLASS (true_code) == '<';
4099 /* Simplify storing of the truth value. */
4100 if (comparison_p && true == const_true_rtx && false == const0_rtx)
4101 return gen_binary (true_code, mode, XEXP (cond, 0), XEXP (cond, 1));
4103 /* Also when the truth value has to be reversed. */
4104 if (comparison_p && reversible_comparison_p (cond)
4105 && true == const0_rtx && false == const_true_rtx)
4106 return gen_binary (reverse_condition (true_code),
4107 mode, XEXP (cond, 0), XEXP (cond, 1));
4109 /* Sometimes we can simplify the arm of an IF_THEN_ELSE if a register used
4110 in it is being compared against certain values. Get the true and false
4111 comparisons and see if that says anything about the value of each arm. */
4113 if (comparison_p && reversible_comparison_p (cond)
4114 && GET_CODE (XEXP (cond, 0)) == REG)
4117 rtx from = XEXP (cond, 0);
4118 enum rtx_code false_code = reverse_condition (true_code);
4119 rtx true_val = XEXP (cond, 1);
4120 rtx false_val = true_val;
4123 /* If FALSE_CODE is EQ, swap the codes and arms. */
4125 if (false_code == EQ)
4127 swapped = 1, true_code = EQ, false_code = NE;
4128 temp = true, true = false, false = temp;
4131 /* If we are comparing against zero and the expression being tested has
4132 only a single bit that might be nonzero, that is its value when it is
4133 not equal to zero. Similarly if it is known to be -1 or 0. */
4135 if (true_code == EQ && true_val == const0_rtx
4136 && exact_log2 (nzb = nonzero_bits (from, GET_MODE (from))) >= 0)
4137 false_code = EQ, false_val = GEN_INT (nzb);
4138 else if (true_code == EQ && true_val == const0_rtx
4139 && (num_sign_bit_copies (from, GET_MODE (from))
4140 == GET_MODE_BITSIZE (GET_MODE (from))))
4141 false_code = EQ, false_val = constm1_rtx;
4143 /* Now simplify an arm if we know the value of the register in the
4144 branch and it is used in the arm. Be careful due to the potential
4145 of locally-shared RTL. */
4147 if (reg_mentioned_p (from, true))
4148 true = subst (known_cond (copy_rtx (true), true_code, from, true_val),
4149 pc_rtx, pc_rtx, 0, 0);
4150 if (reg_mentioned_p (from, false))
4151 false = subst (known_cond (copy_rtx (false), false_code,
4153 pc_rtx, pc_rtx, 0, 0);
4155 SUBST (XEXP (x, 1), swapped ? false : true);
4156 SUBST (XEXP (x, 2), swapped ? true : false);
4158 true = XEXP (x, 1), false = XEXP (x, 2), true_code = GET_CODE (cond);
4161 /* If we have (if_then_else FOO (pc) (label_ref BAR)) and FOO can be
4162 reversed, do so to avoid needing two sets of patterns for
4163 subtract-and-branch insns. Similarly if we have a constant in the true
4164 arm, the false arm is the same as the first operand of the comparison, or
4165 the false arm is more complicated than the true arm. */
4167 if (comparison_p && reversible_comparison_p (cond)
4169 || (CONSTANT_P (true)
4170 && GET_CODE (false) != CONST_INT && false != pc_rtx)
4171 || true == const0_rtx
4172 || (GET_RTX_CLASS (GET_CODE (true)) == 'o'
4173 && GET_RTX_CLASS (GET_CODE (false)) != 'o')
4174 || (GET_CODE (true) == SUBREG
4175 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (true))) == 'o'
4176 && GET_RTX_CLASS (GET_CODE (false)) != 'o')
4177 || reg_mentioned_p (true, false)
4178 || rtx_equal_p (false, XEXP (cond, 0))))
4180 true_code = reverse_condition (true_code);
4182 gen_binary (true_code, GET_MODE (cond), XEXP (cond, 0),
4185 SUBST (XEXP (x, 1), false);
4186 SUBST (XEXP (x, 2), true);
4188 temp = true, true = false, false = temp, cond = XEXP (x, 0);
4190 /* It is possible that the conditional has been simplified out. */
4191 true_code = GET_CODE (cond);
4192 comparison_p = GET_RTX_CLASS (true_code) == '<';
4195 /* If the two arms are identical, we don't need the comparison. */
4197 if (rtx_equal_p (true, false) && ! side_effects_p (cond))
4200 /* Convert a == b ? b : a to "a". */
4201 if (true_code == EQ && ! side_effects_p (cond)
4202 && rtx_equal_p (XEXP (cond, 0), false)
4203 && rtx_equal_p (XEXP (cond, 1), true))
4205 else if (true_code == NE && ! side_effects_p (cond)
4206 && rtx_equal_p (XEXP (cond, 0), true)
4207 && rtx_equal_p (XEXP (cond, 1), false))
4210 /* Look for cases where we have (abs x) or (neg (abs X)). */
4212 if (GET_MODE_CLASS (mode) == MODE_INT
4213 && GET_CODE (false) == NEG
4214 && rtx_equal_p (true, XEXP (false, 0))
4216 && rtx_equal_p (true, XEXP (cond, 0))
4217 && ! side_effects_p (true))
4222 return gen_unary (ABS, mode, mode, true);
4225 return gen_unary (NEG, mode, mode, gen_unary (ABS, mode, mode, true));
4228 /* Look for MIN or MAX. */
4230 if ((! FLOAT_MODE_P (mode) || flag_fast_math)
4232 && rtx_equal_p (XEXP (cond, 0), true)
4233 && rtx_equal_p (XEXP (cond, 1), false)
4234 && ! side_effects_p (cond))
4239 return gen_binary (SMAX, mode, true, false);
4242 return gen_binary (SMIN, mode, true, false);
4245 return gen_binary (UMAX, mode, true, false);
4248 return gen_binary (UMIN, mode, true, false);
4251 /* If we have (if_then_else COND (OP Z C1) Z) and OP is an identity when its
4252 second operand is zero, this can be done as (OP Z (mult COND C2)) where
4253 C2 = C1 * STORE_FLAG_VALUE. Similarly if OP has an outer ZERO_EXTEND or
4254 SIGN_EXTEND as long as Z is already extended (so we don't destroy it).
4255 We can do this kind of thing in some cases when STORE_FLAG_VALUE is
4256 neither 1 or -1, but it isn't worth checking for. */
4258 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
4259 && comparison_p && mode != VOIDmode && ! side_effects_p (x))
4261 rtx t = make_compound_operation (true, SET);
4262 rtx f = make_compound_operation (false, SET);
4263 rtx cond_op0 = XEXP (cond, 0);
4264 rtx cond_op1 = XEXP (cond, 1);
4265 enum rtx_code op, extend_op = NIL;
4266 enum machine_mode m = mode;
4269 if ((GET_CODE (t) == PLUS || GET_CODE (t) == MINUS
4270 || GET_CODE (t) == IOR || GET_CODE (t) == XOR
4271 || GET_CODE (t) == ASHIFT
4272 || GET_CODE (t) == LSHIFTRT || GET_CODE (t) == ASHIFTRT)
4273 && rtx_equal_p (XEXP (t, 0), f))
4274 c1 = XEXP (t, 1), op = GET_CODE (t), z = f;
4276 /* If an identity-zero op is commutative, check whether there
4277 would be a match if we swapped the operands. */
4278 else if ((GET_CODE (t) == PLUS || GET_CODE (t) == IOR
4279 || GET_CODE (t) == XOR)
4280 && rtx_equal_p (XEXP (t, 1), f))
4281 c1 = XEXP (t, 0), op = GET_CODE (t), z = f;
4282 else if (GET_CODE (t) == SIGN_EXTEND
4283 && (GET_CODE (XEXP (t, 0)) == PLUS
4284 || GET_CODE (XEXP (t, 0)) == MINUS
4285 || GET_CODE (XEXP (t, 0)) == IOR
4286 || GET_CODE (XEXP (t, 0)) == XOR
4287 || GET_CODE (XEXP (t, 0)) == ASHIFT
4288 || GET_CODE (XEXP (t, 0)) == LSHIFTRT
4289 || GET_CODE (XEXP (t, 0)) == ASHIFTRT)
4290 && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG
4291 && subreg_lowpart_p (XEXP (XEXP (t, 0), 0))
4292 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f)
4293 && (num_sign_bit_copies (f, GET_MODE (f))
4294 > (GET_MODE_BITSIZE (mode)
4295 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t, 0), 0))))))
4297 c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0));
4298 extend_op = SIGN_EXTEND;
4299 m = GET_MODE (XEXP (t, 0));
4301 else if (GET_CODE (t) == SIGN_EXTEND
4302 && (GET_CODE (XEXP (t, 0)) == PLUS
4303 || GET_CODE (XEXP (t, 0)) == IOR
4304 || GET_CODE (XEXP (t, 0)) == XOR)
4305 && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG
4306 && subreg_lowpart_p (XEXP (XEXP (t, 0), 1))
4307 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f)
4308 && (num_sign_bit_copies (f, GET_MODE (f))
4309 > (GET_MODE_BITSIZE (mode)
4310 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t, 0), 1))))))
4312 c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0));
4313 extend_op = SIGN_EXTEND;
4314 m = GET_MODE (XEXP (t, 0));
4316 else if (GET_CODE (t) == ZERO_EXTEND
4317 && (GET_CODE (XEXP (t, 0)) == PLUS
4318 || GET_CODE (XEXP (t, 0)) == MINUS
4319 || GET_CODE (XEXP (t, 0)) == IOR
4320 || GET_CODE (XEXP (t, 0)) == XOR
4321 || GET_CODE (XEXP (t, 0)) == ASHIFT
4322 || GET_CODE (XEXP (t, 0)) == LSHIFTRT
4323 || GET_CODE (XEXP (t, 0)) == ASHIFTRT)
4324 && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG
4325 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4326 && subreg_lowpart_p (XEXP (XEXP (t, 0), 0))
4327 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f)
4328 && ((nonzero_bits (f, GET_MODE (f))
4329 & ~ GET_MODE_MASK (GET_MODE (XEXP (XEXP (t, 0), 0))))
4332 c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0));
4333 extend_op = ZERO_EXTEND;
4334 m = GET_MODE (XEXP (t, 0));
4336 else if (GET_CODE (t) == ZERO_EXTEND
4337 && (GET_CODE (XEXP (t, 0)) == PLUS
4338 || GET_CODE (XEXP (t, 0)) == IOR
4339 || GET_CODE (XEXP (t, 0)) == XOR)
4340 && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG
4341 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4342 && subreg_lowpart_p (XEXP (XEXP (t, 0), 1))
4343 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f)
4344 && ((nonzero_bits (f, GET_MODE (f))
4345 & ~ GET_MODE_MASK (GET_MODE (XEXP (XEXP (t, 0), 1))))
4348 c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0));
4349 extend_op = ZERO_EXTEND;
4350 m = GET_MODE (XEXP (t, 0));
4355 temp = subst (gen_binary (true_code, m, cond_op0, cond_op1),
4356 pc_rtx, pc_rtx, 0, 0);
4357 temp = gen_binary (MULT, m, temp,
4358 gen_binary (MULT, m, c1, const_true_rtx));
4359 temp = subst (temp, pc_rtx, pc_rtx, 0, 0);
4360 temp = gen_binary (op, m, gen_lowpart_for_combine (m, z), temp);
4362 if (extend_op != NIL)
4363 temp = gen_unary (extend_op, mode, m, temp);
4369 /* If we have (if_then_else (ne A 0) C1 0) and either A is known to be 0 or
4370 1 and C1 is a single bit or A is known to be 0 or -1 and C1 is the
4371 negation of a single bit, we can convert this operation to a shift. We
4372 can actually do this more generally, but it doesn't seem worth it. */
4374 if (true_code == NE && XEXP (cond, 1) == const0_rtx
4375 && false == const0_rtx && GET_CODE (true) == CONST_INT
4376 && ((1 == nonzero_bits (XEXP (cond, 0), mode)
4377 && (i = exact_log2 (INTVAL (true))) >= 0)
4378 || ((num_sign_bit_copies (XEXP (cond, 0), mode)
4379 == GET_MODE_BITSIZE (mode))
4380 && (i = exact_log2 (- INTVAL (true))) >= 0)))
4382 simplify_shift_const (NULL_RTX, ASHIFT, mode,
4383 gen_lowpart_for_combine (mode, XEXP (cond, 0)), i);
4388 /* Simplify X, a SET expression. Return the new expression. */
4394 rtx src = SET_SRC (x);
4395 rtx dest = SET_DEST (x);
4396 enum machine_mode mode
4397 = GET_MODE (src) != VOIDmode ? GET_MODE (src) : GET_MODE (dest);
4401 /* (set (pc) (return)) gets written as (return). */
4402 if (GET_CODE (dest) == PC && GET_CODE (src) == RETURN)
4405 /* Now that we know for sure which bits of SRC we are using, see if we can
4406 simplify the expression for the object knowing that we only need the
4409 if (GET_MODE_CLASS (mode) == MODE_INT)
4410 src = force_to_mode (src, mode, GET_MODE_MASK (mode), NULL_RTX, 0);
4412 /* If we are setting CC0 or if the source is a COMPARE, look for the use of
4413 the comparison result and try to simplify it unless we already have used
4414 undobuf.other_insn. */
4415 if ((GET_CODE (src) == COMPARE
4420 && (cc_use = find_single_use (dest, subst_insn, &other_insn)) != 0
4421 && (undobuf.other_insn == 0 || other_insn == undobuf.other_insn)
4422 && GET_RTX_CLASS (GET_CODE (*cc_use)) == '<'
4423 && rtx_equal_p (XEXP (*cc_use, 0), dest))
4425 enum rtx_code old_code = GET_CODE (*cc_use);
4426 enum rtx_code new_code;
4428 int other_changed = 0;
4429 enum machine_mode compare_mode = GET_MODE (dest);
4431 if (GET_CODE (src) == COMPARE)
4432 op0 = XEXP (src, 0), op1 = XEXP (src, 1);
4434 op0 = src, op1 = const0_rtx;
4436 /* Simplify our comparison, if possible. */
4437 new_code = simplify_comparison (old_code, &op0, &op1);
4439 #ifdef EXTRA_CC_MODES
4440 /* If this machine has CC modes other than CCmode, check to see if we
4441 need to use a different CC mode here. */
4442 compare_mode = SELECT_CC_MODE (new_code, op0, op1);
4443 #endif /* EXTRA_CC_MODES */
4445 #if !defined (HAVE_cc0) && defined (EXTRA_CC_MODES)
4446 /* If the mode changed, we have to change SET_DEST, the mode in the
4447 compare, and the mode in the place SET_DEST is used. If SET_DEST is
4448 a hard register, just build new versions with the proper mode. If it
4449 is a pseudo, we lose unless it is only time we set the pseudo, in
4450 which case we can safely change its mode. */
4451 if (compare_mode != GET_MODE (dest))
4453 int regno = REGNO (dest);
4454 rtx new_dest = gen_rtx (REG, compare_mode, regno);
4456 if (regno < FIRST_PSEUDO_REGISTER
4457 || (REG_N_SETS (regno) == 1 && ! REG_USERVAR_P (dest)))
4459 if (regno >= FIRST_PSEUDO_REGISTER)
4460 SUBST (regno_reg_rtx[regno], new_dest);
4462 SUBST (SET_DEST (x), new_dest);
4463 SUBST (XEXP (*cc_use, 0), new_dest);
4471 /* If the code changed, we have to build a new comparison in
4472 undobuf.other_insn. */
4473 if (new_code != old_code)
4475 unsigned HOST_WIDE_INT mask;
4477 SUBST (*cc_use, gen_rtx_combine (new_code, GET_MODE (*cc_use),
4480 /* If the only change we made was to change an EQ into an NE or
4481 vice versa, OP0 has only one bit that might be nonzero, and OP1
4482 is zero, check if changing the user of the condition code will
4483 produce a valid insn. If it won't, we can keep the original code
4484 in that insn by surrounding our operation with an XOR. */
4486 if (((old_code == NE && new_code == EQ)
4487 || (old_code == EQ && new_code == NE))
4488 && ! other_changed && op1 == const0_rtx
4489 && GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
4490 && exact_log2 (mask = nonzero_bits (op0, GET_MODE (op0))) >= 0)
4492 rtx pat = PATTERN (other_insn), note = 0;
4495 if ((recog_for_combine (&pat, other_insn, ¬e, &scratches) < 0
4496 && ! check_asm_operands (pat)))
4498 PUT_CODE (*cc_use, old_code);
4501 op0 = gen_binary (XOR, GET_MODE (op0), op0, GEN_INT (mask));
4509 undobuf.other_insn = other_insn;
4512 /* If we are now comparing against zero, change our source if
4513 needed. If we do not use cc0, we always have a COMPARE. */
4514 if (op1 == const0_rtx && dest == cc0_rtx)
4516 SUBST (SET_SRC (x), op0);
4522 /* Otherwise, if we didn't previously have a COMPARE in the
4523 correct mode, we need one. */
4524 if (GET_CODE (src) != COMPARE || GET_MODE (src) != compare_mode)
4527 gen_rtx_combine (COMPARE, compare_mode, op0, op1));
4532 /* Otherwise, update the COMPARE if needed. */
4533 SUBST (XEXP (src, 0), op0);
4534 SUBST (XEXP (src, 1), op1);
4539 /* Get SET_SRC in a form where we have placed back any
4540 compound expressions. Then do the checks below. */
4541 src = make_compound_operation (src, SET);
4542 SUBST (SET_SRC (x), src);
4545 /* If we have (set x (subreg:m1 (op:m2 ...) 0)) with OP being some operation,
4546 and X being a REG or (subreg (reg)), we may be able to convert this to
4547 (set (subreg:m2 x) (op)).
4549 We can always do this if M1 is narrower than M2 because that means that
4550 we only care about the low bits of the result.
4552 However, on machines without WORD_REGISTER_OPERATIONS defined, we cannot
4553 perform a narrower operation that requested since the high-order bits will
4554 be undefined. On machine where it is defined, this transformation is safe
4555 as long as M1 and M2 have the same number of words. */
4557 if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src)
4558 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (src))) != 'o'
4559 && (((GET_MODE_SIZE (GET_MODE (src)) + (UNITS_PER_WORD - 1))
4561 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (src)))
4562 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD))
4563 #ifndef WORD_REGISTER_OPERATIONS
4564 && (GET_MODE_SIZE (GET_MODE (src))
4565 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (src))))
4567 #ifdef CLASS_CANNOT_CHANGE_SIZE
4568 && ! (GET_CODE (dest) == REG && REGNO (dest) < FIRST_PSEUDO_REGISTER
4569 && (TEST_HARD_REG_BIT
4570 (reg_class_contents[(int) CLASS_CANNOT_CHANGE_SIZE],
4572 && (GET_MODE_SIZE (GET_MODE (src))
4573 != GET_MODE_SIZE (GET_MODE (SUBREG_REG (src)))))
4575 && (GET_CODE (dest) == REG
4576 || (GET_CODE (dest) == SUBREG
4577 && GET_CODE (SUBREG_REG (dest)) == REG)))
4579 SUBST (SET_DEST (x),
4580 gen_lowpart_for_combine (GET_MODE (SUBREG_REG (src)),
4582 SUBST (SET_SRC (x), SUBREG_REG (src));
4584 src = SET_SRC (x), dest = SET_DEST (x);
4587 #ifdef LOAD_EXTEND_OP
4588 /* If we have (set FOO (subreg:M (mem:N BAR) 0)) with M wider than N, this
4589 would require a paradoxical subreg. Replace the subreg with a
4590 zero_extend to avoid the reload that would otherwise be required. */
4592 if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src)
4593 && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src))) != NIL
4594 && SUBREG_WORD (src) == 0
4595 && (GET_MODE_SIZE (GET_MODE (src))
4596 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (src))))
4597 && GET_CODE (SUBREG_REG (src)) == MEM)
4600 gen_rtx_combine (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src))),
4601 GET_MODE (src), XEXP (src, 0)));
4607 /* If we don't have a conditional move, SET_SRC is an IF_THEN_ELSE, and we
4608 are comparing an item known to be 0 or -1 against 0, use a logical
4609 operation instead. Check for one of the arms being an IOR of the other
4610 arm with some value. We compute three terms to be IOR'ed together. In
4611 practice, at most two will be nonzero. Then we do the IOR's. */
4613 if (GET_CODE (dest) != PC
4614 && GET_CODE (src) == IF_THEN_ELSE
4615 && GET_MODE_CLASS (GET_MODE (src)) == MODE_INT
4616 && (GET_CODE (XEXP (src, 0)) == EQ || GET_CODE (XEXP (src, 0)) == NE)
4617 && XEXP (XEXP (src, 0), 1) == const0_rtx
4618 && GET_MODE (src) == GET_MODE (XEXP (XEXP (src, 0), 0))
4619 #ifdef HAVE_conditional_move
4620 && ! can_conditionally_move_p (GET_MODE (src))
4622 && (num_sign_bit_copies (XEXP (XEXP (src, 0), 0),
4623 GET_MODE (XEXP (XEXP (src, 0), 0)))
4624 == GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (src, 0), 0))))
4625 && ! side_effects_p (src))
4627 rtx true = (GET_CODE (XEXP (src, 0)) == NE
4628 ? XEXP (src, 1) : XEXP (src, 2));
4629 rtx false = (GET_CODE (XEXP (src, 0)) == NE
4630 ? XEXP (src, 2) : XEXP (src, 1));
4631 rtx term1 = const0_rtx, term2, term3;
4633 if (GET_CODE (true) == IOR && rtx_equal_p (XEXP (true, 0), false))
4634 term1 = false, true = XEXP (true, 1), false = const0_rtx;
4635 else if (GET_CODE (true) == IOR
4636 && rtx_equal_p (XEXP (true, 1), false))
4637 term1 = false, true = XEXP (true, 0), false = const0_rtx;
4638 else if (GET_CODE (false) == IOR
4639 && rtx_equal_p (XEXP (false, 0), true))
4640 term1 = true, false = XEXP (false, 1), true = const0_rtx;
4641 else if (GET_CODE (false) == IOR
4642 && rtx_equal_p (XEXP (false, 1), true))
4643 term1 = true, false = XEXP (false, 0), true = const0_rtx;
4645 term2 = gen_binary (AND, GET_MODE (src), XEXP (XEXP (src, 0), 0), true);
4646 term3 = gen_binary (AND, GET_MODE (src),
4647 gen_unary (NOT, GET_MODE (src), GET_MODE (src),
4648 XEXP (XEXP (src, 0), 0)),
4652 gen_binary (IOR, GET_MODE (src),
4653 gen_binary (IOR, GET_MODE (src), term1, term2),
4659 /* If either SRC or DEST is a CLOBBER of (const_int 0), make this
4660 whole thing fail. */
4661 if (GET_CODE (src) == CLOBBER && XEXP (src, 0) == const0_rtx)
4663 else if (GET_CODE (dest) == CLOBBER && XEXP (dest, 0) == const0_rtx)
4666 /* Convert this into a field assignment operation, if possible. */
4667 return make_field_assignment (x);
4670 /* Simplify, X, and AND, IOR, or XOR operation, and return the simplified
4671 result. LAST is nonzero if this is the last retry. */
4674 simplify_logical (x, last)
4678 enum machine_mode mode = GET_MODE (x);
4679 rtx op0 = XEXP (x, 0);
4680 rtx op1 = XEXP (x, 1);
4682 switch (GET_CODE (x))
4685 /* Convert (A ^ B) & A to A & (~ B) since the latter is often a single
4686 insn (and may simplify more). */
4687 if (GET_CODE (op0) == XOR
4688 && rtx_equal_p (XEXP (op0, 0), op1)
4689 && ! side_effects_p (op1))
4690 x = gen_binary (AND, mode,
4691 gen_unary (NOT, mode, mode, XEXP (op0, 1)), op1);
4693 if (GET_CODE (op0) == XOR
4694 && rtx_equal_p (XEXP (op0, 1), op1)
4695 && ! side_effects_p (op1))
4696 x = gen_binary (AND, mode,
4697 gen_unary (NOT, mode, mode, XEXP (op0, 0)), op1);
4699 /* Similarly for (~ (A ^ B)) & A. */
4700 if (GET_CODE (op0) == NOT
4701 && GET_CODE (XEXP (op0, 0)) == XOR
4702 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), op1)
4703 && ! side_effects_p (op1))
4704 x = gen_binary (AND, mode, XEXP (XEXP (op0, 0), 1), op1);
4706 if (GET_CODE (op0) == NOT
4707 && GET_CODE (XEXP (op0, 0)) == XOR
4708 && rtx_equal_p (XEXP (XEXP (op0, 0), 1), op1)
4709 && ! side_effects_p (op1))
4710 x = gen_binary (AND, mode, XEXP (XEXP (op0, 0), 0), op1);
4712 if (GET_CODE (op1) == CONST_INT)
4714 x = simplify_and_const_int (x, mode, op0, INTVAL (op1));
4716 /* If we have (ior (and (X C1) C2)) and the next restart would be
4717 the last, simplify this by making C1 as small as possible
4720 && GET_CODE (x) == IOR && GET_CODE (op0) == AND
4721 && GET_CODE (XEXP (op0, 1)) == CONST_INT
4722 && GET_CODE (op1) == CONST_INT)
4723 return gen_binary (IOR, mode,
4724 gen_binary (AND, mode, XEXP (op0, 0),
4725 GEN_INT (INTVAL (XEXP (op0, 1))
4726 & ~ INTVAL (op1))), op1);
4728 if (GET_CODE (x) != AND)
4731 if (GET_RTX_CLASS (GET_CODE (x)) == 'c'
4732 || GET_RTX_CLASS (GET_CODE (x)) == '2')
4733 op0 = XEXP (x, 0), op1 = XEXP (x, 1);
4736 /* Convert (A | B) & A to A. */
4737 if (GET_CODE (op0) == IOR
4738 && (rtx_equal_p (XEXP (op0, 0), op1)
4739 || rtx_equal_p (XEXP (op0, 1), op1))
4740 && ! side_effects_p (XEXP (op0, 0))
4741 && ! side_effects_p (XEXP (op0, 1)))
4744 /* In the following group of tests (and those in case IOR below),
4745 we start with some combination of logical operations and apply
4746 the distributive law followed by the inverse distributive law.
4747 Most of the time, this results in no change. However, if some of
4748 the operands are the same or inverses of each other, simplifications
4751 For example, (and (ior A B) (not B)) can occur as the result of
4752 expanding a bit field assignment. When we apply the distributive
4753 law to this, we get (ior (and (A (not B))) (and (B (not B)))),
4754 which then simplifies to (and (A (not B))).
4756 If we have (and (ior A B) C), apply the distributive law and then
4757 the inverse distributive law to see if things simplify. */
4759 if (GET_CODE (op0) == IOR || GET_CODE (op0) == XOR)
4761 x = apply_distributive_law
4762 (gen_binary (GET_CODE (op0), mode,
4763 gen_binary (AND, mode, XEXP (op0, 0), op1),
4764 gen_binary (AND, mode, XEXP (op0, 1), op1)));
4765 if (GET_CODE (x) != AND)
4769 if (GET_CODE (op1) == IOR || GET_CODE (op1) == XOR)
4770 return apply_distributive_law
4771 (gen_binary (GET_CODE (op1), mode,
4772 gen_binary (AND, mode, XEXP (op1, 0), op0),
4773 gen_binary (AND, mode, XEXP (op1, 1), op0)));
4775 /* Similarly, taking advantage of the fact that
4776 (and (not A) (xor B C)) == (xor (ior A B) (ior A C)) */
4778 if (GET_CODE (op0) == NOT && GET_CODE (op1) == XOR)
4779 return apply_distributive_law
4780 (gen_binary (XOR, mode,
4781 gen_binary (IOR, mode, XEXP (op0, 0), XEXP (op1, 0)),
4782 gen_binary (IOR, mode, XEXP (op0, 0), XEXP (op1, 1))));
4784 else if (GET_CODE (op1) == NOT && GET_CODE (op0) == XOR)
4785 return apply_distributive_law
4786 (gen_binary (XOR, mode,
4787 gen_binary (IOR, mode, XEXP (op1, 0), XEXP (op0, 0)),
4788 gen_binary (IOR, mode, XEXP (op1, 0), XEXP (op0, 1))));
4792 /* (ior A C) is C if all bits of A that might be nonzero are on in C. */
4793 if (GET_CODE (op1) == CONST_INT
4794 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4795 && (nonzero_bits (op0, mode) & ~ INTVAL (op1)) == 0)
4798 /* Convert (A & B) | A to A. */
4799 if (GET_CODE (op0) == AND
4800 && (rtx_equal_p (XEXP (op0, 0), op1)
4801 || rtx_equal_p (XEXP (op0, 1), op1))
4802 && ! side_effects_p (XEXP (op0, 0))
4803 && ! side_effects_p (XEXP (op0, 1)))
4806 /* If we have (ior (and A B) C), apply the distributive law and then
4807 the inverse distributive law to see if things simplify. */
4809 if (GET_CODE (op0) == AND)
4811 x = apply_distributive_law
4812 (gen_binary (AND, mode,
4813 gen_binary (IOR, mode, XEXP (op0, 0), op1),
4814 gen_binary (IOR, mode, XEXP (op0, 1), op1)));
4816 if (GET_CODE (x) != IOR)
4820 if (GET_CODE (op1) == AND)
4822 x = apply_distributive_law
4823 (gen_binary (AND, mode,
4824 gen_binary (IOR, mode, XEXP (op1, 0), op0),
4825 gen_binary (IOR, mode, XEXP (op1, 1), op0)));
4827 if (GET_CODE (x) != IOR)
4831 /* Convert (ior (ashift A CX) (lshiftrt A CY)) where CX+CY equals the
4832 mode size to (rotate A CX). */
4834 if (((GET_CODE (op0) == ASHIFT && GET_CODE (op1) == LSHIFTRT)
4835 || (GET_CODE (op1) == ASHIFT && GET_CODE (op0) == LSHIFTRT))
4836 && rtx_equal_p (XEXP (op0, 0), XEXP (op1, 0))
4837 && GET_CODE (XEXP (op0, 1)) == CONST_INT
4838 && GET_CODE (XEXP (op1, 1)) == CONST_INT
4839 && (INTVAL (XEXP (op0, 1)) + INTVAL (XEXP (op1, 1))
4840 == GET_MODE_BITSIZE (mode)))
4841 return gen_rtx (ROTATE, mode, XEXP (op0, 0),
4842 (GET_CODE (op0) == ASHIFT
4843 ? XEXP (op0, 1) : XEXP (op1, 1)));
4845 /* If OP0 is (ashiftrt (plus ...) C), it might actually be
4846 a (sign_extend (plus ...)). If so, OP1 is a CONST_INT, and the PLUS
4847 does not affect any of the bits in OP1, it can really be done
4848 as a PLUS and we can associate. We do this by seeing if OP1
4849 can be safely shifted left C bits. */
4850 if (GET_CODE (op1) == CONST_INT && GET_CODE (op0) == ASHIFTRT
4851 && GET_CODE (XEXP (op0, 0)) == PLUS
4852 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
4853 && GET_CODE (XEXP (op0, 1)) == CONST_INT
4854 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT)
4856 int count = INTVAL (XEXP (op0, 1));
4857 HOST_WIDE_INT mask = INTVAL (op1) << count;
4859 if (mask >> count == INTVAL (op1)
4860 && (mask & nonzero_bits (XEXP (op0, 0), mode)) == 0)
4862 SUBST (XEXP (XEXP (op0, 0), 1),
4863 GEN_INT (INTVAL (XEXP (XEXP (op0, 0), 1)) | mask));
4870 /* Convert (XOR (NOT x) (NOT y)) to (XOR x y).
4871 Also convert (XOR (NOT x) y) to (NOT (XOR x y)), similarly for
4874 int num_negated = 0;
4876 if (GET_CODE (op0) == NOT)
4877 num_negated++, op0 = XEXP (op0, 0);
4878 if (GET_CODE (op1) == NOT)
4879 num_negated++, op1 = XEXP (op1, 0);
4881 if (num_negated == 2)
4883 SUBST (XEXP (x, 0), op0);
4884 SUBST (XEXP (x, 1), op1);
4886 else if (num_negated == 1)
4887 return gen_unary (NOT, mode, mode, gen_binary (XOR, mode, op0, op1));
4890 /* Convert (xor (and A B) B) to (and (not A) B). The latter may
4891 correspond to a machine insn or result in further simplifications
4892 if B is a constant. */
4894 if (GET_CODE (op0) == AND
4895 && rtx_equal_p (XEXP (op0, 1), op1)
4896 && ! side_effects_p (op1))
4897 return gen_binary (AND, mode,
4898 gen_unary (NOT, mode, mode, XEXP (op0, 0)),
4901 else if (GET_CODE (op0) == AND
4902 && rtx_equal_p (XEXP (op0, 0), op1)
4903 && ! side_effects_p (op1))
4904 return gen_binary (AND, mode,
4905 gen_unary (NOT, mode, mode, XEXP (op0, 1)),
4908 /* (xor (comparison foo bar) (const_int 1)) can become the reversed
4909 comparison if STORE_FLAG_VALUE is 1. */
4910 if (STORE_FLAG_VALUE == 1
4911 && op1 == const1_rtx
4912 && GET_RTX_CLASS (GET_CODE (op0)) == '<'
4913 && reversible_comparison_p (op0))
4914 return gen_rtx_combine (reverse_condition (GET_CODE (op0)),
4915 mode, XEXP (op0, 0), XEXP (op0, 1));
4917 /* (lshiftrt foo C) where C is the number of bits in FOO minus 1
4918 is (lt foo (const_int 0)), so we can perform the above
4919 simplification if STORE_FLAG_VALUE is 1. */
4921 if (STORE_FLAG_VALUE == 1
4922 && op1 == const1_rtx
4923 && GET_CODE (op0) == LSHIFTRT
4924 && GET_CODE (XEXP (op0, 1)) == CONST_INT
4925 && INTVAL (XEXP (op0, 1)) == GET_MODE_BITSIZE (mode) - 1)
4926 return gen_rtx_combine (GE, mode, XEXP (op0, 0), const0_rtx);
4928 /* (xor (comparison foo bar) (const_int sign-bit))
4929 when STORE_FLAG_VALUE is the sign bit. */
4930 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4931 && ((STORE_FLAG_VALUE & GET_MODE_MASK (mode))
4932 == (HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (mode) - 1))
4933 && op1 == const_true_rtx
4934 && GET_RTX_CLASS (GET_CODE (op0)) == '<'
4935 && reversible_comparison_p (op0))
4936 return gen_rtx_combine (reverse_condition (GET_CODE (op0)),
4937 mode, XEXP (op0, 0), XEXP (op0, 1));
4944 /* We consider ZERO_EXTRACT, SIGN_EXTRACT, and SIGN_EXTEND as "compound
4945 operations" because they can be replaced with two more basic operations.
4946 ZERO_EXTEND is also considered "compound" because it can be replaced with
4947 an AND operation, which is simpler, though only one operation.
4949 The function expand_compound_operation is called with an rtx expression
4950 and will convert it to the appropriate shifts and AND operations,
4951 simplifying at each stage.
4953 The function make_compound_operation is called to convert an expression
4954 consisting of shifts and ANDs into the equivalent compound expression.
4955 It is the inverse of this function, loosely speaking. */
4958 expand_compound_operation (x)
4966 switch (GET_CODE (x))
4971 /* We can't necessarily use a const_int for a multiword mode;
4972 it depends on implicitly extending the value.
4973 Since we don't know the right way to extend it,
4974 we can't tell whether the implicit way is right.
4976 Even for a mode that is no wider than a const_int,
4977 we can't win, because we need to sign extend one of its bits through
4978 the rest of it, and we don't know which bit. */
4979 if (GET_CODE (XEXP (x, 0)) == CONST_INT)
4982 /* Return if (subreg:MODE FROM 0) is not a safe replacement for
4983 (zero_extend:MODE FROM) or (sign_extend:MODE FROM). It is for any MEM
4984 because (SUBREG (MEM...)) is guaranteed to cause the MEM to be
4985 reloaded. If not for that, MEM's would very rarely be safe.
4987 Reject MODEs bigger than a word, because we might not be able
4988 to reference a two-register group starting with an arbitrary register
4989 (and currently gen_lowpart might crash for a SUBREG). */
4991 if (GET_MODE_SIZE (GET_MODE (XEXP (x, 0))) > UNITS_PER_WORD)
4994 len = GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)));
4995 /* If the inner object has VOIDmode (the only way this can happen
4996 is if it is a ASM_OPERANDS), we can't do anything since we don't
4997 know how much masking to do. */
5006 /* If the operand is a CLOBBER, just return it. */
5007 if (GET_CODE (XEXP (x, 0)) == CLOBBER)
5010 if (GET_CODE (XEXP (x, 1)) != CONST_INT
5011 || GET_CODE (XEXP (x, 2)) != CONST_INT
5012 || GET_MODE (XEXP (x, 0)) == VOIDmode)
5015 len = INTVAL (XEXP (x, 1));
5016 pos = INTVAL (XEXP (x, 2));
5018 /* If this goes outside the object being extracted, replace the object
5019 with a (use (mem ...)) construct that only combine understands
5020 and is used only for this purpose. */
5021 if (len + pos > GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))))
5022 SUBST (XEXP (x, 0), gen_rtx (USE, GET_MODE (x), XEXP (x, 0)));
5024 if (BITS_BIG_ENDIAN)
5025 pos = GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - len - pos;
5033 /* We can optimize some special cases of ZERO_EXTEND. */
5034 if (GET_CODE (x) == ZERO_EXTEND)
5036 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI if we
5037 know that the last value didn't have any inappropriate bits
5039 if (GET_CODE (XEXP (x, 0)) == TRUNCATE
5040 && GET_MODE (XEXP (XEXP (x, 0), 0)) == GET_MODE (x)
5041 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
5042 && (nonzero_bits (XEXP (XEXP (x, 0), 0), GET_MODE (x))
5043 & ~ GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5044 return XEXP (XEXP (x, 0), 0);
5046 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
5047 if (GET_CODE (XEXP (x, 0)) == SUBREG
5048 && GET_MODE (SUBREG_REG (XEXP (x, 0))) == GET_MODE (x)
5049 && subreg_lowpart_p (XEXP (x, 0))
5050 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
5051 && (nonzero_bits (SUBREG_REG (XEXP (x, 0)), GET_MODE (x))
5052 & ~ GET_MODE_MASK (GET_MODE (SUBREG_REG (x)))) == 0)
5053 return SUBREG_REG (XEXP (x, 0));
5055 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI when foo
5056 is a comparison and STORE_FLAG_VALUE permits. This is like
5057 the first case, but it works even when GET_MODE (x) is larger
5058 than HOST_WIDE_INT. */
5059 if (GET_CODE (XEXP (x, 0)) == TRUNCATE
5060 && GET_MODE (XEXP (XEXP (x, 0), 0)) == GET_MODE (x)
5061 && GET_RTX_CLASS (GET_CODE (XEXP (XEXP (x, 0), 0))) == '<'
5062 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
5063 <= HOST_BITS_PER_WIDE_INT)
5064 && ((HOST_WIDE_INT) STORE_FLAG_VALUE
5065 & ~ GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5066 return XEXP (XEXP (x, 0), 0);
5068 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
5069 if (GET_CODE (XEXP (x, 0)) == SUBREG
5070 && GET_MODE (SUBREG_REG (XEXP (x, 0))) == GET_MODE (x)
5071 && subreg_lowpart_p (XEXP (x, 0))
5072 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 0)))) == '<'
5073 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
5074 <= HOST_BITS_PER_WIDE_INT)
5075 && ((HOST_WIDE_INT) STORE_FLAG_VALUE
5076 & ~ GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5077 return SUBREG_REG (XEXP (x, 0));
5079 /* If sign extension is cheaper than zero extension, then use it
5080 if we know that no extraneous bits are set, and that the high
5082 if (flag_expensive_optimizations
5083 && ((GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
5084 && ((nonzero_bits (XEXP (x, 0), GET_MODE (x))
5085 & ~ (((unsigned HOST_WIDE_INT)
5086 GET_MODE_MASK (GET_MODE (XEXP (x, 0))))
5089 || (GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
5090 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
5091 <= HOST_BITS_PER_WIDE_INT)
5092 && (((HOST_WIDE_INT) STORE_FLAG_VALUE
5093 & ~ (((unsigned HOST_WIDE_INT)
5094 GET_MODE_MASK (GET_MODE (XEXP (x, 0))))
5098 rtx temp = gen_rtx (SIGN_EXTEND, GET_MODE (x), XEXP (x, 0));
5100 if (rtx_cost (temp, SET) < rtx_cost (x, SET))
5101 return expand_compound_operation (temp);
5105 /* If we reach here, we want to return a pair of shifts. The inner
5106 shift is a left shift of BITSIZE - POS - LEN bits. The outer
5107 shift is a right shift of BITSIZE - LEN bits. It is arithmetic or
5108 logical depending on the value of UNSIGNEDP.
5110 If this was a ZERO_EXTEND or ZERO_EXTRACT, this pair of shifts will be
5111 converted into an AND of a shift.
5113 We must check for the case where the left shift would have a negative
5114 count. This can happen in a case like (x >> 31) & 255 on machines
5115 that can't shift by a constant. On those machines, we would first
5116 combine the shift with the AND to produce a variable-position
5117 extraction. Then the constant of 31 would be substituted in to produce
5118 a such a position. */
5120 modewidth = GET_MODE_BITSIZE (GET_MODE (x));
5121 if (modewidth >= pos - len)
5122 tem = simplify_shift_const (NULL_RTX, unsignedp ? LSHIFTRT : ASHIFTRT,
5124 simplify_shift_const (NULL_RTX, ASHIFT,
5127 modewidth - pos - len),
5130 else if (unsignedp && len < HOST_BITS_PER_WIDE_INT)
5131 tem = simplify_and_const_int (NULL_RTX, GET_MODE (x),
5132 simplify_shift_const (NULL_RTX, LSHIFTRT,
5135 ((HOST_WIDE_INT) 1 << len) - 1);
5137 /* Any other cases we can't handle. */
5141 /* If we couldn't do this for some reason, return the original
5143 if (GET_CODE (tem) == CLOBBER)
5149 /* X is a SET which contains an assignment of one object into
5150 a part of another (such as a bit-field assignment, STRICT_LOW_PART,
5151 or certain SUBREGS). If possible, convert it into a series of
5154 We half-heartedly support variable positions, but do not at all
5155 support variable lengths. */
5158 expand_field_assignment (x)
5162 rtx pos; /* Always counts from low bit. */
5165 enum machine_mode compute_mode;
5167 /* Loop until we find something we can't simplify. */
5170 if (GET_CODE (SET_DEST (x)) == STRICT_LOW_PART
5171 && GET_CODE (XEXP (SET_DEST (x), 0)) == SUBREG)
5173 inner = SUBREG_REG (XEXP (SET_DEST (x), 0));
5174 len = GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0)));
5175 pos = GEN_INT (BITS_PER_WORD * SUBREG_WORD (XEXP (SET_DEST (x), 0)));
5177 else if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
5178 && GET_CODE (XEXP (SET_DEST (x), 1)) == CONST_INT)
5180 inner = XEXP (SET_DEST (x), 0);
5181 len = INTVAL (XEXP (SET_DEST (x), 1));
5182 pos = XEXP (SET_DEST (x), 2);
5184 /* If the position is constant and spans the width of INNER,
5185 surround INNER with a USE to indicate this. */
5186 if (GET_CODE (pos) == CONST_INT
5187 && INTVAL (pos) + len > GET_MODE_BITSIZE (GET_MODE (inner)))
5188 inner = gen_rtx (USE, GET_MODE (SET_DEST (x)), inner);
5190 if (BITS_BIG_ENDIAN)
5192 if (GET_CODE (pos) == CONST_INT)
5193 pos = GEN_INT (GET_MODE_BITSIZE (GET_MODE (inner)) - len
5195 else if (GET_CODE (pos) == MINUS
5196 && GET_CODE (XEXP (pos, 1)) == CONST_INT
5197 && (INTVAL (XEXP (pos, 1))
5198 == GET_MODE_BITSIZE (GET_MODE (inner)) - len))
5199 /* If position is ADJUST - X, new position is X. */
5200 pos = XEXP (pos, 0);
5202 pos = gen_binary (MINUS, GET_MODE (pos),
5203 GEN_INT (GET_MODE_BITSIZE (GET_MODE (inner))
5209 /* A SUBREG between two modes that occupy the same numbers of words
5210 can be done by moving the SUBREG to the source. */
5211 else if (GET_CODE (SET_DEST (x)) == SUBREG
5212 && (((GET_MODE_SIZE (GET_MODE (SET_DEST (x)))
5213 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
5214 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x))))
5215 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)))
5217 x = gen_rtx (SET, VOIDmode, SUBREG_REG (SET_DEST (x)),
5218 gen_lowpart_for_combine (GET_MODE (SUBREG_REG (SET_DEST (x))),
5225 while (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
5226 inner = SUBREG_REG (inner);
5228 compute_mode = GET_MODE (inner);
5230 /* Compute a mask of LEN bits, if we can do this on the host machine. */
5231 if (len < HOST_BITS_PER_WIDE_INT)
5232 mask = GEN_INT (((HOST_WIDE_INT) 1 << len) - 1);
5236 /* Now compute the equivalent expression. Make a copy of INNER
5237 for the SET_DEST in case it is a MEM into which we will substitute;
5238 we don't want shared RTL in that case. */
5239 x = gen_rtx (SET, VOIDmode, copy_rtx (inner),
5240 gen_binary (IOR, compute_mode,
5241 gen_binary (AND, compute_mode,
5242 gen_unary (NOT, compute_mode,
5248 gen_binary (ASHIFT, compute_mode,
5249 gen_binary (AND, compute_mode,
5250 gen_lowpart_for_combine
5260 /* Return an RTX for a reference to LEN bits of INNER. If POS_RTX is nonzero,
5261 it is an RTX that represents a variable starting position; otherwise,
5262 POS is the (constant) starting bit position (counted from the LSB).
5264 INNER may be a USE. This will occur when we started with a bitfield
5265 that went outside the boundary of the object in memory, which is
5266 allowed on most machines. To isolate this case, we produce a USE
5267 whose mode is wide enough and surround the MEM with it. The only
5268 code that understands the USE is this routine. If it is not removed,
5269 it will cause the resulting insn not to match.
5271 UNSIGNEDP is non-zero for an unsigned reference and zero for a
5274 IN_DEST is non-zero if this is a reference in the destination of a
5275 SET. This is used when a ZERO_ or SIGN_EXTRACT isn't needed. If non-zero,
5276 a STRICT_LOW_PART will be used, if zero, ZERO_EXTEND or SIGN_EXTEND will
5279 IN_COMPARE is non-zero if we are in a COMPARE. This means that a
5280 ZERO_EXTRACT should be built even for bits starting at bit 0.
5282 MODE is the desired mode of the result (if IN_DEST == 0).
5284 The result is an RTX for the extraction or NULL_RTX if the target
5288 make_extraction (mode, inner, pos, pos_rtx, len,
5289 unsignedp, in_dest, in_compare)
5290 enum machine_mode mode;
5296 int in_dest, in_compare;
5298 /* This mode describes the size of the storage area
5299 to fetch the overall value from. Within that, we
5300 ignore the POS lowest bits, etc. */
5301 enum machine_mode is_mode = GET_MODE (inner);
5302 enum machine_mode inner_mode;
5303 enum machine_mode wanted_inner_mode = byte_mode;
5304 enum machine_mode wanted_inner_reg_mode = word_mode;
5305 enum machine_mode pos_mode = word_mode;
5306 enum machine_mode extraction_mode = word_mode;
5307 enum machine_mode tmode = mode_for_size (len, MODE_INT, 1);
5310 rtx orig_pos_rtx = pos_rtx;
5313 /* Get some information about INNER and get the innermost object. */
5314 if (GET_CODE (inner) == USE)
5315 /* (use:SI (mem:QI foo)) stands for (mem:SI foo). */
5316 /* We don't need to adjust the position because we set up the USE
5317 to pretend that it was a full-word object. */
5318 spans_byte = 1, inner = XEXP (inner, 0);
5319 else if (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
5321 /* If going from (subreg:SI (mem:QI ...)) to (mem:QI ...),
5322 consider just the QI as the memory to extract from.
5323 The subreg adds or removes high bits; its mode is
5324 irrelevant to the meaning of this extraction,
5325 since POS and LEN count from the lsb. */
5326 if (GET_CODE (SUBREG_REG (inner)) == MEM)
5327 is_mode = GET_MODE (SUBREG_REG (inner));
5328 inner = SUBREG_REG (inner);
5331 inner_mode = GET_MODE (inner);
5333 if (pos_rtx && GET_CODE (pos_rtx) == CONST_INT)
5334 pos = INTVAL (pos_rtx), pos_rtx = 0;
5336 /* See if this can be done without an extraction. We never can if the
5337 width of the field is not the same as that of some integer mode. For
5338 registers, we can only avoid the extraction if the position is at the
5339 low-order bit and this is either not in the destination or we have the
5340 appropriate STRICT_LOW_PART operation available.
5342 For MEM, we can avoid an extract if the field starts on an appropriate
5343 boundary and we can change the mode of the memory reference. However,
5344 we cannot directly access the MEM if we have a USE and the underlying
5345 MEM is not TMODE. This combination means that MEM was being used in a
5346 context where bits outside its mode were being referenced; that is only
5347 valid in bit-field insns. */
5349 if (tmode != BLKmode
5350 && ! (spans_byte && inner_mode != tmode)
5351 && ((pos_rtx == 0 && (pos % BITS_PER_WORD) == 0
5352 && GET_CODE (inner) != MEM
5354 || (GET_CODE (inner) == REG
5355 && (movstrict_optab->handlers[(int) tmode].insn_code
5356 != CODE_FOR_nothing))))
5357 || (GET_CODE (inner) == MEM && pos_rtx == 0
5359 % (STRICT_ALIGNMENT ? GET_MODE_ALIGNMENT (tmode)
5360 : BITS_PER_UNIT)) == 0
5361 /* We can't do this if we are widening INNER_MODE (it
5362 may not be aligned, for one thing). */
5363 && GET_MODE_BITSIZE (inner_mode) >= GET_MODE_BITSIZE (tmode)
5364 && (inner_mode == tmode
5365 || (! mode_dependent_address_p (XEXP (inner, 0))
5366 && ! MEM_VOLATILE_P (inner))))))
5368 /* If INNER is a MEM, make a new MEM that encompasses just the desired
5369 field. If the original and current mode are the same, we need not
5370 adjust the offset. Otherwise, we do if bytes big endian.
5372 If INNER is not a MEM, get a piece consisting of just the field
5373 of interest (in this case POS % BITS_PER_WORD must be 0). */
5375 if (GET_CODE (inner) == MEM)
5378 /* POS counts from lsb, but make OFFSET count in memory order. */
5379 if (BYTES_BIG_ENDIAN)
5380 offset = (GET_MODE_BITSIZE (is_mode) - len - pos) / BITS_PER_UNIT;
5382 offset = pos / BITS_PER_UNIT;
5384 new = gen_rtx (MEM, tmode, plus_constant (XEXP (inner, 0), offset));
5385 RTX_UNCHANGING_P (new) = RTX_UNCHANGING_P (inner);
5386 MEM_VOLATILE_P (new) = MEM_VOLATILE_P (inner);
5387 MEM_IN_STRUCT_P (new) = MEM_IN_STRUCT_P (inner);
5389 else if (GET_CODE (inner) == REG)
5391 /* We can't call gen_lowpart_for_combine here since we always want
5392 a SUBREG and it would sometimes return a new hard register. */
5393 if (tmode != inner_mode)
5394 new = gen_rtx (SUBREG, tmode, inner,
5396 && GET_MODE_SIZE (inner_mode) > UNITS_PER_WORD
5397 ? (((GET_MODE_SIZE (inner_mode)
5398 - GET_MODE_SIZE (tmode))
5400 - pos / BITS_PER_WORD)
5401 : pos / BITS_PER_WORD));
5406 new = force_to_mode (inner, tmode,
5407 len >= HOST_BITS_PER_WIDE_INT
5408 ? GET_MODE_MASK (tmode)
5409 : ((HOST_WIDE_INT) 1 << len) - 1,
5412 /* If this extraction is going into the destination of a SET,
5413 make a STRICT_LOW_PART unless we made a MEM. */
5416 return (GET_CODE (new) == MEM ? new
5417 : (GET_CODE (new) != SUBREG
5418 ? gen_rtx (CLOBBER, tmode, const0_rtx)
5419 : gen_rtx_combine (STRICT_LOW_PART, VOIDmode, new)));
5421 /* Otherwise, sign- or zero-extend unless we already are in the
5424 return (mode == tmode ? new
5425 : gen_rtx_combine (unsignedp ? ZERO_EXTEND : SIGN_EXTEND,
5429 /* Unless this is a COMPARE or we have a funny memory reference,
5430 don't do anything with zero-extending field extracts starting at
5431 the low-order bit since they are simple AND operations. */
5432 if (pos_rtx == 0 && pos == 0 && ! in_dest
5433 && ! in_compare && ! spans_byte && unsignedp)
5436 /* Unless we are allowed to span bytes, reject this if we would be
5437 spanning bytes or if the position is not a constant and the length
5438 is not 1. In all other cases, we would only be going outside
5439 out object in cases when an original shift would have been
5442 && ((pos_rtx == 0 && pos + len > GET_MODE_BITSIZE (is_mode))
5443 || (pos_rtx != 0 && len != 1)))
5446 /* Get the mode to use should INNER not be a MEM, the mode for the position,
5447 and the mode for the result. */
5451 wanted_inner_reg_mode = insn_operand_mode[(int) CODE_FOR_insv][0];
5452 pos_mode = insn_operand_mode[(int) CODE_FOR_insv][2];
5453 extraction_mode = insn_operand_mode[(int) CODE_FOR_insv][3];
5458 if (! in_dest && unsignedp)
5460 wanted_inner_reg_mode = insn_operand_mode[(int) CODE_FOR_extzv][1];
5461 pos_mode = insn_operand_mode[(int) CODE_FOR_extzv][3];
5462 extraction_mode = insn_operand_mode[(int) CODE_FOR_extzv][0];
5467 if (! in_dest && ! unsignedp)
5469 wanted_inner_reg_mode = insn_operand_mode[(int) CODE_FOR_extv][1];
5470 pos_mode = insn_operand_mode[(int) CODE_FOR_extv][3];
5471 extraction_mode = insn_operand_mode[(int) CODE_FOR_extv][0];
5475 /* Never narrow an object, since that might not be safe. */
5477 if (mode != VOIDmode
5478 && GET_MODE_SIZE (extraction_mode) < GET_MODE_SIZE (mode))
5479 extraction_mode = mode;
5481 if (pos_rtx && GET_MODE (pos_rtx) != VOIDmode
5482 && GET_MODE_SIZE (pos_mode) < GET_MODE_SIZE (GET_MODE (pos_rtx)))
5483 pos_mode = GET_MODE (pos_rtx);
5485 /* If this is not from memory, the desired mode is wanted_inner_reg_mode;
5486 if we have to change the mode of memory and cannot, the desired mode is
5488 if (GET_CODE (inner) != MEM)
5489 wanted_inner_mode = wanted_inner_reg_mode;
5490 else if (inner_mode != wanted_inner_mode
5491 && (mode_dependent_address_p (XEXP (inner, 0))
5492 || MEM_VOLATILE_P (inner)))
5493 wanted_inner_mode = extraction_mode;
5497 if (BITS_BIG_ENDIAN)
5499 /* POS is passed as if BITS_BIG_ENDIAN == 0, so we need to convert it to
5500 BITS_BIG_ENDIAN style. If position is constant, compute new
5501 position. Otherwise, build subtraction.
5502 Note that POS is relative to the mode of the original argument.
5503 If it's a MEM we need to recompute POS relative to that.
5504 However, if we're extracting from (or inserting into) a register,
5505 we want to recompute POS relative to wanted_inner_mode. */
5506 int width = (GET_CODE (inner) == MEM
5507 ? GET_MODE_BITSIZE (is_mode)
5508 : GET_MODE_BITSIZE (wanted_inner_mode));
5511 pos = width - len - pos;
5514 = gen_rtx_combine (MINUS, GET_MODE (pos_rtx),
5515 GEN_INT (width - len), pos_rtx);
5516 /* POS may be less than 0 now, but we check for that below.
5517 Note that it can only be less than 0 if GET_CODE (inner) != MEM. */
5520 /* If INNER has a wider mode, make it smaller. If this is a constant
5521 extract, try to adjust the byte to point to the byte containing
5523 if (wanted_inner_mode != VOIDmode
5524 && GET_MODE_SIZE (wanted_inner_mode) < GET_MODE_SIZE (is_mode)
5525 && ((GET_CODE (inner) == MEM
5526 && (inner_mode == wanted_inner_mode
5527 || (! mode_dependent_address_p (XEXP (inner, 0))
5528 && ! MEM_VOLATILE_P (inner))))))
5532 /* The computations below will be correct if the machine is big
5533 endian in both bits and bytes or little endian in bits and bytes.
5534 If it is mixed, we must adjust. */
5536 /* If bytes are big endian and we had a paradoxical SUBREG, we must
5537 adjust OFFSET to compensate. */
5538 if (BYTES_BIG_ENDIAN
5540 && GET_MODE_SIZE (inner_mode) < GET_MODE_SIZE (is_mode))
5541 offset -= GET_MODE_SIZE (is_mode) - GET_MODE_SIZE (inner_mode);
5543 /* If this is a constant position, we can move to the desired byte. */
5546 offset += pos / BITS_PER_UNIT;
5547 pos %= GET_MODE_BITSIZE (wanted_inner_mode);
5550 if (BYTES_BIG_ENDIAN != BITS_BIG_ENDIAN
5552 && is_mode != wanted_inner_mode)
5553 offset = (GET_MODE_SIZE (is_mode)
5554 - GET_MODE_SIZE (wanted_inner_mode) - offset);
5556 if (offset != 0 || inner_mode != wanted_inner_mode)
5558 rtx newmem = gen_rtx (MEM, wanted_inner_mode,
5559 plus_constant (XEXP (inner, 0), offset));
5560 RTX_UNCHANGING_P (newmem) = RTX_UNCHANGING_P (inner);
5561 MEM_VOLATILE_P (newmem) = MEM_VOLATILE_P (inner);
5562 MEM_IN_STRUCT_P (newmem) = MEM_IN_STRUCT_P (inner);
5567 /* If INNER is not memory, we can always get it into the proper mode. If we
5568 are changing its mode, POS must be a constant and smaller than the size
5570 else if (GET_CODE (inner) != MEM)
5572 if (GET_MODE (inner) != wanted_inner_mode
5574 || orig_pos + len > GET_MODE_BITSIZE (wanted_inner_mode)))
5577 inner = force_to_mode (inner, wanted_inner_mode,
5579 || len + orig_pos >= HOST_BITS_PER_WIDE_INT
5580 ? GET_MODE_MASK (wanted_inner_mode)
5581 : (((HOST_WIDE_INT) 1 << len) - 1) << orig_pos,
5585 /* Adjust mode of POS_RTX, if needed. If we want a wider mode, we
5586 have to zero extend. Otherwise, we can just use a SUBREG. */
5588 && GET_MODE_SIZE (pos_mode) > GET_MODE_SIZE (GET_MODE (pos_rtx)))
5589 pos_rtx = gen_rtx_combine (ZERO_EXTEND, pos_mode, pos_rtx);
5590 else if (pos_rtx != 0
5591 && GET_MODE_SIZE (pos_mode) < GET_MODE_SIZE (GET_MODE (pos_rtx)))
5592 pos_rtx = gen_lowpart_for_combine (pos_mode, pos_rtx);
5594 /* Make POS_RTX unless we already have it and it is correct. If we don't
5595 have a POS_RTX but we do have an ORIG_POS_RTX, the latter must
5597 if (pos_rtx == 0 && orig_pos_rtx != 0 && INTVAL (orig_pos_rtx) == pos)
5598 pos_rtx = orig_pos_rtx;
5600 else if (pos_rtx == 0)
5601 pos_rtx = GEN_INT (pos);
5603 /* Make the required operation. See if we can use existing rtx. */
5604 new = gen_rtx_combine (unsignedp ? ZERO_EXTRACT : SIGN_EXTRACT,
5605 extraction_mode, inner, GEN_INT (len), pos_rtx);
5607 new = gen_lowpart_for_combine (mode, new);
5612 /* See if X contains an ASHIFT of COUNT or more bits that can be commuted
5613 with any other operations in X. Return X without that shift if so. */
5616 extract_left_shift (x, count)
5620 enum rtx_code code = GET_CODE (x);
5621 enum machine_mode mode = GET_MODE (x);
5627 /* This is the shift itself. If it is wide enough, we will return
5628 either the value being shifted if the shift count is equal to
5629 COUNT or a shift for the difference. */
5630 if (GET_CODE (XEXP (x, 1)) == CONST_INT
5631 && INTVAL (XEXP (x, 1)) >= count)
5632 return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (x, 0),
5633 INTVAL (XEXP (x, 1)) - count);
5637 if ((tem = extract_left_shift (XEXP (x, 0), count)) != 0)
5638 return gen_unary (code, mode, mode, tem);
5642 case PLUS: case IOR: case XOR: case AND:
5643 /* If we can safely shift this constant and we find the inner shift,
5644 make a new operation. */
5645 if (GET_CODE (XEXP (x,1)) == CONST_INT
5646 && (INTVAL (XEXP (x, 1)) & (((HOST_WIDE_INT) 1 << count)) - 1) == 0
5647 && (tem = extract_left_shift (XEXP (x, 0), count)) != 0)
5648 return gen_binary (code, mode, tem,
5649 GEN_INT (INTVAL (XEXP (x, 1)) >> count));
5657 /* Look at the expression rooted at X. Look for expressions
5658 equivalent to ZERO_EXTRACT, SIGN_EXTRACT, ZERO_EXTEND, SIGN_EXTEND.
5659 Form these expressions.
5661 Return the new rtx, usually just X.
5663 Also, for machines like the Vax that don't have logical shift insns,
5664 try to convert logical to arithmetic shift operations in cases where
5665 they are equivalent. This undoes the canonicalizations to logical
5666 shifts done elsewhere.
5668 We try, as much as possible, to re-use rtl expressions to save memory.
5670 IN_CODE says what kind of expression we are processing. Normally, it is
5671 SET. In a memory address (inside a MEM, PLUS or minus, the latter two
5672 being kludges), it is MEM. When processing the arguments of a comparison
5673 or a COMPARE against zero, it is COMPARE. */
5676 make_compound_operation (x, in_code)
5678 enum rtx_code in_code;
5680 enum rtx_code code = GET_CODE (x);
5681 enum machine_mode mode = GET_MODE (x);
5682 int mode_width = GET_MODE_BITSIZE (mode);
5684 enum rtx_code next_code;
5690 /* Select the code to be used in recursive calls. Once we are inside an
5691 address, we stay there. If we have a comparison, set to COMPARE,
5692 but once inside, go back to our default of SET. */
5694 next_code = (code == MEM || code == PLUS || code == MINUS ? MEM
5695 : ((code == COMPARE || GET_RTX_CLASS (code) == '<')
5696 && XEXP (x, 1) == const0_rtx) ? COMPARE
5697 : in_code == COMPARE ? SET : in_code);
5699 /* Process depending on the code of this operation. If NEW is set
5700 non-zero, it will be returned. */
5705 /* Convert shifts by constants into multiplications if inside
5707 if (in_code == MEM && GET_CODE (XEXP (x, 1)) == CONST_INT
5708 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT
5709 && INTVAL (XEXP (x, 1)) >= 0)
5711 new = make_compound_operation (XEXP (x, 0), next_code);
5712 new = gen_rtx_combine (MULT, mode, new,
5713 GEN_INT ((HOST_WIDE_INT) 1
5714 << INTVAL (XEXP (x, 1))));
5719 /* If the second operand is not a constant, we can't do anything
5721 if (GET_CODE (XEXP (x, 1)) != CONST_INT)
5724 /* If the constant is a power of two minus one and the first operand
5725 is a logical right shift, make an extraction. */
5726 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
5727 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
5729 new = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code);
5730 new = make_extraction (mode, new, 0, XEXP (XEXP (x, 0), 1), i, 1,
5731 0, in_code == COMPARE);
5734 /* Same as previous, but for (subreg (lshiftrt ...)) in first op. */
5735 else if (GET_CODE (XEXP (x, 0)) == SUBREG
5736 && subreg_lowpart_p (XEXP (x, 0))
5737 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == LSHIFTRT
5738 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
5740 new = make_compound_operation (XEXP (SUBREG_REG (XEXP (x, 0)), 0),
5742 new = make_extraction (GET_MODE (SUBREG_REG (XEXP (x, 0))), new, 0,
5743 XEXP (SUBREG_REG (XEXP (x, 0)), 1), i, 1,
5744 0, in_code == COMPARE);
5746 /* Same as previous, but for (xor/ior (lshiftrt...) (lshiftrt...)). */
5747 else if ((GET_CODE (XEXP (x, 0)) == XOR
5748 || GET_CODE (XEXP (x, 0)) == IOR)
5749 && GET_CODE (XEXP (XEXP (x, 0), 0)) == LSHIFTRT
5750 && GET_CODE (XEXP (XEXP (x, 0), 1)) == LSHIFTRT
5751 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
5753 /* Apply the distributive law, and then try to make extractions. */
5754 new = gen_rtx_combine (GET_CODE (XEXP (x, 0)), mode,
5755 gen_rtx (AND, mode, XEXP (XEXP (x, 0), 0),
5757 gen_rtx (AND, mode, XEXP (XEXP (x, 0), 1),
5759 new = make_compound_operation (new, in_code);
5762 /* If we are have (and (rotate X C) M) and C is larger than the number
5763 of bits in M, this is an extraction. */
5765 else if (GET_CODE (XEXP (x, 0)) == ROTATE
5766 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
5767 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0
5768 && i <= INTVAL (XEXP (XEXP (x, 0), 1)))
5770 new = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code);
5771 new = make_extraction (mode, new,
5772 (GET_MODE_BITSIZE (mode)
5773 - INTVAL (XEXP (XEXP (x, 0), 1))),
5774 NULL_RTX, i, 1, 0, in_code == COMPARE);
5777 /* On machines without logical shifts, if the operand of the AND is
5778 a logical shift and our mask turns off all the propagated sign
5779 bits, we can replace the logical shift with an arithmetic shift. */
5780 else if (ashr_optab->handlers[(int) mode].insn_code != CODE_FOR_nothing
5781 && (lshr_optab->handlers[(int) mode].insn_code
5782 == CODE_FOR_nothing)
5783 && GET_CODE (XEXP (x, 0)) == LSHIFTRT
5784 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
5785 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
5786 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT
5787 && mode_width <= HOST_BITS_PER_WIDE_INT)
5789 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
5791 mask >>= INTVAL (XEXP (XEXP (x, 0), 1));
5792 if ((INTVAL (XEXP (x, 1)) & ~mask) == 0)
5794 gen_rtx_combine (ASHIFTRT, mode,
5795 make_compound_operation (XEXP (XEXP (x, 0), 0),
5797 XEXP (XEXP (x, 0), 1)));
5800 /* If the constant is one less than a power of two, this might be
5801 representable by an extraction even if no shift is present.
5802 If it doesn't end up being a ZERO_EXTEND, we will ignore it unless
5803 we are in a COMPARE. */
5804 else if ((i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
5805 new = make_extraction (mode,
5806 make_compound_operation (XEXP (x, 0),
5808 0, NULL_RTX, i, 1, 0, in_code == COMPARE);
5810 /* If we are in a comparison and this is an AND with a power of two,
5811 convert this into the appropriate bit extract. */
5812 else if (in_code == COMPARE
5813 && (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0)
5814 new = make_extraction (mode,
5815 make_compound_operation (XEXP (x, 0),
5817 i, NULL_RTX, 1, 1, 0, 1);
5822 /* If the sign bit is known to be zero, replace this with an
5823 arithmetic shift. */
5824 if (ashr_optab->handlers[(int) mode].insn_code == CODE_FOR_nothing
5825 && lshr_optab->handlers[(int) mode].insn_code != CODE_FOR_nothing
5826 && mode_width <= HOST_BITS_PER_WIDE_INT
5827 && (nonzero_bits (XEXP (x, 0), mode) & (1 << (mode_width - 1))) == 0)
5829 new = gen_rtx_combine (ASHIFTRT, mode,
5830 make_compound_operation (XEXP (x, 0),
5836 /* ... fall through ... */
5842 /* If we have (ashiftrt (ashift foo C1) C2) with C2 >= C1,
5843 this is a SIGN_EXTRACT. */
5844 if (GET_CODE (rhs) == CONST_INT
5845 && GET_CODE (lhs) == ASHIFT
5846 && GET_CODE (XEXP (lhs, 1)) == CONST_INT
5847 && INTVAL (rhs) >= INTVAL (XEXP (lhs, 1)))
5849 new = make_compound_operation (XEXP (lhs, 0), next_code);
5850 new = make_extraction (mode, new,
5851 INTVAL (rhs) - INTVAL (XEXP (lhs, 1)),
5852 NULL_RTX, mode_width - INTVAL (rhs),
5853 code == LSHIFTRT, 0, in_code == COMPARE);
5856 /* See if we have operations between an ASHIFTRT and an ASHIFT.
5857 If so, try to merge the shifts into a SIGN_EXTEND. We could
5858 also do this for some cases of SIGN_EXTRACT, but it doesn't
5859 seem worth the effort; the case checked for occurs on Alpha. */
5861 if (GET_RTX_CLASS (GET_CODE (lhs)) != 'o'
5862 && ! (GET_CODE (lhs) == SUBREG
5863 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (lhs))) == 'o'))
5864 && GET_CODE (rhs) == CONST_INT
5865 && INTVAL (rhs) < HOST_BITS_PER_WIDE_INT
5866 && (new = extract_left_shift (lhs, INTVAL (rhs))) != 0)
5867 new = make_extraction (mode, make_compound_operation (new, next_code),
5868 0, NULL_RTX, mode_width - INTVAL (rhs),
5869 code == LSHIFTRT, 0, in_code == COMPARE);
5874 /* Call ourselves recursively on the inner expression. If we are
5875 narrowing the object and it has a different RTL code from
5876 what it originally did, do this SUBREG as a force_to_mode. */
5878 tem = make_compound_operation (SUBREG_REG (x), in_code);
5879 if (GET_CODE (tem) != GET_CODE (SUBREG_REG (x))
5880 && GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (tem))
5881 && subreg_lowpart_p (x))
5883 rtx newer = force_to_mode (tem, mode,
5884 GET_MODE_MASK (mode), NULL_RTX, 0);
5886 /* If we have something other than a SUBREG, we might have
5887 done an expansion, so rerun outselves. */
5888 if (GET_CODE (newer) != SUBREG)
5889 newer = make_compound_operation (newer, in_code);
5897 x = gen_lowpart_for_combine (mode, new);
5898 code = GET_CODE (x);
5901 /* Now recursively process each operand of this operation. */
5902 fmt = GET_RTX_FORMAT (code);
5903 for (i = 0; i < GET_RTX_LENGTH (code); i++)
5906 new = make_compound_operation (XEXP (x, i), next_code);
5907 SUBST (XEXP (x, i), new);
5913 /* Given M see if it is a value that would select a field of bits
5914 within an item, but not the entire word. Return -1 if not.
5915 Otherwise, return the starting position of the field, where 0 is the
5918 *PLEN is set to the length of the field. */
5921 get_pos_from_mask (m, plen)
5922 unsigned HOST_WIDE_INT m;
5925 /* Get the bit number of the first 1 bit from the right, -1 if none. */
5926 int pos = exact_log2 (m & - m);
5931 /* Now shift off the low-order zero bits and see if we have a power of
5933 *plen = exact_log2 ((m >> pos) + 1);
5941 /* See if X can be simplified knowing that we will only refer to it in
5942 MODE and will only refer to those bits that are nonzero in MASK.
5943 If other bits are being computed or if masking operations are done
5944 that select a superset of the bits in MASK, they can sometimes be
5947 Return a possibly simplified expression, but always convert X to
5948 MODE. If X is a CONST_INT, AND the CONST_INT with MASK.
5950 Also, if REG is non-zero and X is a register equal in value to REG,
5953 If JUST_SELECT is nonzero, don't optimize by noticing that bits in MASK
5954 are all off in X. This is used when X will be complemented, by either
5955 NOT, NEG, or XOR. */
5958 force_to_mode (x, mode, mask, reg, just_select)
5960 enum machine_mode mode;
5961 unsigned HOST_WIDE_INT mask;
5965 enum rtx_code code = GET_CODE (x);
5966 int next_select = just_select || code == XOR || code == NOT || code == NEG;
5967 enum machine_mode op_mode;
5968 unsigned HOST_WIDE_INT fuller_mask, nonzero;
5971 /* If this is a CALL or ASM_OPERANDS, don't do anything. Some of the
5972 code below will do the wrong thing since the mode of such an
5973 expression is VOIDmode. */
5974 if (code == CALL || code == ASM_OPERANDS)
5977 /* We want to perform the operation is its present mode unless we know
5978 that the operation is valid in MODE, in which case we do the operation
5980 op_mode = ((GET_MODE_CLASS (mode) == GET_MODE_CLASS (GET_MODE (x))
5981 && code_to_optab[(int) code] != 0
5982 && (code_to_optab[(int) code]->handlers[(int) mode].insn_code
5983 != CODE_FOR_nothing))
5984 ? mode : GET_MODE (x));
5986 /* It is not valid to do a right-shift in a narrower mode
5987 than the one it came in with. */
5988 if ((code == LSHIFTRT || code == ASHIFTRT)
5989 && GET_MODE_BITSIZE (mode) < GET_MODE_BITSIZE (GET_MODE (x)))
5990 op_mode = GET_MODE (x);
5992 /* Truncate MASK to fit OP_MODE. */
5994 mask &= GET_MODE_MASK (op_mode);
5996 /* When we have an arithmetic operation, or a shift whose count we
5997 do not know, we need to assume that all bit the up to the highest-order
5998 bit in MASK will be needed. This is how we form such a mask. */
6000 fuller_mask = (GET_MODE_BITSIZE (op_mode) >= HOST_BITS_PER_WIDE_INT
6001 ? GET_MODE_MASK (op_mode)
6002 : ((HOST_WIDE_INT) 1 << (floor_log2 (mask) + 1)) - 1);
6004 fuller_mask = ~ (HOST_WIDE_INT) 0;
6006 /* Determine what bits of X are guaranteed to be (non)zero. */
6007 nonzero = nonzero_bits (x, mode);
6009 /* If none of the bits in X are needed, return a zero. */
6010 if (! just_select && (nonzero & mask) == 0)
6013 /* If X is a CONST_INT, return a new one. Do this here since the
6014 test below will fail. */
6015 if (GET_CODE (x) == CONST_INT)
6017 HOST_WIDE_INT cval = INTVAL (x) & mask;
6018 int width = GET_MODE_BITSIZE (mode);
6020 /* If MODE is narrower that HOST_WIDE_INT and CVAL is a negative
6021 number, sign extend it. */
6022 if (width > 0 && width < HOST_BITS_PER_WIDE_INT
6023 && (cval & ((HOST_WIDE_INT) 1 << (width - 1))) != 0)
6024 cval |= (HOST_WIDE_INT) -1 << width;
6026 return GEN_INT (cval);
6029 /* If X is narrower than MODE and we want all the bits in X's mode, just
6030 get X in the proper mode. */
6031 if (GET_MODE_SIZE (GET_MODE (x)) < GET_MODE_SIZE (mode)
6032 && (GET_MODE_MASK (GET_MODE (x)) & ~ mask) == 0)
6033 return gen_lowpart_for_combine (mode, x);
6035 /* If we aren't changing the mode, X is not a SUBREG, and all zero bits in
6036 MASK are already known to be zero in X, we need not do anything. */
6037 if (GET_MODE (x) == mode && code != SUBREG && (~ mask & nonzero) == 0)
6043 /* If X is a (clobber (const_int)), return it since we know we are
6044 generating something that won't match. */
6048 /* X is a (use (mem ..)) that was made from a bit-field extraction that
6049 spanned the boundary of the MEM. If we are now masking so it is
6050 within that boundary, we don't need the USE any more. */
6051 if (! BITS_BIG_ENDIAN
6052 && (mask & ~ GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
6053 return force_to_mode (XEXP (x, 0), mode, mask, reg, next_select);
6060 x = expand_compound_operation (x);
6061 if (GET_CODE (x) != code)
6062 return force_to_mode (x, mode, mask, reg, next_select);
6066 if (reg != 0 && (rtx_equal_p (get_last_value (reg), x)
6067 || rtx_equal_p (reg, get_last_value (x))))
6072 if (subreg_lowpart_p (x)
6073 /* We can ignore the effect of this SUBREG if it narrows the mode or
6074 if the constant masks to zero all the bits the mode doesn't
6076 && ((GET_MODE_SIZE (GET_MODE (x))
6077 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
6079 & GET_MODE_MASK (GET_MODE (x))
6080 & ~ GET_MODE_MASK (GET_MODE (SUBREG_REG (x)))))))
6081 return force_to_mode (SUBREG_REG (x), mode, mask, reg, next_select);
6085 /* If this is an AND with a constant, convert it into an AND
6086 whose constant is the AND of that constant with MASK. If it
6087 remains an AND of MASK, delete it since it is redundant. */
6089 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
6091 x = simplify_and_const_int (x, op_mode, XEXP (x, 0),
6092 mask & INTVAL (XEXP (x, 1)));
6094 /* If X is still an AND, see if it is an AND with a mask that
6095 is just some low-order bits. If so, and it is MASK, we don't
6098 if (GET_CODE (x) == AND && GET_CODE (XEXP (x, 1)) == CONST_INT
6099 && INTVAL (XEXP (x, 1)) == mask)
6102 /* If it remains an AND, try making another AND with the bits
6103 in the mode mask that aren't in MASK turned on. If the
6104 constant in the AND is wide enough, this might make a
6105 cheaper constant. */
6107 if (GET_CODE (x) == AND && GET_CODE (XEXP (x, 1)) == CONST_INT
6108 && GET_MODE_MASK (GET_MODE (x)) != mask
6109 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT)
6111 HOST_WIDE_INT cval = (INTVAL (XEXP (x, 1))
6112 | (GET_MODE_MASK (GET_MODE (x)) & ~ mask));
6113 int width = GET_MODE_BITSIZE (GET_MODE (x));
6116 /* If MODE is narrower that HOST_WIDE_INT and CVAL is a negative
6117 number, sign extend it. */
6118 if (width > 0 && width < HOST_BITS_PER_WIDE_INT
6119 && (cval & ((HOST_WIDE_INT) 1 << (width - 1))) != 0)
6120 cval |= (HOST_WIDE_INT) -1 << width;
6122 y = gen_binary (AND, GET_MODE (x), XEXP (x, 0), GEN_INT (cval));
6123 if (rtx_cost (y, SET) < rtx_cost (x, SET))
6133 /* In (and (plus FOO C1) M), if M is a mask that just turns off
6134 low-order bits (as in an alignment operation) and FOO is already
6135 aligned to that boundary, mask C1 to that boundary as well.
6136 This may eliminate that PLUS and, later, the AND. */
6139 int width = GET_MODE_BITSIZE (mode);
6140 unsigned HOST_WIDE_INT smask = mask;
6142 /* If MODE is narrower than HOST_WIDE_INT and mask is a negative
6143 number, sign extend it. */
6145 if (width < HOST_BITS_PER_WIDE_INT
6146 && (smask & ((HOST_WIDE_INT) 1 << (width - 1))) != 0)
6147 smask |= (HOST_WIDE_INT) -1 << width;
6149 if (GET_CODE (XEXP (x, 1)) == CONST_INT
6150 && exact_log2 (- smask) >= 0
6151 && (nonzero_bits (XEXP (x, 0), mode) & ~ mask) == 0
6152 && (INTVAL (XEXP (x, 1)) & ~ mask) != 0)
6153 return force_to_mode (plus_constant (XEXP (x, 0),
6154 INTVAL (XEXP (x, 1)) & mask),
6155 mode, mask, reg, next_select);
6158 /* ... fall through ... */
6162 /* For PLUS, MINUS and MULT, we need any bits less significant than the
6163 most significant bit in MASK since carries from those bits will
6164 affect the bits we are interested in. */
6170 /* If X is (ior (lshiftrt FOO C1) C2), try to commute the IOR and
6171 LSHIFTRT so we end up with an (and (lshiftrt (ior ...) ...) ...)
6172 operation which may be a bitfield extraction. Ensure that the
6173 constant we form is not wider than the mode of X. */
6175 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
6176 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
6177 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
6178 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT
6179 && GET_CODE (XEXP (x, 1)) == CONST_INT
6180 && ((INTVAL (XEXP (XEXP (x, 0), 1))
6181 + floor_log2 (INTVAL (XEXP (x, 1))))
6182 < GET_MODE_BITSIZE (GET_MODE (x)))
6183 && (INTVAL (XEXP (x, 1))
6184 & ~ nonzero_bits (XEXP (x, 0), GET_MODE (x))) == 0)
6186 temp = GEN_INT ((INTVAL (XEXP (x, 1)) & mask)
6187 << INTVAL (XEXP (XEXP (x, 0), 1)));
6188 temp = gen_binary (GET_CODE (x), GET_MODE (x),
6189 XEXP (XEXP (x, 0), 0), temp);
6190 x = gen_binary (LSHIFTRT, GET_MODE (x), temp,
6191 XEXP (XEXP (x, 0), 1));
6192 return force_to_mode (x, mode, mask, reg, next_select);
6196 /* For most binary operations, just propagate into the operation and
6197 change the mode if we have an operation of that mode. */
6199 op0 = gen_lowpart_for_combine (op_mode,
6200 force_to_mode (XEXP (x, 0), mode, mask,
6202 op1 = gen_lowpart_for_combine (op_mode,
6203 force_to_mode (XEXP (x, 1), mode, mask,
6206 /* If OP1 is a CONST_INT and X is an IOR or XOR, clear bits outside
6207 MASK since OP1 might have been sign-extended but we never want
6208 to turn on extra bits, since combine might have previously relied
6209 on them being off. */
6210 if (GET_CODE (op1) == CONST_INT && (code == IOR || code == XOR)
6211 && (INTVAL (op1) & mask) != 0)
6212 op1 = GEN_INT (INTVAL (op1) & mask);
6214 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
6215 x = gen_binary (code, op_mode, op0, op1);
6219 /* For left shifts, do the same, but just for the first operand.
6220 However, we cannot do anything with shifts where we cannot
6221 guarantee that the counts are smaller than the size of the mode
6222 because such a count will have a different meaning in a
6225 if (! (GET_CODE (XEXP (x, 1)) == CONST_INT
6226 && INTVAL (XEXP (x, 1)) >= 0
6227 && INTVAL (XEXP (x, 1)) < GET_MODE_BITSIZE (mode))
6228 && ! (GET_MODE (XEXP (x, 1)) != VOIDmode
6229 && (nonzero_bits (XEXP (x, 1), GET_MODE (XEXP (x, 1)))
6230 < (unsigned HOST_WIDE_INT) GET_MODE_BITSIZE (mode))))
6233 /* If the shift count is a constant and we can do arithmetic in
6234 the mode of the shift, refine which bits we need. Otherwise, use the
6235 conservative form of the mask. */
6236 if (GET_CODE (XEXP (x, 1)) == CONST_INT
6237 && INTVAL (XEXP (x, 1)) >= 0
6238 && INTVAL (XEXP (x, 1)) < GET_MODE_BITSIZE (op_mode)
6239 && GET_MODE_BITSIZE (op_mode) <= HOST_BITS_PER_WIDE_INT)
6240 mask >>= INTVAL (XEXP (x, 1));
6244 op0 = gen_lowpart_for_combine (op_mode,
6245 force_to_mode (XEXP (x, 0), op_mode,
6246 mask, reg, next_select));
6248 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0))
6249 x = gen_binary (code, op_mode, op0, XEXP (x, 1));
6253 /* Here we can only do something if the shift count is a constant,
6254 this shift constant is valid for the host, and we can do arithmetic
6257 if (GET_CODE (XEXP (x, 1)) == CONST_INT
6258 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT
6259 && GET_MODE_BITSIZE (op_mode) <= HOST_BITS_PER_WIDE_INT)
6261 rtx inner = XEXP (x, 0);
6263 /* Select the mask of the bits we need for the shift operand. */
6264 mask <<= INTVAL (XEXP (x, 1));
6266 /* We can only change the mode of the shift if we can do arithmetic
6267 in the mode of the shift and MASK is no wider than the width of
6269 if (GET_MODE_BITSIZE (op_mode) > HOST_BITS_PER_WIDE_INT
6270 || (mask & ~ GET_MODE_MASK (op_mode)) != 0)
6271 op_mode = GET_MODE (x);
6273 inner = force_to_mode (inner, op_mode, mask, reg, next_select);
6275 if (GET_MODE (x) != op_mode || inner != XEXP (x, 0))
6276 x = gen_binary (LSHIFTRT, op_mode, inner, XEXP (x, 1));
6279 /* If we have (and (lshiftrt FOO C1) C2) where the combination of the
6280 shift and AND produces only copies of the sign bit (C2 is one less
6281 than a power of two), we can do this with just a shift. */
6283 if (GET_CODE (x) == LSHIFTRT
6284 && GET_CODE (XEXP (x, 1)) == CONST_INT
6285 && ((INTVAL (XEXP (x, 1))
6286 + num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0))))
6287 >= GET_MODE_BITSIZE (GET_MODE (x)))
6288 && exact_log2 (mask + 1) >= 0
6289 && (num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
6290 >= exact_log2 (mask + 1)))
6291 x = gen_binary (LSHIFTRT, GET_MODE (x), XEXP (x, 0),
6292 GEN_INT (GET_MODE_BITSIZE (GET_MODE (x))
6293 - exact_log2 (mask + 1)));
6297 /* If we are just looking for the sign bit, we don't need this shift at
6298 all, even if it has a variable count. */
6299 if (GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
6300 && (mask == ((HOST_WIDE_INT) 1
6301 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
6302 return force_to_mode (XEXP (x, 0), mode, mask, reg, next_select);
6304 /* If this is a shift by a constant, get a mask that contains those bits
6305 that are not copies of the sign bit. We then have two cases: If
6306 MASK only includes those bits, this can be a logical shift, which may
6307 allow simplifications. If MASK is a single-bit field not within
6308 those bits, we are requesting a copy of the sign bit and hence can
6309 shift the sign bit to the appropriate location. */
6311 if (GET_CODE (XEXP (x, 1)) == CONST_INT && INTVAL (XEXP (x, 1)) >= 0
6312 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT)
6316 /* If the considered data is wider then HOST_WIDE_INT, we can't
6317 represent a mask for all its bits in a single scalar.
6318 But we only care about the lower bits, so calculate these. */
6320 if (GET_MODE_BITSIZE (GET_MODE (x)) > HOST_BITS_PER_WIDE_INT)
6322 nonzero = ~ (HOST_WIDE_INT) 0;
6324 /* GET_MODE_BITSIZE (GET_MODE (x)) - INTVAL (XEXP (x, 1))
6325 is the number of bits a full-width mask would have set.
6326 We need only shift if these are fewer than nonzero can
6327 hold. If not, we must keep all bits set in nonzero. */
6329 if (GET_MODE_BITSIZE (GET_MODE (x)) - INTVAL (XEXP (x, 1))
6330 < HOST_BITS_PER_WIDE_INT)
6331 nonzero >>= INTVAL (XEXP (x, 1))
6332 + HOST_BITS_PER_WIDE_INT
6333 - GET_MODE_BITSIZE (GET_MODE (x)) ;
6337 nonzero = GET_MODE_MASK (GET_MODE (x));
6338 nonzero >>= INTVAL (XEXP (x, 1));
6341 if ((mask & ~ nonzero) == 0
6342 || (i = exact_log2 (mask)) >= 0)
6344 x = simplify_shift_const
6345 (x, LSHIFTRT, GET_MODE (x), XEXP (x, 0),
6346 i < 0 ? INTVAL (XEXP (x, 1))
6347 : GET_MODE_BITSIZE (GET_MODE (x)) - 1 - i);
6349 if (GET_CODE (x) != ASHIFTRT)
6350 return force_to_mode (x, mode, mask, reg, next_select);
6354 /* If MASK is 1, convert this to a LSHIFTRT. This can be done
6355 even if the shift count isn't a constant. */
6357 x = gen_binary (LSHIFTRT, GET_MODE (x), XEXP (x, 0), XEXP (x, 1));
6359 /* If this is a sign-extension operation that just affects bits
6360 we don't care about, remove it. Be sure the call above returned
6361 something that is still a shift. */
6363 if ((GET_CODE (x) == LSHIFTRT || GET_CODE (x) == ASHIFTRT)
6364 && GET_CODE (XEXP (x, 1)) == CONST_INT
6365 && INTVAL (XEXP (x, 1)) >= 0
6366 && (INTVAL (XEXP (x, 1))
6367 <= GET_MODE_BITSIZE (GET_MODE (x)) - (floor_log2 (mask) + 1))
6368 && GET_CODE (XEXP (x, 0)) == ASHIFT
6369 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
6370 && INTVAL (XEXP (XEXP (x, 0), 1)) == INTVAL (XEXP (x, 1)))
6371 return force_to_mode (XEXP (XEXP (x, 0), 0), mode, mask,
6378 /* If the shift count is constant and we can do computations
6379 in the mode of X, compute where the bits we care about are.
6380 Otherwise, we can't do anything. Don't change the mode of
6381 the shift or propagate MODE into the shift, though. */
6382 if (GET_CODE (XEXP (x, 1)) == CONST_INT
6383 && INTVAL (XEXP (x, 1)) >= 0)
6385 temp = simplify_binary_operation (code == ROTATE ? ROTATERT : ROTATE,
6386 GET_MODE (x), GEN_INT (mask),
6388 if (temp && GET_CODE(temp) == CONST_INT)
6390 force_to_mode (XEXP (x, 0), GET_MODE (x),
6391 INTVAL (temp), reg, next_select));
6396 /* If we just want the low-order bit, the NEG isn't needed since it
6397 won't change the low-order bit. */
6399 return force_to_mode (XEXP (x, 0), mode, mask, reg, just_select);
6401 /* We need any bits less significant than the most significant bit in
6402 MASK since carries from those bits will affect the bits we are
6408 /* (not FOO) is (xor FOO CONST), so if FOO is an LSHIFTRT, we can do the
6409 same as the XOR case above. Ensure that the constant we form is not
6410 wider than the mode of X. */
6412 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
6413 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
6414 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
6415 && (INTVAL (XEXP (XEXP (x, 0), 1)) + floor_log2 (mask)
6416 < GET_MODE_BITSIZE (GET_MODE (x)))
6417 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT)
6419 temp = GEN_INT (mask << INTVAL (XEXP (XEXP (x, 0), 1)));
6420 temp = gen_binary (XOR, GET_MODE (x), XEXP (XEXP (x, 0), 0), temp);
6421 x = gen_binary (LSHIFTRT, GET_MODE (x), temp, XEXP (XEXP (x, 0), 1));
6423 return force_to_mode (x, mode, mask, reg, next_select);
6426 /* (and (not FOO) CONST) is (not (or FOO (not CONST))), so we must
6427 use the full mask inside the NOT. */
6431 op0 = gen_lowpart_for_combine (op_mode,
6432 force_to_mode (XEXP (x, 0), mode, mask,
6434 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0))
6435 x = gen_unary (code, op_mode, op_mode, op0);
6439 /* (and (ne FOO 0) CONST) can be (and FOO CONST) if CONST is included
6440 in STORE_FLAG_VALUE and FOO has a single bit that might be nonzero,
6441 which is equal to STORE_FLAG_VALUE. */
6442 if ((mask & ~ STORE_FLAG_VALUE) == 0 && XEXP (x, 1) == const0_rtx
6443 && exact_log2 (nonzero_bits (XEXP (x, 0), mode)) >= 0
6444 && nonzero_bits (XEXP (x, 0), mode) == STORE_FLAG_VALUE)
6445 return force_to_mode (XEXP (x, 0), mode, mask, reg, next_select);
6450 /* We have no way of knowing if the IF_THEN_ELSE can itself be
6451 written in a narrower mode. We play it safe and do not do so. */
6454 gen_lowpart_for_combine (GET_MODE (x),
6455 force_to_mode (XEXP (x, 1), mode,
6456 mask, reg, next_select)));
6458 gen_lowpart_for_combine (GET_MODE (x),
6459 force_to_mode (XEXP (x, 2), mode,
6460 mask, reg,next_select)));
6464 /* Ensure we return a value of the proper mode. */
6465 return gen_lowpart_for_combine (mode, x);
6468 /* Return nonzero if X is an expression that has one of two values depending on
6469 whether some other value is zero or nonzero. In that case, we return the
6470 value that is being tested, *PTRUE is set to the value if the rtx being
6471 returned has a nonzero value, and *PFALSE is set to the other alternative.
6473 If we return zero, we set *PTRUE and *PFALSE to X. */
6476 if_then_else_cond (x, ptrue, pfalse)
6478 rtx *ptrue, *pfalse;
6480 enum machine_mode mode = GET_MODE (x);
6481 enum rtx_code code = GET_CODE (x);
6482 int size = GET_MODE_BITSIZE (mode);
6483 rtx cond0, cond1, true0, true1, false0, false1;
6484 unsigned HOST_WIDE_INT nz;
6486 /* If this is a unary operation whose operand has one of two values, apply
6487 our opcode to compute those values. */
6488 if (GET_RTX_CLASS (code) == '1'
6489 && (cond0 = if_then_else_cond (XEXP (x, 0), &true0, &false0)) != 0)
6491 *ptrue = gen_unary (code, mode, GET_MODE (XEXP (x, 0)), true0);
6492 *pfalse = gen_unary (code, mode, GET_MODE (XEXP (x, 0)), false0);
6496 /* If this is a COMPARE, do nothing, since the IF_THEN_ELSE we would
6497 make can't possibly match and would suppress other optimizations. */
6498 else if (code == COMPARE)
6501 /* If this is a binary operation, see if either side has only one of two
6502 values. If either one does or if both do and they are conditional on
6503 the same value, compute the new true and false values. */
6504 else if (GET_RTX_CLASS (code) == 'c' || GET_RTX_CLASS (code) == '2'
6505 || GET_RTX_CLASS (code) == '<')
6507 cond0 = if_then_else_cond (XEXP (x, 0), &true0, &false0);
6508 cond1 = if_then_else_cond (XEXP (x, 1), &true1, &false1);
6510 if ((cond0 != 0 || cond1 != 0)
6511 && ! (cond0 != 0 && cond1 != 0 && ! rtx_equal_p (cond0, cond1)))
6513 /* If if_then_else_cond returned zero, then true/false are the
6514 same rtl. We must copy one of them to prevent invalid rtl
6517 true0 = copy_rtx (true0);
6518 else if (cond1 == 0)
6519 true1 = copy_rtx (true1);
6521 *ptrue = gen_binary (code, mode, true0, true1);
6522 *pfalse = gen_binary (code, mode, false0, false1);
6523 return cond0 ? cond0 : cond1;
6526 /* See if we have PLUS, IOR, XOR, MINUS or UMAX, where one of the
6527 operands is zero when the other is non-zero, and vice-versa,
6528 and STORE_FLAG_VALUE is 1 or -1. */
6530 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
6531 && (code == PLUS || code == IOR || code == XOR || code == MINUS
6533 && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT)
6535 rtx op0 = XEXP (XEXP (x, 0), 1);
6536 rtx op1 = XEXP (XEXP (x, 1), 1);
6538 cond0 = XEXP (XEXP (x, 0), 0);
6539 cond1 = XEXP (XEXP (x, 1), 0);
6541 if (GET_RTX_CLASS (GET_CODE (cond0)) == '<'
6542 && GET_RTX_CLASS (GET_CODE (cond1)) == '<'
6543 && reversible_comparison_p (cond1)
6544 && ((GET_CODE (cond0) == reverse_condition (GET_CODE (cond1))
6545 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0))
6546 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1)))
6547 || ((swap_condition (GET_CODE (cond0))
6548 == reverse_condition (GET_CODE (cond1)))
6549 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1))
6550 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0))))
6551 && ! side_effects_p (x))
6553 *ptrue = gen_binary (MULT, mode, op0, const_true_rtx);
6554 *pfalse = gen_binary (MULT, mode,
6556 ? gen_unary (NEG, mode, mode, op1) : op1),
6562 /* Similarly for MULT, AND and UMIN, execpt that for these the result
6564 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
6565 && (code == MULT || code == AND || code == UMIN)
6566 && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT)
6568 cond0 = XEXP (XEXP (x, 0), 0);
6569 cond1 = XEXP (XEXP (x, 1), 0);
6571 if (GET_RTX_CLASS (GET_CODE (cond0)) == '<'
6572 && GET_RTX_CLASS (GET_CODE (cond1)) == '<'
6573 && reversible_comparison_p (cond1)
6574 && ((GET_CODE (cond0) == reverse_condition (GET_CODE (cond1))
6575 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0))
6576 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1)))
6577 || ((swap_condition (GET_CODE (cond0))
6578 == reverse_condition (GET_CODE (cond1)))
6579 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1))
6580 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0))))
6581 && ! side_effects_p (x))
6583 *ptrue = *pfalse = const0_rtx;
6589 else if (code == IF_THEN_ELSE)
6591 /* If we have IF_THEN_ELSE already, extract the condition and
6592 canonicalize it if it is NE or EQ. */
6593 cond0 = XEXP (x, 0);
6594 *ptrue = XEXP (x, 1), *pfalse = XEXP (x, 2);
6595 if (GET_CODE (cond0) == NE && XEXP (cond0, 1) == const0_rtx)
6596 return XEXP (cond0, 0);
6597 else if (GET_CODE (cond0) == EQ && XEXP (cond0, 1) == const0_rtx)
6599 *ptrue = XEXP (x, 2), *pfalse = XEXP (x, 1);
6600 return XEXP (cond0, 0);
6606 /* If X is a normal SUBREG with both inner and outer modes integral,
6607 we can narrow both the true and false values of the inner expression,
6608 if there is a condition. */
6609 else if (code == SUBREG && GET_MODE_CLASS (mode) == MODE_INT
6610 && GET_MODE_CLASS (GET_MODE (SUBREG_REG (x))) == MODE_INT
6611 && GET_MODE_SIZE (mode) <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x)))
6612 && 0 != (cond0 = if_then_else_cond (SUBREG_REG (x),
6615 *ptrue = force_to_mode (true0, mode, GET_MODE_MASK (mode), NULL_RTX, 0);
6617 = force_to_mode (false0, mode, GET_MODE_MASK (mode), NULL_RTX, 0);
6622 /* If X is a constant, this isn't special and will cause confusions
6623 if we treat it as such. Likewise if it is equivalent to a constant. */
6624 else if (CONSTANT_P (x)
6625 || ((cond0 = get_last_value (x)) != 0 && CONSTANT_P (cond0)))
6628 /* If X is known to be either 0 or -1, those are the true and
6629 false values when testing X. */
6630 else if (num_sign_bit_copies (x, mode) == size)
6632 *ptrue = constm1_rtx, *pfalse = const0_rtx;
6636 /* Likewise for 0 or a single bit. */
6637 else if (exact_log2 (nz = nonzero_bits (x, mode)) >= 0)
6639 *ptrue = GEN_INT (nz), *pfalse = const0_rtx;
6643 /* Otherwise fail; show no condition with true and false values the same. */
6644 *ptrue = *pfalse = x;
6648 /* Return the value of expression X given the fact that condition COND
6649 is known to be true when applied to REG as its first operand and VAL
6650 as its second. X is known to not be shared and so can be modified in
6653 We only handle the simplest cases, and specifically those cases that
6654 arise with IF_THEN_ELSE expressions. */
6657 known_cond (x, cond, reg, val)
6662 enum rtx_code code = GET_CODE (x);
6667 if (side_effects_p (x))
6670 if (cond == EQ && rtx_equal_p (x, reg))
6673 /* If X is (abs REG) and we know something about REG's relationship
6674 with zero, we may be able to simplify this. */
6676 if (code == ABS && rtx_equal_p (XEXP (x, 0), reg) && val == const0_rtx)
6679 case GE: case GT: case EQ:
6682 return gen_unary (NEG, GET_MODE (XEXP (x, 0)), GET_MODE (XEXP (x, 0)),
6686 /* The only other cases we handle are MIN, MAX, and comparisons if the
6687 operands are the same as REG and VAL. */
6689 else if (GET_RTX_CLASS (code) == '<' || GET_RTX_CLASS (code) == 'c')
6691 if (rtx_equal_p (XEXP (x, 0), val))
6692 cond = swap_condition (cond), temp = val, val = reg, reg = temp;
6694 if (rtx_equal_p (XEXP (x, 0), reg) && rtx_equal_p (XEXP (x, 1), val))
6696 if (GET_RTX_CLASS (code) == '<')
6697 return (comparison_dominates_p (cond, code) ? const_true_rtx
6698 : (comparison_dominates_p (cond,
6699 reverse_condition (code))
6702 else if (code == SMAX || code == SMIN
6703 || code == UMIN || code == UMAX)
6705 int unsignedp = (code == UMIN || code == UMAX);
6707 if (code == SMAX || code == UMAX)
6708 cond = reverse_condition (cond);
6713 return unsignedp ? x : XEXP (x, 1);
6715 return unsignedp ? x : XEXP (x, 0);
6717 return unsignedp ? XEXP (x, 1) : x;
6719 return unsignedp ? XEXP (x, 0) : x;
6725 fmt = GET_RTX_FORMAT (code);
6726 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
6729 SUBST (XEXP (x, i), known_cond (XEXP (x, i), cond, reg, val));
6730 else if (fmt[i] == 'E')
6731 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
6732 SUBST (XVECEXP (x, i, j), known_cond (XVECEXP (x, i, j),
6739 /* See if X and Y are equal for the purposes of seeing if we can rewrite an
6740 assignment as a field assignment. */
6743 rtx_equal_for_field_assignment_p (x, y)
6749 if (x == y || rtx_equal_p (x, y))
6752 if (x == 0 || y == 0 || GET_MODE (x) != GET_MODE (y))
6755 /* Check for a paradoxical SUBREG of a MEM compared with the MEM.
6756 Note that all SUBREGs of MEM are paradoxical; otherwise they
6757 would have been rewritten. */
6758 if (GET_CODE (x) == MEM && GET_CODE (y) == SUBREG
6759 && GET_CODE (SUBREG_REG (y)) == MEM
6760 && rtx_equal_p (SUBREG_REG (y),
6761 gen_lowpart_for_combine (GET_MODE (SUBREG_REG (y)), x)))
6764 if (GET_CODE (y) == MEM && GET_CODE (x) == SUBREG
6765 && GET_CODE (SUBREG_REG (x)) == MEM
6766 && rtx_equal_p (SUBREG_REG (x),
6767 gen_lowpart_for_combine (GET_MODE (SUBREG_REG (x)), y)))
6770 last_x = get_last_value (x);
6771 last_y = get_last_value (y);
6773 return ((last_x != 0
6774 && GET_CODE (last_x) != CLOBBER
6775 && rtx_equal_for_field_assignment_p (last_x, y))
6777 && GET_CODE (last_y) != CLOBBER
6778 && rtx_equal_for_field_assignment_p (x, last_y))
6779 || (last_x != 0 && last_y != 0
6780 && GET_CODE (last_x) != CLOBBER
6781 && GET_CODE (last_y) != CLOBBER
6782 && rtx_equal_for_field_assignment_p (last_x, last_y)));
6785 /* See if X, a SET operation, can be rewritten as a bit-field assignment.
6786 Return that assignment if so.
6788 We only handle the most common cases. */
6791 make_field_assignment (x)
6794 rtx dest = SET_DEST (x);
6795 rtx src = SET_SRC (x);
6801 enum machine_mode mode;
6803 /* If SRC was (and (not (ashift (const_int 1) POS)) DEST), this is
6804 a clear of a one-bit field. We will have changed it to
6805 (and (rotate (const_int -2) POS) DEST), so check for that. Also check
6808 if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == ROTATE
6809 && GET_CODE (XEXP (XEXP (src, 0), 0)) == CONST_INT
6810 && INTVAL (XEXP (XEXP (src, 0), 0)) == -2
6811 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
6813 assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1),
6816 return gen_rtx (SET, VOIDmode, assign, const0_rtx);
6820 else if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == SUBREG
6821 && subreg_lowpart_p (XEXP (src, 0))
6822 && (GET_MODE_SIZE (GET_MODE (XEXP (src, 0)))
6823 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (src, 0)))))
6824 && GET_CODE (SUBREG_REG (XEXP (src, 0))) == ROTATE
6825 && INTVAL (XEXP (SUBREG_REG (XEXP (src, 0)), 0)) == -2
6826 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
6828 assign = make_extraction (VOIDmode, dest, 0,
6829 XEXP (SUBREG_REG (XEXP (src, 0)), 1),
6832 return gen_rtx (SET, VOIDmode, assign, const0_rtx);
6836 /* If SRC is (ior (ashift (const_int 1) POS) DEST), this is a set of a
6838 else if (GET_CODE (src) == IOR && GET_CODE (XEXP (src, 0)) == ASHIFT
6839 && XEXP (XEXP (src, 0), 0) == const1_rtx
6840 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
6842 assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1),
6845 return gen_rtx (SET, VOIDmode, assign, const1_rtx);
6849 /* The other case we handle is assignments into a constant-position
6850 field. They look like (ior/xor (and DEST C1) OTHER). If C1 represents
6851 a mask that has all one bits except for a group of zero bits and
6852 OTHER is known to have zeros where C1 has ones, this is such an
6853 assignment. Compute the position and length from C1. Shift OTHER
6854 to the appropriate position, force it to the required mode, and
6855 make the extraction. Check for the AND in both operands. */
6857 if (GET_CODE (src) != IOR && GET_CODE (src) != XOR)
6860 rhs = expand_compound_operation (XEXP (src, 0));
6861 lhs = expand_compound_operation (XEXP (src, 1));
6863 if (GET_CODE (rhs) == AND
6864 && GET_CODE (XEXP (rhs, 1)) == CONST_INT
6865 && rtx_equal_for_field_assignment_p (XEXP (rhs, 0), dest))
6866 c1 = INTVAL (XEXP (rhs, 1)), other = lhs;
6867 else if (GET_CODE (lhs) == AND
6868 && GET_CODE (XEXP (lhs, 1)) == CONST_INT
6869 && rtx_equal_for_field_assignment_p (XEXP (lhs, 0), dest))
6870 c1 = INTVAL (XEXP (lhs, 1)), other = rhs;
6874 pos = get_pos_from_mask ((~ c1) & GET_MODE_MASK (GET_MODE (dest)), &len);
6875 if (pos < 0 || pos + len > GET_MODE_BITSIZE (GET_MODE (dest))
6876 || (GET_MODE_BITSIZE (GET_MODE (other)) <= HOST_BITS_PER_WIDE_INT
6877 && (c1 & nonzero_bits (other, GET_MODE (other))) != 0))
6880 assign = make_extraction (VOIDmode, dest, pos, NULL_RTX, len, 1, 1, 0);
6884 /* The mode to use for the source is the mode of the assignment, or of
6885 what is inside a possible STRICT_LOW_PART. */
6886 mode = (GET_CODE (assign) == STRICT_LOW_PART
6887 ? GET_MODE (XEXP (assign, 0)) : GET_MODE (assign));
6889 /* Shift OTHER right POS places and make it the source, restricting it
6890 to the proper length and mode. */
6892 src = force_to_mode (simplify_shift_const (NULL_RTX, LSHIFTRT,
6893 GET_MODE (src), other, pos),
6895 GET_MODE_BITSIZE (mode) >= HOST_BITS_PER_WIDE_INT
6896 ? GET_MODE_MASK (mode)
6897 : ((HOST_WIDE_INT) 1 << len) - 1,
6900 return gen_rtx_combine (SET, VOIDmode, assign, src);
6903 /* See if X is of the form (+ (* a c) (* b c)) and convert to (* (+ a b) c)
6907 apply_distributive_law (x)
6910 enum rtx_code code = GET_CODE (x);
6911 rtx lhs, rhs, other;
6913 enum rtx_code inner_code;
6915 /* Distributivity is not true for floating point.
6916 It can change the value. So don't do it.
6917 -- rms and moshier@world.std.com. */
6918 if (FLOAT_MODE_P (GET_MODE (x)))
6921 /* The outer operation can only be one of the following: */
6922 if (code != IOR && code != AND && code != XOR
6923 && code != PLUS && code != MINUS)
6926 lhs = XEXP (x, 0), rhs = XEXP (x, 1);
6928 /* If either operand is a primitive we can't do anything, so get out
6930 if (GET_RTX_CLASS (GET_CODE (lhs)) == 'o'
6931 || GET_RTX_CLASS (GET_CODE (rhs)) == 'o')
6934 lhs = expand_compound_operation (lhs);
6935 rhs = expand_compound_operation (rhs);
6936 inner_code = GET_CODE (lhs);
6937 if (inner_code != GET_CODE (rhs))
6940 /* See if the inner and outer operations distribute. */
6947 /* These all distribute except over PLUS. */
6948 if (code == PLUS || code == MINUS)
6953 if (code != PLUS && code != MINUS)
6958 /* This is also a multiply, so it distributes over everything. */
6962 /* Non-paradoxical SUBREGs distributes over all operations, provided
6963 the inner modes and word numbers are the same, this is an extraction
6964 of a low-order part, we don't convert an fp operation to int or
6965 vice versa, and we would not be converting a single-word
6966 operation into a multi-word operation. The latter test is not
6967 required, but it prevents generating unneeded multi-word operations.
6968 Some of the previous tests are redundant given the latter test, but
6969 are retained because they are required for correctness.
6971 We produce the result slightly differently in this case. */
6973 if (GET_MODE (SUBREG_REG (lhs)) != GET_MODE (SUBREG_REG (rhs))
6974 || SUBREG_WORD (lhs) != SUBREG_WORD (rhs)
6975 || ! subreg_lowpart_p (lhs)
6976 || (GET_MODE_CLASS (GET_MODE (lhs))
6977 != GET_MODE_CLASS (GET_MODE (SUBREG_REG (lhs))))
6978 || (GET_MODE_SIZE (GET_MODE (lhs))
6979 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs))))
6980 || GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs))) > UNITS_PER_WORD)
6983 tem = gen_binary (code, GET_MODE (SUBREG_REG (lhs)),
6984 SUBREG_REG (lhs), SUBREG_REG (rhs));
6985 return gen_lowpart_for_combine (GET_MODE (x), tem);
6991 /* Set LHS and RHS to the inner operands (A and B in the example
6992 above) and set OTHER to the common operand (C in the example).
6993 These is only one way to do this unless the inner operation is
6995 if (GET_RTX_CLASS (inner_code) == 'c'
6996 && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 0)))
6997 other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 1);
6998 else if (GET_RTX_CLASS (inner_code) == 'c'
6999 && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 1)))
7000 other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 0);
7001 else if (GET_RTX_CLASS (inner_code) == 'c'
7002 && rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 0)))
7003 other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 1);
7004 else if (rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 1)))
7005 other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 0);
7009 /* Form the new inner operation, seeing if it simplifies first. */
7010 tem = gen_binary (code, GET_MODE (x), lhs, rhs);
7012 /* There is one exception to the general way of distributing:
7013 (a ^ b) | (a ^ c) -> (~a) & (b ^ c) */
7014 if (code == XOR && inner_code == IOR)
7017 other = gen_unary (NOT, GET_MODE (x), GET_MODE (x), other);
7020 /* We may be able to continuing distributing the result, so call
7021 ourselves recursively on the inner operation before forming the
7022 outer operation, which we return. */
7023 return gen_binary (inner_code, GET_MODE (x),
7024 apply_distributive_law (tem), other);
7027 /* We have X, a logical `and' of VAROP with the constant CONSTOP, to be done
7030 Return an equivalent form, if different from X. Otherwise, return X. If
7031 X is zero, we are to always construct the equivalent form. */
7034 simplify_and_const_int (x, mode, varop, constop)
7036 enum machine_mode mode;
7038 unsigned HOST_WIDE_INT constop;
7040 unsigned HOST_WIDE_INT nonzero;
7041 int width = GET_MODE_BITSIZE (mode);
7044 /* Simplify VAROP knowing that we will be only looking at some of the
7046 varop = force_to_mode (varop, mode, constop, NULL_RTX, 0);
7048 /* If VAROP is a CLOBBER, we will fail so return it; if it is a
7049 CONST_INT, we are done. */
7050 if (GET_CODE (varop) == CLOBBER || GET_CODE (varop) == CONST_INT)
7053 /* See what bits may be nonzero in VAROP. Unlike the general case of
7054 a call to nonzero_bits, here we don't care about bits outside
7057 nonzero = nonzero_bits (varop, mode) & GET_MODE_MASK (mode);
7059 /* If this would be an entire word for the target, but is not for
7060 the host, then sign-extend on the host so that the number will look
7061 the same way on the host that it would on the target.
7063 For example, when building a 64 bit alpha hosted 32 bit sparc
7064 targeted compiler, then we want the 32 bit unsigned value -1 to be
7065 represented as a 64 bit value -1, and not as 0x00000000ffffffff.
7066 The later confuses the sparc backend. */
7068 if (BITS_PER_WORD < HOST_BITS_PER_WIDE_INT && BITS_PER_WORD == width
7069 && (nonzero & ((HOST_WIDE_INT) 1 << (width - 1))))
7070 nonzero |= ((HOST_WIDE_INT) (-1) << width);
7072 /* Turn off all bits in the constant that are known to already be zero.
7073 Thus, if the AND isn't needed at all, we will have CONSTOP == NONZERO_BITS
7074 which is tested below. */
7078 /* If we don't have any bits left, return zero. */
7082 /* If VAROP is a NEG of something known to be zero or 1 and CONSTOP is
7083 a power of two, we can replace this with a ASHIFT. */
7084 if (GET_CODE (varop) == NEG && nonzero_bits (XEXP (varop, 0), mode) == 1
7085 && (i = exact_log2 (constop)) >= 0)
7086 return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (varop, 0), i);
7088 /* If VAROP is an IOR or XOR, apply the AND to both branches of the IOR
7089 or XOR, then try to apply the distributive law. This may eliminate
7090 operations if either branch can be simplified because of the AND.
7091 It may also make some cases more complex, but those cases probably
7092 won't match a pattern either with or without this. */
7094 if (GET_CODE (varop) == IOR || GET_CODE (varop) == XOR)
7096 gen_lowpart_for_combine
7098 apply_distributive_law
7099 (gen_binary (GET_CODE (varop), GET_MODE (varop),
7100 simplify_and_const_int (NULL_RTX, GET_MODE (varop),
7101 XEXP (varop, 0), constop),
7102 simplify_and_const_int (NULL_RTX, GET_MODE (varop),
7103 XEXP (varop, 1), constop))));
7105 /* Get VAROP in MODE. Try to get a SUBREG if not. Don't make a new SUBREG
7106 if we already had one (just check for the simplest cases). */
7107 if (x && GET_CODE (XEXP (x, 0)) == SUBREG
7108 && GET_MODE (XEXP (x, 0)) == mode
7109 && SUBREG_REG (XEXP (x, 0)) == varop)
7110 varop = XEXP (x, 0);
7112 varop = gen_lowpart_for_combine (mode, varop);
7114 /* If we can't make the SUBREG, try to return what we were given. */
7115 if (GET_CODE (varop) == CLOBBER)
7116 return x ? x : varop;
7118 /* If we are only masking insignificant bits, return VAROP. */
7119 if (constop == nonzero)
7122 /* Otherwise, return an AND. See how much, if any, of X we can use. */
7123 else if (x == 0 || GET_CODE (x) != AND || GET_MODE (x) != mode)
7124 x = gen_binary (AND, mode, varop, GEN_INT (constop));
7128 if (GET_CODE (XEXP (x, 1)) != CONST_INT
7129 || INTVAL (XEXP (x, 1)) != constop)
7130 SUBST (XEXP (x, 1), GEN_INT (constop));
7132 SUBST (XEXP (x, 0), varop);
7138 /* We let num_sign_bit_copies recur into nonzero_bits as that is useful.
7139 We don't let nonzero_bits recur into num_sign_bit_copies, because that
7140 is less useful. We can't allow both, because that results in exponential
7141 run time recusion. There is a nullstone testcase that triggered
7142 this. This macro avoids accidental uses of num_sign_bit_copies. */
7143 #define num_sign_bit_copies()
7145 /* Given an expression, X, compute which bits in X can be non-zero.
7146 We don't care about bits outside of those defined in MODE.
7148 For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is
7149 a shift, AND, or zero_extract, we can do better. */
7151 static unsigned HOST_WIDE_INT
7152 nonzero_bits (x, mode)
7154 enum machine_mode mode;
7156 unsigned HOST_WIDE_INT nonzero = GET_MODE_MASK (mode);
7157 unsigned HOST_WIDE_INT inner_nz;
7159 int mode_width = GET_MODE_BITSIZE (mode);
7162 /* For floating-point values, assume all bits are needed. */
7163 if (FLOAT_MODE_P (GET_MODE (x)) || FLOAT_MODE_P (mode))
7166 /* If X is wider than MODE, use its mode instead. */
7167 if (GET_MODE_BITSIZE (GET_MODE (x)) > mode_width)
7169 mode = GET_MODE (x);
7170 nonzero = GET_MODE_MASK (mode);
7171 mode_width = GET_MODE_BITSIZE (mode);
7174 if (mode_width > HOST_BITS_PER_WIDE_INT)
7175 /* Our only callers in this case look for single bit values. So
7176 just return the mode mask. Those tests will then be false. */
7179 #ifndef WORD_REGISTER_OPERATIONS
7180 /* If MODE is wider than X, but both are a single word for both the host
7181 and target machines, we can compute this from which bits of the
7182 object might be nonzero in its own mode, taking into account the fact
7183 that on many CISC machines, accessing an object in a wider mode
7184 causes the high-order bits to become undefined. So they are
7185 not known to be zero. */
7187 if (GET_MODE (x) != VOIDmode && GET_MODE (x) != mode
7188 && GET_MODE_BITSIZE (GET_MODE (x)) <= BITS_PER_WORD
7189 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
7190 && GET_MODE_BITSIZE (mode) > GET_MODE_BITSIZE (GET_MODE (x)))
7192 nonzero &= nonzero_bits (x, GET_MODE (x));
7193 nonzero |= GET_MODE_MASK (mode) & ~ GET_MODE_MASK (GET_MODE (x));
7198 code = GET_CODE (x);
7202 #ifdef POINTERS_EXTEND_UNSIGNED
7203 /* If pointers extend unsigned and this is a pointer in Pmode, say that
7204 all the bits above ptr_mode are known to be zero. */
7205 if (POINTERS_EXTEND_UNSIGNED && GET_MODE (x) == Pmode
7206 && REGNO_POINTER_FLAG (REGNO (x)))
7207 nonzero &= GET_MODE_MASK (ptr_mode);
7210 #ifdef STACK_BOUNDARY
7211 /* If this is the stack pointer, we may know something about its
7212 alignment. If PUSH_ROUNDING is defined, it is possible for the
7213 stack to be momentarily aligned only to that amount, so we pick
7214 the least alignment. */
7216 /* We can't check for arg_pointer_rtx here, because it is not
7217 guaranteed to have as much alignment as the stack pointer.
7218 In particular, in the Irix6 n64 ABI, the stack has 128 bit
7219 alignment but the argument pointer has only 64 bit alignment. */
7221 if (x == stack_pointer_rtx || x == frame_pointer_rtx
7222 || x == hard_frame_pointer_rtx
7223 || (REGNO (x) >= FIRST_VIRTUAL_REGISTER
7224 && REGNO (x) <= LAST_VIRTUAL_REGISTER))
7226 int sp_alignment = STACK_BOUNDARY / BITS_PER_UNIT;
7228 #ifdef PUSH_ROUNDING
7229 if (REGNO (x) == STACK_POINTER_REGNUM)
7230 sp_alignment = MIN (PUSH_ROUNDING (1), sp_alignment);
7233 /* We must return here, otherwise we may get a worse result from
7234 one of the choices below. There is nothing useful below as
7235 far as the stack pointer is concerned. */
7236 return nonzero &= ~ (sp_alignment - 1);
7240 /* If X is a register whose nonzero bits value is current, use it.
7241 Otherwise, if X is a register whose value we can find, use that
7242 value. Otherwise, use the previously-computed global nonzero bits
7243 for this register. */
7245 if (reg_last_set_value[REGNO (x)] != 0
7246 && reg_last_set_mode[REGNO (x)] == mode
7247 && (REG_N_SETS (REGNO (x)) == 1
7248 || reg_last_set_label[REGNO (x)] == label_tick)
7249 && INSN_CUID (reg_last_set[REGNO (x)]) < subst_low_cuid)
7250 return reg_last_set_nonzero_bits[REGNO (x)];
7252 tem = get_last_value (x);
7256 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
7257 /* If X is narrower than MODE and TEM is a non-negative
7258 constant that would appear negative in the mode of X,
7259 sign-extend it for use in reg_nonzero_bits because some
7260 machines (maybe most) will actually do the sign-extension
7261 and this is the conservative approach.
7263 ??? For 2.5, try to tighten up the MD files in this regard
7264 instead of this kludge. */
7266 if (GET_MODE_BITSIZE (GET_MODE (x)) < mode_width
7267 && GET_CODE (tem) == CONST_INT
7269 && 0 != (INTVAL (tem)
7270 & ((HOST_WIDE_INT) 1
7271 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
7272 tem = GEN_INT (INTVAL (tem)
7273 | ((HOST_WIDE_INT) (-1)
7274 << GET_MODE_BITSIZE (GET_MODE (x))));
7276 return nonzero_bits (tem, mode);
7278 else if (nonzero_sign_valid && reg_nonzero_bits[REGNO (x)])
7279 return reg_nonzero_bits[REGNO (x)] & nonzero;
7284 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
7285 /* If X is negative in MODE, sign-extend the value. */
7286 if (INTVAL (x) > 0 && mode_width < BITS_PER_WORD
7287 && 0 != (INTVAL (x) & ((HOST_WIDE_INT) 1 << (mode_width - 1))))
7288 return (INTVAL (x) | ((HOST_WIDE_INT) (-1) << mode_width));
7294 #ifdef LOAD_EXTEND_OP
7295 /* In many, if not most, RISC machines, reading a byte from memory
7296 zeros the rest of the register. Noticing that fact saves a lot
7297 of extra zero-extends. */
7298 if (LOAD_EXTEND_OP (GET_MODE (x)) == ZERO_EXTEND)
7299 nonzero &= GET_MODE_MASK (GET_MODE (x));
7309 /* If this produces an integer result, we know which bits are set.
7310 Code here used to clear bits outside the mode of X, but that is
7313 if (GET_MODE_CLASS (mode) == MODE_INT
7314 && mode_width <= HOST_BITS_PER_WIDE_INT)
7315 nonzero = STORE_FLAG_VALUE;
7320 /* Disabled to avoid exponential mutual recursion between nonzero_bits
7321 and num_sign_bit_copies. */
7322 if (num_sign_bit_copies (XEXP (x, 0), GET_MODE (x))
7323 == GET_MODE_BITSIZE (GET_MODE (x)))
7327 if (GET_MODE_SIZE (GET_MODE (x)) < mode_width)
7328 nonzero |= (GET_MODE_MASK (mode) & ~ GET_MODE_MASK (GET_MODE (x)));
7333 /* Disabled to avoid exponential mutual recursion between nonzero_bits
7334 and num_sign_bit_copies. */
7335 if (num_sign_bit_copies (XEXP (x, 0), GET_MODE (x))
7336 == GET_MODE_BITSIZE (GET_MODE (x)))
7342 nonzero &= (nonzero_bits (XEXP (x, 0), mode) & GET_MODE_MASK (mode));
7346 nonzero &= nonzero_bits (XEXP (x, 0), mode);
7347 if (GET_MODE (XEXP (x, 0)) != VOIDmode)
7348 nonzero &= GET_MODE_MASK (GET_MODE (XEXP (x, 0)));
7352 /* If the sign bit is known clear, this is the same as ZERO_EXTEND.
7353 Otherwise, show all the bits in the outer mode but not the inner
7355 inner_nz = nonzero_bits (XEXP (x, 0), mode);
7356 if (GET_MODE (XEXP (x, 0)) != VOIDmode)
7358 inner_nz &= GET_MODE_MASK (GET_MODE (XEXP (x, 0)));
7360 & (((HOST_WIDE_INT) 1
7361 << (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - 1))))
7362 inner_nz |= (GET_MODE_MASK (mode)
7363 & ~ GET_MODE_MASK (GET_MODE (XEXP (x, 0))));
7366 nonzero &= inner_nz;
7370 nonzero &= (nonzero_bits (XEXP (x, 0), mode)
7371 & nonzero_bits (XEXP (x, 1), mode));
7375 case UMIN: case UMAX: case SMIN: case SMAX:
7376 nonzero &= (nonzero_bits (XEXP (x, 0), mode)
7377 | nonzero_bits (XEXP (x, 1), mode));
7380 case PLUS: case MINUS:
7382 case DIV: case UDIV:
7383 case MOD: case UMOD:
7384 /* We can apply the rules of arithmetic to compute the number of
7385 high- and low-order zero bits of these operations. We start by
7386 computing the width (position of the highest-order non-zero bit)
7387 and the number of low-order zero bits for each value. */
7389 unsigned HOST_WIDE_INT nz0 = nonzero_bits (XEXP (x, 0), mode);
7390 unsigned HOST_WIDE_INT nz1 = nonzero_bits (XEXP (x, 1), mode);
7391 int width0 = floor_log2 (nz0) + 1;
7392 int width1 = floor_log2 (nz1) + 1;
7393 int low0 = floor_log2 (nz0 & -nz0);
7394 int low1 = floor_log2 (nz1 & -nz1);
7395 HOST_WIDE_INT op0_maybe_minusp
7396 = (nz0 & ((HOST_WIDE_INT) 1 << (mode_width - 1)));
7397 HOST_WIDE_INT op1_maybe_minusp
7398 = (nz1 & ((HOST_WIDE_INT) 1 << (mode_width - 1)));
7399 int result_width = mode_width;
7405 result_width = MAX (width0, width1) + 1;
7406 result_low = MIN (low0, low1);
7409 result_low = MIN (low0, low1);
7412 result_width = width0 + width1;
7413 result_low = low0 + low1;
7416 if (! op0_maybe_minusp && ! op1_maybe_minusp)
7417 result_width = width0;
7420 result_width = width0;
7423 if (! op0_maybe_minusp && ! op1_maybe_minusp)
7424 result_width = MIN (width0, width1);
7425 result_low = MIN (low0, low1);
7428 result_width = MIN (width0, width1);
7429 result_low = MIN (low0, low1);
7433 if (result_width < mode_width)
7434 nonzero &= ((HOST_WIDE_INT) 1 << result_width) - 1;
7437 nonzero &= ~ (((HOST_WIDE_INT) 1 << result_low) - 1);
7442 if (GET_CODE (XEXP (x, 1)) == CONST_INT
7443 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT)
7444 nonzero &= ((HOST_WIDE_INT) 1 << INTVAL (XEXP (x, 1))) - 1;
7448 /* If this is a SUBREG formed for a promoted variable that has
7449 been zero-extended, we know that at least the high-order bits
7450 are zero, though others might be too. */
7452 if (SUBREG_PROMOTED_VAR_P (x) && SUBREG_PROMOTED_UNSIGNED_P (x))
7453 nonzero = (GET_MODE_MASK (GET_MODE (x))
7454 & nonzero_bits (SUBREG_REG (x), GET_MODE (x)));
7456 /* If the inner mode is a single word for both the host and target
7457 machines, we can compute this from which bits of the inner
7458 object might be nonzero. */
7459 if (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x))) <= BITS_PER_WORD
7460 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x)))
7461 <= HOST_BITS_PER_WIDE_INT))
7463 nonzero &= nonzero_bits (SUBREG_REG (x), mode);
7465 #ifndef WORD_REGISTER_OPERATIONS
7466 /* On many CISC machines, accessing an object in a wider mode
7467 causes the high-order bits to become undefined. So they are
7468 not known to be zero. */
7469 if (GET_MODE_SIZE (GET_MODE (x))
7470 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
7471 nonzero |= (GET_MODE_MASK (GET_MODE (x))
7472 & ~ GET_MODE_MASK (GET_MODE (SUBREG_REG (x))));
7481 /* The nonzero bits are in two classes: any bits within MODE
7482 that aren't in GET_MODE (x) are always significant. The rest of the
7483 nonzero bits are those that are significant in the operand of
7484 the shift when shifted the appropriate number of bits. This
7485 shows that high-order bits are cleared by the right shift and
7486 low-order bits by left shifts. */
7487 if (GET_CODE (XEXP (x, 1)) == CONST_INT
7488 && INTVAL (XEXP (x, 1)) >= 0
7489 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT)
7491 enum machine_mode inner_mode = GET_MODE (x);
7492 int width = GET_MODE_BITSIZE (inner_mode);
7493 int count = INTVAL (XEXP (x, 1));
7494 unsigned HOST_WIDE_INT mode_mask = GET_MODE_MASK (inner_mode);
7495 unsigned HOST_WIDE_INT op_nonzero = nonzero_bits (XEXP (x, 0), mode);
7496 unsigned HOST_WIDE_INT inner = op_nonzero & mode_mask;
7497 unsigned HOST_WIDE_INT outer = 0;
7499 if (mode_width > width)
7500 outer = (op_nonzero & nonzero & ~ mode_mask);
7502 if (code == LSHIFTRT)
7504 else if (code == ASHIFTRT)
7508 /* If the sign bit may have been nonzero before the shift, we
7509 need to mark all the places it could have been copied to
7510 by the shift as possibly nonzero. */
7511 if (inner & ((HOST_WIDE_INT) 1 << (width - 1 - count)))
7512 inner |= (((HOST_WIDE_INT) 1 << count) - 1) << (width - count);
7514 else if (code == ASHIFT)
7517 inner = ((inner << (count % width)
7518 | (inner >> (width - (count % width)))) & mode_mask);
7520 nonzero &= (outer | inner);
7525 /* This is at most the number of bits in the mode. */
7526 nonzero = ((HOST_WIDE_INT) 1 << (floor_log2 (mode_width) + 1)) - 1;
7530 nonzero &= (nonzero_bits (XEXP (x, 1), mode)
7531 | nonzero_bits (XEXP (x, 2), mode));
7538 /* See the macro definition above. */
7539 #undef num_sign_bit_copies
7541 /* Return the number of bits at the high-order end of X that are known to
7542 be equal to the sign bit. X will be used in mode MODE; if MODE is
7543 VOIDmode, X will be used in its own mode. The returned value will always
7544 be between 1 and the number of bits in MODE. */
7547 num_sign_bit_copies (x, mode)
7549 enum machine_mode mode;
7551 enum rtx_code code = GET_CODE (x);
7553 int num0, num1, result;
7554 unsigned HOST_WIDE_INT nonzero;
7557 /* If we weren't given a mode, use the mode of X. If the mode is still
7558 VOIDmode, we don't know anything. Likewise if one of the modes is
7561 if (mode == VOIDmode)
7562 mode = GET_MODE (x);
7564 if (mode == VOIDmode || FLOAT_MODE_P (mode) || FLOAT_MODE_P (GET_MODE (x)))
7567 bitwidth = GET_MODE_BITSIZE (mode);
7569 /* For a smaller object, just ignore the high bits. */
7570 if (bitwidth < GET_MODE_BITSIZE (GET_MODE (x)))
7571 return MAX (1, (num_sign_bit_copies (x, GET_MODE (x))
7572 - (GET_MODE_BITSIZE (GET_MODE (x)) - bitwidth)));
7574 #ifndef WORD_REGISTER_OPERATIONS
7575 /* If this machine does not do all register operations on the entire
7576 register and MODE is wider than the mode of X, we can say nothing
7577 at all about the high-order bits. */
7578 if (GET_MODE (x) != VOIDmode && bitwidth > GET_MODE_BITSIZE (GET_MODE (x)))
7586 #ifdef POINTERS_EXTEND_UNSIGNED
7587 /* If pointers extend signed and this is a pointer in Pmode, say that
7588 all the bits above ptr_mode are known to be sign bit copies. */
7589 if (! POINTERS_EXTEND_UNSIGNED && GET_MODE (x) == Pmode && mode == Pmode
7590 && REGNO_POINTER_FLAG (REGNO (x)))
7591 return GET_MODE_BITSIZE (Pmode) - GET_MODE_BITSIZE (ptr_mode) + 1;
7594 if (reg_last_set_value[REGNO (x)] != 0
7595 && reg_last_set_mode[REGNO (x)] == mode
7596 && (REG_N_SETS (REGNO (x)) == 1
7597 || reg_last_set_label[REGNO (x)] == label_tick)
7598 && INSN_CUID (reg_last_set[REGNO (x)]) < subst_low_cuid)
7599 return reg_last_set_sign_bit_copies[REGNO (x)];
7601 tem = get_last_value (x);
7603 return num_sign_bit_copies (tem, mode);
7605 if (nonzero_sign_valid && reg_sign_bit_copies[REGNO (x)] != 0)
7606 return reg_sign_bit_copies[REGNO (x)];
7610 #ifdef LOAD_EXTEND_OP
7611 /* Some RISC machines sign-extend all loads of smaller than a word. */
7612 if (LOAD_EXTEND_OP (GET_MODE (x)) == SIGN_EXTEND)
7613 return MAX (1, bitwidth - GET_MODE_BITSIZE (GET_MODE (x)) + 1);
7618 /* If the constant is negative, take its 1's complement and remask.
7619 Then see how many zero bits we have. */
7620 nonzero = INTVAL (x) & GET_MODE_MASK (mode);
7621 if (bitwidth <= HOST_BITS_PER_WIDE_INT
7622 && (nonzero & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0)
7623 nonzero = (~ nonzero) & GET_MODE_MASK (mode);
7625 return (nonzero == 0 ? bitwidth : bitwidth - floor_log2 (nonzero) - 1);
7628 /* If this is a SUBREG for a promoted object that is sign-extended
7629 and we are looking at it in a wider mode, we know that at least the
7630 high-order bits are known to be sign bit copies. */
7632 if (SUBREG_PROMOTED_VAR_P (x) && ! SUBREG_PROMOTED_UNSIGNED_P (x))
7633 return MAX (bitwidth - GET_MODE_BITSIZE (GET_MODE (x)) + 1,
7634 num_sign_bit_copies (SUBREG_REG (x), mode));
7636 /* For a smaller object, just ignore the high bits. */
7637 if (bitwidth <= GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x))))
7639 num0 = num_sign_bit_copies (SUBREG_REG (x), VOIDmode);
7640 return MAX (1, (num0
7641 - (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x)))
7645 #ifdef WORD_REGISTER_OPERATIONS
7646 #ifdef LOAD_EXTEND_OP
7647 /* For paradoxical SUBREGs on machines where all register operations
7648 affect the entire register, just look inside. Note that we are
7649 passing MODE to the recursive call, so the number of sign bit copies
7650 will remain relative to that mode, not the inner mode. */
7652 /* This works only if loads sign extend. Otherwise, if we get a
7653 reload for the inner part, it may be loaded from the stack, and
7654 then we lose all sign bit copies that existed before the store
7657 if ((GET_MODE_SIZE (GET_MODE (x))
7658 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
7659 && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (x))) == SIGN_EXTEND)
7660 return num_sign_bit_copies (SUBREG_REG (x), mode);
7666 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
7667 return MAX (1, bitwidth - INTVAL (XEXP (x, 1)));
7671 return (bitwidth - GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
7672 + num_sign_bit_copies (XEXP (x, 0), VOIDmode));
7675 /* For a smaller object, just ignore the high bits. */
7676 num0 = num_sign_bit_copies (XEXP (x, 0), VOIDmode);
7677 return MAX (1, (num0 - (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
7681 return num_sign_bit_copies (XEXP (x, 0), mode);
7683 case ROTATE: case ROTATERT:
7684 /* If we are rotating left by a number of bits less than the number
7685 of sign bit copies, we can just subtract that amount from the
7687 if (GET_CODE (XEXP (x, 1)) == CONST_INT
7688 && INTVAL (XEXP (x, 1)) >= 0 && INTVAL (XEXP (x, 1)) < bitwidth)
7690 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
7691 return MAX (1, num0 - (code == ROTATE ? INTVAL (XEXP (x, 1))
7692 : bitwidth - INTVAL (XEXP (x, 1))));
7697 /* In general, this subtracts one sign bit copy. But if the value
7698 is known to be positive, the number of sign bit copies is the
7699 same as that of the input. Finally, if the input has just one bit
7700 that might be nonzero, all the bits are copies of the sign bit. */
7701 nonzero = nonzero_bits (XEXP (x, 0), mode);
7705 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
7707 && bitwidth <= HOST_BITS_PER_WIDE_INT
7708 && (((HOST_WIDE_INT) 1 << (bitwidth - 1)) & nonzero))
7713 case IOR: case AND: case XOR:
7714 case SMIN: case SMAX: case UMIN: case UMAX:
7715 /* Logical operations will preserve the number of sign-bit copies.
7716 MIN and MAX operations always return one of the operands. */
7717 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
7718 num1 = num_sign_bit_copies (XEXP (x, 1), mode);
7719 return MIN (num0, num1);
7721 case PLUS: case MINUS:
7722 /* For addition and subtraction, we can have a 1-bit carry. However,
7723 if we are subtracting 1 from a positive number, there will not
7724 be such a carry. Furthermore, if the positive number is known to
7725 be 0 or 1, we know the result is either -1 or 0. */
7727 if (code == PLUS && XEXP (x, 1) == constm1_rtx
7728 && bitwidth <= HOST_BITS_PER_WIDE_INT)
7730 nonzero = nonzero_bits (XEXP (x, 0), mode);
7731 if ((((HOST_WIDE_INT) 1 << (bitwidth - 1)) & nonzero) == 0)
7732 return (nonzero == 1 || nonzero == 0 ? bitwidth
7733 : bitwidth - floor_log2 (nonzero) - 1);
7736 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
7737 num1 = num_sign_bit_copies (XEXP (x, 1), mode);
7738 return MAX (1, MIN (num0, num1) - 1);
7741 /* The number of bits of the product is the sum of the number of
7742 bits of both terms. However, unless one of the terms if known
7743 to be positive, we must allow for an additional bit since negating
7744 a negative number can remove one sign bit copy. */
7746 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
7747 num1 = num_sign_bit_copies (XEXP (x, 1), mode);
7749 result = bitwidth - (bitwidth - num0) - (bitwidth - num1);
7751 && bitwidth <= HOST_BITS_PER_WIDE_INT
7752 && ((nonzero_bits (XEXP (x, 0), mode)
7753 & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0)
7754 && ((nonzero_bits (XEXP (x, 1), mode)
7755 & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0))
7758 return MAX (1, result);
7761 /* The result must be <= the first operand. */
7762 return num_sign_bit_copies (XEXP (x, 0), mode);
7765 /* The result must be <= the scond operand. */
7766 return num_sign_bit_copies (XEXP (x, 1), mode);
7769 /* Similar to unsigned division, except that we have to worry about
7770 the case where the divisor is negative, in which case we have
7772 result = num_sign_bit_copies (XEXP (x, 0), mode);
7774 && bitwidth <= HOST_BITS_PER_WIDE_INT
7775 && (nonzero_bits (XEXP (x, 1), mode)
7776 & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0)
7782 result = num_sign_bit_copies (XEXP (x, 1), mode);
7784 && bitwidth <= HOST_BITS_PER_WIDE_INT
7785 && (nonzero_bits (XEXP (x, 1), mode)
7786 & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0)
7792 /* Shifts by a constant add to the number of bits equal to the
7794 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
7795 if (GET_CODE (XEXP (x, 1)) == CONST_INT
7796 && INTVAL (XEXP (x, 1)) > 0)
7797 num0 = MIN (bitwidth, num0 + INTVAL (XEXP (x, 1)));
7802 /* Left shifts destroy copies. */
7803 if (GET_CODE (XEXP (x, 1)) != CONST_INT
7804 || INTVAL (XEXP (x, 1)) < 0
7805 || INTVAL (XEXP (x, 1)) >= bitwidth)
7808 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
7809 return MAX (1, num0 - INTVAL (XEXP (x, 1)));
7812 num0 = num_sign_bit_copies (XEXP (x, 1), mode);
7813 num1 = num_sign_bit_copies (XEXP (x, 2), mode);
7814 return MIN (num0, num1);
7816 case EQ: case NE: case GE: case GT: case LE: case LT:
7817 case GEU: case GTU: case LEU: case LTU:
7818 if (STORE_FLAG_VALUE == -1)
7822 /* If we haven't been able to figure it out by one of the above rules,
7823 see if some of the high-order bits are known to be zero. If so,
7824 count those bits and return one less than that amount. If we can't
7825 safely compute the mask for this mode, always return BITWIDTH. */
7827 if (bitwidth > HOST_BITS_PER_WIDE_INT)
7830 nonzero = nonzero_bits (x, mode);
7831 return (nonzero & ((HOST_WIDE_INT) 1 << (bitwidth - 1))
7832 ? 1 : bitwidth - floor_log2 (nonzero) - 1);
7835 /* Return the number of "extended" bits there are in X, when interpreted
7836 as a quantity in MODE whose signedness is indicated by UNSIGNEDP. For
7837 unsigned quantities, this is the number of high-order zero bits.
7838 For signed quantities, this is the number of copies of the sign bit
7839 minus 1. In both case, this function returns the number of "spare"
7840 bits. For example, if two quantities for which this function returns
7841 at least 1 are added, the addition is known not to overflow.
7843 This function will always return 0 unless called during combine, which
7844 implies that it must be called from a define_split. */
7847 extended_count (x, mode, unsignedp)
7849 enum machine_mode mode;
7852 if (nonzero_sign_valid == 0)
7856 ? (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
7857 && (GET_MODE_BITSIZE (mode) - 1
7858 - floor_log2 (nonzero_bits (x, mode))))
7859 : num_sign_bit_copies (x, mode) - 1);
7862 /* This function is called from `simplify_shift_const' to merge two
7863 outer operations. Specifically, we have already found that we need
7864 to perform operation *POP0 with constant *PCONST0 at the outermost
7865 position. We would now like to also perform OP1 with constant CONST1
7866 (with *POP0 being done last).
7868 Return 1 if we can do the operation and update *POP0 and *PCONST0 with
7869 the resulting operation. *PCOMP_P is set to 1 if we would need to
7870 complement the innermost operand, otherwise it is unchanged.
7872 MODE is the mode in which the operation will be done. No bits outside
7873 the width of this mode matter. It is assumed that the width of this mode
7874 is smaller than or equal to HOST_BITS_PER_WIDE_INT.
7876 If *POP0 or OP1 are NIL, it means no operation is required. Only NEG, PLUS,
7877 IOR, XOR, and AND are supported. We may set *POP0 to SET if the proper
7878 result is simply *PCONST0.
7880 If the resulting operation cannot be expressed as one operation, we
7881 return 0 and do not change *POP0, *PCONST0, and *PCOMP_P. */
7884 merge_outer_ops (pop0, pconst0, op1, const1, mode, pcomp_p)
7885 enum rtx_code *pop0;
7886 HOST_WIDE_INT *pconst0;
7888 HOST_WIDE_INT const1;
7889 enum machine_mode mode;
7892 enum rtx_code op0 = *pop0;
7893 HOST_WIDE_INT const0 = *pconst0;
7894 int width = GET_MODE_BITSIZE (mode);
7896 const0 &= GET_MODE_MASK (mode);
7897 const1 &= GET_MODE_MASK (mode);
7899 /* If OP0 is an AND, clear unimportant bits in CONST1. */
7903 /* If OP0 or OP1 is NIL, this is easy. Similarly if they are the same or
7906 if (op1 == NIL || op0 == SET)
7909 else if (op0 == NIL)
7910 op0 = op1, const0 = const1;
7912 else if (op0 == op1)
7934 /* Otherwise, if either is a PLUS or NEG, we can't do anything. */
7935 else if (op0 == PLUS || op1 == PLUS || op0 == NEG || op1 == NEG)
7938 /* If the two constants aren't the same, we can't do anything. The
7939 remaining six cases can all be done. */
7940 else if (const0 != const1)
7948 /* (a & b) | b == b */
7950 else /* op1 == XOR */
7951 /* (a ^ b) | b == a | b */
7957 /* (a & b) ^ b == (~a) & b */
7958 op0 = AND, *pcomp_p = 1;
7959 else /* op1 == IOR */
7960 /* (a | b) ^ b == a & ~b */
7961 op0 = AND, *pconst0 = ~ const0;
7966 /* (a | b) & b == b */
7968 else /* op1 == XOR */
7969 /* (a ^ b) & b) == (~a) & b */
7974 /* Check for NO-OP cases. */
7975 const0 &= GET_MODE_MASK (mode);
7977 && (op0 == IOR || op0 == XOR || op0 == PLUS))
7979 else if (const0 == 0 && op0 == AND)
7981 else if (const0 == GET_MODE_MASK (mode) && op0 == AND)
7984 /* If this would be an entire word for the target, but is not for
7985 the host, then sign-extend on the host so that the number will look
7986 the same way on the host that it would on the target.
7988 For example, when building a 64 bit alpha hosted 32 bit sparc
7989 targeted compiler, then we want the 32 bit unsigned value -1 to be
7990 represented as a 64 bit value -1, and not as 0x00000000ffffffff.
7991 The later confuses the sparc backend. */
7993 if (BITS_PER_WORD < HOST_BITS_PER_WIDE_INT && BITS_PER_WORD == width
7994 && (const0 & ((HOST_WIDE_INT) 1 << (width - 1))))
7995 const0 |= ((HOST_WIDE_INT) (-1) << width);
8003 /* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift.
8004 The result of the shift is RESULT_MODE. X, if non-zero, is an expression
8005 that we started with.
8007 The shift is normally computed in the widest mode we find in VAROP, as
8008 long as it isn't a different number of words than RESULT_MODE. Exceptions
8009 are ASHIFTRT and ROTATE, which are always done in their original mode, */
8012 simplify_shift_const (x, code, result_mode, varop, count)
8015 enum machine_mode result_mode;
8019 enum rtx_code orig_code = code;
8020 int orig_count = count;
8021 enum machine_mode mode = result_mode;
8022 enum machine_mode shift_mode, tmode;
8024 = (GET_MODE_SIZE (mode) + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD;
8025 /* We form (outer_op (code varop count) (outer_const)). */
8026 enum rtx_code outer_op = NIL;
8027 HOST_WIDE_INT outer_const = 0;
8029 int complement_p = 0;
8032 /* If we were given an invalid count, don't do anything except exactly
8033 what was requested. */
8035 if (count < 0 || count > GET_MODE_BITSIZE (mode))
8040 return gen_rtx (code, mode, varop, GEN_INT (count));
8043 /* Unless one of the branches of the `if' in this loop does a `continue',
8044 we will `break' the loop after the `if'. */
8048 /* If we have an operand of (clobber (const_int 0)), just return that
8050 if (GET_CODE (varop) == CLOBBER)
8053 /* If we discovered we had to complement VAROP, leave. Making a NOT
8054 here would cause an infinite loop. */
8058 /* Convert ROTATERT to ROTATE. */
8059 if (code == ROTATERT)
8060 code = ROTATE, count = GET_MODE_BITSIZE (result_mode) - count;
8062 /* We need to determine what mode we will do the shift in. If the
8063 shift is a right shift or a ROTATE, we must always do it in the mode
8064 it was originally done in. Otherwise, we can do it in MODE, the
8065 widest mode encountered. */
8067 = (code == ASHIFTRT || code == LSHIFTRT || code == ROTATE
8068 ? result_mode : mode);
8070 /* Handle cases where the count is greater than the size of the mode
8071 minus 1. For ASHIFT, use the size minus one as the count (this can
8072 occur when simplifying (lshiftrt (ashiftrt ..))). For rotates,
8073 take the count modulo the size. For other shifts, the result is
8076 Since these shifts are being produced by the compiler by combining
8077 multiple operations, each of which are defined, we know what the
8078 result is supposed to be. */
8080 if (count > GET_MODE_BITSIZE (shift_mode) - 1)
8082 if (code == ASHIFTRT)
8083 count = GET_MODE_BITSIZE (shift_mode) - 1;
8084 else if (code == ROTATE || code == ROTATERT)
8085 count %= GET_MODE_BITSIZE (shift_mode);
8088 /* We can't simply return zero because there may be an
8096 /* Negative counts are invalid and should not have been made (a
8097 programmer-specified negative count should have been handled
8102 /* An arithmetic right shift of a quantity known to be -1 or 0
8104 if (code == ASHIFTRT
8105 && (num_sign_bit_copies (varop, shift_mode)
8106 == GET_MODE_BITSIZE (shift_mode)))
8112 /* If we are doing an arithmetic right shift and discarding all but
8113 the sign bit copies, this is equivalent to doing a shift by the
8114 bitsize minus one. Convert it into that shift because it will often
8115 allow other simplifications. */
8117 if (code == ASHIFTRT
8118 && (count + num_sign_bit_copies (varop, shift_mode)
8119 >= GET_MODE_BITSIZE (shift_mode)))
8120 count = GET_MODE_BITSIZE (shift_mode) - 1;
8122 /* We simplify the tests below and elsewhere by converting
8123 ASHIFTRT to LSHIFTRT if we know the sign bit is clear.
8124 `make_compound_operation' will convert it to a ASHIFTRT for
8125 those machines (such as Vax) that don't have a LSHIFTRT. */
8126 if (GET_MODE_BITSIZE (shift_mode) <= HOST_BITS_PER_WIDE_INT
8128 && ((nonzero_bits (varop, shift_mode)
8129 & ((HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (shift_mode) - 1)))
8133 switch (GET_CODE (varop))
8139 new = expand_compound_operation (varop);
8148 /* If we have (xshiftrt (mem ...) C) and C is MODE_WIDTH
8149 minus the width of a smaller mode, we can do this with a
8150 SIGN_EXTEND or ZERO_EXTEND from the narrower memory location. */
8151 if ((code == ASHIFTRT || code == LSHIFTRT)
8152 && ! mode_dependent_address_p (XEXP (varop, 0))
8153 && ! MEM_VOLATILE_P (varop)
8154 && (tmode = mode_for_size (GET_MODE_BITSIZE (mode) - count,
8155 MODE_INT, 1)) != BLKmode)
8157 if (BYTES_BIG_ENDIAN)
8158 new = gen_rtx (MEM, tmode, XEXP (varop, 0));
8160 new = gen_rtx (MEM, tmode,
8161 plus_constant (XEXP (varop, 0),
8162 count / BITS_PER_UNIT));
8163 RTX_UNCHANGING_P (new) = RTX_UNCHANGING_P (varop);
8164 MEM_VOLATILE_P (new) = MEM_VOLATILE_P (varop);
8165 MEM_IN_STRUCT_P (new) = MEM_IN_STRUCT_P (varop);
8166 varop = gen_rtx_combine (code == ASHIFTRT ? SIGN_EXTEND
8167 : ZERO_EXTEND, mode, new);
8174 /* Similar to the case above, except that we can only do this if
8175 the resulting mode is the same as that of the underlying
8176 MEM and adjust the address depending on the *bits* endianness
8177 because of the way that bit-field extract insns are defined. */
8178 if ((code == ASHIFTRT || code == LSHIFTRT)
8179 && (tmode = mode_for_size (GET_MODE_BITSIZE (mode) - count,
8180 MODE_INT, 1)) != BLKmode
8181 && tmode == GET_MODE (XEXP (varop, 0)))
8183 if (BITS_BIG_ENDIAN)
8184 new = XEXP (varop, 0);
8187 new = copy_rtx (XEXP (varop, 0));
8188 SUBST (XEXP (new, 0),
8189 plus_constant (XEXP (new, 0),
8190 count / BITS_PER_UNIT));
8193 varop = gen_rtx_combine (code == ASHIFTRT ? SIGN_EXTEND
8194 : ZERO_EXTEND, mode, new);
8201 /* If VAROP is a SUBREG, strip it as long as the inner operand has
8202 the same number of words as what we've seen so far. Then store
8203 the widest mode in MODE. */
8204 if (subreg_lowpart_p (varop)
8205 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop)))
8206 > GET_MODE_SIZE (GET_MODE (varop)))
8207 && (((GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop)))
8208 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
8211 varop = SUBREG_REG (varop);
8212 if (GET_MODE_SIZE (GET_MODE (varop)) > GET_MODE_SIZE (mode))
8213 mode = GET_MODE (varop);
8219 /* Some machines use MULT instead of ASHIFT because MULT
8220 is cheaper. But it is still better on those machines to
8221 merge two shifts into one. */
8222 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
8223 && exact_log2 (INTVAL (XEXP (varop, 1))) >= 0)
8225 varop = gen_binary (ASHIFT, GET_MODE (varop), XEXP (varop, 0),
8226 GEN_INT (exact_log2 (INTVAL (XEXP (varop, 1)))));;
8232 /* Similar, for when divides are cheaper. */
8233 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
8234 && exact_log2 (INTVAL (XEXP (varop, 1))) >= 0)
8236 varop = gen_binary (LSHIFTRT, GET_MODE (varop), XEXP (varop, 0),
8237 GEN_INT (exact_log2 (INTVAL (XEXP (varop, 1)))));
8243 /* If we are extracting just the sign bit of an arithmetic right
8244 shift, that shift is not needed. */
8245 if (code == LSHIFTRT && count == GET_MODE_BITSIZE (result_mode) - 1)
8247 varop = XEXP (varop, 0);
8251 /* ... fall through ... */
8256 /* Here we have two nested shifts. The result is usually the
8257 AND of a new shift with a mask. We compute the result below. */
8258 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
8259 && INTVAL (XEXP (varop, 1)) >= 0
8260 && INTVAL (XEXP (varop, 1)) < GET_MODE_BITSIZE (GET_MODE (varop))
8261 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
8262 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
8264 enum rtx_code first_code = GET_CODE (varop);
8265 int first_count = INTVAL (XEXP (varop, 1));
8266 unsigned HOST_WIDE_INT mask;
8269 /* We have one common special case. We can't do any merging if
8270 the inner code is an ASHIFTRT of a smaller mode. However, if
8271 we have (ashift:M1 (subreg:M1 (ashiftrt:M2 FOO C1) 0) C2)
8272 with C2 == GET_MODE_BITSIZE (M1) - GET_MODE_BITSIZE (M2),
8273 we can convert it to
8274 (ashiftrt:M1 (ashift:M1 (and:M1 (subreg:M1 FOO 0 C2) C3) C1).
8275 This simplifies certain SIGN_EXTEND operations. */
8276 if (code == ASHIFT && first_code == ASHIFTRT
8277 && (GET_MODE_BITSIZE (result_mode)
8278 - GET_MODE_BITSIZE (GET_MODE (varop))) == count)
8280 /* C3 has the low-order C1 bits zero. */
8282 mask = (GET_MODE_MASK (mode)
8283 & ~ (((HOST_WIDE_INT) 1 << first_count) - 1));
8285 varop = simplify_and_const_int (NULL_RTX, result_mode,
8286 XEXP (varop, 0), mask);
8287 varop = simplify_shift_const (NULL_RTX, ASHIFT, result_mode,
8289 count = first_count;
8294 /* If this was (ashiftrt (ashift foo C1) C2) and FOO has more
8295 than C1 high-order bits equal to the sign bit, we can convert
8296 this to either an ASHIFT or a ASHIFTRT depending on the
8299 We cannot do this if VAROP's mode is not SHIFT_MODE. */
8301 if (code == ASHIFTRT && first_code == ASHIFT
8302 && GET_MODE (varop) == shift_mode
8303 && (num_sign_bit_copies (XEXP (varop, 0), shift_mode)
8306 count -= first_count;
8308 count = - count, code = ASHIFT;
8309 varop = XEXP (varop, 0);
8313 /* There are some cases we can't do. If CODE is ASHIFTRT,
8314 we can only do this if FIRST_CODE is also ASHIFTRT.
8316 We can't do the case when CODE is ROTATE and FIRST_CODE is
8319 If the mode of this shift is not the mode of the outer shift,
8320 we can't do this if either shift is a right shift or ROTATE.
8322 Finally, we can't do any of these if the mode is too wide
8323 unless the codes are the same.
8325 Handle the case where the shift codes are the same
8328 if (code == first_code)
8330 if (GET_MODE (varop) != result_mode
8331 && (code == ASHIFTRT || code == LSHIFTRT
8335 count += first_count;
8336 varop = XEXP (varop, 0);
8340 if (code == ASHIFTRT
8341 || (code == ROTATE && first_code == ASHIFTRT)
8342 || GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT
8343 || (GET_MODE (varop) != result_mode
8344 && (first_code == ASHIFTRT || first_code == LSHIFTRT
8345 || first_code == ROTATE
8346 || code == ROTATE)))
8349 /* To compute the mask to apply after the shift, shift the
8350 nonzero bits of the inner shift the same way the
8351 outer shift will. */
8353 mask_rtx = GEN_INT (nonzero_bits (varop, GET_MODE (varop)));
8356 = simplify_binary_operation (code, result_mode, mask_rtx,
8359 /* Give up if we can't compute an outer operation to use. */
8361 || GET_CODE (mask_rtx) != CONST_INT
8362 || ! merge_outer_ops (&outer_op, &outer_const, AND,
8364 result_mode, &complement_p))
8367 /* If the shifts are in the same direction, we add the
8368 counts. Otherwise, we subtract them. */
8369 if ((code == ASHIFTRT || code == LSHIFTRT)
8370 == (first_code == ASHIFTRT || first_code == LSHIFTRT))
8371 count += first_count;
8373 count -= first_count;
8375 /* If COUNT is positive, the new shift is usually CODE,
8376 except for the two exceptions below, in which case it is
8377 FIRST_CODE. If the count is negative, FIRST_CODE should
8380 && ((first_code == ROTATE && code == ASHIFT)
8381 || (first_code == ASHIFTRT && code == LSHIFTRT)))
8384 code = first_code, count = - count;
8386 varop = XEXP (varop, 0);
8390 /* If we have (A << B << C) for any shift, we can convert this to
8391 (A << C << B). This wins if A is a constant. Only try this if
8392 B is not a constant. */
8394 else if (GET_CODE (varop) == code
8395 && GET_CODE (XEXP (varop, 1)) != CONST_INT
8397 = simplify_binary_operation (code, mode,
8401 varop = gen_rtx_combine (code, mode, new, XEXP (varop, 1));
8408 /* Make this fit the case below. */
8409 varop = gen_rtx_combine (XOR, mode, XEXP (varop, 0),
8410 GEN_INT (GET_MODE_MASK (mode)));
8416 /* If we have (xshiftrt (ior (plus X (const_int -1)) X) C)
8417 with C the size of VAROP - 1 and the shift is logical if
8418 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
8419 we have an (le X 0) operation. If we have an arithmetic shift
8420 and STORE_FLAG_VALUE is 1 or we have a logical shift with
8421 STORE_FLAG_VALUE of -1, we have a (neg (le X 0)) operation. */
8423 if (GET_CODE (varop) == IOR && GET_CODE (XEXP (varop, 0)) == PLUS
8424 && XEXP (XEXP (varop, 0), 1) == constm1_rtx
8425 && (STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
8426 && (code == LSHIFTRT || code == ASHIFTRT)
8427 && count == GET_MODE_BITSIZE (GET_MODE (varop)) - 1
8428 && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
8431 varop = gen_rtx_combine (LE, GET_MODE (varop), XEXP (varop, 1),
8434 if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
8435 varop = gen_rtx_combine (NEG, GET_MODE (varop), varop);
8440 /* If we have (shift (logical)), move the logical to the outside
8441 to allow it to possibly combine with another logical and the
8442 shift to combine with another shift. This also canonicalizes to
8443 what a ZERO_EXTRACT looks like. Also, some machines have
8444 (and (shift)) insns. */
8446 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
8447 && (new = simplify_binary_operation (code, result_mode,
8449 GEN_INT (count))) != 0
8450 && GET_CODE(new) == CONST_INT
8451 && merge_outer_ops (&outer_op, &outer_const, GET_CODE (varop),
8452 INTVAL (new), result_mode, &complement_p))
8454 varop = XEXP (varop, 0);
8458 /* If we can't do that, try to simplify the shift in each arm of the
8459 logical expression, make a new logical expression, and apply
8460 the inverse distributive law. */
8462 rtx lhs = simplify_shift_const (NULL_RTX, code, shift_mode,
8463 XEXP (varop, 0), count);
8464 rtx rhs = simplify_shift_const (NULL_RTX, code, shift_mode,
8465 XEXP (varop, 1), count);
8467 varop = gen_binary (GET_CODE (varop), shift_mode, lhs, rhs);
8468 varop = apply_distributive_law (varop);
8475 /* convert (lshiftrt (eq FOO 0) C) to (xor FOO 1) if STORE_FLAG_VALUE
8476 says that the sign bit can be tested, FOO has mode MODE, C is
8477 GET_MODE_BITSIZE (MODE) - 1, and FOO has only its low-order bit
8478 that may be nonzero. */
8479 if (code == LSHIFTRT
8480 && XEXP (varop, 1) == const0_rtx
8481 && GET_MODE (XEXP (varop, 0)) == result_mode
8482 && count == GET_MODE_BITSIZE (result_mode) - 1
8483 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
8484 && ((STORE_FLAG_VALUE
8485 & ((HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (result_mode) - 1))))
8486 && nonzero_bits (XEXP (varop, 0), result_mode) == 1
8487 && merge_outer_ops (&outer_op, &outer_const, XOR,
8488 (HOST_WIDE_INT) 1, result_mode,
8491 varop = XEXP (varop, 0);
8498 /* (lshiftrt (neg A) C) where A is either 0 or 1 and C is one less
8499 than the number of bits in the mode is equivalent to A. */
8500 if (code == LSHIFTRT && count == GET_MODE_BITSIZE (result_mode) - 1
8501 && nonzero_bits (XEXP (varop, 0), result_mode) == 1)
8503 varop = XEXP (varop, 0);
8508 /* NEG commutes with ASHIFT since it is multiplication. Move the
8509 NEG outside to allow shifts to combine. */
8511 && merge_outer_ops (&outer_op, &outer_const, NEG,
8512 (HOST_WIDE_INT) 0, result_mode,
8515 varop = XEXP (varop, 0);
8521 /* (lshiftrt (plus A -1) C) where A is either 0 or 1 and C
8522 is one less than the number of bits in the mode is
8523 equivalent to (xor A 1). */
8524 if (code == LSHIFTRT && count == GET_MODE_BITSIZE (result_mode) - 1
8525 && XEXP (varop, 1) == constm1_rtx
8526 && nonzero_bits (XEXP (varop, 0), result_mode) == 1
8527 && merge_outer_ops (&outer_op, &outer_const, XOR,
8528 (HOST_WIDE_INT) 1, result_mode,
8532 varop = XEXP (varop, 0);
8536 /* If we have (xshiftrt (plus FOO BAR) C), and the only bits
8537 that might be nonzero in BAR are those being shifted out and those
8538 bits are known zero in FOO, we can replace the PLUS with FOO.
8539 Similarly in the other operand order. This code occurs when
8540 we are computing the size of a variable-size array. */
8542 if ((code == ASHIFTRT || code == LSHIFTRT)
8543 && count < HOST_BITS_PER_WIDE_INT
8544 && nonzero_bits (XEXP (varop, 1), result_mode) >> count == 0
8545 && (nonzero_bits (XEXP (varop, 1), result_mode)
8546 & nonzero_bits (XEXP (varop, 0), result_mode)) == 0)
8548 varop = XEXP (varop, 0);
8551 else if ((code == ASHIFTRT || code == LSHIFTRT)
8552 && count < HOST_BITS_PER_WIDE_INT
8553 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
8554 && 0 == (nonzero_bits (XEXP (varop, 0), result_mode)
8556 && 0 == (nonzero_bits (XEXP (varop, 0), result_mode)
8557 & nonzero_bits (XEXP (varop, 1),
8560 varop = XEXP (varop, 1);
8564 /* (ashift (plus foo C) N) is (plus (ashift foo N) C'). */
8566 && GET_CODE (XEXP (varop, 1)) == CONST_INT
8567 && (new = simplify_binary_operation (ASHIFT, result_mode,
8569 GEN_INT (count))) != 0
8570 && GET_CODE(new) == CONST_INT
8571 && merge_outer_ops (&outer_op, &outer_const, PLUS,
8572 INTVAL (new), result_mode, &complement_p))
8574 varop = XEXP (varop, 0);
8580 /* If we have (xshiftrt (minus (ashiftrt X C)) X) C)
8581 with C the size of VAROP - 1 and the shift is logical if
8582 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
8583 we have a (gt X 0) operation. If the shift is arithmetic with
8584 STORE_FLAG_VALUE of 1 or logical with STORE_FLAG_VALUE == -1,
8585 we have a (neg (gt X 0)) operation. */
8587 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
8588 && GET_CODE (XEXP (varop, 0)) == ASHIFTRT
8589 && count == GET_MODE_BITSIZE (GET_MODE (varop)) - 1
8590 && (code == LSHIFTRT || code == ASHIFTRT)
8591 && GET_CODE (XEXP (XEXP (varop, 0), 1)) == CONST_INT
8592 && INTVAL (XEXP (XEXP (varop, 0), 1)) == count
8593 && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
8596 varop = gen_rtx_combine (GT, GET_MODE (varop), XEXP (varop, 1),
8599 if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
8600 varop = gen_rtx_combine (NEG, GET_MODE (varop), varop);
8610 /* We need to determine what mode to do the shift in. If the shift is
8611 a right shift or ROTATE, we must always do it in the mode it was
8612 originally done in. Otherwise, we can do it in MODE, the widest mode
8613 encountered. The code we care about is that of the shift that will
8614 actually be done, not the shift that was originally requested. */
8616 = (code == ASHIFTRT || code == LSHIFTRT || code == ROTATE
8617 ? result_mode : mode);
8619 /* We have now finished analyzing the shift. The result should be
8620 a shift of type CODE with SHIFT_MODE shifting VAROP COUNT places. If
8621 OUTER_OP is non-NIL, it is an operation that needs to be applied
8622 to the result of the shift. OUTER_CONST is the relevant constant,
8623 but we must turn off all bits turned off in the shift.
8625 If we were passed a value for X, see if we can use any pieces of
8626 it. If not, make new rtx. */
8628 if (x && GET_RTX_CLASS (GET_CODE (x)) == '2'
8629 && GET_CODE (XEXP (x, 1)) == CONST_INT
8630 && INTVAL (XEXP (x, 1)) == count)
8631 const_rtx = XEXP (x, 1);
8633 const_rtx = GEN_INT (count);
8635 if (x && GET_CODE (XEXP (x, 0)) == SUBREG
8636 && GET_MODE (XEXP (x, 0)) == shift_mode
8637 && SUBREG_REG (XEXP (x, 0)) == varop)
8638 varop = XEXP (x, 0);
8639 else if (GET_MODE (varop) != shift_mode)
8640 varop = gen_lowpart_for_combine (shift_mode, varop);
8642 /* If we can't make the SUBREG, try to return what we were given. */
8643 if (GET_CODE (varop) == CLOBBER)
8644 return x ? x : varop;
8646 new = simplify_binary_operation (code, shift_mode, varop, const_rtx);
8651 if (x == 0 || GET_CODE (x) != code || GET_MODE (x) != shift_mode)
8652 x = gen_rtx_combine (code, shift_mode, varop, const_rtx);
8654 SUBST (XEXP (x, 0), varop);
8655 SUBST (XEXP (x, 1), const_rtx);
8658 /* If we have an outer operation and we just made a shift, it is
8659 possible that we could have simplified the shift were it not
8660 for the outer operation. So try to do the simplification
8663 if (outer_op != NIL && GET_CODE (x) == code
8664 && GET_CODE (XEXP (x, 1)) == CONST_INT)
8665 x = simplify_shift_const (x, code, shift_mode, XEXP (x, 0),
8666 INTVAL (XEXP (x, 1)));
8668 /* If we were doing a LSHIFTRT in a wider mode than it was originally,
8669 turn off all the bits that the shift would have turned off. */
8670 if (orig_code == LSHIFTRT && result_mode != shift_mode)
8671 x = simplify_and_const_int (NULL_RTX, shift_mode, x,
8672 GET_MODE_MASK (result_mode) >> orig_count);
8674 /* Do the remainder of the processing in RESULT_MODE. */
8675 x = gen_lowpart_for_combine (result_mode, x);
8677 /* If COMPLEMENT_P is set, we have to complement X before doing the outer
8680 x = gen_unary (NOT, result_mode, result_mode, x);
8682 if (outer_op != NIL)
8684 if (GET_MODE_BITSIZE (result_mode) < HOST_BITS_PER_WIDE_INT)
8686 int width = GET_MODE_BITSIZE (result_mode);
8688 outer_const &= GET_MODE_MASK (result_mode);
8690 /* If this would be an entire word for the target, but is not for
8691 the host, then sign-extend on the host so that the number will
8692 look the same way on the host that it would on the target.
8694 For example, when building a 64 bit alpha hosted 32 bit sparc
8695 targeted compiler, then we want the 32 bit unsigned value -1 to be
8696 represented as a 64 bit value -1, and not as 0x00000000ffffffff.
8697 The later confuses the sparc backend. */
8699 if (BITS_PER_WORD < HOST_BITS_PER_WIDE_INT && BITS_PER_WORD == width
8700 && (outer_const & ((HOST_WIDE_INT) 1 << (width - 1))))
8701 outer_const |= ((HOST_WIDE_INT) (-1) << width);
8704 if (outer_op == AND)
8705 x = simplify_and_const_int (NULL_RTX, result_mode, x, outer_const);
8706 else if (outer_op == SET)
8707 /* This means that we have determined that the result is
8708 equivalent to a constant. This should be rare. */
8709 x = GEN_INT (outer_const);
8710 else if (GET_RTX_CLASS (outer_op) == '1')
8711 x = gen_unary (outer_op, result_mode, result_mode, x);
8713 x = gen_binary (outer_op, result_mode, x, GEN_INT (outer_const));
8719 /* Like recog, but we receive the address of a pointer to a new pattern.
8720 We try to match the rtx that the pointer points to.
8721 If that fails, we may try to modify or replace the pattern,
8722 storing the replacement into the same pointer object.
8724 Modifications include deletion or addition of CLOBBERs.
8726 PNOTES is a pointer to a location where any REG_UNUSED notes added for
8727 the CLOBBERs are placed.
8729 PADDED_SCRATCHES is set to the number of (clobber (scratch)) patterns
8732 The value is the final insn code from the pattern ultimately matched,
8736 recog_for_combine (pnewpat, insn, pnotes, padded_scratches)
8740 int *padded_scratches;
8742 register rtx pat = *pnewpat;
8743 int insn_code_number;
8744 int num_clobbers_to_add = 0;
8748 *padded_scratches = 0;
8750 /* If PAT is a PARALLEL, check to see if it contains the CLOBBER
8751 we use to indicate that something didn't match. If we find such a
8752 thing, force rejection. */
8753 if (GET_CODE (pat) == PARALLEL)
8754 for (i = XVECLEN (pat, 0) - 1; i >= 0; i--)
8755 if (GET_CODE (XVECEXP (pat, 0, i)) == CLOBBER
8756 && XEXP (XVECEXP (pat, 0, i), 0) == const0_rtx)
8759 /* Is the result of combination a valid instruction? */
8760 insn_code_number = recog (pat, insn, &num_clobbers_to_add);
8762 /* If it isn't, there is the possibility that we previously had an insn
8763 that clobbered some register as a side effect, but the combined
8764 insn doesn't need to do that. So try once more without the clobbers
8765 unless this represents an ASM insn. */
8767 if (insn_code_number < 0 && ! check_asm_operands (pat)
8768 && GET_CODE (pat) == PARALLEL)
8772 for (pos = 0, i = 0; i < XVECLEN (pat, 0); i++)
8773 if (GET_CODE (XVECEXP (pat, 0, i)) != CLOBBER)
8776 SUBST (XVECEXP (pat, 0, pos), XVECEXP (pat, 0, i));
8780 SUBST_INT (XVECLEN (pat, 0), pos);
8783 pat = XVECEXP (pat, 0, 0);
8785 insn_code_number = recog (pat, insn, &num_clobbers_to_add);
8788 /* If we had any clobbers to add, make a new pattern than contains
8789 them. Then check to make sure that all of them are dead. */
8790 if (num_clobbers_to_add)
8792 rtx newpat = gen_rtx (PARALLEL, VOIDmode,
8793 gen_rtvec (GET_CODE (pat) == PARALLEL
8794 ? XVECLEN (pat, 0) + num_clobbers_to_add
8795 : num_clobbers_to_add + 1));
8797 if (GET_CODE (pat) == PARALLEL)
8798 for (i = 0; i < XVECLEN (pat, 0); i++)
8799 XVECEXP (newpat, 0, i) = XVECEXP (pat, 0, i);
8801 XVECEXP (newpat, 0, 0) = pat;
8803 add_clobbers (newpat, insn_code_number);
8805 for (i = XVECLEN (newpat, 0) - num_clobbers_to_add;
8806 i < XVECLEN (newpat, 0); i++)
8808 if (GET_CODE (XEXP (XVECEXP (newpat, 0, i), 0)) == REG
8809 && ! reg_dead_at_p (XEXP (XVECEXP (newpat, 0, i), 0), insn))
8811 else if (GET_CODE (XEXP (XVECEXP (newpat, 0, i), 0)) == SCRATCH)
8812 (*padded_scratches)++;
8813 notes = gen_rtx (EXPR_LIST, REG_UNUSED,
8814 XEXP (XVECEXP (newpat, 0, i), 0), notes);
8822 return insn_code_number;
8825 /* Like gen_lowpart but for use by combine. In combine it is not possible
8826 to create any new pseudoregs. However, it is safe to create
8827 invalid memory addresses, because combine will try to recognize
8828 them and all they will do is make the combine attempt fail.
8830 If for some reason this cannot do its job, an rtx
8831 (clobber (const_int 0)) is returned.
8832 An insn containing that will not be recognized. */
8837 gen_lowpart_for_combine (mode, x)
8838 enum machine_mode mode;
8843 if (GET_MODE (x) == mode)
8846 /* We can only support MODE being wider than a word if X is a
8847 constant integer or has a mode the same size. */
8849 if (GET_MODE_SIZE (mode) > UNITS_PER_WORD
8850 && ! ((GET_MODE (x) == VOIDmode
8851 && (GET_CODE (x) == CONST_INT
8852 || GET_CODE (x) == CONST_DOUBLE))
8853 || GET_MODE_SIZE (GET_MODE (x)) == GET_MODE_SIZE (mode)))
8854 return gen_rtx (CLOBBER, GET_MODE (x), const0_rtx);
8856 /* X might be a paradoxical (subreg (mem)). In that case, gen_lowpart
8857 won't know what to do. So we will strip off the SUBREG here and
8858 process normally. */
8859 if (GET_CODE (x) == SUBREG && GET_CODE (SUBREG_REG (x)) == MEM)
8862 if (GET_MODE (x) == mode)
8866 result = gen_lowpart_common (mode, x);
8868 && GET_CODE (result) == SUBREG
8869 && GET_CODE (SUBREG_REG (result)) == REG
8870 && REGNO (SUBREG_REG (result)) >= FIRST_PSEUDO_REGISTER
8871 && (GET_MODE_SIZE (GET_MODE (result))
8872 != GET_MODE_SIZE (GET_MODE (SUBREG_REG (result)))))
8873 REG_CHANGES_SIZE (REGNO (SUBREG_REG (result))) = 1;
8878 if (GET_CODE (x) == MEM)
8880 register int offset = 0;
8883 /* Refuse to work on a volatile memory ref or one with a mode-dependent
8885 if (MEM_VOLATILE_P (x) || mode_dependent_address_p (XEXP (x, 0)))
8886 return gen_rtx (CLOBBER, GET_MODE (x), const0_rtx);
8888 /* If we want to refer to something bigger than the original memref,
8889 generate a perverse subreg instead. That will force a reload
8890 of the original memref X. */
8891 if (GET_MODE_SIZE (GET_MODE (x)) < GET_MODE_SIZE (mode))
8892 return gen_rtx (SUBREG, mode, x, 0);
8894 if (WORDS_BIG_ENDIAN)
8895 offset = (MAX (GET_MODE_SIZE (GET_MODE (x)), UNITS_PER_WORD)
8896 - MAX (GET_MODE_SIZE (mode), UNITS_PER_WORD));
8897 if (BYTES_BIG_ENDIAN)
8899 /* Adjust the address so that the address-after-the-data is
8901 offset -= (MIN (UNITS_PER_WORD, GET_MODE_SIZE (mode))
8902 - MIN (UNITS_PER_WORD, GET_MODE_SIZE (GET_MODE (x))));
8904 new = gen_rtx (MEM, mode, plus_constant (XEXP (x, 0), offset));
8905 RTX_UNCHANGING_P (new) = RTX_UNCHANGING_P (x);
8906 MEM_VOLATILE_P (new) = MEM_VOLATILE_P (x);
8907 MEM_IN_STRUCT_P (new) = MEM_IN_STRUCT_P (x);
8911 /* If X is a comparison operator, rewrite it in a new mode. This
8912 probably won't match, but may allow further simplifications. */
8913 else if (GET_RTX_CLASS (GET_CODE (x)) == '<')
8914 return gen_rtx_combine (GET_CODE (x), mode, XEXP (x, 0), XEXP (x, 1));
8916 /* If we couldn't simplify X any other way, just enclose it in a
8917 SUBREG. Normally, this SUBREG won't match, but some patterns may
8918 include an explicit SUBREG or we may simplify it further in combine. */
8923 if (WORDS_BIG_ENDIAN && GET_MODE_SIZE (GET_MODE (x)) > UNITS_PER_WORD)
8924 word = ((GET_MODE_SIZE (GET_MODE (x))
8925 - MAX (GET_MODE_SIZE (mode), UNITS_PER_WORD))
8927 return gen_rtx (SUBREG, mode, x, word);
8931 /* Make an rtx expression. This is a subset of gen_rtx and only supports
8932 expressions of 1, 2, or 3 operands, each of which are rtx expressions.
8934 If the identical expression was previously in the insn (in the undobuf),
8935 it will be returned. Only if it is not found will a new expression
8940 gen_rtx_combine VPROTO((enum rtx_code code, enum machine_mode mode, ...))
8944 enum machine_mode mode;
8957 code = va_arg (p, enum rtx_code);
8958 mode = va_arg (p, enum machine_mode);
8961 n_args = GET_RTX_LENGTH (code);
8962 fmt = GET_RTX_FORMAT (code);
8964 if (n_args == 0 || n_args > 3)
8967 /* Get each arg and verify that it is supposed to be an expression. */
8968 for (j = 0; j < n_args; j++)
8973 args[j] = va_arg (p, rtx);
8976 /* See if this is in undobuf. Be sure we don't use objects that came
8977 from another insn; this could produce circular rtl structures. */
8979 for (undo = undobuf.undos; undo != undobuf.previous_undos; undo = undo->next)
8981 && GET_CODE (undo->old_contents.r) == code
8982 && GET_MODE (undo->old_contents.r) == mode)
8984 for (j = 0; j < n_args; j++)
8985 if (XEXP (undo->old_contents.r, j) != args[j])
8989 return undo->old_contents.r;
8992 /* Otherwise make a new rtx. We know we have 1, 2, or 3 args.
8993 Use rtx_alloc instead of gen_rtx because it's faster on RISC. */
8994 rt = rtx_alloc (code);
8995 PUT_MODE (rt, mode);
8996 XEXP (rt, 0) = args[0];
8999 XEXP (rt, 1) = args[1];
9001 XEXP (rt, 2) = args[2];
9006 /* These routines make binary and unary operations by first seeing if they
9007 fold; if not, a new expression is allocated. */
9010 gen_binary (code, mode, op0, op1)
9012 enum machine_mode mode;
9018 if (GET_RTX_CLASS (code) == 'c'
9019 && (GET_CODE (op0) == CONST_INT
9020 || (CONSTANT_P (op0) && GET_CODE (op1) != CONST_INT)))
9021 tem = op0, op0 = op1, op1 = tem;
9023 if (GET_RTX_CLASS (code) == '<')
9025 enum machine_mode op_mode = GET_MODE (op0);
9027 /* Strip the COMPARE from (REL_OP (compare X Y) 0) to get
9028 just (REL_OP X Y). */
9029 if (GET_CODE (op0) == COMPARE && op1 == const0_rtx)
9031 op1 = XEXP (op0, 1);
9032 op0 = XEXP (op0, 0);
9033 op_mode = GET_MODE (op0);
9036 if (op_mode == VOIDmode)
9037 op_mode = GET_MODE (op1);
9038 result = simplify_relational_operation (code, op_mode, op0, op1);
9041 result = simplify_binary_operation (code, mode, op0, op1);
9046 /* Put complex operands first and constants second. */
9047 if (GET_RTX_CLASS (code) == 'c'
9048 && ((CONSTANT_P (op0) && GET_CODE (op1) != CONST_INT)
9049 || (GET_RTX_CLASS (GET_CODE (op0)) == 'o'
9050 && GET_RTX_CLASS (GET_CODE (op1)) != 'o')
9051 || (GET_CODE (op0) == SUBREG
9052 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (op0))) == 'o'
9053 && GET_RTX_CLASS (GET_CODE (op1)) != 'o')))
9054 return gen_rtx_combine (code, mode, op1, op0);
9056 return gen_rtx_combine (code, mode, op0, op1);
9060 gen_unary (code, mode, op0_mode, op0)
9062 enum machine_mode mode, op0_mode;
9065 rtx result = simplify_unary_operation (code, mode, op0, op0_mode);
9070 return gen_rtx_combine (code, mode, op0);
9073 /* Simplify a comparison between *POP0 and *POP1 where CODE is the
9074 comparison code that will be tested.
9076 The result is a possibly different comparison code to use. *POP0 and
9077 *POP1 may be updated.
9079 It is possible that we might detect that a comparison is either always
9080 true or always false. However, we do not perform general constant
9081 folding in combine, so this knowledge isn't useful. Such tautologies
9082 should have been detected earlier. Hence we ignore all such cases. */
9084 static enum rtx_code
9085 simplify_comparison (code, pop0, pop1)
9094 enum machine_mode mode, tmode;
9096 /* Try a few ways of applying the same transformation to both operands. */
9099 #ifndef WORD_REGISTER_OPERATIONS
9100 /* The test below this one won't handle SIGN_EXTENDs on these machines,
9101 so check specially. */
9102 if (code != GTU && code != GEU && code != LTU && code != LEU
9103 && GET_CODE (op0) == ASHIFTRT && GET_CODE (op1) == ASHIFTRT
9104 && GET_CODE (XEXP (op0, 0)) == ASHIFT
9105 && GET_CODE (XEXP (op1, 0)) == ASHIFT
9106 && GET_CODE (XEXP (XEXP (op0, 0), 0)) == SUBREG
9107 && GET_CODE (XEXP (XEXP (op1, 0), 0)) == SUBREG
9108 && (GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0)))
9109 == GET_MODE (SUBREG_REG (XEXP (XEXP (op1, 0), 0))))
9110 && GET_CODE (XEXP (op0, 1)) == CONST_INT
9111 && GET_CODE (XEXP (op1, 1)) == CONST_INT
9112 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
9113 && GET_CODE (XEXP (XEXP (op1, 0), 1)) == CONST_INT
9114 && INTVAL (XEXP (op0, 1)) == INTVAL (XEXP (op1, 1))
9115 && INTVAL (XEXP (op0, 1)) == INTVAL (XEXP (XEXP (op0, 0), 1))
9116 && INTVAL (XEXP (op0, 1)) == INTVAL (XEXP (XEXP (op1, 0), 1))
9117 && (INTVAL (XEXP (op0, 1))
9118 == (GET_MODE_BITSIZE (GET_MODE (op0))
9120 (GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0))))))))
9122 op0 = SUBREG_REG (XEXP (XEXP (op0, 0), 0));
9123 op1 = SUBREG_REG (XEXP (XEXP (op1, 0), 0));
9127 /* If both operands are the same constant shift, see if we can ignore the
9128 shift. We can if the shift is a rotate or if the bits shifted out of
9129 this shift are known to be zero for both inputs and if the type of
9130 comparison is compatible with the shift. */
9131 if (GET_CODE (op0) == GET_CODE (op1)
9132 && GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
9133 && ((GET_CODE (op0) == ROTATE && (code == NE || code == EQ))
9134 || ((GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFT)
9135 && (code != GT && code != LT && code != GE && code != LE))
9136 || (GET_CODE (op0) == ASHIFTRT
9137 && (code != GTU && code != LTU
9138 && code != GEU && code != GEU)))
9139 && GET_CODE (XEXP (op0, 1)) == CONST_INT
9140 && INTVAL (XEXP (op0, 1)) >= 0
9141 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT
9142 && XEXP (op0, 1) == XEXP (op1, 1))
9144 enum machine_mode mode = GET_MODE (op0);
9145 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
9146 int shift_count = INTVAL (XEXP (op0, 1));
9148 if (GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFTRT)
9149 mask &= (mask >> shift_count) << shift_count;
9150 else if (GET_CODE (op0) == ASHIFT)
9151 mask = (mask & (mask << shift_count)) >> shift_count;
9153 if ((nonzero_bits (XEXP (op0, 0), mode) & ~ mask) == 0
9154 && (nonzero_bits (XEXP (op1, 0), mode) & ~ mask) == 0)
9155 op0 = XEXP (op0, 0), op1 = XEXP (op1, 0);
9160 /* If both operands are AND's of a paradoxical SUBREG by constant, the
9161 SUBREGs are of the same mode, and, in both cases, the AND would
9162 be redundant if the comparison was done in the narrower mode,
9163 do the comparison in the narrower mode (e.g., we are AND'ing with 1
9164 and the operand's possibly nonzero bits are 0xffffff01; in that case
9165 if we only care about QImode, we don't need the AND). This case
9166 occurs if the output mode of an scc insn is not SImode and
9167 STORE_FLAG_VALUE == 1 (e.g., the 386).
9169 Similarly, check for a case where the AND's are ZERO_EXTEND
9170 operations from some narrower mode even though a SUBREG is not
9173 else if (GET_CODE (op0) == AND && GET_CODE (op1) == AND
9174 && GET_CODE (XEXP (op0, 1)) == CONST_INT
9175 && GET_CODE (XEXP (op1, 1)) == CONST_INT)
9177 rtx inner_op0 = XEXP (op0, 0);
9178 rtx inner_op1 = XEXP (op1, 0);
9179 HOST_WIDE_INT c0 = INTVAL (XEXP (op0, 1));
9180 HOST_WIDE_INT c1 = INTVAL (XEXP (op1, 1));
9183 if (GET_CODE (inner_op0) == SUBREG && GET_CODE (inner_op1) == SUBREG
9184 && (GET_MODE_SIZE (GET_MODE (inner_op0))
9185 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (inner_op0))))
9186 && (GET_MODE (SUBREG_REG (inner_op0))
9187 == GET_MODE (SUBREG_REG (inner_op1)))
9188 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0)))
9189 <= HOST_BITS_PER_WIDE_INT)
9190 && (0 == ((~c0) & nonzero_bits (SUBREG_REG (inner_op0),
9191 GET_MODE (SUBREG_REG (op0)))))
9192 && (0 == ((~c1) & nonzero_bits (SUBREG_REG (inner_op1),
9193 GET_MODE (SUBREG_REG (inner_op1))))))
9195 op0 = SUBREG_REG (inner_op0);
9196 op1 = SUBREG_REG (inner_op1);
9198 /* The resulting comparison is always unsigned since we masked
9199 off the original sign bit. */
9200 code = unsigned_condition (code);
9206 for (tmode = GET_CLASS_NARROWEST_MODE
9207 (GET_MODE_CLASS (GET_MODE (op0)));
9208 tmode != GET_MODE (op0); tmode = GET_MODE_WIDER_MODE (tmode))
9209 if (c0 == GET_MODE_MASK (tmode))
9211 op0 = gen_lowpart_for_combine (tmode, inner_op0);
9212 op1 = gen_lowpart_for_combine (tmode, inner_op1);
9213 code = unsigned_condition (code);
9222 /* If both operands are NOT, we can strip off the outer operation
9223 and adjust the comparison code for swapped operands; similarly for
9224 NEG, except that this must be an equality comparison. */
9225 else if ((GET_CODE (op0) == NOT && GET_CODE (op1) == NOT)
9226 || (GET_CODE (op0) == NEG && GET_CODE (op1) == NEG
9227 && (code == EQ || code == NE)))
9228 op0 = XEXP (op0, 0), op1 = XEXP (op1, 0), code = swap_condition (code);
9234 /* If the first operand is a constant, swap the operands and adjust the
9235 comparison code appropriately, but don't do this if the second operand
9236 is already a constant integer. */
9237 if (CONSTANT_P (op0) && GET_CODE (op1) != CONST_INT)
9239 tem = op0, op0 = op1, op1 = tem;
9240 code = swap_condition (code);
9243 /* We now enter a loop during which we will try to simplify the comparison.
9244 For the most part, we only are concerned with comparisons with zero,
9245 but some things may really be comparisons with zero but not start
9246 out looking that way. */
9248 while (GET_CODE (op1) == CONST_INT)
9250 enum machine_mode mode = GET_MODE (op0);
9251 int mode_width = GET_MODE_BITSIZE (mode);
9252 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
9253 int equality_comparison_p;
9254 int sign_bit_comparison_p;
9255 int unsigned_comparison_p;
9256 HOST_WIDE_INT const_op;
9258 /* We only want to handle integral modes. This catches VOIDmode,
9259 CCmode, and the floating-point modes. An exception is that we
9260 can handle VOIDmode if OP0 is a COMPARE or a comparison
9263 if (GET_MODE_CLASS (mode) != MODE_INT
9264 && ! (mode == VOIDmode
9265 && (GET_CODE (op0) == COMPARE
9266 || GET_RTX_CLASS (GET_CODE (op0)) == '<')))
9269 /* Get the constant we are comparing against and turn off all bits
9270 not on in our mode. */
9271 const_op = INTVAL (op1);
9272 if (mode_width <= HOST_BITS_PER_WIDE_INT)
9275 /* If we are comparing against a constant power of two and the value
9276 being compared can only have that single bit nonzero (e.g., it was
9277 `and'ed with that bit), we can replace this with a comparison
9280 && (code == EQ || code == NE || code == GE || code == GEU
9281 || code == LT || code == LTU)
9282 && mode_width <= HOST_BITS_PER_WIDE_INT
9283 && exact_log2 (const_op) >= 0
9284 && nonzero_bits (op0, mode) == const_op)
9286 code = (code == EQ || code == GE || code == GEU ? NE : EQ);
9287 op1 = const0_rtx, const_op = 0;
9290 /* Similarly, if we are comparing a value known to be either -1 or
9291 0 with -1, change it to the opposite comparison against zero. */
9294 && (code == EQ || code == NE || code == GT || code == LE
9295 || code == GEU || code == LTU)
9296 && num_sign_bit_copies (op0, mode) == mode_width)
9298 code = (code == EQ || code == LE || code == GEU ? NE : EQ);
9299 op1 = const0_rtx, const_op = 0;
9302 /* Do some canonicalizations based on the comparison code. We prefer
9303 comparisons against zero and then prefer equality comparisons.
9304 If we can reduce the size of a constant, we will do that too. */
9309 /* < C is equivalent to <= (C - 1) */
9313 op1 = GEN_INT (const_op);
9315 /* ... fall through to LE case below. */
9321 /* <= C is equivalent to < (C + 1); we do this for C < 0 */
9325 op1 = GEN_INT (const_op);
9329 /* If we are doing a <= 0 comparison on a value known to have
9330 a zero sign bit, we can replace this with == 0. */
9331 else if (const_op == 0
9332 && mode_width <= HOST_BITS_PER_WIDE_INT
9333 && (nonzero_bits (op0, mode)
9334 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)
9339 /* >= C is equivalent to > (C - 1). */
9343 op1 = GEN_INT (const_op);
9345 /* ... fall through to GT below. */
9351 /* > C is equivalent to >= (C + 1); we do this for C < 0*/
9355 op1 = GEN_INT (const_op);
9359 /* If we are doing a > 0 comparison on a value known to have
9360 a zero sign bit, we can replace this with != 0. */
9361 else if (const_op == 0
9362 && mode_width <= HOST_BITS_PER_WIDE_INT
9363 && (nonzero_bits (op0, mode)
9364 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)
9369 /* < C is equivalent to <= (C - 1). */
9373 op1 = GEN_INT (const_op);
9375 /* ... fall through ... */
9378 /* (unsigned) < 0x80000000 is equivalent to >= 0. */
9379 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
9380 && (const_op == (HOST_WIDE_INT) 1 << (mode_width - 1)))
9382 const_op = 0, op1 = const0_rtx;
9390 /* unsigned <= 0 is equivalent to == 0 */
9394 /* (unsigned) <= 0x7fffffff is equivalent to >= 0. */
9395 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
9396 && (const_op == ((HOST_WIDE_INT) 1 << (mode_width - 1)) - 1))
9398 const_op = 0, op1 = const0_rtx;
9404 /* >= C is equivalent to < (C - 1). */
9408 op1 = GEN_INT (const_op);
9410 /* ... fall through ... */
9413 /* (unsigned) >= 0x80000000 is equivalent to < 0. */
9414 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
9415 && (const_op == (HOST_WIDE_INT) 1 << (mode_width - 1)))
9417 const_op = 0, op1 = const0_rtx;
9425 /* unsigned > 0 is equivalent to != 0 */
9429 /* (unsigned) > 0x7fffffff is equivalent to < 0. */
9430 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
9431 && (const_op == ((HOST_WIDE_INT) 1 << (mode_width - 1)) - 1))
9433 const_op = 0, op1 = const0_rtx;
9439 /* Compute some predicates to simplify code below. */
9441 equality_comparison_p = (code == EQ || code == NE);
9442 sign_bit_comparison_p = ((code == LT || code == GE) && const_op == 0);
9443 unsigned_comparison_p = (code == LTU || code == LEU || code == GTU
9446 /* If this is a sign bit comparison and we can do arithmetic in
9447 MODE, say that we will only be needing the sign bit of OP0. */
9448 if (sign_bit_comparison_p
9449 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
9450 op0 = force_to_mode (op0, mode,
9452 << (GET_MODE_BITSIZE (mode) - 1)),
9455 /* Now try cases based on the opcode of OP0. If none of the cases
9456 does a "continue", we exit this loop immediately after the
9459 switch (GET_CODE (op0))
9462 /* If we are extracting a single bit from a variable position in
9463 a constant that has only a single bit set and are comparing it
9464 with zero, we can convert this into an equality comparison
9465 between the position and the location of the single bit. */
9467 if (GET_CODE (XEXP (op0, 0)) == CONST_INT
9468 && XEXP (op0, 1) == const1_rtx
9469 && equality_comparison_p && const_op == 0
9470 && (i = exact_log2 (INTVAL (XEXP (op0, 0)))) >= 0)
9472 if (BITS_BIG_ENDIAN)
9474 i = (GET_MODE_BITSIZE
9475 (insn_operand_mode[(int) CODE_FOR_extzv][1]) - 1 - i);
9477 i = BITS_PER_WORD - 1 - i;
9480 op0 = XEXP (op0, 2);
9484 /* Result is nonzero iff shift count is equal to I. */
9485 code = reverse_condition (code);
9489 /* ... fall through ... */
9492 tem = expand_compound_operation (op0);
9501 /* If testing for equality, we can take the NOT of the constant. */
9502 if (equality_comparison_p
9503 && (tem = simplify_unary_operation (NOT, mode, op1, mode)) != 0)
9505 op0 = XEXP (op0, 0);
9510 /* If just looking at the sign bit, reverse the sense of the
9512 if (sign_bit_comparison_p)
9514 op0 = XEXP (op0, 0);
9515 code = (code == GE ? LT : GE);
9521 /* If testing for equality, we can take the NEG of the constant. */
9522 if (equality_comparison_p
9523 && (tem = simplify_unary_operation (NEG, mode, op1, mode)) != 0)
9525 op0 = XEXP (op0, 0);
9530 /* The remaining cases only apply to comparisons with zero. */
9534 /* When X is ABS or is known positive,
9535 (neg X) is < 0 if and only if X != 0. */
9537 if (sign_bit_comparison_p
9538 && (GET_CODE (XEXP (op0, 0)) == ABS
9539 || (mode_width <= HOST_BITS_PER_WIDE_INT
9540 && (nonzero_bits (XEXP (op0, 0), mode)
9541 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)))
9543 op0 = XEXP (op0, 0);
9544 code = (code == LT ? NE : EQ);
9548 /* If we have NEG of something whose two high-order bits are the
9549 same, we know that "(-a) < 0" is equivalent to "a > 0". */
9550 if (num_sign_bit_copies (op0, mode) >= 2)
9552 op0 = XEXP (op0, 0);
9553 code = swap_condition (code);
9559 /* If we are testing equality and our count is a constant, we
9560 can perform the inverse operation on our RHS. */
9561 if (equality_comparison_p && GET_CODE (XEXP (op0, 1)) == CONST_INT
9562 && (tem = simplify_binary_operation (ROTATERT, mode,
9563 op1, XEXP (op0, 1))) != 0)
9565 op0 = XEXP (op0, 0);
9570 /* If we are doing a < 0 or >= 0 comparison, it means we are testing
9571 a particular bit. Convert it to an AND of a constant of that
9572 bit. This will be converted into a ZERO_EXTRACT. */
9573 if (const_op == 0 && sign_bit_comparison_p
9574 && GET_CODE (XEXP (op0, 1)) == CONST_INT
9575 && mode_width <= HOST_BITS_PER_WIDE_INT)
9577 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
9580 - INTVAL (XEXP (op0, 1)))));
9581 code = (code == LT ? NE : EQ);
9585 /* ... fall through ... */
9588 /* ABS is ignorable inside an equality comparison with zero. */
9589 if (const_op == 0 && equality_comparison_p)
9591 op0 = XEXP (op0, 0);
9598 /* Can simplify (compare (zero/sign_extend FOO) CONST)
9599 to (compare FOO CONST) if CONST fits in FOO's mode and we
9600 are either testing inequality or have an unsigned comparison
9601 with ZERO_EXTEND or a signed comparison with SIGN_EXTEND. */
9602 if (! unsigned_comparison_p
9603 && (GET_MODE_BITSIZE (GET_MODE (XEXP (op0, 0)))
9604 <= HOST_BITS_PER_WIDE_INT)
9605 && ((unsigned HOST_WIDE_INT) const_op
9606 < (((HOST_WIDE_INT) 1
9607 << (GET_MODE_BITSIZE (GET_MODE (XEXP (op0, 0))) - 1)))))
9609 op0 = XEXP (op0, 0);
9615 /* Check for the case where we are comparing A - C1 with C2,
9616 both constants are smaller than 1/2 the maximum positive
9617 value in MODE, and the comparison is equality or unsigned.
9618 In that case, if A is either zero-extended to MODE or has
9619 sufficient sign bits so that the high-order bit in MODE
9620 is a copy of the sign in the inner mode, we can prove that it is
9621 safe to do the operation in the wider mode. This simplifies
9622 many range checks. */
9624 if (mode_width <= HOST_BITS_PER_WIDE_INT
9625 && subreg_lowpart_p (op0)
9626 && GET_CODE (SUBREG_REG (op0)) == PLUS
9627 && GET_CODE (XEXP (SUBREG_REG (op0), 1)) == CONST_INT
9628 && INTVAL (XEXP (SUBREG_REG (op0), 1)) < 0
9629 && (- INTVAL (XEXP (SUBREG_REG (op0), 1))
9630 < GET_MODE_MASK (mode) / 2)
9631 && (unsigned HOST_WIDE_INT) const_op < GET_MODE_MASK (mode) / 2
9632 && (0 == (nonzero_bits (XEXP (SUBREG_REG (op0), 0),
9633 GET_MODE (SUBREG_REG (op0)))
9634 & ~ GET_MODE_MASK (mode))
9635 || (num_sign_bit_copies (XEXP (SUBREG_REG (op0), 0),
9636 GET_MODE (SUBREG_REG (op0)))
9637 > (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0)))
9638 - GET_MODE_BITSIZE (mode)))))
9640 op0 = SUBREG_REG (op0);
9644 /* If the inner mode is narrower and we are extracting the low part,
9645 we can treat the SUBREG as if it were a ZERO_EXTEND. */
9646 if (subreg_lowpart_p (op0)
9647 && GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0))) < mode_width)
9648 /* Fall through */ ;
9652 /* ... fall through ... */
9655 if ((unsigned_comparison_p || equality_comparison_p)
9656 && (GET_MODE_BITSIZE (GET_MODE (XEXP (op0, 0)))
9657 <= HOST_BITS_PER_WIDE_INT)
9658 && ((unsigned HOST_WIDE_INT) const_op
9659 < GET_MODE_MASK (GET_MODE (XEXP (op0, 0)))))
9661 op0 = XEXP (op0, 0);
9667 /* (eq (plus X A) B) -> (eq X (minus B A)). We can only do
9668 this for equality comparisons due to pathological cases involving
9670 if (equality_comparison_p
9671 && 0 != (tem = simplify_binary_operation (MINUS, mode,
9672 op1, XEXP (op0, 1))))
9674 op0 = XEXP (op0, 0);
9679 /* (plus (abs X) (const_int -1)) is < 0 if and only if X == 0. */
9680 if (const_op == 0 && XEXP (op0, 1) == constm1_rtx
9681 && GET_CODE (XEXP (op0, 0)) == ABS && sign_bit_comparison_p)
9683 op0 = XEXP (XEXP (op0, 0), 0);
9684 code = (code == LT ? EQ : NE);
9690 /* (eq (minus A B) C) -> (eq A (plus B C)) or
9691 (eq B (minus A C)), whichever simplifies. We can only do
9692 this for equality comparisons due to pathological cases involving
9694 if (equality_comparison_p
9695 && 0 != (tem = simplify_binary_operation (PLUS, mode,
9696 XEXP (op0, 1), op1)))
9698 op0 = XEXP (op0, 0);
9703 if (equality_comparison_p
9704 && 0 != (tem = simplify_binary_operation (MINUS, mode,
9705 XEXP (op0, 0), op1)))
9707 op0 = XEXP (op0, 1);
9712 /* The sign bit of (minus (ashiftrt X C) X), where C is the number
9713 of bits in X minus 1, is one iff X > 0. */
9714 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == ASHIFTRT
9715 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
9716 && INTVAL (XEXP (XEXP (op0, 0), 1)) == mode_width - 1
9717 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
9719 op0 = XEXP (op0, 1);
9720 code = (code == GE ? LE : GT);
9726 /* (eq (xor A B) C) -> (eq A (xor B C)). This is a simplification
9727 if C is zero or B is a constant. */
9728 if (equality_comparison_p
9729 && 0 != (tem = simplify_binary_operation (XOR, mode,
9730 XEXP (op0, 1), op1)))
9732 op0 = XEXP (op0, 0);
9739 case LT: case LTU: case LE: case LEU:
9740 case GT: case GTU: case GE: case GEU:
9741 /* We can't do anything if OP0 is a condition code value, rather
9742 than an actual data value. */
9745 || XEXP (op0, 0) == cc0_rtx
9747 || GET_MODE_CLASS (GET_MODE (XEXP (op0, 0))) == MODE_CC)
9750 /* Get the two operands being compared. */
9751 if (GET_CODE (XEXP (op0, 0)) == COMPARE)
9752 tem = XEXP (XEXP (op0, 0), 0), tem1 = XEXP (XEXP (op0, 0), 1);
9754 tem = XEXP (op0, 0), tem1 = XEXP (op0, 1);
9756 /* Check for the cases where we simply want the result of the
9757 earlier test or the opposite of that result. */
9759 || (code == EQ && reversible_comparison_p (op0))
9760 || (GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
9761 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
9762 && (STORE_FLAG_VALUE
9763 & (((HOST_WIDE_INT) 1
9764 << (GET_MODE_BITSIZE (GET_MODE (op0)) - 1))))
9766 || (code == GE && reversible_comparison_p (op0)))))
9768 code = (code == LT || code == NE
9769 ? GET_CODE (op0) : reverse_condition (GET_CODE (op0)));
9770 op0 = tem, op1 = tem1;
9776 /* The sign bit of (ior (plus X (const_int -1)) X) is non-zero
9778 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == PLUS
9779 && XEXP (XEXP (op0, 0), 1) == constm1_rtx
9780 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
9782 op0 = XEXP (op0, 1);
9783 code = (code == GE ? GT : LE);
9789 /* Convert (and (xshift 1 X) Y) to (and (lshiftrt Y X) 1). This
9790 will be converted to a ZERO_EXTRACT later. */
9791 if (const_op == 0 && equality_comparison_p
9792 && GET_CODE (XEXP (op0, 0)) == ASHIFT
9793 && XEXP (XEXP (op0, 0), 0) == const1_rtx)
9795 op0 = simplify_and_const_int
9796 (op0, mode, gen_rtx_combine (LSHIFTRT, mode,
9798 XEXP (XEXP (op0, 0), 1)),
9803 /* If we are comparing (and (lshiftrt X C1) C2) for equality with
9804 zero and X is a comparison and C1 and C2 describe only bits set
9805 in STORE_FLAG_VALUE, we can compare with X. */
9806 if (const_op == 0 && equality_comparison_p
9807 && mode_width <= HOST_BITS_PER_WIDE_INT
9808 && GET_CODE (XEXP (op0, 1)) == CONST_INT
9809 && GET_CODE (XEXP (op0, 0)) == LSHIFTRT
9810 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
9811 && INTVAL (XEXP (XEXP (op0, 0), 1)) >= 0
9812 && INTVAL (XEXP (XEXP (op0, 0), 1)) < HOST_BITS_PER_WIDE_INT)
9814 mask = ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
9815 << INTVAL (XEXP (XEXP (op0, 0), 1)));
9816 if ((~ STORE_FLAG_VALUE & mask) == 0
9817 && (GET_RTX_CLASS (GET_CODE (XEXP (XEXP (op0, 0), 0))) == '<'
9818 || ((tem = get_last_value (XEXP (XEXP (op0, 0), 0))) != 0
9819 && GET_RTX_CLASS (GET_CODE (tem)) == '<')))
9821 op0 = XEXP (XEXP (op0, 0), 0);
9826 /* If we are doing an equality comparison of an AND of a bit equal
9827 to the sign bit, replace this with a LT or GE comparison of
9828 the underlying value. */
9829 if (equality_comparison_p
9831 && GET_CODE (XEXP (op0, 1)) == CONST_INT
9832 && mode_width <= HOST_BITS_PER_WIDE_INT
9833 && ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
9834 == (HOST_WIDE_INT) 1 << (mode_width - 1)))
9836 op0 = XEXP (op0, 0);
9837 code = (code == EQ ? GE : LT);
9841 /* If this AND operation is really a ZERO_EXTEND from a narrower
9842 mode, the constant fits within that mode, and this is either an
9843 equality or unsigned comparison, try to do this comparison in
9844 the narrower mode. */
9845 if ((equality_comparison_p || unsigned_comparison_p)
9846 && GET_CODE (XEXP (op0, 1)) == CONST_INT
9847 && (i = exact_log2 ((INTVAL (XEXP (op0, 1))
9848 & GET_MODE_MASK (mode))
9850 && const_op >> i == 0
9851 && (tmode = mode_for_size (i, MODE_INT, 1)) != BLKmode)
9853 op0 = gen_lowpart_for_combine (tmode, XEXP (op0, 0));
9859 /* If we have (compare (ashift FOO N) (const_int C)) and
9860 the high order N bits of FOO (N+1 if an inequality comparison)
9861 are known to be zero, we can do this by comparing FOO with C
9862 shifted right N bits so long as the low-order N bits of C are
9864 if (GET_CODE (XEXP (op0, 1)) == CONST_INT
9865 && INTVAL (XEXP (op0, 1)) >= 0
9866 && ((INTVAL (XEXP (op0, 1)) + ! equality_comparison_p)
9867 < HOST_BITS_PER_WIDE_INT)
9869 & (((HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1))) - 1)) == 0)
9870 && mode_width <= HOST_BITS_PER_WIDE_INT
9871 && (nonzero_bits (XEXP (op0, 0), mode)
9872 & ~ (mask >> (INTVAL (XEXP (op0, 1))
9873 + ! equality_comparison_p))) == 0)
9875 const_op >>= INTVAL (XEXP (op0, 1));
9876 op1 = GEN_INT (const_op);
9877 op0 = XEXP (op0, 0);
9881 /* If we are doing a sign bit comparison, it means we are testing
9882 a particular bit. Convert it to the appropriate AND. */
9883 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 1)) == CONST_INT
9884 && mode_width <= HOST_BITS_PER_WIDE_INT)
9886 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
9889 - INTVAL (XEXP (op0, 1)))));
9890 code = (code == LT ? NE : EQ);
9894 /* If this an equality comparison with zero and we are shifting
9895 the low bit to the sign bit, we can convert this to an AND of the
9897 if (const_op == 0 && equality_comparison_p
9898 && GET_CODE (XEXP (op0, 1)) == CONST_INT
9899 && INTVAL (XEXP (op0, 1)) == mode_width - 1)
9901 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
9908 /* If this is an equality comparison with zero, we can do this
9909 as a logical shift, which might be much simpler. */
9910 if (equality_comparison_p && const_op == 0
9911 && GET_CODE (XEXP (op0, 1)) == CONST_INT)
9913 op0 = simplify_shift_const (NULL_RTX, LSHIFTRT, mode,
9915 INTVAL (XEXP (op0, 1)));
9919 /* If OP0 is a sign extension and CODE is not an unsigned comparison,
9920 do the comparison in a narrower mode. */
9921 if (! unsigned_comparison_p
9922 && GET_CODE (XEXP (op0, 1)) == CONST_INT
9923 && GET_CODE (XEXP (op0, 0)) == ASHIFT
9924 && XEXP (op0, 1) == XEXP (XEXP (op0, 0), 1)
9925 && (tmode = mode_for_size (mode_width - INTVAL (XEXP (op0, 1)),
9926 MODE_INT, 1)) != BLKmode
9927 && ((unsigned HOST_WIDE_INT) const_op <= GET_MODE_MASK (tmode)
9928 || ((unsigned HOST_WIDE_INT) - const_op
9929 <= GET_MODE_MASK (tmode))))
9931 op0 = gen_lowpart_for_combine (tmode, XEXP (XEXP (op0, 0), 0));
9935 /* ... fall through ... */
9937 /* If we have (compare (xshiftrt FOO N) (const_int C)) and
9938 the low order N bits of FOO are known to be zero, we can do this
9939 by comparing FOO with C shifted left N bits so long as no
9941 if (GET_CODE (XEXP (op0, 1)) == CONST_INT
9942 && INTVAL (XEXP (op0, 1)) >= 0
9943 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT
9944 && mode_width <= HOST_BITS_PER_WIDE_INT
9945 && (nonzero_bits (XEXP (op0, 0), mode)
9946 & (((HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1))) - 1)) == 0
9948 || (floor_log2 (const_op) + INTVAL (XEXP (op0, 1))
9951 const_op <<= INTVAL (XEXP (op0, 1));
9952 op1 = GEN_INT (const_op);
9953 op0 = XEXP (op0, 0);
9957 /* If we are using this shift to extract just the sign bit, we
9958 can replace this with an LT or GE comparison. */
9960 && (equality_comparison_p || sign_bit_comparison_p)
9961 && GET_CODE (XEXP (op0, 1)) == CONST_INT
9962 && INTVAL (XEXP (op0, 1)) == mode_width - 1)
9964 op0 = XEXP (op0, 0);
9965 code = (code == NE || code == GT ? LT : GE);
9974 /* Now make any compound operations involved in this comparison. Then,
9975 check for an outmost SUBREG on OP0 that isn't doing anything or is
9976 paradoxical. The latter case can only occur when it is known that the
9977 "extra" bits will be zero. Therefore, it is safe to remove the SUBREG.
9978 We can never remove a SUBREG for a non-equality comparison because the
9979 sign bit is in a different place in the underlying object. */
9981 op0 = make_compound_operation (op0, op1 == const0_rtx ? COMPARE : SET);
9982 op1 = make_compound_operation (op1, SET);
9984 if (GET_CODE (op0) == SUBREG && subreg_lowpart_p (op0)
9985 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
9986 && (code == NE || code == EQ)
9987 && ((GET_MODE_SIZE (GET_MODE (op0))
9988 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (op0))))))
9990 op0 = SUBREG_REG (op0);
9991 op1 = gen_lowpart_for_combine (GET_MODE (op0), op1);
9994 else if (GET_CODE (op0) == SUBREG && subreg_lowpart_p (op0)
9995 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
9996 && (code == NE || code == EQ)
9997 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0)))
9998 <= HOST_BITS_PER_WIDE_INT)
9999 && (nonzero_bits (SUBREG_REG (op0), GET_MODE (SUBREG_REG (op0)))
10000 & ~ GET_MODE_MASK (GET_MODE (op0))) == 0
10001 && (tem = gen_lowpart_for_combine (GET_MODE (SUBREG_REG (op0)),
10003 (nonzero_bits (tem, GET_MODE (SUBREG_REG (op0)))
10004 & ~ GET_MODE_MASK (GET_MODE (op0))) == 0))
10005 op0 = SUBREG_REG (op0), op1 = tem;
10007 /* We now do the opposite procedure: Some machines don't have compare
10008 insns in all modes. If OP0's mode is an integer mode smaller than a
10009 word and we can't do a compare in that mode, see if there is a larger
10010 mode for which we can do the compare. There are a number of cases in
10011 which we can use the wider mode. */
10013 mode = GET_MODE (op0);
10014 if (mode != VOIDmode && GET_MODE_CLASS (mode) == MODE_INT
10015 && GET_MODE_SIZE (mode) < UNITS_PER_WORD
10016 && cmp_optab->handlers[(int) mode].insn_code == CODE_FOR_nothing)
10017 for (tmode = GET_MODE_WIDER_MODE (mode);
10019 && GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT);
10020 tmode = GET_MODE_WIDER_MODE (tmode))
10021 if (cmp_optab->handlers[(int) tmode].insn_code != CODE_FOR_nothing)
10023 /* If the only nonzero bits in OP0 and OP1 are those in the
10024 narrower mode and this is an equality or unsigned comparison,
10025 we can use the wider mode. Similarly for sign-extended
10026 values, in which case it is true for all comparisons. */
10027 if (((code == EQ || code == NE
10028 || code == GEU || code == GTU || code == LEU || code == LTU)
10029 && (nonzero_bits (op0, tmode) & ~ GET_MODE_MASK (mode)) == 0
10030 && (nonzero_bits (op1, tmode) & ~ GET_MODE_MASK (mode)) == 0)
10031 || ((num_sign_bit_copies (op0, tmode)
10032 > GET_MODE_BITSIZE (tmode) - GET_MODE_BITSIZE (mode))
10033 && (num_sign_bit_copies (op1, tmode)
10034 > GET_MODE_BITSIZE (tmode) - GET_MODE_BITSIZE (mode))))
10036 op0 = gen_lowpart_for_combine (tmode, op0);
10037 op1 = gen_lowpart_for_combine (tmode, op1);
10041 /* If this is a test for negative, we can make an explicit
10042 test of the sign bit. */
10044 if (op1 == const0_rtx && (code == LT || code == GE)
10045 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
10047 op0 = gen_binary (AND, tmode,
10048 gen_lowpart_for_combine (tmode, op0),
10049 GEN_INT ((HOST_WIDE_INT) 1
10050 << (GET_MODE_BITSIZE (mode) - 1)));
10051 code = (code == LT) ? NE : EQ;
10056 #ifdef CANONICALIZE_COMPARISON
10057 /* If this machine only supports a subset of valid comparisons, see if we
10058 can convert an unsupported one into a supported one. */
10059 CANONICALIZE_COMPARISON (code, op0, op1);
10068 /* Return 1 if we know that X, a comparison operation, is not operating
10069 on a floating-point value or is EQ or NE, meaning that we can safely
10073 reversible_comparison_p (x)
10076 if (TARGET_FLOAT_FORMAT != IEEE_FLOAT_FORMAT
10078 || GET_CODE (x) == NE || GET_CODE (x) == EQ)
10081 switch (GET_MODE_CLASS (GET_MODE (XEXP (x, 0))))
10084 case MODE_PARTIAL_INT:
10085 case MODE_COMPLEX_INT:
10089 /* If the mode of the condition codes tells us that this is safe,
10090 we need look no further. */
10091 if (REVERSIBLE_CC_MODE (GET_MODE (XEXP (x, 0))))
10094 /* Otherwise try and find where the condition codes were last set and
10096 x = get_last_value (XEXP (x, 0));
10097 return (x && GET_CODE (x) == COMPARE
10098 && ! FLOAT_MODE_P (GET_MODE (XEXP (x, 0))));
10104 /* Utility function for following routine. Called when X is part of a value
10105 being stored into reg_last_set_value. Sets reg_last_set_table_tick
10106 for each register mentioned. Similar to mention_regs in cse.c */
10109 update_table_tick (x)
10112 register enum rtx_code code = GET_CODE (x);
10113 register char *fmt = GET_RTX_FORMAT (code);
10118 int regno = REGNO (x);
10119 int endregno = regno + (regno < FIRST_PSEUDO_REGISTER
10120 ? HARD_REGNO_NREGS (regno, GET_MODE (x)) : 1);
10122 for (i = regno; i < endregno; i++)
10123 reg_last_set_table_tick[i] = label_tick;
10128 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
10129 /* Note that we can't have an "E" in values stored; see
10130 get_last_value_validate. */
10132 update_table_tick (XEXP (x, i));
10135 /* Record that REG is set to VALUE in insn INSN. If VALUE is zero, we
10136 are saying that the register is clobbered and we no longer know its
10137 value. If INSN is zero, don't update reg_last_set; this is only permitted
10138 with VALUE also zero and is used to invalidate the register. */
10141 record_value_for_reg (reg, insn, value)
10146 int regno = REGNO (reg);
10147 int endregno = regno + (regno < FIRST_PSEUDO_REGISTER
10148 ? HARD_REGNO_NREGS (regno, GET_MODE (reg)) : 1);
10151 /* If VALUE contains REG and we have a previous value for REG, substitute
10152 the previous value. */
10153 if (value && insn && reg_overlap_mentioned_p (reg, value))
10157 /* Set things up so get_last_value is allowed to see anything set up to
10159 subst_low_cuid = INSN_CUID (insn);
10160 tem = get_last_value (reg);
10163 value = replace_rtx (copy_rtx (value), reg, tem);
10166 /* For each register modified, show we don't know its value, that
10167 we don't know about its bitwise content, that its value has been
10168 updated, and that we don't know the location of the death of the
10170 for (i = regno; i < endregno; i ++)
10173 reg_last_set[i] = insn;
10174 reg_last_set_value[i] = 0;
10175 reg_last_set_mode[i] = 0;
10176 reg_last_set_nonzero_bits[i] = 0;
10177 reg_last_set_sign_bit_copies[i] = 0;
10178 reg_last_death[i] = 0;
10181 /* Mark registers that are being referenced in this value. */
10183 update_table_tick (value);
10185 /* Now update the status of each register being set.
10186 If someone is using this register in this block, set this register
10187 to invalid since we will get confused between the two lives in this
10188 basic block. This makes using this register always invalid. In cse, we
10189 scan the table to invalidate all entries using this register, but this
10190 is too much work for us. */
10192 for (i = regno; i < endregno; i++)
10194 reg_last_set_label[i] = label_tick;
10195 if (value && reg_last_set_table_tick[i] == label_tick)
10196 reg_last_set_invalid[i] = 1;
10198 reg_last_set_invalid[i] = 0;
10201 /* The value being assigned might refer to X (like in "x++;"). In that
10202 case, we must replace it with (clobber (const_int 0)) to prevent
10204 if (value && ! get_last_value_validate (&value, insn,
10205 reg_last_set_label[regno], 0))
10207 value = copy_rtx (value);
10208 if (! get_last_value_validate (&value, insn,
10209 reg_last_set_label[regno], 1))
10213 /* For the main register being modified, update the value, the mode, the
10214 nonzero bits, and the number of sign bit copies. */
10216 reg_last_set_value[regno] = value;
10220 subst_low_cuid = INSN_CUID (insn);
10221 reg_last_set_mode[regno] = GET_MODE (reg);
10222 reg_last_set_nonzero_bits[regno] = nonzero_bits (value, GET_MODE (reg));
10223 reg_last_set_sign_bit_copies[regno]
10224 = num_sign_bit_copies (value, GET_MODE (reg));
10228 /* Used for communication between the following two routines. */
10229 static rtx record_dead_insn;
10231 /* Called via note_stores from record_dead_and_set_regs to handle one
10232 SET or CLOBBER in an insn. */
10235 record_dead_and_set_regs_1 (dest, setter)
10238 if (GET_CODE (dest) == SUBREG)
10239 dest = SUBREG_REG (dest);
10241 if (GET_CODE (dest) == REG)
10243 /* If we are setting the whole register, we know its value. Otherwise
10244 show that we don't know the value. We can handle SUBREG in
10246 if (GET_CODE (setter) == SET && dest == SET_DEST (setter))
10247 record_value_for_reg (dest, record_dead_insn, SET_SRC (setter));
10248 else if (GET_CODE (setter) == SET
10249 && GET_CODE (SET_DEST (setter)) == SUBREG
10250 && SUBREG_REG (SET_DEST (setter)) == dest
10251 && GET_MODE_BITSIZE (GET_MODE (dest)) <= BITS_PER_WORD
10252 && subreg_lowpart_p (SET_DEST (setter)))
10253 record_value_for_reg (dest, record_dead_insn,
10254 gen_lowpart_for_combine (GET_MODE (dest),
10255 SET_SRC (setter)));
10257 record_value_for_reg (dest, record_dead_insn, NULL_RTX);
10259 else if (GET_CODE (dest) == MEM
10260 /* Ignore pushes, they clobber nothing. */
10261 && ! push_operand (dest, GET_MODE (dest)))
10262 mem_last_set = INSN_CUID (record_dead_insn);
10265 /* Update the records of when each REG was most recently set or killed
10266 for the things done by INSN. This is the last thing done in processing
10267 INSN in the combiner loop.
10269 We update reg_last_set, reg_last_set_value, reg_last_set_mode,
10270 reg_last_set_nonzero_bits, reg_last_set_sign_bit_copies, reg_last_death,
10271 and also the similar information mem_last_set (which insn most recently
10272 modified memory) and last_call_cuid (which insn was the most recent
10273 subroutine call). */
10276 record_dead_and_set_regs (insn)
10282 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
10284 if (REG_NOTE_KIND (link) == REG_DEAD
10285 && GET_CODE (XEXP (link, 0)) == REG)
10287 int regno = REGNO (XEXP (link, 0));
10289 = regno + (regno < FIRST_PSEUDO_REGISTER
10290 ? HARD_REGNO_NREGS (regno, GET_MODE (XEXP (link, 0)))
10293 for (i = regno; i < endregno; i++)
10294 reg_last_death[i] = insn;
10296 else if (REG_NOTE_KIND (link) == REG_INC)
10297 record_value_for_reg (XEXP (link, 0), insn, NULL_RTX);
10300 if (GET_CODE (insn) == CALL_INSN)
10302 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
10303 if (call_used_regs[i])
10305 reg_last_set_value[i] = 0;
10306 reg_last_set_mode[i] = 0;
10307 reg_last_set_nonzero_bits[i] = 0;
10308 reg_last_set_sign_bit_copies[i] = 0;
10309 reg_last_death[i] = 0;
10312 last_call_cuid = mem_last_set = INSN_CUID (insn);
10315 record_dead_insn = insn;
10316 note_stores (PATTERN (insn), record_dead_and_set_regs_1);
10319 /* Utility routine for the following function. Verify that all the registers
10320 mentioned in *LOC are valid when *LOC was part of a value set when
10321 label_tick == TICK. Return 0 if some are not.
10323 If REPLACE is non-zero, replace the invalid reference with
10324 (clobber (const_int 0)) and return 1. This replacement is useful because
10325 we often can get useful information about the form of a value (e.g., if
10326 it was produced by a shift that always produces -1 or 0) even though
10327 we don't know exactly what registers it was produced from. */
10330 get_last_value_validate (loc, insn, tick, replace)
10337 char *fmt = GET_RTX_FORMAT (GET_CODE (x));
10338 int len = GET_RTX_LENGTH (GET_CODE (x));
10341 if (GET_CODE (x) == REG)
10343 int regno = REGNO (x);
10344 int endregno = regno + (regno < FIRST_PSEUDO_REGISTER
10345 ? HARD_REGNO_NREGS (regno, GET_MODE (x)) : 1);
10348 for (j = regno; j < endregno; j++)
10349 if (reg_last_set_invalid[j]
10350 /* If this is a pseudo-register that was only set once, it is
10352 || (! (regno >= FIRST_PSEUDO_REGISTER && REG_N_SETS (regno) == 1)
10353 && reg_last_set_label[j] > tick))
10356 *loc = gen_rtx (CLOBBER, GET_MODE (x), const0_rtx);
10362 /* If this is a memory reference, make sure that there were
10363 no stores after it that might have clobbered the value. We don't
10364 have alias info, so we assume any store invalidates it. */
10365 else if (GET_CODE (x) == MEM && ! RTX_UNCHANGING_P (x)
10366 && INSN_CUID (insn) <= mem_last_set)
10369 *loc = gen_rtx (CLOBBER, GET_MODE (x), const0_rtx);
10373 for (i = 0; i < len; i++)
10375 && get_last_value_validate (&XEXP (x, i), insn, tick, replace) == 0)
10376 /* Don't bother with these. They shouldn't occur anyway. */
10380 /* If we haven't found a reason for it to be invalid, it is valid. */
10384 /* Get the last value assigned to X, if known. Some registers
10385 in the value may be replaced with (clobber (const_int 0)) if their value
10386 is known longer known reliably. */
10395 /* If this is a non-paradoxical SUBREG, get the value of its operand and
10396 then convert it to the desired mode. If this is a paradoxical SUBREG,
10397 we cannot predict what values the "extra" bits might have. */
10398 if (GET_CODE (x) == SUBREG
10399 && subreg_lowpart_p (x)
10400 && (GET_MODE_SIZE (GET_MODE (x))
10401 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
10402 && (value = get_last_value (SUBREG_REG (x))) != 0)
10403 return gen_lowpart_for_combine (GET_MODE (x), value);
10405 if (GET_CODE (x) != REG)
10409 value = reg_last_set_value[regno];
10411 /* If we don't have a value or if it isn't for this basic block,
10415 || (REG_N_SETS (regno) != 1
10416 && reg_last_set_label[regno] != label_tick))
10419 /* If the value was set in a later insn than the ones we are processing,
10420 we can't use it even if the register was only set once, but make a quick
10421 check to see if the previous insn set it to something. This is commonly
10422 the case when the same pseudo is used by repeated insns.
10424 This does not work if there exists an instruction which is temporarily
10425 not on the insn chain. */
10427 if (INSN_CUID (reg_last_set[regno]) >= subst_low_cuid)
10431 /* We can not do anything useful in this case, because there is
10432 an instruction which is not on the insn chain. */
10433 if (subst_prev_insn)
10436 /* Skip over USE insns. They are not useful here, and they may have
10437 been made by combine, in which case they do not have a INSN_CUID
10438 value. We can't use prev_real_insn, because that would incorrectly
10439 take us backwards across labels. Skip over BARRIERs also, since
10440 they could have been made by combine. If we see one, we must be
10441 optimizing dead code, so it doesn't matter what we do. */
10442 for (insn = prev_nonnote_insn (subst_insn);
10443 insn && ((GET_CODE (insn) == INSN
10444 && GET_CODE (PATTERN (insn)) == USE)
10445 || GET_CODE (insn) == BARRIER
10446 || INSN_CUID (insn) >= subst_low_cuid);
10447 insn = prev_nonnote_insn (insn))
10451 && (set = single_set (insn)) != 0
10452 && rtx_equal_p (SET_DEST (set), x))
10454 value = SET_SRC (set);
10456 /* Make sure that VALUE doesn't reference X. Replace any
10457 explicit references with a CLOBBER. If there are any remaining
10458 references (rare), don't use the value. */
10460 if (reg_mentioned_p (x, value))
10461 value = replace_rtx (copy_rtx (value), x,
10462 gen_rtx (CLOBBER, GET_MODE (x), const0_rtx));
10464 if (reg_overlap_mentioned_p (x, value))
10471 /* If the value has all its registers valid, return it. */
10472 if (get_last_value_validate (&value, reg_last_set[regno],
10473 reg_last_set_label[regno], 0))
10476 /* Otherwise, make a copy and replace any invalid register with
10477 (clobber (const_int 0)). If that fails for some reason, return 0. */
10479 value = copy_rtx (value);
10480 if (get_last_value_validate (&value, reg_last_set[regno],
10481 reg_last_set_label[regno], 1))
10487 /* Return nonzero if expression X refers to a REG or to memory
10488 that is set in an instruction more recent than FROM_CUID. */
10491 use_crosses_set_p (x, from_cuid)
10495 register char *fmt;
10497 register enum rtx_code code = GET_CODE (x);
10501 register int regno = REGNO (x);
10502 int endreg = regno + (regno < FIRST_PSEUDO_REGISTER
10503 ? HARD_REGNO_NREGS (regno, GET_MODE (x)) : 1);
10505 #ifdef PUSH_ROUNDING
10506 /* Don't allow uses of the stack pointer to be moved,
10507 because we don't know whether the move crosses a push insn. */
10508 if (regno == STACK_POINTER_REGNUM)
10511 for (;regno < endreg; regno++)
10512 if (reg_last_set[regno]
10513 && INSN_CUID (reg_last_set[regno]) > from_cuid)
10518 if (code == MEM && mem_last_set > from_cuid)
10521 fmt = GET_RTX_FORMAT (code);
10523 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
10528 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
10529 if (use_crosses_set_p (XVECEXP (x, i, j), from_cuid))
10532 else if (fmt[i] == 'e'
10533 && use_crosses_set_p (XEXP (x, i), from_cuid))
10539 /* Define three variables used for communication between the following
10542 static int reg_dead_regno, reg_dead_endregno;
10543 static int reg_dead_flag;
10545 /* Function called via note_stores from reg_dead_at_p.
10547 If DEST is within [reg_dead_regno, reg_dead_endregno), set
10548 reg_dead_flag to 1 if X is a CLOBBER and to -1 it is a SET. */
10551 reg_dead_at_p_1 (dest, x)
10555 int regno, endregno;
10557 if (GET_CODE (dest) != REG)
10560 regno = REGNO (dest);
10561 endregno = regno + (regno < FIRST_PSEUDO_REGISTER
10562 ? HARD_REGNO_NREGS (regno, GET_MODE (dest)) : 1);
10564 if (reg_dead_endregno > regno && reg_dead_regno < endregno)
10565 reg_dead_flag = (GET_CODE (x) == CLOBBER) ? 1 : -1;
10568 /* Return non-zero if REG is known to be dead at INSN.
10570 We scan backwards from INSN. If we hit a REG_DEAD note or a CLOBBER
10571 referencing REG, it is dead. If we hit a SET referencing REG, it is
10572 live. Otherwise, see if it is live or dead at the start of the basic
10573 block we are in. Hard regs marked as being live in NEWPAT_USED_REGS
10574 must be assumed to be always live. */
10577 reg_dead_at_p (reg, insn)
10583 /* Set variables for reg_dead_at_p_1. */
10584 reg_dead_regno = REGNO (reg);
10585 reg_dead_endregno = reg_dead_regno + (reg_dead_regno < FIRST_PSEUDO_REGISTER
10586 ? HARD_REGNO_NREGS (reg_dead_regno,
10592 /* Check that reg isn't mentioned in NEWPAT_USED_REGS. */
10593 if (reg_dead_regno < FIRST_PSEUDO_REGISTER)
10595 for (i = reg_dead_regno; i < reg_dead_endregno; i++)
10596 if (TEST_HARD_REG_BIT (newpat_used_regs, i))
10600 /* Scan backwards until we find a REG_DEAD note, SET, CLOBBER, label, or
10601 beginning of function. */
10602 for (; insn && GET_CODE (insn) != CODE_LABEL && GET_CODE (insn) != BARRIER;
10603 insn = prev_nonnote_insn (insn))
10605 note_stores (PATTERN (insn), reg_dead_at_p_1);
10607 return reg_dead_flag == 1 ? 1 : 0;
10609 if (find_regno_note (insn, REG_DEAD, reg_dead_regno))
10613 /* Get the basic block number that we were in. */
10618 for (block = 0; block < n_basic_blocks; block++)
10619 if (insn == basic_block_head[block])
10622 if (block == n_basic_blocks)
10626 for (i = reg_dead_regno; i < reg_dead_endregno; i++)
10627 if (REGNO_REG_SET_P (basic_block_live_at_start[block], i))
10633 /* Note hard registers in X that are used. This code is similar to
10634 that in flow.c, but much simpler since we don't care about pseudos. */
10637 mark_used_regs_combine (x)
10640 register RTX_CODE code = GET_CODE (x);
10641 register int regno;
10653 case ADDR_DIFF_VEC:
10656 /* CC0 must die in the insn after it is set, so we don't need to take
10657 special note of it here. */
10663 /* If we are clobbering a MEM, mark any hard registers inside the
10664 address as used. */
10665 if (GET_CODE (XEXP (x, 0)) == MEM)
10666 mark_used_regs_combine (XEXP (XEXP (x, 0), 0));
10671 /* A hard reg in a wide mode may really be multiple registers.
10672 If so, mark all of them just like the first. */
10673 if (regno < FIRST_PSEUDO_REGISTER)
10675 /* None of this applies to the stack, frame or arg pointers */
10676 if (regno == STACK_POINTER_REGNUM
10677 #if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM
10678 || regno == HARD_FRAME_POINTER_REGNUM
10680 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
10681 || (regno == ARG_POINTER_REGNUM && fixed_regs[regno])
10683 || regno == FRAME_POINTER_REGNUM)
10686 i = HARD_REGNO_NREGS (regno, GET_MODE (x));
10688 SET_HARD_REG_BIT (newpat_used_regs, regno + i);
10694 /* If setting a MEM, or a SUBREG of a MEM, then note any hard regs in
10696 register rtx testreg = SET_DEST (x);
10698 while (GET_CODE (testreg) == SUBREG
10699 || GET_CODE (testreg) == ZERO_EXTRACT
10700 || GET_CODE (testreg) == SIGN_EXTRACT
10701 || GET_CODE (testreg) == STRICT_LOW_PART)
10702 testreg = XEXP (testreg, 0);
10704 if (GET_CODE (testreg) == MEM)
10705 mark_used_regs_combine (XEXP (testreg, 0));
10707 mark_used_regs_combine (SET_SRC (x));
10712 /* Recursively scan the operands of this expression. */
10715 register char *fmt = GET_RTX_FORMAT (code);
10717 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
10720 mark_used_regs_combine (XEXP (x, i));
10721 else if (fmt[i] == 'E')
10725 for (j = 0; j < XVECLEN (x, i); j++)
10726 mark_used_regs_combine (XVECEXP (x, i, j));
10733 /* Remove register number REGNO from the dead registers list of INSN.
10735 Return the note used to record the death, if there was one. */
10738 remove_death (regno, insn)
10742 register rtx note = find_regno_note (insn, REG_DEAD, regno);
10746 REG_N_DEATHS (regno)--;
10747 remove_note (insn, note);
10753 /* For each register (hardware or pseudo) used within expression X, if its
10754 death is in an instruction with cuid between FROM_CUID (inclusive) and
10755 TO_INSN (exclusive), put a REG_DEAD note for that register in the
10756 list headed by PNOTES.
10758 That said, don't move registers killed by maybe_kill_insn.
10760 This is done when X is being merged by combination into TO_INSN. These
10761 notes will then be distributed as needed. */
10764 move_deaths (x, maybe_kill_insn, from_cuid, to_insn, pnotes)
10766 rtx maybe_kill_insn;
10771 register char *fmt;
10772 register int len, i;
10773 register enum rtx_code code = GET_CODE (x);
10777 register int regno = REGNO (x);
10778 register rtx where_dead = reg_last_death[regno];
10779 register rtx before_dead, after_dead;
10781 /* Don't move the register if it gets killed in between from and to */
10782 if (maybe_kill_insn && reg_set_p (x, maybe_kill_insn)
10783 && !reg_referenced_p (x, maybe_kill_insn))
10786 /* WHERE_DEAD could be a USE insn made by combine, so first we
10787 make sure that we have insns with valid INSN_CUID values. */
10788 before_dead = where_dead;
10789 while (before_dead && INSN_UID (before_dead) > max_uid_cuid)
10790 before_dead = PREV_INSN (before_dead);
10791 after_dead = where_dead;
10792 while (after_dead && INSN_UID (after_dead) > max_uid_cuid)
10793 after_dead = NEXT_INSN (after_dead);
10795 if (before_dead && after_dead
10796 && INSN_CUID (before_dead) >= from_cuid
10797 && (INSN_CUID (after_dead) < INSN_CUID (to_insn)
10798 || (where_dead != after_dead
10799 && INSN_CUID (after_dead) == INSN_CUID (to_insn))))
10801 rtx note = remove_death (regno, where_dead);
10803 /* It is possible for the call above to return 0. This can occur
10804 when reg_last_death points to I2 or I1 that we combined with.
10805 In that case make a new note.
10807 We must also check for the case where X is a hard register
10808 and NOTE is a death note for a range of hard registers
10809 including X. In that case, we must put REG_DEAD notes for
10810 the remaining registers in place of NOTE. */
10812 if (note != 0 && regno < FIRST_PSEUDO_REGISTER
10813 && (GET_MODE_SIZE (GET_MODE (XEXP (note, 0)))
10814 > GET_MODE_SIZE (GET_MODE (x))))
10816 int deadregno = REGNO (XEXP (note, 0));
10818 = (deadregno + HARD_REGNO_NREGS (deadregno,
10819 GET_MODE (XEXP (note, 0))));
10820 int ourend = regno + HARD_REGNO_NREGS (regno, GET_MODE (x));
10823 for (i = deadregno; i < deadend; i++)
10824 if (i < regno || i >= ourend)
10825 REG_NOTES (where_dead)
10826 = gen_rtx (EXPR_LIST, REG_DEAD,
10827 gen_rtx (REG, reg_raw_mode[i], i),
10828 REG_NOTES (where_dead));
10830 /* If we didn't find any note, or if we found a REG_DEAD note that
10831 covers only part of the given reg, and we have a multi-reg hard
10832 register, then to be safe we must check for REG_DEAD notes
10833 for each register other than the first. They could have
10834 their own REG_DEAD notes lying around. */
10835 else if ((note == 0
10837 && (GET_MODE_SIZE (GET_MODE (XEXP (note, 0)))
10838 < GET_MODE_SIZE (GET_MODE (x)))))
10839 && regno < FIRST_PSEUDO_REGISTER
10840 && HARD_REGNO_NREGS (regno, GET_MODE (x)) > 1)
10842 int ourend = regno + HARD_REGNO_NREGS (regno, GET_MODE (x));
10847 offset = HARD_REGNO_NREGS (regno, GET_MODE (XEXP (note, 0)));
10851 for (i = regno + offset; i < ourend; i++)
10852 move_deaths (gen_rtx (REG, reg_raw_mode[i], i),
10853 maybe_kill_insn, from_cuid, to_insn, &oldnotes);
10856 if (note != 0 && GET_MODE (XEXP (note, 0)) == GET_MODE (x))
10858 XEXP (note, 1) = *pnotes;
10862 *pnotes = gen_rtx (EXPR_LIST, REG_DEAD, x, *pnotes);
10864 REG_N_DEATHS (regno)++;
10870 else if (GET_CODE (x) == SET)
10872 rtx dest = SET_DEST (x);
10874 move_deaths (SET_SRC (x), maybe_kill_insn, from_cuid, to_insn, pnotes);
10876 /* In the case of a ZERO_EXTRACT, a STRICT_LOW_PART, or a SUBREG
10877 that accesses one word of a multi-word item, some
10878 piece of everything register in the expression is used by
10879 this insn, so remove any old death. */
10881 if (GET_CODE (dest) == ZERO_EXTRACT
10882 || GET_CODE (dest) == STRICT_LOW_PART
10883 || (GET_CODE (dest) == SUBREG
10884 && (((GET_MODE_SIZE (GET_MODE (dest))
10885 + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
10886 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (dest)))
10887 + UNITS_PER_WORD - 1) / UNITS_PER_WORD))))
10889 move_deaths (dest, maybe_kill_insn, from_cuid, to_insn, pnotes);
10893 /* If this is some other SUBREG, we know it replaces the entire
10894 value, so use that as the destination. */
10895 if (GET_CODE (dest) == SUBREG)
10896 dest = SUBREG_REG (dest);
10898 /* If this is a MEM, adjust deaths of anything used in the address.
10899 For a REG (the only other possibility), the entire value is
10900 being replaced so the old value is not used in this insn. */
10902 if (GET_CODE (dest) == MEM)
10903 move_deaths (XEXP (dest, 0), maybe_kill_insn, from_cuid,
10908 else if (GET_CODE (x) == CLOBBER)
10911 len = GET_RTX_LENGTH (code);
10912 fmt = GET_RTX_FORMAT (code);
10914 for (i = 0; i < len; i++)
10919 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
10920 move_deaths (XVECEXP (x, i, j), maybe_kill_insn, from_cuid,
10923 else if (fmt[i] == 'e')
10924 move_deaths (XEXP (x, i), maybe_kill_insn, from_cuid, to_insn, pnotes);
10928 /* Return 1 if X is the target of a bit-field assignment in BODY, the
10929 pattern of an insn. X must be a REG. */
10932 reg_bitfield_target_p (x, body)
10938 if (GET_CODE (body) == SET)
10940 rtx dest = SET_DEST (body);
10942 int regno, tregno, endregno, endtregno;
10944 if (GET_CODE (dest) == ZERO_EXTRACT)
10945 target = XEXP (dest, 0);
10946 else if (GET_CODE (dest) == STRICT_LOW_PART)
10947 target = SUBREG_REG (XEXP (dest, 0));
10951 if (GET_CODE (target) == SUBREG)
10952 target = SUBREG_REG (target);
10954 if (GET_CODE (target) != REG)
10957 tregno = REGNO (target), regno = REGNO (x);
10958 if (tregno >= FIRST_PSEUDO_REGISTER || regno >= FIRST_PSEUDO_REGISTER)
10959 return target == x;
10961 endtregno = tregno + HARD_REGNO_NREGS (tregno, GET_MODE (target));
10962 endregno = regno + HARD_REGNO_NREGS (regno, GET_MODE (x));
10964 return endregno > tregno && regno < endtregno;
10967 else if (GET_CODE (body) == PARALLEL)
10968 for (i = XVECLEN (body, 0) - 1; i >= 0; i--)
10969 if (reg_bitfield_target_p (x, XVECEXP (body, 0, i)))
10975 /* Given a chain of REG_NOTES originally from FROM_INSN, try to place them
10976 as appropriate. I3 and I2 are the insns resulting from the combination
10977 insns including FROM (I2 may be zero).
10979 ELIM_I2 and ELIM_I1 are either zero or registers that we know will
10980 not need REG_DEAD notes because they are being substituted for. This
10981 saves searching in the most common cases.
10983 Each note in the list is either ignored or placed on some insns, depending
10984 on the type of note. */
10987 distribute_notes (notes, from_insn, i3, i2, elim_i2, elim_i1)
10991 rtx elim_i2, elim_i1;
10993 rtx note, next_note;
10996 for (note = notes; note; note = next_note)
10998 rtx place = 0, place2 = 0;
11000 /* If this NOTE references a pseudo register, ensure it references
11001 the latest copy of that register. */
11002 if (XEXP (note, 0) && GET_CODE (XEXP (note, 0)) == REG
11003 && REGNO (XEXP (note, 0)) >= FIRST_PSEUDO_REGISTER)
11004 XEXP (note, 0) = regno_reg_rtx[REGNO (XEXP (note, 0))];
11006 next_note = XEXP (note, 1);
11007 switch (REG_NOTE_KIND (note))
11010 case REG_EXEC_COUNT:
11011 /* Doesn't matter much where we put this, as long as it's somewhere.
11012 It is preferable to keep these notes on branches, which is most
11013 likely to be i3. */
11018 /* Any clobbers for i3 may still exist, and so we must process
11019 REG_UNUSED notes from that insn.
11021 Any clobbers from i2 or i1 can only exist if they were added by
11022 recog_for_combine. In that case, recog_for_combine created the
11023 necessary REG_UNUSED notes. Trying to keep any original
11024 REG_UNUSED notes from these insns can cause incorrect output
11025 if it is for the same register as the original i3 dest.
11026 In that case, we will notice that the register is set in i3,
11027 and then add a REG_UNUSED note for the destination of i3, which
11028 is wrong. However, it is possible to have REG_UNUSED notes from
11029 i2 or i1 for register which were both used and clobbered, so
11030 we keep notes from i2 or i1 if they will turn into REG_DEAD
11033 /* If this register is set or clobbered in I3, put the note there
11034 unless there is one already. */
11035 if (reg_set_p (XEXP (note, 0), PATTERN (i3)))
11037 if (from_insn != i3)
11040 if (! (GET_CODE (XEXP (note, 0)) == REG
11041 ? find_regno_note (i3, REG_UNUSED, REGNO (XEXP (note, 0)))
11042 : find_reg_note (i3, REG_UNUSED, XEXP (note, 0))))
11045 /* Otherwise, if this register is used by I3, then this register
11046 now dies here, so we must put a REG_DEAD note here unless there
11048 else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3))
11049 && ! (GET_CODE (XEXP (note, 0)) == REG
11050 ? find_regno_note (i3, REG_DEAD, REGNO (XEXP (note, 0)))
11051 : find_reg_note (i3, REG_DEAD, XEXP (note, 0))))
11053 PUT_REG_NOTE_KIND (note, REG_DEAD);
11061 /* These notes say something about results of an insn. We can
11062 only support them if they used to be on I3 in which case they
11063 remain on I3. Otherwise they are ignored.
11065 If the note refers to an expression that is not a constant, we
11066 must also ignore the note since we cannot tell whether the
11067 equivalence is still true. It might be possible to do
11068 slightly better than this (we only have a problem if I2DEST
11069 or I1DEST is present in the expression), but it doesn't
11070 seem worth the trouble. */
11072 if (from_insn == i3
11073 && (XEXP (note, 0) == 0 || CONSTANT_P (XEXP (note, 0))))
11078 case REG_NO_CONFLICT:
11080 /* These notes say something about how a register is used. They must
11081 be present on any use of the register in I2 or I3. */
11082 if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3)))
11085 if (i2 && reg_mentioned_p (XEXP (note, 0), PATTERN (i2)))
11095 /* It is too much trouble to try to see if this note is still
11096 correct in all situations. It is better to simply delete it. */
11100 /* If the insn previously containing this note still exists,
11101 put it back where it was. Otherwise move it to the previous
11102 insn. Adjust the corresponding REG_LIBCALL note. */
11103 if (GET_CODE (from_insn) != NOTE)
11107 tem = find_reg_note (XEXP (note, 0), REG_LIBCALL, NULL_RTX);
11108 place = prev_real_insn (from_insn);
11110 XEXP (tem, 0) = place;
11115 /* This is handled similarly to REG_RETVAL. */
11116 if (GET_CODE (from_insn) != NOTE)
11120 tem = find_reg_note (XEXP (note, 0), REG_RETVAL, NULL_RTX);
11121 place = next_real_insn (from_insn);
11123 XEXP (tem, 0) = place;
11128 /* If the register is used as an input in I3, it dies there.
11129 Similarly for I2, if it is non-zero and adjacent to I3.
11131 If the register is not used as an input in either I3 or I2
11132 and it is not one of the registers we were supposed to eliminate,
11133 there are two possibilities. We might have a non-adjacent I2
11134 or we might have somehow eliminated an additional register
11135 from a computation. For example, we might have had A & B where
11136 we discover that B will always be zero. In this case we will
11137 eliminate the reference to A.
11139 In both cases, we must search to see if we can find a previous
11140 use of A and put the death note there. */
11143 && GET_CODE (from_insn) == CALL_INSN
11144 && find_reg_fusage (from_insn, USE, XEXP (note, 0)))
11146 else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3)))
11148 else if (i2 != 0 && next_nonnote_insn (i2) == i3
11149 && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
11152 if (XEXP (note, 0) == elim_i2 || XEXP (note, 0) == elim_i1)
11155 /* If the register is used in both I2 and I3 and it dies in I3,
11156 we might have added another reference to it. If reg_n_refs
11157 was 2, bump it to 3. This has to be correct since the
11158 register must have been set somewhere. The reason this is
11159 done is because local-alloc.c treats 2 references as a
11162 if (place == i3 && i2 != 0 && GET_CODE (XEXP (note, 0)) == REG
11163 && REG_N_REFS (REGNO (XEXP (note, 0)))== 2
11164 && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
11165 REG_N_REFS (REGNO (XEXP (note, 0))) = 3;
11169 for (tem = prev_nonnote_insn (i3);
11171 && (GET_CODE (tem) == INSN || GET_CODE (tem) == CALL_INSN);
11172 tem = prev_nonnote_insn (tem))
11174 /* If the register is being set at TEM, see if that is all
11175 TEM is doing. If so, delete TEM. Otherwise, make this
11176 into a REG_UNUSED note instead. */
11177 if (reg_set_p (XEXP (note, 0), PATTERN (tem)))
11179 rtx set = single_set (tem);
11181 /* Verify that it was the set, and not a clobber that
11182 modified the register. */
11184 if (set != 0 && ! side_effects_p (SET_SRC (set))
11185 && (rtx_equal_p (XEXP (note, 0), SET_DEST (set))
11186 || (GET_CODE (SET_DEST (set)) == SUBREG
11187 && rtx_equal_p (XEXP (note, 0),
11188 XEXP (SET_DEST (set), 0)))))
11190 /* Move the notes and links of TEM elsewhere.
11191 This might delete other dead insns recursively.
11192 First set the pattern to something that won't use
11195 PATTERN (tem) = pc_rtx;
11197 distribute_notes (REG_NOTES (tem), tem, tem,
11198 NULL_RTX, NULL_RTX, NULL_RTX);
11199 distribute_links (LOG_LINKS (tem));
11201 PUT_CODE (tem, NOTE);
11202 NOTE_LINE_NUMBER (tem) = NOTE_INSN_DELETED;
11203 NOTE_SOURCE_FILE (tem) = 0;
11207 PUT_REG_NOTE_KIND (note, REG_UNUSED);
11209 /* If there isn't already a REG_UNUSED note, put one
11211 if (! find_regno_note (tem, REG_UNUSED,
11212 REGNO (XEXP (note, 0))))
11217 else if (reg_referenced_p (XEXP (note, 0), PATTERN (tem))
11218 || (GET_CODE (tem) == CALL_INSN
11219 && find_reg_fusage (tem, USE, XEXP (note, 0))))
11223 /* If we are doing a 3->2 combination, and we have a
11224 register which formerly died in i3 and was not used
11225 by i2, which now no longer dies in i3 and is used in
11226 i2 but does not die in i2, and place is between i2
11227 and i3, then we may need to move a link from place to
11229 if (i2 && INSN_UID (place) <= max_uid_cuid
11230 && INSN_CUID (place) > INSN_CUID (i2)
11231 && from_insn && INSN_CUID (from_insn) > INSN_CUID (i2)
11232 && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
11234 rtx links = LOG_LINKS (place);
11235 LOG_LINKS (place) = 0;
11236 distribute_links (links);
11242 /* If we haven't found an insn for the death note and it
11243 is still a REG_DEAD note, but we have hit a CODE_LABEL,
11244 insert a USE insn for the register at that label and
11245 put the death node there. This prevents problems with
11246 call-state tracking in caller-save.c. */
11247 if (REG_NOTE_KIND (note) == REG_DEAD && place == 0 && tem != 0)
11250 = emit_insn_after (gen_rtx (USE, VOIDmode, XEXP (note, 0)),
11253 /* If this insn was emitted between blocks, then update
11254 basic_block_head of the current block to include it. */
11255 if (basic_block_end[this_basic_block - 1] == tem)
11256 basic_block_head[this_basic_block] = place;
11260 /* If the register is set or already dead at PLACE, we needn't do
11261 anything with this note if it is still a REG_DEAD note.
11263 Note that we cannot use just `dead_or_set_p' here since we can
11264 convert an assignment to a register into a bit-field assignment.
11265 Therefore, we must also omit the note if the register is the
11266 target of a bitfield assignment. */
11268 if (place && REG_NOTE_KIND (note) == REG_DEAD)
11270 int regno = REGNO (XEXP (note, 0));
11272 if (dead_or_set_p (place, XEXP (note, 0))
11273 || reg_bitfield_target_p (XEXP (note, 0), PATTERN (place)))
11275 /* Unless the register previously died in PLACE, clear
11276 reg_last_death. [I no longer understand why this is
11278 if (reg_last_death[regno] != place)
11279 reg_last_death[regno] = 0;
11283 reg_last_death[regno] = place;
11285 /* If this is a death note for a hard reg that is occupying
11286 multiple registers, ensure that we are still using all
11287 parts of the object. If we find a piece of the object
11288 that is unused, we must add a USE for that piece before
11289 PLACE and put the appropriate REG_DEAD note on it.
11291 An alternative would be to put a REG_UNUSED for the pieces
11292 on the insn that set the register, but that can't be done if
11293 it is not in the same block. It is simpler, though less
11294 efficient, to add the USE insns. */
11296 if (place && regno < FIRST_PSEUDO_REGISTER
11297 && HARD_REGNO_NREGS (regno, GET_MODE (XEXP (note, 0))) > 1)
11300 = regno + HARD_REGNO_NREGS (regno,
11301 GET_MODE (XEXP (note, 0)));
11305 for (i = regno; i < endregno; i++)
11306 if (! refers_to_regno_p (i, i + 1, PATTERN (place), 0)
11307 && ! find_regno_fusage (place, USE, i))
11309 rtx piece = gen_rtx (REG, reg_raw_mode[i], i);
11312 /* See if we already placed a USE note for this
11313 register in front of PLACE. */
11315 GET_CODE (PREV_INSN (p)) == INSN
11316 && GET_CODE (PATTERN (PREV_INSN (p))) == USE;
11318 if (rtx_equal_p (piece,
11319 XEXP (PATTERN (PREV_INSN (p)), 0)))
11328 = emit_insn_before (gen_rtx (USE, VOIDmode,
11331 REG_NOTES (use_insn)
11332 = gen_rtx (EXPR_LIST, REG_DEAD, piece,
11333 REG_NOTES (use_insn));
11339 /* Check for the case where the register dying partially
11340 overlaps the register set by this insn. */
11342 for (i = regno; i < endregno; i++)
11343 if (dead_or_set_regno_p (place, i))
11351 /* Put only REG_DEAD notes for pieces that are
11352 still used and that are not already dead or set. */
11354 for (i = regno; i < endregno; i++)
11356 rtx piece = gen_rtx (REG, reg_raw_mode[i], i);
11358 if ((reg_referenced_p (piece, PATTERN (place))
11359 || (GET_CODE (place) == CALL_INSN
11360 && find_reg_fusage (place, USE, piece)))
11361 && ! dead_or_set_p (place, piece)
11362 && ! reg_bitfield_target_p (piece,
11364 REG_NOTES (place) = gen_rtx (EXPR_LIST, REG_DEAD,
11366 REG_NOTES (place));
11376 /* Any other notes should not be present at this point in the
11383 XEXP (note, 1) = REG_NOTES (place);
11384 REG_NOTES (place) = note;
11386 else if ((REG_NOTE_KIND (note) == REG_DEAD
11387 || REG_NOTE_KIND (note) == REG_UNUSED)
11388 && GET_CODE (XEXP (note, 0)) == REG)
11389 REG_N_DEATHS (REGNO (XEXP (note, 0)))--;
11393 if ((REG_NOTE_KIND (note) == REG_DEAD
11394 || REG_NOTE_KIND (note) == REG_UNUSED)
11395 && GET_CODE (XEXP (note, 0)) == REG)
11396 REG_N_DEATHS (REGNO (XEXP (note, 0)))++;
11398 REG_NOTES (place2) = gen_rtx (GET_CODE (note), REG_NOTE_KIND (note),
11399 XEXP (note, 0), REG_NOTES (place2));
11404 /* Similarly to above, distribute the LOG_LINKS that used to be present on
11405 I3, I2, and I1 to new locations. This is also called in one case to
11406 add a link pointing at I3 when I3's destination is changed. */
11409 distribute_links (links)
11412 rtx link, next_link;
11414 for (link = links; link; link = next_link)
11420 next_link = XEXP (link, 1);
11422 /* If the insn that this link points to is a NOTE or isn't a single
11423 set, ignore it. In the latter case, it isn't clear what we
11424 can do other than ignore the link, since we can't tell which
11425 register it was for. Such links wouldn't be used by combine
11428 It is not possible for the destination of the target of the link to
11429 have been changed by combine. The only potential of this is if we
11430 replace I3, I2, and I1 by I3 and I2. But in that case the
11431 destination of I2 also remains unchanged. */
11433 if (GET_CODE (XEXP (link, 0)) == NOTE
11434 || (set = single_set (XEXP (link, 0))) == 0)
11437 reg = SET_DEST (set);
11438 while (GET_CODE (reg) == SUBREG || GET_CODE (reg) == ZERO_EXTRACT
11439 || GET_CODE (reg) == SIGN_EXTRACT
11440 || GET_CODE (reg) == STRICT_LOW_PART)
11441 reg = XEXP (reg, 0);
11443 /* A LOG_LINK is defined as being placed on the first insn that uses
11444 a register and points to the insn that sets the register. Start
11445 searching at the next insn after the target of the link and stop
11446 when we reach a set of the register or the end of the basic block.
11448 Note that this correctly handles the link that used to point from
11449 I3 to I2. Also note that not much searching is typically done here
11450 since most links don't point very far away. */
11452 for (insn = NEXT_INSN (XEXP (link, 0));
11453 (insn && (this_basic_block == n_basic_blocks - 1
11454 || basic_block_head[this_basic_block + 1] != insn));
11455 insn = NEXT_INSN (insn))
11456 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i'
11457 && reg_overlap_mentioned_p (reg, PATTERN (insn)))
11459 if (reg_referenced_p (reg, PATTERN (insn)))
11463 else if (GET_CODE (insn) == CALL_INSN
11464 && find_reg_fusage (insn, USE, reg))
11470 /* If we found a place to put the link, place it there unless there
11471 is already a link to the same insn as LINK at that point. */
11477 for (link2 = LOG_LINKS (place); link2; link2 = XEXP (link2, 1))
11478 if (XEXP (link2, 0) == XEXP (link, 0))
11483 XEXP (link, 1) = LOG_LINKS (place);
11484 LOG_LINKS (place) = link;
11486 /* Set added_links_insn to the earliest insn we added a
11488 if (added_links_insn == 0
11489 || INSN_CUID (added_links_insn) > INSN_CUID (place))
11490 added_links_insn = place;
11496 /* Compute INSN_CUID for INSN, which is an insn made by combine. */
11502 while (insn != 0 && INSN_UID (insn) > max_uid_cuid
11503 && GET_CODE (insn) == INSN && GET_CODE (PATTERN (insn)) == USE)
11504 insn = NEXT_INSN (insn);
11506 if (INSN_UID (insn) > max_uid_cuid)
11509 return INSN_CUID (insn);
11513 dump_combine_stats (file)
11518 ";; Combiner statistics: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n\n",
11519 combine_attempts, combine_merges, combine_extras, combine_successes);
11523 dump_combine_total_stats (file)
11528 "\n;; Combiner totals: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n",
11529 total_attempts, total_merges, total_extras, total_successes);
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