1 /* Optimize by combining instructions for GNU compiler.
2 Copyright (C) 1987, 1988, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008
4 Free Software Foundation, Inc.
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify it under
9 the terms of the GNU General Public License as published by the Free
10 Software Foundation; either version 3, or (at your option) any later
13 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
14 WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
22 /* This module is essentially the "combiner" phase of the U. of Arizona
23 Portable Optimizer, but redone to work on our list-structured
24 representation for RTL instead of their string representation.
26 The LOG_LINKS of each insn identify the most recent assignment
27 to each REG used in the insn. It is a list of previous insns,
28 each of which contains a SET for a REG that is used in this insn
29 and not used or set in between. LOG_LINKs never cross basic blocks.
30 They were set up by the preceding pass (lifetime analysis).
32 We try to combine each pair of insns joined by a logical link.
33 We also try to combine triples of insns A, B and C when
34 C has a link back to B and B has a link back to A.
36 LOG_LINKS does not have links for use of the CC0. They don't
37 need to, because the insn that sets the CC0 is always immediately
38 before the insn that tests it. So we always regard a branch
39 insn as having a logical link to the preceding insn. The same is true
40 for an insn explicitly using CC0.
42 We check (with use_crosses_set_p) to avoid combining in such a way
43 as to move a computation to a place where its value would be different.
45 Combination is done by mathematically substituting the previous
46 insn(s) values for the regs they set into the expressions in
47 the later insns that refer to these regs. If the result is a valid insn
48 for our target machine, according to the machine description,
49 we install it, delete the earlier insns, and update the data flow
50 information (LOG_LINKS and REG_NOTES) for what we did.
52 There are a few exceptions where the dataflow information isn't
53 completely updated (however this is only a local issue since it is
54 regenerated before the next pass that uses it):
56 - reg_live_length is not updated
57 - reg_n_refs is not adjusted in the rare case when a register is
58 no longer required in a computation
59 - there are extremely rare cases (see distribute_notes) when a
61 - a LOG_LINKS entry that refers to an insn with multiple SETs may be
62 removed because there is no way to know which register it was
65 To simplify substitution, we combine only when the earlier insn(s)
66 consist of only a single assignment. To simplify updating afterward,
67 we never combine when a subroutine call appears in the middle.
69 Since we do not represent assignments to CC0 explicitly except when that
70 is all an insn does, there is no LOG_LINKS entry in an insn that uses
71 the condition code for the insn that set the condition code.
72 Fortunately, these two insns must be consecutive.
73 Therefore, every JUMP_INSN is taken to have an implicit logical link
74 to the preceding insn. This is not quite right, since non-jumps can
75 also use the condition code; but in practice such insns would not
80 #include "coretypes.h"
87 #include "hard-reg-set.h"
88 #include "basic-block.h"
89 #include "insn-config.h"
91 /* Include expr.h after insn-config.h so we get HAVE_conditional_move. */
93 #include "insn-attr.h"
99 #include "insn-codes.h"
100 #include "rtlhooks-def.h"
101 /* Include output.h for dump_file. */
105 #include "tree-pass.h"
109 /* Number of attempts to combine instructions in this function. */
111 static int combine_attempts;
113 /* Number of attempts that got as far as substitution in this function. */
115 static int combine_merges;
117 /* Number of instructions combined with added SETs in this function. */
119 static int combine_extras;
121 /* Number of instructions combined in this function. */
123 static int combine_successes;
125 /* Totals over entire compilation. */
127 static int total_attempts, total_merges, total_extras, total_successes;
129 /* combine_instructions may try to replace the right hand side of the
130 second instruction with the value of an associated REG_EQUAL note
131 before throwing it at try_combine. That is problematic when there
132 is a REG_DEAD note for a register used in the old right hand side
133 and can cause distribute_notes to do wrong things. This is the
134 second instruction if it has been so modified, null otherwise. */
138 /* When I2MOD is nonnull, this is a copy of the old right hand side. */
140 static rtx i2mod_old_rhs;
142 /* When I2MOD is nonnull, this is a copy of the new right hand side. */
144 static rtx i2mod_new_rhs;
146 typedef struct reg_stat_struct {
147 /* Record last point of death of (hard or pseudo) register n. */
150 /* Record last point of modification of (hard or pseudo) register n. */
153 /* The next group of fields allows the recording of the last value assigned
154 to (hard or pseudo) register n. We use this information to see if an
155 operation being processed is redundant given a prior operation performed
156 on the register. For example, an `and' with a constant is redundant if
157 all the zero bits are already known to be turned off.
159 We use an approach similar to that used by cse, but change it in the
162 (1) We do not want to reinitialize at each label.
163 (2) It is useful, but not critical, to know the actual value assigned
164 to a register. Often just its form is helpful.
166 Therefore, we maintain the following fields:
168 last_set_value the last value assigned
169 last_set_label records the value of label_tick when the
170 register was assigned
171 last_set_table_tick records the value of label_tick when a
172 value using the register is assigned
173 last_set_invalid set to nonzero when it is not valid
174 to use the value of this register in some
177 To understand the usage of these tables, it is important to understand
178 the distinction between the value in last_set_value being valid and
179 the register being validly contained in some other expression in the
182 (The next two parameters are out of date).
184 reg_stat[i].last_set_value is valid if it is nonzero, and either
185 reg_n_sets[i] is 1 or reg_stat[i].last_set_label == label_tick.
187 Register I may validly appear in any expression returned for the value
188 of another register if reg_n_sets[i] is 1. It may also appear in the
189 value for register J if reg_stat[j].last_set_invalid is zero, or
190 reg_stat[i].last_set_label < reg_stat[j].last_set_label.
192 If an expression is found in the table containing a register which may
193 not validly appear in an expression, the register is replaced by
194 something that won't match, (clobber (const_int 0)). */
196 /* Record last value assigned to (hard or pseudo) register n. */
200 /* Record the value of label_tick when an expression involving register n
201 is placed in last_set_value. */
203 int last_set_table_tick;
205 /* Record the value of label_tick when the value for register n is placed in
210 /* These fields are maintained in parallel with last_set_value and are
211 used to store the mode in which the register was last set, the bits
212 that were known to be zero when it was last set, and the number of
213 sign bits copies it was known to have when it was last set. */
215 unsigned HOST_WIDE_INT last_set_nonzero_bits;
216 char last_set_sign_bit_copies;
217 ENUM_BITFIELD(machine_mode) last_set_mode : 8;
219 /* Set nonzero if references to register n in expressions should not be
220 used. last_set_invalid is set nonzero when this register is being
221 assigned to and last_set_table_tick == label_tick. */
223 char last_set_invalid;
225 /* Some registers that are set more than once and used in more than one
226 basic block are nevertheless always set in similar ways. For example,
227 a QImode register may be loaded from memory in two places on a machine
228 where byte loads zero extend.
230 We record in the following fields if a register has some leading bits
231 that are always equal to the sign bit, and what we know about the
232 nonzero bits of a register, specifically which bits are known to be
235 If an entry is zero, it means that we don't know anything special. */
237 unsigned char sign_bit_copies;
239 unsigned HOST_WIDE_INT nonzero_bits;
241 /* Record the value of the label_tick when the last truncation
242 happened. The field truncated_to_mode is only valid if
243 truncation_label == label_tick. */
245 int truncation_label;
247 /* Record the last truncation seen for this register. If truncation
248 is not a nop to this mode we might be able to save an explicit
249 truncation if we know that value already contains a truncated
252 ENUM_BITFIELD(machine_mode) truncated_to_mode : 8;
255 DEF_VEC_O(reg_stat_type);
256 DEF_VEC_ALLOC_O(reg_stat_type,heap);
258 static VEC(reg_stat_type,heap) *reg_stat;
260 /* Record the luid of the last insn that invalidated memory
261 (anything that writes memory, and subroutine calls, but not pushes). */
263 static int mem_last_set;
265 /* Record the luid of the last CALL_INSN
266 so we can tell whether a potential combination crosses any calls. */
268 static int last_call_luid;
270 /* When `subst' is called, this is the insn that is being modified
271 (by combining in a previous insn). The PATTERN of this insn
272 is still the old pattern partially modified and it should not be
273 looked at, but this may be used to examine the successors of the insn
274 to judge whether a simplification is valid. */
276 static rtx subst_insn;
278 /* This is the lowest LUID that `subst' is currently dealing with.
279 get_last_value will not return a value if the register was set at or
280 after this LUID. If not for this mechanism, we could get confused if
281 I2 or I1 in try_combine were an insn that used the old value of a register
282 to obtain a new value. In that case, we might erroneously get the
283 new value of the register when we wanted the old one. */
285 static int subst_low_luid;
287 /* This contains any hard registers that are used in newpat; reg_dead_at_p
288 must consider all these registers to be always live. */
290 static HARD_REG_SET newpat_used_regs;
292 /* This is an insn to which a LOG_LINKS entry has been added. If this
293 insn is the earlier than I2 or I3, combine should rescan starting at
296 static rtx added_links_insn;
298 /* Basic block in which we are performing combines. */
299 static basic_block this_basic_block;
302 /* Length of the currently allocated uid_insn_cost array. */
304 static int max_uid_known;
306 /* The following array records the insn_rtx_cost for every insn
307 in the instruction stream. */
309 static int *uid_insn_cost;
311 /* The following array records the LOG_LINKS for every insn in the
312 instruction stream as an INSN_LIST rtx. */
314 static rtx *uid_log_links;
316 #define INSN_COST(INSN) (uid_insn_cost[INSN_UID (INSN)])
317 #define LOG_LINKS(INSN) (uid_log_links[INSN_UID (INSN)])
319 /* Incremented for each basic block. */
321 static int label_tick;
323 /* Reset to label_tick for each label. */
325 static int label_tick_ebb_start;
327 /* Mode used to compute significance in reg_stat[].nonzero_bits. It is the
328 largest integer mode that can fit in HOST_BITS_PER_WIDE_INT. */
330 static enum machine_mode nonzero_bits_mode;
332 /* Nonzero when reg_stat[].nonzero_bits and reg_stat[].sign_bit_copies can
333 be safely used. It is zero while computing them and after combine has
334 completed. This former test prevents propagating values based on
335 previously set values, which can be incorrect if a variable is modified
338 static int nonzero_sign_valid;
341 /* Record one modification to rtl structure
342 to be undone by storing old_contents into *where. */
347 enum { UNDO_RTX, UNDO_INT, UNDO_MODE } kind;
348 union { rtx r; int i; enum machine_mode m; } old_contents;
349 union { rtx *r; int *i; } where;
352 /* Record a bunch of changes to be undone, up to MAX_UNDO of them.
353 num_undo says how many are currently recorded.
355 other_insn is nonzero if we have modified some other insn in the process
356 of working on subst_insn. It must be verified too. */
365 static struct undobuf undobuf;
367 /* Number of times the pseudo being substituted for
368 was found and replaced. */
370 static int n_occurrences;
372 static rtx reg_nonzero_bits_for_combine (const_rtx, enum machine_mode, const_rtx,
374 unsigned HOST_WIDE_INT,
375 unsigned HOST_WIDE_INT *);
376 static rtx reg_num_sign_bit_copies_for_combine (const_rtx, enum machine_mode, const_rtx,
378 unsigned int, unsigned int *);
379 static void do_SUBST (rtx *, rtx);
380 static void do_SUBST_INT (int *, int);
381 static void init_reg_last (void);
382 static void setup_incoming_promotions (rtx);
383 static void set_nonzero_bits_and_sign_copies (rtx, const_rtx, void *);
384 static int cant_combine_insn_p (rtx);
385 static int can_combine_p (rtx, rtx, rtx, rtx, rtx *, rtx *);
386 static int combinable_i3pat (rtx, rtx *, rtx, rtx, int, rtx *);
387 static int contains_muldiv (rtx);
388 static rtx try_combine (rtx, rtx, rtx, int *);
389 static void undo_all (void);
390 static void undo_commit (void);
391 static rtx *find_split_point (rtx *, rtx);
392 static rtx subst (rtx, rtx, rtx, int, int);
393 static rtx combine_simplify_rtx (rtx, enum machine_mode, int);
394 static rtx simplify_if_then_else (rtx);
395 static rtx simplify_set (rtx);
396 static rtx simplify_logical (rtx);
397 static rtx expand_compound_operation (rtx);
398 static const_rtx expand_field_assignment (const_rtx);
399 static rtx make_extraction (enum machine_mode, rtx, HOST_WIDE_INT,
400 rtx, unsigned HOST_WIDE_INT, int, int, int);
401 static rtx extract_left_shift (rtx, int);
402 static rtx make_compound_operation (rtx, enum rtx_code);
403 static int get_pos_from_mask (unsigned HOST_WIDE_INT,
404 unsigned HOST_WIDE_INT *);
405 static rtx canon_reg_for_combine (rtx, rtx);
406 static rtx force_to_mode (rtx, enum machine_mode,
407 unsigned HOST_WIDE_INT, int);
408 static rtx if_then_else_cond (rtx, rtx *, rtx *);
409 static rtx known_cond (rtx, enum rtx_code, rtx, rtx);
410 static int rtx_equal_for_field_assignment_p (rtx, rtx);
411 static rtx make_field_assignment (rtx);
412 static rtx apply_distributive_law (rtx);
413 static rtx distribute_and_simplify_rtx (rtx, int);
414 static rtx simplify_and_const_int_1 (enum machine_mode, rtx,
415 unsigned HOST_WIDE_INT);
416 static rtx simplify_and_const_int (rtx, enum machine_mode, rtx,
417 unsigned HOST_WIDE_INT);
418 static int merge_outer_ops (enum rtx_code *, HOST_WIDE_INT *, enum rtx_code,
419 HOST_WIDE_INT, enum machine_mode, int *);
420 static rtx simplify_shift_const_1 (enum rtx_code, enum machine_mode, rtx, int);
421 static rtx simplify_shift_const (rtx, enum rtx_code, enum machine_mode, rtx,
423 static int recog_for_combine (rtx *, rtx, rtx *);
424 static rtx gen_lowpart_for_combine (enum machine_mode, rtx);
425 static enum rtx_code simplify_comparison (enum rtx_code, rtx *, rtx *);
426 static void update_table_tick (rtx);
427 static void record_value_for_reg (rtx, rtx, rtx);
428 static void check_conversions (rtx, rtx);
429 static void record_dead_and_set_regs_1 (rtx, const_rtx, void *);
430 static void record_dead_and_set_regs (rtx);
431 static int get_last_value_validate (rtx *, rtx, int, int);
432 static rtx get_last_value (const_rtx);
433 static int use_crosses_set_p (const_rtx, int);
434 static void reg_dead_at_p_1 (rtx, const_rtx, void *);
435 static int reg_dead_at_p (rtx, rtx);
436 static void move_deaths (rtx, rtx, int, rtx, rtx *);
437 static int reg_bitfield_target_p (rtx, rtx);
438 static void distribute_notes (rtx, rtx, rtx, rtx, rtx, rtx);
439 static void distribute_links (rtx);
440 static void mark_used_regs_combine (rtx);
441 static void record_promoted_value (rtx, rtx);
442 static int unmentioned_reg_p_1 (rtx *, void *);
443 static bool unmentioned_reg_p (rtx, rtx);
444 static void record_truncated_value (rtx);
445 static bool reg_truncated_to_mode (enum machine_mode, const_rtx);
446 static rtx gen_lowpart_or_truncate (enum machine_mode, rtx);
449 /* It is not safe to use ordinary gen_lowpart in combine.
450 See comments in gen_lowpart_for_combine. */
451 #undef RTL_HOOKS_GEN_LOWPART
452 #define RTL_HOOKS_GEN_LOWPART gen_lowpart_for_combine
454 /* Our implementation of gen_lowpart never emits a new pseudo. */
455 #undef RTL_HOOKS_GEN_LOWPART_NO_EMIT
456 #define RTL_HOOKS_GEN_LOWPART_NO_EMIT gen_lowpart_for_combine
458 #undef RTL_HOOKS_REG_NONZERO_REG_BITS
459 #define RTL_HOOKS_REG_NONZERO_REG_BITS reg_nonzero_bits_for_combine
461 #undef RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES
462 #define RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES reg_num_sign_bit_copies_for_combine
464 #undef RTL_HOOKS_REG_TRUNCATED_TO_MODE
465 #define RTL_HOOKS_REG_TRUNCATED_TO_MODE reg_truncated_to_mode
467 static const struct rtl_hooks combine_rtl_hooks = RTL_HOOKS_INITIALIZER;
470 /* Try to split PATTERN found in INSN. This returns NULL_RTX if
471 PATTERN can not be split. Otherwise, it returns an insn sequence.
472 This is a wrapper around split_insns which ensures that the
473 reg_stat vector is made larger if the splitter creates a new
477 combine_split_insns (rtx pattern, rtx insn)
482 ret = split_insns (pattern, insn);
483 nregs = max_reg_num ();
484 if (nregs > VEC_length (reg_stat_type, reg_stat))
485 VEC_safe_grow_cleared (reg_stat_type, heap, reg_stat, nregs);
489 /* This is used by find_single_use to locate an rtx in LOC that
490 contains exactly one use of DEST, which is typically either a REG
491 or CC0. It returns a pointer to the innermost rtx expression
492 containing DEST. Appearances of DEST that are being used to
493 totally replace it are not counted. */
496 find_single_use_1 (rtx dest, rtx *loc)
499 enum rtx_code code = GET_CODE (x);
517 /* If the destination is anything other than CC0, PC, a REG or a SUBREG
518 of a REG that occupies all of the REG, the insn uses DEST if
519 it is mentioned in the destination or the source. Otherwise, we
520 need just check the source. */
521 if (GET_CODE (SET_DEST (x)) != CC0
522 && GET_CODE (SET_DEST (x)) != PC
523 && !REG_P (SET_DEST (x))
524 && ! (GET_CODE (SET_DEST (x)) == SUBREG
525 && REG_P (SUBREG_REG (SET_DEST (x)))
526 && (((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x))))
527 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
528 == ((GET_MODE_SIZE (GET_MODE (SET_DEST (x)))
529 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD))))
532 return find_single_use_1 (dest, &SET_SRC (x));
536 return find_single_use_1 (dest, &XEXP (x, 0));
542 /* If it wasn't one of the common cases above, check each expression and
543 vector of this code. Look for a unique usage of DEST. */
545 fmt = GET_RTX_FORMAT (code);
546 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
550 if (dest == XEXP (x, i)
551 || (REG_P (dest) && REG_P (XEXP (x, i))
552 && REGNO (dest) == REGNO (XEXP (x, i))))
555 this_result = find_single_use_1 (dest, &XEXP (x, i));
558 result = this_result;
559 else if (this_result)
560 /* Duplicate usage. */
563 else if (fmt[i] == 'E')
567 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
569 if (XVECEXP (x, i, j) == dest
571 && REG_P (XVECEXP (x, i, j))
572 && REGNO (XVECEXP (x, i, j)) == REGNO (dest)))
575 this_result = find_single_use_1 (dest, &XVECEXP (x, i, j));
578 result = this_result;
579 else if (this_result)
589 /* See if DEST, produced in INSN, is used only a single time in the
590 sequel. If so, return a pointer to the innermost rtx expression in which
593 If PLOC is nonzero, *PLOC is set to the insn containing the single use.
595 If DEST is cc0_rtx, we look only at the next insn. In that case, we don't
596 care about REG_DEAD notes or LOG_LINKS.
598 Otherwise, we find the single use by finding an insn that has a
599 LOG_LINKS pointing at INSN and has a REG_DEAD note for DEST. If DEST is
600 only referenced once in that insn, we know that it must be the first
601 and last insn referencing DEST. */
604 find_single_use (rtx dest, rtx insn, rtx *ploc)
613 next = NEXT_INSN (insn);
615 || (!NONJUMP_INSN_P (next) && !JUMP_P (next)))
618 result = find_single_use_1 (dest, &PATTERN (next));
628 for (next = next_nonnote_insn (insn);
629 next != 0 && !LABEL_P (next);
630 next = next_nonnote_insn (next))
631 if (INSN_P (next) && dead_or_set_p (next, dest))
633 for (link = LOG_LINKS (next); link; link = XEXP (link, 1))
634 if (XEXP (link, 0) == insn)
639 result = find_single_use_1 (dest, &PATTERN (next));
649 /* Substitute NEWVAL, an rtx expression, into INTO, a place in some
650 insn. The substitution can be undone by undo_all. If INTO is already
651 set to NEWVAL, do not record this change. Because computing NEWVAL might
652 also call SUBST, we have to compute it before we put anything into
656 do_SUBST (rtx *into, rtx newval)
661 if (oldval == newval)
664 /* We'd like to catch as many invalid transformations here as
665 possible. Unfortunately, there are way too many mode changes
666 that are perfectly valid, so we'd waste too much effort for
667 little gain doing the checks here. Focus on catching invalid
668 transformations involving integer constants. */
669 if (GET_MODE_CLASS (GET_MODE (oldval)) == MODE_INT
670 && GET_CODE (newval) == CONST_INT)
672 /* Sanity check that we're replacing oldval with a CONST_INT
673 that is a valid sign-extension for the original mode. */
674 gcc_assert (INTVAL (newval)
675 == trunc_int_for_mode (INTVAL (newval), GET_MODE (oldval)));
677 /* Replacing the operand of a SUBREG or a ZERO_EXTEND with a
678 CONST_INT is not valid, because after the replacement, the
679 original mode would be gone. Unfortunately, we can't tell
680 when do_SUBST is called to replace the operand thereof, so we
681 perform this test on oldval instead, checking whether an
682 invalid replacement took place before we got here. */
683 gcc_assert (!(GET_CODE (oldval) == SUBREG
684 && GET_CODE (SUBREG_REG (oldval)) == CONST_INT));
685 gcc_assert (!(GET_CODE (oldval) == ZERO_EXTEND
686 && GET_CODE (XEXP (oldval, 0)) == CONST_INT));
690 buf = undobuf.frees, undobuf.frees = buf->next;
692 buf = XNEW (struct undo);
694 buf->kind = UNDO_RTX;
696 buf->old_contents.r = oldval;
699 buf->next = undobuf.undos, undobuf.undos = buf;
702 #define SUBST(INTO, NEWVAL) do_SUBST(&(INTO), (NEWVAL))
704 /* Similar to SUBST, but NEWVAL is an int expression. Note that substitution
705 for the value of a HOST_WIDE_INT value (including CONST_INT) is
709 do_SUBST_INT (int *into, int newval)
714 if (oldval == newval)
718 buf = undobuf.frees, undobuf.frees = buf->next;
720 buf = XNEW (struct undo);
722 buf->kind = UNDO_INT;
724 buf->old_contents.i = oldval;
727 buf->next = undobuf.undos, undobuf.undos = buf;
730 #define SUBST_INT(INTO, NEWVAL) do_SUBST_INT(&(INTO), (NEWVAL))
732 /* Similar to SUBST, but just substitute the mode. This is used when
733 changing the mode of a pseudo-register, so that any other
734 references to the entry in the regno_reg_rtx array will change as
738 do_SUBST_MODE (rtx *into, enum machine_mode newval)
741 enum machine_mode oldval = GET_MODE (*into);
743 if (oldval == newval)
747 buf = undobuf.frees, undobuf.frees = buf->next;
749 buf = XNEW (struct undo);
751 buf->kind = UNDO_MODE;
753 buf->old_contents.m = oldval;
754 adjust_reg_mode (*into, newval);
756 buf->next = undobuf.undos, undobuf.undos = buf;
759 #define SUBST_MODE(INTO, NEWVAL) do_SUBST_MODE(&(INTO), (NEWVAL))
761 /* Subroutine of try_combine. Determine whether the combine replacement
762 patterns NEWPAT, NEWI2PAT and NEWOTHERPAT are cheaper according to
763 insn_rtx_cost that the original instruction sequence I1, I2, I3 and
764 undobuf.other_insn. Note that I1 and/or NEWI2PAT may be NULL_RTX.
765 NEWOTHERPAT and undobuf.other_insn may also both be NULL_RTX. This
766 function returns false, if the costs of all instructions can be
767 estimated, and the replacements are more expensive than the original
771 combine_validate_cost (rtx i1, rtx i2, rtx i3, rtx newpat, rtx newi2pat,
774 int i1_cost, i2_cost, i3_cost;
775 int new_i2_cost, new_i3_cost;
776 int old_cost, new_cost;
778 /* Lookup the original insn_rtx_costs. */
779 i2_cost = INSN_COST (i2);
780 i3_cost = INSN_COST (i3);
784 i1_cost = INSN_COST (i1);
785 old_cost = (i1_cost > 0 && i2_cost > 0 && i3_cost > 0)
786 ? i1_cost + i2_cost + i3_cost : 0;
790 old_cost = (i2_cost > 0 && i3_cost > 0) ? i2_cost + i3_cost : 0;
794 /* Calculate the replacement insn_rtx_costs. */
795 new_i3_cost = insn_rtx_cost (newpat);
798 new_i2_cost = insn_rtx_cost (newi2pat);
799 new_cost = (new_i2_cost > 0 && new_i3_cost > 0)
800 ? new_i2_cost + new_i3_cost : 0;
804 new_cost = new_i3_cost;
808 if (undobuf.other_insn)
810 int old_other_cost, new_other_cost;
812 old_other_cost = INSN_COST (undobuf.other_insn);
813 new_other_cost = insn_rtx_cost (newotherpat);
814 if (old_other_cost > 0 && new_other_cost > 0)
816 old_cost += old_other_cost;
817 new_cost += new_other_cost;
823 /* Disallow this recombination if both new_cost and old_cost are
824 greater than zero, and new_cost is greater than old cost. */
826 && new_cost > old_cost)
833 "rejecting combination of insns %d, %d and %d\n",
834 INSN_UID (i1), INSN_UID (i2), INSN_UID (i3));
835 fprintf (dump_file, "original costs %d + %d + %d = %d\n",
836 i1_cost, i2_cost, i3_cost, old_cost);
841 "rejecting combination of insns %d and %d\n",
842 INSN_UID (i2), INSN_UID (i3));
843 fprintf (dump_file, "original costs %d + %d = %d\n",
844 i2_cost, i3_cost, old_cost);
849 fprintf (dump_file, "replacement costs %d + %d = %d\n",
850 new_i2_cost, new_i3_cost, new_cost);
853 fprintf (dump_file, "replacement cost %d\n", new_cost);
859 /* Update the uid_insn_cost array with the replacement costs. */
860 INSN_COST (i2) = new_i2_cost;
861 INSN_COST (i3) = new_i3_cost;
869 /* Delete any insns that copy a register to itself. */
872 delete_noop_moves (void)
879 for (insn = BB_HEAD (bb); insn != NEXT_INSN (BB_END (bb)); insn = next)
881 next = NEXT_INSN (insn);
882 if (INSN_P (insn) && noop_move_p (insn))
886 /* If we're about to remove the first insn of a libcall
887 then move the libcall note to the next real insn and
888 update the retval note. */
889 if ((note = find_reg_note (insn, REG_LIBCALL, NULL_RTX))
890 && XEXP (note, 0) != insn)
892 rtx new_libcall_insn = next_real_insn (insn);
893 rtx retval_note = find_reg_note (XEXP (note, 0),
894 REG_RETVAL, NULL_RTX);
895 REG_NOTES (new_libcall_insn)
896 = gen_rtx_INSN_LIST (REG_LIBCALL, XEXP (note, 0),
897 REG_NOTES (new_libcall_insn));
898 XEXP (retval_note, 0) = new_libcall_insn;
902 fprintf (dump_file, "deleting noop move %d\n", INSN_UID (insn));
904 delete_insn_and_edges (insn);
911 /* Fill in log links field for all insns. */
914 create_log_links (void)
918 struct df_ref **def_vec, **use_vec;
920 next_use = XCNEWVEC (rtx, max_reg_num ());
922 /* Pass through each block from the end, recording the uses of each
923 register and establishing log links when def is encountered.
924 Note that we do not clear next_use array in order to save time,
925 so we have to test whether the use is in the same basic block as def.
927 There are a few cases below when we do not consider the definition or
928 usage -- these are taken from original flow.c did. Don't ask me why it is
929 done this way; I don't know and if it works, I don't want to know. */
933 FOR_BB_INSNS_REVERSE (bb, insn)
938 /* Log links are created only once. */
939 gcc_assert (!LOG_LINKS (insn));
941 for (def_vec = DF_INSN_DEFS (insn); *def_vec; def_vec++)
943 struct df_ref *def = *def_vec;
944 int regno = DF_REF_REGNO (def);
947 if (!next_use[regno])
950 /* Do not consider if it is pre/post modification in MEM. */
951 if (DF_REF_FLAGS (def) & DF_REF_PRE_POST_MODIFY)
954 /* Do not make the log link for frame pointer. */
955 if ((regno == FRAME_POINTER_REGNUM
956 && (! reload_completed || frame_pointer_needed))
957 #if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM
958 || (regno == HARD_FRAME_POINTER_REGNUM
959 && (! reload_completed || frame_pointer_needed))
961 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
962 || (regno == ARG_POINTER_REGNUM && fixed_regs[regno])
967 use_insn = next_use[regno];
968 if (BLOCK_FOR_INSN (use_insn) == bb)
972 We don't build a LOG_LINK for hard registers contained
973 in ASM_OPERANDs. If these registers get replaced,
974 we might wind up changing the semantics of the insn,
975 even if reload can make what appear to be valid
976 assignments later. */
977 if (regno >= FIRST_PSEUDO_REGISTER
978 || asm_noperands (PATTERN (use_insn)) < 0)
980 /* Don't add duplicate links between instructions. */
982 for (links = LOG_LINKS (use_insn); links;
983 links = XEXP (links, 1))
984 if (insn == XEXP (links, 0))
988 LOG_LINKS (use_insn) =
989 alloc_INSN_LIST (insn, LOG_LINKS (use_insn));
992 next_use[regno] = NULL_RTX;
995 for (use_vec = DF_INSN_USES (insn); *use_vec; use_vec++)
997 struct df_ref *use = *use_vec;
998 int regno = DF_REF_REGNO (use);
1000 /* Do not consider the usage of the stack pointer
1001 by function call. */
1002 if (DF_REF_FLAGS (use) & DF_REF_CALL_STACK_USAGE)
1005 next_use[regno] = insn;
1013 /* Clear LOG_LINKS fields of insns. */
1016 clear_log_links (void)
1020 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
1022 free_INSN_LIST_list (&LOG_LINKS (insn));
1028 /* Main entry point for combiner. F is the first insn of the function.
1029 NREGS is the first unused pseudo-reg number.
1031 Return nonzero if the combiner has turned an indirect jump
1032 instruction into a direct jump. */
1034 combine_instructions (rtx f, unsigned int nregs)
1040 rtx links, nextlinks;
1043 int new_direct_jump_p = 0;
1045 for (first = f; first && !INSN_P (first); )
1046 first = NEXT_INSN (first);
1050 combine_attempts = 0;
1053 combine_successes = 0;
1055 rtl_hooks = combine_rtl_hooks;
1057 VEC_safe_grow_cleared (reg_stat_type, heap, reg_stat, nregs);
1059 init_recog_no_volatile ();
1061 /* Allocate array for insn info. */
1062 max_uid_known = get_max_uid ();
1063 uid_log_links = XCNEWVEC (rtx, max_uid_known + 1);
1064 uid_insn_cost = XCNEWVEC (int, max_uid_known + 1);
1066 nonzero_bits_mode = mode_for_size (HOST_BITS_PER_WIDE_INT, MODE_INT, 0);
1068 /* Don't use reg_stat[].nonzero_bits when computing it. This can cause
1069 problems when, for example, we have j <<= 1 in a loop. */
1071 nonzero_sign_valid = 0;
1073 /* Scan all SETs and see if we can deduce anything about what
1074 bits are known to be zero for some registers and how many copies
1075 of the sign bit are known to exist for those registers.
1077 Also set any known values so that we can use it while searching
1078 for what bits are known to be set. */
1080 label_tick = label_tick_ebb_start = 1;
1082 setup_incoming_promotions (first);
1084 create_log_links ();
1085 FOR_EACH_BB (this_basic_block)
1090 FOR_BB_INSNS (this_basic_block, insn)
1091 if (INSN_P (insn) && BLOCK_FOR_INSN (insn))
1093 subst_low_luid = DF_INSN_LUID (insn);
1096 note_stores (PATTERN (insn), set_nonzero_bits_and_sign_copies,
1098 record_dead_and_set_regs (insn);
1101 for (links = REG_NOTES (insn); links; links = XEXP (links, 1))
1102 if (REG_NOTE_KIND (links) == REG_INC)
1103 set_nonzero_bits_and_sign_copies (XEXP (links, 0), NULL_RTX,
1107 /* Record the current insn_rtx_cost of this instruction. */
1108 if (NONJUMP_INSN_P (insn))
1109 INSN_COST (insn) = insn_rtx_cost (PATTERN (insn));
1111 fprintf(dump_file, "insn_cost %d: %d\n",
1112 INSN_UID (insn), INSN_COST (insn));
1114 else if (LABEL_P (insn))
1115 label_tick_ebb_start = label_tick;
1118 nonzero_sign_valid = 1;
1120 /* Now scan all the insns in forward order. */
1122 label_tick = label_tick_ebb_start = 1;
1124 setup_incoming_promotions (first);
1126 FOR_EACH_BB (this_basic_block)
1131 for (insn = BB_HEAD (this_basic_block);
1132 insn != NEXT_INSN (BB_END (this_basic_block));
1133 insn = next ? next : NEXT_INSN (insn))
1138 /* See if we know about function return values before this
1139 insn based upon SUBREG flags. */
1140 check_conversions (insn, PATTERN (insn));
1142 /* Try this insn with each insn it links back to. */
1144 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
1145 if ((next = try_combine (insn, XEXP (links, 0),
1146 NULL_RTX, &new_direct_jump_p)) != 0)
1149 /* Try each sequence of three linked insns ending with this one. */
1151 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
1153 rtx link = XEXP (links, 0);
1155 /* If the linked insn has been replaced by a note, then there
1156 is no point in pursuing this chain any further. */
1160 for (nextlinks = LOG_LINKS (link);
1162 nextlinks = XEXP (nextlinks, 1))
1163 if ((next = try_combine (insn, link,
1164 XEXP (nextlinks, 0),
1165 &new_direct_jump_p)) != 0)
1170 /* Try to combine a jump insn that uses CC0
1171 with a preceding insn that sets CC0, and maybe with its
1172 logical predecessor as well.
1173 This is how we make decrement-and-branch insns.
1174 We need this special code because data flow connections
1175 via CC0 do not get entered in LOG_LINKS. */
1178 && (prev = prev_nonnote_insn (insn)) != 0
1179 && NONJUMP_INSN_P (prev)
1180 && sets_cc0_p (PATTERN (prev)))
1182 if ((next = try_combine (insn, prev,
1183 NULL_RTX, &new_direct_jump_p)) != 0)
1186 for (nextlinks = LOG_LINKS (prev); nextlinks;
1187 nextlinks = XEXP (nextlinks, 1))
1188 if ((next = try_combine (insn, prev,
1189 XEXP (nextlinks, 0),
1190 &new_direct_jump_p)) != 0)
1194 /* Do the same for an insn that explicitly references CC0. */
1195 if (NONJUMP_INSN_P (insn)
1196 && (prev = prev_nonnote_insn (insn)) != 0
1197 && NONJUMP_INSN_P (prev)
1198 && sets_cc0_p (PATTERN (prev))
1199 && GET_CODE (PATTERN (insn)) == SET
1200 && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (insn))))
1202 if ((next = try_combine (insn, prev,
1203 NULL_RTX, &new_direct_jump_p)) != 0)
1206 for (nextlinks = LOG_LINKS (prev); nextlinks;
1207 nextlinks = XEXP (nextlinks, 1))
1208 if ((next = try_combine (insn, prev,
1209 XEXP (nextlinks, 0),
1210 &new_direct_jump_p)) != 0)
1214 /* Finally, see if any of the insns that this insn links to
1215 explicitly references CC0. If so, try this insn, that insn,
1216 and its predecessor if it sets CC0. */
1217 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
1218 if (NONJUMP_INSN_P (XEXP (links, 0))
1219 && GET_CODE (PATTERN (XEXP (links, 0))) == SET
1220 && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (XEXP (links, 0))))
1221 && (prev = prev_nonnote_insn (XEXP (links, 0))) != 0
1222 && NONJUMP_INSN_P (prev)
1223 && sets_cc0_p (PATTERN (prev))
1224 && (next = try_combine (insn, XEXP (links, 0),
1225 prev, &new_direct_jump_p)) != 0)
1229 /* Try combining an insn with two different insns whose results it
1231 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
1232 for (nextlinks = XEXP (links, 1); nextlinks;
1233 nextlinks = XEXP (nextlinks, 1))
1234 if ((next = try_combine (insn, XEXP (links, 0),
1235 XEXP (nextlinks, 0),
1236 &new_direct_jump_p)) != 0)
1239 /* Try this insn with each REG_EQUAL note it links back to. */
1240 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
1243 rtx temp = XEXP (links, 0);
1244 if ((set = single_set (temp)) != 0
1245 && (note = find_reg_equal_equiv_note (temp)) != 0
1246 && (note = XEXP (note, 0), GET_CODE (note)) != EXPR_LIST
1247 /* Avoid using a register that may already been marked
1248 dead by an earlier instruction. */
1249 && ! unmentioned_reg_p (note, SET_SRC (set))
1250 && (GET_MODE (note) == VOIDmode
1251 ? SCALAR_INT_MODE_P (GET_MODE (SET_DEST (set)))
1252 : GET_MODE (SET_DEST (set)) == GET_MODE (note)))
1254 /* Temporarily replace the set's source with the
1255 contents of the REG_EQUAL note. The insn will
1256 be deleted or recognized by try_combine. */
1257 rtx orig = SET_SRC (set);
1258 SET_SRC (set) = note;
1260 i2mod_old_rhs = copy_rtx (orig);
1261 i2mod_new_rhs = copy_rtx (note);
1262 next = try_combine (insn, i2mod, NULL_RTX,
1263 &new_direct_jump_p);
1267 SET_SRC (set) = orig;
1272 record_dead_and_set_regs (insn);
1277 else if (LABEL_P (insn))
1278 label_tick_ebb_start = label_tick;
1284 new_direct_jump_p |= purge_all_dead_edges ();
1285 delete_noop_moves ();
1288 free (uid_log_links);
1289 free (uid_insn_cost);
1290 VEC_free (reg_stat_type, heap, reg_stat);
1293 struct undo *undo, *next;
1294 for (undo = undobuf.frees; undo; undo = next)
1302 total_attempts += combine_attempts;
1303 total_merges += combine_merges;
1304 total_extras += combine_extras;
1305 total_successes += combine_successes;
1307 nonzero_sign_valid = 0;
1308 rtl_hooks = general_rtl_hooks;
1310 /* Make recognizer allow volatile MEMs again. */
1313 return new_direct_jump_p;
1316 /* Wipe the last_xxx fields of reg_stat in preparation for another pass. */
1319 init_reg_last (void)
1324 for (i = 0; VEC_iterate (reg_stat_type, reg_stat, i, p); ++i)
1325 memset (p, 0, offsetof (reg_stat_type, sign_bit_copies));
1328 /* Set up any promoted values for incoming argument registers. */
1331 setup_incoming_promotions (rtx first)
1334 bool strictly_local = false;
1336 if (!targetm.calls.promote_function_args (TREE_TYPE (cfun->decl)))
1339 for (arg = DECL_ARGUMENTS (current_function_decl); arg;
1340 arg = TREE_CHAIN (arg))
1342 rtx reg = DECL_INCOMING_RTL (arg);
1344 enum machine_mode mode1, mode2, mode3, mode4;
1346 /* Only continue if the incoming argument is in a register. */
1350 /* Determine, if possible, whether all call sites of the current
1351 function lie within the current compilation unit. (This does
1352 take into account the exporting of a function via taking its
1353 address, and so forth.) */
1354 if (flag_unit_at_a_time)
1355 strictly_local = cgraph_local_info (current_function_decl)->local;
1357 /* The mode and signedness of the argument before any promotions happen
1358 (equal to the mode of the pseudo holding it at that stage). */
1359 mode1 = TYPE_MODE (TREE_TYPE (arg));
1360 uns1 = TYPE_UNSIGNED (TREE_TYPE (arg));
1362 /* The mode and signedness of the argument after any source language and
1363 TARGET_PROMOTE_PROTOTYPES-driven promotions. */
1364 mode2 = TYPE_MODE (DECL_ARG_TYPE (arg));
1365 uns3 = TYPE_UNSIGNED (DECL_ARG_TYPE (arg));
1367 /* The mode and signedness of the argument as it is actually passed,
1368 after any TARGET_PROMOTE_FUNCTION_ARGS-driven ABI promotions. */
1369 mode3 = promote_mode (DECL_ARG_TYPE (arg), mode2, &uns3, 1);
1371 /* The mode of the register in which the argument is being passed. */
1372 mode4 = GET_MODE (reg);
1374 /* Eliminate sign extensions in the callee when possible. Only
1376 (a) a mode promotion has occurred;
1377 (b) the mode of the register is the same as the mode of
1378 the argument as it is passed; and
1379 (c) the signedness does not change across any of the promotions; and
1380 (d) when no language-level promotions (which we cannot guarantee
1381 will have been done by an external caller) are necessary,
1382 unless we know that this function is only ever called from
1383 the current compilation unit -- all of whose call sites will
1384 do the mode1 --> mode2 promotion. */
1388 && (mode1 == mode2 || strictly_local))
1390 /* Record that the value was promoted from mode1 to mode3,
1391 so that any sign extension at the head of the current
1392 function may be eliminated. */
1394 x = gen_rtx_CLOBBER (mode1, const0_rtx);
1395 x = gen_rtx_fmt_e ((uns3 ? ZERO_EXTEND : SIGN_EXTEND), mode3, x);
1396 record_value_for_reg (reg, first, x);
1401 /* Called via note_stores. If X is a pseudo that is narrower than
1402 HOST_BITS_PER_WIDE_INT and is being set, record what bits are known zero.
1404 If we are setting only a portion of X and we can't figure out what
1405 portion, assume all bits will be used since we don't know what will
1408 Similarly, set how many bits of X are known to be copies of the sign bit
1409 at all locations in the function. This is the smallest number implied
1413 set_nonzero_bits_and_sign_copies (rtx x, const_rtx set, void *data)
1415 rtx insn = (rtx) data;
1419 && REGNO (x) >= FIRST_PSEUDO_REGISTER
1420 /* If this register is undefined at the start of the file, we can't
1421 say what its contents were. */
1422 && ! REGNO_REG_SET_P
1423 (DF_LR_IN (ENTRY_BLOCK_PTR->next_bb), REGNO (x))
1424 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT)
1426 reg_stat_type *rsp = VEC_index (reg_stat_type, reg_stat, REGNO (x));
1428 if (set == 0 || GET_CODE (set) == CLOBBER)
1430 rsp->nonzero_bits = GET_MODE_MASK (GET_MODE (x));
1431 rsp->sign_bit_copies = 1;
1435 /* If this register is being initialized using itself, and the
1436 register is uninitialized in this basic block, and there are
1437 no LOG_LINKS which set the register, then part of the
1438 register is uninitialized. In that case we can't assume
1439 anything about the number of nonzero bits.
1441 ??? We could do better if we checked this in
1442 reg_{nonzero_bits,num_sign_bit_copies}_for_combine. Then we
1443 could avoid making assumptions about the insn which initially
1444 sets the register, while still using the information in other
1445 insns. We would have to be careful to check every insn
1446 involved in the combination. */
1449 && reg_referenced_p (x, PATTERN (insn))
1450 && !REGNO_REG_SET_P (DF_LR_IN (BLOCK_FOR_INSN (insn)),
1455 for (link = LOG_LINKS (insn); link; link = XEXP (link, 1))
1457 if (dead_or_set_p (XEXP (link, 0), x))
1462 rsp->nonzero_bits = GET_MODE_MASK (GET_MODE (x));
1463 rsp->sign_bit_copies = 1;
1468 /* If this is a complex assignment, see if we can convert it into a
1469 simple assignment. */
1470 set = expand_field_assignment (set);
1472 /* If this is a simple assignment, or we have a paradoxical SUBREG,
1473 set what we know about X. */
1475 if (SET_DEST (set) == x
1476 || (GET_CODE (SET_DEST (set)) == SUBREG
1477 && (GET_MODE_SIZE (GET_MODE (SET_DEST (set)))
1478 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (set)))))
1479 && SUBREG_REG (SET_DEST (set)) == x))
1481 rtx src = SET_SRC (set);
1483 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
1484 /* If X is narrower than a word and SRC is a non-negative
1485 constant that would appear negative in the mode of X,
1486 sign-extend it for use in reg_stat[].nonzero_bits because some
1487 machines (maybe most) will actually do the sign-extension
1488 and this is the conservative approach.
1490 ??? For 2.5, try to tighten up the MD files in this regard
1491 instead of this kludge. */
1493 if (GET_MODE_BITSIZE (GET_MODE (x)) < BITS_PER_WORD
1494 && GET_CODE (src) == CONST_INT
1496 && 0 != (INTVAL (src)
1497 & ((HOST_WIDE_INT) 1
1498 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
1499 src = GEN_INT (INTVAL (src)
1500 | ((HOST_WIDE_INT) (-1)
1501 << GET_MODE_BITSIZE (GET_MODE (x))));
1504 /* Don't call nonzero_bits if it cannot change anything. */
1505 if (rsp->nonzero_bits != ~(unsigned HOST_WIDE_INT) 0)
1506 rsp->nonzero_bits |= nonzero_bits (src, nonzero_bits_mode);
1507 num = num_sign_bit_copies (SET_SRC (set), GET_MODE (x));
1508 if (rsp->sign_bit_copies == 0
1509 || rsp->sign_bit_copies > num)
1510 rsp->sign_bit_copies = num;
1514 rsp->nonzero_bits = GET_MODE_MASK (GET_MODE (x));
1515 rsp->sign_bit_copies = 1;
1520 /* See if INSN can be combined into I3. PRED and SUCC are optionally
1521 insns that were previously combined into I3 or that will be combined
1522 into the merger of INSN and I3.
1524 Return 0 if the combination is not allowed for any reason.
1526 If the combination is allowed, *PDEST will be set to the single
1527 destination of INSN and *PSRC to the single source, and this function
1531 can_combine_p (rtx insn, rtx i3, rtx pred ATTRIBUTE_UNUSED, rtx succ,
1532 rtx *pdest, rtx *psrc)
1541 int all_adjacent = (succ ? (next_active_insn (insn) == succ
1542 && next_active_insn (succ) == i3)
1543 : next_active_insn (insn) == i3);
1545 /* Can combine only if previous insn is a SET of a REG, a SUBREG or CC0.
1546 or a PARALLEL consisting of such a SET and CLOBBERs.
1548 If INSN has CLOBBER parallel parts, ignore them for our processing.
1549 By definition, these happen during the execution of the insn. When it
1550 is merged with another insn, all bets are off. If they are, in fact,
1551 needed and aren't also supplied in I3, they may be added by
1552 recog_for_combine. Otherwise, it won't match.
1554 We can also ignore a SET whose SET_DEST is mentioned in a REG_UNUSED
1557 Get the source and destination of INSN. If more than one, can't
1560 if (GET_CODE (PATTERN (insn)) == SET)
1561 set = PATTERN (insn);
1562 else if (GET_CODE (PATTERN (insn)) == PARALLEL
1563 && GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == SET)
1565 for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
1567 rtx elt = XVECEXP (PATTERN (insn), 0, i);
1570 switch (GET_CODE (elt))
1572 /* This is important to combine floating point insns
1573 for the SH4 port. */
1575 /* Combining an isolated USE doesn't make sense.
1576 We depend here on combinable_i3pat to reject them. */
1577 /* The code below this loop only verifies that the inputs of
1578 the SET in INSN do not change. We call reg_set_between_p
1579 to verify that the REG in the USE does not change between
1581 If the USE in INSN was for a pseudo register, the matching
1582 insn pattern will likely match any register; combining this
1583 with any other USE would only be safe if we knew that the
1584 used registers have identical values, or if there was
1585 something to tell them apart, e.g. different modes. For
1586 now, we forgo such complicated tests and simply disallow
1587 combining of USES of pseudo registers with any other USE. */
1588 if (REG_P (XEXP (elt, 0))
1589 && GET_CODE (PATTERN (i3)) == PARALLEL)
1591 rtx i3pat = PATTERN (i3);
1592 int i = XVECLEN (i3pat, 0) - 1;
1593 unsigned int regno = REGNO (XEXP (elt, 0));
1597 rtx i3elt = XVECEXP (i3pat, 0, i);
1599 if (GET_CODE (i3elt) == USE
1600 && REG_P (XEXP (i3elt, 0))
1601 && (REGNO (XEXP (i3elt, 0)) == regno
1602 ? reg_set_between_p (XEXP (elt, 0),
1603 PREV_INSN (insn), i3)
1604 : regno >= FIRST_PSEUDO_REGISTER))
1611 /* We can ignore CLOBBERs. */
1616 /* Ignore SETs whose result isn't used but not those that
1617 have side-effects. */
1618 if (find_reg_note (insn, REG_UNUSED, SET_DEST (elt))
1619 && (!(note = find_reg_note (insn, REG_EH_REGION, NULL_RTX))
1620 || INTVAL (XEXP (note, 0)) <= 0)
1621 && ! side_effects_p (elt))
1624 /* If we have already found a SET, this is a second one and
1625 so we cannot combine with this insn. */
1633 /* Anything else means we can't combine. */
1639 /* If SET_SRC is an ASM_OPERANDS we can't throw away these CLOBBERs,
1640 so don't do anything with it. */
1641 || GET_CODE (SET_SRC (set)) == ASM_OPERANDS)
1650 set = expand_field_assignment (set);
1651 src = SET_SRC (set), dest = SET_DEST (set);
1653 /* Don't eliminate a store in the stack pointer. */
1654 if (dest == stack_pointer_rtx
1655 /* Don't combine with an insn that sets a register to itself if it has
1656 a REG_EQUAL note. This may be part of a LIBCALL sequence. */
1657 || (rtx_equal_p (src, dest) && find_reg_note (insn, REG_EQUAL, NULL_RTX))
1658 /* Can't merge an ASM_OPERANDS. */
1659 || GET_CODE (src) == ASM_OPERANDS
1660 /* Can't merge a function call. */
1661 || GET_CODE (src) == CALL
1662 /* Don't eliminate a function call argument. */
1664 && (find_reg_fusage (i3, USE, dest)
1666 && REGNO (dest) < FIRST_PSEUDO_REGISTER
1667 && global_regs[REGNO (dest)])))
1668 /* Don't substitute into an incremented register. */
1669 || FIND_REG_INC_NOTE (i3, dest)
1670 || (succ && FIND_REG_INC_NOTE (succ, dest))
1671 /* Don't substitute into a non-local goto, this confuses CFG. */
1672 || (JUMP_P (i3) && find_reg_note (i3, REG_NON_LOCAL_GOTO, NULL_RTX))
1674 /* Don't combine the end of a libcall into anything. */
1675 /* ??? This gives worse code, and appears to be unnecessary, since no
1676 pass after flow uses REG_LIBCALL/REG_RETVAL notes. Local-alloc does
1677 use REG_RETVAL notes for noconflict blocks, but other code here
1678 makes sure that those insns don't disappear. */
1679 || find_reg_note (insn, REG_RETVAL, NULL_RTX)
1681 /* Make sure that DEST is not used after SUCC but before I3. */
1682 || (succ && ! all_adjacent
1683 && reg_used_between_p (dest, succ, i3))
1684 /* Make sure that the value that is to be substituted for the register
1685 does not use any registers whose values alter in between. However,
1686 If the insns are adjacent, a use can't cross a set even though we
1687 think it might (this can happen for a sequence of insns each setting
1688 the same destination; last_set of that register might point to
1689 a NOTE). If INSN has a REG_EQUIV note, the register is always
1690 equivalent to the memory so the substitution is valid even if there
1691 are intervening stores. Also, don't move a volatile asm or
1692 UNSPEC_VOLATILE across any other insns. */
1695 || ! find_reg_note (insn, REG_EQUIV, src))
1696 && use_crosses_set_p (src, DF_INSN_LUID (insn)))
1697 || (GET_CODE (src) == ASM_OPERANDS && MEM_VOLATILE_P (src))
1698 || GET_CODE (src) == UNSPEC_VOLATILE))
1699 /* Don't combine across a CALL_INSN, because that would possibly
1700 change whether the life span of some REGs crosses calls or not,
1701 and it is a pain to update that information.
1702 Exception: if source is a constant, moving it later can't hurt.
1703 Accept that as a special case. */
1704 || (DF_INSN_LUID (insn) < last_call_luid && ! CONSTANT_P (src)))
1707 /* DEST must either be a REG or CC0. */
1710 /* If register alignment is being enforced for multi-word items in all
1711 cases except for parameters, it is possible to have a register copy
1712 insn referencing a hard register that is not allowed to contain the
1713 mode being copied and which would not be valid as an operand of most
1714 insns. Eliminate this problem by not combining with such an insn.
1716 Also, on some machines we don't want to extend the life of a hard
1720 && ((REGNO (dest) < FIRST_PSEUDO_REGISTER
1721 && ! HARD_REGNO_MODE_OK (REGNO (dest), GET_MODE (dest)))
1722 /* Don't extend the life of a hard register unless it is
1723 user variable (if we have few registers) or it can't
1724 fit into the desired register (meaning something special
1726 Also avoid substituting a return register into I3, because
1727 reload can't handle a conflict with constraints of other
1729 || (REGNO (src) < FIRST_PSEUDO_REGISTER
1730 && ! HARD_REGNO_MODE_OK (REGNO (src), GET_MODE (src)))))
1733 else if (GET_CODE (dest) != CC0)
1737 if (GET_CODE (PATTERN (i3)) == PARALLEL)
1738 for (i = XVECLEN (PATTERN (i3), 0) - 1; i >= 0; i--)
1739 if (GET_CODE (XVECEXP (PATTERN (i3), 0, i)) == CLOBBER)
1741 /* Don't substitute for a register intended as a clobberable
1743 rtx reg = XEXP (XVECEXP (PATTERN (i3), 0, i), 0);
1744 if (rtx_equal_p (reg, dest))
1747 /* If the clobber represents an earlyclobber operand, we must not
1748 substitute an expression containing the clobbered register.
1749 As we do not analyze the constraint strings here, we have to
1750 make the conservative assumption. However, if the register is
1751 a fixed hard reg, the clobber cannot represent any operand;
1752 we leave it up to the machine description to either accept or
1753 reject use-and-clobber patterns. */
1755 || REGNO (reg) >= FIRST_PSEUDO_REGISTER
1756 || !fixed_regs[REGNO (reg)])
1757 if (reg_overlap_mentioned_p (reg, src))
1761 /* If INSN contains anything volatile, or is an `asm' (whether volatile
1762 or not), reject, unless nothing volatile comes between it and I3 */
1764 if (GET_CODE (src) == ASM_OPERANDS || volatile_refs_p (src))
1766 /* Make sure succ doesn't contain a volatile reference. */
1767 if (succ != 0 && volatile_refs_p (PATTERN (succ)))
1770 for (p = NEXT_INSN (insn); p != i3; p = NEXT_INSN (p))
1771 if (INSN_P (p) && p != succ && volatile_refs_p (PATTERN (p)))
1775 /* If INSN is an asm, and DEST is a hard register, reject, since it has
1776 to be an explicit register variable, and was chosen for a reason. */
1778 if (GET_CODE (src) == ASM_OPERANDS
1779 && REG_P (dest) && REGNO (dest) < FIRST_PSEUDO_REGISTER)
1782 /* If there are any volatile insns between INSN and I3, reject, because
1783 they might affect machine state. */
1785 for (p = NEXT_INSN (insn); p != i3; p = NEXT_INSN (p))
1786 if (INSN_P (p) && p != succ && volatile_insn_p (PATTERN (p)))
1789 /* If INSN contains an autoincrement or autodecrement, make sure that
1790 register is not used between there and I3, and not already used in
1791 I3 either. Neither must it be used in PRED or SUCC, if they exist.
1792 Also insist that I3 not be a jump; if it were one
1793 and the incremented register were spilled, we would lose. */
1796 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
1797 if (REG_NOTE_KIND (link) == REG_INC
1799 || reg_used_between_p (XEXP (link, 0), insn, i3)
1800 || (pred != NULL_RTX
1801 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (pred)))
1802 || (succ != NULL_RTX
1803 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (succ)))
1804 || reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i3))))
1809 /* Don't combine an insn that follows a CC0-setting insn.
1810 An insn that uses CC0 must not be separated from the one that sets it.
1811 We do, however, allow I2 to follow a CC0-setting insn if that insn
1812 is passed as I1; in that case it will be deleted also.
1813 We also allow combining in this case if all the insns are adjacent
1814 because that would leave the two CC0 insns adjacent as well.
1815 It would be more logical to test whether CC0 occurs inside I1 or I2,
1816 but that would be much slower, and this ought to be equivalent. */
1818 p = prev_nonnote_insn (insn);
1819 if (p && p != pred && NONJUMP_INSN_P (p) && sets_cc0_p (PATTERN (p))
1824 /* If we get here, we have passed all the tests and the combination is
1833 /* LOC is the location within I3 that contains its pattern or the component
1834 of a PARALLEL of the pattern. We validate that it is valid for combining.
1836 One problem is if I3 modifies its output, as opposed to replacing it
1837 entirely, we can't allow the output to contain I2DEST or I1DEST as doing
1838 so would produce an insn that is not equivalent to the original insns.
1842 (set (reg:DI 101) (reg:DI 100))
1843 (set (subreg:SI (reg:DI 101) 0) <foo>)
1845 This is NOT equivalent to:
1847 (parallel [(set (subreg:SI (reg:DI 100) 0) <foo>)
1848 (set (reg:DI 101) (reg:DI 100))])
1850 Not only does this modify 100 (in which case it might still be valid
1851 if 100 were dead in I2), it sets 101 to the ORIGINAL value of 100.
1853 We can also run into a problem if I2 sets a register that I1
1854 uses and I1 gets directly substituted into I3 (not via I2). In that
1855 case, we would be getting the wrong value of I2DEST into I3, so we
1856 must reject the combination. This case occurs when I2 and I1 both
1857 feed into I3, rather than when I1 feeds into I2, which feeds into I3.
1858 If I1_NOT_IN_SRC is nonzero, it means that finding I1 in the source
1859 of a SET must prevent combination from occurring.
1861 Before doing the above check, we first try to expand a field assignment
1862 into a set of logical operations.
1864 If PI3_DEST_KILLED is nonzero, it is a pointer to a location in which
1865 we place a register that is both set and used within I3. If more than one
1866 such register is detected, we fail.
1868 Return 1 if the combination is valid, zero otherwise. */
1871 combinable_i3pat (rtx i3, rtx *loc, rtx i2dest, rtx i1dest,
1872 int i1_not_in_src, rtx *pi3dest_killed)
1876 if (GET_CODE (x) == SET)
1879 rtx dest = SET_DEST (set);
1880 rtx src = SET_SRC (set);
1881 rtx inner_dest = dest;
1884 while (GET_CODE (inner_dest) == STRICT_LOW_PART
1885 || GET_CODE (inner_dest) == SUBREG
1886 || GET_CODE (inner_dest) == ZERO_EXTRACT)
1887 inner_dest = XEXP (inner_dest, 0);
1889 /* Check for the case where I3 modifies its output, as discussed
1890 above. We don't want to prevent pseudos from being combined
1891 into the address of a MEM, so only prevent the combination if
1892 i1 or i2 set the same MEM. */
1893 if ((inner_dest != dest &&
1894 (!MEM_P (inner_dest)
1895 || rtx_equal_p (i2dest, inner_dest)
1896 || (i1dest && rtx_equal_p (i1dest, inner_dest)))
1897 && (reg_overlap_mentioned_p (i2dest, inner_dest)
1898 || (i1dest && reg_overlap_mentioned_p (i1dest, inner_dest))))
1900 /* This is the same test done in can_combine_p except we can't test
1901 all_adjacent; we don't have to, since this instruction will stay
1902 in place, thus we are not considering increasing the lifetime of
1905 Also, if this insn sets a function argument, combining it with
1906 something that might need a spill could clobber a previous
1907 function argument; the all_adjacent test in can_combine_p also
1908 checks this; here, we do a more specific test for this case. */
1910 || (REG_P (inner_dest)
1911 && REGNO (inner_dest) < FIRST_PSEUDO_REGISTER
1912 && (! HARD_REGNO_MODE_OK (REGNO (inner_dest),
1913 GET_MODE (inner_dest))))
1914 || (i1_not_in_src && reg_overlap_mentioned_p (i1dest, src)))
1917 /* If DEST is used in I3, it is being killed in this insn, so
1918 record that for later. We have to consider paradoxical
1919 subregs here, since they kill the whole register, but we
1920 ignore partial subregs, STRICT_LOW_PART, etc.
1921 Never add REG_DEAD notes for the FRAME_POINTER_REGNUM or the
1922 STACK_POINTER_REGNUM, since these are always considered to be
1923 live. Similarly for ARG_POINTER_REGNUM if it is fixed. */
1925 if (GET_CODE (subdest) == SUBREG
1926 && (GET_MODE_SIZE (GET_MODE (subdest))
1927 >= GET_MODE_SIZE (GET_MODE (SUBREG_REG (subdest)))))
1928 subdest = SUBREG_REG (subdest);
1931 && reg_referenced_p (subdest, PATTERN (i3))
1932 && REGNO (subdest) != FRAME_POINTER_REGNUM
1933 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
1934 && REGNO (subdest) != HARD_FRAME_POINTER_REGNUM
1936 #if ARG_POINTER_REGNUM != FRAME_POINTER_REGNUM
1937 && (REGNO (subdest) != ARG_POINTER_REGNUM
1938 || ! fixed_regs [REGNO (subdest)])
1940 && REGNO (subdest) != STACK_POINTER_REGNUM)
1942 if (*pi3dest_killed)
1945 *pi3dest_killed = subdest;
1949 else if (GET_CODE (x) == PARALLEL)
1953 for (i = 0; i < XVECLEN (x, 0); i++)
1954 if (! combinable_i3pat (i3, &XVECEXP (x, 0, i), i2dest, i1dest,
1955 i1_not_in_src, pi3dest_killed))
1962 /* Return 1 if X is an arithmetic expression that contains a multiplication
1963 and division. We don't count multiplications by powers of two here. */
1966 contains_muldiv (rtx x)
1968 switch (GET_CODE (x))
1970 case MOD: case DIV: case UMOD: case UDIV:
1974 return ! (GET_CODE (XEXP (x, 1)) == CONST_INT
1975 && exact_log2 (INTVAL (XEXP (x, 1))) >= 0);
1978 return contains_muldiv (XEXP (x, 0))
1979 || contains_muldiv (XEXP (x, 1));
1982 return contains_muldiv (XEXP (x, 0));
1988 /* Determine whether INSN can be used in a combination. Return nonzero if
1989 not. This is used in try_combine to detect early some cases where we
1990 can't perform combinations. */
1993 cant_combine_insn_p (rtx insn)
1998 /* If this isn't really an insn, we can't do anything.
1999 This can occur when flow deletes an insn that it has merged into an
2000 auto-increment address. */
2001 if (! INSN_P (insn))
2004 /* Never combine loads and stores involving hard regs that are likely
2005 to be spilled. The register allocator can usually handle such
2006 reg-reg moves by tying. If we allow the combiner to make
2007 substitutions of likely-spilled regs, reload might die.
2008 As an exception, we allow combinations involving fixed regs; these are
2009 not available to the register allocator so there's no risk involved. */
2011 set = single_set (insn);
2014 src = SET_SRC (set);
2015 dest = SET_DEST (set);
2016 if (GET_CODE (src) == SUBREG)
2017 src = SUBREG_REG (src);
2018 if (GET_CODE (dest) == SUBREG)
2019 dest = SUBREG_REG (dest);
2020 if (REG_P (src) && REG_P (dest)
2021 && ((REGNO (src) < FIRST_PSEUDO_REGISTER
2022 && ! fixed_regs[REGNO (src)]
2023 && CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (REGNO (src))))
2024 || (REGNO (dest) < FIRST_PSEUDO_REGISTER
2025 && ! fixed_regs[REGNO (dest)]
2026 && CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (REGNO (dest))))))
2032 struct likely_spilled_retval_info
2034 unsigned regno, nregs;
2038 /* Called via note_stores by likely_spilled_retval_p. Remove from info->mask
2039 hard registers that are known to be written to / clobbered in full. */
2041 likely_spilled_retval_1 (rtx x, const_rtx set, void *data)
2043 struct likely_spilled_retval_info *info = data;
2044 unsigned regno, nregs;
2047 if (!REG_P (XEXP (set, 0)))
2050 if (regno >= info->regno + info->nregs)
2052 nregs = hard_regno_nregs[regno][GET_MODE (x)];
2053 if (regno + nregs <= info->regno)
2055 new_mask = (2U << (nregs - 1)) - 1;
2056 if (regno < info->regno)
2057 new_mask >>= info->regno - regno;
2059 new_mask <<= regno - info->regno;
2060 info->mask &= ~new_mask;
2063 /* Return nonzero iff part of the return value is live during INSN, and
2064 it is likely spilled. This can happen when more than one insn is needed
2065 to copy the return value, e.g. when we consider to combine into the
2066 second copy insn for a complex value. */
2069 likely_spilled_retval_p (rtx insn)
2071 rtx use = BB_END (this_basic_block);
2073 unsigned regno, nregs;
2074 /* We assume here that no machine mode needs more than
2075 32 hard registers when the value overlaps with a register
2076 for which FUNCTION_VALUE_REGNO_P is true. */
2078 struct likely_spilled_retval_info info;
2080 if (!NONJUMP_INSN_P (use) || GET_CODE (PATTERN (use)) != USE || insn == use)
2082 reg = XEXP (PATTERN (use), 0);
2083 if (!REG_P (reg) || !FUNCTION_VALUE_REGNO_P (REGNO (reg)))
2085 regno = REGNO (reg);
2086 nregs = hard_regno_nregs[regno][GET_MODE (reg)];
2089 mask = (2U << (nregs - 1)) - 1;
2091 /* Disregard parts of the return value that are set later. */
2095 for (p = PREV_INSN (use); info.mask && p != insn; p = PREV_INSN (p))
2097 note_stores (PATTERN (p), likely_spilled_retval_1, &info);
2100 /* Check if any of the (probably) live return value registers is
2105 if ((mask & 1 << nregs)
2106 && CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (regno + nregs)))
2112 /* Adjust INSN after we made a change to its destination.
2114 Changing the destination can invalidate notes that say something about
2115 the results of the insn and a LOG_LINK pointing to the insn. */
2118 adjust_for_new_dest (rtx insn)
2120 /* For notes, be conservative and simply remove them. */
2121 remove_reg_equal_equiv_notes (insn);
2123 /* The new insn will have a destination that was previously the destination
2124 of an insn just above it. Call distribute_links to make a LOG_LINK from
2125 the next use of that destination. */
2126 distribute_links (gen_rtx_INSN_LIST (VOIDmode, insn, NULL_RTX));
2128 df_insn_rescan (insn);
2131 /* Return TRUE if combine can reuse reg X in mode MODE.
2132 ADDED_SETS is nonzero if the original set is still required. */
2134 can_change_dest_mode (rtx x, int added_sets, enum machine_mode mode)
2142 /* Allow hard registers if the new mode is legal, and occupies no more
2143 registers than the old mode. */
2144 if (regno < FIRST_PSEUDO_REGISTER)
2145 return (HARD_REGNO_MODE_OK (regno, mode)
2146 && (hard_regno_nregs[regno][GET_MODE (x)]
2147 >= hard_regno_nregs[regno][mode]));
2149 /* Or a pseudo that is only used once. */
2150 return (REG_N_SETS (regno) == 1 && !added_sets
2151 && !REG_USERVAR_P (x));
2155 /* Check whether X, the destination of a set, refers to part of
2156 the register specified by REG. */
2159 reg_subword_p (rtx x, rtx reg)
2161 /* Check that reg is an integer mode register. */
2162 if (!REG_P (reg) || GET_MODE_CLASS (GET_MODE (reg)) != MODE_INT)
2165 if (GET_CODE (x) == STRICT_LOW_PART
2166 || GET_CODE (x) == ZERO_EXTRACT)
2169 return GET_CODE (x) == SUBREG
2170 && SUBREG_REG (x) == reg
2171 && GET_MODE_CLASS (GET_MODE (x)) == MODE_INT;
2175 /* Try to combine the insns I1 and I2 into I3.
2176 Here I1 and I2 appear earlier than I3.
2177 I1 can be zero; then we combine just I2 into I3.
2179 If we are combining three insns and the resulting insn is not recognized,
2180 try splitting it into two insns. If that happens, I2 and I3 are retained
2181 and I1 is pseudo-deleted by turning it into a NOTE. Otherwise, I1 and I2
2184 Return 0 if the combination does not work. Then nothing is changed.
2185 If we did the combination, return the insn at which combine should
2188 Set NEW_DIRECT_JUMP_P to a nonzero value if try_combine creates a
2189 new direct jump instruction. */
2192 try_combine (rtx i3, rtx i2, rtx i1, int *new_direct_jump_p)
2194 /* New patterns for I3 and I2, respectively. */
2195 rtx newpat, newi2pat = 0;
2196 rtvec newpat_vec_with_clobbers = 0;
2197 int substed_i2 = 0, substed_i1 = 0;
2198 /* Indicates need to preserve SET in I1 or I2 in I3 if it is not dead. */
2199 int added_sets_1, added_sets_2;
2200 /* Total number of SETs to put into I3. */
2202 /* Nonzero if I2's body now appears in I3. */
2204 /* INSN_CODEs for new I3, new I2, and user of condition code. */
2205 int insn_code_number, i2_code_number = 0, other_code_number = 0;
2206 /* Contains I3 if the destination of I3 is used in its source, which means
2207 that the old life of I3 is being killed. If that usage is placed into
2208 I2 and not in I3, a REG_DEAD note must be made. */
2209 rtx i3dest_killed = 0;
2210 /* SET_DEST and SET_SRC of I2 and I1. */
2211 rtx i2dest, i2src, i1dest = 0, i1src = 0;
2212 /* PATTERN (I1) and PATTERN (I2), or a copy of it in certain cases. */
2213 rtx i1pat = 0, i2pat = 0;
2214 /* Indicates if I2DEST or I1DEST is in I2SRC or I1_SRC. */
2215 int i2dest_in_i2src = 0, i1dest_in_i1src = 0, i2dest_in_i1src = 0;
2216 int i2dest_killed = 0, i1dest_killed = 0;
2217 int i1_feeds_i3 = 0;
2218 /* Notes that must be added to REG_NOTES in I3 and I2. */
2219 rtx new_i3_notes, new_i2_notes;
2220 /* Notes that we substituted I3 into I2 instead of the normal case. */
2221 int i3_subst_into_i2 = 0;
2222 /* Notes that I1, I2 or I3 is a MULT operation. */
2230 rtx new_other_notes;
2233 /* Exit early if one of the insns involved can't be used for
2235 if (cant_combine_insn_p (i3)
2236 || cant_combine_insn_p (i2)
2237 || (i1 && cant_combine_insn_p (i1))
2238 || likely_spilled_retval_p (i3)
2239 /* We also can't do anything if I3 has a
2240 REG_LIBCALL note since we don't want to disrupt the contiguity of a
2243 /* ??? This gives worse code, and appears to be unnecessary, since no
2244 pass after flow uses REG_LIBCALL/REG_RETVAL notes. */
2245 || find_reg_note (i3, REG_LIBCALL, NULL_RTX)
2251 undobuf.other_insn = 0;
2253 /* Reset the hard register usage information. */
2254 CLEAR_HARD_REG_SET (newpat_used_regs);
2256 /* If I1 and I2 both feed I3, they can be in any order. To simplify the
2257 code below, set I1 to be the earlier of the two insns. */
2258 if (i1 && DF_INSN_LUID (i1) > DF_INSN_LUID (i2))
2259 temp = i1, i1 = i2, i2 = temp;
2261 added_links_insn = 0;
2263 /* First check for one important special-case that the code below will
2264 not handle. Namely, the case where I1 is zero, I2 is a PARALLEL
2265 and I3 is a SET whose SET_SRC is a SET_DEST in I2. In that case,
2266 we may be able to replace that destination with the destination of I3.
2267 This occurs in the common code where we compute both a quotient and
2268 remainder into a structure, in which case we want to do the computation
2269 directly into the structure to avoid register-register copies.
2271 Note that this case handles both multiple sets in I2 and also
2272 cases where I2 has a number of CLOBBER or PARALLELs.
2274 We make very conservative checks below and only try to handle the
2275 most common cases of this. For example, we only handle the case
2276 where I2 and I3 are adjacent to avoid making difficult register
2279 if (i1 == 0 && NONJUMP_INSN_P (i3) && GET_CODE (PATTERN (i3)) == SET
2280 && REG_P (SET_SRC (PATTERN (i3)))
2281 && REGNO (SET_SRC (PATTERN (i3))) >= FIRST_PSEUDO_REGISTER
2282 && find_reg_note (i3, REG_DEAD, SET_SRC (PATTERN (i3)))
2283 && GET_CODE (PATTERN (i2)) == PARALLEL
2284 && ! side_effects_p (SET_DEST (PATTERN (i3)))
2285 /* If the dest of I3 is a ZERO_EXTRACT or STRICT_LOW_PART, the code
2286 below would need to check what is inside (and reg_overlap_mentioned_p
2287 doesn't support those codes anyway). Don't allow those destinations;
2288 the resulting insn isn't likely to be recognized anyway. */
2289 && GET_CODE (SET_DEST (PATTERN (i3))) != ZERO_EXTRACT
2290 && GET_CODE (SET_DEST (PATTERN (i3))) != STRICT_LOW_PART
2291 && ! reg_overlap_mentioned_p (SET_SRC (PATTERN (i3)),
2292 SET_DEST (PATTERN (i3)))
2293 && next_real_insn (i2) == i3)
2295 rtx p2 = PATTERN (i2);
2297 /* Make sure that the destination of I3,
2298 which we are going to substitute into one output of I2,
2299 is not used within another output of I2. We must avoid making this:
2300 (parallel [(set (mem (reg 69)) ...)
2301 (set (reg 69) ...)])
2302 which is not well-defined as to order of actions.
2303 (Besides, reload can't handle output reloads for this.)
2305 The problem can also happen if the dest of I3 is a memory ref,
2306 if another dest in I2 is an indirect memory ref. */
2307 for (i = 0; i < XVECLEN (p2, 0); i++)
2308 if ((GET_CODE (XVECEXP (p2, 0, i)) == SET
2309 || GET_CODE (XVECEXP (p2, 0, i)) == CLOBBER)
2310 && reg_overlap_mentioned_p (SET_DEST (PATTERN (i3)),
2311 SET_DEST (XVECEXP (p2, 0, i))))
2314 if (i == XVECLEN (p2, 0))
2315 for (i = 0; i < XVECLEN (p2, 0); i++)
2316 if ((GET_CODE (XVECEXP (p2, 0, i)) == SET
2317 || GET_CODE (XVECEXP (p2, 0, i)) == CLOBBER)
2318 && SET_DEST (XVECEXP (p2, 0, i)) == SET_SRC (PATTERN (i3)))
2323 subst_low_luid = DF_INSN_LUID (i2);
2325 added_sets_2 = added_sets_1 = 0;
2326 i2dest = SET_SRC (PATTERN (i3));
2327 i2dest_killed = dead_or_set_p (i2, i2dest);
2329 /* Replace the dest in I2 with our dest and make the resulting
2330 insn the new pattern for I3. Then skip to where we
2331 validate the pattern. Everything was set up above. */
2332 SUBST (SET_DEST (XVECEXP (p2, 0, i)),
2333 SET_DEST (PATTERN (i3)));
2336 i3_subst_into_i2 = 1;
2337 goto validate_replacement;
2341 /* If I2 is setting a pseudo to a constant and I3 is setting some
2342 sub-part of it to another constant, merge them by making a new
2345 && (temp = single_set (i2)) != 0
2346 && (GET_CODE (SET_SRC (temp)) == CONST_INT
2347 || GET_CODE (SET_SRC (temp)) == CONST_DOUBLE)
2348 && GET_CODE (PATTERN (i3)) == SET
2349 && (GET_CODE (SET_SRC (PATTERN (i3))) == CONST_INT
2350 || GET_CODE (SET_SRC (PATTERN (i3))) == CONST_DOUBLE)
2351 && reg_subword_p (SET_DEST (PATTERN (i3)), SET_DEST (temp)))
2353 rtx dest = SET_DEST (PATTERN (i3));
2357 if (GET_CODE (dest) == ZERO_EXTRACT)
2359 if (GET_CODE (XEXP (dest, 1)) == CONST_INT
2360 && GET_CODE (XEXP (dest, 2)) == CONST_INT)
2362 width = INTVAL (XEXP (dest, 1));
2363 offset = INTVAL (XEXP (dest, 2));
2364 dest = XEXP (dest, 0);
2365 if (BITS_BIG_ENDIAN)
2366 offset = GET_MODE_BITSIZE (GET_MODE (dest)) - width - offset;
2371 if (GET_CODE (dest) == STRICT_LOW_PART)
2372 dest = XEXP (dest, 0);
2373 width = GET_MODE_BITSIZE (GET_MODE (dest));
2379 /* If this is the low part, we're done. */
2380 if (subreg_lowpart_p (dest))
2382 /* Handle the case where inner is twice the size of outer. */
2383 else if (GET_MODE_BITSIZE (GET_MODE (SET_DEST (temp)))
2384 == 2 * GET_MODE_BITSIZE (GET_MODE (dest)))
2385 offset += GET_MODE_BITSIZE (GET_MODE (dest));
2386 /* Otherwise give up for now. */
2392 && (GET_MODE_BITSIZE (GET_MODE (SET_DEST (temp)))
2393 <= HOST_BITS_PER_WIDE_INT * 2))
2395 HOST_WIDE_INT mhi, ohi, ihi;
2396 HOST_WIDE_INT mlo, olo, ilo;
2397 rtx inner = SET_SRC (PATTERN (i3));
2398 rtx outer = SET_SRC (temp);
2400 if (GET_CODE (outer) == CONST_INT)
2402 olo = INTVAL (outer);
2403 ohi = olo < 0 ? -1 : 0;
2407 olo = CONST_DOUBLE_LOW (outer);
2408 ohi = CONST_DOUBLE_HIGH (outer);
2411 if (GET_CODE (inner) == CONST_INT)
2413 ilo = INTVAL (inner);
2414 ihi = ilo < 0 ? -1 : 0;
2418 ilo = CONST_DOUBLE_LOW (inner);
2419 ihi = CONST_DOUBLE_HIGH (inner);
2422 if (width < HOST_BITS_PER_WIDE_INT)
2424 mlo = ((unsigned HOST_WIDE_INT) 1 << width) - 1;
2427 else if (width < HOST_BITS_PER_WIDE_INT * 2)
2429 mhi = ((unsigned HOST_WIDE_INT) 1
2430 << (width - HOST_BITS_PER_WIDE_INT)) - 1;
2442 if (offset >= HOST_BITS_PER_WIDE_INT)
2444 mhi = mlo << (offset - HOST_BITS_PER_WIDE_INT);
2446 ihi = ilo << (offset - HOST_BITS_PER_WIDE_INT);
2449 else if (offset > 0)
2451 mhi = (mhi << offset) | ((unsigned HOST_WIDE_INT) mlo
2452 >> (HOST_BITS_PER_WIDE_INT - offset));
2453 mlo = mlo << offset;
2454 ihi = (ihi << offset) | ((unsigned HOST_WIDE_INT) ilo
2455 >> (HOST_BITS_PER_WIDE_INT - offset));
2456 ilo = ilo << offset;
2459 olo = (olo & ~mlo) | ilo;
2460 ohi = (ohi & ~mhi) | ihi;
2464 subst_low_luid = DF_INSN_LUID (i2);
2465 added_sets_2 = added_sets_1 = 0;
2466 i2dest = SET_DEST (temp);
2467 i2dest_killed = dead_or_set_p (i2, i2dest);
2469 SUBST (SET_SRC (temp),
2470 immed_double_const (olo, ohi, GET_MODE (SET_DEST (temp))));
2472 newpat = PATTERN (i2);
2473 goto validate_replacement;
2478 /* If we have no I1 and I2 looks like:
2479 (parallel [(set (reg:CC X) (compare:CC OP (const_int 0)))
2481 make up a dummy I1 that is
2484 (set (reg:CC X) (compare:CC Y (const_int 0)))
2486 (We can ignore any trailing CLOBBERs.)
2488 This undoes a previous combination and allows us to match a branch-and-
2491 if (i1 == 0 && GET_CODE (PATTERN (i2)) == PARALLEL
2492 && XVECLEN (PATTERN (i2), 0) >= 2
2493 && GET_CODE (XVECEXP (PATTERN (i2), 0, 0)) == SET
2494 && (GET_MODE_CLASS (GET_MODE (SET_DEST (XVECEXP (PATTERN (i2), 0, 0))))
2496 && GET_CODE (SET_SRC (XVECEXP (PATTERN (i2), 0, 0))) == COMPARE
2497 && XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 1) == const0_rtx
2498 && GET_CODE (XVECEXP (PATTERN (i2), 0, 1)) == SET
2499 && REG_P (SET_DEST (XVECEXP (PATTERN (i2), 0, 1)))
2500 && rtx_equal_p (XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 0),
2501 SET_SRC (XVECEXP (PATTERN (i2), 0, 1))))
2503 for (i = XVECLEN (PATTERN (i2), 0) - 1; i >= 2; i--)
2504 if (GET_CODE (XVECEXP (PATTERN (i2), 0, i)) != CLOBBER)
2509 /* We make I1 with the same INSN_UID as I2. This gives it
2510 the same DF_INSN_LUID for value tracking. Our fake I1 will
2511 never appear in the insn stream so giving it the same INSN_UID
2512 as I2 will not cause a problem. */
2514 i1 = gen_rtx_INSN (VOIDmode, INSN_UID (i2), NULL_RTX, i2,
2515 BLOCK_FOR_INSN (i2), INSN_LOCATOR (i2),
2516 XVECEXP (PATTERN (i2), 0, 1), -1, NULL_RTX);
2518 SUBST (PATTERN (i2), XVECEXP (PATTERN (i2), 0, 0));
2519 SUBST (XEXP (SET_SRC (PATTERN (i2)), 0),
2520 SET_DEST (PATTERN (i1)));
2525 /* Verify that I2 and I1 are valid for combining. */
2526 if (! can_combine_p (i2, i3, i1, NULL_RTX, &i2dest, &i2src)
2527 || (i1 && ! can_combine_p (i1, i3, NULL_RTX, i2, &i1dest, &i1src)))
2533 /* Record whether I2DEST is used in I2SRC and similarly for the other
2534 cases. Knowing this will help in register status updating below. */
2535 i2dest_in_i2src = reg_overlap_mentioned_p (i2dest, i2src);
2536 i1dest_in_i1src = i1 && reg_overlap_mentioned_p (i1dest, i1src);
2537 i2dest_in_i1src = i1 && reg_overlap_mentioned_p (i2dest, i1src);
2538 i2dest_killed = dead_or_set_p (i2, i2dest);
2539 i1dest_killed = i1 && dead_or_set_p (i1, i1dest);
2541 /* See if I1 directly feeds into I3. It does if I1DEST is not used
2543 i1_feeds_i3 = i1 && ! reg_overlap_mentioned_p (i1dest, i2src);
2545 /* Ensure that I3's pattern can be the destination of combines. */
2546 if (! combinable_i3pat (i3, &PATTERN (i3), i2dest, i1dest,
2547 i1 && i2dest_in_i1src && i1_feeds_i3,
2554 /* See if any of the insns is a MULT operation. Unless one is, we will
2555 reject a combination that is, since it must be slower. Be conservative
2557 if (GET_CODE (i2src) == MULT
2558 || (i1 != 0 && GET_CODE (i1src) == MULT)
2559 || (GET_CODE (PATTERN (i3)) == SET
2560 && GET_CODE (SET_SRC (PATTERN (i3))) == MULT))
2563 /* If I3 has an inc, then give up if I1 or I2 uses the reg that is inc'd.
2564 We used to do this EXCEPT in one case: I3 has a post-inc in an
2565 output operand. However, that exception can give rise to insns like
2567 which is a famous insn on the PDP-11 where the value of r3 used as the
2568 source was model-dependent. Avoid this sort of thing. */
2571 if (!(GET_CODE (PATTERN (i3)) == SET
2572 && REG_P (SET_SRC (PATTERN (i3)))
2573 && MEM_P (SET_DEST (PATTERN (i3)))
2574 && (GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_INC
2575 || GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_DEC)))
2576 /* It's not the exception. */
2579 for (link = REG_NOTES (i3); link; link = XEXP (link, 1))
2580 if (REG_NOTE_KIND (link) == REG_INC
2581 && (reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i2))
2583 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i1)))))
2590 /* See if the SETs in I1 or I2 need to be kept around in the merged
2591 instruction: whenever the value set there is still needed past I3.
2592 For the SETs in I2, this is easy: we see if I2DEST dies or is set in I3.
2594 For the SET in I1, we have two cases: If I1 and I2 independently
2595 feed into I3, the set in I1 needs to be kept around if I1DEST dies
2596 or is set in I3. Otherwise (if I1 feeds I2 which feeds I3), the set
2597 in I1 needs to be kept around unless I1DEST dies or is set in either
2598 I2 or I3. We can distinguish these cases by seeing if I2SRC mentions
2599 I1DEST. If so, we know I1 feeds into I2. */
2601 added_sets_2 = ! dead_or_set_p (i3, i2dest);
2604 = i1 && ! (i1_feeds_i3 ? dead_or_set_p (i3, i1dest)
2605 : (dead_or_set_p (i3, i1dest) || dead_or_set_p (i2, i1dest)));
2607 /* If the set in I2 needs to be kept around, we must make a copy of
2608 PATTERN (I2), so that when we substitute I1SRC for I1DEST in
2609 PATTERN (I2), we are only substituting for the original I1DEST, not into
2610 an already-substituted copy. This also prevents making self-referential
2611 rtx. If I2 is a PARALLEL, we just need the piece that assigns I2SRC to
2616 if (GET_CODE (PATTERN (i2)) == PARALLEL)
2617 i2pat = gen_rtx_SET (VOIDmode, i2dest, copy_rtx (i2src));
2619 i2pat = copy_rtx (PATTERN (i2));
2624 if (GET_CODE (PATTERN (i1)) == PARALLEL)
2625 i1pat = gen_rtx_SET (VOIDmode, i1dest, copy_rtx (i1src));
2627 i1pat = copy_rtx (PATTERN (i1));
2632 /* Substitute in the latest insn for the regs set by the earlier ones. */
2634 maxreg = max_reg_num ();
2639 /* Many machines that don't use CC0 have insns that can both perform an
2640 arithmetic operation and set the condition code. These operations will
2641 be represented as a PARALLEL with the first element of the vector
2642 being a COMPARE of an arithmetic operation with the constant zero.
2643 The second element of the vector will set some pseudo to the result
2644 of the same arithmetic operation. If we simplify the COMPARE, we won't
2645 match such a pattern and so will generate an extra insn. Here we test
2646 for this case, where both the comparison and the operation result are
2647 needed, and make the PARALLEL by just replacing I2DEST in I3SRC with
2648 I2SRC. Later we will make the PARALLEL that contains I2. */
2650 if (i1 == 0 && added_sets_2 && GET_CODE (PATTERN (i3)) == SET
2651 && GET_CODE (SET_SRC (PATTERN (i3))) == COMPARE
2652 && XEXP (SET_SRC (PATTERN (i3)), 1) == const0_rtx
2653 && rtx_equal_p (XEXP (SET_SRC (PATTERN (i3)), 0), i2dest))
2655 #ifdef SELECT_CC_MODE
2657 enum machine_mode compare_mode;
2660 newpat = PATTERN (i3);
2661 SUBST (XEXP (SET_SRC (newpat), 0), i2src);
2665 #ifdef SELECT_CC_MODE
2666 /* See if a COMPARE with the operand we substituted in should be done
2667 with the mode that is currently being used. If not, do the same
2668 processing we do in `subst' for a SET; namely, if the destination
2669 is used only once, try to replace it with a register of the proper
2670 mode and also replace the COMPARE. */
2671 if (undobuf.other_insn == 0
2672 && (cc_use = find_single_use (SET_DEST (newpat), i3,
2673 &undobuf.other_insn))
2674 && ((compare_mode = SELECT_CC_MODE (GET_CODE (*cc_use),
2676 != GET_MODE (SET_DEST (newpat))))
2678 if (can_change_dest_mode(SET_DEST (newpat), added_sets_2,
2681 unsigned int regno = REGNO (SET_DEST (newpat));
2684 if (regno < FIRST_PSEUDO_REGISTER)
2685 new_dest = gen_rtx_REG (compare_mode, regno);
2688 SUBST_MODE (regno_reg_rtx[regno], compare_mode);
2689 new_dest = regno_reg_rtx[regno];
2692 SUBST (SET_DEST (newpat), new_dest);
2693 SUBST (XEXP (*cc_use, 0), new_dest);
2694 SUBST (SET_SRC (newpat),
2695 gen_rtx_COMPARE (compare_mode, i2src, const0_rtx));
2698 undobuf.other_insn = 0;
2705 /* It is possible that the source of I2 or I1 may be performing
2706 an unneeded operation, such as a ZERO_EXTEND of something
2707 that is known to have the high part zero. Handle that case
2708 by letting subst look at the innermost one of them.
2710 Another way to do this would be to have a function that tries
2711 to simplify a single insn instead of merging two or more
2712 insns. We don't do this because of the potential of infinite
2713 loops and because of the potential extra memory required.
2714 However, doing it the way we are is a bit of a kludge and
2715 doesn't catch all cases.
2717 But only do this if -fexpensive-optimizations since it slows
2718 things down and doesn't usually win.
2720 This is not done in the COMPARE case above because the
2721 unmodified I2PAT is used in the PARALLEL and so a pattern
2722 with a modified I2SRC would not match. */
2724 if (flag_expensive_optimizations)
2726 /* Pass pc_rtx so no substitutions are done, just
2730 subst_low_luid = DF_INSN_LUID (i1);
2731 i1src = subst (i1src, pc_rtx, pc_rtx, 0, 0);
2735 subst_low_luid = DF_INSN_LUID (i2);
2736 i2src = subst (i2src, pc_rtx, pc_rtx, 0, 0);
2740 n_occurrences = 0; /* `subst' counts here */
2742 /* If I1 feeds into I2 (not into I3) and I1DEST is in I1SRC, we
2743 need to make a unique copy of I2SRC each time we substitute it
2744 to avoid self-referential rtl. */
2746 subst_low_luid = DF_INSN_LUID (i2);
2747 newpat = subst (PATTERN (i3), i2dest, i2src, 0,
2748 ! i1_feeds_i3 && i1dest_in_i1src);
2751 /* Record whether i2's body now appears within i3's body. */
2752 i2_is_used = n_occurrences;
2755 /* If we already got a failure, don't try to do more. Otherwise,
2756 try to substitute in I1 if we have it. */
2758 if (i1 && GET_CODE (newpat) != CLOBBER)
2760 /* Check that an autoincrement side-effect on I1 has not been lost.
2761 This happens if I1DEST is mentioned in I2 and dies there, and
2762 has disappeared from the new pattern. */
2763 if ((FIND_REG_INC_NOTE (i1, NULL_RTX) != 0
2765 && dead_or_set_p (i2, i1dest)
2766 && !reg_overlap_mentioned_p (i1dest, newpat))
2767 /* Before we can do this substitution, we must redo the test done
2768 above (see detailed comments there) that ensures that I1DEST
2769 isn't mentioned in any SETs in NEWPAT that are field assignments. */
2770 || !combinable_i3pat (NULL_RTX, &newpat, i1dest, NULL_RTX, 0, 0))
2777 subst_low_luid = DF_INSN_LUID (i1);
2778 newpat = subst (newpat, i1dest, i1src, 0, 0);
2782 /* Fail if an autoincrement side-effect has been duplicated. Be careful
2783 to count all the ways that I2SRC and I1SRC can be used. */
2784 if ((FIND_REG_INC_NOTE (i2, NULL_RTX) != 0
2785 && i2_is_used + added_sets_2 > 1)
2786 || (i1 != 0 && FIND_REG_INC_NOTE (i1, NULL_RTX) != 0
2787 && (n_occurrences + added_sets_1 + (added_sets_2 && ! i1_feeds_i3)
2789 /* Fail if we tried to make a new register. */
2790 || max_reg_num () != maxreg
2791 /* Fail if we couldn't do something and have a CLOBBER. */
2792 || GET_CODE (newpat) == CLOBBER
2793 /* Fail if this new pattern is a MULT and we didn't have one before
2794 at the outer level. */
2795 || (GET_CODE (newpat) == SET && GET_CODE (SET_SRC (newpat)) == MULT
2802 /* If the actions of the earlier insns must be kept
2803 in addition to substituting them into the latest one,
2804 we must make a new PARALLEL for the latest insn
2805 to hold additional the SETs. */
2807 if (added_sets_1 || added_sets_2)
2811 if (GET_CODE (newpat) == PARALLEL)
2813 rtvec old = XVEC (newpat, 0);
2814 total_sets = XVECLEN (newpat, 0) + added_sets_1 + added_sets_2;
2815 newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (total_sets));
2816 memcpy (XVEC (newpat, 0)->elem, &old->elem[0],
2817 sizeof (old->elem[0]) * old->num_elem);
2822 total_sets = 1 + added_sets_1 + added_sets_2;
2823 newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (total_sets));
2824 XVECEXP (newpat, 0, 0) = old;
2828 XVECEXP (newpat, 0, --total_sets) = i1pat;
2832 /* If there is no I1, use I2's body as is. We used to also not do
2833 the subst call below if I2 was substituted into I3,
2834 but that could lose a simplification. */
2836 XVECEXP (newpat, 0, --total_sets) = i2pat;
2838 /* See comment where i2pat is assigned. */
2839 XVECEXP (newpat, 0, --total_sets)
2840 = subst (i2pat, i1dest, i1src, 0, 0);
2844 /* We come here when we are replacing a destination in I2 with the
2845 destination of I3. */
2846 validate_replacement:
2848 /* Note which hard regs this insn has as inputs. */
2849 mark_used_regs_combine (newpat);
2851 /* If recog_for_combine fails, it strips existing clobbers. If we'll
2852 consider splitting this pattern, we might need these clobbers. */
2853 if (i1 && GET_CODE (newpat) == PARALLEL
2854 && GET_CODE (XVECEXP (newpat, 0, XVECLEN (newpat, 0) - 1)) == CLOBBER)
2856 int len = XVECLEN (newpat, 0);
2858 newpat_vec_with_clobbers = rtvec_alloc (len);
2859 for (i = 0; i < len; i++)
2860 RTVEC_ELT (newpat_vec_with_clobbers, i) = XVECEXP (newpat, 0, i);
2863 /* Is the result of combination a valid instruction? */
2864 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2866 /* If the result isn't valid, see if it is a PARALLEL of two SETs where
2867 the second SET's destination is a register that is unused and isn't
2868 marked as an instruction that might trap in an EH region. In that case,
2869 we just need the first SET. This can occur when simplifying a divmod
2870 insn. We *must* test for this case here because the code below that
2871 splits two independent SETs doesn't handle this case correctly when it
2872 updates the register status.
2874 It's pointless doing this if we originally had two sets, one from
2875 i3, and one from i2. Combining then splitting the parallel results
2876 in the original i2 again plus an invalid insn (which we delete).
2877 The net effect is only to move instructions around, which makes
2878 debug info less accurate.
2880 Also check the case where the first SET's destination is unused.
2881 That would not cause incorrect code, but does cause an unneeded
2884 if (insn_code_number < 0
2885 && !(added_sets_2 && i1 == 0)
2886 && GET_CODE (newpat) == PARALLEL
2887 && XVECLEN (newpat, 0) == 2
2888 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
2889 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
2890 && asm_noperands (newpat) < 0)
2892 rtx set0 = XVECEXP (newpat, 0, 0);
2893 rtx set1 = XVECEXP (newpat, 0, 1);
2896 if (((REG_P (SET_DEST (set1))
2897 && find_reg_note (i3, REG_UNUSED, SET_DEST (set1)))
2898 || (GET_CODE (SET_DEST (set1)) == SUBREG
2899 && find_reg_note (i3, REG_UNUSED, SUBREG_REG (SET_DEST (set1)))))
2900 && (!(note = find_reg_note (i3, REG_EH_REGION, NULL_RTX))
2901 || INTVAL (XEXP (note, 0)) <= 0)
2902 && ! side_effects_p (SET_SRC (set1)))
2905 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2908 else if (((REG_P (SET_DEST (set0))
2909 && find_reg_note (i3, REG_UNUSED, SET_DEST (set0)))
2910 || (GET_CODE (SET_DEST (set0)) == SUBREG
2911 && find_reg_note (i3, REG_UNUSED,
2912 SUBREG_REG (SET_DEST (set0)))))
2913 && (!(note = find_reg_note (i3, REG_EH_REGION, NULL_RTX))
2914 || INTVAL (XEXP (note, 0)) <= 0)
2915 && ! side_effects_p (SET_SRC (set0)))
2918 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2920 if (insn_code_number >= 0)
2922 /* If we will be able to accept this, we have made a
2923 change to the destination of I3. This requires us to
2924 do a few adjustments. */
2926 PATTERN (i3) = newpat;
2927 adjust_for_new_dest (i3);
2932 /* If we were combining three insns and the result is a simple SET
2933 with no ASM_OPERANDS that wasn't recognized, try to split it into two
2934 insns. There are two ways to do this. It can be split using a
2935 machine-specific method (like when you have an addition of a large
2936 constant) or by combine in the function find_split_point. */
2938 if (i1 && insn_code_number < 0 && GET_CODE (newpat) == SET
2939 && asm_noperands (newpat) < 0)
2941 rtx parallel, m_split, *split;
2943 /* See if the MD file can split NEWPAT. If it can't, see if letting it
2944 use I2DEST as a scratch register will help. In the latter case,
2945 convert I2DEST to the mode of the source of NEWPAT if we can. */
2947 m_split = combine_split_insns (newpat, i3);
2949 /* We can only use I2DEST as a scratch reg if it doesn't overlap any
2950 inputs of NEWPAT. */
2952 /* ??? If I2DEST is not safe, and I1DEST exists, then it would be
2953 possible to try that as a scratch reg. This would require adding
2954 more code to make it work though. */
2956 if (m_split == 0 && ! reg_overlap_mentioned_p (i2dest, newpat))
2958 enum machine_mode new_mode = GET_MODE (SET_DEST (newpat));
2960 /* First try to split using the original register as a
2961 scratch register. */
2962 parallel = gen_rtx_PARALLEL (VOIDmode,
2963 gen_rtvec (2, newpat,
2964 gen_rtx_CLOBBER (VOIDmode,
2966 m_split = combine_split_insns (parallel, i3);
2968 /* If that didn't work, try changing the mode of I2DEST if
2971 && new_mode != GET_MODE (i2dest)
2972 && new_mode != VOIDmode
2973 && can_change_dest_mode (i2dest, added_sets_2, new_mode))
2975 enum machine_mode old_mode = GET_MODE (i2dest);
2978 if (REGNO (i2dest) < FIRST_PSEUDO_REGISTER)
2979 ni2dest = gen_rtx_REG (new_mode, REGNO (i2dest));
2982 SUBST_MODE (regno_reg_rtx[REGNO (i2dest)], new_mode);
2983 ni2dest = regno_reg_rtx[REGNO (i2dest)];
2986 parallel = (gen_rtx_PARALLEL
2988 gen_rtvec (2, newpat,
2989 gen_rtx_CLOBBER (VOIDmode,
2991 m_split = combine_split_insns (parallel, i3);
2994 && REGNO (i2dest) >= FIRST_PSEUDO_REGISTER)
2998 adjust_reg_mode (regno_reg_rtx[REGNO (i2dest)], old_mode);
2999 buf = undobuf.undos;
3000 undobuf.undos = buf->next;
3001 buf->next = undobuf.frees;
3002 undobuf.frees = buf;
3007 /* If recog_for_combine has discarded clobbers, try to use them
3008 again for the split. */
3009 if (m_split == 0 && newpat_vec_with_clobbers)
3011 parallel = gen_rtx_PARALLEL (VOIDmode, newpat_vec_with_clobbers);
3012 m_split = combine_split_insns (parallel, i3);
3015 if (m_split && NEXT_INSN (m_split) == NULL_RTX)
3017 m_split = PATTERN (m_split);
3018 insn_code_number = recog_for_combine (&m_split, i3, &new_i3_notes);
3019 if (insn_code_number >= 0)
3022 else if (m_split && NEXT_INSN (NEXT_INSN (m_split)) == NULL_RTX
3023 && (next_real_insn (i2) == i3
3024 || ! use_crosses_set_p (PATTERN (m_split), DF_INSN_LUID (i2))))
3027 rtx newi3pat = PATTERN (NEXT_INSN (m_split));
3028 newi2pat = PATTERN (m_split);
3030 i3set = single_set (NEXT_INSN (m_split));
3031 i2set = single_set (m_split);
3033 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
3035 /* If I2 or I3 has multiple SETs, we won't know how to track
3036 register status, so don't use these insns. If I2's destination
3037 is used between I2 and I3, we also can't use these insns. */
3039 if (i2_code_number >= 0 && i2set && i3set
3040 && (next_real_insn (i2) == i3
3041 || ! reg_used_between_p (SET_DEST (i2set), i2, i3)))
3042 insn_code_number = recog_for_combine (&newi3pat, i3,
3044 if (insn_code_number >= 0)
3047 /* It is possible that both insns now set the destination of I3.
3048 If so, we must show an extra use of it. */
3050 if (insn_code_number >= 0)
3052 rtx new_i3_dest = SET_DEST (i3set);
3053 rtx new_i2_dest = SET_DEST (i2set);
3055 while (GET_CODE (new_i3_dest) == ZERO_EXTRACT
3056 || GET_CODE (new_i3_dest) == STRICT_LOW_PART
3057 || GET_CODE (new_i3_dest) == SUBREG)
3058 new_i3_dest = XEXP (new_i3_dest, 0);
3060 while (GET_CODE (new_i2_dest) == ZERO_EXTRACT
3061 || GET_CODE (new_i2_dest) == STRICT_LOW_PART
3062 || GET_CODE (new_i2_dest) == SUBREG)
3063 new_i2_dest = XEXP (new_i2_dest, 0);
3065 if (REG_P (new_i3_dest)
3066 && REG_P (new_i2_dest)
3067 && REGNO (new_i3_dest) == REGNO (new_i2_dest))
3068 INC_REG_N_SETS (REGNO (new_i2_dest), 1);
3072 /* If we can split it and use I2DEST, go ahead and see if that
3073 helps things be recognized. Verify that none of the registers
3074 are set between I2 and I3. */
3075 if (insn_code_number < 0 && (split = find_split_point (&newpat, i3)) != 0
3079 /* We need I2DEST in the proper mode. If it is a hard register
3080 or the only use of a pseudo, we can change its mode.
3081 Make sure we don't change a hard register to have a mode that
3082 isn't valid for it, or change the number of registers. */
3083 && (GET_MODE (*split) == GET_MODE (i2dest)
3084 || GET_MODE (*split) == VOIDmode
3085 || can_change_dest_mode (i2dest, added_sets_2,
3087 && (next_real_insn (i2) == i3
3088 || ! use_crosses_set_p (*split, DF_INSN_LUID (i2)))
3089 /* We can't overwrite I2DEST if its value is still used by
3091 && ! reg_referenced_p (i2dest, newpat))
3093 rtx newdest = i2dest;
3094 enum rtx_code split_code = GET_CODE (*split);
3095 enum machine_mode split_mode = GET_MODE (*split);
3096 bool subst_done = false;
3097 newi2pat = NULL_RTX;
3099 /* Get NEWDEST as a register in the proper mode. We have already
3100 validated that we can do this. */
3101 if (GET_MODE (i2dest) != split_mode && split_mode != VOIDmode)
3103 if (REGNO (i2dest) < FIRST_PSEUDO_REGISTER)
3104 newdest = gen_rtx_REG (split_mode, REGNO (i2dest));
3107 SUBST_MODE (regno_reg_rtx[REGNO (i2dest)], split_mode);
3108 newdest = regno_reg_rtx[REGNO (i2dest)];
3112 /* If *SPLIT is a (mult FOO (const_int pow2)), convert it to
3113 an ASHIFT. This can occur if it was inside a PLUS and hence
3114 appeared to be a memory address. This is a kludge. */
3115 if (split_code == MULT
3116 && GET_CODE (XEXP (*split, 1)) == CONST_INT
3117 && INTVAL (XEXP (*split, 1)) > 0
3118 && (i = exact_log2 (INTVAL (XEXP (*split, 1)))) >= 0)
3120 SUBST (*split, gen_rtx_ASHIFT (split_mode,
3121 XEXP (*split, 0), GEN_INT (i)));
3122 /* Update split_code because we may not have a multiply
3124 split_code = GET_CODE (*split);
3127 #ifdef INSN_SCHEDULING
3128 /* If *SPLIT is a paradoxical SUBREG, when we split it, it should
3129 be written as a ZERO_EXTEND. */
3130 if (split_code == SUBREG && MEM_P (SUBREG_REG (*split)))
3132 #ifdef LOAD_EXTEND_OP
3133 /* Or as a SIGN_EXTEND if LOAD_EXTEND_OP says that that's
3134 what it really is. */
3135 if (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (*split)))
3137 SUBST (*split, gen_rtx_SIGN_EXTEND (split_mode,
3138 SUBREG_REG (*split)));
3141 SUBST (*split, gen_rtx_ZERO_EXTEND (split_mode,
3142 SUBREG_REG (*split)));
3146 /* Attempt to split binary operators using arithmetic identities. */
3147 if (BINARY_P (SET_SRC (newpat))
3148 && split_mode == GET_MODE (SET_SRC (newpat))
3149 && ! side_effects_p (SET_SRC (newpat)))
3151 rtx setsrc = SET_SRC (newpat);
3152 enum machine_mode mode = GET_MODE (setsrc);
3153 enum rtx_code code = GET_CODE (setsrc);
3154 rtx src_op0 = XEXP (setsrc, 0);
3155 rtx src_op1 = XEXP (setsrc, 1);
3157 /* Split "X = Y op Y" as "Z = Y; X = Z op Z". */
3158 if (rtx_equal_p (src_op0, src_op1))
3160 newi2pat = gen_rtx_SET (VOIDmode, newdest, src_op0);
3161 SUBST (XEXP (setsrc, 0), newdest);
3162 SUBST (XEXP (setsrc, 1), newdest);
3165 /* Split "((P op Q) op R) op S" where op is PLUS or MULT. */
3166 else if ((code == PLUS || code == MULT)
3167 && GET_CODE (src_op0) == code
3168 && GET_CODE (XEXP (src_op0, 0)) == code
3169 && (INTEGRAL_MODE_P (mode)
3170 || (FLOAT_MODE_P (mode)
3171 && flag_unsafe_math_optimizations)))
3173 rtx p = XEXP (XEXP (src_op0, 0), 0);
3174 rtx q = XEXP (XEXP (src_op0, 0), 1);
3175 rtx r = XEXP (src_op0, 1);
3178 /* Split both "((X op Y) op X) op Y" and
3179 "((X op Y) op Y) op X" as "T op T" where T is
3181 if ((rtx_equal_p (p,r) && rtx_equal_p (q,s))
3182 || (rtx_equal_p (p,s) && rtx_equal_p (q,r)))
3184 newi2pat = gen_rtx_SET (VOIDmode, newdest,
3186 SUBST (XEXP (setsrc, 0), newdest);
3187 SUBST (XEXP (setsrc, 1), newdest);
3190 /* Split "((X op X) op Y) op Y)" as "T op T" where
3192 else if (rtx_equal_p (p,q) && rtx_equal_p (r,s))
3194 rtx tmp = simplify_gen_binary (code, mode, p, r);
3195 newi2pat = gen_rtx_SET (VOIDmode, newdest, tmp);
3196 SUBST (XEXP (setsrc, 0), newdest);
3197 SUBST (XEXP (setsrc, 1), newdest);
3205 newi2pat = gen_rtx_SET (VOIDmode, newdest, *split);
3206 SUBST (*split, newdest);
3209 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
3211 /* recog_for_combine might have added CLOBBERs to newi2pat.
3212 Make sure NEWPAT does not depend on the clobbered regs. */
3213 if (GET_CODE (newi2pat) == PARALLEL)
3214 for (i = XVECLEN (newi2pat, 0) - 1; i >= 0; i--)
3215 if (GET_CODE (XVECEXP (newi2pat, 0, i)) == CLOBBER)
3217 rtx reg = XEXP (XVECEXP (newi2pat, 0, i), 0);
3218 if (reg_overlap_mentioned_p (reg, newpat))
3225 /* If the split point was a MULT and we didn't have one before,
3226 don't use one now. */
3227 if (i2_code_number >= 0 && ! (split_code == MULT && ! have_mult))
3228 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
3232 /* Check for a case where we loaded from memory in a narrow mode and
3233 then sign extended it, but we need both registers. In that case,
3234 we have a PARALLEL with both loads from the same memory location.
3235 We can split this into a load from memory followed by a register-register
3236 copy. This saves at least one insn, more if register allocation can
3239 We cannot do this if the destination of the first assignment is a
3240 condition code register or cc0. We eliminate this case by making sure
3241 the SET_DEST and SET_SRC have the same mode.
3243 We cannot do this if the destination of the second assignment is
3244 a register that we have already assumed is zero-extended. Similarly
3245 for a SUBREG of such a register. */
3247 else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0
3248 && GET_CODE (newpat) == PARALLEL
3249 && XVECLEN (newpat, 0) == 2
3250 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
3251 && GET_CODE (SET_SRC (XVECEXP (newpat, 0, 0))) == SIGN_EXTEND
3252 && (GET_MODE (SET_DEST (XVECEXP (newpat, 0, 0)))
3253 == GET_MODE (SET_SRC (XVECEXP (newpat, 0, 0))))
3254 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
3255 && rtx_equal_p (SET_SRC (XVECEXP (newpat, 0, 1)),
3256 XEXP (SET_SRC (XVECEXP (newpat, 0, 0)), 0))
3257 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)),
3259 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
3260 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
3261 && ! (temp = SET_DEST (XVECEXP (newpat, 0, 1)),
3263 && VEC_index (reg_stat_type, reg_stat,
3264 REGNO (temp))->nonzero_bits != 0
3265 && GET_MODE_BITSIZE (GET_MODE (temp)) < BITS_PER_WORD
3266 && GET_MODE_BITSIZE (GET_MODE (temp)) < HOST_BITS_PER_INT
3267 && (VEC_index (reg_stat_type, reg_stat,
3268 REGNO (temp))->nonzero_bits
3269 != GET_MODE_MASK (word_mode))))
3270 && ! (GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) == SUBREG
3271 && (temp = SUBREG_REG (SET_DEST (XVECEXP (newpat, 0, 1))),
3273 && VEC_index (reg_stat_type, reg_stat,
3274 REGNO (temp))->nonzero_bits != 0
3275 && GET_MODE_BITSIZE (GET_MODE (temp)) < BITS_PER_WORD
3276 && GET_MODE_BITSIZE (GET_MODE (temp)) < HOST_BITS_PER_INT
3277 && (VEC_index (reg_stat_type, reg_stat,
3278 REGNO (temp))->nonzero_bits
3279 != GET_MODE_MASK (word_mode)))))
3280 && ! reg_overlap_mentioned_p (SET_DEST (XVECEXP (newpat, 0, 1)),
3281 SET_SRC (XVECEXP (newpat, 0, 1)))
3282 && ! find_reg_note (i3, REG_UNUSED,
3283 SET_DEST (XVECEXP (newpat, 0, 0))))
3287 newi2pat = XVECEXP (newpat, 0, 0);
3288 ni2dest = SET_DEST (XVECEXP (newpat, 0, 0));
3289 newpat = XVECEXP (newpat, 0, 1);
3290 SUBST (SET_SRC (newpat),
3291 gen_lowpart (GET_MODE (SET_SRC (newpat)), ni2dest));
3292 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
3294 if (i2_code_number >= 0)
3295 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
3297 if (insn_code_number >= 0)
3301 /* Similarly, check for a case where we have a PARALLEL of two independent
3302 SETs but we started with three insns. In this case, we can do the sets
3303 as two separate insns. This case occurs when some SET allows two
3304 other insns to combine, but the destination of that SET is still live. */
3306 else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0
3307 && GET_CODE (newpat) == PARALLEL
3308 && XVECLEN (newpat, 0) == 2
3309 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
3310 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != ZERO_EXTRACT
3311 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != STRICT_LOW_PART
3312 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
3313 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
3314 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
3315 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)),
3317 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 1)),
3318 XVECEXP (newpat, 0, 0))
3319 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 0)),
3320 XVECEXP (newpat, 0, 1))
3321 && ! (contains_muldiv (SET_SRC (XVECEXP (newpat, 0, 0)))
3322 && contains_muldiv (SET_SRC (XVECEXP (newpat, 0, 1))))
3324 /* We cannot split the parallel into two sets if both sets
3326 && ! (reg_referenced_p (cc0_rtx, XVECEXP (newpat, 0, 0))
3327 && reg_referenced_p (cc0_rtx, XVECEXP (newpat, 0, 1)))
3331 /* Normally, it doesn't matter which of the two is done first,
3332 but it does if one references cc0. In that case, it has to
3335 if (reg_referenced_p (cc0_rtx, XVECEXP (newpat, 0, 0)))
3337 newi2pat = XVECEXP (newpat, 0, 0);
3338 newpat = XVECEXP (newpat, 0, 1);
3343 newi2pat = XVECEXP (newpat, 0, 1);
3344 newpat = XVECEXP (newpat, 0, 0);
3347 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
3349 if (i2_code_number >= 0)
3350 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
3353 /* If it still isn't recognized, fail and change things back the way they
3355 if ((insn_code_number < 0
3356 /* Is the result a reasonable ASM_OPERANDS? */
3357 && (! check_asm_operands (newpat) || added_sets_1 || added_sets_2)))
3363 /* If we had to change another insn, make sure it is valid also. */
3364 if (undobuf.other_insn)
3366 CLEAR_HARD_REG_SET (newpat_used_regs);
3368 other_pat = PATTERN (undobuf.other_insn);
3369 other_code_number = recog_for_combine (&other_pat, undobuf.other_insn,
3372 if (other_code_number < 0 && ! check_asm_operands (other_pat))
3380 /* If I2 is the CC0 setter and I3 is the CC0 user then check whether
3381 they are adjacent to each other or not. */
3383 rtx p = prev_nonnote_insn (i3);
3384 if (p && p != i2 && NONJUMP_INSN_P (p) && newi2pat
3385 && sets_cc0_p (newi2pat))
3393 /* Only allow this combination if insn_rtx_costs reports that the
3394 replacement instructions are cheaper than the originals. */
3395 if (!combine_validate_cost (i1, i2, i3, newpat, newi2pat, other_pat))
3401 /* We now know that we can do this combination. Merge the insns and
3402 update the status of registers and LOG_LINKS. */
3404 if (undobuf.other_insn)
3408 PATTERN (undobuf.other_insn) = other_pat;
3410 /* If any of the notes in OTHER_INSN were REG_UNUSED, ensure that they
3411 are still valid. Then add any non-duplicate notes added by
3412 recog_for_combine. */
3413 for (note = REG_NOTES (undobuf.other_insn); note; note = next)
3415 next = XEXP (note, 1);
3417 if (REG_NOTE_KIND (note) == REG_UNUSED
3418 && ! reg_set_p (XEXP (note, 0), PATTERN (undobuf.other_insn)))
3419 remove_note (undobuf.other_insn, note);
3422 distribute_notes (new_other_notes, undobuf.other_insn,
3423 undobuf.other_insn, NULL_RTX, NULL_RTX, NULL_RTX);
3432 /* I3 now uses what used to be its destination and which is now
3433 I2's destination. This requires us to do a few adjustments. */
3434 PATTERN (i3) = newpat;
3435 adjust_for_new_dest (i3);
3437 /* We need a LOG_LINK from I3 to I2. But we used to have one,
3440 However, some later insn might be using I2's dest and have
3441 a LOG_LINK pointing at I3. We must remove this link.
3442 The simplest way to remove the link is to point it at I1,
3443 which we know will be a NOTE. */
3445 /* newi2pat is usually a SET here; however, recog_for_combine might
3446 have added some clobbers. */
3447 if (GET_CODE (newi2pat) == PARALLEL)
3448 ni2dest = SET_DEST (XVECEXP (newi2pat, 0, 0));
3450 ni2dest = SET_DEST (newi2pat);
3452 for (insn = NEXT_INSN (i3);
3453 insn && (this_basic_block->next_bb == EXIT_BLOCK_PTR
3454 || insn != BB_HEAD (this_basic_block->next_bb));
3455 insn = NEXT_INSN (insn))
3457 if (INSN_P (insn) && reg_referenced_p (ni2dest, PATTERN (insn)))
3459 for (link = LOG_LINKS (insn); link;
3460 link = XEXP (link, 1))
3461 if (XEXP (link, 0) == i3)
3462 XEXP (link, 0) = i1;
3470 rtx i3notes, i2notes, i1notes = 0;
3471 rtx i3links, i2links, i1links = 0;
3474 /* Compute which registers we expect to eliminate. newi2pat may be setting
3475 either i3dest or i2dest, so we must check it. Also, i1dest may be the
3476 same as i3dest, in which case newi2pat may be setting i1dest. */
3477 rtx elim_i2 = ((newi2pat && reg_set_p (i2dest, newi2pat))
3478 || i2dest_in_i2src || i2dest_in_i1src
3481 rtx elim_i1 = (i1 == 0 || i1dest_in_i1src
3482 || (newi2pat && reg_set_p (i1dest, newi2pat))
3486 /* Get the old REG_NOTES and LOG_LINKS from all our insns and
3488 i3notes = REG_NOTES (i3), i3links = LOG_LINKS (i3);
3489 i2notes = REG_NOTES (i2), i2links = LOG_LINKS (i2);
3491 i1notes = REG_NOTES (i1), i1links = LOG_LINKS (i1);
3493 /* Ensure that we do not have something that should not be shared but
3494 occurs multiple times in the new insns. Check this by first
3495 resetting all the `used' flags and then copying anything is shared. */
3497 reset_used_flags (i3notes);
3498 reset_used_flags (i2notes);
3499 reset_used_flags (i1notes);
3500 reset_used_flags (newpat);
3501 reset_used_flags (newi2pat);
3502 if (undobuf.other_insn)
3503 reset_used_flags (PATTERN (undobuf.other_insn));
3505 i3notes = copy_rtx_if_shared (i3notes);
3506 i2notes = copy_rtx_if_shared (i2notes);
3507 i1notes = copy_rtx_if_shared (i1notes);
3508 newpat = copy_rtx_if_shared (newpat);
3509 newi2pat = copy_rtx_if_shared (newi2pat);
3510 if (undobuf.other_insn)
3511 reset_used_flags (PATTERN (undobuf.other_insn));
3513 INSN_CODE (i3) = insn_code_number;
3514 PATTERN (i3) = newpat;
3516 if (CALL_P (i3) && CALL_INSN_FUNCTION_USAGE (i3))
3518 rtx call_usage = CALL_INSN_FUNCTION_USAGE (i3);
3520 reset_used_flags (call_usage);
3521 call_usage = copy_rtx (call_usage);
3524 replace_rtx (call_usage, i2dest, i2src);
3527 replace_rtx (call_usage, i1dest, i1src);
3529 CALL_INSN_FUNCTION_USAGE (i3) = call_usage;
3532 if (undobuf.other_insn)
3533 INSN_CODE (undobuf.other_insn) = other_code_number;
3535 /* We had one special case above where I2 had more than one set and
3536 we replaced a destination of one of those sets with the destination
3537 of I3. In that case, we have to update LOG_LINKS of insns later
3538 in this basic block. Note that this (expensive) case is rare.
3540 Also, in this case, we must pretend that all REG_NOTEs for I2
3541 actually came from I3, so that REG_UNUSED notes from I2 will be
3542 properly handled. */
3544 if (i3_subst_into_i2)
3546 for (i = 0; i < XVECLEN (PATTERN (i2), 0); i++)
3547 if ((GET_CODE (XVECEXP (PATTERN (i2), 0, i)) == SET
3548 || GET_CODE (XVECEXP (PATTERN (i2), 0, i)) == CLOBBER)
3549 && REG_P (SET_DEST (XVECEXP (PATTERN (i2), 0, i)))
3550 && SET_DEST (XVECEXP (PATTERN (i2), 0, i)) != i2dest
3551 && ! find_reg_note (i2, REG_UNUSED,
3552 SET_DEST (XVECEXP (PATTERN (i2), 0, i))))
3553 for (temp = NEXT_INSN (i2);
3554 temp && (this_basic_block->next_bb == EXIT_BLOCK_PTR
3555 || BB_HEAD (this_basic_block) != temp);
3556 temp = NEXT_INSN (temp))
3557 if (temp != i3 && INSN_P (temp))
3558 for (link = LOG_LINKS (temp); link; link = XEXP (link, 1))
3559 if (XEXP (link, 0) == i2)
3560 XEXP (link, 0) = i3;
3565 while (XEXP (link, 1))
3566 link = XEXP (link, 1);
3567 XEXP (link, 1) = i2notes;
3581 INSN_CODE (i2) = i2_code_number;
3582 PATTERN (i2) = newi2pat;
3585 SET_INSN_DELETED (i2);
3591 SET_INSN_DELETED (i1);
3594 /* Get death notes for everything that is now used in either I3 or
3595 I2 and used to die in a previous insn. If we built two new
3596 patterns, move from I1 to I2 then I2 to I3 so that we get the
3597 proper movement on registers that I2 modifies. */
3601 move_deaths (newi2pat, NULL_RTX, DF_INSN_LUID (i1), i2, &midnotes);
3602 move_deaths (newpat, newi2pat, DF_INSN_LUID (i1), i3, &midnotes);
3605 move_deaths (newpat, NULL_RTX, i1 ? DF_INSN_LUID (i1) : DF_INSN_LUID (i2),
3608 /* Distribute all the LOG_LINKS and REG_NOTES from I1, I2, and I3. */
3610 distribute_notes (i3notes, i3, i3, newi2pat ? i2 : NULL_RTX,
3613 distribute_notes (i2notes, i2, i3, newi2pat ? i2 : NULL_RTX,
3616 distribute_notes (i1notes, i1, i3, newi2pat ? i2 : NULL_RTX,
3619 distribute_notes (midnotes, NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
3622 /* Distribute any notes added to I2 or I3 by recog_for_combine. We
3623 know these are REG_UNUSED and want them to go to the desired insn,
3624 so we always pass it as i3. */
3626 if (newi2pat && new_i2_notes)
3627 distribute_notes (new_i2_notes, i2, i2, NULL_RTX, NULL_RTX, NULL_RTX);
3630 distribute_notes (new_i3_notes, i3, i3, NULL_RTX, NULL_RTX, NULL_RTX);
3632 /* If I3DEST was used in I3SRC, it really died in I3. We may need to
3633 put a REG_DEAD note for it somewhere. If NEWI2PAT exists and sets
3634 I3DEST, the death must be somewhere before I2, not I3. If we passed I3
3635 in that case, it might delete I2. Similarly for I2 and I1.
3636 Show an additional death due to the REG_DEAD note we make here. If
3637 we discard it in distribute_notes, we will decrement it again. */
3641 if (newi2pat && reg_set_p (i3dest_killed, newi2pat))
3642 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i3dest_killed,
3644 NULL_RTX, i2, NULL_RTX, elim_i2, elim_i1);
3646 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i3dest_killed,
3648 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
3652 if (i2dest_in_i2src)
3654 if (newi2pat && reg_set_p (i2dest, newi2pat))
3655 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i2dest, NULL_RTX),
3656 NULL_RTX, i2, NULL_RTX, NULL_RTX, NULL_RTX);
3658 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i2dest, NULL_RTX),
3659 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
3660 NULL_RTX, NULL_RTX);
3663 if (i1dest_in_i1src)
3665 if (newi2pat && reg_set_p (i1dest, newi2pat))
3666 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i1dest, NULL_RTX),
3667 NULL_RTX, i2, NULL_RTX, NULL_RTX, NULL_RTX);
3669 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i1dest, NULL_RTX),
3670 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
3671 NULL_RTX, NULL_RTX);
3674 distribute_links (i3links);
3675 distribute_links (i2links);
3676 distribute_links (i1links);
3681 rtx i2_insn = 0, i2_val = 0, set;
3683 /* The insn that used to set this register doesn't exist, and
3684 this life of the register may not exist either. See if one of
3685 I3's links points to an insn that sets I2DEST. If it does,
3686 that is now the last known value for I2DEST. If we don't update
3687 this and I2 set the register to a value that depended on its old
3688 contents, we will get confused. If this insn is used, thing
3689 will be set correctly in combine_instructions. */
3691 for (link = LOG_LINKS (i3); link; link = XEXP (link, 1))
3692 if ((set = single_set (XEXP (link, 0))) != 0
3693 && rtx_equal_p (i2dest, SET_DEST (set)))
3694 i2_insn = XEXP (link, 0), i2_val = SET_SRC (set);
3696 record_value_for_reg (i2dest, i2_insn, i2_val);
3698 /* If the reg formerly set in I2 died only once and that was in I3,
3699 zero its use count so it won't make `reload' do any work. */
3701 && (newi2pat == 0 || ! reg_mentioned_p (i2dest, newi2pat))
3702 && ! i2dest_in_i2src)
3704 regno = REGNO (i2dest);
3705 INC_REG_N_SETS (regno, -1);
3709 if (i1 && REG_P (i1dest))
3712 rtx i1_insn = 0, i1_val = 0, set;
3714 for (link = LOG_LINKS (i3); link; link = XEXP (link, 1))
3715 if ((set = single_set (XEXP (link, 0))) != 0
3716 && rtx_equal_p (i1dest, SET_DEST (set)))
3717 i1_insn = XEXP (link, 0), i1_val = SET_SRC (set);
3719 record_value_for_reg (i1dest, i1_insn, i1_val);
3721 regno = REGNO (i1dest);
3722 if (! added_sets_1 && ! i1dest_in_i1src)
3723 INC_REG_N_SETS (regno, -1);
3726 /* Update reg_stat[].nonzero_bits et al for any changes that may have
3727 been made to this insn. The order of
3728 set_nonzero_bits_and_sign_copies() is important. Because newi2pat
3729 can affect nonzero_bits of newpat */
3731 note_stores (newi2pat, set_nonzero_bits_and_sign_copies, NULL);
3732 note_stores (newpat, set_nonzero_bits_and_sign_copies, NULL);
3734 /* Set new_direct_jump_p if a new return or simple jump instruction
3737 If I3 is now an unconditional jump, ensure that it has a
3738 BARRIER following it since it may have initially been a
3739 conditional jump. It may also be the last nonnote insn. */
3741 if (returnjump_p (i3) || any_uncondjump_p (i3))
3743 *new_direct_jump_p = 1;
3744 mark_jump_label (PATTERN (i3), i3, 0);
3746 if ((temp = next_nonnote_insn (i3)) == NULL_RTX
3747 || !BARRIER_P (temp))
3748 emit_barrier_after (i3);
3751 if (undobuf.other_insn != NULL_RTX
3752 && (returnjump_p (undobuf.other_insn)
3753 || any_uncondjump_p (undobuf.other_insn)))
3755 *new_direct_jump_p = 1;
3757 if ((temp = next_nonnote_insn (undobuf.other_insn)) == NULL_RTX
3758 || !BARRIER_P (temp))
3759 emit_barrier_after (undobuf.other_insn);
3762 /* An NOOP jump does not need barrier, but it does need cleaning up
3764 if (GET_CODE (newpat) == SET
3765 && SET_SRC (newpat) == pc_rtx
3766 && SET_DEST (newpat) == pc_rtx)
3767 *new_direct_jump_p = 1;
3770 if (undobuf.other_insn != NULL_RTX)
3774 fprintf (dump_file, "modifying other_insn ");
3775 dump_insn_slim (dump_file, undobuf.other_insn);
3777 df_insn_rescan (undobuf.other_insn);
3780 if (i1 && !(NOTE_P(i1) && (NOTE_KIND (i1) == NOTE_INSN_DELETED)))
3784 fprintf (dump_file, "modifying insn i1 ");
3785 dump_insn_slim (dump_file, i1);
3787 df_insn_rescan (i1);
3790 if (i2 && !(NOTE_P(i2) && (NOTE_KIND (i2) == NOTE_INSN_DELETED)))
3794 fprintf (dump_file, "modifying insn i2 ");
3795 dump_insn_slim (dump_file, i2);
3797 df_insn_rescan (i2);
3800 if (i3 && !(NOTE_P(i3) && (NOTE_KIND (i3) == NOTE_INSN_DELETED)))
3804 fprintf (dump_file, "modifying insn i3 ");
3805 dump_insn_slim (dump_file, i3);
3807 df_insn_rescan (i3);
3810 combine_successes++;
3813 if (added_links_insn
3814 && (newi2pat == 0 || DF_INSN_LUID (added_links_insn) < DF_INSN_LUID (i2))
3815 && DF_INSN_LUID (added_links_insn) < DF_INSN_LUID (i3))
3816 return added_links_insn;
3818 return newi2pat ? i2 : i3;
3821 /* Undo all the modifications recorded in undobuf. */
3826 struct undo *undo, *next;
3828 for (undo = undobuf.undos; undo; undo = next)
3834 *undo->where.r = undo->old_contents.r;
3837 *undo->where.i = undo->old_contents.i;
3840 adjust_reg_mode (*undo->where.r, undo->old_contents.m);
3846 undo->next = undobuf.frees;
3847 undobuf.frees = undo;
3853 /* We've committed to accepting the changes we made. Move all
3854 of the undos to the free list. */
3859 struct undo *undo, *next;
3861 for (undo = undobuf.undos; undo; undo = next)
3864 undo->next = undobuf.frees;
3865 undobuf.frees = undo;
3870 /* Find the innermost point within the rtx at LOC, possibly LOC itself,
3871 where we have an arithmetic expression and return that point. LOC will
3874 try_combine will call this function to see if an insn can be split into
3878 find_split_point (rtx *loc, rtx insn)
3881 enum rtx_code code = GET_CODE (x);
3883 unsigned HOST_WIDE_INT len = 0;
3884 HOST_WIDE_INT pos = 0;
3886 rtx inner = NULL_RTX;
3888 /* First special-case some codes. */
3892 #ifdef INSN_SCHEDULING
3893 /* If we are making a paradoxical SUBREG invalid, it becomes a split
3895 if (MEM_P (SUBREG_REG (x)))
3898 return find_split_point (&SUBREG_REG (x), insn);
3902 /* If we have (mem (const ..)) or (mem (symbol_ref ...)), split it
3903 using LO_SUM and HIGH. */
3904 if (GET_CODE (XEXP (x, 0)) == CONST
3905 || GET_CODE (XEXP (x, 0)) == SYMBOL_REF)
3908 gen_rtx_LO_SUM (Pmode,
3909 gen_rtx_HIGH (Pmode, XEXP (x, 0)),
3911 return &XEXP (XEXP (x, 0), 0);
3915 /* If we have a PLUS whose second operand is a constant and the
3916 address is not valid, perhaps will can split it up using
3917 the machine-specific way to split large constants. We use
3918 the first pseudo-reg (one of the virtual regs) as a placeholder;
3919 it will not remain in the result. */
3920 if (GET_CODE (XEXP (x, 0)) == PLUS
3921 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3922 && ! memory_address_p (GET_MODE (x), XEXP (x, 0)))
3924 rtx reg = regno_reg_rtx[FIRST_PSEUDO_REGISTER];
3925 rtx seq = combine_split_insns (gen_rtx_SET (VOIDmode, reg,
3929 /* This should have produced two insns, each of which sets our
3930 placeholder. If the source of the second is a valid address,
3931 we can make put both sources together and make a split point
3935 && NEXT_INSN (seq) != NULL_RTX
3936 && NEXT_INSN (NEXT_INSN (seq)) == NULL_RTX
3937 && NONJUMP_INSN_P (seq)
3938 && GET_CODE (PATTERN (seq)) == SET
3939 && SET_DEST (PATTERN (seq)) == reg
3940 && ! reg_mentioned_p (reg,
3941 SET_SRC (PATTERN (seq)))
3942 && NONJUMP_INSN_P (NEXT_INSN (seq))
3943 && GET_CODE (PATTERN (NEXT_INSN (seq))) == SET
3944 && SET_DEST (PATTERN (NEXT_INSN (seq))) == reg
3945 && memory_address_p (GET_MODE (x),
3946 SET_SRC (PATTERN (NEXT_INSN (seq)))))
3948 rtx src1 = SET_SRC (PATTERN (seq));
3949 rtx src2 = SET_SRC (PATTERN (NEXT_INSN (seq)));
3951 /* Replace the placeholder in SRC2 with SRC1. If we can
3952 find where in SRC2 it was placed, that can become our
3953 split point and we can replace this address with SRC2.
3954 Just try two obvious places. */
3956 src2 = replace_rtx (src2, reg, src1);
3958 if (XEXP (src2, 0) == src1)
3959 split = &XEXP (src2, 0);
3960 else if (GET_RTX_FORMAT (GET_CODE (XEXP (src2, 0)))[0] == 'e'
3961 && XEXP (XEXP (src2, 0), 0) == src1)
3962 split = &XEXP (XEXP (src2, 0), 0);
3966 SUBST (XEXP (x, 0), src2);
3971 /* If that didn't work, perhaps the first operand is complex and
3972 needs to be computed separately, so make a split point there.
3973 This will occur on machines that just support REG + CONST
3974 and have a constant moved through some previous computation. */
3976 else if (!OBJECT_P (XEXP (XEXP (x, 0), 0))
3977 && ! (GET_CODE (XEXP (XEXP (x, 0), 0)) == SUBREG
3978 && OBJECT_P (SUBREG_REG (XEXP (XEXP (x, 0), 0)))))
3979 return &XEXP (XEXP (x, 0), 0);
3982 /* If we have a PLUS whose first operand is complex, try computing it
3983 separately by making a split there. */
3984 if (GET_CODE (XEXP (x, 0)) == PLUS
3985 && ! memory_address_p (GET_MODE (x), XEXP (x, 0))
3986 && ! OBJECT_P (XEXP (XEXP (x, 0), 0))
3987 && ! (GET_CODE (XEXP (XEXP (x, 0), 0)) == SUBREG
3988 && OBJECT_P (SUBREG_REG (XEXP (XEXP (x, 0), 0)))))
3989 return &XEXP (XEXP (x, 0), 0);
3994 /* If SET_DEST is CC0 and SET_SRC is not an operand, a COMPARE, or a
3995 ZERO_EXTRACT, the most likely reason why this doesn't match is that
3996 we need to put the operand into a register. So split at that
3999 if (SET_DEST (x) == cc0_rtx
4000 && GET_CODE (SET_SRC (x)) != COMPARE
4001 && GET_CODE (SET_SRC (x)) != ZERO_EXTRACT
4002 && !OBJECT_P (SET_SRC (x))
4003 && ! (GET_CODE (SET_SRC (x)) == SUBREG
4004 && OBJECT_P (SUBREG_REG (SET_SRC (x)))))
4005 return &SET_SRC (x);
4008 /* See if we can split SET_SRC as it stands. */
4009 split = find_split_point (&SET_SRC (x), insn);
4010 if (split && split != &SET_SRC (x))
4013 /* See if we can split SET_DEST as it stands. */
4014 split = find_split_point (&SET_DEST (x), insn);
4015 if (split && split != &SET_DEST (x))
4018 /* See if this is a bitfield assignment with everything constant. If
4019 so, this is an IOR of an AND, so split it into that. */
4020 if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
4021 && (GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0)))
4022 <= HOST_BITS_PER_WIDE_INT)
4023 && GET_CODE (XEXP (SET_DEST (x), 1)) == CONST_INT
4024 && GET_CODE (XEXP (SET_DEST (x), 2)) == CONST_INT
4025 && GET_CODE (SET_SRC (x)) == CONST_INT
4026 && ((INTVAL (XEXP (SET_DEST (x), 1))
4027 + INTVAL (XEXP (SET_DEST (x), 2)))
4028 <= GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0))))
4029 && ! side_effects_p (XEXP (SET_DEST (x), 0)))
4031 HOST_WIDE_INT pos = INTVAL (XEXP (SET_DEST (x), 2));
4032 unsigned HOST_WIDE_INT len = INTVAL (XEXP (SET_DEST (x), 1));
4033 unsigned HOST_WIDE_INT src = INTVAL (SET_SRC (x));
4034 rtx dest = XEXP (SET_DEST (x), 0);
4035 enum machine_mode mode = GET_MODE (dest);
4036 unsigned HOST_WIDE_INT mask = ((HOST_WIDE_INT) 1 << len) - 1;
4039 if (BITS_BIG_ENDIAN)
4040 pos = GET_MODE_BITSIZE (mode) - len - pos;
4042 or_mask = gen_int_mode (src << pos, mode);
4045 simplify_gen_binary (IOR, mode, dest, or_mask));
4048 rtx negmask = gen_int_mode (~(mask << pos), mode);
4050 simplify_gen_binary (IOR, mode,
4051 simplify_gen_binary (AND, mode,
4056 SUBST (SET_DEST (x), dest);
4058 split = find_split_point (&SET_SRC (x), insn);
4059 if (split && split != &SET_SRC (x))
4063 /* Otherwise, see if this is an operation that we can split into two.
4064 If so, try to split that. */
4065 code = GET_CODE (SET_SRC (x));
4070 /* If we are AND'ing with a large constant that is only a single
4071 bit and the result is only being used in a context where we
4072 need to know if it is zero or nonzero, replace it with a bit
4073 extraction. This will avoid the large constant, which might
4074 have taken more than one insn to make. If the constant were
4075 not a valid argument to the AND but took only one insn to make,
4076 this is no worse, but if it took more than one insn, it will
4079 if (GET_CODE (XEXP (SET_SRC (x), 1)) == CONST_INT
4080 && REG_P (XEXP (SET_SRC (x), 0))
4081 && (pos = exact_log2 (INTVAL (XEXP (SET_SRC (x), 1)))) >= 7
4082 && REG_P (SET_DEST (x))
4083 && (split = find_single_use (SET_DEST (x), insn, (rtx*) 0)) != 0
4084 && (GET_CODE (*split) == EQ || GET_CODE (*split) == NE)
4085 && XEXP (*split, 0) == SET_DEST (x)
4086 && XEXP (*split, 1) == const0_rtx)
4088 rtx extraction = make_extraction (GET_MODE (SET_DEST (x)),
4089 XEXP (SET_SRC (x), 0),
4090 pos, NULL_RTX, 1, 1, 0, 0);
4091 if (extraction != 0)
4093 SUBST (SET_SRC (x), extraction);
4094 return find_split_point (loc, insn);
4100 /* If STORE_FLAG_VALUE is -1, this is (NE X 0) and only one bit of X
4101 is known to be on, this can be converted into a NEG of a shift. */
4102 if (STORE_FLAG_VALUE == -1 && XEXP (SET_SRC (x), 1) == const0_rtx
4103 && GET_MODE (SET_SRC (x)) == GET_MODE (XEXP (SET_SRC (x), 0))
4104 && 1 <= (pos = exact_log2
4105 (nonzero_bits (XEXP (SET_SRC (x), 0),
4106 GET_MODE (XEXP (SET_SRC (x), 0))))))
4108 enum machine_mode mode = GET_MODE (XEXP (SET_SRC (x), 0));
4112 gen_rtx_LSHIFTRT (mode,
4113 XEXP (SET_SRC (x), 0),
4116 split = find_split_point (&SET_SRC (x), insn);
4117 if (split && split != &SET_SRC (x))
4123 inner = XEXP (SET_SRC (x), 0);
4125 /* We can't optimize if either mode is a partial integer
4126 mode as we don't know how many bits are significant
4128 if (GET_MODE_CLASS (GET_MODE (inner)) == MODE_PARTIAL_INT
4129 || GET_MODE_CLASS (GET_MODE (SET_SRC (x))) == MODE_PARTIAL_INT)
4133 len = GET_MODE_BITSIZE (GET_MODE (inner));
4139 if (GET_CODE (XEXP (SET_SRC (x), 1)) == CONST_INT
4140 && GET_CODE (XEXP (SET_SRC (x), 2)) == CONST_INT)
4142 inner = XEXP (SET_SRC (x), 0);
4143 len = INTVAL (XEXP (SET_SRC (x), 1));
4144 pos = INTVAL (XEXP (SET_SRC (x), 2));
4146 if (BITS_BIG_ENDIAN)
4147 pos = GET_MODE_BITSIZE (GET_MODE (inner)) - len - pos;
4148 unsignedp = (code == ZERO_EXTRACT);
4156 if (len && pos >= 0 && pos + len <= GET_MODE_BITSIZE (GET_MODE (inner)))
4158 enum machine_mode mode = GET_MODE (SET_SRC (x));
4160 /* For unsigned, we have a choice of a shift followed by an
4161 AND or two shifts. Use two shifts for field sizes where the
4162 constant might be too large. We assume here that we can
4163 always at least get 8-bit constants in an AND insn, which is
4164 true for every current RISC. */
4166 if (unsignedp && len <= 8)
4171 (mode, gen_lowpart (mode, inner),
4173 GEN_INT (((HOST_WIDE_INT) 1 << len) - 1)));
4175 split = find_split_point (&SET_SRC (x), insn);
4176 if (split && split != &SET_SRC (x))
4183 (unsignedp ? LSHIFTRT : ASHIFTRT, mode,
4184 gen_rtx_ASHIFT (mode,
4185 gen_lowpart (mode, inner),
4186 GEN_INT (GET_MODE_BITSIZE (mode)
4188 GEN_INT (GET_MODE_BITSIZE (mode) - len)));
4190 split = find_split_point (&SET_SRC (x), insn);
4191 if (split && split != &SET_SRC (x))
4196 /* See if this is a simple operation with a constant as the second
4197 operand. It might be that this constant is out of range and hence
4198 could be used as a split point. */
4199 if (BINARY_P (SET_SRC (x))
4200 && CONSTANT_P (XEXP (SET_SRC (x), 1))
4201 && (OBJECT_P (XEXP (SET_SRC (x), 0))
4202 || (GET_CODE (XEXP (SET_SRC (x), 0)) == SUBREG
4203 && OBJECT_P (SUBREG_REG (XEXP (SET_SRC (x), 0))))))
4204 return &XEXP (SET_SRC (x), 1);
4206 /* Finally, see if this is a simple operation with its first operand
4207 not in a register. The operation might require this operand in a
4208 register, so return it as a split point. We can always do this
4209 because if the first operand were another operation, we would have
4210 already found it as a split point. */
4211 if ((BINARY_P (SET_SRC (x)) || UNARY_P (SET_SRC (x)))
4212 && ! register_operand (XEXP (SET_SRC (x), 0), VOIDmode))
4213 return &XEXP (SET_SRC (x), 0);
4219 /* We write NOR as (and (not A) (not B)), but if we don't have a NOR,
4220 it is better to write this as (not (ior A B)) so we can split it.
4221 Similarly for IOR. */
4222 if (GET_CODE (XEXP (x, 0)) == NOT && GET_CODE (XEXP (x, 1)) == NOT)
4225 gen_rtx_NOT (GET_MODE (x),
4226 gen_rtx_fmt_ee (code == IOR ? AND : IOR,
4228 XEXP (XEXP (x, 0), 0),
4229 XEXP (XEXP (x, 1), 0))));
4230 return find_split_point (loc, insn);
4233 /* Many RISC machines have a large set of logical insns. If the
4234 second operand is a NOT, put it first so we will try to split the
4235 other operand first. */
4236 if (GET_CODE (XEXP (x, 1)) == NOT)
4238 rtx tem = XEXP (x, 0);
4239 SUBST (XEXP (x, 0), XEXP (x, 1));
4240 SUBST (XEXP (x, 1), tem);
4248 /* Otherwise, select our actions depending on our rtx class. */
4249 switch (GET_RTX_CLASS (code))
4251 case RTX_BITFIELD_OPS: /* This is ZERO_EXTRACT and SIGN_EXTRACT. */
4253 split = find_split_point (&XEXP (x, 2), insn);
4256 /* ... fall through ... */
4258 case RTX_COMM_ARITH:
4260 case RTX_COMM_COMPARE:
4261 split = find_split_point (&XEXP (x, 1), insn);
4264 /* ... fall through ... */
4266 /* Some machines have (and (shift ...) ...) insns. If X is not
4267 an AND, but XEXP (X, 0) is, use it as our split point. */
4268 if (GET_CODE (x) != AND && GET_CODE (XEXP (x, 0)) == AND)
4269 return &XEXP (x, 0);
4271 split = find_split_point (&XEXP (x, 0), insn);
4277 /* Otherwise, we don't have a split point. */
4282 /* Throughout X, replace FROM with TO, and return the result.
4283 The result is TO if X is FROM;
4284 otherwise the result is X, but its contents may have been modified.
4285 If they were modified, a record was made in undobuf so that
4286 undo_all will (among other things) return X to its original state.
4288 If the number of changes necessary is too much to record to undo,
4289 the excess changes are not made, so the result is invalid.
4290 The changes already made can still be undone.
4291 undobuf.num_undo is incremented for such changes, so by testing that
4292 the caller can tell whether the result is valid.
4294 `n_occurrences' is incremented each time FROM is replaced.
4296 IN_DEST is nonzero if we are processing the SET_DEST of a SET.
4298 UNIQUE_COPY is nonzero if each substitution must be unique. We do this
4299 by copying if `n_occurrences' is nonzero. */
4302 subst (rtx x, rtx from, rtx to, int in_dest, int unique_copy)
4304 enum rtx_code code = GET_CODE (x);
4305 enum machine_mode op0_mode = VOIDmode;
4310 /* Two expressions are equal if they are identical copies of a shared
4311 RTX or if they are both registers with the same register number
4314 #define COMBINE_RTX_EQUAL_P(X,Y) \
4316 || (REG_P (X) && REG_P (Y) \
4317 && REGNO (X) == REGNO (Y) && GET_MODE (X) == GET_MODE (Y)))
4319 if (! in_dest && COMBINE_RTX_EQUAL_P (x, from))
4322 return (unique_copy && n_occurrences > 1 ? copy_rtx (to) : to);
4325 /* If X and FROM are the same register but different modes, they
4326 will not have been seen as equal above. However, the log links code
4327 will make a LOG_LINKS entry for that case. If we do nothing, we
4328 will try to rerecognize our original insn and, when it succeeds,
4329 we will delete the feeding insn, which is incorrect.
4331 So force this insn not to match in this (rare) case. */
4332 if (! in_dest && code == REG && REG_P (from)
4333 && reg_overlap_mentioned_p (x, from))
4334 return gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
4336 /* If this is an object, we are done unless it is a MEM or LO_SUM, both
4337 of which may contain things that can be combined. */
4338 if (code != MEM && code != LO_SUM && OBJECT_P (x))
4341 /* It is possible to have a subexpression appear twice in the insn.
4342 Suppose that FROM is a register that appears within TO.
4343 Then, after that subexpression has been scanned once by `subst',
4344 the second time it is scanned, TO may be found. If we were
4345 to scan TO here, we would find FROM within it and create a
4346 self-referent rtl structure which is completely wrong. */
4347 if (COMBINE_RTX_EQUAL_P (x, to))
4350 /* Parallel asm_operands need special attention because all of the
4351 inputs are shared across the arms. Furthermore, unsharing the
4352 rtl results in recognition failures. Failure to handle this case
4353 specially can result in circular rtl.
4355 Solve this by doing a normal pass across the first entry of the
4356 parallel, and only processing the SET_DESTs of the subsequent
4359 if (code == PARALLEL
4360 && GET_CODE (XVECEXP (x, 0, 0)) == SET
4361 && GET_CODE (SET_SRC (XVECEXP (x, 0, 0))) == ASM_OPERANDS)
4363 new = subst (XVECEXP (x, 0, 0), from, to, 0, unique_copy);
4365 /* If this substitution failed, this whole thing fails. */
4366 if (GET_CODE (new) == CLOBBER
4367 && XEXP (new, 0) == const0_rtx)
4370 SUBST (XVECEXP (x, 0, 0), new);
4372 for (i = XVECLEN (x, 0) - 1; i >= 1; i--)
4374 rtx dest = SET_DEST (XVECEXP (x, 0, i));
4377 && GET_CODE (dest) != CC0
4378 && GET_CODE (dest) != PC)
4380 new = subst (dest, from, to, 0, unique_copy);
4382 /* If this substitution failed, this whole thing fails. */
4383 if (GET_CODE (new) == CLOBBER
4384 && XEXP (new, 0) == const0_rtx)
4387 SUBST (SET_DEST (XVECEXP (x, 0, i)), new);
4393 len = GET_RTX_LENGTH (code);
4394 fmt = GET_RTX_FORMAT (code);
4396 /* We don't need to process a SET_DEST that is a register, CC0,
4397 or PC, so set up to skip this common case. All other cases
4398 where we want to suppress replacing something inside a
4399 SET_SRC are handled via the IN_DEST operand. */
4401 && (REG_P (SET_DEST (x))
4402 || GET_CODE (SET_DEST (x)) == CC0
4403 || GET_CODE (SET_DEST (x)) == PC))
4406 /* Get the mode of operand 0 in case X is now a SIGN_EXTEND of a
4409 op0_mode = GET_MODE (XEXP (x, 0));
4411 for (i = 0; i < len; i++)
4416 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
4418 if (COMBINE_RTX_EQUAL_P (XVECEXP (x, i, j), from))
4420 new = (unique_copy && n_occurrences
4421 ? copy_rtx (to) : to);
4426 new = subst (XVECEXP (x, i, j), from, to, 0,
4429 /* If this substitution failed, this whole thing
4431 if (GET_CODE (new) == CLOBBER
4432 && XEXP (new, 0) == const0_rtx)
4436 SUBST (XVECEXP (x, i, j), new);
4439 else if (fmt[i] == 'e')
4441 /* If this is a register being set, ignore it. */
4445 && (((code == SUBREG || code == ZERO_EXTRACT)
4447 || code == STRICT_LOW_PART))
4450 else if (COMBINE_RTX_EQUAL_P (XEXP (x, i), from))
4452 /* In general, don't install a subreg involving two
4453 modes not tieable. It can worsen register
4454 allocation, and can even make invalid reload
4455 insns, since the reg inside may need to be copied
4456 from in the outside mode, and that may be invalid
4457 if it is an fp reg copied in integer mode.
4459 We allow two exceptions to this: It is valid if
4460 it is inside another SUBREG and the mode of that
4461 SUBREG and the mode of the inside of TO is
4462 tieable and it is valid if X is a SET that copies
4465 if (GET_CODE (to) == SUBREG
4466 && ! MODES_TIEABLE_P (GET_MODE (to),
4467 GET_MODE (SUBREG_REG (to)))
4468 && ! (code == SUBREG
4469 && MODES_TIEABLE_P (GET_MODE (x),
4470 GET_MODE (SUBREG_REG (to))))
4472 && ! (code == SET && i == 1 && XEXP (x, 0) == cc0_rtx)
4475 return gen_rtx_CLOBBER (VOIDmode, const0_rtx);
4477 #ifdef CANNOT_CHANGE_MODE_CLASS
4480 && REGNO (to) < FIRST_PSEUDO_REGISTER
4481 && REG_CANNOT_CHANGE_MODE_P (REGNO (to),
4484 return gen_rtx_CLOBBER (VOIDmode, const0_rtx);
4487 new = (unique_copy && n_occurrences ? copy_rtx (to) : to);
4491 /* If we are in a SET_DEST, suppress most cases unless we
4492 have gone inside a MEM, in which case we want to
4493 simplify the address. We assume here that things that
4494 are actually part of the destination have their inner
4495 parts in the first expression. This is true for SUBREG,
4496 STRICT_LOW_PART, and ZERO_EXTRACT, which are the only
4497 things aside from REG and MEM that should appear in a
4499 new = subst (XEXP (x, i), from, to,
4501 && (code == SUBREG || code == STRICT_LOW_PART
4502 || code == ZERO_EXTRACT))
4504 && i == 0), unique_copy);
4506 /* If we found that we will have to reject this combination,
4507 indicate that by returning the CLOBBER ourselves, rather than
4508 an expression containing it. This will speed things up as
4509 well as prevent accidents where two CLOBBERs are considered
4510 to be equal, thus producing an incorrect simplification. */
4512 if (GET_CODE (new) == CLOBBER && XEXP (new, 0) == const0_rtx)
4515 if (GET_CODE (x) == SUBREG
4516 && (GET_CODE (new) == CONST_INT
4517 || GET_CODE (new) == CONST_DOUBLE))
4519 enum machine_mode mode = GET_MODE (x);
4521 x = simplify_subreg (GET_MODE (x), new,
4522 GET_MODE (SUBREG_REG (x)),
4525 x = gen_rtx_CLOBBER (mode, const0_rtx);
4527 else if (GET_CODE (new) == CONST_INT
4528 && GET_CODE (x) == ZERO_EXTEND)
4530 x = simplify_unary_operation (ZERO_EXTEND, GET_MODE (x),
4531 new, GET_MODE (XEXP (x, 0)));
4535 SUBST (XEXP (x, i), new);
4540 /* Check if we are loading something from the constant pool via float
4541 extension; in this case we would undo compress_float_constant
4542 optimization and degenerate constant load to an immediate value. */
4543 if (GET_CODE (x) == FLOAT_EXTEND
4544 && MEM_P (XEXP (x, 0))
4545 && MEM_READONLY_P (XEXP (x, 0)))
4547 rtx tmp = avoid_constant_pool_reference (x);
4552 /* Try to simplify X. If the simplification changed the code, it is likely
4553 that further simplification will help, so loop, but limit the number
4554 of repetitions that will be performed. */
4556 for (i = 0; i < 4; i++)
4558 /* If X is sufficiently simple, don't bother trying to do anything
4560 if (code != CONST_INT && code != REG && code != CLOBBER)
4561 x = combine_simplify_rtx (x, op0_mode, in_dest);
4563 if (GET_CODE (x) == code)
4566 code = GET_CODE (x);
4568 /* We no longer know the original mode of operand 0 since we
4569 have changed the form of X) */
4570 op0_mode = VOIDmode;
4576 /* Simplify X, a piece of RTL. We just operate on the expression at the
4577 outer level; call `subst' to simplify recursively. Return the new
4580 OP0_MODE is the original mode of XEXP (x, 0). IN_DEST is nonzero
4581 if we are inside a SET_DEST. */
4584 combine_simplify_rtx (rtx x, enum machine_mode op0_mode, int in_dest)
4586 enum rtx_code code = GET_CODE (x);
4587 enum machine_mode mode = GET_MODE (x);
4591 /* If this is a commutative operation, put a constant last and a complex
4592 expression first. We don't need to do this for comparisons here. */
4593 if (COMMUTATIVE_ARITH_P (x)
4594 && swap_commutative_operands_p (XEXP (x, 0), XEXP (x, 1)))
4597 SUBST (XEXP (x, 0), XEXP (x, 1));
4598 SUBST (XEXP (x, 1), temp);
4601 /* If this is a simple operation applied to an IF_THEN_ELSE, try
4602 applying it to the arms of the IF_THEN_ELSE. This often simplifies
4603 things. Check for cases where both arms are testing the same
4606 Don't do anything if all operands are very simple. */
4609 && ((!OBJECT_P (XEXP (x, 0))
4610 && ! (GET_CODE (XEXP (x, 0)) == SUBREG
4611 && OBJECT_P (SUBREG_REG (XEXP (x, 0)))))
4612 || (!OBJECT_P (XEXP (x, 1))
4613 && ! (GET_CODE (XEXP (x, 1)) == SUBREG
4614 && OBJECT_P (SUBREG_REG (XEXP (x, 1)))))))
4616 && (!OBJECT_P (XEXP (x, 0))
4617 && ! (GET_CODE (XEXP (x, 0)) == SUBREG
4618 && OBJECT_P (SUBREG_REG (XEXP (x, 0)))))))
4620 rtx cond, true_rtx, false_rtx;
4622 cond = if_then_else_cond (x, &true_rtx, &false_rtx);
4624 /* If everything is a comparison, what we have is highly unlikely
4625 to be simpler, so don't use it. */
4626 && ! (COMPARISON_P (x)
4627 && (COMPARISON_P (true_rtx) || COMPARISON_P (false_rtx))))
4629 rtx cop1 = const0_rtx;
4630 enum rtx_code cond_code = simplify_comparison (NE, &cond, &cop1);
4632 if (cond_code == NE && COMPARISON_P (cond))
4635 /* Simplify the alternative arms; this may collapse the true and
4636 false arms to store-flag values. Be careful to use copy_rtx
4637 here since true_rtx or false_rtx might share RTL with x as a
4638 result of the if_then_else_cond call above. */
4639 true_rtx = subst (copy_rtx (true_rtx), pc_rtx, pc_rtx, 0, 0);
4640 false_rtx = subst (copy_rtx (false_rtx), pc_rtx, pc_rtx, 0, 0);
4642 /* If true_rtx and false_rtx are not general_operands, an if_then_else
4643 is unlikely to be simpler. */
4644 if (general_operand (true_rtx, VOIDmode)
4645 && general_operand (false_rtx, VOIDmode))
4647 enum rtx_code reversed;
4649 /* Restarting if we generate a store-flag expression will cause
4650 us to loop. Just drop through in this case. */
4652 /* If the result values are STORE_FLAG_VALUE and zero, we can
4653 just make the comparison operation. */
4654 if (true_rtx == const_true_rtx && false_rtx == const0_rtx)
4655 x = simplify_gen_relational (cond_code, mode, VOIDmode,
4657 else if (true_rtx == const0_rtx && false_rtx == const_true_rtx
4658 && ((reversed = reversed_comparison_code_parts
4659 (cond_code, cond, cop1, NULL))
4661 x = simplify_gen_relational (reversed, mode, VOIDmode,
4664 /* Likewise, we can make the negate of a comparison operation
4665 if the result values are - STORE_FLAG_VALUE and zero. */
4666 else if (GET_CODE (true_rtx) == CONST_INT
4667 && INTVAL (true_rtx) == - STORE_FLAG_VALUE
4668 && false_rtx == const0_rtx)
4669 x = simplify_gen_unary (NEG, mode,
4670 simplify_gen_relational (cond_code,
4674 else if (GET_CODE (false_rtx) == CONST_INT
4675 && INTVAL (false_rtx) == - STORE_FLAG_VALUE
4676 && true_rtx == const0_rtx
4677 && ((reversed = reversed_comparison_code_parts
4678 (cond_code, cond, cop1, NULL))
4680 x = simplify_gen_unary (NEG, mode,
4681 simplify_gen_relational (reversed,
4686 return gen_rtx_IF_THEN_ELSE (mode,
4687 simplify_gen_relational (cond_code,
4692 true_rtx, false_rtx);
4694 code = GET_CODE (x);
4695 op0_mode = VOIDmode;
4700 /* Try to fold this expression in case we have constants that weren't
4703 switch (GET_RTX_CLASS (code))
4706 if (op0_mode == VOIDmode)
4707 op0_mode = GET_MODE (XEXP (x, 0));
4708 temp = simplify_unary_operation (code, mode, XEXP (x, 0), op0_mode);
4711 case RTX_COMM_COMPARE:
4713 enum machine_mode cmp_mode = GET_MODE (XEXP (x, 0));
4714 if (cmp_mode == VOIDmode)
4716 cmp_mode = GET_MODE (XEXP (x, 1));
4717 if (cmp_mode == VOIDmode)
4718 cmp_mode = op0_mode;
4720 temp = simplify_relational_operation (code, mode, cmp_mode,
4721 XEXP (x, 0), XEXP (x, 1));
4724 case RTX_COMM_ARITH:
4726 temp = simplify_binary_operation (code, mode, XEXP (x, 0), XEXP (x, 1));
4728 case RTX_BITFIELD_OPS:
4730 temp = simplify_ternary_operation (code, mode, op0_mode, XEXP (x, 0),
4731 XEXP (x, 1), XEXP (x, 2));
4740 code = GET_CODE (temp);
4741 op0_mode = VOIDmode;
4742 mode = GET_MODE (temp);
4745 /* First see if we can apply the inverse distributive law. */
4746 if (code == PLUS || code == MINUS
4747 || code == AND || code == IOR || code == XOR)
4749 x = apply_distributive_law (x);
4750 code = GET_CODE (x);
4751 op0_mode = VOIDmode;
4754 /* If CODE is an associative operation not otherwise handled, see if we
4755 can associate some operands. This can win if they are constants or
4756 if they are logically related (i.e. (a & b) & a). */
4757 if ((code == PLUS || code == MINUS || code == MULT || code == DIV
4758 || code == AND || code == IOR || code == XOR
4759 || code == SMAX || code == SMIN || code == UMAX || code == UMIN)
4760 && ((INTEGRAL_MODE_P (mode) && code != DIV)
4761 || (flag_associative_math && FLOAT_MODE_P (mode))))
4763 if (GET_CODE (XEXP (x, 0)) == code)
4765 rtx other = XEXP (XEXP (x, 0), 0);
4766 rtx inner_op0 = XEXP (XEXP (x, 0), 1);
4767 rtx inner_op1 = XEXP (x, 1);
4770 /* Make sure we pass the constant operand if any as the second
4771 one if this is a commutative operation. */
4772 if (CONSTANT_P (inner_op0) && COMMUTATIVE_ARITH_P (x))
4774 rtx tem = inner_op0;
4775 inner_op0 = inner_op1;
4778 inner = simplify_binary_operation (code == MINUS ? PLUS
4779 : code == DIV ? MULT
4781 mode, inner_op0, inner_op1);
4783 /* For commutative operations, try the other pair if that one
4785 if (inner == 0 && COMMUTATIVE_ARITH_P (x))
4787 other = XEXP (XEXP (x, 0), 1);
4788 inner = simplify_binary_operation (code, mode,
4789 XEXP (XEXP (x, 0), 0),
4794 return simplify_gen_binary (code, mode, other, inner);
4798 /* A little bit of algebraic simplification here. */
4802 /* Ensure that our address has any ASHIFTs converted to MULT in case
4803 address-recognizing predicates are called later. */
4804 temp = make_compound_operation (XEXP (x, 0), MEM);
4805 SUBST (XEXP (x, 0), temp);
4809 if (op0_mode == VOIDmode)
4810 op0_mode = GET_MODE (SUBREG_REG (x));
4812 /* See if this can be moved to simplify_subreg. */
4813 if (CONSTANT_P (SUBREG_REG (x))
4814 && subreg_lowpart_offset (mode, op0_mode) == SUBREG_BYTE (x)
4815 /* Don't call gen_lowpart if the inner mode
4816 is VOIDmode and we cannot simplify it, as SUBREG without
4817 inner mode is invalid. */
4818 && (GET_MODE (SUBREG_REG (x)) != VOIDmode
4819 || gen_lowpart_common (mode, SUBREG_REG (x))))
4820 return gen_lowpart (mode, SUBREG_REG (x));
4822 if (GET_MODE_CLASS (GET_MODE (SUBREG_REG (x))) == MODE_CC)
4826 temp = simplify_subreg (mode, SUBREG_REG (x), op0_mode,
4832 /* Don't change the mode of the MEM if that would change the meaning
4834 if (MEM_P (SUBREG_REG (x))
4835 && (MEM_VOLATILE_P (SUBREG_REG (x))
4836 || mode_dependent_address_p (XEXP (SUBREG_REG (x), 0))))
4837 return gen_rtx_CLOBBER (mode, const0_rtx);
4839 /* Note that we cannot do any narrowing for non-constants since
4840 we might have been counting on using the fact that some bits were
4841 zero. We now do this in the SET. */
4846 temp = expand_compound_operation (XEXP (x, 0));
4848 /* For C equal to the width of MODE minus 1, (neg (ashiftrt X C)) can be
4849 replaced by (lshiftrt X C). This will convert
4850 (neg (sign_extract X 1 Y)) to (zero_extract X 1 Y). */
4852 if (GET_CODE (temp) == ASHIFTRT
4853 && GET_CODE (XEXP (temp, 1)) == CONST_INT
4854 && INTVAL (XEXP (temp, 1)) == GET_MODE_BITSIZE (mode) - 1)
4855 return simplify_shift_const (NULL_RTX, LSHIFTRT, mode, XEXP (temp, 0),
4856 INTVAL (XEXP (temp, 1)));
4858 /* If X has only a single bit that might be nonzero, say, bit I, convert
4859 (neg X) to (ashiftrt (ashift X C-I) C-I) where C is the bitsize of
4860 MODE minus 1. This will convert (neg (zero_extract X 1 Y)) to
4861 (sign_extract X 1 Y). But only do this if TEMP isn't a register
4862 or a SUBREG of one since we'd be making the expression more
4863 complex if it was just a register. */
4866 && ! (GET_CODE (temp) == SUBREG
4867 && REG_P (SUBREG_REG (temp)))
4868 && (i = exact_log2 (nonzero_bits (temp, mode))) >= 0)
4870 rtx temp1 = simplify_shift_const
4871 (NULL_RTX, ASHIFTRT, mode,
4872 simplify_shift_const (NULL_RTX, ASHIFT, mode, temp,
4873 GET_MODE_BITSIZE (mode) - 1 - i),
4874 GET_MODE_BITSIZE (mode) - 1 - i);
4876 /* If all we did was surround TEMP with the two shifts, we
4877 haven't improved anything, so don't use it. Otherwise,
4878 we are better off with TEMP1. */
4879 if (GET_CODE (temp1) != ASHIFTRT
4880 || GET_CODE (XEXP (temp1, 0)) != ASHIFT
4881 || XEXP (XEXP (temp1, 0), 0) != temp)
4887 /* We can't handle truncation to a partial integer mode here
4888 because we don't know the real bitsize of the partial
4890 if (GET_MODE_CLASS (mode) == MODE_PARTIAL_INT)
4893 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4894 && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode),
4895 GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))))
4897 force_to_mode (XEXP (x, 0), GET_MODE (XEXP (x, 0)),
4898 GET_MODE_MASK (mode), 0));
4900 /* Similarly to what we do in simplify-rtx.c, a truncate of a register
4901 whose value is a comparison can be replaced with a subreg if
4902 STORE_FLAG_VALUE permits. */
4903 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4904 && ((HOST_WIDE_INT) STORE_FLAG_VALUE & ~GET_MODE_MASK (mode)) == 0
4905 && (temp = get_last_value (XEXP (x, 0)))
4906 && COMPARISON_P (temp))
4907 return gen_lowpart (mode, XEXP (x, 0));
4912 /* Convert (compare FOO (const_int 0)) to FOO unless we aren't
4913 using cc0, in which case we want to leave it as a COMPARE
4914 so we can distinguish it from a register-register-copy. */
4915 if (XEXP (x, 1) == const0_rtx)
4918 /* x - 0 is the same as x unless x's mode has signed zeros and
4919 allows rounding towards -infinity. Under those conditions,
4921 if (!(HONOR_SIGNED_ZEROS (GET_MODE (XEXP (x, 0)))
4922 && HONOR_SIGN_DEPENDENT_ROUNDING (GET_MODE (XEXP (x, 0))))
4923 && XEXP (x, 1) == CONST0_RTX (GET_MODE (XEXP (x, 0))))
4929 /* (const (const X)) can become (const X). Do it this way rather than
4930 returning the inner CONST since CONST can be shared with a
4932 if (GET_CODE (XEXP (x, 0)) == CONST)
4933 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4938 /* Convert (lo_sum (high FOO) FOO) to FOO. This is necessary so we
4939 can add in an offset. find_split_point will split this address up
4940 again if it doesn't match. */
4941 if (GET_CODE (XEXP (x, 0)) == HIGH
4942 && rtx_equal_p (XEXP (XEXP (x, 0), 0), XEXP (x, 1)))
4948 /* (plus (xor (and <foo> (const_int pow2 - 1)) <c>) <-c>)
4949 when c is (const_int (pow2 + 1) / 2) is a sign extension of a
4950 bit-field and can be replaced by either a sign_extend or a
4951 sign_extract. The `and' may be a zero_extend and the two
4952 <c>, -<c> constants may be reversed. */
4953 if (GET_CODE (XEXP (x, 0)) == XOR
4954 && GET_CODE (XEXP (x, 1)) == CONST_INT
4955 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
4956 && INTVAL (XEXP (x, 1)) == -INTVAL (XEXP (XEXP (x, 0), 1))
4957 && ((i = exact_log2 (INTVAL (XEXP (XEXP (x, 0), 1)))) >= 0
4958 || (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0)
4959 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4960 && ((GET_CODE (XEXP (XEXP (x, 0), 0)) == AND
4961 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == CONST_INT
4962 && (INTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1))
4963 == ((HOST_WIDE_INT) 1 << (i + 1)) - 1))
4964 || (GET_CODE (XEXP (XEXP (x, 0), 0)) == ZERO_EXTEND
4965 && (GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)))
4966 == (unsigned int) i + 1))))
4967 return simplify_shift_const
4968 (NULL_RTX, ASHIFTRT, mode,
4969 simplify_shift_const (NULL_RTX, ASHIFT, mode,
4970 XEXP (XEXP (XEXP (x, 0), 0), 0),
4971 GET_MODE_BITSIZE (mode) - (i + 1)),
4972 GET_MODE_BITSIZE (mode) - (i + 1));
4974 /* If only the low-order bit of X is possibly nonzero, (plus x -1)
4975 can become (ashiftrt (ashift (xor x 1) C) C) where C is
4976 the bitsize of the mode - 1. This allows simplification of
4977 "a = (b & 8) == 0;" */
4978 if (XEXP (x, 1) == constm1_rtx
4979 && !REG_P (XEXP (x, 0))
4980 && ! (GET_CODE (XEXP (x, 0)) == SUBREG
4981 && REG_P (SUBREG_REG (XEXP (x, 0))))
4982 && nonzero_bits (XEXP (x, 0), mode) == 1)
4983 return simplify_shift_const (NULL_RTX, ASHIFTRT, mode,
4984 simplify_shift_const (NULL_RTX, ASHIFT, mode,
4985 gen_rtx_XOR (mode, XEXP (x, 0), const1_rtx),
4986 GET_MODE_BITSIZE (mode) - 1),
4987 GET_MODE_BITSIZE (mode) - 1);
4989 /* If we are adding two things that have no bits in common, convert
4990 the addition into an IOR. This will often be further simplified,
4991 for example in cases like ((a & 1) + (a & 2)), which can
4994 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4995 && (nonzero_bits (XEXP (x, 0), mode)
4996 & nonzero_bits (XEXP (x, 1), mode)) == 0)
4998 /* Try to simplify the expression further. */
4999 rtx tor = simplify_gen_binary (IOR, mode, XEXP (x, 0), XEXP (x, 1));
5000 temp = combine_simplify_rtx (tor, mode, in_dest);
5002 /* If we could, great. If not, do not go ahead with the IOR
5003 replacement, since PLUS appears in many special purpose
5004 address arithmetic instructions. */
5005 if (GET_CODE (temp) != CLOBBER && temp != tor)
5011 /* (minus <foo> (and <foo> (const_int -pow2))) becomes
5012 (and <foo> (const_int pow2-1)) */
5013 if (GET_CODE (XEXP (x, 1)) == AND
5014 && GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT
5015 && exact_log2 (-INTVAL (XEXP (XEXP (x, 1), 1))) >= 0
5016 && rtx_equal_p (XEXP (XEXP (x, 1), 0), XEXP (x, 0)))
5017 return simplify_and_const_int (NULL_RTX, mode, XEXP (x, 0),
5018 -INTVAL (XEXP (XEXP (x, 1), 1)) - 1);
5022 /* If we have (mult (plus A B) C), apply the distributive law and then
5023 the inverse distributive law to see if things simplify. This
5024 occurs mostly in addresses, often when unrolling loops. */
5026 if (GET_CODE (XEXP (x, 0)) == PLUS)
5028 rtx result = distribute_and_simplify_rtx (x, 0);
5033 /* Try simplify a*(b/c) as (a*b)/c. */
5034 if (FLOAT_MODE_P (mode) && flag_associative_math
5035 && GET_CODE (XEXP (x, 0)) == DIV)
5037 rtx tem = simplify_binary_operation (MULT, mode,
5038 XEXP (XEXP (x, 0), 0),
5041 return simplify_gen_binary (DIV, mode, tem, XEXP (XEXP (x, 0), 1));
5046 /* If this is a divide by a power of two, treat it as a shift if
5047 its first operand is a shift. */
5048 if (GET_CODE (XEXP (x, 1)) == CONST_INT
5049 && (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0
5050 && (GET_CODE (XEXP (x, 0)) == ASHIFT
5051 || GET_CODE (XEXP (x, 0)) == LSHIFTRT
5052 || GET_CODE (XEXP (x, 0)) == ASHIFTRT
5053 || GET_CODE (XEXP (x, 0)) == ROTATE
5054 || GET_CODE (XEXP (x, 0)) == ROTATERT))
5055 return simplify_shift_const (NULL_RTX, LSHIFTRT, mode, XEXP (x, 0), i);
5059 case GT: case GTU: case GE: case GEU:
5060 case LT: case LTU: case LE: case LEU:
5061 case UNEQ: case LTGT:
5062 case UNGT: case UNGE:
5063 case UNLT: case UNLE:
5064 case UNORDERED: case ORDERED:
5065 /* If the first operand is a condition code, we can't do anything
5067 if (GET_CODE (XEXP (x, 0)) == COMPARE
5068 || (GET_MODE_CLASS (GET_MODE (XEXP (x, 0))) != MODE_CC
5069 && ! CC0_P (XEXP (x, 0))))
5071 rtx op0 = XEXP (x, 0);
5072 rtx op1 = XEXP (x, 1);
5073 enum rtx_code new_code;
5075 if (GET_CODE (op0) == COMPARE)
5076 op1 = XEXP (op0, 1), op0 = XEXP (op0, 0);
5078 /* Simplify our comparison, if possible. */
5079 new_code = simplify_comparison (code, &op0, &op1);
5081 /* If STORE_FLAG_VALUE is 1, we can convert (ne x 0) to simply X
5082 if only the low-order bit is possibly nonzero in X (such as when
5083 X is a ZERO_EXTRACT of one bit). Similarly, we can convert EQ to
5084 (xor X 1) or (minus 1 X); we use the former. Finally, if X is
5085 known to be either 0 or -1, NE becomes a NEG and EQ becomes
5088 Remove any ZERO_EXTRACT we made when thinking this was a
5089 comparison. It may now be simpler to use, e.g., an AND. If a
5090 ZERO_EXTRACT is indeed appropriate, it will be placed back by
5091 the call to make_compound_operation in the SET case. */
5093 if (STORE_FLAG_VALUE == 1
5094 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
5095 && op1 == const0_rtx
5096 && mode == GET_MODE (op0)
5097 && nonzero_bits (op0, mode) == 1)
5098 return gen_lowpart (mode,
5099 expand_compound_operation (op0));
5101 else if (STORE_FLAG_VALUE == 1
5102 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
5103 && op1 == const0_rtx
5104 && mode == GET_MODE (op0)
5105 && (num_sign_bit_copies (op0, mode)
5106 == GET_MODE_BITSIZE (mode)))
5108 op0 = expand_compound_operation (op0);
5109 return simplify_gen_unary (NEG, mode,
5110 gen_lowpart (mode, op0),
5114 else if (STORE_FLAG_VALUE == 1
5115 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
5116 && op1 == const0_rtx
5117 && mode == GET_MODE (op0)
5118 && nonzero_bits (op0, mode) == 1)
5120 op0 = expand_compound_operation (op0);
5121 return simplify_gen_binary (XOR, mode,
5122 gen_lowpart (mode, op0),
5126 else if (STORE_FLAG_VALUE == 1
5127 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
5128 && op1 == const0_rtx
5129 && mode == GET_MODE (op0)
5130 && (num_sign_bit_copies (op0, mode)
5131 == GET_MODE_BITSIZE (mode)))
5133 op0 = expand_compound_operation (op0);
5134 return plus_constant (gen_lowpart (mode, op0), 1);
5137 /* If STORE_FLAG_VALUE is -1, we have cases similar to
5139 if (STORE_FLAG_VALUE == -1
5140 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
5141 && op1 == const0_rtx
5142 && (num_sign_bit_copies (op0, mode)
5143 == GET_MODE_BITSIZE (mode)))
5144 return gen_lowpart (mode,
5145 expand_compound_operation (op0));
5147 else if (STORE_FLAG_VALUE == -1
5148 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
5149 && op1 == const0_rtx
5150 && mode == GET_MODE (op0)
5151 && nonzero_bits (op0, mode) == 1)
5153 op0 = expand_compound_operation (op0);
5154 return simplify_gen_unary (NEG, mode,
5155 gen_lowpart (mode, op0),
5159 else if (STORE_FLAG_VALUE == -1
5160 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
5161 && op1 == const0_rtx
5162 && mode == GET_MODE (op0)
5163 && (num_sign_bit_copies (op0, mode)
5164 == GET_MODE_BITSIZE (mode)))
5166 op0 = expand_compound_operation (op0);
5167 return simplify_gen_unary (NOT, mode,
5168 gen_lowpart (mode, op0),
5172 /* If X is 0/1, (eq X 0) is X-1. */
5173 else if (STORE_FLAG_VALUE == -1
5174 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
5175 && op1 == const0_rtx
5176 && mode == GET_MODE (op0)
5177 && nonzero_bits (op0, mode) == 1)
5179 op0 = expand_compound_operation (op0);
5180 return plus_constant (gen_lowpart (mode, op0), -1);
5183 /* If STORE_FLAG_VALUE says to just test the sign bit and X has just
5184 one bit that might be nonzero, we can convert (ne x 0) to
5185 (ashift x c) where C puts the bit in the sign bit. Remove any
5186 AND with STORE_FLAG_VALUE when we are done, since we are only
5187 going to test the sign bit. */
5188 if (new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
5189 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5190 && ((STORE_FLAG_VALUE & GET_MODE_MASK (mode))
5191 == (unsigned HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (mode) - 1))
5192 && op1 == const0_rtx
5193 && mode == GET_MODE (op0)
5194 && (i = exact_log2 (nonzero_bits (op0, mode))) >= 0)
5196 x = simplify_shift_const (NULL_RTX, ASHIFT, mode,
5197 expand_compound_operation (op0),
5198 GET_MODE_BITSIZE (mode) - 1 - i);
5199 if (GET_CODE (x) == AND && XEXP (x, 1) == const_true_rtx)
5205 /* If the code changed, return a whole new comparison. */
5206 if (new_code != code)
5207 return gen_rtx_fmt_ee (new_code, mode, op0, op1);
5209 /* Otherwise, keep this operation, but maybe change its operands.
5210 This also converts (ne (compare FOO BAR) 0) to (ne FOO BAR). */
5211 SUBST (XEXP (x, 0), op0);
5212 SUBST (XEXP (x, 1), op1);
5217 return simplify_if_then_else (x);
5223 /* If we are processing SET_DEST, we are done. */
5227 return expand_compound_operation (x);
5230 return simplify_set (x);
5234 return simplify_logical (x);
5241 /* If this is a shift by a constant amount, simplify it. */
5242 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
5243 return simplify_shift_const (x, code, mode, XEXP (x, 0),
5244 INTVAL (XEXP (x, 1)));
5246 else if (SHIFT_COUNT_TRUNCATED && !REG_P (XEXP (x, 1)))
5248 force_to_mode (XEXP (x, 1), GET_MODE (XEXP (x, 1)),
5250 << exact_log2 (GET_MODE_BITSIZE (GET_MODE (x))))
5262 /* Simplify X, an IF_THEN_ELSE expression. Return the new expression. */
5265 simplify_if_then_else (rtx x)
5267 enum machine_mode mode = GET_MODE (x);
5268 rtx cond = XEXP (x, 0);
5269 rtx true_rtx = XEXP (x, 1);
5270 rtx false_rtx = XEXP (x, 2);
5271 enum rtx_code true_code = GET_CODE (cond);
5272 int comparison_p = COMPARISON_P (cond);
5275 enum rtx_code false_code;
5278 /* Simplify storing of the truth value. */
5279 if (comparison_p && true_rtx == const_true_rtx && false_rtx == const0_rtx)
5280 return simplify_gen_relational (true_code, mode, VOIDmode,
5281 XEXP (cond, 0), XEXP (cond, 1));
5283 /* Also when the truth value has to be reversed. */
5285 && true_rtx == const0_rtx && false_rtx == const_true_rtx
5286 && (reversed = reversed_comparison (cond, mode)))
5289 /* Sometimes we can simplify the arm of an IF_THEN_ELSE if a register used
5290 in it is being compared against certain values. Get the true and false
5291 comparisons and see if that says anything about the value of each arm. */
5294 && ((false_code = reversed_comparison_code (cond, NULL))
5296 && REG_P (XEXP (cond, 0)))
5299 rtx from = XEXP (cond, 0);
5300 rtx true_val = XEXP (cond, 1);
5301 rtx false_val = true_val;
5304 /* If FALSE_CODE is EQ, swap the codes and arms. */
5306 if (false_code == EQ)
5308 swapped = 1, true_code = EQ, false_code = NE;
5309 temp = true_rtx, true_rtx = false_rtx, false_rtx = temp;
5312 /* If we are comparing against zero and the expression being tested has
5313 only a single bit that might be nonzero, that is its value when it is
5314 not equal to zero. Similarly if it is known to be -1 or 0. */
5316 if (true_code == EQ && true_val == const0_rtx
5317 && exact_log2 (nzb = nonzero_bits (from, GET_MODE (from))) >= 0)
5320 false_val = GEN_INT (trunc_int_for_mode (nzb, GET_MODE (from)));
5322 else if (true_code == EQ && true_val == const0_rtx
5323 && (num_sign_bit_copies (from, GET_MODE (from))
5324 == GET_MODE_BITSIZE (GET_MODE (from))))
5327 false_val = constm1_rtx;
5330 /* Now simplify an arm if we know the value of the register in the
5331 branch and it is used in the arm. Be careful due to the potential
5332 of locally-shared RTL. */
5334 if (reg_mentioned_p (from, true_rtx))
5335 true_rtx = subst (known_cond (copy_rtx (true_rtx), true_code,
5337 pc_rtx, pc_rtx, 0, 0);
5338 if (reg_mentioned_p (from, false_rtx))
5339 false_rtx = subst (known_cond (copy_rtx (false_rtx), false_code,
5341 pc_rtx, pc_rtx, 0, 0);
5343 SUBST (XEXP (x, 1), swapped ? false_rtx : true_rtx);
5344 SUBST (XEXP (x, 2), swapped ? true_rtx : false_rtx);
5346 true_rtx = XEXP (x, 1);
5347 false_rtx = XEXP (x, 2);
5348 true_code = GET_CODE (cond);
5351 /* If we have (if_then_else FOO (pc) (label_ref BAR)) and FOO can be
5352 reversed, do so to avoid needing two sets of patterns for
5353 subtract-and-branch insns. Similarly if we have a constant in the true
5354 arm, the false arm is the same as the first operand of the comparison, or
5355 the false arm is more complicated than the true arm. */
5358 && reversed_comparison_code (cond, NULL) != UNKNOWN
5359 && (true_rtx == pc_rtx
5360 || (CONSTANT_P (true_rtx)
5361 && GET_CODE (false_rtx) != CONST_INT && false_rtx != pc_rtx)
5362 || true_rtx == const0_rtx
5363 || (OBJECT_P (true_rtx) && !OBJECT_P (false_rtx))
5364 || (GET_CODE (true_rtx) == SUBREG && OBJECT_P (SUBREG_REG (true_rtx))
5365 && !OBJECT_P (false_rtx))
5366 || reg_mentioned_p (true_rtx, false_rtx)
5367 || rtx_equal_p (false_rtx, XEXP (cond, 0))))
5369 true_code = reversed_comparison_code (cond, NULL);
5370 SUBST (XEXP (x, 0), reversed_comparison (cond, GET_MODE (cond)));
5371 SUBST (XEXP (x, 1), false_rtx);
5372 SUBST (XEXP (x, 2), true_rtx);
5374 temp = true_rtx, true_rtx = false_rtx, false_rtx = temp;
5377 /* It is possible that the conditional has been simplified out. */
5378 true_code = GET_CODE (cond);
5379 comparison_p = COMPARISON_P (cond);
5382 /* If the two arms are identical, we don't need the comparison. */
5384 if (rtx_equal_p (true_rtx, false_rtx) && ! side_effects_p (cond))
5387 /* Convert a == b ? b : a to "a". */
5388 if (true_code == EQ && ! side_effects_p (cond)
5389 && !HONOR_NANS (mode)
5390 && rtx_equal_p (XEXP (cond, 0), false_rtx)
5391 && rtx_equal_p (XEXP (cond, 1), true_rtx))
5393 else if (true_code == NE && ! side_effects_p (cond)
5394 && !HONOR_NANS (mode)
5395 && rtx_equal_p (XEXP (cond, 0), true_rtx)
5396 && rtx_equal_p (XEXP (cond, 1), false_rtx))
5399 /* Look for cases where we have (abs x) or (neg (abs X)). */
5401 if (GET_MODE_CLASS (mode) == MODE_INT
5403 && XEXP (cond, 1) == const0_rtx
5404 && GET_CODE (false_rtx) == NEG
5405 && rtx_equal_p (true_rtx, XEXP (false_rtx, 0))
5406 && rtx_equal_p (true_rtx, XEXP (cond, 0))
5407 && ! side_effects_p (true_rtx))
5412 return simplify_gen_unary (ABS, mode, true_rtx, mode);
5416 simplify_gen_unary (NEG, mode,
5417 simplify_gen_unary (ABS, mode, true_rtx, mode),
5423 /* Look for MIN or MAX. */
5425 if ((! FLOAT_MODE_P (mode) || flag_unsafe_math_optimizations)
5427 && rtx_equal_p (XEXP (cond, 0), true_rtx)
5428 && rtx_equal_p (XEXP (cond, 1), false_rtx)
5429 && ! side_effects_p (cond))
5434 return simplify_gen_binary (SMAX, mode, true_rtx, false_rtx);
5437 return simplify_gen_binary (SMIN, mode, true_rtx, false_rtx);
5440 return simplify_gen_binary (UMAX, mode, true_rtx, false_rtx);
5443 return simplify_gen_binary (UMIN, mode, true_rtx, false_rtx);
5448 /* If we have (if_then_else COND (OP Z C1) Z) and OP is an identity when its
5449 second operand is zero, this can be done as (OP Z (mult COND C2)) where
5450 C2 = C1 * STORE_FLAG_VALUE. Similarly if OP has an outer ZERO_EXTEND or
5451 SIGN_EXTEND as long as Z is already extended (so we don't destroy it).
5452 We can do this kind of thing in some cases when STORE_FLAG_VALUE is
5453 neither 1 or -1, but it isn't worth checking for. */
5455 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
5457 && GET_MODE_CLASS (mode) == MODE_INT
5458 && ! side_effects_p (x))
5460 rtx t = make_compound_operation (true_rtx, SET);
5461 rtx f = make_compound_operation (false_rtx, SET);
5462 rtx cond_op0 = XEXP (cond, 0);
5463 rtx cond_op1 = XEXP (cond, 1);
5464 enum rtx_code op = UNKNOWN, extend_op = UNKNOWN;
5465 enum machine_mode m = mode;
5466 rtx z = 0, c1 = NULL_RTX;
5468 if ((GET_CODE (t) == PLUS || GET_CODE (t) == MINUS
5469 || GET_CODE (t) == IOR || GET_CODE (t) == XOR
5470 || GET_CODE (t) == ASHIFT
5471 || GET_CODE (t) == LSHIFTRT || GET_CODE (t) == ASHIFTRT)
5472 && rtx_equal_p (XEXP (t, 0), f))
5473 c1 = XEXP (t, 1), op = GET_CODE (t), z = f;
5475 /* If an identity-zero op is commutative, check whether there
5476 would be a match if we swapped the operands. */
5477 else if ((GET_CODE (t) == PLUS || GET_CODE (t) == IOR
5478 || GET_CODE (t) == XOR)
5479 && rtx_equal_p (XEXP (t, 1), f))
5480 c1 = XEXP (t, 0), op = GET_CODE (t), z = f;
5481 else if (GET_CODE (t) == SIGN_EXTEND
5482 && (GET_CODE (XEXP (t, 0)) == PLUS
5483 || GET_CODE (XEXP (t, 0)) == MINUS
5484 || GET_CODE (XEXP (t, 0)) == IOR
5485 || GET_CODE (XEXP (t, 0)) == XOR
5486 || GET_CODE (XEXP (t, 0)) == ASHIFT
5487 || GET_CODE (XEXP (t, 0)) == LSHIFTRT
5488 || GET_CODE (XEXP (t, 0)) == ASHIFTRT)
5489 && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG
5490 && subreg_lowpart_p (XEXP (XEXP (t, 0), 0))
5491 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f)
5492 && (num_sign_bit_copies (f, GET_MODE (f))
5494 (GET_MODE_BITSIZE (mode)
5495 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t, 0), 0))))))
5497 c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0));
5498 extend_op = SIGN_EXTEND;
5499 m = GET_MODE (XEXP (t, 0));
5501 else if (GET_CODE (t) == SIGN_EXTEND
5502 && (GET_CODE (XEXP (t, 0)) == PLUS
5503 || GET_CODE (XEXP (t, 0)) == IOR
5504 || GET_CODE (XEXP (t, 0)) == XOR)
5505 && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG
5506 && subreg_lowpart_p (XEXP (XEXP (t, 0), 1))
5507 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f)
5508 && (num_sign_bit_copies (f, GET_MODE (f))
5510 (GET_MODE_BITSIZE (mode)
5511 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t, 0), 1))))))
5513 c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0));
5514 extend_op = SIGN_EXTEND;
5515 m = GET_MODE (XEXP (t, 0));
5517 else if (GET_CODE (t) == ZERO_EXTEND
5518 && (GET_CODE (XEXP (t, 0)) == PLUS
5519 || GET_CODE (XEXP (t, 0)) == MINUS
5520 || GET_CODE (XEXP (t, 0)) == IOR
5521 || GET_CODE (XEXP (t, 0)) == XOR
5522 || GET_CODE (XEXP (t, 0)) == ASHIFT
5523 || GET_CODE (XEXP (t, 0)) == LSHIFTRT
5524 || GET_CODE (XEXP (t, 0)) == ASHIFTRT)
5525 && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG
5526 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5527 && subreg_lowpart_p (XEXP (XEXP (t, 0), 0))
5528 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f)
5529 && ((nonzero_bits (f, GET_MODE (f))
5530 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t, 0), 0))))
5533 c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0));
5534 extend_op = ZERO_EXTEND;
5535 m = GET_MODE (XEXP (t, 0));
5537 else if (GET_CODE (t) == ZERO_EXTEND
5538 && (GET_CODE (XEXP (t, 0)) == PLUS
5539 || GET_CODE (XEXP (t, 0)) == IOR
5540 || GET_CODE (XEXP (t, 0)) == XOR)
5541 && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG
5542 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5543 && subreg_lowpart_p (XEXP (XEXP (t, 0), 1))
5544 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f)
5545 && ((nonzero_bits (f, GET_MODE (f))
5546 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t, 0), 1))))
5549 c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0));
5550 extend_op = ZERO_EXTEND;
5551 m = GET_MODE (XEXP (t, 0));
5556 temp = subst (simplify_gen_relational (true_code, m, VOIDmode,
5557 cond_op0, cond_op1),
5558 pc_rtx, pc_rtx, 0, 0);
5559 temp = simplify_gen_binary (MULT, m, temp,
5560 simplify_gen_binary (MULT, m, c1,
5562 temp = subst (temp, pc_rtx, pc_rtx, 0, 0);
5563 temp = simplify_gen_binary (op, m, gen_lowpart (m, z), temp);
5565 if (extend_op != UNKNOWN)
5566 temp = simplify_gen_unary (extend_op, mode, temp, m);
5572 /* If we have (if_then_else (ne A 0) C1 0) and either A is known to be 0 or
5573 1 and C1 is a single bit or A is known to be 0 or -1 and C1 is the
5574 negation of a single bit, we can convert this operation to a shift. We
5575 can actually do this more generally, but it doesn't seem worth it. */
5577 if (true_code == NE && XEXP (cond, 1) == const0_rtx
5578 && false_rtx == const0_rtx && GET_CODE (true_rtx) == CONST_INT
5579 && ((1 == nonzero_bits (XEXP (cond, 0), mode)
5580 && (i = exact_log2 (INTVAL (true_rtx))) >= 0)
5581 || ((num_sign_bit_copies (XEXP (cond, 0), mode)
5582 == GET_MODE_BITSIZE (mode))
5583 && (i = exact_log2 (-INTVAL (true_rtx))) >= 0)))
5585 simplify_shift_const (NULL_RTX, ASHIFT, mode,
5586 gen_lowpart (mode, XEXP (cond, 0)), i);
5588 /* (IF_THEN_ELSE (NE REG 0) (0) (8)) is REG for nonzero_bits (REG) == 8. */
5589 if (true_code == NE && XEXP (cond, 1) == const0_rtx
5590 && false_rtx == const0_rtx && GET_CODE (true_rtx) == CONST_INT
5591 && GET_MODE (XEXP (cond, 0)) == mode
5592 && (INTVAL (true_rtx) & GET_MODE_MASK (mode))
5593 == nonzero_bits (XEXP (cond, 0), mode)
5594 && (i = exact_log2 (INTVAL (true_rtx) & GET_MODE_MASK (mode))) >= 0)
5595 return XEXP (cond, 0);
5600 /* Simplify X, a SET expression. Return the new expression. */
5603 simplify_set (rtx x)
5605 rtx src = SET_SRC (x);
5606 rtx dest = SET_DEST (x);
5607 enum machine_mode mode
5608 = GET_MODE (src) != VOIDmode ? GET_MODE (src) : GET_MODE (dest);
5612 /* (set (pc) (return)) gets written as (return). */
5613 if (GET_CODE (dest) == PC && GET_CODE (src) == RETURN)
5616 /* Now that we know for sure which bits of SRC we are using, see if we can
5617 simplify the expression for the object knowing that we only need the
5620 if (GET_MODE_CLASS (mode) == MODE_INT
5621 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
5623 src = force_to_mode (src, mode, ~(HOST_WIDE_INT) 0, 0);
5624 SUBST (SET_SRC (x), src);
5627 /* If we are setting CC0 or if the source is a COMPARE, look for the use of
5628 the comparison result and try to simplify it unless we already have used
5629 undobuf.other_insn. */
5630 if ((GET_MODE_CLASS (mode) == MODE_CC
5631 || GET_CODE (src) == COMPARE
5633 && (cc_use = find_single_use (dest, subst_insn, &other_insn)) != 0
5634 && (undobuf.other_insn == 0 || other_insn == undobuf.other_insn)
5635 && COMPARISON_P (*cc_use)
5636 && rtx_equal_p (XEXP (*cc_use, 0), dest))
5638 enum rtx_code old_code = GET_CODE (*cc_use);
5639 enum rtx_code new_code;
5641 int other_changed = 0;
5642 enum machine_mode compare_mode = GET_MODE (dest);
5644 if (GET_CODE (src) == COMPARE)
5645 op0 = XEXP (src, 0), op1 = XEXP (src, 1);
5647 op0 = src, op1 = CONST0_RTX (GET_MODE (src));
5649 tmp = simplify_relational_operation (old_code, compare_mode, VOIDmode,
5652 new_code = old_code;
5653 else if (!CONSTANT_P (tmp))
5655 new_code = GET_CODE (tmp);
5656 op0 = XEXP (tmp, 0);
5657 op1 = XEXP (tmp, 1);
5661 rtx pat = PATTERN (other_insn);
5662 undobuf.other_insn = other_insn;
5663 SUBST (*cc_use, tmp);
5665 /* Attempt to simplify CC user. */
5666 if (GET_CODE (pat) == SET)
5668 rtx new = simplify_rtx (SET_SRC (pat));
5669 if (new != NULL_RTX)
5670 SUBST (SET_SRC (pat), new);
5673 /* Convert X into a no-op move. */
5674 SUBST (SET_DEST (x), pc_rtx);
5675 SUBST (SET_SRC (x), pc_rtx);
5679 /* Simplify our comparison, if possible. */
5680 new_code = simplify_comparison (new_code, &op0, &op1);
5682 #ifdef SELECT_CC_MODE
5683 /* If this machine has CC modes other than CCmode, check to see if we
5684 need to use a different CC mode here. */
5685 if (GET_MODE_CLASS (GET_MODE (op0)) == MODE_CC)
5686 compare_mode = GET_MODE (op0);
5688 compare_mode = SELECT_CC_MODE (new_code, op0, op1);
5691 /* If the mode changed, we have to change SET_DEST, the mode in the
5692 compare, and the mode in the place SET_DEST is used. If SET_DEST is
5693 a hard register, just build new versions with the proper mode. If it
5694 is a pseudo, we lose unless it is only time we set the pseudo, in
5695 which case we can safely change its mode. */
5696 if (compare_mode != GET_MODE (dest))
5698 if (can_change_dest_mode (dest, 0, compare_mode))
5700 unsigned int regno = REGNO (dest);
5703 if (regno < FIRST_PSEUDO_REGISTER)
5704 new_dest = gen_rtx_REG (compare_mode, regno);
5707 SUBST_MODE (regno_reg_rtx[regno], compare_mode);
5708 new_dest = regno_reg_rtx[regno];
5711 SUBST (SET_DEST (x), new_dest);
5712 SUBST (XEXP (*cc_use, 0), new_dest);
5719 #endif /* SELECT_CC_MODE */
5721 /* If the code changed, we have to build a new comparison in
5722 undobuf.other_insn. */
5723 if (new_code != old_code)
5725 int other_changed_previously = other_changed;
5726 unsigned HOST_WIDE_INT mask;
5728 SUBST (*cc_use, gen_rtx_fmt_ee (new_code, GET_MODE (*cc_use),
5732 /* If the only change we made was to change an EQ into an NE or
5733 vice versa, OP0 has only one bit that might be nonzero, and OP1
5734 is zero, check if changing the user of the condition code will
5735 produce a valid insn. If it won't, we can keep the original code
5736 in that insn by surrounding our operation with an XOR. */
5738 if (((old_code == NE && new_code == EQ)
5739 || (old_code == EQ && new_code == NE))
5740 && ! other_changed_previously && op1 == const0_rtx
5741 && GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
5742 && exact_log2 (mask = nonzero_bits (op0, GET_MODE (op0))) >= 0)
5744 rtx pat = PATTERN (other_insn), note = 0;
5746 if ((recog_for_combine (&pat, other_insn, ¬e) < 0
5747 && ! check_asm_operands (pat)))
5749 PUT_CODE (*cc_use, old_code);
5752 op0 = simplify_gen_binary (XOR, GET_MODE (op0),
5753 op0, GEN_INT (mask));
5759 undobuf.other_insn = other_insn;
5762 /* If we are now comparing against zero, change our source if
5763 needed. If we do not use cc0, we always have a COMPARE. */
5764 if (op1 == const0_rtx && dest == cc0_rtx)
5766 SUBST (SET_SRC (x), op0);
5772 /* Otherwise, if we didn't previously have a COMPARE in the
5773 correct mode, we need one. */
5774 if (GET_CODE (src) != COMPARE || GET_MODE (src) != compare_mode)
5776 SUBST (SET_SRC (x), gen_rtx_COMPARE (compare_mode, op0, op1));
5779 else if (GET_MODE (op0) == compare_mode && op1 == const0_rtx)
5781 SUBST (SET_SRC (x), op0);
5784 /* Otherwise, update the COMPARE if needed. */
5785 else if (XEXP (src, 0) != op0 || XEXP (src, 1) != op1)
5787 SUBST (SET_SRC (x), gen_rtx_COMPARE (compare_mode, op0, op1));
5793 /* Get SET_SRC in a form where we have placed back any
5794 compound expressions. Then do the checks below. */
5795 src = make_compound_operation (src, SET);
5796 SUBST (SET_SRC (x), src);
5799 /* If we have (set x (subreg:m1 (op:m2 ...) 0)) with OP being some operation,
5800 and X being a REG or (subreg (reg)), we may be able to convert this to
5801 (set (subreg:m2 x) (op)).
5803 We can always do this if M1 is narrower than M2 because that means that
5804 we only care about the low bits of the result.
5806 However, on machines without WORD_REGISTER_OPERATIONS defined, we cannot
5807 perform a narrower operation than requested since the high-order bits will
5808 be undefined. On machine where it is defined, this transformation is safe
5809 as long as M1 and M2 have the same number of words. */
5811 if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src)
5812 && !OBJECT_P (SUBREG_REG (src))
5813 && (((GET_MODE_SIZE (GET_MODE (src)) + (UNITS_PER_WORD - 1))
5815 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (src)))
5816 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD))
5817 #ifndef WORD_REGISTER_OPERATIONS
5818 && (GET_MODE_SIZE (GET_MODE (src))
5819 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (src))))
5821 #ifdef CANNOT_CHANGE_MODE_CLASS
5822 && ! (REG_P (dest) && REGNO (dest) < FIRST_PSEUDO_REGISTER
5823 && REG_CANNOT_CHANGE_MODE_P (REGNO (dest),
5824 GET_MODE (SUBREG_REG (src)),
5828 || (GET_CODE (dest) == SUBREG
5829 && REG_P (SUBREG_REG (dest)))))
5831 SUBST (SET_DEST (x),
5832 gen_lowpart (GET_MODE (SUBREG_REG (src)),
5834 SUBST (SET_SRC (x), SUBREG_REG (src));
5836 src = SET_SRC (x), dest = SET_DEST (x);
5840 /* If we have (set (cc0) (subreg ...)), we try to remove the subreg
5843 && GET_CODE (src) == SUBREG
5844 && subreg_lowpart_p (src)
5845 && (GET_MODE_BITSIZE (GET_MODE (src))
5846 < GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (src)))))
5848 rtx inner = SUBREG_REG (src);
5849 enum machine_mode inner_mode = GET_MODE (inner);
5851 /* Here we make sure that we don't have a sign bit on. */
5852 if (GET_MODE_BITSIZE (inner_mode) <= HOST_BITS_PER_WIDE_INT
5853 && (nonzero_bits (inner, inner_mode)
5854 < ((unsigned HOST_WIDE_INT) 1
5855 << (GET_MODE_BITSIZE (GET_MODE (src)) - 1))))
5857 SUBST (SET_SRC (x), inner);
5863 #ifdef LOAD_EXTEND_OP
5864 /* If we have (set FOO (subreg:M (mem:N BAR) 0)) with M wider than N, this
5865 would require a paradoxical subreg. Replace the subreg with a
5866 zero_extend to avoid the reload that would otherwise be required. */
5868 if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src)
5869 && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src))) != UNKNOWN
5870 && SUBREG_BYTE (src) == 0
5871 && (GET_MODE_SIZE (GET_MODE (src))
5872 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (src))))
5873 && MEM_P (SUBREG_REG (src)))
5876 gen_rtx_fmt_e (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src))),
5877 GET_MODE (src), SUBREG_REG (src)));
5883 /* If we don't have a conditional move, SET_SRC is an IF_THEN_ELSE, and we
5884 are comparing an item known to be 0 or -1 against 0, use a logical
5885 operation instead. Check for one of the arms being an IOR of the other
5886 arm with some value. We compute three terms to be IOR'ed together. In
5887 practice, at most two will be nonzero. Then we do the IOR's. */
5889 if (GET_CODE (dest) != PC
5890 && GET_CODE (src) == IF_THEN_ELSE
5891 && GET_MODE_CLASS (GET_MODE (src)) == MODE_INT
5892 && (GET_CODE (XEXP (src, 0)) == EQ || GET_CODE (XEXP (src, 0)) == NE)
5893 && XEXP (XEXP (src, 0), 1) == const0_rtx
5894 && GET_MODE (src) == GET_MODE (XEXP (XEXP (src, 0), 0))
5895 #ifdef HAVE_conditional_move
5896 && ! can_conditionally_move_p (GET_MODE (src))
5898 && (num_sign_bit_copies (XEXP (XEXP (src, 0), 0),
5899 GET_MODE (XEXP (XEXP (src, 0), 0)))
5900 == GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (src, 0), 0))))
5901 && ! side_effects_p (src))
5903 rtx true_rtx = (GET_CODE (XEXP (src, 0)) == NE
5904 ? XEXP (src, 1) : XEXP (src, 2));
5905 rtx false_rtx = (GET_CODE (XEXP (src, 0)) == NE
5906 ? XEXP (src, 2) : XEXP (src, 1));
5907 rtx term1 = const0_rtx, term2, term3;
5909 if (GET_CODE (true_rtx) == IOR
5910 && rtx_equal_p (XEXP (true_rtx, 0), false_rtx))
5911 term1 = false_rtx, true_rtx = XEXP (true_rtx, 1), false_rtx = const0_rtx;
5912 else if (GET_CODE (true_rtx) == IOR
5913 && rtx_equal_p (XEXP (true_rtx, 1), false_rtx))
5914 term1 = false_rtx, true_rtx = XEXP (true_rtx, 0), false_rtx = const0_rtx;
5915 else if (GET_CODE (false_rtx) == IOR
5916 && rtx_equal_p (XEXP (false_rtx, 0), true_rtx))
5917 term1 = true_rtx, false_rtx = XEXP (false_rtx, 1), true_rtx = const0_rtx;
5918 else if (GET_CODE (false_rtx) == IOR
5919 && rtx_equal_p (XEXP (false_rtx, 1), true_rtx))
5920 term1 = true_rtx, false_rtx = XEXP (false_rtx, 0), true_rtx = const0_rtx;
5922 term2 = simplify_gen_binary (AND, GET_MODE (src),
5923 XEXP (XEXP (src, 0), 0), true_rtx);
5924 term3 = simplify_gen_binary (AND, GET_MODE (src),
5925 simplify_gen_unary (NOT, GET_MODE (src),
5926 XEXP (XEXP (src, 0), 0),
5931 simplify_gen_binary (IOR, GET_MODE (src),
5932 simplify_gen_binary (IOR, GET_MODE (src),
5939 /* If either SRC or DEST is a CLOBBER of (const_int 0), make this
5940 whole thing fail. */
5941 if (GET_CODE (src) == CLOBBER && XEXP (src, 0) == const0_rtx)
5943 else if (GET_CODE (dest) == CLOBBER && XEXP (dest, 0) == const0_rtx)
5946 /* Convert this into a field assignment operation, if possible. */
5947 return make_field_assignment (x);
5950 /* Simplify, X, and AND, IOR, or XOR operation, and return the simplified
5954 simplify_logical (rtx x)
5956 enum machine_mode mode = GET_MODE (x);
5957 rtx op0 = XEXP (x, 0);
5958 rtx op1 = XEXP (x, 1);
5960 switch (GET_CODE (x))
5963 /* We can call simplify_and_const_int only if we don't lose
5964 any (sign) bits when converting INTVAL (op1) to
5965 "unsigned HOST_WIDE_INT". */
5966 if (GET_CODE (op1) == CONST_INT
5967 && (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5968 || INTVAL (op1) > 0))
5970 x = simplify_and_const_int (x, mode, op0, INTVAL (op1));
5971 if (GET_CODE (x) != AND)
5978 /* If we have any of (and (ior A B) C) or (and (xor A B) C),
5979 apply the distributive law and then the inverse distributive
5980 law to see if things simplify. */
5981 if (GET_CODE (op0) == IOR || GET_CODE (op0) == XOR)
5983 rtx result = distribute_and_simplify_rtx (x, 0);
5987 if (GET_CODE (op1) == IOR || GET_CODE (op1) == XOR)
5989 rtx result = distribute_and_simplify_rtx (x, 1);
5996 /* If we have (ior (and A B) C), apply the distributive law and then
5997 the inverse distributive law to see if things simplify. */
5999 if (GET_CODE (op0) == AND)
6001 rtx result = distribute_and_simplify_rtx (x, 0);
6006 if (GET_CODE (op1) == AND)
6008 rtx result = distribute_and_simplify_rtx (x, 1);
6021 /* We consider ZERO_EXTRACT, SIGN_EXTRACT, and SIGN_EXTEND as "compound
6022 operations" because they can be replaced with two more basic operations.
6023 ZERO_EXTEND is also considered "compound" because it can be replaced with
6024 an AND operation, which is simpler, though only one operation.
6026 The function expand_compound_operation is called with an rtx expression
6027 and will convert it to the appropriate shifts and AND operations,
6028 simplifying at each stage.
6030 The function make_compound_operation is called to convert an expression
6031 consisting of shifts and ANDs into the equivalent compound expression.
6032 It is the inverse of this function, loosely speaking. */
6035 expand_compound_operation (rtx x)
6037 unsigned HOST_WIDE_INT pos = 0, len;
6039 unsigned int modewidth;
6042 switch (GET_CODE (x))
6047 /* We can't necessarily use a const_int for a multiword mode;
6048 it depends on implicitly extending the value.
6049 Since we don't know the right way to extend it,
6050 we can't tell whether the implicit way is right.
6052 Even for a mode that is no wider than a const_int,
6053 we can't win, because we need to sign extend one of its bits through
6054 the rest of it, and we don't know which bit. */
6055 if (GET_CODE (XEXP (x, 0)) == CONST_INT)
6058 /* Return if (subreg:MODE FROM 0) is not a safe replacement for
6059 (zero_extend:MODE FROM) or (sign_extend:MODE FROM). It is for any MEM
6060 because (SUBREG (MEM...)) is guaranteed to cause the MEM to be
6061 reloaded. If not for that, MEM's would very rarely be safe.
6063 Reject MODEs bigger than a word, because we might not be able
6064 to reference a two-register group starting with an arbitrary register
6065 (and currently gen_lowpart might crash for a SUBREG). */
6067 if (GET_MODE_SIZE (GET_MODE (XEXP (x, 0))) > UNITS_PER_WORD)
6070 /* Reject MODEs that aren't scalar integers because turning vector
6071 or complex modes into shifts causes problems. */
6073 if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x, 0))))
6076 len = GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)));
6077 /* If the inner object has VOIDmode (the only way this can happen
6078 is if it is an ASM_OPERANDS), we can't do anything since we don't
6079 know how much masking to do. */
6088 /* ... fall through ... */
6091 /* If the operand is a CLOBBER, just return it. */
6092 if (GET_CODE (XEXP (x, 0)) == CLOBBER)
6095 if (GET_CODE (XEXP (x, 1)) != CONST_INT
6096 || GET_CODE (XEXP (x, 2)) != CONST_INT
6097 || GET_MODE (XEXP (x, 0)) == VOIDmode)
6100 /* Reject MODEs that aren't scalar integers because turning vector
6101 or complex modes into shifts causes problems. */
6103 if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x, 0))))
6106 len = INTVAL (XEXP (x, 1));
6107 pos = INTVAL (XEXP (x, 2));
6109 /* This should stay within the object being extracted, fail otherwise. */
6110 if (len + pos > GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))))
6113 if (BITS_BIG_ENDIAN)
6114 pos = GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - len - pos;
6121 /* Convert sign extension to zero extension, if we know that the high
6122 bit is not set, as this is easier to optimize. It will be converted
6123 back to cheaper alternative in make_extraction. */
6124 if (GET_CODE (x) == SIGN_EXTEND
6125 && (GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
6126 && ((nonzero_bits (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
6127 & ~(((unsigned HOST_WIDE_INT)
6128 GET_MODE_MASK (GET_MODE (XEXP (x, 0))))
6132 rtx temp = gen_rtx_ZERO_EXTEND (GET_MODE (x), XEXP (x, 0));
6133 rtx temp2 = expand_compound_operation (temp);
6135 /* Make sure this is a profitable operation. */
6136 if (rtx_cost (x, SET) > rtx_cost (temp2, SET))
6138 else if (rtx_cost (x, SET) > rtx_cost (temp, SET))
6144 /* We can optimize some special cases of ZERO_EXTEND. */
6145 if (GET_CODE (x) == ZERO_EXTEND)
6147 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI if we
6148 know that the last value didn't have any inappropriate bits
6150 if (GET_CODE (XEXP (x, 0)) == TRUNCATE
6151 && GET_MODE (XEXP (XEXP (x, 0), 0)) == GET_MODE (x)
6152 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
6153 && (nonzero_bits (XEXP (XEXP (x, 0), 0), GET_MODE (x))
6154 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
6155 return XEXP (XEXP (x, 0), 0);
6157 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
6158 if (GET_CODE (XEXP (x, 0)) == SUBREG
6159 && GET_MODE (SUBREG_REG (XEXP (x, 0))) == GET_MODE (x)
6160 && subreg_lowpart_p (XEXP (x, 0))
6161 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
6162 && (nonzero_bits (SUBREG_REG (XEXP (x, 0)), GET_MODE (x))
6163 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
6164 return SUBREG_REG (XEXP (x, 0));
6166 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI when foo
6167 is a comparison and STORE_FLAG_VALUE permits. This is like
6168 the first case, but it works even when GET_MODE (x) is larger
6169 than HOST_WIDE_INT. */
6170 if (GET_CODE (XEXP (x, 0)) == TRUNCATE
6171 && GET_MODE (XEXP (XEXP (x, 0), 0)) == GET_MODE (x)
6172 && COMPARISON_P (XEXP (XEXP (x, 0), 0))
6173 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
6174 <= HOST_BITS_PER_WIDE_INT)
6175 && ((HOST_WIDE_INT) STORE_FLAG_VALUE
6176 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
6177 return XEXP (XEXP (x, 0), 0);
6179 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
6180 if (GET_CODE (XEXP (x, 0)) == SUBREG
6181 && GET_MODE (SUBREG_REG (XEXP (x, 0))) == GET_MODE (x)
6182 && subreg_lowpart_p (XEXP (x, 0))
6183 && COMPARISON_P (SUBREG_REG (XEXP (x, 0)))
6184 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
6185 <= HOST_BITS_PER_WIDE_INT)
6186 && ((HOST_WIDE_INT) STORE_FLAG_VALUE
6187 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
6188 return SUBREG_REG (XEXP (x, 0));
6192 /* If we reach here, we want to return a pair of shifts. The inner
6193 shift is a left shift of BITSIZE - POS - LEN bits. The outer
6194 shift is a right shift of BITSIZE - LEN bits. It is arithmetic or
6195 logical depending on the value of UNSIGNEDP.
6197 If this was a ZERO_EXTEND or ZERO_EXTRACT, this pair of shifts will be
6198 converted into an AND of a shift.
6200 We must check for the case where the left shift would have a negative
6201 count. This can happen in a case like (x >> 31) & 255 on machines
6202 that can't shift by a constant. On those machines, we would first
6203 combine the shift with the AND to produce a variable-position
6204 extraction. Then the constant of 31 would be substituted in to produce
6205 a such a position. */
6207 modewidth = GET_MODE_BITSIZE (GET_MODE (x));
6208 if (modewidth + len >= pos)
6210 enum machine_mode mode = GET_MODE (x);
6211 tem = gen_lowpart (mode, XEXP (x, 0));
6212 if (!tem || GET_CODE (tem) == CLOBBER)
6214 tem = simplify_shift_const (NULL_RTX, ASHIFT, mode,
6215 tem, modewidth - pos - len);
6216 tem = simplify_shift_const (NULL_RTX, unsignedp ? LSHIFTRT : ASHIFTRT,
6217 mode, tem, modewidth - len);
6219 else if (unsignedp && len < HOST_BITS_PER_WIDE_INT)
6220 tem = simplify_and_const_int (NULL_RTX, GET_MODE (x),
6221 simplify_shift_const (NULL_RTX, LSHIFTRT,
6224 ((HOST_WIDE_INT) 1 << len) - 1);
6226 /* Any other cases we can't handle. */
6229 /* If we couldn't do this for some reason, return the original
6231 if (GET_CODE (tem) == CLOBBER)
6237 /* X is a SET which contains an assignment of one object into
6238 a part of another (such as a bit-field assignment, STRICT_LOW_PART,
6239 or certain SUBREGS). If possible, convert it into a series of
6242 We half-heartedly support variable positions, but do not at all
6243 support variable lengths. */
6246 expand_field_assignment (const_rtx x)
6249 rtx pos; /* Always counts from low bit. */
6251 rtx mask, cleared, masked;
6252 enum machine_mode compute_mode;
6254 /* Loop until we find something we can't simplify. */
6257 if (GET_CODE (SET_DEST (x)) == STRICT_LOW_PART
6258 && GET_CODE (XEXP (SET_DEST (x), 0)) == SUBREG)
6260 inner = SUBREG_REG (XEXP (SET_DEST (x), 0));
6261 len = GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0)));
6262 pos = GEN_INT (subreg_lsb (XEXP (SET_DEST (x), 0)));
6264 else if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
6265 && GET_CODE (XEXP (SET_DEST (x), 1)) == CONST_INT)
6267 inner = XEXP (SET_DEST (x), 0);
6268 len = INTVAL (XEXP (SET_DEST (x), 1));
6269 pos = XEXP (SET_DEST (x), 2);
6271 /* A constant position should stay within the width of INNER. */
6272 if (GET_CODE (pos) == CONST_INT
6273 && INTVAL (pos) + len > GET_MODE_BITSIZE (GET_MODE (inner)))
6276 if (BITS_BIG_ENDIAN)
6278 if (GET_CODE (pos) == CONST_INT)
6279 pos = GEN_INT (GET_MODE_BITSIZE (GET_MODE (inner)) - len
6281 else if (GET_CODE (pos) == MINUS
6282 && GET_CODE (XEXP (pos, 1)) == CONST_INT
6283 && (INTVAL (XEXP (pos, 1))
6284 == GET_MODE_BITSIZE (GET_MODE (inner)) - len))
6285 /* If position is ADJUST - X, new position is X. */
6286 pos = XEXP (pos, 0);
6288 pos = simplify_gen_binary (MINUS, GET_MODE (pos),
6289 GEN_INT (GET_MODE_BITSIZE (
6296 /* A SUBREG between two modes that occupy the same numbers of words
6297 can be done by moving the SUBREG to the source. */
6298 else if (GET_CODE (SET_DEST (x)) == SUBREG
6299 /* We need SUBREGs to compute nonzero_bits properly. */
6300 && nonzero_sign_valid
6301 && (((GET_MODE_SIZE (GET_MODE (SET_DEST (x)))
6302 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
6303 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x))))
6304 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)))
6306 x = gen_rtx_SET (VOIDmode, SUBREG_REG (SET_DEST (x)),
6308 (GET_MODE (SUBREG_REG (SET_DEST (x))),
6315 while (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
6316 inner = SUBREG_REG (inner);
6318 compute_mode = GET_MODE (inner);
6320 /* Don't attempt bitwise arithmetic on non scalar integer modes. */
6321 if (! SCALAR_INT_MODE_P (compute_mode))
6323 enum machine_mode imode;
6325 /* Don't do anything for vector or complex integral types. */
6326 if (! FLOAT_MODE_P (compute_mode))
6329 /* Try to find an integral mode to pun with. */
6330 imode = mode_for_size (GET_MODE_BITSIZE (compute_mode), MODE_INT, 0);
6331 if (imode == BLKmode)
6334 compute_mode = imode;
6335 inner = gen_lowpart (imode, inner);
6338 /* Compute a mask of LEN bits, if we can do this on the host machine. */
6339 if (len >= HOST_BITS_PER_WIDE_INT)
6342 /* Now compute the equivalent expression. Make a copy of INNER
6343 for the SET_DEST in case it is a MEM into which we will substitute;
6344 we don't want shared RTL in that case. */
6345 mask = GEN_INT (((HOST_WIDE_INT) 1 << len) - 1);
6346 cleared = simplify_gen_binary (AND, compute_mode,
6347 simplify_gen_unary (NOT, compute_mode,
6348 simplify_gen_binary (ASHIFT,
6353 masked = simplify_gen_binary (ASHIFT, compute_mode,
6354 simplify_gen_binary (
6356 gen_lowpart (compute_mode, SET_SRC (x)),
6360 x = gen_rtx_SET (VOIDmode, copy_rtx (inner),
6361 simplify_gen_binary (IOR, compute_mode,
6368 /* Return an RTX for a reference to LEN bits of INNER. If POS_RTX is nonzero,
6369 it is an RTX that represents a variable starting position; otherwise,
6370 POS is the (constant) starting bit position (counted from the LSB).
6372 UNSIGNEDP is nonzero for an unsigned reference and zero for a
6375 IN_DEST is nonzero if this is a reference in the destination of a
6376 SET. This is used when a ZERO_ or SIGN_EXTRACT isn't needed. If nonzero,
6377 a STRICT_LOW_PART will be used, if zero, ZERO_EXTEND or SIGN_EXTEND will
6380 IN_COMPARE is nonzero if we are in a COMPARE. This means that a
6381 ZERO_EXTRACT should be built even for bits starting at bit 0.
6383 MODE is the desired mode of the result (if IN_DEST == 0).
6385 The result is an RTX for the extraction or NULL_RTX if the target
6389 make_extraction (enum machine_mode mode, rtx inner, HOST_WIDE_INT pos,
6390 rtx pos_rtx, unsigned HOST_WIDE_INT len, int unsignedp,
6391 int in_dest, int in_compare)
6393 /* This mode describes the size of the storage area
6394 to fetch the overall value from. Within that, we
6395 ignore the POS lowest bits, etc. */
6396 enum machine_mode is_mode = GET_MODE (inner);
6397 enum machine_mode inner_mode;
6398 enum machine_mode wanted_inner_mode;
6399 enum machine_mode wanted_inner_reg_mode = word_mode;
6400 enum machine_mode pos_mode = word_mode;
6401 enum machine_mode extraction_mode = word_mode;
6402 enum machine_mode tmode = mode_for_size (len, MODE_INT, 1);
6404 rtx orig_pos_rtx = pos_rtx;
6405 HOST_WIDE_INT orig_pos;
6407 if (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
6409 /* If going from (subreg:SI (mem:QI ...)) to (mem:QI ...),
6410 consider just the QI as the memory to extract from.
6411 The subreg adds or removes high bits; its mode is
6412 irrelevant to the meaning of this extraction,
6413 since POS and LEN count from the lsb. */
6414 if (MEM_P (SUBREG_REG (inner)))
6415 is_mode = GET_MODE (SUBREG_REG (inner));
6416 inner = SUBREG_REG (inner);
6418 else if (GET_CODE (inner) == ASHIFT
6419 && GET_CODE (XEXP (inner, 1)) == CONST_INT
6420 && pos_rtx == 0 && pos == 0
6421 && len > (unsigned HOST_WIDE_INT) INTVAL (XEXP (inner, 1)))
6423 /* We're extracting the least significant bits of an rtx
6424 (ashift X (const_int C)), where LEN > C. Extract the
6425 least significant (LEN - C) bits of X, giving an rtx
6426 whose mode is MODE, then shift it left C times. */
6427 new = make_extraction (mode, XEXP (inner, 0),
6428 0, 0, len - INTVAL (XEXP (inner, 1)),
6429 unsignedp, in_dest, in_compare);
6431 return gen_rtx_ASHIFT (mode, new, XEXP (inner, 1));
6434 inner_mode = GET_MODE (inner);
6436 if (pos_rtx && GET_CODE (pos_rtx) == CONST_INT)
6437 pos = INTVAL (pos_rtx), pos_rtx = 0;
6439 /* See if this can be done without an extraction. We never can if the
6440 width of the field is not the same as that of some integer mode. For
6441 registers, we can only avoid the extraction if the position is at the
6442 low-order bit and this is either not in the destination or we have the
6443 appropriate STRICT_LOW_PART operation available.
6445 For MEM, we can avoid an extract if the field starts on an appropriate
6446 boundary and we can change the mode of the memory reference. */
6448 if (tmode != BLKmode
6449 && ((pos_rtx == 0 && (pos % BITS_PER_WORD) == 0
6451 && (inner_mode == tmode
6453 || TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (tmode),
6454 GET_MODE_BITSIZE (inner_mode))
6455 || reg_truncated_to_mode (tmode, inner))
6458 && have_insn_for (STRICT_LOW_PART, tmode))))
6459 || (MEM_P (inner) && pos_rtx == 0
6461 % (STRICT_ALIGNMENT ? GET_MODE_ALIGNMENT (tmode)
6462 : BITS_PER_UNIT)) == 0
6463 /* We can't do this if we are widening INNER_MODE (it
6464 may not be aligned, for one thing). */
6465 && GET_MODE_BITSIZE (inner_mode) >= GET_MODE_BITSIZE (tmode)
6466 && (inner_mode == tmode
6467 || (! mode_dependent_address_p (XEXP (inner, 0))
6468 && ! MEM_VOLATILE_P (inner))))))
6470 /* If INNER is a MEM, make a new MEM that encompasses just the desired
6471 field. If the original and current mode are the same, we need not
6472 adjust the offset. Otherwise, we do if bytes big endian.
6474 If INNER is not a MEM, get a piece consisting of just the field
6475 of interest (in this case POS % BITS_PER_WORD must be 0). */
6479 HOST_WIDE_INT offset;
6481 /* POS counts from lsb, but make OFFSET count in memory order. */
6482 if (BYTES_BIG_ENDIAN)
6483 offset = (GET_MODE_BITSIZE (is_mode) - len - pos) / BITS_PER_UNIT;
6485 offset = pos / BITS_PER_UNIT;
6487 new = adjust_address_nv (inner, tmode, offset);
6489 else if (REG_P (inner))
6491 if (tmode != inner_mode)
6493 /* We can't call gen_lowpart in a DEST since we
6494 always want a SUBREG (see below) and it would sometimes
6495 return a new hard register. */
6498 HOST_WIDE_INT final_word = pos / BITS_PER_WORD;
6500 if (WORDS_BIG_ENDIAN
6501 && GET_MODE_SIZE (inner_mode) > UNITS_PER_WORD)
6502 final_word = ((GET_MODE_SIZE (inner_mode)
6503 - GET_MODE_SIZE (tmode))
6504 / UNITS_PER_WORD) - final_word;
6506 final_word *= UNITS_PER_WORD;
6507 if (BYTES_BIG_ENDIAN &&
6508 GET_MODE_SIZE (inner_mode) > GET_MODE_SIZE (tmode))
6509 final_word += (GET_MODE_SIZE (inner_mode)
6510 - GET_MODE_SIZE (tmode)) % UNITS_PER_WORD;
6512 /* Avoid creating invalid subregs, for example when
6513 simplifying (x>>32)&255. */
6514 if (!validate_subreg (tmode, inner_mode, inner, final_word))
6517 new = gen_rtx_SUBREG (tmode, inner, final_word);
6520 new = gen_lowpart (tmode, inner);
6526 new = force_to_mode (inner, tmode,
6527 len >= HOST_BITS_PER_WIDE_INT
6528 ? ~(unsigned HOST_WIDE_INT) 0
6529 : ((unsigned HOST_WIDE_INT) 1 << len) - 1,
6532 /* If this extraction is going into the destination of a SET,
6533 make a STRICT_LOW_PART unless we made a MEM. */
6536 return (MEM_P (new) ? new
6537 : (GET_CODE (new) != SUBREG
6538 ? gen_rtx_CLOBBER (tmode, const0_rtx)
6539 : gen_rtx_STRICT_LOW_PART (VOIDmode, new)));
6544 if (GET_CODE (new) == CONST_INT)
6545 return gen_int_mode (INTVAL (new), mode);
6547 /* If we know that no extraneous bits are set, and that the high
6548 bit is not set, convert the extraction to the cheaper of
6549 sign and zero extension, that are equivalent in these cases. */
6550 if (flag_expensive_optimizations
6551 && (GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT
6552 && ((nonzero_bits (new, tmode)
6553 & ~(((unsigned HOST_WIDE_INT)
6554 GET_MODE_MASK (tmode))
6558 rtx temp = gen_rtx_ZERO_EXTEND (mode, new);
6559 rtx temp1 = gen_rtx_SIGN_EXTEND (mode, new);
6561 /* Prefer ZERO_EXTENSION, since it gives more information to
6563 if (rtx_cost (temp, SET) <= rtx_cost (temp1, SET))
6568 /* Otherwise, sign- or zero-extend unless we already are in the
6571 return (gen_rtx_fmt_e (unsignedp ? ZERO_EXTEND : SIGN_EXTEND,
6575 /* Unless this is a COMPARE or we have a funny memory reference,
6576 don't do anything with zero-extending field extracts starting at
6577 the low-order bit since they are simple AND operations. */
6578 if (pos_rtx == 0 && pos == 0 && ! in_dest
6579 && ! in_compare && unsignedp)
6582 /* Unless INNER is not MEM, reject this if we would be spanning bytes or
6583 if the position is not a constant and the length is not 1. In all
6584 other cases, we would only be going outside our object in cases when
6585 an original shift would have been undefined. */
6587 && ((pos_rtx == 0 && pos + len > GET_MODE_BITSIZE (is_mode))
6588 || (pos_rtx != 0 && len != 1)))
6591 /* Get the mode to use should INNER not be a MEM, the mode for the position,
6592 and the mode for the result. */
6593 if (in_dest && mode_for_extraction (EP_insv, -1) != MAX_MACHINE_MODE)
6595 wanted_inner_reg_mode = mode_for_extraction (EP_insv, 0);
6596 pos_mode = mode_for_extraction (EP_insv, 2);
6597 extraction_mode = mode_for_extraction (EP_insv, 3);
6600 if (! in_dest && unsignedp
6601 && mode_for_extraction (EP_extzv, -1) != MAX_MACHINE_MODE)
6603 wanted_inner_reg_mode = mode_for_extraction (EP_extzv, 1);
6604 pos_mode = mode_for_extraction (EP_extzv, 3);
6605 extraction_mode = mode_for_extraction (EP_extzv, 0);
6608 if (! in_dest && ! unsignedp
6609 && mode_for_extraction (EP_extv, -1) != MAX_MACHINE_MODE)
6611 wanted_inner_reg_mode = mode_for_extraction (EP_extv, 1);
6612 pos_mode = mode_for_extraction (EP_extv, 3);
6613 extraction_mode = mode_for_extraction (EP_extv, 0);
6616 /* Never narrow an object, since that might not be safe. */
6618 if (mode != VOIDmode
6619 && GET_MODE_SIZE (extraction_mode) < GET_MODE_SIZE (mode))
6620 extraction_mode = mode;
6622 if (pos_rtx && GET_MODE (pos_rtx) != VOIDmode
6623 && GET_MODE_SIZE (pos_mode) < GET_MODE_SIZE (GET_MODE (pos_rtx)))
6624 pos_mode = GET_MODE (pos_rtx);
6626 /* If this is not from memory, the desired mode is the preferred mode
6627 for an extraction pattern's first input operand, or word_mode if there
6630 wanted_inner_mode = wanted_inner_reg_mode;
6633 /* Be careful not to go beyond the extracted object and maintain the
6634 natural alignment of the memory. */
6635 wanted_inner_mode = smallest_mode_for_size (len, MODE_INT);
6636 while (pos % GET_MODE_BITSIZE (wanted_inner_mode) + len
6637 > GET_MODE_BITSIZE (wanted_inner_mode))
6639 wanted_inner_mode = GET_MODE_WIDER_MODE (wanted_inner_mode);
6640 gcc_assert (wanted_inner_mode != VOIDmode);
6643 /* If we have to change the mode of memory and cannot, the desired mode
6644 is EXTRACTION_MODE. */
6645 if (inner_mode != wanted_inner_mode
6646 && (mode_dependent_address_p (XEXP (inner, 0))
6647 || MEM_VOLATILE_P (inner)
6649 wanted_inner_mode = extraction_mode;
6654 if (BITS_BIG_ENDIAN)
6656 /* POS is passed as if BITS_BIG_ENDIAN == 0, so we need to convert it to
6657 BITS_BIG_ENDIAN style. If position is constant, compute new
6658 position. Otherwise, build subtraction.
6659 Note that POS is relative to the mode of the original argument.
6660 If it's a MEM we need to recompute POS relative to that.
6661 However, if we're extracting from (or inserting into) a register,
6662 we want to recompute POS relative to wanted_inner_mode. */
6663 int width = (MEM_P (inner)
6664 ? GET_MODE_BITSIZE (is_mode)
6665 : GET_MODE_BITSIZE (wanted_inner_mode));
6668 pos = width - len - pos;
6671 = gen_rtx_MINUS (GET_MODE (pos_rtx), GEN_INT (width - len), pos_rtx);
6672 /* POS may be less than 0 now, but we check for that below.
6673 Note that it can only be less than 0 if !MEM_P (inner). */
6676 /* If INNER has a wider mode, and this is a constant extraction, try to
6677 make it smaller and adjust the byte to point to the byte containing
6679 if (wanted_inner_mode != VOIDmode
6680 && inner_mode != wanted_inner_mode
6682 && GET_MODE_SIZE (wanted_inner_mode) < GET_MODE_SIZE (is_mode)
6684 && ! mode_dependent_address_p (XEXP (inner, 0))
6685 && ! MEM_VOLATILE_P (inner))
6689 /* The computations below will be correct if the machine is big
6690 endian in both bits and bytes or little endian in bits and bytes.
6691 If it is mixed, we must adjust. */
6693 /* If bytes are big endian and we had a paradoxical SUBREG, we must
6694 adjust OFFSET to compensate. */
6695 if (BYTES_BIG_ENDIAN
6696 && GET_MODE_SIZE (inner_mode) < GET_MODE_SIZE (is_mode))
6697 offset -= GET_MODE_SIZE (is_mode) - GET_MODE_SIZE (inner_mode);
6699 /* We can now move to the desired byte. */
6700 offset += (pos / GET_MODE_BITSIZE (wanted_inner_mode))
6701 * GET_MODE_SIZE (wanted_inner_mode);
6702 pos %= GET_MODE_BITSIZE (wanted_inner_mode);
6704 if (BYTES_BIG_ENDIAN != BITS_BIG_ENDIAN
6705 && is_mode != wanted_inner_mode)
6706 offset = (GET_MODE_SIZE (is_mode)
6707 - GET_MODE_SIZE (wanted_inner_mode) - offset);
6709 inner = adjust_address_nv (inner, wanted_inner_mode, offset);
6712 /* If INNER is not memory, we can always get it into the proper mode. If we
6713 are changing its mode, POS must be a constant and smaller than the size
6715 else if (!MEM_P (inner))
6717 if (GET_MODE (inner) != wanted_inner_mode
6719 || orig_pos + len > GET_MODE_BITSIZE (wanted_inner_mode)))
6725 inner = force_to_mode (inner, wanted_inner_mode,
6727 || len + orig_pos >= HOST_BITS_PER_WIDE_INT
6728 ? ~(unsigned HOST_WIDE_INT) 0
6729 : ((((unsigned HOST_WIDE_INT) 1 << len) - 1)
6734 /* Adjust mode of POS_RTX, if needed. If we want a wider mode, we
6735 have to zero extend. Otherwise, we can just use a SUBREG. */
6737 && GET_MODE_SIZE (pos_mode) > GET_MODE_SIZE (GET_MODE (pos_rtx)))
6739 rtx temp = gen_rtx_ZERO_EXTEND (pos_mode, pos_rtx);
6741 /* If we know that no extraneous bits are set, and that the high
6742 bit is not set, convert extraction to cheaper one - either
6743 SIGN_EXTENSION or ZERO_EXTENSION, that are equivalent in these
6745 if (flag_expensive_optimizations
6746 && (GET_MODE_BITSIZE (GET_MODE (pos_rtx)) <= HOST_BITS_PER_WIDE_INT
6747 && ((nonzero_bits (pos_rtx, GET_MODE (pos_rtx))
6748 & ~(((unsigned HOST_WIDE_INT)
6749 GET_MODE_MASK (GET_MODE (pos_rtx)))
6753 rtx temp1 = gen_rtx_SIGN_EXTEND (pos_mode, pos_rtx);
6755 /* Prefer ZERO_EXTENSION, since it gives more information to
6757 if (rtx_cost (temp1, SET) < rtx_cost (temp, SET))
6762 else if (pos_rtx != 0
6763 && GET_MODE_SIZE (pos_mode) < GET_MODE_SIZE (GET_MODE (pos_rtx)))
6764 pos_rtx = gen_lowpart (pos_mode, pos_rtx);
6766 /* Make POS_RTX unless we already have it and it is correct. If we don't
6767 have a POS_RTX but we do have an ORIG_POS_RTX, the latter must
6769 if (pos_rtx == 0 && orig_pos_rtx != 0 && INTVAL (orig_pos_rtx) == pos)
6770 pos_rtx = orig_pos_rtx;
6772 else if (pos_rtx == 0)
6773 pos_rtx = GEN_INT (pos);
6775 /* Make the required operation. See if we can use existing rtx. */
6776 new = gen_rtx_fmt_eee (unsignedp ? ZERO_EXTRACT : SIGN_EXTRACT,
6777 extraction_mode, inner, GEN_INT (len), pos_rtx);
6779 new = gen_lowpart (mode, new);
6784 /* See if X contains an ASHIFT of COUNT or more bits that can be commuted
6785 with any other operations in X. Return X without that shift if so. */
6788 extract_left_shift (rtx x, int count)
6790 enum rtx_code code = GET_CODE (x);
6791 enum machine_mode mode = GET_MODE (x);
6797 /* This is the shift itself. If it is wide enough, we will return
6798 either the value being shifted if the shift count is equal to
6799 COUNT or a shift for the difference. */
6800 if (GET_CODE (XEXP (x, 1)) == CONST_INT
6801 && INTVAL (XEXP (x, 1)) >= count)
6802 return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (x, 0),
6803 INTVAL (XEXP (x, 1)) - count);
6807 if ((tem = extract_left_shift (XEXP (x, 0), count)) != 0)
6808 return simplify_gen_unary (code, mode, tem, mode);
6812 case PLUS: case IOR: case XOR: case AND:
6813 /* If we can safely shift this constant and we find the inner shift,
6814 make a new operation. */
6815 if (GET_CODE (XEXP (x, 1)) == CONST_INT
6816 && (INTVAL (XEXP (x, 1)) & ((((HOST_WIDE_INT) 1 << count)) - 1)) == 0
6817 && (tem = extract_left_shift (XEXP (x, 0), count)) != 0)
6818 return simplify_gen_binary (code, mode, tem,
6819 GEN_INT (INTVAL (XEXP (x, 1)) >> count));
6830 /* Look at the expression rooted at X. Look for expressions
6831 equivalent to ZERO_EXTRACT, SIGN_EXTRACT, ZERO_EXTEND, SIGN_EXTEND.
6832 Form these expressions.
6834 Return the new rtx, usually just X.
6836 Also, for machines like the VAX that don't have logical shift insns,
6837 try to convert logical to arithmetic shift operations in cases where
6838 they are equivalent. This undoes the canonicalizations to logical
6839 shifts done elsewhere.
6841 We try, as much as possible, to re-use rtl expressions to save memory.
6843 IN_CODE says what kind of expression we are processing. Normally, it is
6844 SET. In a memory address (inside a MEM, PLUS or minus, the latter two
6845 being kludges), it is MEM. When processing the arguments of a comparison
6846 or a COMPARE against zero, it is COMPARE. */
6849 make_compound_operation (rtx x, enum rtx_code in_code)
6851 enum rtx_code code = GET_CODE (x);
6852 enum machine_mode mode = GET_MODE (x);
6853 int mode_width = GET_MODE_BITSIZE (mode);
6855 enum rtx_code next_code;
6861 /* Select the code to be used in recursive calls. Once we are inside an
6862 address, we stay there. If we have a comparison, set to COMPARE,
6863 but once inside, go back to our default of SET. */
6865 next_code = (code == MEM || code == PLUS || code == MINUS ? MEM
6866 : ((code == COMPARE || COMPARISON_P (x))
6867 && XEXP (x, 1) == const0_rtx) ? COMPARE
6868 : in_code == COMPARE ? SET : in_code);
6870 /* Process depending on the code of this operation. If NEW is set
6871 nonzero, it will be returned. */
6876 /* Convert shifts by constants into multiplications if inside
6878 if (in_code == MEM && GET_CODE (XEXP (x, 1)) == CONST_INT
6879 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT
6880 && INTVAL (XEXP (x, 1)) >= 0)
6882 new = make_compound_operation (XEXP (x, 0), next_code);
6883 new = gen_rtx_MULT (mode, new,
6884 GEN_INT ((HOST_WIDE_INT) 1
6885 << INTVAL (XEXP (x, 1))));
6890 /* If the second operand is not a constant, we can't do anything
6892 if (GET_CODE (XEXP (x, 1)) != CONST_INT)
6895 /* If the constant is a power of two minus one and the first operand
6896 is a logical right shift, make an extraction. */
6897 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
6898 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6900 new = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code);
6901 new = make_extraction (mode, new, 0, XEXP (XEXP (x, 0), 1), i, 1,
6902 0, in_code == COMPARE);
6905 /* Same as previous, but for (subreg (lshiftrt ...)) in first op. */
6906 else if (GET_CODE (XEXP (x, 0)) == SUBREG
6907 && subreg_lowpart_p (XEXP (x, 0))
6908 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == LSHIFTRT
6909 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6911 new = make_compound_operation (XEXP (SUBREG_REG (XEXP (x, 0)), 0),
6913 new = make_extraction (GET_MODE (SUBREG_REG (XEXP (x, 0))), new, 0,
6914 XEXP (SUBREG_REG (XEXP (x, 0)), 1), i, 1,
6915 0, in_code == COMPARE);
6917 /* Same as previous, but for (xor/ior (lshiftrt...) (lshiftrt...)). */
6918 else if ((GET_CODE (XEXP (x, 0)) == XOR
6919 || GET_CODE (XEXP (x, 0)) == IOR)
6920 && GET_CODE (XEXP (XEXP (x, 0), 0)) == LSHIFTRT
6921 && GET_CODE (XEXP (XEXP (x, 0), 1)) == LSHIFTRT
6922 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6924 /* Apply the distributive law, and then try to make extractions. */
6925 new = gen_rtx_fmt_ee (GET_CODE (XEXP (x, 0)), mode,
6926 gen_rtx_AND (mode, XEXP (XEXP (x, 0), 0),
6928 gen_rtx_AND (mode, XEXP (XEXP (x, 0), 1),
6930 new = make_compound_operation (new, in_code);
6933 /* If we are have (and (rotate X C) M) and C is larger than the number
6934 of bits in M, this is an extraction. */
6936 else if (GET_CODE (XEXP (x, 0)) == ROTATE
6937 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
6938 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0
6939 && i <= INTVAL (XEXP (XEXP (x, 0), 1)))
6941 new = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code);
6942 new = make_extraction (mode, new,
6943 (GET_MODE_BITSIZE (mode)
6944 - INTVAL (XEXP (XEXP (x, 0), 1))),
6945 NULL_RTX, i, 1, 0, in_code == COMPARE);
6948 /* On machines without logical shifts, if the operand of the AND is
6949 a logical shift and our mask turns off all the propagated sign
6950 bits, we can replace the logical shift with an arithmetic shift. */
6951 else if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
6952 && !have_insn_for (LSHIFTRT, mode)
6953 && have_insn_for (ASHIFTRT, mode)
6954 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
6955 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
6956 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT
6957 && mode_width <= HOST_BITS_PER_WIDE_INT)
6959 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
6961 mask >>= INTVAL (XEXP (XEXP (x, 0), 1));
6962 if ((INTVAL (XEXP (x, 1)) & ~mask) == 0)
6964 gen_rtx_ASHIFTRT (mode,
6965 make_compound_operation
6966 (XEXP (XEXP (x, 0), 0), next_code),
6967 XEXP (XEXP (x, 0), 1)));
6970 /* If the constant is one less than a power of two, this might be
6971 representable by an extraction even if no shift is present.
6972 If it doesn't end up being a ZERO_EXTEND, we will ignore it unless
6973 we are in a COMPARE. */
6974 else if ((i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6975 new = make_extraction (mode,
6976 make_compound_operation (XEXP (x, 0),
6978 0, NULL_RTX, i, 1, 0, in_code == COMPARE);
6980 /* If we are in a comparison and this is an AND with a power of two,
6981 convert this into the appropriate bit extract. */
6982 else if (in_code == COMPARE
6983 && (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0)
6984 new = make_extraction (mode,
6985 make_compound_operation (XEXP (x, 0),
6987 i, NULL_RTX, 1, 1, 0, 1);
6992 /* If the sign bit is known to be zero, replace this with an
6993 arithmetic shift. */
6994 if (have_insn_for (ASHIFTRT, mode)
6995 && ! have_insn_for (LSHIFTRT, mode)
6996 && mode_width <= HOST_BITS_PER_WIDE_INT
6997 && (nonzero_bits (XEXP (x, 0), mode) & (1 << (mode_width - 1))) == 0)
6999 new = gen_rtx_ASHIFTRT (mode,
7000 make_compound_operation (XEXP (x, 0),
7006 /* ... fall through ... */
7012 /* If we have (ashiftrt (ashift foo C1) C2) with C2 >= C1,
7013 this is a SIGN_EXTRACT. */
7014 if (GET_CODE (rhs) == CONST_INT
7015 && GET_CODE (lhs) == ASHIFT
7016 && GET_CODE (XEXP (lhs, 1)) == CONST_INT
7017 && INTVAL (rhs) >= INTVAL (XEXP (lhs, 1)))
7019 new = make_compound_operation (XEXP (lhs, 0), next_code);
7020 new = make_extraction (mode, new,
7021 INTVAL (rhs) - INTVAL (XEXP (lhs, 1)),
7022 NULL_RTX, mode_width - INTVAL (rhs),
7023 code == LSHIFTRT, 0, in_code == COMPARE);
7027 /* See if we have operations between an ASHIFTRT and an ASHIFT.
7028 If so, try to merge the shifts into a SIGN_EXTEND. We could
7029 also do this for some cases of SIGN_EXTRACT, but it doesn't
7030 seem worth the effort; the case checked for occurs on Alpha. */
7033 && ! (GET_CODE (lhs) == SUBREG
7034 && (OBJECT_P (SUBREG_REG (lhs))))
7035 && GET_CODE (rhs) == CONST_INT
7036 && INTVAL (rhs) < HOST_BITS_PER_WIDE_INT
7037 && (new = extract_left_shift (lhs, INTVAL (rhs))) != 0)
7038 new = make_extraction (mode, make_compound_operation (new, next_code),
7039 0, NULL_RTX, mode_width - INTVAL (rhs),
7040 code == LSHIFTRT, 0, in_code == COMPARE);
7045 /* Call ourselves recursively on the inner expression. If we are
7046 narrowing the object and it has a different RTL code from
7047 what it originally did, do this SUBREG as a force_to_mode. */
7049 tem = make_compound_operation (SUBREG_REG (x), in_code);
7053 simplified = simplify_subreg (GET_MODE (x), tem, GET_MODE (tem),
7059 if (GET_CODE (tem) != GET_CODE (SUBREG_REG (x))
7060 && GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (tem))
7061 && subreg_lowpart_p (x))
7063 rtx newer = force_to_mode (tem, mode, ~(HOST_WIDE_INT) 0,
7066 /* If we have something other than a SUBREG, we might have
7067 done an expansion, so rerun ourselves. */
7068 if (GET_CODE (newer) != SUBREG)
7069 newer = make_compound_operation (newer, in_code);
7085 x = gen_lowpart (mode, new);
7086 code = GET_CODE (x);
7089 /* Now recursively process each operand of this operation. */
7090 fmt = GET_RTX_FORMAT (code);
7091 for (i = 0; i < GET_RTX_LENGTH (code); i++)
7094 new = make_compound_operation (XEXP (x, i), next_code);
7095 SUBST (XEXP (x, i), new);
7098 /* If this is a commutative operation, the changes to the operands
7099 may have made it noncanonical. */
7100 if (COMMUTATIVE_ARITH_P (x)
7101 && swap_commutative_operands_p (XEXP (x, 0), XEXP (x, 1)))
7104 SUBST (XEXP (x, 0), XEXP (x, 1));
7105 SUBST (XEXP (x, 1), tem);
7111 /* Given M see if it is a value that would select a field of bits
7112 within an item, but not the entire word. Return -1 if not.
7113 Otherwise, return the starting position of the field, where 0 is the
7116 *PLEN is set to the length of the field. */
7119 get_pos_from_mask (unsigned HOST_WIDE_INT m, unsigned HOST_WIDE_INT *plen)
7121 /* Get the bit number of the first 1 bit from the right, -1 if none. */
7122 int pos = exact_log2 (m & -m);
7126 /* Now shift off the low-order zero bits and see if we have a
7127 power of two minus 1. */
7128 len = exact_log2 ((m >> pos) + 1);
7137 /* If X refers to a register that equals REG in value, replace these
7138 references with REG. */
7140 canon_reg_for_combine (rtx x, rtx reg)
7147 enum rtx_code code = GET_CODE (x);
7148 switch (GET_RTX_CLASS (code))
7151 op0 = canon_reg_for_combine (XEXP (x, 0), reg);
7152 if (op0 != XEXP (x, 0))
7153 return simplify_gen_unary (GET_CODE (x), GET_MODE (x), op0,
7158 case RTX_COMM_ARITH:
7159 op0 = canon_reg_for_combine (XEXP (x, 0), reg);
7160 op1 = canon_reg_for_combine (XEXP (x, 1), reg);
7161 if (op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
7162 return simplify_gen_binary (GET_CODE (x), GET_MODE (x), op0, op1);
7166 case RTX_COMM_COMPARE:
7167 op0 = canon_reg_for_combine (XEXP (x, 0), reg);
7168 op1 = canon_reg_for_combine (XEXP (x, 1), reg);
7169 if (op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
7170 return simplify_gen_relational (GET_CODE (x), GET_MODE (x),
7171 GET_MODE (op0), op0, op1);
7175 case RTX_BITFIELD_OPS:
7176 op0 = canon_reg_for_combine (XEXP (x, 0), reg);
7177 op1 = canon_reg_for_combine (XEXP (x, 1), reg);
7178 op2 = canon_reg_for_combine (XEXP (x, 2), reg);
7179 if (op0 != XEXP (x, 0) || op1 != XEXP (x, 1) || op2 != XEXP (x, 2))
7180 return simplify_gen_ternary (GET_CODE (x), GET_MODE (x),
7181 GET_MODE (op0), op0, op1, op2);
7186 if (rtx_equal_p (get_last_value (reg), x)
7187 || rtx_equal_p (reg, get_last_value (x)))
7196 fmt = GET_RTX_FORMAT (code);
7198 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
7201 rtx op = canon_reg_for_combine (XEXP (x, i), reg);
7202 if (op != XEXP (x, i))
7212 else if (fmt[i] == 'E')
7215 for (j = 0; j < XVECLEN (x, i); j++)
7217 rtx op = canon_reg_for_combine (XVECEXP (x, i, j), reg);
7218 if (op != XVECEXP (x, i, j))
7225 XVECEXP (x, i, j) = op;
7236 /* Return X converted to MODE. If the value is already truncated to
7237 MODE we can just return a subreg even though in the general case we
7238 would need an explicit truncation. */
7241 gen_lowpart_or_truncate (enum machine_mode mode, rtx x)
7243 if (GET_MODE_SIZE (GET_MODE (x)) <= GET_MODE_SIZE (mode)
7244 || TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode),
7245 GET_MODE_BITSIZE (GET_MODE (x)))
7246 || (REG_P (x) && reg_truncated_to_mode (mode, x)))
7247 return gen_lowpart (mode, x);
7249 return simplify_gen_unary (TRUNCATE, mode, x, GET_MODE (x));
7252 /* See if X can be simplified knowing that we will only refer to it in
7253 MODE and will only refer to those bits that are nonzero in MASK.
7254 If other bits are being computed or if masking operations are done
7255 that select a superset of the bits in MASK, they can sometimes be
7258 Return a possibly simplified expression, but always convert X to
7259 MODE. If X is a CONST_INT, AND the CONST_INT with MASK.
7261 If JUST_SELECT is nonzero, don't optimize by noticing that bits in MASK
7262 are all off in X. This is used when X will be complemented, by either
7263 NOT, NEG, or XOR. */
7266 force_to_mode (rtx x, enum machine_mode mode, unsigned HOST_WIDE_INT mask,
7269 enum rtx_code code = GET_CODE (x);
7270 int next_select = just_select || code == XOR || code == NOT || code == NEG;
7271 enum machine_mode op_mode;
7272 unsigned HOST_WIDE_INT fuller_mask, nonzero;
7275 /* If this is a CALL or ASM_OPERANDS, don't do anything. Some of the
7276 code below will do the wrong thing since the mode of such an
7277 expression is VOIDmode.
7279 Also do nothing if X is a CLOBBER; this can happen if X was
7280 the return value from a call to gen_lowpart. */
7281 if (code == CALL || code == ASM_OPERANDS || code == CLOBBER)
7284 /* We want to perform the operation is its present mode unless we know
7285 that the operation is valid in MODE, in which case we do the operation
7287 op_mode = ((GET_MODE_CLASS (mode) == GET_MODE_CLASS (GET_MODE (x))
7288 && have_insn_for (code, mode))
7289 ? mode : GET_MODE (x));
7291 /* It is not valid to do a right-shift in a narrower mode
7292 than the one it came in with. */
7293 if ((code == LSHIFTRT || code == ASHIFTRT)
7294 && GET_MODE_BITSIZE (mode) < GET_MODE_BITSIZE (GET_MODE (x)))
7295 op_mode = GET_MODE (x);
7297 /* Truncate MASK to fit OP_MODE. */
7299 mask &= GET_MODE_MASK (op_mode);
7301 /* When we have an arithmetic operation, or a shift whose count we
7302 do not know, we need to assume that all bits up to the highest-order
7303 bit in MASK will be needed. This is how we form such a mask. */
7304 if (mask & ((unsigned HOST_WIDE_INT) 1 << (HOST_BITS_PER_WIDE_INT - 1)))
7305 fuller_mask = ~(unsigned HOST_WIDE_INT) 0;
7307 fuller_mask = (((unsigned HOST_WIDE_INT) 1 << (floor_log2 (mask) + 1))
7310 /* Determine what bits of X are guaranteed to be (non)zero. */
7311 nonzero = nonzero_bits (x, mode);
7313 /* If none of the bits in X are needed, return a zero. */
7314 if (!just_select && (nonzero & mask) == 0 && !side_effects_p (x))
7317 /* If X is a CONST_INT, return a new one. Do this here since the
7318 test below will fail. */
7319 if (GET_CODE (x) == CONST_INT)
7321 if (SCALAR_INT_MODE_P (mode))
7322 return gen_int_mode (INTVAL (x) & mask, mode);
7325 x = GEN_INT (INTVAL (x) & mask);
7326 return gen_lowpart_common (mode, x);
7330 /* If X is narrower than MODE and we want all the bits in X's mode, just
7331 get X in the proper mode. */
7332 if (GET_MODE_SIZE (GET_MODE (x)) < GET_MODE_SIZE (mode)
7333 && (GET_MODE_MASK (GET_MODE (x)) & ~mask) == 0)
7334 return gen_lowpart (mode, x);
7339 /* If X is a (clobber (const_int)), return it since we know we are
7340 generating something that won't match. */
7347 x = expand_compound_operation (x);
7348 if (GET_CODE (x) != code)
7349 return force_to_mode (x, mode, mask, next_select);
7353 if (subreg_lowpart_p (x)
7354 /* We can ignore the effect of this SUBREG if it narrows the mode or
7355 if the constant masks to zero all the bits the mode doesn't
7357 && ((GET_MODE_SIZE (GET_MODE (x))
7358 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
7360 & GET_MODE_MASK (GET_MODE (x))
7361 & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (x)))))))
7362 return force_to_mode (SUBREG_REG (x), mode, mask, next_select);
7366 /* If this is an AND with a constant, convert it into an AND
7367 whose constant is the AND of that constant with MASK. If it
7368 remains an AND of MASK, delete it since it is redundant. */
7370 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
7372 x = simplify_and_const_int (x, op_mode, XEXP (x, 0),
7373 mask & INTVAL (XEXP (x, 1)));
7375 /* If X is still an AND, see if it is an AND with a mask that
7376 is just some low-order bits. If so, and it is MASK, we don't
7379 if (GET_CODE (x) == AND && GET_CODE (XEXP (x, 1)) == CONST_INT
7380 && ((INTVAL (XEXP (x, 1)) & GET_MODE_MASK (GET_MODE (x)))
7384 /* If it remains an AND, try making another AND with the bits
7385 in the mode mask that aren't in MASK turned on. If the
7386 constant in the AND is wide enough, this might make a
7387 cheaper constant. */
7389 if (GET_CODE (x) == AND && GET_CODE (XEXP (x, 1)) == CONST_INT
7390 && GET_MODE_MASK (GET_MODE (x)) != mask
7391 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT)
7393 HOST_WIDE_INT cval = (INTVAL (XEXP (x, 1))
7394 | (GET_MODE_MASK (GET_MODE (x)) & ~mask));
7395 int width = GET_MODE_BITSIZE (GET_MODE (x));
7398 /* If MODE is narrower than HOST_WIDE_INT and CVAL is a negative
7399 number, sign extend it. */
7400 if (width > 0 && width < HOST_BITS_PER_WIDE_INT
7401 && (cval & ((HOST_WIDE_INT) 1 << (width - 1))) != 0)
7402 cval |= (HOST_WIDE_INT) -1 << width;
7404 y = simplify_gen_binary (AND, GET_MODE (x),
7405 XEXP (x, 0), GEN_INT (cval));
7406 if (rtx_cost (y, SET) < rtx_cost (x, SET))
7416 /* In (and (plus FOO C1) M), if M is a mask that just turns off
7417 low-order bits (as in an alignment operation) and FOO is already
7418 aligned to that boundary, mask C1 to that boundary as well.
7419 This may eliminate that PLUS and, later, the AND. */
7422 unsigned int width = GET_MODE_BITSIZE (mode);
7423 unsigned HOST_WIDE_INT smask = mask;
7425 /* If MODE is narrower than HOST_WIDE_INT and mask is a negative
7426 number, sign extend it. */
7428 if (width < HOST_BITS_PER_WIDE_INT
7429 && (smask & ((HOST_WIDE_INT) 1 << (width - 1))) != 0)
7430 smask |= (HOST_WIDE_INT) -1 << width;
7432 if (GET_CODE (XEXP (x, 1)) == CONST_INT
7433 && exact_log2 (- smask) >= 0
7434 && (nonzero_bits (XEXP (x, 0), mode) & ~smask) == 0
7435 && (INTVAL (XEXP (x, 1)) & ~smask) != 0)
7436 return force_to_mode (plus_constant (XEXP (x, 0),
7437 (INTVAL (XEXP (x, 1)) & smask)),
7438 mode, smask, next_select);
7441 /* ... fall through ... */
7444 /* For PLUS, MINUS and MULT, we need any bits less significant than the
7445 most significant bit in MASK since carries from those bits will
7446 affect the bits we are interested in. */
7451 /* If X is (minus C Y) where C's least set bit is larger than any bit
7452 in the mask, then we may replace with (neg Y). */
7453 if (GET_CODE (XEXP (x, 0)) == CONST_INT
7454 && (((unsigned HOST_WIDE_INT) (INTVAL (XEXP (x, 0))
7455 & -INTVAL (XEXP (x, 0))))
7458 x = simplify_gen_unary (NEG, GET_MODE (x), XEXP (x, 1),
7460 return force_to_mode (x, mode, mask, next_select);
7463 /* Similarly, if C contains every bit in the fuller_mask, then we may
7464 replace with (not Y). */
7465 if (GET_CODE (XEXP (x, 0)) == CONST_INT
7466 && ((INTVAL (XEXP (x, 0)) | (HOST_WIDE_INT) fuller_mask)
7467 == INTVAL (XEXP (x, 0))))
7469 x = simplify_gen_unary (NOT, GET_MODE (x),
7470 XEXP (x, 1), GET_MODE (x));
7471 return force_to_mode (x, mode, mask, next_select);
7479 /* If X is (ior (lshiftrt FOO C1) C2), try to commute the IOR and
7480 LSHIFTRT so we end up with an (and (lshiftrt (ior ...) ...) ...)
7481 operation which may be a bitfield extraction. Ensure that the
7482 constant we form is not wider than the mode of X. */
7484 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
7485 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
7486 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
7487 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT
7488 && GET_CODE (XEXP (x, 1)) == CONST_INT
7489 && ((INTVAL (XEXP (XEXP (x, 0), 1))
7490 + floor_log2 (INTVAL (XEXP (x, 1))))
7491 < GET_MODE_BITSIZE (GET_MODE (x)))
7492 && (INTVAL (XEXP (x, 1))
7493 & ~nonzero_bits (XEXP (x, 0), GET_MODE (x))) == 0)
7495 temp = GEN_INT ((INTVAL (XEXP (x, 1)) & mask)
7496 << INTVAL (XEXP (XEXP (x, 0), 1)));
7497 temp = simplify_gen_binary (GET_CODE (x), GET_MODE (x),
7498 XEXP (XEXP (x, 0), 0), temp);
7499 x = simplify_gen_binary (LSHIFTRT, GET_MODE (x), temp,
7500 XEXP (XEXP (x, 0), 1));
7501 return force_to_mode (x, mode, mask, next_select);
7505 /* For most binary operations, just propagate into the operation and
7506 change the mode if we have an operation of that mode. */
7508 op0 = gen_lowpart_or_truncate (op_mode,
7509 force_to_mode (XEXP (x, 0), mode, mask,
7511 op1 = gen_lowpart_or_truncate (op_mode,
7512 force_to_mode (XEXP (x, 1), mode, mask,
7515 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
7516 x = simplify_gen_binary (code, op_mode, op0, op1);
7520 /* For left shifts, do the same, but just for the first operand.
7521 However, we cannot do anything with shifts where we cannot
7522 guarantee that the counts are smaller than the size of the mode
7523 because such a count will have a different meaning in a
7526 if (! (GET_CODE (XEXP (x, 1)) == CONST_INT
7527 && INTVAL (XEXP (x, 1)) >= 0
7528 && INTVAL (XEXP (x, 1)) < GET_MODE_BITSIZE (mode))
7529 && ! (GET_MODE (XEXP (x, 1)) != VOIDmode
7530 && (nonzero_bits (XEXP (x, 1), GET_MODE (XEXP (x, 1)))
7531 < (unsigned HOST_WIDE_INT) GET_MODE_BITSIZE (mode))))
7534 /* If the shift count is a constant and we can do arithmetic in
7535 the mode of the shift, refine which bits we need. Otherwise, use the
7536 conservative form of the mask. */
7537 if (GET_CODE (XEXP (x, 1)) == CONST_INT
7538 && INTVAL (XEXP (x, 1)) >= 0
7539 && INTVAL (XEXP (x, 1)) < GET_MODE_BITSIZE (op_mode)
7540 && GET_MODE_BITSIZE (op_mode) <= HOST_BITS_PER_WIDE_INT)
7541 mask >>= INTVAL (XEXP (x, 1));
7545 op0 = gen_lowpart_or_truncate (op_mode,
7546 force_to_mode (XEXP (x, 0), op_mode,
7547 mask, next_select));
7549 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0))
7550 x = simplify_gen_binary (code, op_mode, op0, XEXP (x, 1));
7554 /* Here we can only do something if the shift count is a constant,
7555 this shift constant is valid for the host, and we can do arithmetic
7558 if (GET_CODE (XEXP (x, 1)) == CONST_INT
7559 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT
7560 && GET_MODE_BITSIZE (op_mode) <= HOST_BITS_PER_WIDE_INT)
7562 rtx inner = XEXP (x, 0);
7563 unsigned HOST_WIDE_INT inner_mask;
7565 /* Select the mask of the bits we need for the shift operand. */
7566 inner_mask = mask << INTVAL (XEXP (x, 1));
7568 /* We can only change the mode of the shift if we can do arithmetic
7569 in the mode of the shift and INNER_MASK is no wider than the
7570 width of X's mode. */
7571 if ((inner_mask & ~GET_MODE_MASK (GET_MODE (x))) != 0)
7572 op_mode = GET_MODE (x);
7574 inner = force_to_mode (inner, op_mode, inner_mask, next_select);
7576 if (GET_MODE (x) != op_mode || inner != XEXP (x, 0))
7577 x = simplify_gen_binary (LSHIFTRT, op_mode, inner, XEXP (x, 1));
7580 /* If we have (and (lshiftrt FOO C1) C2) where the combination of the
7581 shift and AND produces only copies of the sign bit (C2 is one less
7582 than a power of two), we can do this with just a shift. */
7584 if (GET_CODE (x) == LSHIFTRT
7585 && GET_CODE (XEXP (x, 1)) == CONST_INT
7586 /* The shift puts one of the sign bit copies in the least significant
7588 && ((INTVAL (XEXP (x, 1))
7589 + num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0))))
7590 >= GET_MODE_BITSIZE (GET_MODE (x)))
7591 && exact_log2 (mask + 1) >= 0
7592 /* Number of bits left after the shift must be more than the mask
7594 && ((INTVAL (XEXP (x, 1)) + exact_log2 (mask + 1))
7595 <= GET_MODE_BITSIZE (GET_MODE (x)))
7596 /* Must be more sign bit copies than the mask needs. */
7597 && ((int) num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
7598 >= exact_log2 (mask + 1)))
7599 x = simplify_gen_binary (LSHIFTRT, GET_MODE (x), XEXP (x, 0),
7600 GEN_INT (GET_MODE_BITSIZE (GET_MODE (x))
7601 - exact_log2 (mask + 1)));
7606 /* If we are just looking for the sign bit, we don't need this shift at
7607 all, even if it has a variable count. */
7608 if (GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
7609 && (mask == ((unsigned HOST_WIDE_INT) 1
7610 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
7611 return force_to_mode (XEXP (x, 0), mode, mask, next_select);
7613 /* If this is a shift by a constant, get a mask that contains those bits
7614 that are not copies of the sign bit. We then have two cases: If
7615 MASK only includes those bits, this can be a logical shift, which may
7616 allow simplifications. If MASK is a single-bit field not within
7617 those bits, we are requesting a copy of the sign bit and hence can
7618 shift the sign bit to the appropriate location. */
7620 if (GET_CODE (XEXP (x, 1)) == CONST_INT && INTVAL (XEXP (x, 1)) >= 0
7621 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT)
7625 /* If the considered data is wider than HOST_WIDE_INT, we can't
7626 represent a mask for all its bits in a single scalar.
7627 But we only care about the lower bits, so calculate these. */
7629 if (GET_MODE_BITSIZE (GET_MODE (x)) > HOST_BITS_PER_WIDE_INT)
7631 nonzero = ~(HOST_WIDE_INT) 0;
7633 /* GET_MODE_BITSIZE (GET_MODE (x)) - INTVAL (XEXP (x, 1))
7634 is the number of bits a full-width mask would have set.
7635 We need only shift if these are fewer than nonzero can
7636 hold. If not, we must keep all bits set in nonzero. */
7638 if (GET_MODE_BITSIZE (GET_MODE (x)) - INTVAL (XEXP (x, 1))
7639 < HOST_BITS_PER_WIDE_INT)
7640 nonzero >>= INTVAL (XEXP (x, 1))
7641 + HOST_BITS_PER_WIDE_INT
7642 - GET_MODE_BITSIZE (GET_MODE (x)) ;
7646 nonzero = GET_MODE_MASK (GET_MODE (x));
7647 nonzero >>= INTVAL (XEXP (x, 1));
7650 if ((mask & ~nonzero) == 0)
7652 x = simplify_shift_const (NULL_RTX, LSHIFTRT, GET_MODE (x),
7653 XEXP (x, 0), INTVAL (XEXP (x, 1)));
7654 if (GET_CODE (x) != ASHIFTRT)
7655 return force_to_mode (x, mode, mask, next_select);
7658 else if ((i = exact_log2 (mask)) >= 0)
7660 x = simplify_shift_const
7661 (NULL_RTX, LSHIFTRT, GET_MODE (x), XEXP (x, 0),
7662 GET_MODE_BITSIZE (GET_MODE (x)) - 1 - i);
7664 if (GET_CODE (x) != ASHIFTRT)
7665 return force_to_mode (x, mode, mask, next_select);
7669 /* If MASK is 1, convert this to an LSHIFTRT. This can be done
7670 even if the shift count isn't a constant. */
7672 x = simplify_gen_binary (LSHIFTRT, GET_MODE (x),
7673 XEXP (x, 0), XEXP (x, 1));
7677 /* If this is a zero- or sign-extension operation that just affects bits
7678 we don't care about, remove it. Be sure the call above returned
7679 something that is still a shift. */
7681 if ((GET_CODE (x) == LSHIFTRT || GET_CODE (x) == ASHIFTRT)
7682 && GET_CODE (XEXP (x, 1)) == CONST_INT
7683 && INTVAL (XEXP (x, 1)) >= 0
7684 && (INTVAL (XEXP (x, 1))
7685 <= GET_MODE_BITSIZE (GET_MODE (x)) - (floor_log2 (mask) + 1))
7686 && GET_CODE (XEXP (x, 0)) == ASHIFT
7687 && XEXP (XEXP (x, 0), 1) == XEXP (x, 1))
7688 return force_to_mode (XEXP (XEXP (x, 0), 0), mode, mask,
7695 /* If the shift count is constant and we can do computations
7696 in the mode of X, compute where the bits we care about are.
7697 Otherwise, we can't do anything. Don't change the mode of
7698 the shift or propagate MODE into the shift, though. */
7699 if (GET_CODE (XEXP (x, 1)) == CONST_INT
7700 && INTVAL (XEXP (x, 1)) >= 0)
7702 temp = simplify_binary_operation (code == ROTATE ? ROTATERT : ROTATE,
7703 GET_MODE (x), GEN_INT (mask),
7705 if (temp && GET_CODE (temp) == CONST_INT)
7707 force_to_mode (XEXP (x, 0), GET_MODE (x),
7708 INTVAL (temp), next_select));
7713 /* If we just want the low-order bit, the NEG isn't needed since it
7714 won't change the low-order bit. */
7716 return force_to_mode (XEXP (x, 0), mode, mask, just_select);
7718 /* We need any bits less significant than the most significant bit in
7719 MASK since carries from those bits will affect the bits we are
7725 /* (not FOO) is (xor FOO CONST), so if FOO is an LSHIFTRT, we can do the
7726 same as the XOR case above. Ensure that the constant we form is not
7727 wider than the mode of X. */
7729 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
7730 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
7731 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
7732 && (INTVAL (XEXP (XEXP (x, 0), 1)) + floor_log2 (mask)
7733 < GET_MODE_BITSIZE (GET_MODE (x)))
7734 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT)
7736 temp = gen_int_mode (mask << INTVAL (XEXP (XEXP (x, 0), 1)),
7738 temp = simplify_gen_binary (XOR, GET_MODE (x),
7739 XEXP (XEXP (x, 0), 0), temp);
7740 x = simplify_gen_binary (LSHIFTRT, GET_MODE (x),
7741 temp, XEXP (XEXP (x, 0), 1));
7743 return force_to_mode (x, mode, mask, next_select);
7746 /* (and (not FOO) CONST) is (not (or FOO (not CONST))), so we must
7747 use the full mask inside the NOT. */
7751 op0 = gen_lowpart_or_truncate (op_mode,
7752 force_to_mode (XEXP (x, 0), mode, mask,
7754 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0))
7755 x = simplify_gen_unary (code, op_mode, op0, op_mode);
7759 /* (and (ne FOO 0) CONST) can be (and FOO CONST) if CONST is included
7760 in STORE_FLAG_VALUE and FOO has a single bit that might be nonzero,
7761 which is equal to STORE_FLAG_VALUE. */
7762 if ((mask & ~STORE_FLAG_VALUE) == 0 && XEXP (x, 1) == const0_rtx
7763 && GET_MODE (XEXP (x, 0)) == mode
7764 && exact_log2 (nonzero_bits (XEXP (x, 0), mode)) >= 0
7765 && (nonzero_bits (XEXP (x, 0), mode)
7766 == (unsigned HOST_WIDE_INT) STORE_FLAG_VALUE))
7767 return force_to_mode (XEXP (x, 0), mode, mask, next_select);
7772 /* We have no way of knowing if the IF_THEN_ELSE can itself be
7773 written in a narrower mode. We play it safe and do not do so. */
7776 gen_lowpart_or_truncate (GET_MODE (x),
7777 force_to_mode (XEXP (x, 1), mode,
7778 mask, next_select)));
7780 gen_lowpart_or_truncate (GET_MODE (x),
7781 force_to_mode (XEXP (x, 2), mode,
7782 mask, next_select)));
7789 /* Ensure we return a value of the proper mode. */
7790 return gen_lowpart_or_truncate (mode, x);
7793 /* Return nonzero if X is an expression that has one of two values depending on
7794 whether some other value is zero or nonzero. In that case, we return the
7795 value that is being tested, *PTRUE is set to the value if the rtx being
7796 returned has a nonzero value, and *PFALSE is set to the other alternative.
7798 If we return zero, we set *PTRUE and *PFALSE to X. */
7801 if_then_else_cond (rtx x, rtx *ptrue, rtx *pfalse)
7803 enum machine_mode mode = GET_MODE (x);
7804 enum rtx_code code = GET_CODE (x);
7805 rtx cond0, cond1, true0, true1, false0, false1;
7806 unsigned HOST_WIDE_INT nz;
7808 /* If we are comparing a value against zero, we are done. */
7809 if ((code == NE || code == EQ)
7810 && XEXP (x, 1) == const0_rtx)
7812 *ptrue = (code == NE) ? const_true_rtx : const0_rtx;
7813 *pfalse = (code == NE) ? const0_rtx : const_true_rtx;
7817 /* If this is a unary operation whose operand has one of two values, apply
7818 our opcode to compute those values. */
7819 else if (UNARY_P (x)
7820 && (cond0 = if_then_else_cond (XEXP (x, 0), &true0, &false0)) != 0)
7822 *ptrue = simplify_gen_unary (code, mode, true0, GET_MODE (XEXP (x, 0)));
7823 *pfalse = simplify_gen_unary (code, mode, false0,
7824 GET_MODE (XEXP (x, 0)));
7828 /* If this is a COMPARE, do nothing, since the IF_THEN_ELSE we would
7829 make can't possibly match and would suppress other optimizations. */
7830 else if (code == COMPARE)
7833 /* If this is a binary operation, see if either side has only one of two
7834 values. If either one does or if both do and they are conditional on
7835 the same value, compute the new true and false values. */
7836 else if (BINARY_P (x))
7838 cond0 = if_then_else_cond (XEXP (x, 0), &true0, &false0);
7839 cond1 = if_then_else_cond (XEXP (x, 1), &true1, &false1);
7841 if ((cond0 != 0 || cond1 != 0)
7842 && ! (cond0 != 0 && cond1 != 0 && ! rtx_equal_p (cond0, cond1)))
7844 /* If if_then_else_cond returned zero, then true/false are the
7845 same rtl. We must copy one of them to prevent invalid rtl
7848 true0 = copy_rtx (true0);
7849 else if (cond1 == 0)
7850 true1 = copy_rtx (true1);
7852 if (COMPARISON_P (x))
7854 *ptrue = simplify_gen_relational (code, mode, VOIDmode,
7856 *pfalse = simplify_gen_relational (code, mode, VOIDmode,
7861 *ptrue = simplify_gen_binary (code, mode, true0, true1);
7862 *pfalse = simplify_gen_binary (code, mode, false0, false1);
7865 return cond0 ? cond0 : cond1;
7868 /* See if we have PLUS, IOR, XOR, MINUS or UMAX, where one of the
7869 operands is zero when the other is nonzero, and vice-versa,
7870 and STORE_FLAG_VALUE is 1 or -1. */
7872 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
7873 && (code == PLUS || code == IOR || code == XOR || code == MINUS
7875 && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT)
7877 rtx op0 = XEXP (XEXP (x, 0), 1);
7878 rtx op1 = XEXP (XEXP (x, 1), 1);
7880 cond0 = XEXP (XEXP (x, 0), 0);
7881 cond1 = XEXP (XEXP (x, 1), 0);
7883 if (COMPARISON_P (cond0)
7884 && COMPARISON_P (cond1)
7885 && ((GET_CODE (cond0) == reversed_comparison_code (cond1, NULL)
7886 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0))
7887 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1)))
7888 || ((swap_condition (GET_CODE (cond0))
7889 == reversed_comparison_code (cond1, NULL))
7890 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1))
7891 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0))))
7892 && ! side_effects_p (x))
7894 *ptrue = simplify_gen_binary (MULT, mode, op0, const_true_rtx);
7895 *pfalse = simplify_gen_binary (MULT, mode,
7897 ? simplify_gen_unary (NEG, mode,
7905 /* Similarly for MULT, AND and UMIN, except that for these the result
7907 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
7908 && (code == MULT || code == AND || code == UMIN)
7909 && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT)
7911 cond0 = XEXP (XEXP (x, 0), 0);
7912 cond1 = XEXP (XEXP (x, 1), 0);
7914 if (COMPARISON_P (cond0)
7915 && COMPARISON_P (cond1)
7916 && ((GET_CODE (cond0) == reversed_comparison_code (cond1, NULL)
7917 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0))
7918 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1)))
7919 || ((swap_condition (GET_CODE (cond0))
7920 == reversed_comparison_code (cond1, NULL))
7921 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1))
7922 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0))))
7923 && ! side_effects_p (x))
7925 *ptrue = *pfalse = const0_rtx;
7931 else if (code == IF_THEN_ELSE)
7933 /* If we have IF_THEN_ELSE already, extract the condition and
7934 canonicalize it if it is NE or EQ. */
7935 cond0 = XEXP (x, 0);
7936 *ptrue = XEXP (x, 1), *pfalse = XEXP (x, 2);
7937 if (GET_CODE (cond0) == NE && XEXP (cond0, 1) == const0_rtx)
7938 return XEXP (cond0, 0);
7939 else if (GET_CODE (cond0) == EQ && XEXP (cond0, 1) == const0_rtx)
7941 *ptrue = XEXP (x, 2), *pfalse = XEXP (x, 1);
7942 return XEXP (cond0, 0);
7948 /* If X is a SUBREG, we can narrow both the true and false values
7949 if the inner expression, if there is a condition. */
7950 else if (code == SUBREG
7951 && 0 != (cond0 = if_then_else_cond (SUBREG_REG (x),
7954 true0 = simplify_gen_subreg (mode, true0,
7955 GET_MODE (SUBREG_REG (x)), SUBREG_BYTE (x));
7956 false0 = simplify_gen_subreg (mode, false0,
7957 GET_MODE (SUBREG_REG (x)), SUBREG_BYTE (x));
7958 if (true0 && false0)
7966 /* If X is a constant, this isn't special and will cause confusions
7967 if we treat it as such. Likewise if it is equivalent to a constant. */
7968 else if (CONSTANT_P (x)
7969 || ((cond0 = get_last_value (x)) != 0 && CONSTANT_P (cond0)))
7972 /* If we're in BImode, canonicalize on 0 and STORE_FLAG_VALUE, as that
7973 will be least confusing to the rest of the compiler. */
7974 else if (mode == BImode)
7976 *ptrue = GEN_INT (STORE_FLAG_VALUE), *pfalse = const0_rtx;
7980 /* If X is known to be either 0 or -1, those are the true and
7981 false values when testing X. */
7982 else if (x == constm1_rtx || x == const0_rtx
7983 || (mode != VOIDmode
7984 && num_sign_bit_copies (x, mode) == GET_MODE_BITSIZE (mode)))
7986 *ptrue = constm1_rtx, *pfalse = const0_rtx;
7990 /* Likewise for 0 or a single bit. */
7991 else if (SCALAR_INT_MODE_P (mode)
7992 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
7993 && exact_log2 (nz = nonzero_bits (x, mode)) >= 0)
7995 *ptrue = gen_int_mode (nz, mode), *pfalse = const0_rtx;
7999 /* Otherwise fail; show no condition with true and false values the same. */
8000 *ptrue = *pfalse = x;
8004 /* Return the value of expression X given the fact that condition COND
8005 is known to be true when applied to REG as its first operand and VAL
8006 as its second. X is known to not be shared and so can be modified in
8009 We only handle the simplest cases, and specifically those cases that
8010 arise with IF_THEN_ELSE expressions. */
8013 known_cond (rtx x, enum rtx_code cond, rtx reg, rtx val)
8015 enum rtx_code code = GET_CODE (x);
8020 if (side_effects_p (x))
8023 /* If either operand of the condition is a floating point value,
8024 then we have to avoid collapsing an EQ comparison. */
8026 && rtx_equal_p (x, reg)
8027 && ! FLOAT_MODE_P (GET_MODE (x))
8028 && ! FLOAT_MODE_P (GET_MODE (val)))
8031 if (cond == UNEQ && rtx_equal_p (x, reg))
8034 /* If X is (abs REG) and we know something about REG's relationship
8035 with zero, we may be able to simplify this. */
8037 if (code == ABS && rtx_equal_p (XEXP (x, 0), reg) && val == const0_rtx)
8040 case GE: case GT: case EQ:
8043 return simplify_gen_unary (NEG, GET_MODE (XEXP (x, 0)),
8045 GET_MODE (XEXP (x, 0)));
8050 /* The only other cases we handle are MIN, MAX, and comparisons if the
8051 operands are the same as REG and VAL. */
8053 else if (COMPARISON_P (x) || COMMUTATIVE_ARITH_P (x))
8055 if (rtx_equal_p (XEXP (x, 0), val))
8056 cond = swap_condition (cond), temp = val, val = reg, reg = temp;
8058 if (rtx_equal_p (XEXP (x, 0), reg) && rtx_equal_p (XEXP (x, 1), val))
8060 if (COMPARISON_P (x))
8062 if (comparison_dominates_p (cond, code))
8063 return const_true_rtx;
8065 code = reversed_comparison_code (x, NULL);
8067 && comparison_dominates_p (cond, code))
8072 else if (code == SMAX || code == SMIN
8073 || code == UMIN || code == UMAX)
8075 int unsignedp = (code == UMIN || code == UMAX);
8077 /* Do not reverse the condition when it is NE or EQ.
8078 This is because we cannot conclude anything about
8079 the value of 'SMAX (x, y)' when x is not equal to y,
8080 but we can when x equals y. */
8081 if ((code == SMAX || code == UMAX)
8082 && ! (cond == EQ || cond == NE))
8083 cond = reverse_condition (cond);
8088 return unsignedp ? x : XEXP (x, 1);
8090 return unsignedp ? x : XEXP (x, 0);
8092 return unsignedp ? XEXP (x, 1) : x;
8094 return unsignedp ? XEXP (x, 0) : x;
8101 else if (code == SUBREG)
8103 enum machine_mode inner_mode = GET_MODE (SUBREG_REG (x));
8104 rtx new, r = known_cond (SUBREG_REG (x), cond, reg, val);
8106 if (SUBREG_REG (x) != r)
8108 /* We must simplify subreg here, before we lose track of the
8109 original inner_mode. */
8110 new = simplify_subreg (GET_MODE (x), r,
8111 inner_mode, SUBREG_BYTE (x));
8115 SUBST (SUBREG_REG (x), r);
8120 /* We don't have to handle SIGN_EXTEND here, because even in the
8121 case of replacing something with a modeless CONST_INT, a
8122 CONST_INT is already (supposed to be) a valid sign extension for
8123 its narrower mode, which implies it's already properly
8124 sign-extended for the wider mode. Now, for ZERO_EXTEND, the
8125 story is different. */
8126 else if (code == ZERO_EXTEND)
8128 enum machine_mode inner_mode = GET_MODE (XEXP (x, 0));
8129 rtx new, r = known_cond (XEXP (x, 0), cond, reg, val);
8131 if (XEXP (x, 0) != r)
8133 /* We must simplify the zero_extend here, before we lose
8134 track of the original inner_mode. */
8135 new = simplify_unary_operation (ZERO_EXTEND, GET_MODE (x),
8140 SUBST (XEXP (x, 0), r);
8146 fmt = GET_RTX_FORMAT (code);
8147 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
8150 SUBST (XEXP (x, i), known_cond (XEXP (x, i), cond, reg, val));
8151 else if (fmt[i] == 'E')
8152 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
8153 SUBST (XVECEXP (x, i, j), known_cond (XVECEXP (x, i, j),
8160 /* See if X and Y are equal for the purposes of seeing if we can rewrite an
8161 assignment as a field assignment. */
8164 rtx_equal_for_field_assignment_p (rtx x, rtx y)
8166 if (x == y || rtx_equal_p (x, y))
8169 if (x == 0 || y == 0 || GET_MODE (x) != GET_MODE (y))
8172 /* Check for a paradoxical SUBREG of a MEM compared with the MEM.
8173 Note that all SUBREGs of MEM are paradoxical; otherwise they
8174 would have been rewritten. */
8175 if (MEM_P (x) && GET_CODE (y) == SUBREG
8176 && MEM_P (SUBREG_REG (y))
8177 && rtx_equal_p (SUBREG_REG (y),
8178 gen_lowpart (GET_MODE (SUBREG_REG (y)), x)))
8181 if (MEM_P (y) && GET_CODE (x) == SUBREG
8182 && MEM_P (SUBREG_REG (x))
8183 && rtx_equal_p (SUBREG_REG (x),
8184 gen_lowpart (GET_MODE (SUBREG_REG (x)), y)))
8187 /* We used to see if get_last_value of X and Y were the same but that's
8188 not correct. In one direction, we'll cause the assignment to have
8189 the wrong destination and in the case, we'll import a register into this
8190 insn that might have already have been dead. So fail if none of the
8191 above cases are true. */
8195 /* See if X, a SET operation, can be rewritten as a bit-field assignment.
8196 Return that assignment if so.
8198 We only handle the most common cases. */
8201 make_field_assignment (rtx x)
8203 rtx dest = SET_DEST (x);
8204 rtx src = SET_SRC (x);
8209 unsigned HOST_WIDE_INT len;
8211 enum machine_mode mode;
8213 /* If SRC was (and (not (ashift (const_int 1) POS)) DEST), this is
8214 a clear of a one-bit field. We will have changed it to
8215 (and (rotate (const_int -2) POS) DEST), so check for that. Also check
8218 if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == ROTATE
8219 && GET_CODE (XEXP (XEXP (src, 0), 0)) == CONST_INT
8220 && INTVAL (XEXP (XEXP (src, 0), 0)) == -2
8221 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
8223 assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1),
8226 return gen_rtx_SET (VOIDmode, assign, const0_rtx);
8230 if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == SUBREG
8231 && subreg_lowpart_p (XEXP (src, 0))
8232 && (GET_MODE_SIZE (GET_MODE (XEXP (src, 0)))
8233 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (src, 0)))))
8234 && GET_CODE (SUBREG_REG (XEXP (src, 0))) == ROTATE
8235 && GET_CODE (XEXP (SUBREG_REG (XEXP (src, 0)), 0)) == CONST_INT
8236 && INTVAL (XEXP (SUBREG_REG (XEXP (src, 0)), 0)) == -2
8237 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
8239 assign = make_extraction (VOIDmode, dest, 0,
8240 XEXP (SUBREG_REG (XEXP (src, 0)), 1),
8243 return gen_rtx_SET (VOIDmode, assign, const0_rtx);
8247 /* If SRC is (ior (ashift (const_int 1) POS) DEST), this is a set of a
8249 if (GET_CODE (src) == IOR && GET_CODE (XEXP (src, 0)) == ASHIFT
8250 && XEXP (XEXP (src, 0), 0) == const1_rtx
8251 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
8253 assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1),
8256 return gen_rtx_SET (VOIDmode, assign, const1_rtx);
8260 /* If DEST is already a field assignment, i.e. ZERO_EXTRACT, and the
8261 SRC is an AND with all bits of that field set, then we can discard
8263 if (GET_CODE (dest) == ZERO_EXTRACT
8264 && GET_CODE (XEXP (dest, 1)) == CONST_INT
8265 && GET_CODE (src) == AND
8266 && GET_CODE (XEXP (src, 1)) == CONST_INT)
8268 HOST_WIDE_INT width = INTVAL (XEXP (dest, 1));
8269 unsigned HOST_WIDE_INT and_mask = INTVAL (XEXP (src, 1));
8270 unsigned HOST_WIDE_INT ze_mask;
8272 if (width >= HOST_BITS_PER_WIDE_INT)
8275 ze_mask = ((unsigned HOST_WIDE_INT)1 << width) - 1;
8277 /* Complete overlap. We can remove the source AND. */
8278 if ((and_mask & ze_mask) == ze_mask)
8279 return gen_rtx_SET (VOIDmode, dest, XEXP (src, 0));
8281 /* Partial overlap. We can reduce the source AND. */
8282 if ((and_mask & ze_mask) != and_mask)
8284 mode = GET_MODE (src);
8285 src = gen_rtx_AND (mode, XEXP (src, 0),
8286 gen_int_mode (and_mask & ze_mask, mode));
8287 return gen_rtx_SET (VOIDmode, dest, src);
8291 /* The other case we handle is assignments into a constant-position
8292 field. They look like (ior/xor (and DEST C1) OTHER). If C1 represents
8293 a mask that has all one bits except for a group of zero bits and
8294 OTHER is known to have zeros where C1 has ones, this is such an
8295 assignment. Compute the position and length from C1. Shift OTHER
8296 to the appropriate position, force it to the required mode, and
8297 make the extraction. Check for the AND in both operands. */
8299 if (GET_CODE (src) != IOR && GET_CODE (src) != XOR)
8302 rhs = expand_compound_operation (XEXP (src, 0));
8303 lhs = expand_compound_operation (XEXP (src, 1));
8305 if (GET_CODE (rhs) == AND
8306 && GET_CODE (XEXP (rhs, 1)) == CONST_INT
8307 && rtx_equal_for_field_assignment_p (XEXP (rhs, 0), dest))
8308 c1 = INTVAL (XEXP (rhs, 1)), other = lhs;
8309 else if (GET_CODE (lhs) == AND
8310 && GET_CODE (XEXP (lhs, 1)) == CONST_INT
8311 && rtx_equal_for_field_assignment_p (XEXP (lhs, 0), dest))
8312 c1 = INTVAL (XEXP (lhs, 1)), other = rhs;
8316 pos = get_pos_from_mask ((~c1) & GET_MODE_MASK (GET_MODE (dest)), &len);
8317 if (pos < 0 || pos + len > GET_MODE_BITSIZE (GET_MODE (dest))
8318 || GET_MODE_BITSIZE (GET_MODE (dest)) > HOST_BITS_PER_WIDE_INT
8319 || (c1 & nonzero_bits (other, GET_MODE (dest))) != 0)
8322 assign = make_extraction (VOIDmode, dest, pos, NULL_RTX, len, 1, 1, 0);
8326 /* The mode to use for the source is the mode of the assignment, or of
8327 what is inside a possible STRICT_LOW_PART. */
8328 mode = (GET_CODE (assign) == STRICT_LOW_PART
8329 ? GET_MODE (XEXP (assign, 0)) : GET_MODE (assign));
8331 /* Shift OTHER right POS places and make it the source, restricting it
8332 to the proper length and mode. */
8334 src = canon_reg_for_combine (simplify_shift_const (NULL_RTX, LSHIFTRT,
8338 src = force_to_mode (src, mode,
8339 GET_MODE_BITSIZE (mode) >= HOST_BITS_PER_WIDE_INT
8340 ? ~(unsigned HOST_WIDE_INT) 0
8341 : ((unsigned HOST_WIDE_INT) 1 << len) - 1,
8344 /* If SRC is masked by an AND that does not make a difference in
8345 the value being stored, strip it. */
8346 if (GET_CODE (assign) == ZERO_EXTRACT
8347 && GET_CODE (XEXP (assign, 1)) == CONST_INT
8348 && INTVAL (XEXP (assign, 1)) < HOST_BITS_PER_WIDE_INT
8349 && GET_CODE (src) == AND
8350 && GET_CODE (XEXP (src, 1)) == CONST_INT
8351 && ((unsigned HOST_WIDE_INT) INTVAL (XEXP (src, 1))
8352 == ((unsigned HOST_WIDE_INT) 1 << INTVAL (XEXP (assign, 1))) - 1))
8353 src = XEXP (src, 0);
8355 return gen_rtx_SET (VOIDmode, assign, src);
8358 /* See if X is of the form (+ (* a c) (* b c)) and convert to (* (+ a b) c)
8362 apply_distributive_law (rtx x)
8364 enum rtx_code code = GET_CODE (x);
8365 enum rtx_code inner_code;
8366 rtx lhs, rhs, other;
8369 /* Distributivity is not true for floating point as it can change the
8370 value. So we don't do it unless -funsafe-math-optimizations. */
8371 if (FLOAT_MODE_P (GET_MODE (x))
8372 && ! flag_unsafe_math_optimizations)
8375 /* The outer operation can only be one of the following: */
8376 if (code != IOR && code != AND && code != XOR
8377 && code != PLUS && code != MINUS)
8383 /* If either operand is a primitive we can't do anything, so get out
8385 if (OBJECT_P (lhs) || OBJECT_P (rhs))
8388 lhs = expand_compound_operation (lhs);
8389 rhs = expand_compound_operation (rhs);
8390 inner_code = GET_CODE (lhs);
8391 if (inner_code != GET_CODE (rhs))
8394 /* See if the inner and outer operations distribute. */
8401 /* These all distribute except over PLUS. */
8402 if (code == PLUS || code == MINUS)
8407 if (code != PLUS && code != MINUS)
8412 /* This is also a multiply, so it distributes over everything. */
8416 /* Non-paradoxical SUBREGs distributes over all operations,
8417 provided the inner modes and byte offsets are the same, this
8418 is an extraction of a low-order part, we don't convert an fp
8419 operation to int or vice versa, this is not a vector mode,
8420 and we would not be converting a single-word operation into a
8421 multi-word operation. The latter test is not required, but
8422 it prevents generating unneeded multi-word operations. Some
8423 of the previous tests are redundant given the latter test,
8424 but are retained because they are required for correctness.
8426 We produce the result slightly differently in this case. */
8428 if (GET_MODE (SUBREG_REG (lhs)) != GET_MODE (SUBREG_REG (rhs))
8429 || SUBREG_BYTE (lhs) != SUBREG_BYTE (rhs)
8430 || ! subreg_lowpart_p (lhs)
8431 || (GET_MODE_CLASS (GET_MODE (lhs))
8432 != GET_MODE_CLASS (GET_MODE (SUBREG_REG (lhs))))
8433 || (GET_MODE_SIZE (GET_MODE (lhs))
8434 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs))))
8435 || VECTOR_MODE_P (GET_MODE (lhs))
8436 || GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs))) > UNITS_PER_WORD
8437 /* Result might need to be truncated. Don't change mode if
8438 explicit truncation is needed. */
8439 || !TRULY_NOOP_TRUNCATION
8440 (GET_MODE_BITSIZE (GET_MODE (x)),
8441 GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (lhs)))))
8444 tem = simplify_gen_binary (code, GET_MODE (SUBREG_REG (lhs)),
8445 SUBREG_REG (lhs), SUBREG_REG (rhs));
8446 return gen_lowpart (GET_MODE (x), tem);
8452 /* Set LHS and RHS to the inner operands (A and B in the example
8453 above) and set OTHER to the common operand (C in the example).
8454 There is only one way to do this unless the inner operation is
8456 if (COMMUTATIVE_ARITH_P (lhs)
8457 && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 0)))
8458 other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 1);
8459 else if (COMMUTATIVE_ARITH_P (lhs)
8460 && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 1)))
8461 other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 0);
8462 else if (COMMUTATIVE_ARITH_P (lhs)
8463 && rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 0)))
8464 other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 1);
8465 else if (rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 1)))
8466 other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 0);
8470 /* Form the new inner operation, seeing if it simplifies first. */
8471 tem = simplify_gen_binary (code, GET_MODE (x), lhs, rhs);
8473 /* There is one exception to the general way of distributing:
8474 (a | c) ^ (b | c) -> (a ^ b) & ~c */
8475 if (code == XOR && inner_code == IOR)
8478 other = simplify_gen_unary (NOT, GET_MODE (x), other, GET_MODE (x));
8481 /* We may be able to continuing distributing the result, so call
8482 ourselves recursively on the inner operation before forming the
8483 outer operation, which we return. */
8484 return simplify_gen_binary (inner_code, GET_MODE (x),
8485 apply_distributive_law (tem), other);
8488 /* See if X is of the form (* (+ A B) C), and if so convert to
8489 (+ (* A C) (* B C)) and try to simplify.
8491 Most of the time, this results in no change. However, if some of
8492 the operands are the same or inverses of each other, simplifications
8495 For example, (and (ior A B) (not B)) can occur as the result of
8496 expanding a bit field assignment. When we apply the distributive
8497 law to this, we get (ior (and (A (not B))) (and (B (not B)))),
8498 which then simplifies to (and (A (not B))).
8500 Note that no checks happen on the validity of applying the inverse
8501 distributive law. This is pointless since we can do it in the
8502 few places where this routine is called.
8504 N is the index of the term that is decomposed (the arithmetic operation,
8505 i.e. (+ A B) in the first example above). !N is the index of the term that
8506 is distributed, i.e. of C in the first example above. */
8508 distribute_and_simplify_rtx (rtx x, int n)
8510 enum machine_mode mode;
8511 enum rtx_code outer_code, inner_code;
8512 rtx decomposed, distributed, inner_op0, inner_op1, new_op0, new_op1, tmp;
8514 decomposed = XEXP (x, n);
8515 if (!ARITHMETIC_P (decomposed))
8518 mode = GET_MODE (x);
8519 outer_code = GET_CODE (x);
8520 distributed = XEXP (x, !n);
8522 inner_code = GET_CODE (decomposed);
8523 inner_op0 = XEXP (decomposed, 0);
8524 inner_op1 = XEXP (decomposed, 1);
8526 /* Special case (and (xor B C) (not A)), which is equivalent to
8527 (xor (ior A B) (ior A C)) */
8528 if (outer_code == AND && inner_code == XOR && GET_CODE (distributed) == NOT)
8530 distributed = XEXP (distributed, 0);
8536 /* Distribute the second term. */
8537 new_op0 = simplify_gen_binary (outer_code, mode, inner_op0, distributed);
8538 new_op1 = simplify_gen_binary (outer_code, mode, inner_op1, distributed);
8542 /* Distribute the first term. */
8543 new_op0 = simplify_gen_binary (outer_code, mode, distributed, inner_op0);
8544 new_op1 = simplify_gen_binary (outer_code, mode, distributed, inner_op1);
8547 tmp = apply_distributive_law (simplify_gen_binary (inner_code, mode,
8549 if (GET_CODE (tmp) != outer_code
8550 && rtx_cost (tmp, SET) < rtx_cost (x, SET))
8556 /* Simplify a logical `and' of VAROP with the constant CONSTOP, to be done
8557 in MODE. Return an equivalent form, if different from (and VAROP
8558 (const_int CONSTOP)). Otherwise, return NULL_RTX. */
8561 simplify_and_const_int_1 (enum machine_mode mode, rtx varop,
8562 unsigned HOST_WIDE_INT constop)
8564 unsigned HOST_WIDE_INT nonzero;
8565 unsigned HOST_WIDE_INT orig_constop;
8570 orig_constop = constop;
8571 if (GET_CODE (varop) == CLOBBER)
8574 /* Simplify VAROP knowing that we will be only looking at some of the
8577 Note by passing in CONSTOP, we guarantee that the bits not set in
8578 CONSTOP are not significant and will never be examined. We must
8579 ensure that is the case by explicitly masking out those bits
8580 before returning. */
8581 varop = force_to_mode (varop, mode, constop, 0);
8583 /* If VAROP is a CLOBBER, we will fail so return it. */
8584 if (GET_CODE (varop) == CLOBBER)
8587 /* If VAROP is a CONST_INT, then we need to apply the mask in CONSTOP
8588 to VAROP and return the new constant. */
8589 if (GET_CODE (varop) == CONST_INT)
8590 return gen_int_mode (INTVAL (varop) & constop, mode);
8592 /* See what bits may be nonzero in VAROP. Unlike the general case of
8593 a call to nonzero_bits, here we don't care about bits outside
8596 nonzero = nonzero_bits (varop, mode) & GET_MODE_MASK (mode);
8598 /* Turn off all bits in the constant that are known to already be zero.
8599 Thus, if the AND isn't needed at all, we will have CONSTOP == NONZERO_BITS
8600 which is tested below. */
8604 /* If we don't have any bits left, return zero. */
8608 /* If VAROP is a NEG of something known to be zero or 1 and CONSTOP is
8609 a power of two, we can replace this with an ASHIFT. */
8610 if (GET_CODE (varop) == NEG && nonzero_bits (XEXP (varop, 0), mode) == 1
8611 && (i = exact_log2 (constop)) >= 0)
8612 return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (varop, 0), i);
8614 /* If VAROP is an IOR or XOR, apply the AND to both branches of the IOR
8615 or XOR, then try to apply the distributive law. This may eliminate
8616 operations if either branch can be simplified because of the AND.
8617 It may also make some cases more complex, but those cases probably
8618 won't match a pattern either with or without this. */
8620 if (GET_CODE (varop) == IOR || GET_CODE (varop) == XOR)
8624 apply_distributive_law
8625 (simplify_gen_binary (GET_CODE (varop), GET_MODE (varop),
8626 simplify_and_const_int (NULL_RTX,
8630 simplify_and_const_int (NULL_RTX,
8635 /* If VAROP is PLUS, and the constant is a mask of low bits, distribute
8636 the AND and see if one of the operands simplifies to zero. If so, we
8637 may eliminate it. */
8639 if (GET_CODE (varop) == PLUS
8640 && exact_log2 (constop + 1) >= 0)
8644 o0 = simplify_and_const_int (NULL_RTX, mode, XEXP (varop, 0), constop);
8645 o1 = simplify_and_const_int (NULL_RTX, mode, XEXP (varop, 1), constop);
8646 if (o0 == const0_rtx)
8648 if (o1 == const0_rtx)
8652 /* Make a SUBREG if necessary. If we can't make it, fail. */
8653 varop = gen_lowpart (mode, varop);
8654 if (varop == NULL_RTX || GET_CODE (varop) == CLOBBER)
8657 /* If we are only masking insignificant bits, return VAROP. */
8658 if (constop == nonzero)
8661 if (varop == orig_varop && constop == orig_constop)
8664 /* Otherwise, return an AND. */
8665 return simplify_gen_binary (AND, mode, varop, gen_int_mode (constop, mode));
8669 /* We have X, a logical `and' of VAROP with the constant CONSTOP, to be done
8672 Return an equivalent form, if different from X. Otherwise, return X. If
8673 X is zero, we are to always construct the equivalent form. */
8676 simplify_and_const_int (rtx x, enum machine_mode mode, rtx varop,
8677 unsigned HOST_WIDE_INT constop)
8679 rtx tem = simplify_and_const_int_1 (mode, varop, constop);
8684 x = simplify_gen_binary (AND, GET_MODE (varop), varop,
8685 gen_int_mode (constop, mode));
8686 if (GET_MODE (x) != mode)
8687 x = gen_lowpart (mode, x);
8691 /* Given a REG, X, compute which bits in X can be nonzero.
8692 We don't care about bits outside of those defined in MODE.
8694 For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is
8695 a shift, AND, or zero_extract, we can do better. */
8698 reg_nonzero_bits_for_combine (const_rtx x, enum machine_mode mode,
8699 const_rtx known_x ATTRIBUTE_UNUSED,
8700 enum machine_mode known_mode ATTRIBUTE_UNUSED,
8701 unsigned HOST_WIDE_INT known_ret ATTRIBUTE_UNUSED,
8702 unsigned HOST_WIDE_INT *nonzero)
8707 /* If X is a register whose nonzero bits value is current, use it.
8708 Otherwise, if X is a register whose value we can find, use that
8709 value. Otherwise, use the previously-computed global nonzero bits
8710 for this register. */
8712 rsp = VEC_index (reg_stat_type, reg_stat, REGNO (x));
8713 if (rsp->last_set_value != 0
8714 && (rsp->last_set_mode == mode
8715 || (GET_MODE_CLASS (rsp->last_set_mode) == MODE_INT
8716 && GET_MODE_CLASS (mode) == MODE_INT))
8717 && ((rsp->last_set_label >= label_tick_ebb_start
8718 && rsp->last_set_label < label_tick)
8719 || (rsp->last_set_label == label_tick
8720 && DF_INSN_LUID (rsp->last_set) < subst_low_luid)
8721 || (REGNO (x) >= FIRST_PSEUDO_REGISTER
8722 && REG_N_SETS (REGNO (x)) == 1
8724 (DF_LR_IN (ENTRY_BLOCK_PTR->next_bb), REGNO (x)))))
8726 *nonzero &= rsp->last_set_nonzero_bits;
8730 tem = get_last_value (x);
8734 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
8735 /* If X is narrower than MODE and TEM is a non-negative
8736 constant that would appear negative in the mode of X,
8737 sign-extend it for use in reg_nonzero_bits because some
8738 machines (maybe most) will actually do the sign-extension
8739 and this is the conservative approach.
8741 ??? For 2.5, try to tighten up the MD files in this regard
8742 instead of this kludge. */
8744 if (GET_MODE_BITSIZE (GET_MODE (x)) < GET_MODE_BITSIZE (mode)
8745 && GET_CODE (tem) == CONST_INT
8747 && 0 != (INTVAL (tem)
8748 & ((HOST_WIDE_INT) 1
8749 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
8750 tem = GEN_INT (INTVAL (tem)
8751 | ((HOST_WIDE_INT) (-1)
8752 << GET_MODE_BITSIZE (GET_MODE (x))));
8756 else if (nonzero_sign_valid && rsp->nonzero_bits)
8758 unsigned HOST_WIDE_INT mask = rsp->nonzero_bits;
8760 if (GET_MODE_BITSIZE (GET_MODE (x)) < GET_MODE_BITSIZE (mode))
8761 /* We don't know anything about the upper bits. */
8762 mask |= GET_MODE_MASK (mode) ^ GET_MODE_MASK (GET_MODE (x));
8769 /* Return the number of bits at the high-order end of X that are known to
8770 be equal to the sign bit. X will be used in mode MODE; if MODE is
8771 VOIDmode, X will be used in its own mode. The returned value will always
8772 be between 1 and the number of bits in MODE. */
8775 reg_num_sign_bit_copies_for_combine (const_rtx x, enum machine_mode mode,
8776 const_rtx known_x ATTRIBUTE_UNUSED,
8777 enum machine_mode known_mode
8779 unsigned int known_ret ATTRIBUTE_UNUSED,
8780 unsigned int *result)
8785 rsp = VEC_index (reg_stat_type, reg_stat, REGNO (x));
8786 if (rsp->last_set_value != 0
8787 && rsp->last_set_mode == mode
8788 && ((rsp->last_set_label >= label_tick_ebb_start
8789 && rsp->last_set_label < label_tick)
8790 || (rsp->last_set_label == label_tick
8791 && DF_INSN_LUID (rsp->last_set) < subst_low_luid)
8792 || (REGNO (x) >= FIRST_PSEUDO_REGISTER
8793 && REG_N_SETS (REGNO (x)) == 1
8795 (DF_LR_IN (ENTRY_BLOCK_PTR->next_bb), REGNO (x)))))
8797 *result = rsp->last_set_sign_bit_copies;
8801 tem = get_last_value (x);
8805 if (nonzero_sign_valid && rsp->sign_bit_copies != 0
8806 && GET_MODE_BITSIZE (GET_MODE (x)) == GET_MODE_BITSIZE (mode))
8807 *result = rsp->sign_bit_copies;
8812 /* Return the number of "extended" bits there are in X, when interpreted
8813 as a quantity in MODE whose signedness is indicated by UNSIGNEDP. For
8814 unsigned quantities, this is the number of high-order zero bits.
8815 For signed quantities, this is the number of copies of the sign bit
8816 minus 1. In both case, this function returns the number of "spare"
8817 bits. For example, if two quantities for which this function returns
8818 at least 1 are added, the addition is known not to overflow.
8820 This function will always return 0 unless called during combine, which
8821 implies that it must be called from a define_split. */
8824 extended_count (const_rtx x, enum machine_mode mode, int unsignedp)
8826 if (nonzero_sign_valid == 0)
8830 ? (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
8831 ? (unsigned int) (GET_MODE_BITSIZE (mode) - 1
8832 - floor_log2 (nonzero_bits (x, mode)))
8834 : num_sign_bit_copies (x, mode) - 1);
8837 /* This function is called from `simplify_shift_const' to merge two
8838 outer operations. Specifically, we have already found that we need
8839 to perform operation *POP0 with constant *PCONST0 at the outermost
8840 position. We would now like to also perform OP1 with constant CONST1
8841 (with *POP0 being done last).
8843 Return 1 if we can do the operation and update *POP0 and *PCONST0 with
8844 the resulting operation. *PCOMP_P is set to 1 if we would need to
8845 complement the innermost operand, otherwise it is unchanged.
8847 MODE is the mode in which the operation will be done. No bits outside
8848 the width of this mode matter. It is assumed that the width of this mode
8849 is smaller than or equal to HOST_BITS_PER_WIDE_INT.
8851 If *POP0 or OP1 are UNKNOWN, it means no operation is required. Only NEG, PLUS,
8852 IOR, XOR, and AND are supported. We may set *POP0 to SET if the proper
8853 result is simply *PCONST0.
8855 If the resulting operation cannot be expressed as one operation, we
8856 return 0 and do not change *POP0, *PCONST0, and *PCOMP_P. */
8859 merge_outer_ops (enum rtx_code *pop0, HOST_WIDE_INT *pconst0, enum rtx_code op1, HOST_WIDE_INT const1, enum machine_mode mode, int *pcomp_p)
8861 enum rtx_code op0 = *pop0;
8862 HOST_WIDE_INT const0 = *pconst0;
8864 const0 &= GET_MODE_MASK (mode);
8865 const1 &= GET_MODE_MASK (mode);
8867 /* If OP0 is an AND, clear unimportant bits in CONST1. */
8871 /* If OP0 or OP1 is UNKNOWN, this is easy. Similarly if they are the same or
8874 if (op1 == UNKNOWN || op0 == SET)
8877 else if (op0 == UNKNOWN)
8878 op0 = op1, const0 = const1;
8880 else if (op0 == op1)
8904 /* Otherwise, if either is a PLUS or NEG, we can't do anything. */
8905 else if (op0 == PLUS || op1 == PLUS || op0 == NEG || op1 == NEG)
8908 /* If the two constants aren't the same, we can't do anything. The
8909 remaining six cases can all be done. */
8910 else if (const0 != const1)
8918 /* (a & b) | b == b */
8920 else /* op1 == XOR */
8921 /* (a ^ b) | b == a | b */
8927 /* (a & b) ^ b == (~a) & b */
8928 op0 = AND, *pcomp_p = 1;
8929 else /* op1 == IOR */
8930 /* (a | b) ^ b == a & ~b */
8931 op0 = AND, const0 = ~const0;
8936 /* (a | b) & b == b */
8938 else /* op1 == XOR */
8939 /* (a ^ b) & b) == (~a) & b */
8946 /* Check for NO-OP cases. */
8947 const0 &= GET_MODE_MASK (mode);
8949 && (op0 == IOR || op0 == XOR || op0 == PLUS))
8951 else if (const0 == 0 && op0 == AND)
8953 else if ((unsigned HOST_WIDE_INT) const0 == GET_MODE_MASK (mode)
8957 /* ??? Slightly redundant with the above mask, but not entirely.
8958 Moving this above means we'd have to sign-extend the mode mask
8959 for the final test. */
8960 const0 = trunc_int_for_mode (const0, mode);
8968 /* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift.
8969 The result of the shift is RESULT_MODE. Return NULL_RTX if we cannot
8970 simplify it. Otherwise, return a simplified value.
8972 The shift is normally computed in the widest mode we find in VAROP, as
8973 long as it isn't a different number of words than RESULT_MODE. Exceptions
8974 are ASHIFTRT and ROTATE, which are always done in their original mode. */
8977 simplify_shift_const_1 (enum rtx_code code, enum machine_mode result_mode,
8978 rtx varop, int orig_count)
8980 enum rtx_code orig_code = code;
8981 rtx orig_varop = varop;
8983 enum machine_mode mode = result_mode;
8984 enum machine_mode shift_mode, tmode;
8985 unsigned int mode_words
8986 = (GET_MODE_SIZE (mode) + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD;
8987 /* We form (outer_op (code varop count) (outer_const)). */
8988 enum rtx_code outer_op = UNKNOWN;
8989 HOST_WIDE_INT outer_const = 0;
8990 int complement_p = 0;
8993 /* Make sure and truncate the "natural" shift on the way in. We don't
8994 want to do this inside the loop as it makes it more difficult to
8996 if (SHIFT_COUNT_TRUNCATED)
8997 orig_count &= GET_MODE_BITSIZE (mode) - 1;
8999 /* If we were given an invalid count, don't do anything except exactly
9000 what was requested. */
9002 if (orig_count < 0 || orig_count >= (int) GET_MODE_BITSIZE (mode))
9007 /* Unless one of the branches of the `if' in this loop does a `continue',
9008 we will `break' the loop after the `if'. */
9012 /* If we have an operand of (clobber (const_int 0)), fail. */
9013 if (GET_CODE (varop) == CLOBBER)
9016 /* If we discovered we had to complement VAROP, leave. Making a NOT
9017 here would cause an infinite loop. */
9021 /* Convert ROTATERT to ROTATE. */
9022 if (code == ROTATERT)
9024 unsigned int bitsize = GET_MODE_BITSIZE (result_mode);;
9026 if (VECTOR_MODE_P (result_mode))
9027 count = bitsize / GET_MODE_NUNITS (result_mode) - count;
9029 count = bitsize - count;
9032 /* We need to determine what mode we will do the shift in. If the
9033 shift is a right shift or a ROTATE, we must always do it in the mode
9034 it was originally done in. Otherwise, we can do it in MODE, the
9035 widest mode encountered. */
9037 = (code == ASHIFTRT || code == LSHIFTRT || code == ROTATE
9038 ? result_mode : mode);
9040 /* Handle cases where the count is greater than the size of the mode
9041 minus 1. For ASHIFT, use the size minus one as the count (this can
9042 occur when simplifying (lshiftrt (ashiftrt ..))). For rotates,
9043 take the count modulo the size. For other shifts, the result is
9046 Since these shifts are being produced by the compiler by combining
9047 multiple operations, each of which are defined, we know what the
9048 result is supposed to be. */
9050 if (count > (GET_MODE_BITSIZE (shift_mode) - 1))
9052 if (code == ASHIFTRT)
9053 count = GET_MODE_BITSIZE (shift_mode) - 1;
9054 else if (code == ROTATE || code == ROTATERT)
9055 count %= GET_MODE_BITSIZE (shift_mode);
9058 /* We can't simply return zero because there may be an
9066 /* An arithmetic right shift of a quantity known to be -1 or 0
9068 if (code == ASHIFTRT
9069 && (num_sign_bit_copies (varop, shift_mode)
9070 == GET_MODE_BITSIZE (shift_mode)))
9076 /* If we are doing an arithmetic right shift and discarding all but
9077 the sign bit copies, this is equivalent to doing a shift by the
9078 bitsize minus one. Convert it into that shift because it will often
9079 allow other simplifications. */
9081 if (code == ASHIFTRT
9082 && (count + num_sign_bit_copies (varop, shift_mode)
9083 >= GET_MODE_BITSIZE (shift_mode)))
9084 count = GET_MODE_BITSIZE (shift_mode) - 1;
9086 /* We simplify the tests below and elsewhere by converting
9087 ASHIFTRT to LSHIFTRT if we know the sign bit is clear.
9088 `make_compound_operation' will convert it to an ASHIFTRT for
9089 those machines (such as VAX) that don't have an LSHIFTRT. */
9090 if (GET_MODE_BITSIZE (shift_mode) <= HOST_BITS_PER_WIDE_INT
9092 && ((nonzero_bits (varop, shift_mode)
9093 & ((HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (shift_mode) - 1)))
9097 if (((code == LSHIFTRT
9098 && GET_MODE_BITSIZE (shift_mode) <= HOST_BITS_PER_WIDE_INT
9099 && !(nonzero_bits (varop, shift_mode) >> count))
9101 && GET_MODE_BITSIZE (shift_mode) <= HOST_BITS_PER_WIDE_INT
9102 && !((nonzero_bits (varop, shift_mode) << count)
9103 & GET_MODE_MASK (shift_mode))))
9104 && !side_effects_p (varop))
9107 switch (GET_CODE (varop))
9113 new = expand_compound_operation (varop);
9122 /* If we have (xshiftrt (mem ...) C) and C is MODE_WIDTH
9123 minus the width of a smaller mode, we can do this with a
9124 SIGN_EXTEND or ZERO_EXTEND from the narrower memory location. */
9125 if ((code == ASHIFTRT || code == LSHIFTRT)
9126 && ! mode_dependent_address_p (XEXP (varop, 0))
9127 && ! MEM_VOLATILE_P (varop)
9128 && (tmode = mode_for_size (GET_MODE_BITSIZE (mode) - count,
9129 MODE_INT, 1)) != BLKmode)
9131 new = adjust_address_nv (varop, tmode,
9132 BYTES_BIG_ENDIAN ? 0
9133 : count / BITS_PER_UNIT);
9135 varop = gen_rtx_fmt_e (code == ASHIFTRT ? SIGN_EXTEND
9136 : ZERO_EXTEND, mode, new);
9143 /* If VAROP is a SUBREG, strip it as long as the inner operand has
9144 the same number of words as what we've seen so far. Then store
9145 the widest mode in MODE. */
9146 if (subreg_lowpart_p (varop)
9147 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop)))
9148 > GET_MODE_SIZE (GET_MODE (varop)))
9149 && (unsigned int) ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop)))
9150 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
9153 varop = SUBREG_REG (varop);
9154 if (GET_MODE_SIZE (GET_MODE (varop)) > GET_MODE_SIZE (mode))
9155 mode = GET_MODE (varop);
9161 /* Some machines use MULT instead of ASHIFT because MULT
9162 is cheaper. But it is still better on those machines to
9163 merge two shifts into one. */
9164 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
9165 && exact_log2 (INTVAL (XEXP (varop, 1))) >= 0)
9168 = simplify_gen_binary (ASHIFT, GET_MODE (varop),
9170 GEN_INT (exact_log2 (
9171 INTVAL (XEXP (varop, 1)))));
9177 /* Similar, for when divides are cheaper. */
9178 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
9179 && exact_log2 (INTVAL (XEXP (varop, 1))) >= 0)
9182 = simplify_gen_binary (LSHIFTRT, GET_MODE (varop),
9184 GEN_INT (exact_log2 (
9185 INTVAL (XEXP (varop, 1)))));
9191 /* If we are extracting just the sign bit of an arithmetic
9192 right shift, that shift is not needed. However, the sign
9193 bit of a wider mode may be different from what would be
9194 interpreted as the sign bit in a narrower mode, so, if
9195 the result is narrower, don't discard the shift. */
9196 if (code == LSHIFTRT
9197 && count == (GET_MODE_BITSIZE (result_mode) - 1)
9198 && (GET_MODE_BITSIZE (result_mode)
9199 >= GET_MODE_BITSIZE (GET_MODE (varop))))
9201 varop = XEXP (varop, 0);
9205 /* ... fall through ... */
9210 /* Here we have two nested shifts. The result is usually the
9211 AND of a new shift with a mask. We compute the result below. */
9212 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
9213 && INTVAL (XEXP (varop, 1)) >= 0
9214 && INTVAL (XEXP (varop, 1)) < GET_MODE_BITSIZE (GET_MODE (varop))
9215 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
9216 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
9217 && !VECTOR_MODE_P (result_mode))
9219 enum rtx_code first_code = GET_CODE (varop);
9220 unsigned int first_count = INTVAL (XEXP (varop, 1));
9221 unsigned HOST_WIDE_INT mask;
9224 /* We have one common special case. We can't do any merging if
9225 the inner code is an ASHIFTRT of a smaller mode. However, if
9226 we have (ashift:M1 (subreg:M1 (ashiftrt:M2 FOO C1) 0) C2)
9227 with C2 == GET_MODE_BITSIZE (M1) - GET_MODE_BITSIZE (M2),
9228 we can convert it to
9229 (ashiftrt:M1 (ashift:M1 (and:M1 (subreg:M1 FOO 0 C2) C3) C1).
9230 This simplifies certain SIGN_EXTEND operations. */
9231 if (code == ASHIFT && first_code == ASHIFTRT
9232 && count == (GET_MODE_BITSIZE (result_mode)
9233 - GET_MODE_BITSIZE (GET_MODE (varop))))
9235 /* C3 has the low-order C1 bits zero. */
9237 mask = (GET_MODE_MASK (mode)
9238 & ~(((HOST_WIDE_INT) 1 << first_count) - 1));
9240 varop = simplify_and_const_int (NULL_RTX, result_mode,
9241 XEXP (varop, 0), mask);
9242 varop = simplify_shift_const (NULL_RTX, ASHIFT, result_mode,
9244 count = first_count;
9249 /* If this was (ashiftrt (ashift foo C1) C2) and FOO has more
9250 than C1 high-order bits equal to the sign bit, we can convert
9251 this to either an ASHIFT or an ASHIFTRT depending on the
9254 We cannot do this if VAROP's mode is not SHIFT_MODE. */
9256 if (code == ASHIFTRT && first_code == ASHIFT
9257 && GET_MODE (varop) == shift_mode
9258 && (num_sign_bit_copies (XEXP (varop, 0), shift_mode)
9261 varop = XEXP (varop, 0);
9262 count -= first_count;
9272 /* There are some cases we can't do. If CODE is ASHIFTRT,
9273 we can only do this if FIRST_CODE is also ASHIFTRT.
9275 We can't do the case when CODE is ROTATE and FIRST_CODE is
9278 If the mode of this shift is not the mode of the outer shift,
9279 we can't do this if either shift is a right shift or ROTATE.
9281 Finally, we can't do any of these if the mode is too wide
9282 unless the codes are the same.
9284 Handle the case where the shift codes are the same
9287 if (code == first_code)
9289 if (GET_MODE (varop) != result_mode
9290 && (code == ASHIFTRT || code == LSHIFTRT
9294 count += first_count;
9295 varop = XEXP (varop, 0);
9299 if (code == ASHIFTRT
9300 || (code == ROTATE && first_code == ASHIFTRT)
9301 || GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT
9302 || (GET_MODE (varop) != result_mode
9303 && (first_code == ASHIFTRT || first_code == LSHIFTRT
9304 || first_code == ROTATE
9305 || code == ROTATE)))
9308 /* To compute the mask to apply after the shift, shift the
9309 nonzero bits of the inner shift the same way the
9310 outer shift will. */
9312 mask_rtx = GEN_INT (nonzero_bits (varop, GET_MODE (varop)));
9315 = simplify_const_binary_operation (code, result_mode, mask_rtx,
9318 /* Give up if we can't compute an outer operation to use. */
9320 || GET_CODE (mask_rtx) != CONST_INT
9321 || ! merge_outer_ops (&outer_op, &outer_const, AND,
9323 result_mode, &complement_p))
9326 /* If the shifts are in the same direction, we add the
9327 counts. Otherwise, we subtract them. */
9328 if ((code == ASHIFTRT || code == LSHIFTRT)
9329 == (first_code == ASHIFTRT || first_code == LSHIFTRT))
9330 count += first_count;
9332 count -= first_count;
9334 /* If COUNT is positive, the new shift is usually CODE,
9335 except for the two exceptions below, in which case it is
9336 FIRST_CODE. If the count is negative, FIRST_CODE should
9339 && ((first_code == ROTATE && code == ASHIFT)
9340 || (first_code == ASHIFTRT && code == LSHIFTRT)))
9343 code = first_code, count = -count;
9345 varop = XEXP (varop, 0);
9349 /* If we have (A << B << C) for any shift, we can convert this to
9350 (A << C << B). This wins if A is a constant. Only try this if
9351 B is not a constant. */
9353 else if (GET_CODE (varop) == code
9354 && GET_CODE (XEXP (varop, 0)) == CONST_INT
9355 && GET_CODE (XEXP (varop, 1)) != CONST_INT)
9357 rtx new = simplify_const_binary_operation (code, mode,
9360 varop = gen_rtx_fmt_ee (code, mode, new, XEXP (varop, 1));
9367 if (VECTOR_MODE_P (mode))
9370 /* Make this fit the case below. */
9371 varop = gen_rtx_XOR (mode, XEXP (varop, 0),
9372 GEN_INT (GET_MODE_MASK (mode)));
9378 /* If we have (xshiftrt (ior (plus X (const_int -1)) X) C)
9379 with C the size of VAROP - 1 and the shift is logical if
9380 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
9381 we have an (le X 0) operation. If we have an arithmetic shift
9382 and STORE_FLAG_VALUE is 1 or we have a logical shift with
9383 STORE_FLAG_VALUE of -1, we have a (neg (le X 0)) operation. */
9385 if (GET_CODE (varop) == IOR && GET_CODE (XEXP (varop, 0)) == PLUS
9386 && XEXP (XEXP (varop, 0), 1) == constm1_rtx
9387 && (STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
9388 && (code == LSHIFTRT || code == ASHIFTRT)
9389 && count == (GET_MODE_BITSIZE (GET_MODE (varop)) - 1)
9390 && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
9393 varop = gen_rtx_LE (GET_MODE (varop), XEXP (varop, 1),
9396 if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
9397 varop = gen_rtx_NEG (GET_MODE (varop), varop);
9402 /* If we have (shift (logical)), move the logical to the outside
9403 to allow it to possibly combine with another logical and the
9404 shift to combine with another shift. This also canonicalizes to
9405 what a ZERO_EXTRACT looks like. Also, some machines have
9406 (and (shift)) insns. */
9408 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
9409 /* We can't do this if we have (ashiftrt (xor)) and the
9410 constant has its sign bit set in shift_mode. */
9411 && !(code == ASHIFTRT && GET_CODE (varop) == XOR
9412 && 0 > trunc_int_for_mode (INTVAL (XEXP (varop, 1)),
9414 && (new = simplify_const_binary_operation (code, result_mode,
9416 GEN_INT (count))) != 0
9417 && GET_CODE (new) == CONST_INT
9418 && merge_outer_ops (&outer_op, &outer_const, GET_CODE (varop),
9419 INTVAL (new), result_mode, &complement_p))
9421 varop = XEXP (varop, 0);
9425 /* If we can't do that, try to simplify the shift in each arm of the
9426 logical expression, make a new logical expression, and apply
9427 the inverse distributive law. This also can't be done
9428 for some (ashiftrt (xor)). */
9429 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
9430 && !(code == ASHIFTRT && GET_CODE (varop) == XOR
9431 && 0 > trunc_int_for_mode (INTVAL (XEXP (varop, 1)),
9434 rtx lhs = simplify_shift_const (NULL_RTX, code, shift_mode,
9435 XEXP (varop, 0), count);
9436 rtx rhs = simplify_shift_const (NULL_RTX, code, shift_mode,
9437 XEXP (varop, 1), count);
9439 varop = simplify_gen_binary (GET_CODE (varop), shift_mode,
9441 varop = apply_distributive_law (varop);
9449 /* Convert (lshiftrt (eq FOO 0) C) to (xor FOO 1) if STORE_FLAG_VALUE
9450 says that the sign bit can be tested, FOO has mode MODE, C is
9451 GET_MODE_BITSIZE (MODE) - 1, and FOO has only its low-order bit
9452 that may be nonzero. */
9453 if (code == LSHIFTRT
9454 && XEXP (varop, 1) == const0_rtx
9455 && GET_MODE (XEXP (varop, 0)) == result_mode
9456 && count == (GET_MODE_BITSIZE (result_mode) - 1)
9457 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
9458 && STORE_FLAG_VALUE == -1
9459 && nonzero_bits (XEXP (varop, 0), result_mode) == 1
9460 && merge_outer_ops (&outer_op, &outer_const, XOR,
9461 (HOST_WIDE_INT) 1, result_mode,
9464 varop = XEXP (varop, 0);
9471 /* (lshiftrt (neg A) C) where A is either 0 or 1 and C is one less
9472 than the number of bits in the mode is equivalent to A. */
9473 if (code == LSHIFTRT
9474 && count == (GET_MODE_BITSIZE (result_mode) - 1)
9475 && nonzero_bits (XEXP (varop, 0), result_mode) == 1)
9477 varop = XEXP (varop, 0);
9482 /* NEG commutes with ASHIFT since it is multiplication. Move the
9483 NEG outside to allow shifts to combine. */
9485 && merge_outer_ops (&outer_op, &outer_const, NEG,
9486 (HOST_WIDE_INT) 0, result_mode,
9489 varop = XEXP (varop, 0);
9495 /* (lshiftrt (plus A -1) C) where A is either 0 or 1 and C
9496 is one less than the number of bits in the mode is
9497 equivalent to (xor A 1). */
9498 if (code == LSHIFTRT
9499 && count == (GET_MODE_BITSIZE (result_mode) - 1)
9500 && XEXP (varop, 1) == constm1_rtx
9501 && nonzero_bits (XEXP (varop, 0), result_mode) == 1
9502 && merge_outer_ops (&outer_op, &outer_const, XOR,
9503 (HOST_WIDE_INT) 1, result_mode,
9507 varop = XEXP (varop, 0);
9511 /* If we have (xshiftrt (plus FOO BAR) C), and the only bits
9512 that might be nonzero in BAR are those being shifted out and those
9513 bits are known zero in FOO, we can replace the PLUS with FOO.
9514 Similarly in the other operand order. This code occurs when
9515 we are computing the size of a variable-size array. */
9517 if ((code == ASHIFTRT || code == LSHIFTRT)
9518 && count < HOST_BITS_PER_WIDE_INT
9519 && nonzero_bits (XEXP (varop, 1), result_mode) >> count == 0
9520 && (nonzero_bits (XEXP (varop, 1), result_mode)
9521 & nonzero_bits (XEXP (varop, 0), result_mode)) == 0)
9523 varop = XEXP (varop, 0);
9526 else if ((code == ASHIFTRT || code == LSHIFTRT)
9527 && count < HOST_BITS_PER_WIDE_INT
9528 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
9529 && 0 == (nonzero_bits (XEXP (varop, 0), result_mode)
9531 && 0 == (nonzero_bits (XEXP (varop, 0), result_mode)
9532 & nonzero_bits (XEXP (varop, 1),
9535 varop = XEXP (varop, 1);
9539 /* (ashift (plus foo C) N) is (plus (ashift foo N) C'). */
9541 && GET_CODE (XEXP (varop, 1)) == CONST_INT
9542 && (new = simplify_const_binary_operation (ASHIFT, result_mode,
9544 GEN_INT (count))) != 0
9545 && GET_CODE (new) == CONST_INT
9546 && merge_outer_ops (&outer_op, &outer_const, PLUS,
9547 INTVAL (new), result_mode, &complement_p))
9549 varop = XEXP (varop, 0);
9553 /* Check for 'PLUS signbit', which is the canonical form of 'XOR
9554 signbit', and attempt to change the PLUS to an XOR and move it to
9555 the outer operation as is done above in the AND/IOR/XOR case
9556 leg for shift(logical). See details in logical handling above
9557 for reasoning in doing so. */
9558 if (code == LSHIFTRT
9559 && GET_CODE (XEXP (varop, 1)) == CONST_INT
9560 && mode_signbit_p (result_mode, XEXP (varop, 1))
9561 && (new = simplify_const_binary_operation (code, result_mode,
9563 GEN_INT (count))) != 0
9564 && GET_CODE (new) == CONST_INT
9565 && merge_outer_ops (&outer_op, &outer_const, XOR,
9566 INTVAL (new), result_mode, &complement_p))
9568 varop = XEXP (varop, 0);
9575 /* If we have (xshiftrt (minus (ashiftrt X C)) X) C)
9576 with C the size of VAROP - 1 and the shift is logical if
9577 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
9578 we have a (gt X 0) operation. If the shift is arithmetic with
9579 STORE_FLAG_VALUE of 1 or logical with STORE_FLAG_VALUE == -1,
9580 we have a (neg (gt X 0)) operation. */
9582 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
9583 && GET_CODE (XEXP (varop, 0)) == ASHIFTRT
9584 && count == (GET_MODE_BITSIZE (GET_MODE (varop)) - 1)
9585 && (code == LSHIFTRT || code == ASHIFTRT)
9586 && GET_CODE (XEXP (XEXP (varop, 0), 1)) == CONST_INT
9587 && INTVAL (XEXP (XEXP (varop, 0), 1)) == count
9588 && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
9591 varop = gen_rtx_GT (GET_MODE (varop), XEXP (varop, 1),
9594 if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
9595 varop = gen_rtx_NEG (GET_MODE (varop), varop);
9602 /* Change (lshiftrt (truncate (lshiftrt))) to (truncate (lshiftrt))
9603 if the truncate does not affect the value. */
9604 if (code == LSHIFTRT
9605 && GET_CODE (XEXP (varop, 0)) == LSHIFTRT
9606 && GET_CODE (XEXP (XEXP (varop, 0), 1)) == CONST_INT
9607 && (INTVAL (XEXP (XEXP (varop, 0), 1))
9608 >= (GET_MODE_BITSIZE (GET_MODE (XEXP (varop, 0)))
9609 - GET_MODE_BITSIZE (GET_MODE (varop)))))
9611 rtx varop_inner = XEXP (varop, 0);
9614 = gen_rtx_LSHIFTRT (GET_MODE (varop_inner),
9615 XEXP (varop_inner, 0),
9617 (count + INTVAL (XEXP (varop_inner, 1))));
9618 varop = gen_rtx_TRUNCATE (GET_MODE (varop), varop_inner);
9631 /* We need to determine what mode to do the shift in. If the shift is
9632 a right shift or ROTATE, we must always do it in the mode it was
9633 originally done in. Otherwise, we can do it in MODE, the widest mode
9634 encountered. The code we care about is that of the shift that will
9635 actually be done, not the shift that was originally requested. */
9637 = (code == ASHIFTRT || code == LSHIFTRT || code == ROTATE
9638 ? result_mode : mode);
9640 /* We have now finished analyzing the shift. The result should be
9641 a shift of type CODE with SHIFT_MODE shifting VAROP COUNT places. If
9642 OUTER_OP is non-UNKNOWN, it is an operation that needs to be applied
9643 to the result of the shift. OUTER_CONST is the relevant constant,
9644 but we must turn off all bits turned off in the shift. */
9646 if (outer_op == UNKNOWN
9647 && orig_code == code && orig_count == count
9648 && varop == orig_varop
9649 && shift_mode == GET_MODE (varop))
9652 /* Make a SUBREG if necessary. If we can't make it, fail. */
9653 varop = gen_lowpart (shift_mode, varop);
9654 if (varop == NULL_RTX || GET_CODE (varop) == CLOBBER)
9657 /* If we have an outer operation and we just made a shift, it is
9658 possible that we could have simplified the shift were it not
9659 for the outer operation. So try to do the simplification
9662 if (outer_op != UNKNOWN)
9663 x = simplify_shift_const_1 (code, shift_mode, varop, count);
9668 x = simplify_gen_binary (code, shift_mode, varop, GEN_INT (count));
9670 /* If we were doing an LSHIFTRT in a wider mode than it was originally,
9671 turn off all the bits that the shift would have turned off. */
9672 if (orig_code == LSHIFTRT && result_mode != shift_mode)
9673 x = simplify_and_const_int (NULL_RTX, shift_mode, x,
9674 GET_MODE_MASK (result_mode) >> orig_count);
9676 /* Do the remainder of the processing in RESULT_MODE. */
9677 x = gen_lowpart_or_truncate (result_mode, x);
9679 /* If COMPLEMENT_P is set, we have to complement X before doing the outer
9682 x = simplify_gen_unary (NOT, result_mode, x, result_mode);
9684 if (outer_op != UNKNOWN)
9686 if (GET_MODE_BITSIZE (result_mode) < HOST_BITS_PER_WIDE_INT)
9687 outer_const = trunc_int_for_mode (outer_const, result_mode);
9689 if (outer_op == AND)
9690 x = simplify_and_const_int (NULL_RTX, result_mode, x, outer_const);
9691 else if (outer_op == SET)
9693 /* This means that we have determined that the result is
9694 equivalent to a constant. This should be rare. */
9695 if (!side_effects_p (x))
9696 x = GEN_INT (outer_const);
9698 else if (GET_RTX_CLASS (outer_op) == RTX_UNARY)
9699 x = simplify_gen_unary (outer_op, result_mode, x, result_mode);
9701 x = simplify_gen_binary (outer_op, result_mode, x,
9702 GEN_INT (outer_const));
9708 /* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift.
9709 The result of the shift is RESULT_MODE. If we cannot simplify it,
9710 return X or, if it is NULL, synthesize the expression with
9711 simplify_gen_binary. Otherwise, return a simplified value.
9713 The shift is normally computed in the widest mode we find in VAROP, as
9714 long as it isn't a different number of words than RESULT_MODE. Exceptions
9715 are ASHIFTRT and ROTATE, which are always done in their original mode. */
9718 simplify_shift_const (rtx x, enum rtx_code code, enum machine_mode result_mode,
9719 rtx varop, int count)
9721 rtx tem = simplify_shift_const_1 (code, result_mode, varop, count);
9726 x = simplify_gen_binary (code, GET_MODE (varop), varop, GEN_INT (count));
9727 if (GET_MODE (x) != result_mode)
9728 x = gen_lowpart (result_mode, x);
9733 /* Like recog, but we receive the address of a pointer to a new pattern.
9734 We try to match the rtx that the pointer points to.
9735 If that fails, we may try to modify or replace the pattern,
9736 storing the replacement into the same pointer object.
9738 Modifications include deletion or addition of CLOBBERs.
9740 PNOTES is a pointer to a location where any REG_UNUSED notes added for
9741 the CLOBBERs are placed.
9743 The value is the final insn code from the pattern ultimately matched,
9747 recog_for_combine (rtx *pnewpat, rtx insn, rtx *pnotes)
9750 int insn_code_number;
9751 int num_clobbers_to_add = 0;
9754 rtx old_notes, old_pat;
9756 /* If PAT is a PARALLEL, check to see if it contains the CLOBBER
9757 we use to indicate that something didn't match. If we find such a
9758 thing, force rejection. */
9759 if (GET_CODE (pat) == PARALLEL)
9760 for (i = XVECLEN (pat, 0) - 1; i >= 0; i--)
9761 if (GET_CODE (XVECEXP (pat, 0, i)) == CLOBBER
9762 && XEXP (XVECEXP (pat, 0, i), 0) == const0_rtx)
9765 old_pat = PATTERN (insn);
9766 old_notes = REG_NOTES (insn);
9767 PATTERN (insn) = pat;
9768 REG_NOTES (insn) = 0;
9770 insn_code_number = recog (pat, insn, &num_clobbers_to_add);
9771 if (dump_file && (dump_flags & TDF_DETAILS))
9773 if (insn_code_number < 0)
9774 fputs ("Failed to match this instruction:\n", dump_file);
9776 fputs ("Successfully matched this instruction:\n", dump_file);
9777 print_rtl_single (dump_file, pat);
9780 /* If it isn't, there is the possibility that we previously had an insn
9781 that clobbered some register as a side effect, but the combined
9782 insn doesn't need to do that. So try once more without the clobbers
9783 unless this represents an ASM insn. */
9785 if (insn_code_number < 0 && ! check_asm_operands (pat)
9786 && GET_CODE (pat) == PARALLEL)
9790 for (pos = 0, i = 0; i < XVECLEN (pat, 0); i++)
9791 if (GET_CODE (XVECEXP (pat, 0, i)) != CLOBBER)
9794 SUBST (XVECEXP (pat, 0, pos), XVECEXP (pat, 0, i));
9798 SUBST_INT (XVECLEN (pat, 0), pos);
9801 pat = XVECEXP (pat, 0, 0);
9803 PATTERN (insn) = pat;
9804 insn_code_number = recog (pat, insn, &num_clobbers_to_add);
9805 if (dump_file && (dump_flags & TDF_DETAILS))
9807 if (insn_code_number < 0)
9808 fputs ("Failed to match this instruction:\n", dump_file);
9810 fputs ("Successfully matched this instruction:\n", dump_file);
9811 print_rtl_single (dump_file, pat);
9814 PATTERN (insn) = old_pat;
9815 REG_NOTES (insn) = old_notes;
9817 /* Recognize all noop sets, these will be killed by followup pass. */
9818 if (insn_code_number < 0 && GET_CODE (pat) == SET && set_noop_p (pat))
9819 insn_code_number = NOOP_MOVE_INSN_CODE, num_clobbers_to_add = 0;
9821 /* If we had any clobbers to add, make a new pattern than contains
9822 them. Then check to make sure that all of them are dead. */
9823 if (num_clobbers_to_add)
9825 rtx newpat = gen_rtx_PARALLEL (VOIDmode,
9826 rtvec_alloc (GET_CODE (pat) == PARALLEL
9828 + num_clobbers_to_add)
9829 : num_clobbers_to_add + 1));
9831 if (GET_CODE (pat) == PARALLEL)
9832 for (i = 0; i < XVECLEN (pat, 0); i++)
9833 XVECEXP (newpat, 0, i) = XVECEXP (pat, 0, i);
9835 XVECEXP (newpat, 0, 0) = pat;
9837 add_clobbers (newpat, insn_code_number);
9839 for (i = XVECLEN (newpat, 0) - num_clobbers_to_add;
9840 i < XVECLEN (newpat, 0); i++)
9842 if (REG_P (XEXP (XVECEXP (newpat, 0, i), 0))
9843 && ! reg_dead_at_p (XEXP (XVECEXP (newpat, 0, i), 0), insn))
9845 if (GET_CODE (XEXP (XVECEXP (newpat, 0, i), 0)) != SCRATCH)
9847 gcc_assert (REG_P (XEXP (XVECEXP (newpat, 0, i), 0)));
9848 notes = gen_rtx_EXPR_LIST (REG_UNUSED,
9849 XEXP (XVECEXP (newpat, 0, i), 0), notes);
9858 return insn_code_number;
9861 /* Like gen_lowpart_general but for use by combine. In combine it
9862 is not possible to create any new pseudoregs. However, it is
9863 safe to create invalid memory addresses, because combine will
9864 try to recognize them and all they will do is make the combine
9867 If for some reason this cannot do its job, an rtx
9868 (clobber (const_int 0)) is returned.
9869 An insn containing that will not be recognized. */
9872 gen_lowpart_for_combine (enum machine_mode omode, rtx x)
9874 enum machine_mode imode = GET_MODE (x);
9875 unsigned int osize = GET_MODE_SIZE (omode);
9876 unsigned int isize = GET_MODE_SIZE (imode);
9882 /* Return identity if this is a CONST or symbolic reference. */
9884 && (GET_CODE (x) == CONST
9885 || GET_CODE (x) == SYMBOL_REF
9886 || GET_CODE (x) == LABEL_REF))
9889 /* We can only support MODE being wider than a word if X is a
9890 constant integer or has a mode the same size. */
9891 if (GET_MODE_SIZE (omode) > UNITS_PER_WORD
9892 && ! ((imode == VOIDmode
9893 && (GET_CODE (x) == CONST_INT
9894 || GET_CODE (x) == CONST_DOUBLE))
9898 /* X might be a paradoxical (subreg (mem)). In that case, gen_lowpart
9899 won't know what to do. So we will strip off the SUBREG here and
9900 process normally. */
9901 if (GET_CODE (x) == SUBREG && MEM_P (SUBREG_REG (x)))
9905 /* For use in case we fall down into the address adjustments
9906 further below, we need to adjust the known mode and size of
9907 x; imode and isize, since we just adjusted x. */
9908 imode = GET_MODE (x);
9913 isize = GET_MODE_SIZE (imode);
9916 result = gen_lowpart_common (omode, x);
9925 /* Refuse to work on a volatile memory ref or one with a mode-dependent
9927 if (MEM_VOLATILE_P (x) || mode_dependent_address_p (XEXP (x, 0)))
9930 /* If we want to refer to something bigger than the original memref,
9931 generate a paradoxical subreg instead. That will force a reload
9932 of the original memref X. */
9934 return gen_rtx_SUBREG (omode, x, 0);
9936 if (WORDS_BIG_ENDIAN)
9937 offset = MAX (isize, UNITS_PER_WORD) - MAX (osize, UNITS_PER_WORD);
9939 /* Adjust the address so that the address-after-the-data is
9941 if (BYTES_BIG_ENDIAN)
9942 offset -= MIN (UNITS_PER_WORD, osize) - MIN (UNITS_PER_WORD, isize);
9944 return adjust_address_nv (x, omode, offset);
9947 /* If X is a comparison operator, rewrite it in a new mode. This
9948 probably won't match, but may allow further simplifications. */
9949 else if (COMPARISON_P (x))
9950 return gen_rtx_fmt_ee (GET_CODE (x), omode, XEXP (x, 0), XEXP (x, 1));
9952 /* If we couldn't simplify X any other way, just enclose it in a
9953 SUBREG. Normally, this SUBREG won't match, but some patterns may
9954 include an explicit SUBREG or we may simplify it further in combine. */
9960 offset = subreg_lowpart_offset (omode, imode);
9961 if (imode == VOIDmode)
9963 imode = int_mode_for_mode (omode);
9964 x = gen_lowpart_common (imode, x);
9968 res = simplify_gen_subreg (omode, x, imode, offset);
9974 return gen_rtx_CLOBBER (imode, const0_rtx);
9977 /* Simplify a comparison between *POP0 and *POP1 where CODE is the
9978 comparison code that will be tested.
9980 The result is a possibly different comparison code to use. *POP0 and
9981 *POP1 may be updated.
9983 It is possible that we might detect that a comparison is either always
9984 true or always false. However, we do not perform general constant
9985 folding in combine, so this knowledge isn't useful. Such tautologies
9986 should have been detected earlier. Hence we ignore all such cases. */
9988 static enum rtx_code
9989 simplify_comparison (enum rtx_code code, rtx *pop0, rtx *pop1)
9995 enum machine_mode mode, tmode;
9997 /* Try a few ways of applying the same transformation to both operands. */
10000 #ifndef WORD_REGISTER_OPERATIONS
10001 /* The test below this one won't handle SIGN_EXTENDs on these machines,
10002 so check specially. */
10003 if (code != GTU && code != GEU && code != LTU && code != LEU
10004 && GET_CODE (op0) == ASHIFTRT && GET_CODE (op1) == ASHIFTRT
10005 && GET_CODE (XEXP (op0, 0)) == ASHIFT
10006 && GET_CODE (XEXP (op1, 0)) == ASHIFT
10007 && GET_CODE (XEXP (XEXP (op0, 0), 0)) == SUBREG
10008 && GET_CODE (XEXP (XEXP (op1, 0), 0)) == SUBREG
10009 && (GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0)))
10010 == GET_MODE (SUBREG_REG (XEXP (XEXP (op1, 0), 0))))
10011 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10012 && XEXP (op0, 1) == XEXP (op1, 1)
10013 && XEXP (op0, 1) == XEXP (XEXP (op0, 0), 1)
10014 && XEXP (op0, 1) == XEXP (XEXP (op1, 0), 1)
10015 && (INTVAL (XEXP (op0, 1))
10016 == (GET_MODE_BITSIZE (GET_MODE (op0))
10017 - (GET_MODE_BITSIZE
10018 (GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0))))))))
10020 op0 = SUBREG_REG (XEXP (XEXP (op0, 0), 0));
10021 op1 = SUBREG_REG (XEXP (XEXP (op1, 0), 0));
10025 /* If both operands are the same constant shift, see if we can ignore the
10026 shift. We can if the shift is a rotate or if the bits shifted out of
10027 this shift are known to be zero for both inputs and if the type of
10028 comparison is compatible with the shift. */
10029 if (GET_CODE (op0) == GET_CODE (op1)
10030 && GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
10031 && ((GET_CODE (op0) == ROTATE && (code == NE || code == EQ))
10032 || ((GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFT)
10033 && (code != GT && code != LT && code != GE && code != LE))
10034 || (GET_CODE (op0) == ASHIFTRT
10035 && (code != GTU && code != LTU
10036 && code != GEU && code != LEU)))
10037 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10038 && INTVAL (XEXP (op0, 1)) >= 0
10039 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT
10040 && XEXP (op0, 1) == XEXP (op1, 1))
10042 enum machine_mode mode = GET_MODE (op0);
10043 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
10044 int shift_count = INTVAL (XEXP (op0, 1));
10046 if (GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFTRT)
10047 mask &= (mask >> shift_count) << shift_count;
10048 else if (GET_CODE (op0) == ASHIFT)
10049 mask = (mask & (mask << shift_count)) >> shift_count;
10051 if ((nonzero_bits (XEXP (op0, 0), mode) & ~mask) == 0
10052 && (nonzero_bits (XEXP (op1, 0), mode) & ~mask) == 0)
10053 op0 = XEXP (op0, 0), op1 = XEXP (op1, 0);
10058 /* If both operands are AND's of a paradoxical SUBREG by constant, the
10059 SUBREGs are of the same mode, and, in both cases, the AND would
10060 be redundant if the comparison was done in the narrower mode,
10061 do the comparison in the narrower mode (e.g., we are AND'ing with 1
10062 and the operand's possibly nonzero bits are 0xffffff01; in that case
10063 if we only care about QImode, we don't need the AND). This case
10064 occurs if the output mode of an scc insn is not SImode and
10065 STORE_FLAG_VALUE == 1 (e.g., the 386).
10067 Similarly, check for a case where the AND's are ZERO_EXTEND
10068 operations from some narrower mode even though a SUBREG is not
10071 else if (GET_CODE (op0) == AND && GET_CODE (op1) == AND
10072 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10073 && GET_CODE (XEXP (op1, 1)) == CONST_INT)
10075 rtx inner_op0 = XEXP (op0, 0);
10076 rtx inner_op1 = XEXP (op1, 0);
10077 HOST_WIDE_INT c0 = INTVAL (XEXP (op0, 1));
10078 HOST_WIDE_INT c1 = INTVAL (XEXP (op1, 1));
10081 if (GET_CODE (inner_op0) == SUBREG && GET_CODE (inner_op1) == SUBREG
10082 && (GET_MODE_SIZE (GET_MODE (inner_op0))
10083 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (inner_op0))))
10084 && (GET_MODE (SUBREG_REG (inner_op0))
10085 == GET_MODE (SUBREG_REG (inner_op1)))
10086 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (inner_op0)))
10087 <= HOST_BITS_PER_WIDE_INT)
10088 && (0 == ((~c0) & nonzero_bits (SUBREG_REG (inner_op0),
10089 GET_MODE (SUBREG_REG (inner_op0)))))
10090 && (0 == ((~c1) & nonzero_bits (SUBREG_REG (inner_op1),
10091 GET_MODE (SUBREG_REG (inner_op1))))))
10093 op0 = SUBREG_REG (inner_op0);
10094 op1 = SUBREG_REG (inner_op1);
10096 /* The resulting comparison is always unsigned since we masked
10097 off the original sign bit. */
10098 code = unsigned_condition (code);
10104 for (tmode = GET_CLASS_NARROWEST_MODE
10105 (GET_MODE_CLASS (GET_MODE (op0)));
10106 tmode != GET_MODE (op0); tmode = GET_MODE_WIDER_MODE (tmode))
10107 if ((unsigned HOST_WIDE_INT) c0 == GET_MODE_MASK (tmode))
10109 op0 = gen_lowpart (tmode, inner_op0);
10110 op1 = gen_lowpart (tmode, inner_op1);
10111 code = unsigned_condition (code);
10120 /* If both operands are NOT, we can strip off the outer operation
10121 and adjust the comparison code for swapped operands; similarly for
10122 NEG, except that this must be an equality comparison. */
10123 else if ((GET_CODE (op0) == NOT && GET_CODE (op1) == NOT)
10124 || (GET_CODE (op0) == NEG && GET_CODE (op1) == NEG
10125 && (code == EQ || code == NE)))
10126 op0 = XEXP (op0, 0), op1 = XEXP (op1, 0), code = swap_condition (code);
10132 /* If the first operand is a constant, swap the operands and adjust the
10133 comparison code appropriately, but don't do this if the second operand
10134 is already a constant integer. */
10135 if (swap_commutative_operands_p (op0, op1))
10137 tem = op0, op0 = op1, op1 = tem;
10138 code = swap_condition (code);
10141 /* We now enter a loop during which we will try to simplify the comparison.
10142 For the most part, we only are concerned with comparisons with zero,
10143 but some things may really be comparisons with zero but not start
10144 out looking that way. */
10146 while (GET_CODE (op1) == CONST_INT)
10148 enum machine_mode mode = GET_MODE (op0);
10149 unsigned int mode_width = GET_MODE_BITSIZE (mode);
10150 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
10151 int equality_comparison_p;
10152 int sign_bit_comparison_p;
10153 int unsigned_comparison_p;
10154 HOST_WIDE_INT const_op;
10156 /* We only want to handle integral modes. This catches VOIDmode,
10157 CCmode, and the floating-point modes. An exception is that we
10158 can handle VOIDmode if OP0 is a COMPARE or a comparison
10161 if (GET_MODE_CLASS (mode) != MODE_INT
10162 && ! (mode == VOIDmode
10163 && (GET_CODE (op0) == COMPARE || COMPARISON_P (op0))))
10166 /* Get the constant we are comparing against and turn off all bits
10167 not on in our mode. */
10168 const_op = INTVAL (op1);
10169 if (mode != VOIDmode)
10170 const_op = trunc_int_for_mode (const_op, mode);
10171 op1 = GEN_INT (const_op);
10173 /* If we are comparing against a constant power of two and the value
10174 being compared can only have that single bit nonzero (e.g., it was
10175 `and'ed with that bit), we can replace this with a comparison
10178 && (code == EQ || code == NE || code == GE || code == GEU
10179 || code == LT || code == LTU)
10180 && mode_width <= HOST_BITS_PER_WIDE_INT
10181 && exact_log2 (const_op) >= 0
10182 && nonzero_bits (op0, mode) == (unsigned HOST_WIDE_INT) const_op)
10184 code = (code == EQ || code == GE || code == GEU ? NE : EQ);
10185 op1 = const0_rtx, const_op = 0;
10188 /* Similarly, if we are comparing a value known to be either -1 or
10189 0 with -1, change it to the opposite comparison against zero. */
10192 && (code == EQ || code == NE || code == GT || code == LE
10193 || code == GEU || code == LTU)
10194 && num_sign_bit_copies (op0, mode) == mode_width)
10196 code = (code == EQ || code == LE || code == GEU ? NE : EQ);
10197 op1 = const0_rtx, const_op = 0;
10200 /* Do some canonicalizations based on the comparison code. We prefer
10201 comparisons against zero and then prefer equality comparisons.
10202 If we can reduce the size of a constant, we will do that too. */
10207 /* < C is equivalent to <= (C - 1) */
10211 op1 = GEN_INT (const_op);
10213 /* ... fall through to LE case below. */
10219 /* <= C is equivalent to < (C + 1); we do this for C < 0 */
10223 op1 = GEN_INT (const_op);
10227 /* If we are doing a <= 0 comparison on a value known to have
10228 a zero sign bit, we can replace this with == 0. */
10229 else if (const_op == 0
10230 && mode_width <= HOST_BITS_PER_WIDE_INT
10231 && (nonzero_bits (op0, mode)
10232 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)
10237 /* >= C is equivalent to > (C - 1). */
10241 op1 = GEN_INT (const_op);
10243 /* ... fall through to GT below. */
10249 /* > C is equivalent to >= (C + 1); we do this for C < 0. */
10253 op1 = GEN_INT (const_op);
10257 /* If we are doing a > 0 comparison on a value known to have
10258 a zero sign bit, we can replace this with != 0. */
10259 else if (const_op == 0
10260 && mode_width <= HOST_BITS_PER_WIDE_INT
10261 && (nonzero_bits (op0, mode)
10262 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)
10267 /* < C is equivalent to <= (C - 1). */
10271 op1 = GEN_INT (const_op);
10273 /* ... fall through ... */
10276 /* (unsigned) < 0x80000000 is equivalent to >= 0. */
10277 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
10278 && (const_op == (HOST_WIDE_INT) 1 << (mode_width - 1)))
10280 const_op = 0, op1 = const0_rtx;
10288 /* unsigned <= 0 is equivalent to == 0 */
10292 /* (unsigned) <= 0x7fffffff is equivalent to >= 0. */
10293 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
10294 && (const_op == ((HOST_WIDE_INT) 1 << (mode_width - 1)) - 1))
10296 const_op = 0, op1 = const0_rtx;
10302 /* >= C is equivalent to > (C - 1). */
10306 op1 = GEN_INT (const_op);
10308 /* ... fall through ... */
10311 /* (unsigned) >= 0x80000000 is equivalent to < 0. */
10312 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
10313 && (const_op == (HOST_WIDE_INT) 1 << (mode_width - 1)))
10315 const_op = 0, op1 = const0_rtx;
10323 /* unsigned > 0 is equivalent to != 0 */
10327 /* (unsigned) > 0x7fffffff is equivalent to < 0. */
10328 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
10329 && (const_op == ((HOST_WIDE_INT) 1 << (mode_width - 1)) - 1))
10331 const_op = 0, op1 = const0_rtx;
10340 /* Compute some predicates to simplify code below. */
10342 equality_comparison_p = (code == EQ || code == NE);
10343 sign_bit_comparison_p = ((code == LT || code == GE) && const_op == 0);
10344 unsigned_comparison_p = (code == LTU || code == LEU || code == GTU
10347 /* If this is a sign bit comparison and we can do arithmetic in
10348 MODE, say that we will only be needing the sign bit of OP0. */
10349 if (sign_bit_comparison_p
10350 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
10351 op0 = force_to_mode (op0, mode,
10353 << (GET_MODE_BITSIZE (mode) - 1)),
10356 /* Now try cases based on the opcode of OP0. If none of the cases
10357 does a "continue", we exit this loop immediately after the
10360 switch (GET_CODE (op0))
10363 /* If we are extracting a single bit from a variable position in
10364 a constant that has only a single bit set and are comparing it
10365 with zero, we can convert this into an equality comparison
10366 between the position and the location of the single bit. */
10367 /* Except we can't if SHIFT_COUNT_TRUNCATED is set, since we might
10368 have already reduced the shift count modulo the word size. */
10369 if (!SHIFT_COUNT_TRUNCATED
10370 && GET_CODE (XEXP (op0, 0)) == CONST_INT
10371 && XEXP (op0, 1) == const1_rtx
10372 && equality_comparison_p && const_op == 0
10373 && (i = exact_log2 (INTVAL (XEXP (op0, 0)))) >= 0)
10375 if (BITS_BIG_ENDIAN)
10377 enum machine_mode new_mode
10378 = mode_for_extraction (EP_extzv, 1);
10379 if (new_mode == MAX_MACHINE_MODE)
10380 i = BITS_PER_WORD - 1 - i;
10384 i = (GET_MODE_BITSIZE (mode) - 1 - i);
10388 op0 = XEXP (op0, 2);
10392 /* Result is nonzero iff shift count is equal to I. */
10393 code = reverse_condition (code);
10397 /* ... fall through ... */
10400 tem = expand_compound_operation (op0);
10409 /* If testing for equality, we can take the NOT of the constant. */
10410 if (equality_comparison_p
10411 && (tem = simplify_unary_operation (NOT, mode, op1, mode)) != 0)
10413 op0 = XEXP (op0, 0);
10418 /* If just looking at the sign bit, reverse the sense of the
10420 if (sign_bit_comparison_p)
10422 op0 = XEXP (op0, 0);
10423 code = (code == GE ? LT : GE);
10429 /* If testing for equality, we can take the NEG of the constant. */
10430 if (equality_comparison_p
10431 && (tem = simplify_unary_operation (NEG, mode, op1, mode)) != 0)
10433 op0 = XEXP (op0, 0);
10438 /* The remaining cases only apply to comparisons with zero. */
10442 /* When X is ABS or is known positive,
10443 (neg X) is < 0 if and only if X != 0. */
10445 if (sign_bit_comparison_p
10446 && (GET_CODE (XEXP (op0, 0)) == ABS
10447 || (mode_width <= HOST_BITS_PER_WIDE_INT
10448 && (nonzero_bits (XEXP (op0, 0), mode)
10449 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)))
10451 op0 = XEXP (op0, 0);
10452 code = (code == LT ? NE : EQ);
10456 /* If we have NEG of something whose two high-order bits are the
10457 same, we know that "(-a) < 0" is equivalent to "a > 0". */
10458 if (num_sign_bit_copies (op0, mode) >= 2)
10460 op0 = XEXP (op0, 0);
10461 code = swap_condition (code);
10467 /* If we are testing equality and our count is a constant, we
10468 can perform the inverse operation on our RHS. */
10469 if (equality_comparison_p && GET_CODE (XEXP (op0, 1)) == CONST_INT
10470 && (tem = simplify_binary_operation (ROTATERT, mode,
10471 op1, XEXP (op0, 1))) != 0)
10473 op0 = XEXP (op0, 0);
10478 /* If we are doing a < 0 or >= 0 comparison, it means we are testing
10479 a particular bit. Convert it to an AND of a constant of that
10480 bit. This will be converted into a ZERO_EXTRACT. */
10481 if (const_op == 0 && sign_bit_comparison_p
10482 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10483 && mode_width <= HOST_BITS_PER_WIDE_INT)
10485 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
10488 - INTVAL (XEXP (op0, 1)))));
10489 code = (code == LT ? NE : EQ);
10493 /* Fall through. */
10496 /* ABS is ignorable inside an equality comparison with zero. */
10497 if (const_op == 0 && equality_comparison_p)
10499 op0 = XEXP (op0, 0);
10505 /* Can simplify (compare (zero/sign_extend FOO) CONST) to
10506 (compare FOO CONST) if CONST fits in FOO's mode and we
10507 are either testing inequality or have an unsigned
10508 comparison with ZERO_EXTEND or a signed comparison with
10509 SIGN_EXTEND. But don't do it if we don't have a compare
10510 insn of the given mode, since we'd have to revert it
10511 later on, and then we wouldn't know whether to sign- or
10513 mode = GET_MODE (XEXP (op0, 0));
10514 if (mode != VOIDmode && GET_MODE_CLASS (mode) == MODE_INT
10515 && ! unsigned_comparison_p
10516 && (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
10517 && ((unsigned HOST_WIDE_INT) const_op
10518 < (((unsigned HOST_WIDE_INT) 1
10519 << (GET_MODE_BITSIZE (mode) - 1))))
10520 && optab_handler (cmp_optab, mode)->insn_code != CODE_FOR_nothing)
10522 op0 = XEXP (op0, 0);
10528 /* Check for the case where we are comparing A - C1 with C2, that is
10530 (subreg:MODE (plus (A) (-C1))) op (C2)
10532 with C1 a constant, and try to lift the SUBREG, i.e. to do the
10533 comparison in the wider mode. One of the following two conditions
10534 must be true in order for this to be valid:
10536 1. The mode extension results in the same bit pattern being added
10537 on both sides and the comparison is equality or unsigned. As
10538 C2 has been truncated to fit in MODE, the pattern can only be
10541 2. The mode extension results in the sign bit being copied on
10544 The difficulty here is that we have predicates for A but not for
10545 (A - C1) so we need to check that C1 is within proper bounds so
10546 as to perturbate A as little as possible. */
10548 if (mode_width <= HOST_BITS_PER_WIDE_INT
10549 && subreg_lowpart_p (op0)
10550 && GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0))) > mode_width
10551 && GET_CODE (SUBREG_REG (op0)) == PLUS
10552 && GET_CODE (XEXP (SUBREG_REG (op0), 1)) == CONST_INT)
10554 enum machine_mode inner_mode = GET_MODE (SUBREG_REG (op0));
10555 rtx a = XEXP (SUBREG_REG (op0), 0);
10556 HOST_WIDE_INT c1 = -INTVAL (XEXP (SUBREG_REG (op0), 1));
10559 && (unsigned HOST_WIDE_INT) c1
10560 < (unsigned HOST_WIDE_INT) 1 << (mode_width - 1)
10561 && (equality_comparison_p || unsigned_comparison_p)
10562 /* (A - C1) zero-extends if it is positive and sign-extends
10563 if it is negative, C2 both zero- and sign-extends. */
10564 && ((0 == (nonzero_bits (a, inner_mode)
10565 & ~GET_MODE_MASK (mode))
10567 /* (A - C1) sign-extends if it is positive and 1-extends
10568 if it is negative, C2 both sign- and 1-extends. */
10569 || (num_sign_bit_copies (a, inner_mode)
10570 > (unsigned int) (GET_MODE_BITSIZE (inner_mode)
10573 || ((unsigned HOST_WIDE_INT) c1
10574 < (unsigned HOST_WIDE_INT) 1 << (mode_width - 2)
10575 /* (A - C1) always sign-extends, like C2. */
10576 && num_sign_bit_copies (a, inner_mode)
10577 > (unsigned int) (GET_MODE_BITSIZE (inner_mode)
10578 - (mode_width - 1))))
10580 op0 = SUBREG_REG (op0);
10585 /* If the inner mode is narrower and we are extracting the low part,
10586 we can treat the SUBREG as if it were a ZERO_EXTEND. */
10587 if (subreg_lowpart_p (op0)
10588 && GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0))) < mode_width)
10589 /* Fall through */ ;
10593 /* ... fall through ... */
10596 mode = GET_MODE (XEXP (op0, 0));
10597 if (mode != VOIDmode && GET_MODE_CLASS (mode) == MODE_INT
10598 && (unsigned_comparison_p || equality_comparison_p)
10599 && (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
10600 && ((unsigned HOST_WIDE_INT) const_op < GET_MODE_MASK (mode))
10601 && optab_handler (cmp_optab, mode)->insn_code != CODE_FOR_nothing)
10603 op0 = XEXP (op0, 0);
10609 /* (eq (plus X A) B) -> (eq X (minus B A)). We can only do
10610 this for equality comparisons due to pathological cases involving
10612 if (equality_comparison_p
10613 && 0 != (tem = simplify_binary_operation (MINUS, mode,
10614 op1, XEXP (op0, 1))))
10616 op0 = XEXP (op0, 0);
10621 /* (plus (abs X) (const_int -1)) is < 0 if and only if X == 0. */
10622 if (const_op == 0 && XEXP (op0, 1) == constm1_rtx
10623 && GET_CODE (XEXP (op0, 0)) == ABS && sign_bit_comparison_p)
10625 op0 = XEXP (XEXP (op0, 0), 0);
10626 code = (code == LT ? EQ : NE);
10632 /* We used to optimize signed comparisons against zero, but that
10633 was incorrect. Unsigned comparisons against zero (GTU, LEU)
10634 arrive here as equality comparisons, or (GEU, LTU) are
10635 optimized away. No need to special-case them. */
10637 /* (eq (minus A B) C) -> (eq A (plus B C)) or
10638 (eq B (minus A C)), whichever simplifies. We can only do
10639 this for equality comparisons due to pathological cases involving
10641 if (equality_comparison_p
10642 && 0 != (tem = simplify_binary_operation (PLUS, mode,
10643 XEXP (op0, 1), op1)))
10645 op0 = XEXP (op0, 0);
10650 if (equality_comparison_p
10651 && 0 != (tem = simplify_binary_operation (MINUS, mode,
10652 XEXP (op0, 0), op1)))
10654 op0 = XEXP (op0, 1);
10659 /* The sign bit of (minus (ashiftrt X C) X), where C is the number
10660 of bits in X minus 1, is one iff X > 0. */
10661 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == ASHIFTRT
10662 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
10663 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (XEXP (op0, 0), 1))
10665 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
10667 op0 = XEXP (op0, 1);
10668 code = (code == GE ? LE : GT);
10674 /* (eq (xor A B) C) -> (eq A (xor B C)). This is a simplification
10675 if C is zero or B is a constant. */
10676 if (equality_comparison_p
10677 && 0 != (tem = simplify_binary_operation (XOR, mode,
10678 XEXP (op0, 1), op1)))
10680 op0 = XEXP (op0, 0);
10687 case UNEQ: case LTGT:
10688 case LT: case LTU: case UNLT: case LE: case LEU: case UNLE:
10689 case GT: case GTU: case UNGT: case GE: case GEU: case UNGE:
10690 case UNORDERED: case ORDERED:
10691 /* We can't do anything if OP0 is a condition code value, rather
10692 than an actual data value. */
10694 || CC0_P (XEXP (op0, 0))
10695 || GET_MODE_CLASS (GET_MODE (XEXP (op0, 0))) == MODE_CC)
10698 /* Get the two operands being compared. */
10699 if (GET_CODE (XEXP (op0, 0)) == COMPARE)
10700 tem = XEXP (XEXP (op0, 0), 0), tem1 = XEXP (XEXP (op0, 0), 1);
10702 tem = XEXP (op0, 0), tem1 = XEXP (op0, 1);
10704 /* Check for the cases where we simply want the result of the
10705 earlier test or the opposite of that result. */
10706 if (code == NE || code == EQ
10707 || (GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
10708 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
10709 && (STORE_FLAG_VALUE
10710 & (((HOST_WIDE_INT) 1
10711 << (GET_MODE_BITSIZE (GET_MODE (op0)) - 1))))
10712 && (code == LT || code == GE)))
10714 enum rtx_code new_code;
10715 if (code == LT || code == NE)
10716 new_code = GET_CODE (op0);
10718 new_code = reversed_comparison_code (op0, NULL);
10720 if (new_code != UNKNOWN)
10731 /* The sign bit of (ior (plus X (const_int -1)) X) is nonzero
10733 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == PLUS
10734 && XEXP (XEXP (op0, 0), 1) == constm1_rtx
10735 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
10737 op0 = XEXP (op0, 1);
10738 code = (code == GE ? GT : LE);
10744 /* Convert (and (xshift 1 X) Y) to (and (lshiftrt Y X) 1). This
10745 will be converted to a ZERO_EXTRACT later. */
10746 if (const_op == 0 && equality_comparison_p
10747 && GET_CODE (XEXP (op0, 0)) == ASHIFT
10748 && XEXP (XEXP (op0, 0), 0) == const1_rtx)
10750 op0 = simplify_and_const_int
10751 (NULL_RTX, mode, gen_rtx_LSHIFTRT (mode,
10753 XEXP (XEXP (op0, 0), 1)),
10754 (HOST_WIDE_INT) 1);
10758 /* If we are comparing (and (lshiftrt X C1) C2) for equality with
10759 zero and X is a comparison and C1 and C2 describe only bits set
10760 in STORE_FLAG_VALUE, we can compare with X. */
10761 if (const_op == 0 && equality_comparison_p
10762 && mode_width <= HOST_BITS_PER_WIDE_INT
10763 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10764 && GET_CODE (XEXP (op0, 0)) == LSHIFTRT
10765 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
10766 && INTVAL (XEXP (XEXP (op0, 0), 1)) >= 0
10767 && INTVAL (XEXP (XEXP (op0, 0), 1)) < HOST_BITS_PER_WIDE_INT)
10769 mask = ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
10770 << INTVAL (XEXP (XEXP (op0, 0), 1)));
10771 if ((~STORE_FLAG_VALUE & mask) == 0
10772 && (COMPARISON_P (XEXP (XEXP (op0, 0), 0))
10773 || ((tem = get_last_value (XEXP (XEXP (op0, 0), 0))) != 0
10774 && COMPARISON_P (tem))))
10776 op0 = XEXP (XEXP (op0, 0), 0);
10781 /* If we are doing an equality comparison of an AND of a bit equal
10782 to the sign bit, replace this with a LT or GE comparison of
10783 the underlying value. */
10784 if (equality_comparison_p
10786 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10787 && mode_width <= HOST_BITS_PER_WIDE_INT
10788 && ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
10789 == (unsigned HOST_WIDE_INT) 1 << (mode_width - 1)))
10791 op0 = XEXP (op0, 0);
10792 code = (code == EQ ? GE : LT);
10796 /* If this AND operation is really a ZERO_EXTEND from a narrower
10797 mode, the constant fits within that mode, and this is either an
10798 equality or unsigned comparison, try to do this comparison in
10803 (ne:DI (and:DI (reg:DI 4) (const_int 0xffffffff)) (const_int 0))
10804 -> (ne:DI (reg:SI 4) (const_int 0))
10806 unless TRULY_NOOP_TRUNCATION allows it or the register is
10807 known to hold a value of the required mode the
10808 transformation is invalid. */
10809 if ((equality_comparison_p || unsigned_comparison_p)
10810 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10811 && (i = exact_log2 ((INTVAL (XEXP (op0, 1))
10812 & GET_MODE_MASK (mode))
10814 && const_op >> i == 0
10815 && (tmode = mode_for_size (i, MODE_INT, 1)) != BLKmode
10816 && (TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (tmode),
10817 GET_MODE_BITSIZE (GET_MODE (op0)))
10818 || (REG_P (XEXP (op0, 0))
10819 && reg_truncated_to_mode (tmode, XEXP (op0, 0)))))
10821 op0 = gen_lowpart (tmode, XEXP (op0, 0));
10825 /* If this is (and:M1 (subreg:M2 X 0) (const_int C1)) where C1
10826 fits in both M1 and M2 and the SUBREG is either paradoxical
10827 or represents the low part, permute the SUBREG and the AND
10829 if (GET_CODE (XEXP (op0, 0)) == SUBREG)
10831 unsigned HOST_WIDE_INT c1;
10832 tmode = GET_MODE (SUBREG_REG (XEXP (op0, 0)));
10833 /* Require an integral mode, to avoid creating something like
10835 if (SCALAR_INT_MODE_P (tmode)
10836 /* It is unsafe to commute the AND into the SUBREG if the
10837 SUBREG is paradoxical and WORD_REGISTER_OPERATIONS is
10838 not defined. As originally written the upper bits
10839 have a defined value due to the AND operation.
10840 However, if we commute the AND inside the SUBREG then
10841 they no longer have defined values and the meaning of
10842 the code has been changed. */
10844 #ifdef WORD_REGISTER_OPERATIONS
10845 || (mode_width > GET_MODE_BITSIZE (tmode)
10846 && mode_width <= BITS_PER_WORD)
10848 || (mode_width <= GET_MODE_BITSIZE (tmode)
10849 && subreg_lowpart_p (XEXP (op0, 0))))
10850 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10851 && mode_width <= HOST_BITS_PER_WIDE_INT
10852 && GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT
10853 && ((c1 = INTVAL (XEXP (op0, 1))) & ~mask) == 0
10854 && (c1 & ~GET_MODE_MASK (tmode)) == 0
10856 && c1 != GET_MODE_MASK (tmode))
10858 op0 = simplify_gen_binary (AND, tmode,
10859 SUBREG_REG (XEXP (op0, 0)),
10860 gen_int_mode (c1, tmode));
10861 op0 = gen_lowpart (mode, op0);
10866 /* Convert (ne (and (not X) 1) 0) to (eq (and X 1) 0). */
10867 if (const_op == 0 && equality_comparison_p
10868 && XEXP (op0, 1) == const1_rtx
10869 && GET_CODE (XEXP (op0, 0)) == NOT)
10871 op0 = simplify_and_const_int
10872 (NULL_RTX, mode, XEXP (XEXP (op0, 0), 0), (HOST_WIDE_INT) 1);
10873 code = (code == NE ? EQ : NE);
10877 /* Convert (ne (and (lshiftrt (not X)) 1) 0) to
10878 (eq (and (lshiftrt X) 1) 0).
10879 Also handle the case where (not X) is expressed using xor. */
10880 if (const_op == 0 && equality_comparison_p
10881 && XEXP (op0, 1) == const1_rtx
10882 && GET_CODE (XEXP (op0, 0)) == LSHIFTRT)
10884 rtx shift_op = XEXP (XEXP (op0, 0), 0);
10885 rtx shift_count = XEXP (XEXP (op0, 0), 1);
10887 if (GET_CODE (shift_op) == NOT
10888 || (GET_CODE (shift_op) == XOR
10889 && GET_CODE (XEXP (shift_op, 1)) == CONST_INT
10890 && GET_CODE (shift_count) == CONST_INT
10891 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
10892 && (INTVAL (XEXP (shift_op, 1))
10893 == (HOST_WIDE_INT) 1 << INTVAL (shift_count))))
10895 op0 = simplify_and_const_int
10897 gen_rtx_LSHIFTRT (mode, XEXP (shift_op, 0), shift_count),
10898 (HOST_WIDE_INT) 1);
10899 code = (code == NE ? EQ : NE);
10906 /* If we have (compare (ashift FOO N) (const_int C)) and
10907 the high order N bits of FOO (N+1 if an inequality comparison)
10908 are known to be zero, we can do this by comparing FOO with C
10909 shifted right N bits so long as the low-order N bits of C are
10911 if (GET_CODE (XEXP (op0, 1)) == CONST_INT
10912 && INTVAL (XEXP (op0, 1)) >= 0
10913 && ((INTVAL (XEXP (op0, 1)) + ! equality_comparison_p)
10914 < HOST_BITS_PER_WIDE_INT)
10916 & (((HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1))) - 1)) == 0)
10917 && mode_width <= HOST_BITS_PER_WIDE_INT
10918 && (nonzero_bits (XEXP (op0, 0), mode)
10919 & ~(mask >> (INTVAL (XEXP (op0, 1))
10920 + ! equality_comparison_p))) == 0)
10922 /* We must perform a logical shift, not an arithmetic one,
10923 as we want the top N bits of C to be zero. */
10924 unsigned HOST_WIDE_INT temp = const_op & GET_MODE_MASK (mode);
10926 temp >>= INTVAL (XEXP (op0, 1));
10927 op1 = gen_int_mode (temp, mode);
10928 op0 = XEXP (op0, 0);
10932 /* If we are doing a sign bit comparison, it means we are testing
10933 a particular bit. Convert it to the appropriate AND. */
10934 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 1)) == CONST_INT
10935 && mode_width <= HOST_BITS_PER_WIDE_INT)
10937 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
10940 - INTVAL (XEXP (op0, 1)))));
10941 code = (code == LT ? NE : EQ);
10945 /* If this an equality comparison with zero and we are shifting
10946 the low bit to the sign bit, we can convert this to an AND of the
10948 if (const_op == 0 && equality_comparison_p
10949 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10950 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (op0, 1))
10953 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
10954 (HOST_WIDE_INT) 1);
10960 /* If this is an equality comparison with zero, we can do this
10961 as a logical shift, which might be much simpler. */
10962 if (equality_comparison_p && const_op == 0
10963 && GET_CODE (XEXP (op0, 1)) == CONST_INT)
10965 op0 = simplify_shift_const (NULL_RTX, LSHIFTRT, mode,
10967 INTVAL (XEXP (op0, 1)));
10971 /* If OP0 is a sign extension and CODE is not an unsigned comparison,
10972 do the comparison in a narrower mode. */
10973 if (! unsigned_comparison_p
10974 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10975 && GET_CODE (XEXP (op0, 0)) == ASHIFT
10976 && XEXP (op0, 1) == XEXP (XEXP (op0, 0), 1)
10977 && (tmode = mode_for_size (mode_width - INTVAL (XEXP (op0, 1)),
10978 MODE_INT, 1)) != BLKmode
10979 && (((unsigned HOST_WIDE_INT) const_op
10980 + (GET_MODE_MASK (tmode) >> 1) + 1)
10981 <= GET_MODE_MASK (tmode)))
10983 op0 = gen_lowpart (tmode, XEXP (XEXP (op0, 0), 0));
10987 /* Likewise if OP0 is a PLUS of a sign extension with a
10988 constant, which is usually represented with the PLUS
10989 between the shifts. */
10990 if (! unsigned_comparison_p
10991 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10992 && GET_CODE (XEXP (op0, 0)) == PLUS
10993 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
10994 && GET_CODE (XEXP (XEXP (op0, 0), 0)) == ASHIFT
10995 && XEXP (op0, 1) == XEXP (XEXP (XEXP (op0, 0), 0), 1)
10996 && (tmode = mode_for_size (mode_width - INTVAL (XEXP (op0, 1)),
10997 MODE_INT, 1)) != BLKmode
10998 && (((unsigned HOST_WIDE_INT) const_op
10999 + (GET_MODE_MASK (tmode) >> 1) + 1)
11000 <= GET_MODE_MASK (tmode)))
11002 rtx inner = XEXP (XEXP (XEXP (op0, 0), 0), 0);
11003 rtx add_const = XEXP (XEXP (op0, 0), 1);
11004 rtx new_const = simplify_gen_binary (ASHIFTRT, GET_MODE (op0),
11005 add_const, XEXP (op0, 1));
11007 op0 = simplify_gen_binary (PLUS, tmode,
11008 gen_lowpart (tmode, inner),
11013 /* ... fall through ... */
11015 /* If we have (compare (xshiftrt FOO N) (const_int C)) and
11016 the low order N bits of FOO are known to be zero, we can do this
11017 by comparing FOO with C shifted left N bits so long as no
11018 overflow occurs. */
11019 if (GET_CODE (XEXP (op0, 1)) == CONST_INT
11020 && INTVAL (XEXP (op0, 1)) >= 0
11021 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT
11022 && mode_width <= HOST_BITS_PER_WIDE_INT
11023 && (nonzero_bits (XEXP (op0, 0), mode)
11024 & (((HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1))) - 1)) == 0
11025 && (((unsigned HOST_WIDE_INT) const_op
11026 + (GET_CODE (op0) != LSHIFTRT
11027 ? ((GET_MODE_MASK (mode) >> INTVAL (XEXP (op0, 1)) >> 1)
11030 <= GET_MODE_MASK (mode) >> INTVAL (XEXP (op0, 1))))
11032 /* If the shift was logical, then we must make the condition
11034 if (GET_CODE (op0) == LSHIFTRT)
11035 code = unsigned_condition (code);
11037 const_op <<= INTVAL (XEXP (op0, 1));
11038 op1 = GEN_INT (const_op);
11039 op0 = XEXP (op0, 0);
11043 /* If we are using this shift to extract just the sign bit, we
11044 can replace this with an LT or GE comparison. */
11046 && (equality_comparison_p || sign_bit_comparison_p)
11047 && GET_CODE (XEXP (op0, 1)) == CONST_INT
11048 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (op0, 1))
11051 op0 = XEXP (op0, 0);
11052 code = (code == NE || code == GT ? LT : GE);
11064 /* Now make any compound operations involved in this comparison. Then,
11065 check for an outmost SUBREG on OP0 that is not doing anything or is
11066 paradoxical. The latter transformation must only be performed when
11067 it is known that the "extra" bits will be the same in op0 and op1 or
11068 that they don't matter. There are three cases to consider:
11070 1. SUBREG_REG (op0) is a register. In this case the bits are don't
11071 care bits and we can assume they have any convenient value. So
11072 making the transformation is safe.
11074 2. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is not defined.
11075 In this case the upper bits of op0 are undefined. We should not make
11076 the simplification in that case as we do not know the contents of
11079 3. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is defined and not
11080 UNKNOWN. In that case we know those bits are zeros or ones. We must
11081 also be sure that they are the same as the upper bits of op1.
11083 We can never remove a SUBREG for a non-equality comparison because
11084 the sign bit is in a different place in the underlying object. */
11086 op0 = make_compound_operation (op0, op1 == const0_rtx ? COMPARE : SET);
11087 op1 = make_compound_operation (op1, SET);
11089 if (GET_CODE (op0) == SUBREG && subreg_lowpart_p (op0)
11090 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
11091 && GET_MODE_CLASS (GET_MODE (SUBREG_REG (op0))) == MODE_INT
11092 && (code == NE || code == EQ))
11094 if (GET_MODE_SIZE (GET_MODE (op0))
11095 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (op0))))
11097 /* For paradoxical subregs, allow case 1 as above. Case 3 isn't
11099 if (REG_P (SUBREG_REG (op0)))
11101 op0 = SUBREG_REG (op0);
11102 op1 = gen_lowpart (GET_MODE (op0), op1);
11105 else if ((GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0)))
11106 <= HOST_BITS_PER_WIDE_INT)
11107 && (nonzero_bits (SUBREG_REG (op0),
11108 GET_MODE (SUBREG_REG (op0)))
11109 & ~GET_MODE_MASK (GET_MODE (op0))) == 0)
11111 tem = gen_lowpart (GET_MODE (SUBREG_REG (op0)), op1);
11113 if ((nonzero_bits (tem, GET_MODE (SUBREG_REG (op0)))
11114 & ~GET_MODE_MASK (GET_MODE (op0))) == 0)
11115 op0 = SUBREG_REG (op0), op1 = tem;
11119 /* We now do the opposite procedure: Some machines don't have compare
11120 insns in all modes. If OP0's mode is an integer mode smaller than a
11121 word and we can't do a compare in that mode, see if there is a larger
11122 mode for which we can do the compare. There are a number of cases in
11123 which we can use the wider mode. */
11125 mode = GET_MODE (op0);
11126 if (mode != VOIDmode && GET_MODE_CLASS (mode) == MODE_INT
11127 && GET_MODE_SIZE (mode) < UNITS_PER_WORD
11128 && ! have_insn_for (COMPARE, mode))
11129 for (tmode = GET_MODE_WIDER_MODE (mode);
11131 && GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT);
11132 tmode = GET_MODE_WIDER_MODE (tmode))
11133 if (have_insn_for (COMPARE, tmode))
11137 /* If the only nonzero bits in OP0 and OP1 are those in the
11138 narrower mode and this is an equality or unsigned comparison,
11139 we can use the wider mode. Similarly for sign-extended
11140 values, in which case it is true for all comparisons. */
11141 zero_extended = ((code == EQ || code == NE
11142 || code == GEU || code == GTU
11143 || code == LEU || code == LTU)
11144 && (nonzero_bits (op0, tmode)
11145 & ~GET_MODE_MASK (mode)) == 0
11146 && ((GET_CODE (op1) == CONST_INT
11147 || (nonzero_bits (op1, tmode)
11148 & ~GET_MODE_MASK (mode)) == 0)));
11151 || ((num_sign_bit_copies (op0, tmode)
11152 > (unsigned int) (GET_MODE_BITSIZE (tmode)
11153 - GET_MODE_BITSIZE (mode)))
11154 && (num_sign_bit_copies (op1, tmode)
11155 > (unsigned int) (GET_MODE_BITSIZE (tmode)
11156 - GET_MODE_BITSIZE (mode)))))
11158 /* If OP0 is an AND and we don't have an AND in MODE either,
11159 make a new AND in the proper mode. */
11160 if (GET_CODE (op0) == AND
11161 && !have_insn_for (AND, mode))
11162 op0 = simplify_gen_binary (AND, tmode,
11163 gen_lowpart (tmode,
11165 gen_lowpart (tmode,
11168 op0 = gen_lowpart (tmode, op0);
11169 if (zero_extended && GET_CODE (op1) == CONST_INT)
11170 op1 = GEN_INT (INTVAL (op1) & GET_MODE_MASK (mode));
11171 op1 = gen_lowpart (tmode, op1);
11175 /* If this is a test for negative, we can make an explicit
11176 test of the sign bit. */
11178 if (op1 == const0_rtx && (code == LT || code == GE)
11179 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
11181 op0 = simplify_gen_binary (AND, tmode,
11182 gen_lowpart (tmode, op0),
11183 GEN_INT ((HOST_WIDE_INT) 1
11184 << (GET_MODE_BITSIZE (mode)
11186 code = (code == LT) ? NE : EQ;
11191 #ifdef CANONICALIZE_COMPARISON
11192 /* If this machine only supports a subset of valid comparisons, see if we
11193 can convert an unsupported one into a supported one. */
11194 CANONICALIZE_COMPARISON (code, op0, op1);
11203 /* Utility function for record_value_for_reg. Count number of
11208 enum rtx_code code = GET_CODE (x);
11212 if (GET_RTX_CLASS (code) == '2'
11213 || GET_RTX_CLASS (code) == 'c')
11215 rtx x0 = XEXP (x, 0);
11216 rtx x1 = XEXP (x, 1);
11219 return 1 + 2 * count_rtxs (x0);
11221 if ((GET_RTX_CLASS (GET_CODE (x1)) == '2'
11222 || GET_RTX_CLASS (GET_CODE (x1)) == 'c')
11223 && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1)))
11224 return 2 + 2 * count_rtxs (x0)
11225 + count_rtxs (x == XEXP (x1, 0)
11226 ? XEXP (x1, 1) : XEXP (x1, 0));
11228 if ((GET_RTX_CLASS (GET_CODE (x0)) == '2'
11229 || GET_RTX_CLASS (GET_CODE (x0)) == 'c')
11230 && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1)))
11231 return 2 + 2 * count_rtxs (x1)
11232 + count_rtxs (x == XEXP (x0, 0)
11233 ? XEXP (x0, 1) : XEXP (x0, 0));
11236 fmt = GET_RTX_FORMAT (code);
11237 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
11239 ret += count_rtxs (XEXP (x, i));
11244 /* Utility function for following routine. Called when X is part of a value
11245 being stored into last_set_value. Sets last_set_table_tick
11246 for each register mentioned. Similar to mention_regs in cse.c */
11249 update_table_tick (rtx x)
11251 enum rtx_code code = GET_CODE (x);
11252 const char *fmt = GET_RTX_FORMAT (code);
11257 unsigned int regno = REGNO (x);
11258 unsigned int endregno = END_REGNO (x);
11261 for (r = regno; r < endregno; r++)
11263 reg_stat_type *rsp = VEC_index (reg_stat_type, reg_stat, r);
11264 rsp->last_set_table_tick = label_tick;
11270 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
11271 /* Note that we can't have an "E" in values stored; see
11272 get_last_value_validate. */
11275 /* Check for identical subexpressions. If x contains
11276 identical subexpression we only have to traverse one of
11278 if (i == 0 && ARITHMETIC_P (x))
11280 /* Note that at this point x1 has already been
11282 rtx x0 = XEXP (x, 0);
11283 rtx x1 = XEXP (x, 1);
11285 /* If x0 and x1 are identical then there is no need to
11290 /* If x0 is identical to a subexpression of x1 then while
11291 processing x1, x0 has already been processed. Thus we
11292 are done with x. */
11293 if (ARITHMETIC_P (x1)
11294 && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1)))
11297 /* If x1 is identical to a subexpression of x0 then we
11298 still have to process the rest of x0. */
11299 if (ARITHMETIC_P (x0)
11300 && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1)))
11302 update_table_tick (XEXP (x0, x1 == XEXP (x0, 0) ? 1 : 0));
11307 update_table_tick (XEXP (x, i));
11311 /* Record that REG is set to VALUE in insn INSN. If VALUE is zero, we
11312 are saying that the register is clobbered and we no longer know its
11313 value. If INSN is zero, don't update reg_stat[].last_set; this is
11314 only permitted with VALUE also zero and is used to invalidate the
11318 record_value_for_reg (rtx reg, rtx insn, rtx value)
11320 unsigned int regno = REGNO (reg);
11321 unsigned int endregno = END_REGNO (reg);
11323 reg_stat_type *rsp;
11325 /* If VALUE contains REG and we have a previous value for REG, substitute
11326 the previous value. */
11327 if (value && insn && reg_overlap_mentioned_p (reg, value))
11331 /* Set things up so get_last_value is allowed to see anything set up to
11333 subst_low_luid = DF_INSN_LUID (insn);
11334 tem = get_last_value (reg);
11336 /* If TEM is simply a binary operation with two CLOBBERs as operands,
11337 it isn't going to be useful and will take a lot of time to process,
11338 so just use the CLOBBER. */
11342 if (ARITHMETIC_P (tem)
11343 && GET_CODE (XEXP (tem, 0)) == CLOBBER
11344 && GET_CODE (XEXP (tem, 1)) == CLOBBER)
11345 tem = XEXP (tem, 0);
11346 else if (count_occurrences (value, reg, 1) >= 2)
11348 /* If there are two or more occurrences of REG in VALUE,
11349 prevent the value from growing too much. */
11350 if (count_rtxs (tem) > MAX_LAST_VALUE_RTL)
11351 tem = gen_rtx_CLOBBER (GET_MODE (tem), const0_rtx);
11354 value = replace_rtx (copy_rtx (value), reg, tem);
11358 /* For each register modified, show we don't know its value, that
11359 we don't know about its bitwise content, that its value has been
11360 updated, and that we don't know the location of the death of the
11362 for (i = regno; i < endregno; i++)
11364 rsp = VEC_index (reg_stat_type, reg_stat, i);
11367 rsp->last_set = insn;
11369 rsp->last_set_value = 0;
11370 rsp->last_set_mode = 0;
11371 rsp->last_set_nonzero_bits = 0;
11372 rsp->last_set_sign_bit_copies = 0;
11373 rsp->last_death = 0;
11374 rsp->truncated_to_mode = 0;
11377 /* Mark registers that are being referenced in this value. */
11379 update_table_tick (value);
11381 /* Now update the status of each register being set.
11382 If someone is using this register in this block, set this register
11383 to invalid since we will get confused between the two lives in this
11384 basic block. This makes using this register always invalid. In cse, we
11385 scan the table to invalidate all entries using this register, but this
11386 is too much work for us. */
11388 for (i = regno; i < endregno; i++)
11390 rsp = VEC_index (reg_stat_type, reg_stat, i);
11391 rsp->last_set_label = label_tick;
11393 || (value && rsp->last_set_table_tick >= label_tick_ebb_start))
11394 rsp->last_set_invalid = 1;
11396 rsp->last_set_invalid = 0;
11399 /* The value being assigned might refer to X (like in "x++;"). In that
11400 case, we must replace it with (clobber (const_int 0)) to prevent
11402 rsp = VEC_index (reg_stat_type, reg_stat, regno);
11403 if (value && ! get_last_value_validate (&value, insn,
11404 rsp->last_set_label, 0))
11406 value = copy_rtx (value);
11407 if (! get_last_value_validate (&value, insn,
11408 rsp->last_set_label, 1))
11412 /* For the main register being modified, update the value, the mode, the
11413 nonzero bits, and the number of sign bit copies. */
11415 rsp->last_set_value = value;
11419 enum machine_mode mode = GET_MODE (reg);
11420 subst_low_luid = DF_INSN_LUID (insn);
11421 rsp->last_set_mode = mode;
11422 if (GET_MODE_CLASS (mode) == MODE_INT
11423 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
11424 mode = nonzero_bits_mode;
11425 rsp->last_set_nonzero_bits = nonzero_bits (value, mode);
11426 rsp->last_set_sign_bit_copies
11427 = num_sign_bit_copies (value, GET_MODE (reg));
11431 /* Called via note_stores from record_dead_and_set_regs to handle one
11432 SET or CLOBBER in an insn. DATA is the instruction in which the
11433 set is occurring. */
11436 record_dead_and_set_regs_1 (rtx dest, const_rtx setter, void *data)
11438 rtx record_dead_insn = (rtx) data;
11440 if (GET_CODE (dest) == SUBREG)
11441 dest = SUBREG_REG (dest);
11443 if (!record_dead_insn)
11446 record_value_for_reg (dest, NULL_RTX, NULL_RTX);
11452 /* If we are setting the whole register, we know its value. Otherwise
11453 show that we don't know the value. We can handle SUBREG in
11455 if (GET_CODE (setter) == SET && dest == SET_DEST (setter))
11456 record_value_for_reg (dest, record_dead_insn, SET_SRC (setter));
11457 else if (GET_CODE (setter) == SET
11458 && GET_CODE (SET_DEST (setter)) == SUBREG
11459 && SUBREG_REG (SET_DEST (setter)) == dest
11460 && GET_MODE_BITSIZE (GET_MODE (dest)) <= BITS_PER_WORD
11461 && subreg_lowpart_p (SET_DEST (setter)))
11462 record_value_for_reg (dest, record_dead_insn,
11463 gen_lowpart (GET_MODE (dest),
11464 SET_SRC (setter)));
11466 record_value_for_reg (dest, record_dead_insn, NULL_RTX);
11468 else if (MEM_P (dest)
11469 /* Ignore pushes, they clobber nothing. */
11470 && ! push_operand (dest, GET_MODE (dest)))
11471 mem_last_set = DF_INSN_LUID (record_dead_insn);
11474 /* Update the records of when each REG was most recently set or killed
11475 for the things done by INSN. This is the last thing done in processing
11476 INSN in the combiner loop.
11478 We update reg_stat[], in particular fields last_set, last_set_value,
11479 last_set_mode, last_set_nonzero_bits, last_set_sign_bit_copies,
11480 last_death, and also the similar information mem_last_set (which insn
11481 most recently modified memory) and last_call_luid (which insn was the
11482 most recent subroutine call). */
11485 record_dead_and_set_regs (rtx insn)
11490 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
11492 if (REG_NOTE_KIND (link) == REG_DEAD
11493 && REG_P (XEXP (link, 0)))
11495 unsigned int regno = REGNO (XEXP (link, 0));
11496 unsigned int endregno = END_REGNO (XEXP (link, 0));
11498 for (i = regno; i < endregno; i++)
11500 reg_stat_type *rsp;
11502 rsp = VEC_index (reg_stat_type, reg_stat, i);
11503 rsp->last_death = insn;
11506 else if (REG_NOTE_KIND (link) == REG_INC)
11507 record_value_for_reg (XEXP (link, 0), insn, NULL_RTX);
11512 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
11513 if (TEST_HARD_REG_BIT (regs_invalidated_by_call, i))
11515 reg_stat_type *rsp;
11517 rsp = VEC_index (reg_stat_type, reg_stat, i);
11518 rsp->last_set_invalid = 1;
11519 rsp->last_set = insn;
11520 rsp->last_set_value = 0;
11521 rsp->last_set_mode = 0;
11522 rsp->last_set_nonzero_bits = 0;
11523 rsp->last_set_sign_bit_copies = 0;
11524 rsp->last_death = 0;
11525 rsp->truncated_to_mode = 0;
11528 last_call_luid = mem_last_set = DF_INSN_LUID (insn);
11530 /* We can't combine into a call pattern. Remember, though, that
11531 the return value register is set at this LUID. We could
11532 still replace a register with the return value from the
11533 wrong subroutine call! */
11534 note_stores (PATTERN (insn), record_dead_and_set_regs_1, NULL_RTX);
11537 note_stores (PATTERN (insn), record_dead_and_set_regs_1, insn);
11540 /* If a SUBREG has the promoted bit set, it is in fact a property of the
11541 register present in the SUBREG, so for each such SUBREG go back and
11542 adjust nonzero and sign bit information of the registers that are
11543 known to have some zero/sign bits set.
11545 This is needed because when combine blows the SUBREGs away, the
11546 information on zero/sign bits is lost and further combines can be
11547 missed because of that. */
11550 record_promoted_value (rtx insn, rtx subreg)
11553 unsigned int regno = REGNO (SUBREG_REG (subreg));
11554 enum machine_mode mode = GET_MODE (subreg);
11556 if (GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT)
11559 for (links = LOG_LINKS (insn); links;)
11561 reg_stat_type *rsp;
11563 insn = XEXP (links, 0);
11564 set = single_set (insn);
11566 if (! set || !REG_P (SET_DEST (set))
11567 || REGNO (SET_DEST (set)) != regno
11568 || GET_MODE (SET_DEST (set)) != GET_MODE (SUBREG_REG (subreg)))
11570 links = XEXP (links, 1);
11574 rsp = VEC_index (reg_stat_type, reg_stat, regno);
11575 if (rsp->last_set == insn)
11577 if (SUBREG_PROMOTED_UNSIGNED_P (subreg) > 0)
11578 rsp->last_set_nonzero_bits &= GET_MODE_MASK (mode);
11581 if (REG_P (SET_SRC (set)))
11583 regno = REGNO (SET_SRC (set));
11584 links = LOG_LINKS (insn);
11591 /* Check if X, a register, is known to contain a value already
11592 truncated to MODE. In this case we can use a subreg to refer to
11593 the truncated value even though in the generic case we would need
11594 an explicit truncation. */
11597 reg_truncated_to_mode (enum machine_mode mode, const_rtx x)
11599 reg_stat_type *rsp = VEC_index (reg_stat_type, reg_stat, REGNO (x));
11600 enum machine_mode truncated = rsp->truncated_to_mode;
11603 || rsp->truncation_label < label_tick_ebb_start)
11605 if (GET_MODE_SIZE (truncated) <= GET_MODE_SIZE (mode))
11607 if (TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode),
11608 GET_MODE_BITSIZE (truncated)))
11613 /* X is a REG or a SUBREG. If X is some sort of a truncation record
11614 it. For non-TRULY_NOOP_TRUNCATION targets we might be able to turn
11615 a truncate into a subreg using this information. */
11618 record_truncated_value (rtx x)
11620 enum machine_mode truncated_mode;
11621 reg_stat_type *rsp;
11623 if (GET_CODE (x) == SUBREG && REG_P (SUBREG_REG (x)))
11625 enum machine_mode original_mode = GET_MODE (SUBREG_REG (x));
11626 truncated_mode = GET_MODE (x);
11628 if (GET_MODE_SIZE (original_mode) <= GET_MODE_SIZE (truncated_mode))
11631 if (TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (truncated_mode),
11632 GET_MODE_BITSIZE (original_mode)))
11635 x = SUBREG_REG (x);
11637 /* ??? For hard-regs we now record everything. We might be able to
11638 optimize this using last_set_mode. */
11639 else if (REG_P (x) && REGNO (x) < FIRST_PSEUDO_REGISTER)
11640 truncated_mode = GET_MODE (x);
11644 rsp = VEC_index (reg_stat_type, reg_stat, REGNO (x));
11645 if (rsp->truncated_to_mode == 0
11646 || rsp->truncation_label < label_tick_ebb_start
11647 || (GET_MODE_SIZE (truncated_mode)
11648 < GET_MODE_SIZE (rsp->truncated_to_mode)))
11650 rsp->truncated_to_mode = truncated_mode;
11651 rsp->truncation_label = label_tick;
11655 /* Scan X for promoted SUBREGs and truncated REGs. For each one
11656 found, note what it implies to the registers used in it. */
11659 check_conversions (rtx insn, rtx x)
11661 if (GET_CODE (x) == SUBREG || REG_P (x))
11663 if (GET_CODE (x) == SUBREG
11664 && SUBREG_PROMOTED_VAR_P (x)
11665 && REG_P (SUBREG_REG (x)))
11666 record_promoted_value (insn, x);
11668 record_truncated_value (x);
11672 const char *format = GET_RTX_FORMAT (GET_CODE (x));
11675 for (i = 0; i < GET_RTX_LENGTH (GET_CODE (x)); i++)
11679 check_conversions (insn, XEXP (x, i));
11683 if (XVEC (x, i) != 0)
11684 for (j = 0; j < XVECLEN (x, i); j++)
11685 check_conversions (insn, XVECEXP (x, i, j));
11691 /* Utility routine for the following function. Verify that all the registers
11692 mentioned in *LOC are valid when *LOC was part of a value set when
11693 label_tick == TICK. Return 0 if some are not.
11695 If REPLACE is nonzero, replace the invalid reference with
11696 (clobber (const_int 0)) and return 1. This replacement is useful because
11697 we often can get useful information about the form of a value (e.g., if
11698 it was produced by a shift that always produces -1 or 0) even though
11699 we don't know exactly what registers it was produced from. */
11702 get_last_value_validate (rtx *loc, rtx insn, int tick, int replace)
11705 const char *fmt = GET_RTX_FORMAT (GET_CODE (x));
11706 int len = GET_RTX_LENGTH (GET_CODE (x));
11711 unsigned int regno = REGNO (x);
11712 unsigned int endregno = END_REGNO (x);
11715 for (j = regno; j < endregno; j++)
11717 reg_stat_type *rsp = VEC_index (reg_stat_type, reg_stat, j);
11718 if (rsp->last_set_invalid
11719 /* If this is a pseudo-register that was only set once and not
11720 live at the beginning of the function, it is always valid. */
11721 || (! (regno >= FIRST_PSEUDO_REGISTER
11722 && REG_N_SETS (regno) == 1
11723 && (!REGNO_REG_SET_P
11724 (DF_LR_IN (ENTRY_BLOCK_PTR->next_bb), regno)))
11725 && rsp->last_set_label > tick))
11728 *loc = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
11735 /* If this is a memory reference, make sure that there were
11736 no stores after it that might have clobbered the value. We don't
11737 have alias info, so we assume any store invalidates it. */
11738 else if (MEM_P (x) && !MEM_READONLY_P (x)
11739 && DF_INSN_LUID (insn) <= mem_last_set)
11742 *loc = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
11746 for (i = 0; i < len; i++)
11750 /* Check for identical subexpressions. If x contains
11751 identical subexpression we only have to traverse one of
11753 if (i == 1 && ARITHMETIC_P (x))
11755 /* Note that at this point x0 has already been checked
11756 and found valid. */
11757 rtx x0 = XEXP (x, 0);
11758 rtx x1 = XEXP (x, 1);
11760 /* If x0 and x1 are identical then x is also valid. */
11764 /* If x1 is identical to a subexpression of x0 then
11765 while checking x0, x1 has already been checked. Thus
11766 it is valid and so as x. */
11767 if (ARITHMETIC_P (x0)
11768 && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1)))
11771 /* If x0 is identical to a subexpression of x1 then x is
11772 valid iff the rest of x1 is valid. */
11773 if (ARITHMETIC_P (x1)
11774 && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1)))
11776 get_last_value_validate (&XEXP (x1,
11777 x0 == XEXP (x1, 0) ? 1 : 0),
11778 insn, tick, replace);
11781 if (get_last_value_validate (&XEXP (x, i), insn, tick,
11785 /* Don't bother with these. They shouldn't occur anyway. */
11786 else if (fmt[i] == 'E')
11790 /* If we haven't found a reason for it to be invalid, it is valid. */
11794 /* Get the last value assigned to X, if known. Some registers
11795 in the value may be replaced with (clobber (const_int 0)) if their value
11796 is known longer known reliably. */
11799 get_last_value (const_rtx x)
11801 unsigned int regno;
11803 reg_stat_type *rsp;
11805 /* If this is a non-paradoxical SUBREG, get the value of its operand and
11806 then convert it to the desired mode. If this is a paradoxical SUBREG,
11807 we cannot predict what values the "extra" bits might have. */
11808 if (GET_CODE (x) == SUBREG
11809 && subreg_lowpart_p (x)
11810 && (GET_MODE_SIZE (GET_MODE (x))
11811 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
11812 && (value = get_last_value (SUBREG_REG (x))) != 0)
11813 return gen_lowpart (GET_MODE (x), value);
11819 rsp = VEC_index (reg_stat_type, reg_stat, regno);
11820 value = rsp->last_set_value;
11822 /* If we don't have a value, or if it isn't for this basic block and
11823 it's either a hard register, set more than once, or it's a live
11824 at the beginning of the function, return 0.
11826 Because if it's not live at the beginning of the function then the reg
11827 is always set before being used (is never used without being set).
11828 And, if it's set only once, and it's always set before use, then all
11829 uses must have the same last value, even if it's not from this basic
11833 || (rsp->last_set_label < label_tick_ebb_start
11834 && (regno < FIRST_PSEUDO_REGISTER
11835 || REG_N_SETS (regno) != 1
11837 (DF_LR_IN (ENTRY_BLOCK_PTR->next_bb), regno))))
11840 /* If the value was set in a later insn than the ones we are processing,
11841 we can't use it even if the register was only set once. */
11842 if (rsp->last_set_label == label_tick
11843 && DF_INSN_LUID (rsp->last_set) >= subst_low_luid)
11846 /* If the value has all its registers valid, return it. */
11847 if (get_last_value_validate (&value, rsp->last_set,
11848 rsp->last_set_label, 0))
11851 /* Otherwise, make a copy and replace any invalid register with
11852 (clobber (const_int 0)). If that fails for some reason, return 0. */
11854 value = copy_rtx (value);
11855 if (get_last_value_validate (&value, rsp->last_set,
11856 rsp->last_set_label, 1))
11862 /* Return nonzero if expression X refers to a REG or to memory
11863 that is set in an instruction more recent than FROM_LUID. */
11866 use_crosses_set_p (const_rtx x, int from_luid)
11870 enum rtx_code code = GET_CODE (x);
11874 unsigned int regno = REGNO (x);
11875 unsigned endreg = END_REGNO (x);
11877 #ifdef PUSH_ROUNDING
11878 /* Don't allow uses of the stack pointer to be moved,
11879 because we don't know whether the move crosses a push insn. */
11880 if (regno == STACK_POINTER_REGNUM && PUSH_ARGS)
11883 for (; regno < endreg; regno++)
11885 reg_stat_type *rsp = VEC_index (reg_stat_type, reg_stat, regno);
11887 && rsp->last_set_label == label_tick
11888 && DF_INSN_LUID (rsp->last_set) > from_luid)
11894 if (code == MEM && mem_last_set > from_luid)
11897 fmt = GET_RTX_FORMAT (code);
11899 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
11904 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
11905 if (use_crosses_set_p (XVECEXP (x, i, j), from_luid))
11908 else if (fmt[i] == 'e'
11909 && use_crosses_set_p (XEXP (x, i), from_luid))
11915 /* Define three variables used for communication between the following
11918 static unsigned int reg_dead_regno, reg_dead_endregno;
11919 static int reg_dead_flag;
11921 /* Function called via note_stores from reg_dead_at_p.
11923 If DEST is within [reg_dead_regno, reg_dead_endregno), set
11924 reg_dead_flag to 1 if X is a CLOBBER and to -1 it is a SET. */
11927 reg_dead_at_p_1 (rtx dest, const_rtx x, void *data ATTRIBUTE_UNUSED)
11929 unsigned int regno, endregno;
11934 regno = REGNO (dest);
11935 endregno = END_REGNO (dest);
11936 if (reg_dead_endregno > regno && reg_dead_regno < endregno)
11937 reg_dead_flag = (GET_CODE (x) == CLOBBER) ? 1 : -1;
11940 /* Return nonzero if REG is known to be dead at INSN.
11942 We scan backwards from INSN. If we hit a REG_DEAD note or a CLOBBER
11943 referencing REG, it is dead. If we hit a SET referencing REG, it is
11944 live. Otherwise, see if it is live or dead at the start of the basic
11945 block we are in. Hard regs marked as being live in NEWPAT_USED_REGS
11946 must be assumed to be always live. */
11949 reg_dead_at_p (rtx reg, rtx insn)
11954 /* Set variables for reg_dead_at_p_1. */
11955 reg_dead_regno = REGNO (reg);
11956 reg_dead_endregno = END_REGNO (reg);
11960 /* Check that reg isn't mentioned in NEWPAT_USED_REGS. For fixed registers
11961 we allow the machine description to decide whether use-and-clobber
11962 patterns are OK. */
11963 if (reg_dead_regno < FIRST_PSEUDO_REGISTER)
11965 for (i = reg_dead_regno; i < reg_dead_endregno; i++)
11966 if (!fixed_regs[i] && TEST_HARD_REG_BIT (newpat_used_regs, i))
11970 /* Scan backwards until we find a REG_DEAD note, SET, CLOBBER, label, or
11971 beginning of function. */
11972 for (; insn && !LABEL_P (insn) && !BARRIER_P (insn);
11973 insn = prev_nonnote_insn (insn))
11975 note_stores (PATTERN (insn), reg_dead_at_p_1, NULL);
11977 return reg_dead_flag == 1 ? 1 : 0;
11979 if (find_regno_note (insn, REG_DEAD, reg_dead_regno))
11983 /* Get the basic block that we were in. */
11985 block = ENTRY_BLOCK_PTR->next_bb;
11988 FOR_EACH_BB (block)
11989 if (insn == BB_HEAD (block))
11992 if (block == EXIT_BLOCK_PTR)
11996 for (i = reg_dead_regno; i < reg_dead_endregno; i++)
11997 if (REGNO_REG_SET_P (df_get_live_in (block), i))
12003 /* Note hard registers in X that are used. */
12006 mark_used_regs_combine (rtx x)
12008 RTX_CODE code = GET_CODE (x);
12009 unsigned int regno;
12022 case ADDR_DIFF_VEC:
12025 /* CC0 must die in the insn after it is set, so we don't need to take
12026 special note of it here. */
12032 /* If we are clobbering a MEM, mark any hard registers inside the
12033 address as used. */
12034 if (MEM_P (XEXP (x, 0)))
12035 mark_used_regs_combine (XEXP (XEXP (x, 0), 0));
12040 /* A hard reg in a wide mode may really be multiple registers.
12041 If so, mark all of them just like the first. */
12042 if (regno < FIRST_PSEUDO_REGISTER)
12044 /* None of this applies to the stack, frame or arg pointers. */
12045 if (regno == STACK_POINTER_REGNUM
12046 #if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM
12047 || regno == HARD_FRAME_POINTER_REGNUM
12049 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
12050 || (regno == ARG_POINTER_REGNUM && fixed_regs[regno])
12052 || regno == FRAME_POINTER_REGNUM)
12055 add_to_hard_reg_set (&newpat_used_regs, GET_MODE (x), regno);
12061 /* If setting a MEM, or a SUBREG of a MEM, then note any hard regs in
12063 rtx testreg = SET_DEST (x);
12065 while (GET_CODE (testreg) == SUBREG
12066 || GET_CODE (testreg) == ZERO_EXTRACT
12067 || GET_CODE (testreg) == STRICT_LOW_PART)
12068 testreg = XEXP (testreg, 0);
12070 if (MEM_P (testreg))
12071 mark_used_regs_combine (XEXP (testreg, 0));
12073 mark_used_regs_combine (SET_SRC (x));
12081 /* Recursively scan the operands of this expression. */
12084 const char *fmt = GET_RTX_FORMAT (code);
12086 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
12089 mark_used_regs_combine (XEXP (x, i));
12090 else if (fmt[i] == 'E')
12094 for (j = 0; j < XVECLEN (x, i); j++)
12095 mark_used_regs_combine (XVECEXP (x, i, j));
12101 /* Remove register number REGNO from the dead registers list of INSN.
12103 Return the note used to record the death, if there was one. */
12106 remove_death (unsigned int regno, rtx insn)
12108 rtx note = find_regno_note (insn, REG_DEAD, regno);
12111 remove_note (insn, note);
12116 /* For each register (hardware or pseudo) used within expression X, if its
12117 death is in an instruction with luid between FROM_LUID (inclusive) and
12118 TO_INSN (exclusive), put a REG_DEAD note for that register in the
12119 list headed by PNOTES.
12121 That said, don't move registers killed by maybe_kill_insn.
12123 This is done when X is being merged by combination into TO_INSN. These
12124 notes will then be distributed as needed. */
12127 move_deaths (rtx x, rtx maybe_kill_insn, int from_luid, rtx to_insn,
12132 enum rtx_code code = GET_CODE (x);
12136 unsigned int regno = REGNO (x);
12137 rtx where_dead = VEC_index (reg_stat_type, reg_stat, regno)->last_death;
12139 /* Don't move the register if it gets killed in between from and to. */
12140 if (maybe_kill_insn && reg_set_p (x, maybe_kill_insn)
12141 && ! reg_referenced_p (x, maybe_kill_insn))
12145 && DF_INSN_LUID (where_dead) >= from_luid
12146 && DF_INSN_LUID (where_dead) < DF_INSN_LUID (to_insn))
12148 rtx note = remove_death (regno, where_dead);
12150 /* It is possible for the call above to return 0. This can occur
12151 when last_death points to I2 or I1 that we combined with.
12152 In that case make a new note.
12154 We must also check for the case where X is a hard register
12155 and NOTE is a death note for a range of hard registers
12156 including X. In that case, we must put REG_DEAD notes for
12157 the remaining registers in place of NOTE. */
12159 if (note != 0 && regno < FIRST_PSEUDO_REGISTER
12160 && (GET_MODE_SIZE (GET_MODE (XEXP (note, 0)))
12161 > GET_MODE_SIZE (GET_MODE (x))))
12163 unsigned int deadregno = REGNO (XEXP (note, 0));
12164 unsigned int deadend = END_HARD_REGNO (XEXP (note, 0));
12165 unsigned int ourend = END_HARD_REGNO (x);
12168 for (i = deadregno; i < deadend; i++)
12169 if (i < regno || i >= ourend)
12170 REG_NOTES (where_dead)
12171 = gen_rtx_EXPR_LIST (REG_DEAD,
12173 REG_NOTES (where_dead));
12176 /* If we didn't find any note, or if we found a REG_DEAD note that
12177 covers only part of the given reg, and we have a multi-reg hard
12178 register, then to be safe we must check for REG_DEAD notes
12179 for each register other than the first. They could have
12180 their own REG_DEAD notes lying around. */
12181 else if ((note == 0
12183 && (GET_MODE_SIZE (GET_MODE (XEXP (note, 0)))
12184 < GET_MODE_SIZE (GET_MODE (x)))))
12185 && regno < FIRST_PSEUDO_REGISTER
12186 && hard_regno_nregs[regno][GET_MODE (x)] > 1)
12188 unsigned int ourend = END_HARD_REGNO (x);
12189 unsigned int i, offset;
12193 offset = hard_regno_nregs[regno][GET_MODE (XEXP (note, 0))];
12197 for (i = regno + offset; i < ourend; i++)
12198 move_deaths (regno_reg_rtx[i],
12199 maybe_kill_insn, from_luid, to_insn, &oldnotes);
12202 if (note != 0 && GET_MODE (XEXP (note, 0)) == GET_MODE (x))
12204 XEXP (note, 1) = *pnotes;
12208 *pnotes = gen_rtx_EXPR_LIST (REG_DEAD, x, *pnotes);
12214 else if (GET_CODE (x) == SET)
12216 rtx dest = SET_DEST (x);
12218 move_deaths (SET_SRC (x), maybe_kill_insn, from_luid, to_insn, pnotes);
12220 /* In the case of a ZERO_EXTRACT, a STRICT_LOW_PART, or a SUBREG
12221 that accesses one word of a multi-word item, some
12222 piece of everything register in the expression is used by
12223 this insn, so remove any old death. */
12224 /* ??? So why do we test for equality of the sizes? */
12226 if (GET_CODE (dest) == ZERO_EXTRACT
12227 || GET_CODE (dest) == STRICT_LOW_PART
12228 || (GET_CODE (dest) == SUBREG
12229 && (((GET_MODE_SIZE (GET_MODE (dest))
12230 + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
12231 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (dest)))
12232 + UNITS_PER_WORD - 1) / UNITS_PER_WORD))))
12234 move_deaths (dest, maybe_kill_insn, from_luid, to_insn, pnotes);
12238 /* If this is some other SUBREG, we know it replaces the entire
12239 value, so use that as the destination. */
12240 if (GET_CODE (dest) == SUBREG)
12241 dest = SUBREG_REG (dest);
12243 /* If this is a MEM, adjust deaths of anything used in the address.
12244 For a REG (the only other possibility), the entire value is
12245 being replaced so the old value is not used in this insn. */
12248 move_deaths (XEXP (dest, 0), maybe_kill_insn, from_luid,
12253 else if (GET_CODE (x) == CLOBBER)
12256 len = GET_RTX_LENGTH (code);
12257 fmt = GET_RTX_FORMAT (code);
12259 for (i = 0; i < len; i++)
12264 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
12265 move_deaths (XVECEXP (x, i, j), maybe_kill_insn, from_luid,
12268 else if (fmt[i] == 'e')
12269 move_deaths (XEXP (x, i), maybe_kill_insn, from_luid, to_insn, pnotes);
12273 /* Return 1 if X is the target of a bit-field assignment in BODY, the
12274 pattern of an insn. X must be a REG. */
12277 reg_bitfield_target_p (rtx x, rtx body)
12281 if (GET_CODE (body) == SET)
12283 rtx dest = SET_DEST (body);
12285 unsigned int regno, tregno, endregno, endtregno;
12287 if (GET_CODE (dest) == ZERO_EXTRACT)
12288 target = XEXP (dest, 0);
12289 else if (GET_CODE (dest) == STRICT_LOW_PART)
12290 target = SUBREG_REG (XEXP (dest, 0));
12294 if (GET_CODE (target) == SUBREG)
12295 target = SUBREG_REG (target);
12297 if (!REG_P (target))
12300 tregno = REGNO (target), regno = REGNO (x);
12301 if (tregno >= FIRST_PSEUDO_REGISTER || regno >= FIRST_PSEUDO_REGISTER)
12302 return target == x;
12304 endtregno = end_hard_regno (GET_MODE (target), tregno);
12305 endregno = end_hard_regno (GET_MODE (x), regno);
12307 return endregno > tregno && regno < endtregno;
12310 else if (GET_CODE (body) == PARALLEL)
12311 for (i = XVECLEN (body, 0) - 1; i >= 0; i--)
12312 if (reg_bitfield_target_p (x, XVECEXP (body, 0, i)))
12318 /* Given a chain of REG_NOTES originally from FROM_INSN, try to place them
12319 as appropriate. I3 and I2 are the insns resulting from the combination
12320 insns including FROM (I2 may be zero).
12322 ELIM_I2 and ELIM_I1 are either zero or registers that we know will
12323 not need REG_DEAD notes because they are being substituted for. This
12324 saves searching in the most common cases.
12326 Each note in the list is either ignored or placed on some insns, depending
12327 on the type of note. */
12330 distribute_notes (rtx notes, rtx from_insn, rtx i3, rtx i2, rtx elim_i2,
12333 rtx note, next_note;
12336 for (note = notes; note; note = next_note)
12338 rtx place = 0, place2 = 0;
12340 next_note = XEXP (note, 1);
12341 switch (REG_NOTE_KIND (note))
12345 /* Doesn't matter much where we put this, as long as it's somewhere.
12346 It is preferable to keep these notes on branches, which is most
12347 likely to be i3. */
12351 case REG_VALUE_PROFILE:
12352 /* Just get rid of this note, as it is unused later anyway. */
12355 case REG_NON_LOCAL_GOTO:
12360 gcc_assert (i2 && JUMP_P (i2));
12365 case REG_EH_REGION:
12366 /* These notes must remain with the call or trapping instruction. */
12369 else if (i2 && CALL_P (i2))
12373 gcc_assert (flag_non_call_exceptions);
12374 if (may_trap_p (i3))
12376 else if (i2 && may_trap_p (i2))
12378 /* ??? Otherwise assume we've combined things such that we
12379 can now prove that the instructions can't trap. Drop the
12380 note in this case. */
12386 /* These notes must remain with the call. It should not be
12387 possible for both I2 and I3 to be a call. */
12392 gcc_assert (i2 && CALL_P (i2));
12398 /* Any clobbers for i3 may still exist, and so we must process
12399 REG_UNUSED notes from that insn.
12401 Any clobbers from i2 or i1 can only exist if they were added by
12402 recog_for_combine. In that case, recog_for_combine created the
12403 necessary REG_UNUSED notes. Trying to keep any original
12404 REG_UNUSED notes from these insns can cause incorrect output
12405 if it is for the same register as the original i3 dest.
12406 In that case, we will notice that the register is set in i3,
12407 and then add a REG_UNUSED note for the destination of i3, which
12408 is wrong. However, it is possible to have REG_UNUSED notes from
12409 i2 or i1 for register which were both used and clobbered, so
12410 we keep notes from i2 or i1 if they will turn into REG_DEAD
12413 /* If this register is set or clobbered in I3, put the note there
12414 unless there is one already. */
12415 if (reg_set_p (XEXP (note, 0), PATTERN (i3)))
12417 if (from_insn != i3)
12420 if (! (REG_P (XEXP (note, 0))
12421 ? find_regno_note (i3, REG_UNUSED, REGNO (XEXP (note, 0)))
12422 : find_reg_note (i3, REG_UNUSED, XEXP (note, 0))))
12425 /* Otherwise, if this register is used by I3, then this register
12426 now dies here, so we must put a REG_DEAD note here unless there
12428 else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3))
12429 && ! (REG_P (XEXP (note, 0))
12430 ? find_regno_note (i3, REG_DEAD,
12431 REGNO (XEXP (note, 0)))
12432 : find_reg_note (i3, REG_DEAD, XEXP (note, 0))))
12434 PUT_REG_NOTE_KIND (note, REG_DEAD);
12442 /* These notes say something about results of an insn. We can
12443 only support them if they used to be on I3 in which case they
12444 remain on I3. Otherwise they are ignored.
12446 If the note refers to an expression that is not a constant, we
12447 must also ignore the note since we cannot tell whether the
12448 equivalence is still true. It might be possible to do
12449 slightly better than this (we only have a problem if I2DEST
12450 or I1DEST is present in the expression), but it doesn't
12451 seem worth the trouble. */
12453 if (from_insn == i3
12454 && (XEXP (note, 0) == 0 || CONSTANT_P (XEXP (note, 0))))
12459 /* These notes say something about how a register is used. They must
12460 be present on any use of the register in I2 or I3. */
12461 if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3)))
12464 if (i2 && reg_mentioned_p (XEXP (note, 0), PATTERN (i2)))
12473 case REG_LABEL_TARGET:
12474 case REG_LABEL_OPERAND:
12475 /* This can show up in several ways -- either directly in the
12476 pattern, or hidden off in the constant pool with (or without?)
12477 a REG_EQUAL note. */
12478 /* ??? Ignore the without-reg_equal-note problem for now. */
12479 if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3))
12480 || ((tem = find_reg_note (i3, REG_EQUAL, NULL_RTX))
12481 && GET_CODE (XEXP (tem, 0)) == LABEL_REF
12482 && XEXP (XEXP (tem, 0), 0) == XEXP (note, 0)))
12486 && (reg_mentioned_p (XEXP (note, 0), PATTERN (i2))
12487 || ((tem = find_reg_note (i2, REG_EQUAL, NULL_RTX))
12488 && GET_CODE (XEXP (tem, 0)) == LABEL_REF
12489 && XEXP (XEXP (tem, 0), 0) == XEXP (note, 0))))
12497 /* For REG_LABEL_TARGET on a JUMP_P, we prefer to put the note
12498 as a JUMP_LABEL or decrement LABEL_NUSES if it's already
12500 if (place && JUMP_P (place)
12501 && REG_NOTE_KIND (note) == REG_LABEL_TARGET
12502 && (JUMP_LABEL (place) == NULL
12503 || JUMP_LABEL (place) == XEXP (note, 0)))
12505 rtx label = JUMP_LABEL (place);
12508 JUMP_LABEL (place) = XEXP (note, 0);
12509 else if (LABEL_P (label))
12510 LABEL_NUSES (label)--;
12513 if (place2 && JUMP_P (place2)
12514 && REG_NOTE_KIND (note) == REG_LABEL_TARGET
12515 && (JUMP_LABEL (place2) == NULL
12516 || JUMP_LABEL (place2) == XEXP (note, 0)))
12518 rtx label = JUMP_LABEL (place2);
12521 JUMP_LABEL (place2) = XEXP (note, 0);
12522 else if (LABEL_P (label))
12523 LABEL_NUSES (label)--;
12529 /* This note says something about the value of a register prior
12530 to the execution of an insn. It is too much trouble to see
12531 if the note is still correct in all situations. It is better
12532 to simply delete it. */
12536 /* If the insn previously containing this note still exists,
12537 put it back where it was. Otherwise move it to the previous
12538 insn. Adjust the corresponding REG_LIBCALL note. */
12539 if (!NOTE_P (from_insn))
12543 tem = find_reg_note (XEXP (note, 0), REG_LIBCALL, NULL_RTX);
12544 place = prev_real_insn (from_insn);
12546 XEXP (tem, 0) = place;
12547 /* If we're deleting the last remaining instruction of a
12548 libcall sequence, don't add the notes. */
12549 else if (XEXP (note, 0) == from_insn)
12551 /* Don't add the dangling REG_RETVAL note. */
12558 /* This is handled similarly to REG_RETVAL. */
12559 if (!NOTE_P (from_insn))
12563 tem = find_reg_note (XEXP (note, 0), REG_RETVAL, NULL_RTX);
12564 place = next_real_insn (from_insn);
12566 XEXP (tem, 0) = place;
12567 /* If we're deleting the last remaining instruction of a
12568 libcall sequence, don't add the notes. */
12569 else if (XEXP (note, 0) == from_insn)
12571 /* Don't add the dangling REG_LIBCALL note. */
12578 /* If we replaced the right hand side of FROM_INSN with a
12579 REG_EQUAL note, the original use of the dying register
12580 will not have been combined into I3 and I2. In such cases,
12581 FROM_INSN is guaranteed to be the first of the combined
12582 instructions, so we simply need to search back before
12583 FROM_INSN for the previous use or set of this register,
12584 then alter the notes there appropriately.
12586 If the register is used as an input in I3, it dies there.
12587 Similarly for I2, if it is nonzero and adjacent to I3.
12589 If the register is not used as an input in either I3 or I2
12590 and it is not one of the registers we were supposed to eliminate,
12591 there are two possibilities. We might have a non-adjacent I2
12592 or we might have somehow eliminated an additional register
12593 from a computation. For example, we might have had A & B where
12594 we discover that B will always be zero. In this case we will
12595 eliminate the reference to A.
12597 In both cases, we must search to see if we can find a previous
12598 use of A and put the death note there. */
12601 && from_insn == i2mod
12602 && !reg_overlap_mentioned_p (XEXP (note, 0), i2mod_new_rhs))
12607 && CALL_P (from_insn)
12608 && find_reg_fusage (from_insn, USE, XEXP (note, 0)))
12610 else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3)))
12612 else if (i2 != 0 && next_nonnote_insn (i2) == i3
12613 && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
12615 else if ((rtx_equal_p (XEXP (note, 0), elim_i2)
12617 && reg_overlap_mentioned_p (XEXP (note, 0),
12619 || rtx_equal_p (XEXP (note, 0), elim_i1))
12626 basic_block bb = this_basic_block;
12628 for (tem = PREV_INSN (tem); place == 0; tem = PREV_INSN (tem))
12630 if (! INSN_P (tem))
12632 if (tem == BB_HEAD (bb))
12637 /* If the register is being set at TEM, see if that is all
12638 TEM is doing. If so, delete TEM. Otherwise, make this
12639 into a REG_UNUSED note instead. Don't delete sets to
12640 global register vars. */
12641 if ((REGNO (XEXP (note, 0)) >= FIRST_PSEUDO_REGISTER
12642 || !global_regs[REGNO (XEXP (note, 0))])
12643 && reg_set_p (XEXP (note, 0), PATTERN (tem)))
12645 rtx set = single_set (tem);
12646 rtx inner_dest = 0;
12648 rtx cc0_setter = NULL_RTX;
12652 for (inner_dest = SET_DEST (set);
12653 (GET_CODE (inner_dest) == STRICT_LOW_PART
12654 || GET_CODE (inner_dest) == SUBREG
12655 || GET_CODE (inner_dest) == ZERO_EXTRACT);
12656 inner_dest = XEXP (inner_dest, 0))
12659 /* Verify that it was the set, and not a clobber that
12660 modified the register.
12662 CC0 targets must be careful to maintain setter/user
12663 pairs. If we cannot delete the setter due to side
12664 effects, mark the user with an UNUSED note instead
12667 if (set != 0 && ! side_effects_p (SET_SRC (set))
12668 && rtx_equal_p (XEXP (note, 0), inner_dest)
12670 && (! reg_mentioned_p (cc0_rtx, SET_SRC (set))
12671 || ((cc0_setter = prev_cc0_setter (tem)) != NULL
12672 && sets_cc0_p (PATTERN (cc0_setter)) > 0))
12676 /* Move the notes and links of TEM elsewhere.
12677 This might delete other dead insns recursively.
12678 First set the pattern to something that won't use
12680 rtx old_notes = REG_NOTES (tem);
12682 PATTERN (tem) = pc_rtx;
12683 REG_NOTES (tem) = NULL;
12685 distribute_notes (old_notes, tem, tem, NULL_RTX,
12686 NULL_RTX, NULL_RTX);
12687 distribute_links (LOG_LINKS (tem));
12689 SET_INSN_DELETED (tem);
12692 /* Delete the setter too. */
12695 PATTERN (cc0_setter) = pc_rtx;
12696 old_notes = REG_NOTES (cc0_setter);
12697 REG_NOTES (cc0_setter) = NULL;
12699 distribute_notes (old_notes, cc0_setter,
12700 cc0_setter, NULL_RTX,
12701 NULL_RTX, NULL_RTX);
12702 distribute_links (LOG_LINKS (cc0_setter));
12704 SET_INSN_DELETED (cc0_setter);
12710 PUT_REG_NOTE_KIND (note, REG_UNUSED);
12712 /* If there isn't already a REG_UNUSED note, put one
12713 here. Do not place a REG_DEAD note, even if
12714 the register is also used here; that would not
12715 match the algorithm used in lifetime analysis
12716 and can cause the consistency check in the
12717 scheduler to fail. */
12718 if (! find_regno_note (tem, REG_UNUSED,
12719 REGNO (XEXP (note, 0))))
12724 else if (reg_referenced_p (XEXP (note, 0), PATTERN (tem))
12726 && find_reg_fusage (tem, USE, XEXP (note, 0))))
12730 /* If we are doing a 3->2 combination, and we have a
12731 register which formerly died in i3 and was not used
12732 by i2, which now no longer dies in i3 and is used in
12733 i2 but does not die in i2, and place is between i2
12734 and i3, then we may need to move a link from place to
12736 if (i2 && DF_INSN_LUID (place) > DF_INSN_LUID (i2)
12738 && DF_INSN_LUID (from_insn) > DF_INSN_LUID (i2)
12739 && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
12741 rtx links = LOG_LINKS (place);
12742 LOG_LINKS (place) = 0;
12743 distribute_links (links);
12748 if (tem == BB_HEAD (bb))
12754 /* If the register is set or already dead at PLACE, we needn't do
12755 anything with this note if it is still a REG_DEAD note.
12756 We check here if it is set at all, not if is it totally replaced,
12757 which is what `dead_or_set_p' checks, so also check for it being
12760 if (place && REG_NOTE_KIND (note) == REG_DEAD)
12762 unsigned int regno = REGNO (XEXP (note, 0));
12763 reg_stat_type *rsp = VEC_index (reg_stat_type, reg_stat, regno);
12765 if (dead_or_set_p (place, XEXP (note, 0))
12766 || reg_bitfield_target_p (XEXP (note, 0), PATTERN (place)))
12768 /* Unless the register previously died in PLACE, clear
12769 last_death. [I no longer understand why this is
12771 if (rsp->last_death != place)
12772 rsp->last_death = 0;
12776 rsp->last_death = place;
12778 /* If this is a death note for a hard reg that is occupying
12779 multiple registers, ensure that we are still using all
12780 parts of the object. If we find a piece of the object
12781 that is unused, we must arrange for an appropriate REG_DEAD
12782 note to be added for it. However, we can't just emit a USE
12783 and tag the note to it, since the register might actually
12784 be dead; so we recourse, and the recursive call then finds
12785 the previous insn that used this register. */
12787 if (place && regno < FIRST_PSEUDO_REGISTER
12788 && hard_regno_nregs[regno][GET_MODE (XEXP (note, 0))] > 1)
12790 unsigned int endregno = END_HARD_REGNO (XEXP (note, 0));
12794 for (i = regno; i < endregno; i++)
12795 if ((! refers_to_regno_p (i, i + 1, PATTERN (place), 0)
12796 && ! find_regno_fusage (place, USE, i))
12797 || dead_or_set_regno_p (place, i))
12802 /* Put only REG_DEAD notes for pieces that are
12803 not already dead or set. */
12805 for (i = regno; i < endregno;
12806 i += hard_regno_nregs[i][reg_raw_mode[i]])
12808 rtx piece = regno_reg_rtx[i];
12809 basic_block bb = this_basic_block;
12811 if (! dead_or_set_p (place, piece)
12812 && ! reg_bitfield_target_p (piece,
12816 = gen_rtx_EXPR_LIST (REG_DEAD, piece, NULL_RTX);
12818 distribute_notes (new_note, place, place,
12819 NULL_RTX, NULL_RTX, NULL_RTX);
12821 else if (! refers_to_regno_p (i, i + 1,
12822 PATTERN (place), 0)
12823 && ! find_regno_fusage (place, USE, i))
12824 for (tem = PREV_INSN (place); ;
12825 tem = PREV_INSN (tem))
12827 if (! INSN_P (tem))
12829 if (tem == BB_HEAD (bb))
12833 if (dead_or_set_p (tem, piece)
12834 || reg_bitfield_target_p (piece,
12838 = gen_rtx_EXPR_LIST (REG_UNUSED, piece,
12853 /* Any other notes should not be present at this point in the
12855 gcc_unreachable ();
12860 XEXP (note, 1) = REG_NOTES (place);
12861 REG_NOTES (place) = note;
12866 = gen_rtx_fmt_ee (GET_CODE (note), REG_NOTE_KIND (note),
12867 XEXP (note, 0), REG_NOTES (place2));
12871 /* Similarly to above, distribute the LOG_LINKS that used to be present on
12872 I3, I2, and I1 to new locations. This is also called to add a link
12873 pointing at I3 when I3's destination is changed. */
12876 distribute_links (rtx links)
12878 rtx link, next_link;
12880 for (link = links; link; link = next_link)
12886 next_link = XEXP (link, 1);
12888 /* If the insn that this link points to is a NOTE or isn't a single
12889 set, ignore it. In the latter case, it isn't clear what we
12890 can do other than ignore the link, since we can't tell which
12891 register it was for. Such links wouldn't be used by combine
12894 It is not possible for the destination of the target of the link to
12895 have been changed by combine. The only potential of this is if we
12896 replace I3, I2, and I1 by I3 and I2. But in that case the
12897 destination of I2 also remains unchanged. */
12899 if (NOTE_P (XEXP (link, 0))
12900 || (set = single_set (XEXP (link, 0))) == 0)
12903 reg = SET_DEST (set);
12904 while (GET_CODE (reg) == SUBREG || GET_CODE (reg) == ZERO_EXTRACT
12905 || GET_CODE (reg) == STRICT_LOW_PART)
12906 reg = XEXP (reg, 0);
12908 /* A LOG_LINK is defined as being placed on the first insn that uses
12909 a register and points to the insn that sets the register. Start
12910 searching at the next insn after the target of the link and stop
12911 when we reach a set of the register or the end of the basic block.
12913 Note that this correctly handles the link that used to point from
12914 I3 to I2. Also note that not much searching is typically done here
12915 since most links don't point very far away. */
12917 for (insn = NEXT_INSN (XEXP (link, 0));
12918 (insn && (this_basic_block->next_bb == EXIT_BLOCK_PTR
12919 || BB_HEAD (this_basic_block->next_bb) != insn));
12920 insn = NEXT_INSN (insn))
12921 if (INSN_P (insn) && reg_overlap_mentioned_p (reg, PATTERN (insn)))
12923 if (reg_referenced_p (reg, PATTERN (insn)))
12927 else if (CALL_P (insn)
12928 && find_reg_fusage (insn, USE, reg))
12933 else if (INSN_P (insn) && reg_set_p (reg, insn))
12936 /* If we found a place to put the link, place it there unless there
12937 is already a link to the same insn as LINK at that point. */
12943 for (link2 = LOG_LINKS (place); link2; link2 = XEXP (link2, 1))
12944 if (XEXP (link2, 0) == XEXP (link, 0))
12949 XEXP (link, 1) = LOG_LINKS (place);
12950 LOG_LINKS (place) = link;
12952 /* Set added_links_insn to the earliest insn we added a
12954 if (added_links_insn == 0
12955 || DF_INSN_LUID (added_links_insn) > DF_INSN_LUID (place))
12956 added_links_insn = place;
12962 /* Subroutine of unmentioned_reg_p and callback from for_each_rtx.
12963 Check whether the expression pointer to by LOC is a register or
12964 memory, and if so return 1 if it isn't mentioned in the rtx EXPR.
12965 Otherwise return zero. */
12968 unmentioned_reg_p_1 (rtx *loc, void *expr)
12973 && (REG_P (x) || MEM_P (x))
12974 && ! reg_mentioned_p (x, (rtx) expr))
12979 /* Check for any register or memory mentioned in EQUIV that is not
12980 mentioned in EXPR. This is used to restrict EQUIV to "specializations"
12981 of EXPR where some registers may have been replaced by constants. */
12984 unmentioned_reg_p (rtx equiv, rtx expr)
12986 return for_each_rtx (&equiv, unmentioned_reg_p_1, expr);
12990 dump_combine_stats (FILE *file)
12994 ";; Combiner statistics: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n\n",
12995 combine_attempts, combine_merges, combine_extras, combine_successes);
12999 dump_combine_total_stats (FILE *file)
13003 "\n;; Combiner totals: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n",
13004 total_attempts, total_merges, total_extras, total_successes);
13008 gate_handle_combine (void)
13010 return (optimize > 0);
13013 /* Try combining insns through substitution. */
13014 static unsigned int
13015 rest_of_handle_combine (void)
13017 int rebuild_jump_labels_after_combine;
13019 df_set_flags (DF_LR_RUN_DCE + DF_DEFER_INSN_RESCAN);
13020 df_note_add_problem ();
13023 regstat_init_n_sets_and_refs ();
13025 rebuild_jump_labels_after_combine
13026 = combine_instructions (get_insns (), max_reg_num ());
13028 /* Combining insns may have turned an indirect jump into a
13029 direct jump. Rebuild the JUMP_LABEL fields of jumping
13031 if (rebuild_jump_labels_after_combine)
13033 timevar_push (TV_JUMP);
13034 rebuild_jump_labels (get_insns ());
13036 timevar_pop (TV_JUMP);
13039 regstat_free_n_sets_and_refs ();
13043 struct rtl_opt_pass pass_combine =
13047 "combine", /* name */
13048 gate_handle_combine, /* gate */
13049 rest_of_handle_combine, /* execute */
13052 0, /* static_pass_number */
13053 TV_COMBINE, /* tv_id */
13054 0, /* properties_required */
13055 0, /* properties_provided */
13056 0, /* properties_destroyed */
13057 0, /* todo_flags_start */
13059 TODO_df_finish | TODO_verify_rtl_sharing |
13060 TODO_ggc_collect, /* todo_flags_finish */