1 /* Optimize by combining instructions for GNU compiler.
2 Copyright (C) 1987, 1988, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010,
4 2011, 2012 Free Software Foundation, Inc.
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify it under
9 the terms of the GNU General Public License as published by the Free
10 Software Foundation; either version 3, or (at your option) any later
13 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
14 WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
22 /* This module is essentially the "combiner" phase of the U. of Arizona
23 Portable Optimizer, but redone to work on our list-structured
24 representation for RTL instead of their string representation.
26 The LOG_LINKS of each insn identify the most recent assignment
27 to each REG used in the insn. It is a list of previous insns,
28 each of which contains a SET for a REG that is used in this insn
29 and not used or set in between. LOG_LINKs never cross basic blocks.
30 They were set up by the preceding pass (lifetime analysis).
32 We try to combine each pair of insns joined by a logical link.
33 We also try to combine triples of insns A, B and C when
34 C has a link back to B and B has a link back to A.
36 LOG_LINKS does not have links for use of the CC0. They don't
37 need to, because the insn that sets the CC0 is always immediately
38 before the insn that tests it. So we always regard a branch
39 insn as having a logical link to the preceding insn. The same is true
40 for an insn explicitly using CC0.
42 We check (with use_crosses_set_p) to avoid combining in such a way
43 as to move a computation to a place where its value would be different.
45 Combination is done by mathematically substituting the previous
46 insn(s) values for the regs they set into the expressions in
47 the later insns that refer to these regs. If the result is a valid insn
48 for our target machine, according to the machine description,
49 we install it, delete the earlier insns, and update the data flow
50 information (LOG_LINKS and REG_NOTES) for what we did.
52 There are a few exceptions where the dataflow information isn't
53 completely updated (however this is only a local issue since it is
54 regenerated before the next pass that uses it):
56 - reg_live_length is not updated
57 - reg_n_refs is not adjusted in the rare case when a register is
58 no longer required in a computation
59 - there are extremely rare cases (see distribute_notes) when a
61 - a LOG_LINKS entry that refers to an insn with multiple SETs may be
62 removed because there is no way to know which register it was
65 To simplify substitution, we combine only when the earlier insn(s)
66 consist of only a single assignment. To simplify updating afterward,
67 we never combine when a subroutine call appears in the middle.
69 Since we do not represent assignments to CC0 explicitly except when that
70 is all an insn does, there is no LOG_LINKS entry in an insn that uses
71 the condition code for the insn that set the condition code.
72 Fortunately, these two insns must be consecutive.
73 Therefore, every JUMP_INSN is taken to have an implicit logical link
74 to the preceding insn. This is not quite right, since non-jumps can
75 also use the condition code; but in practice such insns would not
80 #include "coretypes.h"
87 #include "hard-reg-set.h"
88 #include "basic-block.h"
89 #include "insn-config.h"
91 /* Include expr.h after insn-config.h so we get HAVE_conditional_move. */
93 #include "insn-attr.h"
95 #include "diagnostic-core.h"
98 #include "insn-codes.h"
99 #include "rtlhooks-def.h"
100 /* Include output.h for dump_file. */
104 #include "tree-pass.h"
109 /* Number of attempts to combine instructions in this function. */
111 static int combine_attempts;
113 /* Number of attempts that got as far as substitution in this function. */
115 static int combine_merges;
117 /* Number of instructions combined with added SETs in this function. */
119 static int combine_extras;
121 /* Number of instructions combined in this function. */
123 static int combine_successes;
125 /* Totals over entire compilation. */
127 static int total_attempts, total_merges, total_extras, total_successes;
129 /* combine_instructions may try to replace the right hand side of the
130 second instruction with the value of an associated REG_EQUAL note
131 before throwing it at try_combine. That is problematic when there
132 is a REG_DEAD note for a register used in the old right hand side
133 and can cause distribute_notes to do wrong things. This is the
134 second instruction if it has been so modified, null otherwise. */
138 /* When I2MOD is nonnull, this is a copy of the old right hand side. */
140 static rtx i2mod_old_rhs;
142 /* When I2MOD is nonnull, this is a copy of the new right hand side. */
144 static rtx i2mod_new_rhs;
146 typedef struct reg_stat_struct {
147 /* Record last point of death of (hard or pseudo) register n. */
150 /* Record last point of modification of (hard or pseudo) register n. */
153 /* The next group of fields allows the recording of the last value assigned
154 to (hard or pseudo) register n. We use this information to see if an
155 operation being processed is redundant given a prior operation performed
156 on the register. For example, an `and' with a constant is redundant if
157 all the zero bits are already known to be turned off.
159 We use an approach similar to that used by cse, but change it in the
162 (1) We do not want to reinitialize at each label.
163 (2) It is useful, but not critical, to know the actual value assigned
164 to a register. Often just its form is helpful.
166 Therefore, we maintain the following fields:
168 last_set_value the last value assigned
169 last_set_label records the value of label_tick when the
170 register was assigned
171 last_set_table_tick records the value of label_tick when a
172 value using the register is assigned
173 last_set_invalid set to nonzero when it is not valid
174 to use the value of this register in some
177 To understand the usage of these tables, it is important to understand
178 the distinction between the value in last_set_value being valid and
179 the register being validly contained in some other expression in the
182 (The next two parameters are out of date).
184 reg_stat[i].last_set_value is valid if it is nonzero, and either
185 reg_n_sets[i] is 1 or reg_stat[i].last_set_label == label_tick.
187 Register I may validly appear in any expression returned for the value
188 of another register if reg_n_sets[i] is 1. It may also appear in the
189 value for register J if reg_stat[j].last_set_invalid is zero, or
190 reg_stat[i].last_set_label < reg_stat[j].last_set_label.
192 If an expression is found in the table containing a register which may
193 not validly appear in an expression, the register is replaced by
194 something that won't match, (clobber (const_int 0)). */
196 /* Record last value assigned to (hard or pseudo) register n. */
200 /* Record the value of label_tick when an expression involving register n
201 is placed in last_set_value. */
203 int last_set_table_tick;
205 /* Record the value of label_tick when the value for register n is placed in
210 /* These fields are maintained in parallel with last_set_value and are
211 used to store the mode in which the register was last set, the bits
212 that were known to be zero when it was last set, and the number of
213 sign bits copies it was known to have when it was last set. */
215 unsigned HOST_WIDE_INT last_set_nonzero_bits;
216 char last_set_sign_bit_copies;
217 ENUM_BITFIELD(machine_mode) last_set_mode : 8;
219 /* Set nonzero if references to register n in expressions should not be
220 used. last_set_invalid is set nonzero when this register is being
221 assigned to and last_set_table_tick == label_tick. */
223 char last_set_invalid;
225 /* Some registers that are set more than once and used in more than one
226 basic block are nevertheless always set in similar ways. For example,
227 a QImode register may be loaded from memory in two places on a machine
228 where byte loads zero extend.
230 We record in the following fields if a register has some leading bits
231 that are always equal to the sign bit, and what we know about the
232 nonzero bits of a register, specifically which bits are known to be
235 If an entry is zero, it means that we don't know anything special. */
237 unsigned char sign_bit_copies;
239 unsigned HOST_WIDE_INT nonzero_bits;
241 /* Record the value of the label_tick when the last truncation
242 happened. The field truncated_to_mode is only valid if
243 truncation_label == label_tick. */
245 int truncation_label;
247 /* Record the last truncation seen for this register. If truncation
248 is not a nop to this mode we might be able to save an explicit
249 truncation if we know that value already contains a truncated
252 ENUM_BITFIELD(machine_mode) truncated_to_mode : 8;
255 DEF_VEC_O(reg_stat_type);
256 DEF_VEC_ALLOC_O(reg_stat_type,heap);
258 static VEC(reg_stat_type,heap) *reg_stat;
260 /* Record the luid of the last insn that invalidated memory
261 (anything that writes memory, and subroutine calls, but not pushes). */
263 static int mem_last_set;
265 /* Record the luid of the last CALL_INSN
266 so we can tell whether a potential combination crosses any calls. */
268 static int last_call_luid;
270 /* When `subst' is called, this is the insn that is being modified
271 (by combining in a previous insn). The PATTERN of this insn
272 is still the old pattern partially modified and it should not be
273 looked at, but this may be used to examine the successors of the insn
274 to judge whether a simplification is valid. */
276 static rtx subst_insn;
278 /* This is the lowest LUID that `subst' is currently dealing with.
279 get_last_value will not return a value if the register was set at or
280 after this LUID. If not for this mechanism, we could get confused if
281 I2 or I1 in try_combine were an insn that used the old value of a register
282 to obtain a new value. In that case, we might erroneously get the
283 new value of the register when we wanted the old one. */
285 static int subst_low_luid;
287 /* This contains any hard registers that are used in newpat; reg_dead_at_p
288 must consider all these registers to be always live. */
290 static HARD_REG_SET newpat_used_regs;
292 /* This is an insn to which a LOG_LINKS entry has been added. If this
293 insn is the earlier than I2 or I3, combine should rescan starting at
296 static rtx added_links_insn;
298 /* Basic block in which we are performing combines. */
299 static basic_block this_basic_block;
300 static bool optimize_this_for_speed_p;
303 /* Length of the currently allocated uid_insn_cost array. */
305 static int max_uid_known;
307 /* The following array records the insn_rtx_cost for every insn
308 in the instruction stream. */
310 static int *uid_insn_cost;
312 /* The following array records the LOG_LINKS for every insn in the
313 instruction stream as struct insn_link pointers. */
317 struct insn_link *next;
320 static struct insn_link **uid_log_links;
322 #define INSN_COST(INSN) (uid_insn_cost[INSN_UID (INSN)])
323 #define LOG_LINKS(INSN) (uid_log_links[INSN_UID (INSN)])
325 #define FOR_EACH_LOG_LINK(L, INSN) \
326 for ((L) = LOG_LINKS (INSN); (L); (L) = (L)->next)
328 /* Links for LOG_LINKS are allocated from this obstack. */
330 static struct obstack insn_link_obstack;
332 /* Allocate a link. */
334 static inline struct insn_link *
335 alloc_insn_link (rtx insn, struct insn_link *next)
338 = (struct insn_link *) obstack_alloc (&insn_link_obstack,
339 sizeof (struct insn_link));
345 /* Incremented for each basic block. */
347 static int label_tick;
349 /* Reset to label_tick for each extended basic block in scanning order. */
351 static int label_tick_ebb_start;
353 /* Mode used to compute significance in reg_stat[].nonzero_bits. It is the
354 largest integer mode that can fit in HOST_BITS_PER_WIDE_INT. */
356 static enum machine_mode nonzero_bits_mode;
358 /* Nonzero when reg_stat[].nonzero_bits and reg_stat[].sign_bit_copies can
359 be safely used. It is zero while computing them and after combine has
360 completed. This former test prevents propagating values based on
361 previously set values, which can be incorrect if a variable is modified
364 static int nonzero_sign_valid;
367 /* Record one modification to rtl structure
368 to be undone by storing old_contents into *where. */
370 enum undo_kind { UNDO_RTX, UNDO_INT, UNDO_MODE, UNDO_LINKS };
376 union { rtx r; int i; enum machine_mode m; struct insn_link *l; } old_contents;
377 union { rtx *r; int *i; struct insn_link **l; } where;
380 /* Record a bunch of changes to be undone, up to MAX_UNDO of them.
381 num_undo says how many are currently recorded.
383 other_insn is nonzero if we have modified some other insn in the process
384 of working on subst_insn. It must be verified too. */
393 static struct undobuf undobuf;
395 /* Number of times the pseudo being substituted for
396 was found and replaced. */
398 static int n_occurrences;
400 static rtx reg_nonzero_bits_for_combine (const_rtx, enum machine_mode, const_rtx,
402 unsigned HOST_WIDE_INT,
403 unsigned HOST_WIDE_INT *);
404 static rtx reg_num_sign_bit_copies_for_combine (const_rtx, enum machine_mode, const_rtx,
406 unsigned int, unsigned int *);
407 static void do_SUBST (rtx *, rtx);
408 static void do_SUBST_INT (int *, int);
409 static void init_reg_last (void);
410 static void setup_incoming_promotions (rtx);
411 static void set_nonzero_bits_and_sign_copies (rtx, const_rtx, void *);
412 static int cant_combine_insn_p (rtx);
413 static int can_combine_p (rtx, rtx, rtx, rtx, rtx, rtx, rtx *, rtx *);
414 static int combinable_i3pat (rtx, rtx *, rtx, rtx, rtx, int, int, rtx *);
415 static int contains_muldiv (rtx);
416 static rtx try_combine (rtx, rtx, rtx, rtx, int *, rtx);
417 static void undo_all (void);
418 static void undo_commit (void);
419 static rtx *find_split_point (rtx *, rtx, bool);
420 static rtx subst (rtx, rtx, rtx, int, int, int);
421 static rtx combine_simplify_rtx (rtx, enum machine_mode, int, int);
422 static rtx simplify_if_then_else (rtx);
423 static rtx simplify_set (rtx);
424 static rtx simplify_logical (rtx);
425 static rtx expand_compound_operation (rtx);
426 static const_rtx expand_field_assignment (const_rtx);
427 static rtx make_extraction (enum machine_mode, rtx, HOST_WIDE_INT,
428 rtx, unsigned HOST_WIDE_INT, int, int, int);
429 static rtx extract_left_shift (rtx, int);
430 static rtx make_compound_operation (rtx, enum rtx_code);
431 static int get_pos_from_mask (unsigned HOST_WIDE_INT,
432 unsigned HOST_WIDE_INT *);
433 static rtx canon_reg_for_combine (rtx, rtx);
434 static rtx force_to_mode (rtx, enum machine_mode,
435 unsigned HOST_WIDE_INT, int);
436 static rtx if_then_else_cond (rtx, rtx *, rtx *);
437 static rtx known_cond (rtx, enum rtx_code, rtx, rtx);
438 static int rtx_equal_for_field_assignment_p (rtx, rtx);
439 static rtx make_field_assignment (rtx);
440 static rtx apply_distributive_law (rtx);
441 static rtx distribute_and_simplify_rtx (rtx, int);
442 static rtx simplify_and_const_int_1 (enum machine_mode, rtx,
443 unsigned HOST_WIDE_INT);
444 static rtx simplify_and_const_int (rtx, enum machine_mode, rtx,
445 unsigned HOST_WIDE_INT);
446 static int merge_outer_ops (enum rtx_code *, HOST_WIDE_INT *, enum rtx_code,
447 HOST_WIDE_INT, enum machine_mode, int *);
448 static rtx simplify_shift_const_1 (enum rtx_code, enum machine_mode, rtx, int);
449 static rtx simplify_shift_const (rtx, enum rtx_code, enum machine_mode, rtx,
451 static int recog_for_combine (rtx *, rtx, rtx *);
452 static rtx gen_lowpart_for_combine (enum machine_mode, rtx);
453 static enum rtx_code simplify_compare_const (enum rtx_code, rtx, rtx *);
454 static enum rtx_code simplify_comparison (enum rtx_code, rtx *, rtx *);
455 static void update_table_tick (rtx);
456 static void record_value_for_reg (rtx, rtx, rtx);
457 static void check_promoted_subreg (rtx, rtx);
458 static void record_dead_and_set_regs_1 (rtx, const_rtx, void *);
459 static void record_dead_and_set_regs (rtx);
460 static int get_last_value_validate (rtx *, rtx, int, int);
461 static rtx get_last_value (const_rtx);
462 static int use_crosses_set_p (const_rtx, int);
463 static void reg_dead_at_p_1 (rtx, const_rtx, void *);
464 static int reg_dead_at_p (rtx, rtx);
465 static void move_deaths (rtx, rtx, int, rtx, rtx *);
466 static int reg_bitfield_target_p (rtx, rtx);
467 static void distribute_notes (rtx, rtx, rtx, rtx, rtx, rtx, rtx);
468 static void distribute_links (struct insn_link *);
469 static void mark_used_regs_combine (rtx);
470 static void record_promoted_value (rtx, rtx);
471 static int unmentioned_reg_p_1 (rtx *, void *);
472 static bool unmentioned_reg_p (rtx, rtx);
473 static int record_truncated_value (rtx *, void *);
474 static void record_truncated_values (rtx *, void *);
475 static bool reg_truncated_to_mode (enum machine_mode, const_rtx);
476 static rtx gen_lowpart_or_truncate (enum machine_mode, rtx);
479 /* It is not safe to use ordinary gen_lowpart in combine.
480 See comments in gen_lowpart_for_combine. */
481 #undef RTL_HOOKS_GEN_LOWPART
482 #define RTL_HOOKS_GEN_LOWPART gen_lowpart_for_combine
484 /* Our implementation of gen_lowpart never emits a new pseudo. */
485 #undef RTL_HOOKS_GEN_LOWPART_NO_EMIT
486 #define RTL_HOOKS_GEN_LOWPART_NO_EMIT gen_lowpart_for_combine
488 #undef RTL_HOOKS_REG_NONZERO_REG_BITS
489 #define RTL_HOOKS_REG_NONZERO_REG_BITS reg_nonzero_bits_for_combine
491 #undef RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES
492 #define RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES reg_num_sign_bit_copies_for_combine
494 #undef RTL_HOOKS_REG_TRUNCATED_TO_MODE
495 #define RTL_HOOKS_REG_TRUNCATED_TO_MODE reg_truncated_to_mode
497 static const struct rtl_hooks combine_rtl_hooks = RTL_HOOKS_INITIALIZER;
500 /* Try to split PATTERN found in INSN. This returns NULL_RTX if
501 PATTERN can not be split. Otherwise, it returns an insn sequence.
502 This is a wrapper around split_insns which ensures that the
503 reg_stat vector is made larger if the splitter creates a new
507 combine_split_insns (rtx pattern, rtx insn)
512 ret = split_insns (pattern, insn);
513 nregs = max_reg_num ();
514 if (nregs > VEC_length (reg_stat_type, reg_stat))
515 VEC_safe_grow_cleared (reg_stat_type, heap, reg_stat, nregs);
519 /* This is used by find_single_use to locate an rtx in LOC that
520 contains exactly one use of DEST, which is typically either a REG
521 or CC0. It returns a pointer to the innermost rtx expression
522 containing DEST. Appearances of DEST that are being used to
523 totally replace it are not counted. */
526 find_single_use_1 (rtx dest, rtx *loc)
529 enum rtx_code code = GET_CODE (x);
547 /* If the destination is anything other than CC0, PC, a REG or a SUBREG
548 of a REG that occupies all of the REG, the insn uses DEST if
549 it is mentioned in the destination or the source. Otherwise, we
550 need just check the source. */
551 if (GET_CODE (SET_DEST (x)) != CC0
552 && GET_CODE (SET_DEST (x)) != PC
553 && !REG_P (SET_DEST (x))
554 && ! (GET_CODE (SET_DEST (x)) == SUBREG
555 && REG_P (SUBREG_REG (SET_DEST (x)))
556 && (((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x))))
557 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
558 == ((GET_MODE_SIZE (GET_MODE (SET_DEST (x)))
559 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD))))
562 return find_single_use_1 (dest, &SET_SRC (x));
566 return find_single_use_1 (dest, &XEXP (x, 0));
572 /* If it wasn't one of the common cases above, check each expression and
573 vector of this code. Look for a unique usage of DEST. */
575 fmt = GET_RTX_FORMAT (code);
576 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
580 if (dest == XEXP (x, i)
581 || (REG_P (dest) && REG_P (XEXP (x, i))
582 && REGNO (dest) == REGNO (XEXP (x, i))))
585 this_result = find_single_use_1 (dest, &XEXP (x, i));
588 result = this_result;
589 else if (this_result)
590 /* Duplicate usage. */
593 else if (fmt[i] == 'E')
597 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
599 if (XVECEXP (x, i, j) == dest
601 && REG_P (XVECEXP (x, i, j))
602 && REGNO (XVECEXP (x, i, j)) == REGNO (dest)))
605 this_result = find_single_use_1 (dest, &XVECEXP (x, i, j));
608 result = this_result;
609 else if (this_result)
619 /* See if DEST, produced in INSN, is used only a single time in the
620 sequel. If so, return a pointer to the innermost rtx expression in which
623 If PLOC is nonzero, *PLOC is set to the insn containing the single use.
625 If DEST is cc0_rtx, we look only at the next insn. In that case, we don't
626 care about REG_DEAD notes or LOG_LINKS.
628 Otherwise, we find the single use by finding an insn that has a
629 LOG_LINKS pointing at INSN and has a REG_DEAD note for DEST. If DEST is
630 only referenced once in that insn, we know that it must be the first
631 and last insn referencing DEST. */
634 find_single_use (rtx dest, rtx insn, rtx *ploc)
639 struct insn_link *link;
644 next = NEXT_INSN (insn);
646 || (!NONJUMP_INSN_P (next) && !JUMP_P (next)))
649 result = find_single_use_1 (dest, &PATTERN (next));
659 bb = BLOCK_FOR_INSN (insn);
660 for (next = NEXT_INSN (insn);
661 next && BLOCK_FOR_INSN (next) == bb;
662 next = NEXT_INSN (next))
663 if (INSN_P (next) && dead_or_set_p (next, dest))
665 FOR_EACH_LOG_LINK (link, next)
666 if (link->insn == insn)
671 result = find_single_use_1 (dest, &PATTERN (next));
681 /* Substitute NEWVAL, an rtx expression, into INTO, a place in some
682 insn. The substitution can be undone by undo_all. If INTO is already
683 set to NEWVAL, do not record this change. Because computing NEWVAL might
684 also call SUBST, we have to compute it before we put anything into
688 do_SUBST (rtx *into, rtx newval)
693 if (oldval == newval)
696 /* We'd like to catch as many invalid transformations here as
697 possible. Unfortunately, there are way too many mode changes
698 that are perfectly valid, so we'd waste too much effort for
699 little gain doing the checks here. Focus on catching invalid
700 transformations involving integer constants. */
701 if (GET_MODE_CLASS (GET_MODE (oldval)) == MODE_INT
702 && CONST_INT_P (newval))
704 /* Sanity check that we're replacing oldval with a CONST_INT
705 that is a valid sign-extension for the original mode. */
706 gcc_assert (INTVAL (newval)
707 == trunc_int_for_mode (INTVAL (newval), GET_MODE (oldval)));
709 /* Replacing the operand of a SUBREG or a ZERO_EXTEND with a
710 CONST_INT is not valid, because after the replacement, the
711 original mode would be gone. Unfortunately, we can't tell
712 when do_SUBST is called to replace the operand thereof, so we
713 perform this test on oldval instead, checking whether an
714 invalid replacement took place before we got here. */
715 gcc_assert (!(GET_CODE (oldval) == SUBREG
716 && CONST_INT_P (SUBREG_REG (oldval))));
717 gcc_assert (!(GET_CODE (oldval) == ZERO_EXTEND
718 && CONST_INT_P (XEXP (oldval, 0))));
722 buf = undobuf.frees, undobuf.frees = buf->next;
724 buf = XNEW (struct undo);
726 buf->kind = UNDO_RTX;
728 buf->old_contents.r = oldval;
731 buf->next = undobuf.undos, undobuf.undos = buf;
734 #define SUBST(INTO, NEWVAL) do_SUBST(&(INTO), (NEWVAL))
736 /* Similar to SUBST, but NEWVAL is an int expression. Note that substitution
737 for the value of a HOST_WIDE_INT value (including CONST_INT) is
741 do_SUBST_INT (int *into, int newval)
746 if (oldval == newval)
750 buf = undobuf.frees, undobuf.frees = buf->next;
752 buf = XNEW (struct undo);
754 buf->kind = UNDO_INT;
756 buf->old_contents.i = oldval;
759 buf->next = undobuf.undos, undobuf.undos = buf;
762 #define SUBST_INT(INTO, NEWVAL) do_SUBST_INT(&(INTO), (NEWVAL))
764 /* Similar to SUBST, but just substitute the mode. This is used when
765 changing the mode of a pseudo-register, so that any other
766 references to the entry in the regno_reg_rtx array will change as
770 do_SUBST_MODE (rtx *into, enum machine_mode newval)
773 enum machine_mode oldval = GET_MODE (*into);
775 if (oldval == newval)
779 buf = undobuf.frees, undobuf.frees = buf->next;
781 buf = XNEW (struct undo);
783 buf->kind = UNDO_MODE;
785 buf->old_contents.m = oldval;
786 adjust_reg_mode (*into, newval);
788 buf->next = undobuf.undos, undobuf.undos = buf;
791 #define SUBST_MODE(INTO, NEWVAL) do_SUBST_MODE(&(INTO), (NEWVAL))
794 /* Similar to SUBST, but NEWVAL is a LOG_LINKS expression. */
797 do_SUBST_LINK (struct insn_link **into, struct insn_link *newval)
800 struct insn_link * oldval = *into;
802 if (oldval == newval)
806 buf = undobuf.frees, undobuf.frees = buf->next;
808 buf = XNEW (struct undo);
810 buf->kind = UNDO_LINKS;
812 buf->old_contents.l = oldval;
815 buf->next = undobuf.undos, undobuf.undos = buf;
818 #define SUBST_LINK(oldval, newval) do_SUBST_LINK (&oldval, newval)
821 /* Subroutine of try_combine. Determine whether the replacement patterns
822 NEWPAT, NEWI2PAT and NEWOTHERPAT are cheaper according to insn_rtx_cost
823 than the original sequence I0, I1, I2, I3 and undobuf.other_insn. Note
824 that I0, I1 and/or NEWI2PAT may be NULL_RTX. Similarly, NEWOTHERPAT and
825 undobuf.other_insn may also both be NULL_RTX. Return false if the cost
826 of all the instructions can be estimated and the replacements are more
827 expensive than the original sequence. */
830 combine_validate_cost (rtx i0, rtx i1, rtx i2, rtx i3, rtx newpat,
831 rtx newi2pat, rtx newotherpat)
833 int i0_cost, i1_cost, i2_cost, i3_cost;
834 int new_i2_cost, new_i3_cost;
835 int old_cost, new_cost;
837 /* Lookup the original insn_rtx_costs. */
838 i2_cost = INSN_COST (i2);
839 i3_cost = INSN_COST (i3);
843 i1_cost = INSN_COST (i1);
846 i0_cost = INSN_COST (i0);
847 old_cost = (i0_cost > 0 && i1_cost > 0 && i2_cost > 0 && i3_cost > 0
848 ? i0_cost + i1_cost + i2_cost + i3_cost : 0);
852 old_cost = (i1_cost > 0 && i2_cost > 0 && i3_cost > 0
853 ? i1_cost + i2_cost + i3_cost : 0);
859 old_cost = (i2_cost > 0 && i3_cost > 0) ? i2_cost + i3_cost : 0;
860 i1_cost = i0_cost = 0;
863 /* Calculate the replacement insn_rtx_costs. */
864 new_i3_cost = insn_rtx_cost (newpat, optimize_this_for_speed_p);
867 new_i2_cost = insn_rtx_cost (newi2pat, optimize_this_for_speed_p);
868 new_cost = (new_i2_cost > 0 && new_i3_cost > 0)
869 ? new_i2_cost + new_i3_cost : 0;
873 new_cost = new_i3_cost;
877 if (undobuf.other_insn)
879 int old_other_cost, new_other_cost;
881 old_other_cost = INSN_COST (undobuf.other_insn);
882 new_other_cost = insn_rtx_cost (newotherpat, optimize_this_for_speed_p);
883 if (old_other_cost > 0 && new_other_cost > 0)
885 old_cost += old_other_cost;
886 new_cost += new_other_cost;
892 /* Disallow this combination if both new_cost and old_cost are greater than
893 zero, and new_cost is greater than old cost. */
894 if (old_cost > 0 && new_cost > old_cost)
901 "rejecting combination of insns %d, %d, %d and %d\n",
902 INSN_UID (i0), INSN_UID (i1), INSN_UID (i2),
904 fprintf (dump_file, "original costs %d + %d + %d + %d = %d\n",
905 i0_cost, i1_cost, i2_cost, i3_cost, old_cost);
910 "rejecting combination of insns %d, %d and %d\n",
911 INSN_UID (i1), INSN_UID (i2), INSN_UID (i3));
912 fprintf (dump_file, "original costs %d + %d + %d = %d\n",
913 i1_cost, i2_cost, i3_cost, old_cost);
918 "rejecting combination of insns %d and %d\n",
919 INSN_UID (i2), INSN_UID (i3));
920 fprintf (dump_file, "original costs %d + %d = %d\n",
921 i2_cost, i3_cost, old_cost);
926 fprintf (dump_file, "replacement costs %d + %d = %d\n",
927 new_i2_cost, new_i3_cost, new_cost);
930 fprintf (dump_file, "replacement cost %d\n", new_cost);
936 /* Update the uid_insn_cost array with the replacement costs. */
937 INSN_COST (i2) = new_i2_cost;
938 INSN_COST (i3) = new_i3_cost;
950 /* Delete any insns that copy a register to itself. */
953 delete_noop_moves (void)
960 for (insn = BB_HEAD (bb); insn != NEXT_INSN (BB_END (bb)); insn = next)
962 next = NEXT_INSN (insn);
963 if (INSN_P (insn) && noop_move_p (insn))
966 fprintf (dump_file, "deleting noop move %d\n", INSN_UID (insn));
968 delete_insn_and_edges (insn);
975 /* Fill in log links field for all insns. */
978 create_log_links (void)
982 df_ref *def_vec, *use_vec;
984 next_use = XCNEWVEC (rtx, max_reg_num ());
986 /* Pass through each block from the end, recording the uses of each
987 register and establishing log links when def is encountered.
988 Note that we do not clear next_use array in order to save time,
989 so we have to test whether the use is in the same basic block as def.
991 There are a few cases below when we do not consider the definition or
992 usage -- these are taken from original flow.c did. Don't ask me why it is
993 done this way; I don't know and if it works, I don't want to know. */
997 FOR_BB_INSNS_REVERSE (bb, insn)
999 if (!NONDEBUG_INSN_P (insn))
1002 /* Log links are created only once. */
1003 gcc_assert (!LOG_LINKS (insn));
1005 for (def_vec = DF_INSN_DEFS (insn); *def_vec; def_vec++)
1007 df_ref def = *def_vec;
1008 int regno = DF_REF_REGNO (def);
1011 if (!next_use[regno])
1014 /* Do not consider if it is pre/post modification in MEM. */
1015 if (DF_REF_FLAGS (def) & DF_REF_PRE_POST_MODIFY)
1018 /* Do not make the log link for frame pointer. */
1019 if ((regno == FRAME_POINTER_REGNUM
1020 && (! reload_completed || frame_pointer_needed))
1021 #if !HARD_FRAME_POINTER_IS_FRAME_POINTER
1022 || (regno == HARD_FRAME_POINTER_REGNUM
1023 && (! reload_completed || frame_pointer_needed))
1025 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
1026 || (regno == ARG_POINTER_REGNUM && fixed_regs[regno])
1031 use_insn = next_use[regno];
1032 if (BLOCK_FOR_INSN (use_insn) == bb)
1036 We don't build a LOG_LINK for hard registers contained
1037 in ASM_OPERANDs. If these registers get replaced,
1038 we might wind up changing the semantics of the insn,
1039 even if reload can make what appear to be valid
1040 assignments later. */
1041 if (regno >= FIRST_PSEUDO_REGISTER
1042 || asm_noperands (PATTERN (use_insn)) < 0)
1044 /* Don't add duplicate links between instructions. */
1045 struct insn_link *links;
1046 FOR_EACH_LOG_LINK (links, use_insn)
1047 if (insn == links->insn)
1051 LOG_LINKS (use_insn)
1052 = alloc_insn_link (insn, LOG_LINKS (use_insn));
1055 next_use[regno] = NULL_RTX;
1058 for (use_vec = DF_INSN_USES (insn); *use_vec; use_vec++)
1060 df_ref use = *use_vec;
1061 int regno = DF_REF_REGNO (use);
1063 /* Do not consider the usage of the stack pointer
1064 by function call. */
1065 if (DF_REF_FLAGS (use) & DF_REF_CALL_STACK_USAGE)
1068 next_use[regno] = insn;
1076 /* Walk the LOG_LINKS of insn B to see if we find a reference to A. Return
1077 true if we found a LOG_LINK that proves that A feeds B. This only works
1078 if there are no instructions between A and B which could have a link
1079 depending on A, since in that case we would not record a link for B.
1080 We also check the implicit dependency created by a cc0 setter/user
1084 insn_a_feeds_b (rtx a, rtx b)
1086 struct insn_link *links;
1087 FOR_EACH_LOG_LINK (links, b)
1088 if (links->insn == a)
1097 /* Main entry point for combiner. F is the first insn of the function.
1098 NREGS is the first unused pseudo-reg number.
1100 Return nonzero if the combiner has turned an indirect jump
1101 instruction into a direct jump. */
1103 combine_instructions (rtx f, unsigned int nregs)
1109 struct insn_link *links, *nextlinks;
1111 basic_block last_bb;
1113 int new_direct_jump_p = 0;
1115 for (first = f; first && !INSN_P (first); )
1116 first = NEXT_INSN (first);
1120 combine_attempts = 0;
1123 combine_successes = 0;
1125 rtl_hooks = combine_rtl_hooks;
1127 VEC_safe_grow_cleared (reg_stat_type, heap, reg_stat, nregs);
1129 init_recog_no_volatile ();
1131 /* Allocate array for insn info. */
1132 max_uid_known = get_max_uid ();
1133 uid_log_links = XCNEWVEC (struct insn_link *, max_uid_known + 1);
1134 uid_insn_cost = XCNEWVEC (int, max_uid_known + 1);
1135 gcc_obstack_init (&insn_link_obstack);
1137 nonzero_bits_mode = mode_for_size (HOST_BITS_PER_WIDE_INT, MODE_INT, 0);
1139 /* Don't use reg_stat[].nonzero_bits when computing it. This can cause
1140 problems when, for example, we have j <<= 1 in a loop. */
1142 nonzero_sign_valid = 0;
1143 label_tick = label_tick_ebb_start = 1;
1145 /* Scan all SETs and see if we can deduce anything about what
1146 bits are known to be zero for some registers and how many copies
1147 of the sign bit are known to exist for those registers.
1149 Also set any known values so that we can use it while searching
1150 for what bits are known to be set. */
1152 setup_incoming_promotions (first);
1153 /* Allow the entry block and the first block to fall into the same EBB.
1154 Conceptually the incoming promotions are assigned to the entry block. */
1155 last_bb = ENTRY_BLOCK_PTR;
1157 create_log_links ();
1158 FOR_EACH_BB (this_basic_block)
1160 optimize_this_for_speed_p = optimize_bb_for_speed_p (this_basic_block);
1165 if (!single_pred_p (this_basic_block)
1166 || single_pred (this_basic_block) != last_bb)
1167 label_tick_ebb_start = label_tick;
1168 last_bb = this_basic_block;
1170 FOR_BB_INSNS (this_basic_block, insn)
1171 if (INSN_P (insn) && BLOCK_FOR_INSN (insn))
1177 subst_low_luid = DF_INSN_LUID (insn);
1180 note_stores (PATTERN (insn), set_nonzero_bits_and_sign_copies,
1182 record_dead_and_set_regs (insn);
1185 for (links = REG_NOTES (insn); links; links = XEXP (links, 1))
1186 if (REG_NOTE_KIND (links) == REG_INC)
1187 set_nonzero_bits_and_sign_copies (XEXP (links, 0), NULL_RTX,
1191 /* Record the current insn_rtx_cost of this instruction. */
1192 if (NONJUMP_INSN_P (insn))
1193 INSN_COST (insn) = insn_rtx_cost (PATTERN (insn),
1194 optimize_this_for_speed_p);
1196 fprintf(dump_file, "insn_cost %d: %d\n",
1197 INSN_UID (insn), INSN_COST (insn));
1201 nonzero_sign_valid = 1;
1203 /* Now scan all the insns in forward order. */
1204 label_tick = label_tick_ebb_start = 1;
1206 setup_incoming_promotions (first);
1207 last_bb = ENTRY_BLOCK_PTR;
1209 FOR_EACH_BB (this_basic_block)
1211 rtx last_combined_insn = NULL_RTX;
1212 optimize_this_for_speed_p = optimize_bb_for_speed_p (this_basic_block);
1217 if (!single_pred_p (this_basic_block)
1218 || single_pred (this_basic_block) != last_bb)
1219 label_tick_ebb_start = label_tick;
1220 last_bb = this_basic_block;
1222 rtl_profile_for_bb (this_basic_block);
1223 for (insn = BB_HEAD (this_basic_block);
1224 insn != NEXT_INSN (BB_END (this_basic_block));
1225 insn = next ? next : NEXT_INSN (insn))
1228 if (NONDEBUG_INSN_P (insn))
1230 while (last_combined_insn
1231 && INSN_DELETED_P (last_combined_insn))
1232 last_combined_insn = PREV_INSN (last_combined_insn);
1233 if (last_combined_insn == NULL_RTX
1234 || BARRIER_P (last_combined_insn)
1235 || BLOCK_FOR_INSN (last_combined_insn) != this_basic_block
1236 || DF_INSN_LUID (last_combined_insn) <= DF_INSN_LUID (insn))
1237 last_combined_insn = insn;
1239 /* See if we know about function return values before this
1240 insn based upon SUBREG flags. */
1241 check_promoted_subreg (insn, PATTERN (insn));
1243 /* See if we can find hardregs and subreg of pseudos in
1244 narrower modes. This could help turning TRUNCATEs
1246 note_uses (&PATTERN (insn), record_truncated_values, NULL);
1248 /* Try this insn with each insn it links back to. */
1250 FOR_EACH_LOG_LINK (links, insn)
1251 if ((next = try_combine (insn, links->insn, NULL_RTX,
1252 NULL_RTX, &new_direct_jump_p,
1253 last_combined_insn)) != 0)
1256 /* Try each sequence of three linked insns ending with this one. */
1258 FOR_EACH_LOG_LINK (links, insn)
1260 rtx link = links->insn;
1262 /* If the linked insn has been replaced by a note, then there
1263 is no point in pursuing this chain any further. */
1267 FOR_EACH_LOG_LINK (nextlinks, link)
1268 if ((next = try_combine (insn, link, nextlinks->insn,
1269 NULL_RTX, &new_direct_jump_p,
1270 last_combined_insn)) != 0)
1275 /* Try to combine a jump insn that uses CC0
1276 with a preceding insn that sets CC0, and maybe with its
1277 logical predecessor as well.
1278 This is how we make decrement-and-branch insns.
1279 We need this special code because data flow connections
1280 via CC0 do not get entered in LOG_LINKS. */
1283 && (prev = prev_nonnote_insn (insn)) != 0
1284 && NONJUMP_INSN_P (prev)
1285 && sets_cc0_p (PATTERN (prev)))
1287 if ((next = try_combine (insn, prev, NULL_RTX, NULL_RTX,
1289 last_combined_insn)) != 0)
1292 FOR_EACH_LOG_LINK (nextlinks, prev)
1293 if ((next = try_combine (insn, prev, nextlinks->insn,
1294 NULL_RTX, &new_direct_jump_p,
1295 last_combined_insn)) != 0)
1299 /* Do the same for an insn that explicitly references CC0. */
1300 if (NONJUMP_INSN_P (insn)
1301 && (prev = prev_nonnote_insn (insn)) != 0
1302 && NONJUMP_INSN_P (prev)
1303 && sets_cc0_p (PATTERN (prev))
1304 && GET_CODE (PATTERN (insn)) == SET
1305 && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (insn))))
1307 if ((next = try_combine (insn, prev, NULL_RTX, NULL_RTX,
1309 last_combined_insn)) != 0)
1312 FOR_EACH_LOG_LINK (nextlinks, prev)
1313 if ((next = try_combine (insn, prev, nextlinks->insn,
1314 NULL_RTX, &new_direct_jump_p,
1315 last_combined_insn)) != 0)
1319 /* Finally, see if any of the insns that this insn links to
1320 explicitly references CC0. If so, try this insn, that insn,
1321 and its predecessor if it sets CC0. */
1322 FOR_EACH_LOG_LINK (links, insn)
1323 if (NONJUMP_INSN_P (links->insn)
1324 && GET_CODE (PATTERN (links->insn)) == SET
1325 && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (links->insn)))
1326 && (prev = prev_nonnote_insn (links->insn)) != 0
1327 && NONJUMP_INSN_P (prev)
1328 && sets_cc0_p (PATTERN (prev))
1329 && (next = try_combine (insn, links->insn,
1330 prev, NULL_RTX, &new_direct_jump_p,
1331 last_combined_insn)) != 0)
1335 /* Try combining an insn with two different insns whose results it
1337 FOR_EACH_LOG_LINK (links, insn)
1338 for (nextlinks = links->next; nextlinks;
1339 nextlinks = nextlinks->next)
1340 if ((next = try_combine (insn, links->insn,
1341 nextlinks->insn, NULL_RTX,
1343 last_combined_insn)) != 0)
1346 /* Try four-instruction combinations. */
1347 FOR_EACH_LOG_LINK (links, insn)
1349 struct insn_link *next1;
1350 rtx link = links->insn;
1352 /* If the linked insn has been replaced by a note, then there
1353 is no point in pursuing this chain any further. */
1357 FOR_EACH_LOG_LINK (next1, link)
1359 rtx link1 = next1->insn;
1362 /* I0 -> I1 -> I2 -> I3. */
1363 FOR_EACH_LOG_LINK (nextlinks, link1)
1364 if ((next = try_combine (insn, link, link1,
1367 last_combined_insn)) != 0)
1369 /* I0, I1 -> I2, I2 -> I3. */
1370 for (nextlinks = next1->next; nextlinks;
1371 nextlinks = nextlinks->next)
1372 if ((next = try_combine (insn, link, link1,
1375 last_combined_insn)) != 0)
1379 for (next1 = links->next; next1; next1 = next1->next)
1381 rtx link1 = next1->insn;
1384 /* I0 -> I2; I1, I2 -> I3. */
1385 FOR_EACH_LOG_LINK (nextlinks, link)
1386 if ((next = try_combine (insn, link, link1,
1389 last_combined_insn)) != 0)
1391 /* I0 -> I1; I1, I2 -> I3. */
1392 FOR_EACH_LOG_LINK (nextlinks, link1)
1393 if ((next = try_combine (insn, link, link1,
1396 last_combined_insn)) != 0)
1401 /* Try this insn with each REG_EQUAL note it links back to. */
1402 FOR_EACH_LOG_LINK (links, insn)
1405 rtx temp = links->insn;
1406 if ((set = single_set (temp)) != 0
1407 && (note = find_reg_equal_equiv_note (temp)) != 0
1408 && (note = XEXP (note, 0), GET_CODE (note)) != EXPR_LIST
1409 /* Avoid using a register that may already been marked
1410 dead by an earlier instruction. */
1411 && ! unmentioned_reg_p (note, SET_SRC (set))
1412 && (GET_MODE (note) == VOIDmode
1413 ? SCALAR_INT_MODE_P (GET_MODE (SET_DEST (set)))
1414 : GET_MODE (SET_DEST (set)) == GET_MODE (note)))
1416 /* Temporarily replace the set's source with the
1417 contents of the REG_EQUAL note. The insn will
1418 be deleted or recognized by try_combine. */
1419 rtx orig = SET_SRC (set);
1420 SET_SRC (set) = note;
1422 i2mod_old_rhs = copy_rtx (orig);
1423 i2mod_new_rhs = copy_rtx (note);
1424 next = try_combine (insn, i2mod, NULL_RTX, NULL_RTX,
1426 last_combined_insn);
1430 SET_SRC (set) = orig;
1435 record_dead_and_set_regs (insn);
1443 default_rtl_profile ();
1445 new_direct_jump_p |= purge_all_dead_edges ();
1446 delete_noop_moves ();
1449 obstack_free (&insn_link_obstack, NULL);
1450 free (uid_log_links);
1451 free (uid_insn_cost);
1452 VEC_free (reg_stat_type, heap, reg_stat);
1455 struct undo *undo, *next;
1456 for (undo = undobuf.frees; undo; undo = next)
1464 total_attempts += combine_attempts;
1465 total_merges += combine_merges;
1466 total_extras += combine_extras;
1467 total_successes += combine_successes;
1469 nonzero_sign_valid = 0;
1470 rtl_hooks = general_rtl_hooks;
1472 /* Make recognizer allow volatile MEMs again. */
1475 return new_direct_jump_p;
1478 /* Wipe the last_xxx fields of reg_stat in preparation for another pass. */
1481 init_reg_last (void)
1486 FOR_EACH_VEC_ELT (reg_stat_type, reg_stat, i, p)
1487 memset (p, 0, offsetof (reg_stat_type, sign_bit_copies));
1490 /* Set up any promoted values for incoming argument registers. */
1493 setup_incoming_promotions (rtx first)
1496 bool strictly_local = false;
1498 for (arg = DECL_ARGUMENTS (current_function_decl); arg;
1499 arg = DECL_CHAIN (arg))
1501 rtx x, reg = DECL_INCOMING_RTL (arg);
1503 enum machine_mode mode1, mode2, mode3, mode4;
1505 /* Only continue if the incoming argument is in a register. */
1509 /* Determine, if possible, whether all call sites of the current
1510 function lie within the current compilation unit. (This does
1511 take into account the exporting of a function via taking its
1512 address, and so forth.) */
1513 strictly_local = cgraph_local_info (current_function_decl)->local;
1515 /* The mode and signedness of the argument before any promotions happen
1516 (equal to the mode of the pseudo holding it at that stage). */
1517 mode1 = TYPE_MODE (TREE_TYPE (arg));
1518 uns1 = TYPE_UNSIGNED (TREE_TYPE (arg));
1520 /* The mode and signedness of the argument after any source language and
1521 TARGET_PROMOTE_PROTOTYPES-driven promotions. */
1522 mode2 = TYPE_MODE (DECL_ARG_TYPE (arg));
1523 uns3 = TYPE_UNSIGNED (DECL_ARG_TYPE (arg));
1525 /* The mode and signedness of the argument as it is actually passed,
1526 after any TARGET_PROMOTE_FUNCTION_ARGS-driven ABI promotions. */
1527 mode3 = promote_function_mode (DECL_ARG_TYPE (arg), mode2, &uns3,
1528 TREE_TYPE (cfun->decl), 0);
1530 /* The mode of the register in which the argument is being passed. */
1531 mode4 = GET_MODE (reg);
1533 /* Eliminate sign extensions in the callee when:
1534 (a) A mode promotion has occurred; */
1537 /* (b) The mode of the register is the same as the mode of
1538 the argument as it is passed; */
1541 /* (c) There's no language level extension; */
1544 /* (c.1) All callers are from the current compilation unit. If that's
1545 the case we don't have to rely on an ABI, we only have to know
1546 what we're generating right now, and we know that we will do the
1547 mode1 to mode2 promotion with the given sign. */
1548 else if (!strictly_local)
1550 /* (c.2) The combination of the two promotions is useful. This is
1551 true when the signs match, or if the first promotion is unsigned.
1552 In the later case, (sign_extend (zero_extend x)) is the same as
1553 (zero_extend (zero_extend x)), so make sure to force UNS3 true. */
1559 /* Record that the value was promoted from mode1 to mode3,
1560 so that any sign extension at the head of the current
1561 function may be eliminated. */
1562 x = gen_rtx_CLOBBER (mode1, const0_rtx);
1563 x = gen_rtx_fmt_e ((uns3 ? ZERO_EXTEND : SIGN_EXTEND), mode3, x);
1564 record_value_for_reg (reg, first, x);
1568 /* Called via note_stores. If X is a pseudo that is narrower than
1569 HOST_BITS_PER_WIDE_INT and is being set, record what bits are known zero.
1571 If we are setting only a portion of X and we can't figure out what
1572 portion, assume all bits will be used since we don't know what will
1575 Similarly, set how many bits of X are known to be copies of the sign bit
1576 at all locations in the function. This is the smallest number implied
1580 set_nonzero_bits_and_sign_copies (rtx x, const_rtx set, void *data)
1582 rtx insn = (rtx) data;
1586 && REGNO (x) >= FIRST_PSEUDO_REGISTER
1587 /* If this register is undefined at the start of the file, we can't
1588 say what its contents were. */
1589 && ! REGNO_REG_SET_P
1590 (DF_LR_IN (ENTRY_BLOCK_PTR->next_bb), REGNO (x))
1591 && HWI_COMPUTABLE_MODE_P (GET_MODE (x)))
1593 reg_stat_type *rsp = VEC_index (reg_stat_type, reg_stat, REGNO (x));
1595 if (set == 0 || GET_CODE (set) == CLOBBER)
1597 rsp->nonzero_bits = GET_MODE_MASK (GET_MODE (x));
1598 rsp->sign_bit_copies = 1;
1602 /* If this register is being initialized using itself, and the
1603 register is uninitialized in this basic block, and there are
1604 no LOG_LINKS which set the register, then part of the
1605 register is uninitialized. In that case we can't assume
1606 anything about the number of nonzero bits.
1608 ??? We could do better if we checked this in
1609 reg_{nonzero_bits,num_sign_bit_copies}_for_combine. Then we
1610 could avoid making assumptions about the insn which initially
1611 sets the register, while still using the information in other
1612 insns. We would have to be careful to check every insn
1613 involved in the combination. */
1616 && reg_referenced_p (x, PATTERN (insn))
1617 && !REGNO_REG_SET_P (DF_LR_IN (BLOCK_FOR_INSN (insn)),
1620 struct insn_link *link;
1622 FOR_EACH_LOG_LINK (link, insn)
1623 if (dead_or_set_p (link->insn, x))
1627 rsp->nonzero_bits = GET_MODE_MASK (GET_MODE (x));
1628 rsp->sign_bit_copies = 1;
1633 /* If this is a complex assignment, see if we can convert it into a
1634 simple assignment. */
1635 set = expand_field_assignment (set);
1637 /* If this is a simple assignment, or we have a paradoxical SUBREG,
1638 set what we know about X. */
1640 if (SET_DEST (set) == x
1641 || (paradoxical_subreg_p (SET_DEST (set))
1642 && SUBREG_REG (SET_DEST (set)) == x))
1644 rtx src = SET_SRC (set);
1646 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
1647 /* If X is narrower than a word and SRC is a non-negative
1648 constant that would appear negative in the mode of X,
1649 sign-extend it for use in reg_stat[].nonzero_bits because some
1650 machines (maybe most) will actually do the sign-extension
1651 and this is the conservative approach.
1653 ??? For 2.5, try to tighten up the MD files in this regard
1654 instead of this kludge. */
1656 if (GET_MODE_PRECISION (GET_MODE (x)) < BITS_PER_WORD
1657 && CONST_INT_P (src)
1659 && val_signbit_known_set_p (GET_MODE (x), INTVAL (src)))
1660 src = GEN_INT (INTVAL (src) | ~GET_MODE_MASK (GET_MODE (x)));
1663 /* Don't call nonzero_bits if it cannot change anything. */
1664 if (rsp->nonzero_bits != ~(unsigned HOST_WIDE_INT) 0)
1665 rsp->nonzero_bits |= nonzero_bits (src, nonzero_bits_mode);
1666 num = num_sign_bit_copies (SET_SRC (set), GET_MODE (x));
1667 if (rsp->sign_bit_copies == 0
1668 || rsp->sign_bit_copies > num)
1669 rsp->sign_bit_copies = num;
1673 rsp->nonzero_bits = GET_MODE_MASK (GET_MODE (x));
1674 rsp->sign_bit_copies = 1;
1679 /* See if INSN can be combined into I3. PRED, PRED2, SUCC and SUCC2 are
1680 optionally insns that were previously combined into I3 or that will be
1681 combined into the merger of INSN and I3. The order is PRED, PRED2,
1682 INSN, SUCC, SUCC2, I3.
1684 Return 0 if the combination is not allowed for any reason.
1686 If the combination is allowed, *PDEST will be set to the single
1687 destination of INSN and *PSRC to the single source, and this function
1691 can_combine_p (rtx insn, rtx i3, rtx pred ATTRIBUTE_UNUSED,
1692 rtx pred2 ATTRIBUTE_UNUSED, rtx succ, rtx succ2,
1693 rtx *pdest, rtx *psrc)
1702 bool all_adjacent = true;
1703 int (*is_volatile_p) (const_rtx);
1709 if (next_active_insn (succ2) != i3)
1710 all_adjacent = false;
1711 if (next_active_insn (succ) != succ2)
1712 all_adjacent = false;
1714 else if (next_active_insn (succ) != i3)
1715 all_adjacent = false;
1716 if (next_active_insn (insn) != succ)
1717 all_adjacent = false;
1719 else if (next_active_insn (insn) != i3)
1720 all_adjacent = false;
1722 /* Can combine only if previous insn is a SET of a REG, a SUBREG or CC0.
1723 or a PARALLEL consisting of such a SET and CLOBBERs.
1725 If INSN has CLOBBER parallel parts, ignore them for our processing.
1726 By definition, these happen during the execution of the insn. When it
1727 is merged with another insn, all bets are off. If they are, in fact,
1728 needed and aren't also supplied in I3, they may be added by
1729 recog_for_combine. Otherwise, it won't match.
1731 We can also ignore a SET whose SET_DEST is mentioned in a REG_UNUSED
1734 Get the source and destination of INSN. If more than one, can't
1737 if (GET_CODE (PATTERN (insn)) == SET)
1738 set = PATTERN (insn);
1739 else if (GET_CODE (PATTERN (insn)) == PARALLEL
1740 && GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == SET)
1742 for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
1744 rtx elt = XVECEXP (PATTERN (insn), 0, i);
1746 switch (GET_CODE (elt))
1748 /* This is important to combine floating point insns
1749 for the SH4 port. */
1751 /* Combining an isolated USE doesn't make sense.
1752 We depend here on combinable_i3pat to reject them. */
1753 /* The code below this loop only verifies that the inputs of
1754 the SET in INSN do not change. We call reg_set_between_p
1755 to verify that the REG in the USE does not change between
1757 If the USE in INSN was for a pseudo register, the matching
1758 insn pattern will likely match any register; combining this
1759 with any other USE would only be safe if we knew that the
1760 used registers have identical values, or if there was
1761 something to tell them apart, e.g. different modes. For
1762 now, we forgo such complicated tests and simply disallow
1763 combining of USES of pseudo registers with any other USE. */
1764 if (REG_P (XEXP (elt, 0))
1765 && GET_CODE (PATTERN (i3)) == PARALLEL)
1767 rtx i3pat = PATTERN (i3);
1768 int i = XVECLEN (i3pat, 0) - 1;
1769 unsigned int regno = REGNO (XEXP (elt, 0));
1773 rtx i3elt = XVECEXP (i3pat, 0, i);
1775 if (GET_CODE (i3elt) == USE
1776 && REG_P (XEXP (i3elt, 0))
1777 && (REGNO (XEXP (i3elt, 0)) == regno
1778 ? reg_set_between_p (XEXP (elt, 0),
1779 PREV_INSN (insn), i3)
1780 : regno >= FIRST_PSEUDO_REGISTER))
1787 /* We can ignore CLOBBERs. */
1792 /* Ignore SETs whose result isn't used but not those that
1793 have side-effects. */
1794 if (find_reg_note (insn, REG_UNUSED, SET_DEST (elt))
1795 && insn_nothrow_p (insn)
1796 && !side_effects_p (elt))
1799 /* If we have already found a SET, this is a second one and
1800 so we cannot combine with this insn. */
1808 /* Anything else means we can't combine. */
1814 /* If SET_SRC is an ASM_OPERANDS we can't throw away these CLOBBERs,
1815 so don't do anything with it. */
1816 || GET_CODE (SET_SRC (set)) == ASM_OPERANDS)
1825 /* The simplification in expand_field_assignment may call back to
1826 get_last_value, so set safe guard here. */
1827 subst_low_luid = DF_INSN_LUID (insn);
1829 set = expand_field_assignment (set);
1830 src = SET_SRC (set), dest = SET_DEST (set);
1832 /* Don't eliminate a store in the stack pointer. */
1833 if (dest == stack_pointer_rtx
1834 /* Don't combine with an insn that sets a register to itself if it has
1835 a REG_EQUAL note. This may be part of a LIBCALL sequence. */
1836 || (rtx_equal_p (src, dest) && find_reg_note (insn, REG_EQUAL, NULL_RTX))
1837 /* Can't merge an ASM_OPERANDS. */
1838 || GET_CODE (src) == ASM_OPERANDS
1839 /* Can't merge a function call. */
1840 || GET_CODE (src) == CALL
1841 /* Don't eliminate a function call argument. */
1843 && (find_reg_fusage (i3, USE, dest)
1845 && REGNO (dest) < FIRST_PSEUDO_REGISTER
1846 && global_regs[REGNO (dest)])))
1847 /* Don't substitute into an incremented register. */
1848 || FIND_REG_INC_NOTE (i3, dest)
1849 || (succ && FIND_REG_INC_NOTE (succ, dest))
1850 || (succ2 && FIND_REG_INC_NOTE (succ2, dest))
1851 /* Don't substitute into a non-local goto, this confuses CFG. */
1852 || (JUMP_P (i3) && find_reg_note (i3, REG_NON_LOCAL_GOTO, NULL_RTX))
1853 /* Make sure that DEST is not used after SUCC but before I3. */
1856 && (reg_used_between_p (dest, succ2, i3)
1857 || reg_used_between_p (dest, succ, succ2)))
1858 || (!succ2 && succ && reg_used_between_p (dest, succ, i3))))
1859 /* Make sure that the value that is to be substituted for the register
1860 does not use any registers whose values alter in between. However,
1861 If the insns are adjacent, a use can't cross a set even though we
1862 think it might (this can happen for a sequence of insns each setting
1863 the same destination; last_set of that register might point to
1864 a NOTE). If INSN has a REG_EQUIV note, the register is always
1865 equivalent to the memory so the substitution is valid even if there
1866 are intervening stores. Also, don't move a volatile asm or
1867 UNSPEC_VOLATILE across any other insns. */
1870 || ! find_reg_note (insn, REG_EQUIV, src))
1871 && use_crosses_set_p (src, DF_INSN_LUID (insn)))
1872 || (GET_CODE (src) == ASM_OPERANDS && MEM_VOLATILE_P (src))
1873 || GET_CODE (src) == UNSPEC_VOLATILE))
1874 /* Don't combine across a CALL_INSN, because that would possibly
1875 change whether the life span of some REGs crosses calls or not,
1876 and it is a pain to update that information.
1877 Exception: if source is a constant, moving it later can't hurt.
1878 Accept that as a special case. */
1879 || (DF_INSN_LUID (insn) < last_call_luid && ! CONSTANT_P (src)))
1882 /* DEST must either be a REG or CC0. */
1885 /* If register alignment is being enforced for multi-word items in all
1886 cases except for parameters, it is possible to have a register copy
1887 insn referencing a hard register that is not allowed to contain the
1888 mode being copied and which would not be valid as an operand of most
1889 insns. Eliminate this problem by not combining with such an insn.
1891 Also, on some machines we don't want to extend the life of a hard
1895 && ((REGNO (dest) < FIRST_PSEUDO_REGISTER
1896 && ! HARD_REGNO_MODE_OK (REGNO (dest), GET_MODE (dest)))
1897 /* Don't extend the life of a hard register unless it is
1898 user variable (if we have few registers) or it can't
1899 fit into the desired register (meaning something special
1901 Also avoid substituting a return register into I3, because
1902 reload can't handle a conflict with constraints of other
1904 || (REGNO (src) < FIRST_PSEUDO_REGISTER
1905 && ! HARD_REGNO_MODE_OK (REGNO (src), GET_MODE (src)))))
1908 else if (GET_CODE (dest) != CC0)
1912 if (GET_CODE (PATTERN (i3)) == PARALLEL)
1913 for (i = XVECLEN (PATTERN (i3), 0) - 1; i >= 0; i--)
1914 if (GET_CODE (XVECEXP (PATTERN (i3), 0, i)) == CLOBBER)
1916 /* Don't substitute for a register intended as a clobberable
1918 rtx reg = XEXP (XVECEXP (PATTERN (i3), 0, i), 0);
1919 if (rtx_equal_p (reg, dest))
1922 /* If the clobber represents an earlyclobber operand, we must not
1923 substitute an expression containing the clobbered register.
1924 As we do not analyze the constraint strings here, we have to
1925 make the conservative assumption. However, if the register is
1926 a fixed hard reg, the clobber cannot represent any operand;
1927 we leave it up to the machine description to either accept or
1928 reject use-and-clobber patterns. */
1930 || REGNO (reg) >= FIRST_PSEUDO_REGISTER
1931 || !fixed_regs[REGNO (reg)])
1932 if (reg_overlap_mentioned_p (reg, src))
1936 /* If INSN contains anything volatile, or is an `asm' (whether volatile
1937 or not), reject, unless nothing volatile comes between it and I3 */
1939 if (GET_CODE (src) == ASM_OPERANDS || volatile_refs_p (src))
1941 /* Make sure neither succ nor succ2 contains a volatile reference. */
1942 if (succ2 != 0 && volatile_refs_p (PATTERN (succ2)))
1944 if (succ != 0 && volatile_refs_p (PATTERN (succ)))
1946 /* We'll check insns between INSN and I3 below. */
1949 /* If INSN is an asm, and DEST is a hard register, reject, since it has
1950 to be an explicit register variable, and was chosen for a reason. */
1952 if (GET_CODE (src) == ASM_OPERANDS
1953 && REG_P (dest) && REGNO (dest) < FIRST_PSEUDO_REGISTER)
1956 /* If INSN contains volatile references (specifically volatile MEMs),
1957 we cannot combine across any other volatile references.
1958 Even if INSN doesn't contain volatile references, any intervening
1959 volatile insn might affect machine state. */
1961 is_volatile_p = volatile_refs_p (PATTERN (insn))
1965 for (p = NEXT_INSN (insn); p != i3; p = NEXT_INSN (p))
1966 if (INSN_P (p) && p != succ && p != succ2 && is_volatile_p (PATTERN (p)))
1969 /* If INSN contains an autoincrement or autodecrement, make sure that
1970 register is not used between there and I3, and not already used in
1971 I3 either. Neither must it be used in PRED or SUCC, if they exist.
1972 Also insist that I3 not be a jump; if it were one
1973 and the incremented register were spilled, we would lose. */
1976 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
1977 if (REG_NOTE_KIND (link) == REG_INC
1979 || reg_used_between_p (XEXP (link, 0), insn, i3)
1980 || (pred != NULL_RTX
1981 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (pred)))
1982 || (pred2 != NULL_RTX
1983 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (pred2)))
1984 || (succ != NULL_RTX
1985 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (succ)))
1986 || (succ2 != NULL_RTX
1987 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (succ2)))
1988 || reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i3))))
1993 /* Don't combine an insn that follows a CC0-setting insn.
1994 An insn that uses CC0 must not be separated from the one that sets it.
1995 We do, however, allow I2 to follow a CC0-setting insn if that insn
1996 is passed as I1; in that case it will be deleted also.
1997 We also allow combining in this case if all the insns are adjacent
1998 because that would leave the two CC0 insns adjacent as well.
1999 It would be more logical to test whether CC0 occurs inside I1 or I2,
2000 but that would be much slower, and this ought to be equivalent. */
2002 p = prev_nonnote_insn (insn);
2003 if (p && p != pred && NONJUMP_INSN_P (p) && sets_cc0_p (PATTERN (p))
2008 /* If we get here, we have passed all the tests and the combination is
2017 /* LOC is the location within I3 that contains its pattern or the component
2018 of a PARALLEL of the pattern. We validate that it is valid for combining.
2020 One problem is if I3 modifies its output, as opposed to replacing it
2021 entirely, we can't allow the output to contain I2DEST, I1DEST or I0DEST as
2022 doing so would produce an insn that is not equivalent to the original insns.
2026 (set (reg:DI 101) (reg:DI 100))
2027 (set (subreg:SI (reg:DI 101) 0) <foo>)
2029 This is NOT equivalent to:
2031 (parallel [(set (subreg:SI (reg:DI 100) 0) <foo>)
2032 (set (reg:DI 101) (reg:DI 100))])
2034 Not only does this modify 100 (in which case it might still be valid
2035 if 100 were dead in I2), it sets 101 to the ORIGINAL value of 100.
2037 We can also run into a problem if I2 sets a register that I1
2038 uses and I1 gets directly substituted into I3 (not via I2). In that
2039 case, we would be getting the wrong value of I2DEST into I3, so we
2040 must reject the combination. This case occurs when I2 and I1 both
2041 feed into I3, rather than when I1 feeds into I2, which feeds into I3.
2042 If I1_NOT_IN_SRC is nonzero, it means that finding I1 in the source
2043 of a SET must prevent combination from occurring. The same situation
2044 can occur for I0, in which case I0_NOT_IN_SRC is set.
2046 Before doing the above check, we first try to expand a field assignment
2047 into a set of logical operations.
2049 If PI3_DEST_KILLED is nonzero, it is a pointer to a location in which
2050 we place a register that is both set and used within I3. If more than one
2051 such register is detected, we fail.
2053 Return 1 if the combination is valid, zero otherwise. */
2056 combinable_i3pat (rtx i3, rtx *loc, rtx i2dest, rtx i1dest, rtx i0dest,
2057 int i1_not_in_src, int i0_not_in_src, rtx *pi3dest_killed)
2061 if (GET_CODE (x) == SET)
2064 rtx dest = SET_DEST (set);
2065 rtx src = SET_SRC (set);
2066 rtx inner_dest = dest;
2069 while (GET_CODE (inner_dest) == STRICT_LOW_PART
2070 || GET_CODE (inner_dest) == SUBREG
2071 || GET_CODE (inner_dest) == ZERO_EXTRACT)
2072 inner_dest = XEXP (inner_dest, 0);
2074 /* Check for the case where I3 modifies its output, as discussed
2075 above. We don't want to prevent pseudos from being combined
2076 into the address of a MEM, so only prevent the combination if
2077 i1 or i2 set the same MEM. */
2078 if ((inner_dest != dest &&
2079 (!MEM_P (inner_dest)
2080 || rtx_equal_p (i2dest, inner_dest)
2081 || (i1dest && rtx_equal_p (i1dest, inner_dest))
2082 || (i0dest && rtx_equal_p (i0dest, inner_dest)))
2083 && (reg_overlap_mentioned_p (i2dest, inner_dest)
2084 || (i1dest && reg_overlap_mentioned_p (i1dest, inner_dest))
2085 || (i0dest && reg_overlap_mentioned_p (i0dest, inner_dest))))
2087 /* This is the same test done in can_combine_p except we can't test
2088 all_adjacent; we don't have to, since this instruction will stay
2089 in place, thus we are not considering increasing the lifetime of
2092 Also, if this insn sets a function argument, combining it with
2093 something that might need a spill could clobber a previous
2094 function argument; the all_adjacent test in can_combine_p also
2095 checks this; here, we do a more specific test for this case. */
2097 || (REG_P (inner_dest)
2098 && REGNO (inner_dest) < FIRST_PSEUDO_REGISTER
2099 && (! HARD_REGNO_MODE_OK (REGNO (inner_dest),
2100 GET_MODE (inner_dest))))
2101 || (i1_not_in_src && reg_overlap_mentioned_p (i1dest, src))
2102 || (i0_not_in_src && reg_overlap_mentioned_p (i0dest, src)))
2105 /* If DEST is used in I3, it is being killed in this insn, so
2106 record that for later. We have to consider paradoxical
2107 subregs here, since they kill the whole register, but we
2108 ignore partial subregs, STRICT_LOW_PART, etc.
2109 Never add REG_DEAD notes for the FRAME_POINTER_REGNUM or the
2110 STACK_POINTER_REGNUM, since these are always considered to be
2111 live. Similarly for ARG_POINTER_REGNUM if it is fixed. */
2113 if (GET_CODE (subdest) == SUBREG
2114 && (GET_MODE_SIZE (GET_MODE (subdest))
2115 >= GET_MODE_SIZE (GET_MODE (SUBREG_REG (subdest)))))
2116 subdest = SUBREG_REG (subdest);
2119 && reg_referenced_p (subdest, PATTERN (i3))
2120 && REGNO (subdest) != FRAME_POINTER_REGNUM
2121 #if !HARD_FRAME_POINTER_IS_FRAME_POINTER
2122 && REGNO (subdest) != HARD_FRAME_POINTER_REGNUM
2124 #if ARG_POINTER_REGNUM != FRAME_POINTER_REGNUM
2125 && (REGNO (subdest) != ARG_POINTER_REGNUM
2126 || ! fixed_regs [REGNO (subdest)])
2128 && REGNO (subdest) != STACK_POINTER_REGNUM)
2130 if (*pi3dest_killed)
2133 *pi3dest_killed = subdest;
2137 else if (GET_CODE (x) == PARALLEL)
2141 for (i = 0; i < XVECLEN (x, 0); i++)
2142 if (! combinable_i3pat (i3, &XVECEXP (x, 0, i), i2dest, i1dest, i0dest,
2143 i1_not_in_src, i0_not_in_src, pi3dest_killed))
2150 /* Return 1 if X is an arithmetic expression that contains a multiplication
2151 and division. We don't count multiplications by powers of two here. */
2154 contains_muldiv (rtx x)
2156 switch (GET_CODE (x))
2158 case MOD: case DIV: case UMOD: case UDIV:
2162 return ! (CONST_INT_P (XEXP (x, 1))
2163 && exact_log2 (UINTVAL (XEXP (x, 1))) >= 0);
2166 return contains_muldiv (XEXP (x, 0))
2167 || contains_muldiv (XEXP (x, 1));
2170 return contains_muldiv (XEXP (x, 0));
2176 /* Determine whether INSN can be used in a combination. Return nonzero if
2177 not. This is used in try_combine to detect early some cases where we
2178 can't perform combinations. */
2181 cant_combine_insn_p (rtx insn)
2186 /* If this isn't really an insn, we can't do anything.
2187 This can occur when flow deletes an insn that it has merged into an
2188 auto-increment address. */
2189 if (! INSN_P (insn))
2192 /* Never combine loads and stores involving hard regs that are likely
2193 to be spilled. The register allocator can usually handle such
2194 reg-reg moves by tying. If we allow the combiner to make
2195 substitutions of likely-spilled regs, reload might die.
2196 As an exception, we allow combinations involving fixed regs; these are
2197 not available to the register allocator so there's no risk involved. */
2199 set = single_set (insn);
2202 src = SET_SRC (set);
2203 dest = SET_DEST (set);
2204 if (GET_CODE (src) == SUBREG)
2205 src = SUBREG_REG (src);
2206 if (GET_CODE (dest) == SUBREG)
2207 dest = SUBREG_REG (dest);
2208 if (REG_P (src) && REG_P (dest)
2209 && ((HARD_REGISTER_P (src)
2210 && ! TEST_HARD_REG_BIT (fixed_reg_set, REGNO (src))
2211 && targetm.class_likely_spilled_p (REGNO_REG_CLASS (REGNO (src))))
2212 || (HARD_REGISTER_P (dest)
2213 && ! TEST_HARD_REG_BIT (fixed_reg_set, REGNO (dest))
2214 && targetm.class_likely_spilled_p (REGNO_REG_CLASS (REGNO (dest))))))
2220 struct likely_spilled_retval_info
2222 unsigned regno, nregs;
2226 /* Called via note_stores by likely_spilled_retval_p. Remove from info->mask
2227 hard registers that are known to be written to / clobbered in full. */
2229 likely_spilled_retval_1 (rtx x, const_rtx set, void *data)
2231 struct likely_spilled_retval_info *const info =
2232 (struct likely_spilled_retval_info *) data;
2233 unsigned regno, nregs;
2236 if (!REG_P (XEXP (set, 0)))
2239 if (regno >= info->regno + info->nregs)
2241 nregs = hard_regno_nregs[regno][GET_MODE (x)];
2242 if (regno + nregs <= info->regno)
2244 new_mask = (2U << (nregs - 1)) - 1;
2245 if (regno < info->regno)
2246 new_mask >>= info->regno - regno;
2248 new_mask <<= regno - info->regno;
2249 info->mask &= ~new_mask;
2252 /* Return nonzero iff part of the return value is live during INSN, and
2253 it is likely spilled. This can happen when more than one insn is needed
2254 to copy the return value, e.g. when we consider to combine into the
2255 second copy insn for a complex value. */
2258 likely_spilled_retval_p (rtx insn)
2260 rtx use = BB_END (this_basic_block);
2262 unsigned regno, nregs;
2263 /* We assume here that no machine mode needs more than
2264 32 hard registers when the value overlaps with a register
2265 for which TARGET_FUNCTION_VALUE_REGNO_P is true. */
2267 struct likely_spilled_retval_info info;
2269 if (!NONJUMP_INSN_P (use) || GET_CODE (PATTERN (use)) != USE || insn == use)
2271 reg = XEXP (PATTERN (use), 0);
2272 if (!REG_P (reg) || !targetm.calls.function_value_regno_p (REGNO (reg)))
2274 regno = REGNO (reg);
2275 nregs = hard_regno_nregs[regno][GET_MODE (reg)];
2278 mask = (2U << (nregs - 1)) - 1;
2280 /* Disregard parts of the return value that are set later. */
2284 for (p = PREV_INSN (use); info.mask && p != insn; p = PREV_INSN (p))
2286 note_stores (PATTERN (p), likely_spilled_retval_1, &info);
2289 /* Check if any of the (probably) live return value registers is
2294 if ((mask & 1 << nregs)
2295 && targetm.class_likely_spilled_p (REGNO_REG_CLASS (regno + nregs)))
2301 /* Adjust INSN after we made a change to its destination.
2303 Changing the destination can invalidate notes that say something about
2304 the results of the insn and a LOG_LINK pointing to the insn. */
2307 adjust_for_new_dest (rtx insn)
2309 /* For notes, be conservative and simply remove them. */
2310 remove_reg_equal_equiv_notes (insn);
2312 /* The new insn will have a destination that was previously the destination
2313 of an insn just above it. Call distribute_links to make a LOG_LINK from
2314 the next use of that destination. */
2315 distribute_links (alloc_insn_link (insn, NULL));
2317 df_insn_rescan (insn);
2320 /* Return TRUE if combine can reuse reg X in mode MODE.
2321 ADDED_SETS is nonzero if the original set is still required. */
2323 can_change_dest_mode (rtx x, int added_sets, enum machine_mode mode)
2331 /* Allow hard registers if the new mode is legal, and occupies no more
2332 registers than the old mode. */
2333 if (regno < FIRST_PSEUDO_REGISTER)
2334 return (HARD_REGNO_MODE_OK (regno, mode)
2335 && (hard_regno_nregs[regno][GET_MODE (x)]
2336 >= hard_regno_nregs[regno][mode]));
2338 /* Or a pseudo that is only used once. */
2339 return (REG_N_SETS (regno) == 1 && !added_sets
2340 && !REG_USERVAR_P (x));
2344 /* Check whether X, the destination of a set, refers to part of
2345 the register specified by REG. */
2348 reg_subword_p (rtx x, rtx reg)
2350 /* Check that reg is an integer mode register. */
2351 if (!REG_P (reg) || GET_MODE_CLASS (GET_MODE (reg)) != MODE_INT)
2354 if (GET_CODE (x) == STRICT_LOW_PART
2355 || GET_CODE (x) == ZERO_EXTRACT)
2358 return GET_CODE (x) == SUBREG
2359 && SUBREG_REG (x) == reg
2360 && GET_MODE_CLASS (GET_MODE (x)) == MODE_INT;
2364 /* Replace auto-increment addressing modes with explicit operations to access
2365 the same addresses without modifying the corresponding registers. */
2368 cleanup_auto_inc_dec (rtx src, enum machine_mode mem_mode)
2371 const RTX_CODE code = GET_CODE (x);
2387 /* SCRATCH must be shared because they represent distinct values. */
2390 if (REG_P (XEXP (x, 0)) && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER)
2395 if (shared_const_p (x))
2400 mem_mode = GET_MODE (x);
2405 gcc_assert (mem_mode != VOIDmode && mem_mode != BLKmode);
2406 return gen_rtx_PLUS (GET_MODE (x),
2407 cleanup_auto_inc_dec (XEXP (x, 0), mem_mode),
2408 GEN_INT (code == PRE_INC
2409 ? GET_MODE_SIZE (mem_mode)
2410 : -GET_MODE_SIZE (mem_mode)));
2416 return cleanup_auto_inc_dec (code == PRE_MODIFY
2417 ? XEXP (x, 1) : XEXP (x, 0),
2424 /* Copy the various flags, fields, and other information. We assume
2425 that all fields need copying, and then clear the fields that should
2426 not be copied. That is the sensible default behavior, and forces
2427 us to explicitly document why we are *not* copying a flag. */
2428 x = shallow_copy_rtx (x);
2430 /* We do not copy the USED flag, which is used as a mark bit during
2431 walks over the RTL. */
2432 RTX_FLAG (x, used) = 0;
2434 /* We do not copy FRAME_RELATED for INSNs. */
2436 RTX_FLAG (x, frame_related) = 0;
2438 fmt = GET_RTX_FORMAT (code);
2439 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
2441 XEXP (x, i) = cleanup_auto_inc_dec (XEXP (x, i), mem_mode);
2442 else if (fmt[i] == 'E' || fmt[i] == 'V')
2445 XVEC (x, i) = rtvec_alloc (XVECLEN (x, i));
2446 for (j = 0; j < XVECLEN (x, i); j++)
2448 = cleanup_auto_inc_dec (XVECEXP (src, i, j), mem_mode);
2455 /* Auxiliary data structure for propagate_for_debug_stmt. */
2457 struct rtx_subst_pair
2463 /* DATA points to an rtx_subst_pair. Return the value that should be
2467 propagate_for_debug_subst (rtx from, const_rtx old_rtx, void *data)
2469 struct rtx_subst_pair *pair = (struct rtx_subst_pair *)data;
2471 if (!rtx_equal_p (from, old_rtx))
2473 if (!pair->adjusted)
2475 pair->adjusted = true;
2477 pair->to = cleanup_auto_inc_dec (pair->to, VOIDmode);
2479 pair->to = copy_rtx (pair->to);
2481 pair->to = make_compound_operation (pair->to, SET);
2484 return copy_rtx (pair->to);
2487 /* Replace all the occurrences of DEST with SRC in DEBUG_INSNs between INSN
2488 and LAST, not including INSN, but including LAST. Also stop at the end
2489 of THIS_BASIC_BLOCK. */
2492 propagate_for_debug (rtx insn, rtx last, rtx dest, rtx src)
2494 rtx next, loc, end = NEXT_INSN (BB_END (this_basic_block));
2496 struct rtx_subst_pair p;
2500 next = NEXT_INSN (insn);
2501 last = NEXT_INSN (last);
2502 while (next != last && next != end)
2505 next = NEXT_INSN (insn);
2506 if (DEBUG_INSN_P (insn))
2508 loc = simplify_replace_fn_rtx (INSN_VAR_LOCATION_LOC (insn),
2509 dest, propagate_for_debug_subst, &p);
2510 if (loc == INSN_VAR_LOCATION_LOC (insn))
2512 INSN_VAR_LOCATION_LOC (insn) = loc;
2513 df_insn_rescan (insn);
2518 /* Delete the unconditional jump INSN and adjust the CFG correspondingly.
2519 Note that the INSN should be deleted *after* removing dead edges, so
2520 that the kept edge is the fallthrough edge for a (set (pc) (pc))
2521 but not for a (set (pc) (label_ref FOO)). */
2524 update_cfg_for_uncondjump (rtx insn)
2526 basic_block bb = BLOCK_FOR_INSN (insn);
2527 gcc_assert (BB_END (bb) == insn);
2529 purge_dead_edges (bb);
2532 if (EDGE_COUNT (bb->succs) == 1)
2536 single_succ_edge (bb)->flags |= EDGE_FALLTHRU;
2538 /* Remove barriers from the footer if there are any. */
2539 for (insn = bb->il.rtl->footer; insn; insn = NEXT_INSN (insn))
2540 if (BARRIER_P (insn))
2542 if (PREV_INSN (insn))
2543 NEXT_INSN (PREV_INSN (insn)) = NEXT_INSN (insn);
2545 bb->il.rtl->footer = NEXT_INSN (insn);
2546 if (NEXT_INSN (insn))
2547 PREV_INSN (NEXT_INSN (insn)) = PREV_INSN (insn);
2549 else if (LABEL_P (insn))
2554 /* Try to combine the insns I0, I1 and I2 into I3.
2555 Here I0, I1 and I2 appear earlier than I3.
2556 I0 and I1 can be zero; then we combine just I2 into I3, or I1 and I2 into
2559 If we are combining more than two insns and the resulting insn is not
2560 recognized, try splitting it into two insns. If that happens, I2 and I3
2561 are retained and I1/I0 are pseudo-deleted by turning them into a NOTE.
2562 Otherwise, I0, I1 and I2 are pseudo-deleted.
2564 Return 0 if the combination does not work. Then nothing is changed.
2565 If we did the combination, return the insn at which combine should
2568 Set NEW_DIRECT_JUMP_P to a nonzero value if try_combine creates a
2569 new direct jump instruction.
2571 LAST_COMBINED_INSN is either I3, or some insn after I3 that has
2572 been I3 passed to an earlier try_combine within the same basic
2576 try_combine (rtx i3, rtx i2, rtx i1, rtx i0, int *new_direct_jump_p,
2577 rtx last_combined_insn)
2579 /* New patterns for I3 and I2, respectively. */
2580 rtx newpat, newi2pat = 0;
2581 rtvec newpat_vec_with_clobbers = 0;
2582 int substed_i2 = 0, substed_i1 = 0, substed_i0 = 0;
2583 /* Indicates need to preserve SET in I0, I1 or I2 in I3 if it is not
2585 int added_sets_0, added_sets_1, added_sets_2;
2586 /* Total number of SETs to put into I3. */
2588 /* Nonzero if I2's or I1's body now appears in I3. */
2589 int i2_is_used = 0, i1_is_used = 0;
2590 /* INSN_CODEs for new I3, new I2, and user of condition code. */
2591 int insn_code_number, i2_code_number = 0, other_code_number = 0;
2592 /* Contains I3 if the destination of I3 is used in its source, which means
2593 that the old life of I3 is being killed. If that usage is placed into
2594 I2 and not in I3, a REG_DEAD note must be made. */
2595 rtx i3dest_killed = 0;
2596 /* SET_DEST and SET_SRC of I2, I1 and I0. */
2597 rtx i2dest = 0, i2src = 0, i1dest = 0, i1src = 0, i0dest = 0, i0src = 0;
2598 /* Copy of SET_SRC of I1 and I0, if needed. */
2599 rtx i1src_copy = 0, i0src_copy = 0, i0src_copy2 = 0;
2600 /* Set if I2DEST was reused as a scratch register. */
2601 bool i2scratch = false;
2602 /* The PATTERNs of I0, I1, and I2, or a copy of them in certain cases. */
2603 rtx i0pat = 0, i1pat = 0, i2pat = 0;
2604 /* Indicates if I2DEST or I1DEST is in I2SRC or I1_SRC. */
2605 int i2dest_in_i2src = 0, i1dest_in_i1src = 0, i2dest_in_i1src = 0;
2606 int i0dest_in_i0src = 0, i1dest_in_i0src = 0, i2dest_in_i0src = 0;
2607 int i2dest_killed = 0, i1dest_killed = 0, i0dest_killed = 0;
2608 int i1_feeds_i2_n = 0, i0_feeds_i2_n = 0, i0_feeds_i1_n = 0;
2609 /* Notes that must be added to REG_NOTES in I3 and I2. */
2610 rtx new_i3_notes, new_i2_notes;
2611 /* Notes that we substituted I3 into I2 instead of the normal case. */
2612 int i3_subst_into_i2 = 0;
2613 /* Notes that I1, I2 or I3 is a MULT operation. */
2616 int changed_i3_dest = 0;
2620 struct insn_link *link;
2622 rtx new_other_notes;
2625 /* Only try four-insn combinations when there's high likelihood of
2626 success. Look for simple insns, such as loads of constants or
2627 binary operations involving a constant. */
2634 if (!flag_expensive_optimizations)
2637 for (i = 0; i < 4; i++)
2639 rtx insn = i == 0 ? i0 : i == 1 ? i1 : i == 2 ? i2 : i3;
2640 rtx set = single_set (insn);
2644 src = SET_SRC (set);
2645 if (CONSTANT_P (src))
2650 else if (BINARY_P (src) && CONSTANT_P (XEXP (src, 1)))
2652 else if (GET_CODE (src) == ASHIFT || GET_CODE (src) == ASHIFTRT
2653 || GET_CODE (src) == LSHIFTRT)
2656 if (ngood < 2 && nshift < 2)
2660 /* Exit early if one of the insns involved can't be used for
2662 if (cant_combine_insn_p (i3)
2663 || cant_combine_insn_p (i2)
2664 || (i1 && cant_combine_insn_p (i1))
2665 || (i0 && cant_combine_insn_p (i0))
2666 || likely_spilled_retval_p (i3))
2670 undobuf.other_insn = 0;
2672 /* Reset the hard register usage information. */
2673 CLEAR_HARD_REG_SET (newpat_used_regs);
2675 if (dump_file && (dump_flags & TDF_DETAILS))
2678 fprintf (dump_file, "\nTrying %d, %d, %d -> %d:\n",
2679 INSN_UID (i0), INSN_UID (i1), INSN_UID (i2), INSN_UID (i3));
2681 fprintf (dump_file, "\nTrying %d, %d -> %d:\n",
2682 INSN_UID (i1), INSN_UID (i2), INSN_UID (i3));
2684 fprintf (dump_file, "\nTrying %d -> %d:\n",
2685 INSN_UID (i2), INSN_UID (i3));
2688 /* If multiple insns feed into one of I2 or I3, they can be in any
2689 order. To simplify the code below, reorder them in sequence. */
2690 if (i0 && DF_INSN_LUID (i0) > DF_INSN_LUID (i2))
2691 temp = i2, i2 = i0, i0 = temp;
2692 if (i0 && DF_INSN_LUID (i0) > DF_INSN_LUID (i1))
2693 temp = i1, i1 = i0, i0 = temp;
2694 if (i1 && DF_INSN_LUID (i1) > DF_INSN_LUID (i2))
2695 temp = i1, i1 = i2, i2 = temp;
2697 added_links_insn = 0;
2699 /* First check for one important special case that the code below will
2700 not handle. Namely, the case where I1 is zero, I2 is a PARALLEL
2701 and I3 is a SET whose SET_SRC is a SET_DEST in I2. In that case,
2702 we may be able to replace that destination with the destination of I3.
2703 This occurs in the common code where we compute both a quotient and
2704 remainder into a structure, in which case we want to do the computation
2705 directly into the structure to avoid register-register copies.
2707 Note that this case handles both multiple sets in I2 and also cases
2708 where I2 has a number of CLOBBERs inside the PARALLEL.
2710 We make very conservative checks below and only try to handle the
2711 most common cases of this. For example, we only handle the case
2712 where I2 and I3 are adjacent to avoid making difficult register
2715 if (i1 == 0 && NONJUMP_INSN_P (i3) && GET_CODE (PATTERN (i3)) == SET
2716 && REG_P (SET_SRC (PATTERN (i3)))
2717 && REGNO (SET_SRC (PATTERN (i3))) >= FIRST_PSEUDO_REGISTER
2718 && find_reg_note (i3, REG_DEAD, SET_SRC (PATTERN (i3)))
2719 && GET_CODE (PATTERN (i2)) == PARALLEL
2720 && ! side_effects_p (SET_DEST (PATTERN (i3)))
2721 /* If the dest of I3 is a ZERO_EXTRACT or STRICT_LOW_PART, the code
2722 below would need to check what is inside (and reg_overlap_mentioned_p
2723 doesn't support those codes anyway). Don't allow those destinations;
2724 the resulting insn isn't likely to be recognized anyway. */
2725 && GET_CODE (SET_DEST (PATTERN (i3))) != ZERO_EXTRACT
2726 && GET_CODE (SET_DEST (PATTERN (i3))) != STRICT_LOW_PART
2727 && ! reg_overlap_mentioned_p (SET_SRC (PATTERN (i3)),
2728 SET_DEST (PATTERN (i3)))
2729 && next_active_insn (i2) == i3)
2731 rtx p2 = PATTERN (i2);
2733 /* Make sure that the destination of I3,
2734 which we are going to substitute into one output of I2,
2735 is not used within another output of I2. We must avoid making this:
2736 (parallel [(set (mem (reg 69)) ...)
2737 (set (reg 69) ...)])
2738 which is not well-defined as to order of actions.
2739 (Besides, reload can't handle output reloads for this.)
2741 The problem can also happen if the dest of I3 is a memory ref,
2742 if another dest in I2 is an indirect memory ref. */
2743 for (i = 0; i < XVECLEN (p2, 0); i++)
2744 if ((GET_CODE (XVECEXP (p2, 0, i)) == SET
2745 || GET_CODE (XVECEXP (p2, 0, i)) == CLOBBER)
2746 && reg_overlap_mentioned_p (SET_DEST (PATTERN (i3)),
2747 SET_DEST (XVECEXP (p2, 0, i))))
2750 if (i == XVECLEN (p2, 0))
2751 for (i = 0; i < XVECLEN (p2, 0); i++)
2752 if (GET_CODE (XVECEXP (p2, 0, i)) == SET
2753 && SET_DEST (XVECEXP (p2, 0, i)) == SET_SRC (PATTERN (i3)))
2758 subst_low_luid = DF_INSN_LUID (i2);
2760 added_sets_2 = added_sets_1 = added_sets_0 = 0;
2761 i2src = SET_SRC (XVECEXP (p2, 0, i));
2762 i2dest = SET_DEST (XVECEXP (p2, 0, i));
2763 i2dest_killed = dead_or_set_p (i2, i2dest);
2765 /* Replace the dest in I2 with our dest and make the resulting
2766 insn the new pattern for I3. Then skip to where we validate
2767 the pattern. Everything was set up above. */
2768 SUBST (SET_DEST (XVECEXP (p2, 0, i)), SET_DEST (PATTERN (i3)));
2770 i3_subst_into_i2 = 1;
2771 goto validate_replacement;
2775 /* If I2 is setting a pseudo to a constant and I3 is setting some
2776 sub-part of it to another constant, merge them by making a new
2779 && (temp = single_set (i2)) != 0
2780 && (CONST_INT_P (SET_SRC (temp))
2781 || GET_CODE (SET_SRC (temp)) == CONST_DOUBLE)
2782 && GET_CODE (PATTERN (i3)) == SET
2783 && (CONST_INT_P (SET_SRC (PATTERN (i3)))
2784 || GET_CODE (SET_SRC (PATTERN (i3))) == CONST_DOUBLE)
2785 && reg_subword_p (SET_DEST (PATTERN (i3)), SET_DEST (temp)))
2787 rtx dest = SET_DEST (PATTERN (i3));
2791 if (GET_CODE (dest) == ZERO_EXTRACT)
2793 if (CONST_INT_P (XEXP (dest, 1))
2794 && CONST_INT_P (XEXP (dest, 2)))
2796 width = INTVAL (XEXP (dest, 1));
2797 offset = INTVAL (XEXP (dest, 2));
2798 dest = XEXP (dest, 0);
2799 if (BITS_BIG_ENDIAN)
2800 offset = GET_MODE_PRECISION (GET_MODE (dest)) - width - offset;
2805 if (GET_CODE (dest) == STRICT_LOW_PART)
2806 dest = XEXP (dest, 0);
2807 width = GET_MODE_PRECISION (GET_MODE (dest));
2813 /* If this is the low part, we're done. */
2814 if (subreg_lowpart_p (dest))
2816 /* Handle the case where inner is twice the size of outer. */
2817 else if (GET_MODE_PRECISION (GET_MODE (SET_DEST (temp)))
2818 == 2 * GET_MODE_PRECISION (GET_MODE (dest)))
2819 offset += GET_MODE_PRECISION (GET_MODE (dest));
2820 /* Otherwise give up for now. */
2826 && (GET_MODE_PRECISION (GET_MODE (SET_DEST (temp)))
2827 <= HOST_BITS_PER_DOUBLE_INT))
2830 rtx inner = SET_SRC (PATTERN (i3));
2831 rtx outer = SET_SRC (temp);
2833 o = rtx_to_double_int (outer);
2834 i = rtx_to_double_int (inner);
2836 m = double_int_mask (width);
2837 i = double_int_and (i, m);
2838 m = double_int_lshift (m, offset, HOST_BITS_PER_DOUBLE_INT, false);
2839 i = double_int_lshift (i, offset, HOST_BITS_PER_DOUBLE_INT, false);
2840 o = double_int_ior (double_int_and_not (o, m), i);
2844 subst_low_luid = DF_INSN_LUID (i2);
2845 added_sets_2 = added_sets_1 = added_sets_0 = 0;
2846 i2dest = SET_DEST (temp);
2847 i2dest_killed = dead_or_set_p (i2, i2dest);
2849 /* Replace the source in I2 with the new constant and make the
2850 resulting insn the new pattern for I3. Then skip to where we
2851 validate the pattern. Everything was set up above. */
2852 SUBST (SET_SRC (temp),
2853 immed_double_int_const (o, GET_MODE (SET_DEST (temp))));
2855 newpat = PATTERN (i2);
2857 /* The dest of I3 has been replaced with the dest of I2. */
2858 changed_i3_dest = 1;
2859 goto validate_replacement;
2864 /* If we have no I1 and I2 looks like:
2865 (parallel [(set (reg:CC X) (compare:CC OP (const_int 0)))
2867 make up a dummy I1 that is
2870 (set (reg:CC X) (compare:CC Y (const_int 0)))
2872 (We can ignore any trailing CLOBBERs.)
2874 This undoes a previous combination and allows us to match a branch-and-
2877 if (i1 == 0 && GET_CODE (PATTERN (i2)) == PARALLEL
2878 && XVECLEN (PATTERN (i2), 0) >= 2
2879 && GET_CODE (XVECEXP (PATTERN (i2), 0, 0)) == SET
2880 && (GET_MODE_CLASS (GET_MODE (SET_DEST (XVECEXP (PATTERN (i2), 0, 0))))
2882 && GET_CODE (SET_SRC (XVECEXP (PATTERN (i2), 0, 0))) == COMPARE
2883 && XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 1) == const0_rtx
2884 && GET_CODE (XVECEXP (PATTERN (i2), 0, 1)) == SET
2885 && REG_P (SET_DEST (XVECEXP (PATTERN (i2), 0, 1)))
2886 && rtx_equal_p (XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 0),
2887 SET_SRC (XVECEXP (PATTERN (i2), 0, 1))))
2889 for (i = XVECLEN (PATTERN (i2), 0) - 1; i >= 2; i--)
2890 if (GET_CODE (XVECEXP (PATTERN (i2), 0, i)) != CLOBBER)
2895 /* We make I1 with the same INSN_UID as I2. This gives it
2896 the same DF_INSN_LUID for value tracking. Our fake I1 will
2897 never appear in the insn stream so giving it the same INSN_UID
2898 as I2 will not cause a problem. */
2900 i1 = gen_rtx_INSN (VOIDmode, INSN_UID (i2), NULL_RTX, i2,
2901 BLOCK_FOR_INSN (i2), XVECEXP (PATTERN (i2), 0, 1),
2902 INSN_LOCATOR (i2), -1, NULL_RTX);
2904 SUBST (PATTERN (i2), XVECEXP (PATTERN (i2), 0, 0));
2905 SUBST (XEXP (SET_SRC (PATTERN (i2)), 0),
2906 SET_DEST (PATTERN (i1)));
2907 SUBST_LINK (LOG_LINKS (i2), alloc_insn_link (i1, LOG_LINKS (i2)));
2912 /* Verify that I2 and I1 are valid for combining. */
2913 if (! can_combine_p (i2, i3, i0, i1, NULL_RTX, NULL_RTX, &i2dest, &i2src)
2914 || (i1 && ! can_combine_p (i1, i3, i0, NULL_RTX, i2, NULL_RTX,
2916 || (i0 && ! can_combine_p (i0, i3, NULL_RTX, NULL_RTX, i1, i2,
2923 /* Record whether I2DEST is used in I2SRC and similarly for the other
2924 cases. Knowing this will help in register status updating below. */
2925 i2dest_in_i2src = reg_overlap_mentioned_p (i2dest, i2src);
2926 i1dest_in_i1src = i1 && reg_overlap_mentioned_p (i1dest, i1src);
2927 i2dest_in_i1src = i1 && reg_overlap_mentioned_p (i2dest, i1src);
2928 i0dest_in_i0src = i0 && reg_overlap_mentioned_p (i0dest, i0src);
2929 i1dest_in_i0src = i0 && reg_overlap_mentioned_p (i1dest, i0src);
2930 i2dest_in_i0src = i0 && reg_overlap_mentioned_p (i2dest, i0src);
2931 i2dest_killed = dead_or_set_p (i2, i2dest);
2932 i1dest_killed = i1 && dead_or_set_p (i1, i1dest);
2933 i0dest_killed = i0 && dead_or_set_p (i0, i0dest);
2935 /* For the earlier insns, determine which of the subsequent ones they
2937 i1_feeds_i2_n = i1 && insn_a_feeds_b (i1, i2);
2938 i0_feeds_i1_n = i0 && insn_a_feeds_b (i0, i1);
2939 i0_feeds_i2_n = (i0 && (!i0_feeds_i1_n ? insn_a_feeds_b (i0, i2)
2940 : (!reg_overlap_mentioned_p (i1dest, i0dest)
2941 && reg_overlap_mentioned_p (i0dest, i2src))));
2943 /* Ensure that I3's pattern can be the destination of combines. */
2944 if (! combinable_i3pat (i3, &PATTERN (i3), i2dest, i1dest, i0dest,
2945 i1 && i2dest_in_i1src && !i1_feeds_i2_n,
2946 i0 && ((i2dest_in_i0src && !i0_feeds_i2_n)
2947 || (i1dest_in_i0src && !i0_feeds_i1_n)),
2954 /* See if any of the insns is a MULT operation. Unless one is, we will
2955 reject a combination that is, since it must be slower. Be conservative
2957 if (GET_CODE (i2src) == MULT
2958 || (i1 != 0 && GET_CODE (i1src) == MULT)
2959 || (i0 != 0 && GET_CODE (i0src) == MULT)
2960 || (GET_CODE (PATTERN (i3)) == SET
2961 && GET_CODE (SET_SRC (PATTERN (i3))) == MULT))
2964 /* If I3 has an inc, then give up if I1 or I2 uses the reg that is inc'd.
2965 We used to do this EXCEPT in one case: I3 has a post-inc in an
2966 output operand. However, that exception can give rise to insns like
2968 which is a famous insn on the PDP-11 where the value of r3 used as the
2969 source was model-dependent. Avoid this sort of thing. */
2972 if (!(GET_CODE (PATTERN (i3)) == SET
2973 && REG_P (SET_SRC (PATTERN (i3)))
2974 && MEM_P (SET_DEST (PATTERN (i3)))
2975 && (GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_INC
2976 || GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_DEC)))
2977 /* It's not the exception. */
2982 for (link = REG_NOTES (i3); link; link = XEXP (link, 1))
2983 if (REG_NOTE_KIND (link) == REG_INC
2984 && (reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i2))
2986 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i1)))))
2994 /* See if the SETs in I1 or I2 need to be kept around in the merged
2995 instruction: whenever the value set there is still needed past I3.
2996 For the SETs in I2, this is easy: we see if I2DEST dies or is set in I3.
2998 For the SET in I1, we have two cases: If I1 and I2 independently
2999 feed into I3, the set in I1 needs to be kept around if I1DEST dies
3000 or is set in I3. Otherwise (if I1 feeds I2 which feeds I3), the set
3001 in I1 needs to be kept around unless I1DEST dies or is set in either
3002 I2 or I3. The same consideration applies to I0. */
3004 added_sets_2 = !dead_or_set_p (i3, i2dest);
3007 added_sets_1 = !(dead_or_set_p (i3, i1dest)
3008 || (i1_feeds_i2_n && dead_or_set_p (i2, i1dest)));
3013 added_sets_0 = !(dead_or_set_p (i3, i0dest)
3014 || (i0_feeds_i2_n && dead_or_set_p (i2, i0dest))
3015 || (i0_feeds_i1_n && dead_or_set_p (i1, i0dest)));
3019 /* We are about to copy insns for the case where they need to be kept
3020 around. Check that they can be copied in the merged instruction. */
3022 if (targetm.cannot_copy_insn_p
3023 && ((added_sets_2 && targetm.cannot_copy_insn_p (i2))
3024 || (i1 && added_sets_1 && targetm.cannot_copy_insn_p (i1))
3025 || (i0 && added_sets_0 && targetm.cannot_copy_insn_p (i0))))
3031 /* If the set in I2 needs to be kept around, we must make a copy of
3032 PATTERN (I2), so that when we substitute I1SRC for I1DEST in
3033 PATTERN (I2), we are only substituting for the original I1DEST, not into
3034 an already-substituted copy. This also prevents making self-referential
3035 rtx. If I2 is a PARALLEL, we just need the piece that assigns I2SRC to
3040 if (GET_CODE (PATTERN (i2)) == PARALLEL)
3041 i2pat = gen_rtx_SET (VOIDmode, i2dest, copy_rtx (i2src));
3043 i2pat = copy_rtx (PATTERN (i2));
3048 if (GET_CODE (PATTERN (i1)) == PARALLEL)
3049 i1pat = gen_rtx_SET (VOIDmode, i1dest, copy_rtx (i1src));
3051 i1pat = copy_rtx (PATTERN (i1));
3056 if (GET_CODE (PATTERN (i0)) == PARALLEL)
3057 i0pat = gen_rtx_SET (VOIDmode, i0dest, copy_rtx (i0src));
3059 i0pat = copy_rtx (PATTERN (i0));
3064 /* Substitute in the latest insn for the regs set by the earlier ones. */
3066 maxreg = max_reg_num ();
3071 /* Many machines that don't use CC0 have insns that can both perform an
3072 arithmetic operation and set the condition code. These operations will
3073 be represented as a PARALLEL with the first element of the vector
3074 being a COMPARE of an arithmetic operation with the constant zero.
3075 The second element of the vector will set some pseudo to the result
3076 of the same arithmetic operation. If we simplify the COMPARE, we won't
3077 match such a pattern and so will generate an extra insn. Here we test
3078 for this case, where both the comparison and the operation result are
3079 needed, and make the PARALLEL by just replacing I2DEST in I3SRC with
3080 I2SRC. Later we will make the PARALLEL that contains I2. */
3082 if (i1 == 0 && added_sets_2 && GET_CODE (PATTERN (i3)) == SET
3083 && GET_CODE (SET_SRC (PATTERN (i3))) == COMPARE
3084 && CONST_INT_P (XEXP (SET_SRC (PATTERN (i3)), 1))
3085 && rtx_equal_p (XEXP (SET_SRC (PATTERN (i3)), 0), i2dest))
3088 rtx *cc_use_loc = NULL, cc_use_insn = NULL_RTX;
3089 rtx op0 = i2src, op1 = XEXP (SET_SRC (PATTERN (i3)), 1);
3090 enum machine_mode compare_mode, orig_compare_mode;
3091 enum rtx_code compare_code = UNKNOWN, orig_compare_code = UNKNOWN;
3093 newpat = PATTERN (i3);
3094 newpat_dest = SET_DEST (newpat);
3095 compare_mode = orig_compare_mode = GET_MODE (newpat_dest);
3097 if (undobuf.other_insn == 0
3098 && (cc_use_loc = find_single_use (SET_DEST (newpat), i3,
3101 compare_code = orig_compare_code = GET_CODE (*cc_use_loc);
3102 compare_code = simplify_compare_const (compare_code,
3104 #ifdef CANONICALIZE_COMPARISON
3105 CANONICALIZE_COMPARISON (compare_code, op0, op1);
3109 /* Do the rest only if op1 is const0_rtx, which may be the
3110 result of simplification. */
3111 if (op1 == const0_rtx)
3113 /* If a single use of the CC is found, prepare to modify it
3114 when SELECT_CC_MODE returns a new CC-class mode, or when
3115 the above simplify_compare_const() returned a new comparison
3116 operator. undobuf.other_insn is assigned the CC use insn
3117 when modifying it. */
3120 #ifdef SELECT_CC_MODE
3121 enum machine_mode new_mode
3122 = SELECT_CC_MODE (compare_code, op0, op1);
3123 if (new_mode != orig_compare_mode
3124 && can_change_dest_mode (SET_DEST (newpat),
3125 added_sets_2, new_mode))
3127 unsigned int regno = REGNO (newpat_dest);
3128 compare_mode = new_mode;
3129 if (regno < FIRST_PSEUDO_REGISTER)
3130 newpat_dest = gen_rtx_REG (compare_mode, regno);
3133 SUBST_MODE (regno_reg_rtx[regno], compare_mode);
3134 newpat_dest = regno_reg_rtx[regno];
3138 /* Cases for modifying the CC-using comparison. */
3139 if (compare_code != orig_compare_code
3140 /* ??? Do we need to verify the zero rtx? */
3141 && XEXP (*cc_use_loc, 1) == const0_rtx)
3143 /* Replace cc_use_loc with entire new RTX. */
3145 gen_rtx_fmt_ee (compare_code, compare_mode,
3146 newpat_dest, const0_rtx));
3147 undobuf.other_insn = cc_use_insn;
3149 else if (compare_mode != orig_compare_mode)
3151 /* Just replace the CC reg with a new mode. */
3152 SUBST (XEXP (*cc_use_loc, 0), newpat_dest);
3153 undobuf.other_insn = cc_use_insn;
3157 /* Now we modify the current newpat:
3158 First, SET_DEST(newpat) is updated if the CC mode has been
3159 altered. For targets without SELECT_CC_MODE, this should be
3161 if (compare_mode != orig_compare_mode)
3162 SUBST (SET_DEST (newpat), newpat_dest);
3163 /* This is always done to propagate i2src into newpat. */
3164 SUBST (SET_SRC (newpat),
3165 gen_rtx_COMPARE (compare_mode, op0, op1));
3166 /* Create new version of i2pat if needed; the below PARALLEL
3167 creation needs this to work correctly. */
3168 if (! rtx_equal_p (i2src, op0))
3169 i2pat = gen_rtx_SET (VOIDmode, i2dest, op0);
3175 if (i2_is_used == 0)
3177 /* It is possible that the source of I2 or I1 may be performing
3178 an unneeded operation, such as a ZERO_EXTEND of something
3179 that is known to have the high part zero. Handle that case
3180 by letting subst look at the inner insns.
3182 Another way to do this would be to have a function that tries
3183 to simplify a single insn instead of merging two or more
3184 insns. We don't do this because of the potential of infinite
3185 loops and because of the potential extra memory required.
3186 However, doing it the way we are is a bit of a kludge and
3187 doesn't catch all cases.
3189 But only do this if -fexpensive-optimizations since it slows
3190 things down and doesn't usually win.
3192 This is not done in the COMPARE case above because the
3193 unmodified I2PAT is used in the PARALLEL and so a pattern
3194 with a modified I2SRC would not match. */
3196 if (flag_expensive_optimizations)
3198 /* Pass pc_rtx so no substitutions are done, just
3202 subst_low_luid = DF_INSN_LUID (i1);
3203 i1src = subst (i1src, pc_rtx, pc_rtx, 0, 0, 0);
3206 subst_low_luid = DF_INSN_LUID (i2);
3207 i2src = subst (i2src, pc_rtx, pc_rtx, 0, 0, 0);
3210 n_occurrences = 0; /* `subst' counts here */
3211 subst_low_luid = DF_INSN_LUID (i2);
3213 /* If I1 feeds into I2 and I1DEST is in I1SRC, we need to make a unique
3214 copy of I2SRC each time we substitute it, in order to avoid creating
3215 self-referential RTL when we will be substituting I1SRC for I1DEST
3216 later. Likewise if I0 feeds into I2, either directly or indirectly
3217 through I1, and I0DEST is in I0SRC. */
3218 newpat = subst (PATTERN (i3), i2dest, i2src, 0, 0,
3219 (i1_feeds_i2_n && i1dest_in_i1src)
3220 || ((i0_feeds_i2_n || (i0_feeds_i1_n && i1_feeds_i2_n))
3221 && i0dest_in_i0src));
3224 /* Record whether I2's body now appears within I3's body. */
3225 i2_is_used = n_occurrences;
3228 /* If we already got a failure, don't try to do more. Otherwise, try to
3229 substitute I1 if we have it. */
3231 if (i1 && GET_CODE (newpat) != CLOBBER)
3233 /* Check that an autoincrement side-effect on I1 has not been lost.
3234 This happens if I1DEST is mentioned in I2 and dies there, and
3235 has disappeared from the new pattern. */
3236 if ((FIND_REG_INC_NOTE (i1, NULL_RTX) != 0
3238 && dead_or_set_p (i2, i1dest)
3239 && !reg_overlap_mentioned_p (i1dest, newpat))
3240 /* Before we can do this substitution, we must redo the test done
3241 above (see detailed comments there) that ensures I1DEST isn't
3242 mentioned in any SETs in NEWPAT that are field assignments. */
3243 || !combinable_i3pat (NULL_RTX, &newpat, i1dest, NULL_RTX, NULL_RTX,
3251 subst_low_luid = DF_INSN_LUID (i1);
3253 /* If the following substitution will modify I1SRC, make a copy of it
3254 for the case where it is substituted for I1DEST in I2PAT later. */
3255 if (added_sets_2 && i1_feeds_i2_n)
3256 i1src_copy = copy_rtx (i1src);
3258 /* If I0 feeds into I1 and I0DEST is in I0SRC, we need to make a unique
3259 copy of I1SRC each time we substitute it, in order to avoid creating
3260 self-referential RTL when we will be substituting I0SRC for I0DEST
3262 newpat = subst (newpat, i1dest, i1src, 0, 0,
3263 i0_feeds_i1_n && i0dest_in_i0src);
3266 /* Record whether I1's body now appears within I3's body. */
3267 i1_is_used = n_occurrences;
3270 /* Likewise for I0 if we have it. */
3272 if (i0 && GET_CODE (newpat) != CLOBBER)
3274 if ((FIND_REG_INC_NOTE (i0, NULL_RTX) != 0
3275 && ((i0_feeds_i2_n && dead_or_set_p (i2, i0dest))
3276 || (i0_feeds_i1_n && dead_or_set_p (i1, i0dest)))
3277 && !reg_overlap_mentioned_p (i0dest, newpat))
3278 || !combinable_i3pat (NULL_RTX, &newpat, i0dest, NULL_RTX, NULL_RTX,
3285 /* If the following substitution will modify I0SRC, make a copy of it
3286 for the case where it is substituted for I0DEST in I1PAT later. */
3287 if (added_sets_1 && i0_feeds_i1_n)
3288 i0src_copy = copy_rtx (i0src);
3289 /* And a copy for I0DEST in I2PAT substitution. */
3290 if (added_sets_2 && ((i0_feeds_i1_n && i1_feeds_i2_n)
3291 || (i0_feeds_i2_n)))
3292 i0src_copy2 = copy_rtx (i0src);
3295 subst_low_luid = DF_INSN_LUID (i0);
3296 newpat = subst (newpat, i0dest, i0src, 0, 0, 0);
3300 /* Fail if an autoincrement side-effect has been duplicated. Be careful
3301 to count all the ways that I2SRC and I1SRC can be used. */
3302 if ((FIND_REG_INC_NOTE (i2, NULL_RTX) != 0
3303 && i2_is_used + added_sets_2 > 1)
3304 || (i1 != 0 && FIND_REG_INC_NOTE (i1, NULL_RTX) != 0
3305 && (i1_is_used + added_sets_1 + (added_sets_2 && i1_feeds_i2_n)
3307 || (i0 != 0 && FIND_REG_INC_NOTE (i0, NULL_RTX) != 0
3308 && (n_occurrences + added_sets_0
3309 + (added_sets_1 && i0_feeds_i1_n)
3310 + (added_sets_2 && i0_feeds_i2_n)
3312 /* Fail if we tried to make a new register. */
3313 || max_reg_num () != maxreg
3314 /* Fail if we couldn't do something and have a CLOBBER. */
3315 || GET_CODE (newpat) == CLOBBER
3316 /* Fail if this new pattern is a MULT and we didn't have one before
3317 at the outer level. */
3318 || (GET_CODE (newpat) == SET && GET_CODE (SET_SRC (newpat)) == MULT
3325 /* If the actions of the earlier insns must be kept
3326 in addition to substituting them into the latest one,
3327 we must make a new PARALLEL for the latest insn
3328 to hold additional the SETs. */
3330 if (added_sets_0 || added_sets_1 || added_sets_2)
3332 int extra_sets = added_sets_0 + added_sets_1 + added_sets_2;
3335 if (GET_CODE (newpat) == PARALLEL)
3337 rtvec old = XVEC (newpat, 0);
3338 total_sets = XVECLEN (newpat, 0) + extra_sets;
3339 newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (total_sets));
3340 memcpy (XVEC (newpat, 0)->elem, &old->elem[0],
3341 sizeof (old->elem[0]) * old->num_elem);
3346 total_sets = 1 + extra_sets;
3347 newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (total_sets));
3348 XVECEXP (newpat, 0, 0) = old;
3352 XVECEXP (newpat, 0, --total_sets) = i0pat;
3358 t = subst (t, i0dest, i0src_copy ? i0src_copy : i0src, 0, 0, 0);
3360 XVECEXP (newpat, 0, --total_sets) = t;
3366 t = subst (t, i1dest, i1src_copy ? i1src_copy : i1src, 0, 0,
3367 i0_feeds_i1_n && i0dest_in_i0src);
3368 if ((i0_feeds_i1_n && i1_feeds_i2_n) || i0_feeds_i2_n)
3369 t = subst (t, i0dest, i0src_copy2 ? i0src_copy2 : i0src, 0, 0, 0);
3371 XVECEXP (newpat, 0, --total_sets) = t;
3375 validate_replacement:
3377 /* Note which hard regs this insn has as inputs. */
3378 mark_used_regs_combine (newpat);
3380 /* If recog_for_combine fails, it strips existing clobbers. If we'll
3381 consider splitting this pattern, we might need these clobbers. */
3382 if (i1 && GET_CODE (newpat) == PARALLEL
3383 && GET_CODE (XVECEXP (newpat, 0, XVECLEN (newpat, 0) - 1)) == CLOBBER)
3385 int len = XVECLEN (newpat, 0);
3387 newpat_vec_with_clobbers = rtvec_alloc (len);
3388 for (i = 0; i < len; i++)
3389 RTVEC_ELT (newpat_vec_with_clobbers, i) = XVECEXP (newpat, 0, i);
3392 /* Is the result of combination a valid instruction? */
3393 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
3395 /* If the result isn't valid, see if it is a PARALLEL of two SETs where
3396 the second SET's destination is a register that is unused and isn't
3397 marked as an instruction that might trap in an EH region. In that case,
3398 we just need the first SET. This can occur when simplifying a divmod
3399 insn. We *must* test for this case here because the code below that
3400 splits two independent SETs doesn't handle this case correctly when it
3401 updates the register status.
3403 It's pointless doing this if we originally had two sets, one from
3404 i3, and one from i2. Combining then splitting the parallel results
3405 in the original i2 again plus an invalid insn (which we delete).
3406 The net effect is only to move instructions around, which makes
3407 debug info less accurate.
3409 Also check the case where the first SET's destination is unused.
3410 That would not cause incorrect code, but does cause an unneeded
3413 if (insn_code_number < 0
3414 && !(added_sets_2 && i1 == 0)
3415 && GET_CODE (newpat) == PARALLEL
3416 && XVECLEN (newpat, 0) == 2
3417 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
3418 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
3419 && asm_noperands (newpat) < 0)
3421 rtx set0 = XVECEXP (newpat, 0, 0);
3422 rtx set1 = XVECEXP (newpat, 0, 1);
3424 if (((REG_P (SET_DEST (set1))
3425 && find_reg_note (i3, REG_UNUSED, SET_DEST (set1)))
3426 || (GET_CODE (SET_DEST (set1)) == SUBREG
3427 && find_reg_note (i3, REG_UNUSED, SUBREG_REG (SET_DEST (set1)))))
3428 && insn_nothrow_p (i3)
3429 && !side_effects_p (SET_SRC (set1)))
3432 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
3435 else if (((REG_P (SET_DEST (set0))
3436 && find_reg_note (i3, REG_UNUSED, SET_DEST (set0)))
3437 || (GET_CODE (SET_DEST (set0)) == SUBREG
3438 && find_reg_note (i3, REG_UNUSED,
3439 SUBREG_REG (SET_DEST (set0)))))
3440 && insn_nothrow_p (i3)
3441 && !side_effects_p (SET_SRC (set0)))
3444 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
3446 if (insn_code_number >= 0)
3447 changed_i3_dest = 1;
3451 /* If we were combining three insns and the result is a simple SET
3452 with no ASM_OPERANDS that wasn't recognized, try to split it into two
3453 insns. There are two ways to do this. It can be split using a
3454 machine-specific method (like when you have an addition of a large
3455 constant) or by combine in the function find_split_point. */
3457 if (i1 && insn_code_number < 0 && GET_CODE (newpat) == SET
3458 && asm_noperands (newpat) < 0)
3460 rtx parallel, m_split, *split;
3462 /* See if the MD file can split NEWPAT. If it can't, see if letting it
3463 use I2DEST as a scratch register will help. In the latter case,
3464 convert I2DEST to the mode of the source of NEWPAT if we can. */
3466 m_split = combine_split_insns (newpat, i3);
3468 /* We can only use I2DEST as a scratch reg if it doesn't overlap any
3469 inputs of NEWPAT. */
3471 /* ??? If I2DEST is not safe, and I1DEST exists, then it would be
3472 possible to try that as a scratch reg. This would require adding
3473 more code to make it work though. */
3475 if (m_split == 0 && ! reg_overlap_mentioned_p (i2dest, newpat))
3477 enum machine_mode new_mode = GET_MODE (SET_DEST (newpat));
3479 /* First try to split using the original register as a
3480 scratch register. */
3481 parallel = gen_rtx_PARALLEL (VOIDmode,
3482 gen_rtvec (2, newpat,
3483 gen_rtx_CLOBBER (VOIDmode,
3485 m_split = combine_split_insns (parallel, i3);
3487 /* If that didn't work, try changing the mode of I2DEST if
3490 && new_mode != GET_MODE (i2dest)
3491 && new_mode != VOIDmode
3492 && can_change_dest_mode (i2dest, added_sets_2, new_mode))
3494 enum machine_mode old_mode = GET_MODE (i2dest);
3497 if (REGNO (i2dest) < FIRST_PSEUDO_REGISTER)
3498 ni2dest = gen_rtx_REG (new_mode, REGNO (i2dest));
3501 SUBST_MODE (regno_reg_rtx[REGNO (i2dest)], new_mode);
3502 ni2dest = regno_reg_rtx[REGNO (i2dest)];
3505 parallel = (gen_rtx_PARALLEL
3507 gen_rtvec (2, newpat,
3508 gen_rtx_CLOBBER (VOIDmode,
3510 m_split = combine_split_insns (parallel, i3);
3513 && REGNO (i2dest) >= FIRST_PSEUDO_REGISTER)
3517 adjust_reg_mode (regno_reg_rtx[REGNO (i2dest)], old_mode);
3518 buf = undobuf.undos;
3519 undobuf.undos = buf->next;
3520 buf->next = undobuf.frees;
3521 undobuf.frees = buf;
3525 i2scratch = m_split != 0;
3528 /* If recog_for_combine has discarded clobbers, try to use them
3529 again for the split. */
3530 if (m_split == 0 && newpat_vec_with_clobbers)
3532 parallel = gen_rtx_PARALLEL (VOIDmode, newpat_vec_with_clobbers);
3533 m_split = combine_split_insns (parallel, i3);
3536 if (m_split && NEXT_INSN (m_split) == NULL_RTX)
3538 m_split = PATTERN (m_split);
3539 insn_code_number = recog_for_combine (&m_split, i3, &new_i3_notes);
3540 if (insn_code_number >= 0)
3543 else if (m_split && NEXT_INSN (NEXT_INSN (m_split)) == NULL_RTX
3544 && (next_nonnote_nondebug_insn (i2) == i3
3545 || ! use_crosses_set_p (PATTERN (m_split), DF_INSN_LUID (i2))))
3548 rtx newi3pat = PATTERN (NEXT_INSN (m_split));
3549 newi2pat = PATTERN (m_split);
3551 i3set = single_set (NEXT_INSN (m_split));
3552 i2set = single_set (m_split);
3554 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
3556 /* If I2 or I3 has multiple SETs, we won't know how to track
3557 register status, so don't use these insns. If I2's destination
3558 is used between I2 and I3, we also can't use these insns. */
3560 if (i2_code_number >= 0 && i2set && i3set
3561 && (next_nonnote_nondebug_insn (i2) == i3
3562 || ! reg_used_between_p (SET_DEST (i2set), i2, i3)))
3563 insn_code_number = recog_for_combine (&newi3pat, i3,
3565 if (insn_code_number >= 0)
3568 /* It is possible that both insns now set the destination of I3.
3569 If so, we must show an extra use of it. */
3571 if (insn_code_number >= 0)
3573 rtx new_i3_dest = SET_DEST (i3set);
3574 rtx new_i2_dest = SET_DEST (i2set);
3576 while (GET_CODE (new_i3_dest) == ZERO_EXTRACT
3577 || GET_CODE (new_i3_dest) == STRICT_LOW_PART
3578 || GET_CODE (new_i3_dest) == SUBREG)
3579 new_i3_dest = XEXP (new_i3_dest, 0);
3581 while (GET_CODE (new_i2_dest) == ZERO_EXTRACT
3582 || GET_CODE (new_i2_dest) == STRICT_LOW_PART
3583 || GET_CODE (new_i2_dest) == SUBREG)
3584 new_i2_dest = XEXP (new_i2_dest, 0);
3586 if (REG_P (new_i3_dest)
3587 && REG_P (new_i2_dest)
3588 && REGNO (new_i3_dest) == REGNO (new_i2_dest))
3589 INC_REG_N_SETS (REGNO (new_i2_dest), 1);
3593 /* If we can split it and use I2DEST, go ahead and see if that
3594 helps things be recognized. Verify that none of the registers
3595 are set between I2 and I3. */
3596 if (insn_code_number < 0
3597 && (split = find_split_point (&newpat, i3, false)) != 0
3601 /* We need I2DEST in the proper mode. If it is a hard register
3602 or the only use of a pseudo, we can change its mode.
3603 Make sure we don't change a hard register to have a mode that
3604 isn't valid for it, or change the number of registers. */
3605 && (GET_MODE (*split) == GET_MODE (i2dest)
3606 || GET_MODE (*split) == VOIDmode
3607 || can_change_dest_mode (i2dest, added_sets_2,
3609 && (next_nonnote_nondebug_insn (i2) == i3
3610 || ! use_crosses_set_p (*split, DF_INSN_LUID (i2)))
3611 /* We can't overwrite I2DEST if its value is still used by
3613 && ! reg_referenced_p (i2dest, newpat))
3615 rtx newdest = i2dest;
3616 enum rtx_code split_code = GET_CODE (*split);
3617 enum machine_mode split_mode = GET_MODE (*split);
3618 bool subst_done = false;
3619 newi2pat = NULL_RTX;
3623 /* *SPLIT may be part of I2SRC, so make sure we have the
3624 original expression around for later debug processing.
3625 We should not need I2SRC any more in other cases. */
3626 if (MAY_HAVE_DEBUG_INSNS)
3627 i2src = copy_rtx (i2src);
3631 /* Get NEWDEST as a register in the proper mode. We have already
3632 validated that we can do this. */
3633 if (GET_MODE (i2dest) != split_mode && split_mode != VOIDmode)
3635 if (REGNO (i2dest) < FIRST_PSEUDO_REGISTER)
3636 newdest = gen_rtx_REG (split_mode, REGNO (i2dest));
3639 SUBST_MODE (regno_reg_rtx[REGNO (i2dest)], split_mode);
3640 newdest = regno_reg_rtx[REGNO (i2dest)];
3644 /* If *SPLIT is a (mult FOO (const_int pow2)), convert it to
3645 an ASHIFT. This can occur if it was inside a PLUS and hence
3646 appeared to be a memory address. This is a kludge. */
3647 if (split_code == MULT
3648 && CONST_INT_P (XEXP (*split, 1))
3649 && INTVAL (XEXP (*split, 1)) > 0
3650 && (i = exact_log2 (UINTVAL (XEXP (*split, 1)))) >= 0)
3652 SUBST (*split, gen_rtx_ASHIFT (split_mode,
3653 XEXP (*split, 0), GEN_INT (i)));
3654 /* Update split_code because we may not have a multiply
3656 split_code = GET_CODE (*split);
3659 #ifdef INSN_SCHEDULING
3660 /* If *SPLIT is a paradoxical SUBREG, when we split it, it should
3661 be written as a ZERO_EXTEND. */
3662 if (split_code == SUBREG && MEM_P (SUBREG_REG (*split)))
3664 #ifdef LOAD_EXTEND_OP
3665 /* Or as a SIGN_EXTEND if LOAD_EXTEND_OP says that that's
3666 what it really is. */
3667 if (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (*split)))
3669 SUBST (*split, gen_rtx_SIGN_EXTEND (split_mode,
3670 SUBREG_REG (*split)));
3673 SUBST (*split, gen_rtx_ZERO_EXTEND (split_mode,
3674 SUBREG_REG (*split)));
3678 /* Attempt to split binary operators using arithmetic identities. */
3679 if (BINARY_P (SET_SRC (newpat))
3680 && split_mode == GET_MODE (SET_SRC (newpat))
3681 && ! side_effects_p (SET_SRC (newpat)))
3683 rtx setsrc = SET_SRC (newpat);
3684 enum machine_mode mode = GET_MODE (setsrc);
3685 enum rtx_code code = GET_CODE (setsrc);
3686 rtx src_op0 = XEXP (setsrc, 0);
3687 rtx src_op1 = XEXP (setsrc, 1);
3689 /* Split "X = Y op Y" as "Z = Y; X = Z op Z". */
3690 if (rtx_equal_p (src_op0, src_op1))
3692 newi2pat = gen_rtx_SET (VOIDmode, newdest, src_op0);
3693 SUBST (XEXP (setsrc, 0), newdest);
3694 SUBST (XEXP (setsrc, 1), newdest);
3697 /* Split "((P op Q) op R) op S" where op is PLUS or MULT. */
3698 else if ((code == PLUS || code == MULT)
3699 && GET_CODE (src_op0) == code
3700 && GET_CODE (XEXP (src_op0, 0)) == code
3701 && (INTEGRAL_MODE_P (mode)
3702 || (FLOAT_MODE_P (mode)
3703 && flag_unsafe_math_optimizations)))
3705 rtx p = XEXP (XEXP (src_op0, 0), 0);
3706 rtx q = XEXP (XEXP (src_op0, 0), 1);
3707 rtx r = XEXP (src_op0, 1);
3710 /* Split both "((X op Y) op X) op Y" and
3711 "((X op Y) op Y) op X" as "T op T" where T is
3713 if ((rtx_equal_p (p,r) && rtx_equal_p (q,s))
3714 || (rtx_equal_p (p,s) && rtx_equal_p (q,r)))
3716 newi2pat = gen_rtx_SET (VOIDmode, newdest,
3718 SUBST (XEXP (setsrc, 0), newdest);
3719 SUBST (XEXP (setsrc, 1), newdest);
3722 /* Split "((X op X) op Y) op Y)" as "T op T" where
3724 else if (rtx_equal_p (p,q) && rtx_equal_p (r,s))
3726 rtx tmp = simplify_gen_binary (code, mode, p, r);
3727 newi2pat = gen_rtx_SET (VOIDmode, newdest, tmp);
3728 SUBST (XEXP (setsrc, 0), newdest);
3729 SUBST (XEXP (setsrc, 1), newdest);
3737 newi2pat = gen_rtx_SET (VOIDmode, newdest, *split);
3738 SUBST (*split, newdest);
3741 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
3743 /* recog_for_combine might have added CLOBBERs to newi2pat.
3744 Make sure NEWPAT does not depend on the clobbered regs. */
3745 if (GET_CODE (newi2pat) == PARALLEL)
3746 for (i = XVECLEN (newi2pat, 0) - 1; i >= 0; i--)
3747 if (GET_CODE (XVECEXP (newi2pat, 0, i)) == CLOBBER)
3749 rtx reg = XEXP (XVECEXP (newi2pat, 0, i), 0);
3750 if (reg_overlap_mentioned_p (reg, newpat))
3757 /* If the split point was a MULT and we didn't have one before,
3758 don't use one now. */
3759 if (i2_code_number >= 0 && ! (split_code == MULT && ! have_mult))
3760 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
3764 /* Check for a case where we loaded from memory in a narrow mode and
3765 then sign extended it, but we need both registers. In that case,
3766 we have a PARALLEL with both loads from the same memory location.
3767 We can split this into a load from memory followed by a register-register
3768 copy. This saves at least one insn, more if register allocation can
3771 We cannot do this if the destination of the first assignment is a
3772 condition code register or cc0. We eliminate this case by making sure
3773 the SET_DEST and SET_SRC have the same mode.
3775 We cannot do this if the destination of the second assignment is
3776 a register that we have already assumed is zero-extended. Similarly
3777 for a SUBREG of such a register. */
3779 else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0
3780 && GET_CODE (newpat) == PARALLEL
3781 && XVECLEN (newpat, 0) == 2
3782 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
3783 && GET_CODE (SET_SRC (XVECEXP (newpat, 0, 0))) == SIGN_EXTEND
3784 && (GET_MODE (SET_DEST (XVECEXP (newpat, 0, 0)))
3785 == GET_MODE (SET_SRC (XVECEXP (newpat, 0, 0))))
3786 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
3787 && rtx_equal_p (SET_SRC (XVECEXP (newpat, 0, 1)),
3788 XEXP (SET_SRC (XVECEXP (newpat, 0, 0)), 0))
3789 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)),
3791 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
3792 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
3793 && ! (temp = SET_DEST (XVECEXP (newpat, 0, 1)),
3795 && VEC_index (reg_stat_type, reg_stat,
3796 REGNO (temp))->nonzero_bits != 0
3797 && GET_MODE_PRECISION (GET_MODE (temp)) < BITS_PER_WORD
3798 && GET_MODE_PRECISION (GET_MODE (temp)) < HOST_BITS_PER_INT
3799 && (VEC_index (reg_stat_type, reg_stat,
3800 REGNO (temp))->nonzero_bits
3801 != GET_MODE_MASK (word_mode))))
3802 && ! (GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) == SUBREG
3803 && (temp = SUBREG_REG (SET_DEST (XVECEXP (newpat, 0, 1))),
3805 && VEC_index (reg_stat_type, reg_stat,
3806 REGNO (temp))->nonzero_bits != 0
3807 && GET_MODE_PRECISION (GET_MODE (temp)) < BITS_PER_WORD
3808 && GET_MODE_PRECISION (GET_MODE (temp)) < HOST_BITS_PER_INT
3809 && (VEC_index (reg_stat_type, reg_stat,
3810 REGNO (temp))->nonzero_bits
3811 != GET_MODE_MASK (word_mode)))))
3812 && ! reg_overlap_mentioned_p (SET_DEST (XVECEXP (newpat, 0, 1)),
3813 SET_SRC (XVECEXP (newpat, 0, 1)))
3814 && ! find_reg_note (i3, REG_UNUSED,
3815 SET_DEST (XVECEXP (newpat, 0, 0))))
3819 newi2pat = XVECEXP (newpat, 0, 0);
3820 ni2dest = SET_DEST (XVECEXP (newpat, 0, 0));
3821 newpat = XVECEXP (newpat, 0, 1);
3822 SUBST (SET_SRC (newpat),
3823 gen_lowpart (GET_MODE (SET_SRC (newpat)), ni2dest));
3824 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
3826 if (i2_code_number >= 0)
3827 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
3829 if (insn_code_number >= 0)
3833 /* Similarly, check for a case where we have a PARALLEL of two independent
3834 SETs but we started with three insns. In this case, we can do the sets
3835 as two separate insns. This case occurs when some SET allows two
3836 other insns to combine, but the destination of that SET is still live. */
3838 else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0
3839 && GET_CODE (newpat) == PARALLEL
3840 && XVECLEN (newpat, 0) == 2
3841 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
3842 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != ZERO_EXTRACT
3843 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != STRICT_LOW_PART
3844 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
3845 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
3846 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
3847 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 1)),
3848 XVECEXP (newpat, 0, 0))
3849 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 0)),
3850 XVECEXP (newpat, 0, 1))
3851 && ! (contains_muldiv (SET_SRC (XVECEXP (newpat, 0, 0)))
3852 && contains_muldiv (SET_SRC (XVECEXP (newpat, 0, 1)))))
3854 /* Normally, it doesn't matter which of the two is done first,
3855 but the one that references cc0 can't be the second, and
3856 one which uses any regs/memory set in between i2 and i3 can't
3858 if (!use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)),
3861 && !reg_referenced_p (cc0_rtx, XVECEXP (newpat, 0, 0))
3865 newi2pat = XVECEXP (newpat, 0, 1);
3866 newpat = XVECEXP (newpat, 0, 0);
3868 else if (!use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 0)),
3871 && !reg_referenced_p (cc0_rtx, XVECEXP (newpat, 0, 1))
3875 newi2pat = XVECEXP (newpat, 0, 0);
3876 newpat = XVECEXP (newpat, 0, 1);
3884 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
3886 if (i2_code_number >= 0)
3888 /* recog_for_combine might have added CLOBBERs to newi2pat.
3889 Make sure NEWPAT does not depend on the clobbered regs. */
3890 if (GET_CODE (newi2pat) == PARALLEL)
3892 for (i = XVECLEN (newi2pat, 0) - 1; i >= 0; i--)
3893 if (GET_CODE (XVECEXP (newi2pat, 0, i)) == CLOBBER)
3895 rtx reg = XEXP (XVECEXP (newi2pat, 0, i), 0);
3896 if (reg_overlap_mentioned_p (reg, newpat))
3904 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
3908 /* If it still isn't recognized, fail and change things back the way they
3910 if ((insn_code_number < 0
3911 /* Is the result a reasonable ASM_OPERANDS? */
3912 && (! check_asm_operands (newpat) || added_sets_1 || added_sets_2)))
3918 /* If we had to change another insn, make sure it is valid also. */
3919 if (undobuf.other_insn)
3921 CLEAR_HARD_REG_SET (newpat_used_regs);
3923 other_pat = PATTERN (undobuf.other_insn);
3924 other_code_number = recog_for_combine (&other_pat, undobuf.other_insn,
3927 if (other_code_number < 0 && ! check_asm_operands (other_pat))
3935 /* If I2 is the CC0 setter and I3 is the CC0 user then check whether
3936 they are adjacent to each other or not. */
3938 rtx p = prev_nonnote_insn (i3);
3939 if (p && p != i2 && NONJUMP_INSN_P (p) && newi2pat
3940 && sets_cc0_p (newi2pat))
3948 /* Only allow this combination if insn_rtx_costs reports that the
3949 replacement instructions are cheaper than the originals. */
3950 if (!combine_validate_cost (i0, i1, i2, i3, newpat, newi2pat, other_pat))
3956 if (MAY_HAVE_DEBUG_INSNS)
3960 for (undo = undobuf.undos; undo; undo = undo->next)
3961 if (undo->kind == UNDO_MODE)
3963 rtx reg = *undo->where.r;
3964 enum machine_mode new_mode = GET_MODE (reg);
3965 enum machine_mode old_mode = undo->old_contents.m;
3967 /* Temporarily revert mode back. */
3968 adjust_reg_mode (reg, old_mode);
3970 if (reg == i2dest && i2scratch)
3972 /* If we used i2dest as a scratch register with a
3973 different mode, substitute it for the original
3974 i2src while its original mode is temporarily
3975 restored, and then clear i2scratch so that we don't
3976 do it again later. */
3977 propagate_for_debug (i2, last_combined_insn, reg, i2src);
3979 /* Put back the new mode. */
3980 adjust_reg_mode (reg, new_mode);
3984 rtx tempreg = gen_raw_REG (old_mode, REGNO (reg));
3990 last = last_combined_insn;
3995 last = undobuf.other_insn;
3997 if (DF_INSN_LUID (last)
3998 < DF_INSN_LUID (last_combined_insn))
3999 last = last_combined_insn;
4002 /* We're dealing with a reg that changed mode but not
4003 meaning, so we want to turn it into a subreg for
4004 the new mode. However, because of REG sharing and
4005 because its mode had already changed, we have to do
4006 it in two steps. First, replace any debug uses of
4007 reg, with its original mode temporarily restored,
4008 with this copy we have created; then, replace the
4009 copy with the SUBREG of the original shared reg,
4010 once again changed to the new mode. */
4011 propagate_for_debug (first, last, reg, tempreg);
4012 adjust_reg_mode (reg, new_mode);
4013 propagate_for_debug (first, last, tempreg,
4014 lowpart_subreg (old_mode, reg, new_mode));
4019 /* If we will be able to accept this, we have made a
4020 change to the destination of I3. This requires us to
4021 do a few adjustments. */
4023 if (changed_i3_dest)
4025 PATTERN (i3) = newpat;
4026 adjust_for_new_dest (i3);
4029 /* We now know that we can do this combination. Merge the insns and
4030 update the status of registers and LOG_LINKS. */
4032 if (undobuf.other_insn)
4036 PATTERN (undobuf.other_insn) = other_pat;
4038 /* If any of the notes in OTHER_INSN were REG_UNUSED, ensure that they
4039 are still valid. Then add any non-duplicate notes added by
4040 recog_for_combine. */
4041 for (note = REG_NOTES (undobuf.other_insn); note; note = next)
4043 next = XEXP (note, 1);
4045 if (REG_NOTE_KIND (note) == REG_UNUSED
4046 && ! reg_set_p (XEXP (note, 0), PATTERN (undobuf.other_insn)))
4047 remove_note (undobuf.other_insn, note);
4050 distribute_notes (new_other_notes, undobuf.other_insn,
4051 undobuf.other_insn, NULL_RTX, NULL_RTX, NULL_RTX,
4058 struct insn_link *link;
4061 /* I3 now uses what used to be its destination and which is now
4062 I2's destination. This requires us to do a few adjustments. */
4063 PATTERN (i3) = newpat;
4064 adjust_for_new_dest (i3);
4066 /* We need a LOG_LINK from I3 to I2. But we used to have one,
4069 However, some later insn might be using I2's dest and have
4070 a LOG_LINK pointing at I3. We must remove this link.
4071 The simplest way to remove the link is to point it at I1,
4072 which we know will be a NOTE. */
4074 /* newi2pat is usually a SET here; however, recog_for_combine might
4075 have added some clobbers. */
4076 if (GET_CODE (newi2pat) == PARALLEL)
4077 ni2dest = SET_DEST (XVECEXP (newi2pat, 0, 0));
4079 ni2dest = SET_DEST (newi2pat);
4081 for (insn = NEXT_INSN (i3);
4082 insn && (this_basic_block->next_bb == EXIT_BLOCK_PTR
4083 || insn != BB_HEAD (this_basic_block->next_bb));
4084 insn = NEXT_INSN (insn))
4086 if (INSN_P (insn) && reg_referenced_p (ni2dest, PATTERN (insn)))
4088 FOR_EACH_LOG_LINK (link, insn)
4089 if (link->insn == i3)
4098 rtx i3notes, i2notes, i1notes = 0, i0notes = 0;
4099 struct insn_link *i3links, *i2links, *i1links = 0, *i0links = 0;
4102 /* Compute which registers we expect to eliminate. newi2pat may be setting
4103 either i3dest or i2dest, so we must check it. Also, i1dest may be the
4104 same as i3dest, in which case newi2pat may be setting i1dest. */
4105 rtx elim_i2 = ((newi2pat && reg_set_p (i2dest, newi2pat))
4106 || i2dest_in_i2src || i2dest_in_i1src || i2dest_in_i0src
4109 rtx elim_i1 = (i1 == 0 || i1dest_in_i1src || i1dest_in_i0src
4110 || (newi2pat && reg_set_p (i1dest, newi2pat))
4113 rtx elim_i0 = (i0 == 0 || i0dest_in_i0src
4114 || (newi2pat && reg_set_p (i0dest, newi2pat))
4118 /* Get the old REG_NOTES and LOG_LINKS from all our insns and
4120 i3notes = REG_NOTES (i3), i3links = LOG_LINKS (i3);
4121 i2notes = REG_NOTES (i2), i2links = LOG_LINKS (i2);
4123 i1notes = REG_NOTES (i1), i1links = LOG_LINKS (i1);
4125 i0notes = REG_NOTES (i0), i0links = LOG_LINKS (i0);
4127 /* Ensure that we do not have something that should not be shared but
4128 occurs multiple times in the new insns. Check this by first
4129 resetting all the `used' flags and then copying anything is shared. */
4131 reset_used_flags (i3notes);
4132 reset_used_flags (i2notes);
4133 reset_used_flags (i1notes);
4134 reset_used_flags (i0notes);
4135 reset_used_flags (newpat);
4136 reset_used_flags (newi2pat);
4137 if (undobuf.other_insn)
4138 reset_used_flags (PATTERN (undobuf.other_insn));
4140 i3notes = copy_rtx_if_shared (i3notes);
4141 i2notes = copy_rtx_if_shared (i2notes);
4142 i1notes = copy_rtx_if_shared (i1notes);
4143 i0notes = copy_rtx_if_shared (i0notes);
4144 newpat = copy_rtx_if_shared (newpat);
4145 newi2pat = copy_rtx_if_shared (newi2pat);
4146 if (undobuf.other_insn)
4147 reset_used_flags (PATTERN (undobuf.other_insn));
4149 INSN_CODE (i3) = insn_code_number;
4150 PATTERN (i3) = newpat;
4152 if (CALL_P (i3) && CALL_INSN_FUNCTION_USAGE (i3))
4154 rtx call_usage = CALL_INSN_FUNCTION_USAGE (i3);
4156 reset_used_flags (call_usage);
4157 call_usage = copy_rtx (call_usage);
4161 /* I2SRC must still be meaningful at this point. Some splitting
4162 operations can invalidate I2SRC, but those operations do not
4165 replace_rtx (call_usage, i2dest, i2src);
4169 replace_rtx (call_usage, i1dest, i1src);
4171 replace_rtx (call_usage, i0dest, i0src);
4173 CALL_INSN_FUNCTION_USAGE (i3) = call_usage;
4176 if (undobuf.other_insn)
4177 INSN_CODE (undobuf.other_insn) = other_code_number;
4179 /* We had one special case above where I2 had more than one set and
4180 we replaced a destination of one of those sets with the destination
4181 of I3. In that case, we have to update LOG_LINKS of insns later
4182 in this basic block. Note that this (expensive) case is rare.
4184 Also, in this case, we must pretend that all REG_NOTEs for I2
4185 actually came from I3, so that REG_UNUSED notes from I2 will be
4186 properly handled. */
4188 if (i3_subst_into_i2)
4190 for (i = 0; i < XVECLEN (PATTERN (i2), 0); i++)
4191 if ((GET_CODE (XVECEXP (PATTERN (i2), 0, i)) == SET
4192 || GET_CODE (XVECEXP (PATTERN (i2), 0, i)) == CLOBBER)
4193 && REG_P (SET_DEST (XVECEXP (PATTERN (i2), 0, i)))
4194 && SET_DEST (XVECEXP (PATTERN (i2), 0, i)) != i2dest
4195 && ! find_reg_note (i2, REG_UNUSED,
4196 SET_DEST (XVECEXP (PATTERN (i2), 0, i))))
4197 for (temp = NEXT_INSN (i2);
4198 temp && (this_basic_block->next_bb == EXIT_BLOCK_PTR
4199 || BB_HEAD (this_basic_block) != temp);
4200 temp = NEXT_INSN (temp))
4201 if (temp != i3 && INSN_P (temp))
4202 FOR_EACH_LOG_LINK (link, temp)
4203 if (link->insn == i2)
4209 while (XEXP (link, 1))
4210 link = XEXP (link, 1);
4211 XEXP (link, 1) = i2notes;
4218 LOG_LINKS (i3) = NULL;
4220 LOG_LINKS (i2) = NULL;
4225 if (MAY_HAVE_DEBUG_INSNS && i2scratch)
4226 propagate_for_debug (i2, last_combined_insn, i2dest, i2src);
4227 INSN_CODE (i2) = i2_code_number;
4228 PATTERN (i2) = newi2pat;
4232 if (MAY_HAVE_DEBUG_INSNS && i2src)
4233 propagate_for_debug (i2, last_combined_insn, i2dest, i2src);
4234 SET_INSN_DELETED (i2);
4239 LOG_LINKS (i1) = NULL;
4241 if (MAY_HAVE_DEBUG_INSNS)
4242 propagate_for_debug (i1, last_combined_insn, i1dest, i1src);
4243 SET_INSN_DELETED (i1);
4248 LOG_LINKS (i0) = NULL;
4250 if (MAY_HAVE_DEBUG_INSNS)
4251 propagate_for_debug (i0, last_combined_insn, i0dest, i0src);
4252 SET_INSN_DELETED (i0);
4255 /* Get death notes for everything that is now used in either I3 or
4256 I2 and used to die in a previous insn. If we built two new
4257 patterns, move from I1 to I2 then I2 to I3 so that we get the
4258 proper movement on registers that I2 modifies. */
4261 from_luid = DF_INSN_LUID (i0);
4263 from_luid = DF_INSN_LUID (i1);
4265 from_luid = DF_INSN_LUID (i2);
4267 move_deaths (newi2pat, NULL_RTX, from_luid, i2, &midnotes);
4268 move_deaths (newpat, newi2pat, from_luid, i3, &midnotes);
4270 /* Distribute all the LOG_LINKS and REG_NOTES from I1, I2, and I3. */
4272 distribute_notes (i3notes, i3, i3, newi2pat ? i2 : NULL_RTX,
4273 elim_i2, elim_i1, elim_i0);
4275 distribute_notes (i2notes, i2, i3, newi2pat ? i2 : NULL_RTX,
4276 elim_i2, elim_i1, elim_i0);
4278 distribute_notes (i1notes, i1, i3, newi2pat ? i2 : NULL_RTX,
4279 elim_i2, elim_i1, elim_i0);
4281 distribute_notes (i0notes, i0, i3, newi2pat ? i2 : NULL_RTX,
4282 elim_i2, elim_i1, elim_i0);
4284 distribute_notes (midnotes, NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
4285 elim_i2, elim_i1, elim_i0);
4287 /* Distribute any notes added to I2 or I3 by recog_for_combine. We
4288 know these are REG_UNUSED and want them to go to the desired insn,
4289 so we always pass it as i3. */
4291 if (newi2pat && new_i2_notes)
4292 distribute_notes (new_i2_notes, i2, i2, NULL_RTX, NULL_RTX, NULL_RTX,
4296 distribute_notes (new_i3_notes, i3, i3, NULL_RTX, NULL_RTX, NULL_RTX,
4299 /* If I3DEST was used in I3SRC, it really died in I3. We may need to
4300 put a REG_DEAD note for it somewhere. If NEWI2PAT exists and sets
4301 I3DEST, the death must be somewhere before I2, not I3. If we passed I3
4302 in that case, it might delete I2. Similarly for I2 and I1.
4303 Show an additional death due to the REG_DEAD note we make here. If
4304 we discard it in distribute_notes, we will decrement it again. */
4308 if (newi2pat && reg_set_p (i3dest_killed, newi2pat))
4309 distribute_notes (alloc_reg_note (REG_DEAD, i3dest_killed,
4311 NULL_RTX, i2, NULL_RTX, elim_i2, elim_i1, elim_i0);
4313 distribute_notes (alloc_reg_note (REG_DEAD, i3dest_killed,
4315 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
4316 elim_i2, elim_i1, elim_i0);
4319 if (i2dest_in_i2src)
4321 rtx new_note = alloc_reg_note (REG_DEAD, i2dest, NULL_RTX);
4322 if (newi2pat && reg_set_p (i2dest, newi2pat))
4323 distribute_notes (new_note, NULL_RTX, i2, NULL_RTX, NULL_RTX,
4324 NULL_RTX, NULL_RTX);
4326 distribute_notes (new_note, NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
4327 NULL_RTX, NULL_RTX, NULL_RTX);
4330 if (i1dest_in_i1src)
4332 rtx new_note = alloc_reg_note (REG_DEAD, i1dest, NULL_RTX);
4333 if (newi2pat && reg_set_p (i1dest, newi2pat))
4334 distribute_notes (new_note, NULL_RTX, i2, NULL_RTX, NULL_RTX,
4335 NULL_RTX, NULL_RTX);
4337 distribute_notes (new_note, NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
4338 NULL_RTX, NULL_RTX, NULL_RTX);
4341 if (i0dest_in_i0src)
4343 rtx new_note = alloc_reg_note (REG_DEAD, i0dest, NULL_RTX);
4344 if (newi2pat && reg_set_p (i0dest, newi2pat))
4345 distribute_notes (new_note, NULL_RTX, i2, NULL_RTX, NULL_RTX,
4346 NULL_RTX, NULL_RTX);
4348 distribute_notes (new_note, NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
4349 NULL_RTX, NULL_RTX, NULL_RTX);
4352 distribute_links (i3links);
4353 distribute_links (i2links);
4354 distribute_links (i1links);
4355 distribute_links (i0links);
4359 struct insn_link *link;
4360 rtx i2_insn = 0, i2_val = 0, set;
4362 /* The insn that used to set this register doesn't exist, and
4363 this life of the register may not exist either. See if one of
4364 I3's links points to an insn that sets I2DEST. If it does,
4365 that is now the last known value for I2DEST. If we don't update
4366 this and I2 set the register to a value that depended on its old
4367 contents, we will get confused. If this insn is used, thing
4368 will be set correctly in combine_instructions. */
4369 FOR_EACH_LOG_LINK (link, i3)
4370 if ((set = single_set (link->insn)) != 0
4371 && rtx_equal_p (i2dest, SET_DEST (set)))
4372 i2_insn = link->insn, i2_val = SET_SRC (set);
4374 record_value_for_reg (i2dest, i2_insn, i2_val);
4376 /* If the reg formerly set in I2 died only once and that was in I3,
4377 zero its use count so it won't make `reload' do any work. */
4379 && (newi2pat == 0 || ! reg_mentioned_p (i2dest, newi2pat))
4380 && ! i2dest_in_i2src)
4381 INC_REG_N_SETS (REGNO (i2dest), -1);
4384 if (i1 && REG_P (i1dest))
4386 struct insn_link *link;
4387 rtx i1_insn = 0, i1_val = 0, set;
4389 FOR_EACH_LOG_LINK (link, i3)
4390 if ((set = single_set (link->insn)) != 0
4391 && rtx_equal_p (i1dest, SET_DEST (set)))
4392 i1_insn = link->insn, i1_val = SET_SRC (set);
4394 record_value_for_reg (i1dest, i1_insn, i1_val);
4396 if (! added_sets_1 && ! i1dest_in_i1src)
4397 INC_REG_N_SETS (REGNO (i1dest), -1);
4400 if (i0 && REG_P (i0dest))
4402 struct insn_link *link;
4403 rtx i0_insn = 0, i0_val = 0, set;
4405 FOR_EACH_LOG_LINK (link, i3)
4406 if ((set = single_set (link->insn)) != 0
4407 && rtx_equal_p (i0dest, SET_DEST (set)))
4408 i0_insn = link->insn, i0_val = SET_SRC (set);
4410 record_value_for_reg (i0dest, i0_insn, i0_val);
4412 if (! added_sets_0 && ! i0dest_in_i0src)
4413 INC_REG_N_SETS (REGNO (i0dest), -1);
4416 /* Update reg_stat[].nonzero_bits et al for any changes that may have
4417 been made to this insn. The order of
4418 set_nonzero_bits_and_sign_copies() is important. Because newi2pat
4419 can affect nonzero_bits of newpat */
4421 note_stores (newi2pat, set_nonzero_bits_and_sign_copies, NULL);
4422 note_stores (newpat, set_nonzero_bits_and_sign_copies, NULL);
4425 if (undobuf.other_insn != NULL_RTX)
4429 fprintf (dump_file, "modifying other_insn ");
4430 dump_insn_slim (dump_file, undobuf.other_insn);
4432 df_insn_rescan (undobuf.other_insn);
4435 if (i0 && !(NOTE_P(i0) && (NOTE_KIND (i0) == NOTE_INSN_DELETED)))
4439 fprintf (dump_file, "modifying insn i1 ");
4440 dump_insn_slim (dump_file, i0);
4442 df_insn_rescan (i0);
4445 if (i1 && !(NOTE_P(i1) && (NOTE_KIND (i1) == NOTE_INSN_DELETED)))
4449 fprintf (dump_file, "modifying insn i1 ");
4450 dump_insn_slim (dump_file, i1);
4452 df_insn_rescan (i1);
4455 if (i2 && !(NOTE_P(i2) && (NOTE_KIND (i2) == NOTE_INSN_DELETED)))
4459 fprintf (dump_file, "modifying insn i2 ");
4460 dump_insn_slim (dump_file, i2);
4462 df_insn_rescan (i2);
4465 if (i3 && !(NOTE_P(i3) && (NOTE_KIND (i3) == NOTE_INSN_DELETED)))
4469 fprintf (dump_file, "modifying insn i3 ");
4470 dump_insn_slim (dump_file, i3);
4472 df_insn_rescan (i3);
4475 /* Set new_direct_jump_p if a new return or simple jump instruction
4476 has been created. Adjust the CFG accordingly. */
4478 if (returnjump_p (i3) || any_uncondjump_p (i3))
4480 *new_direct_jump_p = 1;
4481 mark_jump_label (PATTERN (i3), i3, 0);
4482 update_cfg_for_uncondjump (i3);
4485 if (undobuf.other_insn != NULL_RTX
4486 && (returnjump_p (undobuf.other_insn)
4487 || any_uncondjump_p (undobuf.other_insn)))
4489 *new_direct_jump_p = 1;
4490 update_cfg_for_uncondjump (undobuf.other_insn);
4493 /* A noop might also need cleaning up of CFG, if it comes from the
4494 simplification of a jump. */
4496 && GET_CODE (newpat) == SET
4497 && SET_SRC (newpat) == pc_rtx
4498 && SET_DEST (newpat) == pc_rtx)
4500 *new_direct_jump_p = 1;
4501 update_cfg_for_uncondjump (i3);
4504 if (undobuf.other_insn != NULL_RTX
4505 && JUMP_P (undobuf.other_insn)
4506 && GET_CODE (PATTERN (undobuf.other_insn)) == SET
4507 && SET_SRC (PATTERN (undobuf.other_insn)) == pc_rtx
4508 && SET_DEST (PATTERN (undobuf.other_insn)) == pc_rtx)
4510 *new_direct_jump_p = 1;
4511 update_cfg_for_uncondjump (undobuf.other_insn);
4514 combine_successes++;
4517 if (added_links_insn
4518 && (newi2pat == 0 || DF_INSN_LUID (added_links_insn) < DF_INSN_LUID (i2))
4519 && DF_INSN_LUID (added_links_insn) < DF_INSN_LUID (i3))
4520 return added_links_insn;
4522 return newi2pat ? i2 : i3;
4525 /* Undo all the modifications recorded in undobuf. */
4530 struct undo *undo, *next;
4532 for (undo = undobuf.undos; undo; undo = next)
4538 *undo->where.r = undo->old_contents.r;
4541 *undo->where.i = undo->old_contents.i;
4544 adjust_reg_mode (*undo->where.r, undo->old_contents.m);
4547 *undo->where.l = undo->old_contents.l;
4553 undo->next = undobuf.frees;
4554 undobuf.frees = undo;
4560 /* We've committed to accepting the changes we made. Move all
4561 of the undos to the free list. */
4566 struct undo *undo, *next;
4568 for (undo = undobuf.undos; undo; undo = next)
4571 undo->next = undobuf.frees;
4572 undobuf.frees = undo;
4577 /* Find the innermost point within the rtx at LOC, possibly LOC itself,
4578 where we have an arithmetic expression and return that point. LOC will
4581 try_combine will call this function to see if an insn can be split into
4585 find_split_point (rtx *loc, rtx insn, bool set_src)
4588 enum rtx_code code = GET_CODE (x);
4590 unsigned HOST_WIDE_INT len = 0;
4591 HOST_WIDE_INT pos = 0;
4593 rtx inner = NULL_RTX;
4595 /* First special-case some codes. */
4599 #ifdef INSN_SCHEDULING
4600 /* If we are making a paradoxical SUBREG invalid, it becomes a split
4602 if (MEM_P (SUBREG_REG (x)))
4605 return find_split_point (&SUBREG_REG (x), insn, false);
4609 /* If we have (mem (const ..)) or (mem (symbol_ref ...)), split it
4610 using LO_SUM and HIGH. */
4611 if (GET_CODE (XEXP (x, 0)) == CONST
4612 || GET_CODE (XEXP (x, 0)) == SYMBOL_REF)
4614 enum machine_mode address_mode
4615 = targetm.addr_space.address_mode (MEM_ADDR_SPACE (x));
4618 gen_rtx_LO_SUM (address_mode,
4619 gen_rtx_HIGH (address_mode, XEXP (x, 0)),
4621 return &XEXP (XEXP (x, 0), 0);
4625 /* If we have a PLUS whose second operand is a constant and the
4626 address is not valid, perhaps will can split it up using
4627 the machine-specific way to split large constants. We use
4628 the first pseudo-reg (one of the virtual regs) as a placeholder;
4629 it will not remain in the result. */
4630 if (GET_CODE (XEXP (x, 0)) == PLUS
4631 && CONST_INT_P (XEXP (XEXP (x, 0), 1))
4632 && ! memory_address_addr_space_p (GET_MODE (x), XEXP (x, 0),
4633 MEM_ADDR_SPACE (x)))
4635 rtx reg = regno_reg_rtx[FIRST_PSEUDO_REGISTER];
4636 rtx seq = combine_split_insns (gen_rtx_SET (VOIDmode, reg,
4640 /* This should have produced two insns, each of which sets our
4641 placeholder. If the source of the second is a valid address,
4642 we can make put both sources together and make a split point
4646 && NEXT_INSN (seq) != NULL_RTX
4647 && NEXT_INSN (NEXT_INSN (seq)) == NULL_RTX
4648 && NONJUMP_INSN_P (seq)
4649 && GET_CODE (PATTERN (seq)) == SET
4650 && SET_DEST (PATTERN (seq)) == reg
4651 && ! reg_mentioned_p (reg,
4652 SET_SRC (PATTERN (seq)))
4653 && NONJUMP_INSN_P (NEXT_INSN (seq))
4654 && GET_CODE (PATTERN (NEXT_INSN (seq))) == SET
4655 && SET_DEST (PATTERN (NEXT_INSN (seq))) == reg
4656 && memory_address_addr_space_p
4657 (GET_MODE (x), SET_SRC (PATTERN (NEXT_INSN (seq))),
4658 MEM_ADDR_SPACE (x)))
4660 rtx src1 = SET_SRC (PATTERN (seq));
4661 rtx src2 = SET_SRC (PATTERN (NEXT_INSN (seq)));
4663 /* Replace the placeholder in SRC2 with SRC1. If we can
4664 find where in SRC2 it was placed, that can become our
4665 split point and we can replace this address with SRC2.
4666 Just try two obvious places. */
4668 src2 = replace_rtx (src2, reg, src1);
4670 if (XEXP (src2, 0) == src1)
4671 split = &XEXP (src2, 0);
4672 else if (GET_RTX_FORMAT (GET_CODE (XEXP (src2, 0)))[0] == 'e'
4673 && XEXP (XEXP (src2, 0), 0) == src1)
4674 split = &XEXP (XEXP (src2, 0), 0);
4678 SUBST (XEXP (x, 0), src2);
4683 /* If that didn't work, perhaps the first operand is complex and
4684 needs to be computed separately, so make a split point there.
4685 This will occur on machines that just support REG + CONST
4686 and have a constant moved through some previous computation. */
4688 else if (!OBJECT_P (XEXP (XEXP (x, 0), 0))
4689 && ! (GET_CODE (XEXP (XEXP (x, 0), 0)) == SUBREG
4690 && OBJECT_P (SUBREG_REG (XEXP (XEXP (x, 0), 0)))))
4691 return &XEXP (XEXP (x, 0), 0);
4694 /* If we have a PLUS whose first operand is complex, try computing it
4695 separately by making a split there. */
4696 if (GET_CODE (XEXP (x, 0)) == PLUS
4697 && ! memory_address_addr_space_p (GET_MODE (x), XEXP (x, 0),
4699 && ! OBJECT_P (XEXP (XEXP (x, 0), 0))
4700 && ! (GET_CODE (XEXP (XEXP (x, 0), 0)) == SUBREG
4701 && OBJECT_P (SUBREG_REG (XEXP (XEXP (x, 0), 0)))))
4702 return &XEXP (XEXP (x, 0), 0);
4707 /* If SET_DEST is CC0 and SET_SRC is not an operand, a COMPARE, or a
4708 ZERO_EXTRACT, the most likely reason why this doesn't match is that
4709 we need to put the operand into a register. So split at that
4712 if (SET_DEST (x) == cc0_rtx
4713 && GET_CODE (SET_SRC (x)) != COMPARE
4714 && GET_CODE (SET_SRC (x)) != ZERO_EXTRACT
4715 && !OBJECT_P (SET_SRC (x))
4716 && ! (GET_CODE (SET_SRC (x)) == SUBREG
4717 && OBJECT_P (SUBREG_REG (SET_SRC (x)))))
4718 return &SET_SRC (x);
4721 /* See if we can split SET_SRC as it stands. */
4722 split = find_split_point (&SET_SRC (x), insn, true);
4723 if (split && split != &SET_SRC (x))
4726 /* See if we can split SET_DEST as it stands. */
4727 split = find_split_point (&SET_DEST (x), insn, false);
4728 if (split && split != &SET_DEST (x))
4731 /* See if this is a bitfield assignment with everything constant. If
4732 so, this is an IOR of an AND, so split it into that. */
4733 if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
4734 && HWI_COMPUTABLE_MODE_P (GET_MODE (XEXP (SET_DEST (x), 0)))
4735 && CONST_INT_P (XEXP (SET_DEST (x), 1))
4736 && CONST_INT_P (XEXP (SET_DEST (x), 2))
4737 && CONST_INT_P (SET_SRC (x))
4738 && ((INTVAL (XEXP (SET_DEST (x), 1))
4739 + INTVAL (XEXP (SET_DEST (x), 2)))
4740 <= GET_MODE_PRECISION (GET_MODE (XEXP (SET_DEST (x), 0))))
4741 && ! side_effects_p (XEXP (SET_DEST (x), 0)))
4743 HOST_WIDE_INT pos = INTVAL (XEXP (SET_DEST (x), 2));
4744 unsigned HOST_WIDE_INT len = INTVAL (XEXP (SET_DEST (x), 1));
4745 unsigned HOST_WIDE_INT src = INTVAL (SET_SRC (x));
4746 rtx dest = XEXP (SET_DEST (x), 0);
4747 enum machine_mode mode = GET_MODE (dest);
4748 unsigned HOST_WIDE_INT mask
4749 = ((unsigned HOST_WIDE_INT) 1 << len) - 1;
4752 if (BITS_BIG_ENDIAN)
4753 pos = GET_MODE_PRECISION (mode) - len - pos;
4755 or_mask = gen_int_mode (src << pos, mode);
4758 simplify_gen_binary (IOR, mode, dest, or_mask));
4761 rtx negmask = gen_int_mode (~(mask << pos), mode);
4763 simplify_gen_binary (IOR, mode,
4764 simplify_gen_binary (AND, mode,
4769 SUBST (SET_DEST (x), dest);
4771 split = find_split_point (&SET_SRC (x), insn, true);
4772 if (split && split != &SET_SRC (x))
4776 /* Otherwise, see if this is an operation that we can split into two.
4777 If so, try to split that. */
4778 code = GET_CODE (SET_SRC (x));
4783 /* If we are AND'ing with a large constant that is only a single
4784 bit and the result is only being used in a context where we
4785 need to know if it is zero or nonzero, replace it with a bit
4786 extraction. This will avoid the large constant, which might
4787 have taken more than one insn to make. If the constant were
4788 not a valid argument to the AND but took only one insn to make,
4789 this is no worse, but if it took more than one insn, it will
4792 if (CONST_INT_P (XEXP (SET_SRC (x), 1))
4793 && REG_P (XEXP (SET_SRC (x), 0))
4794 && (pos = exact_log2 (UINTVAL (XEXP (SET_SRC (x), 1)))) >= 7
4795 && REG_P (SET_DEST (x))
4796 && (split = find_single_use (SET_DEST (x), insn, (rtx*) 0)) != 0
4797 && (GET_CODE (*split) == EQ || GET_CODE (*split) == NE)
4798 && XEXP (*split, 0) == SET_DEST (x)
4799 && XEXP (*split, 1) == const0_rtx)
4801 rtx extraction = make_extraction (GET_MODE (SET_DEST (x)),
4802 XEXP (SET_SRC (x), 0),
4803 pos, NULL_RTX, 1, 1, 0, 0);
4804 if (extraction != 0)
4806 SUBST (SET_SRC (x), extraction);
4807 return find_split_point (loc, insn, false);
4813 /* If STORE_FLAG_VALUE is -1, this is (NE X 0) and only one bit of X
4814 is known to be on, this can be converted into a NEG of a shift. */
4815 if (STORE_FLAG_VALUE == -1 && XEXP (SET_SRC (x), 1) == const0_rtx
4816 && GET_MODE (SET_SRC (x)) == GET_MODE (XEXP (SET_SRC (x), 0))
4817 && 1 <= (pos = exact_log2
4818 (nonzero_bits (XEXP (SET_SRC (x), 0),
4819 GET_MODE (XEXP (SET_SRC (x), 0))))))
4821 enum machine_mode mode = GET_MODE (XEXP (SET_SRC (x), 0));
4825 gen_rtx_LSHIFTRT (mode,
4826 XEXP (SET_SRC (x), 0),
4829 split = find_split_point (&SET_SRC (x), insn, true);
4830 if (split && split != &SET_SRC (x))
4836 inner = XEXP (SET_SRC (x), 0);
4838 /* We can't optimize if either mode is a partial integer
4839 mode as we don't know how many bits are significant
4841 if (GET_MODE_CLASS (GET_MODE (inner)) == MODE_PARTIAL_INT
4842 || GET_MODE_CLASS (GET_MODE (SET_SRC (x))) == MODE_PARTIAL_INT)
4846 len = GET_MODE_PRECISION (GET_MODE (inner));
4852 if (CONST_INT_P (XEXP (SET_SRC (x), 1))
4853 && CONST_INT_P (XEXP (SET_SRC (x), 2)))
4855 inner = XEXP (SET_SRC (x), 0);
4856 len = INTVAL (XEXP (SET_SRC (x), 1));
4857 pos = INTVAL (XEXP (SET_SRC (x), 2));
4859 if (BITS_BIG_ENDIAN)
4860 pos = GET_MODE_PRECISION (GET_MODE (inner)) - len - pos;
4861 unsignedp = (code == ZERO_EXTRACT);
4870 && pos + len <= GET_MODE_PRECISION (GET_MODE (inner)))
4872 enum machine_mode mode = GET_MODE (SET_SRC (x));
4874 /* For unsigned, we have a choice of a shift followed by an
4875 AND or two shifts. Use two shifts for field sizes where the
4876 constant might be too large. We assume here that we can
4877 always at least get 8-bit constants in an AND insn, which is
4878 true for every current RISC. */
4880 if (unsignedp && len <= 8)
4885 (mode, gen_lowpart (mode, inner),
4887 GEN_INT (((unsigned HOST_WIDE_INT) 1 << len)
4890 split = find_split_point (&SET_SRC (x), insn, true);
4891 if (split && split != &SET_SRC (x))
4898 (unsignedp ? LSHIFTRT : ASHIFTRT, mode,
4899 gen_rtx_ASHIFT (mode,
4900 gen_lowpart (mode, inner),
4901 GEN_INT (GET_MODE_PRECISION (mode)
4903 GEN_INT (GET_MODE_PRECISION (mode) - len)));
4905 split = find_split_point (&SET_SRC (x), insn, true);
4906 if (split && split != &SET_SRC (x))
4911 /* See if this is a simple operation with a constant as the second
4912 operand. It might be that this constant is out of range and hence
4913 could be used as a split point. */
4914 if (BINARY_P (SET_SRC (x))
4915 && CONSTANT_P (XEXP (SET_SRC (x), 1))
4916 && (OBJECT_P (XEXP (SET_SRC (x), 0))
4917 || (GET_CODE (XEXP (SET_SRC (x), 0)) == SUBREG
4918 && OBJECT_P (SUBREG_REG (XEXP (SET_SRC (x), 0))))))
4919 return &XEXP (SET_SRC (x), 1);
4921 /* Finally, see if this is a simple operation with its first operand
4922 not in a register. The operation might require this operand in a
4923 register, so return it as a split point. We can always do this
4924 because if the first operand were another operation, we would have
4925 already found it as a split point. */
4926 if ((BINARY_P (SET_SRC (x)) || UNARY_P (SET_SRC (x)))
4927 && ! register_operand (XEXP (SET_SRC (x), 0), VOIDmode))
4928 return &XEXP (SET_SRC (x), 0);
4934 /* We write NOR as (and (not A) (not B)), but if we don't have a NOR,
4935 it is better to write this as (not (ior A B)) so we can split it.
4936 Similarly for IOR. */
4937 if (GET_CODE (XEXP (x, 0)) == NOT && GET_CODE (XEXP (x, 1)) == NOT)
4940 gen_rtx_NOT (GET_MODE (x),
4941 gen_rtx_fmt_ee (code == IOR ? AND : IOR,
4943 XEXP (XEXP (x, 0), 0),
4944 XEXP (XEXP (x, 1), 0))));
4945 return find_split_point (loc, insn, set_src);
4948 /* Many RISC machines have a large set of logical insns. If the
4949 second operand is a NOT, put it first so we will try to split the
4950 other operand first. */
4951 if (GET_CODE (XEXP (x, 1)) == NOT)
4953 rtx tem = XEXP (x, 0);
4954 SUBST (XEXP (x, 0), XEXP (x, 1));
4955 SUBST (XEXP (x, 1), tem);
4961 /* Canonicalization can produce (minus A (mult B C)), where C is a
4962 constant. It may be better to try splitting (plus (mult B -C) A)
4963 instead if this isn't a multiply by a power of two. */
4964 if (set_src && code == MINUS && GET_CODE (XEXP (x, 1)) == MULT
4965 && GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT
4966 && exact_log2 (INTVAL (XEXP (XEXP (x, 1), 1))) < 0)
4968 enum machine_mode mode = GET_MODE (x);
4969 unsigned HOST_WIDE_INT this_int = INTVAL (XEXP (XEXP (x, 1), 1));
4970 HOST_WIDE_INT other_int = trunc_int_for_mode (-this_int, mode);
4971 SUBST (*loc, gen_rtx_PLUS (mode, gen_rtx_MULT (mode,
4972 XEXP (XEXP (x, 1), 0),
4973 GEN_INT (other_int)),
4975 return find_split_point (loc, insn, set_src);
4978 /* Split at a multiply-accumulate instruction. However if this is
4979 the SET_SRC, we likely do not have such an instruction and it's
4980 worthless to try this split. */
4981 if (!set_src && GET_CODE (XEXP (x, 0)) == MULT)
4988 /* Otherwise, select our actions depending on our rtx class. */
4989 switch (GET_RTX_CLASS (code))
4991 case RTX_BITFIELD_OPS: /* This is ZERO_EXTRACT and SIGN_EXTRACT. */
4993 split = find_split_point (&XEXP (x, 2), insn, false);
4996 /* ... fall through ... */
4998 case RTX_COMM_ARITH:
5000 case RTX_COMM_COMPARE:
5001 split = find_split_point (&XEXP (x, 1), insn, false);
5004 /* ... fall through ... */
5006 /* Some machines have (and (shift ...) ...) insns. If X is not
5007 an AND, but XEXP (X, 0) is, use it as our split point. */
5008 if (GET_CODE (x) != AND && GET_CODE (XEXP (x, 0)) == AND)
5009 return &XEXP (x, 0);
5011 split = find_split_point (&XEXP (x, 0), insn, false);
5017 /* Otherwise, we don't have a split point. */
5022 /* Throughout X, replace FROM with TO, and return the result.
5023 The result is TO if X is FROM;
5024 otherwise the result is X, but its contents may have been modified.
5025 If they were modified, a record was made in undobuf so that
5026 undo_all will (among other things) return X to its original state.
5028 If the number of changes necessary is too much to record to undo,
5029 the excess changes are not made, so the result is invalid.
5030 The changes already made can still be undone.
5031 undobuf.num_undo is incremented for such changes, so by testing that
5032 the caller can tell whether the result is valid.
5034 `n_occurrences' is incremented each time FROM is replaced.
5036 IN_DEST is nonzero if we are processing the SET_DEST of a SET.
5038 IN_COND is nonzero if we are at the top level of a condition.
5040 UNIQUE_COPY is nonzero if each substitution must be unique. We do this
5041 by copying if `n_occurrences' is nonzero. */
5044 subst (rtx x, rtx from, rtx to, int in_dest, int in_cond, int unique_copy)
5046 enum rtx_code code = GET_CODE (x);
5047 enum machine_mode op0_mode = VOIDmode;
5052 /* Two expressions are equal if they are identical copies of a shared
5053 RTX or if they are both registers with the same register number
5056 #define COMBINE_RTX_EQUAL_P(X,Y) \
5058 || (REG_P (X) && REG_P (Y) \
5059 && REGNO (X) == REGNO (Y) && GET_MODE (X) == GET_MODE (Y)))
5061 if (! in_dest && COMBINE_RTX_EQUAL_P (x, from))
5064 return (unique_copy && n_occurrences > 1 ? copy_rtx (to) : to);
5067 /* If X and FROM are the same register but different modes, they
5068 will not have been seen as equal above. However, the log links code
5069 will make a LOG_LINKS entry for that case. If we do nothing, we
5070 will try to rerecognize our original insn and, when it succeeds,
5071 we will delete the feeding insn, which is incorrect.
5073 So force this insn not to match in this (rare) case. */
5074 if (! in_dest && code == REG && REG_P (from)
5075 && reg_overlap_mentioned_p (x, from))
5076 return gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
5078 /* If this is an object, we are done unless it is a MEM or LO_SUM, both
5079 of which may contain things that can be combined. */
5080 if (code != MEM && code != LO_SUM && OBJECT_P (x))
5083 /* It is possible to have a subexpression appear twice in the insn.
5084 Suppose that FROM is a register that appears within TO.
5085 Then, after that subexpression has been scanned once by `subst',
5086 the second time it is scanned, TO may be found. If we were
5087 to scan TO here, we would find FROM within it and create a
5088 self-referent rtl structure which is completely wrong. */
5089 if (COMBINE_RTX_EQUAL_P (x, to))
5092 /* Parallel asm_operands need special attention because all of the
5093 inputs are shared across the arms. Furthermore, unsharing the
5094 rtl results in recognition failures. Failure to handle this case
5095 specially can result in circular rtl.
5097 Solve this by doing a normal pass across the first entry of the
5098 parallel, and only processing the SET_DESTs of the subsequent
5101 if (code == PARALLEL
5102 && GET_CODE (XVECEXP (x, 0, 0)) == SET
5103 && GET_CODE (SET_SRC (XVECEXP (x, 0, 0))) == ASM_OPERANDS)
5105 new_rtx = subst (XVECEXP (x, 0, 0), from, to, 0, 0, unique_copy);
5107 /* If this substitution failed, this whole thing fails. */
5108 if (GET_CODE (new_rtx) == CLOBBER
5109 && XEXP (new_rtx, 0) == const0_rtx)
5112 SUBST (XVECEXP (x, 0, 0), new_rtx);
5114 for (i = XVECLEN (x, 0) - 1; i >= 1; i--)
5116 rtx dest = SET_DEST (XVECEXP (x, 0, i));
5119 && GET_CODE (dest) != CC0
5120 && GET_CODE (dest) != PC)
5122 new_rtx = subst (dest, from, to, 0, 0, unique_copy);
5124 /* If this substitution failed, this whole thing fails. */
5125 if (GET_CODE (new_rtx) == CLOBBER
5126 && XEXP (new_rtx, 0) == const0_rtx)
5129 SUBST (SET_DEST (XVECEXP (x, 0, i)), new_rtx);
5135 len = GET_RTX_LENGTH (code);
5136 fmt = GET_RTX_FORMAT (code);
5138 /* We don't need to process a SET_DEST that is a register, CC0,
5139 or PC, so set up to skip this common case. All other cases
5140 where we want to suppress replacing something inside a
5141 SET_SRC are handled via the IN_DEST operand. */
5143 && (REG_P (SET_DEST (x))
5144 || GET_CODE (SET_DEST (x)) == CC0
5145 || GET_CODE (SET_DEST (x)) == PC))
5148 /* Get the mode of operand 0 in case X is now a SIGN_EXTEND of a
5151 op0_mode = GET_MODE (XEXP (x, 0));
5153 for (i = 0; i < len; i++)
5158 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
5160 if (COMBINE_RTX_EQUAL_P (XVECEXP (x, i, j), from))
5162 new_rtx = (unique_copy && n_occurrences
5163 ? copy_rtx (to) : to);
5168 new_rtx = subst (XVECEXP (x, i, j), from, to, 0, 0,
5171 /* If this substitution failed, this whole thing
5173 if (GET_CODE (new_rtx) == CLOBBER
5174 && XEXP (new_rtx, 0) == const0_rtx)
5178 SUBST (XVECEXP (x, i, j), new_rtx);
5181 else if (fmt[i] == 'e')
5183 /* If this is a register being set, ignore it. */
5184 new_rtx = XEXP (x, i);
5187 && (((code == SUBREG || code == ZERO_EXTRACT)
5189 || code == STRICT_LOW_PART))
5192 else if (COMBINE_RTX_EQUAL_P (XEXP (x, i), from))
5194 /* In general, don't install a subreg involving two
5195 modes not tieable. It can worsen register
5196 allocation, and can even make invalid reload
5197 insns, since the reg inside may need to be copied
5198 from in the outside mode, and that may be invalid
5199 if it is an fp reg copied in integer mode.
5201 We allow two exceptions to this: It is valid if
5202 it is inside another SUBREG and the mode of that
5203 SUBREG and the mode of the inside of TO is
5204 tieable and it is valid if X is a SET that copies
5207 if (GET_CODE (to) == SUBREG
5208 && ! MODES_TIEABLE_P (GET_MODE (to),
5209 GET_MODE (SUBREG_REG (to)))
5210 && ! (code == SUBREG
5211 && MODES_TIEABLE_P (GET_MODE (x),
5212 GET_MODE (SUBREG_REG (to))))
5214 && ! (code == SET && i == 1 && XEXP (x, 0) == cc0_rtx)
5217 return gen_rtx_CLOBBER (VOIDmode, const0_rtx);
5219 #ifdef CANNOT_CHANGE_MODE_CLASS
5222 && REGNO (to) < FIRST_PSEUDO_REGISTER
5223 && REG_CANNOT_CHANGE_MODE_P (REGNO (to),
5226 return gen_rtx_CLOBBER (VOIDmode, const0_rtx);
5229 new_rtx = (unique_copy && n_occurrences ? copy_rtx (to) : to);
5233 /* If we are in a SET_DEST, suppress most cases unless we
5234 have gone inside a MEM, in which case we want to
5235 simplify the address. We assume here that things that
5236 are actually part of the destination have their inner
5237 parts in the first expression. This is true for SUBREG,
5238 STRICT_LOW_PART, and ZERO_EXTRACT, which are the only
5239 things aside from REG and MEM that should appear in a
5241 new_rtx = subst (XEXP (x, i), from, to,
5243 && (code == SUBREG || code == STRICT_LOW_PART
5244 || code == ZERO_EXTRACT))
5247 code == IF_THEN_ELSE && i == 0,
5250 /* If we found that we will have to reject this combination,
5251 indicate that by returning the CLOBBER ourselves, rather than
5252 an expression containing it. This will speed things up as
5253 well as prevent accidents where two CLOBBERs are considered
5254 to be equal, thus producing an incorrect simplification. */
5256 if (GET_CODE (new_rtx) == CLOBBER && XEXP (new_rtx, 0) == const0_rtx)
5259 if (GET_CODE (x) == SUBREG
5260 && (CONST_INT_P (new_rtx)
5261 || GET_CODE (new_rtx) == CONST_DOUBLE))
5263 enum machine_mode mode = GET_MODE (x);
5265 x = simplify_subreg (GET_MODE (x), new_rtx,
5266 GET_MODE (SUBREG_REG (x)),
5269 x = gen_rtx_CLOBBER (mode, const0_rtx);
5271 else if (CONST_INT_P (new_rtx)
5272 && GET_CODE (x) == ZERO_EXTEND)
5274 x = simplify_unary_operation (ZERO_EXTEND, GET_MODE (x),
5275 new_rtx, GET_MODE (XEXP (x, 0)));
5279 SUBST (XEXP (x, i), new_rtx);
5284 /* Check if we are loading something from the constant pool via float
5285 extension; in this case we would undo compress_float_constant
5286 optimization and degenerate constant load to an immediate value. */
5287 if (GET_CODE (x) == FLOAT_EXTEND
5288 && MEM_P (XEXP (x, 0))
5289 && MEM_READONLY_P (XEXP (x, 0)))
5291 rtx tmp = avoid_constant_pool_reference (x);
5296 /* Try to simplify X. If the simplification changed the code, it is likely
5297 that further simplification will help, so loop, but limit the number
5298 of repetitions that will be performed. */
5300 for (i = 0; i < 4; i++)
5302 /* If X is sufficiently simple, don't bother trying to do anything
5304 if (code != CONST_INT && code != REG && code != CLOBBER)
5305 x = combine_simplify_rtx (x, op0_mode, in_dest, in_cond);
5307 if (GET_CODE (x) == code)
5310 code = GET_CODE (x);
5312 /* We no longer know the original mode of operand 0 since we
5313 have changed the form of X) */
5314 op0_mode = VOIDmode;
5320 /* Simplify X, a piece of RTL. We just operate on the expression at the
5321 outer level; call `subst' to simplify recursively. Return the new
5324 OP0_MODE is the original mode of XEXP (x, 0). IN_DEST is nonzero
5325 if we are inside a SET_DEST. IN_COND is nonzero if we are at the top level
5329 combine_simplify_rtx (rtx x, enum machine_mode op0_mode, int in_dest,
5332 enum rtx_code code = GET_CODE (x);
5333 enum machine_mode mode = GET_MODE (x);
5337 /* If this is a commutative operation, put a constant last and a complex
5338 expression first. We don't need to do this for comparisons here. */
5339 if (COMMUTATIVE_ARITH_P (x)
5340 && swap_commutative_operands_p (XEXP (x, 0), XEXP (x, 1)))
5343 SUBST (XEXP (x, 0), XEXP (x, 1));
5344 SUBST (XEXP (x, 1), temp);
5347 /* If this is a simple operation applied to an IF_THEN_ELSE, try
5348 applying it to the arms of the IF_THEN_ELSE. This often simplifies
5349 things. Check for cases where both arms are testing the same
5352 Don't do anything if all operands are very simple. */
5355 && ((!OBJECT_P (XEXP (x, 0))
5356 && ! (GET_CODE (XEXP (x, 0)) == SUBREG
5357 && OBJECT_P (SUBREG_REG (XEXP (x, 0)))))
5358 || (!OBJECT_P (XEXP (x, 1))
5359 && ! (GET_CODE (XEXP (x, 1)) == SUBREG
5360 && OBJECT_P (SUBREG_REG (XEXP (x, 1)))))))
5362 && (!OBJECT_P (XEXP (x, 0))
5363 && ! (GET_CODE (XEXP (x, 0)) == SUBREG
5364 && OBJECT_P (SUBREG_REG (XEXP (x, 0)))))))
5366 rtx cond, true_rtx, false_rtx;
5368 cond = if_then_else_cond (x, &true_rtx, &false_rtx);
5370 /* If everything is a comparison, what we have is highly unlikely
5371 to be simpler, so don't use it. */
5372 && ! (COMPARISON_P (x)
5373 && (COMPARISON_P (true_rtx) || COMPARISON_P (false_rtx))))
5375 rtx cop1 = const0_rtx;
5376 enum rtx_code cond_code = simplify_comparison (NE, &cond, &cop1);
5378 if (cond_code == NE && COMPARISON_P (cond))
5381 /* Simplify the alternative arms; this may collapse the true and
5382 false arms to store-flag values. Be careful to use copy_rtx
5383 here since true_rtx or false_rtx might share RTL with x as a
5384 result of the if_then_else_cond call above. */
5385 true_rtx = subst (copy_rtx (true_rtx), pc_rtx, pc_rtx, 0, 0, 0);
5386 false_rtx = subst (copy_rtx (false_rtx), pc_rtx, pc_rtx, 0, 0, 0);
5388 /* If true_rtx and false_rtx are not general_operands, an if_then_else
5389 is unlikely to be simpler. */
5390 if (general_operand (true_rtx, VOIDmode)
5391 && general_operand (false_rtx, VOIDmode))
5393 enum rtx_code reversed;
5395 /* Restarting if we generate a store-flag expression will cause
5396 us to loop. Just drop through in this case. */
5398 /* If the result values are STORE_FLAG_VALUE and zero, we can
5399 just make the comparison operation. */
5400 if (true_rtx == const_true_rtx && false_rtx == const0_rtx)
5401 x = simplify_gen_relational (cond_code, mode, VOIDmode,
5403 else if (true_rtx == const0_rtx && false_rtx == const_true_rtx
5404 && ((reversed = reversed_comparison_code_parts
5405 (cond_code, cond, cop1, NULL))
5407 x = simplify_gen_relational (reversed, mode, VOIDmode,
5410 /* Likewise, we can make the negate of a comparison operation
5411 if the result values are - STORE_FLAG_VALUE and zero. */
5412 else if (CONST_INT_P (true_rtx)
5413 && INTVAL (true_rtx) == - STORE_FLAG_VALUE
5414 && false_rtx == const0_rtx)
5415 x = simplify_gen_unary (NEG, mode,
5416 simplify_gen_relational (cond_code,
5420 else if (CONST_INT_P (false_rtx)
5421 && INTVAL (false_rtx) == - STORE_FLAG_VALUE
5422 && true_rtx == const0_rtx
5423 && ((reversed = reversed_comparison_code_parts
5424 (cond_code, cond, cop1, NULL))
5426 x = simplify_gen_unary (NEG, mode,
5427 simplify_gen_relational (reversed,
5432 return gen_rtx_IF_THEN_ELSE (mode,
5433 simplify_gen_relational (cond_code,
5438 true_rtx, false_rtx);
5440 code = GET_CODE (x);
5441 op0_mode = VOIDmode;
5446 /* Try to fold this expression in case we have constants that weren't
5449 switch (GET_RTX_CLASS (code))
5452 if (op0_mode == VOIDmode)
5453 op0_mode = GET_MODE (XEXP (x, 0));
5454 temp = simplify_unary_operation (code, mode, XEXP (x, 0), op0_mode);
5457 case RTX_COMM_COMPARE:
5459 enum machine_mode cmp_mode = GET_MODE (XEXP (x, 0));
5460 if (cmp_mode == VOIDmode)
5462 cmp_mode = GET_MODE (XEXP (x, 1));
5463 if (cmp_mode == VOIDmode)
5464 cmp_mode = op0_mode;
5466 temp = simplify_relational_operation (code, mode, cmp_mode,
5467 XEXP (x, 0), XEXP (x, 1));
5470 case RTX_COMM_ARITH:
5472 temp = simplify_binary_operation (code, mode, XEXP (x, 0), XEXP (x, 1));
5474 case RTX_BITFIELD_OPS:
5476 temp = simplify_ternary_operation (code, mode, op0_mode, XEXP (x, 0),
5477 XEXP (x, 1), XEXP (x, 2));
5486 code = GET_CODE (temp);
5487 op0_mode = VOIDmode;
5488 mode = GET_MODE (temp);
5491 /* First see if we can apply the inverse distributive law. */
5492 if (code == PLUS || code == MINUS
5493 || code == AND || code == IOR || code == XOR)
5495 x = apply_distributive_law (x);
5496 code = GET_CODE (x);
5497 op0_mode = VOIDmode;
5500 /* If CODE is an associative operation not otherwise handled, see if we
5501 can associate some operands. This can win if they are constants or
5502 if they are logically related (i.e. (a & b) & a). */
5503 if ((code == PLUS || code == MINUS || code == MULT || code == DIV
5504 || code == AND || code == IOR || code == XOR
5505 || code == SMAX || code == SMIN || code == UMAX || code == UMIN)
5506 && ((INTEGRAL_MODE_P (mode) && code != DIV)
5507 || (flag_associative_math && FLOAT_MODE_P (mode))))
5509 if (GET_CODE (XEXP (x, 0)) == code)
5511 rtx other = XEXP (XEXP (x, 0), 0);
5512 rtx inner_op0 = XEXP (XEXP (x, 0), 1);
5513 rtx inner_op1 = XEXP (x, 1);
5516 /* Make sure we pass the constant operand if any as the second
5517 one if this is a commutative operation. */
5518 if (CONSTANT_P (inner_op0) && COMMUTATIVE_ARITH_P (x))
5520 rtx tem = inner_op0;
5521 inner_op0 = inner_op1;
5524 inner = simplify_binary_operation (code == MINUS ? PLUS
5525 : code == DIV ? MULT
5527 mode, inner_op0, inner_op1);
5529 /* For commutative operations, try the other pair if that one
5531 if (inner == 0 && COMMUTATIVE_ARITH_P (x))
5533 other = XEXP (XEXP (x, 0), 1);
5534 inner = simplify_binary_operation (code, mode,
5535 XEXP (XEXP (x, 0), 0),
5540 return simplify_gen_binary (code, mode, other, inner);
5544 /* A little bit of algebraic simplification here. */
5548 /* Ensure that our address has any ASHIFTs converted to MULT in case
5549 address-recognizing predicates are called later. */
5550 temp = make_compound_operation (XEXP (x, 0), MEM);
5551 SUBST (XEXP (x, 0), temp);
5555 if (op0_mode == VOIDmode)
5556 op0_mode = GET_MODE (SUBREG_REG (x));
5558 /* See if this can be moved to simplify_subreg. */
5559 if (CONSTANT_P (SUBREG_REG (x))
5560 && subreg_lowpart_offset (mode, op0_mode) == SUBREG_BYTE (x)
5561 /* Don't call gen_lowpart if the inner mode
5562 is VOIDmode and we cannot simplify it, as SUBREG without
5563 inner mode is invalid. */
5564 && (GET_MODE (SUBREG_REG (x)) != VOIDmode
5565 || gen_lowpart_common (mode, SUBREG_REG (x))))
5566 return gen_lowpart (mode, SUBREG_REG (x));
5568 if (GET_MODE_CLASS (GET_MODE (SUBREG_REG (x))) == MODE_CC)
5572 temp = simplify_subreg (mode, SUBREG_REG (x), op0_mode,
5578 /* Don't change the mode of the MEM if that would change the meaning
5580 if (MEM_P (SUBREG_REG (x))
5581 && (MEM_VOLATILE_P (SUBREG_REG (x))
5582 || mode_dependent_address_p (XEXP (SUBREG_REG (x), 0))))
5583 return gen_rtx_CLOBBER (mode, const0_rtx);
5585 /* Note that we cannot do any narrowing for non-constants since
5586 we might have been counting on using the fact that some bits were
5587 zero. We now do this in the SET. */
5592 temp = expand_compound_operation (XEXP (x, 0));
5594 /* For C equal to the width of MODE minus 1, (neg (ashiftrt X C)) can be
5595 replaced by (lshiftrt X C). This will convert
5596 (neg (sign_extract X 1 Y)) to (zero_extract X 1 Y). */
5598 if (GET_CODE (temp) == ASHIFTRT
5599 && CONST_INT_P (XEXP (temp, 1))
5600 && INTVAL (XEXP (temp, 1)) == GET_MODE_PRECISION (mode) - 1)
5601 return simplify_shift_const (NULL_RTX, LSHIFTRT, mode, XEXP (temp, 0),
5602 INTVAL (XEXP (temp, 1)));
5604 /* If X has only a single bit that might be nonzero, say, bit I, convert
5605 (neg X) to (ashiftrt (ashift X C-I) C-I) where C is the bitsize of
5606 MODE minus 1. This will convert (neg (zero_extract X 1 Y)) to
5607 (sign_extract X 1 Y). But only do this if TEMP isn't a register
5608 or a SUBREG of one since we'd be making the expression more
5609 complex if it was just a register. */
5612 && ! (GET_CODE (temp) == SUBREG
5613 && REG_P (SUBREG_REG (temp)))
5614 && (i = exact_log2 (nonzero_bits (temp, mode))) >= 0)
5616 rtx temp1 = simplify_shift_const
5617 (NULL_RTX, ASHIFTRT, mode,
5618 simplify_shift_const (NULL_RTX, ASHIFT, mode, temp,
5619 GET_MODE_PRECISION (mode) - 1 - i),
5620 GET_MODE_PRECISION (mode) - 1 - i);
5622 /* If all we did was surround TEMP with the two shifts, we
5623 haven't improved anything, so don't use it. Otherwise,
5624 we are better off with TEMP1. */
5625 if (GET_CODE (temp1) != ASHIFTRT
5626 || GET_CODE (XEXP (temp1, 0)) != ASHIFT
5627 || XEXP (XEXP (temp1, 0), 0) != temp)
5633 /* We can't handle truncation to a partial integer mode here
5634 because we don't know the real bitsize of the partial
5636 if (GET_MODE_CLASS (mode) == MODE_PARTIAL_INT)
5639 if (HWI_COMPUTABLE_MODE_P (mode))
5641 force_to_mode (XEXP (x, 0), GET_MODE (XEXP (x, 0)),
5642 GET_MODE_MASK (mode), 0));
5644 /* We can truncate a constant value and return it. */
5645 if (CONST_INT_P (XEXP (x, 0)))
5646 return gen_int_mode (INTVAL (XEXP (x, 0)), mode);
5648 /* Similarly to what we do in simplify-rtx.c, a truncate of a register
5649 whose value is a comparison can be replaced with a subreg if
5650 STORE_FLAG_VALUE permits. */
5651 if (HWI_COMPUTABLE_MODE_P (mode)
5652 && (STORE_FLAG_VALUE & ~GET_MODE_MASK (mode)) == 0
5653 && (temp = get_last_value (XEXP (x, 0)))
5654 && COMPARISON_P (temp))
5655 return gen_lowpart (mode, XEXP (x, 0));
5659 /* (const (const X)) can become (const X). Do it this way rather than
5660 returning the inner CONST since CONST can be shared with a
5662 if (GET_CODE (XEXP (x, 0)) == CONST)
5663 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
5668 /* Convert (lo_sum (high FOO) FOO) to FOO. This is necessary so we
5669 can add in an offset. find_split_point will split this address up
5670 again if it doesn't match. */
5671 if (GET_CODE (XEXP (x, 0)) == HIGH
5672 && rtx_equal_p (XEXP (XEXP (x, 0), 0), XEXP (x, 1)))
5678 /* (plus (xor (and <foo> (const_int pow2 - 1)) <c>) <-c>)
5679 when c is (const_int (pow2 + 1) / 2) is a sign extension of a
5680 bit-field and can be replaced by either a sign_extend or a
5681 sign_extract. The `and' may be a zero_extend and the two
5682 <c>, -<c> constants may be reversed. */
5683 if (GET_CODE (XEXP (x, 0)) == XOR
5684 && CONST_INT_P (XEXP (x, 1))
5685 && CONST_INT_P (XEXP (XEXP (x, 0), 1))
5686 && INTVAL (XEXP (x, 1)) == -INTVAL (XEXP (XEXP (x, 0), 1))
5687 && ((i = exact_log2 (UINTVAL (XEXP (XEXP (x, 0), 1)))) >= 0
5688 || (i = exact_log2 (UINTVAL (XEXP (x, 1)))) >= 0)
5689 && HWI_COMPUTABLE_MODE_P (mode)
5690 && ((GET_CODE (XEXP (XEXP (x, 0), 0)) == AND
5691 && CONST_INT_P (XEXP (XEXP (XEXP (x, 0), 0), 1))
5692 && (UINTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1))
5693 == ((unsigned HOST_WIDE_INT) 1 << (i + 1)) - 1))
5694 || (GET_CODE (XEXP (XEXP (x, 0), 0)) == ZERO_EXTEND
5695 && (GET_MODE_PRECISION (GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)))
5696 == (unsigned int) i + 1))))
5697 return simplify_shift_const
5698 (NULL_RTX, ASHIFTRT, mode,
5699 simplify_shift_const (NULL_RTX, ASHIFT, mode,
5700 XEXP (XEXP (XEXP (x, 0), 0), 0),
5701 GET_MODE_PRECISION (mode) - (i + 1)),
5702 GET_MODE_PRECISION (mode) - (i + 1));
5704 /* If only the low-order bit of X is possibly nonzero, (plus x -1)
5705 can become (ashiftrt (ashift (xor x 1) C) C) where C is
5706 the bitsize of the mode - 1. This allows simplification of
5707 "a = (b & 8) == 0;" */
5708 if (XEXP (x, 1) == constm1_rtx
5709 && !REG_P (XEXP (x, 0))
5710 && ! (GET_CODE (XEXP (x, 0)) == SUBREG
5711 && REG_P (SUBREG_REG (XEXP (x, 0))))
5712 && nonzero_bits (XEXP (x, 0), mode) == 1)
5713 return simplify_shift_const (NULL_RTX, ASHIFTRT, mode,
5714 simplify_shift_const (NULL_RTX, ASHIFT, mode,
5715 gen_rtx_XOR (mode, XEXP (x, 0), const1_rtx),
5716 GET_MODE_PRECISION (mode) - 1),
5717 GET_MODE_PRECISION (mode) - 1);
5719 /* If we are adding two things that have no bits in common, convert
5720 the addition into an IOR. This will often be further simplified,
5721 for example in cases like ((a & 1) + (a & 2)), which can
5724 if (HWI_COMPUTABLE_MODE_P (mode)
5725 && (nonzero_bits (XEXP (x, 0), mode)
5726 & nonzero_bits (XEXP (x, 1), mode)) == 0)
5728 /* Try to simplify the expression further. */
5729 rtx tor = simplify_gen_binary (IOR, mode, XEXP (x, 0), XEXP (x, 1));
5730 temp = combine_simplify_rtx (tor, VOIDmode, in_dest, 0);
5732 /* If we could, great. If not, do not go ahead with the IOR
5733 replacement, since PLUS appears in many special purpose
5734 address arithmetic instructions. */
5735 if (GET_CODE (temp) != CLOBBER
5736 && (GET_CODE (temp) != IOR
5737 || ((XEXP (temp, 0) != XEXP (x, 0)
5738 || XEXP (temp, 1) != XEXP (x, 1))
5739 && (XEXP (temp, 0) != XEXP (x, 1)
5740 || XEXP (temp, 1) != XEXP (x, 0)))))
5746 /* (minus <foo> (and <foo> (const_int -pow2))) becomes
5747 (and <foo> (const_int pow2-1)) */
5748 if (GET_CODE (XEXP (x, 1)) == AND
5749 && CONST_INT_P (XEXP (XEXP (x, 1), 1))
5750 && exact_log2 (-UINTVAL (XEXP (XEXP (x, 1), 1))) >= 0
5751 && rtx_equal_p (XEXP (XEXP (x, 1), 0), XEXP (x, 0)))
5752 return simplify_and_const_int (NULL_RTX, mode, XEXP (x, 0),
5753 -INTVAL (XEXP (XEXP (x, 1), 1)) - 1);
5757 /* If we have (mult (plus A B) C), apply the distributive law and then
5758 the inverse distributive law to see if things simplify. This
5759 occurs mostly in addresses, often when unrolling loops. */
5761 if (GET_CODE (XEXP (x, 0)) == PLUS)
5763 rtx result = distribute_and_simplify_rtx (x, 0);
5768 /* Try simplify a*(b/c) as (a*b)/c. */
5769 if (FLOAT_MODE_P (mode) && flag_associative_math
5770 && GET_CODE (XEXP (x, 0)) == DIV)
5772 rtx tem = simplify_binary_operation (MULT, mode,
5773 XEXP (XEXP (x, 0), 0),
5776 return simplify_gen_binary (DIV, mode, tem, XEXP (XEXP (x, 0), 1));
5781 /* If this is a divide by a power of two, treat it as a shift if
5782 its first operand is a shift. */
5783 if (CONST_INT_P (XEXP (x, 1))
5784 && (i = exact_log2 (UINTVAL (XEXP (x, 1)))) >= 0
5785 && (GET_CODE (XEXP (x, 0)) == ASHIFT
5786 || GET_CODE (XEXP (x, 0)) == LSHIFTRT
5787 || GET_CODE (XEXP (x, 0)) == ASHIFTRT
5788 || GET_CODE (XEXP (x, 0)) == ROTATE
5789 || GET_CODE (XEXP (x, 0)) == ROTATERT))
5790 return simplify_shift_const (NULL_RTX, LSHIFTRT, mode, XEXP (x, 0), i);
5794 case GT: case GTU: case GE: case GEU:
5795 case LT: case LTU: case LE: case LEU:
5796 case UNEQ: case LTGT:
5797 case UNGT: case UNGE:
5798 case UNLT: case UNLE:
5799 case UNORDERED: case ORDERED:
5800 /* If the first operand is a condition code, we can't do anything
5802 if (GET_CODE (XEXP (x, 0)) == COMPARE
5803 || (GET_MODE_CLASS (GET_MODE (XEXP (x, 0))) != MODE_CC
5804 && ! CC0_P (XEXP (x, 0))))
5806 rtx op0 = XEXP (x, 0);
5807 rtx op1 = XEXP (x, 1);
5808 enum rtx_code new_code;
5810 if (GET_CODE (op0) == COMPARE)
5811 op1 = XEXP (op0, 1), op0 = XEXP (op0, 0);
5813 /* Simplify our comparison, if possible. */
5814 new_code = simplify_comparison (code, &op0, &op1);
5816 /* If STORE_FLAG_VALUE is 1, we can convert (ne x 0) to simply X
5817 if only the low-order bit is possibly nonzero in X (such as when
5818 X is a ZERO_EXTRACT of one bit). Similarly, we can convert EQ to
5819 (xor X 1) or (minus 1 X); we use the former. Finally, if X is
5820 known to be either 0 or -1, NE becomes a NEG and EQ becomes
5823 Remove any ZERO_EXTRACT we made when thinking this was a
5824 comparison. It may now be simpler to use, e.g., an AND. If a
5825 ZERO_EXTRACT is indeed appropriate, it will be placed back by
5826 the call to make_compound_operation in the SET case.
5828 Don't apply these optimizations if the caller would
5829 prefer a comparison rather than a value.
5830 E.g., for the condition in an IF_THEN_ELSE most targets need
5831 an explicit comparison. */
5836 else if (STORE_FLAG_VALUE == 1
5837 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
5838 && op1 == const0_rtx
5839 && mode == GET_MODE (op0)
5840 && nonzero_bits (op0, mode) == 1)
5841 return gen_lowpart (mode,
5842 expand_compound_operation (op0));
5844 else if (STORE_FLAG_VALUE == 1
5845 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
5846 && op1 == const0_rtx
5847 && mode == GET_MODE (op0)
5848 && (num_sign_bit_copies (op0, mode)
5849 == GET_MODE_PRECISION (mode)))
5851 op0 = expand_compound_operation (op0);
5852 return simplify_gen_unary (NEG, mode,
5853 gen_lowpart (mode, op0),
5857 else if (STORE_FLAG_VALUE == 1
5858 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
5859 && op1 == const0_rtx
5860 && mode == GET_MODE (op0)
5861 && nonzero_bits (op0, mode) == 1)
5863 op0 = expand_compound_operation (op0);
5864 return simplify_gen_binary (XOR, mode,
5865 gen_lowpart (mode, op0),
5869 else if (STORE_FLAG_VALUE == 1
5870 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
5871 && op1 == const0_rtx
5872 && mode == GET_MODE (op0)
5873 && (num_sign_bit_copies (op0, mode)
5874 == GET_MODE_PRECISION (mode)))
5876 op0 = expand_compound_operation (op0);
5877 return plus_constant (gen_lowpart (mode, op0), 1);
5880 /* If STORE_FLAG_VALUE is -1, we have cases similar to
5885 else if (STORE_FLAG_VALUE == -1
5886 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
5887 && op1 == const0_rtx
5888 && (num_sign_bit_copies (op0, mode)
5889 == GET_MODE_PRECISION (mode)))
5890 return gen_lowpart (mode,
5891 expand_compound_operation (op0));
5893 else if (STORE_FLAG_VALUE == -1
5894 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
5895 && op1 == const0_rtx
5896 && mode == GET_MODE (op0)
5897 && nonzero_bits (op0, mode) == 1)
5899 op0 = expand_compound_operation (op0);
5900 return simplify_gen_unary (NEG, mode,
5901 gen_lowpart (mode, op0),
5905 else if (STORE_FLAG_VALUE == -1
5906 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
5907 && op1 == const0_rtx
5908 && mode == GET_MODE (op0)
5909 && (num_sign_bit_copies (op0, mode)
5910 == GET_MODE_PRECISION (mode)))
5912 op0 = expand_compound_operation (op0);
5913 return simplify_gen_unary (NOT, mode,
5914 gen_lowpart (mode, op0),
5918 /* If X is 0/1, (eq X 0) is X-1. */
5919 else if (STORE_FLAG_VALUE == -1
5920 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
5921 && op1 == const0_rtx
5922 && mode == GET_MODE (op0)
5923 && nonzero_bits (op0, mode) == 1)
5925 op0 = expand_compound_operation (op0);
5926 return plus_constant (gen_lowpart (mode, op0), -1);
5929 /* If STORE_FLAG_VALUE says to just test the sign bit and X has just
5930 one bit that might be nonzero, we can convert (ne x 0) to
5931 (ashift x c) where C puts the bit in the sign bit. Remove any
5932 AND with STORE_FLAG_VALUE when we are done, since we are only
5933 going to test the sign bit. */
5934 if (new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
5935 && HWI_COMPUTABLE_MODE_P (mode)
5936 && val_signbit_p (mode, STORE_FLAG_VALUE)
5937 && op1 == const0_rtx
5938 && mode == GET_MODE (op0)
5939 && (i = exact_log2 (nonzero_bits (op0, mode))) >= 0)
5941 x = simplify_shift_const (NULL_RTX, ASHIFT, mode,
5942 expand_compound_operation (op0),
5943 GET_MODE_PRECISION (mode) - 1 - i);
5944 if (GET_CODE (x) == AND && XEXP (x, 1) == const_true_rtx)
5950 /* If the code changed, return a whole new comparison. */
5951 if (new_code != code)
5952 return gen_rtx_fmt_ee (new_code, mode, op0, op1);
5954 /* Otherwise, keep this operation, but maybe change its operands.
5955 This also converts (ne (compare FOO BAR) 0) to (ne FOO BAR). */
5956 SUBST (XEXP (x, 0), op0);
5957 SUBST (XEXP (x, 1), op1);
5962 return simplify_if_then_else (x);
5968 /* If we are processing SET_DEST, we are done. */
5972 return expand_compound_operation (x);
5975 return simplify_set (x);
5979 return simplify_logical (x);
5986 /* If this is a shift by a constant amount, simplify it. */
5987 if (CONST_INT_P (XEXP (x, 1)))
5988 return simplify_shift_const (x, code, mode, XEXP (x, 0),
5989 INTVAL (XEXP (x, 1)));
5991 else if (SHIFT_COUNT_TRUNCATED && !REG_P (XEXP (x, 1)))
5993 force_to_mode (XEXP (x, 1), GET_MODE (XEXP (x, 1)),
5994 ((unsigned HOST_WIDE_INT) 1
5995 << exact_log2 (GET_MODE_BITSIZE (GET_MODE (x))))
6007 /* Simplify X, an IF_THEN_ELSE expression. Return the new expression. */
6010 simplify_if_then_else (rtx x)
6012 enum machine_mode mode = GET_MODE (x);
6013 rtx cond = XEXP (x, 0);
6014 rtx true_rtx = XEXP (x, 1);
6015 rtx false_rtx = XEXP (x, 2);
6016 enum rtx_code true_code = GET_CODE (cond);
6017 int comparison_p = COMPARISON_P (cond);
6020 enum rtx_code false_code;
6023 /* Simplify storing of the truth value. */
6024 if (comparison_p && true_rtx == const_true_rtx && false_rtx == const0_rtx)
6025 return simplify_gen_relational (true_code, mode, VOIDmode,
6026 XEXP (cond, 0), XEXP (cond, 1));
6028 /* Also when the truth value has to be reversed. */
6030 && true_rtx == const0_rtx && false_rtx == const_true_rtx
6031 && (reversed = reversed_comparison (cond, mode)))
6034 /* Sometimes we can simplify the arm of an IF_THEN_ELSE if a register used
6035 in it is being compared against certain values. Get the true and false
6036 comparisons and see if that says anything about the value of each arm. */
6039 && ((false_code = reversed_comparison_code (cond, NULL))
6041 && REG_P (XEXP (cond, 0)))
6044 rtx from = XEXP (cond, 0);
6045 rtx true_val = XEXP (cond, 1);
6046 rtx false_val = true_val;
6049 /* If FALSE_CODE is EQ, swap the codes and arms. */
6051 if (false_code == EQ)
6053 swapped = 1, true_code = EQ, false_code = NE;
6054 temp = true_rtx, true_rtx = false_rtx, false_rtx = temp;
6057 /* If we are comparing against zero and the expression being tested has
6058 only a single bit that might be nonzero, that is its value when it is
6059 not equal to zero. Similarly if it is known to be -1 or 0. */
6061 if (true_code == EQ && true_val == const0_rtx
6062 && exact_log2 (nzb = nonzero_bits (from, GET_MODE (from))) >= 0)
6065 false_val = gen_int_mode (nzb, GET_MODE (from));
6067 else if (true_code == EQ && true_val == const0_rtx
6068 && (num_sign_bit_copies (from, GET_MODE (from))
6069 == GET_MODE_PRECISION (GET_MODE (from))))
6072 false_val = constm1_rtx;
6075 /* Now simplify an arm if we know the value of the register in the
6076 branch and it is used in the arm. Be careful due to the potential
6077 of locally-shared RTL. */
6079 if (reg_mentioned_p (from, true_rtx))
6080 true_rtx = subst (known_cond (copy_rtx (true_rtx), true_code,
6082 pc_rtx, pc_rtx, 0, 0, 0);
6083 if (reg_mentioned_p (from, false_rtx))
6084 false_rtx = subst (known_cond (copy_rtx (false_rtx), false_code,
6086 pc_rtx, pc_rtx, 0, 0, 0);
6088 SUBST (XEXP (x, 1), swapped ? false_rtx : true_rtx);
6089 SUBST (XEXP (x, 2), swapped ? true_rtx : false_rtx);
6091 true_rtx = XEXP (x, 1);
6092 false_rtx = XEXP (x, 2);
6093 true_code = GET_CODE (cond);
6096 /* If we have (if_then_else FOO (pc) (label_ref BAR)) and FOO can be
6097 reversed, do so to avoid needing two sets of patterns for
6098 subtract-and-branch insns. Similarly if we have a constant in the true
6099 arm, the false arm is the same as the first operand of the comparison, or
6100 the false arm is more complicated than the true arm. */
6103 && reversed_comparison_code (cond, NULL) != UNKNOWN
6104 && (true_rtx == pc_rtx
6105 || (CONSTANT_P (true_rtx)
6106 && !CONST_INT_P (false_rtx) && false_rtx != pc_rtx)
6107 || true_rtx == const0_rtx
6108 || (OBJECT_P (true_rtx) && !OBJECT_P (false_rtx))
6109 || (GET_CODE (true_rtx) == SUBREG && OBJECT_P (SUBREG_REG (true_rtx))
6110 && !OBJECT_P (false_rtx))
6111 || reg_mentioned_p (true_rtx, false_rtx)
6112 || rtx_equal_p (false_rtx, XEXP (cond, 0))))
6114 true_code = reversed_comparison_code (cond, NULL);
6115 SUBST (XEXP (x, 0), reversed_comparison (cond, GET_MODE (cond)));
6116 SUBST (XEXP (x, 1), false_rtx);
6117 SUBST (XEXP (x, 2), true_rtx);
6119 temp = true_rtx, true_rtx = false_rtx, false_rtx = temp;
6122 /* It is possible that the conditional has been simplified out. */
6123 true_code = GET_CODE (cond);
6124 comparison_p = COMPARISON_P (cond);
6127 /* If the two arms are identical, we don't need the comparison. */
6129 if (rtx_equal_p (true_rtx, false_rtx) && ! side_effects_p (cond))
6132 /* Convert a == b ? b : a to "a". */
6133 if (true_code == EQ && ! side_effects_p (cond)
6134 && !HONOR_NANS (mode)
6135 && rtx_equal_p (XEXP (cond, 0), false_rtx)
6136 && rtx_equal_p (XEXP (cond, 1), true_rtx))
6138 else if (true_code == NE && ! side_effects_p (cond)
6139 && !HONOR_NANS (mode)
6140 && rtx_equal_p (XEXP (cond, 0), true_rtx)
6141 && rtx_equal_p (XEXP (cond, 1), false_rtx))
6144 /* Look for cases where we have (abs x) or (neg (abs X)). */
6146 if (GET_MODE_CLASS (mode) == MODE_INT
6148 && XEXP (cond, 1) == const0_rtx
6149 && GET_CODE (false_rtx) == NEG
6150 && rtx_equal_p (true_rtx, XEXP (false_rtx, 0))
6151 && rtx_equal_p (true_rtx, XEXP (cond, 0))
6152 && ! side_effects_p (true_rtx))
6157 return simplify_gen_unary (ABS, mode, true_rtx, mode);
6161 simplify_gen_unary (NEG, mode,
6162 simplify_gen_unary (ABS, mode, true_rtx, mode),
6168 /* Look for MIN or MAX. */
6170 if ((! FLOAT_MODE_P (mode) || flag_unsafe_math_optimizations)
6172 && rtx_equal_p (XEXP (cond, 0), true_rtx)
6173 && rtx_equal_p (XEXP (cond, 1), false_rtx)
6174 && ! side_effects_p (cond))
6179 return simplify_gen_binary (SMAX, mode, true_rtx, false_rtx);
6182 return simplify_gen_binary (SMIN, mode, true_rtx, false_rtx);
6185 return simplify_gen_binary (UMAX, mode, true_rtx, false_rtx);
6188 return simplify_gen_binary (UMIN, mode, true_rtx, false_rtx);
6193 /* If we have (if_then_else COND (OP Z C1) Z) and OP is an identity when its
6194 second operand is zero, this can be done as (OP Z (mult COND C2)) where
6195 C2 = C1 * STORE_FLAG_VALUE. Similarly if OP has an outer ZERO_EXTEND or
6196 SIGN_EXTEND as long as Z is already extended (so we don't destroy it).
6197 We can do this kind of thing in some cases when STORE_FLAG_VALUE is
6198 neither 1 or -1, but it isn't worth checking for. */
6200 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
6202 && GET_MODE_CLASS (mode) == MODE_INT
6203 && ! side_effects_p (x))
6205 rtx t = make_compound_operation (true_rtx, SET);
6206 rtx f = make_compound_operation (false_rtx, SET);
6207 rtx cond_op0 = XEXP (cond, 0);
6208 rtx cond_op1 = XEXP (cond, 1);
6209 enum rtx_code op = UNKNOWN, extend_op = UNKNOWN;
6210 enum machine_mode m = mode;
6211 rtx z = 0, c1 = NULL_RTX;
6213 if ((GET_CODE (t) == PLUS || GET_CODE (t) == MINUS
6214 || GET_CODE (t) == IOR || GET_CODE (t) == XOR
6215 || GET_CODE (t) == ASHIFT
6216 || GET_CODE (t) == LSHIFTRT || GET_CODE (t) == ASHIFTRT)
6217 && rtx_equal_p (XEXP (t, 0), f))
6218 c1 = XEXP (t, 1), op = GET_CODE (t), z = f;
6220 /* If an identity-zero op is commutative, check whether there
6221 would be a match if we swapped the operands. */
6222 else if ((GET_CODE (t) == PLUS || GET_CODE (t) == IOR
6223 || GET_CODE (t) == XOR)
6224 && rtx_equal_p (XEXP (t, 1), f))
6225 c1 = XEXP (t, 0), op = GET_CODE (t), z = f;
6226 else if (GET_CODE (t) == SIGN_EXTEND
6227 && (GET_CODE (XEXP (t, 0)) == PLUS
6228 || GET_CODE (XEXP (t, 0)) == MINUS
6229 || GET_CODE (XEXP (t, 0)) == IOR
6230 || GET_CODE (XEXP (t, 0)) == XOR
6231 || GET_CODE (XEXP (t, 0)) == ASHIFT
6232 || GET_CODE (XEXP (t, 0)) == LSHIFTRT
6233 || GET_CODE (XEXP (t, 0)) == ASHIFTRT)
6234 && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG
6235 && subreg_lowpart_p (XEXP (XEXP (t, 0), 0))
6236 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f)
6237 && (num_sign_bit_copies (f, GET_MODE (f))
6239 (GET_MODE_PRECISION (mode)
6240 - GET_MODE_PRECISION (GET_MODE (XEXP (XEXP (t, 0), 0))))))
6242 c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0));
6243 extend_op = SIGN_EXTEND;
6244 m = GET_MODE (XEXP (t, 0));
6246 else if (GET_CODE (t) == SIGN_EXTEND
6247 && (GET_CODE (XEXP (t, 0)) == PLUS
6248 || GET_CODE (XEXP (t, 0)) == IOR
6249 || GET_CODE (XEXP (t, 0)) == XOR)
6250 && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG
6251 && subreg_lowpart_p (XEXP (XEXP (t, 0), 1))
6252 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f)
6253 && (num_sign_bit_copies (f, GET_MODE (f))
6255 (GET_MODE_PRECISION (mode)
6256 - GET_MODE_PRECISION (GET_MODE (XEXP (XEXP (t, 0), 1))))))
6258 c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0));
6259 extend_op = SIGN_EXTEND;
6260 m = GET_MODE (XEXP (t, 0));
6262 else if (GET_CODE (t) == ZERO_EXTEND
6263 && (GET_CODE (XEXP (t, 0)) == PLUS
6264 || GET_CODE (XEXP (t, 0)) == MINUS
6265 || GET_CODE (XEXP (t, 0)) == IOR
6266 || GET_CODE (XEXP (t, 0)) == XOR
6267 || GET_CODE (XEXP (t, 0)) == ASHIFT
6268 || GET_CODE (XEXP (t, 0)) == LSHIFTRT
6269 || GET_CODE (XEXP (t, 0)) == ASHIFTRT)
6270 && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG
6271 && HWI_COMPUTABLE_MODE_P (mode)
6272 && subreg_lowpart_p (XEXP (XEXP (t, 0), 0))
6273 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f)
6274 && ((nonzero_bits (f, GET_MODE (f))
6275 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t, 0), 0))))
6278 c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0));
6279 extend_op = ZERO_EXTEND;
6280 m = GET_MODE (XEXP (t, 0));
6282 else if (GET_CODE (t) == ZERO_EXTEND
6283 && (GET_CODE (XEXP (t, 0)) == PLUS
6284 || GET_CODE (XEXP (t, 0)) == IOR
6285 || GET_CODE (XEXP (t, 0)) == XOR)
6286 && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG
6287 && HWI_COMPUTABLE_MODE_P (mode)
6288 && subreg_lowpart_p (XEXP (XEXP (t, 0), 1))
6289 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f)
6290 && ((nonzero_bits (f, GET_MODE (f))
6291 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t, 0), 1))))
6294 c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0));
6295 extend_op = ZERO_EXTEND;
6296 m = GET_MODE (XEXP (t, 0));
6301 temp = subst (simplify_gen_relational (true_code, m, VOIDmode,
6302 cond_op0, cond_op1),
6303 pc_rtx, pc_rtx, 0, 0, 0);
6304 temp = simplify_gen_binary (MULT, m, temp,
6305 simplify_gen_binary (MULT, m, c1,
6307 temp = subst (temp, pc_rtx, pc_rtx, 0, 0, 0);
6308 temp = simplify_gen_binary (op, m, gen_lowpart (m, z), temp);
6310 if (extend_op != UNKNOWN)
6311 temp = simplify_gen_unary (extend_op, mode, temp, m);
6317 /* If we have (if_then_else (ne A 0) C1 0) and either A is known to be 0 or
6318 1 and C1 is a single bit or A is known to be 0 or -1 and C1 is the
6319 negation of a single bit, we can convert this operation to a shift. We
6320 can actually do this more generally, but it doesn't seem worth it. */
6322 if (true_code == NE && XEXP (cond, 1) == const0_rtx
6323 && false_rtx == const0_rtx && CONST_INT_P (true_rtx)
6324 && ((1 == nonzero_bits (XEXP (cond, 0), mode)
6325 && (i = exact_log2 (UINTVAL (true_rtx))) >= 0)
6326 || ((num_sign_bit_copies (XEXP (cond, 0), mode)
6327 == GET_MODE_PRECISION (mode))
6328 && (i = exact_log2 (-UINTVAL (true_rtx))) >= 0)))
6330 simplify_shift_const (NULL_RTX, ASHIFT, mode,
6331 gen_lowpart (mode, XEXP (cond, 0)), i);
6333 /* (IF_THEN_ELSE (NE REG 0) (0) (8)) is REG for nonzero_bits (REG) == 8. */
6334 if (true_code == NE && XEXP (cond, 1) == const0_rtx
6335 && false_rtx == const0_rtx && CONST_INT_P (true_rtx)
6336 && GET_MODE (XEXP (cond, 0)) == mode
6337 && (UINTVAL (true_rtx) & GET_MODE_MASK (mode))
6338 == nonzero_bits (XEXP (cond, 0), mode)
6339 && (i = exact_log2 (UINTVAL (true_rtx) & GET_MODE_MASK (mode))) >= 0)
6340 return XEXP (cond, 0);
6345 /* Simplify X, a SET expression. Return the new expression. */
6348 simplify_set (rtx x)
6350 rtx src = SET_SRC (x);
6351 rtx dest = SET_DEST (x);
6352 enum machine_mode mode
6353 = GET_MODE (src) != VOIDmode ? GET_MODE (src) : GET_MODE (dest);
6357 /* (set (pc) (return)) gets written as (return). */
6358 if (GET_CODE (dest) == PC && ANY_RETURN_P (src))
6361 /* Now that we know for sure which bits of SRC we are using, see if we can
6362 simplify the expression for the object knowing that we only need the
6365 if (GET_MODE_CLASS (mode) == MODE_INT && HWI_COMPUTABLE_MODE_P (mode))
6367 src = force_to_mode (src, mode, ~(unsigned HOST_WIDE_INT) 0, 0);
6368 SUBST (SET_SRC (x), src);
6371 /* If we are setting CC0 or if the source is a COMPARE, look for the use of
6372 the comparison result and try to simplify it unless we already have used
6373 undobuf.other_insn. */
6374 if ((GET_MODE_CLASS (mode) == MODE_CC
6375 || GET_CODE (src) == COMPARE
6377 && (cc_use = find_single_use (dest, subst_insn, &other_insn)) != 0
6378 && (undobuf.other_insn == 0 || other_insn == undobuf.other_insn)
6379 && COMPARISON_P (*cc_use)
6380 && rtx_equal_p (XEXP (*cc_use, 0), dest))
6382 enum rtx_code old_code = GET_CODE (*cc_use);
6383 enum rtx_code new_code;
6385 int other_changed = 0;
6386 rtx inner_compare = NULL_RTX;
6387 enum machine_mode compare_mode = GET_MODE (dest);
6389 if (GET_CODE (src) == COMPARE)
6391 op0 = XEXP (src, 0), op1 = XEXP (src, 1);
6392 if (GET_CODE (op0) == COMPARE && op1 == const0_rtx)
6394 inner_compare = op0;
6395 op0 = XEXP (inner_compare, 0), op1 = XEXP (inner_compare, 1);
6399 op0 = src, op1 = CONST0_RTX (GET_MODE (src));
6401 tmp = simplify_relational_operation (old_code, compare_mode, VOIDmode,
6404 new_code = old_code;
6405 else if (!CONSTANT_P (tmp))
6407 new_code = GET_CODE (tmp);
6408 op0 = XEXP (tmp, 0);
6409 op1 = XEXP (tmp, 1);
6413 rtx pat = PATTERN (other_insn);
6414 undobuf.other_insn = other_insn;
6415 SUBST (*cc_use, tmp);
6417 /* Attempt to simplify CC user. */
6418 if (GET_CODE (pat) == SET)
6420 rtx new_rtx = simplify_rtx (SET_SRC (pat));
6421 if (new_rtx != NULL_RTX)
6422 SUBST (SET_SRC (pat), new_rtx);
6425 /* Convert X into a no-op move. */
6426 SUBST (SET_DEST (x), pc_rtx);
6427 SUBST (SET_SRC (x), pc_rtx);
6431 /* Simplify our comparison, if possible. */
6432 new_code = simplify_comparison (new_code, &op0, &op1);
6434 #ifdef SELECT_CC_MODE
6435 /* If this machine has CC modes other than CCmode, check to see if we
6436 need to use a different CC mode here. */
6437 if (GET_MODE_CLASS (GET_MODE (op0)) == MODE_CC)
6438 compare_mode = GET_MODE (op0);
6439 else if (inner_compare
6440 && GET_MODE_CLASS (GET_MODE (inner_compare)) == MODE_CC
6441 && new_code == old_code
6442 && op0 == XEXP (inner_compare, 0)
6443 && op1 == XEXP (inner_compare, 1))
6444 compare_mode = GET_MODE (inner_compare);
6446 compare_mode = SELECT_CC_MODE (new_code, op0, op1);
6449 /* If the mode changed, we have to change SET_DEST, the mode in the
6450 compare, and the mode in the place SET_DEST is used. If SET_DEST is
6451 a hard register, just build new versions with the proper mode. If it
6452 is a pseudo, we lose unless it is only time we set the pseudo, in
6453 which case we can safely change its mode. */
6454 if (compare_mode != GET_MODE (dest))
6456 if (can_change_dest_mode (dest, 0, compare_mode))
6458 unsigned int regno = REGNO (dest);
6461 if (regno < FIRST_PSEUDO_REGISTER)
6462 new_dest = gen_rtx_REG (compare_mode, regno);
6465 SUBST_MODE (regno_reg_rtx[regno], compare_mode);
6466 new_dest = regno_reg_rtx[regno];
6469 SUBST (SET_DEST (x), new_dest);
6470 SUBST (XEXP (*cc_use, 0), new_dest);
6477 #endif /* SELECT_CC_MODE */
6479 /* If the code changed, we have to build a new comparison in
6480 undobuf.other_insn. */
6481 if (new_code != old_code)
6483 int other_changed_previously = other_changed;
6484 unsigned HOST_WIDE_INT mask;
6485 rtx old_cc_use = *cc_use;
6487 SUBST (*cc_use, gen_rtx_fmt_ee (new_code, GET_MODE (*cc_use),
6491 /* If the only change we made was to change an EQ into an NE or
6492 vice versa, OP0 has only one bit that might be nonzero, and OP1
6493 is zero, check if changing the user of the condition code will
6494 produce a valid insn. If it won't, we can keep the original code
6495 in that insn by surrounding our operation with an XOR. */
6497 if (((old_code == NE && new_code == EQ)
6498 || (old_code == EQ && new_code == NE))
6499 && ! other_changed_previously && op1 == const0_rtx
6500 && HWI_COMPUTABLE_MODE_P (GET_MODE (op0))
6501 && exact_log2 (mask = nonzero_bits (op0, GET_MODE (op0))) >= 0)
6503 rtx pat = PATTERN (other_insn), note = 0;
6505 if ((recog_for_combine (&pat, other_insn, ¬e) < 0
6506 && ! check_asm_operands (pat)))
6508 *cc_use = old_cc_use;
6511 op0 = simplify_gen_binary (XOR, GET_MODE (op0),
6512 op0, GEN_INT (mask));
6518 undobuf.other_insn = other_insn;
6520 /* Otherwise, if we didn't previously have a COMPARE in the
6521 correct mode, we need one. */
6522 if (GET_CODE (src) != COMPARE || GET_MODE (src) != compare_mode)
6524 SUBST (SET_SRC (x), gen_rtx_COMPARE (compare_mode, op0, op1));
6527 else if (GET_MODE (op0) == compare_mode && op1 == const0_rtx)
6529 SUBST (SET_SRC (x), op0);
6532 /* Otherwise, update the COMPARE if needed. */
6533 else if (XEXP (src, 0) != op0 || XEXP (src, 1) != op1)
6535 SUBST (SET_SRC (x), gen_rtx_COMPARE (compare_mode, op0, op1));
6541 /* Get SET_SRC in a form where we have placed back any
6542 compound expressions. Then do the checks below. */
6543 src = make_compound_operation (src, SET);
6544 SUBST (SET_SRC (x), src);
6547 /* If we have (set x (subreg:m1 (op:m2 ...) 0)) with OP being some operation,
6548 and X being a REG or (subreg (reg)), we may be able to convert this to
6549 (set (subreg:m2 x) (op)).
6551 We can always do this if M1 is narrower than M2 because that means that
6552 we only care about the low bits of the result.
6554 However, on machines without WORD_REGISTER_OPERATIONS defined, we cannot
6555 perform a narrower operation than requested since the high-order bits will
6556 be undefined. On machine where it is defined, this transformation is safe
6557 as long as M1 and M2 have the same number of words. */
6559 if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src)
6560 && !OBJECT_P (SUBREG_REG (src))
6561 && (((GET_MODE_SIZE (GET_MODE (src)) + (UNITS_PER_WORD - 1))
6563 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (src)))
6564 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD))
6565 #ifndef WORD_REGISTER_OPERATIONS
6566 && (GET_MODE_SIZE (GET_MODE (src))
6567 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (src))))
6569 #ifdef CANNOT_CHANGE_MODE_CLASS
6570 && ! (REG_P (dest) && REGNO (dest) < FIRST_PSEUDO_REGISTER
6571 && REG_CANNOT_CHANGE_MODE_P (REGNO (dest),
6572 GET_MODE (SUBREG_REG (src)),
6576 || (GET_CODE (dest) == SUBREG
6577 && REG_P (SUBREG_REG (dest)))))
6579 SUBST (SET_DEST (x),
6580 gen_lowpart (GET_MODE (SUBREG_REG (src)),
6582 SUBST (SET_SRC (x), SUBREG_REG (src));
6584 src = SET_SRC (x), dest = SET_DEST (x);
6588 /* If we have (set (cc0) (subreg ...)), we try to remove the subreg
6591 && GET_CODE (src) == SUBREG
6592 && subreg_lowpart_p (src)
6593 && (GET_MODE_PRECISION (GET_MODE (src))
6594 < GET_MODE_PRECISION (GET_MODE (SUBREG_REG (src)))))
6596 rtx inner = SUBREG_REG (src);
6597 enum machine_mode inner_mode = GET_MODE (inner);
6599 /* Here we make sure that we don't have a sign bit on. */
6600 if (val_signbit_known_clear_p (GET_MODE (src),
6601 nonzero_bits (inner, inner_mode)))
6603 SUBST (SET_SRC (x), inner);
6609 #ifdef LOAD_EXTEND_OP
6610 /* If we have (set FOO (subreg:M (mem:N BAR) 0)) with M wider than N, this
6611 would require a paradoxical subreg. Replace the subreg with a
6612 zero_extend to avoid the reload that would otherwise be required. */
6614 if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src)
6615 && INTEGRAL_MODE_P (GET_MODE (SUBREG_REG (src)))
6616 && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src))) != UNKNOWN
6617 && SUBREG_BYTE (src) == 0
6618 && paradoxical_subreg_p (src)
6619 && MEM_P (SUBREG_REG (src)))
6622 gen_rtx_fmt_e (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src))),
6623 GET_MODE (src), SUBREG_REG (src)));
6629 /* If we don't have a conditional move, SET_SRC is an IF_THEN_ELSE, and we
6630 are comparing an item known to be 0 or -1 against 0, use a logical
6631 operation instead. Check for one of the arms being an IOR of the other
6632 arm with some value. We compute three terms to be IOR'ed together. In
6633 practice, at most two will be nonzero. Then we do the IOR's. */
6635 if (GET_CODE (dest) != PC
6636 && GET_CODE (src) == IF_THEN_ELSE
6637 && GET_MODE_CLASS (GET_MODE (src)) == MODE_INT
6638 && (GET_CODE (XEXP (src, 0)) == EQ || GET_CODE (XEXP (src, 0)) == NE)
6639 && XEXP (XEXP (src, 0), 1) == const0_rtx
6640 && GET_MODE (src) == GET_MODE (XEXP (XEXP (src, 0), 0))
6641 #ifdef HAVE_conditional_move
6642 && ! can_conditionally_move_p (GET_MODE (src))
6644 && (num_sign_bit_copies (XEXP (XEXP (src, 0), 0),
6645 GET_MODE (XEXP (XEXP (src, 0), 0)))
6646 == GET_MODE_PRECISION (GET_MODE (XEXP (XEXP (src, 0), 0))))
6647 && ! side_effects_p (src))
6649 rtx true_rtx = (GET_CODE (XEXP (src, 0)) == NE
6650 ? XEXP (src, 1) : XEXP (src, 2));
6651 rtx false_rtx = (GET_CODE (XEXP (src, 0)) == NE
6652 ? XEXP (src, 2) : XEXP (src, 1));
6653 rtx term1 = const0_rtx, term2, term3;
6655 if (GET_CODE (true_rtx) == IOR
6656 && rtx_equal_p (XEXP (true_rtx, 0), false_rtx))
6657 term1 = false_rtx, true_rtx = XEXP (true_rtx, 1), false_rtx = const0_rtx;
6658 else if (GET_CODE (true_rtx) == IOR
6659 && rtx_equal_p (XEXP (true_rtx, 1), false_rtx))
6660 term1 = false_rtx, true_rtx = XEXP (true_rtx, 0), false_rtx = const0_rtx;
6661 else if (GET_CODE (false_rtx) == IOR
6662 && rtx_equal_p (XEXP (false_rtx, 0), true_rtx))
6663 term1 = true_rtx, false_rtx = XEXP (false_rtx, 1), true_rtx = const0_rtx;
6664 else if (GET_CODE (false_rtx) == IOR
6665 && rtx_equal_p (XEXP (false_rtx, 1), true_rtx))
6666 term1 = true_rtx, false_rtx = XEXP (false_rtx, 0), true_rtx = const0_rtx;
6668 term2 = simplify_gen_binary (AND, GET_MODE (src),
6669 XEXP (XEXP (src, 0), 0), true_rtx);
6670 term3 = simplify_gen_binary (AND, GET_MODE (src),
6671 simplify_gen_unary (NOT, GET_MODE (src),
6672 XEXP (XEXP (src, 0), 0),
6677 simplify_gen_binary (IOR, GET_MODE (src),
6678 simplify_gen_binary (IOR, GET_MODE (src),
6685 /* If either SRC or DEST is a CLOBBER of (const_int 0), make this
6686 whole thing fail. */
6687 if (GET_CODE (src) == CLOBBER && XEXP (src, 0) == const0_rtx)
6689 else if (GET_CODE (dest) == CLOBBER && XEXP (dest, 0) == const0_rtx)
6692 /* Convert this into a field assignment operation, if possible. */
6693 return make_field_assignment (x);
6696 /* Simplify, X, and AND, IOR, or XOR operation, and return the simplified
6700 simplify_logical (rtx x)
6702 enum machine_mode mode = GET_MODE (x);
6703 rtx op0 = XEXP (x, 0);
6704 rtx op1 = XEXP (x, 1);
6706 switch (GET_CODE (x))
6709 /* We can call simplify_and_const_int only if we don't lose
6710 any (sign) bits when converting INTVAL (op1) to
6711 "unsigned HOST_WIDE_INT". */
6712 if (CONST_INT_P (op1)
6713 && (HWI_COMPUTABLE_MODE_P (mode)
6714 || INTVAL (op1) > 0))
6716 x = simplify_and_const_int (x, mode, op0, INTVAL (op1));
6717 if (GET_CODE (x) != AND)
6724 /* If we have any of (and (ior A B) C) or (and (xor A B) C),
6725 apply the distributive law and then the inverse distributive
6726 law to see if things simplify. */
6727 if (GET_CODE (op0) == IOR || GET_CODE (op0) == XOR)
6729 rtx result = distribute_and_simplify_rtx (x, 0);
6733 if (GET_CODE (op1) == IOR || GET_CODE (op1) == XOR)
6735 rtx result = distribute_and_simplify_rtx (x, 1);
6742 /* If we have (ior (and A B) C), apply the distributive law and then
6743 the inverse distributive law to see if things simplify. */
6745 if (GET_CODE (op0) == AND)
6747 rtx result = distribute_and_simplify_rtx (x, 0);
6752 if (GET_CODE (op1) == AND)
6754 rtx result = distribute_and_simplify_rtx (x, 1);
6767 /* We consider ZERO_EXTRACT, SIGN_EXTRACT, and SIGN_EXTEND as "compound
6768 operations" because they can be replaced with two more basic operations.
6769 ZERO_EXTEND is also considered "compound" because it can be replaced with
6770 an AND operation, which is simpler, though only one operation.
6772 The function expand_compound_operation is called with an rtx expression
6773 and will convert it to the appropriate shifts and AND operations,
6774 simplifying at each stage.
6776 The function make_compound_operation is called to convert an expression
6777 consisting of shifts and ANDs into the equivalent compound expression.
6778 It is the inverse of this function, loosely speaking. */
6781 expand_compound_operation (rtx x)
6783 unsigned HOST_WIDE_INT pos = 0, len;
6785 unsigned int modewidth;
6788 switch (GET_CODE (x))
6793 /* We can't necessarily use a const_int for a multiword mode;
6794 it depends on implicitly extending the value.
6795 Since we don't know the right way to extend it,
6796 we can't tell whether the implicit way is right.
6798 Even for a mode that is no wider than a const_int,
6799 we can't win, because we need to sign extend one of its bits through
6800 the rest of it, and we don't know which bit. */
6801 if (CONST_INT_P (XEXP (x, 0)))
6804 /* Return if (subreg:MODE FROM 0) is not a safe replacement for
6805 (zero_extend:MODE FROM) or (sign_extend:MODE FROM). It is for any MEM
6806 because (SUBREG (MEM...)) is guaranteed to cause the MEM to be
6807 reloaded. If not for that, MEM's would very rarely be safe.
6809 Reject MODEs bigger than a word, because we might not be able
6810 to reference a two-register group starting with an arbitrary register
6811 (and currently gen_lowpart might crash for a SUBREG). */
6813 if (GET_MODE_SIZE (GET_MODE (XEXP (x, 0))) > UNITS_PER_WORD)
6816 /* Reject MODEs that aren't scalar integers because turning vector
6817 or complex modes into shifts causes problems. */
6819 if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x, 0))))
6822 len = GET_MODE_PRECISION (GET_MODE (XEXP (x, 0)));
6823 /* If the inner object has VOIDmode (the only way this can happen
6824 is if it is an ASM_OPERANDS), we can't do anything since we don't
6825 know how much masking to do. */
6834 /* ... fall through ... */
6837 /* If the operand is a CLOBBER, just return it. */
6838 if (GET_CODE (XEXP (x, 0)) == CLOBBER)
6841 if (!CONST_INT_P (XEXP (x, 1))
6842 || !CONST_INT_P (XEXP (x, 2))
6843 || GET_MODE (XEXP (x, 0)) == VOIDmode)
6846 /* Reject MODEs that aren't scalar integers because turning vector
6847 or complex modes into shifts causes problems. */
6849 if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x, 0))))
6852 len = INTVAL (XEXP (x, 1));
6853 pos = INTVAL (XEXP (x, 2));
6855 /* This should stay within the object being extracted, fail otherwise. */
6856 if (len + pos > GET_MODE_PRECISION (GET_MODE (XEXP (x, 0))))
6859 if (BITS_BIG_ENDIAN)
6860 pos = GET_MODE_PRECISION (GET_MODE (XEXP (x, 0))) - len - pos;
6867 /* Convert sign extension to zero extension, if we know that the high
6868 bit is not set, as this is easier to optimize. It will be converted
6869 back to cheaper alternative in make_extraction. */
6870 if (GET_CODE (x) == SIGN_EXTEND
6871 && (HWI_COMPUTABLE_MODE_P (GET_MODE (x))
6872 && ((nonzero_bits (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
6873 & ~(((unsigned HOST_WIDE_INT)
6874 GET_MODE_MASK (GET_MODE (XEXP (x, 0))))
6878 rtx temp = gen_rtx_ZERO_EXTEND (GET_MODE (x), XEXP (x, 0));
6879 rtx temp2 = expand_compound_operation (temp);
6881 /* Make sure this is a profitable operation. */
6882 if (set_src_cost (x, optimize_this_for_speed_p)
6883 > set_src_cost (temp2, optimize_this_for_speed_p))
6885 else if (set_src_cost (x, optimize_this_for_speed_p)
6886 > set_src_cost (temp, optimize_this_for_speed_p))
6892 /* We can optimize some special cases of ZERO_EXTEND. */
6893 if (GET_CODE (x) == ZERO_EXTEND)
6895 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI if we
6896 know that the last value didn't have any inappropriate bits
6898 if (GET_CODE (XEXP (x, 0)) == TRUNCATE
6899 && GET_MODE (XEXP (XEXP (x, 0), 0)) == GET_MODE (x)
6900 && HWI_COMPUTABLE_MODE_P (GET_MODE (x))
6901 && (nonzero_bits (XEXP (XEXP (x, 0), 0), GET_MODE (x))
6902 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
6903 return XEXP (XEXP (x, 0), 0);
6905 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
6906 if (GET_CODE (XEXP (x, 0)) == SUBREG
6907 && GET_MODE (SUBREG_REG (XEXP (x, 0))) == GET_MODE (x)
6908 && subreg_lowpart_p (XEXP (x, 0))
6909 && HWI_COMPUTABLE_MODE_P (GET_MODE (x))
6910 && (nonzero_bits (SUBREG_REG (XEXP (x, 0)), GET_MODE (x))
6911 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
6912 return SUBREG_REG (XEXP (x, 0));
6914 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI when foo
6915 is a comparison and STORE_FLAG_VALUE permits. This is like
6916 the first case, but it works even when GET_MODE (x) is larger
6917 than HOST_WIDE_INT. */
6918 if (GET_CODE (XEXP (x, 0)) == TRUNCATE
6919 && GET_MODE (XEXP (XEXP (x, 0), 0)) == GET_MODE (x)
6920 && COMPARISON_P (XEXP (XEXP (x, 0), 0))
6921 && (GET_MODE_PRECISION (GET_MODE (XEXP (x, 0)))
6922 <= HOST_BITS_PER_WIDE_INT)
6923 && (STORE_FLAG_VALUE & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
6924 return XEXP (XEXP (x, 0), 0);
6926 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
6927 if (GET_CODE (XEXP (x, 0)) == SUBREG
6928 && GET_MODE (SUBREG_REG (XEXP (x, 0))) == GET_MODE (x)
6929 && subreg_lowpart_p (XEXP (x, 0))
6930 && COMPARISON_P (SUBREG_REG (XEXP (x, 0)))
6931 && (GET_MODE_PRECISION (GET_MODE (XEXP (x, 0)))
6932 <= HOST_BITS_PER_WIDE_INT)
6933 && (STORE_FLAG_VALUE & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
6934 return SUBREG_REG (XEXP (x, 0));
6938 /* If we reach here, we want to return a pair of shifts. The inner
6939 shift is a left shift of BITSIZE - POS - LEN bits. The outer
6940 shift is a right shift of BITSIZE - LEN bits. It is arithmetic or
6941 logical depending on the value of UNSIGNEDP.
6943 If this was a ZERO_EXTEND or ZERO_EXTRACT, this pair of shifts will be
6944 converted into an AND of a shift.
6946 We must check for the case where the left shift would have a negative
6947 count. This can happen in a case like (x >> 31) & 255 on machines
6948 that can't shift by a constant. On those machines, we would first
6949 combine the shift with the AND to produce a variable-position
6950 extraction. Then the constant of 31 would be substituted in
6951 to produce such a position. */
6953 modewidth = GET_MODE_PRECISION (GET_MODE (x));
6954 if (modewidth >= pos + len)
6956 enum machine_mode mode = GET_MODE (x);
6957 tem = gen_lowpart (mode, XEXP (x, 0));
6958 if (!tem || GET_CODE (tem) == CLOBBER)
6960 tem = simplify_shift_const (NULL_RTX, ASHIFT, mode,
6961 tem, modewidth - pos - len);
6962 tem = simplify_shift_const (NULL_RTX, unsignedp ? LSHIFTRT : ASHIFTRT,
6963 mode, tem, modewidth - len);
6965 else if (unsignedp && len < HOST_BITS_PER_WIDE_INT)
6966 tem = simplify_and_const_int (NULL_RTX, GET_MODE (x),
6967 simplify_shift_const (NULL_RTX, LSHIFTRT,
6970 ((unsigned HOST_WIDE_INT) 1 << len) - 1);
6972 /* Any other cases we can't handle. */
6975 /* If we couldn't do this for some reason, return the original
6977 if (GET_CODE (tem) == CLOBBER)
6983 /* X is a SET which contains an assignment of one object into
6984 a part of another (such as a bit-field assignment, STRICT_LOW_PART,
6985 or certain SUBREGS). If possible, convert it into a series of
6988 We half-heartedly support variable positions, but do not at all
6989 support variable lengths. */
6992 expand_field_assignment (const_rtx x)
6995 rtx pos; /* Always counts from low bit. */
6997 rtx mask, cleared, masked;
6998 enum machine_mode compute_mode;
7000 /* Loop until we find something we can't simplify. */
7003 if (GET_CODE (SET_DEST (x)) == STRICT_LOW_PART
7004 && GET_CODE (XEXP (SET_DEST (x), 0)) == SUBREG)
7006 inner = SUBREG_REG (XEXP (SET_DEST (x), 0));
7007 len = GET_MODE_PRECISION (GET_MODE (XEXP (SET_DEST (x), 0)));
7008 pos = GEN_INT (subreg_lsb (XEXP (SET_DEST (x), 0)));
7010 else if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
7011 && CONST_INT_P (XEXP (SET_DEST (x), 1)))
7013 inner = XEXP (SET_DEST (x), 0);
7014 len = INTVAL (XEXP (SET_DEST (x), 1));
7015 pos = XEXP (SET_DEST (x), 2);
7017 /* A constant position should stay within the width of INNER. */
7018 if (CONST_INT_P (pos)
7019 && INTVAL (pos) + len > GET_MODE_PRECISION (GET_MODE (inner)))
7022 if (BITS_BIG_ENDIAN)
7024 if (CONST_INT_P (pos))
7025 pos = GEN_INT (GET_MODE_PRECISION (GET_MODE (inner)) - len
7027 else if (GET_CODE (pos) == MINUS
7028 && CONST_INT_P (XEXP (pos, 1))
7029 && (INTVAL (XEXP (pos, 1))
7030 == GET_MODE_PRECISION (GET_MODE (inner)) - len))
7031 /* If position is ADJUST - X, new position is X. */
7032 pos = XEXP (pos, 0);
7034 pos = simplify_gen_binary (MINUS, GET_MODE (pos),
7035 GEN_INT (GET_MODE_PRECISION (
7042 /* A SUBREG between two modes that occupy the same numbers of words
7043 can be done by moving the SUBREG to the source. */
7044 else if (GET_CODE (SET_DEST (x)) == SUBREG
7045 /* We need SUBREGs to compute nonzero_bits properly. */
7046 && nonzero_sign_valid
7047 && (((GET_MODE_SIZE (GET_MODE (SET_DEST (x)))
7048 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
7049 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x))))
7050 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)))
7052 x = gen_rtx_SET (VOIDmode, SUBREG_REG (SET_DEST (x)),
7054 (GET_MODE (SUBREG_REG (SET_DEST (x))),
7061 while (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
7062 inner = SUBREG_REG (inner);
7064 compute_mode = GET_MODE (inner);
7066 /* Don't attempt bitwise arithmetic on non scalar integer modes. */
7067 if (! SCALAR_INT_MODE_P (compute_mode))
7069 enum machine_mode imode;
7071 /* Don't do anything for vector or complex integral types. */
7072 if (! FLOAT_MODE_P (compute_mode))
7075 /* Try to find an integral mode to pun with. */
7076 imode = mode_for_size (GET_MODE_BITSIZE (compute_mode), MODE_INT, 0);
7077 if (imode == BLKmode)
7080 compute_mode = imode;
7081 inner = gen_lowpart (imode, inner);
7084 /* Compute a mask of LEN bits, if we can do this on the host machine. */
7085 if (len >= HOST_BITS_PER_WIDE_INT)
7088 /* Now compute the equivalent expression. Make a copy of INNER
7089 for the SET_DEST in case it is a MEM into which we will substitute;
7090 we don't want shared RTL in that case. */
7091 mask = GEN_INT (((unsigned HOST_WIDE_INT) 1 << len) - 1);
7092 cleared = simplify_gen_binary (AND, compute_mode,
7093 simplify_gen_unary (NOT, compute_mode,
7094 simplify_gen_binary (ASHIFT,
7099 masked = simplify_gen_binary (ASHIFT, compute_mode,
7100 simplify_gen_binary (
7102 gen_lowpart (compute_mode, SET_SRC (x)),
7106 x = gen_rtx_SET (VOIDmode, copy_rtx (inner),
7107 simplify_gen_binary (IOR, compute_mode,
7114 /* Return an RTX for a reference to LEN bits of INNER. If POS_RTX is nonzero,
7115 it is an RTX that represents a variable starting position; otherwise,
7116 POS is the (constant) starting bit position (counted from the LSB).
7118 UNSIGNEDP is nonzero for an unsigned reference and zero for a
7121 IN_DEST is nonzero if this is a reference in the destination of a
7122 SET. This is used when a ZERO_ or SIGN_EXTRACT isn't needed. If nonzero,
7123 a STRICT_LOW_PART will be used, if zero, ZERO_EXTEND or SIGN_EXTEND will
7126 IN_COMPARE is nonzero if we are in a COMPARE. This means that a
7127 ZERO_EXTRACT should be built even for bits starting at bit 0.
7129 MODE is the desired mode of the result (if IN_DEST == 0).
7131 The result is an RTX for the extraction or NULL_RTX if the target
7135 make_extraction (enum machine_mode mode, rtx inner, HOST_WIDE_INT pos,
7136 rtx pos_rtx, unsigned HOST_WIDE_INT len, int unsignedp,
7137 int in_dest, int in_compare)
7139 /* This mode describes the size of the storage area
7140 to fetch the overall value from. Within that, we
7141 ignore the POS lowest bits, etc. */
7142 enum machine_mode is_mode = GET_MODE (inner);
7143 enum machine_mode inner_mode;
7144 enum machine_mode wanted_inner_mode;
7145 enum machine_mode wanted_inner_reg_mode = word_mode;
7146 enum machine_mode pos_mode = word_mode;
7147 enum machine_mode extraction_mode = word_mode;
7148 enum machine_mode tmode = mode_for_size (len, MODE_INT, 1);
7150 rtx orig_pos_rtx = pos_rtx;
7151 HOST_WIDE_INT orig_pos;
7153 if (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
7155 /* If going from (subreg:SI (mem:QI ...)) to (mem:QI ...),
7156 consider just the QI as the memory to extract from.
7157 The subreg adds or removes high bits; its mode is
7158 irrelevant to the meaning of this extraction,
7159 since POS and LEN count from the lsb. */
7160 if (MEM_P (SUBREG_REG (inner)))
7161 is_mode = GET_MODE (SUBREG_REG (inner));
7162 inner = SUBREG_REG (inner);
7164 else if (GET_CODE (inner) == ASHIFT
7165 && CONST_INT_P (XEXP (inner, 1))
7166 && pos_rtx == 0 && pos == 0
7167 && len > UINTVAL (XEXP (inner, 1)))
7169 /* We're extracting the least significant bits of an rtx
7170 (ashift X (const_int C)), where LEN > C. Extract the
7171 least significant (LEN - C) bits of X, giving an rtx
7172 whose mode is MODE, then shift it left C times. */
7173 new_rtx = make_extraction (mode, XEXP (inner, 0),
7174 0, 0, len - INTVAL (XEXP (inner, 1)),
7175 unsignedp, in_dest, in_compare);
7177 return gen_rtx_ASHIFT (mode, new_rtx, XEXP (inner, 1));
7180 inner_mode = GET_MODE (inner);
7182 if (pos_rtx && CONST_INT_P (pos_rtx))
7183 pos = INTVAL (pos_rtx), pos_rtx = 0;
7185 /* See if this can be done without an extraction. We never can if the
7186 width of the field is not the same as that of some integer mode. For
7187 registers, we can only avoid the extraction if the position is at the
7188 low-order bit and this is either not in the destination or we have the
7189 appropriate STRICT_LOW_PART operation available.
7191 For MEM, we can avoid an extract if the field starts on an appropriate
7192 boundary and we can change the mode of the memory reference. */
7194 if (tmode != BLKmode
7195 && ((pos_rtx == 0 && (pos % BITS_PER_WORD) == 0
7197 && (inner_mode == tmode
7199 || TRULY_NOOP_TRUNCATION_MODES_P (tmode, inner_mode)
7200 || reg_truncated_to_mode (tmode, inner))
7203 && have_insn_for (STRICT_LOW_PART, tmode))))
7204 || (MEM_P (inner) && pos_rtx == 0
7206 % (STRICT_ALIGNMENT ? GET_MODE_ALIGNMENT (tmode)
7207 : BITS_PER_UNIT)) == 0
7208 /* We can't do this if we are widening INNER_MODE (it
7209 may not be aligned, for one thing). */
7210 && GET_MODE_PRECISION (inner_mode) >= GET_MODE_PRECISION (tmode)
7211 && (inner_mode == tmode
7212 || (! mode_dependent_address_p (XEXP (inner, 0))
7213 && ! MEM_VOLATILE_P (inner))))))
7215 /* If INNER is a MEM, make a new MEM that encompasses just the desired
7216 field. If the original and current mode are the same, we need not
7217 adjust the offset. Otherwise, we do if bytes big endian.
7219 If INNER is not a MEM, get a piece consisting of just the field
7220 of interest (in this case POS % BITS_PER_WORD must be 0). */
7224 HOST_WIDE_INT offset;
7226 /* POS counts from lsb, but make OFFSET count in memory order. */
7227 if (BYTES_BIG_ENDIAN)
7228 offset = (GET_MODE_PRECISION (is_mode) - len - pos) / BITS_PER_UNIT;
7230 offset = pos / BITS_PER_UNIT;
7232 new_rtx = adjust_address_nv (inner, tmode, offset);
7234 else if (REG_P (inner))
7236 if (tmode != inner_mode)
7238 /* We can't call gen_lowpart in a DEST since we
7239 always want a SUBREG (see below) and it would sometimes
7240 return a new hard register. */
7243 HOST_WIDE_INT final_word = pos / BITS_PER_WORD;
7245 if (WORDS_BIG_ENDIAN
7246 && GET_MODE_SIZE (inner_mode) > UNITS_PER_WORD)
7247 final_word = ((GET_MODE_SIZE (inner_mode)
7248 - GET_MODE_SIZE (tmode))
7249 / UNITS_PER_WORD) - final_word;
7251 final_word *= UNITS_PER_WORD;
7252 if (BYTES_BIG_ENDIAN &&
7253 GET_MODE_SIZE (inner_mode) > GET_MODE_SIZE (tmode))
7254 final_word += (GET_MODE_SIZE (inner_mode)
7255 - GET_MODE_SIZE (tmode)) % UNITS_PER_WORD;
7257 /* Avoid creating invalid subregs, for example when
7258 simplifying (x>>32)&255. */
7259 if (!validate_subreg (tmode, inner_mode, inner, final_word))
7262 new_rtx = gen_rtx_SUBREG (tmode, inner, final_word);
7265 new_rtx = gen_lowpart (tmode, inner);
7271 new_rtx = force_to_mode (inner, tmode,
7272 len >= HOST_BITS_PER_WIDE_INT
7273 ? ~(unsigned HOST_WIDE_INT) 0
7274 : ((unsigned HOST_WIDE_INT) 1 << len) - 1,
7277 /* If this extraction is going into the destination of a SET,
7278 make a STRICT_LOW_PART unless we made a MEM. */
7281 return (MEM_P (new_rtx) ? new_rtx
7282 : (GET_CODE (new_rtx) != SUBREG
7283 ? gen_rtx_CLOBBER (tmode, const0_rtx)
7284 : gen_rtx_STRICT_LOW_PART (VOIDmode, new_rtx)));
7289 if (CONST_INT_P (new_rtx)
7290 || GET_CODE (new_rtx) == CONST_DOUBLE)
7291 return simplify_unary_operation (unsignedp ? ZERO_EXTEND : SIGN_EXTEND,
7292 mode, new_rtx, tmode);
7294 /* If we know that no extraneous bits are set, and that the high
7295 bit is not set, convert the extraction to the cheaper of
7296 sign and zero extension, that are equivalent in these cases. */
7297 if (flag_expensive_optimizations
7298 && (HWI_COMPUTABLE_MODE_P (tmode)
7299 && ((nonzero_bits (new_rtx, tmode)
7300 & ~(((unsigned HOST_WIDE_INT)GET_MODE_MASK (tmode)) >> 1))
7303 rtx temp = gen_rtx_ZERO_EXTEND (mode, new_rtx);
7304 rtx temp1 = gen_rtx_SIGN_EXTEND (mode, new_rtx);
7306 /* Prefer ZERO_EXTENSION, since it gives more information to
7308 if (set_src_cost (temp, optimize_this_for_speed_p)
7309 <= set_src_cost (temp1, optimize_this_for_speed_p))
7314 /* Otherwise, sign- or zero-extend unless we already are in the
7317 return (gen_rtx_fmt_e (unsignedp ? ZERO_EXTEND : SIGN_EXTEND,
7321 /* Unless this is a COMPARE or we have a funny memory reference,
7322 don't do anything with zero-extending field extracts starting at
7323 the low-order bit since they are simple AND operations. */
7324 if (pos_rtx == 0 && pos == 0 && ! in_dest
7325 && ! in_compare && unsignedp)
7328 /* Unless INNER is not MEM, reject this if we would be spanning bytes or
7329 if the position is not a constant and the length is not 1. In all
7330 other cases, we would only be going outside our object in cases when
7331 an original shift would have been undefined. */
7333 && ((pos_rtx == 0 && pos + len > GET_MODE_PRECISION (is_mode))
7334 || (pos_rtx != 0 && len != 1)))
7337 /* Get the mode to use should INNER not be a MEM, the mode for the position,
7338 and the mode for the result. */
7339 if (in_dest && mode_for_extraction (EP_insv, -1) != MAX_MACHINE_MODE)
7341 wanted_inner_reg_mode = mode_for_extraction (EP_insv, 0);
7342 pos_mode = mode_for_extraction (EP_insv, 2);
7343 extraction_mode = mode_for_extraction (EP_insv, 3);
7346 if (! in_dest && unsignedp
7347 && mode_for_extraction (EP_extzv, -1) != MAX_MACHINE_MODE)
7349 wanted_inner_reg_mode = mode_for_extraction (EP_extzv, 1);
7350 pos_mode = mode_for_extraction (EP_extzv, 3);
7351 extraction_mode = mode_for_extraction (EP_extzv, 0);
7354 if (! in_dest && ! unsignedp
7355 && mode_for_extraction (EP_extv, -1) != MAX_MACHINE_MODE)
7357 wanted_inner_reg_mode = mode_for_extraction (EP_extv, 1);
7358 pos_mode = mode_for_extraction (EP_extv, 3);
7359 extraction_mode = mode_for_extraction (EP_extv, 0);
7362 /* Never narrow an object, since that might not be safe. */
7364 if (mode != VOIDmode
7365 && GET_MODE_SIZE (extraction_mode) < GET_MODE_SIZE (mode))
7366 extraction_mode = mode;
7368 if (pos_rtx && GET_MODE (pos_rtx) != VOIDmode
7369 && GET_MODE_SIZE (pos_mode) < GET_MODE_SIZE (GET_MODE (pos_rtx)))
7370 pos_mode = GET_MODE (pos_rtx);
7372 /* If this is not from memory, the desired mode is the preferred mode
7373 for an extraction pattern's first input operand, or word_mode if there
7376 wanted_inner_mode = wanted_inner_reg_mode;
7379 /* Be careful not to go beyond the extracted object and maintain the
7380 natural alignment of the memory. */
7381 wanted_inner_mode = smallest_mode_for_size (len, MODE_INT);
7382 while (pos % GET_MODE_BITSIZE (wanted_inner_mode) + len
7383 > GET_MODE_BITSIZE (wanted_inner_mode))
7385 wanted_inner_mode = GET_MODE_WIDER_MODE (wanted_inner_mode);
7386 gcc_assert (wanted_inner_mode != VOIDmode);
7389 /* If we have to change the mode of memory and cannot, the desired mode
7390 is EXTRACTION_MODE. */
7391 if (inner_mode != wanted_inner_mode
7392 && (mode_dependent_address_p (XEXP (inner, 0))
7393 || MEM_VOLATILE_P (inner)
7395 wanted_inner_mode = extraction_mode;
7400 if (BITS_BIG_ENDIAN)
7402 /* POS is passed as if BITS_BIG_ENDIAN == 0, so we need to convert it to
7403 BITS_BIG_ENDIAN style. If position is constant, compute new
7404 position. Otherwise, build subtraction.
7405 Note that POS is relative to the mode of the original argument.
7406 If it's a MEM we need to recompute POS relative to that.
7407 However, if we're extracting from (or inserting into) a register,
7408 we want to recompute POS relative to wanted_inner_mode. */
7409 int width = (MEM_P (inner)
7410 ? GET_MODE_BITSIZE (is_mode)
7411 : GET_MODE_BITSIZE (wanted_inner_mode));
7414 pos = width - len - pos;
7417 = gen_rtx_MINUS (GET_MODE (pos_rtx), GEN_INT (width - len), pos_rtx);
7418 /* POS may be less than 0 now, but we check for that below.
7419 Note that it can only be less than 0 if !MEM_P (inner). */
7422 /* If INNER has a wider mode, and this is a constant extraction, try to
7423 make it smaller and adjust the byte to point to the byte containing
7425 if (wanted_inner_mode != VOIDmode
7426 && inner_mode != wanted_inner_mode
7428 && GET_MODE_SIZE (wanted_inner_mode) < GET_MODE_SIZE (is_mode)
7430 && ! mode_dependent_address_p (XEXP (inner, 0))
7431 && ! MEM_VOLATILE_P (inner))
7435 /* The computations below will be correct if the machine is big
7436 endian in both bits and bytes or little endian in bits and bytes.
7437 If it is mixed, we must adjust. */
7439 /* If bytes are big endian and we had a paradoxical SUBREG, we must
7440 adjust OFFSET to compensate. */
7441 if (BYTES_BIG_ENDIAN
7442 && GET_MODE_SIZE (inner_mode) < GET_MODE_SIZE (is_mode))
7443 offset -= GET_MODE_SIZE (is_mode) - GET_MODE_SIZE (inner_mode);
7445 /* We can now move to the desired byte. */
7446 offset += (pos / GET_MODE_BITSIZE (wanted_inner_mode))
7447 * GET_MODE_SIZE (wanted_inner_mode);
7448 pos %= GET_MODE_BITSIZE (wanted_inner_mode);
7450 if (BYTES_BIG_ENDIAN != BITS_BIG_ENDIAN
7451 && is_mode != wanted_inner_mode)
7452 offset = (GET_MODE_SIZE (is_mode)
7453 - GET_MODE_SIZE (wanted_inner_mode) - offset);
7455 inner = adjust_address_nv (inner, wanted_inner_mode, offset);
7458 /* If INNER is not memory, get it into the proper mode. If we are changing
7459 its mode, POS must be a constant and smaller than the size of the new
7461 else if (!MEM_P (inner))
7463 /* On the LHS, don't create paradoxical subregs implicitely truncating
7464 the register unless TRULY_NOOP_TRUNCATION. */
7466 && !TRULY_NOOP_TRUNCATION_MODES_P (GET_MODE (inner),
7470 if (GET_MODE (inner) != wanted_inner_mode
7472 || orig_pos + len > GET_MODE_BITSIZE (wanted_inner_mode)))
7478 inner = force_to_mode (inner, wanted_inner_mode,
7480 || len + orig_pos >= HOST_BITS_PER_WIDE_INT
7481 ? ~(unsigned HOST_WIDE_INT) 0
7482 : ((((unsigned HOST_WIDE_INT) 1 << len) - 1)
7487 /* Adjust mode of POS_RTX, if needed. If we want a wider mode, we
7488 have to zero extend. Otherwise, we can just use a SUBREG. */
7490 && GET_MODE_SIZE (pos_mode) > GET_MODE_SIZE (GET_MODE (pos_rtx)))
7492 rtx temp = gen_rtx_ZERO_EXTEND (pos_mode, pos_rtx);
7494 /* If we know that no extraneous bits are set, and that the high
7495 bit is not set, convert extraction to cheaper one - either
7496 SIGN_EXTENSION or ZERO_EXTENSION, that are equivalent in these
7498 if (flag_expensive_optimizations
7499 && (HWI_COMPUTABLE_MODE_P (GET_MODE (pos_rtx))
7500 && ((nonzero_bits (pos_rtx, GET_MODE (pos_rtx))
7501 & ~(((unsigned HOST_WIDE_INT)
7502 GET_MODE_MASK (GET_MODE (pos_rtx)))
7506 rtx temp1 = gen_rtx_SIGN_EXTEND (pos_mode, pos_rtx);
7508 /* Prefer ZERO_EXTENSION, since it gives more information to
7510 if (set_src_cost (temp1, optimize_this_for_speed_p)
7511 < set_src_cost (temp, optimize_this_for_speed_p))
7516 else if (pos_rtx != 0
7517 && GET_MODE_SIZE (pos_mode) < GET_MODE_SIZE (GET_MODE (pos_rtx)))
7518 pos_rtx = gen_lowpart (pos_mode, pos_rtx);
7520 /* Make POS_RTX unless we already have it and it is correct. If we don't
7521 have a POS_RTX but we do have an ORIG_POS_RTX, the latter must
7523 if (pos_rtx == 0 && orig_pos_rtx != 0 && INTVAL (orig_pos_rtx) == pos)
7524 pos_rtx = orig_pos_rtx;
7526 else if (pos_rtx == 0)
7527 pos_rtx = GEN_INT (pos);
7529 /* Make the required operation. See if we can use existing rtx. */
7530 new_rtx = gen_rtx_fmt_eee (unsignedp ? ZERO_EXTRACT : SIGN_EXTRACT,
7531 extraction_mode, inner, GEN_INT (len), pos_rtx);
7533 new_rtx = gen_lowpart (mode, new_rtx);
7538 /* See if X contains an ASHIFT of COUNT or more bits that can be commuted
7539 with any other operations in X. Return X without that shift if so. */
7542 extract_left_shift (rtx x, int count)
7544 enum rtx_code code = GET_CODE (x);
7545 enum machine_mode mode = GET_MODE (x);
7551 /* This is the shift itself. If it is wide enough, we will return
7552 either the value being shifted if the shift count is equal to
7553 COUNT or a shift for the difference. */
7554 if (CONST_INT_P (XEXP (x, 1))
7555 && INTVAL (XEXP (x, 1)) >= count)
7556 return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (x, 0),
7557 INTVAL (XEXP (x, 1)) - count);
7561 if ((tem = extract_left_shift (XEXP (x, 0), count)) != 0)
7562 return simplify_gen_unary (code, mode, tem, mode);
7566 case PLUS: case IOR: case XOR: case AND:
7567 /* If we can safely shift this constant and we find the inner shift,
7568 make a new operation. */
7569 if (CONST_INT_P (XEXP (x, 1))
7570 && (UINTVAL (XEXP (x, 1))
7571 & ((((unsigned HOST_WIDE_INT) 1 << count)) - 1)) == 0
7572 && (tem = extract_left_shift (XEXP (x, 0), count)) != 0)
7573 return simplify_gen_binary (code, mode, tem,
7574 GEN_INT (INTVAL (XEXP (x, 1)) >> count));
7585 /* Look at the expression rooted at X. Look for expressions
7586 equivalent to ZERO_EXTRACT, SIGN_EXTRACT, ZERO_EXTEND, SIGN_EXTEND.
7587 Form these expressions.
7589 Return the new rtx, usually just X.
7591 Also, for machines like the VAX that don't have logical shift insns,
7592 try to convert logical to arithmetic shift operations in cases where
7593 they are equivalent. This undoes the canonicalizations to logical
7594 shifts done elsewhere.
7596 We try, as much as possible, to re-use rtl expressions to save memory.
7598 IN_CODE says what kind of expression we are processing. Normally, it is
7599 SET. In a memory address (inside a MEM, PLUS or minus, the latter two
7600 being kludges), it is MEM. When processing the arguments of a comparison
7601 or a COMPARE against zero, it is COMPARE. */
7604 make_compound_operation (rtx x, enum rtx_code in_code)
7606 enum rtx_code code = GET_CODE (x);
7607 enum machine_mode mode = GET_MODE (x);
7608 int mode_width = GET_MODE_PRECISION (mode);
7610 enum rtx_code next_code;
7616 /* Select the code to be used in recursive calls. Once we are inside an
7617 address, we stay there. If we have a comparison, set to COMPARE,
7618 but once inside, go back to our default of SET. */
7620 next_code = (code == MEM ? MEM
7621 : ((code == PLUS || code == MINUS)
7622 && SCALAR_INT_MODE_P (mode)) ? MEM
7623 : ((code == COMPARE || COMPARISON_P (x))
7624 && XEXP (x, 1) == const0_rtx) ? COMPARE
7625 : in_code == COMPARE ? SET : in_code);
7627 /* Process depending on the code of this operation. If NEW is set
7628 nonzero, it will be returned. */
7633 /* Convert shifts by constants into multiplications if inside
7635 if (in_code == MEM && CONST_INT_P (XEXP (x, 1))
7636 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT
7637 && INTVAL (XEXP (x, 1)) >= 0
7638 && SCALAR_INT_MODE_P (mode))
7640 HOST_WIDE_INT count = INTVAL (XEXP (x, 1));
7641 HOST_WIDE_INT multval = (HOST_WIDE_INT) 1 << count;
7643 new_rtx = make_compound_operation (XEXP (x, 0), next_code);
7644 if (GET_CODE (new_rtx) == NEG)
7646 new_rtx = XEXP (new_rtx, 0);
7649 multval = trunc_int_for_mode (multval, mode);
7650 new_rtx = gen_rtx_MULT (mode, new_rtx, GEN_INT (multval));
7657 lhs = make_compound_operation (lhs, next_code);
7658 rhs = make_compound_operation (rhs, next_code);
7659 if (GET_CODE (lhs) == MULT && GET_CODE (XEXP (lhs, 0)) == NEG
7660 && SCALAR_INT_MODE_P (mode))
7662 tem = simplify_gen_binary (MULT, mode, XEXP (XEXP (lhs, 0), 0),
7664 new_rtx = simplify_gen_binary (MINUS, mode, rhs, tem);
7666 else if (GET_CODE (lhs) == MULT
7667 && (CONST_INT_P (XEXP (lhs, 1)) && INTVAL (XEXP (lhs, 1)) < 0))
7669 tem = simplify_gen_binary (MULT, mode, XEXP (lhs, 0),
7670 simplify_gen_unary (NEG, mode,
7673 new_rtx = simplify_gen_binary (MINUS, mode, rhs, tem);
7677 SUBST (XEXP (x, 0), lhs);
7678 SUBST (XEXP (x, 1), rhs);
7681 x = gen_lowpart (mode, new_rtx);
7687 lhs = make_compound_operation (lhs, next_code);
7688 rhs = make_compound_operation (rhs, next_code);
7689 if (GET_CODE (rhs) == MULT && GET_CODE (XEXP (rhs, 0)) == NEG
7690 && SCALAR_INT_MODE_P (mode))
7692 tem = simplify_gen_binary (MULT, mode, XEXP (XEXP (rhs, 0), 0),
7694 new_rtx = simplify_gen_binary (PLUS, mode, tem, lhs);
7696 else if (GET_CODE (rhs) == MULT
7697 && (CONST_INT_P (XEXP (rhs, 1)) && INTVAL (XEXP (rhs, 1)) < 0))
7699 tem = simplify_gen_binary (MULT, mode, XEXP (rhs, 0),
7700 simplify_gen_unary (NEG, mode,
7703 new_rtx = simplify_gen_binary (PLUS, mode, tem, lhs);
7707 SUBST (XEXP (x, 0), lhs);
7708 SUBST (XEXP (x, 1), rhs);
7711 return gen_lowpart (mode, new_rtx);
7714 /* If the second operand is not a constant, we can't do anything
7716 if (!CONST_INT_P (XEXP (x, 1)))
7719 /* If the constant is a power of two minus one and the first operand
7720 is a logical right shift, make an extraction. */
7721 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
7722 && (i = exact_log2 (UINTVAL (XEXP (x, 1)) + 1)) >= 0)
7724 new_rtx = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code);
7725 new_rtx = make_extraction (mode, new_rtx, 0, XEXP (XEXP (x, 0), 1), i, 1,
7726 0, in_code == COMPARE);
7729 /* Same as previous, but for (subreg (lshiftrt ...)) in first op. */
7730 else if (GET_CODE (XEXP (x, 0)) == SUBREG
7731 && subreg_lowpart_p (XEXP (x, 0))
7732 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == LSHIFTRT
7733 && (i = exact_log2 (UINTVAL (XEXP (x, 1)) + 1)) >= 0)
7735 new_rtx = make_compound_operation (XEXP (SUBREG_REG (XEXP (x, 0)), 0),
7737 new_rtx = make_extraction (GET_MODE (SUBREG_REG (XEXP (x, 0))), new_rtx, 0,
7738 XEXP (SUBREG_REG (XEXP (x, 0)), 1), i, 1,
7739 0, in_code == COMPARE);
7741 /* Same as previous, but for (xor/ior (lshiftrt...) (lshiftrt...)). */
7742 else if ((GET_CODE (XEXP (x, 0)) == XOR
7743 || GET_CODE (XEXP (x, 0)) == IOR)
7744 && GET_CODE (XEXP (XEXP (x, 0), 0)) == LSHIFTRT
7745 && GET_CODE (XEXP (XEXP (x, 0), 1)) == LSHIFTRT
7746 && (i = exact_log2 (UINTVAL (XEXP (x, 1)) + 1)) >= 0)
7748 /* Apply the distributive law, and then try to make extractions. */
7749 new_rtx = gen_rtx_fmt_ee (GET_CODE (XEXP (x, 0)), mode,
7750 gen_rtx_AND (mode, XEXP (XEXP (x, 0), 0),
7752 gen_rtx_AND (mode, XEXP (XEXP (x, 0), 1),
7754 new_rtx = make_compound_operation (new_rtx, in_code);
7757 /* If we are have (and (rotate X C) M) and C is larger than the number
7758 of bits in M, this is an extraction. */
7760 else if (GET_CODE (XEXP (x, 0)) == ROTATE
7761 && CONST_INT_P (XEXP (XEXP (x, 0), 1))
7762 && (i = exact_log2 (UINTVAL (XEXP (x, 1)) + 1)) >= 0
7763 && i <= INTVAL (XEXP (XEXP (x, 0), 1)))
7765 new_rtx = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code);
7766 new_rtx = make_extraction (mode, new_rtx,
7767 (GET_MODE_PRECISION (mode)
7768 - INTVAL (XEXP (XEXP (x, 0), 1))),
7769 NULL_RTX, i, 1, 0, in_code == COMPARE);
7772 /* On machines without logical shifts, if the operand of the AND is
7773 a logical shift and our mask turns off all the propagated sign
7774 bits, we can replace the logical shift with an arithmetic shift. */
7775 else if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
7776 && !have_insn_for (LSHIFTRT, mode)
7777 && have_insn_for (ASHIFTRT, mode)
7778 && CONST_INT_P (XEXP (XEXP (x, 0), 1))
7779 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
7780 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT
7781 && mode_width <= HOST_BITS_PER_WIDE_INT)
7783 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
7785 mask >>= INTVAL (XEXP (XEXP (x, 0), 1));
7786 if ((INTVAL (XEXP (x, 1)) & ~mask) == 0)
7788 gen_rtx_ASHIFTRT (mode,
7789 make_compound_operation
7790 (XEXP (XEXP (x, 0), 0), next_code),
7791 XEXP (XEXP (x, 0), 1)));
7794 /* If the constant is one less than a power of two, this might be
7795 representable by an extraction even if no shift is present.
7796 If it doesn't end up being a ZERO_EXTEND, we will ignore it unless
7797 we are in a COMPARE. */
7798 else if ((i = exact_log2 (UINTVAL (XEXP (x, 1)) + 1)) >= 0)
7799 new_rtx = make_extraction (mode,
7800 make_compound_operation (XEXP (x, 0),
7802 0, NULL_RTX, i, 1, 0, in_code == COMPARE);
7804 /* If we are in a comparison and this is an AND with a power of two,
7805 convert this into the appropriate bit extract. */
7806 else if (in_code == COMPARE
7807 && (i = exact_log2 (UINTVAL (XEXP (x, 1)))) >= 0)
7808 new_rtx = make_extraction (mode,
7809 make_compound_operation (XEXP (x, 0),
7811 i, NULL_RTX, 1, 1, 0, 1);
7816 /* If the sign bit is known to be zero, replace this with an
7817 arithmetic shift. */
7818 if (have_insn_for (ASHIFTRT, mode)
7819 && ! have_insn_for (LSHIFTRT, mode)
7820 && mode_width <= HOST_BITS_PER_WIDE_INT
7821 && (nonzero_bits (XEXP (x, 0), mode) & (1 << (mode_width - 1))) == 0)
7823 new_rtx = gen_rtx_ASHIFTRT (mode,
7824 make_compound_operation (XEXP (x, 0),
7830 /* ... fall through ... */
7836 /* If we have (ashiftrt (ashift foo C1) C2) with C2 >= C1,
7837 this is a SIGN_EXTRACT. */
7838 if (CONST_INT_P (rhs)
7839 && GET_CODE (lhs) == ASHIFT
7840 && CONST_INT_P (XEXP (lhs, 1))
7841 && INTVAL (rhs) >= INTVAL (XEXP (lhs, 1))
7842 && INTVAL (XEXP (lhs, 1)) >= 0
7843 && INTVAL (rhs) < mode_width)
7845 new_rtx = make_compound_operation (XEXP (lhs, 0), next_code);
7846 new_rtx = make_extraction (mode, new_rtx,
7847 INTVAL (rhs) - INTVAL (XEXP (lhs, 1)),
7848 NULL_RTX, mode_width - INTVAL (rhs),
7849 code == LSHIFTRT, 0, in_code == COMPARE);
7853 /* See if we have operations between an ASHIFTRT and an ASHIFT.
7854 If so, try to merge the shifts into a SIGN_EXTEND. We could
7855 also do this for some cases of SIGN_EXTRACT, but it doesn't
7856 seem worth the effort; the case checked for occurs on Alpha. */
7859 && ! (GET_CODE (lhs) == SUBREG
7860 && (OBJECT_P (SUBREG_REG (lhs))))
7861 && CONST_INT_P (rhs)
7862 && INTVAL (rhs) < HOST_BITS_PER_WIDE_INT
7863 && INTVAL (rhs) < mode_width
7864 && (new_rtx = extract_left_shift (lhs, INTVAL (rhs))) != 0)
7865 new_rtx = make_extraction (mode, make_compound_operation (new_rtx, next_code),
7866 0, NULL_RTX, mode_width - INTVAL (rhs),
7867 code == LSHIFTRT, 0, in_code == COMPARE);
7872 /* Call ourselves recursively on the inner expression. If we are
7873 narrowing the object and it has a different RTL code from
7874 what it originally did, do this SUBREG as a force_to_mode. */
7876 rtx inner = SUBREG_REG (x), simplified;
7878 tem = make_compound_operation (inner, in_code);
7881 = simplify_subreg (mode, tem, GET_MODE (inner), SUBREG_BYTE (x));
7885 if (GET_CODE (tem) != GET_CODE (inner)
7886 && GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (inner))
7887 && subreg_lowpart_p (x))
7890 = force_to_mode (tem, mode, ~(unsigned HOST_WIDE_INT) 0, 0);
7892 /* If we have something other than a SUBREG, we might have
7893 done an expansion, so rerun ourselves. */
7894 if (GET_CODE (newer) != SUBREG)
7895 newer = make_compound_operation (newer, in_code);
7897 /* force_to_mode can expand compounds. If it just re-expanded the
7898 compound, use gen_lowpart to convert to the desired mode. */
7899 if (rtx_equal_p (newer, x)
7900 /* Likewise if it re-expanded the compound only partially.
7901 This happens for SUBREG of ZERO_EXTRACT if they extract
7902 the same number of bits. */
7903 || (GET_CODE (newer) == SUBREG
7904 && (GET_CODE (SUBREG_REG (newer)) == LSHIFTRT
7905 || GET_CODE (SUBREG_REG (newer)) == ASHIFTRT)
7906 && GET_CODE (inner) == AND
7907 && rtx_equal_p (SUBREG_REG (newer), XEXP (inner, 0))))
7908 return gen_lowpart (GET_MODE (x), tem);
7924 x = gen_lowpart (mode, new_rtx);
7925 code = GET_CODE (x);
7928 /* Now recursively process each operand of this operation. We need to
7929 handle ZERO_EXTEND specially so that we don't lose track of the
7931 if (GET_CODE (x) == ZERO_EXTEND)
7933 new_rtx = make_compound_operation (XEXP (x, 0), next_code);
7934 tem = simplify_const_unary_operation (ZERO_EXTEND, GET_MODE (x),
7935 new_rtx, GET_MODE (XEXP (x, 0)));
7938 SUBST (XEXP (x, 0), new_rtx);
7942 fmt = GET_RTX_FORMAT (code);
7943 for (i = 0; i < GET_RTX_LENGTH (code); i++)
7946 new_rtx = make_compound_operation (XEXP (x, i), next_code);
7947 SUBST (XEXP (x, i), new_rtx);
7949 else if (fmt[i] == 'E')
7950 for (j = 0; j < XVECLEN (x, i); j++)
7952 new_rtx = make_compound_operation (XVECEXP (x, i, j), next_code);
7953 SUBST (XVECEXP (x, i, j), new_rtx);
7957 /* If this is a commutative operation, the changes to the operands
7958 may have made it noncanonical. */
7959 if (COMMUTATIVE_ARITH_P (x)
7960 && swap_commutative_operands_p (XEXP (x, 0), XEXP (x, 1)))
7963 SUBST (XEXP (x, 0), XEXP (x, 1));
7964 SUBST (XEXP (x, 1), tem);
7970 /* Given M see if it is a value that would select a field of bits
7971 within an item, but not the entire word. Return -1 if not.
7972 Otherwise, return the starting position of the field, where 0 is the
7975 *PLEN is set to the length of the field. */
7978 get_pos_from_mask (unsigned HOST_WIDE_INT m, unsigned HOST_WIDE_INT *plen)
7980 /* Get the bit number of the first 1 bit from the right, -1 if none. */
7981 int pos = m ? ctz_hwi (m) : -1;
7985 /* Now shift off the low-order zero bits and see if we have a
7986 power of two minus 1. */
7987 len = exact_log2 ((m >> pos) + 1);
7996 /* If X refers to a register that equals REG in value, replace these
7997 references with REG. */
7999 canon_reg_for_combine (rtx x, rtx reg)
8006 enum rtx_code code = GET_CODE (x);
8007 switch (GET_RTX_CLASS (code))
8010 op0 = canon_reg_for_combine (XEXP (x, 0), reg);
8011 if (op0 != XEXP (x, 0))
8012 return simplify_gen_unary (GET_CODE (x), GET_MODE (x), op0,
8017 case RTX_COMM_ARITH:
8018 op0 = canon_reg_for_combine (XEXP (x, 0), reg);
8019 op1 = canon_reg_for_combine (XEXP (x, 1), reg);
8020 if (op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
8021 return simplify_gen_binary (GET_CODE (x), GET_MODE (x), op0, op1);
8025 case RTX_COMM_COMPARE:
8026 op0 = canon_reg_for_combine (XEXP (x, 0), reg);
8027 op1 = canon_reg_for_combine (XEXP (x, 1), reg);
8028 if (op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
8029 return simplify_gen_relational (GET_CODE (x), GET_MODE (x),
8030 GET_MODE (op0), op0, op1);
8034 case RTX_BITFIELD_OPS:
8035 op0 = canon_reg_for_combine (XEXP (x, 0), reg);
8036 op1 = canon_reg_for_combine (XEXP (x, 1), reg);
8037 op2 = canon_reg_for_combine (XEXP (x, 2), reg);
8038 if (op0 != XEXP (x, 0) || op1 != XEXP (x, 1) || op2 != XEXP (x, 2))
8039 return simplify_gen_ternary (GET_CODE (x), GET_MODE (x),
8040 GET_MODE (op0), op0, op1, op2);
8045 if (rtx_equal_p (get_last_value (reg), x)
8046 || rtx_equal_p (reg, get_last_value (x)))
8055 fmt = GET_RTX_FORMAT (code);
8057 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
8060 rtx op = canon_reg_for_combine (XEXP (x, i), reg);
8061 if (op != XEXP (x, i))
8071 else if (fmt[i] == 'E')
8074 for (j = 0; j < XVECLEN (x, i); j++)
8076 rtx op = canon_reg_for_combine (XVECEXP (x, i, j), reg);
8077 if (op != XVECEXP (x, i, j))
8084 XVECEXP (x, i, j) = op;
8095 /* Return X converted to MODE. If the value is already truncated to
8096 MODE we can just return a subreg even though in the general case we
8097 would need an explicit truncation. */
8100 gen_lowpart_or_truncate (enum machine_mode mode, rtx x)
8102 if (!CONST_INT_P (x)
8103 && GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (x))
8104 && !TRULY_NOOP_TRUNCATION_MODES_P (mode, GET_MODE (x))
8105 && !(REG_P (x) && reg_truncated_to_mode (mode, x)))
8107 /* Bit-cast X into an integer mode. */
8108 if (!SCALAR_INT_MODE_P (GET_MODE (x)))
8109 x = gen_lowpart (int_mode_for_mode (GET_MODE (x)), x);
8110 x = simplify_gen_unary (TRUNCATE, int_mode_for_mode (mode),
8114 return gen_lowpart (mode, x);
8117 /* See if X can be simplified knowing that we will only refer to it in
8118 MODE and will only refer to those bits that are nonzero in MASK.
8119 If other bits are being computed or if masking operations are done
8120 that select a superset of the bits in MASK, they can sometimes be
8123 Return a possibly simplified expression, but always convert X to
8124 MODE. If X is a CONST_INT, AND the CONST_INT with MASK.
8126 If JUST_SELECT is nonzero, don't optimize by noticing that bits in MASK
8127 are all off in X. This is used when X will be complemented, by either
8128 NOT, NEG, or XOR. */
8131 force_to_mode (rtx x, enum machine_mode mode, unsigned HOST_WIDE_INT mask,
8134 enum rtx_code code = GET_CODE (x);
8135 int next_select = just_select || code == XOR || code == NOT || code == NEG;
8136 enum machine_mode op_mode;
8137 unsigned HOST_WIDE_INT fuller_mask, nonzero;
8140 /* If this is a CALL or ASM_OPERANDS, don't do anything. Some of the
8141 code below will do the wrong thing since the mode of such an
8142 expression is VOIDmode.
8144 Also do nothing if X is a CLOBBER; this can happen if X was
8145 the return value from a call to gen_lowpart. */
8146 if (code == CALL || code == ASM_OPERANDS || code == CLOBBER)
8149 /* We want to perform the operation is its present mode unless we know
8150 that the operation is valid in MODE, in which case we do the operation
8152 op_mode = ((GET_MODE_CLASS (mode) == GET_MODE_CLASS (GET_MODE (x))
8153 && have_insn_for (code, mode))
8154 ? mode : GET_MODE (x));
8156 /* It is not valid to do a right-shift in a narrower mode
8157 than the one it came in with. */
8158 if ((code == LSHIFTRT || code == ASHIFTRT)
8159 && GET_MODE_PRECISION (mode) < GET_MODE_PRECISION (GET_MODE (x)))
8160 op_mode = GET_MODE (x);
8162 /* Truncate MASK to fit OP_MODE. */
8164 mask &= GET_MODE_MASK (op_mode);
8166 /* When we have an arithmetic operation, or a shift whose count we
8167 do not know, we need to assume that all bits up to the highest-order
8168 bit in MASK will be needed. This is how we form such a mask. */
8169 if (mask & ((unsigned HOST_WIDE_INT) 1 << (HOST_BITS_PER_WIDE_INT - 1)))
8170 fuller_mask = ~(unsigned HOST_WIDE_INT) 0;
8172 fuller_mask = (((unsigned HOST_WIDE_INT) 1 << (floor_log2 (mask) + 1))
8175 /* Determine what bits of X are guaranteed to be (non)zero. */
8176 nonzero = nonzero_bits (x, mode);
8178 /* If none of the bits in X are needed, return a zero. */
8179 if (!just_select && (nonzero & mask) == 0 && !side_effects_p (x))
8182 /* If X is a CONST_INT, return a new one. Do this here since the
8183 test below will fail. */
8184 if (CONST_INT_P (x))
8186 if (SCALAR_INT_MODE_P (mode))
8187 return gen_int_mode (INTVAL (x) & mask, mode);
8190 x = GEN_INT (INTVAL (x) & mask);
8191 return gen_lowpart_common (mode, x);
8195 /* If X is narrower than MODE and we want all the bits in X's mode, just
8196 get X in the proper mode. */
8197 if (GET_MODE_SIZE (GET_MODE (x)) < GET_MODE_SIZE (mode)
8198 && (GET_MODE_MASK (GET_MODE (x)) & ~mask) == 0)
8199 return gen_lowpart (mode, x);
8201 /* We can ignore the effect of a SUBREG if it narrows the mode or
8202 if the constant masks to zero all the bits the mode doesn't have. */
8203 if (GET_CODE (x) == SUBREG
8204 && subreg_lowpart_p (x)
8205 && ((GET_MODE_SIZE (GET_MODE (x))
8206 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
8208 & GET_MODE_MASK (GET_MODE (x))
8209 & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (x)))))))
8210 return force_to_mode (SUBREG_REG (x), mode, mask, next_select);
8212 /* The arithmetic simplifications here only work for scalar integer modes. */
8213 if (!SCALAR_INT_MODE_P (mode) || !SCALAR_INT_MODE_P (GET_MODE (x)))
8214 return gen_lowpart_or_truncate (mode, x);
8219 /* If X is a (clobber (const_int)), return it since we know we are
8220 generating something that won't match. */
8227 x = expand_compound_operation (x);
8228 if (GET_CODE (x) != code)
8229 return force_to_mode (x, mode, mask, next_select);
8233 /* Similarly for a truncate. */
8234 return force_to_mode (XEXP (x, 0), mode, mask, next_select);
8237 /* If this is an AND with a constant, convert it into an AND
8238 whose constant is the AND of that constant with MASK. If it
8239 remains an AND of MASK, delete it since it is redundant. */
8241 if (CONST_INT_P (XEXP (x, 1)))
8243 x = simplify_and_const_int (x, op_mode, XEXP (x, 0),
8244 mask & INTVAL (XEXP (x, 1)));
8246 /* If X is still an AND, see if it is an AND with a mask that
8247 is just some low-order bits. If so, and it is MASK, we don't
8250 if (GET_CODE (x) == AND && CONST_INT_P (XEXP (x, 1))
8251 && ((INTVAL (XEXP (x, 1)) & GET_MODE_MASK (GET_MODE (x)))
8255 /* If it remains an AND, try making another AND with the bits
8256 in the mode mask that aren't in MASK turned on. If the
8257 constant in the AND is wide enough, this might make a
8258 cheaper constant. */
8260 if (GET_CODE (x) == AND && CONST_INT_P (XEXP (x, 1))
8261 && GET_MODE_MASK (GET_MODE (x)) != mask
8262 && HWI_COMPUTABLE_MODE_P (GET_MODE (x)))
8264 unsigned HOST_WIDE_INT cval
8265 = UINTVAL (XEXP (x, 1))
8266 | (GET_MODE_MASK (GET_MODE (x)) & ~mask);
8267 int width = GET_MODE_PRECISION (GET_MODE (x));
8270 /* If MODE is narrower than HOST_WIDE_INT and CVAL is a negative
8271 number, sign extend it. */
8272 if (width > 0 && width < HOST_BITS_PER_WIDE_INT
8273 && (cval & ((unsigned HOST_WIDE_INT) 1 << (width - 1))) != 0)
8274 cval |= (unsigned HOST_WIDE_INT) -1 << width;
8276 y = simplify_gen_binary (AND, GET_MODE (x),
8277 XEXP (x, 0), GEN_INT (cval));
8278 if (set_src_cost (y, optimize_this_for_speed_p)
8279 < set_src_cost (x, optimize_this_for_speed_p))
8289 /* In (and (plus FOO C1) M), if M is a mask that just turns off
8290 low-order bits (as in an alignment operation) and FOO is already
8291 aligned to that boundary, mask C1 to that boundary as well.
8292 This may eliminate that PLUS and, later, the AND. */
8295 unsigned int width = GET_MODE_PRECISION (mode);
8296 unsigned HOST_WIDE_INT smask = mask;
8298 /* If MODE is narrower than HOST_WIDE_INT and mask is a negative
8299 number, sign extend it. */
8301 if (width < HOST_BITS_PER_WIDE_INT
8302 && (smask & ((unsigned HOST_WIDE_INT) 1 << (width - 1))) != 0)
8303 smask |= (unsigned HOST_WIDE_INT) (-1) << width;
8305 if (CONST_INT_P (XEXP (x, 1))
8306 && exact_log2 (- smask) >= 0
8307 && (nonzero_bits (XEXP (x, 0), mode) & ~smask) == 0
8308 && (INTVAL (XEXP (x, 1)) & ~smask) != 0)
8309 return force_to_mode (plus_constant (XEXP (x, 0),
8310 (INTVAL (XEXP (x, 1)) & smask)),
8311 mode, smask, next_select);
8314 /* ... fall through ... */
8317 /* For PLUS, MINUS and MULT, we need any bits less significant than the
8318 most significant bit in MASK since carries from those bits will
8319 affect the bits we are interested in. */
8324 /* If X is (minus C Y) where C's least set bit is larger than any bit
8325 in the mask, then we may replace with (neg Y). */
8326 if (CONST_INT_P (XEXP (x, 0))
8327 && (((unsigned HOST_WIDE_INT) (INTVAL (XEXP (x, 0))
8328 & -INTVAL (XEXP (x, 0))))
8331 x = simplify_gen_unary (NEG, GET_MODE (x), XEXP (x, 1),
8333 return force_to_mode (x, mode, mask, next_select);
8336 /* Similarly, if C contains every bit in the fuller_mask, then we may
8337 replace with (not Y). */
8338 if (CONST_INT_P (XEXP (x, 0))
8339 && ((UINTVAL (XEXP (x, 0)) | fuller_mask) == UINTVAL (XEXP (x, 0))))
8341 x = simplify_gen_unary (NOT, GET_MODE (x),
8342 XEXP (x, 1), GET_MODE (x));
8343 return force_to_mode (x, mode, mask, next_select);
8351 /* If X is (ior (lshiftrt FOO C1) C2), try to commute the IOR and
8352 LSHIFTRT so we end up with an (and (lshiftrt (ior ...) ...) ...)
8353 operation which may be a bitfield extraction. Ensure that the
8354 constant we form is not wider than the mode of X. */
8356 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
8357 && CONST_INT_P (XEXP (XEXP (x, 0), 1))
8358 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
8359 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT
8360 && CONST_INT_P (XEXP (x, 1))
8361 && ((INTVAL (XEXP (XEXP (x, 0), 1))
8362 + floor_log2 (INTVAL (XEXP (x, 1))))
8363 < GET_MODE_PRECISION (GET_MODE (x)))
8364 && (UINTVAL (XEXP (x, 1))
8365 & ~nonzero_bits (XEXP (x, 0), GET_MODE (x))) == 0)
8367 temp = GEN_INT ((INTVAL (XEXP (x, 1)) & mask)
8368 << INTVAL (XEXP (XEXP (x, 0), 1)));
8369 temp = simplify_gen_binary (GET_CODE (x), GET_MODE (x),
8370 XEXP (XEXP (x, 0), 0), temp);
8371 x = simplify_gen_binary (LSHIFTRT, GET_MODE (x), temp,
8372 XEXP (XEXP (x, 0), 1));
8373 return force_to_mode (x, mode, mask, next_select);
8377 /* For most binary operations, just propagate into the operation and
8378 change the mode if we have an operation of that mode. */
8380 op0 = force_to_mode (XEXP (x, 0), mode, mask, next_select);
8381 op1 = force_to_mode (XEXP (x, 1), mode, mask, next_select);
8383 /* If we ended up truncating both operands, truncate the result of the
8384 operation instead. */
8385 if (GET_CODE (op0) == TRUNCATE
8386 && GET_CODE (op1) == TRUNCATE)
8388 op0 = XEXP (op0, 0);
8389 op1 = XEXP (op1, 0);
8392 op0 = gen_lowpart_or_truncate (op_mode, op0);
8393 op1 = gen_lowpart_or_truncate (op_mode, op1);
8395 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
8396 x = simplify_gen_binary (code, op_mode, op0, op1);
8400 /* For left shifts, do the same, but just for the first operand.
8401 However, we cannot do anything with shifts where we cannot
8402 guarantee that the counts are smaller than the size of the mode
8403 because such a count will have a different meaning in a
8406 if (! (CONST_INT_P (XEXP (x, 1))
8407 && INTVAL (XEXP (x, 1)) >= 0
8408 && INTVAL (XEXP (x, 1)) < GET_MODE_PRECISION (mode))
8409 && ! (GET_MODE (XEXP (x, 1)) != VOIDmode
8410 && (nonzero_bits (XEXP (x, 1), GET_MODE (XEXP (x, 1)))
8411 < (unsigned HOST_WIDE_INT) GET_MODE_PRECISION (mode))))
8414 /* If the shift count is a constant and we can do arithmetic in
8415 the mode of the shift, refine which bits we need. Otherwise, use the
8416 conservative form of the mask. */
8417 if (CONST_INT_P (XEXP (x, 1))
8418 && INTVAL (XEXP (x, 1)) >= 0
8419 && INTVAL (XEXP (x, 1)) < GET_MODE_PRECISION (op_mode)
8420 && HWI_COMPUTABLE_MODE_P (op_mode))
8421 mask >>= INTVAL (XEXP (x, 1));
8425 op0 = gen_lowpart_or_truncate (op_mode,
8426 force_to_mode (XEXP (x, 0), op_mode,
8427 mask, next_select));
8429 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0))
8430 x = simplify_gen_binary (code, op_mode, op0, XEXP (x, 1));
8434 /* Here we can only do something if the shift count is a constant,
8435 this shift constant is valid for the host, and we can do arithmetic
8438 if (CONST_INT_P (XEXP (x, 1))
8439 && INTVAL (XEXP (x, 1)) >= 0
8440 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT
8441 && HWI_COMPUTABLE_MODE_P (op_mode))
8443 rtx inner = XEXP (x, 0);
8444 unsigned HOST_WIDE_INT inner_mask;
8446 /* Select the mask of the bits we need for the shift operand. */
8447 inner_mask = mask << INTVAL (XEXP (x, 1));
8449 /* We can only change the mode of the shift if we can do arithmetic
8450 in the mode of the shift and INNER_MASK is no wider than the
8451 width of X's mode. */
8452 if ((inner_mask & ~GET_MODE_MASK (GET_MODE (x))) != 0)
8453 op_mode = GET_MODE (x);
8455 inner = force_to_mode (inner, op_mode, inner_mask, next_select);
8457 if (GET_MODE (x) != op_mode || inner != XEXP (x, 0))
8458 x = simplify_gen_binary (LSHIFTRT, op_mode, inner, XEXP (x, 1));
8461 /* If we have (and (lshiftrt FOO C1) C2) where the combination of the
8462 shift and AND produces only copies of the sign bit (C2 is one less
8463 than a power of two), we can do this with just a shift. */
8465 if (GET_CODE (x) == LSHIFTRT
8466 && CONST_INT_P (XEXP (x, 1))
8467 /* The shift puts one of the sign bit copies in the least significant
8469 && ((INTVAL (XEXP (x, 1))
8470 + num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0))))
8471 >= GET_MODE_PRECISION (GET_MODE (x)))
8472 && exact_log2 (mask + 1) >= 0
8473 /* Number of bits left after the shift must be more than the mask
8475 && ((INTVAL (XEXP (x, 1)) + exact_log2 (mask + 1))
8476 <= GET_MODE_PRECISION (GET_MODE (x)))
8477 /* Must be more sign bit copies than the mask needs. */
8478 && ((int) num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
8479 >= exact_log2 (mask + 1)))
8480 x = simplify_gen_binary (LSHIFTRT, GET_MODE (x), XEXP (x, 0),
8481 GEN_INT (GET_MODE_PRECISION (GET_MODE (x))
8482 - exact_log2 (mask + 1)));
8487 /* If we are just looking for the sign bit, we don't need this shift at
8488 all, even if it has a variable count. */
8489 if (val_signbit_p (GET_MODE (x), mask))
8490 return force_to_mode (XEXP (x, 0), mode, mask, next_select);
8492 /* If this is a shift by a constant, get a mask that contains those bits
8493 that are not copies of the sign bit. We then have two cases: If
8494 MASK only includes those bits, this can be a logical shift, which may
8495 allow simplifications. If MASK is a single-bit field not within
8496 those bits, we are requesting a copy of the sign bit and hence can
8497 shift the sign bit to the appropriate location. */
8499 if (CONST_INT_P (XEXP (x, 1)) && INTVAL (XEXP (x, 1)) >= 0
8500 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT)
8504 /* If the considered data is wider than HOST_WIDE_INT, we can't
8505 represent a mask for all its bits in a single scalar.
8506 But we only care about the lower bits, so calculate these. */
8508 if (GET_MODE_PRECISION (GET_MODE (x)) > HOST_BITS_PER_WIDE_INT)
8510 nonzero = ~(unsigned HOST_WIDE_INT) 0;
8512 /* GET_MODE_PRECISION (GET_MODE (x)) - INTVAL (XEXP (x, 1))
8513 is the number of bits a full-width mask would have set.
8514 We need only shift if these are fewer than nonzero can
8515 hold. If not, we must keep all bits set in nonzero. */
8517 if (GET_MODE_PRECISION (GET_MODE (x)) - INTVAL (XEXP (x, 1))
8518 < HOST_BITS_PER_WIDE_INT)
8519 nonzero >>= INTVAL (XEXP (x, 1))
8520 + HOST_BITS_PER_WIDE_INT
8521 - GET_MODE_PRECISION (GET_MODE (x)) ;
8525 nonzero = GET_MODE_MASK (GET_MODE (x));
8526 nonzero >>= INTVAL (XEXP (x, 1));
8529 if ((mask & ~nonzero) == 0)
8531 x = simplify_shift_const (NULL_RTX, LSHIFTRT, GET_MODE (x),
8532 XEXP (x, 0), INTVAL (XEXP (x, 1)));
8533 if (GET_CODE (x) != ASHIFTRT)
8534 return force_to_mode (x, mode, mask, next_select);
8537 else if ((i = exact_log2 (mask)) >= 0)
8539 x = simplify_shift_const
8540 (NULL_RTX, LSHIFTRT, GET_MODE (x), XEXP (x, 0),
8541 GET_MODE_PRECISION (GET_MODE (x)) - 1 - i);
8543 if (GET_CODE (x) != ASHIFTRT)
8544 return force_to_mode (x, mode, mask, next_select);
8548 /* If MASK is 1, convert this to an LSHIFTRT. This can be done
8549 even if the shift count isn't a constant. */
8551 x = simplify_gen_binary (LSHIFTRT, GET_MODE (x),
8552 XEXP (x, 0), XEXP (x, 1));
8556 /* If this is a zero- or sign-extension operation that just affects bits
8557 we don't care about, remove it. Be sure the call above returned
8558 something that is still a shift. */
8560 if ((GET_CODE (x) == LSHIFTRT || GET_CODE (x) == ASHIFTRT)
8561 && CONST_INT_P (XEXP (x, 1))
8562 && INTVAL (XEXP (x, 1)) >= 0
8563 && (INTVAL (XEXP (x, 1))
8564 <= GET_MODE_PRECISION (GET_MODE (x)) - (floor_log2 (mask) + 1))
8565 && GET_CODE (XEXP (x, 0)) == ASHIFT
8566 && XEXP (XEXP (x, 0), 1) == XEXP (x, 1))
8567 return force_to_mode (XEXP (XEXP (x, 0), 0), mode, mask,
8574 /* If the shift count is constant and we can do computations
8575 in the mode of X, compute where the bits we care about are.
8576 Otherwise, we can't do anything. Don't change the mode of
8577 the shift or propagate MODE into the shift, though. */
8578 if (CONST_INT_P (XEXP (x, 1))
8579 && INTVAL (XEXP (x, 1)) >= 0)
8581 temp = simplify_binary_operation (code == ROTATE ? ROTATERT : ROTATE,
8582 GET_MODE (x), GEN_INT (mask),
8584 if (temp && CONST_INT_P (temp))
8586 force_to_mode (XEXP (x, 0), GET_MODE (x),
8587 INTVAL (temp), next_select));
8592 /* If we just want the low-order bit, the NEG isn't needed since it
8593 won't change the low-order bit. */
8595 return force_to_mode (XEXP (x, 0), mode, mask, just_select);
8597 /* We need any bits less significant than the most significant bit in
8598 MASK since carries from those bits will affect the bits we are
8604 /* (not FOO) is (xor FOO CONST), so if FOO is an LSHIFTRT, we can do the
8605 same as the XOR case above. Ensure that the constant we form is not
8606 wider than the mode of X. */
8608 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
8609 && CONST_INT_P (XEXP (XEXP (x, 0), 1))
8610 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
8611 && (INTVAL (XEXP (XEXP (x, 0), 1)) + floor_log2 (mask)
8612 < GET_MODE_PRECISION (GET_MODE (x)))
8613 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT)
8615 temp = gen_int_mode (mask << INTVAL (XEXP (XEXP (x, 0), 1)),
8617 temp = simplify_gen_binary (XOR, GET_MODE (x),
8618 XEXP (XEXP (x, 0), 0), temp);
8619 x = simplify_gen_binary (LSHIFTRT, GET_MODE (x),
8620 temp, XEXP (XEXP (x, 0), 1));
8622 return force_to_mode (x, mode, mask, next_select);
8625 /* (and (not FOO) CONST) is (not (or FOO (not CONST))), so we must
8626 use the full mask inside the NOT. */
8630 op0 = gen_lowpart_or_truncate (op_mode,
8631 force_to_mode (XEXP (x, 0), mode, mask,
8633 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0))
8634 x = simplify_gen_unary (code, op_mode, op0, op_mode);
8638 /* (and (ne FOO 0) CONST) can be (and FOO CONST) if CONST is included
8639 in STORE_FLAG_VALUE and FOO has a single bit that might be nonzero,
8640 which is equal to STORE_FLAG_VALUE. */
8641 if ((mask & ~STORE_FLAG_VALUE) == 0
8642 && XEXP (x, 1) == const0_rtx
8643 && GET_MODE (XEXP (x, 0)) == mode
8644 && exact_log2 (nonzero_bits (XEXP (x, 0), mode)) >= 0
8645 && (nonzero_bits (XEXP (x, 0), mode)
8646 == (unsigned HOST_WIDE_INT) STORE_FLAG_VALUE))
8647 return force_to_mode (XEXP (x, 0), mode, mask, next_select);
8652 /* We have no way of knowing if the IF_THEN_ELSE can itself be
8653 written in a narrower mode. We play it safe and do not do so. */
8656 gen_lowpart_or_truncate (GET_MODE (x),
8657 force_to_mode (XEXP (x, 1), mode,
8658 mask, next_select)));
8660 gen_lowpart_or_truncate (GET_MODE (x),
8661 force_to_mode (XEXP (x, 2), mode,
8662 mask, next_select)));
8669 /* Ensure we return a value of the proper mode. */
8670 return gen_lowpart_or_truncate (mode, x);
8673 /* Return nonzero if X is an expression that has one of two values depending on
8674 whether some other value is zero or nonzero. In that case, we return the
8675 value that is being tested, *PTRUE is set to the value if the rtx being
8676 returned has a nonzero value, and *PFALSE is set to the other alternative.
8678 If we return zero, we set *PTRUE and *PFALSE to X. */
8681 if_then_else_cond (rtx x, rtx *ptrue, rtx *pfalse)
8683 enum machine_mode mode = GET_MODE (x);
8684 enum rtx_code code = GET_CODE (x);
8685 rtx cond0, cond1, true0, true1, false0, false1;
8686 unsigned HOST_WIDE_INT nz;
8688 /* If we are comparing a value against zero, we are done. */
8689 if ((code == NE || code == EQ)
8690 && XEXP (x, 1) == const0_rtx)
8692 *ptrue = (code == NE) ? const_true_rtx : const0_rtx;
8693 *pfalse = (code == NE) ? const0_rtx : const_true_rtx;
8697 /* If this is a unary operation whose operand has one of two values, apply
8698 our opcode to compute those values. */
8699 else if (UNARY_P (x)
8700 && (cond0 = if_then_else_cond (XEXP (x, 0), &true0, &false0)) != 0)
8702 *ptrue = simplify_gen_unary (code, mode, true0, GET_MODE (XEXP (x, 0)));
8703 *pfalse = simplify_gen_unary (code, mode, false0,
8704 GET_MODE (XEXP (x, 0)));
8708 /* If this is a COMPARE, do nothing, since the IF_THEN_ELSE we would
8709 make can't possibly match and would suppress other optimizations. */
8710 else if (code == COMPARE)
8713 /* If this is a binary operation, see if either side has only one of two
8714 values. If either one does or if both do and they are conditional on
8715 the same value, compute the new true and false values. */
8716 else if (BINARY_P (x))
8718 cond0 = if_then_else_cond (XEXP (x, 0), &true0, &false0);
8719 cond1 = if_then_else_cond (XEXP (x, 1), &true1, &false1);
8721 if ((cond0 != 0 || cond1 != 0)
8722 && ! (cond0 != 0 && cond1 != 0 && ! rtx_equal_p (cond0, cond1)))
8724 /* If if_then_else_cond returned zero, then true/false are the
8725 same rtl. We must copy one of them to prevent invalid rtl
8728 true0 = copy_rtx (true0);
8729 else if (cond1 == 0)
8730 true1 = copy_rtx (true1);
8732 if (COMPARISON_P (x))
8734 *ptrue = simplify_gen_relational (code, mode, VOIDmode,
8736 *pfalse = simplify_gen_relational (code, mode, VOIDmode,
8741 *ptrue = simplify_gen_binary (code, mode, true0, true1);
8742 *pfalse = simplify_gen_binary (code, mode, false0, false1);
8745 return cond0 ? cond0 : cond1;
8748 /* See if we have PLUS, IOR, XOR, MINUS or UMAX, where one of the
8749 operands is zero when the other is nonzero, and vice-versa,
8750 and STORE_FLAG_VALUE is 1 or -1. */
8752 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
8753 && (code == PLUS || code == IOR || code == XOR || code == MINUS
8755 && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT)
8757 rtx op0 = XEXP (XEXP (x, 0), 1);
8758 rtx op1 = XEXP (XEXP (x, 1), 1);
8760 cond0 = XEXP (XEXP (x, 0), 0);
8761 cond1 = XEXP (XEXP (x, 1), 0);
8763 if (COMPARISON_P (cond0)
8764 && COMPARISON_P (cond1)
8765 && ((GET_CODE (cond0) == reversed_comparison_code (cond1, NULL)
8766 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0))
8767 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1)))
8768 || ((swap_condition (GET_CODE (cond0))
8769 == reversed_comparison_code (cond1, NULL))
8770 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1))
8771 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0))))
8772 && ! side_effects_p (x))
8774 *ptrue = simplify_gen_binary (MULT, mode, op0, const_true_rtx);
8775 *pfalse = simplify_gen_binary (MULT, mode,
8777 ? simplify_gen_unary (NEG, mode,
8785 /* Similarly for MULT, AND and UMIN, except that for these the result
8787 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
8788 && (code == MULT || code == AND || code == UMIN)
8789 && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT)
8791 cond0 = XEXP (XEXP (x, 0), 0);
8792 cond1 = XEXP (XEXP (x, 1), 0);
8794 if (COMPARISON_P (cond0)
8795 && COMPARISON_P (cond1)
8796 && ((GET_CODE (cond0) == reversed_comparison_code (cond1, NULL)
8797 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0))
8798 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1)))
8799 || ((swap_condition (GET_CODE (cond0))
8800 == reversed_comparison_code (cond1, NULL))
8801 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1))
8802 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0))))
8803 && ! side_effects_p (x))
8805 *ptrue = *pfalse = const0_rtx;
8811 else if (code == IF_THEN_ELSE)
8813 /* If we have IF_THEN_ELSE already, extract the condition and
8814 canonicalize it if it is NE or EQ. */
8815 cond0 = XEXP (x, 0);
8816 *ptrue = XEXP (x, 1), *pfalse = XEXP (x, 2);
8817 if (GET_CODE (cond0) == NE && XEXP (cond0, 1) == const0_rtx)
8818 return XEXP (cond0, 0);
8819 else if (GET_CODE (cond0) == EQ && XEXP (cond0, 1) == const0_rtx)
8821 *ptrue = XEXP (x, 2), *pfalse = XEXP (x, 1);
8822 return XEXP (cond0, 0);
8828 /* If X is a SUBREG, we can narrow both the true and false values
8829 if the inner expression, if there is a condition. */
8830 else if (code == SUBREG
8831 && 0 != (cond0 = if_then_else_cond (SUBREG_REG (x),
8834 true0 = simplify_gen_subreg (mode, true0,
8835 GET_MODE (SUBREG_REG (x)), SUBREG_BYTE (x));
8836 false0 = simplify_gen_subreg (mode, false0,
8837 GET_MODE (SUBREG_REG (x)), SUBREG_BYTE (x));
8838 if (true0 && false0)
8846 /* If X is a constant, this isn't special and will cause confusions
8847 if we treat it as such. Likewise if it is equivalent to a constant. */
8848 else if (CONSTANT_P (x)
8849 || ((cond0 = get_last_value (x)) != 0 && CONSTANT_P (cond0)))
8852 /* If we're in BImode, canonicalize on 0 and STORE_FLAG_VALUE, as that
8853 will be least confusing to the rest of the compiler. */
8854 else if (mode == BImode)
8856 *ptrue = GEN_INT (STORE_FLAG_VALUE), *pfalse = const0_rtx;
8860 /* If X is known to be either 0 or -1, those are the true and
8861 false values when testing X. */
8862 else if (x == constm1_rtx || x == const0_rtx
8863 || (mode != VOIDmode
8864 && num_sign_bit_copies (x, mode) == GET_MODE_PRECISION (mode)))
8866 *ptrue = constm1_rtx, *pfalse = const0_rtx;
8870 /* Likewise for 0 or a single bit. */
8871 else if (HWI_COMPUTABLE_MODE_P (mode)
8872 && exact_log2 (nz = nonzero_bits (x, mode)) >= 0)
8874 *ptrue = gen_int_mode (nz, mode), *pfalse = const0_rtx;
8878 /* Otherwise fail; show no condition with true and false values the same. */
8879 *ptrue = *pfalse = x;
8883 /* Return the value of expression X given the fact that condition COND
8884 is known to be true when applied to REG as its first operand and VAL
8885 as its second. X is known to not be shared and so can be modified in
8888 We only handle the simplest cases, and specifically those cases that
8889 arise with IF_THEN_ELSE expressions. */
8892 known_cond (rtx x, enum rtx_code cond, rtx reg, rtx val)
8894 enum rtx_code code = GET_CODE (x);
8899 if (side_effects_p (x))
8902 /* If either operand of the condition is a floating point value,
8903 then we have to avoid collapsing an EQ comparison. */
8905 && rtx_equal_p (x, reg)
8906 && ! FLOAT_MODE_P (GET_MODE (x))
8907 && ! FLOAT_MODE_P (GET_MODE (val)))
8910 if (cond == UNEQ && rtx_equal_p (x, reg))
8913 /* If X is (abs REG) and we know something about REG's relationship
8914 with zero, we may be able to simplify this. */
8916 if (code == ABS && rtx_equal_p (XEXP (x, 0), reg) && val == const0_rtx)
8919 case GE: case GT: case EQ:
8922 return simplify_gen_unary (NEG, GET_MODE (XEXP (x, 0)),
8924 GET_MODE (XEXP (x, 0)));
8929 /* The only other cases we handle are MIN, MAX, and comparisons if the
8930 operands are the same as REG and VAL. */
8932 else if (COMPARISON_P (x) || COMMUTATIVE_ARITH_P (x))
8934 if (rtx_equal_p (XEXP (x, 0), val))
8935 cond = swap_condition (cond), temp = val, val = reg, reg = temp;
8937 if (rtx_equal_p (XEXP (x, 0), reg) && rtx_equal_p (XEXP (x, 1), val))
8939 if (COMPARISON_P (x))
8941 if (comparison_dominates_p (cond, code))
8942 return const_true_rtx;
8944 code = reversed_comparison_code (x, NULL);
8946 && comparison_dominates_p (cond, code))
8951 else if (code == SMAX || code == SMIN
8952 || code == UMIN || code == UMAX)
8954 int unsignedp = (code == UMIN || code == UMAX);
8956 /* Do not reverse the condition when it is NE or EQ.
8957 This is because we cannot conclude anything about
8958 the value of 'SMAX (x, y)' when x is not equal to y,
8959 but we can when x equals y. */
8960 if ((code == SMAX || code == UMAX)
8961 && ! (cond == EQ || cond == NE))
8962 cond = reverse_condition (cond);
8967 return unsignedp ? x : XEXP (x, 1);
8969 return unsignedp ? x : XEXP (x, 0);
8971 return unsignedp ? XEXP (x, 1) : x;
8973 return unsignedp ? XEXP (x, 0) : x;
8980 else if (code == SUBREG)
8982 enum machine_mode inner_mode = GET_MODE (SUBREG_REG (x));
8983 rtx new_rtx, r = known_cond (SUBREG_REG (x), cond, reg, val);
8985 if (SUBREG_REG (x) != r)
8987 /* We must simplify subreg here, before we lose track of the
8988 original inner_mode. */
8989 new_rtx = simplify_subreg (GET_MODE (x), r,
8990 inner_mode, SUBREG_BYTE (x));
8994 SUBST (SUBREG_REG (x), r);
8999 /* We don't have to handle SIGN_EXTEND here, because even in the
9000 case of replacing something with a modeless CONST_INT, a
9001 CONST_INT is already (supposed to be) a valid sign extension for
9002 its narrower mode, which implies it's already properly
9003 sign-extended for the wider mode. Now, for ZERO_EXTEND, the
9004 story is different. */
9005 else if (code == ZERO_EXTEND)
9007 enum machine_mode inner_mode = GET_MODE (XEXP (x, 0));
9008 rtx new_rtx, r = known_cond (XEXP (x, 0), cond, reg, val);
9010 if (XEXP (x, 0) != r)
9012 /* We must simplify the zero_extend here, before we lose
9013 track of the original inner_mode. */
9014 new_rtx = simplify_unary_operation (ZERO_EXTEND, GET_MODE (x),
9019 SUBST (XEXP (x, 0), r);
9025 fmt = GET_RTX_FORMAT (code);
9026 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
9029 SUBST (XEXP (x, i), known_cond (XEXP (x, i), cond, reg, val));
9030 else if (fmt[i] == 'E')
9031 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
9032 SUBST (XVECEXP (x, i, j), known_cond (XVECEXP (x, i, j),
9039 /* See if X and Y are equal for the purposes of seeing if we can rewrite an
9040 assignment as a field assignment. */
9043 rtx_equal_for_field_assignment_p (rtx x, rtx y)
9045 if (x == y || rtx_equal_p (x, y))
9048 if (x == 0 || y == 0 || GET_MODE (x) != GET_MODE (y))
9051 /* Check for a paradoxical SUBREG of a MEM compared with the MEM.
9052 Note that all SUBREGs of MEM are paradoxical; otherwise they
9053 would have been rewritten. */
9054 if (MEM_P (x) && GET_CODE (y) == SUBREG
9055 && MEM_P (SUBREG_REG (y))
9056 && rtx_equal_p (SUBREG_REG (y),
9057 gen_lowpart (GET_MODE (SUBREG_REG (y)), x)))
9060 if (MEM_P (y) && GET_CODE (x) == SUBREG
9061 && MEM_P (SUBREG_REG (x))
9062 && rtx_equal_p (SUBREG_REG (x),
9063 gen_lowpart (GET_MODE (SUBREG_REG (x)), y)))
9066 /* We used to see if get_last_value of X and Y were the same but that's
9067 not correct. In one direction, we'll cause the assignment to have
9068 the wrong destination and in the case, we'll import a register into this
9069 insn that might have already have been dead. So fail if none of the
9070 above cases are true. */
9074 /* See if X, a SET operation, can be rewritten as a bit-field assignment.
9075 Return that assignment if so.
9077 We only handle the most common cases. */
9080 make_field_assignment (rtx x)
9082 rtx dest = SET_DEST (x);
9083 rtx src = SET_SRC (x);
9088 unsigned HOST_WIDE_INT len;
9090 enum machine_mode mode;
9092 /* If SRC was (and (not (ashift (const_int 1) POS)) DEST), this is
9093 a clear of a one-bit field. We will have changed it to
9094 (and (rotate (const_int -2) POS) DEST), so check for that. Also check
9097 if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == ROTATE
9098 && CONST_INT_P (XEXP (XEXP (src, 0), 0))
9099 && INTVAL (XEXP (XEXP (src, 0), 0)) == -2
9100 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
9102 assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1),
9105 return gen_rtx_SET (VOIDmode, assign, const0_rtx);
9109 if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == SUBREG
9110 && subreg_lowpart_p (XEXP (src, 0))
9111 && (GET_MODE_SIZE (GET_MODE (XEXP (src, 0)))
9112 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (src, 0)))))
9113 && GET_CODE (SUBREG_REG (XEXP (src, 0))) == ROTATE
9114 && CONST_INT_P (XEXP (SUBREG_REG (XEXP (src, 0)), 0))
9115 && INTVAL (XEXP (SUBREG_REG (XEXP (src, 0)), 0)) == -2
9116 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
9118 assign = make_extraction (VOIDmode, dest, 0,
9119 XEXP (SUBREG_REG (XEXP (src, 0)), 1),
9122 return gen_rtx_SET (VOIDmode, assign, const0_rtx);
9126 /* If SRC is (ior (ashift (const_int 1) POS) DEST), this is a set of a
9128 if (GET_CODE (src) == IOR && GET_CODE (XEXP (src, 0)) == ASHIFT
9129 && XEXP (XEXP (src, 0), 0) == const1_rtx
9130 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
9132 assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1),
9135 return gen_rtx_SET (VOIDmode, assign, const1_rtx);
9139 /* If DEST is already a field assignment, i.e. ZERO_EXTRACT, and the
9140 SRC is an AND with all bits of that field set, then we can discard
9142 if (GET_CODE (dest) == ZERO_EXTRACT
9143 && CONST_INT_P (XEXP (dest, 1))
9144 && GET_CODE (src) == AND
9145 && CONST_INT_P (XEXP (src, 1)))
9147 HOST_WIDE_INT width = INTVAL (XEXP (dest, 1));
9148 unsigned HOST_WIDE_INT and_mask = INTVAL (XEXP (src, 1));
9149 unsigned HOST_WIDE_INT ze_mask;
9151 if (width >= HOST_BITS_PER_WIDE_INT)
9154 ze_mask = ((unsigned HOST_WIDE_INT)1 << width) - 1;
9156 /* Complete overlap. We can remove the source AND. */
9157 if ((and_mask & ze_mask) == ze_mask)
9158 return gen_rtx_SET (VOIDmode, dest, XEXP (src, 0));
9160 /* Partial overlap. We can reduce the source AND. */
9161 if ((and_mask & ze_mask) != and_mask)
9163 mode = GET_MODE (src);
9164 src = gen_rtx_AND (mode, XEXP (src, 0),
9165 gen_int_mode (and_mask & ze_mask, mode));
9166 return gen_rtx_SET (VOIDmode, dest, src);
9170 /* The other case we handle is assignments into a constant-position
9171 field. They look like (ior/xor (and DEST C1) OTHER). If C1 represents
9172 a mask that has all one bits except for a group of zero bits and
9173 OTHER is known to have zeros where C1 has ones, this is such an
9174 assignment. Compute the position and length from C1. Shift OTHER
9175 to the appropriate position, force it to the required mode, and
9176 make the extraction. Check for the AND in both operands. */
9178 if (GET_CODE (src) != IOR && GET_CODE (src) != XOR)
9181 rhs = expand_compound_operation (XEXP (src, 0));
9182 lhs = expand_compound_operation (XEXP (src, 1));
9184 if (GET_CODE (rhs) == AND
9185 && CONST_INT_P (XEXP (rhs, 1))
9186 && rtx_equal_for_field_assignment_p (XEXP (rhs, 0), dest))
9187 c1 = INTVAL (XEXP (rhs, 1)), other = lhs;
9188 else if (GET_CODE (lhs) == AND
9189 && CONST_INT_P (XEXP (lhs, 1))
9190 && rtx_equal_for_field_assignment_p (XEXP (lhs, 0), dest))
9191 c1 = INTVAL (XEXP (lhs, 1)), other = rhs;
9195 pos = get_pos_from_mask ((~c1) & GET_MODE_MASK (GET_MODE (dest)), &len);
9196 if (pos < 0 || pos + len > GET_MODE_PRECISION (GET_MODE (dest))
9197 || GET_MODE_PRECISION (GET_MODE (dest)) > HOST_BITS_PER_WIDE_INT
9198 || (c1 & nonzero_bits (other, GET_MODE (dest))) != 0)
9201 assign = make_extraction (VOIDmode, dest, pos, NULL_RTX, len, 1, 1, 0);
9205 /* The mode to use for the source is the mode of the assignment, or of
9206 what is inside a possible STRICT_LOW_PART. */
9207 mode = (GET_CODE (assign) == STRICT_LOW_PART
9208 ? GET_MODE (XEXP (assign, 0)) : GET_MODE (assign));
9210 /* Shift OTHER right POS places and make it the source, restricting it
9211 to the proper length and mode. */
9213 src = canon_reg_for_combine (simplify_shift_const (NULL_RTX, LSHIFTRT,
9217 src = force_to_mode (src, mode,
9218 GET_MODE_PRECISION (mode) >= HOST_BITS_PER_WIDE_INT
9219 ? ~(unsigned HOST_WIDE_INT) 0
9220 : ((unsigned HOST_WIDE_INT) 1 << len) - 1,
9223 /* If SRC is masked by an AND that does not make a difference in
9224 the value being stored, strip it. */
9225 if (GET_CODE (assign) == ZERO_EXTRACT
9226 && CONST_INT_P (XEXP (assign, 1))
9227 && INTVAL (XEXP (assign, 1)) < HOST_BITS_PER_WIDE_INT
9228 && GET_CODE (src) == AND
9229 && CONST_INT_P (XEXP (src, 1))
9230 && UINTVAL (XEXP (src, 1))
9231 == ((unsigned HOST_WIDE_INT) 1 << INTVAL (XEXP (assign, 1))) - 1)
9232 src = XEXP (src, 0);
9234 return gen_rtx_SET (VOIDmode, assign, src);
9237 /* See if X is of the form (+ (* a c) (* b c)) and convert to (* (+ a b) c)
9241 apply_distributive_law (rtx x)
9243 enum rtx_code code = GET_CODE (x);
9244 enum rtx_code inner_code;
9245 rtx lhs, rhs, other;
9248 /* Distributivity is not true for floating point as it can change the
9249 value. So we don't do it unless -funsafe-math-optimizations. */
9250 if (FLOAT_MODE_P (GET_MODE (x))
9251 && ! flag_unsafe_math_optimizations)
9254 /* The outer operation can only be one of the following: */
9255 if (code != IOR && code != AND && code != XOR
9256 && code != PLUS && code != MINUS)
9262 /* If either operand is a primitive we can't do anything, so get out
9264 if (OBJECT_P (lhs) || OBJECT_P (rhs))
9267 lhs = expand_compound_operation (lhs);
9268 rhs = expand_compound_operation (rhs);
9269 inner_code = GET_CODE (lhs);
9270 if (inner_code != GET_CODE (rhs))
9273 /* See if the inner and outer operations distribute. */
9280 /* These all distribute except over PLUS. */
9281 if (code == PLUS || code == MINUS)
9286 if (code != PLUS && code != MINUS)
9291 /* This is also a multiply, so it distributes over everything. */
9295 /* Non-paradoxical SUBREGs distributes over all operations,
9296 provided the inner modes and byte offsets are the same, this
9297 is an extraction of a low-order part, we don't convert an fp
9298 operation to int or vice versa, this is not a vector mode,
9299 and we would not be converting a single-word operation into a
9300 multi-word operation. The latter test is not required, but
9301 it prevents generating unneeded multi-word operations. Some
9302 of the previous tests are redundant given the latter test,
9303 but are retained because they are required for correctness.
9305 We produce the result slightly differently in this case. */
9307 if (GET_MODE (SUBREG_REG (lhs)) != GET_MODE (SUBREG_REG (rhs))
9308 || SUBREG_BYTE (lhs) != SUBREG_BYTE (rhs)
9309 || ! subreg_lowpart_p (lhs)
9310 || (GET_MODE_CLASS (GET_MODE (lhs))
9311 != GET_MODE_CLASS (GET_MODE (SUBREG_REG (lhs))))
9312 || paradoxical_subreg_p (lhs)
9313 || VECTOR_MODE_P (GET_MODE (lhs))
9314 || GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs))) > UNITS_PER_WORD
9315 /* Result might need to be truncated. Don't change mode if
9316 explicit truncation is needed. */
9317 || !TRULY_NOOP_TRUNCATION_MODES_P (GET_MODE (x),
9318 GET_MODE (SUBREG_REG (lhs))))
9321 tem = simplify_gen_binary (code, GET_MODE (SUBREG_REG (lhs)),
9322 SUBREG_REG (lhs), SUBREG_REG (rhs));
9323 return gen_lowpart (GET_MODE (x), tem);
9329 /* Set LHS and RHS to the inner operands (A and B in the example
9330 above) and set OTHER to the common operand (C in the example).
9331 There is only one way to do this unless the inner operation is
9333 if (COMMUTATIVE_ARITH_P (lhs)
9334 && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 0)))
9335 other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 1);
9336 else if (COMMUTATIVE_ARITH_P (lhs)
9337 && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 1)))
9338 other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 0);
9339 else if (COMMUTATIVE_ARITH_P (lhs)
9340 && rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 0)))
9341 other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 1);
9342 else if (rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 1)))
9343 other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 0);
9347 /* Form the new inner operation, seeing if it simplifies first. */
9348 tem = simplify_gen_binary (code, GET_MODE (x), lhs, rhs);
9350 /* There is one exception to the general way of distributing:
9351 (a | c) ^ (b | c) -> (a ^ b) & ~c */
9352 if (code == XOR && inner_code == IOR)
9355 other = simplify_gen_unary (NOT, GET_MODE (x), other, GET_MODE (x));
9358 /* We may be able to continuing distributing the result, so call
9359 ourselves recursively on the inner operation before forming the
9360 outer operation, which we return. */
9361 return simplify_gen_binary (inner_code, GET_MODE (x),
9362 apply_distributive_law (tem), other);
9365 /* See if X is of the form (* (+ A B) C), and if so convert to
9366 (+ (* A C) (* B C)) and try to simplify.
9368 Most of the time, this results in no change. However, if some of
9369 the operands are the same or inverses of each other, simplifications
9372 For example, (and (ior A B) (not B)) can occur as the result of
9373 expanding a bit field assignment. When we apply the distributive
9374 law to this, we get (ior (and (A (not B))) (and (B (not B)))),
9375 which then simplifies to (and (A (not B))).
9377 Note that no checks happen on the validity of applying the inverse
9378 distributive law. This is pointless since we can do it in the
9379 few places where this routine is called.
9381 N is the index of the term that is decomposed (the arithmetic operation,
9382 i.e. (+ A B) in the first example above). !N is the index of the term that
9383 is distributed, i.e. of C in the first example above. */
9385 distribute_and_simplify_rtx (rtx x, int n)
9387 enum machine_mode mode;
9388 enum rtx_code outer_code, inner_code;
9389 rtx decomposed, distributed, inner_op0, inner_op1, new_op0, new_op1, tmp;
9391 /* Distributivity is not true for floating point as it can change the
9392 value. So we don't do it unless -funsafe-math-optimizations. */
9393 if (FLOAT_MODE_P (GET_MODE (x))
9394 && ! flag_unsafe_math_optimizations)
9397 decomposed = XEXP (x, n);
9398 if (!ARITHMETIC_P (decomposed))
9401 mode = GET_MODE (x);
9402 outer_code = GET_CODE (x);
9403 distributed = XEXP (x, !n);
9405 inner_code = GET_CODE (decomposed);
9406 inner_op0 = XEXP (decomposed, 0);
9407 inner_op1 = XEXP (decomposed, 1);
9409 /* Special case (and (xor B C) (not A)), which is equivalent to
9410 (xor (ior A B) (ior A C)) */
9411 if (outer_code == AND && inner_code == XOR && GET_CODE (distributed) == NOT)
9413 distributed = XEXP (distributed, 0);
9419 /* Distribute the second term. */
9420 new_op0 = simplify_gen_binary (outer_code, mode, inner_op0, distributed);
9421 new_op1 = simplify_gen_binary (outer_code, mode, inner_op1, distributed);
9425 /* Distribute the first term. */
9426 new_op0 = simplify_gen_binary (outer_code, mode, distributed, inner_op0);
9427 new_op1 = simplify_gen_binary (outer_code, mode, distributed, inner_op1);
9430 tmp = apply_distributive_law (simplify_gen_binary (inner_code, mode,
9432 if (GET_CODE (tmp) != outer_code
9433 && (set_src_cost (tmp, optimize_this_for_speed_p)
9434 < set_src_cost (x, optimize_this_for_speed_p)))
9440 /* Simplify a logical `and' of VAROP with the constant CONSTOP, to be done
9441 in MODE. Return an equivalent form, if different from (and VAROP
9442 (const_int CONSTOP)). Otherwise, return NULL_RTX. */
9445 simplify_and_const_int_1 (enum machine_mode mode, rtx varop,
9446 unsigned HOST_WIDE_INT constop)
9448 unsigned HOST_WIDE_INT nonzero;
9449 unsigned HOST_WIDE_INT orig_constop;
9454 orig_constop = constop;
9455 if (GET_CODE (varop) == CLOBBER)
9458 /* Simplify VAROP knowing that we will be only looking at some of the
9461 Note by passing in CONSTOP, we guarantee that the bits not set in
9462 CONSTOP are not significant and will never be examined. We must
9463 ensure that is the case by explicitly masking out those bits
9464 before returning. */
9465 varop = force_to_mode (varop, mode, constop, 0);
9467 /* If VAROP is a CLOBBER, we will fail so return it. */
9468 if (GET_CODE (varop) == CLOBBER)
9471 /* If VAROP is a CONST_INT, then we need to apply the mask in CONSTOP
9472 to VAROP and return the new constant. */
9473 if (CONST_INT_P (varop))
9474 return gen_int_mode (INTVAL (varop) & constop, mode);
9476 /* See what bits may be nonzero in VAROP. Unlike the general case of
9477 a call to nonzero_bits, here we don't care about bits outside
9480 nonzero = nonzero_bits (varop, mode) & GET_MODE_MASK (mode);
9482 /* Turn off all bits in the constant that are known to already be zero.
9483 Thus, if the AND isn't needed at all, we will have CONSTOP == NONZERO_BITS
9484 which is tested below. */
9488 /* If we don't have any bits left, return zero. */
9492 /* If VAROP is a NEG of something known to be zero or 1 and CONSTOP is
9493 a power of two, we can replace this with an ASHIFT. */
9494 if (GET_CODE (varop) == NEG && nonzero_bits (XEXP (varop, 0), mode) == 1
9495 && (i = exact_log2 (constop)) >= 0)
9496 return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (varop, 0), i);
9498 /* If VAROP is an IOR or XOR, apply the AND to both branches of the IOR
9499 or XOR, then try to apply the distributive law. This may eliminate
9500 operations if either branch can be simplified because of the AND.
9501 It may also make some cases more complex, but those cases probably
9502 won't match a pattern either with or without this. */
9504 if (GET_CODE (varop) == IOR || GET_CODE (varop) == XOR)
9508 apply_distributive_law
9509 (simplify_gen_binary (GET_CODE (varop), GET_MODE (varop),
9510 simplify_and_const_int (NULL_RTX,
9514 simplify_and_const_int (NULL_RTX,
9519 /* If VAROP is PLUS, and the constant is a mask of low bits, distribute
9520 the AND and see if one of the operands simplifies to zero. If so, we
9521 may eliminate it. */
9523 if (GET_CODE (varop) == PLUS
9524 && exact_log2 (constop + 1) >= 0)
9528 o0 = simplify_and_const_int (NULL_RTX, mode, XEXP (varop, 0), constop);
9529 o1 = simplify_and_const_int (NULL_RTX, mode, XEXP (varop, 1), constop);
9530 if (o0 == const0_rtx)
9532 if (o1 == const0_rtx)
9536 /* Make a SUBREG if necessary. If we can't make it, fail. */
9537 varop = gen_lowpart (mode, varop);
9538 if (varop == NULL_RTX || GET_CODE (varop) == CLOBBER)
9541 /* If we are only masking insignificant bits, return VAROP. */
9542 if (constop == nonzero)
9545 if (varop == orig_varop && constop == orig_constop)
9548 /* Otherwise, return an AND. */
9549 return simplify_gen_binary (AND, mode, varop, gen_int_mode (constop, mode));
9553 /* We have X, a logical `and' of VAROP with the constant CONSTOP, to be done
9556 Return an equivalent form, if different from X. Otherwise, return X. If
9557 X is zero, we are to always construct the equivalent form. */
9560 simplify_and_const_int (rtx x, enum machine_mode mode, rtx varop,
9561 unsigned HOST_WIDE_INT constop)
9563 rtx tem = simplify_and_const_int_1 (mode, varop, constop);
9568 x = simplify_gen_binary (AND, GET_MODE (varop), varop,
9569 gen_int_mode (constop, mode));
9570 if (GET_MODE (x) != mode)
9571 x = gen_lowpart (mode, x);
9575 /* Given a REG, X, compute which bits in X can be nonzero.
9576 We don't care about bits outside of those defined in MODE.
9578 For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is
9579 a shift, AND, or zero_extract, we can do better. */
9582 reg_nonzero_bits_for_combine (const_rtx x, enum machine_mode mode,
9583 const_rtx known_x ATTRIBUTE_UNUSED,
9584 enum machine_mode known_mode ATTRIBUTE_UNUSED,
9585 unsigned HOST_WIDE_INT known_ret ATTRIBUTE_UNUSED,
9586 unsigned HOST_WIDE_INT *nonzero)
9591 /* If X is a register whose nonzero bits value is current, use it.
9592 Otherwise, if X is a register whose value we can find, use that
9593 value. Otherwise, use the previously-computed global nonzero bits
9594 for this register. */
9596 rsp = VEC_index (reg_stat_type, reg_stat, REGNO (x));
9597 if (rsp->last_set_value != 0
9598 && (rsp->last_set_mode == mode
9599 || (GET_MODE_CLASS (rsp->last_set_mode) == MODE_INT
9600 && GET_MODE_CLASS (mode) == MODE_INT))
9601 && ((rsp->last_set_label >= label_tick_ebb_start
9602 && rsp->last_set_label < label_tick)
9603 || (rsp->last_set_label == label_tick
9604 && DF_INSN_LUID (rsp->last_set) < subst_low_luid)
9605 || (REGNO (x) >= FIRST_PSEUDO_REGISTER
9606 && REG_N_SETS (REGNO (x)) == 1
9608 (DF_LR_IN (ENTRY_BLOCK_PTR->next_bb), REGNO (x)))))
9610 *nonzero &= rsp->last_set_nonzero_bits;
9614 tem = get_last_value (x);
9618 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
9619 /* If X is narrower than MODE and TEM is a non-negative
9620 constant that would appear negative in the mode of X,
9621 sign-extend it for use in reg_nonzero_bits because some
9622 machines (maybe most) will actually do the sign-extension
9623 and this is the conservative approach.
9625 ??? For 2.5, try to tighten up the MD files in this regard
9626 instead of this kludge. */
9628 if (GET_MODE_PRECISION (GET_MODE (x)) < GET_MODE_PRECISION (mode)
9629 && CONST_INT_P (tem)
9631 && val_signbit_known_set_p (GET_MODE (x), INTVAL (tem)))
9632 tem = GEN_INT (INTVAL (tem) | ~GET_MODE_MASK (GET_MODE (x)));
9636 else if (nonzero_sign_valid && rsp->nonzero_bits)
9638 unsigned HOST_WIDE_INT mask = rsp->nonzero_bits;
9640 if (GET_MODE_PRECISION (GET_MODE (x)) < GET_MODE_PRECISION (mode))
9641 /* We don't know anything about the upper bits. */
9642 mask |= GET_MODE_MASK (mode) ^ GET_MODE_MASK (GET_MODE (x));
9649 /* Return the number of bits at the high-order end of X that are known to
9650 be equal to the sign bit. X will be used in mode MODE; if MODE is
9651 VOIDmode, X will be used in its own mode. The returned value will always
9652 be between 1 and the number of bits in MODE. */
9655 reg_num_sign_bit_copies_for_combine (const_rtx x, enum machine_mode mode,
9656 const_rtx known_x ATTRIBUTE_UNUSED,
9657 enum machine_mode known_mode
9659 unsigned int known_ret ATTRIBUTE_UNUSED,
9660 unsigned int *result)
9665 rsp = VEC_index (reg_stat_type, reg_stat, REGNO (x));
9666 if (rsp->last_set_value != 0
9667 && rsp->last_set_mode == mode
9668 && ((rsp->last_set_label >= label_tick_ebb_start
9669 && rsp->last_set_label < label_tick)
9670 || (rsp->last_set_label == label_tick
9671 && DF_INSN_LUID (rsp->last_set) < subst_low_luid)
9672 || (REGNO (x) >= FIRST_PSEUDO_REGISTER
9673 && REG_N_SETS (REGNO (x)) == 1
9675 (DF_LR_IN (ENTRY_BLOCK_PTR->next_bb), REGNO (x)))))
9677 *result = rsp->last_set_sign_bit_copies;
9681 tem = get_last_value (x);
9685 if (nonzero_sign_valid && rsp->sign_bit_copies != 0
9686 && GET_MODE_PRECISION (GET_MODE (x)) == GET_MODE_PRECISION (mode))
9687 *result = rsp->sign_bit_copies;
9692 /* Return the number of "extended" bits there are in X, when interpreted
9693 as a quantity in MODE whose signedness is indicated by UNSIGNEDP. For
9694 unsigned quantities, this is the number of high-order zero bits.
9695 For signed quantities, this is the number of copies of the sign bit
9696 minus 1. In both case, this function returns the number of "spare"
9697 bits. For example, if two quantities for which this function returns
9698 at least 1 are added, the addition is known not to overflow.
9700 This function will always return 0 unless called during combine, which
9701 implies that it must be called from a define_split. */
9704 extended_count (const_rtx x, enum machine_mode mode, int unsignedp)
9706 if (nonzero_sign_valid == 0)
9710 ? (HWI_COMPUTABLE_MODE_P (mode)
9711 ? (unsigned int) (GET_MODE_PRECISION (mode) - 1
9712 - floor_log2 (nonzero_bits (x, mode)))
9714 : num_sign_bit_copies (x, mode) - 1);
9717 /* This function is called from `simplify_shift_const' to merge two
9718 outer operations. Specifically, we have already found that we need
9719 to perform operation *POP0 with constant *PCONST0 at the outermost
9720 position. We would now like to also perform OP1 with constant CONST1
9721 (with *POP0 being done last).
9723 Return 1 if we can do the operation and update *POP0 and *PCONST0 with
9724 the resulting operation. *PCOMP_P is set to 1 if we would need to
9725 complement the innermost operand, otherwise it is unchanged.
9727 MODE is the mode in which the operation will be done. No bits outside
9728 the width of this mode matter. It is assumed that the width of this mode
9729 is smaller than or equal to HOST_BITS_PER_WIDE_INT.
9731 If *POP0 or OP1 are UNKNOWN, it means no operation is required. Only NEG, PLUS,
9732 IOR, XOR, and AND are supported. We may set *POP0 to SET if the proper
9733 result is simply *PCONST0.
9735 If the resulting operation cannot be expressed as one operation, we
9736 return 0 and do not change *POP0, *PCONST0, and *PCOMP_P. */
9739 merge_outer_ops (enum rtx_code *pop0, HOST_WIDE_INT *pconst0, enum rtx_code op1, HOST_WIDE_INT const1, enum machine_mode mode, int *pcomp_p)
9741 enum rtx_code op0 = *pop0;
9742 HOST_WIDE_INT const0 = *pconst0;
9744 const0 &= GET_MODE_MASK (mode);
9745 const1 &= GET_MODE_MASK (mode);
9747 /* If OP0 is an AND, clear unimportant bits in CONST1. */
9751 /* If OP0 or OP1 is UNKNOWN, this is easy. Similarly if they are the same or
9754 if (op1 == UNKNOWN || op0 == SET)
9757 else if (op0 == UNKNOWN)
9758 op0 = op1, const0 = const1;
9760 else if (op0 == op1)
9784 /* Otherwise, if either is a PLUS or NEG, we can't do anything. */
9785 else if (op0 == PLUS || op1 == PLUS || op0 == NEG || op1 == NEG)
9788 /* If the two constants aren't the same, we can't do anything. The
9789 remaining six cases can all be done. */
9790 else if (const0 != const1)
9798 /* (a & b) | b == b */
9800 else /* op1 == XOR */
9801 /* (a ^ b) | b == a | b */
9807 /* (a & b) ^ b == (~a) & b */
9808 op0 = AND, *pcomp_p = 1;
9809 else /* op1 == IOR */
9810 /* (a | b) ^ b == a & ~b */
9811 op0 = AND, const0 = ~const0;
9816 /* (a | b) & b == b */
9818 else /* op1 == XOR */
9819 /* (a ^ b) & b) == (~a) & b */
9826 /* Check for NO-OP cases. */
9827 const0 &= GET_MODE_MASK (mode);
9829 && (op0 == IOR || op0 == XOR || op0 == PLUS))
9831 else if (const0 == 0 && op0 == AND)
9833 else if ((unsigned HOST_WIDE_INT) const0 == GET_MODE_MASK (mode)
9839 /* ??? Slightly redundant with the above mask, but not entirely.
9840 Moving this above means we'd have to sign-extend the mode mask
9841 for the final test. */
9842 if (op0 != UNKNOWN && op0 != NEG)
9843 *pconst0 = trunc_int_for_mode (const0, mode);
9848 /* A helper to simplify_shift_const_1 to determine the mode we can perform
9849 the shift in. The original shift operation CODE is performed on OP in
9850 ORIG_MODE. Return the wider mode MODE if we can perform the operation
9851 in that mode. Return ORIG_MODE otherwise. We can also assume that the
9852 result of the shift is subject to operation OUTER_CODE with operand
9855 static enum machine_mode
9856 try_widen_shift_mode (enum rtx_code code, rtx op, int count,
9857 enum machine_mode orig_mode, enum machine_mode mode,
9858 enum rtx_code outer_code, HOST_WIDE_INT outer_const)
9860 if (orig_mode == mode)
9862 gcc_assert (GET_MODE_PRECISION (mode) > GET_MODE_PRECISION (orig_mode));
9864 /* In general we can't perform in wider mode for right shift and rotate. */
9868 /* We can still widen if the bits brought in from the left are identical
9869 to the sign bit of ORIG_MODE. */
9870 if (num_sign_bit_copies (op, mode)
9871 > (unsigned) (GET_MODE_PRECISION (mode)
9872 - GET_MODE_PRECISION (orig_mode)))
9877 /* Similarly here but with zero bits. */
9878 if (HWI_COMPUTABLE_MODE_P (mode)
9879 && (nonzero_bits (op, mode) & ~GET_MODE_MASK (orig_mode)) == 0)
9882 /* We can also widen if the bits brought in will be masked off. This
9883 operation is performed in ORIG_MODE. */
9884 if (outer_code == AND)
9886 int care_bits = low_bitmask_len (orig_mode, outer_const);
9889 && GET_MODE_PRECISION (orig_mode) - care_bits >= count)
9905 /* Simplify a shift of VAROP by ORIG_COUNT bits. CODE says what kind
9906 of shift. The result of the shift is RESULT_MODE. Return NULL_RTX
9907 if we cannot simplify it. Otherwise, return a simplified value.
9909 The shift is normally computed in the widest mode we find in VAROP, as
9910 long as it isn't a different number of words than RESULT_MODE. Exceptions
9911 are ASHIFTRT and ROTATE, which are always done in their original mode. */
9914 simplify_shift_const_1 (enum rtx_code code, enum machine_mode result_mode,
9915 rtx varop, int orig_count)
9917 enum rtx_code orig_code = code;
9918 rtx orig_varop = varop;
9920 enum machine_mode mode = result_mode;
9921 enum machine_mode shift_mode, tmode;
9922 unsigned int mode_words
9923 = (GET_MODE_SIZE (mode) + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD;
9924 /* We form (outer_op (code varop count) (outer_const)). */
9925 enum rtx_code outer_op = UNKNOWN;
9926 HOST_WIDE_INT outer_const = 0;
9927 int complement_p = 0;
9930 /* Make sure and truncate the "natural" shift on the way in. We don't
9931 want to do this inside the loop as it makes it more difficult to
9933 if (SHIFT_COUNT_TRUNCATED)
9934 orig_count &= GET_MODE_BITSIZE (mode) - 1;
9936 /* If we were given an invalid count, don't do anything except exactly
9937 what was requested. */
9939 if (orig_count < 0 || orig_count >= (int) GET_MODE_PRECISION (mode))
9944 /* Unless one of the branches of the `if' in this loop does a `continue',
9945 we will `break' the loop after the `if'. */
9949 /* If we have an operand of (clobber (const_int 0)), fail. */
9950 if (GET_CODE (varop) == CLOBBER)
9953 /* Convert ROTATERT to ROTATE. */
9954 if (code == ROTATERT)
9956 unsigned int bitsize = GET_MODE_PRECISION (result_mode);
9958 if (VECTOR_MODE_P (result_mode))
9959 count = bitsize / GET_MODE_NUNITS (result_mode) - count;
9961 count = bitsize - count;
9964 shift_mode = try_widen_shift_mode (code, varop, count, result_mode,
9965 mode, outer_op, outer_const);
9967 /* Handle cases where the count is greater than the size of the mode
9968 minus 1. For ASHIFT, use the size minus one as the count (this can
9969 occur when simplifying (lshiftrt (ashiftrt ..))). For rotates,
9970 take the count modulo the size. For other shifts, the result is
9973 Since these shifts are being produced by the compiler by combining
9974 multiple operations, each of which are defined, we know what the
9975 result is supposed to be. */
9977 if (count > (GET_MODE_PRECISION (shift_mode) - 1))
9979 if (code == ASHIFTRT)
9980 count = GET_MODE_PRECISION (shift_mode) - 1;
9981 else if (code == ROTATE || code == ROTATERT)
9982 count %= GET_MODE_PRECISION (shift_mode);
9985 /* We can't simply return zero because there may be an
9993 /* If we discovered we had to complement VAROP, leave. Making a NOT
9994 here would cause an infinite loop. */
9998 /* An arithmetic right shift of a quantity known to be -1 or 0
10000 if (code == ASHIFTRT
10001 && (num_sign_bit_copies (varop, shift_mode)
10002 == GET_MODE_PRECISION (shift_mode)))
10008 /* If we are doing an arithmetic right shift and discarding all but
10009 the sign bit copies, this is equivalent to doing a shift by the
10010 bitsize minus one. Convert it into that shift because it will often
10011 allow other simplifications. */
10013 if (code == ASHIFTRT
10014 && (count + num_sign_bit_copies (varop, shift_mode)
10015 >= GET_MODE_PRECISION (shift_mode)))
10016 count = GET_MODE_PRECISION (shift_mode) - 1;
10018 /* We simplify the tests below and elsewhere by converting
10019 ASHIFTRT to LSHIFTRT if we know the sign bit is clear.
10020 `make_compound_operation' will convert it to an ASHIFTRT for
10021 those machines (such as VAX) that don't have an LSHIFTRT. */
10022 if (code == ASHIFTRT
10023 && val_signbit_known_clear_p (shift_mode,
10024 nonzero_bits (varop, shift_mode)))
10027 if (((code == LSHIFTRT
10028 && HWI_COMPUTABLE_MODE_P (shift_mode)
10029 && !(nonzero_bits (varop, shift_mode) >> count))
10031 && HWI_COMPUTABLE_MODE_P (shift_mode)
10032 && !((nonzero_bits (varop, shift_mode) << count)
10033 & GET_MODE_MASK (shift_mode))))
10034 && !side_effects_p (varop))
10035 varop = const0_rtx;
10037 switch (GET_CODE (varop))
10043 new_rtx = expand_compound_operation (varop);
10044 if (new_rtx != varop)
10052 /* If we have (xshiftrt (mem ...) C) and C is MODE_WIDTH
10053 minus the width of a smaller mode, we can do this with a
10054 SIGN_EXTEND or ZERO_EXTEND from the narrower memory location. */
10055 if ((code == ASHIFTRT || code == LSHIFTRT)
10056 && ! mode_dependent_address_p (XEXP (varop, 0))
10057 && ! MEM_VOLATILE_P (varop)
10058 && (tmode = mode_for_size (GET_MODE_BITSIZE (mode) - count,
10059 MODE_INT, 1)) != BLKmode)
10061 new_rtx = adjust_address_nv (varop, tmode,
10062 BYTES_BIG_ENDIAN ? 0
10063 : count / BITS_PER_UNIT);
10065 varop = gen_rtx_fmt_e (code == ASHIFTRT ? SIGN_EXTEND
10066 : ZERO_EXTEND, mode, new_rtx);
10073 /* If VAROP is a SUBREG, strip it as long as the inner operand has
10074 the same number of words as what we've seen so far. Then store
10075 the widest mode in MODE. */
10076 if (subreg_lowpart_p (varop)
10077 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop)))
10078 > GET_MODE_SIZE (GET_MODE (varop)))
10079 && (unsigned int) ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop)))
10080 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
10082 && GET_MODE_CLASS (GET_MODE (varop)) == MODE_INT
10083 && GET_MODE_CLASS (GET_MODE (SUBREG_REG (varop))) == MODE_INT)
10085 varop = SUBREG_REG (varop);
10086 if (GET_MODE_SIZE (GET_MODE (varop)) > GET_MODE_SIZE (mode))
10087 mode = GET_MODE (varop);
10093 /* Some machines use MULT instead of ASHIFT because MULT
10094 is cheaper. But it is still better on those machines to
10095 merge two shifts into one. */
10096 if (CONST_INT_P (XEXP (varop, 1))
10097 && exact_log2 (UINTVAL (XEXP (varop, 1))) >= 0)
10100 = simplify_gen_binary (ASHIFT, GET_MODE (varop),
10102 GEN_INT (exact_log2 (
10103 UINTVAL (XEXP (varop, 1)))));
10109 /* Similar, for when divides are cheaper. */
10110 if (CONST_INT_P (XEXP (varop, 1))
10111 && exact_log2 (UINTVAL (XEXP (varop, 1))) >= 0)
10114 = simplify_gen_binary (LSHIFTRT, GET_MODE (varop),
10116 GEN_INT (exact_log2 (
10117 UINTVAL (XEXP (varop, 1)))));
10123 /* If we are extracting just the sign bit of an arithmetic
10124 right shift, that shift is not needed. However, the sign
10125 bit of a wider mode may be different from what would be
10126 interpreted as the sign bit in a narrower mode, so, if
10127 the result is narrower, don't discard the shift. */
10128 if (code == LSHIFTRT
10129 && count == (GET_MODE_BITSIZE (result_mode) - 1)
10130 && (GET_MODE_BITSIZE (result_mode)
10131 >= GET_MODE_BITSIZE (GET_MODE (varop))))
10133 varop = XEXP (varop, 0);
10137 /* ... fall through ... */
10142 /* Here we have two nested shifts. The result is usually the
10143 AND of a new shift with a mask. We compute the result below. */
10144 if (CONST_INT_P (XEXP (varop, 1))
10145 && INTVAL (XEXP (varop, 1)) >= 0
10146 && INTVAL (XEXP (varop, 1)) < GET_MODE_PRECISION (GET_MODE (varop))
10147 && HWI_COMPUTABLE_MODE_P (result_mode)
10148 && HWI_COMPUTABLE_MODE_P (mode)
10149 && !VECTOR_MODE_P (result_mode))
10151 enum rtx_code first_code = GET_CODE (varop);
10152 unsigned int first_count = INTVAL (XEXP (varop, 1));
10153 unsigned HOST_WIDE_INT mask;
10156 /* We have one common special case. We can't do any merging if
10157 the inner code is an ASHIFTRT of a smaller mode. However, if
10158 we have (ashift:M1 (subreg:M1 (ashiftrt:M2 FOO C1) 0) C2)
10159 with C2 == GET_MODE_BITSIZE (M1) - GET_MODE_BITSIZE (M2),
10160 we can convert it to
10161 (ashiftrt:M1 (ashift:M1 (and:M1 (subreg:M1 FOO 0) C3) C2) C1).
10162 This simplifies certain SIGN_EXTEND operations. */
10163 if (code == ASHIFT && first_code == ASHIFTRT
10164 && count == (GET_MODE_PRECISION (result_mode)
10165 - GET_MODE_PRECISION (GET_MODE (varop))))
10167 /* C3 has the low-order C1 bits zero. */
10169 mask = GET_MODE_MASK (mode)
10170 & ~(((unsigned HOST_WIDE_INT) 1 << first_count) - 1);
10172 varop = simplify_and_const_int (NULL_RTX, result_mode,
10173 XEXP (varop, 0), mask);
10174 varop = simplify_shift_const (NULL_RTX, ASHIFT, result_mode,
10176 count = first_count;
10181 /* If this was (ashiftrt (ashift foo C1) C2) and FOO has more
10182 than C1 high-order bits equal to the sign bit, we can convert
10183 this to either an ASHIFT or an ASHIFTRT depending on the
10186 We cannot do this if VAROP's mode is not SHIFT_MODE. */
10188 if (code == ASHIFTRT && first_code == ASHIFT
10189 && GET_MODE (varop) == shift_mode
10190 && (num_sign_bit_copies (XEXP (varop, 0), shift_mode)
10193 varop = XEXP (varop, 0);
10194 count -= first_count;
10204 /* There are some cases we can't do. If CODE is ASHIFTRT,
10205 we can only do this if FIRST_CODE is also ASHIFTRT.
10207 We can't do the case when CODE is ROTATE and FIRST_CODE is
10210 If the mode of this shift is not the mode of the outer shift,
10211 we can't do this if either shift is a right shift or ROTATE.
10213 Finally, we can't do any of these if the mode is too wide
10214 unless the codes are the same.
10216 Handle the case where the shift codes are the same
10219 if (code == first_code)
10221 if (GET_MODE (varop) != result_mode
10222 && (code == ASHIFTRT || code == LSHIFTRT
10223 || code == ROTATE))
10226 count += first_count;
10227 varop = XEXP (varop, 0);
10231 if (code == ASHIFTRT
10232 || (code == ROTATE && first_code == ASHIFTRT)
10233 || GET_MODE_PRECISION (mode) > HOST_BITS_PER_WIDE_INT
10234 || (GET_MODE (varop) != result_mode
10235 && (first_code == ASHIFTRT || first_code == LSHIFTRT
10236 || first_code == ROTATE
10237 || code == ROTATE)))
10240 /* To compute the mask to apply after the shift, shift the
10241 nonzero bits of the inner shift the same way the
10242 outer shift will. */
10244 mask_rtx = GEN_INT (nonzero_bits (varop, GET_MODE (varop)));
10247 = simplify_const_binary_operation (code, result_mode, mask_rtx,
10250 /* Give up if we can't compute an outer operation to use. */
10252 || !CONST_INT_P (mask_rtx)
10253 || ! merge_outer_ops (&outer_op, &outer_const, AND,
10255 result_mode, &complement_p))
10258 /* If the shifts are in the same direction, we add the
10259 counts. Otherwise, we subtract them. */
10260 if ((code == ASHIFTRT || code == LSHIFTRT)
10261 == (first_code == ASHIFTRT || first_code == LSHIFTRT))
10262 count += first_count;
10264 count -= first_count;
10266 /* If COUNT is positive, the new shift is usually CODE,
10267 except for the two exceptions below, in which case it is
10268 FIRST_CODE. If the count is negative, FIRST_CODE should
10271 && ((first_code == ROTATE && code == ASHIFT)
10272 || (first_code == ASHIFTRT && code == LSHIFTRT)))
10274 else if (count < 0)
10275 code = first_code, count = -count;
10277 varop = XEXP (varop, 0);
10281 /* If we have (A << B << C) for any shift, we can convert this to
10282 (A << C << B). This wins if A is a constant. Only try this if
10283 B is not a constant. */
10285 else if (GET_CODE (varop) == code
10286 && CONST_INT_P (XEXP (varop, 0))
10287 && !CONST_INT_P (XEXP (varop, 1)))
10289 rtx new_rtx = simplify_const_binary_operation (code, mode,
10292 varop = gen_rtx_fmt_ee (code, mode, new_rtx, XEXP (varop, 1));
10299 if (VECTOR_MODE_P (mode))
10302 /* Make this fit the case below. */
10303 varop = gen_rtx_XOR (mode, XEXP (varop, 0), constm1_rtx);
10309 /* If we have (xshiftrt (ior (plus X (const_int -1)) X) C)
10310 with C the size of VAROP - 1 and the shift is logical if
10311 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
10312 we have an (le X 0) operation. If we have an arithmetic shift
10313 and STORE_FLAG_VALUE is 1 or we have a logical shift with
10314 STORE_FLAG_VALUE of -1, we have a (neg (le X 0)) operation. */
10316 if (GET_CODE (varop) == IOR && GET_CODE (XEXP (varop, 0)) == PLUS
10317 && XEXP (XEXP (varop, 0), 1) == constm1_rtx
10318 && (STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
10319 && (code == LSHIFTRT || code == ASHIFTRT)
10320 && count == (GET_MODE_PRECISION (GET_MODE (varop)) - 1)
10321 && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
10324 varop = gen_rtx_LE (GET_MODE (varop), XEXP (varop, 1),
10327 if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
10328 varop = gen_rtx_NEG (GET_MODE (varop), varop);
10333 /* If we have (shift (logical)), move the logical to the outside
10334 to allow it to possibly combine with another logical and the
10335 shift to combine with another shift. This also canonicalizes to
10336 what a ZERO_EXTRACT looks like. Also, some machines have
10337 (and (shift)) insns. */
10339 if (CONST_INT_P (XEXP (varop, 1))
10340 /* We can't do this if we have (ashiftrt (xor)) and the
10341 constant has its sign bit set in shift_mode. */
10342 && !(code == ASHIFTRT && GET_CODE (varop) == XOR
10343 && 0 > trunc_int_for_mode (INTVAL (XEXP (varop, 1)),
10345 && (new_rtx = simplify_const_binary_operation (code, result_mode,
10347 GEN_INT (count))) != 0
10348 && CONST_INT_P (new_rtx)
10349 && merge_outer_ops (&outer_op, &outer_const, GET_CODE (varop),
10350 INTVAL (new_rtx), result_mode, &complement_p))
10352 varop = XEXP (varop, 0);
10356 /* If we can't do that, try to simplify the shift in each arm of the
10357 logical expression, make a new logical expression, and apply
10358 the inverse distributive law. This also can't be done
10359 for some (ashiftrt (xor)). */
10360 if (CONST_INT_P (XEXP (varop, 1))
10361 && !(code == ASHIFTRT && GET_CODE (varop) == XOR
10362 && 0 > trunc_int_for_mode (INTVAL (XEXP (varop, 1)),
10365 rtx lhs = simplify_shift_const (NULL_RTX, code, shift_mode,
10366 XEXP (varop, 0), count);
10367 rtx rhs = simplify_shift_const (NULL_RTX, code, shift_mode,
10368 XEXP (varop, 1), count);
10370 varop = simplify_gen_binary (GET_CODE (varop), shift_mode,
10372 varop = apply_distributive_law (varop);
10380 /* Convert (lshiftrt (eq FOO 0) C) to (xor FOO 1) if STORE_FLAG_VALUE
10381 says that the sign bit can be tested, FOO has mode MODE, C is
10382 GET_MODE_PRECISION (MODE) - 1, and FOO has only its low-order bit
10383 that may be nonzero. */
10384 if (code == LSHIFTRT
10385 && XEXP (varop, 1) == const0_rtx
10386 && GET_MODE (XEXP (varop, 0)) == result_mode
10387 && count == (GET_MODE_PRECISION (result_mode) - 1)
10388 && HWI_COMPUTABLE_MODE_P (result_mode)
10389 && STORE_FLAG_VALUE == -1
10390 && nonzero_bits (XEXP (varop, 0), result_mode) == 1
10391 && merge_outer_ops (&outer_op, &outer_const, XOR, 1, result_mode,
10394 varop = XEXP (varop, 0);
10401 /* (lshiftrt (neg A) C) where A is either 0 or 1 and C is one less
10402 than the number of bits in the mode is equivalent to A. */
10403 if (code == LSHIFTRT
10404 && count == (GET_MODE_PRECISION (result_mode) - 1)
10405 && nonzero_bits (XEXP (varop, 0), result_mode) == 1)
10407 varop = XEXP (varop, 0);
10412 /* NEG commutes with ASHIFT since it is multiplication. Move the
10413 NEG outside to allow shifts to combine. */
10415 && merge_outer_ops (&outer_op, &outer_const, NEG, 0, result_mode,
10418 varop = XEXP (varop, 0);
10424 /* (lshiftrt (plus A -1) C) where A is either 0 or 1 and C
10425 is one less than the number of bits in the mode is
10426 equivalent to (xor A 1). */
10427 if (code == LSHIFTRT
10428 && count == (GET_MODE_PRECISION (result_mode) - 1)
10429 && XEXP (varop, 1) == constm1_rtx
10430 && nonzero_bits (XEXP (varop, 0), result_mode) == 1
10431 && merge_outer_ops (&outer_op, &outer_const, XOR, 1, result_mode,
10435 varop = XEXP (varop, 0);
10439 /* If we have (xshiftrt (plus FOO BAR) C), and the only bits
10440 that might be nonzero in BAR are those being shifted out and those
10441 bits are known zero in FOO, we can replace the PLUS with FOO.
10442 Similarly in the other operand order. This code occurs when
10443 we are computing the size of a variable-size array. */
10445 if ((code == ASHIFTRT || code == LSHIFTRT)
10446 && count < HOST_BITS_PER_WIDE_INT
10447 && nonzero_bits (XEXP (varop, 1), result_mode) >> count == 0
10448 && (nonzero_bits (XEXP (varop, 1), result_mode)
10449 & nonzero_bits (XEXP (varop, 0), result_mode)) == 0)
10451 varop = XEXP (varop, 0);
10454 else if ((code == ASHIFTRT || code == LSHIFTRT)
10455 && count < HOST_BITS_PER_WIDE_INT
10456 && HWI_COMPUTABLE_MODE_P (result_mode)
10457 && 0 == (nonzero_bits (XEXP (varop, 0), result_mode)
10459 && 0 == (nonzero_bits (XEXP (varop, 0), result_mode)
10460 & nonzero_bits (XEXP (varop, 1),
10463 varop = XEXP (varop, 1);
10467 /* (ashift (plus foo C) N) is (plus (ashift foo N) C'). */
10469 && CONST_INT_P (XEXP (varop, 1))
10470 && (new_rtx = simplify_const_binary_operation (ASHIFT, result_mode,
10472 GEN_INT (count))) != 0
10473 && CONST_INT_P (new_rtx)
10474 && merge_outer_ops (&outer_op, &outer_const, PLUS,
10475 INTVAL (new_rtx), result_mode, &complement_p))
10477 varop = XEXP (varop, 0);
10481 /* Check for 'PLUS signbit', which is the canonical form of 'XOR
10482 signbit', and attempt to change the PLUS to an XOR and move it to
10483 the outer operation as is done above in the AND/IOR/XOR case
10484 leg for shift(logical). See details in logical handling above
10485 for reasoning in doing so. */
10486 if (code == LSHIFTRT
10487 && CONST_INT_P (XEXP (varop, 1))
10488 && mode_signbit_p (result_mode, XEXP (varop, 1))
10489 && (new_rtx = simplify_const_binary_operation (code, result_mode,
10491 GEN_INT (count))) != 0
10492 && CONST_INT_P (new_rtx)
10493 && merge_outer_ops (&outer_op, &outer_const, XOR,
10494 INTVAL (new_rtx), result_mode, &complement_p))
10496 varop = XEXP (varop, 0);
10503 /* If we have (xshiftrt (minus (ashiftrt X C)) X) C)
10504 with C the size of VAROP - 1 and the shift is logical if
10505 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
10506 we have a (gt X 0) operation. If the shift is arithmetic with
10507 STORE_FLAG_VALUE of 1 or logical with STORE_FLAG_VALUE == -1,
10508 we have a (neg (gt X 0)) operation. */
10510 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
10511 && GET_CODE (XEXP (varop, 0)) == ASHIFTRT
10512 && count == (GET_MODE_PRECISION (GET_MODE (varop)) - 1)
10513 && (code == LSHIFTRT || code == ASHIFTRT)
10514 && CONST_INT_P (XEXP (XEXP (varop, 0), 1))
10515 && INTVAL (XEXP (XEXP (varop, 0), 1)) == count
10516 && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
10519 varop = gen_rtx_GT (GET_MODE (varop), XEXP (varop, 1),
10522 if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
10523 varop = gen_rtx_NEG (GET_MODE (varop), varop);
10530 /* Change (lshiftrt (truncate (lshiftrt))) to (truncate (lshiftrt))
10531 if the truncate does not affect the value. */
10532 if (code == LSHIFTRT
10533 && GET_CODE (XEXP (varop, 0)) == LSHIFTRT
10534 && CONST_INT_P (XEXP (XEXP (varop, 0), 1))
10535 && (INTVAL (XEXP (XEXP (varop, 0), 1))
10536 >= (GET_MODE_PRECISION (GET_MODE (XEXP (varop, 0)))
10537 - GET_MODE_PRECISION (GET_MODE (varop)))))
10539 rtx varop_inner = XEXP (varop, 0);
10542 = gen_rtx_LSHIFTRT (GET_MODE (varop_inner),
10543 XEXP (varop_inner, 0),
10545 (count + INTVAL (XEXP (varop_inner, 1))));
10546 varop = gen_rtx_TRUNCATE (GET_MODE (varop), varop_inner);
10559 shift_mode = try_widen_shift_mode (code, varop, count, result_mode, mode,
10560 outer_op, outer_const);
10562 /* We have now finished analyzing the shift. The result should be
10563 a shift of type CODE with SHIFT_MODE shifting VAROP COUNT places. If
10564 OUTER_OP is non-UNKNOWN, it is an operation that needs to be applied
10565 to the result of the shift. OUTER_CONST is the relevant constant,
10566 but we must turn off all bits turned off in the shift. */
10568 if (outer_op == UNKNOWN
10569 && orig_code == code && orig_count == count
10570 && varop == orig_varop
10571 && shift_mode == GET_MODE (varop))
10574 /* Make a SUBREG if necessary. If we can't make it, fail. */
10575 varop = gen_lowpart (shift_mode, varop);
10576 if (varop == NULL_RTX || GET_CODE (varop) == CLOBBER)
10579 /* If we have an outer operation and we just made a shift, it is
10580 possible that we could have simplified the shift were it not
10581 for the outer operation. So try to do the simplification
10584 if (outer_op != UNKNOWN)
10585 x = simplify_shift_const_1 (code, shift_mode, varop, count);
10590 x = simplify_gen_binary (code, shift_mode, varop, GEN_INT (count));
10592 /* If we were doing an LSHIFTRT in a wider mode than it was originally,
10593 turn off all the bits that the shift would have turned off. */
10594 if (orig_code == LSHIFTRT && result_mode != shift_mode)
10595 x = simplify_and_const_int (NULL_RTX, shift_mode, x,
10596 GET_MODE_MASK (result_mode) >> orig_count);
10598 /* Do the remainder of the processing in RESULT_MODE. */
10599 x = gen_lowpart_or_truncate (result_mode, x);
10601 /* If COMPLEMENT_P is set, we have to complement X before doing the outer
10604 x = simplify_gen_unary (NOT, result_mode, x, result_mode);
10606 if (outer_op != UNKNOWN)
10608 if (GET_RTX_CLASS (outer_op) != RTX_UNARY
10609 && GET_MODE_PRECISION (result_mode) < HOST_BITS_PER_WIDE_INT)
10610 outer_const = trunc_int_for_mode (outer_const, result_mode);
10612 if (outer_op == AND)
10613 x = simplify_and_const_int (NULL_RTX, result_mode, x, outer_const);
10614 else if (outer_op == SET)
10616 /* This means that we have determined that the result is
10617 equivalent to a constant. This should be rare. */
10618 if (!side_effects_p (x))
10619 x = GEN_INT (outer_const);
10621 else if (GET_RTX_CLASS (outer_op) == RTX_UNARY)
10622 x = simplify_gen_unary (outer_op, result_mode, x, result_mode);
10624 x = simplify_gen_binary (outer_op, result_mode, x,
10625 GEN_INT (outer_const));
10631 /* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift.
10632 The result of the shift is RESULT_MODE. If we cannot simplify it,
10633 return X or, if it is NULL, synthesize the expression with
10634 simplify_gen_binary. Otherwise, return a simplified value.
10636 The shift is normally computed in the widest mode we find in VAROP, as
10637 long as it isn't a different number of words than RESULT_MODE. Exceptions
10638 are ASHIFTRT and ROTATE, which are always done in their original mode. */
10641 simplify_shift_const (rtx x, enum rtx_code code, enum machine_mode result_mode,
10642 rtx varop, int count)
10644 rtx tem = simplify_shift_const_1 (code, result_mode, varop, count);
10649 x = simplify_gen_binary (code, GET_MODE (varop), varop, GEN_INT (count));
10650 if (GET_MODE (x) != result_mode)
10651 x = gen_lowpart (result_mode, x);
10656 /* Like recog, but we receive the address of a pointer to a new pattern.
10657 We try to match the rtx that the pointer points to.
10658 If that fails, we may try to modify or replace the pattern,
10659 storing the replacement into the same pointer object.
10661 Modifications include deletion or addition of CLOBBERs.
10663 PNOTES is a pointer to a location where any REG_UNUSED notes added for
10664 the CLOBBERs are placed.
10666 The value is the final insn code from the pattern ultimately matched,
10670 recog_for_combine (rtx *pnewpat, rtx insn, rtx *pnotes)
10672 rtx pat = *pnewpat;
10673 int insn_code_number;
10674 int num_clobbers_to_add = 0;
10677 rtx old_notes, old_pat;
10679 /* If PAT is a PARALLEL, check to see if it contains the CLOBBER
10680 we use to indicate that something didn't match. If we find such a
10681 thing, force rejection. */
10682 if (GET_CODE (pat) == PARALLEL)
10683 for (i = XVECLEN (pat, 0) - 1; i >= 0; i--)
10684 if (GET_CODE (XVECEXP (pat, 0, i)) == CLOBBER
10685 && XEXP (XVECEXP (pat, 0, i), 0) == const0_rtx)
10688 old_pat = PATTERN (insn);
10689 old_notes = REG_NOTES (insn);
10690 PATTERN (insn) = pat;
10691 REG_NOTES (insn) = 0;
10693 insn_code_number = recog (pat, insn, &num_clobbers_to_add);
10694 if (dump_file && (dump_flags & TDF_DETAILS))
10696 if (insn_code_number < 0)
10697 fputs ("Failed to match this instruction:\n", dump_file);
10699 fputs ("Successfully matched this instruction:\n", dump_file);
10700 print_rtl_single (dump_file, pat);
10703 /* If it isn't, there is the possibility that we previously had an insn
10704 that clobbered some register as a side effect, but the combined
10705 insn doesn't need to do that. So try once more without the clobbers
10706 unless this represents an ASM insn. */
10708 if (insn_code_number < 0 && ! check_asm_operands (pat)
10709 && GET_CODE (pat) == PARALLEL)
10713 for (pos = 0, i = 0; i < XVECLEN (pat, 0); i++)
10714 if (GET_CODE (XVECEXP (pat, 0, i)) != CLOBBER)
10717 SUBST (XVECEXP (pat, 0, pos), XVECEXP (pat, 0, i));
10721 SUBST_INT (XVECLEN (pat, 0), pos);
10724 pat = XVECEXP (pat, 0, 0);
10726 PATTERN (insn) = pat;
10727 insn_code_number = recog (pat, insn, &num_clobbers_to_add);
10728 if (dump_file && (dump_flags & TDF_DETAILS))
10730 if (insn_code_number < 0)
10731 fputs ("Failed to match this instruction:\n", dump_file);
10733 fputs ("Successfully matched this instruction:\n", dump_file);
10734 print_rtl_single (dump_file, pat);
10737 PATTERN (insn) = old_pat;
10738 REG_NOTES (insn) = old_notes;
10740 /* Recognize all noop sets, these will be killed by followup pass. */
10741 if (insn_code_number < 0 && GET_CODE (pat) == SET && set_noop_p (pat))
10742 insn_code_number = NOOP_MOVE_INSN_CODE, num_clobbers_to_add = 0;
10744 /* If we had any clobbers to add, make a new pattern than contains
10745 them. Then check to make sure that all of them are dead. */
10746 if (num_clobbers_to_add)
10748 rtx newpat = gen_rtx_PARALLEL (VOIDmode,
10749 rtvec_alloc (GET_CODE (pat) == PARALLEL
10750 ? (XVECLEN (pat, 0)
10751 + num_clobbers_to_add)
10752 : num_clobbers_to_add + 1));
10754 if (GET_CODE (pat) == PARALLEL)
10755 for (i = 0; i < XVECLEN (pat, 0); i++)
10756 XVECEXP (newpat, 0, i) = XVECEXP (pat, 0, i);
10758 XVECEXP (newpat, 0, 0) = pat;
10760 add_clobbers (newpat, insn_code_number);
10762 for (i = XVECLEN (newpat, 0) - num_clobbers_to_add;
10763 i < XVECLEN (newpat, 0); i++)
10765 if (REG_P (XEXP (XVECEXP (newpat, 0, i), 0))
10766 && ! reg_dead_at_p (XEXP (XVECEXP (newpat, 0, i), 0), insn))
10768 if (GET_CODE (XEXP (XVECEXP (newpat, 0, i), 0)) != SCRATCH)
10770 gcc_assert (REG_P (XEXP (XVECEXP (newpat, 0, i), 0)));
10771 notes = alloc_reg_note (REG_UNUSED,
10772 XEXP (XVECEXP (newpat, 0, i), 0), notes);
10781 return insn_code_number;
10784 /* Like gen_lowpart_general but for use by combine. In combine it
10785 is not possible to create any new pseudoregs. However, it is
10786 safe to create invalid memory addresses, because combine will
10787 try to recognize them and all they will do is make the combine
10790 If for some reason this cannot do its job, an rtx
10791 (clobber (const_int 0)) is returned.
10792 An insn containing that will not be recognized. */
10795 gen_lowpart_for_combine (enum machine_mode omode, rtx x)
10797 enum machine_mode imode = GET_MODE (x);
10798 unsigned int osize = GET_MODE_SIZE (omode);
10799 unsigned int isize = GET_MODE_SIZE (imode);
10802 if (omode == imode)
10805 /* Return identity if this is a CONST or symbolic reference. */
10807 && (GET_CODE (x) == CONST
10808 || GET_CODE (x) == SYMBOL_REF
10809 || GET_CODE (x) == LABEL_REF))
10812 /* We can only support MODE being wider than a word if X is a
10813 constant integer or has a mode the same size. */
10814 if (GET_MODE_SIZE (omode) > UNITS_PER_WORD
10815 && ! ((imode == VOIDmode
10816 && (CONST_INT_P (x)
10817 || GET_CODE (x) == CONST_DOUBLE))
10818 || isize == osize))
10821 /* X might be a paradoxical (subreg (mem)). In that case, gen_lowpart
10822 won't know what to do. So we will strip off the SUBREG here and
10823 process normally. */
10824 if (GET_CODE (x) == SUBREG && MEM_P (SUBREG_REG (x)))
10826 x = SUBREG_REG (x);
10828 /* For use in case we fall down into the address adjustments
10829 further below, we need to adjust the known mode and size of
10830 x; imode and isize, since we just adjusted x. */
10831 imode = GET_MODE (x);
10833 if (imode == omode)
10836 isize = GET_MODE_SIZE (imode);
10839 result = gen_lowpart_common (omode, x);
10848 /* Refuse to work on a volatile memory ref or one with a mode-dependent
10850 if (MEM_VOLATILE_P (x) || mode_dependent_address_p (XEXP (x, 0)))
10853 /* If we want to refer to something bigger than the original memref,
10854 generate a paradoxical subreg instead. That will force a reload
10855 of the original memref X. */
10857 return gen_rtx_SUBREG (omode, x, 0);
10859 if (WORDS_BIG_ENDIAN)
10860 offset = MAX (isize, UNITS_PER_WORD) - MAX (osize, UNITS_PER_WORD);
10862 /* Adjust the address so that the address-after-the-data is
10864 if (BYTES_BIG_ENDIAN)
10865 offset -= MIN (UNITS_PER_WORD, osize) - MIN (UNITS_PER_WORD, isize);
10867 return adjust_address_nv (x, omode, offset);
10870 /* If X is a comparison operator, rewrite it in a new mode. This
10871 probably won't match, but may allow further simplifications. */
10872 else if (COMPARISON_P (x))
10873 return gen_rtx_fmt_ee (GET_CODE (x), omode, XEXP (x, 0), XEXP (x, 1));
10875 /* If we couldn't simplify X any other way, just enclose it in a
10876 SUBREG. Normally, this SUBREG won't match, but some patterns may
10877 include an explicit SUBREG or we may simplify it further in combine. */
10883 offset = subreg_lowpart_offset (omode, imode);
10884 if (imode == VOIDmode)
10886 imode = int_mode_for_mode (omode);
10887 x = gen_lowpart_common (imode, x);
10891 res = simplify_gen_subreg (omode, x, imode, offset);
10897 return gen_rtx_CLOBBER (omode, const0_rtx);
10900 /* Try to simplify a comparison between OP0 and a constant OP1,
10901 where CODE is the comparison code that will be tested, into a
10902 (CODE OP0 const0_rtx) form.
10904 The result is a possibly different comparison code to use.
10905 *POP1 may be updated. */
10907 static enum rtx_code
10908 simplify_compare_const (enum rtx_code code, rtx op0, rtx *pop1)
10910 enum machine_mode mode = GET_MODE (op0);
10911 unsigned int mode_width = GET_MODE_PRECISION (mode);
10912 HOST_WIDE_INT const_op = INTVAL (*pop1);
10914 /* Get the constant we are comparing against and turn off all bits
10915 not on in our mode. */
10916 if (mode != VOIDmode)
10917 const_op = trunc_int_for_mode (const_op, mode);
10919 /* If we are comparing against a constant power of two and the value
10920 being compared can only have that single bit nonzero (e.g., it was
10921 `and'ed with that bit), we can replace this with a comparison
10924 && (code == EQ || code == NE || code == GE || code == GEU
10925 || code == LT || code == LTU)
10926 && mode_width <= HOST_BITS_PER_WIDE_INT
10927 && exact_log2 (const_op) >= 0
10928 && nonzero_bits (op0, mode) == (unsigned HOST_WIDE_INT) const_op)
10930 code = (code == EQ || code == GE || code == GEU ? NE : EQ);
10934 /* Similarly, if we are comparing a value known to be either -1 or
10935 0 with -1, change it to the opposite comparison against zero. */
10937 && (code == EQ || code == NE || code == GT || code == LE
10938 || code == GEU || code == LTU)
10939 && num_sign_bit_copies (op0, mode) == mode_width)
10941 code = (code == EQ || code == LE || code == GEU ? NE : EQ);
10945 /* Do some canonicalizations based on the comparison code. We prefer
10946 comparisons against zero and then prefer equality comparisons.
10947 If we can reduce the size of a constant, we will do that too. */
10951 /* < C is equivalent to <= (C - 1) */
10956 /* ... fall through to LE case below. */
10962 /* <= C is equivalent to < (C + 1); we do this for C < 0 */
10969 /* If we are doing a <= 0 comparison on a value known to have
10970 a zero sign bit, we can replace this with == 0. */
10971 else if (const_op == 0
10972 && mode_width <= HOST_BITS_PER_WIDE_INT
10973 && (nonzero_bits (op0, mode)
10974 & ((unsigned HOST_WIDE_INT) 1 << (mode_width - 1)))
10980 /* >= C is equivalent to > (C - 1). */
10985 /* ... fall through to GT below. */
10991 /* > C is equivalent to >= (C + 1); we do this for C < 0. */
10998 /* If we are doing a > 0 comparison on a value known to have
10999 a zero sign bit, we can replace this with != 0. */
11000 else if (const_op == 0
11001 && mode_width <= HOST_BITS_PER_WIDE_INT
11002 && (nonzero_bits (op0, mode)
11003 & ((unsigned HOST_WIDE_INT) 1 << (mode_width - 1)))
11009 /* < C is equivalent to <= (C - 1). */
11014 /* ... fall through ... */
11016 /* (unsigned) < 0x80000000 is equivalent to >= 0. */
11017 else if (mode_width <= HOST_BITS_PER_WIDE_INT
11018 && (unsigned HOST_WIDE_INT) const_op
11019 == (unsigned HOST_WIDE_INT) 1 << (mode_width - 1))
11029 /* unsigned <= 0 is equivalent to == 0 */
11032 /* (unsigned) <= 0x7fffffff is equivalent to >= 0. */
11033 else if (mode_width <= HOST_BITS_PER_WIDE_INT
11034 && (unsigned HOST_WIDE_INT) const_op
11035 == ((unsigned HOST_WIDE_INT) 1 << (mode_width - 1)) - 1)
11043 /* >= C is equivalent to > (C - 1). */
11048 /* ... fall through ... */
11051 /* (unsigned) >= 0x80000000 is equivalent to < 0. */
11052 else if (mode_width <= HOST_BITS_PER_WIDE_INT
11053 && (unsigned HOST_WIDE_INT) const_op
11054 == (unsigned HOST_WIDE_INT) 1 << (mode_width - 1))
11064 /* unsigned > 0 is equivalent to != 0 */
11067 /* (unsigned) > 0x7fffffff is equivalent to < 0. */
11068 else if (mode_width <= HOST_BITS_PER_WIDE_INT
11069 && (unsigned HOST_WIDE_INT) const_op
11070 == ((unsigned HOST_WIDE_INT) 1 << (mode_width - 1)) - 1)
11081 *pop1 = GEN_INT (const_op);
11085 /* Simplify a comparison between *POP0 and *POP1 where CODE is the
11086 comparison code that will be tested.
11088 The result is a possibly different comparison code to use. *POP0 and
11089 *POP1 may be updated.
11091 It is possible that we might detect that a comparison is either always
11092 true or always false. However, we do not perform general constant
11093 folding in combine, so this knowledge isn't useful. Such tautologies
11094 should have been detected earlier. Hence we ignore all such cases. */
11096 static enum rtx_code
11097 simplify_comparison (enum rtx_code code, rtx *pop0, rtx *pop1)
11103 enum machine_mode mode, tmode;
11105 /* Try a few ways of applying the same transformation to both operands. */
11108 #ifndef WORD_REGISTER_OPERATIONS
11109 /* The test below this one won't handle SIGN_EXTENDs on these machines,
11110 so check specially. */
11111 if (code != GTU && code != GEU && code != LTU && code != LEU
11112 && GET_CODE (op0) == ASHIFTRT && GET_CODE (op1) == ASHIFTRT
11113 && GET_CODE (XEXP (op0, 0)) == ASHIFT
11114 && GET_CODE (XEXP (op1, 0)) == ASHIFT
11115 && GET_CODE (XEXP (XEXP (op0, 0), 0)) == SUBREG
11116 && GET_CODE (XEXP (XEXP (op1, 0), 0)) == SUBREG
11117 && (GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0)))
11118 == GET_MODE (SUBREG_REG (XEXP (XEXP (op1, 0), 0))))
11119 && CONST_INT_P (XEXP (op0, 1))
11120 && XEXP (op0, 1) == XEXP (op1, 1)
11121 && XEXP (op0, 1) == XEXP (XEXP (op0, 0), 1)
11122 && XEXP (op0, 1) == XEXP (XEXP (op1, 0), 1)
11123 && (INTVAL (XEXP (op0, 1))
11124 == (GET_MODE_PRECISION (GET_MODE (op0))
11125 - (GET_MODE_PRECISION
11126 (GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0))))))))
11128 op0 = SUBREG_REG (XEXP (XEXP (op0, 0), 0));
11129 op1 = SUBREG_REG (XEXP (XEXP (op1, 0), 0));
11133 /* If both operands are the same constant shift, see if we can ignore the
11134 shift. We can if the shift is a rotate or if the bits shifted out of
11135 this shift are known to be zero for both inputs and if the type of
11136 comparison is compatible with the shift. */
11137 if (GET_CODE (op0) == GET_CODE (op1)
11138 && HWI_COMPUTABLE_MODE_P (GET_MODE(op0))
11139 && ((GET_CODE (op0) == ROTATE && (code == NE || code == EQ))
11140 || ((GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFT)
11141 && (code != GT && code != LT && code != GE && code != LE))
11142 || (GET_CODE (op0) == ASHIFTRT
11143 && (code != GTU && code != LTU
11144 && code != GEU && code != LEU)))
11145 && CONST_INT_P (XEXP (op0, 1))
11146 && INTVAL (XEXP (op0, 1)) >= 0
11147 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT
11148 && XEXP (op0, 1) == XEXP (op1, 1))
11150 enum machine_mode mode = GET_MODE (op0);
11151 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
11152 int shift_count = INTVAL (XEXP (op0, 1));
11154 if (GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFTRT)
11155 mask &= (mask >> shift_count) << shift_count;
11156 else if (GET_CODE (op0) == ASHIFT)
11157 mask = (mask & (mask << shift_count)) >> shift_count;
11159 if ((nonzero_bits (XEXP (op0, 0), mode) & ~mask) == 0
11160 && (nonzero_bits (XEXP (op1, 0), mode) & ~mask) == 0)
11161 op0 = XEXP (op0, 0), op1 = XEXP (op1, 0);
11166 /* If both operands are AND's of a paradoxical SUBREG by constant, the
11167 SUBREGs are of the same mode, and, in both cases, the AND would
11168 be redundant if the comparison was done in the narrower mode,
11169 do the comparison in the narrower mode (e.g., we are AND'ing with 1
11170 and the operand's possibly nonzero bits are 0xffffff01; in that case
11171 if we only care about QImode, we don't need the AND). This case
11172 occurs if the output mode of an scc insn is not SImode and
11173 STORE_FLAG_VALUE == 1 (e.g., the 386).
11175 Similarly, check for a case where the AND's are ZERO_EXTEND
11176 operations from some narrower mode even though a SUBREG is not
11179 else if (GET_CODE (op0) == AND && GET_CODE (op1) == AND
11180 && CONST_INT_P (XEXP (op0, 1))
11181 && CONST_INT_P (XEXP (op1, 1)))
11183 rtx inner_op0 = XEXP (op0, 0);
11184 rtx inner_op1 = XEXP (op1, 0);
11185 HOST_WIDE_INT c0 = INTVAL (XEXP (op0, 1));
11186 HOST_WIDE_INT c1 = INTVAL (XEXP (op1, 1));
11189 if (paradoxical_subreg_p (inner_op0)
11190 && GET_CODE (inner_op1) == SUBREG
11191 && (GET_MODE (SUBREG_REG (inner_op0))
11192 == GET_MODE (SUBREG_REG (inner_op1)))
11193 && (GET_MODE_PRECISION (GET_MODE (SUBREG_REG (inner_op0)))
11194 <= HOST_BITS_PER_WIDE_INT)
11195 && (0 == ((~c0) & nonzero_bits (SUBREG_REG (inner_op0),
11196 GET_MODE (SUBREG_REG (inner_op0)))))
11197 && (0 == ((~c1) & nonzero_bits (SUBREG_REG (inner_op1),
11198 GET_MODE (SUBREG_REG (inner_op1))))))
11200 op0 = SUBREG_REG (inner_op0);
11201 op1 = SUBREG_REG (inner_op1);
11203 /* The resulting comparison is always unsigned since we masked
11204 off the original sign bit. */
11205 code = unsigned_condition (code);
11211 for (tmode = GET_CLASS_NARROWEST_MODE
11212 (GET_MODE_CLASS (GET_MODE (op0)));
11213 tmode != GET_MODE (op0); tmode = GET_MODE_WIDER_MODE (tmode))
11214 if ((unsigned HOST_WIDE_INT) c0 == GET_MODE_MASK (tmode))
11216 op0 = gen_lowpart (tmode, inner_op0);
11217 op1 = gen_lowpart (tmode, inner_op1);
11218 code = unsigned_condition (code);
11227 /* If both operands are NOT, we can strip off the outer operation
11228 and adjust the comparison code for swapped operands; similarly for
11229 NEG, except that this must be an equality comparison. */
11230 else if ((GET_CODE (op0) == NOT && GET_CODE (op1) == NOT)
11231 || (GET_CODE (op0) == NEG && GET_CODE (op1) == NEG
11232 && (code == EQ || code == NE)))
11233 op0 = XEXP (op0, 0), op1 = XEXP (op1, 0), code = swap_condition (code);
11239 /* If the first operand is a constant, swap the operands and adjust the
11240 comparison code appropriately, but don't do this if the second operand
11241 is already a constant integer. */
11242 if (swap_commutative_operands_p (op0, op1))
11244 tem = op0, op0 = op1, op1 = tem;
11245 code = swap_condition (code);
11248 /* We now enter a loop during which we will try to simplify the comparison.
11249 For the most part, we only are concerned with comparisons with zero,
11250 but some things may really be comparisons with zero but not start
11251 out looking that way. */
11253 while (CONST_INT_P (op1))
11255 enum machine_mode mode = GET_MODE (op0);
11256 unsigned int mode_width = GET_MODE_PRECISION (mode);
11257 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
11258 int equality_comparison_p;
11259 int sign_bit_comparison_p;
11260 int unsigned_comparison_p;
11261 HOST_WIDE_INT const_op;
11263 /* We only want to handle integral modes. This catches VOIDmode,
11264 CCmode, and the floating-point modes. An exception is that we
11265 can handle VOIDmode if OP0 is a COMPARE or a comparison
11268 if (GET_MODE_CLASS (mode) != MODE_INT
11269 && ! (mode == VOIDmode
11270 && (GET_CODE (op0) == COMPARE || COMPARISON_P (op0))))
11273 /* Try to simplify the compare to constant, possibly changing the
11274 comparison op, and/or changing op1 to zero. */
11275 code = simplify_compare_const (code, op0, &op1);
11276 const_op = INTVAL (op1);
11278 /* Compute some predicates to simplify code below. */
11280 equality_comparison_p = (code == EQ || code == NE);
11281 sign_bit_comparison_p = ((code == LT || code == GE) && const_op == 0);
11282 unsigned_comparison_p = (code == LTU || code == LEU || code == GTU
11285 /* If this is a sign bit comparison and we can do arithmetic in
11286 MODE, say that we will only be needing the sign bit of OP0. */
11287 if (sign_bit_comparison_p && HWI_COMPUTABLE_MODE_P (mode))
11288 op0 = force_to_mode (op0, mode,
11289 (unsigned HOST_WIDE_INT) 1
11290 << (GET_MODE_PRECISION (mode) - 1),
11293 /* Now try cases based on the opcode of OP0. If none of the cases
11294 does a "continue", we exit this loop immediately after the
11297 switch (GET_CODE (op0))
11300 /* If we are extracting a single bit from a variable position in
11301 a constant that has only a single bit set and are comparing it
11302 with zero, we can convert this into an equality comparison
11303 between the position and the location of the single bit. */
11304 /* Except we can't if SHIFT_COUNT_TRUNCATED is set, since we might
11305 have already reduced the shift count modulo the word size. */
11306 if (!SHIFT_COUNT_TRUNCATED
11307 && CONST_INT_P (XEXP (op0, 0))
11308 && XEXP (op0, 1) == const1_rtx
11309 && equality_comparison_p && const_op == 0
11310 && (i = exact_log2 (UINTVAL (XEXP (op0, 0)))) >= 0)
11312 if (BITS_BIG_ENDIAN)
11314 enum machine_mode new_mode
11315 = mode_for_extraction (EP_extzv, 1);
11316 if (new_mode == MAX_MACHINE_MODE)
11317 i = BITS_PER_WORD - 1 - i;
11321 i = (GET_MODE_PRECISION (mode) - 1 - i);
11325 op0 = XEXP (op0, 2);
11329 /* Result is nonzero iff shift count is equal to I. */
11330 code = reverse_condition (code);
11334 /* ... fall through ... */
11337 tem = expand_compound_operation (op0);
11346 /* If testing for equality, we can take the NOT of the constant. */
11347 if (equality_comparison_p
11348 && (tem = simplify_unary_operation (NOT, mode, op1, mode)) != 0)
11350 op0 = XEXP (op0, 0);
11355 /* If just looking at the sign bit, reverse the sense of the
11357 if (sign_bit_comparison_p)
11359 op0 = XEXP (op0, 0);
11360 code = (code == GE ? LT : GE);
11366 /* If testing for equality, we can take the NEG of the constant. */
11367 if (equality_comparison_p
11368 && (tem = simplify_unary_operation (NEG, mode, op1, mode)) != 0)
11370 op0 = XEXP (op0, 0);
11375 /* The remaining cases only apply to comparisons with zero. */
11379 /* When X is ABS or is known positive,
11380 (neg X) is < 0 if and only if X != 0. */
11382 if (sign_bit_comparison_p
11383 && (GET_CODE (XEXP (op0, 0)) == ABS
11384 || (mode_width <= HOST_BITS_PER_WIDE_INT
11385 && (nonzero_bits (XEXP (op0, 0), mode)
11386 & ((unsigned HOST_WIDE_INT) 1 << (mode_width - 1)))
11389 op0 = XEXP (op0, 0);
11390 code = (code == LT ? NE : EQ);
11394 /* If we have NEG of something whose two high-order bits are the
11395 same, we know that "(-a) < 0" is equivalent to "a > 0". */
11396 if (num_sign_bit_copies (op0, mode) >= 2)
11398 op0 = XEXP (op0, 0);
11399 code = swap_condition (code);
11405 /* If we are testing equality and our count is a constant, we
11406 can perform the inverse operation on our RHS. */
11407 if (equality_comparison_p && CONST_INT_P (XEXP (op0, 1))
11408 && (tem = simplify_binary_operation (ROTATERT, mode,
11409 op1, XEXP (op0, 1))) != 0)
11411 op0 = XEXP (op0, 0);
11416 /* If we are doing a < 0 or >= 0 comparison, it means we are testing
11417 a particular bit. Convert it to an AND of a constant of that
11418 bit. This will be converted into a ZERO_EXTRACT. */
11419 if (const_op == 0 && sign_bit_comparison_p
11420 && CONST_INT_P (XEXP (op0, 1))
11421 && mode_width <= HOST_BITS_PER_WIDE_INT)
11423 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
11424 ((unsigned HOST_WIDE_INT) 1
11426 - INTVAL (XEXP (op0, 1)))));
11427 code = (code == LT ? NE : EQ);
11431 /* Fall through. */
11434 /* ABS is ignorable inside an equality comparison with zero. */
11435 if (const_op == 0 && equality_comparison_p)
11437 op0 = XEXP (op0, 0);
11443 /* Can simplify (compare (zero/sign_extend FOO) CONST) to
11444 (compare FOO CONST) if CONST fits in FOO's mode and we
11445 are either testing inequality or have an unsigned
11446 comparison with ZERO_EXTEND or a signed comparison with
11447 SIGN_EXTEND. But don't do it if we don't have a compare
11448 insn of the given mode, since we'd have to revert it
11449 later on, and then we wouldn't know whether to sign- or
11451 mode = GET_MODE (XEXP (op0, 0));
11452 if (GET_MODE_CLASS (mode) == MODE_INT
11453 && ! unsigned_comparison_p
11454 && HWI_COMPUTABLE_MODE_P (mode)
11455 && trunc_int_for_mode (const_op, mode) == const_op
11456 && have_insn_for (COMPARE, mode))
11458 op0 = XEXP (op0, 0);
11464 /* Check for the case where we are comparing A - C1 with C2, that is
11466 (subreg:MODE (plus (A) (-C1))) op (C2)
11468 with C1 a constant, and try to lift the SUBREG, i.e. to do the
11469 comparison in the wider mode. One of the following two conditions
11470 must be true in order for this to be valid:
11472 1. The mode extension results in the same bit pattern being added
11473 on both sides and the comparison is equality or unsigned. As
11474 C2 has been truncated to fit in MODE, the pattern can only be
11477 2. The mode extension results in the sign bit being copied on
11480 The difficulty here is that we have predicates for A but not for
11481 (A - C1) so we need to check that C1 is within proper bounds so
11482 as to perturbate A as little as possible. */
11484 if (mode_width <= HOST_BITS_PER_WIDE_INT
11485 && subreg_lowpart_p (op0)
11486 && GET_MODE_PRECISION (GET_MODE (SUBREG_REG (op0))) > mode_width
11487 && GET_CODE (SUBREG_REG (op0)) == PLUS
11488 && CONST_INT_P (XEXP (SUBREG_REG (op0), 1)))
11490 enum machine_mode inner_mode = GET_MODE (SUBREG_REG (op0));
11491 rtx a = XEXP (SUBREG_REG (op0), 0);
11492 HOST_WIDE_INT c1 = -INTVAL (XEXP (SUBREG_REG (op0), 1));
11495 && (unsigned HOST_WIDE_INT) c1
11496 < (unsigned HOST_WIDE_INT) 1 << (mode_width - 1)
11497 && (equality_comparison_p || unsigned_comparison_p)
11498 /* (A - C1) zero-extends if it is positive and sign-extends
11499 if it is negative, C2 both zero- and sign-extends. */
11500 && ((0 == (nonzero_bits (a, inner_mode)
11501 & ~GET_MODE_MASK (mode))
11503 /* (A - C1) sign-extends if it is positive and 1-extends
11504 if it is negative, C2 both sign- and 1-extends. */
11505 || (num_sign_bit_copies (a, inner_mode)
11506 > (unsigned int) (GET_MODE_PRECISION (inner_mode)
11509 || ((unsigned HOST_WIDE_INT) c1
11510 < (unsigned HOST_WIDE_INT) 1 << (mode_width - 2)
11511 /* (A - C1) always sign-extends, like C2. */
11512 && num_sign_bit_copies (a, inner_mode)
11513 > (unsigned int) (GET_MODE_PRECISION (inner_mode)
11514 - (mode_width - 1))))
11516 op0 = SUBREG_REG (op0);
11521 /* If the inner mode is narrower and we are extracting the low part,
11522 we can treat the SUBREG as if it were a ZERO_EXTEND. */
11523 if (subreg_lowpart_p (op0)
11524 && GET_MODE_PRECISION (GET_MODE (SUBREG_REG (op0))) < mode_width)
11525 /* Fall through */ ;
11529 /* ... fall through ... */
11532 mode = GET_MODE (XEXP (op0, 0));
11533 if (GET_MODE_CLASS (mode) == MODE_INT
11534 && (unsigned_comparison_p || equality_comparison_p)
11535 && HWI_COMPUTABLE_MODE_P (mode)
11536 && (unsigned HOST_WIDE_INT) const_op <= GET_MODE_MASK (mode)
11538 && have_insn_for (COMPARE, mode))
11540 op0 = XEXP (op0, 0);
11546 /* (eq (plus X A) B) -> (eq X (minus B A)). We can only do
11547 this for equality comparisons due to pathological cases involving
11549 if (equality_comparison_p
11550 && 0 != (tem = simplify_binary_operation (MINUS, mode,
11551 op1, XEXP (op0, 1))))
11553 op0 = XEXP (op0, 0);
11558 /* (plus (abs X) (const_int -1)) is < 0 if and only if X == 0. */
11559 if (const_op == 0 && XEXP (op0, 1) == constm1_rtx
11560 && GET_CODE (XEXP (op0, 0)) == ABS && sign_bit_comparison_p)
11562 op0 = XEXP (XEXP (op0, 0), 0);
11563 code = (code == LT ? EQ : NE);
11569 /* We used to optimize signed comparisons against zero, but that
11570 was incorrect. Unsigned comparisons against zero (GTU, LEU)
11571 arrive here as equality comparisons, or (GEU, LTU) are
11572 optimized away. No need to special-case them. */
11574 /* (eq (minus A B) C) -> (eq A (plus B C)) or
11575 (eq B (minus A C)), whichever simplifies. We can only do
11576 this for equality comparisons due to pathological cases involving
11578 if (equality_comparison_p
11579 && 0 != (tem = simplify_binary_operation (PLUS, mode,
11580 XEXP (op0, 1), op1)))
11582 op0 = XEXP (op0, 0);
11587 if (equality_comparison_p
11588 && 0 != (tem = simplify_binary_operation (MINUS, mode,
11589 XEXP (op0, 0), op1)))
11591 op0 = XEXP (op0, 1);
11596 /* The sign bit of (minus (ashiftrt X C) X), where C is the number
11597 of bits in X minus 1, is one iff X > 0. */
11598 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == ASHIFTRT
11599 && CONST_INT_P (XEXP (XEXP (op0, 0), 1))
11600 && UINTVAL (XEXP (XEXP (op0, 0), 1)) == mode_width - 1
11601 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
11603 op0 = XEXP (op0, 1);
11604 code = (code == GE ? LE : GT);
11610 /* (eq (xor A B) C) -> (eq A (xor B C)). This is a simplification
11611 if C is zero or B is a constant. */
11612 if (equality_comparison_p
11613 && 0 != (tem = simplify_binary_operation (XOR, mode,
11614 XEXP (op0, 1), op1)))
11616 op0 = XEXP (op0, 0);
11623 case UNEQ: case LTGT:
11624 case LT: case LTU: case UNLT: case LE: case LEU: case UNLE:
11625 case GT: case GTU: case UNGT: case GE: case GEU: case UNGE:
11626 case UNORDERED: case ORDERED:
11627 /* We can't do anything if OP0 is a condition code value, rather
11628 than an actual data value. */
11630 || CC0_P (XEXP (op0, 0))
11631 || GET_MODE_CLASS (GET_MODE (XEXP (op0, 0))) == MODE_CC)
11634 /* Get the two operands being compared. */
11635 if (GET_CODE (XEXP (op0, 0)) == COMPARE)
11636 tem = XEXP (XEXP (op0, 0), 0), tem1 = XEXP (XEXP (op0, 0), 1);
11638 tem = XEXP (op0, 0), tem1 = XEXP (op0, 1);
11640 /* Check for the cases where we simply want the result of the
11641 earlier test or the opposite of that result. */
11642 if (code == NE || code == EQ
11643 || (val_signbit_known_set_p (GET_MODE (op0), STORE_FLAG_VALUE)
11644 && (code == LT || code == GE)))
11646 enum rtx_code new_code;
11647 if (code == LT || code == NE)
11648 new_code = GET_CODE (op0);
11650 new_code = reversed_comparison_code (op0, NULL);
11652 if (new_code != UNKNOWN)
11663 /* The sign bit of (ior (plus X (const_int -1)) X) is nonzero
11665 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == PLUS
11666 && XEXP (XEXP (op0, 0), 1) == constm1_rtx
11667 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
11669 op0 = XEXP (op0, 1);
11670 code = (code == GE ? GT : LE);
11676 /* Convert (and (xshift 1 X) Y) to (and (lshiftrt Y X) 1). This
11677 will be converted to a ZERO_EXTRACT later. */
11678 if (const_op == 0 && equality_comparison_p
11679 && GET_CODE (XEXP (op0, 0)) == ASHIFT
11680 && XEXP (XEXP (op0, 0), 0) == const1_rtx)
11682 op0 = gen_rtx_LSHIFTRT (mode, XEXP (op0, 1),
11683 XEXP (XEXP (op0, 0), 1));
11684 op0 = simplify_and_const_int (NULL_RTX, mode, op0, 1);
11688 /* If we are comparing (and (lshiftrt X C1) C2) for equality with
11689 zero and X is a comparison and C1 and C2 describe only bits set
11690 in STORE_FLAG_VALUE, we can compare with X. */
11691 if (const_op == 0 && equality_comparison_p
11692 && mode_width <= HOST_BITS_PER_WIDE_INT
11693 && CONST_INT_P (XEXP (op0, 1))
11694 && GET_CODE (XEXP (op0, 0)) == LSHIFTRT
11695 && CONST_INT_P (XEXP (XEXP (op0, 0), 1))
11696 && INTVAL (XEXP (XEXP (op0, 0), 1)) >= 0
11697 && INTVAL (XEXP (XEXP (op0, 0), 1)) < HOST_BITS_PER_WIDE_INT)
11699 mask = ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
11700 << INTVAL (XEXP (XEXP (op0, 0), 1)));
11701 if ((~STORE_FLAG_VALUE & mask) == 0
11702 && (COMPARISON_P (XEXP (XEXP (op0, 0), 0))
11703 || ((tem = get_last_value (XEXP (XEXP (op0, 0), 0))) != 0
11704 && COMPARISON_P (tem))))
11706 op0 = XEXP (XEXP (op0, 0), 0);
11711 /* If we are doing an equality comparison of an AND of a bit equal
11712 to the sign bit, replace this with a LT or GE comparison of
11713 the underlying value. */
11714 if (equality_comparison_p
11716 && CONST_INT_P (XEXP (op0, 1))
11717 && mode_width <= HOST_BITS_PER_WIDE_INT
11718 && ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
11719 == (unsigned HOST_WIDE_INT) 1 << (mode_width - 1)))
11721 op0 = XEXP (op0, 0);
11722 code = (code == EQ ? GE : LT);
11726 /* If this AND operation is really a ZERO_EXTEND from a narrower
11727 mode, the constant fits within that mode, and this is either an
11728 equality or unsigned comparison, try to do this comparison in
11733 (ne:DI (and:DI (reg:DI 4) (const_int 0xffffffff)) (const_int 0))
11734 -> (ne:DI (reg:SI 4) (const_int 0))
11736 unless TRULY_NOOP_TRUNCATION allows it or the register is
11737 known to hold a value of the required mode the
11738 transformation is invalid. */
11739 if ((equality_comparison_p || unsigned_comparison_p)
11740 && CONST_INT_P (XEXP (op0, 1))
11741 && (i = exact_log2 ((UINTVAL (XEXP (op0, 1))
11742 & GET_MODE_MASK (mode))
11744 && const_op >> i == 0
11745 && (tmode = mode_for_size (i, MODE_INT, 1)) != BLKmode
11746 && (TRULY_NOOP_TRUNCATION_MODES_P (tmode, GET_MODE (op0))
11747 || (REG_P (XEXP (op0, 0))
11748 && reg_truncated_to_mode (tmode, XEXP (op0, 0)))))
11750 op0 = gen_lowpart (tmode, XEXP (op0, 0));
11754 /* If this is (and:M1 (subreg:M2 X 0) (const_int C1)) where C1
11755 fits in both M1 and M2 and the SUBREG is either paradoxical
11756 or represents the low part, permute the SUBREG and the AND
11758 if (GET_CODE (XEXP (op0, 0)) == SUBREG)
11760 unsigned HOST_WIDE_INT c1;
11761 tmode = GET_MODE (SUBREG_REG (XEXP (op0, 0)));
11762 /* Require an integral mode, to avoid creating something like
11764 if (SCALAR_INT_MODE_P (tmode)
11765 /* It is unsafe to commute the AND into the SUBREG if the
11766 SUBREG is paradoxical and WORD_REGISTER_OPERATIONS is
11767 not defined. As originally written the upper bits
11768 have a defined value due to the AND operation.
11769 However, if we commute the AND inside the SUBREG then
11770 they no longer have defined values and the meaning of
11771 the code has been changed. */
11773 #ifdef WORD_REGISTER_OPERATIONS
11774 || (mode_width > GET_MODE_PRECISION (tmode)
11775 && mode_width <= BITS_PER_WORD)
11777 || (mode_width <= GET_MODE_PRECISION (tmode)
11778 && subreg_lowpart_p (XEXP (op0, 0))))
11779 && CONST_INT_P (XEXP (op0, 1))
11780 && mode_width <= HOST_BITS_PER_WIDE_INT
11781 && HWI_COMPUTABLE_MODE_P (tmode)
11782 && ((c1 = INTVAL (XEXP (op0, 1))) & ~mask) == 0
11783 && (c1 & ~GET_MODE_MASK (tmode)) == 0
11785 && c1 != GET_MODE_MASK (tmode))
11787 op0 = simplify_gen_binary (AND, tmode,
11788 SUBREG_REG (XEXP (op0, 0)),
11789 gen_int_mode (c1, tmode));
11790 op0 = gen_lowpart (mode, op0);
11795 /* Convert (ne (and (not X) 1) 0) to (eq (and X 1) 0). */
11796 if (const_op == 0 && equality_comparison_p
11797 && XEXP (op0, 1) == const1_rtx
11798 && GET_CODE (XEXP (op0, 0)) == NOT)
11800 op0 = simplify_and_const_int (NULL_RTX, mode,
11801 XEXP (XEXP (op0, 0), 0), 1);
11802 code = (code == NE ? EQ : NE);
11806 /* Convert (ne (and (lshiftrt (not X)) 1) 0) to
11807 (eq (and (lshiftrt X) 1) 0).
11808 Also handle the case where (not X) is expressed using xor. */
11809 if (const_op == 0 && equality_comparison_p
11810 && XEXP (op0, 1) == const1_rtx
11811 && GET_CODE (XEXP (op0, 0)) == LSHIFTRT)
11813 rtx shift_op = XEXP (XEXP (op0, 0), 0);
11814 rtx shift_count = XEXP (XEXP (op0, 0), 1);
11816 if (GET_CODE (shift_op) == NOT
11817 || (GET_CODE (shift_op) == XOR
11818 && CONST_INT_P (XEXP (shift_op, 1))
11819 && CONST_INT_P (shift_count)
11820 && HWI_COMPUTABLE_MODE_P (mode)
11821 && (UINTVAL (XEXP (shift_op, 1))
11822 == (unsigned HOST_WIDE_INT) 1
11823 << INTVAL (shift_count))))
11826 = gen_rtx_LSHIFTRT (mode, XEXP (shift_op, 0), shift_count);
11827 op0 = simplify_and_const_int (NULL_RTX, mode, op0, 1);
11828 code = (code == NE ? EQ : NE);
11835 /* If we have (compare (ashift FOO N) (const_int C)) and
11836 the high order N bits of FOO (N+1 if an inequality comparison)
11837 are known to be zero, we can do this by comparing FOO with C
11838 shifted right N bits so long as the low-order N bits of C are
11840 if (CONST_INT_P (XEXP (op0, 1))
11841 && INTVAL (XEXP (op0, 1)) >= 0
11842 && ((INTVAL (XEXP (op0, 1)) + ! equality_comparison_p)
11843 < HOST_BITS_PER_WIDE_INT)
11844 && (((unsigned HOST_WIDE_INT) const_op
11845 & (((unsigned HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1)))
11847 && mode_width <= HOST_BITS_PER_WIDE_INT
11848 && (nonzero_bits (XEXP (op0, 0), mode)
11849 & ~(mask >> (INTVAL (XEXP (op0, 1))
11850 + ! equality_comparison_p))) == 0)
11852 /* We must perform a logical shift, not an arithmetic one,
11853 as we want the top N bits of C to be zero. */
11854 unsigned HOST_WIDE_INT temp = const_op & GET_MODE_MASK (mode);
11856 temp >>= INTVAL (XEXP (op0, 1));
11857 op1 = gen_int_mode (temp, mode);
11858 op0 = XEXP (op0, 0);
11862 /* If we are doing a sign bit comparison, it means we are testing
11863 a particular bit. Convert it to the appropriate AND. */
11864 if (sign_bit_comparison_p && CONST_INT_P (XEXP (op0, 1))
11865 && mode_width <= HOST_BITS_PER_WIDE_INT)
11867 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
11868 ((unsigned HOST_WIDE_INT) 1
11870 - INTVAL (XEXP (op0, 1)))));
11871 code = (code == LT ? NE : EQ);
11875 /* If this an equality comparison with zero and we are shifting
11876 the low bit to the sign bit, we can convert this to an AND of the
11878 if (const_op == 0 && equality_comparison_p
11879 && CONST_INT_P (XEXP (op0, 1))
11880 && UINTVAL (XEXP (op0, 1)) == mode_width - 1)
11882 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0), 1);
11888 /* If this is an equality comparison with zero, we can do this
11889 as a logical shift, which might be much simpler. */
11890 if (equality_comparison_p && const_op == 0
11891 && CONST_INT_P (XEXP (op0, 1)))
11893 op0 = simplify_shift_const (NULL_RTX, LSHIFTRT, mode,
11895 INTVAL (XEXP (op0, 1)));
11899 /* If OP0 is a sign extension and CODE is not an unsigned comparison,
11900 do the comparison in a narrower mode. */
11901 if (! unsigned_comparison_p
11902 && CONST_INT_P (XEXP (op0, 1))
11903 && GET_CODE (XEXP (op0, 0)) == ASHIFT
11904 && XEXP (op0, 1) == XEXP (XEXP (op0, 0), 1)
11905 && (tmode = mode_for_size (mode_width - INTVAL (XEXP (op0, 1)),
11906 MODE_INT, 1)) != BLKmode
11907 && (((unsigned HOST_WIDE_INT) const_op
11908 + (GET_MODE_MASK (tmode) >> 1) + 1)
11909 <= GET_MODE_MASK (tmode)))
11911 op0 = gen_lowpart (tmode, XEXP (XEXP (op0, 0), 0));
11915 /* Likewise if OP0 is a PLUS of a sign extension with a
11916 constant, which is usually represented with the PLUS
11917 between the shifts. */
11918 if (! unsigned_comparison_p
11919 && CONST_INT_P (XEXP (op0, 1))
11920 && GET_CODE (XEXP (op0, 0)) == PLUS
11921 && CONST_INT_P (XEXP (XEXP (op0, 0), 1))
11922 && GET_CODE (XEXP (XEXP (op0, 0), 0)) == ASHIFT
11923 && XEXP (op0, 1) == XEXP (XEXP (XEXP (op0, 0), 0), 1)
11924 && (tmode = mode_for_size (mode_width - INTVAL (XEXP (op0, 1)),
11925 MODE_INT, 1)) != BLKmode
11926 && (((unsigned HOST_WIDE_INT) const_op
11927 + (GET_MODE_MASK (tmode) >> 1) + 1)
11928 <= GET_MODE_MASK (tmode)))
11930 rtx inner = XEXP (XEXP (XEXP (op0, 0), 0), 0);
11931 rtx add_const = XEXP (XEXP (op0, 0), 1);
11932 rtx new_const = simplify_gen_binary (ASHIFTRT, GET_MODE (op0),
11933 add_const, XEXP (op0, 1));
11935 op0 = simplify_gen_binary (PLUS, tmode,
11936 gen_lowpart (tmode, inner),
11941 /* ... fall through ... */
11943 /* If we have (compare (xshiftrt FOO N) (const_int C)) and
11944 the low order N bits of FOO are known to be zero, we can do this
11945 by comparing FOO with C shifted left N bits so long as no
11946 overflow occurs. Even if the low order N bits of FOO aren't known
11947 to be zero, if the comparison is >= or < we can use the same
11948 optimization and for > or <= by setting all the low
11949 order N bits in the comparison constant. */
11950 if (CONST_INT_P (XEXP (op0, 1))
11951 && INTVAL (XEXP (op0, 1)) > 0
11952 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT
11953 && mode_width <= HOST_BITS_PER_WIDE_INT
11954 && (((unsigned HOST_WIDE_INT) const_op
11955 + (GET_CODE (op0) != LSHIFTRT
11956 ? ((GET_MODE_MASK (mode) >> INTVAL (XEXP (op0, 1)) >> 1)
11959 <= GET_MODE_MASK (mode) >> INTVAL (XEXP (op0, 1))))
11961 unsigned HOST_WIDE_INT low_bits
11962 = (nonzero_bits (XEXP (op0, 0), mode)
11963 & (((unsigned HOST_WIDE_INT) 1
11964 << INTVAL (XEXP (op0, 1))) - 1));
11965 if (low_bits == 0 || !equality_comparison_p)
11967 /* If the shift was logical, then we must make the condition
11969 if (GET_CODE (op0) == LSHIFTRT)
11970 code = unsigned_condition (code);
11972 const_op <<= INTVAL (XEXP (op0, 1));
11974 && (code == GT || code == GTU
11975 || code == LE || code == LEU))
11977 |= (((HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1))) - 1);
11978 op1 = GEN_INT (const_op);
11979 op0 = XEXP (op0, 0);
11984 /* If we are using this shift to extract just the sign bit, we
11985 can replace this with an LT or GE comparison. */
11987 && (equality_comparison_p || sign_bit_comparison_p)
11988 && CONST_INT_P (XEXP (op0, 1))
11989 && UINTVAL (XEXP (op0, 1)) == mode_width - 1)
11991 op0 = XEXP (op0, 0);
11992 code = (code == NE || code == GT ? LT : GE);
12004 /* Now make any compound operations involved in this comparison. Then,
12005 check for an outmost SUBREG on OP0 that is not doing anything or is
12006 paradoxical. The latter transformation must only be performed when
12007 it is known that the "extra" bits will be the same in op0 and op1 or
12008 that they don't matter. There are three cases to consider:
12010 1. SUBREG_REG (op0) is a register. In this case the bits are don't
12011 care bits and we can assume they have any convenient value. So
12012 making the transformation is safe.
12014 2. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is not defined.
12015 In this case the upper bits of op0 are undefined. We should not make
12016 the simplification in that case as we do not know the contents of
12019 3. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is defined and not
12020 UNKNOWN. In that case we know those bits are zeros or ones. We must
12021 also be sure that they are the same as the upper bits of op1.
12023 We can never remove a SUBREG for a non-equality comparison because
12024 the sign bit is in a different place in the underlying object. */
12026 op0 = make_compound_operation (op0, op1 == const0_rtx ? COMPARE : SET);
12027 op1 = make_compound_operation (op1, SET);
12029 if (GET_CODE (op0) == SUBREG && subreg_lowpart_p (op0)
12030 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
12031 && GET_MODE_CLASS (GET_MODE (SUBREG_REG (op0))) == MODE_INT
12032 && (code == NE || code == EQ))
12034 if (paradoxical_subreg_p (op0))
12036 /* For paradoxical subregs, allow case 1 as above. Case 3 isn't
12038 if (REG_P (SUBREG_REG (op0)))
12040 op0 = SUBREG_REG (op0);
12041 op1 = gen_lowpart (GET_MODE (op0), op1);
12044 else if ((GET_MODE_PRECISION (GET_MODE (SUBREG_REG (op0)))
12045 <= HOST_BITS_PER_WIDE_INT)
12046 && (nonzero_bits (SUBREG_REG (op0),
12047 GET_MODE (SUBREG_REG (op0)))
12048 & ~GET_MODE_MASK (GET_MODE (op0))) == 0)
12050 tem = gen_lowpart (GET_MODE (SUBREG_REG (op0)), op1);
12052 if ((nonzero_bits (tem, GET_MODE (SUBREG_REG (op0)))
12053 & ~GET_MODE_MASK (GET_MODE (op0))) == 0)
12054 op0 = SUBREG_REG (op0), op1 = tem;
12058 /* We now do the opposite procedure: Some machines don't have compare
12059 insns in all modes. If OP0's mode is an integer mode smaller than a
12060 word and we can't do a compare in that mode, see if there is a larger
12061 mode for which we can do the compare. There are a number of cases in
12062 which we can use the wider mode. */
12064 mode = GET_MODE (op0);
12065 if (mode != VOIDmode && GET_MODE_CLASS (mode) == MODE_INT
12066 && GET_MODE_SIZE (mode) < UNITS_PER_WORD
12067 && ! have_insn_for (COMPARE, mode))
12068 for (tmode = GET_MODE_WIDER_MODE (mode);
12069 (tmode != VOIDmode && HWI_COMPUTABLE_MODE_P (tmode));
12070 tmode = GET_MODE_WIDER_MODE (tmode))
12071 if (have_insn_for (COMPARE, tmode))
12075 /* If this is a test for negative, we can make an explicit
12076 test of the sign bit. Test this first so we can use
12077 a paradoxical subreg to extend OP0. */
12079 if (op1 == const0_rtx && (code == LT || code == GE)
12080 && HWI_COMPUTABLE_MODE_P (mode))
12082 op0 = simplify_gen_binary (AND, tmode,
12083 gen_lowpart (tmode, op0),
12084 GEN_INT ((unsigned HOST_WIDE_INT) 1
12085 << (GET_MODE_BITSIZE (mode)
12087 code = (code == LT) ? NE : EQ;
12091 /* If the only nonzero bits in OP0 and OP1 are those in the
12092 narrower mode and this is an equality or unsigned comparison,
12093 we can use the wider mode. Similarly for sign-extended
12094 values, in which case it is true for all comparisons. */
12095 zero_extended = ((code == EQ || code == NE
12096 || code == GEU || code == GTU
12097 || code == LEU || code == LTU)
12098 && (nonzero_bits (op0, tmode)
12099 & ~GET_MODE_MASK (mode)) == 0
12100 && ((CONST_INT_P (op1)
12101 || (nonzero_bits (op1, tmode)
12102 & ~GET_MODE_MASK (mode)) == 0)));
12105 || ((num_sign_bit_copies (op0, tmode)
12106 > (unsigned int) (GET_MODE_PRECISION (tmode)
12107 - GET_MODE_PRECISION (mode)))
12108 && (num_sign_bit_copies (op1, tmode)
12109 > (unsigned int) (GET_MODE_PRECISION (tmode)
12110 - GET_MODE_PRECISION (mode)))))
12112 /* If OP0 is an AND and we don't have an AND in MODE either,
12113 make a new AND in the proper mode. */
12114 if (GET_CODE (op0) == AND
12115 && !have_insn_for (AND, mode))
12116 op0 = simplify_gen_binary (AND, tmode,
12117 gen_lowpart (tmode,
12119 gen_lowpart (tmode,
12125 op0 = simplify_gen_unary (ZERO_EXTEND, tmode, op0, mode);
12126 op1 = simplify_gen_unary (ZERO_EXTEND, tmode, op1, mode);
12130 op0 = simplify_gen_unary (SIGN_EXTEND, tmode, op0, mode);
12131 op1 = simplify_gen_unary (SIGN_EXTEND, tmode, op1, mode);
12138 #ifdef CANONICALIZE_COMPARISON
12139 /* If this machine only supports a subset of valid comparisons, see if we
12140 can convert an unsupported one into a supported one. */
12141 CANONICALIZE_COMPARISON (code, op0, op1);
12150 /* Utility function for record_value_for_reg. Count number of
12155 enum rtx_code code = GET_CODE (x);
12159 if (GET_RTX_CLASS (code) == '2'
12160 || GET_RTX_CLASS (code) == 'c')
12162 rtx x0 = XEXP (x, 0);
12163 rtx x1 = XEXP (x, 1);
12166 return 1 + 2 * count_rtxs (x0);
12168 if ((GET_RTX_CLASS (GET_CODE (x1)) == '2'
12169 || GET_RTX_CLASS (GET_CODE (x1)) == 'c')
12170 && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1)))
12171 return 2 + 2 * count_rtxs (x0)
12172 + count_rtxs (x == XEXP (x1, 0)
12173 ? XEXP (x1, 1) : XEXP (x1, 0));
12175 if ((GET_RTX_CLASS (GET_CODE (x0)) == '2'
12176 || GET_RTX_CLASS (GET_CODE (x0)) == 'c')
12177 && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1)))
12178 return 2 + 2 * count_rtxs (x1)
12179 + count_rtxs (x == XEXP (x0, 0)
12180 ? XEXP (x0, 1) : XEXP (x0, 0));
12183 fmt = GET_RTX_FORMAT (code);
12184 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
12186 ret += count_rtxs (XEXP (x, i));
12187 else if (fmt[i] == 'E')
12188 for (j = 0; j < XVECLEN (x, i); j++)
12189 ret += count_rtxs (XVECEXP (x, i, j));
12194 /* Utility function for following routine. Called when X is part of a value
12195 being stored into last_set_value. Sets last_set_table_tick
12196 for each register mentioned. Similar to mention_regs in cse.c */
12199 update_table_tick (rtx x)
12201 enum rtx_code code = GET_CODE (x);
12202 const char *fmt = GET_RTX_FORMAT (code);
12207 unsigned int regno = REGNO (x);
12208 unsigned int endregno = END_REGNO (x);
12211 for (r = regno; r < endregno; r++)
12213 reg_stat_type *rsp = VEC_index (reg_stat_type, reg_stat, r);
12214 rsp->last_set_table_tick = label_tick;
12220 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
12223 /* Check for identical subexpressions. If x contains
12224 identical subexpression we only have to traverse one of
12226 if (i == 0 && ARITHMETIC_P (x))
12228 /* Note that at this point x1 has already been
12230 rtx x0 = XEXP (x, 0);
12231 rtx x1 = XEXP (x, 1);
12233 /* If x0 and x1 are identical then there is no need to
12238 /* If x0 is identical to a subexpression of x1 then while
12239 processing x1, x0 has already been processed. Thus we
12240 are done with x. */
12241 if (ARITHMETIC_P (x1)
12242 && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1)))
12245 /* If x1 is identical to a subexpression of x0 then we
12246 still have to process the rest of x0. */
12247 if (ARITHMETIC_P (x0)
12248 && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1)))
12250 update_table_tick (XEXP (x0, x1 == XEXP (x0, 0) ? 1 : 0));
12255 update_table_tick (XEXP (x, i));
12257 else if (fmt[i] == 'E')
12258 for (j = 0; j < XVECLEN (x, i); j++)
12259 update_table_tick (XVECEXP (x, i, j));
12262 /* Record that REG is set to VALUE in insn INSN. If VALUE is zero, we
12263 are saying that the register is clobbered and we no longer know its
12264 value. If INSN is zero, don't update reg_stat[].last_set; this is
12265 only permitted with VALUE also zero and is used to invalidate the
12269 record_value_for_reg (rtx reg, rtx insn, rtx value)
12271 unsigned int regno = REGNO (reg);
12272 unsigned int endregno = END_REGNO (reg);
12274 reg_stat_type *rsp;
12276 /* If VALUE contains REG and we have a previous value for REG, substitute
12277 the previous value. */
12278 if (value && insn && reg_overlap_mentioned_p (reg, value))
12282 /* Set things up so get_last_value is allowed to see anything set up to
12284 subst_low_luid = DF_INSN_LUID (insn);
12285 tem = get_last_value (reg);
12287 /* If TEM is simply a binary operation with two CLOBBERs as operands,
12288 it isn't going to be useful and will take a lot of time to process,
12289 so just use the CLOBBER. */
12293 if (ARITHMETIC_P (tem)
12294 && GET_CODE (XEXP (tem, 0)) == CLOBBER
12295 && GET_CODE (XEXP (tem, 1)) == CLOBBER)
12296 tem = XEXP (tem, 0);
12297 else if (count_occurrences (value, reg, 1) >= 2)
12299 /* If there are two or more occurrences of REG in VALUE,
12300 prevent the value from growing too much. */
12301 if (count_rtxs (tem) > MAX_LAST_VALUE_RTL)
12302 tem = gen_rtx_CLOBBER (GET_MODE (tem), const0_rtx);
12305 value = replace_rtx (copy_rtx (value), reg, tem);
12309 /* For each register modified, show we don't know its value, that
12310 we don't know about its bitwise content, that its value has been
12311 updated, and that we don't know the location of the death of the
12313 for (i = regno; i < endregno; i++)
12315 rsp = VEC_index (reg_stat_type, reg_stat, i);
12318 rsp->last_set = insn;
12320 rsp->last_set_value = 0;
12321 rsp->last_set_mode = VOIDmode;
12322 rsp->last_set_nonzero_bits = 0;
12323 rsp->last_set_sign_bit_copies = 0;
12324 rsp->last_death = 0;
12325 rsp->truncated_to_mode = VOIDmode;
12328 /* Mark registers that are being referenced in this value. */
12330 update_table_tick (value);
12332 /* Now update the status of each register being set.
12333 If someone is using this register in this block, set this register
12334 to invalid since we will get confused between the two lives in this
12335 basic block. This makes using this register always invalid. In cse, we
12336 scan the table to invalidate all entries using this register, but this
12337 is too much work for us. */
12339 for (i = regno; i < endregno; i++)
12341 rsp = VEC_index (reg_stat_type, reg_stat, i);
12342 rsp->last_set_label = label_tick;
12344 || (value && rsp->last_set_table_tick >= label_tick_ebb_start))
12345 rsp->last_set_invalid = 1;
12347 rsp->last_set_invalid = 0;
12350 /* The value being assigned might refer to X (like in "x++;"). In that
12351 case, we must replace it with (clobber (const_int 0)) to prevent
12353 rsp = VEC_index (reg_stat_type, reg_stat, regno);
12354 if (value && !get_last_value_validate (&value, insn, label_tick, 0))
12356 value = copy_rtx (value);
12357 if (!get_last_value_validate (&value, insn, label_tick, 1))
12361 /* For the main register being modified, update the value, the mode, the
12362 nonzero bits, and the number of sign bit copies. */
12364 rsp->last_set_value = value;
12368 enum machine_mode mode = GET_MODE (reg);
12369 subst_low_luid = DF_INSN_LUID (insn);
12370 rsp->last_set_mode = mode;
12371 if (GET_MODE_CLASS (mode) == MODE_INT
12372 && HWI_COMPUTABLE_MODE_P (mode))
12373 mode = nonzero_bits_mode;
12374 rsp->last_set_nonzero_bits = nonzero_bits (value, mode);
12375 rsp->last_set_sign_bit_copies
12376 = num_sign_bit_copies (value, GET_MODE (reg));
12380 /* Called via note_stores from record_dead_and_set_regs to handle one
12381 SET or CLOBBER in an insn. DATA is the instruction in which the
12382 set is occurring. */
12385 record_dead_and_set_regs_1 (rtx dest, const_rtx setter, void *data)
12387 rtx record_dead_insn = (rtx) data;
12389 if (GET_CODE (dest) == SUBREG)
12390 dest = SUBREG_REG (dest);
12392 if (!record_dead_insn)
12395 record_value_for_reg (dest, NULL_RTX, NULL_RTX);
12401 /* If we are setting the whole register, we know its value. Otherwise
12402 show that we don't know the value. We can handle SUBREG in
12404 if (GET_CODE (setter) == SET && dest == SET_DEST (setter))
12405 record_value_for_reg (dest, record_dead_insn, SET_SRC (setter));
12406 else if (GET_CODE (setter) == SET
12407 && GET_CODE (SET_DEST (setter)) == SUBREG
12408 && SUBREG_REG (SET_DEST (setter)) == dest
12409 && GET_MODE_PRECISION (GET_MODE (dest)) <= BITS_PER_WORD
12410 && subreg_lowpart_p (SET_DEST (setter)))
12411 record_value_for_reg (dest, record_dead_insn,
12412 gen_lowpart (GET_MODE (dest),
12413 SET_SRC (setter)));
12415 record_value_for_reg (dest, record_dead_insn, NULL_RTX);
12417 else if (MEM_P (dest)
12418 /* Ignore pushes, they clobber nothing. */
12419 && ! push_operand (dest, GET_MODE (dest)))
12420 mem_last_set = DF_INSN_LUID (record_dead_insn);
12423 /* Update the records of when each REG was most recently set or killed
12424 for the things done by INSN. This is the last thing done in processing
12425 INSN in the combiner loop.
12427 We update reg_stat[], in particular fields last_set, last_set_value,
12428 last_set_mode, last_set_nonzero_bits, last_set_sign_bit_copies,
12429 last_death, and also the similar information mem_last_set (which insn
12430 most recently modified memory) and last_call_luid (which insn was the
12431 most recent subroutine call). */
12434 record_dead_and_set_regs (rtx insn)
12439 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
12441 if (REG_NOTE_KIND (link) == REG_DEAD
12442 && REG_P (XEXP (link, 0)))
12444 unsigned int regno = REGNO (XEXP (link, 0));
12445 unsigned int endregno = END_REGNO (XEXP (link, 0));
12447 for (i = regno; i < endregno; i++)
12449 reg_stat_type *rsp;
12451 rsp = VEC_index (reg_stat_type, reg_stat, i);
12452 rsp->last_death = insn;
12455 else if (REG_NOTE_KIND (link) == REG_INC)
12456 record_value_for_reg (XEXP (link, 0), insn, NULL_RTX);
12461 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
12462 if (TEST_HARD_REG_BIT (regs_invalidated_by_call, i))
12464 reg_stat_type *rsp;
12466 rsp = VEC_index (reg_stat_type, reg_stat, i);
12467 rsp->last_set_invalid = 1;
12468 rsp->last_set = insn;
12469 rsp->last_set_value = 0;
12470 rsp->last_set_mode = VOIDmode;
12471 rsp->last_set_nonzero_bits = 0;
12472 rsp->last_set_sign_bit_copies = 0;
12473 rsp->last_death = 0;
12474 rsp->truncated_to_mode = VOIDmode;
12477 last_call_luid = mem_last_set = DF_INSN_LUID (insn);
12479 /* We can't combine into a call pattern. Remember, though, that
12480 the return value register is set at this LUID. We could
12481 still replace a register with the return value from the
12482 wrong subroutine call! */
12483 note_stores (PATTERN (insn), record_dead_and_set_regs_1, NULL_RTX);
12486 note_stores (PATTERN (insn), record_dead_and_set_regs_1, insn);
12489 /* If a SUBREG has the promoted bit set, it is in fact a property of the
12490 register present in the SUBREG, so for each such SUBREG go back and
12491 adjust nonzero and sign bit information of the registers that are
12492 known to have some zero/sign bits set.
12494 This is needed because when combine blows the SUBREGs away, the
12495 information on zero/sign bits is lost and further combines can be
12496 missed because of that. */
12499 record_promoted_value (rtx insn, rtx subreg)
12501 struct insn_link *links;
12503 unsigned int regno = REGNO (SUBREG_REG (subreg));
12504 enum machine_mode mode = GET_MODE (subreg);
12506 if (GET_MODE_PRECISION (mode) > HOST_BITS_PER_WIDE_INT)
12509 for (links = LOG_LINKS (insn); links;)
12511 reg_stat_type *rsp;
12513 insn = links->insn;
12514 set = single_set (insn);
12516 if (! set || !REG_P (SET_DEST (set))
12517 || REGNO (SET_DEST (set)) != regno
12518 || GET_MODE (SET_DEST (set)) != GET_MODE (SUBREG_REG (subreg)))
12520 links = links->next;
12524 rsp = VEC_index (reg_stat_type, reg_stat, regno);
12525 if (rsp->last_set == insn)
12527 if (SUBREG_PROMOTED_UNSIGNED_P (subreg) > 0)
12528 rsp->last_set_nonzero_bits &= GET_MODE_MASK (mode);
12531 if (REG_P (SET_SRC (set)))
12533 regno = REGNO (SET_SRC (set));
12534 links = LOG_LINKS (insn);
12541 /* Check if X, a register, is known to contain a value already
12542 truncated to MODE. In this case we can use a subreg to refer to
12543 the truncated value even though in the generic case we would need
12544 an explicit truncation. */
12547 reg_truncated_to_mode (enum machine_mode mode, const_rtx x)
12549 reg_stat_type *rsp = VEC_index (reg_stat_type, reg_stat, REGNO (x));
12550 enum machine_mode truncated = rsp->truncated_to_mode;
12553 || rsp->truncation_label < label_tick_ebb_start)
12555 if (GET_MODE_SIZE (truncated) <= GET_MODE_SIZE (mode))
12557 if (TRULY_NOOP_TRUNCATION_MODES_P (mode, truncated))
12562 /* Callback for for_each_rtx. If *P is a hard reg or a subreg record the mode
12563 that the register is accessed in. For non-TRULY_NOOP_TRUNCATION targets we
12564 might be able to turn a truncate into a subreg using this information.
12565 Return -1 if traversing *P is complete or 0 otherwise. */
12568 record_truncated_value (rtx *p, void *data ATTRIBUTE_UNUSED)
12571 enum machine_mode truncated_mode;
12572 reg_stat_type *rsp;
12574 if (GET_CODE (x) == SUBREG && REG_P (SUBREG_REG (x)))
12576 enum machine_mode original_mode = GET_MODE (SUBREG_REG (x));
12577 truncated_mode = GET_MODE (x);
12579 if (GET_MODE_SIZE (original_mode) <= GET_MODE_SIZE (truncated_mode))
12582 if (TRULY_NOOP_TRUNCATION_MODES_P (truncated_mode, original_mode))
12585 x = SUBREG_REG (x);
12587 /* ??? For hard-regs we now record everything. We might be able to
12588 optimize this using last_set_mode. */
12589 else if (REG_P (x) && REGNO (x) < FIRST_PSEUDO_REGISTER)
12590 truncated_mode = GET_MODE (x);
12594 rsp = VEC_index (reg_stat_type, reg_stat, REGNO (x));
12595 if (rsp->truncated_to_mode == 0
12596 || rsp->truncation_label < label_tick_ebb_start
12597 || (GET_MODE_SIZE (truncated_mode)
12598 < GET_MODE_SIZE (rsp->truncated_to_mode)))
12600 rsp->truncated_to_mode = truncated_mode;
12601 rsp->truncation_label = label_tick;
12607 /* Callback for note_uses. Find hardregs and subregs of pseudos and
12608 the modes they are used in. This can help truning TRUNCATEs into
12612 record_truncated_values (rtx *x, void *data ATTRIBUTE_UNUSED)
12614 for_each_rtx (x, record_truncated_value, NULL);
12617 /* Scan X for promoted SUBREGs. For each one found,
12618 note what it implies to the registers used in it. */
12621 check_promoted_subreg (rtx insn, rtx x)
12623 if (GET_CODE (x) == SUBREG
12624 && SUBREG_PROMOTED_VAR_P (x)
12625 && REG_P (SUBREG_REG (x)))
12626 record_promoted_value (insn, x);
12629 const char *format = GET_RTX_FORMAT (GET_CODE (x));
12632 for (i = 0; i < GET_RTX_LENGTH (GET_CODE (x)); i++)
12636 check_promoted_subreg (insn, XEXP (x, i));
12640 if (XVEC (x, i) != 0)
12641 for (j = 0; j < XVECLEN (x, i); j++)
12642 check_promoted_subreg (insn, XVECEXP (x, i, j));
12648 /* Verify that all the registers and memory references mentioned in *LOC are
12649 still valid. *LOC was part of a value set in INSN when label_tick was
12650 equal to TICK. Return 0 if some are not. If REPLACE is nonzero, replace
12651 the invalid references with (clobber (const_int 0)) and return 1. This
12652 replacement is useful because we often can get useful information about
12653 the form of a value (e.g., if it was produced by a shift that always
12654 produces -1 or 0) even though we don't know exactly what registers it
12655 was produced from. */
12658 get_last_value_validate (rtx *loc, rtx insn, int tick, int replace)
12661 const char *fmt = GET_RTX_FORMAT (GET_CODE (x));
12662 int len = GET_RTX_LENGTH (GET_CODE (x));
12667 unsigned int regno = REGNO (x);
12668 unsigned int endregno = END_REGNO (x);
12671 for (j = regno; j < endregno; j++)
12673 reg_stat_type *rsp = VEC_index (reg_stat_type, reg_stat, j);
12674 if (rsp->last_set_invalid
12675 /* If this is a pseudo-register that was only set once and not
12676 live at the beginning of the function, it is always valid. */
12677 || (! (regno >= FIRST_PSEUDO_REGISTER
12678 && REG_N_SETS (regno) == 1
12679 && (!REGNO_REG_SET_P
12680 (DF_LR_IN (ENTRY_BLOCK_PTR->next_bb), regno)))
12681 && rsp->last_set_label > tick))
12684 *loc = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
12691 /* If this is a memory reference, make sure that there were no stores after
12692 it that might have clobbered the value. We don't have alias info, so we
12693 assume any store invalidates it. Moreover, we only have local UIDs, so
12694 we also assume that there were stores in the intervening basic blocks. */
12695 else if (MEM_P (x) && !MEM_READONLY_P (x)
12696 && (tick != label_tick || DF_INSN_LUID (insn) <= mem_last_set))
12699 *loc = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
12703 for (i = 0; i < len; i++)
12707 /* Check for identical subexpressions. If x contains
12708 identical subexpression we only have to traverse one of
12710 if (i == 1 && ARITHMETIC_P (x))
12712 /* Note that at this point x0 has already been checked
12713 and found valid. */
12714 rtx x0 = XEXP (x, 0);
12715 rtx x1 = XEXP (x, 1);
12717 /* If x0 and x1 are identical then x is also valid. */
12721 /* If x1 is identical to a subexpression of x0 then
12722 while checking x0, x1 has already been checked. Thus
12723 it is valid and so as x. */
12724 if (ARITHMETIC_P (x0)
12725 && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1)))
12728 /* If x0 is identical to a subexpression of x1 then x is
12729 valid iff the rest of x1 is valid. */
12730 if (ARITHMETIC_P (x1)
12731 && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1)))
12733 get_last_value_validate (&XEXP (x1,
12734 x0 == XEXP (x1, 0) ? 1 : 0),
12735 insn, tick, replace);
12738 if (get_last_value_validate (&XEXP (x, i), insn, tick,
12742 else if (fmt[i] == 'E')
12743 for (j = 0; j < XVECLEN (x, i); j++)
12744 if (get_last_value_validate (&XVECEXP (x, i, j),
12745 insn, tick, replace) == 0)
12749 /* If we haven't found a reason for it to be invalid, it is valid. */
12753 /* Get the last value assigned to X, if known. Some registers
12754 in the value may be replaced with (clobber (const_int 0)) if their value
12755 is known longer known reliably. */
12758 get_last_value (const_rtx x)
12760 unsigned int regno;
12762 reg_stat_type *rsp;
12764 /* If this is a non-paradoxical SUBREG, get the value of its operand and
12765 then convert it to the desired mode. If this is a paradoxical SUBREG,
12766 we cannot predict what values the "extra" bits might have. */
12767 if (GET_CODE (x) == SUBREG
12768 && subreg_lowpart_p (x)
12769 && !paradoxical_subreg_p (x)
12770 && (value = get_last_value (SUBREG_REG (x))) != 0)
12771 return gen_lowpart (GET_MODE (x), value);
12777 rsp = VEC_index (reg_stat_type, reg_stat, regno);
12778 value = rsp->last_set_value;
12780 /* If we don't have a value, or if it isn't for this basic block and
12781 it's either a hard register, set more than once, or it's a live
12782 at the beginning of the function, return 0.
12784 Because if it's not live at the beginning of the function then the reg
12785 is always set before being used (is never used without being set).
12786 And, if it's set only once, and it's always set before use, then all
12787 uses must have the same last value, even if it's not from this basic
12791 || (rsp->last_set_label < label_tick_ebb_start
12792 && (regno < FIRST_PSEUDO_REGISTER
12793 || REG_N_SETS (regno) != 1
12795 (DF_LR_IN (ENTRY_BLOCK_PTR->next_bb), regno))))
12798 /* If the value was set in a later insn than the ones we are processing,
12799 we can't use it even if the register was only set once. */
12800 if (rsp->last_set_label == label_tick
12801 && DF_INSN_LUID (rsp->last_set) >= subst_low_luid)
12804 /* If the value has all its registers valid, return it. */
12805 if (get_last_value_validate (&value, rsp->last_set, rsp->last_set_label, 0))
12808 /* Otherwise, make a copy and replace any invalid register with
12809 (clobber (const_int 0)). If that fails for some reason, return 0. */
12811 value = copy_rtx (value);
12812 if (get_last_value_validate (&value, rsp->last_set, rsp->last_set_label, 1))
12818 /* Return nonzero if expression X refers to a REG or to memory
12819 that is set in an instruction more recent than FROM_LUID. */
12822 use_crosses_set_p (const_rtx x, int from_luid)
12826 enum rtx_code code = GET_CODE (x);
12830 unsigned int regno = REGNO (x);
12831 unsigned endreg = END_REGNO (x);
12833 #ifdef PUSH_ROUNDING
12834 /* Don't allow uses of the stack pointer to be moved,
12835 because we don't know whether the move crosses a push insn. */
12836 if (regno == STACK_POINTER_REGNUM && PUSH_ARGS)
12839 for (; regno < endreg; regno++)
12841 reg_stat_type *rsp = VEC_index (reg_stat_type, reg_stat, regno);
12843 && rsp->last_set_label == label_tick
12844 && DF_INSN_LUID (rsp->last_set) > from_luid)
12850 if (code == MEM && mem_last_set > from_luid)
12853 fmt = GET_RTX_FORMAT (code);
12855 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
12860 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
12861 if (use_crosses_set_p (XVECEXP (x, i, j), from_luid))
12864 else if (fmt[i] == 'e'
12865 && use_crosses_set_p (XEXP (x, i), from_luid))
12871 /* Define three variables used for communication between the following
12874 static unsigned int reg_dead_regno, reg_dead_endregno;
12875 static int reg_dead_flag;
12877 /* Function called via note_stores from reg_dead_at_p.
12879 If DEST is within [reg_dead_regno, reg_dead_endregno), set
12880 reg_dead_flag to 1 if X is a CLOBBER and to -1 it is a SET. */
12883 reg_dead_at_p_1 (rtx dest, const_rtx x, void *data ATTRIBUTE_UNUSED)
12885 unsigned int regno, endregno;
12890 regno = REGNO (dest);
12891 endregno = END_REGNO (dest);
12892 if (reg_dead_endregno > regno && reg_dead_regno < endregno)
12893 reg_dead_flag = (GET_CODE (x) == CLOBBER) ? 1 : -1;
12896 /* Return nonzero if REG is known to be dead at INSN.
12898 We scan backwards from INSN. If we hit a REG_DEAD note or a CLOBBER
12899 referencing REG, it is dead. If we hit a SET referencing REG, it is
12900 live. Otherwise, see if it is live or dead at the start of the basic
12901 block we are in. Hard regs marked as being live in NEWPAT_USED_REGS
12902 must be assumed to be always live. */
12905 reg_dead_at_p (rtx reg, rtx insn)
12910 /* Set variables for reg_dead_at_p_1. */
12911 reg_dead_regno = REGNO (reg);
12912 reg_dead_endregno = END_REGNO (reg);
12916 /* Check that reg isn't mentioned in NEWPAT_USED_REGS. For fixed registers
12917 we allow the machine description to decide whether use-and-clobber
12918 patterns are OK. */
12919 if (reg_dead_regno < FIRST_PSEUDO_REGISTER)
12921 for (i = reg_dead_regno; i < reg_dead_endregno; i++)
12922 if (!fixed_regs[i] && TEST_HARD_REG_BIT (newpat_used_regs, i))
12926 /* Scan backwards until we find a REG_DEAD note, SET, CLOBBER, or
12927 beginning of basic block. */
12928 block = BLOCK_FOR_INSN (insn);
12933 note_stores (PATTERN (insn), reg_dead_at_p_1, NULL);
12935 return reg_dead_flag == 1 ? 1 : 0;
12937 if (find_regno_note (insn, REG_DEAD, reg_dead_regno))
12941 if (insn == BB_HEAD (block))
12944 insn = PREV_INSN (insn);
12947 /* Look at live-in sets for the basic block that we were in. */
12948 for (i = reg_dead_regno; i < reg_dead_endregno; i++)
12949 if (REGNO_REG_SET_P (df_get_live_in (block), i))
12955 /* Note hard registers in X that are used. */
12958 mark_used_regs_combine (rtx x)
12960 RTX_CODE code = GET_CODE (x);
12961 unsigned int regno;
12974 case ADDR_DIFF_VEC:
12977 /* CC0 must die in the insn after it is set, so we don't need to take
12978 special note of it here. */
12984 /* If we are clobbering a MEM, mark any hard registers inside the
12985 address as used. */
12986 if (MEM_P (XEXP (x, 0)))
12987 mark_used_regs_combine (XEXP (XEXP (x, 0), 0));
12992 /* A hard reg in a wide mode may really be multiple registers.
12993 If so, mark all of them just like the first. */
12994 if (regno < FIRST_PSEUDO_REGISTER)
12996 /* None of this applies to the stack, frame or arg pointers. */
12997 if (regno == STACK_POINTER_REGNUM
12998 #if !HARD_FRAME_POINTER_IS_FRAME_POINTER
12999 || regno == HARD_FRAME_POINTER_REGNUM
13001 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
13002 || (regno == ARG_POINTER_REGNUM && fixed_regs[regno])
13004 || regno == FRAME_POINTER_REGNUM)
13007 add_to_hard_reg_set (&newpat_used_regs, GET_MODE (x), regno);
13013 /* If setting a MEM, or a SUBREG of a MEM, then note any hard regs in
13015 rtx testreg = SET_DEST (x);
13017 while (GET_CODE (testreg) == SUBREG
13018 || GET_CODE (testreg) == ZERO_EXTRACT
13019 || GET_CODE (testreg) == STRICT_LOW_PART)
13020 testreg = XEXP (testreg, 0);
13022 if (MEM_P (testreg))
13023 mark_used_regs_combine (XEXP (testreg, 0));
13025 mark_used_regs_combine (SET_SRC (x));
13033 /* Recursively scan the operands of this expression. */
13036 const char *fmt = GET_RTX_FORMAT (code);
13038 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
13041 mark_used_regs_combine (XEXP (x, i));
13042 else if (fmt[i] == 'E')
13046 for (j = 0; j < XVECLEN (x, i); j++)
13047 mark_used_regs_combine (XVECEXP (x, i, j));
13053 /* Remove register number REGNO from the dead registers list of INSN.
13055 Return the note used to record the death, if there was one. */
13058 remove_death (unsigned int regno, rtx insn)
13060 rtx note = find_regno_note (insn, REG_DEAD, regno);
13063 remove_note (insn, note);
13068 /* For each register (hardware or pseudo) used within expression X, if its
13069 death is in an instruction with luid between FROM_LUID (inclusive) and
13070 TO_INSN (exclusive), put a REG_DEAD note for that register in the
13071 list headed by PNOTES.
13073 That said, don't move registers killed by maybe_kill_insn.
13075 This is done when X is being merged by combination into TO_INSN. These
13076 notes will then be distributed as needed. */
13079 move_deaths (rtx x, rtx maybe_kill_insn, int from_luid, rtx to_insn,
13084 enum rtx_code code = GET_CODE (x);
13088 unsigned int regno = REGNO (x);
13089 rtx where_dead = VEC_index (reg_stat_type, reg_stat, regno)->last_death;
13091 /* Don't move the register if it gets killed in between from and to. */
13092 if (maybe_kill_insn && reg_set_p (x, maybe_kill_insn)
13093 && ! reg_referenced_p (x, maybe_kill_insn))
13097 && BLOCK_FOR_INSN (where_dead) == BLOCK_FOR_INSN (to_insn)
13098 && DF_INSN_LUID (where_dead) >= from_luid
13099 && DF_INSN_LUID (where_dead) < DF_INSN_LUID (to_insn))
13101 rtx note = remove_death (regno, where_dead);
13103 /* It is possible for the call above to return 0. This can occur
13104 when last_death points to I2 or I1 that we combined with.
13105 In that case make a new note.
13107 We must also check for the case where X is a hard register
13108 and NOTE is a death note for a range of hard registers
13109 including X. In that case, we must put REG_DEAD notes for
13110 the remaining registers in place of NOTE. */
13112 if (note != 0 && regno < FIRST_PSEUDO_REGISTER
13113 && (GET_MODE_SIZE (GET_MODE (XEXP (note, 0)))
13114 > GET_MODE_SIZE (GET_MODE (x))))
13116 unsigned int deadregno = REGNO (XEXP (note, 0));
13117 unsigned int deadend = END_HARD_REGNO (XEXP (note, 0));
13118 unsigned int ourend = END_HARD_REGNO (x);
13121 for (i = deadregno; i < deadend; i++)
13122 if (i < regno || i >= ourend)
13123 add_reg_note (where_dead, REG_DEAD, regno_reg_rtx[i]);
13126 /* If we didn't find any note, or if we found a REG_DEAD note that
13127 covers only part of the given reg, and we have a multi-reg hard
13128 register, then to be safe we must check for REG_DEAD notes
13129 for each register other than the first. They could have
13130 their own REG_DEAD notes lying around. */
13131 else if ((note == 0
13133 && (GET_MODE_SIZE (GET_MODE (XEXP (note, 0)))
13134 < GET_MODE_SIZE (GET_MODE (x)))))
13135 && regno < FIRST_PSEUDO_REGISTER
13136 && hard_regno_nregs[regno][GET_MODE (x)] > 1)
13138 unsigned int ourend = END_HARD_REGNO (x);
13139 unsigned int i, offset;
13143 offset = hard_regno_nregs[regno][GET_MODE (XEXP (note, 0))];
13147 for (i = regno + offset; i < ourend; i++)
13148 move_deaths (regno_reg_rtx[i],
13149 maybe_kill_insn, from_luid, to_insn, &oldnotes);
13152 if (note != 0 && GET_MODE (XEXP (note, 0)) == GET_MODE (x))
13154 XEXP (note, 1) = *pnotes;
13158 *pnotes = alloc_reg_note (REG_DEAD, x, *pnotes);
13164 else if (GET_CODE (x) == SET)
13166 rtx dest = SET_DEST (x);
13168 move_deaths (SET_SRC (x), maybe_kill_insn, from_luid, to_insn, pnotes);
13170 /* In the case of a ZERO_EXTRACT, a STRICT_LOW_PART, or a SUBREG
13171 that accesses one word of a multi-word item, some
13172 piece of everything register in the expression is used by
13173 this insn, so remove any old death. */
13174 /* ??? So why do we test for equality of the sizes? */
13176 if (GET_CODE (dest) == ZERO_EXTRACT
13177 || GET_CODE (dest) == STRICT_LOW_PART
13178 || (GET_CODE (dest) == SUBREG
13179 && (((GET_MODE_SIZE (GET_MODE (dest))
13180 + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
13181 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (dest)))
13182 + UNITS_PER_WORD - 1) / UNITS_PER_WORD))))
13184 move_deaths (dest, maybe_kill_insn, from_luid, to_insn, pnotes);
13188 /* If this is some other SUBREG, we know it replaces the entire
13189 value, so use that as the destination. */
13190 if (GET_CODE (dest) == SUBREG)
13191 dest = SUBREG_REG (dest);
13193 /* If this is a MEM, adjust deaths of anything used in the address.
13194 For a REG (the only other possibility), the entire value is
13195 being replaced so the old value is not used in this insn. */
13198 move_deaths (XEXP (dest, 0), maybe_kill_insn, from_luid,
13203 else if (GET_CODE (x) == CLOBBER)
13206 len = GET_RTX_LENGTH (code);
13207 fmt = GET_RTX_FORMAT (code);
13209 for (i = 0; i < len; i++)
13214 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
13215 move_deaths (XVECEXP (x, i, j), maybe_kill_insn, from_luid,
13218 else if (fmt[i] == 'e')
13219 move_deaths (XEXP (x, i), maybe_kill_insn, from_luid, to_insn, pnotes);
13223 /* Return 1 if X is the target of a bit-field assignment in BODY, the
13224 pattern of an insn. X must be a REG. */
13227 reg_bitfield_target_p (rtx x, rtx body)
13231 if (GET_CODE (body) == SET)
13233 rtx dest = SET_DEST (body);
13235 unsigned int regno, tregno, endregno, endtregno;
13237 if (GET_CODE (dest) == ZERO_EXTRACT)
13238 target = XEXP (dest, 0);
13239 else if (GET_CODE (dest) == STRICT_LOW_PART)
13240 target = SUBREG_REG (XEXP (dest, 0));
13244 if (GET_CODE (target) == SUBREG)
13245 target = SUBREG_REG (target);
13247 if (!REG_P (target))
13250 tregno = REGNO (target), regno = REGNO (x);
13251 if (tregno >= FIRST_PSEUDO_REGISTER || regno >= FIRST_PSEUDO_REGISTER)
13252 return target == x;
13254 endtregno = end_hard_regno (GET_MODE (target), tregno);
13255 endregno = end_hard_regno (GET_MODE (x), regno);
13257 return endregno > tregno && regno < endtregno;
13260 else if (GET_CODE (body) == PARALLEL)
13261 for (i = XVECLEN (body, 0) - 1; i >= 0; i--)
13262 if (reg_bitfield_target_p (x, XVECEXP (body, 0, i)))
13268 /* Given a chain of REG_NOTES originally from FROM_INSN, try to place them
13269 as appropriate. I3 and I2 are the insns resulting from the combination
13270 insns including FROM (I2 may be zero).
13272 ELIM_I2 and ELIM_I1 are either zero or registers that we know will
13273 not need REG_DEAD notes because they are being substituted for. This
13274 saves searching in the most common cases.
13276 Each note in the list is either ignored or placed on some insns, depending
13277 on the type of note. */
13280 distribute_notes (rtx notes, rtx from_insn, rtx i3, rtx i2, rtx elim_i2,
13281 rtx elim_i1, rtx elim_i0)
13283 rtx note, next_note;
13286 for (note = notes; note; note = next_note)
13288 rtx place = 0, place2 = 0;
13290 next_note = XEXP (note, 1);
13291 switch (REG_NOTE_KIND (note))
13295 /* Doesn't matter much where we put this, as long as it's somewhere.
13296 It is preferable to keep these notes on branches, which is most
13297 likely to be i3. */
13301 case REG_NON_LOCAL_GOTO:
13306 gcc_assert (i2 && JUMP_P (i2));
13311 case REG_EH_REGION:
13312 /* These notes must remain with the call or trapping instruction. */
13315 else if (i2 && CALL_P (i2))
13319 gcc_assert (cfun->can_throw_non_call_exceptions);
13320 if (may_trap_p (i3))
13322 else if (i2 && may_trap_p (i2))
13324 /* ??? Otherwise assume we've combined things such that we
13325 can now prove that the instructions can't trap. Drop the
13326 note in this case. */
13330 case REG_ARGS_SIZE:
13331 /* ??? How to distribute between i3-i1. Assume i3 contains the
13332 entire adjustment. Assert i3 contains at least some adjust. */
13333 if (!noop_move_p (i3))
13335 int old_size, args_size = INTVAL (XEXP (note, 0));
13336 /* fixup_args_size_notes looks at REG_NORETURN note,
13337 so ensure the note is placed there first. */
13341 for (np = &next_note; *np; np = &XEXP (*np, 1))
13342 if (REG_NOTE_KIND (*np) == REG_NORETURN)
13346 XEXP (n, 1) = REG_NOTES (i3);
13347 REG_NOTES (i3) = n;
13351 old_size = fixup_args_size_notes (PREV_INSN (i3), i3, args_size);
13352 /* emit_call_1 adds for !ACCUMULATE_OUTGOING_ARGS
13353 REG_ARGS_SIZE note to all noreturn calls, allow that here. */
13354 gcc_assert (old_size != args_size
13356 && !ACCUMULATE_OUTGOING_ARGS
13357 && find_reg_note (i3, REG_NORETURN, NULL_RTX)));
13364 /* These notes must remain with the call. It should not be
13365 possible for both I2 and I3 to be a call. */
13370 gcc_assert (i2 && CALL_P (i2));
13376 /* Any clobbers for i3 may still exist, and so we must process
13377 REG_UNUSED notes from that insn.
13379 Any clobbers from i2 or i1 can only exist if they were added by
13380 recog_for_combine. In that case, recog_for_combine created the
13381 necessary REG_UNUSED notes. Trying to keep any original
13382 REG_UNUSED notes from these insns can cause incorrect output
13383 if it is for the same register as the original i3 dest.
13384 In that case, we will notice that the register is set in i3,
13385 and then add a REG_UNUSED note for the destination of i3, which
13386 is wrong. However, it is possible to have REG_UNUSED notes from
13387 i2 or i1 for register which were both used and clobbered, so
13388 we keep notes from i2 or i1 if they will turn into REG_DEAD
13391 /* If this register is set or clobbered in I3, put the note there
13392 unless there is one already. */
13393 if (reg_set_p (XEXP (note, 0), PATTERN (i3)))
13395 if (from_insn != i3)
13398 if (! (REG_P (XEXP (note, 0))
13399 ? find_regno_note (i3, REG_UNUSED, REGNO (XEXP (note, 0)))
13400 : find_reg_note (i3, REG_UNUSED, XEXP (note, 0))))
13403 /* Otherwise, if this register is used by I3, then this register
13404 now dies here, so we must put a REG_DEAD note here unless there
13406 else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3))
13407 && ! (REG_P (XEXP (note, 0))
13408 ? find_regno_note (i3, REG_DEAD,
13409 REGNO (XEXP (note, 0)))
13410 : find_reg_note (i3, REG_DEAD, XEXP (note, 0))))
13412 PUT_REG_NOTE_KIND (note, REG_DEAD);
13420 /* These notes say something about results of an insn. We can
13421 only support them if they used to be on I3 in which case they
13422 remain on I3. Otherwise they are ignored.
13424 If the note refers to an expression that is not a constant, we
13425 must also ignore the note since we cannot tell whether the
13426 equivalence is still true. It might be possible to do
13427 slightly better than this (we only have a problem if I2DEST
13428 or I1DEST is present in the expression), but it doesn't
13429 seem worth the trouble. */
13431 if (from_insn == i3
13432 && (XEXP (note, 0) == 0 || CONSTANT_P (XEXP (note, 0))))
13437 /* These notes say something about how a register is used. They must
13438 be present on any use of the register in I2 or I3. */
13439 if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3)))
13442 if (i2 && reg_mentioned_p (XEXP (note, 0), PATTERN (i2)))
13451 case REG_LABEL_TARGET:
13452 case REG_LABEL_OPERAND:
13453 /* This can show up in several ways -- either directly in the
13454 pattern, or hidden off in the constant pool with (or without?)
13455 a REG_EQUAL note. */
13456 /* ??? Ignore the without-reg_equal-note problem for now. */
13457 if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3))
13458 || ((tem = find_reg_note (i3, REG_EQUAL, NULL_RTX))
13459 && GET_CODE (XEXP (tem, 0)) == LABEL_REF
13460 && XEXP (XEXP (tem, 0), 0) == XEXP (note, 0)))
13464 && (reg_mentioned_p (XEXP (note, 0), PATTERN (i2))
13465 || ((tem = find_reg_note (i2, REG_EQUAL, NULL_RTX))
13466 && GET_CODE (XEXP (tem, 0)) == LABEL_REF
13467 && XEXP (XEXP (tem, 0), 0) == XEXP (note, 0))))
13475 /* For REG_LABEL_TARGET on a JUMP_P, we prefer to put the note
13476 as a JUMP_LABEL or decrement LABEL_NUSES if it's already
13478 if (place && JUMP_P (place)
13479 && REG_NOTE_KIND (note) == REG_LABEL_TARGET
13480 && (JUMP_LABEL (place) == NULL
13481 || JUMP_LABEL (place) == XEXP (note, 0)))
13483 rtx label = JUMP_LABEL (place);
13486 JUMP_LABEL (place) = XEXP (note, 0);
13487 else if (LABEL_P (label))
13488 LABEL_NUSES (label)--;
13491 if (place2 && JUMP_P (place2)
13492 && REG_NOTE_KIND (note) == REG_LABEL_TARGET
13493 && (JUMP_LABEL (place2) == NULL
13494 || JUMP_LABEL (place2) == XEXP (note, 0)))
13496 rtx label = JUMP_LABEL (place2);
13499 JUMP_LABEL (place2) = XEXP (note, 0);
13500 else if (LABEL_P (label))
13501 LABEL_NUSES (label)--;
13507 /* This note says something about the value of a register prior
13508 to the execution of an insn. It is too much trouble to see
13509 if the note is still correct in all situations. It is better
13510 to simply delete it. */
13514 /* If we replaced the right hand side of FROM_INSN with a
13515 REG_EQUAL note, the original use of the dying register
13516 will not have been combined into I3 and I2. In such cases,
13517 FROM_INSN is guaranteed to be the first of the combined
13518 instructions, so we simply need to search back before
13519 FROM_INSN for the previous use or set of this register,
13520 then alter the notes there appropriately.
13522 If the register is used as an input in I3, it dies there.
13523 Similarly for I2, if it is nonzero and adjacent to I3.
13525 If the register is not used as an input in either I3 or I2
13526 and it is not one of the registers we were supposed to eliminate,
13527 there are two possibilities. We might have a non-adjacent I2
13528 or we might have somehow eliminated an additional register
13529 from a computation. For example, we might have had A & B where
13530 we discover that B will always be zero. In this case we will
13531 eliminate the reference to A.
13533 In both cases, we must search to see if we can find a previous
13534 use of A and put the death note there. */
13537 && from_insn == i2mod
13538 && !reg_overlap_mentioned_p (XEXP (note, 0), i2mod_new_rhs))
13543 && CALL_P (from_insn)
13544 && find_reg_fusage (from_insn, USE, XEXP (note, 0)))
13546 else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3)))
13548 else if (i2 != 0 && next_nonnote_nondebug_insn (i2) == i3
13549 && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
13551 else if ((rtx_equal_p (XEXP (note, 0), elim_i2)
13553 && reg_overlap_mentioned_p (XEXP (note, 0),
13555 || rtx_equal_p (XEXP (note, 0), elim_i1)
13556 || rtx_equal_p (XEXP (note, 0), elim_i0))
13563 basic_block bb = this_basic_block;
13565 for (tem = PREV_INSN (tem); place == 0; tem = PREV_INSN (tem))
13567 if (!NONDEBUG_INSN_P (tem))
13569 if (tem == BB_HEAD (bb))
13574 /* If the register is being set at TEM, see if that is all
13575 TEM is doing. If so, delete TEM. Otherwise, make this
13576 into a REG_UNUSED note instead. Don't delete sets to
13577 global register vars. */
13578 if ((REGNO (XEXP (note, 0)) >= FIRST_PSEUDO_REGISTER
13579 || !global_regs[REGNO (XEXP (note, 0))])
13580 && reg_set_p (XEXP (note, 0), PATTERN (tem)))
13582 rtx set = single_set (tem);
13583 rtx inner_dest = 0;
13585 rtx cc0_setter = NULL_RTX;
13589 for (inner_dest = SET_DEST (set);
13590 (GET_CODE (inner_dest) == STRICT_LOW_PART
13591 || GET_CODE (inner_dest) == SUBREG
13592 || GET_CODE (inner_dest) == ZERO_EXTRACT);
13593 inner_dest = XEXP (inner_dest, 0))
13596 /* Verify that it was the set, and not a clobber that
13597 modified the register.
13599 CC0 targets must be careful to maintain setter/user
13600 pairs. If we cannot delete the setter due to side
13601 effects, mark the user with an UNUSED note instead
13604 if (set != 0 && ! side_effects_p (SET_SRC (set))
13605 && rtx_equal_p (XEXP (note, 0), inner_dest)
13607 && (! reg_mentioned_p (cc0_rtx, SET_SRC (set))
13608 || ((cc0_setter = prev_cc0_setter (tem)) != NULL
13609 && sets_cc0_p (PATTERN (cc0_setter)) > 0))
13613 /* Move the notes and links of TEM elsewhere.
13614 This might delete other dead insns recursively.
13615 First set the pattern to something that won't use
13617 rtx old_notes = REG_NOTES (tem);
13619 PATTERN (tem) = pc_rtx;
13620 REG_NOTES (tem) = NULL;
13622 distribute_notes (old_notes, tem, tem, NULL_RTX,
13623 NULL_RTX, NULL_RTX, NULL_RTX);
13624 distribute_links (LOG_LINKS (tem));
13626 SET_INSN_DELETED (tem);
13631 /* Delete the setter too. */
13634 PATTERN (cc0_setter) = pc_rtx;
13635 old_notes = REG_NOTES (cc0_setter);
13636 REG_NOTES (cc0_setter) = NULL;
13638 distribute_notes (old_notes, cc0_setter,
13639 cc0_setter, NULL_RTX,
13640 NULL_RTX, NULL_RTX, NULL_RTX);
13641 distribute_links (LOG_LINKS (cc0_setter));
13643 SET_INSN_DELETED (cc0_setter);
13644 if (cc0_setter == i2)
13651 PUT_REG_NOTE_KIND (note, REG_UNUSED);
13653 /* If there isn't already a REG_UNUSED note, put one
13654 here. Do not place a REG_DEAD note, even if
13655 the register is also used here; that would not
13656 match the algorithm used in lifetime analysis
13657 and can cause the consistency check in the
13658 scheduler to fail. */
13659 if (! find_regno_note (tem, REG_UNUSED,
13660 REGNO (XEXP (note, 0))))
13665 else if (reg_referenced_p (XEXP (note, 0), PATTERN (tem))
13667 && find_reg_fusage (tem, USE, XEXP (note, 0))))
13671 /* If we are doing a 3->2 combination, and we have a
13672 register which formerly died in i3 and was not used
13673 by i2, which now no longer dies in i3 and is used in
13674 i2 but does not die in i2, and place is between i2
13675 and i3, then we may need to move a link from place to
13677 if (i2 && DF_INSN_LUID (place) > DF_INSN_LUID (i2)
13679 && DF_INSN_LUID (from_insn) > DF_INSN_LUID (i2)
13680 && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
13682 struct insn_link *links = LOG_LINKS (place);
13683 LOG_LINKS (place) = NULL;
13684 distribute_links (links);
13689 if (tem == BB_HEAD (bb))
13695 /* If the register is set or already dead at PLACE, we needn't do
13696 anything with this note if it is still a REG_DEAD note.
13697 We check here if it is set at all, not if is it totally replaced,
13698 which is what `dead_or_set_p' checks, so also check for it being
13701 if (place && REG_NOTE_KIND (note) == REG_DEAD)
13703 unsigned int regno = REGNO (XEXP (note, 0));
13704 reg_stat_type *rsp = VEC_index (reg_stat_type, reg_stat, regno);
13706 if (dead_or_set_p (place, XEXP (note, 0))
13707 || reg_bitfield_target_p (XEXP (note, 0), PATTERN (place)))
13709 /* Unless the register previously died in PLACE, clear
13710 last_death. [I no longer understand why this is
13712 if (rsp->last_death != place)
13713 rsp->last_death = 0;
13717 rsp->last_death = place;
13719 /* If this is a death note for a hard reg that is occupying
13720 multiple registers, ensure that we are still using all
13721 parts of the object. If we find a piece of the object
13722 that is unused, we must arrange for an appropriate REG_DEAD
13723 note to be added for it. However, we can't just emit a USE
13724 and tag the note to it, since the register might actually
13725 be dead; so we recourse, and the recursive call then finds
13726 the previous insn that used this register. */
13728 if (place && regno < FIRST_PSEUDO_REGISTER
13729 && hard_regno_nregs[regno][GET_MODE (XEXP (note, 0))] > 1)
13731 unsigned int endregno = END_HARD_REGNO (XEXP (note, 0));
13735 for (i = regno; i < endregno; i++)
13736 if ((! refers_to_regno_p (i, i + 1, PATTERN (place), 0)
13737 && ! find_regno_fusage (place, USE, i))
13738 || dead_or_set_regno_p (place, i))
13743 /* Put only REG_DEAD notes for pieces that are
13744 not already dead or set. */
13746 for (i = regno; i < endregno;
13747 i += hard_regno_nregs[i][reg_raw_mode[i]])
13749 rtx piece = regno_reg_rtx[i];
13750 basic_block bb = this_basic_block;
13752 if (! dead_or_set_p (place, piece)
13753 && ! reg_bitfield_target_p (piece,
13756 rtx new_note = alloc_reg_note (REG_DEAD, piece,
13759 distribute_notes (new_note, place, place,
13760 NULL_RTX, NULL_RTX, NULL_RTX,
13763 else if (! refers_to_regno_p (i, i + 1,
13764 PATTERN (place), 0)
13765 && ! find_regno_fusage (place, USE, i))
13766 for (tem = PREV_INSN (place); ;
13767 tem = PREV_INSN (tem))
13769 if (!NONDEBUG_INSN_P (tem))
13771 if (tem == BB_HEAD (bb))
13775 if (dead_or_set_p (tem, piece)
13776 || reg_bitfield_target_p (piece,
13779 add_reg_note (tem, REG_UNUSED, piece);
13793 /* Any other notes should not be present at this point in the
13795 gcc_unreachable ();
13800 XEXP (note, 1) = REG_NOTES (place);
13801 REG_NOTES (place) = note;
13805 add_reg_note (place2, REG_NOTE_KIND (note), XEXP (note, 0));
13809 /* Similarly to above, distribute the LOG_LINKS that used to be present on
13810 I3, I2, and I1 to new locations. This is also called to add a link
13811 pointing at I3 when I3's destination is changed. */
13814 distribute_links (struct insn_link *links)
13816 struct insn_link *link, *next_link;
13818 for (link = links; link; link = next_link)
13824 next_link = link->next;
13826 /* If the insn that this link points to is a NOTE or isn't a single
13827 set, ignore it. In the latter case, it isn't clear what we
13828 can do other than ignore the link, since we can't tell which
13829 register it was for. Such links wouldn't be used by combine
13832 It is not possible for the destination of the target of the link to
13833 have been changed by combine. The only potential of this is if we
13834 replace I3, I2, and I1 by I3 and I2. But in that case the
13835 destination of I2 also remains unchanged. */
13837 if (NOTE_P (link->insn)
13838 || (set = single_set (link->insn)) == 0)
13841 reg = SET_DEST (set);
13842 while (GET_CODE (reg) == SUBREG || GET_CODE (reg) == ZERO_EXTRACT
13843 || GET_CODE (reg) == STRICT_LOW_PART)
13844 reg = XEXP (reg, 0);
13846 /* A LOG_LINK is defined as being placed on the first insn that uses
13847 a register and points to the insn that sets the register. Start
13848 searching at the next insn after the target of the link and stop
13849 when we reach a set of the register or the end of the basic block.
13851 Note that this correctly handles the link that used to point from
13852 I3 to I2. Also note that not much searching is typically done here
13853 since most links don't point very far away. */
13855 for (insn = NEXT_INSN (link->insn);
13856 (insn && (this_basic_block->next_bb == EXIT_BLOCK_PTR
13857 || BB_HEAD (this_basic_block->next_bb) != insn));
13858 insn = NEXT_INSN (insn))
13859 if (DEBUG_INSN_P (insn))
13861 else if (INSN_P (insn) && reg_overlap_mentioned_p (reg, PATTERN (insn)))
13863 if (reg_referenced_p (reg, PATTERN (insn)))
13867 else if (CALL_P (insn)
13868 && find_reg_fusage (insn, USE, reg))
13873 else if (INSN_P (insn) && reg_set_p (reg, insn))
13876 /* If we found a place to put the link, place it there unless there
13877 is already a link to the same insn as LINK at that point. */
13881 struct insn_link *link2;
13883 FOR_EACH_LOG_LINK (link2, place)
13884 if (link2->insn == link->insn)
13889 link->next = LOG_LINKS (place);
13890 LOG_LINKS (place) = link;
13892 /* Set added_links_insn to the earliest insn we added a
13894 if (added_links_insn == 0
13895 || DF_INSN_LUID (added_links_insn) > DF_INSN_LUID (place))
13896 added_links_insn = place;
13902 /* Subroutine of unmentioned_reg_p and callback from for_each_rtx.
13903 Check whether the expression pointer to by LOC is a register or
13904 memory, and if so return 1 if it isn't mentioned in the rtx EXPR.
13905 Otherwise return zero. */
13908 unmentioned_reg_p_1 (rtx *loc, void *expr)
13913 && (REG_P (x) || MEM_P (x))
13914 && ! reg_mentioned_p (x, (rtx) expr))
13919 /* Check for any register or memory mentioned in EQUIV that is not
13920 mentioned in EXPR. This is used to restrict EQUIV to "specializations"
13921 of EXPR where some registers may have been replaced by constants. */
13924 unmentioned_reg_p (rtx equiv, rtx expr)
13926 return for_each_rtx (&equiv, unmentioned_reg_p_1, expr);
13930 dump_combine_stats (FILE *file)
13934 ";; Combiner statistics: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n\n",
13935 combine_attempts, combine_merges, combine_extras, combine_successes);
13939 dump_combine_total_stats (FILE *file)
13943 "\n;; Combiner totals: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n",
13944 total_attempts, total_merges, total_extras, total_successes);
13948 gate_handle_combine (void)
13950 return (optimize > 0);
13953 /* Try combining insns through substitution. */
13954 static unsigned int
13955 rest_of_handle_combine (void)
13957 int rebuild_jump_labels_after_combine;
13959 df_set_flags (DF_LR_RUN_DCE + DF_DEFER_INSN_RESCAN);
13960 df_note_add_problem ();
13963 regstat_init_n_sets_and_refs ();
13965 rebuild_jump_labels_after_combine
13966 = combine_instructions (get_insns (), max_reg_num ());
13968 /* Combining insns may have turned an indirect jump into a
13969 direct jump. Rebuild the JUMP_LABEL fields of jumping
13971 if (rebuild_jump_labels_after_combine)
13973 timevar_push (TV_JUMP);
13974 rebuild_jump_labels (get_insns ());
13976 timevar_pop (TV_JUMP);
13979 regstat_free_n_sets_and_refs ();
13983 struct rtl_opt_pass pass_combine =
13987 "combine", /* name */
13988 gate_handle_combine, /* gate */
13989 rest_of_handle_combine, /* execute */
13992 0, /* static_pass_number */
13993 TV_COMBINE, /* tv_id */
13994 PROP_cfglayout, /* properties_required */
13995 0, /* properties_provided */
13996 0, /* properties_destroyed */
13997 0, /* todo_flags_start */
13998 TODO_df_finish | TODO_verify_rtl_sharing |
13999 TODO_ggc_collect, /* todo_flags_finish */