1 /* Optimize by combining instructions for GNU compiler.
2 Copyright (C) 1987, 88, 92-96, 1997 Free Software Foundation, Inc.
4 This file is part of GNU CC.
6 GNU CC is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2, or (at your option)
11 GNU CC is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GNU CC; see the file COPYING. If not, write to
18 the Free Software Foundation, 59 Temple Place - Suite 330,
19 Boston, MA 02111-1307, USA. */
22 /* This module is essentially the "combiner" phase of the U. of Arizona
23 Portable Optimizer, but redone to work on our list-structured
24 representation for RTL instead of their string representation.
26 The LOG_LINKS of each insn identify the most recent assignment
27 to each REG used in the insn. It is a list of previous insns,
28 each of which contains a SET for a REG that is used in this insn
29 and not used or set in between. LOG_LINKs never cross basic blocks.
30 They were set up by the preceding pass (lifetime analysis).
32 We try to combine each pair of insns joined by a logical link.
33 We also try to combine triples of insns A, B and C when
34 C has a link back to B and B has a link back to A.
36 LOG_LINKS does not have links for use of the CC0. They don't
37 need to, because the insn that sets the CC0 is always immediately
38 before the insn that tests it. So we always regard a branch
39 insn as having a logical link to the preceding insn. The same is true
40 for an insn explicitly using CC0.
42 We check (with use_crosses_set_p) to avoid combining in such a way
43 as to move a computation to a place where its value would be different.
45 Combination is done by mathematically substituting the previous
46 insn(s) values for the regs they set into the expressions in
47 the later insns that refer to these regs. If the result is a valid insn
48 for our target machine, according to the machine description,
49 we install it, delete the earlier insns, and update the data flow
50 information (LOG_LINKS and REG_NOTES) for what we did.
52 There are a few exceptions where the dataflow information created by
53 flow.c aren't completely updated:
55 - reg_live_length is not updated
56 - reg_n_refs is not adjusted in the rare case when a register is
57 no longer required in a computation
58 - there are extremely rare cases (see distribute_regnotes) when a
60 - a LOG_LINKS entry that refers to an insn with multiple SETs may be
61 removed because there is no way to know which register it was
64 To simplify substitution, we combine only when the earlier insn(s)
65 consist of only a single assignment. To simplify updating afterward,
66 we never combine when a subroutine call appears in the middle.
68 Since we do not represent assignments to CC0 explicitly except when that
69 is all an insn does, there is no LOG_LINKS entry in an insn that uses
70 the condition code for the insn that set the condition code.
71 Fortunately, these two insns must be consecutive.
72 Therefore, every JUMP_INSN is taken to have an implicit logical link
73 to the preceding insn. This is not quite right, since non-jumps can
74 also use the condition code; but in practice such insns would not
84 /* Must precede rtl.h for FFS. */
90 #include "hard-reg-set.h"
92 #include "basic-block.h"
93 #include "insn-config.h"
94 #include "insn-flags.h"
95 #include "insn-codes.h"
96 #include "insn-attr.h"
100 /* It is not safe to use ordinary gen_lowpart in combine.
101 Use gen_lowpart_for_combine instead. See comments there. */
102 #define gen_lowpart dont_use_gen_lowpart_you_dummy
104 /* Number of attempts to combine instructions in this function. */
106 static int combine_attempts;
108 /* Number of attempts that got as far as substitution in this function. */
110 static int combine_merges;
112 /* Number of instructions combined with added SETs in this function. */
114 static int combine_extras;
116 /* Number of instructions combined in this function. */
118 static int combine_successes;
120 /* Totals over entire compilation. */
122 static int total_attempts, total_merges, total_extras, total_successes;
124 /* Define a default value for REVERSIBLE_CC_MODE.
125 We can never assume that a condition code mode is safe to reverse unless
126 the md tells us so. */
127 #ifndef REVERSIBLE_CC_MODE
128 #define REVERSIBLE_CC_MODE(MODE) 0
131 /* Vector mapping INSN_UIDs to cuids.
132 The cuids are like uids but increase monotonically always.
133 Combine always uses cuids so that it can compare them.
134 But actually renumbering the uids, which we used to do,
135 proves to be a bad idea because it makes it hard to compare
136 the dumps produced by earlier passes with those from later passes. */
138 static int *uid_cuid;
139 static int max_uid_cuid;
141 /* Get the cuid of an insn. */
143 #define INSN_CUID(INSN) \
144 (INSN_UID (INSN) > max_uid_cuid ? insn_cuid (INSN) : uid_cuid[INSN_UID (INSN)])
146 /* Maximum register number, which is the size of the tables below. */
148 static int combine_max_regno;
150 /* Record last point of death of (hard or pseudo) register n. */
152 static rtx *reg_last_death;
154 /* Record last point of modification of (hard or pseudo) register n. */
156 static rtx *reg_last_set;
158 /* Record the cuid of the last insn that invalidated memory
159 (anything that writes memory, and subroutine calls, but not pushes). */
161 static int mem_last_set;
163 /* Record the cuid of the last CALL_INSN
164 so we can tell whether a potential combination crosses any calls. */
166 static int last_call_cuid;
168 /* When `subst' is called, this is the insn that is being modified
169 (by combining in a previous insn). The PATTERN of this insn
170 is still the old pattern partially modified and it should not be
171 looked at, but this may be used to examine the successors of the insn
172 to judge whether a simplification is valid. */
174 static rtx subst_insn;
176 /* This is an insn that belongs before subst_insn, but is not currently
177 on the insn chain. */
179 static rtx subst_prev_insn;
181 /* This is the lowest CUID that `subst' is currently dealing with.
182 get_last_value will not return a value if the register was set at or
183 after this CUID. If not for this mechanism, we could get confused if
184 I2 or I1 in try_combine were an insn that used the old value of a register
185 to obtain a new value. In that case, we might erroneously get the
186 new value of the register when we wanted the old one. */
188 static int subst_low_cuid;
190 /* This contains any hard registers that are used in newpat; reg_dead_at_p
191 must consider all these registers to be always live. */
193 static HARD_REG_SET newpat_used_regs;
195 /* This is an insn to which a LOG_LINKS entry has been added. If this
196 insn is the earlier than I2 or I3, combine should rescan starting at
199 static rtx added_links_insn;
201 /* Basic block number of the block in which we are performing combines. */
202 static int this_basic_block;
204 /* The next group of arrays allows the recording of the last value assigned
205 to (hard or pseudo) register n. We use this information to see if a
206 operation being processed is redundant given a prior operation performed
207 on the register. For example, an `and' with a constant is redundant if
208 all the zero bits are already known to be turned off.
210 We use an approach similar to that used by cse, but change it in the
213 (1) We do not want to reinitialize at each label.
214 (2) It is useful, but not critical, to know the actual value assigned
215 to a register. Often just its form is helpful.
217 Therefore, we maintain the following arrays:
219 reg_last_set_value the last value assigned
220 reg_last_set_label records the value of label_tick when the
221 register was assigned
222 reg_last_set_table_tick records the value of label_tick when a
223 value using the register is assigned
224 reg_last_set_invalid set to non-zero when it is not valid
225 to use the value of this register in some
228 To understand the usage of these tables, it is important to understand
229 the distinction between the value in reg_last_set_value being valid
230 and the register being validly contained in some other expression in the
233 Entry I in reg_last_set_value is valid if it is non-zero, and either
234 reg_n_sets[i] is 1 or reg_last_set_label[i] == label_tick.
236 Register I may validly appear in any expression returned for the value
237 of another register if reg_n_sets[i] is 1. It may also appear in the
238 value for register J if reg_last_set_label[i] < reg_last_set_label[j] or
239 reg_last_set_invalid[j] is zero.
241 If an expression is found in the table containing a register which may
242 not validly appear in an expression, the register is replaced by
243 something that won't match, (clobber (const_int 0)).
245 reg_last_set_invalid[i] is set non-zero when register I is being assigned
246 to and reg_last_set_table_tick[i] == label_tick. */
248 /* Record last value assigned to (hard or pseudo) register n. */
250 static rtx *reg_last_set_value;
252 /* Record the value of label_tick when the value for register n is placed in
253 reg_last_set_value[n]. */
255 static int *reg_last_set_label;
257 /* Record the value of label_tick when an expression involving register n
258 is placed in reg_last_set_value. */
260 static int *reg_last_set_table_tick;
262 /* Set non-zero if references to register n in expressions should not be
265 static char *reg_last_set_invalid;
267 /* Incremented for each label. */
269 static int label_tick;
271 /* Some registers that are set more than once and used in more than one
272 basic block are nevertheless always set in similar ways. For example,
273 a QImode register may be loaded from memory in two places on a machine
274 where byte loads zero extend.
276 We record in the following array what we know about the nonzero
277 bits of a register, specifically which bits are known to be zero.
279 If an entry is zero, it means that we don't know anything special. */
281 static unsigned HOST_WIDE_INT *reg_nonzero_bits;
283 /* Mode used to compute significance in reg_nonzero_bits. It is the largest
284 integer mode that can fit in HOST_BITS_PER_WIDE_INT. */
286 static enum machine_mode nonzero_bits_mode;
288 /* Nonzero if we know that a register has some leading bits that are always
289 equal to the sign bit. */
291 static char *reg_sign_bit_copies;
293 /* Nonzero when reg_nonzero_bits and reg_sign_bit_copies can be safely used.
294 It is zero while computing them and after combine has completed. This
295 former test prevents propagating values based on previously set values,
296 which can be incorrect if a variable is modified in a loop. */
298 static int nonzero_sign_valid;
300 /* These arrays are maintained in parallel with reg_last_set_value
301 and are used to store the mode in which the register was last set,
302 the bits that were known to be zero when it was last set, and the
303 number of sign bits copies it was known to have when it was last set. */
305 static enum machine_mode *reg_last_set_mode;
306 static unsigned HOST_WIDE_INT *reg_last_set_nonzero_bits;
307 static char *reg_last_set_sign_bit_copies;
309 /* Record one modification to rtl structure
310 to be undone by storing old_contents into *where.
311 is_int is 1 if the contents are an int. */
317 union {rtx r; int i;} old_contents;
318 union {rtx *r; int *i;} where;
321 /* Record a bunch of changes to be undone, up to MAX_UNDO of them.
322 num_undo says how many are currently recorded.
324 storage is nonzero if we must undo the allocation of new storage.
325 The value of storage is what to pass to obfree.
327 other_insn is nonzero if we have modified some other insn in the process
328 of working on subst_insn. It must be verified too.
330 previous_undos is the value of undobuf.undos when we started processing
331 this substitution. This will prevent gen_rtx_combine from re-used a piece
332 from the previous expression. Doing so can produce circular rtl
340 struct undo *previous_undos;
344 static struct undobuf undobuf;
346 /* Substitute NEWVAL, an rtx expression, into INTO, a place in some
347 insn. The substitution can be undone by undo_all. If INTO is already
348 set to NEWVAL, do not record this change. Because computing NEWVAL might
349 also call SUBST, we have to compute it before we put anything into
352 #define SUBST(INTO, NEWVAL) \
353 do { rtx _new = (NEWVAL); \
357 _buf = undobuf.frees, undobuf.frees = _buf->next; \
359 _buf = (struct undo *) xmalloc (sizeof (struct undo)); \
362 _buf->where.r = &INTO; \
363 _buf->old_contents.r = INTO; \
365 if (_buf->old_contents.r == INTO) \
366 _buf->next = undobuf.frees, undobuf.frees = _buf; \
368 _buf->next = undobuf.undos, undobuf.undos = _buf; \
371 /* Similar to SUBST, but NEWVAL is an int expression. Note that substitution
372 for the value of a HOST_WIDE_INT value (including CONST_INT) is
375 #define SUBST_INT(INTO, NEWVAL) \
376 do { struct undo *_buf; \
379 _buf = undobuf.frees, undobuf.frees = _buf->next; \
381 _buf = (struct undo *) xmalloc (sizeof (struct undo)); \
384 _buf->where.i = (int *) &INTO; \
385 _buf->old_contents.i = INTO; \
387 if (_buf->old_contents.i == INTO) \
388 _buf->next = undobuf.frees, undobuf.frees = _buf; \
390 _buf->next = undobuf.undos, undobuf.undos = _buf; \
393 /* Number of times the pseudo being substituted for
394 was found and replaced. */
396 static int n_occurrences;
398 static void init_reg_last_arrays PROTO((void));
399 static void setup_incoming_promotions PROTO((void));
400 static void set_nonzero_bits_and_sign_copies PROTO((rtx, rtx));
401 static int can_combine_p PROTO((rtx, rtx, rtx, rtx, rtx *, rtx *));
402 static int combinable_i3pat PROTO((rtx, rtx *, rtx, rtx, int, rtx *));
403 static rtx try_combine PROTO((rtx, rtx, rtx));
404 static void undo_all PROTO((void));
405 static rtx *find_split_point PROTO((rtx *, rtx));
406 static rtx subst PROTO((rtx, rtx, rtx, int, int));
407 static rtx simplify_rtx PROTO((rtx, enum machine_mode, int, int));
408 static rtx simplify_if_then_else PROTO((rtx));
409 static rtx simplify_set PROTO((rtx));
410 static rtx simplify_logical PROTO((rtx, int));
411 static rtx expand_compound_operation PROTO((rtx));
412 static rtx expand_field_assignment PROTO((rtx));
413 static rtx make_extraction PROTO((enum machine_mode, rtx, int, rtx, int,
415 static rtx extract_left_shift PROTO((rtx, int));
416 static rtx make_compound_operation PROTO((rtx, enum rtx_code));
417 static int get_pos_from_mask PROTO((unsigned HOST_WIDE_INT, int *));
418 static rtx force_to_mode PROTO((rtx, enum machine_mode,
419 unsigned HOST_WIDE_INT, rtx, int));
420 static rtx if_then_else_cond PROTO((rtx, rtx *, rtx *));
421 static rtx known_cond PROTO((rtx, enum rtx_code, rtx, rtx));
422 static int rtx_equal_for_field_assignment_p PROTO((rtx, rtx));
423 static rtx make_field_assignment PROTO((rtx));
424 static rtx apply_distributive_law PROTO((rtx));
425 static rtx simplify_and_const_int PROTO((rtx, enum machine_mode, rtx,
426 unsigned HOST_WIDE_INT));
427 static unsigned HOST_WIDE_INT nonzero_bits PROTO((rtx, enum machine_mode));
428 static int num_sign_bit_copies PROTO((rtx, enum machine_mode));
429 static int merge_outer_ops PROTO((enum rtx_code *, HOST_WIDE_INT *,
430 enum rtx_code, HOST_WIDE_INT,
431 enum machine_mode, int *));
432 static rtx simplify_shift_const PROTO((rtx, enum rtx_code, enum machine_mode,
434 static int recog_for_combine PROTO((rtx *, rtx, rtx *, int *));
435 static rtx gen_lowpart_for_combine PROTO((enum machine_mode, rtx));
436 static rtx gen_rtx_combine PVPROTO((enum rtx_code code, enum machine_mode mode,
438 static rtx gen_binary PROTO((enum rtx_code, enum machine_mode,
440 static rtx gen_unary PROTO((enum rtx_code, enum machine_mode,
441 enum machine_mode, rtx));
442 static enum rtx_code simplify_comparison PROTO((enum rtx_code, rtx *, rtx *));
443 static int reversible_comparison_p PROTO((rtx));
444 static void update_table_tick PROTO((rtx));
445 static void record_value_for_reg PROTO((rtx, rtx, rtx));
446 static void record_dead_and_set_regs_1 PROTO((rtx, rtx));
447 static void record_dead_and_set_regs PROTO((rtx));
448 static int get_last_value_validate PROTO((rtx *, rtx, int, int));
449 static rtx get_last_value PROTO((rtx));
450 static int use_crosses_set_p PROTO((rtx, int));
451 static void reg_dead_at_p_1 PROTO((rtx, rtx));
452 static int reg_dead_at_p PROTO((rtx, rtx));
453 static void move_deaths PROTO((rtx, rtx, int, rtx, rtx *));
454 static int reg_bitfield_target_p PROTO((rtx, rtx));
455 static void distribute_notes PROTO((rtx, rtx, rtx, rtx, rtx, rtx));
456 static void distribute_links PROTO((rtx));
457 static void mark_used_regs_combine PROTO((rtx));
458 static int insn_cuid PROTO((rtx));
460 /* Main entry point for combiner. F is the first insn of the function.
461 NREGS is the first unused pseudo-reg number. */
464 combine_instructions (f, nregs)
468 register rtx insn, next, prev;
470 register rtx links, nextlinks;
472 combine_attempts = 0;
475 combine_successes = 0;
476 undobuf.undos = undobuf.previous_undos = 0;
478 combine_max_regno = nregs;
481 = (unsigned HOST_WIDE_INT *) alloca (nregs * sizeof (HOST_WIDE_INT));
482 reg_sign_bit_copies = (char *) alloca (nregs * sizeof (char));
484 bzero ((char *) reg_nonzero_bits, nregs * sizeof (HOST_WIDE_INT));
485 bzero (reg_sign_bit_copies, nregs * sizeof (char));
487 reg_last_death = (rtx *) alloca (nregs * sizeof (rtx));
488 reg_last_set = (rtx *) alloca (nregs * sizeof (rtx));
489 reg_last_set_value = (rtx *) alloca (nregs * sizeof (rtx));
490 reg_last_set_table_tick = (int *) alloca (nregs * sizeof (int));
491 reg_last_set_label = (int *) alloca (nregs * sizeof (int));
492 reg_last_set_invalid = (char *) alloca (nregs * sizeof (char));
494 = (enum machine_mode *) alloca (nregs * sizeof (enum machine_mode));
495 reg_last_set_nonzero_bits
496 = (unsigned HOST_WIDE_INT *) alloca (nregs * sizeof (HOST_WIDE_INT));
497 reg_last_set_sign_bit_copies
498 = (char *) alloca (nregs * sizeof (char));
500 init_reg_last_arrays ();
502 init_recog_no_volatile ();
504 /* Compute maximum uid value so uid_cuid can be allocated. */
506 for (insn = f, i = 0; insn; insn = NEXT_INSN (insn))
507 if (INSN_UID (insn) > i)
510 uid_cuid = (int *) alloca ((i + 1) * sizeof (int));
513 nonzero_bits_mode = mode_for_size (HOST_BITS_PER_WIDE_INT, MODE_INT, 0);
515 /* Don't use reg_nonzero_bits when computing it. This can cause problems
516 when, for example, we have j <<= 1 in a loop. */
518 nonzero_sign_valid = 0;
520 /* Compute the mapping from uids to cuids.
521 Cuids are numbers assigned to insns, like uids,
522 except that cuids increase monotonically through the code.
524 Scan all SETs and see if we can deduce anything about what
525 bits are known to be zero for some registers and how many copies
526 of the sign bit are known to exist for those registers.
528 Also set any known values so that we can use it while searching
529 for what bits are known to be set. */
533 /* We need to initialize it here, because record_dead_and_set_regs may call
535 subst_prev_insn = NULL_RTX;
537 setup_incoming_promotions ();
539 for (insn = f, i = 0; insn; insn = NEXT_INSN (insn))
541 uid_cuid[INSN_UID (insn)] = ++i;
545 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i')
547 note_stores (PATTERN (insn), set_nonzero_bits_and_sign_copies);
548 record_dead_and_set_regs (insn);
551 for (links = REG_NOTES (insn); links; links = XEXP (links, 1))
552 if (REG_NOTE_KIND (links) == REG_INC)
553 set_nonzero_bits_and_sign_copies (XEXP (links, 0), NULL_RTX);
557 if (GET_CODE (insn) == CODE_LABEL)
561 nonzero_sign_valid = 1;
563 /* Now scan all the insns in forward order. */
565 this_basic_block = -1;
569 init_reg_last_arrays ();
570 setup_incoming_promotions ();
572 for (insn = f; insn; insn = next ? next : NEXT_INSN (insn))
576 /* If INSN starts a new basic block, update our basic block number. */
577 if (this_basic_block + 1 < n_basic_blocks
578 && basic_block_head[this_basic_block + 1] == insn)
581 if (GET_CODE (insn) == CODE_LABEL)
584 else if (GET_RTX_CLASS (GET_CODE (insn)) == 'i')
586 /* Try this insn with each insn it links back to. */
588 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
589 if ((next = try_combine (insn, XEXP (links, 0), NULL_RTX)) != 0)
592 /* Try each sequence of three linked insns ending with this one. */
594 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
595 for (nextlinks = LOG_LINKS (XEXP (links, 0)); nextlinks;
596 nextlinks = XEXP (nextlinks, 1))
597 if ((next = try_combine (insn, XEXP (links, 0),
598 XEXP (nextlinks, 0))) != 0)
602 /* Try to combine a jump insn that uses CC0
603 with a preceding insn that sets CC0, and maybe with its
604 logical predecessor as well.
605 This is how we make decrement-and-branch insns.
606 We need this special code because data flow connections
607 via CC0 do not get entered in LOG_LINKS. */
609 if (GET_CODE (insn) == JUMP_INSN
610 && (prev = prev_nonnote_insn (insn)) != 0
611 && GET_CODE (prev) == INSN
612 && sets_cc0_p (PATTERN (prev)))
614 if ((next = try_combine (insn, prev, NULL_RTX)) != 0)
617 for (nextlinks = LOG_LINKS (prev); nextlinks;
618 nextlinks = XEXP (nextlinks, 1))
619 if ((next = try_combine (insn, prev,
620 XEXP (nextlinks, 0))) != 0)
624 /* Do the same for an insn that explicitly references CC0. */
625 if (GET_CODE (insn) == INSN
626 && (prev = prev_nonnote_insn (insn)) != 0
627 && GET_CODE (prev) == INSN
628 && sets_cc0_p (PATTERN (prev))
629 && GET_CODE (PATTERN (insn)) == SET
630 && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (insn))))
632 if ((next = try_combine (insn, prev, NULL_RTX)) != 0)
635 for (nextlinks = LOG_LINKS (prev); nextlinks;
636 nextlinks = XEXP (nextlinks, 1))
637 if ((next = try_combine (insn, prev,
638 XEXP (nextlinks, 0))) != 0)
642 /* Finally, see if any of the insns that this insn links to
643 explicitly references CC0. If so, try this insn, that insn,
644 and its predecessor if it sets CC0. */
645 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
646 if (GET_CODE (XEXP (links, 0)) == INSN
647 && GET_CODE (PATTERN (XEXP (links, 0))) == SET
648 && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (XEXP (links, 0))))
649 && (prev = prev_nonnote_insn (XEXP (links, 0))) != 0
650 && GET_CODE (prev) == INSN
651 && sets_cc0_p (PATTERN (prev))
652 && (next = try_combine (insn, XEXP (links, 0), prev)) != 0)
656 /* Try combining an insn with two different insns whose results it
658 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
659 for (nextlinks = XEXP (links, 1); nextlinks;
660 nextlinks = XEXP (nextlinks, 1))
661 if ((next = try_combine (insn, XEXP (links, 0),
662 XEXP (nextlinks, 0))) != 0)
665 if (GET_CODE (insn) != NOTE)
666 record_dead_and_set_regs (insn);
673 total_attempts += combine_attempts;
674 total_merges += combine_merges;
675 total_extras += combine_extras;
676 total_successes += combine_successes;
678 nonzero_sign_valid = 0;
681 /* Wipe the reg_last_xxx arrays in preparation for another pass. */
684 init_reg_last_arrays ()
686 int nregs = combine_max_regno;
688 bzero ((char *) reg_last_death, nregs * sizeof (rtx));
689 bzero ((char *) reg_last_set, nregs * sizeof (rtx));
690 bzero ((char *) reg_last_set_value, nregs * sizeof (rtx));
691 bzero ((char *) reg_last_set_table_tick, nregs * sizeof (int));
692 bzero ((char *) reg_last_set_label, nregs * sizeof (int));
693 bzero (reg_last_set_invalid, nregs * sizeof (char));
694 bzero ((char *) reg_last_set_mode, nregs * sizeof (enum machine_mode));
695 bzero ((char *) reg_last_set_nonzero_bits, nregs * sizeof (HOST_WIDE_INT));
696 bzero (reg_last_set_sign_bit_copies, nregs * sizeof (char));
699 /* Set up any promoted values for incoming argument registers. */
702 setup_incoming_promotions ()
704 #ifdef PROMOTE_FUNCTION_ARGS
707 enum machine_mode mode;
709 rtx first = get_insns ();
711 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
712 if (FUNCTION_ARG_REGNO_P (regno)
713 && (reg = promoted_input_arg (regno, &mode, &unsignedp)) != 0)
714 record_value_for_reg (reg, first,
715 gen_rtx (unsignedp ? ZERO_EXTEND : SIGN_EXTEND,
717 gen_rtx (CLOBBER, mode, const0_rtx)));
721 /* Called via note_stores. If X is a pseudo that is narrower than
722 HOST_BITS_PER_WIDE_INT and is being set, record what bits are known zero.
724 If we are setting only a portion of X and we can't figure out what
725 portion, assume all bits will be used since we don't know what will
728 Similarly, set how many bits of X are known to be copies of the sign bit
729 at all locations in the function. This is the smallest number implied
733 set_nonzero_bits_and_sign_copies (x, set)
739 if (GET_CODE (x) == REG
740 && REGNO (x) >= FIRST_PSEUDO_REGISTER
741 /* If this register is undefined at the start of the file, we can't
742 say what its contents were. */
743 && ! REGNO_REG_SET_P (basic_block_live_at_start[0], REGNO (x))
744 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT)
746 if (set == 0 || GET_CODE (set) == CLOBBER)
748 reg_nonzero_bits[REGNO (x)] = GET_MODE_MASK (GET_MODE (x));
749 reg_sign_bit_copies[REGNO (x)] = 1;
753 /* If this is a complex assignment, see if we can convert it into a
754 simple assignment. */
755 set = expand_field_assignment (set);
757 /* If this is a simple assignment, or we have a paradoxical SUBREG,
758 set what we know about X. */
760 if (SET_DEST (set) == x
761 || (GET_CODE (SET_DEST (set)) == SUBREG
762 && (GET_MODE_SIZE (GET_MODE (SET_DEST (set)))
763 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (set)))))
764 && SUBREG_REG (SET_DEST (set)) == x))
766 rtx src = SET_SRC (set);
768 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
769 /* If X is narrower than a word and SRC is a non-negative
770 constant that would appear negative in the mode of X,
771 sign-extend it for use in reg_nonzero_bits because some
772 machines (maybe most) will actually do the sign-extension
773 and this is the conservative approach.
775 ??? For 2.5, try to tighten up the MD files in this regard
776 instead of this kludge. */
778 if (GET_MODE_BITSIZE (GET_MODE (x)) < BITS_PER_WORD
779 && GET_CODE (src) == CONST_INT
781 && 0 != (INTVAL (src)
783 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
784 src = GEN_INT (INTVAL (src)
785 | ((HOST_WIDE_INT) (-1)
786 << GET_MODE_BITSIZE (GET_MODE (x))));
789 reg_nonzero_bits[REGNO (x)]
790 |= nonzero_bits (src, nonzero_bits_mode);
791 num = num_sign_bit_copies (SET_SRC (set), GET_MODE (x));
792 if (reg_sign_bit_copies[REGNO (x)] == 0
793 || reg_sign_bit_copies[REGNO (x)] > num)
794 reg_sign_bit_copies[REGNO (x)] = num;
798 reg_nonzero_bits[REGNO (x)] = GET_MODE_MASK (GET_MODE (x));
799 reg_sign_bit_copies[REGNO (x)] = 1;
804 /* See if INSN can be combined into I3. PRED and SUCC are optionally
805 insns that were previously combined into I3 or that will be combined
806 into the merger of INSN and I3.
808 Return 0 if the combination is not allowed for any reason.
810 If the combination is allowed, *PDEST will be set to the single
811 destination of INSN and *PSRC to the single source, and this function
815 can_combine_p (insn, i3, pred, succ, pdest, psrc)
822 rtx set = 0, src, dest;
824 int all_adjacent = (succ ? (next_active_insn (insn) == succ
825 && next_active_insn (succ) == i3)
826 : next_active_insn (insn) == i3);
828 /* Can combine only if previous insn is a SET of a REG, a SUBREG or CC0.
829 or a PARALLEL consisting of such a SET and CLOBBERs.
831 If INSN has CLOBBER parallel parts, ignore them for our processing.
832 By definition, these happen during the execution of the insn. When it
833 is merged with another insn, all bets are off. If they are, in fact,
834 needed and aren't also supplied in I3, they may be added by
835 recog_for_combine. Otherwise, it won't match.
837 We can also ignore a SET whose SET_DEST is mentioned in a REG_UNUSED
840 Get the source and destination of INSN. If more than one, can't
843 if (GET_CODE (PATTERN (insn)) == SET)
844 set = PATTERN (insn);
845 else if (GET_CODE (PATTERN (insn)) == PARALLEL
846 && GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == SET)
848 for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
850 rtx elt = XVECEXP (PATTERN (insn), 0, i);
852 switch (GET_CODE (elt))
854 /* We can ignore CLOBBERs. */
859 /* Ignore SETs whose result isn't used but not those that
860 have side-effects. */
861 if (find_reg_note (insn, REG_UNUSED, SET_DEST (elt))
862 && ! side_effects_p (elt))
865 /* If we have already found a SET, this is a second one and
866 so we cannot combine with this insn. */
874 /* Anything else means we can't combine. */
880 /* If SET_SRC is an ASM_OPERANDS we can't throw away these CLOBBERs,
881 so don't do anything with it. */
882 || GET_CODE (SET_SRC (set)) == ASM_OPERANDS)
891 set = expand_field_assignment (set);
892 src = SET_SRC (set), dest = SET_DEST (set);
894 /* Don't eliminate a store in the stack pointer. */
895 if (dest == stack_pointer_rtx
896 /* If we couldn't eliminate a field assignment, we can't combine. */
897 || GET_CODE (dest) == ZERO_EXTRACT || GET_CODE (dest) == STRICT_LOW_PART
898 /* Don't combine with an insn that sets a register to itself if it has
899 a REG_EQUAL note. This may be part of a REG_NO_CONFLICT sequence. */
900 || (rtx_equal_p (src, dest) && find_reg_note (insn, REG_EQUAL, NULL_RTX))
901 /* Can't merge a function call. */
902 || GET_CODE (src) == CALL
903 /* Don't eliminate a function call argument. */
904 || (GET_CODE (i3) == CALL_INSN
905 && (find_reg_fusage (i3, USE, dest)
906 || (GET_CODE (dest) == REG
907 && REGNO (dest) < FIRST_PSEUDO_REGISTER
908 && global_regs[REGNO (dest)])))
909 /* Don't substitute into an incremented register. */
910 || FIND_REG_INC_NOTE (i3, dest)
911 || (succ && FIND_REG_INC_NOTE (succ, dest))
912 /* Don't combine the end of a libcall into anything. */
913 || find_reg_note (insn, REG_RETVAL, NULL_RTX)
914 /* Make sure that DEST is not used after SUCC but before I3. */
915 || (succ && ! all_adjacent
916 && reg_used_between_p (dest, succ, i3))
917 /* Make sure that the value that is to be substituted for the register
918 does not use any registers whose values alter in between. However,
919 If the insns are adjacent, a use can't cross a set even though we
920 think it might (this can happen for a sequence of insns each setting
921 the same destination; reg_last_set of that register might point to
922 a NOTE). If INSN has a REG_EQUIV note, the register is always
923 equivalent to the memory so the substitution is valid even if there
924 are intervening stores. Also, don't move a volatile asm or
925 UNSPEC_VOLATILE across any other insns. */
927 && (((GET_CODE (src) != MEM
928 || ! find_reg_note (insn, REG_EQUIV, src))
929 && use_crosses_set_p (src, INSN_CUID (insn)))
930 || (GET_CODE (src) == ASM_OPERANDS && MEM_VOLATILE_P (src))
931 || GET_CODE (src) == UNSPEC_VOLATILE))
932 /* If there is a REG_NO_CONFLICT note for DEST in I3 or SUCC, we get
933 better register allocation by not doing the combine. */
934 || find_reg_note (i3, REG_NO_CONFLICT, dest)
935 || (succ && find_reg_note (succ, REG_NO_CONFLICT, dest))
936 /* Don't combine across a CALL_INSN, because that would possibly
937 change whether the life span of some REGs crosses calls or not,
938 and it is a pain to update that information.
939 Exception: if source is a constant, moving it later can't hurt.
940 Accept that special case, because it helps -fforce-addr a lot. */
941 || (INSN_CUID (insn) < last_call_cuid && ! CONSTANT_P (src)))
944 /* DEST must either be a REG or CC0. */
945 if (GET_CODE (dest) == REG)
947 /* If register alignment is being enforced for multi-word items in all
948 cases except for parameters, it is possible to have a register copy
949 insn referencing a hard register that is not allowed to contain the
950 mode being copied and which would not be valid as an operand of most
951 insns. Eliminate this problem by not combining with such an insn.
953 Also, on some machines we don't want to extend the life of a hard
956 This is the same test done in can_combine except that we don't test
957 if SRC is a CALL operation to permit a hard register with
958 SMALL_REGISTER_CLASSES, and that we have to take all_adjacent
961 if (GET_CODE (src) == REG
962 && ((REGNO (dest) < FIRST_PSEUDO_REGISTER
963 && ! HARD_REGNO_MODE_OK (REGNO (dest), GET_MODE (dest)))
964 /* Don't extend the life of a hard register unless it is
965 user variable (if we have few registers) or it can't
966 fit into the desired register (meaning something special
968 Also avoid substituting a return register into I3, because
969 reload can't handle a conflict with constraints of other
971 || (REGNO (src) < FIRST_PSEUDO_REGISTER
972 && (! HARD_REGNO_MODE_OK (REGNO (src), GET_MODE (src))
973 #ifdef SMALL_REGISTER_CLASSES
974 || (SMALL_REGISTER_CLASSES
975 && ((! all_adjacent && ! REG_USERVAR_P (src))
976 || (FUNCTION_VALUE_REGNO_P (REGNO (src))
977 && ! REG_USERVAR_P (src))))
982 else if (GET_CODE (dest) != CC0)
985 /* Don't substitute for a register intended as a clobberable operand.
986 Similarly, don't substitute an expression containing a register that
987 will be clobbered in I3. */
988 if (GET_CODE (PATTERN (i3)) == PARALLEL)
989 for (i = XVECLEN (PATTERN (i3), 0) - 1; i >= 0; i--)
990 if (GET_CODE (XVECEXP (PATTERN (i3), 0, i)) == CLOBBER
991 && (reg_overlap_mentioned_p (XEXP (XVECEXP (PATTERN (i3), 0, i), 0),
993 || rtx_equal_p (XEXP (XVECEXP (PATTERN (i3), 0, i), 0), dest)))
996 /* If INSN contains anything volatile, or is an `asm' (whether volatile
997 or not), reject, unless nothing volatile comes between it and I3,
998 with the exception of SUCC. */
1000 if (GET_CODE (src) == ASM_OPERANDS || volatile_refs_p (src))
1001 for (p = NEXT_INSN (insn); p != i3; p = NEXT_INSN (p))
1002 if (GET_RTX_CLASS (GET_CODE (p)) == 'i'
1003 && p != succ && volatile_refs_p (PATTERN (p)))
1006 /* If INSN is an asm, and DEST is a hard register, reject, since it has
1007 to be an explicit register variable, and was chosen for a reason. */
1009 if (GET_CODE (src) == ASM_OPERANDS
1010 && GET_CODE (dest) == REG && REGNO (dest) < FIRST_PSEUDO_REGISTER)
1013 /* If there are any volatile insns between INSN and I3, reject, because
1014 they might affect machine state. */
1016 for (p = NEXT_INSN (insn); p != i3; p = NEXT_INSN (p))
1017 if (GET_RTX_CLASS (GET_CODE (p)) == 'i'
1018 && p != succ && volatile_insn_p (PATTERN (p)))
1021 /* If INSN or I2 contains an autoincrement or autodecrement,
1022 make sure that register is not used between there and I3,
1023 and not already used in I3 either.
1024 Also insist that I3 not be a jump; if it were one
1025 and the incremented register were spilled, we would lose. */
1028 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
1029 if (REG_NOTE_KIND (link) == REG_INC
1030 && (GET_CODE (i3) == JUMP_INSN
1031 || reg_used_between_p (XEXP (link, 0), insn, i3)
1032 || reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i3))))
1037 /* Don't combine an insn that follows a CC0-setting insn.
1038 An insn that uses CC0 must not be separated from the one that sets it.
1039 We do, however, allow I2 to follow a CC0-setting insn if that insn
1040 is passed as I1; in that case it will be deleted also.
1041 We also allow combining in this case if all the insns are adjacent
1042 because that would leave the two CC0 insns adjacent as well.
1043 It would be more logical to test whether CC0 occurs inside I1 or I2,
1044 but that would be much slower, and this ought to be equivalent. */
1046 p = prev_nonnote_insn (insn);
1047 if (p && p != pred && GET_CODE (p) == INSN && sets_cc0_p (PATTERN (p))
1052 /* If we get here, we have passed all the tests and the combination is
1061 /* LOC is the location within I3 that contains its pattern or the component
1062 of a PARALLEL of the pattern. We validate that it is valid for combining.
1064 One problem is if I3 modifies its output, as opposed to replacing it
1065 entirely, we can't allow the output to contain I2DEST or I1DEST as doing
1066 so would produce an insn that is not equivalent to the original insns.
1070 (set (reg:DI 101) (reg:DI 100))
1071 (set (subreg:SI (reg:DI 101) 0) <foo>)
1073 This is NOT equivalent to:
1075 (parallel [(set (subreg:SI (reg:DI 100) 0) <foo>)
1076 (set (reg:DI 101) (reg:DI 100))])
1078 Not only does this modify 100 (in which case it might still be valid
1079 if 100 were dead in I2), it sets 101 to the ORIGINAL value of 100.
1081 We can also run into a problem if I2 sets a register that I1
1082 uses and I1 gets directly substituted into I3 (not via I2). In that
1083 case, we would be getting the wrong value of I2DEST into I3, so we
1084 must reject the combination. This case occurs when I2 and I1 both
1085 feed into I3, rather than when I1 feeds into I2, which feeds into I3.
1086 If I1_NOT_IN_SRC is non-zero, it means that finding I1 in the source
1087 of a SET must prevent combination from occurring.
1089 On machines where SMALL_REGISTER_CLASSES is defined, we don't combine
1090 if the destination of a SET is a hard register that isn't a user
1093 Before doing the above check, we first try to expand a field assignment
1094 into a set of logical operations.
1096 If PI3_DEST_KILLED is non-zero, it is a pointer to a location in which
1097 we place a register that is both set and used within I3. If more than one
1098 such register is detected, we fail.
1100 Return 1 if the combination is valid, zero otherwise. */
1103 combinable_i3pat (i3, loc, i2dest, i1dest, i1_not_in_src, pi3dest_killed)
1109 rtx *pi3dest_killed;
1113 if (GET_CODE (x) == SET)
1115 rtx set = expand_field_assignment (x);
1116 rtx dest = SET_DEST (set);
1117 rtx src = SET_SRC (set);
1118 rtx inner_dest = dest, inner_src = src;
1122 while (GET_CODE (inner_dest) == STRICT_LOW_PART
1123 || GET_CODE (inner_dest) == SUBREG
1124 || GET_CODE (inner_dest) == ZERO_EXTRACT)
1125 inner_dest = XEXP (inner_dest, 0);
1127 /* We probably don't need this any more now that LIMIT_RELOAD_CLASS
1130 while (GET_CODE (inner_src) == STRICT_LOW_PART
1131 || GET_CODE (inner_src) == SUBREG
1132 || GET_CODE (inner_src) == ZERO_EXTRACT)
1133 inner_src = XEXP (inner_src, 0);
1135 /* If it is better that two different modes keep two different pseudos,
1136 avoid combining them. This avoids producing the following pattern
1138 (set (subreg:SI (reg/v:QI 21) 0)
1139 (lshiftrt:SI (reg/v:SI 20)
1141 If that were made, reload could not handle the pair of
1142 reg 20/21, since it would try to get any GENERAL_REGS
1143 but some of them don't handle QImode. */
1145 if (rtx_equal_p (inner_src, i2dest)
1146 && GET_CODE (inner_dest) == REG
1147 && ! MODES_TIEABLE_P (GET_MODE (i2dest), GET_MODE (inner_dest)))
1151 /* Check for the case where I3 modifies its output, as
1153 if ((inner_dest != dest
1154 && (reg_overlap_mentioned_p (i2dest, inner_dest)
1155 || (i1dest && reg_overlap_mentioned_p (i1dest, inner_dest))))
1156 /* This is the same test done in can_combine_p except that we
1157 allow a hard register with SMALL_REGISTER_CLASSES if SRC is a
1159 Moreover, we can't test all_adjacent; we don't have to, since
1160 this instruction will stay in place, thus we are not considering
1161 to increase the lifetime of INNER_DEST. */
1162 || (GET_CODE (inner_dest) == REG
1163 && REGNO (inner_dest) < FIRST_PSEUDO_REGISTER
1164 && (! HARD_REGNO_MODE_OK (REGNO (inner_dest),
1165 GET_MODE (inner_dest))
1166 #ifdef SMALL_REGISTER_CLASSES
1167 || (SMALL_REGISTER_CLASSES
1168 && GET_CODE (src) != CALL && ! REG_USERVAR_P (inner_dest)
1169 && FUNCTION_VALUE_REGNO_P (REGNO (inner_dest)))
1172 || (i1_not_in_src && reg_overlap_mentioned_p (i1dest, src)))
1175 /* If DEST is used in I3, it is being killed in this insn,
1176 so record that for later.
1177 Never add REG_DEAD notes for the FRAME_POINTER_REGNUM or the
1178 STACK_POINTER_REGNUM, since these are always considered to be
1179 live. Similarly for ARG_POINTER_REGNUM if it is fixed. */
1180 if (pi3dest_killed && GET_CODE (dest) == REG
1181 && reg_referenced_p (dest, PATTERN (i3))
1182 && REGNO (dest) != FRAME_POINTER_REGNUM
1183 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
1184 && REGNO (dest) != HARD_FRAME_POINTER_REGNUM
1186 #if ARG_POINTER_REGNUM != FRAME_POINTER_REGNUM
1187 && (REGNO (dest) != ARG_POINTER_REGNUM
1188 || ! fixed_regs [REGNO (dest)])
1190 && REGNO (dest) != STACK_POINTER_REGNUM)
1192 if (*pi3dest_killed)
1195 *pi3dest_killed = dest;
1199 else if (GET_CODE (x) == PARALLEL)
1203 for (i = 0; i < XVECLEN (x, 0); i++)
1204 if (! combinable_i3pat (i3, &XVECEXP (x, 0, i), i2dest, i1dest,
1205 i1_not_in_src, pi3dest_killed))
1212 /* Try to combine the insns I1 and I2 into I3.
1213 Here I1 and I2 appear earlier than I3.
1214 I1 can be zero; then we combine just I2 into I3.
1216 It we are combining three insns and the resulting insn is not recognized,
1217 try splitting it into two insns. If that happens, I2 and I3 are retained
1218 and I1 is pseudo-deleted by turning it into a NOTE. Otherwise, I1 and I2
1221 Return 0 if the combination does not work. Then nothing is changed.
1222 If we did the combination, return the insn at which combine should
1226 try_combine (i3, i2, i1)
1227 register rtx i3, i2, i1;
1229 /* New patterns for I3 and I3, respectively. */
1230 rtx newpat, newi2pat = 0;
1231 /* Indicates need to preserve SET in I1 or I2 in I3 if it is not dead. */
1232 int added_sets_1, added_sets_2;
1233 /* Total number of SETs to put into I3. */
1235 /* Nonzero is I2's body now appears in I3. */
1237 /* INSN_CODEs for new I3, new I2, and user of condition code. */
1238 int insn_code_number, i2_code_number, other_code_number;
1239 /* Contains I3 if the destination of I3 is used in its source, which means
1240 that the old life of I3 is being killed. If that usage is placed into
1241 I2 and not in I3, a REG_DEAD note must be made. */
1242 rtx i3dest_killed = 0;
1243 /* SET_DEST and SET_SRC of I2 and I1. */
1244 rtx i2dest, i2src, i1dest = 0, i1src = 0;
1245 /* PATTERN (I2), or a copy of it in certain cases. */
1247 /* Indicates if I2DEST or I1DEST is in I2SRC or I1_SRC. */
1248 int i2dest_in_i2src = 0, i1dest_in_i1src = 0, i2dest_in_i1src = 0;
1249 int i1_feeds_i3 = 0;
1250 /* Notes that must be added to REG_NOTES in I3 and I2. */
1251 rtx new_i3_notes, new_i2_notes;
1252 /* Notes that we substituted I3 into I2 instead of the normal case. */
1253 int i3_subst_into_i2 = 0;
1254 /* Notes that I1, I2 or I3 is a MULT operation. */
1256 /* Number of clobbers of SCRATCH we had to add. */
1257 int i3_scratches = 0, i2_scratches = 0, other_scratches = 0;
1264 /* If any of I1, I2, and I3 isn't really an insn, we can't do anything.
1265 This can occur when flow deletes an insn that it has merged into an
1266 auto-increment address. We also can't do anything if I3 has a
1267 REG_LIBCALL note since we don't want to disrupt the contiguity of a
1270 if (GET_RTX_CLASS (GET_CODE (i3)) != 'i'
1271 || GET_RTX_CLASS (GET_CODE (i2)) != 'i'
1272 || (i1 && GET_RTX_CLASS (GET_CODE (i1)) != 'i')
1273 || find_reg_note (i3, REG_LIBCALL, NULL_RTX))
1278 undobuf.undos = undobuf.previous_undos = 0;
1279 undobuf.other_insn = 0;
1281 /* Save the current high-water-mark so we can free storage if we didn't
1282 accept this combination. */
1283 undobuf.storage = (char *) oballoc (0);
1285 /* Reset the hard register usage information. */
1286 CLEAR_HARD_REG_SET (newpat_used_regs);
1288 /* If I1 and I2 both feed I3, they can be in any order. To simplify the
1289 code below, set I1 to be the earlier of the two insns. */
1290 if (i1 && INSN_CUID (i1) > INSN_CUID (i2))
1291 temp = i1, i1 = i2, i2 = temp;
1293 added_links_insn = 0;
1295 /* First check for one important special-case that the code below will
1296 not handle. Namely, the case where I1 is zero, I2 has multiple sets,
1297 and I3 is a SET whose SET_SRC is a SET_DEST in I2. In that case,
1298 we may be able to replace that destination with the destination of I3.
1299 This occurs in the common code where we compute both a quotient and
1300 remainder into a structure, in which case we want to do the computation
1301 directly into the structure to avoid register-register copies.
1303 We make very conservative checks below and only try to handle the
1304 most common cases of this. For example, we only handle the case
1305 where I2 and I3 are adjacent to avoid making difficult register
1308 if (i1 == 0 && GET_CODE (i3) == INSN && GET_CODE (PATTERN (i3)) == SET
1309 && GET_CODE (SET_SRC (PATTERN (i3))) == REG
1310 && REGNO (SET_SRC (PATTERN (i3))) >= FIRST_PSEUDO_REGISTER
1311 #ifdef SMALL_REGISTER_CLASSES
1312 && (! SMALL_REGISTER_CLASSES
1313 || GET_CODE (SET_DEST (PATTERN (i3))) != REG
1314 || REGNO (SET_DEST (PATTERN (i3))) >= FIRST_PSEUDO_REGISTER
1315 || REG_USERVAR_P (SET_DEST (PATTERN (i3))))
1317 && find_reg_note (i3, REG_DEAD, SET_SRC (PATTERN (i3)))
1318 && GET_CODE (PATTERN (i2)) == PARALLEL
1319 && ! side_effects_p (SET_DEST (PATTERN (i3)))
1320 /* If the dest of I3 is a ZERO_EXTRACT or STRICT_LOW_PART, the code
1321 below would need to check what is inside (and reg_overlap_mentioned_p
1322 doesn't support those codes anyway). Don't allow those destinations;
1323 the resulting insn isn't likely to be recognized anyway. */
1324 && GET_CODE (SET_DEST (PATTERN (i3))) != ZERO_EXTRACT
1325 && GET_CODE (SET_DEST (PATTERN (i3))) != STRICT_LOW_PART
1326 && ! reg_overlap_mentioned_p (SET_SRC (PATTERN (i3)),
1327 SET_DEST (PATTERN (i3)))
1328 && next_real_insn (i2) == i3)
1330 rtx p2 = PATTERN (i2);
1332 /* Make sure that the destination of I3,
1333 which we are going to substitute into one output of I2,
1334 is not used within another output of I2. We must avoid making this:
1335 (parallel [(set (mem (reg 69)) ...)
1336 (set (reg 69) ...)])
1337 which is not well-defined as to order of actions.
1338 (Besides, reload can't handle output reloads for this.)
1340 The problem can also happen if the dest of I3 is a memory ref,
1341 if another dest in I2 is an indirect memory ref. */
1342 for (i = 0; i < XVECLEN (p2, 0); i++)
1343 if ((GET_CODE (XVECEXP (p2, 0, i)) == SET
1344 || GET_CODE (XVECEXP (p2, 0, i)) == CLOBBER)
1345 && reg_overlap_mentioned_p (SET_DEST (PATTERN (i3)),
1346 SET_DEST (XVECEXP (p2, 0, i))))
1349 if (i == XVECLEN (p2, 0))
1350 for (i = 0; i < XVECLEN (p2, 0); i++)
1351 if (SET_DEST (XVECEXP (p2, 0, i)) == SET_SRC (PATTERN (i3)))
1356 subst_low_cuid = INSN_CUID (i2);
1358 added_sets_2 = added_sets_1 = 0;
1359 i2dest = SET_SRC (PATTERN (i3));
1361 /* Replace the dest in I2 with our dest and make the resulting
1362 insn the new pattern for I3. Then skip to where we
1363 validate the pattern. Everything was set up above. */
1364 SUBST (SET_DEST (XVECEXP (p2, 0, i)),
1365 SET_DEST (PATTERN (i3)));
1368 i3_subst_into_i2 = 1;
1369 goto validate_replacement;
1374 /* If we have no I1 and I2 looks like:
1375 (parallel [(set (reg:CC X) (compare:CC OP (const_int 0)))
1377 make up a dummy I1 that is
1380 (set (reg:CC X) (compare:CC Y (const_int 0)))
1382 (We can ignore any trailing CLOBBERs.)
1384 This undoes a previous combination and allows us to match a branch-and-
1387 if (i1 == 0 && GET_CODE (PATTERN (i2)) == PARALLEL
1388 && XVECLEN (PATTERN (i2), 0) >= 2
1389 && GET_CODE (XVECEXP (PATTERN (i2), 0, 0)) == SET
1390 && (GET_MODE_CLASS (GET_MODE (SET_DEST (XVECEXP (PATTERN (i2), 0, 0))))
1392 && GET_CODE (SET_SRC (XVECEXP (PATTERN (i2), 0, 0))) == COMPARE
1393 && XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 1) == const0_rtx
1394 && GET_CODE (XVECEXP (PATTERN (i2), 0, 1)) == SET
1395 && GET_CODE (SET_DEST (XVECEXP (PATTERN (i2), 0, 1))) == REG
1396 && rtx_equal_p (XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 0),
1397 SET_SRC (XVECEXP (PATTERN (i2), 0, 1))))
1399 for (i = XVECLEN (PATTERN (i2), 0) - 1; i >= 2; i--)
1400 if (GET_CODE (XVECEXP (PATTERN (i2), 0, i)) != CLOBBER)
1405 /* We make I1 with the same INSN_UID as I2. This gives it
1406 the same INSN_CUID for value tracking. Our fake I1 will
1407 never appear in the insn stream so giving it the same INSN_UID
1408 as I2 will not cause a problem. */
1410 subst_prev_insn = i1
1411 = gen_rtx (INSN, VOIDmode, INSN_UID (i2), NULL_RTX, i2,
1412 XVECEXP (PATTERN (i2), 0, 1), -1, NULL_RTX, NULL_RTX);
1414 SUBST (PATTERN (i2), XVECEXP (PATTERN (i2), 0, 0));
1415 SUBST (XEXP (SET_SRC (PATTERN (i2)), 0),
1416 SET_DEST (PATTERN (i1)));
1421 /* Verify that I2 and I1 are valid for combining. */
1422 if (! can_combine_p (i2, i3, i1, NULL_RTX, &i2dest, &i2src)
1423 || (i1 && ! can_combine_p (i1, i3, NULL_RTX, i2, &i1dest, &i1src)))
1429 /* Record whether I2DEST is used in I2SRC and similarly for the other
1430 cases. Knowing this will help in register status updating below. */
1431 i2dest_in_i2src = reg_overlap_mentioned_p (i2dest, i2src);
1432 i1dest_in_i1src = i1 && reg_overlap_mentioned_p (i1dest, i1src);
1433 i2dest_in_i1src = i1 && reg_overlap_mentioned_p (i2dest, i1src);
1435 /* See if I1 directly feeds into I3. It does if I1DEST is not used
1437 i1_feeds_i3 = i1 && ! reg_overlap_mentioned_p (i1dest, i2src);
1439 /* Ensure that I3's pattern can be the destination of combines. */
1440 if (! combinable_i3pat (i3, &PATTERN (i3), i2dest, i1dest,
1441 i1 && i2dest_in_i1src && i1_feeds_i3,
1448 /* See if any of the insns is a MULT operation. Unless one is, we will
1449 reject a combination that is, since it must be slower. Be conservative
1451 if (GET_CODE (i2src) == MULT
1452 || (i1 != 0 && GET_CODE (i1src) == MULT)
1453 || (GET_CODE (PATTERN (i3)) == SET
1454 && GET_CODE (SET_SRC (PATTERN (i3))) == MULT))
1457 /* If I3 has an inc, then give up if I1 or I2 uses the reg that is inc'd.
1458 We used to do this EXCEPT in one case: I3 has a post-inc in an
1459 output operand. However, that exception can give rise to insns like
1461 which is a famous insn on the PDP-11 where the value of r3 used as the
1462 source was model-dependent. Avoid this sort of thing. */
1465 if (!(GET_CODE (PATTERN (i3)) == SET
1466 && GET_CODE (SET_SRC (PATTERN (i3))) == REG
1467 && GET_CODE (SET_DEST (PATTERN (i3))) == MEM
1468 && (GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_INC
1469 || GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_DEC)))
1470 /* It's not the exception. */
1473 for (link = REG_NOTES (i3); link; link = XEXP (link, 1))
1474 if (REG_NOTE_KIND (link) == REG_INC
1475 && (reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i2))
1477 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i1)))))
1484 /* See if the SETs in I1 or I2 need to be kept around in the merged
1485 instruction: whenever the value set there is still needed past I3.
1486 For the SETs in I2, this is easy: we see if I2DEST dies or is set in I3.
1488 For the SET in I1, we have two cases: If I1 and I2 independently
1489 feed into I3, the set in I1 needs to be kept around if I1DEST dies
1490 or is set in I3. Otherwise (if I1 feeds I2 which feeds I3), the set
1491 in I1 needs to be kept around unless I1DEST dies or is set in either
1492 I2 or I3. We can distinguish these cases by seeing if I2SRC mentions
1493 I1DEST. If so, we know I1 feeds into I2. */
1495 added_sets_2 = ! dead_or_set_p (i3, i2dest);
1498 = i1 && ! (i1_feeds_i3 ? dead_or_set_p (i3, i1dest)
1499 : (dead_or_set_p (i3, i1dest) || dead_or_set_p (i2, i1dest)));
1501 /* If the set in I2 needs to be kept around, we must make a copy of
1502 PATTERN (I2), so that when we substitute I1SRC for I1DEST in
1503 PATTERN (I2), we are only substituting for the original I1DEST, not into
1504 an already-substituted copy. This also prevents making self-referential
1505 rtx. If I2 is a PARALLEL, we just need the piece that assigns I2SRC to
1508 i2pat = (GET_CODE (PATTERN (i2)) == PARALLEL
1509 ? gen_rtx (SET, VOIDmode, i2dest, i2src)
1513 i2pat = copy_rtx (i2pat);
1517 /* Substitute in the latest insn for the regs set by the earlier ones. */
1519 maxreg = max_reg_num ();
1523 /* It is possible that the source of I2 or I1 may be performing an
1524 unneeded operation, such as a ZERO_EXTEND of something that is known
1525 to have the high part zero. Handle that case by letting subst look at
1526 the innermost one of them.
1528 Another way to do this would be to have a function that tries to
1529 simplify a single insn instead of merging two or more insns. We don't
1530 do this because of the potential of infinite loops and because
1531 of the potential extra memory required. However, doing it the way
1532 we are is a bit of a kludge and doesn't catch all cases.
1534 But only do this if -fexpensive-optimizations since it slows things down
1535 and doesn't usually win. */
1537 if (flag_expensive_optimizations)
1539 /* Pass pc_rtx so no substitutions are done, just simplifications.
1540 The cases that we are interested in here do not involve the few
1541 cases were is_replaced is checked. */
1544 subst_low_cuid = INSN_CUID (i1);
1545 i1src = subst (i1src, pc_rtx, pc_rtx, 0, 0);
1549 subst_low_cuid = INSN_CUID (i2);
1550 i2src = subst (i2src, pc_rtx, pc_rtx, 0, 0);
1553 undobuf.previous_undos = undobuf.undos;
1557 /* Many machines that don't use CC0 have insns that can both perform an
1558 arithmetic operation and set the condition code. These operations will
1559 be represented as a PARALLEL with the first element of the vector
1560 being a COMPARE of an arithmetic operation with the constant zero.
1561 The second element of the vector will set some pseudo to the result
1562 of the same arithmetic operation. If we simplify the COMPARE, we won't
1563 match such a pattern and so will generate an extra insn. Here we test
1564 for this case, where both the comparison and the operation result are
1565 needed, and make the PARALLEL by just replacing I2DEST in I3SRC with
1566 I2SRC. Later we will make the PARALLEL that contains I2. */
1568 if (i1 == 0 && added_sets_2 && GET_CODE (PATTERN (i3)) == SET
1569 && GET_CODE (SET_SRC (PATTERN (i3))) == COMPARE
1570 && XEXP (SET_SRC (PATTERN (i3)), 1) == const0_rtx
1571 && rtx_equal_p (XEXP (SET_SRC (PATTERN (i3)), 0), i2dest))
1574 enum machine_mode compare_mode;
1576 newpat = PATTERN (i3);
1577 SUBST (XEXP (SET_SRC (newpat), 0), i2src);
1581 #ifdef EXTRA_CC_MODES
1582 /* See if a COMPARE with the operand we substituted in should be done
1583 with the mode that is currently being used. If not, do the same
1584 processing we do in `subst' for a SET; namely, if the destination
1585 is used only once, try to replace it with a register of the proper
1586 mode and also replace the COMPARE. */
1587 if (undobuf.other_insn == 0
1588 && (cc_use = find_single_use (SET_DEST (newpat), i3,
1589 &undobuf.other_insn))
1590 && ((compare_mode = SELECT_CC_MODE (GET_CODE (*cc_use),
1592 != GET_MODE (SET_DEST (newpat))))
1594 int regno = REGNO (SET_DEST (newpat));
1595 rtx new_dest = gen_rtx (REG, compare_mode, regno);
1597 if (regno < FIRST_PSEUDO_REGISTER
1598 || (REG_N_SETS (regno) == 1 && ! added_sets_2
1599 && ! REG_USERVAR_P (SET_DEST (newpat))))
1601 if (regno >= FIRST_PSEUDO_REGISTER)
1602 SUBST (regno_reg_rtx[regno], new_dest);
1604 SUBST (SET_DEST (newpat), new_dest);
1605 SUBST (XEXP (*cc_use, 0), new_dest);
1606 SUBST (SET_SRC (newpat),
1607 gen_rtx_combine (COMPARE, compare_mode,
1608 i2src, const0_rtx));
1611 undobuf.other_insn = 0;
1618 n_occurrences = 0; /* `subst' counts here */
1620 /* If I1 feeds into I2 (not into I3) and I1DEST is in I1SRC, we
1621 need to make a unique copy of I2SRC each time we substitute it
1622 to avoid self-referential rtl. */
1624 subst_low_cuid = INSN_CUID (i2);
1625 newpat = subst (PATTERN (i3), i2dest, i2src, 0,
1626 ! i1_feeds_i3 && i1dest_in_i1src);
1627 undobuf.previous_undos = undobuf.undos;
1629 /* Record whether i2's body now appears within i3's body. */
1630 i2_is_used = n_occurrences;
1633 /* If we already got a failure, don't try to do more. Otherwise,
1634 try to substitute in I1 if we have it. */
1636 if (i1 && GET_CODE (newpat) != CLOBBER)
1638 /* Before we can do this substitution, we must redo the test done
1639 above (see detailed comments there) that ensures that I1DEST
1640 isn't mentioned in any SETs in NEWPAT that are field assignments. */
1642 if (! combinable_i3pat (NULL_RTX, &newpat, i1dest, NULL_RTX,
1650 subst_low_cuid = INSN_CUID (i1);
1651 newpat = subst (newpat, i1dest, i1src, 0, 0);
1652 undobuf.previous_undos = undobuf.undos;
1655 /* Fail if an autoincrement side-effect has been duplicated. Be careful
1656 to count all the ways that I2SRC and I1SRC can be used. */
1657 if ((FIND_REG_INC_NOTE (i2, NULL_RTX) != 0
1658 && i2_is_used + added_sets_2 > 1)
1659 || (i1 != 0 && FIND_REG_INC_NOTE (i1, NULL_RTX) != 0
1660 && (n_occurrences + added_sets_1 + (added_sets_2 && ! i1_feeds_i3)
1662 /* Fail if we tried to make a new register (we used to abort, but there's
1663 really no reason to). */
1664 || max_reg_num () != maxreg
1665 /* Fail if we couldn't do something and have a CLOBBER. */
1666 || GET_CODE (newpat) == CLOBBER
1667 /* Fail if this new pattern is a MULT and we didn't have one before
1668 at the outer level. */
1669 || (GET_CODE (newpat) == SET && GET_CODE (SET_SRC (newpat)) == MULT
1676 /* If the actions of the earlier insns must be kept
1677 in addition to substituting them into the latest one,
1678 we must make a new PARALLEL for the latest insn
1679 to hold additional the SETs. */
1681 if (added_sets_1 || added_sets_2)
1685 if (GET_CODE (newpat) == PARALLEL)
1687 rtvec old = XVEC (newpat, 0);
1688 total_sets = XVECLEN (newpat, 0) + added_sets_1 + added_sets_2;
1689 newpat = gen_rtx (PARALLEL, VOIDmode, rtvec_alloc (total_sets));
1690 bcopy ((char *) &old->elem[0], (char *) XVEC (newpat, 0)->elem,
1691 sizeof (old->elem[0]) * old->num_elem);
1696 total_sets = 1 + added_sets_1 + added_sets_2;
1697 newpat = gen_rtx (PARALLEL, VOIDmode, rtvec_alloc (total_sets));
1698 XVECEXP (newpat, 0, 0) = old;
1702 XVECEXP (newpat, 0, --total_sets)
1703 = (GET_CODE (PATTERN (i1)) == PARALLEL
1704 ? gen_rtx (SET, VOIDmode, i1dest, i1src) : PATTERN (i1));
1708 /* If there is no I1, use I2's body as is. We used to also not do
1709 the subst call below if I2 was substituted into I3,
1710 but that could lose a simplification. */
1712 XVECEXP (newpat, 0, --total_sets) = i2pat;
1714 /* See comment where i2pat is assigned. */
1715 XVECEXP (newpat, 0, --total_sets)
1716 = subst (i2pat, i1dest, i1src, 0, 0);
1720 /* We come here when we are replacing a destination in I2 with the
1721 destination of I3. */
1722 validate_replacement:
1724 /* Note which hard regs this insn has as inputs. */
1725 mark_used_regs_combine (newpat);
1727 /* Is the result of combination a valid instruction? */
1729 = recog_for_combine (&newpat, i3, &new_i3_notes, &i3_scratches);
1731 /* If the result isn't valid, see if it is a PARALLEL of two SETs where
1732 the second SET's destination is a register that is unused. In that case,
1733 we just need the first SET. This can occur when simplifying a divmod
1734 insn. We *must* test for this case here because the code below that
1735 splits two independent SETs doesn't handle this case correctly when it
1736 updates the register status. Also check the case where the first
1737 SET's destination is unused. That would not cause incorrect code, but
1738 does cause an unneeded insn to remain. */
1740 if (insn_code_number < 0 && GET_CODE (newpat) == PARALLEL
1741 && XVECLEN (newpat, 0) == 2
1742 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
1743 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
1744 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) == REG
1745 && find_reg_note (i3, REG_UNUSED, SET_DEST (XVECEXP (newpat, 0, 1)))
1746 && ! side_effects_p (SET_SRC (XVECEXP (newpat, 0, 1)))
1747 && asm_noperands (newpat) < 0)
1749 newpat = XVECEXP (newpat, 0, 0);
1751 = recog_for_combine (&newpat, i3, &new_i3_notes, &i3_scratches);
1754 else if (insn_code_number < 0 && GET_CODE (newpat) == PARALLEL
1755 && XVECLEN (newpat, 0) == 2
1756 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
1757 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
1758 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) == REG
1759 && find_reg_note (i3, REG_UNUSED, SET_DEST (XVECEXP (newpat, 0, 0)))
1760 && ! side_effects_p (SET_SRC (XVECEXP (newpat, 0, 0)))
1761 && asm_noperands (newpat) < 0)
1763 newpat = XVECEXP (newpat, 0, 1);
1765 = recog_for_combine (&newpat, i3, &new_i3_notes, &i3_scratches);
1768 /* If we were combining three insns and the result is a simple SET
1769 with no ASM_OPERANDS that wasn't recognized, try to split it into two
1770 insns. There are two ways to do this. It can be split using a
1771 machine-specific method (like when you have an addition of a large
1772 constant) or by combine in the function find_split_point. */
1774 if (i1 && insn_code_number < 0 && GET_CODE (newpat) == SET
1775 && asm_noperands (newpat) < 0)
1777 rtx m_split, *split;
1778 rtx ni2dest = i2dest;
1780 /* See if the MD file can split NEWPAT. If it can't, see if letting it
1781 use I2DEST as a scratch register will help. In the latter case,
1782 convert I2DEST to the mode of the source of NEWPAT if we can. */
1784 m_split = split_insns (newpat, i3);
1786 /* We can only use I2DEST as a scratch reg if it doesn't overlap any
1787 inputs of NEWPAT. */
1789 /* ??? If I2DEST is not safe, and I1DEST exists, then it would be
1790 possible to try that as a scratch reg. This would require adding
1791 more code to make it work though. */
1793 if (m_split == 0 && ! reg_overlap_mentioned_p (ni2dest, newpat))
1795 /* If I2DEST is a hard register or the only use of a pseudo,
1796 we can change its mode. */
1797 if (GET_MODE (SET_DEST (newpat)) != GET_MODE (i2dest)
1798 && GET_MODE (SET_DEST (newpat)) != VOIDmode
1799 && GET_CODE (i2dest) == REG
1800 && (REGNO (i2dest) < FIRST_PSEUDO_REGISTER
1801 || (REG_N_SETS (REGNO (i2dest)) == 1 && ! added_sets_2
1802 && ! REG_USERVAR_P (i2dest))))
1803 ni2dest = gen_rtx (REG, GET_MODE (SET_DEST (newpat)),
1806 m_split = split_insns (gen_rtx (PARALLEL, VOIDmode,
1807 gen_rtvec (2, newpat,
1814 if (m_split && GET_CODE (m_split) == SEQUENCE
1815 && XVECLEN (m_split, 0) == 2
1816 && (next_real_insn (i2) == i3
1817 || ! use_crosses_set_p (PATTERN (XVECEXP (m_split, 0, 0)),
1821 rtx newi3pat = PATTERN (XVECEXP (m_split, 0, 1));
1822 newi2pat = PATTERN (XVECEXP (m_split, 0, 0));
1824 i3set = single_set (XVECEXP (m_split, 0, 1));
1825 i2set = single_set (XVECEXP (m_split, 0, 0));
1827 /* In case we changed the mode of I2DEST, replace it in the
1828 pseudo-register table here. We can't do it above in case this
1829 code doesn't get executed and we do a split the other way. */
1831 if (REGNO (i2dest) >= FIRST_PSEUDO_REGISTER)
1832 SUBST (regno_reg_rtx[REGNO (i2dest)], ni2dest);
1834 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes,
1837 /* If I2 or I3 has multiple SETs, we won't know how to track
1838 register status, so don't use these insns. If I2's destination
1839 is used between I2 and I3, we also can't use these insns. */
1841 if (i2_code_number >= 0 && i2set && i3set
1842 && (next_real_insn (i2) == i3
1843 || ! reg_used_between_p (SET_DEST (i2set), i2, i3)))
1844 insn_code_number = recog_for_combine (&newi3pat, i3, &new_i3_notes,
1846 if (insn_code_number >= 0)
1849 /* It is possible that both insns now set the destination of I3.
1850 If so, we must show an extra use of it. */
1852 if (insn_code_number >= 0)
1854 rtx new_i3_dest = SET_DEST (i3set);
1855 rtx new_i2_dest = SET_DEST (i2set);
1857 while (GET_CODE (new_i3_dest) == ZERO_EXTRACT
1858 || GET_CODE (new_i3_dest) == STRICT_LOW_PART
1859 || GET_CODE (new_i3_dest) == SUBREG)
1860 new_i3_dest = XEXP (new_i3_dest, 0);
1862 while (GET_CODE (new_i2_dest) == ZERO_EXTRACT
1863 || GET_CODE (new_i2_dest) == STRICT_LOW_PART
1864 || GET_CODE (new_i2_dest) == SUBREG)
1865 new_i2_dest = XEXP (new_i2_dest, 0);
1867 if (GET_CODE (new_i3_dest) == REG
1868 && GET_CODE (new_i2_dest) == REG
1869 && REGNO (new_i3_dest) == REGNO (new_i2_dest))
1870 REG_N_SETS (REGNO (new_i2_dest))++;
1874 /* If we can split it and use I2DEST, go ahead and see if that
1875 helps things be recognized. Verify that none of the registers
1876 are set between I2 and I3. */
1877 if (insn_code_number < 0 && (split = find_split_point (&newpat, i3)) != 0
1879 && GET_CODE (i2dest) == REG
1881 /* We need I2DEST in the proper mode. If it is a hard register
1882 or the only use of a pseudo, we can change its mode. */
1883 && (GET_MODE (*split) == GET_MODE (i2dest)
1884 || GET_MODE (*split) == VOIDmode
1885 || REGNO (i2dest) < FIRST_PSEUDO_REGISTER
1886 || (REG_N_SETS (REGNO (i2dest)) == 1 && ! added_sets_2
1887 && ! REG_USERVAR_P (i2dest)))
1888 && (next_real_insn (i2) == i3
1889 || ! use_crosses_set_p (*split, INSN_CUID (i2)))
1890 /* We can't overwrite I2DEST if its value is still used by
1892 && ! reg_referenced_p (i2dest, newpat))
1894 rtx newdest = i2dest;
1895 enum rtx_code split_code = GET_CODE (*split);
1896 enum machine_mode split_mode = GET_MODE (*split);
1898 /* Get NEWDEST as a register in the proper mode. We have already
1899 validated that we can do this. */
1900 if (GET_MODE (i2dest) != split_mode && split_mode != VOIDmode)
1902 newdest = gen_rtx (REG, split_mode, REGNO (i2dest));
1904 if (REGNO (i2dest) >= FIRST_PSEUDO_REGISTER)
1905 SUBST (regno_reg_rtx[REGNO (i2dest)], newdest);
1908 /* If *SPLIT is a (mult FOO (const_int pow2)), convert it to
1909 an ASHIFT. This can occur if it was inside a PLUS and hence
1910 appeared to be a memory address. This is a kludge. */
1911 if (split_code == MULT
1912 && GET_CODE (XEXP (*split, 1)) == CONST_INT
1913 && (i = exact_log2 (INTVAL (XEXP (*split, 1)))) >= 0)
1915 SUBST (*split, gen_rtx_combine (ASHIFT, split_mode,
1916 XEXP (*split, 0), GEN_INT (i)));
1917 /* Update split_code because we may not have a multiply
1919 split_code = GET_CODE (*split);
1922 #ifdef INSN_SCHEDULING
1923 /* If *SPLIT is a paradoxical SUBREG, when we split it, it should
1924 be written as a ZERO_EXTEND. */
1925 if (split_code == SUBREG && GET_CODE (SUBREG_REG (*split)) == MEM)
1926 SUBST (*split, gen_rtx_combine (ZERO_EXTEND, split_mode,
1930 newi2pat = gen_rtx_combine (SET, VOIDmode, newdest, *split);
1931 SUBST (*split, newdest);
1933 = recog_for_combine (&newi2pat, i2, &new_i2_notes, &i2_scratches);
1935 /* If the split point was a MULT and we didn't have one before,
1936 don't use one now. */
1937 if (i2_code_number >= 0 && ! (split_code == MULT && ! have_mult))
1939 = recog_for_combine (&newpat, i3, &new_i3_notes, &i3_scratches);
1943 /* Check for a case where we loaded from memory in a narrow mode and
1944 then sign extended it, but we need both registers. In that case,
1945 we have a PARALLEL with both loads from the same memory location.
1946 We can split this into a load from memory followed by a register-register
1947 copy. This saves at least one insn, more if register allocation can
1950 We cannot do this if the destination of the second assignment is
1951 a register that we have already assumed is zero-extended. Similarly
1952 for a SUBREG of such a register. */
1954 else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0
1955 && GET_CODE (newpat) == PARALLEL
1956 && XVECLEN (newpat, 0) == 2
1957 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
1958 && GET_CODE (SET_SRC (XVECEXP (newpat, 0, 0))) == SIGN_EXTEND
1959 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
1960 && rtx_equal_p (SET_SRC (XVECEXP (newpat, 0, 1)),
1961 XEXP (SET_SRC (XVECEXP (newpat, 0, 0)), 0))
1962 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)),
1964 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
1965 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
1966 && ! (temp = SET_DEST (XVECEXP (newpat, 0, 1)),
1967 (GET_CODE (temp) == REG
1968 && reg_nonzero_bits[REGNO (temp)] != 0
1969 && GET_MODE_BITSIZE (GET_MODE (temp)) < BITS_PER_WORD
1970 && GET_MODE_BITSIZE (GET_MODE (temp)) < HOST_BITS_PER_INT
1971 && (reg_nonzero_bits[REGNO (temp)]
1972 != GET_MODE_MASK (word_mode))))
1973 && ! (GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) == SUBREG
1974 && (temp = SUBREG_REG (SET_DEST (XVECEXP (newpat, 0, 1))),
1975 (GET_CODE (temp) == REG
1976 && reg_nonzero_bits[REGNO (temp)] != 0
1977 && GET_MODE_BITSIZE (GET_MODE (temp)) < BITS_PER_WORD
1978 && GET_MODE_BITSIZE (GET_MODE (temp)) < HOST_BITS_PER_INT
1979 && (reg_nonzero_bits[REGNO (temp)]
1980 != GET_MODE_MASK (word_mode)))))
1981 && ! reg_overlap_mentioned_p (SET_DEST (XVECEXP (newpat, 0, 1)),
1982 SET_SRC (XVECEXP (newpat, 0, 1)))
1983 && ! find_reg_note (i3, REG_UNUSED,
1984 SET_DEST (XVECEXP (newpat, 0, 0))))
1988 newi2pat = XVECEXP (newpat, 0, 0);
1989 ni2dest = SET_DEST (XVECEXP (newpat, 0, 0));
1990 newpat = XVECEXP (newpat, 0, 1);
1991 SUBST (SET_SRC (newpat),
1992 gen_lowpart_for_combine (GET_MODE (SET_SRC (newpat)), ni2dest));
1994 = recog_for_combine (&newi2pat, i2, &new_i2_notes, &i2_scratches);
1996 if (i2_code_number >= 0)
1998 = recog_for_combine (&newpat, i3, &new_i3_notes, &i3_scratches);
2000 if (insn_code_number >= 0)
2005 /* If we will be able to accept this, we have made a change to the
2006 destination of I3. This can invalidate a LOG_LINKS pointing
2007 to I3. No other part of combine.c makes such a transformation.
2009 The new I3 will have a destination that was previously the
2010 destination of I1 or I2 and which was used in i2 or I3. Call
2011 distribute_links to make a LOG_LINK from the next use of
2012 that destination. */
2014 PATTERN (i3) = newpat;
2015 distribute_links (gen_rtx (INSN_LIST, VOIDmode, i3, NULL_RTX));
2017 /* I3 now uses what used to be its destination and which is
2018 now I2's destination. That means we need a LOG_LINK from
2019 I3 to I2. But we used to have one, so we still will.
2021 However, some later insn might be using I2's dest and have
2022 a LOG_LINK pointing at I3. We must remove this link.
2023 The simplest way to remove the link is to point it at I1,
2024 which we know will be a NOTE. */
2026 for (insn = NEXT_INSN (i3);
2027 insn && (this_basic_block == n_basic_blocks - 1
2028 || insn != basic_block_head[this_basic_block + 1]);
2029 insn = NEXT_INSN (insn))
2031 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i'
2032 && reg_referenced_p (ni2dest, PATTERN (insn)))
2034 for (link = LOG_LINKS (insn); link;
2035 link = XEXP (link, 1))
2036 if (XEXP (link, 0) == i3)
2037 XEXP (link, 0) = i1;
2045 /* Similarly, check for a case where we have a PARALLEL of two independent
2046 SETs but we started with three insns. In this case, we can do the sets
2047 as two separate insns. This case occurs when some SET allows two
2048 other insns to combine, but the destination of that SET is still live. */
2050 else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0
2051 && GET_CODE (newpat) == PARALLEL
2052 && XVECLEN (newpat, 0) == 2
2053 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
2054 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != ZERO_EXTRACT
2055 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != STRICT_LOW_PART
2056 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
2057 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
2058 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
2059 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)),
2061 /* Don't pass sets with (USE (MEM ...)) dests to the following. */
2062 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != USE
2063 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != USE
2064 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 1)),
2065 XVECEXP (newpat, 0, 0))
2066 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 0)),
2067 XVECEXP (newpat, 0, 1)))
2069 newi2pat = XVECEXP (newpat, 0, 1);
2070 newpat = XVECEXP (newpat, 0, 0);
2073 = recog_for_combine (&newi2pat, i2, &new_i2_notes, &i2_scratches);
2075 if (i2_code_number >= 0)
2077 = recog_for_combine (&newpat, i3, &new_i3_notes, &i3_scratches);
2080 /* If it still isn't recognized, fail and change things back the way they
2082 if ((insn_code_number < 0
2083 /* Is the result a reasonable ASM_OPERANDS? */
2084 && (! check_asm_operands (newpat) || added_sets_1 || added_sets_2)))
2090 /* If we had to change another insn, make sure it is valid also. */
2091 if (undobuf.other_insn)
2093 rtx other_pat = PATTERN (undobuf.other_insn);
2094 rtx new_other_notes;
2097 CLEAR_HARD_REG_SET (newpat_used_regs);
2100 = recog_for_combine (&other_pat, undobuf.other_insn,
2101 &new_other_notes, &other_scratches);
2103 if (other_code_number < 0 && ! check_asm_operands (other_pat))
2109 PATTERN (undobuf.other_insn) = other_pat;
2111 /* If any of the notes in OTHER_INSN were REG_UNUSED, ensure that they
2112 are still valid. Then add any non-duplicate notes added by
2113 recog_for_combine. */
2114 for (note = REG_NOTES (undobuf.other_insn); note; note = next)
2116 next = XEXP (note, 1);
2118 if (REG_NOTE_KIND (note) == REG_UNUSED
2119 && ! reg_set_p (XEXP (note, 0), PATTERN (undobuf.other_insn)))
2121 if (GET_CODE (XEXP (note, 0)) == REG)
2122 REG_N_DEATHS (REGNO (XEXP (note, 0)))--;
2124 remove_note (undobuf.other_insn, note);
2128 for (note = new_other_notes; note; note = XEXP (note, 1))
2129 if (GET_CODE (XEXP (note, 0)) == REG)
2130 REG_N_DEATHS (REGNO (XEXP (note, 0)))++;
2132 distribute_notes (new_other_notes, undobuf.other_insn,
2133 undobuf.other_insn, NULL_RTX, NULL_RTX, NULL_RTX);
2136 /* We now know that we can do this combination. Merge the insns and
2137 update the status of registers and LOG_LINKS. */
2140 rtx i3notes, i2notes, i1notes = 0;
2141 rtx i3links, i2links, i1links = 0;
2144 /* Compute which registers we expect to eliminate. */
2145 rtx elim_i2 = (newi2pat || i2dest_in_i2src || i2dest_in_i1src
2147 rtx elim_i1 = i1 == 0 || i1dest_in_i1src ? 0 : i1dest;
2149 /* Get the old REG_NOTES and LOG_LINKS from all our insns and
2151 i3notes = REG_NOTES (i3), i3links = LOG_LINKS (i3);
2152 i2notes = REG_NOTES (i2), i2links = LOG_LINKS (i2);
2154 i1notes = REG_NOTES (i1), i1links = LOG_LINKS (i1);
2156 /* Ensure that we do not have something that should not be shared but
2157 occurs multiple times in the new insns. Check this by first
2158 resetting all the `used' flags and then copying anything is shared. */
2160 reset_used_flags (i3notes);
2161 reset_used_flags (i2notes);
2162 reset_used_flags (i1notes);
2163 reset_used_flags (newpat);
2164 reset_used_flags (newi2pat);
2165 if (undobuf.other_insn)
2166 reset_used_flags (PATTERN (undobuf.other_insn));
2168 i3notes = copy_rtx_if_shared (i3notes);
2169 i2notes = copy_rtx_if_shared (i2notes);
2170 i1notes = copy_rtx_if_shared (i1notes);
2171 newpat = copy_rtx_if_shared (newpat);
2172 newi2pat = copy_rtx_if_shared (newi2pat);
2173 if (undobuf.other_insn)
2174 reset_used_flags (PATTERN (undobuf.other_insn));
2176 INSN_CODE (i3) = insn_code_number;
2177 PATTERN (i3) = newpat;
2178 if (undobuf.other_insn)
2179 INSN_CODE (undobuf.other_insn) = other_code_number;
2181 /* We had one special case above where I2 had more than one set and
2182 we replaced a destination of one of those sets with the destination
2183 of I3. In that case, we have to update LOG_LINKS of insns later
2184 in this basic block. Note that this (expensive) case is rare.
2186 Also, in this case, we must pretend that all REG_NOTEs for I2
2187 actually came from I3, so that REG_UNUSED notes from I2 will be
2188 properly handled. */
2190 if (i3_subst_into_i2)
2192 for (i = 0; i < XVECLEN (PATTERN (i2), 0); i++)
2193 if (GET_CODE (SET_DEST (XVECEXP (PATTERN (i2), 0, i))) == REG
2194 && SET_DEST (XVECEXP (PATTERN (i2), 0, i)) != i2dest
2195 && ! find_reg_note (i2, REG_UNUSED,
2196 SET_DEST (XVECEXP (PATTERN (i2), 0, i))))
2197 for (temp = NEXT_INSN (i2);
2198 temp && (this_basic_block == n_basic_blocks - 1
2199 || basic_block_head[this_basic_block] != temp);
2200 temp = NEXT_INSN (temp))
2201 if (temp != i3 && GET_RTX_CLASS (GET_CODE (temp)) == 'i')
2202 for (link = LOG_LINKS (temp); link; link = XEXP (link, 1))
2203 if (XEXP (link, 0) == i2)
2204 XEXP (link, 0) = i3;
2209 while (XEXP (link, 1))
2210 link = XEXP (link, 1);
2211 XEXP (link, 1) = i2notes;
2225 INSN_CODE (i2) = i2_code_number;
2226 PATTERN (i2) = newi2pat;
2230 PUT_CODE (i2, NOTE);
2231 NOTE_LINE_NUMBER (i2) = NOTE_INSN_DELETED;
2232 NOTE_SOURCE_FILE (i2) = 0;
2239 PUT_CODE (i1, NOTE);
2240 NOTE_LINE_NUMBER (i1) = NOTE_INSN_DELETED;
2241 NOTE_SOURCE_FILE (i1) = 0;
2244 /* Get death notes for everything that is now used in either I3 or
2245 I2 and used to die in a previous insn. If we built two new
2246 patterns, move from I1 to I2 then I2 to I3 so that we get the
2247 proper movement on registers that I2 modifies. */
2251 move_deaths (newi2pat, NULL_RTX, INSN_CUID (i1), i2, &midnotes);
2252 move_deaths (newpat, newi2pat, INSN_CUID (i1), i3, &midnotes);
2255 move_deaths (newpat, NULL_RTX, i1 ? INSN_CUID (i1) : INSN_CUID (i2),
2258 /* Distribute all the LOG_LINKS and REG_NOTES from I1, I2, and I3. */
2260 distribute_notes (i3notes, i3, i3, newi2pat ? i2 : NULL_RTX,
2263 distribute_notes (i2notes, i2, i3, newi2pat ? i2 : NULL_RTX,
2266 distribute_notes (i1notes, i1, i3, newi2pat ? i2 : NULL_RTX,
2269 distribute_notes (midnotes, NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
2272 /* Distribute any notes added to I2 or I3 by recog_for_combine. We
2273 know these are REG_UNUSED and want them to go to the desired insn,
2274 so we always pass it as i3. We have not counted the notes in
2275 reg_n_deaths yet, so we need to do so now. */
2277 if (newi2pat && new_i2_notes)
2279 for (temp = new_i2_notes; temp; temp = XEXP (temp, 1))
2280 if (GET_CODE (XEXP (temp, 0)) == REG)
2281 REG_N_DEATHS (REGNO (XEXP (temp, 0)))++;
2283 distribute_notes (new_i2_notes, i2, i2, NULL_RTX, NULL_RTX, NULL_RTX);
2288 for (temp = new_i3_notes; temp; temp = XEXP (temp, 1))
2289 if (GET_CODE (XEXP (temp, 0)) == REG)
2290 REG_N_DEATHS (REGNO (XEXP (temp, 0)))++;
2292 distribute_notes (new_i3_notes, i3, i3, NULL_RTX, NULL_RTX, NULL_RTX);
2295 /* If I3DEST was used in I3SRC, it really died in I3. We may need to
2296 put a REG_DEAD note for it somewhere. Similarly for I2 and I1.
2297 Show an additional death due to the REG_DEAD note we make here. If
2298 we discard it in distribute_notes, we will decrement it again. */
2302 if (GET_CODE (i3dest_killed) == REG)
2303 REG_N_DEATHS (REGNO (i3dest_killed))++;
2305 distribute_notes (gen_rtx (EXPR_LIST, REG_DEAD, i3dest_killed,
2307 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
2308 NULL_RTX, NULL_RTX);
2311 /* For I2 and I1, we have to be careful. If NEWI2PAT exists and sets
2312 I2DEST or I1DEST, the death must be somewhere before I2, not I3. If
2313 we passed I3 in that case, it might delete I2. */
2315 if (i2dest_in_i2src)
2317 if (GET_CODE (i2dest) == REG)
2318 REG_N_DEATHS (REGNO (i2dest))++;
2320 if (newi2pat && reg_set_p (i2dest, newi2pat))
2321 distribute_notes (gen_rtx (EXPR_LIST, REG_DEAD, i2dest, NULL_RTX),
2322 NULL_RTX, i2, NULL_RTX, NULL_RTX, NULL_RTX);
2324 distribute_notes (gen_rtx (EXPR_LIST, REG_DEAD, i2dest, NULL_RTX),
2325 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
2326 NULL_RTX, NULL_RTX);
2329 if (i1dest_in_i1src)
2331 if (GET_CODE (i1dest) == REG)
2332 REG_N_DEATHS (REGNO (i1dest))++;
2334 if (newi2pat && reg_set_p (i1dest, newi2pat))
2335 distribute_notes (gen_rtx (EXPR_LIST, REG_DEAD, i1dest, NULL_RTX),
2336 NULL_RTX, i2, NULL_RTX, NULL_RTX, NULL_RTX);
2338 distribute_notes (gen_rtx (EXPR_LIST, REG_DEAD, i1dest, NULL_RTX),
2339 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
2340 NULL_RTX, NULL_RTX);
2343 distribute_links (i3links);
2344 distribute_links (i2links);
2345 distribute_links (i1links);
2347 if (GET_CODE (i2dest) == REG)
2350 rtx i2_insn = 0, i2_val = 0, set;
2352 /* The insn that used to set this register doesn't exist, and
2353 this life of the register may not exist either. See if one of
2354 I3's links points to an insn that sets I2DEST. If it does,
2355 that is now the last known value for I2DEST. If we don't update
2356 this and I2 set the register to a value that depended on its old
2357 contents, we will get confused. If this insn is used, thing
2358 will be set correctly in combine_instructions. */
2360 for (link = LOG_LINKS (i3); link; link = XEXP (link, 1))
2361 if ((set = single_set (XEXP (link, 0))) != 0
2362 && rtx_equal_p (i2dest, SET_DEST (set)))
2363 i2_insn = XEXP (link, 0), i2_val = SET_SRC (set);
2365 record_value_for_reg (i2dest, i2_insn, i2_val);
2367 /* If the reg formerly set in I2 died only once and that was in I3,
2368 zero its use count so it won't make `reload' do any work. */
2370 && (newi2pat == 0 || ! reg_mentioned_p (i2dest, newi2pat))
2371 && ! i2dest_in_i2src)
2373 regno = REGNO (i2dest);
2374 REG_N_SETS (regno)--;
2375 if (REG_N_SETS (regno) == 0
2376 && ! REGNO_REG_SET_P (basic_block_live_at_start[0], regno))
2377 REG_N_REFS (regno) = 0;
2381 if (i1 && GET_CODE (i1dest) == REG)
2384 rtx i1_insn = 0, i1_val = 0, set;
2386 for (link = LOG_LINKS (i3); link; link = XEXP (link, 1))
2387 if ((set = single_set (XEXP (link, 0))) != 0
2388 && rtx_equal_p (i1dest, SET_DEST (set)))
2389 i1_insn = XEXP (link, 0), i1_val = SET_SRC (set);
2391 record_value_for_reg (i1dest, i1_insn, i1_val);
2393 regno = REGNO (i1dest);
2394 if (! added_sets_1 && ! i1dest_in_i1src)
2396 REG_N_SETS (regno)--;
2397 if (REG_N_SETS (regno) == 0
2398 && ! REGNO_REG_SET_P (basic_block_live_at_start[0], regno))
2399 REG_N_REFS (regno) = 0;
2403 /* Update reg_nonzero_bits et al for any changes that may have been made
2406 note_stores (newpat, set_nonzero_bits_and_sign_copies);
2408 note_stores (newi2pat, set_nonzero_bits_and_sign_copies);
2410 /* If we added any (clobber (scratch)), add them to the max for a
2411 block. This is a very pessimistic calculation, since we might
2412 have had them already and this might not be the worst block, but
2413 it's not worth doing any better. */
2414 max_scratch += i3_scratches + i2_scratches + other_scratches;
2416 /* If I3 is now an unconditional jump, ensure that it has a
2417 BARRIER following it since it may have initially been a
2418 conditional jump. It may also be the last nonnote insn. */
2420 if ((GET_CODE (newpat) == RETURN || simplejump_p (i3))
2421 && ((temp = next_nonnote_insn (i3)) == NULL_RTX
2422 || GET_CODE (temp) != BARRIER))
2423 emit_barrier_after (i3);
2426 combine_successes++;
2428 /* Clear this here, so that subsequent get_last_value calls are not
2430 subst_prev_insn = NULL_RTX;
2432 if (added_links_insn
2433 && (newi2pat == 0 || INSN_CUID (added_links_insn) < INSN_CUID (i2))
2434 && INSN_CUID (added_links_insn) < INSN_CUID (i3))
2435 return added_links_insn;
2437 return newi2pat ? i2 : i3;
2440 /* Undo all the modifications recorded in undobuf. */
2445 struct undo *undo, *next;
2447 for (undo = undobuf.undos; undo; undo = next)
2451 *undo->where.i = undo->old_contents.i;
2453 *undo->where.r = undo->old_contents.r;
2455 undo->next = undobuf.frees;
2456 undobuf.frees = undo;
2459 obfree (undobuf.storage);
2460 undobuf.undos = undobuf.previous_undos = 0;
2462 /* Clear this here, so that subsequent get_last_value calls are not
2464 subst_prev_insn = NULL_RTX;
2467 /* Find the innermost point within the rtx at LOC, possibly LOC itself,
2468 where we have an arithmetic expression and return that point. LOC will
2471 try_combine will call this function to see if an insn can be split into
2475 find_split_point (loc, insn)
2480 enum rtx_code code = GET_CODE (x);
2482 int len = 0, pos, unsignedp;
2485 /* First special-case some codes. */
2489 #ifdef INSN_SCHEDULING
2490 /* If we are making a paradoxical SUBREG invalid, it becomes a split
2492 if (GET_CODE (SUBREG_REG (x)) == MEM)
2495 return find_split_point (&SUBREG_REG (x), insn);
2499 /* If we have (mem (const ..)) or (mem (symbol_ref ...)), split it
2500 using LO_SUM and HIGH. */
2501 if (GET_CODE (XEXP (x, 0)) == CONST
2502 || GET_CODE (XEXP (x, 0)) == SYMBOL_REF)
2505 gen_rtx_combine (LO_SUM, Pmode,
2506 gen_rtx_combine (HIGH, Pmode, XEXP (x, 0)),
2508 return &XEXP (XEXP (x, 0), 0);
2512 /* If we have a PLUS whose second operand is a constant and the
2513 address is not valid, perhaps will can split it up using
2514 the machine-specific way to split large constants. We use
2515 the first pseudo-reg (one of the virtual regs) as a placeholder;
2516 it will not remain in the result. */
2517 if (GET_CODE (XEXP (x, 0)) == PLUS
2518 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
2519 && ! memory_address_p (GET_MODE (x), XEXP (x, 0)))
2521 rtx reg = regno_reg_rtx[FIRST_PSEUDO_REGISTER];
2522 rtx seq = split_insns (gen_rtx (SET, VOIDmode, reg, XEXP (x, 0)),
2525 /* This should have produced two insns, each of which sets our
2526 placeholder. If the source of the second is a valid address,
2527 we can make put both sources together and make a split point
2530 if (seq && XVECLEN (seq, 0) == 2
2531 && GET_CODE (XVECEXP (seq, 0, 0)) == INSN
2532 && GET_CODE (PATTERN (XVECEXP (seq, 0, 0))) == SET
2533 && SET_DEST (PATTERN (XVECEXP (seq, 0, 0))) == reg
2534 && ! reg_mentioned_p (reg,
2535 SET_SRC (PATTERN (XVECEXP (seq, 0, 0))))
2536 && GET_CODE (XVECEXP (seq, 0, 1)) == INSN
2537 && GET_CODE (PATTERN (XVECEXP (seq, 0, 1))) == SET
2538 && SET_DEST (PATTERN (XVECEXP (seq, 0, 1))) == reg
2539 && memory_address_p (GET_MODE (x),
2540 SET_SRC (PATTERN (XVECEXP (seq, 0, 1)))))
2542 rtx src1 = SET_SRC (PATTERN (XVECEXP (seq, 0, 0)));
2543 rtx src2 = SET_SRC (PATTERN (XVECEXP (seq, 0, 1)));
2545 /* Replace the placeholder in SRC2 with SRC1. If we can
2546 find where in SRC2 it was placed, that can become our
2547 split point and we can replace this address with SRC2.
2548 Just try two obvious places. */
2550 src2 = replace_rtx (src2, reg, src1);
2552 if (XEXP (src2, 0) == src1)
2553 split = &XEXP (src2, 0);
2554 else if (GET_RTX_FORMAT (GET_CODE (XEXP (src2, 0)))[0] == 'e'
2555 && XEXP (XEXP (src2, 0), 0) == src1)
2556 split = &XEXP (XEXP (src2, 0), 0);
2560 SUBST (XEXP (x, 0), src2);
2565 /* If that didn't work, perhaps the first operand is complex and
2566 needs to be computed separately, so make a split point there.
2567 This will occur on machines that just support REG + CONST
2568 and have a constant moved through some previous computation. */
2570 else if (GET_RTX_CLASS (GET_CODE (XEXP (XEXP (x, 0), 0))) != 'o'
2571 && ! (GET_CODE (XEXP (XEXP (x, 0), 0)) == SUBREG
2572 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (XEXP (x, 0), 0))))
2574 return &XEXP (XEXP (x, 0), 0);
2580 /* If SET_DEST is CC0 and SET_SRC is not an operand, a COMPARE, or a
2581 ZERO_EXTRACT, the most likely reason why this doesn't match is that
2582 we need to put the operand into a register. So split at that
2585 if (SET_DEST (x) == cc0_rtx
2586 && GET_CODE (SET_SRC (x)) != COMPARE
2587 && GET_CODE (SET_SRC (x)) != ZERO_EXTRACT
2588 && GET_RTX_CLASS (GET_CODE (SET_SRC (x))) != 'o'
2589 && ! (GET_CODE (SET_SRC (x)) == SUBREG
2590 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (SET_SRC (x)))) == 'o'))
2591 return &SET_SRC (x);
2594 /* See if we can split SET_SRC as it stands. */
2595 split = find_split_point (&SET_SRC (x), insn);
2596 if (split && split != &SET_SRC (x))
2599 /* See if we can split SET_DEST as it stands. */
2600 split = find_split_point (&SET_DEST (x), insn);
2601 if (split && split != &SET_DEST (x))
2604 /* See if this is a bitfield assignment with everything constant. If
2605 so, this is an IOR of an AND, so split it into that. */
2606 if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
2607 && (GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0)))
2608 <= HOST_BITS_PER_WIDE_INT)
2609 && GET_CODE (XEXP (SET_DEST (x), 1)) == CONST_INT
2610 && GET_CODE (XEXP (SET_DEST (x), 2)) == CONST_INT
2611 && GET_CODE (SET_SRC (x)) == CONST_INT
2612 && ((INTVAL (XEXP (SET_DEST (x), 1))
2613 + INTVAL (XEXP (SET_DEST (x), 2)))
2614 <= GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0))))
2615 && ! side_effects_p (XEXP (SET_DEST (x), 0)))
2617 int pos = INTVAL (XEXP (SET_DEST (x), 2));
2618 int len = INTVAL (XEXP (SET_DEST (x), 1));
2619 int src = INTVAL (SET_SRC (x));
2620 rtx dest = XEXP (SET_DEST (x), 0);
2621 enum machine_mode mode = GET_MODE (dest);
2622 unsigned HOST_WIDE_INT mask = ((HOST_WIDE_INT) 1 << len) - 1;
2624 if (BITS_BIG_ENDIAN)
2625 pos = GET_MODE_BITSIZE (mode) - len - pos;
2629 gen_binary (IOR, mode, dest, GEN_INT (src << pos)));
2632 gen_binary (IOR, mode,
2633 gen_binary (AND, mode, dest,
2634 GEN_INT (~ (mask << pos)
2635 & GET_MODE_MASK (mode))),
2636 GEN_INT (src << pos)));
2638 SUBST (SET_DEST (x), dest);
2640 split = find_split_point (&SET_SRC (x), insn);
2641 if (split && split != &SET_SRC (x))
2645 /* Otherwise, see if this is an operation that we can split into two.
2646 If so, try to split that. */
2647 code = GET_CODE (SET_SRC (x));
2652 /* If we are AND'ing with a large constant that is only a single
2653 bit and the result is only being used in a context where we
2654 need to know if it is zero or non-zero, replace it with a bit
2655 extraction. This will avoid the large constant, which might
2656 have taken more than one insn to make. If the constant were
2657 not a valid argument to the AND but took only one insn to make,
2658 this is no worse, but if it took more than one insn, it will
2661 if (GET_CODE (XEXP (SET_SRC (x), 1)) == CONST_INT
2662 && GET_CODE (XEXP (SET_SRC (x), 0)) == REG
2663 && (pos = exact_log2 (INTVAL (XEXP (SET_SRC (x), 1)))) >= 7
2664 && GET_CODE (SET_DEST (x)) == REG
2665 && (split = find_single_use (SET_DEST (x), insn, NULL_PTR)) != 0
2666 && (GET_CODE (*split) == EQ || GET_CODE (*split) == NE)
2667 && XEXP (*split, 0) == SET_DEST (x)
2668 && XEXP (*split, 1) == const0_rtx)
2670 rtx extraction = make_extraction (GET_MODE (SET_DEST (x)),
2671 XEXP (SET_SRC (x), 0),
2672 pos, NULL_RTX, 1, 1, 0, 0);
2673 if (extraction != 0)
2675 SUBST (SET_SRC (x), extraction);
2676 return find_split_point (loc, insn);
2682 /* if STORE_FLAG_VALUE is -1, this is (NE X 0) and only one bit of X
2683 is known to be on, this can be converted into a NEG of a shift. */
2684 if (STORE_FLAG_VALUE == -1 && XEXP (SET_SRC (x), 1) == const0_rtx
2685 && GET_MODE (SET_SRC (x)) == GET_MODE (XEXP (SET_SRC (x), 0))
2686 && 1 <= (pos = exact_log2
2687 (nonzero_bits (XEXP (SET_SRC (x), 0),
2688 GET_MODE (XEXP (SET_SRC (x), 0))))))
2690 enum machine_mode mode = GET_MODE (XEXP (SET_SRC (x), 0));
2693 gen_rtx_combine (NEG, mode,
2694 gen_rtx_combine (LSHIFTRT, mode,
2695 XEXP (SET_SRC (x), 0),
2698 split = find_split_point (&SET_SRC (x), insn);
2699 if (split && split != &SET_SRC (x))
2705 inner = XEXP (SET_SRC (x), 0);
2707 /* We can't optimize if either mode is a partial integer
2708 mode as we don't know how many bits are significant
2710 if (GET_MODE_CLASS (GET_MODE (inner)) == MODE_PARTIAL_INT
2711 || GET_MODE_CLASS (GET_MODE (SET_SRC (x))) == MODE_PARTIAL_INT)
2715 len = GET_MODE_BITSIZE (GET_MODE (inner));
2721 if (GET_CODE (XEXP (SET_SRC (x), 1)) == CONST_INT
2722 && GET_CODE (XEXP (SET_SRC (x), 2)) == CONST_INT)
2724 inner = XEXP (SET_SRC (x), 0);
2725 len = INTVAL (XEXP (SET_SRC (x), 1));
2726 pos = INTVAL (XEXP (SET_SRC (x), 2));
2728 if (BITS_BIG_ENDIAN)
2729 pos = GET_MODE_BITSIZE (GET_MODE (inner)) - len - pos;
2730 unsignedp = (code == ZERO_EXTRACT);
2735 if (len && pos >= 0 && pos + len <= GET_MODE_BITSIZE (GET_MODE (inner)))
2737 enum machine_mode mode = GET_MODE (SET_SRC (x));
2739 /* For unsigned, we have a choice of a shift followed by an
2740 AND or two shifts. Use two shifts for field sizes where the
2741 constant might be too large. We assume here that we can
2742 always at least get 8-bit constants in an AND insn, which is
2743 true for every current RISC. */
2745 if (unsignedp && len <= 8)
2750 gen_rtx_combine (LSHIFTRT, mode,
2751 gen_lowpart_for_combine (mode, inner),
2753 GEN_INT (((HOST_WIDE_INT) 1 << len) - 1)));
2755 split = find_split_point (&SET_SRC (x), insn);
2756 if (split && split != &SET_SRC (x))
2763 (unsignedp ? LSHIFTRT : ASHIFTRT, mode,
2764 gen_rtx_combine (ASHIFT, mode,
2765 gen_lowpart_for_combine (mode, inner),
2766 GEN_INT (GET_MODE_BITSIZE (mode)
2768 GEN_INT (GET_MODE_BITSIZE (mode) - len)));
2770 split = find_split_point (&SET_SRC (x), insn);
2771 if (split && split != &SET_SRC (x))
2776 /* See if this is a simple operation with a constant as the second
2777 operand. It might be that this constant is out of range and hence
2778 could be used as a split point. */
2779 if ((GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '2'
2780 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == 'c'
2781 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '<')
2782 && CONSTANT_P (XEXP (SET_SRC (x), 1))
2783 && (GET_RTX_CLASS (GET_CODE (XEXP (SET_SRC (x), 0))) == 'o'
2784 || (GET_CODE (XEXP (SET_SRC (x), 0)) == SUBREG
2785 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (SET_SRC (x), 0))))
2787 return &XEXP (SET_SRC (x), 1);
2789 /* Finally, see if this is a simple operation with its first operand
2790 not in a register. The operation might require this operand in a
2791 register, so return it as a split point. We can always do this
2792 because if the first operand were another operation, we would have
2793 already found it as a split point. */
2794 if ((GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '2'
2795 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == 'c'
2796 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '<'
2797 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '1')
2798 && ! register_operand (XEXP (SET_SRC (x), 0), VOIDmode))
2799 return &XEXP (SET_SRC (x), 0);
2805 /* We write NOR as (and (not A) (not B)), but if we don't have a NOR,
2806 it is better to write this as (not (ior A B)) so we can split it.
2807 Similarly for IOR. */
2808 if (GET_CODE (XEXP (x, 0)) == NOT && GET_CODE (XEXP (x, 1)) == NOT)
2811 gen_rtx_combine (NOT, GET_MODE (x),
2812 gen_rtx_combine (code == IOR ? AND : IOR,
2814 XEXP (XEXP (x, 0), 0),
2815 XEXP (XEXP (x, 1), 0))));
2816 return find_split_point (loc, insn);
2819 /* Many RISC machines have a large set of logical insns. If the
2820 second operand is a NOT, put it first so we will try to split the
2821 other operand first. */
2822 if (GET_CODE (XEXP (x, 1)) == NOT)
2824 rtx tem = XEXP (x, 0);
2825 SUBST (XEXP (x, 0), XEXP (x, 1));
2826 SUBST (XEXP (x, 1), tem);
2831 /* Otherwise, select our actions depending on our rtx class. */
2832 switch (GET_RTX_CLASS (code))
2834 case 'b': /* This is ZERO_EXTRACT and SIGN_EXTRACT. */
2836 split = find_split_point (&XEXP (x, 2), insn);
2839 /* ... fall through ... */
2843 split = find_split_point (&XEXP (x, 1), insn);
2846 /* ... fall through ... */
2848 /* Some machines have (and (shift ...) ...) insns. If X is not
2849 an AND, but XEXP (X, 0) is, use it as our split point. */
2850 if (GET_CODE (x) != AND && GET_CODE (XEXP (x, 0)) == AND)
2851 return &XEXP (x, 0);
2853 split = find_split_point (&XEXP (x, 0), insn);
2859 /* Otherwise, we don't have a split point. */
2863 /* Throughout X, replace FROM with TO, and return the result.
2864 The result is TO if X is FROM;
2865 otherwise the result is X, but its contents may have been modified.
2866 If they were modified, a record was made in undobuf so that
2867 undo_all will (among other things) return X to its original state.
2869 If the number of changes necessary is too much to record to undo,
2870 the excess changes are not made, so the result is invalid.
2871 The changes already made can still be undone.
2872 undobuf.num_undo is incremented for such changes, so by testing that
2873 the caller can tell whether the result is valid.
2875 `n_occurrences' is incremented each time FROM is replaced.
2877 IN_DEST is non-zero if we are processing the SET_DEST of a SET.
2879 UNIQUE_COPY is non-zero if each substitution must be unique. We do this
2880 by copying if `n_occurrences' is non-zero. */
2883 subst (x, from, to, in_dest, unique_copy)
2884 register rtx x, from, to;
2888 register enum rtx_code code = GET_CODE (x);
2889 enum machine_mode op0_mode = VOIDmode;
2891 register int len, i;
2894 /* Two expressions are equal if they are identical copies of a shared
2895 RTX or if they are both registers with the same register number
2898 #define COMBINE_RTX_EQUAL_P(X,Y) \
2900 || (GET_CODE (X) == REG && GET_CODE (Y) == REG \
2901 && REGNO (X) == REGNO (Y) && GET_MODE (X) == GET_MODE (Y)))
2903 if (! in_dest && COMBINE_RTX_EQUAL_P (x, from))
2906 return (unique_copy && n_occurrences > 1 ? copy_rtx (to) : to);
2909 /* If X and FROM are the same register but different modes, they will
2910 not have been seen as equal above. However, flow.c will make a
2911 LOG_LINKS entry for that case. If we do nothing, we will try to
2912 rerecognize our original insn and, when it succeeds, we will
2913 delete the feeding insn, which is incorrect.
2915 So force this insn not to match in this (rare) case. */
2916 if (! in_dest && code == REG && GET_CODE (from) == REG
2917 && REGNO (x) == REGNO (from))
2918 return gen_rtx (CLOBBER, GET_MODE (x), const0_rtx);
2920 /* If this is an object, we are done unless it is a MEM or LO_SUM, both
2921 of which may contain things that can be combined. */
2922 if (code != MEM && code != LO_SUM && GET_RTX_CLASS (code) == 'o')
2925 /* It is possible to have a subexpression appear twice in the insn.
2926 Suppose that FROM is a register that appears within TO.
2927 Then, after that subexpression has been scanned once by `subst',
2928 the second time it is scanned, TO may be found. If we were
2929 to scan TO here, we would find FROM within it and create a
2930 self-referent rtl structure which is completely wrong. */
2931 if (COMBINE_RTX_EQUAL_P (x, to))
2934 len = GET_RTX_LENGTH (code);
2935 fmt = GET_RTX_FORMAT (code);
2937 /* We don't need to process a SET_DEST that is a register, CC0, or PC, so
2938 set up to skip this common case. All other cases where we want to
2939 suppress replacing something inside a SET_SRC are handled via the
2942 && (GET_CODE (SET_DEST (x)) == REG
2943 || GET_CODE (SET_DEST (x)) == CC0
2944 || GET_CODE (SET_DEST (x)) == PC))
2947 /* Get the mode of operand 0 in case X is now a SIGN_EXTEND of a
2950 op0_mode = GET_MODE (XEXP (x, 0));
2952 for (i = 0; i < len; i++)
2957 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
2959 if (COMBINE_RTX_EQUAL_P (XVECEXP (x, i, j), from))
2961 new = (unique_copy && n_occurrences ? copy_rtx (to) : to);
2966 new = subst (XVECEXP (x, i, j), from, to, 0, unique_copy);
2968 /* If this substitution failed, this whole thing fails. */
2969 if (GET_CODE (new) == CLOBBER && XEXP (new, 0) == const0_rtx)
2973 SUBST (XVECEXP (x, i, j), new);
2976 else if (fmt[i] == 'e')
2978 if (COMBINE_RTX_EQUAL_P (XEXP (x, i), from))
2980 /* In general, don't install a subreg involving two modes not
2981 tieable. It can worsen register allocation, and can even
2982 make invalid reload insns, since the reg inside may need to
2983 be copied from in the outside mode, and that may be invalid
2984 if it is an fp reg copied in integer mode.
2986 We allow two exceptions to this: It is valid if it is inside
2987 another SUBREG and the mode of that SUBREG and the mode of
2988 the inside of TO is tieable and it is valid if X is a SET
2989 that copies FROM to CC0. */
2990 if (GET_CODE (to) == SUBREG
2991 && ! MODES_TIEABLE_P (GET_MODE (to),
2992 GET_MODE (SUBREG_REG (to)))
2993 && ! (code == SUBREG
2994 && MODES_TIEABLE_P (GET_MODE (x),
2995 GET_MODE (SUBREG_REG (to))))
2997 && ! (code == SET && i == 1 && XEXP (x, 0) == cc0_rtx)
3000 return gen_rtx (CLOBBER, VOIDmode, const0_rtx);
3002 new = (unique_copy && n_occurrences ? copy_rtx (to) : to);
3006 /* If we are in a SET_DEST, suppress most cases unless we
3007 have gone inside a MEM, in which case we want to
3008 simplify the address. We assume here that things that
3009 are actually part of the destination have their inner
3010 parts in the first expression. This is true for SUBREG,
3011 STRICT_LOW_PART, and ZERO_EXTRACT, which are the only
3012 things aside from REG and MEM that should appear in a
3014 new = subst (XEXP (x, i), from, to,
3016 && (code == SUBREG || code == STRICT_LOW_PART
3017 || code == ZERO_EXTRACT))
3019 && i == 0), unique_copy);
3021 /* If we found that we will have to reject this combination,
3022 indicate that by returning the CLOBBER ourselves, rather than
3023 an expression containing it. This will speed things up as
3024 well as prevent accidents where two CLOBBERs are considered
3025 to be equal, thus producing an incorrect simplification. */
3027 if (GET_CODE (new) == CLOBBER && XEXP (new, 0) == const0_rtx)
3030 SUBST (XEXP (x, i), new);
3034 /* Try to simplify X. If the simplification changed the code, it is likely
3035 that further simplification will help, so loop, but limit the number
3036 of repetitions that will be performed. */
3038 for (i = 0; i < 4; i++)
3040 /* If X is sufficiently simple, don't bother trying to do anything
3042 if (code != CONST_INT && code != REG && code != CLOBBER)
3043 x = simplify_rtx (x, op0_mode, i == 3, in_dest);
3045 if (GET_CODE (x) == code)
3048 code = GET_CODE (x);
3050 /* We no longer know the original mode of operand 0 since we
3051 have changed the form of X) */
3052 op0_mode = VOIDmode;
3058 /* Simplify X, a piece of RTL. We just operate on the expression at the
3059 outer level; call `subst' to simplify recursively. Return the new
3062 OP0_MODE is the original mode of XEXP (x, 0); LAST is nonzero if this
3063 will be the iteration even if an expression with a code different from
3064 X is returned; IN_DEST is nonzero if we are inside a SET_DEST. */
3067 simplify_rtx (x, op0_mode, last, in_dest)
3069 enum machine_mode op0_mode;
3073 enum rtx_code code = GET_CODE (x);
3074 enum machine_mode mode = GET_MODE (x);
3078 /* If this is a commutative operation, put a constant last and a complex
3079 expression first. We don't need to do this for comparisons here. */
3080 if (GET_RTX_CLASS (code) == 'c'
3081 && ((CONSTANT_P (XEXP (x, 0)) && GET_CODE (XEXP (x, 1)) != CONST_INT)
3082 || (GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == 'o'
3083 && GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) != 'o')
3084 || (GET_CODE (XEXP (x, 0)) == SUBREG
3085 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 0)))) == 'o'
3086 && GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) != 'o')))
3089 SUBST (XEXP (x, 0), XEXP (x, 1));
3090 SUBST (XEXP (x, 1), temp);
3093 /* If this is a PLUS, MINUS, or MULT, and the first operand is the
3094 sign extension of a PLUS with a constant, reverse the order of the sign
3095 extension and the addition. Note that this not the same as the original
3096 code, but overflow is undefined for signed values. Also note that the
3097 PLUS will have been partially moved "inside" the sign-extension, so that
3098 the first operand of X will really look like:
3099 (ashiftrt (plus (ashift A C4) C5) C4).
3101 (plus (ashiftrt (ashift A C4) C2) C4)
3102 and replace the first operand of X with that expression. Later parts
3103 of this function may simplify the expression further.
3105 For example, if we start with (mult (sign_extend (plus A C1)) C2),
3106 we swap the SIGN_EXTEND and PLUS. Later code will apply the
3107 distributive law to produce (plus (mult (sign_extend X) C1) C3).
3109 We do this to simplify address expressions. */
3111 if ((code == PLUS || code == MINUS || code == MULT)
3112 && GET_CODE (XEXP (x, 0)) == ASHIFTRT
3113 && GET_CODE (XEXP (XEXP (x, 0), 0)) == PLUS
3114 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == ASHIFT
3115 && GET_CODE (XEXP (XEXP (XEXP (XEXP (x, 0), 0), 0), 1)) == CONST_INT
3116 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3117 && XEXP (XEXP (XEXP (XEXP (x, 0), 0), 0), 1) == XEXP (XEXP (x, 0), 1)
3118 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == CONST_INT
3119 && (temp = simplify_binary_operation (ASHIFTRT, mode,
3120 XEXP (XEXP (XEXP (x, 0), 0), 1),
3121 XEXP (XEXP (x, 0), 1))) != 0)
3124 = simplify_shift_const (NULL_RTX, ASHIFT, mode,
3125 XEXP (XEXP (XEXP (XEXP (x, 0), 0), 0), 0),
3126 INTVAL (XEXP (XEXP (x, 0), 1)));
3128 new = simplify_shift_const (NULL_RTX, ASHIFTRT, mode, new,
3129 INTVAL (XEXP (XEXP (x, 0), 1)));
3131 SUBST (XEXP (x, 0), gen_binary (PLUS, mode, new, temp));
3134 /* If this is a simple operation applied to an IF_THEN_ELSE, try
3135 applying it to the arms of the IF_THEN_ELSE. This often simplifies
3136 things. Check for cases where both arms are testing the same
3139 Don't do anything if all operands are very simple. */
3141 if (((GET_RTX_CLASS (code) == '2' || GET_RTX_CLASS (code) == 'c'
3142 || GET_RTX_CLASS (code) == '<')
3143 && ((GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) != 'o'
3144 && ! (GET_CODE (XEXP (x, 0)) == SUBREG
3145 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 0))))
3147 || (GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) != 'o'
3148 && ! (GET_CODE (XEXP (x, 1)) == SUBREG
3149 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 1))))
3151 || (GET_RTX_CLASS (code) == '1'
3152 && ((GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) != 'o'
3153 && ! (GET_CODE (XEXP (x, 0)) == SUBREG
3154 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 0))))
3157 rtx cond, true, false;
3159 cond = if_then_else_cond (x, &true, &false);
3161 /* If everything is a comparison, what we have is highly unlikely
3162 to be simpler, so don't use it. */
3163 && ! (GET_RTX_CLASS (code) == '<'
3164 && (GET_RTX_CLASS (GET_CODE (true)) == '<'
3165 || GET_RTX_CLASS (GET_CODE (false)) == '<')))
3167 rtx cop1 = const0_rtx;
3168 enum rtx_code cond_code = simplify_comparison (NE, &cond, &cop1);
3170 if (cond_code == NE && GET_RTX_CLASS (GET_CODE (cond)) == '<')
3173 /* Simplify the alternative arms; this may collapse the true and
3174 false arms to store-flag values. */
3175 true = subst (true, pc_rtx, pc_rtx, 0, 0);
3176 false = subst (false, pc_rtx, pc_rtx, 0, 0);
3178 /* Restarting if we generate a store-flag expression will cause
3179 us to loop. Just drop through in this case. */
3181 /* If the result values are STORE_FLAG_VALUE and zero, we can
3182 just make the comparison operation. */
3183 if (true == const_true_rtx && false == const0_rtx)
3184 x = gen_binary (cond_code, mode, cond, cop1);
3185 else if (true == const0_rtx && false == const_true_rtx)
3186 x = gen_binary (reverse_condition (cond_code), mode, cond, cop1);
3188 /* Likewise, we can make the negate of a comparison operation
3189 if the result values are - STORE_FLAG_VALUE and zero. */
3190 else if (GET_CODE (true) == CONST_INT
3191 && INTVAL (true) == - STORE_FLAG_VALUE
3192 && false == const0_rtx)
3193 x = gen_unary (NEG, mode, mode,
3194 gen_binary (cond_code, mode, cond, cop1));
3195 else if (GET_CODE (false) == CONST_INT
3196 && INTVAL (false) == - STORE_FLAG_VALUE
3197 && true == const0_rtx)
3198 x = gen_unary (NEG, mode, mode,
3199 gen_binary (reverse_condition (cond_code),
3202 return gen_rtx (IF_THEN_ELSE, mode,
3203 gen_binary (cond_code, VOIDmode, cond, cop1),
3206 code = GET_CODE (x);
3207 op0_mode = VOIDmode;
3211 /* Try to fold this expression in case we have constants that weren't
3214 switch (GET_RTX_CLASS (code))
3217 temp = simplify_unary_operation (code, mode, XEXP (x, 0), op0_mode);
3220 temp = simplify_relational_operation (code, op0_mode,
3221 XEXP (x, 0), XEXP (x, 1));
3222 #ifdef FLOAT_STORE_FLAG_VALUE
3223 if (temp != 0 && GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
3224 temp = ((temp == const0_rtx) ? CONST0_RTX (GET_MODE (x))
3225 : immed_real_const_1 (FLOAT_STORE_FLAG_VALUE, GET_MODE (x)));
3230 temp = simplify_binary_operation (code, mode, XEXP (x, 0), XEXP (x, 1));
3234 temp = simplify_ternary_operation (code, mode, op0_mode, XEXP (x, 0),
3235 XEXP (x, 1), XEXP (x, 2));
3240 x = temp, code = GET_CODE (temp);
3242 /* First see if we can apply the inverse distributive law. */
3243 if (code == PLUS || code == MINUS
3244 || code == AND || code == IOR || code == XOR)
3246 x = apply_distributive_law (x);
3247 code = GET_CODE (x);
3250 /* If CODE is an associative operation not otherwise handled, see if we
3251 can associate some operands. This can win if they are constants or
3252 if they are logically related (i.e. (a & b) & a. */
3253 if ((code == PLUS || code == MINUS
3254 || code == MULT || code == AND || code == IOR || code == XOR
3255 || code == DIV || code == UDIV
3256 || code == SMAX || code == SMIN || code == UMAX || code == UMIN)
3257 && INTEGRAL_MODE_P (mode))
3259 if (GET_CODE (XEXP (x, 0)) == code)
3261 rtx other = XEXP (XEXP (x, 0), 0);
3262 rtx inner_op0 = XEXP (XEXP (x, 0), 1);
3263 rtx inner_op1 = XEXP (x, 1);
3266 /* Make sure we pass the constant operand if any as the second
3267 one if this is a commutative operation. */
3268 if (CONSTANT_P (inner_op0) && GET_RTX_CLASS (code) == 'c')
3270 rtx tem = inner_op0;
3271 inner_op0 = inner_op1;
3274 inner = simplify_binary_operation (code == MINUS ? PLUS
3275 : code == DIV ? MULT
3276 : code == UDIV ? MULT
3278 mode, inner_op0, inner_op1);
3280 /* For commutative operations, try the other pair if that one
3282 if (inner == 0 && GET_RTX_CLASS (code) == 'c')
3284 other = XEXP (XEXP (x, 0), 1);
3285 inner = simplify_binary_operation (code, mode,
3286 XEXP (XEXP (x, 0), 0),
3291 return gen_binary (code, mode, other, inner);
3295 /* A little bit of algebraic simplification here. */
3299 /* Ensure that our address has any ASHIFTs converted to MULT in case
3300 address-recognizing predicates are called later. */
3301 temp = make_compound_operation (XEXP (x, 0), MEM);
3302 SUBST (XEXP (x, 0), temp);
3306 /* (subreg:A (mem:B X) N) becomes a modified MEM unless the SUBREG
3307 is paradoxical. If we can't do that safely, then it becomes
3308 something nonsensical so that this combination won't take place. */
3310 if (GET_CODE (SUBREG_REG (x)) == MEM
3311 && (GET_MODE_SIZE (mode)
3312 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x)))))
3314 rtx inner = SUBREG_REG (x);
3315 int endian_offset = 0;
3316 /* Don't change the mode of the MEM
3317 if that would change the meaning of the address. */
3318 if (MEM_VOLATILE_P (SUBREG_REG (x))
3319 || mode_dependent_address_p (XEXP (inner, 0)))
3320 return gen_rtx (CLOBBER, mode, const0_rtx);
3322 if (BYTES_BIG_ENDIAN)
3324 if (GET_MODE_SIZE (mode) < UNITS_PER_WORD)
3325 endian_offset += UNITS_PER_WORD - GET_MODE_SIZE (mode);
3326 if (GET_MODE_SIZE (GET_MODE (inner)) < UNITS_PER_WORD)
3327 endian_offset -= (UNITS_PER_WORD
3328 - GET_MODE_SIZE (GET_MODE (inner)));
3330 /* Note if the plus_constant doesn't make a valid address
3331 then this combination won't be accepted. */
3332 x = gen_rtx (MEM, mode,
3333 plus_constant (XEXP (inner, 0),
3334 (SUBREG_WORD (x) * UNITS_PER_WORD
3336 MEM_VOLATILE_P (x) = MEM_VOLATILE_P (inner);
3337 RTX_UNCHANGING_P (x) = RTX_UNCHANGING_P (inner);
3338 MEM_IN_STRUCT_P (x) = MEM_IN_STRUCT_P (inner);
3342 /* If we are in a SET_DEST, these other cases can't apply. */
3346 /* Changing mode twice with SUBREG => just change it once,
3347 or not at all if changing back to starting mode. */
3348 if (GET_CODE (SUBREG_REG (x)) == SUBREG)
3350 if (mode == GET_MODE (SUBREG_REG (SUBREG_REG (x)))
3351 && SUBREG_WORD (x) == 0 && SUBREG_WORD (SUBREG_REG (x)) == 0)
3352 return SUBREG_REG (SUBREG_REG (x));
3354 SUBST_INT (SUBREG_WORD (x),
3355 SUBREG_WORD (x) + SUBREG_WORD (SUBREG_REG (x)));
3356 SUBST (SUBREG_REG (x), SUBREG_REG (SUBREG_REG (x)));
3359 /* SUBREG of a hard register => just change the register number
3360 and/or mode. If the hard register is not valid in that mode,
3361 suppress this combination. If the hard register is the stack,
3362 frame, or argument pointer, leave this as a SUBREG. */
3364 if (GET_CODE (SUBREG_REG (x)) == REG
3365 && REGNO (SUBREG_REG (x)) < FIRST_PSEUDO_REGISTER
3366 && REGNO (SUBREG_REG (x)) != FRAME_POINTER_REGNUM
3367 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
3368 && REGNO (SUBREG_REG (x)) != HARD_FRAME_POINTER_REGNUM
3370 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
3371 && REGNO (SUBREG_REG (x)) != ARG_POINTER_REGNUM
3373 && REGNO (SUBREG_REG (x)) != STACK_POINTER_REGNUM)
3375 if (HARD_REGNO_MODE_OK (REGNO (SUBREG_REG (x)) + SUBREG_WORD (x),
3377 return gen_rtx (REG, mode,
3378 REGNO (SUBREG_REG (x)) + SUBREG_WORD (x));
3380 return gen_rtx (CLOBBER, mode, const0_rtx);
3383 /* For a constant, try to pick up the part we want. Handle a full
3384 word and low-order part. Only do this if we are narrowing
3385 the constant; if it is being widened, we have no idea what
3386 the extra bits will have been set to. */
3388 if (CONSTANT_P (SUBREG_REG (x)) && op0_mode != VOIDmode
3389 && GET_MODE_SIZE (mode) == UNITS_PER_WORD
3390 && GET_MODE_SIZE (op0_mode) > UNITS_PER_WORD
3391 && GET_MODE_CLASS (mode) == MODE_INT)
3393 temp = operand_subword (SUBREG_REG (x), SUBREG_WORD (x),
3399 /* If we want a subreg of a constant, at offset 0,
3400 take the low bits. On a little-endian machine, that's
3401 always valid. On a big-endian machine, it's valid
3402 only if the constant's mode fits in one word. Note that we
3403 cannot use subreg_lowpart_p since SUBREG_REG may be VOIDmode. */
3404 if (CONSTANT_P (SUBREG_REG (x))
3405 && ((GET_MODE_SIZE (op0_mode) <= UNITS_PER_WORD
3406 || ! WORDS_BIG_ENDIAN)
3407 ? SUBREG_WORD (x) == 0
3409 == ((GET_MODE_SIZE (op0_mode)
3410 - MAX (GET_MODE_SIZE (mode), UNITS_PER_WORD))
3412 && GET_MODE_SIZE (mode) <= GET_MODE_SIZE (op0_mode)
3413 && (! WORDS_BIG_ENDIAN
3414 || GET_MODE_BITSIZE (op0_mode) <= BITS_PER_WORD))
3415 return gen_lowpart_for_combine (mode, SUBREG_REG (x));
3417 /* A paradoxical SUBREG of a VOIDmode constant is the same constant,
3418 since we are saying that the high bits don't matter. */
3419 if (CONSTANT_P (SUBREG_REG (x)) && GET_MODE (SUBREG_REG (x)) == VOIDmode
3420 && GET_MODE_SIZE (mode) > GET_MODE_SIZE (op0_mode))
3421 return SUBREG_REG (x);
3423 /* Note that we cannot do any narrowing for non-constants since
3424 we might have been counting on using the fact that some bits were
3425 zero. We now do this in the SET. */
3430 /* (not (plus X -1)) can become (neg X). */
3431 if (GET_CODE (XEXP (x, 0)) == PLUS
3432 && XEXP (XEXP (x, 0), 1) == constm1_rtx)
3433 return gen_rtx_combine (NEG, mode, XEXP (XEXP (x, 0), 0));
3435 /* Similarly, (not (neg X)) is (plus X -1). */
3436 if (GET_CODE (XEXP (x, 0)) == NEG)
3437 return gen_rtx_combine (PLUS, mode, XEXP (XEXP (x, 0), 0),
3440 /* (not (xor X C)) for C constant is (xor X D) with D = ~ C. */
3441 if (GET_CODE (XEXP (x, 0)) == XOR
3442 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3443 && (temp = simplify_unary_operation (NOT, mode,
3444 XEXP (XEXP (x, 0), 1),
3446 return gen_binary (XOR, mode, XEXP (XEXP (x, 0), 0), temp);
3448 /* (not (ashift 1 X)) is (rotate ~1 X). We used to do this for operands
3449 other than 1, but that is not valid. We could do a similar
3450 simplification for (not (lshiftrt C X)) where C is just the sign bit,
3451 but this doesn't seem common enough to bother with. */
3452 if (GET_CODE (XEXP (x, 0)) == ASHIFT
3453 && XEXP (XEXP (x, 0), 0) == const1_rtx)
3454 return gen_rtx (ROTATE, mode, gen_unary (NOT, mode, mode, const1_rtx),
3455 XEXP (XEXP (x, 0), 1));
3457 if (GET_CODE (XEXP (x, 0)) == SUBREG
3458 && subreg_lowpart_p (XEXP (x, 0))
3459 && (GET_MODE_SIZE (GET_MODE (XEXP (x, 0)))
3460 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (x, 0)))))
3461 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == ASHIFT
3462 && XEXP (SUBREG_REG (XEXP (x, 0)), 0) == const1_rtx)
3464 enum machine_mode inner_mode = GET_MODE (SUBREG_REG (XEXP (x, 0)));
3466 x = gen_rtx (ROTATE, inner_mode,
3467 gen_unary (NOT, inner_mode, inner_mode, const1_rtx),
3468 XEXP (SUBREG_REG (XEXP (x, 0)), 1));
3469 return gen_lowpart_for_combine (mode, x);
3472 /* If STORE_FLAG_VALUE is -1, (not (comparison foo bar)) can be done by
3473 reversing the comparison code if valid. */
3474 if (STORE_FLAG_VALUE == -1
3475 && GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
3476 && reversible_comparison_p (XEXP (x, 0)))
3477 return gen_rtx_combine (reverse_condition (GET_CODE (XEXP (x, 0))),
3478 mode, XEXP (XEXP (x, 0), 0),
3479 XEXP (XEXP (x, 0), 1));
3481 /* (ashiftrt foo C) where C is the number of bits in FOO minus 1
3482 is (lt foo (const_int 0)) if STORE_FLAG_VALUE is -1, so we can
3483 perform the above simplification. */
3485 if (STORE_FLAG_VALUE == -1
3486 && XEXP (x, 1) == const1_rtx
3487 && GET_CODE (XEXP (x, 0)) == ASHIFTRT
3488 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3489 && INTVAL (XEXP (XEXP (x, 0), 1)) == GET_MODE_BITSIZE (mode) - 1)
3490 return gen_rtx_combine (GE, mode, XEXP (XEXP (x, 0), 0), const0_rtx);
3492 /* Apply De Morgan's laws to reduce number of patterns for machines
3493 with negating logical insns (and-not, nand, etc.). If result has
3494 only one NOT, put it first, since that is how the patterns are
3497 if (GET_CODE (XEXP (x, 0)) == IOR || GET_CODE (XEXP (x, 0)) == AND)
3499 rtx in1 = XEXP (XEXP (x, 0), 0), in2 = XEXP (XEXP (x, 0), 1);
3501 if (GET_CODE (in1) == NOT)
3502 in1 = XEXP (in1, 0);
3504 in1 = gen_rtx_combine (NOT, GET_MODE (in1), in1);
3506 if (GET_CODE (in2) == NOT)
3507 in2 = XEXP (in2, 0);
3508 else if (GET_CODE (in2) == CONST_INT
3509 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
3510 in2 = GEN_INT (GET_MODE_MASK (mode) & ~ INTVAL (in2));
3512 in2 = gen_rtx_combine (NOT, GET_MODE (in2), in2);
3514 if (GET_CODE (in2) == NOT)
3517 in2 = in1; in1 = tem;
3520 return gen_rtx_combine (GET_CODE (XEXP (x, 0)) == IOR ? AND : IOR,
3526 /* (neg (plus X 1)) can become (not X). */
3527 if (GET_CODE (XEXP (x, 0)) == PLUS
3528 && XEXP (XEXP (x, 0), 1) == const1_rtx)
3529 return gen_rtx_combine (NOT, mode, XEXP (XEXP (x, 0), 0));
3531 /* Similarly, (neg (not X)) is (plus X 1). */
3532 if (GET_CODE (XEXP (x, 0)) == NOT)
3533 return plus_constant (XEXP (XEXP (x, 0), 0), 1);
3535 /* (neg (minus X Y)) can become (minus Y X). */
3536 if (GET_CODE (XEXP (x, 0)) == MINUS
3537 && (! FLOAT_MODE_P (mode)
3538 /* x-y != -(y-x) with IEEE floating point. */
3539 || TARGET_FLOAT_FORMAT != IEEE_FLOAT_FORMAT
3541 return gen_binary (MINUS, mode, XEXP (XEXP (x, 0), 1),
3542 XEXP (XEXP (x, 0), 0));
3544 /* (neg (xor A 1)) is (plus A -1) if A is known to be either 0 or 1. */
3545 if (GET_CODE (XEXP (x, 0)) == XOR && XEXP (XEXP (x, 0), 1) == const1_rtx
3546 && nonzero_bits (XEXP (XEXP (x, 0), 0), mode) == 1)
3547 return gen_binary (PLUS, mode, XEXP (XEXP (x, 0), 0), constm1_rtx);
3549 /* NEG commutes with ASHIFT since it is multiplication. Only do this
3550 if we can then eliminate the NEG (e.g.,
3551 if the operand is a constant). */
3553 if (GET_CODE (XEXP (x, 0)) == ASHIFT)
3555 temp = simplify_unary_operation (NEG, mode,
3556 XEXP (XEXP (x, 0), 0), mode);
3559 SUBST (XEXP (XEXP (x, 0), 0), temp);
3564 temp = expand_compound_operation (XEXP (x, 0));
3566 /* For C equal to the width of MODE minus 1, (neg (ashiftrt X C)) can be
3567 replaced by (lshiftrt X C). This will convert
3568 (neg (sign_extract X 1 Y)) to (zero_extract X 1 Y). */
3570 if (GET_CODE (temp) == ASHIFTRT
3571 && GET_CODE (XEXP (temp, 1)) == CONST_INT
3572 && INTVAL (XEXP (temp, 1)) == GET_MODE_BITSIZE (mode) - 1)
3573 return simplify_shift_const (temp, LSHIFTRT, mode, XEXP (temp, 0),
3574 INTVAL (XEXP (temp, 1)));
3576 /* If X has only a single bit that might be nonzero, say, bit I, convert
3577 (neg X) to (ashiftrt (ashift X C-I) C-I) where C is the bitsize of
3578 MODE minus 1. This will convert (neg (zero_extract X 1 Y)) to
3579 (sign_extract X 1 Y). But only do this if TEMP isn't a register
3580 or a SUBREG of one since we'd be making the expression more
3581 complex if it was just a register. */
3583 if (GET_CODE (temp) != REG
3584 && ! (GET_CODE (temp) == SUBREG
3585 && GET_CODE (SUBREG_REG (temp)) == REG)
3586 && (i = exact_log2 (nonzero_bits (temp, mode))) >= 0)
3588 rtx temp1 = simplify_shift_const
3589 (NULL_RTX, ASHIFTRT, mode,
3590 simplify_shift_const (NULL_RTX, ASHIFT, mode, temp,
3591 GET_MODE_BITSIZE (mode) - 1 - i),
3592 GET_MODE_BITSIZE (mode) - 1 - i);
3594 /* If all we did was surround TEMP with the two shifts, we
3595 haven't improved anything, so don't use it. Otherwise,
3596 we are better off with TEMP1. */
3597 if (GET_CODE (temp1) != ASHIFTRT
3598 || GET_CODE (XEXP (temp1, 0)) != ASHIFT
3599 || XEXP (XEXP (temp1, 0), 0) != temp)
3605 /* We can't handle truncation to a partial integer mode here
3606 because we don't know the real bitsize of the partial
3608 if (GET_MODE_CLASS (mode) == MODE_PARTIAL_INT)
3611 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
3613 force_to_mode (XEXP (x, 0), GET_MODE (XEXP (x, 0)),
3614 GET_MODE_MASK (mode), NULL_RTX, 0));
3616 /* (truncate:SI ({sign,zero}_extend:DI foo:SI)) == foo:SI. */
3617 if ((GET_CODE (XEXP (x, 0)) == SIGN_EXTEND
3618 || GET_CODE (XEXP (x, 0)) == ZERO_EXTEND)
3619 && GET_MODE (XEXP (XEXP (x, 0), 0)) == mode)
3620 return XEXP (XEXP (x, 0), 0);
3622 /* (truncate:SI (OP:DI ({sign,zero}_extend:DI foo:SI))) is
3623 (OP:SI foo:SI) if OP is NEG or ABS. */
3624 if ((GET_CODE (XEXP (x, 0)) == ABS
3625 || GET_CODE (XEXP (x, 0)) == NEG)
3626 && (GET_CODE (XEXP (XEXP (x, 0), 0)) == SIGN_EXTEND
3627 || GET_CODE (XEXP (XEXP (x, 0), 0)) == ZERO_EXTEND)
3628 && GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == mode)
3629 return gen_unary (GET_CODE (XEXP (x, 0)), mode, mode,
3630 XEXP (XEXP (XEXP (x, 0), 0), 0));
3632 /* (truncate:SI (subreg:DI (truncate:SI X) 0)) is
3634 if (GET_CODE (XEXP (x, 0)) == SUBREG
3635 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == TRUNCATE
3636 && subreg_lowpart_p (XEXP (x, 0)))
3637 return SUBREG_REG (XEXP (x, 0));
3639 /* If we know that the value is already truncated, we can
3640 replace the TRUNCATE with a SUBREG. */
3641 if (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) <= HOST_BITS_PER_WIDE_INT
3642 && (nonzero_bits (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
3643 &~ GET_MODE_MASK (mode)) == 0)
3644 return gen_lowpart_for_combine (mode, XEXP (x, 0));
3646 /* A truncate of a comparison can be replaced with a subreg if
3647 STORE_FLAG_VALUE permits. This is like the previous test,
3648 but it works even if the comparison is done in a mode larger
3649 than HOST_BITS_PER_WIDE_INT. */
3650 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
3651 && GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
3652 && ((HOST_WIDE_INT) STORE_FLAG_VALUE &~ GET_MODE_MASK (mode)) == 0)
3653 return gen_lowpart_for_combine (mode, XEXP (x, 0));
3655 /* Similarly, a truncate of a register whose value is a
3656 comparison can be replaced with a subreg if STORE_FLAG_VALUE
3658 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
3659 && ((HOST_WIDE_INT) STORE_FLAG_VALUE &~ GET_MODE_MASK (mode)) == 0
3660 && (temp = get_last_value (XEXP (x, 0)))
3661 && GET_RTX_CLASS (GET_CODE (temp)) == '<')
3662 return gen_lowpart_for_combine (mode, XEXP (x, 0));
3666 case FLOAT_TRUNCATE:
3667 /* (float_truncate:SF (float_extend:DF foo:SF)) = foo:SF. */
3668 if (GET_CODE (XEXP (x, 0)) == FLOAT_EXTEND
3669 && GET_MODE (XEXP (XEXP (x, 0), 0)) == mode)
3670 return XEXP (XEXP (x, 0), 0);
3672 /* (float_truncate:SF (OP:DF (float_extend:DF foo:sf))) is
3673 (OP:SF foo:SF) if OP is NEG or ABS. */
3674 if ((GET_CODE (XEXP (x, 0)) == ABS
3675 || GET_CODE (XEXP (x, 0)) == NEG)
3676 && GET_CODE (XEXP (XEXP (x, 0), 0)) == FLOAT_EXTEND
3677 && GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == mode)
3678 return gen_unary (GET_CODE (XEXP (x, 0)), mode, mode,
3679 XEXP (XEXP (XEXP (x, 0), 0), 0));
3681 /* (float_truncate:SF (subreg:DF (float_truncate:SF X) 0))
3682 is (float_truncate:SF x). */
3683 if (GET_CODE (XEXP (x, 0)) == SUBREG
3684 && subreg_lowpart_p (XEXP (x, 0))
3685 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == FLOAT_TRUNCATE)
3686 return SUBREG_REG (XEXP (x, 0));
3691 /* Convert (compare FOO (const_int 0)) to FOO unless we aren't
3692 using cc0, in which case we want to leave it as a COMPARE
3693 so we can distinguish it from a register-register-copy. */
3694 if (XEXP (x, 1) == const0_rtx)
3697 /* In IEEE floating point, x-0 is not the same as x. */
3698 if ((TARGET_FLOAT_FORMAT != IEEE_FLOAT_FORMAT
3699 || ! FLOAT_MODE_P (GET_MODE (XEXP (x, 0)))
3701 && XEXP (x, 1) == CONST0_RTX (GET_MODE (XEXP (x, 0))))
3707 /* (const (const X)) can become (const X). Do it this way rather than
3708 returning the inner CONST since CONST can be shared with a
3710 if (GET_CODE (XEXP (x, 0)) == CONST)
3711 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
3716 /* Convert (lo_sum (high FOO) FOO) to FOO. This is necessary so we
3717 can add in an offset. find_split_point will split this address up
3718 again if it doesn't match. */
3719 if (GET_CODE (XEXP (x, 0)) == HIGH
3720 && rtx_equal_p (XEXP (XEXP (x, 0), 0), XEXP (x, 1)))
3726 /* If we have (plus (plus (A const) B)), associate it so that CONST is
3727 outermost. That's because that's the way indexed addresses are
3728 supposed to appear. This code used to check many more cases, but
3729 they are now checked elsewhere. */
3730 if (GET_CODE (XEXP (x, 0)) == PLUS
3731 && CONSTANT_ADDRESS_P (XEXP (XEXP (x, 0), 1)))
3732 return gen_binary (PLUS, mode,
3733 gen_binary (PLUS, mode, XEXP (XEXP (x, 0), 0),
3735 XEXP (XEXP (x, 0), 1));
3737 /* (plus (xor (and <foo> (const_int pow2 - 1)) <c>) <-c>)
3738 when c is (const_int (pow2 + 1) / 2) is a sign extension of a
3739 bit-field and can be replaced by either a sign_extend or a
3740 sign_extract. The `and' may be a zero_extend. */
3741 if (GET_CODE (XEXP (x, 0)) == XOR
3742 && GET_CODE (XEXP (x, 1)) == CONST_INT
3743 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3744 && INTVAL (XEXP (x, 1)) == - INTVAL (XEXP (XEXP (x, 0), 1))
3745 && (i = exact_log2 (INTVAL (XEXP (XEXP (x, 0), 1)))) >= 0
3746 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
3747 && ((GET_CODE (XEXP (XEXP (x, 0), 0)) == AND
3748 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == CONST_INT
3749 && (INTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1))
3750 == ((HOST_WIDE_INT) 1 << (i + 1)) - 1))
3751 || (GET_CODE (XEXP (XEXP (x, 0), 0)) == ZERO_EXTEND
3752 && (GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)))
3754 return simplify_shift_const
3755 (NULL_RTX, ASHIFTRT, mode,
3756 simplify_shift_const (NULL_RTX, ASHIFT, mode,
3757 XEXP (XEXP (XEXP (x, 0), 0), 0),
3758 GET_MODE_BITSIZE (mode) - (i + 1)),
3759 GET_MODE_BITSIZE (mode) - (i + 1));
3761 /* (plus (comparison A B) C) can become (neg (rev-comp A B)) if
3762 C is 1 and STORE_FLAG_VALUE is -1 or if C is -1 and STORE_FLAG_VALUE
3763 is 1. This produces better code than the alternative immediately
3765 if (GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
3766 && reversible_comparison_p (XEXP (x, 0))
3767 && ((STORE_FLAG_VALUE == -1 && XEXP (x, 1) == const1_rtx)
3768 || (STORE_FLAG_VALUE == 1 && XEXP (x, 1) == constm1_rtx)))
3770 gen_unary (NEG, mode, mode,
3771 gen_binary (reverse_condition (GET_CODE (XEXP (x, 0))),
3772 mode, XEXP (XEXP (x, 0), 0),
3773 XEXP (XEXP (x, 0), 1)));
3775 /* If only the low-order bit of X is possibly nonzero, (plus x -1)
3776 can become (ashiftrt (ashift (xor x 1) C) C) where C is
3777 the bitsize of the mode - 1. This allows simplification of
3778 "a = (b & 8) == 0;" */
3779 if (XEXP (x, 1) == constm1_rtx
3780 && GET_CODE (XEXP (x, 0)) != REG
3781 && ! (GET_CODE (XEXP (x,0)) == SUBREG
3782 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == REG)
3783 && nonzero_bits (XEXP (x, 0), mode) == 1)
3784 return simplify_shift_const (NULL_RTX, ASHIFTRT, mode,
3785 simplify_shift_const (NULL_RTX, ASHIFT, mode,
3786 gen_rtx_combine (XOR, mode,
3787 XEXP (x, 0), const1_rtx),
3788 GET_MODE_BITSIZE (mode) - 1),
3789 GET_MODE_BITSIZE (mode) - 1);
3791 /* If we are adding two things that have no bits in common, convert
3792 the addition into an IOR. This will often be further simplified,
3793 for example in cases like ((a & 1) + (a & 2)), which can
3796 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
3797 && (nonzero_bits (XEXP (x, 0), mode)
3798 & nonzero_bits (XEXP (x, 1), mode)) == 0)
3799 return gen_binary (IOR, mode, XEXP (x, 0), XEXP (x, 1));
3803 /* If STORE_FLAG_VALUE is 1, (minus 1 (comparison foo bar)) can be done
3804 by reversing the comparison code if valid. */
3805 if (STORE_FLAG_VALUE == 1
3806 && XEXP (x, 0) == const1_rtx
3807 && GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) == '<'
3808 && reversible_comparison_p (XEXP (x, 1)))
3809 return gen_binary (reverse_condition (GET_CODE (XEXP (x, 1))),
3810 mode, XEXP (XEXP (x, 1), 0),
3811 XEXP (XEXP (x, 1), 1));
3813 /* (minus <foo> (and <foo> (const_int -pow2))) becomes
3814 (and <foo> (const_int pow2-1)) */
3815 if (GET_CODE (XEXP (x, 1)) == AND
3816 && GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT
3817 && exact_log2 (- INTVAL (XEXP (XEXP (x, 1), 1))) >= 0
3818 && rtx_equal_p (XEXP (XEXP (x, 1), 0), XEXP (x, 0)))
3819 return simplify_and_const_int (NULL_RTX, mode, XEXP (x, 0),
3820 - INTVAL (XEXP (XEXP (x, 1), 1)) - 1);
3822 /* Canonicalize (minus A (plus B C)) to (minus (minus A B) C) for
3824 if (GET_CODE (XEXP (x, 1)) == PLUS && INTEGRAL_MODE_P (mode))
3825 return gen_binary (MINUS, mode,
3826 gen_binary (MINUS, mode, XEXP (x, 0),
3827 XEXP (XEXP (x, 1), 0)),
3828 XEXP (XEXP (x, 1), 1));
3832 /* If we have (mult (plus A B) C), apply the distributive law and then
3833 the inverse distributive law to see if things simplify. This
3834 occurs mostly in addresses, often when unrolling loops. */
3836 if (GET_CODE (XEXP (x, 0)) == PLUS)
3838 x = apply_distributive_law
3839 (gen_binary (PLUS, mode,
3840 gen_binary (MULT, mode,
3841 XEXP (XEXP (x, 0), 0), XEXP (x, 1)),
3842 gen_binary (MULT, mode,
3843 XEXP (XEXP (x, 0), 1), XEXP (x, 1))));
3845 if (GET_CODE (x) != MULT)
3851 /* If this is a divide by a power of two, treat it as a shift if
3852 its first operand is a shift. */
3853 if (GET_CODE (XEXP (x, 1)) == CONST_INT
3854 && (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0
3855 && (GET_CODE (XEXP (x, 0)) == ASHIFT
3856 || GET_CODE (XEXP (x, 0)) == LSHIFTRT
3857 || GET_CODE (XEXP (x, 0)) == ASHIFTRT
3858 || GET_CODE (XEXP (x, 0)) == ROTATE
3859 || GET_CODE (XEXP (x, 0)) == ROTATERT))
3860 return simplify_shift_const (NULL_RTX, LSHIFTRT, mode, XEXP (x, 0), i);
3864 case GT: case GTU: case GE: case GEU:
3865 case LT: case LTU: case LE: case LEU:
3866 /* If the first operand is a condition code, we can't do anything
3868 if (GET_CODE (XEXP (x, 0)) == COMPARE
3869 || (GET_MODE_CLASS (GET_MODE (XEXP (x, 0))) != MODE_CC
3871 && XEXP (x, 0) != cc0_rtx
3875 rtx op0 = XEXP (x, 0);
3876 rtx op1 = XEXP (x, 1);
3877 enum rtx_code new_code;
3879 if (GET_CODE (op0) == COMPARE)
3880 op1 = XEXP (op0, 1), op0 = XEXP (op0, 0);
3882 /* Simplify our comparison, if possible. */
3883 new_code = simplify_comparison (code, &op0, &op1);
3885 /* If STORE_FLAG_VALUE is 1, we can convert (ne x 0) to simply X
3886 if only the low-order bit is possibly nonzero in X (such as when
3887 X is a ZERO_EXTRACT of one bit). Similarly, we can convert EQ to
3888 (xor X 1) or (minus 1 X); we use the former. Finally, if X is
3889 known to be either 0 or -1, NE becomes a NEG and EQ becomes
3892 Remove any ZERO_EXTRACT we made when thinking this was a
3893 comparison. It may now be simpler to use, e.g., an AND. If a
3894 ZERO_EXTRACT is indeed appropriate, it will be placed back by
3895 the call to make_compound_operation in the SET case. */
3897 if (STORE_FLAG_VALUE == 1
3898 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
3899 && op1 == const0_rtx && nonzero_bits (op0, mode) == 1)
3900 return gen_lowpart_for_combine (mode,
3901 expand_compound_operation (op0));
3903 else if (STORE_FLAG_VALUE == 1
3904 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
3905 && op1 == const0_rtx
3906 && (num_sign_bit_copies (op0, mode)
3907 == GET_MODE_BITSIZE (mode)))
3909 op0 = expand_compound_operation (op0);
3910 return gen_unary (NEG, mode, mode,
3911 gen_lowpart_for_combine (mode, op0));
3914 else if (STORE_FLAG_VALUE == 1
3915 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
3916 && op1 == const0_rtx
3917 && nonzero_bits (op0, mode) == 1)
3919 op0 = expand_compound_operation (op0);
3920 return gen_binary (XOR, mode,
3921 gen_lowpart_for_combine (mode, op0),
3925 else if (STORE_FLAG_VALUE == 1
3926 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
3927 && op1 == const0_rtx
3928 && (num_sign_bit_copies (op0, mode)
3929 == GET_MODE_BITSIZE (mode)))
3931 op0 = expand_compound_operation (op0);
3932 return plus_constant (gen_lowpart_for_combine (mode, op0), 1);
3935 /* If STORE_FLAG_VALUE is -1, we have cases similar to
3937 if (STORE_FLAG_VALUE == -1
3938 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
3939 && op1 == const0_rtx
3940 && (num_sign_bit_copies (op0, mode)
3941 == GET_MODE_BITSIZE (mode)))
3942 return gen_lowpart_for_combine (mode,
3943 expand_compound_operation (op0));
3945 else if (STORE_FLAG_VALUE == -1
3946 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
3947 && op1 == const0_rtx
3948 && nonzero_bits (op0, mode) == 1)
3950 op0 = expand_compound_operation (op0);
3951 return gen_unary (NEG, mode, mode,
3952 gen_lowpart_for_combine (mode, op0));
3955 else if (STORE_FLAG_VALUE == -1
3956 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
3957 && op1 == const0_rtx
3958 && (num_sign_bit_copies (op0, mode)
3959 == GET_MODE_BITSIZE (mode)))
3961 op0 = expand_compound_operation (op0);
3962 return gen_unary (NOT, mode, mode,
3963 gen_lowpart_for_combine (mode, op0));
3966 /* If X is 0/1, (eq X 0) is X-1. */
3967 else if (STORE_FLAG_VALUE == -1
3968 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
3969 && op1 == const0_rtx
3970 && nonzero_bits (op0, mode) == 1)
3972 op0 = expand_compound_operation (op0);
3973 return plus_constant (gen_lowpart_for_combine (mode, op0), -1);
3976 /* If STORE_FLAG_VALUE says to just test the sign bit and X has just
3977 one bit that might be nonzero, we can convert (ne x 0) to
3978 (ashift x c) where C puts the bit in the sign bit. Remove any
3979 AND with STORE_FLAG_VALUE when we are done, since we are only
3980 going to test the sign bit. */
3981 if (new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
3982 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
3983 && ((STORE_FLAG_VALUE & GET_MODE_MASK (mode))
3984 == (HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (mode) - 1))
3985 && op1 == const0_rtx
3986 && mode == GET_MODE (op0)
3987 && (i = exact_log2 (nonzero_bits (op0, mode))) >= 0)
3989 x = simplify_shift_const (NULL_RTX, ASHIFT, mode,
3990 expand_compound_operation (op0),
3991 GET_MODE_BITSIZE (mode) - 1 - i);
3992 if (GET_CODE (x) == AND && XEXP (x, 1) == const_true_rtx)
3998 /* If the code changed, return a whole new comparison. */
3999 if (new_code != code)
4000 return gen_rtx_combine (new_code, mode, op0, op1);
4002 /* Otherwise, keep this operation, but maybe change its operands.
4003 This also converts (ne (compare FOO BAR) 0) to (ne FOO BAR). */
4004 SUBST (XEXP (x, 0), op0);
4005 SUBST (XEXP (x, 1), op1);
4010 return simplify_if_then_else (x);
4016 /* If we are processing SET_DEST, we are done. */
4020 return expand_compound_operation (x);
4023 return simplify_set (x);
4028 return simplify_logical (x, last);
4031 /* (abs (neg <foo>)) -> (abs <foo>) */
4032 if (GET_CODE (XEXP (x, 0)) == NEG)
4033 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4035 /* If operand is something known to be positive, ignore the ABS. */
4036 if (GET_CODE (XEXP (x, 0)) == FFS || GET_CODE (XEXP (x, 0)) == ABS
4037 || ((GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
4038 <= HOST_BITS_PER_WIDE_INT)
4039 && ((nonzero_bits (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
4040 & ((HOST_WIDE_INT) 1
4041 << (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - 1)))
4046 /* If operand is known to be only -1 or 0, convert ABS to NEG. */
4047 if (num_sign_bit_copies (XEXP (x, 0), mode) == GET_MODE_BITSIZE (mode))
4048 return gen_rtx_combine (NEG, mode, XEXP (x, 0));
4053 /* (ffs (*_extend <X>)) = (ffs <X>) */
4054 if (GET_CODE (XEXP (x, 0)) == SIGN_EXTEND
4055 || GET_CODE (XEXP (x, 0)) == ZERO_EXTEND)
4056 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4060 /* (float (sign_extend <X>)) = (float <X>). */
4061 if (GET_CODE (XEXP (x, 0)) == SIGN_EXTEND)
4062 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4070 /* If this is a shift by a constant amount, simplify it. */
4071 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
4072 return simplify_shift_const (x, code, mode, XEXP (x, 0),
4073 INTVAL (XEXP (x, 1)));
4075 #ifdef SHIFT_COUNT_TRUNCATED
4076 else if (SHIFT_COUNT_TRUNCATED && GET_CODE (XEXP (x, 1)) != REG)
4078 force_to_mode (XEXP (x, 1), GET_MODE (x),
4080 << exact_log2 (GET_MODE_BITSIZE (GET_MODE (x))))
4091 /* Simplify X, an IF_THEN_ELSE expression. Return the new expression. */
4094 simplify_if_then_else (x)
4097 enum machine_mode mode = GET_MODE (x);
4098 rtx cond = XEXP (x, 0);
4099 rtx true = XEXP (x, 1);
4100 rtx false = XEXP (x, 2);
4101 enum rtx_code true_code = GET_CODE (cond);
4102 int comparison_p = GET_RTX_CLASS (true_code) == '<';
4106 /* Simplify storing of the truth value. */
4107 if (comparison_p && true == const_true_rtx && false == const0_rtx)
4108 return gen_binary (true_code, mode, XEXP (cond, 0), XEXP (cond, 1));
4110 /* Also when the truth value has to be reversed. */
4111 if (comparison_p && reversible_comparison_p (cond)
4112 && true == const0_rtx && false == const_true_rtx)
4113 return gen_binary (reverse_condition (true_code),
4114 mode, XEXP (cond, 0), XEXP (cond, 1));
4116 /* Sometimes we can simplify the arm of an IF_THEN_ELSE if a register used
4117 in it is being compared against certain values. Get the true and false
4118 comparisons and see if that says anything about the value of each arm. */
4120 if (comparison_p && reversible_comparison_p (cond)
4121 && GET_CODE (XEXP (cond, 0)) == REG)
4124 rtx from = XEXP (cond, 0);
4125 enum rtx_code false_code = reverse_condition (true_code);
4126 rtx true_val = XEXP (cond, 1);
4127 rtx false_val = true_val;
4130 /* If FALSE_CODE is EQ, swap the codes and arms. */
4132 if (false_code == EQ)
4134 swapped = 1, true_code = EQ, false_code = NE;
4135 temp = true, true = false, false = temp;
4138 /* If we are comparing against zero and the expression being tested has
4139 only a single bit that might be nonzero, that is its value when it is
4140 not equal to zero. Similarly if it is known to be -1 or 0. */
4142 if (true_code == EQ && true_val == const0_rtx
4143 && exact_log2 (nzb = nonzero_bits (from, GET_MODE (from))) >= 0)
4144 false_code = EQ, false_val = GEN_INT (nzb);
4145 else if (true_code == EQ && true_val == const0_rtx
4146 && (num_sign_bit_copies (from, GET_MODE (from))
4147 == GET_MODE_BITSIZE (GET_MODE (from))))
4148 false_code = EQ, false_val = constm1_rtx;
4150 /* Now simplify an arm if we know the value of the register in the
4151 branch and it is used in the arm. Be careful due to the potential
4152 of locally-shared RTL. */
4154 if (reg_mentioned_p (from, true))
4155 true = subst (known_cond (copy_rtx (true), true_code, from, true_val),
4156 pc_rtx, pc_rtx, 0, 0);
4157 if (reg_mentioned_p (from, false))
4158 false = subst (known_cond (copy_rtx (false), false_code,
4160 pc_rtx, pc_rtx, 0, 0);
4162 SUBST (XEXP (x, 1), swapped ? false : true);
4163 SUBST (XEXP (x, 2), swapped ? true : false);
4165 true = XEXP (x, 1), false = XEXP (x, 2), true_code = GET_CODE (cond);
4168 /* If we have (if_then_else FOO (pc) (label_ref BAR)) and FOO can be
4169 reversed, do so to avoid needing two sets of patterns for
4170 subtract-and-branch insns. Similarly if we have a constant in the true
4171 arm, the false arm is the same as the first operand of the comparison, or
4172 the false arm is more complicated than the true arm. */
4174 if (comparison_p && reversible_comparison_p (cond)
4176 || (CONSTANT_P (true)
4177 && GET_CODE (false) != CONST_INT && false != pc_rtx)
4178 || true == const0_rtx
4179 || (GET_RTX_CLASS (GET_CODE (true)) == 'o'
4180 && GET_RTX_CLASS (GET_CODE (false)) != 'o')
4181 || (GET_CODE (true) == SUBREG
4182 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (true))) == 'o'
4183 && GET_RTX_CLASS (GET_CODE (false)) != 'o')
4184 || reg_mentioned_p (true, false)
4185 || rtx_equal_p (false, XEXP (cond, 0))))
4187 true_code = reverse_condition (true_code);
4189 gen_binary (true_code, GET_MODE (cond), XEXP (cond, 0),
4192 SUBST (XEXP (x, 1), false);
4193 SUBST (XEXP (x, 2), true);
4195 temp = true, true = false, false = temp, cond = XEXP (x, 0);
4197 /* It is possible that the conditional has been simplified out. */
4198 true_code = GET_CODE (cond);
4199 comparison_p = GET_RTX_CLASS (true_code) == '<';
4202 /* If the two arms are identical, we don't need the comparison. */
4204 if (rtx_equal_p (true, false) && ! side_effects_p (cond))
4207 /* Convert a == b ? b : a to "a". */
4208 if (true_code == EQ && ! side_effects_p (cond)
4209 && rtx_equal_p (XEXP (cond, 0), false)
4210 && rtx_equal_p (XEXP (cond, 1), true))
4212 else if (true_code == NE && ! side_effects_p (cond)
4213 && rtx_equal_p (XEXP (cond, 0), true)
4214 && rtx_equal_p (XEXP (cond, 1), false))
4217 /* Look for cases where we have (abs x) or (neg (abs X)). */
4219 if (GET_MODE_CLASS (mode) == MODE_INT
4220 && GET_CODE (false) == NEG
4221 && rtx_equal_p (true, XEXP (false, 0))
4223 && rtx_equal_p (true, XEXP (cond, 0))
4224 && ! side_effects_p (true))
4229 return gen_unary (ABS, mode, mode, true);
4232 return gen_unary (NEG, mode, mode, gen_unary (ABS, mode, mode, true));
4235 /* Look for MIN or MAX. */
4237 if ((! FLOAT_MODE_P (mode) || flag_fast_math)
4239 && rtx_equal_p (XEXP (cond, 0), true)
4240 && rtx_equal_p (XEXP (cond, 1), false)
4241 && ! side_effects_p (cond))
4246 return gen_binary (SMAX, mode, true, false);
4249 return gen_binary (SMIN, mode, true, false);
4252 return gen_binary (UMAX, mode, true, false);
4255 return gen_binary (UMIN, mode, true, false);
4258 /* If we have (if_then_else COND (OP Z C1) Z) and OP is an identity when its
4259 second operand is zero, this can be done as (OP Z (mult COND C2)) where
4260 C2 = C1 * STORE_FLAG_VALUE. Similarly if OP has an outer ZERO_EXTEND or
4261 SIGN_EXTEND as long as Z is already extended (so we don't destroy it).
4262 We can do this kind of thing in some cases when STORE_FLAG_VALUE is
4263 neither 1 or -1, but it isn't worth checking for. */
4265 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
4266 && comparison_p && mode != VOIDmode && ! side_effects_p (x))
4268 rtx t = make_compound_operation (true, SET);
4269 rtx f = make_compound_operation (false, SET);
4270 rtx cond_op0 = XEXP (cond, 0);
4271 rtx cond_op1 = XEXP (cond, 1);
4272 enum rtx_code op, extend_op = NIL;
4273 enum machine_mode m = mode;
4276 if ((GET_CODE (t) == PLUS || GET_CODE (t) == MINUS
4277 || GET_CODE (t) == IOR || GET_CODE (t) == XOR
4278 || GET_CODE (t) == ASHIFT
4279 || GET_CODE (t) == LSHIFTRT || GET_CODE (t) == ASHIFTRT)
4280 && rtx_equal_p (XEXP (t, 0), f))
4281 c1 = XEXP (t, 1), op = GET_CODE (t), z = f;
4283 /* If an identity-zero op is commutative, check whether there
4284 would be a match if we swapped the operands. */
4285 else if ((GET_CODE (t) == PLUS || GET_CODE (t) == IOR
4286 || GET_CODE (t) == XOR)
4287 && rtx_equal_p (XEXP (t, 1), f))
4288 c1 = XEXP (t, 0), op = GET_CODE (t), z = f;
4289 else if (GET_CODE (t) == SIGN_EXTEND
4290 && (GET_CODE (XEXP (t, 0)) == PLUS
4291 || GET_CODE (XEXP (t, 0)) == MINUS
4292 || GET_CODE (XEXP (t, 0)) == IOR
4293 || GET_CODE (XEXP (t, 0)) == XOR
4294 || GET_CODE (XEXP (t, 0)) == ASHIFT
4295 || GET_CODE (XEXP (t, 0)) == LSHIFTRT
4296 || GET_CODE (XEXP (t, 0)) == ASHIFTRT)
4297 && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG
4298 && subreg_lowpart_p (XEXP (XEXP (t, 0), 0))
4299 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f)
4300 && (num_sign_bit_copies (f, GET_MODE (f))
4301 > (GET_MODE_BITSIZE (mode)
4302 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t, 0), 0))))))
4304 c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0));
4305 extend_op = SIGN_EXTEND;
4306 m = GET_MODE (XEXP (t, 0));
4308 else if (GET_CODE (t) == SIGN_EXTEND
4309 && (GET_CODE (XEXP (t, 0)) == PLUS
4310 || GET_CODE (XEXP (t, 0)) == IOR
4311 || GET_CODE (XEXP (t, 0)) == XOR)
4312 && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG
4313 && subreg_lowpart_p (XEXP (XEXP (t, 0), 1))
4314 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f)
4315 && (num_sign_bit_copies (f, GET_MODE (f))
4316 > (GET_MODE_BITSIZE (mode)
4317 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t, 0), 1))))))
4319 c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0));
4320 extend_op = SIGN_EXTEND;
4321 m = GET_MODE (XEXP (t, 0));
4323 else if (GET_CODE (t) == ZERO_EXTEND
4324 && (GET_CODE (XEXP (t, 0)) == PLUS
4325 || GET_CODE (XEXP (t, 0)) == MINUS
4326 || GET_CODE (XEXP (t, 0)) == IOR
4327 || GET_CODE (XEXP (t, 0)) == XOR
4328 || GET_CODE (XEXP (t, 0)) == ASHIFT
4329 || GET_CODE (XEXP (t, 0)) == LSHIFTRT
4330 || GET_CODE (XEXP (t, 0)) == ASHIFTRT)
4331 && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG
4332 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4333 && subreg_lowpart_p (XEXP (XEXP (t, 0), 0))
4334 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f)
4335 && ((nonzero_bits (f, GET_MODE (f))
4336 & ~ GET_MODE_MASK (GET_MODE (XEXP (XEXP (t, 0), 0))))
4339 c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0));
4340 extend_op = ZERO_EXTEND;
4341 m = GET_MODE (XEXP (t, 0));
4343 else if (GET_CODE (t) == ZERO_EXTEND
4344 && (GET_CODE (XEXP (t, 0)) == PLUS
4345 || GET_CODE (XEXP (t, 0)) == IOR
4346 || GET_CODE (XEXP (t, 0)) == XOR)
4347 && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG
4348 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4349 && subreg_lowpart_p (XEXP (XEXP (t, 0), 1))
4350 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f)
4351 && ((nonzero_bits (f, GET_MODE (f))
4352 & ~ GET_MODE_MASK (GET_MODE (XEXP (XEXP (t, 0), 1))))
4355 c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0));
4356 extend_op = ZERO_EXTEND;
4357 m = GET_MODE (XEXP (t, 0));
4362 temp = subst (gen_binary (true_code, m, cond_op0, cond_op1),
4363 pc_rtx, pc_rtx, 0, 0);
4364 temp = gen_binary (MULT, m, temp,
4365 gen_binary (MULT, m, c1, const_true_rtx));
4366 temp = subst (temp, pc_rtx, pc_rtx, 0, 0);
4367 temp = gen_binary (op, m, gen_lowpart_for_combine (m, z), temp);
4369 if (extend_op != NIL)
4370 temp = gen_unary (extend_op, mode, m, temp);
4376 /* If we have (if_then_else (ne A 0) C1 0) and either A is known to be 0 or
4377 1 and C1 is a single bit or A is known to be 0 or -1 and C1 is the
4378 negation of a single bit, we can convert this operation to a shift. We
4379 can actually do this more generally, but it doesn't seem worth it. */
4381 if (true_code == NE && XEXP (cond, 1) == const0_rtx
4382 && false == const0_rtx && GET_CODE (true) == CONST_INT
4383 && ((1 == nonzero_bits (XEXP (cond, 0), mode)
4384 && (i = exact_log2 (INTVAL (true))) >= 0)
4385 || ((num_sign_bit_copies (XEXP (cond, 0), mode)
4386 == GET_MODE_BITSIZE (mode))
4387 && (i = exact_log2 (- INTVAL (true))) >= 0)))
4389 simplify_shift_const (NULL_RTX, ASHIFT, mode,
4390 gen_lowpart_for_combine (mode, XEXP (cond, 0)), i);
4395 /* Simplify X, a SET expression. Return the new expression. */
4401 rtx src = SET_SRC (x);
4402 rtx dest = SET_DEST (x);
4403 enum machine_mode mode
4404 = GET_MODE (src) != VOIDmode ? GET_MODE (src) : GET_MODE (dest);
4408 /* (set (pc) (return)) gets written as (return). */
4409 if (GET_CODE (dest) == PC && GET_CODE (src) == RETURN)
4412 /* Now that we know for sure which bits of SRC we are using, see if we can
4413 simplify the expression for the object knowing that we only need the
4416 if (GET_MODE_CLASS (mode) == MODE_INT)
4417 src = force_to_mode (src, mode, GET_MODE_MASK (mode), NULL_RTX, 0);
4419 /* If we are setting CC0 or if the source is a COMPARE, look for the use of
4420 the comparison result and try to simplify it unless we already have used
4421 undobuf.other_insn. */
4422 if ((GET_CODE (src) == COMPARE
4427 && (cc_use = find_single_use (dest, subst_insn, &other_insn)) != 0
4428 && (undobuf.other_insn == 0 || other_insn == undobuf.other_insn)
4429 && GET_RTX_CLASS (GET_CODE (*cc_use)) == '<'
4430 && rtx_equal_p (XEXP (*cc_use, 0), dest))
4432 enum rtx_code old_code = GET_CODE (*cc_use);
4433 enum rtx_code new_code;
4435 int other_changed = 0;
4436 enum machine_mode compare_mode = GET_MODE (dest);
4438 if (GET_CODE (src) == COMPARE)
4439 op0 = XEXP (src, 0), op1 = XEXP (src, 1);
4441 op0 = src, op1 = const0_rtx;
4443 /* Simplify our comparison, if possible. */
4444 new_code = simplify_comparison (old_code, &op0, &op1);
4446 #ifdef EXTRA_CC_MODES
4447 /* If this machine has CC modes other than CCmode, check to see if we
4448 need to use a different CC mode here. */
4449 compare_mode = SELECT_CC_MODE (new_code, op0, op1);
4450 #endif /* EXTRA_CC_MODES */
4452 #if !defined (HAVE_cc0) && defined (EXTRA_CC_MODES)
4453 /* If the mode changed, we have to change SET_DEST, the mode in the
4454 compare, and the mode in the place SET_DEST is used. If SET_DEST is
4455 a hard register, just build new versions with the proper mode. If it
4456 is a pseudo, we lose unless it is only time we set the pseudo, in
4457 which case we can safely change its mode. */
4458 if (compare_mode != GET_MODE (dest))
4460 int regno = REGNO (dest);
4461 rtx new_dest = gen_rtx (REG, compare_mode, regno);
4463 if (regno < FIRST_PSEUDO_REGISTER
4464 || (REG_N_SETS (regno) == 1 && ! REG_USERVAR_P (dest)))
4466 if (regno >= FIRST_PSEUDO_REGISTER)
4467 SUBST (regno_reg_rtx[regno], new_dest);
4469 SUBST (SET_DEST (x), new_dest);
4470 SUBST (XEXP (*cc_use, 0), new_dest);
4478 /* If the code changed, we have to build a new comparison in
4479 undobuf.other_insn. */
4480 if (new_code != old_code)
4482 unsigned HOST_WIDE_INT mask;
4484 SUBST (*cc_use, gen_rtx_combine (new_code, GET_MODE (*cc_use),
4487 /* If the only change we made was to change an EQ into an NE or
4488 vice versa, OP0 has only one bit that might be nonzero, and OP1
4489 is zero, check if changing the user of the condition code will
4490 produce a valid insn. If it won't, we can keep the original code
4491 in that insn by surrounding our operation with an XOR. */
4493 if (((old_code == NE && new_code == EQ)
4494 || (old_code == EQ && new_code == NE))
4495 && ! other_changed && op1 == const0_rtx
4496 && GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
4497 && exact_log2 (mask = nonzero_bits (op0, GET_MODE (op0))) >= 0)
4499 rtx pat = PATTERN (other_insn), note = 0;
4502 if ((recog_for_combine (&pat, other_insn, ¬e, &scratches) < 0
4503 && ! check_asm_operands (pat)))
4505 PUT_CODE (*cc_use, old_code);
4508 op0 = gen_binary (XOR, GET_MODE (op0), op0, GEN_INT (mask));
4516 undobuf.other_insn = other_insn;
4519 /* If we are now comparing against zero, change our source if
4520 needed. If we do not use cc0, we always have a COMPARE. */
4521 if (op1 == const0_rtx && dest == cc0_rtx)
4523 SUBST (SET_SRC (x), op0);
4529 /* Otherwise, if we didn't previously have a COMPARE in the
4530 correct mode, we need one. */
4531 if (GET_CODE (src) != COMPARE || GET_MODE (src) != compare_mode)
4534 gen_rtx_combine (COMPARE, compare_mode, op0, op1));
4539 /* Otherwise, update the COMPARE if needed. */
4540 SUBST (XEXP (src, 0), op0);
4541 SUBST (XEXP (src, 1), op1);
4546 /* Get SET_SRC in a form where we have placed back any
4547 compound expressions. Then do the checks below. */
4548 src = make_compound_operation (src, SET);
4549 SUBST (SET_SRC (x), src);
4552 /* If we have (set x (subreg:m1 (op:m2 ...) 0)) with OP being some operation,
4553 and X being a REG or (subreg (reg)), we may be able to convert this to
4554 (set (subreg:m2 x) (op)).
4556 We can always do this if M1 is narrower than M2 because that means that
4557 we only care about the low bits of the result.
4559 However, on machines without WORD_REGISTER_OPERATIONS defined, we cannot
4560 perform a narrower operation that requested since the high-order bits will
4561 be undefined. On machine where it is defined, this transformation is safe
4562 as long as M1 and M2 have the same number of words. */
4564 if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src)
4565 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (src))) != 'o'
4566 && (((GET_MODE_SIZE (GET_MODE (src)) + (UNITS_PER_WORD - 1))
4568 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (src)))
4569 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD))
4570 #ifndef WORD_REGISTER_OPERATIONS
4571 && (GET_MODE_SIZE (GET_MODE (src))
4572 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (src))))
4574 #ifdef CLASS_CANNOT_CHANGE_SIZE
4575 && ! (GET_CODE (dest) == REG && REGNO (dest) < FIRST_PSEUDO_REGISTER
4576 && (TEST_HARD_REG_BIT
4577 (reg_class_contents[(int) CLASS_CANNOT_CHANGE_SIZE],
4579 && (GET_MODE_SIZE (GET_MODE (src))
4580 != GET_MODE_SIZE (GET_MODE (SUBREG_REG (src)))))
4582 && (GET_CODE (dest) == REG
4583 || (GET_CODE (dest) == SUBREG
4584 && GET_CODE (SUBREG_REG (dest)) == REG)))
4586 SUBST (SET_DEST (x),
4587 gen_lowpart_for_combine (GET_MODE (SUBREG_REG (src)),
4589 SUBST (SET_SRC (x), SUBREG_REG (src));
4591 src = SET_SRC (x), dest = SET_DEST (x);
4594 #ifdef LOAD_EXTEND_OP
4595 /* If we have (set FOO (subreg:M (mem:N BAR) 0)) with M wider than N, this
4596 would require a paradoxical subreg. Replace the subreg with a
4597 zero_extend to avoid the reload that would otherwise be required. */
4599 if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src)
4600 && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src))) != NIL
4601 && SUBREG_WORD (src) == 0
4602 && (GET_MODE_SIZE (GET_MODE (src))
4603 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (src))))
4604 && GET_CODE (SUBREG_REG (src)) == MEM)
4607 gen_rtx_combine (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src))),
4608 GET_MODE (src), XEXP (src, 0)));
4614 /* If we don't have a conditional move, SET_SRC is an IF_THEN_ELSE, and we
4615 are comparing an item known to be 0 or -1 against 0, use a logical
4616 operation instead. Check for one of the arms being an IOR of the other
4617 arm with some value. We compute three terms to be IOR'ed together. In
4618 practice, at most two will be nonzero. Then we do the IOR's. */
4620 if (GET_CODE (dest) != PC
4621 && GET_CODE (src) == IF_THEN_ELSE
4622 && GET_MODE_CLASS (GET_MODE (src)) == MODE_INT
4623 && (GET_CODE (XEXP (src, 0)) == EQ || GET_CODE (XEXP (src, 0)) == NE)
4624 && XEXP (XEXP (src, 0), 1) == const0_rtx
4625 && GET_MODE (src) == GET_MODE (XEXP (XEXP (src, 0), 0))
4626 #ifdef HAVE_conditional_move
4627 && ! can_conditionally_move_p (GET_MODE (src))
4629 && (num_sign_bit_copies (XEXP (XEXP (src, 0), 0),
4630 GET_MODE (XEXP (XEXP (src, 0), 0)))
4631 == GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (src, 0), 0))))
4632 && ! side_effects_p (src))
4634 rtx true = (GET_CODE (XEXP (src, 0)) == NE
4635 ? XEXP (src, 1) : XEXP (src, 2));
4636 rtx false = (GET_CODE (XEXP (src, 0)) == NE
4637 ? XEXP (src, 2) : XEXP (src, 1));
4638 rtx term1 = const0_rtx, term2, term3;
4640 if (GET_CODE (true) == IOR && rtx_equal_p (XEXP (true, 0), false))
4641 term1 = false, true = XEXP (true, 1), false = const0_rtx;
4642 else if (GET_CODE (true) == IOR
4643 && rtx_equal_p (XEXP (true, 1), false))
4644 term1 = false, true = XEXP (true, 0), false = const0_rtx;
4645 else if (GET_CODE (false) == IOR
4646 && rtx_equal_p (XEXP (false, 0), true))
4647 term1 = true, false = XEXP (false, 1), true = const0_rtx;
4648 else if (GET_CODE (false) == IOR
4649 && rtx_equal_p (XEXP (false, 1), true))
4650 term1 = true, false = XEXP (false, 0), true = const0_rtx;
4652 term2 = gen_binary (AND, GET_MODE (src), XEXP (XEXP (src, 0), 0), true);
4653 term3 = gen_binary (AND, GET_MODE (src),
4654 gen_unary (NOT, GET_MODE (src), GET_MODE (src),
4655 XEXP (XEXP (src, 0), 0)),
4659 gen_binary (IOR, GET_MODE (src),
4660 gen_binary (IOR, GET_MODE (src), term1, term2),
4666 /* If either SRC or DEST is a CLOBBER of (const_int 0), make this
4667 whole thing fail. */
4668 if (GET_CODE (src) == CLOBBER && XEXP (src, 0) == const0_rtx)
4670 else if (GET_CODE (dest) == CLOBBER && XEXP (dest, 0) == const0_rtx)
4673 /* Convert this into a field assignment operation, if possible. */
4674 return make_field_assignment (x);
4677 /* Simplify, X, and AND, IOR, or XOR operation, and return the simplified
4678 result. LAST is nonzero if this is the last retry. */
4681 simplify_logical (x, last)
4685 enum machine_mode mode = GET_MODE (x);
4686 rtx op0 = XEXP (x, 0);
4687 rtx op1 = XEXP (x, 1);
4689 switch (GET_CODE (x))
4692 /* Convert (A ^ B) & A to A & (~ B) since the latter is often a single
4693 insn (and may simplify more). */
4694 if (GET_CODE (op0) == XOR
4695 && rtx_equal_p (XEXP (op0, 0), op1)
4696 && ! side_effects_p (op1))
4697 x = gen_binary (AND, mode,
4698 gen_unary (NOT, mode, mode, XEXP (op0, 1)), op1);
4700 if (GET_CODE (op0) == XOR
4701 && rtx_equal_p (XEXP (op0, 1), op1)
4702 && ! side_effects_p (op1))
4703 x = gen_binary (AND, mode,
4704 gen_unary (NOT, mode, mode, XEXP (op0, 0)), op1);
4706 /* Similarly for (~ (A ^ B)) & A. */
4707 if (GET_CODE (op0) == NOT
4708 && GET_CODE (XEXP (op0, 0)) == XOR
4709 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), op1)
4710 && ! side_effects_p (op1))
4711 x = gen_binary (AND, mode, XEXP (XEXP (op0, 0), 1), op1);
4713 if (GET_CODE (op0) == NOT
4714 && GET_CODE (XEXP (op0, 0)) == XOR
4715 && rtx_equal_p (XEXP (XEXP (op0, 0), 1), op1)
4716 && ! side_effects_p (op1))
4717 x = gen_binary (AND, mode, XEXP (XEXP (op0, 0), 0), op1);
4719 if (GET_CODE (op1) == CONST_INT)
4721 x = simplify_and_const_int (x, mode, op0, INTVAL (op1));
4723 /* If we have (ior (and (X C1) C2)) and the next restart would be
4724 the last, simplify this by making C1 as small as possible
4727 && GET_CODE (x) == IOR && GET_CODE (op0) == AND
4728 && GET_CODE (XEXP (op0, 1)) == CONST_INT
4729 && GET_CODE (op1) == CONST_INT)
4730 return gen_binary (IOR, mode,
4731 gen_binary (AND, mode, XEXP (op0, 0),
4732 GEN_INT (INTVAL (XEXP (op0, 1))
4733 & ~ INTVAL (op1))), op1);
4735 if (GET_CODE (x) != AND)
4738 if (GET_RTX_CLASS (GET_CODE (x)) == 'c'
4739 || GET_RTX_CLASS (GET_CODE (x)) == '2')
4740 op0 = XEXP (x, 0), op1 = XEXP (x, 1);
4743 /* Convert (A | B) & A to A. */
4744 if (GET_CODE (op0) == IOR
4745 && (rtx_equal_p (XEXP (op0, 0), op1)
4746 || rtx_equal_p (XEXP (op0, 1), op1))
4747 && ! side_effects_p (XEXP (op0, 0))
4748 && ! side_effects_p (XEXP (op0, 1)))
4751 /* In the following group of tests (and those in case IOR below),
4752 we start with some combination of logical operations and apply
4753 the distributive law followed by the inverse distributive law.
4754 Most of the time, this results in no change. However, if some of
4755 the operands are the same or inverses of each other, simplifications
4758 For example, (and (ior A B) (not B)) can occur as the result of
4759 expanding a bit field assignment. When we apply the distributive
4760 law to this, we get (ior (and (A (not B))) (and (B (not B)))),
4761 which then simplifies to (and (A (not B))).
4763 If we have (and (ior A B) C), apply the distributive law and then
4764 the inverse distributive law to see if things simplify. */
4766 if (GET_CODE (op0) == IOR || GET_CODE (op0) == XOR)
4768 x = apply_distributive_law
4769 (gen_binary (GET_CODE (op0), mode,
4770 gen_binary (AND, mode, XEXP (op0, 0), op1),
4771 gen_binary (AND, mode, XEXP (op0, 1), op1)));
4772 if (GET_CODE (x) != AND)
4776 if (GET_CODE (op1) == IOR || GET_CODE (op1) == XOR)
4777 return apply_distributive_law
4778 (gen_binary (GET_CODE (op1), mode,
4779 gen_binary (AND, mode, XEXP (op1, 0), op0),
4780 gen_binary (AND, mode, XEXP (op1, 1), op0)));
4782 /* Similarly, taking advantage of the fact that
4783 (and (not A) (xor B C)) == (xor (ior A B) (ior A C)) */
4785 if (GET_CODE (op0) == NOT && GET_CODE (op1) == XOR)
4786 return apply_distributive_law
4787 (gen_binary (XOR, mode,
4788 gen_binary (IOR, mode, XEXP (op0, 0), XEXP (op1, 0)),
4789 gen_binary (IOR, mode, XEXP (op0, 0), XEXP (op1, 1))));
4791 else if (GET_CODE (op1) == NOT && GET_CODE (op0) == XOR)
4792 return apply_distributive_law
4793 (gen_binary (XOR, mode,
4794 gen_binary (IOR, mode, XEXP (op1, 0), XEXP (op0, 0)),
4795 gen_binary (IOR, mode, XEXP (op1, 0), XEXP (op0, 1))));
4799 /* (ior A C) is C if all bits of A that might be nonzero are on in C. */
4800 if (GET_CODE (op1) == CONST_INT
4801 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4802 && (nonzero_bits (op0, mode) & ~ INTVAL (op1)) == 0)
4805 /* Convert (A & B) | A to A. */
4806 if (GET_CODE (op0) == AND
4807 && (rtx_equal_p (XEXP (op0, 0), op1)
4808 || rtx_equal_p (XEXP (op0, 1), op1))
4809 && ! side_effects_p (XEXP (op0, 0))
4810 && ! side_effects_p (XEXP (op0, 1)))
4813 /* If we have (ior (and A B) C), apply the distributive law and then
4814 the inverse distributive law to see if things simplify. */
4816 if (GET_CODE (op0) == AND)
4818 x = apply_distributive_law
4819 (gen_binary (AND, mode,
4820 gen_binary (IOR, mode, XEXP (op0, 0), op1),
4821 gen_binary (IOR, mode, XEXP (op0, 1), op1)));
4823 if (GET_CODE (x) != IOR)
4827 if (GET_CODE (op1) == AND)
4829 x = apply_distributive_law
4830 (gen_binary (AND, mode,
4831 gen_binary (IOR, mode, XEXP (op1, 0), op0),
4832 gen_binary (IOR, mode, XEXP (op1, 1), op0)));
4834 if (GET_CODE (x) != IOR)
4838 /* Convert (ior (ashift A CX) (lshiftrt A CY)) where CX+CY equals the
4839 mode size to (rotate A CX). */
4841 if (((GET_CODE (op0) == ASHIFT && GET_CODE (op1) == LSHIFTRT)
4842 || (GET_CODE (op1) == ASHIFT && GET_CODE (op0) == LSHIFTRT))
4843 && rtx_equal_p (XEXP (op0, 0), XEXP (op1, 0))
4844 && GET_CODE (XEXP (op0, 1)) == CONST_INT
4845 && GET_CODE (XEXP (op1, 1)) == CONST_INT
4846 && (INTVAL (XEXP (op0, 1)) + INTVAL (XEXP (op1, 1))
4847 == GET_MODE_BITSIZE (mode)))
4848 return gen_rtx (ROTATE, mode, XEXP (op0, 0),
4849 (GET_CODE (op0) == ASHIFT
4850 ? XEXP (op0, 1) : XEXP (op1, 1)));
4852 /* If OP0 is (ashiftrt (plus ...) C), it might actually be
4853 a (sign_extend (plus ...)). If so, OP1 is a CONST_INT, and the PLUS
4854 does not affect any of the bits in OP1, it can really be done
4855 as a PLUS and we can associate. We do this by seeing if OP1
4856 can be safely shifted left C bits. */
4857 if (GET_CODE (op1) == CONST_INT && GET_CODE (op0) == ASHIFTRT
4858 && GET_CODE (XEXP (op0, 0)) == PLUS
4859 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
4860 && GET_CODE (XEXP (op0, 1)) == CONST_INT
4861 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT)
4863 int count = INTVAL (XEXP (op0, 1));
4864 HOST_WIDE_INT mask = INTVAL (op1) << count;
4866 if (mask >> count == INTVAL (op1)
4867 && (mask & nonzero_bits (XEXP (op0, 0), mode)) == 0)
4869 SUBST (XEXP (XEXP (op0, 0), 1),
4870 GEN_INT (INTVAL (XEXP (XEXP (op0, 0), 1)) | mask));
4877 /* Convert (XOR (NOT x) (NOT y)) to (XOR x y).
4878 Also convert (XOR (NOT x) y) to (NOT (XOR x y)), similarly for
4881 int num_negated = 0;
4883 if (GET_CODE (op0) == NOT)
4884 num_negated++, op0 = XEXP (op0, 0);
4885 if (GET_CODE (op1) == NOT)
4886 num_negated++, op1 = XEXP (op1, 0);
4888 if (num_negated == 2)
4890 SUBST (XEXP (x, 0), op0);
4891 SUBST (XEXP (x, 1), op1);
4893 else if (num_negated == 1)
4894 return gen_unary (NOT, mode, mode, gen_binary (XOR, mode, op0, op1));
4897 /* Convert (xor (and A B) B) to (and (not A) B). The latter may
4898 correspond to a machine insn or result in further simplifications
4899 if B is a constant. */
4901 if (GET_CODE (op0) == AND
4902 && rtx_equal_p (XEXP (op0, 1), op1)
4903 && ! side_effects_p (op1))
4904 return gen_binary (AND, mode,
4905 gen_unary (NOT, mode, mode, XEXP (op0, 0)),
4908 else if (GET_CODE (op0) == AND
4909 && rtx_equal_p (XEXP (op0, 0), op1)
4910 && ! side_effects_p (op1))
4911 return gen_binary (AND, mode,
4912 gen_unary (NOT, mode, mode, XEXP (op0, 1)),
4915 /* (xor (comparison foo bar) (const_int 1)) can become the reversed
4916 comparison if STORE_FLAG_VALUE is 1. */
4917 if (STORE_FLAG_VALUE == 1
4918 && op1 == const1_rtx
4919 && GET_RTX_CLASS (GET_CODE (op0)) == '<'
4920 && reversible_comparison_p (op0))
4921 return gen_rtx_combine (reverse_condition (GET_CODE (op0)),
4922 mode, XEXP (op0, 0), XEXP (op0, 1));
4924 /* (lshiftrt foo C) where C is the number of bits in FOO minus 1
4925 is (lt foo (const_int 0)), so we can perform the above
4926 simplification if STORE_FLAG_VALUE is 1. */
4928 if (STORE_FLAG_VALUE == 1
4929 && op1 == const1_rtx
4930 && GET_CODE (op0) == LSHIFTRT
4931 && GET_CODE (XEXP (op0, 1)) == CONST_INT
4932 && INTVAL (XEXP (op0, 1)) == GET_MODE_BITSIZE (mode) - 1)
4933 return gen_rtx_combine (GE, mode, XEXP (op0, 0), const0_rtx);
4935 /* (xor (comparison foo bar) (const_int sign-bit))
4936 when STORE_FLAG_VALUE is the sign bit. */
4937 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4938 && ((STORE_FLAG_VALUE & GET_MODE_MASK (mode))
4939 == (HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (mode) - 1))
4940 && op1 == const_true_rtx
4941 && GET_RTX_CLASS (GET_CODE (op0)) == '<'
4942 && reversible_comparison_p (op0))
4943 return gen_rtx_combine (reverse_condition (GET_CODE (op0)),
4944 mode, XEXP (op0, 0), XEXP (op0, 1));
4951 /* We consider ZERO_EXTRACT, SIGN_EXTRACT, and SIGN_EXTEND as "compound
4952 operations" because they can be replaced with two more basic operations.
4953 ZERO_EXTEND is also considered "compound" because it can be replaced with
4954 an AND operation, which is simpler, though only one operation.
4956 The function expand_compound_operation is called with an rtx expression
4957 and will convert it to the appropriate shifts and AND operations,
4958 simplifying at each stage.
4960 The function make_compound_operation is called to convert an expression
4961 consisting of shifts and ANDs into the equivalent compound expression.
4962 It is the inverse of this function, loosely speaking. */
4965 expand_compound_operation (x)
4973 switch (GET_CODE (x))
4978 /* We can't necessarily use a const_int for a multiword mode;
4979 it depends on implicitly extending the value.
4980 Since we don't know the right way to extend it,
4981 we can't tell whether the implicit way is right.
4983 Even for a mode that is no wider than a const_int,
4984 we can't win, because we need to sign extend one of its bits through
4985 the rest of it, and we don't know which bit. */
4986 if (GET_CODE (XEXP (x, 0)) == CONST_INT)
4989 /* Return if (subreg:MODE FROM 0) is not a safe replacement for
4990 (zero_extend:MODE FROM) or (sign_extend:MODE FROM). It is for any MEM
4991 because (SUBREG (MEM...)) is guaranteed to cause the MEM to be
4992 reloaded. If not for that, MEM's would very rarely be safe.
4994 Reject MODEs bigger than a word, because we might not be able
4995 to reference a two-register group starting with an arbitrary register
4996 (and currently gen_lowpart might crash for a SUBREG). */
4998 if (GET_MODE_SIZE (GET_MODE (XEXP (x, 0))) > UNITS_PER_WORD)
5001 len = GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)));
5002 /* If the inner object has VOIDmode (the only way this can happen
5003 is if it is a ASM_OPERANDS), we can't do anything since we don't
5004 know how much masking to do. */
5013 /* If the operand is a CLOBBER, just return it. */
5014 if (GET_CODE (XEXP (x, 0)) == CLOBBER)
5017 if (GET_CODE (XEXP (x, 1)) != CONST_INT
5018 || GET_CODE (XEXP (x, 2)) != CONST_INT
5019 || GET_MODE (XEXP (x, 0)) == VOIDmode)
5022 len = INTVAL (XEXP (x, 1));
5023 pos = INTVAL (XEXP (x, 2));
5025 /* If this goes outside the object being extracted, replace the object
5026 with a (use (mem ...)) construct that only combine understands
5027 and is used only for this purpose. */
5028 if (len + pos > GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))))
5029 SUBST (XEXP (x, 0), gen_rtx (USE, GET_MODE (x), XEXP (x, 0)));
5031 if (BITS_BIG_ENDIAN)
5032 pos = GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - len - pos;
5040 /* We can optimize some special cases of ZERO_EXTEND. */
5041 if (GET_CODE (x) == ZERO_EXTEND)
5043 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI if we
5044 know that the last value didn't have any inappropriate bits
5046 if (GET_CODE (XEXP (x, 0)) == TRUNCATE
5047 && GET_MODE (XEXP (XEXP (x, 0), 0)) == GET_MODE (x)
5048 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
5049 && (nonzero_bits (XEXP (XEXP (x, 0), 0), GET_MODE (x))
5050 & ~ GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5051 return XEXP (XEXP (x, 0), 0);
5053 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
5054 if (GET_CODE (XEXP (x, 0)) == SUBREG
5055 && GET_MODE (SUBREG_REG (XEXP (x, 0))) == GET_MODE (x)
5056 && subreg_lowpart_p (XEXP (x, 0))
5057 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
5058 && (nonzero_bits (SUBREG_REG (XEXP (x, 0)), GET_MODE (x))
5059 & ~ GET_MODE_MASK (GET_MODE (SUBREG_REG (x)))) == 0)
5060 return SUBREG_REG (XEXP (x, 0));
5062 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI when foo
5063 is a comparison and STORE_FLAG_VALUE permits. This is like
5064 the first case, but it works even when GET_MODE (x) is larger
5065 than HOST_WIDE_INT. */
5066 if (GET_CODE (XEXP (x, 0)) == TRUNCATE
5067 && GET_MODE (XEXP (XEXP (x, 0), 0)) == GET_MODE (x)
5068 && GET_RTX_CLASS (GET_CODE (XEXP (XEXP (x, 0), 0))) == '<'
5069 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
5070 <= HOST_BITS_PER_WIDE_INT)
5071 && ((HOST_WIDE_INT) STORE_FLAG_VALUE
5072 & ~ GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5073 return XEXP (XEXP (x, 0), 0);
5075 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
5076 if (GET_CODE (XEXP (x, 0)) == SUBREG
5077 && GET_MODE (SUBREG_REG (XEXP (x, 0))) == GET_MODE (x)
5078 && subreg_lowpart_p (XEXP (x, 0))
5079 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 0)))) == '<'
5080 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
5081 <= HOST_BITS_PER_WIDE_INT)
5082 && ((HOST_WIDE_INT) STORE_FLAG_VALUE
5083 & ~ GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5084 return SUBREG_REG (XEXP (x, 0));
5086 /* If sign extension is cheaper than zero extension, then use it
5087 if we know that no extraneous bits are set, and that the high
5089 if (flag_expensive_optimizations
5090 && ((GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
5091 && ((nonzero_bits (XEXP (x, 0), GET_MODE (x))
5092 & ~ (((unsigned HOST_WIDE_INT)
5093 GET_MODE_MASK (GET_MODE (XEXP (x, 0))))
5096 || (GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
5097 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
5098 <= HOST_BITS_PER_WIDE_INT)
5099 && (((HOST_WIDE_INT) STORE_FLAG_VALUE
5100 & ~ (((unsigned HOST_WIDE_INT)
5101 GET_MODE_MASK (GET_MODE (XEXP (x, 0))))
5105 rtx temp = gen_rtx (SIGN_EXTEND, GET_MODE (x), XEXP (x, 0));
5107 if (rtx_cost (temp, SET) < rtx_cost (x, SET))
5108 return expand_compound_operation (temp);
5112 /* If we reach here, we want to return a pair of shifts. The inner
5113 shift is a left shift of BITSIZE - POS - LEN bits. The outer
5114 shift is a right shift of BITSIZE - LEN bits. It is arithmetic or
5115 logical depending on the value of UNSIGNEDP.
5117 If this was a ZERO_EXTEND or ZERO_EXTRACT, this pair of shifts will be
5118 converted into an AND of a shift.
5120 We must check for the case where the left shift would have a negative
5121 count. This can happen in a case like (x >> 31) & 255 on machines
5122 that can't shift by a constant. On those machines, we would first
5123 combine the shift with the AND to produce a variable-position
5124 extraction. Then the constant of 31 would be substituted in to produce
5125 a such a position. */
5127 modewidth = GET_MODE_BITSIZE (GET_MODE (x));
5128 if (modewidth >= pos - len)
5129 tem = simplify_shift_const (NULL_RTX, unsignedp ? LSHIFTRT : ASHIFTRT,
5131 simplify_shift_const (NULL_RTX, ASHIFT,
5134 modewidth - pos - len),
5137 else if (unsignedp && len < HOST_BITS_PER_WIDE_INT)
5138 tem = simplify_and_const_int (NULL_RTX, GET_MODE (x),
5139 simplify_shift_const (NULL_RTX, LSHIFTRT,
5142 ((HOST_WIDE_INT) 1 << len) - 1);
5144 /* Any other cases we can't handle. */
5148 /* If we couldn't do this for some reason, return the original
5150 if (GET_CODE (tem) == CLOBBER)
5156 /* X is a SET which contains an assignment of one object into
5157 a part of another (such as a bit-field assignment, STRICT_LOW_PART,
5158 or certain SUBREGS). If possible, convert it into a series of
5161 We half-heartedly support variable positions, but do not at all
5162 support variable lengths. */
5165 expand_field_assignment (x)
5169 rtx pos; /* Always counts from low bit. */
5172 enum machine_mode compute_mode;
5174 /* Loop until we find something we can't simplify. */
5177 if (GET_CODE (SET_DEST (x)) == STRICT_LOW_PART
5178 && GET_CODE (XEXP (SET_DEST (x), 0)) == SUBREG)
5180 inner = SUBREG_REG (XEXP (SET_DEST (x), 0));
5181 len = GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0)));
5182 pos = GEN_INT (BITS_PER_WORD * SUBREG_WORD (XEXP (SET_DEST (x), 0)));
5184 else if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
5185 && GET_CODE (XEXP (SET_DEST (x), 1)) == CONST_INT)
5187 inner = XEXP (SET_DEST (x), 0);
5188 len = INTVAL (XEXP (SET_DEST (x), 1));
5189 pos = XEXP (SET_DEST (x), 2);
5191 /* If the position is constant and spans the width of INNER,
5192 surround INNER with a USE to indicate this. */
5193 if (GET_CODE (pos) == CONST_INT
5194 && INTVAL (pos) + len > GET_MODE_BITSIZE (GET_MODE (inner)))
5195 inner = gen_rtx (USE, GET_MODE (SET_DEST (x)), inner);
5197 if (BITS_BIG_ENDIAN)
5199 if (GET_CODE (pos) == CONST_INT)
5200 pos = GEN_INT (GET_MODE_BITSIZE (GET_MODE (inner)) - len
5202 else if (GET_CODE (pos) == MINUS
5203 && GET_CODE (XEXP (pos, 1)) == CONST_INT
5204 && (INTVAL (XEXP (pos, 1))
5205 == GET_MODE_BITSIZE (GET_MODE (inner)) - len))
5206 /* If position is ADJUST - X, new position is X. */
5207 pos = XEXP (pos, 0);
5209 pos = gen_binary (MINUS, GET_MODE (pos),
5210 GEN_INT (GET_MODE_BITSIZE (GET_MODE (inner))
5216 /* A SUBREG between two modes that occupy the same numbers of words
5217 can be done by moving the SUBREG to the source. */
5218 else if (GET_CODE (SET_DEST (x)) == SUBREG
5219 && (((GET_MODE_SIZE (GET_MODE (SET_DEST (x)))
5220 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
5221 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x))))
5222 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)))
5224 x = gen_rtx (SET, VOIDmode, SUBREG_REG (SET_DEST (x)),
5225 gen_lowpart_for_combine (GET_MODE (SUBREG_REG (SET_DEST (x))),
5232 while (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
5233 inner = SUBREG_REG (inner);
5235 compute_mode = GET_MODE (inner);
5237 /* Compute a mask of LEN bits, if we can do this on the host machine. */
5238 if (len < HOST_BITS_PER_WIDE_INT)
5239 mask = GEN_INT (((HOST_WIDE_INT) 1 << len) - 1);
5243 /* Now compute the equivalent expression. Make a copy of INNER
5244 for the SET_DEST in case it is a MEM into which we will substitute;
5245 we don't want shared RTL in that case. */
5246 x = gen_rtx (SET, VOIDmode, copy_rtx (inner),
5247 gen_binary (IOR, compute_mode,
5248 gen_binary (AND, compute_mode,
5249 gen_unary (NOT, compute_mode,
5255 gen_binary (ASHIFT, compute_mode,
5256 gen_binary (AND, compute_mode,
5257 gen_lowpart_for_combine
5267 /* Return an RTX for a reference to LEN bits of INNER. If POS_RTX is nonzero,
5268 it is an RTX that represents a variable starting position; otherwise,
5269 POS is the (constant) starting bit position (counted from the LSB).
5271 INNER may be a USE. This will occur when we started with a bitfield
5272 that went outside the boundary of the object in memory, which is
5273 allowed on most machines. To isolate this case, we produce a USE
5274 whose mode is wide enough and surround the MEM with it. The only
5275 code that understands the USE is this routine. If it is not removed,
5276 it will cause the resulting insn not to match.
5278 UNSIGNEDP is non-zero for an unsigned reference and zero for a
5281 IN_DEST is non-zero if this is a reference in the destination of a
5282 SET. This is used when a ZERO_ or SIGN_EXTRACT isn't needed. If non-zero,
5283 a STRICT_LOW_PART will be used, if zero, ZERO_EXTEND or SIGN_EXTEND will
5286 IN_COMPARE is non-zero if we are in a COMPARE. This means that a
5287 ZERO_EXTRACT should be built even for bits starting at bit 0.
5289 MODE is the desired mode of the result (if IN_DEST == 0).
5291 The result is an RTX for the extraction or NULL_RTX if the target
5295 make_extraction (mode, inner, pos, pos_rtx, len,
5296 unsignedp, in_dest, in_compare)
5297 enum machine_mode mode;
5303 int in_dest, in_compare;
5305 /* This mode describes the size of the storage area
5306 to fetch the overall value from. Within that, we
5307 ignore the POS lowest bits, etc. */
5308 enum machine_mode is_mode = GET_MODE (inner);
5309 enum machine_mode inner_mode;
5310 enum machine_mode wanted_inner_mode = byte_mode;
5311 enum machine_mode wanted_inner_reg_mode = word_mode;
5312 enum machine_mode pos_mode = word_mode;
5313 enum machine_mode extraction_mode = word_mode;
5314 enum machine_mode tmode = mode_for_size (len, MODE_INT, 1);
5317 rtx orig_pos_rtx = pos_rtx;
5320 /* Get some information about INNER and get the innermost object. */
5321 if (GET_CODE (inner) == USE)
5322 /* (use:SI (mem:QI foo)) stands for (mem:SI foo). */
5323 /* We don't need to adjust the position because we set up the USE
5324 to pretend that it was a full-word object. */
5325 spans_byte = 1, inner = XEXP (inner, 0);
5326 else if (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
5328 /* If going from (subreg:SI (mem:QI ...)) to (mem:QI ...),
5329 consider just the QI as the memory to extract from.
5330 The subreg adds or removes high bits; its mode is
5331 irrelevant to the meaning of this extraction,
5332 since POS and LEN count from the lsb. */
5333 if (GET_CODE (SUBREG_REG (inner)) == MEM)
5334 is_mode = GET_MODE (SUBREG_REG (inner));
5335 inner = SUBREG_REG (inner);
5338 inner_mode = GET_MODE (inner);
5340 if (pos_rtx && GET_CODE (pos_rtx) == CONST_INT)
5341 pos = INTVAL (pos_rtx), pos_rtx = 0;
5343 /* See if this can be done without an extraction. We never can if the
5344 width of the field is not the same as that of some integer mode. For
5345 registers, we can only avoid the extraction if the position is at the
5346 low-order bit and this is either not in the destination or we have the
5347 appropriate STRICT_LOW_PART operation available.
5349 For MEM, we can avoid an extract if the field starts on an appropriate
5350 boundary and we can change the mode of the memory reference. However,
5351 we cannot directly access the MEM if we have a USE and the underlying
5352 MEM is not TMODE. This combination means that MEM was being used in a
5353 context where bits outside its mode were being referenced; that is only
5354 valid in bit-field insns. */
5356 if (tmode != BLKmode
5357 && ! (spans_byte && inner_mode != tmode)
5358 && ((pos_rtx == 0 && (pos % BITS_PER_WORD) == 0
5359 && GET_CODE (inner) != MEM
5361 || (GET_CODE (inner) == REG
5362 && (movstrict_optab->handlers[(int) tmode].insn_code
5363 != CODE_FOR_nothing))))
5364 || (GET_CODE (inner) == MEM && pos_rtx == 0
5366 % (STRICT_ALIGNMENT ? GET_MODE_ALIGNMENT (tmode)
5367 : BITS_PER_UNIT)) == 0
5368 /* We can't do this if we are widening INNER_MODE (it
5369 may not be aligned, for one thing). */
5370 && GET_MODE_BITSIZE (inner_mode) >= GET_MODE_BITSIZE (tmode)
5371 && (inner_mode == tmode
5372 || (! mode_dependent_address_p (XEXP (inner, 0))
5373 && ! MEM_VOLATILE_P (inner))))))
5375 /* If INNER is a MEM, make a new MEM that encompasses just the desired
5376 field. If the original and current mode are the same, we need not
5377 adjust the offset. Otherwise, we do if bytes big endian.
5379 If INNER is not a MEM, get a piece consisting of just the field
5380 of interest (in this case POS % BITS_PER_WORD must be 0). */
5382 if (GET_CODE (inner) == MEM)
5385 /* POS counts from lsb, but make OFFSET count in memory order. */
5386 if (BYTES_BIG_ENDIAN)
5387 offset = (GET_MODE_BITSIZE (is_mode) - len - pos) / BITS_PER_UNIT;
5389 offset = pos / BITS_PER_UNIT;
5391 new = gen_rtx (MEM, tmode, plus_constant (XEXP (inner, 0), offset));
5392 RTX_UNCHANGING_P (new) = RTX_UNCHANGING_P (inner);
5393 MEM_VOLATILE_P (new) = MEM_VOLATILE_P (inner);
5394 MEM_IN_STRUCT_P (new) = MEM_IN_STRUCT_P (inner);
5396 else if (GET_CODE (inner) == REG)
5398 /* We can't call gen_lowpart_for_combine here since we always want
5399 a SUBREG and it would sometimes return a new hard register. */
5400 if (tmode != inner_mode)
5401 new = gen_rtx (SUBREG, tmode, inner,
5403 && GET_MODE_SIZE (inner_mode) > UNITS_PER_WORD
5404 ? (((GET_MODE_SIZE (inner_mode)
5405 - GET_MODE_SIZE (tmode))
5407 - pos / BITS_PER_WORD)
5408 : pos / BITS_PER_WORD));
5413 new = force_to_mode (inner, tmode,
5414 len >= HOST_BITS_PER_WIDE_INT
5415 ? GET_MODE_MASK (tmode)
5416 : ((HOST_WIDE_INT) 1 << len) - 1,
5419 /* If this extraction is going into the destination of a SET,
5420 make a STRICT_LOW_PART unless we made a MEM. */
5423 return (GET_CODE (new) == MEM ? new
5424 : (GET_CODE (new) != SUBREG
5425 ? gen_rtx (CLOBBER, tmode, const0_rtx)
5426 : gen_rtx_combine (STRICT_LOW_PART, VOIDmode, new)));
5428 /* Otherwise, sign- or zero-extend unless we already are in the
5431 return (mode == tmode ? new
5432 : gen_rtx_combine (unsignedp ? ZERO_EXTEND : SIGN_EXTEND,
5436 /* Unless this is a COMPARE or we have a funny memory reference,
5437 don't do anything with zero-extending field extracts starting at
5438 the low-order bit since they are simple AND operations. */
5439 if (pos_rtx == 0 && pos == 0 && ! in_dest
5440 && ! in_compare && ! spans_byte && unsignedp)
5443 /* Unless we are allowed to span bytes, reject this if we would be
5444 spanning bytes or if the position is not a constant and the length
5445 is not 1. In all other cases, we would only be going outside
5446 out object in cases when an original shift would have been
5449 && ((pos_rtx == 0 && pos + len > GET_MODE_BITSIZE (is_mode))
5450 || (pos_rtx != 0 && len != 1)))
5453 /* Get the mode to use should INNER not be a MEM, the mode for the position,
5454 and the mode for the result. */
5458 wanted_inner_reg_mode = insn_operand_mode[(int) CODE_FOR_insv][0];
5459 pos_mode = insn_operand_mode[(int) CODE_FOR_insv][2];
5460 extraction_mode = insn_operand_mode[(int) CODE_FOR_insv][3];
5465 if (! in_dest && unsignedp)
5467 wanted_inner_reg_mode = insn_operand_mode[(int) CODE_FOR_extzv][1];
5468 pos_mode = insn_operand_mode[(int) CODE_FOR_extzv][3];
5469 extraction_mode = insn_operand_mode[(int) CODE_FOR_extzv][0];
5474 if (! in_dest && ! unsignedp)
5476 wanted_inner_reg_mode = insn_operand_mode[(int) CODE_FOR_extv][1];
5477 pos_mode = insn_operand_mode[(int) CODE_FOR_extv][3];
5478 extraction_mode = insn_operand_mode[(int) CODE_FOR_extv][0];
5482 /* Never narrow an object, since that might not be safe. */
5484 if (mode != VOIDmode
5485 && GET_MODE_SIZE (extraction_mode) < GET_MODE_SIZE (mode))
5486 extraction_mode = mode;
5488 if (pos_rtx && GET_MODE (pos_rtx) != VOIDmode
5489 && GET_MODE_SIZE (pos_mode) < GET_MODE_SIZE (GET_MODE (pos_rtx)))
5490 pos_mode = GET_MODE (pos_rtx);
5492 /* If this is not from memory, the desired mode is wanted_inner_reg_mode;
5493 if we have to change the mode of memory and cannot, the desired mode is
5495 if (GET_CODE (inner) != MEM)
5496 wanted_inner_mode = wanted_inner_reg_mode;
5497 else if (inner_mode != wanted_inner_mode
5498 && (mode_dependent_address_p (XEXP (inner, 0))
5499 || MEM_VOLATILE_P (inner)))
5500 wanted_inner_mode = extraction_mode;
5504 if (BITS_BIG_ENDIAN)
5506 /* POS is passed as if BITS_BIG_ENDIAN == 0, so we need to convert it to
5507 BITS_BIG_ENDIAN style. If position is constant, compute new
5508 position. Otherwise, build subtraction.
5509 Note that POS is relative to the mode of the original argument.
5510 If it's a MEM we need to recompute POS relative to that.
5511 However, if we're extracting from (or inserting into) a register,
5512 we want to recompute POS relative to wanted_inner_mode. */
5513 int width = (GET_CODE (inner) == MEM
5514 ? GET_MODE_BITSIZE (is_mode)
5515 : GET_MODE_BITSIZE (wanted_inner_mode));
5518 pos = width - len - pos;
5521 = gen_rtx_combine (MINUS, GET_MODE (pos_rtx),
5522 GEN_INT (width - len), pos_rtx);
5523 /* POS may be less than 0 now, but we check for that below.
5524 Note that it can only be less than 0 if GET_CODE (inner) != MEM. */
5527 /* If INNER has a wider mode, make it smaller. If this is a constant
5528 extract, try to adjust the byte to point to the byte containing
5530 if (wanted_inner_mode != VOIDmode
5531 && GET_MODE_SIZE (wanted_inner_mode) < GET_MODE_SIZE (is_mode)
5532 && ((GET_CODE (inner) == MEM
5533 && (inner_mode == wanted_inner_mode
5534 || (! mode_dependent_address_p (XEXP (inner, 0))
5535 && ! MEM_VOLATILE_P (inner))))))
5539 /* The computations below will be correct if the machine is big
5540 endian in both bits and bytes or little endian in bits and bytes.
5541 If it is mixed, we must adjust. */
5543 /* If bytes are big endian and we had a paradoxical SUBREG, we must
5544 adjust OFFSET to compensate. */
5545 if (BYTES_BIG_ENDIAN
5547 && GET_MODE_SIZE (inner_mode) < GET_MODE_SIZE (is_mode))
5548 offset -= GET_MODE_SIZE (is_mode) - GET_MODE_SIZE (inner_mode);
5550 /* If this is a constant position, we can move to the desired byte. */
5553 offset += pos / BITS_PER_UNIT;
5554 pos %= GET_MODE_BITSIZE (wanted_inner_mode);
5557 if (BYTES_BIG_ENDIAN != BITS_BIG_ENDIAN
5559 && is_mode != wanted_inner_mode)
5560 offset = (GET_MODE_SIZE (is_mode)
5561 - GET_MODE_SIZE (wanted_inner_mode) - offset);
5563 if (offset != 0 || inner_mode != wanted_inner_mode)
5565 rtx newmem = gen_rtx (MEM, wanted_inner_mode,
5566 plus_constant (XEXP (inner, 0), offset));
5567 RTX_UNCHANGING_P (newmem) = RTX_UNCHANGING_P (inner);
5568 MEM_VOLATILE_P (newmem) = MEM_VOLATILE_P (inner);
5569 MEM_IN_STRUCT_P (newmem) = MEM_IN_STRUCT_P (inner);
5574 /* If INNER is not memory, we can always get it into the proper mode. If we
5575 are changing its mode, POS must be a constant and smaller than the size
5577 else if (GET_CODE (inner) != MEM)
5579 if (GET_MODE (inner) != wanted_inner_mode
5581 || orig_pos + len > GET_MODE_BITSIZE (wanted_inner_mode)))
5584 inner = force_to_mode (inner, wanted_inner_mode,
5586 || len + orig_pos >= HOST_BITS_PER_WIDE_INT
5587 ? GET_MODE_MASK (wanted_inner_mode)
5588 : (((HOST_WIDE_INT) 1 << len) - 1) << orig_pos,
5592 /* Adjust mode of POS_RTX, if needed. If we want a wider mode, we
5593 have to zero extend. Otherwise, we can just use a SUBREG. */
5595 && GET_MODE_SIZE (pos_mode) > GET_MODE_SIZE (GET_MODE (pos_rtx)))
5596 pos_rtx = gen_rtx_combine (ZERO_EXTEND, pos_mode, pos_rtx);
5597 else if (pos_rtx != 0
5598 && GET_MODE_SIZE (pos_mode) < GET_MODE_SIZE (GET_MODE (pos_rtx)))
5599 pos_rtx = gen_lowpart_for_combine (pos_mode, pos_rtx);
5601 /* Make POS_RTX unless we already have it and it is correct. If we don't
5602 have a POS_RTX but we do have an ORIG_POS_RTX, the latter must
5604 if (pos_rtx == 0 && orig_pos_rtx != 0 && INTVAL (orig_pos_rtx) == pos)
5605 pos_rtx = orig_pos_rtx;
5607 else if (pos_rtx == 0)
5608 pos_rtx = GEN_INT (pos);
5610 /* Make the required operation. See if we can use existing rtx. */
5611 new = gen_rtx_combine (unsignedp ? ZERO_EXTRACT : SIGN_EXTRACT,
5612 extraction_mode, inner, GEN_INT (len), pos_rtx);
5614 new = gen_lowpart_for_combine (mode, new);
5619 /* See if X contains an ASHIFT of COUNT or more bits that can be commuted
5620 with any other operations in X. Return X without that shift if so. */
5623 extract_left_shift (x, count)
5627 enum rtx_code code = GET_CODE (x);
5628 enum machine_mode mode = GET_MODE (x);
5634 /* This is the shift itself. If it is wide enough, we will return
5635 either the value being shifted if the shift count is equal to
5636 COUNT or a shift for the difference. */
5637 if (GET_CODE (XEXP (x, 1)) == CONST_INT
5638 && INTVAL (XEXP (x, 1)) >= count)
5639 return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (x, 0),
5640 INTVAL (XEXP (x, 1)) - count);
5644 if ((tem = extract_left_shift (XEXP (x, 0), count)) != 0)
5645 return gen_unary (code, mode, mode, tem);
5649 case PLUS: case IOR: case XOR: case AND:
5650 /* If we can safely shift this constant and we find the inner shift,
5651 make a new operation. */
5652 if (GET_CODE (XEXP (x,1)) == CONST_INT
5653 && (INTVAL (XEXP (x, 1)) & (((HOST_WIDE_INT) 1 << count)) - 1) == 0
5654 && (tem = extract_left_shift (XEXP (x, 0), count)) != 0)
5655 return gen_binary (code, mode, tem,
5656 GEN_INT (INTVAL (XEXP (x, 1)) >> count));
5664 /* Look at the expression rooted at X. Look for expressions
5665 equivalent to ZERO_EXTRACT, SIGN_EXTRACT, ZERO_EXTEND, SIGN_EXTEND.
5666 Form these expressions.
5668 Return the new rtx, usually just X.
5670 Also, for machines like the Vax that don't have logical shift insns,
5671 try to convert logical to arithmetic shift operations in cases where
5672 they are equivalent. This undoes the canonicalizations to logical
5673 shifts done elsewhere.
5675 We try, as much as possible, to re-use rtl expressions to save memory.
5677 IN_CODE says what kind of expression we are processing. Normally, it is
5678 SET. In a memory address (inside a MEM, PLUS or minus, the latter two
5679 being kludges), it is MEM. When processing the arguments of a comparison
5680 or a COMPARE against zero, it is COMPARE. */
5683 make_compound_operation (x, in_code)
5685 enum rtx_code in_code;
5687 enum rtx_code code = GET_CODE (x);
5688 enum machine_mode mode = GET_MODE (x);
5689 int mode_width = GET_MODE_BITSIZE (mode);
5691 enum rtx_code next_code;
5697 /* Select the code to be used in recursive calls. Once we are inside an
5698 address, we stay there. If we have a comparison, set to COMPARE,
5699 but once inside, go back to our default of SET. */
5701 next_code = (code == MEM || code == PLUS || code == MINUS ? MEM
5702 : ((code == COMPARE || GET_RTX_CLASS (code) == '<')
5703 && XEXP (x, 1) == const0_rtx) ? COMPARE
5704 : in_code == COMPARE ? SET : in_code);
5706 /* Process depending on the code of this operation. If NEW is set
5707 non-zero, it will be returned. */
5712 /* Convert shifts by constants into multiplications if inside
5714 if (in_code == MEM && GET_CODE (XEXP (x, 1)) == CONST_INT
5715 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT
5716 && INTVAL (XEXP (x, 1)) >= 0)
5718 new = make_compound_operation (XEXP (x, 0), next_code);
5719 new = gen_rtx_combine (MULT, mode, new,
5720 GEN_INT ((HOST_WIDE_INT) 1
5721 << INTVAL (XEXP (x, 1))));
5726 /* If the second operand is not a constant, we can't do anything
5728 if (GET_CODE (XEXP (x, 1)) != CONST_INT)
5731 /* If the constant is a power of two minus one and the first operand
5732 is a logical right shift, make an extraction. */
5733 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
5734 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
5736 new = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code);
5737 new = make_extraction (mode, new, 0, XEXP (XEXP (x, 0), 1), i, 1,
5738 0, in_code == COMPARE);
5741 /* Same as previous, but for (subreg (lshiftrt ...)) in first op. */
5742 else if (GET_CODE (XEXP (x, 0)) == SUBREG
5743 && subreg_lowpart_p (XEXP (x, 0))
5744 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == LSHIFTRT
5745 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
5747 new = make_compound_operation (XEXP (SUBREG_REG (XEXP (x, 0)), 0),
5749 new = make_extraction (GET_MODE (SUBREG_REG (XEXP (x, 0))), new, 0,
5750 XEXP (SUBREG_REG (XEXP (x, 0)), 1), i, 1,
5751 0, in_code == COMPARE);
5753 /* Same as previous, but for (xor/ior (lshiftrt...) (lshiftrt...)). */
5754 else if ((GET_CODE (XEXP (x, 0)) == XOR
5755 || GET_CODE (XEXP (x, 0)) == IOR)
5756 && GET_CODE (XEXP (XEXP (x, 0), 0)) == LSHIFTRT
5757 && GET_CODE (XEXP (XEXP (x, 0), 1)) == LSHIFTRT
5758 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
5760 /* Apply the distributive law, and then try to make extractions. */
5761 new = gen_rtx_combine (GET_CODE (XEXP (x, 0)), mode,
5762 gen_rtx (AND, mode, XEXP (XEXP (x, 0), 0),
5764 gen_rtx (AND, mode, XEXP (XEXP (x, 0), 1),
5766 new = make_compound_operation (new, in_code);
5769 /* If we are have (and (rotate X C) M) and C is larger than the number
5770 of bits in M, this is an extraction. */
5772 else if (GET_CODE (XEXP (x, 0)) == ROTATE
5773 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
5774 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0
5775 && i <= INTVAL (XEXP (XEXP (x, 0), 1)))
5777 new = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code);
5778 new = make_extraction (mode, new,
5779 (GET_MODE_BITSIZE (mode)
5780 - INTVAL (XEXP (XEXP (x, 0), 1))),
5781 NULL_RTX, i, 1, 0, in_code == COMPARE);
5784 /* On machines without logical shifts, if the operand of the AND is
5785 a logical shift and our mask turns off all the propagated sign
5786 bits, we can replace the logical shift with an arithmetic shift. */
5787 else if (ashr_optab->handlers[(int) mode].insn_code != CODE_FOR_nothing
5788 && (lshr_optab->handlers[(int) mode].insn_code
5789 == CODE_FOR_nothing)
5790 && GET_CODE (XEXP (x, 0)) == LSHIFTRT
5791 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
5792 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
5793 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT
5794 && mode_width <= HOST_BITS_PER_WIDE_INT)
5796 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
5798 mask >>= INTVAL (XEXP (XEXP (x, 0), 1));
5799 if ((INTVAL (XEXP (x, 1)) & ~mask) == 0)
5801 gen_rtx_combine (ASHIFTRT, mode,
5802 make_compound_operation (XEXP (XEXP (x, 0), 0),
5804 XEXP (XEXP (x, 0), 1)));
5807 /* If the constant is one less than a power of two, this might be
5808 representable by an extraction even if no shift is present.
5809 If it doesn't end up being a ZERO_EXTEND, we will ignore it unless
5810 we are in a COMPARE. */
5811 else if ((i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
5812 new = make_extraction (mode,
5813 make_compound_operation (XEXP (x, 0),
5815 0, NULL_RTX, i, 1, 0, in_code == COMPARE);
5817 /* If we are in a comparison and this is an AND with a power of two,
5818 convert this into the appropriate bit extract. */
5819 else if (in_code == COMPARE
5820 && (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0)
5821 new = make_extraction (mode,
5822 make_compound_operation (XEXP (x, 0),
5824 i, NULL_RTX, 1, 1, 0, 1);
5829 /* If the sign bit is known to be zero, replace this with an
5830 arithmetic shift. */
5831 if (ashr_optab->handlers[(int) mode].insn_code == CODE_FOR_nothing
5832 && lshr_optab->handlers[(int) mode].insn_code != CODE_FOR_nothing
5833 && mode_width <= HOST_BITS_PER_WIDE_INT
5834 && (nonzero_bits (XEXP (x, 0), mode) & (1 << (mode_width - 1))) == 0)
5836 new = gen_rtx_combine (ASHIFTRT, mode,
5837 make_compound_operation (XEXP (x, 0),
5843 /* ... fall through ... */
5849 /* If we have (ashiftrt (ashift foo C1) C2) with C2 >= C1,
5850 this is a SIGN_EXTRACT. */
5851 if (GET_CODE (rhs) == CONST_INT
5852 && GET_CODE (lhs) == ASHIFT
5853 && GET_CODE (XEXP (lhs, 1)) == CONST_INT
5854 && INTVAL (rhs) >= INTVAL (XEXP (lhs, 1)))
5856 new = make_compound_operation (XEXP (lhs, 0), next_code);
5857 new = make_extraction (mode, new,
5858 INTVAL (rhs) - INTVAL (XEXP (lhs, 1)),
5859 NULL_RTX, mode_width - INTVAL (rhs),
5860 code == LSHIFTRT, 0, in_code == COMPARE);
5863 /* See if we have operations between an ASHIFTRT and an ASHIFT.
5864 If so, try to merge the shifts into a SIGN_EXTEND. We could
5865 also do this for some cases of SIGN_EXTRACT, but it doesn't
5866 seem worth the effort; the case checked for occurs on Alpha. */
5868 if (GET_RTX_CLASS (GET_CODE (lhs)) != 'o'
5869 && ! (GET_CODE (lhs) == SUBREG
5870 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (lhs))) == 'o'))
5871 && GET_CODE (rhs) == CONST_INT
5872 && INTVAL (rhs) < HOST_BITS_PER_WIDE_INT
5873 && (new = extract_left_shift (lhs, INTVAL (rhs))) != 0)
5874 new = make_extraction (mode, make_compound_operation (new, next_code),
5875 0, NULL_RTX, mode_width - INTVAL (rhs),
5876 code == LSHIFTRT, 0, in_code == COMPARE);
5881 /* Call ourselves recursively on the inner expression. If we are
5882 narrowing the object and it has a different RTL code from
5883 what it originally did, do this SUBREG as a force_to_mode. */
5885 tem = make_compound_operation (SUBREG_REG (x), in_code);
5886 if (GET_CODE (tem) != GET_CODE (SUBREG_REG (x))
5887 && GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (tem))
5888 && subreg_lowpart_p (x))
5890 rtx newer = force_to_mode (tem, mode,
5891 GET_MODE_MASK (mode), NULL_RTX, 0);
5893 /* If we have something other than a SUBREG, we might have
5894 done an expansion, so rerun outselves. */
5895 if (GET_CODE (newer) != SUBREG)
5896 newer = make_compound_operation (newer, in_code);
5904 x = gen_lowpart_for_combine (mode, new);
5905 code = GET_CODE (x);
5908 /* Now recursively process each operand of this operation. */
5909 fmt = GET_RTX_FORMAT (code);
5910 for (i = 0; i < GET_RTX_LENGTH (code); i++)
5913 new = make_compound_operation (XEXP (x, i), next_code);
5914 SUBST (XEXP (x, i), new);
5920 /* Given M see if it is a value that would select a field of bits
5921 within an item, but not the entire word. Return -1 if not.
5922 Otherwise, return the starting position of the field, where 0 is the
5925 *PLEN is set to the length of the field. */
5928 get_pos_from_mask (m, plen)
5929 unsigned HOST_WIDE_INT m;
5932 /* Get the bit number of the first 1 bit from the right, -1 if none. */
5933 int pos = exact_log2 (m & - m);
5938 /* Now shift off the low-order zero bits and see if we have a power of
5940 *plen = exact_log2 ((m >> pos) + 1);
5948 /* See if X can be simplified knowing that we will only refer to it in
5949 MODE and will only refer to those bits that are nonzero in MASK.
5950 If other bits are being computed or if masking operations are done
5951 that select a superset of the bits in MASK, they can sometimes be
5954 Return a possibly simplified expression, but always convert X to
5955 MODE. If X is a CONST_INT, AND the CONST_INT with MASK.
5957 Also, if REG is non-zero and X is a register equal in value to REG,
5960 If JUST_SELECT is nonzero, don't optimize by noticing that bits in MASK
5961 are all off in X. This is used when X will be complemented, by either
5962 NOT, NEG, or XOR. */
5965 force_to_mode (x, mode, mask, reg, just_select)
5967 enum machine_mode mode;
5968 unsigned HOST_WIDE_INT mask;
5972 enum rtx_code code = GET_CODE (x);
5973 int next_select = just_select || code == XOR || code == NOT || code == NEG;
5974 enum machine_mode op_mode;
5975 unsigned HOST_WIDE_INT fuller_mask, nonzero;
5978 /* If this is a CALL or ASM_OPERANDS, don't do anything. Some of the
5979 code below will do the wrong thing since the mode of such an
5980 expression is VOIDmode. */
5981 if (code == CALL || code == ASM_OPERANDS)
5984 /* We want to perform the operation is its present mode unless we know
5985 that the operation is valid in MODE, in which case we do the operation
5987 op_mode = ((GET_MODE_CLASS (mode) == GET_MODE_CLASS (GET_MODE (x))
5988 && code_to_optab[(int) code] != 0
5989 && (code_to_optab[(int) code]->handlers[(int) mode].insn_code
5990 != CODE_FOR_nothing))
5991 ? mode : GET_MODE (x));
5993 /* It is not valid to do a right-shift in a narrower mode
5994 than the one it came in with. */
5995 if ((code == LSHIFTRT || code == ASHIFTRT)
5996 && GET_MODE_BITSIZE (mode) < GET_MODE_BITSIZE (GET_MODE (x)))
5997 op_mode = GET_MODE (x);
5999 /* Truncate MASK to fit OP_MODE. */
6001 mask &= GET_MODE_MASK (op_mode);
6003 /* When we have an arithmetic operation, or a shift whose count we
6004 do not know, we need to assume that all bit the up to the highest-order
6005 bit in MASK will be needed. This is how we form such a mask. */
6007 fuller_mask = (GET_MODE_BITSIZE (op_mode) >= HOST_BITS_PER_WIDE_INT
6008 ? GET_MODE_MASK (op_mode)
6009 : ((HOST_WIDE_INT) 1 << (floor_log2 (mask) + 1)) - 1);
6011 fuller_mask = ~ (HOST_WIDE_INT) 0;
6013 /* Determine what bits of X are guaranteed to be (non)zero. */
6014 nonzero = nonzero_bits (x, mode);
6016 /* If none of the bits in X are needed, return a zero. */
6017 if (! just_select && (nonzero & mask) == 0)
6020 /* If X is a CONST_INT, return a new one. Do this here since the
6021 test below will fail. */
6022 if (GET_CODE (x) == CONST_INT)
6024 HOST_WIDE_INT cval = INTVAL (x) & mask;
6025 int width = GET_MODE_BITSIZE (mode);
6027 /* If MODE is narrower that HOST_WIDE_INT and CVAL is a negative
6028 number, sign extend it. */
6029 if (width > 0 && width < HOST_BITS_PER_WIDE_INT
6030 && (cval & ((HOST_WIDE_INT) 1 << (width - 1))) != 0)
6031 cval |= (HOST_WIDE_INT) -1 << width;
6033 return GEN_INT (cval);
6036 /* If X is narrower than MODE and we want all the bits in X's mode, just
6037 get X in the proper mode. */
6038 if (GET_MODE_SIZE (GET_MODE (x)) < GET_MODE_SIZE (mode)
6039 && (GET_MODE_MASK (GET_MODE (x)) & ~ mask) == 0)
6040 return gen_lowpart_for_combine (mode, x);
6042 /* If we aren't changing the mode, X is not a SUBREG, and all zero bits in
6043 MASK are already known to be zero in X, we need not do anything. */
6044 if (GET_MODE (x) == mode && code != SUBREG && (~ mask & nonzero) == 0)
6050 /* If X is a (clobber (const_int)), return it since we know we are
6051 generating something that won't match. */
6055 /* X is a (use (mem ..)) that was made from a bit-field extraction that
6056 spanned the boundary of the MEM. If we are now masking so it is
6057 within that boundary, we don't need the USE any more. */
6058 if (! BITS_BIG_ENDIAN
6059 && (mask & ~ GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
6060 return force_to_mode (XEXP (x, 0), mode, mask, reg, next_select);
6067 x = expand_compound_operation (x);
6068 if (GET_CODE (x) != code)
6069 return force_to_mode (x, mode, mask, reg, next_select);
6073 if (reg != 0 && (rtx_equal_p (get_last_value (reg), x)
6074 || rtx_equal_p (reg, get_last_value (x))))
6079 if (subreg_lowpart_p (x)
6080 /* We can ignore the effect of this SUBREG if it narrows the mode or
6081 if the constant masks to zero all the bits the mode doesn't
6083 && ((GET_MODE_SIZE (GET_MODE (x))
6084 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
6086 & GET_MODE_MASK (GET_MODE (x))
6087 & ~ GET_MODE_MASK (GET_MODE (SUBREG_REG (x)))))))
6088 return force_to_mode (SUBREG_REG (x), mode, mask, reg, next_select);
6092 /* If this is an AND with a constant, convert it into an AND
6093 whose constant is the AND of that constant with MASK. If it
6094 remains an AND of MASK, delete it since it is redundant. */
6096 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
6098 x = simplify_and_const_int (x, op_mode, XEXP (x, 0),
6099 mask & INTVAL (XEXP (x, 1)));
6101 /* If X is still an AND, see if it is an AND with a mask that
6102 is just some low-order bits. If so, and it is MASK, we don't
6105 if (GET_CODE (x) == AND && GET_CODE (XEXP (x, 1)) == CONST_INT
6106 && INTVAL (XEXP (x, 1)) == mask)
6109 /* If it remains an AND, try making another AND with the bits
6110 in the mode mask that aren't in MASK turned on. If the
6111 constant in the AND is wide enough, this might make a
6112 cheaper constant. */
6114 if (GET_CODE (x) == AND && GET_CODE (XEXP (x, 1)) == CONST_INT
6115 && GET_MODE_MASK (GET_MODE (x)) != mask
6116 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT)
6118 HOST_WIDE_INT cval = (INTVAL (XEXP (x, 1))
6119 | (GET_MODE_MASK (GET_MODE (x)) & ~ mask));
6120 int width = GET_MODE_BITSIZE (GET_MODE (x));
6123 /* If MODE is narrower that HOST_WIDE_INT and CVAL is a negative
6124 number, sign extend it. */
6125 if (width > 0 && width < HOST_BITS_PER_WIDE_INT
6126 && (cval & ((HOST_WIDE_INT) 1 << (width - 1))) != 0)
6127 cval |= (HOST_WIDE_INT) -1 << width;
6129 y = gen_binary (AND, GET_MODE (x), XEXP (x, 0), GEN_INT (cval));
6130 if (rtx_cost (y, SET) < rtx_cost (x, SET))
6140 /* In (and (plus FOO C1) M), if M is a mask that just turns off
6141 low-order bits (as in an alignment operation) and FOO is already
6142 aligned to that boundary, mask C1 to that boundary as well.
6143 This may eliminate that PLUS and, later, the AND. */
6146 int width = GET_MODE_BITSIZE (mode);
6147 unsigned HOST_WIDE_INT smask = mask;
6149 /* If MODE is narrower than HOST_WIDE_INT and mask is a negative
6150 number, sign extend it. */
6152 if (width < HOST_BITS_PER_WIDE_INT
6153 && (smask & ((HOST_WIDE_INT) 1 << (width - 1))) != 0)
6154 smask |= (HOST_WIDE_INT) -1 << width;
6156 if (GET_CODE (XEXP (x, 1)) == CONST_INT
6157 && exact_log2 (- smask) >= 0
6158 && (nonzero_bits (XEXP (x, 0), mode) & ~ mask) == 0
6159 && (INTVAL (XEXP (x, 1)) & ~ mask) != 0)
6160 return force_to_mode (plus_constant (XEXP (x, 0),
6161 INTVAL (XEXP (x, 1)) & mask),
6162 mode, mask, reg, next_select);
6165 /* ... fall through ... */
6169 /* For PLUS, MINUS and MULT, we need any bits less significant than the
6170 most significant bit in MASK since carries from those bits will
6171 affect the bits we are interested in. */
6177 /* If X is (ior (lshiftrt FOO C1) C2), try to commute the IOR and
6178 LSHIFTRT so we end up with an (and (lshiftrt (ior ...) ...) ...)
6179 operation which may be a bitfield extraction. Ensure that the
6180 constant we form is not wider than the mode of X. */
6182 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
6183 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
6184 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
6185 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT
6186 && GET_CODE (XEXP (x, 1)) == CONST_INT
6187 && ((INTVAL (XEXP (XEXP (x, 0), 1))
6188 + floor_log2 (INTVAL (XEXP (x, 1))))
6189 < GET_MODE_BITSIZE (GET_MODE (x)))
6190 && (INTVAL (XEXP (x, 1))
6191 & ~ nonzero_bits (XEXP (x, 0), GET_MODE (x))) == 0)
6193 temp = GEN_INT ((INTVAL (XEXP (x, 1)) & mask)
6194 << INTVAL (XEXP (XEXP (x, 0), 1)));
6195 temp = gen_binary (GET_CODE (x), GET_MODE (x),
6196 XEXP (XEXP (x, 0), 0), temp);
6197 x = gen_binary (LSHIFTRT, GET_MODE (x), temp,
6198 XEXP (XEXP (x, 0), 1));
6199 return force_to_mode (x, mode, mask, reg, next_select);
6203 /* For most binary operations, just propagate into the operation and
6204 change the mode if we have an operation of that mode. */
6206 op0 = gen_lowpart_for_combine (op_mode,
6207 force_to_mode (XEXP (x, 0), mode, mask,
6209 op1 = gen_lowpart_for_combine (op_mode,
6210 force_to_mode (XEXP (x, 1), mode, mask,
6213 /* If OP1 is a CONST_INT and X is an IOR or XOR, clear bits outside
6214 MASK since OP1 might have been sign-extended but we never want
6215 to turn on extra bits, since combine might have previously relied
6216 on them being off. */
6217 if (GET_CODE (op1) == CONST_INT && (code == IOR || code == XOR)
6218 && (INTVAL (op1) & mask) != 0)
6219 op1 = GEN_INT (INTVAL (op1) & mask);
6221 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
6222 x = gen_binary (code, op_mode, op0, op1);
6226 /* For left shifts, do the same, but just for the first operand.
6227 However, we cannot do anything with shifts where we cannot
6228 guarantee that the counts are smaller than the size of the mode
6229 because such a count will have a different meaning in a
6232 if (! (GET_CODE (XEXP (x, 1)) == CONST_INT
6233 && INTVAL (XEXP (x, 1)) >= 0
6234 && INTVAL (XEXP (x, 1)) < GET_MODE_BITSIZE (mode))
6235 && ! (GET_MODE (XEXP (x, 1)) != VOIDmode
6236 && (nonzero_bits (XEXP (x, 1), GET_MODE (XEXP (x, 1)))
6237 < (unsigned HOST_WIDE_INT) GET_MODE_BITSIZE (mode))))
6240 /* If the shift count is a constant and we can do arithmetic in
6241 the mode of the shift, refine which bits we need. Otherwise, use the
6242 conservative form of the mask. */
6243 if (GET_CODE (XEXP (x, 1)) == CONST_INT
6244 && INTVAL (XEXP (x, 1)) >= 0
6245 && INTVAL (XEXP (x, 1)) < GET_MODE_BITSIZE (op_mode)
6246 && GET_MODE_BITSIZE (op_mode) <= HOST_BITS_PER_WIDE_INT)
6247 mask >>= INTVAL (XEXP (x, 1));
6251 op0 = gen_lowpart_for_combine (op_mode,
6252 force_to_mode (XEXP (x, 0), op_mode,
6253 mask, reg, next_select));
6255 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0))
6256 x = gen_binary (code, op_mode, op0, XEXP (x, 1));
6260 /* Here we can only do something if the shift count is a constant,
6261 this shift constant is valid for the host, and we can do arithmetic
6264 if (GET_CODE (XEXP (x, 1)) == CONST_INT
6265 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT
6266 && GET_MODE_BITSIZE (op_mode) <= HOST_BITS_PER_WIDE_INT)
6268 rtx inner = XEXP (x, 0);
6270 /* Select the mask of the bits we need for the shift operand. */
6271 mask <<= INTVAL (XEXP (x, 1));
6273 /* We can only change the mode of the shift if we can do arithmetic
6274 in the mode of the shift and MASK is no wider than the width of
6276 if (GET_MODE_BITSIZE (op_mode) > HOST_BITS_PER_WIDE_INT
6277 || (mask & ~ GET_MODE_MASK (op_mode)) != 0)
6278 op_mode = GET_MODE (x);
6280 inner = force_to_mode (inner, op_mode, mask, reg, next_select);
6282 if (GET_MODE (x) != op_mode || inner != XEXP (x, 0))
6283 x = gen_binary (LSHIFTRT, op_mode, inner, XEXP (x, 1));
6286 /* If we have (and (lshiftrt FOO C1) C2) where the combination of the
6287 shift and AND produces only copies of the sign bit (C2 is one less
6288 than a power of two), we can do this with just a shift. */
6290 if (GET_CODE (x) == LSHIFTRT
6291 && GET_CODE (XEXP (x, 1)) == CONST_INT
6292 && ((INTVAL (XEXP (x, 1))
6293 + num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0))))
6294 >= GET_MODE_BITSIZE (GET_MODE (x)))
6295 && exact_log2 (mask + 1) >= 0
6296 && (num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
6297 >= exact_log2 (mask + 1)))
6298 x = gen_binary (LSHIFTRT, GET_MODE (x), XEXP (x, 0),
6299 GEN_INT (GET_MODE_BITSIZE (GET_MODE (x))
6300 - exact_log2 (mask + 1)));
6304 /* If we are just looking for the sign bit, we don't need this shift at
6305 all, even if it has a variable count. */
6306 if (GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
6307 && (mask == ((HOST_WIDE_INT) 1
6308 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
6309 return force_to_mode (XEXP (x, 0), mode, mask, reg, next_select);
6311 /* If this is a shift by a constant, get a mask that contains those bits
6312 that are not copies of the sign bit. We then have two cases: If
6313 MASK only includes those bits, this can be a logical shift, which may
6314 allow simplifications. If MASK is a single-bit field not within
6315 those bits, we are requesting a copy of the sign bit and hence can
6316 shift the sign bit to the appropriate location. */
6318 if (GET_CODE (XEXP (x, 1)) == CONST_INT && INTVAL (XEXP (x, 1)) >= 0
6319 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT)
6323 /* If the considered data is wider then HOST_WIDE_INT, we can't
6324 represent a mask for all its bits in a single scalar.
6325 But we only care about the lower bits, so calculate these. */
6327 if (GET_MODE_BITSIZE (GET_MODE (x)) > HOST_BITS_PER_WIDE_INT)
6329 nonzero = ~ (HOST_WIDE_INT) 0;
6331 /* GET_MODE_BITSIZE (GET_MODE (x)) - INTVAL (XEXP (x, 1))
6332 is the number of bits a full-width mask would have set.
6333 We need only shift if these are fewer than nonzero can
6334 hold. If not, we must keep all bits set in nonzero. */
6336 if (GET_MODE_BITSIZE (GET_MODE (x)) - INTVAL (XEXP (x, 1))
6337 < HOST_BITS_PER_WIDE_INT)
6338 nonzero >>= INTVAL (XEXP (x, 1))
6339 + HOST_BITS_PER_WIDE_INT
6340 - GET_MODE_BITSIZE (GET_MODE (x)) ;
6344 nonzero = GET_MODE_MASK (GET_MODE (x));
6345 nonzero >>= INTVAL (XEXP (x, 1));
6348 if ((mask & ~ nonzero) == 0
6349 || (i = exact_log2 (mask)) >= 0)
6351 x = simplify_shift_const
6352 (x, LSHIFTRT, GET_MODE (x), XEXP (x, 0),
6353 i < 0 ? INTVAL (XEXP (x, 1))
6354 : GET_MODE_BITSIZE (GET_MODE (x)) - 1 - i);
6356 if (GET_CODE (x) != ASHIFTRT)
6357 return force_to_mode (x, mode, mask, reg, next_select);
6361 /* If MASK is 1, convert this to a LSHIFTRT. This can be done
6362 even if the shift count isn't a constant. */
6364 x = gen_binary (LSHIFTRT, GET_MODE (x), XEXP (x, 0), XEXP (x, 1));
6366 /* If this is a sign-extension operation that just affects bits
6367 we don't care about, remove it. Be sure the call above returned
6368 something that is still a shift. */
6370 if ((GET_CODE (x) == LSHIFTRT || GET_CODE (x) == ASHIFTRT)
6371 && GET_CODE (XEXP (x, 1)) == CONST_INT
6372 && INTVAL (XEXP (x, 1)) >= 0
6373 && (INTVAL (XEXP (x, 1))
6374 <= GET_MODE_BITSIZE (GET_MODE (x)) - (floor_log2 (mask) + 1))
6375 && GET_CODE (XEXP (x, 0)) == ASHIFT
6376 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
6377 && INTVAL (XEXP (XEXP (x, 0), 1)) == INTVAL (XEXP (x, 1)))
6378 return force_to_mode (XEXP (XEXP (x, 0), 0), mode, mask,
6385 /* If the shift count is constant and we can do computations
6386 in the mode of X, compute where the bits we care about are.
6387 Otherwise, we can't do anything. Don't change the mode of
6388 the shift or propagate MODE into the shift, though. */
6389 if (GET_CODE (XEXP (x, 1)) == CONST_INT
6390 && INTVAL (XEXP (x, 1)) >= 0)
6392 temp = simplify_binary_operation (code == ROTATE ? ROTATERT : ROTATE,
6393 GET_MODE (x), GEN_INT (mask),
6395 if (temp && GET_CODE(temp) == CONST_INT)
6397 force_to_mode (XEXP (x, 0), GET_MODE (x),
6398 INTVAL (temp), reg, next_select));
6403 /* If we just want the low-order bit, the NEG isn't needed since it
6404 won't change the low-order bit. */
6406 return force_to_mode (XEXP (x, 0), mode, mask, reg, just_select);
6408 /* We need any bits less significant than the most significant bit in
6409 MASK since carries from those bits will affect the bits we are
6415 /* (not FOO) is (xor FOO CONST), so if FOO is an LSHIFTRT, we can do the
6416 same as the XOR case above. Ensure that the constant we form is not
6417 wider than the mode of X. */
6419 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
6420 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
6421 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
6422 && (INTVAL (XEXP (XEXP (x, 0), 1)) + floor_log2 (mask)
6423 < GET_MODE_BITSIZE (GET_MODE (x)))
6424 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT)
6426 temp = GEN_INT (mask << INTVAL (XEXP (XEXP (x, 0), 1)));
6427 temp = gen_binary (XOR, GET_MODE (x), XEXP (XEXP (x, 0), 0), temp);
6428 x = gen_binary (LSHIFTRT, GET_MODE (x), temp, XEXP (XEXP (x, 0), 1));
6430 return force_to_mode (x, mode, mask, reg, next_select);
6433 /* (and (not FOO) CONST) is (not (or FOO (not CONST))), so we must
6434 use the full mask inside the NOT. */
6438 op0 = gen_lowpart_for_combine (op_mode,
6439 force_to_mode (XEXP (x, 0), mode, mask,
6441 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0))
6442 x = gen_unary (code, op_mode, op_mode, op0);
6446 /* (and (ne FOO 0) CONST) can be (and FOO CONST) if CONST is included
6447 in STORE_FLAG_VALUE and FOO has a single bit that might be nonzero,
6448 which is equal to STORE_FLAG_VALUE. */
6449 if ((mask & ~ STORE_FLAG_VALUE) == 0 && XEXP (x, 1) == const0_rtx
6450 && exact_log2 (nonzero_bits (XEXP (x, 0), mode)) >= 0
6451 && nonzero_bits (XEXP (x, 0), mode) == STORE_FLAG_VALUE)
6452 return force_to_mode (XEXP (x, 0), mode, mask, reg, next_select);
6457 /* We have no way of knowing if the IF_THEN_ELSE can itself be
6458 written in a narrower mode. We play it safe and do not do so. */
6461 gen_lowpart_for_combine (GET_MODE (x),
6462 force_to_mode (XEXP (x, 1), mode,
6463 mask, reg, next_select)));
6465 gen_lowpart_for_combine (GET_MODE (x),
6466 force_to_mode (XEXP (x, 2), mode,
6467 mask, reg,next_select)));
6471 /* Ensure we return a value of the proper mode. */
6472 return gen_lowpart_for_combine (mode, x);
6475 /* Return nonzero if X is an expression that has one of two values depending on
6476 whether some other value is zero or nonzero. In that case, we return the
6477 value that is being tested, *PTRUE is set to the value if the rtx being
6478 returned has a nonzero value, and *PFALSE is set to the other alternative.
6480 If we return zero, we set *PTRUE and *PFALSE to X. */
6483 if_then_else_cond (x, ptrue, pfalse)
6485 rtx *ptrue, *pfalse;
6487 enum machine_mode mode = GET_MODE (x);
6488 enum rtx_code code = GET_CODE (x);
6489 int size = GET_MODE_BITSIZE (mode);
6490 rtx cond0, cond1, true0, true1, false0, false1;
6491 unsigned HOST_WIDE_INT nz;
6493 /* If this is a unary operation whose operand has one of two values, apply
6494 our opcode to compute those values. */
6495 if (GET_RTX_CLASS (code) == '1'
6496 && (cond0 = if_then_else_cond (XEXP (x, 0), &true0, &false0)) != 0)
6498 *ptrue = gen_unary (code, mode, GET_MODE (XEXP (x, 0)), true0);
6499 *pfalse = gen_unary (code, mode, GET_MODE (XEXP (x, 0)), false0);
6503 /* If this is a COMPARE, do nothing, since the IF_THEN_ELSE we would
6504 make can't possibly match and would suppress other optimizations. */
6505 else if (code == COMPARE)
6508 /* If this is a binary operation, see if either side has only one of two
6509 values. If either one does or if both do and they are conditional on
6510 the same value, compute the new true and false values. */
6511 else if (GET_RTX_CLASS (code) == 'c' || GET_RTX_CLASS (code) == '2'
6512 || GET_RTX_CLASS (code) == '<')
6514 cond0 = if_then_else_cond (XEXP (x, 0), &true0, &false0);
6515 cond1 = if_then_else_cond (XEXP (x, 1), &true1, &false1);
6517 if ((cond0 != 0 || cond1 != 0)
6518 && ! (cond0 != 0 && cond1 != 0 && ! rtx_equal_p (cond0, cond1)))
6520 /* If if_then_else_cond returned zero, then true/false are the
6521 same rtl. We must copy one of them to prevent invalid rtl
6524 true0 = copy_rtx (true0);
6525 else if (cond1 == 0)
6526 true1 = copy_rtx (true1);
6528 *ptrue = gen_binary (code, mode, true0, true1);
6529 *pfalse = gen_binary (code, mode, false0, false1);
6530 return cond0 ? cond0 : cond1;
6533 /* See if we have PLUS, IOR, XOR, MINUS or UMAX, where one of the
6534 operands is zero when the other is non-zero, and vice-versa,
6535 and STORE_FLAG_VALUE is 1 or -1. */
6537 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
6538 && (code == PLUS || code == IOR || code == XOR || code == MINUS
6540 && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT)
6542 rtx op0 = XEXP (XEXP (x, 0), 1);
6543 rtx op1 = XEXP (XEXP (x, 1), 1);
6545 cond0 = XEXP (XEXP (x, 0), 0);
6546 cond1 = XEXP (XEXP (x, 1), 0);
6548 if (GET_RTX_CLASS (GET_CODE (cond0)) == '<'
6549 && GET_RTX_CLASS (GET_CODE (cond1)) == '<'
6550 && reversible_comparison_p (cond1)
6551 && ((GET_CODE (cond0) == reverse_condition (GET_CODE (cond1))
6552 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0))
6553 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1)))
6554 || ((swap_condition (GET_CODE (cond0))
6555 == reverse_condition (GET_CODE (cond1)))
6556 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1))
6557 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0))))
6558 && ! side_effects_p (x))
6560 *ptrue = gen_binary (MULT, mode, op0, const_true_rtx);
6561 *pfalse = gen_binary (MULT, mode,
6563 ? gen_unary (NEG, mode, mode, op1) : op1),
6569 /* Similarly for MULT, AND and UMIN, execpt that for these the result
6571 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
6572 && (code == MULT || code == AND || code == UMIN)
6573 && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT)
6575 cond0 = XEXP (XEXP (x, 0), 0);
6576 cond1 = XEXP (XEXP (x, 1), 0);
6578 if (GET_RTX_CLASS (GET_CODE (cond0)) == '<'
6579 && GET_RTX_CLASS (GET_CODE (cond1)) == '<'
6580 && reversible_comparison_p (cond1)
6581 && ((GET_CODE (cond0) == reverse_condition (GET_CODE (cond1))
6582 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0))
6583 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1)))
6584 || ((swap_condition (GET_CODE (cond0))
6585 == reverse_condition (GET_CODE (cond1)))
6586 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1))
6587 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0))))
6588 && ! side_effects_p (x))
6590 *ptrue = *pfalse = const0_rtx;
6596 else if (code == IF_THEN_ELSE)
6598 /* If we have IF_THEN_ELSE already, extract the condition and
6599 canonicalize it if it is NE or EQ. */
6600 cond0 = XEXP (x, 0);
6601 *ptrue = XEXP (x, 1), *pfalse = XEXP (x, 2);
6602 if (GET_CODE (cond0) == NE && XEXP (cond0, 1) == const0_rtx)
6603 return XEXP (cond0, 0);
6604 else if (GET_CODE (cond0) == EQ && XEXP (cond0, 1) == const0_rtx)
6606 *ptrue = XEXP (x, 2), *pfalse = XEXP (x, 1);
6607 return XEXP (cond0, 0);
6613 /* If X is a normal SUBREG with both inner and outer modes integral,
6614 we can narrow both the true and false values of the inner expression,
6615 if there is a condition. */
6616 else if (code == SUBREG && GET_MODE_CLASS (mode) == MODE_INT
6617 && GET_MODE_CLASS (GET_MODE (SUBREG_REG (x))) == MODE_INT
6618 && GET_MODE_SIZE (mode) <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x)))
6619 && 0 != (cond0 = if_then_else_cond (SUBREG_REG (x),
6622 *ptrue = force_to_mode (true0, mode, GET_MODE_MASK (mode), NULL_RTX, 0);
6624 = force_to_mode (false0, mode, GET_MODE_MASK (mode), NULL_RTX, 0);
6629 /* If X is a constant, this isn't special and will cause confusions
6630 if we treat it as such. Likewise if it is equivalent to a constant. */
6631 else if (CONSTANT_P (x)
6632 || ((cond0 = get_last_value (x)) != 0 && CONSTANT_P (cond0)))
6635 /* If X is known to be either 0 or -1, those are the true and
6636 false values when testing X. */
6637 else if (num_sign_bit_copies (x, mode) == size)
6639 *ptrue = constm1_rtx, *pfalse = const0_rtx;
6643 /* Likewise for 0 or a single bit. */
6644 else if (exact_log2 (nz = nonzero_bits (x, mode)) >= 0)
6646 *ptrue = GEN_INT (nz), *pfalse = const0_rtx;
6650 /* Otherwise fail; show no condition with true and false values the same. */
6651 *ptrue = *pfalse = x;
6655 /* Return the value of expression X given the fact that condition COND
6656 is known to be true when applied to REG as its first operand and VAL
6657 as its second. X is known to not be shared and so can be modified in
6660 We only handle the simplest cases, and specifically those cases that
6661 arise with IF_THEN_ELSE expressions. */
6664 known_cond (x, cond, reg, val)
6669 enum rtx_code code = GET_CODE (x);
6674 if (side_effects_p (x))
6677 if (cond == EQ && rtx_equal_p (x, reg))
6680 /* If X is (abs REG) and we know something about REG's relationship
6681 with zero, we may be able to simplify this. */
6683 if (code == ABS && rtx_equal_p (XEXP (x, 0), reg) && val == const0_rtx)
6686 case GE: case GT: case EQ:
6689 return gen_unary (NEG, GET_MODE (XEXP (x, 0)), GET_MODE (XEXP (x, 0)),
6693 /* The only other cases we handle are MIN, MAX, and comparisons if the
6694 operands are the same as REG and VAL. */
6696 else if (GET_RTX_CLASS (code) == '<' || GET_RTX_CLASS (code) == 'c')
6698 if (rtx_equal_p (XEXP (x, 0), val))
6699 cond = swap_condition (cond), temp = val, val = reg, reg = temp;
6701 if (rtx_equal_p (XEXP (x, 0), reg) && rtx_equal_p (XEXP (x, 1), val))
6703 if (GET_RTX_CLASS (code) == '<')
6704 return (comparison_dominates_p (cond, code) ? const_true_rtx
6705 : (comparison_dominates_p (cond,
6706 reverse_condition (code))
6709 else if (code == SMAX || code == SMIN
6710 || code == UMIN || code == UMAX)
6712 int unsignedp = (code == UMIN || code == UMAX);
6714 if (code == SMAX || code == UMAX)
6715 cond = reverse_condition (cond);
6720 return unsignedp ? x : XEXP (x, 1);
6722 return unsignedp ? x : XEXP (x, 0);
6724 return unsignedp ? XEXP (x, 1) : x;
6726 return unsignedp ? XEXP (x, 0) : x;
6732 fmt = GET_RTX_FORMAT (code);
6733 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
6736 SUBST (XEXP (x, i), known_cond (XEXP (x, i), cond, reg, val));
6737 else if (fmt[i] == 'E')
6738 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
6739 SUBST (XVECEXP (x, i, j), known_cond (XVECEXP (x, i, j),
6746 /* See if X and Y are equal for the purposes of seeing if we can rewrite an
6747 assignment as a field assignment. */
6750 rtx_equal_for_field_assignment_p (x, y)
6756 if (x == y || rtx_equal_p (x, y))
6759 if (x == 0 || y == 0 || GET_MODE (x) != GET_MODE (y))
6762 /* Check for a paradoxical SUBREG of a MEM compared with the MEM.
6763 Note that all SUBREGs of MEM are paradoxical; otherwise they
6764 would have been rewritten. */
6765 if (GET_CODE (x) == MEM && GET_CODE (y) == SUBREG
6766 && GET_CODE (SUBREG_REG (y)) == MEM
6767 && rtx_equal_p (SUBREG_REG (y),
6768 gen_lowpart_for_combine (GET_MODE (SUBREG_REG (y)), x)))
6771 if (GET_CODE (y) == MEM && GET_CODE (x) == SUBREG
6772 && GET_CODE (SUBREG_REG (x)) == MEM
6773 && rtx_equal_p (SUBREG_REG (x),
6774 gen_lowpart_for_combine (GET_MODE (SUBREG_REG (x)), y)))
6777 last_x = get_last_value (x);
6778 last_y = get_last_value (y);
6780 return ((last_x != 0
6781 && GET_CODE (last_x) != CLOBBER
6782 && rtx_equal_for_field_assignment_p (last_x, y))
6784 && GET_CODE (last_y) != CLOBBER
6785 && rtx_equal_for_field_assignment_p (x, last_y))
6786 || (last_x != 0 && last_y != 0
6787 && GET_CODE (last_x) != CLOBBER
6788 && GET_CODE (last_y) != CLOBBER
6789 && rtx_equal_for_field_assignment_p (last_x, last_y)));
6792 /* See if X, a SET operation, can be rewritten as a bit-field assignment.
6793 Return that assignment if so.
6795 We only handle the most common cases. */
6798 make_field_assignment (x)
6801 rtx dest = SET_DEST (x);
6802 rtx src = SET_SRC (x);
6808 enum machine_mode mode;
6810 /* If SRC was (and (not (ashift (const_int 1) POS)) DEST), this is
6811 a clear of a one-bit field. We will have changed it to
6812 (and (rotate (const_int -2) POS) DEST), so check for that. Also check
6815 if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == ROTATE
6816 && GET_CODE (XEXP (XEXP (src, 0), 0)) == CONST_INT
6817 && INTVAL (XEXP (XEXP (src, 0), 0)) == -2
6818 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
6820 assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1),
6823 return gen_rtx (SET, VOIDmode, assign, const0_rtx);
6827 else if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == SUBREG
6828 && subreg_lowpart_p (XEXP (src, 0))
6829 && (GET_MODE_SIZE (GET_MODE (XEXP (src, 0)))
6830 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (src, 0)))))
6831 && GET_CODE (SUBREG_REG (XEXP (src, 0))) == ROTATE
6832 && INTVAL (XEXP (SUBREG_REG (XEXP (src, 0)), 0)) == -2
6833 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
6835 assign = make_extraction (VOIDmode, dest, 0,
6836 XEXP (SUBREG_REG (XEXP (src, 0)), 1),
6839 return gen_rtx (SET, VOIDmode, assign, const0_rtx);
6843 /* If SRC is (ior (ashift (const_int 1) POS) DEST), this is a set of a
6845 else if (GET_CODE (src) == IOR && GET_CODE (XEXP (src, 0)) == ASHIFT
6846 && XEXP (XEXP (src, 0), 0) == const1_rtx
6847 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
6849 assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1),
6852 return gen_rtx (SET, VOIDmode, assign, const1_rtx);
6856 /* The other case we handle is assignments into a constant-position
6857 field. They look like (ior/xor (and DEST C1) OTHER). If C1 represents
6858 a mask that has all one bits except for a group of zero bits and
6859 OTHER is known to have zeros where C1 has ones, this is such an
6860 assignment. Compute the position and length from C1. Shift OTHER
6861 to the appropriate position, force it to the required mode, and
6862 make the extraction. Check for the AND in both operands. */
6864 if (GET_CODE (src) != IOR && GET_CODE (src) != XOR)
6867 rhs = expand_compound_operation (XEXP (src, 0));
6868 lhs = expand_compound_operation (XEXP (src, 1));
6870 if (GET_CODE (rhs) == AND
6871 && GET_CODE (XEXP (rhs, 1)) == CONST_INT
6872 && rtx_equal_for_field_assignment_p (XEXP (rhs, 0), dest))
6873 c1 = INTVAL (XEXP (rhs, 1)), other = lhs;
6874 else if (GET_CODE (lhs) == AND
6875 && GET_CODE (XEXP (lhs, 1)) == CONST_INT
6876 && rtx_equal_for_field_assignment_p (XEXP (lhs, 0), dest))
6877 c1 = INTVAL (XEXP (lhs, 1)), other = rhs;
6881 pos = get_pos_from_mask ((~ c1) & GET_MODE_MASK (GET_MODE (dest)), &len);
6882 if (pos < 0 || pos + len > GET_MODE_BITSIZE (GET_MODE (dest))
6883 || (GET_MODE_BITSIZE (GET_MODE (other)) <= HOST_BITS_PER_WIDE_INT
6884 && (c1 & nonzero_bits (other, GET_MODE (other))) != 0))
6887 assign = make_extraction (VOIDmode, dest, pos, NULL_RTX, len, 1, 1, 0);
6891 /* The mode to use for the source is the mode of the assignment, or of
6892 what is inside a possible STRICT_LOW_PART. */
6893 mode = (GET_CODE (assign) == STRICT_LOW_PART
6894 ? GET_MODE (XEXP (assign, 0)) : GET_MODE (assign));
6896 /* Shift OTHER right POS places and make it the source, restricting it
6897 to the proper length and mode. */
6899 src = force_to_mode (simplify_shift_const (NULL_RTX, LSHIFTRT,
6900 GET_MODE (src), other, pos),
6902 GET_MODE_BITSIZE (mode) >= HOST_BITS_PER_WIDE_INT
6903 ? GET_MODE_MASK (mode)
6904 : ((HOST_WIDE_INT) 1 << len) - 1,
6907 return gen_rtx_combine (SET, VOIDmode, assign, src);
6910 /* See if X is of the form (+ (* a c) (* b c)) and convert to (* (+ a b) c)
6914 apply_distributive_law (x)
6917 enum rtx_code code = GET_CODE (x);
6918 rtx lhs, rhs, other;
6920 enum rtx_code inner_code;
6922 /* Distributivity is not true for floating point.
6923 It can change the value. So don't do it.
6924 -- rms and moshier@world.std.com. */
6925 if (FLOAT_MODE_P (GET_MODE (x)))
6928 /* The outer operation can only be one of the following: */
6929 if (code != IOR && code != AND && code != XOR
6930 && code != PLUS && code != MINUS)
6933 lhs = XEXP (x, 0), rhs = XEXP (x, 1);
6935 /* If either operand is a primitive we can't do anything, so get out
6937 if (GET_RTX_CLASS (GET_CODE (lhs)) == 'o'
6938 || GET_RTX_CLASS (GET_CODE (rhs)) == 'o')
6941 lhs = expand_compound_operation (lhs);
6942 rhs = expand_compound_operation (rhs);
6943 inner_code = GET_CODE (lhs);
6944 if (inner_code != GET_CODE (rhs))
6947 /* See if the inner and outer operations distribute. */
6954 /* These all distribute except over PLUS. */
6955 if (code == PLUS || code == MINUS)
6960 if (code != PLUS && code != MINUS)
6965 /* This is also a multiply, so it distributes over everything. */
6969 /* Non-paradoxical SUBREGs distributes over all operations, provided
6970 the inner modes and word numbers are the same, this is an extraction
6971 of a low-order part, we don't convert an fp operation to int or
6972 vice versa, and we would not be converting a single-word
6973 operation into a multi-word operation. The latter test is not
6974 required, but it prevents generating unneeded multi-word operations.
6975 Some of the previous tests are redundant given the latter test, but
6976 are retained because they are required for correctness.
6978 We produce the result slightly differently in this case. */
6980 if (GET_MODE (SUBREG_REG (lhs)) != GET_MODE (SUBREG_REG (rhs))
6981 || SUBREG_WORD (lhs) != SUBREG_WORD (rhs)
6982 || ! subreg_lowpart_p (lhs)
6983 || (GET_MODE_CLASS (GET_MODE (lhs))
6984 != GET_MODE_CLASS (GET_MODE (SUBREG_REG (lhs))))
6985 || (GET_MODE_SIZE (GET_MODE (lhs))
6986 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs))))
6987 || GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs))) > UNITS_PER_WORD)
6990 tem = gen_binary (code, GET_MODE (SUBREG_REG (lhs)),
6991 SUBREG_REG (lhs), SUBREG_REG (rhs));
6992 return gen_lowpart_for_combine (GET_MODE (x), tem);
6998 /* Set LHS and RHS to the inner operands (A and B in the example
6999 above) and set OTHER to the common operand (C in the example).
7000 These is only one way to do this unless the inner operation is
7002 if (GET_RTX_CLASS (inner_code) == 'c'
7003 && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 0)))
7004 other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 1);
7005 else if (GET_RTX_CLASS (inner_code) == 'c'
7006 && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 1)))
7007 other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 0);
7008 else if (GET_RTX_CLASS (inner_code) == 'c'
7009 && rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 0)))
7010 other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 1);
7011 else if (rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 1)))
7012 other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 0);
7016 /* Form the new inner operation, seeing if it simplifies first. */
7017 tem = gen_binary (code, GET_MODE (x), lhs, rhs);
7019 /* There is one exception to the general way of distributing:
7020 (a ^ b) | (a ^ c) -> (~a) & (b ^ c) */
7021 if (code == XOR && inner_code == IOR)
7024 other = gen_unary (NOT, GET_MODE (x), GET_MODE (x), other);
7027 /* We may be able to continuing distributing the result, so call
7028 ourselves recursively on the inner operation before forming the
7029 outer operation, which we return. */
7030 return gen_binary (inner_code, GET_MODE (x),
7031 apply_distributive_law (tem), other);
7034 /* We have X, a logical `and' of VAROP with the constant CONSTOP, to be done
7037 Return an equivalent form, if different from X. Otherwise, return X. If
7038 X is zero, we are to always construct the equivalent form. */
7041 simplify_and_const_int (x, mode, varop, constop)
7043 enum machine_mode mode;
7045 unsigned HOST_WIDE_INT constop;
7047 unsigned HOST_WIDE_INT nonzero;
7048 int width = GET_MODE_BITSIZE (mode);
7051 /* Simplify VAROP knowing that we will be only looking at some of the
7053 varop = force_to_mode (varop, mode, constop, NULL_RTX, 0);
7055 /* If VAROP is a CLOBBER, we will fail so return it; if it is a
7056 CONST_INT, we are done. */
7057 if (GET_CODE (varop) == CLOBBER || GET_CODE (varop) == CONST_INT)
7060 /* See what bits may be nonzero in VAROP. Unlike the general case of
7061 a call to nonzero_bits, here we don't care about bits outside
7064 nonzero = nonzero_bits (varop, mode) & GET_MODE_MASK (mode);
7066 /* If this would be an entire word for the target, but is not for
7067 the host, then sign-extend on the host so that the number will look
7068 the same way on the host that it would on the target.
7070 For example, when building a 64 bit alpha hosted 32 bit sparc
7071 targeted compiler, then we want the 32 bit unsigned value -1 to be
7072 represented as a 64 bit value -1, and not as 0x00000000ffffffff.
7073 The later confuses the sparc backend. */
7075 if (BITS_PER_WORD < HOST_BITS_PER_WIDE_INT && BITS_PER_WORD == width
7076 && (nonzero & ((HOST_WIDE_INT) 1 << (width - 1))))
7077 nonzero |= ((HOST_WIDE_INT) (-1) << width);
7079 /* Turn off all bits in the constant that are known to already be zero.
7080 Thus, if the AND isn't needed at all, we will have CONSTOP == NONZERO_BITS
7081 which is tested below. */
7085 /* If we don't have any bits left, return zero. */
7089 /* If VAROP is a NEG of something known to be zero or 1 and CONSTOP is
7090 a power of two, we can replace this with a ASHIFT. */
7091 if (GET_CODE (varop) == NEG && nonzero_bits (XEXP (varop, 0), mode) == 1
7092 && (i = exact_log2 (constop)) >= 0)
7093 return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (varop, 0), i);
7095 /* If VAROP is an IOR or XOR, apply the AND to both branches of the IOR
7096 or XOR, then try to apply the distributive law. This may eliminate
7097 operations if either branch can be simplified because of the AND.
7098 It may also make some cases more complex, but those cases probably
7099 won't match a pattern either with or without this. */
7101 if (GET_CODE (varop) == IOR || GET_CODE (varop) == XOR)
7103 gen_lowpart_for_combine
7105 apply_distributive_law
7106 (gen_binary (GET_CODE (varop), GET_MODE (varop),
7107 simplify_and_const_int (NULL_RTX, GET_MODE (varop),
7108 XEXP (varop, 0), constop),
7109 simplify_and_const_int (NULL_RTX, GET_MODE (varop),
7110 XEXP (varop, 1), constop))));
7112 /* Get VAROP in MODE. Try to get a SUBREG if not. Don't make a new SUBREG
7113 if we already had one (just check for the simplest cases). */
7114 if (x && GET_CODE (XEXP (x, 0)) == SUBREG
7115 && GET_MODE (XEXP (x, 0)) == mode
7116 && SUBREG_REG (XEXP (x, 0)) == varop)
7117 varop = XEXP (x, 0);
7119 varop = gen_lowpart_for_combine (mode, varop);
7121 /* If we can't make the SUBREG, try to return what we were given. */
7122 if (GET_CODE (varop) == CLOBBER)
7123 return x ? x : varop;
7125 /* If we are only masking insignificant bits, return VAROP. */
7126 if (constop == nonzero)
7129 /* Otherwise, return an AND. See how much, if any, of X we can use. */
7130 else if (x == 0 || GET_CODE (x) != AND || GET_MODE (x) != mode)
7131 x = gen_binary (AND, mode, varop, GEN_INT (constop));
7135 if (GET_CODE (XEXP (x, 1)) != CONST_INT
7136 || INTVAL (XEXP (x, 1)) != constop)
7137 SUBST (XEXP (x, 1), GEN_INT (constop));
7139 SUBST (XEXP (x, 0), varop);
7145 /* We let num_sign_bit_copies recur into nonzero_bits as that is useful.
7146 We don't let nonzero_bits recur into num_sign_bit_copies, because that
7147 is less useful. We can't allow both, because that results in exponential
7148 run time recusion. There is a nullstone testcase that triggered
7149 this. This macro avoids accidental uses of num_sign_bit_copies. */
7150 #define num_sign_bit_copies()
7152 /* Given an expression, X, compute which bits in X can be non-zero.
7153 We don't care about bits outside of those defined in MODE.
7155 For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is
7156 a shift, AND, or zero_extract, we can do better. */
7158 static unsigned HOST_WIDE_INT
7159 nonzero_bits (x, mode)
7161 enum machine_mode mode;
7163 unsigned HOST_WIDE_INT nonzero = GET_MODE_MASK (mode);
7164 unsigned HOST_WIDE_INT inner_nz;
7166 int mode_width = GET_MODE_BITSIZE (mode);
7169 /* For floating-point values, assume all bits are needed. */
7170 if (FLOAT_MODE_P (GET_MODE (x)) || FLOAT_MODE_P (mode))
7173 /* If X is wider than MODE, use its mode instead. */
7174 if (GET_MODE_BITSIZE (GET_MODE (x)) > mode_width)
7176 mode = GET_MODE (x);
7177 nonzero = GET_MODE_MASK (mode);
7178 mode_width = GET_MODE_BITSIZE (mode);
7181 if (mode_width > HOST_BITS_PER_WIDE_INT)
7182 /* Our only callers in this case look for single bit values. So
7183 just return the mode mask. Those tests will then be false. */
7186 #ifndef WORD_REGISTER_OPERATIONS
7187 /* If MODE is wider than X, but both are a single word for both the host
7188 and target machines, we can compute this from which bits of the
7189 object might be nonzero in its own mode, taking into account the fact
7190 that on many CISC machines, accessing an object in a wider mode
7191 causes the high-order bits to become undefined. So they are
7192 not known to be zero. */
7194 if (GET_MODE (x) != VOIDmode && GET_MODE (x) != mode
7195 && GET_MODE_BITSIZE (GET_MODE (x)) <= BITS_PER_WORD
7196 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
7197 && GET_MODE_BITSIZE (mode) > GET_MODE_BITSIZE (GET_MODE (x)))
7199 nonzero &= nonzero_bits (x, GET_MODE (x));
7200 nonzero |= GET_MODE_MASK (mode) & ~ GET_MODE_MASK (GET_MODE (x));
7205 code = GET_CODE (x);
7209 #ifdef POINTERS_EXTEND_UNSIGNED
7210 /* If pointers extend unsigned and this is a pointer in Pmode, say that
7211 all the bits above ptr_mode are known to be zero. */
7212 if (POINTERS_EXTEND_UNSIGNED && GET_MODE (x) == Pmode
7213 && REGNO_POINTER_FLAG (REGNO (x)))
7214 nonzero &= GET_MODE_MASK (ptr_mode);
7217 #ifdef STACK_BOUNDARY
7218 /* If this is the stack pointer, we may know something about its
7219 alignment. If PUSH_ROUNDING is defined, it is possible for the
7220 stack to be momentarily aligned only to that amount, so we pick
7221 the least alignment. */
7223 /* We can't check for arg_pointer_rtx here, because it is not
7224 guaranteed to have as much alignment as the stack pointer.
7225 In particular, in the Irix6 n64 ABI, the stack has 128 bit
7226 alignment but the argument pointer has only 64 bit alignment. */
7228 if (x == stack_pointer_rtx || x == frame_pointer_rtx
7229 || x == hard_frame_pointer_rtx
7230 || (REGNO (x) >= FIRST_VIRTUAL_REGISTER
7231 && REGNO (x) <= LAST_VIRTUAL_REGISTER))
7233 int sp_alignment = STACK_BOUNDARY / BITS_PER_UNIT;
7235 #ifdef PUSH_ROUNDING
7236 if (REGNO (x) == STACK_POINTER_REGNUM)
7237 sp_alignment = MIN (PUSH_ROUNDING (1), sp_alignment);
7240 /* We must return here, otherwise we may get a worse result from
7241 one of the choices below. There is nothing useful below as
7242 far as the stack pointer is concerned. */
7243 return nonzero &= ~ (sp_alignment - 1);
7247 /* If X is a register whose nonzero bits value is current, use it.
7248 Otherwise, if X is a register whose value we can find, use that
7249 value. Otherwise, use the previously-computed global nonzero bits
7250 for this register. */
7252 if (reg_last_set_value[REGNO (x)] != 0
7253 && reg_last_set_mode[REGNO (x)] == mode
7254 && (REG_N_SETS (REGNO (x)) == 1
7255 || reg_last_set_label[REGNO (x)] == label_tick)
7256 && INSN_CUID (reg_last_set[REGNO (x)]) < subst_low_cuid)
7257 return reg_last_set_nonzero_bits[REGNO (x)];
7259 tem = get_last_value (x);
7263 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
7264 /* If X is narrower than MODE and TEM is a non-negative
7265 constant that would appear negative in the mode of X,
7266 sign-extend it for use in reg_nonzero_bits because some
7267 machines (maybe most) will actually do the sign-extension
7268 and this is the conservative approach.
7270 ??? For 2.5, try to tighten up the MD files in this regard
7271 instead of this kludge. */
7273 if (GET_MODE_BITSIZE (GET_MODE (x)) < mode_width
7274 && GET_CODE (tem) == CONST_INT
7276 && 0 != (INTVAL (tem)
7277 & ((HOST_WIDE_INT) 1
7278 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
7279 tem = GEN_INT (INTVAL (tem)
7280 | ((HOST_WIDE_INT) (-1)
7281 << GET_MODE_BITSIZE (GET_MODE (x))));
7283 return nonzero_bits (tem, mode);
7285 else if (nonzero_sign_valid && reg_nonzero_bits[REGNO (x)])
7286 return reg_nonzero_bits[REGNO (x)] & nonzero;
7291 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
7292 /* If X is negative in MODE, sign-extend the value. */
7293 if (INTVAL (x) > 0 && mode_width < BITS_PER_WORD
7294 && 0 != (INTVAL (x) & ((HOST_WIDE_INT) 1 << (mode_width - 1))))
7295 return (INTVAL (x) | ((HOST_WIDE_INT) (-1) << mode_width));
7301 #ifdef LOAD_EXTEND_OP
7302 /* In many, if not most, RISC machines, reading a byte from memory
7303 zeros the rest of the register. Noticing that fact saves a lot
7304 of extra zero-extends. */
7305 if (LOAD_EXTEND_OP (GET_MODE (x)) == ZERO_EXTEND)
7306 nonzero &= GET_MODE_MASK (GET_MODE (x));
7316 /* If this produces an integer result, we know which bits are set.
7317 Code here used to clear bits outside the mode of X, but that is
7320 if (GET_MODE_CLASS (mode) == MODE_INT
7321 && mode_width <= HOST_BITS_PER_WIDE_INT)
7322 nonzero = STORE_FLAG_VALUE;
7327 /* Disabled to avoid exponential mutual recursion between nonzero_bits
7328 and num_sign_bit_copies. */
7329 if (num_sign_bit_copies (XEXP (x, 0), GET_MODE (x))
7330 == GET_MODE_BITSIZE (GET_MODE (x)))
7334 if (GET_MODE_SIZE (GET_MODE (x)) < mode_width)
7335 nonzero |= (GET_MODE_MASK (mode) & ~ GET_MODE_MASK (GET_MODE (x)));
7340 /* Disabled to avoid exponential mutual recursion between nonzero_bits
7341 and num_sign_bit_copies. */
7342 if (num_sign_bit_copies (XEXP (x, 0), GET_MODE (x))
7343 == GET_MODE_BITSIZE (GET_MODE (x)))
7349 nonzero &= (nonzero_bits (XEXP (x, 0), mode) & GET_MODE_MASK (mode));
7353 nonzero &= nonzero_bits (XEXP (x, 0), mode);
7354 if (GET_MODE (XEXP (x, 0)) != VOIDmode)
7355 nonzero &= GET_MODE_MASK (GET_MODE (XEXP (x, 0)));
7359 /* If the sign bit is known clear, this is the same as ZERO_EXTEND.
7360 Otherwise, show all the bits in the outer mode but not the inner
7362 inner_nz = nonzero_bits (XEXP (x, 0), mode);
7363 if (GET_MODE (XEXP (x, 0)) != VOIDmode)
7365 inner_nz &= GET_MODE_MASK (GET_MODE (XEXP (x, 0)));
7367 & (((HOST_WIDE_INT) 1
7368 << (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - 1))))
7369 inner_nz |= (GET_MODE_MASK (mode)
7370 & ~ GET_MODE_MASK (GET_MODE (XEXP (x, 0))));
7373 nonzero &= inner_nz;
7377 nonzero &= (nonzero_bits (XEXP (x, 0), mode)
7378 & nonzero_bits (XEXP (x, 1), mode));
7382 case UMIN: case UMAX: case SMIN: case SMAX:
7383 nonzero &= (nonzero_bits (XEXP (x, 0), mode)
7384 | nonzero_bits (XEXP (x, 1), mode));
7387 case PLUS: case MINUS:
7389 case DIV: case UDIV:
7390 case MOD: case UMOD:
7391 /* We can apply the rules of arithmetic to compute the number of
7392 high- and low-order zero bits of these operations. We start by
7393 computing the width (position of the highest-order non-zero bit)
7394 and the number of low-order zero bits for each value. */
7396 unsigned HOST_WIDE_INT nz0 = nonzero_bits (XEXP (x, 0), mode);
7397 unsigned HOST_WIDE_INT nz1 = nonzero_bits (XEXP (x, 1), mode);
7398 int width0 = floor_log2 (nz0) + 1;
7399 int width1 = floor_log2 (nz1) + 1;
7400 int low0 = floor_log2 (nz0 & -nz0);
7401 int low1 = floor_log2 (nz1 & -nz1);
7402 HOST_WIDE_INT op0_maybe_minusp
7403 = (nz0 & ((HOST_WIDE_INT) 1 << (mode_width - 1)));
7404 HOST_WIDE_INT op1_maybe_minusp
7405 = (nz1 & ((HOST_WIDE_INT) 1 << (mode_width - 1)));
7406 int result_width = mode_width;
7412 result_width = MAX (width0, width1) + 1;
7413 result_low = MIN (low0, low1);
7416 result_low = MIN (low0, low1);
7419 result_width = width0 + width1;
7420 result_low = low0 + low1;
7423 if (! op0_maybe_minusp && ! op1_maybe_minusp)
7424 result_width = width0;
7427 result_width = width0;
7430 if (! op0_maybe_minusp && ! op1_maybe_minusp)
7431 result_width = MIN (width0, width1);
7432 result_low = MIN (low0, low1);
7435 result_width = MIN (width0, width1);
7436 result_low = MIN (low0, low1);
7440 if (result_width < mode_width)
7441 nonzero &= ((HOST_WIDE_INT) 1 << result_width) - 1;
7444 nonzero &= ~ (((HOST_WIDE_INT) 1 << result_low) - 1);
7449 if (GET_CODE (XEXP (x, 1)) == CONST_INT
7450 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT)
7451 nonzero &= ((HOST_WIDE_INT) 1 << INTVAL (XEXP (x, 1))) - 1;
7455 /* If this is a SUBREG formed for a promoted variable that has
7456 been zero-extended, we know that at least the high-order bits
7457 are zero, though others might be too. */
7459 if (SUBREG_PROMOTED_VAR_P (x) && SUBREG_PROMOTED_UNSIGNED_P (x))
7460 nonzero = (GET_MODE_MASK (GET_MODE (x))
7461 & nonzero_bits (SUBREG_REG (x), GET_MODE (x)));
7463 /* If the inner mode is a single word for both the host and target
7464 machines, we can compute this from which bits of the inner
7465 object might be nonzero. */
7466 if (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x))) <= BITS_PER_WORD
7467 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x)))
7468 <= HOST_BITS_PER_WIDE_INT))
7470 nonzero &= nonzero_bits (SUBREG_REG (x), mode);
7472 #ifndef WORD_REGISTER_OPERATIONS
7473 /* On many CISC machines, accessing an object in a wider mode
7474 causes the high-order bits to become undefined. So they are
7475 not known to be zero. */
7476 if (GET_MODE_SIZE (GET_MODE (x))
7477 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
7478 nonzero |= (GET_MODE_MASK (GET_MODE (x))
7479 & ~ GET_MODE_MASK (GET_MODE (SUBREG_REG (x))));
7488 /* The nonzero bits are in two classes: any bits within MODE
7489 that aren't in GET_MODE (x) are always significant. The rest of the
7490 nonzero bits are those that are significant in the operand of
7491 the shift when shifted the appropriate number of bits. This
7492 shows that high-order bits are cleared by the right shift and
7493 low-order bits by left shifts. */
7494 if (GET_CODE (XEXP (x, 1)) == CONST_INT
7495 && INTVAL (XEXP (x, 1)) >= 0
7496 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT)
7498 enum machine_mode inner_mode = GET_MODE (x);
7499 int width = GET_MODE_BITSIZE (inner_mode);
7500 int count = INTVAL (XEXP (x, 1));
7501 unsigned HOST_WIDE_INT mode_mask = GET_MODE_MASK (inner_mode);
7502 unsigned HOST_WIDE_INT op_nonzero = nonzero_bits (XEXP (x, 0), mode);
7503 unsigned HOST_WIDE_INT inner = op_nonzero & mode_mask;
7504 unsigned HOST_WIDE_INT outer = 0;
7506 if (mode_width > width)
7507 outer = (op_nonzero & nonzero & ~ mode_mask);
7509 if (code == LSHIFTRT)
7511 else if (code == ASHIFTRT)
7515 /* If the sign bit may have been nonzero before the shift, we
7516 need to mark all the places it could have been copied to
7517 by the shift as possibly nonzero. */
7518 if (inner & ((HOST_WIDE_INT) 1 << (width - 1 - count)))
7519 inner |= (((HOST_WIDE_INT) 1 << count) - 1) << (width - count);
7521 else if (code == ASHIFT)
7524 inner = ((inner << (count % width)
7525 | (inner >> (width - (count % width)))) & mode_mask);
7527 nonzero &= (outer | inner);
7532 /* This is at most the number of bits in the mode. */
7533 nonzero = ((HOST_WIDE_INT) 1 << (floor_log2 (mode_width) + 1)) - 1;
7537 nonzero &= (nonzero_bits (XEXP (x, 1), mode)
7538 | nonzero_bits (XEXP (x, 2), mode));
7545 /* See the macro definition above. */
7546 #undef num_sign_bit_copies
7548 /* Return the number of bits at the high-order end of X that are known to
7549 be equal to the sign bit. X will be used in mode MODE; if MODE is
7550 VOIDmode, X will be used in its own mode. The returned value will always
7551 be between 1 and the number of bits in MODE. */
7554 num_sign_bit_copies (x, mode)
7556 enum machine_mode mode;
7558 enum rtx_code code = GET_CODE (x);
7560 int num0, num1, result;
7561 unsigned HOST_WIDE_INT nonzero;
7564 /* If we weren't given a mode, use the mode of X. If the mode is still
7565 VOIDmode, we don't know anything. Likewise if one of the modes is
7568 if (mode == VOIDmode)
7569 mode = GET_MODE (x);
7571 if (mode == VOIDmode || FLOAT_MODE_P (mode) || FLOAT_MODE_P (GET_MODE (x)))
7574 bitwidth = GET_MODE_BITSIZE (mode);
7576 /* For a smaller object, just ignore the high bits. */
7577 if (bitwidth < GET_MODE_BITSIZE (GET_MODE (x)))
7578 return MAX (1, (num_sign_bit_copies (x, GET_MODE (x))
7579 - (GET_MODE_BITSIZE (GET_MODE (x)) - bitwidth)));
7581 #ifndef WORD_REGISTER_OPERATIONS
7582 /* If this machine does not do all register operations on the entire
7583 register and MODE is wider than the mode of X, we can say nothing
7584 at all about the high-order bits. */
7585 if (GET_MODE (x) != VOIDmode && bitwidth > GET_MODE_BITSIZE (GET_MODE (x)))
7593 #ifdef POINTERS_EXTEND_UNSIGNED
7594 /* If pointers extend signed and this is a pointer in Pmode, say that
7595 all the bits above ptr_mode are known to be sign bit copies. */
7596 if (! POINTERS_EXTEND_UNSIGNED && GET_MODE (x) == Pmode && mode == Pmode
7597 && REGNO_POINTER_FLAG (REGNO (x)))
7598 return GET_MODE_BITSIZE (Pmode) - GET_MODE_BITSIZE (ptr_mode) + 1;
7601 if (reg_last_set_value[REGNO (x)] != 0
7602 && reg_last_set_mode[REGNO (x)] == mode
7603 && (REG_N_SETS (REGNO (x)) == 1
7604 || reg_last_set_label[REGNO (x)] == label_tick)
7605 && INSN_CUID (reg_last_set[REGNO (x)]) < subst_low_cuid)
7606 return reg_last_set_sign_bit_copies[REGNO (x)];
7608 tem = get_last_value (x);
7610 return num_sign_bit_copies (tem, mode);
7612 if (nonzero_sign_valid && reg_sign_bit_copies[REGNO (x)] != 0)
7613 return reg_sign_bit_copies[REGNO (x)];
7617 #ifdef LOAD_EXTEND_OP
7618 /* Some RISC machines sign-extend all loads of smaller than a word. */
7619 if (LOAD_EXTEND_OP (GET_MODE (x)) == SIGN_EXTEND)
7620 return MAX (1, bitwidth - GET_MODE_BITSIZE (GET_MODE (x)) + 1);
7625 /* If the constant is negative, take its 1's complement and remask.
7626 Then see how many zero bits we have. */
7627 nonzero = INTVAL (x) & GET_MODE_MASK (mode);
7628 if (bitwidth <= HOST_BITS_PER_WIDE_INT
7629 && (nonzero & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0)
7630 nonzero = (~ nonzero) & GET_MODE_MASK (mode);
7632 return (nonzero == 0 ? bitwidth : bitwidth - floor_log2 (nonzero) - 1);
7635 /* If this is a SUBREG for a promoted object that is sign-extended
7636 and we are looking at it in a wider mode, we know that at least the
7637 high-order bits are known to be sign bit copies. */
7639 if (SUBREG_PROMOTED_VAR_P (x) && ! SUBREG_PROMOTED_UNSIGNED_P (x))
7640 return MAX (bitwidth - GET_MODE_BITSIZE (GET_MODE (x)) + 1,
7641 num_sign_bit_copies (SUBREG_REG (x), mode));
7643 /* For a smaller object, just ignore the high bits. */
7644 if (bitwidth <= GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x))))
7646 num0 = num_sign_bit_copies (SUBREG_REG (x), VOIDmode);
7647 return MAX (1, (num0
7648 - (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x)))
7652 #ifdef WORD_REGISTER_OPERATIONS
7653 #ifdef LOAD_EXTEND_OP
7654 /* For paradoxical SUBREGs on machines where all register operations
7655 affect the entire register, just look inside. Note that we are
7656 passing MODE to the recursive call, so the number of sign bit copies
7657 will remain relative to that mode, not the inner mode. */
7659 /* This works only if loads sign extend. Otherwise, if we get a
7660 reload for the inner part, it may be loaded from the stack, and
7661 then we lose all sign bit copies that existed before the store
7664 if ((GET_MODE_SIZE (GET_MODE (x))
7665 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
7666 && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (x))) == SIGN_EXTEND)
7667 return num_sign_bit_copies (SUBREG_REG (x), mode);
7673 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
7674 return MAX (1, bitwidth - INTVAL (XEXP (x, 1)));
7678 return (bitwidth - GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
7679 + num_sign_bit_copies (XEXP (x, 0), VOIDmode));
7682 /* For a smaller object, just ignore the high bits. */
7683 num0 = num_sign_bit_copies (XEXP (x, 0), VOIDmode);
7684 return MAX (1, (num0 - (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
7688 return num_sign_bit_copies (XEXP (x, 0), mode);
7690 case ROTATE: case ROTATERT:
7691 /* If we are rotating left by a number of bits less than the number
7692 of sign bit copies, we can just subtract that amount from the
7694 if (GET_CODE (XEXP (x, 1)) == CONST_INT
7695 && INTVAL (XEXP (x, 1)) >= 0 && INTVAL (XEXP (x, 1)) < bitwidth)
7697 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
7698 return MAX (1, num0 - (code == ROTATE ? INTVAL (XEXP (x, 1))
7699 : bitwidth - INTVAL (XEXP (x, 1))));
7704 /* In general, this subtracts one sign bit copy. But if the value
7705 is known to be positive, the number of sign bit copies is the
7706 same as that of the input. Finally, if the input has just one bit
7707 that might be nonzero, all the bits are copies of the sign bit. */
7708 nonzero = nonzero_bits (XEXP (x, 0), mode);
7712 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
7714 && bitwidth <= HOST_BITS_PER_WIDE_INT
7715 && (((HOST_WIDE_INT) 1 << (bitwidth - 1)) & nonzero))
7720 case IOR: case AND: case XOR:
7721 case SMIN: case SMAX: case UMIN: case UMAX:
7722 /* Logical operations will preserve the number of sign-bit copies.
7723 MIN and MAX operations always return one of the operands. */
7724 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
7725 num1 = num_sign_bit_copies (XEXP (x, 1), mode);
7726 return MIN (num0, num1);
7728 case PLUS: case MINUS:
7729 /* For addition and subtraction, we can have a 1-bit carry. However,
7730 if we are subtracting 1 from a positive number, there will not
7731 be such a carry. Furthermore, if the positive number is known to
7732 be 0 or 1, we know the result is either -1 or 0. */
7734 if (code == PLUS && XEXP (x, 1) == constm1_rtx
7735 && bitwidth <= HOST_BITS_PER_WIDE_INT)
7737 nonzero = nonzero_bits (XEXP (x, 0), mode);
7738 if ((((HOST_WIDE_INT) 1 << (bitwidth - 1)) & nonzero) == 0)
7739 return (nonzero == 1 || nonzero == 0 ? bitwidth
7740 : bitwidth - floor_log2 (nonzero) - 1);
7743 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
7744 num1 = num_sign_bit_copies (XEXP (x, 1), mode);
7745 return MAX (1, MIN (num0, num1) - 1);
7748 /* The number of bits of the product is the sum of the number of
7749 bits of both terms. However, unless one of the terms if known
7750 to be positive, we must allow for an additional bit since negating
7751 a negative number can remove one sign bit copy. */
7753 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
7754 num1 = num_sign_bit_copies (XEXP (x, 1), mode);
7756 result = bitwidth - (bitwidth - num0) - (bitwidth - num1);
7758 && bitwidth <= HOST_BITS_PER_WIDE_INT
7759 && ((nonzero_bits (XEXP (x, 0), mode)
7760 & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0)
7761 && ((nonzero_bits (XEXP (x, 1), mode)
7762 & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0))
7765 return MAX (1, result);
7768 /* The result must be <= the first operand. */
7769 return num_sign_bit_copies (XEXP (x, 0), mode);
7772 /* The result must be <= the scond operand. */
7773 return num_sign_bit_copies (XEXP (x, 1), mode);
7776 /* Similar to unsigned division, except that we have to worry about
7777 the case where the divisor is negative, in which case we have
7779 result = num_sign_bit_copies (XEXP (x, 0), mode);
7781 && bitwidth <= HOST_BITS_PER_WIDE_INT
7782 && (nonzero_bits (XEXP (x, 1), mode)
7783 & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0)
7789 result = num_sign_bit_copies (XEXP (x, 1), mode);
7791 && bitwidth <= HOST_BITS_PER_WIDE_INT
7792 && (nonzero_bits (XEXP (x, 1), mode)
7793 & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0)
7799 /* Shifts by a constant add to the number of bits equal to the
7801 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
7802 if (GET_CODE (XEXP (x, 1)) == CONST_INT
7803 && INTVAL (XEXP (x, 1)) > 0)
7804 num0 = MIN (bitwidth, num0 + INTVAL (XEXP (x, 1)));
7809 /* Left shifts destroy copies. */
7810 if (GET_CODE (XEXP (x, 1)) != CONST_INT
7811 || INTVAL (XEXP (x, 1)) < 0
7812 || INTVAL (XEXP (x, 1)) >= bitwidth)
7815 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
7816 return MAX (1, num0 - INTVAL (XEXP (x, 1)));
7819 num0 = num_sign_bit_copies (XEXP (x, 1), mode);
7820 num1 = num_sign_bit_copies (XEXP (x, 2), mode);
7821 return MIN (num0, num1);
7823 case EQ: case NE: case GE: case GT: case LE: case LT:
7824 case GEU: case GTU: case LEU: case LTU:
7825 if (STORE_FLAG_VALUE == -1)
7829 /* If we haven't been able to figure it out by one of the above rules,
7830 see if some of the high-order bits are known to be zero. If so,
7831 count those bits and return one less than that amount. If we can't
7832 safely compute the mask for this mode, always return BITWIDTH. */
7834 if (bitwidth > HOST_BITS_PER_WIDE_INT)
7837 nonzero = nonzero_bits (x, mode);
7838 return (nonzero & ((HOST_WIDE_INT) 1 << (bitwidth - 1))
7839 ? 1 : bitwidth - floor_log2 (nonzero) - 1);
7842 /* Return the number of "extended" bits there are in X, when interpreted
7843 as a quantity in MODE whose signedness is indicated by UNSIGNEDP. For
7844 unsigned quantities, this is the number of high-order zero bits.
7845 For signed quantities, this is the number of copies of the sign bit
7846 minus 1. In both case, this function returns the number of "spare"
7847 bits. For example, if two quantities for which this function returns
7848 at least 1 are added, the addition is known not to overflow.
7850 This function will always return 0 unless called during combine, which
7851 implies that it must be called from a define_split. */
7854 extended_count (x, mode, unsignedp)
7856 enum machine_mode mode;
7859 if (nonzero_sign_valid == 0)
7863 ? (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
7864 && (GET_MODE_BITSIZE (mode) - 1
7865 - floor_log2 (nonzero_bits (x, mode))))
7866 : num_sign_bit_copies (x, mode) - 1);
7869 /* This function is called from `simplify_shift_const' to merge two
7870 outer operations. Specifically, we have already found that we need
7871 to perform operation *POP0 with constant *PCONST0 at the outermost
7872 position. We would now like to also perform OP1 with constant CONST1
7873 (with *POP0 being done last).
7875 Return 1 if we can do the operation and update *POP0 and *PCONST0 with
7876 the resulting operation. *PCOMP_P is set to 1 if we would need to
7877 complement the innermost operand, otherwise it is unchanged.
7879 MODE is the mode in which the operation will be done. No bits outside
7880 the width of this mode matter. It is assumed that the width of this mode
7881 is smaller than or equal to HOST_BITS_PER_WIDE_INT.
7883 If *POP0 or OP1 are NIL, it means no operation is required. Only NEG, PLUS,
7884 IOR, XOR, and AND are supported. We may set *POP0 to SET if the proper
7885 result is simply *PCONST0.
7887 If the resulting operation cannot be expressed as one operation, we
7888 return 0 and do not change *POP0, *PCONST0, and *PCOMP_P. */
7891 merge_outer_ops (pop0, pconst0, op1, const1, mode, pcomp_p)
7892 enum rtx_code *pop0;
7893 HOST_WIDE_INT *pconst0;
7895 HOST_WIDE_INT const1;
7896 enum machine_mode mode;
7899 enum rtx_code op0 = *pop0;
7900 HOST_WIDE_INT const0 = *pconst0;
7901 int width = GET_MODE_BITSIZE (mode);
7903 const0 &= GET_MODE_MASK (mode);
7904 const1 &= GET_MODE_MASK (mode);
7906 /* If OP0 is an AND, clear unimportant bits in CONST1. */
7910 /* If OP0 or OP1 is NIL, this is easy. Similarly if they are the same or
7913 if (op1 == NIL || op0 == SET)
7916 else if (op0 == NIL)
7917 op0 = op1, const0 = const1;
7919 else if (op0 == op1)
7941 /* Otherwise, if either is a PLUS or NEG, we can't do anything. */
7942 else if (op0 == PLUS || op1 == PLUS || op0 == NEG || op1 == NEG)
7945 /* If the two constants aren't the same, we can't do anything. The
7946 remaining six cases can all be done. */
7947 else if (const0 != const1)
7955 /* (a & b) | b == b */
7957 else /* op1 == XOR */
7958 /* (a ^ b) | b == a | b */
7964 /* (a & b) ^ b == (~a) & b */
7965 op0 = AND, *pcomp_p = 1;
7966 else /* op1 == IOR */
7967 /* (a | b) ^ b == a & ~b */
7968 op0 = AND, *pconst0 = ~ const0;
7973 /* (a | b) & b == b */
7975 else /* op1 == XOR */
7976 /* (a ^ b) & b) == (~a) & b */
7981 /* Check for NO-OP cases. */
7982 const0 &= GET_MODE_MASK (mode);
7984 && (op0 == IOR || op0 == XOR || op0 == PLUS))
7986 else if (const0 == 0 && op0 == AND)
7988 else if (const0 == GET_MODE_MASK (mode) && op0 == AND)
7991 /* If this would be an entire word for the target, but is not for
7992 the host, then sign-extend on the host so that the number will look
7993 the same way on the host that it would on the target.
7995 For example, when building a 64 bit alpha hosted 32 bit sparc
7996 targeted compiler, then we want the 32 bit unsigned value -1 to be
7997 represented as a 64 bit value -1, and not as 0x00000000ffffffff.
7998 The later confuses the sparc backend. */
8000 if (BITS_PER_WORD < HOST_BITS_PER_WIDE_INT && BITS_PER_WORD == width
8001 && (const0 & ((HOST_WIDE_INT) 1 << (width - 1))))
8002 const0 |= ((HOST_WIDE_INT) (-1) << width);
8010 /* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift.
8011 The result of the shift is RESULT_MODE. X, if non-zero, is an expression
8012 that we started with.
8014 The shift is normally computed in the widest mode we find in VAROP, as
8015 long as it isn't a different number of words than RESULT_MODE. Exceptions
8016 are ASHIFTRT and ROTATE, which are always done in their original mode, */
8019 simplify_shift_const (x, code, result_mode, varop, count)
8022 enum machine_mode result_mode;
8026 enum rtx_code orig_code = code;
8027 int orig_count = count;
8028 enum machine_mode mode = result_mode;
8029 enum machine_mode shift_mode, tmode;
8031 = (GET_MODE_SIZE (mode) + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD;
8032 /* We form (outer_op (code varop count) (outer_const)). */
8033 enum rtx_code outer_op = NIL;
8034 HOST_WIDE_INT outer_const = 0;
8036 int complement_p = 0;
8039 /* If we were given an invalid count, don't do anything except exactly
8040 what was requested. */
8042 if (count < 0 || count > GET_MODE_BITSIZE (mode))
8047 return gen_rtx (code, mode, varop, GEN_INT (count));
8050 /* Unless one of the branches of the `if' in this loop does a `continue',
8051 we will `break' the loop after the `if'. */
8055 /* If we have an operand of (clobber (const_int 0)), just return that
8057 if (GET_CODE (varop) == CLOBBER)
8060 /* If we discovered we had to complement VAROP, leave. Making a NOT
8061 here would cause an infinite loop. */
8065 /* Convert ROTATERT to ROTATE. */
8066 if (code == ROTATERT)
8067 code = ROTATE, count = GET_MODE_BITSIZE (result_mode) - count;
8069 /* We need to determine what mode we will do the shift in. If the
8070 shift is a right shift or a ROTATE, we must always do it in the mode
8071 it was originally done in. Otherwise, we can do it in MODE, the
8072 widest mode encountered. */
8074 = (code == ASHIFTRT || code == LSHIFTRT || code == ROTATE
8075 ? result_mode : mode);
8077 /* Handle cases where the count is greater than the size of the mode
8078 minus 1. For ASHIFT, use the size minus one as the count (this can
8079 occur when simplifying (lshiftrt (ashiftrt ..))). For rotates,
8080 take the count modulo the size. For other shifts, the result is
8083 Since these shifts are being produced by the compiler by combining
8084 multiple operations, each of which are defined, we know what the
8085 result is supposed to be. */
8087 if (count > GET_MODE_BITSIZE (shift_mode) - 1)
8089 if (code == ASHIFTRT)
8090 count = GET_MODE_BITSIZE (shift_mode) - 1;
8091 else if (code == ROTATE || code == ROTATERT)
8092 count %= GET_MODE_BITSIZE (shift_mode);
8095 /* We can't simply return zero because there may be an
8103 /* Negative counts are invalid and should not have been made (a
8104 programmer-specified negative count should have been handled
8109 /* An arithmetic right shift of a quantity known to be -1 or 0
8111 if (code == ASHIFTRT
8112 && (num_sign_bit_copies (varop, shift_mode)
8113 == GET_MODE_BITSIZE (shift_mode)))
8119 /* If we are doing an arithmetic right shift and discarding all but
8120 the sign bit copies, this is equivalent to doing a shift by the
8121 bitsize minus one. Convert it into that shift because it will often
8122 allow other simplifications. */
8124 if (code == ASHIFTRT
8125 && (count + num_sign_bit_copies (varop, shift_mode)
8126 >= GET_MODE_BITSIZE (shift_mode)))
8127 count = GET_MODE_BITSIZE (shift_mode) - 1;
8129 /* We simplify the tests below and elsewhere by converting
8130 ASHIFTRT to LSHIFTRT if we know the sign bit is clear.
8131 `make_compound_operation' will convert it to a ASHIFTRT for
8132 those machines (such as Vax) that don't have a LSHIFTRT. */
8133 if (GET_MODE_BITSIZE (shift_mode) <= HOST_BITS_PER_WIDE_INT
8135 && ((nonzero_bits (varop, shift_mode)
8136 & ((HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (shift_mode) - 1)))
8140 switch (GET_CODE (varop))
8146 new = expand_compound_operation (varop);
8155 /* If we have (xshiftrt (mem ...) C) and C is MODE_WIDTH
8156 minus the width of a smaller mode, we can do this with a
8157 SIGN_EXTEND or ZERO_EXTEND from the narrower memory location. */
8158 if ((code == ASHIFTRT || code == LSHIFTRT)
8159 && ! mode_dependent_address_p (XEXP (varop, 0))
8160 && ! MEM_VOLATILE_P (varop)
8161 && (tmode = mode_for_size (GET_MODE_BITSIZE (mode) - count,
8162 MODE_INT, 1)) != BLKmode)
8164 if (BYTES_BIG_ENDIAN)
8165 new = gen_rtx (MEM, tmode, XEXP (varop, 0));
8167 new = gen_rtx (MEM, tmode,
8168 plus_constant (XEXP (varop, 0),
8169 count / BITS_PER_UNIT));
8170 RTX_UNCHANGING_P (new) = RTX_UNCHANGING_P (varop);
8171 MEM_VOLATILE_P (new) = MEM_VOLATILE_P (varop);
8172 MEM_IN_STRUCT_P (new) = MEM_IN_STRUCT_P (varop);
8173 varop = gen_rtx_combine (code == ASHIFTRT ? SIGN_EXTEND
8174 : ZERO_EXTEND, mode, new);
8181 /* Similar to the case above, except that we can only do this if
8182 the resulting mode is the same as that of the underlying
8183 MEM and adjust the address depending on the *bits* endianness
8184 because of the way that bit-field extract insns are defined. */
8185 if ((code == ASHIFTRT || code == LSHIFTRT)
8186 && (tmode = mode_for_size (GET_MODE_BITSIZE (mode) - count,
8187 MODE_INT, 1)) != BLKmode
8188 && tmode == GET_MODE (XEXP (varop, 0)))
8190 if (BITS_BIG_ENDIAN)
8191 new = XEXP (varop, 0);
8194 new = copy_rtx (XEXP (varop, 0));
8195 SUBST (XEXP (new, 0),
8196 plus_constant (XEXP (new, 0),
8197 count / BITS_PER_UNIT));
8200 varop = gen_rtx_combine (code == ASHIFTRT ? SIGN_EXTEND
8201 : ZERO_EXTEND, mode, new);
8208 /* If VAROP is a SUBREG, strip it as long as the inner operand has
8209 the same number of words as what we've seen so far. Then store
8210 the widest mode in MODE. */
8211 if (subreg_lowpart_p (varop)
8212 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop)))
8213 > GET_MODE_SIZE (GET_MODE (varop)))
8214 && (((GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop)))
8215 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
8218 varop = SUBREG_REG (varop);
8219 if (GET_MODE_SIZE (GET_MODE (varop)) > GET_MODE_SIZE (mode))
8220 mode = GET_MODE (varop);
8226 /* Some machines use MULT instead of ASHIFT because MULT
8227 is cheaper. But it is still better on those machines to
8228 merge two shifts into one. */
8229 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
8230 && exact_log2 (INTVAL (XEXP (varop, 1))) >= 0)
8232 varop = gen_binary (ASHIFT, GET_MODE (varop), XEXP (varop, 0),
8233 GEN_INT (exact_log2 (INTVAL (XEXP (varop, 1)))));;
8239 /* Similar, for when divides are cheaper. */
8240 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
8241 && exact_log2 (INTVAL (XEXP (varop, 1))) >= 0)
8243 varop = gen_binary (LSHIFTRT, GET_MODE (varop), XEXP (varop, 0),
8244 GEN_INT (exact_log2 (INTVAL (XEXP (varop, 1)))));
8250 /* If we are extracting just the sign bit of an arithmetic right
8251 shift, that shift is not needed. */
8252 if (code == LSHIFTRT && count == GET_MODE_BITSIZE (result_mode) - 1)
8254 varop = XEXP (varop, 0);
8258 /* ... fall through ... */
8263 /* Here we have two nested shifts. The result is usually the
8264 AND of a new shift with a mask. We compute the result below. */
8265 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
8266 && INTVAL (XEXP (varop, 1)) >= 0
8267 && INTVAL (XEXP (varop, 1)) < GET_MODE_BITSIZE (GET_MODE (varop))
8268 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
8269 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
8271 enum rtx_code first_code = GET_CODE (varop);
8272 int first_count = INTVAL (XEXP (varop, 1));
8273 unsigned HOST_WIDE_INT mask;
8276 /* We have one common special case. We can't do any merging if
8277 the inner code is an ASHIFTRT of a smaller mode. However, if
8278 we have (ashift:M1 (subreg:M1 (ashiftrt:M2 FOO C1) 0) C2)
8279 with C2 == GET_MODE_BITSIZE (M1) - GET_MODE_BITSIZE (M2),
8280 we can convert it to
8281 (ashiftrt:M1 (ashift:M1 (and:M1 (subreg:M1 FOO 0 C2) C3) C1).
8282 This simplifies certain SIGN_EXTEND operations. */
8283 if (code == ASHIFT && first_code == ASHIFTRT
8284 && (GET_MODE_BITSIZE (result_mode)
8285 - GET_MODE_BITSIZE (GET_MODE (varop))) == count)
8287 /* C3 has the low-order C1 bits zero. */
8289 mask = (GET_MODE_MASK (mode)
8290 & ~ (((HOST_WIDE_INT) 1 << first_count) - 1));
8292 varop = simplify_and_const_int (NULL_RTX, result_mode,
8293 XEXP (varop, 0), mask);
8294 varop = simplify_shift_const (NULL_RTX, ASHIFT, result_mode,
8296 count = first_count;
8301 /* If this was (ashiftrt (ashift foo C1) C2) and FOO has more
8302 than C1 high-order bits equal to the sign bit, we can convert
8303 this to either an ASHIFT or a ASHIFTRT depending on the
8306 We cannot do this if VAROP's mode is not SHIFT_MODE. */
8308 if (code == ASHIFTRT && first_code == ASHIFT
8309 && GET_MODE (varop) == shift_mode
8310 && (num_sign_bit_copies (XEXP (varop, 0), shift_mode)
8313 count -= first_count;
8315 count = - count, code = ASHIFT;
8316 varop = XEXP (varop, 0);
8320 /* There are some cases we can't do. If CODE is ASHIFTRT,
8321 we can only do this if FIRST_CODE is also ASHIFTRT.
8323 We can't do the case when CODE is ROTATE and FIRST_CODE is
8326 If the mode of this shift is not the mode of the outer shift,
8327 we can't do this if either shift is a right shift or ROTATE.
8329 Finally, we can't do any of these if the mode is too wide
8330 unless the codes are the same.
8332 Handle the case where the shift codes are the same
8335 if (code == first_code)
8337 if (GET_MODE (varop) != result_mode
8338 && (code == ASHIFTRT || code == LSHIFTRT
8342 count += first_count;
8343 varop = XEXP (varop, 0);
8347 if (code == ASHIFTRT
8348 || (code == ROTATE && first_code == ASHIFTRT)
8349 || GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT
8350 || (GET_MODE (varop) != result_mode
8351 && (first_code == ASHIFTRT || first_code == LSHIFTRT
8352 || first_code == ROTATE
8353 || code == ROTATE)))
8356 /* To compute the mask to apply after the shift, shift the
8357 nonzero bits of the inner shift the same way the
8358 outer shift will. */
8360 mask_rtx = GEN_INT (nonzero_bits (varop, GET_MODE (varop)));
8363 = simplify_binary_operation (code, result_mode, mask_rtx,
8366 /* Give up if we can't compute an outer operation to use. */
8368 || GET_CODE (mask_rtx) != CONST_INT
8369 || ! merge_outer_ops (&outer_op, &outer_const, AND,
8371 result_mode, &complement_p))
8374 /* If the shifts are in the same direction, we add the
8375 counts. Otherwise, we subtract them. */
8376 if ((code == ASHIFTRT || code == LSHIFTRT)
8377 == (first_code == ASHIFTRT || first_code == LSHIFTRT))
8378 count += first_count;
8380 count -= first_count;
8382 /* If COUNT is positive, the new shift is usually CODE,
8383 except for the two exceptions below, in which case it is
8384 FIRST_CODE. If the count is negative, FIRST_CODE should
8387 && ((first_code == ROTATE && code == ASHIFT)
8388 || (first_code == ASHIFTRT && code == LSHIFTRT)))
8391 code = first_code, count = - count;
8393 varop = XEXP (varop, 0);
8397 /* If we have (A << B << C) for any shift, we can convert this to
8398 (A << C << B). This wins if A is a constant. Only try this if
8399 B is not a constant. */
8401 else if (GET_CODE (varop) == code
8402 && GET_CODE (XEXP (varop, 1)) != CONST_INT
8404 = simplify_binary_operation (code, mode,
8408 varop = gen_rtx_combine (code, mode, new, XEXP (varop, 1));
8415 /* Make this fit the case below. */
8416 varop = gen_rtx_combine (XOR, mode, XEXP (varop, 0),
8417 GEN_INT (GET_MODE_MASK (mode)));
8423 /* If we have (xshiftrt (ior (plus X (const_int -1)) X) C)
8424 with C the size of VAROP - 1 and the shift is logical if
8425 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
8426 we have an (le X 0) operation. If we have an arithmetic shift
8427 and STORE_FLAG_VALUE is 1 or we have a logical shift with
8428 STORE_FLAG_VALUE of -1, we have a (neg (le X 0)) operation. */
8430 if (GET_CODE (varop) == IOR && GET_CODE (XEXP (varop, 0)) == PLUS
8431 && XEXP (XEXP (varop, 0), 1) == constm1_rtx
8432 && (STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
8433 && (code == LSHIFTRT || code == ASHIFTRT)
8434 && count == GET_MODE_BITSIZE (GET_MODE (varop)) - 1
8435 && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
8438 varop = gen_rtx_combine (LE, GET_MODE (varop), XEXP (varop, 1),
8441 if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
8442 varop = gen_rtx_combine (NEG, GET_MODE (varop), varop);
8447 /* If we have (shift (logical)), move the logical to the outside
8448 to allow it to possibly combine with another logical and the
8449 shift to combine with another shift. This also canonicalizes to
8450 what a ZERO_EXTRACT looks like. Also, some machines have
8451 (and (shift)) insns. */
8453 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
8454 && (new = simplify_binary_operation (code, result_mode,
8456 GEN_INT (count))) != 0
8457 && GET_CODE(new) == CONST_INT
8458 && merge_outer_ops (&outer_op, &outer_const, GET_CODE (varop),
8459 INTVAL (new), result_mode, &complement_p))
8461 varop = XEXP (varop, 0);
8465 /* If we can't do that, try to simplify the shift in each arm of the
8466 logical expression, make a new logical expression, and apply
8467 the inverse distributive law. */
8469 rtx lhs = simplify_shift_const (NULL_RTX, code, shift_mode,
8470 XEXP (varop, 0), count);
8471 rtx rhs = simplify_shift_const (NULL_RTX, code, shift_mode,
8472 XEXP (varop, 1), count);
8474 varop = gen_binary (GET_CODE (varop), shift_mode, lhs, rhs);
8475 varop = apply_distributive_law (varop);
8482 /* convert (lshiftrt (eq FOO 0) C) to (xor FOO 1) if STORE_FLAG_VALUE
8483 says that the sign bit can be tested, FOO has mode MODE, C is
8484 GET_MODE_BITSIZE (MODE) - 1, and FOO has only its low-order bit
8485 that may be nonzero. */
8486 if (code == LSHIFTRT
8487 && XEXP (varop, 1) == const0_rtx
8488 && GET_MODE (XEXP (varop, 0)) == result_mode
8489 && count == GET_MODE_BITSIZE (result_mode) - 1
8490 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
8491 && ((STORE_FLAG_VALUE
8492 & ((HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (result_mode) - 1))))
8493 && nonzero_bits (XEXP (varop, 0), result_mode) == 1
8494 && merge_outer_ops (&outer_op, &outer_const, XOR,
8495 (HOST_WIDE_INT) 1, result_mode,
8498 varop = XEXP (varop, 0);
8505 /* (lshiftrt (neg A) C) where A is either 0 or 1 and C is one less
8506 than the number of bits in the mode is equivalent to A. */
8507 if (code == LSHIFTRT && count == GET_MODE_BITSIZE (result_mode) - 1
8508 && nonzero_bits (XEXP (varop, 0), result_mode) == 1)
8510 varop = XEXP (varop, 0);
8515 /* NEG commutes with ASHIFT since it is multiplication. Move the
8516 NEG outside to allow shifts to combine. */
8518 && merge_outer_ops (&outer_op, &outer_const, NEG,
8519 (HOST_WIDE_INT) 0, result_mode,
8522 varop = XEXP (varop, 0);
8528 /* (lshiftrt (plus A -1) C) where A is either 0 or 1 and C
8529 is one less than the number of bits in the mode is
8530 equivalent to (xor A 1). */
8531 if (code == LSHIFTRT && count == GET_MODE_BITSIZE (result_mode) - 1
8532 && XEXP (varop, 1) == constm1_rtx
8533 && nonzero_bits (XEXP (varop, 0), result_mode) == 1
8534 && merge_outer_ops (&outer_op, &outer_const, XOR,
8535 (HOST_WIDE_INT) 1, result_mode,
8539 varop = XEXP (varop, 0);
8543 /* If we have (xshiftrt (plus FOO BAR) C), and the only bits
8544 that might be nonzero in BAR are those being shifted out and those
8545 bits are known zero in FOO, we can replace the PLUS with FOO.
8546 Similarly in the other operand order. This code occurs when
8547 we are computing the size of a variable-size array. */
8549 if ((code == ASHIFTRT || code == LSHIFTRT)
8550 && count < HOST_BITS_PER_WIDE_INT
8551 && nonzero_bits (XEXP (varop, 1), result_mode) >> count == 0
8552 && (nonzero_bits (XEXP (varop, 1), result_mode)
8553 & nonzero_bits (XEXP (varop, 0), result_mode)) == 0)
8555 varop = XEXP (varop, 0);
8558 else if ((code == ASHIFTRT || code == LSHIFTRT)
8559 && count < HOST_BITS_PER_WIDE_INT
8560 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
8561 && 0 == (nonzero_bits (XEXP (varop, 0), result_mode)
8563 && 0 == (nonzero_bits (XEXP (varop, 0), result_mode)
8564 & nonzero_bits (XEXP (varop, 1),
8567 varop = XEXP (varop, 1);
8571 /* (ashift (plus foo C) N) is (plus (ashift foo N) C'). */
8573 && GET_CODE (XEXP (varop, 1)) == CONST_INT
8574 && (new = simplify_binary_operation (ASHIFT, result_mode,
8576 GEN_INT (count))) != 0
8577 && GET_CODE(new) == CONST_INT
8578 && merge_outer_ops (&outer_op, &outer_const, PLUS,
8579 INTVAL (new), result_mode, &complement_p))
8581 varop = XEXP (varop, 0);
8587 /* If we have (xshiftrt (minus (ashiftrt X C)) X) C)
8588 with C the size of VAROP - 1 and the shift is logical if
8589 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
8590 we have a (gt X 0) operation. If the shift is arithmetic with
8591 STORE_FLAG_VALUE of 1 or logical with STORE_FLAG_VALUE == -1,
8592 we have a (neg (gt X 0)) operation. */
8594 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
8595 && GET_CODE (XEXP (varop, 0)) == ASHIFTRT
8596 && count == GET_MODE_BITSIZE (GET_MODE (varop)) - 1
8597 && (code == LSHIFTRT || code == ASHIFTRT)
8598 && GET_CODE (XEXP (XEXP (varop, 0), 1)) == CONST_INT
8599 && INTVAL (XEXP (XEXP (varop, 0), 1)) == count
8600 && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
8603 varop = gen_rtx_combine (GT, GET_MODE (varop), XEXP (varop, 1),
8606 if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
8607 varop = gen_rtx_combine (NEG, GET_MODE (varop), varop);
8617 /* We need to determine what mode to do the shift in. If the shift is
8618 a right shift or ROTATE, we must always do it in the mode it was
8619 originally done in. Otherwise, we can do it in MODE, the widest mode
8620 encountered. The code we care about is that of the shift that will
8621 actually be done, not the shift that was originally requested. */
8623 = (code == ASHIFTRT || code == LSHIFTRT || code == ROTATE
8624 ? result_mode : mode);
8626 /* We have now finished analyzing the shift. The result should be
8627 a shift of type CODE with SHIFT_MODE shifting VAROP COUNT places. If
8628 OUTER_OP is non-NIL, it is an operation that needs to be applied
8629 to the result of the shift. OUTER_CONST is the relevant constant,
8630 but we must turn off all bits turned off in the shift.
8632 If we were passed a value for X, see if we can use any pieces of
8633 it. If not, make new rtx. */
8635 if (x && GET_RTX_CLASS (GET_CODE (x)) == '2'
8636 && GET_CODE (XEXP (x, 1)) == CONST_INT
8637 && INTVAL (XEXP (x, 1)) == count)
8638 const_rtx = XEXP (x, 1);
8640 const_rtx = GEN_INT (count);
8642 if (x && GET_CODE (XEXP (x, 0)) == SUBREG
8643 && GET_MODE (XEXP (x, 0)) == shift_mode
8644 && SUBREG_REG (XEXP (x, 0)) == varop)
8645 varop = XEXP (x, 0);
8646 else if (GET_MODE (varop) != shift_mode)
8647 varop = gen_lowpart_for_combine (shift_mode, varop);
8649 /* If we can't make the SUBREG, try to return what we were given. */
8650 if (GET_CODE (varop) == CLOBBER)
8651 return x ? x : varop;
8653 new = simplify_binary_operation (code, shift_mode, varop, const_rtx);
8658 if (x == 0 || GET_CODE (x) != code || GET_MODE (x) != shift_mode)
8659 x = gen_rtx_combine (code, shift_mode, varop, const_rtx);
8661 SUBST (XEXP (x, 0), varop);
8662 SUBST (XEXP (x, 1), const_rtx);
8665 /* If we have an outer operation and we just made a shift, it is
8666 possible that we could have simplified the shift were it not
8667 for the outer operation. So try to do the simplification
8670 if (outer_op != NIL && GET_CODE (x) == code
8671 && GET_CODE (XEXP (x, 1)) == CONST_INT)
8672 x = simplify_shift_const (x, code, shift_mode, XEXP (x, 0),
8673 INTVAL (XEXP (x, 1)));
8675 /* If we were doing a LSHIFTRT in a wider mode than it was originally,
8676 turn off all the bits that the shift would have turned off. */
8677 if (orig_code == LSHIFTRT && result_mode != shift_mode)
8678 x = simplify_and_const_int (NULL_RTX, shift_mode, x,
8679 GET_MODE_MASK (result_mode) >> orig_count);
8681 /* Do the remainder of the processing in RESULT_MODE. */
8682 x = gen_lowpart_for_combine (result_mode, x);
8684 /* If COMPLEMENT_P is set, we have to complement X before doing the outer
8687 x = gen_unary (NOT, result_mode, result_mode, x);
8689 if (outer_op != NIL)
8691 if (GET_MODE_BITSIZE (result_mode) < HOST_BITS_PER_WIDE_INT)
8693 int width = GET_MODE_BITSIZE (result_mode);
8695 outer_const &= GET_MODE_MASK (result_mode);
8697 /* If this would be an entire word for the target, but is not for
8698 the host, then sign-extend on the host so that the number will
8699 look the same way on the host that it would on the target.
8701 For example, when building a 64 bit alpha hosted 32 bit sparc
8702 targeted compiler, then we want the 32 bit unsigned value -1 to be
8703 represented as a 64 bit value -1, and not as 0x00000000ffffffff.
8704 The later confuses the sparc backend. */
8706 if (BITS_PER_WORD < HOST_BITS_PER_WIDE_INT && BITS_PER_WORD == width
8707 && (outer_const & ((HOST_WIDE_INT) 1 << (width - 1))))
8708 outer_const |= ((HOST_WIDE_INT) (-1) << width);
8711 if (outer_op == AND)
8712 x = simplify_and_const_int (NULL_RTX, result_mode, x, outer_const);
8713 else if (outer_op == SET)
8714 /* This means that we have determined that the result is
8715 equivalent to a constant. This should be rare. */
8716 x = GEN_INT (outer_const);
8717 else if (GET_RTX_CLASS (outer_op) == '1')
8718 x = gen_unary (outer_op, result_mode, result_mode, x);
8720 x = gen_binary (outer_op, result_mode, x, GEN_INT (outer_const));
8726 /* Like recog, but we receive the address of a pointer to a new pattern.
8727 We try to match the rtx that the pointer points to.
8728 If that fails, we may try to modify or replace the pattern,
8729 storing the replacement into the same pointer object.
8731 Modifications include deletion or addition of CLOBBERs.
8733 PNOTES is a pointer to a location where any REG_UNUSED notes added for
8734 the CLOBBERs are placed.
8736 PADDED_SCRATCHES is set to the number of (clobber (scratch)) patterns
8739 The value is the final insn code from the pattern ultimately matched,
8743 recog_for_combine (pnewpat, insn, pnotes, padded_scratches)
8747 int *padded_scratches;
8749 register rtx pat = *pnewpat;
8750 int insn_code_number;
8751 int num_clobbers_to_add = 0;
8755 *padded_scratches = 0;
8757 /* If PAT is a PARALLEL, check to see if it contains the CLOBBER
8758 we use to indicate that something didn't match. If we find such a
8759 thing, force rejection. */
8760 if (GET_CODE (pat) == PARALLEL)
8761 for (i = XVECLEN (pat, 0) - 1; i >= 0; i--)
8762 if (GET_CODE (XVECEXP (pat, 0, i)) == CLOBBER
8763 && XEXP (XVECEXP (pat, 0, i), 0) == const0_rtx)
8766 /* Is the result of combination a valid instruction? */
8767 insn_code_number = recog (pat, insn, &num_clobbers_to_add);
8769 /* If it isn't, there is the possibility that we previously had an insn
8770 that clobbered some register as a side effect, but the combined
8771 insn doesn't need to do that. So try once more without the clobbers
8772 unless this represents an ASM insn. */
8774 if (insn_code_number < 0 && ! check_asm_operands (pat)
8775 && GET_CODE (pat) == PARALLEL)
8779 for (pos = 0, i = 0; i < XVECLEN (pat, 0); i++)
8780 if (GET_CODE (XVECEXP (pat, 0, i)) != CLOBBER)
8783 SUBST (XVECEXP (pat, 0, pos), XVECEXP (pat, 0, i));
8787 SUBST_INT (XVECLEN (pat, 0), pos);
8790 pat = XVECEXP (pat, 0, 0);
8792 insn_code_number = recog (pat, insn, &num_clobbers_to_add);
8795 /* If we had any clobbers to add, make a new pattern than contains
8796 them. Then check to make sure that all of them are dead. */
8797 if (num_clobbers_to_add)
8799 rtx newpat = gen_rtx (PARALLEL, VOIDmode,
8800 gen_rtvec (GET_CODE (pat) == PARALLEL
8801 ? XVECLEN (pat, 0) + num_clobbers_to_add
8802 : num_clobbers_to_add + 1));
8804 if (GET_CODE (pat) == PARALLEL)
8805 for (i = 0; i < XVECLEN (pat, 0); i++)
8806 XVECEXP (newpat, 0, i) = XVECEXP (pat, 0, i);
8808 XVECEXP (newpat, 0, 0) = pat;
8810 add_clobbers (newpat, insn_code_number);
8812 for (i = XVECLEN (newpat, 0) - num_clobbers_to_add;
8813 i < XVECLEN (newpat, 0); i++)
8815 if (GET_CODE (XEXP (XVECEXP (newpat, 0, i), 0)) == REG
8816 && ! reg_dead_at_p (XEXP (XVECEXP (newpat, 0, i), 0), insn))
8818 else if (GET_CODE (XEXP (XVECEXP (newpat, 0, i), 0)) == SCRATCH)
8819 (*padded_scratches)++;
8820 notes = gen_rtx (EXPR_LIST, REG_UNUSED,
8821 XEXP (XVECEXP (newpat, 0, i), 0), notes);
8829 return insn_code_number;
8832 /* Like gen_lowpart but for use by combine. In combine it is not possible
8833 to create any new pseudoregs. However, it is safe to create
8834 invalid memory addresses, because combine will try to recognize
8835 them and all they will do is make the combine attempt fail.
8837 If for some reason this cannot do its job, an rtx
8838 (clobber (const_int 0)) is returned.
8839 An insn containing that will not be recognized. */
8844 gen_lowpart_for_combine (mode, x)
8845 enum machine_mode mode;
8850 if (GET_MODE (x) == mode)
8853 /* We can only support MODE being wider than a word if X is a
8854 constant integer or has a mode the same size. */
8856 if (GET_MODE_SIZE (mode) > UNITS_PER_WORD
8857 && ! ((GET_MODE (x) == VOIDmode
8858 && (GET_CODE (x) == CONST_INT
8859 || GET_CODE (x) == CONST_DOUBLE))
8860 || GET_MODE_SIZE (GET_MODE (x)) == GET_MODE_SIZE (mode)))
8861 return gen_rtx (CLOBBER, GET_MODE (x), const0_rtx);
8863 /* X might be a paradoxical (subreg (mem)). In that case, gen_lowpart
8864 won't know what to do. So we will strip off the SUBREG here and
8865 process normally. */
8866 if (GET_CODE (x) == SUBREG && GET_CODE (SUBREG_REG (x)) == MEM)
8869 if (GET_MODE (x) == mode)
8873 result = gen_lowpart_common (mode, x);
8875 && GET_CODE (result) == SUBREG
8876 && GET_CODE (SUBREG_REG (result)) == REG
8877 && REGNO (SUBREG_REG (result)) >= FIRST_PSEUDO_REGISTER
8878 && (GET_MODE_SIZE (GET_MODE (result))
8879 != GET_MODE_SIZE (GET_MODE (SUBREG_REG (result)))))
8880 REG_CHANGES_SIZE (REGNO (SUBREG_REG (result))) = 1;
8885 if (GET_CODE (x) == MEM)
8887 register int offset = 0;
8890 /* Refuse to work on a volatile memory ref or one with a mode-dependent
8892 if (MEM_VOLATILE_P (x) || mode_dependent_address_p (XEXP (x, 0)))
8893 return gen_rtx (CLOBBER, GET_MODE (x), const0_rtx);
8895 /* If we want to refer to something bigger than the original memref,
8896 generate a perverse subreg instead. That will force a reload
8897 of the original memref X. */
8898 if (GET_MODE_SIZE (GET_MODE (x)) < GET_MODE_SIZE (mode))
8899 return gen_rtx (SUBREG, mode, x, 0);
8901 if (WORDS_BIG_ENDIAN)
8902 offset = (MAX (GET_MODE_SIZE (GET_MODE (x)), UNITS_PER_WORD)
8903 - MAX (GET_MODE_SIZE (mode), UNITS_PER_WORD));
8904 if (BYTES_BIG_ENDIAN)
8906 /* Adjust the address so that the address-after-the-data is
8908 offset -= (MIN (UNITS_PER_WORD, GET_MODE_SIZE (mode))
8909 - MIN (UNITS_PER_WORD, GET_MODE_SIZE (GET_MODE (x))));
8911 new = gen_rtx (MEM, mode, plus_constant (XEXP (x, 0), offset));
8912 RTX_UNCHANGING_P (new) = RTX_UNCHANGING_P (x);
8913 MEM_VOLATILE_P (new) = MEM_VOLATILE_P (x);
8914 MEM_IN_STRUCT_P (new) = MEM_IN_STRUCT_P (x);
8918 /* If X is a comparison operator, rewrite it in a new mode. This
8919 probably won't match, but may allow further simplifications. */
8920 else if (GET_RTX_CLASS (GET_CODE (x)) == '<')
8921 return gen_rtx_combine (GET_CODE (x), mode, XEXP (x, 0), XEXP (x, 1));
8923 /* If we couldn't simplify X any other way, just enclose it in a
8924 SUBREG. Normally, this SUBREG won't match, but some patterns may
8925 include an explicit SUBREG or we may simplify it further in combine. */
8930 if (WORDS_BIG_ENDIAN && GET_MODE_SIZE (GET_MODE (x)) > UNITS_PER_WORD)
8931 word = ((GET_MODE_SIZE (GET_MODE (x))
8932 - MAX (GET_MODE_SIZE (mode), UNITS_PER_WORD))
8934 return gen_rtx (SUBREG, mode, x, word);
8938 /* Make an rtx expression. This is a subset of gen_rtx and only supports
8939 expressions of 1, 2, or 3 operands, each of which are rtx expressions.
8941 If the identical expression was previously in the insn (in the undobuf),
8942 it will be returned. Only if it is not found will a new expression
8947 gen_rtx_combine VPROTO((enum rtx_code code, enum machine_mode mode, ...))
8951 enum machine_mode mode;
8964 code = va_arg (p, enum rtx_code);
8965 mode = va_arg (p, enum machine_mode);
8968 n_args = GET_RTX_LENGTH (code);
8969 fmt = GET_RTX_FORMAT (code);
8971 if (n_args == 0 || n_args > 3)
8974 /* Get each arg and verify that it is supposed to be an expression. */
8975 for (j = 0; j < n_args; j++)
8980 args[j] = va_arg (p, rtx);
8983 /* See if this is in undobuf. Be sure we don't use objects that came
8984 from another insn; this could produce circular rtl structures. */
8986 for (undo = undobuf.undos; undo != undobuf.previous_undos; undo = undo->next)
8988 && GET_CODE (undo->old_contents.r) == code
8989 && GET_MODE (undo->old_contents.r) == mode)
8991 for (j = 0; j < n_args; j++)
8992 if (XEXP (undo->old_contents.r, j) != args[j])
8996 return undo->old_contents.r;
8999 /* Otherwise make a new rtx. We know we have 1, 2, or 3 args.
9000 Use rtx_alloc instead of gen_rtx because it's faster on RISC. */
9001 rt = rtx_alloc (code);
9002 PUT_MODE (rt, mode);
9003 XEXP (rt, 0) = args[0];
9006 XEXP (rt, 1) = args[1];
9008 XEXP (rt, 2) = args[2];
9013 /* These routines make binary and unary operations by first seeing if they
9014 fold; if not, a new expression is allocated. */
9017 gen_binary (code, mode, op0, op1)
9019 enum machine_mode mode;
9025 if (GET_RTX_CLASS (code) == 'c'
9026 && (GET_CODE (op0) == CONST_INT
9027 || (CONSTANT_P (op0) && GET_CODE (op1) != CONST_INT)))
9028 tem = op0, op0 = op1, op1 = tem;
9030 if (GET_RTX_CLASS (code) == '<')
9032 enum machine_mode op_mode = GET_MODE (op0);
9034 /* Strip the COMPARE from (REL_OP (compare X Y) 0) to get
9035 just (REL_OP X Y). */
9036 if (GET_CODE (op0) == COMPARE && op1 == const0_rtx)
9038 op1 = XEXP (op0, 1);
9039 op0 = XEXP (op0, 0);
9040 op_mode = GET_MODE (op0);
9043 if (op_mode == VOIDmode)
9044 op_mode = GET_MODE (op1);
9045 result = simplify_relational_operation (code, op_mode, op0, op1);
9048 result = simplify_binary_operation (code, mode, op0, op1);
9053 /* Put complex operands first and constants second. */
9054 if (GET_RTX_CLASS (code) == 'c'
9055 && ((CONSTANT_P (op0) && GET_CODE (op1) != CONST_INT)
9056 || (GET_RTX_CLASS (GET_CODE (op0)) == 'o'
9057 && GET_RTX_CLASS (GET_CODE (op1)) != 'o')
9058 || (GET_CODE (op0) == SUBREG
9059 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (op0))) == 'o'
9060 && GET_RTX_CLASS (GET_CODE (op1)) != 'o')))
9061 return gen_rtx_combine (code, mode, op1, op0);
9063 return gen_rtx_combine (code, mode, op0, op1);
9067 gen_unary (code, mode, op0_mode, op0)
9069 enum machine_mode mode, op0_mode;
9072 rtx result = simplify_unary_operation (code, mode, op0, op0_mode);
9077 return gen_rtx_combine (code, mode, op0);
9080 /* Simplify a comparison between *POP0 and *POP1 where CODE is the
9081 comparison code that will be tested.
9083 The result is a possibly different comparison code to use. *POP0 and
9084 *POP1 may be updated.
9086 It is possible that we might detect that a comparison is either always
9087 true or always false. However, we do not perform general constant
9088 folding in combine, so this knowledge isn't useful. Such tautologies
9089 should have been detected earlier. Hence we ignore all such cases. */
9091 static enum rtx_code
9092 simplify_comparison (code, pop0, pop1)
9101 enum machine_mode mode, tmode;
9103 /* Try a few ways of applying the same transformation to both operands. */
9106 #ifndef WORD_REGISTER_OPERATIONS
9107 /* The test below this one won't handle SIGN_EXTENDs on these machines,
9108 so check specially. */
9109 if (code != GTU && code != GEU && code != LTU && code != LEU
9110 && GET_CODE (op0) == ASHIFTRT && GET_CODE (op1) == ASHIFTRT
9111 && GET_CODE (XEXP (op0, 0)) == ASHIFT
9112 && GET_CODE (XEXP (op1, 0)) == ASHIFT
9113 && GET_CODE (XEXP (XEXP (op0, 0), 0)) == SUBREG
9114 && GET_CODE (XEXP (XEXP (op1, 0), 0)) == SUBREG
9115 && (GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0)))
9116 == GET_MODE (SUBREG_REG (XEXP (XEXP (op1, 0), 0))))
9117 && GET_CODE (XEXP (op0, 1)) == CONST_INT
9118 && GET_CODE (XEXP (op1, 1)) == CONST_INT
9119 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
9120 && GET_CODE (XEXP (XEXP (op1, 0), 1)) == CONST_INT
9121 && INTVAL (XEXP (op0, 1)) == INTVAL (XEXP (op1, 1))
9122 && INTVAL (XEXP (op0, 1)) == INTVAL (XEXP (XEXP (op0, 0), 1))
9123 && INTVAL (XEXP (op0, 1)) == INTVAL (XEXP (XEXP (op1, 0), 1))
9124 && (INTVAL (XEXP (op0, 1))
9125 == (GET_MODE_BITSIZE (GET_MODE (op0))
9127 (GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0))))))))
9129 op0 = SUBREG_REG (XEXP (XEXP (op0, 0), 0));
9130 op1 = SUBREG_REG (XEXP (XEXP (op1, 0), 0));
9134 /* If both operands are the same constant shift, see if we can ignore the
9135 shift. We can if the shift is a rotate or if the bits shifted out of
9136 this shift are known to be zero for both inputs and if the type of
9137 comparison is compatible with the shift. */
9138 if (GET_CODE (op0) == GET_CODE (op1)
9139 && GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
9140 && ((GET_CODE (op0) == ROTATE && (code == NE || code == EQ))
9141 || ((GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFT)
9142 && (code != GT && code != LT && code != GE && code != LE))
9143 || (GET_CODE (op0) == ASHIFTRT
9144 && (code != GTU && code != LTU
9145 && code != GEU && code != GEU)))
9146 && GET_CODE (XEXP (op0, 1)) == CONST_INT
9147 && INTVAL (XEXP (op0, 1)) >= 0
9148 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT
9149 && XEXP (op0, 1) == XEXP (op1, 1))
9151 enum machine_mode mode = GET_MODE (op0);
9152 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
9153 int shift_count = INTVAL (XEXP (op0, 1));
9155 if (GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFTRT)
9156 mask &= (mask >> shift_count) << shift_count;
9157 else if (GET_CODE (op0) == ASHIFT)
9158 mask = (mask & (mask << shift_count)) >> shift_count;
9160 if ((nonzero_bits (XEXP (op0, 0), mode) & ~ mask) == 0
9161 && (nonzero_bits (XEXP (op1, 0), mode) & ~ mask) == 0)
9162 op0 = XEXP (op0, 0), op1 = XEXP (op1, 0);
9167 /* If both operands are AND's of a paradoxical SUBREG by constant, the
9168 SUBREGs are of the same mode, and, in both cases, the AND would
9169 be redundant if the comparison was done in the narrower mode,
9170 do the comparison in the narrower mode (e.g., we are AND'ing with 1
9171 and the operand's possibly nonzero bits are 0xffffff01; in that case
9172 if we only care about QImode, we don't need the AND). This case
9173 occurs if the output mode of an scc insn is not SImode and
9174 STORE_FLAG_VALUE == 1 (e.g., the 386).
9176 Similarly, check for a case where the AND's are ZERO_EXTEND
9177 operations from some narrower mode even though a SUBREG is not
9180 else if (GET_CODE (op0) == AND && GET_CODE (op1) == AND
9181 && GET_CODE (XEXP (op0, 1)) == CONST_INT
9182 && GET_CODE (XEXP (op1, 1)) == CONST_INT)
9184 rtx inner_op0 = XEXP (op0, 0);
9185 rtx inner_op1 = XEXP (op1, 0);
9186 HOST_WIDE_INT c0 = INTVAL (XEXP (op0, 1));
9187 HOST_WIDE_INT c1 = INTVAL (XEXP (op1, 1));
9190 if (GET_CODE (inner_op0) == SUBREG && GET_CODE (inner_op1) == SUBREG
9191 && (GET_MODE_SIZE (GET_MODE (inner_op0))
9192 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (inner_op0))))
9193 && (GET_MODE (SUBREG_REG (inner_op0))
9194 == GET_MODE (SUBREG_REG (inner_op1)))
9195 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0)))
9196 <= HOST_BITS_PER_WIDE_INT)
9197 && (0 == ((~c0) & nonzero_bits (SUBREG_REG (inner_op0),
9198 GET_MODE (SUBREG_REG (op0)))))
9199 && (0 == ((~c1) & nonzero_bits (SUBREG_REG (inner_op1),
9200 GET_MODE (SUBREG_REG (inner_op1))))))
9202 op0 = SUBREG_REG (inner_op0);
9203 op1 = SUBREG_REG (inner_op1);
9205 /* The resulting comparison is always unsigned since we masked
9206 off the original sign bit. */
9207 code = unsigned_condition (code);
9213 for (tmode = GET_CLASS_NARROWEST_MODE
9214 (GET_MODE_CLASS (GET_MODE (op0)));
9215 tmode != GET_MODE (op0); tmode = GET_MODE_WIDER_MODE (tmode))
9216 if (c0 == GET_MODE_MASK (tmode))
9218 op0 = gen_lowpart_for_combine (tmode, inner_op0);
9219 op1 = gen_lowpart_for_combine (tmode, inner_op1);
9220 code = unsigned_condition (code);
9229 /* If both operands are NOT, we can strip off the outer operation
9230 and adjust the comparison code for swapped operands; similarly for
9231 NEG, except that this must be an equality comparison. */
9232 else if ((GET_CODE (op0) == NOT && GET_CODE (op1) == NOT)
9233 || (GET_CODE (op0) == NEG && GET_CODE (op1) == NEG
9234 && (code == EQ || code == NE)))
9235 op0 = XEXP (op0, 0), op1 = XEXP (op1, 0), code = swap_condition (code);
9241 /* If the first operand is a constant, swap the operands and adjust the
9242 comparison code appropriately, but don't do this if the second operand
9243 is already a constant integer. */
9244 if (CONSTANT_P (op0) && GET_CODE (op1) != CONST_INT)
9246 tem = op0, op0 = op1, op1 = tem;
9247 code = swap_condition (code);
9250 /* We now enter a loop during which we will try to simplify the comparison.
9251 For the most part, we only are concerned with comparisons with zero,
9252 but some things may really be comparisons with zero but not start
9253 out looking that way. */
9255 while (GET_CODE (op1) == CONST_INT)
9257 enum machine_mode mode = GET_MODE (op0);
9258 int mode_width = GET_MODE_BITSIZE (mode);
9259 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
9260 int equality_comparison_p;
9261 int sign_bit_comparison_p;
9262 int unsigned_comparison_p;
9263 HOST_WIDE_INT const_op;
9265 /* We only want to handle integral modes. This catches VOIDmode,
9266 CCmode, and the floating-point modes. An exception is that we
9267 can handle VOIDmode if OP0 is a COMPARE or a comparison
9270 if (GET_MODE_CLASS (mode) != MODE_INT
9271 && ! (mode == VOIDmode
9272 && (GET_CODE (op0) == COMPARE
9273 || GET_RTX_CLASS (GET_CODE (op0)) == '<')))
9276 /* Get the constant we are comparing against and turn off all bits
9277 not on in our mode. */
9278 const_op = INTVAL (op1);
9279 if (mode_width <= HOST_BITS_PER_WIDE_INT)
9282 /* If we are comparing against a constant power of two and the value
9283 being compared can only have that single bit nonzero (e.g., it was
9284 `and'ed with that bit), we can replace this with a comparison
9287 && (code == EQ || code == NE || code == GE || code == GEU
9288 || code == LT || code == LTU)
9289 && mode_width <= HOST_BITS_PER_WIDE_INT
9290 && exact_log2 (const_op) >= 0
9291 && nonzero_bits (op0, mode) == const_op)
9293 code = (code == EQ || code == GE || code == GEU ? NE : EQ);
9294 op1 = const0_rtx, const_op = 0;
9297 /* Similarly, if we are comparing a value known to be either -1 or
9298 0 with -1, change it to the opposite comparison against zero. */
9301 && (code == EQ || code == NE || code == GT || code == LE
9302 || code == GEU || code == LTU)
9303 && num_sign_bit_copies (op0, mode) == mode_width)
9305 code = (code == EQ || code == LE || code == GEU ? NE : EQ);
9306 op1 = const0_rtx, const_op = 0;
9309 /* Do some canonicalizations based on the comparison code. We prefer
9310 comparisons against zero and then prefer equality comparisons.
9311 If we can reduce the size of a constant, we will do that too. */
9316 /* < C is equivalent to <= (C - 1) */
9320 op1 = GEN_INT (const_op);
9322 /* ... fall through to LE case below. */
9328 /* <= C is equivalent to < (C + 1); we do this for C < 0 */
9332 op1 = GEN_INT (const_op);
9336 /* If we are doing a <= 0 comparison on a value known to have
9337 a zero sign bit, we can replace this with == 0. */
9338 else if (const_op == 0
9339 && mode_width <= HOST_BITS_PER_WIDE_INT
9340 && (nonzero_bits (op0, mode)
9341 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)
9346 /* >= C is equivalent to > (C - 1). */
9350 op1 = GEN_INT (const_op);
9352 /* ... fall through to GT below. */
9358 /* > C is equivalent to >= (C + 1); we do this for C < 0*/
9362 op1 = GEN_INT (const_op);
9366 /* If we are doing a > 0 comparison on a value known to have
9367 a zero sign bit, we can replace this with != 0. */
9368 else if (const_op == 0
9369 && mode_width <= HOST_BITS_PER_WIDE_INT
9370 && (nonzero_bits (op0, mode)
9371 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)
9376 /* < C is equivalent to <= (C - 1). */
9380 op1 = GEN_INT (const_op);
9382 /* ... fall through ... */
9385 /* (unsigned) < 0x80000000 is equivalent to >= 0. */
9386 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
9387 && (const_op == (HOST_WIDE_INT) 1 << (mode_width - 1)))
9389 const_op = 0, op1 = const0_rtx;
9397 /* unsigned <= 0 is equivalent to == 0 */
9401 /* (unsigned) <= 0x7fffffff is equivalent to >= 0. */
9402 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
9403 && (const_op == ((HOST_WIDE_INT) 1 << (mode_width - 1)) - 1))
9405 const_op = 0, op1 = const0_rtx;
9411 /* >= C is equivalent to < (C - 1). */
9415 op1 = GEN_INT (const_op);
9417 /* ... fall through ... */
9420 /* (unsigned) >= 0x80000000 is equivalent to < 0. */
9421 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
9422 && (const_op == (HOST_WIDE_INT) 1 << (mode_width - 1)))
9424 const_op = 0, op1 = const0_rtx;
9432 /* unsigned > 0 is equivalent to != 0 */
9436 /* (unsigned) > 0x7fffffff is equivalent to < 0. */
9437 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
9438 && (const_op == ((HOST_WIDE_INT) 1 << (mode_width - 1)) - 1))
9440 const_op = 0, op1 = const0_rtx;
9446 /* Compute some predicates to simplify code below. */
9448 equality_comparison_p = (code == EQ || code == NE);
9449 sign_bit_comparison_p = ((code == LT || code == GE) && const_op == 0);
9450 unsigned_comparison_p = (code == LTU || code == LEU || code == GTU
9453 /* If this is a sign bit comparison and we can do arithmetic in
9454 MODE, say that we will only be needing the sign bit of OP0. */
9455 if (sign_bit_comparison_p
9456 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
9457 op0 = force_to_mode (op0, mode,
9459 << (GET_MODE_BITSIZE (mode) - 1)),
9462 /* Now try cases based on the opcode of OP0. If none of the cases
9463 does a "continue", we exit this loop immediately after the
9466 switch (GET_CODE (op0))
9469 /* If we are extracting a single bit from a variable position in
9470 a constant that has only a single bit set and are comparing it
9471 with zero, we can convert this into an equality comparison
9472 between the position and the location of the single bit. */
9474 if (GET_CODE (XEXP (op0, 0)) == CONST_INT
9475 && XEXP (op0, 1) == const1_rtx
9476 && equality_comparison_p && const_op == 0
9477 && (i = exact_log2 (INTVAL (XEXP (op0, 0)))) >= 0)
9479 if (BITS_BIG_ENDIAN)
9481 i = (GET_MODE_BITSIZE
9482 (insn_operand_mode[(int) CODE_FOR_extzv][1]) - 1 - i);
9484 i = BITS_PER_WORD - 1 - i;
9487 op0 = XEXP (op0, 2);
9491 /* Result is nonzero iff shift count is equal to I. */
9492 code = reverse_condition (code);
9496 /* ... fall through ... */
9499 tem = expand_compound_operation (op0);
9508 /* If testing for equality, we can take the NOT of the constant. */
9509 if (equality_comparison_p
9510 && (tem = simplify_unary_operation (NOT, mode, op1, mode)) != 0)
9512 op0 = XEXP (op0, 0);
9517 /* If just looking at the sign bit, reverse the sense of the
9519 if (sign_bit_comparison_p)
9521 op0 = XEXP (op0, 0);
9522 code = (code == GE ? LT : GE);
9528 /* If testing for equality, we can take the NEG of the constant. */
9529 if (equality_comparison_p
9530 && (tem = simplify_unary_operation (NEG, mode, op1, mode)) != 0)
9532 op0 = XEXP (op0, 0);
9537 /* The remaining cases only apply to comparisons with zero. */
9541 /* When X is ABS or is known positive,
9542 (neg X) is < 0 if and only if X != 0. */
9544 if (sign_bit_comparison_p
9545 && (GET_CODE (XEXP (op0, 0)) == ABS
9546 || (mode_width <= HOST_BITS_PER_WIDE_INT
9547 && (nonzero_bits (XEXP (op0, 0), mode)
9548 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)))
9550 op0 = XEXP (op0, 0);
9551 code = (code == LT ? NE : EQ);
9555 /* If we have NEG of something whose two high-order bits are the
9556 same, we know that "(-a) < 0" is equivalent to "a > 0". */
9557 if (num_sign_bit_copies (op0, mode) >= 2)
9559 op0 = XEXP (op0, 0);
9560 code = swap_condition (code);
9566 /* If we are testing equality and our count is a constant, we
9567 can perform the inverse operation on our RHS. */
9568 if (equality_comparison_p && GET_CODE (XEXP (op0, 1)) == CONST_INT
9569 && (tem = simplify_binary_operation (ROTATERT, mode,
9570 op1, XEXP (op0, 1))) != 0)
9572 op0 = XEXP (op0, 0);
9577 /* If we are doing a < 0 or >= 0 comparison, it means we are testing
9578 a particular bit. Convert it to an AND of a constant of that
9579 bit. This will be converted into a ZERO_EXTRACT. */
9580 if (const_op == 0 && sign_bit_comparison_p
9581 && GET_CODE (XEXP (op0, 1)) == CONST_INT
9582 && mode_width <= HOST_BITS_PER_WIDE_INT)
9584 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
9587 - INTVAL (XEXP (op0, 1)))));
9588 code = (code == LT ? NE : EQ);
9592 /* ... fall through ... */
9595 /* ABS is ignorable inside an equality comparison with zero. */
9596 if (const_op == 0 && equality_comparison_p)
9598 op0 = XEXP (op0, 0);
9605 /* Can simplify (compare (zero/sign_extend FOO) CONST)
9606 to (compare FOO CONST) if CONST fits in FOO's mode and we
9607 are either testing inequality or have an unsigned comparison
9608 with ZERO_EXTEND or a signed comparison with SIGN_EXTEND. */
9609 if (! unsigned_comparison_p
9610 && (GET_MODE_BITSIZE (GET_MODE (XEXP (op0, 0)))
9611 <= HOST_BITS_PER_WIDE_INT)
9612 && ((unsigned HOST_WIDE_INT) const_op
9613 < (((HOST_WIDE_INT) 1
9614 << (GET_MODE_BITSIZE (GET_MODE (XEXP (op0, 0))) - 1)))))
9616 op0 = XEXP (op0, 0);
9622 /* Check for the case where we are comparing A - C1 with C2,
9623 both constants are smaller than 1/2 the maximum positive
9624 value in MODE, and the comparison is equality or unsigned.
9625 In that case, if A is either zero-extended to MODE or has
9626 sufficient sign bits so that the high-order bit in MODE
9627 is a copy of the sign in the inner mode, we can prove that it is
9628 safe to do the operation in the wider mode. This simplifies
9629 many range checks. */
9631 if (mode_width <= HOST_BITS_PER_WIDE_INT
9632 && subreg_lowpart_p (op0)
9633 && GET_CODE (SUBREG_REG (op0)) == PLUS
9634 && GET_CODE (XEXP (SUBREG_REG (op0), 1)) == CONST_INT
9635 && INTVAL (XEXP (SUBREG_REG (op0), 1)) < 0
9636 && (- INTVAL (XEXP (SUBREG_REG (op0), 1))
9637 < GET_MODE_MASK (mode) / 2)
9638 && (unsigned HOST_WIDE_INT) const_op < GET_MODE_MASK (mode) / 2
9639 && (0 == (nonzero_bits (XEXP (SUBREG_REG (op0), 0),
9640 GET_MODE (SUBREG_REG (op0)))
9641 & ~ GET_MODE_MASK (mode))
9642 || (num_sign_bit_copies (XEXP (SUBREG_REG (op0), 0),
9643 GET_MODE (SUBREG_REG (op0)))
9644 > (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0)))
9645 - GET_MODE_BITSIZE (mode)))))
9647 op0 = SUBREG_REG (op0);
9651 /* If the inner mode is narrower and we are extracting the low part,
9652 we can treat the SUBREG as if it were a ZERO_EXTEND. */
9653 if (subreg_lowpart_p (op0)
9654 && GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0))) < mode_width)
9655 /* Fall through */ ;
9659 /* ... fall through ... */
9662 if ((unsigned_comparison_p || equality_comparison_p)
9663 && (GET_MODE_BITSIZE (GET_MODE (XEXP (op0, 0)))
9664 <= HOST_BITS_PER_WIDE_INT)
9665 && ((unsigned HOST_WIDE_INT) const_op
9666 < GET_MODE_MASK (GET_MODE (XEXP (op0, 0)))))
9668 op0 = XEXP (op0, 0);
9674 /* (eq (plus X A) B) -> (eq X (minus B A)). We can only do
9675 this for equality comparisons due to pathological cases involving
9677 if (equality_comparison_p
9678 && 0 != (tem = simplify_binary_operation (MINUS, mode,
9679 op1, XEXP (op0, 1))))
9681 op0 = XEXP (op0, 0);
9686 /* (plus (abs X) (const_int -1)) is < 0 if and only if X == 0. */
9687 if (const_op == 0 && XEXP (op0, 1) == constm1_rtx
9688 && GET_CODE (XEXP (op0, 0)) == ABS && sign_bit_comparison_p)
9690 op0 = XEXP (XEXP (op0, 0), 0);
9691 code = (code == LT ? EQ : NE);
9697 /* (eq (minus A B) C) -> (eq A (plus B C)) or
9698 (eq B (minus A C)), whichever simplifies. We can only do
9699 this for equality comparisons due to pathological cases involving
9701 if (equality_comparison_p
9702 && 0 != (tem = simplify_binary_operation (PLUS, mode,
9703 XEXP (op0, 1), op1)))
9705 op0 = XEXP (op0, 0);
9710 if (equality_comparison_p
9711 && 0 != (tem = simplify_binary_operation (MINUS, mode,
9712 XEXP (op0, 0), op1)))
9714 op0 = XEXP (op0, 1);
9719 /* The sign bit of (minus (ashiftrt X C) X), where C is the number
9720 of bits in X minus 1, is one iff X > 0. */
9721 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == ASHIFTRT
9722 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
9723 && INTVAL (XEXP (XEXP (op0, 0), 1)) == mode_width - 1
9724 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
9726 op0 = XEXP (op0, 1);
9727 code = (code == GE ? LE : GT);
9733 /* (eq (xor A B) C) -> (eq A (xor B C)). This is a simplification
9734 if C is zero or B is a constant. */
9735 if (equality_comparison_p
9736 && 0 != (tem = simplify_binary_operation (XOR, mode,
9737 XEXP (op0, 1), op1)))
9739 op0 = XEXP (op0, 0);
9746 case LT: case LTU: case LE: case LEU:
9747 case GT: case GTU: case GE: case GEU:
9748 /* We can't do anything if OP0 is a condition code value, rather
9749 than an actual data value. */
9752 || XEXP (op0, 0) == cc0_rtx
9754 || GET_MODE_CLASS (GET_MODE (XEXP (op0, 0))) == MODE_CC)
9757 /* Get the two operands being compared. */
9758 if (GET_CODE (XEXP (op0, 0)) == COMPARE)
9759 tem = XEXP (XEXP (op0, 0), 0), tem1 = XEXP (XEXP (op0, 0), 1);
9761 tem = XEXP (op0, 0), tem1 = XEXP (op0, 1);
9763 /* Check for the cases where we simply want the result of the
9764 earlier test or the opposite of that result. */
9766 || (code == EQ && reversible_comparison_p (op0))
9767 || (GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
9768 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
9769 && (STORE_FLAG_VALUE
9770 & (((HOST_WIDE_INT) 1
9771 << (GET_MODE_BITSIZE (GET_MODE (op0)) - 1))))
9773 || (code == GE && reversible_comparison_p (op0)))))
9775 code = (code == LT || code == NE
9776 ? GET_CODE (op0) : reverse_condition (GET_CODE (op0)));
9777 op0 = tem, op1 = tem1;
9783 /* The sign bit of (ior (plus X (const_int -1)) X) is non-zero
9785 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == PLUS
9786 && XEXP (XEXP (op0, 0), 1) == constm1_rtx
9787 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
9789 op0 = XEXP (op0, 1);
9790 code = (code == GE ? GT : LE);
9796 /* Convert (and (xshift 1 X) Y) to (and (lshiftrt Y X) 1). This
9797 will be converted to a ZERO_EXTRACT later. */
9798 if (const_op == 0 && equality_comparison_p
9799 && GET_CODE (XEXP (op0, 0)) == ASHIFT
9800 && XEXP (XEXP (op0, 0), 0) == const1_rtx)
9802 op0 = simplify_and_const_int
9803 (op0, mode, gen_rtx_combine (LSHIFTRT, mode,
9805 XEXP (XEXP (op0, 0), 1)),
9810 /* If we are comparing (and (lshiftrt X C1) C2) for equality with
9811 zero and X is a comparison and C1 and C2 describe only bits set
9812 in STORE_FLAG_VALUE, we can compare with X. */
9813 if (const_op == 0 && equality_comparison_p
9814 && mode_width <= HOST_BITS_PER_WIDE_INT
9815 && GET_CODE (XEXP (op0, 1)) == CONST_INT
9816 && GET_CODE (XEXP (op0, 0)) == LSHIFTRT
9817 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
9818 && INTVAL (XEXP (XEXP (op0, 0), 1)) >= 0
9819 && INTVAL (XEXP (XEXP (op0, 0), 1)) < HOST_BITS_PER_WIDE_INT)
9821 mask = ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
9822 << INTVAL (XEXP (XEXP (op0, 0), 1)));
9823 if ((~ STORE_FLAG_VALUE & mask) == 0
9824 && (GET_RTX_CLASS (GET_CODE (XEXP (XEXP (op0, 0), 0))) == '<'
9825 || ((tem = get_last_value (XEXP (XEXP (op0, 0), 0))) != 0
9826 && GET_RTX_CLASS (GET_CODE (tem)) == '<')))
9828 op0 = XEXP (XEXP (op0, 0), 0);
9833 /* If we are doing an equality comparison of an AND of a bit equal
9834 to the sign bit, replace this with a LT or GE comparison of
9835 the underlying value. */
9836 if (equality_comparison_p
9838 && GET_CODE (XEXP (op0, 1)) == CONST_INT
9839 && mode_width <= HOST_BITS_PER_WIDE_INT
9840 && ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
9841 == (HOST_WIDE_INT) 1 << (mode_width - 1)))
9843 op0 = XEXP (op0, 0);
9844 code = (code == EQ ? GE : LT);
9848 /* If this AND operation is really a ZERO_EXTEND from a narrower
9849 mode, the constant fits within that mode, and this is either an
9850 equality or unsigned comparison, try to do this comparison in
9851 the narrower mode. */
9852 if ((equality_comparison_p || unsigned_comparison_p)
9853 && GET_CODE (XEXP (op0, 1)) == CONST_INT
9854 && (i = exact_log2 ((INTVAL (XEXP (op0, 1))
9855 & GET_MODE_MASK (mode))
9857 && const_op >> i == 0
9858 && (tmode = mode_for_size (i, MODE_INT, 1)) != BLKmode)
9860 op0 = gen_lowpart_for_combine (tmode, XEXP (op0, 0));
9866 /* If we have (compare (ashift FOO N) (const_int C)) and
9867 the high order N bits of FOO (N+1 if an inequality comparison)
9868 are known to be zero, we can do this by comparing FOO with C
9869 shifted right N bits so long as the low-order N bits of C are
9871 if (GET_CODE (XEXP (op0, 1)) == CONST_INT
9872 && INTVAL (XEXP (op0, 1)) >= 0
9873 && ((INTVAL (XEXP (op0, 1)) + ! equality_comparison_p)
9874 < HOST_BITS_PER_WIDE_INT)
9876 & (((HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1))) - 1)) == 0)
9877 && mode_width <= HOST_BITS_PER_WIDE_INT
9878 && (nonzero_bits (XEXP (op0, 0), mode)
9879 & ~ (mask >> (INTVAL (XEXP (op0, 1))
9880 + ! equality_comparison_p))) == 0)
9882 const_op >>= INTVAL (XEXP (op0, 1));
9883 op1 = GEN_INT (const_op);
9884 op0 = XEXP (op0, 0);
9888 /* If we are doing a sign bit comparison, it means we are testing
9889 a particular bit. Convert it to the appropriate AND. */
9890 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 1)) == CONST_INT
9891 && mode_width <= HOST_BITS_PER_WIDE_INT)
9893 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
9896 - INTVAL (XEXP (op0, 1)))));
9897 code = (code == LT ? NE : EQ);
9901 /* If this an equality comparison with zero and we are shifting
9902 the low bit to the sign bit, we can convert this to an AND of the
9904 if (const_op == 0 && equality_comparison_p
9905 && GET_CODE (XEXP (op0, 1)) == CONST_INT
9906 && INTVAL (XEXP (op0, 1)) == mode_width - 1)
9908 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
9915 /* If this is an equality comparison with zero, we can do this
9916 as a logical shift, which might be much simpler. */
9917 if (equality_comparison_p && const_op == 0
9918 && GET_CODE (XEXP (op0, 1)) == CONST_INT)
9920 op0 = simplify_shift_const (NULL_RTX, LSHIFTRT, mode,
9922 INTVAL (XEXP (op0, 1)));
9926 /* If OP0 is a sign extension and CODE is not an unsigned comparison,
9927 do the comparison in a narrower mode. */
9928 if (! unsigned_comparison_p
9929 && GET_CODE (XEXP (op0, 1)) == CONST_INT
9930 && GET_CODE (XEXP (op0, 0)) == ASHIFT
9931 && XEXP (op0, 1) == XEXP (XEXP (op0, 0), 1)
9932 && (tmode = mode_for_size (mode_width - INTVAL (XEXP (op0, 1)),
9933 MODE_INT, 1)) != BLKmode
9934 && ((unsigned HOST_WIDE_INT) const_op <= GET_MODE_MASK (tmode)
9935 || ((unsigned HOST_WIDE_INT) - const_op
9936 <= GET_MODE_MASK (tmode))))
9938 op0 = gen_lowpart_for_combine (tmode, XEXP (XEXP (op0, 0), 0));
9942 /* ... fall through ... */
9944 /* If we have (compare (xshiftrt FOO N) (const_int C)) and
9945 the low order N bits of FOO are known to be zero, we can do this
9946 by comparing FOO with C shifted left N bits so long as no
9948 if (GET_CODE (XEXP (op0, 1)) == CONST_INT
9949 && INTVAL (XEXP (op0, 1)) >= 0
9950 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT
9951 && mode_width <= HOST_BITS_PER_WIDE_INT
9952 && (nonzero_bits (XEXP (op0, 0), mode)
9953 & (((HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1))) - 1)) == 0
9955 || (floor_log2 (const_op) + INTVAL (XEXP (op0, 1))
9958 const_op <<= INTVAL (XEXP (op0, 1));
9959 op1 = GEN_INT (const_op);
9960 op0 = XEXP (op0, 0);
9964 /* If we are using this shift to extract just the sign bit, we
9965 can replace this with an LT or GE comparison. */
9967 && (equality_comparison_p || sign_bit_comparison_p)
9968 && GET_CODE (XEXP (op0, 1)) == CONST_INT
9969 && INTVAL (XEXP (op0, 1)) == mode_width - 1)
9971 op0 = XEXP (op0, 0);
9972 code = (code == NE || code == GT ? LT : GE);
9981 /* Now make any compound operations involved in this comparison. Then,
9982 check for an outmost SUBREG on OP0 that isn't doing anything or is
9983 paradoxical. The latter case can only occur when it is known that the
9984 "extra" bits will be zero. Therefore, it is safe to remove the SUBREG.
9985 We can never remove a SUBREG for a non-equality comparison because the
9986 sign bit is in a different place in the underlying object. */
9988 op0 = make_compound_operation (op0, op1 == const0_rtx ? COMPARE : SET);
9989 op1 = make_compound_operation (op1, SET);
9991 if (GET_CODE (op0) == SUBREG && subreg_lowpart_p (op0)
9992 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
9993 && (code == NE || code == EQ)
9994 && ((GET_MODE_SIZE (GET_MODE (op0))
9995 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (op0))))))
9997 op0 = SUBREG_REG (op0);
9998 op1 = gen_lowpart_for_combine (GET_MODE (op0), op1);
10001 else if (GET_CODE (op0) == SUBREG && subreg_lowpart_p (op0)
10002 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
10003 && (code == NE || code == EQ)
10004 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0)))
10005 <= HOST_BITS_PER_WIDE_INT)
10006 && (nonzero_bits (SUBREG_REG (op0), GET_MODE (SUBREG_REG (op0)))
10007 & ~ GET_MODE_MASK (GET_MODE (op0))) == 0
10008 && (tem = gen_lowpart_for_combine (GET_MODE (SUBREG_REG (op0)),
10010 (nonzero_bits (tem, GET_MODE (SUBREG_REG (op0)))
10011 & ~ GET_MODE_MASK (GET_MODE (op0))) == 0))
10012 op0 = SUBREG_REG (op0), op1 = tem;
10014 /* We now do the opposite procedure: Some machines don't have compare
10015 insns in all modes. If OP0's mode is an integer mode smaller than a
10016 word and we can't do a compare in that mode, see if there is a larger
10017 mode for which we can do the compare. There are a number of cases in
10018 which we can use the wider mode. */
10020 mode = GET_MODE (op0);
10021 if (mode != VOIDmode && GET_MODE_CLASS (mode) == MODE_INT
10022 && GET_MODE_SIZE (mode) < UNITS_PER_WORD
10023 && cmp_optab->handlers[(int) mode].insn_code == CODE_FOR_nothing)
10024 for (tmode = GET_MODE_WIDER_MODE (mode);
10026 && GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT);
10027 tmode = GET_MODE_WIDER_MODE (tmode))
10028 if (cmp_optab->handlers[(int) tmode].insn_code != CODE_FOR_nothing)
10030 /* If the only nonzero bits in OP0 and OP1 are those in the
10031 narrower mode and this is an equality or unsigned comparison,
10032 we can use the wider mode. Similarly for sign-extended
10033 values, in which case it is true for all comparisons. */
10034 if (((code == EQ || code == NE
10035 || code == GEU || code == GTU || code == LEU || code == LTU)
10036 && (nonzero_bits (op0, tmode) & ~ GET_MODE_MASK (mode)) == 0
10037 && (nonzero_bits (op1, tmode) & ~ GET_MODE_MASK (mode)) == 0)
10038 || ((num_sign_bit_copies (op0, tmode)
10039 > GET_MODE_BITSIZE (tmode) - GET_MODE_BITSIZE (mode))
10040 && (num_sign_bit_copies (op1, tmode)
10041 > GET_MODE_BITSIZE (tmode) - GET_MODE_BITSIZE (mode))))
10043 op0 = gen_lowpart_for_combine (tmode, op0);
10044 op1 = gen_lowpart_for_combine (tmode, op1);
10048 /* If this is a test for negative, we can make an explicit
10049 test of the sign bit. */
10051 if (op1 == const0_rtx && (code == LT || code == GE)
10052 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
10054 op0 = gen_binary (AND, tmode,
10055 gen_lowpart_for_combine (tmode, op0),
10056 GEN_INT ((HOST_WIDE_INT) 1
10057 << (GET_MODE_BITSIZE (mode) - 1)));
10058 code = (code == LT) ? NE : EQ;
10063 #ifdef CANONICALIZE_COMPARISON
10064 /* If this machine only supports a subset of valid comparisons, see if we
10065 can convert an unsupported one into a supported one. */
10066 CANONICALIZE_COMPARISON (code, op0, op1);
10075 /* Return 1 if we know that X, a comparison operation, is not operating
10076 on a floating-point value or is EQ or NE, meaning that we can safely
10080 reversible_comparison_p (x)
10083 if (TARGET_FLOAT_FORMAT != IEEE_FLOAT_FORMAT
10085 || GET_CODE (x) == NE || GET_CODE (x) == EQ)
10088 switch (GET_MODE_CLASS (GET_MODE (XEXP (x, 0))))
10091 case MODE_PARTIAL_INT:
10092 case MODE_COMPLEX_INT:
10096 /* If the mode of the condition codes tells us that this is safe,
10097 we need look no further. */
10098 if (REVERSIBLE_CC_MODE (GET_MODE (XEXP (x, 0))))
10101 /* Otherwise try and find where the condition codes were last set and
10103 x = get_last_value (XEXP (x, 0));
10104 return (x && GET_CODE (x) == COMPARE
10105 && ! FLOAT_MODE_P (GET_MODE (XEXP (x, 0))));
10111 /* Utility function for following routine. Called when X is part of a value
10112 being stored into reg_last_set_value. Sets reg_last_set_table_tick
10113 for each register mentioned. Similar to mention_regs in cse.c */
10116 update_table_tick (x)
10119 register enum rtx_code code = GET_CODE (x);
10120 register char *fmt = GET_RTX_FORMAT (code);
10125 int regno = REGNO (x);
10126 int endregno = regno + (regno < FIRST_PSEUDO_REGISTER
10127 ? HARD_REGNO_NREGS (regno, GET_MODE (x)) : 1);
10129 for (i = regno; i < endregno; i++)
10130 reg_last_set_table_tick[i] = label_tick;
10135 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
10136 /* Note that we can't have an "E" in values stored; see
10137 get_last_value_validate. */
10139 update_table_tick (XEXP (x, i));
10142 /* Record that REG is set to VALUE in insn INSN. If VALUE is zero, we
10143 are saying that the register is clobbered and we no longer know its
10144 value. If INSN is zero, don't update reg_last_set; this is only permitted
10145 with VALUE also zero and is used to invalidate the register. */
10148 record_value_for_reg (reg, insn, value)
10153 int regno = REGNO (reg);
10154 int endregno = regno + (regno < FIRST_PSEUDO_REGISTER
10155 ? HARD_REGNO_NREGS (regno, GET_MODE (reg)) : 1);
10158 /* If VALUE contains REG and we have a previous value for REG, substitute
10159 the previous value. */
10160 if (value && insn && reg_overlap_mentioned_p (reg, value))
10164 /* Set things up so get_last_value is allowed to see anything set up to
10166 subst_low_cuid = INSN_CUID (insn);
10167 tem = get_last_value (reg);
10170 value = replace_rtx (copy_rtx (value), reg, tem);
10173 /* For each register modified, show we don't know its value, that
10174 we don't know about its bitwise content, that its value has been
10175 updated, and that we don't know the location of the death of the
10177 for (i = regno; i < endregno; i ++)
10180 reg_last_set[i] = insn;
10181 reg_last_set_value[i] = 0;
10182 reg_last_set_mode[i] = 0;
10183 reg_last_set_nonzero_bits[i] = 0;
10184 reg_last_set_sign_bit_copies[i] = 0;
10185 reg_last_death[i] = 0;
10188 /* Mark registers that are being referenced in this value. */
10190 update_table_tick (value);
10192 /* Now update the status of each register being set.
10193 If someone is using this register in this block, set this register
10194 to invalid since we will get confused between the two lives in this
10195 basic block. This makes using this register always invalid. In cse, we
10196 scan the table to invalidate all entries using this register, but this
10197 is too much work for us. */
10199 for (i = regno; i < endregno; i++)
10201 reg_last_set_label[i] = label_tick;
10202 if (value && reg_last_set_table_tick[i] == label_tick)
10203 reg_last_set_invalid[i] = 1;
10205 reg_last_set_invalid[i] = 0;
10208 /* The value being assigned might refer to X (like in "x++;"). In that
10209 case, we must replace it with (clobber (const_int 0)) to prevent
10211 if (value && ! get_last_value_validate (&value, insn,
10212 reg_last_set_label[regno], 0))
10214 value = copy_rtx (value);
10215 if (! get_last_value_validate (&value, insn,
10216 reg_last_set_label[regno], 1))
10220 /* For the main register being modified, update the value, the mode, the
10221 nonzero bits, and the number of sign bit copies. */
10223 reg_last_set_value[regno] = value;
10227 subst_low_cuid = INSN_CUID (insn);
10228 reg_last_set_mode[regno] = GET_MODE (reg);
10229 reg_last_set_nonzero_bits[regno] = nonzero_bits (value, GET_MODE (reg));
10230 reg_last_set_sign_bit_copies[regno]
10231 = num_sign_bit_copies (value, GET_MODE (reg));
10235 /* Used for communication between the following two routines. */
10236 static rtx record_dead_insn;
10238 /* Called via note_stores from record_dead_and_set_regs to handle one
10239 SET or CLOBBER in an insn. */
10242 record_dead_and_set_regs_1 (dest, setter)
10245 if (GET_CODE (dest) == SUBREG)
10246 dest = SUBREG_REG (dest);
10248 if (GET_CODE (dest) == REG)
10250 /* If we are setting the whole register, we know its value. Otherwise
10251 show that we don't know the value. We can handle SUBREG in
10253 if (GET_CODE (setter) == SET && dest == SET_DEST (setter))
10254 record_value_for_reg (dest, record_dead_insn, SET_SRC (setter));
10255 else if (GET_CODE (setter) == SET
10256 && GET_CODE (SET_DEST (setter)) == SUBREG
10257 && SUBREG_REG (SET_DEST (setter)) == dest
10258 && GET_MODE_BITSIZE (GET_MODE (dest)) <= BITS_PER_WORD
10259 && subreg_lowpart_p (SET_DEST (setter)))
10260 record_value_for_reg (dest, record_dead_insn,
10261 gen_lowpart_for_combine (GET_MODE (dest),
10262 SET_SRC (setter)));
10264 record_value_for_reg (dest, record_dead_insn, NULL_RTX);
10266 else if (GET_CODE (dest) == MEM
10267 /* Ignore pushes, they clobber nothing. */
10268 && ! push_operand (dest, GET_MODE (dest)))
10269 mem_last_set = INSN_CUID (record_dead_insn);
10272 /* Update the records of when each REG was most recently set or killed
10273 for the things done by INSN. This is the last thing done in processing
10274 INSN in the combiner loop.
10276 We update reg_last_set, reg_last_set_value, reg_last_set_mode,
10277 reg_last_set_nonzero_bits, reg_last_set_sign_bit_copies, reg_last_death,
10278 and also the similar information mem_last_set (which insn most recently
10279 modified memory) and last_call_cuid (which insn was the most recent
10280 subroutine call). */
10283 record_dead_and_set_regs (insn)
10289 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
10291 if (REG_NOTE_KIND (link) == REG_DEAD
10292 && GET_CODE (XEXP (link, 0)) == REG)
10294 int regno = REGNO (XEXP (link, 0));
10296 = regno + (regno < FIRST_PSEUDO_REGISTER
10297 ? HARD_REGNO_NREGS (regno, GET_MODE (XEXP (link, 0)))
10300 for (i = regno; i < endregno; i++)
10301 reg_last_death[i] = insn;
10303 else if (REG_NOTE_KIND (link) == REG_INC)
10304 record_value_for_reg (XEXP (link, 0), insn, NULL_RTX);
10307 if (GET_CODE (insn) == CALL_INSN)
10309 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
10310 if (call_used_regs[i])
10312 reg_last_set_value[i] = 0;
10313 reg_last_set_mode[i] = 0;
10314 reg_last_set_nonzero_bits[i] = 0;
10315 reg_last_set_sign_bit_copies[i] = 0;
10316 reg_last_death[i] = 0;
10319 last_call_cuid = mem_last_set = INSN_CUID (insn);
10322 record_dead_insn = insn;
10323 note_stores (PATTERN (insn), record_dead_and_set_regs_1);
10326 /* Utility routine for the following function. Verify that all the registers
10327 mentioned in *LOC are valid when *LOC was part of a value set when
10328 label_tick == TICK. Return 0 if some are not.
10330 If REPLACE is non-zero, replace the invalid reference with
10331 (clobber (const_int 0)) and return 1. This replacement is useful because
10332 we often can get useful information about the form of a value (e.g., if
10333 it was produced by a shift that always produces -1 or 0) even though
10334 we don't know exactly what registers it was produced from. */
10337 get_last_value_validate (loc, insn, tick, replace)
10344 char *fmt = GET_RTX_FORMAT (GET_CODE (x));
10345 int len = GET_RTX_LENGTH (GET_CODE (x));
10348 if (GET_CODE (x) == REG)
10350 int regno = REGNO (x);
10351 int endregno = regno + (regno < FIRST_PSEUDO_REGISTER
10352 ? HARD_REGNO_NREGS (regno, GET_MODE (x)) : 1);
10355 for (j = regno; j < endregno; j++)
10356 if (reg_last_set_invalid[j]
10357 /* If this is a pseudo-register that was only set once, it is
10359 || (! (regno >= FIRST_PSEUDO_REGISTER && REG_N_SETS (regno) == 1)
10360 && reg_last_set_label[j] > tick))
10363 *loc = gen_rtx (CLOBBER, GET_MODE (x), const0_rtx);
10369 /* If this is a memory reference, make sure that there were
10370 no stores after it that might have clobbered the value. We don't
10371 have alias info, so we assume any store invalidates it. */
10372 else if (GET_CODE (x) == MEM && ! RTX_UNCHANGING_P (x)
10373 && INSN_CUID (insn) <= mem_last_set)
10376 *loc = gen_rtx (CLOBBER, GET_MODE (x), const0_rtx);
10380 for (i = 0; i < len; i++)
10382 && get_last_value_validate (&XEXP (x, i), insn, tick, replace) == 0)
10383 /* Don't bother with these. They shouldn't occur anyway. */
10387 /* If we haven't found a reason for it to be invalid, it is valid. */
10391 /* Get the last value assigned to X, if known. Some registers
10392 in the value may be replaced with (clobber (const_int 0)) if their value
10393 is known longer known reliably. */
10402 /* If this is a non-paradoxical SUBREG, get the value of its operand and
10403 then convert it to the desired mode. If this is a paradoxical SUBREG,
10404 we cannot predict what values the "extra" bits might have. */
10405 if (GET_CODE (x) == SUBREG
10406 && subreg_lowpart_p (x)
10407 && (GET_MODE_SIZE (GET_MODE (x))
10408 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
10409 && (value = get_last_value (SUBREG_REG (x))) != 0)
10410 return gen_lowpart_for_combine (GET_MODE (x), value);
10412 if (GET_CODE (x) != REG)
10416 value = reg_last_set_value[regno];
10418 /* If we don't have a value or if it isn't for this basic block,
10422 || (REG_N_SETS (regno) != 1
10423 && reg_last_set_label[regno] != label_tick))
10426 /* If the value was set in a later insn than the ones we are processing,
10427 we can't use it even if the register was only set once, but make a quick
10428 check to see if the previous insn set it to something. This is commonly
10429 the case when the same pseudo is used by repeated insns.
10431 This does not work if there exists an instruction which is temporarily
10432 not on the insn chain. */
10434 if (INSN_CUID (reg_last_set[regno]) >= subst_low_cuid)
10438 /* We can not do anything useful in this case, because there is
10439 an instruction which is not on the insn chain. */
10440 if (subst_prev_insn)
10443 /* Skip over USE insns. They are not useful here, and they may have
10444 been made by combine, in which case they do not have a INSN_CUID
10445 value. We can't use prev_real_insn, because that would incorrectly
10446 take us backwards across labels. Skip over BARRIERs also, since
10447 they could have been made by combine. If we see one, we must be
10448 optimizing dead code, so it doesn't matter what we do. */
10449 for (insn = prev_nonnote_insn (subst_insn);
10450 insn && ((GET_CODE (insn) == INSN
10451 && GET_CODE (PATTERN (insn)) == USE)
10452 || GET_CODE (insn) == BARRIER
10453 || INSN_CUID (insn) >= subst_low_cuid);
10454 insn = prev_nonnote_insn (insn))
10458 && (set = single_set (insn)) != 0
10459 && rtx_equal_p (SET_DEST (set), x))
10461 value = SET_SRC (set);
10463 /* Make sure that VALUE doesn't reference X. Replace any
10464 explicit references with a CLOBBER. If there are any remaining
10465 references (rare), don't use the value. */
10467 if (reg_mentioned_p (x, value))
10468 value = replace_rtx (copy_rtx (value), x,
10469 gen_rtx (CLOBBER, GET_MODE (x), const0_rtx));
10471 if (reg_overlap_mentioned_p (x, value))
10478 /* If the value has all its registers valid, return it. */
10479 if (get_last_value_validate (&value, reg_last_set[regno],
10480 reg_last_set_label[regno], 0))
10483 /* Otherwise, make a copy and replace any invalid register with
10484 (clobber (const_int 0)). If that fails for some reason, return 0. */
10486 value = copy_rtx (value);
10487 if (get_last_value_validate (&value, reg_last_set[regno],
10488 reg_last_set_label[regno], 1))
10494 /* Return nonzero if expression X refers to a REG or to memory
10495 that is set in an instruction more recent than FROM_CUID. */
10498 use_crosses_set_p (x, from_cuid)
10502 register char *fmt;
10504 register enum rtx_code code = GET_CODE (x);
10508 register int regno = REGNO (x);
10509 int endreg = regno + (regno < FIRST_PSEUDO_REGISTER
10510 ? HARD_REGNO_NREGS (regno, GET_MODE (x)) : 1);
10512 #ifdef PUSH_ROUNDING
10513 /* Don't allow uses of the stack pointer to be moved,
10514 because we don't know whether the move crosses a push insn. */
10515 if (regno == STACK_POINTER_REGNUM)
10518 for (;regno < endreg; regno++)
10519 if (reg_last_set[regno]
10520 && INSN_CUID (reg_last_set[regno]) > from_cuid)
10525 if (code == MEM && mem_last_set > from_cuid)
10528 fmt = GET_RTX_FORMAT (code);
10530 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
10535 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
10536 if (use_crosses_set_p (XVECEXP (x, i, j), from_cuid))
10539 else if (fmt[i] == 'e'
10540 && use_crosses_set_p (XEXP (x, i), from_cuid))
10546 /* Define three variables used for communication between the following
10549 static int reg_dead_regno, reg_dead_endregno;
10550 static int reg_dead_flag;
10552 /* Function called via note_stores from reg_dead_at_p.
10554 If DEST is within [reg_dead_regno, reg_dead_endregno), set
10555 reg_dead_flag to 1 if X is a CLOBBER and to -1 it is a SET. */
10558 reg_dead_at_p_1 (dest, x)
10562 int regno, endregno;
10564 if (GET_CODE (dest) != REG)
10567 regno = REGNO (dest);
10568 endregno = regno + (regno < FIRST_PSEUDO_REGISTER
10569 ? HARD_REGNO_NREGS (regno, GET_MODE (dest)) : 1);
10571 if (reg_dead_endregno > regno && reg_dead_regno < endregno)
10572 reg_dead_flag = (GET_CODE (x) == CLOBBER) ? 1 : -1;
10575 /* Return non-zero if REG is known to be dead at INSN.
10577 We scan backwards from INSN. If we hit a REG_DEAD note or a CLOBBER
10578 referencing REG, it is dead. If we hit a SET referencing REG, it is
10579 live. Otherwise, see if it is live or dead at the start of the basic
10580 block we are in. Hard regs marked as being live in NEWPAT_USED_REGS
10581 must be assumed to be always live. */
10584 reg_dead_at_p (reg, insn)
10590 /* Set variables for reg_dead_at_p_1. */
10591 reg_dead_regno = REGNO (reg);
10592 reg_dead_endregno = reg_dead_regno + (reg_dead_regno < FIRST_PSEUDO_REGISTER
10593 ? HARD_REGNO_NREGS (reg_dead_regno,
10599 /* Check that reg isn't mentioned in NEWPAT_USED_REGS. */
10600 if (reg_dead_regno < FIRST_PSEUDO_REGISTER)
10602 for (i = reg_dead_regno; i < reg_dead_endregno; i++)
10603 if (TEST_HARD_REG_BIT (newpat_used_regs, i))
10607 /* Scan backwards until we find a REG_DEAD note, SET, CLOBBER, label, or
10608 beginning of function. */
10609 for (; insn && GET_CODE (insn) != CODE_LABEL && GET_CODE (insn) != BARRIER;
10610 insn = prev_nonnote_insn (insn))
10612 note_stores (PATTERN (insn), reg_dead_at_p_1);
10614 return reg_dead_flag == 1 ? 1 : 0;
10616 if (find_regno_note (insn, REG_DEAD, reg_dead_regno))
10620 /* Get the basic block number that we were in. */
10625 for (block = 0; block < n_basic_blocks; block++)
10626 if (insn == basic_block_head[block])
10629 if (block == n_basic_blocks)
10633 for (i = reg_dead_regno; i < reg_dead_endregno; i++)
10634 if (REGNO_REG_SET_P (basic_block_live_at_start[block], i))
10640 /* Note hard registers in X that are used. This code is similar to
10641 that in flow.c, but much simpler since we don't care about pseudos. */
10644 mark_used_regs_combine (x)
10647 register RTX_CODE code = GET_CODE (x);
10648 register int regno;
10660 case ADDR_DIFF_VEC:
10663 /* CC0 must die in the insn after it is set, so we don't need to take
10664 special note of it here. */
10670 /* If we are clobbering a MEM, mark any hard registers inside the
10671 address as used. */
10672 if (GET_CODE (XEXP (x, 0)) == MEM)
10673 mark_used_regs_combine (XEXP (XEXP (x, 0), 0));
10678 /* A hard reg in a wide mode may really be multiple registers.
10679 If so, mark all of them just like the first. */
10680 if (regno < FIRST_PSEUDO_REGISTER)
10682 /* None of this applies to the stack, frame or arg pointers */
10683 if (regno == STACK_POINTER_REGNUM
10684 #if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM
10685 || regno == HARD_FRAME_POINTER_REGNUM
10687 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
10688 || (regno == ARG_POINTER_REGNUM && fixed_regs[regno])
10690 || regno == FRAME_POINTER_REGNUM)
10693 i = HARD_REGNO_NREGS (regno, GET_MODE (x));
10695 SET_HARD_REG_BIT (newpat_used_regs, regno + i);
10701 /* If setting a MEM, or a SUBREG of a MEM, then note any hard regs in
10703 register rtx testreg = SET_DEST (x);
10705 while (GET_CODE (testreg) == SUBREG
10706 || GET_CODE (testreg) == ZERO_EXTRACT
10707 || GET_CODE (testreg) == SIGN_EXTRACT
10708 || GET_CODE (testreg) == STRICT_LOW_PART)
10709 testreg = XEXP (testreg, 0);
10711 if (GET_CODE (testreg) == MEM)
10712 mark_used_regs_combine (XEXP (testreg, 0));
10714 mark_used_regs_combine (SET_SRC (x));
10719 /* Recursively scan the operands of this expression. */
10722 register char *fmt = GET_RTX_FORMAT (code);
10724 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
10727 mark_used_regs_combine (XEXP (x, i));
10728 else if (fmt[i] == 'E')
10732 for (j = 0; j < XVECLEN (x, i); j++)
10733 mark_used_regs_combine (XVECEXP (x, i, j));
10740 /* Remove register number REGNO from the dead registers list of INSN.
10742 Return the note used to record the death, if there was one. */
10745 remove_death (regno, insn)
10749 register rtx note = find_regno_note (insn, REG_DEAD, regno);
10753 REG_N_DEATHS (regno)--;
10754 remove_note (insn, note);
10760 /* For each register (hardware or pseudo) used within expression X, if its
10761 death is in an instruction with cuid between FROM_CUID (inclusive) and
10762 TO_INSN (exclusive), put a REG_DEAD note for that register in the
10763 list headed by PNOTES.
10765 That said, don't move registers killed by maybe_kill_insn.
10767 This is done when X is being merged by combination into TO_INSN. These
10768 notes will then be distributed as needed. */
10771 move_deaths (x, maybe_kill_insn, from_cuid, to_insn, pnotes)
10773 rtx maybe_kill_insn;
10778 register char *fmt;
10779 register int len, i;
10780 register enum rtx_code code = GET_CODE (x);
10784 register int regno = REGNO (x);
10785 register rtx where_dead = reg_last_death[regno];
10786 register rtx before_dead, after_dead;
10788 /* Don't move the register if it gets killed in between from and to */
10789 if (maybe_kill_insn && reg_set_p (x, maybe_kill_insn)
10790 && !reg_referenced_p (x, maybe_kill_insn))
10793 /* WHERE_DEAD could be a USE insn made by combine, so first we
10794 make sure that we have insns with valid INSN_CUID values. */
10795 before_dead = where_dead;
10796 while (before_dead && INSN_UID (before_dead) > max_uid_cuid)
10797 before_dead = PREV_INSN (before_dead);
10798 after_dead = where_dead;
10799 while (after_dead && INSN_UID (after_dead) > max_uid_cuid)
10800 after_dead = NEXT_INSN (after_dead);
10802 if (before_dead && after_dead
10803 && INSN_CUID (before_dead) >= from_cuid
10804 && (INSN_CUID (after_dead) < INSN_CUID (to_insn)
10805 || (where_dead != after_dead
10806 && INSN_CUID (after_dead) == INSN_CUID (to_insn))))
10808 rtx note = remove_death (regno, where_dead);
10810 /* It is possible for the call above to return 0. This can occur
10811 when reg_last_death points to I2 or I1 that we combined with.
10812 In that case make a new note.
10814 We must also check for the case where X is a hard register
10815 and NOTE is a death note for a range of hard registers
10816 including X. In that case, we must put REG_DEAD notes for
10817 the remaining registers in place of NOTE. */
10819 if (note != 0 && regno < FIRST_PSEUDO_REGISTER
10820 && (GET_MODE_SIZE (GET_MODE (XEXP (note, 0)))
10821 > GET_MODE_SIZE (GET_MODE (x))))
10823 int deadregno = REGNO (XEXP (note, 0));
10825 = (deadregno + HARD_REGNO_NREGS (deadregno,
10826 GET_MODE (XEXP (note, 0))));
10827 int ourend = regno + HARD_REGNO_NREGS (regno, GET_MODE (x));
10830 for (i = deadregno; i < deadend; i++)
10831 if (i < regno || i >= ourend)
10832 REG_NOTES (where_dead)
10833 = gen_rtx (EXPR_LIST, REG_DEAD,
10834 gen_rtx (REG, reg_raw_mode[i], i),
10835 REG_NOTES (where_dead));
10837 /* If we didn't find any note, or if we found a REG_DEAD note that
10838 covers only part of the given reg, and we have a multi-reg hard
10839 register, then to be safe we must check for REG_DEAD notes
10840 for each register other than the first. They could have
10841 their own REG_DEAD notes lying around. */
10842 else if ((note == 0
10844 && (GET_MODE_SIZE (GET_MODE (XEXP (note, 0)))
10845 < GET_MODE_SIZE (GET_MODE (x)))))
10846 && regno < FIRST_PSEUDO_REGISTER
10847 && HARD_REGNO_NREGS (regno, GET_MODE (x)) > 1)
10849 int ourend = regno + HARD_REGNO_NREGS (regno, GET_MODE (x));
10854 offset = HARD_REGNO_NREGS (regno, GET_MODE (XEXP (note, 0)));
10858 for (i = regno + offset; i < ourend; i++)
10859 move_deaths (gen_rtx (REG, reg_raw_mode[i], i),
10860 maybe_kill_insn, from_cuid, to_insn, &oldnotes);
10863 if (note != 0 && GET_MODE (XEXP (note, 0)) == GET_MODE (x))
10865 XEXP (note, 1) = *pnotes;
10869 *pnotes = gen_rtx (EXPR_LIST, REG_DEAD, x, *pnotes);
10871 REG_N_DEATHS (regno)++;
10877 else if (GET_CODE (x) == SET)
10879 rtx dest = SET_DEST (x);
10881 move_deaths (SET_SRC (x), maybe_kill_insn, from_cuid, to_insn, pnotes);
10883 /* In the case of a ZERO_EXTRACT, a STRICT_LOW_PART, or a SUBREG
10884 that accesses one word of a multi-word item, some
10885 piece of everything register in the expression is used by
10886 this insn, so remove any old death. */
10888 if (GET_CODE (dest) == ZERO_EXTRACT
10889 || GET_CODE (dest) == STRICT_LOW_PART
10890 || (GET_CODE (dest) == SUBREG
10891 && (((GET_MODE_SIZE (GET_MODE (dest))
10892 + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
10893 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (dest)))
10894 + UNITS_PER_WORD - 1) / UNITS_PER_WORD))))
10896 move_deaths (dest, maybe_kill_insn, from_cuid, to_insn, pnotes);
10900 /* If this is some other SUBREG, we know it replaces the entire
10901 value, so use that as the destination. */
10902 if (GET_CODE (dest) == SUBREG)
10903 dest = SUBREG_REG (dest);
10905 /* If this is a MEM, adjust deaths of anything used in the address.
10906 For a REG (the only other possibility), the entire value is
10907 being replaced so the old value is not used in this insn. */
10909 if (GET_CODE (dest) == MEM)
10910 move_deaths (XEXP (dest, 0), maybe_kill_insn, from_cuid,
10915 else if (GET_CODE (x) == CLOBBER)
10918 len = GET_RTX_LENGTH (code);
10919 fmt = GET_RTX_FORMAT (code);
10921 for (i = 0; i < len; i++)
10926 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
10927 move_deaths (XVECEXP (x, i, j), maybe_kill_insn, from_cuid,
10930 else if (fmt[i] == 'e')
10931 move_deaths (XEXP (x, i), maybe_kill_insn, from_cuid, to_insn, pnotes);
10935 /* Return 1 if X is the target of a bit-field assignment in BODY, the
10936 pattern of an insn. X must be a REG. */
10939 reg_bitfield_target_p (x, body)
10945 if (GET_CODE (body) == SET)
10947 rtx dest = SET_DEST (body);
10949 int regno, tregno, endregno, endtregno;
10951 if (GET_CODE (dest) == ZERO_EXTRACT)
10952 target = XEXP (dest, 0);
10953 else if (GET_CODE (dest) == STRICT_LOW_PART)
10954 target = SUBREG_REG (XEXP (dest, 0));
10958 if (GET_CODE (target) == SUBREG)
10959 target = SUBREG_REG (target);
10961 if (GET_CODE (target) != REG)
10964 tregno = REGNO (target), regno = REGNO (x);
10965 if (tregno >= FIRST_PSEUDO_REGISTER || regno >= FIRST_PSEUDO_REGISTER)
10966 return target == x;
10968 endtregno = tregno + HARD_REGNO_NREGS (tregno, GET_MODE (target));
10969 endregno = regno + HARD_REGNO_NREGS (regno, GET_MODE (x));
10971 return endregno > tregno && regno < endtregno;
10974 else if (GET_CODE (body) == PARALLEL)
10975 for (i = XVECLEN (body, 0) - 1; i >= 0; i--)
10976 if (reg_bitfield_target_p (x, XVECEXP (body, 0, i)))
10982 /* Given a chain of REG_NOTES originally from FROM_INSN, try to place them
10983 as appropriate. I3 and I2 are the insns resulting from the combination
10984 insns including FROM (I2 may be zero).
10986 ELIM_I2 and ELIM_I1 are either zero or registers that we know will
10987 not need REG_DEAD notes because they are being substituted for. This
10988 saves searching in the most common cases.
10990 Each note in the list is either ignored or placed on some insns, depending
10991 on the type of note. */
10994 distribute_notes (notes, from_insn, i3, i2, elim_i2, elim_i1)
10998 rtx elim_i2, elim_i1;
11000 rtx note, next_note;
11003 for (note = notes; note; note = next_note)
11005 rtx place = 0, place2 = 0;
11007 /* If this NOTE references a pseudo register, ensure it references
11008 the latest copy of that register. */
11009 if (XEXP (note, 0) && GET_CODE (XEXP (note, 0)) == REG
11010 && REGNO (XEXP (note, 0)) >= FIRST_PSEUDO_REGISTER)
11011 XEXP (note, 0) = regno_reg_rtx[REGNO (XEXP (note, 0))];
11013 next_note = XEXP (note, 1);
11014 switch (REG_NOTE_KIND (note))
11017 case REG_EXEC_COUNT:
11018 /* Doesn't matter much where we put this, as long as it's somewhere.
11019 It is preferable to keep these notes on branches, which is most
11020 likely to be i3. */
11025 /* Any clobbers for i3 may still exist, and so we must process
11026 REG_UNUSED notes from that insn.
11028 Any clobbers from i2 or i1 can only exist if they were added by
11029 recog_for_combine. In that case, recog_for_combine created the
11030 necessary REG_UNUSED notes. Trying to keep any original
11031 REG_UNUSED notes from these insns can cause incorrect output
11032 if it is for the same register as the original i3 dest.
11033 In that case, we will notice that the register is set in i3,
11034 and then add a REG_UNUSED note for the destination of i3, which
11035 is wrong. However, it is possible to have REG_UNUSED notes from
11036 i2 or i1 for register which were both used and clobbered, so
11037 we keep notes from i2 or i1 if they will turn into REG_DEAD
11040 /* If this register is set or clobbered in I3, put the note there
11041 unless there is one already. */
11042 if (reg_set_p (XEXP (note, 0), PATTERN (i3)))
11044 if (from_insn != i3)
11047 if (! (GET_CODE (XEXP (note, 0)) == REG
11048 ? find_regno_note (i3, REG_UNUSED, REGNO (XEXP (note, 0)))
11049 : find_reg_note (i3, REG_UNUSED, XEXP (note, 0))))
11052 /* Otherwise, if this register is used by I3, then this register
11053 now dies here, so we must put a REG_DEAD note here unless there
11055 else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3))
11056 && ! (GET_CODE (XEXP (note, 0)) == REG
11057 ? find_regno_note (i3, REG_DEAD, REGNO (XEXP (note, 0)))
11058 : find_reg_note (i3, REG_DEAD, XEXP (note, 0))))
11060 PUT_REG_NOTE_KIND (note, REG_DEAD);
11069 /* These notes say something about results of an insn. We can
11070 only support them if they used to be on I3 in which case they
11071 remain on I3. Otherwise they are ignored.
11073 If the note refers to an expression that is not a constant, we
11074 must also ignore the note since we cannot tell whether the
11075 equivalence is still true. It might be possible to do
11076 slightly better than this (we only have a problem if I2DEST
11077 or I1DEST is present in the expression), but it doesn't
11078 seem worth the trouble. */
11080 if (from_insn == i3
11081 && (XEXP (note, 0) == 0 || CONSTANT_P (XEXP (note, 0))))
11086 case REG_NO_CONFLICT:
11088 /* These notes say something about how a register is used. They must
11089 be present on any use of the register in I2 or I3. */
11090 if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3)))
11093 if (i2 && reg_mentioned_p (XEXP (note, 0), PATTERN (i2)))
11103 /* It is too much trouble to try to see if this note is still
11104 correct in all situations. It is better to simply delete it. */
11108 /* If the insn previously containing this note still exists,
11109 put it back where it was. Otherwise move it to the previous
11110 insn. Adjust the corresponding REG_LIBCALL note. */
11111 if (GET_CODE (from_insn) != NOTE)
11115 tem = find_reg_note (XEXP (note, 0), REG_LIBCALL, NULL_RTX);
11116 place = prev_real_insn (from_insn);
11118 XEXP (tem, 0) = place;
11123 /* This is handled similarly to REG_RETVAL. */
11124 if (GET_CODE (from_insn) != NOTE)
11128 tem = find_reg_note (XEXP (note, 0), REG_RETVAL, NULL_RTX);
11129 place = next_real_insn (from_insn);
11131 XEXP (tem, 0) = place;
11136 /* If the register is used as an input in I3, it dies there.
11137 Similarly for I2, if it is non-zero and adjacent to I3.
11139 If the register is not used as an input in either I3 or I2
11140 and it is not one of the registers we were supposed to eliminate,
11141 there are two possibilities. We might have a non-adjacent I2
11142 or we might have somehow eliminated an additional register
11143 from a computation. For example, we might have had A & B where
11144 we discover that B will always be zero. In this case we will
11145 eliminate the reference to A.
11147 In both cases, we must search to see if we can find a previous
11148 use of A and put the death note there. */
11151 && GET_CODE (from_insn) == CALL_INSN
11152 && find_reg_fusage (from_insn, USE, XEXP (note, 0)))
11154 else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3)))
11156 else if (i2 != 0 && next_nonnote_insn (i2) == i3
11157 && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
11160 if (XEXP (note, 0) == elim_i2 || XEXP (note, 0) == elim_i1)
11163 /* If the register is used in both I2 and I3 and it dies in I3,
11164 we might have added another reference to it. If reg_n_refs
11165 was 2, bump it to 3. This has to be correct since the
11166 register must have been set somewhere. The reason this is
11167 done is because local-alloc.c treats 2 references as a
11170 if (place == i3 && i2 != 0 && GET_CODE (XEXP (note, 0)) == REG
11171 && REG_N_REFS (REGNO (XEXP (note, 0)))== 2
11172 && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
11173 REG_N_REFS (REGNO (XEXP (note, 0))) = 3;
11177 for (tem = prev_nonnote_insn (i3);
11179 && (GET_CODE (tem) == INSN || GET_CODE (tem) == CALL_INSN);
11180 tem = prev_nonnote_insn (tem))
11182 /* If the register is being set at TEM, see if that is all
11183 TEM is doing. If so, delete TEM. Otherwise, make this
11184 into a REG_UNUSED note instead. */
11185 if (reg_set_p (XEXP (note, 0), PATTERN (tem)))
11187 rtx set = single_set (tem);
11189 /* Verify that it was the set, and not a clobber that
11190 modified the register. */
11192 if (set != 0 && ! side_effects_p (SET_SRC (set))
11193 && (rtx_equal_p (XEXP (note, 0), SET_DEST (set))
11194 || (GET_CODE (SET_DEST (set)) == SUBREG
11195 && rtx_equal_p (XEXP (note, 0),
11196 XEXP (SET_DEST (set), 0)))))
11198 /* Move the notes and links of TEM elsewhere.
11199 This might delete other dead insns recursively.
11200 First set the pattern to something that won't use
11203 PATTERN (tem) = pc_rtx;
11205 distribute_notes (REG_NOTES (tem), tem, tem,
11206 NULL_RTX, NULL_RTX, NULL_RTX);
11207 distribute_links (LOG_LINKS (tem));
11209 PUT_CODE (tem, NOTE);
11210 NOTE_LINE_NUMBER (tem) = NOTE_INSN_DELETED;
11211 NOTE_SOURCE_FILE (tem) = 0;
11215 PUT_REG_NOTE_KIND (note, REG_UNUSED);
11217 /* If there isn't already a REG_UNUSED note, put one
11219 if (! find_regno_note (tem, REG_UNUSED,
11220 REGNO (XEXP (note, 0))))
11225 else if (reg_referenced_p (XEXP (note, 0), PATTERN (tem))
11226 || (GET_CODE (tem) == CALL_INSN
11227 && find_reg_fusage (tem, USE, XEXP (note, 0))))
11231 /* If we are doing a 3->2 combination, and we have a
11232 register which formerly died in i3 and was not used
11233 by i2, which now no longer dies in i3 and is used in
11234 i2 but does not die in i2, and place is between i2
11235 and i3, then we may need to move a link from place to
11237 if (i2 && INSN_UID (place) <= max_uid_cuid
11238 && INSN_CUID (place) > INSN_CUID (i2)
11239 && from_insn && INSN_CUID (from_insn) > INSN_CUID (i2)
11240 && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
11242 rtx links = LOG_LINKS (place);
11243 LOG_LINKS (place) = 0;
11244 distribute_links (links);
11250 /* If we haven't found an insn for the death note and it
11251 is still a REG_DEAD note, but we have hit a CODE_LABEL,
11252 insert a USE insn for the register at that label and
11253 put the death node there. This prevents problems with
11254 call-state tracking in caller-save.c. */
11255 if (REG_NOTE_KIND (note) == REG_DEAD && place == 0 && tem != 0)
11258 = emit_insn_after (gen_rtx (USE, VOIDmode, XEXP (note, 0)),
11261 /* If this insn was emitted between blocks, then update
11262 basic_block_head of the current block to include it. */
11263 if (basic_block_end[this_basic_block - 1] == tem)
11264 basic_block_head[this_basic_block] = place;
11268 /* If the register is set or already dead at PLACE, we needn't do
11269 anything with this note if it is still a REG_DEAD note.
11271 Note that we cannot use just `dead_or_set_p' here since we can
11272 convert an assignment to a register into a bit-field assignment.
11273 Therefore, we must also omit the note if the register is the
11274 target of a bitfield assignment. */
11276 if (place && REG_NOTE_KIND (note) == REG_DEAD)
11278 int regno = REGNO (XEXP (note, 0));
11280 if (dead_or_set_p (place, XEXP (note, 0))
11281 || reg_bitfield_target_p (XEXP (note, 0), PATTERN (place)))
11283 /* Unless the register previously died in PLACE, clear
11284 reg_last_death. [I no longer understand why this is
11286 if (reg_last_death[regno] != place)
11287 reg_last_death[regno] = 0;
11291 reg_last_death[regno] = place;
11293 /* If this is a death note for a hard reg that is occupying
11294 multiple registers, ensure that we are still using all
11295 parts of the object. If we find a piece of the object
11296 that is unused, we must add a USE for that piece before
11297 PLACE and put the appropriate REG_DEAD note on it.
11299 An alternative would be to put a REG_UNUSED for the pieces
11300 on the insn that set the register, but that can't be done if
11301 it is not in the same block. It is simpler, though less
11302 efficient, to add the USE insns. */
11304 if (place && regno < FIRST_PSEUDO_REGISTER
11305 && HARD_REGNO_NREGS (regno, GET_MODE (XEXP (note, 0))) > 1)
11308 = regno + HARD_REGNO_NREGS (regno,
11309 GET_MODE (XEXP (note, 0)));
11313 for (i = regno; i < endregno; i++)
11314 if (! refers_to_regno_p (i, i + 1, PATTERN (place), 0)
11315 && ! find_regno_fusage (place, USE, i))
11317 rtx piece = gen_rtx (REG, reg_raw_mode[i], i);
11320 /* See if we already placed a USE note for this
11321 register in front of PLACE. */
11323 GET_CODE (PREV_INSN (p)) == INSN
11324 && GET_CODE (PATTERN (PREV_INSN (p))) == USE;
11326 if (rtx_equal_p (piece,
11327 XEXP (PATTERN (PREV_INSN (p)), 0)))
11336 = emit_insn_before (gen_rtx (USE, VOIDmode,
11339 REG_NOTES (use_insn)
11340 = gen_rtx (EXPR_LIST, REG_DEAD, piece,
11341 REG_NOTES (use_insn));
11347 /* Check for the case where the register dying partially
11348 overlaps the register set by this insn. */
11350 for (i = regno; i < endregno; i++)
11351 if (dead_or_set_regno_p (place, i))
11359 /* Put only REG_DEAD notes for pieces that are
11360 still used and that are not already dead or set. */
11362 for (i = regno; i < endregno; i++)
11364 rtx piece = gen_rtx (REG, reg_raw_mode[i], i);
11366 if ((reg_referenced_p (piece, PATTERN (place))
11367 || (GET_CODE (place) == CALL_INSN
11368 && find_reg_fusage (place, USE, piece)))
11369 && ! dead_or_set_p (place, piece)
11370 && ! reg_bitfield_target_p (piece,
11372 REG_NOTES (place) = gen_rtx (EXPR_LIST, REG_DEAD,
11374 REG_NOTES (place));
11384 /* Any other notes should not be present at this point in the
11391 XEXP (note, 1) = REG_NOTES (place);
11392 REG_NOTES (place) = note;
11394 else if ((REG_NOTE_KIND (note) == REG_DEAD
11395 || REG_NOTE_KIND (note) == REG_UNUSED)
11396 && GET_CODE (XEXP (note, 0)) == REG)
11397 REG_N_DEATHS (REGNO (XEXP (note, 0)))--;
11401 if ((REG_NOTE_KIND (note) == REG_DEAD
11402 || REG_NOTE_KIND (note) == REG_UNUSED)
11403 && GET_CODE (XEXP (note, 0)) == REG)
11404 REG_N_DEATHS (REGNO (XEXP (note, 0)))++;
11406 REG_NOTES (place2) = gen_rtx (GET_CODE (note), REG_NOTE_KIND (note),
11407 XEXP (note, 0), REG_NOTES (place2));
11412 /* Similarly to above, distribute the LOG_LINKS that used to be present on
11413 I3, I2, and I1 to new locations. This is also called in one case to
11414 add a link pointing at I3 when I3's destination is changed. */
11417 distribute_links (links)
11420 rtx link, next_link;
11422 for (link = links; link; link = next_link)
11428 next_link = XEXP (link, 1);
11430 /* If the insn that this link points to is a NOTE or isn't a single
11431 set, ignore it. In the latter case, it isn't clear what we
11432 can do other than ignore the link, since we can't tell which
11433 register it was for. Such links wouldn't be used by combine
11436 It is not possible for the destination of the target of the link to
11437 have been changed by combine. The only potential of this is if we
11438 replace I3, I2, and I1 by I3 and I2. But in that case the
11439 destination of I2 also remains unchanged. */
11441 if (GET_CODE (XEXP (link, 0)) == NOTE
11442 || (set = single_set (XEXP (link, 0))) == 0)
11445 reg = SET_DEST (set);
11446 while (GET_CODE (reg) == SUBREG || GET_CODE (reg) == ZERO_EXTRACT
11447 || GET_CODE (reg) == SIGN_EXTRACT
11448 || GET_CODE (reg) == STRICT_LOW_PART)
11449 reg = XEXP (reg, 0);
11451 /* A LOG_LINK is defined as being placed on the first insn that uses
11452 a register and points to the insn that sets the register. Start
11453 searching at the next insn after the target of the link and stop
11454 when we reach a set of the register or the end of the basic block.
11456 Note that this correctly handles the link that used to point from
11457 I3 to I2. Also note that not much searching is typically done here
11458 since most links don't point very far away. */
11460 for (insn = NEXT_INSN (XEXP (link, 0));
11461 (insn && (this_basic_block == n_basic_blocks - 1
11462 || basic_block_head[this_basic_block + 1] != insn));
11463 insn = NEXT_INSN (insn))
11464 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i'
11465 && reg_overlap_mentioned_p (reg, PATTERN (insn)))
11467 if (reg_referenced_p (reg, PATTERN (insn)))
11471 else if (GET_CODE (insn) == CALL_INSN
11472 && find_reg_fusage (insn, USE, reg))
11478 /* If we found a place to put the link, place it there unless there
11479 is already a link to the same insn as LINK at that point. */
11485 for (link2 = LOG_LINKS (place); link2; link2 = XEXP (link2, 1))
11486 if (XEXP (link2, 0) == XEXP (link, 0))
11491 XEXP (link, 1) = LOG_LINKS (place);
11492 LOG_LINKS (place) = link;
11494 /* Set added_links_insn to the earliest insn we added a
11496 if (added_links_insn == 0
11497 || INSN_CUID (added_links_insn) > INSN_CUID (place))
11498 added_links_insn = place;
11504 /* Compute INSN_CUID for INSN, which is an insn made by combine. */
11510 while (insn != 0 && INSN_UID (insn) > max_uid_cuid
11511 && GET_CODE (insn) == INSN && GET_CODE (PATTERN (insn)) == USE)
11512 insn = NEXT_INSN (insn);
11514 if (INSN_UID (insn) > max_uid_cuid)
11517 return INSN_CUID (insn);
11521 dump_combine_stats (file)
11526 ";; Combiner statistics: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n\n",
11527 combine_attempts, combine_merges, combine_extras, combine_successes);
11531 dump_combine_total_stats (file)
11536 "\n;; Combiner totals: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n",
11537 total_attempts, total_merges, total_extras, total_successes);