1 /* Optimize by combining instructions for GNU compiler.
2 Copyright (C) 1987, 1988, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it under
8 the terms of the GNU General Public License as published by the Free
9 Software Foundation; either version 2, or (at your option) any later
12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING. If not, write to the Free
19 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
22 /* This module is essentially the "combiner" phase of the U. of Arizona
23 Portable Optimizer, but redone to work on our list-structured
24 representation for RTL instead of their string representation.
26 The LOG_LINKS of each insn identify the most recent assignment
27 to each REG used in the insn. It is a list of previous insns,
28 each of which contains a SET for a REG that is used in this insn
29 and not used or set in between. LOG_LINKs never cross basic blocks.
30 They were set up by the preceding pass (lifetime analysis).
32 We try to combine each pair of insns joined by a logical link.
33 We also try to combine triples of insns A, B and C when
34 C has a link back to B and B has a link back to A.
36 LOG_LINKS does not have links for use of the CC0. They don't
37 need to, because the insn that sets the CC0 is always immediately
38 before the insn that tests it. So we always regard a branch
39 insn as having a logical link to the preceding insn. The same is true
40 for an insn explicitly using CC0.
42 We check (with use_crosses_set_p) to avoid combining in such a way
43 as to move a computation to a place where its value would be different.
45 Combination is done by mathematically substituting the previous
46 insn(s) values for the regs they set into the expressions in
47 the later insns that refer to these regs. If the result is a valid insn
48 for our target machine, according to the machine description,
49 we install it, delete the earlier insns, and update the data flow
50 information (LOG_LINKS and REG_NOTES) for what we did.
52 There are a few exceptions where the dataflow information created by
53 flow.c aren't completely updated:
55 - reg_live_length is not updated
56 - reg_n_refs is not adjusted in the rare case when a register is
57 no longer required in a computation
58 - there are extremely rare cases (see distribute_regnotes) when a
60 - a LOG_LINKS entry that refers to an insn with multiple SETs may be
61 removed because there is no way to know which register it was
64 To simplify substitution, we combine only when the earlier insn(s)
65 consist of only a single assignment. To simplify updating afterward,
66 we never combine when a subroutine call appears in the middle.
68 Since we do not represent assignments to CC0 explicitly except when that
69 is all an insn does, there is no LOG_LINKS entry in an insn that uses
70 the condition code for the insn that set the condition code.
71 Fortunately, these two insns must be consecutive.
72 Therefore, every JUMP_INSN is taken to have an implicit logical link
73 to the preceding insn. This is not quite right, since non-jumps can
74 also use the condition code; but in practice such insns would not
83 #include "hard-reg-set.h"
84 #include "basic-block.h"
85 #include "insn-config.h"
87 /* Include expr.h after insn-config.h so we get HAVE_conditional_move. */
89 #include "insn-attr.h"
94 /* It is not safe to use ordinary gen_lowpart in combine.
95 Use gen_lowpart_for_combine instead. See comments there. */
96 #define gen_lowpart dont_use_gen_lowpart_you_dummy
98 /* Number of attempts to combine instructions in this function. */
100 static int combine_attempts;
102 /* Number of attempts that got as far as substitution in this function. */
104 static int combine_merges;
106 /* Number of instructions combined with added SETs in this function. */
108 static int combine_extras;
110 /* Number of instructions combined in this function. */
112 static int combine_successes;
114 /* Totals over entire compilation. */
116 static int total_attempts, total_merges, total_extras, total_successes;
119 /* Vector mapping INSN_UIDs to cuids.
120 The cuids are like uids but increase monotonically always.
121 Combine always uses cuids so that it can compare them.
122 But actually renumbering the uids, which we used to do,
123 proves to be a bad idea because it makes it hard to compare
124 the dumps produced by earlier passes with those from later passes. */
126 static int *uid_cuid;
127 static int max_uid_cuid;
129 /* Get the cuid of an insn. */
131 #define INSN_CUID(INSN) \
132 (INSN_UID (INSN) > max_uid_cuid ? insn_cuid (INSN) : uid_cuid[INSN_UID (INSN)])
134 /* In case BITS_PER_WORD == HOST_BITS_PER_WIDE_INT, shifting by
135 BITS_PER_WORD would invoke undefined behavior. Work around it. */
137 #define UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD(val) \
138 (((unsigned HOST_WIDE_INT) (val) << (BITS_PER_WORD - 1)) << 1)
140 /* Maximum register number, which is the size of the tables below. */
142 static unsigned int combine_max_regno;
144 /* Record last point of death of (hard or pseudo) register n. */
146 static rtx *reg_last_death;
148 /* Record last point of modification of (hard or pseudo) register n. */
150 static rtx *reg_last_set;
152 /* Record the cuid of the last insn that invalidated memory
153 (anything that writes memory, and subroutine calls, but not pushes). */
155 static int mem_last_set;
157 /* Record the cuid of the last CALL_INSN
158 so we can tell whether a potential combination crosses any calls. */
160 static int last_call_cuid;
162 /* When `subst' is called, this is the insn that is being modified
163 (by combining in a previous insn). The PATTERN of this insn
164 is still the old pattern partially modified and it should not be
165 looked at, but this may be used to examine the successors of the insn
166 to judge whether a simplification is valid. */
168 static rtx subst_insn;
170 /* This is an insn that belongs before subst_insn, but is not currently
171 on the insn chain. */
173 static rtx subst_prev_insn;
175 /* This is the lowest CUID that `subst' is currently dealing with.
176 get_last_value will not return a value if the register was set at or
177 after this CUID. If not for this mechanism, we could get confused if
178 I2 or I1 in try_combine were an insn that used the old value of a register
179 to obtain a new value. In that case, we might erroneously get the
180 new value of the register when we wanted the old one. */
182 static int subst_low_cuid;
184 /* This contains any hard registers that are used in newpat; reg_dead_at_p
185 must consider all these registers to be always live. */
187 static HARD_REG_SET newpat_used_regs;
189 /* This is an insn to which a LOG_LINKS entry has been added. If this
190 insn is the earlier than I2 or I3, combine should rescan starting at
193 static rtx added_links_insn;
195 /* Basic block in which we are performing combines. */
196 static basic_block this_basic_block;
198 /* A bitmap indicating which blocks had registers go dead at entry.
199 After combine, we'll need to re-do global life analysis with
200 those blocks as starting points. */
201 static sbitmap refresh_blocks;
202 static int need_refresh;
204 /* The next group of arrays allows the recording of the last value assigned
205 to (hard or pseudo) register n. We use this information to see if a
206 operation being processed is redundant given a prior operation performed
207 on the register. For example, an `and' with a constant is redundant if
208 all the zero bits are already known to be turned off.
210 We use an approach similar to that used by cse, but change it in the
213 (1) We do not want to reinitialize at each label.
214 (2) It is useful, but not critical, to know the actual value assigned
215 to a register. Often just its form is helpful.
217 Therefore, we maintain the following arrays:
219 reg_last_set_value the last value assigned
220 reg_last_set_label records the value of label_tick when the
221 register was assigned
222 reg_last_set_table_tick records the value of label_tick when a
223 value using the register is assigned
224 reg_last_set_invalid set to non-zero when it is not valid
225 to use the value of this register in some
228 To understand the usage of these tables, it is important to understand
229 the distinction between the value in reg_last_set_value being valid
230 and the register being validly contained in some other expression in the
233 Entry I in reg_last_set_value is valid if it is non-zero, and either
234 reg_n_sets[i] is 1 or reg_last_set_label[i] == label_tick.
236 Register I may validly appear in any expression returned for the value
237 of another register if reg_n_sets[i] is 1. It may also appear in the
238 value for register J if reg_last_set_label[i] < reg_last_set_label[j] or
239 reg_last_set_invalid[j] is zero.
241 If an expression is found in the table containing a register which may
242 not validly appear in an expression, the register is replaced by
243 something that won't match, (clobber (const_int 0)).
245 reg_last_set_invalid[i] is set non-zero when register I is being assigned
246 to and reg_last_set_table_tick[i] == label_tick. */
248 /* Record last value assigned to (hard or pseudo) register n. */
250 static rtx *reg_last_set_value;
252 /* Record the value of label_tick when the value for register n is placed in
253 reg_last_set_value[n]. */
255 static int *reg_last_set_label;
257 /* Record the value of label_tick when an expression involving register n
258 is placed in reg_last_set_value. */
260 static int *reg_last_set_table_tick;
262 /* Set non-zero if references to register n in expressions should not be
265 static char *reg_last_set_invalid;
267 /* Incremented for each label. */
269 static int label_tick;
271 /* Some registers that are set more than once and used in more than one
272 basic block are nevertheless always set in similar ways. For example,
273 a QImode register may be loaded from memory in two places on a machine
274 where byte loads zero extend.
276 We record in the following array what we know about the nonzero
277 bits of a register, specifically which bits are known to be zero.
279 If an entry is zero, it means that we don't know anything special. */
281 static unsigned HOST_WIDE_INT *reg_nonzero_bits;
283 /* Mode used to compute significance in reg_nonzero_bits. It is the largest
284 integer mode that can fit in HOST_BITS_PER_WIDE_INT. */
286 static enum machine_mode nonzero_bits_mode;
288 /* Nonzero if we know that a register has some leading bits that are always
289 equal to the sign bit. */
291 static unsigned char *reg_sign_bit_copies;
293 /* Nonzero when reg_nonzero_bits and reg_sign_bit_copies can be safely used.
294 It is zero while computing them and after combine has completed. This
295 former test prevents propagating values based on previously set values,
296 which can be incorrect if a variable is modified in a loop. */
298 static int nonzero_sign_valid;
300 /* These arrays are maintained in parallel with reg_last_set_value
301 and are used to store the mode in which the register was last set,
302 the bits that were known to be zero when it was last set, and the
303 number of sign bits copies it was known to have when it was last set. */
305 static enum machine_mode *reg_last_set_mode;
306 static unsigned HOST_WIDE_INT *reg_last_set_nonzero_bits;
307 static char *reg_last_set_sign_bit_copies;
309 /* Record one modification to rtl structure
310 to be undone by storing old_contents into *where.
311 is_int is 1 if the contents are an int. */
317 union {rtx r; int i;} old_contents;
318 union {rtx *r; int *i;} where;
321 /* Record a bunch of changes to be undone, up to MAX_UNDO of them.
322 num_undo says how many are currently recorded.
324 other_insn is nonzero if we have modified some other insn in the process
325 of working on subst_insn. It must be verified too. */
334 static struct undobuf undobuf;
336 /* Number of times the pseudo being substituted for
337 was found and replaced. */
339 static int n_occurrences;
341 static void do_SUBST PARAMS ((rtx *, rtx));
342 static void do_SUBST_INT PARAMS ((int *, int));
343 static void init_reg_last_arrays PARAMS ((void));
344 static void setup_incoming_promotions PARAMS ((void));
345 static void set_nonzero_bits_and_sign_copies PARAMS ((rtx, rtx, void *));
346 static int cant_combine_insn_p PARAMS ((rtx));
347 static int can_combine_p PARAMS ((rtx, rtx, rtx, rtx, rtx *, rtx *));
348 static int sets_function_arg_p PARAMS ((rtx));
349 static int combinable_i3pat PARAMS ((rtx, rtx *, rtx, rtx, int, rtx *));
350 static int contains_muldiv PARAMS ((rtx));
351 static rtx try_combine PARAMS ((rtx, rtx, rtx, int *));
352 static void undo_all PARAMS ((void));
353 static void undo_commit PARAMS ((void));
354 static rtx *find_split_point PARAMS ((rtx *, rtx));
355 static rtx subst PARAMS ((rtx, rtx, rtx, int, int));
356 static rtx combine_simplify_rtx PARAMS ((rtx, enum machine_mode, int, int));
357 static rtx simplify_if_then_else PARAMS ((rtx));
358 static rtx simplify_set PARAMS ((rtx));
359 static rtx simplify_logical PARAMS ((rtx, int));
360 static rtx expand_compound_operation PARAMS ((rtx));
361 static rtx expand_field_assignment PARAMS ((rtx));
362 static rtx make_extraction PARAMS ((enum machine_mode, rtx, HOST_WIDE_INT,
363 rtx, unsigned HOST_WIDE_INT, int,
365 static rtx extract_left_shift PARAMS ((rtx, int));
366 static rtx make_compound_operation PARAMS ((rtx, enum rtx_code));
367 static int get_pos_from_mask PARAMS ((unsigned HOST_WIDE_INT,
368 unsigned HOST_WIDE_INT *));
369 static rtx force_to_mode PARAMS ((rtx, enum machine_mode,
370 unsigned HOST_WIDE_INT, rtx, int));
371 static rtx if_then_else_cond PARAMS ((rtx, rtx *, rtx *));
372 static rtx known_cond PARAMS ((rtx, enum rtx_code, rtx, rtx));
373 static int rtx_equal_for_field_assignment_p PARAMS ((rtx, rtx));
374 static rtx make_field_assignment PARAMS ((rtx));
375 static rtx apply_distributive_law PARAMS ((rtx));
376 static rtx simplify_and_const_int PARAMS ((rtx, enum machine_mode, rtx,
377 unsigned HOST_WIDE_INT));
378 static unsigned HOST_WIDE_INT nonzero_bits PARAMS ((rtx, enum machine_mode));
379 static unsigned int num_sign_bit_copies PARAMS ((rtx, enum machine_mode));
380 static int merge_outer_ops PARAMS ((enum rtx_code *, HOST_WIDE_INT *,
381 enum rtx_code, HOST_WIDE_INT,
382 enum machine_mode, int *));
383 static rtx simplify_shift_const PARAMS ((rtx, enum rtx_code, enum machine_mode,
385 static int recog_for_combine PARAMS ((rtx *, rtx, rtx *));
386 static rtx gen_lowpart_for_combine PARAMS ((enum machine_mode, rtx));
387 static rtx gen_binary PARAMS ((enum rtx_code, enum machine_mode,
389 static enum rtx_code simplify_comparison PARAMS ((enum rtx_code, rtx *, rtx *));
390 static void update_table_tick PARAMS ((rtx));
391 static void record_value_for_reg PARAMS ((rtx, rtx, rtx));
392 static void check_promoted_subreg PARAMS ((rtx, rtx));
393 static void record_dead_and_set_regs_1 PARAMS ((rtx, rtx, void *));
394 static void record_dead_and_set_regs PARAMS ((rtx));
395 static int get_last_value_validate PARAMS ((rtx *, rtx, int, int));
396 static rtx get_last_value PARAMS ((rtx));
397 static int use_crosses_set_p PARAMS ((rtx, int));
398 static void reg_dead_at_p_1 PARAMS ((rtx, rtx, void *));
399 static int reg_dead_at_p PARAMS ((rtx, rtx));
400 static void move_deaths PARAMS ((rtx, rtx, int, rtx, rtx *));
401 static int reg_bitfield_target_p PARAMS ((rtx, rtx));
402 static void distribute_notes PARAMS ((rtx, rtx, rtx, rtx, rtx, rtx));
403 static void distribute_links PARAMS ((rtx));
404 static void mark_used_regs_combine PARAMS ((rtx));
405 static int insn_cuid PARAMS ((rtx));
406 static void record_promoted_value PARAMS ((rtx, rtx));
407 static rtx reversed_comparison PARAMS ((rtx, enum machine_mode, rtx, rtx));
408 static enum rtx_code combine_reversed_comparison_code PARAMS ((rtx));
410 /* Substitute NEWVAL, an rtx expression, into INTO, a place in some
411 insn. The substitution can be undone by undo_all. If INTO is already
412 set to NEWVAL, do not record this change. Because computing NEWVAL might
413 also call SUBST, we have to compute it before we put anything into
417 do_SUBST (into, newval)
423 if (oldval == newval)
426 /* We'd like to catch as many invalid transformations here as
427 possible. Unfortunately, there are way too many mode changes
428 that are perfectly valid, so we'd waste too much effort for
429 little gain doing the checks here. Focus on catching invalid
430 transformations involving integer constants. */
431 if (GET_MODE_CLASS (GET_MODE (oldval)) == MODE_INT
432 && GET_CODE (newval) == CONST_INT)
434 /* Sanity check that we're replacing oldval with a CONST_INT
435 that is a valid sign-extension for the original mode. */
436 if (INTVAL (newval) != trunc_int_for_mode (INTVAL (newval),
440 /* Replacing the operand of a SUBREG or a ZERO_EXTEND with a
441 CONST_INT is not valid, because after the replacement, the
442 original mode would be gone. Unfortunately, we can't tell
443 when do_SUBST is called to replace the operand thereof, so we
444 perform this test on oldval instead, checking whether an
445 invalid replacement took place before we got here. */
446 if ((GET_CODE (oldval) == SUBREG
447 && GET_CODE (SUBREG_REG (oldval)) == CONST_INT)
448 || (GET_CODE (oldval) == ZERO_EXTEND
449 && GET_CODE (XEXP (oldval, 0)) == CONST_INT))
454 buf = undobuf.frees, undobuf.frees = buf->next;
456 buf = (struct undo *) xmalloc (sizeof (struct undo));
460 buf->old_contents.r = oldval;
463 buf->next = undobuf.undos, undobuf.undos = buf;
466 #define SUBST(INTO, NEWVAL) do_SUBST(&(INTO), (NEWVAL))
468 /* Similar to SUBST, but NEWVAL is an int expression. Note that substitution
469 for the value of a HOST_WIDE_INT value (including CONST_INT) is
473 do_SUBST_INT (into, newval)
479 if (oldval == newval)
483 buf = undobuf.frees, undobuf.frees = buf->next;
485 buf = (struct undo *) xmalloc (sizeof (struct undo));
489 buf->old_contents.i = oldval;
492 buf->next = undobuf.undos, undobuf.undos = buf;
495 #define SUBST_INT(INTO, NEWVAL) do_SUBST_INT(&(INTO), (NEWVAL))
497 /* Main entry point for combiner. F is the first insn of the function.
498 NREGS is the first unused pseudo-reg number.
500 Return non-zero if the combiner has turned an indirect jump
501 instruction into a direct jump. */
503 combine_instructions (f, nregs)
512 rtx links, nextlinks;
514 int new_direct_jump_p = 0;
516 combine_attempts = 0;
519 combine_successes = 0;
521 combine_max_regno = nregs;
523 reg_nonzero_bits = ((unsigned HOST_WIDE_INT *)
524 xcalloc (nregs, sizeof (unsigned HOST_WIDE_INT)));
526 = (unsigned char *) xcalloc (nregs, sizeof (unsigned char));
528 reg_last_death = (rtx *) xmalloc (nregs * sizeof (rtx));
529 reg_last_set = (rtx *) xmalloc (nregs * sizeof (rtx));
530 reg_last_set_value = (rtx *) xmalloc (nregs * sizeof (rtx));
531 reg_last_set_table_tick = (int *) xmalloc (nregs * sizeof (int));
532 reg_last_set_label = (int *) xmalloc (nregs * sizeof (int));
533 reg_last_set_invalid = (char *) xmalloc (nregs * sizeof (char));
535 = (enum machine_mode *) xmalloc (nregs * sizeof (enum machine_mode));
536 reg_last_set_nonzero_bits
537 = (unsigned HOST_WIDE_INT *) xmalloc (nregs * sizeof (HOST_WIDE_INT));
538 reg_last_set_sign_bit_copies
539 = (char *) xmalloc (nregs * sizeof (char));
541 init_reg_last_arrays ();
543 init_recog_no_volatile ();
545 /* Compute maximum uid value so uid_cuid can be allocated. */
547 for (insn = f, i = 0; insn; insn = NEXT_INSN (insn))
548 if (INSN_UID (insn) > i)
551 uid_cuid = (int *) xmalloc ((i + 1) * sizeof (int));
554 nonzero_bits_mode = mode_for_size (HOST_BITS_PER_WIDE_INT, MODE_INT, 0);
556 /* Don't use reg_nonzero_bits when computing it. This can cause problems
557 when, for example, we have j <<= 1 in a loop. */
559 nonzero_sign_valid = 0;
561 /* Compute the mapping from uids to cuids.
562 Cuids are numbers assigned to insns, like uids,
563 except that cuids increase monotonically through the code.
565 Scan all SETs and see if we can deduce anything about what
566 bits are known to be zero for some registers and how many copies
567 of the sign bit are known to exist for those registers.
569 Also set any known values so that we can use it while searching
570 for what bits are known to be set. */
574 /* We need to initialize it here, because record_dead_and_set_regs may call
576 subst_prev_insn = NULL_RTX;
578 setup_incoming_promotions ();
580 refresh_blocks = sbitmap_alloc (last_basic_block);
581 sbitmap_zero (refresh_blocks);
584 for (insn = f, i = 0; insn; insn = NEXT_INSN (insn))
586 uid_cuid[INSN_UID (insn)] = ++i;
592 note_stores (PATTERN (insn), set_nonzero_bits_and_sign_copies,
594 record_dead_and_set_regs (insn);
597 for (links = REG_NOTES (insn); links; links = XEXP (links, 1))
598 if (REG_NOTE_KIND (links) == REG_INC)
599 set_nonzero_bits_and_sign_copies (XEXP (links, 0), NULL_RTX,
604 if (GET_CODE (insn) == CODE_LABEL)
608 nonzero_sign_valid = 1;
610 /* Now scan all the insns in forward order. */
615 init_reg_last_arrays ();
616 setup_incoming_promotions ();
618 FOR_EACH_BB (this_basic_block)
620 for (insn = this_basic_block->head;
621 insn != NEXT_INSN (this_basic_block->end);
622 insn = next ? next : NEXT_INSN (insn))
626 if (GET_CODE (insn) == CODE_LABEL)
629 else if (INSN_P (insn))
631 /* See if we know about function return values before this
632 insn based upon SUBREG flags. */
633 check_promoted_subreg (insn, PATTERN (insn));
635 /* Try this insn with each insn it links back to. */
637 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
638 if ((next = try_combine (insn, XEXP (links, 0),
639 NULL_RTX, &new_direct_jump_p)) != 0)
642 /* Try each sequence of three linked insns ending with this one. */
644 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
646 rtx link = XEXP (links, 0);
648 /* If the linked insn has been replaced by a note, then there
649 is no point in pursuing this chain any further. */
650 if (GET_CODE (link) == NOTE)
653 for (nextlinks = LOG_LINKS (link);
655 nextlinks = XEXP (nextlinks, 1))
656 if ((next = try_combine (insn, link,
658 &new_direct_jump_p)) != 0)
663 /* Try to combine a jump insn that uses CC0
664 with a preceding insn that sets CC0, and maybe with its
665 logical predecessor as well.
666 This is how we make decrement-and-branch insns.
667 We need this special code because data flow connections
668 via CC0 do not get entered in LOG_LINKS. */
670 if (GET_CODE (insn) == JUMP_INSN
671 && (prev = prev_nonnote_insn (insn)) != 0
672 && GET_CODE (prev) == INSN
673 && sets_cc0_p (PATTERN (prev)))
675 if ((next = try_combine (insn, prev,
676 NULL_RTX, &new_direct_jump_p)) != 0)
679 for (nextlinks = LOG_LINKS (prev); nextlinks;
680 nextlinks = XEXP (nextlinks, 1))
681 if ((next = try_combine (insn, prev,
683 &new_direct_jump_p)) != 0)
687 /* Do the same for an insn that explicitly references CC0. */
688 if (GET_CODE (insn) == INSN
689 && (prev = prev_nonnote_insn (insn)) != 0
690 && GET_CODE (prev) == INSN
691 && sets_cc0_p (PATTERN (prev))
692 && GET_CODE (PATTERN (insn)) == SET
693 && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (insn))))
695 if ((next = try_combine (insn, prev,
696 NULL_RTX, &new_direct_jump_p)) != 0)
699 for (nextlinks = LOG_LINKS (prev); nextlinks;
700 nextlinks = XEXP (nextlinks, 1))
701 if ((next = try_combine (insn, prev,
703 &new_direct_jump_p)) != 0)
707 /* Finally, see if any of the insns that this insn links to
708 explicitly references CC0. If so, try this insn, that insn,
709 and its predecessor if it sets CC0. */
710 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
711 if (GET_CODE (XEXP (links, 0)) == INSN
712 && GET_CODE (PATTERN (XEXP (links, 0))) == SET
713 && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (XEXP (links, 0))))
714 && (prev = prev_nonnote_insn (XEXP (links, 0))) != 0
715 && GET_CODE (prev) == INSN
716 && sets_cc0_p (PATTERN (prev))
717 && (next = try_combine (insn, XEXP (links, 0),
718 prev, &new_direct_jump_p)) != 0)
722 /* Try combining an insn with two different insns whose results it
724 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
725 for (nextlinks = XEXP (links, 1); nextlinks;
726 nextlinks = XEXP (nextlinks, 1))
727 if ((next = try_combine (insn, XEXP (links, 0),
729 &new_direct_jump_p)) != 0)
732 if (GET_CODE (insn) != NOTE)
733 record_dead_and_set_regs (insn);
742 EXECUTE_IF_SET_IN_SBITMAP (refresh_blocks, 0, i,
743 BASIC_BLOCK (i)->flags |= BB_DIRTY);
744 new_direct_jump_p |= purge_all_dead_edges (0);
745 delete_noop_moves (f);
747 update_life_info_in_dirty_blocks (UPDATE_LIFE_GLOBAL_RM_NOTES,
748 PROP_DEATH_NOTES | PROP_SCAN_DEAD_CODE
749 | PROP_KILL_DEAD_CODE);
752 sbitmap_free (refresh_blocks);
753 free (reg_nonzero_bits);
754 free (reg_sign_bit_copies);
755 free (reg_last_death);
757 free (reg_last_set_value);
758 free (reg_last_set_table_tick);
759 free (reg_last_set_label);
760 free (reg_last_set_invalid);
761 free (reg_last_set_mode);
762 free (reg_last_set_nonzero_bits);
763 free (reg_last_set_sign_bit_copies);
767 struct undo *undo, *next;
768 for (undo = undobuf.frees; undo; undo = next)
776 total_attempts += combine_attempts;
777 total_merges += combine_merges;
778 total_extras += combine_extras;
779 total_successes += combine_successes;
781 nonzero_sign_valid = 0;
783 /* Make recognizer allow volatile MEMs again. */
786 return new_direct_jump_p;
789 /* Wipe the reg_last_xxx arrays in preparation for another pass. */
792 init_reg_last_arrays ()
794 unsigned int nregs = combine_max_regno;
796 memset ((char *) reg_last_death, 0, nregs * sizeof (rtx));
797 memset ((char *) reg_last_set, 0, nregs * sizeof (rtx));
798 memset ((char *) reg_last_set_value, 0, nregs * sizeof (rtx));
799 memset ((char *) reg_last_set_table_tick, 0, nregs * sizeof (int));
800 memset ((char *) reg_last_set_label, 0, nregs * sizeof (int));
801 memset (reg_last_set_invalid, 0, nregs * sizeof (char));
802 memset ((char *) reg_last_set_mode, 0, nregs * sizeof (enum machine_mode));
803 memset ((char *) reg_last_set_nonzero_bits, 0, nregs * sizeof (HOST_WIDE_INT));
804 memset (reg_last_set_sign_bit_copies, 0, nregs * sizeof (char));
807 /* Set up any promoted values for incoming argument registers. */
810 setup_incoming_promotions ()
812 #ifdef PROMOTE_FUNCTION_ARGS
815 enum machine_mode mode;
817 rtx first = get_insns ();
819 #ifndef OUTGOING_REGNO
820 #define OUTGOING_REGNO(N) N
822 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
823 /* Check whether this register can hold an incoming pointer
824 argument. FUNCTION_ARG_REGNO_P tests outgoing register
825 numbers, so translate if necessary due to register windows. */
826 if (FUNCTION_ARG_REGNO_P (OUTGOING_REGNO (regno))
827 && (reg = promoted_input_arg (regno, &mode, &unsignedp)) != 0)
830 (reg, first, gen_rtx_fmt_e ((unsignedp ? ZERO_EXTEND
833 gen_rtx_CLOBBER (mode, const0_rtx)));
838 /* Called via note_stores. If X is a pseudo that is narrower than
839 HOST_BITS_PER_WIDE_INT and is being set, record what bits are known zero.
841 If we are setting only a portion of X and we can't figure out what
842 portion, assume all bits will be used since we don't know what will
845 Similarly, set how many bits of X are known to be copies of the sign bit
846 at all locations in the function. This is the smallest number implied
850 set_nonzero_bits_and_sign_copies (x, set, data)
853 void *data ATTRIBUTE_UNUSED;
857 if (GET_CODE (x) == REG
858 && REGNO (x) >= FIRST_PSEUDO_REGISTER
859 /* If this register is undefined at the start of the file, we can't
860 say what its contents were. */
861 && ! REGNO_REG_SET_P (ENTRY_BLOCK_PTR->next_bb->global_live_at_start, REGNO (x))
862 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT)
864 if (set == 0 || GET_CODE (set) == CLOBBER)
866 reg_nonzero_bits[REGNO (x)] = GET_MODE_MASK (GET_MODE (x));
867 reg_sign_bit_copies[REGNO (x)] = 1;
871 /* If this is a complex assignment, see if we can convert it into a
872 simple assignment. */
873 set = expand_field_assignment (set);
875 /* If this is a simple assignment, or we have a paradoxical SUBREG,
876 set what we know about X. */
878 if (SET_DEST (set) == x
879 || (GET_CODE (SET_DEST (set)) == SUBREG
880 && (GET_MODE_SIZE (GET_MODE (SET_DEST (set)))
881 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (set)))))
882 && SUBREG_REG (SET_DEST (set)) == x))
884 rtx src = SET_SRC (set);
886 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
887 /* If X is narrower than a word and SRC is a non-negative
888 constant that would appear negative in the mode of X,
889 sign-extend it for use in reg_nonzero_bits because some
890 machines (maybe most) will actually do the sign-extension
891 and this is the conservative approach.
893 ??? For 2.5, try to tighten up the MD files in this regard
894 instead of this kludge. */
896 if (GET_MODE_BITSIZE (GET_MODE (x)) < BITS_PER_WORD
897 && GET_CODE (src) == CONST_INT
899 && 0 != (INTVAL (src)
901 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
902 src = GEN_INT (INTVAL (src)
903 | ((HOST_WIDE_INT) (-1)
904 << GET_MODE_BITSIZE (GET_MODE (x))));
907 /* Don't call nonzero_bits if it cannot change anything. */
908 if (reg_nonzero_bits[REGNO (x)] != ~(unsigned HOST_WIDE_INT) 0)
909 reg_nonzero_bits[REGNO (x)]
910 |= nonzero_bits (src, nonzero_bits_mode);
911 num = num_sign_bit_copies (SET_SRC (set), GET_MODE (x));
912 if (reg_sign_bit_copies[REGNO (x)] == 0
913 || reg_sign_bit_copies[REGNO (x)] > num)
914 reg_sign_bit_copies[REGNO (x)] = num;
918 reg_nonzero_bits[REGNO (x)] = GET_MODE_MASK (GET_MODE (x));
919 reg_sign_bit_copies[REGNO (x)] = 1;
924 /* See if INSN can be combined into I3. PRED and SUCC are optionally
925 insns that were previously combined into I3 or that will be combined
926 into the merger of INSN and I3.
928 Return 0 if the combination is not allowed for any reason.
930 If the combination is allowed, *PDEST will be set to the single
931 destination of INSN and *PSRC to the single source, and this function
935 can_combine_p (insn, i3, pred, succ, pdest, psrc)
938 rtx pred ATTRIBUTE_UNUSED;
943 rtx set = 0, src, dest;
948 int all_adjacent = (succ ? (next_active_insn (insn) == succ
949 && next_active_insn (succ) == i3)
950 : next_active_insn (insn) == i3);
952 /* Can combine only if previous insn is a SET of a REG, a SUBREG or CC0.
953 or a PARALLEL consisting of such a SET and CLOBBERs.
955 If INSN has CLOBBER parallel parts, ignore them for our processing.
956 By definition, these happen during the execution of the insn. When it
957 is merged with another insn, all bets are off. If they are, in fact,
958 needed and aren't also supplied in I3, they may be added by
959 recog_for_combine. Otherwise, it won't match.
961 We can also ignore a SET whose SET_DEST is mentioned in a REG_UNUSED
964 Get the source and destination of INSN. If more than one, can't
967 if (GET_CODE (PATTERN (insn)) == SET)
968 set = PATTERN (insn);
969 else if (GET_CODE (PATTERN (insn)) == PARALLEL
970 && GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == SET)
972 for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
974 rtx elt = XVECEXP (PATTERN (insn), 0, i);
976 switch (GET_CODE (elt))
978 /* This is important to combine floating point insns
981 /* Combining an isolated USE doesn't make sense.
982 We depend here on combinable_i3pat to reject them. */
983 /* The code below this loop only verifies that the inputs of
984 the SET in INSN do not change. We call reg_set_between_p
985 to verify that the REG in the USE does not change between
987 If the USE in INSN was for a pseudo register, the matching
988 insn pattern will likely match any register; combining this
989 with any other USE would only be safe if we knew that the
990 used registers have identical values, or if there was
991 something to tell them apart, e.g. different modes. For
992 now, we forgo such complicated tests and simply disallow
993 combining of USES of pseudo registers with any other USE. */
994 if (GET_CODE (XEXP (elt, 0)) == REG
995 && GET_CODE (PATTERN (i3)) == PARALLEL)
997 rtx i3pat = PATTERN (i3);
998 int i = XVECLEN (i3pat, 0) - 1;
999 unsigned int regno = REGNO (XEXP (elt, 0));
1003 rtx i3elt = XVECEXP (i3pat, 0, i);
1005 if (GET_CODE (i3elt) == USE
1006 && GET_CODE (XEXP (i3elt, 0)) == REG
1007 && (REGNO (XEXP (i3elt, 0)) == regno
1008 ? reg_set_between_p (XEXP (elt, 0),
1009 PREV_INSN (insn), i3)
1010 : regno >= FIRST_PSEUDO_REGISTER))
1017 /* We can ignore CLOBBERs. */
1022 /* Ignore SETs whose result isn't used but not those that
1023 have side-effects. */
1024 if (find_reg_note (insn, REG_UNUSED, SET_DEST (elt))
1025 && ! side_effects_p (elt))
1028 /* If we have already found a SET, this is a second one and
1029 so we cannot combine with this insn. */
1037 /* Anything else means we can't combine. */
1043 /* If SET_SRC is an ASM_OPERANDS we can't throw away these CLOBBERs,
1044 so don't do anything with it. */
1045 || GET_CODE (SET_SRC (set)) == ASM_OPERANDS)
1054 set = expand_field_assignment (set);
1055 src = SET_SRC (set), dest = SET_DEST (set);
1057 /* Don't eliminate a store in the stack pointer. */
1058 if (dest == stack_pointer_rtx
1059 /* If we couldn't eliminate a field assignment, we can't combine. */
1060 || GET_CODE (dest) == ZERO_EXTRACT || GET_CODE (dest) == STRICT_LOW_PART
1061 /* Don't combine with an insn that sets a register to itself if it has
1062 a REG_EQUAL note. This may be part of a REG_NO_CONFLICT sequence. */
1063 || (rtx_equal_p (src, dest) && find_reg_note (insn, REG_EQUAL, NULL_RTX))
1064 /* Can't merge an ASM_OPERANDS. */
1065 || GET_CODE (src) == ASM_OPERANDS
1066 /* Can't merge a function call. */
1067 || GET_CODE (src) == CALL
1068 /* Don't eliminate a function call argument. */
1069 || (GET_CODE (i3) == CALL_INSN
1070 && (find_reg_fusage (i3, USE, dest)
1071 || (GET_CODE (dest) == REG
1072 && REGNO (dest) < FIRST_PSEUDO_REGISTER
1073 && global_regs[REGNO (dest)])))
1074 /* Don't substitute into an incremented register. */
1075 || FIND_REG_INC_NOTE (i3, dest)
1076 || (succ && FIND_REG_INC_NOTE (succ, dest))
1078 /* Don't combine the end of a libcall into anything. */
1079 /* ??? This gives worse code, and appears to be unnecessary, since no
1080 pass after flow uses REG_LIBCALL/REG_RETVAL notes. Local-alloc does
1081 use REG_RETVAL notes for noconflict blocks, but other code here
1082 makes sure that those insns don't disappear. */
1083 || find_reg_note (insn, REG_RETVAL, NULL_RTX)
1085 /* Make sure that DEST is not used after SUCC but before I3. */
1086 || (succ && ! all_adjacent
1087 && reg_used_between_p (dest, succ, i3))
1088 /* Make sure that the value that is to be substituted for the register
1089 does not use any registers whose values alter in between. However,
1090 If the insns are adjacent, a use can't cross a set even though we
1091 think it might (this can happen for a sequence of insns each setting
1092 the same destination; reg_last_set of that register might point to
1093 a NOTE). If INSN has a REG_EQUIV note, the register is always
1094 equivalent to the memory so the substitution is valid even if there
1095 are intervening stores. Also, don't move a volatile asm or
1096 UNSPEC_VOLATILE across any other insns. */
1098 && (((GET_CODE (src) != MEM
1099 || ! find_reg_note (insn, REG_EQUIV, src))
1100 && use_crosses_set_p (src, INSN_CUID (insn)))
1101 || (GET_CODE (src) == ASM_OPERANDS && MEM_VOLATILE_P (src))
1102 || GET_CODE (src) == UNSPEC_VOLATILE))
1103 /* If there is a REG_NO_CONFLICT note for DEST in I3 or SUCC, we get
1104 better register allocation by not doing the combine. */
1105 || find_reg_note (i3, REG_NO_CONFLICT, dest)
1106 || (succ && find_reg_note (succ, REG_NO_CONFLICT, dest))
1107 /* Don't combine across a CALL_INSN, because that would possibly
1108 change whether the life span of some REGs crosses calls or not,
1109 and it is a pain to update that information.
1110 Exception: if source is a constant, moving it later can't hurt.
1111 Accept that special case, because it helps -fforce-addr a lot. */
1112 || (INSN_CUID (insn) < last_call_cuid && ! CONSTANT_P (src)))
1115 /* DEST must either be a REG or CC0. */
1116 if (GET_CODE (dest) == REG)
1118 /* If register alignment is being enforced for multi-word items in all
1119 cases except for parameters, it is possible to have a register copy
1120 insn referencing a hard register that is not allowed to contain the
1121 mode being copied and which would not be valid as an operand of most
1122 insns. Eliminate this problem by not combining with such an insn.
1124 Also, on some machines we don't want to extend the life of a hard
1127 if (GET_CODE (src) == REG
1128 && ((REGNO (dest) < FIRST_PSEUDO_REGISTER
1129 && ! HARD_REGNO_MODE_OK (REGNO (dest), GET_MODE (dest)))
1130 /* Don't extend the life of a hard register unless it is
1131 user variable (if we have few registers) or it can't
1132 fit into the desired register (meaning something special
1134 Also avoid substituting a return register into I3, because
1135 reload can't handle a conflict with constraints of other
1137 || (REGNO (src) < FIRST_PSEUDO_REGISTER
1138 && ! HARD_REGNO_MODE_OK (REGNO (src), GET_MODE (src)))))
1141 else if (GET_CODE (dest) != CC0)
1144 /* Don't substitute for a register intended as a clobberable operand.
1145 Similarly, don't substitute an expression containing a register that
1146 will be clobbered in I3. */
1147 if (GET_CODE (PATTERN (i3)) == PARALLEL)
1148 for (i = XVECLEN (PATTERN (i3), 0) - 1; i >= 0; i--)
1149 if (GET_CODE (XVECEXP (PATTERN (i3), 0, i)) == CLOBBER
1150 && (reg_overlap_mentioned_p (XEXP (XVECEXP (PATTERN (i3), 0, i), 0),
1152 || rtx_equal_p (XEXP (XVECEXP (PATTERN (i3), 0, i), 0), dest)))
1155 /* If INSN contains anything volatile, or is an `asm' (whether volatile
1156 or not), reject, unless nothing volatile comes between it and I3 */
1158 if (GET_CODE (src) == ASM_OPERANDS || volatile_refs_p (src))
1160 /* Make sure succ doesn't contain a volatile reference. */
1161 if (succ != 0 && volatile_refs_p (PATTERN (succ)))
1164 for (p = NEXT_INSN (insn); p != i3; p = NEXT_INSN (p))
1165 if (INSN_P (p) && p != succ && volatile_refs_p (PATTERN (p)))
1169 /* If INSN is an asm, and DEST is a hard register, reject, since it has
1170 to be an explicit register variable, and was chosen for a reason. */
1172 if (GET_CODE (src) == ASM_OPERANDS
1173 && GET_CODE (dest) == REG && REGNO (dest) < FIRST_PSEUDO_REGISTER)
1176 /* If there are any volatile insns between INSN and I3, reject, because
1177 they might affect machine state. */
1179 for (p = NEXT_INSN (insn); p != i3; p = NEXT_INSN (p))
1180 if (INSN_P (p) && p != succ && volatile_insn_p (PATTERN (p)))
1183 /* If INSN or I2 contains an autoincrement or autodecrement,
1184 make sure that register is not used between there and I3,
1185 and not already used in I3 either.
1186 Also insist that I3 not be a jump; if it were one
1187 and the incremented register were spilled, we would lose. */
1190 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
1191 if (REG_NOTE_KIND (link) == REG_INC
1192 && (GET_CODE (i3) == JUMP_INSN
1193 || reg_used_between_p (XEXP (link, 0), insn, i3)
1194 || reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i3))))
1199 /* Don't combine an insn that follows a CC0-setting insn.
1200 An insn that uses CC0 must not be separated from the one that sets it.
1201 We do, however, allow I2 to follow a CC0-setting insn if that insn
1202 is passed as I1; in that case it will be deleted also.
1203 We also allow combining in this case if all the insns are adjacent
1204 because that would leave the two CC0 insns adjacent as well.
1205 It would be more logical to test whether CC0 occurs inside I1 or I2,
1206 but that would be much slower, and this ought to be equivalent. */
1208 p = prev_nonnote_insn (insn);
1209 if (p && p != pred && GET_CODE (p) == INSN && sets_cc0_p (PATTERN (p))
1214 /* If we get here, we have passed all the tests and the combination is
1223 /* Check if PAT is an insn - or a part of it - used to set up an
1224 argument for a function in a hard register. */
1227 sets_function_arg_p (pat)
1233 switch (GET_CODE (pat))
1236 return sets_function_arg_p (PATTERN (pat));
1239 for (i = XVECLEN (pat, 0); --i >= 0;)
1240 if (sets_function_arg_p (XVECEXP (pat, 0, i)))
1246 inner_dest = SET_DEST (pat);
1247 while (GET_CODE (inner_dest) == STRICT_LOW_PART
1248 || GET_CODE (inner_dest) == SUBREG
1249 || GET_CODE (inner_dest) == ZERO_EXTRACT)
1250 inner_dest = XEXP (inner_dest, 0);
1252 return (GET_CODE (inner_dest) == REG
1253 && REGNO (inner_dest) < FIRST_PSEUDO_REGISTER
1254 && FUNCTION_ARG_REGNO_P (REGNO (inner_dest)));
1263 /* LOC is the location within I3 that contains its pattern or the component
1264 of a PARALLEL of the pattern. We validate that it is valid for combining.
1266 One problem is if I3 modifies its output, as opposed to replacing it
1267 entirely, we can't allow the output to contain I2DEST or I1DEST as doing
1268 so would produce an insn that is not equivalent to the original insns.
1272 (set (reg:DI 101) (reg:DI 100))
1273 (set (subreg:SI (reg:DI 101) 0) <foo>)
1275 This is NOT equivalent to:
1277 (parallel [(set (subreg:SI (reg:DI 100) 0) <foo>)
1278 (set (reg:DI 101) (reg:DI 100))])
1280 Not only does this modify 100 (in which case it might still be valid
1281 if 100 were dead in I2), it sets 101 to the ORIGINAL value of 100.
1283 We can also run into a problem if I2 sets a register that I1
1284 uses and I1 gets directly substituted into I3 (not via I2). In that
1285 case, we would be getting the wrong value of I2DEST into I3, so we
1286 must reject the combination. This case occurs when I2 and I1 both
1287 feed into I3, rather than when I1 feeds into I2, which feeds into I3.
1288 If I1_NOT_IN_SRC is non-zero, it means that finding I1 in the source
1289 of a SET must prevent combination from occurring.
1291 Before doing the above check, we first try to expand a field assignment
1292 into a set of logical operations.
1294 If PI3_DEST_KILLED is non-zero, it is a pointer to a location in which
1295 we place a register that is both set and used within I3. If more than one
1296 such register is detected, we fail.
1298 Return 1 if the combination is valid, zero otherwise. */
1301 combinable_i3pat (i3, loc, i2dest, i1dest, i1_not_in_src, pi3dest_killed)
1307 rtx *pi3dest_killed;
1311 if (GET_CODE (x) == SET)
1313 rtx set = expand_field_assignment (x);
1314 rtx dest = SET_DEST (set);
1315 rtx src = SET_SRC (set);
1316 rtx inner_dest = dest;
1319 rtx inner_src = src;
1324 while (GET_CODE (inner_dest) == STRICT_LOW_PART
1325 || GET_CODE (inner_dest) == SUBREG
1326 || GET_CODE (inner_dest) == ZERO_EXTRACT)
1327 inner_dest = XEXP (inner_dest, 0);
1329 /* We probably don't need this any more now that LIMIT_RELOAD_CLASS
1332 while (GET_CODE (inner_src) == STRICT_LOW_PART
1333 || GET_CODE (inner_src) == SUBREG
1334 || GET_CODE (inner_src) == ZERO_EXTRACT)
1335 inner_src = XEXP (inner_src, 0);
1337 /* If it is better that two different modes keep two different pseudos,
1338 avoid combining them. This avoids producing the following pattern
1340 (set (subreg:SI (reg/v:QI 21) 0)
1341 (lshiftrt:SI (reg/v:SI 20)
1343 If that were made, reload could not handle the pair of
1344 reg 20/21, since it would try to get any GENERAL_REGS
1345 but some of them don't handle QImode. */
1347 if (rtx_equal_p (inner_src, i2dest)
1348 && GET_CODE (inner_dest) == REG
1349 && ! MODES_TIEABLE_P (GET_MODE (i2dest), GET_MODE (inner_dest)))
1353 /* Check for the case where I3 modifies its output, as
1355 if ((inner_dest != dest
1356 && (reg_overlap_mentioned_p (i2dest, inner_dest)
1357 || (i1dest && reg_overlap_mentioned_p (i1dest, inner_dest))))
1359 /* This is the same test done in can_combine_p except we can't test
1360 all_adjacent; we don't have to, since this instruction will stay
1361 in place, thus we are not considering increasing the lifetime of
1364 Also, if this insn sets a function argument, combining it with
1365 something that might need a spill could clobber a previous
1366 function argument; the all_adjacent test in can_combine_p also
1367 checks this; here, we do a more specific test for this case. */
1369 || (GET_CODE (inner_dest) == REG
1370 && REGNO (inner_dest) < FIRST_PSEUDO_REGISTER
1371 && (! HARD_REGNO_MODE_OK (REGNO (inner_dest),
1372 GET_MODE (inner_dest))))
1373 || (i1_not_in_src && reg_overlap_mentioned_p (i1dest, src)))
1376 /* If DEST is used in I3, it is being killed in this insn,
1377 so record that for later.
1378 Never add REG_DEAD notes for the FRAME_POINTER_REGNUM or the
1379 STACK_POINTER_REGNUM, since these are always considered to be
1380 live. Similarly for ARG_POINTER_REGNUM if it is fixed. */
1381 if (pi3dest_killed && GET_CODE (dest) == REG
1382 && reg_referenced_p (dest, PATTERN (i3))
1383 && REGNO (dest) != FRAME_POINTER_REGNUM
1384 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
1385 && REGNO (dest) != HARD_FRAME_POINTER_REGNUM
1387 #if ARG_POINTER_REGNUM != FRAME_POINTER_REGNUM
1388 && (REGNO (dest) != ARG_POINTER_REGNUM
1389 || ! fixed_regs [REGNO (dest)])
1391 && REGNO (dest) != STACK_POINTER_REGNUM)
1393 if (*pi3dest_killed)
1396 *pi3dest_killed = dest;
1400 else if (GET_CODE (x) == PARALLEL)
1404 for (i = 0; i < XVECLEN (x, 0); i++)
1405 if (! combinable_i3pat (i3, &XVECEXP (x, 0, i), i2dest, i1dest,
1406 i1_not_in_src, pi3dest_killed))
1413 /* Return 1 if X is an arithmetic expression that contains a multiplication
1414 and division. We don't count multiplications by powers of two here. */
1420 switch (GET_CODE (x))
1422 case MOD: case DIV: case UMOD: case UDIV:
1426 return ! (GET_CODE (XEXP (x, 1)) == CONST_INT
1427 && exact_log2 (INTVAL (XEXP (x, 1))) >= 0);
1429 switch (GET_RTX_CLASS (GET_CODE (x)))
1431 case 'c': case '<': case '2':
1432 return contains_muldiv (XEXP (x, 0))
1433 || contains_muldiv (XEXP (x, 1));
1436 return contains_muldiv (XEXP (x, 0));
1444 /* Determine whether INSN can be used in a combination. Return nonzero if
1445 not. This is used in try_combine to detect early some cases where we
1446 can't perform combinations. */
1449 cant_combine_insn_p (insn)
1455 /* If this isn't really an insn, we can't do anything.
1456 This can occur when flow deletes an insn that it has merged into an
1457 auto-increment address. */
1458 if (! INSN_P (insn))
1461 /* Never combine loads and stores involving hard regs. The register
1462 allocator can usually handle such reg-reg moves by tying. If we allow
1463 the combiner to make substitutions of hard regs, we risk aborting in
1464 reload on machines that have SMALL_REGISTER_CLASSES.
1465 As an exception, we allow combinations involving fixed regs; these are
1466 not available to the register allocator so there's no risk involved. */
1468 set = single_set (insn);
1471 src = SET_SRC (set);
1472 dest = SET_DEST (set);
1473 if (GET_CODE (src) == SUBREG)
1474 src = SUBREG_REG (src);
1475 if (GET_CODE (dest) == SUBREG)
1476 dest = SUBREG_REG (dest);
1477 if (REG_P (src) && REG_P (dest)
1478 && ((REGNO (src) < FIRST_PSEUDO_REGISTER
1479 && ! fixed_regs[REGNO (src)])
1480 || (REGNO (dest) < FIRST_PSEUDO_REGISTER
1481 && ! fixed_regs[REGNO (dest)])))
1487 /* Try to combine the insns I1 and I2 into I3.
1488 Here I1 and I2 appear earlier than I3.
1489 I1 can be zero; then we combine just I2 into I3.
1491 If we are combining three insns and the resulting insn is not recognized,
1492 try splitting it into two insns. If that happens, I2 and I3 are retained
1493 and I1 is pseudo-deleted by turning it into a NOTE. Otherwise, I1 and I2
1496 Return 0 if the combination does not work. Then nothing is changed.
1497 If we did the combination, return the insn at which combine should
1500 Set NEW_DIRECT_JUMP_P to a non-zero value if try_combine creates a
1501 new direct jump instruction. */
1504 try_combine (i3, i2, i1, new_direct_jump_p)
1506 int *new_direct_jump_p;
1508 /* New patterns for I3 and I2, respectively. */
1509 rtx newpat, newi2pat = 0;
1510 int substed_i2 = 0, substed_i1 = 0;
1511 /* Indicates need to preserve SET in I1 or I2 in I3 if it is not dead. */
1512 int added_sets_1, added_sets_2;
1513 /* Total number of SETs to put into I3. */
1515 /* Nonzero is I2's body now appears in I3. */
1517 /* INSN_CODEs for new I3, new I2, and user of condition code. */
1518 int insn_code_number, i2_code_number = 0, other_code_number = 0;
1519 /* Contains I3 if the destination of I3 is used in its source, which means
1520 that the old life of I3 is being killed. If that usage is placed into
1521 I2 and not in I3, a REG_DEAD note must be made. */
1522 rtx i3dest_killed = 0;
1523 /* SET_DEST and SET_SRC of I2 and I1. */
1524 rtx i2dest, i2src, i1dest = 0, i1src = 0;
1525 /* PATTERN (I2), or a copy of it in certain cases. */
1527 /* Indicates if I2DEST or I1DEST is in I2SRC or I1_SRC. */
1528 int i2dest_in_i2src = 0, i1dest_in_i1src = 0, i2dest_in_i1src = 0;
1529 int i1_feeds_i3 = 0;
1530 /* Notes that must be added to REG_NOTES in I3 and I2. */
1531 rtx new_i3_notes, new_i2_notes;
1532 /* Notes that we substituted I3 into I2 instead of the normal case. */
1533 int i3_subst_into_i2 = 0;
1534 /* Notes that I1, I2 or I3 is a MULT operation. */
1542 /* Exit early if one of the insns involved can't be used for
1544 if (cant_combine_insn_p (i3)
1545 || cant_combine_insn_p (i2)
1546 || (i1 && cant_combine_insn_p (i1))
1547 /* We also can't do anything if I3 has a
1548 REG_LIBCALL note since we don't want to disrupt the contiguity of a
1551 /* ??? This gives worse code, and appears to be unnecessary, since no
1552 pass after flow uses REG_LIBCALL/REG_RETVAL notes. */
1553 || find_reg_note (i3, REG_LIBCALL, NULL_RTX)
1559 undobuf.other_insn = 0;
1561 /* Reset the hard register usage information. */
1562 CLEAR_HARD_REG_SET (newpat_used_regs);
1564 /* If I1 and I2 both feed I3, they can be in any order. To simplify the
1565 code below, set I1 to be the earlier of the two insns. */
1566 if (i1 && INSN_CUID (i1) > INSN_CUID (i2))
1567 temp = i1, i1 = i2, i2 = temp;
1569 added_links_insn = 0;
1571 /* First check for one important special-case that the code below will
1572 not handle. Namely, the case where I1 is zero, I2 is a PARALLEL
1573 and I3 is a SET whose SET_SRC is a SET_DEST in I2. In that case,
1574 we may be able to replace that destination with the destination of I3.
1575 This occurs in the common code where we compute both a quotient and
1576 remainder into a structure, in which case we want to do the computation
1577 directly into the structure to avoid register-register copies.
1579 Note that this case handles both multiple sets in I2 and also
1580 cases where I2 has a number of CLOBBER or PARALLELs.
1582 We make very conservative checks below and only try to handle the
1583 most common cases of this. For example, we only handle the case
1584 where I2 and I3 are adjacent to avoid making difficult register
1587 if (i1 == 0 && GET_CODE (i3) == INSN && GET_CODE (PATTERN (i3)) == SET
1588 && GET_CODE (SET_SRC (PATTERN (i3))) == REG
1589 && REGNO (SET_SRC (PATTERN (i3))) >= FIRST_PSEUDO_REGISTER
1590 && find_reg_note (i3, REG_DEAD, SET_SRC (PATTERN (i3)))
1591 && GET_CODE (PATTERN (i2)) == PARALLEL
1592 && ! side_effects_p (SET_DEST (PATTERN (i3)))
1593 /* If the dest of I3 is a ZERO_EXTRACT or STRICT_LOW_PART, the code
1594 below would need to check what is inside (and reg_overlap_mentioned_p
1595 doesn't support those codes anyway). Don't allow those destinations;
1596 the resulting insn isn't likely to be recognized anyway. */
1597 && GET_CODE (SET_DEST (PATTERN (i3))) != ZERO_EXTRACT
1598 && GET_CODE (SET_DEST (PATTERN (i3))) != STRICT_LOW_PART
1599 && ! reg_overlap_mentioned_p (SET_SRC (PATTERN (i3)),
1600 SET_DEST (PATTERN (i3)))
1601 && next_real_insn (i2) == i3)
1603 rtx p2 = PATTERN (i2);
1605 /* Make sure that the destination of I3,
1606 which we are going to substitute into one output of I2,
1607 is not used within another output of I2. We must avoid making this:
1608 (parallel [(set (mem (reg 69)) ...)
1609 (set (reg 69) ...)])
1610 which is not well-defined as to order of actions.
1611 (Besides, reload can't handle output reloads for this.)
1613 The problem can also happen if the dest of I3 is a memory ref,
1614 if another dest in I2 is an indirect memory ref. */
1615 for (i = 0; i < XVECLEN (p2, 0); i++)
1616 if ((GET_CODE (XVECEXP (p2, 0, i)) == SET
1617 || GET_CODE (XVECEXP (p2, 0, i)) == CLOBBER)
1618 && reg_overlap_mentioned_p (SET_DEST (PATTERN (i3)),
1619 SET_DEST (XVECEXP (p2, 0, i))))
1622 if (i == XVECLEN (p2, 0))
1623 for (i = 0; i < XVECLEN (p2, 0); i++)
1624 if ((GET_CODE (XVECEXP (p2, 0, i)) == SET
1625 || GET_CODE (XVECEXP (p2, 0, i)) == CLOBBER)
1626 && SET_DEST (XVECEXP (p2, 0, i)) == SET_SRC (PATTERN (i3)))
1631 subst_low_cuid = INSN_CUID (i2);
1633 added_sets_2 = added_sets_1 = 0;
1634 i2dest = SET_SRC (PATTERN (i3));
1636 /* Replace the dest in I2 with our dest and make the resulting
1637 insn the new pattern for I3. Then skip to where we
1638 validate the pattern. Everything was set up above. */
1639 SUBST (SET_DEST (XVECEXP (p2, 0, i)),
1640 SET_DEST (PATTERN (i3)));
1643 i3_subst_into_i2 = 1;
1644 goto validate_replacement;
1648 /* If I2 is setting a double-word pseudo to a constant and I3 is setting
1649 one of those words to another constant, merge them by making a new
1652 && (temp = single_set (i2)) != 0
1653 && (GET_CODE (SET_SRC (temp)) == CONST_INT
1654 || GET_CODE (SET_SRC (temp)) == CONST_DOUBLE)
1655 && GET_CODE (SET_DEST (temp)) == REG
1656 && GET_MODE_CLASS (GET_MODE (SET_DEST (temp))) == MODE_INT
1657 && GET_MODE_SIZE (GET_MODE (SET_DEST (temp))) == 2 * UNITS_PER_WORD
1658 && GET_CODE (PATTERN (i3)) == SET
1659 && GET_CODE (SET_DEST (PATTERN (i3))) == SUBREG
1660 && SUBREG_REG (SET_DEST (PATTERN (i3))) == SET_DEST (temp)
1661 && GET_MODE_CLASS (GET_MODE (SET_DEST (PATTERN (i3)))) == MODE_INT
1662 && GET_MODE_SIZE (GET_MODE (SET_DEST (PATTERN (i3)))) == UNITS_PER_WORD
1663 && GET_CODE (SET_SRC (PATTERN (i3))) == CONST_INT)
1665 HOST_WIDE_INT lo, hi;
1667 if (GET_CODE (SET_SRC (temp)) == CONST_INT)
1668 lo = INTVAL (SET_SRC (temp)), hi = lo < 0 ? -1 : 0;
1671 lo = CONST_DOUBLE_LOW (SET_SRC (temp));
1672 hi = CONST_DOUBLE_HIGH (SET_SRC (temp));
1675 if (subreg_lowpart_p (SET_DEST (PATTERN (i3))))
1677 /* We don't handle the case of the target word being wider
1678 than a host wide int. */
1679 if (HOST_BITS_PER_WIDE_INT < BITS_PER_WORD)
1682 lo &= ~(UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD (1) - 1);
1683 lo |= (INTVAL (SET_SRC (PATTERN (i3)))
1684 & (UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD (1) - 1));
1686 else if (HOST_BITS_PER_WIDE_INT == BITS_PER_WORD)
1687 hi = INTVAL (SET_SRC (PATTERN (i3)));
1688 else if (HOST_BITS_PER_WIDE_INT >= 2 * BITS_PER_WORD)
1690 int sign = -(int) ((unsigned HOST_WIDE_INT) lo
1691 >> (HOST_BITS_PER_WIDE_INT - 1));
1693 lo &= ~ (UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD
1694 (UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD (1) - 1));
1695 lo |= (UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD
1696 (INTVAL (SET_SRC (PATTERN (i3)))));
1698 hi = lo < 0 ? -1 : 0;
1701 /* We don't handle the case of the higher word not fitting
1702 entirely in either hi or lo. */
1707 subst_low_cuid = INSN_CUID (i2);
1708 added_sets_2 = added_sets_1 = 0;
1709 i2dest = SET_DEST (temp);
1711 SUBST (SET_SRC (temp),
1712 immed_double_const (lo, hi, GET_MODE (SET_DEST (temp))));
1714 newpat = PATTERN (i2);
1715 goto validate_replacement;
1719 /* If we have no I1 and I2 looks like:
1720 (parallel [(set (reg:CC X) (compare:CC OP (const_int 0)))
1722 make up a dummy I1 that is
1725 (set (reg:CC X) (compare:CC Y (const_int 0)))
1727 (We can ignore any trailing CLOBBERs.)
1729 This undoes a previous combination and allows us to match a branch-and-
1732 if (i1 == 0 && GET_CODE (PATTERN (i2)) == PARALLEL
1733 && XVECLEN (PATTERN (i2), 0) >= 2
1734 && GET_CODE (XVECEXP (PATTERN (i2), 0, 0)) == SET
1735 && (GET_MODE_CLASS (GET_MODE (SET_DEST (XVECEXP (PATTERN (i2), 0, 0))))
1737 && GET_CODE (SET_SRC (XVECEXP (PATTERN (i2), 0, 0))) == COMPARE
1738 && XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 1) == const0_rtx
1739 && GET_CODE (XVECEXP (PATTERN (i2), 0, 1)) == SET
1740 && GET_CODE (SET_DEST (XVECEXP (PATTERN (i2), 0, 1))) == REG
1741 && rtx_equal_p (XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 0),
1742 SET_SRC (XVECEXP (PATTERN (i2), 0, 1))))
1744 for (i = XVECLEN (PATTERN (i2), 0) - 1; i >= 2; i--)
1745 if (GET_CODE (XVECEXP (PATTERN (i2), 0, i)) != CLOBBER)
1750 /* We make I1 with the same INSN_UID as I2. This gives it
1751 the same INSN_CUID for value tracking. Our fake I1 will
1752 never appear in the insn stream so giving it the same INSN_UID
1753 as I2 will not cause a problem. */
1755 subst_prev_insn = i1
1756 = gen_rtx_INSN (VOIDmode, INSN_UID (i2), NULL_RTX, i2,
1757 BLOCK_FOR_INSN (i2), INSN_SCOPE (i2),
1758 XVECEXP (PATTERN (i2), 0, 1), -1, NULL_RTX,
1761 SUBST (PATTERN (i2), XVECEXP (PATTERN (i2), 0, 0));
1762 SUBST (XEXP (SET_SRC (PATTERN (i2)), 0),
1763 SET_DEST (PATTERN (i1)));
1768 /* Verify that I2 and I1 are valid for combining. */
1769 if (! can_combine_p (i2, i3, i1, NULL_RTX, &i2dest, &i2src)
1770 || (i1 && ! can_combine_p (i1, i3, NULL_RTX, i2, &i1dest, &i1src)))
1776 /* Record whether I2DEST is used in I2SRC and similarly for the other
1777 cases. Knowing this will help in register status updating below. */
1778 i2dest_in_i2src = reg_overlap_mentioned_p (i2dest, i2src);
1779 i1dest_in_i1src = i1 && reg_overlap_mentioned_p (i1dest, i1src);
1780 i2dest_in_i1src = i1 && reg_overlap_mentioned_p (i2dest, i1src);
1782 /* See if I1 directly feeds into I3. It does if I1DEST is not used
1784 i1_feeds_i3 = i1 && ! reg_overlap_mentioned_p (i1dest, i2src);
1786 /* Ensure that I3's pattern can be the destination of combines. */
1787 if (! combinable_i3pat (i3, &PATTERN (i3), i2dest, i1dest,
1788 i1 && i2dest_in_i1src && i1_feeds_i3,
1795 /* See if any of the insns is a MULT operation. Unless one is, we will
1796 reject a combination that is, since it must be slower. Be conservative
1798 if (GET_CODE (i2src) == MULT
1799 || (i1 != 0 && GET_CODE (i1src) == MULT)
1800 || (GET_CODE (PATTERN (i3)) == SET
1801 && GET_CODE (SET_SRC (PATTERN (i3))) == MULT))
1804 /* If I3 has an inc, then give up if I1 or I2 uses the reg that is inc'd.
1805 We used to do this EXCEPT in one case: I3 has a post-inc in an
1806 output operand. However, that exception can give rise to insns like
1808 which is a famous insn on the PDP-11 where the value of r3 used as the
1809 source was model-dependent. Avoid this sort of thing. */
1812 if (!(GET_CODE (PATTERN (i3)) == SET
1813 && GET_CODE (SET_SRC (PATTERN (i3))) == REG
1814 && GET_CODE (SET_DEST (PATTERN (i3))) == MEM
1815 && (GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_INC
1816 || GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_DEC)))
1817 /* It's not the exception. */
1820 for (link = REG_NOTES (i3); link; link = XEXP (link, 1))
1821 if (REG_NOTE_KIND (link) == REG_INC
1822 && (reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i2))
1824 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i1)))))
1831 /* See if the SETs in I1 or I2 need to be kept around in the merged
1832 instruction: whenever the value set there is still needed past I3.
1833 For the SETs in I2, this is easy: we see if I2DEST dies or is set in I3.
1835 For the SET in I1, we have two cases: If I1 and I2 independently
1836 feed into I3, the set in I1 needs to be kept around if I1DEST dies
1837 or is set in I3. Otherwise (if I1 feeds I2 which feeds I3), the set
1838 in I1 needs to be kept around unless I1DEST dies or is set in either
1839 I2 or I3. We can distinguish these cases by seeing if I2SRC mentions
1840 I1DEST. If so, we know I1 feeds into I2. */
1842 added_sets_2 = ! dead_or_set_p (i3, i2dest);
1845 = i1 && ! (i1_feeds_i3 ? dead_or_set_p (i3, i1dest)
1846 : (dead_or_set_p (i3, i1dest) || dead_or_set_p (i2, i1dest)));
1848 /* If the set in I2 needs to be kept around, we must make a copy of
1849 PATTERN (I2), so that when we substitute I1SRC for I1DEST in
1850 PATTERN (I2), we are only substituting for the original I1DEST, not into
1851 an already-substituted copy. This also prevents making self-referential
1852 rtx. If I2 is a PARALLEL, we just need the piece that assigns I2SRC to
1855 i2pat = (GET_CODE (PATTERN (i2)) == PARALLEL
1856 ? gen_rtx_SET (VOIDmode, i2dest, i2src)
1860 i2pat = copy_rtx (i2pat);
1864 /* Substitute in the latest insn for the regs set by the earlier ones. */
1866 maxreg = max_reg_num ();
1870 /* It is possible that the source of I2 or I1 may be performing an
1871 unneeded operation, such as a ZERO_EXTEND of something that is known
1872 to have the high part zero. Handle that case by letting subst look at
1873 the innermost one of them.
1875 Another way to do this would be to have a function that tries to
1876 simplify a single insn instead of merging two or more insns. We don't
1877 do this because of the potential of infinite loops and because
1878 of the potential extra memory required. However, doing it the way
1879 we are is a bit of a kludge and doesn't catch all cases.
1881 But only do this if -fexpensive-optimizations since it slows things down
1882 and doesn't usually win. */
1884 if (flag_expensive_optimizations)
1886 /* Pass pc_rtx so no substitutions are done, just simplifications.
1887 The cases that we are interested in here do not involve the few
1888 cases were is_replaced is checked. */
1891 subst_low_cuid = INSN_CUID (i1);
1892 i1src = subst (i1src, pc_rtx, pc_rtx, 0, 0);
1896 subst_low_cuid = INSN_CUID (i2);
1897 i2src = subst (i2src, pc_rtx, pc_rtx, 0, 0);
1902 /* Many machines that don't use CC0 have insns that can both perform an
1903 arithmetic operation and set the condition code. These operations will
1904 be represented as a PARALLEL with the first element of the vector
1905 being a COMPARE of an arithmetic operation with the constant zero.
1906 The second element of the vector will set some pseudo to the result
1907 of the same arithmetic operation. If we simplify the COMPARE, we won't
1908 match such a pattern and so will generate an extra insn. Here we test
1909 for this case, where both the comparison and the operation result are
1910 needed, and make the PARALLEL by just replacing I2DEST in I3SRC with
1911 I2SRC. Later we will make the PARALLEL that contains I2. */
1913 if (i1 == 0 && added_sets_2 && GET_CODE (PATTERN (i3)) == SET
1914 && GET_CODE (SET_SRC (PATTERN (i3))) == COMPARE
1915 && XEXP (SET_SRC (PATTERN (i3)), 1) == const0_rtx
1916 && rtx_equal_p (XEXP (SET_SRC (PATTERN (i3)), 0), i2dest))
1918 #ifdef EXTRA_CC_MODES
1920 enum machine_mode compare_mode;
1923 newpat = PATTERN (i3);
1924 SUBST (XEXP (SET_SRC (newpat), 0), i2src);
1928 #ifdef EXTRA_CC_MODES
1929 /* See if a COMPARE with the operand we substituted in should be done
1930 with the mode that is currently being used. If not, do the same
1931 processing we do in `subst' for a SET; namely, if the destination
1932 is used only once, try to replace it with a register of the proper
1933 mode and also replace the COMPARE. */
1934 if (undobuf.other_insn == 0
1935 && (cc_use = find_single_use (SET_DEST (newpat), i3,
1936 &undobuf.other_insn))
1937 && ((compare_mode = SELECT_CC_MODE (GET_CODE (*cc_use),
1939 != GET_MODE (SET_DEST (newpat))))
1941 unsigned int regno = REGNO (SET_DEST (newpat));
1942 rtx new_dest = gen_rtx_REG (compare_mode, regno);
1944 if (regno < FIRST_PSEUDO_REGISTER
1945 || (REG_N_SETS (regno) == 1 && ! added_sets_2
1946 && ! REG_USERVAR_P (SET_DEST (newpat))))
1948 if (regno >= FIRST_PSEUDO_REGISTER)
1949 SUBST (regno_reg_rtx[regno], new_dest);
1951 SUBST (SET_DEST (newpat), new_dest);
1952 SUBST (XEXP (*cc_use, 0), new_dest);
1953 SUBST (SET_SRC (newpat),
1954 gen_rtx_COMPARE (compare_mode, i2src, const0_rtx));
1957 undobuf.other_insn = 0;
1964 n_occurrences = 0; /* `subst' counts here */
1966 /* If I1 feeds into I2 (not into I3) and I1DEST is in I1SRC, we
1967 need to make a unique copy of I2SRC each time we substitute it
1968 to avoid self-referential rtl. */
1970 subst_low_cuid = INSN_CUID (i2);
1971 newpat = subst (PATTERN (i3), i2dest, i2src, 0,
1972 ! i1_feeds_i3 && i1dest_in_i1src);
1975 /* Record whether i2's body now appears within i3's body. */
1976 i2_is_used = n_occurrences;
1979 /* If we already got a failure, don't try to do more. Otherwise,
1980 try to substitute in I1 if we have it. */
1982 if (i1 && GET_CODE (newpat) != CLOBBER)
1984 /* Before we can do this substitution, we must redo the test done
1985 above (see detailed comments there) that ensures that I1DEST
1986 isn't mentioned in any SETs in NEWPAT that are field assignments. */
1988 if (! combinable_i3pat (NULL_RTX, &newpat, i1dest, NULL_RTX,
1996 subst_low_cuid = INSN_CUID (i1);
1997 newpat = subst (newpat, i1dest, i1src, 0, 0);
2001 /* Fail if an autoincrement side-effect has been duplicated. Be careful
2002 to count all the ways that I2SRC and I1SRC can be used. */
2003 if ((FIND_REG_INC_NOTE (i2, NULL_RTX) != 0
2004 && i2_is_used + added_sets_2 > 1)
2005 || (i1 != 0 && FIND_REG_INC_NOTE (i1, NULL_RTX) != 0
2006 && (n_occurrences + added_sets_1 + (added_sets_2 && ! i1_feeds_i3)
2008 /* Fail if we tried to make a new register (we used to abort, but there's
2009 really no reason to). */
2010 || max_reg_num () != maxreg
2011 /* Fail if we couldn't do something and have a CLOBBER. */
2012 || GET_CODE (newpat) == CLOBBER
2013 /* Fail if this new pattern is a MULT and we didn't have one before
2014 at the outer level. */
2015 || (GET_CODE (newpat) == SET && GET_CODE (SET_SRC (newpat)) == MULT
2022 /* If the actions of the earlier insns must be kept
2023 in addition to substituting them into the latest one,
2024 we must make a new PARALLEL for the latest insn
2025 to hold additional the SETs. */
2027 if (added_sets_1 || added_sets_2)
2031 if (GET_CODE (newpat) == PARALLEL)
2033 rtvec old = XVEC (newpat, 0);
2034 total_sets = XVECLEN (newpat, 0) + added_sets_1 + added_sets_2;
2035 newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (total_sets));
2036 memcpy (XVEC (newpat, 0)->elem, &old->elem[0],
2037 sizeof (old->elem[0]) * old->num_elem);
2042 total_sets = 1 + added_sets_1 + added_sets_2;
2043 newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (total_sets));
2044 XVECEXP (newpat, 0, 0) = old;
2048 XVECEXP (newpat, 0, --total_sets)
2049 = (GET_CODE (PATTERN (i1)) == PARALLEL
2050 ? gen_rtx_SET (VOIDmode, i1dest, i1src) : PATTERN (i1));
2054 /* If there is no I1, use I2's body as is. We used to also not do
2055 the subst call below if I2 was substituted into I3,
2056 but that could lose a simplification. */
2058 XVECEXP (newpat, 0, --total_sets) = i2pat;
2060 /* See comment where i2pat is assigned. */
2061 XVECEXP (newpat, 0, --total_sets)
2062 = subst (i2pat, i1dest, i1src, 0, 0);
2066 /* We come here when we are replacing a destination in I2 with the
2067 destination of I3. */
2068 validate_replacement:
2070 /* Note which hard regs this insn has as inputs. */
2071 mark_used_regs_combine (newpat);
2073 /* Is the result of combination a valid instruction? */
2074 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2076 /* If the result isn't valid, see if it is a PARALLEL of two SETs where
2077 the second SET's destination is a register that is unused. In that case,
2078 we just need the first SET. This can occur when simplifying a divmod
2079 insn. We *must* test for this case here because the code below that
2080 splits two independent SETs doesn't handle this case correctly when it
2081 updates the register status. Also check the case where the first
2082 SET's destination is unused. That would not cause incorrect code, but
2083 does cause an unneeded insn to remain. */
2085 if (insn_code_number < 0 && GET_CODE (newpat) == PARALLEL
2086 && XVECLEN (newpat, 0) == 2
2087 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
2088 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
2089 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) == REG
2090 && find_reg_note (i3, REG_UNUSED, SET_DEST (XVECEXP (newpat, 0, 1)))
2091 && ! side_effects_p (SET_SRC (XVECEXP (newpat, 0, 1)))
2092 && asm_noperands (newpat) < 0)
2094 newpat = XVECEXP (newpat, 0, 0);
2095 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2098 else if (insn_code_number < 0 && GET_CODE (newpat) == PARALLEL
2099 && XVECLEN (newpat, 0) == 2
2100 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
2101 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
2102 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) == REG
2103 && find_reg_note (i3, REG_UNUSED, SET_DEST (XVECEXP (newpat, 0, 0)))
2104 && ! side_effects_p (SET_SRC (XVECEXP (newpat, 0, 0)))
2105 && asm_noperands (newpat) < 0)
2107 newpat = XVECEXP (newpat, 0, 1);
2108 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2111 /* If we were combining three insns and the result is a simple SET
2112 with no ASM_OPERANDS that wasn't recognized, try to split it into two
2113 insns. There are two ways to do this. It can be split using a
2114 machine-specific method (like when you have an addition of a large
2115 constant) or by combine in the function find_split_point. */
2117 if (i1 && insn_code_number < 0 && GET_CODE (newpat) == SET
2118 && asm_noperands (newpat) < 0)
2120 rtx m_split, *split;
2121 rtx ni2dest = i2dest;
2123 /* See if the MD file can split NEWPAT. If it can't, see if letting it
2124 use I2DEST as a scratch register will help. In the latter case,
2125 convert I2DEST to the mode of the source of NEWPAT if we can. */
2127 m_split = split_insns (newpat, i3);
2129 /* We can only use I2DEST as a scratch reg if it doesn't overlap any
2130 inputs of NEWPAT. */
2132 /* ??? If I2DEST is not safe, and I1DEST exists, then it would be
2133 possible to try that as a scratch reg. This would require adding
2134 more code to make it work though. */
2136 if (m_split == 0 && ! reg_overlap_mentioned_p (ni2dest, newpat))
2138 /* If I2DEST is a hard register or the only use of a pseudo,
2139 we can change its mode. */
2140 if (GET_MODE (SET_DEST (newpat)) != GET_MODE (i2dest)
2141 && GET_MODE (SET_DEST (newpat)) != VOIDmode
2142 && GET_CODE (i2dest) == REG
2143 && (REGNO (i2dest) < FIRST_PSEUDO_REGISTER
2144 || (REG_N_SETS (REGNO (i2dest)) == 1 && ! added_sets_2
2145 && ! REG_USERVAR_P (i2dest))))
2146 ni2dest = gen_rtx_REG (GET_MODE (SET_DEST (newpat)),
2149 m_split = split_insns (gen_rtx_PARALLEL
2151 gen_rtvec (2, newpat,
2152 gen_rtx_CLOBBER (VOIDmode,
2155 /* If the split with the mode-changed register didn't work, try
2156 the original register. */
2157 if (! m_split && ni2dest != i2dest)
2160 m_split = split_insns (gen_rtx_PARALLEL
2162 gen_rtvec (2, newpat,
2163 gen_rtx_CLOBBER (VOIDmode,
2169 if (m_split && NEXT_INSN (m_split) == NULL_RTX)
2171 m_split = PATTERN (m_split);
2172 insn_code_number = recog_for_combine (&m_split, i3, &new_i3_notes);
2173 if (insn_code_number >= 0)
2176 else if (m_split && NEXT_INSN (NEXT_INSN (m_split)) == NULL_RTX
2177 && (next_real_insn (i2) == i3
2178 || ! use_crosses_set_p (PATTERN (m_split), INSN_CUID (i2))))
2181 rtx newi3pat = PATTERN (NEXT_INSN (m_split));
2182 newi2pat = PATTERN (m_split);
2184 i3set = single_set (NEXT_INSN (m_split));
2185 i2set = single_set (m_split);
2187 /* In case we changed the mode of I2DEST, replace it in the
2188 pseudo-register table here. We can't do it above in case this
2189 code doesn't get executed and we do a split the other way. */
2191 if (REGNO (i2dest) >= FIRST_PSEUDO_REGISTER)
2192 SUBST (regno_reg_rtx[REGNO (i2dest)], ni2dest);
2194 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
2196 /* If I2 or I3 has multiple SETs, we won't know how to track
2197 register status, so don't use these insns. If I2's destination
2198 is used between I2 and I3, we also can't use these insns. */
2200 if (i2_code_number >= 0 && i2set && i3set
2201 && (next_real_insn (i2) == i3
2202 || ! reg_used_between_p (SET_DEST (i2set), i2, i3)))
2203 insn_code_number = recog_for_combine (&newi3pat, i3,
2205 if (insn_code_number >= 0)
2208 /* It is possible that both insns now set the destination of I3.
2209 If so, we must show an extra use of it. */
2211 if (insn_code_number >= 0)
2213 rtx new_i3_dest = SET_DEST (i3set);
2214 rtx new_i2_dest = SET_DEST (i2set);
2216 while (GET_CODE (new_i3_dest) == ZERO_EXTRACT
2217 || GET_CODE (new_i3_dest) == STRICT_LOW_PART
2218 || GET_CODE (new_i3_dest) == SUBREG)
2219 new_i3_dest = XEXP (new_i3_dest, 0);
2221 while (GET_CODE (new_i2_dest) == ZERO_EXTRACT
2222 || GET_CODE (new_i2_dest) == STRICT_LOW_PART
2223 || GET_CODE (new_i2_dest) == SUBREG)
2224 new_i2_dest = XEXP (new_i2_dest, 0);
2226 if (GET_CODE (new_i3_dest) == REG
2227 && GET_CODE (new_i2_dest) == REG
2228 && REGNO (new_i3_dest) == REGNO (new_i2_dest))
2229 REG_N_SETS (REGNO (new_i2_dest))++;
2233 /* If we can split it and use I2DEST, go ahead and see if that
2234 helps things be recognized. Verify that none of the registers
2235 are set between I2 and I3. */
2236 if (insn_code_number < 0 && (split = find_split_point (&newpat, i3)) != 0
2238 && GET_CODE (i2dest) == REG
2240 /* We need I2DEST in the proper mode. If it is a hard register
2241 or the only use of a pseudo, we can change its mode. */
2242 && (GET_MODE (*split) == GET_MODE (i2dest)
2243 || GET_MODE (*split) == VOIDmode
2244 || REGNO (i2dest) < FIRST_PSEUDO_REGISTER
2245 || (REG_N_SETS (REGNO (i2dest)) == 1 && ! added_sets_2
2246 && ! REG_USERVAR_P (i2dest)))
2247 && (next_real_insn (i2) == i3
2248 || ! use_crosses_set_p (*split, INSN_CUID (i2)))
2249 /* We can't overwrite I2DEST if its value is still used by
2251 && ! reg_referenced_p (i2dest, newpat))
2253 rtx newdest = i2dest;
2254 enum rtx_code split_code = GET_CODE (*split);
2255 enum machine_mode split_mode = GET_MODE (*split);
2257 /* Get NEWDEST as a register in the proper mode. We have already
2258 validated that we can do this. */
2259 if (GET_MODE (i2dest) != split_mode && split_mode != VOIDmode)
2261 newdest = gen_rtx_REG (split_mode, REGNO (i2dest));
2263 if (REGNO (i2dest) >= FIRST_PSEUDO_REGISTER)
2264 SUBST (regno_reg_rtx[REGNO (i2dest)], newdest);
2267 /* If *SPLIT is a (mult FOO (const_int pow2)), convert it to
2268 an ASHIFT. This can occur if it was inside a PLUS and hence
2269 appeared to be a memory address. This is a kludge. */
2270 if (split_code == MULT
2271 && GET_CODE (XEXP (*split, 1)) == CONST_INT
2272 && INTVAL (XEXP (*split, 1)) > 0
2273 && (i = exact_log2 (INTVAL (XEXP (*split, 1)))) >= 0)
2275 SUBST (*split, gen_rtx_ASHIFT (split_mode,
2276 XEXP (*split, 0), GEN_INT (i)));
2277 /* Update split_code because we may not have a multiply
2279 split_code = GET_CODE (*split);
2282 #ifdef INSN_SCHEDULING
2283 /* If *SPLIT is a paradoxical SUBREG, when we split it, it should
2284 be written as a ZERO_EXTEND. */
2285 if (split_code == SUBREG && GET_CODE (SUBREG_REG (*split)) == MEM)
2287 #ifdef LOAD_EXTEND_OP
2288 /* Or as a SIGN_EXTEND if LOAD_EXTEND_OP says that that's
2289 what it really is. */
2290 if (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (*split)))
2292 SUBST (*split, gen_rtx_SIGN_EXTEND (split_mode,
2293 SUBREG_REG (*split)));
2296 SUBST (*split, gen_rtx_ZERO_EXTEND (split_mode,
2297 SUBREG_REG (*split)));
2301 newi2pat = gen_rtx_SET (VOIDmode, newdest, *split);
2302 SUBST (*split, newdest);
2303 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
2305 /* If the split point was a MULT and we didn't have one before,
2306 don't use one now. */
2307 if (i2_code_number >= 0 && ! (split_code == MULT && ! have_mult))
2308 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2312 /* Check for a case where we loaded from memory in a narrow mode and
2313 then sign extended it, but we need both registers. In that case,
2314 we have a PARALLEL with both loads from the same memory location.
2315 We can split this into a load from memory followed by a register-register
2316 copy. This saves at least one insn, more if register allocation can
2319 We cannot do this if the destination of the second assignment is
2320 a register that we have already assumed is zero-extended. Similarly
2321 for a SUBREG of such a register. */
2323 else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0
2324 && GET_CODE (newpat) == PARALLEL
2325 && XVECLEN (newpat, 0) == 2
2326 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
2327 && GET_CODE (SET_SRC (XVECEXP (newpat, 0, 0))) == SIGN_EXTEND
2328 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
2329 && rtx_equal_p (SET_SRC (XVECEXP (newpat, 0, 1)),
2330 XEXP (SET_SRC (XVECEXP (newpat, 0, 0)), 0))
2331 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)),
2333 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
2334 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
2335 && ! (temp = SET_DEST (XVECEXP (newpat, 0, 1)),
2336 (GET_CODE (temp) == REG
2337 && reg_nonzero_bits[REGNO (temp)] != 0
2338 && GET_MODE_BITSIZE (GET_MODE (temp)) < BITS_PER_WORD
2339 && GET_MODE_BITSIZE (GET_MODE (temp)) < HOST_BITS_PER_INT
2340 && (reg_nonzero_bits[REGNO (temp)]
2341 != GET_MODE_MASK (word_mode))))
2342 && ! (GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) == SUBREG
2343 && (temp = SUBREG_REG (SET_DEST (XVECEXP (newpat, 0, 1))),
2344 (GET_CODE (temp) == REG
2345 && reg_nonzero_bits[REGNO (temp)] != 0
2346 && GET_MODE_BITSIZE (GET_MODE (temp)) < BITS_PER_WORD
2347 && GET_MODE_BITSIZE (GET_MODE (temp)) < HOST_BITS_PER_INT
2348 && (reg_nonzero_bits[REGNO (temp)]
2349 != GET_MODE_MASK (word_mode)))))
2350 && ! reg_overlap_mentioned_p (SET_DEST (XVECEXP (newpat, 0, 1)),
2351 SET_SRC (XVECEXP (newpat, 0, 1)))
2352 && ! find_reg_note (i3, REG_UNUSED,
2353 SET_DEST (XVECEXP (newpat, 0, 0))))
2357 newi2pat = XVECEXP (newpat, 0, 0);
2358 ni2dest = SET_DEST (XVECEXP (newpat, 0, 0));
2359 newpat = XVECEXP (newpat, 0, 1);
2360 SUBST (SET_SRC (newpat),
2361 gen_lowpart_for_combine (GET_MODE (SET_SRC (newpat)), ni2dest));
2362 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
2364 if (i2_code_number >= 0)
2365 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2367 if (insn_code_number >= 0)
2372 /* If we will be able to accept this, we have made a change to the
2373 destination of I3. This can invalidate a LOG_LINKS pointing
2374 to I3. No other part of combine.c makes such a transformation.
2376 The new I3 will have a destination that was previously the
2377 destination of I1 or I2 and which was used in i2 or I3. Call
2378 distribute_links to make a LOG_LINK from the next use of
2379 that destination. */
2381 PATTERN (i3) = newpat;
2382 distribute_links (gen_rtx_INSN_LIST (VOIDmode, i3, NULL_RTX));
2384 /* I3 now uses what used to be its destination and which is
2385 now I2's destination. That means we need a LOG_LINK from
2386 I3 to I2. But we used to have one, so we still will.
2388 However, some later insn might be using I2's dest and have
2389 a LOG_LINK pointing at I3. We must remove this link.
2390 The simplest way to remove the link is to point it at I1,
2391 which we know will be a NOTE. */
2393 for (insn = NEXT_INSN (i3);
2394 insn && (this_basic_block->next_bb == EXIT_BLOCK_PTR
2395 || insn != this_basic_block->next_bb->head);
2396 insn = NEXT_INSN (insn))
2398 if (INSN_P (insn) && reg_referenced_p (ni2dest, PATTERN (insn)))
2400 for (link = LOG_LINKS (insn); link;
2401 link = XEXP (link, 1))
2402 if (XEXP (link, 0) == i3)
2403 XEXP (link, 0) = i1;
2411 /* Similarly, check for a case where we have a PARALLEL of two independent
2412 SETs but we started with three insns. In this case, we can do the sets
2413 as two separate insns. This case occurs when some SET allows two
2414 other insns to combine, but the destination of that SET is still live. */
2416 else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0
2417 && GET_CODE (newpat) == PARALLEL
2418 && XVECLEN (newpat, 0) == 2
2419 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
2420 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != ZERO_EXTRACT
2421 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != STRICT_LOW_PART
2422 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
2423 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
2424 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
2425 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)),
2427 /* Don't pass sets with (USE (MEM ...)) dests to the following. */
2428 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != USE
2429 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != USE
2430 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 1)),
2431 XVECEXP (newpat, 0, 0))
2432 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 0)),
2433 XVECEXP (newpat, 0, 1))
2434 && ! (contains_muldiv (SET_SRC (XVECEXP (newpat, 0, 0)))
2435 && contains_muldiv (SET_SRC (XVECEXP (newpat, 0, 1)))))
2437 /* Normally, it doesn't matter which of the two is done first,
2438 but it does if one references cc0. In that case, it has to
2441 if (reg_referenced_p (cc0_rtx, XVECEXP (newpat, 0, 0)))
2443 newi2pat = XVECEXP (newpat, 0, 0);
2444 newpat = XVECEXP (newpat, 0, 1);
2449 newi2pat = XVECEXP (newpat, 0, 1);
2450 newpat = XVECEXP (newpat, 0, 0);
2453 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
2455 if (i2_code_number >= 0)
2456 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2459 /* If it still isn't recognized, fail and change things back the way they
2461 if ((insn_code_number < 0
2462 /* Is the result a reasonable ASM_OPERANDS? */
2463 && (! check_asm_operands (newpat) || added_sets_1 || added_sets_2)))
2469 /* If we had to change another insn, make sure it is valid also. */
2470 if (undobuf.other_insn)
2472 rtx other_pat = PATTERN (undobuf.other_insn);
2473 rtx new_other_notes;
2476 CLEAR_HARD_REG_SET (newpat_used_regs);
2478 other_code_number = recog_for_combine (&other_pat, undobuf.other_insn,
2481 if (other_code_number < 0 && ! check_asm_operands (other_pat))
2487 PATTERN (undobuf.other_insn) = other_pat;
2489 /* If any of the notes in OTHER_INSN were REG_UNUSED, ensure that they
2490 are still valid. Then add any non-duplicate notes added by
2491 recog_for_combine. */
2492 for (note = REG_NOTES (undobuf.other_insn); note; note = next)
2494 next = XEXP (note, 1);
2496 if (REG_NOTE_KIND (note) == REG_UNUSED
2497 && ! reg_set_p (XEXP (note, 0), PATTERN (undobuf.other_insn)))
2499 if (GET_CODE (XEXP (note, 0)) == REG)
2500 REG_N_DEATHS (REGNO (XEXP (note, 0)))--;
2502 remove_note (undobuf.other_insn, note);
2506 for (note = new_other_notes; note; note = XEXP (note, 1))
2507 if (GET_CODE (XEXP (note, 0)) == REG)
2508 REG_N_DEATHS (REGNO (XEXP (note, 0)))++;
2510 distribute_notes (new_other_notes, undobuf.other_insn,
2511 undobuf.other_insn, NULL_RTX, NULL_RTX, NULL_RTX);
2514 /* If I2 is the setter CC0 and I3 is the user CC0 then check whether
2515 they are adjacent to each other or not. */
2517 rtx p = prev_nonnote_insn (i3);
2518 if (p && p != i2 && GET_CODE (p) == INSN && newi2pat
2519 && sets_cc0_p (newi2pat))
2527 /* We now know that we can do this combination. Merge the insns and
2528 update the status of registers and LOG_LINKS. */
2531 rtx i3notes, i2notes, i1notes = 0;
2532 rtx i3links, i2links, i1links = 0;
2535 /* Compute which registers we expect to eliminate. newi2pat may be setting
2536 either i3dest or i2dest, so we must check it. Also, i1dest may be the
2537 same as i3dest, in which case newi2pat may be setting i1dest. */
2538 rtx elim_i2 = ((newi2pat && reg_set_p (i2dest, newi2pat))
2539 || i2dest_in_i2src || i2dest_in_i1src
2541 rtx elim_i1 = (i1 == 0 || i1dest_in_i1src
2542 || (newi2pat && reg_set_p (i1dest, newi2pat))
2545 /* Get the old REG_NOTES and LOG_LINKS from all our insns and
2547 i3notes = REG_NOTES (i3), i3links = LOG_LINKS (i3);
2548 i2notes = REG_NOTES (i2), i2links = LOG_LINKS (i2);
2550 i1notes = REG_NOTES (i1), i1links = LOG_LINKS (i1);
2552 /* Ensure that we do not have something that should not be shared but
2553 occurs multiple times in the new insns. Check this by first
2554 resetting all the `used' flags and then copying anything is shared. */
2556 reset_used_flags (i3notes);
2557 reset_used_flags (i2notes);
2558 reset_used_flags (i1notes);
2559 reset_used_flags (newpat);
2560 reset_used_flags (newi2pat);
2561 if (undobuf.other_insn)
2562 reset_used_flags (PATTERN (undobuf.other_insn));
2564 i3notes = copy_rtx_if_shared (i3notes);
2565 i2notes = copy_rtx_if_shared (i2notes);
2566 i1notes = copy_rtx_if_shared (i1notes);
2567 newpat = copy_rtx_if_shared (newpat);
2568 newi2pat = copy_rtx_if_shared (newi2pat);
2569 if (undobuf.other_insn)
2570 reset_used_flags (PATTERN (undobuf.other_insn));
2572 INSN_CODE (i3) = insn_code_number;
2573 PATTERN (i3) = newpat;
2575 if (GET_CODE (i3) == CALL_INSN && CALL_INSN_FUNCTION_USAGE (i3))
2577 rtx call_usage = CALL_INSN_FUNCTION_USAGE (i3);
2579 reset_used_flags (call_usage);
2580 call_usage = copy_rtx (call_usage);
2583 replace_rtx (call_usage, i2dest, i2src);
2586 replace_rtx (call_usage, i1dest, i1src);
2588 CALL_INSN_FUNCTION_USAGE (i3) = call_usage;
2591 if (undobuf.other_insn)
2592 INSN_CODE (undobuf.other_insn) = other_code_number;
2594 /* We had one special case above where I2 had more than one set and
2595 we replaced a destination of one of those sets with the destination
2596 of I3. In that case, we have to update LOG_LINKS of insns later
2597 in this basic block. Note that this (expensive) case is rare.
2599 Also, in this case, we must pretend that all REG_NOTEs for I2
2600 actually came from I3, so that REG_UNUSED notes from I2 will be
2601 properly handled. */
2603 if (i3_subst_into_i2)
2605 for (i = 0; i < XVECLEN (PATTERN (i2), 0); i++)
2606 if (GET_CODE (XVECEXP (PATTERN (i2), 0, i)) != USE
2607 && GET_CODE (SET_DEST (XVECEXP (PATTERN (i2), 0, i))) == REG
2608 && SET_DEST (XVECEXP (PATTERN (i2), 0, i)) != i2dest
2609 && ! find_reg_note (i2, REG_UNUSED,
2610 SET_DEST (XVECEXP (PATTERN (i2), 0, i))))
2611 for (temp = NEXT_INSN (i2);
2612 temp && (this_basic_block->next_bb == EXIT_BLOCK_PTR
2613 || this_basic_block->head != temp);
2614 temp = NEXT_INSN (temp))
2615 if (temp != i3 && INSN_P (temp))
2616 for (link = LOG_LINKS (temp); link; link = XEXP (link, 1))
2617 if (XEXP (link, 0) == i2)
2618 XEXP (link, 0) = i3;
2623 while (XEXP (link, 1))
2624 link = XEXP (link, 1);
2625 XEXP (link, 1) = i2notes;
2639 INSN_CODE (i2) = i2_code_number;
2640 PATTERN (i2) = newi2pat;
2644 PUT_CODE (i2, NOTE);
2645 NOTE_LINE_NUMBER (i2) = NOTE_INSN_DELETED;
2646 NOTE_SOURCE_FILE (i2) = 0;
2653 PUT_CODE (i1, NOTE);
2654 NOTE_LINE_NUMBER (i1) = NOTE_INSN_DELETED;
2655 NOTE_SOURCE_FILE (i1) = 0;
2658 /* Get death notes for everything that is now used in either I3 or
2659 I2 and used to die in a previous insn. If we built two new
2660 patterns, move from I1 to I2 then I2 to I3 so that we get the
2661 proper movement on registers that I2 modifies. */
2665 move_deaths (newi2pat, NULL_RTX, INSN_CUID (i1), i2, &midnotes);
2666 move_deaths (newpat, newi2pat, INSN_CUID (i1), i3, &midnotes);
2669 move_deaths (newpat, NULL_RTX, i1 ? INSN_CUID (i1) : INSN_CUID (i2),
2672 /* Distribute all the LOG_LINKS and REG_NOTES from I1, I2, and I3. */
2674 distribute_notes (i3notes, i3, i3, newi2pat ? i2 : NULL_RTX,
2677 distribute_notes (i2notes, i2, i3, newi2pat ? i2 : NULL_RTX,
2680 distribute_notes (i1notes, i1, i3, newi2pat ? i2 : NULL_RTX,
2683 distribute_notes (midnotes, NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
2686 /* Distribute any notes added to I2 or I3 by recog_for_combine. We
2687 know these are REG_UNUSED and want them to go to the desired insn,
2688 so we always pass it as i3. We have not counted the notes in
2689 reg_n_deaths yet, so we need to do so now. */
2691 if (newi2pat && new_i2_notes)
2693 for (temp = new_i2_notes; temp; temp = XEXP (temp, 1))
2694 if (GET_CODE (XEXP (temp, 0)) == REG)
2695 REG_N_DEATHS (REGNO (XEXP (temp, 0)))++;
2697 distribute_notes (new_i2_notes, i2, i2, NULL_RTX, NULL_RTX, NULL_RTX);
2702 for (temp = new_i3_notes; temp; temp = XEXP (temp, 1))
2703 if (GET_CODE (XEXP (temp, 0)) == REG)
2704 REG_N_DEATHS (REGNO (XEXP (temp, 0)))++;
2706 distribute_notes (new_i3_notes, i3, i3, NULL_RTX, NULL_RTX, NULL_RTX);
2709 /* If I3DEST was used in I3SRC, it really died in I3. We may need to
2710 put a REG_DEAD note for it somewhere. If NEWI2PAT exists and sets
2711 I3DEST, the death must be somewhere before I2, not I3. If we passed I3
2712 in that case, it might delete I2. Similarly for I2 and I1.
2713 Show an additional death due to the REG_DEAD note we make here. If
2714 we discard it in distribute_notes, we will decrement it again. */
2718 if (GET_CODE (i3dest_killed) == REG)
2719 REG_N_DEATHS (REGNO (i3dest_killed))++;
2721 if (newi2pat && reg_set_p (i3dest_killed, newi2pat))
2722 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i3dest_killed,
2724 NULL_RTX, i2, NULL_RTX, elim_i2, elim_i1);
2726 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i3dest_killed,
2728 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
2732 if (i2dest_in_i2src)
2734 if (GET_CODE (i2dest) == REG)
2735 REG_N_DEATHS (REGNO (i2dest))++;
2737 if (newi2pat && reg_set_p (i2dest, newi2pat))
2738 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i2dest, NULL_RTX),
2739 NULL_RTX, i2, NULL_RTX, NULL_RTX, NULL_RTX);
2741 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i2dest, NULL_RTX),
2742 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
2743 NULL_RTX, NULL_RTX);
2746 if (i1dest_in_i1src)
2748 if (GET_CODE (i1dest) == REG)
2749 REG_N_DEATHS (REGNO (i1dest))++;
2751 if (newi2pat && reg_set_p (i1dest, newi2pat))
2752 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i1dest, NULL_RTX),
2753 NULL_RTX, i2, NULL_RTX, NULL_RTX, NULL_RTX);
2755 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i1dest, NULL_RTX),
2756 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
2757 NULL_RTX, NULL_RTX);
2760 distribute_links (i3links);
2761 distribute_links (i2links);
2762 distribute_links (i1links);
2764 if (GET_CODE (i2dest) == REG)
2767 rtx i2_insn = 0, i2_val = 0, set;
2769 /* The insn that used to set this register doesn't exist, and
2770 this life of the register may not exist either. See if one of
2771 I3's links points to an insn that sets I2DEST. If it does,
2772 that is now the last known value for I2DEST. If we don't update
2773 this and I2 set the register to a value that depended on its old
2774 contents, we will get confused. If this insn is used, thing
2775 will be set correctly in combine_instructions. */
2777 for (link = LOG_LINKS (i3); link; link = XEXP (link, 1))
2778 if ((set = single_set (XEXP (link, 0))) != 0
2779 && rtx_equal_p (i2dest, SET_DEST (set)))
2780 i2_insn = XEXP (link, 0), i2_val = SET_SRC (set);
2782 record_value_for_reg (i2dest, i2_insn, i2_val);
2784 /* If the reg formerly set in I2 died only once and that was in I3,
2785 zero its use count so it won't make `reload' do any work. */
2787 && (newi2pat == 0 || ! reg_mentioned_p (i2dest, newi2pat))
2788 && ! i2dest_in_i2src)
2790 regno = REGNO (i2dest);
2791 REG_N_SETS (regno)--;
2795 if (i1 && GET_CODE (i1dest) == REG)
2798 rtx i1_insn = 0, i1_val = 0, set;
2800 for (link = LOG_LINKS (i3); link; link = XEXP (link, 1))
2801 if ((set = single_set (XEXP (link, 0))) != 0
2802 && rtx_equal_p (i1dest, SET_DEST (set)))
2803 i1_insn = XEXP (link, 0), i1_val = SET_SRC (set);
2805 record_value_for_reg (i1dest, i1_insn, i1_val);
2807 regno = REGNO (i1dest);
2808 if (! added_sets_1 && ! i1dest_in_i1src)
2809 REG_N_SETS (regno)--;
2812 /* Update reg_nonzero_bits et al for any changes that may have been made
2813 to this insn. The order of set_nonzero_bits_and_sign_copies() is
2814 important. Because newi2pat can affect nonzero_bits of newpat */
2816 note_stores (newi2pat, set_nonzero_bits_and_sign_copies, NULL);
2817 note_stores (newpat, set_nonzero_bits_and_sign_copies, NULL);
2819 /* Set new_direct_jump_p if a new return or simple jump instruction
2822 If I3 is now an unconditional jump, ensure that it has a
2823 BARRIER following it since it may have initially been a
2824 conditional jump. It may also be the last nonnote insn. */
2826 if (GET_CODE (newpat) == RETURN || any_uncondjump_p (i3))
2828 *new_direct_jump_p = 1;
2830 if ((temp = next_nonnote_insn (i3)) == NULL_RTX
2831 || GET_CODE (temp) != BARRIER)
2832 emit_barrier_after (i3);
2834 /* An NOOP jump does not need barrier, but it does need cleaning up
2836 if (GET_CODE (newpat) == SET
2837 && SET_SRC (newpat) == pc_rtx
2838 && SET_DEST (newpat) == pc_rtx)
2839 *new_direct_jump_p = 1;
2842 combine_successes++;
2845 /* Clear this here, so that subsequent get_last_value calls are not
2847 subst_prev_insn = NULL_RTX;
2849 if (added_links_insn
2850 && (newi2pat == 0 || INSN_CUID (added_links_insn) < INSN_CUID (i2))
2851 && INSN_CUID (added_links_insn) < INSN_CUID (i3))
2852 return added_links_insn;
2854 return newi2pat ? i2 : i3;
2857 /* Undo all the modifications recorded in undobuf. */
2862 struct undo *undo, *next;
2864 for (undo = undobuf.undos; undo; undo = next)
2868 *undo->where.i = undo->old_contents.i;
2870 *undo->where.r = undo->old_contents.r;
2872 undo->next = undobuf.frees;
2873 undobuf.frees = undo;
2878 /* Clear this here, so that subsequent get_last_value calls are not
2880 subst_prev_insn = NULL_RTX;
2883 /* We've committed to accepting the changes we made. Move all
2884 of the undos to the free list. */
2889 struct undo *undo, *next;
2891 for (undo = undobuf.undos; undo; undo = next)
2894 undo->next = undobuf.frees;
2895 undobuf.frees = undo;
2901 /* Find the innermost point within the rtx at LOC, possibly LOC itself,
2902 where we have an arithmetic expression and return that point. LOC will
2905 try_combine will call this function to see if an insn can be split into
2909 find_split_point (loc, insn)
2914 enum rtx_code code = GET_CODE (x);
2916 unsigned HOST_WIDE_INT len = 0;
2917 HOST_WIDE_INT pos = 0;
2919 rtx inner = NULL_RTX;
2921 /* First special-case some codes. */
2925 #ifdef INSN_SCHEDULING
2926 /* If we are making a paradoxical SUBREG invalid, it becomes a split
2928 if (GET_CODE (SUBREG_REG (x)) == MEM)
2931 return find_split_point (&SUBREG_REG (x), insn);
2935 /* If we have (mem (const ..)) or (mem (symbol_ref ...)), split it
2936 using LO_SUM and HIGH. */
2937 if (GET_CODE (XEXP (x, 0)) == CONST
2938 || GET_CODE (XEXP (x, 0)) == SYMBOL_REF)
2941 gen_rtx_LO_SUM (Pmode,
2942 gen_rtx_HIGH (Pmode, XEXP (x, 0)),
2944 return &XEXP (XEXP (x, 0), 0);
2948 /* If we have a PLUS whose second operand is a constant and the
2949 address is not valid, perhaps will can split it up using
2950 the machine-specific way to split large constants. We use
2951 the first pseudo-reg (one of the virtual regs) as a placeholder;
2952 it will not remain in the result. */
2953 if (GET_CODE (XEXP (x, 0)) == PLUS
2954 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
2955 && ! memory_address_p (GET_MODE (x), XEXP (x, 0)))
2957 rtx reg = regno_reg_rtx[FIRST_PSEUDO_REGISTER];
2958 rtx seq = split_insns (gen_rtx_SET (VOIDmode, reg, XEXP (x, 0)),
2961 /* This should have produced two insns, each of which sets our
2962 placeholder. If the source of the second is a valid address,
2963 we can make put both sources together and make a split point
2967 && NEXT_INSN (seq) != NULL_RTX
2968 && NEXT_INSN (NEXT_INSN (seq)) == NULL_RTX
2969 && GET_CODE (seq) == INSN
2970 && GET_CODE (PATTERN (seq)) == SET
2971 && SET_DEST (PATTERN (seq)) == reg
2972 && ! reg_mentioned_p (reg,
2973 SET_SRC (PATTERN (seq)))
2974 && GET_CODE (NEXT_INSN (seq)) == INSN
2975 && GET_CODE (PATTERN (NEXT_INSN (seq))) == SET
2976 && SET_DEST (PATTERN (NEXT_INSN (seq))) == reg
2977 && memory_address_p (GET_MODE (x),
2978 SET_SRC (PATTERN (NEXT_INSN (seq)))))
2980 rtx src1 = SET_SRC (PATTERN (seq));
2981 rtx src2 = SET_SRC (PATTERN (NEXT_INSN (seq)));
2983 /* Replace the placeholder in SRC2 with SRC1. If we can
2984 find where in SRC2 it was placed, that can become our
2985 split point and we can replace this address with SRC2.
2986 Just try two obvious places. */
2988 src2 = replace_rtx (src2, reg, src1);
2990 if (XEXP (src2, 0) == src1)
2991 split = &XEXP (src2, 0);
2992 else if (GET_RTX_FORMAT (GET_CODE (XEXP (src2, 0)))[0] == 'e'
2993 && XEXP (XEXP (src2, 0), 0) == src1)
2994 split = &XEXP (XEXP (src2, 0), 0);
2998 SUBST (XEXP (x, 0), src2);
3003 /* If that didn't work, perhaps the first operand is complex and
3004 needs to be computed separately, so make a split point there.
3005 This will occur on machines that just support REG + CONST
3006 and have a constant moved through some previous computation. */
3008 else if (GET_RTX_CLASS (GET_CODE (XEXP (XEXP (x, 0), 0))) != 'o'
3009 && ! (GET_CODE (XEXP (XEXP (x, 0), 0)) == SUBREG
3010 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (XEXP (x, 0), 0))))
3012 return &XEXP (XEXP (x, 0), 0);
3018 /* If SET_DEST is CC0 and SET_SRC is not an operand, a COMPARE, or a
3019 ZERO_EXTRACT, the most likely reason why this doesn't match is that
3020 we need to put the operand into a register. So split at that
3023 if (SET_DEST (x) == cc0_rtx
3024 && GET_CODE (SET_SRC (x)) != COMPARE
3025 && GET_CODE (SET_SRC (x)) != ZERO_EXTRACT
3026 && GET_RTX_CLASS (GET_CODE (SET_SRC (x))) != 'o'
3027 && ! (GET_CODE (SET_SRC (x)) == SUBREG
3028 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (SET_SRC (x)))) == 'o'))
3029 return &SET_SRC (x);
3032 /* See if we can split SET_SRC as it stands. */
3033 split = find_split_point (&SET_SRC (x), insn);
3034 if (split && split != &SET_SRC (x))
3037 /* See if we can split SET_DEST as it stands. */
3038 split = find_split_point (&SET_DEST (x), insn);
3039 if (split && split != &SET_DEST (x))
3042 /* See if this is a bitfield assignment with everything constant. If
3043 so, this is an IOR of an AND, so split it into that. */
3044 if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
3045 && (GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0)))
3046 <= HOST_BITS_PER_WIDE_INT)
3047 && GET_CODE (XEXP (SET_DEST (x), 1)) == CONST_INT
3048 && GET_CODE (XEXP (SET_DEST (x), 2)) == CONST_INT
3049 && GET_CODE (SET_SRC (x)) == CONST_INT
3050 && ((INTVAL (XEXP (SET_DEST (x), 1))
3051 + INTVAL (XEXP (SET_DEST (x), 2)))
3052 <= GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0))))
3053 && ! side_effects_p (XEXP (SET_DEST (x), 0)))
3055 HOST_WIDE_INT pos = INTVAL (XEXP (SET_DEST (x), 2));
3056 unsigned HOST_WIDE_INT len = INTVAL (XEXP (SET_DEST (x), 1));
3057 unsigned HOST_WIDE_INT src = INTVAL (SET_SRC (x));
3058 rtx dest = XEXP (SET_DEST (x), 0);
3059 enum machine_mode mode = GET_MODE (dest);
3060 unsigned HOST_WIDE_INT mask = ((HOST_WIDE_INT) 1 << len) - 1;
3062 if (BITS_BIG_ENDIAN)
3063 pos = GET_MODE_BITSIZE (mode) - len - pos;
3067 gen_binary (IOR, mode, dest, GEN_INT (src << pos)));
3070 gen_binary (IOR, mode,
3071 gen_binary (AND, mode, dest,
3072 gen_int_mode (~(mask << pos),
3074 GEN_INT (src << pos)));
3076 SUBST (SET_DEST (x), dest);
3078 split = find_split_point (&SET_SRC (x), insn);
3079 if (split && split != &SET_SRC (x))
3083 /* Otherwise, see if this is an operation that we can split into two.
3084 If so, try to split that. */
3085 code = GET_CODE (SET_SRC (x));
3090 /* If we are AND'ing with a large constant that is only a single
3091 bit and the result is only being used in a context where we
3092 need to know if it is zero or non-zero, replace it with a bit
3093 extraction. This will avoid the large constant, which might
3094 have taken more than one insn to make. If the constant were
3095 not a valid argument to the AND but took only one insn to make,
3096 this is no worse, but if it took more than one insn, it will
3099 if (GET_CODE (XEXP (SET_SRC (x), 1)) == CONST_INT
3100 && GET_CODE (XEXP (SET_SRC (x), 0)) == REG
3101 && (pos = exact_log2 (INTVAL (XEXP (SET_SRC (x), 1)))) >= 7
3102 && GET_CODE (SET_DEST (x)) == REG
3103 && (split = find_single_use (SET_DEST (x), insn, (rtx*) 0)) != 0
3104 && (GET_CODE (*split) == EQ || GET_CODE (*split) == NE)
3105 && XEXP (*split, 0) == SET_DEST (x)
3106 && XEXP (*split, 1) == const0_rtx)
3108 rtx extraction = make_extraction (GET_MODE (SET_DEST (x)),
3109 XEXP (SET_SRC (x), 0),
3110 pos, NULL_RTX, 1, 1, 0, 0);
3111 if (extraction != 0)
3113 SUBST (SET_SRC (x), extraction);
3114 return find_split_point (loc, insn);
3120 /* if STORE_FLAG_VALUE is -1, this is (NE X 0) and only one bit of X
3121 is known to be on, this can be converted into a NEG of a shift. */
3122 if (STORE_FLAG_VALUE == -1 && XEXP (SET_SRC (x), 1) == const0_rtx
3123 && GET_MODE (SET_SRC (x)) == GET_MODE (XEXP (SET_SRC (x), 0))
3124 && 1 <= (pos = exact_log2
3125 (nonzero_bits (XEXP (SET_SRC (x), 0),
3126 GET_MODE (XEXP (SET_SRC (x), 0))))))
3128 enum machine_mode mode = GET_MODE (XEXP (SET_SRC (x), 0));
3132 gen_rtx_LSHIFTRT (mode,
3133 XEXP (SET_SRC (x), 0),
3136 split = find_split_point (&SET_SRC (x), insn);
3137 if (split && split != &SET_SRC (x))
3143 inner = XEXP (SET_SRC (x), 0);
3145 /* We can't optimize if either mode is a partial integer
3146 mode as we don't know how many bits are significant
3148 if (GET_MODE_CLASS (GET_MODE (inner)) == MODE_PARTIAL_INT
3149 || GET_MODE_CLASS (GET_MODE (SET_SRC (x))) == MODE_PARTIAL_INT)
3153 len = GET_MODE_BITSIZE (GET_MODE (inner));
3159 if (GET_CODE (XEXP (SET_SRC (x), 1)) == CONST_INT
3160 && GET_CODE (XEXP (SET_SRC (x), 2)) == CONST_INT)
3162 inner = XEXP (SET_SRC (x), 0);
3163 len = INTVAL (XEXP (SET_SRC (x), 1));
3164 pos = INTVAL (XEXP (SET_SRC (x), 2));
3166 if (BITS_BIG_ENDIAN)
3167 pos = GET_MODE_BITSIZE (GET_MODE (inner)) - len - pos;
3168 unsignedp = (code == ZERO_EXTRACT);
3176 if (len && pos >= 0 && pos + len <= GET_MODE_BITSIZE (GET_MODE (inner)))
3178 enum machine_mode mode = GET_MODE (SET_SRC (x));
3180 /* For unsigned, we have a choice of a shift followed by an
3181 AND or two shifts. Use two shifts for field sizes where the
3182 constant might be too large. We assume here that we can
3183 always at least get 8-bit constants in an AND insn, which is
3184 true for every current RISC. */
3186 if (unsignedp && len <= 8)
3191 (mode, gen_lowpart_for_combine (mode, inner),
3193 GEN_INT (((HOST_WIDE_INT) 1 << len) - 1)));
3195 split = find_split_point (&SET_SRC (x), insn);
3196 if (split && split != &SET_SRC (x))
3203 (unsignedp ? LSHIFTRT : ASHIFTRT, mode,
3204 gen_rtx_ASHIFT (mode,
3205 gen_lowpart_for_combine (mode, inner),
3206 GEN_INT (GET_MODE_BITSIZE (mode)
3208 GEN_INT (GET_MODE_BITSIZE (mode) - len)));
3210 split = find_split_point (&SET_SRC (x), insn);
3211 if (split && split != &SET_SRC (x))
3216 /* See if this is a simple operation with a constant as the second
3217 operand. It might be that this constant is out of range and hence
3218 could be used as a split point. */
3219 if ((GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '2'
3220 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == 'c'
3221 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '<')
3222 && CONSTANT_P (XEXP (SET_SRC (x), 1))
3223 && (GET_RTX_CLASS (GET_CODE (XEXP (SET_SRC (x), 0))) == 'o'
3224 || (GET_CODE (XEXP (SET_SRC (x), 0)) == SUBREG
3225 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (SET_SRC (x), 0))))
3227 return &XEXP (SET_SRC (x), 1);
3229 /* Finally, see if this is a simple operation with its first operand
3230 not in a register. The operation might require this operand in a
3231 register, so return it as a split point. We can always do this
3232 because if the first operand were another operation, we would have
3233 already found it as a split point. */
3234 if ((GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '2'
3235 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == 'c'
3236 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '<'
3237 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '1')
3238 && ! register_operand (XEXP (SET_SRC (x), 0), VOIDmode))
3239 return &XEXP (SET_SRC (x), 0);
3245 /* We write NOR as (and (not A) (not B)), but if we don't have a NOR,
3246 it is better to write this as (not (ior A B)) so we can split it.
3247 Similarly for IOR. */
3248 if (GET_CODE (XEXP (x, 0)) == NOT && GET_CODE (XEXP (x, 1)) == NOT)
3251 gen_rtx_NOT (GET_MODE (x),
3252 gen_rtx_fmt_ee (code == IOR ? AND : IOR,
3254 XEXP (XEXP (x, 0), 0),
3255 XEXP (XEXP (x, 1), 0))));
3256 return find_split_point (loc, insn);
3259 /* Many RISC machines have a large set of logical insns. If the
3260 second operand is a NOT, put it first so we will try to split the
3261 other operand first. */
3262 if (GET_CODE (XEXP (x, 1)) == NOT)
3264 rtx tem = XEXP (x, 0);
3265 SUBST (XEXP (x, 0), XEXP (x, 1));
3266 SUBST (XEXP (x, 1), tem);
3274 /* Otherwise, select our actions depending on our rtx class. */
3275 switch (GET_RTX_CLASS (code))
3277 case 'b': /* This is ZERO_EXTRACT and SIGN_EXTRACT. */
3279 split = find_split_point (&XEXP (x, 2), insn);
3282 /* ... fall through ... */
3286 split = find_split_point (&XEXP (x, 1), insn);
3289 /* ... fall through ... */
3291 /* Some machines have (and (shift ...) ...) insns. If X is not
3292 an AND, but XEXP (X, 0) is, use it as our split point. */
3293 if (GET_CODE (x) != AND && GET_CODE (XEXP (x, 0)) == AND)
3294 return &XEXP (x, 0);
3296 split = find_split_point (&XEXP (x, 0), insn);
3302 /* Otherwise, we don't have a split point. */
3306 /* Throughout X, replace FROM with TO, and return the result.
3307 The result is TO if X is FROM;
3308 otherwise the result is X, but its contents may have been modified.
3309 If they were modified, a record was made in undobuf so that
3310 undo_all will (among other things) return X to its original state.
3312 If the number of changes necessary is too much to record to undo,
3313 the excess changes are not made, so the result is invalid.
3314 The changes already made can still be undone.
3315 undobuf.num_undo is incremented for such changes, so by testing that
3316 the caller can tell whether the result is valid.
3318 `n_occurrences' is incremented each time FROM is replaced.
3320 IN_DEST is non-zero if we are processing the SET_DEST of a SET.
3322 UNIQUE_COPY is non-zero if each substitution must be unique. We do this
3323 by copying if `n_occurrences' is non-zero. */
3326 subst (x, from, to, in_dest, unique_copy)
3331 enum rtx_code code = GET_CODE (x);
3332 enum machine_mode op0_mode = VOIDmode;
3337 /* Two expressions are equal if they are identical copies of a shared
3338 RTX or if they are both registers with the same register number
3341 #define COMBINE_RTX_EQUAL_P(X,Y) \
3343 || (GET_CODE (X) == REG && GET_CODE (Y) == REG \
3344 && REGNO (X) == REGNO (Y) && GET_MODE (X) == GET_MODE (Y)))
3346 if (! in_dest && COMBINE_RTX_EQUAL_P (x, from))
3349 return (unique_copy && n_occurrences > 1 ? copy_rtx (to) : to);
3352 /* If X and FROM are the same register but different modes, they will
3353 not have been seen as equal above. However, flow.c will make a
3354 LOG_LINKS entry for that case. If we do nothing, we will try to
3355 rerecognize our original insn and, when it succeeds, we will
3356 delete the feeding insn, which is incorrect.
3358 So force this insn not to match in this (rare) case. */
3359 if (! in_dest && code == REG && GET_CODE (from) == REG
3360 && REGNO (x) == REGNO (from))
3361 return gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
3363 /* If this is an object, we are done unless it is a MEM or LO_SUM, both
3364 of which may contain things that can be combined. */
3365 if (code != MEM && code != LO_SUM && GET_RTX_CLASS (code) == 'o')
3368 /* It is possible to have a subexpression appear twice in the insn.
3369 Suppose that FROM is a register that appears within TO.
3370 Then, after that subexpression has been scanned once by `subst',
3371 the second time it is scanned, TO may be found. If we were
3372 to scan TO here, we would find FROM within it and create a
3373 self-referent rtl structure which is completely wrong. */
3374 if (COMBINE_RTX_EQUAL_P (x, to))
3377 /* Parallel asm_operands need special attention because all of the
3378 inputs are shared across the arms. Furthermore, unsharing the
3379 rtl results in recognition failures. Failure to handle this case
3380 specially can result in circular rtl.
3382 Solve this by doing a normal pass across the first entry of the
3383 parallel, and only processing the SET_DESTs of the subsequent
3386 if (code == PARALLEL
3387 && GET_CODE (XVECEXP (x, 0, 0)) == SET
3388 && GET_CODE (SET_SRC (XVECEXP (x, 0, 0))) == ASM_OPERANDS)
3390 new = subst (XVECEXP (x, 0, 0), from, to, 0, unique_copy);
3392 /* If this substitution failed, this whole thing fails. */
3393 if (GET_CODE (new) == CLOBBER
3394 && XEXP (new, 0) == const0_rtx)
3397 SUBST (XVECEXP (x, 0, 0), new);
3399 for (i = XVECLEN (x, 0) - 1; i >= 1; i--)
3401 rtx dest = SET_DEST (XVECEXP (x, 0, i));
3403 if (GET_CODE (dest) != REG
3404 && GET_CODE (dest) != CC0
3405 && GET_CODE (dest) != PC)
3407 new = subst (dest, from, to, 0, unique_copy);
3409 /* If this substitution failed, this whole thing fails. */
3410 if (GET_CODE (new) == CLOBBER
3411 && XEXP (new, 0) == const0_rtx)
3414 SUBST (SET_DEST (XVECEXP (x, 0, i)), new);
3420 len = GET_RTX_LENGTH (code);
3421 fmt = GET_RTX_FORMAT (code);
3423 /* We don't need to process a SET_DEST that is a register, CC0,
3424 or PC, so set up to skip this common case. All other cases
3425 where we want to suppress replacing something inside a
3426 SET_SRC are handled via the IN_DEST operand. */
3428 && (GET_CODE (SET_DEST (x)) == REG
3429 || GET_CODE (SET_DEST (x)) == CC0
3430 || GET_CODE (SET_DEST (x)) == PC))
3433 /* Get the mode of operand 0 in case X is now a SIGN_EXTEND of a
3436 op0_mode = GET_MODE (XEXP (x, 0));
3438 for (i = 0; i < len; i++)
3443 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
3445 if (COMBINE_RTX_EQUAL_P (XVECEXP (x, i, j), from))
3447 new = (unique_copy && n_occurrences
3448 ? copy_rtx (to) : to);
3453 new = subst (XVECEXP (x, i, j), from, to, 0,
3456 /* If this substitution failed, this whole thing
3458 if (GET_CODE (new) == CLOBBER
3459 && XEXP (new, 0) == const0_rtx)
3463 SUBST (XVECEXP (x, i, j), new);
3466 else if (fmt[i] == 'e')
3468 /* If this is a register being set, ignore it. */
3471 && (code == SUBREG || code == STRICT_LOW_PART
3472 || code == ZERO_EXTRACT)
3474 && GET_CODE (new) == REG)
3477 else if (COMBINE_RTX_EQUAL_P (XEXP (x, i), from))
3479 /* In general, don't install a subreg involving two
3480 modes not tieable. It can worsen register
3481 allocation, and can even make invalid reload
3482 insns, since the reg inside may need to be copied
3483 from in the outside mode, and that may be invalid
3484 if it is an fp reg copied in integer mode.
3486 We allow two exceptions to this: It is valid if
3487 it is inside another SUBREG and the mode of that
3488 SUBREG and the mode of the inside of TO is
3489 tieable and it is valid if X is a SET that copies
3492 if (GET_CODE (to) == SUBREG
3493 && ! MODES_TIEABLE_P (GET_MODE (to),
3494 GET_MODE (SUBREG_REG (to)))
3495 && ! (code == SUBREG
3496 && MODES_TIEABLE_P (GET_MODE (x),
3497 GET_MODE (SUBREG_REG (to))))
3499 && ! (code == SET && i == 1 && XEXP (x, 0) == cc0_rtx)
3502 return gen_rtx_CLOBBER (VOIDmode, const0_rtx);
3504 #ifdef CLASS_CANNOT_CHANGE_MODE
3506 && GET_CODE (to) == REG
3507 && REGNO (to) < FIRST_PSEUDO_REGISTER
3508 && (TEST_HARD_REG_BIT
3509 (reg_class_contents[(int) CLASS_CANNOT_CHANGE_MODE],
3511 && CLASS_CANNOT_CHANGE_MODE_P (GET_MODE (to),
3513 return gen_rtx_CLOBBER (VOIDmode, const0_rtx);
3516 new = (unique_copy && n_occurrences ? copy_rtx (to) : to);
3520 /* If we are in a SET_DEST, suppress most cases unless we
3521 have gone inside a MEM, in which case we want to
3522 simplify the address. We assume here that things that
3523 are actually part of the destination have their inner
3524 parts in the first expression. This is true for SUBREG,
3525 STRICT_LOW_PART, and ZERO_EXTRACT, which are the only
3526 things aside from REG and MEM that should appear in a
3528 new = subst (XEXP (x, i), from, to,
3530 && (code == SUBREG || code == STRICT_LOW_PART
3531 || code == ZERO_EXTRACT))
3533 && i == 0), unique_copy);
3535 /* If we found that we will have to reject this combination,
3536 indicate that by returning the CLOBBER ourselves, rather than
3537 an expression containing it. This will speed things up as
3538 well as prevent accidents where two CLOBBERs are considered
3539 to be equal, thus producing an incorrect simplification. */
3541 if (GET_CODE (new) == CLOBBER && XEXP (new, 0) == const0_rtx)
3544 if (GET_CODE (new) == CONST_INT && GET_CODE (x) == SUBREG)
3546 enum machine_mode mode = GET_MODE (x);
3548 x = simplify_subreg (GET_MODE (x), new,
3549 GET_MODE (SUBREG_REG (x)),
3552 x = gen_rtx_CLOBBER (mode, const0_rtx);
3554 else if (GET_CODE (new) == CONST_INT
3555 && GET_CODE (x) == ZERO_EXTEND)
3557 x = simplify_unary_operation (ZERO_EXTEND, GET_MODE (x),
3558 new, GET_MODE (XEXP (x, 0)));
3563 SUBST (XEXP (x, i), new);
3568 /* Try to simplify X. If the simplification changed the code, it is likely
3569 that further simplification will help, so loop, but limit the number
3570 of repetitions that will be performed. */
3572 for (i = 0; i < 4; i++)
3574 /* If X is sufficiently simple, don't bother trying to do anything
3576 if (code != CONST_INT && code != REG && code != CLOBBER)
3577 x = combine_simplify_rtx (x, op0_mode, i == 3, in_dest);
3579 if (GET_CODE (x) == code)
3582 code = GET_CODE (x);
3584 /* We no longer know the original mode of operand 0 since we
3585 have changed the form of X) */
3586 op0_mode = VOIDmode;
3592 /* Simplify X, a piece of RTL. We just operate on the expression at the
3593 outer level; call `subst' to simplify recursively. Return the new
3596 OP0_MODE is the original mode of XEXP (x, 0); LAST is nonzero if this
3597 will be the iteration even if an expression with a code different from
3598 X is returned; IN_DEST is nonzero if we are inside a SET_DEST. */
3601 combine_simplify_rtx (x, op0_mode, last, in_dest)
3603 enum machine_mode op0_mode;
3607 enum rtx_code code = GET_CODE (x);
3608 enum machine_mode mode = GET_MODE (x);
3613 /* If this is a commutative operation, put a constant last and a complex
3614 expression first. We don't need to do this for comparisons here. */
3615 if (GET_RTX_CLASS (code) == 'c'
3616 && swap_commutative_operands_p (XEXP (x, 0), XEXP (x, 1)))
3619 SUBST (XEXP (x, 0), XEXP (x, 1));
3620 SUBST (XEXP (x, 1), temp);
3623 /* If this is a PLUS, MINUS, or MULT, and the first operand is the
3624 sign extension of a PLUS with a constant, reverse the order of the sign
3625 extension and the addition. Note that this not the same as the original
3626 code, but overflow is undefined for signed values. Also note that the
3627 PLUS will have been partially moved "inside" the sign-extension, so that
3628 the first operand of X will really look like:
3629 (ashiftrt (plus (ashift A C4) C5) C4).
3631 (plus (ashiftrt (ashift A C4) C2) C4)
3632 and replace the first operand of X with that expression. Later parts
3633 of this function may simplify the expression further.
3635 For example, if we start with (mult (sign_extend (plus A C1)) C2),
3636 we swap the SIGN_EXTEND and PLUS. Later code will apply the
3637 distributive law to produce (plus (mult (sign_extend X) C1) C3).
3639 We do this to simplify address expressions. */
3641 if ((code == PLUS || code == MINUS || code == MULT)
3642 && GET_CODE (XEXP (x, 0)) == ASHIFTRT
3643 && GET_CODE (XEXP (XEXP (x, 0), 0)) == PLUS
3644 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == ASHIFT
3645 && GET_CODE (XEXP (XEXP (XEXP (XEXP (x, 0), 0), 0), 1)) == CONST_INT
3646 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3647 && XEXP (XEXP (XEXP (XEXP (x, 0), 0), 0), 1) == XEXP (XEXP (x, 0), 1)
3648 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == CONST_INT
3649 && (temp = simplify_binary_operation (ASHIFTRT, mode,
3650 XEXP (XEXP (XEXP (x, 0), 0), 1),
3651 XEXP (XEXP (x, 0), 1))) != 0)
3654 = simplify_shift_const (NULL_RTX, ASHIFT, mode,
3655 XEXP (XEXP (XEXP (XEXP (x, 0), 0), 0), 0),
3656 INTVAL (XEXP (XEXP (x, 0), 1)));
3658 new = simplify_shift_const (NULL_RTX, ASHIFTRT, mode, new,
3659 INTVAL (XEXP (XEXP (x, 0), 1)));
3661 SUBST (XEXP (x, 0), gen_binary (PLUS, mode, new, temp));
3664 /* If this is a simple operation applied to an IF_THEN_ELSE, try
3665 applying it to the arms of the IF_THEN_ELSE. This often simplifies
3666 things. Check for cases where both arms are testing the same
3669 Don't do anything if all operands are very simple. */
3671 if (((GET_RTX_CLASS (code) == '2' || GET_RTX_CLASS (code) == 'c'
3672 || GET_RTX_CLASS (code) == '<')
3673 && ((GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) != 'o'
3674 && ! (GET_CODE (XEXP (x, 0)) == SUBREG
3675 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 0))))
3677 || (GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) != 'o'
3678 && ! (GET_CODE (XEXP (x, 1)) == SUBREG
3679 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 1))))
3681 || (GET_RTX_CLASS (code) == '1'
3682 && ((GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) != 'o'
3683 && ! (GET_CODE (XEXP (x, 0)) == SUBREG
3684 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 0))))
3687 rtx cond, true_rtx, false_rtx;
3689 cond = if_then_else_cond (x, &true_rtx, &false_rtx);
3691 /* If everything is a comparison, what we have is highly unlikely
3692 to be simpler, so don't use it. */
3693 && ! (GET_RTX_CLASS (code) == '<'
3694 && (GET_RTX_CLASS (GET_CODE (true_rtx)) == '<'
3695 || GET_RTX_CLASS (GET_CODE (false_rtx)) == '<')))
3697 rtx cop1 = const0_rtx;
3698 enum rtx_code cond_code = simplify_comparison (NE, &cond, &cop1);
3700 if (cond_code == NE && GET_RTX_CLASS (GET_CODE (cond)) == '<')
3703 /* Simplify the alternative arms; this may collapse the true and
3704 false arms to store-flag values. */
3705 true_rtx = subst (true_rtx, pc_rtx, pc_rtx, 0, 0);
3706 false_rtx = subst (false_rtx, pc_rtx, pc_rtx, 0, 0);
3708 /* If true_rtx and false_rtx are not general_operands, an if_then_else
3709 is unlikely to be simpler. */
3710 if (general_operand (true_rtx, VOIDmode)
3711 && general_operand (false_rtx, VOIDmode))
3713 /* Restarting if we generate a store-flag expression will cause
3714 us to loop. Just drop through in this case. */
3716 /* If the result values are STORE_FLAG_VALUE and zero, we can
3717 just make the comparison operation. */
3718 if (true_rtx == const_true_rtx && false_rtx == const0_rtx)
3719 x = gen_binary (cond_code, mode, cond, cop1);
3720 else if (true_rtx == const0_rtx && false_rtx == const_true_rtx
3721 && reverse_condition (cond_code) != UNKNOWN)
3722 x = gen_binary (reverse_condition (cond_code),
3725 /* Likewise, we can make the negate of a comparison operation
3726 if the result values are - STORE_FLAG_VALUE and zero. */
3727 else if (GET_CODE (true_rtx) == CONST_INT
3728 && INTVAL (true_rtx) == - STORE_FLAG_VALUE
3729 && false_rtx == const0_rtx)
3730 x = simplify_gen_unary (NEG, mode,
3731 gen_binary (cond_code, mode, cond,
3734 else if (GET_CODE (false_rtx) == CONST_INT
3735 && INTVAL (false_rtx) == - STORE_FLAG_VALUE
3736 && true_rtx == const0_rtx)
3737 x = simplify_gen_unary (NEG, mode,
3738 gen_binary (reverse_condition
3743 return gen_rtx_IF_THEN_ELSE (mode,
3744 gen_binary (cond_code, VOIDmode,
3746 true_rtx, false_rtx);
3748 code = GET_CODE (x);
3749 op0_mode = VOIDmode;
3754 /* Try to fold this expression in case we have constants that weren't
3757 switch (GET_RTX_CLASS (code))
3760 temp = simplify_unary_operation (code, mode, XEXP (x, 0), op0_mode);
3764 enum machine_mode cmp_mode = GET_MODE (XEXP (x, 0));
3765 if (cmp_mode == VOIDmode)
3767 cmp_mode = GET_MODE (XEXP (x, 1));
3768 if (cmp_mode == VOIDmode)
3769 cmp_mode = op0_mode;
3771 temp = simplify_relational_operation (code, cmp_mode,
3772 XEXP (x, 0), XEXP (x, 1));
3774 #ifdef FLOAT_STORE_FLAG_VALUE
3775 if (temp != 0 && GET_MODE_CLASS (mode) == MODE_FLOAT)
3777 if (temp == const0_rtx)
3778 temp = CONST0_RTX (mode);
3780 temp = CONST_DOUBLE_FROM_REAL_VALUE (FLOAT_STORE_FLAG_VALUE (mode),
3787 temp = simplify_binary_operation (code, mode, XEXP (x, 0), XEXP (x, 1));
3791 temp = simplify_ternary_operation (code, mode, op0_mode, XEXP (x, 0),
3792 XEXP (x, 1), XEXP (x, 2));
3799 code = GET_CODE (temp);
3800 op0_mode = VOIDmode;
3801 mode = GET_MODE (temp);
3804 /* First see if we can apply the inverse distributive law. */
3805 if (code == PLUS || code == MINUS
3806 || code == AND || code == IOR || code == XOR)
3808 x = apply_distributive_law (x);
3809 code = GET_CODE (x);
3810 op0_mode = VOIDmode;
3813 /* If CODE is an associative operation not otherwise handled, see if we
3814 can associate some operands. This can win if they are constants or
3815 if they are logically related (i.e. (a & b) & a). */
3816 if ((code == PLUS || code == MINUS || code == MULT || code == DIV
3817 || code == AND || code == IOR || code == XOR
3818 || code == SMAX || code == SMIN || code == UMAX || code == UMIN)
3819 && ((INTEGRAL_MODE_P (mode) && code != DIV)
3820 || (flag_unsafe_math_optimizations && FLOAT_MODE_P (mode))))
3822 if (GET_CODE (XEXP (x, 0)) == code)
3824 rtx other = XEXP (XEXP (x, 0), 0);
3825 rtx inner_op0 = XEXP (XEXP (x, 0), 1);
3826 rtx inner_op1 = XEXP (x, 1);
3829 /* Make sure we pass the constant operand if any as the second
3830 one if this is a commutative operation. */
3831 if (CONSTANT_P (inner_op0) && GET_RTX_CLASS (code) == 'c')
3833 rtx tem = inner_op0;
3834 inner_op0 = inner_op1;
3837 inner = simplify_binary_operation (code == MINUS ? PLUS
3838 : code == DIV ? MULT
3840 mode, inner_op0, inner_op1);
3842 /* For commutative operations, try the other pair if that one
3844 if (inner == 0 && GET_RTX_CLASS (code) == 'c')
3846 other = XEXP (XEXP (x, 0), 1);
3847 inner = simplify_binary_operation (code, mode,
3848 XEXP (XEXP (x, 0), 0),
3853 return gen_binary (code, mode, other, inner);
3857 /* A little bit of algebraic simplification here. */
3861 /* Ensure that our address has any ASHIFTs converted to MULT in case
3862 address-recognizing predicates are called later. */
3863 temp = make_compound_operation (XEXP (x, 0), MEM);
3864 SUBST (XEXP (x, 0), temp);
3868 if (op0_mode == VOIDmode)
3869 op0_mode = GET_MODE (SUBREG_REG (x));
3871 /* simplify_subreg can't use gen_lowpart_for_combine. */
3872 if (CONSTANT_P (SUBREG_REG (x))
3873 && subreg_lowpart_offset (mode, op0_mode) == SUBREG_BYTE (x)
3874 /* Don't call gen_lowpart_for_combine if the inner mode
3875 is VOIDmode and we cannot simplify it, as SUBREG without
3876 inner mode is invalid. */
3877 && (GET_MODE (SUBREG_REG (x)) != VOIDmode
3878 || gen_lowpart_common (mode, SUBREG_REG (x))))
3879 return gen_lowpart_for_combine (mode, SUBREG_REG (x));
3881 if (GET_MODE_CLASS (GET_MODE (SUBREG_REG (x))) == MODE_CC)
3885 temp = simplify_subreg (mode, SUBREG_REG (x), op0_mode,
3891 /* Don't change the mode of the MEM if that would change the meaning
3893 if (GET_CODE (SUBREG_REG (x)) == MEM
3894 && (MEM_VOLATILE_P (SUBREG_REG (x))
3895 || mode_dependent_address_p (XEXP (SUBREG_REG (x), 0))))
3896 return gen_rtx_CLOBBER (mode, const0_rtx);
3898 /* Note that we cannot do any narrowing for non-constants since
3899 we might have been counting on using the fact that some bits were
3900 zero. We now do this in the SET. */
3905 /* (not (plus X -1)) can become (neg X). */
3906 if (GET_CODE (XEXP (x, 0)) == PLUS
3907 && XEXP (XEXP (x, 0), 1) == constm1_rtx)
3908 return gen_rtx_NEG (mode, XEXP (XEXP (x, 0), 0));
3910 /* Similarly, (not (neg X)) is (plus X -1). */
3911 if (GET_CODE (XEXP (x, 0)) == NEG)
3912 return gen_rtx_PLUS (mode, XEXP (XEXP (x, 0), 0), constm1_rtx);
3914 /* (not (xor X C)) for C constant is (xor X D) with D = ~C. */
3915 if (GET_CODE (XEXP (x, 0)) == XOR
3916 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3917 && (temp = simplify_unary_operation (NOT, mode,
3918 XEXP (XEXP (x, 0), 1),
3920 return gen_binary (XOR, mode, XEXP (XEXP (x, 0), 0), temp);
3922 /* (not (ashift 1 X)) is (rotate ~1 X). We used to do this for operands
3923 other than 1, but that is not valid. We could do a similar
3924 simplification for (not (lshiftrt C X)) where C is just the sign bit,
3925 but this doesn't seem common enough to bother with. */
3926 if (GET_CODE (XEXP (x, 0)) == ASHIFT
3927 && XEXP (XEXP (x, 0), 0) == const1_rtx)
3928 return gen_rtx_ROTATE (mode, simplify_gen_unary (NOT, mode,
3930 XEXP (XEXP (x, 0), 1));
3932 if (GET_CODE (XEXP (x, 0)) == SUBREG
3933 && subreg_lowpart_p (XEXP (x, 0))
3934 && (GET_MODE_SIZE (GET_MODE (XEXP (x, 0)))
3935 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (x, 0)))))
3936 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == ASHIFT
3937 && XEXP (SUBREG_REG (XEXP (x, 0)), 0) == const1_rtx)
3939 enum machine_mode inner_mode = GET_MODE (SUBREG_REG (XEXP (x, 0)));
3941 x = gen_rtx_ROTATE (inner_mode,
3942 simplify_gen_unary (NOT, inner_mode, const1_rtx,
3944 XEXP (SUBREG_REG (XEXP (x, 0)), 1));
3945 return gen_lowpart_for_combine (mode, x);
3948 /* If STORE_FLAG_VALUE is -1, (not (comparison foo bar)) can be done by
3949 reversing the comparison code if valid. */
3950 if (STORE_FLAG_VALUE == -1
3951 && GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
3952 && (reversed = reversed_comparison (x, mode, XEXP (XEXP (x, 0), 0),
3953 XEXP (XEXP (x, 0), 1))))
3956 /* (not (ashiftrt foo C)) where C is the number of bits in FOO minus 1
3957 is (ge foo (const_int 0)) if STORE_FLAG_VALUE is -1, so we can
3958 perform the above simplification. */
3960 if (STORE_FLAG_VALUE == -1
3961 && GET_CODE (XEXP (x, 0)) == ASHIFTRT
3962 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3963 && INTVAL (XEXP (XEXP (x, 0), 1)) == GET_MODE_BITSIZE (mode) - 1)
3964 return gen_rtx_GE (mode, XEXP (XEXP (x, 0), 0), const0_rtx);
3966 /* Apply De Morgan's laws to reduce number of patterns for machines
3967 with negating logical insns (and-not, nand, etc.). If result has
3968 only one NOT, put it first, since that is how the patterns are
3971 if (GET_CODE (XEXP (x, 0)) == IOR || GET_CODE (XEXP (x, 0)) == AND)
3973 rtx in1 = XEXP (XEXP (x, 0), 0), in2 = XEXP (XEXP (x, 0), 1);
3974 enum machine_mode op_mode;
3976 op_mode = GET_MODE (in1);
3977 in1 = simplify_gen_unary (NOT, op_mode, in1, op_mode);
3979 op_mode = GET_MODE (in2);
3980 if (op_mode == VOIDmode)
3982 in2 = simplify_gen_unary (NOT, op_mode, in2, op_mode);
3984 if (GET_CODE (in2) == NOT && GET_CODE (in1) != NOT)
3987 in2 = in1; in1 = tem;
3990 return gen_rtx_fmt_ee (GET_CODE (XEXP (x, 0)) == IOR ? AND : IOR,
3996 /* (neg (plus X 1)) can become (not X). */
3997 if (GET_CODE (XEXP (x, 0)) == PLUS
3998 && XEXP (XEXP (x, 0), 1) == const1_rtx)
3999 return gen_rtx_NOT (mode, XEXP (XEXP (x, 0), 0));
4001 /* Similarly, (neg (not X)) is (plus X 1). */
4002 if (GET_CODE (XEXP (x, 0)) == NOT)
4003 return plus_constant (XEXP (XEXP (x, 0), 0), 1);
4005 /* (neg (minus X Y)) can become (minus Y X). This transformation
4006 isn't safe for modes with signed zeros, since if X and Y are
4007 both +0, (minus Y X) is the same as (minus X Y). If the rounding
4008 mode is towards +infinity (or -infinity) then the two expressions
4009 will be rounded differently. */
4010 if (GET_CODE (XEXP (x, 0)) == MINUS
4011 && !HONOR_SIGNED_ZEROS (mode)
4012 && !HONOR_SIGN_DEPENDENT_ROUNDING (mode))
4013 return gen_binary (MINUS, mode, XEXP (XEXP (x, 0), 1),
4014 XEXP (XEXP (x, 0), 0));
4016 /* (neg (xor A 1)) is (plus A -1) if A is known to be either 0 or 1. */
4017 if (GET_CODE (XEXP (x, 0)) == XOR && XEXP (XEXP (x, 0), 1) == const1_rtx
4018 && nonzero_bits (XEXP (XEXP (x, 0), 0), mode) == 1)
4019 return gen_binary (PLUS, mode, XEXP (XEXP (x, 0), 0), constm1_rtx);
4021 /* NEG commutes with ASHIFT since it is multiplication. Only do this
4022 if we can then eliminate the NEG (e.g.,
4023 if the operand is a constant). */
4025 if (GET_CODE (XEXP (x, 0)) == ASHIFT)
4027 temp = simplify_unary_operation (NEG, mode,
4028 XEXP (XEXP (x, 0), 0), mode);
4030 return gen_binary (ASHIFT, mode, temp, XEXP (XEXP (x, 0), 1));
4033 temp = expand_compound_operation (XEXP (x, 0));
4035 /* For C equal to the width of MODE minus 1, (neg (ashiftrt X C)) can be
4036 replaced by (lshiftrt X C). This will convert
4037 (neg (sign_extract X 1 Y)) to (zero_extract X 1 Y). */
4039 if (GET_CODE (temp) == ASHIFTRT
4040 && GET_CODE (XEXP (temp, 1)) == CONST_INT
4041 && INTVAL (XEXP (temp, 1)) == GET_MODE_BITSIZE (mode) - 1)
4042 return simplify_shift_const (temp, LSHIFTRT, mode, XEXP (temp, 0),
4043 INTVAL (XEXP (temp, 1)));
4045 /* If X has only a single bit that might be nonzero, say, bit I, convert
4046 (neg X) to (ashiftrt (ashift X C-I) C-I) where C is the bitsize of
4047 MODE minus 1. This will convert (neg (zero_extract X 1 Y)) to
4048 (sign_extract X 1 Y). But only do this if TEMP isn't a register
4049 or a SUBREG of one since we'd be making the expression more
4050 complex if it was just a register. */
4052 if (GET_CODE (temp) != REG
4053 && ! (GET_CODE (temp) == SUBREG
4054 && GET_CODE (SUBREG_REG (temp)) == REG)
4055 && (i = exact_log2 (nonzero_bits (temp, mode))) >= 0)
4057 rtx temp1 = simplify_shift_const
4058 (NULL_RTX, ASHIFTRT, mode,
4059 simplify_shift_const (NULL_RTX, ASHIFT, mode, temp,
4060 GET_MODE_BITSIZE (mode) - 1 - i),
4061 GET_MODE_BITSIZE (mode) - 1 - i);
4063 /* If all we did was surround TEMP with the two shifts, we
4064 haven't improved anything, so don't use it. Otherwise,
4065 we are better off with TEMP1. */
4066 if (GET_CODE (temp1) != ASHIFTRT
4067 || GET_CODE (XEXP (temp1, 0)) != ASHIFT
4068 || XEXP (XEXP (temp1, 0), 0) != temp)
4074 /* We can't handle truncation to a partial integer mode here
4075 because we don't know the real bitsize of the partial
4077 if (GET_MODE_CLASS (mode) == MODE_PARTIAL_INT)
4080 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4081 && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode),
4082 GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))))
4084 force_to_mode (XEXP (x, 0), GET_MODE (XEXP (x, 0)),
4085 GET_MODE_MASK (mode), NULL_RTX, 0));
4087 /* (truncate:SI ({sign,zero}_extend:DI foo:SI)) == foo:SI. */
4088 if ((GET_CODE (XEXP (x, 0)) == SIGN_EXTEND
4089 || GET_CODE (XEXP (x, 0)) == ZERO_EXTEND)
4090 && GET_MODE (XEXP (XEXP (x, 0), 0)) == mode)
4091 return XEXP (XEXP (x, 0), 0);
4093 /* (truncate:SI (OP:DI ({sign,zero}_extend:DI foo:SI))) is
4094 (OP:SI foo:SI) if OP is NEG or ABS. */
4095 if ((GET_CODE (XEXP (x, 0)) == ABS
4096 || GET_CODE (XEXP (x, 0)) == NEG)
4097 && (GET_CODE (XEXP (XEXP (x, 0), 0)) == SIGN_EXTEND
4098 || GET_CODE (XEXP (XEXP (x, 0), 0)) == ZERO_EXTEND)
4099 && GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == mode)
4100 return simplify_gen_unary (GET_CODE (XEXP (x, 0)), mode,
4101 XEXP (XEXP (XEXP (x, 0), 0), 0), mode);
4103 /* (truncate:SI (subreg:DI (truncate:SI X) 0)) is
4105 if (GET_CODE (XEXP (x, 0)) == SUBREG
4106 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == TRUNCATE
4107 && subreg_lowpart_p (XEXP (x, 0)))
4108 return SUBREG_REG (XEXP (x, 0));
4110 /* If we know that the value is already truncated, we can
4111 replace the TRUNCATE with a SUBREG if TRULY_NOOP_TRUNCATION
4112 is nonzero for the corresponding modes. But don't do this
4113 for an (LSHIFTRT (MULT ...)) since this will cause problems
4114 with the umulXi3_highpart patterns. */
4115 if (TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode),
4116 GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))))
4117 && num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
4118 >= (unsigned int) (GET_MODE_BITSIZE (mode) + 1)
4119 && ! (GET_CODE (XEXP (x, 0)) == LSHIFTRT
4120 && GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT))
4121 return gen_lowpart_for_combine (mode, XEXP (x, 0));
4123 /* A truncate of a comparison can be replaced with a subreg if
4124 STORE_FLAG_VALUE permits. This is like the previous test,
4125 but it works even if the comparison is done in a mode larger
4126 than HOST_BITS_PER_WIDE_INT. */
4127 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4128 && GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
4129 && ((HOST_WIDE_INT) STORE_FLAG_VALUE & ~GET_MODE_MASK (mode)) == 0)
4130 return gen_lowpart_for_combine (mode, XEXP (x, 0));
4132 /* Similarly, a truncate of a register whose value is a
4133 comparison can be replaced with a subreg if STORE_FLAG_VALUE
4135 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4136 && ((HOST_WIDE_INT) STORE_FLAG_VALUE & ~GET_MODE_MASK (mode)) == 0
4137 && (temp = get_last_value (XEXP (x, 0)))
4138 && GET_RTX_CLASS (GET_CODE (temp)) == '<')
4139 return gen_lowpart_for_combine (mode, XEXP (x, 0));
4143 case FLOAT_TRUNCATE:
4144 /* (float_truncate:SF (float_extend:DF foo:SF)) = foo:SF. */
4145 if (GET_CODE (XEXP (x, 0)) == FLOAT_EXTEND
4146 && GET_MODE (XEXP (XEXP (x, 0), 0)) == mode)
4147 return XEXP (XEXP (x, 0), 0);
4149 /* (float_truncate:SF (OP:DF (float_extend:DF foo:sf))) is
4150 (OP:SF foo:SF) if OP is NEG or ABS. */
4151 if ((GET_CODE (XEXP (x, 0)) == ABS
4152 || GET_CODE (XEXP (x, 0)) == NEG)
4153 && GET_CODE (XEXP (XEXP (x, 0), 0)) == FLOAT_EXTEND
4154 && GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == mode)
4155 return simplify_gen_unary (GET_CODE (XEXP (x, 0)), mode,
4156 XEXP (XEXP (XEXP (x, 0), 0), 0), mode);
4158 /* (float_truncate:SF (subreg:DF (float_truncate:SF X) 0))
4159 is (float_truncate:SF x). */
4160 if (GET_CODE (XEXP (x, 0)) == SUBREG
4161 && subreg_lowpart_p (XEXP (x, 0))
4162 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == FLOAT_TRUNCATE)
4163 return SUBREG_REG (XEXP (x, 0));
4168 /* Convert (compare FOO (const_int 0)) to FOO unless we aren't
4169 using cc0, in which case we want to leave it as a COMPARE
4170 so we can distinguish it from a register-register-copy. */
4171 if (XEXP (x, 1) == const0_rtx)
4174 /* x - 0 is the same as x unless x's mode has signed zeros and
4175 allows rounding towards -infinity. Under those conditions,
4177 if (!(HONOR_SIGNED_ZEROS (GET_MODE (XEXP (x, 0)))
4178 && HONOR_SIGN_DEPENDENT_ROUNDING (GET_MODE (XEXP (x, 0))))
4179 && XEXP (x, 1) == CONST0_RTX (GET_MODE (XEXP (x, 0))))
4185 /* (const (const X)) can become (const X). Do it this way rather than
4186 returning the inner CONST since CONST can be shared with a
4188 if (GET_CODE (XEXP (x, 0)) == CONST)
4189 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4194 /* Convert (lo_sum (high FOO) FOO) to FOO. This is necessary so we
4195 can add in an offset. find_split_point will split this address up
4196 again if it doesn't match. */
4197 if (GET_CODE (XEXP (x, 0)) == HIGH
4198 && rtx_equal_p (XEXP (XEXP (x, 0), 0), XEXP (x, 1)))
4204 /* If we have (plus (plus (A const) B)), associate it so that CONST is
4205 outermost. That's because that's the way indexed addresses are
4206 supposed to appear. This code used to check many more cases, but
4207 they are now checked elsewhere. */
4208 if (GET_CODE (XEXP (x, 0)) == PLUS
4209 && CONSTANT_ADDRESS_P (XEXP (XEXP (x, 0), 1)))
4210 return gen_binary (PLUS, mode,
4211 gen_binary (PLUS, mode, XEXP (XEXP (x, 0), 0),
4213 XEXP (XEXP (x, 0), 1));
4215 /* (plus (xor (and <foo> (const_int pow2 - 1)) <c>) <-c>)
4216 when c is (const_int (pow2 + 1) / 2) is a sign extension of a
4217 bit-field and can be replaced by either a sign_extend or a
4218 sign_extract. The `and' may be a zero_extend and the two
4219 <c>, -<c> constants may be reversed. */
4220 if (GET_CODE (XEXP (x, 0)) == XOR
4221 && GET_CODE (XEXP (x, 1)) == CONST_INT
4222 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
4223 && INTVAL (XEXP (x, 1)) == -INTVAL (XEXP (XEXP (x, 0), 1))
4224 && ((i = exact_log2 (INTVAL (XEXP (XEXP (x, 0), 1)))) >= 0
4225 || (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0)
4226 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4227 && ((GET_CODE (XEXP (XEXP (x, 0), 0)) == AND
4228 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == CONST_INT
4229 && (INTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1))
4230 == ((HOST_WIDE_INT) 1 << (i + 1)) - 1))
4231 || (GET_CODE (XEXP (XEXP (x, 0), 0)) == ZERO_EXTEND
4232 && (GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)))
4233 == (unsigned int) i + 1))))
4234 return simplify_shift_const
4235 (NULL_RTX, ASHIFTRT, mode,
4236 simplify_shift_const (NULL_RTX, ASHIFT, mode,
4237 XEXP (XEXP (XEXP (x, 0), 0), 0),
4238 GET_MODE_BITSIZE (mode) - (i + 1)),
4239 GET_MODE_BITSIZE (mode) - (i + 1));
4241 /* (plus (comparison A B) C) can become (neg (rev-comp A B)) if
4242 C is 1 and STORE_FLAG_VALUE is -1 or if C is -1 and STORE_FLAG_VALUE
4243 is 1. This produces better code than the alternative immediately
4245 if (GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
4246 && ((STORE_FLAG_VALUE == -1 && XEXP (x, 1) == const1_rtx)
4247 || (STORE_FLAG_VALUE == 1 && XEXP (x, 1) == constm1_rtx))
4248 && (reversed = reversed_comparison (XEXP (x, 0), mode,
4249 XEXP (XEXP (x, 0), 0),
4250 XEXP (XEXP (x, 0), 1))))
4252 simplify_gen_unary (NEG, mode, reversed, mode);
4254 /* If only the low-order bit of X is possibly nonzero, (plus x -1)
4255 can become (ashiftrt (ashift (xor x 1) C) C) where C is
4256 the bitsize of the mode - 1. This allows simplification of
4257 "a = (b & 8) == 0;" */
4258 if (XEXP (x, 1) == constm1_rtx
4259 && GET_CODE (XEXP (x, 0)) != REG
4260 && ! (GET_CODE (XEXP (x,0)) == SUBREG
4261 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == REG)
4262 && nonzero_bits (XEXP (x, 0), mode) == 1)
4263 return simplify_shift_const (NULL_RTX, ASHIFTRT, mode,
4264 simplify_shift_const (NULL_RTX, ASHIFT, mode,
4265 gen_rtx_XOR (mode, XEXP (x, 0), const1_rtx),
4266 GET_MODE_BITSIZE (mode) - 1),
4267 GET_MODE_BITSIZE (mode) - 1);
4269 /* If we are adding two things that have no bits in common, convert
4270 the addition into an IOR. This will often be further simplified,
4271 for example in cases like ((a & 1) + (a & 2)), which can
4274 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4275 && (nonzero_bits (XEXP (x, 0), mode)
4276 & nonzero_bits (XEXP (x, 1), mode)) == 0)
4278 /* Try to simplify the expression further. */
4279 rtx tor = gen_binary (IOR, mode, XEXP (x, 0), XEXP (x, 1));
4280 temp = combine_simplify_rtx (tor, mode, last, in_dest);
4282 /* If we could, great. If not, do not go ahead with the IOR
4283 replacement, since PLUS appears in many special purpose
4284 address arithmetic instructions. */
4285 if (GET_CODE (temp) != CLOBBER && temp != tor)
4291 /* If STORE_FLAG_VALUE is 1, (minus 1 (comparison foo bar)) can be done
4292 by reversing the comparison code if valid. */
4293 if (STORE_FLAG_VALUE == 1
4294 && XEXP (x, 0) == const1_rtx
4295 && GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) == '<'
4296 && (reversed = reversed_comparison (XEXP (x, 1), mode,
4297 XEXP (XEXP (x, 1), 0),
4298 XEXP (XEXP (x, 1), 1))))
4301 /* (minus <foo> (and <foo> (const_int -pow2))) becomes
4302 (and <foo> (const_int pow2-1)) */
4303 if (GET_CODE (XEXP (x, 1)) == AND
4304 && GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT
4305 && exact_log2 (-INTVAL (XEXP (XEXP (x, 1), 1))) >= 0
4306 && rtx_equal_p (XEXP (XEXP (x, 1), 0), XEXP (x, 0)))
4307 return simplify_and_const_int (NULL_RTX, mode, XEXP (x, 0),
4308 -INTVAL (XEXP (XEXP (x, 1), 1)) - 1);
4310 /* Canonicalize (minus A (plus B C)) to (minus (minus A B) C) for
4312 if (GET_CODE (XEXP (x, 1)) == PLUS && INTEGRAL_MODE_P (mode))
4313 return gen_binary (MINUS, mode,
4314 gen_binary (MINUS, mode, XEXP (x, 0),
4315 XEXP (XEXP (x, 1), 0)),
4316 XEXP (XEXP (x, 1), 1));
4320 /* If we have (mult (plus A B) C), apply the distributive law and then
4321 the inverse distributive law to see if things simplify. This
4322 occurs mostly in addresses, often when unrolling loops. */
4324 if (GET_CODE (XEXP (x, 0)) == PLUS)
4326 x = apply_distributive_law
4327 (gen_binary (PLUS, mode,
4328 gen_binary (MULT, mode,
4329 XEXP (XEXP (x, 0), 0), XEXP (x, 1)),
4330 gen_binary (MULT, mode,
4331 XEXP (XEXP (x, 0), 1),
4332 copy_rtx (XEXP (x, 1)))));
4334 if (GET_CODE (x) != MULT)
4337 /* Try simplify a*(b/c) as (a*b)/c. */
4338 if (FLOAT_MODE_P (mode) && flag_unsafe_math_optimizations
4339 && GET_CODE (XEXP (x, 0)) == DIV)
4341 rtx tem = simplify_binary_operation (MULT, mode,
4342 XEXP (XEXP (x, 0), 0),
4345 return gen_binary (DIV, mode, tem, XEXP (XEXP (x, 0), 1));
4350 /* If this is a divide by a power of two, treat it as a shift if
4351 its first operand is a shift. */
4352 if (GET_CODE (XEXP (x, 1)) == CONST_INT
4353 && (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0
4354 && (GET_CODE (XEXP (x, 0)) == ASHIFT
4355 || GET_CODE (XEXP (x, 0)) == LSHIFTRT
4356 || GET_CODE (XEXP (x, 0)) == ASHIFTRT
4357 || GET_CODE (XEXP (x, 0)) == ROTATE
4358 || GET_CODE (XEXP (x, 0)) == ROTATERT))
4359 return simplify_shift_const (NULL_RTX, LSHIFTRT, mode, XEXP (x, 0), i);
4363 case GT: case GTU: case GE: case GEU:
4364 case LT: case LTU: case LE: case LEU:
4365 case UNEQ: case LTGT:
4366 case UNGT: case UNGE:
4367 case UNLT: case UNLE:
4368 case UNORDERED: case ORDERED:
4369 /* If the first operand is a condition code, we can't do anything
4371 if (GET_CODE (XEXP (x, 0)) == COMPARE
4372 || (GET_MODE_CLASS (GET_MODE (XEXP (x, 0))) != MODE_CC
4374 && XEXP (x, 0) != cc0_rtx
4378 rtx op0 = XEXP (x, 0);
4379 rtx op1 = XEXP (x, 1);
4380 enum rtx_code new_code;
4382 if (GET_CODE (op0) == COMPARE)
4383 op1 = XEXP (op0, 1), op0 = XEXP (op0, 0);
4385 /* Simplify our comparison, if possible. */
4386 new_code = simplify_comparison (code, &op0, &op1);
4388 /* If STORE_FLAG_VALUE is 1, we can convert (ne x 0) to simply X
4389 if only the low-order bit is possibly nonzero in X (such as when
4390 X is a ZERO_EXTRACT of one bit). Similarly, we can convert EQ to
4391 (xor X 1) or (minus 1 X); we use the former. Finally, if X is
4392 known to be either 0 or -1, NE becomes a NEG and EQ becomes
4395 Remove any ZERO_EXTRACT we made when thinking this was a
4396 comparison. It may now be simpler to use, e.g., an AND. If a
4397 ZERO_EXTRACT is indeed appropriate, it will be placed back by
4398 the call to make_compound_operation in the SET case. */
4400 if (STORE_FLAG_VALUE == 1
4401 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4402 && op1 == const0_rtx
4403 && mode == GET_MODE (op0)
4404 && nonzero_bits (op0, mode) == 1)
4405 return gen_lowpart_for_combine (mode,
4406 expand_compound_operation (op0));
4408 else if (STORE_FLAG_VALUE == 1
4409 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4410 && op1 == const0_rtx
4411 && mode == GET_MODE (op0)
4412 && (num_sign_bit_copies (op0, mode)
4413 == GET_MODE_BITSIZE (mode)))
4415 op0 = expand_compound_operation (op0);
4416 return simplify_gen_unary (NEG, mode,
4417 gen_lowpart_for_combine (mode, op0),
4421 else if (STORE_FLAG_VALUE == 1
4422 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
4423 && op1 == const0_rtx
4424 && mode == GET_MODE (op0)
4425 && nonzero_bits (op0, mode) == 1)
4427 op0 = expand_compound_operation (op0);
4428 return gen_binary (XOR, mode,
4429 gen_lowpart_for_combine (mode, op0),
4433 else if (STORE_FLAG_VALUE == 1
4434 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
4435 && op1 == const0_rtx
4436 && mode == GET_MODE (op0)
4437 && (num_sign_bit_copies (op0, mode)
4438 == GET_MODE_BITSIZE (mode)))
4440 op0 = expand_compound_operation (op0);
4441 return plus_constant (gen_lowpart_for_combine (mode, op0), 1);
4444 /* If STORE_FLAG_VALUE is -1, we have cases similar to
4446 if (STORE_FLAG_VALUE == -1
4447 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4448 && op1 == const0_rtx
4449 && (num_sign_bit_copies (op0, mode)
4450 == GET_MODE_BITSIZE (mode)))
4451 return gen_lowpart_for_combine (mode,
4452 expand_compound_operation (op0));
4454 else if (STORE_FLAG_VALUE == -1
4455 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4456 && op1 == const0_rtx
4457 && mode == GET_MODE (op0)
4458 && nonzero_bits (op0, mode) == 1)
4460 op0 = expand_compound_operation (op0);
4461 return simplify_gen_unary (NEG, mode,
4462 gen_lowpart_for_combine (mode, op0),
4466 else if (STORE_FLAG_VALUE == -1
4467 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
4468 && op1 == const0_rtx
4469 && mode == GET_MODE (op0)
4470 && (num_sign_bit_copies (op0, mode)
4471 == GET_MODE_BITSIZE (mode)))
4473 op0 = expand_compound_operation (op0);
4474 return simplify_gen_unary (NOT, mode,
4475 gen_lowpart_for_combine (mode, op0),
4479 /* If X is 0/1, (eq X 0) is X-1. */
4480 else if (STORE_FLAG_VALUE == -1
4481 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
4482 && op1 == const0_rtx
4483 && mode == GET_MODE (op0)
4484 && nonzero_bits (op0, mode) == 1)
4486 op0 = expand_compound_operation (op0);
4487 return plus_constant (gen_lowpart_for_combine (mode, op0), -1);
4490 /* If STORE_FLAG_VALUE says to just test the sign bit and X has just
4491 one bit that might be nonzero, we can convert (ne x 0) to
4492 (ashift x c) where C puts the bit in the sign bit. Remove any
4493 AND with STORE_FLAG_VALUE when we are done, since we are only
4494 going to test the sign bit. */
4495 if (new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4496 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4497 && ((STORE_FLAG_VALUE & GET_MODE_MASK (mode))
4498 == (unsigned HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE(mode)-1))
4499 && op1 == const0_rtx
4500 && mode == GET_MODE (op0)
4501 && (i = exact_log2 (nonzero_bits (op0, mode))) >= 0)
4503 x = simplify_shift_const (NULL_RTX, ASHIFT, mode,
4504 expand_compound_operation (op0),
4505 GET_MODE_BITSIZE (mode) - 1 - i);
4506 if (GET_CODE (x) == AND && XEXP (x, 1) == const_true_rtx)
4512 /* If the code changed, return a whole new comparison. */
4513 if (new_code != code)
4514 return gen_rtx_fmt_ee (new_code, mode, op0, op1);
4516 /* Otherwise, keep this operation, but maybe change its operands.
4517 This also converts (ne (compare FOO BAR) 0) to (ne FOO BAR). */
4518 SUBST (XEXP (x, 0), op0);
4519 SUBST (XEXP (x, 1), op1);
4524 return simplify_if_then_else (x);
4530 /* If we are processing SET_DEST, we are done. */
4534 return expand_compound_operation (x);
4537 return simplify_set (x);
4542 return simplify_logical (x, last);
4545 /* (abs (neg <foo>)) -> (abs <foo>) */
4546 if (GET_CODE (XEXP (x, 0)) == NEG)
4547 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4549 /* If the mode of the operand is VOIDmode (i.e. if it is ASM_OPERANDS),
4551 if (GET_MODE (XEXP (x, 0)) == VOIDmode)
4554 /* If operand is something known to be positive, ignore the ABS. */
4555 if (GET_CODE (XEXP (x, 0)) == FFS || GET_CODE (XEXP (x, 0)) == ABS
4556 || ((GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
4557 <= HOST_BITS_PER_WIDE_INT)
4558 && ((nonzero_bits (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
4559 & ((HOST_WIDE_INT) 1
4560 << (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - 1)))
4564 /* If operand is known to be only -1 or 0, convert ABS to NEG. */
4565 if (num_sign_bit_copies (XEXP (x, 0), mode) == GET_MODE_BITSIZE (mode))
4566 return gen_rtx_NEG (mode, XEXP (x, 0));
4571 /* (ffs (*_extend <X>)) = (ffs <X>) */
4572 if (GET_CODE (XEXP (x, 0)) == SIGN_EXTEND
4573 || GET_CODE (XEXP (x, 0)) == ZERO_EXTEND)
4574 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4578 /* (float (sign_extend <X>)) = (float <X>). */
4579 if (GET_CODE (XEXP (x, 0)) == SIGN_EXTEND)
4580 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4588 /* If this is a shift by a constant amount, simplify it. */
4589 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
4590 return simplify_shift_const (x, code, mode, XEXP (x, 0),
4591 INTVAL (XEXP (x, 1)));
4593 #ifdef SHIFT_COUNT_TRUNCATED
4594 else if (SHIFT_COUNT_TRUNCATED && GET_CODE (XEXP (x, 1)) != REG)
4596 force_to_mode (XEXP (x, 1), GET_MODE (XEXP (x, 1)),
4598 << exact_log2 (GET_MODE_BITSIZE (GET_MODE (x))))
4607 rtx op0 = XEXP (x, 0);
4608 rtx op1 = XEXP (x, 1);
4611 if (GET_CODE (op1) != PARALLEL)
4613 len = XVECLEN (op1, 0);
4615 && GET_CODE (XVECEXP (op1, 0, 0)) == CONST_INT
4616 && GET_CODE (op0) == VEC_CONCAT)
4618 int offset = INTVAL (XVECEXP (op1, 0, 0)) * GET_MODE_SIZE (GET_MODE (x));
4620 /* Try to find the element in the VEC_CONCAT. */
4623 if (GET_MODE (op0) == GET_MODE (x))
4625 if (GET_CODE (op0) == VEC_CONCAT)
4627 HOST_WIDE_INT op0_size = GET_MODE_SIZE (GET_MODE (XEXP (op0, 0)));
4628 if (op0_size < offset)
4629 op0 = XEXP (op0, 0);
4633 op0 = XEXP (op0, 1);
4651 /* Simplify X, an IF_THEN_ELSE expression. Return the new expression. */
4654 simplify_if_then_else (x)
4657 enum machine_mode mode = GET_MODE (x);
4658 rtx cond = XEXP (x, 0);
4659 rtx true_rtx = XEXP (x, 1);
4660 rtx false_rtx = XEXP (x, 2);
4661 enum rtx_code true_code = GET_CODE (cond);
4662 int comparison_p = GET_RTX_CLASS (true_code) == '<';
4665 enum rtx_code false_code;
4668 /* Simplify storing of the truth value. */
4669 if (comparison_p && true_rtx == const_true_rtx && false_rtx == const0_rtx)
4670 return gen_binary (true_code, mode, XEXP (cond, 0), XEXP (cond, 1));
4672 /* Also when the truth value has to be reversed. */
4674 && true_rtx == const0_rtx && false_rtx == const_true_rtx
4675 && (reversed = reversed_comparison (cond, mode, XEXP (cond, 0),
4679 /* Sometimes we can simplify the arm of an IF_THEN_ELSE if a register used
4680 in it is being compared against certain values. Get the true and false
4681 comparisons and see if that says anything about the value of each arm. */
4684 && ((false_code = combine_reversed_comparison_code (cond))
4686 && GET_CODE (XEXP (cond, 0)) == REG)
4689 rtx from = XEXP (cond, 0);
4690 rtx true_val = XEXP (cond, 1);
4691 rtx false_val = true_val;
4694 /* If FALSE_CODE is EQ, swap the codes and arms. */
4696 if (false_code == EQ)
4698 swapped = 1, true_code = EQ, false_code = NE;
4699 temp = true_rtx, true_rtx = false_rtx, false_rtx = temp;
4702 /* If we are comparing against zero and the expression being tested has
4703 only a single bit that might be nonzero, that is its value when it is
4704 not equal to zero. Similarly if it is known to be -1 or 0. */
4706 if (true_code == EQ && true_val == const0_rtx
4707 && exact_log2 (nzb = nonzero_bits (from, GET_MODE (from))) >= 0)
4708 false_code = EQ, false_val = GEN_INT (nzb);
4709 else if (true_code == EQ && true_val == const0_rtx
4710 && (num_sign_bit_copies (from, GET_MODE (from))
4711 == GET_MODE_BITSIZE (GET_MODE (from))))
4712 false_code = EQ, false_val = constm1_rtx;
4714 /* Now simplify an arm if we know the value of the register in the
4715 branch and it is used in the arm. Be careful due to the potential
4716 of locally-shared RTL. */
4718 if (reg_mentioned_p (from, true_rtx))
4719 true_rtx = subst (known_cond (copy_rtx (true_rtx), true_code,
4721 pc_rtx, pc_rtx, 0, 0);
4722 if (reg_mentioned_p (from, false_rtx))
4723 false_rtx = subst (known_cond (copy_rtx (false_rtx), false_code,
4725 pc_rtx, pc_rtx, 0, 0);
4727 SUBST (XEXP (x, 1), swapped ? false_rtx : true_rtx);
4728 SUBST (XEXP (x, 2), swapped ? true_rtx : false_rtx);
4730 true_rtx = XEXP (x, 1);
4731 false_rtx = XEXP (x, 2);
4732 true_code = GET_CODE (cond);
4735 /* If we have (if_then_else FOO (pc) (label_ref BAR)) and FOO can be
4736 reversed, do so to avoid needing two sets of patterns for
4737 subtract-and-branch insns. Similarly if we have a constant in the true
4738 arm, the false arm is the same as the first operand of the comparison, or
4739 the false arm is more complicated than the true arm. */
4742 && combine_reversed_comparison_code (cond) != UNKNOWN
4743 && (true_rtx == pc_rtx
4744 || (CONSTANT_P (true_rtx)
4745 && GET_CODE (false_rtx) != CONST_INT && false_rtx != pc_rtx)
4746 || true_rtx == const0_rtx
4747 || (GET_RTX_CLASS (GET_CODE (true_rtx)) == 'o'
4748 && GET_RTX_CLASS (GET_CODE (false_rtx)) != 'o')
4749 || (GET_CODE (true_rtx) == SUBREG
4750 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (true_rtx))) == 'o'
4751 && GET_RTX_CLASS (GET_CODE (false_rtx)) != 'o')
4752 || reg_mentioned_p (true_rtx, false_rtx)
4753 || rtx_equal_p (false_rtx, XEXP (cond, 0))))
4755 true_code = reversed_comparison_code (cond, NULL);
4757 reversed_comparison (cond, GET_MODE (cond), XEXP (cond, 0),
4760 SUBST (XEXP (x, 1), false_rtx);
4761 SUBST (XEXP (x, 2), true_rtx);
4763 temp = true_rtx, true_rtx = false_rtx, false_rtx = temp;
4766 /* It is possible that the conditional has been simplified out. */
4767 true_code = GET_CODE (cond);
4768 comparison_p = GET_RTX_CLASS (true_code) == '<';
4771 /* If the two arms are identical, we don't need the comparison. */
4773 if (rtx_equal_p (true_rtx, false_rtx) && ! side_effects_p (cond))
4776 /* Convert a == b ? b : a to "a". */
4777 if (true_code == EQ && ! side_effects_p (cond)
4778 && !HONOR_NANS (mode)
4779 && rtx_equal_p (XEXP (cond, 0), false_rtx)
4780 && rtx_equal_p (XEXP (cond, 1), true_rtx))
4782 else if (true_code == NE && ! side_effects_p (cond)
4783 && !HONOR_NANS (mode)
4784 && rtx_equal_p (XEXP (cond, 0), true_rtx)
4785 && rtx_equal_p (XEXP (cond, 1), false_rtx))
4788 /* Look for cases where we have (abs x) or (neg (abs X)). */
4790 if (GET_MODE_CLASS (mode) == MODE_INT
4791 && GET_CODE (false_rtx) == NEG
4792 && rtx_equal_p (true_rtx, XEXP (false_rtx, 0))
4794 && rtx_equal_p (true_rtx, XEXP (cond, 0))
4795 && ! side_effects_p (true_rtx))
4800 return simplify_gen_unary (ABS, mode, true_rtx, mode);
4804 simplify_gen_unary (NEG, mode,
4805 simplify_gen_unary (ABS, mode, true_rtx, mode),
4811 /* Look for MIN or MAX. */
4813 if ((! FLOAT_MODE_P (mode) || flag_unsafe_math_optimizations)
4815 && rtx_equal_p (XEXP (cond, 0), true_rtx)
4816 && rtx_equal_p (XEXP (cond, 1), false_rtx)
4817 && ! side_effects_p (cond))
4822 return gen_binary (SMAX, mode, true_rtx, false_rtx);
4825 return gen_binary (SMIN, mode, true_rtx, false_rtx);
4828 return gen_binary (UMAX, mode, true_rtx, false_rtx);
4831 return gen_binary (UMIN, mode, true_rtx, false_rtx);
4836 /* If we have (if_then_else COND (OP Z C1) Z) and OP is an identity when its
4837 second operand is zero, this can be done as (OP Z (mult COND C2)) where
4838 C2 = C1 * STORE_FLAG_VALUE. Similarly if OP has an outer ZERO_EXTEND or
4839 SIGN_EXTEND as long as Z is already extended (so we don't destroy it).
4840 We can do this kind of thing in some cases when STORE_FLAG_VALUE is
4841 neither 1 or -1, but it isn't worth checking for. */
4843 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
4844 && comparison_p && mode != VOIDmode && ! side_effects_p (x))
4846 rtx t = make_compound_operation (true_rtx, SET);
4847 rtx f = make_compound_operation (false_rtx, SET);
4848 rtx cond_op0 = XEXP (cond, 0);
4849 rtx cond_op1 = XEXP (cond, 1);
4850 enum rtx_code op = NIL, extend_op = NIL;
4851 enum machine_mode m = mode;
4852 rtx z = 0, c1 = NULL_RTX;
4854 if ((GET_CODE (t) == PLUS || GET_CODE (t) == MINUS
4855 || GET_CODE (t) == IOR || GET_CODE (t) == XOR
4856 || GET_CODE (t) == ASHIFT
4857 || GET_CODE (t) == LSHIFTRT || GET_CODE (t) == ASHIFTRT)
4858 && rtx_equal_p (XEXP (t, 0), f))
4859 c1 = XEXP (t, 1), op = GET_CODE (t), z = f;
4861 /* If an identity-zero op is commutative, check whether there
4862 would be a match if we swapped the operands. */
4863 else if ((GET_CODE (t) == PLUS || GET_CODE (t) == IOR
4864 || GET_CODE (t) == XOR)
4865 && rtx_equal_p (XEXP (t, 1), f))
4866 c1 = XEXP (t, 0), op = GET_CODE (t), z = f;
4867 else if (GET_CODE (t) == SIGN_EXTEND
4868 && (GET_CODE (XEXP (t, 0)) == PLUS
4869 || GET_CODE (XEXP (t, 0)) == MINUS
4870 || GET_CODE (XEXP (t, 0)) == IOR
4871 || GET_CODE (XEXP (t, 0)) == XOR
4872 || GET_CODE (XEXP (t, 0)) == ASHIFT
4873 || GET_CODE (XEXP (t, 0)) == LSHIFTRT
4874 || GET_CODE (XEXP (t, 0)) == ASHIFTRT)
4875 && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG
4876 && subreg_lowpart_p (XEXP (XEXP (t, 0), 0))
4877 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f)
4878 && (num_sign_bit_copies (f, GET_MODE (f))
4880 (GET_MODE_BITSIZE (mode)
4881 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t, 0), 0))))))
4883 c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0));
4884 extend_op = SIGN_EXTEND;
4885 m = GET_MODE (XEXP (t, 0));
4887 else if (GET_CODE (t) == SIGN_EXTEND
4888 && (GET_CODE (XEXP (t, 0)) == PLUS
4889 || GET_CODE (XEXP (t, 0)) == IOR
4890 || GET_CODE (XEXP (t, 0)) == XOR)
4891 && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG
4892 && subreg_lowpart_p (XEXP (XEXP (t, 0), 1))
4893 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f)
4894 && (num_sign_bit_copies (f, GET_MODE (f))
4896 (GET_MODE_BITSIZE (mode)
4897 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t, 0), 1))))))
4899 c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0));
4900 extend_op = SIGN_EXTEND;
4901 m = GET_MODE (XEXP (t, 0));
4903 else if (GET_CODE (t) == ZERO_EXTEND
4904 && (GET_CODE (XEXP (t, 0)) == PLUS
4905 || GET_CODE (XEXP (t, 0)) == MINUS
4906 || GET_CODE (XEXP (t, 0)) == IOR
4907 || GET_CODE (XEXP (t, 0)) == XOR
4908 || GET_CODE (XEXP (t, 0)) == ASHIFT
4909 || GET_CODE (XEXP (t, 0)) == LSHIFTRT
4910 || GET_CODE (XEXP (t, 0)) == ASHIFTRT)
4911 && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG
4912 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4913 && subreg_lowpart_p (XEXP (XEXP (t, 0), 0))
4914 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f)
4915 && ((nonzero_bits (f, GET_MODE (f))
4916 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t, 0), 0))))
4919 c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0));
4920 extend_op = ZERO_EXTEND;
4921 m = GET_MODE (XEXP (t, 0));
4923 else if (GET_CODE (t) == ZERO_EXTEND
4924 && (GET_CODE (XEXP (t, 0)) == PLUS
4925 || GET_CODE (XEXP (t, 0)) == IOR
4926 || GET_CODE (XEXP (t, 0)) == XOR)
4927 && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG
4928 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4929 && subreg_lowpart_p (XEXP (XEXP (t, 0), 1))
4930 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f)
4931 && ((nonzero_bits (f, GET_MODE (f))
4932 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t, 0), 1))))
4935 c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0));
4936 extend_op = ZERO_EXTEND;
4937 m = GET_MODE (XEXP (t, 0));
4942 temp = subst (gen_binary (true_code, m, cond_op0, cond_op1),
4943 pc_rtx, pc_rtx, 0, 0);
4944 temp = gen_binary (MULT, m, temp,
4945 gen_binary (MULT, m, c1, const_true_rtx));
4946 temp = subst (temp, pc_rtx, pc_rtx, 0, 0);
4947 temp = gen_binary (op, m, gen_lowpart_for_combine (m, z), temp);
4949 if (extend_op != NIL)
4950 temp = simplify_gen_unary (extend_op, mode, temp, m);
4956 /* If we have (if_then_else (ne A 0) C1 0) and either A is known to be 0 or
4957 1 and C1 is a single bit or A is known to be 0 or -1 and C1 is the
4958 negation of a single bit, we can convert this operation to a shift. We
4959 can actually do this more generally, but it doesn't seem worth it. */
4961 if (true_code == NE && XEXP (cond, 1) == const0_rtx
4962 && false_rtx == const0_rtx && GET_CODE (true_rtx) == CONST_INT
4963 && ((1 == nonzero_bits (XEXP (cond, 0), mode)
4964 && (i = exact_log2 (INTVAL (true_rtx))) >= 0)
4965 || ((num_sign_bit_copies (XEXP (cond, 0), mode)
4966 == GET_MODE_BITSIZE (mode))
4967 && (i = exact_log2 (-INTVAL (true_rtx))) >= 0)))
4969 simplify_shift_const (NULL_RTX, ASHIFT, mode,
4970 gen_lowpart_for_combine (mode, XEXP (cond, 0)), i);
4975 /* Simplify X, a SET expression. Return the new expression. */
4981 rtx src = SET_SRC (x);
4982 rtx dest = SET_DEST (x);
4983 enum machine_mode mode
4984 = GET_MODE (src) != VOIDmode ? GET_MODE (src) : GET_MODE (dest);
4988 /* (set (pc) (return)) gets written as (return). */
4989 if (GET_CODE (dest) == PC && GET_CODE (src) == RETURN)
4992 /* Now that we know for sure which bits of SRC we are using, see if we can
4993 simplify the expression for the object knowing that we only need the
4996 if (GET_MODE_CLASS (mode) == MODE_INT)
4998 src = force_to_mode (src, mode, ~(HOST_WIDE_INT) 0, NULL_RTX, 0);
4999 SUBST (SET_SRC (x), src);
5002 /* If we are setting CC0 or if the source is a COMPARE, look for the use of
5003 the comparison result and try to simplify it unless we already have used
5004 undobuf.other_insn. */
5005 if ((GET_CODE (src) == COMPARE
5010 && (cc_use = find_single_use (dest, subst_insn, &other_insn)) != 0
5011 && (undobuf.other_insn == 0 || other_insn == undobuf.other_insn)
5012 && GET_RTX_CLASS (GET_CODE (*cc_use)) == '<'
5013 && rtx_equal_p (XEXP (*cc_use, 0), dest))
5015 enum rtx_code old_code = GET_CODE (*cc_use);
5016 enum rtx_code new_code;
5018 int other_changed = 0;
5019 enum machine_mode compare_mode = GET_MODE (dest);
5021 if (GET_CODE (src) == COMPARE)
5022 op0 = XEXP (src, 0), op1 = XEXP (src, 1);
5024 op0 = src, op1 = const0_rtx;
5026 /* Simplify our comparison, if possible. */
5027 new_code = simplify_comparison (old_code, &op0, &op1);
5029 #ifdef EXTRA_CC_MODES
5030 /* If this machine has CC modes other than CCmode, check to see if we
5031 need to use a different CC mode here. */
5032 compare_mode = SELECT_CC_MODE (new_code, op0, op1);
5033 #endif /* EXTRA_CC_MODES */
5035 #if !defined (HAVE_cc0) && defined (EXTRA_CC_MODES)
5036 /* If the mode changed, we have to change SET_DEST, the mode in the
5037 compare, and the mode in the place SET_DEST is used. If SET_DEST is
5038 a hard register, just build new versions with the proper mode. If it
5039 is a pseudo, we lose unless it is only time we set the pseudo, in
5040 which case we can safely change its mode. */
5041 if (compare_mode != GET_MODE (dest))
5043 unsigned int regno = REGNO (dest);
5044 rtx new_dest = gen_rtx_REG (compare_mode, regno);
5046 if (regno < FIRST_PSEUDO_REGISTER
5047 || (REG_N_SETS (regno) == 1 && ! REG_USERVAR_P (dest)))
5049 if (regno >= FIRST_PSEUDO_REGISTER)
5050 SUBST (regno_reg_rtx[regno], new_dest);
5052 SUBST (SET_DEST (x), new_dest);
5053 SUBST (XEXP (*cc_use, 0), new_dest);
5061 /* If the code changed, we have to build a new comparison in
5062 undobuf.other_insn. */
5063 if (new_code != old_code)
5065 unsigned HOST_WIDE_INT mask;
5067 SUBST (*cc_use, gen_rtx_fmt_ee (new_code, GET_MODE (*cc_use),
5070 /* If the only change we made was to change an EQ into an NE or
5071 vice versa, OP0 has only one bit that might be nonzero, and OP1
5072 is zero, check if changing the user of the condition code will
5073 produce a valid insn. If it won't, we can keep the original code
5074 in that insn by surrounding our operation with an XOR. */
5076 if (((old_code == NE && new_code == EQ)
5077 || (old_code == EQ && new_code == NE))
5078 && ! other_changed && op1 == const0_rtx
5079 && GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
5080 && exact_log2 (mask = nonzero_bits (op0, GET_MODE (op0))) >= 0)
5082 rtx pat = PATTERN (other_insn), note = 0;
5084 if ((recog_for_combine (&pat, other_insn, ¬e) < 0
5085 && ! check_asm_operands (pat)))
5087 PUT_CODE (*cc_use, old_code);
5090 op0 = gen_binary (XOR, GET_MODE (op0), op0, GEN_INT (mask));
5098 undobuf.other_insn = other_insn;
5101 /* If we are now comparing against zero, change our source if
5102 needed. If we do not use cc0, we always have a COMPARE. */
5103 if (op1 == const0_rtx && dest == cc0_rtx)
5105 SUBST (SET_SRC (x), op0);
5111 /* Otherwise, if we didn't previously have a COMPARE in the
5112 correct mode, we need one. */
5113 if (GET_CODE (src) != COMPARE || GET_MODE (src) != compare_mode)
5115 SUBST (SET_SRC (x), gen_rtx_COMPARE (compare_mode, op0, op1));
5120 /* Otherwise, update the COMPARE if needed. */
5121 SUBST (XEXP (src, 0), op0);
5122 SUBST (XEXP (src, 1), op1);
5127 /* Get SET_SRC in a form where we have placed back any
5128 compound expressions. Then do the checks below. */
5129 src = make_compound_operation (src, SET);
5130 SUBST (SET_SRC (x), src);
5133 /* If we have (set x (subreg:m1 (op:m2 ...) 0)) with OP being some operation,
5134 and X being a REG or (subreg (reg)), we may be able to convert this to
5135 (set (subreg:m2 x) (op)).
5137 We can always do this if M1 is narrower than M2 because that means that
5138 we only care about the low bits of the result.
5140 However, on machines without WORD_REGISTER_OPERATIONS defined, we cannot
5141 perform a narrower operation than requested since the high-order bits will
5142 be undefined. On machine where it is defined, this transformation is safe
5143 as long as M1 and M2 have the same number of words. */
5145 if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src)
5146 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (src))) != 'o'
5147 && (((GET_MODE_SIZE (GET_MODE (src)) + (UNITS_PER_WORD - 1))
5149 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (src)))
5150 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD))
5151 #ifndef WORD_REGISTER_OPERATIONS
5152 && (GET_MODE_SIZE (GET_MODE (src))
5153 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (src))))
5155 #ifdef CLASS_CANNOT_CHANGE_MODE
5156 && ! (GET_CODE (dest) == REG && REGNO (dest) < FIRST_PSEUDO_REGISTER
5157 && (TEST_HARD_REG_BIT
5158 (reg_class_contents[(int) CLASS_CANNOT_CHANGE_MODE],
5160 && CLASS_CANNOT_CHANGE_MODE_P (GET_MODE (src),
5161 GET_MODE (SUBREG_REG (src))))
5163 && (GET_CODE (dest) == REG
5164 || (GET_CODE (dest) == SUBREG
5165 && GET_CODE (SUBREG_REG (dest)) == REG)))
5167 SUBST (SET_DEST (x),
5168 gen_lowpart_for_combine (GET_MODE (SUBREG_REG (src)),
5170 SUBST (SET_SRC (x), SUBREG_REG (src));
5172 src = SET_SRC (x), dest = SET_DEST (x);
5176 /* If we have (set (cc0) (subreg ...)), we try to remove the subreg
5179 && GET_CODE (src) == SUBREG
5180 && subreg_lowpart_p (src)
5181 && (GET_MODE_BITSIZE (GET_MODE (src))
5182 < GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (src)))))
5184 rtx inner = SUBREG_REG (src);
5185 enum machine_mode inner_mode = GET_MODE (inner);
5187 /* Here we make sure that we don't have a sign bit on. */
5188 if (GET_MODE_BITSIZE (inner_mode) <= HOST_BITS_PER_WIDE_INT
5189 && (nonzero_bits (inner, inner_mode)
5190 < ((unsigned HOST_WIDE_INT) 1
5191 << (GET_MODE_BITSIZE (inner_mode) - 1))))
5193 SUBST (SET_SRC (x), inner);
5199 #ifdef LOAD_EXTEND_OP
5200 /* If we have (set FOO (subreg:M (mem:N BAR) 0)) with M wider than N, this
5201 would require a paradoxical subreg. Replace the subreg with a
5202 zero_extend to avoid the reload that would otherwise be required. */
5204 if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src)
5205 && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src))) != NIL
5206 && SUBREG_BYTE (src) == 0
5207 && (GET_MODE_SIZE (GET_MODE (src))
5208 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (src))))
5209 && GET_CODE (SUBREG_REG (src)) == MEM)
5212 gen_rtx (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src))),
5213 GET_MODE (src), SUBREG_REG (src)));
5219 /* If we don't have a conditional move, SET_SRC is an IF_THEN_ELSE, and we
5220 are comparing an item known to be 0 or -1 against 0, use a logical
5221 operation instead. Check for one of the arms being an IOR of the other
5222 arm with some value. We compute three terms to be IOR'ed together. In
5223 practice, at most two will be nonzero. Then we do the IOR's. */
5225 if (GET_CODE (dest) != PC
5226 && GET_CODE (src) == IF_THEN_ELSE
5227 && GET_MODE_CLASS (GET_MODE (src)) == MODE_INT
5228 && (GET_CODE (XEXP (src, 0)) == EQ || GET_CODE (XEXP (src, 0)) == NE)
5229 && XEXP (XEXP (src, 0), 1) == const0_rtx
5230 && GET_MODE (src) == GET_MODE (XEXP (XEXP (src, 0), 0))
5231 #ifdef HAVE_conditional_move
5232 && ! can_conditionally_move_p (GET_MODE (src))
5234 && (num_sign_bit_copies (XEXP (XEXP (src, 0), 0),
5235 GET_MODE (XEXP (XEXP (src, 0), 0)))
5236 == GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (src, 0), 0))))
5237 && ! side_effects_p (src))
5239 rtx true_rtx = (GET_CODE (XEXP (src, 0)) == NE
5240 ? XEXP (src, 1) : XEXP (src, 2));
5241 rtx false_rtx = (GET_CODE (XEXP (src, 0)) == NE
5242 ? XEXP (src, 2) : XEXP (src, 1));
5243 rtx term1 = const0_rtx, term2, term3;
5245 if (GET_CODE (true_rtx) == IOR
5246 && rtx_equal_p (XEXP (true_rtx, 0), false_rtx))
5247 term1 = false_rtx, true_rtx = XEXP(true_rtx, 1), false_rtx = const0_rtx;
5248 else if (GET_CODE (true_rtx) == IOR
5249 && rtx_equal_p (XEXP (true_rtx, 1), false_rtx))
5250 term1 = false_rtx, true_rtx = XEXP(true_rtx, 0), false_rtx = const0_rtx;
5251 else if (GET_CODE (false_rtx) == IOR
5252 && rtx_equal_p (XEXP (false_rtx, 0), true_rtx))
5253 term1 = true_rtx, false_rtx = XEXP(false_rtx, 1), true_rtx = const0_rtx;
5254 else if (GET_CODE (false_rtx) == IOR
5255 && rtx_equal_p (XEXP (false_rtx, 1), true_rtx))
5256 term1 = true_rtx, false_rtx = XEXP(false_rtx, 0), true_rtx = const0_rtx;
5258 term2 = gen_binary (AND, GET_MODE (src),
5259 XEXP (XEXP (src, 0), 0), true_rtx);
5260 term3 = gen_binary (AND, GET_MODE (src),
5261 simplify_gen_unary (NOT, GET_MODE (src),
5262 XEXP (XEXP (src, 0), 0),
5267 gen_binary (IOR, GET_MODE (src),
5268 gen_binary (IOR, GET_MODE (src), term1, term2),
5274 /* If either SRC or DEST is a CLOBBER of (const_int 0), make this
5275 whole thing fail. */
5276 if (GET_CODE (src) == CLOBBER && XEXP (src, 0) == const0_rtx)
5278 else if (GET_CODE (dest) == CLOBBER && XEXP (dest, 0) == const0_rtx)
5281 /* Convert this into a field assignment operation, if possible. */
5282 return make_field_assignment (x);
5285 /* Simplify, X, and AND, IOR, or XOR operation, and return the simplified
5286 result. LAST is nonzero if this is the last retry. */
5289 simplify_logical (x, last)
5293 enum machine_mode mode = GET_MODE (x);
5294 rtx op0 = XEXP (x, 0);
5295 rtx op1 = XEXP (x, 1);
5298 switch (GET_CODE (x))
5301 /* Convert (A ^ B) & A to A & (~B) since the latter is often a single
5302 insn (and may simplify more). */
5303 if (GET_CODE (op0) == XOR
5304 && rtx_equal_p (XEXP (op0, 0), op1)
5305 && ! side_effects_p (op1))
5306 x = gen_binary (AND, mode,
5307 simplify_gen_unary (NOT, mode, XEXP (op0, 1), mode),
5310 if (GET_CODE (op0) == XOR
5311 && rtx_equal_p (XEXP (op0, 1), op1)
5312 && ! side_effects_p (op1))
5313 x = gen_binary (AND, mode,
5314 simplify_gen_unary (NOT, mode, XEXP (op0, 0), mode),
5317 /* Similarly for (~(A ^ B)) & A. */
5318 if (GET_CODE (op0) == NOT
5319 && GET_CODE (XEXP (op0, 0)) == XOR
5320 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), op1)
5321 && ! side_effects_p (op1))
5322 x = gen_binary (AND, mode, XEXP (XEXP (op0, 0), 1), op1);
5324 if (GET_CODE (op0) == NOT
5325 && GET_CODE (XEXP (op0, 0)) == XOR
5326 && rtx_equal_p (XEXP (XEXP (op0, 0), 1), op1)
5327 && ! side_effects_p (op1))
5328 x = gen_binary (AND, mode, XEXP (XEXP (op0, 0), 0), op1);
5330 /* We can call simplify_and_const_int only if we don't lose
5331 any (sign) bits when converting INTVAL (op1) to
5332 "unsigned HOST_WIDE_INT". */
5333 if (GET_CODE (op1) == CONST_INT
5334 && (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5335 || INTVAL (op1) > 0))
5337 x = simplify_and_const_int (x, mode, op0, INTVAL (op1));
5339 /* If we have (ior (and (X C1) C2)) and the next restart would be
5340 the last, simplify this by making C1 as small as possible
5343 && GET_CODE (x) == IOR && GET_CODE (op0) == AND
5344 && GET_CODE (XEXP (op0, 1)) == CONST_INT
5345 && GET_CODE (op1) == CONST_INT)
5346 return gen_binary (IOR, mode,
5347 gen_binary (AND, mode, XEXP (op0, 0),
5348 GEN_INT (INTVAL (XEXP (op0, 1))
5349 & ~INTVAL (op1))), op1);
5351 if (GET_CODE (x) != AND)
5354 if (GET_RTX_CLASS (GET_CODE (x)) == 'c'
5355 || GET_RTX_CLASS (GET_CODE (x)) == '2')
5356 op0 = XEXP (x, 0), op1 = XEXP (x, 1);
5359 /* Convert (A | B) & A to A. */
5360 if (GET_CODE (op0) == IOR
5361 && (rtx_equal_p (XEXP (op0, 0), op1)
5362 || rtx_equal_p (XEXP (op0, 1), op1))
5363 && ! side_effects_p (XEXP (op0, 0))
5364 && ! side_effects_p (XEXP (op0, 1)))
5367 /* In the following group of tests (and those in case IOR below),
5368 we start with some combination of logical operations and apply
5369 the distributive law followed by the inverse distributive law.
5370 Most of the time, this results in no change. However, if some of
5371 the operands are the same or inverses of each other, simplifications
5374 For example, (and (ior A B) (not B)) can occur as the result of
5375 expanding a bit field assignment. When we apply the distributive
5376 law to this, we get (ior (and (A (not B))) (and (B (not B)))),
5377 which then simplifies to (and (A (not B))).
5379 If we have (and (ior A B) C), apply the distributive law and then
5380 the inverse distributive law to see if things simplify. */
5382 if (GET_CODE (op0) == IOR || GET_CODE (op0) == XOR)
5384 x = apply_distributive_law
5385 (gen_binary (GET_CODE (op0), mode,
5386 gen_binary (AND, mode, XEXP (op0, 0), op1),
5387 gen_binary (AND, mode, XEXP (op0, 1),
5389 if (GET_CODE (x) != AND)
5393 if (GET_CODE (op1) == IOR || GET_CODE (op1) == XOR)
5394 return apply_distributive_law
5395 (gen_binary (GET_CODE (op1), mode,
5396 gen_binary (AND, mode, XEXP (op1, 0), op0),
5397 gen_binary (AND, mode, XEXP (op1, 1),
5400 /* Similarly, taking advantage of the fact that
5401 (and (not A) (xor B C)) == (xor (ior A B) (ior A C)) */
5403 if (GET_CODE (op0) == NOT && GET_CODE (op1) == XOR)
5404 return apply_distributive_law
5405 (gen_binary (XOR, mode,
5406 gen_binary (IOR, mode, XEXP (op0, 0), XEXP (op1, 0)),
5407 gen_binary (IOR, mode, copy_rtx (XEXP (op0, 0)),
5410 else if (GET_CODE (op1) == NOT && GET_CODE (op0) == XOR)
5411 return apply_distributive_law
5412 (gen_binary (XOR, mode,
5413 gen_binary (IOR, mode, XEXP (op1, 0), XEXP (op0, 0)),
5414 gen_binary (IOR, mode, copy_rtx (XEXP (op1, 0)), XEXP (op0, 1))));
5418 /* (ior A C) is C if all bits of A that might be nonzero are on in C. */
5419 if (GET_CODE (op1) == CONST_INT
5420 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5421 && (nonzero_bits (op0, mode) & ~INTVAL (op1)) == 0)
5424 /* Convert (A & B) | A to A. */
5425 if (GET_CODE (op0) == AND
5426 && (rtx_equal_p (XEXP (op0, 0), op1)
5427 || rtx_equal_p (XEXP (op0, 1), op1))
5428 && ! side_effects_p (XEXP (op0, 0))
5429 && ! side_effects_p (XEXP (op0, 1)))
5432 /* If we have (ior (and A B) C), apply the distributive law and then
5433 the inverse distributive law to see if things simplify. */
5435 if (GET_CODE (op0) == AND)
5437 x = apply_distributive_law
5438 (gen_binary (AND, mode,
5439 gen_binary (IOR, mode, XEXP (op0, 0), op1),
5440 gen_binary (IOR, mode, XEXP (op0, 1),
5443 if (GET_CODE (x) != IOR)
5447 if (GET_CODE (op1) == AND)
5449 x = apply_distributive_law
5450 (gen_binary (AND, mode,
5451 gen_binary (IOR, mode, XEXP (op1, 0), op0),
5452 gen_binary (IOR, mode, XEXP (op1, 1),
5455 if (GET_CODE (x) != IOR)
5459 /* Convert (ior (ashift A CX) (lshiftrt A CY)) where CX+CY equals the
5460 mode size to (rotate A CX). */
5462 if (((GET_CODE (op0) == ASHIFT && GET_CODE (op1) == LSHIFTRT)
5463 || (GET_CODE (op1) == ASHIFT && GET_CODE (op0) == LSHIFTRT))
5464 && rtx_equal_p (XEXP (op0, 0), XEXP (op1, 0))
5465 && GET_CODE (XEXP (op0, 1)) == CONST_INT
5466 && GET_CODE (XEXP (op1, 1)) == CONST_INT
5467 && (INTVAL (XEXP (op0, 1)) + INTVAL (XEXP (op1, 1))
5468 == GET_MODE_BITSIZE (mode)))
5469 return gen_rtx_ROTATE (mode, XEXP (op0, 0),
5470 (GET_CODE (op0) == ASHIFT
5471 ? XEXP (op0, 1) : XEXP (op1, 1)));
5473 /* If OP0 is (ashiftrt (plus ...) C), it might actually be
5474 a (sign_extend (plus ...)). If so, OP1 is a CONST_INT, and the PLUS
5475 does not affect any of the bits in OP1, it can really be done
5476 as a PLUS and we can associate. We do this by seeing if OP1
5477 can be safely shifted left C bits. */
5478 if (GET_CODE (op1) == CONST_INT && GET_CODE (op0) == ASHIFTRT
5479 && GET_CODE (XEXP (op0, 0)) == PLUS
5480 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
5481 && GET_CODE (XEXP (op0, 1)) == CONST_INT
5482 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT)
5484 int count = INTVAL (XEXP (op0, 1));
5485 HOST_WIDE_INT mask = INTVAL (op1) << count;
5487 if (mask >> count == INTVAL (op1)
5488 && (mask & nonzero_bits (XEXP (op0, 0), mode)) == 0)
5490 SUBST (XEXP (XEXP (op0, 0), 1),
5491 GEN_INT (INTVAL (XEXP (XEXP (op0, 0), 1)) | mask));
5498 /* If we are XORing two things that have no bits in common,
5499 convert them into an IOR. This helps to detect rotation encoded
5500 using those methods and possibly other simplifications. */
5502 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5503 && (nonzero_bits (op0, mode)
5504 & nonzero_bits (op1, mode)) == 0)
5505 return (gen_binary (IOR, mode, op0, op1));
5507 /* Convert (XOR (NOT x) (NOT y)) to (XOR x y).
5508 Also convert (XOR (NOT x) y) to (NOT (XOR x y)), similarly for
5511 int num_negated = 0;
5513 if (GET_CODE (op0) == NOT)
5514 num_negated++, op0 = XEXP (op0, 0);
5515 if (GET_CODE (op1) == NOT)
5516 num_negated++, op1 = XEXP (op1, 0);
5518 if (num_negated == 2)
5520 SUBST (XEXP (x, 0), op0);
5521 SUBST (XEXP (x, 1), op1);
5523 else if (num_negated == 1)
5525 simplify_gen_unary (NOT, mode, gen_binary (XOR, mode, op0, op1),
5529 /* Convert (xor (and A B) B) to (and (not A) B). The latter may
5530 correspond to a machine insn or result in further simplifications
5531 if B is a constant. */
5533 if (GET_CODE (op0) == AND
5534 && rtx_equal_p (XEXP (op0, 1), op1)
5535 && ! side_effects_p (op1))
5536 return gen_binary (AND, mode,
5537 simplify_gen_unary (NOT, mode, XEXP (op0, 0), mode),
5540 else if (GET_CODE (op0) == AND
5541 && rtx_equal_p (XEXP (op0, 0), op1)
5542 && ! side_effects_p (op1))
5543 return gen_binary (AND, mode,
5544 simplify_gen_unary (NOT, mode, XEXP (op0, 1), mode),
5547 /* (xor (comparison foo bar) (const_int 1)) can become the reversed
5548 comparison if STORE_FLAG_VALUE is 1. */
5549 if (STORE_FLAG_VALUE == 1
5550 && op1 == const1_rtx
5551 && GET_RTX_CLASS (GET_CODE (op0)) == '<'
5552 && (reversed = reversed_comparison (op0, mode, XEXP (op0, 0),
5556 /* (lshiftrt foo C) where C is the number of bits in FOO minus 1
5557 is (lt foo (const_int 0)), so we can perform the above
5558 simplification if STORE_FLAG_VALUE is 1. */
5560 if (STORE_FLAG_VALUE == 1
5561 && op1 == const1_rtx
5562 && GET_CODE (op0) == LSHIFTRT
5563 && GET_CODE (XEXP (op0, 1)) == CONST_INT
5564 && INTVAL (XEXP (op0, 1)) == GET_MODE_BITSIZE (mode) - 1)
5565 return gen_rtx_GE (mode, XEXP (op0, 0), const0_rtx);
5567 /* (xor (comparison foo bar) (const_int sign-bit))
5568 when STORE_FLAG_VALUE is the sign bit. */
5569 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5570 && ((STORE_FLAG_VALUE & GET_MODE_MASK (mode))
5571 == (unsigned HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (mode) - 1))
5572 && op1 == const_true_rtx
5573 && GET_RTX_CLASS (GET_CODE (op0)) == '<'
5574 && (reversed = reversed_comparison (op0, mode, XEXP (op0, 0),
5587 /* We consider ZERO_EXTRACT, SIGN_EXTRACT, and SIGN_EXTEND as "compound
5588 operations" because they can be replaced with two more basic operations.
5589 ZERO_EXTEND is also considered "compound" because it can be replaced with
5590 an AND operation, which is simpler, though only one operation.
5592 The function expand_compound_operation is called with an rtx expression
5593 and will convert it to the appropriate shifts and AND operations,
5594 simplifying at each stage.
5596 The function make_compound_operation is called to convert an expression
5597 consisting of shifts and ANDs into the equivalent compound expression.
5598 It is the inverse of this function, loosely speaking. */
5601 expand_compound_operation (x)
5604 unsigned HOST_WIDE_INT pos = 0, len;
5606 unsigned int modewidth;
5609 switch (GET_CODE (x))
5614 /* We can't necessarily use a const_int for a multiword mode;
5615 it depends on implicitly extending the value.
5616 Since we don't know the right way to extend it,
5617 we can't tell whether the implicit way is right.
5619 Even for a mode that is no wider than a const_int,
5620 we can't win, because we need to sign extend one of its bits through
5621 the rest of it, and we don't know which bit. */
5622 if (GET_CODE (XEXP (x, 0)) == CONST_INT)
5625 /* Return if (subreg:MODE FROM 0) is not a safe replacement for
5626 (zero_extend:MODE FROM) or (sign_extend:MODE FROM). It is for any MEM
5627 because (SUBREG (MEM...)) is guaranteed to cause the MEM to be
5628 reloaded. If not for that, MEM's would very rarely be safe.
5630 Reject MODEs bigger than a word, because we might not be able
5631 to reference a two-register group starting with an arbitrary register
5632 (and currently gen_lowpart might crash for a SUBREG). */
5634 if (GET_MODE_SIZE (GET_MODE (XEXP (x, 0))) > UNITS_PER_WORD)
5637 /* Reject MODEs that aren't scalar integers because turning vector
5638 or complex modes into shifts causes problems. */
5640 if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x, 0))))
5643 len = GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)));
5644 /* If the inner object has VOIDmode (the only way this can happen
5645 is if it is an ASM_OPERANDS), we can't do anything since we don't
5646 know how much masking to do. */
5655 /* If the operand is a CLOBBER, just return it. */
5656 if (GET_CODE (XEXP (x, 0)) == CLOBBER)
5659 if (GET_CODE (XEXP (x, 1)) != CONST_INT
5660 || GET_CODE (XEXP (x, 2)) != CONST_INT
5661 || GET_MODE (XEXP (x, 0)) == VOIDmode)
5664 /* Reject MODEs that aren't scalar integers because turning vector
5665 or complex modes into shifts causes problems. */
5667 if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x, 0))))
5670 len = INTVAL (XEXP (x, 1));
5671 pos = INTVAL (XEXP (x, 2));
5673 /* If this goes outside the object being extracted, replace the object
5674 with a (use (mem ...)) construct that only combine understands
5675 and is used only for this purpose. */
5676 if (len + pos > GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))))
5677 SUBST (XEXP (x, 0), gen_rtx_USE (GET_MODE (x), XEXP (x, 0)));
5679 if (BITS_BIG_ENDIAN)
5680 pos = GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - len - pos;
5687 /* Convert sign extension to zero extension, if we know that the high
5688 bit is not set, as this is easier to optimize. It will be converted
5689 back to cheaper alternative in make_extraction. */
5690 if (GET_CODE (x) == SIGN_EXTEND
5691 && (GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
5692 && ((nonzero_bits (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
5693 & ~(((unsigned HOST_WIDE_INT)
5694 GET_MODE_MASK (GET_MODE (XEXP (x, 0))))
5698 rtx temp = gen_rtx_ZERO_EXTEND (GET_MODE (x), XEXP (x, 0));
5699 return expand_compound_operation (temp);
5702 /* We can optimize some special cases of ZERO_EXTEND. */
5703 if (GET_CODE (x) == ZERO_EXTEND)
5705 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI if we
5706 know that the last value didn't have any inappropriate bits
5708 if (GET_CODE (XEXP (x, 0)) == TRUNCATE
5709 && GET_MODE (XEXP (XEXP (x, 0), 0)) == GET_MODE (x)
5710 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
5711 && (nonzero_bits (XEXP (XEXP (x, 0), 0), GET_MODE (x))
5712 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5713 return XEXP (XEXP (x, 0), 0);
5715 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
5716 if (GET_CODE (XEXP (x, 0)) == SUBREG
5717 && GET_MODE (SUBREG_REG (XEXP (x, 0))) == GET_MODE (x)
5718 && subreg_lowpart_p (XEXP (x, 0))
5719 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
5720 && (nonzero_bits (SUBREG_REG (XEXP (x, 0)), GET_MODE (x))
5721 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5722 return SUBREG_REG (XEXP (x, 0));
5724 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI when foo
5725 is a comparison and STORE_FLAG_VALUE permits. This is like
5726 the first case, but it works even when GET_MODE (x) is larger
5727 than HOST_WIDE_INT. */
5728 if (GET_CODE (XEXP (x, 0)) == TRUNCATE
5729 && GET_MODE (XEXP (XEXP (x, 0), 0)) == GET_MODE (x)
5730 && GET_RTX_CLASS (GET_CODE (XEXP (XEXP (x, 0), 0))) == '<'
5731 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
5732 <= HOST_BITS_PER_WIDE_INT)
5733 && ((HOST_WIDE_INT) STORE_FLAG_VALUE
5734 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5735 return XEXP (XEXP (x, 0), 0);
5737 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
5738 if (GET_CODE (XEXP (x, 0)) == SUBREG
5739 && GET_MODE (SUBREG_REG (XEXP (x, 0))) == GET_MODE (x)
5740 && subreg_lowpart_p (XEXP (x, 0))
5741 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 0)))) == '<'
5742 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
5743 <= HOST_BITS_PER_WIDE_INT)
5744 && ((HOST_WIDE_INT) STORE_FLAG_VALUE
5745 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5746 return SUBREG_REG (XEXP (x, 0));
5750 /* If we reach here, we want to return a pair of shifts. The inner
5751 shift is a left shift of BITSIZE - POS - LEN bits. The outer
5752 shift is a right shift of BITSIZE - LEN bits. It is arithmetic or
5753 logical depending on the value of UNSIGNEDP.
5755 If this was a ZERO_EXTEND or ZERO_EXTRACT, this pair of shifts will be
5756 converted into an AND of a shift.
5758 We must check for the case where the left shift would have a negative
5759 count. This can happen in a case like (x >> 31) & 255 on machines
5760 that can't shift by a constant. On those machines, we would first
5761 combine the shift with the AND to produce a variable-position
5762 extraction. Then the constant of 31 would be substituted in to produce
5763 a such a position. */
5765 modewidth = GET_MODE_BITSIZE (GET_MODE (x));
5766 if (modewidth + len >= pos)
5767 tem = simplify_shift_const (NULL_RTX, unsignedp ? LSHIFTRT : ASHIFTRT,
5769 simplify_shift_const (NULL_RTX, ASHIFT,
5772 modewidth - pos - len),
5775 else if (unsignedp && len < HOST_BITS_PER_WIDE_INT)
5776 tem = simplify_and_const_int (NULL_RTX, GET_MODE (x),
5777 simplify_shift_const (NULL_RTX, LSHIFTRT,
5780 ((HOST_WIDE_INT) 1 << len) - 1);
5782 /* Any other cases we can't handle. */
5785 /* If we couldn't do this for some reason, return the original
5787 if (GET_CODE (tem) == CLOBBER)
5793 /* X is a SET which contains an assignment of one object into
5794 a part of another (such as a bit-field assignment, STRICT_LOW_PART,
5795 or certain SUBREGS). If possible, convert it into a series of
5798 We half-heartedly support variable positions, but do not at all
5799 support variable lengths. */
5802 expand_field_assignment (x)
5806 rtx pos; /* Always counts from low bit. */
5809 enum machine_mode compute_mode;
5811 /* Loop until we find something we can't simplify. */
5814 if (GET_CODE (SET_DEST (x)) == STRICT_LOW_PART
5815 && GET_CODE (XEXP (SET_DEST (x), 0)) == SUBREG)
5817 inner = SUBREG_REG (XEXP (SET_DEST (x), 0));
5818 len = GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0)));
5819 pos = GEN_INT (subreg_lsb (XEXP (SET_DEST (x), 0)));
5821 else if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
5822 && GET_CODE (XEXP (SET_DEST (x), 1)) == CONST_INT)
5824 inner = XEXP (SET_DEST (x), 0);
5825 len = INTVAL (XEXP (SET_DEST (x), 1));
5826 pos = XEXP (SET_DEST (x), 2);
5828 /* If the position is constant and spans the width of INNER,
5829 surround INNER with a USE to indicate this. */
5830 if (GET_CODE (pos) == CONST_INT
5831 && INTVAL (pos) + len > GET_MODE_BITSIZE (GET_MODE (inner)))
5832 inner = gen_rtx_USE (GET_MODE (SET_DEST (x)), inner);
5834 if (BITS_BIG_ENDIAN)
5836 if (GET_CODE (pos) == CONST_INT)
5837 pos = GEN_INT (GET_MODE_BITSIZE (GET_MODE (inner)) - len
5839 else if (GET_CODE (pos) == MINUS
5840 && GET_CODE (XEXP (pos, 1)) == CONST_INT
5841 && (INTVAL (XEXP (pos, 1))
5842 == GET_MODE_BITSIZE (GET_MODE (inner)) - len))
5843 /* If position is ADJUST - X, new position is X. */
5844 pos = XEXP (pos, 0);
5846 pos = gen_binary (MINUS, GET_MODE (pos),
5847 GEN_INT (GET_MODE_BITSIZE (GET_MODE (inner))
5853 /* A SUBREG between two modes that occupy the same numbers of words
5854 can be done by moving the SUBREG to the source. */
5855 else if (GET_CODE (SET_DEST (x)) == SUBREG
5856 /* We need SUBREGs to compute nonzero_bits properly. */
5857 && nonzero_sign_valid
5858 && (((GET_MODE_SIZE (GET_MODE (SET_DEST (x)))
5859 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
5860 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x))))
5861 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)))
5863 x = gen_rtx_SET (VOIDmode, SUBREG_REG (SET_DEST (x)),
5864 gen_lowpart_for_combine
5865 (GET_MODE (SUBREG_REG (SET_DEST (x))),
5872 while (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
5873 inner = SUBREG_REG (inner);
5875 compute_mode = GET_MODE (inner);
5877 /* Don't attempt bitwise arithmetic on non scalar integer modes. */
5878 if (! SCALAR_INT_MODE_P (compute_mode))
5880 enum machine_mode imode;
5882 /* Don't do anything for vector or complex integral types. */
5883 if (! FLOAT_MODE_P (compute_mode))
5886 /* Try to find an integral mode to pun with. */
5887 imode = mode_for_size (GET_MODE_BITSIZE (compute_mode), MODE_INT, 0);
5888 if (imode == BLKmode)
5891 compute_mode = imode;
5892 inner = gen_lowpart_for_combine (imode, inner);
5895 /* Compute a mask of LEN bits, if we can do this on the host machine. */
5896 if (len < HOST_BITS_PER_WIDE_INT)
5897 mask = GEN_INT (((HOST_WIDE_INT) 1 << len) - 1);
5901 /* Now compute the equivalent expression. Make a copy of INNER
5902 for the SET_DEST in case it is a MEM into which we will substitute;
5903 we don't want shared RTL in that case. */
5905 (VOIDmode, copy_rtx (inner),
5906 gen_binary (IOR, compute_mode,
5907 gen_binary (AND, compute_mode,
5908 simplify_gen_unary (NOT, compute_mode,
5914 gen_binary (ASHIFT, compute_mode,
5915 gen_binary (AND, compute_mode,
5916 gen_lowpart_for_combine
5917 (compute_mode, SET_SRC (x)),
5925 /* Return an RTX for a reference to LEN bits of INNER. If POS_RTX is nonzero,
5926 it is an RTX that represents a variable starting position; otherwise,
5927 POS is the (constant) starting bit position (counted from the LSB).
5929 INNER may be a USE. This will occur when we started with a bitfield
5930 that went outside the boundary of the object in memory, which is
5931 allowed on most machines. To isolate this case, we produce a USE
5932 whose mode is wide enough and surround the MEM with it. The only
5933 code that understands the USE is this routine. If it is not removed,
5934 it will cause the resulting insn not to match.
5936 UNSIGNEDP is non-zero for an unsigned reference and zero for a
5939 IN_DEST is non-zero if this is a reference in the destination of a
5940 SET. This is used when a ZERO_ or SIGN_EXTRACT isn't needed. If non-zero,
5941 a STRICT_LOW_PART will be used, if zero, ZERO_EXTEND or SIGN_EXTEND will
5944 IN_COMPARE is non-zero if we are in a COMPARE. This means that a
5945 ZERO_EXTRACT should be built even for bits starting at bit 0.
5947 MODE is the desired mode of the result (if IN_DEST == 0).
5949 The result is an RTX for the extraction or NULL_RTX if the target
5953 make_extraction (mode, inner, pos, pos_rtx, len,
5954 unsignedp, in_dest, in_compare)
5955 enum machine_mode mode;
5959 unsigned HOST_WIDE_INT len;
5961 int in_dest, in_compare;
5963 /* This mode describes the size of the storage area
5964 to fetch the overall value from. Within that, we
5965 ignore the POS lowest bits, etc. */
5966 enum machine_mode is_mode = GET_MODE (inner);
5967 enum machine_mode inner_mode;
5968 enum machine_mode wanted_inner_mode = byte_mode;
5969 enum machine_mode wanted_inner_reg_mode = word_mode;
5970 enum machine_mode pos_mode = word_mode;
5971 enum machine_mode extraction_mode = word_mode;
5972 enum machine_mode tmode = mode_for_size (len, MODE_INT, 1);
5975 rtx orig_pos_rtx = pos_rtx;
5976 HOST_WIDE_INT orig_pos;
5978 /* Get some information about INNER and get the innermost object. */
5979 if (GET_CODE (inner) == USE)
5980 /* (use:SI (mem:QI foo)) stands for (mem:SI foo). */
5981 /* We don't need to adjust the position because we set up the USE
5982 to pretend that it was a full-word object. */
5983 spans_byte = 1, inner = XEXP (inner, 0);
5984 else if (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
5986 /* If going from (subreg:SI (mem:QI ...)) to (mem:QI ...),
5987 consider just the QI as the memory to extract from.
5988 The subreg adds or removes high bits; its mode is
5989 irrelevant to the meaning of this extraction,
5990 since POS and LEN count from the lsb. */
5991 if (GET_CODE (SUBREG_REG (inner)) == MEM)
5992 is_mode = GET_MODE (SUBREG_REG (inner));
5993 inner = SUBREG_REG (inner);
5995 else if (GET_CODE (inner) == ASHIFT
5996 && GET_CODE (XEXP (inner, 1)) == CONST_INT
5997 && pos_rtx == 0 && pos == 0
5998 && len > (unsigned HOST_WIDE_INT) INTVAL (XEXP (inner, 1)))
6000 /* We're extracting the least significant bits of an rtx
6001 (ashift X (const_int C)), where LEN > C. Extract the
6002 least significant (LEN - C) bits of X, giving an rtx
6003 whose mode is MODE, then shift it left C times. */
6004 new = make_extraction (mode, XEXP (inner, 0),
6005 0, 0, len - INTVAL (XEXP (inner, 1)),
6006 unsignedp, in_dest, in_compare);
6008 return gen_rtx_ASHIFT (mode, new, XEXP (inner, 1));
6011 inner_mode = GET_MODE (inner);
6013 if (pos_rtx && GET_CODE (pos_rtx) == CONST_INT)
6014 pos = INTVAL (pos_rtx), pos_rtx = 0;
6016 /* See if this can be done without an extraction. We never can if the
6017 width of the field is not the same as that of some integer mode. For
6018 registers, we can only avoid the extraction if the position is at the
6019 low-order bit and this is either not in the destination or we have the
6020 appropriate STRICT_LOW_PART operation available.
6022 For MEM, we can avoid an extract if the field starts on an appropriate
6023 boundary and we can change the mode of the memory reference. However,
6024 we cannot directly access the MEM if we have a USE and the underlying
6025 MEM is not TMODE. This combination means that MEM was being used in a
6026 context where bits outside its mode were being referenced; that is only
6027 valid in bit-field insns. */
6029 if (tmode != BLKmode
6030 && ! (spans_byte && inner_mode != tmode)
6031 && ((pos_rtx == 0 && (pos % BITS_PER_WORD) == 0
6032 && GET_CODE (inner) != MEM
6034 || (GET_CODE (inner) == REG
6035 && have_insn_for (STRICT_LOW_PART, tmode))))
6036 || (GET_CODE (inner) == MEM && pos_rtx == 0
6038 % (STRICT_ALIGNMENT ? GET_MODE_ALIGNMENT (tmode)
6039 : BITS_PER_UNIT)) == 0
6040 /* We can't do this if we are widening INNER_MODE (it
6041 may not be aligned, for one thing). */
6042 && GET_MODE_BITSIZE (inner_mode) >= GET_MODE_BITSIZE (tmode)
6043 && (inner_mode == tmode
6044 || (! mode_dependent_address_p (XEXP (inner, 0))
6045 && ! MEM_VOLATILE_P (inner))))))
6047 /* If INNER is a MEM, make a new MEM that encompasses just the desired
6048 field. If the original and current mode are the same, we need not
6049 adjust the offset. Otherwise, we do if bytes big endian.
6051 If INNER is not a MEM, get a piece consisting of just the field
6052 of interest (in this case POS % BITS_PER_WORD must be 0). */
6054 if (GET_CODE (inner) == MEM)
6056 HOST_WIDE_INT offset;
6058 /* POS counts from lsb, but make OFFSET count in memory order. */
6059 if (BYTES_BIG_ENDIAN)
6060 offset = (GET_MODE_BITSIZE (is_mode) - len - pos) / BITS_PER_UNIT;
6062 offset = pos / BITS_PER_UNIT;
6064 new = adjust_address_nv (inner, tmode, offset);
6066 else if (GET_CODE (inner) == REG)
6068 /* We can't call gen_lowpart_for_combine here since we always want
6069 a SUBREG and it would sometimes return a new hard register. */
6070 if (tmode != inner_mode)
6072 HOST_WIDE_INT final_word = pos / BITS_PER_WORD;
6074 if (WORDS_BIG_ENDIAN
6075 && GET_MODE_SIZE (inner_mode) > UNITS_PER_WORD)
6076 final_word = ((GET_MODE_SIZE (inner_mode)
6077 - GET_MODE_SIZE (tmode))
6078 / UNITS_PER_WORD) - final_word;
6080 final_word *= UNITS_PER_WORD;
6081 if (BYTES_BIG_ENDIAN &&
6082 GET_MODE_SIZE (inner_mode) > GET_MODE_SIZE (tmode))
6083 final_word += (GET_MODE_SIZE (inner_mode)
6084 - GET_MODE_SIZE (tmode)) % UNITS_PER_WORD;
6086 new = gen_rtx_SUBREG (tmode, inner, final_word);
6092 new = force_to_mode (inner, tmode,
6093 len >= HOST_BITS_PER_WIDE_INT
6094 ? ~(unsigned HOST_WIDE_INT) 0
6095 : ((unsigned HOST_WIDE_INT) 1 << len) - 1,
6098 /* If this extraction is going into the destination of a SET,
6099 make a STRICT_LOW_PART unless we made a MEM. */
6102 return (GET_CODE (new) == MEM ? new
6103 : (GET_CODE (new) != SUBREG
6104 ? gen_rtx_CLOBBER (tmode, const0_rtx)
6105 : gen_rtx_STRICT_LOW_PART (VOIDmode, new)));
6110 if (GET_CODE (new) == CONST_INT)
6111 return gen_int_mode (INTVAL (new), mode);
6113 /* If we know that no extraneous bits are set, and that the high
6114 bit is not set, convert the extraction to the cheaper of
6115 sign and zero extension, that are equivalent in these cases. */
6116 if (flag_expensive_optimizations
6117 && (GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT
6118 && ((nonzero_bits (new, tmode)
6119 & ~(((unsigned HOST_WIDE_INT)
6120 GET_MODE_MASK (tmode))
6124 rtx temp = gen_rtx_ZERO_EXTEND (mode, new);
6125 rtx temp1 = gen_rtx_SIGN_EXTEND (mode, new);
6127 /* Prefer ZERO_EXTENSION, since it gives more information to
6129 if (rtx_cost (temp, SET) <= rtx_cost (temp1, SET))
6134 /* Otherwise, sign- or zero-extend unless we already are in the
6137 return (gen_rtx_fmt_e (unsignedp ? ZERO_EXTEND : SIGN_EXTEND,
6141 /* Unless this is a COMPARE or we have a funny memory reference,
6142 don't do anything with zero-extending field extracts starting at
6143 the low-order bit since they are simple AND operations. */
6144 if (pos_rtx == 0 && pos == 0 && ! in_dest
6145 && ! in_compare && ! spans_byte && unsignedp)
6148 /* Unless we are allowed to span bytes or INNER is not MEM, reject this if
6149 we would be spanning bytes or if the position is not a constant and the
6150 length is not 1. In all other cases, we would only be going outside
6151 our object in cases when an original shift would have been
6153 if (! spans_byte && GET_CODE (inner) == MEM
6154 && ((pos_rtx == 0 && pos + len > GET_MODE_BITSIZE (is_mode))
6155 || (pos_rtx != 0 && len != 1)))
6158 /* Get the mode to use should INNER not be a MEM, the mode for the position,
6159 and the mode for the result. */
6160 if (in_dest && mode_for_extraction (EP_insv, -1) != MAX_MACHINE_MODE)
6162 wanted_inner_reg_mode = mode_for_extraction (EP_insv, 0);
6163 pos_mode = mode_for_extraction (EP_insv, 2);
6164 extraction_mode = mode_for_extraction (EP_insv, 3);
6167 if (! in_dest && unsignedp
6168 && mode_for_extraction (EP_extzv, -1) != MAX_MACHINE_MODE)
6170 wanted_inner_reg_mode = mode_for_extraction (EP_extzv, 1);
6171 pos_mode = mode_for_extraction (EP_extzv, 3);
6172 extraction_mode = mode_for_extraction (EP_extzv, 0);
6175 if (! in_dest && ! unsignedp
6176 && mode_for_extraction (EP_extv, -1) != MAX_MACHINE_MODE)
6178 wanted_inner_reg_mode = mode_for_extraction (EP_extv, 1);
6179 pos_mode = mode_for_extraction (EP_extv, 3);
6180 extraction_mode = mode_for_extraction (EP_extv, 0);
6183 /* Never narrow an object, since that might not be safe. */
6185 if (mode != VOIDmode
6186 && GET_MODE_SIZE (extraction_mode) < GET_MODE_SIZE (mode))
6187 extraction_mode = mode;
6189 if (pos_rtx && GET_MODE (pos_rtx) != VOIDmode
6190 && GET_MODE_SIZE (pos_mode) < GET_MODE_SIZE (GET_MODE (pos_rtx)))
6191 pos_mode = GET_MODE (pos_rtx);
6193 /* If this is not from memory, the desired mode is wanted_inner_reg_mode;
6194 if we have to change the mode of memory and cannot, the desired mode is
6196 if (GET_CODE (inner) != MEM)
6197 wanted_inner_mode = wanted_inner_reg_mode;
6198 else if (inner_mode != wanted_inner_mode
6199 && (mode_dependent_address_p (XEXP (inner, 0))
6200 || MEM_VOLATILE_P (inner)))
6201 wanted_inner_mode = extraction_mode;
6205 if (BITS_BIG_ENDIAN)
6207 /* POS is passed as if BITS_BIG_ENDIAN == 0, so we need to convert it to
6208 BITS_BIG_ENDIAN style. If position is constant, compute new
6209 position. Otherwise, build subtraction.
6210 Note that POS is relative to the mode of the original argument.
6211 If it's a MEM we need to recompute POS relative to that.
6212 However, if we're extracting from (or inserting into) a register,
6213 we want to recompute POS relative to wanted_inner_mode. */
6214 int width = (GET_CODE (inner) == MEM
6215 ? GET_MODE_BITSIZE (is_mode)
6216 : GET_MODE_BITSIZE (wanted_inner_mode));
6219 pos = width - len - pos;
6222 = gen_rtx_MINUS (GET_MODE (pos_rtx), GEN_INT (width - len), pos_rtx);
6223 /* POS may be less than 0 now, but we check for that below.
6224 Note that it can only be less than 0 if GET_CODE (inner) != MEM. */
6227 /* If INNER has a wider mode, make it smaller. If this is a constant
6228 extract, try to adjust the byte to point to the byte containing
6230 if (wanted_inner_mode != VOIDmode
6231 && GET_MODE_SIZE (wanted_inner_mode) < GET_MODE_SIZE (is_mode)
6232 && ((GET_CODE (inner) == MEM
6233 && (inner_mode == wanted_inner_mode
6234 || (! mode_dependent_address_p (XEXP (inner, 0))
6235 && ! MEM_VOLATILE_P (inner))))))
6239 /* The computations below will be correct if the machine is big
6240 endian in both bits and bytes or little endian in bits and bytes.
6241 If it is mixed, we must adjust. */
6243 /* If bytes are big endian and we had a paradoxical SUBREG, we must
6244 adjust OFFSET to compensate. */
6245 if (BYTES_BIG_ENDIAN
6247 && GET_MODE_SIZE (inner_mode) < GET_MODE_SIZE (is_mode))
6248 offset -= GET_MODE_SIZE (is_mode) - GET_MODE_SIZE (inner_mode);
6250 /* If this is a constant position, we can move to the desired byte. */
6253 offset += pos / BITS_PER_UNIT;
6254 pos %= GET_MODE_BITSIZE (wanted_inner_mode);
6257 if (BYTES_BIG_ENDIAN != BITS_BIG_ENDIAN
6259 && is_mode != wanted_inner_mode)
6260 offset = (GET_MODE_SIZE (is_mode)
6261 - GET_MODE_SIZE (wanted_inner_mode) - offset);
6263 if (offset != 0 || inner_mode != wanted_inner_mode)
6264 inner = adjust_address_nv (inner, wanted_inner_mode, offset);
6267 /* If INNER is not memory, we can always get it into the proper mode. If we
6268 are changing its mode, POS must be a constant and smaller than the size
6270 else if (GET_CODE (inner) != MEM)
6272 if (GET_MODE (inner) != wanted_inner_mode
6274 || orig_pos + len > GET_MODE_BITSIZE (wanted_inner_mode)))
6277 inner = force_to_mode (inner, wanted_inner_mode,
6279 || len + orig_pos >= HOST_BITS_PER_WIDE_INT
6280 ? ~(unsigned HOST_WIDE_INT) 0
6281 : ((((unsigned HOST_WIDE_INT) 1 << len) - 1)
6286 /* Adjust mode of POS_RTX, if needed. If we want a wider mode, we
6287 have to zero extend. Otherwise, we can just use a SUBREG. */
6289 && GET_MODE_SIZE (pos_mode) > GET_MODE_SIZE (GET_MODE (pos_rtx)))
6291 rtx temp = gen_rtx_ZERO_EXTEND (pos_mode, pos_rtx);
6293 /* If we know that no extraneous bits are set, and that the high
6294 bit is not set, convert extraction to cheaper one - either
6295 SIGN_EXTENSION or ZERO_EXTENSION, that are equivalent in these
6297 if (flag_expensive_optimizations
6298 && (GET_MODE_BITSIZE (GET_MODE (pos_rtx)) <= HOST_BITS_PER_WIDE_INT
6299 && ((nonzero_bits (pos_rtx, GET_MODE (pos_rtx))
6300 & ~(((unsigned HOST_WIDE_INT)
6301 GET_MODE_MASK (GET_MODE (pos_rtx)))
6305 rtx temp1 = gen_rtx_SIGN_EXTEND (pos_mode, pos_rtx);
6307 /* Prefer ZERO_EXTENSION, since it gives more information to
6309 if (rtx_cost (temp1, SET) < rtx_cost (temp, SET))
6314 else if (pos_rtx != 0
6315 && GET_MODE_SIZE (pos_mode) < GET_MODE_SIZE (GET_MODE (pos_rtx)))
6316 pos_rtx = gen_lowpart_for_combine (pos_mode, pos_rtx);
6318 /* Make POS_RTX unless we already have it and it is correct. If we don't
6319 have a POS_RTX but we do have an ORIG_POS_RTX, the latter must
6321 if (pos_rtx == 0 && orig_pos_rtx != 0 && INTVAL (orig_pos_rtx) == pos)
6322 pos_rtx = orig_pos_rtx;
6324 else if (pos_rtx == 0)
6325 pos_rtx = GEN_INT (pos);
6327 /* Make the required operation. See if we can use existing rtx. */
6328 new = gen_rtx_fmt_eee (unsignedp ? ZERO_EXTRACT : SIGN_EXTRACT,
6329 extraction_mode, inner, GEN_INT (len), pos_rtx);
6331 new = gen_lowpart_for_combine (mode, new);
6336 /* See if X contains an ASHIFT of COUNT or more bits that can be commuted
6337 with any other operations in X. Return X without that shift if so. */
6340 extract_left_shift (x, count)
6344 enum rtx_code code = GET_CODE (x);
6345 enum machine_mode mode = GET_MODE (x);
6351 /* This is the shift itself. If it is wide enough, we will return
6352 either the value being shifted if the shift count is equal to
6353 COUNT or a shift for the difference. */
6354 if (GET_CODE (XEXP (x, 1)) == CONST_INT
6355 && INTVAL (XEXP (x, 1)) >= count)
6356 return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (x, 0),
6357 INTVAL (XEXP (x, 1)) - count);
6361 if ((tem = extract_left_shift (XEXP (x, 0), count)) != 0)
6362 return simplify_gen_unary (code, mode, tem, mode);
6366 case PLUS: case IOR: case XOR: case AND:
6367 /* If we can safely shift this constant and we find the inner shift,
6368 make a new operation. */
6369 if (GET_CODE (XEXP (x,1)) == CONST_INT
6370 && (INTVAL (XEXP (x, 1)) & ((((HOST_WIDE_INT) 1 << count)) - 1)) == 0
6371 && (tem = extract_left_shift (XEXP (x, 0), count)) != 0)
6372 return gen_binary (code, mode, tem,
6373 GEN_INT (INTVAL (XEXP (x, 1)) >> count));
6384 /* Look at the expression rooted at X. Look for expressions
6385 equivalent to ZERO_EXTRACT, SIGN_EXTRACT, ZERO_EXTEND, SIGN_EXTEND.
6386 Form these expressions.
6388 Return the new rtx, usually just X.
6390 Also, for machines like the VAX that don't have logical shift insns,
6391 try to convert logical to arithmetic shift operations in cases where
6392 they are equivalent. This undoes the canonicalizations to logical
6393 shifts done elsewhere.
6395 We try, as much as possible, to re-use rtl expressions to save memory.
6397 IN_CODE says what kind of expression we are processing. Normally, it is
6398 SET. In a memory address (inside a MEM, PLUS or minus, the latter two
6399 being kludges), it is MEM. When processing the arguments of a comparison
6400 or a COMPARE against zero, it is COMPARE. */
6403 make_compound_operation (x, in_code)
6405 enum rtx_code in_code;
6407 enum rtx_code code = GET_CODE (x);
6408 enum machine_mode mode = GET_MODE (x);
6409 int mode_width = GET_MODE_BITSIZE (mode);
6411 enum rtx_code next_code;
6417 /* Select the code to be used in recursive calls. Once we are inside an
6418 address, we stay there. If we have a comparison, set to COMPARE,
6419 but once inside, go back to our default of SET. */
6421 next_code = (code == MEM || code == PLUS || code == MINUS ? MEM
6422 : ((code == COMPARE || GET_RTX_CLASS (code) == '<')
6423 && XEXP (x, 1) == const0_rtx) ? COMPARE
6424 : in_code == COMPARE ? SET : in_code);
6426 /* Process depending on the code of this operation. If NEW is set
6427 non-zero, it will be returned. */
6432 /* Convert shifts by constants into multiplications if inside
6434 if (in_code == MEM && GET_CODE (XEXP (x, 1)) == CONST_INT
6435 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT
6436 && INTVAL (XEXP (x, 1)) >= 0)
6438 new = make_compound_operation (XEXP (x, 0), next_code);
6439 new = gen_rtx_MULT (mode, new,
6440 GEN_INT ((HOST_WIDE_INT) 1
6441 << INTVAL (XEXP (x, 1))));
6446 /* If the second operand is not a constant, we can't do anything
6448 if (GET_CODE (XEXP (x, 1)) != CONST_INT)
6451 /* If the constant is a power of two minus one and the first operand
6452 is a logical right shift, make an extraction. */
6453 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
6454 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6456 new = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code);
6457 new = make_extraction (mode, new, 0, XEXP (XEXP (x, 0), 1), i, 1,
6458 0, in_code == COMPARE);
6461 /* Same as previous, but for (subreg (lshiftrt ...)) in first op. */
6462 else if (GET_CODE (XEXP (x, 0)) == SUBREG
6463 && subreg_lowpart_p (XEXP (x, 0))
6464 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == LSHIFTRT
6465 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6467 new = make_compound_operation (XEXP (SUBREG_REG (XEXP (x, 0)), 0),
6469 new = make_extraction (GET_MODE (SUBREG_REG (XEXP (x, 0))), new, 0,
6470 XEXP (SUBREG_REG (XEXP (x, 0)), 1), i, 1,
6471 0, in_code == COMPARE);
6473 /* Same as previous, but for (xor/ior (lshiftrt...) (lshiftrt...)). */
6474 else if ((GET_CODE (XEXP (x, 0)) == XOR
6475 || GET_CODE (XEXP (x, 0)) == IOR)
6476 && GET_CODE (XEXP (XEXP (x, 0), 0)) == LSHIFTRT
6477 && GET_CODE (XEXP (XEXP (x, 0), 1)) == LSHIFTRT
6478 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6480 /* Apply the distributive law, and then try to make extractions. */
6481 new = gen_rtx_fmt_ee (GET_CODE (XEXP (x, 0)), mode,
6482 gen_rtx_AND (mode, XEXP (XEXP (x, 0), 0),
6484 gen_rtx_AND (mode, XEXP (XEXP (x, 0), 1),
6486 new = make_compound_operation (new, in_code);
6489 /* If we are have (and (rotate X C) M) and C is larger than the number
6490 of bits in M, this is an extraction. */
6492 else if (GET_CODE (XEXP (x, 0)) == ROTATE
6493 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
6494 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0
6495 && i <= INTVAL (XEXP (XEXP (x, 0), 1)))
6497 new = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code);
6498 new = make_extraction (mode, new,
6499 (GET_MODE_BITSIZE (mode)
6500 - INTVAL (XEXP (XEXP (x, 0), 1))),
6501 NULL_RTX, i, 1, 0, in_code == COMPARE);
6504 /* On machines without logical shifts, if the operand of the AND is
6505 a logical shift and our mask turns off all the propagated sign
6506 bits, we can replace the logical shift with an arithmetic shift. */
6507 else if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
6508 && !have_insn_for (LSHIFTRT, mode)
6509 && have_insn_for (ASHIFTRT, mode)
6510 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
6511 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
6512 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT
6513 && mode_width <= HOST_BITS_PER_WIDE_INT)
6515 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
6517 mask >>= INTVAL (XEXP (XEXP (x, 0), 1));
6518 if ((INTVAL (XEXP (x, 1)) & ~mask) == 0)
6520 gen_rtx_ASHIFTRT (mode,
6521 make_compound_operation
6522 (XEXP (XEXP (x, 0), 0), next_code),
6523 XEXP (XEXP (x, 0), 1)));
6526 /* If the constant is one less than a power of two, this might be
6527 representable by an extraction even if no shift is present.
6528 If it doesn't end up being a ZERO_EXTEND, we will ignore it unless
6529 we are in a COMPARE. */
6530 else if ((i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6531 new = make_extraction (mode,
6532 make_compound_operation (XEXP (x, 0),
6534 0, NULL_RTX, i, 1, 0, in_code == COMPARE);
6536 /* If we are in a comparison and this is an AND with a power of two,
6537 convert this into the appropriate bit extract. */
6538 else if (in_code == COMPARE
6539 && (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0)
6540 new = make_extraction (mode,
6541 make_compound_operation (XEXP (x, 0),
6543 i, NULL_RTX, 1, 1, 0, 1);
6548 /* If the sign bit is known to be zero, replace this with an
6549 arithmetic shift. */
6550 if (have_insn_for (ASHIFTRT, mode)
6551 && ! have_insn_for (LSHIFTRT, mode)
6552 && mode_width <= HOST_BITS_PER_WIDE_INT
6553 && (nonzero_bits (XEXP (x, 0), mode) & (1 << (mode_width - 1))) == 0)
6555 new = gen_rtx_ASHIFTRT (mode,
6556 make_compound_operation (XEXP (x, 0),
6562 /* ... fall through ... */
6568 /* If we have (ashiftrt (ashift foo C1) C2) with C2 >= C1,
6569 this is a SIGN_EXTRACT. */
6570 if (GET_CODE (rhs) == CONST_INT
6571 && GET_CODE (lhs) == ASHIFT
6572 && GET_CODE (XEXP (lhs, 1)) == CONST_INT
6573 && INTVAL (rhs) >= INTVAL (XEXP (lhs, 1)))
6575 new = make_compound_operation (XEXP (lhs, 0), next_code);
6576 new = make_extraction (mode, new,
6577 INTVAL (rhs) - INTVAL (XEXP (lhs, 1)),
6578 NULL_RTX, mode_width - INTVAL (rhs),
6579 code == LSHIFTRT, 0, in_code == COMPARE);
6583 /* See if we have operations between an ASHIFTRT and an ASHIFT.
6584 If so, try to merge the shifts into a SIGN_EXTEND. We could
6585 also do this for some cases of SIGN_EXTRACT, but it doesn't
6586 seem worth the effort; the case checked for occurs on Alpha. */
6588 if (GET_RTX_CLASS (GET_CODE (lhs)) != 'o'
6589 && ! (GET_CODE (lhs) == SUBREG
6590 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (lhs))) == 'o'))
6591 && GET_CODE (rhs) == CONST_INT
6592 && INTVAL (rhs) < HOST_BITS_PER_WIDE_INT
6593 && (new = extract_left_shift (lhs, INTVAL (rhs))) != 0)
6594 new = make_extraction (mode, make_compound_operation (new, next_code),
6595 0, NULL_RTX, mode_width - INTVAL (rhs),
6596 code == LSHIFTRT, 0, in_code == COMPARE);
6601 /* Call ourselves recursively on the inner expression. If we are
6602 narrowing the object and it has a different RTL code from
6603 what it originally did, do this SUBREG as a force_to_mode. */
6605 tem = make_compound_operation (SUBREG_REG (x), in_code);
6606 if (GET_CODE (tem) != GET_CODE (SUBREG_REG (x))
6607 && GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (tem))
6608 && subreg_lowpart_p (x))
6610 rtx newer = force_to_mode (tem, mode, ~(HOST_WIDE_INT) 0,
6613 /* If we have something other than a SUBREG, we might have
6614 done an expansion, so rerun ourselves. */
6615 if (GET_CODE (newer) != SUBREG)
6616 newer = make_compound_operation (newer, in_code);
6621 /* If this is a paradoxical subreg, and the new code is a sign or
6622 zero extension, omit the subreg and widen the extension. If it
6623 is a regular subreg, we can still get rid of the subreg by not
6624 widening so much, or in fact removing the extension entirely. */
6625 if ((GET_CODE (tem) == SIGN_EXTEND
6626 || GET_CODE (tem) == ZERO_EXTEND)
6627 && subreg_lowpart_p (x))
6629 if (GET_MODE_SIZE (mode) > GET_MODE_SIZE (GET_MODE (tem))
6630 || (GET_MODE_SIZE (mode) >
6631 GET_MODE_SIZE (GET_MODE (XEXP (tem, 0)))))
6633 if (! INTEGRAL_MODE_P (mode))
6635 tem = gen_rtx_fmt_e (GET_CODE (tem), mode, XEXP (tem, 0));
6638 tem = gen_lowpart_for_combine (mode, XEXP (tem, 0));
6649 x = gen_lowpart_for_combine (mode, new);
6650 code = GET_CODE (x);
6653 /* Now recursively process each operand of this operation. */
6654 fmt = GET_RTX_FORMAT (code);
6655 for (i = 0; i < GET_RTX_LENGTH (code); i++)
6658 new = make_compound_operation (XEXP (x, i), next_code);
6659 SUBST (XEXP (x, i), new);
6665 /* Given M see if it is a value that would select a field of bits
6666 within an item, but not the entire word. Return -1 if not.
6667 Otherwise, return the starting position of the field, where 0 is the
6670 *PLEN is set to the length of the field. */
6673 get_pos_from_mask (m, plen)
6674 unsigned HOST_WIDE_INT m;
6675 unsigned HOST_WIDE_INT *plen;
6677 /* Get the bit number of the first 1 bit from the right, -1 if none. */
6678 int pos = exact_log2 (m & -m);
6684 /* Now shift off the low-order zero bits and see if we have a power of
6686 len = exact_log2 ((m >> pos) + 1);
6695 /* See if X can be simplified knowing that we will only refer to it in
6696 MODE and will only refer to those bits that are nonzero in MASK.
6697 If other bits are being computed or if masking operations are done
6698 that select a superset of the bits in MASK, they can sometimes be
6701 Return a possibly simplified expression, but always convert X to
6702 MODE. If X is a CONST_INT, AND the CONST_INT with MASK.
6704 Also, if REG is non-zero and X is a register equal in value to REG,
6707 If JUST_SELECT is nonzero, don't optimize by noticing that bits in MASK
6708 are all off in X. This is used when X will be complemented, by either
6709 NOT, NEG, or XOR. */
6712 force_to_mode (x, mode, mask, reg, just_select)
6714 enum machine_mode mode;
6715 unsigned HOST_WIDE_INT mask;
6719 enum rtx_code code = GET_CODE (x);
6720 int next_select = just_select || code == XOR || code == NOT || code == NEG;
6721 enum machine_mode op_mode;
6722 unsigned HOST_WIDE_INT fuller_mask, nonzero;
6725 /* If this is a CALL or ASM_OPERANDS, don't do anything. Some of the
6726 code below will do the wrong thing since the mode of such an
6727 expression is VOIDmode.
6729 Also do nothing if X is a CLOBBER; this can happen if X was
6730 the return value from a call to gen_lowpart_for_combine. */
6731 if (code == CALL || code == ASM_OPERANDS || code == CLOBBER)
6734 /* We want to perform the operation is its present mode unless we know
6735 that the operation is valid in MODE, in which case we do the operation
6737 op_mode = ((GET_MODE_CLASS (mode) == GET_MODE_CLASS (GET_MODE (x))
6738 && have_insn_for (code, mode))
6739 ? mode : GET_MODE (x));
6741 /* It is not valid to do a right-shift in a narrower mode
6742 than the one it came in with. */
6743 if ((code == LSHIFTRT || code == ASHIFTRT)
6744 && GET_MODE_BITSIZE (mode) < GET_MODE_BITSIZE (GET_MODE (x)))
6745 op_mode = GET_MODE (x);
6747 /* Truncate MASK to fit OP_MODE. */
6749 mask &= GET_MODE_MASK (op_mode);
6751 /* When we have an arithmetic operation, or a shift whose count we
6752 do not know, we need to assume that all bit the up to the highest-order
6753 bit in MASK will be needed. This is how we form such a mask. */
6755 fuller_mask = (GET_MODE_BITSIZE (op_mode) >= HOST_BITS_PER_WIDE_INT
6756 ? GET_MODE_MASK (op_mode)
6757 : (((unsigned HOST_WIDE_INT) 1 << (floor_log2 (mask) + 1))
6760 fuller_mask = ~(HOST_WIDE_INT) 0;
6762 /* Determine what bits of X are guaranteed to be (non)zero. */
6763 nonzero = nonzero_bits (x, mode);
6765 /* If none of the bits in X are needed, return a zero. */
6766 if (! just_select && (nonzero & mask) == 0)
6769 /* If X is a CONST_INT, return a new one. Do this here since the
6770 test below will fail. */
6771 if (GET_CODE (x) == CONST_INT)
6772 return gen_int_mode (INTVAL (x) & mask, mode);
6774 /* If X is narrower than MODE and we want all the bits in X's mode, just
6775 get X in the proper mode. */
6776 if (GET_MODE_SIZE (GET_MODE (x)) < GET_MODE_SIZE (mode)
6777 && (GET_MODE_MASK (GET_MODE (x)) & ~mask) == 0)
6778 return gen_lowpart_for_combine (mode, x);
6780 /* If we aren't changing the mode, X is not a SUBREG, and all zero bits in
6781 MASK are already known to be zero in X, we need not do anything. */
6782 if (GET_MODE (x) == mode && code != SUBREG && (~mask & nonzero) == 0)
6788 /* If X is a (clobber (const_int)), return it since we know we are
6789 generating something that won't match. */
6793 /* X is a (use (mem ..)) that was made from a bit-field extraction that
6794 spanned the boundary of the MEM. If we are now masking so it is
6795 within that boundary, we don't need the USE any more. */
6796 if (! BITS_BIG_ENDIAN
6797 && (mask & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
6798 return force_to_mode (XEXP (x, 0), mode, mask, reg, next_select);
6805 x = expand_compound_operation (x);
6806 if (GET_CODE (x) != code)
6807 return force_to_mode (x, mode, mask, reg, next_select);
6811 if (reg != 0 && (rtx_equal_p (get_last_value (reg), x)
6812 || rtx_equal_p (reg, get_last_value (x))))
6817 if (subreg_lowpart_p (x)
6818 /* We can ignore the effect of this SUBREG if it narrows the mode or
6819 if the constant masks to zero all the bits the mode doesn't
6821 && ((GET_MODE_SIZE (GET_MODE (x))
6822 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
6824 & GET_MODE_MASK (GET_MODE (x))
6825 & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (x)))))))
6826 return force_to_mode (SUBREG_REG (x), mode, mask, reg, next_select);
6830 /* If this is an AND with a constant, convert it into an AND
6831 whose constant is the AND of that constant with MASK. If it
6832 remains an AND of MASK, delete it since it is redundant. */
6834 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
6836 x = simplify_and_const_int (x, op_mode, XEXP (x, 0),
6837 mask & INTVAL (XEXP (x, 1)));
6839 /* If X is still an AND, see if it is an AND with a mask that
6840 is just some low-order bits. If so, and it is MASK, we don't
6843 if (GET_CODE (x) == AND && GET_CODE (XEXP (x, 1)) == CONST_INT
6844 && ((INTVAL (XEXP (x, 1)) & GET_MODE_MASK (GET_MODE (x)))
6848 /* If it remains an AND, try making another AND with the bits
6849 in the mode mask that aren't in MASK turned on. If the
6850 constant in the AND is wide enough, this might make a
6851 cheaper constant. */
6853 if (GET_CODE (x) == AND && GET_CODE (XEXP (x, 1)) == CONST_INT
6854 && GET_MODE_MASK (GET_MODE (x)) != mask
6855 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT)
6857 HOST_WIDE_INT cval = (INTVAL (XEXP (x, 1))
6858 | (GET_MODE_MASK (GET_MODE (x)) & ~mask));
6859 int width = GET_MODE_BITSIZE (GET_MODE (x));
6862 /* If MODE is narrower that HOST_WIDE_INT and CVAL is a negative
6863 number, sign extend it. */
6864 if (width > 0 && width < HOST_BITS_PER_WIDE_INT
6865 && (cval & ((HOST_WIDE_INT) 1 << (width - 1))) != 0)
6866 cval |= (HOST_WIDE_INT) -1 << width;
6868 y = gen_binary (AND, GET_MODE (x), XEXP (x, 0), GEN_INT (cval));
6869 if (rtx_cost (y, SET) < rtx_cost (x, SET))
6879 /* In (and (plus FOO C1) M), if M is a mask that just turns off
6880 low-order bits (as in an alignment operation) and FOO is already
6881 aligned to that boundary, mask C1 to that boundary as well.
6882 This may eliminate that PLUS and, later, the AND. */
6885 unsigned int width = GET_MODE_BITSIZE (mode);
6886 unsigned HOST_WIDE_INT smask = mask;
6888 /* If MODE is narrower than HOST_WIDE_INT and mask is a negative
6889 number, sign extend it. */
6891 if (width < HOST_BITS_PER_WIDE_INT
6892 && (smask & ((HOST_WIDE_INT) 1 << (width - 1))) != 0)
6893 smask |= (HOST_WIDE_INT) -1 << width;
6895 if (GET_CODE (XEXP (x, 1)) == CONST_INT
6896 && exact_log2 (- smask) >= 0
6897 && (nonzero_bits (XEXP (x, 0), mode) & ~smask) == 0
6898 && (INTVAL (XEXP (x, 1)) & ~smask) != 0)
6899 return force_to_mode (plus_constant (XEXP (x, 0),
6900 (INTVAL (XEXP (x, 1)) & smask)),
6901 mode, smask, reg, next_select);
6904 /* ... fall through ... */
6907 /* For PLUS, MINUS and MULT, we need any bits less significant than the
6908 most significant bit in MASK since carries from those bits will
6909 affect the bits we are interested in. */
6914 /* If X is (minus C Y) where C's least set bit is larger than any bit
6915 in the mask, then we may replace with (neg Y). */
6916 if (GET_CODE (XEXP (x, 0)) == CONST_INT
6917 && (((unsigned HOST_WIDE_INT) (INTVAL (XEXP (x, 0))
6918 & -INTVAL (XEXP (x, 0))))
6921 x = simplify_gen_unary (NEG, GET_MODE (x), XEXP (x, 1),
6923 return force_to_mode (x, mode, mask, reg, next_select);
6926 /* Similarly, if C contains every bit in the mask, then we may
6927 replace with (not Y). */
6928 if (GET_CODE (XEXP (x, 0)) == CONST_INT
6929 && ((INTVAL (XEXP (x, 0)) | (HOST_WIDE_INT) mask)
6930 == INTVAL (XEXP (x, 0))))
6932 x = simplify_gen_unary (NOT, GET_MODE (x),
6933 XEXP (x, 1), GET_MODE (x));
6934 return force_to_mode (x, mode, mask, reg, next_select);
6942 /* If X is (ior (lshiftrt FOO C1) C2), try to commute the IOR and
6943 LSHIFTRT so we end up with an (and (lshiftrt (ior ...) ...) ...)
6944 operation which may be a bitfield extraction. Ensure that the
6945 constant we form is not wider than the mode of X. */
6947 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
6948 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
6949 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
6950 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT
6951 && GET_CODE (XEXP (x, 1)) == CONST_INT
6952 && ((INTVAL (XEXP (XEXP (x, 0), 1))
6953 + floor_log2 (INTVAL (XEXP (x, 1))))
6954 < GET_MODE_BITSIZE (GET_MODE (x)))
6955 && (INTVAL (XEXP (x, 1))
6956 & ~nonzero_bits (XEXP (x, 0), GET_MODE (x))) == 0)
6958 temp = GEN_INT ((INTVAL (XEXP (x, 1)) & mask)
6959 << INTVAL (XEXP (XEXP (x, 0), 1)));
6960 temp = gen_binary (GET_CODE (x), GET_MODE (x),
6961 XEXP (XEXP (x, 0), 0), temp);
6962 x = gen_binary (LSHIFTRT, GET_MODE (x), temp,
6963 XEXP (XEXP (x, 0), 1));
6964 return force_to_mode (x, mode, mask, reg, next_select);
6968 /* For most binary operations, just propagate into the operation and
6969 change the mode if we have an operation of that mode. */
6971 op0 = gen_lowpart_for_combine (op_mode,
6972 force_to_mode (XEXP (x, 0), mode, mask,
6974 op1 = gen_lowpart_for_combine (op_mode,
6975 force_to_mode (XEXP (x, 1), mode, mask,
6978 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
6979 x = gen_binary (code, op_mode, op0, op1);
6983 /* For left shifts, do the same, but just for the first operand.
6984 However, we cannot do anything with shifts where we cannot
6985 guarantee that the counts are smaller than the size of the mode
6986 because such a count will have a different meaning in a
6989 if (! (GET_CODE (XEXP (x, 1)) == CONST_INT
6990 && INTVAL (XEXP (x, 1)) >= 0
6991 && INTVAL (XEXP (x, 1)) < GET_MODE_BITSIZE (mode))
6992 && ! (GET_MODE (XEXP (x, 1)) != VOIDmode
6993 && (nonzero_bits (XEXP (x, 1), GET_MODE (XEXP (x, 1)))
6994 < (unsigned HOST_WIDE_INT) GET_MODE_BITSIZE (mode))))
6997 /* If the shift count is a constant and we can do arithmetic in
6998 the mode of the shift, refine which bits we need. Otherwise, use the
6999 conservative form of the mask. */
7000 if (GET_CODE (XEXP (x, 1)) == CONST_INT
7001 && INTVAL (XEXP (x, 1)) >= 0
7002 && INTVAL (XEXP (x, 1)) < GET_MODE_BITSIZE (op_mode)
7003 && GET_MODE_BITSIZE (op_mode) <= HOST_BITS_PER_WIDE_INT)
7004 mask >>= INTVAL (XEXP (x, 1));
7008 op0 = gen_lowpart_for_combine (op_mode,
7009 force_to_mode (XEXP (x, 0), op_mode,
7010 mask, reg, next_select));
7012 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0))
7013 x = gen_binary (code, op_mode, op0, XEXP (x, 1));
7017 /* Here we can only do something if the shift count is a constant,
7018 this shift constant is valid for the host, and we can do arithmetic
7021 if (GET_CODE (XEXP (x, 1)) == CONST_INT
7022 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT
7023 && GET_MODE_BITSIZE (op_mode) <= HOST_BITS_PER_WIDE_INT)
7025 rtx inner = XEXP (x, 0);
7026 unsigned HOST_WIDE_INT inner_mask;
7028 /* Select the mask of the bits we need for the shift operand. */
7029 inner_mask = mask << INTVAL (XEXP (x, 1));
7031 /* We can only change the mode of the shift if we can do arithmetic
7032 in the mode of the shift and INNER_MASK is no wider than the
7033 width of OP_MODE. */
7034 if (GET_MODE_BITSIZE (op_mode) > HOST_BITS_PER_WIDE_INT
7035 || (inner_mask & ~GET_MODE_MASK (op_mode)) != 0)
7036 op_mode = GET_MODE (x);
7038 inner = force_to_mode (inner, op_mode, inner_mask, reg, next_select);
7040 if (GET_MODE (x) != op_mode || inner != XEXP (x, 0))
7041 x = gen_binary (LSHIFTRT, op_mode, inner, XEXP (x, 1));
7044 /* If we have (and (lshiftrt FOO C1) C2) where the combination of the
7045 shift and AND produces only copies of the sign bit (C2 is one less
7046 than a power of two), we can do this with just a shift. */
7048 if (GET_CODE (x) == LSHIFTRT
7049 && GET_CODE (XEXP (x, 1)) == CONST_INT
7050 /* The shift puts one of the sign bit copies in the least significant
7052 && ((INTVAL (XEXP (x, 1))
7053 + num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0))))
7054 >= GET_MODE_BITSIZE (GET_MODE (x)))
7055 && exact_log2 (mask + 1) >= 0
7056 /* Number of bits left after the shift must be more than the mask
7058 && ((INTVAL (XEXP (x, 1)) + exact_log2 (mask + 1))
7059 <= GET_MODE_BITSIZE (GET_MODE (x)))
7060 /* Must be more sign bit copies than the mask needs. */
7061 && ((int) num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
7062 >= exact_log2 (mask + 1)))
7063 x = gen_binary (LSHIFTRT, GET_MODE (x), XEXP (x, 0),
7064 GEN_INT (GET_MODE_BITSIZE (GET_MODE (x))
7065 - exact_log2 (mask + 1)));
7070 /* If we are just looking for the sign bit, we don't need this shift at
7071 all, even if it has a variable count. */
7072 if (GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
7073 && (mask == ((unsigned HOST_WIDE_INT) 1
7074 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
7075 return force_to_mode (XEXP (x, 0), mode, mask, reg, next_select);
7077 /* If this is a shift by a constant, get a mask that contains those bits
7078 that are not copies of the sign bit. We then have two cases: If
7079 MASK only includes those bits, this can be a logical shift, which may
7080 allow simplifications. If MASK is a single-bit field not within
7081 those bits, we are requesting a copy of the sign bit and hence can
7082 shift the sign bit to the appropriate location. */
7084 if (GET_CODE (XEXP (x, 1)) == CONST_INT && INTVAL (XEXP (x, 1)) >= 0
7085 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT)
7089 /* If the considered data is wider than HOST_WIDE_INT, we can't
7090 represent a mask for all its bits in a single scalar.
7091 But we only care about the lower bits, so calculate these. */
7093 if (GET_MODE_BITSIZE (GET_MODE (x)) > HOST_BITS_PER_WIDE_INT)
7095 nonzero = ~(HOST_WIDE_INT) 0;
7097 /* GET_MODE_BITSIZE (GET_MODE (x)) - INTVAL (XEXP (x, 1))
7098 is the number of bits a full-width mask would have set.
7099 We need only shift if these are fewer than nonzero can
7100 hold. If not, we must keep all bits set in nonzero. */
7102 if (GET_MODE_BITSIZE (GET_MODE (x)) - INTVAL (XEXP (x, 1))
7103 < HOST_BITS_PER_WIDE_INT)
7104 nonzero >>= INTVAL (XEXP (x, 1))
7105 + HOST_BITS_PER_WIDE_INT
7106 - GET_MODE_BITSIZE (GET_MODE (x)) ;
7110 nonzero = GET_MODE_MASK (GET_MODE (x));
7111 nonzero >>= INTVAL (XEXP (x, 1));
7114 if ((mask & ~nonzero) == 0
7115 || (i = exact_log2 (mask)) >= 0)
7117 x = simplify_shift_const
7118 (x, LSHIFTRT, GET_MODE (x), XEXP (x, 0),
7119 i < 0 ? INTVAL (XEXP (x, 1))
7120 : GET_MODE_BITSIZE (GET_MODE (x)) - 1 - i);
7122 if (GET_CODE (x) != ASHIFTRT)
7123 return force_to_mode (x, mode, mask, reg, next_select);
7127 /* If MASK is 1, convert this to an LSHIFTRT. This can be done
7128 even if the shift count isn't a constant. */
7130 x = gen_binary (LSHIFTRT, GET_MODE (x), XEXP (x, 0), XEXP (x, 1));
7134 /* If this is a zero- or sign-extension operation that just affects bits
7135 we don't care about, remove it. Be sure the call above returned
7136 something that is still a shift. */
7138 if ((GET_CODE (x) == LSHIFTRT || GET_CODE (x) == ASHIFTRT)
7139 && GET_CODE (XEXP (x, 1)) == CONST_INT
7140 && INTVAL (XEXP (x, 1)) >= 0
7141 && (INTVAL (XEXP (x, 1))
7142 <= GET_MODE_BITSIZE (GET_MODE (x)) - (floor_log2 (mask) + 1))
7143 && GET_CODE (XEXP (x, 0)) == ASHIFT
7144 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
7145 && INTVAL (XEXP (XEXP (x, 0), 1)) == INTVAL (XEXP (x, 1)))
7146 return force_to_mode (XEXP (XEXP (x, 0), 0), mode, mask,
7153 /* If the shift count is constant and we can do computations
7154 in the mode of X, compute where the bits we care about are.
7155 Otherwise, we can't do anything. Don't change the mode of
7156 the shift or propagate MODE into the shift, though. */
7157 if (GET_CODE (XEXP (x, 1)) == CONST_INT
7158 && INTVAL (XEXP (x, 1)) >= 0)
7160 temp = simplify_binary_operation (code == ROTATE ? ROTATERT : ROTATE,
7161 GET_MODE (x), GEN_INT (mask),
7163 if (temp && GET_CODE(temp) == CONST_INT)
7165 force_to_mode (XEXP (x, 0), GET_MODE (x),
7166 INTVAL (temp), reg, next_select));
7171 /* If we just want the low-order bit, the NEG isn't needed since it
7172 won't change the low-order bit. */
7174 return force_to_mode (XEXP (x, 0), mode, mask, reg, just_select);
7176 /* We need any bits less significant than the most significant bit in
7177 MASK since carries from those bits will affect the bits we are
7183 /* (not FOO) is (xor FOO CONST), so if FOO is an LSHIFTRT, we can do the
7184 same as the XOR case above. Ensure that the constant we form is not
7185 wider than the mode of X. */
7187 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
7188 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
7189 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
7190 && (INTVAL (XEXP (XEXP (x, 0), 1)) + floor_log2 (mask)
7191 < GET_MODE_BITSIZE (GET_MODE (x)))
7192 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT)
7194 temp = GEN_INT (mask << INTVAL (XEXP (XEXP (x, 0), 1)));
7195 temp = gen_binary (XOR, GET_MODE (x), XEXP (XEXP (x, 0), 0), temp);
7196 x = gen_binary (LSHIFTRT, GET_MODE (x), temp, XEXP (XEXP (x, 0), 1));
7198 return force_to_mode (x, mode, mask, reg, next_select);
7201 /* (and (not FOO) CONST) is (not (or FOO (not CONST))), so we must
7202 use the full mask inside the NOT. */
7206 op0 = gen_lowpart_for_combine (op_mode,
7207 force_to_mode (XEXP (x, 0), mode, mask,
7209 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0))
7210 x = simplify_gen_unary (code, op_mode, op0, op_mode);
7214 /* (and (ne FOO 0) CONST) can be (and FOO CONST) if CONST is included
7215 in STORE_FLAG_VALUE and FOO has a single bit that might be nonzero,
7216 which is equal to STORE_FLAG_VALUE. */
7217 if ((mask & ~STORE_FLAG_VALUE) == 0 && XEXP (x, 1) == const0_rtx
7218 && exact_log2 (nonzero_bits (XEXP (x, 0), mode)) >= 0
7219 && nonzero_bits (XEXP (x, 0), mode) == STORE_FLAG_VALUE)
7220 return force_to_mode (XEXP (x, 0), mode, mask, reg, next_select);
7225 /* We have no way of knowing if the IF_THEN_ELSE can itself be
7226 written in a narrower mode. We play it safe and do not do so. */
7229 gen_lowpart_for_combine (GET_MODE (x),
7230 force_to_mode (XEXP (x, 1), mode,
7231 mask, reg, next_select)));
7233 gen_lowpart_for_combine (GET_MODE (x),
7234 force_to_mode (XEXP (x, 2), mode,
7235 mask, reg,next_select)));
7242 /* Ensure we return a value of the proper mode. */
7243 return gen_lowpart_for_combine (mode, x);
7246 /* Return nonzero if X is an expression that has one of two values depending on
7247 whether some other value is zero or nonzero. In that case, we return the
7248 value that is being tested, *PTRUE is set to the value if the rtx being
7249 returned has a nonzero value, and *PFALSE is set to the other alternative.
7251 If we return zero, we set *PTRUE and *PFALSE to X. */
7254 if_then_else_cond (x, ptrue, pfalse)
7256 rtx *ptrue, *pfalse;
7258 enum machine_mode mode = GET_MODE (x);
7259 enum rtx_code code = GET_CODE (x);
7260 rtx cond0, cond1, true0, true1, false0, false1;
7261 unsigned HOST_WIDE_INT nz;
7263 /* If we are comparing a value against zero, we are done. */
7264 if ((code == NE || code == EQ)
7265 && GET_CODE (XEXP (x, 1)) == CONST_INT && INTVAL (XEXP (x, 1)) == 0)
7267 *ptrue = (code == NE) ? const_true_rtx : const0_rtx;
7268 *pfalse = (code == NE) ? const0_rtx : const_true_rtx;
7272 /* If this is a unary operation whose operand has one of two values, apply
7273 our opcode to compute those values. */
7274 else if (GET_RTX_CLASS (code) == '1'
7275 && (cond0 = if_then_else_cond (XEXP (x, 0), &true0, &false0)) != 0)
7277 *ptrue = simplify_gen_unary (code, mode, true0, GET_MODE (XEXP (x, 0)));
7278 *pfalse = simplify_gen_unary (code, mode, false0,
7279 GET_MODE (XEXP (x, 0)));
7283 /* If this is a COMPARE, do nothing, since the IF_THEN_ELSE we would
7284 make can't possibly match and would suppress other optimizations. */
7285 else if (code == COMPARE)
7288 /* If this is a binary operation, see if either side has only one of two
7289 values. If either one does or if both do and they are conditional on
7290 the same value, compute the new true and false values. */
7291 else if (GET_RTX_CLASS (code) == 'c' || GET_RTX_CLASS (code) == '2'
7292 || GET_RTX_CLASS (code) == '<')
7294 cond0 = if_then_else_cond (XEXP (x, 0), &true0, &false0);
7295 cond1 = if_then_else_cond (XEXP (x, 1), &true1, &false1);
7297 if ((cond0 != 0 || cond1 != 0)
7298 && ! (cond0 != 0 && cond1 != 0 && ! rtx_equal_p (cond0, cond1)))
7300 /* If if_then_else_cond returned zero, then true/false are the
7301 same rtl. We must copy one of them to prevent invalid rtl
7304 true0 = copy_rtx (true0);
7305 else if (cond1 == 0)
7306 true1 = copy_rtx (true1);
7308 *ptrue = gen_binary (code, mode, true0, true1);
7309 *pfalse = gen_binary (code, mode, false0, false1);
7310 return cond0 ? cond0 : cond1;
7313 /* See if we have PLUS, IOR, XOR, MINUS or UMAX, where one of the
7314 operands is zero when the other is non-zero, and vice-versa,
7315 and STORE_FLAG_VALUE is 1 or -1. */
7317 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
7318 && (code == PLUS || code == IOR || code == XOR || code == MINUS
7320 && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT)
7322 rtx op0 = XEXP (XEXP (x, 0), 1);
7323 rtx op1 = XEXP (XEXP (x, 1), 1);
7325 cond0 = XEXP (XEXP (x, 0), 0);
7326 cond1 = XEXP (XEXP (x, 1), 0);
7328 if (GET_RTX_CLASS (GET_CODE (cond0)) == '<'
7329 && GET_RTX_CLASS (GET_CODE (cond1)) == '<'
7330 && ((GET_CODE (cond0) == combine_reversed_comparison_code (cond1)
7331 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0))
7332 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1)))
7333 || ((swap_condition (GET_CODE (cond0))
7334 == combine_reversed_comparison_code (cond1))
7335 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1))
7336 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0))))
7337 && ! side_effects_p (x))
7339 *ptrue = gen_binary (MULT, mode, op0, const_true_rtx);
7340 *pfalse = gen_binary (MULT, mode,
7342 ? simplify_gen_unary (NEG, mode, op1,
7350 /* Similarly for MULT, AND and UMIN, except that for these the result
7352 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
7353 && (code == MULT || code == AND || code == UMIN)
7354 && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT)
7356 cond0 = XEXP (XEXP (x, 0), 0);
7357 cond1 = XEXP (XEXP (x, 1), 0);
7359 if (GET_RTX_CLASS (GET_CODE (cond0)) == '<'
7360 && GET_RTX_CLASS (GET_CODE (cond1)) == '<'
7361 && ((GET_CODE (cond0) == combine_reversed_comparison_code (cond1)
7362 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0))
7363 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1)))
7364 || ((swap_condition (GET_CODE (cond0))
7365 == combine_reversed_comparison_code (cond1))
7366 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1))
7367 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0))))
7368 && ! side_effects_p (x))
7370 *ptrue = *pfalse = const0_rtx;
7376 else if (code == IF_THEN_ELSE)
7378 /* If we have IF_THEN_ELSE already, extract the condition and
7379 canonicalize it if it is NE or EQ. */
7380 cond0 = XEXP (x, 0);
7381 *ptrue = XEXP (x, 1), *pfalse = XEXP (x, 2);
7382 if (GET_CODE (cond0) == NE && XEXP (cond0, 1) == const0_rtx)
7383 return XEXP (cond0, 0);
7384 else if (GET_CODE (cond0) == EQ && XEXP (cond0, 1) == const0_rtx)
7386 *ptrue = XEXP (x, 2), *pfalse = XEXP (x, 1);
7387 return XEXP (cond0, 0);
7393 /* If X is a SUBREG, we can narrow both the true and false values
7394 if the inner expression, if there is a condition. */
7395 else if (code == SUBREG
7396 && 0 != (cond0 = if_then_else_cond (SUBREG_REG (x),
7399 *ptrue = simplify_gen_subreg (mode, true0,
7400 GET_MODE (SUBREG_REG (x)), SUBREG_BYTE (x));
7401 *pfalse = simplify_gen_subreg (mode, false0,
7402 GET_MODE (SUBREG_REG (x)), SUBREG_BYTE (x));
7407 /* If X is a constant, this isn't special and will cause confusions
7408 if we treat it as such. Likewise if it is equivalent to a constant. */
7409 else if (CONSTANT_P (x)
7410 || ((cond0 = get_last_value (x)) != 0 && CONSTANT_P (cond0)))
7413 /* If we're in BImode, canonicalize on 0 and STORE_FLAG_VALUE, as that
7414 will be least confusing to the rest of the compiler. */
7415 else if (mode == BImode)
7417 *ptrue = GEN_INT (STORE_FLAG_VALUE), *pfalse = const0_rtx;
7421 /* If X is known to be either 0 or -1, those are the true and
7422 false values when testing X. */
7423 else if (x == constm1_rtx || x == const0_rtx
7424 || (mode != VOIDmode
7425 && num_sign_bit_copies (x, mode) == GET_MODE_BITSIZE (mode)))
7427 *ptrue = constm1_rtx, *pfalse = const0_rtx;
7431 /* Likewise for 0 or a single bit. */
7432 else if (mode != VOIDmode
7433 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
7434 && exact_log2 (nz = nonzero_bits (x, mode)) >= 0)
7436 *ptrue = gen_int_mode (nz, mode), *pfalse = const0_rtx;
7440 /* Otherwise fail; show no condition with true and false values the same. */
7441 *ptrue = *pfalse = x;
7445 /* Return the value of expression X given the fact that condition COND
7446 is known to be true when applied to REG as its first operand and VAL
7447 as its second. X is known to not be shared and so can be modified in
7450 We only handle the simplest cases, and specifically those cases that
7451 arise with IF_THEN_ELSE expressions. */
7454 known_cond (x, cond, reg, val)
7459 enum rtx_code code = GET_CODE (x);
7464 if (side_effects_p (x))
7467 /* If either operand of the condition is a floating point value,
7468 then we have to avoid collapsing an EQ comparison. */
7470 && rtx_equal_p (x, reg)
7471 && ! FLOAT_MODE_P (GET_MODE (x))
7472 && ! FLOAT_MODE_P (GET_MODE (val)))
7475 if (cond == UNEQ && rtx_equal_p (x, reg))
7478 /* If X is (abs REG) and we know something about REG's relationship
7479 with zero, we may be able to simplify this. */
7481 if (code == ABS && rtx_equal_p (XEXP (x, 0), reg) && val == const0_rtx)
7484 case GE: case GT: case EQ:
7487 return simplify_gen_unary (NEG, GET_MODE (XEXP (x, 0)),
7489 GET_MODE (XEXP (x, 0)));
7494 /* The only other cases we handle are MIN, MAX, and comparisons if the
7495 operands are the same as REG and VAL. */
7497 else if (GET_RTX_CLASS (code) == '<' || GET_RTX_CLASS (code) == 'c')
7499 if (rtx_equal_p (XEXP (x, 0), val))
7500 cond = swap_condition (cond), temp = val, val = reg, reg = temp;
7502 if (rtx_equal_p (XEXP (x, 0), reg) && rtx_equal_p (XEXP (x, 1), val))
7504 if (GET_RTX_CLASS (code) == '<')
7506 if (comparison_dominates_p (cond, code))
7507 return const_true_rtx;
7509 code = combine_reversed_comparison_code (x);
7511 && comparison_dominates_p (cond, code))
7516 else if (code == SMAX || code == SMIN
7517 || code == UMIN || code == UMAX)
7519 int unsignedp = (code == UMIN || code == UMAX);
7521 /* Do not reverse the condition when it is NE or EQ.
7522 This is because we cannot conclude anything about
7523 the value of 'SMAX (x, y)' when x is not equal to y,
7524 but we can when x equals y. */
7525 if ((code == SMAX || code == UMAX)
7526 && ! (cond == EQ || cond == NE))
7527 cond = reverse_condition (cond);
7532 return unsignedp ? x : XEXP (x, 1);
7534 return unsignedp ? x : XEXP (x, 0);
7536 return unsignedp ? XEXP (x, 1) : x;
7538 return unsignedp ? XEXP (x, 0) : x;
7545 else if (code == SUBREG)
7547 enum machine_mode inner_mode = GET_MODE (SUBREG_REG (x));
7548 rtx new, r = known_cond (SUBREG_REG (x), cond, reg, val);
7550 if (SUBREG_REG (x) != r)
7552 /* We must simplify subreg here, before we lose track of the
7553 original inner_mode. */
7554 new = simplify_subreg (GET_MODE (x), r,
7555 inner_mode, SUBREG_BYTE (x));
7559 SUBST (SUBREG_REG (x), r);
7564 /* We don't have to handle SIGN_EXTEND here, because even in the
7565 case of replacing something with a modeless CONST_INT, a
7566 CONST_INT is already (supposed to be) a valid sign extension for
7567 its narrower mode, which implies it's already properly
7568 sign-extended for the wider mode. Now, for ZERO_EXTEND, the
7569 story is different. */
7570 else if (code == ZERO_EXTEND)
7572 enum machine_mode inner_mode = GET_MODE (XEXP (x, 0));
7573 rtx new, r = known_cond (XEXP (x, 0), cond, reg, val);
7575 if (XEXP (x, 0) != r)
7577 /* We must simplify the zero_extend here, before we lose
7578 track of the original inner_mode. */
7579 new = simplify_unary_operation (ZERO_EXTEND, GET_MODE (x),
7584 SUBST (XEXP (x, 0), r);
7590 fmt = GET_RTX_FORMAT (code);
7591 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
7594 SUBST (XEXP (x, i), known_cond (XEXP (x, i), cond, reg, val));
7595 else if (fmt[i] == 'E')
7596 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
7597 SUBST (XVECEXP (x, i, j), known_cond (XVECEXP (x, i, j),
7604 /* See if X and Y are equal for the purposes of seeing if we can rewrite an
7605 assignment as a field assignment. */
7608 rtx_equal_for_field_assignment_p (x, y)
7612 if (x == y || rtx_equal_p (x, y))
7615 if (x == 0 || y == 0 || GET_MODE (x) != GET_MODE (y))
7618 /* Check for a paradoxical SUBREG of a MEM compared with the MEM.
7619 Note that all SUBREGs of MEM are paradoxical; otherwise they
7620 would have been rewritten. */
7621 if (GET_CODE (x) == MEM && GET_CODE (y) == SUBREG
7622 && GET_CODE (SUBREG_REG (y)) == MEM
7623 && rtx_equal_p (SUBREG_REG (y),
7624 gen_lowpart_for_combine (GET_MODE (SUBREG_REG (y)), x)))
7627 if (GET_CODE (y) == MEM && GET_CODE (x) == SUBREG
7628 && GET_CODE (SUBREG_REG (x)) == MEM
7629 && rtx_equal_p (SUBREG_REG (x),
7630 gen_lowpart_for_combine (GET_MODE (SUBREG_REG (x)), y)))
7633 /* We used to see if get_last_value of X and Y were the same but that's
7634 not correct. In one direction, we'll cause the assignment to have
7635 the wrong destination and in the case, we'll import a register into this
7636 insn that might have already have been dead. So fail if none of the
7637 above cases are true. */
7641 /* See if X, a SET operation, can be rewritten as a bit-field assignment.
7642 Return that assignment if so.
7644 We only handle the most common cases. */
7647 make_field_assignment (x)
7650 rtx dest = SET_DEST (x);
7651 rtx src = SET_SRC (x);
7656 unsigned HOST_WIDE_INT len;
7658 enum machine_mode mode;
7660 /* If SRC was (and (not (ashift (const_int 1) POS)) DEST), this is
7661 a clear of a one-bit field. We will have changed it to
7662 (and (rotate (const_int -2) POS) DEST), so check for that. Also check
7665 if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == ROTATE
7666 && GET_CODE (XEXP (XEXP (src, 0), 0)) == CONST_INT
7667 && INTVAL (XEXP (XEXP (src, 0), 0)) == -2
7668 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
7670 assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1),
7673 return gen_rtx_SET (VOIDmode, assign, const0_rtx);
7677 else if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == SUBREG
7678 && subreg_lowpart_p (XEXP (src, 0))
7679 && (GET_MODE_SIZE (GET_MODE (XEXP (src, 0)))
7680 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (src, 0)))))
7681 && GET_CODE (SUBREG_REG (XEXP (src, 0))) == ROTATE
7682 && INTVAL (XEXP (SUBREG_REG (XEXP (src, 0)), 0)) == -2
7683 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
7685 assign = make_extraction (VOIDmode, dest, 0,
7686 XEXP (SUBREG_REG (XEXP (src, 0)), 1),
7689 return gen_rtx_SET (VOIDmode, assign, const0_rtx);
7693 /* If SRC is (ior (ashift (const_int 1) POS) DEST), this is a set of a
7695 else if (GET_CODE (src) == IOR && GET_CODE (XEXP (src, 0)) == ASHIFT
7696 && XEXP (XEXP (src, 0), 0) == const1_rtx
7697 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
7699 assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1),
7702 return gen_rtx_SET (VOIDmode, assign, const1_rtx);
7706 /* The other case we handle is assignments into a constant-position
7707 field. They look like (ior/xor (and DEST C1) OTHER). If C1 represents
7708 a mask that has all one bits except for a group of zero bits and
7709 OTHER is known to have zeros where C1 has ones, this is such an
7710 assignment. Compute the position and length from C1. Shift OTHER
7711 to the appropriate position, force it to the required mode, and
7712 make the extraction. Check for the AND in both operands. */
7714 if (GET_CODE (src) != IOR && GET_CODE (src) != XOR)
7717 rhs = expand_compound_operation (XEXP (src, 0));
7718 lhs = expand_compound_operation (XEXP (src, 1));
7720 if (GET_CODE (rhs) == AND
7721 && GET_CODE (XEXP (rhs, 1)) == CONST_INT
7722 && rtx_equal_for_field_assignment_p (XEXP (rhs, 0), dest))
7723 c1 = INTVAL (XEXP (rhs, 1)), other = lhs;
7724 else if (GET_CODE (lhs) == AND
7725 && GET_CODE (XEXP (lhs, 1)) == CONST_INT
7726 && rtx_equal_for_field_assignment_p (XEXP (lhs, 0), dest))
7727 c1 = INTVAL (XEXP (lhs, 1)), other = rhs;
7731 pos = get_pos_from_mask ((~c1) & GET_MODE_MASK (GET_MODE (dest)), &len);
7732 if (pos < 0 || pos + len > GET_MODE_BITSIZE (GET_MODE (dest))
7733 || GET_MODE_BITSIZE (GET_MODE (dest)) > HOST_BITS_PER_WIDE_INT
7734 || (c1 & nonzero_bits (other, GET_MODE (dest))) != 0)
7737 assign = make_extraction (VOIDmode, dest, pos, NULL_RTX, len, 1, 1, 0);
7741 /* The mode to use for the source is the mode of the assignment, or of
7742 what is inside a possible STRICT_LOW_PART. */
7743 mode = (GET_CODE (assign) == STRICT_LOW_PART
7744 ? GET_MODE (XEXP (assign, 0)) : GET_MODE (assign));
7746 /* Shift OTHER right POS places and make it the source, restricting it
7747 to the proper length and mode. */
7749 src = force_to_mode (simplify_shift_const (NULL_RTX, LSHIFTRT,
7750 GET_MODE (src), other, pos),
7752 GET_MODE_BITSIZE (mode) >= HOST_BITS_PER_WIDE_INT
7753 ? ~(unsigned HOST_WIDE_INT) 0
7754 : ((unsigned HOST_WIDE_INT) 1 << len) - 1,
7757 return gen_rtx_SET (VOIDmode, assign, src);
7760 /* See if X is of the form (+ (* a c) (* b c)) and convert to (* (+ a b) c)
7764 apply_distributive_law (x)
7767 enum rtx_code code = GET_CODE (x);
7768 rtx lhs, rhs, other;
7770 enum rtx_code inner_code;
7772 /* Distributivity is not true for floating point.
7773 It can change the value. So don't do it.
7774 -- rms and moshier@world.std.com. */
7775 if (FLOAT_MODE_P (GET_MODE (x)))
7778 /* The outer operation can only be one of the following: */
7779 if (code != IOR && code != AND && code != XOR
7780 && code != PLUS && code != MINUS)
7783 lhs = XEXP (x, 0), rhs = XEXP (x, 1);
7785 /* If either operand is a primitive we can't do anything, so get out
7787 if (GET_RTX_CLASS (GET_CODE (lhs)) == 'o'
7788 || GET_RTX_CLASS (GET_CODE (rhs)) == 'o')
7791 lhs = expand_compound_operation (lhs);
7792 rhs = expand_compound_operation (rhs);
7793 inner_code = GET_CODE (lhs);
7794 if (inner_code != GET_CODE (rhs))
7797 /* See if the inner and outer operations distribute. */
7804 /* These all distribute except over PLUS. */
7805 if (code == PLUS || code == MINUS)
7810 if (code != PLUS && code != MINUS)
7815 /* This is also a multiply, so it distributes over everything. */
7819 /* Non-paradoxical SUBREGs distributes over all operations, provided
7820 the inner modes and byte offsets are the same, this is an extraction
7821 of a low-order part, we don't convert an fp operation to int or
7822 vice versa, and we would not be converting a single-word
7823 operation into a multi-word operation. The latter test is not
7824 required, but it prevents generating unneeded multi-word operations.
7825 Some of the previous tests are redundant given the latter test, but
7826 are retained because they are required for correctness.
7828 We produce the result slightly differently in this case. */
7830 if (GET_MODE (SUBREG_REG (lhs)) != GET_MODE (SUBREG_REG (rhs))
7831 || SUBREG_BYTE (lhs) != SUBREG_BYTE (rhs)
7832 || ! subreg_lowpart_p (lhs)
7833 || (GET_MODE_CLASS (GET_MODE (lhs))
7834 != GET_MODE_CLASS (GET_MODE (SUBREG_REG (lhs))))
7835 || (GET_MODE_SIZE (GET_MODE (lhs))
7836 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs))))
7837 || GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs))) > UNITS_PER_WORD)
7840 tem = gen_binary (code, GET_MODE (SUBREG_REG (lhs)),
7841 SUBREG_REG (lhs), SUBREG_REG (rhs));
7842 return gen_lowpart_for_combine (GET_MODE (x), tem);
7848 /* Set LHS and RHS to the inner operands (A and B in the example
7849 above) and set OTHER to the common operand (C in the example).
7850 These is only one way to do this unless the inner operation is
7852 if (GET_RTX_CLASS (inner_code) == 'c'
7853 && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 0)))
7854 other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 1);
7855 else if (GET_RTX_CLASS (inner_code) == 'c'
7856 && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 1)))
7857 other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 0);
7858 else if (GET_RTX_CLASS (inner_code) == 'c'
7859 && rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 0)))
7860 other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 1);
7861 else if (rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 1)))
7862 other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 0);
7866 /* Form the new inner operation, seeing if it simplifies first. */
7867 tem = gen_binary (code, GET_MODE (x), lhs, rhs);
7869 /* There is one exception to the general way of distributing:
7870 (a ^ b) | (a ^ c) -> (~a) & (b ^ c) */
7871 if (code == XOR && inner_code == IOR)
7874 other = simplify_gen_unary (NOT, GET_MODE (x), other, GET_MODE (x));
7877 /* We may be able to continuing distributing the result, so call
7878 ourselves recursively on the inner operation before forming the
7879 outer operation, which we return. */
7880 return gen_binary (inner_code, GET_MODE (x),
7881 apply_distributive_law (tem), other);
7884 /* We have X, a logical `and' of VAROP with the constant CONSTOP, to be done
7887 Return an equivalent form, if different from X. Otherwise, return X. If
7888 X is zero, we are to always construct the equivalent form. */
7891 simplify_and_const_int (x, mode, varop, constop)
7893 enum machine_mode mode;
7895 unsigned HOST_WIDE_INT constop;
7897 unsigned HOST_WIDE_INT nonzero;
7900 /* Simplify VAROP knowing that we will be only looking at some of the
7903 Note by passing in CONSTOP, we guarantee that the bits not set in
7904 CONSTOP are not significant and will never be examined. We must
7905 ensure that is the case by explicitly masking out those bits
7906 before returning. */
7907 varop = force_to_mode (varop, mode, constop, NULL_RTX, 0);
7909 /* If VAROP is a CLOBBER, we will fail so return it. */
7910 if (GET_CODE (varop) == CLOBBER)
7913 /* If VAROP is a CONST_INT, then we need to apply the mask in CONSTOP
7914 to VAROP and return the new constant. */
7915 if (GET_CODE (varop) == CONST_INT)
7916 return GEN_INT (trunc_int_for_mode (INTVAL (varop) & constop, mode));
7918 /* See what bits may be nonzero in VAROP. Unlike the general case of
7919 a call to nonzero_bits, here we don't care about bits outside
7922 nonzero = nonzero_bits (varop, mode) & GET_MODE_MASK (mode);
7924 /* Turn off all bits in the constant that are known to already be zero.
7925 Thus, if the AND isn't needed at all, we will have CONSTOP == NONZERO_BITS
7926 which is tested below. */
7930 /* If we don't have any bits left, return zero. */
7934 /* If VAROP is a NEG of something known to be zero or 1 and CONSTOP is
7935 a power of two, we can replace this with an ASHIFT. */
7936 if (GET_CODE (varop) == NEG && nonzero_bits (XEXP (varop, 0), mode) == 1
7937 && (i = exact_log2 (constop)) >= 0)
7938 return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (varop, 0), i);
7940 /* If VAROP is an IOR or XOR, apply the AND to both branches of the IOR
7941 or XOR, then try to apply the distributive law. This may eliminate
7942 operations if either branch can be simplified because of the AND.
7943 It may also make some cases more complex, but those cases probably
7944 won't match a pattern either with or without this. */
7946 if (GET_CODE (varop) == IOR || GET_CODE (varop) == XOR)
7948 gen_lowpart_for_combine
7950 apply_distributive_law
7951 (gen_binary (GET_CODE (varop), GET_MODE (varop),
7952 simplify_and_const_int (NULL_RTX, GET_MODE (varop),
7953 XEXP (varop, 0), constop),
7954 simplify_and_const_int (NULL_RTX, GET_MODE (varop),
7955 XEXP (varop, 1), constop))));
7957 /* If VAROP is PLUS, and the constant is a mask of low bite, distribute
7958 the AND and see if one of the operands simplifies to zero. If so, we
7959 may eliminate it. */
7961 if (GET_CODE (varop) == PLUS
7962 && exact_log2 (constop + 1) >= 0)
7966 o0 = simplify_and_const_int (NULL_RTX, mode, XEXP (varop, 0), constop);
7967 o1 = simplify_and_const_int (NULL_RTX, mode, XEXP (varop, 1), constop);
7968 if (o0 == const0_rtx)
7970 if (o1 == const0_rtx)
7974 /* Get VAROP in MODE. Try to get a SUBREG if not. Don't make a new SUBREG
7975 if we already had one (just check for the simplest cases). */
7976 if (x && GET_CODE (XEXP (x, 0)) == SUBREG
7977 && GET_MODE (XEXP (x, 0)) == mode
7978 && SUBREG_REG (XEXP (x, 0)) == varop)
7979 varop = XEXP (x, 0);
7981 varop = gen_lowpart_for_combine (mode, varop);
7983 /* If we can't make the SUBREG, try to return what we were given. */
7984 if (GET_CODE (varop) == CLOBBER)
7985 return x ? x : varop;
7987 /* If we are only masking insignificant bits, return VAROP. */
7988 if (constop == nonzero)
7992 /* Otherwise, return an AND. */
7993 constop = trunc_int_for_mode (constop, mode);
7994 /* See how much, if any, of X we can use. */
7995 if (x == 0 || GET_CODE (x) != AND || GET_MODE (x) != mode)
7996 x = gen_binary (AND, mode, varop, GEN_INT (constop));
8000 if (GET_CODE (XEXP (x, 1)) != CONST_INT
8001 || (unsigned HOST_WIDE_INT) INTVAL (XEXP (x, 1)) != constop)
8002 SUBST (XEXP (x, 1), GEN_INT (constop));
8004 SUBST (XEXP (x, 0), varop);
8011 /* We let num_sign_bit_copies recur into nonzero_bits as that is useful.
8012 We don't let nonzero_bits recur into num_sign_bit_copies, because that
8013 is less useful. We can't allow both, because that results in exponential
8014 run time recursion. There is a nullstone testcase that triggered
8015 this. This macro avoids accidental uses of num_sign_bit_copies. */
8016 #define num_sign_bit_copies()
8018 /* Given an expression, X, compute which bits in X can be non-zero.
8019 We don't care about bits outside of those defined in MODE.
8021 For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is
8022 a shift, AND, or zero_extract, we can do better. */
8024 static unsigned HOST_WIDE_INT
8025 nonzero_bits (x, mode)
8027 enum machine_mode mode;
8029 unsigned HOST_WIDE_INT nonzero = GET_MODE_MASK (mode);
8030 unsigned HOST_WIDE_INT inner_nz;
8032 unsigned int mode_width = GET_MODE_BITSIZE (mode);
8035 /* For floating-point values, assume all bits are needed. */
8036 if (FLOAT_MODE_P (GET_MODE (x)) || FLOAT_MODE_P (mode))
8039 /* If X is wider than MODE, use its mode instead. */
8040 if (GET_MODE_BITSIZE (GET_MODE (x)) > mode_width)
8042 mode = GET_MODE (x);
8043 nonzero = GET_MODE_MASK (mode);
8044 mode_width = GET_MODE_BITSIZE (mode);
8047 if (mode_width > HOST_BITS_PER_WIDE_INT)
8048 /* Our only callers in this case look for single bit values. So
8049 just return the mode mask. Those tests will then be false. */
8052 #ifndef WORD_REGISTER_OPERATIONS
8053 /* If MODE is wider than X, but both are a single word for both the host
8054 and target machines, we can compute this from which bits of the
8055 object might be nonzero in its own mode, taking into account the fact
8056 that on many CISC machines, accessing an object in a wider mode
8057 causes the high-order bits to become undefined. So they are
8058 not known to be zero. */
8060 if (GET_MODE (x) != VOIDmode && GET_MODE (x) != mode
8061 && GET_MODE_BITSIZE (GET_MODE (x)) <= BITS_PER_WORD
8062 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
8063 && GET_MODE_BITSIZE (mode) > GET_MODE_BITSIZE (GET_MODE (x)))
8065 nonzero &= nonzero_bits (x, GET_MODE (x));
8066 nonzero |= GET_MODE_MASK (mode) & ~GET_MODE_MASK (GET_MODE (x));
8071 code = GET_CODE (x);
8075 #if defined(POINTERS_EXTEND_UNSIGNED) && !defined(HAVE_ptr_extend)
8076 /* If pointers extend unsigned and this is a pointer in Pmode, say that
8077 all the bits above ptr_mode are known to be zero. */
8078 if (POINTERS_EXTEND_UNSIGNED && GET_MODE (x) == Pmode
8080 nonzero &= GET_MODE_MASK (ptr_mode);
8083 /* Include declared information about alignment of pointers. */
8084 /* ??? We don't properly preserve REG_POINTER changes across
8085 pointer-to-integer casts, so we can't trust it except for
8086 things that we know must be pointers. See execute/960116-1.c. */
8087 if ((x == stack_pointer_rtx
8088 || x == frame_pointer_rtx
8089 || x == arg_pointer_rtx)
8090 && REGNO_POINTER_ALIGN (REGNO (x)))
8092 unsigned HOST_WIDE_INT alignment
8093 = REGNO_POINTER_ALIGN (REGNO (x)) / BITS_PER_UNIT;
8095 #ifdef PUSH_ROUNDING
8096 /* If PUSH_ROUNDING is defined, it is possible for the
8097 stack to be momentarily aligned only to that amount,
8098 so we pick the least alignment. */
8099 if (x == stack_pointer_rtx && PUSH_ARGS)
8100 alignment = MIN (PUSH_ROUNDING (1), alignment);
8103 nonzero &= ~(alignment - 1);
8106 /* If X is a register whose nonzero bits value is current, use it.
8107 Otherwise, if X is a register whose value we can find, use that
8108 value. Otherwise, use the previously-computed global nonzero bits
8109 for this register. */
8111 if (reg_last_set_value[REGNO (x)] != 0
8112 && (reg_last_set_mode[REGNO (x)] == mode
8113 || (GET_MODE_CLASS (reg_last_set_mode[REGNO (x)]) == MODE_INT
8114 && GET_MODE_CLASS (mode) == MODE_INT))
8115 && (reg_last_set_label[REGNO (x)] == label_tick
8116 || (REGNO (x) >= FIRST_PSEUDO_REGISTER
8117 && REG_N_SETS (REGNO (x)) == 1
8118 && ! REGNO_REG_SET_P (ENTRY_BLOCK_PTR->next_bb->global_live_at_start,
8120 && INSN_CUID (reg_last_set[REGNO (x)]) < subst_low_cuid)
8121 return reg_last_set_nonzero_bits[REGNO (x)] & nonzero;
8123 tem = get_last_value (x);
8127 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
8128 /* If X is narrower than MODE and TEM is a non-negative
8129 constant that would appear negative in the mode of X,
8130 sign-extend it for use in reg_nonzero_bits because some
8131 machines (maybe most) will actually do the sign-extension
8132 and this is the conservative approach.
8134 ??? For 2.5, try to tighten up the MD files in this regard
8135 instead of this kludge. */
8137 if (GET_MODE_BITSIZE (GET_MODE (x)) < mode_width
8138 && GET_CODE (tem) == CONST_INT
8140 && 0 != (INTVAL (tem)
8141 & ((HOST_WIDE_INT) 1
8142 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
8143 tem = GEN_INT (INTVAL (tem)
8144 | ((HOST_WIDE_INT) (-1)
8145 << GET_MODE_BITSIZE (GET_MODE (x))));
8147 return nonzero_bits (tem, mode) & nonzero;
8149 else if (nonzero_sign_valid && reg_nonzero_bits[REGNO (x)])
8151 unsigned HOST_WIDE_INT mask = reg_nonzero_bits[REGNO (x)];
8153 if (GET_MODE_BITSIZE (GET_MODE (x)) < mode_width)
8154 /* We don't know anything about the upper bits. */
8155 mask |= GET_MODE_MASK (mode) ^ GET_MODE_MASK (GET_MODE (x));
8156 return nonzero & mask;
8162 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
8163 /* If X is negative in MODE, sign-extend the value. */
8164 if (INTVAL (x) > 0 && mode_width < BITS_PER_WORD
8165 && 0 != (INTVAL (x) & ((HOST_WIDE_INT) 1 << (mode_width - 1))))
8166 return (INTVAL (x) | ((HOST_WIDE_INT) (-1) << mode_width));
8172 #ifdef LOAD_EXTEND_OP
8173 /* In many, if not most, RISC machines, reading a byte from memory
8174 zeros the rest of the register. Noticing that fact saves a lot
8175 of extra zero-extends. */
8176 if (LOAD_EXTEND_OP (GET_MODE (x)) == ZERO_EXTEND)
8177 nonzero &= GET_MODE_MASK (GET_MODE (x));
8182 case UNEQ: case LTGT:
8183 case GT: case GTU: case UNGT:
8184 case LT: case LTU: case UNLT:
8185 case GE: case GEU: case UNGE:
8186 case LE: case LEU: case UNLE:
8187 case UNORDERED: case ORDERED:
8189 /* If this produces an integer result, we know which bits are set.
8190 Code here used to clear bits outside the mode of X, but that is
8193 if (GET_MODE_CLASS (mode) == MODE_INT
8194 && mode_width <= HOST_BITS_PER_WIDE_INT)
8195 nonzero = STORE_FLAG_VALUE;
8200 /* Disabled to avoid exponential mutual recursion between nonzero_bits
8201 and num_sign_bit_copies. */
8202 if (num_sign_bit_copies (XEXP (x, 0), GET_MODE (x))
8203 == GET_MODE_BITSIZE (GET_MODE (x)))
8207 if (GET_MODE_SIZE (GET_MODE (x)) < mode_width)
8208 nonzero |= (GET_MODE_MASK (mode) & ~GET_MODE_MASK (GET_MODE (x)));
8213 /* Disabled to avoid exponential mutual recursion between nonzero_bits
8214 and num_sign_bit_copies. */
8215 if (num_sign_bit_copies (XEXP (x, 0), GET_MODE (x))
8216 == GET_MODE_BITSIZE (GET_MODE (x)))
8222 nonzero &= (nonzero_bits (XEXP (x, 0), mode) & GET_MODE_MASK (mode));
8226 nonzero &= nonzero_bits (XEXP (x, 0), mode);
8227 if (GET_MODE (XEXP (x, 0)) != VOIDmode)
8228 nonzero &= GET_MODE_MASK (GET_MODE (XEXP (x, 0)));
8232 /* If the sign bit is known clear, this is the same as ZERO_EXTEND.
8233 Otherwise, show all the bits in the outer mode but not the inner
8235 inner_nz = nonzero_bits (XEXP (x, 0), mode);
8236 if (GET_MODE (XEXP (x, 0)) != VOIDmode)
8238 inner_nz &= GET_MODE_MASK (GET_MODE (XEXP (x, 0)));
8240 & (((HOST_WIDE_INT) 1
8241 << (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - 1))))
8242 inner_nz |= (GET_MODE_MASK (mode)
8243 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0))));
8246 nonzero &= inner_nz;
8250 nonzero &= (nonzero_bits (XEXP (x, 0), mode)
8251 & nonzero_bits (XEXP (x, 1), mode));
8255 case UMIN: case UMAX: case SMIN: case SMAX:
8257 unsigned HOST_WIDE_INT nonzero0 = nonzero_bits (XEXP (x, 0), mode);
8259 /* Don't call nonzero_bits for the second time if it cannot change
8261 if ((nonzero & nonzero0) != nonzero)
8262 nonzero &= (nonzero0 | nonzero_bits (XEXP (x, 1), mode));
8266 case PLUS: case MINUS:
8268 case DIV: case UDIV:
8269 case MOD: case UMOD:
8270 /* We can apply the rules of arithmetic to compute the number of
8271 high- and low-order zero bits of these operations. We start by
8272 computing the width (position of the highest-order non-zero bit)
8273 and the number of low-order zero bits for each value. */
8275 unsigned HOST_WIDE_INT nz0 = nonzero_bits (XEXP (x, 0), mode);
8276 unsigned HOST_WIDE_INT nz1 = nonzero_bits (XEXP (x, 1), mode);
8277 int width0 = floor_log2 (nz0) + 1;
8278 int width1 = floor_log2 (nz1) + 1;
8279 int low0 = floor_log2 (nz0 & -nz0);
8280 int low1 = floor_log2 (nz1 & -nz1);
8281 HOST_WIDE_INT op0_maybe_minusp
8282 = (nz0 & ((HOST_WIDE_INT) 1 << (mode_width - 1)));
8283 HOST_WIDE_INT op1_maybe_minusp
8284 = (nz1 & ((HOST_WIDE_INT) 1 << (mode_width - 1)));
8285 unsigned int result_width = mode_width;
8291 result_width = MAX (width0, width1) + 1;
8292 result_low = MIN (low0, low1);
8295 result_low = MIN (low0, low1);
8298 result_width = width0 + width1;
8299 result_low = low0 + low1;
8304 if (! op0_maybe_minusp && ! op1_maybe_minusp)
8305 result_width = width0;
8310 result_width = width0;
8315 if (! op0_maybe_minusp && ! op1_maybe_minusp)
8316 result_width = MIN (width0, width1);
8317 result_low = MIN (low0, low1);
8322 result_width = MIN (width0, width1);
8323 result_low = MIN (low0, low1);
8329 if (result_width < mode_width)
8330 nonzero &= ((HOST_WIDE_INT) 1 << result_width) - 1;
8333 nonzero &= ~(((HOST_WIDE_INT) 1 << result_low) - 1);
8335 #ifdef POINTERS_EXTEND_UNSIGNED
8336 /* If pointers extend unsigned and this is an addition or subtraction
8337 to a pointer in Pmode, all the bits above ptr_mode are known to be
8339 if (POINTERS_EXTEND_UNSIGNED > 0 && GET_MODE (x) == Pmode
8340 && (code == PLUS || code == MINUS)
8341 && GET_CODE (XEXP (x, 0)) == REG && REG_POINTER (XEXP (x, 0)))
8342 nonzero &= GET_MODE_MASK (ptr_mode);
8348 if (GET_CODE (XEXP (x, 1)) == CONST_INT
8349 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT)
8350 nonzero &= ((HOST_WIDE_INT) 1 << INTVAL (XEXP (x, 1))) - 1;
8354 /* If this is a SUBREG formed for a promoted variable that has
8355 been zero-extended, we know that at least the high-order bits
8356 are zero, though others might be too. */
8358 if (SUBREG_PROMOTED_VAR_P (x) && SUBREG_PROMOTED_UNSIGNED_P (x) > 0)
8359 nonzero = (GET_MODE_MASK (GET_MODE (x))
8360 & nonzero_bits (SUBREG_REG (x), GET_MODE (x)));
8362 /* If the inner mode is a single word for both the host and target
8363 machines, we can compute this from which bits of the inner
8364 object might be nonzero. */
8365 if (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x))) <= BITS_PER_WORD
8366 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x)))
8367 <= HOST_BITS_PER_WIDE_INT))
8369 nonzero &= nonzero_bits (SUBREG_REG (x), mode);
8371 #if defined (WORD_REGISTER_OPERATIONS) && defined (LOAD_EXTEND_OP)
8372 /* If this is a typical RISC machine, we only have to worry
8373 about the way loads are extended. */
8374 if ((LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (x))) == SIGN_EXTEND
8376 & (((unsigned HOST_WIDE_INT) 1
8377 << (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x))) - 1))))
8379 : LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (x))) != ZERO_EXTEND)
8380 || GET_CODE (SUBREG_REG (x)) != MEM)
8383 /* On many CISC machines, accessing an object in a wider mode
8384 causes the high-order bits to become undefined. So they are
8385 not known to be zero. */
8386 if (GET_MODE_SIZE (GET_MODE (x))
8387 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
8388 nonzero |= (GET_MODE_MASK (GET_MODE (x))
8389 & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (x))));
8398 /* The nonzero bits are in two classes: any bits within MODE
8399 that aren't in GET_MODE (x) are always significant. The rest of the
8400 nonzero bits are those that are significant in the operand of
8401 the shift when shifted the appropriate number of bits. This
8402 shows that high-order bits are cleared by the right shift and
8403 low-order bits by left shifts. */
8404 if (GET_CODE (XEXP (x, 1)) == CONST_INT
8405 && INTVAL (XEXP (x, 1)) >= 0
8406 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT)
8408 enum machine_mode inner_mode = GET_MODE (x);
8409 unsigned int width = GET_MODE_BITSIZE (inner_mode);
8410 int count = INTVAL (XEXP (x, 1));
8411 unsigned HOST_WIDE_INT mode_mask = GET_MODE_MASK (inner_mode);
8412 unsigned HOST_WIDE_INT op_nonzero = nonzero_bits (XEXP (x, 0), mode);
8413 unsigned HOST_WIDE_INT inner = op_nonzero & mode_mask;
8414 unsigned HOST_WIDE_INT outer = 0;
8416 if (mode_width > width)
8417 outer = (op_nonzero & nonzero & ~mode_mask);
8419 if (code == LSHIFTRT)
8421 else if (code == ASHIFTRT)
8425 /* If the sign bit may have been nonzero before the shift, we
8426 need to mark all the places it could have been copied to
8427 by the shift as possibly nonzero. */
8428 if (inner & ((HOST_WIDE_INT) 1 << (width - 1 - count)))
8429 inner |= (((HOST_WIDE_INT) 1 << count) - 1) << (width - count);
8431 else if (code == ASHIFT)
8434 inner = ((inner << (count % width)
8435 | (inner >> (width - (count % width)))) & mode_mask);
8437 nonzero &= (outer | inner);
8442 /* This is at most the number of bits in the mode. */
8443 nonzero = ((HOST_WIDE_INT) 1 << (floor_log2 (mode_width) + 1)) - 1;
8447 nonzero &= (nonzero_bits (XEXP (x, 1), mode)
8448 | nonzero_bits (XEXP (x, 2), mode));
8458 /* See the macro definition above. */
8459 #undef num_sign_bit_copies
8461 /* Return the number of bits at the high-order end of X that are known to
8462 be equal to the sign bit. X will be used in mode MODE; if MODE is
8463 VOIDmode, X will be used in its own mode. The returned value will always
8464 be between 1 and the number of bits in MODE. */
8467 num_sign_bit_copies (x, mode)
8469 enum machine_mode mode;
8471 enum rtx_code code = GET_CODE (x);
8472 unsigned int bitwidth;
8473 int num0, num1, result;
8474 unsigned HOST_WIDE_INT nonzero;
8477 /* If we weren't given a mode, use the mode of X. If the mode is still
8478 VOIDmode, we don't know anything. Likewise if one of the modes is
8481 if (mode == VOIDmode)
8482 mode = GET_MODE (x);
8484 if (mode == VOIDmode || FLOAT_MODE_P (mode) || FLOAT_MODE_P (GET_MODE (x)))
8487 bitwidth = GET_MODE_BITSIZE (mode);
8489 /* For a smaller object, just ignore the high bits. */
8490 if (bitwidth < GET_MODE_BITSIZE (GET_MODE (x)))
8492 num0 = num_sign_bit_copies (x, GET_MODE (x));
8494 num0 - (int) (GET_MODE_BITSIZE (GET_MODE (x)) - bitwidth));
8497 if (GET_MODE (x) != VOIDmode && bitwidth > GET_MODE_BITSIZE (GET_MODE (x)))
8499 #ifndef WORD_REGISTER_OPERATIONS
8500 /* If this machine does not do all register operations on the entire
8501 register and MODE is wider than the mode of X, we can say nothing
8502 at all about the high-order bits. */
8505 /* Likewise on machines that do, if the mode of the object is smaller
8506 than a word and loads of that size don't sign extend, we can say
8507 nothing about the high order bits. */
8508 if (GET_MODE_BITSIZE (GET_MODE (x)) < BITS_PER_WORD
8509 #ifdef LOAD_EXTEND_OP
8510 && LOAD_EXTEND_OP (GET_MODE (x)) != SIGN_EXTEND
8521 #if defined(POINTERS_EXTEND_UNSIGNED) && !defined(HAVE_ptr_extend)
8522 /* If pointers extend signed and this is a pointer in Pmode, say that
8523 all the bits above ptr_mode are known to be sign bit copies. */
8524 if (! POINTERS_EXTEND_UNSIGNED && GET_MODE (x) == Pmode && mode == Pmode
8526 return GET_MODE_BITSIZE (Pmode) - GET_MODE_BITSIZE (ptr_mode) + 1;
8529 if (reg_last_set_value[REGNO (x)] != 0
8530 && reg_last_set_mode[REGNO (x)] == mode
8531 && (reg_last_set_label[REGNO (x)] == label_tick
8532 || (REGNO (x) >= FIRST_PSEUDO_REGISTER
8533 && REG_N_SETS (REGNO (x)) == 1
8534 && ! REGNO_REG_SET_P (ENTRY_BLOCK_PTR->next_bb->global_live_at_start,
8536 && INSN_CUID (reg_last_set[REGNO (x)]) < subst_low_cuid)
8537 return reg_last_set_sign_bit_copies[REGNO (x)];
8539 tem = get_last_value (x);
8541 return num_sign_bit_copies (tem, mode);
8543 if (nonzero_sign_valid && reg_sign_bit_copies[REGNO (x)] != 0
8544 && GET_MODE_BITSIZE (GET_MODE (x)) == bitwidth)
8545 return reg_sign_bit_copies[REGNO (x)];
8549 #ifdef LOAD_EXTEND_OP
8550 /* Some RISC machines sign-extend all loads of smaller than a word. */
8551 if (LOAD_EXTEND_OP (GET_MODE (x)) == SIGN_EXTEND)
8552 return MAX (1, ((int) bitwidth
8553 - (int) GET_MODE_BITSIZE (GET_MODE (x)) + 1));
8558 /* If the constant is negative, take its 1's complement and remask.
8559 Then see how many zero bits we have. */
8560 nonzero = INTVAL (x) & GET_MODE_MASK (mode);
8561 if (bitwidth <= HOST_BITS_PER_WIDE_INT
8562 && (nonzero & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0)
8563 nonzero = (~nonzero) & GET_MODE_MASK (mode);
8565 return (nonzero == 0 ? bitwidth : bitwidth - floor_log2 (nonzero) - 1);
8568 /* If this is a SUBREG for a promoted object that is sign-extended
8569 and we are looking at it in a wider mode, we know that at least the
8570 high-order bits are known to be sign bit copies. */
8572 if (SUBREG_PROMOTED_VAR_P (x) && ! SUBREG_PROMOTED_UNSIGNED_P (x))
8574 num0 = num_sign_bit_copies (SUBREG_REG (x), mode);
8575 return MAX ((int) bitwidth
8576 - (int) GET_MODE_BITSIZE (GET_MODE (x)) + 1,
8580 /* For a smaller object, just ignore the high bits. */
8581 if (bitwidth <= GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x))))
8583 num0 = num_sign_bit_copies (SUBREG_REG (x), VOIDmode);
8584 return MAX (1, (num0
8585 - (int) (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x)))
8589 #ifdef WORD_REGISTER_OPERATIONS
8590 #ifdef LOAD_EXTEND_OP
8591 /* For paradoxical SUBREGs on machines where all register operations
8592 affect the entire register, just look inside. Note that we are
8593 passing MODE to the recursive call, so the number of sign bit copies
8594 will remain relative to that mode, not the inner mode. */
8596 /* This works only if loads sign extend. Otherwise, if we get a
8597 reload for the inner part, it may be loaded from the stack, and
8598 then we lose all sign bit copies that existed before the store
8601 if ((GET_MODE_SIZE (GET_MODE (x))
8602 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
8603 && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (x))) == SIGN_EXTEND
8604 && GET_CODE (SUBREG_REG (x)) == MEM)
8605 return num_sign_bit_copies (SUBREG_REG (x), mode);
8611 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
8612 return MAX (1, (int) bitwidth - INTVAL (XEXP (x, 1)));
8616 return (bitwidth - GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
8617 + num_sign_bit_copies (XEXP (x, 0), VOIDmode));
8620 /* For a smaller object, just ignore the high bits. */
8621 num0 = num_sign_bit_copies (XEXP (x, 0), VOIDmode);
8622 return MAX (1, (num0 - (int) (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
8626 return num_sign_bit_copies (XEXP (x, 0), mode);
8628 case ROTATE: case ROTATERT:
8629 /* If we are rotating left by a number of bits less than the number
8630 of sign bit copies, we can just subtract that amount from the
8632 if (GET_CODE (XEXP (x, 1)) == CONST_INT
8633 && INTVAL (XEXP (x, 1)) >= 0
8634 && INTVAL (XEXP (x, 1)) < (int) bitwidth)
8636 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
8637 return MAX (1, num0 - (code == ROTATE ? INTVAL (XEXP (x, 1))
8638 : (int) bitwidth - INTVAL (XEXP (x, 1))));
8643 /* In general, this subtracts one sign bit copy. But if the value
8644 is known to be positive, the number of sign bit copies is the
8645 same as that of the input. Finally, if the input has just one bit
8646 that might be nonzero, all the bits are copies of the sign bit. */
8647 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
8648 if (bitwidth > HOST_BITS_PER_WIDE_INT)
8649 return num0 > 1 ? num0 - 1 : 1;
8651 nonzero = nonzero_bits (XEXP (x, 0), mode);
8656 && (((HOST_WIDE_INT) 1 << (bitwidth - 1)) & nonzero))
8661 case IOR: case AND: case XOR:
8662 case SMIN: case SMAX: case UMIN: case UMAX:
8663 /* Logical operations will preserve the number of sign-bit copies.
8664 MIN and MAX operations always return one of the operands. */
8665 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
8666 num1 = num_sign_bit_copies (XEXP (x, 1), mode);
8667 return MIN (num0, num1);
8669 case PLUS: case MINUS:
8670 /* For addition and subtraction, we can have a 1-bit carry. However,
8671 if we are subtracting 1 from a positive number, there will not
8672 be such a carry. Furthermore, if the positive number is known to
8673 be 0 or 1, we know the result is either -1 or 0. */
8675 if (code == PLUS && XEXP (x, 1) == constm1_rtx
8676 && bitwidth <= HOST_BITS_PER_WIDE_INT)
8678 nonzero = nonzero_bits (XEXP (x, 0), mode);
8679 if ((((HOST_WIDE_INT) 1 << (bitwidth - 1)) & nonzero) == 0)
8680 return (nonzero == 1 || nonzero == 0 ? bitwidth
8681 : bitwidth - floor_log2 (nonzero) - 1);
8684 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
8685 num1 = num_sign_bit_copies (XEXP (x, 1), mode);
8686 result = MAX (1, MIN (num0, num1) - 1);
8688 #ifdef POINTERS_EXTEND_UNSIGNED
8689 /* If pointers extend signed and this is an addition or subtraction
8690 to a pointer in Pmode, all the bits above ptr_mode are known to be
8692 if (! POINTERS_EXTEND_UNSIGNED && GET_MODE (x) == Pmode
8693 && (code == PLUS || code == MINUS)
8694 && GET_CODE (XEXP (x, 0)) == REG && REG_POINTER (XEXP (x, 0)))
8695 result = MAX ((int) (GET_MODE_BITSIZE (Pmode)
8696 - GET_MODE_BITSIZE (ptr_mode) + 1),
8702 /* The number of bits of the product is the sum of the number of
8703 bits of both terms. However, unless one of the terms if known
8704 to be positive, we must allow for an additional bit since negating
8705 a negative number can remove one sign bit copy. */
8707 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
8708 num1 = num_sign_bit_copies (XEXP (x, 1), mode);
8710 result = bitwidth - (bitwidth - num0) - (bitwidth - num1);
8712 && (bitwidth > HOST_BITS_PER_WIDE_INT
8713 || (((nonzero_bits (XEXP (x, 0), mode)
8714 & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0)
8715 && ((nonzero_bits (XEXP (x, 1), mode)
8716 & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0))))
8719 return MAX (1, result);
8722 /* The result must be <= the first operand. If the first operand
8723 has the high bit set, we know nothing about the number of sign
8725 if (bitwidth > HOST_BITS_PER_WIDE_INT)
8727 else if ((nonzero_bits (XEXP (x, 0), mode)
8728 & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0)
8731 return num_sign_bit_copies (XEXP (x, 0), mode);
8734 /* The result must be <= the second operand. */
8735 return num_sign_bit_copies (XEXP (x, 1), mode);
8738 /* Similar to unsigned division, except that we have to worry about
8739 the case where the divisor is negative, in which case we have
8741 result = num_sign_bit_copies (XEXP (x, 0), mode);
8743 && (bitwidth > HOST_BITS_PER_WIDE_INT
8744 || (nonzero_bits (XEXP (x, 1), mode)
8745 & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0))
8751 result = num_sign_bit_copies (XEXP (x, 1), mode);
8753 && (bitwidth > HOST_BITS_PER_WIDE_INT
8754 || (nonzero_bits (XEXP (x, 1), mode)
8755 & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0))
8761 /* Shifts by a constant add to the number of bits equal to the
8763 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
8764 if (GET_CODE (XEXP (x, 1)) == CONST_INT
8765 && INTVAL (XEXP (x, 1)) > 0)
8766 num0 = MIN ((int) bitwidth, num0 + INTVAL (XEXP (x, 1)));
8771 /* Left shifts destroy copies. */
8772 if (GET_CODE (XEXP (x, 1)) != CONST_INT
8773 || INTVAL (XEXP (x, 1)) < 0
8774 || INTVAL (XEXP (x, 1)) >= (int) bitwidth)
8777 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
8778 return MAX (1, num0 - INTVAL (XEXP (x, 1)));
8781 num0 = num_sign_bit_copies (XEXP (x, 1), mode);
8782 num1 = num_sign_bit_copies (XEXP (x, 2), mode);
8783 return MIN (num0, num1);
8785 case EQ: case NE: case GE: case GT: case LE: case LT:
8786 case UNEQ: case LTGT: case UNGE: case UNGT: case UNLE: case UNLT:
8787 case GEU: case GTU: case LEU: case LTU:
8788 case UNORDERED: case ORDERED:
8789 /* If the constant is negative, take its 1's complement and remask.
8790 Then see how many zero bits we have. */
8791 nonzero = STORE_FLAG_VALUE;
8792 if (bitwidth <= HOST_BITS_PER_WIDE_INT
8793 && (nonzero & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0)
8794 nonzero = (~nonzero) & GET_MODE_MASK (mode);
8796 return (nonzero == 0 ? bitwidth : bitwidth - floor_log2 (nonzero) - 1);
8803 /* If we haven't been able to figure it out by one of the above rules,
8804 see if some of the high-order bits are known to be zero. If so,
8805 count those bits and return one less than that amount. If we can't
8806 safely compute the mask for this mode, always return BITWIDTH. */
8808 if (bitwidth > HOST_BITS_PER_WIDE_INT)
8811 nonzero = nonzero_bits (x, mode);
8812 return (nonzero & ((HOST_WIDE_INT) 1 << (bitwidth - 1))
8813 ? 1 : bitwidth - floor_log2 (nonzero) - 1);
8816 /* Return the number of "extended" bits there are in X, when interpreted
8817 as a quantity in MODE whose signedness is indicated by UNSIGNEDP. For
8818 unsigned quantities, this is the number of high-order zero bits.
8819 For signed quantities, this is the number of copies of the sign bit
8820 minus 1. In both case, this function returns the number of "spare"
8821 bits. For example, if two quantities for which this function returns
8822 at least 1 are added, the addition is known not to overflow.
8824 This function will always return 0 unless called during combine, which
8825 implies that it must be called from a define_split. */
8828 extended_count (x, mode, unsignedp)
8830 enum machine_mode mode;
8833 if (nonzero_sign_valid == 0)
8837 ? (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
8838 ? (unsigned int) (GET_MODE_BITSIZE (mode) - 1
8839 - floor_log2 (nonzero_bits (x, mode)))
8841 : num_sign_bit_copies (x, mode) - 1);
8844 /* This function is called from `simplify_shift_const' to merge two
8845 outer operations. Specifically, we have already found that we need
8846 to perform operation *POP0 with constant *PCONST0 at the outermost
8847 position. We would now like to also perform OP1 with constant CONST1
8848 (with *POP0 being done last).
8850 Return 1 if we can do the operation and update *POP0 and *PCONST0 with
8851 the resulting operation. *PCOMP_P is set to 1 if we would need to
8852 complement the innermost operand, otherwise it is unchanged.
8854 MODE is the mode in which the operation will be done. No bits outside
8855 the width of this mode matter. It is assumed that the width of this mode
8856 is smaller than or equal to HOST_BITS_PER_WIDE_INT.
8858 If *POP0 or OP1 are NIL, it means no operation is required. Only NEG, PLUS,
8859 IOR, XOR, and AND are supported. We may set *POP0 to SET if the proper
8860 result is simply *PCONST0.
8862 If the resulting operation cannot be expressed as one operation, we
8863 return 0 and do not change *POP0, *PCONST0, and *PCOMP_P. */
8866 merge_outer_ops (pop0, pconst0, op1, const1, mode, pcomp_p)
8867 enum rtx_code *pop0;
8868 HOST_WIDE_INT *pconst0;
8870 HOST_WIDE_INT const1;
8871 enum machine_mode mode;
8874 enum rtx_code op0 = *pop0;
8875 HOST_WIDE_INT const0 = *pconst0;
8877 const0 &= GET_MODE_MASK (mode);
8878 const1 &= GET_MODE_MASK (mode);
8880 /* If OP0 is an AND, clear unimportant bits in CONST1. */
8884 /* If OP0 or OP1 is NIL, this is easy. Similarly if they are the same or
8887 if (op1 == NIL || op0 == SET)
8890 else if (op0 == NIL)
8891 op0 = op1, const0 = const1;
8893 else if (op0 == op1)
8917 /* Otherwise, if either is a PLUS or NEG, we can't do anything. */
8918 else if (op0 == PLUS || op1 == PLUS || op0 == NEG || op1 == NEG)
8921 /* If the two constants aren't the same, we can't do anything. The
8922 remaining six cases can all be done. */
8923 else if (const0 != const1)
8931 /* (a & b) | b == b */
8933 else /* op1 == XOR */
8934 /* (a ^ b) | b == a | b */
8940 /* (a & b) ^ b == (~a) & b */
8941 op0 = AND, *pcomp_p = 1;
8942 else /* op1 == IOR */
8943 /* (a | b) ^ b == a & ~b */
8944 op0 = AND, *pconst0 = ~const0;
8949 /* (a | b) & b == b */
8951 else /* op1 == XOR */
8952 /* (a ^ b) & b) == (~a) & b */
8959 /* Check for NO-OP cases. */
8960 const0 &= GET_MODE_MASK (mode);
8962 && (op0 == IOR || op0 == XOR || op0 == PLUS))
8964 else if (const0 == 0 && op0 == AND)
8966 else if ((unsigned HOST_WIDE_INT) const0 == GET_MODE_MASK (mode)
8970 /* ??? Slightly redundant with the above mask, but not entirely.
8971 Moving this above means we'd have to sign-extend the mode mask
8972 for the final test. */
8973 const0 = trunc_int_for_mode (const0, mode);
8981 /* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift.
8982 The result of the shift is RESULT_MODE. X, if non-zero, is an expression
8983 that we started with.
8985 The shift is normally computed in the widest mode we find in VAROP, as
8986 long as it isn't a different number of words than RESULT_MODE. Exceptions
8987 are ASHIFTRT and ROTATE, which are always done in their original mode, */
8990 simplify_shift_const (x, code, result_mode, varop, orig_count)
8993 enum machine_mode result_mode;
8997 enum rtx_code orig_code = code;
9000 enum machine_mode mode = result_mode;
9001 enum machine_mode shift_mode, tmode;
9002 unsigned int mode_words
9003 = (GET_MODE_SIZE (mode) + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD;
9004 /* We form (outer_op (code varop count) (outer_const)). */
9005 enum rtx_code outer_op = NIL;
9006 HOST_WIDE_INT outer_const = 0;
9008 int complement_p = 0;
9011 /* Make sure and truncate the "natural" shift on the way in. We don't
9012 want to do this inside the loop as it makes it more difficult to
9014 #ifdef SHIFT_COUNT_TRUNCATED
9015 if (SHIFT_COUNT_TRUNCATED)
9016 orig_count &= GET_MODE_BITSIZE (mode) - 1;
9019 /* If we were given an invalid count, don't do anything except exactly
9020 what was requested. */
9022 if (orig_count < 0 || orig_count >= (int) GET_MODE_BITSIZE (mode))
9027 return gen_rtx_fmt_ee (code, mode, varop, GEN_INT (orig_count));
9032 /* Unless one of the branches of the `if' in this loop does a `continue',
9033 we will `break' the loop after the `if'. */
9037 /* If we have an operand of (clobber (const_int 0)), just return that
9039 if (GET_CODE (varop) == CLOBBER)
9042 /* If we discovered we had to complement VAROP, leave. Making a NOT
9043 here would cause an infinite loop. */
9047 /* Convert ROTATERT to ROTATE. */
9048 if (code == ROTATERT)
9049 code = ROTATE, count = GET_MODE_BITSIZE (result_mode) - count;
9051 /* We need to determine what mode we will do the shift in. If the
9052 shift is a right shift or a ROTATE, we must always do it in the mode
9053 it was originally done in. Otherwise, we can do it in MODE, the
9054 widest mode encountered. */
9056 = (code == ASHIFTRT || code == LSHIFTRT || code == ROTATE
9057 ? result_mode : mode);
9059 /* Handle cases where the count is greater than the size of the mode
9060 minus 1. For ASHIFT, use the size minus one as the count (this can
9061 occur when simplifying (lshiftrt (ashiftrt ..))). For rotates,
9062 take the count modulo the size. For other shifts, the result is
9065 Since these shifts are being produced by the compiler by combining
9066 multiple operations, each of which are defined, we know what the
9067 result is supposed to be. */
9069 if (count > (unsigned int) (GET_MODE_BITSIZE (shift_mode) - 1))
9071 if (code == ASHIFTRT)
9072 count = GET_MODE_BITSIZE (shift_mode) - 1;
9073 else if (code == ROTATE || code == ROTATERT)
9074 count %= GET_MODE_BITSIZE (shift_mode);
9077 /* We can't simply return zero because there may be an
9085 /* An arithmetic right shift of a quantity known to be -1 or 0
9087 if (code == ASHIFTRT
9088 && (num_sign_bit_copies (varop, shift_mode)
9089 == GET_MODE_BITSIZE (shift_mode)))
9095 /* If we are doing an arithmetic right shift and discarding all but
9096 the sign bit copies, this is equivalent to doing a shift by the
9097 bitsize minus one. Convert it into that shift because it will often
9098 allow other simplifications. */
9100 if (code == ASHIFTRT
9101 && (count + num_sign_bit_copies (varop, shift_mode)
9102 >= GET_MODE_BITSIZE (shift_mode)))
9103 count = GET_MODE_BITSIZE (shift_mode) - 1;
9105 /* We simplify the tests below and elsewhere by converting
9106 ASHIFTRT to LSHIFTRT if we know the sign bit is clear.
9107 `make_compound_operation' will convert it to an ASHIFTRT for
9108 those machines (such as VAX) that don't have an LSHIFTRT. */
9109 if (GET_MODE_BITSIZE (shift_mode) <= HOST_BITS_PER_WIDE_INT
9111 && ((nonzero_bits (varop, shift_mode)
9112 & ((HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (shift_mode) - 1)))
9116 switch (GET_CODE (varop))
9122 new = expand_compound_operation (varop);
9131 /* If we have (xshiftrt (mem ...) C) and C is MODE_WIDTH
9132 minus the width of a smaller mode, we can do this with a
9133 SIGN_EXTEND or ZERO_EXTEND from the narrower memory location. */
9134 if ((code == ASHIFTRT || code == LSHIFTRT)
9135 && ! mode_dependent_address_p (XEXP (varop, 0))
9136 && ! MEM_VOLATILE_P (varop)
9137 && (tmode = mode_for_size (GET_MODE_BITSIZE (mode) - count,
9138 MODE_INT, 1)) != BLKmode)
9140 new = adjust_address_nv (varop, tmode,
9141 BYTES_BIG_ENDIAN ? 0
9142 : count / BITS_PER_UNIT);
9144 varop = gen_rtx_fmt_e (code == ASHIFTRT ? SIGN_EXTEND
9145 : ZERO_EXTEND, mode, new);
9152 /* Similar to the case above, except that we can only do this if
9153 the resulting mode is the same as that of the underlying
9154 MEM and adjust the address depending on the *bits* endianness
9155 because of the way that bit-field extract insns are defined. */
9156 if ((code == ASHIFTRT || code == LSHIFTRT)
9157 && (tmode = mode_for_size (GET_MODE_BITSIZE (mode) - count,
9158 MODE_INT, 1)) != BLKmode
9159 && tmode == GET_MODE (XEXP (varop, 0)))
9161 if (BITS_BIG_ENDIAN)
9162 new = XEXP (varop, 0);
9165 new = copy_rtx (XEXP (varop, 0));
9166 SUBST (XEXP (new, 0),
9167 plus_constant (XEXP (new, 0),
9168 count / BITS_PER_UNIT));
9171 varop = gen_rtx_fmt_e (code == ASHIFTRT ? SIGN_EXTEND
9172 : ZERO_EXTEND, mode, new);
9179 /* If VAROP is a SUBREG, strip it as long as the inner operand has
9180 the same number of words as what we've seen so far. Then store
9181 the widest mode in MODE. */
9182 if (subreg_lowpart_p (varop)
9183 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop)))
9184 > GET_MODE_SIZE (GET_MODE (varop)))
9185 && (unsigned int) ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop)))
9186 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
9189 varop = SUBREG_REG (varop);
9190 if (GET_MODE_SIZE (GET_MODE (varop)) > GET_MODE_SIZE (mode))
9191 mode = GET_MODE (varop);
9197 /* Some machines use MULT instead of ASHIFT because MULT
9198 is cheaper. But it is still better on those machines to
9199 merge two shifts into one. */
9200 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
9201 && exact_log2 (INTVAL (XEXP (varop, 1))) >= 0)
9204 = gen_binary (ASHIFT, GET_MODE (varop), XEXP (varop, 0),
9205 GEN_INT (exact_log2 (INTVAL (XEXP (varop, 1)))));
9211 /* Similar, for when divides are cheaper. */
9212 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
9213 && exact_log2 (INTVAL (XEXP (varop, 1))) >= 0)
9216 = gen_binary (LSHIFTRT, GET_MODE (varop), XEXP (varop, 0),
9217 GEN_INT (exact_log2 (INTVAL (XEXP (varop, 1)))));
9223 /* If we are extracting just the sign bit of an arithmetic
9224 right shift, that shift is not needed. However, the sign
9225 bit of a wider mode may be different from what would be
9226 interpreted as the sign bit in a narrower mode, so, if
9227 the result is narrower, don't discard the shift. */
9228 if (code == LSHIFTRT
9229 && count == (unsigned int) (GET_MODE_BITSIZE (result_mode) - 1)
9230 && (GET_MODE_BITSIZE (result_mode)
9231 >= GET_MODE_BITSIZE (GET_MODE (varop))))
9233 varop = XEXP (varop, 0);
9237 /* ... fall through ... */
9242 /* Here we have two nested shifts. The result is usually the
9243 AND of a new shift with a mask. We compute the result below. */
9244 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
9245 && INTVAL (XEXP (varop, 1)) >= 0
9246 && INTVAL (XEXP (varop, 1)) < GET_MODE_BITSIZE (GET_MODE (varop))
9247 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
9248 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
9250 enum rtx_code first_code = GET_CODE (varop);
9251 unsigned int first_count = INTVAL (XEXP (varop, 1));
9252 unsigned HOST_WIDE_INT mask;
9255 /* We have one common special case. We can't do any merging if
9256 the inner code is an ASHIFTRT of a smaller mode. However, if
9257 we have (ashift:M1 (subreg:M1 (ashiftrt:M2 FOO C1) 0) C2)
9258 with C2 == GET_MODE_BITSIZE (M1) - GET_MODE_BITSIZE (M2),
9259 we can convert it to
9260 (ashiftrt:M1 (ashift:M1 (and:M1 (subreg:M1 FOO 0 C2) C3) C1).
9261 This simplifies certain SIGN_EXTEND operations. */
9262 if (code == ASHIFT && first_code == ASHIFTRT
9263 && count == (unsigned int)
9264 (GET_MODE_BITSIZE (result_mode)
9265 - GET_MODE_BITSIZE (GET_MODE (varop))))
9267 /* C3 has the low-order C1 bits zero. */
9269 mask = (GET_MODE_MASK (mode)
9270 & ~(((HOST_WIDE_INT) 1 << first_count) - 1));
9272 varop = simplify_and_const_int (NULL_RTX, result_mode,
9273 XEXP (varop, 0), mask);
9274 varop = simplify_shift_const (NULL_RTX, ASHIFT, result_mode,
9276 count = first_count;
9281 /* If this was (ashiftrt (ashift foo C1) C2) and FOO has more
9282 than C1 high-order bits equal to the sign bit, we can convert
9283 this to either an ASHIFT or an ASHIFTRT depending on the
9286 We cannot do this if VAROP's mode is not SHIFT_MODE. */
9288 if (code == ASHIFTRT && first_code == ASHIFT
9289 && GET_MODE (varop) == shift_mode
9290 && (num_sign_bit_copies (XEXP (varop, 0), shift_mode)
9293 varop = XEXP (varop, 0);
9295 signed_count = count - first_count;
9296 if (signed_count < 0)
9297 count = -signed_count, code = ASHIFT;
9299 count = signed_count;
9304 /* There are some cases we can't do. If CODE is ASHIFTRT,
9305 we can only do this if FIRST_CODE is also ASHIFTRT.
9307 We can't do the case when CODE is ROTATE and FIRST_CODE is
9310 If the mode of this shift is not the mode of the outer shift,
9311 we can't do this if either shift is a right shift or ROTATE.
9313 Finally, we can't do any of these if the mode is too wide
9314 unless the codes are the same.
9316 Handle the case where the shift codes are the same
9319 if (code == first_code)
9321 if (GET_MODE (varop) != result_mode
9322 && (code == ASHIFTRT || code == LSHIFTRT
9326 count += first_count;
9327 varop = XEXP (varop, 0);
9331 if (code == ASHIFTRT
9332 || (code == ROTATE && first_code == ASHIFTRT)
9333 || GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT
9334 || (GET_MODE (varop) != result_mode
9335 && (first_code == ASHIFTRT || first_code == LSHIFTRT
9336 || first_code == ROTATE
9337 || code == ROTATE)))
9340 /* To compute the mask to apply after the shift, shift the
9341 nonzero bits of the inner shift the same way the
9342 outer shift will. */
9344 mask_rtx = GEN_INT (nonzero_bits (varop, GET_MODE (varop)));
9347 = simplify_binary_operation (code, result_mode, mask_rtx,
9350 /* Give up if we can't compute an outer operation to use. */
9352 || GET_CODE (mask_rtx) != CONST_INT
9353 || ! merge_outer_ops (&outer_op, &outer_const, AND,
9355 result_mode, &complement_p))
9358 /* If the shifts are in the same direction, we add the
9359 counts. Otherwise, we subtract them. */
9360 signed_count = count;
9361 if ((code == ASHIFTRT || code == LSHIFTRT)
9362 == (first_code == ASHIFTRT || first_code == LSHIFTRT))
9363 signed_count += first_count;
9365 signed_count -= first_count;
9367 /* If COUNT is positive, the new shift is usually CODE,
9368 except for the two exceptions below, in which case it is
9369 FIRST_CODE. If the count is negative, FIRST_CODE should
9371 if (signed_count > 0
9372 && ((first_code == ROTATE && code == ASHIFT)
9373 || (first_code == ASHIFTRT && code == LSHIFTRT)))
9374 code = first_code, count = signed_count;
9375 else if (signed_count < 0)
9376 code = first_code, count = -signed_count;
9378 count = signed_count;
9380 varop = XEXP (varop, 0);
9384 /* If we have (A << B << C) for any shift, we can convert this to
9385 (A << C << B). This wins if A is a constant. Only try this if
9386 B is not a constant. */
9388 else if (GET_CODE (varop) == code
9389 && GET_CODE (XEXP (varop, 1)) != CONST_INT
9391 = simplify_binary_operation (code, mode,
9395 varop = gen_rtx_fmt_ee (code, mode, new, XEXP (varop, 1));
9402 /* Make this fit the case below. */
9403 varop = gen_rtx_XOR (mode, XEXP (varop, 0),
9404 GEN_INT (GET_MODE_MASK (mode)));
9410 /* If we have (xshiftrt (ior (plus X (const_int -1)) X) C)
9411 with C the size of VAROP - 1 and the shift is logical if
9412 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
9413 we have an (le X 0) operation. If we have an arithmetic shift
9414 and STORE_FLAG_VALUE is 1 or we have a logical shift with
9415 STORE_FLAG_VALUE of -1, we have a (neg (le X 0)) operation. */
9417 if (GET_CODE (varop) == IOR && GET_CODE (XEXP (varop, 0)) == PLUS
9418 && XEXP (XEXP (varop, 0), 1) == constm1_rtx
9419 && (STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
9420 && (code == LSHIFTRT || code == ASHIFTRT)
9421 && count == (unsigned int)
9422 (GET_MODE_BITSIZE (GET_MODE (varop)) - 1)
9423 && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
9426 varop = gen_rtx_LE (GET_MODE (varop), XEXP (varop, 1),
9429 if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
9430 varop = gen_rtx_NEG (GET_MODE (varop), varop);
9435 /* If we have (shift (logical)), move the logical to the outside
9436 to allow it to possibly combine with another logical and the
9437 shift to combine with another shift. This also canonicalizes to
9438 what a ZERO_EXTRACT looks like. Also, some machines have
9439 (and (shift)) insns. */
9441 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
9442 && (new = simplify_binary_operation (code, result_mode,
9444 GEN_INT (count))) != 0
9445 && GET_CODE (new) == CONST_INT
9446 && merge_outer_ops (&outer_op, &outer_const, GET_CODE (varop),
9447 INTVAL (new), result_mode, &complement_p))
9449 varop = XEXP (varop, 0);
9453 /* If we can't do that, try to simplify the shift in each arm of the
9454 logical expression, make a new logical expression, and apply
9455 the inverse distributive law. */
9457 rtx lhs = simplify_shift_const (NULL_RTX, code, shift_mode,
9458 XEXP (varop, 0), count);
9459 rtx rhs = simplify_shift_const (NULL_RTX, code, shift_mode,
9460 XEXP (varop, 1), count);
9462 varop = gen_binary (GET_CODE (varop), shift_mode, lhs, rhs);
9463 varop = apply_distributive_law (varop);
9470 /* convert (lshiftrt (eq FOO 0) C) to (xor FOO 1) if STORE_FLAG_VALUE
9471 says that the sign bit can be tested, FOO has mode MODE, C is
9472 GET_MODE_BITSIZE (MODE) - 1, and FOO has only its low-order bit
9473 that may be nonzero. */
9474 if (code == LSHIFTRT
9475 && XEXP (varop, 1) == const0_rtx
9476 && GET_MODE (XEXP (varop, 0)) == result_mode
9477 && count == (unsigned int) (GET_MODE_BITSIZE (result_mode) - 1)
9478 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
9479 && ((STORE_FLAG_VALUE
9480 & ((HOST_WIDE_INT) 1
9481 < (GET_MODE_BITSIZE (result_mode) - 1))))
9482 && nonzero_bits (XEXP (varop, 0), result_mode) == 1
9483 && merge_outer_ops (&outer_op, &outer_const, XOR,
9484 (HOST_WIDE_INT) 1, result_mode,
9487 varop = XEXP (varop, 0);
9494 /* (lshiftrt (neg A) C) where A is either 0 or 1 and C is one less
9495 than the number of bits in the mode is equivalent to A. */
9496 if (code == LSHIFTRT
9497 && count == (unsigned int) (GET_MODE_BITSIZE (result_mode) - 1)
9498 && nonzero_bits (XEXP (varop, 0), result_mode) == 1)
9500 varop = XEXP (varop, 0);
9505 /* NEG commutes with ASHIFT since it is multiplication. Move the
9506 NEG outside to allow shifts to combine. */
9508 && merge_outer_ops (&outer_op, &outer_const, NEG,
9509 (HOST_WIDE_INT) 0, result_mode,
9512 varop = XEXP (varop, 0);
9518 /* (lshiftrt (plus A -1) C) where A is either 0 or 1 and C
9519 is one less than the number of bits in the mode is
9520 equivalent to (xor A 1). */
9521 if (code == LSHIFTRT
9522 && count == (unsigned int) (GET_MODE_BITSIZE (result_mode) - 1)
9523 && XEXP (varop, 1) == constm1_rtx
9524 && nonzero_bits (XEXP (varop, 0), result_mode) == 1
9525 && merge_outer_ops (&outer_op, &outer_const, XOR,
9526 (HOST_WIDE_INT) 1, result_mode,
9530 varop = XEXP (varop, 0);
9534 /* If we have (xshiftrt (plus FOO BAR) C), and the only bits
9535 that might be nonzero in BAR are those being shifted out and those
9536 bits are known zero in FOO, we can replace the PLUS with FOO.
9537 Similarly in the other operand order. This code occurs when
9538 we are computing the size of a variable-size array. */
9540 if ((code == ASHIFTRT || code == LSHIFTRT)
9541 && count < HOST_BITS_PER_WIDE_INT
9542 && nonzero_bits (XEXP (varop, 1), result_mode) >> count == 0
9543 && (nonzero_bits (XEXP (varop, 1), result_mode)
9544 & nonzero_bits (XEXP (varop, 0), result_mode)) == 0)
9546 varop = XEXP (varop, 0);
9549 else if ((code == ASHIFTRT || code == LSHIFTRT)
9550 && count < HOST_BITS_PER_WIDE_INT
9551 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
9552 && 0 == (nonzero_bits (XEXP (varop, 0), result_mode)
9554 && 0 == (nonzero_bits (XEXP (varop, 0), result_mode)
9555 & nonzero_bits (XEXP (varop, 1),
9558 varop = XEXP (varop, 1);
9562 /* (ashift (plus foo C) N) is (plus (ashift foo N) C'). */
9564 && GET_CODE (XEXP (varop, 1)) == CONST_INT
9565 && (new = simplify_binary_operation (ASHIFT, result_mode,
9567 GEN_INT (count))) != 0
9568 && GET_CODE (new) == CONST_INT
9569 && merge_outer_ops (&outer_op, &outer_const, PLUS,
9570 INTVAL (new), result_mode, &complement_p))
9572 varop = XEXP (varop, 0);
9578 /* If we have (xshiftrt (minus (ashiftrt X C)) X) C)
9579 with C the size of VAROP - 1 and the shift is logical if
9580 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
9581 we have a (gt X 0) operation. If the shift is arithmetic with
9582 STORE_FLAG_VALUE of 1 or logical with STORE_FLAG_VALUE == -1,
9583 we have a (neg (gt X 0)) operation. */
9585 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
9586 && GET_CODE (XEXP (varop, 0)) == ASHIFTRT
9587 && count == (unsigned int)
9588 (GET_MODE_BITSIZE (GET_MODE (varop)) - 1)
9589 && (code == LSHIFTRT || code == ASHIFTRT)
9590 && GET_CODE (XEXP (XEXP (varop, 0), 1)) == CONST_INT
9591 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (XEXP (varop, 0), 1))
9593 && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
9596 varop = gen_rtx_GT (GET_MODE (varop), XEXP (varop, 1),
9599 if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
9600 varop = gen_rtx_NEG (GET_MODE (varop), varop);
9607 /* Change (lshiftrt (truncate (lshiftrt))) to (truncate (lshiftrt))
9608 if the truncate does not affect the value. */
9609 if (code == LSHIFTRT
9610 && GET_CODE (XEXP (varop, 0)) == LSHIFTRT
9611 && GET_CODE (XEXP (XEXP (varop, 0), 1)) == CONST_INT
9612 && (INTVAL (XEXP (XEXP (varop, 0), 1))
9613 >= (GET_MODE_BITSIZE (GET_MODE (XEXP (varop, 0)))
9614 - GET_MODE_BITSIZE (GET_MODE (varop)))))
9616 rtx varop_inner = XEXP (varop, 0);
9619 = gen_rtx_LSHIFTRT (GET_MODE (varop_inner),
9620 XEXP (varop_inner, 0),
9622 (count + INTVAL (XEXP (varop_inner, 1))));
9623 varop = gen_rtx_TRUNCATE (GET_MODE (varop), varop_inner);
9636 /* We need to determine what mode to do the shift in. If the shift is
9637 a right shift or ROTATE, we must always do it in the mode it was
9638 originally done in. Otherwise, we can do it in MODE, the widest mode
9639 encountered. The code we care about is that of the shift that will
9640 actually be done, not the shift that was originally requested. */
9642 = (code == ASHIFTRT || code == LSHIFTRT || code == ROTATE
9643 ? result_mode : mode);
9645 /* We have now finished analyzing the shift. The result should be
9646 a shift of type CODE with SHIFT_MODE shifting VAROP COUNT places. If
9647 OUTER_OP is non-NIL, it is an operation that needs to be applied
9648 to the result of the shift. OUTER_CONST is the relevant constant,
9649 but we must turn off all bits turned off in the shift.
9651 If we were passed a value for X, see if we can use any pieces of
9652 it. If not, make new rtx. */
9654 if (x && GET_RTX_CLASS (GET_CODE (x)) == '2'
9655 && GET_CODE (XEXP (x, 1)) == CONST_INT
9656 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (x, 1)) == count)
9657 const_rtx = XEXP (x, 1);
9659 const_rtx = GEN_INT (count);
9661 if (x && GET_CODE (XEXP (x, 0)) == SUBREG
9662 && GET_MODE (XEXP (x, 0)) == shift_mode
9663 && SUBREG_REG (XEXP (x, 0)) == varop)
9664 varop = XEXP (x, 0);
9665 else if (GET_MODE (varop) != shift_mode)
9666 varop = gen_lowpart_for_combine (shift_mode, varop);
9668 /* If we can't make the SUBREG, try to return what we were given. */
9669 if (GET_CODE (varop) == CLOBBER)
9670 return x ? x : varop;
9672 new = simplify_binary_operation (code, shift_mode, varop, const_rtx);
9676 x = gen_rtx_fmt_ee (code, shift_mode, varop, const_rtx);
9678 /* If we have an outer operation and we just made a shift, it is
9679 possible that we could have simplified the shift were it not
9680 for the outer operation. So try to do the simplification
9683 if (outer_op != NIL && GET_CODE (x) == code
9684 && GET_CODE (XEXP (x, 1)) == CONST_INT)
9685 x = simplify_shift_const (x, code, shift_mode, XEXP (x, 0),
9686 INTVAL (XEXP (x, 1)));
9688 /* If we were doing an LSHIFTRT in a wider mode than it was originally,
9689 turn off all the bits that the shift would have turned off. */
9690 if (orig_code == LSHIFTRT && result_mode != shift_mode)
9691 x = simplify_and_const_int (NULL_RTX, shift_mode, x,
9692 GET_MODE_MASK (result_mode) >> orig_count);
9694 /* Do the remainder of the processing in RESULT_MODE. */
9695 x = gen_lowpart_for_combine (result_mode, x);
9697 /* If COMPLEMENT_P is set, we have to complement X before doing the outer
9700 x =simplify_gen_unary (NOT, result_mode, x, result_mode);
9702 if (outer_op != NIL)
9704 if (GET_MODE_BITSIZE (result_mode) < HOST_BITS_PER_WIDE_INT)
9705 outer_const = trunc_int_for_mode (outer_const, result_mode);
9707 if (outer_op == AND)
9708 x = simplify_and_const_int (NULL_RTX, result_mode, x, outer_const);
9709 else if (outer_op == SET)
9710 /* This means that we have determined that the result is
9711 equivalent to a constant. This should be rare. */
9712 x = GEN_INT (outer_const);
9713 else if (GET_RTX_CLASS (outer_op) == '1')
9714 x = simplify_gen_unary (outer_op, result_mode, x, result_mode);
9716 x = gen_binary (outer_op, result_mode, x, GEN_INT (outer_const));
9722 /* Like recog, but we receive the address of a pointer to a new pattern.
9723 We try to match the rtx that the pointer points to.
9724 If that fails, we may try to modify or replace the pattern,
9725 storing the replacement into the same pointer object.
9727 Modifications include deletion or addition of CLOBBERs.
9729 PNOTES is a pointer to a location where any REG_UNUSED notes added for
9730 the CLOBBERs are placed.
9732 The value is the final insn code from the pattern ultimately matched,
9736 recog_for_combine (pnewpat, insn, pnotes)
9742 int insn_code_number;
9743 int num_clobbers_to_add = 0;
9748 /* If PAT is a PARALLEL, check to see if it contains the CLOBBER
9749 we use to indicate that something didn't match. If we find such a
9750 thing, force rejection. */
9751 if (GET_CODE (pat) == PARALLEL)
9752 for (i = XVECLEN (pat, 0) - 1; i >= 0; i--)
9753 if (GET_CODE (XVECEXP (pat, 0, i)) == CLOBBER
9754 && XEXP (XVECEXP (pat, 0, i), 0) == const0_rtx)
9757 /* *pnewpat does not have to be actual PATTERN (insn), so make a dummy
9758 instruction for pattern recognition. */
9759 dummy_insn = shallow_copy_rtx (insn);
9760 PATTERN (dummy_insn) = pat;
9761 REG_NOTES (dummy_insn) = 0;
9763 insn_code_number = recog (pat, dummy_insn, &num_clobbers_to_add);
9765 /* If it isn't, there is the possibility that we previously had an insn
9766 that clobbered some register as a side effect, but the combined
9767 insn doesn't need to do that. So try once more without the clobbers
9768 unless this represents an ASM insn. */
9770 if (insn_code_number < 0 && ! check_asm_operands (pat)
9771 && GET_CODE (pat) == PARALLEL)
9775 for (pos = 0, i = 0; i < XVECLEN (pat, 0); i++)
9776 if (GET_CODE (XVECEXP (pat, 0, i)) != CLOBBER)
9779 SUBST (XVECEXP (pat, 0, pos), XVECEXP (pat, 0, i));
9783 SUBST_INT (XVECLEN (pat, 0), pos);
9786 pat = XVECEXP (pat, 0, 0);
9788 PATTERN (dummy_insn) = pat;
9789 insn_code_number = recog (pat, dummy_insn, &num_clobbers_to_add);
9792 /* Recognize all noop sets, these will be killed by followup pass. */
9793 if (insn_code_number < 0 && GET_CODE (pat) == SET && set_noop_p (pat))
9794 insn_code_number = NOOP_MOVE_INSN_CODE, num_clobbers_to_add = 0;
9796 /* If we had any clobbers to add, make a new pattern than contains
9797 them. Then check to make sure that all of them are dead. */
9798 if (num_clobbers_to_add)
9800 rtx newpat = gen_rtx_PARALLEL (VOIDmode,
9801 rtvec_alloc (GET_CODE (pat) == PARALLEL
9803 + num_clobbers_to_add)
9804 : num_clobbers_to_add + 1));
9806 if (GET_CODE (pat) == PARALLEL)
9807 for (i = 0; i < XVECLEN (pat, 0); i++)
9808 XVECEXP (newpat, 0, i) = XVECEXP (pat, 0, i);
9810 XVECEXP (newpat, 0, 0) = pat;
9812 add_clobbers (newpat, insn_code_number);
9814 for (i = XVECLEN (newpat, 0) - num_clobbers_to_add;
9815 i < XVECLEN (newpat, 0); i++)
9817 if (GET_CODE (XEXP (XVECEXP (newpat, 0, i), 0)) == REG
9818 && ! reg_dead_at_p (XEXP (XVECEXP (newpat, 0, i), 0), insn))
9820 notes = gen_rtx_EXPR_LIST (REG_UNUSED,
9821 XEXP (XVECEXP (newpat, 0, i), 0), notes);
9829 return insn_code_number;
9832 /* Like gen_lowpart but for use by combine. In combine it is not possible
9833 to create any new pseudoregs. However, it is safe to create
9834 invalid memory addresses, because combine will try to recognize
9835 them and all they will do is make the combine attempt fail.
9837 If for some reason this cannot do its job, an rtx
9838 (clobber (const_int 0)) is returned.
9839 An insn containing that will not be recognized. */
9844 gen_lowpart_for_combine (mode, x)
9845 enum machine_mode mode;
9850 if (GET_MODE (x) == mode)
9853 /* We can only support MODE being wider than a word if X is a
9854 constant integer or has a mode the same size. */
9856 if (GET_MODE_SIZE (mode) > UNITS_PER_WORD
9857 && ! ((GET_MODE (x) == VOIDmode
9858 && (GET_CODE (x) == CONST_INT
9859 || GET_CODE (x) == CONST_DOUBLE))
9860 || GET_MODE_SIZE (GET_MODE (x)) == GET_MODE_SIZE (mode)))
9861 return gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
9863 /* X might be a paradoxical (subreg (mem)). In that case, gen_lowpart
9864 won't know what to do. So we will strip off the SUBREG here and
9865 process normally. */
9866 if (GET_CODE (x) == SUBREG && GET_CODE (SUBREG_REG (x)) == MEM)
9869 if (GET_MODE (x) == mode)
9873 result = gen_lowpart_common (mode, x);
9874 #ifdef CLASS_CANNOT_CHANGE_MODE
9876 && GET_CODE (result) == SUBREG
9877 && GET_CODE (SUBREG_REG (result)) == REG
9878 && REGNO (SUBREG_REG (result)) >= FIRST_PSEUDO_REGISTER
9879 && CLASS_CANNOT_CHANGE_MODE_P (GET_MODE (result),
9880 GET_MODE (SUBREG_REG (result))))
9881 REG_CHANGES_MODE (REGNO (SUBREG_REG (result))) = 1;
9887 if (GET_CODE (x) == MEM)
9891 /* Refuse to work on a volatile memory ref or one with a mode-dependent
9893 if (MEM_VOLATILE_P (x) || mode_dependent_address_p (XEXP (x, 0)))
9894 return gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
9896 /* If we want to refer to something bigger than the original memref,
9897 generate a perverse subreg instead. That will force a reload
9898 of the original memref X. */
9899 if (GET_MODE_SIZE (GET_MODE (x)) < GET_MODE_SIZE (mode))
9900 return gen_rtx_SUBREG (mode, x, 0);
9902 if (WORDS_BIG_ENDIAN)
9903 offset = (MAX (GET_MODE_SIZE (GET_MODE (x)), UNITS_PER_WORD)
9904 - MAX (GET_MODE_SIZE (mode), UNITS_PER_WORD));
9906 if (BYTES_BIG_ENDIAN)
9908 /* Adjust the address so that the address-after-the-data is
9910 offset -= (MIN (UNITS_PER_WORD, GET_MODE_SIZE (mode))
9911 - MIN (UNITS_PER_WORD, GET_MODE_SIZE (GET_MODE (x))));
9914 return adjust_address_nv (x, mode, offset);
9917 /* If X is a comparison operator, rewrite it in a new mode. This
9918 probably won't match, but may allow further simplifications. */
9919 else if (GET_RTX_CLASS (GET_CODE (x)) == '<')
9920 return gen_rtx_fmt_ee (GET_CODE (x), mode, XEXP (x, 0), XEXP (x, 1));
9922 /* If we couldn't simplify X any other way, just enclose it in a
9923 SUBREG. Normally, this SUBREG won't match, but some patterns may
9924 include an explicit SUBREG or we may simplify it further in combine. */
9929 enum machine_mode sub_mode = GET_MODE (x);
9931 offset = subreg_lowpart_offset (mode, sub_mode);
9932 if (sub_mode == VOIDmode)
9934 sub_mode = int_mode_for_mode (mode);
9935 x = gen_lowpart_common (sub_mode, x);
9937 res = simplify_gen_subreg (mode, x, sub_mode, offset);
9940 return gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
9944 /* These routines make binary and unary operations by first seeing if they
9945 fold; if not, a new expression is allocated. */
9948 gen_binary (code, mode, op0, op1)
9950 enum machine_mode mode;
9956 if (GET_RTX_CLASS (code) == 'c'
9957 && swap_commutative_operands_p (op0, op1))
9958 tem = op0, op0 = op1, op1 = tem;
9960 if (GET_RTX_CLASS (code) == '<')
9962 enum machine_mode op_mode = GET_MODE (op0);
9964 /* Strip the COMPARE from (REL_OP (compare X Y) 0) to get
9965 just (REL_OP X Y). */
9966 if (GET_CODE (op0) == COMPARE && op1 == const0_rtx)
9968 op1 = XEXP (op0, 1);
9969 op0 = XEXP (op0, 0);
9970 op_mode = GET_MODE (op0);
9973 if (op_mode == VOIDmode)
9974 op_mode = GET_MODE (op1);
9975 result = simplify_relational_operation (code, op_mode, op0, op1);
9978 result = simplify_binary_operation (code, mode, op0, op1);
9983 /* Put complex operands first and constants second. */
9984 if (GET_RTX_CLASS (code) == 'c'
9985 && swap_commutative_operands_p (op0, op1))
9986 return gen_rtx_fmt_ee (code, mode, op1, op0);
9988 /* If we are turning off bits already known off in OP0, we need not do
9990 else if (code == AND && GET_CODE (op1) == CONST_INT
9991 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
9992 && (nonzero_bits (op0, mode) & ~INTVAL (op1)) == 0)
9995 return gen_rtx_fmt_ee (code, mode, op0, op1);
9998 /* Simplify a comparison between *POP0 and *POP1 where CODE is the
9999 comparison code that will be tested.
10001 The result is a possibly different comparison code to use. *POP0 and
10002 *POP1 may be updated.
10004 It is possible that we might detect that a comparison is either always
10005 true or always false. However, we do not perform general constant
10006 folding in combine, so this knowledge isn't useful. Such tautologies
10007 should have been detected earlier. Hence we ignore all such cases. */
10009 static enum rtx_code
10010 simplify_comparison (code, pop0, pop1)
10011 enum rtx_code code;
10019 enum machine_mode mode, tmode;
10021 /* Try a few ways of applying the same transformation to both operands. */
10024 #ifndef WORD_REGISTER_OPERATIONS
10025 /* The test below this one won't handle SIGN_EXTENDs on these machines,
10026 so check specially. */
10027 if (code != GTU && code != GEU && code != LTU && code != LEU
10028 && GET_CODE (op0) == ASHIFTRT && GET_CODE (op1) == ASHIFTRT
10029 && GET_CODE (XEXP (op0, 0)) == ASHIFT
10030 && GET_CODE (XEXP (op1, 0)) == ASHIFT
10031 && GET_CODE (XEXP (XEXP (op0, 0), 0)) == SUBREG
10032 && GET_CODE (XEXP (XEXP (op1, 0), 0)) == SUBREG
10033 && (GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0)))
10034 == GET_MODE (SUBREG_REG (XEXP (XEXP (op1, 0), 0))))
10035 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10036 && GET_CODE (XEXP (op1, 1)) == CONST_INT
10037 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
10038 && GET_CODE (XEXP (XEXP (op1, 0), 1)) == CONST_INT
10039 && INTVAL (XEXP (op0, 1)) == INTVAL (XEXP (op1, 1))
10040 && INTVAL (XEXP (op0, 1)) == INTVAL (XEXP (XEXP (op0, 0), 1))
10041 && INTVAL (XEXP (op0, 1)) == INTVAL (XEXP (XEXP (op1, 0), 1))
10042 && (INTVAL (XEXP (op0, 1))
10043 == (GET_MODE_BITSIZE (GET_MODE (op0))
10044 - (GET_MODE_BITSIZE
10045 (GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0))))))))
10047 op0 = SUBREG_REG (XEXP (XEXP (op0, 0), 0));
10048 op1 = SUBREG_REG (XEXP (XEXP (op1, 0), 0));
10052 /* If both operands are the same constant shift, see if we can ignore the
10053 shift. We can if the shift is a rotate or if the bits shifted out of
10054 this shift are known to be zero for both inputs and if the type of
10055 comparison is compatible with the shift. */
10056 if (GET_CODE (op0) == GET_CODE (op1)
10057 && GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
10058 && ((GET_CODE (op0) == ROTATE && (code == NE || code == EQ))
10059 || ((GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFT)
10060 && (code != GT && code != LT && code != GE && code != LE))
10061 || (GET_CODE (op0) == ASHIFTRT
10062 && (code != GTU && code != LTU
10063 && code != GEU && code != LEU)))
10064 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10065 && INTVAL (XEXP (op0, 1)) >= 0
10066 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT
10067 && XEXP (op0, 1) == XEXP (op1, 1))
10069 enum machine_mode mode = GET_MODE (op0);
10070 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
10071 int shift_count = INTVAL (XEXP (op0, 1));
10073 if (GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFTRT)
10074 mask &= (mask >> shift_count) << shift_count;
10075 else if (GET_CODE (op0) == ASHIFT)
10076 mask = (mask & (mask << shift_count)) >> shift_count;
10078 if ((nonzero_bits (XEXP (op0, 0), mode) & ~mask) == 0
10079 && (nonzero_bits (XEXP (op1, 0), mode) & ~mask) == 0)
10080 op0 = XEXP (op0, 0), op1 = XEXP (op1, 0);
10085 /* If both operands are AND's of a paradoxical SUBREG by constant, the
10086 SUBREGs are of the same mode, and, in both cases, the AND would
10087 be redundant if the comparison was done in the narrower mode,
10088 do the comparison in the narrower mode (e.g., we are AND'ing with 1
10089 and the operand's possibly nonzero bits are 0xffffff01; in that case
10090 if we only care about QImode, we don't need the AND). This case
10091 occurs if the output mode of an scc insn is not SImode and
10092 STORE_FLAG_VALUE == 1 (e.g., the 386).
10094 Similarly, check for a case where the AND's are ZERO_EXTEND
10095 operations from some narrower mode even though a SUBREG is not
10098 else if (GET_CODE (op0) == AND && GET_CODE (op1) == AND
10099 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10100 && GET_CODE (XEXP (op1, 1)) == CONST_INT)
10102 rtx inner_op0 = XEXP (op0, 0);
10103 rtx inner_op1 = XEXP (op1, 0);
10104 HOST_WIDE_INT c0 = INTVAL (XEXP (op0, 1));
10105 HOST_WIDE_INT c1 = INTVAL (XEXP (op1, 1));
10108 if (GET_CODE (inner_op0) == SUBREG && GET_CODE (inner_op1) == SUBREG
10109 && (GET_MODE_SIZE (GET_MODE (inner_op0))
10110 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (inner_op0))))
10111 && (GET_MODE (SUBREG_REG (inner_op0))
10112 == GET_MODE (SUBREG_REG (inner_op1)))
10113 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (inner_op0)))
10114 <= HOST_BITS_PER_WIDE_INT)
10115 && (0 == ((~c0) & nonzero_bits (SUBREG_REG (inner_op0),
10116 GET_MODE (SUBREG_REG (inner_op0)))))
10117 && (0 == ((~c1) & nonzero_bits (SUBREG_REG (inner_op1),
10118 GET_MODE (SUBREG_REG (inner_op1))))))
10120 op0 = SUBREG_REG (inner_op0);
10121 op1 = SUBREG_REG (inner_op1);
10123 /* The resulting comparison is always unsigned since we masked
10124 off the original sign bit. */
10125 code = unsigned_condition (code);
10131 for (tmode = GET_CLASS_NARROWEST_MODE
10132 (GET_MODE_CLASS (GET_MODE (op0)));
10133 tmode != GET_MODE (op0); tmode = GET_MODE_WIDER_MODE (tmode))
10134 if ((unsigned HOST_WIDE_INT) c0 == GET_MODE_MASK (tmode))
10136 op0 = gen_lowpart_for_combine (tmode, inner_op0);
10137 op1 = gen_lowpart_for_combine (tmode, inner_op1);
10138 code = unsigned_condition (code);
10147 /* If both operands are NOT, we can strip off the outer operation
10148 and adjust the comparison code for swapped operands; similarly for
10149 NEG, except that this must be an equality comparison. */
10150 else if ((GET_CODE (op0) == NOT && GET_CODE (op1) == NOT)
10151 || (GET_CODE (op0) == NEG && GET_CODE (op1) == NEG
10152 && (code == EQ || code == NE)))
10153 op0 = XEXP (op0, 0), op1 = XEXP (op1, 0), code = swap_condition (code);
10159 /* If the first operand is a constant, swap the operands and adjust the
10160 comparison code appropriately, but don't do this if the second operand
10161 is already a constant integer. */
10162 if (swap_commutative_operands_p (op0, op1))
10164 tem = op0, op0 = op1, op1 = tem;
10165 code = swap_condition (code);
10168 /* We now enter a loop during which we will try to simplify the comparison.
10169 For the most part, we only are concerned with comparisons with zero,
10170 but some things may really be comparisons with zero but not start
10171 out looking that way. */
10173 while (GET_CODE (op1) == CONST_INT)
10175 enum machine_mode mode = GET_MODE (op0);
10176 unsigned int mode_width = GET_MODE_BITSIZE (mode);
10177 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
10178 int equality_comparison_p;
10179 int sign_bit_comparison_p;
10180 int unsigned_comparison_p;
10181 HOST_WIDE_INT const_op;
10183 /* We only want to handle integral modes. This catches VOIDmode,
10184 CCmode, and the floating-point modes. An exception is that we
10185 can handle VOIDmode if OP0 is a COMPARE or a comparison
10188 if (GET_MODE_CLASS (mode) != MODE_INT
10189 && ! (mode == VOIDmode
10190 && (GET_CODE (op0) == COMPARE
10191 || GET_RTX_CLASS (GET_CODE (op0)) == '<')))
10194 /* Get the constant we are comparing against and turn off all bits
10195 not on in our mode. */
10196 const_op = INTVAL (op1);
10197 if (mode != VOIDmode)
10198 const_op = trunc_int_for_mode (const_op, mode);
10199 op1 = GEN_INT (const_op);
10201 /* If we are comparing against a constant power of two and the value
10202 being compared can only have that single bit nonzero (e.g., it was
10203 `and'ed with that bit), we can replace this with a comparison
10206 && (code == EQ || code == NE || code == GE || code == GEU
10207 || code == LT || code == LTU)
10208 && mode_width <= HOST_BITS_PER_WIDE_INT
10209 && exact_log2 (const_op) >= 0
10210 && nonzero_bits (op0, mode) == (unsigned HOST_WIDE_INT) const_op)
10212 code = (code == EQ || code == GE || code == GEU ? NE : EQ);
10213 op1 = const0_rtx, const_op = 0;
10216 /* Similarly, if we are comparing a value known to be either -1 or
10217 0 with -1, change it to the opposite comparison against zero. */
10220 && (code == EQ || code == NE || code == GT || code == LE
10221 || code == GEU || code == LTU)
10222 && num_sign_bit_copies (op0, mode) == mode_width)
10224 code = (code == EQ || code == LE || code == GEU ? NE : EQ);
10225 op1 = const0_rtx, const_op = 0;
10228 /* Do some canonicalizations based on the comparison code. We prefer
10229 comparisons against zero and then prefer equality comparisons.
10230 If we can reduce the size of a constant, we will do that too. */
10235 /* < C is equivalent to <= (C - 1) */
10239 op1 = GEN_INT (const_op);
10241 /* ... fall through to LE case below. */
10247 /* <= C is equivalent to < (C + 1); we do this for C < 0 */
10251 op1 = GEN_INT (const_op);
10255 /* If we are doing a <= 0 comparison on a value known to have
10256 a zero sign bit, we can replace this with == 0. */
10257 else if (const_op == 0
10258 && mode_width <= HOST_BITS_PER_WIDE_INT
10259 && (nonzero_bits (op0, mode)
10260 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)
10265 /* >= C is equivalent to > (C - 1). */
10269 op1 = GEN_INT (const_op);
10271 /* ... fall through to GT below. */
10277 /* > C is equivalent to >= (C + 1); we do this for C < 0. */
10281 op1 = GEN_INT (const_op);
10285 /* If we are doing a > 0 comparison on a value known to have
10286 a zero sign bit, we can replace this with != 0. */
10287 else if (const_op == 0
10288 && mode_width <= HOST_BITS_PER_WIDE_INT
10289 && (nonzero_bits (op0, mode)
10290 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)
10295 /* < C is equivalent to <= (C - 1). */
10299 op1 = GEN_INT (const_op);
10301 /* ... fall through ... */
10304 /* (unsigned) < 0x80000000 is equivalent to >= 0. */
10305 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
10306 && (const_op == (HOST_WIDE_INT) 1 << (mode_width - 1)))
10308 const_op = 0, op1 = const0_rtx;
10316 /* unsigned <= 0 is equivalent to == 0 */
10320 /* (unsigned) <= 0x7fffffff is equivalent to >= 0. */
10321 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
10322 && (const_op == ((HOST_WIDE_INT) 1 << (mode_width - 1)) - 1))
10324 const_op = 0, op1 = const0_rtx;
10330 /* >= C is equivalent to < (C - 1). */
10334 op1 = GEN_INT (const_op);
10336 /* ... fall through ... */
10339 /* (unsigned) >= 0x80000000 is equivalent to < 0. */
10340 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
10341 && (const_op == (HOST_WIDE_INT) 1 << (mode_width - 1)))
10343 const_op = 0, op1 = const0_rtx;
10351 /* unsigned > 0 is equivalent to != 0 */
10355 /* (unsigned) > 0x7fffffff is equivalent to < 0. */
10356 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
10357 && (const_op == ((HOST_WIDE_INT) 1 << (mode_width - 1)) - 1))
10359 const_op = 0, op1 = const0_rtx;
10368 /* Compute some predicates to simplify code below. */
10370 equality_comparison_p = (code == EQ || code == NE);
10371 sign_bit_comparison_p = ((code == LT || code == GE) && const_op == 0);
10372 unsigned_comparison_p = (code == LTU || code == LEU || code == GTU
10375 /* If this is a sign bit comparison and we can do arithmetic in
10376 MODE, say that we will only be needing the sign bit of OP0. */
10377 if (sign_bit_comparison_p
10378 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
10379 op0 = force_to_mode (op0, mode,
10381 << (GET_MODE_BITSIZE (mode) - 1)),
10384 /* Now try cases based on the opcode of OP0. If none of the cases
10385 does a "continue", we exit this loop immediately after the
10388 switch (GET_CODE (op0))
10391 /* If we are extracting a single bit from a variable position in
10392 a constant that has only a single bit set and are comparing it
10393 with zero, we can convert this into an equality comparison
10394 between the position and the location of the single bit. */
10396 if (GET_CODE (XEXP (op0, 0)) == CONST_INT
10397 && XEXP (op0, 1) == const1_rtx
10398 && equality_comparison_p && const_op == 0
10399 && (i = exact_log2 (INTVAL (XEXP (op0, 0)))) >= 0)
10401 if (BITS_BIG_ENDIAN)
10403 enum machine_mode new_mode
10404 = mode_for_extraction (EP_extzv, 1);
10405 if (new_mode == MAX_MACHINE_MODE)
10406 i = BITS_PER_WORD - 1 - i;
10410 i = (GET_MODE_BITSIZE (mode) - 1 - i);
10414 op0 = XEXP (op0, 2);
10418 /* Result is nonzero iff shift count is equal to I. */
10419 code = reverse_condition (code);
10423 /* ... fall through ... */
10426 tem = expand_compound_operation (op0);
10435 /* If testing for equality, we can take the NOT of the constant. */
10436 if (equality_comparison_p
10437 && (tem = simplify_unary_operation (NOT, mode, op1, mode)) != 0)
10439 op0 = XEXP (op0, 0);
10444 /* If just looking at the sign bit, reverse the sense of the
10446 if (sign_bit_comparison_p)
10448 op0 = XEXP (op0, 0);
10449 code = (code == GE ? LT : GE);
10455 /* If testing for equality, we can take the NEG of the constant. */
10456 if (equality_comparison_p
10457 && (tem = simplify_unary_operation (NEG, mode, op1, mode)) != 0)
10459 op0 = XEXP (op0, 0);
10464 /* The remaining cases only apply to comparisons with zero. */
10468 /* When X is ABS or is known positive,
10469 (neg X) is < 0 if and only if X != 0. */
10471 if (sign_bit_comparison_p
10472 && (GET_CODE (XEXP (op0, 0)) == ABS
10473 || (mode_width <= HOST_BITS_PER_WIDE_INT
10474 && (nonzero_bits (XEXP (op0, 0), mode)
10475 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)))
10477 op0 = XEXP (op0, 0);
10478 code = (code == LT ? NE : EQ);
10482 /* If we have NEG of something whose two high-order bits are the
10483 same, we know that "(-a) < 0" is equivalent to "a > 0". */
10484 if (num_sign_bit_copies (op0, mode) >= 2)
10486 op0 = XEXP (op0, 0);
10487 code = swap_condition (code);
10493 /* If we are testing equality and our count is a constant, we
10494 can perform the inverse operation on our RHS. */
10495 if (equality_comparison_p && GET_CODE (XEXP (op0, 1)) == CONST_INT
10496 && (tem = simplify_binary_operation (ROTATERT, mode,
10497 op1, XEXP (op0, 1))) != 0)
10499 op0 = XEXP (op0, 0);
10504 /* If we are doing a < 0 or >= 0 comparison, it means we are testing
10505 a particular bit. Convert it to an AND of a constant of that
10506 bit. This will be converted into a ZERO_EXTRACT. */
10507 if (const_op == 0 && sign_bit_comparison_p
10508 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10509 && mode_width <= HOST_BITS_PER_WIDE_INT)
10511 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
10514 - INTVAL (XEXP (op0, 1)))));
10515 code = (code == LT ? NE : EQ);
10519 /* Fall through. */
10522 /* ABS is ignorable inside an equality comparison with zero. */
10523 if (const_op == 0 && equality_comparison_p)
10525 op0 = XEXP (op0, 0);
10531 /* Can simplify (compare (zero/sign_extend FOO) CONST)
10532 to (compare FOO CONST) if CONST fits in FOO's mode and we
10533 are either testing inequality or have an unsigned comparison
10534 with ZERO_EXTEND or a signed comparison with SIGN_EXTEND. */
10535 if (! unsigned_comparison_p
10536 && (GET_MODE_BITSIZE (GET_MODE (XEXP (op0, 0)))
10537 <= HOST_BITS_PER_WIDE_INT)
10538 && ((unsigned HOST_WIDE_INT) const_op
10539 < (((unsigned HOST_WIDE_INT) 1
10540 << (GET_MODE_BITSIZE (GET_MODE (XEXP (op0, 0))) - 1)))))
10542 op0 = XEXP (op0, 0);
10548 /* Check for the case where we are comparing A - C1 with C2,
10549 both constants are smaller than 1/2 the maximum positive
10550 value in MODE, and the comparison is equality or unsigned.
10551 In that case, if A is either zero-extended to MODE or has
10552 sufficient sign bits so that the high-order bit in MODE
10553 is a copy of the sign in the inner mode, we can prove that it is
10554 safe to do the operation in the wider mode. This simplifies
10555 many range checks. */
10557 if (mode_width <= HOST_BITS_PER_WIDE_INT
10558 && subreg_lowpart_p (op0)
10559 && GET_CODE (SUBREG_REG (op0)) == PLUS
10560 && GET_CODE (XEXP (SUBREG_REG (op0), 1)) == CONST_INT
10561 && INTVAL (XEXP (SUBREG_REG (op0), 1)) < 0
10562 && (-INTVAL (XEXP (SUBREG_REG (op0), 1))
10563 < (HOST_WIDE_INT) (GET_MODE_MASK (mode) / 2))
10564 && (unsigned HOST_WIDE_INT) const_op < GET_MODE_MASK (mode) / 2
10565 && (0 == (nonzero_bits (XEXP (SUBREG_REG (op0), 0),
10566 GET_MODE (SUBREG_REG (op0)))
10567 & ~GET_MODE_MASK (mode))
10568 || (num_sign_bit_copies (XEXP (SUBREG_REG (op0), 0),
10569 GET_MODE (SUBREG_REG (op0)))
10571 (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0)))
10572 - GET_MODE_BITSIZE (mode)))))
10574 op0 = SUBREG_REG (op0);
10578 /* If the inner mode is narrower and we are extracting the low part,
10579 we can treat the SUBREG as if it were a ZERO_EXTEND. */
10580 if (subreg_lowpart_p (op0)
10581 && GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0))) < mode_width)
10582 /* Fall through */ ;
10586 /* ... fall through ... */
10589 if ((unsigned_comparison_p || equality_comparison_p)
10590 && (GET_MODE_BITSIZE (GET_MODE (XEXP (op0, 0)))
10591 <= HOST_BITS_PER_WIDE_INT)
10592 && ((unsigned HOST_WIDE_INT) const_op
10593 < GET_MODE_MASK (GET_MODE (XEXP (op0, 0)))))
10595 op0 = XEXP (op0, 0);
10601 /* (eq (plus X A) B) -> (eq X (minus B A)). We can only do
10602 this for equality comparisons due to pathological cases involving
10604 if (equality_comparison_p
10605 && 0 != (tem = simplify_binary_operation (MINUS, mode,
10606 op1, XEXP (op0, 1))))
10608 op0 = XEXP (op0, 0);
10613 /* (plus (abs X) (const_int -1)) is < 0 if and only if X == 0. */
10614 if (const_op == 0 && XEXP (op0, 1) == constm1_rtx
10615 && GET_CODE (XEXP (op0, 0)) == ABS && sign_bit_comparison_p)
10617 op0 = XEXP (XEXP (op0, 0), 0);
10618 code = (code == LT ? EQ : NE);
10624 /* We used to optimize signed comparisons against zero, but that
10625 was incorrect. Unsigned comparisons against zero (GTU, LEU)
10626 arrive here as equality comparisons, or (GEU, LTU) are
10627 optimized away. No need to special-case them. */
10629 /* (eq (minus A B) C) -> (eq A (plus B C)) or
10630 (eq B (minus A C)), whichever simplifies. We can only do
10631 this for equality comparisons due to pathological cases involving
10633 if (equality_comparison_p
10634 && 0 != (tem = simplify_binary_operation (PLUS, mode,
10635 XEXP (op0, 1), op1)))
10637 op0 = XEXP (op0, 0);
10642 if (equality_comparison_p
10643 && 0 != (tem = simplify_binary_operation (MINUS, mode,
10644 XEXP (op0, 0), op1)))
10646 op0 = XEXP (op0, 1);
10651 /* The sign bit of (minus (ashiftrt X C) X), where C is the number
10652 of bits in X minus 1, is one iff X > 0. */
10653 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == ASHIFTRT
10654 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
10655 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (XEXP (op0, 0), 1))
10657 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
10659 op0 = XEXP (op0, 1);
10660 code = (code == GE ? LE : GT);
10666 /* (eq (xor A B) C) -> (eq A (xor B C)). This is a simplification
10667 if C is zero or B is a constant. */
10668 if (equality_comparison_p
10669 && 0 != (tem = simplify_binary_operation (XOR, mode,
10670 XEXP (op0, 1), op1)))
10672 op0 = XEXP (op0, 0);
10679 case UNEQ: case LTGT:
10680 case LT: case LTU: case UNLT: case LE: case LEU: case UNLE:
10681 case GT: case GTU: case UNGT: case GE: case GEU: case UNGE:
10682 case UNORDERED: case ORDERED:
10683 /* We can't do anything if OP0 is a condition code value, rather
10684 than an actual data value. */
10687 || XEXP (op0, 0) == cc0_rtx
10689 || GET_MODE_CLASS (GET_MODE (XEXP (op0, 0))) == MODE_CC)
10692 /* Get the two operands being compared. */
10693 if (GET_CODE (XEXP (op0, 0)) == COMPARE)
10694 tem = XEXP (XEXP (op0, 0), 0), tem1 = XEXP (XEXP (op0, 0), 1);
10696 tem = XEXP (op0, 0), tem1 = XEXP (op0, 1);
10698 /* Check for the cases where we simply want the result of the
10699 earlier test or the opposite of that result. */
10700 if (code == NE || code == EQ
10701 || (GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
10702 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
10703 && (STORE_FLAG_VALUE
10704 & (((HOST_WIDE_INT) 1
10705 << (GET_MODE_BITSIZE (GET_MODE (op0)) - 1))))
10706 && (code == LT || code == GE)))
10708 enum rtx_code new_code;
10709 if (code == LT || code == NE)
10710 new_code = GET_CODE (op0);
10712 new_code = combine_reversed_comparison_code (op0);
10714 if (new_code != UNKNOWN)
10725 /* The sign bit of (ior (plus X (const_int -1)) X) is non-zero
10727 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == PLUS
10728 && XEXP (XEXP (op0, 0), 1) == constm1_rtx
10729 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
10731 op0 = XEXP (op0, 1);
10732 code = (code == GE ? GT : LE);
10738 /* Convert (and (xshift 1 X) Y) to (and (lshiftrt Y X) 1). This
10739 will be converted to a ZERO_EXTRACT later. */
10740 if (const_op == 0 && equality_comparison_p
10741 && GET_CODE (XEXP (op0, 0)) == ASHIFT
10742 && XEXP (XEXP (op0, 0), 0) == const1_rtx)
10744 op0 = simplify_and_const_int
10745 (op0, mode, gen_rtx_LSHIFTRT (mode,
10747 XEXP (XEXP (op0, 0), 1)),
10748 (HOST_WIDE_INT) 1);
10752 /* If we are comparing (and (lshiftrt X C1) C2) for equality with
10753 zero and X is a comparison and C1 and C2 describe only bits set
10754 in STORE_FLAG_VALUE, we can compare with X. */
10755 if (const_op == 0 && equality_comparison_p
10756 && mode_width <= HOST_BITS_PER_WIDE_INT
10757 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10758 && GET_CODE (XEXP (op0, 0)) == LSHIFTRT
10759 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
10760 && INTVAL (XEXP (XEXP (op0, 0), 1)) >= 0
10761 && INTVAL (XEXP (XEXP (op0, 0), 1)) < HOST_BITS_PER_WIDE_INT)
10763 mask = ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
10764 << INTVAL (XEXP (XEXP (op0, 0), 1)));
10765 if ((~STORE_FLAG_VALUE & mask) == 0
10766 && (GET_RTX_CLASS (GET_CODE (XEXP (XEXP (op0, 0), 0))) == '<'
10767 || ((tem = get_last_value (XEXP (XEXP (op0, 0), 0))) != 0
10768 && GET_RTX_CLASS (GET_CODE (tem)) == '<')))
10770 op0 = XEXP (XEXP (op0, 0), 0);
10775 /* If we are doing an equality comparison of an AND of a bit equal
10776 to the sign bit, replace this with a LT or GE comparison of
10777 the underlying value. */
10778 if (equality_comparison_p
10780 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10781 && mode_width <= HOST_BITS_PER_WIDE_INT
10782 && ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
10783 == (unsigned HOST_WIDE_INT) 1 << (mode_width - 1)))
10785 op0 = XEXP (op0, 0);
10786 code = (code == EQ ? GE : LT);
10790 /* If this AND operation is really a ZERO_EXTEND from a narrower
10791 mode, the constant fits within that mode, and this is either an
10792 equality or unsigned comparison, try to do this comparison in
10793 the narrower mode. */
10794 if ((equality_comparison_p || unsigned_comparison_p)
10795 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10796 && (i = exact_log2 ((INTVAL (XEXP (op0, 1))
10797 & GET_MODE_MASK (mode))
10799 && const_op >> i == 0
10800 && (tmode = mode_for_size (i, MODE_INT, 1)) != BLKmode)
10802 op0 = gen_lowpart_for_combine (tmode, XEXP (op0, 0));
10806 /* If this is (and:M1 (subreg:M2 X 0) (const_int C1)) where C1 fits
10807 in both M1 and M2 and the SUBREG is either paradoxical or
10808 represents the low part, permute the SUBREG and the AND and
10810 if (GET_CODE (XEXP (op0, 0)) == SUBREG
10812 #ifdef WORD_REGISTER_OPERATIONS
10814 > (GET_MODE_BITSIZE
10815 (GET_MODE (SUBREG_REG (XEXP (op0, 0))))))
10816 && mode_width <= BITS_PER_WORD)
10819 <= (GET_MODE_BITSIZE
10820 (GET_MODE (SUBREG_REG (XEXP (op0, 0))))))
10821 && subreg_lowpart_p (XEXP (op0, 0))))
10822 #ifndef WORD_REGISTER_OPERATIONS
10823 /* It is unsafe to commute the AND into the SUBREG if the SUBREG
10824 is paradoxical and WORD_REGISTER_OPERATIONS is not defined.
10825 As originally written the upper bits have a defined value
10826 due to the AND operation. However, if we commute the AND
10827 inside the SUBREG then they no longer have defined values
10828 and the meaning of the code has been changed. */
10829 && (GET_MODE_SIZE (GET_MODE (XEXP (op0, 0)))
10830 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (op0, 0)))))
10832 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10833 && mode_width <= HOST_BITS_PER_WIDE_INT
10834 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (XEXP (op0, 0))))
10835 <= HOST_BITS_PER_WIDE_INT)
10836 && (INTVAL (XEXP (op0, 1)) & ~mask) == 0
10837 && 0 == (~GET_MODE_MASK (GET_MODE (SUBREG_REG (XEXP (op0, 0))))
10838 & INTVAL (XEXP (op0, 1)))
10839 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (op0, 1)) != mask
10840 && ((unsigned HOST_WIDE_INT) INTVAL (XEXP (op0, 1))
10841 != GET_MODE_MASK (GET_MODE (SUBREG_REG (XEXP (op0, 0))))))
10845 = gen_lowpart_for_combine
10847 gen_binary (AND, GET_MODE (SUBREG_REG (XEXP (op0, 0))),
10848 SUBREG_REG (XEXP (op0, 0)), XEXP (op0, 1)));
10852 /* Convert (ne (and (lshiftrt (not X)) 1) 0) to
10853 (eq (and (lshiftrt X) 1) 0). */
10854 if (const_op == 0 && equality_comparison_p
10855 && XEXP (op0, 1) == const1_rtx
10856 && GET_CODE (XEXP (op0, 0)) == LSHIFTRT
10857 && GET_CODE (XEXP (XEXP (op0, 0), 0)) == NOT)
10859 op0 = simplify_and_const_int
10861 gen_rtx_LSHIFTRT (mode, XEXP (XEXP (XEXP (op0, 0), 0), 0),
10862 XEXP (XEXP (op0, 0), 1)),
10863 (HOST_WIDE_INT) 1);
10864 code = (code == NE ? EQ : NE);
10870 /* If we have (compare (ashift FOO N) (const_int C)) and
10871 the high order N bits of FOO (N+1 if an inequality comparison)
10872 are known to be zero, we can do this by comparing FOO with C
10873 shifted right N bits so long as the low-order N bits of C are
10875 if (GET_CODE (XEXP (op0, 1)) == CONST_INT
10876 && INTVAL (XEXP (op0, 1)) >= 0
10877 && ((INTVAL (XEXP (op0, 1)) + ! equality_comparison_p)
10878 < HOST_BITS_PER_WIDE_INT)
10880 & (((HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1))) - 1)) == 0)
10881 && mode_width <= HOST_BITS_PER_WIDE_INT
10882 && (nonzero_bits (XEXP (op0, 0), mode)
10883 & ~(mask >> (INTVAL (XEXP (op0, 1))
10884 + ! equality_comparison_p))) == 0)
10886 /* We must perform a logical shift, not an arithmetic one,
10887 as we want the top N bits of C to be zero. */
10888 unsigned HOST_WIDE_INT temp = const_op & GET_MODE_MASK (mode);
10890 temp >>= INTVAL (XEXP (op0, 1));
10891 op1 = gen_int_mode (temp, mode);
10892 op0 = XEXP (op0, 0);
10896 /* If we are doing a sign bit comparison, it means we are testing
10897 a particular bit. Convert it to the appropriate AND. */
10898 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 1)) == CONST_INT
10899 && mode_width <= HOST_BITS_PER_WIDE_INT)
10901 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
10904 - INTVAL (XEXP (op0, 1)))));
10905 code = (code == LT ? NE : EQ);
10909 /* If this an equality comparison with zero and we are shifting
10910 the low bit to the sign bit, we can convert this to an AND of the
10912 if (const_op == 0 && equality_comparison_p
10913 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10914 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (op0, 1))
10917 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
10918 (HOST_WIDE_INT) 1);
10924 /* If this is an equality comparison with zero, we can do this
10925 as a logical shift, which might be much simpler. */
10926 if (equality_comparison_p && const_op == 0
10927 && GET_CODE (XEXP (op0, 1)) == CONST_INT)
10929 op0 = simplify_shift_const (NULL_RTX, LSHIFTRT, mode,
10931 INTVAL (XEXP (op0, 1)));
10935 /* If OP0 is a sign extension and CODE is not an unsigned comparison,
10936 do the comparison in a narrower mode. */
10937 if (! unsigned_comparison_p
10938 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10939 && GET_CODE (XEXP (op0, 0)) == ASHIFT
10940 && XEXP (op0, 1) == XEXP (XEXP (op0, 0), 1)
10941 && (tmode = mode_for_size (mode_width - INTVAL (XEXP (op0, 1)),
10942 MODE_INT, 1)) != BLKmode
10943 && (((unsigned HOST_WIDE_INT) const_op
10944 + (GET_MODE_MASK (tmode) >> 1) + 1)
10945 <= GET_MODE_MASK (tmode)))
10947 op0 = gen_lowpart_for_combine (tmode, XEXP (XEXP (op0, 0), 0));
10951 /* Likewise if OP0 is a PLUS of a sign extension with a
10952 constant, which is usually represented with the PLUS
10953 between the shifts. */
10954 if (! unsigned_comparison_p
10955 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10956 && GET_CODE (XEXP (op0, 0)) == PLUS
10957 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
10958 && GET_CODE (XEXP (XEXP (op0, 0), 0)) == ASHIFT
10959 && XEXP (op0, 1) == XEXP (XEXP (XEXP (op0, 0), 0), 1)
10960 && (tmode = mode_for_size (mode_width - INTVAL (XEXP (op0, 1)),
10961 MODE_INT, 1)) != BLKmode
10962 && (((unsigned HOST_WIDE_INT) const_op
10963 + (GET_MODE_MASK (tmode) >> 1) + 1)
10964 <= GET_MODE_MASK (tmode)))
10966 rtx inner = XEXP (XEXP (XEXP (op0, 0), 0), 0);
10967 rtx add_const = XEXP (XEXP (op0, 0), 1);
10968 rtx new_const = gen_binary (ASHIFTRT, GET_MODE (op0), add_const,
10971 op0 = gen_binary (PLUS, tmode,
10972 gen_lowpart_for_combine (tmode, inner),
10977 /* ... fall through ... */
10979 /* If we have (compare (xshiftrt FOO N) (const_int C)) and
10980 the low order N bits of FOO are known to be zero, we can do this
10981 by comparing FOO with C shifted left N bits so long as no
10982 overflow occurs. */
10983 if (GET_CODE (XEXP (op0, 1)) == CONST_INT
10984 && INTVAL (XEXP (op0, 1)) >= 0
10985 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT
10986 && mode_width <= HOST_BITS_PER_WIDE_INT
10987 && (nonzero_bits (XEXP (op0, 0), mode)
10988 & (((HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1))) - 1)) == 0
10989 && (((unsigned HOST_WIDE_INT) const_op
10990 + (GET_CODE (op0) != LSHIFTRT
10991 ? ((GET_MODE_MASK (mode) >> INTVAL (XEXP (op0, 1)) >> 1)
10994 <= GET_MODE_MASK (mode) >> INTVAL (XEXP (op0, 1))))
10996 /* If the shift was logical, then we must make the condition
10998 if (GET_CODE (op0) == LSHIFTRT)
10999 code = unsigned_condition (code);
11001 const_op <<= INTVAL (XEXP (op0, 1));
11002 op1 = GEN_INT (const_op);
11003 op0 = XEXP (op0, 0);
11007 /* If we are using this shift to extract just the sign bit, we
11008 can replace this with an LT or GE comparison. */
11010 && (equality_comparison_p || sign_bit_comparison_p)
11011 && GET_CODE (XEXP (op0, 1)) == CONST_INT
11012 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (op0, 1))
11015 op0 = XEXP (op0, 0);
11016 code = (code == NE || code == GT ? LT : GE);
11028 /* Now make any compound operations involved in this comparison. Then,
11029 check for an outmost SUBREG on OP0 that is not doing anything or is
11030 paradoxical. The latter transformation must only be performed when
11031 it is known that the "extra" bits will be the same in op0 and op1 or
11032 that they don't matter. There are three cases to consider:
11034 1. SUBREG_REG (op0) is a register. In this case the bits are don't
11035 care bits and we can assume they have any convenient value. So
11036 making the transformation is safe.
11038 2. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is not defined.
11039 In this case the upper bits of op0 are undefined. We should not make
11040 the simplification in that case as we do not know the contents of
11043 3. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is defined and not
11044 NIL. In that case we know those bits are zeros or ones. We must
11045 also be sure that they are the same as the upper bits of op1.
11047 We can never remove a SUBREG for a non-equality comparison because
11048 the sign bit is in a different place in the underlying object. */
11050 op0 = make_compound_operation (op0, op1 == const0_rtx ? COMPARE : SET);
11051 op1 = make_compound_operation (op1, SET);
11053 if (GET_CODE (op0) == SUBREG && subreg_lowpart_p (op0)
11054 /* Case 3 above, to sometimes allow (subreg (mem x)), isn't
11056 && GET_CODE (SUBREG_REG (op0)) == REG
11057 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
11058 && GET_MODE_CLASS (GET_MODE (SUBREG_REG (op0))) == MODE_INT
11059 && (code == NE || code == EQ))
11061 if (GET_MODE_SIZE (GET_MODE (op0))
11062 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (op0))))
11064 op0 = SUBREG_REG (op0);
11065 op1 = gen_lowpart_for_combine (GET_MODE (op0), op1);
11067 else if ((GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0)))
11068 <= HOST_BITS_PER_WIDE_INT)
11069 && (nonzero_bits (SUBREG_REG (op0),
11070 GET_MODE (SUBREG_REG (op0)))
11071 & ~GET_MODE_MASK (GET_MODE (op0))) == 0)
11073 tem = gen_lowpart_for_combine (GET_MODE (SUBREG_REG (op0)), op1);
11075 if ((nonzero_bits (tem, GET_MODE (SUBREG_REG (op0)))
11076 & ~GET_MODE_MASK (GET_MODE (op0))) == 0)
11077 op0 = SUBREG_REG (op0), op1 = tem;
11081 /* We now do the opposite procedure: Some machines don't have compare
11082 insns in all modes. If OP0's mode is an integer mode smaller than a
11083 word and we can't do a compare in that mode, see if there is a larger
11084 mode for which we can do the compare. There are a number of cases in
11085 which we can use the wider mode. */
11087 mode = GET_MODE (op0);
11088 if (mode != VOIDmode && GET_MODE_CLASS (mode) == MODE_INT
11089 && GET_MODE_SIZE (mode) < UNITS_PER_WORD
11090 && ! have_insn_for (COMPARE, mode))
11091 for (tmode = GET_MODE_WIDER_MODE (mode);
11093 && GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT);
11094 tmode = GET_MODE_WIDER_MODE (tmode))
11095 if (have_insn_for (COMPARE, tmode))
11099 /* If the only nonzero bits in OP0 and OP1 are those in the
11100 narrower mode and this is an equality or unsigned comparison,
11101 we can use the wider mode. Similarly for sign-extended
11102 values, in which case it is true for all comparisons. */
11103 zero_extended = ((code == EQ || code == NE
11104 || code == GEU || code == GTU
11105 || code == LEU || code == LTU)
11106 && (nonzero_bits (op0, tmode)
11107 & ~GET_MODE_MASK (mode)) == 0
11108 && ((GET_CODE (op1) == CONST_INT
11109 || (nonzero_bits (op1, tmode)
11110 & ~GET_MODE_MASK (mode)) == 0)));
11113 || ((num_sign_bit_copies (op0, tmode)
11114 > (unsigned int) (GET_MODE_BITSIZE (tmode)
11115 - GET_MODE_BITSIZE (mode)))
11116 && (num_sign_bit_copies (op1, tmode)
11117 > (unsigned int) (GET_MODE_BITSIZE (tmode)
11118 - GET_MODE_BITSIZE (mode)))))
11120 /* If OP0 is an AND and we don't have an AND in MODE either,
11121 make a new AND in the proper mode. */
11122 if (GET_CODE (op0) == AND
11123 && !have_insn_for (AND, mode))
11124 op0 = gen_binary (AND, tmode,
11125 gen_lowpart_for_combine (tmode,
11127 gen_lowpart_for_combine (tmode,
11130 op0 = gen_lowpart_for_combine (tmode, op0);
11131 if (zero_extended && GET_CODE (op1) == CONST_INT)
11132 op1 = GEN_INT (INTVAL (op1) & GET_MODE_MASK (mode));
11133 op1 = gen_lowpart_for_combine (tmode, op1);
11137 /* If this is a test for negative, we can make an explicit
11138 test of the sign bit. */
11140 if (op1 == const0_rtx && (code == LT || code == GE)
11141 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
11143 op0 = gen_binary (AND, tmode,
11144 gen_lowpart_for_combine (tmode, op0),
11145 GEN_INT ((HOST_WIDE_INT) 1
11146 << (GET_MODE_BITSIZE (mode) - 1)));
11147 code = (code == LT) ? NE : EQ;
11152 #ifdef CANONICALIZE_COMPARISON
11153 /* If this machine only supports a subset of valid comparisons, see if we
11154 can convert an unsupported one into a supported one. */
11155 CANONICALIZE_COMPARISON (code, op0, op1);
11164 /* Like jump.c' reversed_comparison_code, but use combine infrastructure for
11165 searching backward. */
11166 static enum rtx_code
11167 combine_reversed_comparison_code (exp)
11170 enum rtx_code code1 = reversed_comparison_code (exp, NULL);
11173 if (code1 != UNKNOWN
11174 || GET_MODE_CLASS (GET_MODE (XEXP (exp, 0))) != MODE_CC)
11176 /* Otherwise try and find where the condition codes were last set and
11178 x = get_last_value (XEXP (exp, 0));
11179 if (!x || GET_CODE (x) != COMPARE)
11181 return reversed_comparison_code_parts (GET_CODE (exp),
11182 XEXP (x, 0), XEXP (x, 1), NULL);
11184 /* Return comparison with reversed code of EXP and operands OP0 and OP1.
11185 Return NULL_RTX in case we fail to do the reversal. */
11187 reversed_comparison (exp, mode, op0, op1)
11189 enum machine_mode mode;
11191 enum rtx_code reversed_code = combine_reversed_comparison_code (exp);
11192 if (reversed_code == UNKNOWN)
11195 return gen_binary (reversed_code, mode, op0, op1);
11198 /* Utility function for following routine. Called when X is part of a value
11199 being stored into reg_last_set_value. Sets reg_last_set_table_tick
11200 for each register mentioned. Similar to mention_regs in cse.c */
11203 update_table_tick (x)
11206 enum rtx_code code = GET_CODE (x);
11207 const char *fmt = GET_RTX_FORMAT (code);
11212 unsigned int regno = REGNO (x);
11213 unsigned int endregno
11214 = regno + (regno < FIRST_PSEUDO_REGISTER
11215 ? HARD_REGNO_NREGS (regno, GET_MODE (x)) : 1);
11218 for (r = regno; r < endregno; r++)
11219 reg_last_set_table_tick[r] = label_tick;
11224 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
11225 /* Note that we can't have an "E" in values stored; see
11226 get_last_value_validate. */
11228 update_table_tick (XEXP (x, i));
11231 /* Record that REG is set to VALUE in insn INSN. If VALUE is zero, we
11232 are saying that the register is clobbered and we no longer know its
11233 value. If INSN is zero, don't update reg_last_set; this is only permitted
11234 with VALUE also zero and is used to invalidate the register. */
11237 record_value_for_reg (reg, insn, value)
11242 unsigned int regno = REGNO (reg);
11243 unsigned int endregno
11244 = regno + (regno < FIRST_PSEUDO_REGISTER
11245 ? HARD_REGNO_NREGS (regno, GET_MODE (reg)) : 1);
11248 /* If VALUE contains REG and we have a previous value for REG, substitute
11249 the previous value. */
11250 if (value && insn && reg_overlap_mentioned_p (reg, value))
11254 /* Set things up so get_last_value is allowed to see anything set up to
11256 subst_low_cuid = INSN_CUID (insn);
11257 tem = get_last_value (reg);
11259 /* If TEM is simply a binary operation with two CLOBBERs as operands,
11260 it isn't going to be useful and will take a lot of time to process,
11261 so just use the CLOBBER. */
11265 if ((GET_RTX_CLASS (GET_CODE (tem)) == '2'
11266 || GET_RTX_CLASS (GET_CODE (tem)) == 'c')
11267 && GET_CODE (XEXP (tem, 0)) == CLOBBER
11268 && GET_CODE (XEXP (tem, 1)) == CLOBBER)
11269 tem = XEXP (tem, 0);
11271 value = replace_rtx (copy_rtx (value), reg, tem);
11275 /* For each register modified, show we don't know its value, that
11276 we don't know about its bitwise content, that its value has been
11277 updated, and that we don't know the location of the death of the
11279 for (i = regno; i < endregno; i++)
11282 reg_last_set[i] = insn;
11284 reg_last_set_value[i] = 0;
11285 reg_last_set_mode[i] = 0;
11286 reg_last_set_nonzero_bits[i] = 0;
11287 reg_last_set_sign_bit_copies[i] = 0;
11288 reg_last_death[i] = 0;
11291 /* Mark registers that are being referenced in this value. */
11293 update_table_tick (value);
11295 /* Now update the status of each register being set.
11296 If someone is using this register in this block, set this register
11297 to invalid since we will get confused between the two lives in this
11298 basic block. This makes using this register always invalid. In cse, we
11299 scan the table to invalidate all entries using this register, but this
11300 is too much work for us. */
11302 for (i = regno; i < endregno; i++)
11304 reg_last_set_label[i] = label_tick;
11305 if (value && reg_last_set_table_tick[i] == label_tick)
11306 reg_last_set_invalid[i] = 1;
11308 reg_last_set_invalid[i] = 0;
11311 /* The value being assigned might refer to X (like in "x++;"). In that
11312 case, we must replace it with (clobber (const_int 0)) to prevent
11314 if (value && ! get_last_value_validate (&value, insn,
11315 reg_last_set_label[regno], 0))
11317 value = copy_rtx (value);
11318 if (! get_last_value_validate (&value, insn,
11319 reg_last_set_label[regno], 1))
11323 /* For the main register being modified, update the value, the mode, the
11324 nonzero bits, and the number of sign bit copies. */
11326 reg_last_set_value[regno] = value;
11330 enum machine_mode mode = GET_MODE (reg);
11331 subst_low_cuid = INSN_CUID (insn);
11332 reg_last_set_mode[regno] = mode;
11333 if (GET_MODE_CLASS (mode) == MODE_INT
11334 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
11335 mode = nonzero_bits_mode;
11336 reg_last_set_nonzero_bits[regno] = nonzero_bits (value, mode);
11337 reg_last_set_sign_bit_copies[regno]
11338 = num_sign_bit_copies (value, GET_MODE (reg));
11342 /* Called via note_stores from record_dead_and_set_regs to handle one
11343 SET or CLOBBER in an insn. DATA is the instruction in which the
11344 set is occurring. */
11347 record_dead_and_set_regs_1 (dest, setter, data)
11351 rtx record_dead_insn = (rtx) data;
11353 if (GET_CODE (dest) == SUBREG)
11354 dest = SUBREG_REG (dest);
11356 if (GET_CODE (dest) == REG)
11358 /* If we are setting the whole register, we know its value. Otherwise
11359 show that we don't know the value. We can handle SUBREG in
11361 if (GET_CODE (setter) == SET && dest == SET_DEST (setter))
11362 record_value_for_reg (dest, record_dead_insn, SET_SRC (setter));
11363 else if (GET_CODE (setter) == SET
11364 && GET_CODE (SET_DEST (setter)) == SUBREG
11365 && SUBREG_REG (SET_DEST (setter)) == dest
11366 && GET_MODE_BITSIZE (GET_MODE (dest)) <= BITS_PER_WORD
11367 && subreg_lowpart_p (SET_DEST (setter)))
11368 record_value_for_reg (dest, record_dead_insn,
11369 gen_lowpart_for_combine (GET_MODE (dest),
11370 SET_SRC (setter)));
11372 record_value_for_reg (dest, record_dead_insn, NULL_RTX);
11374 else if (GET_CODE (dest) == MEM
11375 /* Ignore pushes, they clobber nothing. */
11376 && ! push_operand (dest, GET_MODE (dest)))
11377 mem_last_set = INSN_CUID (record_dead_insn);
11380 /* Update the records of when each REG was most recently set or killed
11381 for the things done by INSN. This is the last thing done in processing
11382 INSN in the combiner loop.
11384 We update reg_last_set, reg_last_set_value, reg_last_set_mode,
11385 reg_last_set_nonzero_bits, reg_last_set_sign_bit_copies, reg_last_death,
11386 and also the similar information mem_last_set (which insn most recently
11387 modified memory) and last_call_cuid (which insn was the most recent
11388 subroutine call). */
11391 record_dead_and_set_regs (insn)
11397 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
11399 if (REG_NOTE_KIND (link) == REG_DEAD
11400 && GET_CODE (XEXP (link, 0)) == REG)
11402 unsigned int regno = REGNO (XEXP (link, 0));
11403 unsigned int endregno
11404 = regno + (regno < FIRST_PSEUDO_REGISTER
11405 ? HARD_REGNO_NREGS (regno, GET_MODE (XEXP (link, 0)))
11408 for (i = regno; i < endregno; i++)
11409 reg_last_death[i] = insn;
11411 else if (REG_NOTE_KIND (link) == REG_INC)
11412 record_value_for_reg (XEXP (link, 0), insn, NULL_RTX);
11415 if (GET_CODE (insn) == CALL_INSN)
11417 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
11418 if (TEST_HARD_REG_BIT (regs_invalidated_by_call, i))
11420 reg_last_set_value[i] = 0;
11421 reg_last_set_mode[i] = 0;
11422 reg_last_set_nonzero_bits[i] = 0;
11423 reg_last_set_sign_bit_copies[i] = 0;
11424 reg_last_death[i] = 0;
11427 last_call_cuid = mem_last_set = INSN_CUID (insn);
11429 /* Don't bother recording what this insn does. It might set the
11430 return value register, but we can't combine into a call
11431 pattern anyway, so there's no point trying (and it may cause
11432 a crash, if e.g. we wind up asking for last_set_value of a
11433 SUBREG of the return value register). */
11437 note_stores (PATTERN (insn), record_dead_and_set_regs_1, insn);
11440 /* If a SUBREG has the promoted bit set, it is in fact a property of the
11441 register present in the SUBREG, so for each such SUBREG go back and
11442 adjust nonzero and sign bit information of the registers that are
11443 known to have some zero/sign bits set.
11445 This is needed because when combine blows the SUBREGs away, the
11446 information on zero/sign bits is lost and further combines can be
11447 missed because of that. */
11450 record_promoted_value (insn, subreg)
11455 unsigned int regno = REGNO (SUBREG_REG (subreg));
11456 enum machine_mode mode = GET_MODE (subreg);
11458 if (GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT)
11461 for (links = LOG_LINKS (insn); links;)
11463 insn = XEXP (links, 0);
11464 set = single_set (insn);
11466 if (! set || GET_CODE (SET_DEST (set)) != REG
11467 || REGNO (SET_DEST (set)) != regno
11468 || GET_MODE (SET_DEST (set)) != GET_MODE (SUBREG_REG (subreg)))
11470 links = XEXP (links, 1);
11474 if (reg_last_set[regno] == insn)
11476 if (SUBREG_PROMOTED_UNSIGNED_P (subreg) > 0)
11477 reg_last_set_nonzero_bits[regno] &= GET_MODE_MASK (mode);
11480 if (GET_CODE (SET_SRC (set)) == REG)
11482 regno = REGNO (SET_SRC (set));
11483 links = LOG_LINKS (insn);
11490 /* Scan X for promoted SUBREGs. For each one found,
11491 note what it implies to the registers used in it. */
11494 check_promoted_subreg (insn, x)
11498 if (GET_CODE (x) == SUBREG && SUBREG_PROMOTED_VAR_P (x)
11499 && GET_CODE (SUBREG_REG (x)) == REG)
11500 record_promoted_value (insn, x);
11503 const char *format = GET_RTX_FORMAT (GET_CODE (x));
11506 for (i = 0; i < GET_RTX_LENGTH (GET_CODE (x)); i++)
11510 check_promoted_subreg (insn, XEXP (x, i));
11514 if (XVEC (x, i) != 0)
11515 for (j = 0; j < XVECLEN (x, i); j++)
11516 check_promoted_subreg (insn, XVECEXP (x, i, j));
11522 /* Utility routine for the following function. Verify that all the registers
11523 mentioned in *LOC are valid when *LOC was part of a value set when
11524 label_tick == TICK. Return 0 if some are not.
11526 If REPLACE is non-zero, replace the invalid reference with
11527 (clobber (const_int 0)) and return 1. This replacement is useful because
11528 we often can get useful information about the form of a value (e.g., if
11529 it was produced by a shift that always produces -1 or 0) even though
11530 we don't know exactly what registers it was produced from. */
11533 get_last_value_validate (loc, insn, tick, replace)
11540 const char *fmt = GET_RTX_FORMAT (GET_CODE (x));
11541 int len = GET_RTX_LENGTH (GET_CODE (x));
11544 if (GET_CODE (x) == REG)
11546 unsigned int regno = REGNO (x);
11547 unsigned int endregno
11548 = regno + (regno < FIRST_PSEUDO_REGISTER
11549 ? HARD_REGNO_NREGS (regno, GET_MODE (x)) : 1);
11552 for (j = regno; j < endregno; j++)
11553 if (reg_last_set_invalid[j]
11554 /* If this is a pseudo-register that was only set once and not
11555 live at the beginning of the function, it is always valid. */
11556 || (! (regno >= FIRST_PSEUDO_REGISTER
11557 && REG_N_SETS (regno) == 1
11558 && (! REGNO_REG_SET_P
11559 (ENTRY_BLOCK_PTR->next_bb->global_live_at_start, regno)))
11560 && reg_last_set_label[j] > tick))
11563 *loc = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
11569 /* If this is a memory reference, make sure that there were
11570 no stores after it that might have clobbered the value. We don't
11571 have alias info, so we assume any store invalidates it. */
11572 else if (GET_CODE (x) == MEM && ! RTX_UNCHANGING_P (x)
11573 && INSN_CUID (insn) <= mem_last_set)
11576 *loc = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
11580 for (i = 0; i < len; i++)
11582 && get_last_value_validate (&XEXP (x, i), insn, tick, replace) == 0)
11583 /* Don't bother with these. They shouldn't occur anyway. */
11587 /* If we haven't found a reason for it to be invalid, it is valid. */
11591 /* Get the last value assigned to X, if known. Some registers
11592 in the value may be replaced with (clobber (const_int 0)) if their value
11593 is known longer known reliably. */
11599 unsigned int regno;
11602 /* If this is a non-paradoxical SUBREG, get the value of its operand and
11603 then convert it to the desired mode. If this is a paradoxical SUBREG,
11604 we cannot predict what values the "extra" bits might have. */
11605 if (GET_CODE (x) == SUBREG
11606 && subreg_lowpart_p (x)
11607 && (GET_MODE_SIZE (GET_MODE (x))
11608 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
11609 && (value = get_last_value (SUBREG_REG (x))) != 0)
11610 return gen_lowpart_for_combine (GET_MODE (x), value);
11612 if (GET_CODE (x) != REG)
11616 value = reg_last_set_value[regno];
11618 /* If we don't have a value, or if it isn't for this basic block and
11619 it's either a hard register, set more than once, or it's a live
11620 at the beginning of the function, return 0.
11622 Because if it's not live at the beginning of the function then the reg
11623 is always set before being used (is never used without being set).
11624 And, if it's set only once, and it's always set before use, then all
11625 uses must have the same last value, even if it's not from this basic
11629 || (reg_last_set_label[regno] != label_tick
11630 && (regno < FIRST_PSEUDO_REGISTER
11631 || REG_N_SETS (regno) != 1
11632 || (REGNO_REG_SET_P
11633 (ENTRY_BLOCK_PTR->next_bb->global_live_at_start, regno)))))
11636 /* If the value was set in a later insn than the ones we are processing,
11637 we can't use it even if the register was only set once. */
11638 if (INSN_CUID (reg_last_set[regno]) >= subst_low_cuid)
11641 /* If the value has all its registers valid, return it. */
11642 if (get_last_value_validate (&value, reg_last_set[regno],
11643 reg_last_set_label[regno], 0))
11646 /* Otherwise, make a copy and replace any invalid register with
11647 (clobber (const_int 0)). If that fails for some reason, return 0. */
11649 value = copy_rtx (value);
11650 if (get_last_value_validate (&value, reg_last_set[regno],
11651 reg_last_set_label[regno], 1))
11657 /* Return nonzero if expression X refers to a REG or to memory
11658 that is set in an instruction more recent than FROM_CUID. */
11661 use_crosses_set_p (x, from_cuid)
11667 enum rtx_code code = GET_CODE (x);
11671 unsigned int regno = REGNO (x);
11672 unsigned endreg = regno + (regno < FIRST_PSEUDO_REGISTER
11673 ? HARD_REGNO_NREGS (regno, GET_MODE (x)) : 1);
11675 #ifdef PUSH_ROUNDING
11676 /* Don't allow uses of the stack pointer to be moved,
11677 because we don't know whether the move crosses a push insn. */
11678 if (regno == STACK_POINTER_REGNUM && PUSH_ARGS)
11681 for (; regno < endreg; regno++)
11682 if (reg_last_set[regno]
11683 && INSN_CUID (reg_last_set[regno]) > from_cuid)
11688 if (code == MEM && mem_last_set > from_cuid)
11691 fmt = GET_RTX_FORMAT (code);
11693 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
11698 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
11699 if (use_crosses_set_p (XVECEXP (x, i, j), from_cuid))
11702 else if (fmt[i] == 'e'
11703 && use_crosses_set_p (XEXP (x, i), from_cuid))
11709 /* Define three variables used for communication between the following
11712 static unsigned int reg_dead_regno, reg_dead_endregno;
11713 static int reg_dead_flag;
11715 /* Function called via note_stores from reg_dead_at_p.
11717 If DEST is within [reg_dead_regno, reg_dead_endregno), set
11718 reg_dead_flag to 1 if X is a CLOBBER and to -1 it is a SET. */
11721 reg_dead_at_p_1 (dest, x, data)
11724 void *data ATTRIBUTE_UNUSED;
11726 unsigned int regno, endregno;
11728 if (GET_CODE (dest) != REG)
11731 regno = REGNO (dest);
11732 endregno = regno + (regno < FIRST_PSEUDO_REGISTER
11733 ? HARD_REGNO_NREGS (regno, GET_MODE (dest)) : 1);
11735 if (reg_dead_endregno > regno && reg_dead_regno < endregno)
11736 reg_dead_flag = (GET_CODE (x) == CLOBBER) ? 1 : -1;
11739 /* Return non-zero if REG is known to be dead at INSN.
11741 We scan backwards from INSN. If we hit a REG_DEAD note or a CLOBBER
11742 referencing REG, it is dead. If we hit a SET referencing REG, it is
11743 live. Otherwise, see if it is live or dead at the start of the basic
11744 block we are in. Hard regs marked as being live in NEWPAT_USED_REGS
11745 must be assumed to be always live. */
11748 reg_dead_at_p (reg, insn)
11755 /* Set variables for reg_dead_at_p_1. */
11756 reg_dead_regno = REGNO (reg);
11757 reg_dead_endregno = reg_dead_regno + (reg_dead_regno < FIRST_PSEUDO_REGISTER
11758 ? HARD_REGNO_NREGS (reg_dead_regno,
11764 /* Check that reg isn't mentioned in NEWPAT_USED_REGS. */
11765 if (reg_dead_regno < FIRST_PSEUDO_REGISTER)
11767 for (i = reg_dead_regno; i < reg_dead_endregno; i++)
11768 if (TEST_HARD_REG_BIT (newpat_used_regs, i))
11772 /* Scan backwards until we find a REG_DEAD note, SET, CLOBBER, label, or
11773 beginning of function. */
11774 for (; insn && GET_CODE (insn) != CODE_LABEL && GET_CODE (insn) != BARRIER;
11775 insn = prev_nonnote_insn (insn))
11777 note_stores (PATTERN (insn), reg_dead_at_p_1, NULL);
11779 return reg_dead_flag == 1 ? 1 : 0;
11781 if (find_regno_note (insn, REG_DEAD, reg_dead_regno))
11785 /* Get the basic block that we were in. */
11787 block = ENTRY_BLOCK_PTR->next_bb;
11790 FOR_EACH_BB (block)
11791 if (insn == block->head)
11794 if (block == EXIT_BLOCK_PTR)
11798 for (i = reg_dead_regno; i < reg_dead_endregno; i++)
11799 if (REGNO_REG_SET_P (block->global_live_at_start, i))
11805 /* Note hard registers in X that are used. This code is similar to
11806 that in flow.c, but much simpler since we don't care about pseudos. */
11809 mark_used_regs_combine (x)
11812 RTX_CODE code = GET_CODE (x);
11813 unsigned int regno;
11826 case ADDR_DIFF_VEC:
11829 /* CC0 must die in the insn after it is set, so we don't need to take
11830 special note of it here. */
11836 /* If we are clobbering a MEM, mark any hard registers inside the
11837 address as used. */
11838 if (GET_CODE (XEXP (x, 0)) == MEM)
11839 mark_used_regs_combine (XEXP (XEXP (x, 0), 0));
11844 /* A hard reg in a wide mode may really be multiple registers.
11845 If so, mark all of them just like the first. */
11846 if (regno < FIRST_PSEUDO_REGISTER)
11848 unsigned int endregno, r;
11850 /* None of this applies to the stack, frame or arg pointers */
11851 if (regno == STACK_POINTER_REGNUM
11852 #if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM
11853 || regno == HARD_FRAME_POINTER_REGNUM
11855 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
11856 || (regno == ARG_POINTER_REGNUM && fixed_regs[regno])
11858 || regno == FRAME_POINTER_REGNUM)
11861 endregno = regno + HARD_REGNO_NREGS (regno, GET_MODE (x));
11862 for (r = regno; r < endregno; r++)
11863 SET_HARD_REG_BIT (newpat_used_regs, r);
11869 /* If setting a MEM, or a SUBREG of a MEM, then note any hard regs in
11871 rtx testreg = SET_DEST (x);
11873 while (GET_CODE (testreg) == SUBREG
11874 || GET_CODE (testreg) == ZERO_EXTRACT
11875 || GET_CODE (testreg) == SIGN_EXTRACT
11876 || GET_CODE (testreg) == STRICT_LOW_PART)
11877 testreg = XEXP (testreg, 0);
11879 if (GET_CODE (testreg) == MEM)
11880 mark_used_regs_combine (XEXP (testreg, 0));
11882 mark_used_regs_combine (SET_SRC (x));
11890 /* Recursively scan the operands of this expression. */
11893 const char *fmt = GET_RTX_FORMAT (code);
11895 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
11898 mark_used_regs_combine (XEXP (x, i));
11899 else if (fmt[i] == 'E')
11903 for (j = 0; j < XVECLEN (x, i); j++)
11904 mark_used_regs_combine (XVECEXP (x, i, j));
11910 /* Remove register number REGNO from the dead registers list of INSN.
11912 Return the note used to record the death, if there was one. */
11915 remove_death (regno, insn)
11916 unsigned int regno;
11919 rtx note = find_regno_note (insn, REG_DEAD, regno);
11923 REG_N_DEATHS (regno)--;
11924 remove_note (insn, note);
11930 /* For each register (hardware or pseudo) used within expression X, if its
11931 death is in an instruction with cuid between FROM_CUID (inclusive) and
11932 TO_INSN (exclusive), put a REG_DEAD note for that register in the
11933 list headed by PNOTES.
11935 That said, don't move registers killed by maybe_kill_insn.
11937 This is done when X is being merged by combination into TO_INSN. These
11938 notes will then be distributed as needed. */
11941 move_deaths (x, maybe_kill_insn, from_cuid, to_insn, pnotes)
11943 rtx maybe_kill_insn;
11950 enum rtx_code code = GET_CODE (x);
11954 unsigned int regno = REGNO (x);
11955 rtx where_dead = reg_last_death[regno];
11956 rtx before_dead, after_dead;
11958 /* Don't move the register if it gets killed in between from and to */
11959 if (maybe_kill_insn && reg_set_p (x, maybe_kill_insn)
11960 && ! reg_referenced_p (x, maybe_kill_insn))
11963 /* WHERE_DEAD could be a USE insn made by combine, so first we
11964 make sure that we have insns with valid INSN_CUID values. */
11965 before_dead = where_dead;
11966 while (before_dead && INSN_UID (before_dead) > max_uid_cuid)
11967 before_dead = PREV_INSN (before_dead);
11969 after_dead = where_dead;
11970 while (after_dead && INSN_UID (after_dead) > max_uid_cuid)
11971 after_dead = NEXT_INSN (after_dead);
11973 if (before_dead && after_dead
11974 && INSN_CUID (before_dead) >= from_cuid
11975 && (INSN_CUID (after_dead) < INSN_CUID (to_insn)
11976 || (where_dead != after_dead
11977 && INSN_CUID (after_dead) == INSN_CUID (to_insn))))
11979 rtx note = remove_death (regno, where_dead);
11981 /* It is possible for the call above to return 0. This can occur
11982 when reg_last_death points to I2 or I1 that we combined with.
11983 In that case make a new note.
11985 We must also check for the case where X is a hard register
11986 and NOTE is a death note for a range of hard registers
11987 including X. In that case, we must put REG_DEAD notes for
11988 the remaining registers in place of NOTE. */
11990 if (note != 0 && regno < FIRST_PSEUDO_REGISTER
11991 && (GET_MODE_SIZE (GET_MODE (XEXP (note, 0)))
11992 > GET_MODE_SIZE (GET_MODE (x))))
11994 unsigned int deadregno = REGNO (XEXP (note, 0));
11995 unsigned int deadend
11996 = (deadregno + HARD_REGNO_NREGS (deadregno,
11997 GET_MODE (XEXP (note, 0))));
11998 unsigned int ourend
11999 = regno + HARD_REGNO_NREGS (regno, GET_MODE (x));
12002 for (i = deadregno; i < deadend; i++)
12003 if (i < regno || i >= ourend)
12004 REG_NOTES (where_dead)
12005 = gen_rtx_EXPR_LIST (REG_DEAD,
12007 REG_NOTES (where_dead));
12010 /* If we didn't find any note, or if we found a REG_DEAD note that
12011 covers only part of the given reg, and we have a multi-reg hard
12012 register, then to be safe we must check for REG_DEAD notes
12013 for each register other than the first. They could have
12014 their own REG_DEAD notes lying around. */
12015 else if ((note == 0
12017 && (GET_MODE_SIZE (GET_MODE (XEXP (note, 0)))
12018 < GET_MODE_SIZE (GET_MODE (x)))))
12019 && regno < FIRST_PSEUDO_REGISTER
12020 && HARD_REGNO_NREGS (regno, GET_MODE (x)) > 1)
12022 unsigned int ourend
12023 = regno + HARD_REGNO_NREGS (regno, GET_MODE (x));
12024 unsigned int i, offset;
12028 offset = HARD_REGNO_NREGS (regno, GET_MODE (XEXP (note, 0)));
12032 for (i = regno + offset; i < ourend; i++)
12033 move_deaths (regno_reg_rtx[i],
12034 maybe_kill_insn, from_cuid, to_insn, &oldnotes);
12037 if (note != 0 && GET_MODE (XEXP (note, 0)) == GET_MODE (x))
12039 XEXP (note, 1) = *pnotes;
12043 *pnotes = gen_rtx_EXPR_LIST (REG_DEAD, x, *pnotes);
12045 REG_N_DEATHS (regno)++;
12051 else if (GET_CODE (x) == SET)
12053 rtx dest = SET_DEST (x);
12055 move_deaths (SET_SRC (x), maybe_kill_insn, from_cuid, to_insn, pnotes);
12057 /* In the case of a ZERO_EXTRACT, a STRICT_LOW_PART, or a SUBREG
12058 that accesses one word of a multi-word item, some
12059 piece of everything register in the expression is used by
12060 this insn, so remove any old death. */
12061 /* ??? So why do we test for equality of the sizes? */
12063 if (GET_CODE (dest) == ZERO_EXTRACT
12064 || GET_CODE (dest) == STRICT_LOW_PART
12065 || (GET_CODE (dest) == SUBREG
12066 && (((GET_MODE_SIZE (GET_MODE (dest))
12067 + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
12068 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (dest)))
12069 + UNITS_PER_WORD - 1) / UNITS_PER_WORD))))
12071 move_deaths (dest, maybe_kill_insn, from_cuid, to_insn, pnotes);
12075 /* If this is some other SUBREG, we know it replaces the entire
12076 value, so use that as the destination. */
12077 if (GET_CODE (dest) == SUBREG)
12078 dest = SUBREG_REG (dest);
12080 /* If this is a MEM, adjust deaths of anything used in the address.
12081 For a REG (the only other possibility), the entire value is
12082 being replaced so the old value is not used in this insn. */
12084 if (GET_CODE (dest) == MEM)
12085 move_deaths (XEXP (dest, 0), maybe_kill_insn, from_cuid,
12090 else if (GET_CODE (x) == CLOBBER)
12093 len = GET_RTX_LENGTH (code);
12094 fmt = GET_RTX_FORMAT (code);
12096 for (i = 0; i < len; i++)
12101 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
12102 move_deaths (XVECEXP (x, i, j), maybe_kill_insn, from_cuid,
12105 else if (fmt[i] == 'e')
12106 move_deaths (XEXP (x, i), maybe_kill_insn, from_cuid, to_insn, pnotes);
12110 /* Return 1 if X is the target of a bit-field assignment in BODY, the
12111 pattern of an insn. X must be a REG. */
12114 reg_bitfield_target_p (x, body)
12120 if (GET_CODE (body) == SET)
12122 rtx dest = SET_DEST (body);
12124 unsigned int regno, tregno, endregno, endtregno;
12126 if (GET_CODE (dest) == ZERO_EXTRACT)
12127 target = XEXP (dest, 0);
12128 else if (GET_CODE (dest) == STRICT_LOW_PART)
12129 target = SUBREG_REG (XEXP (dest, 0));
12133 if (GET_CODE (target) == SUBREG)
12134 target = SUBREG_REG (target);
12136 if (GET_CODE (target) != REG)
12139 tregno = REGNO (target), regno = REGNO (x);
12140 if (tregno >= FIRST_PSEUDO_REGISTER || regno >= FIRST_PSEUDO_REGISTER)
12141 return target == x;
12143 endtregno = tregno + HARD_REGNO_NREGS (tregno, GET_MODE (target));
12144 endregno = regno + HARD_REGNO_NREGS (regno, GET_MODE (x));
12146 return endregno > tregno && regno < endtregno;
12149 else if (GET_CODE (body) == PARALLEL)
12150 for (i = XVECLEN (body, 0) - 1; i >= 0; i--)
12151 if (reg_bitfield_target_p (x, XVECEXP (body, 0, i)))
12157 /* Given a chain of REG_NOTES originally from FROM_INSN, try to place them
12158 as appropriate. I3 and I2 are the insns resulting from the combination
12159 insns including FROM (I2 may be zero).
12161 ELIM_I2 and ELIM_I1 are either zero or registers that we know will
12162 not need REG_DEAD notes because they are being substituted for. This
12163 saves searching in the most common cases.
12165 Each note in the list is either ignored or placed on some insns, depending
12166 on the type of note. */
12169 distribute_notes (notes, from_insn, i3, i2, elim_i2, elim_i1)
12173 rtx elim_i2, elim_i1;
12175 rtx note, next_note;
12178 for (note = notes; note; note = next_note)
12180 rtx place = 0, place2 = 0;
12182 /* If this NOTE references a pseudo register, ensure it references
12183 the latest copy of that register. */
12184 if (XEXP (note, 0) && GET_CODE (XEXP (note, 0)) == REG
12185 && REGNO (XEXP (note, 0)) >= FIRST_PSEUDO_REGISTER)
12186 XEXP (note, 0) = regno_reg_rtx[REGNO (XEXP (note, 0))];
12188 next_note = XEXP (note, 1);
12189 switch (REG_NOTE_KIND (note))
12193 case REG_EXEC_COUNT:
12194 /* Doesn't matter much where we put this, as long as it's somewhere.
12195 It is preferable to keep these notes on branches, which is most
12196 likely to be i3. */
12200 case REG_VTABLE_REF:
12201 /* ??? Should remain with *a particular* memory load. Given the
12202 nature of vtable data, the last insn seems relatively safe. */
12206 case REG_NON_LOCAL_GOTO:
12207 if (GET_CODE (i3) == JUMP_INSN)
12209 else if (i2 && GET_CODE (i2) == JUMP_INSN)
12215 case REG_EH_REGION:
12216 /* These notes must remain with the call or trapping instruction. */
12217 if (GET_CODE (i3) == CALL_INSN)
12219 else if (i2 && GET_CODE (i2) == CALL_INSN)
12221 else if (flag_non_call_exceptions)
12223 if (may_trap_p (i3))
12225 else if (i2 && may_trap_p (i2))
12227 /* ??? Otherwise assume we've combined things such that we
12228 can now prove that the instructions can't trap. Drop the
12229 note in this case. */
12237 /* These notes must remain with the call. It should not be
12238 possible for both I2 and I3 to be a call. */
12239 if (GET_CODE (i3) == CALL_INSN)
12241 else if (i2 && GET_CODE (i2) == CALL_INSN)
12248 /* Any clobbers for i3 may still exist, and so we must process
12249 REG_UNUSED notes from that insn.
12251 Any clobbers from i2 or i1 can only exist if they were added by
12252 recog_for_combine. In that case, recog_for_combine created the
12253 necessary REG_UNUSED notes. Trying to keep any original
12254 REG_UNUSED notes from these insns can cause incorrect output
12255 if it is for the same register as the original i3 dest.
12256 In that case, we will notice that the register is set in i3,
12257 and then add a REG_UNUSED note for the destination of i3, which
12258 is wrong. However, it is possible to have REG_UNUSED notes from
12259 i2 or i1 for register which were both used and clobbered, so
12260 we keep notes from i2 or i1 if they will turn into REG_DEAD
12263 /* If this register is set or clobbered in I3, put the note there
12264 unless there is one already. */
12265 if (reg_set_p (XEXP (note, 0), PATTERN (i3)))
12267 if (from_insn != i3)
12270 if (! (GET_CODE (XEXP (note, 0)) == REG
12271 ? find_regno_note (i3, REG_UNUSED, REGNO (XEXP (note, 0)))
12272 : find_reg_note (i3, REG_UNUSED, XEXP (note, 0))))
12275 /* Otherwise, if this register is used by I3, then this register
12276 now dies here, so we must put a REG_DEAD note here unless there
12278 else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3))
12279 && ! (GET_CODE (XEXP (note, 0)) == REG
12280 ? find_regno_note (i3, REG_DEAD,
12281 REGNO (XEXP (note, 0)))
12282 : find_reg_note (i3, REG_DEAD, XEXP (note, 0))))
12284 PUT_REG_NOTE_KIND (note, REG_DEAD);
12292 /* These notes say something about results of an insn. We can
12293 only support them if they used to be on I3 in which case they
12294 remain on I3. Otherwise they are ignored.
12296 If the note refers to an expression that is not a constant, we
12297 must also ignore the note since we cannot tell whether the
12298 equivalence is still true. It might be possible to do
12299 slightly better than this (we only have a problem if I2DEST
12300 or I1DEST is present in the expression), but it doesn't
12301 seem worth the trouble. */
12303 if (from_insn == i3
12304 && (XEXP (note, 0) == 0 || CONSTANT_P (XEXP (note, 0))))
12309 case REG_NO_CONFLICT:
12310 /* These notes say something about how a register is used. They must
12311 be present on any use of the register in I2 or I3. */
12312 if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3)))
12315 if (i2 && reg_mentioned_p (XEXP (note, 0), PATTERN (i2)))
12325 /* This can show up in several ways -- either directly in the
12326 pattern, or hidden off in the constant pool with (or without?)
12327 a REG_EQUAL note. */
12328 /* ??? Ignore the without-reg_equal-note problem for now. */
12329 if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3))
12330 || ((tem = find_reg_note (i3, REG_EQUAL, NULL_RTX))
12331 && GET_CODE (XEXP (tem, 0)) == LABEL_REF
12332 && XEXP (XEXP (tem, 0), 0) == XEXP (note, 0)))
12336 && (reg_mentioned_p (XEXP (note, 0), PATTERN (i2))
12337 || ((tem = find_reg_note (i2, REG_EQUAL, NULL_RTX))
12338 && GET_CODE (XEXP (tem, 0)) == LABEL_REF
12339 && XEXP (XEXP (tem, 0), 0) == XEXP (note, 0))))
12347 /* Don't attach REG_LABEL note to a JUMP_INSN which has
12348 JUMP_LABEL already. Instead, decrement LABEL_NUSES. */
12349 if (place && GET_CODE (place) == JUMP_INSN && JUMP_LABEL (place))
12351 if (JUMP_LABEL (place) != XEXP (note, 0))
12353 if (GET_CODE (JUMP_LABEL (place)) == CODE_LABEL)
12354 LABEL_NUSES (JUMP_LABEL (place))--;
12357 if (place2 && GET_CODE (place2) == JUMP_INSN && JUMP_LABEL (place2))
12359 if (JUMP_LABEL (place2) != XEXP (note, 0))
12361 if (GET_CODE (JUMP_LABEL (place2)) == CODE_LABEL)
12362 LABEL_NUSES (JUMP_LABEL (place2))--;
12369 /* These notes say something about the value of a register prior
12370 to the execution of an insn. It is too much trouble to see
12371 if the note is still correct in all situations. It is better
12372 to simply delete it. */
12376 /* If the insn previously containing this note still exists,
12377 put it back where it was. Otherwise move it to the previous
12378 insn. Adjust the corresponding REG_LIBCALL note. */
12379 if (GET_CODE (from_insn) != NOTE)
12383 tem = find_reg_note (XEXP (note, 0), REG_LIBCALL, NULL_RTX);
12384 place = prev_real_insn (from_insn);
12386 XEXP (tem, 0) = place;
12387 /* If we're deleting the last remaining instruction of a
12388 libcall sequence, don't add the notes. */
12389 else if (XEXP (note, 0) == from_insn)
12395 /* This is handled similarly to REG_RETVAL. */
12396 if (GET_CODE (from_insn) != NOTE)
12400 tem = find_reg_note (XEXP (note, 0), REG_RETVAL, NULL_RTX);
12401 place = next_real_insn (from_insn);
12403 XEXP (tem, 0) = place;
12404 /* If we're deleting the last remaining instruction of a
12405 libcall sequence, don't add the notes. */
12406 else if (XEXP (note, 0) == from_insn)
12412 /* If the register is used as an input in I3, it dies there.
12413 Similarly for I2, if it is non-zero and adjacent to I3.
12415 If the register is not used as an input in either I3 or I2
12416 and it is not one of the registers we were supposed to eliminate,
12417 there are two possibilities. We might have a non-adjacent I2
12418 or we might have somehow eliminated an additional register
12419 from a computation. For example, we might have had A & B where
12420 we discover that B will always be zero. In this case we will
12421 eliminate the reference to A.
12423 In both cases, we must search to see if we can find a previous
12424 use of A and put the death note there. */
12427 && GET_CODE (from_insn) == CALL_INSN
12428 && find_reg_fusage (from_insn, USE, XEXP (note, 0)))
12430 else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3)))
12432 else if (i2 != 0 && next_nonnote_insn (i2) == i3
12433 && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
12436 if (rtx_equal_p (XEXP (note, 0), elim_i2)
12437 || rtx_equal_p (XEXP (note, 0), elim_i1))
12442 basic_block bb = this_basic_block;
12444 for (tem = PREV_INSN (i3); place == 0; tem = PREV_INSN (tem))
12446 if (! INSN_P (tem))
12448 if (tem == bb->head)
12453 /* If the register is being set at TEM, see if that is all
12454 TEM is doing. If so, delete TEM. Otherwise, make this
12455 into a REG_UNUSED note instead. */
12456 if (reg_set_p (XEXP (note, 0), PATTERN (tem)))
12458 rtx set = single_set (tem);
12459 rtx inner_dest = 0;
12461 rtx cc0_setter = NULL_RTX;
12465 for (inner_dest = SET_DEST (set);
12466 (GET_CODE (inner_dest) == STRICT_LOW_PART
12467 || GET_CODE (inner_dest) == SUBREG
12468 || GET_CODE (inner_dest) == ZERO_EXTRACT);
12469 inner_dest = XEXP (inner_dest, 0))
12472 /* Verify that it was the set, and not a clobber that
12473 modified the register.
12475 CC0 targets must be careful to maintain setter/user
12476 pairs. If we cannot delete the setter due to side
12477 effects, mark the user with an UNUSED note instead
12480 if (set != 0 && ! side_effects_p (SET_SRC (set))
12481 && rtx_equal_p (XEXP (note, 0), inner_dest)
12483 && (! reg_mentioned_p (cc0_rtx, SET_SRC (set))
12484 || ((cc0_setter = prev_cc0_setter (tem)) != NULL
12485 && sets_cc0_p (PATTERN (cc0_setter)) > 0))
12489 /* Move the notes and links of TEM elsewhere.
12490 This might delete other dead insns recursively.
12491 First set the pattern to something that won't use
12494 PATTERN (tem) = pc_rtx;
12496 distribute_notes (REG_NOTES (tem), tem, tem,
12497 NULL_RTX, NULL_RTX, NULL_RTX);
12498 distribute_links (LOG_LINKS (tem));
12500 PUT_CODE (tem, NOTE);
12501 NOTE_LINE_NUMBER (tem) = NOTE_INSN_DELETED;
12502 NOTE_SOURCE_FILE (tem) = 0;
12505 /* Delete the setter too. */
12508 PATTERN (cc0_setter) = pc_rtx;
12510 distribute_notes (REG_NOTES (cc0_setter),
12511 cc0_setter, cc0_setter,
12512 NULL_RTX, NULL_RTX, NULL_RTX);
12513 distribute_links (LOG_LINKS (cc0_setter));
12515 PUT_CODE (cc0_setter, NOTE);
12516 NOTE_LINE_NUMBER (cc0_setter)
12517 = NOTE_INSN_DELETED;
12518 NOTE_SOURCE_FILE (cc0_setter) = 0;
12522 /* If the register is both set and used here, put the
12523 REG_DEAD note here, but place a REG_UNUSED note
12524 here too unless there already is one. */
12525 else if (reg_referenced_p (XEXP (note, 0),
12530 if (! find_regno_note (tem, REG_UNUSED,
12531 REGNO (XEXP (note, 0))))
12533 = gen_rtx_EXPR_LIST (REG_UNUSED, XEXP (note, 0),
12538 PUT_REG_NOTE_KIND (note, REG_UNUSED);
12540 /* If there isn't already a REG_UNUSED note, put one
12542 if (! find_regno_note (tem, REG_UNUSED,
12543 REGNO (XEXP (note, 0))))
12548 else if (reg_referenced_p (XEXP (note, 0), PATTERN (tem))
12549 || (GET_CODE (tem) == CALL_INSN
12550 && find_reg_fusage (tem, USE, XEXP (note, 0))))
12554 /* If we are doing a 3->2 combination, and we have a
12555 register which formerly died in i3 and was not used
12556 by i2, which now no longer dies in i3 and is used in
12557 i2 but does not die in i2, and place is between i2
12558 and i3, then we may need to move a link from place to
12560 if (i2 && INSN_UID (place) <= max_uid_cuid
12561 && INSN_CUID (place) > INSN_CUID (i2)
12563 && INSN_CUID (from_insn) > INSN_CUID (i2)
12564 && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
12566 rtx links = LOG_LINKS (place);
12567 LOG_LINKS (place) = 0;
12568 distribute_links (links);
12573 if (tem == bb->head)
12577 /* We haven't found an insn for the death note and it
12578 is still a REG_DEAD note, but we have hit the beginning
12579 of the block. If the existing life info says the reg
12580 was dead, there's nothing left to do. Otherwise, we'll
12581 need to do a global life update after combine. */
12582 if (REG_NOTE_KIND (note) == REG_DEAD && place == 0
12583 && REGNO_REG_SET_P (bb->global_live_at_start,
12584 REGNO (XEXP (note, 0))))
12586 SET_BIT (refresh_blocks, this_basic_block->index);
12591 /* If the register is set or already dead at PLACE, we needn't do
12592 anything with this note if it is still a REG_DEAD note.
12593 We can here if it is set at all, not if is it totally replace,
12594 which is what `dead_or_set_p' checks, so also check for it being
12597 if (place && REG_NOTE_KIND (note) == REG_DEAD)
12599 unsigned int regno = REGNO (XEXP (note, 0));
12601 /* Similarly, if the instruction on which we want to place
12602 the note is a noop, we'll need do a global live update
12603 after we remove them in delete_noop_moves. */
12604 if (noop_move_p (place))
12606 SET_BIT (refresh_blocks, this_basic_block->index);
12610 if (dead_or_set_p (place, XEXP (note, 0))
12611 || reg_bitfield_target_p (XEXP (note, 0), PATTERN (place)))
12613 /* Unless the register previously died in PLACE, clear
12614 reg_last_death. [I no longer understand why this is
12616 if (reg_last_death[regno] != place)
12617 reg_last_death[regno] = 0;
12621 reg_last_death[regno] = place;
12623 /* If this is a death note for a hard reg that is occupying
12624 multiple registers, ensure that we are still using all
12625 parts of the object. If we find a piece of the object
12626 that is unused, we must arrange for an appropriate REG_DEAD
12627 note to be added for it. However, we can't just emit a USE
12628 and tag the note to it, since the register might actually
12629 be dead; so we recourse, and the recursive call then finds
12630 the previous insn that used this register. */
12632 if (place && regno < FIRST_PSEUDO_REGISTER
12633 && HARD_REGNO_NREGS (regno, GET_MODE (XEXP (note, 0))) > 1)
12635 unsigned int endregno
12636 = regno + HARD_REGNO_NREGS (regno,
12637 GET_MODE (XEXP (note, 0)));
12641 for (i = regno; i < endregno; i++)
12642 if ((! refers_to_regno_p (i, i + 1, PATTERN (place), 0)
12643 && ! find_regno_fusage (place, USE, i))
12644 || dead_or_set_regno_p (place, i))
12649 /* Put only REG_DEAD notes for pieces that are
12650 not already dead or set. */
12652 for (i = regno; i < endregno;
12653 i += HARD_REGNO_NREGS (i, reg_raw_mode[i]))
12655 rtx piece = regno_reg_rtx[i];
12656 basic_block bb = this_basic_block;
12658 if (! dead_or_set_p (place, piece)
12659 && ! reg_bitfield_target_p (piece,
12663 = gen_rtx_EXPR_LIST (REG_DEAD, piece, NULL_RTX);
12665 distribute_notes (new_note, place, place,
12666 NULL_RTX, NULL_RTX, NULL_RTX);
12668 else if (! refers_to_regno_p (i, i + 1,
12669 PATTERN (place), 0)
12670 && ! find_regno_fusage (place, USE, i))
12671 for (tem = PREV_INSN (place); ;
12672 tem = PREV_INSN (tem))
12674 if (! INSN_P (tem))
12676 if (tem == bb->head)
12678 SET_BIT (refresh_blocks,
12679 this_basic_block->index);
12685 if (dead_or_set_p (tem, piece)
12686 || reg_bitfield_target_p (piece,
12690 = gen_rtx_EXPR_LIST (REG_UNUSED, piece,
12705 /* Any other notes should not be present at this point in the
12712 XEXP (note, 1) = REG_NOTES (place);
12713 REG_NOTES (place) = note;
12715 else if ((REG_NOTE_KIND (note) == REG_DEAD
12716 || REG_NOTE_KIND (note) == REG_UNUSED)
12717 && GET_CODE (XEXP (note, 0)) == REG)
12718 REG_N_DEATHS (REGNO (XEXP (note, 0)))--;
12722 if ((REG_NOTE_KIND (note) == REG_DEAD
12723 || REG_NOTE_KIND (note) == REG_UNUSED)
12724 && GET_CODE (XEXP (note, 0)) == REG)
12725 REG_N_DEATHS (REGNO (XEXP (note, 0)))++;
12727 REG_NOTES (place2) = gen_rtx_fmt_ee (GET_CODE (note),
12728 REG_NOTE_KIND (note),
12730 REG_NOTES (place2));
12735 /* Similarly to above, distribute the LOG_LINKS that used to be present on
12736 I3, I2, and I1 to new locations. This is also called in one case to
12737 add a link pointing at I3 when I3's destination is changed. */
12740 distribute_links (links)
12743 rtx link, next_link;
12745 for (link = links; link; link = next_link)
12751 next_link = XEXP (link, 1);
12753 /* If the insn that this link points to is a NOTE or isn't a single
12754 set, ignore it. In the latter case, it isn't clear what we
12755 can do other than ignore the link, since we can't tell which
12756 register it was for. Such links wouldn't be used by combine
12759 It is not possible for the destination of the target of the link to
12760 have been changed by combine. The only potential of this is if we
12761 replace I3, I2, and I1 by I3 and I2. But in that case the
12762 destination of I2 also remains unchanged. */
12764 if (GET_CODE (XEXP (link, 0)) == NOTE
12765 || (set = single_set (XEXP (link, 0))) == 0)
12768 reg = SET_DEST (set);
12769 while (GET_CODE (reg) == SUBREG || GET_CODE (reg) == ZERO_EXTRACT
12770 || GET_CODE (reg) == SIGN_EXTRACT
12771 || GET_CODE (reg) == STRICT_LOW_PART)
12772 reg = XEXP (reg, 0);
12774 /* A LOG_LINK is defined as being placed on the first insn that uses
12775 a register and points to the insn that sets the register. Start
12776 searching at the next insn after the target of the link and stop
12777 when we reach a set of the register or the end of the basic block.
12779 Note that this correctly handles the link that used to point from
12780 I3 to I2. Also note that not much searching is typically done here
12781 since most links don't point very far away. */
12783 for (insn = NEXT_INSN (XEXP (link, 0));
12784 (insn && (this_basic_block->next_bb == EXIT_BLOCK_PTR
12785 || this_basic_block->next_bb->head != insn));
12786 insn = NEXT_INSN (insn))
12787 if (INSN_P (insn) && reg_overlap_mentioned_p (reg, PATTERN (insn)))
12789 if (reg_referenced_p (reg, PATTERN (insn)))
12793 else if (GET_CODE (insn) == CALL_INSN
12794 && find_reg_fusage (insn, USE, reg))
12800 /* If we found a place to put the link, place it there unless there
12801 is already a link to the same insn as LINK at that point. */
12807 for (link2 = LOG_LINKS (place); link2; link2 = XEXP (link2, 1))
12808 if (XEXP (link2, 0) == XEXP (link, 0))
12813 XEXP (link, 1) = LOG_LINKS (place);
12814 LOG_LINKS (place) = link;
12816 /* Set added_links_insn to the earliest insn we added a
12818 if (added_links_insn == 0
12819 || INSN_CUID (added_links_insn) > INSN_CUID (place))
12820 added_links_insn = place;
12826 /* Compute INSN_CUID for INSN, which is an insn made by combine. */
12832 while (insn != 0 && INSN_UID (insn) > max_uid_cuid
12833 && GET_CODE (insn) == INSN && GET_CODE (PATTERN (insn)) == USE)
12834 insn = NEXT_INSN (insn);
12836 if (INSN_UID (insn) > max_uid_cuid)
12839 return INSN_CUID (insn);
12843 dump_combine_stats (file)
12848 ";; Combiner statistics: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n\n",
12849 combine_attempts, combine_merges, combine_extras, combine_successes);
12853 dump_combine_total_stats (file)
12858 "\n;; Combiner totals: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n",
12859 total_attempts, total_merges, total_extras, total_successes);