change jpeg IPCores. startgen signal distribute into all module

[fpga-leon-mjpeg/leon-mjpeg.git] / grlib-gpl-1.0.22-b4095 / lib / kuri / mjpeg / huffmemcont.vhd

diff --git a/grlib-gpl-1.0.22-b4095/lib/kuri/mjpeg/huffmemcont.vhd b/grlib-gpl-1.0.22-b4095/lib/kuri/mjpeg/huffmemcont.vhd
index cb05470..356017b 100644 (file)
--- a/grlib-gpl-1.0.22-b4095/lib/kuri/mjpeg/huffmemcont.vhd
+++ b/grlib-gpl-1.0.22-b4095/lib/kuri/mjpeg/huffmemcont.vhd
@@ -54,7 +54,9 @@ entity huffmemcont is
       
       kaddq : in std_logic_vector(7 downto 0);
       krdq : in std_logic;
-      krddataq : out std_logic_vector(7 downto 0)
+      krddataq : out std_logic_vector(7 downto 0);
+      
+      startgen : in std_logic
    );
 end;
  
@@ -120,7 +122,7 @@ begin
     qram  : syncram generic map(tech => memtech, abits => 8, dbits => 8)
                 port map( clk, qaddress, qdatain, qdataout, qenable, qwrite);
     
-comb : process (r, rst, kstrobe1, kaddress1, kdata1, kready2, m0dataout, m1dataout, kstrobeq1, kdataq1, kaddq, krdq)
+comb : process (r, rst, kstrobe1, kaddress1, kdata1, kready2, m0dataout, m1dataout, kstrobeq1, kdataq1, kaddq, krdq, samp_fact, startgen)
       variable v : control_reg;   
       variable vkready1 : std_logic;
       variable verror : std_logic;
@@ -331,7 +333,7 @@ debug_bcountup <= bcountup;
 
 
 -- reset part
-   if rst = '0' then
+   if rst = '0' or startgen= '1' then
        v.swf := mem0;
        v.swb := mem0;
        v.mem0state := fill0;