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Merge branch freedesktop/master into otc-private/master
authorChad Versace <chad.versace@linux.intel.com>
Fri, 31 May 2013 02:41:05 +0000 (19:41 -0700)
committerChad Versace <chad.versace@linux.intel.com>
Fri, 31 May 2013 21:52:36 +0000 (14:52 -0700)
Topi's GL_OES_EGL_image_external patches and Anholt's miptree cleanups
conflicted nontrivially in {brw,gen7}_wm_surface_state.c

Conflicts:
    src/mesa/drivers/dri/i965/brw_clear.c
Anholt removed the 8x4 alignemtn restriction, and Tapani added
        a workaround below it.

    src/mesa/drivers/dri/i965/brw_wm_surface_state.c
    src/mesa/drivers/dri/i965/gen7_wm_surface_state.c
        Topi's GL_OES_EGL_image_external patches conflicted with Anholt's
        miptree cleanups.

    src/mesa/drivers/dri/intel/intel_mipmap_tree.c
    src/mesa/drivers/dri/intel/intel_mipmap_tree.h
        Trivial conflicts.

16 files changed:
1  2 
Android.mk
src/mesa/drivers/dri/i915/i915_state.c
src/mesa/drivers/dri/i965/Makefile.sources
src/mesa/drivers/dri/i965/brw_clear.c
src/mesa/drivers/dri/i965/brw_context.h
src/mesa/drivers/dri/i965/brw_fs.h
src/mesa/drivers/dri/i965/brw_fs_emit.cpp
src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
src/mesa/drivers/dri/i965/brw_state.h
src/mesa/drivers/dri/i965/brw_wm_surface_state.c
src/mesa/drivers/dri/i965/gen7_wm_surface_state.c
src/mesa/drivers/dri/intel/intel_extensions.c
src/mesa/drivers/dri/intel/intel_screen.c
src/mesa/drivers/dri/intel/intel_tex_image.c
src/mesa/main/extensions.c
src/mesa/main/version.c

diff --cc Android.mk
Simple merge
@@@ -59,9 -59,7 +59,8 @@@ i965_FILES = 
        brw_fs_fp.cpp \
        brw_fs_live_variables.cpp \
        brw_fs_reg_allocate.cpp \
-       brw_fs_schedule_instructions.cpp \
        brw_fs_vector_splitting.cpp \
 +      brw_fs_ext_texture.cpp \
        brw_fs_visitor.cpp \
        brw_gs.c \
        brw_gs_emit.c \
@@@ -128,27 -128,6 +128,14 @@@ brw_fast_clear_depth(struct gl_context 
        return false;
     }
  
-    /* The rendered area has to be 8x4 samples, not resolved pixels, so we look
-     * at the miptree slice dimensions instead of renderbuffer size.
-     */
-    if (mt->level[depth_irb->mt_level].width % 8 != 0 ||
-        mt->level[depth_irb->mt_level].height % 4 != 0) {
-       perf_debug("Failed to fast clear depth due to width/height %d,%d not "
-                  "being aligned to 8,4.  Possible 5%% performance win if "
-                  "avoided\n",
-                  mt->level[depth_irb->mt_level].width,
-                  mt->level[depth_irb->mt_level].height);
-       return false;
-    }
 +   /* check that colorbuffer depth equals to depthbuffer depth on IVB */
 +   if(intel->gen == 7) {
 +      struct gl_renderbuffer *rb = ctx->DrawBuffer->_ColorDrawBuffers[0];
 +      if (rb && _mesa_get_format_bytes(rb->Format) !=
 +                _mesa_get_format_bytes(intel_rb_format(depth_irb)))
 +         return false;
 +   }
 +
     uint32_t depth_clear_value;
     switch (mt->format) {
     case MESA_FORMAT_Z32_FLOAT_X24S8:
Simple merge
Simple merge
@@@ -854,37 -949,57 +949,38 @@@ brw_update_buffer_texture_surface(struc
  }
  
  static void
 -brw_update_texture_surface(struct gl_context *ctx,
 -                           unsigned unit,
 -                           uint32_t *binding_table,
 -                           unsigned surf_index)
 +brw_update_texture_component(struct brw_context *brw,
 +                             uint32_t *binding_table_slot,
 +                             const struct intel_mipmap_tree *mt,
 +                             unsigned width, unsigned height,
 +                             unsigned depth, unsigned stride,
 +                             GLuint target, GLuint tex_format,
-                              uint32_t offset, uint32_t levels)
++                             uint32_t offset, uint32_t levels,
++                             uint32_t first_level)
  {
 -   struct intel_context *intel = intel_context(ctx);
 -   struct brw_context *brw = brw_context(ctx);
 -   struct gl_texture_object *tObj = ctx->Texture.Unit[unit]._Current;
 -   struct intel_texture_object *intelObj = intel_texture_object(tObj);
 -   struct intel_mipmap_tree *mt = intelObj->mt;
 -   struct gl_texture_image *firstImage = tObj->Image[0][tObj->BaseLevel];
 -   struct gl_sampler_object *sampler = _mesa_get_samplerobj(ctx, unit);
 -   uint32_t *surf;
 -   int width, height, depth;
     uint32_t tile_x, tile_y;
-    const struct intel_region *region = mt->region;
 +   uint32_t *surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
 +                                    6 * 4, 32, binding_table_slot);
  
 -   if (tObj->Target == GL_TEXTURE_BUFFER) {
 -      brw_update_buffer_texture_surface(ctx, unit, binding_table, surf_index);
 -      return;
 -   }
 -
 -   intel_miptree_get_dimensions_for_image(firstImage, &width, &height, &depth);
 -
 -   surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
 -                        6 * 4, 32, &binding_table[surf_index]);
 -
 -   surf[0] = (translate_tex_target(tObj->Target) << BRW_SURFACE_TYPE_SHIFT |
 +   surf[0] = (target << BRW_SURFACE_TYPE_SHIFT |
              BRW_SURFACE_MIPMAPLAYOUT_BELOW << BRW_SURFACE_MIPLAYOUT_SHIFT |
              BRW_SURFACE_CUBEFACE_ENABLES |
 -            (translate_tex_format(intel,
 -                                    mt->format,
 -                                  firstImage->InternalFormat,
 -                                  tObj->DepthMode,
 -                                  sampler->sRGBDecode) <<
 -             BRW_SURFACE_FORMAT_SHIFT));
 -
 -   surf[1] = intelObj->mt->region->bo->offset + intelObj->mt->offset; /* reloc */
 -   surf[1] += intel_miptree_get_tile_offsets(intelObj->mt, firstImage->Level, 0,
 +            (tex_format << BRW_SURFACE_FORMAT_SHIFT));
 +
-    surf[1] = region->bo->offset + offset;
++   surf[1] = mt->region->bo->offset + offset;
++   surf[1] += intel_miptree_get_tile_offsets(mt, first_level, 0,
+                                              &tile_x, &tile_y);
  
 -   surf[2] = ((intelObj->_MaxLevel - tObj->BaseLevel) << BRW_SURFACE_LOD_SHIFT |
 +   surf[2] = (levels << BRW_SURFACE_LOD_SHIFT |
              (width - 1) << BRW_SURFACE_WIDTH_SHIFT |
              (height - 1) << BRW_SURFACE_HEIGHT_SHIFT);
  
-    surf[3] = (brw_get_surface_tiling_bits(region->tiling) |
 -   surf[3] = (brw_get_surface_tiling_bits(intelObj->mt->region->tiling) |
++   surf[3] = (brw_get_surface_tiling_bits(mt->region->tiling) |
              (depth - 1) << BRW_SURFACE_DEPTH_SHIFT |
 -            (intelObj->mt->region->pitch - 1) <<
 -            BRW_SURFACE_PITCH_SHIFT);
 +            (stride - 1) << BRW_SURFACE_PITCH_SHIFT);
  
 -   surf[4] = brw_get_surface_num_multisamples(intelObj->mt->num_samples);
 +   surf[4] = brw_get_surface_num_multisamples(mt->num_samples);
  
-    intel_miptree_get_tile_offsets(mt, 0, 0, &tile_x, &tile_y);
     assert(brw->has_surface_tile_offset || (tile_x == 0 && tile_y == 0));
     /* Note that the low bits of these fields are missing, so
      * there's the possibility of getting in trouble.
  
     /* Emit relocation to surface contents */
     drm_intel_bo_emit_reloc(brw->intel.batch.bo,
-                          *binding_table_slot + 4,
-                          region->bo,
-                            offset,
 -                         binding_table[surf_index] + 4,
 -                         intelObj->mt->region->bo,
 -                           surf[1] - intelObj->mt->region->bo->offset,
--                         I915_GEM_DOMAIN_SAMPLER, 0);
++                           *binding_table_slot + 4,
++                           mt->region->bo,
++                           surf[1] - mt->region->bo->offset,
++                           I915_GEM_DOMAIN_SAMPLER, 0);
 +}
 +
 +static void
 +brw_update_ext_texture_surface(struct brw_context *brw,
 +                               uint32_t *binding_table_slots,
 +                               const struct intel_texture_image *intel_img)
 +{
 +   unsigned i;
 +   const struct intel_region *region = intel_img->mt->region;
 +   const struct intel_image_format *f = intel_img->ext_format;
 +
 +   for (i = 0; i < f->nplanes; ++i) {
 +      int format = BRW_SURFACEFORMAT_R8_UNORM;
 +      int index = f->planes[i].buffer_index;
 +
 +      if (f->planes[i].dri_format == __DRI_IMAGE_FORMAT_GR88)
 +         format = BRW_SURFACEFORMAT_R8G8_UNORM;
 +
 +      brw_update_texture_component(brw, binding_table_slots + i,
 +         intel_img->mt,
 +         region->width >> f->planes[i].width_shift,
 +         region->height >> f->planes[i].height_shift,
 +         intel_img->base.Base.Depth,
 +         intel_img->ext_strides[index],
 +         BRW_SURFACE_2D,
 +         format,
 +         intel_img->ext_offsets[index],
-          0);
++         0 /*levels*/,
++         0 /*first_level*/);
 +   }
 +}
 +
 +static void
 +brw_update_texture_surface(struct gl_context *ctx,
 +                           unsigned unit,
 +                           uint32_t *binding_table,
 +                           unsigned surf_index)
 +{
 +   struct brw_context *brw = brw_context(ctx);
 +   struct gl_texture_object *tObj = ctx->Texture.Unit[unit]._Current;
 +   struct intel_texture_object *intelObj = intel_texture_object(tObj);
 +   struct intel_mipmap_tree *mt = intelObj->mt;
 +   struct gl_texture_image *firstImage = tObj->Image[0][tObj->BaseLevel];
 +   const struct intel_texture_image *intel_img =
 +      (const struct intel_texture_image *)firstImage;
 +   struct gl_sampler_object *sampler = _mesa_get_samplerobj(ctx, unit);
 +   int width, height, depth;
 +
 +   if (tObj->Target == GL_TEXTURE_BUFFER) {
 +      brw_update_buffer_texture_surface(ctx, unit, binding_table, surf_index);
 +      return;
 +   }
 +   else if (tObj->Target == GL_TEXTURE_EXTERNAL_OES && intel_img->ext_format) {
 +      brw_update_ext_texture_surface(brw, binding_table + surf_index,
 +                                     intel_img); 
 +      return;
 +   }
 +
 +   intel_miptree_get_dimensions_for_image(firstImage, &width, &height, &depth);
 +
 +   brw_update_texture_component(brw, binding_table + surf_index,
 +      mt, width, height, depth, mt->region->pitch,
 +      translate_tex_target(tObj->Target),
 +      translate_tex_format(intel_context(ctx), mt->format,
 +         firstImage->InternalFormat, tObj->DepthMode, sampler->sRGBDecode),
 +      mt->offset,
-       intelObj->_MaxLevel - tObj->BaseLevel);
++      intelObj->_MaxLevel - tObj->BaseLevel,
++      firstImage->Level);
  }
  
  /**
@@@ -313,7 -330,9 +313,9 @@@ gen7_update_texture_component(struct br
     if (mt->array_spacing_lod0)
        surf[0] |= GEN7_SURFACE_ARYSPC_LOD0;
  
-    surf[1] = region->bo->offset + offset;
 -   surf[1] = mt->region->bo->offset + mt->offset; /* reloc */
 -   surf[1] += intel_miptree_get_tile_offsets(intelObj->mt, firstImage->Level, 0,
++   surf[1] = mt->region->bo->offset + offset;
++   surf[1] += intel_miptree_get_tile_offsets(mt, first_level, 0,
+                                              &tile_x, &tile_y);
  
     surf[2] = SET_FIELD(width - 1, GEN7_SURFACE_WIDTH) |
               SET_FIELD(height - 1, GEN7_SURFACE_HEIGHT);
  
     /* Emit relocation to surface contents */
     drm_intel_bo_emit_reloc(brw->intel.batch.bo,
 -                         binding_table[surf_index] + 4,
 -                         intelObj->mt->region->bo,
 -                           surf[1] - intelObj->mt->region->bo->offset,
 -                         I915_GEM_DOMAIN_SAMPLER, 0);
 +                           *binding_table_slot + 4,
-                            region->bo, offset,
++                           mt->region->bo,
++                           surf[1] - mt->region->bo->offset,
 +                           I915_GEM_DOMAIN_SAMPLER, 0);
  
     gen7_check_surface_setup(surf, false /* is_render_target */);
  }
Simple merge
Simple merge