1 /**************************************************************************
3 * Copyright (c) (2005-2007) Imagination Technologies Limited.
4 * Copyright (c) 2007, Intel Corporation.
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms and conditions of the GNU General Public License,
9 * version 2, as published by the Free Software Foundation.
11 * This program is distributed in the hope it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 * You should have received a copy of the GNU General Public License along with
17 * this program; if not, write to the Free Software Foundation, Inc.,
18 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
20 * Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
21 * develop this driver.
23 **************************************************************************/
29 #define PSB_CR_CLKGATECTL 0x0000
30 #define _PSB_C_CLKGATECTL_AUTO_MAN_REG (1 << 24)
31 #define _PSB_C_CLKGATECTL_USE_CLKG_SHIFT (20)
32 #define _PSB_C_CLKGATECTL_USE_CLKG_MASK (0x3 << 20)
33 #define _PSB_C_CLKGATECTL_DPM_CLKG_SHIFT (16)
34 #define _PSB_C_CLKGATECTL_DPM_CLKG_MASK (0x3 << 16)
35 #define _PSB_C_CLKGATECTL_TA_CLKG_SHIFT (12)
36 #define _PSB_C_CLKGATECTL_TA_CLKG_MASK (0x3 << 12)
37 #define _PSB_C_CLKGATECTL_TSP_CLKG_SHIFT (8)
38 #define _PSB_C_CLKGATECTL_TSP_CLKG_MASK (0x3 << 8)
39 #define _PSB_C_CLKGATECTL_ISP_CLKG_SHIFT (4)
40 #define _PSB_C_CLKGATECTL_ISP_CLKG_MASK (0x3 << 4)
41 #define _PSB_C_CLKGATECTL_2D_CLKG_SHIFT (0)
42 #define _PSB_C_CLKGATECTL_2D_CLKG_MASK (0x3 << 0)
43 #define _PSB_C_CLKGATECTL_CLKG_ENABLED (0)
44 #define _PSB_C_CLKGATECTL_CLKG_DISABLED (1)
45 #define _PSB_C_CLKGATECTL_CLKG_AUTO (2)
47 #define PSB_CR_CORE_ID 0x0010
48 #define _PSB_CC_ID_ID_SHIFT (16)
49 #define _PSB_CC_ID_ID_MASK (0xFFFF << 16)
50 #define _PSB_CC_ID_CONFIG_SHIFT (0)
51 #define _PSB_CC_ID_CONFIG_MASK (0xFFFF << 0)
53 #define PSB_CR_CORE_REVISION 0x0014
54 #define _PSB_CC_REVISION_DESIGNER_SHIFT (24)
55 #define _PSB_CC_REVISION_DESIGNER_MASK (0xFF << 24)
56 #define _PSB_CC_REVISION_MAJOR_SHIFT (16)
57 #define _PSB_CC_REVISION_MAJOR_MASK (0xFF << 16)
58 #define _PSB_CC_REVISION_MINOR_SHIFT (8)
59 #define _PSB_CC_REVISION_MINOR_MASK (0xFF << 8)
60 #define _PSB_CC_REVISION_MAINTENANCE_SHIFT (0)
61 #define _PSB_CC_REVISION_MAINTENANCE_MASK (0xFF << 0)
63 #define PSB_CR_DESIGNER_REV_FIELD1 0x0018
65 #define PSB_CR_SOFT_RESET 0x0080
66 #define _PSB_CS_RESET_TSP_RESET (1 << 6)
67 #define _PSB_CS_RESET_ISP_RESET (1 << 5)
68 #define _PSB_CS_RESET_USE_RESET (1 << 4)
69 #define _PSB_CS_RESET_TA_RESET (1 << 3)
70 #define _PSB_CS_RESET_DPM_RESET (1 << 2)
71 #define _PSB_CS_RESET_TWOD_RESET (1 << 1)
72 #define _PSB_CS_RESET_BIF_RESET (1 << 0)
74 #define PSB_CR_DESIGNER_REV_FIELD2 0x001C
76 #define PSB_CR_EVENT_HOST_ENABLE2 0x0110
78 #define PSB_CR_EVENT_STATUS2 0x0118
80 #define PSB_CR_EVENT_HOST_CLEAR2 0x0114
81 #define _PSB_CE2_BIF_REQUESTER_FAULT (1 << 4)
83 #define PSB_CR_EVENT_STATUS 0x012C
85 #define PSB_CR_EVENT_HOST_ENABLE 0x0130
87 #define PSB_CR_EVENT_HOST_CLEAR 0x0134
88 #define _PSB_CE_MASTER_INTERRUPT (1 << 31)
89 #define _PSB_CE_TA_DPM_FAULT (1 << 28)
90 #define _PSB_CE_TWOD_COMPLETE (1 << 27)
91 #define _PSB_CE_DPM_OUT_OF_MEMORY_ZLS (1 << 25)
92 #define _PSB_CE_DPM_TA_MEM_FREE (1 << 24)
93 #define _PSB_CE_PIXELBE_END_RENDER (1 << 18)
94 #define _PSB_CE_SW_EVENT (1 << 14)
95 #define _PSB_CE_TA_FINISHED (1 << 13)
96 #define _PSB_CE_TA_TERMINATE (1 << 12)
97 #define _PSB_CE_DPM_REACHED_MEM_THRESH (1 << 3)
98 #define _PSB_CE_DPM_OUT_OF_MEMORY_GBL (1 << 2)
99 #define _PSB_CE_DPM_OUT_OF_MEMORY_MT (1 << 1)
100 #define _PSB_CE_DPM_3D_MEM_FREE (1 << 0)
103 #define PSB_USE_OFFSET_MASK 0x0007FFFF
104 #define PSB_USE_OFFSET_SIZE (PSB_USE_OFFSET_MASK + 1)
105 #define PSB_CR_USE_CODE_BASE0 0x0A0C
106 #define PSB_CR_USE_CODE_BASE1 0x0A10
107 #define PSB_CR_USE_CODE_BASE2 0x0A14
108 #define PSB_CR_USE_CODE_BASE3 0x0A18
109 #define PSB_CR_USE_CODE_BASE4 0x0A1C
110 #define PSB_CR_USE_CODE_BASE5 0x0A20
111 #define PSB_CR_USE_CODE_BASE6 0x0A24
112 #define PSB_CR_USE_CODE_BASE7 0x0A28
113 #define PSB_CR_USE_CODE_BASE8 0x0A2C
114 #define PSB_CR_USE_CODE_BASE9 0x0A30
115 #define PSB_CR_USE_CODE_BASE10 0x0A34
116 #define PSB_CR_USE_CODE_BASE11 0x0A38
117 #define PSB_CR_USE_CODE_BASE12 0x0A3C
118 #define PSB_CR_USE_CODE_BASE13 0x0A40
119 #define PSB_CR_USE_CODE_BASE14 0x0A44
120 #define PSB_CR_USE_CODE_BASE15 0x0A48
121 #define PSB_CR_USE_CODE_BASE(_i) (0x0A0C + ((_i) << 2))
122 #define _PSB_CUC_BASE_DM_SHIFT (25)
123 #define _PSB_CUC_BASE_DM_MASK (0x3 << 25)
124 #define _PSB_CUC_BASE_ADDR_SHIFT (0) // 1024-bit aligned address?
125 #define _PSB_CUC_BASE_ADDR_ALIGNSHIFT (7)
126 #define _PSB_CUC_BASE_ADDR_MASK (0x1FFFFFF << 0)
127 #define _PSB_CUC_DM_VERTEX (0)
128 #define _PSB_CUC_DM_PIXEL (1)
129 #define _PSB_CUC_DM_RESERVED (2)
130 #define _PSB_CUC_DM_EDM (3)
132 #define PSB_CR_PDS_EXEC_BASE 0x0AB8
133 #define _PSB_CR_PDS_EXEC_BASE_ADDR_SHIFT (20) // 1MB aligned address
134 #define _PSB_CR_PDS_EXEC_BASE_ADDR_ALIGNSHIFT (20)
136 #define PSB_CR_EVENT_KICKER 0x0AC4
137 #define _PSB_CE_KICKER_ADDRESS_SHIFT (4) // 128-bit aligned address
139 #define PSB_CR_EVENT_KICK 0x0AC8
140 #define _PSB_CE_KICK_NOW (1 << 0)
143 #define PSB_CR_BIF_DIR_LIST_BASE1 0x0C38
145 #define PSB_CR_BIF_CTRL 0x0C00
146 #define _PSB_CB_CTRL_CLEAR_FAULT (1 << 4)
147 #define _PSB_CB_CTRL_INVALDC (1 << 3)
148 #define _PSB_CB_CTRL_FLUSH (1 << 2)
150 #define PSB_CR_BIF_INT_STAT 0x0C04
152 #define PSB_CR_BIF_FAULT 0x0C08
153 #define _PSB_CBI_STAT_PF_N_RW (1 << 14)
154 #define _PSB_CBI_STAT_FAULT_SHIFT (0)
155 #define _PSB_CBI_STAT_FAULT_MASK (0x3FFF << 0)
156 #define _PSB_CBI_STAT_FAULT_CACHE (1 << 1)
157 #define _PSB_CBI_STAT_FAULT_TA (1 << 2)
158 #define _PSB_CBI_STAT_FAULT_VDM (1 << 3)
159 #define _PSB_CBI_STAT_FAULT_2D (1 << 4)
160 #define _PSB_CBI_STAT_FAULT_PBE (1 << 5)
161 #define _PSB_CBI_STAT_FAULT_TSP (1 << 6)
162 #define _PSB_CBI_STAT_FAULT_ISP (1 << 7)
163 #define _PSB_CBI_STAT_FAULT_USSEPDS (1 << 8)
164 #define _PSB_CBI_STAT_FAULT_HOST (1 << 9)
166 #define PSB_CR_BIF_BANK0 0x0C78
168 #define PSB_CR_BIF_BANK1 0x0C7C
170 #define PSB_CR_BIF_DIR_LIST_BASE0 0x0C84
172 #define PSB_CR_BIF_TWOD_REQ_BASE 0x0C88
173 #define PSB_CR_BIF_3D_REQ_BASE 0x0CAC
175 #define PSB_CR_2D_SOCIF 0x0E18
176 #define _PSB_C2_SOCIF_FREESPACE_SHIFT (0)
177 #define _PSB_C2_SOCIF_FREESPACE_MASK (0xFF << 0)
178 #define _PSB_C2_SOCIF_EMPTY (0x80 << 0)
180 #define PSB_CR_2D_BLIT_STATUS 0x0E04
181 #define _PSB_C2B_STATUS_BUSY (1 << 24)
182 #define _PSB_C2B_STATUS_COMPLETE_SHIFT (0)
183 #define _PSB_C2B_STATUS_COMPLETE_MASK (0xFFFFFF << 0)
190 * 2D Slave Port Data : Block Header's Object Type
193 #define PSB_2D_CLIP_BH (0x00000000)
194 #define PSB_2D_PAT_BH (0x10000000)
195 #define PSB_2D_CTRL_BH (0x20000000)
196 #define PSB_2D_SRC_OFF_BH (0x30000000)
197 #define PSB_2D_MASK_OFF_BH (0x40000000)
198 #define PSB_2D_RESERVED1_BH (0x50000000)
199 #define PSB_2D_RESERVED2_BH (0x60000000)
200 #define PSB_2D_FENCE_BH (0x70000000)
201 #define PSB_2D_BLIT_BH (0x80000000)
202 #define PSB_2D_SRC_SURF_BH (0x90000000)
203 #define PSB_2D_DST_SURF_BH (0xA0000000)
204 #define PSB_2D_PAT_SURF_BH (0xB0000000)
205 #define PSB_2D_SRC_PAL_BH (0xC0000000)
206 #define PSB_2D_PAT_PAL_BH (0xD0000000)
207 #define PSB_2D_MASK_SURF_BH (0xE0000000)
208 #define PSB_2D_FLUSH_BH (0xF0000000)
211 * Clip Definition block (PSB_2D_CLIP_BH)
213 #define PSB_2D_CLIPCOUNT_MAX (1)
214 #define PSB_2D_CLIPCOUNT_MASK (0x00000000)
215 #define PSB_2D_CLIPCOUNT_CLRMASK (0xFFFFFFFF)
216 #define PSB_2D_CLIPCOUNT_SHIFT (0)
217 // clip rectangle min & max
218 #define PSB_2D_CLIP_XMAX_MASK (0x00FFF000)
219 #define PSB_2D_CLIP_XMAX_CLRMASK (0xFF000FFF)
220 #define PSB_2D_CLIP_XMAX_SHIFT (12)
221 #define PSB_2D_CLIP_XMIN_MASK (0x00000FFF)
222 #define PSB_2D_CLIP_XMIN_CLRMASK (0x00FFF000)
223 #define PSB_2D_CLIP_XMIN_SHIFT (0)
224 // clip rectangle offset
225 #define PSB_2D_CLIP_YMAX_MASK (0x00FFF000)
226 #define PSB_2D_CLIP_YMAX_CLRMASK (0xFF000FFF)
227 #define PSB_2D_CLIP_YMAX_SHIFT (12)
228 #define PSB_2D_CLIP_YMIN_MASK (0x00000FFF)
229 #define PSB_2D_CLIP_YMIN_CLRMASK (0x00FFF000)
230 #define PSB_2D_CLIP_YMIN_SHIFT (0)
233 * Pattern Control (PSB_2D_PAT_BH)
235 #define PSB_2D_PAT_HEIGHT_MASK (0x0000001F)
236 #define PSB_2D_PAT_HEIGHT_SHIFT (0)
237 #define PSB_2D_PAT_WIDTH_MASK (0x000003E0)
238 #define PSB_2D_PAT_WIDTH_SHIFT (5)
239 #define PSB_2D_PAT_YSTART_MASK (0x00007C00)
240 #define PSB_2D_PAT_YSTART_SHIFT (10)
241 #define PSB_2D_PAT_XSTART_MASK (0x000F8000)
242 #define PSB_2D_PAT_XSTART_SHIFT (15)
245 * 2D Control block (PSB_2D_CTRL_BH)
248 #define PSB_2D_SRCCK_CTRL (0x00000001)
249 #define PSB_2D_DSTCK_CTRL (0x00000002)
250 #define PSB_2D_ALPHA_CTRL (0x00000004)
251 // Colour Key Colour (SRC/DST)
252 #define PSB_2D_CK_COL_MASK (0xFFFFFFFF)
253 #define PSB_2D_CK_COL_CLRMASK (0x00000000)
254 #define PSB_2D_CK_COL_SHIFT (0)
255 // Colour Key Mask (SRC/DST)
256 #define PSB_2D_CK_MASK_MASK (0xFFFFFFFF)
257 #define PSB_2D_CK_MASK_CLRMASK (0x00000000)
258 #define PSB_2D_CK_MASK_SHIFT (0)
259 // Alpha Control (Alpha/RGB)
260 #define PSB_2D_GBLALPHA_MASK (0x000FF000)
261 #define PSB_2D_GBLALPHA_CLRMASK (0xFFF00FFF)
262 #define PSB_2D_GBLALPHA_SHIFT (12)
263 #define PSB_2D_SRCALPHA_OP_MASK (0x00700000)
264 #define PSB_2D_SRCALPHA_OP_CLRMASK (0xFF8FFFFF)
265 #define PSB_2D_SRCALPHA_OP_SHIFT (20)
266 #define PSB_2D_SRCALPHA_OP_ONE (0x00000000)
267 #define PSB_2D_SRCALPHA_OP_SRC (0x00100000)
268 #define PSB_2D_SRCALPHA_OP_DST (0x00200000)
269 #define PSB_2D_SRCALPHA_OP_SG (0x00300000)
270 #define PSB_2D_SRCALPHA_OP_DG (0x00400000)
271 #define PSB_2D_SRCALPHA_OP_GBL (0x00500000)
272 #define PSB_2D_SRCALPHA_OP_ZERO (0x00600000)
273 #define PSB_2D_SRCALPHA_INVERT (0x00800000)
274 #define PSB_2D_SRCALPHA_INVERT_CLR (0xFF7FFFFF)
275 #define PSB_2D_DSTALPHA_OP_MASK (0x07000000)
276 #define PSB_2D_DSTALPHA_OP_CLRMASK (0xF8FFFFFF)
277 #define PSB_2D_DSTALPHA_OP_SHIFT (24)
278 #define PSB_2D_DSTALPHA_OP_ONE (0x00000000)
279 #define PSB_2D_DSTALPHA_OP_SRC (0x01000000)
280 #define PSB_2D_DSTALPHA_OP_DST (0x02000000)
281 #define PSB_2D_DSTALPHA_OP_SG (0x03000000)
282 #define PSB_2D_DSTALPHA_OP_DG (0x04000000)
283 #define PSB_2D_DSTALPHA_OP_GBL (0x05000000)
284 #define PSB_2D_DSTALPHA_OP_ZERO (0x06000000)
285 #define PSB_2D_DSTALPHA_INVERT (0x08000000)
286 #define PSB_2D_DSTALPHA_INVERT_CLR (0xF7FFFFFF)
288 #define PSB_2D_PRE_MULTIPLICATION_ENABLE (0x10000000)
289 #define PSB_2D_PRE_MULTIPLICATION_CLRMASK (0xEFFFFFFF)
290 #define PSB_2D_ZERO_SOURCE_ALPHA_ENABLE (0x20000000)
291 #define PSB_2D_ZERO_SOURCE_ALPHA_CLRMASK (0xDFFFFFFF)
294 *Source Offset (PSB_2D_SRC_OFF_BH)
296 #define PSB_2D_SRCOFF_XSTART_MASK ((0x00000FFF) << 12)
297 #define PSB_2D_SRCOFF_XSTART_SHIFT (12)
298 #define PSB_2D_SRCOFF_YSTART_MASK (0x00000FFF)
299 #define PSB_2D_SRCOFF_YSTART_SHIFT (0)
302 * Mask Offset (PSB_2D_MASK_OFF_BH)
304 #define PSB_2D_MASKOFF_XSTART_MASK ((0x00000FFF) << 12)
305 #define PSB_2D_MASKOFF_XSTART_SHIFT (12)
306 #define PSB_2D_MASKOFF_YSTART_MASK (0x00000FFF)
307 #define PSB_2D_MASKOFF_YSTART_SHIFT (0)
310 * 2D Fence (see PSB_2D_FENCE_BH): bits 0:27 are ignored
314 *Blit Rectangle (PSB_2D_BLIT_BH)
317 #define PSB_2D_ROT_MASK (3<<25)
318 #define PSB_2D_ROT_CLRMASK (~PSB_2D_ROT_MASK)
319 #define PSB_2D_ROT_NONE (0<<25)
320 #define PSB_2D_ROT_90DEGS (1<<25)
321 #define PSB_2D_ROT_180DEGS (2<<25)
322 #define PSB_2D_ROT_270DEGS (3<<25)
324 #define PSB_2D_COPYORDER_MASK (3<<23)
325 #define PSB_2D_COPYORDER_CLRMASK (~PSB_2D_COPYORDER_MASK)
326 #define PSB_2D_COPYORDER_TL2BR (0<<23)
327 #define PSB_2D_COPYORDER_BR2TL (1<<23)
328 #define PSB_2D_COPYORDER_TR2BL (2<<23)
329 #define PSB_2D_COPYORDER_BL2TR (3<<23)
331 #define PSB_2D_DSTCK_CLRMASK (0xFF9FFFFF)
332 #define PSB_2D_DSTCK_DISABLE (0x00000000)
333 #define PSB_2D_DSTCK_PASS (0x00200000)
334 #define PSB_2D_DSTCK_REJECT (0x00400000)
336 #define PSB_2D_SRCCK_CLRMASK (0xFFE7FFFF)
337 #define PSB_2D_SRCCK_DISABLE (0x00000000)
338 #define PSB_2D_SRCCK_PASS (0x00080000)
339 #define PSB_2D_SRCCK_REJECT (0x00100000)
341 #define PSB_2D_CLIP_ENABLE (0x00040000)
343 #define PSB_2D_ALPHA_ENABLE (0x00020000)
345 #define PSB_2D_PAT_CLRMASK (0xFFFEFFFF)
346 #define PSB_2D_PAT_MASK (0x00010000)
347 #define PSB_2D_USE_PAT (0x00010000)
348 #define PSB_2D_USE_FILL (0x00000000)
350 * Tungsten Graphics note on rop codes: If rop A and rop B are
351 * identical, the mask surface will not be read and need not be
355 #define PSB_2D_ROP3B_MASK (0x0000FF00)
356 #define PSB_2D_ROP3B_CLRMASK (0xFFFF00FF)
357 #define PSB_2D_ROP3B_SHIFT (8)
359 #define PSB_2D_ROP3A_MASK (0x000000FF)
360 #define PSB_2D_ROP3A_CLRMASK (0xFFFFFF00)
361 #define PSB_2D_ROP3A_SHIFT (0)
363 #define PSB_2D_ROP4_MASK (0x0000FFFF)
365 * DWORD0: (Only pass if Pattern control == Use Fill Colour)
366 * Fill Colour RGBA8888
368 #define PSB_2D_FILLCOLOUR_MASK (0xFFFFFFFF)
369 #define PSB_2D_FILLCOLOUR_SHIFT (0)
371 * DWORD1: (Always Present)
375 #define PSB_2D_DST_XSTART_MASK (0x00FFF000)
376 #define PSB_2D_DST_XSTART_CLRMASK (0xFF000FFF)
377 #define PSB_2D_DST_XSTART_SHIFT (12)
378 #define PSB_2D_DST_YSTART_MASK (0x00000FFF)
379 #define PSB_2D_DST_YSTART_CLRMASK (0xFFFFF000)
380 #define PSB_2D_DST_YSTART_SHIFT (0)
382 * DWORD2: (Always Present)
386 #define PSB_2D_DST_XSIZE_MASK (0x00FFF000)
387 #define PSB_2D_DST_XSIZE_CLRMASK (0xFF000FFF)
388 #define PSB_2D_DST_XSIZE_SHIFT (12)
389 #define PSB_2D_DST_YSIZE_MASK (0x00000FFF)
390 #define PSB_2D_DST_YSIZE_CLRMASK (0xFFFFF000)
391 #define PSB_2D_DST_YSIZE_SHIFT (0)
394 * Source Surface (PSB_2D_SRC_SURF_BH)
400 #define PSB_2D_SRC_FORMAT_MASK (0x00078000)
401 #define PSB_2D_SRC_1_PAL (0x00000000)
402 #define PSB_2D_SRC_2_PAL (0x00008000)
403 #define PSB_2D_SRC_4_PAL (0x00010000)
404 #define PSB_2D_SRC_8_PAL (0x00018000)
405 #define PSB_2D_SRC_8_ALPHA (0x00020000)
406 #define PSB_2D_SRC_4_ALPHA (0x00028000)
407 #define PSB_2D_SRC_332RGB (0x00030000)
408 #define PSB_2D_SRC_4444ARGB (0x00038000)
409 #define PSB_2D_SRC_555RGB (0x00040000)
410 #define PSB_2D_SRC_1555ARGB (0x00048000)
411 #define PSB_2D_SRC_565RGB (0x00050000)
412 #define PSB_2D_SRC_0888ARGB (0x00058000)
413 #define PSB_2D_SRC_8888ARGB (0x00060000)
414 #define PSB_2D_SRC_8888UYVY (0x00068000)
415 #define PSB_2D_SRC_RESERVED (0x00070000)
416 #define PSB_2D_SRC_1555ARGB_LOOKUP (0x00078000)
419 #define PSB_2D_SRC_STRIDE_MASK (0x00007FFF)
420 #define PSB_2D_SRC_STRIDE_CLRMASK (0xFFFF8000)
421 #define PSB_2D_SRC_STRIDE_SHIFT (0)
423 * WORD 1 - Base Address
425 #define PSB_2D_SRC_ADDR_MASK (0x0FFFFFFC)
426 #define PSB_2D_SRC_ADDR_CLRMASK (0x00000003)
427 #define PSB_2D_SRC_ADDR_SHIFT (2)
428 #define PSB_2D_SRC_ADDR_ALIGNSHIFT (2)
431 * Pattern Surface (PSB_2D_PAT_SURF_BH)
437 #define PSB_2D_PAT_FORMAT_MASK (0x00078000)
438 #define PSB_2D_PAT_1_PAL (0x00000000)
439 #define PSB_2D_PAT_2_PAL (0x00008000)
440 #define PSB_2D_PAT_4_PAL (0x00010000)
441 #define PSB_2D_PAT_8_PAL (0x00018000)
442 #define PSB_2D_PAT_8_ALPHA (0x00020000)
443 #define PSB_2D_PAT_4_ALPHA (0x00028000)
444 #define PSB_2D_PAT_332RGB (0x00030000)
445 #define PSB_2D_PAT_4444ARGB (0x00038000)
446 #define PSB_2D_PAT_555RGB (0x00040000)
447 #define PSB_2D_PAT_1555ARGB (0x00048000)
448 #define PSB_2D_PAT_565RGB (0x00050000)
449 #define PSB_2D_PAT_0888ARGB (0x00058000)
450 #define PSB_2D_PAT_8888ARGB (0x00060000)
452 #define PSB_2D_PAT_STRIDE_MASK (0x00007FFF)
453 #define PSB_2D_PAT_STRIDE_CLRMASK (0xFFFF8000)
454 #define PSB_2D_PAT_STRIDE_SHIFT (0)
456 * WORD 1 - Base Address
458 #define PSB_2D_PAT_ADDR_MASK (0x0FFFFFFC)
459 #define PSB_2D_PAT_ADDR_CLRMASK (0x00000003)
460 #define PSB_2D_PAT_ADDR_SHIFT (2)
461 #define PSB_2D_PAT_ADDR_ALIGNSHIFT (2)
464 * Destination Surface (PSB_2D_DST_SURF_BH)
470 #define PSB_2D_DST_FORMAT_MASK (0x00078000)
471 #define PSB_2D_DST_332RGB (0x00030000)
472 #define PSB_2D_DST_4444ARGB (0x00038000)
473 #define PSB_2D_DST_555RGB (0x00040000)
474 #define PSB_2D_DST_1555ARGB (0x00048000)
475 #define PSB_2D_DST_565RGB (0x00050000)
476 #define PSB_2D_DST_0888ARGB (0x00058000)
477 #define PSB_2D_DST_8888ARGB (0x00060000)
478 #define PSB_2D_DST_8888AYUV (0x00070000)
480 #define PSB_2D_DST_STRIDE_MASK (0x00007FFF)
481 #define PSB_2D_DST_STRIDE_CLRMASK (0xFFFF8000)
482 #define PSB_2D_DST_STRIDE_SHIFT (0)
484 * WORD 1 - Base Address
486 #define PSB_2D_DST_ADDR_MASK (0x0FFFFFFC)
487 #define PSB_2D_DST_ADDR_CLRMASK (0x00000003)
488 #define PSB_2D_DST_ADDR_SHIFT (2)
489 #define PSB_2D_DST_ADDR_ALIGNSHIFT (2)
492 * Mask Surface (PSB_2D_MASK_SURF_BH)
497 #define PSB_2D_MASK_STRIDE_MASK (0x00007FFF)
498 #define PSB_2D_MASK_STRIDE_CLRMASK (0xFFFF8000)
499 #define PSB_2D_MASK_STRIDE_SHIFT (0)
501 * WORD 1 - Base Address
503 #define PSB_2D_MASK_ADDR_MASK (0x0FFFFFFC)
504 #define PSB_2D_MASK_ADDR_CLRMASK (0x00000003)
505 #define PSB_2D_MASK_ADDR_SHIFT (2)
506 #define PSB_2D_MASK_ADDR_ALIGNSHIFT (2)
509 * Source Palette (PSB_2D_SRC_PAL_BH)
512 #define PSB_2D_SRCPAL_ADDR_SHIFT (0)
513 #define PSB_2D_SRCPAL_ADDR_CLRMASK (0xF0000007)
514 #define PSB_2D_SRCPAL_ADDR_MASK (0x0FFFFFF8)
515 #define PSB_2D_SRCPAL_BYTEALIGN (1024)
518 * Pattern Palette (PSB_2D_PAT_PAL_BH)
521 #define PSB_2D_PATPAL_ADDR_SHIFT (0)
522 #define PSB_2D_PATPAL_ADDR_CLRMASK (0xF0000007)
523 #define PSB_2D_PATPAL_ADDR_MASK (0x0FFFFFF8)
524 #define PSB_2D_PATPAL_BYTEALIGN (1024)
527 * Rop3 Codes (2 LS bytes)
530 #define PSB_2D_ROP3_SRCCOPY (0xCCCC)
531 #define PSB_2D_ROP3_PATCOPY (0xF0F0)
532 #define PSB_2D_ROP3_WHITENESS (0xFFFF)
533 #define PSB_2D_ROP3_BLACKNESS (0x0000)
534 #define PSB_2D_ROP3_SRC (0xCC)
535 #define PSB_2D_ROP3_PAT (0xF0)
536 #define PSB_2D_ROP3_DST (0xAA)
543 #define PSB_SCENE_HW_COOKIE_SIZE 16
544 #define PSB_TA_MEM_HW_COOKIE_SIZE 16
550 #define PSB_NUM_HW_SCENES 2
553 * Scheduler completion actions.
556 #define PSB_RASTER_BLOCK 0