1 /**************************************************************************
2 * Copyright (c) 2007, Intel Corporation.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18 * Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
19 * develop this driver.
21 **************************************************************************/
30 #include "psb_schedule.h"
31 #include "intel_drv.h"
35 #define MAX_BLIT_REQ_SIZE 16*4
36 #define PSB_BLIT_QUEUE_LEN 100
38 typedef struct delayed_2d_blit_req
40 unsigned char BlitReqData[MAX_BLIT_REQ_SIZE];
41 int gnBlitCmdSize; //always 40 bytes now!
42 }delayed_2d_blit_req_t, *delayed_2d_blit_req_ptr;
44 typedef struct psb_2d_blit_queue
46 delayed_2d_blit_req_t sBlitReq[PSB_BLIT_QUEUE_LEN];
49 }psb_2d_blit_queue_t, *psb_2d_blit_queue_ptr;
51 extern int psb_blit_queue_init(psb_2d_blit_queue_ptr q);
52 extern int psb_blit_queue_is_empty(psb_2d_blit_queue_ptr q);
53 extern int psb_blit_queue_is_full(psb_2d_blit_queue_ptr q);
54 extern delayed_2d_blit_req_ptr psb_blit_queue_get_item(psb_2d_blit_queue_ptr q);
55 extern int psb_blit_queue_put_item(psb_2d_blit_queue_ptr q, delayed_2d_blit_req_ptr elem);
56 void psb_blit_queue_clear(psb_2d_blit_queue_ptr q);
58 #endif /* PSB_DETEAR */
70 #define FIX_TG_2D_CLOCKGATE
72 #define DRIVER_NAME "psb"
73 #define DRIVER_DESC "drm driver for the Intel GMA500"
74 #define DRIVER_AUTHOR "Tungsten Graphics Inc."
76 #define PSB_DRM_DRIVER_DATE "20090416"
77 #define PSB_DRM_DRIVER_MAJOR 4
78 #define PSB_DRM_DRIVER_MINOR 41
79 #define PSB_DRM_DRIVER_PATCHLEVEL 1
81 #define PSB_VDC_OFFSET 0x00000000
82 #define PSB_VDC_SIZE 0x000080000
83 #define PSB_SGX_SIZE 0x8000
84 #define PSB_SGX_OFFSET 0x00040000
85 #define PSB_MMIO_RESOURCE 0
86 #define PSB_GATT_RESOURCE 2
87 #define PSB_GTT_RESOURCE 3
88 #define PSB_GMCH_CTRL 0x52
90 #define _PSB_GMCH_ENABLED 0x4
91 #define PSB_PGETBL_CTL 0x2020
92 #define _PSB_PGETBL_ENABLED 0x00000001
93 #define PSB_SGX_2D_SLAVE_PORT 0x4000
94 #define PSB_TT_PRIV0_LIMIT (256*1024*1024)
95 #define PSB_TT_PRIV0_PLIMIT (PSB_TT_PRIV0_LIMIT >> PAGE_SHIFT)
96 #define PSB_NUM_VALIDATE_BUFFERS 1024
97 #define PSB_MEM_KERNEL_START 0x10000000
98 #define PSB_MEM_PDS_START 0x20000000
99 #define PSB_MEM_MMU_START 0x40000000
101 #define DRM_PSB_MEM_KERNEL DRM_BO_MEM_PRIV0
102 #define DRM_PSB_FLAG_MEM_KERNEL DRM_BO_FLAG_MEM_PRIV0
105 * Flags for external memory type field.
108 #define PSB_MSVDX_OFFSET 0x50000 /*MSVDX Base offset */
109 #define PSB_MSVDX_SIZE 0x8000 /*MSVDX MMIO region is 0x50000 - 0x57fff ==> 32KB */
111 #define PSB_MMU_CACHED_MEMORY 0x0001 /* Bind to MMU only */
112 #define PSB_MMU_RO_MEMORY 0x0002 /* MMU RO memory */
113 #define PSB_MMU_WO_MEMORY 0x0004 /* MMU WO memory */
119 #define PSB_PDE_MASK 0x003FFFFF
120 #define PSB_PDE_SHIFT 22
121 #define PSB_PTE_SHIFT 12
123 #define PSB_PTE_VALID 0x0001 /* PTE / PDE valid */
124 #define PSB_PTE_WO 0x0002 /* Write only */
125 #define PSB_PTE_RO 0x0004 /* Read only */
126 #define PSB_PTE_CACHED 0x0008 /* CPU cache coherent */
129 * VDC registers and bits
131 #define PSB_HWSTAM 0x2098
132 #define PSB_INSTPM 0x20C0
133 #define PSB_INT_IDENTITY_R 0x20A4
134 #define _PSB_VSYNC_PIPEB_FLAG (1<<5)
135 #define _PSB_VSYNC_PIPEA_FLAG (1<<7)
136 #define _PSB_HOTPLUG_INTERRUPT_FLAG (1<<17)
137 #define _PSB_IRQ_SGX_FLAG (1<<18)
138 #define _PSB_IRQ_MSVDX_FLAG (1<<19)
139 #define PSB_INT_MASK_R 0x20A8
140 #define PSB_INT_ENABLE_R 0x20A0
141 #define _PSB_HOTPLUG_INTERRUPT_ENABLE (1<<17)
142 #define PSB_PIPEASTAT 0x70024
143 #define _PSB_VBLANK_INTERRUPT_ENABLE (1 << 17)
144 #define _PSB_VBLANK_CLEAR (1 << 1)
145 #define PSB_PIPEBSTAT 0x71024
147 #define PORT_HOTPLUG_ENABLE_REG 0x61110
148 #define SDVOB_HOTPLUG_DETECT_ENABLE (1 << 26)
149 #define PORT_HOTPLUG_STATUS_REG 0x61114
150 #define SDVOB_HOTPLUG_STATUS_ISPLUG (1 << 15)
151 #define SDVOB_HOTPLUG_STATUS (1 << 6)
153 #define _PSB_MMU_ER_MASK 0x0001FF00
154 #define _PSB_MMU_ER_HOST (1 << 16)
163 #define GPIO_CLOCK_DIR_MASK (1 << 0)
164 #define GPIO_CLOCK_DIR_IN (0 << 1)
165 #define GPIO_CLOCK_DIR_OUT (1 << 1)
166 #define GPIO_CLOCK_VAL_MASK (1 << 2)
167 #define GPIO_CLOCK_VAL_OUT (1 << 3)
168 #define GPIO_CLOCK_VAL_IN (1 << 4)
169 #define GPIO_CLOCK_PULLUP_DISABLE (1 << 5)
170 #define GPIO_DATA_DIR_MASK (1 << 8)
171 #define GPIO_DATA_DIR_IN (0 << 9)
172 #define GPIO_DATA_DIR_OUT (1 << 9)
173 #define GPIO_DATA_VAL_MASK (1 << 10)
174 #define GPIO_DATA_VAL_OUT (1 << 11)
175 #define GPIO_DATA_VAL_IN (1 << 12)
176 #define GPIO_DATA_PULLUP_DISABLE (1 << 13)
178 #define VCLK_DIVISOR_VGA0 0x6000
179 #define VCLK_DIVISOR_VGA1 0x6004
180 #define VCLK_POST_DIV 0x6010
182 #define DRM_DRIVER_PRIVATE_T struct drm_psb_private
183 #define I915_WRITE(_offs, _val) \
184 iowrite32(_val, dev_priv->vdc_reg + (_offs))
185 #define I915_READ(_offs) \
186 ioread32(dev_priv->vdc_reg + (_offs))
188 #define PSB_COMM_2D (PSB_ENGINE_2D << 4)
189 #define PSB_COMM_3D (PSB_ENGINE_3D << 4)
190 #define PSB_COMM_TA (PSB_ENGINE_TA << 4)
191 #define PSB_COMM_HP (PSB_ENGINE_HP << 4)
192 #define PSB_COMM_USER_IRQ (1024 >> 2)
193 #define PSB_COMM_USER_IRQ_LOST (PSB_COMM_USER_IRQ + 1)
194 #define PSB_COMM_FW (2048 >> 2)
196 #define PSB_UIRQ_VISTEST 1
197 #define PSB_UIRQ_OOM_REPLY 2
198 #define PSB_UIRQ_FIRE_TA_REPLY 3
199 #define PSB_UIRQ_FIRE_RASTER_REPLY 4
201 #define PSB_2D_SIZE (256*1024*1024)
202 #define PSB_MAX_RELOC_PAGES 1024
204 #define PSB_LOW_REG_OFFS 0x0204
205 #define PSB_HIGH_REG_OFFS 0x0600
207 #define PSB_NUM_VBLANKS 2
209 #define PSB_COMM_2D (PSB_ENGINE_2D << 4)
210 #define PSB_COMM_3D (PSB_ENGINE_3D << 4)
211 #define PSB_COMM_TA (PSB_ENGINE_TA << 4)
212 #define PSB_COMM_HP (PSB_ENGINE_HP << 4)
213 #define PSB_COMM_FW (2048 >> 2)
215 #define PSB_2D_SIZE (256*1024*1024)
216 #define PSB_MAX_RELOC_PAGES 1024
218 #define PSB_LOW_REG_OFFS 0x0204
219 #define PSB_HIGH_REG_OFFS 0x0600
221 #define PSB_NUM_VBLANKS 2
222 #define PSB_WATCHDOG_DELAY (DRM_HZ / 10)
228 struct drm_psb_uopt {
233 struct drm_device *dev;
237 uint32_t gtt_phys_start;
240 uint32_t stolen_base;
243 unsigned long stolen_size;
245 struct rw_semaphore sem;
248 struct psb_use_base {
249 struct list_head head;
250 struct drm_fence_object *fence;
252 unsigned long offset;
256 struct psb_buflist_item;
258 struct psb_msvdx_cmd_queue {
259 struct list_head head;
261 unsigned long cmd_size;
265 struct drm_psb_private {
266 unsigned long chipset;
269 struct psb_xhw_buf resume_buf;
270 struct drm_psb_dev_info_arg dev_info;
271 struct drm_psb_uopt uopt;
275 struct page *scratch_page;
276 struct page *comm_page;
278 volatile uint32_t *comm;
279 uint32_t comm_mmu_offset;
280 uint32_t mmu_2d_offset;
281 uint32_t sequence[PSB_NUM_ENGINES];
282 uint32_t last_sequence[PSB_NUM_ENGINES];
283 int idle[PSB_NUM_ENGINES];
284 uint32_t last_submitted_seq[PSB_NUM_ENGINES];
285 int engine_lockup_2d;
287 struct psb_mmu_driver *mmu;
288 struct psb_mmu_pd *pf_pd;
297 int msvdx_needs_reset;
299 uint32_t gatt_free_offset;
300 atomic_t msvdx_mmu_invaldc;
301 int msvdx_power_saving;
307 uint32_t sgx_irq_mask;
308 uint32_t sgx2_irq_mask;
309 uint32_t vdc_irq_mask;
311 spinlock_t irqmask_lock;
312 spinlock_t sequence_lock;
315 unsigned int irqen_count_2d;
316 wait_queue_head_t event_2d_queue;
319 wait_queue_head_t queue_2d;
322 atomic_t ta_wait_2d_irq;
325 struct mutex mutex_2d;
327 uint32_t msvdx_current_sequence;
328 uint32_t msvdx_last_sequence;
329 #define MSVDX_MAX_IDELTIME HZ*30
330 uint32_t msvdx_finished_sequence;
331 uint32_t msvdx_start_idle;
332 unsigned long msvdx_idle_start_jiffies;
337 * MSVDX Rendec Memory
339 struct drm_buffer_object *ccb0;
341 struct drm_buffer_object *ccb1;
354 int have_mem_rastgeom;
355 struct mutex temp_mem;
358 * Relocation buffer mapping.
361 spinlock_t reloc_lock;
362 unsigned int rel_mapped_pages;
363 wait_queue_head_t rel_mapped_queue;
368 struct drm_psb_sarea *sarea_priv;
373 int backlight_duty_cycle; /* restore backlight to this value */
374 bool panel_wants_dither;
375 struct drm_display_mode *panel_fixed_mode;
380 uint32_t saveDSPACNTR;
381 uint32_t saveDSPBCNTR;
382 uint32_t savePIPEACONF;
383 uint32_t savePIPEBCONF;
384 uint32_t savePIPEASRC;
385 uint32_t savePIPEBSRC;
389 uint32_t saveDPLL_A_MD;
390 uint32_t saveHTOTAL_A;
391 uint32_t saveHBLANK_A;
392 uint32_t saveHSYNC_A;
393 uint32_t saveVTOTAL_A;
394 uint32_t saveVBLANK_A;
395 uint32_t saveVSYNC_A;
396 uint32_t saveDSPASTRIDE;
397 uint32_t saveDSPASIZE;
398 uint32_t saveDSPAPOS;
399 uint32_t saveDSPABASE;
400 uint32_t saveDSPASURF;
404 uint32_t saveDPLL_B_MD;
405 uint32_t saveHTOTAL_B;
406 uint32_t saveHBLANK_B;
407 uint32_t saveHSYNC_B;
408 uint32_t saveVTOTAL_B;
409 uint32_t saveVBLANK_B;
410 uint32_t saveVSYNC_B;
411 uint32_t saveDSPBSTRIDE;
412 uint32_t saveDSPBSIZE;
413 uint32_t saveDSPBPOS;
414 uint32_t saveDSPBBASE;
415 uint32_t saveDSPBSURF;
416 uint32_t saveVCLK_DIVISOR_VGA0;
417 uint32_t saveVCLK_DIVISOR_VGA1;
418 uint32_t saveVCLK_POST_DIV;
419 uint32_t saveVGACNTRL;
427 uint32_t savePP_CONTROL;
428 uint32_t savePP_CYCLE;
429 uint32_t savePFIT_CONTROL;
430 uint32_t savePaletteA[256];
431 uint32_t savePaletteB[256];
432 uint32_t saveBLC_PWM_CTL;
433 uint32_t saveCLOCKGATING;
436 * USE code base register management.
439 struct drm_reg_manager use_manager;
446 struct drm_buffer_object *xhw_bo;
447 struct drm_bo_kmap_obj xhw_kmap;
448 struct list_head xhw_in;
451 struct drm_file *xhw_file;
452 wait_queue_head_t xhw_queue;
453 wait_queue_head_t xhw_caller_queue;
454 struct mutex xhw_mutex;
455 struct psb_xhw_buf *xhw_cur_buf;
463 struct mutex reset_mutex;
464 struct mutex cmdbuf_mutex;
465 struct psb_scheduler scheduler;
466 struct psb_buflist_item *buffers;
467 uint32_t ta_mem_pages;
468 struct psb_ta_mem *ta_mem;
469 int force_ta_mem_load;
475 spinlock_t watchdog_lock;
476 struct timer_list watchdog_timer;
477 struct work_struct watchdog_wq;
478 struct work_struct msvdx_watchdog_wq;
482 * msvdx command queue
484 spinlock_t msvdx_lock;
485 struct mutex msvdx_mutex;
486 struct list_head msvdx_queue;
490 * DVD detear performance evalue
492 struct timeval latest_vblank;
493 wait_queue_head_t blit_2d_queue;
497 struct psb_mmu_driver;
499 extern struct psb_mmu_driver *psb_mmu_driver_init(uint8_t __iomem * registers,
502 atomic_t *msvdx_mmu_invaldc);
503 extern void psb_mmu_driver_takedown(struct psb_mmu_driver *driver);
504 extern struct psb_mmu_pd *psb_mmu_get_default_pd(struct psb_mmu_driver *driver);
505 extern void psb_mmu_mirror_gtt(struct psb_mmu_pd *pd, uint32_t mmu_offset,
506 uint32_t gtt_start, uint32_t gtt_pages);
507 extern void psb_mmu_test(struct psb_mmu_driver *driver, uint32_t offset);
508 extern struct psb_mmu_pd *psb_mmu_alloc_pd(struct psb_mmu_driver *driver,
511 extern void psb_mmu_free_pagedir(struct psb_mmu_pd *pd);
512 extern void psb_mmu_flush(struct psb_mmu_driver *driver);
513 extern void psb_mmu_remove_pfn_sequence(struct psb_mmu_pd *pd,
514 unsigned long address,
516 extern int psb_mmu_insert_pfn_sequence(struct psb_mmu_pd *pd,
518 unsigned long address,
519 uint32_t num_pages, int type);
520 extern int psb_mmu_virtual_to_pfn(struct psb_mmu_pd *pd, uint32_t virtual,
524 * Enable / disable MMU for different requestors.
527 extern void psb_mmu_enable_requestor(struct psb_mmu_driver *driver,
529 extern void psb_mmu_disable_requestor(struct psb_mmu_driver *driver,
531 extern void psb_mmu_set_pd_context(struct psb_mmu_pd *pd, int hw_context);
532 extern int psb_mmu_insert_pages(struct psb_mmu_pd *pd, struct page **pages,
533 unsigned long address, uint32_t num_pages,
534 uint32_t desired_tile_stride,
535 uint32_t hw_tile_stride, int type);
536 extern void psb_mmu_remove_pages(struct psb_mmu_pd *pd, unsigned long address,
538 uint32_t desired_tile_stride,
539 uint32_t hw_tile_stride);
544 extern int psb_blit_sequence(struct drm_psb_private *dev_priv,
546 extern void psb_init_2d(struct drm_psb_private *dev_priv);
547 extern int psb_idle_2d(struct drm_device *dev);
548 extern int psb_idle_3d(struct drm_device *dev);
549 extern int psb_emit_2d_copy_blit(struct drm_device *dev,
551 uint32_t dst_offset, uint32_t pages,
553 extern int psb_cmdbuf_ioctl(struct drm_device *dev, void *data,
554 struct drm_file *file_priv);
555 extern int psb_reg_submit(struct drm_psb_private *dev_priv, uint32_t * regs,
557 extern int psb_submit_copy_cmdbuf(struct drm_device *dev,
558 struct drm_buffer_object *cmd_buffer,
559 unsigned long cmd_offset,
560 unsigned long cmd_size, int engine,
561 uint32_t * copy_buffer);
562 extern void psb_fence_or_sync(struct drm_file *priv,
564 struct drm_psb_cmdbuf_arg *arg,
565 struct drm_fence_arg *fence_arg,
566 struct drm_fence_object **fence_p);
567 extern void psb_init_disallowed(void);
573 extern irqreturn_t psb_irq_handler(DRM_IRQ_ARGS);
574 extern void psb_irq_preinstall(struct drm_device *dev);
575 extern void psb_irq_postinstall(struct drm_device *dev);
576 extern void psb_irq_uninstall(struct drm_device *dev);
577 extern int psb_vblank_wait2(struct drm_device *dev, unsigned int *sequence);
578 extern int psb_vblank_wait(struct drm_device *dev, unsigned int *sequence);
584 extern void psb_fence_handler(struct drm_device *dev, uint32_t class);
585 extern void psb_2D_irq_off(struct drm_psb_private *dev_priv);
586 extern void psb_2D_irq_on(struct drm_psb_private *dev_priv);
587 extern uint32_t psb_fence_advance_sequence(struct drm_device *dev,
589 extern int psb_fence_emit_sequence(struct drm_device *dev, uint32_t fence_class,
590 uint32_t flags, uint32_t * sequence,
591 uint32_t * native_type);
592 extern void psb_fence_error(struct drm_device *dev,
594 uint32_t sequence, uint32_t type, int error);
597 extern void psb_msvdx_irq_off(struct drm_psb_private *dev_priv);
598 extern void psb_msvdx_irq_on(struct drm_psb_private *dev_priv);
599 extern int psb_hw_info_ioctl(struct drm_device *dev, void *data,
600 struct drm_file *file_priv);
605 extern struct drm_ttm_backend *drm_psb_tbe_init(struct drm_device *dev);
606 extern int psb_fence_types(struct drm_buffer_object *bo, uint32_t * class,
608 extern uint32_t psb_evict_mask(struct drm_buffer_object *bo);
609 extern int psb_invalidate_caches(struct drm_device *dev, uint64_t flags);
610 extern int psb_init_mem_type(struct drm_device *dev, uint32_t type,
611 struct drm_mem_type_manager *man);
612 extern int psb_move(struct drm_buffer_object *bo,
613 int evict, int no_wait, struct drm_bo_mem_reg *new_mem);
614 extern int psb_tbe_size(struct drm_device *dev, unsigned long num_pages);
619 extern int psb_gtt_init(struct psb_gtt *pg, int resume);
620 extern int psb_gtt_insert_pages(struct psb_gtt *pg, struct page **pages,
621 unsigned offset_pages, unsigned num_pages,
622 unsigned desired_tile_stride,
623 unsigned hw_tile_stride, int type);
624 extern int psb_gtt_remove_pages(struct psb_gtt *pg, unsigned offset_pages,
626 unsigned desired_tile_stride,
627 unsigned hw_tile_stride);
629 extern struct psb_gtt *psb_gtt_alloc(struct drm_device *dev);
630 extern void psb_gtt_takedown(struct psb_gtt *pg, int free);
635 extern int psbfb_probe(struct drm_device *dev, struct drm_crtc *crtc);
636 extern int psbfb_remove(struct drm_device *dev, struct drm_crtc *crtc);
637 extern int psbfb_kms_off_ioctl(struct drm_device *dev, void *data,
638 struct drm_file *file_priv);
639 extern int psbfb_kms_on_ioctl(struct drm_device *dev, void *data,
640 struct drm_file *file_priv);
641 extern void psbfb_suspend(struct drm_device *dev);
642 extern void psbfb_resume(struct drm_device *dev);
648 extern void psb_reset(struct drm_psb_private *dev_priv, int reset_2d);
649 extern void psb_schedule_watchdog(struct drm_psb_private *dev_priv);
650 extern void psb_watchdog_init(struct drm_psb_private *dev_priv);
651 extern void psb_watchdog_takedown(struct drm_psb_private *dev_priv);
652 extern void psb_print_pagefault(struct drm_psb_private *dev_priv);
658 extern void psb_takedown_use_base(struct drm_psb_private *dev_priv);
659 extern int psb_grab_use_base(struct drm_psb_private *dev_priv,
660 unsigned long dev_virtual,
662 unsigned int data_master,
663 uint32_t fence_class,
667 int *r_reg, uint32_t * r_offset);
668 extern int psb_init_use_base(struct drm_psb_private *dev_priv,
669 unsigned int reg_start, unsigned int reg_num);
675 extern int psb_xhw_ioctl(struct drm_device *dev, void *data,
676 struct drm_file *file_priv);
677 extern int psb_xhw_init_ioctl(struct drm_device *dev, void *data,
678 struct drm_file *file_priv);
679 extern int psb_xhw_init(struct drm_device *dev);
680 extern void psb_xhw_takedown(struct drm_psb_private *dev_priv);
681 extern void psb_xhw_init_takedown(struct drm_psb_private *dev_priv,
682 struct drm_file *file_priv, int closing);
683 extern int psb_xhw_scene_bind_fire(struct drm_psb_private *dev_priv,
684 struct psb_xhw_buf *buf,
689 uint32_t num_oom_cmds,
691 uint32_t engine, uint32_t flags);
692 extern int psb_xhw_fire_raster(struct drm_psb_private *dev_priv,
693 struct psb_xhw_buf *buf, uint32_t fire_flags);
694 extern int psb_xhw_scene_info(struct drm_psb_private *dev_priv,
695 struct psb_xhw_buf *buf,
698 uint32_t * hw_cookie,
700 uint32_t * clear_p_start,
701 uint32_t * clear_num_pages);
703 extern int psb_xhw_reset_dpm(struct drm_psb_private *dev_priv,
704 struct psb_xhw_buf *buf);
705 extern int psb_xhw_check_lockup(struct drm_psb_private *dev_priv,
706 struct psb_xhw_buf *buf, uint32_t * value);
707 extern int psb_xhw_ta_mem_info(struct drm_psb_private *dev_priv,
708 struct psb_xhw_buf *buf,
710 uint32_t * hw_cookie, uint32_t * size);
711 extern int psb_xhw_ta_oom(struct drm_psb_private *dev_priv,
712 struct psb_xhw_buf *buf, uint32_t * cookie);
713 extern void psb_xhw_ta_oom_reply(struct drm_psb_private *dev_priv,
714 struct psb_xhw_buf *buf,
717 uint32_t * rca, uint32_t * flags);
718 extern int psb_xhw_vistest(struct drm_psb_private *dev_priv,
719 struct psb_xhw_buf *buf);
720 extern int psb_xhw_handler(struct drm_psb_private *dev_priv);
721 extern int psb_xhw_resume(struct drm_psb_private *dev_priv,
722 struct psb_xhw_buf *buf);
723 extern void psb_xhw_fire_reply(struct drm_psb_private *dev_priv,
724 struct psb_xhw_buf *buf, uint32_t * cookie);
725 extern int psb_xhw_ta_mem_load(struct drm_psb_private *dev_priv,
726 struct psb_xhw_buf *buf,
728 uint32_t param_offset,
729 uint32_t pt_offset, uint32_t * hw_cookie);
730 extern void psb_xhw_clean_buf(struct drm_psb_private *dev_priv,
731 struct psb_xhw_buf *buf);
733 extern int psb_xhw_hotplug(struct drm_psb_private *dev_priv, struct psb_xhw_buf *buf);
735 * psb_schedule.c: HW bug fixing.
740 extern void psb_2d_unlock(struct drm_psb_private *dev_priv);
741 extern void psb_2d_lock(struct drm_psb_private *dev_priv);
742 extern void psb_resume_ta_2d_idle(struct drm_psb_private *dev_priv);
746 #define psb_2d_lock(_dev_priv) mutex_lock(&(_dev_priv)->mutex_2d)
747 #define psb_2d_unlock(_dev_priv) mutex_unlock(&(_dev_priv)->mutex_2d)
755 #define PSB_ALIGN_TO(_val, _align) \
756 (((_val) + ((_align) - 1)) & ~((_align) - 1))
757 #define PSB_WVDC32(_val, _offs) \
758 iowrite32(_val, dev_priv->vdc_reg + (_offs))
759 #define PSB_RVDC32(_offs) \
760 ioread32(dev_priv->vdc_reg + (_offs))
761 #define PSB_WSGX32(_val, _offs) \
762 iowrite32(_val, dev_priv->sgx_reg + (_offs))
763 #define PSB_RSGX32(_offs) \
764 ioread32(dev_priv->sgx_reg + (_offs))
765 #define PSB_WMSVDX32(_val, _offs) \
766 iowrite32(_val, dev_priv->msvdx_reg + (_offs))
767 #define PSB_RMSVDX32(_offs) \
768 ioread32(dev_priv->msvdx_reg + (_offs))
770 #define PSB_ALPL(_val, _base) \
771 (((_val) >> (_base ## _ALIGNSHIFT)) << (_base ## _SHIFT))
772 #define PSB_ALPLM(_val, _base) \
773 ((((_val) >> (_base ## _ALIGNSHIFT)) << (_base ## _SHIFT)) & (_base ## _MASK))
775 #define PSB_D_RENDER (1 << 16)
777 #define PSB_D_GENERAL (1 << 0)
778 #define PSB_D_INIT (1 << 1)
779 #define PSB_D_IRQ (1 << 2)
780 #define PSB_D_FW (1 << 3)
781 #define PSB_D_PERF (1 << 4)
782 #define PSB_D_TMP (1 << 5)
783 #define PSB_D_RELOC (1 << 6)
785 extern int drm_psb_debug;
786 extern int drm_psb_no_fb;
787 extern int drm_psb_disable_vsync;
788 extern int drm_psb_detear;
790 #define PSB_DEBUG_FW(_fmt, _arg...) \
791 PSB_DEBUG(PSB_D_FW, _fmt, ##_arg)
792 #define PSB_DEBUG_GENERAL(_fmt, _arg...) \
793 PSB_DEBUG(PSB_D_GENERAL, _fmt, ##_arg)
794 #define PSB_DEBUG_INIT(_fmt, _arg...) \
795 PSB_DEBUG(PSB_D_INIT, _fmt, ##_arg)
796 #define PSB_DEBUG_IRQ(_fmt, _arg...) \
797 PSB_DEBUG(PSB_D_IRQ, _fmt, ##_arg)
798 #define PSB_DEBUG_RENDER(_fmt, _arg...) \
799 PSB_DEBUG(PSB_D_RENDER, _fmt, ##_arg)
800 #define PSB_DEBUG_PERF(_fmt, _arg...) \
801 PSB_DEBUG(PSB_D_PERF, _fmt, ##_arg)
802 #define PSB_DEBUG_TMP(_fmt, _arg...) \
803 PSB_DEBUG(PSB_D_TMP, _fmt, ##_arg)
804 #define PSB_DEBUG_RELOC(_fmt, _arg...) \
805 PSB_DEBUG(PSB_D_RELOC, _fmt, ##_arg)
808 #define PSB_DEBUG(_flag, _fmt, _arg...) \
810 if (unlikely((_flag) & drm_psb_debug)) \
812 "[psb:0x%02x:%s] " _fmt , _flag, \
813 __FUNCTION__ , ##_arg); \
816 #define PSB_DEBUG(_fmt, _arg...) do { } while (0)