1 ------------------------------------------------------------------------------
2 -- Copyright (C) 2010, Kenichi Kurimoto
4 -- This program is free software; you can redistribute it and/or modify
5 -- it under the terms of the GNU General Public License as published by
6 -- the Free Software Foundation; either version 2 of the License, or
7 -- (at your option) any later version.
9 -- This program is distributed in the hope that it will be useful,
10 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- GNU General Public License for more details.
14 -- You should have received a copy of the GNU General Public License
15 -- along with this program; if not, write to the Free Software
16 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -----------------------------------------------------------------------------
22 use ieee.std_logic_1164.all;
24 use ieee.std_logic_textio.all;
25 --use ieee.numeric_std.all;
30 use gaisler.ambatest.all;
31 use gaisler.ahbtbp.all;
33 use techmap.gencomp.all;
44 entity sim_huffdctycc is
47 clkperiod : integer := 20);
51 architecture behav of sim_huffdctycc is
55 component bus_huffdctycc
59 ctrl_in1 : in ahbtbm_ctrl_in_type;
60 ctrl_out1 : out ahbtbm_ctrl_out_type
65 signal clk : std_ulogic := '0';
66 signal rst : std_ulogic := '0';
67 signal ctrl1 : ahbtb_ctrl_type;
68 -- signal data_in : std_logic_vector(31 downto 0);
70 file in_file : text open read_mode is "in_huff.txt";
71 file in_quantfile : text open read_mode is "in_qtbl.txt";
72 file compare_file : text open read_mode is "out_upycc.txt";
73 file in_acfile : text open read_mode is "in_accache.txt";
74 file in_dcfile : text open read_mode is "in_dccache.txt";
75 file in_maxcfile : text open read_mode is "in_maxcode.txt";
76 file in_offsfile : text open read_mode is "in_valoffs.txt";
77 file in_huffvfile : text open read_mode is "in_huffval.txt";
82 port map (rst,clk,ctrl1.i,ctrl1.o);
95 variable i,j : integer;
96 -- variable dctindata : std_logic_vector(11 downto 0);
97 variable indata : std_logic_vector(31 downto 0);
98 variable radd : std_logic_vector(31 downto 0);
99 -- variable cdata1, cdata2 : std_logic_vector(15 downto 0);
100 variable cdata32 : std_logic_vector(31 downto 0);
101 variable quantvec : std_logic_vector(7 downto 0);
102 variable wadd : std_logic_vector(31 downto 0);
106 report " stimulus process start ";
114 -- Write Control registers through APB bus
116 ahbwrite(x"80000200", x"a0000000", "10", "10", '1', 2, false , ctrl1);
117 --ahbwrite(x"80000204", x"00082464", "10", "10", '1', 2, false , ctrl1);
118 ahbwrite(x"80000204", x"005c9a84", "10", "10", '1', 2, false , ctrl1);
119 ahbwrite(x"80000208", x"04E4B504", "10", "10", '1', 2, false , ctrl1);
120 ahbwrite(x"8000020C", x"00000000", "10", "10", '1', 2, false , ctrl1);
121 ahbwrite(x"8000020C", x"f0000000", "10", "10", '1', 2, false , ctrl1);
123 ahbtbmidle(true, ctrl1);
126 for i in 0 to 191 loop
127 readline(in_quantfile, li);
129 ahbwrite(wadd, x"000000" & quantvec, "10", "10", '1', 2, false, ctrl1);
130 wadd := wadd + x"00000004";
132 ahbtbmidle(true, ctrl1);
135 for i in 0 to 1023 loop
136 readline(in_acfile, li);
139 wadd := wadd(29 downto 0) & "00";
140 wadd := wadd +"100000000000000";
141 wadd := wadd + x"90000000";
142 ahbwrite(wadd, cdata32, "10", "10", '1', 2, false , ctrl1);
144 for i in 0 to 1023 loop
145 readline(in_dcfile, li);
147 wadd := wadd(29 downto 0) & "00";
148 wadd := wadd + "1000000000000000";
149 wadd := wadd + x"90000000";
151 ahbwrite(wadd, cdata32, "10", "10", '1', 2, false , ctrl1);
153 for i in 0 to 71 loop
154 readline(in_maxcfile,li);
156 wadd := wadd(29 downto 0) & "00";
157 wadd := x"90000400" + wadd ;
159 ahbwrite(wadd, cdata32, "10", "10", '1', 2, false , ctrl1);
161 for i in 0 to 71 loop
162 readline(in_offsfile,li);
164 wadd := wadd(29 downto 0) & "00";
165 wadd := x"90000800" + wadd ;
167 ahbwrite(wadd, cdata32, "10", "10", '1', 2, false , ctrl1);
169 for i in 0 to 1023 loop
170 readline(in_huffvfile,li);
172 wadd := wadd(29 downto 0) & "00";
173 wadd := x"90002000" + wadd ;
175 ahbwrite(wadd, cdata32, "10", "10", '1', 2, false , ctrl1);
178 ahbtbmidle(true,ctrl1);
182 -- Write scan data for IP core
183 -- for i in 0 to 2718 loop
184 for i in 0 to 120 loop
185 readline(in_file,li);
187 ahbwrite(x"90000000", cdata32, "10", "10", '1', 2, false , ctrl1);
188 ahbtbmidle(true, ctrl1);
192 ahbtbmidle(true,ctrl1);
197 -- for i in 0 to 79 loop
198 for i in 0 to 16 loop
199 -- for j in 0 to 39 loop
200 for j in 0 to 160 loop
201 readline(compare_file, lc);
203 ahbread(radd, cdata32, "10", 2, false, ctrl1);
204 radd := radd + x"004";
206 -- radd := radd + x"460";
207 radd := radd + x"280";
210 ahbtbmidle(true,ctrl1);
213 ahbtbmdone(0, ctrl1);
216 report "stimulus process end" severity failure;