grlib-gpl-1.0.22-b4095/designs/work_ip/Makefile

   1 GRLIB=../..
   2 TOP=bus_huffdctycc
   3 BOARD=altera-ep3c25-eek
   4 include $(GRLIB)/boards/$(BOARD)/Makefile.inc
   5 DEVICE=$(PART)-$(PACKAGE)$(SPEED)
   6 UCF=$(GRLIB)/boards/$(BOARD)/$(TOP).ucf
   7 QSF=$(GRLIB)/boards/$(BOARD)/$(TOP).qsf
   8 EFFORT=std
   9 XSTOPT=
  10 SYNPOPT="set_option -pipe 1; set_option -retiming 1"
  11 VHDLSYNFILES=config.vhd bus_huffdctycc.vhd
  12 VHDLSIMFILES=sim_huffdctycc.vhd sim_huff.vhd bus_huff.vhd
  13 SIMTOP=sim_upycc
  14 SDCFILE=$(GRLIB)/boards/$(BOARD)/default.sdc
  15 BITGEN=$(GRLIB)/boards/$(BOARD)/default.ut
  16 CLEAN=soft-clean
  17
  18 TECHLIBS = altera altera_mf cycloneiii
  19 LIBSKIP = core1553bbc core1553brm core1553brt gr1553 corePCIF \
  20         tmtc openchip hynix cypress ihp gleichmann opencores micron\
  21         stratixii stratixiii usbhc spw \
  22         eth fmf spansion gsi
  23 DIRSKIP = b1553 pcif leon2 leon2ft crypto satcan pci leon3ft can \
  24         grusbhc spacewire hcan ddr net greth haps leon3 ata usb uart jtag arith
  25 FILESKIP = grcan.vhd i2cmst.vhd
  26
  27 include $(GRLIB)/software/leon3/Makefile
  28 include $(GRLIB)/bin/Makefile
  29
  30
  31 ##################  project specific targets ##########################
  32