1 ;;- Machine description for GNU compiler -- S/390 / zSeries version.
2 ;; Copyright (C) 1999, 2000, 2001, 2002, 2003, 2004, 2005
3 ;; Free Software Foundation, Inc.
4 ;; Contributed by Hartmut Penner (hpenner@de.ibm.com) and
5 ;; Ulrich Weigand (uweigand@de.ibm.com).
7 ;; This file is part of GCC.
9 ;; GCC is free software; you can redistribute it and/or modify it under
10 ;; the terms of the GNU General Public License as published by the Free
11 ;; Software Foundation; either version 2, or (at your option) any later
14 ;; GCC is distributed in the hope that it will be useful, but WITHOUT ANY
15 ;; WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 ;; FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
19 ;; You should have received a copy of the GNU General Public License
20 ;; along with GCC; see the file COPYING. If not, write to the Free
21 ;; Software Foundation, 59 Temple Place - Suite 330, Boston, MA
25 ;; Special constraints for s/390 machine description:
27 ;; a -- Any address register from 1 to 15.
28 ;; c -- Condition code register 33.
29 ;; d -- Any register from 0 to 15.
30 ;; I -- An 8-bit constant (0..255).
31 ;; J -- A 12-bit constant (0..4095).
32 ;; K -- A 16-bit constant (-32768..32767).
33 ;; L -- Value appropriate as displacement.
34 ;; (0..4095) for short displacement
35 ;; (-524288..524287) for long displacement
36 ;; M -- Constant integer with a value of 0x7fffffff.
37 ;; N -- Multiple letter constraint followed by 4 parameter letters.
38 ;; 0..9,x: number of the part counting from most to least significant
39 ;; H,Q: mode of the part
40 ;; D,S,H: mode of the containing operand
41 ;; 0,F: value of the other parts (F - all bits set)
43 ;; The constraint matches if the specified part of a constant
44 ;; has a value different from its other parts. If the letter x
45 ;; is specified instead of a part number, the constraint matches
46 ;; if there is any single part with non-default value.
47 ;; Q -- Memory reference without index register and with short displacement.
48 ;; R -- Memory reference with index register and short displacement.
49 ;; S -- Memory reference without index register but with long displacement.
50 ;; T -- Memory reference with index register and long displacement.
51 ;; A -- Multiple letter constraint followed by Q, R, S, or T:
52 ;; Offsettable memory reference of type specified by second letter.
53 ;; B -- Multiple letter constraint followed by Q, R, S, or T:
54 ;; Memory reference of the type specified by second letter that
55 ;; does *not* refer to a literal pool entry.
56 ;; U -- Pointer with short displacement.
57 ;; W -- Pointer with long displacement.
58 ;; Y -- Shift count operand.
60 ;; Special formats used for outputting 390 instructions.
62 ;; %C: print opcode suffix for branch condition.
63 ;; %D: print opcode suffix for inverse branch condition.
64 ;; %J: print tls_load/tls_gdcall/tls_ldcall suffix
65 ;; %O: print only the displacement of a memory reference.
66 ;; %R: print only the base register of a memory reference.
67 ;; %S: print S-type memory reference (base+displacement).
68 ;; %N: print the second word of a DImode operand.
69 ;; %M: print the second word of a TImode operand.
71 ;; %b: print integer X as if it's an unsigned byte.
72 ;; %x: print integer X as if it's an unsigned word.
73 ;; %h: print integer X as if it's a signed word.
74 ;; %i: print the first nonzero HImode part of X
75 ;; %j: print the first HImode part unequal to 0xffff of X
78 ;; We have a special constraint for pattern matching.
80 ;; s_operand -- Matches a valid S operand in a RS, SI or SS type instruction.
93 ; GOT/PLT and lt-relative accesses
94 (UNSPEC_LTREL_OFFSET 100)
95 (UNSPEC_LTREL_BASE 101)
103 (UNSPEC_RELOAD_BASE 210)
104 (UNSPEC_MAIN_BASE 211)
109 ; TLS relocation specifiers
114 (UNSPEC_GOTNTPOFF 504)
115 (UNSPEC_INDNTPOFF 505)
118 (UNSPEC_TLSLDM_NTPOFF 511)
119 (UNSPEC_TLS_LOAD 512)
126 ;; UNSPEC_VOLATILE usage
134 (UNSPECV_TPF_PROLOGUE 20)
135 (UNSPECV_TPF_EPILOGUE 21)
139 (UNSPECV_POOL_SECTION 201)
140 (UNSPECV_POOL_ALIGN 202)
141 (UNSPECV_POOL_ENTRY 203)
142 (UNSPECV_MAIN_POOL 300)
149 ;; Instruction operand type as used in the Principles of Operation.
150 ;; Used to determine defaults for length and other attribute values.
152 (define_attr "op_type"
153 "NN,E,RR,RRE,RX,RS,RSI,RI,SI,S,SS,SSE,RXE,RSE,RIL,RIE,RXY,RSY,SIY"
156 ;; Instruction type attribute used for scheduling.
158 (define_attr "type" "none,integer,load,lr,la,larl,lm,stm,
160 imulhi,imulsi,imuldi,
161 branch,jsr,fsimpd,fsimps,
162 floadd,floads,fstored, fstores,
163 fmuld,fmuls,fdivd,fdivs,
164 ftoi,itof,fsqrtd,fsqrts,
166 (cond [(eq_attr "op_type" "NN") (const_string "other")
167 (eq_attr "op_type" "SS") (const_string "cs")]
168 (const_string "integer")))
170 ;; Another attribute used for scheduling purposes:
171 ;; agen: Instruction uses the address generation unit
172 ;; reg: Instruction does not use the agen unit
174 (define_attr "atype" "agen,reg"
175 (cond [(eq_attr "op_type" "E") (const_string "reg")
176 (eq_attr "op_type" "RR") (const_string "reg")
177 (eq_attr "op_type" "RX") (const_string "agen")
178 (eq_attr "op_type" "RI") (const_string "reg")
179 (eq_attr "op_type" "RRE") (const_string "reg")
180 (eq_attr "op_type" "RS") (const_string "agen")
181 (eq_attr "op_type" "RSI") (const_string "agen")
182 (eq_attr "op_type" "S") (const_string "agen")
183 (eq_attr "op_type" "SI") (const_string "agen")
184 (eq_attr "op_type" "SS") (const_string "agen")
185 (eq_attr "op_type" "SSE") (const_string "agen")
186 (eq_attr "op_type" "RXE") (const_string "agen")
187 (eq_attr "op_type" "RSE") (const_string "agen")
188 (eq_attr "op_type" "RIL") (const_string "agen")
189 (eq_attr "op_type" "RXY") (const_string "agen")
190 (eq_attr "op_type" "RSY") (const_string "agen")
191 (eq_attr "op_type" "SIY") (const_string "agen")]
192 (const_string "agen")))
196 (define_attr "length" ""
197 (cond [(eq_attr "op_type" "E") (const_int 2)
198 (eq_attr "op_type" "RR") (const_int 2)
199 (eq_attr "op_type" "RX") (const_int 4)
200 (eq_attr "op_type" "RI") (const_int 4)
201 (eq_attr "op_type" "RRE") (const_int 4)
202 (eq_attr "op_type" "RS") (const_int 4)
203 (eq_attr "op_type" "RSI") (const_int 4)
204 (eq_attr "op_type" "S") (const_int 4)
205 (eq_attr "op_type" "SI") (const_int 4)
206 (eq_attr "op_type" "SS") (const_int 6)
207 (eq_attr "op_type" "SSE") (const_int 6)
208 (eq_attr "op_type" "RXE") (const_int 6)
209 (eq_attr "op_type" "RSE") (const_int 6)
210 (eq_attr "op_type" "RIL") (const_int 6)
211 (eq_attr "op_type" "RXY") (const_int 6)
212 (eq_attr "op_type" "RSY") (const_int 6)
213 (eq_attr "op_type" "SIY") (const_int 6)]
217 ;; Processor type. This attribute must exactly match the processor_type
218 ;; enumeration in s390.h. The current machine description does not
219 ;; distinguish between g5 and g6, but there are differences between the two
220 ;; CPUs could in theory be modeled.
222 (define_attr "cpu" "g5,g6,z900,z990"
223 (const (symbol_ref "s390_tune")))
225 ;; Pipeline description for z900. For lack of anything better,
226 ;; this description is also used for the g5 and g6.
229 ;; Pipeline description for z990.
233 (include "predicates.md")
238 ;; This mode macro allows the QI and HI patterns to be defined from
239 ;; the same template.
240 (define_mode_macro HQI [HI QI])
243 ;; ICM mask required to load MODE value into the highest subreg
244 ;; of a SImode register.
245 (define_mode_attr icm_hi [(HI "12") (QI "8")])
247 ;; ICM mask required to load MODE value into the lowest subreg
248 ;; of a SImode register.
249 (define_mode_attr icm_lo [(HI "3") (QI "1")])
251 ;; Maximum unsigned integer that fits in MODE.
252 (define_mode_attr max_uint [(HI "65535") (QI "255")])
256 ;;- Compare instructions.
259 (define_expand "cmpdi"
261 (compare:CC (match_operand:DI 0 "register_operand" "")
262 (match_operand:DI 1 "general_operand" "")))]
265 s390_compare_op0 = operands[0];
266 s390_compare_op1 = operands[1];
270 (define_expand "cmpsi"
272 (compare:CC (match_operand:SI 0 "register_operand" "")
273 (match_operand:SI 1 "general_operand" "")))]
276 s390_compare_op0 = operands[0];
277 s390_compare_op1 = operands[1];
281 (define_expand "cmpdf"
283 (compare:CC (match_operand:DF 0 "register_operand" "")
284 (match_operand:DF 1 "general_operand" "")))]
287 s390_compare_op0 = operands[0];
288 s390_compare_op1 = operands[1];
292 (define_expand "cmpsf"
294 (compare:CC (match_operand:SF 0 "register_operand" "")
295 (match_operand:SF 1 "general_operand" "")))]
298 s390_compare_op0 = operands[0];
299 s390_compare_op1 = operands[1];
304 ; Test-under-Mask instructions
306 (define_insn "*tmqi_mem"
308 (compare (and:QI (match_operand:QI 0 "memory_operand" "Q,S")
309 (match_operand:QI 1 "immediate_operand" "n,n"))
310 (match_operand:QI 2 "immediate_operand" "n,n")))]
311 "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], 0))"
315 [(set_attr "op_type" "SI,SIY")])
317 (define_insn "*tmdi_reg"
319 (compare (and:DI (match_operand:DI 0 "nonimmediate_operand" "d,d,d,d")
320 (match_operand:DI 1 "immediate_operand"
321 "N0HD0,N1HD0,N2HD0,N3HD0"))
322 (match_operand:DI 2 "immediate_operand" "n,n,n,n")))]
324 && s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], 1))
325 && s390_single_part (operands[1], DImode, HImode, 0) >= 0"
331 [(set_attr "op_type" "RI")])
333 (define_insn "*tmsi_reg"
335 (compare (and:SI (match_operand:SI 0 "nonimmediate_operand" "d,d")
336 (match_operand:SI 1 "immediate_operand" "N0HS0,N1HS0"))
337 (match_operand:SI 2 "immediate_operand" "n,n")))]
338 "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], 1))
339 && s390_single_part (operands[1], SImode, HImode, 0) >= 0"
343 [(set_attr "op_type" "RI")])
345 (define_insn "*tm<mode>_full"
347 (compare (match_operand:HQI 0 "register_operand" "d")
348 (match_operand:HQI 1 "immediate_operand" "n")))]
349 "s390_match_ccmode (insn, s390_tm_ccmode (constm1_rtx, operands[1], 1))"
351 [(set_attr "op_type" "RI")])
354 ; Load-and-Test instructions
356 (define_insn "*tstdi_sign"
358 (compare (ashiftrt:DI (ashift:DI (subreg:DI (match_operand:SI 0 "register_operand" "d") 0)
359 (const_int 32)) (const_int 32))
360 (match_operand:DI 1 "const0_operand" "")))
361 (set (match_operand:DI 2 "register_operand" "=d")
362 (sign_extend:DI (match_dup 0)))]
363 "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT"
365 [(set_attr "op_type" "RRE")])
367 (define_insn "*tstdi"
369 (compare (match_operand:DI 0 "register_operand" "d")
370 (match_operand:DI 1 "const0_operand" "")))
371 (set (match_operand:DI 2 "register_operand" "=d")
373 "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT"
375 [(set_attr "op_type" "RRE")])
377 (define_insn "*tstdi_cconly"
379 (compare (match_operand:DI 0 "register_operand" "d")
380 (match_operand:DI 1 "const0_operand" "")))]
381 "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT"
383 [(set_attr "op_type" "RRE")])
385 (define_insn "*tstdi_cconly_31"
387 (compare (match_operand:DI 0 "register_operand" "d")
388 (match_operand:DI 1 "const0_operand" "")))]
389 "s390_match_ccmode(insn, CCSmode) && !TARGET_64BIT"
391 [(set_attr "op_type" "RS")
392 (set_attr "atype" "reg")])
395 (define_insn "*tstsi"
397 (compare (match_operand:SI 0 "nonimmediate_operand" "d,Q,S")
398 (match_operand:SI 1 "const0_operand" "")))
399 (set (match_operand:SI 2 "register_operand" "=d,d,d")
401 "s390_match_ccmode(insn, CCSmode)"
406 [(set_attr "op_type" "RR,RS,RSY")])
408 (define_insn "*tstsi_cconly"
410 (compare (match_operand:SI 0 "nonimmediate_operand" "d,Q,S")
411 (match_operand:SI 1 "const0_operand" "")))
412 (clobber (match_scratch:SI 2 "=X,d,d"))]
413 "s390_match_ccmode(insn, CCSmode)"
418 [(set_attr "op_type" "RR,RS,RSY")])
420 (define_insn "*tstsi_cconly2"
422 (compare (match_operand:SI 0 "register_operand" "d")
423 (match_operand:SI 1 "const0_operand" "")))]
424 "s390_match_ccmode(insn, CCSmode)"
426 [(set_attr "op_type" "RR")])
428 (define_insn "*tst<mode>CCT"
430 (compare (match_operand:HQI 0 "nonimmediate_operand" "?Q,?S,d")
431 (match_operand:HQI 1 "const0_operand" "")))
432 (set (match_operand:HQI 2 "register_operand" "=d,d,0")
434 "s390_match_ccmode(insn, CCTmode)"
437 icmy\t%2,<icm_lo>,%S0
439 [(set_attr "op_type" "RS,RSY,RI")])
441 (define_insn "*tsthiCCT_cconly"
443 (compare (match_operand:HI 0 "nonimmediate_operand" "Q,S,d")
444 (match_operand:HI 1 "const0_operand" "")))
445 (clobber (match_scratch:HI 2 "=d,d,X"))]
446 "s390_match_ccmode(insn, CCTmode)"
451 [(set_attr "op_type" "RS,RSY,RI")])
453 (define_insn "*tstqiCCT_cconly"
455 (compare (match_operand:QI 0 "nonimmediate_operand" "?Q,?S,d")
456 (match_operand:QI 1 "const0_operand" "")))]
457 "s390_match_ccmode(insn, CCTmode)"
462 [(set_attr "op_type" "SI,SIY,RI")])
464 (define_insn "*tst<mode>"
466 (compare (match_operand:HQI 0 "s_operand" "Q,S")
467 (match_operand:HQI 1 "const0_operand" "")))
468 (set (match_operand:HQI 2 "register_operand" "=d,d")
470 "s390_match_ccmode(insn, CCSmode)"
473 icmy\t%2,<icm_lo>,%S0"
474 [(set_attr "op_type" "RS,RSY")])
476 (define_insn "*tst<mode>_cconly"
478 (compare (match_operand:HQI 0 "s_operand" "Q,S")
479 (match_operand:HQI 1 "const0_operand" "")))
480 (clobber (match_scratch:HQI 2 "=d,d"))]
481 "s390_match_ccmode(insn, CCSmode)"
484 icmy\t%2,<icm_lo>,%S0"
485 [(set_attr "op_type" "RS,RSY")])
488 ; Compare (equality) instructions
490 (define_insn "*cmpdi_cct"
492 (compare (match_operand:DI 0 "nonimmediate_operand" "%d,d,d,Q")
493 (match_operand:DI 1 "general_operand" "d,K,m,BQ")))]
494 "s390_match_ccmode (insn, CCTmode) && TARGET_64BIT"
500 [(set_attr "op_type" "RRE,RI,RXY,SS")])
502 (define_insn "*cmpsi_cct"
504 (compare (match_operand:SI 0 "nonimmediate_operand" "%d,d,d,d,Q")
505 (match_operand:SI 1 "general_operand" "d,K,R,T,BQ")))]
506 "s390_match_ccmode (insn, CCTmode)"
513 [(set_attr "op_type" "RR,RI,RX,RXY,SS")])
516 ; Compare (signed) instructions
518 (define_insn "*cmpdi_ccs_sign"
520 (compare (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,m"))
521 (match_operand:DI 0 "register_operand" "d,d")))]
522 "s390_match_ccmode(insn, CCSRmode) && TARGET_64BIT"
526 [(set_attr "op_type" "RRE,RXY")])
528 (define_insn "*cmpdi_ccs"
530 (compare (match_operand:DI 0 "register_operand" "d,d,d")
531 (match_operand:DI 1 "general_operand" "d,K,m")))]
532 "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT"
537 [(set_attr "op_type" "RRE,RI,RXY")])
539 (define_insn "*cmpsi_ccs_sign"
541 (compare (sign_extend:SI (match_operand:HI 1 "memory_operand" "R,T"))
542 (match_operand:SI 0 "register_operand" "d,d")))]
543 "s390_match_ccmode(insn, CCSRmode)"
547 [(set_attr "op_type" "RX,RXY")])
549 (define_insn "*cmpsi_ccs"
551 (compare (match_operand:SI 0 "register_operand" "d,d,d,d")
552 (match_operand:SI 1 "general_operand" "d,K,R,T")))]
553 "s390_match_ccmode(insn, CCSmode)"
559 [(set_attr "op_type" "RR,RI,RX,RXY")])
562 ; Compare (unsigned) instructions
564 (define_insn "*cmpdi_ccu_zero"
566 (compare (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,m"))
567 (match_operand:DI 0 "register_operand" "d,d")))]
568 "s390_match_ccmode (insn, CCURmode) && TARGET_64BIT"
572 [(set_attr "op_type" "RRE,RXY")])
574 (define_insn "*cmpdi_ccu"
576 (compare (match_operand:DI 0 "nonimmediate_operand" "d,d,Q,BQ")
577 (match_operand:DI 1 "general_operand" "d,m,BQ,Q")))]
578 "s390_match_ccmode (insn, CCUmode) && TARGET_64BIT"
584 [(set_attr "op_type" "RRE,RXY,SS,SS")])
586 (define_insn "*cmpsi_ccu"
588 (compare (match_operand:SI 0 "nonimmediate_operand" "d,d,d,Q,BQ")
589 (match_operand:SI 1 "general_operand" "d,R,T,BQ,Q")))]
590 "s390_match_ccmode (insn, CCUmode)"
597 [(set_attr "op_type" "RR,RX,RXY,SS,SS")])
599 (define_insn "*cmphi_ccu"
601 (compare (match_operand:HI 0 "nonimmediate_operand" "d,d,Q,BQ")
602 (match_operand:HI 1 "general_operand" "Q,S,BQ,Q")))]
603 "s390_match_ccmode (insn, CCUmode)
604 && !register_operand (operands[1], HImode)"
610 [(set_attr "op_type" "RS,RSY,SS,SS")])
612 (define_insn "*cmpqi_ccu"
614 (compare (match_operand:QI 0 "nonimmediate_operand" "d,d,Q,S,Q,BQ")
615 (match_operand:QI 1 "general_operand" "Q,S,n,n,BQ,Q")))]
616 "s390_match_ccmode (insn, CCUmode)
617 && !register_operand (operands[1], QImode)"
625 [(set_attr "op_type" "RS,RSY,SI,SIY,SS,SS")])
628 ; Block compare (CLC) instruction patterns.
632 (compare (match_operand:BLK 0 "memory_operand" "Q")
633 (match_operand:BLK 1 "memory_operand" "Q")))
634 (use (match_operand 2 "const_int_operand" "n"))]
635 "s390_match_ccmode (insn, CCUmode)
636 && INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
637 "clc\t%O0(%2,%R0),%S1"
638 [(set_attr "op_type" "SS")])
642 (compare (match_operand 0 "memory_operand" "")
643 (match_operand 1 "memory_operand" "")))]
645 && s390_match_ccmode (insn, CCUmode)
646 && GET_MODE (operands[0]) == GET_MODE (operands[1])
647 && GET_MODE_SIZE (GET_MODE (operands[0])) > 0"
649 [(set (match_dup 0) (match_dup 1))
650 (use (match_dup 2))])]
652 operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0])));
653 operands[0] = adjust_address (operands[0], BLKmode, 0);
654 operands[1] = adjust_address (operands[1], BLKmode, 0);
656 operands[1] = gen_rtx_COMPARE (GET_MODE (SET_DEST (PATTERN (curr_insn))),
657 operands[0], operands[1]);
658 operands[0] = SET_DEST (PATTERN (curr_insn));
664 (define_insn "*cmpdf_ccs_0"
666 (compare (match_operand:DF 0 "register_operand" "f")
667 (match_operand:DF 1 "const0_operand" "")))]
668 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
670 [(set_attr "op_type" "RRE")
671 (set_attr "type" "fsimpd")])
673 (define_insn "*cmpdf_ccs_0_ibm"
675 (compare (match_operand:DF 0 "register_operand" "f")
676 (match_operand:DF 1 "const0_operand" "")))]
677 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
679 [(set_attr "op_type" "RR")
680 (set_attr "type" "fsimpd")])
682 (define_insn "*cmpdf_ccs"
684 (compare (match_operand:DF 0 "register_operand" "f,f")
685 (match_operand:DF 1 "general_operand" "f,R")))]
686 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
690 [(set_attr "op_type" "RRE,RXE")
691 (set_attr "type" "fsimpd")])
693 (define_insn "*cmpdf_ccs_ibm"
695 (compare (match_operand:DF 0 "register_operand" "f,f")
696 (match_operand:DF 1 "general_operand" "f,R")))]
697 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
701 [(set_attr "op_type" "RR,RX")
702 (set_attr "type" "fsimpd")])
707 (define_insn "*cmpsf_ccs_0"
709 (compare (match_operand:SF 0 "register_operand" "f")
710 (match_operand:SF 1 "const0_operand" "")))]
711 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
713 [(set_attr "op_type" "RRE")
714 (set_attr "type" "fsimps")])
716 (define_insn "*cmpsf_ccs_0_ibm"
718 (compare (match_operand:SF 0 "register_operand" "f")
719 (match_operand:SF 1 "const0_operand" "")))]
720 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
722 [(set_attr "op_type" "RR")
723 (set_attr "type" "fsimps")])
725 (define_insn "*cmpsf_ccs"
727 (compare (match_operand:SF 0 "register_operand" "f,f")
728 (match_operand:SF 1 "general_operand" "f,R")))]
729 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
733 [(set_attr "op_type" "RRE,RXE")
734 (set_attr "type" "fsimps")])
736 (define_insn "*cmpsf_ccs"
738 (compare (match_operand:SF 0 "register_operand" "f,f")
739 (match_operand:SF 1 "general_operand" "f,R")))]
740 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
744 [(set_attr "op_type" "RR,RX")
745 (set_attr "type" "fsimps")])
749 ;;- Move instructions.
753 ; movti instruction pattern(s).
757 [(set (match_operand:TI 0 "nonimmediate_operand" "=d,QS,d,o,Q")
758 (match_operand:TI 1 "general_operand" "QS,d,dKm,d,Q"))]
766 [(set_attr "op_type" "RSY,RSY,*,*,SS")
767 (set_attr "type" "lm,stm,*,*,*")])
770 [(set (match_operand:TI 0 "nonimmediate_operand" "")
771 (match_operand:TI 1 "general_operand" ""))]
772 "TARGET_64BIT && reload_completed
773 && s390_split_ok_p (operands[0], operands[1], TImode, 0)"
774 [(set (match_dup 2) (match_dup 4))
775 (set (match_dup 3) (match_dup 5))]
777 operands[2] = operand_subword (operands[0], 0, 0, TImode);
778 operands[3] = operand_subword (operands[0], 1, 0, TImode);
779 operands[4] = operand_subword (operands[1], 0, 0, TImode);
780 operands[5] = operand_subword (operands[1], 1, 0, TImode);
784 [(set (match_operand:TI 0 "nonimmediate_operand" "")
785 (match_operand:TI 1 "general_operand" ""))]
786 "TARGET_64BIT && reload_completed
787 && s390_split_ok_p (operands[0], operands[1], TImode, 1)"
788 [(set (match_dup 2) (match_dup 4))
789 (set (match_dup 3) (match_dup 5))]
791 operands[2] = operand_subword (operands[0], 1, 0, TImode);
792 operands[3] = operand_subword (operands[0], 0, 0, TImode);
793 operands[4] = operand_subword (operands[1], 1, 0, TImode);
794 operands[5] = operand_subword (operands[1], 0, 0, TImode);
798 [(set (match_operand:TI 0 "register_operand" "")
799 (match_operand:TI 1 "memory_operand" ""))]
800 "TARGET_64BIT && reload_completed
801 && !s_operand (operands[1], VOIDmode)"
802 [(set (match_dup 0) (match_dup 1))]
804 rtx addr = operand_subword (operands[0], 1, 0, TImode);
805 s390_load_address (addr, XEXP (operands[1], 0));
806 operands[1] = replace_equiv_address (operands[1], addr);
809 (define_expand "reload_outti"
810 [(parallel [(match_operand:TI 0 "" "")
811 (match_operand:TI 1 "register_operand" "d")
812 (match_operand:DI 2 "register_operand" "=&a")])]
815 gcc_assert (MEM_P (operands[0]));
816 s390_load_address (operands[2], find_replacement (&XEXP (operands[0], 0)));
817 operands[0] = replace_equiv_address (operands[0], operands[2]);
818 emit_move_insn (operands[0], operands[1]);
823 ; movdi instruction pattern(s).
826 (define_expand "movdi"
827 [(set (match_operand:DI 0 "general_operand" "")
828 (match_operand:DI 1 "general_operand" ""))]
831 /* Handle symbolic constants. */
832 if (TARGET_64BIT && SYMBOLIC_CONST (operands[1]))
833 emit_symbolic_move (operands);
836 (define_insn "*movdi_larl"
837 [(set (match_operand:DI 0 "register_operand" "=d")
838 (match_operand:DI 1 "larl_operand" "X"))]
840 && !FP_REG_P (operands[0])"
842 [(set_attr "op_type" "RIL")
843 (set_attr "type" "larl")])
845 (define_insn "*movdi_64"
846 [(set (match_operand:DI 0 "nonimmediate_operand"
847 "=d,d,d,d,d,d,d,d,m,!*f,!*f,!*f,!R,!T,d,t,Q,t,?Q")
848 (match_operand:DI 1 "general_operand"
849 "K,N0HD0,N1HD0,N2HD0,N3HD0,L,d,m,d,*f,R,T,*f,*f,t,d,t,Q,?Q"))]
871 [(set_attr "op_type" "RI,RI,RI,RI,RI,RXY,RRE,RXY,RXY,
872 RR,RX,RXY,RX,RXY,*,*,RS,RS,SS")
873 (set_attr "type" "*,*,*,*,*,la,lr,load,store,
874 floadd,floadd,floadd,fstored,fstored,*,*,*,*,*")])
877 [(set (match_operand:DI 0 "register_operand" "")
878 (match_operand:DI 1 "register_operand" ""))]
879 "TARGET_64BIT && ACCESS_REG_P (operands[1])"
880 [(set (match_dup 2) (match_dup 3))
881 (set (match_dup 0) (ashift:DI (match_dup 0) (const_int 32)))
882 (set (strict_low_part (match_dup 2)) (match_dup 4))]
883 "operands[2] = gen_lowpart (SImode, operands[0]);
884 s390_split_access_reg (operands[1], &operands[4], &operands[3]);")
887 [(set (match_operand:DI 0 "register_operand" "")
888 (match_operand:DI 1 "register_operand" ""))]
889 "TARGET_64BIT && ACCESS_REG_P (operands[0])
890 && dead_or_set_p (insn, operands[1])"
891 [(set (match_dup 3) (match_dup 2))
892 (set (match_dup 1) (lshiftrt:DI (match_dup 1) (const_int 32)))
893 (set (match_dup 4) (match_dup 2))]
894 "operands[2] = gen_lowpart (SImode, operands[1]);
895 s390_split_access_reg (operands[0], &operands[3], &operands[4]);")
898 [(set (match_operand:DI 0 "register_operand" "")
899 (match_operand:DI 1 "register_operand" ""))]
900 "TARGET_64BIT && ACCESS_REG_P (operands[0])
901 && !dead_or_set_p (insn, operands[1])"
902 [(set (match_dup 3) (match_dup 2))
903 (set (match_dup 1) (rotate:DI (match_dup 1) (const_int 32)))
904 (set (match_dup 4) (match_dup 2))
905 (set (match_dup 1) (rotate:DI (match_dup 1) (const_int 32)))]
906 "operands[2] = gen_lowpart (SImode, operands[1]);
907 s390_split_access_reg (operands[0], &operands[3], &operands[4]);")
909 (define_insn "*movdi_31"
910 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,Q,d,o,!*f,!*f,!*f,!R,!T,Q")
911 (match_operand:DI 1 "general_operand" "Q,d,dKm,d,*f,R,T,*f,*f,Q"))]
924 [(set_attr "op_type" "RS,RS,*,*,RR,RX,RXY,RX,RXY,SS")
925 (set_attr "type" "lm,stm,*,*,floadd,floadd,floadd,fstored,fstored,*")])
928 [(set (match_operand:DI 0 "nonimmediate_operand" "")
929 (match_operand:DI 1 "general_operand" ""))]
930 "!TARGET_64BIT && reload_completed
931 && s390_split_ok_p (operands[0], operands[1], DImode, 0)"
932 [(set (match_dup 2) (match_dup 4))
933 (set (match_dup 3) (match_dup 5))]
935 operands[2] = operand_subword (operands[0], 0, 0, DImode);
936 operands[3] = operand_subword (operands[0], 1, 0, DImode);
937 operands[4] = operand_subword (operands[1], 0, 0, DImode);
938 operands[5] = operand_subword (operands[1], 1, 0, DImode);
942 [(set (match_operand:DI 0 "nonimmediate_operand" "")
943 (match_operand:DI 1 "general_operand" ""))]
944 "!TARGET_64BIT && reload_completed
945 && s390_split_ok_p (operands[0], operands[1], DImode, 1)"
946 [(set (match_dup 2) (match_dup 4))
947 (set (match_dup 3) (match_dup 5))]
949 operands[2] = operand_subword (operands[0], 1, 0, DImode);
950 operands[3] = operand_subword (operands[0], 0, 0, DImode);
951 operands[4] = operand_subword (operands[1], 1, 0, DImode);
952 operands[5] = operand_subword (operands[1], 0, 0, DImode);
956 [(set (match_operand:DI 0 "register_operand" "")
957 (match_operand:DI 1 "memory_operand" ""))]
958 "!TARGET_64BIT && reload_completed
959 && !FP_REG_P (operands[0])
960 && !s_operand (operands[1], VOIDmode)"
961 [(set (match_dup 0) (match_dup 1))]
963 rtx addr = operand_subword (operands[0], 1, 0, DImode);
964 s390_load_address (addr, XEXP (operands[1], 0));
965 operands[1] = replace_equiv_address (operands[1], addr);
968 (define_expand "reload_outdi"
969 [(parallel [(match_operand:DI 0 "" "")
970 (match_operand:DI 1 "register_operand" "d")
971 (match_operand:SI 2 "register_operand" "=&a")])]
974 gcc_assert (MEM_P (operands[0]));
975 s390_load_address (operands[2], find_replacement (&XEXP (operands[0], 0)));
976 operands[0] = replace_equiv_address (operands[0], operands[2]);
977 emit_move_insn (operands[0], operands[1]);
982 [(set (match_operand:DI 0 "register_operand" "")
983 (mem:DI (match_operand 1 "address_operand" "")))]
985 && !FP_REG_P (operands[0])
986 && GET_CODE (operands[1]) == SYMBOL_REF
987 && CONSTANT_POOL_ADDRESS_P (operands[1])
988 && get_pool_mode (operands[1]) == DImode
989 && legitimate_reload_constant_p (get_pool_constant (operands[1]))"
990 [(set (match_dup 0) (match_dup 2))]
991 "operands[2] = get_pool_constant (operands[1]);")
993 (define_insn "*la_64"
994 [(set (match_operand:DI 0 "register_operand" "=d,d")
995 (match_operand:QI 1 "address_operand" "U,W"))]
1000 [(set_attr "op_type" "RX,RXY")
1001 (set_attr "type" "la")])
1005 [(set (match_operand:DI 0 "register_operand" "")
1006 (match_operand:QI 1 "address_operand" ""))
1007 (clobber (reg:CC 33))])]
1009 && preferred_la_operand_p (operands[1], const0_rtx)"
1010 [(set (match_dup 0) (match_dup 1))]
1014 [(set (match_operand:DI 0 "register_operand" "")
1015 (match_operand:DI 1 "register_operand" ""))
1018 (plus:DI (match_dup 0)
1019 (match_operand:DI 2 "nonmemory_operand" "")))
1020 (clobber (reg:CC 33))])]
1022 && !reg_overlap_mentioned_p (operands[0], operands[2])
1023 && preferred_la_operand_p (operands[1], operands[2])"
1024 [(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 2)))]
1027 (define_expand "reload_indi"
1028 [(parallel [(match_operand:DI 0 "register_operand" "=a")
1029 (match_operand:DI 1 "s390_plus_operand" "")
1030 (match_operand:DI 2 "register_operand" "=&a")])]
1033 s390_expand_plus_operand (operands[0], operands[1], operands[2]);
1038 ; movsi instruction pattern(s).
1041 (define_expand "movsi"
1042 [(set (match_operand:SI 0 "general_operand" "")
1043 (match_operand:SI 1 "general_operand" ""))]
1046 /* Handle symbolic constants. */
1047 if (!TARGET_64BIT && SYMBOLIC_CONST (operands[1]))
1048 emit_symbolic_move (operands);
1051 (define_insn "*movsi_larl"
1052 [(set (match_operand:SI 0 "register_operand" "=d")
1053 (match_operand:SI 1 "larl_operand" "X"))]
1054 "!TARGET_64BIT && TARGET_CPU_ZARCH
1055 && !FP_REG_P (operands[0])"
1057 [(set_attr "op_type" "RIL")
1058 (set_attr "type" "larl")])
1060 (define_insn "*movsi_zarch"
1061 [(set (match_operand:SI 0 "nonimmediate_operand"
1062 "=d,d,d,d,d,d,d,R,T,!*f,!*f,!*f,!R,!T,d,t,Q,t,?Q")
1063 (match_operand:SI 1 "general_operand"
1064 "K,N0HS0,N1HS0,L,d,R,T,d,d,*f,R,T,*f,*f,t,d,t,Q,?Q"))]
1086 [(set_attr "op_type" "RI,RI,RI,RXY,RR,RX,RXY,RX,RXY,
1087 RR,RX,RXY,RX,RXY,RRE,RRE,RS,RS,SS")
1088 (set_attr "type" "*,*,*,la,lr,load,load,store,store,
1089 floads,floads,floads,fstores,fstores,*,*,*,*,*")])
1091 (define_insn "*movsi_esa"
1092 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,R,!*f,!*f,!R,d,t,Q,t,?Q")
1093 (match_operand:SI 1 "general_operand" "K,d,R,d,*f,R,*f,t,d,t,Q,?Q"))]
1108 [(set_attr "op_type" "RI,RR,RX,RX,RR,RX,RX,RRE,RRE,RS,RS,SS")
1109 (set_attr "type" "*,lr,load,store,floads,floads,fstores,*,*,*,*,*")])
1112 [(set (match_operand:SI 0 "register_operand" "")
1113 (mem:SI (match_operand 1 "address_operand" "")))]
1114 "!FP_REG_P (operands[0])
1115 && GET_CODE (operands[1]) == SYMBOL_REF
1116 && CONSTANT_POOL_ADDRESS_P (operands[1])
1117 && get_pool_mode (operands[1]) == SImode
1118 && legitimate_reload_constant_p (get_pool_constant (operands[1]))"
1119 [(set (match_dup 0) (match_dup 2))]
1120 "operands[2] = get_pool_constant (operands[1]);")
1122 (define_insn "*la_31"
1123 [(set (match_operand:SI 0 "register_operand" "=d,d")
1124 (match_operand:QI 1 "address_operand" "U,W"))]
1125 "!TARGET_64BIT && legitimate_la_operand_p (operands[1])"
1129 [(set_attr "op_type" "RX,RXY")
1130 (set_attr "type" "la")])
1134 [(set (match_operand:SI 0 "register_operand" "")
1135 (match_operand:QI 1 "address_operand" ""))
1136 (clobber (reg:CC 33))])]
1138 && preferred_la_operand_p (operands[1], const0_rtx)"
1139 [(set (match_dup 0) (match_dup 1))]
1143 [(set (match_operand:SI 0 "register_operand" "")
1144 (match_operand:SI 1 "register_operand" ""))
1147 (plus:SI (match_dup 0)
1148 (match_operand:SI 2 "nonmemory_operand" "")))
1149 (clobber (reg:CC 33))])]
1151 && !reg_overlap_mentioned_p (operands[0], operands[2])
1152 && preferred_la_operand_p (operands[1], operands[2])"
1153 [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))]
1156 (define_insn "*la_31_and"
1157 [(set (match_operand:SI 0 "register_operand" "=d,d")
1158 (and:SI (match_operand:QI 1 "address_operand" "U,W")
1159 (const_int 2147483647)))]
1164 [(set_attr "op_type" "RX,RXY")
1165 (set_attr "type" "la")])
1167 (define_insn_and_split "*la_31_and_cc"
1168 [(set (match_operand:SI 0 "register_operand" "=d")
1169 (and:SI (match_operand:QI 1 "address_operand" "p")
1170 (const_int 2147483647)))
1171 (clobber (reg:CC 33))]
1174 "&& reload_completed"
1176 (and:SI (match_dup 1) (const_int 2147483647)))]
1178 [(set_attr "op_type" "RX")
1179 (set_attr "type" "la")])
1181 (define_insn "force_la_31"
1182 [(set (match_operand:SI 0 "register_operand" "=d,d")
1183 (match_operand:QI 1 "address_operand" "U,W"))
1184 (use (const_int 0))]
1189 [(set_attr "op_type" "RX")
1190 (set_attr "type" "la")])
1192 (define_expand "reload_insi"
1193 [(parallel [(match_operand:SI 0 "register_operand" "=a")
1194 (match_operand:SI 1 "s390_plus_operand" "")
1195 (match_operand:SI 2 "register_operand" "=&a")])]
1198 s390_expand_plus_operand (operands[0], operands[1], operands[2]);
1203 ; movhi instruction pattern(s).
1206 (define_expand "movhi"
1207 [(set (match_operand:HI 0 "nonimmediate_operand" "")
1208 (match_operand:HI 1 "general_operand" ""))]
1211 /* Make it explicit that loading a register from memory
1212 always sign-extends (at least) to SImode. */
1213 if (optimize && !no_new_pseudos
1214 && register_operand (operands[0], VOIDmode)
1215 && GET_CODE (operands[1]) == MEM)
1217 rtx tmp = gen_reg_rtx (SImode);
1218 rtx ext = gen_rtx_SIGN_EXTEND (SImode, operands[1]);
1219 emit_insn (gen_rtx_SET (VOIDmode, tmp, ext));
1220 operands[1] = gen_lowpart (HImode, tmp);
1224 (define_insn "*movhi"
1225 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d,d,R,T,?Q")
1226 (match_operand:HI 1 "general_operand" "d,n,R,T,d,d,?Q"))]
1236 [(set_attr "op_type" "RR,RI,RX,RXY,RX,RXY,SS")
1237 (set_attr "type" "lr,*,*,*,store,store,*")])
1240 [(set (match_operand:HI 0 "register_operand" "")
1241 (mem:HI (match_operand 1 "address_operand" "")))]
1242 "GET_CODE (operands[1]) == SYMBOL_REF
1243 && CONSTANT_POOL_ADDRESS_P (operands[1])
1244 && get_pool_mode (operands[1]) == HImode
1245 && GET_CODE (get_pool_constant (operands[1])) == CONST_INT"
1246 [(set (match_dup 0) (match_dup 2))]
1247 "operands[2] = get_pool_constant (operands[1]);")
1250 ; movqi instruction pattern(s).
1253 (define_expand "movqi"
1254 [(set (match_operand:QI 0 "nonimmediate_operand" "")
1255 (match_operand:QI 1 "general_operand" ""))]
1258 /* On z/Architecture, zero-extending from memory to register
1259 is just as fast as a QImode load. */
1260 if (TARGET_ZARCH && optimize && !no_new_pseudos
1261 && register_operand (operands[0], VOIDmode)
1262 && GET_CODE (operands[1]) == MEM)
1264 rtx tmp = gen_reg_rtx (word_mode);
1265 rtx ext = gen_rtx_ZERO_EXTEND (word_mode, operands[1]);
1266 emit_insn (gen_rtx_SET (VOIDmode, tmp, ext));
1267 operands[1] = gen_lowpart (QImode, tmp);
1271 (define_insn "*movqi"
1272 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,d,R,T,Q,S,?Q")
1273 (match_operand:QI 1 "general_operand" "d,n,R,T,d,d,n,n,?Q"))]
1285 [(set_attr "op_type" "RR,RI,RX,RXY,RX,RXY,SI,SIY,SS")
1286 (set_attr "type" "lr,*,*,*,store,store,store,store,*")])
1289 [(set (match_operand:QI 0 "nonimmediate_operand" "")
1290 (mem:QI (match_operand 1 "address_operand" "")))]
1291 "GET_CODE (operands[1]) == SYMBOL_REF
1292 && CONSTANT_POOL_ADDRESS_P (operands[1])
1293 && get_pool_mode (operands[1]) == QImode
1294 && GET_CODE (get_pool_constant (operands[1])) == CONST_INT"
1295 [(set (match_dup 0) (match_dup 2))]
1296 "operands[2] = get_pool_constant (operands[1]);")
1299 ; movstrictqi instruction pattern(s).
1302 (define_insn "*movstrictqi"
1303 [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d,d"))
1304 (match_operand:QI 1 "memory_operand" "R,T"))]
1309 [(set_attr "op_type" "RX,RXY")])
1312 ; movstricthi instruction pattern(s).
1315 (define_insn "*movstricthi"
1316 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d,d"))
1317 (match_operand:HI 1 "memory_operand" "Q,S"))
1318 (clobber (reg:CC 33))]
1323 [(set_attr "op_type" "RS,RSY")])
1326 ; movstrictsi instruction pattern(s).
1329 (define_insn "movstrictsi"
1330 [(set (strict_low_part (match_operand:SI 0 "register_operand" "+d,d,d,d"))
1331 (match_operand:SI 1 "general_operand" "d,R,T,t"))]
1338 [(set_attr "op_type" "RR,RX,RXY,RRE")
1339 (set_attr "type" "lr,load,load,*")])
1342 ; movdf instruction pattern(s).
1345 (define_expand "movdf"
1346 [(set (match_operand:DF 0 "nonimmediate_operand" "")
1347 (match_operand:DF 1 "general_operand" ""))]
1351 (define_insn "*movdf_64"
1352 [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,f,R,T,d,d,m,?Q")
1353 (match_operand:DF 1 "general_operand" "f,R,T,f,f,d,m,d,?Q"))]
1365 [(set_attr "op_type" "RR,RX,RXY,RX,RXY,RRE,RXY,RXY,SS")
1366 (set_attr "type" "floadd,floadd,floadd,fstored,fstored,lr,load,store,*")])
1368 (define_insn "*movdf_31"
1369 [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,f,R,T,d,Q,d,o,Q")
1370 (match_operand:DF 1 "general_operand" "f,R,T,f,f,Q,d,dKm,d,Q"))]
1383 [(set_attr "op_type" "RR,RX,RXY,RX,RXY,RS,RS,*,*,SS")
1384 (set_attr "type" "floadd,floadd,floadd,fstored,fstored,lm,stm,*,*,*")])
1387 [(set (match_operand:DF 0 "nonimmediate_operand" "")
1388 (match_operand:DF 1 "general_operand" ""))]
1389 "!TARGET_64BIT && reload_completed
1390 && s390_split_ok_p (operands[0], operands[1], DFmode, 0)"
1391 [(set (match_dup 2) (match_dup 4))
1392 (set (match_dup 3) (match_dup 5))]
1394 operands[2] = operand_subword (operands[0], 0, 0, DFmode);
1395 operands[3] = operand_subword (operands[0], 1, 0, DFmode);
1396 operands[4] = operand_subword (operands[1], 0, 0, DFmode);
1397 operands[5] = operand_subword (operands[1], 1, 0, DFmode);
1401 [(set (match_operand:DF 0 "nonimmediate_operand" "")
1402 (match_operand:DF 1 "general_operand" ""))]
1403 "!TARGET_64BIT && reload_completed
1404 && s390_split_ok_p (operands[0], operands[1], DFmode, 1)"
1405 [(set (match_dup 2) (match_dup 4))
1406 (set (match_dup 3) (match_dup 5))]
1408 operands[2] = operand_subword (operands[0], 1, 0, DFmode);
1409 operands[3] = operand_subword (operands[0], 0, 0, DFmode);
1410 operands[4] = operand_subword (operands[1], 1, 0, DFmode);
1411 operands[5] = operand_subword (operands[1], 0, 0, DFmode);
1415 [(set (match_operand:DF 0 "register_operand" "")
1416 (match_operand:DF 1 "memory_operand" ""))]
1417 "!TARGET_64BIT && reload_completed
1418 && !FP_REG_P (operands[0])
1419 && !s_operand (operands[1], VOIDmode)"
1420 [(set (match_dup 0) (match_dup 1))]
1422 rtx addr = operand_subword (operands[0], 1, 0, DFmode);
1423 s390_load_address (addr, XEXP (operands[1], 0));
1424 operands[1] = replace_equiv_address (operands[1], addr);
1427 (define_expand "reload_outdf"
1428 [(parallel [(match_operand:DF 0 "" "")
1429 (match_operand:DF 1 "register_operand" "d")
1430 (match_operand:SI 2 "register_operand" "=&a")])]
1433 gcc_assert (MEM_P (operands[0]));
1434 s390_load_address (operands[2], find_replacement (&XEXP (operands[0], 0)));
1435 operands[0] = replace_equiv_address (operands[0], operands[2]);
1436 emit_move_insn (operands[0], operands[1]);
1441 ; movsf instruction pattern(s).
1444 (define_insn "movsf"
1445 [(set (match_operand:SF 0 "nonimmediate_operand" "=f,f,f,R,T,d,d,d,R,T,?Q")
1446 (match_operand:SF 1 "general_operand" "f,R,T,f,f,d,R,T,d,d,?Q"))]
1460 [(set_attr "op_type" "RR,RX,RXY,RX,RXY,RR,RX,RXY,RX,RXY,SS")
1461 (set_attr "type" "floads,floads,floads,fstores,fstores,
1462 lr,load,load,store,store,*")])
1465 ; movcc instruction pattern
1468 (define_insn "movcc"
1469 [(set (match_operand:CC 0 "nonimmediate_operand" "=d,c,d,d,d,R,T")
1470 (match_operand:CC 1 "nonimmediate_operand" "d,d,c,R,T,d,d"))]
1480 [(set_attr "op_type" "RR,RI,RRE,RX,RXY,RX,RXY")
1481 (set_attr "type" "lr,*,*,store,store,load,load")])
1484 ; Block move (MVC) patterns.
1488 [(set (match_operand:BLK 0 "memory_operand" "=Q")
1489 (match_operand:BLK 1 "memory_operand" "Q"))
1490 (use (match_operand 2 "const_int_operand" "n"))]
1491 "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
1492 "mvc\t%O0(%2,%R0),%S1"
1493 [(set_attr "op_type" "SS")])
1496 [(set (match_operand 0 "memory_operand" "")
1497 (match_operand 1 "memory_operand" ""))]
1499 && GET_MODE (operands[0]) == GET_MODE (operands[1])
1500 && GET_MODE_SIZE (GET_MODE (operands[0])) > 0"
1502 [(set (match_dup 0) (match_dup 1))
1503 (use (match_dup 2))])]
1505 operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0])));
1506 operands[0] = adjust_address (operands[0], BLKmode, 0);
1507 operands[1] = adjust_address (operands[1], BLKmode, 0);
1512 [(set (match_operand:BLK 0 "memory_operand" "")
1513 (match_operand:BLK 1 "memory_operand" ""))
1514 (use (match_operand 2 "const_int_operand" ""))])
1516 [(set (match_operand:BLK 3 "memory_operand" "")
1517 (match_operand:BLK 4 "memory_operand" ""))
1518 (use (match_operand 5 "const_int_operand" ""))])]
1519 "s390_offset_p (operands[0], operands[3], operands[2])
1520 && s390_offset_p (operands[1], operands[4], operands[2])
1521 && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256"
1523 [(set (match_dup 6) (match_dup 7))
1524 (use (match_dup 8))])]
1525 "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
1526 operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0));
1527 operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));")
1531 ; load_multiple pattern(s).
1533 ; ??? Due to reload problems with replacing registers inside match_parallel
1534 ; we currently support load_multiple/store_multiple only after reload.
1537 (define_expand "load_multiple"
1538 [(match_par_dup 3 [(set (match_operand 0 "" "")
1539 (match_operand 1 "" ""))
1540 (use (match_operand 2 "" ""))])]
1543 enum machine_mode mode;
1549 /* Support only loading a constant number of fixed-point registers from
1550 memory and only bother with this if more than two */
1551 if (GET_CODE (operands[2]) != CONST_INT
1552 || INTVAL (operands[2]) < 2
1553 || INTVAL (operands[2]) > 16
1554 || GET_CODE (operands[1]) != MEM
1555 || GET_CODE (operands[0]) != REG
1556 || REGNO (operands[0]) >= 16)
1559 count = INTVAL (operands[2]);
1560 regno = REGNO (operands[0]);
1561 mode = GET_MODE (operands[0]);
1562 if (mode != SImode && mode != word_mode)
1565 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
1568 if (GET_CODE (XEXP (operands[1], 0)) == REG)
1570 from = XEXP (operands[1], 0);
1573 else if (GET_CODE (XEXP (operands[1], 0)) == PLUS
1574 && GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == REG
1575 && GET_CODE (XEXP (XEXP (operands[1], 0), 1)) == CONST_INT)
1577 from = XEXP (XEXP (operands[1], 0), 0);
1578 off = INTVAL (XEXP (XEXP (operands[1], 0), 1));
1585 from = force_reg (Pmode, XEXP (operands[1], 0));
1589 for (i = 0; i < count; i++)
1590 XVECEXP (operands[3], 0, i)
1591 = gen_rtx_SET (VOIDmode, gen_rtx_REG (mode, regno + i),
1592 change_address (operands[1], mode,
1593 plus_constant (from, off + i * GET_MODE_SIZE (mode))));
1596 (define_insn "*load_multiple_di"
1597 [(match_parallel 0 "load_multiple_operation"
1598 [(set (match_operand:DI 1 "register_operand" "=r")
1599 (match_operand:DI 2 "s_operand" "QS"))])]
1600 "reload_completed && word_mode == DImode"
1602 int words = XVECLEN (operands[0], 0);
1603 operands[0] = gen_rtx_REG (DImode, REGNO (operands[1]) + words - 1);
1604 return "lmg\t%1,%0,%S2";
1606 [(set_attr "op_type" "RSY")
1607 (set_attr "type" "lm")])
1609 (define_insn "*load_multiple_si"
1610 [(match_parallel 0 "load_multiple_operation"
1611 [(set (match_operand:SI 1 "register_operand" "=r,r")
1612 (match_operand:SI 2 "s_operand" "Q,S"))])]
1615 int words = XVECLEN (operands[0], 0);
1616 operands[0] = gen_rtx_REG (SImode, REGNO (operands[1]) + words - 1);
1617 return which_alternative == 0 ? "lm\t%1,%0,%S2" : "lmy\t%1,%0,%S2";
1619 [(set_attr "op_type" "RS,RSY")
1620 (set_attr "type" "lm")])
1623 ; store multiple pattern(s).
1626 (define_expand "store_multiple"
1627 [(match_par_dup 3 [(set (match_operand 0 "" "")
1628 (match_operand 1 "" ""))
1629 (use (match_operand 2 "" ""))])]
1632 enum machine_mode mode;
1638 /* Support only storing a constant number of fixed-point registers to
1639 memory and only bother with this if more than two. */
1640 if (GET_CODE (operands[2]) != CONST_INT
1641 || INTVAL (operands[2]) < 2
1642 || INTVAL (operands[2]) > 16
1643 || GET_CODE (operands[0]) != MEM
1644 || GET_CODE (operands[1]) != REG
1645 || REGNO (operands[1]) >= 16)
1648 count = INTVAL (operands[2]);
1649 regno = REGNO (operands[1]);
1650 mode = GET_MODE (operands[1]);
1651 if (mode != SImode && mode != word_mode)
1654 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
1658 if (GET_CODE (XEXP (operands[0], 0)) == REG)
1660 to = XEXP (operands[0], 0);
1663 else if (GET_CODE (XEXP (operands[0], 0)) == PLUS
1664 && GET_CODE (XEXP (XEXP (operands[0], 0), 0)) == REG
1665 && GET_CODE (XEXP (XEXP (operands[0], 0), 1)) == CONST_INT)
1667 to = XEXP (XEXP (operands[0], 0), 0);
1668 off = INTVAL (XEXP (XEXP (operands[0], 0), 1));
1675 to = force_reg (Pmode, XEXP (operands[0], 0));
1679 for (i = 0; i < count; i++)
1680 XVECEXP (operands[3], 0, i)
1681 = gen_rtx_SET (VOIDmode,
1682 change_address (operands[0], mode,
1683 plus_constant (to, off + i * GET_MODE_SIZE (mode))),
1684 gen_rtx_REG (mode, regno + i));
1687 (define_insn "*store_multiple_di"
1688 [(match_parallel 0 "store_multiple_operation"
1689 [(set (match_operand:DI 1 "s_operand" "=QS")
1690 (match_operand:DI 2 "register_operand" "r"))])]
1691 "reload_completed && word_mode == DImode"
1693 int words = XVECLEN (operands[0], 0);
1694 operands[0] = gen_rtx_REG (DImode, REGNO (operands[2]) + words - 1);
1695 return "stmg\t%2,%0,%S1";
1697 [(set_attr "op_type" "RSY")
1698 (set_attr "type" "stm")])
1701 (define_insn "*store_multiple_si"
1702 [(match_parallel 0 "store_multiple_operation"
1703 [(set (match_operand:SI 1 "s_operand" "=Q,S")
1704 (match_operand:SI 2 "register_operand" "r,r"))])]
1707 int words = XVECLEN (operands[0], 0);
1708 operands[0] = gen_rtx_REG (SImode, REGNO (operands[2]) + words - 1);
1709 return which_alternative == 0 ? "stm\t%2,%0,%S1" : "stmy\t%2,%0,%S1";
1711 [(set_attr "op_type" "RS,RSY")
1712 (set_attr "type" "stm")])
1715 ;; String instructions.
1718 (define_insn "*execute"
1719 [(match_parallel 0 ""
1720 [(unspec [(match_operand 1 "register_operand" "a")
1721 (match_operand:BLK 2 "memory_operand" "R")
1722 (match_operand 3 "" "")] UNSPEC_EXECUTE)])]
1723 "GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT
1724 && GET_MODE_SIZE (GET_MODE (operands[1])) <= UNITS_PER_WORD"
1726 [(set_attr "op_type" "RX")
1727 (set_attr "type" "cs")])
1731 ; strlenM instruction pattern(s).
1734 (define_expand "strlendi"
1735 [(set (reg:QI 0) (match_operand:QI 2 "immediate_operand" ""))
1738 (unspec:DI [(const_int 0)
1739 (match_operand:BLK 1 "memory_operand" "")
1741 (match_operand 3 "immediate_operand" "")] UNSPEC_SRST))
1742 (clobber (scratch:DI))
1743 (clobber (reg:CC 33))])
1745 [(set (match_operand:DI 0 "register_operand" "")
1746 (minus:DI (match_dup 4) (match_dup 5)))
1747 (clobber (reg:CC 33))])]
1750 operands[4] = gen_reg_rtx (DImode);
1751 operands[5] = gen_reg_rtx (DImode);
1752 emit_move_insn (operands[5], force_operand (XEXP (operands[1], 0), NULL_RTX));
1753 operands[1] = replace_equiv_address (operands[1], operands[5]);
1756 (define_insn "*strlendi"
1757 [(set (match_operand:DI 0 "register_operand" "=a")
1758 (unspec:DI [(match_operand:DI 2 "general_operand" "0")
1759 (mem:BLK (match_operand:DI 3 "register_operand" "1"))
1761 (match_operand 4 "immediate_operand" "")] UNSPEC_SRST))
1762 (clobber (match_scratch:DI 1 "=a"))
1763 (clobber (reg:CC 33))]
1765 "srst\t%0,%1\;jo\t.-4"
1766 [(set_attr "length" "8")
1767 (set_attr "type" "vs")])
1769 (define_expand "strlensi"
1770 [(set (reg:QI 0) (match_operand:QI 2 "immediate_operand" ""))
1773 (unspec:SI [(const_int 0)
1774 (match_operand:BLK 1 "memory_operand" "")
1776 (match_operand 3 "immediate_operand" "")] UNSPEC_SRST))
1777 (clobber (scratch:SI))
1778 (clobber (reg:CC 33))])
1780 [(set (match_operand:SI 0 "register_operand" "")
1781 (minus:SI (match_dup 4) (match_dup 5)))
1782 (clobber (reg:CC 33))])]
1785 operands[4] = gen_reg_rtx (SImode);
1786 operands[5] = gen_reg_rtx (SImode);
1787 emit_move_insn (operands[5], force_operand (XEXP (operands[1], 0), NULL_RTX));
1788 operands[1] = replace_equiv_address (operands[1], operands[5]);
1791 (define_insn "*strlensi"
1792 [(set (match_operand:SI 0 "register_operand" "=a")
1793 (unspec:SI [(match_operand:SI 2 "general_operand" "0")
1794 (mem:BLK (match_operand:SI 3 "register_operand" "1"))
1796 (match_operand 4 "immediate_operand" "")] UNSPEC_SRST))
1797 (clobber (match_scratch:SI 1 "=a"))
1798 (clobber (reg:CC 33))]
1800 "srst\t%0,%1\;jo\t.-4"
1801 [(set_attr "length" "8")
1802 (set_attr "type" "vs")])
1805 ; movmemM instruction pattern(s).
1808 (define_expand "movmemdi"
1809 [(set (match_operand:BLK 0 "memory_operand" "")
1810 (match_operand:BLK 1 "memory_operand" ""))
1811 (use (match_operand:DI 2 "general_operand" ""))
1812 (match_operand 3 "" "")]
1814 "s390_expand_movmem (operands[0], operands[1], operands[2]); DONE;")
1816 (define_expand "movmemsi"
1817 [(set (match_operand:BLK 0 "memory_operand" "")
1818 (match_operand:BLK 1 "memory_operand" ""))
1819 (use (match_operand:SI 2 "general_operand" ""))
1820 (match_operand 3 "" "")]
1822 "s390_expand_movmem (operands[0], operands[1], operands[2]); DONE;")
1824 ; Move a block that is up to 256 bytes in length.
1825 ; The block length is taken as (operands[2] % 256) + 1.
1827 (define_expand "movmem_short"
1829 [(set (match_operand:BLK 0 "memory_operand" "")
1830 (match_operand:BLK 1 "memory_operand" ""))
1831 (use (match_operand 2 "nonmemory_operand" ""))
1832 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
1833 (clobber (match_dup 3))])]
1835 "operands[3] = gen_rtx_SCRATCH (Pmode);")
1837 (define_insn "*movmem_short"
1838 [(set (match_operand:BLK 0 "memory_operand" "=Q,Q,Q")
1839 (match_operand:BLK 1 "memory_operand" "Q,Q,Q"))
1840 (use (match_operand 2 "nonmemory_operand" "n,a,a"))
1841 (use (match_operand 3 "immediate_operand" "X,R,X"))
1842 (clobber (match_scratch 4 "=X,X,&a"))]
1843 "(GET_MODE (operands[2]) == Pmode || GET_MODE (operands[2]) == VOIDmode)
1844 && GET_MODE (operands[4]) == Pmode"
1846 [(set_attr "type" "cs")])
1849 [(set (match_operand:BLK 0 "memory_operand" "")
1850 (match_operand:BLK 1 "memory_operand" ""))
1851 (use (match_operand 2 "const_int_operand" ""))
1852 (use (match_operand 3 "immediate_operand" ""))
1853 (clobber (scratch))]
1856 [(set (match_dup 0) (match_dup 1))
1857 (use (match_dup 2))])]
1858 "operands[2] = GEN_INT ((INTVAL (operands[2]) & 0xff) + 1);")
1861 [(set (match_operand:BLK 0 "memory_operand" "")
1862 (match_operand:BLK 1 "memory_operand" ""))
1863 (use (match_operand 2 "register_operand" ""))
1864 (use (match_operand 3 "memory_operand" ""))
1865 (clobber (scratch))]
1868 [(unspec [(match_dup 2) (match_dup 3)
1869 (const_int 0)] UNSPEC_EXECUTE)
1870 (set (match_dup 0) (match_dup 1))
1871 (use (const_int 1))])]
1875 [(set (match_operand:BLK 0 "memory_operand" "")
1876 (match_operand:BLK 1 "memory_operand" ""))
1877 (use (match_operand 2 "register_operand" ""))
1878 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
1879 (clobber (match_operand 3 "register_operand" ""))]
1880 "reload_completed && TARGET_CPU_ZARCH"
1881 [(set (match_dup 3) (label_ref (match_dup 4)))
1883 [(unspec [(match_dup 2) (mem:BLK (match_dup 3))
1884 (label_ref (match_dup 4))] UNSPEC_EXECUTE)
1885 (set (match_dup 0) (match_dup 1))
1886 (use (const_int 1))])]
1887 "operands[4] = gen_label_rtx ();")
1889 ; Move a block of arbitrary length.
1891 (define_expand "movmem_long"
1893 [(clobber (match_dup 2))
1894 (clobber (match_dup 3))
1895 (set (match_operand:BLK 0 "memory_operand" "")
1896 (match_operand:BLK 1 "memory_operand" ""))
1897 (use (match_operand 2 "general_operand" ""))
1899 (clobber (reg:CC 33))])]
1902 enum machine_mode dword_mode = word_mode == DImode ? TImode : DImode;
1903 rtx reg0 = gen_reg_rtx (dword_mode);
1904 rtx reg1 = gen_reg_rtx (dword_mode);
1905 rtx addr0 = gen_lowpart (Pmode, gen_highpart (word_mode, reg0));
1906 rtx addr1 = gen_lowpart (Pmode, gen_highpart (word_mode, reg1));
1907 rtx len0 = gen_lowpart (Pmode, reg0);
1908 rtx len1 = gen_lowpart (Pmode, reg1);
1910 emit_insn (gen_rtx_CLOBBER (VOIDmode, reg0));
1911 emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX));
1912 emit_move_insn (len0, operands[2]);
1914 emit_insn (gen_rtx_CLOBBER (VOIDmode, reg1));
1915 emit_move_insn (addr1, force_operand (XEXP (operands[1], 0), NULL_RTX));
1916 emit_move_insn (len1, operands[2]);
1918 operands[0] = replace_equiv_address_nv (operands[0], addr0);
1919 operands[1] = replace_equiv_address_nv (operands[1], addr1);
1924 (define_insn "*movmem_long_64"
1925 [(clobber (match_operand:TI 0 "register_operand" "=d"))
1926 (clobber (match_operand:TI 1 "register_operand" "=d"))
1927 (set (mem:BLK (subreg:DI (match_operand:TI 2 "register_operand" "0") 0))
1928 (mem:BLK (subreg:DI (match_operand:TI 3 "register_operand" "1") 0)))
1931 (clobber (reg:CC 33))]
1933 "mvcle\t%0,%1,0\;jo\t.-4"
1934 [(set_attr "length" "8")
1935 (set_attr "type" "vs")])
1937 (define_insn "*movmem_long_31"
1938 [(clobber (match_operand:DI 0 "register_operand" "=d"))
1939 (clobber (match_operand:DI 1 "register_operand" "=d"))
1940 (set (mem:BLK (subreg:SI (match_operand:DI 2 "register_operand" "0") 0))
1941 (mem:BLK (subreg:SI (match_operand:DI 3 "register_operand" "1") 0)))
1944 (clobber (reg:CC 33))]
1946 "mvcle\t%0,%1,0\;jo\t.-4"
1947 [(set_attr "length" "8")
1948 (set_attr "type" "vs")])
1951 ; clrmemM instruction pattern(s).
1954 (define_expand "clrmemdi"
1955 [(set (match_operand:BLK 0 "memory_operand" "")
1957 (use (match_operand:DI 1 "general_operand" ""))
1958 (match_operand 2 "" "")]
1960 "s390_expand_clrmem (operands[0], operands[1]); DONE;")
1962 (define_expand "clrmemsi"
1963 [(set (match_operand:BLK 0 "memory_operand" "")
1965 (use (match_operand:SI 1 "general_operand" ""))
1966 (match_operand 2 "" "")]
1968 "s390_expand_clrmem (operands[0], operands[1]); DONE;")
1970 ; Clear a block that is up to 256 bytes in length.
1971 ; The block length is taken as (operands[1] % 256) + 1.
1973 (define_expand "clrmem_short"
1975 [(set (match_operand:BLK 0 "memory_operand" "")
1977 (use (match_operand 1 "nonmemory_operand" ""))
1978 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
1979 (clobber (match_dup 2))
1980 (clobber (reg:CC 33))])]
1982 "operands[2] = gen_rtx_SCRATCH (Pmode);")
1984 (define_insn "*clrmem_short"
1985 [(set (match_operand:BLK 0 "memory_operand" "=Q,Q,Q")
1987 (use (match_operand 1 "nonmemory_operand" "n,a,a"))
1988 (use (match_operand 2 "immediate_operand" "X,R,X"))
1989 (clobber (match_scratch 3 "=X,X,&a"))
1990 (clobber (reg:CC 33))]
1991 "(GET_MODE (operands[1]) == Pmode || GET_MODE (operands[1]) == VOIDmode)
1992 && GET_MODE (operands[3]) == Pmode"
1994 [(set_attr "type" "cs")])
1997 [(set (match_operand:BLK 0 "memory_operand" "")
1999 (use (match_operand 1 "const_int_operand" ""))
2000 (use (match_operand 2 "immediate_operand" ""))
2002 (clobber (reg:CC 33))]
2005 [(set (match_dup 0) (const_int 0))
2007 (clobber (reg:CC 33))])]
2008 "operands[1] = GEN_INT ((INTVAL (operands[1]) & 0xff) + 1);")
2011 [(set (match_operand:BLK 0 "memory_operand" "")
2013 (use (match_operand 1 "register_operand" ""))
2014 (use (match_operand 2 "memory_operand" ""))
2016 (clobber (reg:CC 33))]
2019 [(unspec [(match_dup 1) (match_dup 2)
2020 (const_int 0)] UNSPEC_EXECUTE)
2021 (set (match_dup 0) (const_int 0))
2023 (clobber (reg:CC 33))])]
2027 [(set (match_operand:BLK 0 "memory_operand" "")
2029 (use (match_operand 1 "register_operand" ""))
2030 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
2031 (clobber (match_operand 2 "register_operand" ""))
2032 (clobber (reg:CC 33))]
2033 "reload_completed && TARGET_CPU_ZARCH"
2034 [(set (match_dup 2) (label_ref (match_dup 3)))
2036 [(unspec [(match_dup 1) (mem:BLK (match_dup 2))
2037 (label_ref (match_dup 3))] UNSPEC_EXECUTE)
2038 (set (match_dup 0) (const_int 0))
2040 (clobber (reg:CC 33))])]
2041 "operands[3] = gen_label_rtx ();")
2043 ; Clear a block of arbitrary length.
2045 (define_expand "clrmem_long"
2047 [(clobber (match_dup 1))
2048 (set (match_operand:BLK 0 "memory_operand" "")
2050 (use (match_operand 1 "general_operand" ""))
2052 (clobber (reg:CC 33))])]
2055 enum machine_mode dword_mode = word_mode == DImode ? TImode : DImode;
2056 rtx reg0 = gen_reg_rtx (dword_mode);
2057 rtx reg1 = gen_reg_rtx (dword_mode);
2058 rtx addr0 = gen_lowpart (Pmode, gen_highpart (word_mode, reg0));
2059 rtx len0 = gen_lowpart (Pmode, reg0);
2061 emit_insn (gen_rtx_CLOBBER (VOIDmode, reg0));
2062 emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX));
2063 emit_move_insn (len0, operands[1]);
2065 emit_move_insn (reg1, const0_rtx);
2067 operands[0] = replace_equiv_address_nv (operands[0], addr0);
2072 (define_insn "*clrmem_long_64"
2073 [(clobber (match_operand:TI 0 "register_operand" "=d"))
2074 (set (mem:BLK (subreg:DI (match_operand:TI 2 "register_operand" "0") 0))
2077 (use (match_operand:TI 1 "register_operand" "d"))
2078 (clobber (reg:CC 33))]
2080 "mvcle\t%0,%1,0\;jo\t.-4"
2081 [(set_attr "length" "8")
2082 (set_attr "type" "vs")])
2084 (define_insn "*clrmem_long_31"
2085 [(clobber (match_operand:DI 0 "register_operand" "=d"))
2086 (set (mem:BLK (subreg:SI (match_operand:DI 2 "register_operand" "0") 0))
2089 (use (match_operand:DI 1 "register_operand" "d"))
2090 (clobber (reg:CC 33))]
2092 "mvcle\t%0,%1,0\;jo\t.-4"
2093 [(set_attr "length" "8")
2094 (set_attr "type" "vs")])
2097 ; cmpmemM instruction pattern(s).
2100 (define_expand "cmpmemsi"
2101 [(set (match_operand:SI 0 "register_operand" "")
2102 (compare:SI (match_operand:BLK 1 "memory_operand" "")
2103 (match_operand:BLK 2 "memory_operand" "") ) )
2104 (use (match_operand:SI 3 "general_operand" ""))
2105 (use (match_operand:SI 4 "" ""))]
2107 "s390_expand_cmpmem (operands[0], operands[1],
2108 operands[2], operands[3]); DONE;")
2110 ; Compare a block that is up to 256 bytes in length.
2111 ; The block length is taken as (operands[2] % 256) + 1.
2113 (define_expand "cmpmem_short"
2116 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
2117 (match_operand:BLK 1 "memory_operand" "")))
2118 (use (match_operand 2 "nonmemory_operand" ""))
2119 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
2120 (clobber (match_dup 3))])]
2122 "operands[3] = gen_rtx_SCRATCH (Pmode);")
2124 (define_insn "*cmpmem_short"
2126 (compare:CCU (match_operand:BLK 0 "memory_operand" "Q,Q,Q")
2127 (match_operand:BLK 1 "memory_operand" "Q,Q,Q")))
2128 (use (match_operand 2 "nonmemory_operand" "n,a,a"))
2129 (use (match_operand 3 "immediate_operand" "X,R,X"))
2130 (clobber (match_scratch 4 "=X,X,&a"))]
2131 "(GET_MODE (operands[2]) == Pmode || GET_MODE (operands[2]) == VOIDmode)
2132 && GET_MODE (operands[4]) == Pmode"
2134 [(set_attr "type" "cs")])
2138 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
2139 (match_operand:BLK 1 "memory_operand" "")))
2140 (use (match_operand 2 "const_int_operand" ""))
2141 (use (match_operand 3 "immediate_operand" ""))
2142 (clobber (scratch))]
2145 [(set (reg:CCU 33) (compare:CCU (match_dup 0) (match_dup 1)))
2146 (use (match_dup 2))])]
2147 "operands[2] = GEN_INT ((INTVAL (operands[2]) & 0xff) + 1);")
2151 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
2152 (match_operand:BLK 1 "memory_operand" "")))
2153 (use (match_operand 2 "register_operand" ""))
2154 (use (match_operand 3 "memory_operand" ""))
2155 (clobber (scratch))]
2158 [(unspec [(match_dup 2) (match_dup 3)
2159 (const_int 0)] UNSPEC_EXECUTE)
2160 (set (reg:CCU 33) (compare:CCU (match_dup 0) (match_dup 1)))
2161 (use (const_int 1))])]
2166 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
2167 (match_operand:BLK 1 "memory_operand" "")))
2168 (use (match_operand 2 "register_operand" ""))
2169 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
2170 (clobber (match_operand 3 "register_operand" ""))]
2171 "reload_completed && TARGET_CPU_ZARCH"
2172 [(set (match_dup 3) (label_ref (match_dup 4)))
2174 [(unspec [(match_dup 2) (mem:BLK (match_dup 3))
2175 (label_ref (match_dup 4))] UNSPEC_EXECUTE)
2176 (set (reg:CCU 33) (compare:CCU (match_dup 0) (match_dup 1)))
2177 (use (const_int 1))])]
2178 "operands[4] = gen_label_rtx ();")
2180 ; Compare a block of arbitrary length.
2182 (define_expand "cmpmem_long"
2184 [(clobber (match_dup 2))
2185 (clobber (match_dup 3))
2187 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
2188 (match_operand:BLK 1 "memory_operand" "")))
2189 (use (match_operand 2 "general_operand" ""))
2190 (use (match_dup 3))])]
2193 enum machine_mode dword_mode = word_mode == DImode ? TImode : DImode;
2194 rtx reg0 = gen_reg_rtx (dword_mode);
2195 rtx reg1 = gen_reg_rtx (dword_mode);
2196 rtx addr0 = gen_lowpart (Pmode, gen_highpart (word_mode, reg0));
2197 rtx addr1 = gen_lowpart (Pmode, gen_highpart (word_mode, reg1));
2198 rtx len0 = gen_lowpart (Pmode, reg0);
2199 rtx len1 = gen_lowpart (Pmode, reg1);
2201 emit_insn (gen_rtx_CLOBBER (VOIDmode, reg0));
2202 emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX));
2203 emit_move_insn (len0, operands[2]);
2205 emit_insn (gen_rtx_CLOBBER (VOIDmode, reg1));
2206 emit_move_insn (addr1, force_operand (XEXP (operands[1], 0), NULL_RTX));
2207 emit_move_insn (len1, operands[2]);
2209 operands[0] = replace_equiv_address_nv (operands[0], addr0);
2210 operands[1] = replace_equiv_address_nv (operands[1], addr1);
2215 (define_insn "*cmpmem_long_64"
2216 [(clobber (match_operand:TI 0 "register_operand" "=d"))
2217 (clobber (match_operand:TI 1 "register_operand" "=d"))
2219 (compare:CCU (mem:BLK (subreg:DI (match_operand:TI 2 "register_operand" "0") 0))
2220 (mem:BLK (subreg:DI (match_operand:TI 3 "register_operand" "1") 0))))
2222 (use (match_dup 3))]
2224 "clcle\t%0,%1,0\;jo\t.-4"
2225 [(set_attr "length" "8")
2226 (set_attr "type" "vs")])
2228 (define_insn "*cmpmem_long_31"
2229 [(clobber (match_operand:DI 0 "register_operand" "=d"))
2230 (clobber (match_operand:DI 1 "register_operand" "=d"))
2232 (compare:CCU (mem:BLK (subreg:SI (match_operand:DI 2 "register_operand" "0") 0))
2233 (mem:BLK (subreg:SI (match_operand:DI 3 "register_operand" "1") 0))))
2235 (use (match_dup 3))]
2237 "clcle\t%0,%1,0\;jo\t.-4"
2238 [(set_attr "length" "8")
2239 (set_attr "type" "vs")])
2241 ; Convert CCUmode condition code to integer.
2242 ; Result is zero if EQ, positive if LTU, negative if GTU.
2244 (define_insn_and_split "cmpint"
2245 [(set (match_operand:SI 0 "register_operand" "=d")
2246 (unspec:SI [(match_operand:CCU 1 "register_operand" "0")]
2248 (clobber (reg:CC 33))]
2252 [(set (match_dup 0) (ashift:SI (match_dup 0) (const_int 2)))
2254 [(set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 30)))
2255 (clobber (reg:CC 33))])])
2257 (define_insn_and_split "*cmpint_cc"
2259 (compare (unspec:SI [(match_operand:CCU 1 "register_operand" "0")]
2262 (set (match_operand:SI 0 "register_operand" "=d")
2263 (unspec:SI [(match_dup 1)] UNSPEC_CMPINT))]
2264 "s390_match_ccmode (insn, CCSmode)"
2266 "&& reload_completed"
2267 [(set (match_dup 0) (ashift:SI (match_dup 0) (const_int 2)))
2269 [(set (match_dup 2) (match_dup 3))
2270 (set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 30)))])]
2272 rtx result = gen_rtx_ASHIFTRT (SImode, operands[0], GEN_INT (30));
2273 operands[2] = SET_DEST (XVECEXP (PATTERN (curr_insn), 0, 0));
2274 operands[3] = gen_rtx_COMPARE (GET_MODE (operands[2]), result, const0_rtx);
2277 (define_insn_and_split "*cmpint_sign"
2278 [(set (match_operand:DI 0 "register_operand" "=d")
2279 (sign_extend:DI (unspec:SI [(match_operand:CCU 1 "register_operand" "0")]
2281 (clobber (reg:CC 33))]
2284 "&& reload_completed"
2285 [(set (match_dup 0) (ashift:DI (match_dup 0) (const_int 34)))
2287 [(set (match_dup 0) (ashiftrt:DI (match_dup 0) (const_int 62)))
2288 (clobber (reg:CC 33))])])
2290 (define_insn_and_split "*cmpint_sign_cc"
2292 (compare (ashiftrt:DI (ashift:DI (subreg:DI
2293 (unspec:SI [(match_operand:CCU 1 "register_operand" "0")]
2295 (const_int 32)) (const_int 32))
2297 (set (match_operand:DI 0 "register_operand" "=d")
2298 (sign_extend:DI (unspec:SI [(match_dup 1)] UNSPEC_CMPINT)))]
2299 "s390_match_ccmode (insn, CCSmode) && TARGET_64BIT"
2301 "&& reload_completed"
2302 [(set (match_dup 0) (ashift:DI (match_dup 0) (const_int 34)))
2304 [(set (match_dup 2) (match_dup 3))
2305 (set (match_dup 0) (ashiftrt:DI (match_dup 0) (const_int 62)))])]
2307 rtx result = gen_rtx_ASHIFTRT (DImode, operands[0], GEN_INT (62));
2308 operands[2] = SET_DEST (XVECEXP (PATTERN (curr_insn), 0, 0));
2309 operands[3] = gen_rtx_COMPARE (GET_MODE (operands[2]), result, const0_rtx);
2314 ;;- Conversion instructions.
2318 (define_insn "*sethigh<mode>si"
2319 [(set (match_operand:SI 0 "register_operand" "=d,d")
2320 (unspec:SI [(match_operand:HQI 1 "s_operand" "Q,S")] UNSPEC_SETHIGH))
2321 (clobber (reg:CC 33))]
2324 icm\t%0,<icm_hi>,%S1
2325 icmy\t%0,<icm_hi>,%S1"
2326 [(set_attr "op_type" "RS,RSY")])
2328 (define_insn "*sethighqidi_64"
2329 [(set (match_operand:DI 0 "register_operand" "=d")
2330 (unspec:DI [(match_operand:QI 1 "s_operand" "QS")] UNSPEC_SETHIGH))
2331 (clobber (reg:CC 33))]
2334 [(set_attr "op_type" "RSY")])
2336 (define_insn "*sethighqidi_31"
2337 [(set (match_operand:DI 0 "register_operand" "=d,d")
2338 (unspec:DI [(match_operand:QI 1 "s_operand" "Q,S")] UNSPEC_SETHIGH))
2339 (clobber (reg:CC 33))]
2344 [(set_attr "op_type" "RS,RSY")])
2346 (define_insn_and_split "*extractqi"
2347 [(set (match_operand:SI 0 "register_operand" "=d")
2348 (zero_extract:SI (match_operand:QI 1 "s_operand" "Q")
2349 (match_operand 2 "const_int_operand" "n")
2351 (clobber (reg:CC 33))]
2353 && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 8"
2355 "&& reload_completed"
2357 [(set (match_dup 0) (unspec:SI [(match_dup 1)] UNSPEC_SETHIGH))
2358 (clobber (reg:CC 33))])
2359 (set (match_dup 0) (lshiftrt:SI (match_dup 0) (match_dup 2)))]
2361 operands[2] = GEN_INT (32 - INTVAL (operands[2]));
2362 operands[1] = change_address (operands[1], QImode, 0);
2365 (define_insn_and_split "*extracthi"
2366 [(set (match_operand:SI 0 "register_operand" "=d")
2367 (zero_extract:SI (match_operand:QI 1 "s_operand" "Q")
2368 (match_operand 2 "const_int_operand" "n")
2370 (clobber (reg:CC 33))]
2372 && INTVAL (operands[2]) >= 8 && INTVAL (operands[2]) < 16"
2374 "&& reload_completed"
2376 [(set (match_dup 0) (unspec:SI [(match_dup 1)] UNSPEC_SETHIGH))
2377 (clobber (reg:CC 33))])
2378 (set (match_dup 0) (lshiftrt:SI (match_dup 0) (match_dup 2)))]
2380 operands[2] = GEN_INT (32 - INTVAL (operands[2]));
2381 operands[1] = change_address (operands[1], HImode, 0);
2385 ; extendsidi2 instruction pattern(s).
2388 (define_expand "extendsidi2"
2389 [(set (match_operand:DI 0 "register_operand" "")
2390 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))]
2396 emit_insn (gen_rtx_CLOBBER (VOIDmode, operands[0]));
2397 emit_move_insn (gen_highpart (SImode, operands[0]), operands[1]);
2398 emit_move_insn (gen_lowpart (SImode, operands[0]), const0_rtx);
2399 emit_insn (gen_ashrdi3 (operands[0], operands[0], GEN_INT (32)));
2405 (define_insn "*extendsidi2"
2406 [(set (match_operand:DI 0 "register_operand" "=d,d")
2407 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,m")))]
2412 [(set_attr "op_type" "RRE,RXY")])
2415 ; extendhidi2 instruction pattern(s).
2418 (define_expand "extendhidi2"
2419 [(set (match_operand:DI 0 "register_operand" "")
2420 (sign_extend:DI (match_operand:HI 1 "register_operand" "")))]
2426 rtx tmp = gen_reg_rtx (SImode);
2427 emit_insn (gen_extendhisi2 (tmp, operands[1]));
2428 emit_insn (gen_extendsidi2 (operands[0], tmp));
2433 operands[1] = gen_lowpart (DImode, operands[1]);
2434 emit_insn (gen_ashldi3 (operands[0], operands[1], GEN_INT (48)));
2435 emit_insn (gen_ashrdi3 (operands[0], operands[0], GEN_INT (48)));
2441 (define_insn "*extendhidi2"
2442 [(set (match_operand:DI 0 "register_operand" "=d")
2443 (sign_extend:DI (match_operand:HI 1 "memory_operand" "m")))]
2446 [(set_attr "op_type" "RXY")])
2449 ; extendqidi2 instruction pattern(s).
2452 (define_expand "extendqidi2"
2453 [(set (match_operand:DI 0 "register_operand" "")
2454 (sign_extend:DI (match_operand:QI 1 "register_operand" "")))]
2460 rtx tmp = gen_reg_rtx (SImode);
2461 emit_insn (gen_extendqisi2 (tmp, operands[1]));
2462 emit_insn (gen_extendsidi2 (operands[0], tmp));
2467 operands[1] = gen_lowpart (DImode, operands[1]);
2468 emit_insn (gen_ashldi3 (operands[0], operands[1], GEN_INT (56)));
2469 emit_insn (gen_ashrdi3 (operands[0], operands[0], GEN_INT (56)));
2475 (define_insn "*extendqidi2"
2476 [(set (match_operand:DI 0 "register_operand" "=d")
2477 (sign_extend:DI (match_operand:QI 1 "memory_operand" "m")))]
2478 "TARGET_64BIT && TARGET_LONG_DISPLACEMENT"
2480 [(set_attr "op_type" "RXY")])
2482 (define_insn_and_split "*extendqidi2_short_displ"
2483 [(set (match_operand:DI 0 "register_operand" "=d")
2484 (sign_extend:DI (match_operand:QI 1 "s_operand" "Q")))
2485 (clobber (reg:CC 33))]
2486 "TARGET_64BIT && !TARGET_LONG_DISPLACEMENT"
2488 "&& reload_completed"
2490 [(set (match_dup 0) (unspec:DI [(match_dup 1)] UNSPEC_SETHIGH))
2491 (clobber (reg:CC 33))])
2493 [(set (match_dup 0) (ashiftrt:DI (match_dup 0) (const_int 56)))
2494 (clobber (reg:CC 33))])]
2498 ; extendhisi2 instruction pattern(s).
2501 (define_expand "extendhisi2"
2502 [(set (match_operand:SI 0 "register_operand" "")
2503 (sign_extend:SI (match_operand:HI 1 "register_operand" "")))]
2507 operands[1] = gen_lowpart (SImode, operands[1]);
2508 emit_insn (gen_ashlsi3 (operands[0], operands[1], GEN_INT (16)));
2509 emit_insn (gen_ashrsi3 (operands[0], operands[0], GEN_INT (16)));
2514 (define_insn "*extendhisi2"
2515 [(set (match_operand:SI 0 "register_operand" "=d,d")
2516 (sign_extend:SI (match_operand:HI 1 "memory_operand" "R,T")))]
2521 [(set_attr "op_type" "RX,RXY")])
2524 ; extendqisi2 instruction pattern(s).
2527 (define_expand "extendqisi2"
2528 [(set (match_operand:SI 0 "register_operand" "")
2529 (sign_extend:SI (match_operand:QI 1 "register_operand" "")))]
2533 operands[1] = gen_lowpart (SImode, operands[1]);
2534 emit_insn (gen_ashlsi3 (operands[0], operands[1], GEN_INT (24)));
2535 emit_insn (gen_ashrsi3 (operands[0], operands[0], GEN_INT (24)));
2540 (define_insn "*extendqisi2"
2541 [(set (match_operand:SI 0 "register_operand" "=d")
2542 (sign_extend:SI (match_operand:QI 1 "memory_operand" "m")))]
2543 "TARGET_LONG_DISPLACEMENT"
2545 [(set_attr "op_type" "RXY")])
2547 (define_insn_and_split "*extendqisi2_short_displ"
2548 [(set (match_operand:SI 0 "register_operand" "=d")
2549 (sign_extend:SI (match_operand:QI 1 "s_operand" "Q")))
2550 (clobber (reg:CC 33))]
2551 "!TARGET_LONG_DISPLACEMENT"
2553 "&& reload_completed"
2555 [(set (match_dup 0) (unspec:SI [(match_dup 1)] UNSPEC_SETHIGH))
2556 (clobber (reg:CC 33))])
2558 [(set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 24)))
2559 (clobber (reg:CC 33))])]
2563 ; extendqihi2 instruction pattern(s).
2568 ; zero_extendsidi2 instruction pattern(s).
2571 (define_expand "zero_extendsidi2"
2572 [(set (match_operand:DI 0 "register_operand" "")
2573 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))]
2579 emit_insn (gen_rtx_CLOBBER (VOIDmode, operands[0]));
2580 emit_move_insn (gen_lowpart (SImode, operands[0]), operands[1]);
2581 emit_move_insn (gen_highpart (SImode, operands[0]), const0_rtx);
2587 (define_insn "*zero_extendsidi2"
2588 [(set (match_operand:DI 0 "register_operand" "=d,d")
2589 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,m")))]
2594 [(set_attr "op_type" "RRE,RXY")])
2597 ; zero_extendhidi2 instruction pattern(s).
2600 (define_expand "zero_extendhidi2"
2601 [(set (match_operand:DI 0 "register_operand" "")
2602 (zero_extend:DI (match_operand:HI 1 "register_operand" "")))]
2608 rtx tmp = gen_reg_rtx (SImode);
2609 emit_insn (gen_zero_extendhisi2 (tmp, operands[1]));
2610 emit_insn (gen_zero_extendsidi2 (operands[0], tmp));
2615 operands[1] = gen_lowpart (DImode, operands[1]);
2616 emit_insn (gen_ashldi3 (operands[0], operands[1], GEN_INT (48)));
2617 emit_insn (gen_lshrdi3 (operands[0], operands[0], GEN_INT (48)));
2623 (define_insn "*zero_extendhidi2"
2624 [(set (match_operand:DI 0 "register_operand" "=d")
2625 (zero_extend:DI (match_operand:HI 1 "memory_operand" "m")))]
2628 [(set_attr "op_type" "RXY")])
2631 ; LLGT-type instructions (zero-extend from 31 bit to 64 bit).
2634 (define_insn "*llgt_sidi"
2635 [(set (match_operand:DI 0 "register_operand" "=d")
2636 (and:DI (subreg:DI (match_operand:SI 1 "memory_operand" "m") 0)
2637 (const_int 2147483647)))]
2640 [(set_attr "op_type" "RXE")])
2642 (define_insn_and_split "*llgt_sidi_split"
2643 [(set (match_operand:DI 0 "register_operand" "=d")
2644 (and:DI (subreg:DI (match_operand:SI 1 "memory_operand" "m") 0)
2645 (const_int 2147483647)))
2646 (clobber (reg:CC 33))]
2649 "&& reload_completed"
2651 (and:DI (subreg:DI (match_dup 1) 0)
2652 (const_int 2147483647)))]
2655 (define_insn "*llgt_sisi"
2656 [(set (match_operand:SI 0 "register_operand" "=d,d")
2657 (and:SI (match_operand:SI 1 "nonimmediate_operand" "d,m")
2658 (const_int 2147483647)))]
2663 [(set_attr "op_type" "RRE,RXE")])
2666 [(set (match_operand:SI 0 "register_operand" "")
2667 (and:SI (match_operand:SI 1 "nonimmediate_operand" "")
2668 (const_int 2147483647)))
2669 (clobber (reg:CC 33))]
2670 "TARGET_64BIT && reload_completed"
2672 (and:SI (match_dup 1)
2673 (const_int 2147483647)))]
2676 (define_insn "*llgt_didi"
2677 [(set (match_operand:DI 0 "register_operand" "=d,d")
2678 (and:DI (match_operand:DI 1 "nonimmediate_operand" "d,o")
2679 (const_int 2147483647)))]
2684 [(set_attr "op_type" "RRE,RXE")])
2687 [(set (match_operand:DI 0 "register_operand" "")
2688 (and:DI (match_operand:DI 1 "nonimmediate_operand" "")
2689 (const_int 2147483647)))
2690 (clobber (reg:CC 33))]
2691 "TARGET_64BIT && reload_completed"
2693 (and:DI (match_dup 1)
2694 (const_int 2147483647)))]
2698 ; zero_extendqidi2 instruction pattern(s)
2701 (define_expand "zero_extendqidi2"
2702 [(set (match_operand:DI 0 "register_operand" "")
2703 (zero_extend:DI (match_operand:QI 1 "register_operand" "")))]
2709 rtx tmp = gen_reg_rtx (SImode);
2710 emit_insn (gen_zero_extendqisi2 (tmp, operands[1]));
2711 emit_insn (gen_zero_extendsidi2 (operands[0], tmp));
2716 operands[1] = gen_lowpart (DImode, operands[1]);
2717 emit_insn (gen_ashldi3 (operands[0], operands[1], GEN_INT (56)));
2718 emit_insn (gen_lshrdi3 (operands[0], operands[0], GEN_INT (56)));
2724 (define_insn "*zero_extendqidi2"
2725 [(set (match_operand:DI 0 "register_operand" "=d")
2726 (zero_extend:DI (match_operand:QI 1 "memory_operand" "m")))]
2729 [(set_attr "op_type" "RXY")])
2732 ; zero_extendhisi2 instruction pattern(s).
2735 (define_expand "zero_extendhisi2"
2736 [(set (match_operand:SI 0 "register_operand" "")
2737 (zero_extend:SI (match_operand:HI 1 "register_operand" "")))]
2741 operands[1] = gen_lowpart (SImode, operands[1]);
2742 emit_insn (gen_andsi3 (operands[0], operands[1], GEN_INT (0xffff)));
2747 (define_insn "*zero_extendhisi2_64"
2748 [(set (match_operand:SI 0 "register_operand" "=d")
2749 (zero_extend:SI (match_operand:HI 1 "memory_operand" "m")))]
2752 [(set_attr "op_type" "RXY")])
2754 (define_insn_and_split "*zero_extendhisi2_31"
2755 [(set (match_operand:SI 0 "register_operand" "=&d")
2756 (zero_extend:SI (match_operand:HI 1 "s_operand" "QS")))
2757 (clobber (reg:CC 33))]
2760 "&& reload_completed"
2761 [(set (match_dup 0) (const_int 0))
2763 [(set (strict_low_part (match_dup 2)) (match_dup 1))
2764 (clobber (reg:CC 33))])]
2765 "operands[2] = gen_lowpart (HImode, operands[0]);")
2768 ; zero_extendqisi2 instruction pattern(s).
2771 (define_expand "zero_extendqisi2"
2772 [(set (match_operand:SI 0 "register_operand" "")
2773 (zero_extend:SI (match_operand:QI 1 "register_operand" "")))]
2777 operands[1] = gen_lowpart (SImode, operands[1]);
2778 emit_insn (gen_andsi3 (operands[0], operands[1], GEN_INT (0xff)));
2783 (define_insn "*zero_extendqisi2_64"
2784 [(set (match_operand:SI 0 "register_operand" "=d")
2785 (zero_extend:SI (match_operand:QI 1 "memory_operand" "m")))]
2788 [(set_attr "op_type" "RXY")])
2790 (define_insn_and_split "*zero_extendqisi2_31"
2791 [(set (match_operand:SI 0 "register_operand" "=&d")
2792 (zero_extend:SI (match_operand:QI 1 "memory_operand" "m")))]
2795 "&& reload_completed"
2796 [(set (match_dup 0) (const_int 0))
2797 (set (strict_low_part (match_dup 2)) (match_dup 1))]
2798 "operands[2] = gen_lowpart (QImode, operands[0]);")
2801 ; zero_extendqihi2 instruction pattern(s).
2804 (define_expand "zero_extendqihi2"
2805 [(set (match_operand:HI 0 "register_operand" "")
2806 (zero_extend:HI (match_operand:QI 1 "register_operand" "")))]
2810 operands[1] = gen_lowpart (HImode, operands[1]);
2811 emit_insn (gen_andhi3 (operands[0], operands[1], GEN_INT (0xff)));
2816 (define_insn "*zero_extendqihi2_64"
2817 [(set (match_operand:HI 0 "register_operand" "=d")
2818 (zero_extend:HI (match_operand:QI 1 "memory_operand" "m")))]
2821 [(set_attr "op_type" "RXY")])
2823 (define_insn_and_split "*zero_extendqihi2_31"
2824 [(set (match_operand:HI 0 "register_operand" "=&d")
2825 (zero_extend:HI (match_operand:QI 1 "memory_operand" "m")))]
2828 "&& reload_completed"
2829 [(set (match_dup 0) (const_int 0))
2830 (set (strict_low_part (match_dup 2)) (match_dup 1))]
2831 "operands[2] = gen_lowpart (QImode, operands[0]);")
2835 ; fixuns_truncdfdi2 and fix_truncdfsi2 instruction pattern(s).
2838 (define_expand "fixuns_truncdfdi2"
2839 [(set (match_operand:DI 0 "register_operand" "")
2840 (unsigned_fix:DI (match_operand:DF 1 "register_operand" "")))]
2841 "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2843 rtx label1 = gen_label_rtx ();
2844 rtx label2 = gen_label_rtx ();
2845 rtx temp = gen_reg_rtx (DFmode);
2846 operands[1] = force_reg (DFmode, operands[1]);
2848 emit_insn (gen_cmpdf (operands[1],
2849 CONST_DOUBLE_FROM_REAL_VALUE (
2850 REAL_VALUE_ATOF ("9223372036854775808.0", DFmode), DFmode)));
2851 emit_jump_insn (gen_blt (label1));
2852 emit_insn (gen_subdf3 (temp, operands[1],
2853 CONST_DOUBLE_FROM_REAL_VALUE (
2854 REAL_VALUE_ATOF ("18446744073709551616.0", DFmode), DFmode)));
2855 emit_insn (gen_fix_truncdfdi2_ieee (operands[0], temp, GEN_INT(7)));
2858 emit_label (label1);
2859 emit_insn (gen_fix_truncdfdi2_ieee (operands[0], operands[1], GEN_INT(5)));
2860 emit_label (label2);
2864 (define_expand "fix_truncdfdi2"
2865 [(set (match_operand:DI 0 "register_operand" "")
2866 (fix:DI (match_operand:DF 1 "nonimmediate_operand" "")))]
2867 "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2869 operands[1] = force_reg (DFmode, operands[1]);
2870 emit_insn (gen_fix_truncdfdi2_ieee (operands[0], operands[1], GEN_INT(5)));
2874 (define_insn "fix_truncdfdi2_ieee"
2875 [(set (match_operand:DI 0 "register_operand" "=d")
2876 (fix:DI (match_operand:DF 1 "register_operand" "f")))
2877 (unspec:DI [(match_operand:DI 2 "immediate_operand" "K")] UNSPEC_ROUND)
2878 (clobber (reg:CC 33))]
2879 "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2881 [(set_attr "op_type" "RRE")
2882 (set_attr "type" "ftoi")])
2885 ; fixuns_truncdfsi2 and fix_truncdfsi2 instruction pattern(s).
2888 (define_expand "fixuns_truncdfsi2"
2889 [(set (match_operand:SI 0 "register_operand" "")
2890 (unsigned_fix:SI (match_operand:DF 1 "register_operand" "")))]
2891 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2893 rtx label1 = gen_label_rtx ();
2894 rtx label2 = gen_label_rtx ();
2895 rtx temp = gen_reg_rtx (DFmode);
2897 operands[1] = force_reg (DFmode,operands[1]);
2898 emit_insn (gen_cmpdf (operands[1],
2899 CONST_DOUBLE_FROM_REAL_VALUE (
2900 REAL_VALUE_ATOF ("2147483648.0", DFmode), DFmode)));
2901 emit_jump_insn (gen_blt (label1));
2902 emit_insn (gen_subdf3 (temp, operands[1],
2903 CONST_DOUBLE_FROM_REAL_VALUE (
2904 REAL_VALUE_ATOF ("4294967296.0", DFmode), DFmode)));
2905 emit_insn (gen_fix_truncdfsi2_ieee (operands[0], temp, GEN_INT (7)));
2908 emit_label (label1);
2909 emit_insn (gen_fix_truncdfsi2_ieee (operands[0], operands[1], GEN_INT (5)));
2910 emit_label (label2);
2914 (define_expand "fix_truncdfsi2"
2915 [(set (match_operand:SI 0 "register_operand" "")
2916 (fix:SI (match_operand:DF 1 "nonimmediate_operand" "")))]
2919 if (TARGET_IBM_FLOAT)
2921 /* This is the algorithm from POP chapter A.5.7.2. */
2923 rtx temp = assign_stack_local (BLKmode, 8, BITS_PER_WORD);
2924 rtx two31r = s390_gen_rtx_const_DI (0x4f000000, 0x08000000);
2925 rtx two32 = s390_gen_rtx_const_DI (0x4e000001, 0x00000000);
2927 operands[1] = force_reg (DFmode, operands[1]);
2928 emit_insn (gen_fix_truncdfsi2_ibm (operands[0], operands[1],
2929 two31r, two32, temp));
2933 operands[1] = force_reg (DFmode, operands[1]);
2934 emit_insn (gen_fix_truncdfsi2_ieee (operands[0], operands[1], GEN_INT (5)));
2940 (define_insn "fix_truncdfsi2_ieee"
2941 [(set (match_operand:SI 0 "register_operand" "=d")
2942 (fix:SI (match_operand:DF 1 "register_operand" "f")))
2943 (unspec:SI [(match_operand:SI 2 "immediate_operand" "K")] UNSPEC_ROUND)
2944 (clobber (reg:CC 33))]
2945 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2947 [(set_attr "op_type" "RRE")
2948 (set_attr "type" "ftoi")])
2950 (define_insn "fix_truncdfsi2_ibm"
2951 [(set (match_operand:SI 0 "register_operand" "=d")
2952 (fix:SI (match_operand:DF 1 "nonimmediate_operand" "+f")))
2953 (use (match_operand:DI 2 "immediate_operand" "m"))
2954 (use (match_operand:DI 3 "immediate_operand" "m"))
2955 (use (match_operand:BLK 4 "memory_operand" "m"))
2956 (clobber (reg:CC 33))]
2957 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
2959 output_asm_insn ("sd\t%1,%2", operands);
2960 output_asm_insn ("aw\t%1,%3", operands);
2961 output_asm_insn ("std\t%1,%4", operands);
2962 output_asm_insn ("xi\t%N4,128", operands);
2965 [(set_attr "length" "20")])
2968 ; fixuns_truncsfdi2 and fix_truncsfdi2 instruction pattern(s).
2971 (define_expand "fixuns_truncsfdi2"
2972 [(set (match_operand:DI 0 "register_operand" "")
2973 (unsigned_fix:DI (match_operand:SF 1 "register_operand" "")))]
2974 "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2976 rtx label1 = gen_label_rtx ();
2977 rtx label2 = gen_label_rtx ();
2978 rtx temp = gen_reg_rtx (SFmode);
2980 operands[1] = force_reg (SFmode, operands[1]);
2981 emit_insn (gen_cmpsf (operands[1],
2982 CONST_DOUBLE_FROM_REAL_VALUE (
2983 REAL_VALUE_ATOF ("9223372036854775808.0", SFmode), SFmode)));
2984 emit_jump_insn (gen_blt (label1));
2986 emit_insn (gen_subsf3 (temp, operands[1],
2987 CONST_DOUBLE_FROM_REAL_VALUE (
2988 REAL_VALUE_ATOF ("18446744073709551616.0", SFmode), SFmode)));
2989 emit_insn (gen_fix_truncsfdi2_ieee (operands[0], temp, GEN_INT(7)));
2992 emit_label (label1);
2993 emit_insn (gen_fix_truncsfdi2_ieee (operands[0], operands[1], GEN_INT(5)));
2994 emit_label (label2);
2998 (define_expand "fix_truncsfdi2"
2999 [(set (match_operand:DI 0 "register_operand" "")
3000 (fix:DI (match_operand:SF 1 "nonimmediate_operand" "")))]
3001 "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3003 operands[1] = force_reg (SFmode, operands[1]);
3004 emit_insn (gen_fix_truncsfdi2_ieee (operands[0], operands[1], GEN_INT(5)));
3008 (define_insn "fix_truncsfdi2_ieee"
3009 [(set (match_operand:DI 0 "register_operand" "=d")
3010 (fix:DI (match_operand:SF 1 "register_operand" "f")))
3011 (unspec:DI [(match_operand:DI 2 "immediate_operand" "K")] UNSPEC_ROUND)
3012 (clobber (reg:CC 33))]
3013 "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3015 [(set_attr "op_type" "RRE")
3016 (set_attr "type" "ftoi")])
3019 ; fixuns_truncsfsi2 and fix_truncsfsi2 instruction pattern(s).
3022 (define_expand "fixuns_truncsfsi2"
3023 [(set (match_operand:SI 0 "register_operand" "")
3024 (unsigned_fix:SI (match_operand:SF 1 "register_operand" "")))]
3025 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3027 rtx label1 = gen_label_rtx ();
3028 rtx label2 = gen_label_rtx ();
3029 rtx temp = gen_reg_rtx (SFmode);
3031 operands[1] = force_reg (SFmode, operands[1]);
3032 emit_insn (gen_cmpsf (operands[1],
3033 CONST_DOUBLE_FROM_REAL_VALUE (
3034 REAL_VALUE_ATOF ("2147483648.0", SFmode), SFmode)));
3035 emit_jump_insn (gen_blt (label1));
3036 emit_insn (gen_subsf3 (temp, operands[1],
3037 CONST_DOUBLE_FROM_REAL_VALUE (
3038 REAL_VALUE_ATOF ("4294967296.0", SFmode), SFmode)));
3039 emit_insn (gen_fix_truncsfsi2_ieee (operands[0], temp, GEN_INT (7)));
3042 emit_label (label1);
3043 emit_insn (gen_fix_truncsfsi2_ieee (operands[0], operands[1], GEN_INT (5)));
3044 emit_label (label2);
3048 (define_expand "fix_truncsfsi2"
3049 [(set (match_operand:SI 0 "register_operand" "")
3050 (fix:SI (match_operand:SF 1 "nonimmediate_operand" "")))]
3053 if (TARGET_IBM_FLOAT)
3055 /* Convert to DFmode and then use the POP algorithm. */
3056 rtx temp = gen_reg_rtx (DFmode);
3057 emit_insn (gen_extendsfdf2 (temp, operands[1]));
3058 emit_insn (gen_fix_truncdfsi2 (operands[0], temp));
3062 operands[1] = force_reg (SFmode, operands[1]);
3063 emit_insn (gen_fix_truncsfsi2_ieee (operands[0], operands[1], GEN_INT (5)));
3069 (define_insn "fix_truncsfsi2_ieee"
3070 [(set (match_operand:SI 0 "register_operand" "=d")
3071 (fix:SI (match_operand:SF 1 "register_operand" "f")))
3072 (unspec:SI [(match_operand:SI 2 "immediate_operand" "K")] UNSPEC_ROUND)
3073 (clobber (reg:CC 33))]
3074 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3076 [(set_attr "op_type" "RRE")
3077 (set_attr "type" "ftoi")])
3080 ; floatdidf2 instruction pattern(s).
3083 (define_insn "floatdidf2"
3084 [(set (match_operand:DF 0 "register_operand" "=f")
3085 (float:DF (match_operand:DI 1 "register_operand" "d")))]
3086 "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3088 [(set_attr "op_type" "RRE")
3089 (set_attr "type" "itof" )])
3092 ; floatdisf2 instruction pattern(s).
3095 (define_insn "floatdisf2"
3096 [(set (match_operand:SF 0 "register_operand" "=f")
3097 (float:SF (match_operand:DI 1 "register_operand" "d")))]
3098 "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3100 [(set_attr "op_type" "RRE")
3101 (set_attr "type" "itof" )])
3104 ; floatsidf2 instruction pattern(s).
3107 (define_expand "floatsidf2"
3108 [(set (match_operand:DF 0 "register_operand" "")
3109 (float:DF (match_operand:SI 1 "register_operand" "")))]
3112 if (TARGET_IBM_FLOAT)
3114 /* This is the algorithm from POP chapter A.5.7.1. */
3116 rtx temp = assign_stack_local (BLKmode, 8, BITS_PER_WORD);
3117 rtx two31 = s390_gen_rtx_const_DI (0x4e000000, 0x80000000);
3119 emit_insn (gen_floatsidf2_ibm (operands[0], operands[1], two31, temp));
3124 (define_insn "floatsidf2_ieee"
3125 [(set (match_operand:DF 0 "register_operand" "=f")
3126 (float:DF (match_operand:SI 1 "register_operand" "d")))]
3127 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3129 [(set_attr "op_type" "RRE")
3130 (set_attr "type" "itof" )])
3132 (define_insn "floatsidf2_ibm"
3133 [(set (match_operand:DF 0 "register_operand" "=f")
3134 (float:DF (match_operand:SI 1 "register_operand" "d")))
3135 (use (match_operand:DI 2 "immediate_operand" "m"))
3136 (use (match_operand:BLK 3 "memory_operand" "m"))
3137 (clobber (reg:CC 33))]
3138 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
3140 output_asm_insn ("st\t%1,%N3", operands);
3141 output_asm_insn ("xi\t%N3,128", operands);
3142 output_asm_insn ("mvc\t%O3(4,%R3),%2", operands);
3143 output_asm_insn ("ld\t%0,%3", operands);
3146 [(set_attr "length" "20")])
3149 ; floatsisf2 instruction pattern(s).
3152 (define_expand "floatsisf2"
3153 [(set (match_operand:SF 0 "register_operand" "")
3154 (float:SF (match_operand:SI 1 "register_operand" "")))]
3157 if (TARGET_IBM_FLOAT)
3159 /* Use the POP algorithm to convert to DFmode and then truncate. */
3160 rtx temp = gen_reg_rtx (DFmode);
3161 emit_insn (gen_floatsidf2 (temp, operands[1]));
3162 emit_insn (gen_truncdfsf2 (operands[0], temp));
3167 (define_insn "floatsisf2_ieee"
3168 [(set (match_operand:SF 0 "register_operand" "=f")
3169 (float:SF (match_operand:SI 1 "register_operand" "d")))]
3170 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3172 [(set_attr "op_type" "RRE")
3173 (set_attr "type" "itof" )])
3176 ; truncdfsf2 instruction pattern(s).
3179 (define_expand "truncdfsf2"
3180 [(set (match_operand:SF 0 "register_operand" "")
3181 (float_truncate:SF (match_operand:DF 1 "register_operand" "")))]
3185 (define_insn "truncdfsf2_ieee"
3186 [(set (match_operand:SF 0 "register_operand" "=f")
3187 (float_truncate:SF (match_operand:DF 1 "register_operand" "f")))]
3188 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3190 [(set_attr "op_type" "RRE")])
3192 (define_insn "truncdfsf2_ibm"
3193 [(set (match_operand:SF 0 "register_operand" "=f,f")
3194 (float_truncate:SF (match_operand:DF 1 "nonimmediate_operand" "f,R")))]
3195 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
3199 [(set_attr "op_type" "RR,RX")
3200 (set_attr "type" "floads,floads")])
3203 ; extendsfdf2 instruction pattern(s).
3206 (define_expand "extendsfdf2"
3207 [(set (match_operand:DF 0 "register_operand" "")
3208 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "")))]
3211 if (TARGET_IBM_FLOAT)
3213 emit_insn (gen_extendsfdf2_ibm (operands[0], operands[1]));
3218 (define_insn "extendsfdf2_ieee"
3219 [(set (match_operand:DF 0 "register_operand" "=f,f")
3220 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "f,R")))]
3221 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3225 [(set_attr "op_type" "RRE,RXE")
3226 (set_attr "type" "floads,floads")])
3228 (define_insn "extendsfdf2_ibm"
3229 [(set (match_operand:DF 0 "register_operand" "=f,f")
3230 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "f,R")))
3231 (clobber (reg:CC 33))]
3232 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
3234 sdr\t%0,%0\;ler\t%0,%1
3235 sdr\t%0,%0\;le\t%0,%1"
3236 [(set_attr "length" "4,6")
3237 (set_attr "type" "floads,floads")])
3241 ;; ARITHMETIC OPERATIONS
3243 ; arithmetic operations set the ConditionCode,
3244 ; because of unpredictable Bits in Register for Halfword and Byte
3245 ; the ConditionCode can be set wrong in operations for Halfword and Byte
3248 ;;- Add instructions.
3252 ; addti3 instruction pattern(s).
3255 (define_insn_and_split "addti3"
3256 [(set (match_operand:TI 0 "register_operand" "=&d")
3257 (plus:TI (match_operand:TI 1 "nonimmediate_operand" "%0")
3258 (match_operand:TI 2 "general_operand" "do") ) )
3259 (clobber (reg:CC 33))]
3262 "&& reload_completed"
3265 (compare:CCL1 (plus:DI (match_dup 7) (match_dup 8))
3267 (set (match_dup 6) (plus:DI (match_dup 7) (match_dup 8)))])
3269 [(set (match_dup 3) (plus:DI (plus:DI (match_dup 4) (match_dup 5))
3270 (ltu:DI (reg:CCL1 33) (const_int 0))))
3271 (clobber (reg:CC 33))])]
3272 "operands[3] = operand_subword (operands[0], 0, 0, TImode);
3273 operands[4] = operand_subword (operands[1], 0, 0, TImode);
3274 operands[5] = operand_subword (operands[2], 0, 0, TImode);
3275 operands[6] = operand_subword (operands[0], 1, 0, TImode);
3276 operands[7] = operand_subword (operands[1], 1, 0, TImode);
3277 operands[8] = operand_subword (operands[2], 1, 0, TImode);")
3280 ; adddi3 instruction pattern(s).
3283 (define_insn "*adddi3_sign"
3284 [(set (match_operand:DI 0 "register_operand" "=d,d")
3285 (plus:DI (sign_extend:DI (match_operand:SI 2 "general_operand" "d,m"))
3286 (match_operand:DI 1 "register_operand" "0,0")))
3287 (clobber (reg:CC 33))]
3292 [(set_attr "op_type" "RRE,RXY")])
3294 (define_insn "*adddi3_zero_cc"
3296 (compare (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m"))
3297 (match_operand:DI 1 "register_operand" "0,0"))
3299 (set (match_operand:DI 0 "register_operand" "=d,d")
3300 (plus:DI (zero_extend:DI (match_dup 2)) (match_dup 1)))]
3301 "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
3305 [(set_attr "op_type" "RRE,RXY")])
3307 (define_insn "*adddi3_zero_cconly"
3309 (compare (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m"))
3310 (match_operand:DI 1 "register_operand" "0,0"))
3312 (clobber (match_scratch:DI 0 "=d,d"))]
3313 "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
3317 [(set_attr "op_type" "RRE,RXY")])
3319 (define_insn "*adddi3_zero"
3320 [(set (match_operand:DI 0 "register_operand" "=d,d")
3321 (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m"))
3322 (match_operand:DI 1 "register_operand" "0,0")))
3323 (clobber (reg:CC 33))]
3328 [(set_attr "op_type" "RRE,RXY")])
3330 (define_insn "*adddi3_imm_cc"
3332 (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "0")
3333 (match_operand:DI 2 "const_int_operand" "K"))
3335 (set (match_operand:DI 0 "register_operand" "=d")
3336 (plus:DI (match_dup 1) (match_dup 2)))]
3338 && s390_match_ccmode (insn, CCAmode)
3339 && CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'K', \"K\")"
3341 [(set_attr "op_type" "RI")])
3343 (define_insn "*adddi3_carry1_cc"
3345 (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
3346 (match_operand:DI 2 "general_operand" "d,m"))
3348 (set (match_operand:DI 0 "register_operand" "=d,d")
3349 (plus:DI (match_dup 1) (match_dup 2)))]
3350 "s390_match_ccmode (insn, CCL1mode) && TARGET_64BIT"
3354 [(set_attr "op_type" "RRE,RXY")])
3356 (define_insn "*adddi3_carry1_cconly"
3358 (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
3359 (match_operand:DI 2 "general_operand" "d,m"))
3361 (clobber (match_scratch:DI 0 "=d,d"))]
3362 "s390_match_ccmode (insn, CCL1mode) && TARGET_64BIT"
3366 [(set_attr "op_type" "RRE,RXY")])
3368 (define_insn "*adddi3_carry2_cc"
3370 (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
3371 (match_operand:DI 2 "general_operand" "d,m"))
3373 (set (match_operand:DI 0 "register_operand" "=d,d")
3374 (plus:DI (match_dup 1) (match_dup 2)))]
3375 "s390_match_ccmode (insn, CCL1mode) && TARGET_64BIT"
3379 [(set_attr "op_type" "RRE,RXY")])
3381 (define_insn "*adddi3_carry2_cconly"
3383 (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
3384 (match_operand:DI 2 "general_operand" "d,m"))
3386 (clobber (match_scratch:DI 0 "=d,d"))]
3387 "s390_match_ccmode (insn, CCL1mode) && TARGET_64BIT"
3391 [(set_attr "op_type" "RRE,RXY")])
3393 (define_insn "*adddi3_cc"
3395 (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
3396 (match_operand:DI 2 "general_operand" "d,m"))
3398 (set (match_operand:DI 0 "register_operand" "=d,d")
3399 (plus:DI (match_dup 1) (match_dup 2)))]
3400 "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
3404 [(set_attr "op_type" "RRE,RXY")])
3406 (define_insn "*adddi3_cconly"
3408 (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
3409 (match_operand:DI 2 "general_operand" "d,m"))
3411 (clobber (match_scratch:DI 0 "=d,d"))]
3412 "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
3416 [(set_attr "op_type" "RRE,RXY")])
3418 (define_insn "*adddi3_cconly2"
3420 (compare (match_operand:DI 1 "nonimmediate_operand" "%0,0")
3421 (neg:SI (match_operand:DI 2 "general_operand" "d,m"))))
3422 (clobber (match_scratch:DI 0 "=d,d"))]
3423 "s390_match_ccmode(insn, CCLmode) && TARGET_64BIT"
3427 [(set_attr "op_type" "RRE,RXY")])
3429 (define_insn "*adddi3_64"
3430 [(set (match_operand:DI 0 "register_operand" "=d,d,d")
3431 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0")
3432 (match_operand:DI 2 "general_operand" "d,K,m") ) )
3433 (clobber (reg:CC 33))]
3439 [(set_attr "op_type" "RRE,RI,RXY")])
3441 (define_insn_and_split "*adddi3_31z"
3442 [(set (match_operand:DI 0 "register_operand" "=&d")
3443 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0")
3444 (match_operand:DI 2 "general_operand" "do") ) )
3445 (clobber (reg:CC 33))]
3446 "!TARGET_64BIT && TARGET_CPU_ZARCH"
3448 "&& reload_completed"
3451 (compare:CCL1 (plus:SI (match_dup 7) (match_dup 8))
3453 (set (match_dup 6) (plus:SI (match_dup 7) (match_dup 8)))])
3455 [(set (match_dup 3) (plus:SI (plus:SI (match_dup 4) (match_dup 5))
3456 (ltu:SI (reg:CCL1 33) (const_int 0))))
3457 (clobber (reg:CC 33))])]
3458 "operands[3] = operand_subword (operands[0], 0, 0, DImode);
3459 operands[4] = operand_subword (operands[1], 0, 0, DImode);
3460 operands[5] = operand_subword (operands[2], 0, 0, DImode);
3461 operands[6] = operand_subword (operands[0], 1, 0, DImode);
3462 operands[7] = operand_subword (operands[1], 1, 0, DImode);
3463 operands[8] = operand_subword (operands[2], 1, 0, DImode);")
3465 (define_insn_and_split "*adddi3_31"
3466 [(set (match_operand:DI 0 "register_operand" "=&d")
3467 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0")
3468 (match_operand:DI 2 "general_operand" "do") ) )
3469 (clobber (reg:CC 33))]
3472 "&& reload_completed"
3474 [(set (match_dup 3) (plus:SI (match_dup 4) (match_dup 5)))
3475 (clobber (reg:CC 33))])
3478 (compare:CCL1 (plus:SI (match_dup 7) (match_dup 8))
3480 (set (match_dup 6) (plus:SI (match_dup 7) (match_dup 8)))])
3482 (if_then_else (ltu (reg:CCL1 33) (const_int 0))
3484 (label_ref (match_dup 9))))
3486 [(set (match_dup 3) (plus:SI (match_dup 3) (const_int 1)))
3487 (clobber (reg:CC 33))])
3489 "operands[3] = operand_subword (operands[0], 0, 0, DImode);
3490 operands[4] = operand_subword (operands[1], 0, 0, DImode);
3491 operands[5] = operand_subword (operands[2], 0, 0, DImode);
3492 operands[6] = operand_subword (operands[0], 1, 0, DImode);
3493 operands[7] = operand_subword (operands[1], 1, 0, DImode);
3494 operands[8] = operand_subword (operands[2], 1, 0, DImode);
3495 operands[9] = gen_label_rtx ();")
3497 (define_expand "adddi3"
3499 [(set (match_operand:DI 0 "register_operand" "")
3500 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "")
3501 (match_operand:DI 2 "general_operand" "")))
3502 (clobber (reg:CC 33))])]
3507 ; addsi3 instruction pattern(s).
3510 (define_insn "*addsi3_imm_cc"
3512 (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "0")
3513 (match_operand:SI 2 "const_int_operand" "K"))
3515 (set (match_operand:SI 0 "register_operand" "=d")
3516 (plus:SI (match_dup 1) (match_dup 2)))]
3517 "s390_match_ccmode (insn, CCAmode)
3518 && CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'K', \"K\")"
3520 [(set_attr "op_type" "RI")])
3522 (define_insn "*addsi3_carry1_cc"
3524 (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
3525 (match_operand:SI 2 "general_operand" "d,R,T"))
3527 (set (match_operand:SI 0 "register_operand" "=d,d,d")
3528 (plus:SI (match_dup 1) (match_dup 2)))]
3529 "s390_match_ccmode (insn, CCL1mode)"
3534 [(set_attr "op_type" "RR,RX,RXY")])
3536 (define_insn "*addsi3_carry1_cconly"
3538 (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
3539 (match_operand:SI 2 "general_operand" "d,R,T"))
3541 (clobber (match_scratch:SI 0 "=d,d,d"))]
3542 "s390_match_ccmode (insn, CCL1mode)"
3547 [(set_attr "op_type" "RR,RX,RXY")])
3549 (define_insn "*addsi3_carry2_cc"
3551 (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
3552 (match_operand:SI 2 "general_operand" "d,R,T"))
3554 (set (match_operand:SI 0 "register_operand" "=d,d,d")
3555 (plus:SI (match_dup 1) (match_dup 2)))]
3556 "s390_match_ccmode (insn, CCL1mode)"
3561 [(set_attr "op_type" "RR,RX,RXY")])
3563 (define_insn "*addsi3_carry2_cconly"
3565 (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
3566 (match_operand:SI 2 "general_operand" "d,R,T"))
3568 (clobber (match_scratch:SI 0 "=d,d,d"))]
3569 "s390_match_ccmode (insn, CCL1mode)"
3574 [(set_attr "op_type" "RR,RX,RXY")])
3576 (define_insn "*addsi3_cc"
3578 (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
3579 (match_operand:SI 2 "general_operand" "d,R,T"))
3581 (set (match_operand:SI 0 "register_operand" "=d,d,d")
3582 (plus:SI (match_dup 1) (match_dup 2)))]
3583 "s390_match_ccmode (insn, CCLmode)"
3588 [(set_attr "op_type" "RR,RX,RXY")])
3590 (define_insn "*addsi3_cconly"
3592 (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
3593 (match_operand:SI 2 "general_operand" "d,R,T"))
3595 (clobber (match_scratch:SI 0 "=d,d,d"))]
3596 "s390_match_ccmode (insn, CCLmode)"
3601 [(set_attr "op_type" "RR,RX,RXY")])
3603 (define_insn "*addsi3_cconly2"
3605 (compare (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
3606 (neg:SI (match_operand:SI 2 "general_operand" "d,R,T"))))
3607 (clobber (match_scratch:SI 0 "=d,d,d"))]
3608 "s390_match_ccmode (insn, CCLmode)"
3613 [(set_attr "op_type" "RR,RX,RXY")])
3615 (define_insn "*addsi3_sign"
3616 [(set (match_operand:SI 0 "register_operand" "=d,d")
3617 (plus:SI (sign_extend:SI (match_operand:HI 2 "memory_operand" "R,T"))
3618 (match_operand:SI 1 "register_operand" "0,0")))
3619 (clobber (reg:CC 33))]
3624 [(set_attr "op_type" "RX,RXY")])
3626 (define_insn "addsi3"
3627 [(set (match_operand:SI 0 "register_operand" "=d,d,d,d")
3628 (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
3629 (match_operand:SI 2 "general_operand" "d,K,R,T")))
3630 (clobber (reg:CC 33))]
3637 [(set_attr "op_type" "RR,RI,RX,RXY")])
3640 ; adddf3 instruction pattern(s).
3643 (define_expand "adddf3"
3645 [(set (match_operand:DF 0 "register_operand" "=f,f")
3646 (plus:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0")
3647 (match_operand:DF 2 "general_operand" "f,R")))
3648 (clobber (reg:CC 33))])]
3652 (define_insn "*adddf3"
3653 [(set (match_operand:DF 0 "register_operand" "=f,f")
3654 (plus:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0")
3655 (match_operand:DF 2 "general_operand" "f,R")))
3656 (clobber (reg:CC 33))]
3657 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3661 [(set_attr "op_type" "RRE,RXE")
3662 (set_attr "type" "fsimpd,fsimpd")])
3664 (define_insn "*adddf3_cc"
3666 (compare (plus:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0")
3667 (match_operand:DF 2 "general_operand" "f,R"))
3668 (match_operand:DF 3 "const0_operand" "")))
3669 (set (match_operand:DF 0 "register_operand" "=f,f")
3670 (plus:DF (match_dup 1) (match_dup 2)))]
3671 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3675 [(set_attr "op_type" "RRE,RXE")
3676 (set_attr "type" "fsimpd,fsimpd")])
3678 (define_insn "*adddf3_cconly"
3680 (compare (plus:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0")
3681 (match_operand:DF 2 "general_operand" "f,R"))
3682 (match_operand:DF 3 "const0_operand" "")))
3683 (clobber (match_scratch:DF 0 "=f,f"))]
3684 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3688 [(set_attr "op_type" "RRE,RXE")
3689 (set_attr "type" "fsimpd,fsimpd")])
3691 (define_insn "*adddf3_ibm"
3692 [(set (match_operand:DF 0 "register_operand" "=f,f")
3693 (plus:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0")
3694 (match_operand:DF 2 "general_operand" "f,R")))
3695 (clobber (reg:CC 33))]
3696 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
3700 [(set_attr "op_type" "RR,RX")
3701 (set_attr "type" "fsimpd,fsimpd")])
3704 ; addsf3 instruction pattern(s).
3707 (define_expand "addsf3"
3709 [(set (match_operand:SF 0 "register_operand" "=f,f")
3710 (plus:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0")
3711 (match_operand:SF 2 "general_operand" "f,R")))
3712 (clobber (reg:CC 33))])]
3716 (define_insn "*addsf3"
3717 [(set (match_operand:SF 0 "register_operand" "=f,f")
3718 (plus:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0")
3719 (match_operand:SF 2 "general_operand" "f,R")))
3720 (clobber (reg:CC 33))]
3721 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3725 [(set_attr "op_type" "RRE,RXE")
3726 (set_attr "type" "fsimps,fsimps")])
3728 (define_insn "*addsf3_cc"
3730 (compare (plus:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0")
3731 (match_operand:SF 2 "general_operand" "f,R"))
3732 (match_operand:SF 3 "const0_operand" "")))
3733 (set (match_operand:SF 0 "register_operand" "=f,f")
3734 (plus:SF (match_dup 1) (match_dup 2)))]
3735 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3739 [(set_attr "op_type" "RRE,RXE")
3740 (set_attr "type" "fsimps,fsimps")])
3742 (define_insn "*addsf3_cconly"
3744 (compare (plus:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0")
3745 (match_operand:SF 2 "general_operand" "f,R"))
3746 (match_operand:SF 3 "const0_operand" "")))
3747 (clobber (match_scratch:SF 0 "=f,f"))]
3748 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3752 [(set_attr "op_type" "RRE,RXE")
3753 (set_attr "type" "fsimps,fsimps")])
3755 (define_insn "*addsf3"
3756 [(set (match_operand:SF 0 "register_operand" "=f,f")
3757 (plus:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0")
3758 (match_operand:SF 2 "general_operand" "f,R")))
3759 (clobber (reg:CC 33))]
3760 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
3764 [(set_attr "op_type" "RR,RX")
3765 (set_attr "type" "fsimps,fsimps")])
3769 ;;- Subtract instructions.
3773 ; subti3 instruction pattern(s).
3776 (define_insn_and_split "subti3"
3777 [(set (match_operand:TI 0 "register_operand" "=&d")
3778 (minus:TI (match_operand:TI 1 "register_operand" "0")
3779 (match_operand:TI 2 "general_operand" "do") ) )
3780 (clobber (reg:CC 33))]
3783 "&& reload_completed"
3786 (compare:CCL2 (minus:DI (match_dup 7) (match_dup 8))
3788 (set (match_dup 6) (minus:DI (match_dup 7) (match_dup 8)))])
3790 [(set (match_dup 3) (minus:DI (minus:DI (match_dup 4) (match_dup 5))
3791 (gtu:DI (reg:CCL2 33) (const_int 0))))
3792 (clobber (reg:CC 33))])]
3793 "operands[3] = operand_subword (operands[0], 0, 0, TImode);
3794 operands[4] = operand_subword (operands[1], 0, 0, TImode);
3795 operands[5] = operand_subword (operands[2], 0, 0, TImode);
3796 operands[6] = operand_subword (operands[0], 1, 0, TImode);
3797 operands[7] = operand_subword (operands[1], 1, 0, TImode);
3798 operands[8] = operand_subword (operands[2], 1, 0, TImode);")
3801 ; subdi3 instruction pattern(s).
3804 (define_insn "*subdi3_sign"
3805 [(set (match_operand:DI 0 "register_operand" "=d,d")
3806 (minus:DI (match_operand:DI 1 "register_operand" "0,0")
3807 (sign_extend:DI (match_operand:SI 2 "general_operand" "d,m"))))
3808 (clobber (reg:CC 33))]
3813 [(set_attr "op_type" "RRE,RXY")])
3815 (define_insn "*subdi3_zero_cc"
3817 (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0")
3818 (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m")))
3820 (set (match_operand:DI 0 "register_operand" "=d,d")
3821 (minus:DI (match_dup 1) (zero_extend:DI (match_dup 2))))]
3822 "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
3826 [(set_attr "op_type" "RRE,RXY")])
3828 (define_insn "*subdi3_zero_cconly"
3830 (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0")
3831 (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m")))
3833 (clobber (match_scratch:DI 0 "=d,d"))]
3834 "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
3838 [(set_attr "op_type" "RRE,RXY")])
3840 (define_insn "*subdi3_zero"
3841 [(set (match_operand:DI 0 "register_operand" "=d,d")
3842 (minus:DI (match_operand:DI 1 "register_operand" "0,0")
3843 (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m"))))
3844 (clobber (reg:CC 33))]
3849 [(set_attr "op_type" "RRE,RXY")])
3851 (define_insn "*subdi3_borrow_cc"
3853 (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0")
3854 (match_operand:DI 2 "general_operand" "d,m"))
3856 (set (match_operand:DI 0 "register_operand" "=d,d")
3857 (minus:DI (match_dup 1) (match_dup 2)))]
3858 "s390_match_ccmode (insn, CCL2mode) && TARGET_64BIT"
3862 [(set_attr "op_type" "RRE,RXY")])
3864 (define_insn "*subdi3_borrow_cconly"
3866 (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0")
3867 (match_operand:DI 2 "general_operand" "d,m"))
3869 (clobber (match_scratch:DI 0 "=d,d"))]
3870 "s390_match_ccmode (insn, CCL2mode) && TARGET_64BIT"
3874 [(set_attr "op_type" "RRE,RXY")])
3876 (define_insn "*subdi3_cc"
3878 (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0")
3879 (match_operand:DI 2 "general_operand" "d,m"))
3881 (set (match_operand:DI 0 "register_operand" "=d,d")
3882 (minus:DI (match_dup 1) (match_dup 2)))]
3883 "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
3887 [(set_attr "op_type" "RRE,RXY")])
3889 (define_insn "*subdi3_cc2"
3891 (compare (match_operand:DI 1 "register_operand" "0,0")
3892 (match_operand:DI 2 "general_operand" "d,m")))
3893 (set (match_operand:DI 0 "register_operand" "=d,d")
3894 (minus:DI (match_dup 1) (match_dup 2)))]
3895 "s390_match_ccmode (insn, CCL3mode) && TARGET_64BIT"
3899 [(set_attr "op_type" "RRE,RXY")])
3901 (define_insn "*subdi3_cconly"
3903 (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0")
3904 (match_operand:DI 2 "general_operand" "d,m"))
3906 (clobber (match_scratch:DI 0 "=d,d"))]
3907 "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
3911 [(set_attr "op_type" "RRE,RXY")])
3913 (define_insn "*subdi3_cconly2"
3915 (compare (match_operand:DI 1 "register_operand" "0,0")
3916 (match_operand:DI 2 "general_operand" "d,m")))
3917 (clobber (match_scratch:DI 0 "=d,d"))]
3918 "s390_match_ccmode (insn, CCL3mode) && TARGET_64BIT"
3922 [(set_attr "op_type" "RRE,RXY")])
3924 (define_insn "*subdi3_64"
3925 [(set (match_operand:DI 0 "register_operand" "=d,d")
3926 (minus:DI (match_operand:DI 1 "register_operand" "0,0")
3927 (match_operand:DI 2 "general_operand" "d,m") ) )
3928 (clobber (reg:CC 33))]
3933 [(set_attr "op_type" "RRE,RRE")])
3935 (define_insn_and_split "*subdi3_31z"
3936 [(set (match_operand:DI 0 "register_operand" "=&d")
3937 (minus:DI (match_operand:DI 1 "register_operand" "0")
3938 (match_operand:DI 2 "general_operand" "do") ) )
3939 (clobber (reg:CC 33))]
3940 "!TARGET_64BIT && TARGET_CPU_ZARCH"
3942 "&& reload_completed"
3945 (compare:CCL2 (minus:SI (match_dup 7) (match_dup 8))
3947 (set (match_dup 6) (minus:SI (match_dup 7) (match_dup 8)))])
3949 [(set (match_dup 3) (minus:SI (minus:SI (match_dup 4) (match_dup 5))
3950 (gtu:SI (reg:CCL2 33) (const_int 0))))
3951 (clobber (reg:CC 33))])]
3952 "operands[3] = operand_subword (operands[0], 0, 0, DImode);
3953 operands[4] = operand_subword (operands[1], 0, 0, DImode);
3954 operands[5] = operand_subword (operands[2], 0, 0, DImode);
3955 operands[6] = operand_subword (operands[0], 1, 0, DImode);
3956 operands[7] = operand_subword (operands[1], 1, 0, DImode);
3957 operands[8] = operand_subword (operands[2], 1, 0, DImode);")
3959 (define_insn_and_split "*subdi3_31"
3960 [(set (match_operand:DI 0 "register_operand" "=&d")
3961 (minus:DI (match_operand:DI 1 "register_operand" "0")
3962 (match_operand:DI 2 "general_operand" "do") ) )
3963 (clobber (reg:CC 33))]
3966 "&& reload_completed"
3968 [(set (match_dup 3) (minus:SI (match_dup 4) (match_dup 5)))
3969 (clobber (reg:CC 33))])
3972 (compare:CCL2 (minus:SI (match_dup 7) (match_dup 8))
3974 (set (match_dup 6) (minus:SI (match_dup 7) (match_dup 8)))])
3976 (if_then_else (gtu (reg:CCL2 33) (const_int 0))
3978 (label_ref (match_dup 9))))
3980 [(set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))
3981 (clobber (reg:CC 33))])
3983 "operands[3] = operand_subword (operands[0], 0, 0, DImode);
3984 operands[4] = operand_subword (operands[1], 0, 0, DImode);
3985 operands[5] = operand_subword (operands[2], 0, 0, DImode);
3986 operands[6] = operand_subword (operands[0], 1, 0, DImode);
3987 operands[7] = operand_subword (operands[1], 1, 0, DImode);
3988 operands[8] = operand_subword (operands[2], 1, 0, DImode);
3989 operands[9] = gen_label_rtx ();")
3991 (define_expand "subdi3"
3993 [(set (match_operand:DI 0 "register_operand" "")
3994 (minus:DI (match_operand:DI 1 "register_operand" "")
3995 (match_operand:DI 2 "general_operand" "")))
3996 (clobber (reg:CC 33))])]
4001 ; subsi3 instruction pattern(s).
4004 (define_insn "*subsi3_borrow_cc"
4006 (compare (minus:SI (match_operand:SI 1 "register_operand" "0,0,0")
4007 (match_operand:SI 2 "general_operand" "d,R,T"))
4009 (set (match_operand:SI 0 "register_operand" "=d,d,d")
4010 (minus:SI (match_dup 1) (match_dup 2)))]
4011 "s390_match_ccmode (insn, CCL2mode)"
4016 [(set_attr "op_type" "RR,RX,RXY")])
4018 (define_insn "*subsi3_borrow_cconly"
4020 (compare (minus:SI (match_operand:SI 1 "register_operand" "0,0,0")
4021 (match_operand:SI 2 "general_operand" "d,R,T"))
4023 (clobber (match_scratch:SI 0 "=d,d,d"))]
4024 "s390_match_ccmode (insn, CCL2mode)"
4029 [(set_attr "op_type" "RR,RX,RXY")])
4031 (define_insn "*subsi3_cc"
4033 (compare (minus:SI (match_operand:SI 1 "register_operand" "0,0,0")
4034 (match_operand:SI 2 "general_operand" "d,R,T"))
4036 (set (match_operand:SI 0 "register_operand" "=d,d,d")
4037 (minus:SI (match_dup 1) (match_dup 2)))]
4038 "s390_match_ccmode (insn, CCLmode)"
4043 [(set_attr "op_type" "RR,RX,RXY")])
4045 (define_insn "*subsi3_cc2"
4047 (compare (match_operand:SI 1 "register_operand" "0,0,0")
4048 (match_operand:SI 2 "general_operand" "d,R,T")))
4049 (set (match_operand:SI 0 "register_operand" "=d,d,d")
4050 (minus:SI (match_dup 1) (match_dup 2)))]
4051 "s390_match_ccmode (insn, CCL3mode)"
4056 [(set_attr "op_type" "RR,RX,RXY")])
4058 (define_insn "*subsi3_cconly"
4060 (compare (minus:SI (match_operand:SI 1 "register_operand" "0,0,0")
4061 (match_operand:SI 2 "general_operand" "d,R,T"))
4063 (clobber (match_scratch:SI 0 "=d,d,d"))]
4064 "s390_match_ccmode (insn, CCLmode)"
4069 [(set_attr "op_type" "RR,RX,RXY")])
4071 (define_insn "*subsi3_cconly2"
4073 (compare (match_operand:SI 1 "register_operand" "0,0,0")
4074 (match_operand:SI 2 "general_operand" "d,R,T")))
4075 (clobber (match_scratch:SI 0 "=d,d,d"))]
4076 "s390_match_ccmode (insn, CCL3mode)"
4081 [(set_attr "op_type" "RR,RX,RXY")])
4083 (define_insn "*subsi3_sign"
4084 [(set (match_operand:SI 0 "register_operand" "=d,d")
4085 (minus:SI (match_operand:SI 1 "register_operand" "0,0")
4086 (sign_extend:SI (match_operand:HI 2 "memory_operand" "R,T"))))
4087 (clobber (reg:CC 33))]
4092 [(set_attr "op_type" "RX,RXY")])
4094 (define_insn "subsi3"
4095 [(set (match_operand:SI 0 "register_operand" "=d,d,d")
4096 (minus:SI (match_operand:SI 1 "register_operand" "0,0,0")
4097 (match_operand:SI 2 "general_operand" "d,R,T")))
4098 (clobber (reg:CC 33))]
4104 [(set_attr "op_type" "RR,RX,RXY")])
4108 ; subdf3 instruction pattern(s).
4111 (define_expand "subdf3"
4113 [(set (match_operand:DF 0 "register_operand" "=f,f")
4114 (minus:DF (match_operand:DF 1 "register_operand" "0,0")
4115 (match_operand:DF 2 "general_operand" "f,R")))
4116 (clobber (reg:CC 33))])]
4120 (define_insn "*subdf3"
4121 [(set (match_operand:DF 0 "register_operand" "=f,f")
4122 (minus:DF (match_operand:DF 1 "register_operand" "0,0")
4123 (match_operand:DF 2 "general_operand" "f,R")))
4124 (clobber (reg:CC 33))]
4125 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
4129 [(set_attr "op_type" "RRE,RXE")
4130 (set_attr "type" "fsimpd,fsimpd")])
4132 (define_insn "*subdf3_cc"
4134 (compare (minus:DF (match_operand:DF 1 "nonimmediate_operand" "0,0")
4135 (match_operand:DF 2 "general_operand" "f,R"))
4136 (match_operand:DF 3 "const0_operand" "")))
4137 (set (match_operand:DF 0 "register_operand" "=f,f")
4138 (minus:DF (match_dup 1) (match_dup 2)))]
4139 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
4143 [(set_attr "op_type" "RRE,RXE")
4144 (set_attr "type" "fsimpd,fsimpd")])
4146 (define_insn "*subdf3_cconly"
4148 (compare (minus:DF (match_operand:DF 1 "nonimmediate_operand" "0,0")
4149 (match_operand:DF 2 "general_operand" "f,R"))
4150 (match_operand:DF 3 "const0_operand" "")))
4151 (clobber (match_scratch:DF 0 "=f,f"))]
4152 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
4156 [(set_attr "op_type" "RRE,RXE")
4157 (set_attr "type" "fsimpd,fsimpd")])
4159 (define_insn "*subdf3_ibm"
4160 [(set (match_operand:DF 0 "register_operand" "=f,f")
4161 (minus:DF (match_operand:DF 1 "register_operand" "0,0")
4162 (match_operand:DF 2 "general_operand" "f,R")))
4163 (clobber (reg:CC 33))]
4164 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
4168 [(set_attr "op_type" "RR,RX")
4169 (set_attr "type" "fsimpd,fsimpd")])
4172 ; subsf3 instruction pattern(s).
4175 (define_expand "subsf3"
4177 [(set (match_operand:SF 0 "register_operand" "=f,f")
4178 (minus:SF (match_operand:SF 1 "register_operand" "0,0")
4179 (match_operand:SF 2 "general_operand" "f,R")))
4180 (clobber (reg:CC 33))])]
4184 (define_insn "*subsf3"
4185 [(set (match_operand:SF 0 "register_operand" "=f,f")
4186 (minus:SF (match_operand:SF 1 "register_operand" "0,0")
4187 (match_operand:SF 2 "general_operand" "f,R")))
4188 (clobber (reg:CC 33))]
4189 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
4193 [(set_attr "op_type" "RRE,RXE")
4194 (set_attr "type" "fsimps,fsimps")])
4196 (define_insn "*subsf3_cc"
4198 (compare (minus:SF (match_operand:SF 1 "nonimmediate_operand" "0,0")
4199 (match_operand:SF 2 "general_operand" "f,R"))
4200 (match_operand:SF 3 "const0_operand" "")))
4201 (set (match_operand:SF 0 "register_operand" "=f,f")
4202 (minus:SF (match_dup 1) (match_dup 2)))]
4203 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
4207 [(set_attr "op_type" "RRE,RXE")
4208 (set_attr "type" "fsimps,fsimps")])
4210 (define_insn "*subsf3_cconly"
4212 (compare (minus:SF (match_operand:SF 1 "nonimmediate_operand" "0,0")
4213 (match_operand:SF 2 "general_operand" "f,R"))
4214 (match_operand:SF 3 "const0_operand" "")))
4215 (clobber (match_scratch:SF 0 "=f,f"))]
4216 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
4220 [(set_attr "op_type" "RRE,RXE")
4221 (set_attr "type" "fsimps,fsimps")])
4223 (define_insn "*subsf3_ibm"
4224 [(set (match_operand:SF 0 "register_operand" "=f,f")
4225 (minus:SF (match_operand:SF 1 "register_operand" "0,0")
4226 (match_operand:SF 2 "general_operand" "f,R")))
4227 (clobber (reg:CC 33))]
4228 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
4232 [(set_attr "op_type" "RR,RX")
4233 (set_attr "type" "fsimps,fsimps")])
4237 ;;- Conditional add/subtract instructions.
4241 ; adddicc instruction pattern(s).
4244 (define_insn "*adddi3_alc_cc"
4247 (plus:DI (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
4248 (match_operand:DI 2 "general_operand" "d,m"))
4249 (match_operand:DI 3 "s390_alc_comparison" ""))
4251 (set (match_operand:DI 0 "register_operand" "=d,d")
4252 (plus:DI (plus:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4253 "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
4257 [(set_attr "op_type" "RRE,RXY")])
4259 (define_insn "*adddi3_alc"
4260 [(set (match_operand:DI 0 "register_operand" "=d,d")
4261 (plus:DI (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
4262 (match_operand:DI 2 "general_operand" "d,m"))
4263 (match_operand:DI 3 "s390_alc_comparison" "")))
4264 (clobber (reg:CC 33))]
4269 [(set_attr "op_type" "RRE,RXY")])
4271 (define_insn "*subdi3_slb_cc"
4274 (minus:DI (minus:DI (match_operand:DI 1 "nonimmediate_operand" "0,0")
4275 (match_operand:DI 2 "general_operand" "d,m"))
4276 (match_operand:DI 3 "s390_slb_comparison" ""))
4278 (set (match_operand:DI 0 "register_operand" "=d,d")
4279 (minus:DI (minus:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4280 "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
4284 [(set_attr "op_type" "RRE,RXY")])
4286 (define_insn "*subdi3_slb"
4287 [(set (match_operand:DI 0 "register_operand" "=d,d")
4288 (minus:DI (minus:DI (match_operand:DI 1 "nonimmediate_operand" "0,0")
4289 (match_operand:DI 2 "general_operand" "d,m"))
4290 (match_operand:DI 3 "s390_slb_comparison" "")))
4291 (clobber (reg:CC 33))]
4296 [(set_attr "op_type" "RRE,RXY")])
4298 (define_expand "adddicc"
4299 [(match_operand:DI 0 "register_operand" "")
4300 (match_operand 1 "comparison_operator" "")
4301 (match_operand:DI 2 "register_operand" "")
4302 (match_operand:DI 3 "const_int_operand" "")]
4304 "if (!s390_expand_addcc (GET_CODE (operands[1]),
4305 s390_compare_op0, s390_compare_op1,
4306 operands[0], operands[2],
4307 operands[3])) FAIL; DONE;")
4310 ; addsicc instruction pattern(s).
4313 (define_insn "*addsi3_alc_cc"
4316 (plus:SI (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
4317 (match_operand:SI 2 "general_operand" "d,m"))
4318 (match_operand:SI 3 "s390_alc_comparison" ""))
4320 (set (match_operand:SI 0 "register_operand" "=d,d")
4321 (plus:SI (plus:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4322 "s390_match_ccmode (insn, CCLmode) && TARGET_CPU_ZARCH"
4326 [(set_attr "op_type" "RRE,RXY")])
4328 (define_insn "*addsi3_alc"
4329 [(set (match_operand:SI 0 "register_operand" "=d,d")
4330 (plus:SI (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
4331 (match_operand:SI 2 "general_operand" "d,m"))
4332 (match_operand:SI 3 "s390_alc_comparison" "")))
4333 (clobber (reg:CC 33))]
4338 [(set_attr "op_type" "RRE,RXY")])
4340 (define_insn "*subsi3_slb_cc"
4343 (minus:SI (minus:SI (match_operand:SI 1 "nonimmediate_operand" "0,0")
4344 (match_operand:SI 2 "general_operand" "d,m"))
4345 (match_operand:SI 3 "s390_slb_comparison" ""))
4347 (set (match_operand:SI 0 "register_operand" "=d,d")
4348 (minus:SI (minus:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4349 "s390_match_ccmode (insn, CCLmode) && TARGET_CPU_ZARCH"
4353 [(set_attr "op_type" "RRE,RXY")])
4355 (define_insn "*subsi3_slb"
4356 [(set (match_operand:SI 0 "register_operand" "=d,d")
4357 (minus:SI (minus:SI (match_operand:SI 1 "nonimmediate_operand" "0,0")
4358 (match_operand:SI 2 "general_operand" "d,m"))
4359 (match_operand:SI 3 "s390_slb_comparison" "")))
4360 (clobber (reg:CC 33))]
4365 [(set_attr "op_type" "RRE,RXY")])
4367 (define_expand "addsicc"
4368 [(match_operand:SI 0 "register_operand" "")
4369 (match_operand 1 "comparison_operator" "")
4370 (match_operand:SI 2 "register_operand" "")
4371 (match_operand:SI 3 "const_int_operand" "")]
4373 "if (!s390_expand_addcc (GET_CODE (operands[1]),
4374 s390_compare_op0, s390_compare_op1,
4375 operands[0], operands[2],
4376 operands[3])) FAIL; DONE;")
4379 ; scond instruction pattern(s).
4382 (define_insn_and_split "*sconddi"
4383 [(set (match_operand:DI 0 "register_operand" "=&d")
4384 (match_operand:DI 1 "s390_alc_comparison" ""))
4385 (clobber (reg:CC 33))]
4388 "&& reload_completed"
4389 [(set (match_dup 0) (const_int 0))
4391 [(set (match_dup 0) (plus:DI (plus:DI (match_dup 0) (match_dup 0))
4393 (clobber (reg:CC 33))])]
4396 (define_insn_and_split "*scondsi"
4397 [(set (match_operand:SI 0 "register_operand" "=&d")
4398 (match_operand:SI 1 "s390_alc_comparison" ""))
4399 (clobber (reg:CC 33))]
4402 "&& reload_completed"
4403 [(set (match_dup 0) (const_int 0))
4405 [(set (match_dup 0) (plus:SI (plus:SI (match_dup 0) (match_dup 0))
4407 (clobber (reg:CC 33))])]
4410 (define_insn_and_split "*sconddi_neg"
4411 [(set (match_operand:DI 0 "register_operand" "=&d")
4412 (match_operand:DI 1 "s390_slb_comparison" ""))
4413 (clobber (reg:CC 33))]
4416 "&& reload_completed"
4417 [(set (match_dup 0) (const_int 0))
4419 [(set (match_dup 0) (minus:DI (minus:DI (match_dup 0) (match_dup 0))
4421 (clobber (reg:CC 33))])
4423 [(set (match_dup 0) (neg:DI (match_dup 0)))
4424 (clobber (reg:CC 33))])]
4427 (define_insn_and_split "*scondsi_neg"
4428 [(set (match_operand:SI 0 "register_operand" "=&d")
4429 (match_operand:SI 1 "s390_slb_comparison" ""))
4430 (clobber (reg:CC 33))]
4433 "&& reload_completed"
4434 [(set (match_dup 0) (const_int 0))
4436 [(set (match_dup 0) (minus:SI (minus:SI (match_dup 0) (match_dup 0))
4438 (clobber (reg:CC 33))])
4440 [(set (match_dup 0) (neg:SI (match_dup 0)))
4441 (clobber (reg:CC 33))])]
4444 (define_expand "sltu"
4445 [(match_operand:SI 0 "register_operand" "")]
4447 "if (!s390_expand_addcc (LTU, s390_compare_op0, s390_compare_op1,
4448 operands[0], const0_rtx, const1_rtx)) FAIL; DONE;")
4450 (define_expand "sgtu"
4451 [(match_operand:SI 0 "register_operand" "")]
4453 "if (!s390_expand_addcc (GTU, s390_compare_op0, s390_compare_op1,
4454 operands[0], const0_rtx, const1_rtx)) FAIL; DONE;")
4456 (define_expand "sleu"
4457 [(match_operand:SI 0 "register_operand" "")]
4459 "if (!s390_expand_addcc (LEU, s390_compare_op0, s390_compare_op1,
4460 operands[0], const0_rtx, const1_rtx)) FAIL; DONE;")
4462 (define_expand "sgeu"
4463 [(match_operand:SI 0 "register_operand" "")]
4465 "if (!s390_expand_addcc (GEU, s390_compare_op0, s390_compare_op1,
4466 operands[0], const0_rtx, const1_rtx)) FAIL; DONE;")
4470 ;;- Multiply instructions.
4474 ; muldi3 instruction pattern(s).
4477 (define_insn "*muldi3_sign"
4478 [(set (match_operand:DI 0 "register_operand" "=d,d")
4479 (mult:DI (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "d,m"))
4480 (match_operand:DI 1 "register_operand" "0,0")))]
4485 [(set_attr "op_type" "RRE,RXY")
4486 (set_attr "type" "imuldi")])
4488 (define_insn "muldi3"
4489 [(set (match_operand:DI 0 "register_operand" "=d,d,d")
4490 (mult:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0")
4491 (match_operand:DI 2 "general_operand" "d,K,m")))]
4497 [(set_attr "op_type" "RRE,RI,RXY")
4498 (set_attr "type" "imuldi")])
4501 ; mulsi3 instruction pattern(s).
4504 (define_insn "*mulsi3_sign"
4505 [(set (match_operand:SI 0 "register_operand" "=d")
4506 (mult:SI (sign_extend:SI (match_operand:HI 2 "memory_operand" "R"))
4507 (match_operand:SI 1 "register_operand" "0")))]
4510 [(set_attr "op_type" "RX")
4511 (set_attr "type" "imulhi")])
4513 (define_insn "mulsi3"
4514 [(set (match_operand:SI 0 "register_operand" "=d,d,d,d")
4515 (mult:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
4516 (match_operand:SI 2 "general_operand" "d,K,R,T")))]
4523 [(set_attr "op_type" "RRE,RI,RX,RXY")
4524 (set_attr "type" "imulsi,imulhi,imulsi,imulsi")])
4527 ; mulsidi3 instruction pattern(s).
4530 (define_insn "mulsidi3"
4531 [(set (match_operand:DI 0 "register_operand" "=d,d")
4532 (mult:DI (sign_extend:DI
4533 (match_operand:SI 1 "register_operand" "%0,0"))
4535 (match_operand:SI 2 "nonimmediate_operand" "d,R"))))]
4540 [(set_attr "op_type" "RR,RX")
4541 (set_attr "type" "imulsi")])
4544 ; umulsidi3 instruction pattern(s).
4547 (define_insn "umulsidi3"
4548 [(set (match_operand:DI 0 "register_operand" "=d,d")
4549 (mult:DI (zero_extend:DI
4550 (match_operand:SI 1 "register_operand" "%0,0"))
4552 (match_operand:SI 2 "nonimmediate_operand" "d,m"))))]
4553 "!TARGET_64BIT && TARGET_CPU_ZARCH"
4557 [(set_attr "op_type" "RRE,RXY")
4558 (set_attr "type" "imulsi")])
4561 ; muldf3 instruction pattern(s).
4564 (define_expand "muldf3"
4565 [(set (match_operand:DF 0 "register_operand" "=f,f")
4566 (mult:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0")
4567 (match_operand:DF 2 "general_operand" "f,R")))]
4571 (define_insn "*muldf3"
4572 [(set (match_operand:DF 0 "register_operand" "=f,f")
4573 (mult:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0")
4574 (match_operand:DF 2 "general_operand" "f,R")))]
4575 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
4579 [(set_attr "op_type" "RRE,RXE")
4580 (set_attr "type" "fmuld")])
4582 (define_insn "*muldf3_ibm"
4583 [(set (match_operand:DF 0 "register_operand" "=f,f")
4584 (mult:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0")
4585 (match_operand:DF 2 "general_operand" "f,R")))]
4586 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
4590 [(set_attr "op_type" "RR,RX")
4591 (set_attr "type" "fmuld")])
4593 (define_insn "*fmadddf"
4594 [(set (match_operand:DF 0 "register_operand" "=f,f")
4595 (plus:DF (mult:DF (match_operand:DF 1 "register_operand" "%f,f")
4596 (match_operand:DF 2 "nonimmediate_operand" "f,R"))
4597 (match_operand:DF 3 "register_operand" "0,0")))]
4598 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT && TARGET_FUSED_MADD"
4602 [(set_attr "op_type" "RRE,RXE")
4603 (set_attr "type" "fmuld")])
4605 (define_insn "*fmsubdf"
4606 [(set (match_operand:DF 0 "register_operand" "=f,f")
4607 (minus:DF (mult:DF (match_operand:DF 1 "register_operand" "f,f")
4608 (match_operand:DF 2 "nonimmediate_operand" "f,R"))
4609 (match_operand:DF 3 "register_operand" "0,0")))]
4610 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT && TARGET_FUSED_MADD"
4614 [(set_attr "op_type" "RRE,RXE")
4615 (set_attr "type" "fmuld")])
4618 ; mulsf3 instruction pattern(s).
4621 (define_expand "mulsf3"
4622 [(set (match_operand:SF 0 "register_operand" "=f,f")
4623 (mult:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0")
4624 (match_operand:SF 2 "general_operand" "f,R")))]
4628 (define_insn "*mulsf3"
4629 [(set (match_operand:SF 0 "register_operand" "=f,f")
4630 (mult:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0")
4631 (match_operand:SF 2 "general_operand" "f,R")))]
4632 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
4636 [(set_attr "op_type" "RRE,RXE")
4637 (set_attr "type" "fmuls")])
4639 (define_insn "*mulsf3_ibm"
4640 [(set (match_operand:SF 0 "register_operand" "=f,f")
4641 (mult:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0")
4642 (match_operand:SF 2 "general_operand" "f,R")))]
4643 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
4647 [(set_attr "op_type" "RR,RX")
4648 (set_attr "type" "fmuls")])
4650 (define_insn "*fmaddsf"
4651 [(set (match_operand:SF 0 "register_operand" "=f,f")
4652 (plus:SF (mult:SF (match_operand:SF 1 "register_operand" "%f,f")
4653 (match_operand:SF 2 "nonimmediate_operand" "f,R"))
4654 (match_operand:SF 3 "register_operand" "0,0")))]
4655 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT && TARGET_FUSED_MADD"
4659 [(set_attr "op_type" "RRE,RXE")
4660 (set_attr "type" "fmuls")])
4662 (define_insn "*fmsubsf"
4663 [(set (match_operand:SF 0 "register_operand" "=f,f")
4664 (minus:SF (mult:SF (match_operand:SF 1 "register_operand" "f,f")
4665 (match_operand:SF 2 "nonimmediate_operand" "f,R"))
4666 (match_operand:SF 3 "register_operand" "0,0")))]
4667 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT && TARGET_FUSED_MADD"
4671 [(set_attr "op_type" "RRE,RXE")
4672 (set_attr "type" "fmuls")])
4675 ;;- Divide and modulo instructions.
4679 ; divmoddi4 instruction pattern(s).
4682 (define_expand "divmoddi4"
4683 [(parallel [(set (match_operand:DI 0 "general_operand" "")
4684 (div:DI (match_operand:DI 1 "register_operand" "")
4685 (match_operand:DI 2 "general_operand" "")))
4686 (set (match_operand:DI 3 "general_operand" "")
4687 (mod:DI (match_dup 1) (match_dup 2)))])
4688 (clobber (match_dup 4))]
4691 rtx insn, div_equal, mod_equal;
4693 div_equal = gen_rtx_DIV (DImode, operands[1], operands[2]);
4694 mod_equal = gen_rtx_MOD (DImode, operands[1], operands[2]);
4696 operands[4] = gen_reg_rtx(TImode);
4697 emit_insn (gen_divmodtidi3 (operands[4], operands[1], operands[2]));
4699 insn = emit_move_insn (operands[0], gen_lowpart (DImode, operands[4]));
4701 gen_rtx_EXPR_LIST (REG_EQUAL, div_equal, REG_NOTES (insn));
4703 insn = emit_move_insn (operands[3], gen_highpart (DImode, operands[4]));
4705 gen_rtx_EXPR_LIST (REG_EQUAL, mod_equal, REG_NOTES (insn));
4710 (define_insn "divmodtidi3"
4711 [(set (match_operand:TI 0 "register_operand" "=d,d")
4715 (mod:DI (match_operand:DI 1 "register_operand" "0,0")
4716 (match_operand:DI 2 "general_operand" "d,m")))
4718 (zero_extend:TI (div:DI (match_dup 1) (match_dup 2)))))]
4723 [(set_attr "op_type" "RRE,RXY")
4724 (set_attr "type" "idiv")])
4726 (define_insn "divmodtisi3"
4727 [(set (match_operand:TI 0 "register_operand" "=d,d")
4731 (mod:DI (match_operand:DI 1 "register_operand" "0,0")
4733 (match_operand:SI 2 "nonimmediate_operand" "d,m"))))
4736 (div:DI (match_dup 1) (sign_extend:DI (match_dup 2))))))]
4741 [(set_attr "op_type" "RRE,RXY")
4742 (set_attr "type" "idiv")])
4745 ; udivmoddi4 instruction pattern(s).
4748 (define_expand "udivmoddi4"
4749 [(parallel [(set (match_operand:DI 0 "general_operand" "")
4750 (udiv:DI (match_operand:DI 1 "general_operand" "")
4751 (match_operand:DI 2 "nonimmediate_operand" "")))
4752 (set (match_operand:DI 3 "general_operand" "")
4753 (umod:DI (match_dup 1) (match_dup 2)))])
4754 (clobber (match_dup 4))]
4757 rtx insn, div_equal, mod_equal, equal;
4759 div_equal = gen_rtx_UDIV (DImode, operands[1], operands[2]);
4760 mod_equal = gen_rtx_UMOD (DImode, operands[1], operands[2]);
4761 equal = gen_rtx_IOR (TImode,
4762 gen_rtx_ASHIFT (TImode,
4763 gen_rtx_ZERO_EXTEND (TImode, mod_equal),
4765 gen_rtx_ZERO_EXTEND (TImode, div_equal));
4767 operands[4] = gen_reg_rtx(TImode);
4768 emit_insn (gen_rtx_CLOBBER (VOIDmode, operands[4]));
4769 emit_move_insn (gen_lowpart (DImode, operands[4]), operands[1]);
4770 emit_move_insn (gen_highpart (DImode, operands[4]), const0_rtx);
4771 insn = emit_insn (gen_udivmodtidi3 (operands[4], operands[4], operands[2]));
4773 gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
4775 insn = emit_move_insn (operands[0], gen_lowpart (DImode, operands[4]));
4777 gen_rtx_EXPR_LIST (REG_EQUAL, div_equal, REG_NOTES (insn));
4779 insn = emit_move_insn (operands[3], gen_highpart (DImode, operands[4]));
4781 gen_rtx_EXPR_LIST (REG_EQUAL, mod_equal, REG_NOTES (insn));
4786 (define_insn "udivmodtidi3"
4787 [(set (match_operand:TI 0 "register_operand" "=d,d")
4792 (umod:TI (match_operand:TI 1 "register_operand" "0,0")
4794 (match_operand:DI 2 "nonimmediate_operand" "d,m")))))
4798 (udiv:TI (match_dup 1) (zero_extend:TI (match_dup 2)))))))]
4803 [(set_attr "op_type" "RRE,RXY")
4804 (set_attr "type" "idiv")])
4807 ; divmodsi4 instruction pattern(s).
4810 (define_expand "divmodsi4"
4811 [(parallel [(set (match_operand:SI 0 "general_operand" "")
4812 (div:SI (match_operand:SI 1 "general_operand" "")
4813 (match_operand:SI 2 "nonimmediate_operand" "")))
4814 (set (match_operand:SI 3 "general_operand" "")
4815 (mod:SI (match_dup 1) (match_dup 2)))])
4816 (clobber (match_dup 4))]
4819 rtx insn, div_equal, mod_equal, equal;
4821 div_equal = gen_rtx_DIV (SImode, operands[1], operands[2]);
4822 mod_equal = gen_rtx_MOD (SImode, operands[1], operands[2]);
4823 equal = gen_rtx_IOR (DImode,
4824 gen_rtx_ASHIFT (DImode,
4825 gen_rtx_ZERO_EXTEND (DImode, mod_equal),
4827 gen_rtx_ZERO_EXTEND (DImode, div_equal));
4829 operands[4] = gen_reg_rtx(DImode);
4830 emit_insn (gen_extendsidi2 (operands[4], operands[1]));
4831 insn = emit_insn (gen_divmoddisi3 (operands[4], operands[4], operands[2]));
4833 gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
4835 insn = emit_move_insn (operands[0], gen_lowpart (SImode, operands[4]));
4837 gen_rtx_EXPR_LIST (REG_EQUAL, div_equal, REG_NOTES (insn));
4839 insn = emit_move_insn (operands[3], gen_highpart (SImode, operands[4]));
4841 gen_rtx_EXPR_LIST (REG_EQUAL, mod_equal, REG_NOTES (insn));
4846 (define_insn "divmoddisi3"
4847 [(set (match_operand:DI 0 "register_operand" "=d,d")
4852 (mod:DI (match_operand:DI 1 "register_operand" "0,0")
4854 (match_operand:SI 2 "nonimmediate_operand" "d,R")))))
4858 (div:DI (match_dup 1) (sign_extend:DI (match_dup 2)))))))]
4863 [(set_attr "op_type" "RR,RX")
4864 (set_attr "type" "idiv")])
4867 ; udivsi3 and umodsi3 instruction pattern(s).
4870 (define_expand "udivmodsi4"
4871 [(parallel [(set (match_operand:SI 0 "general_operand" "")
4872 (udiv:SI (match_operand:SI 1 "general_operand" "")
4873 (match_operand:SI 2 "nonimmediate_operand" "")))
4874 (set (match_operand:SI 3 "general_operand" "")
4875 (umod:SI (match_dup 1) (match_dup 2)))])
4876 (clobber (match_dup 4))]
4877 "!TARGET_64BIT && TARGET_CPU_ZARCH"
4879 rtx insn, div_equal, mod_equal, equal;
4881 div_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]);
4882 mod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]);
4883 equal = gen_rtx_IOR (DImode,
4884 gen_rtx_ASHIFT (DImode,
4885 gen_rtx_ZERO_EXTEND (DImode, mod_equal),
4887 gen_rtx_ZERO_EXTEND (DImode, div_equal));
4889 operands[4] = gen_reg_rtx(DImode);
4890 emit_insn (gen_rtx_CLOBBER (VOIDmode, operands[4]));
4891 emit_move_insn (gen_lowpart (SImode, operands[4]), operands[1]);
4892 emit_move_insn (gen_highpart (SImode, operands[4]), const0_rtx);
4893 insn = emit_insn (gen_udivmoddisi3 (operands[4], operands[4], operands[2]));
4895 gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
4897 insn = emit_move_insn (operands[0], gen_lowpart (SImode, operands[4]));
4899 gen_rtx_EXPR_LIST (REG_EQUAL, div_equal, REG_NOTES (insn));
4901 insn = emit_move_insn (operands[3], gen_highpart (SImode, operands[4]));
4903 gen_rtx_EXPR_LIST (REG_EQUAL, mod_equal, REG_NOTES (insn));
4908 (define_insn "udivmoddisi3"
4909 [(set (match_operand:DI 0 "register_operand" "=d,d")
4914 (umod:DI (match_operand:DI 1 "register_operand" "0,0")
4916 (match_operand:SI 2 "nonimmediate_operand" "d,m")))))
4920 (udiv:DI (match_dup 1) (zero_extend:DI (match_dup 2)))))))]
4921 "!TARGET_64BIT && TARGET_CPU_ZARCH"
4925 [(set_attr "op_type" "RRE,RXY")
4926 (set_attr "type" "idiv")])
4928 (define_expand "udivsi3"
4929 [(set (match_operand:SI 0 "register_operand" "=d")
4930 (udiv:SI (match_operand:SI 1 "general_operand" "")
4931 (match_operand:SI 2 "general_operand" "")))
4932 (clobber (match_dup 3))]
4933 "!TARGET_64BIT && !TARGET_CPU_ZARCH"
4935 rtx insn, udiv_equal, umod_equal, equal;
4937 udiv_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]);
4938 umod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]);
4939 equal = gen_rtx_IOR (DImode,
4940 gen_rtx_ASHIFT (DImode,
4941 gen_rtx_ZERO_EXTEND (DImode, umod_equal),
4943 gen_rtx_ZERO_EXTEND (DImode, udiv_equal));
4945 operands[3] = gen_reg_rtx (DImode);
4947 if (CONSTANT_P (operands[2]))
4949 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0)
4951 rtx label1 = gen_label_rtx ();
4953 operands[1] = make_safe_from (operands[1], operands[0]);
4954 emit_move_insn (operands[0], const0_rtx);
4955 emit_insn (gen_cmpsi (operands[1], operands[2]));
4956 emit_jump_insn (gen_bltu (label1));
4957 emit_move_insn (operands[0], const1_rtx);
4958 emit_label (label1);
4962 operands[2] = force_reg (SImode, operands[2]);
4963 operands[2] = make_safe_from (operands[2], operands[0]);
4965 emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
4966 insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
4969 gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
4971 insn = emit_move_insn (operands[0],
4972 gen_lowpart (SImode, operands[3]));
4974 gen_rtx_EXPR_LIST (REG_EQUAL,
4975 udiv_equal, REG_NOTES (insn));
4980 rtx label1 = gen_label_rtx ();
4981 rtx label2 = gen_label_rtx ();
4982 rtx label3 = gen_label_rtx ();
4984 operands[1] = force_reg (SImode, operands[1]);
4985 operands[1] = make_safe_from (operands[1], operands[0]);
4986 operands[2] = force_reg (SImode, operands[2]);
4987 operands[2] = make_safe_from (operands[2], operands[0]);
4989 emit_move_insn (operands[0], const0_rtx);
4990 emit_insn (gen_cmpsi (operands[2], operands[1]));
4991 emit_jump_insn (gen_bgtu (label3));
4992 emit_insn (gen_cmpsi (operands[2], const0_rtx));
4993 emit_jump_insn (gen_blt (label2));
4994 emit_insn (gen_cmpsi (operands[2], const1_rtx));
4995 emit_jump_insn (gen_beq (label1));
4996 emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
4997 insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
5000 gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
5002 insn = emit_move_insn (operands[0],
5003 gen_lowpart (SImode, operands[3]));
5005 gen_rtx_EXPR_LIST (REG_EQUAL,
5006 udiv_equal, REG_NOTES (insn));
5008 emit_label (label1);
5009 emit_move_insn (operands[0], operands[1]);
5011 emit_label (label2);
5012 emit_move_insn (operands[0], const1_rtx);
5013 emit_label (label3);
5015 emit_move_insn (operands[0], operands[0]);
5019 (define_expand "umodsi3"
5020 [(set (match_operand:SI 0 "register_operand" "=d")
5021 (umod:SI (match_operand:SI 1 "nonimmediate_operand" "")
5022 (match_operand:SI 2 "nonimmediate_operand" "")))
5023 (clobber (match_dup 3))]
5024 "!TARGET_64BIT && !TARGET_CPU_ZARCH"
5026 rtx insn, udiv_equal, umod_equal, equal;
5028 udiv_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]);
5029 umod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]);
5030 equal = gen_rtx_IOR (DImode,
5031 gen_rtx_ASHIFT (DImode,
5032 gen_rtx_ZERO_EXTEND (DImode, umod_equal),
5034 gen_rtx_ZERO_EXTEND (DImode, udiv_equal));
5036 operands[3] = gen_reg_rtx (DImode);
5038 if (CONSTANT_P (operands[2]))
5040 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) <= 0)
5042 rtx label1 = gen_label_rtx ();
5044 operands[1] = make_safe_from (operands[1], operands[0]);
5045 emit_move_insn (operands[0], operands[1]);
5046 emit_insn (gen_cmpsi (operands[0], operands[2]));
5047 emit_jump_insn (gen_bltu (label1));
5048 emit_insn (gen_abssi2 (operands[0], operands[2]));
5049 emit_insn (gen_addsi3 (operands[0], operands[0], operands[1]));
5050 emit_label (label1);
5054 operands[2] = force_reg (SImode, operands[2]);
5055 operands[2] = make_safe_from (operands[2], operands[0]);
5057 emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
5058 insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
5061 gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
5063 insn = emit_move_insn (operands[0],
5064 gen_highpart (SImode, operands[3]));
5066 gen_rtx_EXPR_LIST (REG_EQUAL,
5067 umod_equal, REG_NOTES (insn));
5072 rtx label1 = gen_label_rtx ();
5073 rtx label2 = gen_label_rtx ();
5074 rtx label3 = gen_label_rtx ();
5076 operands[1] = force_reg (SImode, operands[1]);
5077 operands[1] = make_safe_from (operands[1], operands[0]);
5078 operands[2] = force_reg (SImode, operands[2]);
5079 operands[2] = make_safe_from (operands[2], operands[0]);
5081 emit_move_insn(operands[0], operands[1]);
5082 emit_insn (gen_cmpsi (operands[2], operands[1]));
5083 emit_jump_insn (gen_bgtu (label3));
5084 emit_insn (gen_cmpsi (operands[2], const0_rtx));
5085 emit_jump_insn (gen_blt (label2));
5086 emit_insn (gen_cmpsi (operands[2], const1_rtx));
5087 emit_jump_insn (gen_beq (label1));
5088 emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
5089 insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
5092 gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
5094 insn = emit_move_insn (operands[0],
5095 gen_highpart (SImode, operands[3]));
5097 gen_rtx_EXPR_LIST (REG_EQUAL,
5098 umod_equal, REG_NOTES (insn));
5100 emit_label (label1);
5101 emit_move_insn (operands[0], const0_rtx);
5103 emit_label (label2);
5104 emit_insn (gen_subsi3 (operands[0], operands[0], operands[2]));
5105 emit_label (label3);
5111 ; divdf3 instruction pattern(s).
5114 (define_expand "divdf3"
5115 [(set (match_operand:DF 0 "register_operand" "=f,f")
5116 (div:DF (match_operand:DF 1 "register_operand" "0,0")
5117 (match_operand:DF 2 "general_operand" "f,R")))]
5121 (define_insn "*divdf3"
5122 [(set (match_operand:DF 0 "register_operand" "=f,f")
5123 (div:DF (match_operand:DF 1 "register_operand" "0,0")
5124 (match_operand:DF 2 "general_operand" "f,R")))]
5125 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
5129 [(set_attr "op_type" "RRE,RXE")
5130 (set_attr "type" "fdivd")])
5132 (define_insn "*divdf3_ibm"
5133 [(set (match_operand:DF 0 "register_operand" "=f,f")
5134 (div:DF (match_operand:DF 1 "register_operand" "0,0")
5135 (match_operand:DF 2 "general_operand" "f,R")))]
5136 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
5140 [(set_attr "op_type" "RR,RX")
5141 (set_attr "type" "fdivd")])
5144 ; divsf3 instruction pattern(s).
5147 (define_expand "divsf3"
5148 [(set (match_operand:SF 0 "register_operand" "=f,f")
5149 (div:SF (match_operand:SF 1 "register_operand" "0,0")
5150 (match_operand:SF 2 "general_operand" "f,R")))]
5154 (define_insn "*divsf3"
5155 [(set (match_operand:SF 0 "register_operand" "=f,f")
5156 (div:SF (match_operand:SF 1 "register_operand" "0,0")
5157 (match_operand:SF 2 "general_operand" "f,R")))]
5158 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
5162 [(set_attr "op_type" "RRE,RXE")
5163 (set_attr "type" "fdivs")])
5165 (define_insn "*divsf3"
5166 [(set (match_operand:SF 0 "register_operand" "=f,f")
5167 (div:SF (match_operand:SF 1 "register_operand" "0,0")
5168 (match_operand:SF 2 "general_operand" "f,R")))]
5169 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
5173 [(set_attr "op_type" "RR,RX")
5174 (set_attr "type" "fdivs")])
5178 ;;- And instructions.
5182 ; anddi3 instruction pattern(s).
5185 (define_insn "*anddi3_cc"
5187 (compare (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
5188 (match_operand:DI 2 "general_operand" "d,m"))
5190 (set (match_operand:DI 0 "register_operand" "=d,d")
5191 (and:DI (match_dup 1) (match_dup 2)))]
5192 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT"
5196 [(set_attr "op_type" "RRE,RXY")])
5198 (define_insn "*anddi3_cconly"
5200 (compare (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
5201 (match_operand:DI 2 "general_operand" "d,m"))
5203 (clobber (match_scratch:DI 0 "=d,d"))]
5204 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT
5205 /* Do not steal TM patterns. */
5206 && s390_single_part (operands[2], DImode, HImode, 0) < 0"
5210 [(set_attr "op_type" "RRE,RXY")])
5212 (define_insn "*anddi3"
5213 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,d,d,d,d,d,AQ,Q")
5214 (and:DI (match_operand:DI 1 "nonimmediate_operand"
5215 "%d,o,0,0,0,0,0,0,0,0")
5216 (match_operand:DI 2 "general_operand"
5217 "M,M,N0HDF,N1HDF,N2HDF,N3HDF,d,m,NxQDF,Q")))
5218 (clobber (reg:CC 33))]
5219 "TARGET_64BIT && s390_logical_operator_ok_p (operands)"
5231 [(set_attr "op_type" "RRE,RXE,RI,RI,RI,RI,RRE,RXY,SI,SS")])
5234 [(set (match_operand:DI 0 "s_operand" "")
5235 (and:DI (match_dup 0) (match_operand:DI 1 "immediate_operand" "")))
5236 (clobber (reg:CC 33))]
5239 [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1)))
5240 (clobber (reg:CC 33))])]
5241 "s390_narrow_logical_operator (AND, &operands[0], &operands[1]);")
5243 (define_expand "anddi3"
5244 [(set (match_operand:DI 0 "nonimmediate_operand" "")
5245 (and:DI (match_operand:DI 1 "nonimmediate_operand" "")
5246 (match_operand:DI 2 "general_operand" "")))
5247 (clobber (reg:CC 33))]
5249 "s390_expand_logical_operator (AND, DImode, operands); DONE;")
5252 ; andsi3 instruction pattern(s).
5255 (define_insn "*andsi3_cc"
5257 (compare (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
5258 (match_operand:SI 2 "general_operand" "d,R,T"))
5260 (set (match_operand:SI 0 "register_operand" "=d,d,d")
5261 (and:SI (match_dup 1) (match_dup 2)))]
5262 "s390_match_ccmode(insn, CCTmode)"
5267 [(set_attr "op_type" "RR,RX,RXY")])
5269 (define_insn "*andsi3_cconly"
5271 (compare (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
5272 (match_operand:SI 2 "general_operand" "d,R,T"))
5274 (clobber (match_scratch:SI 0 "=d,d,d"))]
5275 "s390_match_ccmode(insn, CCTmode)
5276 /* Do not steal TM patterns. */
5277 && s390_single_part (operands[2], SImode, HImode, 0) < 0"
5282 [(set_attr "op_type" "RR,RX,RXY")])
5284 (define_insn "*andsi3_zarch"
5285 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,d,d,d,d,AQ,Q")
5286 (and:SI (match_operand:SI 1 "nonimmediate_operand"
5287 "%d,o,0,0,0,0,0,0,0")
5288 (match_operand:SI 2 "general_operand"
5289 "M,M,N0HSF,N1HSF,d,R,T,NxQSF,Q")))
5290 (clobber (reg:CC 33))]
5291 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
5302 [(set_attr "op_type" "RRE,RXE,RI,RI,RR,RX,RXY,SI,SS")])
5304 (define_insn "*andsi3_esa"
5305 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,AQ,Q")
5306 (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
5307 (match_operand:SI 2 "general_operand" "d,R,NxQSF,Q")))
5308 (clobber (reg:CC 33))]
5309 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
5315 [(set_attr "op_type" "RR,RX,SI,SS")])
5318 [(set (match_operand:SI 0 "s_operand" "")
5319 (and:SI (match_dup 0) (match_operand:SI 1 "immediate_operand" "")))
5320 (clobber (reg:CC 33))]
5323 [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1)))
5324 (clobber (reg:CC 33))])]
5325 "s390_narrow_logical_operator (AND, &operands[0], &operands[1]);")
5327 (define_expand "andsi3"
5328 [(set (match_operand:SI 0 "nonimmediate_operand" "")
5329 (and:SI (match_operand:SI 1 "nonimmediate_operand" "")
5330 (match_operand:SI 2 "general_operand" "")))
5331 (clobber (reg:CC 33))]
5333 "s390_expand_logical_operator (AND, SImode, operands); DONE;")
5336 ; andhi3 instruction pattern(s).
5339 (define_insn "*andhi3_zarch"
5340 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,AQ,Q")
5341 (and:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0,0")
5342 (match_operand:HI 2 "general_operand" "d,n,NxQHF,Q")))
5343 (clobber (reg:CC 33))]
5344 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
5350 [(set_attr "op_type" "RR,RI,SI,SS")])
5352 (define_insn "*andhi3_esa"
5353 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,AQ,Q")
5354 (and:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0")
5355 (match_operand:HI 2 "general_operand" "d,NxQHF,Q")))
5356 (clobber (reg:CC 33))]
5357 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
5362 [(set_attr "op_type" "RR,SI,SS")])
5365 [(set (match_operand:HI 0 "s_operand" "")
5366 (and:HI (match_dup 0) (match_operand:HI 1 "immediate_operand" "")))
5367 (clobber (reg:CC 33))]
5370 [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1)))
5371 (clobber (reg:CC 33))])]
5372 "s390_narrow_logical_operator (AND, &operands[0], &operands[1]);")
5374 (define_expand "andhi3"
5375 [(set (match_operand:HI 0 "nonimmediate_operand" "")
5376 (and:HI (match_operand:HI 1 "nonimmediate_operand" "")
5377 (match_operand:HI 2 "general_operand" "")))
5378 (clobber (reg:CC 33))]
5380 "s390_expand_logical_operator (AND, HImode, operands); DONE;")
5383 ; andqi3 instruction pattern(s).
5386 (define_insn "*andqi3_zarch"
5387 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,Q,S,Q")
5388 (and:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0,0,0")
5389 (match_operand:QI 2 "general_operand" "d,n,n,n,Q")))
5390 (clobber (reg:CC 33))]
5391 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
5398 [(set_attr "op_type" "RR,RI,SI,SIY,SS")])
5400 (define_insn "*andqi3_esa"
5401 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,Q,Q")
5402 (and:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
5403 (match_operand:QI 2 "general_operand" "d,n,Q")))
5404 (clobber (reg:CC 33))]
5405 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
5410 [(set_attr "op_type" "RR,SI,SS")])
5412 (define_expand "andqi3"
5413 [(set (match_operand:QI 0 "nonimmediate_operand" "")
5414 (and:QI (match_operand:QI 1 "nonimmediate_operand" "")
5415 (match_operand:QI 2 "general_operand" "")))
5416 (clobber (reg:CC 33))]
5418 "s390_expand_logical_operator (AND, QImode, operands); DONE;")
5421 ; Block and (NC) patterns.
5425 [(set (match_operand:BLK 0 "memory_operand" "=Q")
5426 (and:BLK (match_dup 0)
5427 (match_operand:BLK 1 "memory_operand" "Q")))
5428 (use (match_operand 2 "const_int_operand" "n"))
5429 (clobber (reg:CC 33))]
5430 "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
5431 "nc\t%O0(%2,%R0),%S1"
5432 [(set_attr "op_type" "SS")])
5435 [(set (match_operand 0 "memory_operand" "")
5437 (match_operand 1 "memory_operand" "")))
5438 (clobber (reg:CC 33))]
5440 && GET_MODE (operands[0]) == GET_MODE (operands[1])
5441 && GET_MODE_SIZE (GET_MODE (operands[0])) > 0"
5443 [(set (match_dup 0) (and:BLK (match_dup 0) (match_dup 1)))
5445 (clobber (reg:CC 33))])]
5447 operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0])));
5448 operands[0] = adjust_address (operands[0], BLKmode, 0);
5449 operands[1] = adjust_address (operands[1], BLKmode, 0);
5454 [(set (match_operand:BLK 0 "memory_operand" "")
5455 (and:BLK (match_dup 0)
5456 (match_operand:BLK 1 "memory_operand" "")))
5457 (use (match_operand 2 "const_int_operand" ""))
5458 (clobber (reg:CC 33))])
5460 [(set (match_operand:BLK 3 "memory_operand" "")
5461 (and:BLK (match_dup 3)
5462 (match_operand:BLK 4 "memory_operand" "")))
5463 (use (match_operand 5 "const_int_operand" ""))
5464 (clobber (reg:CC 33))])]
5465 "s390_offset_p (operands[0], operands[3], operands[2])
5466 && s390_offset_p (operands[1], operands[4], operands[2])
5467 && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256"
5469 [(set (match_dup 6) (and:BLK (match_dup 6) (match_dup 7)))
5471 (clobber (reg:CC 33))])]
5472 "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
5473 operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0));
5474 operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));")
5478 ;;- Bit set (inclusive or) instructions.
5482 ; iordi3 instruction pattern(s).
5485 (define_insn "*iordi3_cc"
5487 (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
5488 (match_operand:DI 2 "general_operand" "d,m"))
5490 (set (match_operand:DI 0 "register_operand" "=d,d")
5491 (ior:DI (match_dup 1) (match_dup 2)))]
5492 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT"
5496 [(set_attr "op_type" "RRE,RXY")])
5498 (define_insn "*iordi3_cconly"
5500 (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
5501 (match_operand:DI 2 "general_operand" "d,m"))
5503 (clobber (match_scratch:DI 0 "=d,d"))]
5504 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT"
5508 [(set_attr "op_type" "RRE,RXY")])
5510 (define_insn "*iordi3"
5511 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,d,d,d,AQ,Q")
5512 (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,0,0,0,0,0")
5513 (match_operand:DI 2 "general_operand"
5514 "N0HD0,N1HD0,N2HD0,N3HD0,d,m,NxQD0,Q")))
5515 (clobber (reg:CC 33))]
5516 "TARGET_64BIT && s390_logical_operator_ok_p (operands)"
5526 [(set_attr "op_type" "RI,RI,RI,RI,RRE,RXY,SI,SS")])
5529 [(set (match_operand:DI 0 "s_operand" "")
5530 (ior:DI (match_dup 0) (match_operand:DI 1 "immediate_operand" "")))
5531 (clobber (reg:CC 33))]
5534 [(set (match_dup 0) (ior:QI (match_dup 0) (match_dup 1)))
5535 (clobber (reg:CC 33))])]
5536 "s390_narrow_logical_operator (IOR, &operands[0], &operands[1]);")
5538 (define_expand "iordi3"
5539 [(set (match_operand:DI 0 "nonimmediate_operand" "")
5540 (ior:DI (match_operand:DI 1 "nonimmediate_operand" "")
5541 (match_operand:DI 2 "general_operand" "")))
5542 (clobber (reg:CC 33))]
5544 "s390_expand_logical_operator (IOR, DImode, operands); DONE;")
5547 ; iorsi3 instruction pattern(s).
5550 (define_insn "*iorsi3_cc"
5552 (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
5553 (match_operand:SI 2 "general_operand" "d,R,T"))
5555 (set (match_operand:SI 0 "register_operand" "=d,d,d")
5556 (ior:SI (match_dup 1) (match_dup 2)))]
5557 "s390_match_ccmode(insn, CCTmode)"
5562 [(set_attr "op_type" "RR,RX,RXY")])
5564 (define_insn "*iorsi3_cconly"
5566 (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
5567 (match_operand:SI 2 "general_operand" "d,R,T"))
5569 (clobber (match_scratch:SI 0 "=d,d,d"))]
5570 "s390_match_ccmode(insn, CCTmode)"
5575 [(set_attr "op_type" "RR,RX,RXY")])
5577 (define_insn "*iorsi3_zarch"
5578 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,d,d,AQ,Q")
5579 (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0,0,0,0")
5580 (match_operand:SI 2 "general_operand" "N0HS0,N1HS0,d,R,T,NxQS0,Q")))
5581 (clobber (reg:CC 33))]
5582 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
5591 [(set_attr "op_type" "RI,RI,RR,RX,RXY,SI,SS")])
5593 (define_insn "*iorsi3_esa"
5594 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,AQ,Q")
5595 (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
5596 (match_operand:SI 2 "general_operand" "d,R,NxQS0,Q")))
5597 (clobber (reg:CC 33))]
5598 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
5604 [(set_attr "op_type" "RR,RX,SI,SS")])
5607 [(set (match_operand:SI 0 "s_operand" "")
5608 (ior:SI (match_dup 0) (match_operand:SI 1 "immediate_operand" "")))
5609 (clobber (reg:CC 33))]
5612 [(set (match_dup 0) (ior:QI (match_dup 0) (match_dup 1)))
5613 (clobber (reg:CC 33))])]
5614 "s390_narrow_logical_operator (IOR, &operands[0], &operands[1]);")
5616 (define_expand "iorsi3"
5617 [(set (match_operand:SI 0 "nonimmediate_operand" "")
5618 (ior:SI (match_operand:SI 1 "nonimmediate_operand" "")
5619 (match_operand:SI 2 "general_operand" "")))
5620 (clobber (reg:CC 33))]
5622 "s390_expand_logical_operator (IOR, SImode, operands); DONE;")
5625 ; iorhi3 instruction pattern(s).
5628 (define_insn "*iorhi3_zarch"
5629 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,AQ,Q")
5630 (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0,0")
5631 (match_operand:HI 2 "general_operand" "d,n,NxQH0,Q")))
5632 (clobber (reg:CC 33))]
5633 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
5639 [(set_attr "op_type" "RR,RI,SI,SS")])
5641 (define_insn "*iorhi3_esa"
5642 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,AQ,Q")
5643 (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0")
5644 (match_operand:HI 2 "general_operand" "d,NxQH0,Q")))
5645 (clobber (reg:CC 33))]
5646 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
5651 [(set_attr "op_type" "RR,SI,SS")])
5654 [(set (match_operand:HI 0 "s_operand" "")
5655 (ior:HI (match_dup 0) (match_operand:HI 1 "immediate_operand" "")))
5656 (clobber (reg:CC 33))]
5659 [(set (match_dup 0) (ior:QI (match_dup 0) (match_dup 1)))
5660 (clobber (reg:CC 33))])]
5661 "s390_narrow_logical_operator (IOR, &operands[0], &operands[1]);")
5663 (define_expand "iorhi3"
5664 [(set (match_operand:HI 0 "nonimmediate_operand" "")
5665 (ior:HI (match_operand:HI 1 "nonimmediate_operand" "")
5666 (match_operand:HI 2 "general_operand" "")))
5667 (clobber (reg:CC 33))]
5669 "s390_expand_logical_operator (IOR, HImode, operands); DONE;")
5672 ; iorqi3 instruction pattern(s).
5675 (define_insn "*iorqi3_zarch"
5676 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,Q,S,Q")
5677 (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0,0,0")
5678 (match_operand:QI 2 "general_operand" "d,n,n,n,Q")))
5679 (clobber (reg:CC 33))]
5680 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
5687 [(set_attr "op_type" "RR,RI,SI,SIY,SS")])
5689 (define_insn "*iorqi3_esa"
5690 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,Q,Q")
5691 (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
5692 (match_operand:QI 2 "general_operand" "d,n,Q")))
5693 (clobber (reg:CC 33))]
5694 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
5699 [(set_attr "op_type" "RR,SI,SS")])
5701 (define_expand "iorqi3"
5702 [(set (match_operand:QI 0 "nonimmediate_operand" "")
5703 (ior:QI (match_operand:QI 1 "nonimmediate_operand" "")
5704 (match_operand:QI 2 "general_operand" "")))
5705 (clobber (reg:CC 33))]
5707 "s390_expand_logical_operator (IOR, QImode, operands); DONE;")
5710 ; Block inclusive or (OC) patterns.
5714 [(set (match_operand:BLK 0 "memory_operand" "=Q")
5715 (ior:BLK (match_dup 0)
5716 (match_operand:BLK 1 "memory_operand" "Q")))
5717 (use (match_operand 2 "const_int_operand" "n"))
5718 (clobber (reg:CC 33))]
5719 "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
5720 "oc\t%O0(%2,%R0),%S1"
5721 [(set_attr "op_type" "SS")])
5724 [(set (match_operand 0 "memory_operand" "")
5726 (match_operand 1 "memory_operand" "")))
5727 (clobber (reg:CC 33))]
5729 && GET_MODE (operands[0]) == GET_MODE (operands[1])
5730 && GET_MODE_SIZE (GET_MODE (operands[0])) > 0"
5732 [(set (match_dup 0) (ior:BLK (match_dup 0) (match_dup 1)))
5734 (clobber (reg:CC 33))])]
5736 operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0])));
5737 operands[0] = adjust_address (operands[0], BLKmode, 0);
5738 operands[1] = adjust_address (operands[1], BLKmode, 0);
5743 [(set (match_operand:BLK 0 "memory_operand" "")
5744 (ior:BLK (match_dup 0)
5745 (match_operand:BLK 1 "memory_operand" "")))
5746 (use (match_operand 2 "const_int_operand" ""))
5747 (clobber (reg:CC 33))])
5749 [(set (match_operand:BLK 3 "memory_operand" "")
5750 (ior:BLK (match_dup 3)
5751 (match_operand:BLK 4 "memory_operand" "")))
5752 (use (match_operand 5 "const_int_operand" ""))
5753 (clobber (reg:CC 33))])]
5754 "s390_offset_p (operands[0], operands[3], operands[2])
5755 && s390_offset_p (operands[1], operands[4], operands[2])
5756 && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256"
5758 [(set (match_dup 6) (ior:BLK (match_dup 6) (match_dup 7)))
5760 (clobber (reg:CC 33))])]
5761 "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
5762 operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0));
5763 operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));")
5767 ;;- Xor instructions.
5771 ; xordi3 instruction pattern(s).
5774 (define_insn "*xordi3_cc"
5776 (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
5777 (match_operand:DI 2 "general_operand" "d,m"))
5779 (set (match_operand:DI 0 "register_operand" "=d,d")
5780 (xor:DI (match_dup 1) (match_dup 2)))]
5781 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT"
5785 [(set_attr "op_type" "RRE,RXY")])
5787 (define_insn "*xordi3_cconly"
5789 (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
5790 (match_operand:DI 2 "general_operand" "d,m"))
5792 (clobber (match_scratch:DI 0 "=d,d"))]
5793 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT"
5797 [(set_attr "op_type" "RRE,RXY")])
5799 (define_insn "*xordi3"
5800 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,AQ,Q")
5801 (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,0")
5802 (match_operand:DI 2 "general_operand" "d,m,NxQD0,Q")))
5803 (clobber (reg:CC 33))]
5804 "TARGET_64BIT && s390_logical_operator_ok_p (operands)"
5810 [(set_attr "op_type" "RRE,RXY,SI,SS")])
5813 [(set (match_operand:DI 0 "s_operand" "")
5814 (xor:DI (match_dup 0) (match_operand:DI 1 "immediate_operand" "")))
5815 (clobber (reg:CC 33))]
5818 [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1)))
5819 (clobber (reg:CC 33))])]
5820 "s390_narrow_logical_operator (XOR, &operands[0], &operands[1]);")
5822 (define_expand "xordi3"
5823 [(set (match_operand:DI 0 "nonimmediate_operand" "")
5824 (xor:DI (match_operand:DI 1 "nonimmediate_operand" "")
5825 (match_operand:DI 2 "general_operand" "")))
5826 (clobber (reg:CC 33))]
5828 "s390_expand_logical_operator (XOR, DImode, operands); DONE;")
5831 ; xorsi3 instruction pattern(s).
5834 (define_insn "*xorsi3_cc"
5836 (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
5837 (match_operand:SI 2 "general_operand" "d,R,T"))
5839 (set (match_operand:SI 0 "register_operand" "=d,d,d")
5840 (xor:SI (match_dup 1) (match_dup 2)))]
5841 "s390_match_ccmode(insn, CCTmode)"
5846 [(set_attr "op_type" "RR,RX,RXY")])
5848 (define_insn "*xorsi3_cconly"
5850 (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
5851 (match_operand:SI 2 "general_operand" "d,R,T"))
5853 (clobber (match_scratch:SI 0 "=d,d,d"))]
5854 "s390_match_ccmode(insn, CCTmode)"
5859 [(set_attr "op_type" "RR,RX,RXY")])
5861 (define_insn "*xorsi3"
5862 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,AQ,Q")
5863 (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0,0")
5864 (match_operand:SI 2 "general_operand" "d,R,T,NxQS0,Q")))
5865 (clobber (reg:CC 33))]
5866 "s390_logical_operator_ok_p (operands)"
5873 [(set_attr "op_type" "RR,RX,RXY,SI,SS")])
5876 [(set (match_operand:SI 0 "s_operand" "")
5877 (xor:SI (match_dup 0) (match_operand:SI 1 "immediate_operand" "")))
5878 (clobber (reg:CC 33))]
5881 [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1)))
5882 (clobber (reg:CC 33))])]
5883 "s390_narrow_logical_operator (XOR, &operands[0], &operands[1]);")
5885 (define_expand "xorsi3"
5886 [(set (match_operand:SI 0 "nonimmediate_operand" "")
5887 (xor:SI (match_operand:SI 1 "nonimmediate_operand" "")
5888 (match_operand:SI 2 "general_operand" "")))
5889 (clobber (reg:CC 33))]
5891 "s390_expand_logical_operator (XOR, SImode, operands); DONE;")
5894 ; xorhi3 instruction pattern(s).
5897 (define_insn "*xorhi3"
5898 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,AQ,Q")
5899 (xor:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0")
5900 (match_operand:HI 2 "general_operand" "d,NxQH0,Q")))
5901 (clobber (reg:CC 33))]
5902 "s390_logical_operator_ok_p (operands)"
5907 [(set_attr "op_type" "RR,SI,SS")])
5910 [(set (match_operand:HI 0 "s_operand" "")
5911 (xor:HI (match_dup 0) (match_operand:HI 1 "immediate_operand" "")))
5912 (clobber (reg:CC 33))]
5915 [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1)))
5916 (clobber (reg:CC 33))])]
5917 "s390_narrow_logical_operator (XOR, &operands[0], &operands[1]);")
5919 (define_expand "xorhi3"
5920 [(set (match_operand:HI 0 "nonimmediate_operand" "")
5921 (xor:HI (match_operand:HI 1 "nonimmediate_operand" "")
5922 (match_operand:HI 2 "general_operand" "")))
5923 (clobber (reg:CC 33))]
5925 "s390_expand_logical_operator (XOR, HImode, operands); DONE;")
5928 ; xorqi3 instruction pattern(s).
5931 (define_insn "*xorqi3"
5932 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,Q,S,Q")
5933 (xor:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0,0")
5934 (match_operand:QI 2 "general_operand" "d,n,n,Q")))
5935 (clobber (reg:CC 33))]
5936 "s390_logical_operator_ok_p (operands)"
5942 [(set_attr "op_type" "RR,SI,SIY,SS")])
5944 (define_expand "xorqi3"
5945 [(set (match_operand:QI 0 "nonimmediate_operand" "")
5946 (xor:QI (match_operand:QI 1 "nonimmediate_operand" "")
5947 (match_operand:QI 2 "general_operand" "")))
5948 (clobber (reg:CC 33))]
5950 "s390_expand_logical_operator (XOR, QImode, operands); DONE;")
5953 ; Block exclusive or (XC) patterns.
5957 [(set (match_operand:BLK 0 "memory_operand" "=Q")
5958 (xor:BLK (match_dup 0)
5959 (match_operand:BLK 1 "memory_operand" "Q")))
5960 (use (match_operand 2 "const_int_operand" "n"))
5961 (clobber (reg:CC 33))]
5962 "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
5963 "xc\t%O0(%2,%R0),%S1"
5964 [(set_attr "op_type" "SS")])
5967 [(set (match_operand 0 "memory_operand" "")
5969 (match_operand 1 "memory_operand" "")))
5970 (clobber (reg:CC 33))]
5972 && GET_MODE (operands[0]) == GET_MODE (operands[1])
5973 && GET_MODE_SIZE (GET_MODE (operands[0])) > 0"
5975 [(set (match_dup 0) (xor:BLK (match_dup 0) (match_dup 1)))
5977 (clobber (reg:CC 33))])]
5979 operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0])));
5980 operands[0] = adjust_address (operands[0], BLKmode, 0);
5981 operands[1] = adjust_address (operands[1], BLKmode, 0);
5986 [(set (match_operand:BLK 0 "memory_operand" "")
5987 (xor:BLK (match_dup 0)
5988 (match_operand:BLK 1 "memory_operand" "")))
5989 (use (match_operand 2 "const_int_operand" ""))
5990 (clobber (reg:CC 33))])
5992 [(set (match_operand:BLK 3 "memory_operand" "")
5993 (xor:BLK (match_dup 3)
5994 (match_operand:BLK 4 "memory_operand" "")))
5995 (use (match_operand 5 "const_int_operand" ""))
5996 (clobber (reg:CC 33))])]
5997 "s390_offset_p (operands[0], operands[3], operands[2])
5998 && s390_offset_p (operands[1], operands[4], operands[2])
5999 && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256"
6001 [(set (match_dup 6) (xor:BLK (match_dup 6) (match_dup 7)))
6003 (clobber (reg:CC 33))])]
6004 "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
6005 operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0));
6006 operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));")
6009 ; Block xor (XC) patterns with src == dest.
6012 (define_insn "*xc_zero"
6013 [(set (match_operand:BLK 0 "memory_operand" "=Q")
6015 (use (match_operand 1 "const_int_operand" "n"))
6016 (clobber (reg:CC 33))]
6017 "INTVAL (operands[1]) >= 1 && INTVAL (operands[1]) <= 256"
6018 "xc\t%O0(%1,%R0),%S0"
6019 [(set_attr "op_type" "SS")])
6023 [(set (match_operand:BLK 0 "memory_operand" "")
6025 (use (match_operand 1 "const_int_operand" ""))
6026 (clobber (reg:CC 33))])
6028 [(set (match_operand:BLK 2 "memory_operand" "")
6030 (use (match_operand 3 "const_int_operand" ""))
6031 (clobber (reg:CC 33))])]
6032 "s390_offset_p (operands[0], operands[2], operands[1])
6033 && INTVAL (operands[1]) + INTVAL (operands[3]) <= 256"
6035 [(set (match_dup 4) (const_int 0))
6037 (clobber (reg:CC 33))])]
6038 "operands[4] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
6039 operands[5] = GEN_INT (INTVAL (operands[1]) + INTVAL (operands[3]));")
6043 ;;- Negate instructions.
6047 ; negdi2 instruction pattern(s).
6050 (define_expand "negdi2"
6052 [(set (match_operand:DI 0 "register_operand" "=d")
6053 (neg:DI (match_operand:DI 1 "register_operand" "d")))
6054 (clobber (reg:CC 33))])]
6058 (define_insn "*negdi2_sign_cc"
6060 (compare (neg:DI (ashiftrt:DI (ashift:DI (subreg:DI
6061 (match_operand:SI 1 "register_operand" "d") 0)
6062 (const_int 32)) (const_int 32)))
6064 (set (match_operand:DI 0 "register_operand" "=d")
6065 (neg:DI (sign_extend:DI (match_dup 1))))]
6066 "TARGET_64BIT && s390_match_ccmode (insn, CCAmode)"
6068 [(set_attr "op_type" "RRE")])
6070 (define_insn "*negdi2_sign"
6071 [(set (match_operand:DI 0 "register_operand" "=d")
6072 (neg:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "d"))))
6073 (clobber (reg:CC 33))]
6076 [(set_attr "op_type" "RRE")])
6078 (define_insn "*negdi2_cc"
6080 (compare (neg:DI (match_operand:DI 1 "register_operand" "d"))
6082 (set (match_operand:DI 0 "register_operand" "=d")
6083 (neg:DI (match_dup 1)))]
6084 "TARGET_64BIT && s390_match_ccmode (insn, CCAmode)"
6086 [(set_attr "op_type" "RRE")])
6088 (define_insn "*negdi2_cconly"
6090 (compare (neg:DI (match_operand:DI 1 "register_operand" "d"))
6092 (clobber (match_scratch:DI 0 "=d"))]
6093 "TARGET_64BIT && s390_match_ccmode (insn, CCAmode)"
6095 [(set_attr "op_type" "RRE")])
6097 (define_insn "*negdi2_64"
6098 [(set (match_operand:DI 0 "register_operand" "=d")
6099 (neg:DI (match_operand:DI 1 "register_operand" "d")))
6100 (clobber (reg:CC 33))]
6103 [(set_attr "op_type" "RRE")])
6105 (define_insn_and_split "*negdi2_31"
6106 [(set (match_operand:DI 0 "register_operand" "=d")
6107 (neg:DI (match_operand:DI 1 "register_operand" "d")))
6108 (clobber (reg:CC 33))]
6111 "&& reload_completed"
6113 [(set (match_dup 2) (neg:SI (match_dup 3)))
6114 (clobber (reg:CC 33))])
6117 (compare:CCAP (neg:SI (match_dup 5)) (const_int 0)))
6118 (set (match_dup 4) (neg:SI (match_dup 5)))])
6120 (if_then_else (ne (reg:CCAP 33) (const_int 0))
6122 (label_ref (match_dup 6))))
6124 [(set (match_dup 2) (plus:SI (match_dup 2) (const_int -1)))
6125 (clobber (reg:CC 33))])
6127 "operands[2] = operand_subword (operands[0], 0, 0, DImode);
6128 operands[3] = operand_subword (operands[1], 0, 0, DImode);
6129 operands[4] = operand_subword (operands[0], 1, 0, DImode);
6130 operands[5] = operand_subword (operands[1], 1, 0, DImode);
6131 operands[6] = gen_label_rtx ();")
6134 ; negsi2 instruction pattern(s).
6137 (define_insn "*negsi2_cc"
6139 (compare (neg:SI (match_operand:SI 1 "register_operand" "d"))
6141 (set (match_operand:SI 0 "register_operand" "=d")
6142 (neg:SI (match_dup 1)))]
6143 "s390_match_ccmode (insn, CCAmode)"
6145 [(set_attr "op_type" "RR")])
6147 (define_insn "*negsi2_cconly"
6149 (compare (neg:SI (match_operand:SI 1 "register_operand" "d"))
6151 (clobber (match_scratch:SI 0 "=d"))]
6152 "s390_match_ccmode (insn, CCAmode)"
6154 [(set_attr "op_type" "RR")])
6156 (define_insn "negsi2"
6157 [(set (match_operand:SI 0 "register_operand" "=d")
6158 (neg:SI (match_operand:SI 1 "register_operand" "d")))
6159 (clobber (reg:CC 33))]
6162 [(set_attr "op_type" "RR")])
6165 ; negdf2 instruction pattern(s).
6168 (define_expand "negdf2"
6170 [(set (match_operand:DF 0 "register_operand" "=f")
6171 (neg:DF (match_operand:DF 1 "register_operand" "f")))
6172 (clobber (reg:CC 33))])]
6176 (define_insn "*negdf2_cc"
6178 (compare (neg:DF (match_operand:DF 1 "register_operand" "f"))
6179 (match_operand:DF 2 "const0_operand" "")))
6180 (set (match_operand:DF 0 "register_operand" "=f")
6181 (neg:DF (match_dup 1)))]
6182 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
6184 [(set_attr "op_type" "RRE")
6185 (set_attr "type" "fsimpd")])
6187 (define_insn "*negdf2_cconly"
6189 (compare (neg:DF (match_operand:DF 1 "register_operand" "f"))
6190 (match_operand:DF 2 "const0_operand" "")))
6191 (clobber (match_scratch:DF 0 "=f"))]
6192 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
6194 [(set_attr "op_type" "RRE")
6195 (set_attr "type" "fsimpd")])
6197 (define_insn "*negdf2"
6198 [(set (match_operand:DF 0 "register_operand" "=f")
6199 (neg:DF (match_operand:DF 1 "register_operand" "f")))
6200 (clobber (reg:CC 33))]
6201 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
6203 [(set_attr "op_type" "RRE")
6204 (set_attr "type" "fsimpd")])
6206 (define_insn "*negdf2_ibm"
6207 [(set (match_operand:DF 0 "register_operand" "=f")
6208 (neg:DF (match_operand:DF 1 "register_operand" "f")))
6209 (clobber (reg:CC 33))]
6210 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
6212 [(set_attr "op_type" "RR")
6213 (set_attr "type" "fsimpd")])
6216 ; negsf2 instruction pattern(s).
6219 (define_expand "negsf2"
6221 [(set (match_operand:SF 0 "register_operand" "=f")
6222 (neg:SF (match_operand:SF 1 "register_operand" "f")))
6223 (clobber (reg:CC 33))])]
6227 (define_insn "*negsf2_cc"
6229 (compare (neg:SF (match_operand:SF 1 "register_operand" "f"))
6230 (match_operand:SF 2 "const0_operand" "")))
6231 (set (match_operand:SF 0 "register_operand" "=f")
6232 (neg:SF (match_dup 1)))]
6233 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
6235 [(set_attr "op_type" "RRE")
6236 (set_attr "type" "fsimps")])
6238 (define_insn "*negsf2_cconly"
6240 (compare (neg:SF (match_operand:SF 1 "register_operand" "f"))
6241 (match_operand:SF 2 "const0_operand" "")))
6242 (clobber (match_scratch:SF 0 "=f"))]
6243 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
6245 [(set_attr "op_type" "RRE")
6246 (set_attr "type" "fsimps")])
6248 (define_insn "*negsf2"
6249 [(set (match_operand:SF 0 "register_operand" "=f")
6250 (neg:SF (match_operand:SF 1 "register_operand" "f")))
6251 (clobber (reg:CC 33))]
6252 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
6254 [(set_attr "op_type" "RRE")
6255 (set_attr "type" "fsimps")])
6257 (define_insn "*negsf2"
6258 [(set (match_operand:SF 0 "register_operand" "=f")
6259 (neg:SF (match_operand:SF 1 "register_operand" "f")))
6260 (clobber (reg:CC 33))]
6261 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
6263 [(set_attr "op_type" "RR")
6264 (set_attr "type" "fsimps")])
6268 ;;- Absolute value instructions.
6272 ; absdi2 instruction pattern(s).
6275 (define_insn "*absdi2_sign_cc"
6277 (compare (abs:DI (ashiftrt:DI (ashift:DI (subreg:DI
6278 (match_operand:SI 1 "register_operand" "d") 0)
6279 (const_int 32)) (const_int 32)))
6281 (set (match_operand:DI 0 "register_operand" "=d")
6282 (abs:DI (sign_extend:DI (match_dup 1))))]
6283 "TARGET_64BIT && s390_match_ccmode (insn, CCAmode)"
6285 [(set_attr "op_type" "RRE")])
6287 (define_insn "*absdi2_sign"
6288 [(set (match_operand:DI 0 "register_operand" "=d")
6289 (abs:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "d"))))
6290 (clobber (reg:CC 33))]
6293 [(set_attr "op_type" "RRE")])
6295 (define_insn "*absdi2_cc"
6297 (compare (abs:DI (match_operand:DI 1 "register_operand" "d"))
6299 (set (match_operand:DI 0 "register_operand" "=d")
6300 (abs:DI (match_dup 1)))]
6301 "TARGET_64BIT && s390_match_ccmode (insn, CCAmode)"
6303 [(set_attr "op_type" "RRE")])
6305 (define_insn "*absdi2_cconly"
6307 (compare (abs:DI (match_operand:DI 1 "register_operand" "d"))
6309 (clobber (match_scratch:DI 0 "=d"))]
6310 "TARGET_64BIT && s390_match_ccmode (insn, CCAmode)"
6312 [(set_attr "op_type" "RRE")])
6314 (define_insn "absdi2"
6315 [(set (match_operand:DI 0 "register_operand" "=d")
6316 (abs:DI (match_operand:DI 1 "register_operand" "d")))
6317 (clobber (reg:CC 33))]
6320 [(set_attr "op_type" "RRE")])
6323 ; abssi2 instruction pattern(s).
6326 (define_insn "*abssi2_cc"
6328 (compare (abs:SI (match_operand:SI 1 "register_operand" "d"))
6330 (set (match_operand:SI 0 "register_operand" "=d")
6331 (abs:SI (match_dup 1)))]
6332 "s390_match_ccmode (insn, CCAmode)"
6334 [(set_attr "op_type" "RR")])
6336 (define_insn "*abssi2_cconly"
6338 (compare (abs:SI (match_operand:SI 1 "register_operand" "d"))
6340 (clobber (match_scratch:SI 0 "=d"))]
6341 "s390_match_ccmode (insn, CCAmode)"
6343 [(set_attr "op_type" "RR")])
6345 (define_insn "abssi2"
6346 [(set (match_operand:SI 0 "register_operand" "=d")
6347 (abs:SI (match_operand:SI 1 "register_operand" "d")))
6348 (clobber (reg:CC 33))]
6351 [(set_attr "op_type" "RR")])
6354 ; absdf2 instruction pattern(s).
6357 (define_expand "absdf2"
6359 [(set (match_operand:DF 0 "register_operand" "=f")
6360 (abs:DF (match_operand:DF 1 "register_operand" "f")))
6361 (clobber (reg:CC 33))])]
6365 (define_insn "*absdf2_cc"
6367 (compare (abs:DF (match_operand:DF 1 "register_operand" "f"))
6368 (match_operand:DF 2 "const0_operand" "")))
6369 (set (match_operand:DF 0 "register_operand" "=f")
6370 (abs:DF (match_dup 1)))]
6371 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
6373 [(set_attr "op_type" "RRE")
6374 (set_attr "type" "fsimpd")])
6376 (define_insn "*absdf2_cconly"
6378 (compare (abs:DF (match_operand:DF 1 "register_operand" "f"))
6379 (match_operand:DF 2 "const0_operand" "")))
6380 (clobber (match_scratch:DF 0 "=f"))]
6381 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
6383 [(set_attr "op_type" "RRE")
6384 (set_attr "type" "fsimpd")])
6386 (define_insn "*absdf2"
6387 [(set (match_operand:DF 0 "register_operand" "=f")
6388 (abs:DF (match_operand:DF 1 "register_operand" "f")))
6389 (clobber (reg:CC 33))]
6390 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
6392 [(set_attr "op_type" "RRE")
6393 (set_attr "type" "fsimpd")])
6395 (define_insn "*absdf2_ibm"
6396 [(set (match_operand:DF 0 "register_operand" "=f")
6397 (abs:DF (match_operand:DF 1 "register_operand" "f")))
6398 (clobber (reg:CC 33))]
6399 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
6401 [(set_attr "op_type" "RR")
6402 (set_attr "type" "fsimpd")])
6405 ; abssf2 instruction pattern(s).
6408 (define_expand "abssf2"
6410 [(set (match_operand:SF 0 "register_operand" "=f")
6411 (abs:SF (match_operand:SF 1 "register_operand" "f")))
6412 (clobber (reg:CC 33))])]
6416 (define_insn "*abssf2_cc"
6418 (compare (abs:SF (match_operand:SF 1 "register_operand" "f"))
6419 (match_operand:SF 2 "const0_operand" "")))
6420 (set (match_operand:SF 0 "register_operand" "=f")
6421 (abs:SF (match_dup 1)))]
6422 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
6424 [(set_attr "op_type" "RRE")
6425 (set_attr "type" "fsimps")])
6427 (define_insn "*abssf2_cconly"
6429 (compare (abs:SF (match_operand:SF 1 "register_operand" "f"))
6430 (match_operand:SF 2 "const0_operand" "")))
6431 (clobber (match_scratch:SF 0 "=f"))]
6432 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
6434 [(set_attr "op_type" "RRE")
6435 (set_attr "type" "fsimps")])
6437 (define_insn "*abssf2"
6438 [(set (match_operand:SF 0 "register_operand" "=f")
6439 (abs:SF (match_operand:SF 1 "register_operand" "f")))
6440 (clobber (reg:CC 33))]
6441 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
6443 [(set_attr "op_type" "RRE")
6444 (set_attr "type" "fsimps")])
6446 (define_insn "*abssf2_ibm"
6447 [(set (match_operand:SF 0 "register_operand" "=f")
6448 (abs:SF (match_operand:SF 1 "register_operand" "f")))
6449 (clobber (reg:CC 33))]
6450 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
6452 [(set_attr "op_type" "RR")
6453 (set_attr "type" "fsimps")])
6456 ;;- Negated absolute value instructions
6463 (define_insn "*negabsdi2_sign_cc"
6465 (compare (neg:DI (abs:DI (ashiftrt:DI (ashift:DI (subreg:DI
6466 (match_operand:SI 1 "register_operand" "d") 0)
6467 (const_int 32)) (const_int 32))))
6469 (set (match_operand:DI 0 "register_operand" "=d")
6470 (neg:DI (abs:DI (sign_extend:DI (match_dup 1)))))]
6471 "TARGET_64BIT && s390_match_ccmode (insn, CCAmode)"
6473 [(set_attr "op_type" "RRE")])
6475 (define_insn "*negabsdi2_sign"
6476 [(set (match_operand:DI 0 "register_operand" "=d")
6477 (neg:DI (abs:DI (sign_extend:DI
6478 (match_operand:SI 1 "register_operand" "d")))))
6479 (clobber (reg:CC 33))]
6482 [(set_attr "op_type" "RRE")])
6484 (define_insn "*negabsdi2_cc"
6486 (compare (neg:DI (abs:DI (match_operand:DI 1 "register_operand" "d")))
6488 (set (match_operand:DI 0 "register_operand" "=d")
6489 (neg:DI (abs:DI (match_dup 1))))]
6490 "TARGET_64BIT && s390_match_ccmode (insn, CCAmode)"
6492 [(set_attr "op_type" "RRE")])
6494 (define_insn "*negabsdi2_cconly"
6496 (compare (neg:DI (abs:DI (match_operand:DI 1 "register_operand" "d")))
6498 (clobber (match_scratch:DI 0 "=d"))]
6499 "TARGET_64BIT && s390_match_ccmode (insn, CCAmode)"
6501 [(set_attr "op_type" "RRE")])
6503 (define_insn "*negabsdi2"
6504 [(set (match_operand:DI 0 "register_operand" "=d")
6505 (neg:DI (abs:DI (match_operand:DI 1 "register_operand" "d"))))
6506 (clobber (reg:CC 33))]
6509 [(set_attr "op_type" "RRE")])
6511 (define_insn "*negabssi2_cc"
6513 (compare (neg:SI (abs:SI (match_operand:SI 1 "register_operand" "d")))
6515 (set (match_operand:SI 0 "register_operand" "=d")
6516 (neg:SI (abs:SI (match_dup 1))))]
6517 "s390_match_ccmode (insn, CCAmode)"
6519 [(set_attr "op_type" "RR")])
6521 (define_insn "*negabssi2_cconly"
6523 (compare (neg:SI (abs:SI (match_operand:SI 1 "register_operand" "d")))
6525 (clobber (match_scratch:SI 0 "=d"))]
6526 "s390_match_ccmode (insn, CCAmode)"
6528 [(set_attr "op_type" "RR")])
6530 (define_insn "*negabssi2"
6531 [(set (match_operand:SI 0 "register_operand" "=d")
6532 (neg:SI (abs:SI (match_operand:SI 1 "register_operand" "d"))))
6533 (clobber (reg:CC 33))]
6536 [(set_attr "op_type" "RR")])
6542 (define_insn "*negabsdf2_cc"
6544 (compare (neg:DF (abs:DF (match_operand:DF 1 "register_operand" "f")))
6545 (match_operand:DF 2 "const0_operand" "")))
6546 (set (match_operand:DF 0 "register_operand" "=f")
6547 (neg:DF (abs:DF (match_dup 1))))]
6548 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
6550 [(set_attr "op_type" "RRE")
6551 (set_attr "type" "fsimpd")])
6553 (define_insn "*negabsdf2_cconly"
6555 (compare (neg:DF (abs:DF (match_operand:DF 1 "register_operand" "f")))
6556 (match_operand:DF 2 "const0_operand" "")))
6557 (clobber (match_scratch:DF 0 "=f"))]
6558 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
6560 [(set_attr "op_type" "RRE")
6561 (set_attr "type" "fsimpd")])
6563 (define_insn "*negabsdf2"
6564 [(set (match_operand:DF 0 "register_operand" "=f")
6565 (neg:DF (abs:DF (match_operand:DF 1 "register_operand" "f"))))
6566 (clobber (reg:CC 33))]
6567 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
6569 [(set_attr "op_type" "RRE")
6570 (set_attr "type" "fsimpd")])
6572 (define_insn "*negabssf2_cc"
6574 (compare (neg:SF (abs:SF (match_operand:SF 1 "register_operand" "f")))
6575 (match_operand:SF 2 "const0_operand" "")))
6576 (set (match_operand:SF 0 "register_operand" "=f")
6577 (neg:SF (abs:SF (match_dup 1))))]
6578 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
6580 [(set_attr "op_type" "RRE")
6581 (set_attr "type" "fsimps")])
6583 (define_insn "*negabssf2_cconly"
6585 (compare (neg:SF (abs:SF (match_operand:SF 1 "register_operand" "f")))
6586 (match_operand:SF 2 "const0_operand" "")))
6587 (clobber (match_scratch:SF 0 "=f"))]
6588 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
6590 [(set_attr "op_type" "RRE")
6591 (set_attr "type" "fsimps")])
6593 (define_insn "*negabssf2"
6594 [(set (match_operand:SF 0 "register_operand" "=f")
6595 (neg:SF (abs:SF (match_operand:SF 1 "register_operand" "f"))))
6596 (clobber (reg:CC 33))]
6597 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
6599 [(set_attr "op_type" "RRE")
6600 (set_attr "type" "fsimps")])
6603 ;;- Square root instructions.
6607 ; sqrtdf2 instruction pattern(s).
6610 (define_insn "sqrtdf2"
6611 [(set (match_operand:DF 0 "register_operand" "=f,f")
6612 (sqrt:DF (match_operand:DF 1 "general_operand" "f,R")))]
6613 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
6617 [(set_attr "op_type" "RRE,RXE")
6618 (set_attr "type" "fsqrtd")])
6621 ; sqrtsf2 instruction pattern(s).
6624 (define_insn "sqrtsf2"
6625 [(set (match_operand:SF 0 "register_operand" "=f,f")
6626 (sqrt:SF (match_operand:SF 1 "general_operand" "f,R")))]
6627 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
6631 [(set_attr "op_type" "RRE,RXE")
6632 (set_attr "type" "fsqrts")])
6635 ;;- One complement instructions.
6639 ; one_cmpldi2 instruction pattern(s).
6642 (define_expand "one_cmpldi2"
6644 [(set (match_operand:DI 0 "register_operand" "")
6645 (xor:DI (match_operand:DI 1 "register_operand" "")
6647 (clobber (reg:CC 33))])]
6652 ; one_cmplsi2 instruction pattern(s).
6655 (define_expand "one_cmplsi2"
6657 [(set (match_operand:SI 0 "register_operand" "")
6658 (xor:SI (match_operand:SI 1 "register_operand" "")
6660 (clobber (reg:CC 33))])]
6665 ; one_cmplhi2 instruction pattern(s).
6668 (define_expand "one_cmplhi2"
6670 [(set (match_operand:HI 0 "register_operand" "")
6671 (xor:HI (match_operand:HI 1 "register_operand" "")
6673 (clobber (reg:CC 33))])]
6678 ; one_cmplqi2 instruction pattern(s).
6681 (define_expand "one_cmplqi2"
6683 [(set (match_operand:QI 0 "register_operand" "")
6684 (xor:QI (match_operand:QI 1 "register_operand" "")
6686 (clobber (reg:CC 33))])]
6692 ;;- Rotate instructions.
6696 ; rotldi3 instruction pattern(s).
6699 (define_insn "rotldi3"
6700 [(set (match_operand:DI 0 "register_operand" "=d")
6701 (rotate:DI (match_operand:DI 1 "register_operand" "d")
6702 (match_operand:SI 2 "shift_count_operand" "Y")))]
6705 [(set_attr "op_type" "RSE")
6706 (set_attr "atype" "reg")])
6709 ; rotlsi3 instruction pattern(s).
6712 (define_insn "rotlsi3"
6713 [(set (match_operand:SI 0 "register_operand" "=d")
6714 (rotate:SI (match_operand:SI 1 "register_operand" "d")
6715 (match_operand:SI 2 "shift_count_operand" "Y")))]
6718 [(set_attr "op_type" "RSE")
6719 (set_attr "atype" "reg")])
6723 ;;- Arithmetic shift instructions.
6727 ; ashldi3 instruction pattern(s).
6730 (define_expand "ashldi3"
6731 [(set (match_operand:DI 0 "register_operand" "")
6732 (ashift:DI (match_operand:DI 1 "register_operand" "")
6733 (match_operand:SI 2 "shift_count_operand" "")))]
6737 (define_insn "*ashldi3_31"
6738 [(set (match_operand:DI 0 "register_operand" "=d")
6739 (ashift:DI (match_operand:DI 1 "register_operand" "0")
6740 (match_operand:SI 2 "shift_count_operand" "Y")))]
6743 [(set_attr "op_type" "RS")
6744 (set_attr "atype" "reg")])
6746 (define_insn "*ashldi3_64"
6747 [(set (match_operand:DI 0 "register_operand" "=d")
6748 (ashift:DI (match_operand:DI 1 "register_operand" "d")
6749 (match_operand:SI 2 "shift_count_operand" "Y")))]
6752 [(set_attr "op_type" "RSE")
6753 (set_attr "atype" "reg")])
6756 ; ashrdi3 instruction pattern(s).
6759 (define_expand "ashrdi3"
6761 [(set (match_operand:DI 0 "register_operand" "")
6762 (ashiftrt:DI (match_operand:DI 1 "register_operand" "")
6763 (match_operand:SI 2 "shift_count_operand" "")))
6764 (clobber (reg:CC 33))])]
6768 (define_insn "*ashrdi3_cc_31"
6770 (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
6771 (match_operand:SI 2 "shift_count_operand" "Y"))
6773 (set (match_operand:DI 0 "register_operand" "=d")
6774 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
6775 "!TARGET_64BIT && s390_match_ccmode(insn, CCSmode)"
6777 [(set_attr "op_type" "RS")
6778 (set_attr "atype" "reg")])
6780 (define_insn "*ashrdi3_cconly_31"
6782 (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
6783 (match_operand:SI 2 "shift_count_operand" "Y"))
6785 (clobber (match_scratch:DI 0 "=d"))]
6786 "!TARGET_64BIT && s390_match_ccmode(insn, CCSmode)"
6788 [(set_attr "op_type" "RS")
6789 (set_attr "atype" "reg")])
6791 (define_insn "*ashrdi3_31"
6792 [(set (match_operand:DI 0 "register_operand" "=d")
6793 (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
6794 (match_operand:SI 2 "shift_count_operand" "Y")))
6795 (clobber (reg:CC 33))]
6798 [(set_attr "op_type" "RS")
6799 (set_attr "atype" "reg")])
6801 (define_insn "*ashrdi3_cc_64"
6803 (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "d")
6804 (match_operand:SI 2 "shift_count_operand" "Y"))
6806 (set (match_operand:DI 0 "register_operand" "=d")
6807 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
6808 "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT"
6810 [(set_attr "op_type" "RSE")
6811 (set_attr "atype" "reg")])
6813 (define_insn "*ashrdi3_cconly_64"
6815 (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "d")
6816 (match_operand:SI 2 "shift_count_operand" "Y"))
6818 (clobber (match_scratch:DI 0 "=d"))]
6819 "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT"
6821 [(set_attr "op_type" "RSE")
6822 (set_attr "atype" "reg")])
6824 (define_insn "*ashrdi3_64"
6825 [(set (match_operand:DI 0 "register_operand" "=d")
6826 (ashiftrt:DI (match_operand:DI 1 "register_operand" "d")
6827 (match_operand:SI 2 "shift_count_operand" "Y")))
6828 (clobber (reg:CC 33))]
6831 [(set_attr "op_type" "RSE")
6832 (set_attr "atype" "reg")])
6836 ; ashlsi3 instruction pattern(s).
6839 (define_insn "ashlsi3"
6840 [(set (match_operand:SI 0 "register_operand" "=d")
6841 (ashift:SI (match_operand:SI 1 "register_operand" "0")
6842 (match_operand:SI 2 "shift_count_operand" "Y")))]
6845 [(set_attr "op_type" "RS")
6846 (set_attr "atype" "reg")])
6849 ; ashrsi3 instruction pattern(s).
6852 (define_insn "*ashrsi3_cc"
6854 (compare (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
6855 (match_operand:SI 2 "shift_count_operand" "Y"))
6857 (set (match_operand:SI 0 "register_operand" "=d")
6858 (ashiftrt:SI (match_dup 1) (match_dup 2)))]
6859 "s390_match_ccmode(insn, CCSmode)"
6861 [(set_attr "op_type" "RS")
6862 (set_attr "atype" "reg")])
6865 (define_insn "*ashrsi3_cconly"
6867 (compare (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
6868 (match_operand:SI 2 "shift_count_operand" "Y"))
6870 (clobber (match_scratch:SI 0 "=d"))]
6871 "s390_match_ccmode(insn, CCSmode)"
6873 [(set_attr "op_type" "RS")
6874 (set_attr "atype" "reg")])
6876 (define_insn "ashrsi3"
6877 [(set (match_operand:SI 0 "register_operand" "=d")
6878 (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
6879 (match_operand:SI 2 "shift_count_operand" "Y")))
6880 (clobber (reg:CC 33))]
6883 [(set_attr "op_type" "RS")
6884 (set_attr "atype" "reg")])
6888 ;;- logical shift instructions.
6892 ; lshrdi3 instruction pattern(s).
6895 (define_expand "lshrdi3"
6896 [(set (match_operand:DI 0 "register_operand" "")
6897 (lshiftrt:DI (match_operand:DI 1 "register_operand" "")
6898 (match_operand:SI 2 "shift_count_operand" "")))]
6902 (define_insn "*lshrdi3_31"
6903 [(set (match_operand:DI 0 "register_operand" "=d")
6904 (lshiftrt:DI (match_operand:DI 1 "register_operand" "0")
6905 (match_operand:SI 2 "shift_count_operand" "Y")))]
6908 [(set_attr "op_type" "RS")
6909 (set_attr "atype" "reg")])
6911 (define_insn "*lshrdi3_64"
6912 [(set (match_operand:DI 0 "register_operand" "=d")
6913 (lshiftrt:DI (match_operand:DI 1 "register_operand" "d")
6914 (match_operand:SI 2 "shift_count_operand" "Y")))]
6917 [(set_attr "op_type" "RSE")
6918 (set_attr "atype" "reg")])
6921 ; lshrsi3 instruction pattern(s).
6924 (define_insn "lshrsi3"
6925 [(set (match_operand:SI 0 "register_operand" "=d")
6926 (lshiftrt:SI (match_operand:SI 1 "register_operand" "0")
6927 (match_operand:SI 2 "shift_count_operand" "Y")))]
6930 [(set_attr "op_type" "RS")
6931 (set_attr "atype" "reg")])
6935 ;; Branch instruction patterns.
6938 (define_expand "beq"
6939 [(match_operand 0 "" "")]
6941 "s390_emit_jump (operands[0],
6942 s390_emit_compare (EQ, s390_compare_op0, s390_compare_op1)); DONE;")
6944 (define_expand "bne"
6945 [(match_operand 0 "" "")]
6947 "s390_emit_jump (operands[0],
6948 s390_emit_compare (NE, s390_compare_op0, s390_compare_op1)); DONE;")
6950 (define_expand "bgt"
6951 [(match_operand 0 "" "")]
6953 "s390_emit_jump (operands[0],
6954 s390_emit_compare (GT, s390_compare_op0, s390_compare_op1)); DONE;")
6956 (define_expand "bgtu"
6957 [(match_operand 0 "" "")]
6959 "s390_emit_jump (operands[0],
6960 s390_emit_compare (GTU, s390_compare_op0, s390_compare_op1)); DONE;")
6962 (define_expand "blt"
6963 [(match_operand 0 "" "")]
6965 "s390_emit_jump (operands[0],
6966 s390_emit_compare (LT, s390_compare_op0, s390_compare_op1)); DONE;")
6968 (define_expand "bltu"
6969 [(match_operand 0 "" "")]
6971 "s390_emit_jump (operands[0],
6972 s390_emit_compare (LTU, s390_compare_op0, s390_compare_op1)); DONE;")
6974 (define_expand "bge"
6975 [(match_operand 0 "" "")]
6977 "s390_emit_jump (operands[0],
6978 s390_emit_compare (GE, s390_compare_op0, s390_compare_op1)); DONE;")
6980 (define_expand "bgeu"
6981 [(match_operand 0 "" "")]
6983 "s390_emit_jump (operands[0],
6984 s390_emit_compare (GEU, s390_compare_op0, s390_compare_op1)); DONE;")
6986 (define_expand "ble"
6987 [(match_operand 0 "" "")]
6989 "s390_emit_jump (operands[0],
6990 s390_emit_compare (LE, s390_compare_op0, s390_compare_op1)); DONE;")
6992 (define_expand "bleu"
6993 [(match_operand 0 "" "")]
6995 "s390_emit_jump (operands[0],
6996 s390_emit_compare (LEU, s390_compare_op0, s390_compare_op1)); DONE;")
6998 (define_expand "bunordered"
6999 [(match_operand 0 "" "")]
7001 "s390_emit_jump (operands[0],
7002 s390_emit_compare (UNORDERED, s390_compare_op0, s390_compare_op1)); DONE;")
7004 (define_expand "bordered"
7005 [(match_operand 0 "" "")]
7007 "s390_emit_jump (operands[0],
7008 s390_emit_compare (ORDERED, s390_compare_op0, s390_compare_op1)); DONE;")
7010 (define_expand "buneq"
7011 [(match_operand 0 "" "")]
7013 "s390_emit_jump (operands[0],
7014 s390_emit_compare (UNEQ, s390_compare_op0, s390_compare_op1)); DONE;")
7016 (define_expand "bunlt"
7017 [(match_operand 0 "" "")]
7019 "s390_emit_jump (operands[0],
7020 s390_emit_compare (UNLT, s390_compare_op0, s390_compare_op1)); DONE;")
7022 (define_expand "bungt"
7023 [(match_operand 0 "" "")]
7025 "s390_emit_jump (operands[0],
7026 s390_emit_compare (UNGT, s390_compare_op0, s390_compare_op1)); DONE;")
7028 (define_expand "bunle"
7029 [(match_operand 0 "" "")]
7031 "s390_emit_jump (operands[0],
7032 s390_emit_compare (UNLE, s390_compare_op0, s390_compare_op1)); DONE;")
7034 (define_expand "bunge"
7035 [(match_operand 0 "" "")]
7037 "s390_emit_jump (operands[0],
7038 s390_emit_compare (UNGE, s390_compare_op0, s390_compare_op1)); DONE;")
7040 (define_expand "bltgt"
7041 [(match_operand 0 "" "")]
7043 "s390_emit_jump (operands[0],
7044 s390_emit_compare (LTGT, s390_compare_op0, s390_compare_op1)); DONE;")
7048 ;;- Conditional jump instructions.
7051 (define_insn "*cjump_64"
7054 (match_operator 1 "s390_comparison" [(reg 33) (const_int 0)])
7055 (label_ref (match_operand 0 "" ""))
7059 if (get_attr_length (insn) == 4)
7062 return "jg%C1\t%l0";
7064 [(set_attr "op_type" "RI")
7065 (set_attr "type" "branch")
7066 (set (attr "length")
7067 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
7068 (const_int 4) (const_int 6)))])
7070 (define_insn "*cjump_31"
7073 (match_operator 1 "s390_comparison" [(reg 33) (const_int 0)])
7074 (label_ref (match_operand 0 "" ""))
7078 if (get_attr_length (insn) == 4)
7083 [(set_attr "op_type" "RI")
7084 (set_attr "type" "branch")
7085 (set (attr "length")
7086 (if_then_else (eq (symbol_ref "flag_pic") (const_int 0))
7087 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
7088 (const_int 4) (const_int 6))
7089 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
7090 (const_int 4) (const_int 8))))])
7092 (define_insn "*cjump_long"
7095 (match_operator 1 "s390_comparison" [(reg 33) (const_int 0)])
7096 (match_operand 0 "address_operand" "U")
7100 if (get_attr_op_type (insn) == OP_TYPE_RR)
7105 [(set (attr "op_type")
7106 (if_then_else (match_operand 0 "register_operand" "")
7107 (const_string "RR") (const_string "RX")))
7108 (set_attr "type" "branch")
7109 (set_attr "atype" "agen")])
7113 ;;- Negated conditional jump instructions.
7116 (define_insn "*icjump_64"
7119 (match_operator 1 "s390_comparison" [(reg 33) (const_int 0)])
7121 (label_ref (match_operand 0 "" ""))))]
7124 if (get_attr_length (insn) == 4)
7127 return "jg%D1\t%l0";
7129 [(set_attr "op_type" "RI")
7130 (set_attr "type" "branch")
7131 (set (attr "length")
7132 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
7133 (const_int 4) (const_int 6)))])
7135 (define_insn "*icjump_31"
7138 (match_operator 1 "s390_comparison" [(reg 33) (const_int 0)])
7140 (label_ref (match_operand 0 "" ""))))]
7143 if (get_attr_length (insn) == 4)
7148 [(set_attr "op_type" "RI")
7149 (set_attr "type" "branch")
7150 (set (attr "length")
7151 (if_then_else (eq (symbol_ref "flag_pic") (const_int 0))
7152 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
7153 (const_int 4) (const_int 6))
7154 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
7155 (const_int 4) (const_int 8))))])
7157 (define_insn "*icjump_long"
7160 (match_operator 1 "s390_comparison" [(reg 33) (const_int 0)])
7162 (match_operand 0 "address_operand" "U")))]
7165 if (get_attr_op_type (insn) == OP_TYPE_RR)
7170 [(set (attr "op_type")
7171 (if_then_else (match_operand 0 "register_operand" "")
7172 (const_string "RR") (const_string "RX")))
7173 (set_attr "type" "branch")
7174 (set_attr "atype" "agen")])
7177 ;;- Trap instructions.
7181 [(trap_if (const_int 1) (const_int 0))]
7184 [(set_attr "op_type" "RI")
7185 (set_attr "type" "branch")])
7187 (define_expand "conditional_trap"
7188 [(trap_if (match_operand 0 "comparison_operator" "")
7189 (match_operand 1 "general_operand" ""))]
7192 if (operands[1] != const0_rtx) FAIL;
7193 operands[0] = s390_emit_compare (GET_CODE (operands[0]),
7194 s390_compare_op0, s390_compare_op1);
7197 (define_insn "*trap"
7198 [(trap_if (match_operator 0 "s390_comparison" [(reg 33) (const_int 0)])
7202 [(set_attr "op_type" "RI")
7203 (set_attr "type" "branch")])
7206 ;;- Loop instructions.
7208 ;; This is all complicated by the fact that since this is a jump insn
7209 ;; we must handle our own output reloads.
7211 (define_expand "doloop_end"
7212 [(use (match_operand 0 "" "")) ; loop pseudo
7213 (use (match_operand 1 "" "")) ; iterations; zero if unknown
7214 (use (match_operand 2 "" "")) ; max iterations
7215 (use (match_operand 3 "" "")) ; loop level
7216 (use (match_operand 4 "" ""))] ; label
7219 if (GET_MODE (operands[0]) == SImode && !TARGET_CPU_ZARCH)
7220 emit_jump_insn (gen_doloop_si31 (operands[4], operands[0], operands[0]));
7221 else if (GET_MODE (operands[0]) == SImode && TARGET_CPU_ZARCH)
7222 emit_jump_insn (gen_doloop_si64 (operands[4], operands[0], operands[0]));
7223 else if (GET_MODE (operands[0]) == DImode && TARGET_64BIT)
7224 emit_jump_insn (gen_doloop_di (operands[4], operands[0], operands[0]));
7231 (define_insn_and_split "doloop_si64"
7234 (ne (match_operand:SI 1 "register_operand" "d,d")
7236 (label_ref (match_operand 0 "" ""))
7238 (set (match_operand:SI 2 "nonimmediate_operand" "=1,?*m*d")
7239 (plus:SI (match_dup 1) (const_int -1)))
7240 (clobber (match_scratch:SI 3 "=X,&1"))
7241 (clobber (reg:CC 33))]
7244 if (which_alternative != 0)
7246 else if (get_attr_length (insn) == 4)
7247 return "brct\t%1,%l0";
7249 return "ahi\t%1,-1\;jgne\t%l0";
7251 "&& reload_completed
7252 && (! REG_P (operands[2])
7253 || ! rtx_equal_p (operands[1], operands[2]))"
7254 [(parallel [(set (reg:CCAN 33)
7255 (compare:CCAN (plus:SI (match_dup 3) (const_int -1))
7257 (set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))])
7258 (set (match_dup 2) (match_dup 3))
7259 (set (pc) (if_then_else (ne (reg:CCAN 33) (const_int 0))
7260 (label_ref (match_dup 0))
7263 [(set_attr "op_type" "RI")
7264 (set_attr "type" "branch")
7265 (set (attr "length")
7266 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
7267 (const_int 4) (const_int 10)))])
7269 (define_insn_and_split "doloop_si31"
7272 (ne (match_operand:SI 1 "register_operand" "d,d")
7274 (label_ref (match_operand 0 "" ""))
7276 (set (match_operand:SI 2 "nonimmediate_operand" "=1,?*m*d")
7277 (plus:SI (match_dup 1) (const_int -1)))
7278 (clobber (match_scratch:SI 3 "=X,&1"))
7279 (clobber (reg:CC 33))]
7282 if (which_alternative != 0)
7284 else if (get_attr_length (insn) == 4)
7285 return "brct\t%1,%l0";
7289 "&& reload_completed
7290 && (! REG_P (operands[2])
7291 || ! rtx_equal_p (operands[1], operands[2]))"
7292 [(parallel [(set (reg:CCAN 33)
7293 (compare:CCAN (plus:SI (match_dup 3) (const_int -1))
7295 (set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))])
7296 (set (match_dup 2) (match_dup 3))
7297 (set (pc) (if_then_else (ne (reg:CCAN 33) (const_int 0))
7298 (label_ref (match_dup 0))
7301 [(set_attr "op_type" "RI")
7302 (set_attr "type" "branch")
7303 (set (attr "length")
7304 (if_then_else (eq (symbol_ref "flag_pic") (const_int 0))
7305 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
7306 (const_int 4) (const_int 6))
7307 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
7308 (const_int 4) (const_int 8))))])
7310 (define_insn "*doloop_si_long"
7313 (ne (match_operand:SI 1 "register_operand" "d,d")
7315 (match_operand 0 "address_operand" "U,U")
7317 (set (match_operand:SI 2 "register_operand" "=1,?*m*d")
7318 (plus:SI (match_dup 1) (const_int -1)))
7319 (clobber (match_scratch:SI 3 "=X,&1"))
7320 (clobber (reg:CC 33))]
7323 if (get_attr_op_type (insn) == OP_TYPE_RR)
7324 return "bctr\t%1,%0";
7326 return "bct\t%1,%a0";
7328 [(set (attr "op_type")
7329 (if_then_else (match_operand 0 "register_operand" "")
7330 (const_string "RR") (const_string "RX")))
7331 (set_attr "type" "branch")
7332 (set_attr "atype" "agen")])
7334 (define_insn_and_split "doloop_di"
7337 (ne (match_operand:DI 1 "register_operand" "d,d")
7339 (label_ref (match_operand 0 "" ""))
7341 (set (match_operand:DI 2 "nonimmediate_operand" "=1,?*m*d")
7342 (plus:DI (match_dup 1) (const_int -1)))
7343 (clobber (match_scratch:DI 3 "=X,&1"))
7344 (clobber (reg:CC 33))]
7347 if (which_alternative != 0)
7349 else if (get_attr_length (insn) == 4)
7350 return "brctg\t%1,%l0";
7352 return "aghi\t%1,-1\;jgne\t%l0";
7354 "&& reload_completed
7355 && (! REG_P (operands[2])
7356 || ! rtx_equal_p (operands[1], operands[2]))"
7357 [(parallel [(set (reg:CCAN 33)
7358 (compare:CCAN (plus:DI (match_dup 3) (const_int -1))
7360 (set (match_dup 3) (plus:DI (match_dup 3) (const_int -1)))])
7361 (set (match_dup 2) (match_dup 3))
7362 (set (pc) (if_then_else (ne (reg:CCAN 33) (const_int 0))
7363 (label_ref (match_dup 0))
7366 [(set_attr "op_type" "RI")
7367 (set_attr "type" "branch")
7368 (set (attr "length")
7369 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
7370 (const_int 4) (const_int 10)))])
7373 ;;- Unconditional jump instructions.
7377 ; jump instruction pattern(s).
7380 (define_expand "jump"
7381 [(match_operand 0 "" "")]
7383 "s390_emit_jump (operands[0], NULL_RTX); DONE;")
7385 (define_insn "*jump64"
7386 [(set (pc) (label_ref (match_operand 0 "" "")))]
7389 if (get_attr_length (insn) == 4)
7394 [(set_attr "op_type" "RI")
7395 (set_attr "type" "branch")
7396 (set (attr "length")
7397 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
7398 (const_int 4) (const_int 6)))])
7400 (define_insn "*jump31"
7401 [(set (pc) (label_ref (match_operand 0 "" "")))]
7404 if (get_attr_length (insn) == 4)
7409 [(set_attr "op_type" "RI")
7410 (set_attr "type" "branch")
7411 (set (attr "length")
7412 (if_then_else (eq (symbol_ref "flag_pic") (const_int 0))
7413 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
7414 (const_int 4) (const_int 6))
7415 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
7416 (const_int 4) (const_int 8))))])
7419 ; indirect-jump instruction pattern(s).
7422 (define_insn "indirect_jump"
7423 [(set (pc) (match_operand 0 "address_operand" "U"))]
7426 if (get_attr_op_type (insn) == OP_TYPE_RR)
7431 [(set (attr "op_type")
7432 (if_then_else (match_operand 0 "register_operand" "")
7433 (const_string "RR") (const_string "RX")))
7434 (set_attr "type" "branch")
7435 (set_attr "atype" "agen")])
7438 ; casesi instruction pattern(s).
7441 (define_insn "casesi_jump"
7442 [(set (pc) (match_operand 0 "address_operand" "U"))
7443 (use (label_ref (match_operand 1 "" "")))]
7446 if (get_attr_op_type (insn) == OP_TYPE_RR)
7451 [(set (attr "op_type")
7452 (if_then_else (match_operand 0 "register_operand" "")
7453 (const_string "RR") (const_string "RX")))
7454 (set_attr "type" "branch")
7455 (set_attr "atype" "agen")])
7457 (define_expand "casesi"
7458 [(match_operand:SI 0 "general_operand" "")
7459 (match_operand:SI 1 "general_operand" "")
7460 (match_operand:SI 2 "general_operand" "")
7461 (label_ref (match_operand 3 "" ""))
7462 (label_ref (match_operand 4 "" ""))]
7465 rtx index = gen_reg_rtx (SImode);
7466 rtx base = gen_reg_rtx (Pmode);
7467 rtx target = gen_reg_rtx (Pmode);
7469 emit_move_insn (index, operands[0]);
7470 emit_insn (gen_subsi3 (index, index, operands[1]));
7471 emit_cmp_and_jump_insns (index, operands[2], GTU, NULL_RTX, SImode, 1,
7474 if (Pmode != SImode)
7475 index = convert_to_mode (Pmode, index, 1);
7476 if (GET_CODE (index) != REG)
7477 index = copy_to_mode_reg (Pmode, index);
7480 emit_insn (gen_ashldi3 (index, index, GEN_INT (3)));
7482 emit_insn (gen_ashlsi3 (index, index, const2_rtx));
7484 emit_move_insn (base, gen_rtx_LABEL_REF (Pmode, operands[3]));
7486 index = gen_const_mem (Pmode, gen_rtx_PLUS (Pmode, base, index));
7487 emit_move_insn (target, index);
7490 target = gen_rtx_PLUS (Pmode, base, target);
7491 emit_jump_insn (gen_casesi_jump (target, operands[3]));
7498 ;;- Jump to subroutine.
7503 ; untyped call instruction pattern(s).
7506 ;; Call subroutine returning any type.
7507 (define_expand "untyped_call"
7508 [(parallel [(call (match_operand 0 "" "")
7510 (match_operand 1 "" "")
7511 (match_operand 2 "" "")])]
7516 emit_call_insn (gen_call (operands[0], const0_rtx, const0_rtx));
7518 for (i = 0; i < XVECLEN (operands[2], 0); i++)
7520 rtx set = XVECEXP (operands[2], 0, i);
7521 emit_move_insn (SET_DEST (set), SET_SRC (set));
7524 /* The optimizer does not know that the call sets the function value
7525 registers we stored in the result block. We avoid problems by
7526 claiming that all hard registers are used and clobbered at this
7528 emit_insn (gen_blockage ());
7533 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
7534 ;; all of memory. This blocks insns from being moved across this point.
7536 (define_insn "blockage"
7537 [(unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)]
7540 [(set_attr "type" "none")
7541 (set_attr "length" "0")])
7547 (define_expand "sibcall"
7548 [(call (match_operand 0 "" "")
7549 (match_operand 1 "" ""))]
7552 s390_emit_call (XEXP (operands[0], 0), NULL_RTX, NULL_RTX, NULL_RTX);
7556 (define_insn "*sibcall_br"
7557 [(call (mem:QI (reg 1))
7558 (match_operand 0 "const_int_operand" "n"))]
7559 "SIBLING_CALL_P (insn)
7560 && GET_MODE (XEXP (XEXP (PATTERN (insn), 0), 0)) == Pmode"
7562 [(set_attr "op_type" "RR")
7563 (set_attr "type" "branch")
7564 (set_attr "atype" "agen")])
7566 (define_insn "*sibcall_brc"
7567 [(call (mem:QI (match_operand 0 "bras_sym_operand" "X"))
7568 (match_operand 1 "const_int_operand" "n"))]
7569 "SIBLING_CALL_P (insn) && TARGET_SMALL_EXEC"
7571 [(set_attr "op_type" "RI")
7572 (set_attr "type" "branch")])
7574 (define_insn "*sibcall_brcl"
7575 [(call (mem:QI (match_operand 0 "bras_sym_operand" "X"))
7576 (match_operand 1 "const_int_operand" "n"))]
7577 "SIBLING_CALL_P (insn) && TARGET_CPU_ZARCH"
7579 [(set_attr "op_type" "RIL")
7580 (set_attr "type" "branch")])
7583 ; sibcall_value patterns
7586 (define_expand "sibcall_value"
7587 [(set (match_operand 0 "" "")
7588 (call (match_operand 1 "" "")
7589 (match_operand 2 "" "")))]
7592 s390_emit_call (XEXP (operands[1], 0), NULL_RTX, operands[0], NULL_RTX);
7596 (define_insn "*sibcall_value_br"
7597 [(set (match_operand 0 "" "")
7598 (call (mem:QI (reg 1))
7599 (match_operand 1 "const_int_operand" "n")))]
7600 "SIBLING_CALL_P (insn)
7601 && GET_MODE (XEXP (XEXP (XEXP (PATTERN (insn), 1), 0), 0)) == Pmode"
7603 [(set_attr "op_type" "RR")
7604 (set_attr "type" "branch")
7605 (set_attr "atype" "agen")])
7607 (define_insn "*sibcall_value_brc"
7608 [(set (match_operand 0 "" "")
7609 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
7610 (match_operand 2 "const_int_operand" "n")))]
7611 "SIBLING_CALL_P (insn) && TARGET_SMALL_EXEC"
7613 [(set_attr "op_type" "RI")
7614 (set_attr "type" "branch")])
7616 (define_insn "*sibcall_value_brcl"
7617 [(set (match_operand 0 "" "")
7618 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
7619 (match_operand 2 "const_int_operand" "n")))]
7620 "SIBLING_CALL_P (insn) && TARGET_CPU_ZARCH"
7622 [(set_attr "op_type" "RIL")
7623 (set_attr "type" "branch")])
7627 ; call instruction pattern(s).
7630 (define_expand "call"
7631 [(call (match_operand 0 "" "")
7632 (match_operand 1 "" ""))
7633 (use (match_operand 2 "" ""))]
7636 s390_emit_call (XEXP (operands[0], 0), NULL_RTX, NULL_RTX,
7637 gen_rtx_REG (Pmode, RETURN_REGNUM));
7641 (define_insn "*bras"
7642 [(call (mem:QI (match_operand 0 "bras_sym_operand" "X"))
7643 (match_operand 1 "const_int_operand" "n"))
7644 (clobber (match_operand 2 "register_operand" "=r"))]
7645 "!SIBLING_CALL_P (insn)
7646 && TARGET_SMALL_EXEC
7647 && GET_MODE (operands[2]) == Pmode"
7649 [(set_attr "op_type" "RI")
7650 (set_attr "type" "jsr")])
7652 (define_insn "*brasl"
7653 [(call (mem:QI (match_operand 0 "bras_sym_operand" "X"))
7654 (match_operand 1 "const_int_operand" "n"))
7655 (clobber (match_operand 2 "register_operand" "=r"))]
7656 "!SIBLING_CALL_P (insn)
7658 && GET_MODE (operands[2]) == Pmode"
7660 [(set_attr "op_type" "RIL")
7661 (set_attr "type" "jsr")])
7663 (define_insn "*basr"
7664 [(call (mem:QI (match_operand 0 "address_operand" "U"))
7665 (match_operand 1 "const_int_operand" "n"))
7666 (clobber (match_operand 2 "register_operand" "=r"))]
7667 "!SIBLING_CALL_P (insn) && GET_MODE (operands[2]) == Pmode"
7669 if (get_attr_op_type (insn) == OP_TYPE_RR)
7670 return "basr\t%2,%0";
7672 return "bas\t%2,%a0";
7674 [(set (attr "op_type")
7675 (if_then_else (match_operand 0 "register_operand" "")
7676 (const_string "RR") (const_string "RX")))
7677 (set_attr "type" "jsr")
7678 (set_attr "atype" "agen")])
7681 ; call_value instruction pattern(s).
7684 (define_expand "call_value"
7685 [(set (match_operand 0 "" "")
7686 (call (match_operand 1 "" "")
7687 (match_operand 2 "" "")))
7688 (use (match_operand 3 "" ""))]
7691 s390_emit_call (XEXP (operands[1], 0), NULL_RTX, operands[0],
7692 gen_rtx_REG (Pmode, RETURN_REGNUM));
7696 (define_insn "*bras_r"
7697 [(set (match_operand 0 "" "")
7698 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
7699 (match_operand:SI 2 "const_int_operand" "n")))
7700 (clobber (match_operand 3 "register_operand" "=r"))]
7701 "!SIBLING_CALL_P (insn)
7702 && TARGET_SMALL_EXEC
7703 && GET_MODE (operands[3]) == Pmode"
7705 [(set_attr "op_type" "RI")
7706 (set_attr "type" "jsr")])
7708 (define_insn "*brasl_r"
7709 [(set (match_operand 0 "" "")
7710 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
7711 (match_operand 2 "const_int_operand" "n")))
7712 (clobber (match_operand 3 "register_operand" "=r"))]
7713 "!SIBLING_CALL_P (insn)
7715 && GET_MODE (operands[3]) == Pmode"
7717 [(set_attr "op_type" "RIL")
7718 (set_attr "type" "jsr")])
7720 (define_insn "*basr_r"
7721 [(set (match_operand 0 "" "")
7722 (call (mem:QI (match_operand 1 "address_operand" "U"))
7723 (match_operand 2 "const_int_operand" "n")))
7724 (clobber (match_operand 3 "register_operand" "=r"))]
7725 "!SIBLING_CALL_P (insn) && GET_MODE (operands[3]) == Pmode"
7727 if (get_attr_op_type (insn) == OP_TYPE_RR)
7728 return "basr\t%3,%1";
7730 return "bas\t%3,%a1";
7732 [(set (attr "op_type")
7733 (if_then_else (match_operand 1 "register_operand" "")
7734 (const_string "RR") (const_string "RX")))
7735 (set_attr "type" "jsr")
7736 (set_attr "atype" "agen")])
7739 ;;- Thread-local storage support.
7742 (define_expand "get_tp_64"
7743 [(set (match_operand:DI 0 "nonimmediate_operand" "") (reg:DI 36))]
7747 (define_expand "get_tp_31"
7748 [(set (match_operand:SI 0 "nonimmediate_operand" "") (reg:SI 36))]
7752 (define_expand "set_tp_64"
7753 [(set (reg:DI 36) (match_operand:DI 0 "nonimmediate_operand" ""))
7754 (set (reg:DI 36) (unspec_volatile:DI [(reg:DI 36)] UNSPECV_SET_TP))]
7758 (define_expand "set_tp_31"
7759 [(set (reg:SI 36) (match_operand:SI 0 "nonimmediate_operand" ""))
7760 (set (reg:SI 36) (unspec_volatile:SI [(reg:SI 36)] UNSPECV_SET_TP))]
7764 (define_insn "*set_tp"
7765 [(set (reg 36) (unspec_volatile [(reg 36)] UNSPECV_SET_TP))]
7768 [(set_attr "type" "none")
7769 (set_attr "length" "0")])
7771 (define_insn "*tls_load_64"
7772 [(set (match_operand:DI 0 "register_operand" "=d")
7773 (unspec:DI [(match_operand:DI 1 "memory_operand" "m")
7774 (match_operand:DI 2 "" "")]
7778 [(set_attr "op_type" "RXE")])
7780 (define_insn "*tls_load_31"
7781 [(set (match_operand:SI 0 "register_operand" "=d,d")
7782 (unspec:SI [(match_operand:SI 1 "memory_operand" "R,T")
7783 (match_operand:SI 2 "" "")]
7789 [(set_attr "op_type" "RX,RXY")])
7791 (define_insn "*bras_tls"
7792 [(set (match_operand 0 "" "")
7793 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
7794 (match_operand 2 "const_int_operand" "n")))
7795 (clobber (match_operand 3 "register_operand" "=r"))
7796 (use (match_operand 4 "" ""))]
7797 "!SIBLING_CALL_P (insn)
7798 && TARGET_SMALL_EXEC
7799 && GET_MODE (operands[3]) == Pmode"
7801 [(set_attr "op_type" "RI")
7802 (set_attr "type" "jsr")])
7804 (define_insn "*brasl_tls"
7805 [(set (match_operand 0 "" "")
7806 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
7807 (match_operand 2 "const_int_operand" "n")))
7808 (clobber (match_operand 3 "register_operand" "=r"))
7809 (use (match_operand 4 "" ""))]
7810 "!SIBLING_CALL_P (insn)
7812 && GET_MODE (operands[3]) == Pmode"
7814 [(set_attr "op_type" "RIL")
7815 (set_attr "type" "jsr")])
7817 (define_insn "*basr_tls"
7818 [(set (match_operand 0 "" "")
7819 (call (mem:QI (match_operand 1 "address_operand" "U"))
7820 (match_operand 2 "const_int_operand" "n")))
7821 (clobber (match_operand 3 "register_operand" "=r"))
7822 (use (match_operand 4 "" ""))]
7823 "!SIBLING_CALL_P (insn) && GET_MODE (operands[3]) == Pmode"
7825 if (get_attr_op_type (insn) == OP_TYPE_RR)
7826 return "basr\t%3,%1%J4";
7828 return "bas\t%3,%a1%J4";
7830 [(set (attr "op_type")
7831 (if_then_else (match_operand 1 "register_operand" "")
7832 (const_string "RR") (const_string "RX")))
7833 (set_attr "type" "jsr")
7834 (set_attr "atype" "agen")])
7837 ;;- Miscellaneous instructions.
7841 ; allocate stack instruction pattern(s).
7844 (define_expand "allocate_stack"
7845 [(match_operand 0 "general_operand" "")
7846 (match_operand 1 "general_operand" "")]
7849 rtx temp = gen_reg_rtx (Pmode);
7851 emit_move_insn (temp, s390_back_chain_rtx ());
7852 anti_adjust_stack (operands[1]);
7853 emit_move_insn (s390_back_chain_rtx (), temp);
7855 emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
7861 ; setjmp instruction pattern.
7864 (define_expand "builtin_setjmp_receiver"
7865 [(match_operand 0 "" "")]
7868 emit_insn (s390_load_got ());
7869 emit_insn (gen_rtx_USE (VOIDmode, pic_offset_table_rtx));
7873 ;; These patterns say how to save and restore the stack pointer. We need not
7874 ;; save the stack pointer at function level since we are careful to
7875 ;; preserve the backchain. At block level, we have to restore the backchain
7876 ;; when we restore the stack pointer.
7878 ;; For nonlocal gotos, we must save both the stack pointer and its
7879 ;; backchain and restore both. Note that in the nonlocal case, the
7880 ;; save area is a memory location.
7882 (define_expand "save_stack_function"
7883 [(match_operand 0 "general_operand" "")
7884 (match_operand 1 "general_operand" "")]
7888 (define_expand "restore_stack_function"
7889 [(match_operand 0 "general_operand" "")
7890 (match_operand 1 "general_operand" "")]
7894 (define_expand "restore_stack_block"
7895 [(match_operand 0 "register_operand" "")
7896 (match_operand 1 "register_operand" "")]
7899 rtx temp = gen_reg_rtx (Pmode);
7901 emit_move_insn (temp, s390_back_chain_rtx ());
7902 emit_move_insn (operands[0], operands[1]);
7903 emit_move_insn (s390_back_chain_rtx (), temp);
7908 (define_expand "save_stack_nonlocal"
7909 [(match_operand 0 "memory_operand" "")
7910 (match_operand 1 "register_operand" "")]
7913 enum machine_mode mode = TARGET_64BIT ? OImode : TImode;
7914 rtx base = gen_rtx_REG (Pmode, BASE_REGNUM);
7916 /* Copy the backchain to the first word, sp to the second and the
7917 literal pool base to the third. */
7919 if (TARGET_BACKCHAIN)
7921 rtx temp = force_reg (Pmode, s390_back_chain_rtx ());
7922 emit_move_insn (operand_subword (operands[0], 0, 0, mode), temp);
7925 emit_move_insn (operand_subword (operands[0], 1, 0, mode), operands[1]);
7926 emit_move_insn (operand_subword (operands[0], 2, 0, mode), base);
7931 (define_expand "restore_stack_nonlocal"
7932 [(match_operand 0 "register_operand" "")
7933 (match_operand 1 "memory_operand" "")]
7936 enum machine_mode mode = TARGET_64BIT ? OImode : TImode;
7937 rtx base = gen_rtx_REG (Pmode, BASE_REGNUM);
7938 rtx temp = NULL_RTX;
7940 /* Restore the backchain from the first word, sp from the second and the
7941 literal pool base from the third. */
7943 if (TARGET_BACKCHAIN)
7944 temp = force_reg (Pmode, operand_subword (operands[1], 0, 0, mode));
7946 emit_move_insn (base, operand_subword (operands[1], 2, 0, mode));
7947 emit_move_insn (operands[0], operand_subword (operands[1], 1, 0, mode));
7950 emit_move_insn (s390_back_chain_rtx (), temp);
7952 emit_insn (gen_rtx_USE (VOIDmode, base));
7958 ; nop instruction pattern(s).
7965 [(set_attr "op_type" "RR")])
7969 ; Special literal pool access instruction pattern(s).
7972 (define_insn "*pool_entry"
7973 [(unspec_volatile [(match_operand 0 "consttable_operand" "X")]
7974 UNSPECV_POOL_ENTRY)]
7977 enum machine_mode mode = GET_MODE (PATTERN (insn));
7978 unsigned int align = GET_MODE_BITSIZE (mode);
7979 s390_output_pool_entry (operands[0], mode, align);
7982 [(set (attr "length")
7983 (symbol_ref "GET_MODE_SIZE (GET_MODE (PATTERN (insn)))"))])
7985 (define_insn "pool_align"
7986 [(unspec_volatile [(match_operand 0 "const_int_operand" "n")]
7987 UNSPECV_POOL_ALIGN)]
7990 [(set (attr "length") (symbol_ref "INTVAL (operands[0])"))])
7992 (define_insn "pool_section_start"
7993 [(unspec_volatile [(const_int 1)] UNSPECV_POOL_SECTION)]
7996 [(set_attr "length" "0")])
7998 (define_insn "pool_section_end"
7999 [(unspec_volatile [(const_int 0)] UNSPECV_POOL_SECTION)]
8002 [(set_attr "length" "0")])
8004 (define_insn "main_base_31_small"
8005 [(set (match_operand 0 "register_operand" "=a")
8006 (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE))]
8007 "!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
8009 [(set_attr "op_type" "RR")
8010 (set_attr "type" "la")])
8012 (define_insn "main_base_31_large"
8013 [(set (match_operand 0 "register_operand" "=a")
8014 (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE))
8015 (set (pc) (label_ref (match_operand 2 "" "")))]
8016 "!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
8018 [(set_attr "op_type" "RI")])
8020 (define_insn "main_base_64"
8021 [(set (match_operand 0 "register_operand" "=a")
8022 (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE))]
8023 "TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
8025 [(set_attr "op_type" "RIL")
8026 (set_attr "type" "larl")])
8028 (define_insn "main_pool"
8029 [(set (match_operand 0 "register_operand" "=a")
8030 (unspec_volatile [(const_int 0)] UNSPECV_MAIN_POOL))]
8031 "GET_MODE (operands[0]) == Pmode"
8034 (if_then_else (ne (symbol_ref "TARGET_CPU_ZARCH") (const_int 0))
8035 (const_string "larl") (const_string "la")))])
8037 (define_insn "reload_base_31"
8038 [(set (match_operand 0 "register_operand" "=a")
8039 (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_RELOAD_BASE))]
8040 "!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
8041 "basr\t%0,0\;la\t%0,%1-.(%0)"
8042 [(set_attr "length" "6")
8043 (set_attr "type" "la")])
8045 (define_insn "reload_base_64"
8046 [(set (match_operand 0 "register_operand" "=a")
8047 (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_RELOAD_BASE))]
8048 "TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
8050 [(set_attr "op_type" "RIL")
8051 (set_attr "type" "larl")])
8054 [(unspec_volatile [(match_operand 0 "const_int_operand" "n")] UNSPECV_POOL)]
8057 [(set (attr "length") (symbol_ref "INTVAL (operands[0])"))])
8060 ;; Insns related to generating the function prologue and epilogue.
8064 (define_expand "prologue"
8065 [(use (const_int 0))]
8067 "s390_emit_prologue (); DONE;")
8069 (define_insn "prologue_tpf"
8070 [(unspec_volatile [(const_int 0)] UNSPECV_TPF_PROLOGUE)
8071 (clobber (reg:DI 1))]
8072 "TARGET_TPF_PROFILING"
8073 "larl\t%%r1,.+14\;tm\t4065,255\;bnz\t4064"
8074 [(set_attr "length" "14")])
8076 (define_expand "epilogue"
8077 [(use (const_int 1))]
8079 "s390_emit_epilogue (false); DONE;")
8081 (define_insn "epilogue_tpf"
8082 [(unspec_volatile [(const_int 0)] UNSPECV_TPF_EPILOGUE)
8083 (clobber (reg:DI 1))]
8084 "TARGET_TPF_PROFILING"
8085 "larl\t%%r1,.+14\;tm\t4071,255\;bnz\t4070"
8086 [(set_attr "length" "14")])
8088 (define_expand "sibcall_epilogue"
8089 [(use (const_int 0))]
8091 "s390_emit_epilogue (true); DONE;")
8093 (define_insn "*return"
8095 (use (match_operand 0 "register_operand" "a"))]
8096 "GET_MODE (operands[0]) == Pmode"
8098 [(set_attr "op_type" "RR")
8099 (set_attr "type" "jsr")
8100 (set_attr "atype" "agen")])
8103 ;; Instruction definition to extend a 31-bit pointer into a 64-bit
8104 ;; pointer. This is used for compatibility.
8106 (define_expand "ptr_extend"
8107 [(set (match_operand:DI 0 "register_operand" "=r")
8108 (match_operand:SI 1 "register_operand" "r"))]
8111 emit_insn (gen_anddi3 (operands[0],
8112 gen_lowpart (DImode, operands[1]),
8113 GEN_INT (0x7fffffff)));
8117 ;; Instruction definition to expand eh_return macro to support
8118 ;; swapping in special linkage return addresses.
8120 (define_expand "eh_return"
8121 [(use (match_operand 0 "register_operand" ""))]
8124 s390_emit_tpf_eh_return (operands[0]);